From 1a00cc7d944c0504ce3db71235777f8dc98b65d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mia=20Pilchov=C3=A1?= Date: Sat, 15 Feb 2025 17:21:59 +0100 Subject: [PATCH] u-boot: update version /home/liliana/Dingussy/local/releases/tt1467818 --- CHANGELOG | 39683 ++-------------- CREDITS | 99 +- MAINTAINERS | 692 +- MAKEALL | 754 +- Makefile | 2638 +- README | 1196 +- arm_config.mk | 2 +- blackfin_config.mk | 17 +- board/AtmarkTechno/suzaku/Makefile | 20 +- board/AtmarkTechno/suzaku/suzaku.c | 2 +- board/AtmarkTechno/suzaku/u-boot.lds | 3 +- board/BuS/EB+MCF-EV123/EB+MCF-EV123.c | 74 +- board/BuS/EB+MCF-EV123/Makefile | 20 +- board/BuS/EB+MCF-EV123/VCxK.c | 2 +- board/BuS/EB+MCF-EV123/VCxK.h | 16 +- board/BuS/EB+MCF-EV123/cfm_flash.c | 4 +- board/BuS/EB+MCF-EV123/config.mk | 2 +- board/BuS/EB+MCF-EV123/flash.c | 4 +- board/BuS/EB+MCF-EV123/textbase.mk | 2 +- board/BuS/EB+MCF-EV123/u-boot.lds | 11 +- board/LEOX/elpt860/Makefile | 21 +- board/LEOX/elpt860/elpt860.c | 4 +- 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create mode 100644 post/cpu/twox.c create mode 100644 post/dsp.c create mode 100644 post/ether.c create mode 100644 post/i2c.c create mode 100644 post/memory.c create mode 100644 post/rtc.c create mode 100644 post/spr.c create mode 100644 post/sysmon.c create mode 100644 post/uart.c create mode 100644 post/usb.c create mode 100644 post/watchdog.c create mode 100644 rtc/Makefile create mode 100644 rtc/bf533_rtc.c create mode 100644 rtc/date.c create mode 100644 rtc/ds12887.c create mode 100644 rtc/ds1302.c create mode 100644 rtc/ds1306.c create mode 100644 rtc/ds1307.c create mode 100644 rtc/ds1337.c create mode 100644 rtc/ds1374.c create mode 100644 rtc/ds1556.c create mode 100644 rtc/ds164x.c create mode 100644 rtc/ds174x.c create mode 100644 rtc/m41t11.c create mode 100644 rtc/m48t35ax.c create mode 100644 rtc/max6900.c create mode 100644 rtc/mc146818.c create mode 100644 rtc/mk48t59.c create mode 100644 rtc/mpc5xxx.c create mode 100644 rtc/mpc8xx.c create mode 100644 rtc/pcf8563.c create mode 100644 rtc/rs5c372.c create mode 100644 rtc/s3c24x0_rtc.c diff --git a/CHANGELOG b/CHANGELOG index aa1bdc31f..e39b1e751 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,37023 +1,5344 @@ -commit 17e900b8c0f38d922da47073246219dce2a847f2 -Author: Wolfgang Denk -Date: Tue Aug 12 14:54:04 2008 +0200 +====================================================================== +Changes since U-Boot 1.1.4: +====================================================================== - MVBC_P: fix compile problem +* Prevent USB commands from working when USB is stopped. - Signed-off-by: Wolfgang Denk +* Add rudimentary handling of alternate settings of USB interfaces. + This is in order to fix issues with some USB sticks timing out + during initialization. Some code readability improvements. -commit 52b047ae48219b59bebe37ba743ab103fd4f8316 -Author: Wolfgang Denk -Date: Tue Aug 12 12:10:11 2008 +0200 +* PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance + AMCC suggested to set the PMU bit to 0 for best performace on + the PPC440 DDR controller. + Please see doc/README.440-DDR-performance for details. + Patch by Stefan Roese, 28 Jul 2006 - MPC8272ADS: fix build error: 'bd_t' has no member named 'pci_clk' +* AMCC bamboo (440EP) U-Boot image reduced to 384kbyte + Please see doc/README.bamboo for details. + Patch by Stefan Roese, 27 Jul 2006 - Signed-off-by: Wolfgang Denk +* Fix CONFIG_CMDLINE_EDITING implementation + Patch by Stefan Roese, 27 Jul 2006 -commit c9c101c660b3d1995045c61c7c6041f52b6cf335 -Author: Wolfgang Denk -Date: Tue Aug 12 00:36:53 2008 +0200 +* Fix preboot message on TQM5200 after switching to hush parser. - ads5121: fix compiler warnings (unused variables) +* MCC200: set default configuration to low_boot DDR, + and support for configurable options high_boot and/or SDRAM. + +* Add support for 256 MB SDRAM on CPU87 + Patch by Josef Wagner, 25 Nov 2005 - Signed-off-by: Wolfgang Denk +* Add configuration for cam5200 board (based on TQM5200S). -commit 902ca09246039964d59bbcb519b1e1b5aed01308 -Author: Kumar Gala -Date: Mon Aug 11 11:29:28 2008 -0500 +* More code cleanup - 85xx: Rename CONFIG_NR_CPUS to CONFIG_NUM_CPUS +* Disabled kvme080 board in MAKEALL because of build problems. + +* Code cleanup - Use CONFIG_NUM_CPUS to match existing define used by 86xx. +* Update NetStar board + Patch by Ladislav Michl, 03 Nov 2005 - Signed-off-by: Kumar Gala - Acked-by: Jon Loeliger +* Make code better readable. + Patch by Ladislav Michl, 14 Sep 2005 -commit 3216ca9692ff80d7c638723ef448f3d36301d9e7 -Author: Kumar Gala -Date: Mon Aug 11 09:20:53 2008 -0500 +* Enable initrd ATAG for xm250 board. + Patch by Josef Wagner, 05 Sep 2005 - Fix fallout from autostart revert +* Add readline cmdline-editing extension + Patch by JinHua Luo, 01 Sep 2005 - The autostart revert caused a bit of duplicated code as well as - code that was using images->autostart that needs to get removed so - we can build again. +* Add support for friendly-arm SBC-2410X board + Patch by JinHua Luo, 01 Sep 2005 - Signed-off-by: Kumar Gala +* Fix multi-part image support on i386 platform. + Patch by David Updegraff, 19 Aug 2005 -commit 3cf8a234b8e8c02e4da1f23566043bc288b05220 -Author: Kumar Gala -Date: Mon Aug 11 09:16:25 2008 -0500 +* Add support for KVME080 board + Patch by Sangmoon Kim, 18 Aug 2005 - Fix compile error related to r8a66597-hcd & usb +* Fix MIPS LE build problem + Patch by Matej Kupljen, 10 Aug 2005 - When building the 8544DS board we get this error: +* Check argument count in "mii" command. + Problem pointed out by Andrew Dyer, 13 Jun 2005 - In file included from r8a66597-hcd.c:22: - u-boot/include/usb.h:190:2: error: #error USB Lowlevel not defined - make[1]: *** [r8a66597-hcd.o] Error 1 +* Cleanup TQM5200 board configurations: + - make highboot configurations use environment at high end, too, + to avoid flash fragmentation + - always use redundand environment + - don't enable video code for modules without graphics controller + - provide useful (though different) mtdparts settings + - get rid of CONFIG_CS_AUTOCONF which was always set anyway - The cleanest fix is to only build r8a66597-hcd.c if CONFIG_USB_R8A66597_HCD - is set. +* Extend mkconfig tool to print more useful target name - Signed-off-by: Kumar Gala +* Add support for high-boot on TQM5200 and TQM5200S boards. + Hint: the CPLD on the TQM5200 must be programmed with a software + version supporting the high boot option! The new TQM5200S is + already supporting this option. On the TQM5200 this option will be + supported in configurations with MPC5200 rev B processors. + To actually "high boot", set jumper X30 on the STK52xx. + Patch by Martin Krause, 12 Jul 2006 -commit 2d0daa03612338a813e3c9d22680e54eabfea378 -Author: Becky Bruce -Date: Mon Aug 4 14:02:26 2008 -0500 +* Add support for new TQM5200 revisions + - Support for TQM5200S (short version without graphic controller) + - Support for modules with 'N' type S29GL128N Spansion flashes + (requires changes to flash layout) + - Support for MPC5200B cpu (mostly support for second SDRAM bank) + Patch by Martin Krause, 07 Jul 2006 - POWERPC 86xx: Move BAT setup code to C +* Fix support for PS/2 keyboard on TQM85xx boards + The PS/2 keyobard driver for the TQM85xx modules only supports the + internal DUART of the MPC85xx CPU. Since the MPC8560 doesn't + include a DUART, the TQM8560 modules can't be used with the PS/2 + keyboard controller on the STK85xx board. + The PS/2 keyboard driver should work with the modules TQM8540, + TQM8541 and TQM8555, but it only has been tested on a TQM8540, yet. + Make sure the PS/2 controller on the STK85xx is programmed. Jumper + settings: X66 1-2, 9-10; X61 2-3 + Patch by Martin Krause, 21 Jun 2006 - This is needed because we will be possibly be locating - devices at physical addresses above 32bits, and the asm - preprocessing does not appear to deal with ULL constants - properly. We now call write_bat in lib_ppc/bat_rw.c. +* Adjust RTC century handling on STK52xx board to match Linux driver. + Patch by Martin Krause, 12 Jun 2006 - Signed-off-by: Becky Bruce - Acked-by: Jon Loeliger +* Adjust filenames for USB update images on TRAB board. + During an automatic update via USB stick, U-Boot searches for + images with the name "firmware.img" and "kernel.img". This names + are now changed to "firmw_01.img" and "kernl_01.img". This is done, + to prevent updates of new boards (with the new macronics "c" step + flashes) with old, incompatible firmware or kernel versions. + Patch by Martin Krause, 21 Jun 2006 -commit 9de67149db576c91b9c2a0a182652331e7e44211 -Author: Becky Bruce -Date: Mon Aug 4 14:01:53 2008 -0500 +* Bugfix in VFD routine on TRAB board. + Make sure upper lext pixel can be set to blue, too + (so far only red was possible). + Patch by Martin Krause, 15 Feb 2006 - POWERPC: Add synchronization to write_bat in lib_ppc/bat_rw.c +* Enable buffered flash writes for TB5200 board. - Perform sync/isync as required by the architecture. +* Fix some bugs in TRAB board flash driver. + - increase CFG_FLASH_ERASE_TOUT from 2 to 15 seconds + - use CFG_FLASH_WRITE_TOUT for programming instead of CFG_FLASH_ERASE_TOUT + - remove "Unlock Bypass" mode, because macronix flashes do not support + this mode officially + - fix flash reset command from 0x00FF to 0x00F0. 0x00FF is only specified + for Intel compatible flashes, not for AMD compatible. + Patch by Martin Krause, 15 Feb 2006 - Signed-off-by: Becky Bruce - Acked-by: Jon Loeliger +* Add additional error messages to flash driver on TRAB board + (for erase errors and timeout errors) + Patch by Martin Krause, 14 Feb 2006 -commit 23f935c073e7578c6066804fd2f9ee116cae6ffe -Author: Becky Bruce -Date: Mon Aug 4 14:01:16 2008 -0500 +* Add support for TB5200 board + The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module + integrated in a little aluminium case. + Patch by Martin Krause, 8 Jun 2006 - POWERPC: 86xx - add missing CONFIG_HIGH_BATS to sbc8641d config +* Enable buffered flash writes for TQM5200 board. - Signed-off-by: Becky Bruce - Acked-by: Jon Loeliger +* Fix problems with SanDisk Corporation Cruzer Micro USB memory stick. -commit 5276a3584d26a9533404f0ec00c3b61cf9a97939 -Author: Magnus Lilja -Date: Sun Aug 3 21:44:10 2008 +0200 +* Add support for TQM885D board. + Patch by Martin Krause, 20 Mar 2006 - i.MX31: Fix mx31_gpio_mux() function and MUX_-macros. +* Fix FEC initialisation: All MII configuration is done via FEC1 + registers, but MII_SPEED was configured according to FEC used. So + if only FEC2 was used, this caused the real MII_SPEED register in + FEC1 to stay uninitalised, leqading to "mii_send STUCK!" messages. + Fix: always configure MII_SPEED on FEC1 only. + Patch by Markus Klotzbuecher, 12 Jul 2006 + +* Add support for SPC1920 board. + Patch by Markus Klotzbuecher, 12 Jul 2006 + +* MCC200 board: support console on any one of the Quad UART ports. + +* Fix error in flash protection calculation on MCC200 board. + +* Major PCMCIA Cleanup to make code better readable and maintainable. + Notes: + - Board-dependend code for RPXLITE and RPXCLASSIC-based boards + placed to the drivers/rpx_pmcia.c file to avoid duplication. + Same for TQM8xx-based boards (drivers/tqm8xx_pmcia.c). + - drivers/i82365.c has been split into two parts located at + board/atc/ti113x.c and board/cpc45/pd67290.c (ATC and CPC45 are + the only boards using CONFIG_82365). + - Changes were tested for clean build and *very* *few* boards. + +* Fix timer problems on AMCC yucca board. + Set Timer Clock Select to use CPU clock as a timer input source. + +* Bring yucca config more in line with other AMCC boards. - Correct the mx31_gpio_mux() function to allow changing all i.MX31 IOMUX - contacts instead of only the first 256 ones as is the case prior to - this patch. +* Add AMCC bamboo board to MAKEALL build script. - Add missing MUX_* macros and update board files to use the new macros. +* Fix AMCC bamboo eval board compilation errors. + +* Add system memory to the PCI region list for AMCC PPC44x CPUs. + Enabled it for Yucca board. - Signed-off-by: Magnus Lilja +* Cleanup config file and bootup output for Yucca board. -commit b6b183c5b2fffd4c456b7e3fcb064cceb47fe7ac -Author: Magnus Lilja -Date: Sun Aug 3 21:43:37 2008 +0200 +* Fix CONFIG_440_GX define usage. - i.MX31: Fix IOMUX related typos +* Remove autogenerated bmp_logo.h file. - Correct the names of some IOMUX macros. +* Add support for AMCC 440SPe CPU based eval board (Yucca). - Signed-off-by: Magnus Lilja +* Call serial_initialize() before first debug() is used. -commit 4d57b0fb2927d4f50d834884b4ec4a7ca01708b0 -Author: Steve Sakoman -Date: Mon Aug 11 20:26:16 2008 +0200 +* Cleanup trab board for GCC-4.x - OneNAND: Remove unused parameters to onenand_verify_page +* VoiceBlue update: use new MTD flash partitioning methods, use more + reasonable TEXT_BASE, update default environment and enable keyed + autoboot. + Patch by Ladislav Michl, 16. Aug 2005 - The block and page parameters of onenand_verify_page() are not used. This causes a compiler error when CONFIG_MTD_ONENAND_VERIFY_WRITE is enabled. +* Add forgotten changes for the PLEB 2 Board. + Patch by David Snowdon, 13. Aug 2005 - Signed-off-by: Steve Sakoman - Signed-off-by: Dirk Behme +* Add support for wrPPMC7xx/74xx boards + Patch by Richard Danter, 12 Aug 2005 -commit e84d568fa2a9f4ce7888141e71676368ef6b3f25 -Author: Anatolij Gustschin -Date: Fri Aug 8 18:00:40 2008 +0200 +* Add support for gth2 board + Patch by Thomas Lange, Aug 11 2005 - video: fix bug in cfb_console code +* Add support for CONFIG_SERIAL_MULTI on MPC5xxx + Patch by Martin Krause, 8 Jun 2006 - FILL_15BIT_555RGB macro extension for pixel swapping - by commit bed53753dd1d7e6bcbea4339be0fb7760214cc35 - introduced a bug in cfb_console: + This patch supports two serial consoles on boards with + a MPC5xxx CPU. The console can be switched at runtime + by setting stdin, stdout and stderr to the desired serial + interface (serial0 or serial1). The PSCs to be used as + console port are definded by CONFIG_PSC_CONSOLE + and CONFIG_PSC_CONSOLE2. + See README.serial_multi for details. - Bitmaps with odd-numbered width won't be rendered - correctly and even U-Boot crashes are observed on - some platforms while repeated rendering of such - bitmaps with "bmp display". Also if a bitmap is - rendered to an odd-numbered x starting position, - the same problem occurs. This patch is an attempt - to fix it. +* Bugfix in I2C initialisation on S3C2400. + If the bus is blocked because of a previously interrupted + transfer, up to eleven clocks are generated on the I2CSCL + line to complete the transfer and to free the bus. + With this fix pin I2CSCL (PG6) is really configured as GPIO + so the clock pulses are really generated. + Patch by Martin Krause, 04 Apr 2006 - Signed-off-by: Anatolij Gustschin +* Fix DDR6 errata on TQM834x boards + Patch by Thomas Waehner, 07 Mar 2006 -commit d9015f6a50d7258125349ef5c2af836458a0029a -Author: Anatolij Gustschin -Date: Fri Aug 8 18:00:39 2008 +0200 +* Remove obsolete flash driver board/tqm5200/flash.c + Patch by Martin Krause, 11 Jan 2006 - video: fix bug in logo_plot +* Update configuration for CMC-PU2 board + Patch by Martin Krause, 17 Nov 2005 - If logo_plot() should ever be called with x starting - position other than zero and for pixel depths greater - than 8bpp, logo colors distortion will be observed. - This patch fixes the issue. +* Add support for PS/2 keyboard on TQM85xx board + Patch by Martin Krause, 07 Nov 2005 - Signed-off-by: Anatolij Gustschin + Tested on a STK85XX baseboard. Make sure the PS/2 controller + has been programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3 -commit 406819ae94f79f5b59e01d163380ca7d83709251 -Author: Wolfgang Denk -Date: Mon Aug 11 00:17:52 2008 +0200 +* Fix TRAB channel switching delay for trab_fkt.bin standalone applikation + In tsc2000_read_channel() the delay after setting the multiplexer + to a temperature channel is increased from 1,5 ms to 10 ms. This + is to allow the multiplexer inputs to stabilize after huge steps + of the input signal level. + Patch by Martin Krause, 08 Nov 2005 - MAINTAINERS: sort entries +* Adjust TQM5200 make targets + Make the automatic CS configuration the default. + The dedicated configurations CONFIG_TQM5200_AA, CONFIG_TQM5200_AB + and CONFIG_TQM5200_AC are removed. + "TQM5200_config" is now the default for STK52XX.200 base boards. + On a STK52XX.100 base board "TQM5200_STK100_config" must be used. + Patch by Martin Krause, 07 Nov 2005 - Signed-off-by: Wolfgang Denk +* Fix setting of environment variable "ver" on trab board + The environment variable "ver" is now set before + do_auto_update() is called, so that "ver" can be used + in USB update scripts. + Patch by Martin Krause, 27 Oct 2005 -commit cfc442d7913d4d1c3a9bf494f90c012c2f8c3bdc -Author: Roy Zang -Date: Thu Aug 7 18:19:28 2008 +0800 +* Fix wrong usage of udelay() in led_blink() on trab board + Patch by Martin Krause, 27 Oct 2005 - Add mpc7448hpc2 maintainer information +* Fix udelay bug in vfd.c for trab board + Patch by Martin Krause, 27 Oct 2005 - Signed-off-by: Roy Zang +* Disable JFFS2 support for trab board + Patch by Martin Krause, 27 Oct 2005 -commit a9fe0c3e7ca48afa50d6a0db99fa91e7282d73d8 -Author: Gururaja Hebbar K R -Date: Thu Aug 7 13:13:27 2008 +0530 +* Change mtdparts definition on trab board to match current flash map + Patch by Martin Krause, 27 Oct 2005 - common/cmd_load.c - Minor code & Coding Style cleanup +* Fix memory init problems on MCC200 board - - os_data_header Variable is a carry over feature - & unused. So removed all instance of this variable - - Minor Code Style Update +* Fix IxEthDB.h to compile again + Patch by Stefan Roese, 14 Jun 2006 - Signed-off-by: Gururaja Hebbar - Acked-by: Jean-Christophe PLAGNIOL-VILLARD +* Minor cleanup for PCS440EP board + Patch by Stefan Roese, 13 Jun 2006 -commit 0d28f34bbe56d0971bd603789dcc6fe7adf11f14 -Author: Magnus Lilja -Date: Wed Aug 6 19:32:33 2008 +0200 +* Add MCF5282 support (without preloader) + relocate ichache_State to ram + u-boot can run from internal flash + Add EB+MCF-EV123 board support. + Add m68k Boards to MAKEALL + Patch from Jens Scharsig, 08 Aug 2005 - Update the U-Boot wiki URL. +* Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards + Patch by Scott McNutt, 08 Jun 2006 - Signed-off-by: Magnus Lilja +* Nios II - Add EPCS Controller bootrom work-around + -When booting from an epcs controller, the epcs bootrom may leave the + slave select in an asserted state causing soft reset hang. This + patch ensures slave select is negated at reset. + Patch by Scott McNutt, 08 Jun 2006 -commit aa5ffa16d7e4c461b7b77bf8e79d2ef5638cf754 -Author: dirk.behme@googlemail.com -Date: Sun Aug 10 17:56:36 2008 +0200 +* Update PK1C20 board + -Update base addresses for standard configuration + -Eliminate use of CACHE_BYPASS in board code + Patch by Scott McNutt, 08 Jun 2006 - OneNAND: Remove base address offset usage +* Nios II - Fix I/O Macros and mini-app stubs + -Fix asm/io.h macros + -Eliminate use of CACHE_BYPASS in cpu code + -Eliminate assembler warnings + -Fix mini-app stubs and force no small data + Patch by Scott McNutt, 08 Jun 2006 - While locally preparing some U-Boot patches for ARM based OMAP3 boards, some - using OneNAND and some using NAND, we found some differences in OneNAND and - NAND command address handling. +* Fix U-Boot environment sector protection on MCC200 board - As this might confuse users (it already confused us), we like to align OneNAND - and NAND address handling. +* Minor cleanup for PCS440EP board - The issue is that cmd_onenand.c subtracts the onenand base address from the - addresses you type into the u-boot command line so, unlike nand, you can't - use addresses relative to the start of the onenand part e.g. this won't work: +* Update PCS440EP port to fit into one flash device (incl. environment) + Patch by Stefan Roese, 06 Jun 2006 - onenand read 82000000 280000 400000 +* Add support for PCS440EP board + Patch by Stefan Roese, 02 Jun 2006 - you have to use: +* Fix examples/Makefile; some build targets were lost - onenand read 82000000 20280000 400000 +* Fix watchdog handling in CFI flash driver + Just use udelay() when waiting for status changes which will + implicitely trigger the watchdog. - Looking at recent git, the only board currently using OneNAND is Apollon, and - for this the OneNAND base address is 0 (apollon.h) +* Fix PCI to memory window size problems on PM82x boards + We use the "automatic" mode that was used for the MPC8266ADS and + MPC8272 boards. Eventually this should be used on all boards?] + Patch by Wolfgang Grandegger, 17 Jan 2006 - #define CFG_ONENAND_BASE 0x00000000 +* Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone + Patch by Stefan Roese, 29 May 2006 - so patch below won't break any existing boards and will align OneNAND and NAND - handling on boards where OneNAND base address is != 0. +* Update Intel IXP4xx support + - Add IXP4xx NPE ethernet MAC support + - Add support for Intel IXDPG425 board + - Add support for Prodrive PDNB3 board + - Add IRQ support + Patch by Stefan Roese, 23 May 2006 - Signed-off-by: Steve Sakoman - Signed-off-by: Manikandan Pillai - Signed-off-by: Dirk Behme +* Fix problem in PVR detection for 440GR + Patch by Stefan Roese, 18 May 2006 -commit c11528083ef6e55e76df742228c26e39d151813d -Author: Kumar Gala -Date: Thu Aug 7 09:28:20 2008 -0500 +* Fix gcc 3.4.x AFLAGS setting for m68k platform. - mpc85xx: workaround old binutils bug +* Enable autoboot for M5271EVB board. - The recent change to move the .bss outside of the image gives older - binutils (ld from eldk4.1/binutils-2.16) some headache: +* Changed default ramdisk addr in yosemite/yellowstone ports + Patch by Stefan Roese, 15 May 2006 - ppc_85xx-ld: u-boot: Not enough room for program headers (allocated 3, need 4) - ppc_85xx-ld: final link failed: Bad value +* Fix PCMCIA support on virtlab2 - We workaround it by being explicit about the program headers and not - assigning the .bss to a program header. +* Add support for VirtLab2 board + (needed because of differences in the PCMCIA hardware). - Signed-off-by: Kumar Gala +* Minor cleanup. -commit 0bf202ec586d4466c900e987720fa635c594d689 -Author: Wolfgang Denk -Date: Sun Aug 10 01:26:26 2008 +0200 +* Update yosemite configuration to enable flash write buffer support + Patch by Stefan Roese, 10 May 2006 - Revert "[new uImage] Add autostart flag to bootm_headers structure" +* Fix compile warnings in common/xyzModem.c + Patch by Stefan Roese, 10 May 2006 - This reverts commit f5614e7926863bf0225ec860d9b319741a9c4004. +* Add support for AMCC 440EP Rev C and 440GR Rev B + Patch by John Otken, 08 May 2006 - The commit was based on a misunderstanding of the (documented) - meaning of the 'autostart' environment variable. It might cause - boards to hang if 'autostart' was used, with the potential to brick - them. Go back to the documented behaviour. +* OMAP 5912/OSK: update EMIFS CS1 timings: + Problems have been seen in the linux kernel's smc91x network driver + due to improper bus timings. The latest 2.6 OMAP kernels currently + have a workaround, but this fix belongs in u-boot. + Patch by Kevin Hilman, 13 Oct 2005 - Conflicts: +* Fix REG_MPU_LOAD_TIMER definition in multiple OMAP ports + Patch by Hiroki Kaminaga, 11 Mar 2006 - common/cmd_bootm.c - common/image.c - include/image.h +* Update omap5912osk board support + - Fix OMAP support that omap5912osk compiles in current source tree + - Update with code from "http://omap.spectrumdigital.com/osk5912" + to fix problems with DDR initialization + - Fix timer setup + - Use CFI flash driver and support complete 32MB of onboard flash + - Add "print_cpuinfo()" and "checkboard()" functions to display + CPU (with frequency) and Board infos + Patch by Stefan Roese, 10 May 2006 - Signed-off-by: Wolfgang Denk +* Fix watchdog issues for ColdFire boards. -commit 29f8f58ff40c67f7f2e11afd1715173094e52ac2 -Author: Wolfgang Denk -Date: Sat Aug 9 23:17:32 2008 +0200 +* Add M5271EVB board support. - TQM8xx{L,M}: try to normalize config files for TQM8xx? based board +* Make R5200 specific low level initialization board conditional. - - enable CFI driver where this was forgotten - - enable mtdparts support - - adjust default environment - etc. +* Update CPU target identification strings for ColdFire family. - Signed-off-by: Wolfgang Denk +* Update register definitions for MCF5271. -commit 41266c9b5a5f873df3ec891bb0907616958b5602 -Author: Peter Tyser -Date: Tue Aug 5 10:51:57 2008 -0500 +* Fix serial console support for MCF5271. - FIT: Fix handling of images without ramdisks +* Fixes for gcc 3.4 based m68k toolchain, + based on patch by Jate Sujjavanich. - boot_get_ramdisk() should not treat the case when a FIT image does - not contain a ramdisk as an error. +* Fix lowboot support on MCC200 board - Signed-off-by: Peter Tyser - Acked-by: Michal Simek +* Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port: + - Removed MPC8349ADS port + - Added PCI support to MPC8349ADS + - reworked memory map to allow mapping of all regions with BATs + Patch by Kumar Gala, 20 Apr 2006 -commit f77d92a3f56d88e63cc02226a1204b3bdbac6961 -Author: Sergey Lapin -Date: Sat Aug 9 01:39:09 2008 +0400 +* Coding Style cleanup - DataFlash: AT45DB021 fix and AT45DB081 support +* Write RTC seconds first to maintain settings integrity per + Maxim/Dallas DS1306 data sheet. + Patch by Alan J. Luse, 02 May 2006 - Fix for page size of AT45DB021. Also adding bigger AT45DB081 - which comes with some newer boards. +* Scheduled for removal: strnicmp() which is unused - Signed-off-by: Sergey Lapin +* Update for Intel Monahans boards: + - support for magic key detection and handling on delta board + - NAND support for zylonite board + some minor cleanup -commit ba9324451b662dd393afa53e5cc36fc5d3d10966 -Author: Nobuhiro Iwamatsu -Date: Fri Aug 8 16:30:23 2008 +0900 +* Declare load_serial_ymodem() when using CFG_CMD_LOADB. + Patch by Jon Loeliger, 01 May 2006 - sh: Update sh7763rdp config +* Fixed handling of bad checksums with "mkimage -l" - Add sh_eth support to sh7763rdp. +* Added support for BC3450 board + Patch by Stefan Strobl, 21 Oct 2005 - Signed-off-by: Nobuhiro Iwamatsu +* Update for NC650 board: + - Support rev1 and rev2 hardware + - adapt to new NAND layer + - add CP850 configuration based on NC650 -commit 21f971ec265f6042ec21636d55d06a6bc0751077 -Author: Wolfgang Denk -Date: Mon Jul 7 01:22:29 2008 +0200 +* MPC5200: enable snooping of DMA transactions on XLB even if no PCI + is configured; othrwise DMA accesses aren't cache coherent which + causes for example USB to fail. - TQM823L: re-enable logo support; update LCD_INFO text +* Some code cleanup - Signed-off-by: Wolfgang Denk +* Fix dbau1x00 boards broken by dbau1550 patch + PLL:s were not set for boards other than 1550. + Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST. + Default boot is now bootp for cards other than 1550. + Patch by Thomas Lange, 10 Aug 2005 -commit 3b8d17f0f082073346c0df017c9dfd6acdb40d6d -Author: Wolfgang Denk -Date: Fri Aug 8 16:41:56 2008 +0200 +* Fixes common/cmd_flash.c: + - fix some compiler/parser error, if using m68k tool chain + - optical fix for protect on/off all messages, if using more + then one bank + Patch by Jens Scharsig, 28 Jul 2005 - TQM8xxL: fix support for second flash bank +* Fix Quad UART mapping on MCC200 board due to new HW revision - When switching the TQM8xxL modules to use the CFI flash driver, - support for the second flash bank was broken because the CFI driver - did not support dynamically sized banks. This gets fixed now. +* Fix JFFS2 support for legacy NAND driver. - Signed-off-by: Wolfgang Denk +* Remove dependencies between DoC code and old legacy NAND driver. -commit 2a112b234d879f6390503a5f4e38246acce9d0b0 -Author: Wolfgang Denk -Date: Fri Aug 8 16:39:54 2008 +0200 +* Fix PM828_PCI target, for which PCI was *not* configured in. - CFI: allow for dynamically determined flash sizes and addresses +* Fix Lite5200B support: initialize SDelay register + See Freescale's AN3221 "MPC5200B SDRAM Initialization and + Configuration", 3.3.1 SDelay--MBAR + 0x0190 - The CFI driver allowed only for static initializers in the - CFG_FLASH_BANKS_LIST definition, i. e. it did not allow to map - several flash banks contiguously if the bank sizes were not known in - advance, which kind of violates U-Boot's design philosophy. +* Changes/fixes for drivers/cfi_flash.c: - (will be used for example by the TQM8xxL boards) + - Add Intel legacy lock/unlock support to common CFI driver - Signed-off-by: Wolfgang Denk + On some Intel flash's (e.g. Intel J3) legacy unlocking is + supported, meaning that unlocking of one sector will unlock + all sectors of this bank. Using this feature, unlocking + of all sectors upon startup (via env var "unlock=yes") will + get much faster. -commit d9d78ee46d9a396d0a81d00c2b003a9bd32c2e61 -Author: Ben Warren -Date: Thu Aug 7 23:26:35 2008 -0700 + - Fixed problem with multiple reads of envronment variable + "unlock" as pointed out by Reinhard Arlt & Anders Larsen. - QE UEC: Fix compiler warnings + - Removed unwanted linefeeds from "protect" command when + CFG_FLASH_PROTECTION is enabled. - Moved static functions earlier in file so forward declarations are not needed. + - Changed p3p400 board to use CFG_FLASH_PROTECTION - Signed-off-by: Ben Warren + Patch by Stefan Roese, 01 Apr 2006 -commit d5d28fe4aad5f4535400647a5617c11039506467 -Author: David Saada -Date: Mon Mar 31 02:37:38 2008 -0700 +* Changes/fixes for drivers/cfi_flash.c: + - Correctly handle the cases where CFG_HZ != 1000 (several + XScale-based boards) + - Fix the timeout calculation of buffered writes (off by a + factor of 1000) + Patch by Anders Larsen, 31 Mar 2006 - QE UEC: Add MII Commands +* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) - Add MII commands to the UEC driver. Note that once a UEC device is selected, - any device on its MDIO bus can be addressed. + 405 SDRAM: - The SDRAM parameters can now be defined in the board + config file and the 405 SDRAM controller values will + be calculated upon bootup (see PPChameleonEVB). + When those settings are not defined in the board + config file, the register setup will be as it is now, + so this implementation should not break any current + design using this code. - Signed-off-by: David Saada - Signed-off-by: Ben Warren + Thanks to Andrea Marson from DAVE for this patch. -commit fd0f2f3796ff2a7a32d35deb1b7996e485849df7 -Author: Yoshihiro Shimoda -Date: Wed Jul 9 21:07:38 2008 +0900 + 440 DDR: - Added function sdram_tr1_set to auto calculate the + TR1 value for the DDR. + - Added ECC support (see p3p440). - usb: add support for R8A66597 usb controller + Patch by Stefan Roese, 17 Mar 2006 - add support for Renesas R8A66597 usb controller. - This patch supports USB Host mode. +* Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S + Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473] - Signed-off-by: Yoshihiro Shimoda - Signed-off-by: Markus Klotzbuecher +* Add support for ymodem protocol download + Patch by Stefano Babic, 29 Mar 2006 -commit 1d10dcd041aaeae9fd7c821005692898a0303382 -Author: Hunter, Jon -Date: Sat Jul 26 18:59:16 2008 -0500 +* Memory Map Update for Delta board: U-Boot is at 0x80000000-0x84000000 + Merge from Markus Klotzbücher's repo, 01 Apr 2006 - Add support for OMAP5912 and OMAP16xx to usbdcore_omap1510.c +* GCC-4.x fixes: clean up global data pointer initialization for all + boards - Add support to drivers/usb/usbdcore_omap1510.c for OMAP5912 and OMAP16xx devices. +* Update for Delta board: + - redundant NAND environment + - misc Monahans cleanups (remove dead code etc.) + - DA9030 Initialization; some minimal changes to PXA I2C driver to + make it work with the Monahans. + - Make Monahans clock frequency configurable using + CFG_MONAHANS_RUN_MODE_OSC_RATIO and + CFG_MONAHANS_TURBO_RUN_MODE_RATIO. + Merge from Markus Klotzbücher's repo, 25 Mar 2006 - Signed-off-by: Jon Hunter - Signed-off-by: Markus Klotzbuecher +* Enable Quad UART om MCC200 board. -commit eab1007334b93a6209f1ec33615e26ef5311ede7 -Author: Steven A. Falco -Date: Wed Aug 6 15:42:52 2008 -0400 +* Cleanup MCC200 board configuration; omit non-existent stuff. - ppc4xx: Sequoia has two UARTs in "4-pin" mode. Configure the GPIOs as per schematic. +* Add support for MPC859/866 Rev. A.0 - The Sequoia board has two UARTs in "4-pin" mode. This patch modifies the GPIO - configuration to match the schematic, and also sets the SDR0_PFC1 register to - select the corresponding mode for the UARTs. +* Add command for handling DDR ECC registers on MPC8349EE MDS board. - Signed-off-by: Steven A. Falco - Signed-off-by: Stefan Roese +* Fix DDR ECC bit definitions for MPC83xx. -commit 6689484ccd43189322aaa5a1c6cd02cdd511ad7d -Author: Kenneth Johansson -Date: Tue Jul 15 12:13:38 2008 +0200 +* Add initial support for MPC8349E MDS board. - mpc5121: Move iopin features from board specific to common files. +* Add support for ECC DDR initialization on MPC83xx. - And in the process eliminate some duplicate register defines. +* Add DMA support for MPC83xx. - Signed-off-by: Kenneth Johansson +* Add sync in do_reset() routine for MPC83xx after RPR register + was written to. It is need on some targets when BAT translation + is enabled. -commit ef11df6b66ecf5797e94ba322254b8fb7a4e2e12 -Author: John Rigby -Date: Tue Aug 5 17:38:57 2008 -0600 +* Add bit definitions for MPC83xx DDR controller registers. - mpc5121: squash some fdt fixup errors +* Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx. - On ADS5121 when booting linux the following errors are seen: - Unable to update property /soc5121@80000000:bus-frequency, err=FDT_ERR_NOTFOUND - Unable to update property /soc5121@80000000/ethernet@2800:local-mac-address, err=FDT_ERR_NOTFOUND - Unable to update property /soc5121@80000000/ethernet@2800:address, err=FDT_ERR_NOTFOUND +* Correct shift offsets in icache_status and dcache_status for MPC83xx. - This is caused by ft_cpu_setup trying to deal with - both old and new soc node naming. This patch - fixes this by being smarter about what to - fixup. +* Add support for DS1374 RTC chip. - Also do soc node fixups by compatible instead of by path. - A new board config called OF_SOC_COMPAT defined - to be "fsl,mpc5121-immr" replaces the old - OF_SOC node path that was defined to be "soc@80000000". +* Add support for Lite5200B board. + Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006 - Old device trees still work, but the compatiblity - is conditional on CONFIG_OF_SUPPORT_OLD_DEVICE_TREES - which is on by default in include/configs/ads5121.h. +* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific + timer and cpu_reset code from cpu/$(CPU) into the new + cpu/$(CPU)/$(SOC) directories + Patch by Andreas Engel, 13 Mar 2006 - Signed-off-by: John Rigby +* Change max size of uncompressed uImage's to 8MByte and add + CFG_BOOTM_LEN to adjust this setting. -commit 81091f58f0c58ecd26c5b05de2ae20ca6cdb521c -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Aug 2 23:48:30 2008 +0200 + As mentioned by Robin Getz on 2005-05-24 the size of uncompressed + uImages was restricted to 4MBytes. This default size is now + increased to 8Mbytes and can be overrided by setting CFG_BOOTM_LEN + in the board config file. - drivers/serial: Move conditional compilation to Makefile for CONFIG_* macros + Patch by Stefan Roese, 13 Mar 2006 - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c + Patch by Stefan Roese, 13 Mar 2006 -commit 4cd7e6528f61ec669755c3754bb4f9779874fab3 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Aug 2 23:48:32 2008 +0200 +* cpu/ppc4xx/start.S : exceptions are enabled after relocation + Patch by Cedric Vincent, 06 Jul 2005 - nios2/sysid: fix printf warning +* au1x00_eth.c: check malloc return value and abort if it failed + Patch by Andrew Dyer, 26 Jul 2005 - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Change the sequence of events in soft_i2c.c:send_ack() to keep from + incorrectly generating start/stop conditions on the bus. + Patch by Andrew Dyer, 26 Jul 2005 -commit 66da6fa0e35e7ee56628c85981709afe7180fc8e -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Aug 2 23:48:33 2008 +0200 +* Fix bug in [id]cache_status commands for MPC85xx processors; + should look at LSB of L1CSRn registers to determine if L1 cache is + enabled, not the MSB. + Patch by Murray Jensen, 19 Jul 2005 - Fix remaining build issues with MPC8xx FADS boards. +* Fix array overflow with fw_setenv on uninitialised environment + Patch by Murray Jensen, 15 Jul 2005 - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Add support for EmbeddedPlanet EP88x boards + Patch by Yuli Barcohen, 13 Jul 2005 -commit 81d3f1fdddafd1eb53bbca8739f488d417eb3dd2 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Aug 2 23:48:31 2008 +0200 +* Remove board specific configuration includes from the common xilinx + ethernet and iic adapter code. + Patch by Michael Libeskind, 12 Jul 2005 - nios2: fix phys_addr_t and phys_size_t support +* Add Nat Semi DP83865 PHY support to MPC85xx TSEC driver + Patch by Murray Jensen, 08 Jul 2005 - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Add (some) definitions for the MPC85xx local bus controller + Patch by Murray Jensen, 08 Jul 2005 -commit 5fa62000db6d0b46ecdeadbeb50faf5197db49ef -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Aug 2 23:48:34 2008 +0200 +* Add CPM2 I/O pin functions for MPC85xx processors + Patch by Murray Jensen, 08 Jul 2005 - mvbc_p: Fix problem with '#if (CONFIG_CMD_KGDB)' +* Fix compile problem - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Added PCI support for MPC8349ADS board + Patch by Kumar Gala 11 Jan 2006 -commit 1464eff77e7fdaed609ecf263a2423c9dcf96b1f -Author: Mark Jackson -Date: Fri Aug 1 09:48:29 2008 +0100 +* Enable address translation on MPC83xx + Patch by Kumar Gala, 10 Feb 2006 - Fix bitmap display for atmel lcd controller +* Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx + Patch by Kumar Gala, 25 Jan 2006 - The current lcd_display_bitmap() function does not work properly - for the Atmel LCD controller. +* Fixed defines for MPC83xx SICRL register to match current specs + Patch by Kumar Gala, 23 Jan 2006 - 2 fixes need to be done:- +* Only disable the MPC83xx watchdog if its enabled out of reset. + If its disabled out of reset SW can later enable it if so desired + Patch by Kumar Gala, 11 Jan 2006 - (a) when setting the colour map, use the lcd_setcolreg() function - as provided by the Atmel driver - (b) the data is never actually written to the lcd framebuffer !! +* Allow config of GPIO direction & data registers at boot on 83xx + Patch by Kumar Gala, 11 Jan 2006 - Signed-off-by: Mark Jackson +* Enable time handling on 83xx + Patch by Kumar Gala, 11 Jan 2006 -commit 2a433c66b1e2770349fe4911be23c375f053ebd8 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Aug 1 08:40:34 2008 +0200 +* Make System IO Config Registers board configurable on MPC83xx + Patch by Kumar Gala, 11 Jan 2006 - qemu_mips: update README to follow qemu update about default machine +* Fixed PCI indirect config ops to handle multiple PCI controllers + We need to adjust the bus number we are trying to access based + on which PCI controller its on + Patch by Kumar Gala, 12 Jan 2006 - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Report back PCI bus when doing table based device config + Patch by Kumar Gala, 11 Jan 2006 -commit ac169d645f5f0e0b9a232563099209e92a355d8e -Author: TsiChung Liew -Date: Thu Jul 31 19:53:21 2008 -0500 +* Added support for PCI prefetchable region and BARs + If a host controller sets up a region as prefetchable and + a device's BAR denotes it as prefetchable, allocate the + BAR into the prefetch region. - ColdFire: Fix compilation issue caused by a missing function + If a BAR is prefetchable and no prefetchable region has + been setup by the controller we fall back to allocating + the BAR into the normally memory region. + Patch by Kumar Gala, 11 Jan 2006 - Implement usec2ticks() which is used by fsl_i2c.c in - lib_m68k/time.c +* Add helper function for generic flat device tree fixups for mpc83xx + Patch by Kumar Gala, 11 Jan 2006 - Signed-off-by: TsiChung Liew +* Add support for passing initrd information via flat device tree + Patch by Kumar Gala, 11 Jan 2006 -commit 01ae85b58b51d2fb1fac5b93095f6042cf48ae7b -Author: TsiChung Liew -Date: Thu Jul 31 19:53:06 2008 -0500 +* Added OF_STDOUT_PATH and OF_SOC - Fix compilation error for TASREG + OF_STDOUT_PATH specifies the path to the device the kernel can use + for console output - TASREG is ColdFire platform, the include ppc4xx.h in - board/esd/common/flash.c causes conflict. + OF_SOC specifies the proper name of the SOC node if one exists. + Patch by Kumar Gala, 11 Jan 2006 - Signed-off-by: TsiChung Liew +* Allow board code to fixup the flat device tree before booting a kernel + Patch by Kumar Gala, 11 Jan 2006 -commit 35d3bd3cc35c508a6823dac77e0fd126808e4fc7 -Author: TsiChung Liew -Date: Thu Jul 31 19:52:36 2008 -0500 +* Added CONFIG_ options for bd_t and env in flat dev tree - Fix compilation error for MCF5275 + CONFIG_OF_HAS_BD_T will put a copy of the bd_t + into the resulting flat device tree. - Rename OBJ to COBJ in board/platform/Makefile + CONFIG_OF_HAS_UBOOT_ENV will copy the environment + variables from u-boot into the flat device tree - Signed-off-by: TsiChung Liew + Patch by Kumar Gala, 11 Jan 2006 -commit 5c40548f01218360a1f1395198c50ff45f3035b5 -Author: TsiChung Liew -Date: Thu Jul 31 19:52:28 2008 -0500 +* Add support for the DHCP vendor optional bootfile (#67). + Ignores the vendor TFTP server name option (#66). + Patch by Murray Jensen, 30 Jun 2005 - Fix compile error caused by incorrect function return type +* Fix a HW timing issue on 8548 CDS for eTSEC 3 in RGMII mode + Patch by Andy Fleming, 14 Jun 2005 - Rename int mii_init(void) to void mii_init(void) for idmr - ColdFire platform +* Fix bad register definitions for LTX971 PHY on MPC85xx boards. + Patch by Gerhard Jaeger, 21 Jun 2005 - Signed-off-by: TsiChung Liew +* Add netconsole and some more commands to RPXlite_DW board + Patch by Sam Song, 19 Jun 2005 -commit a58c78067c928976c082c758d3987e89ead5b191 -Author: Wolfgang Denk -Date: Fri Aug 1 12:06:22 2008 +0200 +* Fix bad declaration on pci_cfgfunc_nothing + Patch by Sam Song, 19 Jun 2005 - Fix build issues with MPC8xx FADS boards. +* Adjust "echo" as a default command + Patch by Sam Song, 19 Jun 2005 - Signed-off-by: Wolfgang Denk +* Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC + Patch by KokHow Teh, 16 Jun 2005 -commit 4b50cd12a3b3c644153c4cf393f4a4c12289e5aa -Author: Wolfgang Denk -Date: Thu Jul 31 17:54:03 2008 +0200 +* Add crc of data to jffs2 (in jffs2_1pass_build_lists()). + Patch by Rick Bronson, 15 Jun 2005 - Prepare v1.3.4-rc2: update CHANGELOG +* Coding Style cleanup - Signed-off-by: Wolfgang Denk +* Avoid dereferencing NULL in find_cmd() if no valid commands were found + Patch by Andrew Dyer, 13 Jun 2005 -commit a48311557db6e7e9473a6163b44bb1e6c6ed64c4 -Author: Mark Jackson -Date: Thu Jul 31 16:09:00 2008 +0100 +* Add ADI Blackfin support + - add support for Analog Devices Blackfin BF533 CPU + - add support for the ADI BF533 Stamp uClinux board + - add support for the ADI BF533 EZKit board + Patches by Richard Klingler, 11 Jun 2005 - Add gzipped logo support +* Add loads of ntohl() in image header handling + Patch by Steven Scholz, 10 Jun 2005 - The README file states that CONFIG_VIDEO_BMP_GZIP behaves as follows: +* Switch MPC86xADS and MPC885ADS boards to use cpuclk environment + variable to set clock + Patch by Yuli Barcohen, 05 Jun 2005 - If this option is set, additionally to standard BMP - images, gzipped BMP images can be displayed via the - splashscreen support or the bmp command. +* RPXlite configuration fixes + - Use correct flash sector size + - Use correct memory test end address + - Add support for bzip2 compression + - Various small fixes + Patch by Yuli Barcohen, 05 Jun 2005 - However, the splashscreen function *only* supports standard BMP images. +* Memory configuration changes for ZPC.1900 board + - Fix SDRAM timing on both local bus and 60x bus + - Add support for second flash bank (SIMM) + - Change boot flash base + Patch by Yuli Barcohen, 05 Jun 2005 - This patch adds the documented gzip support. +* Add support for Adder boards with 16MB SDRAM; + add support for second FEC on Adder87x board. + Patch by Yuli Barcohen, 05 Jun 2005 - Signed-off-by: Mark Jackson +* Fix conditional for including ks8695eth driver + Patch by Greg Ungerer, 04 Jun 2005 -commit a5bcb01fbde6b1f1c9863cd86e5c4c369f0121ac -Author: Mark Jackson -Date: Thu Jul 31 15:56:48 2008 +0100 +* Fix Makefile: include config.mk only after CROSS_COMPILE is defined + Patch by Friedrich Lobenstock, 02 Jun 2005 - Fix Atmel LCD controller endianess for AVR32 processors +* Fix comment in common/soft_i2c.c + Patches by Peter Korsgaard/Tolunay Orkun, 26 May 2005 - The Atmel lcd controller is used on Atmel's AT91 (little endian) and - AVR32 (big endian) platforms. +* Cleanup compiler warnings. + Patch by Greg Ungerer, 21 May 2005 - As such, the controller can handle both big and little endian memory. +* Word alignment fixes for word aligned NS16550 UART + Patch by Jean-Paul Saman, 01 Mar 2005 - This patch fixes the driver for the AVR32 platform. + Fixes bug with UART that only supports word aligned access: removed + "__attribute__ ((packed));" for "(CFG_NS16550_REG_SIZE == 4)" some + (broken!) versions of GCC generate byte accesses when encountering + the packed attribute regardless if the struct is already correctly + aligned for a platform. Peripherals that can only handle word + aligned access won't work properly when accessed with byte access. + The struct NS16550 is already word aligned for REG_SIZE = 4, so + there is no need to packed the struct in that case. - Signed-off-by: Mark Jackson +* Fix behaviour if gatewayip is not set + Patch by Robin Gilks, 23 Dec 2004 -commit cdb8bd2fd3bcbe65d8e4334a55f5a667845426a1 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Thu Jul 31 15:56:01 2008 +0200 +* Fix cleanup for netstart board. + Remove build results from repository - apollon: fix build out of tree +* Some code cleanup for GCC 4.x - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Fixes to support environment in NAND flash; + enable NAND flash based environment for delta board. -commit 2e752be39d3e398d4ab89ffa6634c397df298297 -Author: Guennadi Liakhovetski -Date: Thu Jul 31 12:35:04 2008 +0200 +* Add support for Intel Monahans CPU on Zylonite and Delta boards + (This is Work in Progress!) - Uncompressed images loaded to their start address shall set load_end too +* Add support for TQM8260-AI boards. - Signed-off-by: Guennadi Liakhovetski - Acked-by: Bartlomiej Sieka +* Minor code cleanup -commit c37207d7f51e19c17f859966f314e27cc1231801 -Author: Wolfgang Denk -Date: Wed Jul 16 16:38:59 2008 +0200 +* Merge the new NAND code (testing-NAND brach); see doc/README.nand + Rewrite of NAND code based on what is in 2.6.12 Linux kernel + Patch by Ladislav Michl, 29 Jun 2005 - Fix printf() format problems with configurable prompts +* Add lowboot target to mcc200 board + Patch by Stefan Roese, 4 Mar 2006 - U-Boot allows for configurable prompt strings using the - CONFIG_AUTOBOOT_PROMPT resp. CONFIG_MENUPROMPT definitions. So far, - the assumption was that any such user defined problts would contain - exactly one "%d" format specifier. But some boards did not. +* Fix problem with flash_get_size() from CFI driver update + Patch by Stefan Roese, 1 Mar 2006 - To allow for flexible boot prompts without adding too complex code we - now allow to specify the whole list of printf() arguments in the user - definition. This is powerful, but requires a responsible user who - really understands what he is doing, as he needs to know for exanple - which variables are available in the respective context. +* Make CFG_NO_FLASH work on ARM systems + Patch by Markus Klotzbuecher, 27 Feb 2006 - Signed-off-by: Wolfgang Denk +* Update mcc200 config: Disable PCI and DoC, use 133 MHz IPB clock, + use hush shell. -commit 54754120637b6a7f4ff774fb199fc550bcfea1da -Author: Wolfgang Denk -Date: Thu Jul 31 17:02:14 2008 +0200 +* Convert mcc200 to use common CFI flash driver + Patch by Stefan Roese, 28 Feb 2006 - TQM85xx: fix typo introduce by commit ffbb5cb9 +* Add env-variable "unlock" to handle initial state of sectors + (locked/unlocked). - Signed-off-by: Wolfgang Denk + Only the U-Boot image and it's environment is protected, + all other sectors are unprotected (unlocked) if flash + hardware protection is used (CFG_FLASH_PROTECTION) and + the environment variable "unlock" is set to "yes". -commit 0b4951d4cddca9cc800745891c95b291e47cbbd7 -Author: Wolfgang Denk -Date: Thu Jul 31 15:27:01 2008 +0200 + Patch by Stefan Roese, 28 Feb 2006 - mvbc_p board: fix most build warnings. +* Update drivers/cfi_flash.c: + - find_sector() called in both versions of flash_write_cfiword() + Patch by Peter Pearse, 27th Feb 2006 - Signed-off-by: Wolfgang Denk +* CFI support for a x8/x16 AMD/Spansion flash configured in x8 mode + Patch by Jose Maria Lopez, 16 Jan 2006 -commit c4ec6db074051d2f6fc76a66411c60621b22bc02 -Author: Wolfgang Denk -Date: Thu Jul 31 13:57:20 2008 +0200 +* Add support for AMD/Spansion Flashes in flash_write_cfibuffer + Patch by Alex Bastos and Thomas Schaefer, 2005-08-29 - E1000: clean up CONFIG_E1000_FALLBACK_MAC handling +* Changes/fixes for drivers/cfi_flash.c: + We *should* check if there are any error bits if the previous call + returned ERR_OK (Otherwise we will have output an error message in + flash_status_check() already.) The original code would only check for + error bits if flash_status_check() returns ERR_TIMEOUT. + Patch by Marcus Hall, 23 Aug 2005 - Avoid "integer constant is too large for 'long' type" warnings. - And simplify the code. +* Changes/fixes for drivers/cfi_flash.c: + - Add CFG_FLASH_PROTECT_CLEAR on drivers/cfi_flash.c + - Prohibit buffer write when buffer_size is 1 on drivers/cfi_flash.c + Patch by Sangmoon Kim, 19 Aug 2005 - Signed-off-by: Wolfgang Denk +* Fixes for drivers/cfi_flash.c: + - Fix wrong timeout value usage in flash_status_check() + - Round write_tout up when converting to msec in flash_get_size() + - Remove clearing flash status at the end of flash_write_cfibuffer() + which sets Intel 28F640J3 flash back to command mode on CSB472 + Patch by Tolunay Orkun, 02 July 2005 -commit 9196b44334c330cc13de2464c59181e4db71f549 -Author: Matvejchikov Ilya -Date: Wed Jul 30 23:21:19 2008 +0400 +* Add basic support for the SMMACO4 Board from PanDaCom. + Patch by Heiko Schocher, 20 Feb 2006 - 8260: Making the use of gd->pci_clk dependant on the CONFIG_PCI +* Add GIT version information (commid ID) to untagged U-Boot versions - Signed-off-by: Matvejchikov Ilya + As done in the linux kernel, the U-Boot version (U_BOOT_VERSION) + of all unreleased (untagged) U-Boot images will be automatically + extended upon compiletime with a part of the GIT commit ID and + possibly with "dirty" if uncommited changes are detected. -commit 6361ad4b596f5a940a01c91ae0297d98f790cbe0 -Author: Matvejchikov Ilya -Date: Wed Jul 30 23:20:32 2008 +0400 + Here an example for the resulting version: + "U-Boot 1.1.4-g3457ac18-dirty" - PPC: Add pci_clk in the global_data for CPM2 processors + The version is now maintained in the toplevel Makefile and the + version headers are autogenerated. - This patch adds pci_clk field to the global_data structure for the - processors which have CPM2 module in case the CONFIG_PCI is defined. + Patch by Stefan Roese, 9 Feb 2006 - Signed-off-by: Matvejchikov Ilya +* Update default environment for INKA4x00 board. -commit f0ff885ca64655bee6540eb8a25eed90b1152686 -Author: Kumar Gala -Date: Wed Jul 30 14:13:30 2008 -0500 +* Convert CPCI750 to use common CFI flash driver + Patch by Reinhard Arlt, 8 Feb 2006 - mpc85xx: Update linker scripts for Freescale boards +* Various changes to esd HH405 board specific files + Patch by Matthias Fuchs, 07 Feb 2006 - * Move to using absolute addressing always. Makes the scripts a bit more - portable and common - * Moved .bss after the end of the image. These allows us to have more - room in the resulting binary image for code and data. - * Removed .text object files that aren't really needed - * Make sure _end is 4-byte aligned as the .bss init code expects this. - (Its possible that the end of .bss isn't 4-byte aligned) +* Cleanup U-Boot boot messages on ARM. - Signed-off-by: Kumar Gala + To match the U-Boot user interface on ARM platforms to the U-Boot + standard (as on PPC platforms), some messages with debug character + are removed from the default U-Boot build. + Enable DEBUG for lib_arm/board.c to enable debug messages. + New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options. + Patch by Stefan Roese, 24 Jan 2006 -commit 57c219ad5d34dd9d49991777a62e3899595f2ec7 -Author: Kumar Gala -Date: Wed Jul 30 08:01:15 2008 -0500 +* Fix various compiler warnings on ppc4xx builds (ELDK 4.0) + Patch by Stefan Roese, 18 Jan 2006 - Fix compile warnings in dlmalloc +* Add VGA support (CT69000) to CPCI750 board. + Insert missing __le32_to_cpu() for filesize in ext2fs_read_file(). + Patch by Reinhard Arlt, 30 Dec 2005 - The origional code was using on odd reference to get to the first - real element in av_[]. The first two elements of the array are - not used for actual bins, but for house keeping. If we are more - explicit about how use the first few elements we can get rid of the - warnings: +* PMC405 and CPCI405: Moved configuration of pci resources + into config file. + PMC405 and CPCI2DP: Added firmware download and booting via pci. + Patch by Matthias Fuchs, 20 Dec 2005 - dlmalloc.c: In function 'malloc_extend_top': - dlmalloc.c:1971: warning: dereferencing type-punned pointer will break strict-aliasing rules - dlmalloc.c:1999: warning: dereferencing type-punned pointer will break strict-aliasing rules - dlmalloc.c:2029: warning: dereferencing type-punned pointer will break strict-aliasing rules - ... +* Add ColdFire targets to MAKEALL script + Patch by Zachary Landau, 26 Jan 2006 - The logic of how this code came to be is: - bin_at(0) = (char*)&(av_[2]) - 2*SIZE_SZ +* Add support for r5200 board + Patch by Zachary Landau, 26 Jan 2006 - SIZE_SZ is the size of pointer, and av_ is arry of pointers so: - bin_at(0) = &(av_[0]) +* Add support for Freescale M5271 processor + Patch by Zachary Landau, 26 Jan 2006 - Going from there to bin_at(0)->fd or bin_at(0)->size should be straight forward. +* Fix 28F256J3A support on PM520 board + (without bank-switching only 32 MB can be accessed) - Signed-off-by: Kumar Gala +* Fix mkimage bug with multifile images created on 64 bit systems. -commit 3f9ae1a5d43c49a8ecf497470c3d1d80255e44b9 -Author: Stefan Roese -Date: Wed Jul 30 10:21:01 2008 +0200 +* Add support for 28F256J3A flash (=> 64 MB) on PM520 board - ppc4xx: Fix W7OLMG compile problems by adding missing LM75 defines +* Fix compiler problem with at91rm9200dk board. + Patch by Eugen Bigz, 19 Dec 2005 - Signed-off-by: Stefan Roese +====================================================================== +Changes for U-Boot 1.1.4: +====================================================================== -commit ebb86c4ecd37a7701358284e497ca4c6483c7cc5 -Author: Stefan Roese -Date: Wed Jul 30 09:59:51 2008 +0200 +* Changes to Yellowstone & Yosemite 440EP/GR eval boards: + - Changed GPIO setup to enable another address line in order to + address 64M of FLASH. + - Added function sdram_tr1_set to auto calculate the tr1 value for + the DDR. + Patch by Steven Blakeslee, 12 Dec 2005 - cmd_bootm.c: Fix problem with '#if (CONFIG_CMD_USB)' +* MPC5200: Set PCI retry counter to 0 = infinite retry; + The default of 255 is too short for slow devices. + Patch by Martin Nykodym, 12 Dec 2005 - A recent patch used '#if (CONFIG_CMD_USB)' instead of - '#if defined(CONFIG_CMD_USB)'. This patch fixes this problem and makes - common/bootm.c compile again. +* Change port configuration for O2DNT (CODEC1 on PSC1). - Signed-off-by: Stefan Roese - Acked-by: Markus Klotzbuecher +* Fix register for PCI async mode on PPC440EP + Patch by Youngchul Bang, 08 Dec 2005 -commit 2cb9080427fe641dcb71da46cd0634dd406f37ed -Author: Kyungmin Park -Date: Tue Jul 22 08:01:43 2008 +0900 +* Fix U-Boot linking problems (add .eh_frame segment to linker script) + This segment may be required by some libgcc.a functions + (like _udivdi3). - Remove unused I2C at apollon board +* Fix DPRAM offset/size for MPC8541/8555. + Simplify TQM85xx Makefile handling. - There are no I2C devices on this board. +* Fix data overflow (typo?) in rtc/ds1302.c - Signed-off-by: Kyungmin Park +* Fix U-Boot compilation for MIPS boards using ELDK 4.0 -commit 3c95960e526b3b026da20201db64526f46faf14b -Author: Wolfgang Denk -Date: Thu Jul 31 10:12:09 2008 +0200 +* Add support for TQM8541/8555 boards, TQM85xx support reworked: + - Support for TQM8541/8555 boards added. + - Complete rework of TQM8540/8560 support. + - Common TQM85xx code now supports all current TQM85xx platforms + (TQM8540/8541/8555/8560). + - DDR SDRAM size detection added. + - CAS latency default values can be overwritten by setting "serial#" + to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used. + If problems are detected with this non default CAS latency, + the default values will be used instead. + - Flash size detection added. + - Moved FCC ethernet driver initialization behind TSEC driver init + -> TSEC is first device. + Patch by Stefan Roese, 30 Nov 2005 - at91rm9200dk, csb637: fix NAND related build problems +* Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board. + Patch by John Otken, 23 Nov 2005 - Tried fixing NAND support for the at91rm9200dk board; untested. - Disabled NAND support in the csb637 board config file. +* Changed PPC44x startup message (cpu info, speed...) to common style: + On PPC44x platforms, the startup message generated in "cpu.c" only + comprised the ppc type and revision but not additional information + like speed etc. Those speed infos where printed in the board specific + code. This new implementation now prints all CPU infos in the common + cpu specific code. No board specific code is needed anymore and + therefore removed from all current 44x implementations. + Patch by Stefan Roese, 27 Nov 2005 - Signed-off-by: Wolfgang Denk +* Adjust TQM834x PHY addresses for latest hardware revision. -commit 09d318a8bb1444ec92e31cafcdba877eb9409e58 -Author: Kumar Gala -Date: Tue Jul 29 12:23:49 2008 -0500 +* Increase malloc arena on TQM5200 board to 256 kB. + With 64 kb uniform flash sector size the old value of 128 kB was + too small. - fsl_i2c: Use timebase timer functions instead of get_timer() +* Fix miiphy global data initialization (problem on 4xx boards when + no ethaddr is assigned). Initialization moved from + miiphy_register() to eth_initialize(). - The current implementation of get_timer() is only really useful after we - have relocated u-boot to memory. The i2c code is used before that as part - of the SPD DDR setup. + Based on initial patch for 4xx platform by Matthias Fuchs. - We actually have a bug when using the get_timer() code before relocation - because the .bss hasn't been setup and thus we could be reading/writing - a random location (probably in flash). +* Remove unnnecessary #include from include/asm-*/u-boot.h - Signed-off-by: Kumar Gala +* Allow use of include/image.h and include/asm-*/u-boot.h in proprietary code. + The COPYING file was extended to make clear that these files can be + used in non-GPL code, too. + Also, a corresponding note was placed in the headers of the affected files. -commit 4fc72a0d6ca85070a5e90d76cc5a853526ac09c4 -Author: Frank Svendsbøe -Date: Tue Jul 29 14:49:31 2008 +0200 +* Add support for Prodrive P3P440 board: + - Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c + - CFG_FLASH_QUIET_TEST added to use the common CFI driver + for bank autodetection + Patch by Stefan Roese, 22 Nov 2005 - Adder8xx: Fix CFG_MONITOR_LEN +* Change all '$(...)' variable references into '${...}' + which makes the environment compatible with the hush shell. + WARNING: Support for the old '$(...)' syntax will be + discontinued in a later version. - Due to increased space usage, U-Boot can no longer be stored in three sectors. - The current U-Boot use just over three flash sectors (197k), and U-Boot will - become corrupt after saving environment variables. This patch adds another 64k - to CFG_MONITOR_LEN. +* Minor changes to init flags in TQM834x PCI. - Signed-off-by: Frank E. Svendsbøe +* Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM) + Patch by Stefan Roese, 15 Nov 2005 -commit a4c59ad4a21140550ada6f97690d2527c4146ce5 -Author: Kyungmin Park -Date: Tue Jul 29 08:47:57 2008 +0900 +* New PPC 405EP board added: CMS700 + Added CONFIG_NET_MULTI for VOM405 board. + Added reset_phy() for VOM405 board. + Patch by Matthias Fuchs, 09 Nov 2005 - Add OneNAND IPL related files to gitignore +* Updated PCI mapping for esd CPCI2DP board. + Add support for error LED. + Patch by Matthias Fuchs, 07 Nov 2005 - Signed-off-by: Kyungmin Park +* Fix MPC85xx PCI support (pci_register_hose() before pci config access) + Patch by Stefan Roese, 07 Nov 2005 -commit 8d87589e8e874df7120a3d9667f051bc33bac250 -Author: Rafal Jaworowski -Date: Mon Jul 28 20:38:25 2008 +0200 +* Correct PPC Timebase register definitions (SPRN_TBRL...) + Patch by Stefan Roese, 07 Nov 2005 - API: Teach the storage layer about SATA and MMC options. +* Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size + Patch by Stefan Roese, 05 Nov 2005 - Signed-off-by: Rafal Czubak - Acked-by: Rafal Jaworowski +* Additional fix for external IRQ config on Yellowstone & Yosemite + Patch by Stefan Roese, 03 Nov 2005 -commit 6b73b754f782e1ecce5048bf20b22ce56a07a5b8 -Author: Rafal Jaworowski -Date: Mon Jul 28 20:37:48 2008 +0200 +* Add support for Ocotea pass 3 with 440GX Rev. F + Patch by Stefan Roese, 01 Nov 2005 - API: Dump contents of sector 0 in the demo application. +* Fix external IRQ configuration on Yellowstone & Yosemite + Patch by Stefan Roese, 28 Oct 2005 - Signed-off-by: Rafal Czubak - Acked-by: Rafal Jaworowski +* Add support for multiple PHYs. + Tested on the following boards: + cmcpu2 (at91rm9200/ether.c) + PPChameleon (ppc4xx/4xx_enet.c) + yukon (mpc8220/fec.c) + uc100 (mpc8xx/fec.c) + tqm834x (mpc834x/tsec.c) with EEPRO100 + lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c) + Main changes include: + common/miiphyutil.c + - miiphy_register routine was added to allow multiple PHYs to be registered + - miiphy_read and miiphy_write are now defined in this file, and + require additional argument (char *devname) + - other miiphy_* routines also require additional device name argument + ../lib_i386/board.c + ../lib_ppc/board.c + Calling reset_phy() was moved to be executed *after* eth_initialize(). + This is necessary as now some of the implementations of reset_phy() + may need to use miiphy_reset() which is not allowed before eth_initialize() + as eth_initialize registers all required miiphy_* routines. + Tested on IP860 and PHY initializes properly after this change. -commit 13ca6305f2eba49c175f6370c35286141059c789 -Author: Rafal Jaworowski -Date: Mon Jul 28 20:37:10 2008 +0200 +* Correct includes for flat tree builder. - API: Correct storage enumeration routine, other minor fixes in API storage area. +* Fix conflicting types (flash_write()) in trab auto_update.c. - Signed-off-by: Rafal Czubak - Acked-by: Rafal Jaworowski +* Add PCI support for the TQM834x board. -commit 05c7fe0f049b1c9eb9a1992f27e5e350d865f4a8 -Author: Rafal Jaworowski -Date: Mon Jul 28 20:36:19 2008 +0200 +* Add missing 4xx board to MAKEALL + Patch by Stefan Roese, 20 Oct 2005 - API: Fix compilation warnings in api_examples/demo.c. +* Fix conflicting types (flash_write()) in esd auto_update.c + Patch by Stefan Roese, 20 Oct 2005 - Signed-off-by: Rafal Czubak +* Fix problem with sleep in NetConsole (use get_timer()) + Patch by Stefan Roese, 20 Oct 2005 -commit c14eefcc48212af2f3314809605698dd8393a90a -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Jul 27 17:09:43 2008 +0200 +* Add NetConsole Support for AMCC eval boards + Patch by Stefan Roese, 20 Oct 2005 - Fix more printf() format warnings +* Fix NetConsole support on 4xx (only print eth link on 1st transfer) + Patch by Stefan Roese, 18 Oct 2005 - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Add fat & ext2 support to AMCC 440EP boards Yosemite & Bamboo. + Fix identation on ext2ls help entry. + Patch by Stefan Roese, 14 Oct 2005 -commit 936897d4d1365452bbbdf8430db5e7769ef08d38 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Jul 25 15:18:16 2008 +0200 +* Add support for TQM834x boards. + Cleanup. - Fix remaining CFG_CMD_ define, ifdef and comments +* Cleanup for GCC-4.x - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Add documentation for Open Firmware Flat Tree and usage. + Patch by Pantelis Antoniou, 13 Oct 2005 -commit 5d1d00fb36005482e1803a00ddc46efa11d719af -Author: Stefano Babic -Date: Fri Jul 25 08:57:40 2008 +0200 +* Add missing files for Pantelis Antoniou's patch + Patch by Pantelis Antoniou, 04 Sep 2005 - Add include for config.h in command.h. +* Fix problem in ppc4xx eth-driver without ethaddr (only without + CONFIG_NET_MULTI set) + Patch by Stefan Roese, 10 Oct 2005 - Because the cmd_tbl_s structure depends on the configuration file, it - must be assured that config.h is included before the structure is - evaluated by the compiler. If this is not certain, it could happen - that the compiler generates structures of different size, depending - on the fact if the source file includes before or after - . +* Fix gzip bmp support (test if malloc fails, warning when truncated). + Increase CFG_VIDEO_LOGO_MAX_SIZE on HH405 board. + Patch by Stefan Roese, 07 Oct 2005 - The effect is that u-boot crashes when tries to relocate the command - table (for ppc) or try to access to the command table for other - architectures. +* Add support for OF flat tree for the STXtc board. + Patch by Pantelis Antoniou, 04 Sep 2005 - The problem can happen on board-depending commands. All general - commands under /common are unaffected, because they include already - config.h before command.h. +* Support passing of OF flat trees to the kernel. + Patch by Pantelis Antoniou, 04 Sep 2005 - Signed-off-by: Stefano Babic +* Cleanup -commit 2dacb734bac9dba1db9e704d3e0b200ef521c79a -Author: Scott Wood -Date: Wed Jul 23 13:16:06 2008 -0500 +* Add support for NetSilicon NS7520 processor. + Patch by Art Shipkowski, 12 May 2005 - NAND: $(obj)-qualify ecc.h in kilauea NAND boot Makefile. +* Add support for AP1000 board. + Patch by James MacAulay, 07 Oct 2005 - This fixes building out-of-tree. +* Eliminate hard-coded address of Ethernet transfer buffer on at91rm9200 + Patch by Anders Larsen, 07 Oct 2005 - Signed-off-by: Scott Wood + The Atmel errata #11 states that the transfer buffer descriptor + table must be aligned on a 16-word boundary. As it turned out, this + is insufficient - it seems the table must be aligned on a boundary + at least as large as the table itself (in Linux this is not an + issue - the table is aligned on a PAGE_SIZE (4096) boundary). -commit 36d59bd9da9e15d19b867b48449408830f4e2ad5 -Author: Heiko Schocher -Date: Wed Jul 23 07:30:46 2008 +0200 +* Fixed compilation for ARM when using a (standard) hard-FP toolchain + Patch by Anders Larsen, 07 Oct 2005 - Fix warnings if compiling with IDE support. +* Cleanup warnings for cpu/arm720t & cpu/arm1136 files. + sed the linker scripts, rather than pre-process them. + Patch by Peter Pearse, 07 Oct 2005 - cmd_ide.c:827: Warnung: weak declaration of `ide_outb' after first use results in unspecified behavior - cmd_ide.c:839: Warnung: weak declaration of `ide_inb' after first use results in unspecified behavior +* Update make target for ARM supported boards. + Use lowlevel_init() instead of platformsetup() [rename]. + Patch by Peter Pearse, 06 Oct 2005 - Signed-off-by: Heiko Schocher +* Fix booting from serial dataflash on AT91RM9200 + Patch by Peter Menzebach, 29 Aug 2005 -commit 7610db17fd4d59c51d825488526d85ede2f06767 -Author: Adrian Filipi -Date: Tue Jul 22 14:28:11 2008 -0400 +* Add JFFS2 support for TRAB board + Patch by Martin Krause, 25 Aug 2005 - Removed support for the adsvix board. +* Remove unnecessary dependency of netconsole on CONFIG_NET_MULTI + Patch by Marcus Hall, 24 Aug 2005 - Support for the adsvix was originally provided by Applied Data - Systems (ADS), inc., now EuroTech, Inc. - The board never shipped aside from some sample boards. +* Fix the machine-id of the Cogent csb637 board + Patch by Anders Larsen, 05 Oct 2005 - Signed-off-by: Adrian Filipi +* Complete support for the KwikByte KB920x boards + Patch by Anders Larsen, 05 Oct 2005 -commit f96b44cef897bd372beb86dde1b33637c119d84d -Author: Remy Bohmer -Date: Tue Jul 22 16:22:11 2008 +0200 +* Set the AT91RM9200 clock to asynchronous mode + Patch by Anders Larsen, 03 May 2005 - ARM: set GD_FLG_RELOC for boards skipping relocation to RAM +* Set the AT91RM9200 clock to synchronous mode + Patch by Anders Larsen, 29 Apr 2005 - If CONFIG_SKIP_RELOCATE_UBOOT is set the flag GD_FLG_RELOC is usually - never set, because relocation to RAM is actually never done by U-boot - itself. However, several pieces of code check if this flag is set at - some time. +* Add support for Cogent csb637 + Patch by Anders Larsen, 29 Apr 2005 - So, to make sure this flag is set on boards skipping relocation, this - is added to the initialisation of U-boot at a moment where it is safe - to do so. +* Fix dm9161.c initialization + Patch by Anders Larsen, 29 Apr 2005 - Signed-off-by: Remy Bohmer +* Fix problems introduced by Patch by Steven Scholz, 02 Mar 2005 + (8e2be51de8dd03c1ce4d06cbb18ad06133d47cd5) -commit e4dafff86f289b5677143a3e41da7b45c6d27fc7 -Author: Timur Tabi -Date: Mon Jul 21 14:26:23 2008 -0500 +* Move dm9161.c and lxt972.c into cpu/arm920t/at91rm9200 + Patch by Anders Larsen, 29 Apr 2005 - fsl-i2c: fix writes to data segment before relocation +* Fix device partition intialization for SystemACE disks. + Patch by Stephen Williams, 28 Apr 2005 - Prevent i2c_init() in fsl_i2c.c from writing to the data segment before - relocation. Commit d8c82db4 added the ability for i2c_init() to program the - I2C bus speed and save the value in i2c_bus_speed[], which is a global - variable. It is an error to write to the data segment before relocation, - which is what i2c_init() does when it stores the bus speed in i2c_bus_speed[]. +* Added support for KwikByte KB920x boards (based on AT91RM9200) + Patch by Matt ?? , 27 Apr 2005 - Signed-off-by: Timur Tabi +* Add support for S29GL064M-R3 flash chip on xsengine board + Patch by Kurt Stremerch, 18 Apr 2005 -commit dbd32387920e5ad6f9dd58a7b5012bbabe2a6a21 -Author: Wolfgang Ocker -Date: Mon Jul 28 16:56:51 2008 +0200 +* E500 update: repoint IVPR to RAM when code is relocated + Patch by Kylo Ginsberg, 13 Apr 2005 - mips: Fix baudrate divisor computation on alchemy cpus +* Fix loop end test in lib_generic/string.c:strswab() + Patch by Andrew Dyer, October 10, 2005 + Signed-off-by: Andrew Dyer - Use CFG_MIPS_TIMER_FREQ when computing the baudrate divisor - on alchemy cpus. +* Cleanup - Signed-off-by: Wolfgang Ocker - Signed-off-by: Shinya Kuribayashi +* Update ARM Integrator boards: + Correct addessing errors in platform files. + Split off common core module data from Integrator header files to + include/armcoremodule.h. + Patch by Peter Pearse, 04 Oct 2005 -commit a229d291f33308ab7761d39f25fa1a53c0fc00a2 -Author: Haavard Skinnemoen -Date: Wed Jul 23 10:55:46 2008 +0200 +* Make sure only supported compiler options are used + Import "cc-option" shell function from kernel and + use it to get the correct ARM GCC options for individual CPUs + Patch by Peter Pearse, 30 Jun 2005 - spi flash: Fix printf() format warnings +* Fix 440GR to print correct cpu revision + Patch by Stefan Roese, 04 Oct 2005 - Signed-off-by: Haavard Skinnemoen +* Change board message on AMCC Yosemite & Yellowstone to common style + Patch by Stefan Roese, 03 Oct 2005 -commit 252a5e0738bcafaf25f7fbb40f19a59abc2cb13e -Author: Haavard Skinnemoen -Date: Wed Jul 23 10:55:31 2008 +0200 +* Fix compiler warning - atmel_mci: Fix printf() format warnings +* Fix FEC PHY addresses for TQM85xx boards - Signed-off-by: Haavard Skinnemoen +* Fix uninitialized variable problem in hush shell + Patch by Lars Rostock, 26 Sep 2005 -commit 7f4b009f4232d57084ce0ec5aeb3b57bccb08e4c -Author: Haavard Skinnemoen -Date: Wed Jul 23 10:55:15 2008 +0200 +* Undo change of f6e20fc6ca... to include/configs/trab.h + (Must have been an accident?) - avr32: Fix printf() format warnings +* Add support for AT91RM9200 OHCI Controller. + Patch by Eric Benard, 07 Apr 2005 - Signed-off-by: Haavard Skinnemoen +* Update ARM mach-types.h + Patch by Eric Benard, 07 Apr 2005 -commit a79c3e8d9c31db25d5ca3ec8e08a97f323410dd4 -Author: Haavard Skinnemoen -Date: Wed Jul 23 10:52:19 2008 +0200 +* Add support for MP2USB board. + Patch by Eric Benard, 07 Apr 2005 - avr32: asm/io.h needs asm/types.h +* Add board support for armadillo HT1070 + Patch by Rowel Atienza, 06 Apr 2005 - map_physmem() takes a phys_addr_t as parameter. This type is defined in - asm/types.h, so we need to include that file. +* Second Ethernet address enabled for MPC885ADS and MPC8272ADS. + Patch by Vitaly Bordug, 30 Mar 2005 - Signed-off-by: Haavard Skinnemoen +* Add iopset command on mpc8xx + Patch by Daniel Eisenhut, 25 Mar 2005 -commit 1953d128fd07f07d1c3810a28c0863ea64dae1b6 -Author: Michal Simek -Date: Thu Jul 17 12:25:46 2008 +0200 +* Add support for MII in eepro100 driver. + Patch by Gleb Natapov, 21 Mar 2005 - microblaze: Fix printf() format issues +* Fixes to the Lubbock (PXA 25x) support: + - Resolve the FIXME with respect to saving the u-boot environment. + - Make the default load address land in real memory. + - Fix lan91c96 SMC_{in,out}{b,w,l}() macros + Patch by David Brownell, 10 Mar 2005 - Signed-off-by: Michal Simek +* Add Barco Streaming Video Card (SVC) and Sample Compress Network (SCN) board + Patch by Marc Leeman, 04 Mar 2005 -commit de2a07e534f18b1ca5f9869a4ef0604ca829cff0 -Author: Gururaja Hebbar K R -Date: Thu Jul 17 07:27:51 2008 +0530 +* OMAP242x H4 board update + - fix for ES2 differences. + - switch to using the cfi_flash driver. + - fix SRAM build address. + - fix for GP device operation. + - unlock SRAM for GP devices. + - display more device information. + - fix potential deadlock in omap24xx_i2c driver. + - fix DLL load values to match dpllout*1 operation. + - fix 2nd chip select init for combo DDR device. + - add support for CFI Intel 28F256L18 on H4 board. + Patch by Richard Woodruff, 03 Mar 2005 - Remove unused code from lib_arm/bootm.c +* Fix formating in include/asm-arm/arch-at91rm9200/AT91RM9200.h + Patch by Steven Scholz, 02 Mar 2005 - Signed-off-by: Gururaja Hebbar +* Fix typo in eth.c + Patch by Ara Avanesyan, 24 Feb 2005 -commit ffbb5cb942e9856fa24e946977e0a60c64df04ab -Author: Detlev Zundel -Date: Wed Jul 16 18:56:45 2008 +0200 +* Remove unneeded #include + Patch by Ladislav Michl, 22 Feb 2005 - tqm85xx: Demystify 'DK: !!!' comment +* Add cramfs support for m68k + Patch by Zachary Landau, 21 Feb 2005 - Signed-off-by: Detlev Zundel +* Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs + Patch by Jeff Angielski, 21 Feb 2005 -commit b2f44ba570f3a01113bbb745daf46f3858d22f53 -Author: Detlev Zundel -Date: Wed Jul 16 18:56:44 2008 +0200 +* Fix au1x00_serial baud rate calculation: + remove hardcoded cpu clock divisor and use register instead; + round up instead of truncate + Patch by Andrew Dyer, 15 Feb 2005 - 83xx/85xx/86xx: Add LTEDR local bus definitions +* Add Xilinx Spartan3 family FPGA support + Patch by Kurt Stremerch, 14 Feb 2005 - Signed-off-by: Detlev Zundel +* Fix drivers/cfi_flash.c: use info->reset_cmd instead of FLASH_CMD_RESET + Patch by Zachary Landau, 11 Feb 2005 -commit f13f64cf42d5abec3e0f920233f6a7a61e7ae494 -Author: Ricardo Ribalda Delgado -Date: Wed Jul 16 16:22:32 2008 +0200 +* Fix VOH405 Support + Patch by Matthias Fuchs, 25 Sep 2005 - serial_xuartlite.c: fix compiler warnings +* Added support for PCI bridge on MPC8272ADS + Patch by Vitaly Bordug, Feb 09 2005 - Signed-off-by: Ricardo Ribalda Delgado - Acked-by: Grant Likely +* Update multicore CM9XX support for Integrator AP to allow booting from flash + Patch by Jean-Paul Saman, 8 Feb 2005 -commit 86446d3a5d9d3ca81e85d1ccd3accaaae6f8e3c9 -Author: Stefan Roese -Date: Fri Jul 18 11:03:35 2008 +0200 +* Fix strswab() to reliably find end of string + Patch by Andrew Dyer, 08 Feb 2005 - POST: Add disable interrupts in some of the missing CPU POST tests +* Fix typos in include/ppc440.h + Patch by Andrew E Mileski, 04 Feb 2005 - Some CPU POST tests did not disable the interrupts while running. This - seems to be necessary to protect this self modifying code. +* Add Vibren (was Accelent) PXA255 IDP Support + Patch by Cliff Brake, 04 Feb 2005 - Signed-off-by: Stefan Roese +* Fix tools/bmp_logo.c using incorrect offset to pixel data + Patch by Andrew Dyer, 31 Jan 2005 -commit 97a3bf268d096e0e97e54048448c35114edcf557 -Author: Stefan Roese -Date: Fri Jul 18 10:43:24 2008 +0200 +* Add ARM946E cpu and core module targets; remap memory to 0x00000000 + Patch by Peter Pearse, 2 Feb 2005 - ide: Use CFG_64BIT_LBA instead of CFG_64BIT_STRTOUL +* Fix error handling in tools/env/fw_env.c + Patch by Ara Avanesyan, 01 Feb 2005 - This is needed for boards that define CFG_64BIT_STRTOUL but don't define - CFG_64BIT_LBA. +* Fix MGT5100 PSC baudrate calculation + Patch by Sebastian Schau, 27 Jan 2005 - Signed-off-by: Stefan Roese +* OMAP242x fix for GP device booting + - Add SRAM unlock for GP devices. + - Change DDR DLL unlock value to allow DPLLout*1 operation. + Patches by Richard Woodruff, 21 Jan 2005: -commit 0043ac55024963295fc79b39af85b6dc3b261e17 -Author: Niklaus Giger -Date: Fri Jul 18 11:22:23 2008 +0200 +* Add support for AMD's Pb1x00 eval board; + add MII routines to the au1x00 ethernet driver; + add USB ohci driver (work in progress) + Patch by Thomas Sailer, 20 Jan 2005 - POST PPC4xx/spr IVPR only if PPC440 +* Update omap5912osk board + Use drivers/cfi_flash.c instead of private flash driver; + Remove hardcoded personalized settings from omap5912osk.h; + Fix spacing with (RO) marks in 'flinfo' output. + Patch by Michael Bendzick, 14 Jan 2005 - The SPR IVPR register is only present (as far as I know) for - processors with a PPC440 core. +* Fix warnings for PCI code on ixp + Patch by Joe , 13 Jan 2005 - Signed-off-by: Niklaus Giger - Acked-by: Stefan Roese +* virtex2 fix for bogus download error messages + The virtex2 FPGA download code watches for init going active during + a download of config data as an error condition. init also goes + active after a configuration is finished in concert with the done + signal. So far, the code does not check for done active until all + of the configuration data is sent. If configuration data has a few + extra pad bytes at the end, this would cause an error message even + though the download had suceeded. + NOTE: virtex2 slave serial and spartan2 versions may still have the + same problem. + Patch by Andrew Dyer, 12 Jan 2005 -commit 1092fbd64748dfa2e979b102611ece9bc5ec1855 -Author: Stefan Roese -Date: Fri Jul 18 10:42:29 2008 +0200 +* Optimize flash_make_cmd in drivers/cfi_flash.c for little endian + Fix "WARNING: flash_make_cmd: unsuppported LittleEndian mode" + message when probing for nonexistent flash in little endian mode. + As a side effect more efficient and smaller code is generated, + which is always a Good Thing (TM). + Patch by Ladislav Michl, 24 Sep 2005 - ppc4xx: Enable 64bit printf format on 440/460 platforms +* Update for TFTP using a fixed UDP port + Use the approved environment variable names. Added "tftpdstp" to + allow ports other than 69 per Tolunay Orkun's recommendation. + Patch by Jerry Van Baren, 12 Jan 2005 - This patch defines CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL for all - 440/460 platforms. This may be needed since those platforms support - 36bit physical address space. +* Allow to force TFTP to use a fixed UDP port + (Add a configuration option CONFIG_TFTP_PORT and optional env + variable tftpport) + Patch by Jerry Van Baren, 10 Jan 2005 - Signed-off-by: Stefan Roese +* Fix ethernet timeouts on dbau1550 and other au1x00 systems + Patch by Leif Lindholm, 29 Dec 2004 -commit 66fe183b1dd9c7534605147a8ecfed1c02345ee5 -Author: Stefan Roese -Date: Fri Jul 18 15:57:23 2008 +0200 +* Cleanup: fix broken builds - ppc4xx: Fix incorrect MODTx setup for some DIMM configurations +* Fix PHY address argument passing with mii info command + Patch by Andrew Dyer, 28 Dec 2004 - This patch fixes a problem with incorrect MODTx (On Die Termination) - setup for a configuration with multiple DIMM's and multiple ranks. - Without this change Katmai was unable to boot Linux with DDR2 frequency - >= 533MHz and mem>=3GB. With this patch Katmai successfully boots Linux - with DDR2 frequency = 640MHz and mem=4GB. +* Cleanup (PPC4xx is AMCC now) - Signed-off-by: Stefan Roese +* esd CPCI2DP board added + Patch by Matthias Fuchs, 22 Sep 2005 -commit 340ccb260f21516be360745d5c5e3bd0657698df -Author: Sebastian Siewior -Date: Wed Jul 16 20:04:49 2008 +0200 +* esd PMC405 board updated + Patch by Matthias Fuchs, 22 Sep 2005 - cfi_flash: fix flash on BE machines with CFG_WRITE_SWAPPED_DATA +* Add SM501 support to HH405 board. + Add support for gzip compressed bmp's (CONFIG_VIDEO_BMP_GZIP). + Add support for eeprom write-enable (CFG_EEPROM_WREN). + Patch by Stefan Roese, 22 Sep 2005 - This got broken by commits 93c56f212c - [cfi_flash: support of long cmd in U-boot.] +* Fix autonegotiation in tsec ethernet driver + Patch by Stefan Roese, 21 Sep 2005 - That command needs to be in little endian format on BE machines - with CFG_WRITE_SWAPPED_DATA. Without this patch, the command 0xf0 - gets saved on stack as 0x00 00 00 f0 and 0x00 gets written into - the cmdbuf in case portwidth = chipwidth = 8bit. +* Fix bug in auto_update (trab board) + Patch by Martin Krause, 16 Sep 2005 - Cc: Alexey Korolev - Cc: Vasiliy Leonenko - Signed-off-by: Sebastian Siewior +* Fix computation of framebuffer palette for 8bpp LCD bitmaps + Patch by Francesco Mandracci, 16 Sep 2005 -commit 699f05125509249072a0b865c8d35520d97cd501 -Author: Wolfgang Denk -Date: Tue Jul 15 22:22:44 2008 +0200 +* Update configuration for INKA4x0 board - Prepare v1.3.4-rc1: Code cleanup, update CHANGELOG, sort Makefile +* Update configuration for PM854 board + Based on patch by R. Loeffl, 20 Jul 2005 - Signed-off-by: Wolfgang Denk +* Add PCI support to TQM8540 and TQM8560 boards + Patch by Stefan Roese, 15 Sep 2005 -commit bcab74baa6b1b1c969038ab6f64a186239180405 -Author: Hugo Villeneuve -Date: Tue Jul 15 11:23:02 2008 -0400 +* Update AMCC Yosemite to get a consistent setup for all AMCC eval + boards (baudrate, environment...). Flash driver fixed. + Patch by Stefan Roese, 15 Sep 2005 - Round the serial port clock divisor value returned by calc_divisor() +* Fix problem in 440GP ethernet driver (ebony). Add support for 2nd + ethernet port on ebony. + Patch by Stefan Roese, 7 Sep 2005 - Round the serial port clock divisor value returned by - calc_divisor() +* Added support for mtddevnum and mtddevname variables (mtdparts command) - Signed-off-by: Hugo Villeneuve - Acked-by: Gerald Van Baren +* Change default console baud rate for stxxtc board -commit 0328ef0edfe950f0b7b8b368dae482531506b74a -Author: Robin Getz -Date: Tue Jul 15 21:44:46 2008 +0200 +* Add I2C support to TQM8540 and TQM8560 boards (EEPROM, RTC, LM75-DTT). + Patch by Stefan Roese, 31 Aug 2005 - Fix DHCP protocol so U-Boot does not respond too early - on the network with it's offered IP number; it should not reply until - after it has received a DHCP ACK message. Also ensures that U-Boot - does it's DHCPREQUEST as broadcast (per RFC 2131). +* Fix default command set (don't include CFG_CMD_DISPLAY command) + Patch by Pantelis Antoniou, 02 Sep 2005 - Signed-off-by: Robin Getz - Acked-by: Ben Warren - Signed-off-by: Wolfgang Denk +* Cleanup -commit 7288f972fcaee14a9741cb08c8688a23874b4a2e -Author: Sebastian Siewior -Date: Tue Jul 15 13:35:23 2008 +0200 +* Enable SM712 driver support for HMI1001 board. - cfi_flash: make the command u32 only +* Fix problems with ld version 2.16 (dot outside sections problem) + Pointed out by Gerhard Jaeger, 31 Aug 2005; + cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html - This got changed by commit 93c56f212c - [cfi_flash: support of long cmd in U-boot.] +* Prepare U-Boot for gcc-4.x: fix global data pointer initialization - Long is the wrong type because it will behave differently on 64bit - machines in a way that is probably not expected. u32 should be - enough. +* Adjust CS3 timings on HMI1001 board for dot matrix display under Linux - Cc: Alexey Korolev - Cc: Vasiliy Leonenko - Signed-off-by: Sebastian Siewior +* Add keyboard and dot matrix display support for HMI1001 board. -commit 31cfe57491b183acae575d486729e158f016c27b -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Jul 14 23:48:41 2008 +0200 +* Prepare U-Boot for gcc-4.x - tools/gitignore: update to all generated files +* Fixed Bamboo port to enable running without DDR-DIMM + (Bamboo has also 64MB onboard DDR) + Patch by Stefan Roese, 24 Aug 2005 - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c + now handling all 4xx cpu's + Patch by Stefan Roese, 16 Aug 2005 -commit 5e0de0e216b8fb27634afb11c60a2fa24c23349e -Author: Andre Schwarz -Date: Wed Jul 9 18:30:44 2008 +0200 +* Fix make dependencies for at91rm9200 and ks8695 cpus + Patch by Steven Scholz, 23 Aug 2005 - mpc5xxx: Add MVBC_P board support +* Add JFFS2 support for TQM5200 board - The MVBC_P is a MPC5200B based camera system with Intel Gigabit ethernet - controller (using e1000) and custom Altera Cyclone-II FPGA on PCI. +* Add esd cpci5200 and pf5200 boards + Patch by Reinhard Arlt, 22 Aug 2005 - Signed-off-by: Andre Schwarz - Signed-off-by: Grant Likely +* Fix sysclock for TQM8540 and TQM8560 boards + Patch by Martin Krause, 25 Jul 2005 -commit e2d31fb3450653115452144363d5bde4e5e3e693 -Author: Timur Tabi -Date: Thu Jun 19 17:56:11 2008 -0500 +* Initialize serial# and ethaddr from manufacturer data in EEPROM on CMC-PU2 + Patch by Martin Krause, 08 Jun 2005 - Update Freescale sys_eeprom.c to handle CCID formats +* Add new board specific commands for TQM5200/STK52XX + - Sound commands (beep, wav, sound) + - Test commands (led, can, backlight, rs232) + Patch by Martin Krause, 02 May 2005 - Update the sys_eeprom.c file to handle both NXID and CCID EEPROM formats. The - NXID format replaces the older CCID format, but it's important to support both - since most boards out there still use the CCID format. This change is in - preparation for using one file to handle both formats. This will also unify - EEPROM support for all Freescale 85xx and 86xx boards. +* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz + because of a bug in the AT91RM9200 CPU PLL + Patch by Martin Krause, 22 Apr 2005 - Also update the 86xx board header files to use the standard CFG_I2C_EEPROM_ADDR - instead of ID_EEPROM_ADDR. +* Add automatic HW detection for another CMC_PU2 variant + Patch by Martin Krause, 20 Apr 2005 - Signed-off-by: Timur Tabi +* Remove CONFIG_AT91RM9200DK in CMC-PU2 configuration + Patch by Martin Krause, 19 Apr 2005 -commit d85f46a25ccb33ed9b295de3c2cfe1ce270ece9a -Author: Nobuhiro Iwamatsu -Date: Fri Jul 11 17:22:43 2008 +0900 +* Fix initialization problem on TQM5200 without SM501 + Patch by Martin Krause, 08 Apr 2005 - pci: sh: Add pci_skip_dev and pci_print_dev function +* Add RTC support for STK52XX.200 + Patch by Martin Krause, 07 Apr 2005 - Add function of new PCI, pci_skip_dev and pci_print_dev. +* Add support for IFM o2dnt board - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu +* Enable PCI on hmi1001 board -commit 1107014e835ec9d46c0333f4211d104f77442db0 -Author: Andy Fleming -Date: Mon Jul 14 20:29:07 2008 -0500 +* Fix return values of the jffs2 commands ls/fsload/fsinfo, + so we can use them to, e.g., check the existence of a file with + "if ls foo; then this; else that; fi" in the hush shell + Patch by Andreas Engel, 16 August 2005 - Clean up INIT_RAM options +* Coding style cleanup - The L2_INIT_RAM option was unused, and recent changes to the TLB code - meant that the INIT_RAM TLBs weren't being cleared out. In order to reduce - the amount of mapped space attached to nothing, we change things so the TLBs - get cleared. +* Add support for Silicon Turnkey eXpress XTc (mpc87x/88x) board. + Patch by Dan Malek and Pantelis Antoniou, 15 Aug 2005 - Signed-off-by: Andy Fleming +* Check return value of malloc in 440gx_enet.c + Patch by Travis B. Sawyer, 18 Jul 2005 -commit 4524561820a9327e89107854b3a7187800ccf719 -Author: Andy Fleming -Date: Mon Jul 14 20:26:57 2008 -0500 +* Add Sandburst Metrobox and Sandburst Karef board support packages. + Second serial port on 440GX now defined as a system device. + Add 'Short Etch' code for Cicada PHY within 440gx_enet.c + Patch by Travis B. Sawyer, 12 Jul 2005 - Remove fake flash bank from 8544 DS +====================================================================== +Changes for U-Boot 1.1.3: +====================================================================== - The fake flash bank was generating errors for anyone who didn't have a - PromJET hooked up to the board. As that constitutes the vast majority of - users, we remove it. +* Minor code cleanup - Signed-off-by: Andy Fleming +* Add forgotten new fils from latest VoiceBlue update -commit 630d9bfcb5f6d3a43f251901a6b480994dcb6ea3 -Author: Kumar Gala -Date: Mon Jul 14 14:07:03 2008 -0500 +* Make bootretry feature work with hush shell. + Caveat: this currently *requires* CONFIG_RESET_TO_RETRY to be set, too. + Patch by Andreas Engel, 19 Jul 2005 - MPC8544DS: Add ATI Video card support +* Update Hymod Board Database PHP code in "tools" directory + Patch by Murray Jensen, 01 Jul 2005 - Add support for using a PCIe ATI Video card on PCIe2. +* Make "tr" command use POSIX compliant; export HOSTOS make variable + Patch by Murray Jensen, 30 Jun 2005 - Signed-off-by: Kumar Gala +* Fix Murray Jensen's mail address. + Patch by Murray Jensen, 30 Jun 2005 -commit 7f9f4347cf325c63a39fe30910f3fb211ae2cc15 -Author: Kumar Gala -Date: Mon Jul 14 14:07:02 2008 -0500 +* Preserve PHY_BMCR during a soft reset. + Patch by Carl Riechers, 24 Jun 2005 - 85xx: Add some L1/L2 SPR register definitions +* VoiceBlue update: eeprom tool can also store firmware version now. + eeprom.bin is runable by jumping at load address. + Patch by Ladislav Michl, 23 May 2005 - Add new L1/L2 SPRs related to e500mc cache config and control. +* Move the AT91RM9200DK to the ARM Systems list. + Patch by Anders Larsen, 26 Apr 2005 - Signed-off-by: Kumar Gala +* Eliminate calls of ARM libgcc.a helper functions _divsi3 and _modsi3 + Patch by Anders Larsen, 26 Apr 2005 -commit e5852787f0c3c442a276262f13d91ca450605ac0 -Author: Kumar Gala -Date: Mon Jul 14 14:07:01 2008 -0500 +* measure_gclk() is needed when DEBUG is enabled + Patch by Bryan O'Donoghue, 25 Apr 2005 - MPC8544DS: Report board id, board version and fpga version. +* Add UPD-Checksum code, fix problem in net.c (return instead of break) + Patch by Reinhard Arlt, 12 Aug 2005 - Signed-off-by: Kumar Gala +* esd PCI405 board updated + Patch by Matthias Fuchs, 28 Jul 2005 -commit 73f15a060f67a2462551c334215bd20fac6b81d1 -Author: Kumar Gala -Date: Mon Jul 14 14:07:00 2008 -0500 +* esd WUH405 and DU405 board updated + Patch by Matthias Fuchs, 27 Jul 2005 - 85xx: Cleanup L2 cache size detection +* Fix problem in cmd_nand.c (only when defined CFG_NAND_SKIP_BAD_DOT_I) + Patch by Matthias Fuchs, 4 May 2005 - The L2 size detection code was a bit confusing and we kept having to add - code to it to handle new processors. Change the sense of detection so we - look for the older processors that aren't changing. +* Update AMCC Yosemite to get a consistent setup for all AMCC eval + boards (baudrate, environment...). Flash driver fixed. + Patch by Stefan Roese, 11 Aug 2005 - Also added support for 1M cache size on 8572. +* Changed AMCC Bubinga (405EP) configuration to support 2nd eth port + Patch by Stefan Roese, 11 Aug 2005 - Signed-off-by: Kumar Gala +* Add NAND FLASH support for AMCC Bamboo 440EP eval board + Patch by Stefan Roese, 11 Aug 2005 -commit c3ca7e5e00a24451f20df3bded9a61ba541921df -Author: Paul Gortmaker -Date: Fri Jul 11 15:33:08 2008 -0400 +* Add configuration for IFM AEV FIFO board. + Minor coding style cleanup. - sbc8560: enable CONFIG_OF_LIBFDT by default +* Add configuration for IFM SPI eval board - Make the default build for the sbc8560 board be powerpc - capable with libfdt support. +* Fix CompactFlash problem on HMI1001 board - Signed-off-by: Paul Gortmaker +* Make new "mtdparts" code build with older compilers + Patch by Andrea Scian, 09 Aug 2005 -commit 6b44a44ec2aab180d7095c1c92e669cee1d3e3bd -Author: Andy Fleming -Date: Mon Jul 14 20:04:40 2008 -0500 +* Changed CONFIG_440_GX, CONFIG_440_EP and CONFIG_440_GR options to + CONFIG_44GX, CONFIG_440EP and CONFIG_440GR for a consistent design + with the 405 defines and the linux kernel defines. + Patch by Stefan Roese, 08 Aug 2005 - Fix indentation for default boot environment variables +* Fix compiler warnings with older GCC versions - This was proposed by Paul Gortmaker in response to Wolfgang's comments on - similar #defines in sbc8560.h. +* Add common (with Linux) MTD partition scheme and "mtdparts" command - Signed-off-by: Andy Fleming + Old, obsolete and duplicated code was cleaned up and replace by the + new partitioning method. There are two possible approaches now: -commit 37fef499104e28e0a83b02b85ca0d1fbe80d294a -Author: Paul Gortmaker -Date: Fri Jul 11 15:33:07 2008 -0400 + The first one is to define a single, static partition: - sbc8560: add default fdt values + #undef CONFIG_JFFS2_CMDLINE + #define CONFIG_JFFS2_DEV "nor0" + #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */ + #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */ + #define CONFIG_JFFS2_PART_OFFSET 0x00000000 - Add in the default fdt settings and the typical EXTRA_ENV - settings as borrowed from the mpc8560ads. Fix a couple - of stale references to the mpc8560ads dating back to the - original clone/fork. + The second method uses the mtdparts command line option and dynamic + partitioning: - Signed-off-by: Paul Gortmaker - Signed-off-by: Andy Fleming + /* mtdparts command line support */ + #define CONFIG_JFFS2_CMDLINE + #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" + #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" -commit d04e76edf92f7f89696989e8702b97e020455af3 -Author: Paul Gortmaker -Date: Fri Jul 11 15:33:06 2008 -0400 + Command line of course produces bigger images, and may be inappropriate + for some targets, so by default it's off. - sbc8560: add in ft_board_setup() +* Fix build problems for PM856 Board - Add in for the sbc8560, the ft_board_setup() routine, based on what is - in use for the Freescale MPC8560ADS board. +* Fix sign extension bug in 'fpga loadb' command; + make 'fpga loadb' always print the file header info + Patch by Andrew Dyer, 11 Jan 2005 - Signed-off-by: Paul Gortmaker +* Fix errors that occur when accessing SystemACE CF + Patch by Jeff Angielski, 09 Jan 2005 -commit c158bcaca3b31cbe38c4143812e6170e38a57393 -Author: Paul Gortmaker -Date: Fri Jul 11 15:33:05 2008 -0400 +* Document switching between U-Boot and PlanetCore on RPXlite + by Sam Song, 24 Dec 2004 - sbc8560: define eth0 and eth1 instead of eth1 and eth2 +* Fix PowerQUICC II mask detection. + Patch by Eugene Surovegin, 20 Dec 2004 - The existing config doesn't define CONFIG_HAS_ETH0, and so the - fdt support doesn't update the zeros in the dtb local-mac with - real data from the u-boot env. Since the existing config is - tailored to just two interfaces, get rid of the ETH2 definitions - at the same time. +* Add support for Altera NIOS DK1C20 board + Patch by Shlomo Kut, 13 Dec 2004 - Also don't include any end user specific data into the environment - by default -- things like MAC address, network parameters etc. need - to come from the end user. +* Add support for ep8248 board + Patch by Yuli Barcohen, 12 Dec 2004 - Signed-off-by: Paul Gortmaker - Signed-off-by: Andy Fleming + Minor code cleanup. -commit 0ec436d2f95076d9e46ae594db6e9b1d8732840d -Author: Paul Gortmaker -Date: Fri Jul 11 15:33:04 2008 -0400 +* Fix baudrate setting for KGDB on MPC8260 + Patch by HoJin, 11 Dec 2004 - sbc8560: properly set cs0_bnds for 512MB +* Fix 'mii help' text formatting + Patch by Cory Tusar, 10 Dec 2004 - The sbc8560 board ships with 512MB of memory installed, - but the current cs0_bnds is hard coded for 256MB. Set the - value based on CFG_SDRAM_SIZE. +* Fix return code of NFS command + Patch by Hiroshi Ito, 11 Dec 2004 - Signed-off-by: Paul Gortmaker +* Fix typo -commit 6de5bf24004c8d9c9b070bb8f7418d1c45e5eb27 -Author: Paul Gortmaker -Date: Fri Jul 11 15:33:03 2008 -0400 +* Fix compiler warnings in cpu/ppc4xx/usbdev.c + Patch by Steven Blakeslee, 04 Aug 2005 - sbc8560: proper definitions for TSEC. +* Add support for AMCC Bamboo PPC440EP eval board + Patch by Stefan Roese, 04 Aug 2005 - The definitions for the TSEC have become out of date. There is no - longer any such options like "CONFIG_MPC85xx_TSEC1" or similar. - Update to match those of other boards, like the MPC8560ADS. +* Patch by Jon Loeliger + Fix style issues primarily in 85xx and 83xx boards. + - C++ comments + - Trailing white space + - Indentation not by TAB + - Excessive amount of empty lines + - Trailing empty lines - Signed-off-by: Paul Gortmaker - Acked-by: Ben Warren +* Patch by Ron Alder, 11 Jul 2005 + Add Xianghua Xiao and Lunsheng Wang's support for the + GDA MPC8540 EVAL board. -commit 71074abbe0c76429577aff58aeff0a24ad210b23 -Author: Paul Gortmaker -Date: Wed Jul 9 13:23:05 2008 -0400 +* Patch by Eran Liberty + Add support for the Freescale MPC8349ADS board. - 8xxx-fdt: set ns16550 clock from CFG_NS16550_CLK, not bi_busfreq +* Patch by Jon Loeliger, 25 Jul 2005 + Move the TSEC driver out of cpu/mpc85xx as it will be shared + by the upcoming mpc83xx family as well. - Some boards that have external 16550 UARTs don't have a direct - tie between bi_busfreq and the clock used for the UARTs. Boards - that do have such a tie should set CFG_NS16550_CLK to be - get_bus_freq(0) -- which most of them do already. +* Patch by Jon Loeliger, 05 May 2005 + Implemented support for MPC8548CDS board. + Added DDR II support based on SPD values for MPC85xx boards. + This roll-up patch also includes bugfies for the previously + published patches: + DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O - Signed-off-by: Paul Gortmaker - Acked-by: Kim Phillips +* Patch by Jon Loeliger, 10 Feb 2005 + Add config option CONFIG_HAS_FEC calling out 8540 FEC features. -commit 24ef76f320fbadf074105229826514db140f939f -Author: Andrew Klossner -Date: Wed Jul 2 07:03:53 2008 -0700 +* Patch by Jon Loeliger, Kumar Gala, 08 Feb 2005 + For MPC85xxCDS: + Adds Relaxed Timing TRLX bit to FLASH ORx regs to allow + for faster flash parts. + Add documentation for BR/OR for FLASH. - Change the temp map to ROM to align addresses to page size. +* Patch by Jon Loeliger 08 Feb 2005 + Determine L2 Cache size dynamically on 85XX boards. - With a page size of BOOKE_PAGESZ_16M, both the real and effective - addresses must be multiples of 16MB. The hardware silently truncates - them so the code happens to work. This patch clarifies the situation - by establishing addresses that the hardware doesn't need to truncate. +* Patch by Jon Loeliger, Kumar Gala 08 Feb 2005 + - Convert the CPM2 based functionality to use new CONFIG_CPM2 + option rather than a myriad of CONFIG_MPC8560-like variants. + Applies to MPC85xx and MPC8260 boards, includes stxgp3 and sbc8560. + Eliminates the CONFIG_MPC8560 option entirely. Distributes the + new CONFIG_CPM2 option to each 8260 board. - Signed-off-by: Andrew Klossner - Signed-off-by: Andy Fleming +* Add support for MicroSys PM856 board + Patch by Josef Wagner, 03 Aug 2005 -commit 06b4186c10204b6683edb047ac5f506fb0ce0937 -Author: Kim Phillips -Date: Tue Jun 17 17:45:22 2008 -0500 +* Minor fixes to PM854 board + Patch by Josef Wagner, 03 Aug 2005 - mpc85xx: use IS_E_PROCESSOR macro +* Adjust configuration of XENIAX board + (chip select and GPIO required for USB operation) - Signed-off-by: Kim Phillips +* Fix typos in cpu/85xx/start.S which caused DataTLB exception to be + routed to the Watchdog handler + Patch by Eugene Surovegin, 18 Jun 2005 -commit 6b70ffb9d1b2e791161f3cf92937aa45b4a07b78 -Author: Kim Phillips -Date: Mon Jun 16 15:55:53 2008 -0500 +* (re)enabled scsi commands do_scsi() and do_scsiboot() + Patch by Denis Peter, 06 Dec 2004 - fdt: add crypto node handling for MPC8{3, 5}xxE processors +* Fix endianess problem in TFTP / NFS default filenames + Patch by Hiroshi Ito, 06 Dec 2004 - Delete the crypto node if not on an E-processor. If on 8360 or 834x family, - check rev and up-rev crypto node (to SEC rev. 2.4 property values) - if on an 'EA' processor, e.g. MPC8349EA. +* Ignore broadcast status bit in received frames in 8260 FCC ethernet + loopback test code + Patch by Murray Jensen, 18 Jul 2005 - Signed-off-by: Kim Phillips +* Fix typo in mkconfig script (used == instead of =) + Patch by Murray Jensen, 18 Jul 2005 -commit 85e5808e8ea9f77da5219f23394112f0b424fa5e -Author: Hugo Villeneuve -Date: Fri Jul 11 15:10:11 2008 -0400 +* Cleanup build problems on 64 bit build hosts - ARM DaVinci: Remove extern phy_t declaration by moving code to proper place +* Update MAINTAINERS file - ARM DaVinci: Remove extern phy_t declaration by moving - code to proper place. +* Patch by Stefan Roese, 01 Aug 2005: + - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea + (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup" + for details. + - Sycamore (PPC405GPr) eval board added (Walnut port is extended + to run on both 405GP and 405GPr eval boards). - Signed-off-by: Hugo Villeneuve +* Patch by Steven Blakeslee, 27 Jul 2005: + - Add support for AMCC PPC440EP/GR. + - Add support for AMCC Yosemite PPC440EP eval board. + - Add support for AMCC Yellowstone PPC440GR eval board. -commit 3a9e7ba2ac14018c5dd1e78a7dd735571569c971 -Author: Hugo Villeneuve -Date: Fri Jul 11 15:10:10 2008 -0400 +* Minor fixes for PPChameleon Board: + - fix alignment of NAND size + - make code do what the comment says - ARM DaVinci: Remove duplicate definitions of MACH_TYPE and prototype of i2c_init() +* Implement h/w sector protection status synchronization at boot. + The code is provided for, and was tested on, the Yukon/Alaska + and PM520 boards only. - ARM DaVinci: Remove duplicate definitions of MACH_TYPE - and prototype of i2c_init(). + A bug in flash_real_protect() for the Yukon board was fixed by + adding a function that tells if two banks are on one flash chip. - Signed-off-by: Hugo Villeneuve +* Fix sysmon POST problem: check I2C error codes + This fixes a problem of displaying bogus voltages when the voltages + are so low that the I2C devices start failing while the rest of the + system keeps running. -commit 348753d416cd2c9e7ec6520a544c8f33cf02a560 -Author: Kumar Gala -Date: Mon Jul 14 14:03:02 2008 -0500 +* Patch by Cedric Vincent, 6 Jul 2005: + Fix CFG_CMD_SETGETDCR handling in "common/cmd_dcr.c" - Fix some more printf() format problems. +* Patch by Jon Loeliger, 20 Jul 2005: + Add missing PCI IO port definitions. - Signed-off-by: Kumar Gala +* Add CompactFlash support for HMI1001 board. -commit 45b16d22c64674ccd8c4637456a987463609141c -Author: Wolfgang Denk -Date: Mon Jul 14 22:38:42 2008 +0200 +* Adjust printed board ID for LWMON board. - Fix coding style; make code better parsable by external tools +* Fix low-level OHCI transfers for ARM920t and MPC5xxx - Signed-off-by: Wolfgang Denk +* Add new argument format for flash commands to allow for usage like + "erase $(addr) +$(filesize)", i. e. a size argument can be used and + U-Boot will automaticially find the end of the corresponding sector. -commit b880cbf207b1c109d3a661417a8feddcbd729a9d -Author: Wolfgang Denk -Date: Mon Jul 14 21:19:08 2008 +0200 +* Patch by Stefan Roese, 5 Jul 2005: + Update uc100 board PHY setup - cpu/i386/serial.c: Fix syntax errors +* Patch by Stefan Roese, 1 Jul 2005: + Fix PHY address for CATcenter board (now correct!) - Signed-off-by: Wolfgang Denk +* Patch by Stefan Roese, 30 Jun 2005: + Fix PHY addresses for PPChameleon and CATcenter boards + Change MAINTAINER for most esd boards -commit e2d45e6f4d9919e1afeac5e09557b2252832fccf -Author: Wolfgang Denk -Date: Mon Jul 14 20:41:35 2008 +0200 +* Patch by Detlev Zundel, 30 Jun 2005: + Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code - elppc board: Coding style cleanup. +* Fix baudrate calculation problem on MPC5200 systems - Signed-off-by: Wolfgang Denk +* Add EEPROM and RTC support for HMI1001 board -commit 82b24a8a505fc81466484b3c55b574ee0b4205bc -Author: Wolfgang Denk -Date: Mon Jul 14 20:40:22 2008 +0200 +* Patch by Detlev Zundel, 20 Jun 2005: + Fix initialization of low active GPIO pins on inka4x0 board - elppc board: fix syntax error. +* Enable redundant environment, disable HW flash protection of + HMI1001 board - Signed-off-by: Wolfgang Denk +* Patch by Travis Sawyer, 10 Jun 2005: + Initialize allocated dev and private hw structures + after their respective allocation in 440gx_enet.c -commit 0fe340585a6a48bd392d315b0dd84d068b1c3790 -Author: Wolfgang Denk -Date: Mon Jul 14 20:38:26 2008 +0200 +* Patch by Steven Scholz, 10 Jun 2005: + Fix byteorder problems with second argument of "bootm" with + standalone images; - EB+MCF-EV123 board: fix coding style (alingment) +* Add support for HMI1001 board - Signed-off-by: Wolfgang Denk +* Disable "date" and "sntp" commands on TQM866M -commit 6841785a0bb0f38175456a923edd634fb7dd6947 -Author: Wolfgang Denk -Date: Mon Jul 14 20:36:44 2008 +0200 +* Fix watchdog reset problems on LWMON board - EB+MCF-EV123 board: fix syntx error +* Patch by Juergen Selent, 17 May 2005: + Add support for Funkwerk VoVPN gateway module. - Signed-off-by: Wolfgang Denk +* Cleanup debug code for MPC8220 FEC driver -commit ab5cda9f88c3eaf9cf599adc3a3375906c4ed904 -Author: Andy Fleming -Date: Mon Jul 7 18:02:08 2008 -0500 +* Extend burst mode RAM test program to take a loop count + (0 = infinite) - Remove LBC_CACHE_BASE from 8544 DS +* Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on + those boards that use it. - The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping - space for some anyway, we were allowing speculative loads into unmapped space, - which would cause an exception (annoying, even if ultimately harmless). - Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the - problem. +* Patches by Greg Ungerer, 19 May 2005: + - add support for the KS8695P (ARM 922 based) CPU + - add support for the OpenGear CM4008, CM4116 and CM4148 boards - Signed-off-by: Andy Fleming +* Patch by Steven Scholz, 19 May 2005: + Add support for CONFIG_SERIAL_TAG on ARM boards -commit d0ff51ba5d0309dbe9e25ea54f8a0285a6d5db90 -Author: Wolfgang Denk -Date: Mon Jul 14 15:19:07 2008 +0200 +* Add PCI support for Sorcery board. + Code cleanup (especially Sorcery / Alaska / Yukon serial driver). - Code cleanup: fix old style assignment ambiguities like "=-" etc. +* Fix compile problems caused by new burst mode SDRAM test; + make port pins to trigger logic analyzer configurable - Signed-off-by: Wolfgang Denk +* Fix timer handling on MPC85xx systems -commit d7854223c5c85b5849fbf422cc8ac0efef461c37 -Author: Wolfgang Denk -Date: Mon Jul 14 15:10:53 2008 +0200 +* Fix debug code in omap5912osk flash driver - AmigaOneG3SE: remove dead and incomplete files +* Add support for MPC8247 based "IDS8247" board. - Signed-off-by: Wolfgang Denk +* Add support for 2 x TSEC interfaces on the TQM8540 board. -commit b64f190b7a34224df09b559ca111eb1b733f00ad -Author: Wolfgang Denk -Date: Mon Jul 14 15:06:35 2008 +0200 +* On LWMON we must use the watchdog to reset the board as the CPU + genereated HRESET pulse is too short to reset the external + circuitry. - Fix printf() format issues with sizeof_t types by using %zu +* Add test tool to exercise SDRAM accesses in burst mode + (as standalone program, MPC8xx/PowerPC only) - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Wolfgang Denk +* Increase CFG_MONITOR_LEN for Rattler board to match actual code + size. -commit f354b73e16a86f9e9085471a830605f74f84ea5d -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Jul 14 14:11:45 2008 +0200 +* Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of + March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI + added to support LZO and LZARI compression modes (undefined by + default). - vsprintf: add z and t options +* Fix problem with symbolic links in JFFS2 code. - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Use linker ASSERT statement to prevent undetected overlapping of + sections on PPChameleon board; other boards might use this, too. -commit 25dbe98abb686d8210e1731fba85ced7d3ce874c -Author: Wolfgang Denk -Date: Sun Jul 13 23:07:35 2008 +0200 +* Patch by Stefan Roese, 03 May 2005: + Update for P3G4 + Fix problems in cmd_universe.c - Fix some more printf() format issues. +* Patch by Matthias Fuchs, 03 May 2005: + Added missing variable declaration in cmd_nand.c + Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram - Signed-off-by: Wolfgang Denk +* Fix INKA4x0: use CS1 as gpio_wkup_6 output -commit d5996dd555edf52721b7691a4c59de016251ed39 -Author: Wolfgang Denk -Date: Sun Jul 13 19:51:00 2008 +0200 +* Fix bug in the SDRAM initialization code for canmb, IceCube and + PM520 boards. + Fix PHY address for canmb board. - Fix some more printf() format problems. +* Cleanup serial console baudrate calculation on AT91RM9200; + get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition - Signed-off-by: Wolfgang Denk +* Patch by Matthias Fuchs, 18 Apr 2005: + Make PCI target address spaces on PMC405 and CPCI405 boards + configurable via environment variables -commit 0f9d5f6d6e814907794995c6a22af752040c35d9 -Author: Wolfgang Denk -Date: Sun Jul 13 19:48:26 2008 +0200 +* Auto-size RAM on canmb board. - ADS5121: Fix (delete) incorrect ads5121_diu_init() prototype +* Add support for canmb board - Signed-off-by: Wolfgang Denk +* Patch by Stefan Roese, 13 Apr 2005: + Update for esd apc405 -commit 322716a1d1eb33a71067ba0eb1c5346fb2dd6b34 -Author: Anatolij Gustschin -Date: Sat Jul 12 17:31:36 2008 +0200 +* Fixes for TQM8560 board: + - fix clock rates + - remove debug messages + - fix flash sector protection - Fix bug in Lime video driver +* Patch by Steven Scholz, 07 Apr 2005: + Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C - We need to wait while drawing engine clears frame - buffer before any further software accesses to frame - buffer will be initiated. Otherwise software drawn - parts could be partially destroyed by the drawing - engine or even GDC chip freeze could occur (as - observed on socrates board). +* Patches by Steven Scholz, 07 Apr 2005: + Fix compiler warning in altera.c + Fix warning in cpu/arm920t/at91rm9200/i2c.c - Signed-off-by: Anatolij Gustschin +* Patch by Ladislav Michl, 06 Apr 2005: + Fix voiceblue configuration. -commit 0a5676befb0c590212a53f7627fa5d0d8a84bf34 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Jul 12 14:36:34 2008 +0200 +* Patch by Stefan Roese, 06 Apr 2005: + Updates for OCOTEA board: + - Changed U-Boot size from 512kByte to 256kByte + - Fixed flash driver to support boot from soldered user flash + - Added README for switch from PIBS firmware to U-Boot - Fix some more printf() format issues. +* Patch by Travis Sawyer, 05 Apr 2005: + - Change timer frequency for ppc 440 from 10 ms to 1 ms. + Problem found by Andrew Wozniak. - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Patch by Steven Scholz, 06 Apr 2005: + - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200 + - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200 -commit 18c8a28aad49803780bd8d52432ded528e37e701 -Author: Michal Simek -Date: Fri Jul 11 15:11:57 2008 +0200 +* Patches by Robert Whaley, 29 Nov 2004: + - update the pxa-regs.h file for PXA27x chips + - add PXA27x based ADSVIX board + - add support for MMC on PXA27x processors - hwmon: rename CONFIG_DS1722 to CONFIG_DTT_DS1722 +* Patch by Andrew E. Mileski, 28 Nov 2004: + Fix PPC4xx SPD SDRAM detection bug - Signed-off-by: Michal Simek - Acked-by: Stefan Roese +* Patch by Hiroshi Ito, 26 Nov 2004: + Fix logic of "test -z" and "test -n" commands -commit 6ecbb45bb027e90c19d63b48e7b0c05acc1a87c0 -Author: Michal Simek -Date: Fri Jul 11 11:50:53 2008 +0200 +* Patch by Ladislav Michl, 05 Apr 2005: + Add support for VoiceBlue board. - hwmon: Cleaning hwmon devices +* Patch by Ladislav Michl, 05 Apr 2005: + Fix netboot_common() prototypes. - Clean Makefile - Move device specific values to driver for better reading +* Patch by Steven Scholz, 05 Apr 2005: + Use i.MX watchdog timer for reset_cpu() - Signed-off-by: Michal Simek - Acked-by: Stefan Roese +* Patch by Steven Scholz, 05 Apr 2005: + Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific + subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/ + (now in interupts.c) -commit c78fce699c7ff467ecd841da6a79f065180bf578 -Author: Michal Simek -Date: Fri Jul 11 10:43:13 2008 +0200 +* Add support for MPC8220 based "sorcery" board. - FIS: repare incorrect return value with ramdisk handling +* Add support for TQM8560 board. - Microblaze and PowerPC use boot_get_ramdisk for loading - ramdisk to memory with checking return value. - Return 0 means success. Return 1 means failed. - Here is correspond part of code from bootm.c which check - return code. +* Add FEC support for TQM8540 board. + Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC - ret = boot_get_ramdisk (argc, argv, images, IH_ARCH_PPC, - &rd_data_start, &rd_data_end); - if (ret) - goto error; +* Patch by Martin Krause, 04 Apr 2005: + Update default configuration for CMC_PU2 board. - Signed-off-by: Michal Simek +* Patch by Steven Scholz, 04 Apr 2005: + - remove all references to CONFIG_INIT_CRITICAL for ARM based boards + - introduce two new configuration options instead: + CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT -commit 84a2c64a26dc5e275e1cf4e76a6e194a18fb5477 -Author: Michal Simek -Date: Fri Jul 11 10:10:32 2008 +0200 +* Patch by Steven Scholz, 04 Apr 2005: + Make sure that MDIO clock does not exceed 2.5 MHz on AT91 - microblaze: Remove useless ancient headers +* Fix timer code for ARM systems: make sure that udelay() does not + reset timers so it's save to use udelay() in timeout code. - Signed-off-by: Michal Simek +* Patch by Mathias Küster, 23 Nov 2004: + add udelay support for the mcf5282 cpu -commit 53ea981c3124b13c137c2d10e975b7c6672266e0 -Author: Michal Simek -Date: Fri Jul 11 10:10:31 2008 +0200 +* Patch by Tolunay Orkun, 16 November 2004: + fix incorrect onboard Xilinx CPLD base address - microblaze: Clean uartlite driver +* Patch by Jerry Van Baren, 08 Nov 2004: + - Add low-boot option for MPC8260ADS board (if lowboot is selected, + the jumper for the HRCW source should select flash. If lowboot is + not selected, the jumper for the HRCW source should select the + BCSR. + - change default load base address to 0x00400000 - Redesign uartlite driver to in_be32 and out_be32 macros - Fix missing header in io.h +* Patch by Yuli Barcohen, 08 Nov 2004: + Add support for Analogue & Micro Rattler boards. + Tested on Rattler8248. - Signed-off-by: Michal Simek - Acked-by: Grant Likely +* Patch by Andre Renaud, 08 Nov 2004: + Fix watchdog support in common/lcd.c -commit dbf3dfb386a2d5d2381814e39985ab2e21894550 -Author: Marcel Ziswiler -Date: Fri Jul 11 02:39:14 2008 +0200 +* Patch by Marc Leeman, 05 Nov 2003: + Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU + bug only affects the XPC8245 processors - Enable passing of ATAGs required by latest Linux kernel. +* Patches by Josef Wagner, 29 Oct 2004: + - Add support for MicroSys CPU87 board + - Add support for MicroSys PM854 board -commit ef130d3093bdf88f01cf3e000fe5df249ebf2b1a -Author: Hugo Villeneuve -Date: Fri Jul 11 10:24:15 2008 -0400 +* Patch by Jian Zhang, 02 Nov 2004: + Add 16-bit NAND support - Fix integer overflow warning in calc_divisor() +* Patch by Scott McNutt, 01 Nov 2004: + Add missing NIOS/NIOS2 support for "iminfo" command - which happened when rounding the serial port clock divisor +* Patch by Detlev Zundel, 29 Oct 2004: + Add missing NIOS/NIOS2 support for "mkimage" tool. - Signed-off-by: Hugo Villeneuve +* Patch by David Adair, 27 Oct 2004: + Add missing 440GX SDRAM Controller reset -commit 6b760189d77f001684e3160b355c185ca3804961 -Author: Marcel Ziswiler -Date: Fri Jul 11 01:09:59 2008 +0200 +* Patch by Steven Scholz, 25 Oct 2004: + Declare reset_cpu() in include/common.h instead locally - Fix build time warnings in function mmc_decode_csd() +* Patch by Yusdi Santoso, 22 Oct 2004: + - Add support for HIDDEN_DRAGON board + - fix endianess problem in driver/rtl1839.c - Signed-off-by: Marcel Ziswiler +* Patch by Allen Curtis, 21 Oct 2004: + support multiple serial ports -commit c15947d6ce0d59925c97fdfac692476af6e262d0 -Author: Hugo Villeneuve -Date: Thu Jul 10 10:46:33 2008 -0400 +* Patch by Richard Klingler, 03 Apr 2005: + Add call to eth_halt() in net/net.c when called functions fail + after eth_init() has been called. - ARM: Fix for broken compilation when defining CONFIG_CMD_ELF +* Patch by Sam Song, 3 April 2005: + - Update README.Netconsole + - Update README - caused by missing dcache status/enable/disable functions. +* Prepare for SoC rework of ARM code: + - rename CONFIG_BOOTBINFUNC into CONFIG_INIT_CRITICAL + - rename memsetup into lowlevel_init (function name and source files) + Patch by Steven Scholz, 03 Apr 2005: + - create SoC specific directories include/asm-arm/arch-imx and + include/asm-arm/arch-s3c24x0 - Signed-off-by: Hugo Villeneuve +* Fix problems with SNTP support; + enable SNTP support in some boards. -commit 068c1b77c8f42a1a31084d2f4b1d5cc807c1a9ce -Author: Stefan Roese -Date: Thu Jul 10 13:53:31 2008 +0200 +* Patches by Martin Krause, 01 Apr 2005: + - Fix flash erase timeout on CMC_PU2 + - Add automatic HW detection for CMC_PU2 and CMC_BASIC - ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boards +* Patch by Steven Scholz, 13 March 2005: + fix cache enabling for AT91RM9200 - This patch removes some ft_board_setup() functions from some 4xx boards. - This can be done since we now have a default weak implementation for this - in cpu/ppc4xx/fdt.c. Only board in need for a different/custom - implementation like canyonlands need their own version. +* Patch by Masami Komiya, 30 Mar 2005: + add SNTP support and expand time server and time offset fields of + DHCP support. See doc/README.SNTP - Signed-off-by: Stefan Roese +* Patch by Steven Scholz, 13 Dec 2004: + Fix bug in at91rm920 ethernet driver -commit d39a089f8bc960ba9ae6a08fda5582b578620cc1 -Author: Wolfgang Denk -Date: Sun Jul 13 14:58:16 2008 +0200 +* Patch by Steven Scholz, 13 Dec 2004: + Remove duplicated code by merging memsetup.S files for + at91rm9200 boards into one cpu/at91rm9200/lowlevel.S - Add last known maintainer for orphaned boards; reformat. +* Patch by Detlev Zundel, 31 Mar 2005: + Cleanup duplicate definition of overwrite_console() - Signed-off-by: Wolfgang Denk +* Update TQM5200 configuration; + prepare for Rev. 200 starter kit boards -commit 5c761d57bb9940e016d561fda8b2ed84c55de5b6 -Author: Haavard Skinnemoen -Date: Thu Jul 10 13:16:04 2008 +0200 +* Patch by Scott McNutt, 21 Oct 2004: + Add support for Nios-II EPCS Controller core. - Remove kharris@nexus-tech.net from MAINTAINERS +* Patch by Scott McNutt, 20 Oct 2004: + Nios-II cleanups: + - Add sysid command (Nios-II only). + - Locate default exception trampoline at proper offset. + - Implement I/O routines (readb, writeb, etc) + - Implement do_bootm_linux - Mail to kharris@nexus-tech.net bounces because the user doesn't exist - anymore. You can't be a maintainer without a valid e-mail address, so - move all boards that used to be maintained by Kyle Harris to the - "orphaned" list. +* Patches by Martin Krause, 22 Mar 2005: + - use TQM5200_auto as MAKEALL target for TQM5200 systems + - add support for SM501 graphics controller + - add support for graphic console on TQM5200 + - add support for TQM5200 Rev 200 + - cleanup, fix typo in include/configs/TQM5200.h - Currently, only PowerPC has a list of orphaned boards, so this patch - creates one for ARM as well. +* Patch by Manfred Baral, 17 Mar 2005: + Fix typo - Signed-off-by: Haavard Skinnemoen +* Fix RTC configuration for PPChameleon board -commit 17bd17071463b0cde391ac4a0863d600474b4ea1 -Author: Anatolij Gustschin -Date: Thu Jul 10 01:15:10 2008 +0200 +* Cleanup, fix typo in include/configs/TQM5200.h - at91: Fix to enable using Teridian MII phy (78Q21x3) with at91sam9260 +* Patch by Stefan Roese, 16 Mar 2005: + Update for esd auto_update and hh405 board - On the at91sam9260ep development board there is an EEPROM - connected to the TWI interface (PA23, PA24 Peripheral A - multiplexing), so we cannot use these pins as ETX2, ETX3. - This patch configures PA10, PA11 pins for ETX2, ETX3 - instead of PA23, PA24 pins. +* Adapt for U-Boot image size (new features enabled) on TQM5200 - Signed-off-by: Anatolij Gustschin - Signed-off-by: Manuel Sahm +* Update code for TQM8540 board (and 85xx in general): + - Change the name of the Ethernet driver: MOTO ENET -> ENET + - Reformat boot messages + - Enable redundant environment + - Replace the -O2 optimization flag with -mno-string -commit f889265753ddf4465d9d580827bb9289bfac55d6 -Author: Kenneth Johansson -Date: Sat Jul 12 13:18:34 2008 -0600 +* Patch by David Brownell, 10 Mar 2005: + Restore copyright statements in OHCI drivers. - fix DIU for small screens +* Add support for TQM8540 board - The DIU_DIV register is 8 bit not 5 bit. This prevented large DIV values - so it was not possible to set a slow pixel clock and thus prevented - display on small screens. +* Patch by Detlev Zundel, 14 Mar 2005: + NC650: changed NAND flash addressing to using UPMB - Signed-off-by: Kenneth Johansson - Acked-by: John Rigby +* Patch by Stefan Roese, 14 Mar 2005: + Update for esd voh405 fpga image -commit b60b8573875e650e4c69be667bfc88d3ed474a7c -Author: John Rigby -Date: Fri Jul 11 14:44:09 2008 -0600 +* INKA4x0: Allow initialization of LCD backlight dimming from + "brightness" environment variable. - ADS5121 cleanup compile warnings +* Add port initialization for digital I/O on INKA4x0 - board/ads5121/iopin.c - Replace bit fields in struct iopin_t with a single - field and intialize it via plain old macros. - This fixes the type pun warnings and makes the code - more readable. +* Patch by Stefan Roese, 01 Mar 2005: + Update for esd boards dp405 and hub405 - board/ads5121/ads5121.c - Add include iopin.h to ads5121.c for the iopin_initialize - prototype. +* Fix get_partition_info() parameter error in all other calls + (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c). - Add an extern void ads5121_diu_init(void) +* Enable USB and IDE support for INKA4x0 board - Signed-off-by: John Rigby +* Patch by Andrew Dyer, 28 Feb 2005: + fix ext2load passing an incorrect pointer to get_partition_info() + resulting in load failure for devices other than 0 -commit bde63587622c4b830a27d1ddf7265843de9e994f -Author: Wolfgang Denk -Date: Fri Jul 11 22:56:11 2008 +0200 +* Add support for SRAM and 2 x Quad UARTs on INKA4x0 board - Fix some more printf() format issues. +* Cleanup USB and partition defines - Signed-off-by: Wolfgang Denk +* Add support for ext2 filesystems and image timestamps to TQM5200 board -commit 184f1b404a90eef8b425c0e7b3018d59ef9982c8 -Author: Wolfgang Denk -Date: Fri Jul 11 22:55:31 2008 +0200 +* Add reset code for Coral-P on INKA4x0 board - Fixed some out-of-tree build issues +* Patch by Martin Krause, 28 Jun 2004: + Update for TRAB board. - Signed-off-by: Wolfgang Denk +* Fix some missing "volatile"s in MPC5xxx FEC driver -commit 47bf9c71ae838305a3ea3161af8d14e6f3fc2c82 -Author: TsiChung Liew -Date: Wed Jul 9 16:20:23 2008 -0500 +* Fix cirrus voltage detection (for CPC45) - ColdFire: Fix FB CS not setup properly for Mcf5282 +* Fix byteorder problem in usbboot and scsiboot commands. - Remove all CFG_CSn_RO in cpu/mcf52x2/cpu_init.c. If - CFG_CSn_RO is defined as 0, the chipselect will not - be assigned. +* Patch by Cajus Hahn, 04 Feb 2005: + - don't insist on leading '/' for filename in ext2load + - set default partition to useful value (1) in ext2load - Signed-off-by: TsiChung Liew +* Patch by Andrew Dyer, 08 Jan 2005: + fix wrong return codes in ext2 code -commit bc3ccb139f0836f0a834cfd370a120a00ad7e63a -Author: TsiChung Liew -Date: Wed Jul 9 15:47:27 2008 -0500 +* Removed '--no-warn-mismatch' option from Makefile. This option + makes 'ld' to overlook binary objects compatibility. - ColdFire: Fix incorrect define for mcf5227x and mcf5445x RTC +* Moved $(PLATFORM_LIBS) from the library group (--start-group ... + --end-group) outside of the group. This will make 'ld' to do + _multiple_ search in the library group when resolving symbol + references and do only a _single_ seach in libgcc.a after the group + search. - Rename CONFIG_MCFTMR to CONFIG_MCFRTC to include real time - clock module in cpu//cpu_init.c +* Fix stability problems on CPC45 board again. - Signed-off-by: TsiChung Liew +* Make image detection for diskboot / usbboot / scsiboot more robust + (also check header checksum) -commit f94945b517f10e01927101679c62361e03d4e837 -Author: TsiChung Liew -Date: Wed Jul 9 15:25:01 2008 -0500 +* Update CPC45 board configuration. - ColdFire: Fix incorrect board name in MAKEALL for M5253EVBE +* Add USB and PCI support for INKA4x0 board - Signed-off-by: TsiChung Liew +* Fix IDE stability problems on CPC45 board (needs 2 x EIEIO). -commit 0e0c4357d14a3563c6a2a1e6d5ad6a2cc4f35cab -Author: TsiChung Liew -Date: Wed Jul 9 15:21:44 2008 -0500 +* Code cleanup - Fix compile error caused by missing timer function +* Patch by Robin Getz, 13 Oct 2004: + Add standalone application to change SMC91C111 MAC addresses, + see examples/README.smc91111_eeprom - Add #define CONFIG_MCFTMR in EB+MCF-EV123.h configuration file +* Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004: + Fix Flash support for ARM Integrator CP. - Signed-off-by: TsiChung Liew +* Patch by Richard Woodruff, 10 Jan 2005: + Update support for OMAP2420 (ARM11) and H4 board: + o clean up and add new types to H4 memory probe code. + o fix to work with internal boot. + o added PRCM config III operation. + o fix marginal flash timings. + o add revison ATAG usage. + o enable voltage scaling at power chip. + o fix compile error for i2c. -commit c37ea031175b807c54e6bad9b270e9bede6c0078 -Author: TsiChung Liew -Date: Wed Jul 9 15:14:25 2008 -0500 +* Fix network problem (error when receiving multiple ARP packets) - Fix compile error caused by incorrect function return type +* Patch by Daniel Poirot, 12 Oct 2004: + Add support for Wind River sbc405 board - Rename int mii_init(void) to void mii_init(void) +* Patch by Rainer Brestan, 12 Oct 2004: + Make examples/Makefile more robust - Signed-off-by: TsiChung Liew +* Patch by Sam Song, 11 October 2004: + - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board + - Adjust CPU:BUS frequency ratio 1:1 when core frequency + less than 50MHz -commit ab4860b255239dbaecccdd002c8d11f4ef54dd75 -Author: TsiChung Liew -Date: Wed Jun 18 19:27:23 2008 -0500 +* Patch by Sam Song, 10 Oct 2004: + Fix a parameter error in run_command() in main.c - ColdFire: Fix power up issue for MCF5235 +* Patch by Richard Woodruff, 01 Oct 2004: + add support for the TI OMAP2420 processor and its H4 reference + board - Signed-off-by: TsiChung Liew +* Patch by Christian Pellegrin, 24 Sep 2004: + Added support for NE2000 compatible (DP8390, DP83902) NICs. -commit dd08e97361fbc9e79fa5ef1a8acf29273b934b11 -Author: TsiChung Liew -Date: Wed Jun 18 19:19:07 2008 -0500 +* Patch by Leif Lindholm, 23 Sep 2004: + add support for the AMD db1550 board - ColdFire: Fix compiling error for MCF5275 +* Patch by Travis Sawyer, 15 Sep 2004: + Add CONFIG_SERIAL_MULTI support for ppc4xx, + update README.serial_multi - The compiling error was caused by missing a closed parentheses - in speed.c +* Patches by David Snowdon, 07 Sep 2004: + - add u-boot.hex target in the top level Makefile + - add support for the UNSW/NICTA PLEB 2 board (pleb2) + - use -mtune=xscale and -march=armv5 options for PXA - Signed-off-by: TsiChung Liew +* Patch by Florian Schlote, 08 Sep 2004: + Add support for SenTec-COBRA5272-board (ColdFire). -commit 94603c2fd4dbe0655878416aa0da9f302d4c30d3 -Author: TsiChung Liew -Date: Wed Jun 18 19:14:01 2008 -0500 +* Patch by Gleb Natapov, 07 Sep 2004: + mpc824x: set PCI latency timer to a sane value + (is 0 after reset). - ColdFire: Fix timer issue for MCF5272 +* Patch by Kurt Stremerch, 03 Sep 2004: + Add bitstream configuration option for fpga command (Xilinx only). - The timer was assigned to wrong timer memory mapped which - caused udelay() and timer() not working properly. +* Patch by Kurt Stremerch, 03 Sep 2004: + Add Xilinx Spartan2E family FPGA support - Signed-off-by: TsiChung Liew +* Patch by Jeff Angielski, 02 Sep 2004: + Add Added support for H2 revision of the EP8260 board. + Fixed formatting for some of the EP8260 related source files. -commit 3b1e8ac9b43f89cc9291a6a86e6b33ef55801515 -Author: TsiChung Liew -Date: Wed Jun 18 19:12:13 2008 -0500 +* Patch by Jon Loeliger, 02 Sep 2004: + Reset monitor size back to 256 so environment can be written + to flash on MPC85xx ADS and CDS releases. - ColdFire: Change invalid JMP to BRA caught by new v4e toolchain +* Patch by Paolo Broggini, 02 Sep 2004: + Make BSS clearing on ARM systems more robust - Signed-off-by: Kurt Mahan +* Patch by Yue Hu and Joe, 01 Sep 2004: + - add PCI support for ixp425; + - add EEPRO100 suppor tfor ixdp425 board. -commit 8371dc2066136be21e10b7b9293e469297d77298 -Author: TsiChung Liew -Date: Wed Jun 18 19:05:23 2008 -0500 +* Fix problem with protected sector detection in driver/cfi_flash.c - ColdFire: Add -got=single param for new linux v4e toolchains +====================================================================== +Changes for U-Boot 1.1.2: +====================================================================== - Signed-off-by: Kurt Mahan +* Code cleanup, mostly for GCC-3.3.x -commit 56d52615cd47bc522ee13bb7ec7e59d6ce9426c7 -Author: TsiChung Liew -Date: Wed Jun 18 13:21:19 2008 -0500 +* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to + pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for + additional ethernet addresses. - ColdFire: Fix code flash configuration for M547x/M548x boards +* Cleanup drivers/i82365.c - avoid duplication of code - Signed-off-by: Kurt Mahan +* Fix bogus "cannot span across banks" flash error message -commit 6e37091afc07fdcc15590093fd066b0cb7399f85 -Author: TsiChung Liew -Date: Tue Jun 24 12:12:16 2008 -0500 +* Code cleanup - ColdFire: Fix warning messages by passing correct data type in board.c +* Add support for CompactFlash for the CPC45 Board. - Signed-off-by: TsiChung Liew +* Fix problems with CMC_PU2 flash driver. -commit 81cc32322acb1b3225ee45606ced48e2a14824dc -Author: TsiChung Liew -Date: Thu May 29 12:21:54 2008 -0500 +* Cleanup: + - avoid trigraph warning in fs/ext2/ext2fs.c + - rename UC100 -> uc100 - ColdFire: Fix UART baudrate formula +* Add support for UC100 board - The formula "counter = (u32) (gd->bus_clk / gd->baudrate) / 32" - can generate the wrong divisor due to integer division truncation. - Round the calculated divisor value by adding 1/2 the baudrate - before dividing by the baudrate. +* Patch by Stefan Roese, 16 Dez 2004: + - ext2fs support added + - Tundra universe support added + - ColdFire MCF5249 support added (no preloader needed!) + - MCF5249 board TASREG added + - PPC boards added: APC405, CPCI405DT, CPCI750, G2000, HH405, + VOM405, WUH405 + - some esd boards updated + - memory commands "mdc" and "mwc" added for cyclic read/write + (CONFIG_MX_CYCLIC, see README for further description) - Signed-off-by: TsiChung Liew - Acked-by: Gerald Van Baren +* Add support for INKA4X0 board -commit b578fb471444cbd7db1285701ba51343baaf73fb -Author: Stefan Roese -Date: Thu Jul 10 11:38:26 2008 +0200 +* Patch by Steven Scholz, 12 Dec 2004: + Fix typo in AT91 memory setup. - ppc4xx: Fix include sequence in 4xx_pcie.c +* Patch by Martin Krause, 27 Oct 2004: + - add support for "STK52xx" board (including PS/2 multiplexer) + - add hardware detection for TQM5200 - This patch now moves common.h to the top of the inlcude list. This - is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that - the phys_size_t/phys_addr_t are defined to the correct size in this - driver. +* Clean up CMC PU2 flash driver - Signed-off-by: Stefan Roese +* Update MAINTAINERS file -commit 9b55a2536919f4de1bb1044e6eb8262c2f53bc96 -Author: Wolfgang Denk -Date: Fri Jul 11 01:16:00 2008 +0200 +* Fix bug in MPC823 LCD driver - Fix some more print() format errors. +* Fix udelay() on AT91RM9200 for delays < 1 ms. - Signed-off-by: Wolfgang Denk +* Enable long help on CMC PU2 board; + fix reset issue; + increase CPU speed from 179 to 207 MHz. -commit fdd70d1921b87287d9a99d1be99bc35226c2b412 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Thu Jul 10 20:57:54 2008 +0200 +* Fix smc91111 ethernet driver for Xaeniax board (need to handle + unaligned tail part specially). - MAKEALL: remove duplicated at91 from ARM9 list and add LIST_at91 to arm +* Update for AT91RM9200DK and CMC_PU2 boards: + - Enable booting directly from flash + - fix CMC_PU2 flash driver - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD +* Fix mkimage usage message -commit c6457e3b8bc79a97381cf7deffa08f7c5a24f86c -Author: Sergey Lapin -Date: Thu Jun 5 11:06:29 2008 +0400 +* Map SRAM on NC650 board - DataFlash AT45DB021 support +* Work around for Ethernet problems on Xaeniax board - Some boards based on AT91SAM926X-EK use smaller DF chips to keep - bootstrap, u-boot and its environment, using NAND or other external - storage for kernel and rootfs. This patch adds support for - small 1024x263 chip. +* Patch by TsiChung Liew, 23 Sep 2004: + - add support for MPC8220 CPU + - Add support for Alaska and Yukon boards - Signed-off-by: Sergey Lapin +* Fix configuration for ERIC board (needs more room) -commit 4109df6f75fc00ab7da56d286ba50149a0d16a69 -Author: Kim Phillips -Date: Thu Jul 10 14:00:15 2008 -0500 +* Adjust MIPS compiler options at run-time depending on tools version + ("-march=4kc -mtune=4kc -Wa,-mips_allow_branch_to_undefined" for new, + "-mcpu=4kc" for old tools) - silence misc printf formatting compiler warnings +* Add passing of the command line and memory size information to the + kernel on xaeniax board. - Signed-off-by: Kim Phillips +* Enable NAND flash support for NC650 board. -commit 3d71c81a9bb03f866a1e98da96363ef3f46c76b3 -Author: Markus Klotzbücher -Date: Thu Jul 10 14:47:09 2008 +0200 +* Patch by Thomas Lange 07 Oct 2004: + Updated README for DBAu1x00 boards to match current status - USB: shutdown USB before booting +* Patch by Philippe Robin, 28 Sept 2004: + Fix Flash support for Versatile. - This patch fixes a potentially serious issue related to USB which was - discouvered by Martin Krause and fixed for - ARM920T. Martin wrote: +* Patch by Roger Blofeld, 16 Sep 2004: + Fix timeout for DHCP command retry - Turn off USB to prevent the host controller from writing to the - SDRAM while Linux is booting. This could happen, because the HCCA - (Host Controller Communication Area) lies within the SDRAM and the - host controller writes continously to this area (as busmaster!), for - example to increase the HccaFrameNumber variable, which happens - every 1 ms. +* Patch by Pantelis Antoniou, 14 Sep 2004: + Fix early serial hang when CONFIG_SERIAL_MULTI is defined. - This is a slightly modified version of the patch in order to shutdown - USB when booting on all architectures. +* Patch by Pantelis Antoniou, 14 Sep 2004: + Kick watchdog when bz-decompressing - Signed-off-by: Markus Klotzbuecher +* Fix CFG_HZ problems on AT91RM9200 systems + [Remember: CFG_HZ should be 1000 on ALL systems!] -commit f31c49db2a5e076f415c0785eb37f67f2faa5fc8 -Author: Martha Marx -Date: Thu May 29 14:23:25 2008 -0400 +* Patch by Gridish Shlomi, 30 Aug 2004: + - Add support to revA version of PQ27 and PQ27E. + - Reverted MPC8260ADS baudrate back to original 115200 - Configuration changes for ADS5121 Rev 3 +* Patch by Hojin, 17 Sep 2004: + Fix typo in cfi_flash.c - ADS5121 Rev 3 board is now the default config +* Patch by Mark Jonas, 09 September 2004: + mtest's data line test (with CFG_ALT_MEMTEST set) returned a wrong + error message - config targets are now +* Patch by Mark Jonas, 31 August 2004: + Added option CFG_XLB_PIPELINING to enable XLB pipelining. This + improves FTP performance for MPC5200 systems. Enabled for IceCube + by default. - ads5121_config - Rev 3 board with - PCI - M41T62 on board RTC - 512MB DRAM +* Patch by Michael Bendzick, 30 Aug 2004: + - Improve platform.S code for omap1510inn that detects whether code + is running from SDRAM or not. Patch allows SDRAM to be configured + if code is running out of SRAM at 0x20000000. - ads5121_rev2_config - Rev 2 board with - No PCI - 256MB DRAM +* Patch by Frederick Klatt, 30 Aug 2004: + Add support for the Wind River SBC8540/SBC8560 boards - Signed-off-by: Martha Marx - Acked-by: Grant Likely - Acked-by: John Rigby +* Configure SX1 board to use drivers/cfi_flash.c -commit 16bee7b0dc294ee01ca2434aa1dd3bd717a69615 -Author: Martha Marx -Date: Thu May 29 15:37:21 2008 -0400 - - Consolidate ADS5121 IO Pin configuration - - Consolidate ADS5121 IO Pin configuration to one file - board/ads5121/iopin.c. - - Remove pin config from cpu/mpc512x/fec.c - - Signed-off-by: Martha Marx - Acked-by: Grant Likely - Acked-by: John Rigby - -commit d4692b0ba83b7b454bbd92bad1f4befe6e1657b7 -Author: Christian Eggers -Date: Fri Jun 27 19:46:51 2008 +0200 - - Fix "usb part" command - - Only print partition for selected device if user supplied the - arg with the "usb part [dev]" command. - - Signed-off-by: Christian Eggers - Acked-by: Markus Klotzbuecher - -commit cc83b27217f7380041fea386ddb6d6d9b261617d -Author: Harald Welte -Date: Mon Jul 7 00:58:05 2008 +0800 - - fix USB devices with multiple configurations - - This patch fixes bugs in usbdcore*.c related to the use of devices - with multiple configurations. - - The original code made mistakes about the meaning of configuration value and - configuration index, and the resulting off-by-one errors resulted in: - - * SET_CONFIGURATION always selected the first configuration, no matter what - wValue is being passed. - * GET_DESCRIPTOR/CONFIGURATION always returned the descriptor for the first - configuration (index 0). - - Signed-off-by: Harald Welte - Acked-by: Markus Klotzbuecher - -commit 06c53beae1a726e707971c555613f09b270a2461 -Author: Wolfgang Denk -Date: Thu Jul 10 13:16:09 2008 +0200 - - Fix some more print() format errors. - - Signed-off-by: Wolfgang Denk - -commit d4b5f3fa001228d76e2c3380cedadf804b802c2a -Author: Christian Eggers -Date: Fri Jun 27 19:46:51 2008 +0200 - - Fix "usb part" command - - Only print partition for selected device if user supplied the - arg with the "usb part [dev]" command. - - Signed-off-by: Christian Eggers - Acked-by: Markus Klotzbuecher - -commit e73b5212e0463a3db0af0a5c95c75bfb762ca973 -Author: Harald Welte -Date: Mon Jul 7 00:58:05 2008 +0800 - - fix USB devices with multiple configurations - - This patch fixes bugs in usbdcore*.c related to the use of devices - with multiple configurations. - - The original code made mistakes about the meaning of configuration value and - configuration index, and the resulting off-by-one errors resulted in: - - * SET_CONFIGURATION always selected the first configuration, no matter what - wValue is being passed. - * GET_DESCRIPTOR/CONFIGURATION always returned the descriptor for the first - configuration (index 0). - - Signed-off-by: Harald Welte - Acked-by: Markus Klotzbuecher - -commit e870690bdca154943ecadd5212d2d59c1b9d391b -Author: Stefan Roese -Date: Thu Jul 10 10:10:54 2008 +0200 - - MTD/NAND: Fix printf format warning in nand code - - This patch fixes NAND related printf format warning. Those warnings are - now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd - [Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is - really helpful. - - Signed-off-by: Stefan Roese - -commit 10943c9afa25694bd9999461f4e9e50ce22fff2b -Author: Stefan Roese -Date: Thu Jul 10 10:00:45 2008 +0200 - - rtc: Fix printf format warning in m41t60.c - - Signed-off-by: Stefan Roese - -commit dc1da42f814cd71e6756c2cf62af1ada1d0581fb -Author: Stefan Roese -Date: Tue Jul 8 12:01:47 2008 +0200 - - pci: Move PCI device configuration check into a separate weak function - - This patch moves the check, if a device should be skipped in PCI PNP - configuration into the function pci_skip_dev(). This function is defined - as weak so that it can be overwritten by a platform specific one if - needed. The check if the device should get printed in the PCI summary upon - bootup (when CONFIG_PCI_SCAN_SHOW is defined) is moved to the function - pci_print_dev() which is also defined as weak too. - - Signed-off-by: Stefan Roese - -commit b002144e1dc21374b1ef5281fe6b5d014af96650 -Author: Stefan Roese -Date: Thu Jul 10 09:58:06 2008 +0200 - - ppc4xx: Fix printf format warnings now visible with the updated format check - - This patch fixes ppc4xx related printf format warning. Those warnings are - now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd - [Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is - really helpful. - - Signed-off-by: Stefan Roese - -commit 5d812b8b4ad9667c77a5bf92b4ba81699abc9fc3 -Author: Stefan Roese -Date: Wed Jul 9 17:33:57 2008 +0200 - - ppc4xx: Enable support for > 2GB SDRAM on AMCC Katmai - - Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. - To support such configurations, we "only" map the first 2GB via the TLB's. We - need some free virtual address space for the remaining peripherals like, SoC - devices, FLASH etc. - - Note that ECC is currently not supported on configurations with more than 2GB - SDRAM. This is because we only map the first 2GB on such systems, and therefore - the ECC parity byte of the remaining area can't be written. - - Signed-off-by: Stefan Roese - -commit cf1c2ed91df26903b956948f37f82de9e1158a89 -Author: Larry Johnson -Date: Sat Jun 14 17:02:49 2008 -0400 - - ppc4xx: Remove implementation of testdram() from Korat board support - - Signed-off-by: Larry Johnson - Signed-off-by: Stefan Roese - -commit 47ce4a28ccfcfb803aa68d3d4505a8de056a8a5e -Author: Larry Johnson -Date: Sat Jun 14 16:53:02 2008 -0400 - - ppc4xx: Update and add FDT to Korat board support - - Signed-off-by: Larry Johnson - Signed-off-by: Stefan Roese - -commit 4188f0491886b3b486164e819c0a83fdb97efd7d -Author: Wolfgang Denk -Date: Thu Jul 10 01:13:30 2008 +0200 - - Minor coding style cleanup; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 8915f1189c1d29d8be7f4de325702d90a8988219 -Author: Paul Gortmaker -Date: Wed Jul 9 17:50:45 2008 -0400 - - e1000: add support for 82545GM 64bit PCI-X copper variant - - This PCI-X e1000 variant works by just adding in the correct - PCI IDs in the appropriate places. - - Signed-off-by: Paul Gortmaker - -commit 21ae6ca0315afdbc65dc3e95ffd5763e6773d030 -Author: Daniel Hellstrom -Date: Wed Jul 9 12:34:11 2008 +0000 - - SPARC: Build error fix - - (introduced by commit 391fd93ab23e15ab3dd58a54f5b609024009c378) - - This patch makes SPARC targets build again. It is caused by - phys_addr_t and phys_size_t being defined in the wrong header - file. include/lmb.h need those typedefs to build. - - Signed-off-by: Daniel Hellstrom - -commit 11ccc33fa21acce108f6b4a6936e3271af904c64 -Author: Marcel Ziswiler -Date: Wed Jul 9 08:17:15 2008 +0200 - - Many spelling fixes in README. - - Signed-off-by: Marcel Ziswiler - -commit dbab0691d2533560f7e91b92ae844046a9ad1df3 -Author: Marcel Ziswiler -Date: Wed Jul 9 08:17:06 2008 +0200 - - Minor spelling fix in comment. - - Signed-off-by: Marcel Ziswiler - -commit 89134ea1f67208fd3160bdbb0b9eaab4eab98484 -Author: Hugo Villeneuve -Date: Tue Jul 8 14:54:58 2008 -0400 - - Round the serial port clock divisor value returned by calc_divisor() - - Round the serial port clock divisor value returned by - calc_divisor(). - - Signed-off-by: Hugo Villeneuve - Signed-off-by: John Roberts - -commit 9d2e3947b2944e5bb85b4335533f8c93c58445fe -Author: Scott Wood -Date: Wed Jul 9 17:47:52 2008 -0500 - - NAND: ifdef-protect most of nand.h when using legacy NAND. - - Some macros such as NAND_CTL_SETALE conflict between current and legacy - NAND, being defined by the subsystem in the former case and the board - config file in the latter. - - Signed-off-by: Scott Wood - -commit 2b1fa9d383cbbb7d347c1583bd6ca4e181ba8e9e -Author: Hugo Villeneuve -Date: Tue Jul 8 11:02:05 2008 -0400 - - ARM: Fix for wrong patch version applied for Lyrtech SFF-SDR board (ARM926EJS) - - ARM: Fix for incorrect version of patch applied when - adding support for the Lyrtech SFF-SDR board. - - Signed-off-by: Hugo Villeneuve - Signed-off-by: Philip Balister, OpenSDR - -commit 47042b363ee5022b8180c65d3f4558e7972c79cd -Author: Kyungmin Park -Date: Tue Jul 8 09:08:40 2008 +0900 - - Remove useless print message at apollon - - Remove useless print message at apollon - - Signed-off-by: Kyungmin Park - -commit 98874ff329d4a5b32c467b43f6e966e1aa68479f -Author: Andy Fleming -Date: Mon Jul 7 14:24:39 2008 -0500 - - Fix LMB type issues - - The LMB code now uses phys_addr_t and phys_size_t. Also, there were a couple - of casting problems in the bootm code that called the LMB functions. - - Signed-off-by: Andy Fleming - -commit da8693a91b8eef75ade8de50a1b2ce035bc5fb54 -Author: Kumar Gala -Date: Mon Jul 7 09:39:06 2008 -0500 - - Fix compiler warnings - - gcc-4.3.x generates the following: - - bootm.c: In function 'do_bootm_linux': - bootm.c:208: warning: cast from pointer to integer of different size - bootm.c:215: warning: cast from pointer to integer of different size - - Signed-off-by: Kumar Gala - -commit 5bb12dbd7ae03189b6c13d8737b5a1b37c3df698 -Author: Harald Welte -Date: Mon Jul 7 15:40:39 2008 +0800 - - Remove code duplication for setting the default environment - - common/env_common.c (default_env): new function that resets the environment to - the default value - common/env_common.c (env_relocate): use default_env instead of own copy - common/env_nand.c (env_relocate_spec): use default_env instead of own copy - include/environment.h: added default_env prototype - - Signed-off-by: Werner Almesberger - Signed-off-by: Harald Welte - -commit 99c2b434d37863df5dda5207a53760c6506fc2be -Author: Marcel Ziswiler -Date: Sun Jun 22 16:13:46 2008 +0200 - - NAND: Fix warning due to missing env_ptr casts to u_char * in env_nand.c. - - The writeenv() and readenv() calls introduced by the recently added bad block - management for environment variables were missing casts therefore producing - compile time warnings. - While at it fixing some typo in a comment and indentation. - - Signed-off-by: Marcel Ziswiler - Signed-off-by: Scott Wood - -commit 3167c5386ea1c98b638be5d8763ef6d5938ef1bd -Author: Scott Wood -Date: Fri Jun 20 12:38:57 2008 -0500 - - NAND: Rename DEBUG to MTDDEBUG to avoid namespace pollution. - - This is particularly problematic now that non-NAND-specific code is - including , and thus all debugging code is being compiled - regardless of whether it was requested, as reported by Scott McNutt - . - - Signed-off-by: Scott Wood - -commit c3bf1ad7baa1b0dd989dedc260b7098b6089ae05 -Author: Haavard Skinnemoen -Date: Thu Jun 12 19:27:58 2008 +0200 - - mmc: Move atmel_mci driver into drivers/mmc - - This makes it easier to use the driver on other platforms. - - Signed-off-by: Haavard Skinnemoen - Acked-by: Jean-Chritophe PLAGNIOL-VILLARD - -commit d2d54ea449639f3d1a6007e333ab9fcc609a18f0 -Author: Haavard Skinnemoen -Date: Thu Jun 12 19:27:57 2008 +0200 - - avr32: Use CONFIG_ATMEL_MCI to select the atmel_mci driver - - After we move the atmel_mci driver into drivers/mmc, we can't select - it with CONFIG_MMC anymore. Introduce a new symbol specifically for - this driver so that there's no ambiguity. - - Signed-off-by: Haavard Skinnemoen - Acked-by: Jean-Chritophe PLAGNIOL-VILLARD - -commit 5ce13051a48c62bda9723df3b4778c492fb47f36 -Author: Haavard Skinnemoen -Date: Thu Jun 12 19:27:56 2008 +0200 - - Create drivers/mmc subdirectory - - In order to consolidate more of the various MMC drivers around the - tree, we must first have a common place to put them. - - Signed-off-by: Haavard Skinnemoen - Acked-by: Jean-Chritophe PLAGNIOL-VILLARD - -commit b502611b51f02718c2d1117d4981dabceb5af6de -Author: Joakim Tjernlund -Date: Sun Jul 6 12:30:09 2008 +0200 - - Change env_get_char from a global function ptr to a function - - This avoids an early global data reference. - - Signed-off-by: Joakim Tjernlund - -commit 27269417ade432189b234d9fbac98b54e37b978c -Author: Matvejchikov Ilya -Date: Sun Jul 6 13:57:58 2008 +0400 - - Some copy-n-paste fixes in printf usage - - Signed-off-by: Matvejchikov Ilya - -commit 0e6989b9faf1588e8723535539e88a0df3c71356 -Author: Matvejchikov Ilya -Date: Sun Jul 6 13:57:00 2008 +0400 - - FDT memory and pci node fixes for MPC8260ADS - - Signed-off-by: Matvejchikov Ilya - -commit dc4b0b38d4aadf08826f6c31270f1eecd27964fd -Author: Andrew Klossner -Date: Mon Jul 7 06:41:14 2008 -0700 - - Fix printf errors. - - The compiler will help find mismatches between printf formats and - arguments if you let it. This patch adds the necessary attributes to - declarations in include/common.h, then begins to correct the resulting - compiler warnings. Some of these were bugs, e.g., "$d" instead of - "%d" and incorrect arguments. Others were just annoying, like - int-long mismatches on a system where both are 32 bits. It's worth - fixing the annoying errors to catch the real ones. - - Signed-off-by: Andrew Klossner - -commit 417faf285b2527acb2de24c5cd3e2621d385408c -Author: Becky Bruce -Date: Wed Jul 9 11:09:41 2008 -0500 - - Allow print_size to print in GB - - Signed-off-by: Becky Bruce - -commit e7c374529c87525c9aa463e0557c287887ae4e9e -Author: Jason McMullan -Date: Sun Jun 8 23:56:00 2008 -0400 - - mips: When booting Linux images, add 'ethaddr' and 'eth1addr' to the environment - - Add 'ethaddr' and 'eth1addr' to the Linux kernel environment if - they are set in the U-Boot environment. - - Signed-off-by: Jason McMullan - Signed-off-by: Shinya Kuribayashi - -commit 0192d7d56e9320819dea262f49789ae18fdd2c72 -Author: Stefan Roese -Date: Tue Jul 8 12:57:14 2008 +0200 - - jedec_flash: Fix AM29DL800BB device ID - - As pointed out by Jerry Hicks, this patch corrects the device ID of - the Spansion AM29DL800BB NOR device. Verified against latest Spansion - datasheet (rev C4 from Dezember 2006). - - Signed-off-by: Stefan Roese - -commit 689c1b30caacba3fbca0b1813facb3ab70b6cd63 -Author: Nobuhiro Iwamatsu -Date: Mon Jul 7 11:22:37 2008 +0900 - - sh: Fix compile error sh7763rdp board - - Disable SH ether driver. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 9e23fe0560b84e324dc5f0ff8813dab2aa34f074 -Author: Nobuhiro Iwamatsu -Date: Tue Jul 8 12:03:24 2008 +0900 - - sh: Fix SH-boards compile error - - By Cleanup out-or-tree building for some boards (.depend) - (commit:c8a3b109f07f02342d097b30908965f7261d9f15) - because filse ware changed, some SH-boards have compile error. - I revised this problem. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 3473ab737282b08ad61841fcbb14c4d264a93a8e -Author: Jason Jin -Date: Tue May 13 11:50:36 2008 +0800 - - Feed the watchdog in u-boot for 8610 board. - - The watchdog on 8610 board is enabled by setting sw[6] - to on. Once enabled, the watchdog can not be disabled - by software. So feed the dog in u-boot is necessary for - normal operation. - - Signed-off-by: Jason Jin - -commit 63676841ca2d603b13765f3f7b72ff1a61c23f90 -Author: Hugo Villeneuve -Date: Wed Jun 18 12:10:33 2008 -0400 - - Remove duplicate code in cpu/arm926ejs/davinci/lxt972.c. - - Remove duplicate code in cpu/arm926ejs/davinci/lxt972.c. - - Remove duplicate code in a if/else block in - cpu/arm926ejs/davinci/lxt972.c. - Fixed style issues. - - Signed-off-by: Hugo Villeneuve - Signed-off-by: Ben Warren - -commit fec61431a003f5778bafa2624073a571af8bec9f -Author: Hugo Villeneuve -Date: Wed Jun 18 12:10:31 2008 -0400 - - Remove duplicate definitions in include/lxt971a.h. - - Remove duplicate definitions in include/lxt971a.h. - - Remove duplicate registers and bits definitions in - include/lxt971a.h for standard MII registers, and - use values in include/miiphy.h instead. - - Signed-off-by: Hugo Villeneuve - Signed-off-by: Ben Warren - -commit 9751ee0990f467941da0b095a4e995f863672d7a -Author: Nobuhiro Iwamatsu -Date: Wed Jun 11 21:05:00 2008 +0900 - - net: sh: Renesas SH7763 Ethernet device support - - Renesas SH7763 has 2 channel Ethernet device. - This is 10/100/1000 Base support. - But this patch check 10/100 Base only. - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Ben Warren - -commit 873d97aabc0b1c8822ed1d87e8c5c8ae0a7e4ae9 -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 16:28:05 2008 +0900 - - sh: Update Renesas R2DPlus board - - New NOR Flash board support and remove old type flash board config. - And Remove network setting from config file. - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit ec39d479d2003f15e86e23ebc4e02a1c9a3a181c -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 16:28:01 2008 +0900 - - sh: Update Renesas R7780MP board - - New NOR Flash board support and remove network setting from config file. - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit c001cd604e9f133743effbddb1c215b48e761c5a -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 16:27:56 2008 +0900 - - sh: Update Renesas Migo-R board - - Remove network setting from config file. - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit f9599eca7cb5ebe40e5305c8006dced6ecc5cd9e -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 16:27:52 2008 +0900 - - sh: Update Hitachi MS7722SE board - - Remove network setting from config file. - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit 26209e48e8791670c93108029a5c31a30016c6df -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 16:27:48 2008 +0900 - - sh: Cleanup source code of SH7763RDP - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit 5cd5b2c96ef0025762931349d350287aec03ab47 -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 16:27:44 2008 +0900 - - sh: Cleanup source code of R2DPlus - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit 4ec7e915cfaa31b392755dd2c8231e64736d2ea8 -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 16:27:41 2008 +0900 - - sh: Cleanup source code of R7780MP - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit 0955ef34c0454ae2ee59a78657a0f01fb3ef16d6 -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 16:27:38 2008 +0900 - - sh: Cleanup source code of MS7722SE - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit 1d7b31d97b34ccb6f9b20a2465864998b0bf2691 -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 16:27:34 2008 +0900 - - sh: Cleanup source code of MS7720SE - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit 3ab4827cbe409488ebea1a2ee5094783f2672214 -Author: Wolfgang Denk -Date: Mon Jul 7 00:45:03 2008 +0200 - - SH: fix out of tree building - - Signed-off-by: Wolfgang Denk - -commit 9047bfa1e737d787be460387dd6f45737eeceb10 -Author: Nobuhiro Iwamatsu -Date: Thu Jul 3 23:16:06 2008 +0900 - - net: smc911x: Fix typo - - Signed-off-by: Nobuhiro Iwamatsu - -commit 5ed546fdd0ca46a165661c2009fa743d9c9fceca -Author: Andre Schwarz -Date: Wed Jul 2 18:54:08 2008 +0200 - - update mvBL-M7 board config - - update mvBL-M7 config file to use UBOOT_VERSION and define - CONFIG_HIGH_BATS. - - Signed-off-by: Andre Schwarz - -commit 5cacc5d0ec52678a5eb83ecda5c3bcb22eb47f30 -Author: Nobuhiro Iwamatsu -Date: Mon Jun 30 17:45:01 2008 +0900 - - net: fix compile problem in smc911x driver. - - Signed-off-by: Nobuhiro Iwamatsu - Acked-by: Ben Warren - -commit 9fea65a6c469b1b474b27446feb58738baba2d31 -Author: Michal Simek -Date: Tue Jun 24 09:54:09 2008 +0200 - - ppc4xx: Rename CONFIG_XILINX_ML300 to CONFIG_XILINX_405 - - This change helps with better handling with others - Xilinx based platform. - - Signed-off-by: Michal Simek - Acked-by: Stefan Roese - -commit cbb6289569ae4fc6e2d676528e46ffcc72d743d0 -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 13:07:11 2008 +0900 - - net: ne2000: Move dev_addr variable from grobal to local. - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Ben Warren - -commit dd7e5fa5f847188f78f62f2c52de6cb3def3ecdb -Author: Nobuhiro Iwamatsu -Date: Tue Jun 17 13:07:15 2008 +0900 - - net: ne2000: Fix compile error of NE2000 - - If enable DEBUG, can not compile ne2000 driver. - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Ben Warren - -commit dd35479a50f6c7c31ea491c07c5200c6dfd06a24 -Author: Ben Warren -Date: Mon Jun 23 22:57:27 2008 -0700 - - Add mechanisms for CPU and board-specific Ethernet initialization - - This patch is the first step in cleaning up net/eth.c, by moving Ethernet - initialization to CPU or board-specific code. Initial implementation is - only on the Freescale TSEC controller, but others will be added soon. - - Signed-off-by: Ben Warren - -commit 7754f2be5d1835d263aad21b5a629526f3e680b0 -Author: Wolfgang Denk -Date: Sun Jul 6 01:21:46 2008 +0200 - - include/sha256.h: fix file permissions. - - Signed-off-by: Wolfgang Denk - -commit d3bcdf838e2991d58571308fa6e04ca335bc06e8 -Author: Patrice Vilchez -Date: Tue May 27 11:15:29 2008 +0200 - - [AT91SAM9] Fix NAND FLASH timings - - Fix NAND FLASH timings for at91sam9x evaluation kits. - - New timings are based on application note - "NAND Flash Support on AT91SAM9 Microcontrollers" available at - http://atmel.com/dyn/resources/prod_documents/doc6255.pdf - - Signed-off-by: Patrice Vilchez - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Acked-by: Stelian Pop - -commit 19bd688484322fe62d1a66c8299da6ff9e967ff9 -Author: Stelian Pop -Date: Thu May 22 00:15:40 2008 +0200 - - Fix boot from NOR due to incorrect reset delay. - - AT91 RSTC registers are battery-backuped, so their values - are not reset across power cycles. One of those registers, - the AT91_RSTC_MR register, is being modified by U-Boot, in - the ethernet initialisation routine, to generate a 500ms - user reset. - - Unfortunately, this value is not being restored afterwards, - causing subsequent resets to also last for 500ms. - - This long reset sequence causes problems (at least) in the - boot sequence from NOR: by the time the CPU tries to load - a program from the NOR flash, the latter is still in reset - and not yet available. - - Additionaly, this patch fixes a bug in the original code which - caused the reset delay to last for 2s instead of 500ms. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit f492dd636fbbae529e17533995bc6e5813c007f6 -Author: Wolfgang Denk -Date: Fri Jul 4 20:11:49 2008 +0200 - - Update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 5e6e350fc489aa19402f1e79037dd8c0a4bbd73d -Author: Wolfgang Denk -Date: Fri Jul 4 20:07:35 2008 +0200 - - CCM/SCM boards: fix out of tree building - - Signed-off-by: Wolfgang Denk - -commit ab4c3a490df9a964711556d2a05b0c787db45fde -Author: Wolfgang Denk -Date: Thu Jul 3 23:22:27 2008 +0200 - - SCM board: fix build errors. - - Signed-off-by: Wolfgang Denk - -commit a566466f17ba0e2d2b6c250e77da678fb932470d -Author: Wolfgang Denk -Date: Thu Jul 3 23:06:36 2008 +0200 - - IAD210 board: fix ``"ALIGN" redefined'' warning. - - Signed-off-by: Wolfgang Denk - -commit ad756314797c16fa5dca23e115aab881011f164f -Author: Wolfgang Denk -Date: Thu Jul 3 23:00:24 2008 +0200 - - CCM board: fix build errors. - - Signed-off-by: Wolfgang Denk - -commit f16ed51702cb9fb6fa2e019bbc0fcd1466b57c3b -Author: Andre Schwarz -Date: Wed Jul 2 18:54:08 2008 +0200 - - update mvBL-M7 board config - - update mvBL-M7 config file to use UBOOT_VERSION. - - Signed-off-by: Andre Schwarz - Signed-off-by: Kim Phillips - -commit ced209c50e80c25f13c083099b05044048d21f4f -Author: Wolfgang Denk -Date: Thu Jul 3 22:39:21 2008 +0200 - - sacsng board: fix warnings "suggest explicit braces to avoid ambiguous 'else'" - - Signed-off-by: Wolfgang Denk - -commit 4ff170a8180a79da4cdaab1b30d58cd7b6be565e -Author: Wolfgang Denk -Date: Thu Jul 3 22:34:08 2008 +0200 - - Cleanup: fix "expected specifier-qualifier-list before 'phys_size_t'" errors - - Signed-off-by: Wolfgang Denk - -commit 730f298485984b011b6ee8f4acb511cb45a843dd -Author: Wolfgang Denk -Date: Thu Jul 3 22:04:17 2008 +0200 - - lmb: fix "implicit declaration of function 'lmb_free'" warning - - Signed-off-by: Wolfgang Denk - -commit 322ef5e28d2dc62571afc699b00add22a8e006e4 -Author: Wolfgang Denk -Date: Wed Jul 2 23:53:23 2008 +0200 - - Cleanup: remove redundant deleting on *~ files - - Signed-off-by: Wolfgang Denk - -commit c8a3b109f07f02342d097b30908965f7261d9f15 -Author: Wolfgang Denk -Date: Wed Jul 2 23:49:18 2008 +0200 - - Cleanup out-or-tree building for some boards (.depend) - - Signed-off-by: Wolfgang Denk - -commit a30cc5a340e7f8f5f85a0e08e7f6c4106ce117c4 -Author: Wolfgang Denk -Date: Wed Jul 2 23:38:50 2008 +0200 - - Cleanup: fix out-of-tree building for some boards - - Signed-off-by: Wolfgang Denk - -commit 461fa68d20861811487944d22291db5a13410e20 -Author: Wolfgang Denk -Date: Wed Jul 2 23:00:14 2008 +0200 - - Cleanup: replace hard-wired $(AR) 'crv' settings by $(ARFLAGS) - - Signed-off-by: Wolfgang Denk - -commit 5981ebd32017e062b08aa6747cf591276f2db779 -Author: Detlev Zundel -Date: Fri Jun 20 22:26:24 2008 +0200 - - fdt: Fix typo in variable name. - - Signed-off-by: Detlev Zundel - -commit a7a5982cd0f3482f88225af4da7795bc4f6cb9bc -Author: Gary Jennejohn -Date: Thu Jun 19 11:11:19 2008 +0200 - - Add logos for RRvision board - - Signed-off-by: Gary Jennejohn - -commit ee4ae38342142237ca85913f88ee570c1eb5ca7c -Author: Esben Haabendal -Date: Wed Jun 18 11:03:57 2008 +0200 - - mpc8260: add fdt_fixup_ethernet support - - Add support for updating mac-address and local-mac-address in fdt for - all MPC8260 targets. - - Signed-off-by: Esben Haabendal - -commit f6a69559d64498a04e1e0b087a9b920e5775f866 -Author: Steven A. Falco -Date: Thu Jun 12 13:24:42 2008 -0400 - - cmd_nvedit.c: clean up syntax highlighting - - My text-editor (vim) has a bit of trouble syntax-highlighting the - cmd_nvedit.c file, because it apparently does not parse C - ifdef/else/endif. The following patch does not change the behavior of - the code at all, but does allow the editor to properly - syntax-highlight the file. - - Signed-off-by: Steve Falco - -commit 75678c807a6272ecc5541eb32898c93887f08400 -Author: Steven A. Falco -Date: Thu Jun 12 13:22:12 2008 -0400 - - Make setenv() return status - - Currently, the setenv function does not return an error code. - This patch allows to test for errors. - - Signed-off-by: Steve Falco - -commit 4928e97c8531283ca9b368b7c29a8a12e726562a -Author: Kumar Gala -Date: Wed Jun 11 10:14:06 2008 -0500 - - PPC: Added fls, fls64, __ilog2_u64, and ffs64 to bitops - - fls64, __ilog2_u64, ffs64 are variants that work on an u64, - and fls is used to implement them. - - Signed-off-by: Kumar Gala - -commit 83002a77cbdf383015ca384eff5fa31722d8e571 -Author: Magnus Lilja -Date: Mon Jun 9 22:58:48 2008 +0200 - - i.MX31: Cleanup comments in lowlevel_init.S. - - Signed-off-by: Magnus Lilja - -commit f8cc312bbee69257d741dc9f4062f4a0f5adf609 -Author: Ben Warren -Date: Sun Jun 8 23:28:33 2008 -0700 - - Move conditional compilation of MPC8XXX SPI driver to Makefile - - Signed-off-by: Ben Warren - -commit d92ea21bafb674ee2bf27447970b047845e7b0a2 -Author: Juergen Kilb -Date: Sun Jun 8 17:59:53 2008 +0200 - - i.MX31: fixed CTRL-C detection - - The Register URXD contains status information in bits [15..8]. - With status bit 15 set, CTRL-C was reported as 0x8003 instead - of 0x03. Therefore CTRL-C was not detected. - To solve this, bits [15..8] were masked out now. - - Signed-off-by: Juergen Kilb - Acked-by: Felix Radensky - -commit dd1c5523d6f44e842e69f2fcb50788c6060eab86 -Author: Stefan Roese -Date: Tue Jul 1 17:03:19 2008 +0200 - - ppc4xx: Fix 460EX/GT PCIe port initialization - - This patch fixes a bug where the 460EX/GT PCIe UTLSET1 register was - configured incorrectly. Thanks to Olga Buchonina from AMCC for pointing - this out. - - Signed-off-by: Stefan Roese - -commit b571afde0295b007a45055ee49f8822c753a5651 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Jun 7 12:29:52 2008 +0200 - - add SHA256 support - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Francesco Albanese - -commit 3bab76a26e03df4ff81342fcc16393ce37d9766b -Author: Marian Balakowicz -Date: Fri Jun 6 23:07:40 2008 +0200 - - Delay FIT format check on sector based devices - - Global FIT image operations like format check cannot be performed on - a first sector data, defer them to the point when whole FIT image was - uploaded to a system RAM. - - Signed-off-by: Marian Balakowicz - Partial ('cmd_nand' case) Acked-by: Grant Erickson - NAND and DOC bits Acked-by: Scott Wood - -commit 9810263afec5ac5f38f92963bb3b6d799e4331d0 -Author: Dave Liu -Date: Tue Jun 3 17:38:19 2008 +0800 - - sata: wait for device updating signature to host - - The driver need wait for the device updating signature to host. - If we don't wait for it, the driver can not detect the device(disk) - when the system powers up. - - Signed-off-by: Dave Liu - -commit 745d8a0d3cea82e6d1753e14afb4588c34761b15 -Author: Stefan Roese -Date: Sat Jun 28 14:56:17 2008 +0200 - - ppc4xx: Fix 460EX errata with CPU lockup upon high AHB traffic - - This patch implements a fix provided by AMCC so that the lockup upon - simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur - anymore: - - Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2] - (bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG, - USB 2.0 host and SATA. - - This errata is not officially available yet. I'll update the comment - to add the errata number later. - - Signed-off-by: Stefan Roese - -commit 8b616edb118e37d05f6401389eaee1c636b22828 -Author: Stuart Wood -Date: Mon Jun 2 16:42:19 2008 -0400 - - serial_pl010.c: add watchdog support - - Signed-off-by: Stuart Wood - -commit 86d3273e2b7be3fffb45e20c08535d6ad3aded6b -Author: Stuart Wood -Date: Mon Jun 2 16:40:08 2008 -0400 - - jffs2_1pass.c: add watchdog support - - Signed-off-by: Stuart Wood - -commit 5744ddc6637fea4f7b911a54a5fa860cb81a5d89 -Author: Sascha Laue -Date: Fri May 30 09:48:14 2008 +0200 - - Configure DSP POST; add watchdog reset to diag command - - Signed-off-by: Sascha Laue - -commit f13526517859bf6b573e23ff47199e107d1009b5 -Author: Tor Krill -Date: Thu May 29 10:40:17 2008 +0200 - - Add sata sil3114 support - - Signed-off-by: Tor Krill - -commit e093a247628228100f405b6d7f6b1bfc16141938 -Author: Wolfgang Denk -Date: Sat Jun 28 23:34:37 2008 +0200 - - Coding Style Cleanup - - Signed-off-by: Wolfgang Denk - -commit 01db232dd7a0ceb81208a9f2545720c80e5bfd83 -Author: Wolfgang Denk -Date: Sat Jun 28 23:16:01 2008 +0200 - - Update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit c7f879ec2b389c4f2bf726b293bd516f4c692e03 -Author: Hugo Villeneuve -Date: Wed May 21 13:58:41 2008 -0400 - - ARM: Add support for Lyrtech SFF-SDR board (ARM926EJS) - - This patch adds support for the Lyrtech SFF-SDR board, - based on the TI DaVinci architecture (ARM926EJS). - - Signed-off-by: Hugo Villeneuve - Signed-off-by: Philip Balister - Signed-off-by: Wolfgang Denk - -commit 341188b9ccaa8d4462d772cc067aca8d7618633a -Author: Haavard Skinnemoen -Date: Thu May 22 11:09:59 2008 +0200 - - MMC: Consolidate MMC/SD command definitions - - This moves the MMC and SD Card command definitions from - include/asm/arch/mmc.h into include/mmc.h. These definitions are - given by the MMC and SD Card standards, not by any particular - architecture. - - There's a lot more room for consolidation in the MMC drivers which - I'm hoping to get done eventually, but this patch is a start. - - Compile-tested for all avr32 boards as well as lpc2292sodimm and - lubbock. This should cover all three mmc drivers in the tree. - - Signed-off-by: Haavard Skinnemoen - -commit fa60edfc4c952626e048c0e065f654b3c1822fa5 -Author: Kyungmin Park -Date: Wed May 21 14:38:08 2008 +0900 - - Use better Ethernet timings for apollon board - - Signed-off-by: Kyungmin Park - -commit 41c5eaa7253ed82bbae1eda5667755872c615164 -Author: Andy Fleming -Date: Mon Jun 16 13:58:56 2008 -0500 - - Resize device tree to allow space for board changes and the chosen node - - Current code requires that a compiled device tree have space added to the end to - leave room for extra nodes added by board code (and the chosen node). This - requires that device tree creators anticipate how much space U-Boot will add to - the tree, which is absurd. Ideally, the code would resize and/or relocate the - tree when it needed more space, but this would require a systemic change to the - fdt code, which is non-trivial. Instead, we resize the tree inside - boot_relocate_fdt, reserving either the remainder of the bootmap (in the case - where the fdt is inside the bootmap), or adding CFG_FDT_PAD bytes to the size. - - Signed-off-by: Andy Fleming - -commit 7570a9941fc565922078679a72d246fe208d696d -Author: Andy Fleming -Date: Mon Jun 16 13:58:55 2008 -0500 - - Fix an underflow bug in __lmb_alloc_base - - __lmb_alloc_base can underflow if it fails to find free space. This was fixed - in linux with commit d9024df02ffe74d723d97d552f86de3b34beb8cc. This patch - merely updates __lmb_alloc_base to resemble the current version in Linux. - - Signed-off-by: Andy Fleming - -commit 63796c4e61b207d2e635729d41b7a7f7d188b03c -Author: Andy Fleming -Date: Mon Jun 16 13:58:54 2008 -0500 - - Add lmb_free - - lmb_free allows us to unreserve some memory so we can use lmb_alloc_base or - lmb_reserve to temporarily reserve some memory. - - Signed-off-by: Andy Fleming - -commit 4b03ac8b5102ad95f9fede7d13fa236977593e7d -Author: Andy Fleming -Date: Mon Jun 16 13:58:53 2008 -0500 - - Add ALIGN() macro - - ALIGN() returns the smallest aligned value greater than the passed - in address or size. Taken from Linux. - - Signed-off-by: Andy Fleming - -commit 93262af85e3e9d9974c6c08fbd37a9a72e090ca2 -Author: Stefan Roese -Date: Tue Jun 24 17:15:22 2008 +0200 - - ppc4xx: Fix compilation problems with phys_size_t - - This patch includes before in some 4xx - board specific files where it has been missing. - - Signed-off-by: Stefan Roese - -commit 28eab0d77352b84885f938759bf2612b7bf0bc44 -Author: Haavard Skinnemoen -Date: Mon May 19 12:26:38 2008 +0200 - - Conditionally add -fno-stack-protector to CFLAGS - - When compile-testing on powerpc, I get errors like this: - - net/nfs.c:422: undefined reference to `__stack_chk_fail_local' - - This seems to be because -fstack-protector is on by default, so - let's explicitly disable it on all architectures that support the - option. - - The Ubuntu toolchain is affected by this problem, and according to - Mike Frysinger, Gentoo has been running with SSP enabled for years. - More and more distros are turning SSP on by default, so this problem - is likely to get worse in the future. - - Also, powerpc just happens to be one of the arches I do - compile-testing on. There may be other arches affected by this too. - - Signed-off-by: Haavard Skinnemoen - -commit dfd3be881c03a26e31f0dea4a42e76061fa610ac -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 18 19:09:52 2008 +0200 - - pcmcia/ti_pci1410a: Move compile condition to the Makefile - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 72d5d5f7b5c74a188df238ec6dd824d80c74857a -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 18 19:09:51 2008 +0200 - - pxa_pcmcia: Move compile condition to the Makefile - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit c9eff32881fb429101c937cf8c268f1d42e5c2a9 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 18 19:09:50 2008 +0200 - - marabun_pcmcia: Move compile condition to the Makefile - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 6a19c46cae43c16c528eddefae3db97134f1915d -Author: Andre Schwarz -Date: Mon Jun 23 13:25:34 2008 +0200 - - fix non-working mvBL-M7 - - Add missing #define CONFIG_HIGH_BATS in mvBL-M7 board config file. - - Signed-off-by: Andre Schwarz - Signed-off-by: Kim Phillips - -commit 846f1574ddddeda2bc227655e687308695f41cdc -Author: Andre Schwarz -Date: Mon Jun 23 11:40:56 2008 +0200 - - fix system config overwrite @ MPC834x and MPC8313 - - During 83xx setup the "System I/O configuration register high" gets - overwritten with user defined value if CFG_SICRH is defined. - - Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH - must keep their reset value regardless of configuration. - - On my board (using RGMII) those bits are set after reset - yet it's - unclear where they come from. - - The patch keeps both bits on MPC834x and MPC8313. - - Signed-off-by: Andre Schwarz - Signed-off-by: Kim Phillips - -commit 4890246a2c5df90a74e2941e3673a49bbd36aee9 -Author: Kim Phillips -Date: Tue Jun 17 17:45:27 2008 -0500 - - mpc83xx: move CPU_TYPE_ENTRY over to processor.h - - to avoid this: - - cpu.c:47:1: warning: "CPU_TYPE_ENTRY" redefined - In file included from cpu.c:33: - /home/kim/git/u-boot/include/asm/processor.h:982:1: warning: this is the location of the previous definition - - Signed-off-by: Kim Phillips - -commit aac7a5095b968d6c9a3e6422f31b4ad203cac9c8 -Author: Stefan Roese -Date: Mon Jun 23 11:15:09 2008 +0200 - - ppc4xx: Fix problem in gpio_config() - - As pointed out by Guennadi Liakhovetski (thanks), pin2 is already shifted - left by one. So the additional shift is bogus. - - Signed-off-by: Stefan Roese - -commit 40777812316fc252c941665c0f60c148fd79d50f -Author: Detlev Zundel -Date: Fri Jun 20 22:24:05 2008 +0200 - - fdt: Fix typo in variable name. - - Signed-off-by: Detlev Zundel - -commit 5f723a3b98c630bde33de74351f2121691fdef14 -Author: Haavard Skinnemoen -Date: Fri Jun 20 10:41:05 2008 +0200 - - avr32: Enable SPI flash support on ATNGW100 - - The ATNGW100 has 8MB DataFlash on board. Give users access to it through - the new SPI flash framework. - - Signed-off-by: Haavard Skinnemoen - -commit 5605ef6b5802921cbefe6a933a9dea3497396b5c -Author: Haavard Skinnemoen -Date: Fri Jun 20 12:44:28 2008 +0200 - - avr32: Fix SPI portmux initialization - - Use the new GPIO manipulation functions to set up the chip select lines, - and make sure both busses use GPIO for chip select control. - - Signed-off-by: Haavard Skinnemoen - -commit 4688f9e34a87e825aed34d07c9ca7a273e6fc8ab -Author: Peter Ma -Date: Sun Jun 1 22:59:24 2008 -0700 - - avr32: Add GPIO manipulation functions - - Adds GPIO manipulation functions for AVR32 AP7 platform. - - Signed-off-by: Peter Ma - [haavard.skinnemoen@atmel.com: coding style fixup, slight simplification] - Signed-off-by: Haavard Skinnemoen - -commit b4fe1a71090c73efc6e4188eed188b2ff67fc02a -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:02:30 2008 +0200 - - MPC8360ERDK: adapt NAND interface for the re-written FSL NAND UPM driver - - This patch is based on the following patch sent a few minutes ago: - "NAND FSL UPM: driver re-write using the hwcontrol callback" - It is untested, of course. Anton, could you please give it a try. - - Signed-off-by: Wolfgang Grandegger - Acked-by: Anton Vorontsov - -commit 96026d42fa4e646d28318c0a1438aac4b2017909 -Author: Anatolij Gustschin -Date: Thu Jun 12 12:40:11 2008 +0200 - - Fix 4xx build issue - - Building for 4xx doesn't work since commit 4dbdb768: - - In file included from 4xx_pcie.c:28: - include/asm/processor.h:971: error: expected ')' before 'ver' - make[1]: *** [4xx_pcie.o] Error 1 - - This patch fixes the problem. - - Signed-off-by: Anatolij Gustschin - Acked-by: Stefan Roese - Acked-by: Kumar Gala - -commit a036b0443657fe0f4773786de9092251869f08ac -Author: Kumar Gala -Date: Thu Jun 19 01:45:50 2008 -0500 - - MPC8610HPCD: Report board id, board version and fpga version. - - Signed-off-by: Kumar Gala - -commit 7de8c21f14df9c20fdcf6027aec8e8545f75f835 -Author: Kumar Gala -Date: Thu Jun 19 01:45:27 2008 -0500 - - MPC8641HPCN: Report board id, board version and fpga version. - - Signed-off-by: Kumar Gala - -commit fb8c061ea05fc68d37e2a8b9f8c949d76c8d71a8 -Author: Stefan Roese -Date: Mon Jun 16 10:40:02 2008 +0200 - - cfi-flash: Fix problem in flash_toggle(), busy was not detected reliably - - This patch simplifies flash_toggle() (AMD commandset), which is used to - detect if a FLASH device is still busy with erase/program operations. On - 800MHz Canyonlands/Glacier boards (460EX/GT) the current implementation - did not detect the busy state reliably, resulting in non erased sectors - etc. This patch now simplifies this function by "just" comparing the - complete data-word instead of ANDing it with the command-word (0x40) - before the compatison. It is done the same way in the Linux implementation - chip_ready() in cfi_cmdset_0002.c. - - Signed-off-by: Stefan Roese - -commit 9e4006bca3d9fb4a2d061996771036cb01e539d3 -Author: Philip Balister -Date: Mon Jun 16 08:58:07 2008 -0400 - - NAND: Add missing declaration to non-redundant saveenv(). - - Signed-off-by: Scott Wood - -commit 2cdb7f50ac59594540fffdf8dbd7b12beac79c52 -Author: Wolfgang Grandegger -Date: Mon Jun 2 15:09:55 2008 +0200 - - MPC8360ERDK: adapt NAND interface for the re-written FSL NAND UPM driver - - Signed-off-by: Wolfgang Grandegger - Acked-by: Anton Vorontsov - Signed-off-by: Scott Wood - -commit 212ed90615c3d20fa6bd73d70d5153bd0d124e5f -Author: Stefan Roese -Date: Tue Jun 10 15:34:11 2008 +0200 - - ppc4xx: Canyonlands: Disable the RTC M41T62 square wave output - - This patch disables the square wave output of the M41T62 RTC used on - Canyonlands & Glacier. Here the explanation: - - The serial real-time clock part used in the design is an - STMicro M41T62. This part has a full-time 32KHz square wave - output that is connected to the TmrClk input to the - processor. The default state for this square wave output is - enabled so the output runs continuously when the board is - powered normally and also from the battery. The TmrClk input - to the processor goes to ground when the power is removed - from the board/processor, and therefore the running square - wave output is driving ground which drains the battery quickly. - - Signed-off-by: Stefan Roese - -commit a94f22f08f280905926219e568568964cb9eeb9d -Author: Andy Fleming -Date: Wed Jun 11 18:10:20 2008 -0500 - - Fix build issue with string.h and linux/string.h - - This commit: - commit 338cc038461a6c7709c5b86fd9a240209338a1ae - Author: Wolfgang Denk - Date: Fri Jun 6 14:28:14 2008 +0200 - - tools/mkimage: fix compiler warnings on some systems. - - Broke building on some systems, because the host's string.h was interfering - with u-boot's linux/string.h. It doesn't look like we need the u-boot one if - we're building for the host, so now we only include when building inside - u-boot. - - Signed-off-by: Andy Fleming - -commit 9973e3c614721bbf169882ffc3be266a6611cd60 -Author: Becky Bruce -Date: Mon Jun 9 16:03:40 2008 -0500 - - Change initdram() return type to phys_size_t - - This patch changes the return type of initdram() from long int to phys_size_t. - This is required for a couple of reasons: long int limits the amount of dram - to 2GB, and u-boot in general is moving over to phys_size_t to represent the - size of physical memory. phys_size_t is defined as an unsigned long on almost - all current platforms. - - This patch *only* changes the return type of the initdram function (in - include/common.h, as well as in each board's implementation of initdram). It - does not actually modify the code inside the function on any of the platforms; - platforms which wish to support more than 2GB of DRAM will need to modify - their initdram() function code. - - Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc - MPC8641HPCN. - - Signed-off-by: Becky Bruce - -commit 391fd93ab23e15ab3dd58a54f5b609024009c378 -Author: Becky Bruce -Date: Mon Jun 9 20:37:18 2008 -0500 - - Change lmb to use phys_size_t/phys_addr_t - - This updates the lmb code to use phys_size_t - and phys_addr_t instead of unsigned long. Other code - which interacts with this code, like getenv_bootm_size() - is also updated. - - Booted on MPC8641HPCN, build-tested ppc, arm, mips. - - Signed-off-by: Becky Bruce - -commit 61b09fc2952dc636017df4e7970e3de132276ba1 -Author: Becky Bruce -Date: Mon Jun 9 20:37:17 2008 -0500 - - Change print_size to take phys_size_t - - Signed-off-by: Becky Bruce - -commit b57ca3e128cc10a133ba79bc7ec3e7b50e7c8fbe -Author: Becky Bruce -Date: Mon Jun 9 20:37:16 2008 -0500 - - Change bd/gd memsize/ram_size to be phys_size_t. - - Currently, both are defined as an unsigned long, but - should be phys_size_t. This should result in no real change, - since phys_size_t is currently an unsigned long for all the - default configs. Also add print_lnum to cmd_bdinfo to deal - with the potentially wider memsize. - - Signed-off-by: Becky Bruce - -commit ba04f7010958e88a8910f2a123fee53fdc72e013 -Author: Kumar Gala -Date: Tue Jun 10 16:16:02 2008 -0500 - - FSL LAW: Add new interface to use the last free LAW - - LAWs have the concept of priority so its useful to be able to allocate - the lowest (highest number) priority. We will end up using this with the - new DDR code. - - Signed-off-by: Kumar Gala - -commit 859a86a25c569d3665ff413d1d923394b8a961f3 -Author: Kumar Gala -Date: Wed Jun 11 00:51:45 2008 -0500 - - 85xx/86xx: Move to dynamic mgmt of LAWs - - With the new LAW interface (set_next_law) we can move to letting the - system allocate which LAWs are used for what purpose. This makes life - a bit easier going forward with the new DDR code. - - Signed-off-by: Kumar Gala - Signed-off-by: Andy Fleming - Acked-by: Jon Loeliger - Acked-by: Becky Bruce - -commit f060054dadbbe7027ca088eed806a3ef1f82fdb7 -Author: Kumar Gala -Date: Wed Jun 11 00:44:10 2008 -0500 - - FSL LAW: Keep track of LAW allocations - - Make it so we keep track of which LAWs have allocated and provide - a function (set_next_law) which can allocate a LAW for us if one is - free. - - In the future we will move to doing more "dynamic" LAW allocation - since the majority of users dont really care about what LAW number - they are at. - - Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them - - Signed-off-by: Kumar Gala - Signed-off-by: Andy Fleming - -commit ddde74a159caa6e18b481fec01d40b885aebb566 -Author: Kumar Gala -Date: Mon Jun 9 22:31:57 2008 -0500 - - 85xx: remove dummy board_early_init_f - - A number of board ports have empty version of board_early_init_f - for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F. - - Signed-off-by: Kumar Gala - -commit 81e56e9af0d43712db8efb843606a8d62eab454f -Author: Kumar Gala -Date: Mon Jun 9 18:55:38 2008 -0500 - - MPC8544DS: Update config.h - - * Enable flash progress - * remove CLEAR_LAW0 since we dont really use it - - Signed-off-by: Kumar Gala - -commit 978e81604c1b28526ed580df0fbe64eb8384e94f -Author: Kumar Gala -Date: Mon Jun 9 13:37:24 2008 -0500 - - 85xx: Remove unused and unconfigured memory test code. - - Remove unused and unconfigured DDR test code from FSL 85xx boards. - Besides, other common code exists. - - Signed-off-by: Kumar Gala - -commit a23cddde1a95f987e3fe2a720a7ec9375b7264d7 -Author: Sergei Poselenov -Date: Fri Jun 6 15:42:45 2008 +0200 - - Socrates: Added FPGA base address update in FDT. - - Signed-off-by: Sergei Poselenov - -commit fd51b0e0e620b8bc9fd4f6daa3a4fa6f5e1316f4 -Author: Sergei Poselenov -Date: Fri Jun 6 15:42:44 2008 +0200 - - Socrates: NAND support added. Changed the U-Boot base address and - - Signed-off-by: Sergei Poselenov - -commit 248ae5cfc8bf69074d1da099dc495d8e06070547 -Author: Sergei Poselenov -Date: Fri Jun 6 15:42:43 2008 +0200 - - NAND: Added support for 128-bit OOB, adapted - - Signed-off-by: Sergei Poselenov - -commit 31ca0208612f2eb57690110d7c2815953650e47b -Author: Sergei Poselenov -Date: Fri Jun 6 15:42:42 2008 +0200 - - Socrates: added missed file with UPMA configuration data. - - Signed-of-by: Sergei Poselenov - -commit 59abd15b43cab7a4d19de4ba0943837d9555f7ba -Author: Sergei Poselenov -Date: Fri Jun 6 15:42:41 2008 +0200 - - Socrates: Added FPGA mapping. LAWs and TLBs cleanup. - - Signed-off-by: Sergei Poselenov - -commit 740280e68ccc0b971e613face7eaaa8bd1382b8c -Author: Sergei Poselenov -Date: Fri Jun 6 15:42:40 2008 +0200 - - Added the upmconfig() function for 85xx. - - Signed-off-by: Sergei Poselenov - Signed-off-by: Andy Fleming - -commit d39e68514ff943930ee692cff3fde03532eb7fec -Author: Sergei Poselenov -Date: Fri Jun 6 15:42:39 2008 +0200 - - Socrates: config file cleanup. - - Signed-off-by: Sergei Poselenov - -commit e8cc3f04b124f757af4528206e60d8eb715ae083 -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:10 2008 +0200 - - TQM85xx: Change memory map to support Flash memory > 128 MiB - - Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash - memory. The current memory map only supports up to 128 MiB Flash. - This patch adds the configuration option CONFIG_TQM_BIGFLASH. If - set, up to 1 GiB flash is supported. To achieve this, the memory - map has to be adjusted in great parts (for example the CCSRBAR is - moved from 0xE0000000 to 0xA0000000). - - If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new - memory map also has to be considered in the kernel (changed - CCSRBAR address, changed PCI IO base address, ...). Please use - an appropriate Flat Device Tree blob (tqm8548.dtb). - - Signed-off-by: Martin Krause - Signed-off-by: Wolfgang Grandegger - -commit 1c2deff22cd6e2bf0e618fd6e09ca3eec5a8d051 -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:09 2008 +0200 - - TQM85xx: NAND support via local bus UPMB - - This patch adds support for NAND FLASH on the TQM8548. It is disabled by - default and can be enabled for the TQM8548 modules. It is now based on - the re-written FSL NAND UPM driver. A patch has been posted earlier today - with the subject: - - "NAND FSL UPM: driver re-write using the hwcontrol callback" - - Note that the R/B pin is not supported by that module requiring to use - the specified maximum delay time. - - Note: With NAND support enabled the size of the U-Boot image exceeds - 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, - doubling the image size :-(. - - Signed-off-by: Thomas Waehner - Signed-off-by: Wolfgang Grandegger - -commit b9e8078bb3f3c48111a7081e27279938c3a445e1 -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:08 2008 +0200 - - TQM8548: PCI express support - - This patch adds support for PCI express cards. The board support - now uses common FSL PCI init code, for both, PCI and PCIe on all - TQM85xx modules. - - Signed-off-by: Thomas Waehner - Signed-off-by: Wolfgang Grandegger - -commit 1287e0c55a2ee2c575ac9ce8e4302cd4085be876 -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:07 2008 +0200 - - TQM8548: Basic support for the TQM8548 modules - - This patch adds basic support for the TQM8548 module from TQ-Components - (http://www.tqc.de/) including DDR2 SDRAM initialisation and support for - eTSEC 3 and 4 - - Furthermore Flash buffer write has been enabled to speed up output to - the Flash by approx. a factor of 10. - - Signed-off-by: Thomas Waehner - Signed-off-by: Wolfgang Grandegger - -commit 25991353204c78b094c3c1fec90182dcd607ab8f -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:06 2008 +0200 - - TQM85xx: Support for Flat Device Tree - - This patch adds support for Linux kernels using the Flat Device Tree. - It also re-defines the default environment settings for booting Linux - with the FDT blob. - - Signed-off-by: Wolfgang Grandegger - -commit d9ee843d54c54776e1fdb86336ce554906a87331 -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:05 2008 +0200 - - TQM85xx: Support for Intel 82527 compatible CAN controller - - This patch adds initialization of the UPMC RAM to support up to two - Intel 82527 compatible CAN controller on the TQM85xx modules. - - Signed-off-by: Thomas Waehner - Signed-off-by: Wolfgang Grandegger - -commit 518d5cfe72916323c746af1647764459914f555f -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:04 2008 +0200 - - TQM85xx: Bugfix in the SDRAM initialisation - - The CS0_BNDS register is now set according to the detected - memory size. - - Signed-off-by Martin Krause - -commit 45dee2e620ccec6ac7b3548fe8979a34fd030e5d -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:03 2008 +0200 - - TQM85xx: Fix chip select configuration for second FLASH bank - - This patch fixes the re-calculation of the automatic chip select - configuration for boards with two populated FLASH banks. - - Signed-off-by: Martin Krause - -commit 46346f27cda6fd025a496bde8f2d4aeee04aca5f -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:02 2008 +0200 - - TQM85xx: Support for Spansion 'N' type flashes added - - The 'N' type Spansion flashes (S29GLxxxN series) have bigger sectors, - than the formerly used 'M' types (S29GLxxxM series), so the flash layout - needs to be changed -> new start address of the environment. The macro - definition CONFIG_TQM_FLASH_N_TYPE is undefined by default and must be - defined for boards with 'N' type flashes. - - Signed-off-by: Martin Krause - Signed-off-by: Wolfgang Grandegger - -commit 5d5bd838f76eade22c0ea40a500389f924d0da36 -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:01 2008 +0200 - - TQM85xx: Fix CPM port pin configuration - - Do not configure port pins PD30/PD31 as SCC1 TxD/RxD except for the TQM8560 - board. On the other TQM85xx boards (TQM8541 and TQM8555) SCC1 is not used - as serial interface anyway. Worse, on some board variants configuring the - pins for SCC1 leads to short circuits (for example on the TQM8541-BG). - - Signed-off-by: Martin Krause - -commit b99ba1679e8cd51b023e67098c89e606e47137d2 -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:12:00 2008 +0200 - - TQM85xx: Various coding style fixes - - Signed-off-by: Wolfgang Grandegger - -commit ae9e97fa96f643c8ba2b666b06a026cc8717eb00 -Author: Gerald Van Baren -Date: Tue Jun 10 22:15:58 2008 -0400 - - libfdt: Move the working_fdt pointer to cmd_fdt.c - - The working_fdt pointer was declared in common/fdt_support.c but was - not used there. Move it to common/cmd_fdt.c where it is used (it is - also used in lib_ppc/bootm.c). - - Signed-off-by: Gerald Van Baren - -commit e489b9c078e22b0d9e75f002cd2a1bd967e88f5e -Author: Kim Phillips -Date: Tue Jun 10 11:06:17 2008 -0500 - - fdt: unshadow global working fdt variable - - differentiate with local variables of the same name by renaming the - global 'fdt' variable 'working_fdt'. - - Signed-off-by: Kim Phillips - -commit e1eb0e25d9d8fd8efdfb93f670a417663f386022 -Author: Andy Fleming -Date: Tue Jun 10 18:49:34 2008 -0500 - - socrates: Fix PCI clk fix patch - - The submitted patch seems to have been more up-to-date, but an older patch was - already in the repository. This patch encompasses the differences - - Taken entirely from Sergei Poselenov - - Signed-off-by: Andy Fleming - -commit a75a57ef6e4b613c81434971e96ed70cf9ec9ba0 -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:02:29 2008 +0200 - - NAND FSL UPM: driver re-write using the hwcontrol callback - - This is a re-write of the NAND FSL UPM driver using the more universal - hwcontrol callback (instead of the cmdfunc callback). Here is a brief - list of furher modifications: - - - For the time being, the UPM setup writing the UPM array has been - removed from the driver and must now be done by the board specific - code. - - - The bus width definition in "struct fsl_upm_nand" is now in bits to - comply with the corresponding Linux driver and 8, 16 and 32 bit - accesses are supported. - - - chip->dev_read is only set if fun->dev_ready != NULL, which is - required for boards not connecting the R/B pin. - - - A few issue have been fixed with MxMR bit manipulation like in the - corresponding Linux driver. - - Note: I think the "io_addr" field of "struct fsl_upm" could be removed - as well, because the address is already determined by - "nand->IO_ADDR_[RW]", but I'm not 100% sure. - - This patch has been tested on a TQM8548 modules with the NAND chip - Micron MT29F8G08FABWP. - - This patch is based on the following patches posted to this list a few - minutes ago: - - PPC: add accessor macros to clear and set bits in one shot - 83xx/85xx/86xx: add more MxMR local bus definitions - - Signed-off-by: Wolfgang Grandegger - Acked-by: Anton Vorontsov - -commit 6beecfbb542992eede5831240cd58678274683a9 -Author: Wolfgang Grandegger -Date: Thu Jun 5 13:11:59 2008 +0200 - - MPC85xx: Beautify boot output of L2 cache configuration - - The boot output is now aligned poperly with other boot output - lines, e.g.: - - FLASH: 128 MB - L2: 512 KB enabled - - Signed-off-by: Wolfgang Grandegger - -commit 398415114f0a705163a14543e9fef03f734b1ffa -Author: Wolfgang Grandegger -Date: Wed Jun 4 12:45:22 2008 +0200 - - PPC: add accessor macros to clear and set bits in one shot - - PPC: add accessor macros to clear and set bits in one shot - - This patch adds macros from linux/include/asm-powerpc/io.h to clear and - set bits in one shot using the in_be32, out_be32, etc. accessor functions. - They are very handy to manipulate bits it I/O registers. - - This patch is required for my forthcoming FSL NAND UPM driver re-write and - the support for the TQM8548 module. - - Signed-off-by: Wolfgang Grandegger - -commit 4677988c7edc070c3786d3db7994abeca3ab82a0 -Author: Wolfgang Grandegger -Date: Wed Jun 4 13:52:17 2008 +0200 - - TQM: move TQM boards to board/tqc - - Move all TQM board directories to the vendor specific directory "tqc" - for modules from TQ-Components GmbH (http://www.tqc.de). - - Signed-off-by: Wolfgang Grandegger - -commit 6fab2fe72ca5bf95280cd52cdf378af3e506eb50 -Author: Wolfgang Grandegger -Date: Mon Jun 2 12:09:30 2008 +0200 - - 83xx/85xx/86xx: add more MxMR local bus definitions - - 83xx/85xx/86xx: add more MxMR local bus definitions - - This patch adds more macro definitions for the UPM Machine Mode Registers - They are copied from "include/mpc82xx.h" to simplify the merge of all 8xxx - common local bus definitions into include/asm-ppc/fsl_lbc.h. They are - required for my forthcoming FSL NAND UPM driver re-write and the support - for the TQM8548 module. - - This patch is based on the following two patches from Anton Vorontsov: - - http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06511.html - http://www.mail-archive.com/u-boot-users@lists.sourceforge.net/msg06587.html - - I leave coding style violation fixes, code beautification and name - corrections to somebody else ;-(. - - Signed-off-by: Wolfgang Grandegger - -commit c8c5fc266e4499e283c293ccb972863156aa4134 -Author: Anton Vorontsov -Date: Thu May 29 18:14:56 2008 +0400 - - 83xx/85xx: further localbus cleanups - - Merge mpc85xx.h's LBC defines to fsl_lbc.h. Also, adopt ACS names - from mpc85xx.h, so ACS_0b10 renamed to ACS_DIV4, ACS_0b11 to ACS_DIV2. - - Signed-off-by: Anton Vorontsov - -commit 42dbd667c88d496882d53e22656e89b654205492 -Author: Anton Vorontsov -Date: Wed May 28 18:20:15 2008 +0400 - - 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h - - This patch moves Freescale Localbus defines out of mpc83xx.h, so we could - use it on MPC85xx and MPC86xx processors. - - Signed-off-by: Anton Vorontsov - -commit 730b2fcf6fcd9eec3ea86fbb087c3f98aa23a769 -Author: Kumar Gala -Date: Thu May 29 11:22:06 2008 -0500 - - 85xx: Add setting of cache props in the device tree. - - Signed-off-by: Kumar Gala - -commit 4dbdb7681e243431530df0725627192a0c4aefda -Author: Kumar Gala -Date: Tue Jun 10 16:53:46 2008 -0500 - - 85xx: expose cpu identification - - The current cpu identification code is used just to return the name - of the processor at boot. There are some other locations that the name - is useful (device tree setup). Expose the functionality to other bits - of code. - - Also, drop the 'E' suffix and add it on by looking at the SVR version - when we print this out. This is mainly to allow the most flexible use - of the name. The device tree code tends to not care about the 'E' suffix. - - Signed-off-by: Kumar Gala - -commit 2329fe113d847e43cca8e4a0e4edd613b50b8492 -Author: Kim Phillips -Date: Tue Jun 10 13:25:24 2008 -0500 - - mpc83xx: MVBLM7: minor build fixups - - Signed-off-by: Kim Phillips - -commit a1293e549b56da135ef32ffca5b9d35a16aa6802 -Author: Andre Schwarz -Date: Tue Jun 10 09:14:05 2008 +0200 - - add MPC8343 based board mvBlueLYNX-M7 (board+make files) - - Add MPC8343 based board mvBlueLYNX-M7. - It's a single board stereo camera system. - Please read doc/README.mvblm7 for details. - - Signed-off-by: Andre Schwarz - Signed-off-by: Kim Phillips - -commit c005b93925ba49f07da2aa748527996d927e172f -Author: Andre Schwarz -Date: Tue Jun 10 09:13:16 2008 +0200 - - add MPC8343 based board mvBlueLYNX-M7 (doc+config) - - Add MPC8343 based board mvBlueLYNX-M7. - It's a single board stereo camera system. - Please read doc/README.mvblm7 for details. - - Signed-off-by: Andre Schwarz - Signed-off-by: Kim Phillips - -commit f9023afbdfd9f27e7c38f3cce965746e56d62dd3 -Author: Anton Vorontsov -Date: Thu May 29 18:14:56 2008 +0400 - - 83xx/85xx: further localbus cleanups - - move the BRx_* and ORx_* left behind in mpc85xx.h - - The same is needed for mpc8xx.h and mpc8260.h (defines are almost - the same, just few differences which needs some attention though). - - But the bad news for mpc8xx and mpc8260 is that there are a lot of users - of these defines. So this cleanup I'll leave for the "better times". - - Signed-off-by: Anton Vorontsov - Signed-off-by: Kim Phillips - -commit bf30bb1f7c954d7855d9b23624b33b00c50b4697 -Author: Anton Vorontsov -Date: Wed May 28 18:20:15 2008 +0400 - - 83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h - - This patch moves Freescale Localbus defines out of mpc83xx.h, so we could - use it on MPC85xx and MPC86xx processors. - - Signed-off-by: Anton Vorontsov - Acked-by: Andy Fleming - Signed-off-by: Kim Phillips - -commit d82b4fc0ce8cca95e857fc51022e841cb2dbee6a -Author: Tor Krill -Date: Mon Jun 2 15:09:30 2008 +0200 - - Add missing CSCONFIG_BANK_BIT_3 define to mpc83xx.h - - Signed-off-by: Tor Krill - Signed-off-by: Kim Phillips - -commit 3b904ccb93c3196727e2e9870cb1df903cab19ad -Author: Shinya Kuribayashi -Date: Mon Jun 9 23:37:44 2008 +0900 - - net: Conditional COBJS inclusion of network drivers - - Replace COBJS-y with appropriate driver config names. - - Signed-off-by: Shinya Kuribayashi - Signed-off-by: Ben Warren - -commit 2fb698bf50f4aff2485581a12fa634a07c040e4a -Author: Gerald Van Baren -Date: Mon Jun 9 21:02:17 2008 -0400 - - Use strncmp() for the fdt command - - Cleaner than doing multiple conditionals on characters. - - Signed-off-by: Gerald Van Baren - -commit 47abe8ab290d2721a8eeadff65b939e6af8c01b0 -Author: Gerald Van Baren -Date: Sat Jun 7 12:25:05 2008 -0400 - - The fdt boardsetup command criteria was not unique - - It was checking just for "b", which is not unique with respect to the - "boot" command. Change to check for "boa"[rdsetup]. - - Signed-off-by: Gerald Van Baren - -commit 2f08bfa9526bae4f461e043530cfb903fec0d273 -Author: David Gibson -Date: Tue May 20 17:19:11 2008 +1000 - - libfdt: Several cleanups to parameter checking - - This patch makes a couple of small cleanups to parameter checking of - libfdt functions. - - - In several functions which take a node offset, we use an - idiom involving fdt_next_tag() first to check that we have indeed been - given a node offset. This patch adds a helper function - _fdt_check_node_offset() to encapsulate this usage of fdt_next_tag(). - - - In fdt_rw.c in several places we have the expanded version - of the RW_CHECK_HEADER() macro for no particular reason. This patch - replaces those instances with an invocation of the macro; that's what - it's for. - - - In fdt_sw.c we rename the check_header_sw() function to - sw_check_header() to match the analgous function in fdt_rw.c, and we - provide an SW_CHECK_HEADER() wrapper macro as RW_CHECK_HEADER() - functions in fdt_rw.c - - Signed-off-by: David Gibson - -commit fec6d9ee7c10443f65ce1788ef818919167bbf2e -Author: Gerald Van Baren -Date: Tue Jun 3 20:34:45 2008 -0400 - - Remove the deprecated CONFIG_OF_FLAT_TREE - - Use CONFIG_OF_LIBFDT instead to support flattened device trees. It is - cleaner, has better functionality, and is better supported. - - Signed-off-by: Gerald Van Baren - -commit 62bcdda293efa752f8281fbd9da03822b27ce82f -Author: Gerald Van Baren -Date: Tue Jun 3 20:26:29 2008 -0400 - - Change the stxxst to CONFIG_OF_LIBFDT - - This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change - to CONFIG_OF_LIBFDT. - - WARNING: It appears that this board lost its ability to boot via a - flattened device tree prior to this changeset. - - WARNING: This conversion was untested because I do not have a board to - test it on. - - Signed-off-by: Gerald Van Baren - -commit 589c04271d129729a8b01391453851ab9cc4069c -Author: Gerald Van Baren -Date: Tue Jun 3 20:24:58 2008 -0400 - - Convert mpc7448hpc2 to CONFIG_OF_LIBFDT - - This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change - to CONFIG_OF_LIBFDT. - - WARNING: This conversion is untested because I do not have a board to - test it on. - - NOTE: The FDT blob (DTS) must have an /aliases/ethernet0 and (optionally) - /aliases/ethernet1 property for the ethernet to work. - - Signed-off-by: Gerald Van Baren - -commit ee1e35bede91debc8bff9b02f75574486033b652 -Author: Kumar Gala -Date: Thu May 29 01:21:24 2008 -0500 - - 85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define it - - Signed-off-by: Kumar Gala - -commit 3b9519fc50802436e417c839e69df7b2016cade5 -Author: Becky Bruce -Date: Wed May 14 13:10:04 2008 -0500 - - MPC85xx: Change traps.c to not reference non-addressable memory - - Currently, END_OF_RAM is used by the trap code to determine if - we should attempt to access the stack pointer or not. However, - on systems with a lot of RAM, only a subset of the RAM is - guaranteed to be mapped in and accessible. Change END_OF_RAM - to use get_effective_memsize() instead of using the raw ram - size out of the bd. - - Signed-off-by: Becky Bruce - -commit 7faddaecea52f585f538fdf9c2e61f85a789b19c -Author: Nobuhiro Iwamatsu -Date: Mon Jun 9 13:39:57 2008 +0900 - - sh: Renesas Solutions SH7763RDP board support - - SH7763RDP has SCIF, NOR Flash, Ethernet, USB host, LCDC and MMC. - In this patch, support SCIF, NOR Flash, and Ethernet. - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit 60179098a95eaa972007d7ec58e4c1588029720f -Author: Nobuhiro Iwamatsu -Date: Fri Jun 6 16:24:13 2008 +0900 - - sh: Add support Renesas SH7763 - - Renesas SH7763 has 3 SCIF, MMC, LCDC, Ethernet and other. - This patch supprts CPU register's header file. - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit 08c5fabe181d663eec0feba5ecd02c0b78934a52 -Author: Nobuhiro Iwamatsu -Date: Fri Jun 6 16:16:08 2008 +0900 - - sh: SH7763 SCIF support - - SH7763 has 3 SCIF channels. SCIF0 and 1 are same register constitution, - but only SCIF2 is different. This patch work all SCIF channel. - - Signed-off-by: Nobuhiro Iwamatsu - Signed-off-by: Nobuhiro Iwamatsu - -commit 79b51ff8205f0354d5300570614c1d2db499679c -Author: Shinya Kuribayashi -Date: Sat Jun 7 20:51:59 2008 +0900 - - [MIPS] cpu/mips/Makefile: Split [CS]OBJS onto separate lines - - Also get rid of some #ifdefs in *.c files. - - Signed-off-by: Shinya Kuribayashi - -commit 8bde63eb3f79d68f693201528dafc8ae7aa087de -Author: Shinya Kuribayashi -Date: Sat Jun 7 20:51:56 2008 +0900 - - [MIPS] Rename Alchemy processor configs into CONFIG_SOC_* - - CONFIG_SOC_AU1X00 - - Common Alchemy Au1x00 stuff. All Alchemy processor based machines - need to have this config as a system type specifier. - - CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200, - CONFIG_SOC_AU1500, CONFIG_SOC_AU1550 - - Machine type specifiers. Each port should have one of aboves. - - Signed-off-by: Shinya Kuribayashi - -commit cc49cadeeb8bb2f0ae3fdc13af7051ae59f083bc -Author: Stuart Wood -Date: Fri May 30 16:05:28 2008 -0400 - - env_nand.c: Added bad block management for environment variables - - Modified to check for bad blocks and to skipping over them when - CFG_ENV_RANGE has been defined. - CFG_ENV_RANGE must be larger than CFG_ENV_SIZE and aligned to the NAND - flash block size. - - Signed-off-by: Stuart Wood - Signed-off-by: Scott Wood - -commit 279726bd00558e80263d44581c44167625b7fb9a -Author: Becky Bruce -Date: Wed May 14 13:09:58 2008 -0500 - - MPC86xx: Change traps.c to not reference non-addressable memory - - Currently, END_OF_RAM is used by the trap code to determine if - we should attempt to access the stack pointer or not. However, - on systems with a lot of RAM, only a subset of the RAM is - guaranteed to be mapped in and accessible. Change END_OF_RAM - to use get_effective_memsize() instead of using the raw ram - size out of the bd to prevent us from trying to access - non-mapped memory. - - Signed-off-by: Becky Bruce - -commit 338cc038461a6c7709c5b86fd9a240209338a1ae -Author: Wolfgang Denk -Date: Fri Jun 6 14:28:14 2008 +0200 - - tools/mkimage: fix compiler warnings on some systems. - - Signed-off-by: Wolfgang Denk - -commit b2815f79288d4da7a3ba18bdbd05120ce09d5622 -Author: Stefan Roese -Date: Fri Jun 6 16:10:41 2008 +0200 - - ppc4xx: Fix misspelled CONFIG_440SPE/440EPX/GRX config options - - We use upper case letters for the AMCC processor defines (like - CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and - not CONFIG_440SPe. This patch fixes the last misspelled config options. - - Signed-off-by: Stefan Roese - -commit 72675dc6c06a48846d180106161d49dd714383cc -Author: Stefan Roese -Date: Fri Jun 6 15:55:21 2008 +0200 - - ppc4xx: Unify AMCC's board config files (part 3/3) - - This patch series unifies the AMCC eval board ports by introducing - a common include header for all AMCC eval boards: - - include/configs/amcc-common.h - - This header now includes all common configuration options/defines which - are removed from the board specific headers. - - The reason for this is ease of maintenance and unified look and feel - of all AMCC boards. - - Signed-off-by: Stefan Roese - -commit 490f204096d6e2c9940f67816f154a8125bab116 -Author: Stefan Roese -Date: Fri Jun 6 15:55:03 2008 +0200 - - ppc4xx: Unify AMCC's board config files (part 2/3) - - This patch series unifies the AMCC eval board ports by introducing - a common include header for all AMCC eval boards: - - include/configs/amcc-common.h - - This header now includes all common configuration options/defines which - are removed from the board specific headers. - - The reason for this is ease of maintenance and unified look and feel - of all AMCC boards. - - Signed-off-by: Stefan Roese - -commit a8a11a9ed046b480a16e47a158f8f5300028dfa6 -Author: Stefan Roese -Date: Fri Jun 6 15:54:31 2008 +0200 - - ppc4xx: Unify AMCC's board config files (part 1/3) - - This patch series unifies the AMCC eval board ports by introducing - a common include header for all AMCC eval boards: - - include/configs/amcc-common.h - - This header now includes all common configuration options/defines which - are removed from the board specific headers. - - The reason for this is ease of maintenance and unified look and feel - of all AMCC boards. - - Signed-off-by: Stefan Roese - -commit 0e38c938ed4bcadb4f4fc1419a541431e94fc202 -Author: Remy Bohmer -Date: Thu Jun 5 13:03:36 2008 +0200 - - DM9000 fix status check fail 0x6d error for trizeps board - - According to the Application Notes of the DM9000, only the 2 bits 0:1 of - the status byte need to be checked to identify a valid packet in the fifo - - But, The several different Application Notes do not all speak the same - language on these bits. They do not disagree, but only 1 Application Note - noted explicitly that only these 2 bits need to be checked. - Even the datasheets do not mention anything about these 2 bits. - - Because the old code, and the kernel check the whole byte, I left this piece - untouched. - - However, I tested all board/DM9000[A|E|EP] devices with this 2 bit check, so - it should work. - - Notice, that the 2nd iteration through this receive loop (when a 2nd packet is - in the fifo) is much shorter now, compared to the older U-boot driver code, - so that we can maybe run into a hardware condition now that was never seen - before, or maybe was seen very unfrequently. - - Additionaly added a cleanup of a stack variable. - - Signed-off-by: Remy Bohmer - Signed-off-by: Ben Warren - -commit 7daf2ebe9196dd67131a06d85049c3a8a08ca413 -Author: Shinya Kuribayashi -Date: Thu Jun 5 22:29:00 2008 +0900 - - [MIPS] Update header - - - Fix traditional KSEG names - - Replace PHYSADDR with CPHYSADDR - - Signed-off-by: Shinya Kuribayashi - -commit f0d5a6f060d00358b85c62a921a423ea8df71184 -Author: Shinya Kuribayashi -Date: Thu Jun 5 22:29:00 2008 +0900 - - [MIPS] mips_config.mk: Misc fixes - - - Kill redundant `-pipe' (this will be added by $(TOPDIR)/config.mk) - - Modify comments - - Signed-off-by: Shinya Kuribayashi - -commit 5f64d21c9a2998794f255b469165b91f092dfc2d -Author: Shinya Kuribayashi -Date: Thu Jun 5 22:29:00 2008 +0900 - - [MIPS] Kill unused inclusions - - Signed-off-by: Shinya Kuribayashi - -commit a55d48174cfd1a5bc184159513f48dcbbe409c83 -Author: Shinya Kuribayashi -Date: Thu Jun 5 22:29:00 2008 +0900 - - [MIPS] lib_mips/time.c: Fix CP0 count register usage and timer routines - - MIPS port has two problems in timer routines. One is now we assume CFG_HZ - equals to CP0 counter frequency, but this is wrong. CFG_HZ has to be 1000 - in the U-Boot system. - - The other is we don't have a proper time management counter like timestamp - other ARCHs have. We need the 32-bit millisecond clock counter. - - This patch introduces timestamp and CYCLES_PER_JIFFY. timestamp is a - 32-bit non-overflowing CFG_HZ counter, and CYCLES_PER_JIFFY is the number - of calculated CP0 counter cycles in a CFG_HZ. - - STRATEGY: - - * Fix improper CFG_HZ value to have 1000 - - * Use CFG_MIPS_TIMER_FREQ for timer counter frequency, instead. - - * timer_init: initialize timestamp and set up the first timer expiration. - Note that we don't need to initialize CP0 count/compare registers here - as they have been already zeroed out on the system reset. Leave them as - they are. - - * get_timer: calculate how many timestamps have been passed, then return - base-relative timestamp. Make sure we can easily count missed timestamps - regardless of CP0 count/compare value. - - * get_ticks: return the current timestamp, that is get_timer(0). - - Most parts are from good old Linux v2.6.16 kernel. - - v2: - - Remove FIXME comments as they turned out to be trivial. - - Use CP0 compare register as a global variable for expirelo. - - Kill a global variable 'cycles_per_jiffy'. Use #define CYCLES_PER_JIFFY - instead. - - Signed-off-by: Shinya Kuribayashi - -commit 199e4f657c8af42efe3fb3ba1d1104eb6bb28c25 -Author: Shinya Kuribayashi -Date: Thu Jun 5 22:29:00 2008 +0900 - - [MIPS] lib_mips/time.c: Fix udelay - - What we have to do is just to wait for given micro-seconds. No need to - take into account current time, get_timer and CFG_HZ. - - Signed-off-by: Shinya Kuribayashi - -commit c7e38e413ae69120d3e51f132c7cb1d6b3514d03 -Author: Shinya Kuribayashi -Date: Thu Jun 5 22:28:59 2008 +0900 - - [MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros - - We already have many pre-defined CP0 access macros in . - This patch replaces mips_{compare,count}_set and mips_count_get with - existing macros. - - Signed-off-by: Shinya Kuribayashi - -commit 6b52cfe16cd539935e32bd8cf19146522e462a4d -Author: Remy Bohmer -Date: Tue Jun 3 15:48:17 2008 +0200 - - Get rid of annoying/superfluous bad-checksum warning message - - U-boot can complain a lot about 'checksum bad' when it is attached to the network. - It is annoying for ordinary users who start to doubt the network connection - in general when they see messages like this. - - This is caused by the routine NetCksumOk() which cannot handle IP-headers longer - than 20 bytes. Those packages can be ignored anyway by U-boot, so we trash them - now before checking the checksum. - - Signed-off-by: Remy Bohmer - Signed-off-by: Ben Warren - -commit d6ee5fa40c26970d39990c6fc4a2f20a97822650 -Author: Remy Bohmer -Date: Wed Jun 4 10:47:25 2008 +0200 - - Fix order for reading rx-status registers in 32bit mode of DM9000 - - A last minute cleanup before submitting the DM9000A patch series yesterday introduced - a bug in reading the rx-status registers in 32bit mode only. - This patch repairs this. - - Signed-off-by: Remy Bohmer - Signed-off-by: Ben Warren - -commit 98291e2e689096420465074cce926b226d2e71b4 -Author: Remy Bohmer -Date: Tue Jun 3 15:26:26 2008 +0200 - - DM9000: Some minor code cleanups - - Some lines of the U-boot DM9000x driver are longer than 80 characters, or - need some other minor cleanup. - - Signed-off-by: Remy Bohmer - Signed-off-by: Ben Warren - -commit 850ba7555dbd4ca8d14fc475b864d534797adab3 -Author: Remy Bohmer -Date: Tue Jun 3 15:26:25 2008 +0200 - - DM9000: Make driver work properly for DM9000A - - The DM9000A network controller does not work with the U-boot DM9000x driver. - Analysis showed that many incoming packets are lost. - - The DM9000A Application Notes V1.20 (section 5.6.1) recommend that the poll to - check for a valid rx packet be done on the interrupt status register, not - directly by performing the dummy read and the rx status check as is currently - the case in the u-boot driver. - - When the recommended poll is done as suggested the driver starts working - correctly on 10Mbit/HD, but on 100MBit/FD packets come in faster so that there - can be more than 1 package in the fifo at the same time. - - The driver must perform the rx-status check in a loop and read and handle all - packages until there is no more left _after_ the interrupt RX flag is set. - - This change has been tested with DM9000A, DM9000E, DM9000EP. - - Signed-off-by: Remy Bohmer - Signed-off-by: Ben Warren - -commit fbcb7ece0ea1e364180f1cf963e0fa0ce7f6560d -Author: Remy Bohmer -Date: Tue Jun 3 15:26:24 2008 +0200 - - DM9000: Improve eth_reset() routine - - According to the application notes of the DM9000 v1.22 chapter 5.2 bullet 2, the - reset procedure must be done twice to properly reset the DM9000 by means of software. - This errata is not needed anymore for the DM9000A, but it does not bother it. - - This change has been tested with DM9000A, DM9000E, DM9000EP. - - Signed-off-by: Remy Bohmer - Signed-off-by: Ben Warren - -commit acba31847fad9ae40708cc2c9f3a634ec35f3416 -Author: Remy Bohmer -Date: Tue Jun 3 15:26:23 2008 +0200 - - DM9000: improve eth_send() routine - - The eth_send routine of the U-boot DM9000x driver does not match the - DM9000 or DM9000A application notes/programming guides. - - This change improves the stability of the DM9000A network controller. - - This change has been tested with DM9000A, DM9000E, DM9000EP. - - Signed-off-by: Remy Bohmer - Signed-off-by: Ben Warren - -commit 134e266253c02a7832560da59d394989c4f64453 -Author: Remy Bohmer -Date: Tue Jun 3 15:26:22 2008 +0200 - - DM9000: repair debug logging - - It seems that the debugging code of the DM9000x driver in U-boot has not been - compiled for a long time, because it cannot compile... - - Also rearranged some loglines to get more useful info while debugging. - - Signed-off-by: Remy Bohmer - Signed-off-by: Ben Warren - -commit a101361bfe23c120321e45d114c0603b8e0763e9 -Author: Remy Bohmer -Date: Tue Jun 3 15:26:21 2008 +0200 - - DM9000: Add data bus-width auto detection. - - The U-boot DM9000x driver contains a compile time bus-width definition for - the databus connected to the network controller. - - This compile check makes the code unclear, inflexible and is unneccessary. - It can be asked to the network controller what its bus-width is by reading bits - 6 and 7 of the interrupt status register. - - The linux kernel already uses a runtime mechanism to determine this bus-width, - so the implementation below looks somewhat like that implementation. - - This change has been tested with DM9000A, DM9000E, DM9000EP. - - Signed-off-by: Remy Bohmer - Signed-off-by: Ben Warren - -commit 63a0afa0c32e5f4ea98a9439542870072437404d -Author: Stefan Roese -Date: Wed Jun 4 19:19:20 2008 +0200 - - ppc4xx: Fix problem with SDRAM init in bamboo NAND booting port - - This patch fixes a problem spotted by Eugene O'Brian (thanks Eugene) - introduced by the commit: - - ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S - - With this patch SDRAM will get initialized again and booting from NAND - is working again. - - Signed-off-by: Stefan Roese - Acked-by: Eugene O'Brien - -commit 9ef1cbef1a649e3779298b0e663be4865cbbbfbc -Author: Wolfgang Denk -Date: Tue May 27 14:19:30 2008 +0200 - - Socrates: Fix PCI bus frequency report - - Signed-off-by: Sergei Poselenov - -commit 8ec6e332eace0ee78c71ee5f645d12b06813b86f -Author: Tor Krill -Date: Thu May 29 11:10:30 2008 +0200 - - Fix incorrect switch for IF_TYPE in part.c - - Use correct field in block_dev_desc_t when writing interface type in - dev_print. Error introduced in 574b3195. - - Also added fix from Martin Krause - - Signed-off-by: Tor Krill - -commit b64b8a0bd310935b70af69ac970952f2b364ae56 -Author: Andre Schwarz -Date: Tue May 27 10:25:39 2008 +0200 - - Add size #defines for Altera Cyclone-II EP2C8 and EP2C20. - - Signed-off-by: Andre Schwarz - -commit 35ef877f0a8f6232cdef748f442fed5accb2b641 -Author: Peter Tyser -Date: Thu May 22 18:56:52 2008 -0500 - - Additional fix to readline_into_buffer() with CONFIG_CMDLINE_EDITING before relocating - - Removed unneeded command line history initialization. Also, the original - code would access the 'initted' variable before relocation to SDRAM - which resulted in erratic behavior since the bss is not initialized when - executing from flash. - - Signed-off-by: Peter Tyser - -commit 22f371b63038a4ecab04068877c1089e51a01ba1 -Author: Grant Erickson -Date: Wed May 21 13:28:30 2008 -0700 - - PPC4xx: Simplified post_word_{load, store} - - This patch simplifies post_word_{load,store} by using the preprocessor - to eliminate redundant, copy-and-pasted code. - - Signed-off-by: Grant Erickson - -commit 9c048b523413ae5f3ff34e00cf57569c3368ab51 -Author: Vasiliy Leoenenko -Date: Wed May 7 21:25:33 2008 +0400 - - cfi_flash: enable M18 flash chips family support. - - Added new command set ID. Buffered write command processing is changed - in order to support M18 flash chips family. - - Signed-off-by: Alexey Korolev - Signed-off-by: Vasiliy Leonenko - -commit 93c56f212ccdadc182018f0769cb284426b88f1d -Author: Vasiliy Leoenenko -Date: Wed May 7 21:24:44 2008 +0400 - - cfi_flash: support of long cmd in U-boot. - - Some NOR flash chips needs support of commands with length grether than max - value size of uchar. For example all M18 family chips use 0x1ff command in - buffered write mode as value of program loops count. - - Signed-off-by: Alexey Korolev - Signed-off-by: Vasiliy Leonenko - -commit 4d91d1df2f16b511ab80dec50c80e050ba0d841e -Author: Stefan Roese -Date: Fri May 16 11:06:06 2008 +0200 - - DTT: Issue one-shot command on AD7414 (LM75 code) to read temp - - On AD7414 the first value upon bootup is not read correctly. - This is most likely because of the 800ms update time of the - temp register in normal update mode. To get current values - each time we issue the "dtt" command including upon powerup - we switch into one-short mode. - - This patch fixes the problem on AD7414 equipped boards (Sequoia, - Canyonlands etc), that temp value printed in the bootup log was - incorrect. - - Signed-off-by: Stefan Roese - -commit de5bfcf7b0425e032be12698252dbaa6b65a28c0 -Author: Matthias Fuchs -Date: Fri May 30 16:55:06 2008 +0200 - - ppc4xx: Cleanup CPCI405 variant's config file - - This patch removes some dead code from CPCI405 board's - config files. JFFS2 support is also removed. It's not used and - CPCI4052 does not build anymore without some size reduction. - - Signed-off-by: Matthias Fuchs - -commit 2918eb9d42bc705fcbd18c9fcc39d15ff2843c65 -Author: Kenneth Johansson -Date: Thu May 29 16:32:33 2008 +0200 - - Remove shell variable UNDEF_SYM. - - UNDEF_SYM is a shell variable in the main Makefile used to force the - linker to add all u-boot commands to the final image. It has no use here. - - Signed-off-by: Kenneth Johansson - -commit 8c66497e06bf803489c589df58ee591d71033274 -Author: Haavard Skinnemoen -Date: Fri May 16 11:10:35 2008 +0200 - - Add support for environment in SPI flash - - This is pretty incomplete...it doesn't handle reading the environment - before relocation, it doesn't support redundant environment, and it - doesn't support embedded environment. But apart from that, it does - seem to work. - - Signed-off-by: Haavard Skinnemoen - -commit b6368467e6a97f225e0a5fd7bfc5c7598ef5ddc4 -Author: Haavard Skinnemoen -Date: Fri May 16 11:10:34 2008 +0200 - - SPI Flash: Add "sf" command - - This adds a new command, "sf" which can be used to manipulate SPI - flash. Currently, initialization, reading, writing and erasing is - supported. - - Signed-off-by: Haavard Skinnemoen - -commit d25ce7d24cc0f93881559f4009175ea305af65e8 -Author: Haavard Skinnemoen -Date: Fri May 16 11:10:33 2008 +0200 - - SPI Flash subsystem - - This adds a new SPI flash subsystem. - - Currently, only AT45 DataFlash in non-power-of-two mode is supported, - but some preliminary support for other flash types is in place as - well. - - Signed-off-by: Haavard Skinnemoen - -commit 60445cb5c3eb77ed1a07f2d908eef09174483698 -Author: Hans-Christian Egtvedt -Date: Fri May 16 11:10:32 2008 +0200 - - atmel_spi: Driver for the Atmel SPI controller - - This adds a driver for the SPI controller found on most AT91 and AVR32 - chips, implementing the new SPI API. - - Changed in v4: - - Update to new API - - Handle zero-length transfers appropriately. The user may send a - zero-length SPI transfer with SPI_XFER_END set in order to - deactivate the chip select after a series of transfers with chip - select active. This is useful e.g. when polling the status - register of DataFlash. - - Signed-off-by: Haavard Skinnemoen - -commit d255bb0e78d1cac5b7c8c98cb77a095f5f16de0d -Author: Haavard Skinnemoen -Date: Fri May 16 11:10:31 2008 +0200 - - SPI API improvements - - This patch gets rid of the spi_chipsel table and adds a handful of new - functions that makes the SPI layer cleaner and more flexible. - - Instead of the spi_chipsel table, each board that wants to use SPI - gets to implement three hooks: - * spi_cs_activate(): Activates the chipselect for a given slave - * spi_cs_deactivate(): Deactivates the chipselect for a given slave - * spi_cs_is_valid(): Determines if the given bus/chipselect - combination can be activated. - - Not all drivers may need those extra functions however. If that's the - case, the board code may just leave them out (assuming they know what - the driver needs) or rely on the linker to strip them out (assuming - --gc-sections is being used.) - - To set up communication parameters for a given slave, the driver needs - to call spi_setup_slave(). This returns a pointer to an opaque - spi_slave struct which must be passed as a parameter to subsequent SPI - calls. This struct can be freed by calling spi_free_slave(), but most - driver probably don't want to do this. - - Before starting one or more SPI transfers, the driver must call - spi_claim_bus() to gain exclusive access to the SPI bus and initialize - the hardware. When all transfers are done, the driver must call - spi_release_bus() to make the bus available to others, and possibly - shut down the SPI controller hardware. - - spi_xfer() behaves mostly the same as before, but it now takes a - spi_slave parameter instead of a spi_chipsel function pointer. It also - got a new parameter, flags, which is used to specify chip select - behaviour. This may be extended with other flags in the future. - - This patch has been build-tested on all powerpc and arm boards - involved. I have not tested NIOS since I don't have a toolchain for it - installed, so I expect some breakage there even though I've tried - fixing up everything I could find by visual inspection. - - I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and - DataFlash drivers posted as a follow-up. I'd like some help testing - other boards that use the existing SPI API. - - But most of all, I'd like some comments on the new API. Is this stuff - usable for everyone? If not, why? - - Changed in v4: - - Build fixes for various boards, drivers and commands - - Provide common struct spi_slave definition that can be extended by - drivers - - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate - - Make default bus and mode build-time configurable - - Override default SPI bus ID and mode on mx32ads and imx31_litekit. - - Changed in v3: - - Add opaque struct spi_slave for controller-specific data associated - with a slave. - - Add spi_claim_bus() and spi_release_bus() - - Add spi_free_slave() - - spi_setup() is now called spi_setup_slave() and returns a - struct spi_slave - - soft_spi now supports four SPI modes (CPOL|CPHA) - - Add bus parameter to spi_setup_slave() - - Convert the new i.MX32 SPI driver - - Convert the new MC13783 RTC driver - - Changed in v2: - - Convert the mpc8xxx_spi driver and the mpc8349emds board to the - new API. - - Signed-off-by: Haavard Skinnemoen - Tested-by: Guennadi Liakhovetski - -commit 289011207d999b2e4085150d2aa30d547ad9b800 -Author: Haavard Skinnemoen -Date: Fri May 16 11:10:30 2008 +0200 - - Move definition of container_of() to common.h - - AVR32 and AT91SAM9 both have their own identical definitions of - container_of() taken from the Linux kernel. Move it to common.h so - that all architectures can use it. - - container_of() is already used by some drivers, and will be used - extensively by the new and improved SPI API. - - Signed-off-by: Haavard Skinnemoen - -commit 110e006fe67fb4a6e1719ae6956c79b7ffc0148b -Author: Haavard Skinnemoen -Date: Fri May 16 11:08:11 2008 +0200 - - soft_i2c: Pull SDA high before reading - - Spotted by Dean Capindale. - - Systems that support open-drain GPIO properly are allowed provide an - empty I2C_TRISTATE define. However, this means that we need to be - careful not to drive SDA low when the slave is expected to respond. - - This patch adds a missing I2C_SDA(1) to read_byte() required to - tristate the SDA line on systems that support open-drain GPIO. - - Signed-off-by: Haavard Skinnemoen - -commit 3c1de1a6d36be9eee284a6c596a86e94f19cc5b2 -Author: Stefan Roese -Date: Mon May 19 11:34:53 2008 +0200 - - ppc4xx: Remove implementations of testdram() - - This patch removes the used testdram() implementations of the board - that are maintained by myself. - - Signed-off-by: Stefan Roese - -commit bbeff30cbd1c5d551eb0ad1c2239ec01844c0b0a -Author: Stefan Roese -Date: Mon Jun 2 17:37:28 2008 +0200 - - ppc4xx: Remove superfluous dram_init() call or replace it by initdram() - - Historically the 405 U-Boot port had a dram_init() call in early init - stage. This function was still called from start.S and most of the time - coded in assembler. This is not needed anymore (since a long time) and - boards should implement the common initdram() function in C instead. - - This patch now removed the dram_init() call from start.S and removes the - empty implementations that are scattered through most of the 405 board - ports. Some older board ports really implement this dram_init() though. - These are: - - csb272 - csb472 - ERIC - EXBITGEN - W7OLMC - W7OLMG - - I changed those boards to call this assembler dram_init() function now - from their board specific initdram() instead. This *should* work, but please - test again on those platforms. And it is perhaps a good idea that those - boards use some common 405 SDRAM initialization code from cpu/ppc4xx at - some time. So further patches welcome here. - - Signed-off-by: Stefan Roese - -commit 192f90e272b3989ee7b4a666d1fdab831f20f8d2 -Author: Stefan Roese -Date: Mon Jun 2 17:22:11 2008 +0200 - - ppc4xx: Use new 4xx SDRAM controller enable defines in common ECC code - - Signed-off-by: Stefan Roese - -commit 39b32be18cd33b53a84065edcd4e465165cc5564 -Author: Stefan Roese -Date: Mon Jun 2 17:20:03 2008 +0200 - - ppc4xx: Fix common ECC generation code for 440GP style platforms - - This patch makes the common 4xx ECC code really usable on 440GP style - platforms. - - Since the IBM DDR controller used on 440GP/GX/EP/GR is not register - compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT - we need to make some processor dependant defines used later on by the - driver. - - Signed-off-by: Stefan Roese - -commit ec724f883ee3f3925e6c55027e8ffa70ada83303 -Author: Stefan Roese -Date: Mon Jun 2 17:13:55 2008 +0200 - - ppc4xx: Change Kilauea to use the common DDR2 init function - - This patch changes the kilauea and kilauea_nand (for NAND booting) - board port to not use a board specific DDR2 init routine anymore. Now - the common code from cpu/ppc4xx is used. - - Thanks to Grant Erickson for all his basic work on this 405EX early - bootup. - - Signed-off-by: Stefan Roese - -commit 17ceb069b85fbb9269c4dc09b2c237f88334c5ba -Author: Stefan Roese -Date: Mon Jun 2 14:59:21 2008 +0200 - - ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part2 - - This patch now adds a new header file (asm-ppc/ppc4xx-sdram.h) for all - ppc4xx related SDRAM/DDR/DDR2 controller defines. - - Signed-off-by: Stefan Roese - -commit 36ea16f6a066ccb046e91ebce4f326b69f4c0569 -Author: Stefan Roese -Date: Mon Jun 2 14:57:41 2008 +0200 - - ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 - - This patch removes all SDRAM related defines from the PPC4xx headers - ppc405.h and ppc440.h. This is needed since now some 405 PPC's use - the same SDRAM controller as 440 systems do (like 405EX and 440SP). - - It also introduces new defines for the equipped SDRAM controller based on - which PPC variant is used. There new defines are: - - used on 405GR/CR/EP and some Xilinx Virtex boards. - - used on 440GP/GX/EP/GR. - - used on 440EPx/GRx. - - used on 405EX/r/440SP/SPe/460EX/GT. - - Signed-off-by: Stefan Roese - -commit 64852d09e06dd6db2b2db2a3c59bc2db176a54d6 -Author: Stefan Roese -Date: Mon Jun 2 14:35:44 2008 +0200 - - ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S - - This patch consolidates the 405 and 440 parts of the NAND booting code - selected via CONFIG_NAND_SPL. Now common code is used to initialize the - SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc. - Only *after* running from this location, nand_boot() is called. - - Please note that the initsdram() call is now moved from nand_boot.c - to start.S. I experienced problems with some boards like Kilauea - (405EX), which don't have internal SRAM (OCM) and relocation needs to - be done to SDRAM before the NAND controller can get accessed. When - initdram() is called later on in nand_boot(), this can lead to problems - with variables in the bss sections like nand_ecc_pos[]. - - Signed-off-by: Stefan Roese - Acked-by: Scott Wood - -commit 8a24c07ba5da2c72ad1f05e3eb8a463750200c98 -Author: Grant Erickson -Date: Thu May 22 14:44:24 2008 -0700 - - ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling - - This patch (Part 2 of 2): - - * Rolls up a suite of changes to enable correct primordial stack and - global data handling when the data cache is used for such a purpose - for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). - - * Related to the first, unifies DDR2 SDRAM and ECC initialization by - eliminating redundant ECC initialization implementations and moving - redundant SDRAM initialization out of board code into shared 4xx - code. - - * Enables MCSR visibility on the 405EX(r). - - * Enables the use of the data cache for initial RAM on - both AMCC's Kilauea and Makalu and removes a redundant - CFG_POST_MEMORY flag from each board's CONFIG_POST value. - - - Removed, per Stefan Roese's request, defunct memory.c file for - Makalu and rolled sdram_init from it into makalu.c. - - With respect to the 4xx DDR initialization and ECC unification, there - is certainly more work that can and should be done (file renaming, - etc.). However, that can be handled at a later date on a second or - third pass. As it stands, this patch moves things forward in an - incremental yet positive way for those platforms that utilize this - code and the features associated with it. - - Signed-off-by: Grant Erickson - Signed-off-by: Stefan Roese - -commit c821b5f120bedf73867513466412587c6912a8f8 -Author: Grant Erickson -Date: Thu May 22 14:44:14 2008 -0700 - - ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling - - This patch (Part 1 of 2): - - * Rolls up a suite of changes to enable correct primordial stack and - global data handling when the data cache is used for such a purpose - for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). - - * Related to the first, unifies DDR2 SDRAM and ECC initialization by - eliminating redundant ECC initialization implementations and moving - redundant SDRAM initialization out of board code into shared 4xx - code. - - * Enables MCSR visibility on the 405EX(r). - - * Enables the use of the data cache for initial RAM on - both AMCC's Kilauea and Makalu and removes a redundant - CFG_POST_MEMORY flag from each board's CONFIG_POST value. - - - Removed, per Stefan Roese's request, defunct memory.c file for - Makalu and rolled sdram_init from it into makalu.c. - - With respect to the 4xx DDR initialization and ECC unification, there - is certainly more work that can and should be done (file renaming, - etc.). However, that can be handled at a later date on a second or - third pass. As it stands, this patch moves things forward in an - incremental yet positive way for those platforms that utilize this - code and the features associated with it. - - Signed-off-by: Grant Erickson - Signed-off-by: Stefan Roese - -commit a439680019e06171d4a5694b7992accce87f590e -Author: Grant Erickson -Date: Wed May 21 13:28:30 2008 -0700 - - PPC4xx: Simplified post_word_{load, store} - - This patch simplifies post_word_{load,store} by using the preprocessor - to eliminate redundant, copy-and-pasted code. - - Signed-off-by: Grant Erickson - -commit f979690ee337450b2030aba128f95b7a8d9881c0 -Author: Kumar Gala -Date: Thu May 15 15:13:08 2008 -0500 - - Fix warnings from gcc-4.3.0 build on a ppc host - - * The cfi_flash.c memset fix actual allows the board to boot so there is - a bit more going on here than just resolving warnings associated with - uninitialized variables. - - * include/asm/bitops.h:302: warning: '__swab32p' is static but used in - inline function 'ext2_find_next_zero_bit' which is not static - - Signed-off-by: Kumar Gala - -commit 9b124a68346ce9605b6e1fcf79e1021541cdba9e -Author: Becky Bruce -Date: Wed May 14 13:09:51 2008 -0500 - - MPC512x: Change traps.c to not reference non-addressable memory - - Currently, END_OF_RAM is used by the trap code to determine if - we should attempt to access the stack pointer or not. However, - on systems with a lot of RAM, only a subset of the RAM is - guaranteed to be mapped in and accessible. Change END_OF_RAM - to use get_effective_memsize() instead of using the raw ram - size out of the bd. - - Signed-off-by: Becky Bruce - -commit 81673e9ae14b771cd13faf19947192599cae3959 -Author: Kumar Gala -Date: Tue May 13 19:01:54 2008 -0500 - - Make sure common.h is the first include. - - If common.h isn't first we can get CONFIG_ options defined in the - board config file ignored. This can cause an issue if any of those - config options impact the size of types of data structures - (eg CONFIG_PHYS_64BIT). - - Signed-off-by: Kumar Gala - -commit 95d449ad4de79dd32b1705b8a4d3550f1e9081e3 -Author: Marian Balakowicz -Date: Tue May 13 15:53:29 2008 +0200 - - Avoid initrd and logbuffer area overlaps - - Add logbuffer to reserved LMB areas to prevent initrd allocation - from overlaping with it. - - Make sure to use correct logbuffer base address. - - Signed-off-by: Marian Balakowicz - -commit 6956d53d9934862507f83f0e3255dfd4662e7482 -Author: Sascha Laue -Date: Tue May 13 13:29:54 2008 +0200 - - lwmon5: add memory-pattern-test to FPGA POST. - -commit e34a0e911b6a1568d0ca864234fbd0ee060d9b35 -Author: Becky Bruce -Date: Thu May 8 19:02:51 2008 -0500 - - PPC: 86xx Add bat registers to reginfo command - - Signed-off-by: Becky Bruce - -commit d5b9b8cdb8b6eb3a8b0f5d9909d69ccc9c703ed9 -Author: Becky Bruce -Date: Fri May 9 15:41:35 2008 -0500 - - PPC: Add print_bats() to lib_ppc/bat_rw.c - - This function prints the values of all the BAT register - pairs - I needed this for debug earlier this week; adding it to - lib_ppc so others can use it (and add it to reginfo commands - if so desired). - - Signed-off-by: Becky Bruce - -commit c148f24c15743a02e855636e6bed013bd121f7f2 -Author: Becky Bruce -Date: Thu May 15 21:29:04 2008 -0500 - - PPC: Change lib_ppc/bat_rw.c to use high bats - - Currently, this code only deals with BATs 0-3, which makes - it useless on systems that support BATs 4-7. Add the - support for these registers. - - Signed-off-by: Becky Bruce - -commit 31d826722434931e1152a09d140187dcf72f8aac -Author: Becky Bruce -Date: Thu May 8 19:02:12 2008 -0500 - - PPC: Create and use CONFIG_HIGH_BATS - - Change all code that conditionally operates on high bat - registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS - instead of the myriad ways this is done now. Define the option - for every config for which high bats are supported (and - enabled by early boot, on parts where they're not always - enabled) - - Signed-off-by: Becky Bruce - -commit aa3b8bf9c30065bb2ea852799d32db5020598495 -Author: Wolfgang Grandegger -Date: Wed May 28 19:55:19 2008 +0200 - - E1000: Add support for the 82541GI LF Intel Pro 1000 GT Desktop Adapter - - Signed-off-by: Wolfgang Grandegger - Signed-off-by: Ben Warren - -commit ff36fbb2e7583fb808eef773f511489c7a9c2df3 -Author: TsiChung Liew -Date: Wed May 28 13:06:25 2008 -0500 - - ColdFire: Add 10 base ethernet support for mcf5445x - - Signed-off-by: TsiChung Liew - Signed-off-by: Ben Warren - -commit 1a9fcc4b765599db24fa9c32293599f24c7a19ba -Author: Jason McMullan -Date: Fri May 30 00:53:38 2008 +0900 - - mips: Add an 'include/asm/errno.h', like all other architectures - - All other u-boot architectures have an include/asm/errno.h, so - this change adds it to the mips include/asm-mips headers also. - - Stolen from Linux 2.6.25. - - Signed-off-by: Jason McMullan - -commit e2ad8426624bac457acc6925b6ff408e9bf20466 -Author: Shinya Kuribayashi -Date: Fri May 30 00:53:38 2008 +0900 - - [MIPS] : Update coprocessor register access macros - - Signed-off-by: Shinya Kuribayashi - -commit 1a3adac81c292f2ee76e43cdeb2fbe8f915fe194 -Author: Shinya Kuribayashi -Date: Fri May 30 00:53:38 2008 +0900 - - [MIPS] : Update register / bit field definitions - - Signed-off-by: Shinya Kuribayashi - -commit bf462ae450a7f2eeeddc699ed345b391e3263540 -Author: Shinya Kuribayashi -Date: Fri May 30 00:53:37 2008 +0900 - - [MIPS] : CodinygStyle cleanups - - No functional changes. - - Signed-off-by: Shinya Kuribayashi - -commit 89a1550ec6b74452274a7a23127936e2c7eec711 -Author: Jason McMullan -Date: Fri May 30 00:53:37 2008 +0900 - - mips: If CONFIG_CMD_SPI is defined, call spi_init() - - The mips architecture currently does not call 'spi_init()' in the generic - board initialization routine is CONFIG_CMD_SPI is defined. - - This patch rectifies that problem. - - Signed-off-by: Jason McMullan - Signed-off-by: Shinya Kuribayashi - -commit e996bc339b0f39f6c0b29b1455ba7eb318b023d3 -Author: Jason McMullan -Date: Fri May 30 00:53:37 2008 +0900 - - [MIPS] lib_mips/board.c: Add nand_init - - This patch adds the standard 'nand_init()' call to the mips generic - 'board_init_r()' call, bringing MIPS in line with the other architectures. - - Signed-off-by: Jason McMullan - Signed-off-by: Shinya Kuribayashi - -commit d6ac2ed893c2168738aee01579d6283af8d37045 -Author: Scott Wood -Date: Thu May 22 10:49:46 2008 -0500 - - Remove prototypes of nand_init() in favor of including nand.h. - - Likewise with onenand_init(). - - Signed-off-by: Scott Wood - -commit 229c56f07a82eacda8c8720cb146fc9be0f6db54 -Author: Scott Wood -Date: Thu May 22 10:49:00 2008 -0500 - - Make onenand_uboot.h self-sufficient. - - Don't assume types are provided by previously included headers. - - Signed-off-by: Scott Wood - -commit 9723bbb46abb7b2ca24eead5114a3faa58060c20 -Author: Dirk Behme -Date: Wed Jan 16 14:26:59 2008 +0100 - - nand: Correct NAND erase percentage output - - For NAND erase sizes smaller than one NAND erase block, erase - percentage output becomes grater than 100% e.g. - - -- cut -- - > nand info - Device 0: NAND 64MiB 1,8V 8-bit, sector size 16 KiB - > nand erase 0x100000 0x2000 - NAND erase: device 0 offset 0x100000, size 0x2000 - Erasing at 0x100000 -- 200% complete. - OK - > - -- cut -- - - Correct this and give user a warning that more is erased than specified: - - -- cut -- - > nand erase 0x100000 0x2000 - NAND erase: device 0 offset 0x100000, size 0x2000 - Warning: Erase size 0x00002000 smaller than one erase block 0x00004000 - Erasing 0x00004000 instead - Erasing at 0x100000 -- 100% complete. - OK - > - -- cut -- - - Signed-off-by: Dirk Behme - -commit 5922db6c0948506be91e0de44e7a6863a18a417f -Author: Stelian Pop -Date: Tue May 13 17:31:24 2008 +0200 - - Cleanup nand_info[] declaration. - - The nand_info array is declared as extern in several .c files. - Those days, nand.h contains a reference to the array, so there is - no need to declare it elsewhere. - - Signed-off-by: Stelian Pop - Signed-off-by: Scott Wood - -commit 135f0a7488af2947adbe4b40b79280bdfe5e9886 -Author: Scott Wood -Date: Mon May 19 09:30:43 2008 -0500 - - NAND: Provide a sane default for NAND_MAX_CHIPS. - - This allows the header to be included regardless of whether a board's - config file provides NAND-related defininitions. - - Signed-off-by: Scott Wood - -commit a8092c021d27f27f4b323b7d49979ca01b3fc19d -Author: Haavard Skinnemoen -Date: Mon May 26 12:19:10 2008 +0200 - - avr32: Fix theoretical race in udelay() - - If the specified delay is very short, the cycle counter may go past the - "end" time we are waiting for before we get around to reading it. - - Fix it by checking the different between the cycle count "now" and the - cycle count at the beginning. This will work as long as the delay - measured in number of cycles is below 2^31. - - Signed-off-by: Haavard Skinnemoen - -commit 48ea623eae8674793372e3e7c95e72e5a44d7a95 -Author: Haavard Skinnemoen -Date: Wed May 21 13:01:09 2008 +0200 - - avr32: Compile atmel_mci.o conditionally - - Remove #ifdef CONFIG_MMC from the source file and use conditional - compilation in the Makefile instead. - - Signed-off-by: Haavard Skinnemoen - -commit e92a5bf8330654e33ac13f6b3058634e58f5d1c0 -Author: Haavard Skinnemoen -Date: Thu May 22 12:28:25 2008 +0200 - - avr32: Fix wrong error flags in atmel_mci driver - - Make sure we check for CRC errors when sending commands that use CRC - checking. - - Reported-by: Gururaja Hebbar K R - Signed-off-by: Haavard Skinnemoen - -commit 7a96ddadd13e6ac9a829affce9b6f8823f580e49 -Author: Haavard Skinnemoen -Date: Wed May 21 11:10:59 2008 +0200 - - avr32: Fix two warnings in atmel_mci.c - - The warnings are harmless but annoying. Let's fix them. - - Signed-off-by: Haavard Skinnemoen - -commit a23e277c4a3a2bbc42d237aae29da3a8971e757f -Author: Haavard Skinnemoen -Date: Mon May 19 11:36:28 2008 +0200 - - avr32: Rework SDRAM initialization code - - This cleans up the SDRAM initialization and related code a bit, and - allows faster booting. - - * Add definitions for EBI and internal SRAM to asm/arch/memory-map.h - * Remove memory test from sdram_init() and make caller responsible - for verifying the SDRAM and determining its size. - * Remove base_address member from struct sdram_config (was sdram_info) - * Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT - * Add support for a common STK1000 hack: 16MB SDRAM instead of 8. - - Signed-off-by: Haavard Skinnemoen - -commit 95107b7c028806919630bf02c653aa8f4f867c94 -Author: Haavard Skinnemoen -Date: Mon May 19 11:27:37 2008 +0200 - - avr32: Do stricter stack checking in the exception handler - - Don't do a stack dump if the stack pointer is outside the memory area - reserved for stack. - - Signed-off-by: Haavard Skinnemoen - -commit caf83ea888a0220f41747d0b7748fa43b4a4bd49 -Author: Haavard Skinnemoen -Date: Fri May 2 15:32:57 2008 +0200 - - avr32: Use the same entry point for reset and exception handling - - Since the reset vector is always aligned to a very large boundary, we - can save a couple of KB worth of alignment padding by placing the - exception vectors at the same address. - - Deciding which one it is is easy: If we're handling an exception, the - CPU is in Exception mode. If we're starting up after reset, the CPU is - in Supervisor mode. So this adds a very minimal overhead to the reset - path (only executed once) and the exception handling path (normally - never executed at all.) - - Signed-off-by: Haavard Skinnemoen - -commit 0c16eed2189a190bd5655b33c029f809a9b31128 -Author: Haavard Skinnemoen -Date: Fri May 2 15:24:22 2008 +0200 - - avr32: Put memset in its own section - - All C code is compiled with -ffunction-sections -fdata-sections. - Assembly functions should get their own sections as well so that - everything looks consistent. - - Signed-off-by: Haavard Skinnemoen - -commit 3ace2527ba80bd2fe1bceaab50d0b3c4fb5dd020 -Author: Haavard Skinnemoen -Date: Fri May 2 15:21:40 2008 +0200 - - avr32: Rename pm_init() as clk_init() and make SoC-specific - - pm_init() was always more about clock initialization than anything - else. Dealing with PLLs, clock gating and such is also inherently - SoC-specific, so move it into a SoC-specific directory. - - Signed-off-by: Haavard Skinnemoen - -commit 4f5972c3b2454c22957f2842cfe64ec8118e015b -Author: Haavard Skinnemoen -Date: Wed Apr 30 16:15:57 2008 +0200 - - avr32: Use new-style Makefile for the at32ap platform - - This makes it easier to avoid compiling certain files later. - - Signed-off-by: Haavard Skinnemoen - -commit a9b2bb78a1bd8ebdb633509bdd1c8134d527b213 -Author: Haavard Skinnemoen -Date: Wed Apr 30 14:36:47 2008 +0200 - - avr32: Remove unused file cpu/at32ap/pm.c - - Signed-off-by: Haavard Skinnemoen - -commit 44453b25b06426eef0b7b2fa7c026fdf19ce34f2 -Author: Haavard Skinnemoen -Date: Wed Apr 30 14:19:28 2008 +0200 - - avr32: Clean up the HMATRIX code - - Rework the HMATRIX configuration interface so that it becomes easier - to configure the HMATRIX for boards with special needs, and add new - parts. - - The HMATRIX header file has been split into a general, - chip-independent part with register definitions, etc. and a - chip-specific part with SFR bitfield definitions and master/slave - identifiers. - - Signed-off-by: Haavard Skinnemoen - -commit 0a2e48792dd372c90b80059f3235e67a567e16fc -Author: Haavard Skinnemoen -Date: Thu Nov 22 12:14:11 2007 +0100 - - avr32: Add support for the ATSTK1006 board - - This is a replacement for ATSTK1002 with 64MB SDRAM and NAND flash on - board. It's currently in production and will be available soon. - - Signed-off-by: Haavard Skinnemoen - -commit 781eb9a1e4af4bd34c138e6126ec5cc6dd4b5440 -Author: Haavard Skinnemoen -Date: Tue Apr 29 12:53:05 2008 +0200 - - avr32: Get rid of the .flashprog section - - The .flashprog section was only needed back when we were running - directly from flash, and it's even more useless on NGW100 since it - uses the CFI flash driver which never used this workaround in the - first place. - - Remove it on STK1000 as well, and get rid of all the associated code and - annotations. - - Signed-off-by: Haavard Skinnemoen - -commit cdd42c0c7a5205fc380912d83229069a71ea3abf -Author: Haavard Skinnemoen -Date: Wed Apr 30 13:09:56 2008 +0200 - - avr32: Use correct condition around macb clock accessors - - get_macb_pclk_rate() and get_macb_hclk_rate() should be available when - the chip has a MACB controller, not when it has a USART. - - Signed-off-by: Haavard Skinnemoen - -commit f793a3581901ff39c2abb94012d9bbc8573ccf02 -Author: David Brownell -Date: Wed Apr 16 22:57:58 2008 -0700 - - avr32: Disable the AP7000 internal watchdog on startup - - This patch forces the watchdog off in all cases. That will at least - get rid of the constant reboot cycle, though it won't let the watchdog - actually run in the new kernels: its probe() comes up with a polite - warning. - - Signed-off-by: Haavard Skinnemoen - -commit 55ac7a7490b55da56659f95d82a0c83b9756df27 -Author: David Brownell -Date: Fri Feb 22 12:54:39 2008 -0800 - - avr32: stk1002 and ngw100 convergence - - Make STK1002 and NGW100 boards act more alike: - - STK boards can use as many arguments as NGW - - STK boards don't need to manage FPGAs either - - NGW commands should match STK ones - - Also spell U-Boot right in prompts for STK1002 and NGW100. - - Signed-off-by: David Brownell - [haavard.skinnemoen@atmel.com: update STK100[34] as well] - Signed-off-by: Haavard Skinnemoen - -commit 5e1882df6a3efc7de5524d28cea4ecde7d163d54 -Author: Sergei Poselenov -Date: Tue May 27 13:47:00 2008 +0200 - - Socrates: Fix PCI bus frequency report - - Signed-off-by: Sergei Poselenov - -commit 791e1dba8de76ad8e762a7badb869f224a1f8b82 -Author: Sergei Poselenov -Date: Tue May 27 11:49:13 2008 +0200 - - Socrates: Added USB support. - - Signed-off-by: Sergei Poselenov - -commit 5a904e5637cff1d708dc67098004f83ba9e84c54 -Author: Sergei Poselenov -Date: Tue May 27 11:35:02 2008 +0200 - - USB: add new configuration variable CONFIG_PCI_OHCI_DEVNO - - In case of several PCI USB controllers on a board this variable - specifys which controller to use. - See doc/README.generic_usb_ohci for details. - - Signed-off-by: Sergei Poselenov - -commit 2f7468aeba60e1288030a8d007c4e63bd3f13221 -Author: Sergei Poselenov -Date: Tue May 27 10:36:07 2008 +0200 - - Socrates: add support for DS75 Digital Thermo Sensor on I2C bus. - - Signed-off-by: Sergei Poselenov - -commit 83e9d7a2614d4006b92690afa3390c291734267e -Author: Sergei Poselenov -Date: Mon May 26 18:16:04 2008 +0200 - - Socrates: Config file cleanup. - - Signed-off-by: Sergei Poselenov - -commit 602cac1389b755b223272f2328a47e6f8c240848 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat May 24 12:47:46 2008 +0200 - - MAKEALL: add at91 list - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 290ef6436838b1cc013bd67e0e0495c9eb3e23c0 -Author: Ron Madrid -Date: Fri May 23 15:37:05 2008 -0700 - - Add Marvell 88E1118 support for TSEC - - Signed-off-by: Ron Madrid - Signed-off-by: Ben Warren - -commit 557b377d8bfc8b833b6e749457bcdfa298331a24 -Author: Jens Gehrlein -Date: Mon May 5 14:06:11 2008 +0200 - - smc911x: add 16 bit support - - Signed-off-by: Jens Gehrlein - Signed-off-by: Ben Warren - -commit 6324e5bec8825f7fee3026ffbd394454ae8b53fb -Author: Christian Eggers -Date: Wed May 21 21:29:10 2008 +0200 - - Fix endianess conversion in usb_ohci.c - - Sorry, I forgot this line: - - Signed-off-by: Christian Eggers - - I think this must be swapped (result may be equal). - -commit c918261c6d9f265f88baf70f8a73dfe6f0cb9596 -Author: Christian Eggers -Date: Wed May 21 22:12:00 2008 +0200 - - USB: replace old swap_ with proper endianess conversion macros - - Signed-off-by: Christian Eggers - Signed-off-by: Markus Klotzbuecher - -commit fb63939b4fe140849cdba69f9e64a3e0e2f3ce1c -Author: Christian Eggers -Date: Wed May 21 21:29:10 2008 +0200 - - Fix endianess conversion in usb_ohci.c - - Signed-off-by: Christian Eggers - Signed-off-by: Markus Klotzbuecher - -commit 477434c63c2ea5baa5c6c4e43500786f436511ff -Author: Sergei Poselenov -Date: Thu May 22 01:15:53 2008 +0200 - - USB: add support for multiple PCI OHCI controllers - - Add new configuration variable CONFIG_PCI_OHCI_DEVNO. - In case of several PCI USB controllers on a board this variable - specifys which controller to use. - - Also add USB support for sokrates board. - - See doc/README.generic_usb_ohci for details. - - Signed-off-by: Sergei Poselenov - Signed-off-by: Markus Klotzbuecher - -commit ce6754df61cbe23b5b73d095a00ac9a8504b3d77 -Author: Wolfgang Denk -Date: Wed May 21 16:56:08 2008 +0200 - - Fix some whitespace issues - - introduced by 53677ef18 "Big white-space cleanup." - - Signed-off-by: Wolfgang Denk - -commit 4416603aeb06861b468b06a981e52c3ff805db7b -Author: York Sun -Date: Mon May 12 14:36:39 2008 -0500 - - Make ads5121 out-of-tree compiling safe - - Reuse the existing DIU driver in board/freescale/common. - - Signed-off-by: York Sun - -commit 0e1bad47cd345c76c91a64caf41011e431b62599 -Author: York Sun -Date: Mon May 5 10:20:01 2008 -0500 - - Adding DIU support for Freescale 5121ADS - - Add DIU and cfb console support to FSL 5121ADS board. - - Use #define CONFIG_VIDEO in config file to enable fb console. - - Signed-off-by: York Sun - -commit a48ff68d235e671176f6b496c44246dbe5e0a93f -Author: York Sun -Date: Mon May 5 10:20:00 2008 -0500 - - Replace DPRINTF with debug - - Remove DPRINTF macro and replace it with generic debug macro. - - Signed-off-by: York Sun - -commit 3b80c5f574ad7f6e1c55a68f42752b427fdf778d -Author: York Sun -Date: Mon May 5 10:19:59 2008 -0500 - - Move pixel clock setting to board file - - The clock divider has different format in 5121 and 8610. This patch moves it to - board specific code. - - Signed-off-by: York Sun - -commit 53677ef18e25c97ac613349087c5cb33ae5a2741 -Author: Wolfgang Denk -Date: Tue May 20 16:00:29 2008 +0200 - - Big white-space cleanup. - - This commit gets rid of a huge amount of silly white-space issues. - Especially, all sequences of SPACEs followed by TAB characters get - removed (unless they appear in print statements). - - Also remove all embedded "vim:" and "vi:" statements which hide - indentation problems. - - Signed-off-by: Wolfgang Denk - -commit 2f845dc2bdf461bfee9fa25823f769f5db9eba0b -Author: Sergei Poselenov -Date: Thu May 8 17:46:23 2008 +0200 - - socrates: fix second TSEC configuration (it is actually TSEC3) - - Signed-off-by: Sergei Poselenov - -commit 793670c3c0f0f72caead62f0be9fc3d9fbc6060f -Author: Sergei Poselenov -Date: Thu May 8 14:17:08 2008 +0200 - - Fixed reset for socrates - - Signed-off-by: Sergei Poselenov - -commit e18575d5f589a62e19c70d471d4b4e27cad3af56 -Author: Sergei Poselenov -Date: Wed May 7 15:10:49 2008 +0200 - - socrates: changes to support FDT - - Signed-off-by: Sergei Poselenov - Signed-off-by: Wolfgang Denk - -commit 5d108ac8f435924c624cd6aaacd44f35f5cf94c0 -Author: Sergei Poselenov -Date: Wed Apr 30 11:42:50 2008 +0200 - - Initial support for "Socrates" board - - Signed-off-by: Sergei Poselenov - -commit 0e15ddd11f1a84c465e434eb051d2ef08ef02b9b -Author: Yuri Tikhonov -Date: Thu May 8 15:46:42 2008 +0200 - - POST: replace the LOGBUFF_INITIALIZED flag in gd->post_log_word (1 << 31) with the GD_FLG_LOGINIT flag in gd->flags. - - This way we become able to utilize the full post_log_word for POST - activities (overwise, POST ECC, which has 0x8000 ID, could be - erroneously treated as started in post_output_backlog() even if there - was actually no POST ECC run (because of OCM POST failure, for - example). - - Signed-off-by: Yuri Tikhonov - -commit 7845d49094c81321021b50a4dbb8864d2f3777e4 -Author: Yuri Tikhonov -Date: Thu May 8 15:46:02 2008 +0200 - - POST: mark OCM test as POST_STOP - - Signed-off-by: Ilya Yanok - -commit 28a385065882d6cb6ac5f443311ff87887ed7c13 -Author: Yuri Tikhonov -Date: Thu May 8 15:45:26 2008 +0200 - - POST: add POST_STOP flag - - Don't run futher tests in case of a test fails that is marked as - POST_STOP. - - Signed-off-by: Ilya Yanok - Signed-off-by: Yuri Tikhonov - -commit a525145d8110d15b4389d23c3ea8a78f22509d3f -Author: Yuri Tikhonov -Date: Thu May 8 15:44:16 2008 +0200 - - POST: switch CFG_POST_OCM with CFG_POST_CODEC (workaround) - - Switch the OCM testid with the codec one. The reason is that current - implementation requires the POST_ROM testid to fit into lower 16 - bits, and the codec test will never run with POST_ROM hopefully. - - Signed-off-by: Ilya Yanok - -commit 8b96c788d58f7cb85a89ee3f19c9b335d22443cd -Author: Yuri Tikhonov -Date: Thu May 8 15:43:28 2008 +0200 - - lwmon5: enable OCM post test on lwmon5 board - - Signed-off-by: Ilya Yanok - -commit 6e8ec682268493b8d098f99e17b1ce71b4448977 -Author: Yuri Tikhonov -Date: Thu May 8 15:42:47 2008 +0200 - - POST: OCM test added. - - Added OCM test to POST layer. This version runs before all other tests - but doesn't yet interrupt post sequence on failure. - - Signed-off-by: Ilya Yanok - Signed-off-by: Yuri Tikhonov - -commit 6891260bdd935a382c95d9fa333922b0dfded68a -Author: Yuri Tikhonov -Date: Thu May 8 15:40:39 2008 +0200 - - POST: typo fix - - Signed-off-by: Ilya Yanok - -commit 727f63334676e760877d43bfb8f0e9331ac8b101 -Author: Hebbar -Date: Tue May 20 02:16:36 2008 -0700 - - common/usb.c: fix incorrect escape sequence - - Signed off by: Gururaja Hebbar - -commit 4ce1e23b5e12283579828b3d23e8fd6e1328a7aa -Author: York Sun -Date: Thu May 15 15:26:27 2008 -0500 - - Fix 8313ERDB board configuration - - Change LCRR clock ratio from 2 to 4 to commodate VSC7385. - Correct TSEC1 vs TSEC2 assignment. - Define ETHADDR and ETH1ADDR always. - - Signed-off-by: York Sun - Signed-off-by: Timur Tabi - -commit 2c289e320dcfb3760e99cf1d765cb067194a1202 -Author: Jon Loeliger -Date: Mon May 19 09:47:25 2008 -0500 - - mpc86xx: Removed unused and unconfigured memory test code. - - Besides, other common code exists. - - Signed-off-by: Jon Loeliger - -commit 180a90abdae72587c0f679edf8991455e559440d -Author: Wolfgang Denk -Date: Mon May 19 12:47:11 2008 +0200 - - Release v1.3.3 - - Update CHANGELOG for release. - - Signed-off-by: Wolfgang Denk - -commit 16bedc661de0dae767b1377d8413373a3fbcfa79 -Author: Stefan Roese -Date: Mon May 19 07:14:38 2008 +0200 - - ppc4xx: Canyonlands: Disable PCIe0/SATA in dev-tree depending on selection - - When SATA is selected (via jumper J6) we need to disable the first PCIe - node in the device tree, so that Linux doesn't initialize it. Otherwise - the Linux SATA driver will fail to detect the devices. - - The same goes the other way around too. So if PCIe is selected we need - to disable the SATA node in the device tree. - - This is because PCIe port 0 and SATA on 460EX share the same pins - (multiplexed) and we have to configure in U-Boot which peripheral is - enabled. - - Signed-off-by: Stefan Roese - -commit 3cc27b426aeefe2930f911692e9df3143fb2565f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 18 19:09:58 2008 +0200 - - i386: Fix multiple definitions of __show_boot_progress - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 311f3446930c1e64c12026c1cfd00500b05be52d -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 18 19:09:57 2008 +0200 - - sc530_spunk: add missing SOBJS entry - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit a559317143b4f95927b08cd388707e6f077e95fa -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 18 19:09:56 2008 +0200 - - sc520_spunk: Fix flash - - flash.c:593: warning: dereferencing type-punned pointer will break strict-aliasing rules - flash.c:398: error: label at end of compound statement - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 91f221317af64191ee8caf303ea9305943158691 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 18 19:09:49 2008 +0200 - - drivers/pcmcia: add missing i82365 - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit dd223944132f97ffa52977ea95e5a52428f5cc2f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 18 19:09:47 2008 +0200 - - i386/bootm: remove unused var - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit a9da341df19b32ad2ecb58ce529f7e4fada7814e -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 18 19:09:45 2008 +0200 - - example/gitignore: update with all generated examples - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit a38dc3ea8614f8b0c41e432b445a9959b9711295 -Author: Wolfgang Denk -Date: Thu May 15 00:42:45 2008 +0200 - - TQM8272: fix out-of-tree building - - ...and add to MAKEALL script - - Signed-off-by: Wolfgang Denk - -commit 4f805c1e3a60b9263da8ec3bcd1f45edcefa7dcf -Author: Wolfgang Denk -Date: Wed May 14 23:34:53 2008 +0200 - - environment: fix bug introduced by commit a8409f4f1ac8 - - env_get_char is not a function, but a pointer to one. - - Signed-off-by: Wolfgang Denk - -commit 0c11935cd62ca1f65eeb228ff4c848440d4553bf -Author: Gary Jennejohn -Date: Wed May 14 13:39:22 2008 +0200 - - ppc4xx: QUAD100HD: Allow the environment to be put into flash. - - After moving TEXT_BASE the value for CFG_ENV_ADDR was incorrect. Also - use a redundant environment. - - Signed-off-by: Gary Jennejohn - -commit cda2a4a9961fd4341b7db305cb22fc05957e8b77 -Author: Wolfgang Denk -Date: Wed May 14 13:55:30 2008 +0200 - - Fix config files for out-of-tree building - - Several board/<...>/config.mk files include dynamically built (by - the Makefile) config files but used the wrong file name of - $(TOPDIR)/board/$(BOARDDIR)/config.tmp - instead if the correct - $(OBJTREE)/board/$(BOARDDIR)/config.tmp - - The bug is nasty because the build result is correct for the (normal) - in-tree builds, and because 'sinclude' is used no errors get raised - even for out-of-tree build tests. But out-of-tree builds use an - incomplete and thus usually incorrect configuration... - - Signed-off-by: Wolfgang Denk - -commit 2dd7082e06d580404010b06fe4e0e8b7038a00c8 -Author: Stefan Roese -Date: Wed May 14 13:40:03 2008 +0200 - - ppc4xx: Fix bogus Canyonlands config.mk - - This patch fixes the canyonlands config.mk file to enable correct - out-of-tree builds. Thanks to Wolfgang Denk for spotting this. - - Signed-off-by: Stefan Roese - -commit fdd1247a66d788a3446244f6fde9955a93c26322 -Author: Stefan Roese -Date: Wed May 14 10:32:32 2008 +0200 - - ppc4xx: Individual handling of ddr2_fixed.c for canyonlands_nand build - - Canyonlands has a file ddr2_fixed.c which needs special treatment when - building in separate directory. It has to be linked to build directory - otherwise it is not seen. - - Signed-off-by: Stefan Roese - -commit a8409f4f1ac84c36273c1a1e341189662521bcfb -Author: Wolfgang Denk -Date: Wed May 14 12:22:49 2008 +0200 - - environment: cleanup prototype declarations of env functions. - - Signed-off-by: Wolfgang Denk - -commit cf39b07948015c480b72a6e732cf7d839aa93a9e -Author: Wolfgang Denk -Date: Wed May 14 12:21:48 2008 +0200 - - linkstation_HGLAN: Fix out of tree building. - - Signed-off-by: Wolfgang Denk - -commit 085551c05ca09e6c491ea11a1c6727a36776a545 -Author: Stefan Roese -Date: Wed May 14 10:32:32 2008 +0200 - - ppc4xx: Individual handling of ddr2_fixed.c for canyonlands_nand build - - Canyonlands has a file ddr2_fixed.c which needs special treatment when - building in separate directory. It has to be linked to build directory - otherwise it is not seen. - - Signed-off-by: Stefan Roese - -commit 1510b82d50615f344e89d42533e8224cce067dc0 -Author: Wolfgang Denk -Date: Tue May 13 23:15:52 2008 +0200 - - Makefile: fix "error: version_autogenerated.h: No such file or directory" - - Signed-off-by: Wolfgang Denk - -commit 54694a91428f6c3280fe1ee0923488a1e7e8dbc4 -Author: Stelian Pop -Date: Tue May 13 17:31:24 2008 +0200 - - Cleanup nand_info[] declaration. - - The nand_info array is declared as extern in several .c files. - Those days, nand.h contains a reference to the array, so there is - no need to declare it elsewhere. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 70fab1908fc1734a403711eaabbef546bc4b77dc -Author: Stefan Roese -Date: Tue May 13 20:22:01 2008 +0200 - - ppc4xx: Add 405EX(r) revision C PVR definitions and detection code - - Signed-off-by: Stefan Roese - -commit 65dcfa79204f4750b905a173a5365e0b2eb6c2f6 -Author: Wolfgang Denk -Date: Mon May 12 01:11:21 2008 +0200 - - Revert "pci: Add CONFIG_PCI_SKIP_HOST_BRIDGE config option" - - This reverts commit 55774b512fdf63c0516d441cc5da7c54bbffb7f2 - which broke many PowerPC boards. - -commit ee0cfa70803a3e629ea581a9b216f8ecef402bfc -Author: Wolfgang Denk -Date: Mon May 12 00:56:28 2008 +0200 - - Revert "Avoid initrd and logbuffer area overlaps" - - This reverts commit 1b5605ca57fbb364f4d78eeee28b974ed875e888 - which breaks building on all PPC boards that don't use a log buffer. - -commit 02b9b22446e3d7ad6a6382be17a1ce79a7de589b -Author: Nick Spence -Date: Sat May 10 14:02:04 2008 -0700 - - Fix offset calculation for multi-type legacy images. - - Calculation of tail was incorrect when size % 4 == 0. - - New code removes the conditional and does the same thing but with arithmetic - - Signed-off-by: Nick Spence - -commit c9dca3c3f37d2647aec4509b24b16d15882ae3e4 -Author: Wolfgang Denk -Date: Mon May 12 00:40:58 2008 +0200 - - Revert "Change env_get_char from a global function ptr to a function." - - This reverts commit c0559be371b2a64b1a817088c3308688e2182f93 - which is known to break booting from dataflash and NAND. - -commit 20e5ed137483823aaea5178169f3b144c7a4d9e0 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 11 23:13:57 2008 +0200 - - API: remove duplicate syscall check - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 67e3beb52c320b0a31cf030716c99392cde2d532 -Author: Stelian Pop -Date: Fri May 9 21:46:51 2008 +0200 - - AT91: Cleanup unused config header file definitions. - - CONFIG_ENV_OVERWRITE is commented out in the config header files, - so let's cleanup the files by removing the whole definition. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 19883aede2ac0a522493bfb2b35a7dbb200071b1 -Author: Stelian Pop -Date: Thu May 8 14:52:34 2008 +0200 - - Support AT91CAP9 revC CPUs - - The AT91CAP9 revC CPU has a few differences over the previous, - revB CPU which was distributed in small quantities only (revA was - an internal Atmel product only). - - The revC silicon needs a special initialisation sequence to - switch from the internal (imprecise) RC oscillator to the - external 32k clock. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 098b7b4b441b12c2a64dd517930f43c793542759 -Author: Stelian Pop -Date: Thu May 8 14:52:33 2008 +0200 - - Use custom logo for Atmel boards - - This patch adds a custom vendor logo for the Atmel AT91 boards. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 761c70b80cdd3bead40146b96a8e713d6ae01632 -Author: Stelian Pop -Date: Thu May 8 14:52:32 2008 +0200 - - AT91SAM9RLEK: hook up the ATMEL LCD driver - - This patch makes the necessary adaptations (PIO configurations and - defines in config header file) to hook up the Atmel LCD driver to the - AT91SAM9RLEK board. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 56a2479cd7fecabdd91348a775b2801dd2e65c7f -Author: Stelian Pop -Date: Thu May 8 14:52:31 2008 +0200 - - AT91SAM9263EK: hook up the ATMEL LCD driver - - This patch makes the necessary adaptations (PIO configurations and - defines in config header file) to hook up the Atmel LCD driver to the - AT91SAM9263EK board. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 820f2a958325061a446115f3035e48e4726b3390 -Author: Stelian Pop -Date: Thu May 8 14:52:30 2008 +0200 - - AT91SAM9261EK: hook up the ATMEL LCD driver - - This patch makes the necessary adaptations (PIO configurations and - defines in config header file) to hook up the Atmel LCD driver to the - AT91SAM9261EK board. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit c139b17d20c8371c1e0a8d7fb27c11050cf86304 -Author: Stelian Pop -Date: Thu May 8 14:52:29 2008 +0200 - - AT91CAP9ADK: hook up the ATMEL LCD driver - - This patch makes the necessary adaptations (PIO configurations and - defines in config header file) to hook up the Atmel LCD driver to the - AT91CAP9ADK board. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 39cf480484fcce5c04a590ee1c30be0c17b02c34 -Author: Stelian Pop -Date: Fri May 9 21:57:18 2008 +0200 - - Add ATMEL LCD driver - - This patch adds support for the ATMEL LCDC driver which is used on some - AT91 and AVR platforms. - - Is has been tested with the AT91CAP9ADK, AT91SAM9261EK, AT91SAM9263EK and - AT91SAM9RLEK boards. Adaptation for AVR32 should probably be easy. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 2118ebb44dc40f8117c94950fd95799a9ef821b2 -Author: Stelian Pop -Date: Thu May 8 18:52:25 2008 +0200 - - AT91SAM9RLEK support - - This patch adds support for the AT91SAM9RL chip and the AT91SAM9RLEK - board. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 8e429b3eee23927c1222679f6b6f53667b21595c -Author: Stelian Pop -Date: Thu May 8 18:52:23 2008 +0200 - - AT91SAM9263EK support - - This patch adds support for the AT91SAM9263 chip and the AT91SAM9263EK - board. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit d99a8ff66d8ae87e5c87590ed2e4ead629540607 -Author: Stelian Pop -Date: Thu May 8 20:52:22 2008 +0200 - - AT91SAM9261EK support - - This patch adds support for the AT91SAM9261 chip and the AT91SAM9261EK - board. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 86c8c8a414988c50104a3b02c29f50af2be738c0 -Author: Stelian Pop -Date: Thu May 8 20:52:21 2008 +0200 - - AT91SAM9260EK: Fix dataflash offsets in CONFIG_BOOTCOMMAND - - This patch fixes the dataflash offsets used in CONFIG_BOOTCOMMAND - in order to cope with the changes in DataFlash partitionning scheme - (cset c3a60cb3). - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 96996ac25d5222611a8888968db6e53a6d3726da -Author: Stelian Pop -Date: Thu May 8 20:52:20 2008 +0200 - - AT91SAM9260EK: Normalize BOOTARGS - - This patch adapts CONFIG_BOOTARGS to the chosen boot method (boot from - DataFlash or from NAND), and gives to Linux a fully specified mtdparts - variable. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 79f0cb6e9c54d31a1d9e3f5e226a9bebc3c3a47a -Author: Stelian Pop -Date: Thu May 8 20:52:19 2008 +0200 - - AT91SAM9260EK: Normalize SPI timings - - This patch changes the SPI timings to closely match the ones - used by the Linux kernel and the Atmel's own bootstrap project. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit c1212b2f5c5ed440bf8e9ebc8e4fd7488858b935 -Author: Stelian Pop -Date: Thu May 8 20:52:18 2008 +0200 - - AT91SAM9260EK: Handle 8 or 16 bit NAND - - The Atmel boards can handle 8 or 16 bit NAND memories. This patch - makes the support configurable in the board config header file - (CFG_NAND_DBW_8 or CFG_NAND_DBW_16). - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit ab52640fc01624e208424e527af0b7b3a5a65a12 -Author: Stelian Pop -Date: Thu May 8 20:52:17 2008 +0200 - - AT91CAP9ADK: Fix dataflash offsets in CONFIG_BOOTCOMMAND - - This patch fixes the dataflash offsets used in CONFIG_BOOTCOMMAND - in order to cope with the changes in DataFlash partitionning scheme - (cset c3a60cb3). - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 3267508ec4c9e74c39ee41c9ae6951ad185fe270 -Author: Stelian Pop -Date: Thu May 8 20:52:16 2008 +0200 - - AT91CAP9ADK: Normalize BOOTARGS - - This patch adapts CONFIG_BOOTARGS to the chosen boot method (boot from - DataFlash or from NAND), and gives to Linux a fully specified mtdparts - variable. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 93da48b910511911ce110656e17ed733c8ac4c45 -Author: Stelian Pop -Date: Thu May 8 20:52:15 2008 +0200 - - AT91CAP9ADK: Normalize SPI timings - - This patch changes the SPI timings to closely match the ones - used by the Linux kernel and the Atmel's own bootstrap project. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 1c90df3e148ce0a3e2c86c63b38b19d47772f2a0 -Author: Stelian Pop -Date: Thu May 8 20:52:14 2008 +0200 - - AT91CAP9ADK: Handle 8 or 16 bit NAND - - The Atmel boards can handle 8 or 16 bit NAND memories. This patch - makes the support configurable in the board config header file - (CFG_NAND_DBW_8 or CFG_NAND_DBW_16). - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 11b162bae058e96c7929e358d4adff2bee6c2cc4 -Author: Stelian Pop -Date: Thu May 8 20:52:13 2008 +0200 - - Use a common u-boot.lds file across all AT91CAP9/AT91SAM9 platforms - - All the AT91CAP9/AT91SAM9 boards have the same linker script. The patch - below avoids the duplication of u-boot.lds by putting the file in the - cpu directory instead of the board one. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit d48abea4b89adaf5e45ea75b5e38c0d8de179ece -Author: Stelian Pop -Date: Thu May 8 20:52:12 2008 +0200 - - Add proper copyright notices in Atmel boards Makefiles - - The Makefiles for the AT91CAP9/AT91SAM9 boards have an incomplete - copyright notice. This patch adds the missing pieces. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit e817a042cef6164bf26fee86f90326f2ec9e6745 -Author: Stelian Pop -Date: Thu May 8 20:52:11 2008 +0200 - - Add copyright information in Atmel boards partition.c - - When Ulf did the dataflash.c cleanup, he didn't add his copyright on - the new created files. This patch fixes the problem. - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 4f6c810106f4f76d83cfc57d98f4540cd45f9a19 -Author: Stelian Pop -Date: Thu May 8 20:52:10 2008 +0200 - - Update origin and copyright information in arch-at91sam9 header files - - When doing the AT91CAP9/AT91SAM9 port, a number of header files were - copied from the Linux kernel sources. This patch explicitly specifies - this origin for all the copied headers, and for those missing copyright - information, adds it. - - Additionaly, the header file 'at91sam926x_mc.h' has been superceeded - in the latest kernel sources by 'at91sam9_smc.h'. - - The copyright information has been confirmed by the AT91 Linux kernel - maintainer, Andrew Victor . - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 79dd1712689d6a5031d7cbff54957049680751c7 -Author: Markus Klotzbücher -Date: Thu May 8 16:00:55 2008 +0200 - - ppc4xx: Kilauea: Add CONFIG_BOOTP_SUBNETMASK to Kilauea board config - - When using dhcp/bootp the "netmask" environment variable is not set - because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is - desireable, so the following patch adds this this option to the board - config. - - Signed-off-by: Markus Klotzbuecher - Signed-off-by: Stefan Roese - -commit 869d14b4cc2e47de2ddcb117bad0407a44436684 -Author: Stefan Roese -Date: Sat May 10 10:30:36 2008 +0200 - - ppc4xx: Update Makalu defconfig to use device-tree booting as default - - This patch reworks the default environment on Makalu. Now "net_nfs" for - example uses the device-tree style booting formerly know as "net_nfs_fdt". - Also the addresses in RAM were changed because of the new image booting - support, which check for image overwriting. So the addresses needed to - get adjusted. - - Signed-off-by: Stefan Roese - -commit f3612a7b199cab3942f60d9c1392eb39d58cc699 -Author: Becky Bruce -Date: Wed May 7 13:28:16 2008 -0500 - - PPC: fix map_physmem build warning - - map_physmem currently generates a warning when CONFIG_PHYS_64BIT is - enabled. This quiets the warning. - - Signed-off-by: Becky Bruce - -commit 36f32675f40292002ee1fed252c180a43022d2d4 -Author: Becky Bruce -Date: Wed May 7 13:24:57 2008 -0500 - - Update pci code to use phys_addr_t - - Physical addrs need to be represented by phys_addr_t, not - unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT - are going to fail mightily. - - Signed-off-by: Becky Bruce - -commit 91a616741fc128cdb88f39bddcd4d72fe17466d0 -Author: Nick Spence -Date: Thu May 8 22:32:22 2008 -0700 - - Support legacy multi-type images without FDT section. - - This patch enables legacy multi-type images containing only a Linux kernel - and root file system to be loaded, maintaining compatibility with previous - versions of u-boot. - - This is required when using old image files such as a Linux 2.4 kernel / - filesystem. - - Signed-off-by: Nick Spence - Acked-by: Bartlomiej Sieka - -commit 881031d9732783b7aeae2198fc7eb480ae8974a6 -Author: Wolfgang Denk -Date: Sat May 10 00:38:02 2008 +0200 - - Update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit e5e9d6c9c08160be7e5a36e04d125ccce99b8774 -Author: Wolfgang Denk -Date: Sat May 10 00:36:09 2008 +0200 - - post/cpu/ppc4xx/Makefile: line length cleanup - - Signed-off-by: Wolfgang Denk - -commit cce9cfdabcf416ecd2aacc3681c91e5378c75a3d -Author: Stelian Pop -Date: Thu May 8 22:52:09 2008 +0200 - - Fix @ -> substitution - - When applying the AT91CAP9 patches upstream, something transformed - the '@' character into the ' ' sequence. - - The patch below restores the original form in all the places where - it has been modified (the AT91CAP9 files, the AT91SAM9260 files which - were copied from AT91CAP9, and a couple of other files where the - ' ' sequence was present). - - Signed-off-by: Stelian Pop - -commit 9606b3c81b3c47a1d58514e9a232c6f461a17597 -Author: Stelian Pop -Date: Thu May 8 22:52:10 2008 +0200 - - Update origin and copyright information in arch-at91sam9 header files - - When doing the AT91CAP9/AT91SAM9 port, a number of header files were - copied from the Linux kernel sources. This patch explicitly specifies - this origin for all the copied headers, and for those missing copyright - information, adds it. - - Additionaly, the header file 'at91sam926x_mc.h' has been superceeded - in the latest kernel sources by 'at91sam9_smc.h'. - - The copyright information has been confirmed by the AT91 Linux kernel - maintainer, Andrew Victor . - - Signed-off-by: Stelian Pop - -commit ceb6b4fbe1dcc40bb672ef8133ddf4813e97cbb1 -Author: Stelian Pop -Date: Thu May 8 22:52:11 2008 +0200 - - Add copyright information in Atmel boards partition.c - - When Ulf did the dataflash.c cleanup, he didn't add his copyright on - the new created files. This patch fixes the problem. - - Signed-off-by: Stelian Pop - -commit 2ab02fd456d8ef92ae9f5439618d1fa7ca16e5f3 -Author: Guennadi Liakhovetski -Date: Thu May 8 10:09:27 2008 +0200 - - mx31ads: fix 32kHz clock handling - - According to schematics and to RedBoot sources, the MX31ADS uses a 32768Hz - oscillator as a SKIL source. Fix previously wrongly assumed 32000Hz value. - Also fix a typo when verifying a jumper configuration. While at it, make - two needlessly global functions static. - - Signed-off-by: Guennadi Liakhovetski - -commit 1b5605ca57fbb364f4d78eeee28b974ed875e888 -Author: Marian Balakowicz -Date: Wed May 7 13:10:04 2008 +0200 - - Avoid initrd and logbuffer area overlaps - - Add logbuffer to reserved LMB areas to prevent initrd allocation - from overlaping with it. - - Make sure to use correct logbuffer base address. - - Signed-off-by: Marian Balakowicz - -commit c59518e15949b3403df5c5b0c2c48ea0e5bea24b -Author: Marian Balakowicz -Date: Wed May 7 13:08:54 2008 +0200 - - ppc: Cleanup get_effective_memsize() use - - Removed duplicated effective memory size calculation code. - - Signed-off-by: Marian Balakowicz - -commit 273c37d843d5b581090378016cd12dd9c586907b -Author: Marian Balakowicz -Date: Wed May 7 09:03:53 2008 +0200 - - Fix build errors when CONFIG_LOGBUFFER and CONFIG_FIT are enabled - - Recent modifcations to LOGBUFFER handling code were incorrecly - introduced to fit_check_kernel() routine during - "Merge branch 'new-image' of git://www.denx.de/git/u-boot-testing", - commit 27f33e9f45ef7f9685cbdc65066a1828e85dde4f. - - This patch cleans up this merge issue. - - Signed-off-by: Marian Balakowicz - -commit bc11756daff89a3de09ca80adac962b88cf06e6e -Author: Grant Erickson -Date: Tue May 6 20:16:15 2008 -0700 - - Propagate Error Status to the Shell on fw_printenv Errors - - Changed implementation such that fw_printenv returns failure status - when one or more specified variables do not exist or when incorrect - command syntax is used. - - This aids scripting fw_printenv such that the script can key of the - return status rather than relying on standard error "scraping". - - Signed-off-by: Grant Erickson - Signed-off-by: Wolfgang Denk - -commit f3b6d528e4dd719640a4bfcd954f4e4c7f5db0d6 -Author: Grant Erickson -Date: Tue May 6 16:18:00 2008 -0700 - - Fix Compilation Errors with 'tools/env/fw_printenv' - - In the current top-of-tree, 1.3.3.-rc2, the optional tool - 'tools/env/fw_printenv' fails to compile for two reasons: - - 1) The header watchdog.h cannot be found. - 2) The header zlib.h is picked up from the tool chain rather than the - project causing a prototype conflict for crc32. - - This patch addresses both of these issues. - - Platforms Tested On: - - AMCC "Kilauea" - - Signed-off-by: Grant Erickson - -commit 597f6c26a18b389903a64692bacbf9a1ca69355b -Author: James Yang -Date: Mon May 5 10:22:53 2008 -0500 - - Fix readline_into_buffer() with CONFIG_CMDLINE_EDITING before relocating - - When CONFIG_CMDLINE_EDITING is enabled, readline_into_buffer() doesn't - work before relocating to RAM because command history is written into - a global array that is not writable before relocation. This patch - defers to the no-editing and no-history code in readline_into_buffer() - if it is called before relocation. - - Signed-off-by: James Yang - Signed-off-by: Kumar Gala - -commit 726c0f1e5f108dccea052965123b95837d2bd402 -Author: Detlev Zundel -Date: Mon May 5 16:11:22 2008 +0200 - - cosmetic: Adjust coding style for switch statements to be consistent - - Signed-off-by: Detlev Zundel - -commit 574b319512b13e10800f0045e39b993f4ca25e42 -Author: Detlev Zundel -Date: Mon May 5 16:11:21 2008 +0200 - - Fix disk type output in disk/part.c - - Signed-off-by: Detlev Zundel - -commit 045b4d2d7168ef09c7349dcf6ecebe7432b74171 -Author: Vlad Lungu -Date: Mon May 5 14:20:03 2008 +0300 - - Mail address change, documentation modified - - Signed-off-by: Vlad Lungu - -commit 4d49b28038e2819088e8356a77212fc95a89ce5a -Author: Michal Simek -Date: Sun May 4 15:42:41 2008 +0200 - - microblaze: Repare intc handling - - Signed-off-by: Michal Simek - -commit 878b3b1e193e570caf3e96ad8e31e561f68d0287 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun May 4 15:17:52 2008 +0200 - - include/gitignore: update to all architectures - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 1df368aed3b8bc240fe1595d290b0e91b22961da -Author: Marcel Ziswiler -Date: Mon May 5 02:12:06 2008 +0200 - - ide: Remove spurious second include of io.h - - Removed the second include, with all the #ifdef around as suggested by Wolfgang. - - Signed-off-by: Marcel Ziswiler - -commit 8fbc985bdad09b23b7eb4df1d2ea589619d8db4c -Author: Adrian Filipi -Date: Tue May 6 16:46:37 2008 -0400 - - Fix some typos - - This patch fixes three typos. - The first is a repetition of CONFIG_CMD_BSP. - The second makes the #endif comment match its #if. - The third is a spelling error. - - Signed-off-by: Adrian Filipi - -commit e419e12d04ae3b280c99a87a2ea4ad7a40628bcb -Author: Grant Erickson -Date: Sun May 4 16:45:01 2008 -0700 - - Recognize 'powerpc' As an Alias for IH_ARCH_PPC - - Add support for the recognition of 'powerpc' as an alias for the PowerPC - architecture type since Linux is already trending in that direction, - preferring 'powerpc' to 'ppc'. - - Signed-off-by: Grant Erickson - -commit f5a24259190c388c2527bdc49fee34577d862cc7 -Author: Wheatley Travis -Date: Fri May 2 13:35:15 2008 -0700 - - 7450 and 86xx L2 cache invalidate bug corrections - - The 7610 and related parts have an L2IP bit in the L2CR that is - monitored to signal when the L2 cache invalidate is complete whereas the - 7450 and related parts utilize L2I for this purpose. However, the - current code does not account for this difference. Additionally the 86xx - L2 cache invalidate code used an "andi" instruction where an "andis" - instruction should have been used. - - This patch addresses both of these bugs. - - Signed-off-by: Travis Wheatley - Acked-By: Jon Loeliger - -commit 4d31cdc45d3592a5545a649fb5a24b458a4e4b72 -Author: Wolfgang Denk -Date: Fri May 9 10:16:13 2008 +0200 - - Avoid infinite loop "Generating include/autoconf.mk" - - Fix a bogus circular dependency that caused an infinite loop of - "Generating include/autoconf.mk" again and again. - - Signed-off-by: Wolfgang Denk - -commit 567fb852178dbf59529d7301620a3f3732a4b02d -Author: Stelian Pop -Date: Thu May 8 22:52:09 2008 +0200 - - Fix @ -> substitution - - When applying the AT91CAP9 patches upstream, something transformed - the '@' character into the ' ' sequence. - - The patch below restores the original form in all the places where - it has been modified (the AT91CAP9 files, the AT91SAM9260 files which - were copied from AT91CAP9, and a couple of other files where the - ' ' sequence was present). - - Signed-off-by: Stelian Pop - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 73ccb3410a0785593cda7aee455dfc51f790e281 -Author: Gary Jennejohn -Date: Mon Apr 28 14:04:32 2008 +0200 - - ppc4xx: Add the Harris QUAD100HD AMCC 405EP-based board - - Signed-off-by: Gary Jennejohn - Signed-off-by: Stefan Roese - -commit ef2642625cbfb1c3695e3478d08ae515052a4950 -Author: Stefan Roese -Date: Thu May 8 11:10:46 2008 +0200 - - ppc4xx: Kilauea: Fix incorrect FPGA FIFO address - - Signed-off-by: Stefan Roese - -commit a00eccfebc954ad9485161efeca7d9aaf626d530 -Author: Stefan Roese -Date: Thu May 8 11:05:15 2008 +0200 - - ppc4xx: Add fdt support to all remaining AMCC PPC4xx eval boards - - This patch adds fdt (flattened device tree) support to all remaining AMCC - eval boards. Most newer boards already support device tree. With this patch, - all AMCC boards now enable device tree passing from U-Boot to Linux - arch/powerpc kernels. - - Signed-off-by: Stefan Roese - -commit cb5d88b9611e0c35c53543ad3b4ab99fa82203e3 -Author: Stefan Roese -Date: Thu May 8 11:01:09 2008 +0200 - - ppc4xx: Add weak default ft_board_setup() routine - - This patch adds a default ft_board_setup() routine to the 4xx fdt code. - This routine is defined as weak and can be overwritten by a board specific - one if needed. - - Signed-off-by: Stefan Roese - -commit d1c1ba85c7915053adf6a8d14a08ac6fcb750d01 -Author: Stefan Roese -Date: Thu May 8 10:48:58 2008 +0200 - - ppc4xx: acadia: Add fdt support and fix section overlap problem - - This patch adds fdt (flattened device tree) support to the AMCC - Acadia eval board. This increases the image size and it doesn't - fit anymore into 256kByte. Since we didn't want to remove features - from the configuration, we decided to increase the U-Boot image size - (add one flash sector). - - Also changed the default environment definition to make it - independent of such changes. - - Signed-off-by: Stefan Roese - -commit 4adb3023de75bc150f088c8935db340930ad38c8 -Author: Ira Snyder -Date: Tue Apr 29 11:18:54 2008 -0700 - - ppc4xx: Add device tree support to AMCC Yosemite - - Add support for booting with a device tree blob. This is needed to boot - ARCH=powerpc kernels. Also add support for setting the eth0 mac address - via the ethaddr variable. - - Signed-off-by: Ira W. Snyder - Signed-off-by: Stefan Roese - -commit b9bbefce1a653ea35f74a66ec117cdda2e043a4b -Author: Dave Mitchell -Date: Wed May 7 09:00:23 2008 -0700 - - ppc4xx: Fix typos in 460GT/EX FBDV array - - Corrected two typos in the 460GT/EX FBDV array. - - Signed-off-by: Dave Mitchell - Signed-off-by: Stefan Roese - -commit 66f5fa9263629271edc86178b1f224e3c9aab2b3 -Author: Andy Fleming -Date: Wed May 7 16:54:31 2008 -0500 - - 85xx: Limit CPU2 workaround to parts that have the errata - - Signed-off-by: Ebony Zhu - Signed-off-by: Andy Fleming - -commit a5fe514e8ace564300d2c1d73846ddff49654243 -Author: Lee Nipper -Date: Fri Apr 25 15:44:45 2008 -0500 - - mpc83xx: system performance settings for MPC8349EMDS. - - These same settings are used on MPC8349ITX, and - improve performance on MPC8349EMDS. - - Signed-off-by: Lee Nipper - Signed-off-by: Kim Phillips - -commit 49387dba910e485640b575e920ee463b7e611dc3 -Author: Shinya Kuribayashi -Date: Tue May 6 13:22:52 2008 +0900 - - [MIPS] cpu/mips/cache.S: Fix build warning - - Some old GNU assemblers, such as v2.14 (ELDK 3.1.1), v2.16 (ELDK 4.1.0), - warns illegal global symbol references by bal (and jal also) instruction. - This does not happen with the latest binutils v2.18. - - Here's an example on gth2_config: - - mips_4KC-gcc -D__ASSEMBLY__ -g -Os -D__KERNEL__ -DTEXT_BASE=0x90000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isy - stem /opt/eldk311/usr/bin/../lib/gcc-lib/mips-linux/3.3.3/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4k - c -EB -c -o cache.o cache.S - cache.S: Assembler messages: - cache.S:243: Warning: Pretending global symbol used as branch target is local. - cache.S:250: Warning: Pretending global symbol used as branch target is local. - - In principle, gas might be sensitive to global symbol references in PIC - code because they should be processed through GOT (global offset table). - But if `bal' instruction is used, it results in PC-based offset jump. - This is the cause of this warning. - - In practice, we know it doesn't matter whether PC-based reference or GOT- - based. As for this case, both will work before/after relocation. But let's - fix the code. - - This patch explicitly sets up a target address, then jump there. - Here's an example of disassembled code with/without this patch. - - 90000668: 1485ffef bne a0,a1,90000628 - 9000066c: ac80fffc sw zero,-4(a0) - 90000670: 01402821 move a1,t2 - -90000674: 0411ffba bal 90000560 - -90000678: 01803021 move a2,t4 - -9000067c: 01602821 move a1,t3 - -90000680: 0411ffcc bal 900005b4 - -90000684: 01a03021 move a2,t5 - -90000688: 03000008 jr t8 - -9000068c: 00000000 nop - +90000674: 01803021 move a2,t4 - +90000678: 8f8f83ec lw t7,-31764(gp) - +9000067c: 01e0f809 jalr t7 - +90000680: 00000000 nop - +90000684: 01602821 move a1,t3 - +90000688: 01a03021 move a2,t5 - +9000068c: 8f8f81e0 lw t7,-32288(gp) - +90000690: 01e0f809 jalr t7 - +90000694: 00000000 nop - +90000698: 03000008 jr t8 - +9000069c: 00000000 nop - - Signed-off-by: Shinya Kuribayashi - -commit 0f8c62a14b523c56874ebcb67c1a16c99aad48b3 -Author: Vlad Lungu -Date: Mon May 5 14:04:00 2008 +0300 - - Allow building mips versions with ELDK 3.1.1 - - .gpword works only with local symbols on certain binutils versions - - Signed-off-by: Vlad Lungu - -commit 12a67a9e51f6b3ec26cb0f077fb5685a447c359d -Author: Wolfgang Denk -Date: Mon May 5 12:52:36 2008 +0200 - - MAKEALL: add inka4x0 board - - Signed-off-by: Wolfgang Denk - -commit b83dcc13ae7b2dab394bfef6f699750d11490ee2 -Author: Wolfgang Denk -Date: Sun May 4 21:34:23 2008 +0200 - - kb9202 board: fix build problem. - - Signed-off-by: Wolfgang Denk - -commit 6adf61dc4cb5c53a2df990cbc8df2bceacbfd869 -Author: Wolfgang Denk -Date: Sun May 4 12:10:33 2008 +0200 - - Prepare for v1.3.3-rc3 - - Update ChNAGELOG, minor white space cleanup. - - Signed-off-by: Wolfgang Denk - -commit 7c0773fde6100b61be2558cb5d8c442a3194aecb -Author: Wolfgang Denk -Date: Sun May 4 00:35:15 2008 +0200 - - drivers/net/tsec.c: Fix typo. - - Signed-off-by: Wolfgang Denk - -commit aa737945e6f37a5de5dbad550a7694e0cb2a8120 -Author: Mike Frysinger -Date: Fri May 2 21:45:12 2008 -0400 - - version_autogenerated.h: use printf rather than echo -n - - Some systems are dumb and do not implement the -n flag to echo (like OS X). - Convert the Makefile to use printf as this should work everywhere. - - Signed-off-by: Mike Frysinger - Signed-off-by: Wolfgang Denk - -commit 4acc2a108ad0a669165924704a6cb083f9138242 -Author: Mike Frysinger -Date: Fri May 2 18:17:50 2008 -0400 - - fix building when saveenv is disabled in some setups - - If you enable environment in the flash, but disable the embedded - option, and you disable the saveenv command, then the #if nested - logic will trigger a compile failure: - env_flash.c: In function 'env_relocate_spec': - env_flash.c:399: error: 'flash_addr' undeclared (first use in this function) - The fix is to add CMD_SAVEENV ifdef protection like everywhere else. - - Signed-off-by: Mike Frysinger - -commit ccf1ad535ae1c0dc2d466235c668adbdfe3a55b7 -Author: Jeremy McNicoll -Date: Fri May 2 16:10:04 2008 -0400 - - SBC8548: fix address mask to allow 64M flash - - Fix incorrect mask to enable all 64MB of onboard flash. - Previously U-Boot incorrectly mapped only 8MB of flash, this - patch correctly maps all the available flash. - - Signed-off-by: Jeremy McNicoll - -commit 3648085c464c8c22ef76fab006ca4344d3796124 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri May 2 19:48:56 2008 +0200 - - qemu_mips: add README - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 6fdd002689190a0022c7b3dbab37fcba724580ce -Author: Marcel Ziswiler -Date: Fri May 2 02:35:59 2008 +0200 - - Fix misspelled comment - - Signed-off-by: Marcel Ziswiler - -commit fa956fde60b7ec4dd66bd62f9910fd341b5049a1 -Author: Mike Frysinger -Date: Thu May 1 04:13:05 2008 -0400 - - mkimage: make mmap() checks consistent - - The mmap() related code is full of inconsistent casts/constants when - it comes to error checking, and may break when building on some - systems (like ones that do not implicitly define the caddr_t type). - Let's just avoid the whole mess by writing the code nice and clean in - the first place. - - Signed-off-by: Mike Frysinger - -commit 8e90cd0447a0f0ccf529ef86f0e6b56187d3b82a -Author: Marcel Ziswiler -Date: Thu May 1 09:05:34 2008 +0200 - - Fix defined but not used build warning - - - warning: 'srom' defined but not used - - Signed-off-by: Marcel Ziswiler - -commit b71190f3250aaffcc81c35f6cfd3498cb7c48013 -Author: Marcel Ziswiler -Date: Thu May 1 09:05:26 2008 +0200 - - Fix implicit declaration build warnings - - - warning: implicit declaration of function ‘serial_initialize’ - - Signed-off-by: Marcel Ziswiler - -commit 9acde129cc3f9c1b3bc11a821480dd446774d618 -Author: Andre Schwarz -Date: Tue Apr 29 19:18:32 2008 +0200 - - TSEC: add config options for VSC8601 RGMII PHY - - The Vitesse VSC8601 RGMII PHY has internal delay for both Rx - and Tx clock lines. They are configured using 2 bits in extended - register 0x17. - Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have - been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay. - - Signed-off-by: Andre Schwarz - Acked-by: Andy Fleming - Acked-by: Ben Warren - -- - - drivers/net/tsec.c | 6 ++++++ - drivers/net/tsec.h | 3 +++ - 2 files changed, 9 insertions(+), 0 deletions(-) - -commit bd98ee60df43ee6dd6f5ebe32c67d03e90513ff8 -Author: Wolfgang Denk -Date: Sat May 3 23:07:15 2008 +0200 - - Revert "ColdFire: Get information from the correct GCC" - - This reverts commit b7166e05a513c0806b63b9dfb6f1d77645cede2a - (replaced by commit c4e5f52a58d278eebb87f476e353972c5dacea40). - -commit c4e5f52a58d278eebb87f476e353972c5dacea40 -Author: Wolfgang Denk -Date: Sat May 3 22:25:00 2008 +0200 - - config.mk: use correct (cross) compiler - - Some config.mk files reference $(CC) to test for specific tool chain - features, so make sure $(CC) gets set before including any such - config files. - - This patch replaces commit b7166e05a5 ("ColdFire: Get information from - the correct GCC"). - - Signed-off-by: Wolfgang Denk - -commit 27c38689d0cfde0e444239345f97b5eecc9f4067 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Thu May 1 02:13:44 2008 +0200 - - pxa: fix previous definition on cpu init - - start.S:183:1: warning: "ICMR" redefined - In file included from start.S:33: - include/asm/arch/pxa-regs.h:935:1: warning: this is the location of the previous definition - start.S:187:1: warning: "RCSR" redefined - ... - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 6d12e697de794d700767f22f950e3026ccf4daf6 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Thu May 1 02:13:43 2008 +0200 - - pxa: fix pcmcia operation on 'i' may be undefined - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Wolfgang Denk - -commit 4d77f5102dfeaa36cd58d9a9f083bd2cc491526f -Author: Kumar Gala -Date: Wed Apr 30 16:24:35 2008 -0500 - - MPC8610HPCD: Drop -O2 from the build flags - - Make the flags use -Os like all other boards - - Signed-off-by: Kumar Gala - -commit 0072b78be2b41e5a0ca3ddc39335574dc2e855bd -Author: Stefan Roese -Date: Wed Apr 30 15:50:39 2008 +0200 - - RTC: Fix month offset by one problem in M41T62 RTC driver - - This patch fixes a problem with the month being read and written - incorrectly (offset by one). This only gets visible by also using - the Linux driver (rtc-m41t80). - - Tested on AMCC Canyonlands. - - Signed-off-by: Stefan Roese - -commit 141ba1cad8e6598a2466e7e2976c6a12285df619 -Author: Shinya Kuribayashi -Date: Sat May 3 13:51:44 2008 +0900 - - [MIPS] cpu/mips/config.mk: Fix GNU assembler minor version picker - - Current trick to pick up GNU assembler minor version uses a dot(.) as a - delimiter, and take the second field to obtain minor version number. But - as can be expected, this doesn't work with a version string which has - dots more than needs. - - Here's an example: - - $ mips-linux-gnu-as --version | grep 'GNU assembler' - GNU assembler (Sourcery G++ Lite 4.2-129) 2.18.50.20080215 - $ mips-linux-gnu-as --version | grep 'GNU assembler' | cut -d. -f2 - 2-129) 2 - $ - - This patch restricts the version format to 2.XX.XX... This will work - in most cases. - - $ mips-linux-gnu-as --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' - 2.18.50.20080215 - $ mips-linux-gnu-as --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2 - 18 - $ - - Signed-off-by: Shinya Kuribayashi - -commit ea638951acead7f1086c908c0b9f086beab82a22 -Author: Shinya Kuribayashi -Date: Sat May 3 13:51:28 2008 +0900 - - [MIPS] cpu/mips/cache.S: Add dcache_enable - - Recent bootelf command fixes (017e9b7925f74878d0e9475388cca9bda5ef9482, - "allow ports to override bootelf behavior") requires ports to have this - function. - - Signed-off-by: Shinya Kuribayashi - Acked-by: Jean-Christophe PLAGNIOL-VILLARD - -commit d2c6fbec4397c936b18cd42482b6973cd6781bdf -Author: Wolfgang Denk -Date: Thu May 1 21:30:16 2008 +0200 - - onenand: rename 16 bit memory copy into memcpy_16() to avoid conflicts - - Onenand needs a version of memcpy() which performs 16 bit accesses - only; make sure the name does not conflict with the standard - function. - - Signed-off-by: Wolfgang Denk - -commit 12bc4e94251c369c529ffa505cf58b148c372f7f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Wed Apr 30 22:38:17 2008 +0200 - - cmd_nand: fix warning: str2long ncompatible pointer type - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 1b9ed2574a38c93cb03dad41885fc06be4bfc9dd -Author: Timur Tabi -Date: Fri Apr 4 11:16:11 2008 -0500 - - Fix calculation of I2C clock for some 86xx chips - - Some 86xx chips use CCB as the base clock for the I2C, and others used CCB/2. - There is no pattern that can be used to determine which chips use which - frequency, so the only way to determine is to look up the actual SOC - designation and use the right value for that SOC. - - Signed-off-by: Timur Tabi - -commit f32f7fe7bd3a5bda3a476520f00e1aca7c2103a9 -Author: TsiChung Liew -Date: Wed Apr 30 12:11:19 2008 -0500 - - ColdFire: Fix ethernet hang issue for mcf547x_8x - - The ethernet hang is caused by receiving buffer in DRAM is not - yet ready due to access cycles require longer time in DRAM. - Relocate DMA buffer descriptors from DRAM to internal SRAM. - - Signed-off-by: TsiChung Liew - -commit 886d90176fc257e0ab4d0db05d11d0749bbed3ca -Author: TsiChung Liew -Date: Wed Apr 30 12:10:47 2008 -0500 - - ColdFire: Fix compilation issue caused by new changes in fsl_i2c.c - - Signed-off-by: Luigi Comio Mantellini - Signed-off-by: TsiChung Liew - -commit b7166e05a513c0806b63b9dfb6f1d77645cede2a -Author: TsiChung Liew -Date: Wed Apr 30 12:10:23 2008 -0500 - - ColdFire: Get information from the correct GCC - - Signed-off-by: Kurt Mahan - Signed-off-by: TsiChung Liew - -commit 378e7ec95da4751ec8fe461baacab2bf7d2512a9 -Author: dirk.behme@googlemail.com -Date: Wed Apr 30 18:02:59 2008 +0200 - - Fix warning in env_nand.c if compiled for DaVinci Schmoogie - - Fix warnings - - nv_nand.c: In function 'saveenv': - env_nand.c:200: warning: passing argument 3 of 'nand_write' from incompatible pointer type - env_nand.c: In function 'env_relocate_spec': - env_nand.c:275: warning: passing argument 3 of 'nand_read' from incompatible pointer type - - if compiled for davinci_schmoogie_config. - - Signed-off-by: Dirk Behme - Ack by: Sergey Kubushyn - -commit 33a4a70d48d622cc4950c60a84fec23b9421f23e -Author: Anatolij Gustschin -Date: Wed Apr 30 13:34:40 2008 +0200 - - Fix warnings while compiling net/net.c for MPC8610HPCD board - - MPC8610HPCD board adds -O2 gcc option to PLATFORM_CPPFLAGS - causing overriding default -Os option. New gcc (ver. 4.2.2) - produces warnings while compiling net/net.c file with -O2 - option. The patch is an attempt to fix this. - - Signed-off-by: Anatolij Gustschin - -commit 58b575e575c25fdf8c88141e145db201f3092149 -Author: Sascha Laue -Date: Wed Apr 30 15:23:38 2008 +0200 - - lwmon5: fix offset error in sysmon0 POST - - Signed-off-by: Sascha Laue - Signed-off-by: Wolfgang Denk - -commit e7419b243a373de4ee042f7d4f45f66de787240d -Author: Sascha Laue -Date: Wed Apr 30 15:16:35 2008 +0200 - - lwmon5: fix manual merge error in POST - - Signed-off-by: Sascha Laue - -commit 42ffcec3f9eba010a662d5b42981812b6bebfb9a -Author: Wolfgang Denk -Date: Wed Apr 30 17:46:26 2008 +0200 - - cmd_nand.c: fix another 'incompatible pointer type' warning. - - Signed-off-by: Wolfgang Denk - -commit de109d909707e2dfe806be5efc3cdb103b47c8ad -Author: Wolfgang Denk -Date: Wed Apr 30 17:25:07 2008 +0200 - - Makefile: fix parallel builds - - This problem shows up with parallel builds only; it results in - somewhat cryptic error messages like - - $ JOBS=-j6 MAKEALL netstar - Configuring for netstar board... - arm-linux-ld: cannot find -lgeneric - make[1]: *** [eeprom.srec] Error 1 - - A few boards (like netstar and voiceblue) need some libraries for - building; however, the board Makefile does not contain any such - dependencies which may cause problems with parallel builds. Adding - such dependencies is difficult as we would also have to provide build - rules, which already exist in the respective library Makefiles. - - To solve this, we make sure that all libraries get built before the - board code. - - Signed-off-by: Wolfgang Denk - -commit 4f27098e5b0736989b13cd61d7bca94b3574cf5f -Author: Stefan Roese -Date: Wed Apr 30 14:51:36 2008 +0200 - - ppc4xx: Adapt Canyonlands fixed DDR2 setup to new DIMM module - - This patch changes the Canyonlands/Glacier fixed DDR2 controller setup - used for NAND booting to match the values needed for the new 512MB - DIMM modules shipped with the productions boards: - - Crucial: CT6464AC667.8FB - - Signed-off-by: Stefan Roese - -commit ea9202a659dc75996facf1475f1866a19a9d3129 -Author: Stefan Roese -Date: Wed Apr 30 10:49:43 2008 +0200 - - ppc4xx: Fix problem with DIMMs with 8 banks in 44x_spd_ddr2.c - - This patch fixes a problem with DIMMs that have 8 banks. Now the - MCIF0_MBxCF register will be setup correctly for this setup too. - - This was noticed with the 512MB DIMM on Canyonlands/Glacier. - - Signed-off-by: Stefan Roese - -commit 76617299358ebba260ecc02d33e8e75d8d13dd3b -Author: Wolfgang Denk -Date: Tue Apr 29 23:41:06 2008 +0200 - - Prepare v1.3.3-rc2, again. - - Signed-off-by: Wolfgang Denk - -commit b7fcc4c13993782342cf5cd20d237a6281648a0b -Author: Wolfgang Denk -Date: Tue Apr 29 23:35:24 2008 +0200 - - Prepare v1.3.3-rc2 - - Signed-off-by: Wolfgang Denk - -commit f7b16a0a4d571dd33b2b5185a54f7ddc311f89d4 -Author: Wolfgang Denk -Date: Tue Apr 29 23:32:20 2008 +0200 - - common/env_nand.c: fix one more incompatible pointer type issue - - Signed-off-by: Wolfgang Denk - -commit ea6f66894f952229eebfc4ad03cd21fe5c8b3f0f -Author: Wolfgang Denk -Date: Tue Apr 29 21:33:08 2008 +0200 - - post/board/lwmon5/sysmon.c: fix manual merge error. - - Signed-off-by: Wolfgang Denk - -commit 70a0f81412b0b18a6fd0bea960451bc6c2cca49a -Author: Kumar Gala -Date: Tue Apr 29 12:54:59 2008 -0500 - - 85xx: Add -mno-spe to e500/85xx builds - - Newer gcc's might be configured to enable autovectorization by default. - If we happen to build with one of those compilers we will get SPE - instructions in random code. - - -mno-spe disables the compiler for automatically generating SPE - instructions without our knowledge. - - Signed-off-by: Kumar Gala - -commit 8ea08e5be69436abcc95d3da114de4a2ff8a6ab5 -Author: Kumar Gala -Date: Tue Apr 29 10:18:34 2008 -0500 - - Update .gitignore for zlib.h - - Signed-off-by: Kumar Gala - -commit 45239cf4152109caa925145ccd433529902df887 -Author: Kumar Gala -Date: Tue Apr 29 10:27:08 2008 -0500 - - 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs - - All the 85xx and 86xx UM describe the register as timing_cfg_3 - not as ext_refrec. - - Signed-off-by: Kumar Gala - -commit ef7d30b14394e4c4a153118f5845760cadada02a -Author: Kumar Gala -Date: Tue Apr 29 10:28:34 2008 -0500 - - 85xx/86xx: Rename DDR init address and init extended address register - - Rename init_addr and init_ext_addr to match the docs between - 85xx and 86xx. Both now use 'init_addr' and 'init_ext_addr'. - - Signed-off-by: Kumar Gala - -commit cf6cc014270549684873a5972d2595052c468cb6 -Author: Kumar Gala -Date: Mon Apr 28 02:24:04 2008 -0500 - - 85xx: Additional fixes and cleanup of MP code - - * adjust __spin_table alignment to match ePAPR v0.94 spec - * loop over all cpus when determing who is up. This fixes an issue if - the "boot cpu" isn't core0. The "boot cpu" will already be in the - cpu_up_mask so there is no harm - * Added some protection in the code to ensure proper behavior. These - changes are explicitly needed but don't hurt: - - Added eieio to ensure the "hot word" of the table is written after - all other table updates have occurred. - - Added isync to ensure we don't prefetch loading of table entries - until we a released - - These issues we raised by Dave Liu. - - Signed-off-by: Kumar Gala - -commit b2d527a8b9fb50afccbaf79b5540952585cdc760 -Author: Yuri Tikhonov -Date: Tue Apr 29 15:06:41 2008 +0200 - - lwmon5: minor clean-up to include/configs/lwmon5.h - - LWMON5 DSPIC POST uses the watch-dog scratch register. So, make - the CFG_DSPIC_TEST_ADDR definition more readable. - - Signed-off-by: Yuri Tikhonov - -commit f4c4d21a885ccc222fd0acdf653b683249e85117 -Author: Stefan Roese -Date: Tue Apr 29 16:08:05 2008 +0200 - - ppc4xx: Fix CFG_MONITOR_LEN on Katmai failsave this time - - Signed-off-by: Stefan Roese - -commit 138105efe1d2b1a40a3a97b4c1f85c2111bea2d8 -Author: Yuri Tikhonov -Date: Tue Apr 29 13:32:45 2008 +0200 - - ppc flush_cache: add watch-dog triggering into the loops. - - Some boards (e.g. lwmon5) need rather a frequent watch-dog - kicking. Since the time it takes for the flush_cache() function - to complete its job depends on the size of data being flushed, one - may encounter watch-dog resets on such boards when, for example, - download big files over ethernet. - - Signed-off-by: Yuri Tikhonov - -commit cab99d6f3281ab6784feccf98b9b425daa58418a -Author: Stefan Roese -Date: Tue Apr 29 14:44:54 2008 +0200 - - ppc4xx: Fix compilation warning in denali_spd_ddr2.c - - Signed-off-by: Stefan Roese - -commit 4ec9d78fe5cd585d2868731fa108ca1e62730e70 -Author: Stefan Roese -Date: Tue Apr 29 14:12:07 2008 +0200 - - ppc4xx: Fix Katmai CFG_MONITOR_LEN - - Signed-off-by: Stefan Roese - -commit 85ad184b3b2b0f8af9228477303c55dca1b52ed7 -Author: Stefan Roese -Date: Tue Apr 29 13:57:07 2008 +0200 - - ppc4xx: Complete remove bogus dflush() - - Since the current dflush() implementation is know to have some problems - (as seem on lwmon5 ECC init) this patch removes it completely and replaces - it by using clean_dcache_range(). - - Tested on Katmai with ECC DIMM. - - Signed-off-by: Stefan Roese - -commit 135846d6ecaad255ad28d93ebbb78b3d5da68cdc -Author: Stefan Roese -Date: Tue Apr 29 13:36:51 2008 +0200 - - ppc4xx: Change ECC initialization on lwmon5 to use clean_dcache_range() - - As it seems the "old" ECC initialization routine by using dflush() didn't - write all lines in the dcache back to memory on lwmon5. This could lead - to ECC error upon Linux booting. This patch changes the program_ecc() - routine to now use clean_dcache_range() instead of dflush(). - clean_dcache_range() uses dcbst which is exactly what we want in this - case. - - Since dflush() is known is cause problems, this routine will be - removed completely and replaced by clean_dcache_range() with an - additional patch. - - Signed-off-by: Stefan Roese - -commit 18ec19e4aa1a045dfbf2c7c2e33963488e92d757 -Author: Yuri Tikhonov -Date: Mon Apr 28 18:19:34 2008 +0200 - - POST: fix Makefiles for mpc8xx, lwmon, and netta POSTs. - - Signed-off-by: Yuri Tikhonov - -commit eea5a743a2193ef2a05b9bc6dc447ba241416f35 -Author: Markus Brunner -Date: Mon Apr 28 08:47:47 2008 +0200 - - ppc4xx: Fixup ebc clock in FDT for 405GP/EP - - On ppc405EP and ppc405GP (at least) the ebc is directly attached to the plb - and not to the opb. This patch will try to fixup /plb/ebc if /plb/opb/ebc - doesn't exist. - - Signed-off-by: Markus Brunner - -commit 2ef7503a593c77a80c2a054011970227c4b62774 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Thu Apr 24 07:57:17 2008 +0200 - - NE2000: Fix regresssion introduced by e710185aae90 on non AX88796 - - Move non-inlied functions into specific drivers file - Set get_prom as weak - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Vlad Lungu - Signed-off-by: Ben Warren - -commit 40cb90ee2b97db1f697e1b54f19a548ffc96d71b -Author: Guennadi Liakhovetski -Date: Thu Apr 3 17:04:19 2008 +0200 - - net: make ARP timeout configurable - - Currently the timeout waiting for an ARP reply is hard set to 5 seconds. - On i.MX31ADS due to a hardware "strangeness" up to four first IP packets - to the boards get lost, which typically are ARP replies. By configuring - the timeout to a lower value we significantly improve the first network - transfer time on this board. The timeout is specified in milliseconds, - later internally it is converted to deciseconds, because it has to be - converted to hardware ticks, and CFG_HZ ranges from 900 to 27000000 on - different boards. - - Signed-off-by: Guennadi Liakhovetski - Signed-off-by: Ben Warren - -commit 13e0b8f7ca9d29267bf01d7a01e521a0517adce1 -Author: Guennadi Liakhovetski -Date: Thu Apr 3 13:36:18 2008 +0200 - - minor cs8900 driver clean up - - Remove a redundant register definition, clean up some coding style - violations. - - Signed-off-by: Guennadi Liakhovetski - Signed-off-by: Ben Warren - -commit 707fa917cca24c0f22776f48ac4a6fa5e5189b10 -Author: Wolfgang Denk -Date: Mon Apr 28 22:01:04 2008 +0200 - - jffs2_1pass.c: fix incompatible pointer type warning - - Signed-off-by: Wolfgang Denk - -commit 6aee00f5e6a1cf29d8fe8fdc9b7252fbd31115d9 -Author: Sascha Laue -Date: Tue Apr 1 10:10:18 2008 +0200 - - lwmon5: update dsPIC POST spezification - - The specification for the lwmon5 board dsPIC POST got changed. - Also add defines for the temperatures and voltages. - - Signed-off-by: Sascha Laue - -commit 3e4615ab7ff38781a5dd80d0f49b9af55b4fe0b7 -Author: Sascha Laue -Date: Tue Apr 1 15:13:03 2008 +0200 - - Fix watchdog POST for lwmon5 - - If the hardware watchdog detects a voltage error, the watchdog sets - GPIO62 to low. The watchdog POST has to detect this low level. - - Signed-off-by: Sascha Laue - Signed-off-by: Wolfgang Denk - -commit dd5748bcd669f46aeb6686c1b341323843738ccc -Author: Guennadi Liakhovetski -Date: Mon Apr 28 14:37:14 2008 +0200 - - rtl8169: fix compiler warnings - - Fix multiple compiler warnings related to argument type mismatch. - - Signed-off-by: Guennadi Liakhovetski - -commit 413bf586266f86c6bdbc6c6d140f67a15af4c4f1 -Author: Guennadi Liakhovetski -Date: Mon Apr 28 14:36:06 2008 +0200 - - IDE: fix compiler warnings - - The IDE driver can use 32-bit addresses in LBA mode, in which case it - spits multiple warnings during compilation. Fix them. - - Signed-off-by: Guennadi Liakhovetski - -commit db9084de28c46ac81c8f681722cb0d7411be4d7f -Author: Guennadi Liakhovetski -Date: Mon Apr 28 14:35:57 2008 +0200 - - LinkStation: fix compiler warning, add a maintainer - - out_8 wants a pointer to an unsigned as the first argument. Add a - maintainer for Linkstation boards. - - Signed-off-by: Guennadi Liakhovetski - -commit c71abba3cb67b063f789f17abf6c7447727c0cd5 -Author: Wolfgang Denk -Date: Mon Apr 28 14:55:12 2008 +0200 - - cmd_nand.c: fix "differ in signedness" problem - - Signed-off-by: Wolfgang Denk - -commit f2c288a35341ad02ac03b1563d786763c9c8f159 -Author: Wolfgang Denk -Date: Mon Apr 28 12:48:47 2008 +0200 - - pcnet.c: fix a merge issue - - Signed-off-by: Wolfgang Denk - -commit 4ca79f477ebd25a6872e6196d80e2f5eff441376 -Author: Wolfgang Denk -Date: Mon Apr 28 12:08:18 2008 +0200 - - NAND: fix some strict-aliasing compiler warnings - - Signed-off-by: Wolfgang Denk - -commit 5cd0130ecc79d6dcde1b1ac253abc457ca8c3115 -Author: Stefan Roese -Date: Mon Apr 28 11:37:14 2008 +0200 - - ppc4xx: Fix compile warning of hcu4 board - - Signed-off-by: Stefan Roese - -commit 5379cd15dd6c74ac51499bce3455bf6e0cdbe9f1 -Author: Wolfgang Denk -Date: Mon Apr 28 11:31:23 2008 +0200 - - MPC8323ERDB: fix implicit declaration of function 'mac_read_from_eeprom' - - Signed-off-by: Wolfgang Denk - -commit 7602ed50a2f0ef3dc8d7da93f116de50288f5b59 -Author: Guennadi Liakhovetski -Date: Mon Apr 28 00:25:32 2008 +0200 - - mx31ads: fix loadaddr environment variable define - - Arithmetic expressions do not get evaluated under stringification. Remove - default network configuration, add DHCP command support. Thanks to Felix - Radensky for reporting. - - Signed-off-by: Guennadi Liakhovetski - -commit 144eec777ac07bcb12bd38245a5a289f694a7f98 -Author: Wolfgang Denk -Date: Mon Apr 28 10:55:24 2008 +0200 - - katmai: fix section overlap problem - - Since we didn't want to remove features from the configuration, we - decided to increase the U-Boot image size (add one flash sector). - - Also changed the default environment definition to make it - independent of such changes. - - Signed-off-by: Wolfgang Denk - Acked-by: Stefan Roese - -commit 941d696d25624e3cc65ebf924199541acf52d74e -Author: Wolfgang Denk -Date: Mon Apr 28 10:55:24 2008 +0200 - - katmai: fix section overlap problem - - Since we didn't want to remove features from the configuration, we - decided to increase the U-Boot image size (add one flash sector). - - Also changed the default environment definition to make it - independent of such changes. - - Signed-off-by: Wolfgang Denk - Acked-by: Stefan Roese - -commit 03c6cd39f9184143fd8c537872b3d4b2e03f1466 -Author: Kumar Gala -Date: Sat Apr 26 11:44:44 2008 -0500 - - post: Fix building with O= - - Signed-off-by: Kumar Gala - -commit fd7531c1e9d56b9e5e06d2c0e02b798dab72f70c -Author: Wolfgang Denk -Date: Sat Apr 26 01:55:00 2008 +0200 - - Prepare v1.3.3-rc1 - - Signed-off-by: Wolfgang Denk - -commit 19cf2ec90d8ce52da60c1693693c4048cb810967 -Author: Wolfgang Denk -Date: Sat Apr 26 01:25:39 2008 +0200 - - post/Makefile: make sure to use the correct flags - - ARFLAGS was not set, which caused "ppc_8xx-ar: creating libgenpost.a" - messages to be printed. - - Signed-off-by: Wolfgang Denk - -commit 7ed4011733e7dca8f64d21291e4294662f7dc3e2 -Author: Wolfgang Denk -Date: Sat Apr 26 00:34:42 2008 +0200 - - Coding Style cleanup, update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit f9204e15173834ff8d123e36279ce49c3c6c74fc -Author: Magnus Lilja -Date: Sun Apr 20 10:38:12 2008 +0200 - - i.MX31: Enable SPI and MC13783/RTC support for the Litekit board - - This patch enables SPI and MC13783/RTC support for the Litekit board. - - Signed-off-by: Magnus Lilja - -commit f97abbfb47d9e407354e157cae3f6369e460cd37 -Author: Ed Swarthout -Date: Fri Apr 25 01:08:32 2008 -0500 - - MPC8544DS: decode pcie3 end-point configuration correctly. - - Signed-off-by: Ed Swarthout - Signed-off-by: Kumar Gala - -commit 292188e15523c165c4269403fdcd33c26d89176e -Author: Roy Zang -Date: Fri Apr 25 00:55:09 2008 -0500 - - MPC8544DS: Removes the unknown flash message information - - This patch removes the unknown flash message information: - '## Unknown FLASH on Bank 1 - Size = 0xdeadbeef = -286261248 MB' - This unknown flash message is caused by PromJet. - Some of the board user is unhappy with this information. - - Signed-off-by: Roy Zang - Signed-off-by: Kumar Gala - -commit b2115757403beef0ac6bc2c6c3b24f31256a75d2 -Author: Kim Phillips -Date: Thu Apr 24 14:07:38 2008 -0500 - - mpc83xx: bump loadaddr over fdtaddr to 0x500000 - - this seems as a good compromise between human memory, typing, - and last but not least, to accommodate for current and future kernel bloat. - - Signed-off-by: Kim Phillips - Acked-by: Dave Liu - -commit be5a7190265a34d968578ff266549c60f6f57654 -Author: Dave Liu -Date: Tue Apr 15 13:12:23 2008 +0800 - - mpc83xx: clean up the readme for 83xx boards - - 1. correct the typo - 2. correct the memory map for 837xerdb board - - Signed-off-by: Dave Liu - -commit bcae52a6819ee9dad5d0d96cd7daeb20108d45ff -Author: Dave Liu -Date: Tue Apr 15 13:11:11 2008 +0800 - - mpc83xx: remove the unused CPM's stuff - - The MPC83xx family never have CPM block, so remove it from 83xx. - - Signed-off-by: Dave Liu - -commit c63ad6325a8ac0097a54b418a3288926b0484b18 -Author: Matthias Fuchs -Date: Fri Apr 18 16:29:40 2008 +0200 - - cfi-flash: Add CFG_FLASH_AUTOPROTECT_LIST - - This patch adds a configurable flash auto protection list that can be used - to make U-Boot protect flash regions in flash_init(). - - The idea has been discussed on the u-boot mailing list starting - on Nov 18th, 2007. - - Even this patch brings a new feature it is used as a bugfix for 4xx - platforms where flash_init() does not completely protect the - monitor's flash range in all situations. - - U-Boot protects the flash range from CFG_MONITOR_BASE to - (CFG_MONITOR_BASE + monitor_flash_len - 1) by default. This does not - include the reset vector at 0xfffffffc. - - Example: - #define CFG_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}} - - This config option will auto protect the last 512k of flash that - contains the bootloader on board like APC405 and PMC405. - - Signed-off-by: Matthias Fuchs - -commit d0d91ae3acb4f29d1a2a3a766747478ed54e2848 -Author: Stefan Roese -Date: Fri Apr 25 13:59:03 2008 +0200 - - ppc4xx: Remove double defines in lwmon5.h - - introduced with latest lwmon5/POST merge - - Signed-off-by: Stefan Roese - -commit 7590378fb9c686709492ceb142825cd058255956 -Author: Bartlomiej Sieka -Date: Fri Apr 25 13:54:02 2008 +0200 - - Use watchdog-aware functions when calculating hashes of images - take two - - Some files didn't get updated properly with the "Use watchdog-aware - functions when calculating hashes of images" commit, this commit - fixes this. - - Signed-off-by: Bartlomiej Sieka - Signed-off-by: Wolfgang Denk - -commit 8e048c438e20ec89b49da5f085f8f756eba6e587 -Author: Matthias Fuchs -Date: Fri Apr 25 12:01:39 2008 +0200 - - ppc4xx: Add bootcount limit handling for APC405 boards - - Signed-off-by: Matthias Fuchs - -commit 1de6b28be5d107ae90ad7a8a43653c49966e8afe -Author: Bartlomiej Sieka -Date: Fri Apr 25 12:10:09 2008 +0200 - - Use watchdog-aware functions when calculating hashes of images - - Signed-off-by: Bartlomiej Sieka - -commit d00ce09040d3100e2c7998ef56db62c2d20d9ee3 -Author: Wolfgang Denk -Date: Fri Apr 25 12:44:08 2008 +0200 - - USB: fix more GCC 4.2.x aliasing warnings - - Signed-off-by: Wolfgang Denk - Acked-by: Markus Klotzbuecher - -commit aff4f86448f6586930f0a3be7fc4b0ddcf450980 -Author: Wolfgang Denk -Date: Fri Apr 25 12:41:53 2008 +0200 - - lib_generic/crc32.c: add missing #include - - Signed-off-by: Wolfgang Denk - -commit 03ccdbcd5602610cea4bd0db7e48e1ef881a51ef -Author: Wolfgang Denk -Date: Fri Apr 25 11:52:21 2008 +0200 - - lib_generic/crc32.c: fix compile problem - - Signed-off-by: Wolfgang Denk - -commit 24bfedbd0be4dcaa94861407820d6a70fea7e03b -Author: Stefan Roese -Date: Tue Apr 22 12:20:32 2008 +0200 - - ppc4xx: Pass PCIe root-complex/endpoint configuration to Linux via the fdt - - The PCIe root-complex/endpoint setup as configured via the "pcie_mode" - environment variable will now get passed to the Linux kernel by setting - the device_type property of the PCIe device tree node. For normal root- - complex configuration it will keep its defaults value of "pci" and for - endpoint configuration it will get changed to "pci-endpoint". - - Signed-off-by: Stefan Roese - -commit eb0615bf600d2caf5aa2958f47f5ba364c52d5e7 -Author: Yuri Tikhonov -Date: Thu Apr 24 10:30:53 2008 +0200 - - lwmon5: watchdog POST fix - - Use the GPT0_MASKx registers as the temporary storage for watch-dog - timer POST test instead of GPT0_COMPx. The latter - (GPT0_COMP1..GPT0_COMP5) are used for the log-buffer header. - - Signed-off-by: Sergei Poselenov - Signed-off-by: Yuri Tikhonov - -commit 78e488298824bc150b5f3ebf7958cd71fa2af1b9 -Author: Kim Phillips -Date: Mon Apr 21 18:10:14 2008 -0500 - - lib_ppc: Revert "Make MPC83xx one step closer to full relocation." - - This reverts commit 70431e8a7393b6b793f77957f95b999fc9a269b8 which has - proven problematic getting right from the start at least on 83xx and - 4xx. - - Signed-off-by: Kim Phillips - -commit a99715b8ebfc500f3f40e01b36b64d473938443d -Author: Detlev Zundel -Date: Fri Apr 18 14:50:01 2008 +0200 - - Realining some header definitions. - - Signed-off-by: Detlev Zundel - -commit 4acbc6c7f993cae409c424615415a3e76820f13d -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Thu Apr 24 07:57:16 2008 +0200 - - NE2000: coding style cleanup - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit b4aff1ffaf7120032c653357c007faa14f74d29d -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Wed Apr 23 00:11:47 2008 +0900 - - qemu-mips.h: Add CFI support - - CONFIG_ENV_OVERWRITE is also added. - - This patch is originally created by Jean-Christophe PLAGNIOL-VILLARD. - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Shinya Kuribayashi - -commit 4a1f11b45a82908e5b0df602d703082413a6b7ed -Author: Shinya Kuribayashi -Date: Tue Apr 22 22:47:27 2008 +0900 - - doc/README.mips: Add MIPS notes - - Signed-off-by: Shinya Kuribayashi - -commit 215b01bba8bc662d35f72b084700b192d367dfb4 -Author: Bartlomiej Sieka -Date: Tue Apr 22 12:27:56 2008 +0200 - - Add support for calculating hashes with watchdog triggering - - Implement watchodg-aware variants of hash calculation functions: - - crc32_wd() - - md5_wd() - - sha1_csum_wd() - The above functions calculate the hash of the input buffer in chunks, - triggering the watchdog after processing each chunk. The chunk size - is given as a function call parameter. - - Signed-off-by: Bartlomiej Sieka - -commit 8875e3abab986df930167ce5c1ac4f95dcacc81c -Author: Shinya Kuribayashi -Date: Wed Apr 23 11:02:12 2008 +0900 - - qemu-mips: Cleanup whitespace, indentation, etc. - - No functional change. - - This patch was originally submitted by Jean-Christophe PLAGNIOL-VILLARD. - Then I re-created from scratch, and changed more lines than the original. - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Shinya Kuribayashi - -commit 386563197e3a50b0e97ad9aae87f57d9aab909ab -Author: Vlad Lungu -Date: Wed Oct 10 23:02:09 2007 +0300 - - Fixed pcnet io_base - - Bus and phys address are not always the same - - Signed-off-by: Vlad Lungu - -commit 11ea26fd1cb63c91403fe04a6eea975cd418603f -Author: Wolfgang Denk -Date: Thu Apr 24 23:44:26 2008 +0200 - - drivers/net/pcnet.c: Coding Style cleanup. - - Signed-off-by: Wolfgang Denk - -commit 899ef7b84578b7cafadfd78488c2fd2aac93f636 -Author: Vlad Lungu -Date: Wed Oct 10 23:04:23 2007 +0300 - - Added Am79C970A chip id to pcnet - - Signed-off-by: Vlad Lungu - -commit 17c9de6bb33f676eb776dcbfc46fc1b14c3871a5 -Author: Magnus Lilja -Date: Sun Apr 20 10:35:03 2008 +0200 - - i.MX31: Fix architecture numbers for ADS and Litekit boards - - Correct the Linux architecture number for i.MX31 Litekit and ADS boards. - - Signed-off-by: Magnus Lilja - -commit e7ae84d6c7288790e88639f57cb60daf89c11369 -Author: Magnus Lilja -Date: Sun Apr 20 10:36:36 2008 +0200 - - i.MX31: Use symbolic names for Litekit membases. - - Use symbolic names instead of hard coded addresses for Litekit membases. - - Signed-off-by: Magnus Lilja - -commit 2ef1d9b6030d02f576b1bcd9fec948e602522012 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Apr 19 17:59:20 2008 +0200 - - Fix show_boot_progress prototype - - in commit fad634071 "make show_boot_progress () weak." - show_boot_progress is supposed to be declared as weak but declared as - inline instead. - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit edbed247a14d70b94958010f736621212285de91 -Author: Bartlomiej Sieka -Date: Fri Apr 18 12:39:23 2008 +0200 - - Memory footprint optimizations - - As suggested by Wolfgang Denk: - - image printing functions: - - remove wrappers - - remove indentation prefix from functions' signatures - - merge getenv_verify and getenv_autostart into one parametrized function - - Signed-off-by: Bartlomiej Sieka - -commit 0a0b606faaec4afb3f750b09aa4df1e40a39dcb8 -Author: Guennadi Liakhovetski -Date: Tue Apr 15 13:33:11 2008 +0200 - - MX31ADS environment variable update, spi and rtc support - - Update MX31ADS default environment to better match the flash layout and - the memory map, support SPI and RTC. - - Signed-off-by: Guennadi Liakhovetski - -commit 022f12163595b9a55380c6d77c3119b93d6a9a4b -Author: Kumar Gala -Date: Mon Apr 21 09:28:36 2008 -0500 - - 85xx: Round up frequency calculations to get reasonable output - - eg. because of rounding error we can get 799Mhz instead of 800Mhz. - - Introduced DIV_ROUND_UP and roundup taken from linux kernel. - - Signed-off-by: Dejan Minic - Signed-off-by: Srikanth Srinivasan - Signed-off-by: Kumar Gala - Acked-by: Andy Fleming - -commit 876b8f978982216ab4a22dcd9efddfcd9b0e04e6 -Author: Kumar Gala -Date: Wed Apr 23 16:58:04 2008 -0500 - - fsl_pci: Only modify registers if we have them - - pme_msg_det exists only on PCIe controllers only set it if we are a "bridge". - - Signed-off-by: Kumar Gala - -commit 83fe32334337def160b302aa9d152d808bfcc68e -Author: Markus Klotzbücher -Date: Wed Apr 23 10:57:33 2008 +0200 - - USB: remove a cpu bug workaround for an unsupported architecture. - - Signed-off-by: Markus Klotzbuecher - -commit f957576cb53e6cfab412709cfc8db1afd39d21c3 -Author: Markus Klotzbücher -Date: Wed Apr 23 10:53:23 2008 +0200 - - USB: fix those pesky aliasing warnings issued by gcc-4.2 - - Signed-off-by: Markus Klotzbuecher - Signed-off-by: Detlev Zundel - -commit 89cdab788f3716b335fefb60b836ebcf975aceab -Author: Mike Frysinger -Date: Mon Mar 31 11:02:01 2008 -0400 - - crc32: use uint32_t rather than unsigned long - - The envcrc.c does sizeof(unsigned long) when calculating the crc, but - this is done with the build toolchain instead of the target tool - chain, so if the build is a 64bit system but the target is 32bits, - the size will obviously be wrong. This converts all unsigned long - stuff related to crc32 to uint32_t types. Compile tested only: output - of ./tools/envcrc when run on a 32bit build system matches that of a - 64bit build system. - - Signed-off-by: Mike Frysinger - Acked-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 80c40b765b3642ddb9f3392b7898715aab44a29c -Author: Dirk Behme -Date: Wed Mar 26 09:53:29 2008 +0100 - - ARM: Davinci: Fix DM644x timer overflow handling and cleanup - - Fix ARM based DaVinci DM644x timer overflow handling and cleanup timer code. - - Changes: - - - Remove *_masked() functions as noted by Wolfgang - - - Adapt register naming to recent TI spec (sprue26, March 2007) - - - Fix reset_timer() handling - - - As reported by Pieter [1] the overflow fix introduced a delay of factor 16 (e.g 2 seconds became 32). While the overflow fix is basically okay, it missed to divide udelay by 16, too. Fix this. - - [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/38179 - - - Remove software division of timer count value (DIV(x) macro) and do it in hardware (TIM_CLK_DIV). - - Many thanks to Troy Kisky and Pieter Voorthuijsen for the hints & testing! - - Patch is compile tested with davinci_dvevm & sonata & schmoogie configuration and tested by Pieter on DaVinci EVM hardware. - - Signed-off-by: Dirk Behme - Acked-by: Pieter Voorthuijsen - -commit a6e6fc610e39dec41b79680413d4ed38145bd3c8 -Author: Sergei Poselenov -Date: Wed Apr 9 16:09:41 2008 +0200 - - Added watchdog triggering calls in the "mtest" test function. - - Signed-off-by: Sergei Poselenov - -commit d32a874b9b4c1e949ee38be7790f6bf6d6143451 -Author: Yuri Tikhonov -Date: Sun Apr 6 19:19:14 2008 +0200 - - lwmon5 watchdog: limit trigger rate - - Limit the rate of h/w watch-dog triggering on the LWMON5 board by - the CONFIG_WD_MAX_RATE value. - - Note that an earlier version of this patch which used microseconds - instead of ticks dis not work. The problem was that we used - usec2ticks() to convert microseconds into ticks. usec2ticks() uses - get_tbclk(), which in turn calls get_sys_info(). It turns out that - this function does a lot of prolonged operations (like divisions) - which take too much time so we do not trigger the watchdog in time, - and it resets the system. - - Signed-off-by: Yuri Tikhonov - -commit 2d2b994a30bb100774dc747ae9865b7f95285a88 -Author: Yuri Tikhonov -Date: Mon Mar 31 10:51:37 2008 +0200 - - POST: move CONFIG_POST to Makefiles - - Introduce the new logical option CONFIG_HAS_POST which is set when the - platform has CONFIG_POST set. Use CONFIG_HAS_POST in the post/ Makefiles - to determine should the POST libs be compiled for the selected target - platform, or not. - - To avoid breaking u-boot linking process, the empty post/libpost.a file is - created for platforms which do not have POSTs. - - Signed-off-by: Yuri Tikhonov - Signed-off-by: Wolfgang Denk - -commit 0a51e9248e2d27e0a02ef1e740c576ce90a39ee1 -Author: Yuri Tikhonov -Date: Mon Mar 31 10:49:34 2008 +0200 - - POST: preparations for moving CONFIG_POST to Makefiles - - Remove CONFIG_POST ifdefs from the post/ source files. - - Signed-off-by: Yuri Tikhonov - Signed-off-by: Wolfgang Denk - -commit 5d40d4430d9ebc8434c6f0798594836e1efa7a1e -Author: Stefan Roese -Date: Tue Apr 22 14:14:20 2008 +0200 - - ppc4xx: Fix Canyonlands and Glacier default environment for fdt usage - - This patch fixes the Canyonlands and Glacier default environment to better - fit to the arch/powerpc device-tree kernels. The variables dealing with - arch/ppc booting are removed, since these boards are supported only in - arch/powerpc. Glacier uses the same config file as Canyonlands. - - Also, the Glacier now uses non-FPU rootpath, since 460GT has no FPU. - - Signed-off-by: Stefan Roese - -commit b789cb4a4c0c1deff82053539cfe29a9c6e23f8b -Author: Stefan Roese -Date: Tue Apr 22 14:06:42 2008 +0200 - - ppc4xx: Small coding style cleanup for the latest esd patches - - Signed-off-by: Stefan Roese - -commit 79941d63bc03aed8c48d7602f18217cc200ee931 -Author: Matthias Fuchs -Date: Mon Apr 21 18:01:07 2008 +0200 - - ppc4xx: Update CPU strapping for PMC440 boards - - This patch removes the temporary 'test' strapping option - of the sbe command. The '667' strapping option now uses - a PLB/PCI divider of 3. - - Signed-off-by: Matthias Fuchs - -commit f00cf3193a6635355b121e90debb2f54e777e7da -Author: Matthias Fuchs -Date: Mon Apr 21 14:42:21 2008 +0200 - - ppc4xx: Remove unused APC405 strataflash driver - - The APC405 board support has been migrated to use the common - CFI flash driver. - - Signed-off-by: Matthias Fuchs - -commit 1c686676a86473bbd92151f0544e109413f6ed06 -Author: Matthias Fuchs -Date: Mon Apr 21 14:42:17 2008 +0200 - - ppc4xx: Update APC405 configuration - - - enable esd's auto_update mechanism - - support alternative flash layout on rev. 1.8 boards - - update default environment - - use common CFI flash driver - - coding style cleanup - - Signed-off-by: Matthias Fuchs - -commit 0b9872515a521bf7866dc24b85ddce708e60d702 -Author: Matthias Fuchs -Date: Mon Apr 21 14:42:11 2008 +0200 - - ppc4xx: Update APC405 board support - - - enable esd's auto_update mechanism - - fix LCD support on latest hardware revision (uses other LCD controller) - - support alternative flash layout on rev. 1.8 boards - - coding style cleanup - - Signed-off-by: Matthias Fuchs - -commit 83975d02e225e231960784972e7820a8b303756b -Author: Matthias Fuchs -Date: Mon Apr 21 14:42:06 2008 +0200 - - ppc4xx: update esd's common auto_update code for 405 boards - - - Coding style cleanup (long lines) - - improve handling of protected flash regions - - remove dead code - - Signed-off-by: Matthias Fuchs - -commit b9233fe5d59cb25d975071616bd1035d6f4c2285 -Author: Matthias Fuchs -Date: Mon Apr 21 14:41:59 2008 +0200 - - ppc4xx: Update esd's common LCD code for 405 boards - - - Coding style cleanup (long lines) - - Add s1d13505 support - - Make some functions return a result code instead of void - - Signed-off-by: Matthias Fuchs - -commit dea68189424c3f1242427a8146a3861bf093173c -Author: Matthias Fuchs -Date: Mon Apr 21 11:36:55 2008 +0200 - - ppc4xx: Update FPGA image for APC405 boards - - Signed-off-by: Matthias Fuchs - -commit 2a05b152924acfcec3b037693329e517e6d3578f -Author: Matthias Fuchs -Date: Mon Apr 21 11:36:08 2008 +0200 - - ppc4xx: Update bootlogo for APC405 boards - - Signed-off-by: Matthias Fuchs - -commit 8deafdc6ad368368cf03b58cab4bd39f45d64b5c -Author: Stefan Roese -Date: Fri Apr 18 16:41:31 2008 +0200 - - ppc4xx: Add dcache_enable() for 440 - - dcache_enable() was missing for 440 and the patch - 017e9b7925f74878d0e9475388cca9bda5ef9482 ["allow ports to override bootelf - "] behavior uses this function. - - Note: Currently the cache handling functions like - d/icache_disable/enable() are NOP's on 440. This may be changed in the - future. - - Signed-off-by: Stefan Roese - -commit a49e0d177a0749614b316ec847fb623f09c82c07 -Author: Matthias Fuchs -Date: Mon Apr 21 11:19:04 2008 +0200 - - video: Add missing free for logo memory - - This patch adds two missing free()s. - - Signed-off-by: Matthias Fuchs - -commit 84c01d3a05ae3aca5f7c0c13a31ca72ba1199a42 -Author: Troy Kisky -Date: Mon Sep 24 16:41:43 2007 -0700 - - PATCH - Fix oob data copied into supplied buffer - - This patch correctly sets the oobavail variable - and fixes a bug where the oob data was not valid when - there where multiple groups in oobfree. - - First segment fixes a typo - Second segment fixes a bug where oob data may be copied incorrectly. - Third segment adds an error message when exiting due to write protect. - Forth segment fixes a bug where oobavail may be set incorrectly. - - Signed-off-by: Troy Kisky - -commit e1d09680f64b452adde89ed9fe28a77c56bedc9a -Author: Matthias Fuchs -Date: Fri Apr 18 17:24:32 2008 +0200 - - ppc4xx: Fix sys_get_info() for 405GP(r) - - This patch assigns the correct EBC clock for 405GP(r) CPUs - to PPC4xx_SYS_INFO structure. Without this patch U-Boot - uses an uninitialized EBC clock in its startup message. - - Signed-off-by: Matthias Fuchs - -commit dc7746d86d2a3dfe01ab9a70cb427f92adc303c7 -Author: Wolfgang Denk -Date: Sun Apr 20 15:39:38 2008 -0700 - - Makefile: remove nand_spl/System.map when cleaning up. - -commit d9a42c0ace4d4f9cb061d62a7265d1780f90447b -Author: Wolfgang Denk -Date: Sun Apr 20 15:35:52 2008 -0700 - - MAKEALL: sort entries / lists. - - Signed-off-by: Wolfgang Denk - -commit 0878af169b181868a105b5c33f3a6423e2c9fd60 -Author: Kumar Gala -Date: Fri Apr 18 11:29:01 2008 -0500 - - 85xx: Fix size of cpu-release-addr property - - The cpu-release-addr is defined as always being a 64-bit quanity regardless - if we are running on a 32-bit or 64-bit machine. - -commit 88353a985109562a639b2f8a0c90d77011bfe374 -Author: Timur Tabi -Date: Fri Apr 4 11:15:58 2008 -0500 - - Fix calculation of I2C clock for some 85xx chips - - Some 85xx chips use CCB as the base clock for the I2C. Some use CCB/2, and - some use CCB/3. There is no pattern that can be used to determine which - chips use which frequency, so the only way to determine is to look up the - actual SOC designation and use the right value for that SOC. - - Update immap_85xx.h to include the GUTS PORDEVSR2 register. - - Signed-off-by: Timur Tabi - -commit 1e01477aeaf409ddb97e2633aab9cf8c9c60612e -Author: Wolfgang Denk -Date: Fri Apr 18 11:44:27 2008 -0700 - - Fix build breakage casued by commit c0559be371b2 - - Change env_get_char from a global function ptr to a function. - - Signed-off-by: Wolfgang Denk - -commit 268a804d7e2fa07b64211fd2f9a9615db4539f23 -Author: Wolfgang Denk -Date: Fri Apr 18 10:53:41 2008 -0700 - - Coding Style cleanup, update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit 92bad20ad74b70adf3839df9a0a47cce000ac3d7 -Author: Mike Frysinger -Date: Tue Apr 8 14:00:57 2008 -0400 - - Add support for u-boot in svn and localversion-* files - - Signed-off-by: Mike Frysinger - -commit d23ff6827decf121461fbc5622612fd7effe207e -Author: Guennadi Liakhovetski -Date: Thu Apr 3 17:04:22 2008 +0200 - - MX31ADS network and flash updates - - This patch allows U-Boot to use buffered writes to the Spansion NOR - flash installed on this board, and eliminates long delays in network - transfers after the board startup. - - Also modify flash layout to embed main and redundant environment - blocks in the U-Boot image. - - Signed-off-by: Guennadi Liakhovetski - -commit b5dc9b304d289831f291843ff88a45cbdf1a6290 -Author: Guennadi Liakhovetski -Date: Mon Apr 14 10:53:12 2008 +0200 - - Support for the MX31ADS evaluation board from Freescale - - This patch adds support for the MX31ADS evaluation board from Freescale, - initialization code is copied from RedBoot sources, also provided by - Freescale. - - Signed-off-by: Guennadi Liakhovetski - -commit 499e7831e1baaac6bfb959213f1950c216fbc5ba -Author: Stefan Roese -Date: Tue Apr 8 10:33:29 2008 +0200 - - ppc4xx: Change Canyonlands to support booting from 2k page NAND devices - - Signed-off-by: Stefan Roese - -commit 5e182dce04d68cc94407a1b1fa09307f2bb96719 -Author: Stefan Roese -Date: Tue Apr 8 10:33:28 2008 +0200 - - ppc4xx: Adjust Canyonlands fixed DDR2 setup (NAND booting) to 512MB SODIMM - - Signed-off-by: Stefan Roese - -commit fe7c0db6b2a9004f96c2a2d4fff2849e19c2d825 -Author: Stefan Roese -Date: Tue Apr 8 10:33:27 2008 +0200 - - ppc4xx: Add Glacier NAND booting target - - Signed-off-by: Stefan Roese - -commit 46f373838e384a4c23d13581b1dfa5acb66b5810 -Author: Stefan Roese -Date: Tue Apr 8 10:31:00 2008 +0200 - - nand_spl: Update nand_spl to support 2k page size NAND devices - - This patch adds support for booting from 2k page sized NAND device - (e.g. Micron 29F2G08AAC). - - Tested on AMCC Canyonlands. - - Signed-off-by: Stefan Roese - -commit 5e3dca577b7c1bf58bd2b48449b18b7e7dcd8e04 -Author: Anatolij Gustschin -Date: Thu Apr 17 18:18:00 2008 +0200 - - Fix crash on sequoia in ppc_4xx_eth_init - - Currently U-Boot crashes in ppc_4xx_eth_init on sequoia - with cache enabled (TLB Parity exeption). This patch - fixes the problem. - - Signed-off-by: Anatolij Gustschin - -commit accf7355767dc7f6b85d88bb1c75c9d95e84ba5b -Author: Anatolij Gustschin -Date: Thu Apr 17 18:15:27 2008 +0200 - - ppc4xx: Fix crash on sequoia with cache enabled - - Currently U-Boot crashes on sequoia board in CPU POST if - cache is enabled (CONFIG_4xx_DCACHE defined). The cache - won't be disabled by change_tlb before CPU POST because - there is an insufficient adress range check since - CFG_MEM_TOP_HIDE was introduced. This patch tries to fix - this problem. - - Signed-off-by: Anatolij Gustschin - -commit 43c509254fab375c49936498da944658117ed07c -Author: Shinya Kuribayashi -Date: Thu Apr 17 23:35:13 2008 +0900 - - Use jr as register jump instruction - - Current assembler codes are inconsistent in the way of register jump - instruction usage; some use jr, some use j. Of course GNU as allows both - usages, but as can be expected from `Jump Register' the mnemonic `jr' is - more intuitive than `j'. For example, Linux doesn't have `j ' usage - at all. - - Signed-off-by: Shinya Kuribayashi - -commit 7ce63709828d37b08866e537339a169bd0db2bd3 -Author: Guennadi Liakhovetski -Date: Tue Apr 15 14:15:30 2008 +0200 - - RTC driver for MC13783 - - MC13783 is a multifunction IS with an SPI interface to the host. This - driver handles the RTC controller in this chip. - - Signed-off-by: Guennadi Liakhovetski - -commit 38254f45b0b412332726c90d3184ad47479fcffb -Author: Guennadi Liakhovetski -Date: Tue Apr 15 14:14:25 2008 +0200 - - New i.MX31 SPI driver - - This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far - only implemented and tested on i.MX31, can with a modified register layout - and definitions be used for i.MX27, I think, MXC CPUs have similar SPI - controllers too. - - Signed-off-by: Guennadi Liakhovetski - -commit 7064122c2eef92f02a03ef37a1a1c07e70cd4e38 -Author: Magnus Lilja -Date: Tue Apr 15 19:09:10 2008 +0200 - - Fix name of i.MX31 boards in config file header - - Correct the name of the i.MX31 Litekit and phyCORE boards in config files. - - Signed-off-by: Magnus Lilja - -commit a49864593e083a5d0779fb9ca98e5a0f2053183d -Author: Mike Frysinger -Date: Sun Apr 13 19:42:19 2008 -0400 - - allow ports to override go behavior - - Split the arch-specific logic out of the common go code and into a dedicated - weak function called do_go_exec() that lives in cpu directories. This will - need review from i386/nios people to make sure I didn't break them. - -commit 017e9b7925f74878d0e9475388cca9bda5ef9482 -Author: Mike Frysinger -Date: Sun Apr 13 19:42:18 2008 -0400 - - allow ports to override bootelf behavior - - Change the bootelf setup function into a dedicated weak function called - do_bootelf_exec. This way ports can control the behavior however they - like before/after calling the ELF entry point. - -commit a4b46ed6b3502335c3f3a5d672abe0bcb44f20b7 -Author: Ulf Samuelsson -Date: Sat Apr 12 20:56:03 2008 +0200 - - Reorder ARM boards in Makefile - - Rearrange ARM boards in Makefile so that ARM926EJ-S boards - are no longer under ARM92xT header. - - Signed-off-by: Ulf Samuelsson - Ack-By Jean-Christophe PLAGNIOL-VILLARD - -commit c3a60cb3bd67e120fc99b6ba88d9295c3c07f688 -Author: Ulf Samuelsson -Date: Sat Apr 12 20:29:44 2008 +0200 - - Clean up dataflash partitioning - - This patch removes the board dependent parts from - "drivers/mtd/dataflash.c". - Each board relying on this, will have the appropriate - code in a new file, "partition.c" in the board directory. - board Makefiles updated to use the file. - - The dataflash partitions are aligned on sector/page boundaries. - - The CONFIG_NEW_DF_PARTITION was used to create named partitions - This is now the default operation, and the CONFIG variable is removed. - - Signed-off-by: Ulf Samuelsson - -commit 51ecde946fec511a16346e498204ca10ad71080d -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Apr 12 14:08:45 2008 +0200 - - gitignore: udpate stgit generated and .patch file - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 66e39818e95f51ee1c1dd2094407a8929543fa6d -Author: Wolfgang Denk -Date: Fri Apr 18 00:15:36 2008 -0700 - - Get rid of redundant copy of renamed header file. - - Signed-off-by: Wolfgang Denk - -commit c3aafd8cf814e33a77de81c2f22b8c772216a3cc -Author: Vlad Lungu -Date: Fri Apr 11 21:20:14 2008 +0300 - - Fix dependency generation for older gcc versions - - With gcc 3.3.3 at least, compilation fails with - - Generating include/autoconf.mk - gcc: compilation of header file requested - make: *** [include/autoconf.mk] Error 1 - - since commit 16fe77752eee099b9fb61ed73460e51cc94b37ba. - - Signed-off-by: Vlad Lungu - -commit cb1c4896905ab22fcd982e6a8a539f0031942e71 -Author: Marian Balakowicz -Date: Fri Apr 11 11:07:49 2008 +0200 - - Restore the ability to continue booting after legacy image overwrite - - Before new uImage code was merged, bootm code allowed for the kernel image to - get overwritten during decompresion. new uImage introduced a check for image - overwrites and refused to boot the image that got overwritten. This patch - restores the old behavior. It also adds a warning when the image overwriten is - a multi-image file, because in such case accessing componentes other than the - first one will fail. - - Signed-off-by: Marian Balakowicz - -commit de2b3216e6b4f3b2fe93759c05b17504f9dfe036 -Author: Marian Balakowicz -Date: Fri Apr 11 11:07:43 2008 +0200 - - ppc: Fix ftd_blob variable init when processing raw blob - - Set fdt_blob variable before its value is printed out. - - Signed-off-by: Marian Balakowicz - -commit 3d36be030043cd841a2551d00a395135e363a64b -Author: Jason Wessel -Date: Thu Apr 10 14:30:16 2008 -0500 - - Remove all the search paths from the .lds files. - - The cross compiler is responsible for providing the correct libraries - and the logic to find the linking libraries. - - Signed-off-by: Jason Wessel - -commit 7d721e34ae6be7d7db63e8d060a246278bb7ae58 -Author: Bartlomiej Sieka -Date: Mon Apr 14 15:44:16 2008 +0200 - - Boot-related documentation update - - - document 'bootm_low' and 'bootm_size' environment variables - - update inaccurate CFG_BOOTMAPSZ entry - - Signed-off-by: Bartlomiej Sieka - -commit a6f0bd9f2b1971e2a61ac0fd1fc2c96cb7a4b67a -Author: Guennadi Liakhovetski -Date: Wed Apr 9 17:34:08 2008 +0200 - - Fix regression introduced by a typo in "Tidied other cpu/arm920t/start.S code" - - Restore logic reverted by commit - - commit 80767a6cead9990d9e77e62be947843c2c72f469 - Author: Peter Pearse - Date: Wed Sep 5 16:04:41 2007 +0100 - - Changed API name to coloured_led.h - Removed code using deprecated ifdef CONFIG_BOOTBINFUNC - Tidied other cpu/arm920t/start.S code - - Signed-off-by: Guennadi Liakhovetski - -commit e25cb8d3f4fcc265a9cdf8e9d577b59bdb64bbaf -Author: Mike Frysinger -Date: Tue Apr 8 10:24:24 2008 -0400 - - Remove conflicting NAND ID - - There are two NAND entries with ID 0xDC and this obviously causes problems. - In the kernel, they punted the first entry, so we should do the same. - - See this upstream e-mail for more info: - http://lists.infradead.org/pipermail/linux-mtd/2007-July/018795.html - - Signed-off-by: Michael Hennerich - Signed-off-by: Mike Frysinger - -commit 188e94c370621708d13547d58dbc6ed3c5602aa8 -Author: Shinya Kuribayashi -Date: Tue Apr 8 16:20:35 2008 +0900 - - cpu/mips/cpu.c: Fix flush_cache bug - - Cache operations have to take line address (addr), not start_addr. - I noticed this bug when debugging ping failure. - - Signed-off-by: Shinya Kuribayashi - -commit 8f2a68a07c058fca1d413e54f71c2e7e78a74ed4 -Author: Martin Krause -Date: Thu Apr 3 14:29:01 2008 +0200 - - TQM5200: fix default IDE reset level - - Before the first call of ide_reset(), the level of the IDE reset - signal on the TQM5200 is low (reset asserted). This patch sets the - default value to high (reset not asserted). - - Currently this patch fixes no real problem, but it is cleaner to - assert the reset signal only on demand, and not permanently. - - Signed-off-by: Martin Krause - -commit c61e033d6e8abb7b4060ee36060961e1399f6079 -Author: Detlev Zundel -Date: Thu Apr 3 14:18:48 2008 +0200 - - mgcoge, mgsuv: realign CONFIG_EXTRA_ENV_SETTING - - Signed-off-by: Detlev Zundel - -commit f308572e19eb7fe63aa3d41f214cde4c23c9800f -Author: Detlev Zundel -Date: Thu Apr 3 14:18:47 2008 +0200 - - mgcoge, mgsuv: rename 'addcon' to 'addcons' - - The latter name with 13 users is already established, so we will use - that. - - Signed-off-by: Detlev Zundel - -commit e175eacc87c3a9e4dad0799fee0e95732520afc7 -Author: Martin Krause -Date: Thu Apr 3 13:37:56 2008 +0200 - - IDE: fix bug in reset sequence - - According to the ata (ata5) specification the RESET- signal - shall be asserted for at least 25 us. Without this patch, - the RESET- signal is asserted on some boards for only < 1 us - (e. g. on the TQM5200). This patch adds a general delay of - 25 us to the RESET- signal. - - Without this patch a Platinum 4 GiB CF card is not recognised - properly on boards with a TQM5200 (STK52xx, TB5200). - - Signed-off-by: Martin Krause - -commit 813bea96a960916c72b4a3a7df840151529c26ce -Author: Sascha Laue -Date: Thu Apr 3 14:43:11 2008 +0200 - - lwmon5: disable CONFIG_ZERO_BOOTDELAY - - Signed-off-by: Sascha Laue - -commit 53eec6f1d25932e76d63ccb14082792b0b96bf41 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Wed Apr 2 08:03:58 2008 +0200 - - ds174x: Fix warning on return in rtc_get and rtc_set functions - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit a253b38bf50c85227c33ca0febc870ee49d1588e -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Wed Apr 2 08:03:57 2008 +0200 - - cmd_log.c: Fix assignment differ in signedness - - In function 'logbuff_init_ptrs': - cmd_log.c:79: warning: pointer targets in assignment differ in signedness - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 6c0e9a8f1cc090fbfbc6f86b6b4fd17a1628f3df -Author: Gururaja Hebbar K R -Date: Wed Apr 2 11:04:43 2008 +0530 - - Remove duplicate #undef SHOW_INFO in drivers/usb/usb_ohci.c - - Signed-off-by: gururaja hebbar - -commit 478d5ec9ae3cbcc6040241d2d73dbbc61fe9b49d -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Tue Apr 1 14:07:10 2008 +0200 - - s3c4510b_eth: fix 'packed' attribute ignored for fields of MACFrame - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit c08fb3ea36d19b1640b7906264581e9105534399 -Author: Guennadi Liakhovetski -Date: Tue Apr 15 10:24:14 2008 +0200 - - Additional PCI IDs for IDE and network controllers - - These PCI IDs are required by the Linkstation platforms. - - Signed-off-by: Guennadi Liakhovetski - -commit c0559be371b2a64b1a817088c3308688e2182f93 -Author: Joakim Tjernlund -Date: Mon Apr 14 23:01:50 2008 +0200 - - Change env_get_char from a global function ptr to a function. - - This avoids an early global data reference. - - Signed-off-by: Joakim Tjernlund - -commit 3e0f331c05d72f140715c1e9fca991927e44d422 -Author: Guennadi Liakhovetski -Date: Tue Apr 29 12:35:08 2008 +0000 - - Clean up smsc911x driver - - Replace direct register address derefencing with accessor functions. - Restrict explicitly 32-bit bus-width, extend affected configurations - respectively. - - Signed-off-by: Guennadi Liakhovetski - Signed-off-by: Ben Warren - -commit de1b686b763aa8b87a86f6748ce9169e7fc0e4cd -Author: Sascha Hauer -Date: Tue Apr 15 00:08:20 2008 -0400 - - This patch adds a driver for the following smsc network controllers: - LAN9115 - LAN9116 - LAN9117 - LAN9215 - LAN9216 - LAN9217 - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - Signed-off-by: Ben Warren - -commit 3dfd4aab929cccddb63d9ea509967861e1333b52 -Author: Sascha Laue -Date: Tue Apr 1 15:13:03 2008 +0200 - - Fix watchdog POST for lwmon5 - - If the hardware watchdog detects a voltage error, the watchdog sets - GPIO62 to low. The watchdog POST has to detect this low level. - - Signed-off-by: Sascha Laue - -commit 24b448448a917e52806f82660a5c9d47608894fb -Author: Dave Liu -Date: Tue Apr 1 15:22:11 2008 +0800 - - ata: update the libata.h from ata.h of linux kernel - - Current libata.h of u-boot is out of sync from linux kernel, - this patch make it be consistent with linux kernel. - - Signed-off-by: Dave Liu - Signed-off-by: Tor Krill - -commit f8f9dc98883f66f59eb0601da65808e6b139c87c -Author: Kumar Gala -Date: Mon Mar 31 11:59:27 2008 -0500 - - Allow use of ARCH=powerpc when building - - The linux kernel is now mostly ARCH=powerpc, so to make life easier - allow use to use ARCH=powerpc and convert it to ARCH=ppc. - - Signed-off-by: Kumar Gala - -commit 8af657d2c6d1ca4f2f76973531394d4578ba2ef0 -Author: Kyungmin Park -Date: Mon Mar 31 10:40:54 2008 +0900 - - Add apollon board MAINTAINERS entry - - Signed-off-by: Kyungmin Park - -commit 77e475cc0ed1832160017d364be32a0be9ff02a9 -Author: Kyungmin Park -Date: Mon Mar 31 10:40:36 2008 +0900 - - Fix OneNAND read - - It should access with 16-bit instead of 8-bit - - Now it uses the generic memcpy with 8-bit access. It means it reads wrong data from OneNAND. - - Signed-off-by: Kyungmin Park - -commit a9da2b41079d230db3a5641625311983f85ce1fb -Author: Kyungmin Park -Date: Mon Mar 31 10:40:19 2008 +0900 - - Fix OneNAND erase command - - It mis-calculates the block address. - Also fix DECLARE_GLOBAL_DATA_PTR in env_onenand. - - Signed-off-by: Kyungmin Park - -commit 61525f2ffa156665a66908fda47dbf29d65ea579 -Author: Guennadi Liakhovetski -Date: Mon Mar 31 01:32:15 2008 +0200 - - Support for LinkStation / KuroBox HD and HG PPC models - - This patch is based on the port by Mihai Georgian (see linkstation.c for - Copyright information) and implements support for LinkStation / KuroBox HD - and HG PPC models from Buffalo Technology, whereby HD is deactivated at - the moment, pending network driver fixing. - - Notice to users: this is pretty much a barebone port. Support for network - on HG models is already in the U-Boot mainline, but you might also want - patches to switch fan / phy modes depending on the negotiated ethernet - parameters. This patch also doesn't support console switching, booting EM - mode, Buffalo specific ext2 magic number. So, if you want to use any of - those, you need additional patches. Otherwise this patche provides a fully - functional u-boot with a network console on your system. - - Signed-off-by: Guennadi Liakhovetski - -commit 0f3ba7e9783f352318f197a3148f6d5cc3d75bea -Author: TsiChung Liew -Date: Sun Mar 30 01:22:13 2008 -0500 - - Add CONFIG_MII_INIT support to related boards - - Replace CONFIG_8xx and CONFIG_MCF532x to CONFIG_MII_INIT in - cmd_init.c. Add CONFIG_MII_INIT to board configuration files - that use mii_init() in cmd_init.c. - - Signed-off-by: TsiChung Liew - Acked-by: Ben Warren - -commit f33fca22e76f20e4e4793810ca7a06a4805a6cf4 -Author: TsiChung Liew -Date: Sun Mar 30 01:19:06 2008 -0500 - - Update CONFIG_PCIAUTO_SKIP_HOST_BRIDGE to related boards - - Remove test for CONFIG_MPC5200 in drivers/pci/pci_auto.c and define - CONFIG_PCIAUTO_SKIP_HOST_BRIDGE in related board configuration files. - - Signed-off-by: TsiChung Liew - -commit e99ccb488181d012248c6be30b2093e950319fc5 -Author: Kumar Gala -Date: Thu Mar 27 11:46:38 2008 -0500 - - Introduce phys_size_t and move phys_addr_t into asm/types.h - - Also add CONFIG_PHYS_64BIT on powerpc to deal with 32-bit ppc's - that have larger physical addresses like 44x, 85xx, and 86xx. - - Signed-off-by: Kumar Gala - -commit 20a14a42a25f72e379f38460b8a8484667536795 -Author: Andy Fleming -Date: Wed Apr 2 16:19:07 2008 -0500 - - Rename include/md5.h to include/u-boot/md5.h - - Some systems have md5.h installed in /usr/include/. This isn't the - desired file (we want the one in include/md5.h). This will avoid the - conflict. This fixes the host tools building problem by creating a new - directory for U-Boot specific header files. - - [Patch by Andy Fleming, modified to use separate directory by Wolfgang - Denk] - - Signed-off-by: Wolfgang Denk - Signed-off-by: Andy Fleming - Acked-by: Timur Tabi - -commit f297b7a1ec87433f66320d89d993e1bc738c66b8 -Author: Dave Liu -Date: Thu Mar 27 18:51:17 2008 +0800 - - drivers: code clean up - - Signed-off-by: Dave Liu - -commit 0ff7cba4a2e51c90827f6d21a0b28b4d67109597 -Author: Dave Liu -Date: Thu Mar 27 18:50:41 2008 +0800 - - drivers: clean up the ata_piix.h - - Signed-off-by: Dave Liu - -commit e8f7ba404f1409606962815ecc955a06984b08b3 -Author: Dave Liu -Date: Thu Mar 27 18:49:56 2008 +0800 - - doc: english polishing for README.sata - - according to gvb's suggestion, polishing for the doc. - - Signed-off-by: Jerry Van Baren - Signed-off-by: Dave Liu - -commit 3e3f766a5274d204780460e1879723b565296d34 -Author: Kumar Gala -Date: Wed Mar 26 18:53:28 2008 -0500 - - Fix warnings introduced by I2C bus speed setting patch - - Signed-off-by: Kumar Gala - -commit 3c735e7437150e8615f26930c7819db85634276d -Author: eran liberty -Date: Thu Mar 27 00:50:49 2008 +0100 - - Altera Stratix II support - - Adds Support for Altera's Stratix II. - - Within your board specific init file you will have to call - - 1. fpga_init (/* relocated code offset. usually => */ gd->reloc_off); - 2. fpga_add (fpga_altera, (Altera_desc*)&altera_desc); - - Altera_desc* contines (for example): - { - Altera_StratixII, /* part type */ - passive_serial, /* interface type */ - 1, /* bytes of data part can accept */ - (void *)(&funcs), /* interface function table */ - 0L, /* base interface address */ - 0 /* implementation specific cookie */ - } - - funcs is the interface. It is of type altera_board_specific_func. - It looks like this: - altera_board_specific_func func = { - pre_fn, - config_fn, - status_fn, - done_fn, - clk_fn, - data_fn, - abort_fn, - post_fn, - }; - - you will have to implement these functions, which is usually bit - banging some gpio. - - Signed-off-by: Eran Liberty - -commit 5ece9ec9f6cd52950ab848e2fe422dacf1d3a335 -Author: Wolfgang Denk -Date: Sun Apr 13 14:32:54 2008 -0700 - - Update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 5ad862166aa24d62a69aa9c708f6b2f5c0d28fb7 -Author: Sascha Hauer -Date: Wed Mar 26 20:41:17 2008 +0100 - - Phytec Phycore-i.MX31 support - - This patch adds support for the Phytec Phycore-i.MX31 board - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit caebc95be3b42e5147b5fac7672ac4b2693ef7e1 -Author: Sascha Hauer -Date: Wed Mar 26 20:41:09 2008 +0100 - - mx31 litekit support - - This patch adds support for the mx31 litekit board - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit cdace0661208754a53019ea0dc7b803a040e0939 -Author: Sascha Hauer -Date: Wed Mar 26 20:40:49 2008 +0100 - - add an i2c driver for mx31 - - This patch adds an i2c driver for Freescale i.MX processors - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit 9b56f4f0306f3940b0aafd823ed6ecfc2d75d6c6 -Author: Sascha Hauer -Date: Wed Mar 26 20:40:42 2008 +0100 - - core support for Freescale mx31 - - This patch adds the core support for Freescale mx31 - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit 7ec68862a27c8f6f6d566228de8f6724d964a939 -Author: Wolfgang Denk -Date: Sun Apr 13 14:19:23 2008 -0700 - - Fix compile error - - ...as suggested by Peter Pearse - - Signed-off-by: Wolfgang Denk - -commit 5252ed95204bdf55bec5a90ea69860bf2f78c643 -Author: Sascha Hauer -Date: Wed Mar 26 20:40:36 2008 +0100 - - Separate omap24xx specific code from arm1136 - - Move omap24xx code to cpu/arm1136/omap24xx, rename include/asm-arm/arch-arm1136 - to cpu/arm1136/omap24xx. - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit 1f1d88dd40815332df32982e739f2ddd2da6fe1a -Author: Mike Frysinger -Date: Tue Jan 29 18:21:05 2008 -0500 - - disable caches before booting an app for Blackfin apps - - It isn't generally save to execute applications outside of U-Boot with caches - enabled due to the way the Blackfin processor handles caches (requires - software assistance). This patch disables caches before booting an ELF or - just booting raw code. The previous discussion on the patch was that we - wanted to use weaks instead, but that proved to not be feasible when multiple - symbols are involved, which puts us back at the ifdef solution. I've - minimized the ugliness by moving the setup step outside of the main function. - - Signed-off-by: Mike Frysinger - -commit e6dfed705efa44ebf00d21bb1588c6ccc8f3ad32 -Author: Wolfgang Denk -Date: Sun Apr 13 10:03:54 2008 -0700 - - ppc: Get rid of unused machine type definitions - - Signed-off-by: Wolfgang Denk - -commit 1aeed8d71acb3290cf2446f316d6ba437e7881c4 -Author: Wolfgang Denk -Date: Sun Apr 13 09:59:26 2008 -0700 - - Coding Style cleanup; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 7754f33c6fb7a2c050388d20bf3847038558bdcf -Author: Larry Johnson -Date: Thu Feb 21 13:58:11 2008 -0500 - - LM73 bug fix for negative temperatures and cleanup - - When the LM73 temperature sensor measures a temperature below 0 C, the - current driver does not perform sign extension, so the result returned is - 512 C too high. This patch fixes the problem, and does general cleanup - of the code. - - Signed-off-by: Larry Johnson - -commit 96ef831f713289afba19da0c8f905e99da2b23e0 -Author: Guennadi Liakhovetski -Date: Thu Apr 3 13:36:02 2008 +0200 - - cfi_flash: Support buffered writes on non-standard Spansion NOR flash - - Some NOR flash chip from Spansion, for example, the s29ws-n MirrorBit - series require different addresses for buffered write commands. Define a - configuration option to support buffered writes on those chips. A more - elegant solution would be to automatically detect those chips by parsing - their CFI records, but that would require introduction of a fixup table - into the cfi_flash driver. - - Signed-off-by: Guennadi Liakhovetski - -commit 3f9c542d3d69b1a10a5e193e779133a0454d1f44 -Author: Lee Nipper -Date: Thu Apr 10 09:35:06 2008 -0500 - - mpc83xx: Update DIMM data bus width test to support 40-bit width - - 32-bit wide ECC memory modules report 40-bit width. - Changed the DIMM data bus width test to 'less than 64' instead of 'equal 32'. - - Signed-off-by: Lee Nipper - Signed-off-by: Kim Phillips - -commit 5fb5a689d822ca61e814bd523fc930af335242fa -Author: Dave Liu -Date: Mon Mar 31 17:05:12 2008 +0800 - - mpc83xx: Fix the bug of serdes initialization - - Currently the serdes will not be initializated due to the - partid's error. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 2000784818f043db7ca60e2846a72d097766b894 -Author: Dave Liu -Date: Thu Apr 3 16:28:29 2008 +0800 - - mpc83xx: Fix the SATA clock setting of 837x targets - - Currently the SATA controller clock is configured as CSB clock, - usually the CSB clock is 400/333/266MHz. - - However, The SATA IP block is only guaranteed to operate up to - 200 MHz as stated in the HW spec. - - The bug is reported by Joe D'Abbraccio - - This patch makes the SATA clock as half of CSB clock. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 1ac4f320bf0b593aa0a741f2d649a8ece8838672 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Wed Apr 2 13:41:21 2008 +0200 - - mpc837xerdb: Fix warning: implicit declaration of function 'fdt_fixup_dr_usb' - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Kim Phillips - -commit 97b3ecb575a92fa34c1765229dbc06f2b662f139 -Author: Kumar Gala -Date: Wed Apr 9 04:20:57 2008 -0500 - - 85xx: Fix detection of MP cpu spin up - - We were looking at the wrong memory offset to determine of a secondary - cpu had been spun up or not. Also added a warning message if the - all the secondary cpus we expect don't spin up. - - Signed-off-by: Kumar Gala - -commit f3e04bdc3f360c66801a9048956e61e41a16edba -Author: Kumar Gala -Date: Tue Apr 8 10:45:50 2008 -0500 - - 85xx: Use SVR_SOC_VER instead of SVR_VER - - The recent change introduced by 'Update SVR numbers to expand support' - now requires that we use SVR_SOC_VER instead of SVR_VER if we want - to compare against a particular processor id. - - Signed-off-by: Kumar Gala - -commit 5b2052e5f5fcce5dbd4d2750a29c0e45bce806e7 -Author: Eugene O'Brien -Date: Fri Apr 11 10:00:35 2008 -0400 - - ppc4xx: Fix power mgt definitions for PPC440 - - Corrected DCR addresses of PPC440EP power management registers. - - Signed-off-by: Eugene O'Brien - -commit 950a392464e616b4590bc4501be46e2d7d162dea -Author: Wolfgang Denk -Date: Fri Apr 11 15:11:26 2008 +0200 - - Revert merge of git://www.denx.de/git/u-boot-arm, commit 62479b18: - - Reverting became necessary after it turned out that the patches in - the u-boot-arm repo were modified, and in some cases corrupted. - - This reverts the following commits: - - 066bebd6353e33af3adefc3404560871699e9961 - 7a837b7310166ae8fc8b8d66d7ef01b60a80f9d6 - c88ae20580b2b01487b4cdcc8b2a113f551aee36 - a147e56f03871bba4f05058d5e04ce7deb010b04 - d6674e0e2a6a1f033945f78838566210d3f28c95 - 8c8463cce44d849e37744749b32d38e1dfb12e50 - c98b47ad24b2d91f41c09a3d62d7f70ad84f4b7d - 8bf69d81782619187933a605f1a95ee1d069478d - 8c16cb0d3b971f46fbe77c072664c0f2dcd4471d - a574a73852a527779234e73e17e7597fd8128882 - 1377b5583a48021d983e1fd565f7d40c89e84d63 - 1704dc20917b4f71e373e2c888497ee666d40380 - - Signed-off-by: Wolfgang Denk - -commit 64e541f4c1b413dd84c7e409f5c2bf328db2ac13 -Author: Stefan Roese -Date: Fri Apr 11 07:02:29 2008 +0200 - - ppc4xx: Update Kilauea defconfig to use device-tree booting as default - - This patch reworks the default environment on Kilauea/Haleakala. Now - "net_nfs" for exmaple uses the device-tree style booting formerly know - as "net_nfs_fdt". Also the addresses in RAM were changed because of the - new image booting support, which check for image overwriting. So the - addresses needed togeet adjusted. - - Signed-off-by: Stefan Roese - -commit 756f5dacda3810b094b94bcceffd3ce6c7ff9a28 -Author: Stefan Roese -Date: Wed Apr 9 11:58:02 2008 +0200 - - ppc4xx: Fix Canyonlands default environment to work with new image support - - Since the new image support checks for image overwriting, the default - environment needs to get adjusted to use correct addresses. - - Signed-off-by: Stefan Roese - -commit dfc6c7b647dba7ab86749616f0e9e5740deed422 -Author: Stefan Roese -Date: Wed Apr 9 11:54:11 2008 +0200 - - ppc: Revert patch 70431e8a that used _start instead of CFG_MONITOR_BASE - - The patch 70431e8a7393b6b793f77957f95b999fc9a269b8 (Make MPC83xx one step - closer to full relocation.) doesn't use CFG_MONITOR_BASE anymore. But - on 4xx systems _start currently cannot be used for this calculation. - So revert back to the original version for now. - - Signed-off-by: Stefan Roese - -commit f91374f65eae8b42cac329e06ba1c54728278efb -Author: Michal Simek -Date: Fri Mar 28 12:49:52 2008 +0100 - - microblaze: Sort microblaze boards in MAKEALL script - -commit 62032deb7214c6d9b4396297e2aaa559bc2f8495 -Author: Michal Simek -Date: Fri Mar 28 11:58:45 2008 +0100 - - microblaze: clean microblaze_config.mk - - FLAGS are generated by U-BOOT generator. - Board specific FLAGS are in board directory - - Signed-off-by: Michal Simek - -commit cf5c679ca04a6b54bf53a55b8b9c29335b387287 -Author: Michal Simek -Date: Fri Mar 28 12:47:19 2008 +0100 - - microblaze: xupv2p fix config file for supporting FDT - -commit 188dc16b189143573b1ed90e584bf866d75cdd12 -Author: Michal Simek -Date: Fri Mar 28 11:53:02 2008 +0100 - - microblaze: ml401 fix config file for supporting FDT - - Signed-off-by: Michal Simek - -commit 4c6a6f02e239236261333759997eeaf86b30b54c -Author: Michal Simek -Date: Fri Mar 28 11:22:48 2008 +0100 - - microblaze: ml401 - add ifdef for GPIO - - Signed-off-by: Michal Simek - -commit af7ae1a411c67ee9d17a66d17ce50b374f3dd4e7 -Author: Michal Simek -Date: Fri Mar 28 12:13:03 2008 +0100 - - microblaze: clean uart16550 and uartlite handling - - Signed-off-by: Michal Simek - -commit 0b20f250877441460fb79d72192954abe8498834 -Author: Michal Simek -Date: Fri Mar 28 11:08:31 2008 +0100 - - microblaze: Add Emaclite driver to Makefile - - Signed-off-by: Michal Simek - -commit 868cde5310f88234b774878e4f06e79df10a88b3 -Author: Michal Simek -Date: Fri Mar 28 11:08:01 2008 +0100 - - microblaze: Add Emac driver to Makefile - - Signed-off-by: Michal Simek - -commit 6f961b4f461f6cbb83a467d468a02e6078c2b327 -Author: Michal Simek -Date: Fri Mar 28 12:42:29 2008 +0100 - - microblaze: add Emac ethernet driver - -commit 89c53891b18cbafd29ab8931b40e27ad231b6085 -Author: Michal Simek -Date: Fri Mar 28 12:41:56 2008 +0100 - - microblaze: add Emaclite ethernet driver - -commit e5845e21224dbe2fe47b11f1cdf95de7f84be7cb -Author: Michal Simek -Date: Fri Mar 28 11:04:01 2008 +0100 - - microblaze: ML401 and XUPV2P remove emac and emaclite reference - - Signed-off-by: Michal Simek - -commit 6bf3e982aefdb1daf9f5462d482c8f9d1cc90a57 -Author: Michal Simek -Date: Fri Mar 28 10:59:32 2008 +0100 - - microblaze: remove old setting for emac driver - - Signed-off-by: Michal Simek - -commit cd2b75efb9cc037c74ecee9b3586f9bf9e1d4e57 -Author: Michal Simek -Date: Fri Mar 28 10:58:15 2008 +0100 - - microblaze: Clean Makefile from ancient emac driver - - Signed-off-by: Michal Simek - -commit ab68f921d9c741830f721c3d879c13a0c5597183 -Author: Daniel Hellstrom -Date: Fri Mar 28 10:20:43 2008 +0100 - - SPARC/LEON2: added support for Gaisler simulator GRSIM/TSIM for SPARC/LEON2 targets. See www.gaisler.com for information. - - Signed-off-by: Daniel Hellstrom - -commit 6ed8a43a19bb0275501bc286007daafa923552cf -Author: Daniel Hellstrom -Date: Wed Mar 26 23:38:48 2008 +0100 - - SPARC/LEON3: added support for GR-CPCI-AX2000 FPGA AX board. The FPGA is exchangeable but a standard LEON3 design is assumed. See www.gaisler.com for information. - - Signed-off-by: Daniel Hellstrom - -commit 6940383d9ec1bfe2f13e339e6f723e8d34af2b12 -Author: Daniel Hellstrom -Date: Wed Mar 26 23:34:47 2008 +0100 - - SPARC/LEON3: added support for Altera NIOS Development kit (STRATIX II Edition) with GRLIB template design. See www.gaisler.com for information. - - Signed-off-by: Daniel Hellstrom - -commit 823edd8a66ed50af5aaba0c79567f67061e4d79a -Author: Daniel Hellstrom -Date: Fri Mar 28 10:06:52 2008 +0100 - - SPARC/LEON3: added support for Gaisler GRSIM/TSIM2 SPARC/LEON3 simulatorn. See www.gaisler.com for information. - - Signed-off-by: Daniel Hellstrom - -commit 71d7e4c0489e5ed8fc69382236aaa2a1e510c135 -Author: Daniel Hellstrom -Date: Wed Mar 26 23:26:48 2008 +0100 - - SPARC/LEON3: added support for GR-XC3S-1500 board with GRLIB template design. See www.gaisler.com for board information. - - Signed-off-by: Daniel Hellstrom - -commit b330990c2f36ee4a8bb318360e1c8ba965269ab6 -Author: Daniel Hellstrom -Date: Fri Mar 28 10:00:33 2008 +0100 - - SPARC: Added support for SPARC LEON2 SOC Processor. - - Signed-off-by: Daniel Hellstrom - -commit 2a2fa797e63b1e3cd4d570318ca5fbf8723ef53a -Author: Daniel Hellstrom -Date: Wed Mar 26 23:00:38 2008 +0100 - - SPARC/LEON3: Added AMBA Bus Plug&Play information print command (ambapp). It can print available cores (type: AHB Master, AHB Slave, APB Slave), their address ranges, IRQ number and version. - - Signed-off-by: Daniel Hellstrom - -commit 1e9a164e22976933002c5e4b0b79b09fcede9cd4 -Author: Daniel Hellstrom -Date: Wed Mar 26 22:51:29 2008 +0100 - - SPARC: Added support for SPARC LEON3 SOC processor. - - Signed-off-by: Daniel Hellstrom - -commit bf3d8b31169546fcddb4737391e1893fb12d033a -Author: Daniel Hellstrom -Date: Fri Mar 28 08:29:26 2008 +0100 - - SPARC: added SPARC support for new uimage in common code. - - Signed-off-by: Daniel Hellstrom - -commit 00ab32c85405a4fe65fd4128243086210fc90a21 -Author: Daniel Hellstrom -Date: Wed Mar 26 22:36:03 2008 +0100 - - SPARC: added SPARC board information to the command bdinfo. - - Signed-off-by: Daniel Hellstrom - -commit c2f02da21a3f37f0878554eebc785e04fdc4e128 -Author: Daniel Hellstrom -Date: Fri Mar 28 09:47:00 2008 +0100 - - SPARC: Added generic support for SPARC architecture. - - Signed-off-by: Daniel Hellstrom - -commit e54ec0f016803e4d9524ff71f7971bda0c51b287 -Author: Stefan Roese -Date: Thu Apr 3 14:50:34 2008 +0200 - - ppc4xx: Fix 4xx enet driver to support 460GT EMAC2+3 - - This patch fixes a problem with the RGMII setup of the 460GT. The 460GT - has 2 RGMII instances and we need to configure the 2nd RGMII instance - for the EMAC2+3 channels. - - Signed-off-by: Stefan Roese - -commit c2a545ce33b26d80337f80b533828839249fb1c9 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Wed Apr 2 08:03:56 2008 +0200 - - MPC8xx: Fix libfdt support introduced in commit 77ff7b74 - - fdt.c: In function 'ft_cpu_setup': - fdt.c:33: warning: implicit declaration of function 'do_fixup_by_prop_u32' - fdt.c:39: warning: implicit declaration of function 'do_fixup_by_compat_u32' - fdt.c:43: warning: implicit declaration of function 'fdt_fixup_ethernet' - fdt.c:45: warning: implicit declaration of function 'fdt_fixup_memory' - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 4abd844d8eb108736e1cf8fbf3dbf61f2d5fc11b -Author: Andy Fleming -Date: Mon Mar 31 20:45:56 2008 -0500 - - Fix fdt set command to conform to dts spec - - The fdt set command was treating properties specified as <00> and <0011> - as byte streams, rather than as an array of cells. As we already have - syntax for expressing the desire for a stream of bytes ([ xx xx ...]), - we should use the <> syntax to describe arrays of cells, which are always - 32-bits per element. If we imagine this likely (IMHO) scenario: - - > fdt set /ethernet-phy@1 reg <1> - - With the old code, this would create a bad fdt, since the reg cell would be - made to be one byte in length. But the cell must be 4 bytes, so this would - break mysteriously. - - Also, the dts spec calls for constants inside the angle brackets (<>) - to conform to C constant standards as they pertain to base. - Take this scenario: - - > fdt set /ethernet@f00 reg <0xe250000\ 0x1000> - - The old fdt command would complain that it couldn't parse that. Or, if you - wanted to specify that a certain clock ran at 33 MHz, you'd be required to - do this: - - > fdt set /mydev clock <1f78a40> - - Whereas the new code will accept decimal numbers. - - While I was in there, I extended the fdt command parser to handle property - strings which are split across multiple arguments: - - > fdt set /ethernet@f00 interrupts < 33 2 34 2 36 2 > - > fdt p /ethernet@f00 - ethernet@f00 { - interrupts = <0x21 0x2 0x22 0x2 0x24 0x2>; - }; - - Lastly, the fdt print code was rearranged slightly to print arrays of cells - if the length of the property is a multiple of 4 bytes, and to not print - leading zeros. - - Signed-off-by: Andy Fleming - -commit 1c2926abdd7db89296a8cc7f224dd9d5d4e37a56 -Author: Stefan Roese -Date: Wed Apr 2 08:39:33 2008 +0200 - - ppc4xx: Canyonlands: Init SATA/PCIe port correctly - - Canyonlands (460EX) shares the first PCIe interface with the SoC SATA - interface. This usage can be configured with the jumper J6. This patch - correctly configures the SATA/PCIe PHY for SATA usage when this jumper - is installed. - - Signed-off-by: Stefan Roese - -commit 6fe2946f198481254a6ee9600d7456b8316a4083 -Author: Kim Phillips -Date: Fri Mar 28 17:37:49 2008 -0500 - - remove remaining CONFIG_OF_HAS_{UBOOT_ENV,BD_T} code - - finish off what commit 43ddd9c820fec44816188f53346b464e20b3142d, - "Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_T" - started. - - Signed-off-by: Kim Phillips - -commit b5873f1732b92a25690e1513b90dfb0d644f6697 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Tue Apr 1 07:30:51 2008 +0200 - - dataflash: Move CONFIG_HAS_DATAFLASH to Makefile - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 2d934ea51f276522b532f870a820e844ff480b5b -Author: Tor Krill -Date: Fri Mar 28 15:29:45 2008 +0100 - - Add Vitesse 8601 support to TSEC driver - - Add phy_info for Vitesse VSC8601. - Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation. - - Signed-off-by: Tor Krill - Reviewed-by: Kim Phillips - Signed-off-by: Ben Warren - -commit 3eac6402a508b0f68a21cc9cbc2cc49347de0c31 -Author: Daniel Hellstrom -Date: Mon Mar 31 14:25:00 2008 +0000 - - SPARC: added SMC91111 driver in and out macros for LEON processors. - - This patch makes SPARC/LEON processors able to read and write - to the SMC91111 chip using the chip external I/O bus of the memory - controller. This patchs defines the standard in and out macros - expected by the SMC9111 driver. - - To access that I/O bus one must set up the memory controller - (MCTRL or FTMCTRL) correctly. It is assumed that the user sets - up this correctly when the other MCTRL parameters are set up. It - can be set up from the board configuration header file. - - Signed-off-by: Daniel Hellstrom - Signed-off-by: Ben Warren - -commit 3ca7c558eba36332556bc470d45e2f5d42bd0ca6 -Author: Stelian Pop -Date: Wed Mar 26 18:52:34 2008 +0100 - - Add maintainership information for AT91CAP9ADK and AT91SAM9260EK boards - - Signed-off-by: Stelian Pop - -commit 4e03dde84dd2c91e327cdc23ae119d432559a7a3 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Mar 31 21:31:04 2008 +0200 - - AT91SAM9260EK: Move CONFIG_CMD_NAND to Makefile - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 0176d43e759a6e00cacc85eff26fd60f74b4f6b7 -Author: Stelian Pop -Date: Wed Mar 26 18:52:33 2008 +0100 - - Add support for AT91SAM9260EK - - Support for booting from internal DataFlash, external DataFlash card - or NAND flash is available. - - Signed-off-by: Stelian Pop - -commit 1762f13b4aab88b685b1722f17dada247945624b -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Mar 31 21:20:49 2008 +0200 - - AT91SAM9: Move CONFIG_HAS_DATAFLASH to Makefile - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 761712188b353494defb2b644491ff73d0daaa6f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Mar 31 21:12:17 2008 +0200 - - AT91CAP9ADK: Move CONFIG_CMD_NAND to Makefile - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 983c1db04c1dd0f92e02f06d29f0c65a3d9a2687 -Author: Stelian Pop -Date: Wed Mar 26 20:52:32 2008 +0100 - - Port AT91CAP9 to the new headers - - Adapt the existing AT91CAP9 code to the new headers and APIs. - - Signed-off-by: Stelian Pop - -commit 177e8a5ac81bbc531a1d54abdb47f2860266c3aa -Author: Stelian Pop -Date: Wed Mar 26 19:52:31 2008 +0100 - - Finish header files reworking - - Replace AT91CAP9.h file with several splitted header files coming - from the Linux kernel. - - This is part 2 of the replacement: more header imports and edits. - - Signed-off-by: Stelian Pop - -commit 6d1dbbbf9fdf727384002e553e615c15d8b967f4 -Author: Stelian Pop -Date: Wed Mar 26 19:52:30 2008 +0100 - - Import several header files from Linux - - Replace AT91CAP9.h file with several splitted header files coming - from the Linux kernel. - - This is part 1 of the replacement: pristine header files import. - - Signed-off-by: Stelian Pop - -commit a8a78f2d99dc1bd30dc3595da118539b506c6118 -Author: Stelian Pop -Date: Wed Mar 26 20:52:28 2008 +0100 - - Move at91cap9 specific files to at91sam9 directory - - AT91CAP9 and AT91SAM9 SoCs are very close hardware wise, so a - common infrastructure can be used. Let this infrastructure be - named after the AT91SAM9 family, and move the existing AT91CAP9 - files to the new place. - - Signed-off-by: Stelian Pop - -commit 61106a565870ff503f92b251b94bd7afef889a04 -Author: Stelian Pop -Date: Wed Mar 26 21:52:27 2008 +0100 - - Use timer_init() instead of board supplied interrupt_init() - - The timer on AT91CAP9/AT91SAM9 is supplied by the SoC, and not by - the board, so use timer_init() instead of interrupt_init(). - - Signed-off-by: Stelian Pop - -commit 5604e2178c5218fbfdba2e4293ca7652e829ac25 -Author: Stelian Pop -Date: Wed Mar 26 21:52:36 2008 +0100 - - Cleanup DataFlash partition handling - - DataFlash partition information has become a mess. This patch - defines a single partition scheme for Atmel DataFlashes. This partition - scheme will be used by all AT91CAP9 and AT91SAM9 boards. - - Signed-off-by: Stelian Pop - -commit 9b46432fc65ce0f0826b32e4f15c15b33ccb8d42 -Author: TsiChung Liew -Date: Fri Mar 28 08:47:45 2008 -0500 - - ColdFire: Fix alignment issue after CONFIG_IDENT_STRING in start.S - - When the version_string function in start.S is not 4-byte align, - it will cause the compiler generates "unaligned opcodes detected - in executable segment". This issue affects all ColdFire CPUs. - By adding .align 4 after CONFIG_IDENT_STRING, it will pad 0's if - it is not aligned. - - Signed-off-by: TsiChung Liew - Acked-by: John Rigby - -commit bae61eefe15b4d454060a7140e49ae58322be803 -Author: TsiChung Liew -Date: Tue Mar 25 15:41:15 2008 -0500 - - ColdFire: Add dspi and serial flash support for MCF5445x - - Signed-off-by: TsiChung Liew - Acked-by: John Rigby - -commit 48ead7a7a922fceaf494e352abfab8216a41b417 -Author: TsiChung Liew -Date: Tue Mar 18 17:37:01 2008 -0500 - - ColdFire: Remove R5200 board - - This board never went into production - - Signed-off-by: Zachary P. Landau - Acked-by: TsiChung Liew - Acked-by: John Rigby - -commit 545c8e0a7cd3ca9d3846668f69b0d201250abea8 -Author: Matthew Fettke <[matthew.fettke@gmail.com]> -Date: Thu Jan 24 14:02:32 2008 -0600 - - ColdFire: Added M5275EVB support. - - Signed-off-by: Matthew Fettke - Signed-off-by: TsiChung Liew - Acked-by: John Rigby - -commit f71d9d91a2cd9c30b2b6369f15c1a46c11537c2b -Author: Matthew Fettke <[matthew.fettke@gmail.com]> -Date: Mon Feb 4 15:38:20 2008 -0600 - - ColdFire: Added MCF5275 cpu support. - - Signed-off-by: Matthew Fettke - Signed-off-by: TsiChung Liew - Acked-by: John Rigby - -commit 44e5b9edab077aba6e9b849afa4b7fbd8fd7b02b -Author: TsiChung Liew -Date: Mon Mar 17 12:14:11 2008 -0500 - - ColdFire: Define bootdelay in configuration file for M52277EVB - - Signed-off-by: Matt Wadel - Acked-by: TsiChung Liew - Acked-by: John Rigby - -commit 77878f16cedee17161ff2336990970fffc6cea35 -Author: TsiChung Liew -Date: Mon Mar 17 12:09:07 2008 -0500 - - ColdFire: Fix second memory Chipselect for M5475EVB - - Signed-off-by: TsiChung Liew - Acked-by: John Rigby - -commit 43d60642395a550956cb21d287c8cfa563913d28 -Author: TsiChung Liew -Date: Thu Mar 13 14:26:32 2008 -0500 - - ColdFire: Update correct FLASHBAR and RAMBAR1 for MCF5282 - - Signed-off-by: TsiChung Liew - Acked-by: John Rigby - -commit eb14ebe813a0cb5d47905228da446a5ad692473b -Author: Larry Johnson -Date: Sun Mar 30 20:33:04 2008 -0500 - - ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setup - - Signed-off-by: Larry Johnson - -commit 02e3892021112f21067d9ed1d04ae4182725ba52 -Author: Stefan Roese -Date: Mon Mar 31 12:20:48 2008 +0200 - - ppc4xx: Small whitespace fix of esd patches - - Signed-off-by: Stefan Roese - -commit 034394abb524785047c815f00dde8cdbdc1593c5 -Author: Matthias Fuchs -Date: Sun Mar 30 18:52:44 2008 +0200 - - ppc4xx: Cleanup PMC440 board support - - Signed-off-by: Matthias Fuchs - -commit a6cc6c37188d85c25d167a4515da86f48d9a583e -Author: Matthias Fuchs -Date: Sun Mar 30 18:52:06 2008 +0200 - - ppc4xx: Add ptm configuration variables for PMC440 - - Add support for the ptm1la, ptm1ms, ptm2la and ptm2ms - environment variables. - - Cleanup pci_target_init. - - Signed-off-by: Matthias Fuchs - -commit 7c91f51a2fe296909147f1646a1412729dd10b1d -Author: Matthias Fuchs -Date: Sun Mar 30 18:01:15 2008 +0200 - - ppc4xx: Minor updates for DU440 boards - - Signed-off-by: Matthias Fuchs - -commit d5bffeb868d6b4d462f558dac43011027b6644b7 -Author: Mike Frysinger -Date: Tue Feb 19 00:54:20 2008 -0500 - - Blackfin: cleanup and overhaul common board init functions - - Signed-off-by: Mike Frysinger - -commit b86b3416f874358acaf07519e7620cdb2145f75b -Author: Mike Frysinger -Date: Tue Feb 19 00:50:58 2008 -0500 - - Blackfin: cleanup lib_blackfin/cache.c - - Signed-off-by: Mike Frysinger - -commit 9171fc81722c20fdb5a829a58b17c9eaadd5fb44 -Author: Mike Frysinger -Date: Sun Mar 30 15:46:13 2008 -0400 - - Blackfin: unify cpu and boot modes - - All of the duplicated code for Blackfin processors and boot modes have been - unified. After all, the core is the same for all processors, just the - peripheral set differs (which gets handled in the drivers). - - Signed-off-by: Mike Frysinger - -commit 880cc4381ea8360248cddcdf87a64566745a5724 -Author: Stelian Pop -Date: Wed Mar 26 22:52:35 2008 +0100 - - Fix CFG_NO_FLASH compilation. - - Many Atmel boards have no "real" (NOR) flash on board, and rely only - on DataFlash and NAND memories. This patch enables CFG_NO_FLASH to - be present in a board configuration file, while still enabling flash - commands like 'flinfo', 'protect', etc. - - Signed-off-by: Stelian Pop - -commit 9ce7e53abd039decea1af67aec81bbd5df7a2593 -Author: Mike Frysinger -Date: Tue Feb 19 00:58:13 2008 -0500 - - Blackfin: BF537-stamp: cleanup spi flash driver - - This punts the old spi flash driver for a new/generalized one until the - common one can be integrated. - - Signed-off-by: Mike Frysinger - -commit bb8e3cf25bc0b04936c0c1a075985dd8700a244b -Author: Ben Warren -Date: Sun Mar 30 11:34:34 2008 -0400 - - Fix macro typo in common/cmd_mii.c - - This typo was introduced in commit 233a8bcd94997f3f345833a3b82e836222f2a206. I - actually applied the wrong patch. - - Signed-off-by: Ben Warren - -commit f1b985f2d724ccaa4d3def07917f0caaf18fa77d -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Mar 30 16:39:53 2008 +0200 - - use correct at91rm9200 register name in m501sk board - - This fixes a naming bug for at91rm9200 lowlevel init code: - NOR boot flash is on chipselect 0, not chipselect 2. This - makes code use the register name from chip datasheets. - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 480ed1dea103a1c8f4591afc77d2de3c7868d983 -Author: David Brownell -Date: Fri Jan 18 12:55:00 2008 -0800 - - use correct at91rm9200 register name - - This fixes a naming bug for at91rm9200 lowlevel init code: - NOR boot flash is on chipselect 0, not chipselect 2. This - makes code use the register name from chip datasheets. - - Signed-off-by: David Brownell - -commit a3543d6dc52b0ba9c64016687cf32d600b31a476 -Author: David Brownell -Date: Fri Jan 18 12:45:45 2008 -0800 - - add missing ARM boards to MAKEALL - - Add some missing ARM boards to MAKEALL. These build correctly, - unlike several of the boards already listed. - - Signed-off-by: David Brownell - -commit 066bebd6353e33af3adefc3404560871699e9961 -Author: Peter Pearse -Date: Sun Mar 30 11:34:09 2008 +0100 - - Bracket READ_TIMER macro in cpu/arm1136/omap24xx/interrupts.c - to prevent compilation error. - - Signed-off-by: Peter Pearse - -commit 7a837b7310166ae8fc8b8d66d7ef01b60a80f9d6 -Author: Guennadi Liakhovetski <[lg@denx.de]> -Date: Sun Mar 30 11:32:30 2008 +0100 - - Support for the MX31ADS evaluation board from Freescale - - This patch adds support for the MX31ADS evaluation board from Freescale, - initialization code is copied from RedBoot sources, also provided by Freescale. - - Signed-off-by: Guennadi Liakhovetski - -commit c88ae20580b2b01487b4cdcc8b2a113f551aee36 -Author: Sascha Hauer -Date: Sun Mar 30 11:32:27 2008 +0100 - - Phytec Phycore-i.MX31 support - - This patch adds support for the Phytec Phycore-i.MX31 board - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit a147e56f03871bba4f05058d5e04ce7deb010b04 -Author: Sascha Hauer -Date: Sun Mar 30 11:32:24 2008 +0100 - - mx31 litekit support - - This patch adds support for the mx31 litekit board - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit d6674e0e2a6a1f033945f78838566210d3f28c95 -Author: Sascha Hauer -Date: Sun Mar 30 11:32:21 2008 +0100 - - add SMSC LAN9x1x Network driver - - This patch adds a driver for the following smsc network controllers: - LAN9115 - LAN9116 - LAN9117 - LAN9215 - LAN9216 - LAN9217 - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit 8c8463cce44d849e37744749b32d38e1dfb12e50 -Author: Sascha Hauer -Date: Sun Mar 30 11:32:16 2008 +0100 - - add an i2c driver for mx31 - - This patch adds an i2c driver for Freescale i.MX processors - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit c98b47ad24b2d91f41c09a3d62d7f70ad84f4b7d -Author: Sascha Hauer -Date: Sun Mar 30 11:30:43 2008 +0100 - - core support for Freescale mx31 - - This patch adds the core support for Freescale mx31 - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit 8bf69d81782619187933a605f1a95ee1d069478d -Author: Sascha Hauer -Date: Sun Mar 30 11:28:46 2008 +0100 - - Separate omap24xx specific code from arm1136 - - Move omap24xx code to cpu/arm1136/omap24xx, rename include/asm-arm/arch-arm1136 to cpu/arm1136/omap24xx. - - Signed-off-by: Sascha Hauer - Signed-off-by: Guennadi Liakhovetski - -commit 8c16cb0d3b971f46fbe77c072664c0f2dcd4471d -Author: Peter Pearse -Date: Sun Mar 30 11:23:05 2008 +0100 - - Add pmdra into MAKEALL - - Signed-off-by: Peter Pearse - -commit a574a73852a527779234e73e17e7597fd8128882 -Author: Pieter Voorthuijsen <[pieter.voorthuijsen@Prodrive.nl]> -Date: Sun Mar 30 11:21:58 2008 +0100 - - Adds support for the Prodrive PMDRA board, based on a DM6441 - - Signed-off-by: Pieter Voorthuijsen - -commit 1377b5583a48021d983e1fd565f7d40c89e84d63 -Author: Pieter Voorthuijsen <[pieter.voorthuijsen@Prodrive.nl]> -Date: Sun Mar 30 11:11:34 2008 +0100 - - Removes all board specific code from the arch. part for DM644x (DaVinci) boards - - Signed-off-by: Pieter Voorthuijsen - -commit 1704dc20917b4f71e373e2c888497ee666d40380 -Author: Dirk Behme -Date: Sun Mar 30 11:09:01 2008 +0100 - - - Remove *_masked() functions as noted by Wolfgang - - Adapt register naming to recent TI spec (sprue26, March 2007) - - Fix reset_timer() handling - - As reported by Pieter [1] the overflow fix introduced a - delay of factor 16 (e.g 2 seconds became 32). While the - overflow fix is basically okay, it missed to divide udelay by - 16, too. Fix this. - [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/38179 - - Remove software division of timer count value (DIV(x) - macro) and do it in hardware (TIM_CLK_DIV). - Many thanks to Troy Kisky - and Pieter Voorthuijsen for - the hints & testing! - - Signed-off-by: Dirk Behme - - Acked-by: Pieter Voorthuijsen - -commit ac3315c26e143c31680750c9c13f027efbcc887e -Author: Andre Schwarz -Date: Thu Mar 6 16:45:44 2008 +0100 - - new PHY @ e1000 - 2nd try - - Add 82541ER device with latest integrated IGP2 PHY. - Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom. - - Signed-off-by: Andre Schwarz - Signed-off-by: Ben Warren - -commit c2b7da552293b50c9c9e46ed71267b02c2de9ea8 -Author: Daniel Hellstrom -Date: Fri Mar 28 20:22:53 2008 +0100 - - SPARC/LEON3: Added GRETH Ethernet 10/100/1000 driver. - - GRETH is an Ethernet 10/100 or 10/100/1000 MAC with out without - a debug link (EDCL). The GRETH core is documented in GRIP.pdf - available at www.gaisler.com. - - If the GRETH has GigaBit support (GBIT, Scatter gather, checksum - offloading etc.) can be determined by a bit in the control register. - The GBIT MAC is supported by operating in GRTEH 10/100 legacy mode. - - Signed-off-by: Daniel Hellstrom - Signed-off-by: Ben Warren - -commit 233a8bcd94997f3f345833a3b82e836222f2a206 -Author: Tsi-Chung Liew -Date: Mon Mar 17 17:08:22 2008 -0500 - - Add CONFIG_MII_INIT in cmd_mii.c - - Provide common configuration in do_mii() to execute mii_init() - for all cpu architectures - - Signed-off-by: TsiChung Liew - Signed-off-by: Ben Warren - -commit f605479de2deb11e834f31dfdb0af107c86aced6 -Author: Tsi-Chung Liew -Date: Mon Mar 17 17:08:16 2008 -0500 - - ColdFire: Fix FEC transmit issue for MCF5275 - - Signed-off-by: TsiChung Liew - Signed-off-by: Ben Warren - -commit d9a2f416d6ac6058cd7845033ae4dc32ef1c0746 -Author: Aras Vaichas -Date: Wed Mar 26 09:43:57 2008 +1100 - - DHCP request fix for Windows Server 2003 - - Added option CONFIG_BOOTP_DHCP_REQUEST_DELAY. This provides an optional - delay before sending "DHCP Request" in net/bootp.c. Required to overcome - interoperability problems with Windows Server 200x DHCP server when U-Boot - client responds too fast for server to handle. - - Signed-off-by: Aras Vaichas - Signed-off-by: Ben Warren - -commit 97bf85d784fbed485e652eb907589ad0d5cb7262 -Author: Daniel Hellstrom -Date: Fri Mar 28 20:40:19 2008 +0100 - - MTD/CFI: flash_read64 is defined a weak function (for SPARC) - - SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address. - SPARC CPUs implement flash_read64 which calls __raw_readq. - - For current SPARC architectures (LEON2 and LEON3) each read from the - FLASH must lead to a cache miss. This is because FLASH can not be set - non-cacheable since program code resides there, and alternatively disabling - cache is poor from performance view, or doing a cache flush between each - read is even poorer. - - Forcing a cache miss on a SPARC is done by a special instruction "lda" - - load alternative space, the alternative space number (ASI) is processor - implementation spcific and can be found by including . - - Signed-off-by: Daniel Hellstrom - -commit 70431e8a7393b6b793f77957f95b999fc9a269b8 -Author: Joakim Tjernlund -Date: Fri Mar 28 15:41:25 2008 +0100 - - Make MPC83xx one step closer to full relocation. - - Remove a few absolute references to CFG_MONITOR_BASE for ppc/mpc83xx - and use GOT relative reference. - - Signed-off-by: Joakim Tjernlund - Signed-off-by: Kim Phillips - -commit 5b2793a3f3de34d439232b05acc8af67a028fd35 -Author: Michael Barkowski -Date: Thu Mar 27 14:34:43 2008 -0400 - - mpc8323erdb: fix EEPROM page size and get MAC from EEPROM - - This patch fixes eeprom page size so that you can now write more than - 64 bytes at a time. - - It also makes the board take MAC addresses, if found, from EEPROM. - - User should place up to 4 addresses at offset 0x7f00, for - eth{,1,2,3}addr. Any unused addresses should be zero. This group of - four six-byte values should have it's CRC at the end. crc32 and - eeprom commands can be used to accomplish this. - - If CRC fails, MAC addresses come from the environment. If CRC - succeeds, the environment is overwritten at startup. - - Signed-off-by: Michael Barkowski - Signed-off-by: Kim Phillips - -commit 8f325cff31f6e745e6540014b131b9a97f61944c -Author: Michael Barkowski -Date: Fri Mar 28 15:15:38 2008 -0400 - - mpc8323erdb: define CONFIG_PCI_SKIP_HOST_BRIDGE - - Commit 55774b512fdf63c0516d441cc5da7c54bbffb7f2 broke the onboard USB - controller on the PCI bus in Linux on the MPC8323ERDB. - - This fixes it by defining CONFIG_PCI_SKIP_HOST_BRIDGE in the board's - config file. - - Signed-off-by: Michael Barkowski - Signed-off-by: Kim Phillips - -commit e5c4ade4db1e16d3e5d4a7887f34e10e516ed3a9 -Author: Kim Phillips -Date: Fri Mar 28 10:19:07 2008 -0500 - - mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) code - - in the spirit of commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6, - 85xx's "Update SVR numbers to expand support", simplify SPRIDR processing - and processor ID display. Add REVID_{MAJ,MIN}OR macros to make - REVID dependent code simpler. Also added PARTID_NO_E and IS_E_PROCESSOR - convenience macros. - - Signed-off-by: Kim Phillips - -commit 81fd52c6c8fd19f0b7856b98217ce37c46c521af -Author: Kim Phillips -Date: Fri Mar 28 10:18:53 2008 -0500 - - mpc83xx: display ddr frequency in board_add_ram_info banner - - Signed-off-by: Kim Phillips - -commit 35cf155c5ec1ceab2849fa5b6aa3d9a3e9e6f482 -Author: Kim Phillips -Date: Fri Mar 28 10:18:40 2008 -0500 - - mpc83xx: unreinvent mem_clk - - delete ddr_clk and use mem_clk instead. Rename other ddr_*_clk to - mem_*_clk for consistency's sake. - - Signed-off-by: Kim Phillips - -commit 730e792926ca3fe4dd1b734a3bf44e55afa6f536 -Author: Kim Phillips -Date: Fri Mar 28 14:31:23 2008 -0500 - - mpc83xx: enable the SATA interface on mpc8315 rdb and mpc837x rdb boards - - Signed-off-by: Kim Phillips - -commit 2eeb3e4fc54ef2f5d574dafd42c6ce93afa30393 -Author: Dave Liu -Date: Wed Mar 26 22:57:19 2008 +0800 - - mpc83xx: enable the SATA interface on mpc837xemds board - - Enable the first two SATA interfaces on MPC837xEMDS board, - The two SATA ports are on LYNX1. (SATA0/1 on J4/5) - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 6f8c85e8d1865730c158d9ef5a06c70c3a10600a -Author: Dave Liu -Date: Wed Mar 26 22:56:36 2008 +0800 - - mpc83xx: initialize serdes for MPC837xEMDS boards - - This patch is stolen from Anton Vorontsov's patch - for mpc837xerdb boards. - - The reference clk and xcorevdd voltage of serdes1/2 - is same between mpc837xemds and mpc837xerdb. - - 8377E: LYNX1- 2 SATA LYNX2- 2 PCIE - 8378E: LYNX1- 2 SGMII LYNX2- 2 PCIE - 8379E: LYNX1- 2 SATA LYNX2- 2 SATA - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit cc8e839abc80887ae832767b5930d40edd6d7eb7 -Author: Stefan Roese -Date: Fri Mar 28 14:09:04 2008 +0100 - - ppc4xx: Canyonlands: Print SATA/PCIe configuration and board revision - - Canyonlands (460EX) shares the first PCIe interface with the SoC SATA - interface. This usage can be configured with the jumper J6. This patch - displays the current configuration upon bootup and changes the PCIe - init loop, to only initialize the availabel PCIe slots. - - Signed-off-by: Stefan Roese - -commit 90447ecbbac8572457b6d8903073ac3f120995ba -Author: Tor Krill -Date: Fri Mar 28 11:29:10 2008 +0100 - - MTD/CFI: Add support for 16bit legacy AMD flash - - Add entry for 512Kx16 AMD flash to jedec_table. - Read out 16bit device id if chipwidth is 16bit. - Fixed coding style after Stefans feedback - - Signed-off-by: Tor Krill - -commit 5e12e75d17c4b15a310a45cd78fe71b7698a8a8e -Author: Stefan Roese -Date: Fri Mar 28 11:02:53 2008 +0100 - - ppc: Small change to CFG_MEM_TOP_HIDE description - - Signed-off-by: Stefan Roese - -commit 280df59a8d62c6e74c281b1cb7e2052df4d6cb00 -Author: Nobuhiro Iwamatsu -Date: Thu Mar 27 15:44:12 2008 +0900 - - sh: Add support stat structure and stat.h - - Signed-off-by: Nobuhiro Iwamatsu - -commit 4be9eb789e72b845d6693cc36b70a0b3529b3f09 -Author: Mark Jonas -Date: Sat Mar 22 19:27:52 2008 +0100 - - sh: Removed warning when compiling drivers/serial/serial_sh.c. - - Signed-off-by: Mark Jonas - Signed-off-by: Nobuhiro Iwamatsu - -commit f309fa38929ffba71230c02330ffa42f4bba6333 -Author: Nobuhiro Iwamatsu -Date: Wed Mar 12 18:02:57 2008 +0900 - - sh: Remove disable_ctrlc function from R7780MP - - Signed-off-by: Nobuhiro Iwamatsu - -commit 6f4b266ff2a4fcc2bff985d6a217852469afddb3 -Author: Nobuhiro Iwamatsu -Date: Wed Mar 12 17:55:15 2008 +0900 - - sh: Add maintainer of R7780MP to MAINTAINER file - - Update MAINTAINER entry for R7780MP. And fix maintainer's name. - - Signed-off-by: Nobuhiro Iwamatsu - -commit f5e2466f7baa887a7df0c536333eea8231333497 -Author: Nobuhiro Iwamatsu -Date: Tue Mar 25 17:11:24 2008 +0900 - - sh: Add support Renesas Solutions R2D plus board - - R2D plus is SH reference board used with SH7751R. - This board has 266Mhz CPU, 64MB SDRAM, Cardbus, CF interface, - one PCI bus, VGA, and two Ethernet controller. - - Signed-off-by: Nobuhiro Iwamatsu - -commit e92c95180bb5bc5fd4051598a9d60beaba48988d -Author: Nobuhiro Iwamatsu -Date: Wed Mar 12 12:15:29 2008 +0900 - - sh: Add support SH4 cache control - - Add support SH4 cache control and flash_cache function - - Signed-off-by: Nobuhiro Iwamatsu - -commit 28e5efde4d925fcb34901d0030d0648de2da7e89 -Author: Nobuhiro Iwamatsu -Date: Mon Mar 24 01:53:01 2008 +0900 - - sh: Add support PCI host driver for SH7751/SH7751R - - Signed-off-by: Nobuhiro Iwamatsu - -commit ab8f4d40d069cd3cbe7563ddfe3e5f03b0c7c721 -Author: Nobuhiro Iwamatsu -Date: Mon Mar 24 02:11:26 2008 +0900 - - sh: Move SuperH PCI driver from cpu/sh4 to drivers/pci - - Signed-off-by: Nobuhiro Iwamatsu - -commit 566933278101c144d75361ea682678a326c1290d -Author: Nobuhiro Iwamatsu -Date: Wed Mar 12 12:10:28 2008 +0900 - - sh: Add support SuperH SH7751/SH7751R - - Signed-off-by: Nobuhiro Iwamatsu - -commit 3313e0e26224fc9a0c445124f3455058c696df84 -Author: Mark Jonas -Date: Mon Mar 10 11:37:10 2008 +0100 - - sh: Added support for SH7720 based board MPR2. - - Signed-off-by: Mark Jonas - Signed-off-by: Nobuhiro Iwamatsu - -commit 3ecff1d70ae93e628fe65b3fe1fc7c9c76cdf99f -Author: Nobuhiro Iwamatsu -Date: Thu Mar 6 14:05:53 2008 +0900 - - sh: Fix receive FIFO level register of SH4A - - Receive FIFO level register is different in SH4A. - Because register is different, cannot occasionally receive data. - - Signed-off-by: Nobuhiro Iwamatsu - -commit c133c1fb0b590662206b0eba70f4478ee0300a9a -Author: Yusuke Goda -Date: Tue Mar 11 12:55:12 2008 +0900 - - sh: Add support Renesas Solutions R7780MP - - Renesas Solutions R7780MP is a reference board on SH7780. - This board has serial, 10/100 base Ethernet deivice, CF slot - and VGA devices. This board can set extension board. - Extension board has 10/100/1000 base Ethernet device, PCI slot, - S-ATA, iDVR slot. - - Signed-off-by: Yusuke Goda - Signed-off-by: Nobuhiro Iwamatsu - -commit 1a2334a4eb6386d7cd35d9de5fa39af2c764ad28 -Author: Yusuke Goda -Date: Wed Mar 5 14:30:02 2008 +0900 - - sh: Add support PCI of SuperH and SH7780 - - This patch add support PCI of SuperH base code and SH7780 specific code. - - Signed-off-by: Yusuke Goda - Signed-off-by: Nobuhiro Iwamatsu - -commit b55523efff2ae11f0b9ae3cc405893c32eb78156 -Author: Yusuke Goda -Date: Wed Mar 5 14:23:26 2008 +0900 - - sh: Add support SH7780 - - SH7780 is CPU of Renesas Technology. - This CPU has - - CPU clock 400MHz - - PCI support - - DDR-SDRAM controller - - etc ... - - Signed-off-by: Yusuke Goda - Signed-off-by: Nobuhiro Iwamatsu - -commit c2042f5952a686c414031309b8f244513bf578f0 -Author: goda.yusuke -Date: Fri Jan 25 20:46:36 2008 +0900 - - sh: Add support Renesas Solutions Migo-R board - - Migo-R is a board based on SH7722 and has may devices. - In this patch, supported SCIF, NOR flash and Ethernet. - - Signed-off-by: Yusuke Goda - Signed-off-by: Nobuhiro Iwamatsu - -commit 74d1e66d22dac91388bc538b2fe19f735edc5b82 -Author: Bartlomiej Sieka -Date: Thu Mar 27 15:06:40 2008 +0100 - - Fix host tool build breakage, take two - - Revert commit 87c8431f and fix build breakage so that the build continues - to work on FC systems. - - Signed-off-by: Bartlomiej Sieka - -commit 7e4a0d25ed18f6437bdf59ebfa49bb0edc2f24e6 -Author: Stefan Roese -Date: Wed Mar 19 09:36:47 2008 +0100 - - ppc4xx: Enable ECC on LWMON5 - - Since all ECC related problems seem to be resolved on LWMON5, this patch - now enables ECC support. - - We have to write the ECC bytes by zeroing and flushing in smaller - steps, since the whole 256MByte takes too long for the external - watchdog. - - Signed-off-by: Stefan Roese - -commit 6433fa202a91a6594dd48f06807ac38ba27fa0bb -Author: Larry Johnson -Date: Mon Mar 17 11:10:35 2008 -0500 - - ppc4xx: Updates to Korat-specific code - - This patch contains updates for changes for the Korat PPC440EPx board. - These changes include: - - (1) Support for "permanent" and "upgradable" copies of U-Boot, as - described in the new "doc/README.korat" file; - - (2) a new memory map for the registers in the board's CPLD; - - (3) a revised format for manufacturer's data in serial EEPROM; and - - (4) changes to track updates to U-Boot for the Sequoia board. - - Signed-off-by: Larry Johnson - -commit f766cdf89b3a2a7634b8c5869f606150e332036c -Author: Markus Brunner -Date: Thu Mar 27 10:46:25 2008 +0100 - - ppc4xx: PPC405EP Set EMAC noise filter bits - - This bug was introduced with commit aee747f19b460a0e9da20ff21e90fdaac1cec359 - which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally - disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set. - - Signed-off-by: Markus Brunner - Signed-off-by: Stefan Roese - -commit f66e2c8b25c04b79e5fb385bc8989c2de7f63991 -Author: Mike Nuss -Date: Wed Feb 20 11:54:20 2008 -0500 - - ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPx - - On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured - after startup to change the speed of the clocks. This patch adds the - option CFG_PLL_RECONFIG. If this option is set to 667, the CPU - initialization code will reconfigure the PLL to run the system with a CPU - frequency of 667MHz and PLB frequency of 166MHz, without the need for an - external EEPROM. - - Signed-off-by: Mike Nuss - Acked-by: Stefan Roese - -commit 87c8431fe24d48121f053fe67cff4ccfe097d4d1 -Author: Haavard Skinnemoen -Date: Thu Mar 27 09:12:40 2008 +0100 - - new-image: Fix host tool build breakage - - Signed-off-by: Haavard Skinnemoen - -commit 6fb4b640562a10daff0dbe537638d511b5b48650 -Author: Stefan Roese -Date: Thu Mar 27 10:24:03 2008 +0100 - - ppc: Set CFG_MEM_TOP_HIDE to 0 if not already defined - - Signed-off-by: Stefan Roese - -commit 9462732a3ec551c11862450902cd8ee1bedea6d9 -Author: Stefan Roese -Date: Wed Mar 19 10:23:43 2008 +0100 - - ppc4xx: Add fdt support to Prodrive alpr - - Since this board will probably be ported to arch/powerpc in the - near future, we add device tree support now. This way we are - "ready" for arch/powerpc from now on. - - Signed-off-by: Stefan Roese - -commit 511e4f9e7f7b6719e4d91d7f0fc89412b13b5150 -Author: Pieter Voorthuijsen -Date: Mon Mar 17 09:27:56 2008 +0100 - - ppc4xx: Enable cache support on the ALPR board - - Signed-off-by: Pieter Voorthuijsen - -commit 14f73ca679f6fdb44cff0b7304d419db41a0ab69 -Author: Stefan Roese -Date: Wed Mar 26 10:14:11 2008 +0100 - - ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched" - - If CFG_MEM_TOP_HIDE is defined in the board config header, this specified - memory area will get subtracted from the top (end) of ram and won't get - "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel - should gets passed the now "corrected" memory size and won't touch it - either. This should work for arch/ppc and arch/powerpc. Only Linux board - ports in arch/powerpc with bootwrapper support, which recalculate the - memory size from the SDRAM controller setup, will have to get fixed - in Linux additionally. - - This patch enables this config option on some PPC440EPx boards as a workaround - for the CHIP 11 errata. Here the description from the AMCC documentation: - - CHIP_11: End of memory range area restricted access. - Category: 3 - - Overview: - The 440EPx DDR controller does not acknowledge any - transaction which is determined to be crossing over the - end-of-memory-range boundary, even if the starting address is - within valid memory space. Any such transaction from any PLB4 - master will result in a PLB time-out on PLB4 bus. - - Impact: - In case of such misaligned bursts, PLB4 masters will not - retrieve any data at all, just the available data up to the - end of memory, especially the 440 CPU. For example, if a CPU - instruction required an operand located in memory within the - last 7 words of memory, the DCU master would burst read 8 - words to update the data cache and cross over the - end-of-memory-range boundary. Such a DCU read would not be - answered by the DDR controller, resulting in a PLB4 time-out - and ultimately in a Machine Check interrupt. The data would - be inaccessible to the CPU. - - Workaround: - Forbid any application to access the last 256 bytes of DDR - memory. For example, make your operating system believe that - the last 256 bytes of DDR memory are absent. AMCC has a patch - that does this, available for Linux. - - This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: - lwmon5, korat, sequoia - - The other remaining 440EPx board were intentionally not included - since it is not clear to me, if they use the end of ram for some - other purpose. This is unclear, since these boards have CONFIG_PRAM - defined and even comments like this: - - PMC440.h: - /* esd expects pram at end of physical memory. - * So no logbuffer at the moment. - */ - - It is strongly recommended to not use the last 256 bytes on those - boards too. Patches from the board maintainers are welcome. - - Signed-off-by: Stefan Roese - -commit c664bf8c3c9bb9e236891f0d8dfda883e86d159b -Author: Stefan Roese -Date: Thu Mar 27 10:09:05 2008 +0100 - - ppc4xx: Fix Canyonlands linker script (remove bogus ASSERT) - - Signed-off-by: Stefan Roese - -commit d56a3ce179688cde61073a3690e21703d68fafd7 -Author: Stefan Roese -Date: Tue Mar 25 17:51:13 2008 +0100 - - ppc4xx: Correctly pass phyiscal FLASH base address into dtb - - The routine ft_board_setup() configures the EBC NOR mappings for the - Linux physmap_of driver. Since on 460EX/GT we remap the FLASH from - 0x4.fc00.0000 to 0x4.cc00.0000 because of the max. 16MByte boot-CS - problem, we need to pass the corrected address here too. - - Signed-off-by: Stefan Roese - -commit 9ad31989de12ce5c67b07c4867ead47465655c4b -Author: Stefan Roese -Date: Wed Mar 19 16:35:12 2008 +0100 - - ppc4xx: Fix compilation warning in 4xx_enet.c - - Signed-off-by: Stefan Roese - -commit 4c9e855734c523900322a7c3cdd9099b4f51b51d -Author: Stefan Roese -Date: Wed Mar 19 16:20:49 2008 +0100 - - ppc4xx: Add AMCC Glacier 406GT eval board support - - This patch adds support for the AMCC Glacier 460GT eval board. - The main difference to the Canyonlands board are listed here: - - - 4 ethernet ports instead of 2 - - no SATA port - - no USB port - - Currently EMAC2+3 are not working. This will be fixed in a later - release. - - Signed-off-by: Stefan Roese - -commit d8bd643141af4710d7f1b69bbab6b760de0af0a1 -Author: Stefan Roese -Date: Thu Mar 27 08:47:26 2008 +0100 - - ppc4xx: Mask 'vec' with 0x1f in uic_interrupt() for bit set/clear - - Signed-off-by: Stefan Roese - -commit b9670dd85be6e0496ef2e231043c23cad9b1d903 -Author: Anatolij Gustschin -Date: Wed Mar 26 21:05:43 2008 +0100 - - Fix out of tree building issue - - Currently U-Boot building in some external directory - doesn't work. This patch tries to fix the problem. - - Signed-off-by: Anatolij Gustschin - -commit d4ee711d8a5c366ee3f857c26b927d12e66614ff -Author: Anatolij Gustschin -Date: Wed Mar 26 18:13:33 2008 +0100 - - README: update documentation (availability, links, etc.) - - Fix typo in README - - Signed-off-by: Anatolij Gustschin - -commit e813eae3bfeba9c0bda9d1bf9fc3d081f790972f -Author: Anatolij Gustschin -Date: Wed Mar 26 17:47:44 2008 +0100 - - Fix compilation error in cmd_usb.c - - This patch fixes compilation error - cmd_usb.c: In function 'do_usb': - cmd_usb.c:552: error: void value not ignored as it ought to be - - Signed-off-by: Anatolij Gustschin - -commit d8c82db482d6b535d12b419d6440b88bf7091c9b -Author: Timur Tabi -Date: Fri Mar 14 17:45:29 2008 -0500 - - Add support for setting the I2C bus speed in fsl_i2c.c - - Add support to the Freescale I2C driver (fsl_i2c.c) for setting and querying - the I2C bus speed. Current 8[356]xx boards define the CFG_I2C_SPEED macro, - but fsl_i2c.c ignores it and uses conservative value when programming the - I2C bus speed. - - Signed-off-by: Timur Tabi - Acked-by: Andy Fleming - -commit d049cc7f71c0d875e8f5099d1ed23666a82b8f8e -Author: Wolfgang Denk -Date: Thu Mar 27 00:03:57 2008 +0100 - - Coding style cleanup, update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit fd0b1fe3c388a77e8fe00cdd930ca317a91198d4 -Author: Dave Liu -Date: Wed Mar 26 22:55:32 2008 +0800 - - drivers: add the support for Freescale SATA controller - - Add the Freescale on-chip SATA controller driver to u-boot, - The SATA controller is used on the 837x and 8315 targets, - The driver can be used to load kernel, fs and dtb. - - The features list: - - 1.5/3 Gbps link speed - - LBA48, LBA28 support - - DMA and FPDMA support - - Two ports support - - Signed-off-by: Dave Liu - -commit bede87f4c87c3ccd868cc60ebf792e0560c6d024 -Author: Dave Liu -Date: Wed Mar 26 22:54:44 2008 +0800 - - ata: add the readme for SATA command line - - Signed-off-by: Dave Liu - -commit cd54081cd479e542fc399b8a40651ff11a1ad849 -Author: Dave Liu -Date: Wed Mar 26 22:53:24 2008 +0800 - - ata: enable the sata initialize on boot up - - Signed-off-by: Dave Liu - -commit 69386383c5c2b323c66495b0b0cef6a9714d83bf -Author: Dave Liu -Date: Wed Mar 26 22:52:36 2008 +0800 - - ata: add the fis struct for SATA - - Signed-off-by: Dave Liu - -commit ffc664e80dfb2e17de0df5ad39e91a02e9c361bc -Author: Dave Liu -Date: Wed Mar 26 22:51:44 2008 +0800 - - ata: add the libata support - - add simple libata support in u-boot - - Signed-off-by: Dave Liu - -commit 8e9bb43429e50df55fa41932cbe65841ff579220 -Author: Dave Liu -Date: Wed Mar 26 22:50:45 2008 +0800 - - ata: make the ata_piix driver using new SATA framework - - original ata_piix driver is using IDE framework, not real - SATA framework. For now, the ata_piix driver is only used - by x86 sc520_cdp board. This patch makes the ata_piix driver - use the new SATA framework, so - - - remove the duplicated command stuff - - remove the CONFIG_CMD_IDE define in the sc520_cdp.h - - add the CONFIG_CMD_SATA define to sc520_cdp.h - - Signed-off-by: Dave Liu - -commit c7057b529c3c3cb9c0ac9060686a4068f1491bbe -Author: Dave Liu -Date: Wed Mar 26 22:49:44 2008 +0800 - - ata: add the support for SATA framework - - - add the SATA framework - - add the SATA command line - - Signed-off-by: Dave Liu - -commit 83c7f470a4ce94f33600f11ae85ce4dcf00aa90c -Author: Dave Liu -Date: Wed Mar 26 22:48:18 2008 +0800 - - ata: merge the header of ata_piix driver - - move the sata.h from include/ to drivers/block/ata_piix.h - - Signed-off-by: Dave Liu - -commit 9eef62804d9695425b24c87b46a61a7fa74afee0 -Author: Dave Liu -Date: Wed Mar 26 22:47:06 2008 +0800 - - ata: merge the ata_piix driver - - move the cmd_sata.c from common/ to drivers/ata_piix.c, - the cmd_sata.c have some part of ata_piix controller drivers. - consolidate the driver to have better framework. - - Signed-off-by: Dave Liu - -commit b9e749e95354f33eb5dc6653c6db7d502adb95fe -Author: Markus Klotzbuecher -Date: Wed Mar 26 18:26:43 2008 +0100 - - USB, Storage: fix a bug introduced in commit - f6b44e0e4d18fe507833a0f76d24a9aa72c123f1 that will cause usb_stor_info - to only print only information on one storage device, but not for - multiple. - - Signed-off-by: Markus Klotzbuecher - -commit 841e5edd1623f3fecb6bffc5c2f938ed7a947360 -Author: Anatolij Gustschin -Date: Wed Mar 26 17:47:44 2008 +0100 - - Fix compilation error in cmd_usb.c - - This patch fixes compilation error - cmd_usb.c: In function 'do_usb': - cmd_usb.c:552: error: void value not ignored as it ought to be - - Signed-off-by: Anatolij Gustschin - Signed-off-by: Markus Klotzbuecher - -commit dd6c910aadf27c822f17b87eae1a9bd0b2e3aa15 -Author: Kumar Gala -Date: Wed Mar 26 08:53:53 2008 -0500 - - 85xx: Add cpu_mp_lmb_reserve helper to reserve boot page - - Provide a board_lmb_reserve helper function to ensure we reserve - the page of memory we are using for the boot page translation code. - - Signed-off-by: Kumar Gala - -commit 79679d80021ab095e639e250ca472fe526da02e2 -Author: Kumar Gala -Date: Wed Mar 26 08:34:25 2008 -0500 - - 85xx: Update multicore boot mechanism to ePAPR v0.81 spec - - The following changes are needed to be inline with ePAPR v0.81: - - * r4, r5 and now always set to 0 on boot release - * r7 is used to pass the size of the initial map area (IMA) - * EPAPR_MAGIC value changed for book-e processors - * changes in the spin table layout - * spin table supports a 64-bit physical release address - - Signed-off-by: Kumar Gala - -commit 25eedb2c1958a13110c7de1fc809b624053cc69c -Author: Jon Loeliger -Date: Wed Mar 19 15:02:07 2008 -0500 - - FSL: Clean up board/freescale/common/Makefile - - Each file that can be built here now follows some - CONFIG_ option so that they are appropriately built - or not, as needed. And CONFIG_ defines were added - to various board config files to make sure that happens. - - The other board/freescale/*/Makefiles no longer need - to reach up and over into ../common to build their - individually needed files any more. - - Boards that are CDS specific were renamed with cds_ prefix. - - Signed-off-by: Jon Loeliger - -commit a5af4b358a7caa9c0aa374d4d894bf762ec37669 -Author: Kumar Gala -Date: Wed Feb 27 22:00:27 2008 -0600 - - 85xx: Fix merge duplication - - ft_fixup_cpu() got duplicated in some merge snafu. Remove the duplicate. - - Signed-off-by: Kumar Gala - -commit 5893b3d0a4084f87a06a5d3dc03db91206818941 -Author: James Yang -Date: Tue Feb 12 16:35:07 2008 -0600 - - 85xx: Expand CCSR space with more DDR controller registers. - - Signed-off-by: James Yang - Signed-off-by: Jon Loeliger - Signed-off-by: Kumar Gala - -commit a3e77fa5359b3f9f59e4e946b46d57a53057cc85 -Author: James Yang -Date: Fri Feb 8 18:05:08 2008 -0600 - - 85xx: Speed up get_ddr_freq() and get_bus_freq() - - get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were - called. However, get_sys_info() recalculates extraneous information when - called each time. Have get_ddr_freq() and get_bus_freq() return memoized - values from global_data instead. - - Signed-off-by: James Yang - Signed-off-by: Kumar Gala - -commit e9ea679918fbc9a53fa2f2a904aac874ea736036 -Author: James Yang -Date: Fri Feb 8 16:46:27 2008 -0600 - - 85xx: Show DDR memory data rate in addition to the memory clock frequency. - - Show the DDR memory data rate in addition to the memory clock - frequency. For DDR/DDR2 memories the memory data rate is 2x the - memory clock. - - Signed-off-by: James Yang - Signed-off-by: Kumar Gala - -commit 591933ca6eabc440e6ed6967233aaf56fce464a3 -Author: James Yang -Date: Fri Feb 8 16:44:53 2008 -0600 - - 85xx: get_tbclk() speed up and rounding fix - - Speed up get_tbclk() by referencing pre-computed bus clock - frequency value from global data instead of sys_info_t. Fix - rounding of result to nearest; previously it was rounding - upwards. - - Signed-off-by: James Yang - Signed-off-by: Kumar Gala - -commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6 -Author: Andy Fleming -Date: Wed Feb 6 01:19:40 2008 -0600 - - Update SVR numbers to expand support - - FSL has taken to using SVR[16:23] as an SOC sub-version field. This - is used to distinguish certain variants within an SOC family. To - account for this, we add the SVR_SOC_VER() macro, and update the SVR_* - constants to reflect the larger value. We also add SVR numbers for all - of the current variants. Finally, to make things neater, rather than - use an enormous switch statement to print out the CPU type, we create - and array of SVR/name pairs (using a macro), and print out the CPU name - that matches the SVR SOC version. - - Signed-off-by: Andy Fleming - -commit b83eef440cf3cef816172ccbb5897ccd8e403cf3 -Author: Andy Fleming -Date: Wed Feb 6 01:12:57 2008 -0600 - - Add the Freescale PCI device IDs - - Signed-off-by: Andy Fleming - -commit 7aff0c051ad0613171cf2b9941ee48675c62e7cd -Author: Kumar Gala -Date: Thu Feb 14 11:04:23 2008 -0600 - - 85xx: Added support for multicore boot mechanism - - Added the cpu command that provides a generic mechanism to get status, - reset, and release secondary cores in multicore processors. - - Added support for using the ePAPR defined spin-table mechanism on 85xx. - - Signed-off-by: Kumar Gala - Signed-off-by: Andy Fleming - -commit ec2b74ffd36f02c6123725e7c2533dd2deaf4b64 -Author: Kumar Gala -Date: Thu Jan 17 16:48:33 2008 -0600 - - 85xx: Added support for multicore boot mechanism - - Added the cpu command that provides a generic mechanism to get status, - reset, and release secondary cores in multicore processors. - - Added support for using the ePAPR defined spin-table mechanism on 85xx. - - Signed-off-by: Kumar Gala - -commit f69766e4b5d47ecd3aa58677a8da875694f364f2 -Author: Kumar Gala -Date: Wed Jan 30 14:55:14 2008 -0600 - - 85xx: Add the concept of CFG_CCSRBAR_PHYS - - When we go to 36-bit physical addresses we need to keep the concept of - the physical CCSRBAR address seperate from the virtual one. - - For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR - - Signed-off-by: Kumar Gala - -commit 5b5eb9ca5b778f763bcf332697b35cc1e747626e -Author: Wolfgang Denk -Date: Wed Mar 26 15:38:47 2008 +0100 - - Coding style cleanup. - - Signed-off-by: Wolfgang Denk - -commit da8808df7a9cef5a3d2ee286ef9ebf9de1780660 -Author: Joakim Tjernlund -Date: Wed Mar 26 13:02:13 2008 +0100 - - Add CFG_RTC_DS1337_NOOSC to turn off OSC output - - The default settings for RTC DS1337 keeps the OSC - output, 32,768 Hz, on. This add CFG_RTC_DS1337_NOOSC to - turn it off. - - Signed-off-by: Joakim Tjernlund - -commit 438a4c11260b4ea9805039b0b4f92f9df5306b02 -Author: Wolfgang Denk -Date: Wed Mar 26 11:48:46 2008 +0100 - - Cleanup coding style, update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 218ca724c08ca8a649f0917cf201cf23d4b33f39 -Author: Wolfgang Denk -Date: Wed Mar 26 10:40:12 2008 +0100 - - README: update documentation (availability, links, etc.) - - Signed-off-by: Wolfgang Denk - -commit f6b44e0e4d18fe507833a0f76d24a9aa72c123f1 -Author: Aras Vaichas -Date: Tue Mar 25 12:09:07 2008 +1100 - - USB Storage, add meaningful return value - - This patch changes the "usb storage" command to return success if it - finds a USB storage device, otherwise it returns error. - - Signed-off-by: Markus Klotzbuecher - -commit 18e69a35efbb078403db0c0063986470dad7d082 -Author: Anton Vorontsov -Date: Fri Mar 14 23:20:18 2008 +0300 - - 83xx/fdt_support: let user specifiy FSL USB Dual-Role controller role - - Linux understands "host" (default), "peripheral" and "otg" (broken). - Though, U-Boot doesn't restrict dr_mode variable to these values (think - of renames in future). - - Signed-off-by: Anton Vorontsov - Signed-off-by: Kim Phillips - -commit c7604783b236e368f225efb7b3efb418fe20b404 -Author: Anton Vorontsov -Date: Fri Mar 14 23:20:30 2008 +0300 - - tsec: fix link detection for the RTL8211B PHY - - RTL8211B sets link state register after autonegotiation complete, - so with bootdelay=0 RTL8211B will report lack of the link. - - To fix this, we should wait for aneg to complete, even if the - link is currently down. - - Signed-off-by: Anton Vorontsov - Signed-off-by: Kim Phillips - -commit 7fa9cbb00dc83fcf175042b6f20c2c9bce9a15f4 -Author: Anton Vorontsov -Date: Mon Mar 24 20:47:09 2008 +0300 - - mpc83xx: add "fsl,soc" and "fsl,immr" compatible fixups - - device_type = "soc" is being deprecated, newer device trees will use - "fsl,soc" and/or "fsl,immr" for the soc nodes. - - This patch also adds clock-frequency property for soc nodes (the same - value as bus-frequency). - - Signed-off-by: Anton Vorontsov - -commit 507e2d79c91441a0bb2cd3d0c31c8bfe3f8cec07 -Author: Joe D'Abbraccio -Date: Mon Mar 24 13:00:59 2008 -0400 - - Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock - - With the original value of 1/2 clock cycle delay, the system ran relatively - stable except when we run benchmarks that are intensive users of memory. - When I run samba connected disk with a HDBENCH test, the system locks-up - or reboots sporadically. - - Signed-off by: Joe D'Abbraccio - -commit a7ba32d480a86db5db8dcd8ca66b21b4cadda923 -Author: Scott Wood -Date: Mon Mar 24 12:44:13 2008 -0500 - - mpc83xx: Set PCI I/O bus-address base to zero. - - The device trees for these boards describe PCI I/O as starting from - address zero from the device's perspective. - - Placing I/O elsewhere may cause problems with certain PCI boards, and may - cause problems with Linux. - - Signed-off-by: Scott Wood - -commit f700e7df7fecf2d3765ae568ce77ce788cde4f3e -Author: Anton Vorontsov -Date: Mon Mar 24 20:47:05 2008 +0300 - - mpc83xx: MPC8360E-RDK: use 33.3(3)MHz CLKIN/SYS_CLK - - At least on the "33MHz Pilot" board crystal is actually 33.3MHz. - This patch fixes "system time drifting" problem. - - Signed-off-by: Anton Vorontsov - -commit 3a0cfdd576dc9b16d1468d37339182607c697fb7 -Author: Anton Vorontsov -Date: Mon Mar 24 20:47:02 2008 +0300 - - mpc83xx: MPC8360E-RDK: define CONFIG_OF_STDOUT_VIA_ALIAS - - This is needed to update /choosen/linux,stdout-path properly. - - Signed-off-by: Anton Vorontsov - -commit 3419eb62f088d7a22f1d2a3cebf76b77e408b5b9 -Author: Anton Vorontsov -Date: Mon Mar 24 20:47:00 2008 +0300 - - mpc83xx: MPC8360E-RDK: add dhcp command - - Plus modify environment to use it and remove bootfile env variable, - it is internal and CONFIG_BOOTFILE is used for these purposes. - - Signed-off-by: Anton Vorontsov - -commit d892b2dbb4087a26778bfd42470c3ea7d0e2b6aa -Author: Anton Vorontsov -Date: Mon Mar 24 20:46:57 2008 +0300 - - mpc83xx: MPC8360E-RDK: rework ddr setup, enable ecc - - Current DDR setup easily causes memory corruption, this patch fixes it. - - Also fix TIMING_CFG0_MRS_CYC definition. - - Signed-off-by: Anton Vorontsov - -commit d47d49cc37a38f2719a3e1b9bbe08ac810cf2d9a -Author: Anton Vorontsov -Date: Mon Mar 24 20:46:53 2008 +0300 - - mpc83xx: MPC8360E-RDK: configure pario pins for AD7843 and FHCI - - This patch adds qe pario pins configuration for AD7843 ADC/Touchscreen - controller and FHCI (QE USB). - - Signed-off-by: Anton Vorontsov - -commit 7ad959490962e6842648d87d4bd795ea6cdcce67 -Author: Anton Vorontsov -Date: Mon Mar 24 20:46:51 2008 +0300 - - mpc83xx: MPC8360E-RDK: add support for NAND - - Signed-off-by: Anton Vorontsov - -commit 9a3e832aeb491861d029991241572ebdf4b5b61b -Author: Anton Vorontsov -Date: Mon Mar 24 20:46:46 2008 +0300 - - mpc83xx: MPC8360E-RDK: use RGMII_RXID interface mode - - This is needed for BCM PHYs to work on this board. - - Signed-off-by: Anton Vorontsov - -commit 300615dc5d9b0a2022fbc6af0c13159e33fd752e -Author: Anton Vorontsov -Date: Mon Mar 24 20:46:34 2008 +0300 - - uec: add support for Broadcom BCM5481 Gigabit PHY - - This patch adds basic support for Broadcom BCM5481 PHY. - - RXD-RXC delay quirk comes from MPC8360E-RDK BSP source, author is - Peter Barada . - - Signed-off-by: Anton Vorontsov - -commit 6a600c3a1876bc203445df4f0fd6b12648259666 -Author: Anton Vorontsov -Date: Mon Mar 24 20:46:28 2008 +0300 - - uec: add support for RGMII_RXID interface mode - - PHY drivers will use it to setup software delay between RXD and RXC - signals. - - Signed-off-by: Anton Vorontsov - -commit 91cdaa3a9d7562b869d96774e9c9ddf142c0848d -Author: Anton Vorontsov -Date: Mon Mar 24 20:46:24 2008 +0300 - - uec: add support for gbit mii status readings - - Signed-off-by: Anton Vorontsov - -commit aabce7fb505ffe55ebf3bf4dcafdae97a581558d -Author: Anton Vorontsov -Date: Mon Mar 24 17:40:47 2008 +0300 - - 83xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boards - - This is primarily for the early console support. - - Signed-off-by: Anton Vorontsov - -commit 2bd7460e9283ec98565189b3cdbcfb2bcdcdd635 -Author: Anton Vorontsov -Date: Mon Mar 24 17:40:43 2008 +0300 - - 83xx: initialize serdes for MPC837XRDB boards - - On the MPC8377ERDB: 2 SATA and 2 PCI-E. - On the MPC8378ERDB: 2 PCI-E - On the MPC8379ERDB: 4 SATA - - Signed-off-by: Anton Vorontsov - -commit 453316a2a19642d8afcbca7452e40a6b44a197b1 -Author: Anton Vorontsov -Date: Mon Mar 24 17:40:32 2008 +0300 - - 83xx: serdes setup routines - - This patch adds few routines to configure serdes on 837x targets. - - Signed-off-by: Anton Vorontsov - -commit a796cdf9c377cb4e5d61d1079a296608f8fbd903 -Author: Anton Vorontsov -Date: Mon Mar 24 17:40:27 2008 +0300 - - 83xx: split COBJS onto separate lines - - ..plus get rid of some #ifdefs in the .c files. - - Signed-off-by: Anton Vorontsov - -commit 46a3aeea73c13ab04ebf7a8739afb87ac5da94a3 -Author: Anton Vorontsov -Date: Mon Mar 24 17:40:23 2008 +0300 - - 83xx: nand support for MPC837XRDB boards - - Signed-off-by: Anton Vorontsov - -commit 82e45a204190593e8613145a928f998fb8c909c4 -Author: Jerry Van Baren -Date: Tue Mar 18 21:44:41 2008 -0400 - - Enable CONFIG_FLASH_SHOW_PROGRESS on the MPC8360EMDS. - - Signed-off-by: Gerald Van Baren - Signed-off-by: Kim Phillips - -commit 0fa7a1b4719e325fce332689fb8754ec166191ff -Author: Michael Barkowski -Date: Thu Mar 20 13:15:39 2008 -0400 - - mpc8323erdb: remove RTC and add EEPROM - - There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM. - - Signed-off-by: Michael Barkowski - Acked-by: Kim Phillips - -commit 5bbeea86eb6afb872374cd23217cb3c1018443ed -Author: Michael Barkowski -Date: Thu Mar 20 13:15:34 2008 -0400 - - mpc8323erdb: Improve the system performance - - The following changes are based on kernel UCC ethernet performance: - - 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode - 2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT - switch to enable this setting. - - The following changes are based on the App Note AN3369 and - verified to improve memory latency using LMbench: - - 3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0 - 4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting - previously. - 5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on - Twr=15ns, and this was already the setting in DDR_MODE) - 6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on - Trp=15ns) - 7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on - Tras=40ns) - 8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on - Trcd=15ns) - 9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on - Trfc=75ns) - 10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based - on Tfaw=50ns) - 11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based - on CL=3 and WL=2). - - Signed-off-by: Michael Barkowski - Acked-by: Kim Phillips - -commit fc549c871f43933396a5b3e21d897023d4b31b8d -Author: Michael Barkowski -Date: Thu Mar 20 13:15:28 2008 -0400 - - mpc8323erdb: use readable DDR config macros - - Use available shift/mask macros to define DDR configuration. - - Signed-off-by: Michael Barkowski - Acked-by: Kim Phillips - -commit 89c7784ed90ba50301eec521144f95111e472906 -Author: Timur Tabi -Date: Fri Feb 8 13:15:55 2008 -0600 - - 83xx: Add Vitesse VSC7385 firmware uploading - - Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload - the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET. - Cleaned up the board header files to make selecting the VSC7385 easier to - control. - - Signed-off-by: Timur Tabi - Signed-off-by: Kim Phillips - -commit b55d98c6d5b8694e560a0e727b14cb6921d7cfcc -Author: Timur Tabi -Date: Fri Feb 8 13:15:54 2008 -0600 - - NET: Add Vitesse VSC7385 firmware uploading - - The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX - and other boards. A small firwmare must be uploaded to its on-board memory - before it can be enabled. This patch adds the code which uploads firmware - (but not the firmware itself). - - Previously, this feature was provided by a U-Boot application that was - made available only on Freescale BSPs. The VSC7385 firmware must still - be obtained separately, but at least there is no longer a need for a separate - application. - - Signed-off-by: Timur Tabi - Acked-by: Ben Warren - -commit aa6f6d171a1f9f46ee4f03ad6acb97a6bfb71855 -Author: Wolfgang Denk -Date: Wed Mar 26 00:52:10 2008 +0100 - - Coding Style cleanyp; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 43ddd9c820fec44816188f53346b464e20b3142d -Author: Jerry Van Baren -Date: Sat Mar 22 14:23:49 2008 -0400 - - Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_T - - These defines embedded the u-boot env variables and/or the bd_t structure - in the fdt blob. The conclusion of discussion on the u-boot email list - was that embedding these in the fdt blob is not useful: there are better - ways of passing the data (in fact, the fdt blob itself replaces the - bd_t struct). - - The only board that enables these is the stxxtc and they don't appear - to be used by linux. - - Signed-off-by: Gerald Van Baren - Acked-by: Kim Phillips - -commit 22ed2285743359fd1fe73e411dff914b2256e68f -Author: Stefan Roese -Date: Mon Mar 17 10:49:25 2008 +0100 - - rtc: Remove 2nd reference to max6900.o in drivers/rtc/Makefile - - Signed-off-by: Stefan Roese - -commit 1bb707c39a0833e91d9f797dd862aaaaf4af264d -Author: Kyungmin Park -Date: Mon Mar 17 08:54:06 2008 +0900 - - Add Flex-OneNAND booting support - - Flex-OneNAND is a monolithic integrated circuit with a NAND Flash array - using a NOR Flash interface. This on-chip integration enables system designers - to reduce external system logic and use high-density NAND Flash - in applications that would otherwise have to use more NOR components. - - Flex-OneNAND enables users to configure to partition it into SLC and MLC areas - in more flexible way. While MLC area of Flex-OneNAND can be used to store data - that require low reliability and high density, SLC area of Flex-OneNAND - to store data that need high reliability and high performance. Flex-OneNAND - can let users take advantage of storing these two different types of data - into one chip, which is making Flex-OneNAND more cost- and space-effective. - - Signed-off-by: Kyungmin Park - -commit c512389cc4a10253249271ff6c887c6dab1f0db2 -Author: André Schwarz -Date: Thu Mar 13 13:50:52 2008 +0100 - - MPC5200: support setup without FEC - - Include FEC specific nodes in ft_cpu_setup only if CONFIG_MPC5xxx_FEC is - defined. Systems without FEC, i.e. no FEC node in DTB, should be possible. - - Signed-off-by: Andre Schwarz - Acked-by: Grant Likely - -commit aa3511e422946041ef626f80a05ae5e8bfc700e6 -Author: Jon Loeliger -Date: Wed Mar 5 18:05:46 2008 -0600 - - FSL: Move board/mpc8266ads under board/freescale - - Signed-off-by: Jon Loeliger - -commit 7f1d846e5c5754449c286587d099d85246062772 -Author: Jon Loeliger -Date: Wed Mar 5 18:05:47 2008 -0600 - - FSL: Move board/mpc7448hpc2 under board/freescale - - Signed-off-by: Jon Loeliger - -commit b7e24d283e34727c2a6cdfdac2e09a426c579b73 -Author: Jon Loeliger -Date: Wed Mar 5 18:05:45 2008 -0600 - - FSL: Move board/mpc8260ads under board/freescale - - Signed-off-by: Jon Loeliger - -commit 6a8a5dc4759867c45aa95580deb8bf26669a5d97 -Author: goda.yusuke -Date: Wed Mar 5 17:08:33 2008 +0900 - - net: Add support AX88796L ethernet device - - AX88796L is device of NE2000 compatible. - This patch support AX88796L ethernet device. - - Signed-off-by: Yusuke Goda - Acked-by: Nobuhiro Iwamatsu - -commit e0a6140dd381e1eed1ada2291166ef2616d8822b -Author: Wolfgang Denk -Date: Tue Mar 25 22:50:41 2008 +0100 - - ne2000 driver: change #ifdef to Makefile conditional compilation - - Signed-off-by: Wolfgang Denk - -commit e710185aae90c64d39c2d453e40e58ceefe4f250 -Author: goda.yusuke -Date: Wed Mar 5 17:08:20 2008 +0900 - - net: Divided code of NE2000 ethernet driver - - There are more devices of the NE2000 base. - A present code is difficult for us to support more devices. - To support more NE2000 clone devices, separated the function. - - Signed-off-by: Yusuke Goda - Acked-by: Nobuhiro Iwamatsu - -commit 395bce4f59a507a60a475f7ee46bed47de9482df -Author: Mike Frysinger -Date: Sun Feb 24 23:58:13 2008 -0500 - - net/Blackfin: move on-chip MAC driver into drivers/net/ - - The Blackfin on-chip MAC driver was being managed in the BF537-STAMP board - directory, but it is not board specific, so relocate it to the drivers dir - so that other Blackfin ports can utilize it. - - Signed-off-by: Mike Frysinger - -commit 8a30b4700942f37495d2e67f5998cdffb6e3ba8a -Author: Mike Frysinger -Date: Sun Feb 24 23:52:35 2008 -0500 - - smc91111: use SSYNC() rather than asm(ssync) for Blackfin - - Since the "ssync" instruction may have hardware anomalies associated with - it, have the smc91111 driver use the SSYNC macro rather than invoking it - directly. We workaround all the anomalies via this macro. - - Signed-off-by: Mike Frysinger - -commit 77ff7b7444ceb8022b46114f3d0b6d18e2fd1138 -Author: Bryan O'Donoghue -Date: Sun Feb 17 22:57:47 2008 +0000 - - 8xx: Update OF support on 8xx - - This patch does some shifting around of OF support on 8xx. - - Signed-off-by: Bryan O'Donoghue - -commit 9c666a7db0b2285a270c68810889ce7d5dba304b -Author: Kumar Gala -Date: Fri Feb 15 15:16:18 2008 -0600 - - ppc: Allow boards to specify how much memory they can map - - For historical reasons we limited the stack to 256M because some boards - could only map that much via BATS. However newer boards are capable of - mapping more memory (for example 85xx is capble of doing up to 2G). - - Signed-off-by: Kumar Gala - -commit a6f5f317cd074bbbfa2aab4fca05904c811c19fb -Author: Bryan O'Donoghue -Date: Fri Feb 15 01:05:58 2008 +0000 - - 8xx : Add OF support to Adder875 board port - resubmit - - Signed-off-by: Bryan O'Donoghue - -commit d058698fd2d9f769ff38ac53c8708b3fdd314f2d -Author: Kumar Gala -Date: Thu Feb 14 20:44:42 2008 -0600 - - Add setexpr command - - Add a simple expr style command that will set an env variable as the result - of the command. This allows us to do simple math in shell. The following - operations are supported: &, |, ^, +, -, *, /. - - Signed-off-by: Kumar Gala - -commit 3f105faa64b9826e088711fdfcaa70cb1230397a -Author: Jon Loeliger -Date: Wed Mar 5 17:27:48 2008 -0600 - - FSL: Move board/mpc7448hpc2 under board/freescale - - Signed-off-by: Jon Loeliger - -commit 449c703374a8868453425e15da7e2f76221b72e4 -Author: Jon Loeliger -Date: Wed Mar 5 17:21:43 2008 -0600 - - FSL: Move board/mpc8266ads under board/freescale - - Signed-off-by: Jon Loeliger - -commit 5863577989ad689427bb750107e9a75f1c1645d2 -Author: Jon Loeliger -Date: Wed Mar 5 16:41:41 2008 -0600 - - FSL: Move board/mpc8260ads under board/freescale - - Signed-off-by: Jon Loeliger - -commit 8a773983957ee6c4aa344469b742f29c7d26afbd -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:08 2008 +0900 - - [MIPS] Move gth2_config from ARM section to MIPS - - Signed-off-by: Shinya Kuribayashi - -commit 373b16fc0c5ae34d28b9027f809ae3cbf45cdd15 -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:07 2008 +0900 - - [MIPS] Extend MIPS_MAX_CACHE_SIZE upto 64kB - - Signed-off-by: Shinya Kuribayashi - -commit d98e348e2ed5aab8f7a6471ff628ab0688b8a459 -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:07 2008 +0900 - - [MIPS] Fix dcache_status() - - You can't judge UNCACHED by Config.K0 LSB. - - Signed-off-by: Shinya Kuribayashi - -commit b0c66af53ec9385ac2d1cc2e5d7d1ecdc81caf34 -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:07 2008 +0900 - - [MIPS] Introduce _machine_restart - - Handles machine specific functions by using weak functions. - - Signed-off-by: Shinya Kuribayashi - -commit decaba6f5cf386d569ac3997bebb871b966c6b18 -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:07 2008 +0900 - - [MIPS] Cleanup CP0 Status initialization - - Add setup_c0_status from Linux. For the moment we disable interrupts, set - CU0, mark the kernel mode, and clear ERL and EXL. This is good enough for - reset-time configuration and will work well across most processors. - - Signed-off-by: Shinya Kuribayashi - -commit d43d43ef2845af309c25a64bb9c2c5fb3261bc23 -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:07 2008 +0900 - - [MIPS] Initialize CP0 Cause before setting up CP0 Status register - - Without this change, we'll be suffering from deffered WATCH exception - once Status.EXL is cleared. Make sure Cause.WP is cleared. - - Signed-off-by: Shinya Kuribayashi - -commit 26138623230ca2bad3c78e05a65527ea70c8b688 -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:07 2008 +0900 - - [MIPS] INCA-IP: Move watchdog init code from start.S to lowlevel_init() - - Move things to appropriate place. - - Signed-off-by: Shinya Kuribayashi - -commit ccf8f824ef67df028dedb29f8ea5d71a5a88d895 -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:06 2008 +0900 - - [MIPS] Implement flush_cache() - - We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you - don't need to do Hit_Invalidate_I, but flush_cache() needs it since this - function is used not only in U-Boot specfic programs but also at loading - target binaries. - - Signed-off-by: Shinya Kuribayashi - -commit 2e0e5271aac917812a76c72030a2b2c6f1d3387d -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:06 2008 +0900 - - [MIPS] Fix I-/D-cache initialization loops - - Currently we do 1) Index_Store_Tag_I, 2) Fill and 3) Index_Store_Tag_I - again per a loop for I-cache initialization. But according to 'See MIPS - Run', we're encouraged to use three separate loops rather than combining - them *for both I- and D-cache*. This patch tries to fix this. - - In accordance with fixing above, mips_init_[id]cache are separated from - mips_cache_reset(), and rewrite cache loops are completely rewritten with - useful macros. - - Signed-off-by: Shinya Kuribayashi - -commit 1898840797c7f50799377bd5b285a8a93a82c419 -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:06 2008 +0900 - - [MIPS] Replace memory clearance code with f_fill64 - - This routine fills memory with zero by 64 bytes, and is 64-bit capable. - - Signed-off-by: Shinya Kuribayashi - -commit 2f5d414ccb4024dd0992ff6b22561732dbc73590 -Author: Shinya Kuribayashi -Date: Tue Mar 25 21:30:06 2008 +0900 - - [MIPS] cpu/mips/cache.S: Introduce NESTED/LEAF/END macros - - This patch replaces the current function definitions with NESTED, LEAF - and END macro. They specify some more additional information about the - function; an alignment of symbol, type of symbol, stack frame usage, etc. - These information explicitly tells the assembler and the debugger about - the types of code we want to generate. - - Signed-off-by: Shinya Kuribayashi - -commit 282223a607c611425fa33f5428f8eae6636972bb -Author: Shinya Kuribayashi -Date: Tue Mar 25 11:43:17 2008 +0900 - - [MIPS] asm headers' updates - - Make some asm headers adjusted to the latest Linux kernel. - - Signed-off-by: Shinya Kuribayashi - -commit e1390801a3c1a2b6d12fa90be368efc19f5b9bfd -Author: Shinya Kuribayashi -Date: Tue Mar 25 11:39:29 2008 +0900 - - [MIPS] Request for the 'mips_cache_lock()' removal - - The initial intension of having mips_cache_lock() was to use the cache - as memory for temporary stack use so that a C environment can be set up - as early as possible. - - But now mips_cache_lock() follow lowlevel_init(). We've already have the - real memory initilaized at this point, therefore we could/should use it. - No reason to lock at all. - - Other problems: - - Cache locking is not consistent across MIPS implementaions. Some imple- - mentations don't support locking at all. The style of locking varies - - some support per line locking, others per way, etc. Some parts use bits - in status registers instead of cache ops. Current mips_cache_lock() is - not necessarily general-purpose. - - And this is worthy of special mention; once U-Boot/MIPS locks the lines, - they are never get unlocked, so the code relies on whatever gets loaded - after U-Boot to re-initialize the cache and clear the locks. We're sup- - posed to have CFG_INIT_RAM_LOCK and unlock_ram_in_cache() implemented, - but leave the situation as it is for a long time. - - For these reasons, I proposed the removal of mips_cache_lock() from the - global start-up code. - - This patch adds CFG_INIT_RAM_LOCK_MIPS to make existing users aware that - *things have changed*. If he wants the same behavior as before, he needs - to have CFG_INIT_RAM_LOCK_MIPS in his config file. - - If we don't have any regression report through several releases, then - we'll remove codes entirely. - - Signed-off-by: Shinya Kuribayashi - Acked-by: Andrew Dyer - -commit 0d48926c87ec96f974a6ac4034f4a2f2eab3255f -Author: Yuri Tikhonov -Date: Mon Mar 24 11:30:54 2008 +0100 - - lwmon5 SYSMON POST: fix backlight control - - If the LWMON5 config has SYSMON POST among CONFIG_POSTs which may be - run on the board, then the SYSMON POST controls the display backlight - (doesn't switch backlight ON if POST FAILED, and does switch the - backlight ON if PASSED). - - If not, then the video driver controls the display backlight (just - switch ON the backlight upon initialization). - - Signed-off-by: Yuri Tikhonov - -commit ff2bdfb2c1e073f65c065011f1e18d0a130bd3d8 -Author: Yuri Tikhonov -Date: Mon Mar 24 11:29:14 2008 +0100 - - lwmon5 SYSMON POST: fix handling of negative temperatures - - Fix errors in the LWMON5 Sysmon POST for negative temperatures. - - Signed-off-by: Yuri Tikhonov - -commit 55774b512fdf63c0516d441cc5da7c54bbffb7f2 -Author: Nobuhiro Iwamatsu -Date: Fri Mar 7 16:04:25 2008 +0900 - - pci: Add CONFIG_PCI_SKIP_HOST_BRIDGE config option - - In current source code, when the device number of PCI is 0, process PCI - bridge without fail. However, when the device number is 0, it is not PCI - always bridge. There are times when device of PCI allocates. - - When CONFIG_PCI_SKIP_HOST_BRIDGE is enable, this problem is solved when - use this patch. - - Signed-off-by: Nobuhiro Iwamatsu - Acked-by: Stefan Roese - -commit 86aea3eaefa248ffb9328e2b50c64720489cdbeb -Author: Yuri Tikhonov -Date: Fri Mar 21 09:18:40 2008 +0100 - - LWMON5: fix dsPIC POST - - Add test for DPIC_SYS_ERROR_REG to be zero in the LWMON5 dsPIC POST. - - Signed-off-by: Yuri Tikhonov --- - -commit 388b82fddc7c05596f3f615f190da0448227dc82 -Author: Bartlomiej Sieka -Date: Thu Mar 20 23:23:13 2008 +0100 - - [new uImage] Enable new uImage support for the pcs440ep board. - - Signed-off-by: Bartlomiej Sieka - -commit 95f4ec2b9c910c7261e6f060ea530d58b039692d -Author: Bartlomiej Sieka -Date: Thu Mar 20 23:23:13 2008 +0100 - - [new uImage] Do not compile new uImage format support by default - - Disable default building of new uImage format support in preparation - for merge with the master. Support for new format can be enabled on - a per-board basis, by defining the following in the board's config file: - - #define CONFIG_FIT 1 - #define CONFIG_OF_LIBFDT 1 - - This can be optionally defined to give more verbose output: - - #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ - - Signed-off-by: Bartlomiej Sieka - -commit dafaede8a46c7159310239e036c93e31c6374487 -Author: Bartlomiej Sieka -Date: Thu Mar 20 23:20:31 2008 +0100 - - [new uImage] Disable debuging output in preparation for merge with master - - Signed-off-by: Bartlomiej Sieka - -commit fbe7a155027beacebaee9b32e1ada781fe924bca -Author: Bartlomiej Sieka -Date: Thu Mar 20 19:38:45 2008 +0100 - - [new uImage] Compilation and new uImage handling fixes for imxtract - - Fix imxtract command not being compiled-in despite CONFIG_CMD_XIMG being in - include/config_cmd_default.h. Fix few warnings and handling of new format - images. - - Signed-off-by: Bartlomiej Sieka - -commit 36cc8cbb3379d5166f882641123521735c469f92 -Author: Bartlomiej Sieka -Date: Thu Mar 20 23:10:19 2008 +0100 - - [new uImage] Fix autoscr command used with new uImage format - - Signed-off-by: Bartlomiej Sieka - -commit 43142e817f0597be412e7cbe19413f5532eafa5d -Author: Bartlomiej Sieka -Date: Thu Mar 20 23:10:19 2008 +0100 - - [new uImage] Fix *.its files location in documentation - - Signed-off-by: Bartlomiej Sieka - -commit 81a0ac62ea29f8252d0a714709d0ecfdbba2a15e -Author: Wolfgang Denk -Date: Thu Mar 20 22:01:38 2008 +0100 - - lwmon5 POST: remove unreachable code - - plus some coding style cleanup - - Signed-off-by: Wolfgang Denk - -commit b73a19e1609d0f705cbab8014ca17aefe89e4c76 -Author: Yuri Tikhonov -Date: Thu Mar 20 17:56:04 2008 +0300 - - LWMON5: POST RTC fix - - Modify the RTC API to provide one a status for the time reported by - the rtc_get() function: - 0 - a reliable time is guaranteed, - < 0 - a reliable time isn't guaranteed (power fault, clock issues, - and so on). - - The RTC chip drivers are responsible for providing this info if the - corresponding chip supports such functionality. If not - always - report that the time is reliable. - - The POST RTC test was modified to detect the RTC faults utilizing - this new rtc_get() feature. - - Signed-off-by: Yuri Tikhonov - -commit a5cc5555ccee596908a7d8cf22a104f6b993bfd5 -Author: Martin Krause -Date: Wed Mar 19 14:25:14 2008 +0100 - - TQM5200B: update MTD partition layout - - - insert partition for dtb blob to TQM5200B MTD layout - - set env variables dependent on the configured board - (TQM5200 or TQM5200B) - - Signed-off-by: Martin Krause - -commit f0105727d132f56a21fa3ed8b162309cca6cac44 -Author: Stefan Roese -Date: Wed Mar 19 07:09:26 2008 +0100 - - CFI: Small cleanup for FLASH_SHOW_PROGRESS - - With this patch we don't need that many #ifdef's in the code. It moves - the subtraction into the macro and defines a NOP-macro when - CONFIG_FLASH_SHOW_PROGRESS is not defined. - - Signed-off-by: Stefan Roese - Acked-by: Gerald Van Baren - -commit 9a042e9ca512beaaa2cb450274313fc477141241 -Author: Jerry Van Baren -Date: Sat Mar 8 13:48:01 2008 -0500 - - Flash programming progress countdown. - - Signed-off-by: Gerald Van Baren - -commit 5e339fd9ed539a7d7fec59cfc88f0857ab26a53f -Author: Bartlomiej Sieka -Date: Wed Mar 19 10:00:06 2008 +0100 - - [new uImage] Fix style issue spotted by Wolfgang Denk - - Signed-off-by: Bartlomiej Sieka - -commit 11abe45c48ec3485a6c1a5168ce8d79c3288adc1 -Author: David Gibson -Date: Mon Feb 18 18:09:04 2008 +1100 - - libfdt: Remove no longer used code from fdt_node_offset_by_compatible() - - Since fdt_node_offset_by_compatible() was converted to the new - fdt_next_node() iterator, a chunk of initialization code became - redundant, but was not removed by oversight. This patch cleans it up. - - Signed-off-by: David Gibson - -commit d0ccb9b140b472039732de102fc14597eedb14df -Author: David Gibson -Date: Mon Feb 18 18:06:31 2008 +1100 - - libfdt: Trivial cleanup for CHECK_HEADER) - - Currently the CHECK_HEADER() macro is defined local to fdt_ro.c. - However, there are a handful of functions (fdt_move, rw_check_header, - fdt_open_into) from other files which could also use it (currently - they open-code something more-or-less identical). Therefore, this - patch moves CHECK_HEADER() to libfdt_internal.h and uses it in those - places. - - Signed-off-by: David Gibson - -commit fe30a354cdbb808b5f15366a935b151a4ccee74f -Author: Kumar Gala -Date: Wed Feb 20 14:32:36 2008 -0600 - - Fix fdt boardsetup command parsing - - The introduciton of the 'fdt bootcpu' broke parsing for 'fdt boardsetup'. - - Signed-off-by: Kumar Gala - -commit 804887e6001e2f00bea11431bf34d6d472512cda -Author: Kumar Gala -Date: Fri Feb 15 03:34:36 2008 -0600 - - Add sub-commands to fdt - - fdt header - Display header info - fdt bootcpu - Set boot cpuid - fdt memory - Add/Update memory node - fdt rsvmem print - Show current mem reserves - fdt rsvmem add - Add a mem reserve - fdt rsvmem delete - Delete a mem reserves - - Signed-off-by: Kumar Gala - -commit f84d65f9b085ffbed464d1d58e8aaa8f5a2efc07 -Author: David Gibson -Date: Thu Feb 14 16:50:34 2008 +1100 - - libfdt: Fix NOP handling bug in fdt_add_subnode_namelen() - - fdt_add_subnode_namelen() has a bug if asked to add a subnode to a - node which has NOP tags interspersed with its properties. In this - case fdt_add_subnode_namelen() will put the new subnode before the - first NOP tag, even if there are properties after it, which will - result in an invalid blob. - - This patch fixes the bug, and adds a testcase for it. - - Signed-off-by: David Gibson - -commit ae0b5908de3b9855f8931bc9b32c9fc4962df5a9 -Author: David Gibson -Date: Tue Feb 12 11:58:31 2008 +1100 - - libfdt: Add and use a node iteration helper function. - - This patch adds an fdt_next_node() function which can be used to - iterate through nodes of the tree while keeping track of depth. This - function is used to simplify the iteration code in a lot of other - functions, and is also exported for use by library users. - - Signed-off-by: David Gibson - -commit 9eaeb07a7185d852c7aa10735ecd4e9edf24fb5d -Author: David Gibson -Date: Fri Jan 11 14:55:05 2008 +1100 - - libfdt: Add fdt_set_name() function - - This patch adds an fdt_set_name() function to libfdt, mirroring - fdt_get_name(). This is a r/w function which alters the name of a - given device tree node. - - Signed-off-by: David Gibson - -commit 23e20aa6488e6c0622496549861bfdc74108debe -Author: Yuri Tikhonov -Date: Tue Mar 18 13:33:30 2008 +0100 - - lwmon5: Fix register test logic to match the specific GDC h/w. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit 46bc0a938779aa1d664b847d36b08aa00f22e539 -Author: Yuri Tikhonov -Date: Tue Mar 18 13:27:57 2008 +0100 - - Fix backlight in the lwmon5 POST. - - Backlight was switched on even when temperature was too low. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit 3d61018643a2cd38c145aa6dde53f3f5f1a0e9cf -Author: Yuri Tikhonov -Date: Wed Feb 6 18:48:36 2008 +0100 - - The patch introduces the alternative configuration of the log buffer for the lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory), the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ..., PPC440EPX_GPT0_COMP5). - - To enable this, alternative, configuration the U-Boot board configuration - file for lwmon5 includes the definitions of alternative addresses for header - (CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR). - - The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set, - and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the - lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h). - - Signed-off-by: Yuri Tikhonov - -commit 0f009f781b5b88f25769e154ea4d42db13baf0c6 -Author: Yuri Tikhonov -Date: Mon Feb 4 17:11:53 2008 +0100 - - Add support for the lwmon5 board reset via GPIO58. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit f694e32f93565ec1fa8d0226c584d6b89e931ed9 -Author: Yuri Tikhonov -Date: Mon Feb 4 17:09:55 2008 +0100 - - Some fixes to dspic, fpga, and gdc post tests for lwmon5. Disable external watch-dog for now. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit b428f6a8c65c5303e5f96db8d24f2f699d94a98c -Author: Yuri Tikhonov -Date: Mon Feb 4 14:11:03 2008 +0100 - - The patch introduces the CRITICAL feature of POST tests. If the test marked as POST_CRITICAL fails then the alternative, post_critical, boot-command is used. If this command is not defined then U-Boot enters into interactive mode. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit 8f15d4addd49c956412e1e3bfc764a0c8b1f3184 -Author: Yuri Tikhonov -Date: Mon Feb 4 14:10:42 2008 +0100 - - The patch adds new POST tests for the Lwmon5 board. These are: - - * External Watchdog test; - * dsPIC tests; - * FPGA test; - * GDC test; - * Sysmon tests. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit c2ed33efbfff5767bca236828e021c55fd547b6c -Author: Yuri Tikhonov -Date: Mon Feb 4 14:10:01 2008 +0100 - - Enable CODEC POST with CFG_POST_CODEC rather than with CFG_POST_DSP. - - Signed-off-by: Dmitry Rakhchev - -commit 3a5d1e7f1309998791702b2a559e3126781746b9 -Author: Yuri Tikhonov -Date: Tue Mar 18 13:33:30 2008 +0100 - - lwmon5: Fix register test logic to match the specific GDC h/w. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit 0f855a1f056a8c22116a2103a3900cbfb669df0b -Author: Yuri Tikhonov -Date: Tue Mar 18 13:27:57 2008 +0100 - - Fix backlight in the lwmon5 POST. - - Backlight was switcehd on even when temperature was too low. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit 2d991958b1e420fbfe17b128bd26ade74be5efcc -Author: Yuri Tikhonov -Date: Wed Feb 6 18:48:36 2008 +0100 - - The patch introduces the alternative configuration of the log buffer for - the lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory), - the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ..., - PPC440EPX_GPT0_COMP5). - - To enable this, alternative, configuration the U-Boot board configuration - file for lwmon5 includes the definitions of alternative addresses for header - (CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR). - - The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set, - and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the - lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h). - - Signed-off-by: Yuri Tikhonov - -commit ff818b21b069f4bc9cb73373cc5a16014be101b7 -Author: Yuri Tikhonov -Date: Mon Feb 4 17:11:53 2008 +0100 - - Add support for the lwmon5 board reset via GPIO58. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit 603f194e5ad81bb2ef42d6d8aaa74de175bcb411 -Author: Yuri Tikhonov -Date: Mon Feb 4 17:09:55 2008 +0100 - - Some fixes to dspic, fpga, and gdc post tests for lwmon5. - Disable external watch-dog for now. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit e262efe35742c1ad4b0966ff501efc26f34a0aec -Author: Yuri Tikhonov -Date: Mon Feb 4 14:11:03 2008 +0100 - - The patch introduces the CRITICAL feature of POST tests. If the test - marked as POST_CRITICAL fails then the alternative, post_critical, - boot-command is used. If this command is not defined then U-Boot - enters into interactive mode. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit 65b20dcefc89618193fa51947968dada91e4c778 -Author: Yuri Tikhonov -Date: Mon Feb 4 14:10:42 2008 +0100 - - The patch adds new POST tests for the Lwmon5 board. - These are: - - * External Watchdog test; - * dsPIC tests; - * FPGA test; - * GDC test; - * Sysmon tests. - - Signed-off-by: Dmitry Rakhchev - Signed-off-by: Yuri Tikhonov - -commit 8dc3b2303d2b57c774b609ca0e7043ed8f9b88c1 -Author: Yuri Tikhonov -Date: Mon Feb 4 14:10:01 2008 +0100 - - Enable CODEC POST with CFG_POST_CODEC rather than with CFG_POST_DSP. - - Signed-off-by: Dmitry Rakhchev - -commit 3515fd18d4e8e44f863ac7142b55e22b109e9af2 -Author: Wolfgang Denk -Date: Tue Mar 18 17:35:51 2008 +0100 - - HMI1001: fix compile problem. - - Signed-off-by: Wolfgang Denk - -commit 1f2a9970109cebf7446e0503b10b71f8673045ee -Author: Mike Frysinger -Date: Mon Feb 18 05:32:30 2008 -0500 - - Blackfin: BF537-stamp: drop board-specific flash driver for CFI - - The parallel flash on the BF537-STAMP is CFI compliant, so there is no need - for the board specific driver at all. Just use the common CFI driver. - - Signed-off-by: Mike Frysinger - -commit 5b22163fef865af2b6bfb6b75f1b7bf443ce170c -Author: Mike Frysinger -Date: Tue Feb 19 00:36:14 2008 -0500 - - Blackfin: add proper ELF markings to some assembly functions - - Signed-off-by: Mike Frysinger - -commit cf675d3b2b9c3511c1d99bc8f8f38fd2f08bfcaf -Author: Mike Frysinger -Date: Tue Feb 19 00:35:17 2008 -0500 - - Blackfin: new cplbinfo command for viewing cplb tables - - Signed-off-by: Mike Frysinger - -commit aadb72503cd1602349a5fe53356d5f55ecc1b900 -Author: Mike Frysinger -Date: Mon Feb 18 05:37:51 2008 -0500 - - Blackfin: update MAINTAINERS list - - Add maintainer information for the Blackfin boards. - - Signed-off-by: Mike Frysinger - -commit f7ce12cb65a30c6e152eecf26f0304b7d78cf39d -Author: Mike Frysinger -Date: Mon Feb 18 05:26:48 2008 -0500 - - Blackfin: convert BFIN_CPU to CONFIG_BFIN_CPU - - Stop tying things to the processor that should be tied to other defines and - change BFIN_CPU to CONFIG_BFIN_CPU so that it can be used in the build - system to select the -mcpu option. - - Signed-off-by: Mike Frysinger - -commit 86a20fb920bd198105acf7b1191117f566d637ed -Author: Mike Frysinger -Date: Sat Feb 16 07:40:36 2008 -0500 - - Blackfin: move bootldr command to common code - - This moves the Blackfin-common bootldr command out of the BF537-STAMP - specific board directory and into the common directory so that all Blackfin - boards may utilize it. - - Signed-off-by: Mike Frysinger - -commit decbe029b2a9d3333d02c433389b1c821eea96d7 -Author: Heiko Schocher -Date: Fri Mar 14 11:05:20 2008 +0100 - - mgcoge: update configuration - - Fix configuration for mgcoge board - - Signed-off-by: Heiko Schocher - -commit c136724cda0219c49f1d4b346f00da29b14fdf14 -Author: Wolfgang Denk -Date: Sun Mar 16 01:22:59 2008 +0100 - - drivers/rtc/Makefile: keep list sorted - - Signed-off-by: Wolfgang Denk - -commit 9536dfcce03e7be4ccbceb47a08d9ba07ada362f -Author: Tor Krill -Date: Sat Mar 15 15:40:26 2008 +0100 - - Add support for Intersil isl1208 RTC - - Signed-off-by: Tor Krill - -commit 0210cff3d079d97b2156b13685ee8de368e68a1a -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Mar 15 17:36:41 2008 +0100 - - cramfs: Fix ifdef - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 0b8f2a27861a9fd06eb55a34f855ec9c5102aab4 -Author: Wolfgang Denk -Date: Sun Mar 16 01:12:58 2008 +0100 - - Conding style cleanup - - Signed-off-by: Wolfgang Denk - -commit 41712b4e8c95dff23354bcd620e1f9477160c190 -Author: Stefan Roese -Date: Wed Mar 5 12:31:53 2008 +0100 - - ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval board - - This patch adds USB OHCI support to the Canyonlands board port. It also - enables EXT2 support. - - Signed-off-by: Stefan Roese - -commit 2596f5b9d353ff3e4387a3325d05740f16958038 -Author: Stefan Roese -Date: Wed Mar 5 12:29:32 2008 +0100 - - usb: Add CFG_OHCI_USE_NPS to common USB-OHCI driver - - This patch adds CFG_OHCI_USE_NPS to the common USB-OHCI driver. This - way a board just needs to define this new option to enable the "force - NoPowerSwitching mode" instead of adding new CPU/architecture defines - to the USB source itself. - - This new option will be used first with the new AMCC 460EX Canyonlands - board port, which will be posted in a few days. - - This patch also fixes a small compilation problem when DEBUG is enabled. - - Signed-off-by: Stefan Roese - -commit 71665ebf88408ff2acb762af47989fd4365b321a -Author: Stefan Roese -Date: Mon Mar 3 17:27:02 2008 +0100 - - ppc4xx: Add Canyonlands NAND booting support - - 460EX doesn't support a fixed bootstrap option to boot from 512 byte page - NAND devices. The only bootstrap option for NAND booting is option F for - 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap - EEPROM needs to be programmed accordingly. - - This patch adds basic NAND booting support for the AMCC Canyonlands aval - board and also adds support to the "bootstrap" command, to enable NAND - booting I2C setting. - - Tested with 512 byte page NAND device (32MByte) on Canyonlands. - - Signed-off-by: Stefan Roese - -commit c813f1f835a7edfdb929f2843b09db72cd5cd2f2 -Author: Stefan Roese -Date: Tue Mar 11 16:53:00 2008 +0100 - - ppc4xx: Add AMCC Canyonlands support (460EX) (3/3) - - This patch adds support for the AMCC Canyonlands 460EX evaluation - board. - - Signed-off-by: Stefan Roese - -commit 6983fe21f774a924d3adb263a270bc2f301f2aa2 -Author: Stefan Roese -Date: Tue Mar 11 16:52:24 2008 +0100 - - ppc4xx: Add AMCC Canyonlands support (460EX) (2/3) - - This patch adds support for the AMCC Canyonlands 460EX evaluation - board. - - Signed-off-by: Stefan Roese - -commit 8e1a3fe545bbcfceafe183344ebc9f1ad03819c1 -Author: Stefan Roese -Date: Tue Mar 11 16:51:17 2008 +0100 - - ppc4xx: Add AMCC Canyonlands support (460EX) (1/3) - - This patch adds support for the AMCC Canyonlands 460EX evaluation - board. - - Signed-off-by: Stefan Roese - -commit 43c60992cdf72496e7eaaa3fbd37ebbe75835f69 -Author: Stefan Roese -Date: Tue Mar 11 15:11:43 2008 +0100 - - ppc4xx: Add basic support for AMCC 460EX/460GT (5/5) - - This patch adds basic support for the AMCC 460EX/460GT PPC's. - - Signed-off-by: Stefan Roese - -commit 6f2eb3f3d8ea2dbb224d0da5a12038693bab9945 -Author: Stefan Roese -Date: Tue Mar 11 15:11:18 2008 +0100 - - ppc4xx: Add basic support for AMCC 460EX/460GT (4/5) - - This patch adds basic support for the AMCC 460EX/460GT PPC's. - - Signed-off-by: Stefan Roese - -commit 999ecd5aca381984d8ebbeb207ece82a1c275577 -Author: Stefan Roese -Date: Tue Mar 11 15:07:10 2008 +0100 - - ppc4xx: Add basic support for AMCC 460EX/460GT (3/5) - - This patch adds basic support for the AMCC 460EX/460GT PPC's. - - Signed-off-by: Stefan Roese - -commit 2801b2d2a9906f206ab9ee8d0b6e746d2b7fe05a -Author: Stefan Roese -Date: Tue Mar 11 15:05:50 2008 +0100 - - ppc4xx: Add basic support for AMCC 460EX/460GT (2/5) - - This patch adds basic support for the AMCC 460EX/460GT PPC's. - - Signed-off-by: Stefan Roese - -commit 8ac41e3e37c3080c6b1d9461d654161cfe2aa492 -Author: Stefan Roese -Date: Tue Mar 11 15:05:26 2008 +0100 - - ppc4xx: Add basic support for AMCC 460EX/460GT (1/5) - - This patch adds basic support for the AMCC 460EX/460GT PPC's. - - Signed-off-by: Stefan Roese - -commit 56e410178375d9f20be25fb24e180974f0ae120b -Author: Stefan Roese -Date: Tue Feb 19 22:07:57 2008 +0100 - - ppc4xx: interrupt.c reworked - - This patch is a rework of the 4xx interrupt handling done while - adding the 460EX/GT support. Interrupts are needed on 4xx for the - EMAC driver. - - Signed-off-by: Stefan Roese - -commit 84a999b6cdd0b02dc7de2cacc306eaa84afe2b46 -Author: Stefan Roese -Date: Tue Feb 19 22:01:57 2008 +0100 - - ppc4xx: program_tlb now uses 64bit physical addess - - This patch changes the physical addess parameter from 32bit to 64bit. - This is needed for 36bit 4xx platforms to access areas located - beyond the 4GB border, like SoC peripherals (EBC etc.). - - Signed-off-by: Stefan Roese - -commit c3307fa186af85771924c434997089b8104c0a46 -Author: Stefan Roese -Date: Tue Feb 19 21:58:25 2008 +0100 - - ppc4xx: miiphy.c reworked - - While adding the 460EX/GT support I reworked the 4xx miiphy code. It - badly neede some cleanup. - - Signed-off-by: Stefan Roese - -commit 88aff62df39c0756241ea9f9b5a7b3ade26cb82b -Author: Stefan Roese -Date: Tue Feb 19 16:21:49 2008 +0100 - - rtc: Add M41T62 support - - This patch add support for the STM M41T62 RTC. It is used and tested - on the AMCC Canyonlands 406EX platform. - - Signed-off-by: Stefan Roese - -commit 217d383e201adc7f2271145ae345ea5eae2b7170 -Author: Niklaus Giger -Date: Mon Feb 25 18:46:43 2008 +0100 - - ppc4xx: Add 405GPr based MCU25 board specific files - - Signed-off-by: Niklaus Giger - -commit 75a66dcdb383863ad33f0534cfc27b7a86947dad -Author: Niklaus Giger -Date: Mon Feb 25 18:46:42 2008 +0100 - - ppc4xx: Add 405GPr based MCU25 board config file - - Signed-off-by: Niklaus Giger - -commit b05f35436b733a240559e77e46bed8439665ecc5 -Author: Niklaus Giger -Date: Mon Feb 25 18:46:41 2008 +0100 - - ppc4xx: Add 405GPr based MCU25 board. Global files - - Signed-off-by: Niklaus Giger - -commit 14c27b35ac812a71abce6e3e2f4129d5e9313660 -Author: Niklaus Giger -Date: Mon Feb 25 18:37:02 2008 +0100 - - ppc4xx: HCU4/5. remove obsolete hcu_flash.c - - Signed-off-by: Niklaus Giger - -commit a079494853cc2bfeddb26673219db0b4b2b31566 -Author: Niklaus Giger -Date: Mon Feb 25 18:37:01 2008 +0100 - - ppc4xx: HCU4/5. Use FLASH_CFI_LEGACY - - Cleanup: Remove custom flash driver for 8 bit boot-eprom and replace it with - the FLASH_CFI_LEGACY et al. config options. - - Signed-off-by: Niklaus Giger - -commit e4170e5a50c8110f792bc37472833ae669d69951 -Author: Stefan Roese -Date: Tue Mar 11 13:52:25 2008 +0100 - - ppc4xx: Fix comment in 405EX DDR2 init code - - Signed-off-by: Stefan Roese - -commit 766529fccc860ecb9e955b4239dff69cd9e4ea09 -Author: Bartlomiej Sieka -Date: Fri Mar 14 16:22:34 2008 +0100 - - Add MD5 support to the new uImage format - - Signed-off-by: Bartlomiej Sieka - -commit 0ede0c383530a418cf98be9122371a86573cd0db -Author: Bartlomiej Sieka -Date: Fri Mar 14 16:22:34 2008 +0100 - - Add the MD5 algorithm - - MD5 supoprt is turned on by defining CONFIG_MD5, the digest can be then - calculated using the md5() function -- see include/md5.h for details. - - Signed-off-by: Bartlomiej Sieka - -commit b8aa57b5d4d69e8f0810a5e632c0ce41c0f46ee0 -Author: Wolfgang Denk -Date: Fri Mar 14 16:04:54 2008 +0100 - - tools/setlocalversion: use a git-describe-ish format - - Change the automatic local version to have the form -nnnnn-gSHA1SUMID, - where 'nnnnn' is the number of commits since the last tag (i.e., - 1.3.2-rc3). This makes it much easier to recognize "newer" versions - and to see how much has been changed since the referenced tag. - - Stolen from Linux kernel's scripts/setlocalversio, see commit d882421f. - - Signed-off-by: Wolfgang Denk - -commit c6dc21c84de0f159a1752c5ebd33cff843f63609 -Author: Wolfgang Denk -Date: Thu Mar 13 14:32:03 2008 +0100 - - HMI1001: add support for MPC5200 Rev. B processors. - - Signed-off-by: Wolfgang Denk - -commit 90f13dce7a7a9a84d5730576c9a24d0dbb07cb3a -Author: Wolfgang Denk -Date: Thu Mar 13 14:29:49 2008 +0100 - - TQM5200: remove dead code - - This board never used a MGT5100 processor. - - Signed-off-by: Wolfgang Denk - -commit afe45c87e3c5d77bad76b1a57dccd20764d45b5d -Author: Marian Balakowicz -Date: Wed Mar 12 12:14:15 2008 +0100 - - [new uImage] Fix build issue on ARM - - ARM platforms don't have a bd->bi_memsize so use bd->bi_dram[0].size instead. - - Signed-off-by: Kumar Gala - -commit 3310c549a73a949430bfda90876df7552a1dab0c -Author: Marian Balakowicz -Date: Wed Mar 12 12:13:13 2008 +0100 - - [new uImage] Add new uImage format documentation and examples - - Create doc/uImage.FIT documentation directory with the following files: - - command_syntax_extensions.txt : extended command syntax description - - howto.txt : short usage howto - - source_file_format.txt : internal new uImage format description - - Add example image source files: - - kernel.its - - kernel_fdt.its - - multi.its - - Update README appropriately. - - Signed-off-by: Marian Balakowicz - Signed-off-by: Bartlomiej Sieka - -commit 1ec73761d2e247078f4520a265d463e8b73391a2 -Author: Marian Balakowicz -Date: Wed Mar 12 10:35:52 2008 +0100 - - [new uImage] Fix definition of common bootm_headers_t fields - - verify, autostart and lmb fields are used regardless of CONFIG_FIT - setting, move their definitions to common section. - - Signed-off-by: Marian Balakowicz - -commit 1d1cb4270edc6a99276834064069717f9782c491 -Author: Marian Balakowicz -Date: Wed Mar 12 10:35:51 2008 +0100 - - [new uImage] Fix build problems on trab board - - Signed-off-by: Marian Balakowicz - -commit f773bea8e11f4a11c388dcee956b2444203e6b65 -Author: Marian Balakowicz -Date: Wed Mar 12 10:35:46 2008 +0100 - - [new uImage] Add proper ramdisk/FDT handling when FIT configuration is used - - Save FIT configuration provied in the first bootm argument and use it - when to get ramdisk/FDT subimages when second and third (ramdisk/FDT) - arguments are not specified. - - Signed-off-by: Marian Balakowicz - -commit 2682ce8a4225f23d72bb7fed069e928dd39d34ae -Author: Marian Balakowicz -Date: Wed Mar 12 10:33:01 2008 +0100 - - [new uImage] More verbose kernel image uncompress error message - - Signed-off-by: Marian Balakowicz - -commit 1372cce2b9040fb640e5032b84e3a033a22d6ff0 -Author: Marian Balakowicz -Date: Wed Mar 12 10:33:01 2008 +0100 - - [new uImage] Use show_boot_progress() for new uImage format - - This patch allocates a set of show_boot_progress() IDs for new uImage format - and adds show_boot_progress() calls in new uImage format handling code. - - Signed-off-by: Marian Balakowicz - -commit c28c4d193dbfb20b2dd3a5447640fd6de7fd0720 -Author: Marian Balakowicz -Date: Wed Mar 12 10:33:01 2008 +0100 - - [new uImage] Add new uImage fromat support to fpga command - - Signed-off-by: Marian Balakowicz - -commit 09475f7527460e426c0e0628fc5b8f3754fbaa23 -Author: Marian Balakowicz -Date: Wed Mar 12 10:33:01 2008 +0100 - - [new uImage] Add new uImage format handling to other bootm related commands - - Updated commands: - - docboot - cmd_doc.c - fdcboot - cmd_fdc.c - diskboot - cmd_ide.c - nboot - cmd_nand.c - scsiboot - cmd_scsi.c - usbboot - cmd_usb.c - - Signed-off-by: Marian Balakowicz - -commit 1b7897f28d49a80d78d760ec6f6f11dc0f914338 -Author: Marian Balakowicz -Date: Wed Mar 12 10:33:00 2008 +0100 - - [new uImage] Add new uImage format support to imgextract command - - Signed-off-by: Marian Balakowicz - -commit 424c4abdd175d2c470510df8ce0e32d3f463ec16 -Author: Marian Balakowicz -Date: Wed Mar 12 10:33:00 2008 +0100 - - [new uImage] Add new uImage format support to autoscript routine - - autoscript() routine is updated to accept second argument, which - is only used for FIT images and provides a FIT subimage unit name. - - autoscript() routine callers must now pass two arguments. For - non-interactive use (like in cmd_load.c, cmd_net.c), new environment - variable 'autoscript_uname' is introduced and used as a FIT - subimage unit name source. - - autoscript command accepts extended syntax of the addr argument: - addr: - - Signed-off-by: Marian Balakowicz - -commit cd7c596e9f561dbbc17b717277438aee78cde14f -Author: Marian Balakowicz -Date: Wed Mar 12 10:33:00 2008 +0100 - - [new uImage] Add new uImage format support to arch specific do_bootm_linux() routines - - This patch updates architecture specific implementations of - do_bootm_linux() adding new uImage format handling for - operations like get kernel entry point address, get kernel - image data start address. - - Signed-off-by: Marian Balakowicz - -commit 3dfe110149311425919e6d6a14b561b4207498f1 -Author: Marian Balakowicz -Date: Wed Mar 12 10:32:59 2008 +0100 - - [new uImage] Add node offsets for FIT images listed in struct bootm_headers - - This patch adds new node offset fields to struct bootm_headers - and updates bootm_headers processing code to make use of them. - Saved node offsets allow to avoid repeating fit_image_get_node() calls. - - Signed-off-by: Marian Balakowicz - -commit bc8ed486b125452ba3bd8344f052f437329150c5 -Author: Marian Balakowicz -Date: Wed Mar 12 10:32:53 2008 +0100 - - [new uImage] ppc: Add new uImage format support to FDT handling routines - - Support for new (FIT) format uImages is added to powerpc specific - boot_get_fdt() routine which now recognizes, sanity checks FIT image - and is able to access data sections of the requested component image. - - Signed-off-by: Marian Balakowicz - -commit a44a269a905f924b420020506a4d7d7eedcc0eaf -Author: Marian Balakowicz -Date: Wed Mar 12 10:14:57 2008 +0100 - - [new uImage] Re-enable interrupts for non automatic booting - - Re-enable interrupts if we return from do_bootm_ and 'autostart' - environment variable is not set to 'yes'. - - Signed-off-by: Marian Balakowicz - -commit d985c8498c4e47095820da97aa722381d39172c5 -Author: Marian Balakowicz -Date: Wed Mar 12 10:14:38 2008 +0100 - - [new uImage] Remove unnecessary arguments passed to ramdisk routines - - boot_get_ramdisk() and image_get_ramdisk() do not need all - cmdtp, flag, argc and argv arguments. Simplify routines definition. - - Signed-off-by: Marian Balakowicz - -commit c87796483bc7c2900470dc747c367f602577608d -Author: Marian Balakowicz -Date: Wed Mar 12 10:12:37 2008 +0100 - - [new uImage] Add new uImage format support for ramdisk handling - - This patch updates boot_get_ramdisk() routine adding format - verification and handling for new (FIT) uImages. - - Signed-off-by: Marian Balakowicz - -commit 6986a385671749ecb3f60cf99e9cbae8e47bb50e -Author: Marian Balakowicz -Date: Wed Mar 12 10:01:05 2008 +0100 - - [new uImage] Add new uImage format support for kernel booting - - New format uImages are recognized by the bootm command, - validity of specified kernel component image is checked and - its data section located and used for further processing - (uncompress, load, etc.) - - Signed-off-by: Marian Balakowicz - -commit e32fea6adb620ecf2bd70acf2dd37e53df9d1547 -Author: Marian Balakowicz -Date: Tue Mar 11 12:35:20 2008 +0100 - - [new uImage] Add new uImage format support for imls and iminfo commands - - imls and iminfo can now recognize nad print out contents of the new (FIT) - format uImages. - - Signed-off-by: Marian Balakowicz - -commit 9d25438fe7d70cf35a8a293ea5e392fefc672613 -Author: Bartlomiej Sieka -Date: Tue Mar 11 12:34:47 2008 +0100 - - [new uImage] Add support for new uImage format to mkimage tool - - Support for the new uImage format (FIT) is added to mkimage tool. - Commandline syntax is appropriately extended: - - mkimage [-D dtc_options] -f fit-image.its fit-image - - mkimage (together with dtc) takes fit-image.its and referenced therein - binaries (like vmlinux.bin.gz) as inputs, and produces fit-image file -- the - final image that can be transferred to the target (e.g., via tftp) and then - booted using the bootm command in U-Boot. - - Signed-off-by: Bartlomiej Sieka - -commit eb6175edd6c120d8b89678243e5a2be362ee8e40 -Author: Marian Balakowicz -Date: Mon Mar 10 17:53:49 2008 +0100 - - [new uImage] Make node unit names const in struct bootm_headers - - Signed-off-by: Marian Balakowicz - -commit 5dfb52138688ccbf0146f62683fe6217b3ce1b05 -Author: Marian Balakowicz -Date: Fri Feb 29 21:24:06 2008 +0100 - - [new uImage] New uImage low-level API - - Add FDT-based functions for handling new format component images, - configurations, node operations, property get/set, etc. - - fit_ - routines handling global new format uImage operations - like get/set top level property, process all nodes, etc. - fit_image_ - routines handling component images subnodes - fit_conf_ - routines handling configurations node - - Signed-off-by: Bartlomiej Sieka - Signed-off-by: Marian Balakowicz - -commit 30f1806f60978d707b0cff2d7bf89d141fc24290 -Author: Wolfgang Denk -Date: Sun Mar 9 16:20:02 2008 +0100 - - Release v1.3.2 - - Update CHANGELOG for release. - - Signed-off-by: Wolfgang Denk - -commit 5b464c289ba715d0979b6e1f94947bb8f1068d16 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Mar 9 14:52:11 2008 +0100 - - SCM: fix 'packed' attribute ignored for field of type 'can_msg_t' warnings - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Wolfgang Denk - -commit db695b78515ddb88a2d4f3357c120345efbf59ec -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Mar 9 10:44:01 2008 +0100 - - scb9328: Fix flash warning: type qualifiers ignored on function return type - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 2b3e7e61d6a72f16aee93f870bc6af67f30758c4 -Author: Wolfgang Denk -Date: Sun Mar 9 10:50:41 2008 +0100 - - esd/common/fpga.c: fix indentation. - - Signed-off-by: Wolfgang Denk - -commit cc3843e36453e2b8db65d7e56de938ba045016a0 -Author: Wolfgang Denk -Date: Sun Mar 9 10:33:31 2008 +0100 - - common/kgdb.c: fix 'dereferencing type-punned pointer' warning - - and get rid of a couple of unneeded casts. - - Signed-off-by: Wolfgang Denk - -commit 8d4f4a838d7dc7cf4de17e3e9a67e2f222b6a1c8 -Author: Wolfgang Denk -Date: Sun Mar 9 10:09:53 2008 +0100 - - esd/common/fpga.c: fix 'assignment of read-only location' error - - Signed-off-by: Wolfgang Denk - -commit c6fe4dabac066e8758345d249032768496983a3e -Author: Wolfgang Denk -Date: Sun Mar 9 02:13:19 2008 +0100 - - Makefile: make build silently again. - - Signed-off-by: Wolfgang Denk - -commit 76babc86576f092573599334c85ec543fdbc6015 -Author: Wolfgang Denk -Date: Sun Mar 9 02:07:49 2008 +0100 - - m501sk: Fix out of tree building - - Signed-off-by: Wolfgang Denk - -commit 210ed2004e062fdd03f25ab4925998aa1bd08a07 -Author: Wolfgang Denk -Date: Sun Mar 9 00:06:09 2008 +0100 - - ADS5121: fix out of tree build - - and simplify Makefile a bit. - - Signed-off-by: Wolfgang Denk - -commit 46cb5074a3f74de64ebd97dd0c4ec7eb3d768b93 -Author: Wolfgang Denk -Date: Sat Mar 8 22:35:31 2008 +0100 - - Release v1.3.2 - - Signed-off-by: Wolfgang Denk - -commit 78a90f827df74520e939c794fc7413dace21c4db -Author: Wolfgang Denk -Date: Sat Mar 8 22:35:04 2008 +0100 - - Update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 58f3c57c6008b42e01f551d3be6efd88c14ac87f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Mar 8 21:30:04 2008 +0100 - - esd: Fix warning: passing argument 1 of 'fpga_boot' discards qualifiers from pointer target type - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit d75469d48c05795144f4b8ba76addbb4920a7bba -Author: Nobuhiro Iwamatsu -Date: Sat Mar 8 09:25:49 2008 +0900 - - net: rtl8169: Add processing when OWNbit did't enable in rtl_recv() - - When rtl_recv() of rtl8169 is called, OWNbit of status register - is not enable occasionally. - rtl_recv() doesn't work normally when the driver doesn't do - appropriate processing. - This patch fix this problem. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 82afabfeb8ae6a27c7b396011ea99f4712aa73fa -Author: Heiko Schocher -Date: Fri Mar 7 08:15:28 2008 +0100 - - mgsuvd: update board configuration - - initialize the UPIOx controller. - - Signed-off-by: Heiko Schocher - -commit e492c90c26215e459aec0fdf0f8ef1fd204988f5 -Author: Heiko Schocher -Date: Fri Mar 7 08:13:41 2008 +0100 - - mgcoge: update board configuration - - add support for the config Flash. - initialize the UPIOx controller. - - Signed-off-by: Heiko Schocher - -commit 270fe261b7f9292800b2b3d1bf19ae7cbc880258 -Author: Kim Phillips -Date: Fri Mar 7 12:27:31 2008 -0600 - - mpc83xx: make dtb basename file references equal those of linux - - the dts file basenames were updated in linux - this helps avoid - inadvertently loading any old dtbs laying around. - - Signed-off-by: Kim Phillips - -commit f30b6154f16f5ffa4a9f5bfca5e114d72b6ef675 -Author: Kim Phillips -Date: Wed Feb 27 16:08:22 2008 -0600 - - net: uec_phy: actually increment the timeout counter - - allow u-boot to recover (and, e.g., switch to another interface) in the - case where a PHY does not report autonegotiation is complete within its - two second timeout value. - - Signed-off-by: Kim Phillips - -commit 772003e43957ee0c895abed7cd82cbe72820cbb8 -Author: Markus Brunner -Date: Wed Mar 5 21:38:12 2008 +0100 - - fix taihu soft spi_read - - The taihu board used gpio_read_out_bit which reads the output register and not - the pin state. - - Signed-off-by: Markus Brunner - -commit fc84a8495ac750f6b4adae81f8c4f100f65b6340 -Author: Stefan Roese -Date: Fri Mar 7 08:01:43 2008 +0100 - - ppc4xx: Sequoia: Add device tree (fdt) Linux booting default env variables - - Signed-off-by: Stefan Roese - -commit bd4458cb47abecabd406b1210457be96c69fc49d -Author: Dave Liu -Date: Tue Mar 4 16:59:22 2008 +0800 - - 837xEMDS: Improve the system performance - - 1. Make the CSB bus pipeline depth as 4, and enable - the repeat mode; - 2. Raise the eTSEC emergency priority; - 3. Use the highest IP blocks clock. - - Signed-off-by: Dave Liu - -commit d8ab58b212481b1c57947ea21aa96c4ce800d0b4 -Author: Detlev Zundel -Date: Thu Mar 6 16:45:53 2008 +0100 - - Replace "run load; run update" with conditionalized "run load update". - - The latter version stops when "run load" fails for whatever reasons - rendering the combination *a lot* more secure. - - Signed-off-by: Detlev Zundel - -commit 6bc113886d7d316df1a4e459bec8baf027518551 -Author: Stefan Roese -Date: Tue Mar 4 17:40:41 2008 +0100 - - net: Print error message upon net usage when no ethernet-interface is found - - This patch fixes a problem seen on PPC4xx boards, when no MAC address is - defined. Then no ethernet interface is available but a simple "tftp" - command will return without any error message which is quite confusing. - - Signed-off-by: Stefan Roese - -commit a30a549a3553032d809e0356306b62de0b125901 -Author: Jon Loeliger -Date: Tue Mar 4 10:03:03 2008 -0600 - - Remove erroneous or extra spd.h #includers. - - Many of the spd.h #includers don't need it, - and wanted to have spd_sdram() declared instead. - Since they didn't get that, some also had open - coded extern declarations of it instead or as well. - Fix it all up by using spd_sdram.h where needed. - - Signed-off-by: Jon Loeliger - -commit a4475386cef14af3fd88f0518b688e755669486d -Author: Wolfgang Denk -Date: Tue Mar 4 17:41:28 2008 +0100 - - PCS440EP: fix build problems (redundant #define) - - Signed-off-by: Wolfgang Denk - -commit e85e2fa85ec09a6fac2846d1d881d8737e2bbda9 -Author: Stefan Roese -Date: Tue Mar 4 17:39:25 2008 +0100 - - net: Print error message upon net usage when no ethernet-interface is found - - This patch fixes a problem seen on PPC4xx boards, when no MAC address is - defined. Then no ethernet interface is available but a simple "tftp" - command will return without any error message which is quite confusing. - - Signed-off-by: Stefan Roese - -commit 384faaafb999cae3ce447c93e28a0b7e2e5fef53 -Author: Wolfgang Denk -Date: Tue Mar 4 17:38:50 2008 +0100 - - W7OLMC/W7OLMG: fix build problems (redundant #define) - - Signed-off-by: Wolfgang Denk - -commit f9301e1cda296245ba052d7b08321199c3d0af9d -Author: Wolfgang Denk -Date: Tue Mar 4 14:58:31 2008 +0100 - - Makefile: fix problem with out-of-tree builds introduced by 5013c09f - - Commit 5013c09f (Makefile: cleanup "clean" target) introduced a - problem for out-of-tree builds which caused "make clean" to fail. - - Signed-off-by: Wolfgang Denk - -commit dfece9500556bed5d8244b1c15d973cec7c25bfe -Author: Wolfgang Denk -Date: Tue Mar 4 11:58:26 2008 +0100 - - examples/Makefile: build "hello_world" on 8xx, too. - - Signed-off-by: Wolfgang Denk - -commit 74eb0222594fd23aafdf168e60e872814eea8b62 -Author: Mike Nuss -Date: Mon Mar 3 15:27:05 2008 -0500 - - PPC4xx (Sequoia): Fix Ethernet "remote fault" problems - - Every now and then a Sequoia board (or equivalent hardware) had - problems connecting to a Gigabit capable network interface. - - There were differences in the PHY setup between Linux and U-Boot. - - This patch fixes the problem. Apparently "remote fault" is being set, - which signals to some devices (on the other end of the cable) that a - fault has occurred, while other devices ignore it. I believe the RF bit - was causing the issue, but I removed T4 also, to match up with Linux. - - Signed-off-by: Mike Nuss - -commit 491fb6dea9f52fdb9cb5996e8e978b9e9685179f -Author: Timur Tabi -Date: Mon Mar 3 09:58:52 2008 -0600 - - fix QE firmware uploading limit - - Fix a typo in qe_upload_firmware() that prevented uploading firmware on - systems with more than one RISC core. - - Signed-off-by: Timur Tabi - -commit 42ba58e0c302b339a3c2faa6006a013c6f186b7a -Author: Bernhard Nemec -Date: Mon Mar 3 11:57:23 2008 +0000 - - Fix endianess problem in cramfs code (cramfs is always host-endian in Linux) - - Originally pointed out by Laurent Pinchart , - see http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/22846 - - Signed-off-by: Bernhard Nemec ganssloser.com> - -commit 84d0c2f1e39caff58bf765a7ab7c72da23c25ec8 -Author: Kim B. Heino -Date: Mon Mar 3 10:39:13 2008 +0200 - - fix copy from ram to dataflash - - If I try to "cp.b ", u-boot selects normal flash - routines instead of dataflash. This is because it checks "if source - address is not dataflash" instead of target address. - - Signed-off-by: Kim B. Heino - -commit 32bf3d143a888f8deacfdcc97e898f6c06d0aea4 -Author: Wolfgang Denk -Date: Mon Mar 3 12:16:44 2008 +0100 - - Fix quoting problem (preboot setting) in many board config files. - - Signed-off-by: Wolfgang Denk - -commit 5b0b2b6fc9fe22e3864c2a57316d91a2507ec215 -Author: Wolfgang Denk -Date: Mon Mar 3 12:36:49 2008 +0100 - - ADS5121: Fix default environment. - - Signed-off-by: Wolfgang Denk - -commit 91c82076ae492bb1f9d9c47a481314631d32dc8e -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Mar 2 16:12:31 2008 +0100 - - Makefile: Fix missing unconfig and mkconfig use - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 8ce4e5c2c02cb7e8adddf7b651d3050d81ce4c1d -Author: michael -Date: Sun Mar 2 23:33:46 2008 +0100 - - Fix checking fat32 cluster size. - - This fixes the cluster size tests in the FAT32 file system. - The current implementation of VFAT support doesn't work if the - referred cluster has an offset > 16bit representation, causing - "fatload" and "fatls" commands etc. to fail. - - Signed-off-by: michael trimarchi - -commit 661bad63a076a96c39c64f136915f146725af92b -Author: Wolfgang Denk -Date: Sun Mar 2 22:57:23 2008 +0100 - - Prepare v1.3.2-rc2 release candidate - - Signed-off-by: Wolfgang Denk - -commit 76957cb3d621bf664311908e5962e151c633c285 -Author: Stefan Roese -Date: Sat Mar 1 12:11:40 2008 +0100 - - ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1 - - The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But - currently 4k/2k is configured. This patch fixes this issue. - - Thanks to Thomas Kindler for pointing this out. - - Signed-off-by: Stefan Roese - -commit 118978c8eb43803e2794233922df4249fa278b83 -Author: Woodruff, Richard -Date: Fri Feb 29 17:34:35 2008 -0600 - - Fix alignment error on ARM for modules - - Fix alignment fault on ARM when running modules. With out an explicit - linker file gcc4.2.1 will half word align __bss_start's value. The word - dereference will crash hello_world. - - signed-off-by Richard Woodruff - -commit ce1120dd703e6f12c59e4eba9962356a0300b832 -Author: Dave Liu -Date: Fri Feb 29 17:45:31 2008 +0800 - - fs: Fix ext2 read issue - - The ext2 aligned process will corrupt the key - data struct, the patch fix this. - - Signed-off-by: Dave Liu - -commit 5013c09f7a5675952a3ca88b6bc6c924e63af33e -Author: Wolfgang Denk -Date: Sun Mar 2 22:45:33 2008 +0100 - - Makefile: cleanup "clean" target - - Make sure CDPATH settings cannot interfere. - Update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit ffda586fc1373243c9794babde69500f6293a8d8 -Author: Li Yang -Date: Fri Feb 29 11:46:05 2008 +0800 - - add cscope build target - - Add cscope build target to generate cscope database for code browsing. - - Signed-off-by: Li Yang - -commit f655adef65e4cf6b929054b049ee19ae9b5ccbe2 -Author: Kim Phillips -Date: Wed Feb 27 15:06:39 2008 -0600 - - net: uec_phy: handle 88e1111 rev.B2 erratum 5.6 - - erratum 5.6 states the autoneg completion bit is functional only if the - autoneg bit is asserted. - - This fixes any secondarily-issued networking commands on non-gigabit - links on the mpc8360 mds board. - - Signed-off-by: Kim Phillips - -commit 5f91db7f582ca17b1f19f10189c025696f333d2e -Author: John Rigby -Date: Tue Feb 26 09:38:14 2008 -0700 - - MPC5121e ADS PCI support take 3 - - Adds PCI support for MPC5121 - - Tested with drivers/net/rtl8139.c - - Support is conditional since PCI on old silicon does not work. - - ads5121_PCI_config turns on PCI - - In this version, condition compilation of PCI code has been moved - from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as - suggested by Jean-Christophe PLAGNIOL-VILLARD - - Signed-off-by: John Rigby - -commit 44b4dbed4133f657705b7c5193209da9978243a7 -Author: Anatolij Gustschin -Date: Mon Feb 25 23:53:07 2008 +0100 - - Fix warnings while compilation of post/drivers/memory.c - - Fix warnings while compilation with new gcc in eldk-4.2 - - Signed-off-by: Anatolij Gustschin - -commit 4fae35a53b3e958254d6574a1cc7e10811fc6726 -Author: Anatolij Gustschin -Date: Mon Feb 25 20:54:04 2008 +0100 - - ppc4xx: Fix problem in 4xx_enet.c driver - - U-Boot crashes in the net loop if CONFIG_4xx_DCACHE is - enabled. To reproduce the problem ensure that 'ethrotate' - environment variable isn't set to "no" and then run - "tftp 200000 not_existent_file". - This patch tries to fix the issue. - - Signed-off-by: Anatolij Gustschin - -commit 60ec654c5eb80d0fe0c38a3bd42140215bc06484 -Author: Anatolij Gustschin -Date: Mon Feb 25 20:04:20 2008 +0100 - - POST: Disable cache while SPR POST - - Currently (since commit b2e2142c) u-boot crashes on - sequoia board while SPR test if CONFIG_4xx_DCACHE is - enabled. This patch disables the cache while SPR test. - - Signed-off-by: Anatolij Gustschin - -commit c313b2c6c555e7d89ec59bd51c59ab164ad0105d -Author: Martin Krause -Date: Mon Feb 25 17:52:40 2008 +0100 - - TQM5200: use automatic fdt memory fixup (part 2) - - Call fdt_fixup_memory() on the boards TQM5200, TQM5200_B, TQM5200S, - TB5200 and TB5200_B to fixup the /memory node with the memory values - detected by U-Boot. - - Signed-off-by: Martin Krause - -commit 44ceec253ea941b301abf4b079d52324def69d92 -Author: Martin Krause -Date: Mon Feb 25 15:17:05 2008 +0100 - - TQM5200: use automatic fdt memory fixup - - Call fdt_fixup_memory() on the boards TQM5200, TQM5200_B, TQM5200S, - TB5200 and TB5200_B to fixup the /memory node with the memory values - detected by U-Boot. - - Signed-off-by: Martin Krause - -commit f3a329acb26017d8e10e9c93e1e726c2a5ac634a -Author: Martin Krause -Date: Mon Feb 25 13:27:52 2008 +0100 - - TQM5200: fix bug in SDRAM initialization code - - This patch fixes a bug in the SDRAM initialization code for the - TQM5200. The hi_addr bit is now set correctly. Without this patch - the hi_addr bit is always set to 1, if the second SDRAM bank is - not populated. - - For other MPC5200 boards a correspondig patch has already been applied - some time ago, see commit a63109281ad41b0fb489fdcb901171f76bcdbc2c. - - Signed-off-by: Martin Krause - -- - Forget the first patch please. I confused flash with SDRAM in - the comment ... - -commit 217bf6b6a313d9ccb619a4dbc09f73f77cd48df1 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Feb 25 00:03:12 2008 +0100 - - mx1fs2/flash: Fix multiple compiler warnings - - "pointer targets in assignment differ in signedness" - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 5599c28cef55be42a8ca6fa8086b1a44e56a85d2 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Feb 25 00:03:11 2008 +0100 - - arm-imx: Fix register definitions - - Sync register definitions with linux - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit c9bcf75fecc58886af77d2a571cff2eab39eab6f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Feb 25 00:03:10 2008 +0100 - - actua1/actua2/actua3: Fix multiple unused variable warnings - - - actua1: - actux1.c: In function 'checkboard': - actux1.c:92: warning: unused variable 'revision' - - - actua2: - actux2.c: In function 'checkboard': - actux2.c:100: warning: unused variable 's' - actux2.c:99: warning: unused variable 'revision' - actux2.c: In function 'reset_phy': - actux2.c:130: warning: unused variable 'i' - - - actua3: - actux3.c: In function 'checkboard': - actux3.c:114: warning: unused variable 'revision' - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit f8fa6368a6a0c02164da8e2f52f18d457c6977bd -Author: Shinya Kuribayashi -Date: Sun Feb 24 11:44:29 2008 +0900 - - Remove the __STRICT_ANSI__ check from the __u64/__s64 declaration on 32bit targets. - - The previous patch was lacking of i386, microblaze, nios and nios2. This - patch tries to fix them. - - Signed-off-by: Shinya Kuribayashi - -commit 05e07b1ea22844e946cfcf7d5e8a0199d18d2a95 -Author: Marian Balakowicz -Date: Fri Feb 29 22:22:46 2008 +0100 - - [new uImage] Fix FDT blob totalsize calculation in boot_relocate_fdt() - - Do not use global fdt blob pointer, calculate blob size from routine - argument blob pointer. - - Signed-off-by: Marian Balakowicz - -commit d1cc52879c8966507dad9fb575481e6d3985e64e -Author: David Gibson -Date: Tue Feb 12 00:58:31 2008 +1100 - - libfdt: Add and use a node iteration helper function. - - This patch adds an fdt_next_node() function which can be used to - iterate through nodes of the tree while keeping track of depth. This - function is used to simplify the iteration code in a lot of other - functions, and is also exported for use by library users. - - Signed-off-by: David Gibson - -commit 8cf30809a82902a471866d2f07725ce3b8a22291 -Author: Bartlomiej Sieka -Date: Fri Feb 29 16:00:24 2008 +0100 - - [new uImage] Add libfdt support to mkimage - - Signed-off-by: Bartlomiej Sieka - -commit a6e530f00d31a8494a0422799b2b9a692a9c0eb9 -Author: Bartlomiej Sieka -Date: Fri Feb 29 16:00:23 2008 +0100 - - [new uImage] Add sha1.o object to mkimage binary build - - Signed-off-by: Bartlomiej Sieka - -commit df6f1b895c997978f03afe04502ee76b7ba34ab9 -Author: Marian Balakowicz -Date: Fri Feb 29 16:00:06 2008 +0100 - - [new uImage] Fix component handling for legacy multi component images - - Use uint32_t when accessing size table in image_multi_count() and - image_multi_getimg() for multi component images. - - Add missing uimage_to_cpu() endianness conversion. - - Signed-off-by: Marian Balakowicz - -commit 570abb0ad120f6002bcaa3cf6f32bd4ca2e1b248 -Author: Marian Balakowicz -Date: Fri Feb 29 15:59:59 2008 +0100 - - [new uImage] Share common uImage code between mkimage and U-boot - - This patch adds the following common routines: - - 1) Dedicated mkimage print_header() is replaced with common - image_print_contents() - image_print_contents_noindent() - - 2) Common os/arch/type/comp fields name <--> id translation routines - genimg_get_os_name() - genimg_get_arch_name() - genimg_get_type_name() - genimg_get_comp_name() - genimg_get_os_id() - genimg_get_arch_id() - genimg_get_type_id() - genimg_get_comp_id() - - Signed-off-by: Marian Balakowicz - -commit 9a4daad0a35eb5143037eea9f786a3e9d672bdd6 -Author: Marian Balakowicz -Date: Fri Feb 29 14:58:34 2008 +0100 - - [new uImage] Update naming convention for bootm/uImage related code - - This patch introduces the following prefix convention for the - image format handling and bootm related code: - - genimg_ - dual format shared code - image_ - legacy uImage format specific code - fit_ - new uImage format specific code - boot_ - booting process related code - - Related routines are renamed and a few pieces of code are moved around and - re-grouped. - - Signed-off-by: Marian Balakowicz - -commit 75fa002c47171b73fb4c1f2c2fe4d6391c136276 -Author: Kumar Gala -Date: Wed Feb 27 21:51:51 2008 -0600 - - [new uImage] Respect autostart setting in linux bootm - - Signed-off-by: Kumar Gala - Acked-by: Marian Balakowicz - -commit d3f2fa0d278467b2232e4eb2372f905c3febfbeb -Author: Kumar Gala -Date: Wed Feb 27 21:51:50 2008 -0600 - - [new uImage] Provide ability to restrict region used for boot images - - Allow the user to set 'bootm_low' and 'bootm_size' env vars as a way - to restrict what memory range is used for bootm. - - Signed-off-by: Kumar Gala - Acked-by: Marian Balakowicz - -commit e822d7fc4dd4755d4d0a22f05e33f33d1a0481da -Author: Kumar Gala -Date: Wed Feb 27 21:51:49 2008 -0600 - - [new uImage] Use lmb for bootm allocations - - Convert generic ramdisk_high(), get_boot_cmdline(), get_boot_kbd() - functions over to using lmb for allocation of the ramdisk, command line - and kernel bd info. - - Convert PPC specific fdt_relocate() to use lmb for allocation of the device - tree. - - Provided a weak function that board code can call to do additional - lmb reserves if needed. - - Also introduce the concept of bootmap_base to specify the offset in - physical memory that the bootmap is located at. This is used for - allocations of the cmdline, kernel bd, and device tree as they should - be contained within bootmap_base and bootmap_base + CFG_BOOTMAPSZ. - - Signed-off-by: Kumar Gala - -commit f5614e7926863bf0225ec860d9b319741a9c4004 -Author: Kumar Gala -Date: Wed Feb 27 21:51:48 2008 -0600 - - [new uImage] Add autostart flag to bootm_headers structure - - The autostart env variable was dropped as part of the initial new uImage - cleanup. Add it back here so the arch specific code can decide if it - wants to really boot or not. - - Signed-off-by: Kumar Gala - Acked-by: Marian Balakowicz - -commit 4ed6552f715983bfc7d212c1199a1f796f1144ad -Author: Kumar Gala -Date: Wed Feb 27 21:51:47 2008 -0600 - - [new uImage] Introduce lmb from linux kernel for memory mgmt of boot images - - Introduce the LMB lib used on PPC in the kernel as a clean way to manage - the memory spaces used by various boot images and structures. This code - will allow us to simplify the code in bootm and its support functions. - - Signed-off-by: Kumar Gala - -commit 4648c2e7a173b0d7f17bef4adaa0623090c9e904 -Author: Kumar Gala -Date: Tue Feb 19 22:03:47 2008 -0600 - - [new uImage] ppc: Allow boards to specify effective amount of memory - - For historical reasons we limited the stack to 256M because some boards - could only map that much via BATS. However newer boards are capable of - mapping more memory (for example 85xx is capable of doing up to 2G). - - Signed-off-by: Kumar Gala - Acked-by: Marian Balakowicz - -commit 274cea2bddbca10cdad7daa518951b75c44ef6bc -Author: Kumar Gala -Date: Wed Feb 27 21:51:46 2008 -0600 - - [new uImage] rework error handling so common functions don't reset - - Changed image_get_ramdisk() to just return NULL on error and have - get_ramdisk() propogate that error to the caller. It's left to the - caller to call do_reset() if it wants to. - - Also moved calling do_reset() in get_fdt() and fdt_relocate() on ppc - to a common location. In the future we will change get_fdt() and - fdt_relocate() to return success/failure and not call do_reset() at all. - - Signed-off-by: Kumar Gala - Acked-by: Marian Balakowicz - -commit d2bc095a639672def11d5d043b5688d0dbd692ec -Author: Kumar Gala -Date: Wed Feb 27 21:51:45 2008 -0600 - - [new uImage] ppc: Re-order ramdisk/fdt handling sequence - - Doing the fdt before the ramdisk allows us to grow the fdt w/o concern - however it does mean we have to go in and fixup the initrd info since - we don't know where it will be. - - Signed-off-by: Kumar Gala - -commit 27953493ef025fb698d68c5dee39b36f01f4d530 -Author: Kumar Gala -Date: Wed Feb 27 21:51:44 2008 -0600 - - [new uImage] ppc: Determine if we are booting an OF style - - If we are bootin OF style than we can skip setting up some things - that are used for the old boot method. - - Signed-off-by: Kumar Gala - Acked-by: Marian Balakowicz - -commit a6612bdfe7ef37b9787b66800cf02aaded05fbeb -Author: Kumar Gala -Date: Wed Feb 27 21:51:43 2008 -0600 - - [new uImage] Don't pass kdb to ramdisk_high since we may not have one - - We don't actually need the kdb param as we are just using it to get - bd->bi_memsize which we can get from gd->bd->bi_memsize. Also, if we - boot via OF we might not actually fill out a kdb. - - Signed-off-by: Kumar Gala - Acked-by: Marian Balakowicz - -commit 2b22fa4baee51e6b467c44ea1be0d1ecd86e8775 -Author: Kumar Gala -Date: Wed Feb 27 16:30:47 2008 -0600 - - 85xx: Don't icbi when unlocking the cache - - There is no reason to icbi when invalidating the temporary stack in - the d-cache. Its impossible on e500 to have the i-cache contain - any addresses in the temp stack and it can be problematic in generating - transactions on the bus to non-valid addresses. - - Signed-off-by: Kumar Gala - -commit 534ea6b6f86f8b75ef2ac061ef110a98f103d7d6 -Author: Andy Fleming -Date: Wed Feb 27 15:50:50 2008 -0600 - - Fix source for ECM error IVPR - - The source vector for the ECM was being set to 2, - but that's what the source vector for DDR was being - set to. Change it to 1. - - Signed-off-by: Andy Fleming - -commit 21fae8b2b4e4e6e648796e07e20ab13e9cb18923 -Author: Andy Fleming -Date: Wed Feb 27 14:29:58 2008 -0600 - - Invalidate INIT_RAM TLB mappings - - Commit 0db37dc... (and some others) changed the INIT_RAM TLB - mappings to be unguarded. This collided with an existing "bug" - where the mappings for the INIT_RAM were being kept around. - This meant that speculative loads to those addresses were - succeeding in the TLB, and going out to the bus, where they - were causing an exception (there's nothing at that address). The - Flash code was coincidentally causing such a speculative load. - Rather than go back to mapping the INIT RAM as guarded, we fix - it so that the entries for the INIT_RAM are invalidated. Thus - the speculative loads will fail in the TLB, and have no effect. - - Signed-off-by: Andy Fleming - -commit 347b7938d3e561eb215aa386c37fb5acb5a383c6 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 17 22:56:17 2008 +0100 - - sbc8548: Fix Revision reading and unused variable 'path' - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 495d162374c472f46454453553382ad0735dc725 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 17 22:56:16 2008 +0100 - - sbc8548: Fix cfi flash bank declaration - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 4efbe9dbb129f857f27856936112c8c02f016be6 -Author: Marian Balakowicz -Date: Wed Feb 27 11:02:26 2008 +0100 - - [new uImage] Correct raw FDT blob handlig when CONFIG_FIT is disabled - - Dual format image code must properly handle all three FDT passing methods: - - raw FDT blob passed - - FDT blob embedded in the legacy uImage - - FDT blob embedded in the new uImage - - This patch enables proper raw FDT handling when no FIT imaeg support - is compiled in. This is a bit tricky as we must dected FIT format even - when FIT uImage handling is not enabled as both FIT uImages and raw FDT - blobs use tha same low level format (libfdt). - - Signed-off-by: Marian Balakowicz - -commit ff0734cff0fb5397ce2f4602f4f3e5ec9c8a36e8 -Author: Marian Balakowicz -Date: Wed Feb 27 11:02:26 2008 +0100 - - [new uImage] POWERPC: Add image_get_fdt() routine - - FDT blob may be passed either: (1) raw (2) or embedded in the legacy uImage - (3) or embedded in the new uImage. For the (2) case embedding image must be - verified before we get FDT from it. This patch factors out legacy image - specific verification routine to the separate helper routine. - - Signed-off-by: Marian Balakowicz - Acked-by: Kumar Gala - -commit 1efd43601f90de21ec6c0ebb9880823e822927b1 -Author: Marian Balakowicz -Date: Wed Feb 27 11:02:07 2008 +0100 - - [new uImage] Add image_get_kernel() routine - - Legacy image specific verification is factored out to a separate helper - routine to keep get_kernel() generic and simple. - - Signed-off-by: Marian Balakowicz - Acked-by: Kumar Gala - -commit 8a5ea3e6168fe6a2780eeaf257a3b19f30dec658 -Author: Marian Balakowicz -Date: Wed Feb 27 11:01:04 2008 +0100 - - [new uImage] Move image verify flag to bootm_headers structure - - Do not pass image verification flag directly to related routines. - Simplify argument passing and move it to the bootm_header structure which - contains curently processed image specific data and is already being passed - on the argument list. - - Signed-off-by: Marian Balakowicz - Acked-by: Kumar Gala - -commit 823afe7cefe00dafefc6696c1cc7aa828c394234 -Author: Marian Balakowicz -Date: Wed Feb 27 11:00:47 2008 +0100 - - [Makefile] Sort COBJS in lib_ Makefiles - - Signed-off-by: Marian Balakowicz - -commit 6f0f9dfc4ee880fbf400a2ebe14238181a6c3f91 -Author: Marian Balakowicz -Date: Wed Feb 27 11:00:47 2008 +0100 - - [new uImage] Optimize gen_get_image() flow control - - When CONFIG_HAS_DATAFLASH is not defined gen_get_image() routine has nothing - to do, update its control flow to better reflect that simple case. - - Signed-off-by: Marian Balakowicz - Acked-by: Kumar Gala - -commit d2ced9eb19ec74f4a359949dbe353427fa6d55ca -Author: Marian Balakowicz -Date: Mon Feb 4 08:28:17 2008 +0100 - - [new uImage] POWERPC: Split get_fdt() into get and relocate routines - - PPC specific FDT blob handling code is divided into two separate routines: - - get_fdt() - find and verify a FDT blob (either raw or image embedded) - fdt_relocate() - move FDT blob to within BOOTMAP if needed - - Signed-off-by: Marian Balakowicz - Acked-by: Kumar Gala - -commit 33fa5c0bfaf465de8ceb23fcd6b397f68b35a817 -Author: Jon Loeliger -Date: Mon Feb 25 13:13:37 2008 -0600 - - 86xx: Fix renamed GUR symbols in sbc8641d board. - - Back in commit a551cee99ad1d1da20fd23ad265de47448852f56 - (86xx: Fix GUR PCI config registers properly), we should have - changed the MPC86xx_PORBMSR_HA and MPC86xx_PORDEVSR_IO_SEL - symbols in the sbc8641d board as well. Fix this oversight. - - Signed-off-by: Jon Loeliger - -commit 64cd594e623c39f73964d18787763e4533f791f7 -Author: Stefan Roese -Date: Mon Feb 25 16:50:48 2008 +0100 - - ppc4xx: Fix acadia_nand build problem - - Don't include testdram() on NAND-booting target acadia_nand. This saves - a few bytes and makes the target build clean again. - - Signed-off-by: Stefan Roese - -commit 14e099e698d41e8179d05c2b2dbcf704a236f748 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 24 23:03:12 2008 +0000 - - mx1fs2/flash: Fix multiple pointertargets in assignment differ in signedness - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 724902c8464e610642b3a170278b99710325888e -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 24 23:03:11 2008 +0000 - - arm-imx: Fix registers definition - - Sync registers definition with linux - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 4cd288b589ea1178947c6e364453c32b3dede6b7 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 24 23:03:10 2008 +0000 - - actua1/actua2/actua3: Fix multipleunused variable - - - actua1: - actux1.c: In function 'checkboard': - actux1.c:92: warning: unused variable 'revision' - - - actua2: - actux2.c: In function 'checkboard': - actux2.c:100: warning: unused variable 's' - actux2.c:99: warning: unused variable 'revision' - actux2.c: In function 'reset_phy': - actux2.c:130: warning: unused variable 'i' - - - actua3: - actux3.c: In function 'checkboard': - actux3.c:114: warning: unused variable 'revision' - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit d5934ad7756f038a393a9cfab76a4fe306d9d930 -Author: Marian Balakowicz -Date: Mon Feb 4 08:28:09 2008 +0100 - - [new uImage] Add dual format uImage support framework - - This patch adds framework for dual format images. Format detection is added - and the bootm controll flow is updated to include cases for new FIT format - uImages. - - When the legacy (image_header based) format is detected appropriate - legacy specific handling is invoked. For the new (FIT based) format uImages - dual boot framework has a minial support, that will only print out a - corresponding debug messages. Implementation of the FIT specific handling will - be added in following patches. - - Signed-off-by: Marian Balakowicz - -commit b29661fc1151077776454288051bc9a488351ce8 -Author: Wolfgang Denk -Date: Sun Feb 24 15:21:36 2008 +0100 - - Coding style cleanup. Prepare v1.3.2-rc2 release candidate - - Signed-off-by: Wolfgang Denk - -commit 00b48a48424894daa589d166d73277830b1c6ac4 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Feb 23 12:15:56 2008 +0100 - - ENV: remove saveenv when CFG_ENV_IS_NOWHERE is selected - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit b075d74efb70ff68c49a2532f26b56d6703b69c1 -Author: Shinya Kuribayashi -Date: Sat Feb 23 17:24:16 2008 +0900 - - Remove the __STRICT_ANSI__ check from the __u64/__s64 declaration on 32bit targets. - - ---------------------------------------------------------------- - Olaf Hering [Wed, 17 Oct 2007 06:27:13 +0000 (23:27 -0700)] - - Remove the __STRICT_ANSI__ check from the __u64/__s64 declaration on - 32bit targets. - - GCC can be made to warn about usage of long long types with ISO C90 - (-ansi), but only with -pedantic. You can write this in a way that even - then it doesn't cause warnings, namely by: - - #ifdef __GNUC__ - __extension__ typedef __signed__ long long __s64; - __extension__ typedef unsigned long long __u64; - #endif - - The __extension__ keyword in front of this switches off any pedantic - warnings for this expression. - - Signed-off-by: Olaf Hering - Cc: - Signed-off-by: Andrew Morton - Signed-off-by: Linus Torvalds - ---------------------------------------------------------------- - - Signed-off-by: Shinya Kuribayashi - -commit 208acd112e6517b21fc30c420396902b103563ac -Author: Shinya Kuribayashi -Date: Sat Feb 23 17:07:57 2008 +0900 - - cpu/mcf52x2/config.mk: Make needlessly deffered expansions immediate. - - This will reduce the build time. - - Signed-off-by: Shinya Kuribayashi - -commit 495a0dde7fa1b14cdc15607d86503ec2bdcd02c4 -Author: Shinya Kuribayashi -Date: Sat Feb 23 17:05:00 2008 +0900 - - cpu/ppc4xx/config.mk: Make a needlessly deffered expansion immediate. - - This will reduce the build time. - - Signed-off-by: Shinya Kuribayashi - -commit e682ba399a1d76f09d8cc7af1e57066f1d360d91 -Author: Shinya Kuribayashi -Date: Sat Feb 23 16:58:41 2008 +0900 - - cpu/mips/cofigl.mk: Make a needlessly deffered expansion immediate. - - This reduces the build time by ~10%. Here's the gth2_config example. - - BEFORE AFTER - real 0m31.441s 0m27.833s - user 0m24.766s 0m23.045s - sys 0m10.425s 0m7.468s - - Signed-off-by: Shinya Kuribayashi - -commit 02409f8cf54c7cd91981f0dfec135dbf3858090c -Author: Marcel Moolenaar -Date: Fri Feb 22 10:48:07 2008 -0800 - - make define2mk.sed work on FreeBSD - - In the thread "[1.3.2-rc1] MPC8548CDS/MPC8555CDS configs fails to link", - the define2mk.sed script was identified as the source of the link - failure on FreeBSD. The problem is that sed(1) does not always support - the '+' operator. It isn't on FreeBSD. The attach patch implements the - equivalent, using the '*' operator instead and should work everywhere. - - Signed-off-by: Marcel Moolenaar - -commit e5084af8ded58453cd07ec1af8b0f29f34122bbc -Author: Detlev Zundel -Date: Fri Feb 22 17:21:32 2008 +0100 - - Replace deprecated "ramdisk" with "ramdisk_size" kernel parameter. - - The Linux commit fac8b209b1084bc85748bd54e13d00c1262b220f ("Remove - final traces of long-deprecated "ramdisk" kernel parm") makes these - changes neccessary. - - Signed-off-by: Detlev Zundel - -commit d01b847c5cd070895c4ba178c85cd068a95cf7cd -Author: Larry Johnson -Date: Thu Feb 21 13:58:16 2008 -0500 - - LM75 bug fix for negative temperatures - - When the LM75 temperature sensor measures a temperature below 0 C, the - current driver does not perform sign extension, so the result returned is - 256 C too high. This patch fixes the problem. - - Signed-off-by: Larry Johnson - -commit 5a910c224b13e413bda41922379add6d75c32da3 -Author: Heiko Schocher -Date: Thu Feb 21 18:33:45 2008 +0100 - - IDS8247: update MAINTAINER entry. - - Signed-off-by: Heiko Schocher - -commit 79eac2bfb591f2b028ec1735049dc91e4320de4a -Author: Heiko Schocher -Date: Thu Feb 21 18:31:15 2008 +0100 - - Fix device tree for mgsuvd board. - - Rename the "scc" node in "ethernet" for the mgsuvd board. - - Signed-off-by: Heiko Schocher - -commit 2e721094a70a52206af2e1bf1208d9a7131f6dad -Author: Yuri Tikhonov -Date: Thu Feb 21 14:23:42 2008 +0100 - - lwmon5: enable hardware watchdog - - Some boards (e.g. lwmon5) may use rather small watchdog intervals, so - causing it to reboot the board if U-Boot does a long busy-wait with - udelay(). Thus, for these boards we have to restart WD more - frequently. - - This patch splits the busy-wait udelay() into smaller, predefined, - intervals, so that the watchdog timer may be resetted with the - configurable (CONFIG_WD_PERIOD) interval. - - Signed-off-by: Yuri Tikhonov - -commit bc77881247ee6f95d7a9ebc499d26b96bae38c9d -Author: Anatolij Gustschin -Date: Thu Feb 21 12:52:29 2008 +0100 - - ppc4xx: Support for ATI Radeon 9200 card on sequoia - - Adds configuration option for ATI Radeon 9200 card - support to sequoia config file. If CONFIG_VIDEO - is enabled, TEXT_BASE should be changed to 0xFFF80000. - - Signed-off-by: Anatolij Gustschin - -commit 5a9abcc317cf3c8a69559ff83081f4e5d719edb7 -Author: Kumar Gala -Date: Mon Feb 18 08:18:07 2008 -0600 - - Remove duplicate defines for ARRAY_SIZE - - A few duplicate of the ARRAY_SIZE macro sneaked in since we put - the define in common.h. - - Signed-off-by: Kumar Gala - -commit 81d93e5c4b83d8b6dcee69de6f4a14ccf6f7114a -Author: Kumar Gala -Date: Mon Feb 18 08:09:37 2008 -0600 - - ppc: Allow boards to specify effective amount of memory - - For historical reasons we limited the stack to 256M because some boards - could only map that much via BATS. However newer boards are capable of - mapping more memory (for example 85xx is capable of doing up to 2G). - - Signed-off-by: Kumar Gala - -commit 755c35f54ba7eb7687aa7935e04a02a01ef1b27b -Author: Mike Frysinger -Date: Mon Feb 18 05:24:13 2008 -0500 - - include autoconf.mk before any other .mk files - - This bumps the autoconf.mk include step above board/cpu/arch/etc... so that - those .mk files can have make if statements based on the current config. - - Signed-off-by: Mike Frysinger - -commit 16fe77752eee099b9fb61ed73460e51cc94b37ba -Author: Mike Frysinger -Date: Mon Feb 18 05:10:07 2008 -0500 - - error check autoconf.mk generation - - If any of the steps for generating autoconf.mk fail currently, they go - unnoticed. To fix, we can simply add 'set -e' to the long list of commands. - This is simpler and more robust than placing '|| exit $$?' after every line. - - Signed-off-by: Mike Frysinger - -commit 019895a8dee71a9f00da05c03e379f45d581b0fe -Author: Stefano Babic -Date: Mon Feb 18 08:03:51 2008 +0100 - - Fix bug in dependency checking - - By adding VERSION_FILE to the PHONY targets the script - /tools/setlocalversion is always called and version_autogenerated.h - is replaced only if the script find a modified source file. - - Signed-off-by: Stefano Babic - -commit 98ba144ccc912eee90dd42699f023c497ce774c6 -Author: Kyungmin Park -Date: Mon Feb 18 14:35:43 2008 +0900 - - Fix GPMC CS2 memory setup at apollon - - It disables the current map first - - Signed-off-by: Kyungmin Park - -commit e845e07e1e6e64f40e35688439d3cdcf01cfff4f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 17 23:52:46 2008 +0100 - - uli526x: Fix multiple differ in signedness and parentheses around comparison - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit beeccf7a5dc5415c202e0132a33c58fc316c2a62 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 17 16:58:04 2008 +0100 - - MIPS: Fix CFG_NO_FLASH support - - - Fix flash_init call when CFG_NO_FLASH is used - - Remove no more needed flash.c for qemu-mips - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit edfed1d91df2b2670a812ca9d1a1f9faae7dba47 -Author: Mike Frysinger -Date: Sat Feb 16 02:40:18 2008 -0500 - - easylogo: clean up some more and add -r (rgb) support - - Michael Hennerich added support for outputting an image in RGB format rather - than forcing YUYV all the time. This makes obvious sense if the display you - have takes RGB input rather than YUYV. - - Rather than hack in support for options, I've converted it to use getopt and - cleaned up the argument parsing in the process. - - Signed-off-by: Michael Hennerich - Signed-off-by: Mike Frysinger - -commit f65c98129ccada3f7caf97d80395a95b84e911de -Author: Mike Frysinger -Date: Sat Feb 16 02:12:37 2008 -0500 - - Makefile: add target for $(LDSCRIPT) - - If the $(LDSCRIPT) does not exist (normally it's board/$(BOARD)/u-boot.lds), - then change into the board directory and try and create it. This allows you - to generate the linker script on the fly based upon board defines (like the - Blackfin boards do). - - There should be no regressions due to this change as the normal case is to - already have a u-boot.lds file. If that's the case, then there's nothing to - generate, and so make will always exit. The fix here is that if the linker - script does not exist, the implicit rules take over and attempt to guess how - to generate the file. - - Signed-off-by: Mike Frysinger - -commit 5583cbf736474ef754e128a54fb78632f57b48fd -Author: Marian Balakowicz -Date: Thu Feb 21 17:27:49 2008 +0100 - - [new uImage] Fix erroneous use of image_get_magic() in fdc/usb cmds - - Signed-off-by: Marian Balakowicz - -commit 2242f5369822bc7780db95c47985bb408ea9157b -Author: Marian Balakowicz -Date: Thu Feb 21 17:27:41 2008 +0100 - - [new uImage] Rename and move print_image_hdr() routine - - Signed-off-by: Marian Balakowicz - -commit f50433d670ec2ee9e96abac67cdc6e5e061a810d -Author: Marian Balakowicz -Date: Thu Feb 21 17:20:20 2008 +0100 - - [new uImage] Add fit_parse_conf() and fit_parse_subimage() routines - - Introducing routines for parsing new uImage format bootm arguments: - []# - configuration specification - []: - subimage specification - - New format images can contain multiple subimages of the same type. For example - a single new format image file can contain three kernels, two ramdisks and a - couple of FDT blobs. Subimage and configuration specifications are extensions - to bootm (and other image-related commands) arguments' syntax that allow to - specify which particular subimage should be operated on. - - Subimage specification is used to denote a particular subimage. Configurations - are a bit more complex -- they are used to define a particualr booting setup, - for example a (kernel, fdt blob) pair, or a (kernel, ramdisk, fdt blob) tuple, - etc. - - Signed-off-by: Marian Balakowicz - -commit fff888a1997ff7de9b29e24050fc4a0fd403ba16 -Author: Marian Balakowicz -Date: Thu Feb 21 17:20:19 2008 +0100 - - [new uImage] Add gen_get_image() routine - - This routine assures that image (whether legacy or FIT) is not - in a special dataflash storage. - - If image address is a dataflash address image is moved to system RAM. - - Signed-off-by: Marian Balakowicz - -commit 75d3e8fbd93c14d9929d024c75af2d742c76db70 -Author: Marian Balakowicz -Date: Thu Feb 21 17:20:18 2008 +0100 - - [new uImage] Pull in libfdt if CONFIG_FIT is enabled - - New uImage format (Flattened Image Tree) requires libfdt - functionality, print out error message if CONFIG_OF_LIBFDT - is not defined. - - New uImage support is enabled by defining CONFIG_FIT (and CONFIG_OF_LIBFDT). - This commit turns it on by default. - - Signed-off-by: Marian Balakowicz - -commit 1ba639da5604a64b3ed884a2cbb1c5414a9fa728 -Author: Michael Schwingen -Date: Mon Feb 18 23:16:35 2008 +0100 - - CFI: Do not use uninitialized cmd_reset - - Do not use uninitialized cmd_reset; issue both AMD and Intel reset - commands instead - - From a short test, it looks like AMD-style flash roms treat *any* unknown - command write as a reset, at least when in CFI Query mode, so issuing the - Intel reset command to AMD-style flashs seems safe (from the small sample I - have), plus the 3-cycle magic sequence should kick the state machine into - the right state even without a reset command. Since the AMD-style flashs - require the unlock sequence for real operation, I chose to try the AMD reset - command first, so that Intel flashs do no see an invalid command prior to - the CFI query. - - I have tested the patch on AM29LV320-style flashs from Fujitsu and Macronix, - plus Intel StrataFlash. - - Signed-off-by: Michael Schwingen - Signed-off-by: Stefan Roese - -commit e7a85f26830c9f2e78506421c2d519a2965bc7a1 -Author: Rafal Jaworowski -Date: Thu Feb 21 11:56:44 2008 +0100 - - API: Add (c) and licensing notice to the public API header. - - Signed-off-by: Rafal Jaworowski - -commit 928d1d77f8623c120d8763e20e1ca58df9c5c4c6 -Author: Yuri Tikhonov -Date: Thu Feb 21 11:06:07 2008 +0100 - - Fix CPU POST test failure - - The CPU POST test code (run from cpu_post_exec_31()) doesn't follow the - ABI carefully, at least the CR3, CR4, and CR5 fields of CR are clobbered - by it. The gcc-4.2 with its more aggressive optimization exposes this fact. - This patch just saves the CR value before running the test code, so allowing - it to do anything it wants with CR. - - Signed-off-by: Dmitry Rakhchev - Acked-by: Yuri Tikhonov - -- - -commit d5908b093955415f3d340706378b991f911af671 -Author: Jon Loeliger -Date: Wed Feb 20 15:26:51 2008 -0600 - - 8610HPCD: Document the flashbank selection switches. - - Signed-off-by: Jon Loeliger - -commit a551cee99ad1d1da20fd23ad265de47448852f56 -Author: Jon Loeliger -Date: Wed Feb 20 14:22:26 2008 -0600 - - 86xx: Fix GUR PCI config registers properly. - - Back in commit 975a083a5ef785c414b35f9c5b8ae25b26b41524 where - I tried to "8610HPCD: Fix typos in two PCI setup registers", I - botched it due to not realizing that 8610 and 8641 had different - Global Utility Register defintions, one of which was like 85xx, - and the other wasn't. Correct this problem by introducing two - symbols, one for each 86xx SoC, but neither of which is named - anything like 85xx. - - My bad. Lovely Wednesday with git bisect. You know. - - Signed-off-by: Jon Loeliger - -commit cb06eb961bdffc8728b38c242473d802e83ab2b4 -Author: Jon Loeliger -Date: Wed Feb 20 12:24:11 2008 -0600 - - 8610HPCD: Don't use VIDEO/CFB_CONSOLE by default. - - Without an actual supported video card hooked up, enabling - the CONFIG_VIDEO by default just makes it look broken by - routing all console output to the video card. Don't. - - Signed-off-by: Jon Loeliger - -commit 4d264eff4312f230776b913edade7ceb75f1b1e0 -Author: TsiChungLiew -Date: Wed Jan 30 15:08:15 2008 -0600 - - ColdFire: Fix missing code flash size for M5485EVB - - Signed-off-by: James Mahan - Signed-off-by: TsiChung Liew - -commit c54f9263e4e11e34b1e70c160bc467ef1d8ec59d -Author: TsiChungLiew -Date: Wed Jan 30 15:04:42 2008 -0600 - - ColdFire: Fix 5282 and 5271 interrupt mask bit - - Signed-off-by: TsiChung Liew - -commit 975a083a5ef785c414b35f9c5b8ae25b26b41524 -Author: Jon Loeliger -Date: Tue Feb 19 12:31:08 2008 -0600 - - 8610HPCD: Fix typos in two PCI setup registers. - - The two symbols MPC86xx_PORDEVSR_IO_SEL and MPC86xx_PORBMSR_HA - were erroneously present as 85xx names and values, leftover from - the clone wars. Fix this by removing the 85xx cruft from the - 86xx codebase. - - Signed-off-by: Jon Loeliger - -commit 13f5433f700d4da9f6fdf2a4bb80310133a7c170 -Author: Jon Loeliger -Date: Mon Feb 18 14:01:56 2008 -0600 - - 86xx: Convert sbc8641d to use libfdt. - - This is the proper fix for a missing closing brace in the function - ft_cpu_setup() noticed by joe.hamman embeddedspecialties.com. - The ft_cpu_setup() function in mpc8641hpcn.c should have been - removed earlier as it was under the obsolete CONFIG_OF_FLAT_TREE, - but was missed. Only, the sbc8641d was nominally still using it. - It all got ripped out, and the funcality that was in ft_board_setup() - was refactored to remove the CPU portions into the new file - cpu/mpc86xx/fdt.c instead. Make sbc8641d use this now. - - Based loosely on an original patch from joe.hamman@embeddedspecialties.com - - Signed-off-by: Jon Loeliger - -commit 04efddc87c50c84f85dad5c331c634a6ce830a83 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 17 23:35:31 2008 +0100 - - mpc86xx: Fix unused variable 'config' and 'immap' - - and remove useless CONFIG_DDR_INTERLEAVE - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 83d1b3876695c4f21faff2b731d9ef83f38ed208 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 17 23:03:36 2008 +0100 - - mpc86xx: Fix implicit declaration of functions 'init_laws' and 'disable_law' - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit b6f29c84c208a091f95a10cbc9852d729659ba20 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 17 14:15:31 2008 +0100 - - s3c24x0: Fix unused variable 'i' in function 'serial_init_dev' - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 0937b8d869fdb42d6ad4fe312958639bd62c973f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 17 14:15:32 2008 +0100 - - pxa: fix assignment from incompatible pointer type - - fix mmc_bread function prototype - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 64d792063fff90b8118179b092feee09fe5cae13 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 17 14:15:30 2008 +0100 - - at91cap9adk: fix implicit declaration of function 'eth_init' - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 375c4353db8f900f7ec772e26fab116ec00f7d3a -Author: Wolfgang Denk -Date: Sun Feb 17 15:43:44 2008 +0100 - - Remove files added by mistake, update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit b738654d3c84a30f2bfd9a8d7652ff20807c890c -Author: Mike Nuss -Date: Wed Feb 6 11:10:11 2008 -0500 - - PPC440EPx: Optionally enable second I2C bus - - The option CONFIG_I2C_MULTI_BUS does not have any effect on Sequoia, the - PPC440EPx reference platform, because IIC1 is never enabled. Add Sequoia board - code to turn on IIC1 if CONFIG_I2C_MULTI_BUS is selected. - - Signed-off-by: Mike Nuss - Cc: Stefan Roese - -commit ef5b4f221c22d05770878513951745f236b5b43f -Author: Niklaus Giger -Date: Tue Feb 5 10:26:44 2008 +0100 - - ppc4xx: HCU4/5. Cleanup configs - - - hcu4.h: Removed define of CONFIG_PPC405GPr - - Corrected phy addresses - - Fix boot variables - - Respect line length of 80 chars - - Signed-off-by: Niklaus Giger - -commit 74973126d1be63ac75bdc192f46234dca3a7c421 -Author: Niklaus Giger -Date: Tue Feb 5 11:31:28 2008 +0100 - - ppc4xx: HCU4/5. Cleanups - - - Fix some coding style violations. - - Use in/out_u16/32 where appropriate. - - Use register names from ppc405.h. - - Fix trace useage for Lauterbach. - - Remove obsolete generation HCU2. - - Renamed fixed_hcu4_sdram to init_ppc405_sdram. - - Signed-off-by: Niklaus Giger - -commit 8cc10d06b833ed917a19ad358c8ebbed8bc19555 -Author: Niklaus Giger -Date: Tue Feb 5 10:26:41 2008 +0100 - - ppc4xx: PPC405GPr fix missing register definitions - - Signed-off-by: Niklaus Giger - -commit 214398d9cb22268d9d4f7563359edca0f78297a2 -Author: Larry Johnson -Date: Fri Jan 18 21:49:05 2008 -0500 - - ppc4xx: Beautify configuration files for Sequoia and Korat boards - - Signed-off-by: Larry Johnson - -commit 30c6a241e88499f536e86d325759e29ba00ff67f -Author: Anatolij Gustschin -Date: Fri Feb 15 20:09:01 2008 +0100 - - Wipe out assembler warnings while compiling x86 biosemu - - This patch tries to get rid of some assembler warnings about - changed .got2 section type while compiling x86 bios emulator - code. - - Signed-off-by: Anatolij Gustschin - -commit 67a4389e39ad853d65b72e2b7cad15c7e8291147 -Author: Wolfgang Denk -Date: Fri Feb 15 00:57:09 2008 +0100 - - Prepare v1.3.2-rc1 release candidate - -commit f33e9653c9c09868995d788511d573771c209fe5 -Author: Anatolij Gustschin -Date: Fri Feb 15 00:13:20 2008 +0100 - - Fix compile warning on lib_ppc/board.c - - Signed-off-by: Anatolij Gustschin - -commit e5c6f9f8bec4dff9603419161e3a15cc8ad5d5f4 -Author: Anatolij Gustschin -Date: Thu Feb 14 18:22:04 2008 +0100 - - Add Radeon Mobility 9200 pci device id to the radeon driver - - This patch extends PCI device id table of the - radeon driver so that the driver will also support - Radeon Mobility 9200 (M9+) based boards. - - Signed-off-by: Anatolij Gustschin - -commit 1b8607e1f7143548c6062c28371449ec69588c00 -Author: Anatolij Gustschin -Date: Thu Feb 14 18:19:50 2008 +0100 - - Extend ATI Radeon driver to support more video modes - - Adds ATI Radeon 9200 support for 1280x1024, 1024x768, - 800x600, 640x480 at 24, 16 and 8 bpp. - - Signed-off-by: Anatolij Gustschin - -commit 4124382de029d361162a4b8cecc773eb8f26e2a8 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Feb 10 17:05:20 2008 +0100 - - xsengine: fix typo and few coding style - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 6f4abee789b6d9be3ec4b97ad48f509355559e9e -Author: Guennadi Liakhovetski -Date: Fri Feb 8 21:25:58 2008 +0100 - - Fix wrong memory limit calculation in memory-test - - If the length of the memory address range passed to the "mtest" command is - not of the form 2^x - 1, not all address lines are tested. This bug is - inherited from the original software at - http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C. Fix - this. - - Signed-off-by: Guennadi Liakhovetski - -commit 7e30f5eac7f07082a7ca77b7d91b944a8d0af6db -Author: Wolfgang Denk -Date: Fri Feb 15 00:11:39 2008 +0100 - - Coding STyle cleanup. - - Signed-off-by: Wolfgang Denk - -commit f6921e3dc331293c873ec4d109fd5517a42a90b3 -Author: Nobuhiro Iwamatsu -Date: Tue Feb 5 13:30:43 2008 +0900 - - sh: Fix register address of SH7722 - - The address of SH7722 is wrong by old document. - This patch fixes this problem. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 0ec7a061fb1c277f6afd73d61dd71bd21e7ef7b2 -Author: Mike Frysinger -Date: Mon Feb 4 17:44:23 2008 -0500 - - only update version header as needed - - Constantly rebuilding the version header will force useless relinking, so we - simply need to compare the new header with the existing one before updating - it. - - Signed-off-by: Mike Frysinger - -commit 208447f8e953f347425eb92c8e28d59e6d911363 -Author: Mike Frysinger -Date: Mon Jan 28 05:56:19 2008 -0500 - - Do not specify a CROSS_COMPILE default when executing size - - Signed-off-by: Mike Frysinger - -commit 1f780aa6f17a5d79791d69ec1d2f66d76ac45d8e -Author: Guennadi Liakhovetski -Date: Wed Feb 13 11:19:19 2008 +0100 - - Fix return value of mtest when CFG_ALT_MEMTEST set - - Fix a missing return statement from a non-void function. - - Signed-off-by: Guennadi Liakhovetski - -commit 943afa229cf5bf70ef917c7eb6bd0db59a1ba602 -Author: Timur Tabi -Date: Wed Jan 9 14:35:26 2008 -0600 - - 85xx, 86xx: Determine I2C clock frequencies and store in global_data - - Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx. - - Update the get_clocks() function in 85xx and 86xx to determine the I2C - clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk. - - Signed-off-by: Timur Tabi - -commit b931b3a9c3bdfaaeaa71e57a6026eec726005b08 -Author: Wolfgang Denk -Date: Thu Feb 14 23:18:01 2008 +0100 - - TQM834x: clean up configuration - - Get board name consistent with Linux and elsewhere; - get rid of local network definitions etc. - - Signed-off-by: Wolfgang Denk - -commit 38cc09c55b1d7f233789052c6fc462e5377669a9 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Thu Feb 14 08:02:12 2008 +0100 - - TFTP: fix search of ':' in BootFile - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 0bc9efada170096c6b273f19165e32936d330d80 -Author: Wolfgang Denk -Date: Thu Feb 14 22:46:55 2008 +0100 - - Coding style cleanup; update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit e7670f6c1e52ae6d2a43ff75a8bcfa7a5c86e47b -Author: Wolfgang Denk -Date: Thu Feb 14 22:43:22 2008 +0100 - - PPC: Use r2 instead of r29 as global data pointer - - R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc - will refuse to use load/store multiple insns; instead, it issues a - list of simple load/store instructions upon function entry and exit, - resulting in bigger code size, which in turn makes the build for a - few boards fail. - - Use r2 instead. - - Signed-off-by: Wolfgang Denk - -commit 3c234efa693bc59906c2be55c7918ecbb55392ea -Author: Uwe Kleine-König -Date: Wed Jan 30 09:08:49 2008 +0100 - - ARM: make the machid configurable via the environment - - If the variable "machid" exists, let do_bootm_linux use that instead - of bd->bi_arch_number. - - Signed-off-by: Uwe Kleine-König - -commit dd24058407c5add45cc60aec6c757ddc1a17e1b0 -Author: Vlad Lungu -Date: Wed Jan 23 16:34:46 2008 +0200 - - Use #ifdef CONFIG_FSLDMAFEC - - MCD_tasks.c lacks [subject] so compilation of mips targets (and more, probably) - fails - - Signed-off-by: Vlad Lungu - -commit 26c7bab81e08dc7bd696c48f753428a829629bd8 -Author: Shinya Kuribayashi -Date: Sat Jan 19 10:25:59 2008 +0900 - - common/miiphyutil.c: Cleanup MII_DEBUG and debug() - - Current MII_DEBUG is confusing in two ways. One is useless define-then- - undef at the top of the file. The other is there is only one debug() in - this file, and that doesn't seem worthwhile to bother having MII_DEBUG. - While there are many useful printf()/puts() debug codes, but they are for - DEBUG, not for MII_DEBUG. - - This patch tries to put them all together into MII_DEBUG and debug(). - - Signed-off-by: Shinya Kuribayashi - -commit 751b9b5189f3274b03c809172631316d6b002c82 -Author: Kyungmin Park -Date: Thu Jan 17 16:43:25 2008 +0900 - - OneNAND Initial Program Loader (IPL) support - - This patch enables the OneNAND boot within U-Boot. - Before this work, we used another OneNAND IPL called X-Loader based - on open source. With this work, we can build the oneboot.bin image - without other program. - - The build sequence is simple. - First, it compiles the u-boot.bin - Second, it compiles OneNAND IPL - Finally, it becomes the oneboot.bin from OneNAND IPL and u-boot.bin - The mechanism is similar with NAND boot except it boots from itself. - - Another thing is that you can only use the OneNAND IPL only to work - other bootloader such as RedBoot and so on. - - Signed-off-by: Kyungmin Park - -commit 21f6f9636f0e978397548751347425fbf8d42bb3 -Author: Andy Fleming -Date: Wed Jan 16 13:06:59 2008 -0600 - - Fix CONFIG_MMC usage in fat code - - A #if statement in fat.c depended on CONFIG_MMC, instead of - defined(CONFIG_MMC). This meant CONFIG_MMC needed to be defined - as "1" rather than just defined. Now it's better. - - Signed-off-by: Andy Fleming - -commit f57d7d364ce189e39b0a64338d2f8012c074a2bd -Author: Rafal Jaworowski -Date: Tue Jan 15 12:52:31 2008 +0100 - - ppc: Refactor cache routines, so there is only one common set. - - Signed-off-by: Rafal Jaworowski - -commit 3f2ac8f928c76cbd2374437b2d079f8b4324aaba -Author: Jon Loeliger -Date: Wed Jan 23 15:55:02 2008 -0600 - - 86xx: Fix compilation warning in sys_eprom.c - - sys_eeprom.c:82:9: warning: unknown escape sequence '\/' - - Signed-off-by: Jon Loeliger - -commit 65230107025733e89e28fd5e5cfd916d4953c28a -Author: Haavard Skinnemoen -Date: Fri Feb 22 11:40:50 2008 +0000 - - Move AT91RM9200DK board support under board/atmel - - We already have a vendor subdir for Atmel, so we should use it. - - Signed-off-by: Haavard Skinnemoen atmel.com> - -commit 6d0943a6be99977d6d853d51749e9963d68eb192 -Author: Andreas Engel -Date: Mon Jan 14 09:06:52 2008 +0000 - - ARM: cleanup duplicated exception handlingcode - - Move duplicated exception handling code into lib_arm. - - Signed-off-by: Andreas Engel - -commit ea8d989f4ef8203e1c0291e62435a8c62e3cfb29 -Author: Timo Tuunainen -Date: Fri Feb 1 10:09:03 2008 +0000 - - Support for Artila M-501 starter kit - - Kimmo Leppala / Sysart and - Timo Tuunainen / Sysart - -commit 9604b6e53ddae4fe00a488cbcd6b0e6cb344bccc -Author: Stelian Pop -Date: Mon Feb 11 10:50:19 2008 +0000 - - AT91CAP9 support - - --------------------------------- - - read_dataflash() takes a signed char pointer as a parameter. Silence a - few warnings dues to incorrect parameter types in env_dataflash.c. - - Signed-off-by: Stelian Pop - -commit 64e8a06af68cda174a8a06d0a61fce5e5bb189d7 -Author: Stelian Pop -Date: Thu Feb 7 09:42:57 2008 +0000 - - AT91CAP9 support : move board files to Atmel vendor directory. - - AT91CAP9 support : move at91cap9adk board files to Atmel vendor directory. - - Signed-off-by: Stelian Pop - -commit 7263ef191b87da94768f762c7093bedeb70db98f -Author: Stelian Pop -Date: Thu Jan 3 21:15:56 2008 +0000 - - AT91CAP9 support : MACB changes - - Signed-off-by: Stelian Pop popies.net> - Acked-by: Haavard Skinnemoen atmel.com> - -commit 6afcabf11d7321850f4feaadfee841488ace54c5 -Author: Stelian Pop -Date: Thu Feb 7 16:37:54 2008 +0000 - - AT91CAP9 support : board/ files - - Signed-off-by: Stelian Pop - -commit fefb6c10928caa9e71335cad64dcb65c83fce8ab -Author: Stelian Pop -Date: Wed Jan 30 21:15:54 2008 +0000 - - AT91CAP9 support : cpu/ files - - Signed-off-by: Stelian Pop popies.net> - -commit fa506a926cec348805143576c941f8e61b333cc0 -Author: Stelian Pop -Date: Thu Jan 31 21:15:53 2008 +0000 - - AT91CAP9 support : include/ files - - Signed-off-by: Stelian Pop - -commit 20b197c6f2799af399a68f96a1aff543a75621b8 -Author: Stelian Pop -Date: Sun Jan 20 19:49:21 2008 +0000 - - AT91CAP9 support : build integration - - Signed-off-by: Stelian Pop - -commit d49fe4bed5b69ec910909d1bd62da23ecd8801fd -Author: Stelian Pop -Date: Sun Jan 20 21:07:00 2008 +0000 - - Improve DataFlash CS definition. - - Use a structure instead of the error prone unnamed array to - define the possible dataflash banks. - - Signed-off-by: Stelian Pop - -commit a6cdd21b56014208706238712a853a9e9a0a2290 -Author: Stelian Pop -Date: Sat Jan 19 21:09:35 2008 +0000 - - Fix arm926ejs compile when SKIP_LOWLEVEL_INIT is on - - Fix arm926ejs compile when SKIP_LOWLEVEL_INIT is on. - - cpu/arm926ejs/start.o: In function `cpu_init_crit': - .../cpu/arm926ejs/start.S:227: undefined reference to `lowlevel_init' - - Signed-off-by: Stelian Pop - -commit ea686f52e45b3df2938866d3f5a98bb2556dfe2b -Author: Peter Pearse -Date: Fri Feb 1 16:50:24 2008 +0000 - - Fix timer overflow in DaVinci - Signed-off-by: Dirk Behme - -commit f4e7cbfcb0fcbc325a2bcfea7e00e3dd37f93846 -Author: Peter Pearse -Date: Fri Feb 1 16:49:08 2008 +0000 - - Update board NetStar - Signed-off-by: Ladislav Michl - -commit b7f6193e76651e1fd606e46eb11915b53cb6618b -Author: Niklaus Giger -Date: Tue Feb 5 10:26:42 2008 +0100 - - ppc4xx: HCU4/5. Fix make O=../xx - - Signed-off-by: Niklaus Giger - -commit 29e3500cbc43c89eff6e720ca83e375deeecd9b3 -Author: Larry Johnson -Date: Tue Jan 22 08:51:59 2008 -0500 - - ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code - - Signed-off-by: Larry Johnson - -commit fe891ecf4d187e9d11dde869ed4623af52b54451 -Author: Hiroshi Ito -Date: Thu Jan 31 18:35:04 2008 +0900 - - NFS Timeout with large files. - - Retry to send NFS packet before reaching timeout. - - Signed-off-by: Hiroshi Ito - -commit 88f72527f5b89c0905ad5c36cc2ef8d29dd6bbf0 -Author: Johannes Stezenbach -Date: Tue Jan 29 00:11:25 2008 +0100 - - Add dependencies to avoid race conditions with parallel make. - - Signed-off-by: Johannes Stezenbach - -commit 6d1b6f9f89c815eaca44acff8e73ece7181f61b6 -Author: Mike Frysinger -Date: Mon Jan 28 05:46:01 2008 -0500 - - Mark board_init_[fr] as noreturn - - Signed-off-by: Mike Frysinger - -commit 161b2af4d7b48fd602ce333c355a4df0337892bb -Author: Mike Frysinger -Date: Mon Jan 28 05:28:50 2008 -0500 - - Only use TEXT_BASE if defined by the board - - Signed-off-by: Mike Frysinger - -commit 1b769881750030f10743808b9d6013e11f559350 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Jan 25 07:54:47 2008 +0100 - - Fix remaining CONFIG_COMMANDS - - update comments - Fix coding style - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 0c9d42e6b0b83d507335a291e3ea99240038f4b9 -Author: Niklaus Giger -Date: Mon Jan 21 16:46:00 2008 +0100 - - Add *~ to .gitignore - - One should never add a backup file ending in with ~ to the git repository. - - Signed-off-by: Niklaus Giger - -commit 3cfb0c51b2bb5ede54eca85ace5b1ba12be314b0 -Author: Kumar Gala -Date: Thu Jan 17 00:02:10 2008 -0600 - - Remove duplicate defines for ARRAY_SIZE - - Signed-off-by: Kumar Gala - -commit c77ce474b1c57b13e9d36d9830f147966c143694 -Author: Stelian Pop -Date: Mon Jan 14 22:08:14 2008 +0100 - - Fix incorrect address test in AT91F_DataflashSelect(). - - Signed-off-by: Stelian Pop - -commit d9ad115bbf7bb0842de7dbd2502b7e430f83cc3d -Author: Kumar Gala -Date: Wed Feb 13 15:09:58 2008 -0600 - - Fix building of fdt_support.c if DEBUG set - - Signed-off-by: Kumar Gala - -commit ccd6e1464e5396bc1a9aebf7077ddf4342eafe03 -Author: Jon Loeliger -Date: Tue Feb 12 14:53:28 2008 -0600 - - Add CFG_MPC86xx_DDR_ADDR and CFG_MPC86xx_DDR2_ADDR symbols - - These replace direct structure references for IMMR sections. - - Signed-off-by: Jon Loeliger - -commit c62776be8dca4097ca03d4f9415f08d4887b45d0 -Author: Wolfgang Denk -Date: Tue Feb 12 00:45:06 2008 +0100 - - Get rid of "#undef DEBUG" from board config files. - - Signed-off-by: Wolfgang Denk - -commit 73bf1e2de7862bcdbd5a9f993b3e84b67c8ea9c8 -Author: Timur Tabi -Date: Tue Jan 15 17:09:41 2008 -0600 - - Remove #undef DEBUG from MPC83xx board header files - - Remove the "#undef DEBUG" line from all Freescale 83xx board header files. - The inclusion of this line makes it impossible to enable debug code in - other source files, because "#define DEBUG" typically needs to be defined - before any header files are included. - - Signed-off-by: Timur Tabi - -commit 69018ce2e086e9caf35b914d675b82bc4888f077 -Author: Kumar Gala -Date: Thu Jan 17 08:25:45 2008 -0600 - - QE: Move FDT support into a common file - - Move the flat device tree setup for QE related devices into - a common file shared between 83xx & 85xx platforms that have QE's. - - Signed-off-by: Kumar Gala - -commit 5cf746c303710329f8040d9c62ee354313e3e91f -Author: Marian Balakowicz -Date: Thu Jan 31 13:59:09 2008 +0100 - - [new uImage] Move kernel data find code to get_kernel() routine - - Verification of the kernel image (in old format) and finding kernel - data is moved to a dedicated routine. The routine will also hold - support for, to be added, new image format. - - Signed-off-by: Marian Balakowicz - -commit 7b325454fd231d4273de3fe373850f777fb086bf -Author: Marian Balakowicz -Date: Thu Jan 31 13:58:20 2008 +0100 - - [new uImage] Cleanup FDT handling in PPC do_boot_linux() - - Move FDT blob finding and relocation to a dedicated - get_fdt() routine. It increases code readability and - will make adding support for new uImage format easier. - - Signed-off-by: Marian Balakowicz - -commit b6b0fe6460b7063ac60b9a3531ef210aedb31451 -Author: Marian Balakowicz -Date: Thu Jan 31 13:58:13 2008 +0100 - - [new uImage] Cleanup do_botm_linux() boot allocations - - This patch moves common pre-boot allocation steps shared between PPC - and M68K to a helper routines: - - common: - - get_boot_sp_limit() - - get_boot_cmline() - - get_boot_kbd() - - platform: - - set_clocks_in_mhz() - - Signed-off-by: Marian Balakowicz - -commit ceaed2b1e54ebf14d600e02fef016c8df5cc4d40 -Author: Marian Balakowicz -Date: Thu Jan 31 13:57:17 2008 +0100 - - [new uImage] Move ramdisk loading to a common routine - - Ramdisk loading code, including initrd_high variable handling, - was duplicated for PPC and M68K platforms. This patch creates - common helper routine that is being called from both platform - do_bootm_linux() routines. - - Signed-off-by: Marian Balakowicz - -commit 68d4f05e6b2383a442fb71f80f2a9fbb3d8def68 -Author: Marian Balakowicz -Date: Thu Jan 31 13:55:53 2008 +0100 - - [new uImage] Removed dead ramdisk code on microblaze architectures - - Microblaze do_bootm_linux() includes ramdisk processing code but - the ramdisk does not get used anywhere later on. - - Signed-off-by: Marian Balakowicz - -commit 5ad03eb3854c162684222a718b44c0716ea0db03 -Author: Marian Balakowicz -Date: Thu Jan 31 13:55:39 2008 +0100 - - [new uImage] Factor out common image_get_ramdisk() routine - - Architecture specific do_bootm_linux() routines share common - ramdisk image processing code. Move this code to a common - helper routine. - - Signed-off-by: Marian Balakowicz - -commit d3c5eb6dd1f4ed3c3388386cf1d1bf82aa51d56b -Author: Marian Balakowicz -Date: Thu Jan 31 13:20:08 2008 +0100 - - [new uImage] Move FDT error printing to common fdt_error() routine - - FDT error handling in PPC do_bootm_linux() shares the same message format. - This patch moves error message printing to a helper fdt_error() routine. - - Signed-off-by: Marian Balakowicz - Acked-by: Gerald Van Baren - -commit 42b73e8ee00d48004791dea64b8093fb974c57e1 -Author: Marian Balakowicz -Date: Thu Jan 31 13:20:07 2008 +0100 - - [new uImage] Factor out common routines for getting os/arch/type/comp names - - Move numeric-id to name translation for image os/arch/type/comp header - fields to a helper routines: image_get_os_name(), image_get_arch_name(), - image_get_type_name(), image_get_comp_name(). - - Signed-off-by: Marian Balakowicz - -commit e99c26694a384221d336f6448c06a57479c0baa4 -Author: Marian Balakowicz -Date: Thu Jan 31 13:20:07 2008 +0100 - - [new uImage] Remove standalone applications handling from boootm - - Standalone applications are supposed to be run using the "go" command. - This patch removes standalone images handling from the do_bootm(). - - Signed-off-by: Marian Balakowicz - -commit 4a2ad5ff6400698433dd7203d34939c3c9cc9bff -Author: Marian Balakowicz -Date: Thu Jan 31 13:20:07 2008 +0100 - - [new uImage] Remove OF_FLAT_TREE support from PPC bootm code - - Support for OF_FLAT_TREE is to be obsoleted in the near future, - remove related code from the bootm routines. - - Signed-off-by: Marian Balakowicz - -commit 82850f3d32a2661868ec6876bed7a22c55cef718 -Author: Marian Balakowicz -Date: Thu Jan 31 13:20:06 2008 +0100 - - [new uImage] Use image API in SH do_bootm_linux() routine - - Introduce image handling API for lately added Hitachi SH architecture. - - Signed-off-by: Marian Balakowicz - -commit 4a995edec1ac163d9326d143ffe2b47e7543407f -Author: Marian Balakowicz -Date: Thu Jan 31 13:20:06 2008 +0100 - - [new uImage] Rename architecture specific bootm code files - - Implementation of the do_bootm_linux() and other bootm helper routines is - architecture specific code. As such it resides in lib_ directories - in files named _linux.c - - This patch renames those files to a more clear and accurate - lib_/bootm.c form. - - List of the renamed files: - lib_arm/armlinux.c -> lib_arm/bootm.c - lib_avr32/avr32_linux.c -> lib_avr32/bootm.c - lib_blackfin/bf533_linux.c -> lib_blackfin/bootm.c - lib_i386/i386_linux.c -> lib_i386/bootm.c - lib_m68k/m68k_linux.c -> lib_m68k/bootm.c - lib_microblaze/microblaze_linux.c -> lib_microblaze/bootm.c - lib_mips/mips_linux.c -> lib_mips/bootm.c - lib_nios/nios_linux.c -> lib_nios/bootm.c - lib_nios2/nios_linux.c -> lib_nios2/bootm.c - lib_ppc/ppc_linux.c -> lib_ppc/bootm.c - lib_sh/sh_linux.c -> lib_sh/bootm.c - - Signed-off-by: Marian Balakowicz - -commit 7582438c285bf0cef82909d0f232de64ec567a8a -Author: Marian Balakowicz -Date: Thu Jan 31 13:20:06 2008 +0100 - - [new uImage] Return error on image move/uncompress overwrites - - Check for overwrites during image move/uncompress, return with error - when the original image gets corrupted. Report clear message to the user - and prevent further troubles when pointer to the corrupted images is passed - to do_bootm_linux routine. - - Signed-off-by: Marian Balakowicz - -commit f13e7b2e993c61fed1f607962501e051940d6e80 -Author: Marian Balakowicz -Date: Tue Jan 8 18:12:17 2008 +0100 - - [new uImage] Cleanup image header pointer use in bootm code - - - use single image header pointer instead of a set of auxilliary variables. - - add multi component image helper routines: get component size/data address - - Signed-off-by: Marian Balakowicz - -commit 1ee1180b6e93e56d0282ac8d943e448e9d0eab20 -Author: Marian Balakowicz -Date: Tue Jan 8 18:17:10 2008 +0100 - - [new uImage] Cleanup cmd_bootm.c - - - sort and cleanup headers, declarations, etc. - - group related routines - - cleanup indentation, white spaces - - Signed-off-by: Marian Balakowicz - -commit af13cdbc01eaf88880978bfb4f603e012818ba24 -Author: Marian Balakowicz -Date: Tue Jan 8 18:11:45 2008 +0100 - - [new uImage] Add memmove_wd() common routine - - Move common, watchdog sensible memmove code to a helper memmmove_wd() routine. - - Signed-off-by: Marian Balakowicz - -commit 958fc48abddeab513ea4847e34f22a2e9fe67fe1 -Author: Marian Balakowicz -Date: Tue Jan 8 18:11:44 2008 +0100 - - [new uImage] Fix FDT header verification in PPC do_boot_linux() routine - - Signed-off-by: Marian Balakowicz - -commit 15158971f49255ccef54f0979a942cfd3de2ae52 -Author: Marian Balakowicz -Date: Tue Jan 8 18:11:44 2008 +0100 - - [new uImage] Fix uImage header pointer use in i386 do_bootm_linux() - - Use image header copy instead of a (possibly corrupted) pointer to - a initial image location. - - Signed-off-by: Marian Balakowicz - -commit 261dcf4624b25f3c551efcf8634e9194fabba9c3 -Author: Marian Balakowicz -Date: Tue Jan 8 18:11:44 2008 +0100 - - [new uImage] Remove I386 uImage fake_header() routine - - I386 targets are not using a uImage format, instead fake header - is added to ram image before it is further processed by bootm. - - Remove this fixup and force proper uImage use for I386. - - Signed-off-by: Marian Balakowicz - -commit 559316faf7eae0614c91d77f509b57d6c4c091ba -Author: Marian Balakowicz -Date: Tue Jan 8 18:11:44 2008 +0100 - - [new uImage] Move CHUNKSZ definition to image.h - - CHUNKSZ defined for PPC and M68K is set to the same value of 64K, - move this definition to a common header. - - Signed-off-by: Marian Balakowicz - -commit 321359f20823e0b8c5ad38b64d007a6c48cda16e -Author: Marian Balakowicz -Date: Tue Jan 8 18:11:43 2008 +0100 - - [new uImage] Move gunzip() common code to common/gunzip.c - - Move gunzip(), zalloc() and zfree() to a separate file. - Share zalloc() and zfree() with cramfs uncompress routine. - - Signed-off-by: Marian Balakowicz - -commit d45d5a18b6b36688f2365623f9d550566c664b5b -Author: Marian Balakowicz -Date: Tue Jan 8 18:11:43 2008 +0100 - - [new uImage] Cleanup OF/FDT #if/#elif/#endif use in do_bootm_linux() - - Make CONFIG_OF_LIBFDT and CONFIG_OF_FLAT_TREE use more - readable in PPC variant of do_bootm_linux() routine. - - Signed-off-by: Marian Balakowicz - -commit 5d3cc55ecbae277e08f5ff771da20b1d6a36ec36 -Author: Marian Balakowicz -Date: Tue Jan 8 18:11:43 2008 +0100 - - [new uImage] Move PPC do_bootm_linux() to lib_ppc/ppc_linux.c - - PPC implementation of do_bootm_linux() routine is moved to - a dedicated file lib_ppc/ppc_linux.c - - Signed-off-by: Marian Balakowicz - -commit b97a2a0a21f279d66de8a9bdbfe21920968bcb1c -Author: Marian Balakowicz -Date: Tue Jan 8 18:14:09 2008 +0100 - - [new uImage] Define a API for image handling operations - - - Add inline helper macros for basic header processing - - Move common non inline code common/image.c - - Replace direct header access with the API routines - - Rename IH_CPU_* to IH_ARCH_* - - Signed-off-by: Marian Balakowicz - -commit ed29bc4e8142b46b626f67524207b36e43d9aad6 -Author: Marian Balakowicz -Date: Thu Jan 31 13:19:58 2008 +0100 - - Add missing cmd_ximg.o to common/Makefile - - Signed-off-by: Marian Balakowicz - -commit 37e3c62fa07a823e7569c872e3a9395d227ed8e3 -Author: Grzegorz Bernacki -Date: Mon Jan 28 10:15:02 2008 +0100 - - ADS5121e: DDR2 init/timing update. - - Signed-off-by: John Rigby - Signed-off-by: Grzegorz Bernacki - -commit ac9152830d7fdebace8a260b7737ef2870c21ca0 -Author: John Rigby -Date: Wed Jan 30 13:36:57 2008 -0700 - - Device tree updates - - Changes to match 5121 device tree going mainline in 2.6.25. - - Change OF_SOC from "soc5121" to plain "soc". - Remove unneeded "ref-frequency" fixups. - Remove "address" enetaddr fixup. - - Add bus-frequency fixup for old OF_SOC so old - kernels with old device trees will work with new - u-boot with 66MHz IPS clock - - Signed-off-by: John Rigby - -commit de55d18df3ff2ea614624e74793de7c43520e0e7 -Author: John Rigby -Date: Wed Jan 30 13:36:56 2008 -0700 - - Change IPS freq to 66MHz - - Recommended frequency is 66MHz - Change divider from 4 to 3. - - Signed-off-by: John Rigby - -commit cd9cb62f9d8b78d6c3af5d1e9b5a3d68a3d73974 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Jan 14 22:38:55 2008 +0100 - - xsengine: rename board_post_init to board_late_init - - missing migration from "Cleanup of some init functions" - in c837dcb1a316745092567bfe4fb266d0941884ff - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 8dafa87476b0d7170e219c2f5e3842c833a91807 -Author: Larry Johnson -Date: Sat Jan 12 23:35:33 2008 -0500 - - Add attribute POST_PREREL to ECC memory POST - - Signed-off-by: Larry Johnson - -commit ed2cf548cac80cd3cf8154dcfe7b2685bef45938 -Author: Kumar Gala -Date: Thu Jan 17 08:25:45 2008 -0600 - - QE: Move FDT support into a common file - - Move the flat device tree setup for QE related devices into - a common file shared between 83xx & 85xx platforms that have QE's. - - Signed-off-by: Kumar Gala - -commit d38da537943cd36356b9d3d9d9b60533554b81d8 -Author: Haavard Skinnemoen -Date: Wed Jan 23 17:20:14 2008 +0100 - - AVR32: Make SDRAM refresh rate configurable - - The existing code assumes the SDRAM row refresh period should always - be 15.6 us. This is not always true, and indeed on the ATNGW100, the - refresh rate should really be 7.81 us. - - Add a refresh_period member to struct sdram_info and initialize it - properly for both ATSTK1000 and ATNGW100. Out-of-tree boards will - panic() until the refresh_period member is updated properly. - - Big thanks to Gerhard Berghofer for pointing out this issue. - - Signed-off-by: Haavard Skinnemoen - -commit 61151cccb660cdb06a07fb283de6089913d7bde0 -Author: Haavard Skinnemoen -Date: Thu Apr 19 10:10:11 2007 +0200 - - ATSTK1000: Fix potential flash programming bug - - The (now obsolete) atngw100 flash programming code was having problems - programming the onboard at49bv642 chip. The atstk1000 flash - programming code may have the same bug, so import fix for this problem - from the AVR32 Linux BSP. - - Signed-off-by: Haavard Skinnemoen - -commit b2e1d5b64469f10dfcce27f7b0afd935684a8e11 -Author: Haavard Skinnemoen -Date: Thu Nov 22 17:04:13 2007 +0100 - - ATSTK1004: Fix comment about default load address - - The default load address is SDRAM + 2MB, not SDRAM + 4MB. The latter - wouldn't have worked anyway since the board can only access 4MB of - SDRAM. - - Signed-off-by: Haavard Skinnemoen - -commit 8269ab53608d8db2aa06969c337ab0b0518211e5 -Author: Haavard Skinnemoen -Date: Thu Nov 22 17:01:24 2007 +0100 - - ATSTK1002: Use SDRAM + 4MB as default load address - - Many people run into problems when they compile a big kernel and load - the uImage at the default SDRAM + 2MB address as the kernel will - overwrite the uImage as it is being unpacked. Increase the default - load address so that we can load a 4MB kernel image without any - problems. - - Signed-off-by: Haavard Skinnemoen - -commit 2bcacc2d841b77f3d2d3910db722003742727e9f -Author: Haavard Skinnemoen -Date: Thu Nov 22 16:51:39 2007 +0100 - - ATNGW100: Fix default mtest range - - Let mtest cover the whole SDRAM except the last megabyte, which is - where u-boot lives. - - Signed-off-by: Haavard Skinnemoen - -commit 9856a6b3104e0bc210b0868dfe691c52bf03c227 -Author: Nobuhiro Iwamatsu -Date: Tue Jan 22 15:31:56 2008 +0900 - - sh: Fix register address of SH7722. - - The address of SH7722 is wrong by old document. - This patch fixes this problem. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 30942b18b66f35f2ceedab39af10e9eccaa943cc -Author: Mike Frysinger -Date: Mon Feb 4 19:26:57 2008 -0500 - - new command for displaying strings at specified memory locations - - Signed-off-by: Mike Frysinger - -commit b58d8b48e25b0c866d167cc577f118f528cd9e0a -Author: Mike Frysinger -Date: Mon Feb 4 19:26:57 2008 -0500 - - rewrite/cleanup Blackfin RTC driver - - Signed-off-by: Mike Frysinger - -commit 94a91e248b71c3ff951fc27cff6909e82ca37d15 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:57 2008 -0500 - - generate u-boot.ldr for Blackfin targets - - Signed-off-by: Mike Frysinger - -commit b779f7a59530436040f157f7841db7ab796542df -Author: Mike Frysinger -Date: Mon Feb 4 19:26:57 2008 -0500 - - scrub unused symbols - - Signed-off-by: Mike Frysinger - -commit cc2977acc3bbbb7850f16645dd1081f95335868d -Author: Mike Frysinger -Date: Mon Feb 4 19:26:57 2008 -0500 - - move Blackfin cpu object list to respective cpu directories - - Signed-off-by: Mike Frysinger - -commit d0b01a246d0a351bc7dce1d0c9cf6aebdf6d7505 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:57 2008 -0500 - - interface to Blackfin on-chip One-Time-Programmable memory - - Signed-off-by: Mike Frysinger - -commit 4c727c77e43872d3a1d1f76a949fcb3f26a38788 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:56 2008 -0500 - - add support for memory commands with Blackfin L1 instruction memory - - Signed-off-by: Mike Frysinger - -commit 6b9097e5e7490aa7b828c6f1a1c7a0e875df8464 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:56 2008 -0500 - - use C code rather than inline assembly - - Signed-off-by: Mike Frysinger - -commit 97c26e006d2fa6d4e1560933ee6f385d8b8908b9 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:56 2008 -0500 - - add Blackfin-specific reginfo command - - Signed-off-by: Mike Frysinger - -commit 0858b835e7ea501ea084d34cef75932f098342bb -Author: Mike Frysinger -Date: Mon Feb 4 19:26:55 2008 -0500 - - add support for Blackfin symbol prefixes to examples - - Signed-off-by: Mike Frysinger - -commit 8dc48d71a4be753ea9f84956cd33600de35fad04 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:55 2008 -0500 - - add Blackfin-specific bdinfo command - - Signed-off-by: Mike Frysinger - -commit 0003613e3c7df3b84b2cb92e797d77f46f15a43a -Author: Mike Frysinger -Date: Mon Feb 4 19:26:55 2008 -0500 - - move -ffixed-P5 to blackfin_config.mk and drop unused -D__BLACKFIN__ - - Signed-off-by: Mike Frysinger - -commit 60fa72d65610c7ef33e1d6db858979d05ff0df58 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:55 2008 -0500 - - unify the Blackfin board targets - - Signed-off-by: Mike Frysinger - -commit d4d7730853e5d675f76ec666807da3028c91d592 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:55 2008 -0500 - - punt Blackfin VDSP headers and import sanitized/auto-generated ones - - Signed-off-by: Mike Frysinger - -commit 6cfcce67671a3425229d66203386fa3cbd0cc3bd -Author: Mike Frysinger -Date: Mon Feb 4 19:26:54 2008 -0500 - - always pull in asm/blackfin.h for Blackfin ports - - Signed-off-by: Mike Frysinger - -commit bf53974c2ddae678d7660f2b5ccfeb0732b6f5dc -Author: Mike Frysinger -Date: Mon Feb 4 19:26:54 2008 -0500 - - add missing __raw versions of Blackfin read/write io functions - - Signed-off-by: Mike Frysinger - -commit 24e02d0fd3acc50e73e1a3cdd567f0a77946f15d -Author: Mike Frysinger -Date: Mon Feb 4 19:26:54 2008 -0500 - - add the default Blackfin logo used by Blackfin boards with splash screens - - Signed-off-by: Mike Frysinger - -commit 4c58eb5552220e425c8af6ac8d2839244a2f57b1 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:54 2008 -0500 - - add some more Blackfin docs - - Signed-off-by: Mike Frysinger - -commit 32a9f5f2160a034ea87ea651b233ef7c635e55cf -Author: Mike Frysinger -Date: Mon Feb 4 19:26:54 2008 -0500 - - make smc91111_eeprom managment simpler by depending on the board configuration file rather than a hardcoded list of boards - - Signed-off-by: Mike Frysinger - -commit 4087bc88cebec75c432a7fe9f6afb545b0919831 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:54 2008 -0500 - - fix building on Blackfin as the assembler supports the .set syntax, not the = syntax, for assigning symbols - - Signed-off-by: Mike Frysinger - -commit b45264ee85cbd92020640a32e02fb434fd557108 -Author: Mike Frysinger -Date: Mon Feb 4 19:26:53 2008 -0500 - - add gitignores for Blackfin pieces - - Signed-off-by: Mike Frysinger - -commit a93907c43f847f076dd0e34ee3b69b5e8e6d0d29 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Jan 18 01:14:03 2008 +0100 - - TFTP: add host ip addr support - - allow to use a different server as set in serverip - add CONFIG_TFTP_FILE_NAME_MAX_LEN to configure the file name length - if not defined the max length will be at 128 - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit e56b4b494cd92def577969f9678395aa22d34c9f -Author: Timur Tabi -Date: Wed Jan 9 14:35:26 2008 -0600 - - 85xx,86xx: Determine I2C clock frequencies and store in global_data - - Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx. - - Update the get_clocks() function in 85xx and 86xx to determine the I2C - clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk. - - Signed-off-by: Timur Tabi - -commit 7ec8bb15ee368ea54d48d64867767a704d9ab4c2 -Author: Wolfgang Denk -Date: Thu Dec 27 10:56:54 2007 +0100 - - OMAP5912: fix FIFO handling in UART driver - - According to the OMAP5912 Serial Interfaces Reference Guide (see - http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the - FIFO_EN enable bit in the FIFO Control Register (FCR) can only be - changed when the baud clock is not running, i. e. when both DLL and - DLH are set to 0. - - Thus make sure that DLL and DLH are 0 when writing the FCR. - - Signed-off-by: Wolfgang Denk - -commit 16158778b5f52f201e95ded2d2d9084b0ed5670d -Author: Harald Welte -Date: Wed Dec 19 15:10:52 2007 +0100 - - ARM: S3C24x0 SoC NAND controller support - - This patch adds NAND support to the S3C24x0 SoC code in u-boot - - Signed-off-by: Harald Welte - -commit a7c185ed3d9f8ebd85cfc286e1ffee72e4803163 -Author: Harald Welte -Date: Wed Dec 19 14:24:40 2007 +0100 - - ARM: s3c24xx: Multiple serial port support - - This patch adds support for CONFIG_SERIAL_MULTI on s3c24x0 CPU's - - Signed-off-by: Harald Welte - -commit a25f72f1f73a11de68251fb88c89991e202e68fa -Author: Harald Welte -Date: Wed Dec 19 14:16:57 2007 +0100 - - ARM: arm920t: Allow use of 'gd' pointer from IRQ - - This patch allows us to use the 'gd' pointer (and thus environment - and everything else associated with it) from interrupt context on - arm920t. - - Signed-off-by: Harald Welte - -commit be19bd5cd0f454b63298844a0b5377e029b2caad -Author: Harald Welte -Date: Wed Dec 19 14:19:38 2007 +0100 - - ARM: arm920/s3c24xx: IRQ demulitplexer callback - - This patch adds a IRQ demultiplexer callback to the arm920 cpu core code, - plus a stub implementation of it for the S3C2410. - - The purpose is to allow arm920t implementations such as the s3c24x0 to - implement interrupt handlers in u-boot without having to touch core - arm920t code. - - Signed-off-by: Harald Welte - -commit a41dbbd98d201d8aea31b5d21df4742c20cd7eda -Author: Hebbar -Date: Tue Dec 18 16:03:07 2007 -0800 - - ARM: Display Ethernet info in do_bdinfo only if CONFIG_CMD_NET is defined - - Add ifdef to bdinfo command to display ethernet information - only if CONFIG_CMD_NET is defined for arm modules. - - Signed-off-by: K R Gururaja Hebbar - -commit f7ad79b6f9f0f45437b62e19b45356cc2aaf4884 -Author: Hebbar -Date: Tue Dec 18 16:00:54 2007 -0800 - - ARM: add I2C init function call in lib_arm/board.c - - Adds I2C init func call to init sequence for ARM boards. This is - present in ppc,blackfin and other processor init sequence. - - Signed-off-by: K R Gururaja Hebbar - -commit ff02f139804f3cb61414f7bbcbfdaa0279e3efae -Author: Stefan Roese -Date: Fri Feb 1 09:38:29 2008 +0100 - - ppc4xx: Fix ndfc HW ECC byte order - - The current ndfc HW ECC implementation swaps the first two ECC bytes. - But the 4xx NDFC already uses the SMC (Smart Media Card) ECC ordering, - so this swapping in the HW ECC driver is bogus. This patch fixes this - problem and now really uses the SMC ECC byte order. - - Thanks to Sean MacLennan for pointing this out. - - Signed-off-by: Stefan Roese - -commit e1d1429b49b0ee58c80f8c7b29c1ebaf8be7f5f1 -Author: Stefan Roese -Date: Wed Jan 30 15:35:50 2008 +0100 - - ppc4xx: Fix GPIO configuration for pcs440ep - - The SRD0_PFC0 register was not configured correctly to enable the GPIO's - 49-63 for GPIO. They have been configured as trace signals. This patch - fixes this by clearing the corresponding bit. - - Signed-off-by: Stefan Roese - -commit 28d77d968bfe0316deb5bf15c17f57d5ff2c8821 -Author: Stefan Roese -Date: Wed Jan 30 14:48:28 2008 +0100 - - ppc4xx: Fix problem with init-ram bigger than 4k on 440 platforms - - Signed-off-by: Stefan Roese - -commit 4fedfddf97461b88668b9aec774dfb7a0c6dc368 -Author: Ladislav Michl -Date: Fri Dec 7 00:42:32 2007 +0100 - - ARM: Board voiceblue update - - Signed-off-by: Ladislav Michl - -commit 2c5260f711168d5ee91c70ddbb7d897013eefc46 -Author: Ladislav Michl -Date: Thu Dec 6 23:24:57 2007 +0100 - - ARM: AT91RM9200 based boards config cleanup - - Signed-off-by: Ladislav Michl - - Remove nowhere used struct bd_info_ext, remove trailing whitespaces, fix - indentation. - -commit 481f28b1db5cd21deb55f69399ba240e107af4c7 -Author: Ladislav Michl -Date: Thu Dec 6 22:59:16 2007 +0100 - - ARM: Fix at91rm9200dk base address - - Somewhere during development of U-Boot-1.1.3 CONFIG_BOOTBINFUNC was - renamed into CONFIG_INIT_CRITICAL which was 04 Apr 2005 replaced - with CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT. - However CONFIG_SKIP_LOWLEVEL_INIT has oposite meaning to - CONFIG_BOOTBINFUNC, so fix configuration to reflect this fact. - I'm sending this patch 4th (!) time in hope it produces at least some - reaction. - - Signed-off-by: Ladislav Michl - - Fix at91rm9200dk base and environment address. - -commit c95219fae2a7add7daa2f91aedca65b1698465c7 -Author: stefano babic -Date: Tue Nov 20 10:40:24 2007 +0100 - - MMC for PXA 27X (resubmit) - - MMC support for X_Scale PXA is broken and does not work. - Mainly, the mmc_init() function cannot recognize current SD/MMC cards. - There were already some patches around the world but none of them was - merged into the official u-boot tree. - - This patch makes order fixing this issue. Resubmit after code cleanup. - - Applied and tested on PXA 270 (TrizepsIV module). - - Signed-off-by: Stefano Babic - -commit 96bbfa1e6625ce23a150936863b3ecf4c853eb33 -Author: stefano babic -Date: Tue Nov 20 10:37:04 2007 +0100 - - Fix gcc issues in pxa-regs.h - - Fix gcc4 issue. With some toolchain, a previous patch that fixes gcc4 - issues generates wrong code. - (Problem was reported with gcc-4.0.2-glibc-2.3.6/arm-softfloat-linux-gnu). - This patch fixes the problem and solves the gcc-4 issues as the linux - kernel does. - - Signed-off-by: Stefano Babic - Signed-off-by: Dmitry Ivanov - -commit 7047b388876e7b905b2ec4edb8010543e3641b85 -Author: Jens Gehrlein -Date: Tue Jan 29 08:45:03 2008 +0100 - - TQM834x: enable DHCP - - Signed-off-by: Jens Gehrlein - Signed-off-by: Kim Phillips - -commit a877004d44ca7dbc1e618add3eeb1da7c84e4bec -Author: Jens Gehrlein -Date: Tue Jan 29 08:45:02 2008 +0100 - - TQM834x: support for Spansion N-type Flashes (sector size = 256 KiB at 2x16 Bit). - - Signed-off-by: Jens Gehrlein - Signed-off-by: Kim Phillips - -commit 8931ab176025b03cfc320b3fd1eca432a88ed560 -Author: Ben Warren -Date: Sat Jan 26 23:41:19 2008 -0500 - - Fix conditional compilation of mpx8xxx_spi driver - - This driver should only compile if CONFIG_MPC8XXX_SPI is set - - Signed-off-by: Ben Warren - Signed-off-by: Kim Phillips - -commit 63f732d3d3880feb531f48af247c025bf01462b0 -Author: Rafal Jaworowski -Date: Tue Jan 29 17:00:34 2008 +0100 - - API: Provide dummy halt() in the glue layer. - - This fixes a demo app link failure on platforms configured with CONFIG_PANIC_HANG. - - Signed-off-by: Rafal Jaworowski - -commit 0dc1fc22af86d16993388d9ed9630dbaa2d51826 -Author: Rafal Jaworowski -Date: Tue Jan 29 16:57:38 2008 +0100 - - API: Convert conditional building to the new scheme. - - This fixes a build breakage with CONFIG_API enabled, which appeared after - the recent changes in the U-Boot build system. - - Signed-off-by: Rafal Jaworowski - -commit 98b742489c09780be6a832eeaa4e5eff824792bb -Author: Wolfgang Denk -Date: Fri Jan 25 09:56:17 2008 +0100 - - inka4x0: remove dead code - - Signed-off-by: Wolfgang Denk - -commit 4f93f8b1a4d35b6d302842132edba920ef8f62aa -Author: Becky Bruce -Date: Wed Jan 23 16:31:06 2008 -0600 - - 86xx: Add reginfo command - - Signed-off-by: Becky Bruce - -commit ddcebcb638715a6278da93b553d5016f99823816 -Author: Becky Bruce -Date: Wed Jan 23 16:31:05 2008 -0600 - - 86xx: Add print_laws function to fsl_law.c - - This can be used for debug, and will be used by board code - to help implement reginfo. - - Signed-off-by: Becky Bruce - -commit 9cd32426f26a0567bb61f339edd83c6a2ce9bfc3 -Author: Becky Bruce -Date: Wed Jan 23 16:31:04 2008 -0600 - - 86xx: Remove old-style law setup code - - This includes mpc8610hpcd, mpc8641hpcn, and sbc8641d. - - Signed-off-by: Becky Bruce - -commit 713d8186649dae874613d495b0cecaa039a98b30 -Author: Becky Bruce -Date: Wed Jan 23 16:31:03 2008 -0600 - - 86xx: Convert sbc8641d to use new law setup code. - - Signed-off-by: Becky Bruce - -commit 031976f6364b93833e989f57e9f1e023e0be8c4c -Author: Becky Bruce -Date: Wed Jan 23 16:31:02 2008 -0600 - - 86xx: Convert mpc8610hpcd to new law setup method. - - Signed-off-by: Becky Bruce - -commit 4933b91f8a49e436681f163df3173beb91cac44a -Author: Becky Bruce -Date: Wed Jan 23 16:31:01 2008 -0600 - - 86xx: Support new law setup method and convert mpc8641 - - Adds the support code in cpu/mpc86xx for the new law setup code - recently created fsl_law.c, and changes the MPC8641HPCN config - to use this code. - - Signed-off-by: Becky Bruce - -commit 1a41f7ce9c086e208c0eabf52565a237af2a2bd1 -Author: Becky Bruce -Date: Wed Jan 23 16:31:00 2008 -0600 - - 86xx: Rearrange the sequence in start.S - - * split the BAT initialization so that only 2 BATs (for the boot page - and stack) are programmed very early on. The rest are initialized later. - * Move other BAT setup, ccsrbar setup, and law setup later in the code - after translation has been enabled. - - These changes will facilitate the moving of law and BAT initialization - to C code, and will aid with 36-bit physical addressing support. - - Signed-off-by: Becky Bruce - -commit 33dac03b1b5d61e4fed7bad445ba40b4c97feba0 -Author: Wolfgang Denk -Date: Wed Jan 23 14:41:37 2008 +0100 - - Coding Style Cleanup; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 865f0f9754b95183cad395de7e8cb85df0c6ea1f -Author: Wolfgang Denk -Date: Wed Jan 23 14:31:17 2008 +0100 - - Coding Style Cleanup; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit cfe5ca77976afdbe7ecb86e39fd7505bde636ace -Author: Dave Liu -Date: Fri Jan 18 10:07:04 2008 +0800 - - mpc83xx: Correct the struct spi8xxx in mpc8xxx_spi.h - - The commit 04a9e1180ac76a7bacc15a6fcd95ad839d65bddb - cause the 83xx immap broken, so the DMA and PCI will - be failed. - - The patch fix the struct spi8xxx and rm struct spi83xx. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 6b4439444286e0fcd01596df504e6ca897ad3e5a -Author: Haavard Skinnemoen -Date: Sat Apr 14 17:11:49 2007 +0200 - - AVR32: ATNGW100 board support - - Add support for the ATNGW100 Network Gateway reference design, - including flash, ethernet and MMC support. - - Signed-off-by: Haavard Skinnemoen - -commit e006927a0b9a54e8ee7685d8ac748aaad6801862 -Author: Haavard Skinnemoen -Date: Sat Nov 24 18:15:31 2007 +0100 - - AVR32: Initialize ipaddr, loadaddr and bootfile at startup - - I don't know why the relevant layers can't do this by itself, but this - is what ppc does. - - Signed-off-by: Haavard Skinnemoen - -commit 799891ef7b1b3432032ec23466df6b665a797fa4 -Author: Michael Schwingen -Date: Fri Jan 18 00:04:28 2008 +0100 - - Add AcTux board support - - Hi, - - The patch adds 4 boards, called AcTux-1 .. AcTux-4. This patch contains the - files that - contain changes for multiple boards, the board-specific files follow as - separate patches. - - Signed-off-by: Michael Schwingen - -commit 66a4344a4d910a11125df7768899ad529719855e -Author: Michael Schwingen -Date: Wed Jan 16 19:53:23 2008 +0100 - - add AcTux-4 board support - - Signed-off-by: Michael Schwingen - -commit bc24345e4101a5c996d6b48ce497b09c53025dc6 -Author: Michael Schwingen -Date: Wed Jan 16 19:51:55 2008 +0100 - - add AcTux-3 board support - - Signed-off-by: Michael Schwingen - -commit aebf00fc4d1343b24715373893f7b20bf462d1e9 -Author: Michael Schwingen -Date: Wed Jan 16 19:51:14 2008 +0100 - - add AcTux-2 board support - - Signed-off-by: Michael Schwingen - -commit ea99e8f05b7240fd657739e286664664ae160abe -Author: Michael Schwingen -Date: Wed Jan 16 19:50:37 2008 +0100 - - add AcTux-1 board support - - Signed-off-by: Michael Schwingen - -commit 3d9f3bfb7a33efe8e41e01b025563cd712c57d64 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Jan 14 19:20:08 2008 +0100 - - ARM: remove useless function board_post_init - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 96bd462942022e4569b582c072a0ed26de1cd19b -Author: Michael Schwingen -Date: Thu Jan 10 14:59:46 2008 +0100 - - IXP: enable RTS - - enables the RTS signal with CONFIG_SERIAL_RTS_ACTIVE. - No handshaking is done, but the active RTS signal allows to - connect to the target using a PC which is using RTS/CTS - handshake, and does no harm if the PC is set to ignore RTS. - - Signed-off-by: Michael Schwingen - -commit a1cf027a08f9dc1c0e769499e6f4fbddcf9cab93 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Jan 7 08:41:34 2008 +0100 - - IXP: add dynamic microcode addr - - allow to load the microde from flash or ram by download it through - the serial or other. - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Acked-by: Stefan Roese - -commit 63ebcc4615dd39926ccf61f1d5f3510262ef6564 -Author: Michael Schwingen -Date: Sat Nov 10 15:44:12 2007 +0100 - - load ixp42x NPE firmware from separate flash block, remove dead code - - Hi, - - the following patch adds support to move the IXP42X NPE firmware to a - separate flash block, whose start address is defined in - CONFIG_IXP4XX_NPE_EXT_UCODE_BASE. Using that, it is possible to build - NPE-enabled u-boot without copyright problems due to the NPE firmware. - - I hope the patch applies, I get whitespace-related differences in the NPE - files due to trailing whitespace in the original versions. - - Signed-off-by: Michael Schwingen - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 57a127201eb3d8cc19170a008e0bd7af608bd72f -Author: TsiChungLiew -Date: Tue Jan 15 14:15:46 2008 -0600 - - ColdFire: MCF547x_8x - Add M5475EVB and M5485EVB support - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit 1aee111135d8660a164d4f6bf7d66b032ea535cf -Author: TsiChungLiew -Date: Tue Jan 15 14:02:49 2008 -0600 - - ColdFire: MCF547x_8x - Add M547xEVB and M548xEVB board - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit 777d1abd9796f1c2e148417cc10657e847d318ce -Author: TsiChungLiew -Date: Tue Jan 15 14:00:25 2008 -0600 - - ColdFire: Add MCF547x_8x FEC driver - - Signed-off-by: TsiChungLiew - Signed-off-by: Ben Warren - Signed-off by: John Rigby - -commit 72f56adc0b25d43875ad067bae6be1bcea86b79f -Author: TsiChungLiew -Date: Tue Jan 15 13:54:09 2008 -0600 - - ColdFire: Add MCF547x_8x dma code and header files - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit ce09fc49b56ea3c442794b6be9b7db4b99dfdc87 -Author: TsiChungLiew -Date: Tue Jan 15 13:52:03 2008 -0600 - - ColdFire: Add MCF547x_8x dma code - 2 - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit 11865ea844e7154fd30c7e2860da4eed4a12ad1f -Author: TsiChungLiew -Date: Tue Jan 15 13:48:52 2008 -0600 - - ColdFire: Add MCF547x_8x dma code - 1 - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit 4621fc3fe7cd65b78b3cbd31f65c9f7f72b22bd3 -Author: TsiChungLiew -Date: Tue Jan 15 13:39:44 2008 -0600 - - ColdFire: Add MCF547x_8x related header files - - Signed-off-by: TsiChungLiew - Signed-off-by: Ben Warren - Signed-off by: John Rigby - -commit 570c0186aecab1b747b2d44d0e1d3c1ac4cb27f5 -Author: TsiChungLiew -Date: Tue Jan 15 13:37:34 2008 -0600 - - ColdFire: Add MCF547x_8x cpu arch - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit e2756f4b54aba0e0523b81dd145666829cf7fd59 -Author: TsiChungLiew -Date: Mon Jan 14 17:47:23 2008 -0600 - - ColdFire: Add MCF5227x cpu and M52277EVB support-3 - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit c87581027994c148131b2f11aa75501f782ec19a -Author: TsiChungLiew -Date: Mon Jan 14 17:46:19 2008 -0600 - - ColdFire: Add MCF5227x cpu and MCF52277EVB support-2 - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit 1552af70ecab11b9f3dceff7528ed15faf678b9d -Author: TsiChungLiew -Date: Mon Jan 14 17:43:33 2008 -0600 - - ColdFire: Add MCF5227x cpu and M52277EVB support-1 - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit 397b7b81a1f1008798ae1206913508cc89cb3a7d -Author: TsiChungLiew -Date: Mon Jan 14 17:35:44 2008 -0600 - - ColdFire: Fix CFI Flash low level Read/Write macro - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit aa5f1f9dc815a76f6dffb580798599c028fe7feb -Author: TsiChungLiew -Date: Mon Jan 14 17:23:08 2008 -0600 - - ColdFire: Add M5373EVB platform support - 2 - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit 1ac559d4aa358f63b48c62b564224c06feeb4e36 -Author: TsiChungLiew -Date: Mon Jan 14 17:19:54 2008 -0600 - - ColdFire: Add M5373EVB platform support - 1 - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit 320d61991fa3190ee41765601ed017b6b5ff7b2b -Author: TsiChungLiew -Date: Mon Jan 14 17:17:03 2008 -0600 - - ColdFire: Update FlexBus CS for MCF532x - - Definition update and change from 16bit to 32bit - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit 2e72ad0644b940817a89a3590ce0d7b99c05c396 -Author: TsiChungLiew -Date: Mon Jan 14 17:11:47 2008 -0600 - - ColdFire: PCI and misc updates for MCF5445x - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit d2b16493480ac3d4a60ad7d835b0dc27d2e99cee -Author: TsiChungLiew -Date: Mon Jan 14 17:06:55 2008 -0600 - - ColdFire: MCF5445x header files cleanup - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit d9aae6260993a93f7fcf13abff85a601f4f50ea7 -Author: TsiChungLiew -Date: Mon Jan 14 16:59:42 2008 -0600 - - ColdFire: MCF532x header files cleanup - - Signed-off-by: TsiChungLiew - Signed-off by: John Rigby - -commit 7af7751d047e74b2ec58400f97b879c56446b3e8 -Author: TsiChungLiew -Date: Mon Jan 14 15:30:15 2008 -0600 - - ColdFire: Add modules header files - - Add CF specific modules header files - - Signed-off-by: TsiChung Liew - Signed-off-by: John Rigby - -commit 2956acd5ef93a498337f8ac2ec6ae6a77d491dc5 -Author: Kim Phillips -Date: Thu Jan 17 12:48:00 2008 -0600 - - codingstyle cleanup for spi driver - - ..and rm unused CONFIG_FSL_SPI define - - Signed-off-by: Kim Phillips - -commit d59feffb42c9f174116db7a82a311df98983dfce -Author: Haiying Wang -Date: Wed Jan 16 17:12:12 2008 -0500 - - FSL: Fix common EEPROM_data structure definition - - - Fix EEPROM_data structure definition according to System EEPROM Data Format. - - Read MAC addresses from EEPROM to ethXaddr before saving ethXaddr to - bd->bi_ethaddr. - - Signed-off-by: Haiying Wang - -commit 6bee764bd6da510a4aad614880300c968bc7318d -Author: Timur Tabi -Date: Wed Jan 16 15:48:12 2008 -0600 - - 86xx: enable command-line editing - - Enable command-line editing for all MPC86xx boards. - - Signed-off-by: Timur Tabi - -commit 80ddd22626d321a772ebfba304eb7830cb4f6bac -Author: Ben Warren -Date: Wed Jan 16 22:37:42 2008 -0500 - - Implement hard SPI driver on MPC8349EMDS - - This patch implements the fsl_spi driver on the MPC8349EMDS evaluation board. - This board has an ST M25P40 4Mbit EEPROM on its SPI bus - - Signed-off-by: Ben Warren - Signed-off-by: Kim Phillips - -commit 04a9e1180ac76a7bacc15a6fcd95ad839d65bddb -Author: Ben Warren -Date: Wed Jan 16 22:37:35 2008 -0500 - - Add support for a Freescale non-CPM SPI controller - - This patch adds support for the SPI controller found on Freescale PowerPC - processors such as the MCP834x family. Additionally, a new config option, - CONFIG_HARD_SPI, is added for general purpose SPI controller use. - - Signed-off-by: Ben Warren - Signed-off-by: Kim Phillips - -commit a8cb43a89be6cfd283257a603dd9841503ccce0f -Author: Dave Liu -Date: Thu Jan 17 18:23:19 2008 +0800 - - mpc83xx: Fix the fatal conflict of merge - - The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7 - will cause the mpc8315erdb board can't boot up. - - The patch fix that bug, and remove the duplicated #ifdef - CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for - MPC8313E processor. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 3259eeaa4148125a81417477f62c05bd67f60587 -Author: Larry Johnson -Date: Thu Jan 17 08:50:09 2008 -0500 - - Merge Sequoia beautification into Korat code - - Signed-off-by: Larry Johnson - -commit e16925773211291b562e77187061e9dd1d757217 -Author: Matthias Fuchs -Date: Thu Jan 17 07:45:05 2008 +0100 - - net: add 'ethrotate' environment variable - - [PATCH] net: add 'ethrotate' environment variable - - This patch replaces the buildtime configuration option - CONFIG_NET_DO_NOT_TRY_ANOTHER through the 'ethrotate' runtime - configuration veriable. See README. - - Signed-off-by: Matthias Fuchs - Signed-off-by: Ben Warren - -commit ba52be3d0e618c26070e93aaf3c1f2d2adf5571f -Author: Stefan Roese -Date: Thu Jan 17 14:29:04 2008 +0100 - - ppc4xx: Fix compilation warnings and coding style issues in HCU4/HCU5 - - Signed-off-by: Stefan Roese - -commit 55ed1516cbc1dad3ae277c67ee06fc4a46eaac7d -Author: Nobuhiro Iwamatsu -Date: Thu Jan 17 18:07:32 2008 +0900 - - sh: Remove CONFIG_COMMANDS from MS7720SE config file - - Signed-off-by: Nobuhiro Iwamatsu - -commit 055606bd25e88c0cd04ad348a679a04b1b616bee -Author: Niklaus Giger -Date: Wed Jan 16 18:39:20 2008 +0100 - - ppc4xx: Netstal HCU4 board: added various fixes and POST - - - Moved some common code to netstal/common/nm_bsp.c. - - sdram initialisation goes go netstal/common/fixed_sdram.c. - - Added support for POST. - - Stylistic cleanups (multi-line comments/ enforce 80 colomn width) - - Signed-off-by: Niklaus Giger - -commit 69b0634a4ee98c9791815600d43b99f626a952f3 -Author: Niklaus Giger -Date: Thu Jan 17 12:53:56 2008 +0100 - - ppc4xx: netstal/common define routines used by all boards - - Added some routines used by all Netstal boards: - - nm_bsp.c: - nm_show_print and - - common_misc_init_r - - set_params_for_sw_install. Very specific code to handle our SW - installation procedure - - fixed_sdram.c: Common routines for HCU4 (and upcoming) MCU25 boards - to handle sdram initialization. - - nm.h: Common header - - Signed-off-by: Niklaus Giger - -commit efeff5382b7a91b48a1aa68b2b75f92ad1d33ff8 -Author: Niklaus Giger -Date: Wed Jan 16 18:39:18 2008 +0100 - - ppc4xx: Netstal HCU5 board: added various fixes and POST - - - Moved some common code to nestal/common/nm_bsp.c. - - Added support for the vxWorks EDR. - - Enable trace for Lauterbach, if present. - - Added support for POST. - - Stylistic cleanups (multi-line comments/ enforce 80 colomn width) - - Signed-off-by: Niklaus Giger - -commit 4371090e5da77edc7bf9f296364db4801639d9c4 -Author: Niklaus Giger -Date: Wed Jan 16 18:39:08 2008 +0100 - - ppc4xx: Netstal HCU5 board. Added POST. Various fixes - - - Various fixes - - Reduced rom_size from 384 to 320 kB - - Environment is now in flash - - Added POST - - Support for OF - - Signed-off-by: Niklaus Giger - -commit 4bd5036e60afac37e484c2d35cbbe7f6cc1623e7 -Author: Niklaus Giger -Date: Wed Jan 16 18:37:50 2008 +0100 - - ppc4xx: Netstal HCU4 board. Added POST. Various fixes - - - Various fixes - - Reduced rom_size from 384 to 320 kB - - Environment is now in flash - - Added POST - - Support for OF - - Signed-off-by: Niklaus Giger - -commit 1a3ac86b79fcb690275c85861c8efa6a3899060a -Author: Matthias Fuchs -Date: Thu Jan 17 10:53:08 2008 +0100 - - ppc4xx: Complete DU440 board support - - Signed-off-by: Matthias Fuchs - -commit 15a08bc2bef91e5f1ea4b9cf60e46832d86bcc1f -Author: Matthias Fuchs -Date: Thu Jan 17 10:52:30 2008 +0100 - - ppc4xx: Add DU440 board support - - Signed-off-by: Matthias Fuchs - -commit ac331da07db3860f11fa1d0fd3db7c810bce1198 -Author: Nobuhiro Iwamatsu -Date: Thu Jan 17 15:53:52 2008 +0900 - - sh: Update SuperH SCIF driver - - This patch fixed wrong SH7720 CPU macro and changed macro that - calculated value of SCBRR register. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 334e442e6fac59be91244063e9b3f6ca25e8daf8 -Author: Grzegorz Bernacki -Date: Wed Jan 16 15:12:47 2008 +0100 - - Set ips dividor to 1/4 of csb clock. - - Previous setting cause ips clock to be out of spec. This bug was found by John - Rigby from Freescale. - - Signed-off-by: Grzegorz Bernacki - -commit 7dc358bb0de9e2fa341f3b4c914466b1f34b2d89 -Author: Kumar Gala -Date: Thu Jan 17 02:19:18 2008 -0600 - - 85xx: Get ride of old TLB setup code - - Now that all boards have been converted, remove old config code and the - config option for the new style. - - Signed-off-by: Kumar Gala - -commit 3b558e26a5ef31635787d6d6e97d70939d4f892d -Author: Kumar Gala -Date: Thu Jan 17 02:02:10 2008 -0600 - - 85xx: Convert TQM85xx to new TLB setup - - Signed-off-by: Kumar Gala - -commit 74121b470c14f7eaf284ee838bffca6f9521069e -Author: Kumar Gala -Date: Thu Jan 17 01:56:32 2008 -0600 - - 85xx: Convert STXGP3 & STXSSA to new TLB setup - - Signed-off-by: Kumar Gala - -commit 143b518d9125b54f96f1d7f1afc640b8aae81ff0 -Author: Kumar Gala -Date: Thu Jan 17 01:44:34 2008 -0600 - - 85xx: Convert SBC8540/SBC8560/SBC8548 to new TLB setup - - Signed-off-by: Kumar Gala - -commit 818218bac6a11591e2542c344d2330e0f4e1968b -Author: Kumar Gala -Date: Thu Jan 17 01:31:34 2008 -0600 - - 85xx: Convert PM854/PM856 to new TLB setup - - Signed-off-by: Kumar Gala - -commit ff4681c9285b2b4d24552a19cacc1769fe2fc7e0 -Author: Kumar Gala -Date: Thu Jan 17 01:25:33 2008 -0600 - - 85xx: Convert MPC8540EVAL to new TLB setup - - Signed-off-by: Kumar Gala - -commit 73aa9ac2b46f1cfd039106ebd6b9865016005234 -Author: Kumar Gala -Date: Thu Jan 17 01:12:22 2008 -0600 - - 85xx: Convert MPC8568 MDS to new TLB setup - - Signed-off-by: Kumar Gala - -commit 0db37dc2eed30884db2daa24dbd9a113b5d00610 -Author: Kumar Gala -Date: Thu Jan 17 01:01:09 2008 -0600 - - 85xx: Convert MPC8541/MPC8555/MPC8548 CDS to new TLB setup - - Signed-off-by: Kumar Gala - -commit 219a81b98d834f9071b6f7c3bdc6b7ec39cc46cc -Author: Kumar Gala -Date: Thu Jan 17 00:52:29 2008 -0600 - - 85xx: Convert MPC8540/MPC8560 ADS to new TLB setup - - Signed-off-by: Kumar Gala - -commit 80d0b6a1498761c4355b2db9c8001b04c295e7b8 -Author: Kumar Gala -Date: Thu Jan 17 00:32:17 2008 -0600 - - 85xx: Convert ATUM8548 to new TLB setup - - Signed-off-by: Kumar Gala - -commit 0f7a3dc95cbff3c21bd6dbc639313796412bbbab -Author: Kumar Gala -Date: Wed Jan 16 23:11:57 2008 -0600 - - 85xx: Convert MPC8544 DS to new TLB setup - - Signed-off-by: Kumar Gala - -commit 8716318057a5f60ab1ba081ece2dbe82ae00e1ee -Author: Kumar Gala -Date: Wed Jan 16 22:38:34 2008 -0600 - - 85xx: Reworked initial processor init - - Reworked the initial processor initialzation sequence: - * introduced cpu_early_init_f that is run in address space 1 (AS=1) - * Moved TLB/LAW and CCSR init into cpu_early_init_f() - * Reworked initial asm code to do most of the core init before TLBs - - The main reasons for these changes are to allow handling of 36-bit phys - addresses in the future and some of the issues that will exist when we - do that. - - There are a few caveats on what can be initialized via the LAW and TLB - static tables: - * TLB entry 14/15 can't be initialized via the TLB table - * any LAW that covers the implicit boot window (4G-8M to 4G) must map to - the code that is currently executing. - - Signed-off-by: Kumar Gala - -commit 44a23cfd6360a68eaa41f945190618a55519eac3 -Author: Kumar Gala -Date: Wed Jan 16 22:33:22 2008 -0600 - - 85xx: Introduce new tlb API - - Add a set of functions to manipulate TLB entries: - * set_tlb() - write a tlb entry - * invalidate_tlb() - invalidate a tlb array - * disable_tlb() - disable a variable size tlb entry - * init_tlbs() - setup initial tlbs based on static table - - Signed-off-by: Kumar Gala - -commit be88b1699863c262818f3af7f60173b4d48df8fc -Author: Stefan Roese -Date: Thu Jan 17 07:50:17 2008 +0100 - - ppc4xx: Fix remaining CONFIG_COMMANDS in 4xx files - - Signed-off-by: Stefan Roese - -commit c8c41d4a80b1a8ad5984a287d81ea780496259f8 -Author: Kumar Gala -Date: Wed Jan 16 10:04:42 2008 -0600 - - 85xx: Use proper defines for PCI addresses - - We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE. - While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only - be used for configuring the PCI ATMU. - - Signed-off-by: Kumar Gala - -commit 54a5070115eff38e9b324b78abdfa0b4520580b9 -Author: Kumar Gala -Date: Wed Jan 16 09:22:29 2008 -0600 - - 85xx: Remove old style of LAW init - - All boards are now using the new fsl_law code so we can drop the old version. - - Signed-off-by: Kumar Gala - -commit 4d3521cc79cabc61edf12c48c0ce318d4efb712f -Author: Kumar Gala -Date: Wed Jan 16 09:15:29 2008 -0600 - - 85xx: convert remaining 85xx boards over to use new LAW init code - - Converted ATUM8548, MPC8568 MDS, MPC8540 EVAL, and TQM85xx boards over - to use new LAW init code. - - Signed-off-by: Kumar Gala - -commit 572b13afc42710f2957c382a710360429c0e099b -Author: Kumar Gala -Date: Wed Jan 16 09:11:53 2008 -0600 - - 85xx: convert STXGP3/STXSSA over to use new LAW init code - - Signed-off-by: Kumar Gala - -commit 45f2166ac0233a9263058378f39612bd11f61196 -Author: Kumar Gala -Date: Wed Jan 16 09:06:48 2008 -0600 - - 85xx: convert PM854/PM856 over to use new LAW init code - - Signed-off-by: Kumar Gala - -commit e2b159d0070ee06e4ac7e2f9381d3e8e542e614a -Author: Kumar Gala -Date: Wed Jan 16 09:05:27 2008 -0600 - - 85xx: convert SBC8540/SBC8560/SBC8548 over to use new LAW init code - - Signed-off-by: Kumar Gala - -commit 2cfaa1aa1aac39a81006b7b27e0e431bf21f6dfa -Author: Kumar Gala -Date: Wed Jan 16 01:45:10 2008 -0600 - - 85xx: convert MPC8541/MPC8555/MPC8548 CDS over to use new LAW init code - - Signed-off-by: Kumar Gala - -commit 7232a2724ccc9dcbc3ec4ef84ada02f13ccd1238 -Author: Kumar Gala -Date: Wed Jan 16 01:32:06 2008 -0600 - - 85xx: convert MPC8540/MPC8560 ADS over to use new LAW init code - - Signed-off-by: Kumar Gala - -commit 4bcae9c92aee0d72a2f19b81cab27ef38107ce75 -Author: Kumar Gala -Date: Wed Jan 16 01:16:16 2008 -0600 - - 85xx: convert MPC8544 DS over to use new LAW init code - - Signed-off-by: Kumar Gala - -commit 83d40dfd79fe868796275802f60116d84b9e4395 -Author: Kumar Gala -Date: Wed Jan 16 01:13:58 2008 -0600 - - 85xx: Move LAW init code into C - - Move the initialization of the LAWs into C code and provide an API - to allow modification of LAWs after init. - - Board code is responsible to provide a law_table and num_law_entries. - - We should be able to use the same code on 86xx as well. - - Signed-off-by: Kumar Gala - -commit bed8ce838a609aaab136d43b25e6df2a520bc854 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Dec 22 15:03:12 2007 +0100 - - qemu-mips: active HUSH PARSER, AUTO_COMPLETE and CMDLINE_EDITING - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 0764c164fed6277d359cf132d55187ea34290114 -Author: Vlad Lungu -Date: Wed Jan 16 19:27:51 2008 +0200 - - MIPS:Target support for qemu -M mips - - With serial, NE2000, IDE support. Tested in big-endian mode. - Memory size hard-coded to 128M for now, so don't play with - the -m option. - - Signed-off-by: Vlad Lungu - -commit 7f52fa3c2df59e49dc2badd7c084cf2d007c438f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Jan 11 00:01:37 2008 +0100 - - Fix nfs command help to reflect that the serverip is optional - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Ben Warren - -commit b8f4162a4f7a9bee5e9d0305c17f2d34de466a9b -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Mon Dec 10 22:32:14 2007 +0100 - - bf537-stamp: remove already defined is_zero_ether_addr and is_multicast_ether_addr - - and move is_valid_ether_addr board file - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Ben Warren - -commit c2f896b8fc4722e36915903e1942e138e68ce804 -Author: Shinya Kuribayashi -Date: Wed Jan 16 16:13:31 2008 +0900 - - drivers/net/rtl8139.c: rx_status should be le32_to_cpu(rx_status). - - rx_status on the memory is basically in LE, but needs to be handled in CPU - endian. le32_to_cpu() takes up this mission. Even if on the sane hardware, - it'll work fine. - - Signed-off-by: Shinya Kuribayashi - Cc: Masami Komiya - Cc: Lucas Jin - Signed-off-by: Ben Warren - -commit 96a236746fe6a7b84802afb4ed31536696d34812 -Author: Shinya Kuribayashi -Date: Wed Jan 16 16:12:26 2008 +0900 - - drivers/net/rtl8139.c: Fix cache coherency issues - - Current driver is meant for cache coherent systems. This patch adds - flush_cache() routines to support cache non-coherent systems. - - Signed-off-by: Shinya Kuribayashi - Cc: Masami Komiya - Cc: Lucas Jin - Signed-off-by: Ben Warren - -commit d1276c76c1e2b5035296689280ba1acb2c425104 -Author: Shinya Kuribayashi -Date: Wed Jan 16 16:11:14 2008 +0900 - - drivers/net/rtl8139.c: Fix tx timeout - - "to = (currticks() + RTL_TIMEOUT)" has possibilities to wrap around. If it - does, the condition "(currticks() < to)" becomes invalid and immediately - leads to tx timeout error. This patch introduces the fine-graded udely(10) - loops to ease the impact of wrapping around. - - Signed-off-by: Shinya Kuribayashi - Cc: Masami Komiya - Cc: Lucas Jin - Signed-off-by: Ben Warren - -commit 18ee320ff63edbf7b27bbeb05f0e12a52302c68a -Author: Dave Liu -Date: Fri Jan 11 18:45:28 2008 +0800 - - TSEC: Add the support for RealTek RTL8211B PHY - - Add the support of RealTek RTL8211B PHY, the RTL8211B - PHY only supports RGMII and MII mode. - - Signed-off-by: Dave Liu - Signed-off-by: Ben Warren - -commit 84a3047b72b70e862b0b7a8e2058077457f89a32 -Author: Joakim Tjernlund -Date: Wed Jan 16 09:40:41 2008 +0100 - - Remove annoying debug printout for PHY less boards. - - PHY less board prints out lots of "read wrong ...": - read wrong value : mii_id 3,mii_reg 2, base e0102320 - read wrong value : mii_id 3,mii_reg 3, base e0102320 - UEC: PHY is Generic MII (ffffffff) - read wrong value : mii_id 3,mii_reg 4, base e0102320 - read wrong value : mii_id 3,mii_reg 0, base e0102320 - read wrong value : mii_id 3,mii_reg 1, base e0102320 - read wrong value : mii_id 3,mii_reg 1, base e0102320 - read wrong value : mii_id 3,mii_reg 5, base e0102320 - read wrong value : mii_id 3,mii_reg 1, base e0102320 - read wrong value : mii_id 3,mii_reg 1, base e0102320 - read wrong value : mii_id 3,mii_reg 5, base e0102320 - FSL UEC0: Full Duplex - FSL UEC0: Speed 100BT - FSL UEC0: Link is up - Using FSL UEC0 device - - Make this printout depend on UEC_VERBOSE_DEBUG and - remove its definition in uec_phy.c - - Signed-off-by: Joakim Tjernlund - Signed-off-by: Ben Warren - -commit ee62ed3286f83b98b7785e0318dc6379e78f7ff6 -Author: Kim Phillips -Date: Tue Jan 15 14:11:00 2008 -0600 - - net: reduce boot latency on QE UEC based boards - - actually polling for PHY autonegotiation to finish enables us to remove the - 5 second boot prompt latency present on QE based boards. - - call to qe_set_mii_clk_src in init_phy, and mv call to init_phy from - uec_initialize to uec_init by Joakim Tjernlund; autonegotiation wait - code shamelessly stolen from tsec driver. - - also rm unused CONFIG_RMII_MODE code. - - Signed-off-by: Kim Phillips - Signed-off-by: Joakim Tjernlund - Signed-off-by: Ben Warren - -commit 55fe7c57a8b99a130925052dcdbb77f053dc50e3 -Author: michael.firth@bt.com -Date: Wed Jan 16 11:40:51 2008 +0000 - - TSEC driver: Change MDIO support to allow access to any PHYs on the MDIO bus - - The current TSEC driver limits MDIO access to the devices that have been configured as attached - to a TSEC MAC. This patch allows access to any PHY device on the MDIO bus through the 'mii' commands. - - Signed-off-by: Michael Firth - Acked-by: Andy Fleming - Signed-off-by: Ben Warren - -commit 5e918a98c26e8ab9b5d2d48d998a2ced2b5b85b3 -Author: Kim Phillips -Date: Wed Jan 16 00:38:05 2008 -0600 - - Add support for the MPC837xERDB - - MPC837xERDB board support includes: - * DDR2 330MHz hardcoded (soldered on the board) - * Local Bus NOR Flash - * I2C, UART and RTC - * eTSEC RGMII (TSEC0 - RTL8211B with MII; - * TSEC1 - VSC7385 local bus, hardcoded, requires seperate firmware - * load) - - Signed-off-by: Kevin Lam - Signed-off-by: Joe D'Abbraccio - Signed-off-by: Kim Phillips - -commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7 -Author: Kim Phillips -Date: Wed Jan 16 12:06:16 2008 -0600 - - mpc83xx: add support for more system clock performance controls - - System registers that are modified are the Arbiter Configuration - Register (ACR), the System Priority Control Register (SPCR), and the - System Clock Configuration Register (SCCR). - - Signed-off by: Michael F. Reiss - Signed-off by: Joe D'Abbraccio - Signed-off-by: Kim Phillips - -commit 16c3cde050e2d243e62b37486f1558570787beb8 -Author: James Yang -Date: Wed Jan 16 11:58:08 2008 -0600 - - FSL: Generalize PIXIS reset command parsing. - - Before, the order of arguments to the pixis_reset - command needed to be supplied in a hard-coded order. - Generalize the command parsing to allow any order. - - Signed-off-by: James Yang - Acked-by: Jon Loeliger - -commit ad8f8687b78c3e917b173f038926695383c55555 -Author: Jon Loeliger -Date: Tue Jan 15 13:42:41 2008 -0600 - - FSL: Convert board/freescale/common/Makefile to use CONFIG_ - - Convert the board/freescale/common/Makefile to use - CONFIG_* options to select which files to conditionally - compile into the board/freescale/common library rather - than conditionally compiling entire files. - - Now handles:: - CONFIG_FSL_PIXIS - CONFIG_FSL_DIU_FB - CONFIG_PQ_MDS_PIB - - CONFIG_ID_EEPROM is introduced until CFG_ID_EEPROM is gone. - - Signed-off-by: Jon Loeliger - -commit 7c2221eb230372a9e537c4f6636b147b0909325f -Author: Roy Zang -Date: Tue Jan 15 16:38:38 2008 +0800 - - Use CONFIG_ULI526X as MPC8610HPCD default Ethernet driver - - Use driver/net/uli526x.c as MPC8610HPCD default Ethernet driver. - Remove unused ethernet CONFIG_ options. - - Signed-off-by: Roy Zang - Acked-by: Jon Loeliger - -commit 711a7946277d2e29af481011e8635e9975c54e45 -Author: Kim Phillips -Date: Tue Jan 15 14:05:14 2008 -0600 - - mpc83xx: fix QE ETHPRIMEs to correct 'FSL UEC0' value - - continuation of commit b96c83d4ae475a70ef2635cd0e748174c44c8601 - - Signed-off-by: Kim Phillips - -commit 363eea9ff7f19a2cba17f262bd17559f166e134e -Author: Kim Phillips -Date: Tue Jan 15 09:51:12 2008 -0600 - - mpc83xx: clean up mpc8360emds.c warnings - - mpc8360emds.c: In function 'ft_board_setup': - mpc8360emds.c:327: warning: assignment makes pointer from integer without a cast - mpc8360emds.c:329: warning: passing argument 2 of 'fdt_getprop' makes integer from pointer without a cast - mpc8360emds.c:334: warning: passing argument 2 of 'fdt_setprop' makes integer from pointer without a cast - mpc8360emds.c:341: warning: assignment makes pointer from integer without a cast - mpc8360emds.c:343: warning: passing argument 2 of 'fdt_getprop' makes integer from pointer without a cast - mpc8360emds.c:348: warning: passing argument 2 of 'fdt_setprop' makes integer from pointer without a cast - - Signed-off-by: Kim Phillips - -commit f09880ea72a1c806db223ce594c5fb1b6542ff6a -Author: Kim Phillips -Date: Mon Jan 14 16:14:46 2008 -0600 - - mpc83xx: fix phy-connection-type fixup code - - use tree passed to us in local blob, not global fdt. - - Also use fdt_path_offset to convert to relative offset, since absolute - reference is needed to check for rgmii-id mode string value. - - Signed-off-by: Kim Phillips - -commit 2b4c952be7c4357a13e839d48df80853820c33eb -Author: Kumar Gala -Date: Mon Jan 14 09:01:40 2008 -0600 - - mpc83xx: fix mpc8313/mpc8315/mpc8349itx Makefiles for silent build (with -s) - - Signed-off-by: Kumar Gala - Signed-off-by: Kim Phillips - -commit e1d8ed2c08da14b168658cc5fa78529d461aea70 -Author: Poonam Aggrwal -Date: Mon Jan 14 09:41:14 2008 +0530 - - Changes in uboot DDR configuration for MPC8313eRDB - - These changes were identified by HighSmith Bill ,Mazzyar and Joseph for - DDR configuration in u-boot code. Some are related to performance, some - affect stability and some correct few basic errors in the current - configuration. - - The changes have been tested and found to give better memory latency - figures on MPC8313eRDB.LMBench figures prove it. - - The changes are: - - - CS0_CONFIG[ AP_n_EN] is changed from 1 to 0 - (this may improve performance for application with many read - or write to open pages). - - CS0_CONFIG[ODT_WR_CFG] is currently changed from 100 to - 001 (activating all the CS when only one is used may cause - unwanted noise on the system) - - - TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 8clks (based on - Tras=45ns) - - TIMING_CFG_1[REFREC] changed from 21 clks to 18clks. - - - TIMING_CFG_2[AL] value changed from 0 setting to 1 clk to - comply with the 3 ODT clk requirements) - - TIMING_CFG_2[CPO] was set to a reserved value, changed to RL+3/4. - - TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 6clks. - - - DDR_SDRAM_MODE[AL]changed from 0 to 1. - - DDR_SDRAM_MODE[WRREC] changed from 1 clk to 3 clks. - - - DDR_SDRAM_INTERVAL[REFINT] is changed from 0x0320 to 0x0510. - - DDR_SDRAM_INTERVAL[BSTOPRE] is changed from 0x64 to 0x0500. - - The patch is based of git://www.denx.de/git/u-boot-mpc83xx.git - The last commit on this tree was 6775c68683a53c7abc778774641aac6f833a2cbf - - Signed-off-by: Poonam Aggrwal-b10812 - Cc: Bill HighSmith - Cc: Razzaz Mazyar - Cc: Josep P J - Signed-off-by: Kim Phillips - -commit b5cdd7df4a06edb91539c9a2ea7c178a870c3a95 -Author: Jerry Van Baren -Date: Sat Jan 12 13:24:14 2008 -0500 - - Enable the isdram command on the MPC8360EMDS board - - The isdram command prints out decoded information the "serial presence - detect" (SPD) chip on the SDRAM SIMMs. This can be very helpful when - debugging memory configuration problems. - - Signed-off-by: Gerald Van Baren - Signed-off-by: Kim Phillips - -commit 8bd522ce4afda3d4868ee8c913f5394094326be1 -Author: Dave Liu -Date: Fri Jan 11 18:48:24 2008 +0800 - - mpc83xx: Add the support for MPC8315ERDB board - - The features list: - - Boot from NOR Flash - - DDR2 266MHz hardcoded configuration - - Local bus NOR Flash R/W operation - - I2C, UART, MII and RTC - - eTSEC0/1 support - - PCI host - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit b05884efa614e4d8a9413158fc228e0dc02ab704 -Author: Dave Liu -Date: Fri Jan 11 18:46:50 2008 +0800 - - mpc83xx: Add config of eTSEC emergency priority in SPCR - - The TSEC emergency priority definition of 831x/837x - is different than the definition of 834x in SPCR register. - - Add the other config of TSEC emergency priority into - cpu_init.c - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 9b958234b0783f13d92f007f753fd2c3ae2c8680 -Author: Dave Liu -Date: Fri Jan 11 18:42:19 2008 +0800 - - mpc83xx: Remove cache config from MPC8360ERDK.h - - The MPC8360ERDK board support patch is added before - the commit 2c5b48fc205c3e2752910da8f39209ed075929e5 - so, miss clean up it. - - The patch clean up the miss cache config. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit cd9d23053d435c08fc8695017b5cb9003fcda786 -Author: Anton Vorontsov -Date: Mon Jan 14 23:09:32 2008 +0300 - - nand: FSL UPM NAND driver - - Signed-off-by: Anton Vorontsov - -commit 6cb2239ae76faee64434286c4f8fc71374702dd2 -Author: Kyungmin Park -Date: Tue Jan 15 08:59:44 2008 +0900 - - OneNAND: Separate U-Boot dependent code from OneNAND - - OneNAND: Separate U-Boot dependent code from OneNAND - - Signed-off-by: Kyungmin Park - -commit 83a49c8dd7998be2d1f0d420597a36bbf0bf4164 -Author: Matthias Fuchs -Date: Wed Jan 16 10:33:46 2008 +0100 - - ppc4xx: Sequoia coding style cleanup and beautification - - Signed-off-by: Matthias Fuchs - -commit 4b3cc6ece9c455504cf12909fae38d085d848ac0 -Author: Larry Johnson -Date: Tue Jan 15 14:35:58 2008 -0500 - - ppc4xx: Refactor ECC POST for AMCC Denali core - - The ECC POST reported intermittent failures running after power-up on - the Korat PPC440EPx board. Even when the test passed, the debugging - output occasionally reported additional unexpected ECC errors. - - This refactoring has three main objectives: (1) minimize the code - executed with ECC enabled during the tests, (2) add more checking of the - results so any unexpected ECC errors would cause the test to fail, and - (3) use synchronization (only) where required by the processor. - - Signed-off-by: Larry Johnson - -commit 2465665b73ac2f688af945b1ed510752afa816a4 -Author: David Saada -Date: Tue Jan 15 10:40:24 2008 +0200 - - QE UEC: Extend number of supported UECs to 4 - - This patch extends the number of supported UECs to 4. Note that the - problem of QE thread resources exhaustion is resolved by setting the - correct number of QE threads according to Ethernet type (GBE or FE). - - Signed-off-by: David Saada - Signed-off-by: Ben Warren - -commit 58d204256cb1ce1bd323847d9f644acf70a72e6a -Author: Wolfgang Denk -Date: Wed Jan 16 00:01:01 2008 +0100 - - LWMON5: enable hush shell as command line parser - - Signed-off-by: Wolfgang Denk - -commit 66ffb1883feedddc813d8a507d060f2a940eb2b2 -Author: Wolfgang Denk -Date: Tue Jan 15 17:22:28 2008 +0100 - - ADS5121: disable watchdog; enable image timestamps - - Signed-off-by: Wolfgang Denk - -commit 2b4f778fe9d1de61d7445bae7b325340aba6968d -Author: Wolfgang Denk -Date: Tue Jan 15 17:21:28 2008 +0100 - - TK885D: fixes for bigger flash sector sizes on new modules; - adjust default environment; - disable SCC ethernet (not used on this board). - - Signed-off-by: Wolfgang Denk - -commit f91d7ae5ca89acf9fa1ed1015dc078cf29581607 -Author: Nobuhiro Iwamatsu -Date: Tue Jan 15 17:48:13 2008 +0900 - - pcmcia: Remove CONFIG_COMMANDS from marubun pcmcia driver - - Signed-off-by: Nobuhiro Iwamatsu - -commit 76e49aa7fb8e76cc49092c1acd53fff921e26360 -Author: Nobuhiro Iwamatsu -Date: Tue Jan 15 23:25:25 2008 +0900 - - sh: Add support SH7710/SH7712 - - SH7710/SH7712 of SH3 CPU are supported. - SH771X is called SH-Ether, and has the Ether controller in CPU. - The driver of Ether is not included in this patch. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 63a11be68306870e04d3851ed9fa41955cdf4894 -Author: Nobuhiro Iwamatsu -Date: Tue Jan 15 23:06:17 2008 +0900 - - sh: Add support of map_physmem() and unmap_physmem() to SuperH - - This patch add the support of map_physmem() and unmap_physmem() - used with Common Flash Interface(CFI) driver. - - Signed-off-by: Nobuhiro Iwamatsu - -commit db3995fe5164ac5d630b7ecb96286a9828dfbb54 -Author: Nobuhiro Iwamatsu -Date: Wed Jan 9 14:42:27 2008 +0900 - - sh: Add maintainer of MS7720SE to the MAINTAINER file - - Signed-off-by: Nobuhiro Iwamatsu - -commit dcd99e88e03d56a0aeecd42b507d2d29d20ab0e3 -Author: Nobuhiro Iwamatsu -Date: Wed Jan 9 14:39:58 2008 +0900 - - sh: Fix board name in MS7720SE's config.mk - - Signed-off-by: Nobuhiro Iwamatsu - -commit c0a04d93734d768b39dbb72fb501b65614c8615d -Author: Nobuhiro Iwamatsu -Date: Wed Jan 9 14:37:36 2008 +0900 - - sh: Add MS7720SE to MAKEALL - - Signed-off-by: Nobuhiro Iwamatsu - -commit b2b5e2bb78a1ef4ae8504f5a26bfdc3293ea74ae -Author: Yoshihiro Shimoda -Date: Mon Dec 3 22:58:50 2007 +0900 - - sh: Add support for MS7720RP02 board - - Signed-off-by: Yoshihiro Shimoda - CC: Nobuhiro Iwamatsu - Acked-by: Nobuhiro Iwamatsu - -commit 7c10c57275901939a8ece4a9ef3e7ccb7c12a0ed -Author: Yoshihiro Shimoda -Date: Wed Jan 9 14:30:02 2008 +0900 - - sh: Add support for SH7720 in serial_sh driver. - - Signed-off-by: Yoshihiro Shimoda - CC: Nobuhiro Iwamatsu - Acked-by: Nobuhiro Iwamatsu - -commit f9913a8ee71ff14fcfc1c7fd0e6912f897e69403 -Author: Yoshihiro Shimoda -Date: Mon Dec 3 22:58:45 2007 +0900 - - sh: Add support SH3 and SH7720 - - Signed-off-by: Yoshihiro Shimoda - CC: Nobuhiro Iwamatsu - Acked-by: Nobuhiro Iwamatsu - -commit 9adfc9fb9ade64cdf1ed9ff842e4f900cbda78bd -Author: Stefan Roese -Date: Tue Jan 15 10:11:02 2008 +0100 - - ppc4xx: Remove compiler warning in cpu/ppc4xx/44x_spd_ddr2.c - - Signed-off-by: Stefan Roese - -commit 17bef68097ab3692500a36fb31115bff7910aa99 -Author: Niklaus Giger -Date: Mon Jan 14 14:04:42 2008 +0100 - - ppc_4xx: Fix post spr.c for PPC405 - - post/cpu/ppc4xx/spr.c contained a few checks for registers only present - for PPC440 and derivates processor. - - Signed-off-by: Niklaus Giger - -commit 06c428bcd4413014b43236e77765022071424fa6 -Author: Dave Liu -Date: Mon Jan 14 11:12:01 2008 +0800 - - QE: fix compile warning - - qe.c: In function 'qe_upload_firmware': - qe.c:390: warning: pointer targets in passing argument 2 - uec.c: In function 'uec_initialize': - uec.c:1236: warning: 'uec_info' may be used uninitialized - - Signed-off-by: Dave Liu - -commit a0dd99d51efa55fe023e19c97ead92683725eb11 -Author: Stefan Roese -Date: Mon Jan 14 10:05:05 2008 +0100 - - ppc4xx: Update Kilauea CPLD configuration with USB PHY reset bit - - Now that bit 29 is the USB PHY reset bit, update the Kilauea port - to remove the USB PHY reset after powerup. The CPLD will keep the - USB PHY in reset (active low) until the bit is set to 1 in - board_early_init_f(). - - Signed-off-by: Stefan Roese - -commit f43ad53908f1ea83a7c26c3505bbe84382e47aad -Author: Wolfgang Denk -Date: Sun Jan 13 23:26:45 2008 +0100 - - ARM: update mach-types.h from 2.6.24-rc7 Linux kernel tree - - Signed-off-by: Wolfgang Denk - -commit 8d103071b7b0e3ec888859bfcb9d422565e6d750 -Author: Wolfgang Denk -Date: Sun Jan 13 23:37:50 2008 +0100 - - ADS5121: Fix typo in ads5121.c, adjust default environment - - Signed-off-by: Wolfgang Denk - -commit 51b67d06faa670c65de6f29ec5b5aace74b2a047 -Author: John Rigby -Date: Fri Aug 24 18:18:43 2007 -0600 - - ADS5121: MAX slew rate for PATA pins - - Signed-off-by: John Rigby - -commit dd531aac34aaad138f16cacdb51d61908d59c0e2 -Author: Wolfgang Denk -Date: Sun Jan 13 21:05:52 2008 +0100 - - Fix Makefile dependency problem with parallel builds. - - Signed-off-by: Wolfgang Denk - -commit 89967841e3ea02e3d0e5e1295ab687576e5b1089 -Author: Wolfgang Denk -Date: Sun Jan 13 19:51:39 2008 +0100 - - MPC8544DS: fix board Makefile for silent build (with -s) - - Signed-off-by: Wolfgang Denk - -commit 6d714f82fb4b8bb7e267e9c71b8009bc670bfe88 -Author: Wolfgang Denk -Date: Sun Jan 13 16:44:08 2008 +0100 - - PMC440 board: fix board Makefile for out-of-tree building - - Signed-off-by: Wolfgang Denk - -commit 6eb3fb15588d319bd3099d5f9b910051dfeab6b2 -Author: Wolfgang Denk -Date: Sun Jan 13 16:07:44 2008 +0100 - - Makalu: fix compile warning - - Signed-off-by: Wolfgang Denk - -commit 0a1e03bcadc7734688a21e8dd2e46a4f608193c0 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Jan 13 12:36:12 2008 +0100 - - cmd_nand : fix compiler warning. - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 8225d1e3ac0ab147cdde4b0042812583380afb8a -Author: Michael Schwingen -Date: Sat Jan 12 20:29:47 2008 +0100 - - CFI: Fix CONFIG_FLASH_CFI_LEGACY compilation - - Signed-off-by: Michael Schwingen - Acked-by: Stefan Roese - -commit 2b2f43ed6a30ece77f76191c845ac95267daa31a -Author: Wolfgang Denk -Date: Sun Jan 13 02:19:44 2008 +0100 - - MPC8360ERDK: fix incorrect initialization of CFG_I2C_NOPROBES - - Signed-off-by: Wolfgang Denk - -commit 08e99e1dd01a3e0e3dc3a7138eb827c997e2b74d -Author: Wolfgang Denk -Date: Sun Jan 13 02:19:13 2008 +0100 - - MPC8xx FEC driver: fix compiler warning. - - Signed-off-by: Wolfgang Denk - -commit ae6d1056d2c2e4d1266413c0ae8a6d5529ecde4b -Author: Wolfgang Denk -Date: Sun Jan 13 00:59:21 2008 +0100 - - Fix Makefile dependencies issues; allow silent build - - - get rid of "version" target whichdidn't really work - - make autoconf.mk depend on version_autogenerated.h to make sure - to rebuild files as needed - - add XECHO macro to allow for silent build using "make -s" - - Signed-off-by: Wolfgang Denk - -commit e343ab83d5135b558aa58db9be8fc7faa68d77ed -Author: Wolfgang Denk -Date: Sun Jan 13 00:55:47 2008 +0100 - - ADS5121e: fix compile warning - - Signed-off-by: Wolfgang Denk - -commit f2b6f4610627fe3d607620e25082916a01538875 -Author: Wolfgang Denk -Date: Sun Jan 13 00:55:18 2008 +0100 - - MUNICes: fix board Makefile for remote build directory - - Signed-off-by: Wolfgang Denk - -commit 2ad4d3999fe801aa716221d7d9a4c5bdad74783a -Author: Oliver Weber -Date: Wed Jan 9 17:04:38 2008 +0100 - - MPC5200: don't use hardcoded MBAR address in Bestcomm firmware - - Signed-off-by: Oliver Weber - -commit 00ac50e348d1bace27a174b7f528d113bc7cdf7f -Author: Andreas Engel -Date: Wed Jan 9 17:10:56 2008 +0100 - - Make bootretry work when command line editing is enabled - - Currently, when CONFIG_CMDLINE_EDITING is set, bootretry doesn't work. - This patch fixes the problem. - - Signed-off-by: Andreas Engel - -commit 632de0672d3c3ab53ad798c47f5f1eb26008a0e4 -Author: Larry Johnson -Date: Fri Jan 11 23:26:18 2008 -0500 - - Refactor code for "i2c sdram" command - - Signed-off-by: Larry Johnson - -commit 0df6b8446c4721b91ce311548114891130371083 -Author: Larry Johnson -Date: Thu Jan 10 22:23:39 2008 -0500 - - Fix "i2c sdram" command for DDR2 DIMMs - - Many of the SPD bytes for DDR2 SDRAM are not interpreted correctly by the - "i2c sdram" command. This patch provides correct alternative - interpretations when DDR2 memory is detected. - - Signed-off-by: Larry Johnson - -commit 64134f011254123618798ff77c42ba196b2ec485 -Author: Wolfgang Denk -Date: Sat Jan 12 20:31:39 2008 +0100 - - Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections - - With recent toolchain versions, some boards would not build because - or errors like this one (here for ocotea board when building with - ELDK 4.2 beta): - ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] - - For many boards, the .bss section is big enough that it wraps around - at the end of the address space (0xFFFFFFFF), so the problem will not - be visible unless you use a 64 bit tool chain for development. On - some boards however, changes to the code size (due to different - optimizations) we bail out with section overlaps like above. - - The fix is to add the NOLOAD attribute to the .bss and .sbss - sections, telling the linker that .bss does not consume any space in - the image. - - Signed-off-by: Wolfgang Denk - -commit 3afac79ec27b91df185f090b31dad9620779f440 -Author: TsiChung Liew -Date: Fri Jan 11 20:42:58 2008 -0600 - - USB: Add Philips 1561 PCI-OHCI ids - (needed for M5475EVB) - - Signed-off-by: TsiChungLiew - -commit 5e8def6731cd7bec74bff42a16b139de04010353 -Author: Wolfgang Denk -Date: Sat Jan 12 15:51:34 2008 +0100 - - Add MAINTAINERS entries for ids8247, jupiter, municse, sc3 and uc101 - boards. - - Signed-off-by: Heiko Schocher - Signed-off-by: Wolfgang Denk - -commit 5d49e0e152a8b81cc0602271e8fd259371f559b7 -Author: Grzegorz Bernacki -Date: Fri Jan 11 12:03:43 2008 +0100 - - MPC512X: Cleanup bus clock names. - - Signed-off-by: Grzegorz Bernacki - -commit 66a9455b6bf46d69cec5c88d1a600d1d9a10670d -Author: Grzegorz Bernacki -Date: Tue Jan 8 17:16:59 2008 +0100 - - MPC512X: Fixed typo in macro name. - - Signed-off-by: Grzegorz Bernacki - -commit 281ff9a45cf9eb17b8a9afc436cb783cf1f62363 -Author: Grzegorz Bernacki -Date: Tue Jan 8 17:16:15 2008 +0100 - - ads5121: Added support for FDT. - - Signed-off-by: Grzegorz Bernacki - -commit a10ff9196183e7e5f2ae3c4f5f3cbe92ae9cb719 -Author: Wolfgang Denk -Date: Sat Jan 12 01:05:50 2008 +0100 - - Coding Style cleanup; update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit f6db945649e5e9d0c7efe33b507d243cdc86cf03 -Author: Heiko Schocher -Date: Fri Jan 11 15:15:17 2008 +0100 - - Fixed syntax error in function init_e300_core() of mpc83xx/start.S if - - Signed-off-by: Timur Tabi - Signed-off-by: Heiko Schocher - -commit fa05664cd8c7ab1ecf062aa73b992b7b58bba49c -Author: Heiko Schocher -Date: Fri Jan 11 15:15:16 2008 +0100 - - MUNICes: Set the right CFG_DEFAULT_MBAR value. - - Signed-off-by: Heiko Schocher - -commit 5fb2b2342ece8d786c6f7fdba1bc273febd3b3d2 -Author: Heiko Schocher -Date: Fri Jan 11 15:15:15 2008 +0100 - - added the config File for the MUNICes board. - - Signed-off-by: Heiko Schocher - -commit 6341d9d723b71b4c0bf86f979e4cb228c02fd09d -Author: Heiko Schocher -Date: Fri Jan 11 15:15:14 2008 +0100 - - added basic support for the MUNICes board. - - Signed-off-by: Heiko Schocher - -commit 3bb77fb09a1caabf5a292cc5b486a78b977fbe19 -Author: Wolfgang Denk -Date: Sat Jan 12 00:39:37 2008 +0100 - - Update CHANGELOG and MAINTAINERS files. - - Signed-off-by: Wolfgang Denk - -commit 5ba7390c3cb579172be66888a371707b47b5be4e -Author: Anatolij Gustschin -Date: Fri Jan 11 02:15:02 2008 +0100 - - Fix compilation problem in common/cmd_bmp.c - - common/cmd_bmp.c fails to compile if CONFIG_VIDEO_BMP_GZIP - isn't defined. This patch fix this. - - Signed-off-by: Anatolij Gustschin - -commit 5aa437baae5fe629abeab99bef793a2a1fc71b58 -Author: Heiko Schocher -Date: Fri Jan 11 01:12:09 2008 +0100 - - Fix defaultconfig for the mgcoge board. - - Signed-off-by: Heiko Schocher - -commit ac9db066b26935f31bff15c98168b19faeb603f3 -Author: Heiko Schocher -Date: Fri Jan 11 01:12:08 2008 +0100 - - Added support for the mgcoge board from keymile. - - Signed-off-by: Heiko Schocher - -commit b423d055cc2e13c4ef1f0389c3fa2988d0eed818 -Author: Heiko Schocher -Date: Fri Jan 11 01:12:07 2008 +0100 - - Enable SMC microcode relocation patch for SMC1. - - Signed-off-by: Heiko Schocher - -commit 381e4e639720d8d2efb8066c7c48ec9588cb28c7 -Author: Heiko Schocher -Date: Fri Jan 11 01:12:06 2008 +0100 - - Added support for the mgsuvd board from keymile. - - Signed-off-by: Heiko Schocher - -commit bf05293973b348f6946c9df92cd3c65ece42d0be -Author: James Yang -Date: Thu Jan 10 16:02:07 2008 -0600 - - Fix 64-bit vsprintf. - - There were some size and unsigned problems. - Also add support for "ll" size modifier in format string like glibc - - Signed-off-by: James Yang - Acked-by: Jon Loeliger - -commit 92fa37eac530860643afa26ae347af3d23d67309 -Author: Larry Johnson -Date: Wed Jan 9 12:42:35 2008 -0500 - - Remove superfluous preprocessor conditionals from LM73 driver - - (1) Remove unused symbol "CFG_EEPROM_PAGE_WRITE_ENABLE". - - (2) Use conditional Makefile.o. - - Signed-off-by: Larry Johnson - -commit efc6f447c1b940d1650c4b854c5598a595ddc3da -Author: Guennadi Liakhovetski -Date: Thu Jan 10 17:59:07 2008 +0100 - - Add support for the TK885D baseboard from TELE-DATA - - The TK885D board uses a TQM885D module from TQ, this port adds an - own configuration file and adds a last_stage_init() method to - configure the two PHYs, depending on the phy_auto_nego environment - variable. - - Signed-off-by: Guennadi Liakhovetski - -commit 0ec595243dc99edcd248bbcfbfd5a1dc860bde89 -Author: Kumar Gala -Date: Thu Jan 10 02:22:05 2008 -0600 - - Fix compiler warning - - main.c: In function 'readline_into_buffer': - main.c:927: warning: unused variable 'p_buf' - - Signed-off-by: Kumar Gala - -commit bed53753dd1d7e6bcbea4339be0fb7760214cc35 -Author: Anatolij Gustschin -Date: Fri Jan 11 14:30:01 2008 +0100 - - Add Fujitsu CoralP/Lime video driver - - Signed-off-by: Anatolij Gustschin - Signed-off-by: Rodolfo Giometti - -commit 20c450ef61ef2eb1c96f9b59ba0eb8d849bba058 -Author: Anatolij Gustschin -Date: Fri Jan 11 02:39:47 2008 +0100 - - Fix video console newline and carriage return handling - - Lines of the lenght CONSOLE_COLS or greater than CONSOLE_COLS - are not displayed correctly. This is an attempt to fix - this issue. Also add carriage return handling. - - Signed-off-by: Anatolij Gustschin - Signed-off-by: Rodolfo Giometti - -commit d5a163d6baa04f5a8edcc10ebc6fad08657d3093 -Author: Stefan Roese -Date: Fri Jan 11 15:53:58 2008 +0100 - - ppc4xx: Fix sdram init on Sequoia boards - - Clear possible errors in MCSR resulting from data-eye-search. - If not done, then we could get an interrupt later on when - exceptions are enabled. - - Signed-off-by: Stefan Roese - -commit d610a60730b7464f6f659db49d264d89a7c71061 -Author: Anatolij Gustschin -Date: Fri Jan 11 15:31:09 2008 +0100 - - ppc4xx: Rework Lime support for lwmon5 - - Rework Lime support for lwmon5 using new video driver - - Signed-off-by: Anatolij Gustschin - -commit ff41ffc93c1592e77a44bdbebd5d781739f3aae0 -Author: Matthias Fuchs -Date: Fri Jan 11 14:55:16 2008 +0100 - - ppc4xx: Update PMC440 config file - - Signed-off-by: Matthias Fuchs - -commit e3edcb36f14f0aabb6f50e96014d6877f73d64ea -Author: Matthias Fuchs -Date: Fri Jan 11 14:55:08 2008 +0100 - - ppx4xx: Fix sdram init on PMC440 boards - - Signed-off-by: Matthias Fuchs - -commit 061aad4d320dddce26247699dcf2875ee2ea1366 -Author: Dave Liu -Date: Thu Jan 10 23:09:33 2008 +0800 - - mpc83xx: Fix the bug of 266MHz data rate DDR - - The DDR doesn't work on the 266MHz data rate, - the patch fix the bug. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit ded08317ad9e340b887bf2eb46e9565a0f610a93 -Author: Dave Liu -Date: Thu Jan 10 23:08:26 2008 +0800 - - mpc83xx: Make the code more readable - - Format the code, make it more readable - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 7e74d63d1a211fbc34ec424e2dc6726601f323d0 -Author: Dave Liu -Date: Thu Jan 10 23:07:23 2008 +0800 - - mpc83xx: Reduce the latency of DDR - - Reduce the AL from 2 to 1 clock to improve the performance. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 6f3931a2bed5412c20d5e5536c865fbd657f7d28 -Author: Dave Liu -Date: Thu Jan 10 23:06:05 2008 +0800 - - mpc83xx: Fix the wrong definition of MPC8315E - - According to the latest user manual of MPC8315E, - 1) The SVCOD of HRCWL is different than 837x - 2) The SCCR has changes - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit ec2638ea08a537a1bd409db873aaaa33a053ebae -Author: Dave Liu -Date: Thu Jan 10 23:05:00 2008 +0800 - - mpc83xx: Fix the typo in mpc83xx.h - - The SPCR about TSEC priority is wrong. - - Signed-off-by: Michael Barkowski - Signed-off-by: Joe D'Abbraccio - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit c86ef2cd9ef81935049231fa89f36c7b793f2d4b -Author: Dave Liu -Date: Thu Jan 10 23:04:13 2008 +0800 - - mpc83xx: Fix the typo in global data struct - - Fix the typo in global_data.h - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 2c5b48fc205c3e2752910da8f39209ed075929e5 -Author: Dave Liu -Date: Thu Jan 10 23:03:03 2008 +0800 - - mpc83xx: Remove cache config from config.h - - clean up the cache config from configs.h of board - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit fab6f556bbbbd1bb35a5433161f7f173c18df559 -Author: Anton Vorontsov -Date: Wed Jan 9 20:57:47 2008 +0300 - - mpc83xx: add support for the MPC8360E-RDK - - This is MPC8360E based board with: - - 256MB fixed SDRAM; - - 8MB Intel Strata NOR flash; - - StMICRO 64MiB NAND flash; - - two 10/100/1000 ethernet ports connected via Broadcom - BCM5481 PHYs; - - two 10/100 ethernet ports connected via National - DP83848 PHYs; - - one PCI and one miniPCI slots; - - four serial ports (two NS16550-compatible, two UCCs); - - four USB ports working through MPC8360E "FHCI" USB controller; - - Fujitsu MB86277 graphics controller; - - Analog to Digital Converter/Touchscreen controller, AD7843 - connected to SPI. - - Features not supported in this patch are: - - StMICRO 64MiB NAND flash (patch sent); - - MINT framebuffer initialization (patch is pending); - - Fetching production information from the EEPROM via I2C; - - FHCI USB; - - Two slow UCCs used as RS-485 UARTs. - - Signed-off-by: Anton Vorontsov - Signed-off-by: Kim Phillips - -commit b3d2cde7a3aa1e83b7968cdff929e52c8cc617bb -Author: Anton Vorontsov -Date: Wed Jan 9 20:57:40 2008 +0300 - - mpc83xx: add "fsl, qe" compatible fixups - - New device trees will use "fsl,qe" compatible properties. - - Signed-off-by: Anton Vorontsov - Signed-off-by: Kim Phillips - -commit 977b57583a7c34010e566a09a679ec3c1836f996 -Author: Kim Phillips -Date: Wed Jan 9 15:24:06 2008 -0600 - - mpc83xx: add missing CONFIG_HAS_ETH0 defines - - the new libfdt code only updates eth0 if CONFIG_HAS_ETH0 - is defined; add the define to the missing board configs. - - Thanks to Emilian Medve for finding this. - - Signed-off-by: Kim Phillips - -commit b830b7f1635984ba607219fcbd78597c28eeb529 -Author: Becky Bruce -Date: Thu Jan 10 14:00:28 2008 -0600 - - 86xx: Support 2GB DIMMs - - Configure the number of bits used to address the banks inside the SDRAM - device. The default register value of 0 means 2 bits to address 4 banks. - Higher capacity devices like a 2GB DIMM require 3 bits to address 8 banks. - - Signed-off-by: Becky Bruce - -commit 4d332dbeb08f5863d1ea69d91a00c5499d3a87ed -Author: Niklaus Giger -Date: Thu Jan 10 18:50:33 2008 +0100 - - ppc4xx: Make Sequoia boot vxWorks - - vxWorks expects in - TLB 0 a entry for the Machine Check interrupt - TLB 1 a entry for the RAM - TLB 2 a entry for the EBC - TLB 3 a entry for the boot flash - - After changing the baudrate to 9600 I had no problems to boot the - vxWorks image as distributed by WindRiver (Revision 2.0/1 from - June 18, 2007) - - Signed-off-by: Niklaus Giger - -commit 6d8184b00c0d1d7090e4a2f514e310d98a394f8d -Author: Larry Johnson -Date: Wed Jan 9 23:10:27 2008 -0500 - - ppc4xx: Fix dflush() to restore DVLIM register - - Signed-off-by: Larry Johnson - -commit 252f60b068d1f94190b5bcfda169db582387e15e -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Thu Jan 10 03:52:44 2008 -0500 - - Nios2: remove common/cmd_bdinfo.c unused variable. - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Scott McNutt - -commit 422b1a01602b6e2fbf8444a1192c7ba31461fd4c -Author: Ben Warren -Date: Wed Jan 9 18:15:53 2008 -0500 - - Fix Ethernet init() return codes - - Change return values of init() functions in all Ethernet drivers to conform - to the following: - - >=0: Success - <0: Failure - - All drivers going forward should return 0 on success. Current drivers that - return 1 on success were left as-is to minimize changes. - - Signed-off-by: Ben Warren - Acked-by: Stefan Roese - Acked-by: Jean-Christophe PLAGNIOL-VILLARD - Acked-by: Kim Phillips - Acked-by: Haavard Skinnemoen - Acked-By: Timur Tabi - -commit d3a6532cbe263d992f49e86ac95bede28e96f9c8 -Author: Wolfgang Denk -Date: Thu Jan 10 00:55:14 2008 +0100 - - Coding Style cleanup; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 17a41e4492121ccf9fa2c10c2cb1a6d1c18d74f7 -Author: Kim Phillips -Date: Wed Jan 9 16:56:54 2008 -0600 - - Add QE brg freq and correct qe bus freq fdt update code - - Signed-off-by: Kim Phillips - Signed-off-by: Andy Fleming - -commit 890dfef06c2d169a3356359596890754dfb8ee1c -Author: Andy Fleming -Date: Wed Jan 9 16:34:51 2008 -0600 - - Remove cache config from ATUM8548 and sbc8548 configs - - These boards weren't updated by Kumar's config patch because they - weren't in the tree, yet. - - Signed-off-by: Andy Fleming - -commit b8ec2385038c094b07ec5b49336289a46b6e9cc6 -Author: Timur Tabi -Date: Mon Jan 7 13:31:19 2008 -0600 - - 85xx: add ability to upload QE firmware - - Define the layout of a binary blob that contains a QE firmware and instructions - on how to upload it. Add function qe_upload_firmware() to parse the blob and - perform the actual upload. Add command-line command "qe fw" to take a firmware - blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the - 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define - 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. - - Signed-off-by: Timur Tabi - -commit b009f3eca99bb7b9e6ba6639a8909a138dd5e9fe -Author: Kumar Gala -Date: Tue Jan 8 01:22:21 2008 -0600 - - 85xx: Remove cache config from configs.h - - Either use the standard defines in asm/cache.h or grab the information - at runtime from the L1CFG SPR. - - Also, minor cleanup in cache.h to make the code a bit more readable. - - Signed-off-by: Kumar Gala - -commit b964e9368f45372aaf1da0c13fe56f6d81ae8e96 -Author: robert lazarski -Date: Fri Dec 21 10:39:27 2007 -0500 - - mpc85xx: Add support for ATUM8548 (updated) - - Add support for Instituto Atlantico's ATUM8548 board - - Signed-off-by: robert lazarski - Signed-off-by: Andy Fleming - -commit 7bd6104b71de9bca80ac8e0936003443bb42f2fc -Author: robert lazarski -Date: Fri Dec 21 10:36:37 2007 -0500 - - mpc85xx: Add support for ATUM8548 (updated) - - Add support for Instituto Atlantico's ATUM8548 board - - Signed-off-by: robert lazarski - -commit 9e3ed392d2c8965e24c942b58796c31c644c2f70 -Author: Joe Hamman -Date: Thu Dec 13 06:45:14 2007 -0600 - - mpc85xx: Add support for SBC8548 (updated) - - Add support for Wind River's SBC8548 reference board. - - Signed-off by: Joe Hamman - -commit 11c45ebd46d6517b51b7a92dd52a618b2f4e5586 -Author: Joe Hamman -Date: Thu Dec 13 06:45:08 2007 -0600 - - mpc85xx: Add support for SBC8548 (updated) - - Add support for Wind River's SBC8548 reference board. - - Signed-off by: Joe Hamman - Signed-off by: Andy Fleming - -commit 64d4bcb087c2ece1c4d0de8efe85e0075e5b1594 -Author: Anton Vorontsov -Date: Mon Oct 22 19:58:19 2007 +0400 - - MPC8568E-MDS: set up QE pario for UART1 - - To use UART1 on the MPC8568E-MDS, QE pario pins PC[0:3] should - be set up appropriately. - - Signed-off-by: Anton Vorontsov - -commit ad162249cb371e9e38971676f09be791e5f3cf4a -Author: Anton Vorontsov -Date: Mon Oct 22 18:12:46 2007 +0400 - - MPC8568E-MDS: reset UCCs to use them reliably - - In order to use GETH1 and GETH2 on the MPC8568E-MDS, we should reset - UCCs. - - p.s Similar code exists in the Linux kernel board file (for capability - reasons with older U-Boots), but should be removed some day. - - Signed-off-by: Anton Vorontsov - -commit 2146cf56821c3364786ca94a7306008c5824b238 -Author: Kumar Gala -Date: Wed Dec 19 01:18:15 2007 -0600 - - Reworked FSL Book-E TLB macros to be more readable - - The old macros made it difficult to know what WIMGE and perm bits - were set for a TLB entry. Actually use the bit masks for these items - since they are only a single bit. - - Also moved the macros into mmu.h out of e500.h since they aren't specific - to e500. - - Signed-off-by: Kumar Gala - -commit 1d47273d46925929f8f2c1913cd96d7257aade88 -Author: Kumar Gala -Date: Tue Dec 18 23:21:51 2007 -0600 - - Use FSL Book-E MMU macros from Linux Kernel - - Grab the FSL Book-E MAS register macros from Linux. Also added - defines for page sizes up to 4TB and removed SHAREN since it doesnt - really exist. - - Signed-off-by: Kumar Gala - -commit 02df4a270f817ef6ec39047a01b55fecdc5f3b37 -Author: Andy Fleming -Date: Wed Jan 9 13:51:32 2008 -0600 - - Fix my own merge stupidity - - Way back in August I merged Heiko's patch: - 566a494f592: [PCS440EP] upgrade the PCS440EP board - - with Jon's CONFIG_COMMANDS patches. - - This was done in commit: 6bf6f114dcdd97ec3f80c2761ed40e31229d6b78 - - However, in the process, I left out some of Heiko's good changes. - - Now Heiko's and Jon's patches are properly merged in fat_register_device() - - Signed-off-by: Andy Fleming - -commit 6636b62a6efc7f14e6e788788631ae7a7fca4537 -Author: James Yang -Date: Wed Jan 9 11:17:49 2008 -0600 - - Expose parse_line() globally. - - Add new function readline_into_buffer() that allows the - output of readline to be put into a pointer to char buffer. - - This refactoring allows other functions besides the - main command loop to also use the same input mechanism. - - Signed-off-by: James Yang - Acked-by: Jon Loeliger - -commit 7ca90513486abd4ae50bd1b7403f47cc58c5ad25 -Author: Guennadi Liakhovetski -Date: Wed Jan 9 01:15:25 2008 +0100 - - trivial: fix consequences of a bad merge - - Fix what looks like a merge artifact. - - Signed-off-by: Guennadi Liakhovetski - -commit 4785a694c0045996ccf0ac5b8edf531efc1b730e -Author: Zhang Wei -Date: Thu Jan 3 10:51:15 2008 +0800 - - Add Ctrl combo key support to usb keyboard driver. - - Ctrl combo key support is added, which is very useful to input Ctrl-C - for interrupt current job. - Also add usb_event_poll() calling to usb_kbd_testc(), which can get - key input when tstc() is called. - - Signed-off-by: Zhang Wei - -commit 10c7382bc5d5e64c47f94ac2ca78cc574442e82d -Author: Marcel Ziswiler -Date: Sun Dec 30 03:30:56 2007 +0100 - - fix various comments - - Signed-off-by: Marcel Ziswiler - -commit 7817cb2083d982923752fe0f12b67c0e7c09a027 -Author: Marcel Ziswiler -Date: Sun Dec 30 03:30:46 2007 +0100 - - fix comments with new drivers organization - - Signed-off-by: Marcel Ziswiler - -commit a9b410dc7d2a4721c408b13abfc037988150f145 -Author: Shinya Kuribayashi -Date: Fri Dec 28 12:50:59 2007 +0900 - - Remove the obsolete terse version of do_mii() - - We now have more useful version of do_mii() and everybody use it. - Gerald Van Baren says: - - > When I originally wrote the mii command 6(!) years ago, I wrote a - > verbose version that printed human readable decomposition of the flags, - > etc., and a terse one that didn't print as much stuff and thus had a - > smaller memory footprint. - > - > It sounds like the terse version has withered and died, apparently - > people are only using the verbose version (which is very understandable, - > I do myself). - - Signed-off-by: Shinya Kuribayashi - Signed-off-by: Gerald Van Baren - -commit 01c687aa6e065bd4faf80f723361e798941dd6b0 -Author: Mike Frysinger -Date: Thu Dec 27 13:42:56 2007 -0500 - - Do not reference sha1.c when building mkimage. - - remove sha1.o from mkimage linking since it isn't actually used. - - Signed-Off-By: Mike Frysinger - -commit b9173af73e524d37c812f210173cf83385c5171a -Author: Shinya Kuribayashi -Date: Thu Dec 27 15:39:54 2007 +0900 - - common/cmd_mii.c: Add sanity argc check - - If type mii command without arguments, we suffer from uninitialized argv[] - entries; for example we MIPS get stuck by TLB error. - - Signed-off-by: Shinya Kuribayashi - -commit 500856eb1707ed17d9204baa61dd59948d3b2899 -Author: Rafal Jaworowski -Date: Wed Jan 9 19:39:36 2008 +0100 - - API for external applications. - - This is an API for external (standalone) applications running on top of - U-Boot, and is meant to be more extensible and robust than the existing - jumptable mechanism. It is similar to UNIX syscall approach. See api/README - for more details. - - Included is the demo application using this new framework (api_examples). - - Please note this is still an experimental feature, and is turned off by - default. - - Signed-off-by: Rafal Jaworowski - -commit fe8dd0b2220b7c02b0d4c9c4f9967879970477b1 -Author: Jon Loeliger -Date: Wed Jan 9 12:14:55 2008 -0600 - - 86xx: Remove cache config from configs.h - - Just use the standard defines in asm/cache.h. - - Signed-off-by: Jon Loeliger - -commit 26a41790f8eba19ad450e18ae91351daf485b3e2 -Author: Rafal Jaworowski -Date: Wed Jan 9 18:05:27 2008 +0100 - - Globalize envmatch() - - The newly introduced API (routines related to env vars) will need to call - it. - - Signed-off-by: Rafal Zabdyr - -commit 1df170f8b2a99e1e2f940f9f0b56511e1e4c9e1f -Author: Jon Loeliger -Date: Fri Jan 4 12:07:27 2008 -0600 - - Convert MPC8610HPCD to use libfdt. - - Assumes the presence of the aliases node in the DTS to - locate the pci and serial nodes for fixups. - - Use consistent fdtaddr and fdtfile in environment variables. - - Signed-off-by: Jon Loeliger - -commit c9974ab0a4d3731cdb76a7599d9fe9445d764d60 -Author: Jon Loeliger -Date: Fri Jan 4 11:58:23 2008 -0600 - - 8610: Fix lingering compile warnings. - - Turn off DEBUG. - - Signed-off-by: Jon Loeliger - -commit 6007f3251c0967adc13f2ed8be1b924ddc30124d -Author: Wolfgang Denk -Date: Wed Jan 9 15:14:46 2008 +0100 - - Coding Style cleanup, update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit fc6414eca55f1fc108fb12fc8cdc43bd8b4463f9 -Author: Mike Frysinger -Date: Tue Dec 18 04:29:55 2007 -0500 - - fix easylogo on big endian dev systems - - didnt realize how out of shape easylogo actually was until i tried using it. - this patch does byte swapping as need be on the input tga header since the tga - is in little endian but the host could just as well be big endian. i didnt - bother using bswap macros or such stuff from system headers as nothing in - POSIX dictates byte swapping functionality. - - Signed-Off-By: Mike Frysinger - -commit 38d299c2db81bd889c601b5dfc12c4e83ef83333 -Author: Mike Frysinger -Date: Tue Dec 18 03:23:25 2007 -0500 - - cleanup easylogo - - - make the Makefile not suck - - include proper headers for prototypes - - fix obvious broken handling of strchr() when handling '.' in filenames - - Signed-Off-By: Mike Frysinger - -commit 883e3925d99a8dd69c5b0201cba5b1887f88f95c -Author: raptorbrino@aim.com -Date: Thu Dec 13 21:23:28 2007 -0500 - - Fix build problems under Cygwin - - This patch allows u-boot to build without error in a cygwin - environment. Cygwin does not define __u64 in it's - include/asm/types.h file. The -idirafter flag in the u-boot - build causes the inclusion of the cygwin types.h file as opposed - to u-bot/include/asm/types.h file which does define __u64. - Subsequently, sha1.c compile fails due to unknown symbol. - - Signed-off-by: Brian Miller - -commit 43ef1c381f9195504a2488f5cb909227eb97d475 -Author: Hans-Christian Egtvedt -Date: Fri Nov 30 17:29:59 2007 +0100 - - cmd_bmp: Add support for displaying gzip compressed bmps - - The existing code can show information about a gzip compressed BMP - image, but can't actually display it. - - Therefore, move the decompression code out of bmp_info() and use it in - bmp_display() as well in order to display a compressed BMP image. - - Also, clean things up a bit and fix a memory leak while we're at it. - - [hskinnemoen@atmel.com: a bit of refactoring] - Signed-off-by: Haavard Skinnemoen - -commit d197ffd8172c6fdef38733424640a9a47295d6e9 -Author: Guennadi Liakhovetski -Date: Thu Nov 29 21:15:56 2007 +0100 - - Fix and optimize MII operations on FEC (MPC8xx) controllers - - This patch fixes several issues at least on a MPC885 based system with two - FEC interfaces used in MII mode. - - 1. PHY discovery should first read PHY_PHYIDR2 register and only then - PHY_PHYIDR1 like cpu/mpc8xx/fec.c::mii_discover_phy() does it, - otherwise the values read are wrong. Also notice, that PHY discovery - cannot work on MPC88x / MPC87x in setups with both FECs active at all - in its present form, because for both interfaces the registers from FEC - 1 are used to communicate over MII. - - 2. Remove code duplication for resetting the FEC by isolating it into a - separate function. - - 3. Initialize MII on FEC 1 when communicating over FEC 2 in fec_init(). - - 4. Optimize mii_init() to only reset the FEC 1 controller once. - - 5. Fix a typo in mii_init() using index i instead of j thus potentially - leading to unpredictable results. - - Signed-off-by: Guennadi Liakhovetski - -commit 6a5e1d75bf106fa157e9ce68bcaf4b13e8a1d214 -Author: Guennadi Liakhovetski -Date: Tue Nov 20 13:14:20 2007 +0100 - - Fix endianness conversions in rtl8169 driver - - It is unclear on what platforms this driver has been tested, since - noone up to now defines CONFIG_RTL8169 in the board configuration - header. Now it has been fixed for a big-endian mpc8241 based - linkstation platform. This patch presents the necessary endianness - conversion fixes. - - Signed-off-by: Guennadi Liakhovetski - -commit 58694f9709c0c3e3178e349ae748d98cfb0c639a -Author: Zhang Wei -Date: Thu Jan 3 10:51:15 2008 +0800 - - Add Ctrl combo key support to usb keyboard driver. - - Ctrl combo key support is added, which is very useful to input Ctrl-C - for interrupt current job. - Also add usb_event_poll() calling to usb_kbd_testc(), which can get - key input when tstc() is called. - - Signed-off-by: Zhang Wei - Signed-off-by: Markus Klotzbuecher - -commit 07eb02687f008721974a2fb54cd7fdc28033ab3c -Author: Wolfgang Denk -Date: Wed Jan 9 13:43:38 2008 +0100 - - Coding Style clenaup; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit c26acc1a43b31ddca5add42fd0360ff0eee90c80 -Author: Matthias Fuchs -Date: Thu Dec 27 17:13:11 2007 +0100 - - Remove bit swapping in Xilinx Spartan bitfile loading - - This patch removes the unnecessary bit swapping when - booting .bit files with the 'fpga loadb' command. - - Signed-off-by: Matthias Fuchs - -commit 437fc7327f0611f82937858f2d80e4cd61b40984 -Author: Matthias Fuchs -Date: Thu Dec 27 17:13:05 2007 +0100 - - Fix MSB check in Xilinx Spartan slave serial mode - - Signed-off-by: Matthias Fuchs - -commit 3bff4ffa33729a42645e328a21e8d16488872958 -Author: Matthias Fuchs -Date: Thu Dec 27 17:12:56 2007 +0100 - - Add new Xilinx Spartan FPGA types - - Signed-off-by: Matthias Fuchs - -commit 21d39d598c4e74d4e7761608c79dba2715d40a4c -Author: Matthias Fuchs -Date: Thu Dec 27 17:12:43 2007 +0100 - - Add pre and post configuration callbacks for Spartan FPGAs - - This patch adds a post configuration callback for Spartan2/3 FPGAs. - pre and post configuration callback are now optional and - not called when the function pointer is set to NULL. - - Signed-off-by: Matthias Fuchs - -commit 0133502e39ff89b67c26cb4015e0e7e8d9571184 -Author: Matthias Fuchs -Date: Thu Dec 27 17:12:34 2007 +0100 - - Improve configuration of FPGA subsystem - - This patch removes the FPGA subsystem configuration through - the CONFIG_FPGA bitmask configuration option. - - See README for the new options: - - CONFIG_FPGA, - CONFIG_FPGA_, - CONFIG_FPGA_ - - Signed-off-by: Matthias Fuchs - -commit 95c6bc7d4a3588b452baca610f8c795a83630477 -Author: Matthias Fuchs -Date: Thu Dec 27 16:55:17 2007 +0100 - - Add Epson RX8025 RTC support - - Signed-off-by: Matthias Fuchs - -commit 1208a2dfde02bedd3c5bda29a606632b8e0be058 -Author: Matthias Fuchs -Date: Thu Dec 27 16:57:23 2007 +0100 - - serial: Make default_serial_console() a weak function - - With this patch it is possible to reimplement default_serial_console() - in board specific code. This will be done in the upcomming PMC440 - U-Boot port. This also allows the lwmon board maintainer to - remove the '#if !defined(CONFIG_LWMON) ...' from common/serial.c. - - Signed-off-by: Matthias Fuchs - -commit d16471ee05ce7ac5392bc0e9fe3ff4b58a768f33 -Author: Harald Welte -Date: Wed Dec 19 14:14:47 2007 +0100 - - add 'terminal program' functionality - - This patch adds a 'cu' like serial terminal command to u-boot - using which you can access other serial ports from the system console. - - OpenMoko uses this in their Neo1973 phones to get access to the GSM - Modem and GPS chip from the bootloader. - - Signed-off-by: Harald Welte - -commit 62d4f4365341576f5a5307b2b205a5aa2e3c6be6 -Author: Harald Welte -Date: Wed Dec 19 14:12:53 2007 +0100 - - Re-introduce the 'nand read.oob' and 'nand write.oob' commands - that used to exist with the legacy NAND code - - Signed-off-by: Harald Welte - -commit f540c42d9564854b19ce9bbb70affe172529fe70 -Author: Harald Welte -Date: Wed Dec 19 14:09:58 2007 +0100 - - Fix building with CRAMFS but not JFFS2 support - - Signed-off-by: Harald Welte - -commit 23d0baf967fecdaf1804f045f6339337c5607eec -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Dec 22 15:52:58 2007 +0100 - - Allow CONFIG_AUTO_COMPLETE and command history CONFIG_CMDLINE_EDITING at the sametime - - Signed-off-by: Mike Frysinger - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 23776ff292966a85d811126933830bed48211826 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Tue Dec 11 10:53:12 2007 +0100 - - ARM: support board-specific ethernet PHY init - - Add until the new phylib will be arrived - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 7b74ebe723e576baedf5a8b6240589b19b845a1b -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Dec 8 16:34:08 2007 +0100 - - IXP: Add full baud-rate support for ixp42x, ixp45x and ixp46x - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit a2df4da31b1a1e41e3e9e1358cfc52b806046ce1 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Dec 9 11:01:10 2007 +0100 - - Add missing file in gitignore and comments - - based on Linux source tree's .gitignore files - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 435dc8fcdb3bc61d3d490773a8f369f98a20c868 -Author: Wolfgang Denk -Date: Wed Jan 9 11:36:21 2008 +0100 - - Coding Style cleanup, update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit b2e2142c500c48a57f18f9dd30e66c13caea0971 -Author: Stefan Roese -Date: Wed Jan 9 10:38:58 2008 +0100 - - POST: Execute SPR test after relocation - - On LWMON5 we now use d-cache as init-ram and stack. The SPR POST test uses - self modifying code and this doesn't work with stack in d-cache, since - I can't move the code from d-cache to i-cache. We move the SPR test to - be executed a little later, after relocation. Then stack is located in - SDRAM and this self-modifying code is no problem anymore. - - Signed-off-by: Stefan Roese - -commit 8f24e0637ae113500d8bd60d80d57afcc0aa8bde -Author: Stefan Roese -Date: Wed Jan 9 10:28:20 2008 +0100 - - ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymore - - This patch configures the LWMON5 port to use d-cache as init-ram and - the unused GPT0_COMP6 as POST WORD storage. - - Signed-off-by: Stefan Roese - -commit 1754f50b710194f886b6f2831803d8960171a14d -Author: Stefan Roese -Date: Wed Jan 9 10:25:46 2008 +0100 - - ppc4xx: Add CFG_POST_ALT_WORD_ADDR to support non OCM POST WORD storage - - The privious 4xx POST implementation only supported storing the POST - WORD in OCM. Since we need to reserve the OCM on LWMON5 for the logbuffer - we need to store the POST WORD in some other non volatile location. - This patch adds CFG_POST_ALT_WORD_ADDR to specify an address for such - a location. - - Signed-off-by: Stefan Roese - -commit e02c521d94b45d7b05aa522e4ccde6b74bf5fe57 -Author: Stefan Roese -Date: Wed Jan 9 10:23:16 2008 +0100 - - ppc4xx: Add 44x cache locking to better support init-ram in d-cache - - This patch adds support for locking the init-ram/stack in d-cache, - so that other regions may use d-cache as well - - Note, that this current implementation locks exactly 4k of d-cache, - so please make sure that you don't define a bigger init-ram area. Take - a look at the lwmon5 440EPx implementation as a reference. - - Signed-off-by: Stefan Roese - -commit 0ddb89601a8d29e808db450366752ffdc6267c53 -Author: Wolfgang Denk -Date: Wed Jan 9 10:16:33 2008 +0100 - - Fix memset bug in ext2fs_read_file() - - ext2fs_read_file() had the function arguments swapped. - - Pointed out by Mike Montour, 19 Dec 2007 22:34:25 -0800 - - Signed-off-by: Wolfgang Denk - -commit 32d6f1bc09175f3b77469771e839bc7255a9f22e -Author: Markus Klotzbücher -Date: Tue Jan 5 08:17:15 1988 +0100 - - Fix problems with usb storage devices on MPC5200 /TQM5200 - - The MPC5200 OHCI controller operates in big endian, so - CFG_OHCI_BE_CONTROLLER must be defined for it to work properly. - - Signed-off-by: Markus Klotzbuecher - -commit 46f6e5019048b103d7693d5310de0f1cfbaf4c19 -Author: Wolfgang Denk -Date: Tue Jan 8 22:58:27 2008 +0100 - - Fix compile problem with new env code. - - Signed-off-by: Wolfgang Denk - -commit 64b3727b9779d86127cd576e392a987de5ebb9fd -Author: Markus Klotzbücher -Date: Tue Nov 27 10:23:20 2007 +0100 - - tools: fix fw_printenv tool to compile again - - This patch updates the fw_printenv/fw_setenv userspace tool to include - the correct MTD header in order to compile against current kernel - headers. Backward compatibility is preserved by introducing an option - MTD_VERSION which can be set to "old" for compilation using the old MTD - headers. Along with this a number of warnings are fixed. - - Signed-off-by: Markus Klotzbuecher - -commit 1f84021a85abeb837d2ce0dc84297b4f1d45d516 -Author: Matthias Fuchs -Date: Tue Jan 8 15:40:09 2008 +0100 - - ppc4xx: assign PCI interrupts on seuqoia boards - - Some operating systems rely on assigned PCI interrupts. - - Signed-off-by: Matthias Fuchs - -commit 6e9233d30afe57cb6e148fbfa4895e7810196fac -Author: Matthias Fuchs -Date: Tue Jan 8 15:50:49 2008 +0100 - - ppc4xx: Move cpu/ppc4xx/vecnum.h into include path - - This patch allows the use of 4xx interrupt vector number defines - in board specific code outside cpu/ppc4xx. - - Signed-off-by: Matthias Fuchs - -commit 580d1d3186a2bc6dbdb626941b716dae1788e51e -Author: Matthias Fuchs -Date: Tue Jan 8 15:39:01 2008 +0100 - - ppc4xx: Fix UIC2 vector number base - - Signed-off-by: Matthias Fuchs - -commit ff5fb8a6ccba56e3482d0e297d8cfb7faa040811 -Author: Matthias Fuchs -Date: Tue Jan 8 12:49:58 2008 +0100 - - ppc4xx: Update PLB/PCI divider for PMC440 board - - This patch updates the PLB/PCI divider when running at - 400MHz CPU frequency from 4 to 3 which results in 44MHz PCI sync clock. - - Signed-off-by: Matthias Fuchs - -commit 7d5d75633174867316a0c0f2fca5ceb2cf312cde -Author: Matthias Fuchs -Date: Tue Jan 8 11:13:09 2008 +0100 - - ppc4xx: Disable error message when no NAND chip is installed on PMC440 - - Add CFG_NAND_QUIET_TEST option to disable error message when - no NAND chip is installed on PMC440 boards. - - Disable a couple of config defines that are only used for NAND_U_BOOT. - - Signed-off-by: Matthias Fuchs - -commit c83d7ca4dadd44ae430235077f63b64a11f36f6e -Author: Wolfgang Denk -Date: Tue Jan 8 22:58:27 2008 +0100 - - Fix compile problem with new env code. - - Signed-off-by: Wolfgang Denk - -commit 6de66b35426312a21174a9bf0576a094e2904bea -Author: Markus Klotzbücher -Date: Tue Nov 27 10:23:20 2007 +0100 - - tools: fix fw_printenv tool to compile again - - This patch updates the fw_printenv/fw_setenv userspace tool to include - the correct MTD header in order to compile against current kernel - headers. Backward compatibility is preserved by introducing an option - MTD_VERSION which can be set to "old" for compilation using the old MTD - headers. Along with this a number of warnings are fixed. - - Signed-off-by: Markus Klotzbuecher - -commit ad3006fe7e84667021753b74247b0bafd97ba35f -Author: Gerald Van Baren -Date: Mon Jan 7 23:47:32 2008 -0500 - - LIBFDT: use memmove() instead of memcpy() - - This is partial patch from the DTC/libfdt - commit 67b6b33b9b413a450a72135b5dc59c0a1e33e647 - Author: David Gibson - Date: Wed Nov 21 11:56:14 2007 +1100 - - The patch also fixes one genuine bug caught by valgrind - - _packblocks() in fdt_rw.c was using memcpy() where it should have been - using memmove(). - - Signed-off-by: Gerald Van Baren - -commit aec7135bc300e3340d18f203347ee00c5b5f68c0 -Author: David Gibson -Date: Mon Dec 17 14:42:07 2007 +1100 - - libfdt: Add more documentation (patch the seventh) - - This patch adds more documenting comments to libfdt.h. Specifically, - these document the read/write functions (not including fdt_open_into() - and fdt_pack(), for now). - - Signed-off-by: David Gibson - -commit 9d4450b5adc36623e9c1de1f92539db77ad0c57e -Author: David Gibson -Date: Mon Dec 17 14:41:52 2007 +1100 - - libfdt: Add more documentation (patch the sixth) - - This patch adds some more documenting comments to libfdt.h. - Specifically this documents all the write-in-place functions. - - Signed-off-by: David Gibson - -commit b60af3d4c1680487ee37e11aa1b3db6dec04d8f0 -Author: Gerald Van Baren -Date: Sat Dec 29 22:45:27 2007 -0500 - - Fine grained per property /chosen updating. - - Implement a suggestion by Scott Wood to make the /chosen handling fine - grained. Don't overwrite pre-existing properties on a per-property basis, - so if /chosen exists but a necessary /chosen/property doesn't, it gets - created. If a /chosen property exists, it is NOT overwritten unless the - "force" flag is true. - - Signed-off-by: Gerald Van Baren - -commit 238cb7a423c6eaa36496efb788cfb9798cea7f95 -Author: Gerald Van Baren -Date: Sat Jan 5 15:33:29 2008 -0500 - - Improve the FDT help message. - - Add a note that "fdt copy" makes the new address active. - Remove most of the extra hints at the end of the fdt help. - - Signed-off-by: Gerald Van Baren - -commit ea6d8be153ceaf16958f8009cea6d75f3ff58d92 -Author: Gerald Van Baren -Date: Sat Jan 5 14:52:04 2008 -0500 - - Support setting FDT properties with optional values. - - Fix a bug found and documented by Bartlomiej Sieka where the optional - value on "fdt set []" wasn't optional. - - => fdt mknode / testnode - => fdt print /testnode - testnode { - }; - => fdt set /testnode testprop - => fdt print /testnode - testnode { - testprop; - }; - - Signed-off-by: Gerald Van Baren - -commit 22fb2246df91bfc840d87f0c5910818bad55577a -Author: Matthias Fuchs -Date: Fri Dec 28 11:56:30 2007 +0100 - - Add fdt_find_and_setprop() to fdt_support.h - - fdt_find_and_setprop() is used by several 4xx boards and it's - missing in the appropriate header. This patch eliminates a - warning when building U-Boot for such boards. - - Signed-off-by: Matthias Fuchs - Acked-by: Stefan Roese - -commit 802b769bac17b0560d3535a42c502469ee190cd1 -Author: Stefan Roese -Date: Tue Jan 8 18:39:30 2008 +0100 - - ppc4xx: Return 0 on success in 4xx ethernet driver - - Signed-off-by: Stefan Roese - -commit 6775c68683a53c7abc778774641aac6f833a2cbf -Author: Kim Phillips -Date: Tue Jan 8 09:59:49 2008 -0600 - - mpc83xx: fix missed pci_hose -> hose conversion for new libfdt code - - Signed-off-by: Kim Phillips - -commit 94fab25f5f1a7d1c0cc63c17e813ea8943fe49c7 -Author: Kim Phillips -Date: Thu Dec 20 16:28:34 2007 -0600 - - mpc83xx: rm remaining FLAT_TREE code - - ..in board pci.c files - - Signed-off-by: Kim Phillips - -commit b3458d2cd55d01732e30a76d898afd99e871cd67 -Author: Kim Phillips -Date: Thu Dec 20 15:57:28 2007 -0600 - - mpc83xx: remove FLAT_TREE code - - need to rm it from pci code, too! - - Signed-off-by: Kim Phillips - -commit 5b8bc606c61456566af6912f818a153b6b06f242 -Author: Kim Phillips -Date: Thu Dec 20 14:09:22 2007 -0600 - - mpc83xx: convert to using do_fixup_*() - - convert to using simpler mpc85xx style fdt update code; streamline by - eliminating macros OF_SOC, OF_CPU, etc. which allows us to rm - the old school FLAT_TREE code from 83xx (since the sbc8349 was just - converted over to using libfdt). - - Signed-off-by: Kim Phillips - -commit e496865ecc31a2fe2f9abfe798334bb02aaf05ab -Author: Paul Gortmaker -Date: Thu Dec 20 12:58:51 2007 -0500 - - sbc8349: enable libfdt by default on WRS SBC8349 board. - - Make libfdt the default for the WRS SBC8349 board. - Parallel of commit 35cc4e4823668e8745854899cfaedd4489beb0ef - done for the other 83xx based boards. Also fix a typo in CONFIG_PCI. - - Signed-off-by: Paul Gortmaker - -commit 2408b3f20bcbdd9c6c397cd03ab0d71d54680a40 -Author: Paul Gortmaker -Date: Thu Dec 20 12:58:16 2007 -0500 - - sbc8349: migrate board to libfdt - - This adds libfdt support code for the Wind River sbc8349 board. - - Parallel of commit 3fde9e8b22cfbd7af489214758f9839a206576cb for - the other Freescale 83xx boards. - - Signed-off-by: Paul Gortmaker - -commit 27a256a90cc86392ac9bf0039a3afe638ec2c18d -Author: Paul Gortmaker -Date: Thu Dec 20 12:56:19 2007 -0500 - - sbc8349: Remove board specific ECC code - - ECC code is now shared for all 83xx boards, so remove board specific one. - See commit daab8c67d2defef73dc26ab07f0c3afd1b05d019 for reference. - - Signed-off-by: Paul Gortmaker - -commit a1e1ac849249310e5e2e5c7148e9fb353a8317a7 -Author: Kim Phillips -Date: Thu Dec 20 01:30:48 2007 -0600 - - mpc83xx: Remove CONFIG options related to OF that we dont use (on 837x) - - continuation of commit 37395fa2b0d9d617f28d44ca11592260ef16105a to 837x - - Signed-off-by: Kim Phillips - -commit ccf21c311e68d48399eff1e72936052885f6e3f7 -Author: Joakim Tjernlund -Date: Thu Dec 6 16:43:40 2007 +0100 - - Add support CONFIG_UEC_ETH3 in MPC83xx - - Signed-off-by: Joakim Tjernlund - -commit e6af9932d31171e35db880e7b2f29f903b1b7660 -Author: Kumar Gala -Date: Mon Nov 26 11:00:54 2007 -0600 - - Remove CONFIG options related to OF that we dont use - - The MPC8360E MDS config defined: - CONFIG_OF_HAS_BD_T - CONFIG_OF_HAS_UBOOT_ENV - - Which we don't use or ever needed. This seems like copy-paste feature creep. - - Signed-off-by: Kumar Gala - -commit f602082b4b7ed4ee16432067cc67a0a24fedc715 -Author: Kim Phillips -Date: Mon Dec 10 14:16:22 2007 -0600 - - mpc83xx: supress compiler warning - - mpc8360emds.c: In function ‘ft_board_setup’: - mpc8360emds.c:335: warning: assignment discards qualifiers from pointer target type - mpc8360emds.c:345: warning: assignment discards qualifiers from pointer target type - - Signed-off-by: Kim Phillips - -commit c16e44fa835fb9eec982d919863a04e2f78e5ce7 -Author: Kim Phillips -Date: Tue Nov 27 14:17:29 2007 -0600 - - mpc83xx: fix remaining fdt_find_node_by_path references - - rename to fdt_path_offset - - Signed-off-by: Kim Phillips - -commit 921d4b19ad1be704df58725485d9292dc0414adf -Author: Kim Phillips -Date: Mon Nov 19 12:30:09 2007 -0600 - - mpc83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE definitions for 837x - - Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for 837x. - This change guarantees that the environment will be located on the - first flash sector after the U-Boot image. - - Signed-off-by: Kim Phillips - -commit 24f868433b50ecbaa88e118aadc7bd254013c6ae -Author: Kim Phillips -Date: Fri Nov 9 14:28:08 2007 -0600 - - mpc83xx: mpc8360 rev.2.1 erratum 2: replace rgmii-id with rgmii-rxid - - u-boot itself uses GMII mode on the 8360. Fix up UCC phy-connection-type - properties in the device tree so the PHY gets configured for internal delay on - RX only by the OS, as prescribed by mpc8360 rev. 2.1 pb mds erratum #2. - - Signed-off-by: Kim Phillips - -commit 22b448dbfbe2a98f01ff4adc3c3979f8c541ad7b -Author: Dave Liu -Date: Tue Sep 18 12:41:15 2007 +0800 - - mpc83xx: update the CREDITS and MAINTAINERS - - update the CREDITS and MAINTAINERS. - - Signed-off-by: Dave Liu - -commit b21add4b42af7b767448251b599b91066a160e0d -Author: Dave Liu -Date: Tue Sep 18 12:40:21 2007 +0800 - - mpc83xx: add MAINTAINER and MAKEALL entries for the mpc837xemds - - Add the MAINTAINER and MAKEALL entries for mpc837xemds - - Signed-off-by: Dave Liu - -commit f8900ce9094c462355eb792eea264ff16ac8fd16 -Author: Dave Liu -Date: Tue Sep 18 12:38:53 2007 +0800 - - mpc83xx: Add the MPC837xEMDS board readme - - Add the README.mpc837xemds to /doc - - Signed-off-by: Dave Liu - -commit 19580e660cc8da49f16536a8bd78c047c7bc12e5 -Author: Dave Liu -Date: Tue Sep 18 12:37:57 2007 +0800 - - mpc83xx: Add the support of MPC837xEMDS board - - The MPC837xEMDS board support: - * DDR2 400MHz hardcoded and SPD init - * Local bus NOR Flash - * I2C, UART, MII and RTC - * eTSEC RGMII - * PCI host - - Signed-off-by: Dave Liu - -commit 555da61702771fe0f76f3de23b4e7590f3704161 -Author: Dave Liu -Date: Tue Sep 18 12:36:58 2007 +0800 - - mpc83xx: Add the support of MPC8315E SoC - - The MPC8315E SoC including e300c3 core and new IP blocks, - such as TDM, PCI Express and SATA controller. - - Signed-off-by: Dave Liu - -commit 03051c3d35c9981ceaa059005660e699f3eacf1c -Author: Dave Liu -Date: Tue Sep 18 12:36:11 2007 +0800 - - mpc83xx: Add the support of MPC837x SoC - - The MPC837x SoC including e300c4 core and new IP blocks, - such as SDHC, PCI Express and SATA controller. - - Signed-off-by: Dave Liu - -commit 651d96f7e4c84adcdb98ef07ec878c20326e3359 -Author: Anton Vorontsov -Date: Wed Nov 14 18:54:53 2007 +0300 - - MPC8360E-MDS: configure and enable second UART - - Despite user manual, BCSR9.7 is negated (high) on HRST, so - UART2 is disabled. Fix that and configure QE pins properly. - - Signed-off-by: Anton Vorontsov - -commit b2893e1fcb28fad8c8b317104df8cee0142c7631 -Author: Timur Tabi -Date: Mon Nov 5 09:34:06 2007 -0600 - - 83xx: fix CFG_ENV_ADDR and CFG_ENV_SECT_SIZE definitions - - Fix the definitions of CFG_ENV_ADDR and CFG_ENV_SECT_SIZE for all of the - currently-defined 83xx boards. This change guarantees that the environment - will be located on the first flash sector after the U-Boot image. - - Signed-off-by: Timur Tabi - Signed-off-by: Kim Phillips - -commit e05329516a13616b53240cd85b739217c2bf87f1 -Author: Larry Johnson -Date: Fri Jan 4 13:27:02 2008 -0500 - - ppc4xx: Remove weak binding from common Denali data-eye search code - - Now that there are no board-specific versions of - "denali_core_search_data_eye()", the weak binding on the common version - can be removed. - - Signed-off-by: Larry Johnson - -commit 5ba576c01602fd328800a427964c36a0a05c5dce -Author: Stefan Roese -Date: Sat Jan 5 09:13:46 2008 +0100 - - ppc4xx: Remove unused CONFIG_ECC_ERROR_RESET from 44x_spd_ddr2.c - - Signed-off-by: Stefan Roese - -commit 845c6c95dbfe6c915ce68a0a115852fa17932fb4 -Author: Stefan Roese -Date: Sat Jan 5 09:12:41 2008 +0100 - - ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup - - On Katmai the complete auto-calibration somehow doesn't seem to - produce the best results, meaning optimal values for RQFD/RFFD. - This was discovered by GDA using a high bandwidth scope, - analyzing the DDR2 signals. GDA provided a fixed value for RQFD, - so now on Katmai "only" RFFD is auto-calibrated. - - This patch also adds RDCC calibration as mentioned on page 7 of - the AMCC PowerPC440SP/SPe DDR2 application note: - "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" - - Signed-off-by: Stefan Roese - -commit 49db47b8ae6afff2b898be312948ff501357dc80 -Author: Matthias Fuchs -Date: Wed Jan 2 16:48:42 2008 +0100 - - ppc4xx: Remove sdram.h from PMC440 board - - Signed-off-by: Matthias Fuchs - -commit 34065a2ce0d8972f2ec6652076014ab243d2ce8a -Author: Matthias Fuchs -Date: Wed Jan 2 16:48:34 2008 +0100 - - ppc4xx: use common denali core defines and data eye search code for PMC440 - - Signed-off-by: Matthias Fuchs - -commit 9ac6b6f3d3f1b072d89268b2efe47e95e6659489 -Author: Matthias Fuchs -Date: Wed Jan 2 12:05:14 2008 +0100 - - ppc4xx: More cleanup for esd's LCD code - - Signed-off-by: Matthias Fuchs - -commit fe9c26b330a21ce73e52b5bd347d725cb81e3cfb -Author: Stefan Roese -Date: Fri Jan 4 12:00:01 2008 +0100 - - ppc4xx: Fix Sequoia NAND booting target - - The Sequoia NAND booting target now uses the recently extracted - cpu/ppc4xx/denali_data_eye.c file too. - - Signed-off-by: Stefan Roese - -commit 0ddd969aec532bd7eae30fc09590488a3aaa629a -Author: Lawrence R. Johnson -Date: Thu Jan 3 15:02:02 2008 -0500 - - ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Korat board - - Signed-off-by: Larry Johnson - -commit b05e8bf58be9d8956fdfde3d8c8e87c140414663 -Author: Lawrence R. Johnson -Date: Fri Jan 4 02:11:56 2008 -0500 - - ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia board - - Note: this patch changes the configuration of some GPIO registers: - - Register Old Value New Value - --------------- ---------- ---------- - DCR GPIO0_TCR 0x0000000F 0x0000F0CF - DCR GPIO0_TSRH 0x55005000 0x00000000 - DCR GPIO1_TCR 0xC2000000 0xE2000000 - DCR GPIO1_TSRL 0x0C000000 0x00200000 - DCR GPIO1_ISR2L 0x00050000 0x00110000 - - Signed-off-by: Larry Johnson - -commit 5ab884b254ca2e707ab50545cd705f30108cf491 -Author: Lawrence R. Johnson -Date: Thu Jan 3 18:54:00 2008 -0500 - - ppc4xx: Add functionality to GPIO support - - This patch makes two additions to GPIO support: - - First, it adds function gpio_read_in_bit() to read the a bit from the - GPIO Input Register (GPIOx_IR) in the same way that function - gpio_read_out_bit() reads a bit from the GPIO Output Register - (GPIOx_OR). - - Second, it modifies function gpio_set_chip_configuration() to provide - an additional option for configuring the GPIO from the - "CFG_4xx_GPIO_TABLE". - - According to the 440EPx User's Manual, when an alternate output is used, - the three-state control is configured in one of two ways, depending on - the particular output. The first option is to select the corresponding - alternate three-state control in the GPIOx_TRSH/L registers. The second - option is to select the GPIO Three-State Control Register (GPIOx_TCR) in - the GPIOx_TRSH/L registers, and set the corresponding bit in the - GPIOx_TCR register to enable the output. For example, the Manual - specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use - the alternate three-state control (first option), and specifies - configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output - enabled in the GPIOx_TCR register (second option). - - Currently, gpio_set_chip_configuration() configures all alternate signal - outputs to use the first option. This patch allow the second option to - be selected by setting the "out_val" element in the table entry to - "GPIO_OUT_1". The first option is used when the "out_val" element is - set to "GPIO_OUT_0". Because "out_val" is not currently used when an - alternate signal is selected, and because all current GPIO tables set - "out_val" to "GPIO_OUT_0" for all alternate signals, this patch should - not change any existing configurations. - - Signed-off-by: Larry Johnson - -commit 196404cdc1de495d6182e84731c200fc5748df15 -Author: Larry Johnson -Date: Sun Dec 30 01:01:54 2007 -0500 - - PPC4xx: Remove sdram.h from board/lwmon5 - - These definitions are now in "include/ppc440.h". - - Signed-off-by: Larry Johnson - -commit ef16fccf96e55eab93fe25d03ebe2e9b56e5332b -Author: Larry Johnson -Date: Sun Dec 30 01:01:32 2007 -0500 - - PPC4xx: Use common code for LWMON5 board SDRAM support - - This patch also modifies the functionality of the code so that the data-eye - search is now done with with the cache disabled. - - Signed-off-by: Larry Johnson - -commit 62cc3951ab72135d9c101f1845b794e63a0fa189 -Author: Larry Johnson -Date: Sun Dec 30 01:01:14 2007 -0500 - - PPC4xx: Remove sdram.h from board/amcc/sequoia - - These definitions are now in "include/ppc440.h". - - Signed-off-by: Larry Johnson - -commit ce3902e1765bbfb07cf5bbe98be9a68e3009996a -Author: Larry Johnson -Date: Sun Dec 30 01:00:50 2007 -0500 - - PPC4xx: Use common code for Sequoia board SDRAM support - - Signed-off-by: Larry Johnson - -commit 8b0c5c127690335758100c25eaec2b84db97c101 -Author: Matthias Fuchs -Date: Thu Dec 27 16:58:41 2007 +0100 - - net: Add CONFIG_NET_DO_NOT_TRY_ANOTHER option - - When CONFIG_NET_DO_NOT_TRY_ANOTHER is defined U-Boot's - networking stack does not automatically switch to - another interface. This patch does not touch the default - behavior. - - Signed-off-by: Matthias Fuchs - Signed-off-by: Ben Warren - -commit 505be87a65e4f87ad7d8da1d57ea4dcd487d7e32 -Author: Upakul Barkakaty -Date: Thu Nov 29 12:16:13 2007 +0530 - - NET: Proper return code handling in eth_init() function in file eth.c - - This patch modifies the return code handling in the eth_init() - function, to be compatible with the handling of the return codes in - the other network stack files. It now returns a 0 on Success and -1 on - error. - - Signed-off-by: Upakul Barkakaty - Signed-off-by: Ben Warren - -commit 5ca2d0953e4579a80810966cca2077e20d912c97 -Author: Shinya Kuribayashi -Date: Mon Nov 19 20:27:04 2007 +0900 - - net/eth.c: Fix env_enetaddr signed overflow - - Assigning the output of simple_strtoul(CB:A9:87:65:43:21) to `char', we are - warned as below: - - U-Boot 1.2.0 (Aug 30 2007 - 08:27:37) - - DRAM: 256 MB - Flash: 32 MB - In: serial - Out: serial - Err: serial - Net: NEC-Candy - Warning: NEC-Candy MAC addresses don't match: - Address in SROM is 00:00:4C:80:92:A2 - Address in environment is FFFFFFCB:FFFFFFA9:FFFFFF87:65:43:21 - - This patch changes env_enetaddr type from `char' to `unsigned char'. - - Cc: Masaki Ishikawa - Signed-off-by: Shinya Kuribayashi - Signed-off-by: Ben Warren - -commit f85b60710571b37293d2233933b76e2aa3db5635 -Author: Rafal Jaworowski -Date: Thu Dec 27 18:19:02 2007 +0100 - - Introduce new eth_receive routine - - The purpose of this routine is receiving a single network frame, outside of - U-Boot's NetLoop(). Exporting it to standalone programs that run on top of - U-Boot will let them utilise networking facilities. For sending a raw frame - the already existing eth_send() can be used. - - The direct consumer of this routine is the newly introduced API layer for - external applications (enabled with CONFIG_API). - - Signed-off-by: Rafal Jaworowski - Signed-off-by: Piotr Kruszynski - Signed-off-by: Ben Warren - -commit 5c740711f0ea5b51414b341b71597c4a0751be74 -Author: Jon Loeliger -Date: Thu Jan 3 10:41:04 2008 -0600 - - 8610: Move include of config.h earlier. - - Include config.h earlier in the set of #includes - so as to avoid a incidental and duplicate definition - of CFG_CACHELINE_SIZE. - - Signed-off-by: Jon Loeliger - -commit 61d3421bdea090bd0399b14c3e10a3bebcc8d5ff -Author: Jon Loeliger -Date: Tue Dec 4 10:53:34 2007 -0600 - - Don't slam #undef DEBUG in the 8641HPCN config file. - - Doing so prevents it from being individually set - and useful in other files. - - Signed-off-by: Jon Loeliger - -commit ea9f7395ec362584e5e4f266bd0b0c4422cf6a4c -Author: Jon Loeliger -Date: Wed Nov 28 14:47:18 2007 -0600 - - Convert MPC8641HPCN to use libfdt. - - Assumes the presence of the aliases node in the DTS to - locate the ethernet, pci and serial nodes for fixups. - - Use consistent fdtaddr and fdtfile in environment variables. - - Signed-off-by: Jon Loeliger - -commit ce37422d0002e10490e268392e0c4e3028e52cec -Author: Stefan Roese -Date: Wed Jan 2 14:06:26 2008 +0100 - - cfi_flash: Fix bug in flash_isset() to use correct 32bit function - - This bug was detected on the LWMON5 target which has 2 Intel 16bit wide - flash chips connected to a 32bit wide port. - - Signed-off-by: Stefan Roese - -commit 1182e9f8e3b92fc372d64943293de53daa2e26cf -Author: Wolfgang Denk -Date: Wed Jan 2 15:58:44 2008 +0100 - - Fix compile problem introduced by "cleanup" commit 3dfd708c - - Signed-off-by: Wolfgang Denk - -commit 1aaab9bfae0b3b2ee2b418c22c651280ee7b65c7 -Author: Wolfgang Denk -Date: Wed Jan 2 15:54:45 2008 +0100 - - Make scripts and Makefiles POSIX compliant - - The bash builtin versions of the "test" (resp. "[") command allow - using "==" for string comparisons, but POSIX compatible implemen- - tations (like /usr/bin/test) insist on using "=" only. On such systems - you will see: - - $ /usr/bin/test a == a && echo OK - /usr/bin/test: ==: binary operator expected - - This patch fixes Makefiles and scripts to use POSIX style. - - Signed-off-by: Wolfgang Denk - -commit 47cc23cbe9a669c510183f4f049bf703ef445f3b -Author: Stefan Roese -Date: Wed Jan 2 14:05:37 2008 +0100 - - cfi_flash: Fix bug in flash_isset() to use correct 32bit function - - This bug was detected on the LWMON5 target which has 2 Intel 16bit wide - flash chips connected to a 32bit wide port. - - Signed-off-by: Stefan Roese - -commit 3dfd708cc1b2a966ad454ca9ed125dd17dbadbcc -Author: Wolfgang Denk -Date: Wed Jan 2 12:38:43 2008 +0100 - - Minor coding style cleanup. - - Signed-off-by: Wolfgang Denk - -commit e174ac34adf5d5653df12bc3cf19c52063a71269 -Author: Stefan Roese -Date: Fri Dec 28 17:29:56 2007 +0100 - - ppc4xx: Coding style cleanup - - Signed-off-by: Stefan Roese - -commit 8ba132cab18ae438b6dd5b0214c28a8fc0d976e5 -Author: Matthias Fuchs -Date: Fri Dec 28 17:07:24 2007 +0100 - - ppc4xx: Complete PMC440 board support - - This patch brings the PMC440 board configuration file. - Finally it enables the PMC440 board support. - - Signed-off-by: Matthias Fuchs - -commit 407843a582560fc5231299561ab3c2b6b6cd3397 -Author: Matthias Fuchs -Date: Fri Dec 28 17:07:18 2007 +0100 - - ppc4xx: Add FPGA support and BSP commands for PMC440 boards - - This patch adds some BSP commands and FPGA booting support - for esd's PMC440 boards. - - Signed-off-by: Matthias Fuchs - -commit 72c5d52aedcce35e4b4fa5895605554825b6a76f -Author: Matthias Fuchs -Date: Fri Dec 28 17:07:14 2007 +0100 - - ppc4xx: Add initial esd PMC440 board files - - This patch adds the first files for the new esd PMC440 boards. - The next two patches will complete the PMC440 board support. - - Signed-off-by: Matthias Fuchs - -commit f6e0f1f61896ce7729ba1bcea2ffbd138d3947f5 -Author: Matthias Fuchs -Date: Fri Dec 28 17:10:36 2007 +0100 - - ppc4xx: Add EEPROM write protection for PLU405 boards + misc. updates - - - add EEPROM write protection for esd PLU405 boards. - - initialize NAND GPIOs - - use correct io accessors - - cleanup - - Signed-off-by: Matthias Fuchs - -commit 77660c4b59055d621d2a8595bd4c18bb277268fc -Author: Matthias Fuchs -Date: Fri Dec 28 17:10:44 2007 +0100 - - ppc4xx: use correct io accessors for esd's LCD code - - This patch fixes esd's LCD dectection code to work correctly with - newer gcc versions. - - Signed-off-by: Matthias Fuchs - -commit b56bd0fcfc1c73db722e3462c8a9bf607ba7775e -Author: Matthias Fuchs -Date: Fri Dec 28 17:10:42 2007 +0100 - - ppc4xx: Maintenance patch for VOH405 boards - - - add EEPROM write protection - - initialize NAND GPIOs - - use correct io accessors - - slow down I2C clock to 100kHz - - enable ext. I2C bus - - cleanup - - Signed-off-by: Matthias Fuchs - -commit c05569066dbcba3fdf36d4d1943df265dc316a86 -Author: Stefan Roese -Date: Fri Dec 28 16:08:08 2007 +0100 - - ppc4xx: Enable 405EP PCI arbiter per default on all boards - - In an attmemt to clean up the 4xx start.S file, I removed the enabling - of the internal 405EP PCI arbiter. This is needed for multiple other - 405EP platforms, like most of the esd 405EP. Now the internal PCI - arbiter is enabled again per default as it has been before. - - Signed-off-by: Stefan Roese - Acked-by: Matthias Fuchs - -commit bec9264616fb78273a1d93e87ff4b0b67c7bec1b -Author: Stefan Roese -Date: Fri Dec 28 15:53:46 2007 +0100 - - ppc4xx: Fix bug in cpu_init.c (405EP instead of 450EP) - - Signed-off-by: Stefan Roese - Acked-by: Matthias Fuchs - -commit fb83a65c60ab5ca12358b75f1257e5eee6cdbf79 -Author: Stefan Roese -Date: Fri Dec 28 06:06:04 2007 +0100 - - ppc4xx: Fix compilation problem of kilauea/haleakala nand booting target - - Use correct link to nand_ecc now located in drivers/mtd/nand/ for the - platforms mentioned above. - - Signed-off-by: Stefan Roese - -commit b568fd25574181a3b12ae3d66b2913903442cb83 -Author: Matthias Fuchs -Date: Thu Dec 27 17:03:46 2007 +0100 - - Remove CPCI440 board - - This board never left prototyping state and it - became a millstone round my neck. So remove it. - - Signed-off-by: Matthias Fuchs - -commit c591dffe0cbacd896ccbad06011fe6d6afa080da -Author: Larry Johnson -Date: Thu Dec 27 11:28:51 2007 -0500 - - Add support for Korat PPC440EPx board - - These patches add support for the PPC440EPx-based "Korat" board to - U-Boot. They are based primarily on support for the Sequoia board. - - Signed-off-by: Larry Johnson - -commit 87dc096829e6a6363f4fdd73653b0093a85adbe0 -Author: Larry Johnson -Date: Sat Dec 22 15:16:25 2007 -0500 - - Add configuration file for Korat board - - This patch supplies the configuration file for the Korat PPC440EPx- - processor board. - - Signed-off-by: Larry Johnson - -commit 8eb52d5d982b764b39c88d9d1064d56c5397bfa5 -Author: Larry Johnson -Date: Sat Dec 22 15:16:11 2007 -0500 - - Add denali_data_eye.o and denali_spd_ddr2.o to PPC4xx Makefile - - Signed-off-by: Larry Johnson - -commit aba19604d848b2838cfb9ebe818909e6a216058e -Author: Larry Johnson -Date: Thu Dec 27 10:54:48 2007 -0500 - - Add 440EPx DDR2 SPD DIMM support - - This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM - controller. It should also work on the 440GRx. It is based on the DDR2 - SPD code for the 440EP/440EPx, but makes no provision for DDR1 support. - - This code has been tested on prototype Korat boards with three Kingston - DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC - (two ranks). The Korat board has a single DIMM socket, but support has - been provided (though not tested) for boards with two DIMM sockets. - - Signed-off-by: Larry Johnson - -commit 8a24a6963002cb867d5a6b70e3560f0b1467f55f -Author: Larry Johnson -Date: Sat Dec 22 15:15:30 2007 -0500 - - Copy 440EPx/GRx SDRAM data-eye search to common directory - - This patch creates a non-board-specific file for performing the SDRAM - data-eye search. It also adds ECC error checking to the test of valid - data on readback when ECC is enabled. - - Signed-off-by: Larry Johnson - -commit c46f53333b22b1f9098676bea8884fc7db820cf3 -Author: Larry Johnson -Date: Sat Dec 22 15:15:13 2007 -0500 - - Add definitions for 440EPx/GRx SDRAM controller to ppc440.h - - This patch adds the Denali SDRAM controller definitions to "ppc440.h". - It also fixes two typos in the definitions, so the board-specific - "sdram.h" files containing these definitions are also fixed to avoid - compiler warnings. - - Signed-off-by: Larry Johnson - -commit c348578bf612d0c56d8d376d23cae16defbd86af -Author: Larry Johnson -Date: Thu Dec 27 10:50:55 2007 -0500 - - Add Ethernet 1000BASE-X support for PPC4xx - - This patch adds a new switch: "CONFIG_PHY_DYNAMIC_ANEG". When this symbol - is defined, the PHY will advertise it's capabilities for autonegotiation - based on the capabilities shown in the PHY's status registers, including - 1000BASE-X. When "CONFIG_PHY_DYNAMIC_ANEG" is not defined, the PHY will - advertise hard-coded capabilities, as before. - - Signed-off-by: Larry Johnson - -commit 9e2c347151db5ae8acf5f18b99493cd53e6637e3 -Author: Larry Johnson -Date: Thu Dec 27 09:52:17 2007 -0500 - - Add driver for National Semiconductor LM73 temperature sensor - - This driver is based on the driver for the LM75. - - Signed-off-by: Larry Johnson - -commit 12618278688ea9b3d76536960a5ad2e3790fac40 -Author: Larry Johnson -Date: Sat Dec 22 15:14:00 2007 -0500 - - Add driver for STMicroelectronics M41T60 RTC - - This driver is based on the driver for the M41T11. In the intended - application, the RTC will be powered by a large capacitor, rather than a - battery. The driver therefore checks to see whether the RTC has lost - power. The chip's OUT bit is normally reset from its power-up state. If - the OUT bit is read as set, or if the date and time are not valid, then the - RTC is assumed to have lost power, and its date and time are reset to - 1900-01-01 00:00:00. - - Support for adjusting the speed of the clock to improve accuracy is - provided through an environment variable. - - Signed-off-by: Larry Johnson - -commit d3471173e14b7544bb60339eda8d3d3906694b0a -Author: Larry Johnson -Date: Sat Dec 22 15:34:39 2007 -0500 - - Use out_be32() and friends to access memory-mapped registers in sequoia.c - - Signed-off-by: Larry Johnson - -commit c68f59fe3ec16769f82b5fca7421983c336d3aac -Author: Larry Johnson -Date: Sat Dec 22 15:34:20 2007 -0500 - - Use definitions from "asm-ppc/mmu.h" in init.S for Sequoia - - Signed-off-by: Larry Johnson - -commit 0d9cdeac1d3fa8d62ed7d883acc950c364f5bda8 -Author: Larry Johnson -Date: Sat Dec 22 15:23:50 2007 -0500 - - Cosmetic changes to ECC POST for AMCC Denali core - - Signed-off-by: Larry Johnson - -commit 2e583d6c81034f80a267b89fa55498ae063ccef1 -Author: Stefan Roese -Date: Wed Dec 26 20:20:19 2007 +0100 - - ppc4xx: Fix compilation problem in 405 cache POST test - - Signed-off-by: Stefan Roese - -commit 42d55ea0bde06e47d5a3b49b0d91002acd8e5708 -Author: Stefan Roese -Date: Sat Dec 22 12:20:09 2007 +0100 - - ppc4xx: Move virtual address of POST cache test to bigger address - - On Sequoia & LWMON5 the virtual address of the POST cache test is now - moved to a bigger address. This enables usage of more memory on those - boards. - - Signed-off-by: Stefan Roese - -commit d91722102cf63f77a0148ed3f3d54a26d87575e9 -Author: Stefan Roese -Date: Sat Dec 22 12:18:26 2007 +0100 - - ppc4xx: Fix problem in 44x cache POST routine - - As repoted by Larry Johnson, running "diag run cache" caused a crash - in U-Boot. This problem was introduced by a patch that removed the - TLB entry for the cache test after the test has completed. Since this - TLB was only setup once, a 2nd attempt to run this cache test - failed with a crash. Now this TLB entry is created every time the - routine is called. - - Signed-off-by: Stefan Roese - -commit b0265b576bb8fa9465f99e99c323768b562fadc2 -Author: Stefan Roese -Date: Fri Dec 21 07:51:29 2007 +0100 - - ppc4xx: Update Makalu fdt support - - Signed-off-by: Stefan Roese - -commit bf8324e4a50758daff8cddd04c6a2ff8ed775bea -Author: Stefan Roese -Date: Wed Dec 19 09:05:40 2007 +0100 - - ppc4xx: Add fdt support to AMCC Katmai eval board - - Signed-off-by: Stefan Roese - -commit 328a340392a5df9aaf00792be989df73e750859e -Author: Stefan Roese -Date: Tue Dec 18 08:44:51 2007 +0100 - - ppc4xx: fdt: Cleanup setup of cpu node setup - - Now the cpu node setup ("timebase-frequency" and "clock-frequency") is - without using the absolute path to the cpu node. This makes it possible - to use this U-Boot version with both versions of cpu-node naming - "cpu@0" and the former "PowerPC,440EPx@0". - - Signed-off-by: Stefan Roese - -commit 7812bc4a2e2436ebbc0ce5b4e99c1dfc2e77eb5b -Author: Stefan Roese -Date: Mon Dec 17 17:26:21 2007 +0100 - - ppc4xx: Fix lwmon5 compilation problem - - Now that the 440EPx ECC test is not board specific anymore - remove this Makefile. - - Signed-off-by: Stefan Roese - -commit 42ed33ffe135f618680f9d6e9712eb35a85bcb62 -Author: Anatolij Gustschin -Date: Wed Dec 5 17:43:20 2007 +0100 - - Fix ppc4xx clear_bss() code - - ppc4xx clear_bss() fails if BSS segment size is not - divisible by 4 without remainder. This patch provides - fix for this problem. - - Signed-off-by: Anatolij Gustschin - -commit 85dc2a7f82d11e17f0ca2a448118aed7f7a4b85d -Author: Niklaus Giger -Date: Fri Nov 30 18:35:11 2007 +0100 - - PPC4xx: Minimal changes to add vxWorks support - - Signed-off-by: Niklaus Giger - -commit 052440b022ca8981d39b6f8c10d1aa6326f47480 -Author: Markus Klotzbücher -Date: Fri Nov 23 13:09:18 2007 +0100 - - ppc4xx: Add CONFIG_BOOTP_SUBNETMASK to Sequoia board config - - When using dhcp/bootp the "netmask" environment variable is not - set because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is - desireable, so the following patch adds this this option to the board - config. - - Signed-off-by: Markus Klotzbuecher - Signed-off-by: Stefan Roese - -commit a724a9b40c7fbeb6ade193ca52321b441eaecb4e -Author: Larry Johnson -Date: Sat Oct 27 12:48:15 2007 -0400 - - Fix/enhance ECC POST for 440EPx/GRx - - This patch allows the ECC POST to be used for different boards with the - PPC440 Denali SDRAM controller. Modifications include skipping the test - if ECC is not enabled (as for non-ECC DIMMs) and adding synchronization - to prevent timing errors. - - Signed-off-by: Larry Johnson - -commit 454a6cf8d498f70d2b3e18f07837603eb24b12d4 -Author: Larry Johnson -Date: Sat Oct 27 12:48:05 2007 -0400 - - PPC4xx: Move/rename ECC POST for 440EPx/GRx - - Signed-off-by: Larry Johnson - -commit c29d2d3680046d430022c55e50fcb27f5866517e -Author: Matthias Fuchs -Date: Fri Dec 14 11:20:33 2007 +0100 - - ppc4xx: use correct io accessors for 4xx ethernet POST - - Signed-off-by: Matthias Fuchs - -commit ba79fde58a48c0a6ff8e2a96caba951594142203 -Author: Matthias Fuchs -Date: Fri Dec 14 11:19:56 2007 +0100 - - ppc4xx: fix flush + invalidate_dcache_range arguments - - flush + invalidate_dcache_range() expect the start and stop+1 address. - So the stop address is the first address behind (!) the range. - - Signed-off-by: Matthias Fuchs - -commit 871e6ce188a7c6bc7321bcf8372857035d20f1cd -Author: Stefan Roese -Date: Fri Dec 14 08:41:29 2007 +0100 - - ppc4xx: fdt: use fdt_fixup_ethernet() - - By using aliases in the dts file, the ethernet node fixup is - much easier with the recently added functions. - - Please note that the dts file needs the aliases for this to work. - - Signed-off-by: Stefan Roese - -commit 136288847e3b04f2ff357a067ad45e10afa0a24c -Author: Stefan Roese -Date: Thu Dec 13 14:52:53 2007 +0100 - - ppc4xx: Bring 4xx fdt support up-to-date - - This patch update the 4xx fdt support. It enabled fdt booting - on the AMCC Kilauea and Sequoia for now. More can follow later - quite easily. - - Signed-off-by: Stefan Roese - -commit 0dc80e2759fba859ccc4cdadc633577ca2971f3e -Author: Stefan Roese -Date: Thu Dec 27 07:50:54 2007 +0100 - - cfi_flash: Add missing check for erased dest to flash_write_cfibuffer() - - The check for an sufficiently erased destination was missing in the - buffered write function of the cfi flash driver (when - CFG_FLASH_USE_BUFFER_WRITE is defined). This patch adds this check to that - writing to such a region will fail with the currect error message. - - Signed-off-by: Stefan Roese - -commit 33ed73bc0e38d0f2b5c183d4629d8f207e5b9994 -Author: Martin Krause -Date: Mon Nov 12 10:56:17 2007 +0100 - - Some configuration updates for the TQM5200 based TB5200 board: - - - enable command line history - - increase malloc space (because of bigger flash sectors) - - Signed-off-by: Martin Krause - -commit e318d9e9021a0af7508171f84ed09d0e79f0284e -Author: Martin Krause -Date: Thu Sep 27 11:10:08 2007 +0200 - - TQM8xx: use the CFI flash driver on all TQM8xx boards - - Signed-off-by: Martin Krause - -commit 11d9eec479b470eab9242ab937fca70a876d9376 -Author: Martin Krause -Date: Wed Sep 26 17:55:56 2007 +0200 - - TQM885D: adjust for doubled flash sector size + some minor fixes - - Signed-off-by: Martin Krause - -commit 22d1a56cbfb0bff34f477b4db6a55d076d829b83 -Author: Jens Gehrlein -Date: Wed Sep 26 17:55:54 2007 +0200 - - TQM885D: Exchanged SDRAM timing by a more relaxed timing. - - CAS-Latency=2, Write Recovery Time tWR=2 - The max. supported bus frequency is 66 MHz. Therefore, changed - threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz. - - Signed-off-by: Martin Krause - -commit b988b8cd443989be65161888eea0127ad03f846f -Author: Martin Krause -Date: Wed Sep 26 17:55:56 2007 +0200 - - TQM885D: use calculated cpuclk instead of measuring it - - On the TQM885D the measurement of cpuclk with the PIT reference - timer ist not necessary. Since all module variants use the same - external 10 MHz oscillator, the cpuclk only depends on the PLL - configuration - which is readable by software. - - Signed-off-by: Martin Krause - -commit 492c7049869348d31168de8dad89651315e468e0 -Author: Jens Gehrlein -Date: Thu Sep 27 14:54:46 2007 +0200 - - TQM885D: fix SDRAM refresh - - At 133 MHz the current SDRAM refresh rate is too fast - (measured 4 * 1.17 us). - CFG_MAMR_PTA changes from 39 to 128. This result - in a refresh rate of 4 * 7.8 us at the default clock - 66 MHz. At 133 MHz the value will be then 4 * 3.8 us. - This is a compromise until a new method is found to - adjust the refresh rate. - - Signed-off-by: Martin Krause - -commit dabad4b9bc46908e301f73ce76b38b23626a96e9 -Author: Jens Gehrlein -Date: Thu Sep 27 14:54:46 2007 +0200 - - TQM860M: Support for 10col SDRAMs, max. 128 MiB - - Signed-off-by: Martin Krause - -commit 61fb15c516fef5631e305f1976d7b3a679725856 -Author: Wolfgang Denk -Date: Thu Dec 27 01:52:50 2007 +0100 - - Fix coding style issues; update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit 467bcee11fe26ad422f2de971aa70866079870f2 -Author: Haavard Skinnemoen -Date: Fri Dec 14 15:36:18 2007 +0100 - - cfi_flash: Add manufacturer-specific fixups - - Run fixups based on the JEDEC manufacturer ID independent of the - command set ID. - - This changes current behaviour: Previously, geometry reversal for AMD - chips were done based on the command set ID, while they are now done - based on the JEDEC manufacturer and device ID. - - Also add fixup for top-boot Atmel chips. A fixup is needed for - AT49BV6416(T) too, but since u-boot currently only reads the low byte - of the device ID, there's no way to tell it apart from AT49BV642D, - which should not have this fixup. Since AT49BV642D support is - necessary to get ATNGW100 board support into mainline, I've commented - out the fixup for now. - - Signed-off-by: Haavard Skinnemoen - -commit 0ddf06ddf6b4bd057ad4c5f0dffea7870ba06a2a -Author: Haavard Skinnemoen -Date: Fri Dec 14 15:36:17 2007 +0100 - - cfi_flash: Add cmdset-specific init functions - - Move things like reading JEDEC IDs and fixing up geometry reversal - into separate functions. The geometry reversal fixup is now performed - by altering the qry structure directly, which makes the sector init - code slightly cleaner. - - Signed-off-by: Haavard Skinnemoen - -commit e23741f4a6d8047520ef0d4971762749b3587d32 -Author: Haavard Skinnemoen -Date: Fri Dec 14 15:36:16 2007 +0100 - - cfi_flash: Read whole QRY structure in one go - - Read out the whole CFI Standard Query structure after successful cfi - identification. This allows subsequent code to access this information - directly without having to go through flash_read_uchar() and friends. - - Signed-off-by: Haavard Skinnemoen - -commit df9c25ea04b38a0e05d4f8c73c5cc144cdafa7db -Author: Haavard Skinnemoen -Date: Mon Dec 17 11:02:44 2007 +0100 - - AVR32: Fix logic inversion in disable_interrupts() - - disable_interrupts() should return nonzero if interrupts were - _enabled_ before, not disabled. - - Signed-off-by: Haavard Skinnemoen - -commit acac475212cbedb17b321a363a1c878e2b47b37f -Author: Haavard Skinnemoen -Date: Fri Dec 14 16:51:22 2007 +0100 - - AVR32: Enable interrupts at bootup - - The timer code depends on the timer interrupt to keep track of the - upper 32 bits of the cycle counter. This obviously doesn't work when - interrupts are disabled the whole time. - - Signed-off-by: Haavard Skinnemoen - -commit 9570bcd87f4db255514f43b6701746c412f8fef0 -Author: Haavard Skinnemoen -Date: Thu Nov 15 10:03:45 2007 +0100 - - AVR32: Fix wrong pin setup for USART3 - - As reported by Gerhard Berghofer: - - in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18 - instead of PB18 and PB19. - - which is obviously correct. There's currently no code that uses - USART3, but custom boards may run into problems. - - Signed-off-by: Haavard Skinnemoen - -commit 09ea0de03dcc3ee7af045b0b572227bda2c1c918 -Author: Haavard Skinnemoen -Date: Thu Nov 1 12:44:20 2007 +0100 - - README: Remove ATSTK1000 daughterboard list - - As noted by Kim Phillips, these lists tend to become out of date. - - Signed-off-by: Haavard Skinnemoen - -commit c81cbbad21cb0ae983e2e796211202234cdc8be2 -Author: Haavard Skinnemoen -Date: Tue Oct 30 14:56:36 2007 +0100 - - Add ATSTK100[234] to MAINTAINERS - - Add all the ATSTK1000 daughterboards to MAINTAINERS along with their - "mother". Also update the entry for ATSTK1000 to be not only about the - AP7000 CPU; it's intended to handle all CPUs in the AT32AP family. - - Signed-off-by: Haavard Skinnemoen - -commit 64ff2357b1727213803591813dbc779c924bf772 -Author: Haavard Skinnemoen -Date: Mon Oct 29 13:02:54 2007 +0100 - - AVR32: Add support for the ATSTK1004 board - - ATSTK1004 is a daughterboard for ATSTK1000 with the AT32AP7002 CPU, - which is a derivative of AT32AP7000. - - Signed-off-by: Haavard Skinnemoen - -commit 667568db157f374b85abd7e03596ddd1f0b25681 -Author: Haavard Skinnemoen -Date: Mon Oct 29 13:02:54 2007 +0100 - - AVR32: Add support for the ATSTK1003 board - - ATSTK1003 is a daughterboard for ATSTK1000 with the AT32AP7001 CPU, - which is a derivative of AT32AP7000. - - Signed-off-by: Haavard Skinnemoen - -commit 5fee84a794a51ec830548cda485a770efb018b92 -Author: Haavard Skinnemoen -Date: Mon Oct 29 13:23:33 2007 +0100 - - AVR32: Make some AT32AP700x peripherals optional - - Add a chip-features file providing definitions of the form - - AT32AP700x_CHIP_HAS_ - - to indicate the availability of the given peripheral on the currently - selected chip. - - Signed-off-by: Haavard Skinnemoen - -commit 36f28f8a9605ee5dcfa330482cfc62171261af97 -Author: Haavard Skinnemoen -Date: Mon Oct 29 13:09:56 2007 +0100 - - AVR32: Rename at32ap7000 -> at32ap700x - - The SoC-specific code for all the AT32AP700x CPUs is practically - identical; the only difference is that some chips have less features - than others. By doing this rename, we can add support for the AP7000 - derivatives simply by making some features conditional. - - Signed-off-by: Haavard Skinnemoen - -commit 4d5fa99c73f354e7cf985efcf417ea55ca2f6a5e -Author: Haavard Skinnemoen -Date: Fri Jun 29 18:22:34 2007 +0200 - - atmel_mci: Show SR when block read fails - - Show controller status as well as card status when an error occurs - during block read. - - Signed-off-by: Haavard Skinnemoen - -commit 8697e6a19b10f514511b6a9c86de88bd108c4f8d -Author: Stefan Roese -Date: Thu Dec 13 14:52:53 2007 +0100 - - ppc4xx: Bring 4xx fdt support up-to-date - - This patch update the 4xx fdt support. It enabled fdt booting - on the AMCC Kilauea and Sequoia for now. More can follow later - quite easily. - - Signed-off-by: Stefan Roese - -commit 12d30aa79779c2aa7a998bbae4c075f822a53004 -Author: Haavard Skinnemoen -Date: Thu Dec 13 12:56:34 2007 +0100 - - cfi_flash: Use map_physmem() and unmap_physmem() - - Use map_physmem() and unmap_physmem() to convert from physical to - virtual addresses. This gives the arch a chance to provide an uncached - mapping for flash accesses. - - Signed-off-by: Haavard Skinnemoen - -commit 4d7d6936eb29af7cca330937808312aa5f61454d -Author: Haavard Skinnemoen -Date: Thu Dec 13 12:56:33 2007 +0100 - - Introduce map_physmem() and unmap_physmem() - - map_physmem() returns a virtual address which can be used to access a - given physical address without involving the cache. unmap_physmem() - should be called when the virtual address returned by map_physmem() is - no longer needed. - - This patch adds a stub implementation which simply returns the - physical address cast to a uchar * for all architectures except AVR32, - which converts the physical address to an uncached virtual mapping. - unmap_physmem() is a no-op on all architectures, but if any - architecture needs to do such mappings through the TLB, this is the - hook where those TLB entries can be invalidated. - - Signed-off-by: Haavard Skinnemoen - -commit cdbaefb5f5f03e54455d0439dcf6dbd97ead1f9d -Author: Haavard Skinnemoen -Date: Thu Dec 13 12:56:32 2007 +0100 - - cfi_flash: Introduce read and write accessors - - Introduce flash_read{8,16,32,64) and flash_write{8,16,32,64} and use - them to access the flash memory. This makes it clearer when the flash - is actually being accessed; merely dereferencing a volatile pointer - looks just like any other kind of access. - - Signed-off-by: Haavard Skinnemoen - -commit 812711ce6b3a386125dcf0d6a59588e461abbb87 -Author: Haavard Skinnemoen -Date: Thu Dec 13 12:56:31 2007 +0100 - - Implement __raw_{read,write}[bwl] on all architectures - - This adds implementations of __raw_read[bwl] and __raw_write[bwl] to - m68k, ppc, nios and nios2. The m68k and ppc implementations were taken - from Linux. - - Signed-off-by: Haavard Skinnemoen - -commit be60a9021c82fc5aecd5b2b1fc96f70a9c81bbcd -Author: Haavard Skinnemoen -Date: Sat Oct 6 18:55:36 2007 +0200 - - cfi_flash: Reorder functions and eliminate extra prototypes - - Reorder the functions in cfi_flash.c so that each function only uses - functions that have been defined before it. This allows the static - prototype declarations near the top to be eliminated and might allow - gcc to do a better job inlining functions. - - Signed-off-by: Haavard Skinnemoen - -commit 3055793bcbdf24b1f8117f606ffb766d32eb766f -Author: Haavard Skinnemoen -Date: Thu Dec 13 12:56:29 2007 +0100 - - cfi_flash: Make some needlessly global functions static - - Make functions not declared in any header file static. - - Signed-off-by: Haavard Skinnemoen - -commit 7e5b9b471518c5652febc68ba62b432193d6abf4 -Author: Haavard Skinnemoen -Date: Thu Dec 13 12:56:28 2007 +0100 - - cfi_flash: Break long lines - - This patch tries to keep all lines in the cfi_flash driver below 80 - columns. There are a few lines left which don't fit this requirement - because I couldn't find any trivial way to break them (i.e. it would - take some restructuring, which I intend to do in a later patch.) - - Signed-off-by: Haavard Skinnemoen - -commit 42026c9cb3a76849b41e6e24abfb7b56807a5c1a -Author: Bartlomiej Sieka -Date: Tue Dec 11 13:59:57 2007 +0100 - - CFI: synchronize command offsets with Linux CFI driver - - Fixes non-working CFI Flash on the Inka4x0 board. - - Signed-off-by: Bartlomiej Sieka - -commit 8ff3de61fc5f9b3b21647bce081a3b7f710f0d4d -Author: Kumar Gala -Date: Fri Dec 7 12:17:34 2007 -0600 - - Handle MPC85xx PCIe reset errata (PCI-Ex 38) - - On the MPC85xx boards that have PCIe enable the PCIe errata fix. - (MPC8544DS, MPC8548CDS, MPC8568MDS). - - Signed-off-by: Kumar Gala - -commit 82ac8c97145a4c3bf8b3dbfad00fa96e920f9b9c -Author: Kumar Gala -Date: Fri Dec 7 12:04:30 2007 -0600 - - Update Freescale MPC85xx ADS/CDS/MDS board config - - * Enabled CONFIG_CMD_ELF - - Signed-off-by: Kumar Gala - -commit d435793229ce29a42797c1edc39f5b34f987f91a -Author: Kumar Gala -Date: Fri Dec 7 04:59:26 2007 -0600 - - Handle Asynchronous DDR clock on 85xx - - The MPC8572 introduces the concept of an asynchronous DDR clock with - regards to the platform clock. - - Introduce get_ddr_freq() to report the DDR freq regardless of sync/async - mode. - - Signed-off-by: Kumar Gala - -commit 22abb2d2eaf7b795a6923c6273ec9cb53fda9a10 -Author: Kumar Gala -Date: Thu Nov 29 10:34:28 2007 -0600 - - Update Freescale MPC85xx ADS/CDS/MDS board config - - * Removed some misc environment setup - * Enabled CONFIG_CMDLINE_EDITING - - Signed-off-by: Kumar Gala - -commit 415a613babb84d5e5d5b42e8e553868c71fc3a64 -Author: Kumar Gala -Date: Thu Nov 29 10:47:44 2007 -0600 - - Move the MPC8541/MPC8555/MPC8548 CDS board under board/freescale. - - Minor path corrections needed to ensure buildability. - - Signed-off-by: Kumar Gala - -commit c2d943ffbfd3359b3b45d177b437379d2cb86fbf -Author: Kumar Gala -Date: Thu Nov 29 10:16:18 2007 -0600 - - Move the MPC8540 ADS board under board/freescale. - - Minor path corrections needed to ensure buildability. - - Signed-off-by: Kumar Gala - -commit 870ceac5b3a3486c109396e005af81ae762b5710 -Author: Kumar Gala -Date: Thu Nov 29 10:14:50 2007 -0600 - - Move the MPC8560 ADS board under board/freescale. - - Minor path corrections needed to ensure buildability. - - Signed-off-by: Kumar Gala - -commit acbca876fb3fec25cd9c55b0efc81ff618ff5262 -Author: Kumar Gala -Date: Thu Nov 29 10:13:47 2007 -0600 - - Move the MPC8568 MDS board under board/freescale. - - Minor path corrections needed to ensure buildability. - - Signed-off-by: Kumar Gala - -commit a853d56c59b33415304531443633808736acfc6e -Author: Kumar Gala -Date: Thu Nov 29 02:18:59 2007 -0600 - - Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx - - We already had defines for LAWAR_TRGT_IF_* that we should use - rather than creating new ones. Also, added some missing defines for - PCIE targets. - - Signed-off-by: Kumar Gala - -commit 04db400892da37b76a585e332a0c137954ad2015 -Author: Kumar Gala -Date: Thu Nov 29 02:10:09 2007 -0600 - - Stop using immap_t on 85xx - - In the future the offsets to various blocks may not be in same location. - Move to using CFG_MPC85xx_*_ADDR as the base of the registers - instead of getting it via &immap. - - Signed-off-by: Kumar Gala - -commit 2714223f8e04ab3e4133ff65872eef366d90bfea -Author: Kumar Gala -Date: Thu Nov 29 01:23:09 2007 -0600 - - Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdt - - Signed-off-by: Kumar Gala - -commit c480861bf000156e6a3e932c258db59ff2212dd3 -Author: Kumar Gala -Date: Thu Nov 29 01:06:19 2007 -0600 - - Update MPC8568 MDS to use libfdt - - Updated the MPC8568 MDS config to use libfdt and assume use of aliases for - ethernet, pci, and serial for the various fixups that are done. - - Signed-off-by: Kumar Gala - -commit 1563f56e0c68f6920f956382d6d13bee3f01c0f7 -Author: Haiying Wang -Date: Wed Nov 14 15:52:06 2007 -0500 - - Add PCI Express support on MPC8568MDS - - Signed-off-by: Haiying Wang - Signed-off-by: Kumar Gala - -commit b90d25497625b90ffa3f2911a0895ca237556ff5 -Author: Kumar Gala -Date: Thu Nov 29 00:11:44 2007 -0600 - - Update MPC85xx CDS to use libfdt - - Updated the MPC85xx CDS config to use libfdt and assume use of aliases for - ethernet, pci, and serial for the various fixups that are done. - - Signed-off-by: Kumar Gala - -commit 0fd5ec66b10521a057ad73e69ab5f0f9eafba255 -Author: Kumar Gala -Date: Wed Nov 28 22:54:27 2007 -0600 - - Update MPC8540 ADS to use libfdt - - Updated the MPC8540 ADS config to use libfdt and assume use of aliases for - ethernet, pci, and serial for the various fixups that are done. - - Signed-off-by: Kumar Gala - -commit 5ce715802f6c50dc78b3405b92f184b1e3710519 -Author: Kumar Gala -Date: Wed Nov 28 22:40:31 2007 -0600 - - Update MPC8560 ADS to use libfdt - - Updated the MPC8560 ADS config to use libfdt and assume use of aliases for - ethernet, pci, and serial for the various fixups that are done. - - Signed-off-by: Kumar Gala - -commit aafeefbdb8b029f5ca2a195598d0a501a606eea9 -Author: Kumar Gala -Date: Wed Nov 28 00:36:33 2007 -0600 - - Stop using immap_t for cpm offset on 85xx - - In the future the offsets to various blocks may not be in same location. - Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers - instead of getting it via &immap->im_cpm. - - Signed-off-by: Kumar Gala - -commit f59b55a5b8fcadaa99781ba48e7a38e956afa527 -Author: Kumar Gala -Date: Tue Nov 27 23:25:02 2007 -0600 - - Stop using immap_t for guts offset on 85xx - - In the future the offsets to various blocks may not be in same location. - Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers - instead of getting it via &immap->im_gur. - - Signed-off-by: Kumar Gala - -commit 50c03c8cf494d91cdec39670d95337c743e16ec9 -Author: Kumar Gala -Date: Tue Nov 27 22:42:34 2007 -0600 - - Update MPC8544 DS config - - * Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2 - * Removed some misc environment setup - * Moved to using fdtfile & fdtaddr as fdt env var names - * Enabled CONFIG_CMDLINE_EDITING - - Signed-off-by: Kumar Gala - -commit addce57e2e4c49e77ffb2020a84690713bb18b47 -Author: Kumar Gala -Date: Mon Nov 26 17:12:24 2007 -0600 - - Update MPC8544DS to use libfdt - - Updated the MPC8544DS config to use libfdt and assume use of aliases for - ethernet, pci, and serial for the various fixups that are done. - - Signed-off-by: Kumar Gala - -commit f852ce72f100cabd1f11c21c085a0ad8eca9fb65 -Author: Kumar Gala -Date: Thu Nov 29 00:15:30 2007 -0600 - - Add libfdt based ft_cpu_setup for mpc85xx - - Signed-off-by: Kumar Gala - -commit 3b9abdc448a1c2c6a4c2aa292724b4d1a05166a9 -Author: Stefan Roese -Date: Tue Dec 11 13:38:19 2007 +0100 - - ppc4xx: Correct GPIO offset in gpio_config() - - Thanks to Gary Jennejohn for pointing this out. - - Signed-off-by: Stefan Roese - -commit 8809a2713b1ceaf3da55d9d785470294f15de06a -Author: Stefan Roese -Date: Tue Dec 11 11:46:01 2007 +0100 - - rtc: Fix merging problem - - Signed-off-by: Stefan Roese - -commit 7cfc12a7dcfdb350e2ab76db4dafcc30f7e77c2b -Author: Stefan Roese -Date: Sat Dec 8 14:47:34 2007 +0100 - - ppc4xx: 405EX: Correctly enable USB pins - - This patch selects the USB data pins in the 405EX GPIO and MFC (multi - function control) registers. This is done for the AMCC Kilauea and - Makalu eval boards. - - Signed-off-by: Stefan Roese - -commit 9692c2734a47f23b44a0f68042a3e2ca8d1bfb39 -Author: Stefan Roese -Date: Sat Dec 8 08:25:09 2007 +0100 - - CFI: Coding style cleanup - - Signed-off-by: Stefan Roese - -commit 81b20ccc2d795ae9a1199db5a50ad9c28d1e4d22 -Author: Michael Schwingen -Date: Fri Dec 7 23:35:02 2007 +0100 - - CFI: support JEDEC flash roms in CFI-flash framework - - The following patch adds support for non-CFI flash ROMS, by hooking into the - CFI flash code and using most of its code, as recently discussed here in the - thread "Mixing CFI and non-CFI flashs". - - Signed-off-by: Michael Schwingen - Signed-off-by: Stefan Roese - -commit c01b17dd856fa120b2970f50d9598546a4927ec3 -Author: Gerald Van Baren -Date: Wed Nov 28 21:24:50 2007 -0500 - - Conditionally compile fdt_fixup_ethernet() - - Fix compiler warnings: On boards that don't have ethernets defined, - don't compile fdt_fixup_ethernet(). - -commit 246d4ae6bc282bc1841224e1c5fc49dc925e0bf7 -Author: Kumar Gala -Date: Tue Nov 27 21:59:46 2007 -0600 - - Convert boards that set memory node to use fdt_fixup_memory() - - Signed-off-by: Kumar Gala - -commit 151c8b09b35eebe8fd9139cb6c1d91c27b22f058 -Author: Kumar Gala -Date: Mon Nov 26 17:06:15 2007 -0600 - - Added fdt_fixup_stdout that uses aliases to set linux,stdout-path - - We use a combination of the serialN alias and CONFIG_CONS_INDEX to - determine which serial alias we should set linux,stdout-path to. - - Signed-off-by: Kumar Gala - -commit 3c9272813fad84c691d0e4989bb18a3ffebdebfc -Author: Kumar Gala -Date: Mon Nov 26 14:57:45 2007 -0600 - - Add common memory fixup function - - Add the function fdt_fixup_memory() to fixup the /memory node of the fdt - - Signed-off-by: Kumar Gala - -commit 9c9109e7fcf7ac2ca19c95b8ac54b8d1c773b157 -Author: Kumar Gala -Date: Mon Nov 26 11:19:12 2007 -0600 - - Conditionally compile fdt_support.c - - Modify common/Makefile to conditionally compile fdt_support.c based - on CONFIG_OF_LIBFDT. - - Signed-off-by: Kumar Gala - -commit d88e7ba0980773479e1a64badb293116071b7ef0 -Author: Kumar Gala -Date: Mon Nov 26 10:41:40 2007 -0600 - - Fix build breakage due to libfdt import - - The IDS8247 got lost in the update and need an API update - do to rename of functions in libfdt. - - Signed-off-by: Kumar Gala - -commit 28f384b171bbf1fb2dafb1046e6d259a6b2f8714 -Author: Gerald Van Baren -Date: Fri Nov 23 19:43:20 2007 -0500 - - Add spaces around the = in the fdt print format. - - Signed-off-by: Gerald Van Baren - -commit 29592ecba3b932b9b152bcec6c0c0806412db4a3 -Author: Nobuhiro Iwamatsu -Date: Fri Dec 7 01:25:38 2007 +0900 - - sh: Moved driver of the SuperH dependence - - The composition of the directory in the drivers/ changed. - I moved SuperH serial driver and marubun PCMCIA driver. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 41be969f4957115ed7b1fe8b890bfaee99d7a7a2 -Author: Wolfgang Denk -Date: Thu Dec 6 10:21:19 2007 +0100 - - Release v1.3.1 - - Signed-off-by: Wolfgang Denk - -commit cf5933ba1e97a1cd8f5f24070e820f21d976eaeb -Author: Wolfgang Denk -Date: Thu Dec 6 10:21:03 2007 +0100 - - ADS5121 Board: fix compile problem. - - Signed-off-by: Wolfgang Denk - -commit a27044b14a9e93678a82d7b35f202b93e7687abc -Author: Stefan Roese -Date: Thu Dec 6 05:58:43 2007 +0100 - - ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boards - - This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by - setting the FIXD bit in the SDR0_MFR register. Here a description of the - symptoms: - - Problem Description - ------------------------------ - If a DMA is performed between memory and PCI with the DMA 1 Controller - using prefetch, and as a result uses a special purpose buffer selected by - the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29), - the first part of the transfer sequence is performed twice. The - PPC440SPe PCI Controller requests more data than was needed such that in - the case of enforce memory protection, a host CPU exception can occur. - No data is corrupted, because data transfer is stopped in the PCI - Controller. Prefetch enable is specified by setting DMA Configuration - Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0. - - Behavior that may be observed in a running system - --------------------------------------------------------------------------- - - 1. DMA performance is decreased because of the double access on the PCI bus - interface. - 2. If an illegal access to some address on the PCI bus is detected at the - system level, a machine check or similar system error may occur. - - Workarounds Available - ---------------------------------- - - 1. Do not program prefetch. Note that a prefetch command cannot be programmed - without selecting a special purpose buffer. - 2. To avoid crossing a physical boundary of the PCI slave device, add 512 - bytes of address to the PCI address range. - - This patch was originally provided by Pravin M. Bathija - from AMCC and slighly changed. - - Signed-off-by: Pravin M. Bathija - Signed-off-by: Stefan Roese - -commit a90921f71d225bf9e0f0fc7b8beadeb8001bf78a -Author: Stefan Roese -Date: Tue Dec 4 16:29:48 2007 +0100 - - ppc4xx: Yosemite/Yellowstone: Add DTT AD7414 support - - Signed-off-by: Stefan Roese - -commit 8d4f040a3c15036a6ea25a9c39e7d89fefa8440d -Author: Wolfgang Denk -Date: Mon Dec 3 00:15:28 2007 +0100 - - Prepare for 1.3.1-rc1 - - Signed-off-by: Wolfgang Denk - -commit e15e33433e7c05111968dc9b434a52fd42cbd221 -Author: Stefan Roese -Date: Fri Nov 30 07:15:41 2007 +0100 - - ppc4xx: Kilauea: Add PCIe reset assertion upon power-up - - This manual PCIe reset triggering solves the problem seen with the - Intel EPRO/1000 card, which was not detected (link not established) - upon power-up reset. - - Signed-off-by: Stefan Roese - -commit 260eea5676ca46903a335686cc020b29c4ca46fe -Author: Nobuhiro Iwamatsu -Date: Thu Nov 29 01:21:54 2007 +0900 - - sh: Add SuperH boards maintainer to MAINTAINERS file - - Add MS7750SE and MS7722SE's board maintainer to MAINTAINERS file. - - Signed-off-by: Nobuhiro Iwamatsu - -commit aa9c4f1d22701a92347c1c81f34d12c8ad3a3747 -Author: Nobuhiro Iwamatsu -Date: Thu Nov 29 00:13:04 2007 +0900 - - sh: Add ms7750se support in MAKEALL - - Signed-off-by: Nobuhiro Iwamatsu - -commit c7144373427a178332bf9754131c8c34c52c200a -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Tue Nov 27 09:44:53 2007 +0100 - - sh: Add sh3 and sh4 support in MAKEALL - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Nobuhiro Iwamatsu - -commit 130080874a3d28450098481a262c5f7c855e908d -Author: Nobuhiro Iwamatsu -Date: Sun Nov 25 02:51:17 2007 +0900 - - sh: Add document for SuperH. - - This document is a summary of information concerning SuperH of U-Boot. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 33ecdc2f9d64926e1a6067b28f3a0aefc3b6d23d -Author: Nobuhiro Iwamatsu -Date: Sun Nov 25 02:39:31 2007 +0900 - - sh: Add marubun's pcmcia driver - - Marubun pcmcia is a chip for PCMCIA used with SuperH. - Of course, this can be used even by other architectures. - When use this driver, came to be able to use CompactFlash - and Ethernet. - - Signed-off-by: Nobuhiro Iwamatsu - -commit febd86b969b975289ed948f1ac0eb9722da41ced -Author: Nobuhiro Iwamatsu -Date: Sun Nov 25 02:32:13 2007 +0900 - - sh: Update SuperH SCIF driver - - - Changed volatile unsigned to vu_. - - Changed Makefile for kconfig. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 8be760903645af09871be50ad0a6f9ebb62b311d -Author: Stefan Roese -Date: Tue Nov 27 11:57:35 2007 +0100 - - ppc4xx: Kilauea & Makalu: Fix ext IRQ pin multiplexing - - After an error in the AMCC 405EX users manual now correctly configure - IRQ2 (Kilauea)/IRQ0 (Makalu) as alternate 2 signal for external IRQ - usage. - - Signed-off-by: Stefan Roese - -commit a5f601fd1b1278deae5aa9fc27a232b0d1c1c788 -Author: Wolfgang Denk -Date: Mon Nov 26 19:18:21 2007 +0100 - - Cleanup coding style; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 3deca9d44767efd1b83f4b701f0dbf21a7595f7b -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Nov 25 22:39:25 2007 +0100 - - MAKEALL: add missing 512x boards in ppc - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit a340c325e668ca7386c2276387681720be9c3757 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Nov 25 18:45:47 2007 +0100 - - Makefile : fix tags ctags etags with new drivers organization - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 63362cfc6baa97ae0e37ba2c6ece530fcac9f79e -Author: Stefan Roese -Date: Mon Nov 26 15:06:14 2007 +0100 - - ppc4xx: Makalu: Change EBC setup for CS0 to enable 400MHz usage - - As suggested by Senao, use a different EBC_PB0AP setup for 400MHz - operation. - - Signed-off-by: Stefan Roese - -commit ca1ce226287270bb01e25b8e3674c701f12edf19 -Author: Stefan Roese -Date: Mon Nov 26 15:01:45 2007 +0100 - - ppc4xx: Kilauea: Configure pin mux to use ext IRQ2 as interrupt - - Signed-off-by: Stefan Roese - -commit 87ddedd6ad804427ce125ceaa076d7a4f74e9d5d -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Nov 25 18:45:47 2007 +0100 - - Makefile : fix tags ctags etags with new drivers organization - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 59829cc189378c142c13d2aa8d9a897d8bef3961 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Nov 24 21:26:56 2007 +0100 - - drivers/mtd : move mtd drivers to drivers/mtd - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 318c0b90431f2648552e5ade78833f42652ce859 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Nov 24 21:17:55 2007 +0100 - - drivers/misc : move misc drivers to drivers/misc - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 33daf5b7858807cb4ce4158c2c56524671c14c08 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Nov 24 21:13:59 2007 +0100 - - drivers/block : move block drivers to drivers/block - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 0c698dcaa70275eb8814f665b545547cee013892 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Nov 24 20:59:50 2007 +0100 - - drivers/rtc : move rtc drivers to drivers/rtc - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit f868cc5a50757d94f36c312395481cb0f187d9e6 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Nov 24 20:14:44 2007 +0100 - - drivers/hwmon : move hardware monitor drviers to drivers/hwmon - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 16b195c82a18cbfd164800f17a1ef9db2e48331a -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Nov 24 19:46:45 2007 +0100 - - drivers/input : move input drivers to drivers/input - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit e4558666293364fc3af1c1d9381ca933fa0f1275 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Nov 24 19:40:11 2007 +0100 - - drivers/usb : move usb drivers to drivers/usb - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 1378df792a7ff3abd1bf54a63f5475784f5b083c -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Nov 24 19:33:38 2007 +0100 - - drivers/serial : move serial drivers to drivers/serial - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 2439e4bfa111babf4bc07ba20efbf3e36036813e -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Wed Nov 21 21:19:24 2007 +0100 - - drivers/net : move net drivers to drivers/net - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 352d259130b349fe9593b8dada641bd78a9659e5 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Tue Nov 20 20:41:48 2007 +0100 - - drivers/video : move video drivers to drivers/video - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 73646217186aa17afc8e305c5f06f06dd335eaad -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Tue Nov 20 20:33:09 2007 +0100 - - drivers/pcmcia : move pcmcia drivers to drivers/pcmcia - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 93a686ee9c5ddc6fa368c32cfbfde6f6724599fc -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Tue Nov 20 20:28:09 2007 +0100 - - drivers/pci : move pci drivers to drivers/pci - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 9162352817579840d7802da6d85872b3ca003c97 -Author: Gerald Van Baren -Date: Thu Nov 22 17:23:23 2007 -0500 - - Fix fdt printing for updated libfdt - - Also improve printing (adopt dtc v1 "c style" hex format), whitespace cleanup. - - Signed-off-by: Gerald Van Baren - -commit 9eb77cea1fa12d5969eb26a1d1d81da381bd6b1c -Author: Kumar Gala -Date: Wed Nov 21 13:30:15 2007 -0600 - - Add additional fdt fixup helper functions - - Added the following fdt fixup helpers: - * do_fixup_by_prop{_u32} - Find matching nodes by property name/value - * do_fixup_by_compat{_u32} - Find matching nodes by compat - - The _u32 variants work the same only the property they are setting - is know to be a 32-bit integer instead of a byte buffer. - - Signed-off-by: Kumar Gala - -commit ab544633abdd14f4dd5d92e500b73eb59ef57e67 -Author: Kumar Gala -Date: Wed Nov 21 11:11:03 2007 -0600 - - Add fdt_fixup_ethernet helper to set mac addresses - - Added a fixup helper that uses aliases to set mac addresses - in the device tree based on the bd_t - - Signed-off-by: Kumar Gala - -commit dbaf07ce620aab249e3502b20a986234a6af1d3a -Author: Kumar Gala -Date: Wed Nov 21 14:07:46 2007 -0600 - - Fix warnings from import of libfdt - - cmd_fdt.c: In function fdt_print: - cmd_fdt.c:586: warning: assignment discards qualifiers from pointer target type - cmd_fdt.c:613: warning: assignment discards qualifiers from pointer target type - cmd_fdt.c:635: warning: assignment discards qualifiers from pointer target type - cmd_fdt.c:636: warning: assignment discards qualifiers from pointer target type - - Signed-off-by: Kumar Gala - -commit 8d04f02f6224e6983f4812ea4da704950ec8539c -Author: Kumar Gala -Date: Wed Oct 24 11:04:22 2007 -0500 - - Update libfdt from device tree compiler (dtc) - - Update libfdt to commit 8eaf5e358366017aa2e846c5038d1aa19958314e from - the device tree compiler (dtc) project. - - Signed-off-by: Kumar Gala - -commit e93becf80d732b64aef81b23e8b6ece02c40533d -Author: Kumar Gala -Date: Sat Nov 3 19:46:28 2007 -0500 - - Move do_fixup* for libfdt into common code - - Moved the generic fixup handling code out of cpu/mpc5xxx and cpu/mpc8260 - into common/fdt_support.c and renamed: - - do_fixup() -> do_fixup_by_path() - do_fixup_u32() -> do_fixup_by_path_u32() - - Signed-off-by: Kumar Gala - -commit f738b4a75998f42a7408defadc9baac7a31c92db -Author: Kumar Gala -Date: Thu Oct 25 16:15:07 2007 -0500 - - Make no options to fdt print default to '/' - - Signed-off-by: Kumar Gala - -commit a3c2933e02503fe36ade2c1b65af46f2b7a168e7 -Author: Kumar Gala -Date: Wed Oct 24 10:21:57 2007 -0500 - - Removed some nonused fdt functions and moved fdt_find_and_setprop out of libfdt - - Removed: - fdt_node_is_compatible - fdt_find_node_by_type - fdt_find_compatible_node - - To ease merge of newer libfdt as we aren't using them anywhere at this time. - - Also moved fdt_find_and_setprop out of libfdt into fdt_support.c for the same - reason. - - Signed-off-by: Kumar Gala - -commit 98e2867cc85409b919f862e6c16026461ec955df -Author: Grant Likely -Date: Wed Nov 21 09:19:37 2007 -0700 - - [BUILD] Remove libraries when updating autoconf.mk - - Fix library problems caused by conditional compilation. Using - autoconf.mk to decide which files to compile has caused a problem when - changing configuration from one board to another without clearing out - the library (*.a) files. - - It used to be that the linker was always passed the same list of .o - files when building the .a files. However, that is not longer true - with conditional compilation. Now, a different board config will have - a different file list passed to the linker. The problem occurs when - a library has already been built and the board config is changed. - - Since the linker will update instead of replace a preexisting library, - then if the file list changes to remove some object files the old - objects will still exist in the library. - - The solution is to remove all old library files when autoconf.mk is - made. - - Signed-off-by: Grant Likely - -commit ed1353d74b9ce8a7fcd660570b848a184d614b5f -Author: Kumar Gala -Date: Wed Nov 21 08:49:50 2007 -0600 - - [BUILD] conditionally compile libfdt/*.c in libfdt/Makefile - - Modify libfdt/Makefile to conditionally compile the *.c files based - on the board config. - - Signed-off-by: Kumar Gala - -commit 4a43719a7738712811d822ca8125427b27a55cdc -Author: Grant Likely -Date: Mon Sep 24 09:05:31 2007 -0600 - - [BUILD] conditionally compile common/cmd_*.c in common/Makefile - - Modify common/Makefile to conditionally compile the cmd_*.c files based - on the board config. - - Signed-off-by: Grant Likely - -commit 2f155f6c0a1f5e9a306a3f1f4fbe067db7ced3b1 -Author: Grant Likely -Date: Mon Sep 24 09:05:31 2007 -0600 - - [BUILD] Generate include/autoconf.mk from board config files - - Use cpp and sed to postprocess config.h and import the defined values - into include/autoconf.mk. autoconf.mk is then included by config.mk to - give 'make' access to the board configuration. - - Doing this enables conditional compilation at the Makefile level instead - of by wrapping every .c file with #ifdef/#endif wrappers. - - Signed-off-by: Grant Likely - -commit 68b88999da87ab88e71e1306192905be3450198e -Author: Jon Loeliger -Date: Tue Nov 20 15:02:26 2007 -0600 - - 8610HPCD: Enable the 8610 Display Interface Unit - - Signed-off-by: Jon Loeliger - -commit 74f89faa9d1e77ed947e628d3effaa513fe05d05 -Author: Jon Loeliger -Date: Tue Nov 20 15:00:53 2007 -0600 - - Move 8610 DIU interface structure definitions to header file. - - These two structures are still needed during the - initialization and setup of the DIU hardware. - So move them to the fsl_diu_fb.h file for now. - Official "blah". - - Noticed-by: York Sun - Signed-off-by: Jon Loeliger - -commit 080c646dbf474a109c3f85718fb01ce042a38c45 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Tue Nov 20 20:14:18 2007 +0100 - - drivers/i2c : move i2c drivers to drivers/i2c - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 9a337ddc154a10a26f117fd147b009abcdeba75a -Author: Wolfgang Denk -Date: Mon Nov 19 22:20:24 2007 +0100 - - Prepare for 1.3.0 release. - - Signed-off-by: Wolfgang Denk - -commit f30ad49b16bf998b03c1a5228b6c86369d61c258 -Author: Haiying Wang -Date: Mon Nov 19 10:02:13 2007 -0500 - - Move CONFIG_QE out of CONFIG_PCI wrap for MPC8568MDS - - CONFIG_QE shouldn't be in the wrap of CONFIG_PCI, fix it. - - Signed-off-by: Haiying Wang - -commit f8c320609366176b31104d9bf5e295232e1c7f1d -Author: Shinya Kuribayashi -Date: Mon Nov 19 11:14:16 2007 +0900 - - [MIPS] board/gth2/lowlevel_init.S: Fix a build warning - - lowlevel_init.S: Assembler messages: - lowlevel_init.S:413: Warning: Pretending global symbol used as branch target is local. - - Looking at codes, the `memtest' and `clearmem' are intentional mixed - use of `global symbols' and `label' for debugging purpose. To make it - build, just disable global-symbols-use for now. As a result `memtest' - still remains as unused, but leave it be... - - Signed-off-by: Shinya Kuribayashi - -commit e8da58f2bc092891e8cc92b927ed5c4bd0cb0cab -Author: Wolfgang Denk -Date: Mon Nov 19 12:59:14 2007 +0100 - - Fix build problems with mp2usb board - - Signed-off-by: Wolfgang Denk - -commit 6bf4c686afca1e86e1c384d59218f914605713bf -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Nov 18 18:36:11 2007 +0100 - - s3c24x0: Fix usb_ohci.c missing in Makefile - and usb_ohci.c warning differ in signedness - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 6073f61e078da5ddb521b56256bcc36508589883 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Nov 18 12:55:02 2007 +0100 - - pb1x00 board: Fix u16 status declaration when PCMCIA is defined - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 8412d814ce8bf5570a2b747f1e7fd321097fe987 -Author: Wolfgang Denk -Date: Sun Nov 18 17:11:09 2007 +0100 - - Fix compiler warnings for ARM systems. - - Signed-off-by: Wolfgang Denk - -commit 409ecdc0bb47dd28b0af6c25ffd658d22cc36b37 -Author: Wolfgang Denk -Date: Sun Nov 18 16:36:27 2007 +0100 - - Fix compiler warnings for PPC systems. Update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit 653811a3c2b35856bf12e196dcc8c4694e28e420 -Author: Stefan Roese -Date: Sun Nov 18 14:44:44 2007 +0100 - - ppc4xx: Correct 405EX PCIe UTL register mapping - - Map 4k mem space for UTL registers for each port. - - Signed-off-by: Stefan Roese - -commit 079c2c4fa71c0d1ebef394508df9088df8a308d3 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Nov 17 11:31:10 2007 +0100 - - Fix warning differ in signedness in net/net.c and net/nfs.c - -commit 7e14fc65368cbd2861b1207453da55a4fc7b3f81 -Author: Shinya Kuribayashi -Date: Sat Nov 17 20:42:45 2007 +0900 - - gth2.c: Fix a warning on gth2 build. - - gth2.c: In function 'misc_init_r': - gth2.c:434: warning: pointer targets in passing argument 2 of 'setenv' differ in signedness - - Signed-off-by: Shinya Kuribayashi - -commit 2309c130aa4c84b91bd874a41269c923eb61b555 -Author: Stefan Roese -Date: Sat Nov 17 07:58:25 2007 +0100 - - Fix warning differ in signedness in common/cmd_scsi.c - - Signed-off-by: Stefan Roese - -commit 9ea61b57968554eaf0f474ec7e088b17d367f474 -Author: Stefan Roese -Date: Sat Nov 17 14:52:29 2007 +0100 - - ppc4xx: Update AMCC Kilauea config file - - - Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE) - - Signed-off-by: Stefan Roese - -commit 7e1d884b7cb602007329c517ec1c453e3a6a5d9c -Author: Shinya Kuribayashi -Date: Sat Nov 17 20:05:26 2007 +0900 - - [MIPS] cpu/mips/config.mk: Fix GNU assembler minor version picker - - Current trick to pick up GNU assembler minor version does not work with the - latest binutils (2007-03-01 or later) due to ${PKGVERSION} now default to - "(GNU Binutils) ". - - $ sde-as --version |grep "GNU assembler" - GNU assembler 2.15.94 mipssde-6.02.02-20050602 - $ sde-as --version |grep "GNU assembler" |awk '{print $3}' - 2.15.94 - $ sde-as --version |grep "GNU assembler" |awk '{print $3}' |awk -F. '{print $2}' - 15 - $ - - $ mips-linux-as --version |grep "GNU assembler" - GNU assembler (GNU Binutils) 2.18 - $ mips-linux-as --version |grep "GNU assembler" |awk '{print $3}' - (GNU - $ mips-linux-as --version |grep "GNU assembler" |awk '{print $3}' |awk -F. '{print $2}' - (no output) - $ - - As a result of above, you'll see many noises with such binutils: - - make -C cpu/mips/ - /bin/sh: line 0: [: : integer expression expected - /bin/sh: line 0: [: : integer expression expected - make[1]: Entering directory `/home/skuribay/devel/u-boot.git/cpu/mips' - mips-linux-gcc -D__ASSEMBLY__ -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /home/skuribay/devel/buildroot/build_mips/staging_dir/usr/bin/../lib/gcc/mips-linux-uclibc/4.2.1/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4kc -EB -c -o incaip_wdt.o incaip_wdt.S - /bin/sh: line 0: [: : integer expression expected - mips-linux-gcc -D__ASSEMBLY__ -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /home/skuribay/devel/buildroot/build_mips/staging_dir/usr/bin/../lib/gcc/mips-linux-uclibc/4.2.1/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4kc -EB -c -o cache.o cache.S - /bin/sh: line 0: [: : integer expression expected - mips-linux-gcc -g -Os -D__KERNEL__ -DTEXT_BASE=0xB0000000 -I/home/skuribay/devel/u-boot.git/include -fno-builtin -ffreestanding -nostdinc -isystem /home/skuribay/devel/buildroot/build_mips/staging_dir/usr/bin/../lib/gcc/mips-linux-uclibc/4.2.1/include -pipe -DCONFIG_MIPS -D__MIPS__ -G 0 -mabicalls -fpic -pipe -msoft-float -march=4kc -mtune=4kc -EB -Wall -Wstrict-prototypes -c -o asc_serial.o asc_serial.c - /bin/sh: line 0: [: : integer expression expected - - This patch simplifies the trick and makes it work with both versions of gas. - I also replace an expensive `awk (or gawk)' with `cut'. - - Signed-off-by: Shinya Kuribayashi - -commit 16664f72850846e645616da1c0fa5afcd6d15f15 -Author: Shinya Kuribayashi -Date: Sat Nov 17 20:05:26 2007 +0900 - - [MIPS] Remove useless instructions for initializing $gp. - - Signed-off-by: Shinya Kuribayashi - -commit 03c031d5660ea946c39af6e2e16267da857c609f -Author: Shinya Kuribayashi -Date: Sat Oct 27 15:27:06 2007 +0900 - - [MIPS] MIPS 4K core: Coding style cleanups - - No logical changes. - - Signed-off-by: Shinya Kuribayashi - -commit f5e429d3860bba4c6ae8bead8f78349fa24491b2 -Author: Shinya Kuribayashi -Date: Sat Nov 17 20:05:20 2007 +0900 - - [MIPS] gth2.c: Fix a warning on gth2 build. - - gth2.c: In function 'misc_init_r': - gth2.c:434: warning: pointer targets in passing argument 2 of 'setenv' differ in signedness - - Signed-off-by: Shinya Kuribayashi - -commit 4fbd0741b2b6441da10be93e10267122581b7079 -Author: Shinya Kuribayashi -Date: Sat Oct 27 15:22:33 2007 +0900 - - [MIPS] au1x00_eth.c: Fixed a warning on pb1000 build. - - au1x00_eth.c: In function 'au1x00_miiphy_write': - au1x00_eth.c:139: warning: 'return' with no value, in function returning non-void - - Signed-off-by: Shinya Kuribayashi - -commit f01320459736f156707425cf8112f98606301aa4 -Author: Shinya Kuribayashi -Date: Sat Oct 27 15:00:25 2007 +0900 - - [MIPS] au1x00_eth.c: Fix au1x00_miiphy_{read,write} build error - - au1x00_eth.c: In function 'au1x00_enet_initialize': - au1x00_eth.c:246: error: 'au1x00_miiphy_read' undeclared (first use in this function) - au1x00_eth.c:246: error: (Each undeclared identifier is reported only once - au1x00_eth.c:246: error: for each function it appears in.) - au1x00_eth.c:246: error: 'au1x00_miiphy_write' undeclared (first use in this function) - au1x00_eth.c: In function 'au1x00_miiphy_write': - au1x00_eth.c:298: warning: 'return' with no value, in function returning non-void - make[1]: *** [au1x00_eth.o] Error 1 - - Fixed by moving these two functions forward. - - Signed-off-by: Shinya Kuribayashi - -commit b09258c5393edd1087c5f39ae68338f16b49f8b3 -Author: Shinya Kuribayashi -Date: Sat Oct 27 15:00:25 2007 +0900 - - MAKEALL: Added missing pb1000 board - - Signed-off-by: Shinya Kuribayashi - -commit 2e4a6e3667a1e39c0e6e99498686b15d2718b369 -Author: Shinya Kuribayashi -Date: Sat Oct 27 15:00:24 2007 +0900 - - [MIPS] pb1000: Replace obsolete memsetup.S with lowlevel_init.S - - Signed-off-by: Shinya Kuribayashi - -commit 662e5cb397249c3ea88a4c3255e9ccfc40b98d82 -Author: Shinya Kuribayashi -Date: Sat Oct 27 15:00:24 2007 +0900 - - [MIPS] u-boot.lds: Cleanup __u_boot_cmd_{start,end} - - Signed-off-by: Shinya Kuribayashi - -commit 5947f6999aafa7c54c1390983d264a8463dfea8e -Author: Wolfgang Denk -Date: Sat Nov 17 02:34:38 2007 +0100 - - Update CHANGELOIG, prepare for -rc4 - - Signed-off-by: Wolfgang Denk - -commit fd329e6f05bbdfe6bd71b0e09f0c76d3b0a025a5 -Author: Luotao Fu -Date: Wed Nov 14 18:58:33 2007 +0100 - - Fix the i2c frequency and default address in rsdproto board - - rsdproto board support has wrong I2C frequency and wrong return value - handling. - - Signed-off-by: Luotao Fu - -commit 429c180edad038f91c989cb14b478228092e7054 -Author: Wolfgang Denk -Date: Sat Nov 17 01:45:38 2007 +0100 - - powerpc: Backout relocation changes for MPC5121, too. - - Apply Grant Likely's backout to MPC5121 code, too. - - Pointed out by Rafal Jaworowski - - Signed-off-by: Wolfgang Denk - -commit 1c3dd43338a077165e7e0309cb3994e65d2bdbf8 -Author: Grant Likely -Date: Tue Nov 13 22:18:33 2007 -0700 - - powerpc: Backout relocation changes. - - Ugh. I *hate* to back this change out, but these compiler flags don't - work for relocation on all versions of GCC. I've not been able to - reproduce the environment in my setup (and hence, not been able to - find a combination that *does* work), so I've got no choice but to go - back to the old gcc flags and linker script. - - Signed-off-by: Grant Likely - -commit 5c15010efad980ad5498cc565fc1ed70df2f52b4 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Tue Nov 13 09:11:05 2007 +0100 - - Fixed mips_io_port_base build errors. - - This patch has been sent on: - - 29 Sep 2007 - - Although mips_io_port_base is currently a part of IDE command, it is quite - fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move - it to MIPS general part, and introduce `set_io_port_base()' from Linux. - - This patch is triggered by multiple definition of `mips_io_port_base' build - error on gth2 (and tb0229 also needs this fix.) - - board/gth2/libgth2.a(gth2.o): In function `log_serial_char': - /home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base' - common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here - make: *** [u-boot] Error 1 - - Signed-off-by: Shinya Kuribayashi - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 6ecbb7a3fa9b0940ed33e490d195d4b6830b2422 -Author: Wolfgang Denk -Date: Sat Nov 17 01:30:40 2007 +0100 - - Fix a bug in the slave serial programming mode for the Xilinx - Spartan2/3 FPGAs. The old code used "< 0" on a "char" type to test if - the most significant bit was set, which did not work on any - architecture where "char" defaulted to be an unsigned type. - - Based on a patch by Angelos Manousaridis - - Signed-off-by: Wolfgang Denk - -commit d08b7233bc252faad8339e7ca0ddfd62fa79903c -Author: Jon Loeliger -Date: Thu Nov 1 12:23:29 2007 -0500 - - 86xx: Fix broken variable reference when #def DEBUGing. - - Sometimes you can't reference the DDR2 controller variables. - - Signed-off-by: Jon Loeliger - -commit f9d9164d9c6b5a7f0393fd8d7e246b8a0326bc19 -Author: Jason Jin -Date: Fri Oct 26 18:32:00 2007 +0800 - - make 8610 board use pixis reset - - Signed-off-by: Jason Jin - -commit db74b3c1c9481a6bffbf8cd445e5bcbf6908e836 -Author: Jason Jin -Date: Mon Oct 29 19:26:21 2007 +0800 - - Unify pixis_reset altbank across board families - - Basically, refactor the CFG_PIXIS_VBOOT_MASK values - into the separate board config files. - - Signed-off-by: Jason Jin - Signed-off-by: Jon Loeliger - -commit 64bf555465c7926be13e1046ac0d0f05ac72829c -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Wed Nov 7 08:19:21 2007 +0100 - - Fix warning: pointer targets in assignment differ in signedness - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 7a60ee7c6248a958c5757d3660a1702723a2786d -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Wed Nov 7 08:19:19 2007 +0100 - - Fix warning differ in signedness in common/cmd_ide.c - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit f31d38b9eea9b32f6a1ac848a298cc71ca4c9a03 -Author: Stefan Roese -Date: Fri Nov 16 14:16:54 2007 +0100 - - ppc4xx: Enable 405EX PCIe UTL register configuration - - Till now the UTL registers on 405EX were not initialized but left with - their default values. This patch new initializes some of the UTL - registers on 405EX. - - Signed-off-by: Stefan Roese - -commit ecdcbd4f8c1f8cefd785752f4e7536aae2a4ecf9 -Author: Stefan Roese -Date: Fri Nov 16 14:00:59 2007 +0100 - - ppc4xx: Update AMCC Makalu for board rev 1.1 - - This patch adds changes needed for Makalu rev 1.1: - - - Enable 2nd DDR2 bank resulting in 256MByte of SDRAM - - Enable 2nd ethernet port EMAC1 - - Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE) - - Reset PCIe ports via GPIO upon bootup - - Signed-off-by: Stefan Roese - -commit 4d4faae65e115e327425cd514c1a35146a85166b -Author: Grant Likely -Date: Mon Sep 24 09:05:31 2007 -0600 - - Group PCI and PCMCIA drivers in drivers/Makefile - - Signed-off-by: Grant Likely - -commit 5798f87dc10a496d79d3177b9f5a76488987fd35 -Author: Grant Likely -Date: Mon Sep 24 09:05:31 2007 -0600 - - Group block/flash drivers in drivers/Makefile - - Signed-off-by: Grant Likely - -commit df58c81551700f058b44cacf55a7997fa63bfe0a -Author: Grant Likely -Date: Mon Sep 24 09:05:31 2007 -0600 - - Group USB drivers in drivers/Makefile - - Signed-off-by: Grant Likely - -commit 5dbb6ed622e539b0c8493ef7e578d3a533181d29 -Author: Grant Likely -Date: Mon Sep 24 09:05:30 2007 -0600 - - Group i2c drivers in drivers/Makefile - - Signed-off-by: Grant Likely - -commit ec00c76de0e5971273905998d62d6bb119324218 -Author: Grant Likely -Date: Mon Sep 24 09:05:30 2007 -0600 - - Group console drivers in drivers/Makefile - - Signed-off-by: Grant Likely - -commit 754f230aa01b8c789fc31f8013c2487954073300 -Author: Grant Likely -Date: Mon Sep 24 09:05:30 2007 -0600 - - Group network drivers in drivers/Makefile - - Signed-off-by: Grant Likely - -commit f0037c56b0d12cd46215124667b9f83d60ef9391 -Author: Grant Likely -Date: Mon Sep 24 09:05:30 2007 -0600 - - Build: split COBJS value into multiple lines - - This change is in preparation for condtitionial compile support in the - build system. By spliting them all into seperate lines now, subsequent - patches that change 'COBJS-y += ' into 'COBJS-$(CONFIG_) += ' will - be less invasive and easier to review - - Signed-off-by: Grant Likely - -commit 1b4aaffe4fb2a5e95d9111a5d94fd1f89215dce4 -Author: Grant Likely -Date: Mon Sep 24 09:05:30 2007 -0600 - - Add .gitignore files - - Signed-off-by: Grant Likely - Acked-by: Kim Phillips - -commit 955413f35f054a82e40042f1dbcf501c6a05719b -Author: Grant Likely -Date: Thu Nov 15 08:27:52 2007 -0700 - - Revert "Correct relocation fixup for mpc5xx" - - This reverts commit 3649cd99ba815b6601868735765602f00ef3692b. - Signed-off-by: Grant Likely - -commit e15633888a058aacb31a62d2cf1278e1e4c236ab -Author: Grant Likely -Date: Thu Nov 15 08:24:32 2007 -0700 - - Revert "Correct fixup relocation for MPC5xxx" - - This reverts commit 6f7576b20ecf0d040c3ac3b032b5cbc860e38a90. - Signed-off-by: Grant Likely - -commit 139365fbe566d0fc619a1ed04452ec5388f0cef8 -Author: Grant Likely -Date: Thu Nov 15 08:21:04 2007 -0700 - - Revert "Correct fixup relocation for mpc8220" - - This reverts commit a85dd254c0577fca13627c46e93fc2ad4c4f1f00. - Signed-off-by: Grant Likely - -commit 70922342369e5e39b286fe21e768a239ca07a514 -Author: Grant Likely -Date: Thu Nov 15 08:20:57 2007 -0700 - - Revert "Correct fixup relocation for mpc824x" - - This reverts commit f3a52fe05923935db86985daf9438e2f70ac39aa. - Signed-off-by: Grant Likely - -commit 96279ab4cad60cb5972aa934fbe4845ac02cc75a -Author: Grant Likely -Date: Thu Nov 15 08:20:50 2007 -0700 - - Revert "Correct fixup relocation for mpc8260" - - This reverts commit 5af61b2f4b838a05f79be274f3e5a66edd2d9c96. - Signed-off-by: Grant Likely - -commit 928fe33b24cdf382a8dc8687fed24b1961cdb5d6 -Author: Grant Likely -Date: Thu Nov 15 08:20:43 2007 -0700 - - Revert "Correct fixup relocation for mpc83xx" - - This reverts commit 057004f4a4863554d56cc56268bfa7c7d9738e27. - Signed-off-by: Grant Likely - -commit c93945e8f9e300860d2bf73a2549ce5794f8bd00 -Author: Grant Likely -Date: Thu Nov 15 08:20:25 2007 -0700 - - Revert "[MPC512x] Correct fixup relocation" - - This reverts commit 8d17979d0359492a822a0a409d26e3a3549b4cd4. - Signed-off-by: Grant Likely - -commit c9672f81f1bdb4e8ddf62aa72ca0206e8b72aa1c -Author: Stefan Roese -Date: Thu Nov 15 14:25:09 2007 +0100 - - ppc4xx: Small AMCC Kilauea cleanup - - Remove not needed pci_target_init() function. - - Signed-off-by: Stefan Roese - -commit aee747f19b460a0e9da20ff21e90fdaac1cec359 -Author: Stefan Roese -Date: Thu Nov 15 14:23:55 2007 +0100 - - ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platforms - - - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - - Cleanup of the 4xx GPIO functions - - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h - - Signed-off-by: Stefan Roese - -commit 8ada0ebf38e4073beea0309188b25d82a112a2ae -Author: Stefan Roese -Date: Thu Nov 15 14:20:08 2007 +0100 - - ppc4xx: AMCC Taihu board config file cleanup - - This patch makes the AMCC Taihu a little more compatible to the other - AMCC eval boards. - - Signed-off-by: Stefan Roese - -commit 5e71c51d74c963d3174060c078dcacf13bdd02ef -Author: Marian Balakowicz -Date: Thu Nov 15 13:37:28 2007 +0100 - - [INKA4x0] NG hardware: flash support - - Disabled and remove inka4x0 custom flash driver, use CFI flash - driver instead. - - Signed-off-by: Marian Balakowicz - -commit 5fb6d7191e206cdde0e23140fd8111caed93a595 -Author: Marian Balakowicz -Date: Thu Nov 15 13:29:55 2007 +0100 - - [INKA4x0] NG hardware: SDRAM support - - Add support for three new DDR chips that may be present on a NG - INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT. - - Cleanup board/inka4x0/mt48lc16m16a2-75.h file. - - Signed-off-by: Marian Balakowicz - -commit f23cb34c367bb27585a4fdb8a75277370e7d0596 -Author: Marian Balakowicz -Date: Thu Nov 15 13:24:43 2007 +0100 - - [INKA4x0] NG hardware: platform code update - - - Cleanup compile warnings. - - Add missing '\0' in default environment. - - Increase CFG_MONITOR_LEN to 256 KiB. - - Add required CFG_USE_PPCENV. - - Signed-off-by: Marian Balakowicz - -commit 2ae64f5135e51bb18753884d1265b99e89b5aedd -Author: Peter Pearse -Date: Thu Nov 15 08:58:00 2007 +0000 - - Remove warnings re CONFIG_EXTRA_ENV_SETTINGS - Remove warnings re onenand_read() & write() - -commit 2db916e14410e3ec1738508c7bf4dfeb2b299ae7 -Author: Peter Pearse -Date: Thu Nov 15 08:45:13 2007 +0000 - - Correction patch - -commit 1d8a49eca1c7bdc8db1c47a92f9014a29ead03ae -Author: Roy Zang -Date: Thu Sep 13 18:52:28 2007 +0800 - - Enable ULi1575 Ethernet support in 8610HPCD config - - Signed-off-by: Roy Zang - Acked-by: Jon Loeliger - -commit 54fd6c93c28a0a45352fff5dd92673401ff563f2 -Author: Stefan Roese -Date: Tue Nov 13 08:18:20 2007 +0100 - - ppc4xx: lwmon5: Change PHY reset sequence for PHY MDIO address latching - - Signed-off-by: Stefan Roese - -commit 7d0a4066b5a6b698e5fc1b66cfe9705774bbce93 -Author: Stefan Roese -Date: Tue Nov 13 08:06:11 2007 +0100 - - ppc4xx: Fix 405EX PCIe UTLSET register setup - - Signed-off-by: Stefan Roese - -commit 1ce55151c85d068f70317a8d65c61058b891afb4 -Author: Heiko Schocher -Date: Tue Nov 13 07:50:29 2007 +0100 - - [UC101] SRAM now with 2 MB working. - - Signed-off-by: Heiko Schocher - -commit 2d14684341109a69616e4d6016cd61402d55086f -Author: Matthias Fuchs -Date: Fri Nov 9 15:37:53 2007 +0100 - - ppc4xx: Use generic usb-ohci driver for sequoia board - - This patch makes the sequoia board use the generic usb-ohci driver - instead of cpu/ppc4xx/usb_ohci.c. - - Signed-off-by: Matthias Fuchs - Signed-off-by: Stefan Roese - -commit 9be659ac0868dc367caa957c5c725e46b07f6a5f -Author: Matthias Fuchs -Date: Fri Nov 9 15:37:23 2007 +0100 - - ppc4xx: Make USB working with CONFIG_4xx_DCACHE defined - - This patch disables the 44x d-cache on 'usb start' and - reenables it on 'usb stop'. This should be seen as a - temporary fix until the generic usb-ohci driver can - life with d-cache enabled. - - Signed-off-by: Matthias Fuchs - Signed-off-by: Stefan Roese - -commit fbde2169d2c48fcc9ff03489534a78ffb0a8a0d4 -Author: Matthias Fuchs -Date: Fri Nov 9 15:36:44 2007 +0100 - - ppc4xx: Remove redundant code from 4xx network driver - - This patch removes some redundant code and decrements the end - address of cache flush and invalidate by 1. - - Signed-off-by: Matthias Fuchs - Signed-off-by: Stefan Roese - -commit 5ca9881aad8c413ac2a82868a5e3719178254502 -Author: Peter Pearse -Date: Fri Nov 9 15:24:26 2007 +0000 - - Add apollon board support - Signed-off-by: Kyungmin Park - -commit b53313dbfc74525d85f1e7e0102f902d5c863beb -Author: Stefan Roese -Date: Fri Nov 9 12:19:58 2007 +0100 - - ppc4xx: Remove In:/Out:/Err: boot output for AMCC Kilauea - - Signed-off-by: Stefan Roese - -commit c7f69c340277935a6c19a956421852da944a365f -Author: Stefan Roese -Date: Fri Nov 9 12:18:54 2007 +0100 - - ppc4xx: Make output a little shorter on I2C bootrom detection - - Most 4xx PPC capable of using an I2C bootrom for bootstrap setting - already print a line with the information which I2C bootrom is - used for bootstrap configuration. So we don't need this extra line - with "I2C boot EEPROM en-/dis-abled". - - This patch also has a little code cleanup integrated. - - Signed-off-by: Stefan Roese - -commit 8d737a28152ec12873f8544cca1fb39a49e5e693 -Author: TsiChungLiew -Date: Thu Nov 8 12:50:18 2007 -0600 - - ColdFire: MCF5329 - Remove reset registers from CCM - - Signed-off-by: TsiChungLiew - -commit 7d7cdea769a60b0a6e4c18bef7f9d648fd14b8d7 -Author: TsiChungLiew -Date: Thu Nov 8 12:31:11 2007 -0600 - - ColdFire: MCF5329 - Add Reset structure to immap_5329.h - - Signed-off-by: TsiChungLiew - -commit 09b26cf00d76d75fdf7fdc4b13e4dd929743bc21 -Author: TsiChungLiew -Date: Thu Nov 8 12:19:01 2007 -0600 - - ColdFire: MCF5329 - revert include/asm-m68k/m5329.h file mode - - Signed-off-by: TsiChungLiew - -commit 225a24b5e062ad94627424508ae814f51dbe1a34 -Author: TsiChungLiew -Date: Wed Nov 7 18:00:54 2007 -0600 - - ColdFire: MCF5445x - Update correct RAMBAR and missing linker files - - Signed-off-by: TsiChungLiew - -commit 248c7c14835f34d5d910b45e5600050e58ca6cab -Author: TsiChungLiew -Date: Wed Nov 7 17:56:15 2007 -0600 - - ColdFire: MCF532x - Update do_reset() using core reset - - Signed-off-by: TsiChungLiew - -commit d9240a5f827eb3b476a6ba2938d01f1a9e7688f4 -Author: TsiChungLiew -Date: Wed Nov 7 17:51:00 2007 -0600 - - ColdFire: Update cpu flag for 4.2-xx compiler - - Signed-off-by: TsiChungLiew - -commit 070ba56115b4da63b46e974287fa4550d4023386 -Author: York Sun -Date: Wed Oct 31 14:59:04 2007 -0500 - - 8610: Add console frame buffer support to FSL 8610 DIU driver. - - Add cfb console support to FSL 8610 DIU driver. - Inspect board version from PIXIS to obtain correct pixel format. - - Use #define CONFIG_VIDEO in config file to enable fb console. - - To switch monitor, set monitor variable to - 0 - DVI, 1 - Single link LVDS, 2 - Double link LVDS - followed by "diufb init". - - Preserve logo bitmap at the top of the fb console. - - Signed-off-by: York Sun - Signed-off-by: Jon Loeliger - -commit a877880c6949e948bd63cd6ea4e216573d2f53dd -Author: York Sun -Date: Mon Oct 29 13:58:39 2007 -0500 - - 8610: Add 8610 DIU display driver - - 1280x1024 and 1024x768 @ 32 bpp are supported now. - DVI, Single-link LVDS, Double-link LVDS are all supported. - - Environmental variable "monitor" is used to specify monitor port. - - A new command "diufb" is introduced to reinitialize monitor - and display a BMP file in the memory. So far, 1-bit, 4-bit, - 8-bit and 24-bit BMP formats are supported. - - diufb init - - initialize the diu driver - Enable the port specified in the environmental variable "monitor" - - diufb addr - - display bmp file in memory. - The bmp image should be no bigger than the resolution, 1280x1024 - for DVI and double-link LVDS, 1024x768 for single-link LVDS. - - Note, this driver allocate memory but doesn't free it after use - It is written on purpose -- to avoid a failure of reallocation - due to memory fragement. - - ECC of DDR is disabled for DIU performance. L2 data cache is also disabled. - - Signed-off-by: York Sun - Signed-off-by: Jon loeliger - -commit 52e5ddfecdda308f75782fae206b677b1810f5f9 -Author: York Sun -Date: Wed Oct 31 10:43:59 2007 -0500 - - FSL: Add a freescale bitmap logo. - - This Freescale logo is a 340 x 128 x 4bpp BMP file - that can be displayed by the DIU Framebuffer driver. - - Signed-off-by: York Sun - Signed-off-by: Jon Loeliger - -commit 1815338fbd1c0f94f8276d2891b99caa5a05f622 -Author: York Sun -Date: Mon Oct 29 13:57:53 2007 -0500 - - 8610: Make some extra debug environment variables conditional. - - One may #define ENV_DEBUG to get them back again. - - Signed-off-by: York Sun - -commit 761421ccca80a9fb37b19c37aa61d46ef75e0647 -Author: Jason Jin -Date: Mon Oct 29 19:26:21 2007 +0800 - - 8610: Actually enable pixis_reset CONFIGs - - Signed-off-by: Jason Jin - -commit f3bceaab230b4748d0afc4109b6837308f018b40 -Author: Jason Jin -Date: Fri Oct 26 18:31:59 2007 +0800 - - Fix the BAT definition of PCI IO on 8610 board - - The address in the BAT register is aligned with the BAT size. - The original definition actually did not define BAT for PCIE2 IO. - This patch fix this. - - Signed-off-by: Jason Jin - -commit 9f23ca334a6f5f021ef9e9d0fad9da80d63b2d56 -Author: Jason Jin -Date: Mon Oct 29 19:26:21 2007 +0800 - - Unify pixis_reset altbank across board families - - Basically, refactor the CFG_PIXIS_VBOOT_MASK values - into the separate board config files. - - Signed-off-by: Jason Jin - Signed-off-by: Jon Loeliger - -commit a8318ec205c8e8794b5f9f1b8584abadb440e8ba -Author: Jason Jin -Date: Fri Oct 26 18:32:00 2007 +0800 - - make 8610 board use pixis reset - - Signed-off-by: Jason Jin - -commit 9c84709eedce9c680dd695984ab7d2328f4f04f5 -Author: Jon Loeliger -Date: Thu Nov 1 12:23:29 2007 -0500 - - 86xx: Fix broken variable reference when #def DEBUGing. - - Sometimes you can't reference the DDR2 controller variables. - - Signed-off-by: Jon Loeliger - -commit 1f103105a3746ab12279b63b8c1d372c0ce2cc58 -Author: Roy Zang -Date: Mon Nov 5 17:39:24 2007 +0800 - - Implement general ULi 526x Ethernet driver support in U-boot - - This patch implements general ULi 526x Ethernet driver. - Until now, it is the only native Ethernet port on - MPC8610HPCD board, but it could be used on other boards - with ULi 526x Ethernet port as well. - - Signed-off-by: Roy Zang - Signed-off-by: Zhang Wei - Acked-by: Jon Loeliger - Signed-off-by: Ben Warren - -commit 71bc6e6474fea8ef481b9b45d1edd7ad1f6dfbbd -Author: Larry Johnson -Date: Thu Nov 1 08:46:50 2007 -0500 - - NET: Add Ethernet 1000BASE-X support for PPC4xx - - This patch adds support for 1000BASE-X to functions "miiphy_speed ()" and - "miiphy_duplex()". It also adds function "miiphy_is_1000base_x ()", which - returns non-zero iff the PHY registers are configured for 1000BASE-X. The - "mii info" command is modified to distinguish between 1000BASE-T and -X. - - Signed-off-by: Larry Johnson - Signed-off-by: Ben Warren - -commit 298035df4948b113d29ac0e694717d34b95bc5dc -Author: Larry Johnson -Date: Wed Oct 31 11:21:29 2007 -0500 - - NET: Cosmetic changes - - Signed-off-by: Larry Johnson - Signed-off-by: Ben Warren - -commit 654f38b3a387886996a5a75771fbfc29cb4f225e -Author: Stefan Roese -Date: Mon Nov 5 07:43:05 2007 +0100 - - ppc4xx: Make output a little shorter on PCIe detection - - Now not max 3 lines but 2 lines are printed per PCIe port. - - Signed-off-by: Stefan Roese - -commit 992742a5b09d9040adbd156fb90756af66ade310 -Author: Wolfgang Denk -Date: Sat Nov 3 23:09:27 2007 +0100 - - Cleanup coding style; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit e881cb563e32f45832b7b6db77bdcd017adcbb41 -Author: Bruce Adler -Date: Fri Nov 2 13:15:42 2007 -0700 - - fix wording in README - - Changed the wording to properly describe the shadowing - of the environment from ROM to RAM - - Signed-off-by: Bruce Adler - -commit ad845beef06245426c57b53dcdc01b7dc70e0d45 -Author: Shinya Kuribayashi -Date: Wed Oct 31 02:18:15 2007 +0900 - - blackfin: Move `-D__BLACKFIN__' to $(ARCH)_config.mk - - Signed-off-by: Shinya Kuribayashi - -commit ec22755799466c8a103664bb3a5e647bf9c238f4 -Author: Vlad Lungu -Date: Thu Oct 25 16:08:14 2007 +0300 - - Trimmed some variables in ne2000.c - - Signed-off-by: Vlad Lungu - -commit eb6f214d3644b2a77968c176ed36dcf858cfe7e0 -Author: Zhang Wei -Date: Thu Oct 25 17:51:27 2007 +0800 - - Fix the issue of usb_kbd driver missing the scan code of key 'z'. - - The scan code of the key 'z' is 0x1d, which should be handled. - - The change has be tested on NOVATEK USB keyboard and ULI PCI OHCI - controller. - - Signed-off-by: Zhang Wei - -commit bbf4796f6498fbade56d56eff3a0a49b299d93e5 -Author: Zhang Wei -Date: Thu Oct 25 17:30:04 2007 +0800 - - Fix USB support issue for MPC8641HPCN board. - - The configuration file has already enabled USB, but it - missed definition of CFG_OHCI_SWAP_REG_ACCESS, the USB - on MPC8641HPCN can not work because of the wrong USB - register endian. - - And add the USB command to U-Boot commands list. - - Signed-off-by: Zhang Wei - -commit 4e62041023dc3de9d98d977bb080235bc6d035e0 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Wed Oct 24 18:16:01 2007 +0200 - - Use config_cmd_default.h instead of config_cmd_all.h - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 56622f87857439b1c221e9deef11a9d5bb5d4308 -Author: Marian Balakowicz -Date: Wed Oct 24 01:37:36 2007 +0200 - - TQM5200: Call usb_cpu_init() during board init - - usb_cpu_init() configures GPS USB pins, clocks, etc. and - is required for proper operation of kernel USB subsystem. - This setup was previously done in the kernel by the fixup - code which is being removed, thus low level init must be - done by U-boot now. - - Signed-off-by: Marian Balakowicz - -commit 29c29c0267fe857e72014ce90c5d35b2ef6302bd -Author: Guennadi Liakhovetski -Date: Tue Oct 23 16:25:50 2007 +0200 - - Fix typo in nfs.c - - An obvious typo. Originally fixed in linkstation u-boot port. - - Signed-off-by: Guennadi Liakhovetski - -commit 59543fe00a4ce720ef9f5aa7fb387c6daf1c7d78 -Author: Guennadi Liakhovetski -Date: Tue Oct 23 14:35:05 2007 +0200 - - Fix a typo in cpu/mpc824x/interrupts.c - - Since December 2003 the timer_interrupt_cpu() function in - cpu/mpc824x/interrupts.c contains what seems to be a superfluous - parameter. Remove it. - - Signed-off-by: Guennadi Liakhovetski - -commit c9e7b9b9a1700fe009678d1f9b41e6364ac5df2d -Author: Sergej Stepanov -Date: Wed Oct 17 11:13:51 2007 +0200 - - add ft_cpu_setup(..) on mpc8260 - - Add ft_cpu_setup(..)-function to adapt it for use with libfdt - based on code from mpc5xxx - - Sigend-off-by: Sergej Stepanov - -- - -commit 6abd82e19ae93c0b4d104e50165e235915ec0875 -Author: Sergej Stepanov -Date: Wed Oct 17 11:18:42 2007 +0200 - - changes for IDS8247 board support - - To get the IDS8247 board working following are done: - - FCC2 is deactivated - - FCC1 is activated - - I2C is activated - - CFI driver is activated - - Adapted for use with LIBFDT - - Signed-off-by: Sergej Stepanov - -- - -commit 3d6cb3b24add6415f86a0f013ea40f5639b90047 -Author: Stefan Roese -Date: Sat Nov 3 12:08:28 2007 +0100 - - ppc4xx: Add AMCC Kilauea/Haleakala NAND booting support - - This patch adds NAND booting support for the AMCC 405EX(r) eval boards. - Again, only one image supports both targets. - - Signed-off-by: Stefan Roese - -commit 8b6684a698500be9c142ec2c9f46cfc348e17f0c -Author: Haavard Skinnemoen -Date: Wed Oct 24 15:48:37 2007 +0200 - - ATSTK1002: Remove default ethernet addresses - - Wolfgang is right: It's not a good idea to set up default initial - ethernet addresses for a board, even though they belong to the local - range. - - This will change the failure mode from "IT manager screams at you for - using duplicate ethernet addresses" to a nice error message explaining - that the ethernet address hasn't been set properly. - - Signed-off-by: Haavard Skinnemoen - -commit e5c794e491a57d829b6d8733e2ed8368a2269abf -Author: Justin Flammia -Date: Mon Oct 29 17:40:35 2007 -0400 - - DHCP Client Fix - - This is a multi-part message in MIME format. - - commit e6e505eae94ed721e123e177489291fc4544b7b8 - Author: Justin Flammia - Date: Mon Oct 29 17:19:03 2007 -0400 - - Found a bug in the way the DHCP Request packet is built, where the IP address - that is offered by the server is bound to prematurely. This patch is a fix of - that bug where the IP address offered by the DHCP server is not used until - after the DHCP ACK from the server is received. - - Signed-off-by: Justin Flammia - Signed-off-by: Ben Warren - -commit 5d96d40d3f36da33348e68f9ea993f383e11f997 -Author: Stefan Roese -Date: Wed Oct 31 20:58:34 2007 +0100 - - ppc4xx: Fix acadia_nand build problem - - Since the cache handling functions were moved from start.S into cache.S - the acadia NAND booting Makfile needs to be adapted accordingly. - - Signed-off-by: Stefan Roese - -commit ea2e142843533ca593fcb5cb3e1daf1b7f5e5949 -Author: Stefan Roese -Date: Wed Oct 31 20:57:11 2007 +0100 - - ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM - - This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files - and to the Sequoia TLB init code. Now the cache can be enabled on 44x - boards by defining CONFIG_4xx_DCACHE in the board config file. This - option will disappear, when more boards use is successfully and no - more known problems exist. - - This is tested successfully on Sequoia and Katmai. The only problem that - needs to be fixed is, that USB is not working on Sequoia right now, since - it will need some cache handling code too, similar to the 4xx EMAC driver. - - Signed-off-by: Stefan Roese - -commit 3db93b8bedd32e914b38976141b3fdf4ea3ff738 -Author: Stefan Roese -Date: Wed Oct 31 20:51:10 2007 +0100 - - ppc4xx: Enable CPU POST test for 4xx with dcache enabled - - Now with caches enabled (i- and d-cache) on 44x, we need a chance to - disable the cache for the CPU POST tests, since these tests consist - of self modifying code. This is done via the new change_tlb() function. - - Signed-off-by: Stefan Roese - -commit f71b2888b4b3c870909a0341427b2a914246f81f -Author: Stefan Roese -Date: Wed Oct 31 20:47:26 2007 +0100 - - ppc4xx: Change 4xx POST ethernet test to handle cached memory too - - This patch enables the 4xx EMAC POST driver to work too, when dcache is - enabled. - - Signed-off-by: Stefan Roese - -commit a2685904061b35a17583d65fe47cdc2686a69eaa -Author: Stefan Roese -Date: Wed Oct 31 20:45:53 2007 +0100 - - ppc4xx: Remove temporary TLB entry in POST cache test only for 440 - - Signed-off-by: Stefan Roese - -commit ff768cb168d8157c24a25016dbfbeb465e47f420 -Author: Stefan Roese -Date: Wed Oct 31 18:01:24 2007 +0100 - - ppc4xx: Change 4xx ethernet driver to handle cached memory too - - This patch enables the 4xx EMAC driver to work too, when dcache is - enabled. - - Signed-off-by: Stefan Roese - -commit 483e09a223c666269ef81d3573a6591b1046b0ef -Author: Stefan Roese -Date: Wed Oct 31 17:59:22 2007 +0100 - - ppc4xx: Add change_tlb function to modify I attribute of TLB(s) - - This function is used to either turn cache on or off in a specific - memory area. - - Signed-off-by: Stefan Roese - -commit d25dfe08fbd1220cb994e7e6b105049aa9aa8e79 -Author: Stefan Roese -Date: Wed Oct 31 17:57:52 2007 +0100 - - ppc4xx: Remove cache definition from 4xx board config files - - All 4xx board config files don't need the cache definitions anymore. - These are now defined in common headers. - - Signed-off-by: Stefan Roese - -commit 9b94ac61d2176185c30adf0793e079ec30e68687 -Author: Stefan Roese -Date: Wed Oct 31 17:55:58 2007 +0100 - - ppc4xx: Rework 4xx cache support - - New cache handling functions added and all existing functions - moved from start.S into seperate cache.S. - - Signed-off-by: Stefan Roese - -commit 06713773da4ac3d390c63d82641eb553224b27c2 -Author: Stefan Roese -Date: Tue Oct 23 18:03:12 2007 +0200 - - ppc4xx: Remove compiler warning from previous commit - - Signed-off-by: Stefan Roese - -commit 6fa397df67c0f269e4528bf181a6e8c88f9723f9 -Author: Stefan Roese -Date: Tue Oct 23 14:40:30 2007 +0200 - - ppc4xx: Remove temporary TLB entry in POST cache test - - Signed-off-by: Stefan Roese - -commit 1338e6a81834099ba19733b69aafd8ef5f098094 -Author: Stefan Roese -Date: Tue Oct 23 14:05:08 2007 +0200 - - ppc4xx: Change autonegotiation timeout from 4 to 5 seconds - - I lately noticed, that newer 4xx board with GBit support sometimes don't - finish link autonegotiation in 4 seconds. Changing this timeout to 5 - seconds seems fine here. - - Signed-off-by: Stefan Roese - -commit 2d83476a4c1c9911d158a3f8a4312d354bc1bdb7 -Author: Stefan Roese -Date: Tue Oct 23 14:03:17 2007 +0200 - - ppc4xx: Change 4xx_enet & miiphy to use out_be32() and friends - - This patch changes all in32/out32 calls to use the recommended in_be32/ - out_be32 macros instead. - - Signed-off-by: Stefan Roese - -commit 7d47cee2cc57f907380f2c06f5b6c683d03e423a -Author: Stefan Roese -Date: Thu Oct 25 12:24:59 2007 +0200 - - ppc4xx: Fix POST ethernet test for Haleakala - - The POST ethernet test needed to be changed to dynamically determine - the count of ethernet devices. This code is cloned from the 4xx - ethernet driver. - - Signed-off-by: Stefan Roese - -commit f10493c6d77a1e07a6c2ff4d772937a5e7359d6a -Author: Stefan Roese -Date: Tue Oct 23 11:31:05 2007 +0200 - - ppc4xx: Correct UART input clock calculation and passing to fdt - - We now use a value in the gd (global data) structure for the UART input - frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely - in get_sys_info(). - - Signed-off-by: Stefan Roese - -commit 353f2688b4e0fc7b969bc70a02be4b40bf0dd124 -Author: Stefan Roese -Date: Tue Oct 23 10:10:08 2007 +0200 - - ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board support - - The Haleakala is nearly identical with the Kilauea eval board. The only - difference is that the 405EXr only supports one EMAC and one PCIe - interface. This patch adds support for the Haleakala board by using - the identical image for Kilauea and Haleakala. The distinction is done - by comparing the PVR. - - Signed-off-by: Stefan Roese - -commit 9f798766aa85e62eb8fa8c721e148df609b78137 -Author: Eugene O'Brien -Date: Tue Oct 23 08:29:10 2007 +0200 - - ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAM - - This patch also adds a note to the fixed DDR setup for Bamboo NAND booting: - - Note: - As found out by Eugene O'Brien , the fixed - DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM - modules are still plugged in. So it is recommended to remove the DIMM - modules while using the NAND booting code with the fixed SDRAM setup! - - Signed-off-by: Eugene O'Brien - Signed-off-by: Stefan Roese - -commit afe9fa59cb63b4f9d16bf01c93eb212f25a38c2a -Author: Stefan Roese -Date: Mon Oct 22 16:24:44 2007 +0200 - - ppc4xx: Add SNTP support to AMCC Katmai, Kilauea & Makalu boards - - Signed-off-by: Stefan Roese - -commit 3248f63ad89cb031491edb7016587fe6e9a238b9 -Author: Stefan Roese -Date: Mon Oct 22 16:22:40 2007 +0200 - - ppc4xx: Rework of 4xx serial driver (4) - - Change 4xx_uart.c: - - - Use in_8/out_8 macros instead of in8/out8 - - No need for UART_BASE marco anymore, now really handled via function - parameter - - serial_init_common() introduced - - Further coding style cleanup - - Signed-off-by: Stefan Roese - -commit e61cb8163a66b8a135696ae232e2bead1ce0a049 -Author: Stefan Roese -Date: Mon Oct 22 15:45:49 2007 +0200 - - ppc4xx: Rework of 4xx serial driver (3) - - Change all linker scripts to reference the changed driver name iop480_uart.o. - - Signed-off-by: Stefan Roese - -commit 882ae41274921f9016131806bdeb27e19606f47a -Author: Stefan Roese -Date: Mon Oct 22 15:44:39 2007 +0200 - - ppc4xx: Rework of 4xx serial driver (2) - - Change all linker scripts to reference the changed driver name 4xx_uart.o. - - Note: In most cased all these explicit referencing of these object files - in the linker scripts is not neccessary. Only for manually embedded - environment into the U-Boot image, which is not done is most cases. - - Signed-off-by: Stefan Roese - -commit ad31e40bed042cb670d0036fea96435007afb838 -Author: Stefan Roese -Date: Mon Oct 22 15:09:59 2007 +0200 - - ppc4xx: Rework of 4xx serial driver (1) - - This patch starts the rework of the PPC4xx serial driver. First we split - the file into two seperate files, one 4xx_uart.c with the 405/440 UART - handling code and the other one iop480_uart.c with the UART code for the - PLX-Tech IOP480 PPC (PPC403 based). - - Signed-off-by: Stefan Roese - -commit 764e7417ee5f6e25b1715720e7d7dd3487109385 -Author: Stefan Roese -Date: Mon Oct 22 10:30:38 2007 +0200 - - ppc4xx: Correct UART input clock calculation and passing to fdt - - Signed-off-by: Stefan Roese - -commit 211ea91ac6c225bec7e668a03d0ba7d7310679fa -Author: Stefan Roese -Date: Mon Oct 22 07:34:34 2007 +0200 - - ppc4xx: Add initial AMCC Makalu 405EX support - - Signed-off-by: Stefan Roese - -commit fa8aea20456e6f1dba43f46bcc72024dd9499998 -Author: Stefan Roese -Date: Mon Oct 22 07:33:52 2007 +0200 - - ppc4xx: Add freqUART to CPU speed detection - - This value is needed later for the device tree configuration of - the uart clock. - - Signed-off-by: Stefan Roese - -commit 837c730b4d7c6b1ddf3d1e247cb4445005d9bf0d -Author: Stefan Roese -Date: Sun Oct 21 14:26:29 2007 +0200 - - ppc: Small Kilauea cleanup of config file - - Signed-off-by: Stefan Roese - -commit 758c037aeead34b49631b8da3a90b1bba14c0410 -Author: Stefan Roese -Date: Sun Oct 21 08:16:12 2007 +0200 - - rtc: Add Xicor/Intersil X1205 RTC support - - This patch adds support for the Xicor/Intersil X1205 RTC used on the - AMCC Makalu eval board. This driver is basically cloned from the Linux - driver version (2.6.23). - - This patch also introduces the Linux bcd.h header for the BCD2BIN/ - BIN2BCD conversions. In the future some of the other U-Boot RTC driver - should be converted to also use this header instead of implementing - their own local copy of these functions/macros. - - Signed-off-by: Stefan Roese - -commit 087dfdb79b5fd1ab99a26990c62a732c01a8c7f6 -Author: Stefan Roese -Date: Sun Oct 21 08:12:41 2007 +0200 - - ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx - - This patch moves some common 4xx macros and the PPC405_SYS_INFO/ - PPC440_SYS_INFO structure into the common ppc4xx.h header. - - Lot's of other macros are good candidates to be consolidated this way - in the future. - - Signed-off-by: Stefan Roese - -commit 770c7af5800f598d22730d1f4b70f16c9b33512e -Author: Stefan Roese -Date: Sun Oct 21 08:05:18 2007 +0200 - - ppc4xx: Fix size setup in Kilauea DDR2 init routine - - The size was initilized wrong. Instead of 256MB, the DDR2 controller - was setup to 512MB. Now the correct values is used. - - This patch also does a little cleanup and adds a comment here. - - Signed-off-by: Stefan Roese - -commit f6ba9b56607d4b27550301c7c7f6b55b654fd62a -Author: Eugene O'Brien -Date: Thu Oct 18 17:29:04 2007 +0200 - - ppc4xx: Define CONFIG_BOOKE for all PPC440 based processors - - CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR - number is used to access system registers. - - Signed-off-by: Eugene O'Brien - Signed-off-by: Stefan Roese - -commit c36c68160333ac5fe41ec3db12a728b7075b3912 -Author: Stefan Roese -Date: Thu Oct 18 07:42:27 2007 +0200 - - ppc4xx: Change inbound PCIe location for endpoint tests on Katmai - - On Yucca & Katmai, the inbound memory map pointed to 0x4.0000.0000, which - is the internal SRAM. Since I now ported and tested this endpoint mode - on Kilauea successfully to map to 0 (SDRAM), I also changed this for - Katmai. - - Yucca will stay at internal SRAM for now. Not sure if somebody relies on - this setup. - - Signed-off-by: Stefan Roese - -commit 5cb4af4791f61843432155142b6cfac901f66c10 -Author: Stefan Roese -Date: Thu Oct 18 07:39:38 2007 +0200 - - ppc4xx: Add PCIe endpoint support on Kilauea (405EX) - - This patch adds endpoint support for the AMCC Kilauea eval board. It can - be tested by connecting a reworked PCIe cable (only 1x lane singles - connected) to another root-complex. - - In this test setup, a 64MB inbound window is configured at BAR0 which maps - to 0 on the PLB side. So accessing this BAR0 from the root-complex will - access the first 64MB of the SDRAM on the PPC side. - - Signed-off-by: Stefan Roese - -commit d4cb2d17946466740afeb195a57d6cb290bf4cc0 -Author: Stefan Roese -Date: Sat Oct 13 16:43:23 2007 +0200 - - ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode - - This patch adds support for dynamic configuration of PCIe ports for the - AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe - boards Yucca & Katmai and the 405EX board Kilauea. - - This dynamic configuration is done via the "pcie_mode" environement - variable. This variable can be set to "EP" or "RP" for endpoint or - rootpoint mode. Multiple values can be joined via the ":" delimiter. - Here an example: - - pcie_mode=RP:EP:EP - - This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 - as endpoint. - - Per default Yucca will be configured as: - pcie_mode=RP:EP:EP - - Per default Katmai will be configured as: - pcie_mode=RP:RP:REP - - Per default Kilauea will be configured as: - pcie_mode=RP:RP - - Signed-off-by: Tirumala R Marri - Signed-off-by: Stefan Roese - -commit fd671802b67a0ef37a06124fa2ce85f00aa22c6f -Author: Stefan Roese -Date: Thu Oct 11 11:15:59 2007 +0200 - - ppc4xx: Enable device tree support (fdt) on Kilauea per default - - This patch enables the fdt support on the AMCC Kilauea eval board. - Additionally now EBC ranges fdt fixup is included to support NOR - FLASH mapping via the Linux physmap_of driver. - - This Kilauea port now support booting arch/ppc and arch/powerpc - Linux kernels. The default environment "net_nfs" is for arch/ppc - and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc - support will be removed. - - Signed-off-by: Stefan Roese - -commit 4994ffd890b9d95d807387a9b7bd8a4803ee406e -Author: Stefan Roese -Date: Thu Oct 11 11:11:45 2007 +0200 - - ppc4xx: Add additional debug info to 4xx fdt support - - Signed-off-by: Stefan Roese - -commit db3232ddb058d0ed0bc31f7c5c296748a1afac67 -Author: Stefan Roese -Date: Fri Oct 5 21:28:58 2007 +0200 - - ppc4xx: Fix small merge problems with CPCI440 and Acadia boards - - Signed-off-by: Stefan Roese - -commit 1941cce71b1ae975602854045061e82f94ecd012 -Author: Stefan Roese -Date: Fri Oct 5 17:35:10 2007 +0200 - - ppc4xx: Fix small merge problem in 4xx_enet.c - - Signed-off-by: Stefan Roese - -commit 566806ca1a1bf4d895daaf0b2ba5494abbffebaf -Author: Stefan Roese -Date: Fri Oct 5 17:11:30 2007 +0200 - - ppc4xx: Add initial AMCC Kilauea 405EX support - - Signed-off-by: Stefan Roese - -commit dbbd125721aea6645fdb962f36bd41f59e272f9d -Author: Stefan Roese -Date: Fri Oct 5 17:10:59 2007 +0200 - - ppc4xx: Add PPC405EX support - - Signed-off-by: Stefan Roese - -commit 1d7b874e9c9a7c66f5d8da9ec78a3733765d3e31 -Author: Stefan Roese -Date: Fri Oct 5 17:09:36 2007 +0200 - - ppc4xx: Cleanup of 4xx PCI and PCIe support (renaming) - - Signed-off-by: Stefan Roese - -commit 4f14ed6230b9c109aac9a6fb878497dabd44c2db -Author: Stefan Roese -Date: Fri Oct 5 17:07:50 2007 +0200 - - ppc4xx: Add initial fdt support to 4xx (first needed on 405EX) - - Signed-off-by: Stefan Roese - -commit a424a8bb2924b90724b944165d3141f1fa8dfe5b -Author: Stefan Roese -Date: Fri Oct 5 17:04:57 2007 +0200 - - POST: Add 405EX support to 4xx UART POST test - - Signed-off-by: Stefan Roese - -commit 4f2e92c11f6e2392fc8187829211a5ca7f0c1e12 -Author: Stefan Roese -Date: Fri Oct 5 15:10:02 2007 +0200 - - DTT: Prepare DS1775 driver for use of different I2C addresses - - Signed-off-by: Stefan Roese - -commit 19e93b1e16d267220440d827b920fbad8abfa70f -Author: Stefan Roese -Date: Fri Oct 5 14:23:43 2007 +0200 - - ppc4xx: 4xx_pcie: Change PCIe status output to match common style - - Signed-off-by: Stefan Roese - -commit ff68f66bcb0da847845aa2fac11eba6c25938c99 -Author: Stefan Roese -Date: Fri Oct 5 09:22:33 2007 +0200 - - ppc4xx: 4xx_pcie: Disable debug output as default - - Signed-off-by: Stefan Roese - -commit 97923770cb52b64d69eec958a11b2eda8d46e0f7 -Author: Stefan Roese -Date: Fri Oct 5 09:18:23 2007 +0200 - - ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support added - - Signed-off-by: Stefan Roese - -commit 4dbee8a90df613eb517aadbecebd70f168913d30 -Author: Stefan Roese -Date: Fri Oct 5 07:57:20 2007 +0200 - - ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & Katmai - - 128MB seems to be the smallest possible value for the memory size - for on PCIe port. With this change now the BAR's of the PCIe cards - are accessible under U-Boot. - - One big note: This only works for PCIe port 0 & 1. For port 2 this - currently doesn't work, since the base address is now 0xc0000000 - (0xb0000000 + 2 * 0x08000000), and this is already occupied by - CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean - to change the base addresses completely and this change would have - too much impact right now. - - This patch adds debug output to the 4xx pcie driver too. - - Signed-off-by: Stefan Roese - -commit 6d95289281ed2958ebf76d2b55f86bbd88591fd2 -Author: Stefan Roese -Date: Wed Oct 3 21:16:32 2007 +0200 - - ppc4xx: 4xx_pcie: Fix problem with SDRN access using port number as idx - - Signed-off-by: Stefan Roese - -commit 3048bcbf0bad262378c5af68f2bf6778fb7d829a -Author: Stefan Roese -Date: Wed Oct 3 15:01:02 2007 +0200 - - ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platforms - - These files were introduced with the IBM 405GP but are currently used on all - 4xx PPC platforms. So the name doesn't match the content anymore. This patch - renames the files to 4xx_pci.c/h. - - Signed-off-by: Stefan Roese - -commit 94276eb0a7a35b9e8c053d589ae225b0f017a237 -Author: Stefan Roese -Date: Wed Oct 3 14:14:58 2007 +0200 - - ppc4xx: Add a comment for 405EX PCIe endpoint configuration - - Signed-off-by: Stefan Roese - -commit 03d344bb6a5f082ea10ec9d753558ea7dfd1c626 -Author: Stefan Roese -Date: Wed Oct 3 10:38:09 2007 +0200 - - ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3) - - (3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access - the SDR registers of the PCIe ports. This makes the overall design - clearer, since it removed a lot of switch statements which are not - needed anymore. - - Also, the functions ppc4xx_init_pcie_rootport() and - ppc4xx_init_pcie_entport() are merged into a single function - ppc4xx_init_pcie_port(), since most of the code was duplicated. - This makes maintainance and porting to other 4xx platforms - easier. - - Signed-off-by: Stefan Roese - -commit 026f71106871f31d17d0ea0db9a7547ff92934bc -Author: Stefan Roese -Date: Wed Oct 3 07:48:09 2007 +0200 - - ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2) - - This patch is the first patch of a series to make the 440SPe PCIe code - usable on different 4xx PPC platforms. In preperation for the new 405EX - which is also equipped with PCIe interfaces. - - (2) This patch renames the functions from 440spe_ to 4xx_ with a - little additional cleanup - - Signed-off-by: Stefan Roese - -commit c7c6da23028f146d912514b95aefa3da7cf37699 -Author: Stefan Roese -Date: Wed Oct 3 07:34:10 2007 +0200 - - ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1) - - This patch is the first patch of a series to make the 440SPe PCIe code - usable on different 4xx PPC platforms. In preperation for the new 405EX - which is also equipped with PCIe interfaces. - - (1) This patch renames the files from 440spe_pcie to 4xx_pcie - - Signed-off-by: Stefan Roese - -commit 245a362ad3c0c1b84fccc9fec7b623eb14f6e502 -Author: Marian Balakowicz -Date: Wed Oct 24 01:37:36 2007 +0200 - - TQM5200: Call usb_cpu_init() during board init - - usb_cpu_init() configures GPS USB pins, clocks, etc. and - is required for proper operation of kernel USB subsystem. - This setup was previously done in the kernel by the fixup - code which is being removed, thus low level init must be - done by U-boot now. - - Signed-off-by: Marian Balakowicz - Signed-off-by: Markus Klotzbuecher - -commit b5af773f8d92677e06f3295b45557c9d0a487c24 -Author: Zhang Wei -Date: Thu Oct 25 17:51:27 2007 +0800 - - Fix the issue of usb_kbd driver missing the scan code of key 'z'. - - The scan code of the key 'z' is 0x1d, which should be handled. - - The change has be tested on NOVATEK USB keyboard and ULI PCI OHCI - controller. - - Signed-off-by: Zhang Wei - Signed-off-by: Markus Klotzbuecher - -commit 85ac988e86f9414fa645b0148dc66c3520a1eb84 -Author: Rodolfo Giometti -Date: Mon Oct 15 11:59:17 2007 +0200 - - PXA USB OHCI: "usb stop" implementation. - - Some USB keys need to be switched off before loading the kernel - otherwise they can remain in an undefined status which prevents them - to be correctly recognized by the kernel. - - Signed-off-by: Rodolfo Giometti - Signed-off-by: Markus Klotzbuecher - -commit 31548249decf18a6b877a18436b6139dd483fe4a -Author: Justin Flammia -Date: Mon Oct 29 17:40:35 2007 -0400 - - DHCP Client Fix - - This is a multi-part message in MIME format. - - commit e6e505eae94ed721e123e177489291fc4544b7b8 - Author: Justin Flammia - Date: Mon Oct 29 17:19:03 2007 -0400 - - Found a bug in the way the DHCP Request packet is built, where the IP address - that is offered by the server is bound to prematurely. This patch is a fix of - that bug where the IP address offered by the DHCP server is not used until - after the DHCP ACK from the server is received. - - Signed-off-by: Justin Flammia - Signed-off-by: Ben Warren - -commit e8ee8f3ade2a06c1893dd5e68f223070d650c7ed -Author: TsiChungLiew -Date: Thu Oct 25 17:16:22 2007 -0500 - - ColdFire 54455: Fix correct boot location for atmel and intel - - Signed-off-by: TsiChungLiew - -commit 688e8eb414ac111cca7ce60bdf30e805ab9a7bcb -Author: TsiChungLiew -Date: Thu Oct 25 17:14:00 2007 -0500 - - ColdFire: Fix build error when CONFIG_WATCHDOG is defined - - Signed-off-by: TsiChungLiew - -commit c67e12e705b204cfe914e3e3e693d69a445dcabf -Author: TsiChungLiew -Date: Thu Oct 25 17:12:36 2007 -0500 - - ColdFire 5329: Assign correct SDRAM size and fix cache - - Signed-off-by: TsiChungLiew - -commit 95e9f2c212a65610b2e59a5c00d0113383a4da0b -Author: TsiChungLiew -Date: Thu Oct 25 17:10:23 2007 -0500 - - ColdFire 5253: Assign correct SDRAM size - - Signed-off-by: TsiChungLiew - -commit 2acefa72ee0026f862ab65597ca687428f63a973 -Author: TsiChungLiew -Date: Thu Oct 25 17:09:17 2007 -0500 - - ColdFire 5282: Fix external flash boot and return dramsize - - Signed-off-by: TsiChungLiew - -commit d78791ae914d4e7c5edca1cdad73b3dc81a4eb82 -Author: Bartlomiej Sieka -Date: Thu Oct 25 17:20:01 2007 +0200 - - TQM5200: increase kernel_addr_r and fdt_addr_r (hinted by Wolfgang Denk). - - Signed-off-by: Bartlomiej Sieka - -commit 1a0ce20aa4cb4e3068da04e7290ee9986fd0b834 -Author: Martin Krause -Date: Wed Oct 24 08:42:25 2007 +0200 - - TQM5200: fix spurious characters on second serial interface - - With this patch PSC3 is configured as UART. This is done, because if - the pins of PSC3 are not configured at all (-> all pins are GPI), - due to crosstalk, spurious characters may be send over the RX232_2_TXD - signal line. - - Signed-off-by: Martin Krause - Signed-off-by: Grant Likely - -commit be4a87f11e297a5cededbf7dd71c0248f3874acd -Author: Martin Krause -Date: Wed Oct 24 08:41:27 2007 +0200 - - TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller - - Some commands for the STK52xx base board try to access the SM501 grafic - controller. But the TQM5200S has no grafic controller (only the TQM5200 - and the TQM5200B have). This patch deactivates the commands accessing - the SM501 for the TQM5200S. - - Signed-off-by: Martin Krause - Signed-off-by: Grant Likely - -commit b31f64343ead9482cd439b1adbe4c34026a641b1 -Author: Martin Krause -Date: Mon Oct 22 16:45:53 2007 +0200 - - TQM5200: fix spurious characters on second serial interface - - With this patch PSC3 is configured as UART. This is done, because if - the pins of PSC3 are not configured at all (-> all pins are GPI), - due to crosstalk, spurious characters may be send over the RX232_2_TXD - signal line. - - Signed-off-by: Martin Krause - -commit 0fc0f91b20ffa802f5a66534ca5c2844910583f6 -Author: Martin Krause -Date: Mon Oct 22 16:40:06 2007 +0200 - - TQM5200S: fix commands for STK52xx base board because of missing SM501 grafic controller - - Some commands for the STK52xx base board try to access the SM501 grafic - controller. But the TQM5200S has no grafic controller (only the TQM5200 - and the TQM5200B have). This patch deactivates the commands accessing - the SM501 for the TQM5200S. - - Signed-off-by: Martin Krause - -commit 7b0a42219f30277f71f4405cbaf8a269f6d2d227 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sun Oct 21 09:14:28 2007 +0200 - - Mips: Fix string functions differ prototype declaration - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit cb8250fe4b3c4ed549b270e8a20bc22060e7e1d2 -Author: Ed Swarthout -Date: Fri Oct 19 17:51:40 2007 -0500 - - fsl_pci_init enable COMMAND_MEMORY if inbound window - - Patch 16e23c3f removed PCSRBAR allocation. But passing zero windows - to pciauto_setup_device has the side effect of not getting - COMMAND_MEMORY set. - - Signed-off-by: Ed Swarthout - -commit e9d0d527992566ebef9826962ff1745b2f082b92 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Oct 19 10:55:24 2007 +0200 - - delta: Fix OHCI_REGS_BASE undeclared and wait_ms implicit declaration - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 9c4884f54da982ce990c7d1760ac81b0704d3c64 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Oct 19 08:10:15 2007 +0200 - - fix warning: no return statement in function returning non-void - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit e78220f6e514206757acfe247297fc9a328a881f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Oct 19 06:33:45 2007 +0200 - - xsengine: Fix no partition type specified, use DOS as default - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 10cdb8dbd67a818823ab9ec88b68fc348903db59 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Oct 19 00:24:59 2007 +0200 - - lubbock: Fix no partition type specified, use DOS as default - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 41b4d282d38fa7231c315c5f6cfff5bdd24e0191 -Author: Wolfgang Denk -Date: Tue Oct 23 16:50:03 2007 +0200 - - Coding style: keep lists sorted; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 58b74b05c621e2835ecf4e2d3243042cf4186777 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Oct 19 00:09:05 2007 +0200 - - Fix missing drivers makefile entries ds1722.c mw_eeprom.c - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 96455bfebc9887837095c9051d216f53c61b5f10 -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Fri Oct 19 00:07:39 2007 +0200 - - Fix warning differ in signedness in board/innokom/innokom.c - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 2a4741d9a14ec475f50e9856d2c0a67e8b4271bd -Author: Marcel Ziswiler -Date: Fri Oct 19 00:25:33 2007 +0200 - - fix pxa255_idp board - - The pxa255_idp being an old unmaintained board showed several issues: - 1. CONFIG_INIT_CRITICAL was still defined. - 2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined. - 3. Symbol flash_addr was undeclared. - 4. The boards lowlevel_init function was still called memsetup. - 5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000. - 6. Using -march=armv5 instead of -march=armv5te resulted in lots of - 'target CPU does not support interworking' warnings on recent compilers. - 7. The PXA's serial driver redefined FFUART, BTUART and STUART used as - indexes rather than the register definitions from the pxa-regs header - file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to - avoid any ambiguities. - 8. There were several redefinition warnings concerning ICMR, OSMR3, - OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file. - 9. The board configuration file was rather outdated. - 10. The part header file defined the vendor, product and revision arrays - as unsigned chars instead of just chars in the block_dev_desc_t - structure. - - Signed-off-by: Marcel Ziswiler - -commit 298cd4cafe81ff8a6c87be8fbc440a20720d3ed6 -Author: Rune Torgersen -Date: Wed Oct 17 11:56:31 2007 -0500 - - Make MPC8266ADS command selection more robust - - Fix MPC8266 command line definition so it won't break when new commands - are added to u-boot. - Signed-off-by Rune Torgersen - -commit d3afa1ee19345a31fd1eaad3e98b97d13ca47315 -Author: Bartlomiej Sieka -Date: Tue Oct 23 13:14:10 2007 +0200 - - Motion-PRO: Update configuration to accomodate next generation board. - - New board has faster oscillator and a different Flash chip. This affects: - - CFG_MPC5XXX_CLKIN - - SDRAM timings - - Flash CS configuration (timings) - - Flash sector size, and thus MTD partition layout - - malloc() arena size (due to bigger Flash sectors) - - smaller memory test range (due to bigger malloc() arena) - - This patch also enables more extensive memory testing via "mtest". - - Signed-off-by: Bartlomiej Sieka - -commit eff501904df2bf1724a750062628ba2c51dbb1f8 -Author: Bartlomiej Sieka -Date: Tue Oct 23 11:36:07 2007 +0200 - - Motion-PRO: Add setting of SDelay reg. to SDRAM controller configuration. - - Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay - register must be written a value of 0x00000004 as the first step of the - SDRAM contorller configuration. - - Signed-off-by: Bartlomiej Sieka - -commit 7a9348728ebda63cdbaacffd83099aa71d9d4c54 -Author: Peter Pearse -Date: Tue Oct 23 10:22:16 2007 +0100 - - Move PL01* serial drivers to drivers/serial and adjust Makefiles. - -commit 20d500d531a6b971ce6cc1bf191cb0092cdc0afc -Author: Stefan Roese -Date: Tue Oct 23 10:17:42 2007 +0200 - - ppc4xx: lwmon5: Some further GPIO config changes - - Signed-off-by: Stefan Roese - -commit de9a738faa7c2f47286119c3bfebc3dfbfe7d86d -Author: Vlad Lungu -Date: Sun Oct 21 22:10:10 2007 +0900 - - [MIPS] Fix UNCACHED_SDRAM - - PHYSADDR is for physical address, KSEG1ADDR is for uncached. - - Signed-off-by: Vlad Lungu - Signed-off-by: Shinya Kuribayashi - -commit 00101dd7a32d12f698150123e47e4b3420279f86 -Author: Shinya Kuribayashi -Date: Sun Oct 21 21:30:42 2007 +0900 - - [MIPS] Add PIC-related switches to PLATFORM_{CPP,LD}FLAGS and cleanup - - Signed-off-by: Shinya Kuribayashi - -commit eb700636db017d310edaeb559b13d82588560674 -Author: Shinya Kuribayashi -Date: Sun Oct 21 10:55:37 2007 +0900 - - [MIPS] u-boot.lds: Define _gp in a standard manner - - Signed-off-by: Shinya Kuribayashi - -commit 22069215eb7adf5a3888bf7c7784ea9d70a72cd0 -Author: Shinya Kuribayashi -Date: Sun Oct 21 10:55:36 2007 +0900 - - [MIPS] Fix $gp usage - - Now we load $gp with _GLOBAL_OFFSET_TABLE_, but this is incorrect use. - As a general principle, we should use _gp for $gp. - - Thanks to linker script's help we fortunately have _gp which equals to - _GLOBAL_OFFSET_TABLE_. But once _gp gets out of alignment, we will not - be able to access to GOT entires, global variables and procedure entry - points. The right thing to do is to use _gp. - - This patch also introduce a new symbol `.gpword _GLOBAL_OFFSET_TABLE_' - which holds the offset from _gp. When updating GOT entries, we use this - offset and _gp to calculate the final _GLOBAL_OFFSET_TABLE_. - - This patch is originally submitted by Vlad Lungu , then - I made some change to leave over num_got_entries. - - Signed-off-by: Shinya Kuribayashi - Cc: Vlad Lungu - -commit cbf2323b5b8285ea01acba7bbb905a3162d9b021 -Author: Shinya Kuribayashi -Date: Sun Oct 21 10:55:36 2007 +0900 - - [MIPS] u-boot.lds: Fix __got_start and __got_end - - Ensure that __got_start points to top of the `.got', and __got_end points - to bottom as well, so that we never fail to count num_got_entries. - - Signed-off-by: Shinya Kuribayashi - -commit e5f325fec5b48ae705c89522923ba5a2e37cd5c7 -Author: Shinya Kuribayashi -Date: Sun Oct 21 10:55:36 2007 +0900 - - [MIPS] u-boot.lds: Remove duplicated .sdata section - - Signed-off-by: Shinya Kuribayashi - -commit 05bf4919c1ce49cdedadacd564d0786a8ed796a1 -Author: Wolfgang Denk -Date: Sun Oct 21 01:01:17 2007 +0200 - - Minor coding style cleanup; update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit ff285ca07eda1ea4a8909848cc1cc604ec8fec9c -Author: Vlad Lungu -Date: Thu Oct 4 20:47:10 2007 +0300 - - Fix NE2000 driver: - - Fixed typo in ne2000.h, thinko re n2k_inb() usage, don't try - to do anything in eth_stop() if eth_init() was not called. - Simplified RX path in order to avoid timeouts on really really - fast NE2000 cards (read: qemu with internal tftp), NetLoop() is - clever enough to cope with 1 packet per eth_rx(). - - Signed-off-by: Vlad Lungu - -commit df90968b48fb34fa9072fab150db2ac89678f537 -Author: urwithsughosh@gmail.com -Date: Mon Sep 24 13:32:13 2007 -0400 - - Setting MSR[DE] in do_reset - - Hello, - This patch ensures the soft reset of the board for the 85xx boards - by setting the MSR[DE] in the do_reset function. - - Signed-off-by: Sughosh Ganu - -commit 1e701e701304b3c3a3768ca83dd2ab7b9e88c77d -Author: urwithsughosh@gmail.com -Date: Mon Sep 24 13:36:01 2007 -0400 - - MSR overwrite fix - - Hello, - This patch fixes the MSR overwrite in the start.S when moving out of - the last 4K page. - - Signed-off-by: Sughosh Ganu - -commit 5c7ea64bb74a850a2b2303f853a8270695ad8602 -Author: Dan Wilson -Date: Fri Oct 19 11:33:48 2007 -0500 - - tsec driver should clear RHALT on startup - - This was causing problems for some people. - - Signed-off-by: Alain Gravel - Signed-off-by: Dan Wilson - Signed-off-by: Andy Fleming - -commit 7600d47b8f6a10019e537dc9a62aa1498df58d25 -Author: Kumar Gala -Date: Thu Oct 11 00:29:18 2007 -0500 - - Improve handling of PCI interrupt device tree fixup on MPC85xx CDS - - On the MPC85xx CDS we have two issues: - - 1. The device tree fixup code did not check to see if the property we are - trying to update is actually found. Its possible that it would update - random memory starting at 0. - - 2. Newer Linux kernel's have moved the location of the PCI nodes to be - sibilings of the soc node and not children. The explicit PATH to the PCI - node would not be found for these device trees. Add the ability to handle - both paths. In the future we shouldn't handle such fixups by explicit path. - - Signed-off-by: Kumar Gala - -commit a3063eec775719b7e91023bbec3f64b3118791df -Author: Kumar Gala -Date: Thu Oct 11 00:18:48 2007 -0500 - - Set OF_STDOUT_PATH to match the default console on MPC8568 MDS - - On the MPC8568 MDS we use ttyS0, UART0, etc. as the standard configured - console. Make it so we match that config what we tell Linux as the early - STDOUT console. - - Signed-off-by: Kumar Gala - -commit e1ce3cb617bb06f91f82f98915391175addf3e82 -Author: Kumar Gala -Date: Tue Oct 2 11:12:27 2007 -0500 - - Remove magic numbers from cache related operations for mpc85xx - - The mpc85xx start code uses some magic numbers that we actually - have #defines for in so use those instead. - - Signed-off-by: Kumar Gala - -commit 5441f61a3d8b7034f19fc1361183e936198e6dbb -Author: Detlev Zundel -Date: Fri Oct 19 16:47:26 2007 +0200 - - Fix two typos. - - Signed-off-by: Detlev Zundel - -commit 281df457c1aa50d2752165d0c5c3282d4027b974 -Author: Tony Li -Date: Thu Oct 18 17:47:19 2007 +0800 - - mpc83xx: Add configure entry for MPC83xx ATM support - - Add MPC8360EMDS_ATM_config and MPC832XEMDS_ATM_config into - Makfile and MAKEALL - - Signed-off-by: Tony Li - Signed-off-by: Kim Phillips - -commit d2646554f529a9577515eceb0ec5eceee18244ba -Author: Tony Li -Date: Thu Oct 18 17:44:38 2007 +0800 - - mpc83xx: pq-mds-pib.c typo error - - Correct to val8 from val. - - Signed-off-by: Tony Li - Signed-off-by: Kim Phillips - -commit 3e11ae80fec1ee12194940955431186abf6009c2 -Author: Stefan Roese -Date: Wed Oct 17 15:40:19 2007 +0200 - - ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap command - - Signed-off-by: Stefan Roese - -commit 3c89d75409eb26639d36dfa11d4ee3d8b962dc3c -Author: Jon Loeliger -Date: Tue Oct 16 15:27:43 2007 -0500 - - Initial mpc8610hpcd Makefile files. - - Signed-off-by: Ed Swarthout - Signed-off-by: Mahesh Jade - Signed-off-by: Jason Jin - Signed-off-by: Jon Loeliger - -commit 9553df86d3a319c3a1a7cde7e4edd6eeb5aa64c7 -Author: Jon Loeliger -Date: Tue Oct 16 15:26:51 2007 -0500 - - Initial mpc8610hpcd cpu/, README and include/ files. - - Signed-off-by: Ed Swarthout - Signed-off-by: Mahesh Jade - Signed-off-by: Jason Jin - Signed-off-by: Jon Loeliger - -commit 3dd2db53ceb0dff80f25c2a07f83f29b907b403e -Author: Jon Loeliger -Date: Tue Oct 16 13:54:01 2007 -0500 - - Initial mpc8610hpcd board files. - - Signed-off-by: Ed Swarthout - Signed-off-by: Mahesh Jade - Signed-off-by: Jason Jin - Signed-off-by: Jon Loeliger - -commit 7ee6ba1a056e4061ab4cfde30127e332e7957afd -Author: runet@innovsys.com -Date: Tue Oct 16 14:50:40 2007 -0500 - - Make MPC8266ADS board compile again. - - Signed-off-by: Runet Torgersen - -commit 2491167c245d8ebe6f2dbd8c4287aaa0d14fe93a -Author: Jon Loeliger -Date: Mon Aug 27 12:41:03 2007 -0500 - - 86xx: Allow for fewer DDR slots per memory controller. - - As a direct correlation exists between DDR DIMM slots - and SPD EEPROM addresses used to configure them, use - the individually defined SPD_EEPROM_ADDRESS* values to - determine if a DDR DIMM slot should have its SPD - configuration read or not. - - Effectively, this now allows for 1 or 2 DIMM slots - per memory controller. - - Signed-off-by: Jon Loeliger - -commit 4d4a945e189a2f384c66432316da2788a0ac1607 -Author: Rodolfo Giometti -Date: Mon Oct 15 11:59:17 2007 +0200 - - PXA USB OHCI: "usb stop" implementation. - - Some USB keys need to be switched off before loading the kernel - otherwise they can remain in an undefined status which prevents them - to be correctly recognized by the kernel. - - Signed-off-by: Rodolfo Giometti - -commit e2e93442e558cf1500e92861f99713b2f045ea22 -Author: Stefan Roese -Date: Mon Oct 15 11:39:00 2007 +0200 - - ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier - - The I2C bootstrap values that can be setup via the "bootstrap" command, - were setup incorrect regarding the generation of the internal sync PCI - clock. The values for PLB clock == 133MHz were slighly incorrect and the - values for PLB clock == 166MHz were totally incorrect. This could - lead to a hangup upon booting while PCI configuration scan. - - This patch fixes this issue and configures valid PCI divisor values - for the sync PCI clock, with respect to the provided external async - PCI frequency. - - Here the values of the formula in the chapter 14.2 "PCI clocking" - from the 440EPx users manual: - - AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz - - 33MHz async PCI frequency: - PLB = 133: - => 32 <= 44.3 <= 65 (div = 3) - - PLB = 166: - => 32 <= 55.3 <= 65 (div = 3) - - 66MHz async PCI frequency: - PLB = 133: - => 65 <= 66.5 <= 132 (div = 2) - - PLB = 166: - => 65 <= 83 <= 132 (div = 2) - - Signed-off-by: Stefan Roese - -commit 5a5958b7de70ae99f0e7cbd5c97ec1346e051587 -Author: Stefan Roese -Date: Mon Oct 15 11:29:33 2007 +0200 - - ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite - - The BCSR status bit for the 66MHz PCI operation was correctly - addressed (MSB/LSB problem). Now the correct currently setup - PCI frequency is displayed upon bootup. - - This patch also fixes this problem on Rainier & Yellowstone, since these - boards use the same souce code as Sequoia & Yosemite do. - - Signed-off-by: Stefan Roese - -commit da3aad55cbde80ab6e301aafa82a2c411aa53eff -Author: Martin Krause -Date: Wed Sep 26 17:55:56 2007 +0200 - - TQM860M: adjust for doubled flash sector size. - - Adjust flash map to support the new S29GLxxN (N-Type) Flashes with - doubled sector size. - - Signed-off-by: Martin Krause - -commit 9d29250e2e62f4bf20c7a20b4173d84c48f11f5d -Author: Jens Gehrlein -Date: Wed Sep 26 17:55:54 2007 +0200 - - TQM8xx: Fix CAN timing. - - Signed-off-by: Martin Krause - -commit d43e489baf02afae49077791fb22332d240d8656 -Author: Martin Krause -Date: Thu Sep 27 14:54:36 2007 +0200 - - TQM866M: fix SDRAM refresh - - At 133 MHz the current SDRAM refresh rate is too fast - (measured 4 * 1.17 us). - CFG_MAMR_PTA changes from 39 to 97. This result - in a refresh rate of 4 * 7.8 us at the default clock - 50 MHz. At 133 MHz the value will be then 4 * 2.9 us. - This is a compromise until a new method is found to - adjust the refresh rate. - - Signed-off-by: Martin Krause - -commit 9ef57bbee1c67cc01da2026c242c4692db32be36 -Author: Martin Krause -Date: Wed Sep 26 17:55:55 2007 +0200 - - TQM866M: adjust for doubled flash sector size. - - Adjust flash map to support the new S29GLxxN (N-Type) Flashes with - doubled sector size. - - Signed-off-by: Martin Krause - -commit f8bf90461d9bad2e6fed31fcebaf235f60dd6763 -Author: Michal Simek -Date: Sun Oct 14 16:12:29 2007 +0200 - - [FIX] XUPV2P change command handling - and remove code violation - -commit 636400198228d96983c06657b17f760f5989958e -Author: Wolfgang Denk -Date: Sun Oct 14 00:13:19 2007 +0200 - - Prepare for 1.3.0-rc3 release - - Signed-off-by: Wolfgang Denk - -commit 68f14f77ca5fe5f9cc025c8cae101671f628309f -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Sat Sep 29 13:41:37 2007 +0200 - - Fix warning differ in signedness in cpu/pxa/mmc.c - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit fc19e36f741e8bc727c0a330170b3b5db90399ef -Author: Wolfgang Denk -Date: Sat Oct 13 23:51:14 2007 +0200 - - Fix warning differ in signedness in board/mpl/vcma9/vcma9.c - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - Signed-off-by: Wolfgang Denk - -commit de74b9eeacccaf0a42e5ecc9ae79a88f7a311296 -Author: Wolfgang Denk -Date: Sat Oct 13 21:15:39 2007 +0200 - - Coding Style cleanup. - - Signed-off-by: Wolfgang Denk - -commit e1893815b0999410d7a327589611c7b38e95299e -Author: Wolfgang Denk -Date: Fri Oct 12 15:49:39 2007 +0200 - - GP3 SSA: enable RTC - - Signed-off-by: Wolfgang Denk - -commit 8002012041f1ff9f997a5727abe5015f70cd2e46 -Author: Grzegorz Bernacki -Date: Tue Oct 9 13:58:24 2007 +0200 - - [ads5121] EEPROM support added. - - Signed-off-by: Grzegorz Bernacki - -commit 7b624ad254b97e5a25dca2304a398b64aeedaffe -Author: Haavard Skinnemoen -Date: Sat Oct 6 18:55:35 2007 +0200 - - AVR32: Initialize bi_flash* in board_init_r - - The ATSTK1000-specific flash driver intializes bi_flashstart, - bi_flashsize and bi_flashoffset, but other flash drivers, like the CFI - driver, don't. - - Initialize these in board_init_r instead so that things will still be - set up correctly when we switch to the CFI driver. - - Signed-off-by: Haavard Skinnemoen - -commit 2b2a587d6d3076387d22ac740f44044bf46e2cb8 -Author: Marian Balakowicz -Date: Fri Oct 5 10:40:54 2007 +0200 - - tqm5200: Fix CONFIG_CMD_PCI typo in board config file. - - Signed-off-by: Marian Balakowicz - -commit 92869195ef8210758d2176230c0a36897afd50ed -Author: Bartlomiej Sieka -Date: Fri Oct 5 09:46:06 2007 +0200 - - CM5200: Fix missing null-termination in hostname manipulation code - - Signed-off-by: Bartlomiej Sieka - -commit 9add9884b1fddc34ca186e00a2f868ccd5d02d87 -Author: Haavard Skinnemoen -Date: Tue Oct 2 19:09:01 2007 +0200 - - Fix memtest breakage - - CFG_MEMTEST_START uses weird magic involving gd, which fails to - compile. Use hardcoded values instead (we actually know how much RAM - we have on board.) - - Signed-off-by: Haavard Skinnemoen - -commit 738815c0cc44aa329097f868dc1efc49ede9c5ba -Author: Stefan Roese -Date: Tue Oct 2 11:44:46 2007 +0200 - - ppc4xx: Coding style cleanup - - Signed-off-by: Stefan Roese - -commit 87c1833a39e944db66385286fd5e28f9b3fcdd50 -Author: Stefan Roese -Date: Tue Oct 2 11:44:19 2007 +0200 - - ppc4xx: lwmon5: Remove watchdog for now, since not fully tested yet - - Signed-off-by: Stefan Roese - -commit 2db64784061bfc34f4ba70ef1d2fbe7133b55670 -Author: Grzegorz Bernacki -Date: Mon Oct 1 09:51:50 2007 +0200 - - Program EPLD to force full duplex mode for PHY. - - EPLD forces modes of PHY operation. By default full duplex is turned off. - This fix turns it on. - - Signed-off-by: Grzegorz Bernacki - -commit 785c13477b77dcd2e6c5128fffcdb4e1943f4818 -Author: Timo Ketola -Date: Mon Sep 24 14:50:32 2007 +0300 - - Bugfix: Use only one PTD for one endpoint - - Original isp116x-hcd code prepared multiple PTDs for longer than 16 - byte transfers for one endpoint. That is unnecessary because the - ISP116x is able to split long data from one PTD into multiple - transactions based on the buffer size of the endpoint. It also caused - serious problems if the endpoint NAKed some of the transactions. In - that case ISP116x wouldn't notice that the other PTDs were for the same - endpoint and would try the other PTDs possibly out of order. That would - break the whole transfer. - - This patch makes isp116x_submit_job to use one PTD for one transfer. - - Signed-off-by: Timo Ketola - Signed-off-by: Markus Klotzbuecher - -commit 86ec86c04326c3913178a7679aa910de071da75d -Author: Jean-Christophe PLAGNIOL-VILLARD -Date: Thu Sep 27 23:27:47 2007 +0200 - - Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial - - Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD - -commit 3e954beb614b5b190d7f4f4c3b641437a0132e35 -Author: Stefan Roese -Date: Tue Sep 11 14:12:55 2007 +0200 - - ppc4xx: lwmon5: Change GPIO 58 to default to low (watchdog test) - - Signed-off-by: Stefan Roese - -commit 1487adbdcf9594bb2eb686325a6f9540dad1b70a -Author: Ed Swarthout -Date: Wed Sep 26 16:35:54 2007 -0500 - - 85xx io out functions need sync after write. - - This fixes the mc146818 rtc_read/write functions for 85xx. - - Signed-off-by: Ed Swarthout - -commit 0d38effc6e359e6b1b0c78d66e8bc1a4dc15a2ae -Author: Grant Likely -Date: Tue Sep 25 15:48:05 2007 -0600 - - Fpga: fix incorrect test of CFG_FPGA_XILINX macro - - CFG_FPGA_XILINX is a bit value used to test against the value in - CONFIG_FPGA. Testing for a value will always return TRUE. I don't - think that is the intention in this code. - - Signed-off-by: Grant Likely - -commit 853643d8cf2ca80cb2e25c53ad5dc580abafe166 -Author: Michal Simek -Date: Mon Sep 24 00:41:30 2007 +0200 - - [FIX] change command handling and removing code violation - -commit f240356507038e5ce55e8a24cb2607e9eae6d10c -Author: Michal Simek -Date: Mon Sep 24 00:36:06 2007 +0200 - - [FIX] change sets of commands - because changing of command handling brings - compilation problems - -commit cb1bc63b75a232571eb69aa2c8aa919321655845 -Author: Michal Simek -Date: Mon Sep 24 00:30:42 2007 +0200 - - [FIX] Email reparation & Copyright - Both codes are written by myself without any - support from CTU - -commit 0731cbae6c2feab93b244d83fd6a43f5cc9bf852 -Author: Michal Simek -Date: Mon Sep 24 00:25:11 2007 +0200 - - [PATCH] Change macro name for UartLite - because PowerPC 405 can use UartLite as console - -commit 1c1100d2fcf46b9d11dcf78d6e5aea75e2e8b716 -Author: Michal Simek -Date: Mon Sep 24 00:21:19 2007 +0200 - - [PATCH] Add support for design without interrupt controller - Polling timer - -commit 0731933ec8ec45d02ba89b52df673d526873cdde -Author: Michal Simek -Date: Mon Sep 24 00:19:48 2007 +0200 - - [FIX] resolve problem with cpu without barrel shifter - -commit db14d77995ce515b728b178b63f82babe60e3d56 -Author: Michal Simek -Date: Mon Sep 24 00:18:46 2007 +0200 - - [FIX] repair email address - -commit 481d4328618804add1f818a6c96296121cd0528e -Author: Michal Simek -Date: Mon Sep 24 00:17:42 2007 +0200 - - [FIX] repair MFSL commands - -commit b90c045f035c3cc9b5d2edaed6048dfb74e40763 -Author: Michal Simek -Date: Mon Sep 24 00:08:37 2007 +0200 - - synchronizition with mainline - -commit eda3e1e6619ad0bee94ae4b16c99d88e77e2af13 -Author: Nobuhiro Iwamatsu -Date: Sun Sep 23 02:42:38 2007 +0900 - - sh: Add support command of ide with sh - - Signed-off-by: Nobuhiro Iwamatsu - -commit d91ea45d15cf8e0987456bd211ffbb650824b6f1 -Author: Nobuhiro Iwamatsu -Date: Sun Sep 23 02:38:42 2007 +0900 - - sh: Update Makefile - - Add support MS7722SE01 to Makefile. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 6c0bbdccd379f5c8702af9e0765294c2fb7472a6 -Author: Nobuhiro Iwamatsu -Date: Sun Sep 23 02:31:13 2007 +0900 - - sh: Add support Renesas sh7722 processor and Hitachi MS7722SE01 board - - Signed-off-by: Nobuhiro Iwamatsu - -commit 047375bfa4c3052fa50a748da7ff89e9dad3b364 -Author: Nobuhiro Iwamatsu -Date: Sun Sep 23 02:19:24 2007 +0900 - - sh: Update MS7750SE01 platform - - Signed-off-by: Nobuhiro Iwamatsu - -commit 516ad760db3553766267ada01b7d5d727faa4bbd -Author: Nobuhiro Iwamatsu -Date: Sun Sep 23 02:17:08 2007 +0900 - - sh: Remove comment out code from include/asm-sh/cpu_sh4.h - - Signed-off-by: Nobuhiro Iwamatsu - -commit b02bad128669e567fce87d8df823b06a0144b8db -Author: Nobuhiro Iwamatsu -Date: Sun Sep 23 02:12:30 2007 +0900 - - sh: Update core code of SuperH. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 66dcad3a9a53e0766d90e0084123bd8529522fb0 -Author: Wolfgang Denk -Date: Thu Sep 20 00:04:14 2007 +0200 - - v1.3.0-rc2 - - Signed-off-by: Wolfgang Denk - -commit 135e19bc2773ebca487e9a8371f67e1ba202313a -Author: Wolfgang Denk -Date: Tue Sep 18 21:36:35 2007 +0200 - - Avoid compiler warning. - - Signed-off-by: Wolfgang Denk - -commit 8a783a65851bc7421ab69f442261215e21b8891a -Author: Grant Likely -Date: Tue Sep 18 12:24:57 2007 -0600 - - Bugfix: remove embedded null (\0) from CFG_BOOTFILE macro in TQM8540_config - - /bin/bash and /bin/dash (which /bin/sh is linked to on ubuntu) handle embedded - nulls in a string differently. For example, the following statement: - echo "this is a string\0" > afile - Will produce the following with /bin/bash: - "this is a string\0" - But with /bin/dash, will produce: - "this is a string - - Bug fixed by moving the embedded null out of the makefile and into the - config header. Also renamed the macro to avoid usage colision with the same - macro used by other board ports. - - Signed-off-by: Grant Likely - -commit f8d3ca7b6fa322ac57e8e831f07dbeea039a9f35 -Author: Wolfgang Denk -Date: Tue Sep 18 17:40:27 2007 +0200 - - MCC200: fix build warning - - The MCC200 board config file includes version.h for some customer- - specific setting, which causes warnings with "make depend"; build - version.h before depend. - - Signed-off-by: Wolfgang Denk - -commit bd86220f58b99d6896198c385fda132f0c980915 -Author: Peter Pearse -Date: Tue Sep 18 13:07:54 2007 +0100 - - Move coloured led API to status_led.h - Improve indentation in drivers/at45.c - -commit e80e585b00fbbab7ad1bf71619741f2c5b029ab7 -Author: Eirik Aanonsen -Date: Tue Sep 18 08:47:20 2007 +0200 - - Update atstk1002 bootargs. - - Updates to atstk1002 U-Boot header file: - - Changed bootargs: - * Set the bootargs for at1002 to point to the SD-card partition instead - * ... of the boot flash. - * Removing the rootfstype since that argument are not needed. - - Signed-off-by: Eirik Aanonsen - Signed-off-by: Haavard Skinnemoen - -commit a4f3aab6dfbed6c29367c688bfb8a47eef62c225 -Author: Eirik Aanonsen -Date: Wed Sep 12 13:32:37 2007 +0200 - - Add some comments to clocks in atstk1002.h - - This patch applies some clarifying comments to how the different - clocks are setup according to atstk1002.h Some of the previous - comments where stating wrongful information. - - Signed-off-by: Haavard Skinnemoen - -commit 97213f32416ead885deafea86774e912ffd60ad0 -Author: David Saada -Date: Mon Sep 17 17:04:47 2007 +0200 - - Description: Add NEC's PCI OHCI module ID to the USB OHCI driver - - Signed-off-by: David Saada - -commit 30363e98fa470fbecea5e8bc0f1443352754f303 -Author: Stefan Roese -Date: Mon Sep 17 08:20:47 2007 +0200 - - Small whitespace cleanup of OneNAND patch - - Signed-off-by: Stefan Roese - -commit d7e8ce101a4a45ed6ed45739fc2de5f87b13f7f1 -Author: Kyungmin Park -Date: Mon Sep 10 17:15:14 2007 +0900 - - OneNAND support (take #2) - - [PATCH 3/3] OneNAND support (take #2) - - OneNAND support at U-Boot - - Signed-off-by: Kyungmin Park - -commit 17aa2800457df0c06b41516f46f126712c196219 -Author: Kyungmin Park -Date: Mon Sep 10 17:14:34 2007 +0900 - - OneNAND support (take #2) - - [PATCH 2/3] OneNAND support (take #2) - - OneNAND support at U-Boot - - Signed-off-by: Kyungmin Park - -commit 916527f4809a7bcd811f1f1daf34af184e31dd8c -Author: Kyungmin Park -Date: Mon Sep 10 17:13:49 2007 +0900 - - OneNAND support (take #2) - - [PATCH 1/3] OneNAND support (take #2) - - OneNAND support at U-Boot - - Signed-off-by: Kyungmin Park - -commit b49c90df6e7cfcfb8b862b8bbf8448dff5eed9a5 -Author: Michal Simek -Date: Sun Sep 16 20:51:57 2007 +0200 - - [FIX] remove files form repository - -commit 67c31036acaaaa992fc346cc89db0909a7e733c4 -Author: Wolfgang Denk -Date: Sun Sep 16 17:10:04 2007 +0200 - - TQM8xx[LM]: Fix broken environment alignment. - - With recent toolchains, the environment sectors were no longer aligned to - sector boundaries. The reason was a combination of two bugs: - - 1) common/environment.c assumed that CONFIG_TQM8xxL would be defined - for all TQM8xxL and TQM8xxM boards. But "include/common.h", where - this gets defined, is not included here (and cannot be included - without causing lots of problems). - - Added a new #define CFG_USE_PPCENV for all boards which really - want to put the environment is a ".ppcenv" section. - - 2) The linker scripts just include environment.o, silently assuming - that the objects in that file are really in the order in which - they are coded in the C file, i. e. "environment" first, then - "redundand_environment", and "env_size" last. However, current - toolchains (GCC-4.x) reorder the objects, causing the environment - data not to start on a flash sector boundary: - - Instead of: we got: - - 40008000 T environment 40008000 T env_size - 4000c000 T redundand_environment 40008004 T redundand_environment - 40010000 T env_size 4000c004 T environment - - Note: this patch fixes just the first part, and cures the alignment - problem by making sure that "env_size" gets placed correctly. However, - we still have a potential issue because primary and redundant - environment sectors are actually swapped, i. e. we have now: - - 40008000 T redundand_environment - 4000c000 T environment - 40010000 T env_size - - This shall be fixed in the next version. - - Signed-off-by: Wolfgang Denk - -commit eb6da8050797c204c9d010548424186c7ce32fc1 -Author: Wolfgang Denk -Date: Sun Sep 16 02:39:35 2007 +0200 - - TQM8xx/FPS8xx: adjust flash partitions for 2.6 ARCH=powerpc kernels - - Signed-off-by: Wolfgang Denk - -commit cd2d1602c54cc6957bdef3872272a4b264893960 -Author: urwithsughosh@gmail.com -Date: Mon Sep 10 14:54:56 2007 -0400 - - Typo fix in tsec.c - - Fixup for the break statement in wrong place. - - [Patch by urwithsughosh@gmail.com] - Acked-by: Andy Fleming - Signed-off-by: Wolfgang Denk - -commit 5bd7fe9aeb76906371f40b8fd07613f10922e3e7 -Author: Matthias Fuchs -Date: Tue Sep 11 17:04:00 2007 +0200 - - Fix do_div() usage in nand process output - - Fix usage of do_div() in nand erase|read|write process output. - - The last patch to nand_util.c introduced do_div() instead of libgcc's - implementation. But do_div() returns the quotient in its first - macro parameter and not as result. - - Signed-off-by: Matthias Fuchs - -commit c750d2e6692a000a82f29de7bf24e3dc21239161 -Author: Matthias Fuchs -Date: Wed Sep 12 12:36:53 2007 +0200 - - NAND: Add CFG_NAND_QUIET option - - This config option sets the default for the progress information - output behavior that can also be configured through the 'quiet' - environment variable. - - The legacy NAND code does not print the current progress info - on the console. So this option is for backward compatibility for - units that are in the field and where setting the quiet variable - is not an option. With CFG_NAND_QUIET set to '1' the console - progress info is turned off. This can still be overwritten - through the environment variable. - - Signed-off-by: Matthias Fuchs - -commit dcb88630290d2bcd803386dd4c2be73142994c4f -Author: Liew Tsi Chung-r5aahp -Date: Thu Sep 13 16:06:05 2007 -0700 - - ColdFire: fix build error becasue of bad type of mii_init() - - Signed-off-by: TsiChungLiew - -commit 314d5b6ce52a4ed19dd295d1364e246c5e605017 -Author: Liew Tsi Chung-r5aahp -Date: Thu Sep 13 16:04:05 2007 -0700 - - ColdFire: Fix build error caused by pixis.c - - Moved the #include inside the #ifdef CONFIG_FSL_PIXIS. - - Signed-off-by: TsiChungLiew - -commit e21659e30660a1377c42af135a6114efe39801d9 -Author: Sam Sparks -Date: Fri Sep 14 11:14:42 2007 -0600 - - Update MPC8349ITX*_config to place config.tmp in right place. - - MPC834ITX*_config does not store config.tmp at the correct locatation, - causing MPC8349ITXGP to have the wrong TEXT_BASE. - - Signed-off-by: Sam Sparks - Signed-off-by: Grant Likely - -commit 1218abf1b5817a39a82399b4b928b00750575bda -Author: Wolfgang Denk -Date: Sat Sep 15 20:48:41 2007 +0200 - - Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global - - Signed-off-by: Wolfgang Denk - -commit 66b3f24d665be678a9dbb125b1e84185400f63b5 -Author: Dirk Behme -Date: Sat Sep 15 11:55:42 2007 +0200 - - Make DECLARE_GLOBAL_DATA_PTR global for DaVinci - - As discussed in [1], DECLARE_GLOBAL_DATA_PTR has to be global and not - function local. - - Signed-off-by: Dirk Behme - - [1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805 - -commit 991b089d1ce5ad945725e3657a8f106dfa02a38e -Author: Michal Simek -Date: Sat Sep 15 00:03:35 2007 +0200 - - Synchronize with U-BOOT mainline - -commit d7fee32b7e61fe11c64e371cde79faa4768e8350 -Author: Sam Sparks -Date: Fri Sep 14 11:14:42 2007 -0600 - - Update MPC8349ITX*_config to place config.tmp in right place. - - MPC834ITX*_config does not store config.tmp at the correct locatation, - causing MPC8349ITXGP to have the wrong TEXT_BASE. - - Signed-off-by: Sam Sparks - Signed-off-by: Grant Likely - Signed-off-by: Kim Phillips - -commit 6e7b7b6ea1b6d04dbe96242eb6a0c1c664c98e8c -Author: Bartlomiej Sieka -Date: Thu Sep 13 18:21:48 2007 +0200 - - cm5200: Fix a typo introduced by afaac86fe2948ac84cd9a12bbed883b3c683e7d9 - - Signed-off-by: Marian Balakowicz - -commit e1f601b572db5de9aa81a0b77c68a86994fe24c4 -Author: Bartlomiej Sieka -Date: Thu Sep 13 16:33:59 2007 +0200 - - tqm5200: Restore customary env. variable boot commands for powerpc kernels - - - update default definitions of kernel_addr and fdt_addr env. variables - - make arch/powerpc booting the default scenario - - update MTD partition layout to match the above - - Signed-off-by: Bartlomiej Sieka - -commit f34024d4a328e6edd906456da98d2c537155c4f7 -Author: Wolfgang Denk -Date: Wed Sep 12 00:48:57 2007 +0200 - - Fix memory corruption problem on STX GP3 SSA Board. - - Signed-off-by: Wolfgang Denk - -commit d94c79e47011af5e8dd10ed6163c09b4cfc743cc -Author: Peter Pearse -Date: Tue Sep 11 15:35:01 2007 +0100 - - Final tidy - -commit 38ad82da0c1180ecdeb212a8f4245e945bcc546e -Author: Grzegorz Bernacki -Date: Tue Sep 11 15:42:11 2007 +0200 - - [GP3SSA] Add define CONFIG_MPC85XX_PCI2 in config file to allow u-boot to - scan on second pci bus. - - Signed-off-by: Grzegorz Bernacki - -commit 6c2f4f388e8181655ea8b69343ea00b68aa6e8d0 -Author: Grzegorz Bernacki -Date: Tue Sep 11 12:57:52 2007 +0200 - - [ppc4xx] Individual handling of sdram.c for bamboo_nand build - - Bamboo has a file sdram.c which needs special treatment when building in - separate directory. It has to be linked to build directory otherwise it is - not seen. - - Signed-off-by: Grzegorz Bernacki - -commit d45963854eff39d575124d859419bb4953ce2c87 -Author: Michal Simek -Date: Tue Sep 11 00:37:04 2007 +0200 - - [FIX] Microblaze ML401 - repare FLASH handling - -commit 38c1ef728d19950414a8ab1ccfc53767848fa346 -Author: Sean MCGOOGAN -Date: Mon Sep 10 16:55:59 2007 +0100 - - Allocate CPU Architecture Code for STMicroelectronics' ST200. - - Signed-off-by: Sean McGoogan - --------------------------------------------------- - -commit 754bac48156f8958d8f6a53a51eda88ab5758929 -Author: Wolfgang Denk -Date: Mon Sep 10 20:42:31 2007 +0200 - - Update version to match current state. - - Signed-off-by: Wolfgang Denk - -commit 7a888d6b3c32a126dbb504ef146bb4c26574ca7b -Author: Grzegorz Bernacki -Date: Mon Sep 10 17:39:08 2007 +0200 - - [MPC512x] Streamline frame handling in the FEC driver - - - convert frame size settings to be derived from a single base - - set frame size to the recommended default value - - Signed-off-by: Grzegorz Bernacki - -commit e251e00d0db4b36d1d2b7e38fec43a7296b529a2 -Author: Kyungmin Park -Date: Mon Sep 10 11:34:00 2007 +0900 - - Remove compiler warning: target CPU does not support interworking - - Signed-off-by: Kyungmin Park - -commit 1d9e31e04911a6bb7cc66dd91132c699101c32e2 -Author: Wolfgang Denk -Date: Sun Sep 9 21:21:33 2007 +0200 - - Fix compile error in spc1920 config. - - Signed-off-by: Markus Klotzbücher - Signed-off-by: Wolfgang Denk - -commit a7d7eca791a37f452c9da10fef4b31dd7aa9a622 -Author: Grant Likely -Date: Fri Sep 7 09:25:07 2007 -0600 - - Bugfix: make bootm+libfdt compile on boards with no flash - - Signed-off-by: Grant Likely - -commit 6efc1fc0b63e55f94c5bc61d8dd23c918e3bc778 -Author: Grzegorz Bernacki -Date: Fri Sep 7 18:35:37 2007 +0200 - - [PPC440SPe] PCIe environment settings for Katmai and Yucca - - - 'pciconfighost' is set by default in order to be able to scan bridges - behind the primary host/PCIe - - - 'pciscandelay' env variable is recognized to allow for user-controlled - delay before the PCIe bus enumeration; some peripheral devices require a - significant delay before they can be scanned (e.g. LSI8408E); without the - delay they are not detected - - Signed-off-by: Grzegorz Bernacki - -commit 7f1913938984ef6c6a46cb53e003719196d9c5de -Author: Grzegorz Bernacki -Date: Fri Sep 7 18:20:23 2007 +0200 - - [PPC440SPe] Improve PCIe configuration space access - - - correct configuration space mapping - - correct bus numbering - - better access to config space - - Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the - first device on the first bus. We now allow to configure up to 16 buses; - also, scanning for devices behind the PCIe-PCIe bridge is supported, so - peripheral devices farther in hierarchy can be identified. - - Signed-off-by: Grzegorz Bernacki - -commit 15ee4734e4e08003d73d9ead3ca80e2a0672e427 -Author: Grzegorz Bernacki -Date: Fri Sep 7 17:46:18 2007 +0200 - - [PPC440SPe] Convert machine check exceptions handling - - Convert using fixup mechanism to suppressing MCK for the duration of config - read/write transaction: while fixups work fine with the case of a precise - exception, we identified a major drawback with this approach when there's - an imprecise case. In this scenario there is the following race condition: - the fixup is (by design) set to catch the instruction following the one - actually causing the exception; if an interrupt (e.g. decrementer) happens - between those two instructions, the ISR code is executed before the fixup - handler the machine check is no longer protected by the fixup handler as it - appears as within the ISR code. In consequence the fixup approach is being - phased out and replaced with explicit suppressing of MCK during a PCIe - config read/write cycle. - - Signed-off-by: Grzegorz Bernacki - -commit ff7640c9ead8806b5d827f2b29f9cb2632add729 -Author: Wolfgang Denk -Date: Fri Sep 7 17:43:36 2007 +0200 - - Fix typo in MAKEALL script. - - Signed-off-by: Wolfgang Denk - -commit 08e2e5fcd2e06670b62e1680a3934c0e55c72810 -Author: Grzegorz Bernacki -Date: Fri Sep 7 17:09:21 2007 +0200 - - [MPC512x] Proper handling of larger frames in the FEC driver - - When frame larger than local RX buffer is received, it is split and handled - by two buffer descriptors. Prior to this patch the FEC driver discarded - contents of a buffer descriptor without the 'LAST' bit set, so the first - part of the frame was lost in case of larger frames. This fix allows to - safely combine the two pieces into the whole frame. - - Signed-off-by: Grzegorz Bernacki - -commit 8d17979d0359492a822a0a409d26e3a3549b4cd4 -Author: Rafal Jaworowski -Date: Fri Sep 7 17:05:36 2007 +0200 - - [MPC512x] Correct fixup relocation - - Signed-off-by: Rafal Jaworowski - -commit a89cbbd27a60e6740772000fd0688ffba1c2576a -Author: Wolfgang Denk -Date: Fri Sep 7 01:21:25 2007 +0200 - - Update CHANGELOG, minor coding style cleanup. - -commit 5e5803e119de3bebd76fc9a57baac0b5aeccc8a3 -Author: stefano babic -Date: Thu Aug 30 23:01:49 2007 +0200 - - PXA270: Added support for TrizepsIV board. - - This patch add support for the Trizeps IV module (520Mhz). - - Signed-off-by: Stefano Babic - -commit 80172c6181c912fbb34ea3ba0c22b232b419b47f -Author: stefano babic -Date: Thu Aug 30 22:57:04 2007 +0200 - - PXA270: Add support for multiple serial ports. - - This patch adds support for multiple serial ports to the PXA target. - FFUART, BTUART and STUART are supported. - - Signed-off-by: Stefano Babic - -commit 28bb3f72c687ac6b2eb076b01dd21a5fd657d45e -Author: stefano babic -Date: Thu Aug 30 22:48:47 2007 +0200 - - PXA270: fix compile issue (invalid lvalue) - - Code is broken for PXA270 due to "invalid lvalue in assignment". - - This patch fix it in pxa-regs.h - - Signed-off-by: Stefano Babic - -commit 1d2ca446e1a731df420206d04fe278c27ea6b8e8 -Author: Jason Jin -Date: Thu Aug 30 18:19:05 2007 +0800 - - Add BUILD_DIR support for bios emulator. - - Signed-off-by: Jason Jin - -commit b4d8a55145442f136982634862341a3e02002bda -Author: Shinya Kuribayashi -Date: Fri Aug 31 14:41:51 2007 +0900 - - [MIPS] Remove inline asm string functions - - Stop using inline string functions on MIPS as other ARCHs do so, - since the optimized inline asm versions are not small. - - This change is triggered by a following MIPS build error: - common/libcommon.a(exports.o)(.text+0xdc): In function `jumptable_init': - common/exports.c:32: undefined reference to `strcmp' - make: *** [u-boot] Error 1 - - Signed-off-by: Shinya Kuribayashi - -commit 8ea2c4e54833deaebc24c3ca6b7f21353c25b0f5 -Author: Shinya Kuribayashi -Date: Fri Aug 31 14:41:45 2007 +0900 - - [MIPS] Update asm string header - - This patches contains several bugfixes and cleanups in the latest upstream: - - - Don't include linux/config.h - - Remove buggy inline version of memscan. - - Merge with Linux 2.6.11-rc3. - - Fix undefined reference to strcpy in binfmt_misc caused by gcc 3.4. - - Goodbye mips64. 31704 lines of code bite the dust. - - Replace extern inline with static inline. - - Fix return value of strncpy. - - Remove a bunch more "$1" clobbers. - - Signed-off-by: Shinya Kuribayashi - -commit 5b729fb3bd98f49855d6bfc657c3fbae95f2adc2 -Author: Bartlomiej Sieka -Date: Tue Sep 4 17:31:22 2007 +0200 - - Fix do_bootm_linux() so that multi-file images with FDT blob boot. - - Fix incorrect blob address calculation in do_bootm_linux() that prevents - booting the kernel from a multi-file image (kernel + initrd + blob). - - Also, make minor updates to the U-Boot's output and to the coding style. - - Signed-off-by: Bartlomiej Sieka - -commit 041a2554ad619e80dce520c1a33210affcb6a3f2 -Author: Gary Jennejohn -Date: Fri Aug 31 14:29:04 2007 +0200 - - Add support for Sil680 IDE controller. - - o add drivers/sil680.c to support the Sil680 IDE-controller. - o drivers/Makefile: add sil680.o. - - Signed-off-by: Gary Jennejohn - -commit e79021223bc339df655e360645a52c457a74b067 -Author: Grant Likely -Date: Thu Sep 6 09:47:40 2007 -0600 - - bootm/fdt: Only process the fdt if an fdt address was provided - - Boards with CONFIG_OF_LIBFDT enabled are not able to boot old-style - kernels using the board info structure (instead of passing a device tree) - This change allows the old style booting to be used if the fdt argument - was not passed to 'bootm'. - - Signed-off-by: Grant Likely - Acked-by: Kim Phillips - -commit cf2817a84c2e9bea2c5dfc084bce2f2d2563ac43 -Author: Grant Likely -Date: Thu Sep 6 09:46:23 2007 -0600 - - Migrate 5xxx boards from CONFIG_OF_FLAT_TREE to CONFIG_OF_LIBFDT - - Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200 - - Tested on: lite5200b - - Note: the fixup functions have not been moved to a common place. This - patch is targeted for immediate merging as in solves a build issue, but - the final name/location of the fixups is still subject to debate. I - propose to merge this now, and move the fixups in the next merge window - to be usable by all targets. - - Signed-off-by: Grant Likely - -commit 41bb76e941929f54a73206fb132f7a4c275543a3 -Author: Grant Likely -Date: Thu Sep 6 09:46:17 2007 -0600 - - libfdt: add convenience function fdt_find_and_setprop() - - Given the path to a node, fdt_find_and_setprop() allows a property value - to be set directly. - - Signed-off-by: Grant Likely - -commit 80767a6cead9990d9e77e62be947843c2c72f469 -Author: Peter Pearse -Date: Wed Sep 5 16:04:41 2007 +0100 - - Changed API name to coloured_led.h - Removed code using deprecated ifdef CONFIG_BOOTBINFUNC - Tidied other cpu/arm920t/start.S code - -commit 56a9270521baaa00e12639a978302a67f61ef060 -Author: Kumar Gala -Date: Thu Aug 30 16:18:18 2007 -0500 - - Fix ULI RTC support on MPC8544 DS - - The RTC on the M1575 ULI chipset requires a dummy read before - we are able to talk to the RTC. We accomplish this by adding a - second memory region to the PHB the ULI is on and read from it. - - The second region is added to maintain compatiabilty with Linux's - view of the PCI memory map. - - Signed-off-by: Kumar Gala - -commit f75e89e9b5714db2b0e80074071dfbdd6f59488a -Author: Ed Swarthout -Date: Thu Aug 30 01:58:48 2007 -0500 - - ft_board_setup update 85xx/86xx of pci/pcie bus-range property. - - pcie is now differentiated from pci. Add 8641 bus-range updates. - - Signed-off-by: Ed Swarthout - -commit 9f5c3d3720e777a572dcdc8af2008b44c7243885 -Author: Peter Pearse -Date: Tue Sep 4 16:18:38 2007 +0100 - - Add coloured led interface for ARM boards. - Use it in cpu/arm920t/start.S to indicate U-Boot code has been entered. - -commit 7462fe0d5a9d40cde083fb1a3cd73911996b5ecb -Author: Peter Pearse -Date: Tue Sep 4 14:49:28 2007 +0100 - - Move include/led.h to board/at91rm9200dk - -commit 6e4bf9b24e57c15abc6542e685d06380bc64af27 -Author: Peter Pearse -Date: Tue Sep 4 14:25:51 2007 +0100 - - Ran Lindent on drivers/at45.c - -commit 557ab89d294f08dd532f21d19861b40093200a33 -Author: Peter Pearse -Date: Tue Sep 4 14:23:50 2007 +0100 - - Rename CONFIG_CMD_MUX to CONFIG_CMD_AT91_SPIMUX - -commit 81b73dec16fd1227369a191e725e10044a9d56b8 -Author: Gary Jennejohn -Date: Fri Aug 31 15:21:46 2007 +0200 - - ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia - - The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is - set to non-zero, because it doesn't support MRM (memory-read- - multiple) correctly. We now added the possibility to configure - this register in the board config file, so that the default value - of 8 can be overridden. - - Here the details of this patch: - - o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow - board-specific settings. As an example the sequoia board requires 0. - Idea from Stefan Roese . - o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the - PCI IO-space. Obtained from Stefan Roese . - o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set - CFG_PCI_CACHE_LINE_SIZE to 0. - - Signed-off-by: Gary Jennejohn - Signed-off-by: Stefan Roese - -commit 60174746c668b309378a91488dded898e9553eae -Author: Wolfgang Denk -Date: Fri Aug 31 10:01:51 2007 +0200 - - Fix TFTP OACK code for short packets. - - The old code had a loop limit overflow bug which caused a semi- - infinite loop for small packets, because in "i - -commit 696dd1307cd8e73a10e9bb3c51731bfd6f837bee -Author: Hans-Christian Egtvedt -Date: Thu Aug 30 15:03:05 2007 +0200 - - Reduce BOOTDELAY variable to 1 second by default for STK1002 - - Signed-off-by: Hans-Christian Egtvedt - Signed-off-by: Haavard Skinnemoen - -commit c88b6e1cbf9a8ae2a34fb602f78a1bf4e6692b6a -Author: Hans-Christian Egtvedt -Date: Thu Aug 30 15:03:04 2007 +0200 - - Remove double quotation marks around MAC address for STK1002 - - Signed-off-by: Hans-Christian Egtvedt - Signed-off-by: Haavard Skinnemoen - -commit ff13ac8c7bbebb238e339592de765c546dba1073 -Author: Wolfgang Denk -Date: Thu Aug 30 14:42:15 2007 +0200 - - Backout commit 8f1bc284 as it causes TFTP to fail. - - Signed-off-by: Wolfgang Denk - -commit 1900fbf255acba8b94fb442a16408ea85a1d46a6 -Author: Ed Swarthout -Date: Thu Aug 30 02:26:17 2007 -0500 - - Revert "Fix MPC8544DS PCIe3 scsi." - - This reverts commit 9468e680. - Commit 16e23c3f5da removing allocation of PCSRBAR is sufficient. - - Signed-off-by: Ed Swarthout - -commit 8f1bc28408ded213418d9bc0780c7d8fb8a03774 -Author: Grant Likely -Date: Wed Aug 29 18:26:24 2007 -0600 - - tftp: don't implicity trust the format of recevied packets - - The TFTP OACK code trusts that the incoming packet is formated as - ASCII text and can be processed by string functions. It also has a - loop limit overflow bug where if the packet length is less than 8, it - ends up looping over *all* of memory to find the 'blksize' string. - - This patch solves the problem by forcing the packet to be null - terminated and using strstr() to search for the sub string. - - Signed-off-by: Grant Likely - -commit 04625764cc93ce8a61625ac19d7fe2a2ceee8143 -Author: Stefan Roese -Date: Wed Aug 29 16:31:18 2007 +0200 - - ppc4xx: Change lwmon5 default environment to support Linux RTC - - The Linux PCF8563 RTC driver doesn't do autoprobing, so we need - to supply the RTC I2C address as bootline parameter. This patch - adds support for this rtc probing parameter to the bootargs: - - "rtc-pcf8563.probe=0,0x51" - - Signed-off-by: Stefan Roese - -commit 2602a5c40ae37ab965a4e240854fdaffb51328a4 -Author: Kim Phillips -Date: Wed Aug 29 09:06:05 2007 -0500 - - sbc8641: remove unused OF_FLAT_TREE_MAX_SIZE - - this had slipped through the cracks, since the sbc board was added - after I wrote the original patch to remove all these symbols, and - before it was merged. - - Signed-off-by: Kim Phillips - -commit c5bded3c88e48ae648a75d357dc81a8255fa81f1 -Author: Wolfgang Denk -Date: Wed Aug 29 14:05:30 2007 +0200 - - Add mii_init() prototype - - to get rid of a *lot* of compiler warnings. - - Signed-off-by: Wolfgang Denk - -commit 2d1f23aa1e74e4a8f8ffa67f246eb98c522dfd7f -Author: Wolfgang Denk -Date: Wed Aug 29 13:35:03 2007 +0200 - - Disable network support on cmi_mpc5xx board - - ..because it caused compiler errors and there seems to be no - board maintainer to take care of this. - - Signed-off-by: Wolfgang Denk - -commit 9468e6804b7e25b0f6f52e53f47bce3175400a16 -Author: Kumar Gala -Date: Mon Aug 20 09:44:00 2007 -0500 - - Fix MPC8544DS PCIe3 scsi. - - - - The problem is pciauto_setup_device() getting called from fsl_pci_init.c - is allocating memory space it doesn't need. - - Signed-off-by: Ed Swarthout - Signed-off-by: Andy Fleming - -commit 4bf4abb8a4e9955556b120a1aafa30c03e74032a -Author: Ed Swarthout -Date: Tue Aug 21 09:38:59 2007 -0500 - - 8548cds fixes - - Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the - correct consoledev needed for linux boot. - Standardize on fdt{file,addr} var to hold dtb file name. - - Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}. - - Signed-off-by: Ed Swarthout - -commit 7a1ac419fa0d2d23ddd08bd61d16896a9f33c933 -Author: Haiying Wang -Date: Thu Aug 23 15:20:54 2007 -0400 - - Enable L2 cache for MPC8568MDS board - - The L2 cache size is 512KB for 8568, print out the correct informaiton. - - Signed-off-by: Haiying Wang - -commit 94c47fdaf14cb29fa3fb4d4da2efdd96c803b46b -Author: Jason Jin -Date: Wed Aug 22 17:54:49 2007 +0800 - - Remove the bios emulator binary files from MAI board - - Signed-off-by: Jason Jin - -commit 7608d75f9c87c9eb5b3a43219d0506d3e979a13f -Author: Kim Phillips -Date: Tue Aug 21 17:00:17 2007 -0500 - - support board vendor-common makefiles - - if a board/$(VENDOR)/common/Makefile exists, build it. - - also add the first such case, board/freescale/common/Makefile, to - handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as - dictated by board configuration. - - thusly get rid of alternate build dir errors such as: - - FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory - - by putting the common/ mkdir command in its proper place (the common - Makefile). Common bits from existing individual board Makefiles have - been removed. - - Signed-off-by: Kim Phillips - -commit ef8f20752712dc1cdbd86f47e3bd6e35f81c83fd -Author: stefano babic -Date: Tue Aug 21 15:52:33 2007 +0200 - - Fix: TFTP is not working on little endian systems - - TFTP does not work anymore after multicast tftp - patch was applied on little endian systems. - This patch fix it. - - Signed-off-by: Stefano Babic - -commit 5f470948570526e9186f053a3003da7719604e90 -Author: stefano babic -Date: Tue Aug 21 15:50:33 2007 +0200 - - Fix MAC address setting in DM9000 driver. - - The logic to check if there is a correct MAC address in the DM9000 - EEPROM, added in the last patch, is wrong. Now the MAC address is - always taken from the environment, even if a suitable MAC is present - in the EEPROM. - - Signed-off-by: Stefano Babic - -commit 4a8527ef086ec7c89f40674ef024ae6f988a614a -Author: Martin Krause -Date: Tue Aug 21 12:40:34 2007 +0200 - - MPC5xxx: fix some compiler warnings in USB code - - Fix the following warnings: - - usb.c:xx: warning: function declaration isn't a prototype - - usb_ohci.c:xxx: warning: passing argument 1 of '__fswab32' makes integer - from pointer wihtout a cast - - Signed-off-by: Martin Krause - -commit 16e23c3f5dab6937f5109365416808c7f15c122b -Author: Ed Swarthout -Date: Mon Aug 20 23:55:33 2007 -0500 - - fsl_pci_init - Remove self PCSRBAR allocation - - CPU physical address space was being wasted by allocating a - PCSRBAR PCI inbound region to it's memory space. - - As a rule, PCSRBAR should be left alone since it does not affect - transactions from self and other masters may have changed it. - - Signed-off-by: Ed Swarthout - -commit 0e700ce03a23bb1921149bc77008ace7103d5289 -Author: Martin Krause -Date: Mon Aug 20 13:56:47 2007 +0200 - - Fix compiler warning in include/s3c2410.h - - This patch fixes the "type qualifiers ignored on fuction return tpye" - warning for include/s3c2410.h - - Signed-off-by: Martin Krause - -commit 9bb8b209ed2058a5756ecbeb544c067e44a42aea -Author: Dirk Behme -Date: Mon Aug 20 07:09:05 2007 +0200 - - Fix compilation error for omap2420h4_config. - - omap2420h4 switched to cfi, so remove old (already disabled) flash.c - and flash_probe() calls in env_flash.c. - - Signed-off-by: Dirk Behme - -commit 3bb342fc85d79dbb6b8c2039e7cdcddc82b8d90f -Author: Kim Phillips -Date: Fri Aug 10 14:34:14 2007 -0500 - - fdt: remove unused OF_FLAT_TREE_MAX_SIZE references - - and make some minor corrections to the FDT part of the README. - - Signed-off-by: Kim Phillips - -commit 6af2eeb1e99c2dcc584d4c5ab7fcae30a325f4de -Author: Wolfgang Denk -Date: Wed Aug 29 01:32:05 2007 +0200 - - Minor coding style cleanup. - - Signed-off-by: Wolfgang Denk - -commit a861558c65f65f1cf1302f3a35e9db7686b9e1a3 -Author: Heiko Schocher -Date: Tue Aug 28 17:40:33 2007 +0200 - - [UC101] Fix: if no CF in the board, U-Boot resets sometimes. - - Signed-off-by: Heiko Schocher - -commit f98984cb194bb34dbe1db9429d3b51133af30d07 -Author: Heiko Schocher -Date: Tue Aug 28 17:39:14 2007 +0200 - - IDE: - make ide_inb () and ide_outb () "weak", so boards can - define there own I/O functions. - (Needed for the pcs440ep board). - - The default I/O Functions are again 8 Bit accesses. - - Added CONFIG_CMD_IDE for the pcs440ep Board. - - Signed-off-by: Heiko Schocher - -commit 2c05fd125744981e5f2828d24e66ccc20a77d25d -Author: Semih Hazar -Date: Mon Aug 20 19:00:01 2007 +0300 - - AVR32: Change prototype of memset - - Signed-off-by: Semih Hazar - Signed-off-by: Haavard Skinnemoen - -commit 9c02defc29b57945b600714cf61ddfd02b02fb14 -Author: Yuri Tikhonov -Date: Sat Aug 25 05:07:16 2007 +0200 - - POST: limit memory test area to not touch global data anymore - - As experienced on lwmon5, on some boards the POST memory test can - corrupt the global data buffer (bd). This patch fixes this issue - by checking and limiting this area. - - Signed-off-by: Yuri Tikhonov - Signed-off-by: Stefan Roese - -commit 75e1a84d483e36be10e206e539b028c4889e1158 -Author: Stefan Roese -Date: Fri Aug 24 15:41:42 2007 +0200 - - ppc4xx: Add RTC POST test to lwmon5 board configuration - - Since this RTC POST test is taking quite a while to complete - it's only initiated upon special keypress same as the complete - memory POST. - - Signed-off-by: Stefan Roese - -commit d7bfa620037a6d2210159387571bdf93aa32c162 -Author: Stefan Roese -Date: Fri Aug 24 15:19:10 2007 +0200 - - ppc4xx: Change GPIO signal for watchdog triggering on lwmon5 - - Signed-off-by: Stefan Roese - -commit c25dd8fc25e9ca3695db996a257d9ba4dab414db -Author: Stefan Roese -Date: Thu Aug 23 11:02:37 2007 +0200 - - ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 board - - This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5 - board. Now the "eeprom" command can be used to read/write from/to this - device. Additionally a new command was added "eepromwp" to en-/disable - the write-protect of this 2nd EEPROM. - - The 1st EEPROM is not affected by this write-protect command. - - Signed-off-by: Stefan Roese - -commit c64fb30e4c5976007d56fc1789c7a0666082b536 -Author: Stefan Roese -Date: Wed Aug 22 08:56:09 2007 +0200 - - ppc4xx: Remove unused option CFG_INIT_RAM_OCM - - Signed-off-by: Stefan Roese - -commit 3ad63878737a5a2b1e60825bf0a7d601d7a695e7 -Author: Stefan Roese -Date: Tue Aug 21 16:27:57 2007 +0200 - - ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based) - - This patch adds support for the matrix keyboard on the lwmon5 board. - Since the implementation in the dsPCI is kind of compatible with the - "old" lwmon board, most of the code is copied from the lwmon - board directory. - - Signed-off-by: Stefan Roese - -commit 3e66c078003607a7d1d214c15a5f262bc1b4032f -Author: Wolfgang Denk -Date: Sun Aug 19 10:27:34 2007 +0200 - - Fix some build errors. - - Signed-off-by: Wolfgang Denk - -commit 05675735ef77dc23b5e0eb782bad1ff477b55e86 -Author: Wolfgang Denk -Date: Sat Aug 18 22:00:38 2007 +0200 - - Update CHANGELOG. - -commit 79f240f7ecc0506b43ac50d1ea405ff6540d4d57 -Author: Kim Phillips -Date: Thu Aug 16 22:52:39 2007 -0500 - - lib_ppc: make board_add_ram_info weak - - platforms wishing to display RAM diagnostics in addition to size, - can do so, on one line, in their own board_add_ram_info() - implementation. - - this consequently eliminates CONFIG_ADD_RAM_INFO. - - Thanks to Stefan for the hint. - - Signed-off-by: Kim Phillips - -commit 815b5bd5b18569917c3e04b9757511e6ed23b9f6 -Author: Shinya Kuribayashi -Date: Fri Aug 17 12:43:44 2007 +0900 - - PCI_READ_VIA_DWORD_OP: Fix *val uninitialized bug - - This patch has been sent on: - - 6 Jun 2007 - - Many users of PCI config read routines tend to ignore the function - ret value, and are only concerned about the contents of *val. Based - on this, pci_hose_read_config_{byte,word}_via_dword should initialize - the *val on dword read error. - - Without this fix, for example, we'll go on scanning bus with vendor or - header_type uninitialized. This brings many unnecessary config trials. - - Signed-off-by: Shinya Kuribayashi - -commit 26667b7fa05a8bf2fc65fb9f3230b02b1a10c367 -Author: Stefan Roese -Date: Sat Aug 18 14:37:52 2007 +0200 - - ColdFire: Fix some remaining problems with CFG_CMD_ - - Signed-off-by: Stefan Roese - -commit 8280f6a1c43247616b68224675188e5ccd124650 -Author: Stefan Roese -Date: Sat Aug 18 14:33:02 2007 +0200 - - Coding style cleanup - - Signed-off-by: Stefan Roese - -commit 4a442d3186b31893b4f77c6e82f63c4517a5224b -Author: TsiChungLiew -Date: Thu Aug 16 19:23:50 2007 -0500 - - ColdFire: Add M5235EVB Platform for MCF523x - - Signed-off-by: TsiChungLiew - -commit 4cc1cd5941827a04cf5c51a07fcc42e8945894aa -Author: Kim Phillips -Date: Fri Aug 17 09:30:00 2007 -0500 - - mpc83xx: fix typo in DDR2 programming - - introduced in the implement board_add_ram_info patch as I was cleaning out the - magic numbers. sorry. - - Signed-off-by: Kim Phillips - -commit e58fe95784d2514fc9c21028dc59f2b319a35d80 -Author: Kim Phillips -Date: Thu Aug 16 22:53:09 2007 -0500 - - mpc83xx: move freescale boards to boards/freescale - - includes build fixes. - - Signed-off-by: Kim Phillips - -commit 5aa4ad8d8e7e9468219990c7875d5fdc9e962f47 -Author: Kim Phillips -Date: Thu Aug 16 22:52:59 2007 -0500 - - mpc83xx: suppress unused variable 'val8' warning - - Signed-off-by: Kim Phillips - -commit bbea46f76f767b919070b4829bf34c86bd223248 -Author: Kim Phillips -Date: Thu Aug 16 22:52:48 2007 -0500 - - mpc83xx: implement board_add_ram_info - - add board_add_ram_info, to make memory diagnostic output more - consistent. u-boot banner output now looks like: - - DRAM: 256 MB (DDR1, 64-bit, ECC on) - - and for boards with SDRAM on the local bus, a line such as this is - added: - - SDRAM: 64 MB (local bus) - - also replaced some magic numbers with their equivalent define names. - - Signed-off-by: Kim Phillips - -commit 14778585d1389d86d5846efec29e5fce892680ce -Author: Tony Li -Date: Fri Aug 17 10:35:59 2007 +0800 - - mpc83xx: Split PIB init code from pci.c and add Qoc3 ATM card support - - The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c - And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board. - - Signed-off-by Tony Li - -commit 8ae158cd87a4a25722b27835261b6ff0fa2aa6a7 -Author: TsiChungLiew -Date: Thu Aug 16 15:05:11 2007 -0500 - - ColdFire: Add M54455EVB for MCF5445x - - Signed-off-by: TsiChungLiew - -commit a1436a842654a8d3927d082a8ae9ee0a10da62d7 -Author: TsiChungLiew -Date: Thu Aug 16 13:20:50 2007 -0500 - - ColdFire: Add M5253EVBE platform for MCF52x2 - - Signed-off-by: TsiChungLiew - -commit a605aacd8324094199402816cc6d9124aba57b8d -Author: TsiChungLiew -Date: Thu Aug 16 05:04:31 2007 -0500 - - ColdFire: Add M5249EVB platform for MCF52x2 - - Signed-off-by: TsiChungLiew - -commit f28e1bd9daa6de5eb33ae4822bda6b008ccb4e9e -Author: TsiChungLiew -Date: Wed Aug 15 20:32:06 2007 -0500 - - ColdFire: Update Freescale MCF52x2 platforms - - Signed-off-by: TsiChungLiew - -commit 870470dbf6f4bb9864e0d97aeedbc17c167c6d1c -Author: TsiChungLiew -Date: Wed Aug 15 19:55:10 2007 -0500 - - ColdFire: Update EB+MCF-EV123 platform - - Signed-off-by: TsiChungLiew - -commit aa93d859d9b1fcd8eea52d51b06e86c38f72111b -Author: TsiChungLiew -Date: Wed Aug 15 19:46:38 2007 -0500 - - ColdFire: update TASREG platform for MCF52x2 - - Signed-off-by: TsiChungLiew - -commit a9505510bf56a9b5558248dd8b73ec9d9a1556a2 -Author: TsiChungLiew -Date: Wed Aug 15 19:45:51 2007 -0500 - - ColdFire: update r5200 platform for MCF52x2 - - Signed-off-by: TsiChungLiew - -commit 6cfd3c7bc813fb317ab7c0781f0d1874b1c0877c -Author: TsiChungLiew -Date: Wed Aug 15 19:43:20 2007 -0500 - - ColdFire: idmr platform MCF52x2 update - - Signed-off-by: TsiChungLiew - -commit 6706424d0bb851fb52af00cd1c3301e91ee7f2b0 -Author: TsiChungLiew -Date: Wed Aug 15 19:41:06 2007 -0500 - - ColdFire: cobra5272 platform for MCF52x2 update - - Signed-off-by: TsiChungLiew - -commit 56115665b4a64c10c01440c57749b265e0908fa4 -Author: TsiChungLiew -Date: Wed Aug 15 19:38:15 2007 -0500 - - ColdFire: MCF52x2 Header files update - - Signed-off-by: TsiChungLiew - -commit 83ec20bc4380eebddfde45da6e3a69a92d4db21d -Author: TsiChungLiew -Date: Wed Aug 15 19:21:21 2007 -0500 - - ColdFire: MCF52x2 update - - Signed-off-by: TsiChungLiew - -commit f52e78304dcc0ac459c0ea1fa5be275c7d1642cf -Author: TsiChungLiew -Date: Wed Aug 15 18:46:11 2007 -0500 - - ColdFire: MCF5329 update cache - - Signed-off-by: TsiChungLiew - -commit 7171977fb8fd77cfb6676953fa9a05789c450513 -Author: TsiChungLiew -Date: Wed Aug 15 15:40:20 2007 -0500 - - ColdFire: MCF5329 header file clean up - - Signed-off-by: TsiChungLiew - -commit ab77bc547ba561c25ea34457ed17aa0b2f7c2723 -Author: TsiChungLiew -Date: Wed Aug 15 15:39:17 2007 -0500 - - ColdFire: MCF5329 Update and cleanup - - Signed-off-by: TsiChungLiew - -commit 10327dc5541f947c0cf7e31fef86c4706169607a -Author: Andy Fleming -Date: Thu Aug 16 16:35:02 2007 -0500 - - Add CONFIG_HAS_ETH0 to all boards with TSEC - - The 85xx code now relies on CONFIG_HAS_ETH0 to determine whether - to update TSEC1's device-tree node, so we need to add it - to all the boards with TSECs. Do this for 83xx and 86xx, too, - since they will eventually do something similar. - - Signed-off-by: Andy Fleming - -commit d64ee908a1b525e5bb2b4cbeb5c449ad6a469666 -Author: Kumar Gala -Date: Thu Aug 16 15:05:04 2007 -0500 - - Update MPC8544 DS PCI memory map - - The PCIe bus that the ULI M1575 is connected to has no possible way of - needing more than the fixed amount of IO & Memory space needed by the ULI. - - So make it use far less IO & memory space and have it use the shared LAW. This - free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed - by each bus. - - Signed-off-by: Kumar Gala - -commit ea5877e31ed63ade948fd1293895ec23fe01472e -Author: Kumar Gala -Date: Thu Aug 16 11:01:21 2007 -0500 - - Fix up some fdt issues on 8544DS - - It looks like we had a merge issue that duplicated a bit of code - in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get - the MAC address properly set in the device tree on boot for TSEC1 - - Signed-off-by: Kumar Gala - -commit 07bc20560cb9d3d186cca268c05c82762e8c55ad -Author: Niklaus Giger -Date: Thu Aug 16 15:16:03 2007 +0200 - - PPC4xx:HCU4/5 cleanup - - Minor cleanups to confirm to the u-boot coding style. - Some german expressions -> english. - HCU5 enforces a unique IP adress for a given slot in the rack. - - Signed-off-by: Niklaus Giger - -commit 1e6b07c64967c1eb2cd84faa4c32bf2a769bc8eb -Author: Niklaus Giger -Date: Thu Aug 16 15:16:02 2007 +0200 - - PPC4xx:HCU4/5 cleanup ecc/sdram init - - Make ecc initialisation robust, as DDR2-ECC errors may be generated - while zeroing the RAM. - - Return 16 bytes (a cacheline) less than the available memory, as the - board and/or PPC440EPx might have problems accessing the last bytes. - - Signed-off-by: Niklaus Giger - -commit d35b508a55508535b6e8445b718585d27df733d3 -Author: Kim Phillips -Date: Wed Aug 15 22:29:56 2007 -0500 - - fdt: suppress unused variable 'bd' warning - - Signed-off-by: Kim Phillips - -commit 82bd9ee77490588d4da785d75829ca63d0176baf -Author: Andy Fleming -Date: Wed Aug 15 20:06:50 2007 -0500 - - Fix warnings from of_data copy fix - - Forgot to cast of_flat_tree to ulong. - - Signed-off-by: Andy Fleming - -commit 7613afda77d5eec0f47d303025b0c661b70e4c73 -Author: Andy Fleming -Date: Wed Aug 15 20:03:44 2007 -0500 - - Don't wait for disconnected TSECs - - The TSEC driver's PHY code waits a long time for autonegotiation to - complete, even if the link is down. The PHY knows the link is - down or up before autonegotiation completes, so we can short-circuit - the process if the link is down. - - Signed-off-by: Andy Fleming - -commit b96c83d4ae475a70ef2635cd0e748174c44c8601 -Author: Andy Fleming -Date: Wed Aug 15 20:03:34 2007 -0500 - - Fix numerous bugs in the 8568 UEC support - - Actually, fixed a large bug in the UEC for *all* platforms. - How did this ever work? - - uec_init() did not follow the spec for eth_init(), and returned - 0 on success. Switch it to return the link like tsec_init() - (and 0 on error) - - The immap for the 8568 was defined based on MPC8568, rather than - CONFIG_MPC8568 - - CONFIG_QE was off - - CONFIG_ETHPRIME was set to "Freescale GETH". Now is "FSL UEC0" - - Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is - enabled - - Signed-off-by: Andy Fleming - -commit 3a79013e2adda53332dfd0b511066a805e929a9d -Author: Andy Fleming -Date: Wed Aug 15 20:03:25 2007 -0500 - - Define tsec flag values in config files - - The tsec_info structure and array has a "flags" field for each - ethernet controller. This field is the only reason there are - settings. Switch to defining TSECn_FLAGS for each controller - in the config header, and we can greatly simplify the array, and - also simplify the addition of future boards. - - Signed-off-by: Andy Fleming - -commit ec7238229507e7f47533a611ea8c53319d234cf3 -Author: Andy Fleming -Date: Wed Aug 15 20:03:13 2007 -0500 - - Add support for building all boards with a TSEC - - Changes to the TSEC driver affect almost all 83xx, 85xx, and 86xx boards. - Now we can do a MAKEALL test on all of them! - - Signed-off-by: Andy Fleming - -commit 10aaf716cb0dc6614df54ef78bed5144afd23ef8 -Author: Andy Fleming -Date: Wed Aug 15 17:30:56 2007 -0500 - - Fix of_data copying for CONFIG_OF_FLAT_TREE-using boards - - The fix, "Fix where the #ifdef CFG_BOOTMAPSZ is placed" - neglected to *also* put the code inside the similar #ifdef - for CONFIG_OF_FLAT_TREE. - - Signed-off-by: Andy Fleming - -commit 78f9fef7f406078c8bf7191e665a73f795157746 -Author: Scott Wood -Date: Wed Aug 15 15:46:46 2007 -0500 - - mpc885ads: Don't define CONFIG_BZIP2. - - bzip2 requires a significant chunk of malloc space, and there isn't - enough room on mpc885ads (with only 8MB RAM) for both bzip2's malloc area - and a downloaded image at 0x400000. - - Signed-off-by: Scott Wood - -commit 002275a3ed8b114885f6702d6d544d0780dfe689 -Author: Michal Simek -Date: Thu Aug 16 08:54:10 2007 +0200 - - Bios emulator - fix microblaze toolchain problem - - microblaze CPU have problem with bios_emulator code. - Microblaze toolchain doesn't support PRAGMA PACK. - - Signed-off-by: Michal Simek - -commit a5a38f4fd7e5366d706ff6a985f9b6715ddbc98b -Author: Wolfgang Denk -Date: Thu Aug 16 11:51:04 2007 +0200 - - Minor Coding Style fix; Update CHANGELOG file. - - Signed-off-by: Wolfgang Denk - -commit 8fb6e80c06849e3013ac5c9350d8ed9e52967991 -Author: Stefan Roese -Date: Thu Aug 16 11:21:49 2007 +0200 - - ppc4xx: Remove #warning in esd auto_update.c - - Signed-off-by: Stefan Roese - -commit 2d78074d2e806edc380c1464eb9e5df335ece65e -Author: Stefan Roese -Date: Fri Jun 22 17:32:28 2007 +0200 - - ppc7xx: Update CPCI750 board - - This small CPCI750 update extends the board specific command - "show_config" to display the Marvell strapping registers and - extends the PCI IDE controller. - - Signed-off-by: Reinhard Arlt - Signed-off-by: Stefan Roese - -commit 78cff50edba6b1508eb15c2f53ce966ac891eb9e -Author: Michal Simek -Date: Thu Aug 16 10:46:28 2007 +0200 - - [FIX] Changes for bios_emulator code for others architecture - -commit 6e0e2253f039344f8ebd2787285fdba90e6714e8 -Author: Michal Simek -Date: Thu Aug 16 10:45:09 2007 +0200 - - [FIX] Remove unused include file - -commit 9de469bd960cc1870bb40d6672ed42726b8b50d7 -Author: Stefan Roese -Date: Thu Aug 16 10:18:33 2007 +0200 - - ppc4xx: Only enable POST FPU test on Sequoia and not Rainier - - Signed-off-by: Stefan Roese - -commit 6da0c5bd4a53e40eb4f7eb72a4c051ecabad783c -Author: Stefan Roese -Date: Thu Aug 16 09:54:51 2007 +0200 - - Add missing rainier (PPC440GRx) target to MAKEALL and MAINTAINERs files - - Signed-off-by: Stefan Roese - -commit 02ba7022f62bb75908296c58c63866e1d294b69a -Author: Stefan Roese -Date: Thu Aug 16 09:52:29 2007 +0200 - - ppc4xx: Update Sequoia/Rainier bootstrap command - - As suggested by David Mitchell, here an update for the Sequoia/Rainier - bootstrap command. - - Signed-off-by: Stefan Roese - -commit 35cc4e4823668e8745854899cfaedd4489beb0ef -Author: Kim Phillips -Date: Wed Aug 15 22:30:39 2007 -0500 - - mpc83xx: enable libfdt by default on freescale boards - - this enables libfdt code by default for the - freescale mpc8313erdb, mpc832xemds, mpc8349emds, - mpc8349itx and gp boards. - - Signed-off-by: Kim Phillips - -commit 3fde9e8b22cfbd7af489214758f9839a206576cb -Author: Kim Phillips -Date: Wed Aug 15 22:30:33 2007 -0500 - - mpc83xx: migrate remaining freescale boards to libfdt - - this adds libfdt support code for the freescale - mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx, - and gp boards. - - Boards remain compatible with OF_FLAT_TREE. - - Signed-off-by: Kim Phillips - -commit 6a16e0dfcc4119b46adb1dce2d6c8fb3c5d108e1 -Author: Kim Phillips -Date: Wed Aug 15 22:30:26 2007 -0500 - - mpc83xx: move common /memory node update mechanism to cpu.c - - also adds common prototypes to include/common.h. - - Signed-off-by: Kim Phillips - -commit 8f9e0e9f339aee4ce31a338d5f27356eb5457f85 -Author: Kim Phillips -Date: Wed Aug 15 22:30:19 2007 -0500 - - mpc83xx: remaining 8360 libfdt fixes - - PCI clocks and QE frequencies weren't being updated, and the core clock - was being updated incorrectly. This patch also adds a /memory node if - it doesn't already exist prior to update. - - plus some cosmetic trimming to single line comments. - - Signed-off-by: Kim Phillips - -commit f4b2ac5ed9aaff9920d487bff8a59696c083a524 -Author: Kim Phillips -Date: Wed Aug 15 22:30:12 2007 -0500 - - mpc83xx: fix UEC2->1 typo in libfdt setup code - - Signed-off-by: Kim Phillips - -commit 19fa1c35368484d4ed10ddce8a7793c21862e3a3 -Author: Kim Phillips -Date: Wed Aug 15 22:30:05 2007 -0500 - - mpc83xx: add MAINTAINER and MAKEALL entries for the mpc8323erdb - - and reorder the existing 83xx maintainers alpha. - - Signed-off-by: Kim Phillips - -commit 5b4de9309d7a03aa1db2e5391ab696363391f460 -Author: Michal Simek -Date: Wed Aug 15 21:15:05 2007 +0200 - - [FIX] Resolve problem with warnings - microblaze toolchain don't support PRAGMA PACK. - -commit d1ed28cf36ab6b1d4c479809de7252bf53d2f2d4 -Author: Michal Simek -Date: Wed Aug 15 21:05:07 2007 +0200 - - [FIX] Correction command setting for Microblaze boards - -commit 7aa63d8cd30ab20ac2fd1ab86e60471de8b1f1e5 -Author: Michal Simek -Date: Wed Aug 15 21:03:41 2007 +0200 - - [FIX] Correction command definition - -commit 30b52df9e906bf0e465916c2c6bb5192b438e0b8 -Author: Jon Loeliger -Date: Wed Aug 15 11:55:35 2007 -0500 - - 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h - - Remove a leftover in net/tftp.c while we're at it. - - Signed-off-by: Jon Loeliger - -commit 4ce917742b1e48faa9bf9a9757545e56fb4cfe44 -Author: Jon Loeliger -Date: Wed Aug 15 12:20:40 2007 -0500 - - Move the MPC8641HPCN board under board/freescale. - - Minor path corrections needed to ensure buildability. - - Signed-off-by: Jon Loeliger - -commit 8662577fe36fdb6a44b55b998d9daac6392a736a -Author: Jon Loeliger -Date: Wed Aug 15 11:46:22 2007 -0500 - - 86xx: Fix lingering CFG_CMD_* references in sbc8641d.h - - Remove a leftover in net/tftp.c while we're at it. - - Signed-off-by: Jon Loeliger - -commit 210f463c71917b7a4495c2103c228b9c179ae64d -Author: Jerry Van Baren -Date: Wed Aug 15 11:13:15 2007 -0400 - - Fix where the #ifdef CFG_BOOTMAPSZ is placed. - - Commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 "Fix initrd/dtb - interaction" put the new code outside of the #if defined(CONFIG_OF_LIBFDT) - when it should have gone inside of the conditional. As a result, it - broke non-LIBFDT board builds. - - Also added a missing "not." to the comment. - - Signed-off-by: Gerald Van Baren - -commit 0e19209767194a97cec6d93dba9e64d1da8d548e -Author: Niklaus Giger -Date: Wed Aug 15 12:14:23 2007 +0200 - - PPC4xx:HCU4/5-Board fix compile warning - - Signed-off-by: Niklaus Giger - -commit 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7 -Author: Ed Swarthout -Date: Tue Aug 14 14:06:45 2007 -0500 - - Fix malloc size error in ahci_init_one. - - Typically this causes scsi init to corrupt the - devlist and break the coninfo command. - Fix a compiler size warning. - - Signed-off-by: Jason Jin - Signed-off-by: Ed Swarthout - Acked-by: Andy Fleming - -commit b361acd64fd2525c081b9b288b0804efe209c0e9 -Author: ksi@koi8.net -Date: Tue Aug 14 10:02:16 2007 -0700 - - TI DaVinci - fix unsupported %hhx format - - Signed-off-by: Sergey Kubushyn - -commit f01dbb5424a81453c81190dd30e945891466f621 -Author: Wolfgang Denk -Date: Tue Aug 14 18:42:36 2007 +0200 - - Coding style cleanup. Update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit 073e1b509980cefe6f53c2d7fbbcd135df1e3924 -Author: Andy Fleming -Date: Tue Aug 14 10:32:59 2007 -0500 - - Fix initrd/dtb interaction - - The original code would wrongly relocate the blob to be right before - the initrd if it existed. The blob *must* be within CFG_BOOTMAPSZ, - if it is defined. So we make two changes: - - 1) flag the blob for relocation whenever its address is above BOOTMAPSZ - - 2) If the blob is being relocated, relocate it before kbd, not initrd - - Signed-off-by: Andy Fleming - -commit e54b970173769307a116bd34028b6d0c2eea2a4e -Author: Peter Pearse -Date: Tue Aug 14 15:40:00 2007 +0100 - - Supply spi interface in at45.c - -commit 4ce846ec59f36b85d6644a769690ad3feb667575 -Author: Stefan Roese -Date: Tue Aug 14 15:12:01 2007 +0200 - - POST: Fix merge problem - - Signed-off-by: Stefan Roese - -commit 429d9571f60631ae8a2fe12b11be4c75b0c2b37c -Author: Stefan Roese -Date: Tue Aug 14 15:03:17 2007 +0200 - - Coding style cleanup - - Signed-off-by: Stefan Roese - -commit 779e975117a75e91fcebe226a63104dbfb924ab1 -Author: Stefan Roese -Date: Tue Aug 14 14:44:41 2007 +0200 - - ppc4xx: Add initial Zeus (PPC405EP) board support - - Signed-off-by: Stefan Roese - -commit c5a172a5fd636c12467429e3f7910e53773979c6 -Author: Stefan Roese -Date: Tue Aug 14 14:41:55 2007 +0200 - - POST: Add option for external ethernet loopback test - - When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST - is not done using an internal loopback connection, but by assuming - that an external loopback connector is plugged into the board. - - Signed-off-by: Stefan Roese - -commit eb2b4010ae426245172988804ee8d9193fb41038 -Author: Stefan Roese -Date: Tue Aug 14 14:39:44 2007 +0200 - - POST: Add ppc405 support to cache and UART POST - - Signed-off-by: Stefan Roese - -commit 0c42f36f15074bd9808a7dbd7ef611fad9bf537c -Author: Peter Pearse -Date: Tue Aug 14 10:46:32 2007 +0100 - - Replace lost end of at45.c. - -commit 65d7ada64557e76094b4fd3bad30a0f18f5fb2b2 -Author: Peter Pearse -Date: Tue Aug 14 10:30:06 2007 +0100 - - Update Makefiles for merged and split at45.c. - -commit 3454cece2db57cb9eb7087995f7e73066a163f71 -Author: Peter Pearse -Date: Tue Aug 14 10:21:06 2007 +0100 - - Delete the merged files. - -commit dcbfd2e5649f97aa04fbbc6ea2b008aa4486e225 -Author: Peter Pearse -Date: Tue Aug 14 10:14:05 2007 +0100 - - Add the files. - -commit d4fc6012fd0a5c211b825691f44b06f8032c0551 -Author: Peter Pearse -Date: Tue Aug 14 10:10:52 2007 +0100 - - Add MACH_TYPE records for several AT91 boards. - Merge to two at45.c files into a common file, split to at45.c and spi.c - Fix spelling error in DM9161 PHY Support. - Initialize at91rm9200 board (and set LED). - Add PIO control for at91rm9200dk LEDs and Mux. - Change dataflash partition boundaries to be compatible with Linux 2.6. - - Signed-off-by: Peter Pearse - Signed-off-by: Ulf Samuelsson - -commit 4ef35e53c693556c54b0c22d6f873de87bade253 -Author: Wolfgang Denk -Date: Tue Aug 14 09:54:46 2007 +0200 - - Coding style cleanup, update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 85eb5caf6b906f7ec5b54814e8c7c74f55986bb7 -Author: Wolfgang Denk -Date: Tue Aug 14 09:47:27 2007 +0200 - - Coding style cleanup; rebuild CHANGELOG - -commit 7f3f2bd2dc08e0b05e185662ca2e2d283757104a -Author: Randy Vinson -Date: Tue Feb 27 19:42:22 2007 -0700 - - 85xxCDS: Add make targets for legacy systems. - - The PCI ID select values on the Arcadia main board differ depending - on the version of the hardware. The standard configuration supports - Rev 3.1. The legacy target supports Rev 2.x. - - Signed-off-by Randy Vinson - -commit e41094c7e38177c755fbd9b182018069614f080d -Author: Andy Fleming -Date: Tue Aug 14 01:50:09 2007 -0500 - - 85xxCDS: Enable the VIA PCI-to-ISA bridge. - - Author: Randy Vinson - - Enable the PCI-to-ISA bridge in the VIA Southbridge located on the - Arcadia main board. - - Signed-off-by: Randy Vinson - Signed-off-by: York Sun - -commit da9d4610d76e52c4d20a8f3d8433439a7fcf5b71 -Author: Andy Fleming -Date: Tue Aug 14 00:14:25 2007 -0500 - - Add support for UEC to 8568 - - Signed-off-by: Haiying Wang - Signed-off-by: Andy Fleming - -commit c59e4091ffe0148398b9e9ff14a019ea038b7432 -Author: Haiying Wang -Date: Tue Jun 19 14:18:34 2007 -0400 - - Add PCI support for MPC8568MDS board - - This patch is against u-boot-mpc85xx.git of www.denx.com - - Signed-off-by: Haiying Wang - Signed-off-by: Ebony Zhu - -commit d111d6382c99fdea08c2312eeeae8786945e189a -Author: Haiying Wang -Date: Tue Jun 19 14:18:32 2007 -0400 - - Empirically set cpo and clk_adjust for mpc85xx DDR2 support - - This patch is against u-boot-mpc85xx.git of www.denx.com - - Setting cpo to 0x9 for frequencies higher than 333MHz is verified on - both MPC8548CDS board and MPC8568MDS board, especially for supporting - 533MHz DDR2. - - Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for - DDR2 on all current board versions especially ver 1.92 or later to bring - up. - - Signed-off-by: Haiying Wang - -commit 3db0bef59eab1155801618cef5c481e97553b597 -Author: Kumar Gala -Date: Tue Aug 7 18:07:27 2007 -0500 - - Use an absolute address when jumping out of 4k boot page - - On e500 when we leave the 4k boot page we should use an absolute address since - we don't know where the board code may want us to be really running at. - - Signed-off-by: Kumar Gala - -commit 39980c610c9a4c381907c9e1d1b9c0e1c0dca57a -Author: Andy Fleming -Date: Mon Aug 13 14:49:59 2007 -0500 - - MPC85xx BA bits not set for 3-bit bank address DIMM - - The current implementation does not set the number of bank address bits - (BA) in the processor. The default assumes 2 logical bank bits. This - works fine for a DIMM that uses devices with 4 internal banks (SPD - byte17 = 0x4) but needs to be set appropriately for a DIMM that uses - devices with 8 internal banks (SPD byte17 = 0x8). - - Signed-off-by: Greg Davis - -commit 6c543597bb4b1ecf5d8589f7abb0f39929fb7fd1 -Author: Andy Fleming -Date: Mon Aug 13 14:38:06 2007 -0500 - - Fix minor 85xx warnings - - Some patches had inserted warnings into the build: - * mpc8560ads declared data without using it - * cpu_init declared ecm and immap without using it in all CONFIGs - * MPC8548CDS.h had its default filenames changed so that they contained - "\m" in the paths. Made the defaults not Windows-specific (or - anything-specific) - - Signed-off-by: Andy Fleming - -commit f2cff6b104f82b993bef6086ce0c97159bbe1add -Author: Ed Swarthout -Date: Fri Jul 27 01:50:52 2007 -0500 - - 8548cds PCIE support. - - Make the early L1 cache stack region guarded to prevent speculative - fetches outside the locked range. - - Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions. - init.S whitespace cleanup. - - Allow TEXT_BASE value to be specified on command line. This allows it - to be set to 0xfffc0000 which cuts the uboot binary in half. - - Clear and enable lbc and ecm errors. - - Update last_busno in device-tree for pci and pcie. - - Remove load of obsolete cpu/mpc85xx/pci.0 - - Signed-off-by: Ed Swarthout - Acked-by: Andy Fleming - -commit 837f1ba05cfb248aba5ab8e1fb1bfeefa07d5962 -Author: Ed Swarthout -Date: Fri Jul 27 01:50:51 2007 -0500 - - 8544ds PCIE support - - PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. - - Enable LBC and ECM errors and clear error registers. - - Add tftpflash env var to get uboot from tftp server and flash it. - - Add pci/pcie convenience env vars to display register space: - "run pcie3regs" to see all pcie3 ccsr registers - "run pcie3cfg" to see all cfg registers - Whitespace cleanup and MPC8544DS.h - - Enable CONFIG_INTERRUPTS. - - Signed-off-by: Ed Swarthout - Acked-by: Andy Fleming - -commit 61a21e980a7b9188424d04f1c265fdc5c21c7e85 -Author: Andy Fleming -Date: Tue Aug 14 01:34:21 2007 -0500 - - 85xx start.S cleanup and exception support - - From: Ed Swarthout - - Support external interrupts from platform to eliminate system hangs. - Define CONFIG_INTERRUPTS board configure option to enable. - Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC. - - Remove extra cpu initialization redundant with hardware initialization. - Whitespace cleanup. - - Define and use _START_OFFSET consistent with other processors using - ppc_asm.tmpl - - Move additional code from .text to boot page to make room for - exception vectors at start of image. - - Handle Machine Check, External and Critical exceptions. - - Fix e500 machine check error determination in traps.c - - TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half. - - Signed-off-by: Ed Swarthout - Acked-by: Andy Fleming - -commit 7bd30fc4a6475b41d6679ae3aafc9fa505260c47 -Author: Andy Fleming -Date: Tue Aug 14 01:33:18 2007 -0500 - - Add MPC8544DS README - - Signed-off-by: Andy Fleming - -commit 40c7f9b0de4e300370adfc704128fa0f79a143b6 -Author: Ed Swarthout -Date: Fri Jul 27 01:50:48 2007 -0500 - - 85xx allow debugger to configure ddr. - - Only check for mpc8548 rev 1 when compiled for 8548. - - Signed-off-by: Ed Swarthout - Acked-by: Andy Fleming - -commit 29372ff38c5baab7d0e3a8c14fe11fa194a38704 -Author: Ed Swarthout -Date: Fri Jul 27 01:50:47 2007 -0500 - - mpc85xx L2 cache reporting and SRAM relocation option. - - Allow debugger to override flash cs0/cs1 settings to enable alternate - boot regions - - Signed-off-by: Ed Swarthout - Acked-by: Andy Fleming - -commit 41f0f8fb1ab92f0cba7d329de90070f822f8299f -Author: Ed Swarthout -Date: Fri Jul 27 01:50:46 2007 -0500 - - e500 needs ppc_asm.tmp MCK_EXCEPTION - - Always define MCK_EXCEPTION macro - so e500 can use it too. - - Signed-off-by: Ed Swarthout - Acked-by: Andy Fleming - -commit 53a5c424bf8655b7b4e2c305a441963259a26a81 -Author: David Updegraff -Date: Mon Jun 11 10:41:07 2007 -0500 - - multicast tftp: RFC2090 - - Implemented IETF RFC2090, Multicast TFTP. Initial implementation - on Realtek RTL8139 and Freescale TSEC. - - Signed-off-by: David Updegraff - Signed-off-by: Ben Warren - -commit 5d110f0aa69f065ee386ec1840dfee1e8cc46bc1 -Author: Wilson Callan -Date: Sat Jul 28 10:56:13 2007 -0400 - - New CONFIG_BOOTP_SERVERIP option - - Added CONFIG_BOOTP_SERVERIP to allow the tftp server to be different - from the bootp server - - Signed-off-by: Wilson Callan - Signed-off-by: Ben Warren - -commit 50cca8b976ec74069860208c36e64ce8f4d5e4c1 -Author: Mike Rapoport -Date: Sun Aug 12 08:48:27 2007 +0300 - - Add ability to take MAC address from the environment to DM9000 driver - - Signed-off-by: Mike Rapoport - Signed-off-by: Ben Warren - -commit be5d72d10d47609326226225181e301fb9a33b58 -Author: Wolfgang Denk -Date: Mon Aug 13 21:57:53 2007 +0200 - - Minor coding style cleanup. Update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit cca34967cbd13ff6bd352be29e3f1cc88ab24c05 -Author: Joe Hamman -Date: Sat Aug 11 06:54:58 2007 -0500 - - Modify SBC8641D to use new Freescale PCI routines - - PCI-Express sockets 1 and 2 verified working with Intel Pro/1000 PT - adapter. - - Signed-off-by: Joe Hamman - Signde-off-by: Jon Loeliger - -commit a08458303e7f9db67f296980036d3292c35cb45c -Author: Haavard Skinnemoen -Date: Fri Jun 29 18:38:51 2007 +0200 - - atmel_mci: Fix data timeout value - - Calculate the data timeout based on values from the CSD instead of - just using a hardcoded DTOR value. This is a backport of a similar fix - in BSP 2.0, with one additional fix: the DTOCYC value is rounded up - instead of down. - - Signed-off-by: Haavard Skinnemoen - -commit 0ba8eed28b575626b17e0a7882f923b83e0d7584 -Author: Haavard Skinnemoen -Date: Mon Aug 13 17:22:31 2007 +0200 - - AVR32: Include instead of - - include/asm-avr32/div64.h was recently moved to include/div64.h, but - cpu/at32ap/interrupts.c wasn't properly updated (an earlier version of - the patch was merged perhaps?) - - This patch updates cpu/at32ap/interrupts.c so that the avr32 port - compiles again. - - Signed-off-by: Haavard Skinnemoen - -commit f0d1246ed7cb5a88522244c596d7ae7e6f161283 -Author: Haavard Skinnemoen -Date: Wed Jun 27 13:34:26 2007 +0200 - - atmel_mci: Use 512 byte blocksize if possible - - Instead of always using the largest blocksize the card supports, check - if it can support smaller block sizes and use 512 bytes if possible. - Most cards do support this, and other parts of u-boot seem to have - trouble with block sizes different from 512 bytes. - - Also enable underrun/overrun protection. - - Signed-off-by: Haavard Skinnemoen - Acked-by: Hans-Christian Egtvedt - -commit 273db7e1bdd1937e32f1d4507321bb721ebd3118 -Author: Stefan Roese -Date: Mon Aug 13 09:05:33 2007 +0200 - - ppc4xx: Fix problem in PLL clock calculation - - This patch was originall provided by David Mitchell - and fixes a bug in the PLL clock calculation. - - Signed-off-by: Stefan Roese - -commit 9986bc3e40e899bea372a99a2bca4071bdf2e24b -Author: Wolfgang Denk -Date: Sun Aug 12 21:34:50 2007 +0200 - - Update CHANGELOG - -commit 77d19a8bf3b0b1e401cb9f23c81e2ef419705c1a -Author: Wolfgang Denk -Date: Sun Aug 12 21:34:34 2007 +0200 - - Minor alignment of output, 2nd try. - Also update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 6b309f22a724fad8418e811751a0741b893419cf -Author: Wolfgang Denk -Date: Sun Aug 12 20:35:49 2007 +0200 - - Minor alignment of output - - Signed-off-by: Wolfgang Denk - -commit 6f6d7b9c8559e241e8d232621542b8b59699b07b -Author: Wolfgang Denk -Date: Sun Aug 12 18:28:18 2007 +0200 - - Cleanup output on ADS5121 board - - Signed-off-by: Wolfgang Denk - -commit a4d2636f2a859245ed3a401f26189da2dfda4ceb -Author: Wolfgang Denk -Date: Sun Aug 12 15:11:38 2007 +0200 - - Adapt board configuration and fix kernel crash on MCC200 board. - - The update procedure was modified to turn off the USB subsystem - before exit for MCC200 and TRAB. This is necessary as otherwise the - USB controller continues to write periodically to system memory! - - MCC200-specific notes: - - the patch disables the magic key check for MCC200 - - the patch contains the configuration changes made - for the new revision of the board. - - Signed-off-by: Sergei Poselenov - Signed-off-by: Wolfgang Denk - -commit e27f3a6efb9db5a533223b05c629ff4ac8d921bf -Author: Wolfgang Denk -Date: Sun Aug 12 14:47:54 2007 +0200 - - Adjust default configuration of ADS5121 board. - - Signed-off-by: Wolfgang Denk - -commit afaac86fe2948ac84cd9a12bbed883b3c683e7d9 -Author: Wolfgang Denk -Date: Sun Aug 12 14:27:39 2007 +0200 - - Clean up some remaining CFG_CMD_ -> CONFIG_CMD_ issues. - - Signed-off-by: Wolfgang Denk - -commit 5fe6be6208dda852c3564e384bd78d75784dea3e -Author: Gerald Van Baren -Date: Tue Aug 7 21:14:22 2007 -0400 - - Improve error print messages. - - Signed-off-by: Gerald Van Baren - -commit 99dffca3b7590a16a00bc475c860b67b2a3f1462 -Author: Kim Phillips -Date: Tue Jul 17 13:57:04 2007 -0500 - - fdt: allow for builds that don't want env and bd_t nodes - - protect fdt_env and fdt_bd_t invocations, fix codingstyle while in the - area. - - Signed-off-by: Kim Phillips - -commit 91148bf7aeba142d6f348805db7625db7da64d6f -Author: Kim Phillips -Date: Tue Jul 17 13:56:53 2007 -0500 - - fdt: do board setup based on fdt address specified on bootm line - - The last fdt patch to bootm did board setup based on the address - specified by a prior fdt address command invocation. The bootm - code, as its call to fdt_chosen does, should use the fdt specified - by the user on the bootm command. Note this restores full - functionality for the 8360's existing default boot environment - values, e.g. 'run nfsboot' (i.e. no having to 'fdt addr $fdtaddr' - before booting a kernel). - - Signed-off-by: Kim Phillips - -commit e125a2ffc209dd34794e326c7175658253beadf3 -Author: Gerald Van Baren -Date: Tue Jul 10 20:40:39 2007 -0400 - - Call ft_board_setup() from the bootm command. - - In the patch titled "Create new fdt boardsetup command..." I removed the - call to ft_board_setup() from the routine fdt_chosen(), but I forgot - to add a direct call back into cmd_bootm.c - - This fixes the oversight by adding the direct call to the bootm command. - - Signed-off-by: Gerald Van Baren - -commit fd61e55dd8cb52ce3ff91b3917af26e24b6b0845 -Author: Gerald Van Baren -Date: Mon Jun 25 23:25:28 2007 -0400 - - Create new fdt boardsetup command, fix bug parsing [] form of set values. - - Previously ft_board_setup() was called by fdt_chosen() which was not - really correctly structured. This splits ft_board_setup() out by creating - a new fdt boardsetup command. - - Fix a bug when parsing fdt set command values which have the square - bracket form [00 11 22 33] - the length was updated incorrectly in when - parsing that form. - - Signed-off-by: Gerald Van Baren - -commit 6f35ded9e85493595e0eb66a82b502a95326d049 -Author: Gerald Van Baren -Date: Mon Jun 25 20:55:58 2007 -0400 - - Tighten up the error messages. - - Signed-off-by: Gerald Van Baren - -commit c45874b05aae897a6c29d1a97d4bb708fca2756c -Author: Gerald Van Baren -Date: Mon Jun 25 19:52:23 2007 -0400 - - Asthetic improvements: error messages and line lengths. - - Tighten up the error messages, split overlength lines. - - Signed-off-by: Gerald Van Baren - -commit 35ec398f16e17df600edc1b38c1e9e62c15c9aa1 -Author: Gerald Van Baren -Date: Fri May 25 22:08:57 2007 -0400 - - Fix fdt_chosen() to call ft_board_setup(), clean up long lines. - - The fdt_chosen() function was adding/seting some properties ad-hoc - improperly and duplicated (poorly) what was done in ft_board_setup() - - Clean up long lines (setting properties, printing errors). - - Signed-off-by: Gerald Van Baren - -commit 06e19a07701c968f15d72c083b5872a1a11c7b01 -Author: Gerald Van Baren -Date: Mon May 21 23:27:16 2007 -0400 - - For fdt_find_node_by_path(), handle the root path properly. - - Also removes the special case root path detection in cmd_fdt.c since it - is no longer necessary. - - Signed-off-by: Gerald Van Baren - -commit 9675ee7208ab965d13ea8d8262d77ac4160ef549 -Author: Gerald Van Baren -Date: Thu May 17 23:54:36 2007 -0400 - - Add fdt_find_node_by_type() and fdt_find_compatible_node() to LIBFDT - - Signed-off-by: Wolfgang Grandegger - Acked-by: Gerald Van Baren - -commit 1a861169bc3758f9de3aead62b058736c6891246 -Author: Gerald Van Baren -Date: Wed Jun 6 22:47:58 2007 -0400 - - Replace fdt_node_offset() with fdt_find_node_by_path(). - - The new name matches more closely the kernel's name, which is also - a much better description. - - Signed-off-by: Wolfgang Grandegger - Acked-by: Gerald Van Baren - -commit addd8ce83078c25f0eca5f23adbdfc64ca50a243 -Author: Gerald Van Baren -Date: Wed May 16 22:39:59 2007 -0400 - - Fix cmd_fdt line lengths, refactor code. - - Break lines that were greater than 80 characters in length. - Move the fdt print and property parsing code to separate static functions - to reduce coding clutter in the fdt_cmd handling body. - - Signed-off-by: Gerald Van Baren - -commit 25114033ab21788810c48ba4df103b649da1223b -Author: Gerald Van Baren -Date: Sat May 12 09:47:25 2007 -0400 - - FDT command improvements. - - Fix "fdt set" so that it will create a non-existing property. - Add "fdt mknode" to create nodes. - - Signed-off-by: Gerald Van Baren - -commit 38eb508e8e811e2e57628f445de3a24a23c7d804 -Author: Gerald Van Baren -Date: Sat May 12 09:45:46 2007 -0400 - - Reorganize and fix problems (returns) in the bootm command. - - Do *NOT* return after the "point of no return" has been passed. - If something goes wrong, the board must be reset after that point. - Move the "Transferring control to Linux" debug message back to where it - belongs: just before transferring control to linux. - - Signed-off-by: Gerald Van Baren - -commit 89c8757d8f213c47709bdc4efe0695263a6080a6 -Author: Gerald Van Baren -Date: Tue May 8 21:27:35 2007 -0400 - - Fix bugs in the CONFIG_OF_LIBFDT - - Stupid coding mistakes (identified by Timur Tabi, thanks). - - Signed-off-by: Gerald Van Baren - -commit 6be07cc1ca458278c85ecdbf1a0536cff4c701ec -Author: Gerald Van Baren -Date: Wed Apr 25 22:47:15 2007 -0400 - - Improve fdt move length handling. - - Make the length parameter optional: if not specified, do the move using - the current size unchanged. - - Signed-off-by: Gerald Van Baren - -commit bb930e76fea6cf89ca2d98e2f7c7a6043d79327d -Author: Gerald Van Baren -Date: Wed Apr 25 22:23:36 2007 -0400 - - Minor code clean up. - - Declare the variable fdt properly as extern. - Call the "set_fn" function pointer the "short way" without the full - dereferencing syntax. - - Signed-off-by: Gerald Van Baren - -commit ba24e2ac3bdb5c489f3c787e7542b6474c4d65c6 -Author: Gerald Van Baren -Date: Wed Apr 25 21:24:27 2007 -0400 - - Improve error messages, more informative. - - Print more than the raw libfdt error message strings. This is especially - useful for cluing in the user when the bootm command aborts due to - blob problems. - - Signed-off-by: Gerald Van Baren - -commit 8096b3b8f772c1894ddeda9dbceff6a8826473a4 -Author: Gerald Van Baren -Date: Fri Apr 20 22:46:53 2007 -0400 - - libfdt: Conditionally compile based on CONFIG_OF_LIBFDT - - This is the way u-boot reduces configured-out code. At Wolfgang - Grandegger and Wolfgang Denk's request, make libfdt conform. - - Signed-off-by: Gerald Van Baren - -commit 923efd286411ed052d9e074f59f8986d6081061c -Author: Bruce Adler -Date: Fri Aug 10 14:54:47 2007 -0700 - - add image size and descriptors for Spartan 3E FPGA chips - - Spartan 3E image sizes taken from Table 1-4 in Xilinx UG332 (v1.1) - - Signed-off by: Bruce Adler - -commit fb56579ffe7ef3275b7036bb7b924e5a0d32bd70 -Author: Kim Phillips -Date: Fri Aug 10 15:34:48 2007 -0500 - - make MAKEALL more immune to merge conflicts - - ..by placing board entries one per line, as suggested by jdl. - - Signed-off-by: Kim Phillips - -commit 2628114ec564f969f34b5f7105fbd168cb8c9c3f -Author: Kim Phillips -Date: Fri Aug 10 13:28:25 2007 -0500 - - README: Remove outdated cpu type, board type, and NAME_config lists - - Signed-off-by: Kim Phillips - -commit 49bb59912d21aacb507eb81fd21fb7af650c706c -Author: Dave Liu -Date: Fri Aug 10 15:48:59 2007 +0800 - - mpc83xx: Suppress the warning 'burstlen' - - suppress the warning 'burstlen' of spd_sdram. - - Signed-off-by: Dave Liu - -commit c646bba6465a45c60746d4cc1602cd06c1960f2d -Author: Joe Hamman -Date: Thu Aug 9 15:11:03 2007 -0500 - - Add support for SBC8641D. Config files. - - Add support for Wind River's SBC8641D reference board. - - Signed-off by: Joe Hamman - Acked-by: Wolfgang Denk - Acked-by: Jon Loeliger - -commit 8ac273271d57321f90505c7a51cdb1ef2113b628 -Author: Joe Hamman -Date: Thu Aug 9 15:10:53 2007 -0500 - - Add support for SBC8641D. Board files. - - Add support for Wind River's SBC8641D reference board. - - Signed-off by: Joe Hamman - Acked-by: Wolfgang Denk - Acked-by: Jon Loeliger - -commit c2c0ab4aff86622b837a48a0e560351f9afafb95 -Author: Stefan Roese -Date: Fri Aug 10 20:34:58 2007 +0200 - - Conding style cleanup - - Signed-off-by: Stefan Roese - -commit c74b2108e31fe09bd1c5d291c3cf360510d4f13e -Author: Sergey Kubushyn -Date: Fri Aug 10 20:26:18 2007 +0200 - - [ARM] TI DaVinci support, hopefully final - - Add support for the following DaVinci boards: - - DV_EVM - - SCHMOOGIE - - SONATA - - Changes: - - - Split into separate board directories - - Removed changes to MTD_DEBUG (or whatever it's called) - - New CONFIG_CMD party line followed - - Some cosmetic fixes, cleanup etc. - - Patches against the latest U-Boot tree as of now. - - Fixed CONFIG_CMD_NET in net files. - - Fixed CONFIG_CMD_EEPROM for schmoogie. - - Made sure it compiles and works (forceenv() link problem) on SCHMOOGIE and - DV_EVM. Can't check if it works on SONATA, don't have a board any more, - but it at least compiles. - - Here is an excerpt from session log on SCHMOOGIE... - - U-Boot 1.2.0-g6c33c785-dirty (Aug 7 2007 - 13:07:17) - - DRAM: 128 MB - NAND: 128 MiB - In: serial - Out: serial - Err: serial - ARM Clock : 297MHz - DDR Clock : 162MHz - ETH PHY : DP83848 @ 0x01 - U-Boot > iprobe - Valid chip addresses: 1B 38 3A 3D 3F 50 5D 6F - U-Boot > ping 192.168.253.10 - host 192.168.253.10 is alive - U-Boot > - - Signed-off-by: Sergey Kubushyn - Acked-by: Dirk Behme - Acked-by: Zach Sadecki - Acked-by: Stefan Roese - -commit 2e4d94f1e3c2961428967a33b6ff2520568391b3 -Author: Ed Swarthout -Date: Fri Jul 27 01:50:45 2007 -0500 - - fsl_pci_init cleanup. - - Do not enable normal errors created during probe (master abort, perr, - and pcie Invalid Configuration access). - - Add CONFIG_PCI_NOSCAN board option to prevent bus scan. - - Signed-off-by: Ed Swarthout - Acked-by: Andy Fleming - -commit 936b3e69b667c3eb9a61ece4e78647d3fce9fc2a -Author: Ed Swarthout -Date: Fri Jul 27 01:50:44 2007 -0500 - - pciauto_setup_device bars_num fix - - Passing bars_num=0 to pciauto_setup_device should assign no bars. - - Signed-off-by: Ed Swarthout - Acked-by: Shinya Kuribayashi - Acked-by: Andy Fleming - -commit cf0b185e58ca0aec8ae2b2a8804ec0ef58ee21d4 -Author: Jon Loeliger -Date: Mon Aug 6 17:39:44 2007 -0500 - - 8641hpcn: Do correct sized pointer math. - - When I rebased Ed's patch and cleaned up a few compilation - problems, I apparently rebased my brain on crack first. - Fix that by doing (char *) sized pointer math as needed. - - Signed-off-by: Jon Loeliger - -commit cfc7a7f5bb3273c9951173c788001d45118f141f -Author: Jon Loeliger -Date: Thu Aug 2 14:42:20 2007 -0500 - - cpu/86xx fixes. - - Remove rev 1 fixes. - Always set PICGCR_MODE. - Enable machine check and provide board config option - to set and handle SoC error interrupts. - - Include MSSSR0 in error message. - - Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. - - Signed-off-by: Ed Swarthout - Signed-off-by: Jon Loeliger - -commit 35d22f957a85a22bb3cd1ad084fa5404620d1c42 -Author: Stefan Roese -Date: Fri Aug 10 10:42:25 2007 +0200 - - Coding style cleanup - - Signed-off-by: Stefan Roese - -commit 3a6d56c20989fe27360afe743bd2a7ad4d76e48f -Author: Dirk Behme -Date: Thu Aug 2 17:42:08 2007 +0200 - - Make use of generic 64bit division in nand_util.c - - Use generic 64bit division in nand_util.c. This makes nand_util.c - independent of any toolchain 64bit division. - - Signed-off-by: Dirk Behme - -commit f7c086e94e8ce9aad7268af97f73aa6884686f27 -Author: Dirk Behme -Date: Thu Aug 2 17:41:14 2007 +0200 - - Move 64bit division from avr32 to generic lib - - Move the 64bit division from lib_avr32 to lib_generic. With this, all - boards can do_div/__div64_32 if needed, not only avr one. Code is put - to lib_generic, so no larger memory footprint if not used. No code - modifications. Thanks for proposal by HÃ¥vard Skinnemoen. - - Signed-off-by: Dirk Behme - -commit 157cda4d0c3d592ccbb19bbfc07d9251894f0894 -Author: Niklaus Giger -Date: Fri Jul 27 11:31:22 2007 +0200 - - Add PPC4xx-HCU4 and HCU5 boards: HCU5 files - - Signed-off-by: Niklaus Giger - -commit 6e5de26c6e7580faf16e87745cd488b92b492d0c -Author: Niklaus Giger -Date: Fri Jul 27 11:30:33 2007 +0200 - - Add PPC4xx-HCU4 and HCU5 boards: HCU4 files - - Signed-off-by: Niklaus Giger - -commit e8397fc78c9394d71de233a4d810fbc9047e4c76 -Author: Niklaus Giger -Date: Fri Jul 27 11:38:26 2007 +0200 - - Add PPC4xx-HCU4 and HCU5 boards: common files - - Signed-off-by: Niklaus Giger - -commit ac982ea5a4f2f993efcf52dca122f5a59df047d8 -Author: Niklaus Giger -Date: Fri Jul 27 11:28:44 2007 +0200 - - Add PPC4xx-HCU4 and HCU5 boards: make related - - Signed-off-by: Niklaus Giger - -commit 137fdd9f474ecb853efdace5200576308c67f18d -Author: Niklaus Giger -Date: Fri Jul 27 11:28:03 2007 +0200 - - Add PPC4xx-HCU4 and HCU5 boards: HCU5 config - - Signed-off-by: Niklaus Giger - -commit 714bc55b35b6f6a65cc8740a3842a543e88cdef2 -Author: Niklaus Giger -Date: Fri Jul 27 11:27:15 2007 +0200 - - Add PPC4xx-HCU4 and HCU5 boards: HCU4 config - - Signed-off-by: Niklaus Giger - -commit 1894dd381124bdbfbdae7cf3a6ca52a8eb1f4421 -Author: Niklaus Giger -Date: Fri Jul 27 11:25:31 2007 +0200 - - Add PPC4xx-HCU4 and HCU5 boards: READMEs - - Signed-off-by: Niklaus Giger - -commit 641cca9569ce351ddb287fd3343d8b1dcb591db4 -Author: Niklaus Giger -Date: Fri Jul 27 11:37:40 2007 +0200 - - Add PPC4xx-HCU4 and HCU5 boards: Infrastructure - - This series of patches adds support for 2 boards from Netstal Maschinen. - - The HCU4 has a PPC405Gpr and - the HCU5 has a PPC440EPX. - - The HCU4 has a somehow complicated flash setup, as the booteprom is - only 8 bits and the CFI 16 bits wide, which makes it impossible to use a more - elegant solution. - - The HCU5 has only a booteprom as the whole code will be downloaded from a - different board which has HD, CD-ROM, etc and where all code is stored. - - This is my third try. I incorporated all suggestions made by Wolfgang and Stefan. - Thanks them a lot. - - Signed-off-by: Niklaus Giger - -commit 3e4c90c6233618fc1806e63fde68df5f3d6a0171 -Author: Stefan Roese -Date: Fri Aug 10 08:42:55 2007 +0200 - - ppc4xx: Update lwmon5 POST configuration - - Signed-off-by: Stefan Roese - -commit 29cb25da56afe18cf5e7072a92a9d98ea8af1fd4 -Author: Yuri Tikhonov -Date: Fri Aug 10 08:25:22 2007 +0200 - - POST: Add ppc4xx UART POST support without external uart clock (lwmon5) - - The patch adds support for UART POST on ppc44x-based boards with no - external serial clocks installed. - - Signed-off-by: Yuri Tikhonov - Acked-by: Stefan Roese - -commit 99c2fdab91bc633e46fb41dbaa629f87ccf6e00f -Author: Kim Phillips -Date: Mon Aug 6 18:18:34 2007 -0500 - - mpc83xx: fix ITX[GP] O=builddir builds - - make: *** No rule to make target `/work/wd/tmp/board/mpc8349itx/u-boot.lds', needed by `/work/wd/tmp/u-boot'. Stop. - - Both the ITX and ITX-GP fail when you use "make O= ..." or - "BUILD_DIR= ./MAKEALL ..." - - Signed-off-by: Kim Phillips - -commit 47e8bc846759e037b8af0e5f9c9f9cfa7a1050c3 -Author: Dave Liu -Date: Wed Aug 1 15:00:59 2007 +0800 - - mpc83xx: Correct the README for DDR ECC - - Update the README for DDR ECC, change the name - to README.mpc83xx.ddrecc. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit daab8c67d2defef73dc26ab07f0c3afd1b05d019 -Author: Dave Liu -Date: Wed Aug 1 15:00:15 2007 +0800 - - mpc83xx: Consolidate the ECC support of 83xx - - Remove the duplicated source code of ecc command on the .c, - for reused, move these code to cpu/mpc83xx directory. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 036575c544cf1b69654d8fb334bda69c6ff3da36 -Author: Dave Liu -Date: Sat Aug 4 13:37:39 2007 +0800 - - mpc83xx: Correct the burst length for DDR2 with 32 bits - - The burst length should be 4 for DDR2 with 32 bits bus - - Signed-off-by: Dave Liu - -commit 1c274c4e05b6dc9b24edc8aa618b02f607ee6eed -Author: Kim Phillips -Date: Wed Jul 25 19:25:33 2007 -0500 - - mpc83xx: add support for the MPC8323E RDB - - MPC8323E based board with 64MB fixed SDRAM, 16MB flash, - five 10/100 ethernet ports connected via an ICPlus IP175C - switch, one PCI slot, and serial. Features not supported - in this patch are SD card interface, 2 USB ports, and the - two phone ports. - - Signed-off-by: Michael Barkowski - Signed-off-by: Kim Phillips - -commit 343d91009d55fc5b3ff8cc940597af6c6aa1d359 -Author: Kim Phillips -Date: Wed Jul 25 19:25:28 2007 -0500 - - mpc83xx: fixup generic pci for libfdt - - add libfdt support to the generic 83xx pci code - - Signed-off-by: Kim Phillips - -commit f57ac7a7b37109245b69db80839ebee26179966a -Author: Kim Phillips -Date: Wed Jul 25 19:25:22 2007 -0500 - - mpc83xx: fix 8360 and cpu functions to update fdt being passed - - ..and not the global fdt. Rename local fdt vars to blob so as not to - be confused with the global var with the same three-letter name. - - Signed-off-by: Kim Phillips - -commit 8be404459a6b7395415a57bb35e8377e3b2b5acb -Author: Jerry Van Baren -Date: Wed Jul 4 21:34:24 2007 -0400 - - mpc83xx: Fix errors when CONFIG_OF_LIBFDT is enabled - - Several node strings were not correct (trailing slashes and properties - in the strings) - Added setting of the timebase-frequency. - Improved error messages and use debug() instead of printf(). - - Signed-off-by: Gerald Van Baren - Signed-off-by: Kim Phillips - -commit 26d02c9bbac1751c5e19294f000100b48d43a920 -Author: Jerry Van Baren -Date: Wed Jul 4 21:27:30 2007 -0400 - - mpc83xx: Replace fdt_node_offset() with fdt_find_node_by_path(). - - The new name matches more closely the kernel's name, which is also - a much better description. - - These are the mpc83xx changes made necessary by the function name change. - - Signed-off-by: Wolfgang Grandegger - Acked-by: Gerald Van Baren - Signed-off-by: Kim Phillips - -commit 9be39a67c9f8fef7107f5df09d673005f04d0963 -Author: Dave Liu -Date: Mon Jun 25 10:41:56 2007 +0800 - - mpc83xx: Add support for the display of reset status - - 83xx processor family has many reset sources, such as - power on reset, software hard reset, software soft reset, - JTAG, bus monitor, software watchdog, check stop reset, - external hard reset, external software reset. - sometimes, to figure out the fault of system, we need to - know the cause of reset early before the prompt of - u-boot present. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit ff9658d7049bf8c8e8e0a05dbe5e9f7e91aa5a5d -Author: Dave Liu -Date: Mon Jun 25 10:41:04 2007 +0800 - - mpc83xx: Fix the align bug of SDMA buffer - - According to the latest user manual, the SDMA temporary - buffer base address must be 4KB aligned. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit 66dc2c2dc51f8b88bb8e231bc80cd92eae1d6476 -Author: Dave Liu -Date: Mon Jun 25 13:21:12 2007 +0800 - - mpc83xx: Revise the MPC8360EMDS readme doc - - When the rev2.x silicon mount on the MPC8360EMDS baord, - and if you are using the u-boot version after the commit - 3fc0bd159103b536e1c54c6f4457a09b3aba66ca. - to make the ethernet interface usable, we have to setup - the jumpers correctly. - - Signed-off-by: Dave Liu - Signed-off-by: Kim Phillips - -commit e739bc95797aac4fefc4c75b55c7c78e59d3ea9c -Author: Timur Tabi -Date: Tue Jul 3 13:46:32 2007 -0500 - - FSL I2C driver programs the two I2C busses differently - - The i2c_init() function in fsl_i2c.c programs the two I2C busses differently. - The second I2C bus has its slave address programmed incorrectly and is - missing a 5-us delay. - - Signed-off-by: Timur Tabi - Signed-off-by: Kim Phillips - -commit df33f6b4d6d63693dd9200808b242de1b86cb8e8 -Author: Timur Tabi -Date: Tue Jul 3 13:04:34 2007 -0500 - - Update SCCR programming in cpu_init_f() to support all 83xx processors - - Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the - bitfields for all 83xx processors. The code to update some bitfields was - compiled only on some processors. Now, the bitfields are programmed as long - as the corresponding CFG_SCCR option is defined in the board header file. - This means that the board header file should not define any CFG_SCCR macros - for bitfields that don't exist on that processor, otherwise the SCCR will be - programmed incorrectly. - - Signed-off-by: Timur Tabi - Signed-off-by: Kim Phillips - -commit 9546266999f0b9b51372636614211b88d90f0f25 -Author: Martin Krause -Date: Fri Jun 22 13:04:22 2007 +0200 - - TQM834x: cleanup configuraton - - Remove irritating #undef DEBUG - - Signed-off-by: Martin Krause - Signed-off-by: Kim Phillips - -commit 5d497e6bf0f5bf63729b4a47b3fd786d3c77a1bc -Author: david.saada -Date: Mon Jun 18 09:09:53 2007 -0700 - - MPC83xx: Fix makefile to generate config.h file in the build directory - - MPC83xx: Fix the Makefile config sections to generate the include/config.h - file in the build directory instead of the source directory. - - Signed-off-by: David Saada - Signed-off-by: Kim Phillips - -commit 1ded0242e437259366792d52b7e9d1e1931d8fa5 -Author: Lee Nipper -Date: Thu Jun 14 20:07:33 2007 -0500 - - mpc83xx: Add support for 8360 silicon revision 2.1 - - This change adds 8360 silicon revision 2.1 support to u-boot. - - Signed-off-by: Lee Nipper - Signed-off-by: Kim Phillips - -commit a22806469a8f2b69c829f4fd5361fdebd0cb01b4 -Author: Kumar Gala -Date: Wed Aug 8 04:14:28 2007 -0500 - - Treat ppc64 host as ppc - - Signed-off-by: Kumar Gala - -commit 0dc4279b08ff82472bec2e2c90858602459febe8 -Author: Jason Jin -Date: Wed Aug 8 09:01:46 2007 +0800 - - Minor fix for bios emulator makefile - - Add $(obj) to LIB avoiding objects be built in the source dir - - Signed-off-by: Jason Jin - -commit ce981dc857adfc8036ca2f6d5d5a06c2a8aa77d6 -Author: Jason Jin -Date: Wed Aug 8 08:33:11 2007 +0800 - - Add CONFIG_BIOSEMU define to guard all the bios emulator code - - Signed-off-by: Jason Jin - - This patch fix the compile issue on the board that did not enable the bios emulator - -commit ed8106433522f2ea8933e9808346860d061d7731 -Author: Zach Sadecki -Date: Tue Jul 31 12:27:25 2007 -0500 - - tsec: fix multiple PHY support - - The change entitled "Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx" - broke multiple PHY support in tsec.c. This fixes it. - - Signed-off-by: Zach Sadecki - Signed-off-by: Kim Phillips - -commit dcb84b7208ade0bbebbeb56bec9c2c64f8b2eede -Author: Joe Hamman -Date: Thu Aug 9 09:08:18 2007 -0500 - - tsec: Allow Ten Bit Interface address to be configurable - - Allow the address of the Ten Bit Interface (TBI) to be changed in the - event of a conflict with another device. - - Signed-off by: Joe Hamman - -commit 3ba4c2d68f6541db4677b4aea12071f56e6ff6e6 -Author: Stefan Roese -Date: Wed Aug 8 09:54:26 2007 +0200 - - Coding style cleanup - - Signed-off-by: Stefan Roese - -commit a41de1f0d373e09c782dea558385a06247111ba5 -Author: TsiChungLiew -Date: Sun Aug 5 05:15:18 2007 -0500 - - Port enabled for I2C signals and chipselects port configuration. - - Signed-off-by: TsiChungLiew - -commit 1a33ce65a4c51a69190dd8c408f9e1c62a66e94f -Author: TsiChungLiew -Date: Sun Aug 5 04:31:18 2007 -0500 - - Added NAND support - - Signed-off-by: TsiChungLiew - -commit eaf9e447beb3e498818ef8ad0b8c1597cd506149 -Author: TsiChungLiew -Date: Sun Aug 5 04:11:20 2007 -0500 - - Added I2C support - - Signed-off-by: TsiChungLiew - -commit 99c03c175d2689093176facf17c58ce2cb320001 -Author: TsiChungLiew -Date: Sun Aug 5 03:58:52 2007 -0500 - - Changed CFG_CLK to gd->bus_clk for CFG_TIMER_PRESCALER. Added DECLARE_GLOBAL_DATA_PTR for time.c - - Signed-off-by: TsiChungLiew - -commit 8d1d66af54d305de29d0bbf4aa8c9e6375f7f731 -Author: TsiChungLiew -Date: Sun Aug 5 03:55:21 2007 -0500 - - Added uart_gpio_conf() in serial_init(), seperated uart port configuration from cpu_init() to uart_gpio_conf() - - Signed-off-by: TsiChungLiew - -commit 6fde84a44b7e575ea80fe0e2d5be3b6f73d1e630 -Author: TsiChungLiew -Date: Sun Aug 5 03:43:30 2007 -0500 - - Moved sync() from board file to include/asm-m68k/io.h - - Signed-off-by: TsiChungLiew - -commit 9e737d8476e7d6a596d16caaf6a3853a9a1190a2 -Author: TsiChungLiew -Date: Sun Aug 5 03:30:44 2007 -0500 - - Declared attributes of void __mii_init(void) as an alias for int mii_init(void) - - Signed-off-by: TsiChungLiew - -commit 9998bd37ead85e93953559720710d3b0685c81e6 -Author: TsiChungLiew -Date: Sun Aug 5 03:19:10 2007 -0500 - - Renamed CONFIG_MCFSERIAL to CONFIG_MCFUART - - Signed-off-by: TsiChungLiew - -commit 7c4c3722a38d40b0cf537ddae72b04f4088b190c -Author: Jason Jin -Date: Tue Aug 7 16:17:06 2007 +0800 - - Add CONFIG_BIOSEMU define to guard all the bios emulator code - - This patch fix the compile issue on the board that did not enable the bios emulator - -commit bf1060ea4f9eaa7e7d164a70a7d6f28939882053 -Author: Wolfgang Denk -Date: Tue Aug 7 16:02:13 2007 +0200 - - Fix missing brace error in fs/fat/fat.c - [pointed out by Roderik Wildenburg] - - Signed-off-by: Wolfgang Denk - -commit 706714d97a0d08d59eda4de2268c39f504688329 -Author: Michal Simek -Date: Mon Aug 6 23:41:53 2007 +0200 - - [FIX] remove cute code - -commit f500d9fdeb576288656dac427052ad2c5ca0ad1a -Author: Michal Simek -Date: Mon Aug 6 23:35:26 2007 +0200 - - [FIX] Fix romfs code - -commit ab4b956d3143f8f8174089053f5dfabbb04762b0 -Author: Michal Simek -Date: Mon Aug 6 23:31:49 2007 +0200 - - [FIX] Coding style cleanup - Wolfgang's suggestions - -commit 6c33c78557ca6f8da68c01ce33e278695197d3f4 -Author: Wolfgang Denk -Date: Mon Aug 6 23:21:05 2007 +0200 - - Fixed typo in README (pointed out by Martin Jost). - - Signed-off-by: Wolfgang Denk - -commit 537223afa61f64480df31ce440a9cb386df4a814 -Author: Stefan Roese -Date: Mon Aug 6 21:10:17 2007 +0200 - - ppc4xx: Update AMCC Bamboo README doc/README.bamboo - - As suggested by Eugene O'Brien , - here an updated Bamboo README. - - Signed-off-by: Stefan Roese - -commit 9c7e4b06214db61bb21f1bcbe57c97519669baae -Author: Wolfgang Denk -Date: Mon Aug 6 02:17:36 2007 +0200 - - Coding style cleanup. Update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit 221838cc7eb178370ff62aa05920a582e12ac322 -Author: Jason Jin -Date: Tue Jul 10 09:03:22 2007 +0800 - - Remove the bios emulator from MAI board. - - The bios emulator in the MAI board can not pass compile - and have a lot of crap in it. remove it and will have a - clean and small bios emulator in the drivers directory - which can be uesed for every board. - - Signed-off-by: Jason Jin - -commit 5618332409bb96f4448d1712899369fc80c0b489 -Author: Jason Jin -Date: Fri Jul 13 12:14:59 2007 +0800 - - Fix some compile issues for MAI board. - - Signed-off-by: Jason Jin - -commit 0f460a1ee148b648ee242c3157650287d4296260 -Author: Jason Jin -Date: Fri Jul 13 12:14:58 2007 +0800 - - Configurations for ATI video card BIOS emulator - - This patch add definition of the BIOS emulator and the ATI framebuffer - driver for MPC8641HPCN board. - - Signed-off-by: Jason Jin - Signed-off-by: Zhang Wei - -commit ece92f85053b8df613edcf05b26a416cbc3d629c -Author: Jason Jin -Date: Fri Jul 6 08:34:56 2007 +0800 - - This is a BIOS emulator, porting from SciTech for u-boot, mainly for - ATI video card BIOS. and can be used for x86 code emulation by some - modifications. - - Signed-off-by: Jason Jin - -commit 5072188acabde3178fac7f5a597150e6e74fd40c -Author: Jason Jin -Date: Fri Jul 6 08:33:33 2007 +0800 - - This is a framebuffer driver for ATI video card, can work for PCI9200, - X300, X700, X800 ATI video cards. - - Signed-off-by: Zhang Wei - Signed-off-by: Jason Jin - -commit 5728be389e65fd47f34b33c2596271eb4db751ae -Author: Wolfgang Denk -Date: Mon Aug 6 01:01:49 2007 +0200 - - Coding style cleanup. Update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit 8092fef4c29b395958bb649647da7e3775731517 -Author: Martin Krause -Date: Tue Dec 12 14:26:01 2006 +0100 - - Add functions to list of exported functions - - Additionally export the following fuctions (to make trab_config build again): - - simple_strtol() - - strcmp() - - Also bump the ABI version to reflect this change - - Signed-off-by: Martin Krause - -commit 63cec5814fab5d2b1c86982327433807a5ac0249 -Author: Ed Swarthout -Date: Thu Aug 2 14:09:49 2007 -0500 - - Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. - - All of the PCI/PCI-Express driver and initialization code that - was in the MPC8641HPCN port has now been moved into the common - drivers/fsl_pci_init.c. In a subsequent patch, this will be - utilized by the 85xx ports as well. - - Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. - - Also enable the second PCI-Express controller on 8641 - by getting its BATS and CFG_ setup right. - - Fixed a u16 vendor compiler warning in AHCI driver too. - - Signed-off-by: Ed Swarthout - Signed-off-by: Zhang Wei - Signed-off-by: Jon Loeliger - -commit a274ca4f6d68830e7c916f897561cff8c4101c38 -Author: Michal Simek -Date: Sun Aug 5 22:33:05 2007 +0200 - - [FIX] Coding style cleanup - -commit af8377d4eb3a0ac5a831830d5ce63fbf65fecb7f -Author: Michal Simek -Date: Sun Aug 5 16:13:31 2007 +0200 - - [FIX] Xilinx Uartlite driver - Because PPC405 can use UARTLITE serial interface and - Microblaze can use Uart16550 serial interface not only Uartlite. - -commit 98889edd50aadf862071eb5664747ad0d568a20e -Author: Michal Simek -Date: Sun Aug 5 15:54:53 2007 +0200 - - [FIX] Change configuration for XUPV2P Microblaze board - -commit 537091b4eed9302865d03fef3f7212b4fe5cf28f -Author: Michal Simek -Date: Sun Aug 5 15:53:50 2007 +0200 - - [PATCH] Added support for Xilinx Emac community driver - -commit 86b116b1b1e165ca4840daefed36d2e3b8460173 -Author: Bartlomiej Sieka -Date: Fri Aug 3 12:08:16 2007 +0200 - - cm1_qp1 -> cm5200: single U-Boot image for modules from the cm5200 family. - - Add the ability for modules from the Schindler cm5200 family to use a - single U-Boot image: - - rename cm1_qp1 to cm5200 - - add run-time module detection - - parametrize SDRAM configuration according to the module we are running on - - Few minor, board-specific fixes included in this patch: - - better MAC address handling - - updated default environment ('update' command uses +{filesize} now) - - improved error messages in the auto-update code - - allow booting U-Boot from RAM (CFG_RAMBOOT) - - Signed-off-by: Grzegorz Bernacki - Signed-off-by: Piotr Kruszynski - Signed-off-by: Bartlomiej Sieka - -commit c7e717ebc2b044d7a71062552c9dc0f54ea9b779 -Author: Andy Fleming -Date: Fri Aug 3 04:05:25 2007 -0500 - - Add Marvell 1149 PHY support to the TSEC - -commit b1b54e352028ed370c3aa95d6fdeb9d64c5d2f86 -Author: Wolfgang Denk -Date: Thu Aug 2 21:27:46 2007 +0200 - - Coding style cleanup, update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 63e22764d2f8653f68888c667eb65b3996b52680 -Author: Wolfgang Denk -Date: Thu Aug 2 10:11:18 2007 +0200 - - Minor cleanup of _nand build rules. - -commit 9ca8d79de096c65b9b9c867259b3ff4685f775ef -Author: Stefan Roese -Date: Thu Aug 2 08:33:56 2007 +0200 - - ppc4xx: Code cleanup - - Signed-off-by: Stefan Roese - -commit c92409812206ac67a7fa7aae298539a9c3804a46 -Author: Grzegorz Bernacki -Date: Tue Jul 31 18:51:48 2007 +0200 - - [ppc440SPe] Graceful recovery from machine check during PCIe configuration - - During config transactions on the PCIe bus an attempt to scan for a - non-existent device can lead to a machine check exception with certain - peripheral devices. In order to avoid crashing in such scenarios the - instrumented versions of the config cycle read routines are introduced, so - the exceptions fixups framework can gracefully recover. - - Signed-off-by: Grzegorz Bernacki - Acked-by: Rafal Jaworowski - -commit dec99558b9ea75a37940d07f41a3565a50b54ad1 -Author: Rafal Jaworowski -Date: Tue Jul 31 18:19:54 2007 +0200 - - [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.A - - This brings back separate settings for PCIe bus numbers depending on chip - revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa - commit. 440SPe rev. A does NOT work properly with the same settings as for - the rev. B (no devices are seen on the bus during enumeration). - - Signed-off-by: Rafal Jaworowski - -commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 -Author: Wolfgang Denk -Date: Thu Aug 2 00:48:45 2007 +0200 - - Fix build errors and warnings / code cleanup. - - Signed-off-by: Wolfgang Denk - -commit d2f68006627eda6cb6c7f364bddf621dbfd2fc68 -Author: Eugene OBrien -Date: Tue Jul 31 10:24:56 2007 +0200 - - ppc4xx: Update AMCC Bamboo 440EP support - - Changed storage type of cfg_simulate_spd_eeprom to const - Changed storage type of gpio_tab to stack storage - (Cannot access global data declarations in .bss until afer code relocation) - - Improved SDRAM tests to catch problems where data is not uniquely addressable - (e.g. incorrectly programmed SDRAM row or columns) - - Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules - Fixed AM29LV320DT (OpCode Flash) sector map - - Signed-off-by: Eugene OBrien - Signed-off-by: Stefan Roese - -commit ea9f6bce383cc9fbcdee28b5836109b1a6dba574 -Author: Stefan Roese -Date: Tue Jul 31 08:37:01 2007 +0200 - - ppc4xx: Update 440EPx lwmon5 board support - - - Clear ECC status regs after ECC POST test - - Set dcbz for ECC generation with caches enabled as default - - Code cleanup - - Signed-off-by: Stefan Roese - -commit 27a528fb41433c4c1e2b5d6bd3fd8d78606fc724 -Author: Stefan Roese -Date: Mon Jul 30 11:04:57 2007 +0200 - - ppc4xx: Only print ECC related info when the error bis are set - - Signed-off-by: Stefan Roese - -commit e36220a4baf1f188ba60f17e9d0f043069b1362a -Author: Matthias Fuchs -Date: Fri Jul 27 16:44:31 2007 +0200 - - new FPGA image for PLU405 board - - new FPGA image for PLU405 board with improved CompactFlash timing - - Signed-off-by: Matthias Fuchs - -commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6 -Author: Rafal Jaworowski -Date: Fri Jul 27 14:43:59 2007 +0200 - - [ADS5121] Support for the ADS5121 board - - The following MPC5121e subsystems are supported: - - - low-level CPU init - - NOR Boot Flash (common CFI driver) - - DDR SDRAM - - FEC - - I2C - - Watchdog - - Signed-off-by: Grzegorz Bernacki - Signed-off-by: Rafal Jaworowski - Signed-off-by: Jan Wrobel - -commit 1863cfb7b100ba0ee3401799457a01dc058745f8 -Author: Rafal Jaworowski -Date: Fri Jul 27 14:22:04 2007 +0200 - - [PPC] Remove unused MSR_USER definition - - Signed-off-by: Rafal Jaworowski - -commit d4024bb72dd81695ec099b2199eda0d27c623e62 -Author: John Otken -Date: Thu Jul 26 17:49:11 2007 +0200 - - ppc4xx: Add support for AMCC 405EP Taihu board - - Signed-off-by: John Otken - -commit b66091de6c7390620312c2501db23d8391e7cabb -Author: Anatolij Gustschin -Date: Thu Jul 26 15:08:01 2007 +0200 - - ppc4xx: lwmon5: Update Lime initialization - - Change Lime SDRAM initialization to now support 100MHz and - 133MHz (if enabled). Also the framebuffer is initialized to - display a blue rectangle with a white border. - - Signed-off-by: Anatolij Gustschin - Signed-off-by: Stefan Roese - -commit 9f24a808f17fc0f37b7fb4805f734741335caecc -Author: Stefan Roese -Date: Tue Jul 24 09:52:52 2007 +0200 - - ppc4xx: lwmon5: Support for 128 MByte NOR FLASH added - - The used Intel NOR FLASH chips have internally two dies, and are now - treated as two seperate chips. - - Signed-off-by: Stefan Roese - -commit aedf5bde179ecfbd0a96130d18996a96518b785f -Author: Stefan Roese -Date: Tue Jul 24 07:20:09 2007 +0200 - - ppc4xx: Fix lwmon5 interrupt controller setup (polarity, trigger...) - - As suggested by Hakan Eryigit, here an updated setup for the lwmon5 - interrupt controller. - - Signed-off-by: Stefan Roese - -commit a71d96eac8130b53a91f93cd10c70fca0db18d52 -Author: Stefan Roese -Date: Fri Jul 20 15:03:44 2007 +0200 - - ppc4xx: Fix bug with default GPIO output value - - As spotted by Matthias Fuchs, the default output values for all GPIO1 - outputs were not setup correctly. This patch fixes this issue. - - Signed-off-by: Stefan Roese - -commit 531e3e8b831f357056448fa573137d5fb37000fd -Author: Pavel Kolesnikov -Date: Fri Jul 20 15:03:03 2007 +0200 - - POST: Add ECC POST for the lwmon5 board - - This patch adds ECC Post test for the Lwmon5 board based - on PPC440EPx to U-Boot. - - Signed-off-by: Pavel Kolesnikov - Acked-by: Yuri Tikhonov - Acked-by: Stefan Roese - -commit cc3023b9f95d7ac959a764471a65001062aecf41 -Author: Rafal Jaworowski -Date: Thu Jul 19 17:12:28 2007 +0200 - - Fix breakage of 8xx boards from recent commit. - - This patch fixes the negative consequences for 8xx of the recent - "ppc4xx: Clean up 440 exceptions handling" commit. - - Signed-off-by: Rafal Jaworowski - -commit c883f6ea32dce91f07670b3aafecf6c99b1e5341 -Author: Stefan Roese -Date: Mon Jul 16 13:11:12 2007 +0200 - - Coding style cleanup - - Signed-off-by: Stefan Roese - -commit 8848ec858f74ed6dab06fb6d5ddc933e0a1328bf -Author: Stefan Roese -Date: Mon Jul 16 10:02:12 2007 +0200 - - ppc4xx: Code cleanup - - Signed-off-by: Stefan Roese - -commit 2a49fc17d09020e7ebd9536694d99d20e419fcb8 -Author: Stefan Roese -Date: Mon Jul 16 10:01:38 2007 +0200 - - ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setup - - Signed-off-by: Stefan Roese - -commit df3f17422aeb03fb81a7ac8c78d2b05d05aa4cf9 -Author: Stefan Roese -Date: Mon Jul 16 10:00:43 2007 +0200 - - ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c - - The new boardspecific DDR2 controller configuration is used for the Yucca - board. Now the Yucca board with 440SPe Rev. A chips is also supported. - - Signed-off-by: Stefan Roese - -commit 6ed14addf97c8cd8f531e9ae7b2d3e222fffd53e -Author: Stefan Roese -Date: Mon Jul 16 09:57:00 2007 +0200 - - ppc4xx: Add new weak functions to support boardspecific DDR2 configuration - - The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better - support non default, boardspecific DDR(2) controller configuration. - - Signed-off-by: Stefan Roese - -commit 5743a9207a370b90f09b20ebd61167c806b937f3 -Author: Stefan Roese -Date: Mon Jul 16 08:53:51 2007 +0200 - - ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup - - The new function remove_tlb() can be used to remove the TLB's used to - map a specific memory region. This is especially useful for the DDR(2) - setup routines which configure the SDRAM area temporarily as a cached - area (for speedup on auto-calibration and ECC generation) and later - need this area uncached for normal usage. - - Signed-off-by: Stefan Roese - -commit 0c0a9cda1bde37106520476ed486bd67eb8d30ae -Author: Michal Simek -Date: Mon Jul 16 00:31:07 2007 +0200 - - [PATCH] Support for Xilinx EmacLite controller - -commit 3a6cab844cf74f76639d795e0be8717e02c86af7 -Author: Wolfgang Denk -Date: Sat Jul 14 22:51:02 2007 +0200 - - Update CHANGELOG - - Signed-off-by: Wolfgang Denk - -commit 5280f352c8da33b1d7fbf448768717d9e16ff9a1 -Author: Michal Simek -Date: Sat Jul 14 13:11:28 2007 +0200 - - [FIX] support for simply measuring time - -commit 91bb4ca665d2e0cf7f60c4b5b370990250ec0c43 -Author: Michal Simek -Date: Sat Jul 14 12:41:23 2007 +0200 - - [FS] Added support for ROMFS - -commit 011595307731a7a67a7445d107c279d031e8ab97 -Author: Heiko Schocher -Date: Sat Jul 14 01:06:58 2007 +0200 - - [PCS440EP] - fix compile error, if BUILD_DIR is used - -commit 5a2f1098d81ad58b309e5e558d0492643166a799 -Author: Michal Simek -Date: Sat Jul 14 00:18:48 2007 +0200 - - [PATCH] Support time without timer - -commit a476ca2ac2217ddd05a2bf0c514075814b10a3c0 -Author: Michal Simek -Date: Fri Jul 13 21:43:55 2007 +0200 - - [PATCH] Remove problem with disabled BARREL SHIFTER - -commit 55e26ad62107d2f14f757de3ae0b14b9aa7aed94 -Author: Michal Simek -Date: Fri Jul 13 21:41:44 2007 +0200 - - [FIX] correct help for rspr - -commit fad63407154f46246ce80d53a9c669a44362ac67 -Author: Heiko Schocher -Date: Fri Jul 13 09:54:17 2007 +0200 - - make show_boot_progress () weak. - - Signed-off-by: Heiko Schocher - -commit 907902472391b6ca1876ec300687562ecaf459b1 -Author: Heiko Schocher -Date: Fri Jul 13 08:26:05 2007 +0200 - - [PCS440EP] - The DIAG LEDs are now blinking, if an error occur - - fix compile error, if BUILD_DIR is used - - Signed-off-by: Heiko Schocher - -commit a2e1c7098cf9574386b0c96841dfc8ea5cc93578 -Author: Stefan Roese -Date: Thu Jul 12 16:32:08 2007 +0200 - - ppc4xx: Change receive buffer handling in the 4xx emac driver - - This change fixes a bug in the receive buffer handling, that - could lead to problems upon high network traffic (broadcasts...). - - Signed-off-by: Stefan Roese - -commit 239f05ee4dd4cfe0b50f251b533dcebe9e67c360 -Author: Wolfgang Denk -Date: Thu Jul 12 01:45:34 2007 +0200 - - Update CHANGELOG, minor coding style cleanup. - - Signed-off-by: Wolfgang Denk - -commit 5a56af3b522ba47fb33a3fee84d23bf1e5429654 -Author: Andy Fleming -Date: Fri Jun 8 16:41:18 2007 -0500 - - Remove erroneous errata code from Marvel 88E1111S driver - - The Marvel 88E1111S driver for the TSEC was copied from the - 88E1101 driver, and included a fix for an erratum which does not - exist on that part. Now it is removed - - Signed-off-by: Andy Fleming - -commit 982efcf23fd03647e01e2fbe28a7a36239156cc0 -Author: Andy Fleming -Date: Tue Jun 5 16:38:44 2007 -0500 - - From: eran liberty - - adds the reset register to 85xx immap - - Signed-off-by: Eran Liberty - Signed-off-by: Andy Fleming - -commit d3ec0d943a045bdb99e159e7bbc77430e09f11d7 -Author: Andy Fleming -Date: Thu May 10 17:50:01 2007 -0500 - - Polished the 85xx ADS config files - - Made the boot commands use device trees by default. - Also moved the ramdisk to 1000000 (I think the previous address - was getting overridden during boot). - - Signed-off-by: Andy Fleming - -commit bfb37b32d1b0b03f18077dba49cc66a6e76fa038 -Author: Ed Swarthout -Date: Wed May 9 11:03:32 2007 -0500 - - 8544ds: Fix Makefile after moving pixis to board/freescale. - - The OBJTREE != SRCTREE build scenario was broken. - This fixes it. - - Signed-off-by: Ed Swarthout - Signed-off-by: Jon Loeliger - -commit 2a3cee43c3b71fa5b8d91db19f05067865290f3e -Author: Andy Fleming -Date: Wed May 9 00:54:20 2007 -0500 - - tsec: Fix PHY code to match first driver - - Jarrold Wen noticed that the generic PHY code always matches - under the current implementation. Change it so the first match - wins, and *only* unknown PHYs trigger the generic driver - - Signed-off-by: Andy Fleming - -commit ccc091aac61a38cd998d575d92f7232e256d6312 -Author: Andy Fleming -Date: Tue May 8 17:27:43 2007 -0500 - - Add support for CPM device tree configuration to 8560 ADS - - * Adds code to modify CPM frequencies - * Cleans up the config file to #define TSEC and (for now) #undef FCC - * Adds the MII command for all 8560 ADS configurations - * Updates config file to provide convenience commands for booting - with a device tree - - Signed-off-by: Vitaly Bordug - Signed-off-by: Andy Fleming - -commit 7507d56ccaf7aae1c474342a9a5540165cd7e9d9 -Author: Andy Fleming -Date: Tue May 8 17:23:02 2007 -0500 - - Fix Marvell 88e1145 PHY init code - - Fix a bug in the Marvell 88e1145 PHY init code in the TSEC driver - where the reset was being done after the errata code instead of - before. - - Signed-off-by: Haiying Wang - Signed-off-by: Andy Fleming - -commit 5dc210dec5bace98a50b6ba905347890091a9bb0 -Author: Ed Swarthout -Date: Wed Jul 11 14:52:16 2007 -0500 - - Add simple agent/end-point configuration in PCI AutoConfig for PCI_CLASS_PROCESSOR_POWERPC. - - Signed-off-by: Ed Swarthout - -commit e8b85f3ba4cd8930e0a2fea2100c815d64201765 -Author: Ed Swarthout -Date: Wed Jul 11 14:52:08 2007 -0500 - - pciauto setup bridge - - The P2P bridge bus numbers programmed into the device are relative to - hose->first_busno. - - Signed-off-by: Ed Swarthout - -commit 571f49fa717004ca4268b4e24057efc7bf9f987b -Author: Ed Swarthout -Date: Wed Jul 11 14:52:01 2007 -0500 - - Support PCIe extended config registers - - FSL PCIe block has extended cfg registers in the 100 and 400 range. - For example, to read the LTSSM register: pci display .0 404 1 - - Signed-off-by: Ed Swarthout - -commit ba5feb12581bb2912ce301e4866b71f846e9fc07 -Author: Ed Swarthout -Date: Wed Jul 11 14:51:48 2007 -0500 - - Minor improvements to drivers/pci_auto.c - - - Make pciauto_{pre,post}scan_setup_bridge non-static - - Added physical address display in debug messages. - - Signed-off-by: Ed Swarthout - -commit 40e81addab7bb74d20ddf681ce9babc880a828ee -Author: Ed Swarthout -Date: Wed Jul 11 14:51:35 2007 -0500 - - Start pci hose scan from hose->current_busno. - - Ensure hose->current_busno is not less than first_busno. This fixes - broken board code which leaves current_busno=0 when first_busno is - greater than 0 for the cases with multiple controllers. - - Signed-off-by: Ed Swarthout - -commit 3865b1fb7843a08ad49a6319a36415752276ff48 -Author: Stefan Roese -Date: Wed Jul 11 12:13:53 2007 +0200 - - Fix some compile problems introduced by the latest CFG_CMD_xxx cleanup - - Signed-off-by: Stefan Roese - -commit fa1df308926a6f70e3504c57514ef27ac31fd13a -Author: Bartlomiej Sieka -Date: Wed Jul 11 20:11:07 2007 +0200 - - CM1.QP1: Support for the Schindler CM1.QP1 board. - - Signed-off-by: Piotr Kruszynski - Signed-off-by: Bartlomiej Sieka - -commit 96e1d75be8193ca79e4215a368bf9d7f2362450f -Author: Heiko Schocher -Date: Wed Jul 11 18:39:11 2007 +0200 - - [PCS440EP] - Show on the DIAG LEDs, if the SHA1 check failed - - now the Flash ST M29W040B is supported (not tested) - - fix the "led" command - - fix compile error, if BUILD_DIR is used - - Signed-off-by: Heiko Schocher - -commit e9514751cfa5cce61ea699fa0d3eb37898a5eeb5 -Author: Stefan Roese -Date: Sun Jul 8 13:44:27 2007 +0200 - - Fix malloc problem introduced with the relocation fixup for the PPC platform - - The relocation fixup didn't handle the malloc pointer initialization - correctly. This patch fixes this problem. Tested successfully on 4xx. - The relocation fixup patches for 4xx will follow soon. - - Signed-off-by: Stefan Roese - -commit 0dca874db62718e41253659e60f3a1de7eb418ce -Author: TsiChung -Date: Tue Jul 10 15:45:43 2007 -0500 - - Cache update and added CFG_UNIFY_CACHE - - Enabled cache in cpu_init_f() for faster flash to mem allocation. Updated cache handling in start.S. Applied cache invalidate in fec_send() and fec_recv(). Added CFG_UNIFY_CACHE for CF V3 only. - - Signed-off-by: TsiChung - -commit 52b017604a8f4d4a795880ef6e7861d7f2f1b005 -Author: TsiChungLiew -Date: Thu Jul 5 23:36:16 2007 -0500 - - Update header file. Include dtimer_intr_setup(). Changed timer divider to global define. - - Include immap.h and timer.h. Moved dtimer interrupt setup to dtimer_intr_setup() from cpu/mcf532x/interrupts.c. Changed (CFG_CLK /1000000) -1 << 8 to CFG_TIMER_PRESCALER - - Signed-off-by: TsiChungLiew - -commit 5cdc07c7ef8f08ea55d3c47ed9221d91aa6d5fac -Author: TsiChungLiew -Date: Thu Jul 5 23:31:25 2007 -0500 - - Update header files - - Include immap.h and renamed mcfrtc.h to rtc.h - - Signed-off-by: TsiChungLiew - -commit 2870e98ac8e5553e9187b12a47e5f46babb53990 -Author: TsiChungLiew -Date: Thu Jul 5 23:29:21 2007 -0500 - - Add mcffec_initialize() - - Added mcffec_initialize() in eth_initialize() - - Signed-off-by: TsiChungLiew - -commit 45a25bfd0c52f8a3fa137216bc94d32f90bedc5d -Author: TsiChungLiew -Date: Thu Jul 5 23:27:40 2007 -0500 - - Update header file and clean up - - Include immap.h - - Signed-off-by: TsiChungLiew - -commit 0cee9c66318602c856a899ae5fa7579ccba6443a -Author: TsiChungLiew -Date: Thu Jul 5 23:23:15 2007 -0500 - - New uart structure and defines - - Seperated from mcfuart.h - - Signed-off-by: TsiChungLiew - -commit a90e79de8d99e9c9d69d60bfff9f24c337165900 -Author: TsiChungLiew -Date: Thu Jul 5 23:22:31 2007 -0500 - - New timer structure and defines - - Seperated from mcftimer.h - - Signed-off-by: TsiChungLiew - -commit e04acb2eba4782489417240eff76e20e176aec10 -Author: TsiChungLiew -Date: Thu Jul 5 23:21:09 2007 -0500 - - Rename mcfrtc to rtc - - Since it is already in m68k folder, un-necessary to pad mcf. Replaced immap_5329.h and m5329.h to immap.h - - Signed-off-by: TsiChungLiew - -commit 2bd806fe4fc23958b8f78778199e7a6e3f8f6ad5 -Author: TsiChungLiew -Date: Thu Jul 5 23:17:36 2007 -0500 - - Rename mcfserial.c. Update include header - - Renamed mcfserial.c to mcfuart.c. Modified Makefile for mcfuart.o from mcfserial.o. Replace immap_5329.h and m5329.h to immap.h - - Signed-off-by: TsiChungLiew - -commit f2208fbc2eb9de3f4285bfaa021c6ebae16c9b0e -Author: TsiChungLiew -Date: Thu Jul 5 23:13:58 2007 -0500 - - Header file update, clean up and cache handling - - Replaced immap_5329.h and m5329.h with immap.h. Included cache_invalid. - - Signed-off-by: TsiChungLiew - -commit 2e3f25ae9082daa9f5d181db45dfbc2e52ce0f97 -Author: TsiChungLiew -Date: Thu Jul 5 23:10:40 2007 -0500 - - Create interrupts.c and modify Makefile - - interrupt_init() and dtimer_intr_setup() are placed in interrupts.c. Added interrupts.o to Makefile - - Signed-off-by: TsiChungLiew - -commit ddd104f1ed655eda50c06ba636237a83ed943f34 -Author: TsiChungLiew -Date: Thu Jul 5 23:06:55 2007 -0500 - - Enable Icache - - Signed-off-by: TsiChungLiew - -commit b9bf3de377b2bae70c983c9b97feae914999e735 -Author: TsiChungLiew -Date: Thu Jul 5 23:05:31 2007 -0500 - - Update header file and some clean up - - Replaced immap_5329.h and m5329.h with immap.h. Removed whitespaces. - - Signed-off-by: TsiChungLiew - -commit 84a015b52ec820a5ae173717d78516de731c89c2 -Author: TsiChungLiew -Date: Thu Jul 5 23:03:28 2007 -0500 - - Update header file and enable icache - - Replaced immap_5329.h and m5329.h with immap.h. Enabled icache_enable() in cpu_init_r(). - - Signed-off-by: TsiChungLiew - -commit 7a17e759c7a8b58e910daf54df611e94fc8ca074 -Author: TsiChungLiew -Date: Thu Jul 5 23:01:22 2007 -0500 - - Update header file and removed interrupt_init() - - Replace immap_5329.h and m5329.h with immap.h. Removed interrupt_init() and placed it in interrupts.c - - Signed-off-by: TsiChungLiew - -commit 3b635492c95bd0d6e08f93f699821cba1f602a64 -Author: TsiChungLiew -Date: Thu Jul 5 22:57:46 2007 -0500 - - Update for flash.o and mii.o - - Removed flash.o and added mii.o - - Signed-off-by: TsiChungLiew - -commit c5ded275d839e4ff79f41718d50a835d989f57bc -Author: TsiChungLiew -Date: Thu Jul 5 22:56:19 2007 -0500 - - MII functions calls. - - Signed-off-by: TsiChungLiew - -commit 427c814104560e29bda14955c67703245aaaa5b4 -Author: TsiChungLiew -Date: Thu Jul 5 22:54:42 2007 -0500 - - Removed MII functions and replaced immap_5329.h and m5329.h with immap.h. - - The removed MII routines will be placed in mii.c. - - Signed-off-by: TsiChungLiew - -commit 01a793fda09c63df5a496f09dc1c7cb26e6751a2 -Author: TsiChungLiew -Date: Thu Jul 5 22:51:05 2007 -0500 - - Duplicate code - - There is a Common Flash Interface Driver existed. To use the CFI driver, define CFG_FLASH_CFI in configuration file. - - Signed-off-by: TsiChungLiew - -commit 2744354a8437b8f78db178e30660215688bff570 -Author: TsiChungLiew -Date: Thu Jul 5 22:46:38 2007 -0500 - - Seperate old structure defines and new structure defines - - Removed new uart structure and defines to uart.h - - Signed-off-by: TsiChungLiew - -commit 2bd58608dbcff8890ca9a0c59e861ac24f8bb230 -Author: TsiChungLiew -Date: Thu Jul 5 22:45:01 2007 -0500 - - Seperate old structure defines and new structure defines - - New timer structure and defines will move to new timer.h - - Signed-off-by: TsiChungLiew - -commit 8cd5cd6de4ff92e03978338ed7aeb3ce7b7b9784 -Author: TsiChungLiew -Date: Thu Jul 5 22:42:23 2007 -0500 - - Clean up - - Removed whitespace - - Signed-off-by: TsiChungLiew - -commit 514871f565dd8bd1121e4a3ac1665a790e20b8f2 -Author: TsiChungLiew -Date: Thu Jul 5 22:41:24 2007 -0500 - - Clean up - - Replaced whitespace with tabs - - Signed-off-by: TsiChungLiew - -commit 48dbfeabc7afffe30609a4489f10c22cb67ef7dd -Author: TsiChungLiew -Date: Thu Jul 5 22:39:07 2007 -0500 - - Create new header file and move peripherals base address from configs file to new header file. - - Create new header file to include immap_5xxx.h and m5xxx.h and to share among drivers without update in driver file each processor is added. Moved peripherals base address and defines from configs file to immap.h. - - Signed-off-by: TsiChungLiew - -commit be296e31c4411f96d9cb3d2afc8fcb006867abfa -Author: TsiChungLiew -Date: Thu Jul 5 22:24:58 2007 -0500 - - Revert file mode - - Changed MAKEALL file mode to executable, removed executable file mode from Makefile - - Signed-off-by: TsiChungLiew - -commit b3aff0cb9ecf236d7e8c93761dd1dadf6837a582 -Author: Jon Loeliger -Date: Tue Jul 10 11:19:50 2007 -0500 - - disk/ doc/ lib_*/ and tools/: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger - -commit ddb5d86f0215bcb6c293510c50eb050e92883b7a -Author: Jon Loeliger -Date: Tue Jul 10 11:13:21 2007 -0500 - - drivers/: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger - -commit f40a7f3e3888b42a43674b099e5470022c8c544c -Author: Jon Loeliger -Date: Tue Jul 10 11:07:56 2007 -0500 - - fs/: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger - -commit 610f2e9c28a9c101e09fa1b78143cf5f00ed1593 -Author: Jon Loeliger -Date: Tue Jul 10 11:05:02 2007 -0500 - - net/: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger - -commit 902531788376046da212afd1661cffb62f3daa1c -Author: Jon Loeliger -Date: Tue Jul 10 11:02:44 2007 -0500 - - common/: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger - -commit d39b57415838c73fb0a37eca84de3c68ba990586 -Author: Jon Loeliger -Date: Tue Jul 10 10:48:22 2007 -0500 - - board/[j-z]*: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger - -commit 77a318545d57aefa844752465b94c7e09a3f26d0 -Author: Jon Loeliger -Date: Tue Jul 10 10:39:10 2007 -0500 - - board/[A-Za-i]*: Remove lingering references to CFG_CMD_* symbols. - - Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. - Those always evaluated TRUE, and thus were always compiled - even when IDE really wasn't defined/wanted. - - Signed-off-by: Jon Loeliger - -commit 068b60a0eb7e73b243ca55399f2a7df76e2c3f3d -Author: Jon Loeliger -Date: Tue Jul 10 10:27:39 2007 -0500 - - cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger - -commit 079a136c3588814784561d6e4856970ee82d6e2a -Author: Jon Loeliger -Date: Tue Jul 10 10:12:10 2007 -0500 - - include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger - -commit 7f5c01577400c74cc5bac74f41dd0d3c79df623c -Author: Jon Loeliger -Date: Tue Jul 10 09:38:02 2007 -0500 - - include/configs/[g-o]*: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger - -commit 80ff4f99b84b64edca3fd10da365ec1493be1c95 -Author: Jon Loeliger -Date: Tue Jul 10 09:29:01 2007 -0500 - - include/configs/[a-e]*: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger - -commit a1aa0bb502e25fd598b5e0ccdfb2c174921d714a -Author: Jon Loeliger -Date: Tue Jul 10 09:22:23 2007 -0500 - - include/configs/[P-Z]*: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger - -commit 659e2f6736232a08acca8785c206e2b4d9cd07d7 -Author: Jon Loeliger -Date: Tue Jul 10 09:10:49 2007 -0500 - - include/configs/[J-O]*: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger - -commit 11799434c5ff15a612577bb1ad1f4ea1a0595e4b -Author: Jon Loeliger -Date: Tue Jul 10 09:02:57 2007 -0500 - - include/configs/[A-I]*: Cleanup BOOTP and lingering CFG_CMD_*. - - Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h - used to be included but CONFIG_BOOTP_MASK was not defined. - - Remove lingering references to CFG_CMD_* symbols. - - Signed-off-by: Jon Loeliger - -commit 1fe80d79c5c4e52d3410a7ab4b8515da095cdab3 -Author: Jon Loeliger -Date: Mon Jul 9 22:08:34 2007 -0500 - - Finally retire cmd_confdefs.h and CONFIG_BOOTP_MASK! - - All of the choices for CONFIG_BOOTP_ are now documented in - the README file. You must now individually select exactly - the set that you want using a series of - #define CONFIG_BOOTP_ - statements in the board port config files now. - - Signed-off-by: Jon Loeliger - -commit d3b8c1a743dcd31625c99e6a44590f207eb00028 -Author: Jon Loeliger -Date: Mon Jul 9 21:57:31 2007 -0500 - - include/configs/[m-z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger - -commit 2fd90ce575b02d189cbf443c85309bcd001aa393 -Author: Jon Loeliger -Date: Mon Jul 9 21:48:26 2007 -0500 - - include/configs/[a-m]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger - -commit 37d4bb70586659dedef1658ce1bed071be098aec -Author: Jon Loeliger -Date: Mon Jul 9 21:38:02 2007 -0500 - - include/configs/[T-Z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger - -commit 18225e8dd1950bd6dbf35011e436db7f474c187d -Author: Jon Loeliger -Date: Mon Jul 9 21:31:24 2007 -0500 - - include/configs/[P-S]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger - -commit 7be044e4ea644b0ef1c486dadc1a4c2665b4374d -Author: Jon Loeliger -Date: Mon Jul 9 21:24:19 2007 -0500 - - include/configs/[H-N]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger - -commit 5d2ebe1b3ef0055c661bb1a0d252bf252380069f -Author: Jon Loeliger -Date: Mon Jul 9 21:16:53 2007 -0500 - - include/configs/[A-G]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. - - Signed-off-by: Jon Loeliger - -commit f55f7f8d83f36021ab1f0e3d738f5d8c8083a7e3 -Author: Jon Loeliger -Date: Mon Jul 9 19:12:30 2007 -0500 - - Retire CONFIG_COMMANDS finally. - Strip old CFG_CMD_* symbols out. - - Signed-off-by: Jon Loeliger - -commit b5501f7d720fed99ab0b42c83f5dea52868ce007 -Author: Jon Loeliger -Date: Mon Jul 9 19:10:03 2007 -0500 - - Update README.* to reference new CONFIG_CMD_* names now. - - Signed-off-by: Jon Loeliger - -commit 4431283c7e6d54ae180d466e51bf2d97471a0ad9 -Author: Jon Loeliger -Date: Mon Jul 9 19:06:00 2007 -0500 - - cpu/m*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit 3a1ed1e1f922c419bb71f7df4949d783ade369fa -Author: Jon Loeliger -Date: Mon Jul 9 18:57:22 2007 -0500 - - cpu/[7a-ln-z]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit ab3abcbabd840928fb1eb5122118ca466b5e5013 -Author: Jon Loeliger -Date: Mon Jul 9 18:45:16 2007 -0500 - - board/[q-z]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit 3fe00109a5f12de55b6e25b1f98dfc24bc9090c9 -Author: Jon Loeliger -Date: Mon Jul 9 18:38:39 2007 -0500 - - board/[m-p]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit c508a4cefd8a953fc64957650506a035e6e3d9d1 -Author: Jon Loeliger -Date: Mon Jul 9 18:31:28 2007 -0500 - - board/[f-l]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit b9307262f8a9f3b5c9e15a6067eadc17407146f6 -Author: Jon Loeliger -Date: Mon Jul 9 18:24:55 2007 -0500 - - board/[d-e]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit fcec2eb93e126400009729328e797f12bc94f1fd -Author: Jon Loeliger -Date: Mon Jul 9 18:19:09 2007 -0500 - - board/[A-Za-c]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit a593814f2be0c9cdc3133cd550b167b8a988328f -Author: Jon Loeliger -Date: Mon Jul 9 18:10:50 2007 -0500 - - rtc/: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit 67350568f9d46e66c21829f3513b3db0caeb948b -Author: Jon Loeliger -Date: Mon Jul 9 18:05:38 2007 -0500 - - lib_{arm,avr32,blackfin,generic,i386}/: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit 7def6b34f910f08d7ef0a14646da067719237ca2 -Author: Jon Loeliger -Date: Mon Jul 9 18:02:11 2007 -0500 - - lib_{m68k,microblaze,mips,ppc}/: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit dd60d1223b99a88a7216f3e041fe40634ad4c2bb -Author: Jon Loeliger -Date: Mon Jul 9 17:56:50 2007 -0500 - - fs/: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit c91898bbc505aff3e12a807af88e76da18efb7ee -Author: Jon Loeliger -Date: Mon Jul 9 17:46:09 2007 -0500 - - tools/: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit 643d1ab23960950b52e0a2803c2d3ea4c558fa01 -Author: Jon Loeliger -Date: Mon Jul 9 17:45:14 2007 -0500 - - net/: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit cb51c0bf88f95a1bca68324b0126f8eed8b43273 -Author: Jon Loeliger -Date: Mon Jul 9 17:39:42 2007 -0500 - - drivers/[n-z]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit 07d38a17e964aec4c7827f0ee9a583bc8cc1ad6b -Author: Jon Loeliger -Date: Mon Jul 9 17:30:01 2007 -0500 - - drivers/[a-m]*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit cde5c64d17cf4834aa7b5c373f288bc7dad27b29 -Author: Jon Loeliger -Date: Mon Jul 9 17:22:37 2007 -0500 - - disk/: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit 639221c76c88215bd55af83ad174fc30d1940f8f -Author: Jon Loeliger -Date: Mon Jul 9 17:15:49 2007 -0500 - - include/: Remove obsolete references to CONFIG_COMMANDS - Mostly removed from comments here. - - Signed-off-by: Jon Loeliger - -commit 4ef218f6fdf8d747f4589da5252b004e7d2c2876 -Author: Wolfgang Denk -Date: Tue Jul 10 00:01:28 2007 +0200 - - Coding style cleanup; update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit c8603cfbd4573379a6076c9c208545ba2bbf019a -Author: Stefan Roese -Date: Mon Jul 9 11:00:24 2007 +0200 - - Small coding style cleanup - - Signed-off-by: Stefan Roese - -commit 0f92c7e7c9a62755b1457d3c46f93c8c1f6c19fc -Author: Matthias Fuchs -Date: Mon Jul 9 10:10:08 2007 +0200 - - Migrate esd 405EP boards to new NAND subsystem - - Remove unused CFG_NAND_LEGACY define - - These boards to not have NAND. - - Signed-off-by: Matthias Fuchs - -commit bd84ee4c2020c3a6861f4bb2e7ea0fb49f82e803 -Author: Matthias Fuchs -Date: Mon Jul 9 10:10:06 2007 +0200 - - Migrate esd 405EP boards to new NAND subsystem - - Migrate esd 405EP boards to new NAND subsystem - - -cleanup - -use correct io accessors (in/out_be32()) - - Signed-off-by: Matthias Fuchs - -commit e09f7ab5749c345f924da272bea0521a73af5b11 -Author: Matthias Fuchs -Date: Mon Jul 9 10:10:04 2007 +0200 - - Migrate esd 405EP boards to new NAND subsystem - - This patch prepares the migration from the legacy NAND driver - to U-Boot's new NAND subsystem for esd boards. - - Signed-off-by: Matthias Fuchs - -commit c3517f919d0f61650cf3027fd4faf0f631142f6c -Author: Jon Loeliger -Date: Sun Jul 8 18:10:08 2007 -0500 - - common/* non-cmd*: Remove obsolete references to CONFIG_COMMANDS - - Signed-off-by: Jon Loeliger - -commit fd9bcaa35be64fe41a4223fdb6ecdbad52470b39 -Author: Jon Loeliger -Date: Sun Jul 8 18:05:39 2007 -0500 - - common/cmd_[p-x]*: Remove obsolete references to CONFIG_COMMANDS. - - Signed-off-by: Jon Loeliger - -commit c76fe47425afc7d5d670ff0539823c85d65d9c42 -Author: Jon Loeliger -Date: Sun Jul 8 18:02:23 2007 -0500 - - common/cmd_[i-n]*: Remove obsolete references to CONFIG_COMMANDS. - - Signed-off-by: Jon Loeliger - -commit baa26db4113679b80970ff447d91cc10217742a6 -Author: Jon Loeliger -Date: Sun Jul 8 17:51:39 2007 -0500 - - common/cmd_[af]*: Remove obsolete references to CONFIG_COMMANDS. - - Signed-off-by: Jon Loeliger - -commit af075ee96e52dda7b6bca6c937588aeaaec5f2cd -Author: Jon Loeliger -Date: Sun Jul 8 17:02:01 2007 -0500 - - Clear up confusion over the CMD_POST and POST_DIAG mess. - - For some reason, CONFIG_POST permeated as CONFIG_CMD_POST_DIAG - when it really means just CONFIG_CMD_DIAG. There is no CMD_POST. - Clear this mess up some. - - Signed-off-by: Jon Loeliger - -commit b3631487105a57ab7cbadfc26efbaf9676275018 -Author: Jon Loeliger -Date: Sun Jul 8 15:45:08 2007 -0500 - - Remove references to the old cmd_confdefs.h include file. - - Signed-off-by: Jon Loeliger - -commit a22d4da95e20049b4daa1c2a022f61e8a72f2fb6 -Author: Jon Loeliger -Date: Sun Jul 8 15:42:59 2007 -0500 - - include/configs: Catch some CONFIG_CMD_* conversion stragglers. - - Use new CONFIG_CMD_* in lwmon5.h board config file. - Fix CONFIG_CMD_* typo braindamage in omap1510inn.h - - Signed-off-by: Jon Loeliger - -commit a5562901661bd428f7e5feb333f796372cb81019 -Author: Jon Loeliger -Date: Sun Jul 8 15:31:57 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various [TUVWZYZ]* named board config files. - - Signed-off-by: Jon Loeliger - -commit fe7f782d5b8c64a0195c68c31a0a11d4f641355e -Author: Jon Loeliger -Date: Sun Jul 8 15:02:44 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various S* named board config files. - - Signed-off-by: Jon Loeliger - -commit e9a0f8f15c11f337967aa0600ad6e8af33037f50 -Author: Jon Loeliger -Date: Sun Jul 8 15:12:40 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various R* named board config files. - - Signed-off-by: Jon Loeliger - -commit 12aa9fd23d724bd6ab88e1baa0db35133a27303f -Author: Jon Loeliger -Date: Sun Jul 8 14:55:07 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various Q* named board config files. - - Signed-off-by: Jon Loeliger - -commit acf0269779422f3e147d2ddfb499c9f6ff10ad5e -Author: Jon Loeliger -Date: Sun Jul 8 14:49:44 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various P* named board config files. - - Signed-off-by: Jon Loeliger - -commit e18a1061a8630cb67995fdf99afd3fb50d1b187d -Author: Jon Loeliger -Date: Sun Jul 8 14:21:43 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various [NO]* named board config files. - - Signed-off-by: Jon Loeliger - -commit 8353e139bfad9059c54f5b2421f1a3090e15a2e2 -Author: Jon Loeliger -Date: Sun Jul 8 14:14:17 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various M* named board config files. - - Signed-off-by: Jon Loeliger - -commit 348f258f24253433e4a2302a0bbceb6740a67246 -Author: Jon Loeliger -Date: Sun Jul 8 13:46:18 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various [IJKL]* named board config files. - - Signed-off-by: Jon Loeliger - -commit 6c4f4da9bfc9f9403f54fce678ed0364b7c86a6a -Author: Jon Loeliger -Date: Sun Jul 8 10:09:35 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various H* named board config files. - - Signed-off-by: Jon Loeliger - -commit 60a0876b5106b34220e459c208bbf648073306c0 -Author: Jon Loeliger -Date: Sat Jul 7 21:04:26 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various F* and G* named board config files. - - Signed-off-by: Jon Loeliger - -commit dcaa71562826a2466e894c868d132509dcda8444 -Author: Jon Loeliger -Date: Sat Jul 7 20:56:05 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various E* named board config files. - - Signed-off-by: Jon Loeliger - -commit 3c3227f3c737502311b25b72084573901cbbf17d -Author: Jon Loeliger -Date: Sat Jul 7 20:40:43 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various D* named board config files. - - Signed-off-by: Jon Loeliger - -commit 49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c -Author: Jon Loeliger -Date: Thu Jul 5 19:52:35 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various C* named board config files. - - Signed-off-by: Jon Loeliger - -commit de8b2a6e33298dcdb10bdda48db25e53c3089eba -Author: Jon Loeliger -Date: Thu Jul 5 19:32:07 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various B* named board config files. - - Signed-off-by: Jon Loeliger - -commit 498ff9a228485bd4b9f23d066bada268f9add1dd -Author: Jon Loeliger -Date: Thu Jul 5 19:13:52 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various A* named board config files. - - Since ADS860.h includes "board/fads/fads.h" with ramifications - on the CONFIG_COMMAND treatment, it too has to be adjusted to - exclude already configured commands in this same commit. - - Signed-off-by: Jon Loeliger - -commit 10e038932f22ee80ebd53de312531e70e6590a2f -Author: Thomas Knobloch -Date: Fri Jul 6 14:58:39 2007 +0200 - - [NAND] Bad block skipping for command nboot - - The old implementation of command nboot does not support reading the image from - NAND flash with skipping of bad blocks. The patch implements a new version of - the nboot command: by calling nboot.jffs2 from the u-boot command line the - command will load the image from NAND flash with respect to bad blocks (by using - nand_read_opts()). This is similar to e.g. the NAND read command: "nand - read.jffs2 ...". - - Signed-off-by: Thomas Knobloch - Signed-off-by: Stefan Roese - -commit 334043f601a90ac53e5ecc846fbb73a1ef38cb1f -Author: Stefan Roese -Date: Fri Jul 6 12:26:51 2007 +0200 - - ppc4xx: Update lwmon5 default environment - - Signed-off-by: Stefan Roese - -commit 5d187430a055d62f17ca84d75e7245439d1f7e75 -Author: Stefan Roese -Date: Fri Jul 6 11:48:24 2007 +0200 - - ppc4xx: Update lwmon5 board - - Add unlock=yes environment variable to default variables to unlock - the CFI flash by default. - - Signed-off-by: Stefan Roese - -commit 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e -Author: Stefan Roese -Date: Fri Jul 6 09:45:47 2007 +0200 - - Fix problem with get/setdcr commands introduced by cfg patches - - Signed-off-by: Stefan Roese - -commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f -Author: Wolfgang Denk -Date: Fri Jul 6 02:50:19 2007 +0200 - - Code cleanup and default config update for STC GP3 SSA board. - - Signed-off-by: Wolfgang Denk - -commit e4dbe1b215f5c6c462e76909d240bd96472b84de -Author: Wolfgang Denk -Date: Thu Jul 5 17:56:27 2007 +0200 - - Fixing some typos etc. introduced mainly by cfg patches. - - Signed-off-by: Wolfgang Denk - -commit b6b4684546809f89c8bac72863ca49b5fd8ac0cd -Author: Wolfgang Denk -Date: Thu Jul 5 11:12:16 2007 +0200 - - Minor coding style cleanup. Update CHANGELOG. - -commit dca3b3d6d6396b67e5e84af53452164923c73443 -Author: Jon Loeliger -Date: Wed Jul 4 22:33:46 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various [v-z]* named board config files. - - Signed-off-by: Jon Loeliger - -commit 6c18eb9804b525f3e4f3bb3d014dd69a200d9fa7 -Author: Jon Loeliger -Date: Wed Jul 4 22:33:38 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various t* and u* named board config files. - - Signed-off-by: Jon Loeliger - -commit 46da1e96b7db14f4fcd2c92544e7c0862024bc76 -Author: Jon Loeliger -Date: Wed Jul 4 22:33:30 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various s* named board config files. - - Signed-off-by: Jon Loeliger - -commit 90cc3eb6d2be856d9ddd81436de9cf343bc6b5c8 -Author: Jon Loeliger -Date: Wed Jul 4 22:33:23 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various q* and r* named board config files. - - Signed-off-by: Jon Loeliger - -commit 26a34560d56a9df5bc2ae23525d9229736134757 -Author: Jon Loeliger -Date: Wed Jul 4 22:33:17 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various p* named board config files. - - Signed-off-by: Jon Loeliger - -commit a5cb23092a7d31490a33d4ec871468b63babfa3c -Author: Jon Loeliger -Date: Wed Jul 4 22:33:13 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various o* named board config files. - - Signed-off-by: Jon Loeliger - -commit 929a2bfd142737003a8fc32e1b86e1f2c1850257 -Author: Jon Loeliger -Date: Wed Jul 4 22:33:07 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various n* named board config files. - - Signed-off-by: Jon Loeliger - -commit 5dc11a511960d490f7f01ffd746edfe6277f99b0 -Author: Jon Loeliger -Date: Wed Jul 4 22:33:01 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various m* named board config files. - - Signed-off-by: Jon Loeliger - -commit 9bbb1c0820c1fbd3811ab6ee4ba0f6c6f76b27e4 -Author: Jon Loeliger -Date: Wed Jul 4 22:32:57 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various l* named board config files. - - Signed-off-by: Jon Loeliger - -commit bc234c129fa04fb9fa33530930e5cbc6084cd47a -Author: Jon Loeliger -Date: Wed Jul 4 22:32:51 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various j* and k* named board config files. - - Signed-off-by: Jon Loeliger - -commit 1d2c6bc491969f8d8fb34c8e30e8bea7a2af9c31 -Author: Jon Loeliger -Date: Wed Jul 4 22:32:32 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various i* named board config files. - - Signed-off-by: Jon Loeliger - -commit 48d5d102a2f2e619c92050b9aedbb69689185bc0 -Author: Jon Loeliger -Date: Wed Jul 4 22:32:25 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various h* named board config files. - - Signed-off-by: Jon Loeliger - -commit 72eb0efaed7048afcc61fc6f0085c49394b5dc36 -Author: Jon Loeliger -Date: Wed Jul 4 22:32:19 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various g* named board config files. - - Signed-off-by: Jon Loeliger - -commit 1bec3d3002d3bbbae6f2468a0f7376db1120d33e -Author: Jon Loeliger -Date: Wed Jul 4 22:32:10 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various e* named board config files. - - Signed-off-by: Jon Loeliger - -commit ab999ba1b31ebe78dd16374394a55d7c6e5aa6e4 -Author: Jon Loeliger -Date: Wed Jul 4 22:32:03 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various d* named board config files. - - Signed-off-by: Jon Loeliger - -commit 37e4f24b87fa255ae456d193b7cd23c18dd1d56b -Author: Jon Loeliger -Date: Wed Jul 4 22:31:56 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various c* named board config files. - - Signed-off-by: Jon Loeliger - -commit ba2351f9d1e841bd00ea6dad1e3c16d0259ad264 -Author: Jon Loeliger -Date: Wed Jul 4 22:31:49 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various b* named board config files. - - Signed-off-by: Jon Loeliger - -commit 0b361c916617aff79e647b40f0e43361e0bbaccf -Author: Jon Loeliger -Date: Wed Jul 4 22:31:42 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various a* named board config files. - - Signed-off-by: Jon Loeliger - -commit b730cda82e362df6a22f4c59c0a9b97e885b1014 -Author: Jon Loeliger -Date: Wed Jul 4 22:31:35 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in mpc5xx board config files. - - Signed-off-by: Jon Loeliger - -commit d794cfefead5fc177cf4f41164e80382e9c9484a -Author: Jon Loeliger -Date: Wed Jul 4 22:31:15 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in various 5200 board config files. - - Signed-off-by: Jon Loeliger - -commit ef0df52ab49eea4a30c15087fd27d54c1d946f2c -Author: Jon Loeliger -Date: Wed Jul 4 22:31:07 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in STx board config files. - - Signed-off-by: Jon Loeliger - -commit 866e3089bfc826bb4dc74637f8aad87a3bab79fc -Author: Jon Loeliger -Date: Wed Jul 4 22:30:58 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in sbc* board config files. - - Signed-off-by: Jon Loeliger - -commit 2694690e285acaa34922f55f4b5ae030da60c55a -Author: Jon Loeliger -Date: Wed Jul 4 22:30:50 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in TQM board config files. - - Signed-off-by: Jon Loeliger - -commit 1cc4c458329765b58e584a19821e796b3c10e976 -Author: Jon Loeliger -Date: Wed Jul 4 22:30:28 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in 82xx board config files. - - Signed-off-by: Jon Loeliger - -commit 8ea5499afdaba0acf60923dd99001c399d4a7c8e -Author: Jon Loeliger -Date: Wed Jul 4 22:30:06 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in 83xx board config files. - - Signed-off-by: Jon Loeliger - -commit b44896215a09c60fa40cae906f7ed207bbc2c492 -Author: Sergei Poselenov -Date: Thu Jul 5 08:17:37 2007 +0200 - - Merged POST framework with the current TOT. - - Signed-off-by: Sergei Poselenov - -commit b24629fa377214d63bb40d1360e354b6d3e4af56 -Author: Jon Loeliger -Date: Wed Jun 13 13:23:15 2007 -0500 - - mpc86xx: Remove old CFG_CMD_* references. - - Signed-off-by: Jon Loeliger - -commit 46175d9764da129bb4fd341cd2554dc7d55f5b2a -Author: Jon Loeliger -Date: Wed Jun 13 13:22:54 2007 -0500 - - Add MPC8568MDS to MAKEALL 85xx target. - - It was missing from the original port submission. - - Signed-off-by: Jon Loeliger - -commit 2835e518c969e5124ba1174eef3e8375e12fa7d5 -Author: Jon Loeliger -Date: Wed Jun 13 13:22:08 2007 -0500 - - include/configs: Use new CONFIG_CMD_* in 85xx board config files. - - Signed-off-by: Jon Loeliger - -commit 56b304ac2091689506088a9ae67f63fd6300cf16 -Author: Jon Loeliger -Date: Wed Jun 13 13:21:37 2007 -0500 - - Fix #if typo in CONFIG_CMD_* changes. - - Signed-off-by: Jon Loeliger - -commit f780b83316d9af1f61d71cc88b1917b387b9b995 -Author: Niklaus Giger -Date: Wed Jun 27 18:11:38 2007 +0200 - - resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX - - Signed-off-by: Niklaus Giger - -commit 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 -Author: Stefan Roese -Date: Wed Jul 4 10:06:30 2007 +0200 - - ppc4xx: Update lwmon5 board - - - Add optional ECC generation routine to preserve existing - RAM values. This is needed for the Linux log-buffer support - - Add optional DDR2 setup with CL=4 - - GPIO50 not used anymore - - Lime register setup added - - Signed-off-by: Stefan Roese - -commit 6810a34677dbc446334f5e451f1682426dd33b49 -Author: Grant Likely -Date: Tue Jul 3 00:17:28 2007 -0600 - - Fix Makefile to use $(MKCONFIG) macro for all board ports - - Signed-off-by: Grant Likely - -commit 90b1b2d69b9396ff2f01165ebc16c9a594eb5926 -Author: Grant Likely -Date: Tue Jul 3 00:17:28 2007 -0600 - - Fix Makefile to use $(MKCONFIG) macro for all board ports - - Signed-off-by: Grant Likely - -commit 057004f4a4863554d56cc56268bfa7c7d9738e27 -Author: Grant Likely -Date: Tue Jul 3 00:34:49 2007 -0600 - - Correct fixup relocation for mpc83xx - - Signed-off-by: Grant Likely - -commit 5af61b2f4b838a05f79be274f3e5a66edd2d9c96 -Author: Grant Likely -Date: Tue Jul 3 00:34:44 2007 -0600 - - Correct fixup relocation for mpc8260 - - Signed-off-by: Grant Likely - -commit f3a52fe05923935db86985daf9438e2f70ac39aa -Author: Grant Likely -Date: Tue Jul 3 00:34:39 2007 -0600 - - Correct fixup relocation for mpc824x - - Signed-off-by: Grant Likely - -commit a85dd254c0577fca13627c46e93fc2ad4c4f1f00 -Author: Grant Likely -Date: Tue Jul 3 00:34:34 2007 -0600 - - Correct fixup relocation for mpc8220 - - Signed-off-by: Grant Likely - -commit 6f7576b20ecf0d040c3ac3b032b5cbc860e38a90 -Author: Grant Likely -Date: Tue Jul 3 00:34:29 2007 -0600 - - Correct fixup relocation for MPC5xxx - - Signed-off-by: Grant Likely - -commit 3649cd99ba815b6601868735765602f00ef3692b -Author: Grant Likely -Date: Tue Jul 3 00:34:24 2007 -0600 - - Correct relocation fixup for mpc5xx - - Signed-off-by: Grant Likely - -commit f82b3b6304b620ef7e28bfaa1ea887a2ad2fa325 -Author: Grant Likely -Date: Tue Jul 3 00:34:19 2007 -0600 - - Don't set gd->reloc_off if relocation of .fixup works correctly - - Signed-off-by: Grant Likely - -commit e1a6144c32dc7de73bcdd33995de0148cbd0bd28 -Author: Grant Likely -Date: Tue Jul 3 00:34:14 2007 -0600 - - Remove obsolete mpc83xx linker scripts - - Signed-off-by: Grant Likely - -commit 17e32fc3908bf7089d3f16fc82a1c3ae674dd65b -Author: Grant Likely -Date: Tue Jul 3 00:34:09 2007 -0600 - - Consolidate mpc8260 linker scripts - - Signed-off-by: Grant Likely - -commit af7d38b393690d7eeaf418ac85a1e831a50d5fd0 -Author: Grant Likely -Date: Tue Jul 3 00:34:04 2007 -0600 - - Remove obsolete mpc824x linker scripts - - Signed-off-by: Grant Likely - -commit f94a3aecebc40ca0939c7d66d010009cf51be9e2 -Author: Grant Likely -Date: Tue Jul 3 00:33:59 2007 -0600 - - Remove obsolete mpc824x linker scripts (3 of 4) - - Signed-off-by: Grant Likely - -commit a71c084f3ac7fedf144537db2b2da47323068833 -Author: Grant Likely -Date: Tue Jul 3 00:33:53 2007 -0600 - - Remove obsolete mpc824x linker scripts (2 of 4) - - Signed-off-by: Grant Likely - -commit f670a15468d1365241d40022b9408e1004181f5e -Author: Grant Likely -Date: Tue Jul 3 00:33:48 2007 -0600 - - Remove obsolete mpc824x linker scripts (1 of 4) - - Signed-off-by: Grant Likely - -commit 09555bd45a04c0e54f172528d21bc18896550d28 -Author: Grant Likely -Date: Tue Jul 3 00:33:43 2007 -0600 - - Remove obsolete mpc8220 linker scripts - - Signed-off-by: Grant Likely - -commit 5efb992f046e51225c93d52f80fecbe433abd789 -Author: Grant Likely -Date: Tue Jul 3 00:33:38 2007 -0600 - - Remove obsolete mpc5xxx linker scripts (3 of 3) - - Signed-off-by: Grant Likely - -commit 07c13dfef65b31647e69d8b61daa1eec598add1a -Author: Grant Likely -Date: Tue Jul 3 00:33:33 2007 -0600 - - Remove obsolete mpc5xxx linker scripts (2 of 3) - - Signed-off-by: Grant Likely - -commit b4f67513a624ce85866c66c575bd2d9d7977d7f0 -Author: Grant Likely -Date: Tue Jul 3 00:33:28 2007 -0600 - - Remove obsolete mpc5xxx linker scripts (1 of 3) - - Signed-off-by: Grant Likely - -commit b7d8e05f8675249b5f208aa73babeed384a4519d -Author: Grant Likely -Date: Tue Jul 3 00:33:23 2007 -0600 - - Remove obsolete mpc5xx linker scripts - - Signed-off-by: Grant Likely - -commit 416a0b6d40f6eba3a2fc547253c16bda28d922f7 -Author: Grant Likely -Date: Tue Jul 3 00:33:18 2007 -0600 - - Consolidate mpc83xx linker scripts - - Signed-off-by: Grant Likely - -commit 5fc59175b92883ed5d2666a04e6bc49e70a4a365 -Author: Grant Likely -Date: Tue Jul 3 00:33:13 2007 -0600 - - Consolidate mpc8260 linker scripts - - Signed-off-by: Grant Likely - -commit 737f9eb02d7335df2b3e4d7a4d3348784d1da207 -Author: Grant Likely -Date: Tue Jul 3 00:33:08 2007 -0600 - - Consolidate mpc824x linker scripts - - Signed-off-by: Grant Likely - -commit 9c757b789a59a855db57b448dd825329c4e9c4a0 -Author: Grant Likely -Date: Tue Jul 3 00:33:03 2007 -0600 - - Consolidate mpc8220 linker scripts - - Signed-off-by: Grant Likely - -commit d181c9a15cd41863fe24840d17848429f27d3c8c -Author: Grant Likely -Date: Tue Jul 3 00:32:58 2007 -0600 - - Consolidate mpc5xxx linker scripts - - Signed-off-by: Grant Likely - -commit 287ac924adb7291bebe5086652a362a30ab28b13 -Author: Grant Likely -Date: Tue Jul 3 00:32:53 2007 -0600 - - Consolidate mpc5xx linker scripts - - Signed-off-by: Grant Likely - -commit 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd -Author: Wolfgang Denk -Date: Wed Jul 4 00:43:53 2007 +0200 - - Fix a few file permission problems. - - Signed-off-by: Wolfgang Denk - -commit 78e0cf2de7be7f1eaeeb622eb61fd50e4d5e205c -Author: Wolfgang Denk -Date: Wed Jul 4 00:38:38 2007 +0200 - - Minor coding style cleanup. Rebuild CHANGELOG file. - -commit 2f9c19e496acb6bb50d9299e1aab377625d48c38 -Author: Jon Loeliger -Date: Mon Jun 11 19:03:44 2007 -0500 - - configs/ mpc86xx: Rewrite command line options using new CONFIG_CMD-* style. - - Signed-off-by: Jon Loeliger - -commit 602ad3b33d9ceef83dbab46be68646d645d637ee -Author: Jon Loeliger -Date: Mon Jun 11 19:03:39 2007 -0500 - - README: Rewrite command line config to use CONFIG_CMD_* names. - - Signed-off-by: Jon Loeliger - -commit 72a074cec68e5bad60d63206c050974e08afd804 -Author: Jon Loeliger -Date: Mon Jun 11 19:03:34 2007 -0500 - - include/ non-config: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 5fcf543e0b6628c76ff48705b1b0566bfd11507b -Author: Jon Loeliger -Date: Mon Jun 11 19:03:28 2007 -0500 - - tools/ : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 9107ebe0d352420895ab69b715697bdebc8caf50 -Author: Jon Loeliger -Date: Mon Jun 11 19:03:23 2007 -0500 - - board/[k-z]*: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 5e378003d592ea828ec69d6defcd4de79096dd5c -Author: Jon Loeliger -Date: Mon Jun 11 19:03:19 2007 -0500 - - board/[Ma-i]*: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 737184114ec9c9e0ab94d6713536126073bd2472 -Author: Jon Loeliger -Date: Mon Jun 11 19:03:15 2007 -0500 - - cpu/ non-mpc*: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit f48070fe5fe440dfb5ee5268c920de70e48ea327 -Author: Jon Loeliger -Date: Mon Jun 11 19:03:08 2007 -0500 - - cpu/mpc*/ : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 0c505db0a0dc1f670b13ce3b4d3fbf1ec5b3cbd2 -Author: Jon Loeliger -Date: Mon Jun 11 19:03:03 2007 -0500 - - lib_*/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 73f032021ec5f13cda8faa4e34b6de80960eb86f -Author: Jon Loeliger -Date: Mon Jun 11 19:02:58 2007 -0500 - - lib_ppc/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 98b79003c21c2578206003256de4e781d6b36ca8 -Author: Jon Loeliger -Date: Mon Jun 11 19:02:53 2007 -0500 - - rtc/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 6e2115acb6a892d53a6881bf253ae41d3df39156 -Author: Jon Loeliger -Date: Mon Jun 11 19:02:49 2007 -0500 - - net/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 45cdb9b72c94655c7308b464a2666057c0b286e0 -Author: Jon Loeliger -Date: Mon Jun 11 19:02:34 2007 -0500 - - disk/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 4e109ae98294a5ca7ff848b7652c7bfd4023a94a -Author: Jon Loeliger -Date: Mon Jun 11 19:02:20 2007 -0500 - - fs/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit d5be43de93ff905c465e509d45a3164ef48d26e7 -Author: Jon Loeliger -Date: Mon Jun 11 19:02:10 2007 -0500 - - drivers/: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit b453960d4fdb87b3970d96119b90df2ed024fc4a -Author: Jon Loeliger -Date: Mon Jun 11 19:02:05 2007 -0500 - - common/ non-cmd: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit 65c450b47a62659d522cfa8f4fa1e4e5c60dccd0 -Author: Jon Loeliger -Date: Mon Jun 11 19:01:54 2007 -0500 - - common/cmd_[i-z]* : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit a76adc8142c1d956385a109e0b70f9319ede4d66 -Author: Jon Loeliger -Date: Mon Jun 11 19:01:43 2007 -0500 - - common/cmd_[a-f]* : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). - - This is a compatibility step that allows both the older form - and the new form to co-exist for a while until the older can - be removed entirely. - - All transformations are of the form: - Before: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) - After: - #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) - - Signed-off-by: Jon Loeliger - -commit ec63b10b61fd68238d4c15c1cd04c0b38228e2c1 -Author: Jon Loeliger -Date: Mon Jun 11 19:01:34 2007 -0500 - - Introduce initial versions of new Command Config files. - - Derive three new files from cmd_confdefs.h: - config_bootp.h - Has BOOTP related config options, not commands - config_cmd_all.h - Has a CONFIG_CMD_* definition for every command - config_cmd_default.h - Has a CONFIG_CMD_* definition for default cmds. - - For now, include "config_bootp.h" for compatability until all - users of it directly include it properly. - - Signed-off-by: Jon Loeliger - -commit 1f2a05898658900dc5717761e27abf2052e67e13 -Author: Mushtaq Khan -Date: Sat Jun 30 18:50:48 2007 +0200 - - Fix S-ATA support. - - Signed-off-by: mushtaq khan - -commit a5d71e290f3673269be8eefb4ec44f53412f9461 -Author: Heiko Schocher -Date: Mon Jun 25 19:11:37 2007 +0200 - - [PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG - - Signed-off-by: Heiko Schocher - -commit a1bd6200eccd3a02040a955d5f43d3ee1fc9f93b -Author: Niklaus Giger -Date: Mon Jun 25 17:03:13 2007 +0200 - - ppc4xx: PPC440EPx Emit DDR0 registers on machine check interrupt - - This patch prints the DDR status registers upon machine check - interrupt on the 440EPx/GRx. This can be useful especially when - ECC support is enabled. - - I added some small changes to the original patch from Niklaus to - make it compile clean. - - Signed-off-by: Niklaus Giger - Signed-off-by: Stefan Roese - -commit 807018fb7faceb429ce0cb47baa2073746b33a4e -Author: Niklaus Giger -Date: Mon Jun 25 16:50:55 2007 +0200 - - ppc4xx: Fix O=buildir builds - - This patch fixes the problem to assemble cpu/ppc4xx/start.S - experienced last week where building failed having specified - O=../build.sequoia. - - Signed-off-by: Niklaus Giger - -commit 466fff1a7bb5fe764a06450626f6098219f446b8 -Author: Stefan Roese -Date: Mon Jun 25 15:57:39 2007 +0200 - - ppc4xx: Add pci_pre_init() for 405 boards - - This patch removes the CFG_PCI_PRE_INIT option completely, since - it's not needed anymore with the patch from Matthias Fuchs with - the "weak" pci_pre_init() implementation. - - Signed-off-by: Stefan Roese - -commit 6f35c53166213c24a5a0e2390ed861136ff73870 -Author: Matthias Fuchs -Date: Sun Jun 24 17:41:21 2007 +0200 - - ppc4xx: Maintenance patch for esd's CPCI405 derivats - - -add pci_pre_init() for pci interrupt fixup code - -disable phy sleep mode via reset_phy() function - -use correct io accessors - -cleanup - - Signed-off-by: Matthias Fuchs - -commit 5a1c9ff0c44305b57cb4d8f9369bba90bcf0e1f8 -Author: Matthias Fuchs -Date: Sun Jun 24 17:23:41 2007 +0200 - - ppc4xx: Add pci_pre_init() for 405 boards - - This patch adds support for calling a plattform dependant - pci_pre_init() function for 405 boards. This can be used to - move the current pci_405gp_fixup_irq() function into the - board code. - - This patch also makes the CFG_PCI_PRE_INIT define obsolete. - A default function with 'weak' attribute is used when - a board specific pci_pre_init() is not implemented. - - Signed-off-by: Matthias Fuchs - -commit 1636d1c8529c006d106287cfbc20cd0a246fe1cb -Author: Wolfgang Denk -Date: Fri Jun 22 23:59:00 2007 +0200 - - Coding stylke cleanup; rebuild CHANGELOG - -commit 2dc64451b4c08ffd619372abfdc2506a2e2363b9 -Author: Igor Lisitsin -Date: Wed Apr 18 14:55:19 2007 +0400 - - Adapt log buffer code to support Linux 2.6 - - A new environment variable, "logversion", selects the log buffer - behaviour. If it is not set or set to a value other than 2, then the - old, Linux 2.4.4, behaviour is selected. - - Signed-off-by: Igor Lisitsin - -- - -commit a11e06965ec91270c51853407ff1261d3c740386 -Author: Igor Lisitsin -Date: Wed Mar 28 19:06:19 2007 +0400 - - Extend POST support for PPC440 - - Added memory, CPU, UART, I2C and SPR POST tests for PPC440. - - Signed-off-by: Igor Lisitsin - -- - -commit 566a494f592ae3b3c0785d90d4e1ba45574880c4 -Author: Heiko Schocher -Date: Fri Jun 22 19:11:54 2007 +0200 - - [PCS440EP] upgrade the PCS440EP board: - - Show on the Status LEDs, some States of the board. - - Get the MAC addresses from the EEProm - - use PREBOOT - - use the CF on the board. - - check the U-Boot image in the Flash with a SHA1 - checksum. - - use dynamic TLB entries generation for the SDRAM - - Signed-off-by: Heiko Schocher - -commit 3a1f5c81b0b9557817a789bece839905581c2205 -Author: Stefan Roese -Date: Fri Jun 22 16:58:40 2007 +0200 - - ppc4xx: Fix problem with extended program_tlb() funtion - - The recently extended program_tlb() function had a problem when - multiple TLB's had to be setup (for example with 512MB of SDRAM). The - virtual address was not incremented. This patch fixes this issue - and is tested on Katmai with 512MB SDRAM. - - Signed-off-by: Stefan Roese - -commit 02032e8f14751a1a751b09240a4f1cf9f8a2077f -Author: Rafal Jaworowski -Date: Fri Jun 22 14:58:04 2007 +0200 - - [ppc] Fix build breakage for all non-4xx PowerPC variants. - - - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - - minor 4xx cleanup - -commit d677b32855f577ae2690dcd64a172cdd706e0ffc -Author: Mike Frysinger -Date: Fri Jun 22 10:34:12 2007 +0200 - - [patch] add nand_init() prototype to nand.h - - since nand_init() is expected to be called by other parts of u-boot, there - should be a prototype for it in nand.h - - Signed-off-by: Mike Frysinger - Signed-off-by: Stefan Roese - -commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b -Author: Wolfgang Denk -Date: Wed Jun 20 18:14:24 2007 +0200 - - Coding style cleanup. Refresh CHANGELOG. - -commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024 -Author: Stefan Roese -Date: Tue Jun 19 17:22:44 2007 +0200 - - ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval board - - This patch adds a board command to configure the I2C bootstrap EEPROM - values. Right now 533 and 667MHz are supported for booting either via NOR - or NAND FLASH. Here the usage: - - => bootstrap 533 nor ;to configure the board for 533MHz NOR booting - => bootstrap 667 nand ;to configure the board for 667MHz NNAND booting - - Signed-off-by: Stefan Roese - -commit df8a24cdd30151505cf57bbee5289e91bf53bd1b -Author: Stefan Roese -Date: Tue Jun 19 16:42:31 2007 +0200 - - [ppc4xx] Fix problem with NAND booting on AMCC Acadia - - The latest changes showed a problem with the location of the NAND-SPL - image in the OCM and the init-data area (incl. cache). This patch - fixes this problem. - - Signed-off-by: Stefan Roese - -commit 86ba99e34194394052d24c04dc40d1263d29a26f -Author: Stefan Roese -Date: Tue Jun 19 16:40:58 2007 +0200 - - [ppc4xx] Change board/amcc/acadia/cpr.c to pll.c - - Signed-off-by: Stefan Roese - -commit 8e585f02f82c17cc66cd229dbf0fd3066bbbf658 -Author: TsiChung Liew -Date: Mon Jun 18 13:50:13 2007 -0500 - - Added M5329AFEE and M5329BFEE Platforms - - Added board/freescale/m5329evb, cpu/mcf532x, drivers/net, - drivers/serial, immap_5329.h, m5329.h, mcfrtc.h, - include/configs/M5329EVB.h, lib_m68k/interrupts.c, and - rtc/mcfrtc.c - - Modified CREDITS, MAKEFILE, Makefile, README, common/cmd_bdinfo.c, - common/cmd_mii.c, include/asm-m68k/byteorder.h, include/asm-m68k/fec.h, - include/asm-m68k/io.h, include/asm-m68k/mcftimer.h, - include/asm-m68k/mcfuart.h, include/asm-m68k/ptrace.h, - include/asm-m68k/u-boot.h, lib_m68k/Makefile, lib_m68k/board.c, - lib_m68k/time.c, net/eth.c and rtc/Makefile - - Signed-off-by: TsiChung Liew - -commit 093172f08d6afb3f34d8a2f26ee0ee874261cf27 -Author: Michal Simek -Date: Sun Jun 17 19:04:11 2007 +0200 - - [fix] email reparation - -commit 3666afffe7baf859c6ae0ce2bebbc8ab7e512ddc -Author: Michal Simek -Date: Sun Jun 17 19:03:21 2007 +0200 - - [FIX] fix microblaze file permitission - -commit e73846b7cf1e29ae635bf9bb5570269663df2ee5 -Author: Stefan Roese -Date: Fri Jun 15 11:33:41 2007 +0200 - - [ppc4xx] Change lwmon5 port to work with recent 440 exception rework - - Now CONFIG_440 has to be defined in all PPC440 board config files. - - Signed-off-by: Stefan Roese - -commit efa35cf12d914d4caba942acd5a6c45f217de302 -Author: Grzegorz Bernacki -Date: Fri Jun 15 11:19:28 2007 +0200 - - ppc4xx: Clean up 440 exceptions handling - - - Introduced dedicated switches for building 440 and 405 images required - for 440-specific machine instructions like 'rfmci' etc. - - - Exception vectors moved to the proper location (_start moved away from - the critical exception handler space, which it occupied) - - - CriticalInput now serviced (with default handler) - - - MachineCheck properly serviced (added a dedicated handler and return - subroutine) - - - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, - unhandled and those not relevant for 4xx were eliminated) - - - Eliminated Linux leftovers, removed dead code - - Signed-off-by: Grzegorz Bernacki - Signed-off-by: Rafal Jaworowski - Signed-off-by: Stefan Roese - -commit b765ffb773f5a3cd5aa94ec76b6a05276b8cd5b2 -Author: Stefan Roese -Date: Fri Jun 15 08:18:01 2007 +0200 - - [ppc4xx] Add initial lwmon5 board support - - This patch adds initial support for the Liebherr lwmon5 board euqipped - with an AMCC 440EPx PowerPC. - - Signed-off-by: Stefan Roese - -commit 85f737376d5ff3d5f0d45a8b657686326d175307 -Author: Stefan Roese -Date: Fri Jun 15 07:39:43 2007 +0200 - - [ppc4xx] Extend 44x GPIO setup with default output state - - The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup - is extended with the default GPIO output state (level). - - Signed-off-by: Stefan Roese - -commit dbca208518e5e7f01a6420588d1cd6e60db74c2b -Author: Stefan Roese -Date: Thu Jun 14 11:14:32 2007 +0200 - - [ppc4xx] Extend program_tlb() with virtual & physical addresses - - Now program_tlb() allows to program a TLB (or multiple) with - different virtual and physical addresses. With this change, now one - physical region (e.g. SDRAM) can be mapped 2 times, once with caches - diabled and once with caches enabled. - - Signed-off-by: Stefan Roese - -commit 9912121f7ed804ea58fd62f3f230b5dcfc357d88 -Author: Detlev Zundel -Date: Wed May 23 19:02:41 2007 +0200 - - Change 'repeatable' attribute of some commands to sensible values. - - Most prominently this changes 'erase' to be non-repeatable. - - Signed-off-by: Detlev Zundel - -commit 5afb202093f6a001797db92cf695b93a70ea9ab4 -Author: Detlev Zundel -Date: Wed May 23 18:47:48 2007 +0200 - - Fix 'run' not to continue after interrupted command - - Signed-off-by: Detlev Zundel - -commit 9b7464a2c88614e1061f509c48930a3d240d1a35 -Author: Jason Jin -Date: Mon Jun 11 15:14:24 2007 +0200 - - USB: This patch fix readl in ohci swap reg access. - - Signed-off-by: Jason Jin - -commit 8f8416fada9faf94b9a92f21fe6000643cb521d5 -Author: Bartlomiej Sieka -Date: Fri Jun 8 14:52:22 2007 +0200 - - TQM5200: Add Flat Device Tree support, update default env. accordingly. - - Signed-off-by: Jan Wrobel - Acked-by: Bartlomiej Sieka - -commit 9045f33c023f698660a2e45d1b2194c0711abebc -Author: Wolfgang Denk -Date: Fri Jun 8 10:24:58 2007 +0200 - - Fix config problems on SC3 board; make ide_reset_timeout work. - -commit fba3fb0449b8a54542aed1e729de76e7f5a2ff1b -Author: Benoît Monin -Date: Fri Jun 8 09:55:24 2007 +0200 - - [PATCH] fix gpio setting when using CFG_440_GPIO_TABLE - - Set the correct value in GPIOx_TCR when configuring the gpio - with CFG_440_GPIO_TABLE. - - Signed-off-by: Benoit Monin - Signed-off-by: Stefan Roese - -commit f539edc076cfe52bff919dd512ba8d7af0e22092 -Author: Vadim Bendebury -Date: Thu May 24 15:52:25 2007 -0700 - - cosmetic changes to bcm570x driver - - This is a cosmetic only changes submission. - It affects files relevant to bcm570x driver. - the commands used to generate this change was - - cd drivers - Lindent -pcs -l80 bcm570x.c bcm570x_lm.h bcm570x_mm.h tigon3.c tigon3.h - - The BMW target (the only one using this chip so far) builds cleanly, the - `before and after' generated object files for drivers/bcm570x.c and - drivers/tigon3.o are identical as reported by objdump -d - - Signed-off-by: Vadim Bendebury - Signed-off-by: Ben Warren - -commit 725671ccd2cd04c9ebc50c9e5a94dd8cbade66b7 -Author: Wolfgang Denk -Date: Wed Jun 6 16:26:56 2007 +0200 - - Coding Style cleanup; generate new CHANGELOG file. - - Signed-off-by: Wolfgang Denk - -commit 19d763c35e0b5568eaf0b8adbf7a68ccfe7fa243 -Author: Markus Klotzbuecher -Date: Wed Jun 6 11:49:44 2007 +0200 - - TRAB, USB: update trab board configuration for use of generic ohci driver - -commit dace45acd1c1357daa9322099d07c9a9e08b0024 -Author: Markus Klotzbuecher -Date: Wed Jun 6 11:49:43 2007 +0200 - - USB: ohci fixes and cleanup for ppc4xx and yosemite board. - -commit 72657570b61635c74fa0c3f0e9e7d0671a9d08df -Author: Markus Klotzbuecher -Date: Wed Jun 6 11:49:43 2007 +0200 - - USB: ohci fixes and cleanup for mpc5xxx and IceCube board config - -commit fc43be478f2aa37ce38acd85355038866e4162af -Author: Markus Klotzbuecher -Date: Wed Jun 6 11:49:35 2007 +0200 - - USB/OHCI: endianness cleanup in the generic ohci driver - -commit c440bfe6d6d92d66478a7e84402b31f48413617b -Author: Stefan Roese -Date: Wed Jun 6 11:42:13 2007 +0200 - - ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board - - This patch adds NAND booting support for the AMCC Acadia eval board. - - Please make sure to configure jumper J7 to position 2-3 when booting - from NOR, and to position 1-2 when booting for NAND. - - I also added a board command to configure the I2C bootstrap EEPROM - values. Right now only 267MHz is support for booting either via NOR - or NAND FLASH. Here the usage: - - => bootstrap 267 nor ;to configure the board for 267MHz NOR booting - => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting - - Signed-off-by: Stefan Roese - -commit 18135125f909948b85d1d6881ab4ac0efb4a1c58 -Author: Rodolfo Giometti -Date: Wed Jun 6 10:08:14 2007 +0200 - - Files include/linux/byteorder/{big,little}_endian.h define - __BIG_ENDIAN and __LITTLE_ENDIAN. - - Signed-off-by: Rodolfo Giometti - -commit a81d1c0b85b13e9d45f2d87de96a51a6e0ef0f82 -Author: Zhang Wei -Date: Wed Jun 6 10:08:14 2007 +0200 - - Add USB PCI-OHCI, USB keyboard and event poll support to the - MPC8641HPCN board config file. - - Signed-off-by: Zhang Wei - -commit 4dae14ce8fbdf380017dc54f172218e7d2acc889 -Author: Zhang Wei -Date: Wed Jun 6 10:08:14 2007 +0200 - - USB PCI-OHCI, interrupt pipe and usb event poll support - - This patch added USB PCI-OHCI chips support, interrupt pipe support - and usb event poll support. For supporting the USB interrupt pipe, the - globe urb_priv is moved to purb in ed struct. Now, we can process - several urbs at one time. The interrupt pipe support codes are ported - from Linux kernel 2.4. - - Signed-off-by: Zhang Wei - -commit fdcfaa1b02268b2899e374b35adf936c911a47eb -Author: Zhang Wei -Date: Wed Jun 6 10:08:13 2007 +0200 - - USB event poll support - - This patch adds USB event poll support, which could be used in usbkbd - and other usb devices driver when the asynchronous interrupt - processing is supported. - - Signed-off-by: Zhang Wei -Date: Wed Jun 6 10:08:12 2007 +0200 - - ISP116x: delay for crappy USB keys - - Using some (very) slow USB keys cause the USB host controller buffers - are not ready to be read by the CPU so we need an extra delay before - reading the USB storage data. - - Signed-off-by: Rodolfo Giometti - -commit 09444143670c9c2243cb7aba9f70b3713d33bed1 -Author: Markus Klotzbuecher -Date: Wed Jun 6 10:08:12 2007 +0200 - - Change duplicate usb_cpu_init_fail to usb_board_init_fail - - Thanks to Liew Tsi Chung for pointing - this out. - - Signed-off-by: Markus Klotzbuecher - -commit 32922cdc470fdfd39bea0c1c4f582d3fb340421e -Author: Ed Swarthout -Date: Tue Jun 5 12:30:52 2007 -0500 - - mpc8641 image size cleanup - - e600 does not have a bootpg restriction. - Move the version string to beginning of image at fff00000. - Resetvec.S is not needed. - Update flash copy instructions. - Add tftpflash env variable - - Signed-off-by: Ed Swarthout - Signed-off-by: Jon Loeliger - -commit e3cbe1f93c5722f8ebbad468e30c069a2b511097 -Author: Benoît Monin -Date: Mon Jun 4 08:36:05 2007 +0200 - - [PATCH] Fix ppc4xx bootstrap letter displayed on startup - - The attached patch is mainly cosmetic, allowing u-boot to - display the correct bootstrap option letter according to the - datasheets. - - The original patch was extended with 405EZ support by Stefan - Roese. - - Signed-off-by: Benoit Monin - Signed-off-by: Stefan Roese - -commit 5b1313fb2758ffce8b624457f777d8cc6709608d -Author: Nikita V. Youshchenko -Date: Wed May 23 12:45:19 2007 +0400 - - fix compilation problem for mpc8349itx CFG_RAMBOOT - - Current include/configs/MPC8349ITX.h does contain some support for building - image that will be started from memory (without putting in into flash). - It could be triggered by building with TEXT_BASE set to a low value. - - However, this support is incomplete: using of low TEXT_BASE causes - defining configuration macros in inconsistent way, which later leads - to compilation errors. In particular. flash support is being disabled, - but then flash structures get referenced. - - This patch fixes this, making it possible to build with low TEXT_BASE. - - Signed-Off-By: Nikita Youshchenko - - Signed-off-by: Kim Phillips - -commit 8a364f0970de49949d635e60accf463c6443ef8c -Author: Nikita V. Youshchenko -Date: Wed May 23 12:45:25 2007 +0400 - - add missing 'console' var to default mpc8349itx config - - Signed-off-by: Kim Phillips - -commit 18d156eb37c90fadc8ec7a81a3b89176161f85b7 -Author: Stefan Roese -Date: Fri Jun 1 16:18:17 2007 +0200 - - ppc4xx: Add missing file for Bamboo NAND booting support - - Signed-off-by: Stefan Roese - -commit 155a96478a0881e6da96cbbbcf34952d6a3b1b4b -Author: Stefan Roese -Date: Fri Jun 1 15:58:19 2007 +0200 - - ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHz - - This patch undoes the patch by Jeff Mann with commit-id ada4697d. As - suggested by AMCC it is not recommended to dynamically change the EBC - speed after bootup. So we undo this change to be on the safe side. - - Signed-off-by: Stefan Roese - -commit 9d9096043e8f713d4bf1743d32e1459e6a11644b -Author: Stefan Roese -Date: Fri Jun 1 15:29:04 2007 +0200 - - ppc4xx: Update Sequoia NAND booting support with ECC - - Signed-off-by: Stefan Roese - -commit cf959c7d6687567c308e366e9581e1a5aff5cc5b -Author: Stefan Roese -Date: Fri Jun 1 15:27:11 2007 +0200 - - ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board - - This patch adds NAND booting support for the AMCC Bamboo eval board. - Since the NAND-SPL boot image is limited to 4kbytes, this version - only supports the onboard 64MBytes of DDR. The DIMM modules can't be - supported, since the setup code for I2C DIMM autodetection and - configuration is too big for this NAND bootloader. - - Signed-off-by: Stefan Roese - -commit 42be56f53c8b107868e6125c8524ae84293e95a7 -Author: Stefan Roese -Date: Fri Jun 1 15:23:04 2007 +0200 - - NAND: Add ECC support to NAND booting support in nand_spl/nand_boot.c - - The U-Boot NAND booting support is now extended to support ECC - upon loading of the NAND U-Boot image. - - Tested on AMCC Sequoia (440EPx) and Bamboo (440EP). - - Signed-off-by: Stefan Roese - -commit a471db07fbb65a841ffc9f4f112562b945230f98 -Author: Stefan Roese -Date: Fri Jun 1 15:19:29 2007 +0200 - - ppc4xx: Prepare Bamboo port for NAND booting support - - This patch updates the "normal" Bamboo NOR booting port, so - that it is compatible with the coming soon NAND booting - Bamboo port. - - It also enables the 2nd NAND flash on the Bamboo. - - Signed-off-by: Stefan Roese - -commit 53ad02103fb8be4138a9937a8ab91fcdff7b4987 -Author: Stefan Roese -Date: Fri Jun 1 15:16:58 2007 +0200 - - ppc4xx: Update in_be32() functions and friends to latest Linux version - - Signed-off-by: Stefan Roese - -commit 91da09cfbce0c1de05d6d84aa8363d666fa7ea3c -Author: Stefan Roese -Date: Fri Jun 1 15:15:12 2007 +0200 - - NAND: Add hardware ECC support to the PPC4xx NAND driver ndfc.c - - This patch adds hardware ECC support to the NDFC driver. It also - changes the register access from using the "simple" in32/out32 - functions to the in_be32/out_be32 functions, which make sure - that the access is correctly synced. This is the only recommended - access to SoC registers in the current Linux kernel. - - Signed-off-by: Stefan Roese - -commit 17b5e862287cca76f19dcf8b741e61a7d06617f2 -Author: Stefan Roese -Date: Fri Jun 1 15:12:15 2007 +0200 - - NAND: Update nand_ecc.c to latest Linux version - - This patch updates the nand_ecc code to the latest Linux version. - The main reason for this is the more compact code. This makes - it possible to include the ECC code into the NAND bootloader - image (NAND_SPL) for PPC4xx. - - Signed-off-by: Stefan Roese - -commit d2d432760d2199d0e8558fdd9d1789b8131abcf7 -Author: Stefan Roese -Date: Fri Jun 1 15:09:50 2007 +0200 - - ppc4xx: 44x DDR driver code cleanup and small fix for Bamboo - - Signed-off-by: Stefan Roese - -commit e4bbed2803a2ad0521c7362f5d3e065f99abaedc -Author: Stefan Roese -Date: Fri Jun 1 13:45:24 2007 +0200 - - ppc4xx: Change Luan config file to support ECC - - With the updated 44x DDR2 driver the Luan board now supports - ECC generation and checking. - - Signed-off-by: Stefan Roese - -commit 7187db73491c8de0fb56efb5e5134ba5ec443089 -Author: Stefan Roese -Date: Fri Jun 1 13:45:00 2007 +0200 - - ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe) - - Add config option for 180 degree advance clock control as needed - for the AMCC Luan eval board. - - Signed-off-by: Stefan Roese - -commit ee1529838abbfaa35f14e3ffbeaaba693159475f -Author: Wolfgang Denk -Date: Thu May 31 17:20:09 2007 +0200 - - Add support for STX GP3SSA (stxssa) Board with 4 MiB flash. - - Signed-off-by: Wolfgang Denk - -commit 7049288fb1f16f1b317140226cdebd07bd416395 -Author: Bartlomiej Sieka -Date: Sun May 27 17:26:46 2007 +0200 - - Motion-PRO: Code cleanup, fix of a typo in OF_STDOUT_PATH. - - Signed-off-by: Bartlomiej Sieka - -commit 4520fd4d2c450da49637216aa0e53739b61c60ac -Author: Bartlomiej Sieka -Date: Sun May 27 17:06:36 2007 +0200 - - Motion-PRO: Add support for redundant environment. - - Enable redundant environment, add a MTD partition for it; also add env. - variable command for passing MTD partitions to the kernel command line. - - Signed-off-by: Piotr Kruszynski - Acked-by: Bartlomiej Sieka - -commit a26eabeec31746f06d309103690892805696e344 -Author: Bartlomiej Sieka -Date: Sun May 27 17:05:11 2007 +0200 - - Motion-PRO: Change maximum console buffer size from 256 to 1024 bytes. - - Allow passing longer command line to the kernel - useful especially - for passing MTD partition layout. - - Signed-off-by: Piotr Kruszynski - Acked-by: Bartlomiej Sieka - -commit 9160b96f71483a116de81c68985e8ee306d36764 -Author: Bartlomiej Sieka -Date: Sun May 27 17:04:18 2007 +0200 - - Fix: Add missing NULL termination in strings expanded by macros parser. - - Signed-off-by: Piotr Kruszynski - Acked-by: Bartlomiej Sieka - -commit 630ec84aef7228fc1dbfb38dec78541403a786cd -Author: Bartlomiej Sieka -Date: Sun May 27 17:03:37 2007 +0200 - - Motion-PRO: Update EEPROM's page write bits and write delay. - - Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A - have a page write capability of two bytes", and "This device offers fast (1ms) - byte write". Add 3ms of extra delay. - - Signed-off-by: Piotr Kruszynski - Acked-by: Bartlomiej Sieka - -commit c00125e07c1ebc125bab40e1e18bceed8be0c162 -Author: Bartlomiej Sieka -Date: Sun May 27 16:58:45 2007 +0200 - - MPC5XXX, Motion-PRO: Fix PHY initialization problem. - - After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which - networking does not function. This commit switches PHY to TX mode by clearing - the FX_SEL bit of Mode Control Register. It also reverses commit - 008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround. - - Signed-off-by: Grzegorz Bernacki - Acked-by: Bartlomiej Sieka - -commit 93b78f534a6e708b4cf1a4ffb4d8438c67a007db -Author: Bartlomiej Sieka -Date: Sun May 27 16:57:15 2007 +0200 - - Motion-PRO: Add support for the temperature sensor. - - Signed-off-by: Piotr Kruszynski - Acked-by: Bartlomiej Sieka - -commit c75e639630cc132dc19cd1ecda5922c0db0bfbba -Author: Bartlomiej Sieka -Date: Sun May 27 16:55:23 2007 +0200 - - Motion-PRO: Add displaying of CPLD revision information during boot. - - Signed-off-by: Jan Wrobel - Acked-by: Bartlomiej Sieka - -commit c99512d6bd3973f01ca2fc4896d829b46e68f150 -Author: Bartlomiej Sieka -Date: Sun May 27 16:53:43 2007 +0200 - - MPC5xxx: Change names of defines related to IPB and PCI clocks. - - Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining - them does not cause PCI or IPB clocks to run at the specified speed. - Instead, they configure divisors used to calculate said clocks. This - patch renames the defines according to their real function. - - Signed-off-by: Grzegorz Bernacki - Acked-by: Bartlomiej Sieka - -commit a11c0b85dc3664bb3c1e781137118730c8f619ab -Author: Bartlomiej Sieka -Date: Sun May 27 16:51:48 2007 +0200 - - Motion-PRO: Add LED support. - - Signed-off-by: Jan Wrobel - Signed-off-by: Marian Balakowicz - Acked-by: Bartlomiej Sieka - -commit 7ebb4479b07ff294eb4d76e420753a0349f7c93b -Author: Ulf Samuelsson -Date: Thu May 24 12:12:47 2007 +0200 - - [PATCH][NAND] Define the Vendor Id for Micron NAND Flash - - Signed-off-by: Ulf Samuelsson - Signed-off-by: Ladislav Michl - Signed-off-by: Stefan Roese - -commit d756894722c888d09a9fa1df8323753772d3dcce -Author: Stefan Roese -Date: Thu May 24 09:49:00 2007 +0200 - - ppc4xx: Fix small 405EZ OCM initilization bug in start.S - - As pointed out by Bruce Adler this patch - fixes a small bug in the 405EZ OCM initialization. Thanks for - spotting. - - Signed-off-by: Stefan Roese - -commit 5d4a179013d59a76446462e1eb0a969fba63eb81 -Author: Stefan Roese -Date: Thu May 24 08:22:09 2007 +0200 - - ppc4xx: Update AMCC Acadia support for board revision 1.1 - - This patch updates the Acadia (405EZ) support for the new 1.1 board - revision. It also adds support for NAND FLASH via the 4xx NDFC. - - Please note that the jumper J7 must be in position 2-3 for this - NAND support. Position 1-2 is for NAND booting only. NAND booting - support will follow later. - - Signed-off-by: Stefan Roese - -commit 822d55365bb557e084d0e33625a6dedcc866110b -Author: Jon Loeliger -Date: Wed May 23 14:09:46 2007 -0500 - - Add LIST_86xx MAKEALL target for PowerPC builds. - - Signed-off-by: Jon Loeliger - -commit 9f0077abd69f7a7c756a915b961037302be3e6f2 -Author: Stefan Roese -Date: Tue May 22 12:48:09 2007 +0200 - - ppc4xx: Use do { ... } while (0) for CPR & SDR access macros - - Signed-off-by: Stefan Roese - -commit 6f3dfc139a838b0841c151efe00ad47db2366e79 -Author: Stefan Roese -Date: Tue May 22 12:46:10 2007 +0200 - - ppc4xx: Add 405 support to 4xx NAND driver ndfc.c - - This patch adds support for 405 PPC's to the 4xx NAND driver - ndfc.c. This is in preparation for the new AMCC 405EZ. - - Signed-off-by: Stefan Roese - -commit 10603d76767426be803dadd4fb688b97eb69481c -Author: Stefan Roese -Date: Mon May 21 07:41:22 2007 +0200 - - ppc4xx: Fix problem in 405EZ OCM initialization - - As spotted by Bruce Adler this patch fixes an initialization problem - for the 405EZ OCM. - - Signed-off-by: Stefan Roese - -commit 3e3b956906eba9e4ad7931581ecedaad10eccce8 -Author: Peter Pearse -Date: Fri May 18 16:47:03 2007 +0100 - - Reduce line lengths to 80 characters max. - -commit 93ef45c9ddfdd9fc17c4e74bd8e2f2456580eb72 -Author: Peter Pearse -Date: Fri May 18 14:34:07 2007 +0100 - - Makefile permissions - -commit 1443a31457d68f7e8f0b9403e9832ec1e79dc59d -Author: Peter Pearse -Date: Fri May 18 14:33:11 2007 +0100 - - Makefile permissions - -commit 255a3577c848706441daee0174543efe205a77f8 -Author: Kim Phillips -Date: Wed May 16 16:52:19 2007 -0500 - - Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx - - For all practical u-boot purposes, TSECs don't differ throughout the - mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. - - Signed-off-by: Kim Phillips - -commit 70124c2602ae2d4c5d3dba05b482d91548242de8 -Author: Stefano Babic -Date: Wed May 16 14:49:12 2007 +0200 - - Fix compile problem cause my Microblaze merge - - Signed-off-by: Stefano Babic - -commit ada4697d0230d6da552867777f98a67ec3ba2579 -Author: Jeffrey Mann -Date: Wed May 16 13:23:10 2007 +0200 - - [PATCH] Run new sequoia boards with an EBC speed of 83MHz - - Because the Sequoia board does not boot with an EBC faster than 66MHz, - the clock divider are changed after the initial boot process. - - This allows for maximum clocking speeds to be achieved on newer boards. - Sequoia boards with 666.66 MHz processors require that the EBC divider - be set to 3 in order to start the initial boot process at a slower EBC - speed. After the initial boot process, the divider can be set back to 2, - which will cause the boards to run at 83.333MHz. This is backward - compatible with boards with 533.33 MHz processors, as these boards will - already be set with an EBC divider of 2. - - Signed-off-by: Jeffrey Mann - -commit a7676ea7732f3c596805079fed7e5c9fac652cfc -Author: Wolfgang Denk -Date: Wed May 16 01:16:53 2007 +0200 - - Minor Coding Style cleanup, update CHANGELOG. - - Signed-off-by: Wolfgang Denk - -commit d62f64cc23a940eafe712c776b3249e4160753d1 -Author: Wolfgang Denk -Date: Wed May 16 00:13:33 2007 +0200 - - Coding Style Cleanup, new CHANGELOG - -commit 3162eb836903c8b247fdc7470dd39bfa6996f495 -Author: Wolfgang Denk -Date: Tue May 15 23:38:05 2007 +0200 - - Minor coding style cleanup. - -commit 66d9dbec1cc27d6398ee6cf84639dbe14971251e -Author: mushtaq khan -Date: Fri Apr 20 14:23:02 2007 +0530 - - Add driver for S-ATA-controller on Intel processors with South - Bridge, ICH-5, ICH-6 and ICH-7. - - Implementation: - - 1. Code is divided in to two files. All functions, which are - controller specific are kept in "drivers/ata_piix.c" file and - functions, which are not controller specific, are kept in - "common/cmd_sata.c" file. - - 2. Reading and Writing from the S-ATA drive is done using PIO method. - - 3. Driver can be configured for 48-bit addressing by defining macro - CONFIG_LBA48, if this macro is not defined driver uses the 28-bit - addressing. - - 4. S-ATA read function is hooked to the File system, commands like - ext2ls and ext2load file can be used. This has been tested. - - 5. U-Boot command "SATA_init" is added, which initializes the S-ATA - controller and identifies the S-ATA drives connected to it. - - 6. U-Boot command "sata" is added, which is used to read/write, print - partition table and get info about the drives present. This I have - implemented in same way as "ide" command is implemented in U-Boot. - - 7. This driver is for S-ATA in native mode. - - 8. This driver does not support the Native command queuing and - Hot-plugging. - - Signed-off-by: Mushtaq Khan - -commit 644e6fb4eb8be90ea04ba34b643a8bf019d680e0 -Author: mushtaq khan -Date: Mon Apr 30 15:57:22 2007 +0530 - - Fixes bug clearing the bss section for i386 - - Hi, - There is a bug in the code of clearing the bss section for processor - i386.(File: cpu/i386/start.S) - In the code, bss_start addr (starting addr of bss section) is put into - the register %eax, but the code which clears the bss section refers to - the addr pointed by %edi. - - This patch fixes this bug by putting bss_start into %edi register. - - Signed-off-by: Mushtaq Khan - -commit c3243cf7b490057277d61acffe4ad0946f9eb4a4 -Author: Joe Hamman -Date: Mon Apr 30 16:47:28 2007 -0500 - - Add support for BCM5464 Quad Phy - - Added support for Broadcom's BCM5464 Quad Phy - - Signed-off-by: Joe Hamman - -commit 1b305bdc754c8468e1d5d858f5dcf8a7a0a4bb7a -Author: Zang Roy-r61911 -Date: Wed May 9 08:10:57 2007 +0800 - - Search the exception table with linear algorithm - - Search the exception table with linear algorithm instead of - bisecting algorithm. - Because the exception table might be unsorted. - - Signed-off-by: Roy Zang - -commit 5dfaa50eb819686bfba1927e8c5b8a70a4d65fd3 -Author: Aubrey.Li -Date: Mon May 14 11:47:35 2007 +0800 - - Fix compilation issues on MACOSX - - Singed-off-by: Marc Hoffman - Signed-off-by: Aubrey Li - -commit 56fd7162985c412317bbf763a225fba23c64fd31 -Author: Stephen Williams -Date: Tue May 15 07:55:42 2007 -0700 - - Fix for compile of JSE target - - The attached patch fixes the compile of the JSE board in the - denx git as of 14 may 2007. It is an extremely simple patch, - it just adds the missing define of CFG_SYSTEMACE_WIDTH. - - Fix to compile JSE against 20070514 git of u-boot - -commit 69df3c4da0c93017cceb25a366e794570bd0ed98 -Author: Nobuhiro Iwamatsu -Date: Sun May 13 21:01:03 2007 +0900 - - sh: MS7750SE support. - - This adds support for the Hitachi MS7750SE. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 0b135cfc2e524dc249b75057b55dd4cc09842e27 -Author: Nobuhiro Iwamatsu -Date: Sun May 13 20:58:00 2007 +0900 - - sh: First support code of SuperH. - - Signed-off-by: Nobuhiro Iwamatsu - -commit 61936667e86a250ae12fd2dc189d3588f0a59e0b -Author: Stefan Roese -Date: Fri May 11 12:01:49 2007 +0200 - - ppc4xx: Add mtcpr/mfcpr access macros - - Signed-off-by: Stefan Roese - -commit 343c48bd84606c4025c8a7c7263fda465d6e284c -Author: Stefan Roese -Date: Fri May 11 12:01:06 2007 +0200 - - ppc4xx: Set bd->bi_pci_busfreq on 440EPx/GRx too - - Signed-off-by: Stefan Roese - -commit 7d98ba770a7eaefa29ce927f31a0956df85bf650 -Author: Piotr Kruszynski -Date: Thu May 10 16:55:52 2007 +0200 - - [Motion-PRO] Add MTD and JFFS2 support, also add default partition - definition. - -commit 65fb6a676e821f9570a2a376dc204bf611ce5f81 -Author: Peter Pearse -Date: Wed May 9 11:42:44 2007 +0100 - - Add the board directory for SMN42 - -commit 160131bf965785419626df6c388729fe0b597992 -Author: Peter Pearse -Date: Wed May 9 11:41:58 2007 +0100 - - Add the files for the SMN42 board - -commit 5c6d2b5a500f8c49670de8910150b78a41f781fc -Author: Peter Pearse -Date: Wed May 9 11:40:34 2007 +0100 - - Remove the deleted files for the SMN42 patch - -commit b0d8f5bf0d215adc9424cb228b2484dbf07f7761 -Author: Peter Pearse -Date: Wed May 9 11:37:56 2007 +0100 - - New board SMN42 branch - -commit 29f3be0caf0799ca6b89dfd9824c15619a50000f -Author: Peter Pearse -Date: Wed May 9 10:24:38 2007 +0100 - - Makefile permissions - -commit b84289b595731e8851df46e893845cc1322c9b9b -Author: Ed Swarthout -Date: Tue May 8 14:17:07 2007 -0500 - - 8641hpcn: Fix Makefile after moving pixis to board/freescale. - - The OBJTREE != SRCTREE build scenario was broken. - This fixes it. - - Signed-off-by: Ed Swarthout - Signed-off-by: Jon Loeliger - -commit e69f66c6ebe82bbbd1da766bc4eda40ec7ee5af1 -Author: Michal Simek -Date: Tue May 8 15:57:43 2007 +0200 - - add: reading special purpose registers - -commit 1a50f164beb065f360fbddb76029607d6b099698 -Author: Michal Simek -Date: Tue May 8 14:52:52 2007 +0200 - - add: Microblaze V5 exception handling - -commit ab874d5047e5d30dbc1e517ff26083efffa98ecb -Author: Michal Simek -Date: Tue May 8 14:39:11 2007 +0200 - - add: FSL control read and write - -commit de1de02a7cbf05e6b63e0d8ffc624f12493f6ba3 -Author: Piotr Kruszynski -Date: Tue May 8 13:05:44 2007 +0200 - - [Motion-PRO] Add support for I2C, EEPROM and RTC. - -commit fa5c2ba123b1bf88455bfc21db5e786ca045029d -Author: Bartlomiej Sieka -Date: Tue May 8 10:23:56 2007 +0200 - - [Motion-PRO] Add ATA support. Add CF-booting commands to the default +* Patches by Michael Bendzick, 30 Aug 2004: + - Configure omap1510inn board to use drivers/cfi_flash.c + - Make drivers/cfi_flash.c protect environment and redundant environment. -commit 06241d50a3ab1b20a0b08baeeaffcaa23ae4b839 -Author: Bartlomiej Sieka -Date: Tue May 8 09:39:12 2007 +0200 +* Patch by Steven Scholz, 23 Jun 2004: + - Add script (tools/img2brec.sh) to programm U-Boot into + (Synch)Flash using the Bootstrap Mode of the MC9328MX1/L + +* Patches by Scott McNutt, 24 Aug 2004: + - Add support for Altera Nios-II processors. + - Add support for Psyent PCI-5441 board. + - Add support for Psyent PK1C20 board. + +* Patches by Jon Loeliger, 24 Aug 2004: + - Add support for the MPC8541 and MPC8555 CDS boards + - Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR + - Convert MPC85xxADS to use common CFI flash driver + - Fix PCI window on MPC85xx; remove unneeded PCI initialization + from board_early_init_f() + - Provide SW workaround for PCI initialization on 85xx CDS + +* Patches by George G. Davis, 24 Aug 2004: + - Enable ramdisk/initrd tagged param support for omap1610h2_config + - Remove static network setup defaults from mx1ads_config + - update ARM boards to use constants from mach-types.h + +* Patch by Gary Jennejohn, 04 Oct 2004: + - fix I2C on at91rm9200 + - add support for Ricoh RS5C372A RTC + +* Patch by Gary Jennejohn, 01 Oct 2004: + - add support for CMC PU2 board + - add support for I2C on at91rm9200 + +* Patch by Gary Jennejohn, 28 Sep 2004: + fix baudrate handling on at91rm9200 + +* Patch by Yuli Barcohen, 22 Aug 2004: + - remove ZPC.1900 board-specific flash driver; + switch the port to generic CFI driver; + - port clean-up + +* Patch by Hinko Kocevar, 21 Aug 2004: + Add calc_fbsize() function used with VIDEOLFB_TAG on TRAB + +* Clean up tools/bmp_logo.c to not add trailing white space + +* Patch by Hinko Kocevar, 21 Aug 2004: + - Group common framebuffer functions in common/lcd.c + - Group common framebuffer macros and #defines in include/lcd.h + - Provide calc_fbsize() for video ATAG + +* Patch by Sam Song, 21 August 2004: + - Fix a typo in README + - Align "(RO)" output for "flinfo" after "protect on" + - Add RESET support for RPXlite_DW board; adjust CPU:BUS frequency + ratio 1:1 when core frequency less than 50MHz - [Motion-PRO] Change IPB clock frequency from 50MHz to 100MHz. This - eliminates networking problems in Linux (timeouts). +* Patches by Hinko Kocevar, 21 Aug 2004: + - fix some "use of label at end of compound statement" warnings + - Define type of LCD panel on lubbock board if CONFIG_LCD is used -commit 1f1369c34b629be94702684d41d3fddf0f6193e7 -Author: Bartlomiej Sieka -Date: Tue May 8 09:21:57 2007 +0200 +* Patch by Steven Scholz, 16 Aug 2004: + - Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)" + - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0 + - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/ + - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/ + into cpu/arm920t/$(SOC)/ - [Motion-PRO] Enable Flat Device Tree support and modify default environment - to allow booting of FDT-expecting kernels. +* Patches by Sean Chang, 09 Aug 2004: + - Added support for both 8 and 16 bit mode access to System ACE CF + through MPU. + - Fixed missing System ACE CF device during get FAT partition info + in fat_register_device function. + - Enabled System ACE CF support on ML300. -commit fb05f6da35ea1c15c553abe6f23f656bf18dc5db -Author: Michal Simek -Date: Mon May 7 23:58:31 2007 +0200 +* Patch by Sean Chang, 09 Aug 2004: + Synch defines for saveenv and do_saveenv functions so they get + compiled under the same statement. - new: USE_MSR_INTR support +* Patch by Sean Chang, 09 Aug 2004: + - Added I2C support for ML300. + - Added support for ML300 to read out its environment information + stored on the EEPROM. + - Added support to use board specific parameters as part of + U-Boot's environment information. + - Updated MLD files to support configuration for new features + above. -commit 008861a2f3ef2c062744d733787c7e530a1b8761 -Author: Bartlomiej Sieka -Date: Mon May 7 22:36:15 2007 +0200 +* Patches by Travis Sawyer, 05 Aug 2004: + - Remove incorrect bridge settings for eth group 6 + - Add call to setup bridge in ppc_440x_eth_initialize + - Fix ppc_440x_eth_init to reset the phy only if its the + first time through, otherwise, just check the phy for the + autonegotiated speed/duplex. This allows the use of netconsole + - only print the speed/duplex the first time the phy is reset. - [MPC5xxx] There are networking problems on the Motion-PRO board with - current PHY initalization code (tftp timeouts all the time). This commit - temporarily disables PHY initalization sequence to make the networking - operational, until a fix is found. +* Patch by Shlomo Kut, 29 Mar 2004: + Add support for MKS Instruments "Quantum" board -commit abca901869c3760b6c5fecb825db6c1d91a78a93 -Author: Wolfgang Denk -Date: Mon May 7 22:10:36 2007 +0200 +* Fix build problem with Cogent boards; + avoid using when using the host compiler - Get rid of duplicated file (see include/configs/sbc8560.h instead) +* Patch by Ganapathi C, 04 Aug 2004: + Fix NFS timeout issue - Signed-off-by: Wolfgang Denk +* Patch by Yuli Barcohen, 19 Jul 2004: + - Fix host tools building in Cygwin environment + - Fix header files search order for host tools -commit 207b7b2c9d9752e0f6478c30c29b7087f6e6cbb6 -Author: Wolfgang Denk -Date: Mon May 7 22:07:08 2007 +0200 +* Patch by Tom Armistead, 19 Jul 2004: + Fix kgdb.S support for 74xx_75x cpu - Get rid of duplicated file (see doc/README.SBC8560 instead) +* Patch by Jon Loeliger, 15 Jul 2004: + Fix MPC85xx I2C driver - Signed-off-by: Wolfgang Denk +* Fix problems with CDROM drive as slave device on Lite5200 IDE bus. -commit a7bac7e9b57ba948051beb19ec5be3a75ce75383 -Author: Michal Simek -Date: Mon May 7 19:43:10 2007 +0200 +* Patch by Stephen Williams, 15 July 2004 + Set the PCI class code for JSE board as part of PCI interface setup - fix: read and write MSR - repair number of parameters +* Patch by Michael Bendzick, 15 Jul 2004: + Fix problem with writes with odd sizes in drivers/cfi_flash.c when + CFG_FLASH_USE_BUFFER_WRITE is set -commit 193b4a3bb3acaddf798da8de0da05d94ba8774ee -Author: Jeffrey Mann -Date: Mon May 7 19:42:49 2007 +0200 +* Patch by Yuli Barcohen, 13 Jul 2004: + Allow clock setting on MPC866/MPC885 series chips according to + environment variable `cpuclk' - [PATCH] ppc4xx: Fix CONFIG_SYS_CLK_FREQ definition in Sequoia config file +* Patch by Yuli Barcohen, 20 Apr 2004: + Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x - A '3' got cut off in the formatting of the last patch to automatically - change the clock speed of the system clock on sequoia board. +* Patch by Vincent Dubey, 24 Sep 2004: + Add support for xaeniax board - Signed-off-by: Jeffrey Mann - Signed-off-by: Stefan Roese +* Add comment about non-GPL character of standalone applications to + COPYING file -commit 19bf1fbad7f19d5a120be9b1daf136e052fcab39 -Author: Michal Simek -Date: Mon May 7 19:33:51 2007 +0200 +* Fix FEC ethernet problem on NSCU board. - new: fsl interrupt support - FSL_Has_data is connected to INTC. +* Patch by Gary Jennejohn, 09 Sep 2004: + allow to use USART1 as console port on at91rm9200dk boards -commit 792032baa7d625e34c981ab6df521911bd8dc861 -Author: Michal Simek -Date: Mon May 7 19:30:12 2007 +0200 +* Patch by Stefan Roese, 16 Sep 2004: + Update AR405 board. - fix: interrupt handler - remove asm code +* Fix SysClk handling for PPChameleon and CATcenter boards -commit f3f001a341ef185d0f13841be5b5dc3395aacc31 -Author: Michal Simek -Date: Mon May 7 19:25:08 2007 +0200 +* Patch by Detlev Zundel, 08 Sep 2004: + Update etags build target - fix: remove asm code +* Improve NetConsole support: add support for broadcast destination + address and buffered input. -commit fb7c2dbef02c9f6f8d7b04ec4c2bfb91418b9c01 -Author: Michal Simek -Date: Mon May 7 19:12:43 2007 +0200 +* Cleanup compiler warnings for GCC 3.3.x and later - fix: clean interrupt +* Fix problem in cmd_jffs2.c introduced by CFG_JFFS_SINGLE_PART patch -commit 42efed6130c8fcf7da881385b5427065d2801757 -Author: Michal Simek -Date: Mon May 7 17:22:25 2007 +0200 +* Add support for IDS "NC650" board - fix: interrupt handler for multiple sources +* Add automatic update support for LWMON board -commit 48fbd3a4cdabbebc1debd7eed73c00c2caf914f6 -Author: Michal Simek -Date: Mon May 7 17:11:09 2007 +0200 +* Clear Block Lock-Bits when erasing flash on LWMON board. - new: add writing to msr register +* Fix return code of "fatload" command -commit 3a619dd7bed03e8b4d22a3911f90fd12af5376c2 -Author: Markus Klotzbuecher -Date: Mon May 7 16:43:56 2007 +0200 +* Enable MSDOS/VFAT filesystem support for LWMON board - Fix an ancient CHANGELOG conflict +* Patch by Martin Krause, 03 Aug 2004: + change timing for SM501 graphics controller on TQM5200 module -commit ac4cd59d59c9bf3f89cb7a344abf8184d678f562 -Author: Timur Tabi -Date: Sat May 5 08:12:30 2007 +0200 +* Patch by Mark Jonas, 13 July 2004: + - Total5200 LCD now run in little endian mode. Endianess conversion + is done in hardware. + - Removed last reference to "console" environment variable. - 5xxx: write MAC address to mac-address and local-mac-address +* Patches by Lars Munch, 12 Jul 2004: + - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk + board specific + - split out the LXT971A PHY from ns_9750_eth.h + - split the dm9161 phy part out of at91rm9200_ether.c - Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() - should write the MAC address to mac-address and local-mac-address, if they - exist. +* Patch by Andreas Engel, 12 Jul 2004: + Replaced hardcoded PL011 clock frequency with config variable. + Fixed wrong CONFIG_CMD_DFL doc. - Signed-off-by: Timur Tabi - Acked-by: Grant Likely +* Patch by Thomas Viehweger, 09 Jun 2004: + make it possible to remove chpart when there is only one partition -commit a9d87e2707dcb249f6bb7f7ff7e00acd8cda9fd2 -Author: Grzegorz Wianecki -Date: Sun Apr 29 14:01:54 2007 +0200 +* Add support for console over UDP (compatible to Ingo Molnar's + netconsole patch under Linux) - [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message +* Patch by Jon Loeliger, 16 Jul 2004: + - support larger DDR memories up to 2G on the PC8540/8560ADS and + STXGP3 boards + - Made MPC8540/8560ADS be 33Mhz PCI by default. + - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 + and CONFIG_L2_INIT_RAM options. + - Refactor Local Bus initialization out of SDRAM setup. + - Re-implement new version of LBC11/DDR11 errata workarounds. + - Moved board specific PCI init parts out of CPU directory. + - Added TLB entry for PCI-1 IO Memory + - Updated README.mpc85xxads - MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up - message. Use PVR to distinguish between the two variants, and print proper CPU - information. +* Patch by Sascha Hauer, 28 Jun: + - add generic support for Motorola i.MX architecture + - add support for mx1ads, mx1fs2 and scb9328 boards - Signed-off-by: Grzegorz Wianecki - Signed-off-by: Bartlomiej Sieka - Signed-off-by: Grant Likely +* Patches by Marc Leeman, 23 Jul 2004: + - Add define for the PCI/Memory Buffer Configuration Register + - corrected comments in cpu/mpc824x/cpu_init.c -commit 4ec5bd55ed1ffa91a774af298769621f4fbb18c1 -Author: Ladislav Michl -Date: Wed Apr 25 16:01:26 2007 +0200 +* Add support for multiple serial interfaces + (for example to allow modem dial-in / dial-out) - [PATCH] simplify silent console +* Patch by Stefan Roese, 15 Jul 2004: + cpu/ppc4xx/sdram.c rewritten now using get_ram_size() - Signed-off-by: Ladislav Michl - Acked-by: Stefan Roese +* Fix NSCU config; add ethernet wakeup code. -commit b7598a43f2b421a713d8135e98a42c37d9eb9df0 -Author: Sergei Shtylyov -Date: Mon Apr 23 15:30:39 2007 +0200 +* Add link for preloader for Motorola ColdFire to README.m68k - [PATCH] Avoid assigning PCI resources from zero address +* Patch by Michael Bendzick, 12 Jul 2004: + fix output formatting in drivers/cfi_flash.c - If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE - core complains and IDE drivers fails to work. Also, assigning zero to a BAR - was illegal according to PCI 2.1 (the later revisions seem to have excluded the - sentence about "0" being considered an invalid address) -- so, use a reasonable - starting value of 0x1000 (that's what the most Linux archs are using). +* Patch by Mark Jonas, 02 Jul 2004: + Fix lowboot (again) on MPC5xxx - Alternatively, one might have fixed the calls to pci_set_region() individually - (some code even seems to have taken care of this issue) but that would have - been a lot more work. :-) +* Patch by Curt Brune, 07 Jul 2004: + relocate exception vectors on arm720t if needed - Signed-off-by: Sergei Shtylyov - Acked-by: Stefan Roese +* Patch by George G. Davis, 06 Jul 2004: + - update mach-types.h to latest arm.linux.org.uk master list + - Set correct OMAP1610 bi_arch_number for build target -commit 9ffd451afeb08e5be7ddae680487ec962b2bca25 -Author: Jeffrey Mann -Date: Mon Apr 23 14:00:11 2007 +0200 +* Patch by Curt Brune, 06 Jul 2004: + evb4510: add support for timer interrupt; cleanup - [patch] setenv(...) can delete environmentalvariables +* Patch by Dan Poirot, 06 Jul 2004: + Fix sbc8260 environment variables - update setenv() function so that entering a NULL value for the - variable's value will delete the environmental variable +* Cleanup redundand "console" environment variable - Signed-off-by: Jeffrey Mann - Acked-by: Stefan Roese +* Patch by Mark Jonas, 05 Jul 2004: + add support for the Total5100's and Total5200's LCD screen -commit ebd0a0ae05a44769c4e27458ad4e9f3438250443 -Author: Mike Frysinger -Date: Mon Apr 23 13:54:24 2007 +0200 +* Patches by Dan Eisenhut, 01 Jul 2004: + - README fixes. + - Move doc2000.h include to prevent compiler warning on some boards - [patch] use unsigned char in smc91111 driver for mac +* Patch by Mark Jonas, 01 Jul 2004: + Added support for Total5100 and Total5200 (Rev.1 and Rev.2) + MGT5100 and MPC5200 based Freescale platforms. - the v_mac variable in the smc91111 driver is declared as a signed char ... - this causes problems when one of the bytes in the MAC is "signed" like 0xE0 - because when it gets printed out, you get a display like: - 0xFFFFFFE0 and that's no good +* Patch by Philippe Robin, 01 Jul 2004: + Add initialization for Integrator and versatile board files. - Signed-off-by: Mike Frysinger +* Patch by Hinko Kocevar, 01 Jun 2004: + Fix VFD FB allocation, add LCD FB allocation on ARM -commit ffc50f9bb194343c6303517a517708457a5eb6b8 -Author: Michal Simek -Date: Sat May 5 18:54:42 2007 +0200 +* Patch by Martin Krause, 30 Jun 2004: + Add support for TQM5200 board - new: FSL and MSR support #2 +* Patch by Martin Krause, 29 Jun 2004: + Add loopw command: infinite write loop on address range -commit f7e2e0eb0668136305f78bb9c21be79b48a34247 -Author: Michal Simek -Date: Sat May 5 18:27:16 2007 +0200 +* Patches by Yasushi Shoji, 29 Jun 2004: + - add empty include/asm-microblaze/processor.h + - add to CREDITS and MAINTAINERS + - add gd initialization + - add MicroBlaze and SUZAKU board to MAKEALL script + - add reset support for SUZAKU + - add flush_cache() for MicroBlaze + - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed + size flash memory on SUZAKU - new: FSL and MSR support +* Patch by Prakash Kumar, 27 Jun 2004: + Add support for the PXA250 based Intrinsyc Cerf board. -commit 2f15278c2eb911c668b4fe562130b78cf554d139 -Author: Wolfgang Denk -Date: Sat May 5 18:23:11 2007 +0200 +* Patch by Yasushi Shoji, 27 Jun 2004: + fix comment in include/common.h - Coding stylke cleanup; update CHANGELOG. +* Rename SBC8560 into sbc8560 for consistency - Signed-off-by: Wolfgang Denk +* Patch by Daniel Poirot, 24 Jun 2004: + Add support for Wind River's sbc8240 board -commit 885ec89b648a899a2f32393fd3ffd9f7234c4402 -Author: Wolfgang Denk -Date: Sat May 5 18:05:02 2007 +0200 +* Patches by Yasushi Shoji, 26 Jun 2004: + - drivers/serial_xuartlite.c: fix "return 0" in void function + - add microblaze support to mkimage tool - Add STX GP3 SSA board to MAKEALL script; update CHANGELOG. +* Patch by Fred Klatt, 25 Jun 2004: + Add support for WindRiver's sbc8560 board - Signed-off-by: Wolfgang Denk +* Patch by Nicolas Lacressonniere, 24 Jun 2004 + Small Bugs fixes for "at91rm9200dk" board: + - Timing modifications for SPI DataFlash access + - Fix NAND flash detection bug -commit 5499645b3fe17a548af9dfc479ca6e2455f179a2 -Author: Wolfgang Denk -Date: Sat May 5 17:15:50 2007 +0200 +* Patch by Nicolas Lacressonniere, 24 Jun 2004: + Add Support for Flash AT49BV6416 for AT91RM9200DK board - Make "file" command happy with some config.mk files; update CHANGELOG +* Patch by Jon Loeliger, 17 June 2004: + Completion of the 8540ADS/8560ADS updates: + Fix some PCI and Rapid I/O memory maps, + Initialize both TSEC 1 and 2, + Initialize SDRAM + Update MAINTAINER for 85xx boards and README.mpc85xxads -commit e3b8c78bc2489c27ae020986ef0eaca684866cef -Author: Jeffrey Mann -Date: Sat May 5 08:32:14 2007 +0200 +* Patch by Yuli Barcohen, 16 Jun 2004: + Remove obsolete AdderII port which was superseded by unified + AdderII/Adder87x port - ppc4xx: Detect if the sysclk on Sequoia is 33 or 33.333 MHz +* Patch by Ladislav Michl, 16 Jun 2004: + Fix gcc-3.3.3 warnings for smc91111.c - The AMCC Secquoia board has been changed in a new revision from using a - 33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD - indicates the difference. This patch reads that bit and uses the correct - clock speed for the board. This code is backward compatable will all - prior boards. All prior boards will be read as 33.000. +* Patch by Stefan Roese, 02 Jul 2004: + - Fix bug in 405 ethernet driver; allocated data not cleared! + - Fix problem in 405 i2c driver; don't try to print without console! - Signed-off-by: Jeffrey Mann - Signed-off-by: Stefan Roese +* Patch by Paul Ruhland, 11 Jun 2004: + Remove debug code from 'board/lpd7a40x/flash.c' -commit f544ff6656fca263ed1ebe39899b6d95da67c8b8 -Author: Stefan Roese -Date: Sat May 5 08:29:01 2007 +0200 +* Patch by Andrea Marson, 11 Jun 2004: + Update for PPChameleon board: + - support for SysClk @ 25MHz + - support for Silicon Motion SM712 VGA controller + - some clean ups - ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting +* Patches by Richard Woodruff, 10 Jun 2004: + - fix problems with examples/stubs.c for GCC >= 3.4 + - fix problems with gd initialization - Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big - for the 4k NAND boot image so define bus_frequency to 133MHz here - which is save for the refresh counter setup. +* Patch by Curt Brune, 17 May 2004: + - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC) + - Add support for ESPD-Inc. EVB4510 Board - Signed-off-by: Stefan Roese +* Patch by Marc Leeman, 11 May 2004: + Fix for MPC8245 - reading PPC Memory from another device with the + PPC as PCI target device corrupts data due to interenal hardware + buffering. -commit 2f550ab976405300f5b07bf2890800840d0aa05f -Author: Timur Tabi -Date: Sat May 5 08:12:30 2007 +0200 +* Fix "cls" command when used with splash screen - 5xxx: write MAC address to mac-address and local-mac-address +* Increase NFS download timeout (now 1 min - 10 sec is to short for a + slow download of a big image) - Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() - should write the MAC address to mac-address and local-mac-address, if they - exist. +* Add "cls" function to MPC823 LCD driver so we can reinitialize the + display even after showing a bitmap - Signed-off-by: Timur Tabi - Acked-by: Grant Likely +* Patch by Josef Wagner, 04 Jun 2004: + - DDR Ram support for PM520 (MPC5200) + - support for different flash types (PM520) + - USB / IDE / CF-Card / DiskOnChip support for PM520 + - 8 bit boot rom support for PM520/CE520 + - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245) + - I2C and RTC support for CPC45 + - support of new flash type (28F160C3T) for CPC45 -commit a79886590593ba1d667c840caa4940c61639f18f -Author: Thomas Knobloch -Date: Sat May 5 07:04:42 2007 +0200 +* Fix flash parameters passed to Linux for PPChameleon board - NAND: Wrong calculation of page number in nand_block_bad() +* Remove eth_init() from lib_arm/board.c; it's done in net.net.c. - In case that there is no memory based bad block table available the - function nand_block_checkbad() in drivers/mtd/nand/nand_base.c will call - nand_block_bad() directly. When parameter 'getchip' is set to zero, - nand_block_bad() will not right shift the offset to calculate the - correct page number. +* Patch by Paul Ruhland, 10 Jun 2004: + fix support for Logic SDK-LH7A404 board and clean up the + LH7A404 register macros. - Signed-off-by: Thomas Knobloch - Signed-off-by: Stefan Roese +* Patch by Matthew McClintock, 10 Jun 2004: + Modify code to select correct serial clock on Sandpoint8245 -commit 9877d7dcd1eebe61aa5d8b8ffe9c048ea426e6f6 -Author: Wolfgang Denk -Date: Fri May 4 10:02:33 2007 +0200 +* Patch by Robert Schwebel, 10 Jun 2004: + Add support for Intel K3 strata flash. - Fix initrd length corruption in bootm command. +* Patch by Thomas Brand, 10 Jun 2004: + Fix "loads" command on DK1S10 board - When using FDT Images, the length of an inital ramdisk was - overwritten (bug introduced by commit 87a449c8, 22 Aug 2006). +* Patch by Yuli Barcohen, 09 Jun 2004: + Add support for 8MB flash SIMM and JFFS2 file system on + Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS). + +* Patch by Yuli Barcohen, 09 Jun 2004: + Add support for Analogue&Micro Adder87x and the older AdderII board. + +* Patch by Ming-Len Wu, 09 Jun 2004: + Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board + +* Patch by Sam Song, 09 Jun 2004: + - Add support for RPXlite_DW board + - Update FLASH driver for 4*AM29DL323DB90VI + - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board + +* Patch by Mark Jonas, 08 June 2004: + - Make MPC5200 boards evaluate the SVR to print processor name and + version in checkcpu() (cpu/mpc5xxx/cpu.c). + +* Patch by Kai-Uwe Bloem, 06 May 2004: + Fix endianess problem in cramfs code + +* Patch by Tom Armistead, 04 Jun 2004: + Add support for MAX6900 RTC + +* Patches by Ladislav Michl, 03 Jun 2004: + - fix cfi_flash.c on LE systems + - let 'make mrproper' delete u-boot.img as well + - turn printf into debug in cfi_flash.c + +* Patch by Kurt Stremerch, 28 May 2004: + Add support for Exys XSEngine board + +* Patch by Martin Krause, 27 May 2004: + Fix a MPC5xxx I2C timing issue in i2c_probe(). + +* Patch by Leif Lindholm, 27 May 2004: + Fix board_init_f() for dbau1x00 board. + +* Patch by Imre Deak, 26 May 2004: + On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3). + Set flash base accordingly, and decide whether to do or skip board + specific setup steps. + +* Patch by Josef Baumgartner, 26 May 2004: + Add missing define in include/asm-m68k/global_data.h + +* Patch by Josef Baumgartner, 25 May 2004: + Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c + +* Patch by Paul Ruhland, 24 May 2004: + fix SDRAM initialization for LPD7A400 board. - Patches by Timur Tabi & Johns Daniel. +* Patch by Jian Zhang, 20 May 2004: + add support for environment in NAND flash - Signed-off-by: Wolfgang Denk +* Patch by Yuli Barcohen, 20 May 2004: + Add support for Interphase iSPAN boards. + +* Patches by Paul Ruhland, 17 May 2004: + - Add I/O functions to the smc91111 ethernet driver to support the + Logic LPD7A40x boards. + - Add support for the Logic Zoom LH7A40x based SDK board(s), + specifically the LPD7A400. -commit 068aab660bc3912b930be5540e6b3f3fd6ad3c96 -Author: Kim Phillips -Date: Thu May 3 19:43:52 2007 -0500 +* Patches by Robert Schwebel, 15 May 2004: + - call MAC address reading code also for SMSC91C111; + - make SMSC91C111 timeout configurable, remove duplicate code + - fix get_timer() for PXA + - update doc/README.JFFS2 + - use "bootfile" env variable also for jffs2 + +* Patch by Tolunay Orkun, 14 May 2004: + Add support for Cogent CSB472 board (8MB Flash Rev) + +* Patch by Thomas Viehweger, 14 May 2004: + - flash.h: more flash types added + - immap_8260.h: some bits added (useful for RMII) + - cmd_coninfo.c: typo corrected, printf -> puts + - reduced size by replacing spaces with tab + +* Patch by Robert Schwebel, 13 May 2004: + Add 'imgextract' command: extract one part of a multi file image. + +* Patches by Jon Loeliger, 11 May 2004: + Dynamically handle REV1 and REV2 MPC85xx parts. + (Jon Loeliger, 10-May-2004). + New consistent memory map and Local Access Window across MPC85xx line. + New CCSRBAR at 0xE000_0000 now. + Add RAPID I/O memory map. + New memory map in README.MPC85xxads + (Kumar Gala, 10-May-2004) + Better board and CPU identification on MPC85xx boards at boot. + (Jon Loeliger, 10-May-2004) + SDRAM clock control fixes on MPC8540ADS & MPC8560 boards. + Some configuration options for MPC8540ADS & MPC8560ADS cleaned up. + (Jim Robertson, 10-May-2004) + Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver. + Supports multiple PHYs. + (Andy Fleming, 10-May-2004) + Some README.MPC85xxads updates. + (Kumar Gala, 10-May-2004) + Copyright updates for "Freescale" + (Andy Fleming, 10-May-2004) - mpc83xx: fix trivial error in MAKEALL +* Patch by Stephen Williams, 11 May 2004: + Add flash support for ST M29W040B + Reduce JSE specific flash.c to remove dead code. - Signed-off-by: Kim Phillips +* Patch by Markus Pietrek, 04 May 2004: + Fix clear_bss code for ARM systems (all except s3c44b0 which + doesn't clear BSS at all?) -commit c64a89d6ce8584b9fc64f4e85da9ecac3cfc2c2a -Author: Wolfgang Denk -Date: Thu May 3 16:34:41 2007 +0200 +* Fix "ping" problem on INC-IP board. Strange problem: + Sometimes the store word instruction hangs while writing to one of + the Switch registers, but only if the next instruction is 16-byte + aligned. Moving the instruction into a separate function somehow + makes the problem go away. - Update board configuration for STX GP3SSA board: +* Patch by Rishi Bhattacharya, 08 May 2004: + Add support for TI OMAP5912 OSK Board - Enable hush shell, environment in flash rather in EEPROM, - more user-friendly default environment, etc. - The simple EEPROM environment can be selected easily in the board - config file. +* Patch by Sam Song May, 07 May 2004: + Fix typo of UPM table for rmu board - Signed-off-by: Wolfgang Denk +* Patch by Pantelis Antoniou, 05 May 2004: + - Intracom board update. + - Add Codec POST. -commit 2c6fb199dc5756fc72f49d1f4de105e089049d65 -Author: Wolfgang Denk -Date: Tue Apr 24 14:37:49 2007 +0200 +* Add support for the second Ethernet interface for the 'PPChameleon' + board. - Cleanup STX GP3SSA code; fix build and compile problems. +* Patch by Dave Peverley, 30 Apr 2004: + Add support for OMAP730 Perseus2 Development board -commit 35171dc04e028ecacc23ad916a66295472555dbf -Author: Dan Malek -Date: Fri Jan 5 09:15:34 2007 +0100 +* Patch by Alan J. Luse, 29 Apr 2004: + Fix flash chip-select (OR0) option register setting on FADS boards. - Add support for STX GP3SSA (stxssa) Board +* Patch by Alan J. Luse, 29 Apr 2004: + Report MII network speed and duplex setting properly when + auto-negotiate is not enabled. - Signed-off-by Dan Malek, +* Patch by Jarrett Redd, 29 Apr 2004: + Fix hang on reset on Ocotea board due to flash in wrong mode. -commit f2134f8e9eb006bdcd729e89f309c07b2fa45180 -Author: Haavard Skinnemoen -Date: Wed May 2 13:31:53 2007 +0200 +* Patch by Dave Peverley, 29 Apr 2004: + add MAC address detection to smc91111 driver - macb: Don't restart autonegotiation if we already have link +* Patch by David Müller, 28 Apr 2004: + fix typo in lib_arm/board.c - Rework macb_phy_init so that it doesn't attempt to re-negotiate if the - link is already up. +* Patch by Tolunay Orkun, 20 Apr 2004: + - README update: add CONFIG_CSB272 and csb272_config + - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and + i2cfast environment variable - Signed-off-by: Haavard Skinnemoen +* Patch by Yuli Barcohen, 19 Apr 2004: + - Rename DUET_ADS to MPC885ADS + - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY + - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY + - Clean up FADS family port to use the new defines -commit 04fcb5d38bc90779cd9a710d60702075986f0e29 -Author: Haavard Skinnemoen -Date: Wed May 2 13:22:38 2007 +0200 +* Fix PCI support on CPC45 board - macb: Introduce a few barriers when dealing with DMA descriptors +* Patch by Scott McNutt, 25 Apr 2004: + Add Nios GDB/JTAG Console support: + - Add stubs to support gdb via JTAG. + - Add support for console over JTAG. + - Minor cleanup. - There were a few theoretical possibilities that the compiler might - optimize away DMA descriptor reads and/or writes and thus cause - synchronization problems with the hardware. Insert barriers where - we depend on reads/writes actually hitting memory. +* Add support for CATcenter board (based on PPChameleon ME module) - Signed-off-by: Haavard Skinnemoen +* Patch by Klaus Heydeck, 12 May 2004: + Using external watchdog for KUP4 boards in mpc8xx/cpu.c; + load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c; + various changes to KUP4 board specific files -commit ffa621a0d12a1ccd81c936c567f8917a213787a8 -Author: Andy Fleming -Date: Sat Feb 24 01:08:13 2007 -0600 +* Fix minor network problem on MPC5200: need some delay between + resetting the PHY and sending the first packet. Implemented in a + "natural" way by invoking the PHY reset and initialization code + only once after power on vs. each time the interface is brought up. - Cleaned up some 85xx PCI bugs +* Add some limited support for low-speed devices to SL811 USB controller + (at least "usb reset" now passes successfully and "usb info" displays + correct information) - * Cleaned up the CDS PCI Config Tables and added NULL entries to - the end - * Fixed PCIe LAWBAR assignemt to use the cpu-relative address - * Fixed 85xx PCI code to assign powar region sizes based on the - config values (rather than hard-coding them) - * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address +* Change init sequence for multiple network interfaces: initialize + on-chip interfaces before external cards. - Signed-off-by: Andy Fleming +* Fix memory leak in the NAND-specific JFFS2 code -commit 6743105988fc44d5b0d30388c790607835aae7a6 -Author: Andy Fleming -Date: Mon Apr 23 02:54:25 2007 -0500 +* Fix SL811 USB controller when attached to a USB hub - Add support for the 8568 MDS board +* Fix config option spelling in PM520 config file - This included some changes to common files: - * Add 8568 processor SVR to various places - * Add support for setting the qe bus-frequency value in the dts - * Add the 8568MDS target to the Makefile +* Fix PHY discovery problem in cpu/mpc8xx/fec.c (introduced by + patches by Pantelis Antoniou, 30 Mar 2004) - Signed-off-by: Andy Fleming +* Fix minor NAND JFFS2 related issue -commit af1c2b84bf27c8565baddc82d1abb93700d10e2e -Author: David Updegraff -Date: Fri Apr 20 14:34:48 2007 -0500 +* Fixes for SL811 USB controller: + - implement workaround for broken memory stick + - improve error handling - Add support for treating unknown PHYs as generic PHYs. +* Increase packet send timeout to 1 ms in cpu/mpc8xx/scc.c to better + cope with congested networks. - When bringing up u-boot on new boards, PHY support sometimes gets - neglected. Most PHYs don't really need any special support, - though. By adding a generic entry that always matches if nothing - else does, we can provide support for "unsupported" PHYs for the - tsec. +====================================================================== +Changes for U-Boot 1.1.1: +====================================================================== - The generic PHY driver supports most PHYs, including gigabit. +* Patch by Travis Sawyer, 23 Apr 2004: + Fix VSC/CIS 8201 phy descrambler interoperability timing due to + errata from Vitesse Semiconductor. - Signed-off-by: David Updegraff - Signed-off-by: Andy Fleming +* Patch by Philippe Robin, 22 Apr 2004: + Fix ethernet configuration for "versatile" board -commit a75af9bfd8fff0499efdbb90601cec5a2afef117 -Author: James Yang -Date: Wed Feb 7 15:28:04 2007 -0600 +* Patch by Kshitij Gupta, 21 Apr 2004: + Remove busy loop and use MPU timer fr usleep() on OMAP1510/1610 boards - Conditionalize 8641 Rev1.0 MCM workarounds +* Patch by Steven Scholz, 24 Feb 2004: + Fix a bug in AT91RM9200 ethernet driver: + The MII interface is now initialized before accessing the PHY. - Signed-off-by: James Yang - Signed-off-by: Jon Loeliger +* Patch by John Kerl, 19 Apr 2004: + Use U-boot's miiphy.h for PHY register names, rather than + introducing a new header file. -commit f64702b7fc8f8df39d31add770df6e372f9e9ce3 -Author: Timur Tabi -Date: Mon Apr 30 13:59:50 2007 -0500 +* Update pci_ids.h from linux-2.4.26 - Fix memory initialization on MPC8349E-mITX +* Patch by Masami Komiya, 19 Apr 2004: + Fix problem cause by VLAN function on little endian architecture + without VLAN environment - Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. - This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary - on some ITX boards, notably those with a revision 3.1 CPU. +* Clean up the TQM8xx_YYMHz configurations; allow to use the same + binary image for all clock frequencies. Implement run-time + optimization of flash access timing based on the actual bus + frequency. - Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into - ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. +* Modify KUP4X board configuration to use SL811 driver for USB memory + sticks (including FAT / VFAT filesystem support) - Signed-off-by: Timur Tabi - Acked-by: Michael Benedict - Signed-off-by: Kim Phillips +* Add SL811 Host Controller Interface driver for USB -commit 54b2d434ae9d01787936f34fe1759cf3d7624ae3 -Author: Kim Phillips -Date: Mon Apr 30 15:26:21 2007 -0500 +* Add CFG_I2C_EEPROM_ADDR_OVERFLOW desription to README - mpc83xx: replace elaborate boottime verbosity with 'clocks' command +* Patch by Pantelis Antoniou, 19 Apr 2004: + Allow to use shell style syntax (i. e. ${var} ) with standard parser. + Minor patches for Intracom boards. - and fix CPU: to align with Board: display text. +* Patch by Christian Pell, 19 Apr 2004: + cleanup support for CF/IDE on PCMCIA for PXA25X - Signed-off-by: Kim Phillips +* Temporarily disabled John Kerl's extended MII command code because + "miivals.h" is missing -commit c1ab82669d9525998c34e802a12cad662723f22a -Author: James Yang -Date: Fri Mar 16 13:02:53 2007 -0500 +* Patches by Mark Jonas, 13 Apr 2004: + - Remove CS0 chip select timing setting from cpu/mpc5xxx/start.S + - Add sync instructions to IceCube SDRAM init code + - Move SDRAM chip constants into seperate include files + - Unify DDR and SDR initialization code + - Unify all IceCube (Lite5xxx) target names - Rewrote picos_to_clk() to avoid rounding errors. - Clarified that conversion is to DRAM clocks rather than platform clocks. - Made function static to spd_sdram.c. +* Patch by John Kerl, 16 Apr 2004: + Enable ranges in mii command, e.g. mii read 0-1f 0 or + mii read 4-7 18-1a. Also add mii dump subcommand for + pretty-printing standard regs 0-5. - Signed-off-by: James Yang - Signed-off-by: Jon Loeliger +* Patch by Stephen Williams, 16 April 2004: + fix typo in JSE.h; update MAINTAINERS -commit 8b39501d28754e72726ce7fb02310e56dbdf116a -Author: Stefan Roese -Date: Sun Apr 29 14:13:01 2007 +0200 +* Patch by Matthew S. McClintock, 14 Apr 2004: + fix initdram function for utx8245 board - ppc4xx: Bamboo: Use current NAND driver and *not* the legacy driver +* Patch by Markus Pietrek, 14 Apr 2004: + use ATAG_INITRD2 instead of deprecated ATAG_INITRD tag + +* Patch by Reinhard Meyer, 18 Apr 2004: + provide the IDE Reset Function for EMK 5200 boards - Signed-off-by: Stefan Roese +* Patch by Masami Komiya, 12 Apr 2004: + fix pci_hose_write_config_{byte,word}_via_dword problems + +* Patch by Sangmoon Kim, 12 Apr 2004: + Update max RAM size for debris board -commit 864aa6a6a466fcb92bf32b1d7dba79cd709b52c9 -Author: Grzegorz Wianecki -Date: Sun Apr 29 14:01:54 2007 +0200 +* Patch by Travis Sawyer, 08 Apr 2004: + Add TLB entry for second DIMM slot on ocotea - [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message +* Patch by Masami Komiya, 08 Apr 2004: + add RTL8169 network driver - MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up - message. Use PVR to distinguish between the two variants, and print proper CPU - information. +* Patch by Dan Malek, 07 Apr 2004: + - Add support for RPC/STx GP3, Motorola 8560 board + - Update 85xx TSEC driver so it searches MII for first available PHY + and uses that one. + - Add functions to support console MII commands. + +* Patch by Tolunay Orkun, 07 Apr 2004: + Move initialization of bi_iic_fast[] + from board_init_f() to board_init_r() + +* Patch by Yasushi Shoji, 07 Apr 2004: + Cleanup microblaze port + +* Patch by Sangmoon Kim, 07 Apr 2004: + Add auto SDRAM module detection for Debris board + +* Patch by Rune Torgersen, 06 Apr 2004: + - Fix some PCI problems on the MPC8266ADS board + - Fix the location of some PCI entries in the immap structure + +* Patch by Yasushi Shoji, 07 Apr 2004: + - add support for microblaze processors + - add support for AtmarkTechno "suzaku" board + +* Configure PPChameleon board to use redundand environment in flash + +* Configure PPChameleon board to use JFFS2 NAND support. + +* Added support for JFFS2 filesystem (read-only) on top of NAND flash + +* Patch by Rune Torgersen, 16 Apr 2004: + LBA48 fixes + +* Patches by Pantelis Antoniou, 16 Apr 2004: + - add support for a new version of an Intracom board and fix + various other things on others. + - add verify support to the crc32 command (define + CONFIG_CRC32_VERIFY to enable it) + - fix FEC driver for MPC8xx systems: + 1. fix compilation problems for boards that use dynamic + allocation of DPRAM + 2. shut down FEC after network transfers + - HUSH parser fixes: + 1. A new test command was added. This is a simplified version of + the one in the bourne shell. + 2. A new exit command was added which terminates the current + executing script. + 3. Fixed handing of $? (exit code of last executed command) + - Fix some compile problems; + add "once" functionality for the netretry variable + +* Patch by George G. Davis, 02 Apr 2004: + add support for Intel Assabet board + +* Patch by Stephen Williams, 01 Apr 2004: + Add support for Picture Elements JSE board + +* Patch by Christian Pell, 01 Apr 2004: + Add CompactFlash support for PXA systems. + +* Patches by Pantelis Antoniou, 30 Mar 2004: + - add auto-complete support to the U-Boot CLI + - add support for NETTA and NETPHONE boards; fix NETVIA board + - add support for the Epson 156x series of graphical displays + (These displays are serial and not suitable for using a normal + framebuffer console on them) + - add infrastructure needed in order to POST any DSPs in a board + - improve and fix various things in the MPC8xx FEC driver: + 1. The new 87x and 88x series of processors have two FECs, + and the new driver supports them both. + 2. Another change in the 87x/88x series is support for + the RMII (Reduced MII) interface. However numerous + changes are needed to make it work since the PHYs + are connected to the same lines. That means that + you have to address them correctly over the MII + interface. + 3. We now correctly match the MII/RMII interface + configuration to what the PHY reports. + - Fix problem when readingthe MII status register. Due to the + internal design of many PHYs you have to read the register + twice. The problem is more apparent in 10Mbit mode. + - add new mode ".jffs2s" for reading from a NAND device: it just + skips over bad blocks. + - add networking support for VLANs (802.1q), and CDP (Cisco + Discovery Protocol) + - some minor patches / cleanup + +* Patch by Yuli Barcohen, 28 Mar 2004: + - Add support for MPC8272 family including MPC8247/8248/8271/8272 + - Add support for MPC8272ADS evaluation board (another flavour of MPC8260ADS) + - Change configuration method for MPC8260ADS family + +* add startup code to clear the BSS of standalone applications + +* Fix if / elif handling bug in HUSH shell + +====================================================================== +Changes for U-Boot 1.1.0: +====================================================================== + +* Patch by Mark Jonas: Remove config.tmp files only when + unconfiguring the board + +* Adapt RMU board for bigger flash memory + +* Patch by Klaus Heydeck, 13 Mar 2003: + Add support for KUP4X Board + +* Patch by Pavel Bartusek, 21 Mar 2004 + Add Reiserfs support + +* Patch by Hinko Kocevar, 20 Mar 2004 + - Add auto-release for SMSC LAN91c111 driver + - Add save/restore of PTR and PNR regs as suggested in datasheet + +* Patch by Stephen Williams, 19 March 2004 + Increase speed of sector reads from SystemACE, + shorten poll timeout and remove a useless reset + +* Patch by Tolunay Orkun, 19 Mar 2004: + Make GigE PHY 1000Mbps Speed/Duplex detection conditional + (CONFIG_PHY_GIGE) + +* Patch by Brad Kemp, 18 Mar 2004: + prevent machine checks during a PCI scan + +* Patch by Pierre Aubert, 18 Mar 2004: + Fix string cleaning in IDE identification + +* Patch by Pierre Aubert, 18 Mar 2004: + - Unify video mode handling for Chips & Technologies 69000 Video + chip and Silicon Motion SMI 712/710/810 Video chip + - Add selection of the video output (CRT or LCD) via 'videoout' + environment variable for the Silicon Motion + - README update + +* Patch by Pierre Aubert, 18 Mar 2004: + include/common.h typo fix + +* Patches by Tolunay Orkun, 17 Mar 2004: + - Add support for bd->bi_iic_fast[] initialization via environment + variable "i2cfast" (CONFIG_I2CFAST) + - Add "i2cfast" u-boot environment variable support for csb272 + +* Patch by Carl Riechers, 17 Mar 2004: + Ignore '\0' characters in console input for use with telnet and + telco pads. + +* Patch by Leon Kukovec, 17 Mar 2004: + typo fix for strswab prototype #ifdef - Signed-off-by: Grzegorz Wianecki - Signed-off-by: Bartlomiej Sieka - Signed-off-by: Grant Likely +* Patches by Thomas Viehweger, 16 Mar 2004: + - show PCI clock frequency on MPC8260 systems + - add FCC_PSMR_RMII flag for HiP7 processors + - in do_jffs2_fsload(), take load address from load_addr if not set + explicit, update load_addr otherwise + - replaced printf by putc/puts when no formatting is needed + (smaller code size, faster execution) -commit 5c5d3242935cf3543af01142627494434834cf98 -Author: Kim Phillips -Date: Wed Apr 25 12:34:38 2007 -0500 +* Patch by Phillippe Robin, 16 Mar 2004: + avoid dereferencing NULL pointer in lib_arm/armlinux.c + +* Patch by Stephen Williams, 15 Mar 2004: + Fix CONFIG_SERIAL_SOFTWARE_FIFO documentation - mpc83xx: minor fixups for 8313rdb introduction +* Patch by Tolunay Orkun, 15 Mar 2004: + Initialize bi_opbfreq to real OPB frequency via get_OPB_freq() -commit ada4d40091f6ed4a4f0040e08d20db21967e4a67 -Author: Ladislav Michl -Date: Wed Apr 25 16:01:26 2007 +0200 +* Patch by Travis Sawyer, 15 Mar 2004: + Update CREDITS & MAINTAINERS files for PPC440GX & Ocotea port - [PATCH] simplify silent console +* Add start-up delay to make sure power has stabilized before + attempting to switch on USB on SX1 board. - Signed-off-by: Ladislav Michl - Acked-by: Stefan Roese +* Patch by Josef Wagner, 18 Mar 2004: + - Add support for MicroSys XM250 board (PXA255) + - Add support for MicroSys PM828 board (MPC8280) + - Add support for 32 MB Flash on PM825/826 + - new SDRAM refresh rate for PM825/PM826 + - added support for MicroSys PM520 (MPC5200) + - replaced Query by Identify command in CPU86/flash.c + to support 28F160F3B -commit 144876a380f5756f57412caf74c1d6dc201dd796 -Author: Michal Simek -Date: Tue Apr 24 23:01:02 2007 +0200 +* Fix wrap around problem with udelay() on ARM920T - [PATCH] MTD partition support, JFFS2 support +* Add support for Macronix flash on TRAB board -commit 37ed6cdd4159195bfad68d8a237f6adda8f482cb -Author: Matthias Fuchs -Date: Tue Apr 24 14:03:45 2007 +0200 +* Patch by Pierre Aubert, 15 Mar 2004: + Fix buffer overflow in IDE identification - ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content. +* Fix power-off of LCD for out-of-band temperatures on LWMON board - Signed-off-by: Matthias Fuchs +* Remove redundand #define in IceCube.h -commit 66ed6cca3f340f7a8a06d9272ae2ef8e96f0273d -Author: Andy Fleming -Date: Mon Apr 23 02:37:47 2007 -0500 +* Patch by Steven Scholz, 27 Feb 2004: + - Adding get_ticks() and get_tbclk() for AT91RM9200 + - Many white space fixes in cpu/at91rm9200/interrupts.c - Reworked 85xx speed detection code +* Patches by Steven Scholz, 20 Feb 2004: + some cleanup in AT91RM9200 related code - Changed the code to read the registers and calculate the clock - rates, rather than using a "switch" statement. +* Patches by Travis Sawyer, 12 Mar 2004: + - Fix Gigabit Ethernet support for 440GX + - Add Gigabit Ethernet Support to MII PHY utilities - Idea from Andrew Klossner +* Patch by Brad Kemp, 12 Mar 2004: + Fixes for drivers/cfi_flash.c: + - Better support for x8/x16 implementations + - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE + - Added defines for AMD command and address constants - Signed-off-by: Andy Fleming +* Patch by Leon Kukovec, 12 Mar 2004: + Fix get_dentfromdir() to correctly handle deleted dentries -commit 81f481ca708ed6a56bf9c410e3191dbad581c565 -Author: Andy Fleming -Date: Mon Apr 23 02:24:28 2007 -0500 +* Patch by George G. Davis, 11 Mar 2004: + Remove hard coded network settings in TI OMAP1610 H2 + default board config - Enable 8544 support +* Patch by George G. Davis, 11 Mar 2004: + add support for ADS GraphicsClient+ board. - * Add support to the Makefile - * Add 8544 configuration support to the tsec driver - * Add 8544 SVR numbers to processor.h +* Patch by Pierre Aubert, 11 Mar 2004: + - add bitmap command and splash screen support in cfb console + - add [optional] origin in the bitmap display command - Signed-off-by: Ed Swarthout - Signed-off-by: Jon Loeliger +* Patch by Travis Sawyer, 11 Mar 2004: + Fix ocotea board early init interrupt setup. -commit 0d8c3a2096eaff8d7de89d45e9af4d4b0d4868fe -Author: Andy Fleming -Date: Fri Feb 23 17:12:25 2007 -0600 +* Patch by Thomas Viehweger, 11 Mar 2004: + Remove redundand code; add PCI-specific bits to include/mpc8260.h - Support 1G size on 8548 +* Patch by Stephan Linz, 09 Mar 2004 + - Add support for the SSV ADNP/ESC1 (Nios Softcore) - e500v2 and newer cores support 1G page sizes. +* Patch by George G. Davis, 9 Mar 2004: + fix recent build failure for SA1100 target - Signed-off-by: Ed Swarthout - Signed-off-by: Andy Fleming +* Patch by Travis Sawyer, 09 Mar 2004: + Support native interrupt mode for the IBM440GX. + Previously it was running in 440GP compatibility mode. -commit 45cef612cc601d2d1c890fbbd7cdc9609a189a46 -Author: Andy Fleming -Date: Fri Feb 23 17:11:16 2007 -0600 +* Patch by Philippe Robin, 09 Mar 2004: + Added ARM Integrator AP, CP and Versatile PB926EJ-S Reference + Platform support. - Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nG +* Patch by Masami Komiya, 08 Mar 2004: + Don't overwrite server IP address or boot file name + when the boot server does not return values - The other pagesz constants use one letter to specify order of - magnitude. Also change the one reference to it in mpc8548cds/init.S +* Patch by Tolunay Orkun, 5 Mar 2004: + Removed compile time restriction on CFG_I2C_SPEED for DS1338 RTC - Signed-off-by: Andy Fleming +* Patch by Tolunay Orkun, 5 Mar 2004: + Fix early board initialization for Cogent CSB272 board -commit 1f9a318cea14272edd10d63739e2d326c90f430e -Author: Andy Fleming -Date: Fri Feb 23 16:28:46 2007 -0600 +* Patch by Ed Okerson, 3 Mar 2004: + fix CFI flash writes for little endian systems - Only set ddrioovcr for 8548 rev1. +* Patch by Reinhard Meyer, 01 Mar 2004: + generalize USB and IDE support for MPC5200 with according + changes to IceCube.h and TOP5200.h + add Am29LV256 256 MBit FLASH support for TOP5200 boards + add info about USB and IDE to README - Signed-off-by: Ed Swarthout - Signed-off-by: Andy Fleming +* Patch by Yuli Barcohen, 4 Mar 2004: + Fix problems with GCC 3.3.x which changed handling of global + variables explicitly initialized to zero (now in .bss instead of + .data as before). -commit 9343dbf85bc03033f2102d8e8543567c2c1ad2d2 -Author: Andy Fleming -Date: Sat Feb 24 01:16:45 2007 -0600 +* Patch by Leon Kukovec, 02 Mar 2004: + add strswab() to fix IDE LBA capacity, firmware and model numbers + on little endian machines - Tweak DDR ECC error counter +* Patch by Masami Komiya, 02 Mar 2004: + - Remove get_ticks() from NFS code + - Add verification of RPC transaction ID - Enable single-bit error counter when memory was cleared by ddr controller. +* Patch by Pierre Aubert, 02 Mar 2004: + cleanup for IDE and USB drivers for MPC5200 - Signed-off-by: Ed Swarthout - Signed-off-by: Andy Fleming +* Patch by Travis Sawyer, 01 Mar 2004: + Ocotea: + - Add IBM PPC440GX Ref Platform support (Ocotea) + Original code by Paul Reynolds + Adapted to U-Boot and 440GX port + 440gx_enet.c: + - Add gracious handling of all Ethernet Pin Selections for 440GX + - Add RGMII selection for Cicada CIS8201 Gigabit PHY + ppc440.h: + - Add needed bit definitions + - Fix formatting -commit 85e7c7a45e3dd9c7ce3e722352ba60f8df1a7a4b -Author: Timur Tabi -Date: Mon Feb 12 13:34:55 2007 -0600 +* Patch by Carl Riechers, 1 Mar 2004: + Add PPC440GX prbdv0 divider to fix memory clock calculation. - 85xx: write MAC address to mac-address and local-mac-address +* Patch by Stephan Linz, 27 Feb 2004 + - avoid problems for targets without NFS download support - Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() - should write the MAC address to mac-address and local-mac-address, if they - exist. +* Patch by Rune Torgersen, 27 Feb 2004: + - Added LBA48 support (CONFIG_LBA48 & CFG_64BIT_LBA) + - Added support for 64bit printing in vsprintf (CFG_64BIT_VSPRINTF) + - Added support for 64bit strtoul (CFG_64BIT_STRTOUL) - Signed-off-by: Timur Tabi +* Patch by Masami Komiya, 27 Feb 2004: + Fix rarpboot: add autoload by NFS -commit 03b81b48eec0ad249ec97a4ae16c36fa2e014ff4 -Author: Andy Fleming -Date: Mon Apr 23 01:44:44 2007 -0500 +* Patch by Dan Eisenhut, 26 Feb 2004: + fix flash_write return value in saveenv - Some 85xx cpu cleanups +* Patch by Stephan Linz, 11 Dec 2003 + expand config.mk to avoid trigraph warnings on NIOS - * Cleaned up the TSR[WIS] clearing - * Cleaned up DMA initialization +* Rename "BMS2003" board into "HMI10" - Signed-off-by: Ed Swarthout - Signed-off-by: Jon Loeliger - Acked-by: Andy Fleming +* SX1 patches: use "serial#" for USB serial #; use redundand environment + storage; auto-set console on USB port (using preboot command) -commit 151d5d992eab8c497b24c816c73dc1ad8bffb4eb -Author: Andy Fleming -Date: Mon Apr 23 01:32:22 2007 -0500 +* Add support for SX1 mobile phone; add support for USB-based console + (enable with "setenv stdout usbtty; setenv stdin usbtty") - Add cpu support for the 8544 +* Fix LOWBOOT configuration for MPC5200 with DDR memory - Recognize new SVR values, and add a few register definitions +* Fix SDRAM timings for LITE5200 / IceCube board - Signed-off-by: Ed Swarthout - Signed-off-by: Jon Loeliger - Acked-by: Andy Fleming +* Handle Auti-MDIX / connection status for INCA-IP -commit 25d83d7f4ac65727182d8ddaf7ba42fa74cf65ae -Author: Jon Loeliger -Date: Wed Apr 11 16:51:02 2007 -0500 +* Fix USB problems when attempting to read 0 bytes - Add MPC8544DS basic port board files. +* Patch by Travis Sawyer, 26 Feb 2004: + Fix broken compile for XPEDITE1K target. - Add board port under new board/freescale directory - structure and reuse existing PIXIS FPGA support there. +* Patch by Stephan Linz, 26 Feb 2004: + Bug fix for NFS code on NIOS targets - Signed-off-by: Ed Swarthout - Signed-off-by: Jon Loeliger +* Patch by Stephen Williams, 26 Feb 2004: + Break up SystemACE reads of large block counts -commit 0cde4b00fc7393b89f379d83a9d436dcb1334bfa -Author: Jon Loeliger -Date: Wed Apr 11 16:50:57 2007 -0500 +* Patch by Pierre Aubert, 26 Feb 2004 + add IDE support for MPC5200 - Add MPC8544DS main configuration file. +* Patch by Masami Komiya, 26 Feb 2004: + add autoload via NFS - Signed-off-by: Ed Swarthout - Signed-off-by: Jon Loeliger +* Patch by Stephen Williams + Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses + elsewhere in the source. -commit 362dd83077ac04c0296bca3e824ec2fb3d44d9d6 -Author: Sergei Shtylyov -Date: Wed Dec 27 22:07:15 2006 +0300 +* Patch by Steven Scholz, 25 Feb 2004: + - Timeouts in FPGA code should be based on CFG_HZ + - Minor cleanup in code for Altera FPGA ACEX1K - Fix PCI I/O space mapping on Freescale MPC85x0ADS +* Patch by Steven Scholz, 25 Feb 2004: + Changed "Directory Hierarchy" section in README - The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit - 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's - describing the local address window used for the PCI I/O space accesses -- fix - this and carry over the necessary changes into the MPC8560ADS code since the - PCI I/O space mapping was also broken for this board (by the earlier commit - 087454609e47295443af793a282cddcd91a5f49c). Add the comments clarifying how - the PCI I/O space must be mapped to all the MPC85xx board config. headers. +* Patch by Masami Komiya, 25 Feb 2004: + Reduce copy count in nfs_read_reply() of NFS code - Signed-off-by: Sergei Shtylyov +* Patch by Markus Pietrek, 24 Feb 2004: + NS9750 DevBoard added - board/mpc8540ads/init.S | 4 ++-- - board/mpc8560ads/init.S | 4 ++-- - include/configs/MPC8540ADS.h | 5 ++--- - include/configs/MPC8541CDS.h | 2 +- - include/configs/MPC8548CDS.h | 2 +- - include/configs/MPC8560ADS.h | 8 ++++---- - 6 files changed, 12 insertions(+), 13 deletions(-) +* Patch by Pierre Aubert, 24 Feb 2004 + add USB support for MPC5200 -commit 96629cbabdb727d4a5e62542deefc01d498db6dc -Author: Zang Roy-r61911 -Date: Tue Dec 5 16:42:30 2006 +0800 +* Patch by Steven Scholz, 24 Feb 2004: + - fix MII commands to use values from last command - u-boot: Fix e500 v2 core reset bug +* Patch by Torsten Demke, 24 Feb 2004: + Add support for the eXalion platform (SPSW-8240, F-30, F-300) - The following patch fixes the e500 v2 core reset bug. - For e500 v2 core, a new reset control register is added to reset the - processor. +* Patch by Rahul Shanbhag, 19 Feb 2004: + Fixes for for OMAP1610 board: + - shift some IRQ specific code to platform.S file + - remove duplicatewatchdog reset code from start.S - Signed-off-by: Roy Zang +* Make Auto-MDIX Support configurable on INCA-IP board -commit 63247a5acd58032e6cf33f525bc3923b467bac88 -Author: Zang Roy-r61911 -Date: Wed Dec 20 11:01:00 2006 +0800 +* Fix license for mkimage tool - u-boot: v2: Remove the fixed TLB and LAW entrynubmer +* Patch by Masami Komiya, 24 Feb 2004: + Update NetBootFileXferSize in NFS code - Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW - entry number to control the loop. This can reduce the potential risk - for the 85xx processor increasing its TLB adn LAW entry number. +* Patch by Scott McNutt, 24 Feb 2004: + fix packet length in NFS code - Signed-off-by: Swarthout Edward - Signed-off-by: Roy Zang +* Patch by Masami Komiy, 22 Feb 2004: + Add support for NFS for file download -commit 0b1934ba12fd408fcc3b8bd9f4b04864c42a42bf -Author: Zang Roy-r61911 -Date: Mon Dec 18 17:01:04 2006 +0800 +* Patch by Andrea Scian, 17 Feb 2004: + Add support for S3C44B0 processor and DAVE B2 board - u-boot: Fix the 85xxcds tsec bug +* Patch by Steven Scholz, 20 Feb 2004: + - Add support for MII commands on AT91RM9200 boards + - some cleanup in AT91RM9200 ethernet code - Fix the 85xxcds tsec bug. - When enable PCI, tsec.o should be added to u-boot.lds to make tsec work. +* Patch by Peter Ryser, 20 Feb 2004: + Add support for the Xilinx ML300 platform - Signed-off-by: Roy Zang +* Patch by Stephan Linz, 17 Feb 2004: + Fix watchdog support for NIOS -commit 7337b237ffc4aaf1b9467024fe472a880d852598 -Author: Zang Roy-r61911 -Date: Fri Dec 15 14:43:31 2006 +0800 +* Patch by Josh Fryman, 16 Feb 2004: + Fix byte-swapping for cfi_flash.c for different bus widths - u-boot: Fix CPU2 errata on MPC8548CDS board +* Patch by Jon Diekema, 14 Jeb 2004: + Remove duplicate "FPGA Support" notes from the README file - This patch apply workaround of CPU2 errata on MPC8548CDS board. +* Patches by Reinhard Meyer, 14 Feb 2004: + - update board/emk tree; use common flash driver + - Corrected tested bits in machine check exception in cpu/mpc5xxx/traps.c + [adapted for other PPC CPUs -- wd] + - Added support for the M48T08 on the EVAL5200 board in rtc/mk48t59.c - Signed-off-by:Ebony Zhu +* Patch by Jon Diekema, 13 Feb 2004: + Call show_boot_progress() whenever POST "FAILED" is printed. -commit 39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09 -Author: ebony.zhu@freescale.com -Date: Mon Dec 18 16:25:15 2006 +0800 +* Patch by Nishant Kamat, 13 Feb 2004: + Add support for TI OMAP1610 H2 Board + Fixes for cpu/arm926ejs/interrupt.c + (based on Richard Woodruff's patch for arm925, 16 Oct 03) + Fix for a timer bug in OMAP1610 Innovator + Add support for CS0 (ROM)/CS3 (Flash) boot in OMAP1610 Innovator and H2 - u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default +* Patches by Stephan Linz, 12 Feb 2004: + - add support for NIOS timer with variable period preload counter value + - prepare POST framework support for NIOS targets - This patch disables MPC8548CDS 2T_TIMING for DDR by default. +* Patch by Denis Peter, 11 Feb 2004: + add POST support for the MIP405 board - Signed-off-by:Ebony Zhu +* Patch by Laurent Mohin, 10 Feb 2004: + Fix buffer overflow in common/usb.c -commit 41fb7e0f1ec9b91bdae2565bab5f2e3ee15039c7 -Author: Zang Roy-r61911 -Date: Thu Dec 14 14:14:55 2006 +0800 +* Patch by Tolunay Orkun, 10 Feb 2004: + Add support for Cogent CSB272 board - u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board +* Patch by Thomas Elste, 10 Feb 2004: + Add support for NET+50 CPU and ModNET50 board - Enable PCI function and add PEX & rapidio memory map on MPC8548CDS - board. - Signed-off-by: Roy Zang +* Patch by Sam Song, 10 Feb 2004: + Fix typos in cfi_flash.c -commit 96b8a05432f346f36493535c85320b70ec9c7c1b -Author: Scott Wood -Date: Mon Apr 16 14:54:15 2007 -0500 +* Patch by Leon Kukovec, 10 Feb 2004 + Fixed long dir entry slot id calculation in get_vfatname - mpc83xx: Add MPC8313ERDB support. +* Patch by Robin Gilks, 10 Feb 2004: + add "itest" command (operators: -eq, -ne, -lt, -gt, -le, -ge, ==, + !=, <>, <, >, <=, >=) - Signed-off-by: Scott Wood +* Fix problem with side effects in macros in include/usb.h -commit 49ea3b6eafe606285ae4d5c378026153dde53200 -Author: Scott Wood -Date: Mon Apr 16 14:34:21 2007 -0500 +* Patch by David Benson, 13 Nov 2003: + bug 841358 - fix TFTP download size limit - mpc83xx: Add generic PCI setup code. +* Fixing bug 850768: + improper flush_cache() in load_serial() - Board code can now request the generic setup code rather than having to - copy-and-paste it for themselves. Boards should be converted to use this - once they're tested with it. +* Fixing bug 834943: + MPC8540 - missing volatile declarations - Signed-off-by: Scott Wood +* Patch by Stephen Williams, 09 Feb 2004: + Add support for Xilinx SystemACE chip: + - New files common/cmd_ace.c and include/systemace.h + - Hook systemace support into cmd_fat and the partition manager -commit 7c98e5193e93df6b9b651851d54b638a61ebb0ea -Author: Scott Wood -Date: Mon Apr 16 14:34:19 2007 -0500 +* Patch by Travis Sawyer, 09 Feb 2004: + Add bi_opbfreq & bi_iic_fast to 440GX bd_info as needed for Linux - mpc83xx: Add 831x support to speed.c. +* Patch by Travis Sawyer, 09 Feb 2004: + o 440GX: + - Fix PCI Indirect access for type 1 config cycles with ppc440. + - Add phymode for 440 enet + - fix pci pre init + o XPedite1K: + - Change board_pre_init to board_early_init_f + - Add user flash to bus controller setup + - Fix pci pre init + - Fix is_pci_host to check GPIO for monarch bit + - Force xpedite1k to pci conventional mode (via #define option) - Signed-off-by: Scott Wood +* Patch by Brad Kemp, 4 Feb 2004: + - handle the machine check that is generated during the PCI scans + on 82xx processors. + - define the registers used in the IMMR by the PCI subsystem. -commit 0f253283a32d91e06844d7f87f9b33f4f4fbce8f -Author: Scott Wood -Date: Mon Apr 16 14:34:18 2007 -0500 +* Patch by Pierre Aubert, 03 Feb 2004: + cpu/mpc5xxx/start.S: copy MBAR into SPR311 - mpc83xx: Add 831x support to global_data.h +* Patch by Jeff Angielski, 03 Feb 2004: + Fix copy & paste error in cpu/mpc8260/pci.c - Signed-off-by: Scott Wood +* Patch by Reinhard Meyer, 24 Jan 2004: + Fix typo in cpu/mpc5xxx/pci_mpc5200.c -commit 95e7ef897e54591e615fc1b458b74c286fe1fb06 -Author: Scott Wood -Date: Mon Apr 16 14:34:16 2007 -0500 +* Add Auto-MDIX support for INCA-IP - mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu(). +* Some code cleanup - Rather than misleadingly define PVR_83xx as the specific type of 83xx - being built for, the PVR of each core revision is defined. checkcpu() now - prints the core that it detects, rather than aborting if it doesn't find - what it thinks it wants. +* Patch by Josef Baumgartner, 10 Feb 2004: + Fixes for ColdFire port - Signed-off-by: Scott Wood +* Patch by Brad Kemp, 11 Feb 2004: + Fix CFI flash driver problems -commit a35b0c4950d84cf9e3a9e32b916135956d1ac636 -Author: Scott Wood -Date: Mon Apr 16 14:34:15 2007 -0500 +* Make sure to use a bus clock divider of 2 only when running TQM8xxM + modules at CPU clock frequencies above 66 MHz. - mpc83xx: Recognize SPR values for MPC8311 and MPC8313. +* Optimize flash programming speed for LWMON (by another 100% :-) - Signed-off-by: Scott Wood +* Patch by Jian Zhang, 3 Feb 2004: + - Changed the incorrect FAT12BUFSIZE + - data_begin in fsdata can be negative. Changed it to be short. -commit d87c57b201b4572d16f1b642998faa00c9912b16 -Author: Scott Wood -Date: Mon Apr 16 14:31:55 2007 -0500 +* Patches by Stephan Linz, 30 Jan 2004: + 1: - board/altera/common/flash.c:flash_erase(): + o allow interrupts befor get_timer() call + o check-up each erased sector and avoid unexpected timeouts + - board/altera/dk1c20/dk1s10.c:board_early_init_f(): + o enclose sevenseg_set() in cpp condition + - remove the ASMI configuration for DK1S10_standard_32 (never present) + - fix some typed in mistakes in the NIOS documentation + 2: - split DK1C20 configuration into several header files: + o two new files for each NIOS CPU description + o U-Boot related part is remaining in DK1C20.h + 3: - split DK1S10 configuration into several header files: + o two new files for each NIOS CPU description + o U-Boot related part is remaining in DK1S10.h + 4: - Add support for the Microtronix Linux Development Kit + NIOS CPU configuration at the Altera Nios Development Kit, + Stratix Edition (DK-1S10) + 5: - Add documentation for the Altera Nios Development Kit, + Stratix Edition (DK-1S10) + 6: - Add support for the Nios Serial Peripharel Interface (SPI) + (master only) + 7: - Add support for the common U-Boot SPI framework at + RTC driver DS1306 - mpc83xx: Add register definitions for MPC831x. +* Patch by Rahul Shanbhag, 28 Jan 2004: + Fix flash protection/locking handling for OMAP1610 innovator board. - Signed-off-by: Scott Wood +* Patch by Rolf Peukert, 28 Jan 2004: + fix flash write problems on CSB226 board (write with 32 bit bus width) -commit 7fc4c71a143be8666d70803fb25ae60379c95622 -Author: Stefan Roese -Date: Mon Apr 23 15:39:59 2007 +0200 +* Patches by Mark Jonas, 16 Jan 2004: + - fix rounding error when calculating baudrates for MPC5200 PSCs + - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same + time which is not supported - Fix file mode +* Patch by Yuli Barcohen, 26 Jan 2004: + Allow bzip2 compression for small memory footprint boards - Signed-off-by: Stefan Roese +* Patch by Brad Kemp, 21 Jan 2004: + Add support for CFI flash driver for both the Intel and the AMD + command sets. -commit 38257988abfe74d459ca2ad748b109ca04e4efe1 -Author: Sergei Shtylyov -Date: Mon Apr 23 15:30:39 2007 +0200 +* Patch by Travis Sawyer, 20 Jan 2004: + Fix pci bridge auto enumeration of sibling p2p bridges. - [PATCH] Avoid assigning PCI resources from zero address +* Patch by Tolunay Orkun, 12 Jan 2004: + Add some delays as needed for Intel LXT971A PHY support - If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE - core complains and IDE drivers fails to work. Also, assigning zero to a BAR - was illegal according to PCI 2.1 (the later revisions seem to have excluded the - sentence about "0" being considered an invalid address) -- so, use a reasonable - starting value of 0x1000 (that's what the most Linux archs are using). +* Patches by Stephan Linz, 09 Jan 2004: + - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c + - make DK1C20 board configuration related to ASMI conform to + documentation - Alternatively, one might have fixed the calls to pci_set_region() individually - (some code even seems to have taken care of this issue) but that would have - been a lot more work. :-) +* Patch by Anders Larsen, 09 Jan 2004: - Signed-off-by: Sergei Shtylyov - Acked-by: Stefan Roese + ARM memory layout fixes: the abort-stack is now set up in the + correct RAM area, and the BSS is zeroed out as it should be. -commit afb903a2eb9436baa9270ccc0c27082d86497d89 -Author: Jeffrey Mann -Date: Mon Apr 23 14:00:11 2007 +0200 + Furthermore, the magic variables 'armboot_end' and 'armboot_end_data' + of the linker scripts are replaced by '__bss_start' and '_end', + resp., which is a further step to eliminate unnecessary differences + between the implementation of the CPU architectures. - [patch] setenv(...) can delete environmentalvariables +* Patch by liang a lei, 9 Jan 2004: + Fix Intel 28F128J3 ID in include/flash.h - update setenv() function so that entering a NULL value for the - variable's value will delete the environmental variable +* Patch by Masami Komiya, 09 Jan 2004: + add support for TB0229 board (NEC VR4131 MIPS processor) - Signed-off-by: Jeffrey Mann - Acked-by: Stefan Roese +* Patch by Leon Kukovec, 12 Dec 2003: + changed extern __inline__ into static __inline__ in + include/linux/byteorder/swab.h -commit 36f104e5caa747d568eff26b369565af57c2ffa6 -Author: Mike Frysinger -Date: Mon Apr 23 13:54:24 2007 +0200 +* Patch by Travis Sawyer, 30 Dec 2003: + Add support for IBM PPC440GX. Multiple EMAC Ethernet devices, + select MDI port based on enabled EMAC device. + Add support for XES Inc XPedite1000 440GX + base PrPMC board. - [patch] use unsigned char in smc91111 driver for mac +* Patch by Wolter Kamphuis, 15 Dec 2003: + made CONFIG_SILENT_CONSOLE usable on all architectures - the v_mac variable in the smc91111 driver is declared as a signed char ... - this causes problems when one of the bytes in the MAC is "signed" like 0xE0 - because when it gets printed out, you get a display like: - 0xFFFFFFE0 and that's no good +* Disable date command on TQM866M - there is no RTC on MPC866 - Signed-off-by: Mike Frysinger +* Fix variable CPU clock for MPC859/866 systems for low CPU clocks -commit d98c0885ad617fccf21e7c26ef8cb728fbfb2459 -Author: Rodolfo Giometti -Date: Mon Apr 23 13:10:52 2007 +0200 +* Implement adaptive SDRAM timing configuration based on actual CPU + clock frequency for INCA-IP; fix problem with board hanging when + switching from 150MHz to 100MHz - USB: (Another) delay for crappy USB keys. +* Add PCMCIA CS support for BMS2003 board - Some USB keys are slow in giving back an answer when the Root HUB - enables power lines. +* Add variable CPU clock for MPC859/866 systems (so far only TQM866M): + see doc/README.MPC866 for details; + implement workaround for "SIU4" and "SIU9" silicon bugs on MPC866; + calculate CPU clock frequency from PLL register values. - Signed-off-by: Rodolfo Giometti +* Add support for 128 MB RAM on TQM8xxL/M modules -commit 323bfa8f436dc3bc57187c9b1488bc3146ff1522 -Author: Stefan Roese -Date: Mon Apr 23 12:00:22 2007 +0200 +* Fix PS/2 keyboard problem caused by statically initialized variable + pointing to a location in flash - Remove BOARDLIBS usage completely +* Fix INCA-IP clock calculation: 400/3 = 133.3 MHz, not 130. - Signed-off-by: Stefan Roese +* The PS/2 mux on the BMS2003 board needs 450 ms after power on + before we can access it; add delay in case we are faster (with no + CF card inserted) -commit 32556443840f127170e4baa8bdd5b567039f6c36 -Author: Michal Simek -Date: Sat Apr 21 21:07:22 2007 +0200 +* Cleanup of some init functions - [PATCH] SystemACE support for Microblaze +* Make sure SCC Ethernet is always stopped by the time we boot Linux + to avoid Linux crashes by early packets coming in. -commit 0643631aa1036cd746bf5d15f5a34bc7bc01ea4f -Author: Michal Simek -Date: Sat Apr 21 21:02:40 2007 +0200 +* Accelerate flash accesses on LWMON board by using buffered writes - 16bit read/write little endian +* Fix typo in Makefile; + fix problem with PARTNUM detection -commit 9d1d6a34d26c5933bc097ce73c9348f95573cdd4 -Author: Michal Simek -Date: Sat Apr 21 20:53:31 2007 +0200 +* Patch by Reinhard Meyer, 09 Jan 2004: + - add RTC support for MPC5200 based boards (requires RTC_XTAL) - Change ML401 parameters - Xilinx BSP +* Add support for IDE LED on BMS2003 board + (exclusive with status LED!) -commit 2e343b9a57f32e1bd08c35c9976910333fb4e13d -Author: Ed Swarthout -Date: Wed Feb 28 05:37:29 2007 -0600 +* Add support for PS/2 keyboard (used with PS/2 multiplexor on + BMS2003 board) - mpc8641hpcn: Fix LAW and TLB setup to use the IO_PHYS #defines. +* Patches by Reinhard Meyer, 4 Jan 2004 + 7 Jan 2004: + Add common files for "emk" boards - Signed-off-by: Ed Swarthout +* Add a common get_ram_size() function and modify the the + board-specific files to invoke that common implementation. -commit 79cb47391eebef85acadb3f6961ef6c55cace6ac -Author: Zhang Wei -Date: Fri Jan 19 10:42:37 2007 +0800 +====================================================================== +Changes for U-Boot 1.0.1: +====================================================================== - Enable LAWs for MPC8641 PCI-Ex2. +* Set default clock for INCA-IP to 150 MHz - Signed-off-by: Zhang Wei - Signed-off-by: Jon Loeliger +* Make BMS2003 use a separate config file to avoid #ifdef mess; + add I2C support; add support for DS1337 RTC -commit bd7851ce1e1f140665b520026abf1042968b1102 -Author: Jon Loeliger -Date: Fri Apr 20 14:12:26 2007 -0500 +* Add CompactFlash support for BMS2003 board - mpc86xx; Write MAC address to mac-address and local-mac-address +* Add support for status LED on BMS2003 board - Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() - should write the MAC address to mac-address and local-mac-address, if they - exist. +* Patch by Scott McNutt, 02 Jan 2004: + Add support for the Nios Active Serial Memory Interface (ASMI) + on Cyclone devices - Signed-off-by: Timur Tabi - Signed-off-by: Jon Loeliger +* Patch by Andrea Marson, 16 Dec 2003: + Add support for the PPChameleon ME and HI modules -commit 7dbdf28b8bd855a8530dc3292e4982575a197060 -Author: Jon Loeliger -Date: Fri Apr 20 14:11:38 2007 -0500 +* Patch by Yuli Barcohen, 22 Dec 2003: + Add support for Motorola DUET ADS board (MPC87x/88x) - mpc86xx: protect memcpy to bad address if a mac-address is missing from dt +* Patch by Robert Schwebel, 15 Dec 2003: + add support for cramfs (uses JFFS2 command interface) - Signed-off-by: Kim Phillips - Signed-off-by: Jon Loeliger +* Patches by Stephan Linz, 11 Dec 2003: + - more documentation for NIOS port + - new struct nios_pio_t, struct nios_spi_t + - Reconfiguration for NIOS Development Kit DK1C20: + o move board related code from board/dk1c20 + to board/altera/dk1c20 + o create a new common source path board/altera/common + and move generic flash access stuff into it + o change/expand configuration file DK1C20.h + - Add support for NIOS Development Kit DK1S10 + - Add status LED support for NIOS systems + - Add dual 7-segment LED support for Altera NIOS DevKits -commit 14da5f7675bbb427c469e3f45006e027b6e21db9 -Author: Wolfgang Denk -Date: Fri Apr 20 17:43:28 2007 +0200 +* Patch by Ronen Shitrit, 10 Dec 2003: + Add support for the Marvell DB64360 / DB64460 development boards - Cleanup compiler warnings, update CHANGELOG +* Patch by Detlev Zundel, 10 Dec 2003: + fix dependency problem in examples/Makefile - Signed-off-by: Wolfgang Denk +* Patch by Denis Peter, 8 Dec 2003 + - add support for the PATI board (MPC555) + - add SPI support for the MPC5xx -commit 6923565db12af34fd5e02d354ee65a8c78ac460f -Author: Detlev Zundel -Date: Fri Apr 20 12:01:47 2007 +0200 +* Patch by Anders Larsen, 08 Dec 2003: + add configuration options CONFIG_SERIAL_TAG and CONFIG_REVISION_TAG + to pass ATAG_SERIAL and ATAG_REVISION, resp., to the ARM target; + cleanup some redundand #defines - Fix breakage of NC650 board with respect to nand support. +* Patch by André Schwarz, 8 Dec 2003: + fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM): + - TX and RX deskriptors must be quad-word aligned + - does not work with only one TX deskriptor + - standard reset method does not work - Signed-off-by: Detlev Zundel +* Patch by Masami Komiya, 08 Dec 2003: + add RTL8139 ethernet driver -commit 39f23cd90947639ac278a18ff277ec786b5ac167 -Author: Domen Puncer -Date: Fri Apr 20 11:13:16 2007 +0200 +* Patches by Ed Okerson, 07 Dec 2003: + - fix ethernet for the AU1x00 processors in little-endian mode. + - extend memsetup.S for the AU1x00 processors in BE and LE modes - [RFC PATCH] icecube/lite5200b: fix OF_TBCLK (timebase-frequency) calculation +* Minor code cleanup (coding style) - G2 core reference manual says decrementer and time base - are decreasing/increasing once every 4 bus clock cycles. - Lets fix it, so time in Linux won't run twice as fast +* Patch by Reinhard Meyer, 30 Dec 2003: + - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE, + - added CONFIG_PHY_ADDR to include/configs/IceCube.h, + - turned debug print of PHY registers into a function (called in two places) + - added support for EMK MPC5200 based modules - Signed-off-by: Domen Puncer - Acked-by: Grant Likely +* Fix MPC8xx PLPRCR_MFD_SHIFT typo -commit 7651f8bdbba03bb0b4f241e2d2c4cb65b230bd56 -Author: Gerald Van Baren -Date: Thu Apr 19 23:14:39 2007 -0400 +* Add support for TQM866M modules - Fix serious pointer bug with bootm and reserve map. +* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash) - What was suppose to be a stack variable was declared as a pointer, - overwriting random memory. - Also moved the libfdt.a requirement into the main Makefile. That is - The U-Boot Way. +* Fix a few compiler warnings -commit d21686263574e95cb3e9e9b0496f968b1b897fdb -Author: Stefan Roese -Date: Thu Apr 19 09:53:52 2007 +0200 +* Patch by Reinhard Meyer, 28 Dec 2003: + Add initial support for TOP5200 board + +* Make CPU clock on ICA-IP board controllable by a "cpuclk" + environment variable which can set to "100", "133", or "150". The + CPU clock will be configured accordingly upon next reboot. Other + values are ignored. In case of an invalid or undefined "cpuclk" + value, the compile-time default CPU clock speed will be used. + +* Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory + window that is used to access the UART registers by the Linux driver) + +* Patch by Reinhard Meyer, 20 Dec 2003: + Fix clock calculation for the MPC5200 for higher clock frequencies + (above 2**32 / 10 = 429.5 MHz). + +* Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration + +* Fix IceCube CLKIN configuration (it's 33.000000MHz) + +* Add new configuration for IceCube board with DDR memory + +* Update TRAB memory configurations + +* Add JFFS2 support for INCA-IP board + +* Patch by Bill Hargen, 09 Dec 2003: + - BUBINGA405EP: changed flash driver to protect top sector containing + first instruction. + - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM. + - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access). + - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1). + - 405EP: added/fixed support for "reginfo" command. + - 4xx: removed spurious MII error messages on "mii info" command. + +* Patch by Bernhard Kuhn, 28 Nov 2003: + add support for ColdFire CPU + add support for Motorola M5272C3 and M5282EVB boards + +* Patch by Pierre Aubert, 24 Nov 2003: + - add a return value for the fpga command + - add ide_preinit() function called in ide_init if CONFIG_IDE_PREINIT + is defined. If ide_preinit fails, ide_init is aborted. + - fix an endianess problem in fat.h + +* Patch by Wolter Kamphuis, 05 Dec 2003: + Add support for SNMC's QS850/QS823/QS860T boards + +* Patch by Yuli Barcohen, 3 Dec 2003: + "revive" U-Boot support for old Motorola MPC860ADS board + +* Patch by Cam(ilo?), 03 Dec 2003: + make examples build even with broken Montavista objcopy - ppc4xx: Fix chip select timing for SysACE access on AMCC Katmai +* Patch by Pavel Bartusek, 27 Nov 2003: + fix conversion problem with "bootretry" evironment variable - Previous versions used full wait states for the chip select #1 which - is connected to the Xilinix SystemACE controller on the AMCC Katmai - evaluation board. This leads to really slow access and therefore low - performance. This patch now sets up the chip select a lot faster - resulting in much better read/write performance of the Linux driver. +* Patch by Andre Schwarz, 24 Nov 2003: + add support for mvblue (mvBlueLYNX and mvBlueBOX) boards - Signed-off-by: Stefan Roese +* Patch by Pavel Bartusek, 21 Nov 2003: + set ZMII bridge speed on 440 -commit 37837828d89084879bee2f2b8c7c68d4695940df -Author: Wolfgang Denk -Date: Wed Apr 18 17:49:29 2007 +0200 +* Patch by Anders Larsen, 17 Nov 2003: + Fix mismatched #ifdef / #endif in include/asm-arm/arch-pxa/hardware.h - Clenaup, update CHANGELOG +* Patches by David Müller, 14 Nov 2003: + - board/mpl/common/common_util.c + * implement support for BZIP2 compressed images + * various cleanups (printf -> puts, ...) + - board/mpl/common/flash.c + * report correct errors to upper layers + * check the erase fail and VPP low bits in status reg + - board/mpl/vcma9/cmd_vcma9.c + - board/mpl/vcma9/flash.c + * various cleanups (printf -> puts, ...) + - common/cmd_usb.c + * fix typo in comment + - cpu/arm920t/usb_ohci.c + * support for S3C2410 is missing in #if line + - drivers/cs8900.c + * reinit some registers in case of error (cable missing, ...) + - fs/fat/fat.c + * support for USB/MMC devices is missing in #if line + - include/configs/MIP405.h + - include/configs/PIP405.h + * enable BZIP2 support + * enlarge malloc space to 1MiB because of BZIP2 support + - include/configs/VCMA9.h + * enable BZIP2 support + * enlarge malloc space to 1MiB because of BZIP2 support + * enable USB support + - lib_arm/armlinux.c + * change calling convention of ARM Linux kernel as + described on http://www.arm.linux.org.uk/developer/booting.php - Signed-off-by: Wolfgang Denk +* Patch by Thomas Lange, 14 Nov 2003: + Split dbau1x00 into dbau1000, dbau1100 and dbau1500 configs to + support all these AMD boards. -commit fd094c6379e2ef8a4d0ceb5640b24cb0c8d04449 -Author: Wolfgang Denk -Date: Wed Apr 18 17:20:58 2007 +0200 +* Patch by Thomas Lange, 14 Nov 2003: + Workaround for mips au1x00 physical memory accesses (the au1x00 + uses a 36 bit bus internally and cannot access physical memory + directly. Use the uncached SDRAM address instead of the physical + one.) - Update CHANGELOG +* Patch by Xue Ligong (Joe), 13 Nov 2003: + add Realtek 8019 ethernet driver - Signed-off-by: Wolfgang Denk +* Patch by Yuli Barcohen, 13 Nov 2003: + MPC826xADS/PQ2FADS cleanup -commit 2a26ec4732efd7a308d0bbc97714c1d75ef1173b -Author: Wolfgang Denk -Date: Wed Apr 18 17:07:26 2007 +0200 +* Patch by Anders Larsen, 12 Nov 2003: + Update README to mark the PORTIO commands non-standard - Cleanup, update CHANGELOG +* Patch by Nicolas Lacressonnière, 12 Nov 2003: + update for for Atmel AT91RM9200DK development kit: + - support for environment variables in DataFlash + - Atmel DataFlash AT45DB1282 support - Sigend-off-by: Wolfgang Denk +* Patch by Jeff Carr, 11 Nov 2003: + add support for new version of 8270 processors -commit 5f6c732affea9647762d27a4617a2ae64c52dceb -Author: Wolfgang Denk -Date: Wed Apr 18 16:17:46 2007 +0200 +* Patches by George G. Davis, 05 Nov 2003: + - only pass the ARM linux initrd tag to the kernel when an initrd + is actually present + - update omap1510inn configuration file - Update CHANGELOG +* Patches by Stephan Linz, 3 Nov 2003: + - more endianess fixes for LAN91C111 driver + - CFG_HZ configuration patch for NIOS Cyclone board -commit ad4eb555671d97f96dc56eab55103b1f86874b01 -Author: Wolfgang Denk -Date: Wed Apr 18 14:30:39 2007 +0200 +* Patch by Stephan Linz, 28 Oct 2003: + fix PHY_INT_REG vs. PHY_MASK_REG bug in drivers/smc91111.c - MCC200 board: remove warning which is obsolete after PSoC firmware changes +* Patch by Steven Scholz, 20 Oct 2003: + - make "mii info " show infor for PHY at "addr" only + - Endian fix for miiphy_info() - Signed-off-by: Wolfgang Denk +* Patch by Gleb Natapov, 19 Sep 2003: + Move most of the timer interrupt related PPC code to ppc_lib/interrupts.c -commit 3747a3f010b2b1442dec3e871c69788b6017aaae -Author: Domen Puncer -Date: Wed Apr 18 12:11:05 2007 +0200 +* Patch by Anders Larsen, 17 Sep 2003: + Bring ARM memory layout in sync with the documentation: + stack and malloc-heap are now located _below_ the U-Boot code - [PATCH] icecube/lite5200b: document wakeup from low-power support +* Accelerate booting on TRAB board: read and check autoupdate image + headers first instead of always reading the whole images. - Signed-off-by: Domen Puncer +* Fix type in MPC5XXX code (pointed out by Victor Wren) -commit e673226ff9d6aa91b47ceac74b8c13770b06bb37 -Author: Stefan Roese -Date: Wed Apr 18 12:07:47 2007 +0200 +* Enabled password check on RMU board - ppc4xx: Update Acadia to not setup PLL when booting via bootstrap EEPROM +* Fix configuration problem with IceCube in LOWBOOT configuration: + envrionment got embedded, corrupting the image layout. - Signed-off-by: Stefan Roese +* Fix NEC display names (it's 6440 [for 640x480], not 6640). -commit 90e6f41cf09fc98f6ccb510e183d53ab8546cf2f -Author: Stefan Roese -Date: Wed Apr 18 12:05:59 2007 +0200 +* Added BMS2003 board + add support for NEC NL6448BC33-54. 10.4", 640x480 TFT display - ppc4xx: Add output for bootrom location to 405EZ ports +* Fix flash driver for TRAB board (must use Unlock Bypass Reset + command to exit Unlock Bypass Mode); adjust timings for flash, SRAM + and CPLD - Now 405EZ ports also show upon bootup from which boot device - they are configured to boot: +* Use "-fPIC" instead of "-mrelocatable" to prevent problems with + recent tools - U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05) +* Add checksum verification to 'imls' command - CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz) - Bootstrap Option E - Boot ROM Location EBC (32 bits) - 16 kB I-Cache 16 kB D-Cache - Board: Acadia - AMCC PPC405EZ Evaluation Board +* Add bd_info fields needed for 4xx Linux I2C driver - Signed-off-by: Stefan Roese +* Patch by Martin Krause, 4 Nov. 2003: + Fix error in cmd_vfd.c (TRAB board: "vfd /1" shows now only one Bitmap) -commit 9c00dfb0bf89c8c23e8af5b5bdf49cf66d769f85 -Author: Peter Pearse -Date: Tue Apr 17 13:30:33 2007 +0100 +* Print used network interface when CONFIG_NET_MULTI is set - Move ppearse to ARM board list - Add Konstantin Kletschke for scb9328. - Signed-off-by: Peter Pearse +* Patch by Bernhard Kuhn, 28 Oct 2003: + Add low boot support for MPC5200 -commit d3832e8fe1b214ec62424eac36cfda9fc56d21b3 -Author: Domen Puncer -Date: Mon Apr 16 14:00:13 2007 +0200 +* Fix problem with dual PCMCIA support (NSCU) - [PATCH] icecube/lite5200b: wakeup from low-power support +* Fix MPC5200 I2C initialization function - U-Boot part of Lite5200b low power mode support. - Puts SDRAM out of self-refresh and transfers control to - address saved at physical 0x0. +====================================================================== +Changes for U-Boot 1.0.0: +====================================================================== - Signed-off-by: Domen Puncer - Acked-by: Grant Likely +* Fix parameter passing to standalone images with bootm command -commit f35a53fc7b0c79fcfe7bdc01163c4b34aaba1460 -Author: Gerald Van Baren -Date: Sun Apr 15 13:54:26 2007 -0400 +* Patch by Kyle Harris, 30 Oct 2003: + Fix build errors for ixdp425 board - Fix the ft_cpu_setup() property settings. +* Patch by David M. Horn, 29 Oct 2003: + Fixes to build under CYGWIN - Use "setter" functions instead of flags, cleaner and more flexible. - It also fixes the problem noted by Timur Tabi that the ethernet MAC - addresses were all being set incorrectly to the same MAC address. +* Get IceCube MGT5100 working (again) -commit c28abb9c614f65ce2096cc4a66fc886c77d0e5a4 -Author: Gerald Van Baren -Date: Sat Apr 14 22:51:24 2007 -0400 +* Fix problems in memory test on some boards (which was not + non-destructive as intended) - Improve the bootm command for CONFIG_OF_LIBFDT +* Patch by Gary Jennejohn, 28 Oct 2003: + Change fs/fat/fat.c to put I/O buffers in BSS instead on the stack + to prevent stack overflow on ARM systems - In bootm, create the "/chosen" node only if it doesn't already exist - (better matches the previous behavior). - Update for proper reserved memory map handling for initrd. +* Patch by Stephan Linz, 28 Oct 2003: + fix init sequence error for NIOS port -commit 3f9f08cf91c8a6949a5d78a18bd3d8df7b86d888 -Author: Gerald Van Baren -Date: Sat Apr 14 22:46:41 2007 -0400 +* Allow lowercase spelling for IceCube_5200; support MPC5200LITE name - Add some utilities to manipulate the reserved memory map. +* Add CONFIG_VERSION_VARIABLE to TRAB configuration -commit 8048cdd56f04a756eeea4951f402bf5cc33785db -Author: Wolfgang Denk -Date: Sat Apr 14 21:16:54 2007 +0200 +* Patch by Xiao Xianghua, 23 Oct 2003: + small patch for mpc85xx - Update CHANGELOG +* Fix small problem in MPC5200 I2C driver -commit 8e6875183cdca91c134408d119d4abcd48ef6856 -Author: Haavard Skinnemoen -Date: Sun Dec 17 18:56:46 2006 +0100 +* Fix FCC3 support on ATC board - AVR32: Enable MMC support +* Correct header printing for multi-image files in do_bootm() - Set up the portmux for the MMC interface and enable the MMC driver - along with support for DOS partitions, ext2 and FAT filesystems. +* Make CONFIG_SILENT_CONSOLE work with CONFIG_AUTOBOOT_KEYED - Signed-off-by: Haavard Skinnemoen +* Fix PCI problems on PPChameleon board -commit fc26c97bb6df41b4a95662c34054fe912387bf38 -Author: Haavard Skinnemoen -Date: Fri Jan 20 10:03:53 2006 +0100 +* Patch by Steven Scholz, 18 Oct 2003: + Fix AT91RM9200 ethernet driver - Atmel MCI driver +* Patch by Nye Liu, 17 Oct 2003: + Fix typo in include/mpc8xx.h - Driver for the Atmel MCI controller (MMC interface) for AT32AP CPUs. +* Patch by Richard Woodruff, 16 Oct 03: + Fixes for cpu/arm925/interrupt.c + - Initialize timestamp & lastdec vars. + - fix timestamp overflows. + - fix lastdec overflow. + - smarter normalization to allow udelay() below 1ms to work. - The AT91 ARM-based CPUs use basically the same hardware, so it should - be possible to share this driver, but no effort has been made so far. +* Patch by Scott McNutt, 16 Oct + add networking support for the Altera Nios Development Kit, + Cyclone Edition (DK-1C20) - Hardware documentation can be found in the AT32AP7000 data sheet, - which can be downloaded from +* Patch by Jon Diekema, 14 Oct 2003: + add hint about doc/README.silent to README file - http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 +* Add CompactFlash support for NSCU - Signed-off-by: Haavard Skinnemoen +* Fix PCI problems on PPChameleonEVB -commit 05fdab1ef6a10d049a50021a86f1226f444d9b9f -Author: Haavard Skinnemoen -Date: Sun Dec 17 18:55:37 2006 +0100 +* TRAB auto-update: Base decision if we have to strip the image + header on image type as encoded in the header + (include image type patch by Martin Krause, 17 Oct 2003) - AVR32: Add clk and gpio infrastructure for mmci +* Patches by Xianghua Xiao, 15 Oct 2003: - Implement functions for configuring the mmci pins, as well as - functions for getting the clock rate of the mmci controller. + - Added Motorola CPU 8540/8560 support (cpu/85xx) + - Added Motorola MPC8540ADS board support (board/mpc8540ads) + - Added Motorola MPC8560ADS board support (board/mpc8560ads) - Signed-off-by: Haavard Skinnemoen +* Fix flash timings on TRAB board -commit 7fac3f69e9f05c5e5326681976c35d129324c4de -Author: Haavard Skinnemoen -Date: Sun Dec 17 18:53:56 2006 +0100 +* Make sure HUSH is initialized for running auto-update scripts - Enable partition support with MMC +* Make 5200 reset command _really_ reset the board, without running + any other code after it - Include implementations of init_part() and get_partition_info() when - CONFIG_MMC is set. +* Fix errors with flash erase when range spans across banks + that are mapped in reverse order - Signed-off-by: Haavard Skinnemoen +* Fix flash mapping and display on P3G4 board -commit 9a24f477a1ed5bb0f74377c985d754ebbfa44872 -Author: Haavard Skinnemoen -Date: Sun Dec 17 17:14:30 2006 +0100 +* Patch by Kyle Harris, 15 Jul 2003: + - add support for Intel IXP425 CPU + - add support for IXDP425 eval board - AVR32: Enable networking +* Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent + for more information - Implement MACB initialization for AVR32 and ATSTK1000, and turn - everything on, including the MACB driver. +* Patch by Steven Scholz, 10 Oct 2003 + - Add support for Altera FPGA ACEX1K - Signed-off-by: Haavard Skinnemoen +* Patches by Thomas Lange, 09 Oct 2003: + - fix cmd_ide.c for non ppc boards (read/write functions did not + add ATA base address) + - fix for shannon board + - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code + - Endian swap ATA identity for all big endian CPUs, not just PPC + - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize + args to linux + - add support for dbau1x00 board (MIPS32) -commit 5c1fe1ffffd1750a7e47e5a2e2cd600c00e4f009 -Author: Haavard Skinnemoen -Date: Fri Jan 20 10:03:34 2006 +0100 +* Patch by Sangmoon Kim, 07 Oct 2003: + add support for debris board - Atmel MACB ethernet driver +* Patch by Martin Krause, 09 Oct 2003: + Fixes for TRAB board + - /board/trab/rs485.c: correct baudrate + - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in + udelay(); fix some timing problems with adc controller + - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power; + modify commands: touch and buzzer - Driver for the Atmel MACB on-chip ethernet controller. +* Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE + (quick & dirty workaround for rogue pointer problem in get_vfatname()); + Use direct function calls for auto_update instead of hush commands - This driver has been tested on the ATSTK1000 board with a AT32AP7000 - CPU. It should probably work on AT91SAM926x as well with some minor - modifications. +* Patch by Scott McNutt, 04 Oct 2003: + - add support for Altera Nios-32 CPU + - add support for Nios Cyclone Development Kit (DK-1C20) - Hardware documentation can be found in the AT32AP7000 data sheet, - which can be downloaded from +* Patch by Steven Scholz, 29 Sep 2003: + - A second parameter for bootm overwrites the load address for + "Standalone Application" images. + - bootm sets environment variable "filesize" to the resulting + (uncompressed) data length for "Standalone Application" images + when autostart is set to "no". Now you can do something like + if bootm $fpgadata $some_free_ram ; then + fpga load 0 $some_free_ram $filesize + fi - http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 +* Patch by Denis Peter, 25 Sept 2003: + add support for the MIP405 Rev. C board - Signed-off-by: Haavard Skinnemoen +* Patch by Yuli Barcohen, 25 Sep 2003: + add support for Zephyr Engineering ZPC.1900 board -commit b4ec9c2d43d894729bb633bfdbdfa95a962c1556 -Author: Haavard Skinnemoen -Date: Sun Dec 17 16:56:14 2006 +0100 +* Patch by Anders Larsen, 23 Sep 2003: + add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only + implemented for the x86 architecture) - AVR32: Add clk and gpio infrastructure for macb0 and macb1 +* Patch by Sangmoon Kim, 23 Sep 2003: + fix pll_pci_to_mem_multiplier table for MPC8245 - Implement functions for configuring the macb0 and macb1 pins, as - well as functions for getting the clock rate of the various - busses the macb ethernet controllers are connected to. +* Patch by Anders Larsen, 22 Sep 2003: + enable timed autoboot on PXA - Signed-off-by: Haavard Skinnemoen +* Patch by David Müller, 22 Sep 2003: + - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver + returns correct libgcc file path + - "latency" reduction of busy-loop waiting to improve "U-Boot" boot + time on s3c24x0 systems -commit d5acb95b16a0a74c643524342c3437e765426d05 -Author: Haavard Skinnemoen -Date: Sun Dec 17 15:39:15 2006 +0100 +* Patch by Jon Diekema, 19 Sep 2003: + - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet + link state to the fault LED. + - In NetLoop, make the Fault LED reflect the link status. The link + status gets updated on entry, and on timeouts. - AVR32: Implement simple DMA memory allocator +* Patch by Anders Larsen, 18 Sep 2003: + allow mkimage to build and run on Cygwin-hosted systems - Implement dma_alloc_coherent() which returns cache-aligned - uncacheable memory. +* Patch by Frank Müller, 18 Sep 2003: + use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in + cpu/mpc8xx/fec.c - Signed-off-by: Haavard Skinnemoen +* Patch by Pantelis Antoniou, 16 Sep 2003: + add tool to compute fileds in the PLPRCR register for MPC86x -commit 91975b0fea773c9e681fea8cf3349669f27685ee -Author: Haavard Skinnemoen -Date: Sun Dec 17 15:46:02 2006 +0100 +* Use IH_TYPE_FILESYSTEM for TRAB "disk" images. - Import from the Linux kernel +* Fix build problems under FreeBSD - Instead of creating yet another set of MII register definitions - in the macb driver, here's a complete set of definitions for everyone - to use. +* Add generic filesystem image type - Signed-off-by: Haavard Skinnemoen +* Make fatload set filesize environment variable -commit 1b804b229556a4d862da93c0ec94e79419364b2c -Author: Haavard Skinnemoen -Date: Wed Mar 21 19:47:36 2007 +0100 +* enable basic / medium / high-end configurations for PPChameleonEVB + board; fix NAND code - AVR32: Include more commands for ATSTK1000 +* enable TFTP client code to specify to the server the desired + timeout value (see RFC-2349) - Include the imi, imls and jffs commands sets by default on ATSTK1000. - Also define CONFIG_BOOTARGS to something more useful, define - CONFIG_BOOTCOMMAND and enable autoboot by default. +* Improve SDRAM setup for TRAB board - Signed-off-by: Haavard Skinnemoen +* Suppress all output with splashscreen configured only if "splashimage" + is set -commit 9c0deb5ae3ea0189f2e08ac29ef1316f1fb8548d -Author: Haavard Skinnemoen -Date: Wed Mar 21 19:44:48 2007 +0100 +* Fix problems with I2C support for mpc5200 - AVR32: Provide a definition of struct stat +* Adapt TRAB configuration and auto_update to new memory layout - Copy the definition of struct stat from the Linux kernel. +* Add configuration for wtk board - Signed-off-by: Haavard Skinnemoen +* Add support for the Sharp LQ065T9DR51U LCD display -commit 12f099c08167a7a51aeee623bc16dafd0841271c -Author: Haavard Skinnemoen -Date: Sun Dec 17 14:46:06 2006 +0100 +* Patch by Rune Torgersen, 17 Sep 2003: + - Fixes for MPC8266 default config + - Allow eth_loopback_test() on 8260 to use a subset of the FCC's - AVR32: Use initdram() instead of board_init_memories() +* Patches by Jon Diekema, 17 Sep 2003: + - update README (SHOW_BOOT_PROGRESS values for cmd_nand.c and + env_common.c) + - sbc8260 tweaks + - adjust "help" output - Conform to the "standard" interface and use initdram() instead of - board_init_memories() on AVR32. This enables us to get rid of the - sdram_size member of the global_data struct as well. +* Patches by Anders Larsen, 17 Sep 2003: + - fix spelling errors + - set GD_FLG_DEVINIT flag only after device function pointers + are valid + - Allow CFG_ALT_MEMTEST on systems where address zero isn't + writeable + - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs + - trigger watchdog while waiting in serial driver - Signed-off-by: Haavard Skinnemoen +* Add auto-update code for TRAB board using USB memory sticks, + support new configuration with more memory -commit 1f4f2121c2685182eb87fa9a9b799d1917387a1c -Author: Haavard Skinnemoen -Date: Mon Nov 20 15:53:10 2006 +0100 +* disable MPC5200 bus pipelining as workaround for bus contention - AVR32: Relocate u-boot to SDRAM +* Modify XLB arbiter priorities on MPC5200 so all devices use same + priority; configure critical interrupts to be handled like external + interrupts - Relocate the u-boot image into SDRAM like everyone else does. This - means that we can handle much larger .data and .bss than we used to. +* Make IPB clock on MGT5100/MPC5200 configurable in board config file; + go back to 66 MHz for stability - Signed-off-by: Haavard Skinnemoen +* Patches by Jon Diekema, 15 Sep 2003: + - add description for missing CFG_CMD_* entries in the README file + - sacsng tweaks -commit df548d3c3e2bbc40258713167859ffc2ce99a900 -Author: Haavard Skinnemoen -Date: Sun Nov 19 18:06:53 2006 +0100 +* Patch by Gleb Natapov, 14 Sep 2003: + enable watchdog support for all MPC824x boards that have a watchdog - AVR32: Resource management rewrite +* On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the + "Non-octet Aligned Frame" errors we see at 100 Mbps - Rewrite the resource management code (i.e. I/O memory, clock gating, - gpio) so it doesn't depend on any global state. This is necessary - because this code is heavily used before relocation to RAM, so we - can't write to any global variables. +* Patch by Sharad Gupta, 14 Sep 2003: + fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL]) - As an added bonus, this makes u-boot's memory footprint a bit smaller, - although some functionality has been left out; all clocks are enabled - all the time, and there's no checking for gpio line conflicts. +* Patch by llandre, 11 Sep 2003: + update configuration for PPChameleonEVB board - Signed-off-by: Haavard Skinnemoen +* Patch by David Müller, 13 Sep 2003: + various changes to VCMA9 board specific files -commit 03d1e1365796cd15d1726e8a51fd8b5be50b2fe9 -Author: Haavard Skinnemoen -Date: Sat Nov 18 18:01:13 2006 +0100 +* Add I2C support for MGT5100 / MPC5200 - AVR32: Clean up memory-map.h for at32ap7000 +* Patch by Rune Torgersen, 11 Sep 2003: + Changed default memory option on MPC8266ADS to NOT be Page Based + Interleave, since this doesn't work very well with the standard + 16MB DIMM - Convert spaces to tabs (must have missed this one last time around), - sort the entries by address and group them together by bus - connectivity. +* Patch by George G. Davis, 12 Sep 2003: + fix Makefile settings for sk98 driver - Signed-off-by: Haavard Skinnemoen +* Patch by Stefan Roese, 12 Sep 2003: + - new boards added: DP405, HUB405, PLU405, VOH405 + - some esd boards updated + - cpu/ppc4xx/sdram.c: disable memory controller before setting + first values + - cpu/ppc4xx/405_pci.c: set vendor id on PPC405EP systems -commit 28c699ef69f4b6cdf252e4747b7b590028a88981 -Author: Haavard Skinnemoen -Date: Sat Nov 18 17:32:31 2006 +0100 +* Patch by Martin Krause, 11 Sep 2003: + add burn-in tests for TRAB board - AVR32: Build position-independent u-boot +* Enable instruction cache on MPC5200 board - Add -fPIC -mno-init-got to the avr32-specific CFLAGS to make u-boot - position independent. This will make relocation a lot easier. +* Patch by Denis Peter, 11 Sep 2003: + - fix USB data pointer assignment for bulk only transfer. + - prevent to display erased directories in FAT filesystem. - -mno-init-got means that gcc shouldn't emit code to load the GOT - address into r6 in every function prologue. We do it once and for - all in the early startup assembly code, so enabling this option - makes u-boot a bit faster and smaller. +* Change output format for NAND flash - make it look like for other + memory, too - The assembly parts have always been position-independent, so no code - changes should be necessary. +====================================================================== +Changes for U-Boot 0.4.8: +====================================================================== - Signed-off-by: Haavard Skinnemoen +* Add I2C and RTC support for RMU board -commit 5374b36de91d006d1df9536259fa9f66b01aa3aa -Author: Haavard Skinnemoen -Date: Sat Nov 18 17:24:31 2006 +0100 +* Patches by Denis Peter, 9 Sep 2003: + add FAT support for IDE, SCSI and USB - AVR32: Use avr32-linux- cross-compilation prefix by default +* Patches by Gleb Natapov, 2 Sep 2003: + - cleanup of POST code for unsupported architectures + - MPC824x locks way0 of data cache for use as initial RAM; + this patch unlocks it after relocation to RAM and invalidates + the locked entries. - It doesn't really matter which toolchain you use to compile u-boot, - but the avr32-linux one is probably what most people have installed. +* Patch by Gleb Natapov, 30 Aug 2003: + new I2C driver for mpc107 bridge. Now works from flash. - Signed-off-by: Haavard Skinnemoen +* Patch by Dave Ellis, 11 Aug 2003: + - JFFS2: fix typo in common/cmd_jffs2.c + - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option + - JFFS2: remove node version 0 warning + - JFFS2: accept JFFS2 PADDING nodes + - SXNI855T: add AM29LV800 support + - SXNI855T: move environment from EEPROM to flash + - SXNI855T: boot from JFFS2 in NOR or NAND flash -commit c841beeddebece0039e724fb27f4d1a39ee1c6b6 -Author: Haavard Skinnemoen -Date: Sat Nov 18 17:15:30 2006 +0100 +* Patch by Bill Hargen, 11 Aug 2003: + fixes for I2C on MPC8240 + - fix i2c_write routine + - fix iprobe command + - eliminates use of global variables, plus dead code, cleanup. - AVR32: Split start_u_boot into board_init_f and board_init_r +* Add support for USB Mass Storage Devices (BBB) + (tested with USB memory sticks only) - Split the avr32 initialization code into a function to run before - relocation, board_init_f and a function to run after relocation, - board_init_r. For now, board_init_f simply calls board_init_r - at the end. +* Avoid flicker on TRAB's VFD - Signed-off-by: Haavard Skinnemoen +* Add support for SK98xx driver -commit 37403005cfe6bb13964d450f6a48a0b0f2f7017e -Author: Heiko Schocher -Date: Sat Apr 14 05:26:48 2007 +0200 +* Add PCI support for SL8245 board - [Fix] Set the LED status register on the UC101 for the LXT971 PHY. - clear the Display after reset. +* Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB) + or 1 x AM29LV652 (two LV065 in one chip = 16 MB); + Run IPB at 133 Mhz; adjust the MII clock frequency accordingly - Signed-off-by: Heiko Schocher +* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz) + to allow for more accurate baudrate settings + (error now 0.7% at 115 kbps, instead of 3.5% before) -commit 7882751c78b7ecabfd49b0eff8de27661c71f16c -Author: Denis Peter -Date: Fri Apr 13 09:13:33 2007 +0200 +* Patch by Andreas Mohr, 4 Sep 2003: + Fix a lot of spelling errors - [PATCH] Fix bugs in cmd_ide.c and cmd_scsi.c +* Add support for PPChameleon Eval Board - Fix bug introduced by "Fix get_partition_info() parameter error in all - other calls" from 2005-03-04 in cmd_ide.c and cmd_scsi.c, which prevented - to use diskboot or scsiboot form another device than 0. +* Add support for P3G4 board - Signed-off-by: Denis Peter +* Fix problem with MGT5100 FEC driver: add "early" MAC address + initialization -commit 0b94504d22e70f537c17a0d38c87edb6e370977d -Author: Greg Lopp -Date: Fri Apr 13 08:02:24 2007 +0200 +* Patch by Yuli Barcohen, 7 Aug 2003: + check BCSR to detect if the board is configured in PCI mode - [PATCH] Fix use of "void *" for block dev read/write buffer pointers +====================================================================== +Changes for U-Boot 0.4.7: +====================================================================== - Signed-of-by: Greg Lopp - Acked-by: Grant Likely +* Patch by Raghu Krishnaprasad, 7 Aug 2003: + add support for Adder II MPC852T module -commit 6fbf261f8df294e589cfadebebe5468e3c0f29e9 -Author: Xie Xiaobo -Date: Fri Mar 9 19:08:25 2007 +0800 +* Patch by George G. Davis, 19 Aug 2003: + fix TI Innovator/OMAP1510 pin configs - Fix two bugs for MPC83xx DDR2 controller SPD Init +* Patches by Kshitij, 18 Aug 2003 + - add support for arm926ejs cpu core + - add support for TI OMAP 1610 Innovator Board - There are a few bugs in the cpu/mpc83xx/spd_sdram.c - the first bug is that the picos_to_clk routine introduces a huge - rounding error in 83xx. - the second bug is that the mode register write recovery field is - tWR-1, not tWR >> 1. +* Patch by Yuli Barcohen, 14 Aug 2003: + add support for bzip2 uncompression -commit 2ad3aba01d37b72e7c957b07e102fccd64fe6d13 -Author: Jeffrey Mann -Date: Thu Apr 12 14:15:59 2007 +0200 +* Add GCC library to examples/Makefile so GCC utility functions will + be resolved, too - ppc4xx: Fix i2c divisor calcularion for PPC4xx +* Add I2C and RTC support for RMU board using software I2C driver + (because of better response to iprobe command); fix problem with + "reset" command - This patch fixes changes the i2c_init(...) function to use the function - get_OPB_freq() rather than calculating the OPB speed by - sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is - specific per processor. The prior method was not and so was calculating - the wrong speed for some PPC4xx processors. +* Patch by Matthias Fuchs, 28 Aug 2003: + Added CONFIG_BOOTP_DNS2 and CONFIG_BOOTP_SEND_HOSTNAME to + CONFIG_BOOTP_MAKS (see README). - Signed-off-by: Jeffrey Mann - Signed-off-by: Stefan Roese +* Fix ICU862 environment problem -commit 6c9ba919375db977aaad9146bf320c7afd07ae7a -Author: Wolfgang Denk -Date: Wed Apr 11 17:25:01 2007 +0200 +* Fix RAM size detection for RMU board - Update CHANGELOG +* Implement "reset" for MGT5100/MPC5200 systems - Signed-off-by: Wolfgang Denk +====================================================================== +Changes for U-Boot 0.4.6: +====================================================================== -commit 51056dd9863e6a1bc363afbbe1775c58cd967418 -Author: Wolfgang Denk -Date: Wed Apr 11 17:22:55 2007 +0200 +* Make Ethernet autonegotiation on INCA-IP work for all clock rates; + allow selection of clock frequency as "make" target - Update for SC3 board +* Implement memory autosizing code for IceCube boards - * Make IDE timeout configurable through ide_reset_timeout variable. - * Use Newline as "password" string - * Use just a single partition in NAND flash +* Configure network port on INCA-IP for autonegotiation -commit 3d98b85800c80dc68227c8f10bf5c93456d6d054 -Author: Haiying Wang -Date: Mon Jan 22 12:37:30 2007 -0600 +* Fix overflow problem in network timeout code - Add PIXIS FPGA support for MPC8641HPCN board. +* Patch by Richard Woodruff, 8 Aug 2003: + Allow crc32 to be used at address 0x000 (crc32_no_comp, too). - Move the 8641HPCN's PIXIS code to the new directory - board/freescale/common/ as it will be shared by - future boards not in the same processor family. +====================================================================== +Changes for U-Boot 0.4.5: +====================================================================== - Write a "pixis_reset" command that utilizes the FPGA - reset sequencer to support alternate soft-reset options - such as using the "alternate" flash bank, enabling - the watch dog, or choosing different CPU frequencies. +* Update for TQM board defaults: + disable clocks_in_mhz, enable boot count limit - Add documentation for the pixis_reset to README.mpc8641hpcn. +* Removed tools/gdb from "make all" target. Added make target "gdbtools" + in toplevel directory instead. Removed astest.c from tools/gdb because + it is no longer relevant. - Signed-off-by: Haiying Wang - Signed-off-by: Jon Loeliger +* Fix PCI support for MPC5200 / IceCube Board -commit 64dbbd40c58349b64f43fd33dbb5ca0adb67d642 -Author: Gerald Van Baren -Date: Fri Apr 6 14:19:43 2007 -0400 +* Map ISP1362 USB OTG controller for NSCU board - Moved fdt command support code to fdt_support.c +* Patch by Brad Parker, 02 Aug 2003: + fix sc520_cdp problems - ...in preparation for improving the bootm command's handling of fdt blobs. - Also cleaned up some coding sloppiness. +* Implement Boot Cycle Detection (Req. 2.3 of OSDL CGL Reqirements) -commit 6679f9299534e488a171a9bb8f9bb891de247aab -Author: Gerald Van Baren -Date: Fri Apr 6 14:17:14 2007 -0400 +* Allow erase command to cross flash bank boundaries - libfdt: Make fdt_check_header() public +* Patch by Scott McNutt, 21 Jul 2003: + Add support for LynuxWorks Kernel Downloadable Images (KDIs). + Both LynxOS and BlueCat linux KDIs are supported. - Changed _fdt_check_header() to fdt_check_header() and made it part of - the interface - it is a useful routine. +* Patch by Richard Woodruff, 25 Jul 2003: + use more reliable reset for OMAP/925T - Also did some asthetics cleanup to the include files (headers). +* Patch by Nye Liu, 25 Jul 2003: + fix typo in mpc8xx.h -commit c0707ce65677650b5ceab0500ee50ae5168afef2 -Author: Aubrey Li -Date: Thu Apr 5 18:34:06 2007 +0800 +* Patch by Richard Woodruff, 24 Jul 2003: + Fixes for cmd_nand.c: + - Fixed null dereferece which could result in incorrect ECC values. + - Added support for devices with no Ready/Busy signal hooked up. + - Added OMAP1510 read/write protect handling. + - Fixed nand.h's ECCPOS. A conflict existed with POS5 and badblock + for non-JFFS2. + - Switched default ECC to be JFFS2. - [Blackfin][PATCH] Kill off a bunch of common local prototypes +* Allow crc32 to be used at address 0x000 -commit 7b7e30aa64bb6657a1bfd32fdbdbfeb561e6a48d -Author: Aubrey Li -Date: Thu Apr 5 18:33:04 2007 +0800 +* Provide consistent interface to standalone applications to access + the 'global_data' structure + Provide a doc/README.standalone more useful to users/developers. - [Blackfin][PATCH] Fix dynamic CPLB generation issue +* Make IceCube MGT5100 FEC driver work -commit 0445e3a264251d75b1be45ef713c70726a2952f0 -Author: Aubrey Li -Date: Thu Apr 5 18:31:47 2007 +0800 +* Implement new mechanism to export U-Boot's functions to standalone + applications: instead of using (PPC-specific) system calls we now + use a jump table; please see doc/README.standalone for details - [Blackfin][PATCH] minior cleanup +* Patch by Dave Westwood, 24 Jul 2003: + added support for Unity OS (a proprietary OS) -commit 155fd766573981090e638b493d5857562151862e -Author: Aubrey Li -Date: Thu Apr 5 18:31:18 2007 +0800 +* Patch by Detlev Zundel, 23 Jul 2003: + add "imls" command to print flash table of contents - [Blackfin][PATCH] Fix copyright and update license +* Fix cold boot detection for log buffer reset -commit 9fd437bbd75d282f899e1da50be20a2bf38450bc -Author: Aubrey Li -Date: Thu Apr 5 18:30:25 2007 +0800 +* Return error for invalid length specifiers with "cp.X" etc. - [Blackfin][PATCH] Add BF537 EMAC driver initialization +* Fix startup problem on MIPS -commit 889256e8604e0c68db1d866d720894dffede9df6 -Author: Aubrey Li -Date: Thu Apr 5 18:29:55 2007 +0800 +* Allow for CONFIG_SPLASH_SCREEN even when no explicit + bitmap support is configured - [Blackfin][PATCH] call real the system synchronize instruction +* Patch by Bill Hargen, 18 Jul 2003: + - fix endinaness problem in cpu/mpc824x/drivers/i2c/i2c1.c -commit e0df1c921b788289564e4c1ee7120a6a9cd3ab05 -Author: Aubrey Li -Date: Thu Apr 5 18:29:17 2007 +0800 +* Patch by Denis Peter, 18 Jul 2003: + - fix memory configuration for MIP405T + - fix printout of baudrate for "loadb " - [Blackfin][PATCH] remove asm/page.h as we do not actually use/want any of these definitions nor does any other arch include it +* Cleanup of TQM82xx configurations; use "official" board types + to make selection easier. -commit dfeeab2cd680df047e68e723b246adf6f33bb556 -Author: Aubrey Li -Date: Thu Apr 5 18:28:34 2007 +0800 +* Patch by Martin Krause, 17 Jul 2003: + add delay to get I2C working with "imm" command and s3c24x0_i2c.c - [Blackfin][PATCH]: fix flash unaligned copy issue +* Patch by Richard Woodruff, 17 July 03: + - Fixed bug in OMAP1510 baud rate divisor settings. -commit 443feb740584e406efa203af909fe2926608e8d5 -Author: Igor Marnat -Date: Wed Mar 21 09:55:01 2007 +0300 +* Patch by Nye Liu, 16 July 2003: + MPC860FADS fixes: + - add MPC86xADS support (uses MPC86xADS.h) + - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T) + o PLPRCR changes + o BRG changes (EXTAL/XTAL restricted to 10MHz) + o don't trust gclk() software measurement by default, depend on + CONFIG_8xx_GCLK_FREQ + - add DRAM SIMM not installed detection + - use more "correct" SDRAM initialization sequence + - allow different SDRAM sizes (8xxADS has 8M) + - default DER is 0 + - remove unused MAMR defines from FADS860T.h (all done in fads.c) + - rename MAMR/MBMR defines to be more consistent. Should eventually + be merged into MxMR to better reflect the PowerQUICC datasheet. - Update usage of 'nc' in README.NetConsole +* Patch by Yuli Barcohen, 16 Jul 2003: + support new Motorola PQ2FADS-ZU evaluation board which replaced + MPC8260ADS and MPC8266ADS - Added information about usage of NetConsole on systems where the -l and -p - switches are mutually exclusive. +====================================================================== +Changes for U-Boot 0.4.4: +====================================================================== - Signed-off-by: Igor Marnat - Signed-off-by: Ben Warren +* Add support for IceCube board (with MGT5100 and MPC5200 CPUs) -commit 31c98a88228021b314c89ebb8104fb6473da4471 -Author: Wolfgang Denk -Date: Wed Apr 4 02:09:30 2007 +0200 +* Add support for MGT5100 and MPC5200 processors - Minor coding style cleanup. +* Patch by Lutz Dennig, 15 Jul 2003: + update for R360MPI board -commit 94abd7c0583ebe01e799b25f451201deeaab550d -Author: Wolfgang Denk -Date: Wed Apr 4 01:49:15 2007 +0200 +====================================================================== +Changes for U-Boot 0.4.3: +====================================================================== - Minor cleanup. +* Patches by Kshitij, 04 Jul 2003 + - added support for arm925t cpu core + - added support for TI OMAP 1510 Innovator Board -commit 822af351ad2babc7d99033361a5fcacd30f6bc78 -Author: Rodolfo Giometti -Date: Tue Apr 3 14:27:18 2007 +0200 +* Patches by Martin Krause, 14 Jul 2003: + - add I2C support for s3c2400 systems (trab board) + - (re-) add "ping" to command table - Support for the Philips ISP116x HCD (Host Controller Driver) +* Fix handling of "slow" POST routines - Signed-off-by: Rodolfo Giometti +* Patches by Yuli Barcohen, 13 Jul 2003: + - Correct flash and JFFS2 support for MPC8260ADS + - fix PVR values and clock generation for PowerQUICC II family + (8270/8275/8280) -commit edf5851be6c17c031d4f71dd5b0a12040b7c50c8 -Author: Markus Klotzbuecher -Date: Tue Apr 3 14:27:08 2007 +0200 +* Patch by Bernhard Kuhn, 08 Jul 2003: + - add support for M68K targets - USB: cleanup monahans usb support. Remove dead code. +* Patch by Ken Chou, 3 Jul: + - Fix PCI config table for A3000 + - Fix iobase for natsemi.c + (PCI_BASE_ADDRESS_0 is the IO base register for DP83815) - Signed-off-by: Markus Klotzbuecher +* Allow to enable "slow" POST routines by key press on power-on +* Fix temperature dependend switching of LCD backlight on LWMON +* Tweak output format for LWMON -commit a65c5768e5537530bd1780af3d3fddc3113a163c -Author: Stefan Roese -Date: Mon Apr 2 10:09:30 2007 +0200 +* Patch by Stefan Roese, 11 Jul 2003: + - Fix bug in CONFIG_VERSION_VARIABLE. + - AR405 config updated. + - OCRTC/ORSG: bsp command added. + - ASH405 bsp update. - ppc4xx: Change SysACE address on Katmai +====================================================================== +Changes for U-Boot 0.4.2: +====================================================================== - With this new base address of the Xilinx SystemACE controller - the Linux driver will be easier to adapt, since it can now be - mapped via the "normal" ioremap() call. +* Add support for NSCU board - Signed-off-by: Stefan Roese +* Add support for TQM823M, TQM850M, TQM855M and TQM860M modules -commit aea03c4e8c3a21ce43d3faf48a6e6d474c8bdf73 -Author: Gerald Van Baren -Date: Sat Mar 31 14:30:53 2007 -0400 +* Add support for Am29LV160ML, Am29LV320ML, and Am29LV640ML + mirror bit flash on TQM8xxM modules - Fix some minor whitespace violations. +* Patch by Kenneth Johansson, 30 Jun 2003: + get rid of MK_CMD_ENTRY macro; update doc/README.command -commit 213bf8c822de8eecaf69860684469cdaba2e9e6a -Author: Gerald Van Baren -Date: Sat Mar 31 12:23:51 2007 -0400 +* Patch by Seb James, 30 Jun 2003: + Improve documentation of I2C configuration in README - Add a flattened device tree (fdt) command (2 of 2) +* Fix problems with previous log buffer "fixes" - Modifications to the existing code to support the new fdt command. +* Fix minor help text issues -commit 781e09ee6e3e3e392ab362c1f0ef1068adc76e3e -Author: Gerald Van Baren -Date: Sat Mar 31 12:22:10 2007 -0400 +* "log append" did not append a newline - Add a flattened device tree (fdt) command (1 of 2) +====================================================================== +Changes for U-Boot 0.4.1: +====================================================================== + +* Fix some missing commands, cleanup header files + (autoscript, bmp, bsp, fat, mmc, nand, portio, ...) + +* Rewrite command lookup and help command (fix problems with bubble + sort when sorting command name list). Minor cleanup here and there. + +* Merge from "stable branch", tag LABEL_2003_06_28_1800-stable: + - Allow to call sysmon function interactively + - PIC on LWMON board needs delay after power-on + - Add missing RSR definitions for MPC8xx + - Improve log buffer handling: guarantee clean reset after power-on + - Add support for EXBITGEN board (aka "genie") + - Add support for SL8245 board + +* Code cleanup: + - remove trailing white space, trailing empty lines, C++ comments, etc. + - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) + +* Patches by Kenneth Johansson, 25 Jun 2003: + - major rework of command structure + (work done mostly by Michal Cendrowski and Joakim Kristiansen) + +====================================================================== +Changes for U-Boot 0.4.0: +====================================================================== + +* Patches by Robert Schwebel, 26 Jun 2003: + - csb226 configuration updated + - credits for logodl port updated + - innokom configuration updated + - logodl tree update, still with coding style inconsistencies + - added OCM for ppc405 warning to README + +* Patch by Pantelis Antoniou, 25 Jun 2003: + update NetVia with V2 board support + +* Header file cleanup for ARM + +* Patch by Murray Jensen, 24 Jun 2003: + - make sure to use only U-boot provided header files + - fix problems with ".rodata.str1.4" section as used by GCC-3.x + +* Patch by Stefan Roese, 24 Jun 2003: + - Update esd ASH405 board files. + - Update esd DASA_SIM config file. + - Add ping command to some esd boards. + +* Patch by Yuli Barcohen, 23 Jun 2003: + Update for MPC8260ADS board + +* Patch by Murray Jensen, 23 Jun 2003: + - cleanup of GCC 3.x compiler warnings + +* Patch by Rune Torgersen, 4 Jun 2003: + add large memory support for MPC8266ADS board + +* Patch by Richard Woodruff, 19 June 03: + - Enabled standard u-boot device abstraction for ARM + - Enabled console device for ARM + - Initilized bi_baudrate for ARM + +* Patch by Bill Hargen, 23 Apr 2003: + fix byte order for 824x I2C addresses (write op) + +* Patch by Murray Jensen, 20 Jun 2003: + - hymod update + - cleanup (especially for gcc-3.x compilers) + +* Patch by Tom Guilliams, 20 Jun 2003: + added CONFIG_750FX support for IBM 750FX processors + +* Patch by Devin Crumb, 02 Apr 2003: + Fix clock divider rounding problem in drivers/serial.c + +* Patch by Richard Woodruff, 19 June 03: + - Fixed smc91c111 driver to sync with the u-boot environment + (driver/smc91c111.c). + - Added eth_init error return check in NetLoop (net/net.c). + +* Patch by Ken Chou, 19 June 2003: + Added support for A3000 SBC board (Artis Microsystems Inc.) + +* Patches by Murray Jensen, 17 Jun 2003: + - Hymod board database mods: add "who" field and new xilinx chip types + - provide new "init_cmd_timeout()" function so code external to + "common/main.c" can use the "reset_cmd_timeout()" function before + entering the main loop + - add DTT support for adm1021 (new file dtt/adm1021.c; config + slightly different. see include/configs/hymod.h for an example + (requires CONFIG_DTT_ADM1021, CONFIG_DTT_SENSORS, and + CFG_DTT_ADM1021 defined) + - add new "eeprom_probe()" function which has similar args and + behaves in a similar way to "eeprom_read()" etc. + - add 8260 FCC ethernet loopback code (new "eth_loopback_test()" + function which is enabled by defining CONFIG_ETHER_LOOPBACK_TEST) + - gdbtools copyright update + - ensure that set_msr() executes the "sync" and "isync" instructions + after the "mtmsr" instruction in cpu/mpc8260/interrupts.c + - 8260 I/O ports fix: Open Drain should be set last when configuring + - add SIU IRQ defines for 8260 + - allow LDSCRIPT override and OBJCFLAGS initialization: change to + config.mk to allow board configurations to override the GNU + linker script, selected via the LDSCRIPT, make variable, and to + give an initial value to the OBJCFLAGS make variable + - 8260 i2c enhancement: + o correctly extends the timeout depending on the size of all + queued messages for both transmit and receive + o will not continue with receive if transmit times out + o ensures that the error callback is done for all queued tx + and rx messages + o correctly detects both tx and rx timeouts, only delivers one to + the callback, and does not overwrite an earlier error + o logic in i2c_probe now correct + - add "vprintf()" function so that "panic()" function can be + technically correct + - many Hymod board changes + +* Patches by Robert Schwebel, 14 Jun 2003: + - add support for Logotronic DL datalogger board + - cleanup serial line after kermit binary download + - add debugX macro (debug level support) + - update mach-types.h to latest arm.linux.org.uk master list. + +* Patches by David Müller, 12 Jun 2003: + - rewrite of the S3C24X0 register definitions stuff + - "driver" for the built-in S3C24X0 RTC + +* Patches by Yuli Barcohen, 12 Jun 2003: + - Add MII support and Ethernet PHY initialization for MPC8260ADS board + - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset + configuration word supplied by FPGA on some MPC8260ADS boards + +* Patch by Pantelis Antoniou, 10 Jun 2003: + Unify status LED interface + +* Add support for DS12887 RTC; add RTC support for ATC board + +* Patch by Nicolas Lacressonniere, 11 Jun 2003: + Modifications for Atmel AT91RM9200DK ARM920T based development kit + - Add Atmel DataFlash support for reading and writing. + - Add possibility to boot a Linux from DataFlash with BOOTM command. + - Add Flash detection on Atmel AT91RM9200DK + (between Atmel AT49BV1614 and AT49BV1614A flashes) + - Replace old Ethernet PHY layer functions + - Change link address + +* Patch by Frank Smith, 9 Jun 2003: + use CRIT_EXCEPTION for machine check on 4xx + +* Patch by Detlev Zundel, 13 Jun 2003: + added implementation of the "carinfo" command in cmd_immap.c + +* Fix CONFIG_NET_MULTI support in include/net.h + +* Patches by Kyle Harris, 13 Mar 2003: + - Add FAT partition support + - Add command support for FAT + - Add command support for MMC + ---- + - Add Intel PXA support for video + - Add Intel PXA support for MMC + ---- + - Enable MMC and FAT for lubbock board + - Other misc changes for lubbock board + +* Patch by Robert Schwebel, April 02, 2003: + fix for SMSC91111 driver + +* Patch by Vladimir Gurevich, 04 Jun 2003: + make ppc405 ethernet driver compatible with CONFIG_NET_MULTI option + +* Patch by Stefan Roese, 05 Jun 2003: + - PPC4xx: Fix bug for initial stack in data cache as pointed out by + Thomas Schaefer (tschaefer@giga-stream.de). Now inital stack in + data cache can be used even if the chip select is in use. + - CFG_RX_ETH_BUFFER added to set the ethernet receive buffer count + (see README for further description). + - Changed config files of CONFIG_EEPRO100 boards to use the + CFG_RX_ETH_BUFFER define. + +* Add support for RMU board + +* Add support for TQM862L at 100/50 MHz + +* Patch by Pantelis Antoniou, 02 Jun 2003: + major reconstruction of networking code; + add "ping" support (outgoing only!) + +* Patch by Denis Peter, 04 June 2003: + add support for the MIP405T board + +* Patches by Udi Finkelstein, 2 June 2003: + - Added support for custom keyboards, initialized by defining a + board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD . + - Added support for the RBC823 board. + - cpu/mpc8xx/lcd.c now automatically calculates the + Horizontal Pixel Count field. + +* Fix alignment problem in BOOTP (dhcp_leasetime option) + [pointed out by Nicolas Lacressonnière, 2 Jun 2003] + +* Patch by Mark Rakes, 14 May 2003: + add support for Intel e1000 gig cards. + +* Patch by Nye Liu, 3 Jun 2003: + fix critical typo in MAMR definition (include/mpc8xx.h) + +* Fix requirement to align U-Boot image on 16 kB boundaries on PPC. + +* Patch by Klaus Heydeck, 2 Jun 2003 + Minor changes for KUP4K configuration - The fdt command uses David Gibson's libfdt library to manipulate as well - as print the flattened device tree. This patch is the new command, - the second part is the modifications to the existing code. +* Patch by Marc Singer, 29 May 2003: + Fixed rarp boot method for IA32 and other little-endian CPUs. -commit 3af0d587d93e0be5f96e1b30fa41e662f8b0803e -Author: Gerald Van Baren -Date: Sat Mar 31 12:13:43 2007 -0400 +* Patch by Marc Singer, 28 May 2003: + Added port I/O commands. - libfdt: Enhanced and published fdt_next_tag() +* Patch by Matthew McClintock, 28 May 2003 + - cpu/mpc824x/start.S: fix relocation code when booting from RAM + - minor patches for utx8245 - Enhanced the formerly private function _fdt_next_tag() to allow stepping - through the tree, used to produce a human-readable dump, and made - it part of the published interface. - Also added some comments. +* Patch by Daniel Engström, 28 May 2003: + x86 update -commit fa3a74cec73dfd06a5ae35a9a3368200273aaa71 -Author: Gerald Van Baren -Date: Sat Mar 31 12:05:39 2007 -0400 +* Patch by Dave Ellis, 9 May 2003 + 27 May 2003: + add nand flash support to SXNI855T configuration + fix/extend nand flash support: + - fix 'nand erase' command so does not erase bad blocks + - fix 'nand write' command so does not write to bad blocks + - fix nand_probe() so handles no flash detected properly + - add doc/README.nand + - add .jffs2 and .oob options to nand read/write + - add 'nand bad' command to list bad blocks + - add 'clean' option to 'nand erase' to write JFFS2 clean markers + - make NAND read/write faster - libfdt: Customizations for use by u-boot. +* Patch by Rune Torgersen, 23 May 2003: + Update for MPC8266ADS board - Changes to David Gibson's original source to fit into u-boot's - environment. No functionality changes. +* Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length + instead CFG_MONITOR_LEN is now only used to determine _at_compile_ + _time_ (!) if the environment is embedded within the U-Boot image, + or in a separate flash sector. -commit 35748177c64a4a83a00057e93bb33e40278a2a96 -Author: Gerald Van Baren -Date: Sat Mar 31 12:00:56 2007 -0400 +* Cleanup CFG_DER #defines in config files (wd maintained only) - libfdt: Import libfdt source (2 of 2) +* Fix data abort exception handling for arm920t CPU - This adds the applicable libfdt source files (unmodified) and a README - to explain where the source came from. +* Fix alignment problems with flash driver for TRAB board -commit 7cd5da0fe877e7171a4cdd44880bce783132871a -Author: Gerald Van Baren -Date: Sat Mar 31 11:59:59 2007 -0400 +* Patch by Donald White, 21 May 2003: + fix calculation of base address in pci_hose_config_device() - libfdt: Import libfdt source (1 of 2) +* Fix bug in command line parsing: "cmd1;cmd2" is supposed to always + execute "cmd2", even if "cmd1" fails. Note that this is different + to "run var1 var2" where the contents of "var2" will NOT be + executed when a command in "var1" fails. - This adds the applicable libfdt source files (unmodified) and a README - to explain where the source came from. +* Add zero-copy ramdisk support (requires corresponding kernel support!) -commit da6ebc1bc082cbe3b6bbde079cafe09f7ebbad4b -Author: Stefan Roese -Date: Sat Mar 31 13:16:23 2007 +0200 +* Patch by Kyle Harris, 20 May 2003: + In preparation for an ixp port, rename cpu/xscale and arch-xscale + into cpu/pxa and arch-pxa. - ppc4xx: Update Katmai bootstrap command +* Patch by Stefan Roese, 23 May 2003: + - IBM PPC405EP port added. + - CONFIG_UART1_CONSOLE added. If defined internal UART1 (and not + UART0) is used as default U-Boot console. PPC4xx only! + - esd ASH405 board added (PPC405EP based). + - BUBINGA405EP board added (PPC405EP based - IBM Eval Board). + - esd CPCI405AB board added. + - esd PMC405 board added. + - Update of some esd boards. - Now the DDR2 frequency is also 2*PLB frequency when 166MHz PLB - is selected. +* Patch by Denis Peter, 19 Mai 2003: + add support for the MIP405-3 board - Signed-off-by: Stefan Roese +* Patch by Dave Ellis, 22 May 2003: + Fix problem with only partially cleared .bss segment -commit cabee756a6532986729477c3cc1ea16ef8517ad2 -Author: Stefan Roese -Date: Sat Mar 31 13:15:06 2007 +0200 +* Patch by Rune Torgersen, 12 May 2003: + get PCI to work on a MPC8266ADS board; incorporate change to + cpu/mpc8260/pci.c to enable overrides of PCI memory parameters - ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe) +* Patch by Nye Liu, 1 May 2003: + minor patches for the FADS8xx - Additional RAM information is now printed upon powerup, like - DDR2 frequency and CAS latency. +* Patch by Thomas Schäfer, 28 Apr 2003: + Fix SPD handling for 256 ECC DIMM on Walnut - Signed-off-by: Stefan Roese +* Add support for arbitrary bitmaps for TRAB's VFD command; + allow to pass boot bitmap addresses in environment variables; + allow for zero boot delay -commit 60723803431ac75cad085690789e433d5ab9174e -Author: Stefan Roese -Date: Sat Mar 31 08:48:36 2007 +0200 +* Patch by Christian Geißinger, 19 May 2002: + On TRAB: wait until the dummy byte has been completely sent - ppc4xx: Change Yucca config file to support ECC +* Patch by David Updegraff, 22 Apr 2003: + update for CrayL1 board - With the updated 44x DDR2 driver the Yucca board now supports - ECC generation and checking. +* Patch by Pantelis Antoniou, 21 Apr 2003: + add boot support for ARTOS (a proprietary OS) - Signed-off-by: Stefan Roese +* Patch by Steven Scholz, 11 Apr 2003: + Add support for RTC DS1338 -commit 490e5730c674b20d708b783a2c5ffd7208f83873 -Author: Stefan Roese -Date: Sat Mar 31 08:47:34 2007 +0200 +* Patch by Rod Boyce, 24 Jan 2003: + Fix counting of extended partitions in diskboot command - ppc4xx: Fix "bootstrap" command for Katmai board +* Patch by Christophe Lindheimer, 20 May 2003: + allow the use of CFG_LOADS when CFG_NO_FLASH is set - The board specific "bootstrap" command is now fixed and can - be used for the AMCC Katmai board to configure different - CPU/PLB/OPB frequencies. +* Fix SDRAM timing on Purple board - Signed-off-by: Stefan Roese +* Add support for CompactFlash on ATC board + (includes support for Intel 82365 and compatible PC Card controllers, + and Yenta-compatible PCI-to-CardBus controllers) -commit 94f54703c3a776ec23e427ca2a16e0a79a5d50c1 -Author: Stefan Roese -Date: Sat Mar 31 08:46:08 2007 +0200 +* Patch by Mathijs Haarman, 08 May 2003: + Add lan91c96 driver (tested on Lubbock and custom PXA250 board only) - ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe) +* Fix problem with usage of "true" (undefined in current versions of bfd.h) - Fix a bug in the auto calibration routine. This driver now runs - more reliable with the tested modules. It's also tested with - 167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai. +* Add support for Promess ATC board - Signed-off-by: Stefan Roese +* Patch by Keith Outwater, 28 Apr 2003: + - Miscellaneous corrections and additions to GEN860T board specific code. + - Added GEN860_SC variant to GEN860T. + - Miscellaneous corrections to GEN860T documentation. + - Correct duplicate entry in U-Boot CREDITS file. + - Add GEN860T_SC entry in MAINTAINERS file. + - Update CREDITS file with GEN860T_SC info. -commit 342cd097be1e7affe82f42ab3da220959a699e64 -Author: Michal Simek -Date: Fri Mar 30 22:52:09 2007 +0200 +* Update Smiths Aerospace addresses in MAINTAINERS file - [PATCH] Clean include dependence +* Fix error handling in hush's version of "run" command -commit 6f934210fb293fde2cfb4251c6d96fdc58b6a906 -Author: Michal Simek -Date: Fri Mar 30 22:42:45 2007 +0200 +* LWMON extensions: + - Splashscreen support + - modem support + - sysmon support + - temperature dependend enabling of LCD - [CLEAN] Remove inefficient Suzaku code +* Allow booting from old "PPCBoot" disk partitions -commit 430f1b0f9a670c2f13eaa52e66a10db96dd3647d -Author: Stefan Roese -Date: Wed Mar 28 15:03:16 2007 +0200 +* Add support for TQM8255 Board / MPC8255 CPU - Merge some AMCC make targets to keep the top-level Makefile smaller +====================================================================== +Changes for U-Boot 0.3.1: +====================================================================== - Signed-off-by: Stefan Roese +* Make sure Block Lock Bits get cleared in R360MPI flash driver -commit 0c75c9d84307a9f1cbe1ff0c4d8937ee3a96475e -Author: Stefan Roese -Date: Wed Mar 28 14:52:12 2007 +0200 +* MPC823 LCD driver: Fill color map backwards, to allow for steady + display when Linux takes over - i2c: Enable "old" i2c commands even when CONFIG_I2C_CMD_TREE is defined +* Patch by Erwin Rol, 27 Feb 2003: + Add support for RTEMS (this time for real). - The "old" i2c commands (iprobe, imd...) are now compiled in again, - even when the i2c command tree is enabled via the CONFIG_I2C_CMD_TREE - config option. +* Add support for "bmp info" and "bmp display" commands to load + bitmap images; this can be used (for example in a "preboot" + command) to display a splash screen very quickly after poweron. - Signed-off-by: Stefan Roese +* Add support for 133 MHz clock on INCA-IP board -commit 5da048adf44bea5e3b94080d02903c2e3fe7aa4a -Author: Michal Simek -Date: Tue Mar 27 00:32:16 2007 +0200 +* Patch by Lutz Dennig, 10 Apr 2003: + Update for R360MPI board - PATCH: Resolve GPL license problem +* Add new meaning to "autostart" environment variable: + If set to "no", a standalone image passed to the + "bootm" command will be copied to the load address + (and eventually uncompressed), but NOT be started. + This can be used to load and uncompress arbitrary + data. -commit ae00bb4b2944dc64a485ed72a19754b11af7c223 -Author: Rodolfo Giometti -Date: Mon Mar 26 12:03:36 2007 +0200 +* Patch by Stefan Roese, 10 Apr 2003: + Changed DHCP client to use IP address from server option field #54 + from the OFFER packet in the server option field #54 in the REQUEST + packet. This fixes a problem using a Windows 2000 DHCP server, + where the DHCP-server is not the TFTP-server. - PXA: pxa27x USB OHCI support +* Set max brightness for MN11236 displays on TRAB board - Signed-off-by: Rodolfo Giometti +* Add support for TQM862L modules -commit ae79f60677c208326535647dcbd5c3ec40dbcb0b -Author: Markus Klotzbuecher -Date: Mon Mar 26 11:21:05 2007 +0200 +====================================================================== +Changes for U-Boot 0.3.0: +====================================================================== - USB: remove the S3C24X0_merge #define, which was introduced while - merging OHCI drivers. +* Patch by Arun Dharankar, 4 Apr 2003: + Add IDMA example code (tested on 8260 only) - Signed-off-by: Markus Klotzbuecher +* Add support for Purple Board (MIPS64 5Kc) -commit 1798049522f594013aea29457d46794298c6ae15 -Author: Michal Simek -Date: Mon Mar 26 01:39:07 2007 +0200 +* Add support for MIPS64 5Kc CPUs - Support for XUPV2P board - Reset support - BSP autoconfig support +* Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS -commit 0d974d5297349504a2ddfa09314be573b5df320a -Author: Stefan Roese -Date: Sat Mar 24 15:57:09 2007 +0100 +* Patch by Denis Peter, 04 Apr 2003: + - update MIP405-4 board - [PATCH] Add 4xx GPIO functions +* Patch by Stefan Roese, 4 Apr 2003: + - U-Boot version environment variable "ver" added + (CONFIG_VERSION_VARIABLE). + - Changed PPC405GPr version from A to B. + - Changed CPCI405 to use CTS instead of DSR on PPC405 UART1. - This patch adds some 4xx GPIO functions. It also moves some of the - common code and defines into a common 4xx GPIO header file. +* Patches by Denis Peter, 03 April 2003: + - fix PCI IRQs on MPL boards + - fix two more un-relocated pointer problems - Signed-off-by: Stefan Roese +* Fix behaviour of "run" command: + - print error message iv variable does not exist + - terminate processing of arguments in case of error -commit 2db633658bbf366ab0c8dad7a0727e1fb2ae6b11 -Author: Stefan Roese -Date: Sat Mar 24 15:55:58 2007 +0100 +* Patches by Peter Figuli, 10 Mar 2003 + - Add support for BTUART on PXA platform + - Add support for WEP EP250 (PXA) board - [PATCH] Small Sequoia cleanup +* Fix flash problems on INCA-IP; add tool to allow bruning images to + flash using a BDI2000 - Signed-off-by: Stefan Roese +* Implement fix for I2C Edge Conditions problem for all boards that + use the bit-banging driver (common/soft_i2c.c) -commit 3cb86f3e40d2a80356177434a99f75bc8baa9caf -Author: Stefan Roese -Date: Sat Mar 24 15:45:34 2007 +0100 +* Patch by Martin Winistoerfer, 23 Mar 2003 + - Add port to MPC555/556 microcontrollers + - Add support for cmi customer board with + Intel 28F128J3A, 28F320J3A or 28F640J3A flash. - [PATCH] Clean up 40EZ/Acadia support +* Patch by Rick Bronson, 28 Mar 2003: + - fix common/cmd_nand.c - This patch cleans up all the open issue of the preliminary - Acadia support. +* Patch by Arun Dharankar, 24 Mar 2003: + - add threads / scheduler example code - Signed-off-by: Stefan Roese +* Add patches by Robert Schwebel, 31 Mar 2003: + - add ctrl-c support for kermit download + - align bdinfo output on ARM + - csb226 board: bring in sync with innokom/memsetup.S + - csb226 board: fix MDREFR handling + - misc doc fixes / extensions + - innokom board: cleanup, MDREFR fix in memsetup.S, config update + - add BOOT_PROGRESS to armlinux.c -commit 6eb1df835191d8ce4b81d5af40fa8e0fbe78e997 -Author: Jon Loeliger -Date: Tue Dec 12 11:02:20 2006 -0600 +* Add CPU ID, version, and clock speed for INCA-IP - Fix 8641HPCN problem with ld version 2.16 +* Patches by Dave Ellis, 18 Mar 2003 for SXNI855T board: + - fix SRAM and SDRAM memory sizing + - add status LED support + - add MAC address for second (SCC1) ethernet port - (Dot outside sections problem). +* Update default environment for TQM8260 board + +* Patch by Rick Bronson, 16 Mar 2003: + - Add NAND flash support for reading, writing, and erasing NAND + flash (certain forms of which are called SmartMedia). + - Add support for Atmel AT91RM9200DK ARM920T based development kit. + +* Patches by Robert Schwebel, 19 Mar 2003: + - use arm-linux-gcc as default compiler for ARM + - fix i2c fixup code + - fix missing baudrate setting + - added $loadaddr / CFG_LOAD_ADDR support to loadb + - moved "ignoring trailing characters" _before_ u-boot wants to + print out diagnostics messages; removes bogus characters at the + end of transmission + +* Patch by John Zhan, 18 Mar 2003: + Add support for SinoVee Microsystems SC8xx boards + +* Patch by Rolf Offermanns, 21 Mar 2003: + ported the dnp1110 related changes from the current armboot cvs to + current u-boot cvs. smc91111 does not work. problem marked in + smc91111.c, grep for "FIXME". + +* Patch by Brian Auld, 25 Mar 2003: + Add support for STM flash chips on ebony board + +* Add PCI support for MPC8250 Boards (PM825 module) + +* Patch by Stefan Roese, 25 Mar 2003: + - PCI405 update. + +* Patch by Stefan Roese, 20 Mar 2003: + - CPCI4052 update (support for revision 3). + - Set edge conditioning circuitry on PPC405GPr for compatibility + to existing PPC405GP designs. + - Clip udiv to 5 bits on PPC405 (serial.c). + +* Extend INCAIP board support: + - add automatic RAM size detection + - add "bdinfo" command + - pass flash address and size to Linux kernel + - switch to 150 MHz clock + +* Avoid flicker on the TRAB's VFD by synchronizing the enable with + the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100 + boards, version 153 for Rev. 200 boards). + +* Patch by Vladimir Gurevich, 12 Mar 2003: + Fix relocation problem of statically initialized string pointers + in common/cmd_pci.c + +* Patch by Kai-Uwe Blöm, 12 Mar 2003: + Cleanup & bug fixes for JFFS2 code: + - the memory mangement was broken. It caused havoc on malloc by + writing beyond the block boundaries. + - the length calculation for files was wrong, sometimes resulting + in short file reads. + - data copying now optionally takes fragment version numbers into + account, to avoid copying from older data. + See doc/README.JFFS2 for details. + +* Patch by Josef Wagner, 12 Mar 2003: + - 16/32 MB and 50/80 MHz support with auto-detection for IP860 + - ETH05 and BEDBUG support for CU824 + - added support for MicroSys CPC45 + - new BOOTROM/FLASH0 and DOC base for PM826 + +* Patch by Robert Schwebel, 12 Mar 2003: + Fix the chpart command on innokom board + +* Name cleanup: + mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h + s/PPCBoot/U-Boot/ in some files + s/pImage/uImage/ in some files + +* Patch by Detlev Zundel, 15 Jan 2003: + Fix '' command line quoting + +* Patch by The LEOX team, 19 Jan 2003: + - add support for the ELPT860 board + - add support for Dallas ds164x RTC + +* Patches by David Müller, 31 Jan 2003: + - minimal setup for CardBus bridges + - add EEPROM read/write support in the CS8900 driver + - add support for the builtin I2C controller in the Samsung s3c24x0 chips + - add support for MPL's VCMA9 (Samsung s3c2410 based) board + +* Patch by Steven Scholz, 04 Feb 2003: + add support for RTC DS1307 - This fix is in the spirit of 807d5d7319330e336ab34a5623c5e0d73b87d540. +* Patch by Reinhard Meyer, 5 Feb 2003: + fix PLPRCR/SCCR init sequence on 8xx to allow for + changes of EBDF by software + +* Patch by Vladimir Gurevich, 07 Feb 2003: + "API-compatibility patch" for 4xx I2C driver - Signed-off-by: Jon Loeliger +* TRAB fixes / extensions: + - Restore VFD brightness as saved in environment + - add support for Fujitsu flashes + - make sure both buzzers are turned off (drive low level) -commit 9964a4dd0d4ef5a037febaebf1aa494b1a72991c -Author: Haiying Wang -Date: Thu Dec 7 10:35:55 2006 -0600 +* Patches by Robert Schwebel, 06 Mar 2003: + - fix bug in BOOTP code (must use NetCopyIP) + - update of CSB226 port + - clear BSS segment on XScale + - added support for i2c_init_board() function + - update to the Innokom plattform - Set Rev 2.x 86xx PIC in mixed mode. +* Extend support for redundand environments for configurations where + environment size < sector size - Prevent false interrupt from hanging Linux as MSR[EE] is set - to enable interrupts by changing the PIC out of the default - pass through mode into mixed mode. +* Patch by Rune Torgersen, 13 Feb 2003: + Add support for Motorola MPC8266ADS board - Signed-off-by: Haiying Wang - Signed-off-by: Jon Loeliger +* Patch by Kyle Harris, 19 Feb 2003: + patches for the Intel lubbock board: + memsetup.S - general cleanup (based on Robert's csb226 code) + flash.c - overhaul, actually works now + lubbock.c - fix init funcs to return proper value -commit 5a58a73ceb0a4059c42ef64cedbc1a45e0aaa00e -Author: Jason Jin -Date: Thu Dec 7 10:32:35 2006 -0600 +* Patch by Kenneth Johansson, 26 Feb 2003: + - Fixed off by one in RFTA calculation. + - No need to abort when LDF is lower than we can program it's only + minimum timing so clamp it to what we can do. + - Takes function pointer to function for reading the spd_nvram. Usefull + for faking data or hardcode a module without the nvram. + - fix other user for above change + - fix some comments. - Add flash cmd function to 8641HPCN ramboot +* Patches by Brian Waite, 26 Feb 2003: + - fix port for evb64260 board + - fix PCI for evb64260 board + - fix PCI scan - Also fixes some commmand for 8641 HPCN ramboot case. +* Patch by Reinhard Meyer, 1 Mar 2003: + Add support for EMK TOP860 Module - Signed-off-by: Jason Jin - Signed-off-by: Jon Loeliger +* Patch by Yuli Barcohen, 02 Mar 2003: + Add SPD EEPROM support for MPC8260ADS board -commit 2ccceacc04b009d923afb7c26189ba2f8a2a5d46 -Author: Ed Swarthout -Date: Thu Dec 7 10:34:14 2006 -0600 +* Patch by Robert Schwebel, 21 Jan 2003: + - Add support for Innokom board + - Don't complain if "install" fails + - README cleanup (remove duplicated lines) + - Update PXA header files - Add support for 8641 Rev 2 silicon. +* Add documentation for existing POST code (doc/README.POST) - Without this patch, I am unable to get to the prompt on rev 2 silicon. - Only set ddrioovcr for rev1. +* Patch by Laudney Ren, 15 Jan 2003: + Fix handling of redundand environment in "tools/envcrc.c" - Signed-off-by: Ed Swarthout - Signed-off-by: Jon Loeliger +* Patch by Detlev Zundel, 28 Feb 2003: + Add bedbug support for 824x systems -commit 44ba464b99001f8bd1c456a1e9d59726252f707a -Author: Wolfgang Denk -Date: Thu Mar 22 00:13:12 2007 +0100 +* Add support for 16 MB flash configuration of TRAB board - Code cleanup / re-insert previous Copyright entries. +* Patch by Erwin Rol, 27 Feb 2003: + Add support for RTEMS - Signed-off-by: Wolfgang Denk +* Add image information to README -commit 2a8dfe08359a1b663418b2faa1da1d7bce34d302 -Author: Wolfgang Denk -Date: Wed Mar 21 23:26:15 2007 +0100 +* Patch by Stefan Roese, 18 Feb 2003: + CPCIISER4 configuration updated. - Code cleanup. Update CHANGELOG +* Patch by Stefan Roese, 17 Feb 2003: + Fixed bug in ext. serial clock setup on PPC405 (since PPC440 port). -commit e6615ecf4eaf4dd52696934aed8f5c6474cfd286 -Author: Stefan Roese -Date: Wed Mar 21 14:54:29 2007 +0100 +* Patch by Stefan Roese, 13 Feb 2003: + Add "pcidelay" environment variable (in ms, enabled via + CONFIG_PCI_BOOTDELAY). + PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after + RST# to respond to configuration cycles (33MHz -> 1s). - ppc4xx: Fix file mode of include/configs/acadia.h +* Fix dual PCMCIA slot support (when running with just one + slot populated) - Signed-off-by: Stefan Roese +* Add VFD type detection to trab board -commit d5f4614c9350d9333e575100fb250aab774d0258 -Author: Markus Klotzbuecher -Date: Wed Mar 21 14:41:46 2007 +0100 +* extend drivers/cs8900.c driver to synchronize ethaddr environment + variable with value in the EEPROM - SPC1920: fix small clock routing bug +* Patch by Stefan Roese, 10 Feb 2003: + Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c) - Signed-off-by: Markus Klotzbuecher +* Add support for MIPS32 4Kc CPUs -commit 16c0cc1c82081a493ab87c51980b28336ce1bce8 -Author: Stefan Roese -Date: Wed Mar 21 13:39:57 2007 +0100 +* Add support for INCA-IP Board - [PATCH] Add AMCC Acadia (405EZ) eval board support +====================================================================== +Changes for U-Boot 0.2.2: +====================================================================== - This patch adds support for the new AMCC Acadia eval board. +* Add dual ethernet support on PM826 - Please note that this Acadia/405EZ support is still in a beta stage. - Still lot's of cleanup needed but we need a preliminary release now. +* Add support for LXT971 PHY on PM826 - Signed-off-by: Stefan Roese +* Patch by Tord Andersson, 16 Jan 2003: + Fix flash sector count for TQM8xxL -commit e01bd218b00af73499331a1a701625a852cd286f -Author: Stefan Roese -Date: Wed Mar 21 13:38:59 2007 +0100 +* Fix I2C EEPROM problem on ICU862 board (would only write the first + 16 bytes out of each 32 byte block) - [PATCH] Add AMCC PPC405EZ support +====================================================================== +Changes for U-Boot 0.2.1: +====================================================================== - This patch adds support for the new AMCC 405EZ PPC. It is in - preparation for the AMCC Acadia board support. +* Add support for V37 board + (patch by Jón Benediktsson, 11 Dec 2002) - Please note that this Acadia/405EZ support is still in a beta stage. - Still lot's of cleanup needed but we need a preliminary release now. +* Update baudrate in bd_info when it gets changed - Signed-off-by: Stefan Roese +* Add watchdog trigger points while waiting for serial port + (so far only 8xx -- needed on LWMON with 100ms watchdog) -commit 07e82cb2e284a893df6693f2a1337ab2c47bf6a1 -Author: Heiko Schocher -Date: Wed Mar 21 08:45:17 2007 +0100 +* Improve command line tool to access the U-Boot's environment + (figuration of the utility, using a config file) - [PATCH] TQM8272: dont change the bits given from the HRCW - for the SIUMCR and BCR Register. - Fix the calculation for the EEprom Size +* Add single quote support for (old) command line parser - Signed-off-by: Heiko Schocher +* Switch LWMON board default config from FRAM to EEPROM; + in POST, EEPROM shows up on 8 addresses -commit 654589873dbafcf104dff133ce0d03a4506e9cc3 -Author: Aubrey Li -Date: Tue Mar 20 18:16:24 2007 +0800 +====================================================================== +Changes for U-Boot 0.2.0: +====================================================================== - [Blackfin][PATCH] Add BF561 EZKIT board support +* Use 1-byte-read instead of -write for iprobe() function + Add i2c commands to PM826 config -commit a6154fd1cfd020f6da8527e0365b1020a11a71d0 -Author: Aubrey Li -Date: Mon Mar 19 22:55:58 2007 +0800 +* extend I2C POST code: check for list on known addresses - [Blackfin][PATCH] minor cleanup +* Improve log buffer code; use "loglevel" to decide which messages + to log on the console, too (like in Linux); get rid of "logstart" -commit 389b6bb50f745bf5038ce030300d8a8512e96f79 -Author: Wolfgang Denk -Date: Mon Mar 19 13:10:08 2007 +0100 +* Add command line tool to access the U-Boot's environment + (board-specific for TRAB now, to be fixed later) - Remove obsoleted POST files. +* Patch by Hans-Joerg Frieden, 06 Dec 2002 + Fix misc problems with AmigaOne support - Signed-off-by: Wolfgang Denk +* Patch by Chris Hallinan, 3 Dec 2002: + minor cleanup to the MPC8245 EPIC driver -commit 8e709bbb2636b5670a8f2b575e138eb1f55773f6 -Author: Aubrey Li -Date: Mon Mar 19 01:26:11 2007 +0800 +* Patch by Pierre Aubert , 28 Nov 2002 + Add support for external (SIU) interrupts on MPC8xx - [PATCH] Add flash chip M29W320ET/B support +* Patch by Pierre Aubert , 28 Nov 2002 + Fix nested syscalls bug in standalone applications -commit 26bf7deca364a5b33f39e8f14ddd3f4081345015 -Author: Aubrey Li -Date: Mon Mar 19 01:24:52 2007 +0800 +* Patch by David Müller, 27 Nov 2002: + fix output of "pciinfo" command for CardBus bridge devices. - [Blackfin][PATCH] Add BF537 stamp board support +* Fix bug in TQM8260 board detection - boards got stuck when board ID + was not readable -commit 8423e5e31a7235d05a482627315fb11d49c17bd7 -Author: Stefan Roese -Date: Fri Mar 16 21:11:42 2007 +0100 +* Add LED indication for IDE activity on KUP4K board - [PATCH] Use dynamic SDRAM TLB setup on AMCC Ebony eval board +* Fix startup problems with VFD display on TRAB - Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the - DDR memory are dynamically programmed matching the total size - of the equipped memory (DIMM modules). +* Patch by Pierre Aubert, 20 Nov 2002 + Add driver for Epson SED13806 graphic controller. + Add support for BMP logos in cfb_console driver. - Signed-off-by: Stefan Roese +* Added support for both PCMCIA slots (at the same time!) on MPC8xx -commit 76d1466f918b881cda2d259254761e73885093c2 -Author: Matthias Fuchs -Date: Tue Mar 13 13:38:05 2007 +0100 +* Patch by Rod Boyce, 21 Nov 2002: + fix PCMCIA on MBX8xx board - [PATCH] renamed environment variable 'addcon' to 'addcons' for PCI405 - boards in terms of unification. +* Patch by Pierre Aubert , 21 Nov 2002 + Add CFG_CPM_POST_WORD_ADDR to make the offset of the + bootmode word in DPRAM configurable - Signed-off-by: Matthias Fuchs +* Patch by Daniel Engström, 18 Nov 2002: + Fixes for x86 port (mostly strings issues) -commit a7090b993d3d4d2221ac3f33e6cb1d1b2ccc6bf0 -Author: Wolfgang Denk -Date: Tue Mar 13 16:05:55 2007 +0100 +* Patch by Ken Chou, 18 Nov 2002: + Fix for natsemi NIC cards (DP83815) - Make SC3 board build with 'make O='; use 'addcons' consistently - (SC3 and Jupiter used to use 'addcon' instead). +* Patch by Pierre Aubert, 19 Nov 2002: + fix a bug for the MII configuration, and some warnings - Signed-off-by: Wolfgang Denk wd@denx.de +* Patch by Thomas Frieden, 13 Nov 2002: + Add code for AmigaOne board + (preliminary merge to U-Boot, still WIP) -commit 8502e30a28e492c756ea2d7df0ace026388fce4b -Author: Heiko Schocher -Date: Tue Mar 13 09:40:59 2007 +0100 +* Patch by Jon Diekema, 12 Nov 2002: + - Adding URL for IEEE OUI lookup + - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED + being defined. + - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and + root-on-nfs macros are designed to switch how the default boot + method gets defined. - [PATCH] update board config for jupiter Board: - added Hush Shell, - CONFIG_CMDLINE_EDITING, - CFG_ENV_ADDR_REDUND activated +* Patch by Daniel Engström, 13 Nov 2002: + Add support for i386 architecture and AMD SC520 board - Signed-off-by: Heiko Schocher +* Patch by Pierre Aubert, 12 Nov 2002: + Add support for DOS filesystem and booting from DOS floppy disk -commit 0d93de11449390a5984b0236c3612e50f6dbb7e8 -Author: Aubrey Li -Date: Mon Mar 12 12:11:55 2007 +0800 +* Patch by Jim Sandoz, 07 Nov 2002: + Increase number of network RX buffers (PKTBUFSRX in + "include/net.h") for EEPRO100 based boards (especially SP8240) + which showed "Receiver is not ready" errors when U-Boot was + processing the receive buffers slower than the network controller + was filling them. - [Blackfin][PATCH] minor cleanup +* Patch by Andreas Oberritter, 09 Nov 2002: + Change behaviour of NetLoop(): return -1 for errors, filesize + otherwise; return code 0 is valid an means no file loaded - in this + case the environment still gets updated! -commit bfa5754a58477ac917d21527cd0f079d87cf188e -Author: Aubrey Li -Date: Mon Mar 12 01:42:06 2007 +0800 +* Patches by Jon Diekema, 9 Nov 2002: + - improve ADC/DAC clocking on the SACSng board to align + the failing edges of LRCLK and SCLK + - sbc8260 configuration tweaks + - add status LED support for 82xx systems + - wire sspi/sspo commands into command handler; improved error + handlering + - add timestamp support and alternate memory test to the + SACSng configuration - [Blackfin][PATCH] Fix BUILD_DIR option of MAKEALL building issue +* Patch by Vince Husovsky, 7 Nov 2002: + Add "-n" to linker options to get rid of "Not enough room for + program headers" problem -commit 8440bb14581a294375c34b91b42512f9753d1130 -Author: Aubrey Li -Date: Mon Mar 12 00:25:14 2007 +0800 +* Patch by David Müller, 05 Nov 2002 + Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ + so we can use an already existing name - [Blackfin][PATCH] code cleanup +* Patch by Pierre Aubert, 05 Nov 2002 + Hardware relatied improvments in FDC boot code -commit cfc67116a706fd18b8f6a9c11a16753c5626d689 -Author: Michal Simek -Date: Sun Mar 11 13:48:24 2007 +0100 +* Patch by Holger Schurig, 5 Nov 2002: + Make the PXA really change it's frequency - [Microblaze][PATCH] part 2 - timer support - interrupt controller support - flash support - ethernet support - cache support - board information support - env support - booting image support +* Patch by Pierre Aubert, 05 Nov 2002 + Add support for slave serial Spartan 2 FPGAs - adding support for Xilinx ML401 +* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet + drivers -commit 76316a318de91f6184e7c22a10e02d275ade2441 -Author: Michal Simek -Date: Sun Mar 11 13:42:58 2007 +0100 +* Add support for log buffer which can be passed to Linux kernel's + syslog mechanism; used especially for POST results. - [Microblaze][PATCH] - timer support - interrupt controller support - flash support - ethernet support - cache support - board information support - env support - booting image support +* Patch by Klaus Heydeck, 31 Oct 2002: + Add initial support for kup4k board - adding support for Xilinx ML401 +* Patch by Robert Schwebel, 04 Nov 2002: + - use watchdog to reset PXA250 systems + - added progress callbacks to (some of the) ARM code + - update for Cogent CSB226 board -commit 8db13d63157811c839d15a313d9f2d2f5fd10af3 -Author: Aubrey Li -Date: Sat Mar 10 23:49:29 2007 +0800 +* Add support for FPS860 board - [Blackfin][PATCH] code cleanup +* Patch by Guillaume Alexandre,, 04 Nov 2002: + Improve PCI access on 32-bits Compact PCI bus -commit ef26a08fef928b7bc11ae2c109e638dc3a016d91 -Author: Aubrey.Li -Date: Fri Mar 9 13:40:56 2007 +0800 +* Fix mdelay() on TRAB - this was still the debugging version with + seconds instead of ms. - [Blackfin][PATCH-2/2] Common files changed to support bf533 platform +* Patch by Robert Schwebel, 1 Nov 2002: + XScale related cleanup (affects all ARM boards) -commit 3f0606ad0b5639f7f22848fe5b4574e754d0470f -Author: Aubrey.Li -Date: Fri Mar 9 13:38:44 2007 +0800 +* Cleanup of names and README. - [Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform support +====================================================================== +Notes for U-Boot 0.1.0: +====================================================================== -commit 992423ab43c2bcf6b704853bd00af77450915e20 -Author: Stefan Roese -Date: Thu Mar 8 23:00:08 2007 +0100 +This is the initial version of "Das U-Boot", the Universal Boot Loader. - ppc4xx: Fix file mode of sequoia.c +It is based on version 2.0.0 (the "Halloween Release") of PPCBoot. +For information about the history of the project please see the +PPCBoot project page at http://sourceforge.net/projects/ppcboot - Signed-off-by: Stefan Roese - -commit eb92f613556800f7483666db09d9a237ad911d4a -Author: Wolfgang Denk -Date: Thu Mar 8 22:52:51 2007 +0100 - - Minor cleanup. - -commit 8ce16f55c7b9752af3d8bed84521aec5337e2de1 -Author: John Otken john@softadvances.com -Date: Thu Mar 8 09:39:48 2007 -0600 - - ppc4xx: Clear Sequoia/Rainier security engine reset bits - - Signed-off-by: John Otken john@softadvances.com - -commit 650a330dd2539130c8c324791e2f9f75aed79d4e -Author: Matthias Fuchs -Date: Thu Mar 8 16:26:52 2007 +0100 - - [PATCH] I2C: add some more SPD eeprom decoding for DDR2 modules - - Signed-off-by: Matthias Fuchs - -commit d9fc703246840c4b268debf48c334ba55c597dc0 -Author: Matthias Fuchs -Date: Thu Mar 8 16:25:47 2007 +0100 - - [PATCH] I2C: disable flat i2c commands when CONFIG_I2C_CMD_TREE is defined - - Signed-off-by: Matthias Fuchs - -commit ced5b9029043397348cdc88e0cfcd6b1f629250b -Author: Matthias Fuchs -Date: Thu Mar 8 16:23:11 2007 +0100 - - [PATCH] 4xx: allow CONFIG_I2C_CMD_TREE without CONFIG_I2C_MULTI_BUS - - Signed-off-by: Matthias Fuchs - -commit d8a8ea5c476d37006fc7f85b7f903142795c8b14 -Author: Matthias Fuchs -Date: Thu Mar 8 16:20:32 2007 +0100 - - [PATCH] I2C: Add missing default CFG_SPD_BUS_NUM - - Signed-off-by: Matthias Fuchs - -commit f9fc6a5852a6335840882fa2111925010eea1abe -Author: Matthias Fuchs -Date: Wed Mar 7 15:32:01 2007 +0100 - - fixed ethernet phy configuration for plu405 board - - Signed-off-by: Matthias Fuchs - -commit 769104c9356594deb2092e204a39c05b33202d6c -Author: Wolfgang Denk -Date: Thu Mar 8 21:49:27 2007 +0100 - - Minor cleanup - -commit 00cdb4ce5e1b42248e7e6522ad0da3421b988afa -Author: Stefan Roese -Date: Thu Mar 8 10:13:16 2007 +0100 - - [PATCH] Update AMCC Luan 440SP eval board support - - The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR - inititializition. This includes DDR auto calibration and support - for different DIMM modules, instead of the fixed setup used in - the earlier version. - - This patch also enables the cache in FLASH for the startup - phase of U-Boot (while running from FLASH). After relocating to - SDRAM the cache is disabled again. This will speed up the boot - process, especially the SDRAM setup, since there are some loops - for memory testing (auto calibration). - - Signed-off-by: Stefan Roese - -commit 2f5df47351910a2936c7741cf111855829200943 -Author: Stefan Roese -Date: Thu Mar 8 10:10:18 2007 +0100 - - [PATCH] Update AMCC Yucca 440SPe eval board support - - The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR - inititializition. This includes DDR auto calibration and support - for different DIMM modules, instead of the fixed setup used in - the earlier version. - - Signed-off-by: Stefan Roese - -commit 2721a68a9ea91f1e494649ce68b2577261f578e2 -Author: Stefan Roese -Date: Thu Mar 8 10:07:18 2007 +0100 - - ppc4xx: Small AMCC Katmai 440SPe update - - Signed-off-by: Stefan Roese - -commit df294497479b1dca6dd86318b2a912f72fede0df -Author: Stefan Roese -Date: Thu Mar 8 10:06:09 2007 +0100 - - ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SP - - Signed-off-by: Stefan Roese - -commit 83853178bd36bca6f0f8f1331476620c84a587fc -Author: Ed Swarthout -Date: Wed Mar 7 12:14:50 2007 -0600 - - net - Support ping reply when processing net-loop - - Add ICMP_ECHO_REQUEST packet support by responding with a ICMP_ECHO_REPLY. - - This permits the ping command to test the phy interface when the phy - is put in loopback mode (typically by setting register 0 bit 14). - - It also allows the port to respond to an external ping when u-boot is - processing some other net command (such as tftp). This is useful when - tftp appears to hang. - - Signed-off-by: Ed Swarthout - Signed-off-by: Ben Warren - -commit fa1aef15bcd47736687be1af544506e90fba545d -Author: Stefan Roese -Date: Wed Mar 7 16:43:00 2007 +0100 - - [PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval board - - Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the - DDR memory are dynamically programmed matching the total size - of the equipped memory (DIMM modules). - - Signed-off-by: Stefan Roese - -commit e2ebe696818939e2b974628be9c921ea3fe9de13 -Author: Stefan Roese -Date: Wed Mar 7 16:39:36 2007 +0100 - - [PATCH] Fix AMCC 44x SPD SDRAM init code to support 2 DIMM's - - This patch fixes a problem that occurs when 2 DIMM's are - used. This problem was first spotted and fixed by Gerald Jackson - but this patch fixes the - problem in a little more clever way. - - This patch also adds the nice functionality to dynamically - create the TLB entries for the SDRAM (tlb.c). So we should - never run into such problems with wrong (too short) TLB - initialization again on these platforms. - - As this feature is new to the "old" 44x SPD DDR driver, it - has to be enabled via the CONFIG_PROG_SDRAM_TLB define. - - Signed-off-by: Stefan Roese - -commit 39218433983417b9df087976a79e3f80dd5e83d6 -Author: Wolfgang Denk -Date: Wed Mar 7 16:33:44 2007 +0100 - - UC101: fix compiler warnings - -commit 8d7e2732221bc2d64df14f700c64c23e0a4c3dce -Author: Wolfgang Denk -Date: Wed Mar 7 16:19:46 2007 +0100 - - HMI1001: fix build error, cleanup compiler warnings. - -commit ad5bb451ade552c44bef9119d907929ebc2c126f -Author: Wolfgang Denk -Date: Tue Mar 6 18:08:43 2007 +0100 - - Restructure POST directory to support of other CPUs, boards, etc. - -commit a5284efd125967675b2e9c6ef7b95832268ad360 -Author: Wolfgang Denk -Date: Tue Mar 6 18:01:47 2007 +0100 - - Fix HOSTARCH handling. - Patch by Mike Frysinger, Mar 05 2007 - -commit 07b7b0037aac5102939917d7cbe561b5c0d5aa44 -Author: Stefan Roese -Date: Tue Mar 6 07:47:04 2007 +0100 - - [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup - - As provided by the AMCC applications team, this patch optimizes the - DDR2 setup for 166MHz bus speed. The values provided are also save - to use on a "normal" 133MHz PLB bus system. Only the refresh counter - setup has to be adjusted as done in this patch. - - For this the NAND booting version had to include the "speed.c" file - from the cpu/ppc4xx directory. With this addition the NAND SPL image - will just fit into the 4kbytes of program space. gcc version 4.x as - provided with ELDK 4.x is needed to generate this optimized code. - - Signed-off-by: Stefan Roese - -commit 647d3c3eed0da1d1505eecabe0b0fab96f956e68 -Author: Wolfgang Denk -Date: Sun Mar 4 01:36:05 2007 +0100 - - Some code cleanup. - -commit 781e026c8aa6f7e9eb5f0e72cc4d20971219b148 -Author: Kim Phillips -Date: Wed Feb 28 00:02:04 2007 -0600 - - mpc83xx: fix implicit declaration of function 'ft_get_prop' warnings - - (cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit) - -commit 4feab4de7bfc2cb2fed36ad76f93c3a69659bbaf -Author: Kumar Gala -Date: Tue Feb 27 23:51:42 2007 -0600 - - mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode - - The config value for: - * CFG_ACR_PIPE_DEP - * CFG_ACR_RPTCNT - * CFG_SPCR_TSEC1EP - * CFG_SPCR_TSEC2EP - * CFG_SCCR_TSEC1CM - * CFG_SCCR_TSEC2CM - - Were not being used when setting the appropriate register - - Added: - * CFG_SCCR_USBMPHCM - * CFG_SCCR_USBDRCM - * CFG_SCCR_PCICM - * CFG_SCCR_ENCCM - - To allow full config of the SCCR. - - Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 - that were just bogus. - - Signed-off-by: Kumar Gala - -commit d51b3cf371cd441030460ef19d36b2924c361b1a -Author: Kim Phillips -Date: Thu Feb 22 20:06:57 2007 -0600 - - mpc83xx: update [local-]mac-address properties on UEC based devices - - 8360 and 832x weren't updating their [local-]mac-address - properties. This patch fixes that. - - Signed-off-by: Kim Phillips - -commit 61f4f912acbe60776c5e00df1ec94094ce672957 -Author: Timur Tabi -Date: Tue Feb 13 10:41:42 2007 -0600 - - mpc83xx: write MAC address to mac-address and local-mac-address - - Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, this patch - updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. - This function already updates local-mac-address. - - Signed-off-by: Timur Tabi - -commit 22d71a71f57fd5d38b27ac3848e50d790360a598 -Author: Kim Phillips -Date: Tue Feb 27 18:41:08 2007 -0600 - - mpc83xx: add command line editing by default - -commit 3fc0bd159103b536e1c54c6f4457a09b3aba66ca -Author: Kim Phillips -Date: Wed Feb 14 19:50:53 2007 -0600 - - mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers - - Disable G1TXCLK, G2TXCLK h/w buffers. This patch - fixes a networking timeout issue with MPC8360EA (Rev.2) PBs. - - Verified on Rev. 1.1, Rev. 1.2, and Rev. 2.0 boards. - - Signed-off-by: Kim Phillips - Signed-off-by: Emilian Medve - -commit d61853cf2472e0b8bcbd131461a93d1c49ff0c1f -Author: Xie Xiaobo -Date: Wed Feb 14 18:27:17 2007 +0800 - - mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xx - - The code supply fixed and SPD initialization for MPC83xx DDR2 Controller. - it pass DDR/DDR2 compliance tests. - - Signed-off-by: Xie Xiaobo - -commit b110f40bd180c6b560276589beedf753e97c46ce -Author: Xie Xiaobo -Date: Wed Feb 14 18:27:06 2007 +0800 - - mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDS - - MPC8360E rev2.0 have new spridr,and PVR value, - The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM. - - Signed-off-by: Xie Xiaobo - -commit 8d172c0f0d85998a256a95b7459a5403a30380ed -Author: Xie Xiaobo -Date: Wed Feb 14 18:26:44 2007 +0800 - - mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDS - - MPC8349E rev3.1 have new spridr,and PVR value, - The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM. - - Signed-off-by: Xie Xiaobo - -commit f6f5f709e5c8e4564c4dfeecfdf2279244f9c83b -Author: Joakim Tjernlund -Date: Wed Jan 31 11:04:19 2007 +0100 - - mpc83xx: Fix empty i2c reads/writes in fsl_i2c.c - - Fix empty i2c reads/writes, i2c_write(0x50, 0x00, 0, NULL, 0) - which is used to se if an slave will ACK after receiving its address. - - Correct i2c probing to use this method as the old method could upset - a slave as it wrote a data byte to it. - - Add a small delay in i2c_init() to let the controller - shutdown any ongoing I2C activity. - - Signed-off-by: Joakim Tjernlund - -commit 7a78f148d6a7298e4fface680dc7eacd877b1aba -Author: Timur Tabi -Date: Wed Jan 31 15:54:29 2007 -0600 - - mpc83xx: Add support for the MPC8349E-mITX-GP - - Add support for the MPC8349E-mITX-GP, a stripped-down version of the - MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in - HRCW is 0) for the ITX and a README for the ITX and the ITX-GP. - - Signed-off-by: Timur Tabi - -commit fab16807adad350f618024350c6950165c247c72 -Author: Timur Tabi -Date: Wed Jan 31 15:54:20 2007 -0600 - - mpc83xx: Delete sdram_init() for MPC8349E-mITX - - There is no SDRAM on any of the 8349 ITX variants, so function sdram_init() - never does anything. This patch deletes it. - - Signed-off-by: Timur Tabi - -commit a87c856eb411b9365937d0d4b9c21e46adbe1c14 -Author: Dave Liu -Date: Fri Jan 19 10:43:26 2007 +0800 - - mpc83xx: Fix the LAW1/3 bug - - The patch solves the alignment problem of the local bus access windows to - render accessible the memory bank and PHY registers of UPC 1 (starting at - 0xf801 0000). What we actually did was to adjust the sizes of the bus - access windows so that the base address alignment requirement would be met. - - Signed-off-by: Chereji Marian - Signed-off-by: Gridish Shlomi - Signed-off-by: Dave Liu - -commit 97c4b397dce236a7318b304667bf89e59d08b17c -Author: Kim Phillips -Date: Tue Jan 30 16:15:31 2007 -0600 - - mpc83xx: don't hang if watchdog configured on 8360, 832x - - don't hang if watchdog configured on 8360, 832x - - The watchdog programming model is the same across all 83xx devices; - make the code reflect that. - -commit b70047478570e371ce7223be342ce98afea0f7d6 -Author: Kim Phillips -Date: Tue Jan 30 16:15:21 2007 -0600 - - mpc83xx: protect memcpy to bad address if a local-mac-address is missing from dt - - protect memcpy to bad address if a local-mac-address is missing from dt - -commit 6752ed088c75c26a89b70c46b7326a4cd6015f29 -Author: Kim Phillips -Date: Tue Jan 30 16:15:04 2007 -0600 - - mpc83xx: make 8360 default environment fdt be 8360 (not 8349) - - make 8360 default environment fdt be 8360 (not 8349) - -commit a28899c910024a0226331df07207b1038c300c93 -Author: Emilian Medve -Date: Tue Jan 30 16:14:50 2007 -0600 - - mpc83xx: Fix alternating tx error / tx buffer not ready bug in QE UEC - - The problem is not gcc4 but the code itself. The BD_STATUS() macro can't - be used for busy-waiting since it strips the 'volatile' property from - the bd variable. gcc3 was working by pure luck. - - This is a follow on patch to "Fix the UEC driver bug of QE" - -commit 3e78a31cfe3d3022f46f67eb88e1281d5cc2eb89 -Author: Kumar Gala -Date: Tue Jan 30 14:08:30 2007 -0600 - - mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X instead - - The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all - MPC834X class processors. Change the protections from CONFIG_MPC8349 to - CONFIG_MPC834X so they are more generic. - - Signed-off-by: Kumar Gala - -commit ae246dc6c1937c291014eadd90b6d48c438c7cb0 -Author: Kim Phillips -Date: Thu Jan 25 13:40:55 2007 -0600 - - mpc83xx: add MPC832XEMDS and sbc8349 to MAKEALL - -commit 4decd84e8f04279c5cfff7f8e907465ef8d8a3fb -Author: Kim Phillips -Date: Wed Jan 24 17:18:37 2007 -0600 - - mpc83xx: sort Makefile targets - - reordered targets alphabetically - -commit 91e25769771c1164ed63ffca0add49f934ae3343 -Author: Paul Gortmaker -Date: Tue Jan 16 11:38:14 2007 -0500 - - mpc83xx: U-Boot support for Wind River SBC8349 - - I've redone the SBC8349 support to match git-current, which - incorporates all the MPC834x updates from Freescale since the 1.1.6 - release, including the DDR changes. - - I've kept all the SBC8349 files as parallel as possible to the - MPC8349EMDS ones for ease of maintenance and to allow for easy - inspection of what was changed to support this board. Hence the SBC8349 - U-Boot has FDT support and everything else that the MPC8349EMDS has. - - Fortunately the Freescale updates added support for boards using CS0, - but I had to change spd_sdram.c to allow for board specific settings for - the sdram_clk_cntl (it is/was hard coded to zero, and that remains the - default if the board doesn't specify a value.) - - Hopefully this should be mergeable as-is and require no whitespace - cleanups or similar, but if something doesn't measure up then let me - know and I'll fix it. - - Thanks, - Paul. - -commit 05031db456ab227f3e3752f37b9b812b65bb83ad -Author: Sam Song -Date: Thu Dec 14 19:03:21 2006 +0800 - - mpc83xx: Remove a redundant semicolon in mpc8349itx.c - - A redundant semicolon existed in mpc8349itx.c - should be removed. - - Signed-off-by: Sam Song - -commit f35f358241c549be3f75cfe2eaa642914275b7ba -Author: Jerry Van Baren -Date: Wed Dec 6 21:23:55 2006 -0500 - - mpc83xx: Put the version (and magic) after the HRCW. - - Put the version (and magic) after the HRCW. This puts it in a fixed - location in flash, not at the start of flash but as close as we can get. - - Signed-off-by: Jerry Van Baren - -commit 48aecd969171a6e99a55fae04933857787f9a5bd -Author: Dave Liu -Date: Thu Dec 7 21:14:51 2006 +0800 - - mpc83xx: Add the MPC832XEMDS board readme - - Add the MPC832XEMDS board readme - - Signed-off-by: Dave Liu - -commit 24c3aca3f1358b113d3215adb5433b156e99f72b -Author: Dave Liu -Date: Thu Dec 7 21:13:15 2006 +0800 - - mpc83xx: Add support for the MPC832XEMDS board - - This patch supports DUART, ETH3/4 and PCI etc. - - Signed-off-by: Dave Liu - -commit e080313c32322e15ab5a18eb896a252858c57284 -Author: Dave Liu -Date: Thu Dec 7 21:11:58 2006 +0800 - - mpc83xx: streamline the 83xx immr head file - - For better format and style, I streamlined the 83xx head files, - including immap_83xx.h and mpc83xx.h. In the old head files, 1) - duplicated macro definition appear in the both files; 2) the structure - of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The - macro definition put inside the each structure. So, I cleaned up the - structure of QE immr from immap_83xx.h, deleted the duplicated stuff and - moved the macro definition to mpc83xx.h, Just like MPC8260. - - CHANGELOG - - *streamline the 83xx immr head file - - Signed-off-by: Dave Liu - -commit ddd02492f43db5408f5ab9f823b0ba5796e28ef0 -Author: Dave Liu -Date: Wed Dec 6 11:38:17 2006 +0800 - - mpc83xx: Fix the UEC driver bug of QE - - The patch prevents the GCC tool chain from striping useful code for - optimization. It will make UEC ethernet driver workable, Otherwise the - UEC will fail in tx when you are using gcc4.x. but the driver can work - when using gcc3.4.3. - - CHANGELOG - - *Prevent the GCC from striping code for optimization, Otherwise the UEC - will tx failed when you are using gcc4.x. - - Signed-off-by: Dave Liu - -commit ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35 -Author: Stefan Roese -Date: Thu Mar 1 21:11:36 2007 +0100 - - [PATCH] Update AMCC Katmai 440SPe eval board support - - This patch updates the recently added Katmai board support. The biggest - change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2 - driver. - - Please note, that still some problems are left with some memory - configurations. See the driver for more details. - - Signed-off-by: Stefan Roese - -commit 8c12045a3b06c5b6675d3fe02fbc9f545988129a -Author: Stefan Roese -Date: Thu Mar 1 07:03:25 2007 +0100 - - [PATCH] I2C: Add missing default CFG_RTC_BUS_NUM & CFG_DTT_BUS_NUM - - Signed-off-by: Stefan Roese - -commit ccbc7036648e465697ca298ba51e0e76dda352a0 -Author: Wolfgang Denk -Date: Wed Feb 28 01:28:53 2007 +0100 - - SC3: fix typo in default environment - -commit e344568b1b46af85ec32d815586f91bc115d6223 -Author: Sergei Poselenov -Date: Tue Feb 27 20:15:30 2007 +0300 - - MCC200: Fixes for update procedure - - - fix logic error in image type handling - - make sure file system images (cramfs etc.) get stored in flash - with image header stripped so they can be mounted through MTD - -commit 743571145b37182757d4e688a77860b36ee77573 -Author: Wolfgang Denk -Date: Tue Feb 27 14:26:04 2007 +0100 - - Minor code cleanup. - -commit 638dd1458bbdc2a55d4b9e25c5c4e1f838a5dc72 -Author: Sergei Poselenov -Date: Tue Feb 27 12:40:16 2007 +0300 - - MCC200 update - add LCD Progress Indicator - -commit 6c7cac8c4fce0ea2bf8e15ed8658d87974155b44 -Author: Stefan Roese -Date: Thu Feb 22 07:43:34 2007 +0100 - - [PATCH] get_dev() now unconditionally uses manual relocation - - Since the relocation fix is not included yet and we're not sure how - it will be added, this patch removes code that required relocation - to be fixed for now. - - Signed-off-by: Stefan Roese - -commit 8274ec0bd01d2feb2c7f095eba78d42ea009798b -Author: Stefan Roese -Date: Thu Feb 22 07:40:23 2007 +0100 - - [PATCH] Change systemace driver to select 8 & 16bit mode - - As suggested by Grant Likely this patch enables the Xilinx SystemACE - driver to select 8 or 16bit mode upon startup. - - Signed-off-by: Stefan Roese - -commit 3a197b2fe49d6fa03978e60af2394efe9c70b527 -Author: Haiying Wang -Date: Wed Feb 21 16:52:31 2007 +0100 - - [PATCH v3] Add sync to ensure flash_write_cmd is fully finished - - Some CPUs like PPC, BLACKFIN need sync() to ensure cfi flash write command - is fully finished. The sync() is defined in each CPU's io.h file. For - those CPUs which do not need sync for now, a dummy sync() is defined in - their io.h as well. - - Signed-off-by: Haiying Wang - -commit da04995c7dc6772013a9a0dc5c767f190c402478 -Author: Stefan Roese -Date: Wed Feb 21 13:44:34 2007 +0100 - - [PATCH] Fix problem in systemace driver (ace_writew instead of ace_write) - - Signed-off-by: Stefan Roese - -commit 751bb57107d78978ae08e697c3deba816f5be091 -Author: Stefan Roese -Date: Tue Feb 20 13:21:57 2007 +0100 - - [PATCH] Fix relocation problem with "new" get_dev() function - - This patch enables the "new" get_dev() function for block devices - introduced by Grant Likely to be used on systems that still suffer - from the relocation problems (manual relocation neede because of - problems with linker script). - - Hopefully we can resolve this relocation issue soon for all platform - so we don't need this additional code anymore. - - Signed-off-by: Stefan Roese - -commit d93e2212f962668b3dce091ff5edc33f2347fe37 -Author: Stefan Roese -Date: Tue Feb 20 13:17:42 2007 +0100 - - [PATCH] Update SystemACE driver for 16bit access - - This patch removes some problems when the Xilinx SystemACE driver - is used with 16bit access on an big endian platform (like the - AMCC Katmai). - - Signed-off-by: Stefan Roese - -commit 874bb7b88fe9b4648e1288a387af2e31014a72f3 -Author: Stefan Roese -Date: Tue Feb 20 13:15:40 2007 +0100 - - [PATCH] Clean up Katmai (440SPe) linker script - - Signed-off-by: Stefan Roese - -commit 4745acaa1a603b67f6b9b7970365ebadd7d6586f -Author: Stefan Roese -Date: Tue Feb 20 10:57:08 2007 +0100 - - [PATCH] Add support for the AMCC Katmai (440SPe) eval board - - Signed-off-by: Stefan Roese - -commit 0dc018ece13effc689e47479ea9ebf1c98a507f5 -Author: Stefan Roese -Date: Tue Feb 20 10:51:26 2007 +0100 - - [PATCH] I2C: Add support for multiple I2C busses for RTC & DTT - - This patch switches to the desired I2C bus when the date/dtt - commands are called. This can be configured using the - CFG_RTC_BUS_NUM and/or CFG_DTT_BUS_NUM defines. - - Signed-off-by: Stefan Roese - -commit 4037ed3b63923cfcec27f784a89057c3cbabcedb -Author: Stefan Roese -Date: Tue Feb 20 10:43:34 2007 +0100 - - [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM support - - This patch adds support for the DDR2 controller used on the - 440SP and 440SPe. It is tested on the Katmai (440SPe) eval - board and works fine with the following DIMM modules: - - - Corsair CM2X512-5400C4 (512MByte per DIMM) - - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) - - This patch also adds the nice functionality to dynamically - create the TLB entries for the SDRAM (tlb.c). So we should - never run into such problems with wrong (too short) TLB - initialization again on these platforms. - - Signed-off-by: Stefan Roese - -commit 36d830c9830379045f5daa9f542ac1c990c70068 -Author: Stefan Roese -Date: Tue Feb 20 10:35:42 2007 +0100 - - [PATCH] PPC4xx: Split 4xx SPD SDRAM init routines into 2 files - - Since the existing 4xx SPD SDRAM initialization routines for the - 405 SDRAM controller and the 440 DDR controller don't have much in - common this patch splits both drivers into different files. - - This is in preparation for the 440 DDR2 controller support (440SP/e). - - Signed-off-by: Stefan Roese - -commit 79b2d0bb2eae09602448f7a7cb56530d2f31e6c6 -Author: Stefan Roese -Date: Tue Feb 20 10:27:08 2007 +0100 - - [PATCH] PPC4xx: Add support for multiple I2C busses - - This patch adds support for multiple I2C busses on the PPC4xx - platforms. Define CONFIG_I2C_MULTI_BUS in the board config file - to make use of this feature. - - It also merges the 405 and 440 i2c header files into one common - file 4xx_i2c.h. - - Also the 4xx i2c reset procedure is reworked since I experienced - some problems with the first access on the 440SPe Katmai board. - - Signed-off-by: Stefan Roese - -commit eb867a76238fb38e952c37871b16d0d7fd61c95f -Author: Grant Likely -Date: Tue Feb 20 09:05:45 2007 +0100 - - [PATCH 9_9] Use "void *" not "unsigned long *" for block dev read_write buffer pointers - - Block device read/write is anonymous data; there is no need to use a - typed pointer. void * is fine. Also add a hook for block_read functions - - Signed-off-by: Grant Likely - -commit 53758fa20e935cc87eeb0519ed365df753a6f289 -Author: Grant Likely -Date: Tue Feb 20 09:05:38 2007 +0100 - - [PATCH 8_9] Add block_write hook to block_dev_desc_t - - Preparation for future patches which support block device writing - - Signed-off-by: Grant Likely - -commit f4852ebe6ca946a509667eb68be42026f837be76 -Author: Grant Likely -Date: Tue Feb 20 09:05:31 2007 +0100 - - [PATCH 7_9] Replace ace_readw_ace_writeb functions with macros - - Register read/write does not need to be wrapped in a full function. The - patch replaces them with macros. - - Signed-off-by: Grant Likely - -commit 3a8ce9af6fcb5744a7851b4440c07688acc40844 -Author: Grant Likely -Date: Tue Feb 20 09:05:23 2007 +0100 - - [PATCH 6_9] Move common_cmd_ace.c to drivers_systemace.c - - The code in this file is not a command; it is a device driver. Put it in - the correct place. There are zero functional changes in this patch, it - only moves the file. - - Signed-off-by: Grant Likely - -commit 984618f3e7794c783ec8d1511e74c6ee2d69bfe4 -Author: Grant Likely -Date: Tue Feb 20 09:05:16 2007 +0100 - - [PATCH 5_9] Whitespace fixup on common_cmd_ace.c (using Lindent) - - This patch is in preparation of additional changes to the sysace driver. - May as well take this opportunity to fixup the inconsistent whitespace since - this file is about to undergo major changes anyway. - - There are zero functional changes in this patch. It only cleans up the - the whitespace. - - Signed-off-by: Grant Likely - -commit 80ba981d940471fe7e539e64fa3d2bd80002beda -Author: Grant Likely -Date: Tue Feb 20 09:05:07 2007 +0100 - - [PATCH 4_4] Remove local implementation of isprint() in ft_build.c - - isprint is already defined in ctype.c - - Signed-off-by: Grant Likely - -commit c95c4280d751ca078c2ff58228d2f2b44ccf0600 -Author: Grant Likely -Date: Tue Feb 20 09:05:00 2007 +0100 - - [PATCH 3_9] Move buffer print code from md command to common function - - Printing a buffer is a darn useful thing. Move the buffer print code - into print_buffer() in lib_generic/ - - Signed-off-by: Grant Likely - -commit 99b0f0fd3fbf2572ae1a7723dd90cffc8e85130a -Author: Grant Likely -Date: Tue Feb 20 09:04:52 2007 +0100 - - [PATCH 2_4] Use config.h, not xparameters.h, for xilinx targets - - Change the xilinx device drivers and board code to include config.h - instead of xparameters.h directly. config.h always includes the - correct xparameters file. This change reduces the posibility of - including the wrong file when adding a new xilinx board port - - Signed-off-by: Grant Likely - -commit 735dd97b1b20e777d059c7b389fe9d70cd3f80c7 -Author: Grant Likely -Date: Tue Feb 20 09:04:34 2007 +0100 - - [PATCH 1_4] Merge common get_dev() routines for block devices - - Each of the filesystem drivers duplicate the get_dev routine. This change - merges them into a single function in part.c - - Signed-off-by: Grant Likely - -commit f5fcc3c20b65554e98a165542c36ee0c610a2d81 -Author: Wolfgang Denk -Date: Mon Feb 19 23:09:51 2007 +0100 - - MCC200: Software Updater: allow both "ramdisk" and "filesystem" types - as root file system images. - -commit 489c696ae7211218961d159e43e722d74c36fcbc -Author: Sergei Poselenov -Date: Wed Feb 14 14:30:28 2007 +0300 - - MCC200: Extensions to Software Update Mechanism - - Update / extend Software Update Mechanism for MCC200 board: - - - Add support for rootfs image added. The environment variables - "rootfs_st" and "rootfs_nd" can be used to override the default - values of the image start and end. - - Remove excessive key check code. - - Code cleanup. - -commit 4be23a12f23f1372634edc3215137b09768b7949 -Author: Stefan Roese -Date: Mon Feb 19 08:23:15 2007 +0100 - - [PATCH] Update Sequoia EBC configuration (NOR FLASH) - - As spotted by Matthias Fuchs, the READY input should not be - enabled for the NOR FLASH on the Sequoia board. - - Signed-off-by: Stefan Roese - -commit 2605e90bf676d48123afe5719a846d2b52b24aac -Author: Heiko Schocher -Date: Fri Feb 16 07:57:42 2007 +0100 - - [PATCH] Added support for the jupiter board. - - Signed-off-by: Heiko Schocher - -commit 497d012e5be0194e1084073d0081eb1a844796b2 -Author: Gary Jennejohn -Date: Mon Feb 12 13:11:50 2007 +0100 - - LPC2292: patch from Siemens. - -commit b0b1a920aebead0d44146e73676ae9d80fffc8e2 -Author: Stefan Roese -Date: Sat Feb 10 08:49:31 2007 +0100 - - [PATCH] Add missing p3mx.h file to repository (ups) - - Signed-off-by: Stefan Roese - -commit 53d4a4983fb9b3ae5f7b2f10c599aca2b1b4034a -Author: Bartlomiej Sieka -Date: Fri Feb 9 10:45:42 2007 +0100 - - [Motion-PRO] Preliminary support for the Motion-PRO board. - -commit 5a753f98c6a01bd1c61a9a3f95e8329a35f62994 -Author: Stefan Roese -Date: Wed Feb 7 16:51:08 2007 +0100 - - [PATCH] Update some AMCC 4xx board config files (set initrd_high) - - Some boards that can have more than 768MBytes of SDRAM need to - set "initrd_high", so that the initrd can be accessed by the - Linux kernel. - - Signed-off-by: Stefan Roese - -commit 7372ca68227930d03cffa548310524cad5b96733 -Author: Stefan Roese -Date: Fri Feb 2 12:44:22 2007 +0100 - - [PATCH] Correctly display PCI arbiter en-/disabled on some 4xx boards - - Previously the strapping DCR/SDR was read to determine if the internal PCI - arbiter is enabled or not. This strapping bit can be overridden, so now - the current status is read from the correct DCR/SDR register. - - Signed-off-by: Stefan Roese - -commit 2aa54f651a42d198673318f07a20c89a43e4d197 -Author: Stefan Roese -Date: Fri Feb 2 12:42:08 2007 +0100 - - [PATCH] Change configuration output of Sycamore, Yellowstone & Rainier - - Signed-off-by: Stefan Roese - -commit 23744d6b5bf17592eb6a0ef4f318f6089f55993b -Author: Stefan Roese -Date: Thu Feb 1 13:22:41 2007 +0100 - - [PATCH] Remove PCI-PNP configuration from Sequoia/Rainier config file - - When PCI PNP is enabled the pci pnp configuration routine is called - which sets the PCI_CACHE_SIZE_LINE to 8. This seems to generate some - problems with some PCI cards. For now disable the PCI PNP configuration. - - Signed-off-by: Stefan Roese - -commit 2902fadade3be7659467e8d074048c6b7068f5c0 -Author: Stefan Roese -Date: Wed Jan 31 16:56:10 2007 +0100 - - [PATCH] Update 440EPx/440GRx cpu detection - - Signed-off-by: Stefan Roese - -commit d5ea287b02a6945c3977410e364a879dd1a555c8 -Author: Stefan Roese -Date: Wed Jan 31 16:38:04 2007 +0100 - - [PATCH] Update esd cpci5200 files - - Signed-off-by: Reinhard Arlt - -commit 8b7d1f0ab7d7c4fe3160bbf74a7e9690d9f3a3ab -Author: Stefan Roese -Date: Wed Jan 31 16:37:34 2007 +0100 - - [PATCH] Add support for esd mecp5200 board - - Signed-off-by: Reinhard Arlt - -commit 71a4e5fda8b60044ab9f46069fa1cfa26bdd07ff -Author: Stefan Roese -Date: Wed Jan 31 12:38:50 2007 +0100 - - [PATCH] Remove unneccessary yellowstone board config file - - Signed-off-by: Stefan Roese - -commit e802594b6fa1b166308820c276b96dc0d7cc731c -Author: Stefan Roese -Date: Tue Jan 30 17:06:10 2007 +0100 - - [PATCH] Update Sequoia (440EPx) config file - - The config file now handles the 2nd target, the Rainier (440GRx) - evaluation board better. Additionally the PPC input clock was - adjusted to match the correct value of 33.0 MHz. - - Signed-off-by: Stefan Roese - -commit 700200c67e73b83751418abe7815840dca8fd6cb -Author: Stefan Roese -Date: Tue Jan 30 17:04:19 2007 +0100 - - [PATCH] Merge Yosemite & Yellowstone board ports - - Now the AMCC eval boards Yosemite (440EP) and Yellowstone (440GR) - share one config file and all board specific files. This way we - don't have to maintain two different sets of files for nearly - identical boards. - - Signed-off-by: Stefan Roese - -commit 1bbf5eae322f5f1f6427ecc3ac13a0cb7dba8ad6 -Author: Stefan Roese -Date: Tue Jan 30 15:01:49 2007 +0100 - - [PATCH] Update Prodrive SCPU (PDNB3 variant) board - - SCPU doesn't use redundant environment in flash. - - Signed-off-by: Stefan Roese - -commit 6304430ed642ea8fa15c9e5af965ac2e033eec45 -Author: Stefan Roese -Date: Tue Jan 30 12:51:07 2007 +0100 - - [PATCH] alpr: Update alpr board config file - - Signed-off-by: Stefan Roese - -commit f8db84f132b1e335f20f96138a1f09ed97b08664 -Author: Wolfgang Denk -Date: Tue Jan 30 00:50:40 2007 +0100 - - LPC2292 SODIMM port coding style cleanup. - -commit 6bd2447ee47ee23c18d2b3c7ccd5a20f7626f5b3 -Author: Gary Jennejohn -Date: Wed Jan 24 12:16:56 2007 +0100 - - Add port for the lpc2292sodimm evaluation board from EmbeddedArtists - -commit 2daf046ba627f85f44195815778140039636244e -Author: Bartlomiej Sieka -Date: Tue Jan 23 17:22:06 2007 +0100 - - [iDMR] Add MTD and JFFS2 support, also add default partition definition. - -commit f7db33101fbc9c8f0a10738ce87034875a17aeb9 -Author: Bartlomiej Sieka -Date: Tue Jan 23 14:21:14 2007 +0100 - - [iDMR] Flash driver on initialisation write-protects some sectors, - currently sectors 0-3. Sector 3 does not need to be protected, though - (U-boot occupies sectors 0-1 and the environment sector 2). This commit - fixes this, i.e., only sectors 0-2 are protected. - -commit 0ed47bb119cd2c4c16edb2548789148f9e6dc9de -Author: Bartlomiej Sieka -Date: Tue Jan 23 14:11:22 2007 +0100 - - [iDMR] Using MII-related commands on iDRM board doesn't work now (e.g., - "mii device" results in "Unexpected exception"). Fixing this properly - requires some clean-up in the FEC drivers infrastructure for ColdFire, so - this commit disables MII commads for now. - -commit 363d1d8f9c99b63daef81f5985cab3fc00edde5c -Author: Bartlomiej Sieka -Date: Tue Jan 23 13:25:22 2007 +0100 - - [ColdFire MCF5271 family] Add CPU detection based on the value of Chip - Identification Register (CIR). - -commit fdef388758506765d4d6a7155c8f1584c63ff581 -Author: roy zang -Date: Mon Jan 22 13:19:21 2007 +0800 - - use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP - The patch by Heiko Schocher on Jan, 19, 2007 - fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support - mpc7448hpc2 board. - -commit a4012396645533aef218354eeba754dff0deace8 -Author: Wolfgang Denk -Date: Fri Jan 19 23:08:39 2007 +0100 - - Minor code cleanup. - -commit f539b7ba7d7ef6dd187c8209609001cb1cd95e39 -Author: Heiko Schocher -Date: Fri Jan 19 19:57:10 2007 +0100 - - [PATCH] SC3 board: added CFG_CMD_AUTOSCRIPT. - - Signed-off-by: Heiko Schocher - -commit d0b6e14087ddd8789f224a48e1d33f2a5df4d167 -Author: Heiko Schocher -Date: Fri Jan 19 18:05:26 2007 +0100 - - [PATCH] CFI: define CFG_WRITE_SWAPPED_DATA for the CFI-Flash driver - if you must swap the bytes between reading/writing. - (Needed for the SC3 board) - - Signed-off-by: Heiko Schocher - -commit 9d8d5a5bfb64768f29a0cb47fc37cd6f4c40e276 -Author: Stefan Roese -Date: Thu Jan 18 16:05:47 2007 +0100 - - [PATCH] Add support for Prodrive SCPU (PDNB3 variant) board - - Signed-off-by: Stefan Roese - -commit 0057d758e3e874cbe7f24745d0cce8c1cb6c207e -Author: Stefan Roese -Date: Thu Jan 18 11:54:52 2007 +0100 - - [PATCH] Update Prodrive P3Mx support - - Signed-off-by: Stefan Roese - -commit 34167a36c29ee946b727465db5c014746a08e978 -Author: Stefan Roese -Date: Thu Jan 18 11:48:10 2007 +0100 - - [PATCH] Add missing Taishan config file - - Signed-off-by: Stefan Roese - -commit cb4820725e9fc409c5cbc8e83054a6ed522d2111 -Author: Heiko Schocher -Date: Thu Jan 18 11:28:51 2007 +0100 - - [PATCH] Fix: Compilerwarnings for SC3 board. - The EBC Configuration Register is now by CFG_EBC_CFG definable - Added JFFS2 support for the SC3 board. - - Signed-off-by: Heiko Schocher - -commit 5fb692cae57d1710c8f52a427cf7f39a37383fcd -Author: Stefan Roese -Date: Thu Jan 18 10:25:34 2007 +0100 - - [PATCH] Add support for AMCC Taishan PPC440GX eval board - - Signed-off-by: Stefan Roese - -commit 6d3e0107235aa0e6a6dcb77f9884497280bf85ad -Author: Wolfgang Denk -Date: Tue Jan 16 18:30:50 2007 +0100 - - Raname solidcard3 into sc3; add redundant env for sc3 - -commit 1bbbbdd20fcec9933697000dcf55ff7972622596 -Author: Wolfgang Denk -Date: Tue Jan 16 12:46:35 2007 +0100 - - Update default environment for Solidcard3 - -commit 5a5c56986a9ccf71642c8b6374eb18487b15fecd -Author: Stefan Roese -Date: Mon Jan 15 09:46:29 2007 +0100 - - [PATCH] Fix 440SPe rev B detection from previous patch - - Signed-off-by: Stefan Roese - -commit a443d31410c571ee8f970da819a44d698fdd6b1f -Author: Heiko Schocher -Date: Sun Jan 14 13:35:31 2007 +0100 - - [FIX] correct I2C Writes for the LM81 Sensor. - - Signed-off-by: Heiko Schocher - -commit 0bba5452835f19a61204edcda3a58112fd8e2208 -Author: Wolfgang Denk -Date: Sat Jan 13 11:17:10 2007 +0100 - - Undo commit 3033ebb2: reset command does not take any arguments - - Haiying Wang's modification to the reset command was broken, undo it. - - Signed-off-by: Wolfgang Denk - -commit 95981778cff0038fd9941044d6a3eda810e33258 -Author: Stefan Roese -Date: Sat Jan 13 08:01:03 2007 +0100 - - [PATCH] Update 440SP(e) cpu revisions - - Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's. - - Signed-off-by: Stefan Roese - -commit 77ddc5b9afb325262fd88752ba430a1dded1f0c7 -Author: Stefan Roese -Date: Sat Jan 13 07:59:56 2007 +0100 - - [PATCH] Update Yellowstone (440GR) to display board rev and PCI bus speed - - Now the board revision and the current PCI bus speed are printed after - the board message. - - Also the EBC initialising is now done via defines in the board config - file. - - Signed-off-by: Stefan Roese - -commit 36adff362c2c0141ff8a810d42a7e478f779130f -Author: Stefan Roese -Date: Sat Jan 13 07:59:19 2007 +0100 - - [PATCH] Update Yosemite (440EP) to display board rev and PCI bus speed - - Now the board revision and the current PCI bus speed are printed after - the board message. - - Also the EBC initialising is now done via defines in the board config - file. - - Signed-off-by: Stefan Roese - -commit e0b9ea8c8a294de6a5350ae638879d24b5b709d6 -Author: Stefan Roese -Date: Sat Jan 13 07:57:51 2007 +0100 - - [PATCH] Update Sequoia (440EPx) to display board rev and PCI bus speed - - Now the board revision and the current PCI bus speed are printed after - the board message. - - Signed-off-by: Stefan Roese - -commit ca43ba18e910206ef8063e4b22d282630bff3fd2 -Author: Heiko Schocher -Date: Thu Jan 11 15:44:44 2007 +0100 - - Added support for the SOLIDCARD III board from Eurodesign - - Signed-off-by: Heiko Schocher - -commit 6abaee42621c07e81a2cd189ad4368b5e8c50280 -Author: Reinhard Thies -Date: Wed Jan 10 14:41:14 2007 +0100 - - Adjusted default environment for cam5200 board. - -commit bab5a90d4ccc1a46a8127b867fa59028cc623ad9 -Author: Wolfgang Denk -Date: Wed Jan 10 15:35:52 2007 +0100 - - Update CHANGELOG - -commit 787fa15860a57833e50bd30555079a9cd4e519b8 -Author: Wolfgang Denk -Date: Wed Jan 10 01:28:39 2007 +0100 - - Fix auto_update for MCC200 board. - - The invocation of do_auto_update() is moved to the end of the - misc_init_r() function, after the flash mappings have been - initialized. Please find attached a patch that implements that - change. - - Also correct the decoding of the keypad status. With this update, the - key that will trigger the update is Column 2, Row 2. - -commit d9384de2f571046e71081bae22b49e3d5ca2e3d5 -Author: Marian Balakowicz -Date: Wed Jan 10 00:26:15 2007 +0100 - - CAM5200 flash driver modifications: - - use CFI driver (replaces custom flash driver) for main 'cam5200' target - - add second build target 'cam5200_niosflash' which still uses custom driver - -commit 67fea022fa957f59653b5238c7496f80a6b70432 -Author: Markus Klotzbuecher -Date: Tue Jan 9 16:02:48 2007 +0100 - - SPC1920: cleanup memory contoller setup - -commit 8fc2102faa23593c80381437c09f7745a14deb40 -Author: Markus Klotzbuecher -Date: Tue Jan 9 14:57:14 2007 +0100 - - Fix the cpu speed setup to work with all boards. - -commit 9295acb77481cf099ef9b40e1fa2d145b3c7490c -Author: Markus Klotzbuecher -Date: Tue Jan 9 14:57:13 2007 +0100 - - SPC1920: add support for the FM18L08 Ramtron FRAM - -commit 38ccd2fdf3364a53fe80e9b365303ecdafc9e223 -Author: Markus Klotzbuecher -Date: Tue Jan 9 14:57:13 2007 +0100 - - SPC1920: update the HPI register addresses to work with the second - generation of hardware - -commit 5921e5313fc3eadd42770c2b99badd7fae5ecf1e -Author: Markus Klotzbuecher -Date: Tue Jan 9 14:57:13 2007 +0100 - - Miscellanious spc1920 related cleanups - -commit e4c2d37adc8bb1bf69dcf600cbc6c75f916a6120 -Author: Markus Klotzbuecher -Date: Tue Jan 9 14:57:12 2007 +0100 - - SPC1920 GO/NOGO led should be set to color red in U-Boot - -commit 0be62728aac459ba268d6d752ed49ec0e2bc7348 -Author: Markus Klotzbuecher -Date: Tue Jan 9 14:57:12 2007 +0100 - - Add support for the DS3231 RTC - -commit 8139567b60d678584b05f0718a681f2047c5e14f -Author: Markus Klotzbuecher -Date: Tue Jan 9 14:57:11 2007 +0100 - - SMC1 uses external CLK4 instead of BRG on spc1920 - -commit d8d9de1a02fbd880b613d607143d1f57342affc7 -Author: Markus Klotzbuecher -Date: Tue Jan 9 14:57:10 2007 +0100 - - Update the SPC1920 CMB PLD driver - -commit 3f34f869162750e5e999fd140f884f5de952bcfe -Author: Markus Klotzbuecher -Date: Tue Jan 9 14:57:10 2007 +0100 - - Add / enable I2C support on the spc1920 board - -commit d28707dbce1e9ac2017ad051da4133bf22b4204f -Author: Markus Klotzbuecher -Date: Tue Jan 9 14:57:10 2007 +0100 - - Add support for the tms320671x host port interface (HPI) - -commit f4eb54529bb3664c3a562e488b460fe075f79d67 -Author: Wolfgang Denk -Date: Sun Jan 7 00:13:11 2007 +0100 - - Prepare for release 1.2.0 - -commit f07ae7a9daef27a3d0213a4f3fe39d5342173c02 -Author: Stefan Roese -Date: Sat Jan 6 15:58:09 2007 +0100 - - [PATCH] 44x: Fix problem with DDR controller setup (refresh rate) - - This patch fixes a problem with an incorrect setup for the refresh - timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c - - Signed-off-by: Stefan Roese - -commit f16c1da9577f06c5fc08651a4065537407de4635 -Author: Stefan Roese -Date: Sat Jan 6 15:56:13 2007 +0100 - - [PATCH] Update ALPR board files - - This update brings the ALPR board support to the newest version. - It also fixes a problem with the NAND driver. - - Signed-off-by: Stefan Roese - -commit cd1d937f90250a32988c37b2b4af8364d25de8ed -Author: Stefan Roese -Date: Fri Jan 5 11:46:05 2007 +0100 - - [PATCH] nand: Fix problem with oobsize calculation - - Here the description from Brian Brelsford : - - The Hynix part returns a 0x1d in the 4th ID byte. The Samsung part - returns a 0x15. In the code fragment below bits [1:0] determine the - page size, it is ANDed via "(extid & 0x3)" then shifted out. The - next field is also ANDed with 0x3. However this is a one bit field - as defined in the Hynix and Samsung parts in the 4th ID byte that - determins the oobsize, not a two bit field. It works on Samsung as - bits[3:2] are 01. However for the Hynix there is a 11 in these two - bits, so the oob size gets messed up. - - I checked the correct linux code and the suggested fix from Brian is - also available in the linux nand mtd driver. - - Signed-off-by: Stefan Roese - -commit a78bc443ae5a4a8ba87590587d5e35bf5a787b2e -Author: Stefan Roese -Date: Fri Jan 5 10:40:36 2007 +0100 - - [PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx) - - This fix will make the MAL burst disabling patch for the Linux - EMAC driver obsolete. - - Signed-off-by: Stefan Roese - -commit 023889838282b6237b401664f22dd22dfba2c066 -Author: Stefan Roese -Date: Fri Jan 5 10:38:05 2007 +0100 - - [PATCH] Add DDR2 optimization code for Sequoia (440EPx) board - - This code will optimize the DDR2 controller setup on a board specific - basis. - - Note: This code doesn't work right now on the NAND booting image for the - Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. - - Signed-off-by: Stefan Roese - -commit cce4acbb68398634b8d011ed7bb0d12269c84230 -Author: Bartlomiej Sieka -Date: Thu Dec 28 19:08:21 2006 +0100 - - Few V38B changes: - - fix a typo in V38B config file - - move watchdog initialisation earlier in the boot process - - add "wdt=off" to default kernel command line (disables kernel watchdog) - -commit 92eb729bad876725aeea908d2addba0800620840 -Author: Wolfgang Denk -Date: Wed Dec 27 01:26:13 2006 +0100 - - Fix bug in adaption of Stefano Babic's CFI driver patch. - -commit 9c0f42ecfe25f7ffce8ec7a815f03864d723ffe3 -Author: Wolfgang Denk -Date: Sun Dec 24 01:42:57 2006 +0100 - - Minor code cleanup. - -commit d784fdb05900ada3686d5778783e1fb328e9fb66 -Author: Stefano Babic -Date: Tue Dec 12 00:22:42 2006 +0100 - - Fix cfi failure with Spansion Flash (Spansion Flash Devices have a different offset to go into CFI mode) - -commit 1b3c360c235dc684ec06c2d5f183f0a282ce45e2 -Author: Stefan Roese -Date: Fri Dec 22 14:29:40 2006 +0100 - - [PATCH] Fix sequoia flash autodetection (finally correct) - - Now 32MByte and 64MByte FLASH is know to work and other - configurations should work too. - - Signed-off-by: Stefan Roese - -commit 82e5236a8b719543643fd26d5827938ab2b94818 -Author: Wolfgang Denk -Date: Fri Dec 22 10:30:26 2006 +0100 - - Minor code cleanup; update CHANGELOG. - -commit fa23044564091f05d9695beb7b5b9a931e7f41a4 -Author: Heiko Schocher -Date: Thu Dec 21 17:17:02 2006 +0100 - - Added support for the TQM8272 board from TQ - - Signed-off-by: Heiko Schocher - -commit 6dedf3d49dd14c3bf541c8ecee7ffaac5f0e1d6c -Author: Heiko Schocher -Date: Thu Dec 21 16:14:48 2006 +0100 - - [PATCH] Add support for the UC101 board from MAN. - - Signed-off-by: Heiko Schocher - -commit c84bad0ef60e7055ab0bd49b93069509cecc382a -Author: Bartlomiej Sieka -Date: Wed Dec 20 00:29:43 2006 +0100 - - Fix to make the baudrate changes immediate for the MCF52x2 family. - -commit daa6e418bcc0c717752e8de939c213c790286096 -Author: Bartlomiej Sieka -Date: Wed Dec 20 00:27:32 2006 +0100 - - Preliminary support for the iDMR board (ColdFire). - -commit cdb97a6678826f85e7c69eae6a1c113d034c9b10 -Author: Andrei Safronov -Date: Fri Dec 8 16:23:08 2006 +0100 - - automatic update mechanism - -commit 9d27b3a0685ff99fc477983f315c04d49f657a8a -Author: roy zang -Date: Mon Dec 4 17:56:59 2006 +0800 - - Slight code clean up. - Add comments, delete duplicate define and remove spaces. - Signed-off-by: Roy Zang - -commit 4dbcd69e3e2776ea334590d5768e3692c5fae5c1 -Author: roy zang -Date: Mon Dec 4 17:54:21 2006 +0800 - - Introduce PLL_CFG[0:4] table for processor 7448/7447A/7455/7457. The original - multiplier table can not refect the real PLL clock behavior of these - processors. Please refer to the hardware specification for detailed - information of the corresponding processors. - Signed-off-by: Roy Zang - -commit 4efe20c9579011d9987f62ed7d35ee8cdc1cf0e0 -Author: roy zang -Date: Mon Dec 4 14:46:23 2006 +0800 - - Remove the static MAC address, ip address, server ip, netmask and - gateway ip for network setting. - Signed-off-by: Roy Zang - -commit 6f12c61cf31ed73d72ddfcfc712a854a3a177aaf -Author: roy zang -Date: Mon Dec 4 14:33:08 2006 +0800 - - Remove the duplicate memory test code for mpc744ihpc2 board. - If a memory test is needed, please use the functions in - post/memory.c or memtest command. - Signed-off-by: Roy Zang - -commit c9c1eeed7dd193fa65fb194654132040d49d4d3a -Author: roy zang -Date: Fri Dec 1 19:01:25 2006 +0800 - - Fix the exception occuring in RAM table search issue. - The original search_one_table() function code can only processes the search - for the exception occurring in FLASH/ROM, because the exception and fixup - table usually locate in FLASH. If the exception address is also in - FLASH, it will be OK. - If the exception occurs in RAM, after the u-boot relocation, a - relocation offset should be added. - - clean up the code in cpu/74xx_7xx/cpu.c - - Signed-off-by: Roy Zang - -commit ee311214e0d216f904feea269599d0934bf71f23 -Author: roy zang -Date: Fri Dec 1 11:47:36 2006 +0800 - - Clean up the code according to codestyle: - (1) remove some C++ comments. - (2) remove trailing white space. - (3) remove trailing empty line. - (4) Indentation by table. - (5) remove {} in one line condition. - (6) add space before '(' in function call. - Remove some weird printf () output. - Add necessary comments. - Modified Makefile to support building in a separate directory. - -commit dd520bf314c7add4183c5191692180f576f96b60 -Author: Wolfgang Denk -Date: Thu Nov 30 18:02:20 2006 +0100 - - Code cleanup. - -commit 8d9a8610b8256331132227e9e6585c6bd5742787 -Author: Wolfgang Denk -Date: Thu Nov 30 01:54:07 2006 +0100 - - Code cleanup. Update CHANGELOG. - -commit 726e90aacf0b1ecb0e7055be574622fbe3e450ba -Author: Grant Likely -Date: Wed Nov 29 16:23:42 2006 +0100 - - [PATCH] [MPC52xx] Use IPB bus frequency for SOC peripherals - - The soc node of the mpc52xx needs to be loaded with the IPB bus frequency, - not the XLB frequency. - - This patch depends on the previous patches for MPC52xx device tree support - - Signed-off-by: Grant Likely - Signed-off-by: Sylvain Munaut - -commit 1eac2a71417b6675b11aace72102a2e7fde8f5c6 -Author: Stefan Roese -Date: Wed Nov 29 15:42:37 2006 +0100 - - [PATCH] Add support for Prodrive P3M750 & P3M7448 (P3Mx) boards - - This patch adds support for the Prodrive P3M750 (PPC750 & MV64460) - and the P3M7448 (MPC7448 & MV64460) PMC modules. Both modules are - quite similar and share the same board directory "prodrive/p3mx" - and the same config file "p3mx.h". - - Signed-off-by: Stefan Roese - -commit 1bdd46832aeb569f5e04b1f20f64318525b6525a -Author: Stefan Roese -Date: Wed Nov 29 12:53:15 2006 +0100 - - [PATCH] common/cmd_elf.c: Enable loadaddr as parameter in bootvx command - - In the bootvx command the load address was only read from the env - variable "loadaddr" and not optionally passed as paramter as described - in the help. This is fixed with this patch. The behaviour is now the - same as in the bootelf command. - - Signed-off-by: Stefan Roese - -commit 4e26f1074c3ac1bd8fd094f0dc4a1c4a0b15a592 -Author: Stefan Roese -Date: Wed Nov 29 12:03:57 2006 +0100 - - [PATCH] include/ppc440.h minor error affecting interrupts - - Fixed include/ppc440.c for UIC address Bug - - Corrects bug affecting the addresses for the universal interrupt - controller UIC2 and UIC3 on the PPC440 Epx, GRx, and SPE chips. - - Signed-off-by: Jeff Mann - Signed-off-by: Stefan Roese - -commit 1939d969443ccf316cab2bf32ab1027d4db5ba1a -Author: Joakim Tjernlund -Date: Tue Nov 28 16:17:27 2006 -0600 - - Make fsl-i2c not conflict with SOFT I2C - - Signed-off-by: Timur Tabi - -commit 14198bf768fdc958e3c1afd2404e5262208e98d7 -Author: Joakim Tjernlund -Date: Tue Nov 28 16:17:18 2006 -0600 - - Fix I2C master address initialization. - - Signed-off-by: Timur Tabi - -commit cf3d045e51ca8dcc6cf759827140861d6ac25c04 -Author: Kim Phillips -Date: Tue Nov 28 23:31:19 2006 -0600 - - Assign maintainers for mpc8349emds and mpc8360emds - - Dave for mpc8360emds, and me for mpc8349emds. - -commit 1aa934c81b77f2080d3ca4b226eab67b17a33961 -Author: Kim Phillips -Date: Tue Nov 28 23:28:33 2006 -0600 - - Eliminate gcc 4 'used uninitialized' warnings in drivers/qe/uccf.c - - give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src - since they are passed by reference to ucc_get_cmxucr_reg and assigned. - -commit e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5 -Author: Timur Tabi -Date: Tue Nov 28 12:09:35 2006 -0600 - - mpc83xx: Miscellaneous code style fixes - - Implement various code style fixes and similar changes. - - Signed-off-by: Timur Tabi - -commit e59581c56ab5d6e0207ddac3b2c1d55cb36ec706 -Author: Stefan Roese -Date: Tue Nov 28 17:55:49 2006 +0100 - - [PATCH] Enable the IceCube/lite5200 variants to pass a device tree to Linux. - - This patch adds the code and configuration necessary to boot with an - arch/powerpc Linux kernel. - - Signed-off-by: Grant Likely - Acked-by: Jon Loeliger - -commit e732faec95a83cb468b4850ae807c8301dde8f6a -Author: Stefan Roese -Date: Tue Nov 28 16:09:24 2006 +0100 - - [PATCH] PPC4xx: 440SP Rev. C detection added - - Signed-off-by: Stefan Roese - -commit e7f3e9ff01fbd7fa72eb42a9675fbed6bc4736b0 -Author: Stefan Roese -Date: Tue Nov 28 11:04:45 2006 +0100 - - [PATCH] nand: Fix patch merge problem - - Signed-off-by: Stefan Roese - -commit 58e3b14c18ed3288ceef8d086946dbf3df64ccf2 -Author: Stefan Roese -Date: Tue Nov 28 11:04:45 2006 +0100 - - [PATCH] nand: Fix patch merge problem - - Signed-off-by: Stefan Roese - -commit 4f4b602ec7524a032bdf3c6d28c7f525a4a67eaa -Author: Wolfgang Denk -Date: Mon Nov 27 22:53:53 2006 +0100 - - Update CHANGELOG - -commit f6e495f54cdb8fe340b9c03deab40ad746d52fae -Author: Stefan Roese -Date: Mon Nov 27 17:43:25 2006 +0100 - - [PATCH] 4xx_enet.c: Correct the setting of zmiifer register - - Patch below corrects the setting of the zmiifer register, it was - overwritting the register rather than ORing the settings. - - Signed-off-by: Neil Wilson - Signed-off-by: Stefan Roese - -commit d1a72545296800b7e219f93104ad5836f0003d66 -Author: Stefan Roese -Date: Mon Nov 27 17:34:10 2006 +0100 - - [PATCH] Select NAND embedded environment from board configuration - - The current NAND Bootloader setup forces the environment - variables to be in line with the bootloader. This change - enables the configuration to be made in the board include - file instead so that it can be individually enabled. - - Signed-off-by: Nick Spence - Signed-off-by: Stefan Roese - -commit 15784862857c3c2214498defcfed84ff137fb81e -Author: Stefan Roese -Date: Mon Nov 27 17:22:19 2006 +0100 - - [PATCH] nand_wait() timeout fixes - - Two fixes for the nand_wait() function in - drivers/nand/nand_base.c: - - 1. Use correct timeouts. The original timeouts in Linux - source are 400ms and 20ms not 40s and 20s - - 2. Return correct error value in case of timeout. 0 is - interpreted as OK. - - Signed-off-by: Rui Sousa - Signed-off-by: Stefan Roese - -commit da5553b095bf04f4f109ad7e565dae3aba47b230 -Author: Stefan Roese -Date: Mon Nov 27 17:04:06 2006 +0100 - - [PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel - - This patch allows an arch/ppc kernel to be booted by just passing 1 or 2 - arguments to bootm. It removes the getenv("disable_of") test that used - to be used for this purpose. - - Signed-off-by: Grant Likely - Acked-by: Jon Loeliger - -commit a9398e018593782c5fa7d0741955fc1256b34c1e -Author: Wolfgang Denk -Date: Mon Nov 27 15:32:42 2006 +0100 - - Minor code cleanup. Update CHANGELOG. - -commit 1729b92cde575476684bffe819d0b7791b57bff2 -Author: Stefan Roese -Date: Mon Nov 27 14:52:04 2006 +0100 - - [PATCH] 4xx: Fix problem with board specific reset code (now for real) - - Signed-off-by: Stefan Roese - -commit cc5ee8a92a0e3ca6f727af71b8fd206460c7afd7 -Author: Stefan Roese -Date: Mon Nov 27 14:49:51 2006 +0100 - - [PATCH] alpr: remove unused board specific flash driver - - Signed-off-by: Stefan Roese - -commit 1f94d162e2b5f0edc28d9fb11482502c44d218e1 -Author: Stefan Roese -Date: Mon Nov 27 14:48:41 2006 +0100 - - [PATCH] 4xx: Fix problem with board specific reset code - - Signed-off-by: Stefan Roese - -commit ec0c2ec725aec9524a177a77ce75559e644a931a -Author: Stefan Roese -Date: Mon Nov 27 14:46:06 2006 +0100 - - [PATCH] Remove testing 4xx enet PHY setup - - Signed-off-by: Stefan Roese - -commit 1c2ce2262069510f31c7d3fd7efd3d58b8c0c148 -Author: Stefan Roese -Date: Mon Nov 27 14:12:17 2006 +0100 - - [PATCH] Update Prodrive ALPR board support (440GX) - - Signed-off-by: Stefan Roese - -commit 58b485776698c3d71ec5a215e392123b4c15afa3 -Author: Markus Klotzbuecher -Date: Mon Nov 27 11:51:21 2006 +0100 - - Add a small README with information on the generic ohci driver. - -commit ae3b770e4eae8e98b6e9e29662e18c47fdf0171f -Author: Markus Klotzbuecher -Date: Mon Nov 27 11:46:46 2006 +0100 - - Fix some endianness issues related to the generic ohci driver - -commit 7b59b3c7a8ce2e4b567abf99c1cd667bf35b9418 -Author: Markus Klotzbuecher -Date: Mon Nov 27 11:44:58 2006 +0100 - - Introduced the configuration option CONFIG_USB_OHCI_NEW in order to be able - to choose between the old and the generic OHCI drivers. - -commit 53e336e9ffc51035bdc4e5867631b3378761b4df -Author: Markus Klotzbuecher -Date: Mon Nov 27 11:43:09 2006 +0100 - - Modified the mpc5xxx and the ppc4xx cpu to use the generic OHCI driver - and adapted board configs TQM5200 and yosemite accordingly. This commit - also makes the maximum number of root hub ports configurable - (CFG_USB_OHCI_MAX_ROOT_PORTS). - -commit 78d620ebb5871d252270dedfad60c6568993b780 -Author: Wolfgang Denk -Date: Thu Nov 23 22:58:58 2006 +0100 - - Updates for TQM5200 modules: - - fix off-by-one error in board/tqm5200/cam5200_flash.c error message - - simplify "udate" definitions - -commit 2053283304eeddf250d109e6791eb6fa4cad14f7 -Author: Stefan Roese -Date: Wed Nov 22 13:20:50 2006 +0100 - - [PATCH] PPC4xx start.S: Fix for processor errata - - Fixed cpu/ppc4xx/start.S for 440EPx Errata: further corrects PPC440EPx - errata 1.12: 440_33 by moving patch up in code. - - Signed-off-by: Jeff Mann - Signed-off-by: Stefan Roese - -commit 4ef6251403f637841000e0fef9e832aa01339822 -Author: Stefan Roese -Date: Mon Nov 20 20:39:52 2006 +0100 - - [PATCH] Update AMCC Sequoia config file to support 64MByte NOR FLASH - - Signed-off-by: Stefan Roese - -commit e4bbd8da164b976d38616bd9c69c5e86e193cdf0 -Author: Wolfgang Denk -Date: Mon Nov 20 10:28:30 2006 +0100 - - Update CHANGELOG - -commit 260421a21e934a68d31fb6125b0fbd2631a8ca20 -Author: Stefan Roese -Date: Mon Nov 13 13:55:24 2006 +0100 - - [PATCH] CFI driver AMD Command Set Top boot geometry reversal, etc. [Updated] - - * Adds support for AMD command set Top Boot flash geometry reversal - * Adds support for reading JEDEC Manufacturer ID and Device ID - * Adds support for displaying command set, manufacturer id and - device ids (flinfo) - * Makes flinfo output to be consistent when CFG_FLASH_EMPTY_INFO defined - * Removes outdated change history (refer to git log instead) - - Signed-off-by: Tolunay Orkun - Signed-off-by: Stefan Roese - -commit b21b511d4c50408f4853f46f06b601272196223f -Author: Wolfgang Denk -Date: Sun Nov 12 21:13:23 2006 +0100 - - Update CHANGELOG - -commit ce3f1a40c507afbab06c5eb58ccdc6713eda3245 -Author: Bartlomiej Sieka -Date: Sat Nov 11 22:48:22 2006 +0100 - - Disable the watchdog in the default config for the V38B board. - -commit 44a47e6db2694841211f1c8fdbafd36992e9cd1a -Author: Bartlomiej Sieka -Date: Sat Nov 11 22:43:00 2006 +0100 - - Change the GPIO pin multiplexing configuration for V38B. The USB GPIO pin - group is enabled for USB earlier (in cpu_init_f() instead of - usb_lowlevel_init()). - -commit 91650b3e4de688038d4f71279c44858e3e2c6870 -Author: Wolfgang Denk -Date: Mon Nov 6 17:06:36 2006 +0100 - - Sequential accesses to non-existent memory must be synchronized, - at least on G2 cores. - - This fixes get_ram_size() problems on MPC5200 Rev. B boards. - -commit be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa -Author: Timur Tabi -Date: Fri Nov 3 19:15:00 2006 -0600 - - mpc83xx: Update 83xx to use fsl_i2c.c - - Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete - cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. - Added multiple I2C bus support to fsl_i2c.c. - - Signed-off-by: Timur Tabi - -commit d239d74b1c937984bc519083a8e7de373a390f06 -Author: Timur Tabi -Date: Fri Nov 3 12:00:28 2006 -0600 - - mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR - - Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx - tree matches the other 8xxx trees. - - Signed-off-by: Timur Tabi - -commit f7fb2e703ec9688541416962724adff70a7322cb -Author: Kim Phillips -Date: Thu Nov 2 19:47:11 2006 -0600 - - mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c - -commit 90f30a710a3c619b5405860a686c4ddfc495d4b6 -Author: Dave Liu -Date: Thu Nov 2 18:05:50 2006 -0600 - - mpc83xx: Fix the incorrect dcbz operation - - The 834x rev1.x silicon has one CPU5 errata. - - The issue is when the data cache locked with - HID0[DLOCK], the dcbz instruction looks like no-op inst. - - The right behavior of the data cache is when the data cache - Locked with HID0[DLOCK], the dcbz instruction allocates - new tags in cache. - - The 834x rev3.0 and later and 8360 have not this bug inside. - - So, when 834x rev3.0/8360 are working with ECC, the dcbz - instruction will corrupt the stack in cache, the processor will - checkstop reset. - - However, the 834x rev1.x can work with ECC with these code, - because the sillicon has this cache bug. The dcbz will not - corrupt the stack in cache. - Really, it is the fault code running on fault sillicon. - - This patch fix the incorrect dcbz operation. Instead of - CPU FP writing to initialise the ECC. - - CHANGELOG: - * Fix the incorrect dcbz operation instead of CPU FP - writing to initialise the ECC memory. Otherwise, it - will corrupt the stack in cache, The processor will checkstop - reset. - - Signed-off-by: Dave Liu - -commit bf0b542d6773a5a1cbce77691f009b06d9aeb57d -Author: Kim Phillips -Date: Wed Nov 1 00:10:40 2006 -0600 - - mpc83xx: add OF_FLAT_TREE bits to 83xx boards - - add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and - STDOUT_PATH configuration bits to mpc8349emds, - mpc8349itx, and mpc8360emds board code. - - redo environment to use bootm with the fdtaddr - for booting ARCH=powerpc kernels by default, - and provide default fdtaddr values. - -commit 48041365b3420589ad464ebc7752e0053538b729 -Author: Kim Phillips -Date: Wed Nov 1 00:07:25 2006 -0600 - - mpc83xx: change ft code to modify local-mac-address property - - Update 83xx OF code to update local-mac-address properties - for ethernet instead of the obsolete 'address' property. - -commit 9ca880a250870a7d55754291b5591d2b5fe89b54 -Author: Timur Tabi -Date: Tue Oct 31 21:23:16 2006 -0600 - - mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and MPC8360EMDS - - This patch also adds an improved I2C set_speed(), which handles all clock - frequencies. - - Signed-off-by: Timur Tabi - -commit ac4b5622ce050b5ee1e154b98df630d778661632 -Author: Dave Liu -Date: Tue Oct 31 19:54:59 2006 -0600 - - mpc83xx: add the README.mpc8360emds - - add doc/README.mpc8360emds to accompany the new board support - -commit 7737d5c658c606f999dfbe3e86b0fed49e5c50ef -Author: Dave Liu -Date: Fri Nov 3 12:11:15 2006 -0600 - - mpc83xx: add QE ethernet support - - this patch adds support for the QUICC Engine based UCC gigabit ethernet device. - -commit 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73 -Author: Dave Liu -Date: Fri Nov 3 19:33:44 2006 -0600 - - mpc83xx: Add MPC8360EMDS basic board support - - Add support for the Freescale MPC8360EMDS board. - Includes DDR, DUART, Local Bus, PCI. - -commit 23892e49352de74f7fac36ff90bb1be143d195e3 -Author: Dave Liu -Date: Tue Oct 31 19:30:40 2006 -0600 - - mpc83xx: add the QUICC Engine (QE) immap file - - common QE immap file. Also required for 8360. - -commit b701652a4992bdcc62fb1a6038a85beef9e55da4 -Author: Dave Liu -Date: Tue Oct 31 19:25:38 2006 -0600 - - mpc83xx: Add 8360 specifics to 83xx immap - - Mainly add QE device dependencies, with appropriate 8360 protection. - Lindent also run. - -commit 988833324a7fda482c8ac3ca23eb539f8232e404 -Author: Timur Tabi -Date: Tue Oct 31 19:14:41 2006 -0600 - - mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITX - - PREREQUISITE PATCHES: - - * This patch can only be applied after the following patches have been applied: - - 1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2" - 2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2" - - CHANGELOG: - - * For the 8349E-mITX, fix some size values in pci_init_board(), enable - the clock for the 2nd USB board (Linux kernel will hang otherwise), - and fix the CONFIG_BOOTARGS macro. - - Signed-off-by: Timur Tabi - -commit 2ad6b513b31070bd0c003792ed1c3e7f5d740357 -Author: Timur Tabi -Date: Tue Oct 31 18:44:42 2006 -0600 - - mpc83xx: Add support for the MPC8349E-mITX - - PREREQUISITE PATCHES: - - * This patch can only be applied after the following patches have been applied: - - 1) DNX#2006090742000024 "Add support for multiple I2C buses" - 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" - 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" - 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" - 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" - - CHANGELOG: - - * Add support for the Freescale MPC8349E-mITX reference design platform. - The second TSEC (Vitesse 7385 switch) is not supported at this time. - - Signed-off-by: Timur Tabi - -commit 183da6d9b446cc12123455844ad1187e2375626f -Author: Ben Warren -Date: Tue Sep 12 10:15:53 2006 -0400 - - Additional MPC8349 support for multibus i2c - - Hello, - - Here is a patch for a file that was accidentally left out of a previous - attempt. - - It accompanies the patch with ticket DNX#2006090742000024 - - CHANGELOG: - Change PCI initialization to use new multi-bus I2C API. - - regards, - Ben - -commit b24f119d672b709d153ff2ac091d4aa63ec6877d -Author: Ben Warren -Date: Thu Sep 7 16:51:04 2006 -0400 - - Multi-bus I2C implementation of MPC834x - - Hello, - - Attached is a patch implementing multiple I2C buses on the MPC834x CPU - family and the MPC8349EMDS board in particular. - This patch requires Patch 1 (Add support for multiple I2C buses). - Testing was performed on a 533MHz board. - - /*** Note: This patch replaces ticket DNX#2006083042000027 ***/ - - Signed-off-by: Ben Warren - - CHANGELOG: - Implemented driver-level code to support two I2C buses on the - MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds - are 50kHz, 100kHz and 400kHz on each bus. - - regards, - Ben - -commit bb99ad6d8257bf828f150d40f507b30d80a4a7ae -Author: Ben Warren -Date: Thu Sep 7 16:50:54 2006 -0400 - - Add support for multiple I2C buses - - Hello, - - Attached is a patch providing support for multiple I2C buses at the - command level. The second part of the patch includes an implementation - for the MPC834x CPU and MPC8349EMDS board. - - /*** Note: This patch replaces ticket DNX#2006083042000018 ***/ - - Signed-off-by: Ben Warren - - Overview: - - 1. Include new 'i2c' command (based on USB implementation) using - CONFIG_I2C_CMD_TREE. - - 2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that - the commands to change bus number and speed are only available under the - new 'i2c' command mentioned in the first bullet. - - 3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus - systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form - of an array of bus-device pairs. Otherwise, it is an array of uchar. - - CHANGELOG: - Added new 'i2c' master command for all I2C interaction. This is - conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for - setting I2C bus speed as well as changing the active bus if the board - has more than one (conditionally compiled with - CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses. - Updated README. - - regards, - Ben - -commit bed85caf872714ebf53013967a695c9d63acfc68 -Author: Timur Tabi -Date: Tue Oct 31 18:13:36 2006 -0600 - - mpc83xx: Add support for Errata DDR6 on MPC 834x systems - - CHANGELOG: - - * Errata DDR6, which affects all current MPC 834x processors, lists changes - required to maintain compatibility with various types of DDR memory. This - patch implements those changes. - - Signed-off-by: Timur Tabi - -commit afd6e470f639883002c7c59d562690a5cb0f4865 -Author: Timur Tabi -Date: Wed Oct 25 18:45:23 2006 -0500 - - mpc83xx: fix TQM build by defining a CFG_FLASH_SIZE for it - -commit 31068b7c4abeefcb2c8fd4fbeccc8ec6c6d0475a -Author: Timur Tabi -Date: Tue Aug 22 17:07:00 2006 -0500 - - mpc83xx: Add support for variable flash memory sizes on 83xx systems - - CHANGELOG: - - * On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access - window registers, instead of using a hard-coded value of 8MB. - - Signed-off-by: Timur Tabi - -commit 2fc34ae66e73fa7841d1a006dc1b5dcbc1f78965 -Author: Tanya Jiang -Date: Thu Aug 3 18:38:13 2006 +0800 - - mpc83xx: Unified TQM834x variable names with 83xx and consolidated macros - - Unified TQM834x variable names with 83xx and consolidated macro - in preparation for the 8360 and other upcoming 83xx devices. - - Signed-off-by: Tanya Jiang - -commit f6eda7f80ccc13d658020268c507d7173cf2e8aa -Author: Dave Liu -Date: Wed Oct 25 14:41:21 2006 -0500 - - mpc83xx: Changed to unified mpx83xx names and added common 83xx changes - - Incorporated the common unified variable names and the changes in preparation - for releasing mpc8360 patches. - - Signed-off-by: Dave Liu - -commit 3894c46c27c64891f93ac04edde86a9fa9758d92 -Author: Tanya Jiang -Date: Thu Aug 3 18:36:02 2006 +0800 - - mpc83xx: Fix missing build for mpc8349emds pci.c - - Make pci build for mpc8349emds - - Signed-off-by: Tanya Jiang - -commit 09a81ff740b29deea1e2ab08a3c2ac136c2e6219 -Author: Tanya Jiang -Date: Thu Aug 3 18:39:49 2006 +0800 - - mpc83xx: Removed unused file resetvec.S for mpc83xx cpu - - Removed unused file resetvec.S for mpc83xx cpu - - Signed-off-by: Tanya Jiang - -commit 04f899fc465c3e44f2b55ecc70618f5696fc0ddf -Author: Nick Spence -Date: Sat Sep 30 00:32:59 2006 -0700 - - NAND Flash verify across block boundaries - - This patch addresses a problem when CONFIG_MTD_NAND_VERIFY_WRITE is - defined - and the write crosses a block boundary. The pointer to the verification - buffer (bufstart) is not being updated to reflect the starting of the - new - block so the verification of the second block fails. - - CHANGELOG: - - * Fix NAND FLASH page verification across block boundaries - -commit f484dc791a3932537213c43c654cc1295c64b84c -Author: Nick Spence -Date: Thu Sep 7 07:39:46 2006 -0700 - - Added RGMII support to the TSECs and Marvell 881111 Phy - - Added a phy initialization to adjust the RGMII RX and TX timing - Always set the R100 bit in 100 BaseT mode regardless of the TSEC mode - - Signed-off-by: Nick Spence - -commit 4831c8b8a97799da77923d6bbb4c260c0d45521c -Author: roy zang -Date: Fri Nov 3 13:10:00 2006 +0800 - - Remove some unused CFG define. - undef CFG_DRAM_TEST - -commit 99c09c4dec34f77c243bf51bea532e3f339410ad -Author: roy zang -Date: Fri Nov 3 13:07:36 2006 +0800 - - Change the TEXT_BASE from 0xFFF00000 to 0xFF000000. - Both work. 0xFF000000 seems more reasonable. - -commit c59200443072353044aa4bf737a5a60f9a9af231 -Author: Wolfgang Denk -Date: Thu Nov 2 15:15:01 2006 +0100 - - Release U-Boot 1.1.6 - -commit c1fbe4103a0d6c8957f912af902d705ba67836f2 -Author: roy zang -Date: Thu Nov 2 19:14:48 2006 +0800 - - This patch comes from Yuli's posted patch on 8/8/2006 - titled "CFI Driver Little-Endian write Issue". - - http://sourceforge.net/mailarchive/message.php?msg_id=36311999 - - If that patch applied, please discard this one. - Until now , I do not see his patch is applied. So please apply this one. - - Signed-off-by: Yuli Barcohen - Signed-off-by: Roy Zang - -commit b825f158e449e1e9cf74c08e572955e122394c96 -Author: roy zang -Date: Thu Nov 2 19:12:31 2006 +0800 - - Tsi108 on chip i2c support. - - The i2c Interface provides a master-only, serial interface that can be - used for initializing Tsi108/Tsi109 registers from an EEPROM after a - device reset. - - Signed-off-by: Alexandre Bounine - Signed-off-by: Roy Zang - -commit 9226e7d6f09b9a1ac074cd918c81225a4689bba8 -Author: roy zang -Date: Thu Nov 2 19:11:06 2006 +0800 - - Tsi108 on chip pci controller support. - - If there is no pci card, the tsi108/109 pci configure read will - cause a machine check exception to the processor. PCI error should - also be cleared after the read. - - Signed-off-by: Alexandre Bounine - Signed-off-by: Roy Zang - -commit d1927cee977126e547ceeba23e4f978f377cfb8f -Author: roy zang -Date: Thu Nov 2 19:08:55 2006 +0800 - - Tundra tsi108 on chip Ethernet controller support. - - The following is a brief description of the Ethernet controller: - The Tsi108/9 Ethernet Controller connects Switch Fabric to two independent - Gigabit Ethernet ports,E0 and E1. It uses a single Management interface - to manage the two physical connection devices (PHYs). Each Ethernet port - has its own statistics monitor that tracks and reports key interface - statistics. Each port supports a 256-entry hash table for address - filtering. In addition, each port is bridged to the Switch Fabric - through a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO. - - Each Ethernet port also has a pair of internal Ethernet DMA channels to - support the transmit and receive data flows. The Ethernet DMA channels - use descriptors set up in memory, the memory map of the device, and - access via the Switch Fabric. The Ethernet Controller?s DMA arbiter - handles arbitration for the Switch Fabric. The Controller also - has a register businterface for register accesses and status monitor - control. - - The PMD (Physical Media Device) interface operates in MII, GMII, or TBI - modes. The MII mode is used for connecting with 10 or 100 Mbit/s PMDs. - The GMII and TBI modes are used to connect with Gigabit PMDs. Internal - data flows to and from the Ethernet Controller through the Switch Fabric. - - Each Ethernet port uses its transmit and receive DMA channels to manage - data flows through buffer descriptors that are predefined by the - system (the descriptors can exist anywhere in the system memory map). - These descriptors are data structures that point to buffers filled - with data ready to transmit over Ethernet, or they point to empty - buffers ready to receive data from Ethernet. - - Signed-off-by: Alexandre Bounine - Signed-off-by: Roy Zang - -commit 78aa0c3427f3ecdeb34aabfbbe2dd23b6ad8f40e -Author: roy zang -Date: Thu Nov 2 19:01:33 2006 +0800 - - Tundra tsi108 header file. - - The Tundra Semiconductor Corporation (Tundra) Tsi108 is a host bridge for - PowerPC processors that offers numerous system interconnect options for - embedded application designers. The Tsi108 can interconnect 60x or - MPX processors to PCI/X peripherals, DDR2-400 memory, Gigabit Ethernet, - and Flash. Provided the macro define for tsi108 chip. - - Signed-off-by: Alexandre Bounine - Signed-off-by: Roy Zang - -commit 87c4db09699c6b89176b31004afcb83eb1585d47 -Author: roy zang -Date: Thu Nov 2 18:59:15 2006 +0800 - - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. - mpc7448hpc2 board support high level code:tsi108 init + mpc7448hpc2. - - Signed-off-by: Alexandre Bounine - Signed-off-by: Roy Zang - -commit 27801b8ab11c61b577e45742a515bb3b23b80241 -Author: roy zang -Date: Thu Nov 2 18:57:21 2006 +0800 - - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. - Make ,config.mk and link file for the mpc7448hpc2 board. - - Signed-off-by: Alexandre Bounine - Signed-off-by: Roy Zang - -commit c6411c0c3bbc79f9ba8aef58296a42d8f9d8a0a6 -Author: roy zang -Date: Thu Nov 2 18:55:04 2006 +0800 - - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. - The mpc7448hpc2 board support header file. - - Signed-off-by: Alexandre Bounine - Signed-off-by: Roy Zang - -commit 625bb5ddb50b243f931262ca8c46956409471917 -Author: roy zang -Date: Thu Nov 2 18:52:21 2006 +0800 - - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. - The mpc7448hpc2 board support low level assemble language init code. - - Signed-off-by: Alexandre Bounine - Signed-off-by: Roy Zang - -commit 4c52783b3d024e153c4972b97332e314bc3bdc46 -Author: roy zang -Date: Thu Nov 2 18:49:51 2006 +0800 - - General code modification for mpc7448hpc2 board support. - 1. Add 7447A and 7448 processor support. - 2. Add the following flags. - - CFG_CONFIG_BUS_CLK : If the 74xx bus frequency can be configured dynamically - (such as by switch on board), this flag should be set. - - CFG_EXCEPTION_AFTER_RELOCATE: If an exception occurs after the u-boot - relocates to RAM, this flag should be set. - - CFG_SERIAL_HANG_IN_EXCEPTION: If the print out function will cause the - system hang in exception, this flag should be set. - - There is a design issue for tsi108/109 pci configure read. When pci scan - the slots, if there is no pci card, the tsi108/9 will cause a machine - check exception for mpc7448 processor. - - Signed-off-by: Alexandre Bounine - Signed-off-by: Roy Zang - -commit 69366bf42f22d67efce8da3f8c40a43d4a3c2695 -Author: roy zang -Date: Thu Nov 2 18:34:47 2006 +0800 - - Add README file for mpc7448hpc2 board. - Signed-off-by: Roy Zang - -commit 25721b5cec2be4bce79cfade17ec8f6aa1e67526 -Author: Bartlomiej Sieka -Date: Wed Nov 1 02:04:38 2006 +0100 - - Finish up support for MarelV38B board - - add watchdog support - - enable GPIO_WKUP_7 pin for input - - code cleanup - -commit ffa150bc90c943ca265170bd1be3f293674dd5c7 -Author: Bartlomiej Sieka -Date: Wed Nov 1 01:45:46 2006 +0100 - - - Fix issues related to the use of ELDK 4 when compiling for MarelV38B: - * remove warnings when compiling ethaddr.c - * adjust linker script (fixes a crash resulting from incorrect - definition of __u_boot_cmd_start) - - Some MarelV38B code cleanup. - -commit dae80f3caf9754a6dd3ddf3cf903d0c46cbd4385 -Author: Bartlomiej Sieka -Date: Wed Nov 1 01:38:16 2006 +0100 - - - Add MPC5XXX register definition MPC5XXX_WU_GPIO_DATA_I and change the - MPC5XXX_WU_GPIO_DATA macro to MPC5XXX_WU_GPIO_DATA_O (per MPC5200 User's - Manual). Replace the uses of MPC5XXX_WU_GPIO_DATA with - MPC5XXX_WU_GPIO_DATA_O for affected boards. - - - Add defintions for some MPC5XXX GPIO pins. - -commit 82d9c9ec29a1bec1b03ba616425ebaed231072c8 -Author: Bartlomiej Sieka -Date: Wed Nov 1 01:34:29 2006 +0100 - - Changed MarelV38B board make target to lowercase. Config file cleanup. - -commit 1954be6e9c9421b45d0a9d05b10356acc7563150 -Author: Wolfgang Denk -Date: Sun Oct 29 01:03:51 2006 +0200 - - Automatically adjust ARFLAGS so "make -s" is really silent. - -commit fae684e89844856383bdf101440889557df3e6b1 -Author: Stefan Roese -Date: Sat Oct 28 16:45:00 2006 +0200 - - [PATCH] omap925.c: Remove unused functions - - Signed-off-by: Ladislav Michl - Signed-off-by: Stefan Roese - -commit 1265581502ab8ea8c08e8edbe9bf64fbd62fd776 -Author: Stefan Roese -Date: Sat Oct 28 17:12:58 2006 +0200 - - [PATCH] Add some missing machtypes for netstar & voiceblue boards - - Use MACH_TYPE_NETSTAR and MACH_TYPE_VOICEBLUE defines instead of - numbers in code. - - Signed-off-by: Ladislav Michl - Signed-off-by: Stefan Roese - -commit 856f054410cef52d868feb330168b2a4c4091328 -Author: Stefan Roese -Date: Sat Oct 28 15:55:52 2006 +0200 - - [PATCH] NAND: Partition name support added to NAND subsystem - - chpart, nboot and NAND subsystem related commands now accept also partition - name to specify offset. - - Signed-off-by: Ladislav Michl - Signed-off-by: Stefan Roese - -commit 07a69a18c2ecfda904231fdf23e2523ea7792eb6 -Author: Wolfgang Denk -Date: Sat Oct 28 02:29:44 2006 +0200 - - Update CHANGELOG. - -commit 2751a95abd1b96911081c357e96a12fa97b40dee -Author: Wolfgang Denk -Date: Sat Oct 28 02:29:14 2006 +0200 - - Enable commandline editing and hush shell on all TQM boards. - -commit 8078f1a5f63a739b8533478f6c2b62fb1e2f79d7 -Author: Wolfgang Denk -Date: Sat Oct 28 02:28:02 2006 +0200 - - README says CFG_AUTO_COMPLETE, but ocde uses CONFIG_AUTO_COMPLETE - -commit 471a7be7a042e95e440f5de969c9765214ae8d6e -Author: Wolfgang Denk -Date: Sat Oct 28 01:14:32 2006 +0200 - - Check for illegal character '=' in environment variable names. - - Make sure the string passed as variable name does not contain a '=' - character. This not only prevents the common error or typing - "setenv foo=bar" instead of "setenv foo bar", but (more importantly) - also closes a backdoor which allowed to delete write-protected - environment variables, for example by using "setenv ethaddr=". - -commit 19973b6ad9863a56f5c5fbcfd90e20ab2490a2c2 -Author: Wolfgang Denk -Date: Sat Oct 28 00:38:39 2006 +0200 - - Minor code cleanup. - -commit e11887a77d81077416a2d1c5e0354916fee8c034 -Author: Haavard Skinnemoen -Date: Thu Oct 26 17:55:31 2006 +0200 - - Don't pass any debug options directly to the assembler - - When passing the -g option to gcc, gcc automatically selects a - suitable --g option to pass on to the assembler. - Thus, there's no point in forcing a specific debug option on the - assembler using the -Wa mechanism. - - Signed-off-by: Haavard Skinnemoen - -commit ea08ff6e14f9ebb8c07cfa79c51ef540eb087393 -Author: Jon Loeliger -Date: Fri Oct 27 07:47:22 2006 -0500 - - MPC86xx: Cleaned up unused and conditionally used local variables. - - Signed-off-by: Jon Loeliger - -commit d38936cdae46bfd2623ff83f6ce9b616d36ab0f9 -Author: Wolfgang Denk -Date: Fri Oct 27 11:55:21 2006 +0200 - - Fix "ar" flags in some Makefiles to allow for silent "make -s" - -commit 4653f91c13ed51c21cc4c3855745d69a3fb1817f -Author: Ben Warren -Date: Thu Oct 26 14:38:25 2006 -0400 - - Fix TSEC driver (now for real): avoid crashes if PHY is not attached - to a TSEC (e.g. a switch is connected via RMII) or - if the PHY is defective/incorrectly configured. - - Signed-off-by: Ben Warren - -commit b985b5d6e4fb88f508f7aa0f126c2e27ada2b999 -Author: Ben Warren -Date: Thu Oct 26 14:38:25 2006 -0400 - - Fix TSEC driver: avoid crashes if PHY is not attached - to a TSEC (e.g. a switch is connected via RMII) or - if the PHY is defective/incorrectly configured. - - Signed-off-by: Ben Warren - -commit 2b2a40bebbf1822506e80e631d7253e60f0e0fe6 -Author: Wolfgang Denk -Date: Thu Oct 26 16:24:31 2006 +0200 - - Code cleanup. - -commit 5e3b0bc19f07ed277d85324ad0427642c8981baf -Author: Haavard Skinnemoen -Date: Wed Oct 25 15:48:59 2006 +0200 - - Finish up support for the ATSTK1000/ATSTK1002 boards - - Add atstk1002_config target to Makefile and move the AVR32 section - down below Blackfin so that it doesn't end up in the middle of - MIPS. - - Drop the autogenerated linker script thing for now. Will have to - revisit how to handle chips with different flash and RAM layout - later. - - Signed-off-by: Haavard Skinnemoen - -commit c76f951a747cfb87ba826ef45b5aea82d5b5dbb4 -Author: Kumar Gala -Date: Tue Oct 24 23:47:37 2006 -0500 - - Added support for Multi-Image files that contain a device tree - - If a Multi-Image file contains a third image we try to use it as a - device tree. The device tree image is assumed to be uncompressed in the - image file. We automatically allocate space for the device tree in memory - and provide an 8k pad to allow more than a reasonable amount of growth. - - Additionally, a device tree that was contained in flash will now automatically - get copied to system memory as part of boot. Previously an error was - reported if one tried to boot a device tree that was in flash. - - Signed-off-by: Kumar Gala - -commit 7c52c4b943ff52bbe8796a7e2d3e476ceaf3f512 -Author: Wolfgang Denk -Date: Tue Oct 24 21:35:55 2006 +0200 - - Switch to automatically generated CHANGELOG file. - (use "make CHANGELOG" to update it from time to time) - -commit 7ade0c634a979c32fa91a74e8f5775f24651fbe6 -Author: Stefan Roese -Date: Tue Oct 24 18:06:48 2006 +0200 - - Fix bug in PPC440 NAND driver cpu/ppc4xx/ndfc.c - Patch by Stefan Roese, 24 Oct 2006 - -commit 8ae3b713b2286e0c3213b7802062e4c1599010de -Author: Wolfgang Denk -Date: Tue Oct 24 17:24:55 2006 +0200 - - Merge with /home/wd/git/u-boot/master - -commit 47a6989c10685d2ab3efcf95228ce50d2a496d3e -Author: Wolfgang Denk -Date: Tue Oct 24 15:32:57 2006 +0200 - - Code cleanup - -commit 3a78e3e75b633ecb6413114ffd11e2f000c4f11e -Author: Wolfgang Denk -Date: Tue Oct 24 14:51:36 2006 +0200 - - Move atstk1000 files into vendor specific directory. - Patch by Haavard Skinnemoen, 12 Sep 2006 - -commit 6ccec4492e77428fd6eafd3dfe94fbdf08e91d37 -Author: Wolfgang Denk -Date: Tue Oct 24 14:42:37 2006 +0200 - - Add ATSTK1000 and ATSTK1002 board support - Patch by Haavard Skinnemoen, 06 Sep 2006 - - This patch adds support for the ATSTK1000 with the ATSTK1002 CPU - daughterboard. - - ATSTK1000 is a full-featured development board for AT32AP CPUs. It - has two ethernet ports, a high quality QVGA LCD panel, a loudspeaker, - and connectors for USART, PS/2, VGA, USB, MMC/SD cards and - CompactFlash cards. For more information, please see this page: - - http://www.atmel.com/dyn/products/tools.asp?family_id=682 - - The ATSTK1002 is a daughterboard for the ATSTK1000 supporting the - AT32AP7000 chip. - - Signed-off-by: Haavard Skinnemoen - -commit f93ae788c3640fcde5db383471d45548ff4060d0 -Author: Wolfgang Denk -Date: Tue Oct 24 14:31:24 2006 +0200 - - Add common serial driver for Atmel AT32 and AT91 chips - Patch by Haavard Skinnemoen, 06 Sep 2006 - - This is a first attempt at creating a common serial driver for Atmel - chips. For now, it supports the AT32AP7000 AVR32 chip, but it should - be possible to support AT91RM9200 and other ARM-based chips with some - minor modifications. - - There's nothing fundamentally AVR32-specific in this driver, but it - does use some features which are currently only defined for the - AT32AP CPU port: - * pm_get_clock_freq: Obtain the clock frequency of a given domain - * gd->console_uart: A "struct device" containing information about - register mappings, gpio resources and clocks associated with the - UART device. - - For more information about these features, please see the "AT32AP - CPU" patch. - -commit 72a087e04705c26cad982879ebd06b5281bf825a -Author: Wolfgang Denk -Date: Tue Oct 24 14:27:35 2006 +0200 - - Add AT32AP CPU and AT32AP7000 SoC support - Patch by Haavard Skinnemoen, 06 Sep 2006 - - This patch adds support for the AT32AP CPU family and the AT32AP7000 - chip, which is the first chip implementing the AVR32 architecture. - - The AT32AP CPU core is a high-performance implementation featuring a - 7-stage pipeline, separate instruction- and data caches, and a MMU. - For more information, please see the "AVR32 AP Technical Reference": - - http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf - - In addition to this, the AT32AP7000 chip comes with a large set of - integrated peripherals, many of which are shared with the AT91 series - of ARM-based microcontrollers from Atmel. Full data sheet is - available here: - - http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf - - Signed-off-by: Haavard Skinnemoen - -commit 7b64fef33c66be648826c0ff9758298ef13d0604 -Author: Wolfgang Denk -Date: Tue Oct 24 14:21:16 2006 +0200 - - Add AVR32 architecture support - Patch by Haavard Skinnemoen, 6 Sep 2006 16:23:02 +0200 - - This patch adds common infrastructure code for the Atmel AVR32 - architecture. See doc/README.AVR32 for details. - - Signed-off-by: Haavard Skinnemoen - -commit 2da2d9a4766063b9848f3a35ad6025499cf87265 -Author: Wolfgang Denk -Date: Tue Oct 24 13:57:33 2006 +0200 - - Use -g instead of -gstabs in AFLAGS_DEBUG - Patch by Haavard Skinnemoen, 30 Aug 2006 - - In config.mk, -Wa,-gstabs is unconditionally appended to AFLAGS no - matter what the target's preferred debugging format is. This patch - simply replaces -gstabs with -g, so that the default debugging format - for the architecture is used. - -commit 965829872169c2996023840d98e1d85ad148d629 -Author: Wolfgang Denk -Date: Tue Oct 24 13:55:18 2006 +0200 - - Fix/workaround broken dependency handling with make 3.81 - Based on patch by Haavard Skinnemoen, 29 Aug 2006 11:20:39 +0200 - -commit 8318fbf8cc30418b621ea9f39b84b4c1a08f003a -Author: Marian Balakowicz -Date: Mon Oct 23 22:17:05 2006 +0200 - - Fix sequoia separate object direcory building problems. - -commit 3dfa9cfdcee78b30da3432318b32821ffabe974b -Author: Jon Loeliger -Date: Fri Oct 20 17:16:35 2006 -0500 - - Use generic I2C register block on 85xx and 86xx. - - Replace private IMMAP I2C structures with generic reg block - and allow 86xx to have multiple I2C device busses. - - Signed-off-by: Jon Loeliger - -commit f5012827df11ca0c9be1df5f8b153e188dc2fa7c -Author: Jon Loeliger -Date: Fri Oct 20 15:54:34 2006 -0500 - - Fix compilation warnings on a few 85xx boards. - - Signed-off-by: Jon Loeliger - -commit 2047672684cf85cb6f96a1fbc993180aaaf19a99 -Author: Jon Loeliger -Date: Fri Oct 20 15:50:15 2006 -0500 - - Converted all 85xx boards to use a common FSL I2C driver. - Introduced COFIG_FSL_I2C to select the common FSL I2C driver. - And removed hard i2c path from a few u-boot.lds scipts too. - Minor whitespace cleanups along the way. - - Signed-off-by: Jon Loeliger - -commit 4d45f69e362b05892c9e92a7907e5820995612aa -Author: Jon Loeliger -Date: Thu Oct 19 12:02:24 2006 -0500 - - Rewrite a series of goto statements as a sequences of - conditional expressions instead. - - Use consistent return code 0/-1 for good/bad indicators. - - Include one fewer file if the driver isn't used at all. - - Signed-off-by: Jon Loeliger - -commit 7237c033b02fe295880435f1eb80819a0c987532 -Author: Jon Loeliger -Date: Thu Oct 19 11:02:16 2006 -0500 - - Moved i2c driver out of cpu/mpc86xx/i2c.c into drivers/fsl_i2c.c - - in an effort to begin to unify the umpteen FSL I2C drivers that - are all otherwise very similar. - - Signed-off-by: Jon Loeliger - -commit 13a7fcdf37f6ea9429ae04c9df67f893364cfe4b -Author: Jon Loeliger -Date: Thu Oct 19 11:33:52 2006 -0500 - - * Fix a bunch of compiler warnings for gcc 4.0 - - Signed-off-by: Matthew McClintock - -commit af9e1f5b9e6f9ce810f5e8bf2961c9542a5865c2 -Author: Stefan Roese -Date: Tue Oct 17 06:14:31 2006 +0200 - - Add monitor functions for indirect access to PPC440 DCR's - Patch by Leonid Baryudin, 12 Oct 2006 - -commit 5f3249a0a168e446a4cc9669b2bce0bc456f0a09 -Author: Jon Loeliger -Date: Fri Oct 13 16:47:53 2006 -0500 - - Fixed leading whitespace issues. - Removed spurious LAWAR thing. - - Signed-off-by: Jon Loeliger - -commit 0ee90cb77e01d6e8ccd37e1bd96678597875c391 -Author: Jon Loeliger -Date: Thu Oct 12 10:42:36 2006 -0500 - - Remove unneeded include files and local variable. - - Signed-off-by: Jon Loeliger - -commit 1eaf3a5ff4960a46f3a9063568ba2af7883f07c5 -Author: Grant Likely -Date: Tue Oct 10 00:23:32 2006 -0600 - - Fix possible uninitialized variable compiler warning. - - When CONFIG_OF_FLAG_TREE is set, the compiler complains that 'len' in - do_bootm_linux() may be uninitialized. There is no possibility in the - current code that len will get used uninitialized, but this fix follows - the existing convention of setting both len and data to zero at the same - time. - - Signed-off-by: Grant Likely - -commit 7376eb87aaa601f728f9b8e5e9cd2711a67f529e -Author: Matthew McClintock -Date: Wed Oct 11 15:13:01 2006 -0500 - - * Fix a bunch of compiler warnings for gcc 4.0 - - Signed-off-by: Matthew McClintock - -commit bf651baa365e5447246aad6a633ccd667cf24a39 -Author: Jon Loeliger -Date: Wed Oct 11 10:10:43 2006 -0500 - - Move "ar" flags to config.mk to allow for silent "make -s" - -commit 1fd5699a4a24f5c1dab1b32f480bace1ebb9fc3e -Author: Jon Loeliger -Date: Tue Oct 10 17:19:03 2006 -0500 - - Coding style changes to remove local varible blocks - and reformat a bit nicer. - -commit 8b283dbb3a08d1b8d406bc15f119e081b3e2606a -Author: Jon Loeliger -Date: Tue Oct 10 17:16:04 2006 -0500 - - Fix whitespace issues. - -commit 7b382b7125f2397cce63253df62f183e3dfa2770 -Author: Jon Loeliger -Date: Tue Oct 10 17:14:45 2006 -0500 - - Fix whitespace issues. - -commit e10390ddd736b0dad1528eec4b0fe35c0827139a -Author: Jon Loeliger -Date: Tue Oct 10 17:06:53 2006 -0500 - - Fix whitespace issues. - -commit 89875e96ba3f023157bf50d5f8e33bf254964a76 -Author: Jon Loeliger -Date: Tue Oct 10 17:03:43 2006 -0500 - - Ran lindent and cleaned up whitespace issues. - Format for 80-columns too. - -commit 333961ae7095fc66d8a041fce1ac9ee873b09d86 -Author: Jon Loeliger -Date: Tue Oct 10 17:02:22 2006 -0500 - - Fix whitespace and 80-col issues. - -commit 5c912cb1c31266c66ca59b36f9b6f87296421d75 -Author: Stefan Roese -Date: Sat Oct 7 11:36:51 2006 +0200 - - CFG_NAND_QUIET_TEST added to not warn upon missing NAND device - Patch by Stefan Roese, 07 Oct 2006 - -commit 5bc528fa4da751d472397b308137238a6465afd2 -Author: Stefan Roese -Date: Sat Oct 7 11:35:25 2006 +0200 - - Update ALPR code (NAND support working now) - Patch by Stefan Roese, 07 Oct 2006 - -commit 77d5034847d328753b80c46b83f960a14a26f40e -Author: Stefan Roese -Date: Sat Oct 7 11:33:03 2006 +0200 - - Remove compile warnings in fpga code - Patch by Stefan Roese, 07 Oct 2006 - -commit f3443867e90d2979a7dd1c65b0d537777e1f9850 -Author: Stefan Roese -Date: Sat Oct 7 11:30:52 2006 +0200 - - Add CONFIG_BOARD_RESET to configure board specific reset function - Patch by Stefan Roese, 07 Oct 2006 - -commit f55df18187e7a45cb73fec4370d12135e6691ae1 -Author: John Traill -Date: Fri Sep 29 08:23:12 2006 +0100 - - Fix missing tCycle/modfreq calculation. - - Signed-off-by: John Traill - -commit 8272dc2f58f2473d8995fcc9b916440cfba080f0 -Author: Andy Fleming -Date: Wed Sep 13 10:33:35 2006 -0500 - - Updated config headers to add default FDT-based booting - -commit 09f3e09e9ebcfa7919ca8931a4b5504fadd1f1d3 -Author: Andy Fleming -Date: Wed Sep 13 10:34:18 2006 -0500 - - Add support for eTSEC 3 & 4 on 8548 CDS - - * Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS. - This will only work on rev 1.3 boards (but doesn't break older boards) - * Cleaned up some comments to reflect the expanded role of tsec - in other systems - -commit 084d648b109c8984f83674043c1a7fa3885ef801 -Author: Andy Fleming -Date: Wed Sep 13 10:33:56 2006 -0500 - - Added code to support 2.6.18 PCI changes in u-boot - - * Added code to swizzle the IRQ map for the PCI - -commit afbdc649f8751e4f4f1a6f527edfe139773f2c15 -Author: Jon Loeliger -Date: Tue Sep 19 09:34:10 2006 -0500 - - Modified makefile for new build mechanism. - - Signed-off-by: Jon Loeliger - -commit d14ba6a798beb753e7a864500414fcc2d198b8bc -Author: Jon Loeliger -Date: Thu Sep 14 08:40:36 2006 -0500 - - Handle 86xx SVR values according to the new Reference Manual. - Both 8641 and 8641D have SVR == 0x8090, and are distinguished - by the byte in bits 16-23 instead. - Thanks to Jason Jin for noticing. - - Signed-off-by: Jon Loeliger - -commit 88c8f4921fc47fb0eb2384b16586f1bd7f275be7 -Author: Zhang Wei -Date: Mon Aug 28 14:25:31 2006 +0800 - - Fixed an OF-tree off-by-one bug when adding a new property name. - This bug will cause the kernel booting to pause a long time. - - Signed-off-by: Zhang Wei - (cherry picked from 2f15776ccc6dc32377d8ba9652b8f58059c27c6d commit) - -commit 9bff7a69a885adebbd2bd45990494ec4cf998a30 -Author: Jon Loeliger -Date: Tue Aug 29 11:05:09 2006 -0500 - - Remove trailing empty lines. - -commit cd6d73d5b895a5935ac4fde0a356288142a584e0 -Author: Jon Loeliger -Date: Tue Aug 29 09:48:49 2006 -0500 - - Remove bogus msync and use volatile asm. - -commit 778d45049ce5927b65b3ff1d8e6692b654bdd49e -Author: Jon Loeliger -Date: Tue Aug 29 08:17:14 2006 -0500 - - Add myself as maintainer for MPC8641HPCN. - -commit 2f15776ccc6dc32377d8ba9652b8f58059c27c6d -Author: Zhang Wei -Date: Mon Aug 28 14:25:31 2006 +0800 - - Fixed an OF-tree off-by-one bug when adding a new property name. - This bug will cause the kernel booting to pause a long time. - - Signed-off-by: Zhang Wei - -commit 5567806b67d0ae83493aa8823ad3b6c914f581d7 -Author: Haiying Wang -Date: Fri Aug 25 14:38:34 2006 -0400 - - Change ramdiskaddr and dtbaddr - Remove PEX fluff commands. - - Signed-off-by: Haiying Wang - Signed-off-by: Jon Loeliger - -commit b2b78421d9db49c21a821af8a19c21c1f7dfb29e -Author: Matthew McClintock -Date: Wed Aug 23 13:32:45 2006 -0500 - - * Another small fix for booting with disable_of - - Signed-off-by: Matthew McClintock - -commit 4a7cc0f21918e6ecf07ed57075d67df2c4a1299c -Author: Jon Loeliger -Date: Wed Aug 23 11:04:43 2006 -0500 - - Cleanup and lindent new AHCI driver. - -commit dabf9ef8c10b4dead5ef2106ef742b1c06b542de -Author: Jin Zhengxiong -Date: Wed Aug 23 19:15:12 2006 +0800 - - Add AHCI define and sata support for MPC8641HPCN board. - - Signed-off-by:Jason Jin - -commit 4782ac80b02f0d01afd309e2200dd3c7037f2ba4 -Author: Jin Zhengxiong -Date: Wed Aug 23 19:10:44 2006 +0800 - - Add AHCI support to u-boot - - Add AHCI support in u-boot, enable the sata disk controllers which - following the AHCI protocol. - - Signed-off-by:Jason Jin - -commit d8ea2acf5f137cae99417df4f573d036ee384668 -Author: Zhang Wei -Date: Wed Aug 23 17:54:32 2006 +0800 - - Add dtb boot-up parameter to default boot commands. - - Signed-off-by: Zhang Wei - -commit b93775c2036b99baa390ea425c4771895bbc63c4 -Author: Jon Loeliger -Date: Tue Aug 22 18:26:08 2006 -0500 - - Cleanup even more poorly introduced whitespace. - -commit ae6241685cbcf0c79a3636530d2ceab1fb291a94 -Author: Jon Loeliger -Date: Tue Aug 22 18:07:00 2006 -0500 - - Cleanup more poorly introduced whitespace. - -commit 2c33e8a1c535b3ae91cf0b284480600bf3f57c57 -Author: Jon Loeliger -Date: Tue Aug 22 17:54:05 2006 -0500 - - Cleanup poorly introduced whitespace. - -commit 80e955c7dd98f4b4fd23c2113caf75ed2b77b5b3 -Author: Jon Loeliger -Date: Tue Aug 22 12:25:27 2006 -0500 - - General indent and whitespace cleanups. - -commit ffff3ae56f5842ca3679e4ce7922b819a87aad9f -Author: Jon Loeliger -Date: Tue Aug 22 12:06:18 2006 -0500 - - General indent and whitespace cleanups. - -commit 41a0e8b304d3ff55fe27a230507aac79684016ac -Author: Jon Loeliger -Date: Tue Aug 22 10:42:21 2006 -0500 - - Cleanup compiler warnings. - -commit 5de62c47a8628b3da4d73f7c07027f32a3342d40 -Author: Matthew McClintock -Date: Tue Aug 22 09:31:59 2006 -0500 - - Fix disable_of booting - - Signed-off-by: Matthew McClintock - -commit 87a449c8ac396420cb24260f717ea9e6faa82047 -Author: Matthew McClintock -Date: Tue Aug 22 09:23:55 2006 -0500 - - Support for FDT in uImage format, error when using FDT from flash - - Signed-off-by: Matthew McClintock - -commit 75c299c38369d01addd5e054b8a16217b70f4a86 -Author: Haiying Wang -Date: Tue Aug 15 15:12:55 2006 -0400 - - Unlock cache before kernel starts up for MPC86xx - -commit 67256678f00c09b0a7f19e862e5c1847553d31bc -Author: Haiying Wang -Date: Tue Aug 15 15:13:15 2006 -0400 - - Copy Global Data Pointer to r29 for DECLARE_GLOBAL_DATA_PTR - -commit 1c8f6d8fb028f156094d05f2d14298e6479364ac -Author: Haiying Wang -Date: Tue Aug 15 15:12:55 2006 -0400 - - Unlock cache before kernel starts up for MPC86xx - -commit 0d9ccc55edf9a7f3c5b2b6263580a6ea8d702a04 -Author: Haiying Wang -Date: Tue Aug 15 15:13:15 2006 -0400 - - Copy Global Data Pointer to r29 for DECLARE_GLOBAL_DATA_PTR - -commit 86c8e17f25e972a7e272950a0735fad84e082b88 -Author: Matthew McClintock -Date: Wed Aug 16 13:59:47 2006 -0500 - - * Fix disable_of booting - - Signed-off-by: Matthew McClintock - -commit 25c751e9adc86e22fe3b5b47cf2806379b575db7 -Author: Matthew McClintock -Date: Wed Aug 16 10:54:09 2006 -0500 - - * Support for FDT in uImage format, error when using FDT from flash - - Signed-off-by: Matthew McClintock - -commit 899620c2d66d4eef3b2a0034d062e71d45d886c9 -Author: Stefan Roese -Date: Tue Aug 15 14:22:35 2006 +0200 - - Add initial support for the ALPR board from Prodrive - NAND needs some additional testing - Patch by Heiko Schocher, 15 Aug 2006 - -commit f0ff4692ff3372dec55074a8eb444943ab095abb -Author: Stefan Roese -Date: Tue Aug 15 14:15:51 2006 +0200 - - Add FPGA Altera Cyclone 2 support - Patch by Heiko Schocher, 15 Aug 2006 - -commit fecf1c7e4de1b2779edc18742b91c22bdc32b68b -Author: Jon Loeliger -Date: Mon Aug 14 15:33:38 2006 -0500 - - Fix BAT0 to actually be cacheable, non-guarded as documented. - - Signed-off-by: Jon Loeliger - -commit 40bc83559db5745681909fd7382ae509567e116d -Author: Jon Loeliger -Date: Wed Aug 9 15:32:16 2006 -0500 - - Removed MPC8641HPCN DTS source file from build. - It is no longer linked into U-Boot; its sources are - now located in the kernel tree. - - Signed-off-by: Jon Loeliger - -commit 34c3c0e01dbf1f8cc2bd08de92f2b89ba84921eb -Author: Matthew McClintock -Date: Wed Jun 28 10:47:03 2006 -0500 - - * Switched default PCI speed for 8540 ADS back to 33MHz - - * Added comments and a printf to warn that PCI-X won't - work at 33MHz - Patch by Andy Fleming 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit b6c5e1373b6ea0bb37a18e4aeecec00613d1cd39 -Author: Matthew McClintock -Date: Wed Jun 28 10:46:35 2006 -0500 - - * Fixed a bug where 8555 PCI code used the old variable and function names Patch by Andy Fleming 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit bf1dfffd8c26f8ecdd630a0ae4c834e751e4e452 -Author: Matthew McClintock -Date: Wed Jun 28 10:46:13 2006 -0500 - - * Added VIA configuration table - - * Added support for PCI2 on CDS - Patch by Andy Fleming 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit c88f9fe66b64247e5b6a38410ba315ca25596d16 -Author: Matthew McClintock -Date: Wed Jun 28 10:45:41 2006 -0500 - - * Fixed PCI memory definitions Patch by Andy Fleming 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit 97074ed9655309b64231bc2cee69fe85399f8055 -Author: Matthew McClintock -Date: Wed Jun 28 10:45:17 2006 -0500 - - * Added support for initializing second PCI bus on 85xx Patch by Andy Fleming 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit f0e6f57f71b3c4fdd13028eb03c3f3e91926dda2 -Author: Matthew McClintock -Date: Wed Jun 28 10:44:49 2006 -0500 - - * Added PCI-X #defines for PCI-X initialization Patch by Andy Fleming on 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit a4e11558b810ef2cddffdf7b9d86bc1130441960 -Author: Matthew McClintock -Date: Wed Jun 28 10:44:23 2006 -0500 - - * Made sure the code which disables prefetch for PCI devices sets the size of the prefetch region to 0 Patch by Andy Fleming on 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit 0e16387db1d4aacd5bf35cb6d7c1942765c0347b -Author: Matthew McClintock -Date: Wed Jun 28 10:43:36 2006 -0500 - - * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon Loeliger 17-Jan-2006 - - Signed-off-by: Jon Loeliger - -commit 855e6fb073f9d04fe4a7f06c107ecbac6344ddd4 -Author: Matthew McClintock -Date: Wed Jun 28 10:43:00 2006 -0500 - - * Removed the oftree.dts for stxxtx in light of the changes to the flat device tree handling code Patch by Matthew McClintock 26-June-2006 - -commit 5498d90312aad9f6bdbf047986027c35b03cd163 -Author: Matthew McClintock -Date: Wed Jun 28 10:42:24 2006 -0500 - - * Patch to modify ft_build.c to update flat device trees in place Patch by Matthew McClintock 26-June-2006 - -commit 0267768eddc5ca7bc1865bc40c866829ac5efbfe -Author: Matthew McClintock -Date: Wed Jun 28 10:41:37 2006 -0500 - - * Modify bootm command to support booting with flat device trees Patch by Matthew McClintock 26-June-2006 - -commit 8fc8bd2cc479b6cd188fdede4010e0e052970b8a -Author: John Traill -Date: Wed Aug 9 14:33:50 2006 +0100 - - Add Rapidio support for the MPC8641HPCN - - Signed-off-by: John Traill - -commit 91a414c7d1fb0eac912592cd995b30c9f23045c9 -Author: John Traill -Date: Tue Aug 8 11:32:43 2006 +0100 - - Fix caslat calculation - - Signed-off-by: John Traill - -commit 709d3073e74153278e7904a70819bbef7df50e1a -Author: Jon Loeliger -Date: Thu Aug 3 16:17:56 2006 -0500 - - Convert to mac-address in ethernet nodes. - -commit 71748af833ca1017edf1415be376366ff2937d17 -Author: Haiying Wang -Date: Fri Jul 28 12:41:35 2006 -0400 - - Correct the irq value of DUART2 - -commit 9cb3e8816ae4d854e7dc22128c3eea3d70bb982c -Author: Haiying Wang -Date: Fri Jul 28 12:41:41 2006 -0400 - - Change the space size of PEX IO in README - -commit 239db37c94f7a92941c4465feceb867c609241c5 -Author: Haiying Wang -Date: Fri Jul 28 12:41:18 2006 -0400 - - Move get_board_sys_clk to board directory - -commit 492900b985439fbce1a118afde1e35def870db03 -Author: John Traill -Date: Fri Jul 28 09:03:54 2006 +0100 - - Fix 8641HPCN pollution - -commit 515ab8a62e8574e2babc6e8dcc43544ad221c5b2 -Author: John Traill -Date: Fri Jul 28 08:16:06 2006 +0100 - - Fix 8641HPCN timebase - -commit c86360b830f1eecd7a72208575dde4f57879faea -Author: Zhang Wei -Date: Fri Jul 28 00:01:34 2006 +0800 - - Fixed OF device tree of mpc86xxhpcn board. - - The changes works in with kernel irq mapping rework. - - Signed-off-by: Zhang Wei - -commit bea3f28d285942bf3f7ab339ce85178ded544225 -Author: Haiying Wang -Date: Wed Jul 12 10:48:05 2006 -0400 - - Add support for reading and writing mac addresses to or from ID EEPROM. - - Added code for reading and writing Mac addresses to/from ID EEPROM(0x57). - With attached patch, we can use command "mac/mac read/mac save/" - to read and write EEPROM under u-boot prompt. - - U-boot will calculate the checksum of EEPROM while bootup, - if it is right, then u-boot will check whether the mac address - of eTSEC0/1/2/3 is availalbe (non-zero). - - If there is mac address availabe in EEPROM, u-boot will use it, - otherewise, u-boot will use the mac address defined in - MPC8641HPCN.h. This matches the requirement to set unique mac address - for each TSEC port. - - Signed-off-by: Haiying Wang - Signed-off-by: York Sun - -commit fcb28e763415e0e4e66b0f45842d1557ae198e5e -Author: Jin Zhengxiong -Date: Thu Jul 13 10:35:10 2006 -0500 - - Fixed initrd issue by define big RAM - - Signed-off-by:Jason Jin - -commit e6cd2a1785d74ec3d30a86f1cb360be8de478151 -Author: Jason Jin -Date: Fri Jul 7 10:01:45 2006 -0500 - - We made a u-boot patch to fix the hang up issue - when booting filesystem from ramdisk. - - Signed-off-by:Jason Jin - -commit 38433ccc5850ee70549af0b2bc5b920355ef5388 -Author: Matthew McClintock -Date: Wed Jun 28 10:47:03 2006 -0500 - - * Switched default PCI speed for 8540 ADS back to 33MHz - * Added comments and a printf to warn that PCI-X won't - work at 33MHz - Patch by Andy Fleming 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit e4c2a0eb0c3e3ffbf824800184ee42bdc99d5b19 -Author: Matthew McClintock -Date: Wed Jun 28 10:46:35 2006 -0500 - - * Fixed a bug where 8555 PCI code used the old variable and - function names - Patch by Andy Fleming 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit cbfc7ce756b88eb26e5537bc7b625c445c6dcfac -Author: Matthew McClintock -Date: Wed Jun 28 10:46:13 2006 -0500 - - * Added VIA configuration table - * Added support for PCI2 on CDS - Patch by Andy Fleming 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc -Author: Matthew McClintock -Date: Wed Jun 28 10:45:41 2006 -0500 - - * Fixed PCI memory definitions - Patch by Andy Fleming 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit 087454609e47295443af793a282cddcd91a5f49c -Author: Matthew McClintock -Date: Wed Jun 28 10:45:17 2006 -0500 - - * Added support for initializing second PCI bus on 85xx - Patch by Andy Fleming 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit b636aaeb6fd516a442fb611bbeeddf3077a687fb -Author: Matthew McClintock -Date: Wed Jun 28 10:44:49 2006 -0500 - - * Added PCI-X #defines for PCI-X initialization - Patch by Andy Fleming on 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit 20abbc6fffa115690107cc942c7abf84bdc03a1b -Author: Matthew McClintock -Date: Wed Jun 28 10:44:23 2006 -0500 - - * Made sure the code which disables prefetch for PCI devices - sets the size of the prefetch region to 0 - Patch by Andy Fleming on 17-Mar-2006 - - Signed-off-by: Andy Fleming - -commit 40d5fa35d02df22580593bf0039ab173367e8ef0 -Author: Matthew McClintock -Date: Wed Jun 28 10:43:36 2006 -0500 - - * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards - Patch by Jon Loeliger 17-Jan-2006 - - Signed-off-by: Jon Loeliger - -commit be7e8b0cb5a0c49dc180075b96df296a893bf146 -Author: Matthew McClintock -Date: Wed Jun 28 10:43:00 2006 -0500 - - * Removed the oftree.dts for stxxtx in light of the changes - to the flat device tree handling code - Patch by Matthew McClintock 26-June-2006 - -commit 1b380ec225665e73959677f3893dc658c5925e05 -Author: Matthew McClintock -Date: Wed Jun 28 10:42:24 2006 -0500 - - * Patch to modify ft_build.c to update flat device trees in place - Patch by Matthew McClintock 26-June-2006 - -commit 98a9c4d468a942a09ebe8979bec508017f3e4462 -Author: Matthew McClintock -Date: Wed Jun 28 10:41:37 2006 -0500 - - * Modify bootm command to support booting with flat device trees - Patch by Matthew McClintock 26-June-2006 - -commit da012ab661fd4ab169dd7b9b32201a4df62cf34a -Author: Jin Zhengxiong -Date: Wed Jun 28 08:43:56 2006 -0500 - - Change Id to symbolic name for RTL8139 - - Signed-off-by: Jason Jin - -commit bc09cf3c2bfb8d54c659cbb332f79d0950982fd0 -Author: Jin Zhengxiong-R64188 -Date: Tue Jun 27 18:12:10 2006 +0800 - - Fix RTL8139 in big endian - - signed-off-by: Jason Jin - signed-off-by: Wei Zhang - -commit fcfb9a57947fc203b99fe81ab0578f7286261f9f -Author: Jin Zhengxiong-R64188 -Date: Tue Jun 27 18:12:23 2006 +0800 - - Fix Tsec bug when no link - - When tftp a non-exist file from the tftp server, u-boot will check - the link of all eth port. The original file will return wrong link - state on the no link ports. - - signed-off-by: Jason Jin - -commit bd22c2b97514fbfb0e03bd9c72b3445e4dbd57e2 -Author: Jin Zhengxiong-R64188 -Date: Tue Jun 27 18:12:02 2006 +0800 - - Fix bug for io_bar size during pci scan - - During the pci scan process, Some devices return bar_reponse with the - highest bytes 0, such as the pci bridge in uli1575 return bar_response - with 0xffffff, So the bar_size should be manually set under 64K. - - Signed-off-by: Jason Jin - -commit fa7db9c377bc2353a17bf1d381d65a6c418728f0 -Author: Jin Zhengxiong-R64188 -Date: Tue Jun 27 18:11:54 2006 +0800 - - Enable PCIE1 for MPC8641HPCN board - - Signed-off-by: Jason Jin - -commit 99d70e3a47affb9bae041a2caece7cd516e213b3 -Author: Wolfgang Denk -Date: Mon Jun 26 11:06:00 2006 +0200 - - More code cleanup - -commit 684623ce92c5fd32e7db2d6e016945a67c5ffaba -Author: Jon Loeliger -Date: Thu Jun 22 08:51:46 2006 -0500 - - Fix bug in 8641hpcn reset command with no args. - - Signed-off-by: Haiying Wang - Acked-by: Jon Loeliger - -commit 8be429a5ddbf0ebe2d94174ba58fcfc7a24285dc -Author: Zhang Wei -Date: Tue Jun 20 17:47:15 2006 +0800 - - Reworked IRQ mapping in OF-tree. - -commit 0e4c2a17ca34001ed36d259f13cb88ada4611a8c -Author: Jon Loeliger -Date: Thu Jun 15 21:33:37 2006 -0500 - - Do not enable address translation on secondary CPUs. - Do not set up BATs on secondary CPUs. Let Linux do the nasty. - - Signed-off-by: Jon Loeliger - -commit 386eda022473394ad8f36b86f2bdc9b4cb816291 -Author: Wolfgang Denk -Date: Wed Jun 14 18:14:56 2006 +0200 - - Code cleanup - -commit 16c8d5e76ae0f78f39a60608574adfe0feb9cc70 -Author: Wolfgang Denk -Date: Wed Jun 14 17:45:53 2006 +0200 - - Various USB related patches - - Add support for mpc8xx USB device. - - Add support for Common Device Class - Abstract Control Model USB console. - - Add support for flow control in USB slave devices. - - Add support for switching between gserial and cdc_acm using environment. - - Minor changes to usbdcore_omap1510.c usbdcore_omap1510.h - - Update usbcore slightly to ease host enumeration. - - Fix non-portable endian problems in usbdcore and usbdcore_ep0. - - Add AdderUSB_config as a defconfig to enable usage of the USB console - by default with the Adder87x U-Boot port. - Patches by Bryan O'Donoghue , 29 May 2006 - -commit 8ecc971618f56029ad99d3516f8b297a6ed58971 -Author: Jon Loeliger -Date: Wed Jun 7 10:53:55 2006 -0500 - - Fix a get_board_sys_clk() use-before-def warning. - - Signed-off-by: Jon Loeliger - -commit d9bf4858fca5aa4d651b283270f77da72ebadfd5 -Author: Jon Loeliger -Date: Wed Jun 7 10:52:49 2006 -0500 - - Allow DTC path to be passed in. - - Signed-off-by: Jon Loeliger - -commit c83ae9ea6d93abbe751bf8a3396236a084e56f87 -Author: Haiying Wang -Date: Tue Jun 6 16:54:29 2006 -0400 - - Modify the IRQ of DUART2 - -commit c934f655f9aeca70a5c5f88b465d9e9d57a8d22e -Author: Jon Loeliger -Date: Wed May 31 13:55:35 2006 -0500 - - Review cleanups. - - Signed-off-by: Jon Loeliger - -commit cb5965fb95b77a49f4e6af95248e0c849f4af03e -Author: Jon Loeliger -Date: Wed May 31 12:44:44 2006 -0500 - - White space cleanup. - Some 80-column cleanups. - Convert printf() to puts() where possible. - Use #include "spd_sdram.h" as needed. - Enhanced reset command usage message a bit. - - Signed-off-by: Jon Loeliger - -commit 3d5c5be547445dd3bd2eb7368d80df03ea437970 -Author: Jon Loeliger -Date: Wed May 31 11:39:34 2006 -0500 - - Removed unneeded local_bus_init() from 8641HPCN board. - - Signed-off-by: Jon Loeliger - -commit 4d3d729c16c392d2982d3266b659d333c927697d -Author: Jon Loeliger -Date: Wed May 31 11:24:28 2006 -0500 - - Moved mpc8641hpcn_board_reset() out of cpu/ into board/. - - Signed-off-by: Jon Loeliger - -commit b2a941de060350ad15878d8219825f4950e9bb8e -Author: Jon Loeliger -Date: Wed May 31 10:07:28 2006 -0500 - - Remove dead debug code. - - Signed-off-by: Jon Loeliger - -commit 126aa70f10ba3d20e0a6f4d32328250513b77770 -Author: Jon Loeliger -Date: Tue May 30 17:47:00 2006 -0500 - - Move mpc86xx PIXIS code to board directory - - First cut at moving the PIXIS platform code out of - the 86xx cpu directory and into board/mpc8641hpcn - where it belongs. - - Signed-off-by: Jon Loeliger - -commit ddf83a2fcef1a670c45fc585119dcc1fe062c4a9 -Author: Markus Klotzbuecher -Date: Tue May 30 16:56:14 2006 +0200 - - Support generic OHCI support for the s3c24x0 cpu. - -commit 38cee12dcfcc257371c901c7e13e58ecab0a35d8 -Author: Haiying Wang -Date: Tue May 30 09:10:32 2006 -0500 - - Improve "reset" command's interaction with watchdog. - - "reset altbank" will reset another bank WITHOUT watch dog timer enabled - "reset altbank wd" will reset another bank WITH watch dog enabled - "diswd" will disable watch dog after u-boot boots up successfully - - Signed-off-by: Haiying Wang - -commit 70205e5a6ddc8528b11db9eb4d3fa0209d9fce2a -Author: Haiying Wang -Date: Tue May 30 08:51:19 2006 -0500 - - Fix two SDRAM setup bugs. - - Fix ECC setup bug. - Enable 1T/2T based on number of DIMMs present. - - Signed-off-by: Haiying Wang - -commit d11fec5015334deb2010e36ce00bb118cc5429a5 -Author: Haiying Wang -Date: Fri May 26 10:24:48 2006 -0500 - - Add first draft of the MPC8641HPCN doc/README. - - Signed-off-by: Jon Loeliger - -commit ed45d6c930b5939718a87ee12e25cf9a05978d4a -Author: Haiying Wang -Date: Fri May 26 10:13:04 2006 -0500 - - Added pci@8000 block. - Updated ethernet interrupt mappings (moved up 48). - Cleaned up a few comments. - - Signed-off-by: Jon Loeliger - -commit 3033ebb20fd7c372c7bca3c9955a4692bb2240b7 -Author: Haiying Wang -Date: Fri May 26 10:01:16 2006 -0500 - - Allow args on reset command. - - Signed-off-by: Jon Loeliger - -commit 301f1aa384d0edcae6a22fd9adb933ad71695ecc -Author: Markus Klotzbuecher -Date: Tue May 23 13:38:35 2006 +0200 - - Changed the mp2usb (at91rm9200) board to use the generic OHCI driver. Some - fixes to the latter. - -commit 24e37645e7378b20fa8f20e2996c8fb8e90c70c9 -Author: Markus Klotzbuecher -Date: Tue May 23 10:33:11 2006 +0200 - - More cleanup for the delta board and the generic usb_ohci driver. Added - CFG_USB_BOARD_INIT and CFG_USB_CPU_INIT for enabling board and cpu specific - initialization and cleanup hooks respectively. - -commit 3e326ece9eba8184f5d48aa4fb87760a8f6f0f10 -Author: Markus Klotzbuecher -Date: Mon May 22 16:33:54 2006 +0200 - - This patch adds USB storage support for the delta board. This is the first - board to make use of a generic OHCI driver, that calls hooks for board - dependant initialization. - -commit 14e37081ff3cac7ebe6e93836523429853b6b292 -Author: Jon Loeliger -Date: Fri May 19 13:28:39 2006 -0500 - - Change arbitration to round-robin for SMP linux. - -commit 9a655876e5995be80f49054e2509500e871e4d3a -Author: Jon Loeliger -Date: Fri May 19 13:26:34 2006 -0500 - - Enable dual DDR controllers and interleaving. - -commit 586d1d5abd3e525f1e1d9b81e5a61a4da6b2fa3c -Author: Jon Loeliger -Date: Fri May 19 13:22:44 2006 -0500 - - Update 86xx address map and LAWBARs. - -commit cccce5d0581bb0ba4602799a4b5112e58d1579cb -Author: Jon Loeliger -Date: Fri May 19 13:14:15 2006 -0500 - - Remove L2 Cache invalidate polling. - -commit f35ec68fb066cec0e36294bfe07dec2d4e8ad3a8 -Author: Jon Loeliger -Date: Fri May 19 12:33:09 2006 -0500 - - Enable 2nd CPU and I2C. - -commit bf690dcb512d34c4fceec0eb1e5c0e88a9db5d54 -Author: Jon Loeliger -Date: Mon May 15 07:26:56 2006 -0500 - - Update interrupt mapping. - -commit 6cfea33477b04b63ed47386ed1629529484c33ba -Author: Haiying Wang -Date: Wed May 10 09:38:06 2006 -0500 - - Remove unneeded INIT_RAM_LOCK cache twiddling. - Correctly tracks r29 as global data pointer now. - - Signed-off-by: Haiying Wang - -commit d4dd317b58c126a2a7e73f4764ecc1a7c97f876c -Author: Jon Loeliger -Date: Wed May 10 09:33:07 2006 -0500 - - Remove unnecessary flash.c file. - -commit 18b6c8cd8af6cc7f35180cedc4adb3236cc1a1b8 -Author: Jon Loeliger -Date: Tue May 9 08:23:49 2006 -0500 - - Get MPC8641HPCN flash images working. - - Enable the CFI driver. - Remove bogus LAWBAR7 cruft. - Use correct TEXT_BASE, Fixup load script. - Enable SPD EEPROM during DDR setup. - Use generic RFC 1918 IP addresses by default. - -commit 5c9efb36a6b5431423f52888a0e3b4b515fe7eca -Author: Jon Loeliger -Date: Thu Apr 27 10:15:16 2006 -0500 - - Cleanup whitespaces and style issues. - Removed //-style comments. - Use 80-column lines. - Remove trailing whitespace. - Remove dead code and debug cruft. - -commit a2320a6bf8113a09544c42d160d10ac69d049a03 -Author: Jon Loeliger -Date: Thu Apr 27 08:22:39 2006 -0500 - - Revert bad PCI prefetch limit change. - -commit debb7354d1ea4f694154818df5e5b523f5c1cc1d -Author: Jon Loeliger -Date: Wed Apr 26 17:58:56 2006 -0500 - - Initial support for MPC8641 HPCN board. +====================================================================== diff --git a/CREDITS b/CREDITS index 2b0dab760..32d3060c3 100644 --- a/CREDITS +++ b/CREDITS @@ -117,7 +117,7 @@ N: Arun Dharankar E: ADharankar@ATTBI.Com D: threads / scheduler example code -N: K?ri Dav??sson +N: Kári Davíðsson E: kd@flaga.is D: FLAGA DM Support @@ -143,15 +143,10 @@ E: info@elste.org D: Port for the ModNET50 Board, NET+50 CPU Port W: http://www.imms.de -N: Daniel Engstr?m +N: Daniel Engström E: daniel@omicron.se D: x86 port, Support for sc520_cdp board -N: Hayden Fraser -E: Hayden.Fraser@freescale.com -D: Support for ColdFire MCF5253 -W: www.freescale.com - N: Dr. Wolfgang Grandegger E: wg@denx.de D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards @@ -165,15 +160,6 @@ N: Thomas Frieden E: ThomasF@hyperion-entertainment.com D: Support for AmigaOne -N: Niklaus Giger -E: niklaus.giger@netstal.com -D: Support for HCU(x) boards -W: www.netstal.com - -N: Paul Gortmaker -E: paul.gortmaker@windriver.com -D: Support for WRS SBC8347/8349 boards - N: Frank Gottschling E: fgottschling@eltec.de D: Support for ELTEC MHPC/BAB7xx/ELPPC boards, cfb-console, i8042, SMI LynxEM @@ -236,10 +222,6 @@ E: mark.jonas@freescale.com D: Support for Freescale Total5200 platform W: http://www.mobilegt.com/ -N: Mark Jonas -E: mark.jonas@de.bosch.com -D: Support for MPR2 board - N: Sam Song E: samsongshu@yahoo.com.cn D: Port to the RPXlite_DW board @@ -266,10 +248,6 @@ E: Raghu.Krishnaprasad@fci.com D: Support for Adder-II MPC852T evaluation board W: http://www.forcecomputers.com -N: Sergey Kubushyn -E: ksi@koi8.net -D: Support for various TI DaVinci based boards. - N: Bernhard Kuhn E: bkuhn@metrowerks.com D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards @@ -292,11 +270,6 @@ E: team@leox.org D: Support for LEOX boards, DS164x RTC W: http://www.leox.org -N: TsiChung Liew -E: Tsi-Chung.Liew@freescale.com -D: Support for ColdFire MCF523x, MCF532x, MCF5445x, MCF547x_8x -W: www.freescale.com - N: Leif Lindholm E: leif.lindholm@i3micro.com D: Support for AMD dbau1550 board. @@ -307,20 +280,10 @@ D: Support for Nios Stratix Development Kit (DK-1S10) D: Support for SSV ADNP/ESC1 (Nios Cyclone) W: http://www.li-pro.net -N: Dave Liu -E: daveliu@freescale.com -D: Support for MPC8315, MPC832x, MPC8360, MPC837x -W: www.freescale.com - N: Raymond Lo E: lo@routefree.com D: Support for DOS partitions -N: James MacAulay -E: james.macaulay@amirix.com -D: Suppport for Amirix AP1000 -W: www.amirix.com - N: Dan Malek E: dan@embeddedalley.com D: FADSROM, the grandfather of all of this @@ -343,7 +306,7 @@ N: Frank Morauf E: frank.morauf@salzbrenner.com D: Support for Embedded Planet RPX Super Board -N: David M?ller +N: David Müller E: d.mueller@elsoft.ch D: Support for Samsung ARM920T SMDK2410 eval board @@ -395,14 +358,9 @@ E: dan.poirot@windriver.com D: Support for the Wind River sbc405, sbc8240 board W: http://www.windriver.com -N: Stelian Pop -E: stelian.pop@leadtechdesign.com -D: Atmel AT91CAP9ADK support - N: Stefan Roese -E: sr@denx.de -D: AMCC PPC4xx Support -W: http://www.denx.de +E: stefan.roese@esd-electronics.com +D: AMCC PPC401/403/405GP Support; Windows environment support N: Erwin Rol E: erwin@muffin.org @@ -424,27 +382,13 @@ N: Paolo Scaffardi E: arsenio@tin.it D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more -N: Andre Schwarz -E: andre.schwarz@matrix-vision.de -D: Support for Matrix Vision boards (MVBLM7/MVBC_P) - N: Robert Schwebel E: r.schwebel@pengutronix.de D: Support for csb226, logodl and innokom boards (PXA2xx) -N: Aaron Sells -E: sellsa@embeddedplanet.com -D: Support for EP82xxM - N: Art Shipkowski E: art@videon-central.com D: Support for NetSilicon NS7520 -D: Support for ColdFire MCF5275 - -N: Michal Simek -E: monstr@monstr.eu -D: Support for Microblaze, ML401, XUPV2P board -W: www.monstr.eu N: Yasushi Shoji E: yashi@atmark-techno.com @@ -459,11 +403,6 @@ E: andrea.scian@dave-tech.it D: Port to B2 board W: www.dave-tech.it -N: Timur Tabi -E: timur@freescale.com -D: Support for MPC8349E-mITX -W: www.freescale.com - N: Rob Taylor E: robt@flyingpig.com D: Port to MBX860T and Sandpoint8240 @@ -518,27 +457,7 @@ E: azu@sysgo.de D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM W: www.elinos.com -N: Nobuhiro Iwamatsu -E: iwamatsu@nigauri.org -D: Support for SuperH, MS7750SE01 and MS7722SE01 boards. -W: http://www.nigauri.org/~iwamatsu/ - -N: Alan Lu -E: alnalu001@gmail.com -D: Support for Artila M-501 starter kit -W: http://www.artila.com/ - -N: Kimmo Leppala -E: kimmo.leppala@sysart.fi -D: Support for Artila M-501 starter kit -W: http://www.sysart.fi/ - -N: Timo Tuunainen -E: timo.tuunainen@sysart.fi -D: Support for Artila M-501 starter kit -W: http://www.sysart.fi/ - -N: Philip Balister -E: philip@opensdr.com -D: Port to Lyrtech SFFSDR development board. -W: www.opensdr.com +N: James MacAulay +E: james.macaulay@amirix.com +D: Suppport for Amirix AP1000 +W: www.amirix.com diff --git a/MAINTAINERS b/MAINTAINERS index 777d14186..e1baa422a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14,264 +14,218 @@ # PowerPC Systems: # # # # Maintainer Name, Email Address # -# Board CPU # +# Board CPU # ######################################################################### Greg Allen - UTX8245 MPC8245 + UTX8245 MPC8245 Pantelis Antoniou - NETVIA MPC8xx + NETVIA MPC8xx Reinhard Arlt - cpci5200 MPC5200 - mecp5200 MPC5200 - pf5200 MPC5200 + cpci5200 MPC5200 + pf5200 MPC5200 - CPCI750 PPC750FX/GX + CPCI750 PPC750FX/GX Yuli Barcohen - Adder MPC87x/MPC852T - ep8248 MPC8248 - ISPAN MPC8260 - MPC8260ADS MPC826x/MPC827x/MPC8280 - Rattler MPC8248 - ZPC1900 MPC8265 - -Michael Barkowski - - MPC8323ERDB MPC8323 + Adder MPC87x/MPC852T + ep8248 MPC8248 + ISPAN MPC8260 + MPC8260ADS MPC826x/MPC827x/MPC8280 + Rattler MPC8248 + ZPC1900 MPC8265 Jerry Van Baren - sacsng MPC8260 + sacsng MPC8260 Oliver Brown - gw8260 MPC8260 + gw8260 MPC8260 Conn Clark - ESTEEM192E MPC8xx - -Joe D'Abbraccio - - MPC837xERDB MPC837x + ESTEEM192E MPC8xx Kári Davíðsson - FLAGADM MPC823 + FLAGADM MPC823 Torsten Demke - eXalion MPC824x + eXalion MPC824x Wolfgang Denk - IceCube_5100 MGT5100 - IceCube_5200 MPC5200 + IceCube_5100 MGT5100 + IceCube_5200 MPC5200 - AMX860 MPC860 - ETX094 MPC850 - FPS850L MPC850 - FPS860L MPC860 - ICU862 MPC862 - IP860 MPC860 - IVML24 MPC860 - IVML24_128 MPC860 - IVML24_256 MPC860 - IVMS8 MPC860 - IVMS8_128 MPC860 - IVMS8_256 MPC860 - LANTEC MPC850 - LWMON MPC823 - NC650 MPC852 - R360MPI MPC823 - RMU MPC850 - RRvision MPC823 - SM850 MPC850 - SPD823TS MPC823 - TQM823L MPC823 - TQM823L_LCD MPC823 - TQM850L MPC850 - TQM855L MPC855 - TQM860L MPC860 - TQM860L_FEC MPC860 - c2mon MPC855 - hermes MPC860 - lwmon MPC823 - pcu_e MPC855 + AMX860 MPC860 + ETX094 MPC850 + FPS850L MPC850 + FPS860L MPC860 + ICU862 MPC862 + IP860 MPC860 + IVML24 MPC860 + IVML24_128 MPC860 + IVML24_256 MPC860 + IVMS8 MPC860 + IVMS8_128 MPC860 + IVMS8_256 MPC860 + LANTEC MPC850 + LWMON MPC823 + NC650 MPC852 + R360MPI MPC823 + RMU MPC850 + RRvision MPC823 + SM850 MPC850 + SPD823TS MPC823 + TQM823L MPC823 + TQM823L_LCD MPC823 + TQM850L MPC850 + TQM855L MPC855 + TQM860L MPC860 + TQM860L_FEC MPC860 + c2mon MPC855 + hermes MPC860 + lwmon MPC823 + pcu_e MPC855 - CU824 MPC8240 - Sandpoint8240 MPC8240 - SL8245 MPC8245 + CU824 MPC8240 + Sandpoint8240 MPC8240 + SL8245 MPC8245 - ATC MPC8250 - PM825 MPC8250 + ATC MPC8250 + PM825 MPC8250 - TQM8255 MPC8255 + TQM8255 MPC8255 - CPU86 MPC8260 - PM826 MPC8260 - TQM8260 MPC8260 + CPU86 MPC8260 + PM826 MPC8260 + TQM8260 MPC8260 - P3G4 MPC7410 + P3G4 MPC7410 - PCIPPC2 MPC750 - PCIPPC6 MPC750 + PCIPPC2 MPC750 + PCIPPC6 MPC750 - EXBITGEN PPC405GP + EXBITGEN PPC405GP Jon Diekema - sbc8260 MPC8260 + sbc8260 MPC8260 Dave Ellis - SXNI855T MPC8xx + SXNI855T MPC8xx Thomas Frieden - AmigaOneG3SE MPC7xx + AmigaOneG3SE MPC7xx Matthias Fuchs - ADCIOP IOP480 (PPC401) - APC405 PPC405GP - AR405 PPC405GP - ASH405 PPC405EP - CANBT PPC405CR - CPCI2DP PPC405GP - CPCI405 PPC405GP - CPCI4052 PPC405GP - CPCI405AB PPC405GP - CPCI405DT PPC405GP - CPCIISER4 PPC405GP - DASA_SIM IOP480 (PPC401) - DP405 PPC405EP - DU405 PPC405GP - DU440 PPC440EPx - G2000 PPC405EP - HH405 PPC405EP - HUB405 PPC405EP - OCRTC PPC405GP - ORSG PPC405GP - PCI405 PPC405GP - PLU405 PPC405EP - PMC405 PPC405GP - PMC440 PPC440EPx - VOH405 PPC405EP - VOM405 PPC405EP - WUH405 PPC405EP - CMS700 PPC405EP - -Niklaus Giger - - HCU4 PPC405GPr - MCU25 PPC405GPr - HCU5 PPC440EPx + ADCIOP IOP480 (PPC401) + APC405 PPC405GP + AR405 PPC405GP + ASH405 PPC405EP + CANBT PPC405CR + CPCI2DP PPC405GP + CPCI405 PPC405GP + CPCI4052 PPC405GP + CPCI405AB PPC405GP + CPCI405DT PPC405GP + CPCI440 PPC440GP + CPCIISER4 PPC405GP + DASA_SIM IOP480 (PPC401) + DP405 PPC405EP + DU405 PPC405GP + G2000 PPC405EP + HH405 PPC405EP + HUB405 PPC405EP + OCRTC PPC405GP + ORSG PPC405GP + PCI405 PPC405GP + PLU405 PPC405EP + PMC405 PPC405GP + VOH405 PPC405EP + VOM405 PPC405EP + WUH405 PPC405EP + CMS700 PPC405EP Frank Gottschling - MHPC MPC8xx + MHPC MPC8xx - BAB7xx MPC740/MPC750 + BAB7xx MPC740/MPC750 Wolfgang Grandegger - CCM MPC855 + CCM MPC855 - PN62 MPC8240 - IPHASE4539 MPC8260 - SCM MPC8260 + PN62 MPC8240 + + IPHASE4539 MPC8260 + SCM MPC8260 Howard Gray - MVS1 MPC823 - -Joe Hamman - - sbc8548 MPC8548 - sbc8641d MPC8641D + MVS1 MPC823 Klaus Heydeck - KUP4K MPC855 - KUP4X MPC859 - -Gary Jennejohn - - quad100hd PPC405EP + KUP4K MPC855 + KUP4X MPC859 Murray Jensen - cogent_mpc8xx MPC8xx + cogent_mpc8xx MPC8xx - cogent_mpc8260 MPC8260 - hymod MPC8260 - -Larry Johnson - - korat PPC440EPx + cogent_mpc8260 MPC8260 + hymod MPC8260 Brad Kemp - ppmc8260 MPC8260 + ppmc8260 MPC8260 Sangmoon Kim - debris MPC8245 - KVME080 MPC8245 + debris MPC8245 + KVME080 MPC8245 Thomas Lange - GTH MPC860 - -Robert Lazarski - - ATUM8548 MPC8548 + GTH MPC860 The LEOX team - ELPT860 MPC860T - -Guennadi Liakhovetski - - linkstation MPC8241 - -Dave Liu - - MPC8315ERDB MPC8315 - MPC832XEMDS MPC832x - MPC8360EMDS MPC8360 - MPC837XEMDS MPC837x + ELPT860 MPC860T Nye Liu - ZUMA MPC7xx_74xx + ZUMA MPC7xx_74xx Jon Loeliger - MPC8540ADS MPC8540 - MPC8560ADS MPC8560 - MPC8541CDS MPC8541 - MPC8555CDS MPC8555 + MPC8540ADS MPC8540 + MPC8560ADS MPC8560 + MPC8541CDS MPC8541 + MPC8555CDS MPC8555 - MPC8641HPCN MPC8641D +Dan Malek -Dan Malek - - stxgp3 MPC85xx - stxssa MPC85xx - stxxtc MPC8xx + STxGP3 MPC85xx + STxXTc MPC8xx Eran Man - EVB64260_750CX MPC750CX + EVB64260_750CX MPC750CX Andrea "llandre" Marson @@ -279,75 +233,62 @@ Andrea "llandre" Marson Reinhard Meyer - TOP860 MPC860T - TOP5200 MPC5200 + TOP860 MPC860T + TOP5200 MPC5200 Tolunay Orkun - csb272 PPC405GP - csb472 PPC405GP + csb272 PPC405GP + csb472 PPC405GP John Otken - luan PPC440SP - taihu PPC405EP + luan PPC440SP Keith Outwater - GEN860T MPC860T - GEN860T_SC MPC860T + GEN860T MPC860T + GEN860T_SC MPC860T Frank Panno - ep8260 MPC8260 + ep8260 MPC8260 + +Peter Pearse + integratorcp All current ARM supplied & + supported core modules + - see http://www.arm.com + /products/DevTools + /Hardware_Platforms.html + versatile ARM926EJ-S + versatile ARM926EJ-S Denis Peter - MIP405 PPC4xx - PIP405 PPC4xx - -Kim Phillips - - MPC8349EMDS MPC8349 + MIP405 PPC4xx + PIP405 PPC4xx Daniel Poirot - sbc8240 MPC8240 - sbc405 PPC405GP + sbc8240 MPC8240 + sbc405 PPC405GP Stefan Roese - P3M7448 MPC7448 + uc100 MPC857 - uc100 MPC857 + TQM85xx MPC8540/8541/8555/8560 - TQM85xx MPC8540/8541/8555/8560 - - acadia PPC405EZ - alpr PPC440GX - bamboo PPC440EP - bunbinga PPC405EP - canyonlands PPC460EX - ebony PPC440GP - glacier PPC460GT - haleakala PPC405EXr - katmai PPC440SPe - kilauea PPC405EX - lwmon5 PPC440EPx - makalu PPC405EX - ocotea PPC440GX - p3p440 PPC440GP - pcs440ep PPC440EP - rainier PPC440GRx - sequoia PPC440EPx - sycamore PPC405GPr - taishan PPC440GX - walnut PPC405GP - yellowstone PPC440GR - yosemite PPC440EP - zeus PPC405EP - - P3M750 PPC750FX/GX/GL + bamboo PPC440EP + bunbinga PPC405EP + ebony PPC440GP + ocotea PPC440GX + p3p440 PPC440GP + pcs440ep PPC440EP + sycamore PPC405GPr + walnut PPC405GP + yellowstone PPC440GR + yosemite PPC440EP Yusdi Santoso @@ -355,405 +296,258 @@ Yusdi Santoso Travis Sawyer (travis.sawyer@sandburst.com> - KAREF PPC440GX - METROBOX PPC440GX - XPEDITE1K PPC440GX - -Heiko Schocher - - ids8247 MPC8247 - jupiter MPC5200 - mgcoge MPC8247 - mgsuvd MPC852 - municse MPC5200 - sc3 PPC405GP - uc101 MPC5200 - + KAREF PPC440GX + METROBOX PPC440GX + XPEDITE1K PPC440GX Peter De Schrijver - ML2 PPC4xx - -Andre Schwarz - - mvbc_p MPC5200 - mvblm7 MPC8343 - -Timur Tabi - - MPC8349E-mITX MPC8349 - MPC8349E-mITX-GP MPC8349 + ML2 PPC4xx Erik Theisen - W7OLMC PPC4xx - W7OLMG PPC4xx + W7OLMC PPC4xx + W7OLMG PPC4xx Jim Thompson - MUSENKI MPC8245/8241 - Sandpoint8245 MPC8245 + MUSENKI MPC8245/8241 + Sandpoint8245 MPC8245 Rune Torgersen - MPC8266ADS MPC8266 - - -David Updegraff - - CRAYL1 PPC4xx - -Anton Vorontsov - - MPC8360ERDK MPC8360 + MPC8266ADS MPC8266 Josef Wagner - CPC45 MPC8245 - PM520 MPC5200 + CPC45 MPC8245 + PM520 MPC5200 Stephen Williams - JSE PPC405GPr - -Roy Zang - - mpc7448hpc2 MPC7448 + JSE PPC405GPr John Zhan - svm_sc8xx MPC8xx + svm_sc8xx MPC8xx ------------------------------------------------------------------------- Unknown / orphaned boards: - ADS860 MPC8xx - FADS823 MPC8xx - FADS850SAR MPC8xx - FADS860T MPC8xx - GENIETV MPC8xx - IAD210 MPC8xx - MBX MPC8xx - MBX860T MPC8xx - NX823 MPC8xx - RPXClassic MPC8xx - RPXlite MPC8xx + ADS860 MPC8xx + FADS823 MPC8xx + FADS850SAR MPC8xx + FADS860T MPC8xx + GENIETV MPC8xx + IAD210 MPC8xx + MBX MPC8xx + MBX860T MPC8xx + NX823 MPC8xx + RPXClassic MPC8xx + RPXlite MPC8xx - ERIC PPC4xx + CRAYL1 PPC4xx + ERIC PPC4xx - MOUSSE MPC824x + MOUSSE MPC824x - RPXsuper MPC8260 - rsdproto MPC8260 + RPXsuper MPC8260 + rsdproto MPC8260 - EVB64260 MPC7xx_74xx + EVB64260 MPC7xx_74xx ######################################################################### # ARM Systems: # # # # Maintainer Name, Email Address # -# Board CPU # +# Board CPU # ######################################################################### Rowel Atienza - armadillo ARM720T + armadillo ARM720T Rishi Bhattacharya - omap5912osk ARM926EJS + omap5912osk ARM926EJS Cliff Brake - pxa255_idp xscale + pxa255_idp xscale Rick Bronson - AT91RM9200DK at91rm9200 + AT91RM9200DK at91rm9200 George G. Davis - assabet SA1100 - gcplus SA1100 + assabet SA1100 + gcplus SA1100 Thomas Elste - modnet50 ARM720T (NET+50) + modnet50 ARM720T (NET+50) Peter Figuli - wepep250 xscale + wepep250 xscale Marius Gröger - impa7 ARM720T (EP7211) - ep7312 ARM720T (EP7312) + impa7 ARM720T (EP7211) + ep7312 ARM720T (EP7312) Kshitij Gupta - omap1510inn ARM925T - omap1610inn ARM926EJS + omap1510inn ARM925T + omap1610inn ARM926EJS + +Kyle Harris + + lubbock xscale + cradle xscale + ixdp425 xscale Gary Jennejohn - smdk2400 ARM920T - trab ARM920T - -Konstantin Kletschke - scb9328 ARM920T + smdk2400 ARM920T + trab ARM920T Nishant Kamat - omap1610h2 ARM926EJS - -Sergey Kubushyn - - DV-EVM ARM926EJS - SONATA ARM926EJS - SCHMOOGIE ARM926EJS + omap1610h2 ARM926EJS Prakash Kumar - cerf250 xscale + cerf250 xscale David Müller - smdk2410 ARM920T - VCMA9 ARM920T + smdk2410 ARM920T + VCMA9 ARM920T Rolf Offermanns - shannon SA1100 - -Kyungmin Park - - apollon ARM1136EJS - -Peter Pearse - integratorcp All current ARM supplied & supported core modules - -see http://www.arm.com/products/DevTools/Hardware_Platforms.html - versatile ARM926EJ-S - versatile ARM926EJ-S + shannon SA1100 Dave Peverley - omap730p2 ARM926EJS - -Stelian Pop - - at91cap9adk ARM926EJS (AT91CAP9 SoC) - at91sam9260ek ARM926EJS (AT91SAM9260 SoC) - at91sam9261ek ARM926EJS (AT91SAM9261 SoC) - at91sam9263ek ARM926EJS (AT91SAM9263 SoC) - at91sam9rlek ARM926EJS (AT91SAM9RL SoC) + omap730p2 ARM926EJS Stefan Roese - ixdpg425 xscale - pdnb3 xscale - scpu xscale + ixdpg425 xscale + pdnb3 xscale Robert Schwebel - csb226 xscale - innokom xscale - -Michael Schwingen - - actux1 xscale - actux2 xscale - actux3 xscale - actux4 xscale + csb226 xscale + innokom xscale Andrea Scian - B2 ARM7TDMI (S3C44B0X) + B2 ARM7TDMI (S3C44B0X) Greg Ungerer - cm4008 ks8695p - cm4116 ks8695p - cm4148 ks8695p + cm4008 ks8695p + cm4116 ks8695p + cm4148 ks8695p Richard Woodruff - omap2420h4 ARM1136EJS + omap2420h4 ARM1136EJS Alex Züpke - lart SA1100 - dnp1110 SA1110 - -------------------------------------------------------------------------- - -Unknown / orphaned boards: - Board CPU Last known maintainer / Comment -......................................................................... - cradle xscale Kyle Harris / dead address - ixdp425 xscale Kyle Harris / dead address - lubbock xscale Kyle Harris / dead address + lart SA1100 + dnp1110 SA1110 ######################################################################### # x86 Systems: # # # # Maintainer Name, Email Address # -# Board CPU # +# Board CPU # ######################################################################### Daniel Engström - sc520_cdp x86 + sc520_cdp x86 ######################################################################### # MIPS Systems: # # # # Maintainer Name, Email Address # -# Board CPU # +# Board CPU # ######################################################################### Wolfgang Denk - incaip MIPS32 4Kc - purple MIPS64 5Kc + incaip MIPS32 4Kc + purple MIPS64 5Kc Thomas Lange - dbau1x00 MIPS32 Au1000 - gth2 MIPS32 Au1000 - -Vlad Lungu - qemu_mips MIPS32 + dbau1x00 MIPS32 Au1000 + gth2 MIPS32 Au1000 ######################################################################### # Nios-32 Systems: # # # # Maintainer Name, Email Address # -# Board CPU # +# Board CPU # ######################################################################### Stephan Linz - DK1S10 Nios-32 - ADNPESC1 Nios-32 + DK1S10 Nios-32 + ADNPESC1 Nios-32 Scott McNutt - DK1C20 Nios-32 + DK1C20 Nios-32 ######################################################################### # Nios-II Systems: # # # # Maintainer Name, Email Address # -# Board CPU # +# Board CPU # ######################################################################### Scott McNutt - PCI5441 Nios-II - PK1C20 Nios-II - EP1C20 Nios-II - EP1S10 Nios-II - EP1S40 Nios-II + PCI5441 Nios-II + PK1C20 Nios-II + EP1C20 Nios-II + EP1S10 Nios-II + EP1S40 Nios-II ######################################################################### # MicroBlaze Systems: # # # # Maintainer Name, Email Address # -# Board CPU # +# Board CPU # ######################################################################### Yasushi Shoji - SUZAKU MicroBlaze - -Michal Simek - - ML401 MicroBlaze - XUPV2P MicroBlaze + SUZAKU MicroBlaze ######################################################################### # Coldfire Systems: # # # # Maintainer Name, Email Address # -# Board CPU # +# Board CPU # ######################################################################### Matthias Fuchs - TASREG MCF5249 + TASREG MCF5249 -Hayden Fraser +Zachary P. Landau - M5253EVBE mcf52x2 - -TsiChung Liew - - M52277EVB mcf5227x - M5235EVB mcf52x2 - M5329EVB mcf532x - M5373EVB mcf532x - M54455EVB mcf5445x - M5475EVB mcf547x_8x - M5485EVB mcf547x_8x - -######################################################################### -# AVR32 Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Haavard Skinnemoen - - ATSTK1000 AT32AP7xxx - ATSTK1002 AT32AP7000 - ATSTK1003 AT32AP7001 - ATSTK1004 AT32AP7002 - ATSTK1006 AT32AP7000 - ATNGW100 AT32AP7000 - -######################################################################### -# SuperH Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Yusuke Goda - - MIGO-R SH7722 - -Nobuhiro Iwamatsu - - MS7750SE SH7750 - MS7722SE SH7722 - R7780MP SH7780 - R2DPlus SH7751R - SH7763RDP SH7763 - -Mark Jonas - - mpr2 SH7720 - -Yoshihiro Shimoda - - MS7720SE SH7720 - -######################################################################### -# Blackfin Systems: # -# # -# Maintainer Name, Email Address # -# Board CPU # -######################################################################### - -Mike Frysinger -Blackfin Team - - BF533-EZKIT BF533 - BF533-STAMP BF533 - BF537-STAMP BF537 - BF561-EZKIT BF561 + r5200 mcf52x2 ######################################################################### # End of MAINTAINERS list # diff --git a/MAKEALL b/MAKEALL index ee83ccab4..467a9bee0 100755 --- a/MAKEALL +++ b/MAKEALL @@ -8,17 +8,7 @@ else MAKE=make fi -if [ "${MAKEALL_LOGDIR}" ] ; then - LOG_DIR=${MAKEALL_LOGDIR} -else - LOG_DIR="LOG" -fi - -if [ ! "${BUILD_DIR}" ] ; then - BUILD_DIR="." -fi - -[ -d ${LOG_DIR} ] || mkdir ${LOG_DIR} || exit 1 +[ -d LOG ] || mkdir LOG || exit 1 LIST="" @@ -26,315 +16,110 @@ LIST="" ## MPC5xx Systems ######################################################################### -LIST_5xx=" \ - cmi_mpc5xx \ +LIST_5xx=" \ + cmi_mpc5xx \ " ######################################################################### ## MPC5xxx Systems ######################################################################### -LIST_5xxx=" \ - BC3450 \ - cm5200 \ - cpci5200 \ - EVAL5200 \ - fo300 \ - icecube_5100 \ - icecube_5200 \ - inka4x0 \ - lite5200b \ - mcc200 \ - mecp5200 \ - motionpro \ - munices \ - MVBC_P \ - o2dnt \ - pf5200 \ - PM520 \ - TB5200 \ - Total5100 \ - Total5200 \ - Total5200_Rev2 \ - TQM5200 \ - TQM5200_B \ - TQM5200S \ - v38b \ -" - -######################################################################### -## MPC512x Systems -######################################################################### - -LIST_512x=" \ - ads5121 \ +LIST_5xxx=" \ + BC3450 cpci5200 EVAL5200 icecube_5100 \ + icecube_5200 lite5200b mcc200 o2dnt \ + pf5200 PM520 TB5200 Total5100 \ + Total5200 Total5200_Rev2 TQM5200 TQM5200_B \ + TQM5200S \ " ######################################################################### ## MPC8xx Systems ######################################################################### -LIST_8xx=" \ - Adder87x \ - AdderII \ - ADS860 \ - AMX860 \ - c2mon \ - CCM \ - cogent_mpc8xx \ - ELPT860 \ - EP88x \ - ESTEEM192E \ - ETX094 \ - FADS823 \ - FADS850SAR \ - FADS860T \ - FLAGADM \ - FPS850L \ - GEN860T \ - GEN860T_SC \ - GENIETV \ - GTH \ - hermes \ - IAD210 \ - ICU862_100MHz \ - IP860 \ - IVML24 \ - IVML24_128 \ - IVML24_256 \ - IVMS8 \ - IVMS8_128 \ - IVMS8_256 \ - KUP4K \ - KUP4X \ - LANTEC \ - lwmon \ - MBX \ - MBX860T \ - mgsuvd \ - MHPC \ - MPC86xADS \ - MPC885ADS \ - MVS1 \ - NETPHONE \ - NETTA \ - NETTA2 \ - NETTA_ISDN \ - NETVIA \ - NETVIA_V2 \ - NX823 \ - pcu_e \ - QS823 \ - QS850 \ - QS860T \ - quantum \ - R360MPI \ - RBC823 \ - rmu \ - RPXClassic \ - RPXlite \ - RPXlite_DW \ - RRvision \ - SM850 \ - spc1920 \ - SPD823TS \ - svm_sc8xx \ - SXNI855T \ - TK885D \ - TOP860 \ - TQM823L \ - TQM823L_LCD \ - TQM850L \ - TQM855L \ - TQM860L \ - TQM885D \ - uc100 \ - v37 \ +LIST_8xx=" \ + Adder87x GENIETV MBX860T R360MPI \ + AdderII GTH MHPC RBC823 \ + ADS860 hermes MPC86xADS rmu \ + AMX860 IAD210 MPC885ADS RPXClassic \ + c2mon ICU862_100MHz MVS1 RPXlite \ + CCM IP860 NETPHONE RPXlite_DW \ + cogent_mpc8xx IVML24 NETTA RRvision \ + ELPT860 IVML24_128 NETTA2 SM850 \ + EP88x IVML24_256 NETTA_ISDN spc1920 \ + ESTEEM192E IVMS8 NETVIA SPD823TS \ + ETX094 IVMS8_128 NETVIA_V2 svm_sc8xx \ + FADS823 IVMS8_256 NX823 SXNI855T \ + FADS850SAR KUP4K pcu_e TOP860 \ + FADS860T KUP4X QS823 TQM823L \ + FLAGADM LANTEC QS850 TQM823L_LCD \ + FPS850L lwmon QS860T TQM850L \ + GEN860T MBX quantum TQM855L \ + GEN860T_SC TQM860L \ + TQM885D \ + uc100 \ + v37 \ " ######################################################################### ## PPC4xx Systems ######################################################################### -LIST_4xx=" \ - acadia \ - acadia_nand \ - ADCIOP \ - alpr \ - AP1000 \ - AR405 \ - ASH405 \ - bamboo \ - bamboo_nand \ - bubinga \ - CANBT \ - canyonlands \ - canyonlands_nand \ - CMS700 \ - CPCI2DP \ - CPCI405 \ - CPCI4052 \ - CPCI405AB \ - CPCI405DT \ - CPCIISER4 \ - CRAYL1 \ - csb272 \ - csb472 \ - DASA_SIM \ - DP405 \ - DU405 \ - DU440 \ - ebony \ - ERIC \ - EXBITGEN \ - G2000 \ - glacier \ - haleakala \ - haleakala_nand \ - hcu4 \ - hcu5 \ - HH405 \ - HUB405 \ - JSE \ - KAREF \ - katmai \ - kilauea \ - kilauea_nand \ - korat \ - luan \ - lwmon5 \ - makalu \ - mcu25 \ - METROBOX \ - MIP405 \ - MIP405T \ - ML2 \ - ml300 \ - ocotea \ - OCRTC \ - ORSG \ - p3p440 \ - PCI405 \ - pcs440ep \ - PIP405 \ - PLU405 \ - PMC405 \ - PMC440 \ - PPChameleonEVB \ - quad100hd \ - rainier \ - sbc405 \ - sc3 \ - sequoia \ - sequoia_nand \ - taihu \ - taishan \ - VOH405 \ - VOM405 \ - W7OLMC \ - W7OLMG \ - walnut \ - WUH405 \ - XPEDITE1K \ - yellowstone \ - yosemite \ - yucca \ - zeus \ +LIST_4xx=" \ + ADCIOP AP1000 AR405 ASH405 \ + bubinga CANBT CMS700 CPCI2DP \ + CPCI405 CPCI4052 CPCI405AB CPCI405DT \ + CPCI440 CPCIISER4 CRAYL1 csb272 \ + csb472 DASA_SIM DP405 DU405 \ + ebony ERIC EXBITGEN G2000 \ + HH405 HUB405 JSE KAREF \ + luan METROBOX MIP405 MIP405T \ + ML2 ml300 ocotea OCRTC \ + ORSG p3p440 PCI405 pcs440ep \ + PIP405 PLU405 PMC405 PPChameleonEVB \ + sbc405 VOH405 VOM405 W7OLMC \ + W7OLMG walnut WUH405 XPEDITE1K \ + yellowstone yosemite yucca bamboo \ " ######################################################################### ## MPC8220 Systems ######################################################################### -LIST_8220=" \ - Alaska8220 \ - Yukon8220 \ +LIST_8220=" \ + Alaska8220 Yukon8220 \ " ######################################################################### ## MPC824x Systems ######################################################################### -LIST_824x=" \ - A3000 \ - barco \ - BMW \ - CPC45 \ - CU824 \ - debris \ - eXalion \ - HIDDEN_DRAGON \ - linkstation_HGLAN \ - MOUSSE \ - MUSENKI \ - MVBLUE \ - OXC \ - PN62 \ - Sandpoint8240 \ - Sandpoint8245 \ - sbc8240 \ - SL8245 \ - utx8245 \ +LIST_824x=" \ + A3000 barco BMW CPC45 \ + CU824 debris eXalion HIDDEN_DRAGON \ + MOUSSE MUSENKI MVBLUE \ + OXC PN62 Sandpoint8240 Sandpoint8245 \ + sbc8240 SL8245 utx8245 \ " ######################################################################### ## MPC8260 Systems (includes 8250, 8255 etc.) ######################################################################### -LIST_8260=" \ - atc \ - cogent_mpc8260 \ - CPU86 \ - CPU87 \ - ep8248 \ - ep8260 \ - ep82xxm \ - gw8260 \ - hymod \ - IPHASE4539 \ - ISPAN \ - mgcoge \ - MPC8260ADS \ - MPC8266ADS \ - MPC8272ADS \ - PM826 \ - PM828 \ - ppmc8260 \ - Rattler8248 \ - RPXsuper \ - rsdproto \ - sacsng \ - sbc8260 \ - SCM \ - TQM8260_AC \ - TQM8260_AD \ - TQM8260_AE \ - TQM8272 \ - ZPC1900 \ +LIST_8260=" \ + atc cogent_mpc8260 CPU86 CPU87 \ + ep8248 ep8260 gw8260 hymod \ + IPHASE4539 ISPAN MPC8260ADS MPC8266ADS \ + MPC8272ADS PM826 PM828 ppmc8260 \ + Rattler8248 RPXsuper rsdproto sacsng \ + sbc8260 SCM TQM8260_AC TQM8260_AD \ + TQM8260_AE ZPC1900 \ " ######################################################################### ## MPC83xx Systems (includes 8349, etc.) ######################################################################### -LIST_83xx=" \ - MPC8313ERDB_33 \ - MPC8313ERDB_66 \ - MPC8315ERDB \ - MPC8323ERDB \ - MPC832XEMDS \ - MPC832XEMDS_ATM \ - MPC8349EMDS \ - MPC8349ITX \ - MPC8349ITXGP \ - MPC8360EMDS \ - MPC8360EMDS_ATM \ - MPC8360ERDK_33 \ - MPC8360ERDK_66 \ - MPC837XEMDS \ - MPC837XERDB \ - MVBLM7 \ - sbc8349 \ - TQM834x \ +LIST_83xx=" \ + TQM834x MPC8349EMDS \ " @@ -342,272 +127,111 @@ LIST_83xx=" \ ## MPC85xx Systems (includes 8540, 8560 etc.) ######################################################################### -LIST_85xx=" \ - ATUM8548 \ - MPC8540ADS \ - MPC8540EVAL \ - MPC8541CDS \ - MPC8544DS \ - MPC8548CDS \ - MPC8555CDS \ - MPC8560ADS \ - MPC8568MDS \ - PM854 \ - PM856 \ - sbc8540 \ - sbc8548 \ - sbc8560 \ - socrates \ - stxgp3 \ - stxssa \ - TQM8540 \ - TQM8541 \ - TQM8548 \ - TQM8555 \ - TQM8560 \ -" - -######################################################################### -## MPC86xx Systems -######################################################################### - -LIST_86xx=" \ - MPC8610HPCD \ - MPC8641HPCN \ - sbc8641d \ +LIST_85xx=" \ + MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \ + MPC8555CDS MPC8560ADS PM854 PM856 \ + sbc8540 sbc8560 stxgp3 TQM8540 \ + TQM8541 TQM8555 TQM8560 \ " ######################################################################### ## 74xx/7xx Systems ######################################################################### -LIST_74xx=" \ - DB64360 \ - DB64460 \ - EVB64260 \ - mpc7448hpc2 \ - P3G4 \ - p3m7448 \ - PCIPPC2 \ - PCIPPC6 \ - ZUMA \ +LIST_74xx=" \ + DB64360 DB64460 EVB64260 P3G4 \ + PCIPPC2 PCIPPC6 ZUMA \ " -LIST_7xx=" \ - BAB7xx \ - CPCI750 \ - ELPPC \ - p3m750 \ - ppmc7xx \ +LIST_7xx=" \ + BAB7xx CPCI750 ELPPC ppmc7xx \ " -######################################################################### -## PowerPC groups -######################################################################### - -LIST_TSEC=" \ - ${LIST_83xx} \ - ${LIST_85xx} \ - ${LIST_86xx} \ -" - -LIST_ppc=" \ - ${LIST_5xx} \ - ${LIST_512x} \ - ${LIST_5xxx} \ - ${LIST_8xx} \ - ${LIST_8220} \ - ${LIST_824x} \ - ${LIST_8260} \ - ${LIST_83xx} \ - ${LIST_85xx} \ - ${LIST_86xx} \ - ${LIST_4xx} \ - ${LIST_74xx} \ - ${LIST_7xx} \ -" +LIST_ppc="${LIST_5xx} ${LIST_5xxx} \ + ${LIST_8xx} \ + ${LIST_8220} ${LIST_824x} ${LIST_8260} \ + ${LIST_83xx} \ + ${LIST_85xx} \ + ${LIST_4xx} \ + ${LIST_74xx} ${LIST_7xx}" ######################################################################### ## StrongARM Systems ######################################################################### -LIST_SA=" \ - assabet \ - dnp1110 \ - gcplus \ - lart \ - shannon \ -" +LIST_SA="assabet dnp1110 gcplus lart shannon" ######################################################################### ## ARM7 Systems ######################################################################### -LIST_ARM7=" \ - ap7 \ - ap720t \ - armadillo \ - B2 \ - ep7312 \ - evb4510 \ - impa7 \ - integratorap \ - lpc2292sodimm \ - modnet50 \ - SMN42 \ +LIST_ARM7=" \ + armadillo B2 ep7312 evb4510 \ + impa7 integratorap ap7 ap720t \ + modnet50 \ " ######################################################################### ## ARM9 Systems ######################################################################### -LIST_ARM9=" \ - ap920t \ - ap922_XA10 \ - ap926ejs \ - ap946es \ - ap966 \ - cp920t \ - cp922_XA10 \ - cp926ejs \ - cp946es \ - cp966 \ - lpd7a400 \ - mx1ads \ - mx1fs2 \ - netstar \ - omap1510inn \ - omap1610h2 \ - omap1610inn \ - omap5912osk \ - omap730p2 \ - sbc2410x \ - scb9328 \ - smdk2400 \ - smdk2410 \ - trab \ - VCMA9 \ - versatile \ - versatileab \ - versatilepb \ - voiceblue \ - davinci_dvevm \ - davinci_schmoogie \ - davinci_sffsdr \ - davinci_sonata \ +LIST_ARM9=" \ + at91rm9200dk cmc_pu2 \ + ap920t ap922_XA10 ap926ejs ap946es \ + ap966 cp920t cp922_XA10 cp926ejs \ + cp946es cp966 lpd7a400 mp2usb \ + mx1ads mx1fs2 netstar omap1510inn \ + omap1610h2 omap1610inn omap730p2 sbc2410x \ + scb9328 smdk2400 smdk2410 trab \ + VCMA9 versatile versatileab versatilepb \ + voiceblue \ " ######################################################################### ## ARM10 Systems ######################################################################### -LIST_ARM10=" \ - integratorcp \ - cp1026 \ +LIST_ARM10=" \ + integratorcp cp1026 \ " ######################################################################### ## ARM11 Systems ######################################################################### -LIST_ARM11=" \ - cp1136 \ - omap2420h4 \ - apollon \ - imx31_litekit \ - imx31_phycore \ - mx31ads \ -" - -######################################################################### -## AT91 Systems -######################################################################### - -LIST_at91=" \ - at91cap9adk \ - at91rm9200dk \ - at91sam9260ek \ - at91sam9261ek \ - at91sam9263ek \ - at91sam9rlek \ - cmc_pu2 \ - csb637 \ - kb9202 \ - mp2usb \ - m501sk \ +LIST_ARM11=" \ + cp1136 omap2420h4 \ " ######################################################################### ## Xscale Systems ######################################################################### -LIST_pxa=" \ - cerf250 \ - cradle \ - csb226 \ - delta \ - innokom \ - lubbock \ - pleb2 \ - pxa255_idp \ - wepep250 \ - xaeniax \ - xm250 \ - xsengine \ - zylonite \ +LIST_pxa=" \ + adsvix cerf250 cradle csb226 \ + delta innokom lubbock pleb2 \ + pxa255_idp wepep250 xaeniax xm250 \ + xsengine zylonite \ " -LIST_ixp=" \ - actux1 \ - actux2 \ - actux3 \ - actux4 \ - ixdp425 \ - ixdpg425 \ - pdnb3 \ - scpu \ -" +LIST_ixp="ixdp425 ixdpg425 pdnb3" -######################################################################### -## ARM groups -######################################################################### -LIST_arm=" \ - ${LIST_SA} \ - ${LIST_ARM7} \ - ${LIST_ARM9} \ - ${LIST_ARM10} \ - ${LIST_ARM11} \ - ${LIST_at91} \ - ${LIST_pxa} \ - ${LIST_ixp} \ +LIST_arm=" \ + ${LIST_SA} \ + ${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11} \ + ${LIST_pxa} ${LIST_ixp} \ " ######################################################################### ## MIPS Systems (default = big endian) ######################################################################### -LIST_mips4kc=" \ - incaip \ - qemu_mips \ -" +LIST_mips4kc="incaip" -LIST_mips5kc=" \ - purple \ -" +LIST_mips5kc="purple" -LIST_au1xx0=" \ - dbau1000 \ - dbau1100 \ - dbau1500 \ - dbau1550 \ - dbau1550_el \ - gth2 \ -" +LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el gth2" -LIST_mips=" \ - ${LIST_mips4kc} \ - ${LIST_mips5kc} \ - ${LIST_au1xx0} \ -" +LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}" ######################################################################### ## MIPS Systems (little endian) @@ -617,56 +241,36 @@ LIST_mips4kc_el="" LIST_mips5kc_el="" -LIST_au1xx0_el=" \ - dbau1550_el \ - pb1000 \ -" +LIST_au1xx0_el="dbau1550_el" -LIST_mips_el=" \ - ${LIST_mips4kc_el} \ - ${LIST_mips5kc_el} \ - ${LIST_au1xx0_el} \ -" +LIST_mips_el="${LIST_mips4kc_el} ${LIST_mips5kc_el} ${LIST_au1xx0_el}" ######################################################################### ## i386 Systems ######################################################################### -LIST_I486=" \ - sc520_cdp \ - sc520_spunk \ - sc520_spunk_rel \ -" +LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel" -LIST_x86=" \ - ${LIST_I486} \ -" +LIST_x86="${LIST_I486}" ######################################################################### ## NIOS Systems ######################################################################### -LIST_nios=" \ - ADNPESC1 \ - ADNPESC1_base_32 \ - ADNPESC1_DNPEVA2_base_32\ - DK1C20 \ - DK1C20_standard_32 \ - DK1S10 \ - DK1S10_standard_32 \ - DK1S10_mtx_ldk_20 \ +LIST_nios=" \ + ADNPESC1 ADNPESC1_base_32 \ + ADNPESC1_DNPEVA2_base_32 \ + DK1C20 DK1C20_standard_32 \ + DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \ " ######################################################################### ## Nios-II Systems ######################################################################### -LIST_nios2=" \ - EP1C20 \ - EP1S10 \ - EP1S40 \ - PCI5441 \ - PK1C20 \ +LIST_nios2=" \ + EP1C20 EP1S10 EP1S40 \ + PCI5441 PK1C20 \ " ######################################################################### @@ -674,88 +278,19 @@ LIST_nios2=" \ ######################################################################### LIST_microblaze=" \ - ml401 \ - suzaku \ - xupv2p \ + suzaku " ######################################################################### ## ColdFire Systems ######################################################################### -LIST_coldfire=" \ - cobra5272 \ - EB+MCF-EV123 \ - EB+MCF-EV123_internal \ - idmr \ - M52277EVB \ - M5235EVB \ - M5249EVB \ - M5253EVBE \ - M5271EVB \ - M5272C3 \ - M5275EVB \ - M5282EVB \ - M5329AFEE \ - M5373EVB \ - M54455EVB \ - M5475AFE \ - M5485AFE \ - TASREG \ +LIST_coldfire=" \ + cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \ + M5271EVB M5272C3 M5282EVB TASREG \ + r5200 M5271EVB \ " -######################################################################### -## AVR32 Systems -######################################################################### - -LIST_avr32=" \ - atstk1002 \ - atstk1003 \ - atstk1004 \ - atstk1006 \ - atngw100 \ -" - -######################################################################### -## Blackfin Systems -######################################################################### - -LIST_blackfin=" \ - bf533-ezkit \ - bf533-stamp \ - bf537-stamp \ - bf561-ezkit \ -" - -######################################################################### -## SH Systems -######################################################################### - -LIST_sh3=" \ - mpr2 \ - ms7720se \ -" - -LIST_sh4=" \ - ms7750se \ - ms7722se \ - MigoR \ - r7780mp \ - r2dplus \ - sh7763rdp \ -" - -LIST_sh=" \ - ${LIST_sh3} \ - ${LIST_sh4} \ -" - -######################################################################### -## SPARC Systems -######################################################################### - -LIST_sparc="gr_xc3s_1500 gr_cpci_ax2000 gr_ep2s60 grsim grsim_leon2" - #----------------------------------------------------------------------- #----- for now, just run PPC by default ----- @@ -768,12 +303,8 @@ build_target() { ${MAKE} distclean >/dev/null ${MAKE} ${target}_config - - ${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \ - | tee ${LOG_DIR}/$target.ERR - - ${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \ - | tee -a ${LOG_DIR}/$target.MAKELOG + ${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR + ${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG } #----------------------------------------------------------------------- @@ -782,18 +313,13 @@ build_target() { for arg in $@ do case "$arg" in - arm|SA|ARM7|ARM9|ARM10|ARM11|at91|ixp|pxa \ - |avr32 \ - |blackfin \ - |coldfire \ - |microblaze \ - |mips|mips_el \ - |nios|nios2 \ - |ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \ - |sh|sh3|sh4 \ - |sparc \ - |x86|I486 \ - ) + ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \ + arm|SA|ARM7|ARM9|ARM10|ARM11|pxa|ixp| \ + microblaze| \ + mips|mips_el| \ + nios|nios2| \ + x86|I486| \ + coldfire) for target in `eval echo '$LIST_'${arg}` do build_target ${target} diff --git a/Makefile b/Makefile index 082b08e2c..5987f5f34 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2008 +# (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -12,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -22,11 +22,11 @@ # VERSION = 1 -PATCHLEVEL = 3 +PATCHLEVEL = 1 SUBLEVEL = 4 EXTRAVERSION = U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) -VERSION_FILE = $(obj)include/version_autogenerated.h +VERSION_FILE = include/version_autogenerated.h HOSTARCH := $(shell uname -m | \ sed -e s/i.86/i386/ \ @@ -34,7 +34,6 @@ HOSTARCH := $(shell uname -m | \ -e s/arm.*/arm/ \ -e s/sa110/arm/ \ -e s/powerpc/ppc/ \ - -e s/ppc64/ppc/ \ -e s/macppc/ppc/) HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \ @@ -46,106 +45,32 @@ export HOSTARCH HOSTOS VENDOR= ######################################################################### -# Allow for silent builds -ifeq (,$(findstring s,$(MAKEFLAGS))) -XECHO = echo -else -XECHO = : -endif -######################################################################### -# -# U-boot build supports producing a object files to the separate external -# directory. Two use cases are supported: -# -# 1) Add O= to the make command line -# 'make O=/tmp/build all' -# -# 2) Set environement variable BUILD_DIR to point to the desired location -# 'export BUILD_DIR=/tmp/build' -# 'make' -# -# The second approach can also be used with a MAKEALL script -# 'export BUILD_DIR=/tmp/build' -# './MAKEALL' -# -# Command line 'O=' setting overrides BUILD_DIR environent variable. -# -# When none of the above methods is used the local build is performed and -# the object files are placed in the source directory. -# - -ifdef O -ifeq ("$(origin O)", "command line") -BUILD_DIR := $(O) -endif -endif - -ifneq ($(BUILD_DIR),) -saved-output := $(BUILD_DIR) - -# Attempt to create a output directory. -$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}) - -# Verify if it was successful. -BUILD_DIR := $(shell cd $(BUILD_DIR) && /bin/pwd) -$(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist)) -endif # ifneq ($(BUILD_DIR),) - -OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR)) -SRCTREE := $(CURDIR) -TOPDIR := $(SRCTREE) -LNDIR := $(OBJTREE) -export TOPDIR SRCTREE OBJTREE - -MKCONFIG := $(SRCTREE)/mkconfig -export MKCONFIG - -ifneq ($(OBJTREE),$(SRCTREE)) -REMOTE_BUILD := 1 -export REMOTE_BUILD -endif - -# $(obj) and (src) are defined in config.mk but here in main Makefile -# we also need them before config.mk is included which is the case for -# some targets like unconfig, clean, clobber, distclean, etc. -ifneq ($(OBJTREE),$(SRCTREE)) -obj := $(OBJTREE)/ -src := $(SRCTREE)/ -else -obj := -src := -endif -export obj src - -# Make sure CDPATH settings don't interfere -unexport CDPATH - -######################################################################### - -ifeq ($(ARCH),powerpc) -ARCH = ppc -endif - -ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) +TOPDIR := $(shell if [ "$$PWD" != "" ]; then echo $$PWD; else pwd; fi) +export TOPDIR +ifeq (include/config.mk,$(wildcard include/config.mk)) # load ARCH, BOARD, and CPU configuration -include $(obj)include/config.mk +include include/config.mk export ARCH CPU BOARD VENDOR SOC - ifndef CROSS_COMPILE -ifeq ($(HOSTARCH),$(ARCH)) +ifeq ($(HOSTARCH),ppc) CROSS_COMPILE = else ifeq ($(ARCH),ppc) -CROSS_COMPILE = ppc_8xx- +CROSS_COMPILE = powerpc-linux- endif ifeq ($(ARCH),arm) -CROSS_COMPILE = arm-linux- +#CROSS_COMPILE = arm-linux- +CROSS_COMPILE = arm-none-linux-gnueabi- endif ifeq ($(ARCH),i386) +ifeq ($(HOSTARCH),i386) +CROSS_COMPILE = +else CROSS_COMPILE = i386-linux- endif +endif ifeq ($(ARCH),mips) CROSS_COMPILE = mips_4KC- endif @@ -162,25 +87,17 @@ ifeq ($(ARCH),microblaze) CROSS_COMPILE = mb- endif ifeq ($(ARCH),blackfin) -CROSS_COMPILE = bfin-uclinux- +CROSS_COMPILE = bfin-elf- endif -ifeq ($(ARCH),avr32) -CROSS_COMPILE = avr32-linux- endif -ifeq ($(ARCH),sh) -CROSS_COMPILE = sh4-linux- endif -ifeq ($(ARCH),sparc) -CROSS_COMPILE = sparc-elf- -endif # sparc -endif # HOSTARCH,ARCH -endif # CROSS_COMPILE export CROSS_COMPILE # load other configuration include $(TOPDIR)/config.mk + ######################################################################### # U-Boot objects....order is important (i.e. start must be first) @@ -192,278 +109,133 @@ endif ifeq ($(CPU),ppc4xx) OBJS += cpu/$(CPU)/resetvec.o endif +ifeq ($(CPU),mpc83xx) +OBJS += cpu/$(CPU)/resetvec.o +endif ifeq ($(CPU),mpc85xx) OBJS += cpu/$(CPU)/resetvec.o endif - -OBJS := $(addprefix $(obj),$(OBJS)) +ifeq ($(CPU),bf533) +OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o +OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU)/cplbmgr.o cpu/$(CPU)/flush.o +endif LIBS = lib_generic/libgeneric.a -LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \ - "board/$(VENDOR)/common/lib$(VENDOR).a"; fi) +LIBS += board/$(BOARDDIR)/lib$(BOARD).a LIBS += cpu/$(CPU)/lib$(CPU).a ifdef SOC LIBS += cpu/$(CPU)/$(SOC)/lib$(SOC).a endif -ifeq ($(CPU),ixp) -LIBS += cpu/ixp/npe/libnpe.a -endif LIBS += lib_$(ARCH)/lib$(ARCH).a LIBS += fs/cramfs/libcramfs.a fs/fat/libfat.a fs/fdos/libfdos.a fs/jffs2/libjffs2.a \ fs/reiserfs/libreiserfs.a fs/ext2/libext2fs.a LIBS += net/libnet.a LIBS += disk/libdisk.a -LIBS += drivers/bios_emulator/libatibiosemu.a -LIBS += drivers/block/libblock.a -LIBS += drivers/dma/libdma.a -LIBS += drivers/hwmon/libhwmon.a -LIBS += drivers/i2c/libi2c.a -LIBS += drivers/input/libinput.a -LIBS += drivers/misc/libmisc.a -LIBS += drivers/mmc/libmmc.a -LIBS += drivers/mtd/libmtd.a -LIBS += drivers/mtd/nand/libnand.a -LIBS += drivers/mtd/nand_legacy/libnand_legacy.a -LIBS += drivers/mtd/onenand/libonenand.a -LIBS += drivers/mtd/spi/libspi_flash.a -LIBS += drivers/net/libnet.a -LIBS += drivers/net/sk98lin/libsk98lin.a -LIBS += drivers/pci/libpci.a -LIBS += drivers/pcmcia/libpcmcia.a -LIBS += drivers/spi/libspi.a -ifeq ($(CPU),mpc83xx) -LIBS += drivers/qe/qe.a -endif -ifeq ($(CPU),mpc85xx) -LIBS += drivers/qe/qe.a -endif -LIBS += drivers/rtc/librtc.a -LIBS += drivers/serial/libserial.a -LIBS += drivers/usb/libusb.a -LIBS += drivers/video/libvideo.a +LIBS += rtc/librtc.a +LIBS += dtt/libdtt.a +LIBS += drivers/libdrivers.a +LIBS += drivers/onenand/libonenand.a +LIBS += drivers/nand/libnand.a +LIBS += drivers/nand_legacy/libnand_legacy.a +LIBS += drivers/sk98lin/libsk98lin.a +LIBS += post/libpost.a post/cpu/libcpu.a LIBS += common/libcommon.a -LIBS += libfdt/libfdt.a -LIBS += api/libapi.a -LIBS += post/libpost.a - -LIBS := $(addprefix $(obj),$(LIBS)) -.PHONY : $(LIBS) $(VERSION_FILE) - -LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).a -LIBBOARD := $(addprefix $(obj),$(LIBBOARD)) +LIBS += $(BOARDLIBS) +.PHONY : $(LIBS) # Add GCC lib PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc + # The "tools" are needed early, so put this first # Don't include stuff already done in $(LIBS) SUBDIRS = tools \ + post \ examples \ - api_examples - + post/cpu .PHONY : $(SUBDIRS) -ifeq ($(CONFIG_NAND_U_BOOT),y) -NAND_SPL = nand_spl -U_BOOT_NAND = $(obj)u-boot-nand.bin -endif - -ifeq ($(CONFIG_ONENAND_U_BOOT),y) -ONENAND_IPL = onenand_ipl -U_BOOT_ONENAND = $(obj)u-boot-onenand.bin -endif - -__OBJS := $(subst $(obj),,$(OBJS)) -__LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD)) - ######################################################################### ######################################################################### -ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) -ifeq ($(ARCH),blackfin) -ALL += $(obj)u-boot.ldr -endif +ALL = u-boot.srec u-boot.bin System.map all: $(ALL) -$(obj)u-boot.hex: $(obj)u-boot +u-boot.hex: u-boot $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -$(obj)u-boot.srec: $(obj)u-boot +u-boot.srec: u-boot $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -$(obj)u-boot.bin: $(obj)u-boot +u-boot.bin: u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -$(obj)u-boot.ldr: $(obj)u-boot - $(LDR) -T $(CONFIG_BFIN_CPU) -f -c $@ $< $(LDR_FLAGS) - -$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr - $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary - -$(obj)u-boot.ldr.srec: $(obj)u-boot.ldr - $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary - -$(obj)u-boot.img: $(obj)u-boot.bin +u-boot.img: u-boot.bin ./tools/mkimage -A $(ARCH) -T firmware -C none \ -a $(TEXT_BASE) -e 0 \ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -d $< $@ -$(obj)u-boot.sha1: $(obj)u-boot.bin - $(obj)tools/ubsha1 $(obj)u-boot.bin - -$(obj)u-boot.dis: $(obj)u-boot +u-boot.dis: u-boot $(OBJDUMP) -d $< > $@ -$(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) - UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \ - sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ - --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ +u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) + UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ + $(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \ + --start-group $(LIBS) --end-group $(PLATFORM_LIBS) \ -Map u-boot.map -o u-boot -$(OBJS): depend $(obj)include/autoconf.mk - $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@)) +$(LIBS): + $(MAKE) -C `dirname $@` -$(LIBS): depend $(obj)include/autoconf.mk - $(MAKE) -C $(dir $(subst $(obj),,$@)) - -$(LIBBOARD): depend $(LIBS) $(obj)include/autoconf.mk - $(MAKE) -C $(dir $(subst $(obj),,$@)) - -$(SUBDIRS): depend $(obj)include/autoconf.mk +$(SUBDIRS): $(MAKE) -C $@ all -$(LDSCRIPT): depend $(obj)include/autoconf.mk - $(MAKE) -C $(dir $@) $(notdir $@) - -$(NAND_SPL): $(VERSION_FILE) $(obj)include/autoconf.mk - $(MAKE) -C nand_spl/board/$(BOARDDIR) all - -$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk - cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin - -$(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk - $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all - -$(U_BOOT_ONENAND): $(ONENAND_IPL) $(obj)u-boot.bin $(obj)include/autoconf.mk - cat $(obj)onenand_ipl/onenand-ipl-2k.bin $(obj)u-boot.bin > $(obj)u-boot-onenand.bin - cat $(obj)onenand_ipl/onenand-ipl-4k.bin $(obj)u-boot.bin > $(obj)u-boot-flexonenand.bin - -$(VERSION_FILE): - @( printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' "$(U_BOOT_VERSION)" \ - '$(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion $(TOPDIR))' \ - ) > $@.tmp - @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ +version: + @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \ + echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \ + echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \ + $(TOPDIR)) >> $(VERSION_FILE); \ + echo "\"" >> $(VERSION_FILE) gdbtools: - $(MAKE) -C tools/gdb all || exit 1 + $(MAKE) -C tools/gdb || exit 1 -updater: - $(MAKE) -C tools/updater all || exit 1 +depend dep: + @for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir .depend ; done -env: - $(MAKE) -C tools/env all MTD_VERSION=${MTD_VERSION} || exit 1 - -depend dep: $(VERSION_FILE) - for dir in $(SUBDIRS) ; do $(MAKE) -C $$dir _depend ; done - -TAG_SUBDIRS += include -TAG_SUBDIRS += lib_generic board/$(BOARDDIR) -TAG_SUBDIRS += cpu/$(CPU) -TAG_SUBDIRS += lib_$(ARCH) -TAG_SUBDIRS += fs/cramfs -TAG_SUBDIRS += fs/fat -TAG_SUBDIRS += fs/fdos -TAG_SUBDIRS += fs/jffs2 -TAG_SUBDIRS += net -TAG_SUBDIRS += disk -TAG_SUBDIRS += common -TAG_SUBDIRS += drivers/bios_emulator -TAG_SUBDIRS += drivers/block -TAG_SUBDIRS += drivers/hwmon -TAG_SUBDIRS += drivers/i2c -TAG_SUBDIRS += drivers/input -TAG_SUBDIRS += drivers/misc -TAG_SUBDIRS += drivers/mmc -TAG_SUBDIRS += drivers/mtd -TAG_SUBDIRS += drivers/mtd/nand -TAG_SUBDIRS += drivers/mtd/nand_legacy -TAG_SUBDIRS += drivers/mtd/onenand -TAG_SUBDIRS += drivers/mtd/spi -TAG_SUBDIRS += drivers/net -TAG_SUBDIRS += drivers/net/sk98lin -TAG_SUBDIRS += drivers/pci -TAG_SUBDIRS += drivers/pcmcia -TAG_SUBDIRS += drivers/qe -TAG_SUBDIRS += drivers/rtc -TAG_SUBDIRS += drivers/serial -TAG_SUBDIRS += drivers/spi -TAG_SUBDIRS += drivers/usb -TAG_SUBDIRS += drivers/video - -tags ctags: - ctags -w -o $(obj)ctags `find $(SUBDIRS) $(TAG_SUBDIRS) \ - -name '*.[ch]' -print` +tags: + ctags -w `find $(SUBDIRS) include \ + lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \ + fs/cramfs fs/fat fs/fdos fs/jffs2 \ + net disk rtc dtt drivers drivers/sk98lin common \ + \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)` etags: - etags -a -o $(obj)etags `find $(SUBDIRS) $(TAG_SUBDIRS) \ - -name '*.[ch]' -print` -cscope: - find $(SUBDIRS) $(TAG_SUBDIRS) -name '*.[ch]' -print \ - > cscope.files - cscope -b -q -k + etags -a `find $(SUBDIRS) include \ + lib_generic board/$(BOARDDIR) cpu/$(CPU) lib_$(ARCH) \ + fs/cramfs fs/fat fs/fdos fs/jffs2 \ + net disk rtc dtt drivers drivers/sk98lin common \ + \( -name CVS -prune \) -o \( -name '*.[ch]' -print \)` -$(obj)System.map: $(obj)u-boot +System.map: u-boot @$(NM) $< | \ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ - sort > $(obj)System.map - -# -# Auto-generate the autoconf.mk file (which is included by all makefiles) -# -# This target actually generates 2 files; autoconf.mk and autoconf.mk.dep. -# the dep file is only include in this top level makefile to determine when -# to regenerate the autoconf.mk file. -$(obj)include/autoconf.mk.dep: $(obj)include/config.h include/common.h - @$(XECHO) Generating $@ ; \ - set -e ; \ - : Generate the dependancies ; \ - $(CC) -x c -DDO_DEPS_ONLY -M $(HOST_CFLAGS) $(CPPFLAGS) \ - -MQ $(obj)include/autoconf.mk include/common.h > $@ - -$(obj)include/autoconf.mk: $(obj)include/config.h - @$(XECHO) Generating $@ ; \ - set -e ; \ - : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h | \ - sed -n -f tools/scripts/define2mk.sed > $@ - -sinclude $(obj)include/autoconf.mk.dep + sort > System.map ######################################################################### -else # !config.mk -all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ -$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ -$(SUBDIRS) $(VERSION_FILE) gdbtools updater env depend \ -dep tags ctags etags cscope $(obj)System.map: +else +all install u-boot u-boot.srec depend dep: @echo "System not configured - see README" >&2 @ exit 1 -endif # config.mk - -.PHONY : CHANGELOG -CHANGELOG: - git log --no-merges U-Boot-1_1_5.. | \ - unexpand -a | sed -e 's/\s\s*$$//' > $@ +endif ######################################################################### unconfig: - @rm -f $(obj)include/config.h $(obj)include/config.mk \ - $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \ - $(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep + @rm -f include/config.h include/config.mk board/*/config.tmp #======================================================================== # PowerPC @@ -474,32 +246,29 @@ unconfig: ######################################################################### canmb_config: unconfig - @$(MKCONFIG) -a canmb ppc mpc5xxx canmb + @./mkconfig -a canmb ppc mpc5xxx canmb cmi_mpc5xx_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc5xx cmi + @./mkconfig $(@:_config=) ppc mpc5xx cmi PATI_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc5xx pati mpl + @./mkconfig $(@:_config=) ppc mpc5xx pati mpl ######################################################################### ## MPC5xxx Systems ######################################################################### aev_config: unconfig - @$(MKCONFIG) -a aev ppc mpc5xxx tqm5200 tqc + @./mkconfig -a aev ppc mpc5xxx tqm5200 BC3450_config: unconfig - @$(MKCONFIG) -a BC3450 ppc mpc5xxx bc3450 - -cm5200_config: unconfig - @$(MKCONFIG) -a cm5200 ppc mpc5xxx cm5200 + @./mkconfig -a BC3450 ppc mpc5xxx bc3450 cpci5200_config: unconfig - @$(MKCONFIG) -a cpci5200 ppc mpc5xxx cpci5200 esd + @./mkconfig -a cpci5200 ppc mpc5xxx cpci5200 esd -hmi1001_config: unconfig - @$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001 +hmi1001_config: unconfig + @./mkconfig hmi1001 ppc mpc5xxx hmi1001 Lite5200_config \ Lite5200_LOWBOOT_config \ @@ -507,440 +276,345 @@ Lite5200_LOWBOOT08_config \ icecube_5200_config \ icecube_5200_LOWBOOT_config \ icecube_5200_LOWBOOT08_config \ -icecube_5200_DDR_config \ -icecube_5200_DDR_LOWBOOT_config \ +icecube_5200_DDR_config \ +icecube_5200_DDR_LOWBOOT_config \ icecube_5200_DDR_LOWBOOT08_config \ icecube_5100_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/icecube + @ >include/config.h @[ -z "$(findstring LOWBOOT_,$@)" ] || \ { if [ "$(findstring DDR,$@)" ] ; \ - then echo "TEXT_BASE = 0xFF800000" >$(obj)board/icecube/config.tmp ; \ - else echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \ + then echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \ + else echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \ fi ; \ - $(XECHO) "... with LOWBOOT configuration" ; \ + echo "... with LOWBOOT configuration" ; \ } @[ -z "$(findstring LOWBOOT08,$@)" ] || \ - { echo "TEXT_BASE = 0xFF800000" >$(obj)board/icecube/config.tmp ; \ + { echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \ echo "... with 8 MB flash only" ; \ - $(XECHO) "... with LOWBOOT configuration" ; \ + echo "... with LOWBOOT configuration" ; \ } @[ -z "$(findstring DDR,$@)" ] || \ - { echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h ; \ - $(XECHO) "... DDR memory revision" ; \ + { echo "#define CONFIG_MPC5200_DDR" >>include/config.h ; \ + echo "... DDR memory revision" ; \ } @[ -z "$(findstring 5200,$@)" ] || \ - { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \ - $(XECHO) "... with MPC5200 processor" ; \ + { echo "#define CONFIG_MPC5200" >>include/config.h ; \ + echo "... with MPC5200 processor" ; \ } @[ -z "$(findstring 5100,$@)" ] || \ - { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \ - $(XECHO) "... with MGT5100 processor" ; \ + { echo "#define CONFIG_MGT5100" >>include/config.h ; \ + echo "... with MGT5100 processor" ; \ } - @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube - -jupiter_config: unconfig - @$(MKCONFIG) jupiter ppc mpc5xxx jupiter + @./mkconfig -a IceCube ppc mpc5xxx icecube inka4x0_config: unconfig - @$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0 + @./mkconfig inka4x0 ppc mpc5xxx inka4x0 lite5200b_config \ -lite5200b_PM_config \ lite5200b_LOWBOOT_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/icecube - @ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h - @ $(XECHO) "... DDR memory revision" - @ echo "#define CONFIG_MPC5200" >>$(obj)include/config.h - @ echo "#define CONFIG_LITE5200B" >>$(obj)include/config.h - @[ -z "$(findstring _PM_,$@)" ] || \ - { echo "#define CONFIG_LITE5200B_PM" >>$(obj)include/config.h ; \ - $(XECHO) "... with power management (low-power mode) support" ; \ - } + @ >include/config.h + @ echo "#define CONFIG_MPC5200_DDR" >>include/config.h + @ echo "... DDR memory revision" + @ echo "#define CONFIG_MPC5200" >>include/config.h + @ echo "#define CONFIG_LITE5200B" >>include/config.h @[ -z "$(findstring LOWBOOT_,$@)" ] || \ - { echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \ - $(XECHO) "... with LOWBOOT configuration" ; \ + { echo "TEXT_BASE = 0xFF000000" >board/icecube/config.tmp ; \ + echo "... with LOWBOOT configuration" ; \ } - @ $(XECHO) "... with MPC5200B processor" - @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube + @ echo "... with MPC5200B processor" + @./mkconfig -a IceCube ppc mpc5xxx icecube mcc200_config \ -mcc200_SDRAM_config \ -mcc200_highboot_config \ -mcc200_COM12_config \ -mcc200_COM12_SDRAM_config \ -mcc200_COM12_highboot_config \ -mcc200_COM12_highboot_SDRAM_config \ -mcc200_highboot_SDRAM_config \ -prs200_config \ -prs200_DDR_config \ -prs200_highboot_config \ -prs200_highboot_DDR_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/mcc200 +mcc200_SDRAM \ +mcc200_highboot \ +mcc200_highboot_SDRAM: unconfig + @ >include/config.h @[ -n "$(findstring highboot,$@)" ] || \ - { $(XECHO) "... with lowboot configuration" ; \ + { echo "... with lowboot configuration" ; \ } @[ -z "$(findstring highboot,$@)" ] || \ - { echo "TEXT_BASE = 0xFFF00000" >$(obj)board/mcc200/config.tmp ; \ - $(XECHO) "... with highboot configuration" ; \ + { echo "TEXT_BASE = 0xFFF00000" >board/mcc200/config.tmp ; \ + echo "... with highboot configuration" ; \ } @[ -n "$(findstring _SDRAM,$@)" ] || \ - { if [ -n "$(findstring mcc200,$@)" ]; \ - then \ - $(XECHO) "... with DDR" ; \ - else \ - if [ -n "$(findstring _DDR,$@)" ];\ - then \ - $(XECHO) "... with DDR" ; \ - else \ - echo "#define CONFIG_MCC200_SDRAM" >>$(obj)include/config.h ;\ - $(XECHO) "... with SDRAM" ; \ - fi; \ - fi; \ + { echo "... with DDR" ; \ } @[ -z "$(findstring _SDRAM,$@)" ] || \ - { echo "#define CONFIG_MCC200_SDRAM" >>$(obj)include/config.h ; \ - $(XECHO) "... with SDRAM" ; \ + { echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ; \ + echo "... with SDRAM" ; \ } - @[ -z "$(findstring COM12,$@)" ] || \ - { echo "#define CONFIG_CONSOLE_COM12" >>$(obj)include/config.h ; \ - $(XECHO) "... with console on COM12" ; \ - } - @[ -z "$(findstring prs200,$@)" ] || \ - { echo "#define CONFIG_PRS200" >>$(obj)include/config.h ;\ - } - @$(MKCONFIG) -n $@ -a mcc200 ppc mpc5xxx mcc200 + @./mkconfig -a mcc200 ppc mpc5xxx mcc200 -mecp5200_config: unconfig - @$(MKCONFIG) mecp5200 ppc mpc5xxx mecp5200 esd +o2dnt_config: + @./mkconfig o2dnt ppc mpc5xxx o2dnt -motionpro_config: unconfig - @$(MKCONFIG) motionpro ppc mpc5xxx motionpro - -munices_config: unconfig - @$(MKCONFIG) munices ppc mpc5xxx munices - -MVBC_P_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/mvbc_p - @ >$(obj)include/config.h - @[ -z "$(findstring MVBC_P,$@)" ] || \ - { echo "#define CONFIG_MVBC_P" >>$(obj)include/config.h; } - @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision - -o2dnt_config: unconfig - @$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt - -pf5200_config: unconfig - @$(MKCONFIG) pf5200 ppc mpc5xxx pf5200 esd +pf5200_config: unconfig + @./mkconfig pf5200 ppc mpc5xxx pf5200 esd PM520_config \ PM520_DDR_config \ PM520_ROMBOOT_config \ PM520_ROMBOOT_DDR_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring DDR,$@)" ] || \ - { echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h ; \ - $(XECHO) "... DDR memory revision" ; \ + { echo "#define CONFIG_MPC5200_DDR" >>include/config.h ; \ + echo "... DDR memory revision" ; \ } @[ -z "$(findstring ROMBOOT,$@)" ] || \ - { echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h ; \ - $(XECHO) "... booting from 8-bit flash" ; \ + { echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \ + echo "... booting from 8-bit flash" ; \ } - @$(MKCONFIG) -a PM520 ppc mpc5xxx pm520 + @./mkconfig -a PM520 ppc mpc5xxx pm520 smmaco4_config: unconfig - @$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200 tqc + @./mkconfig -a smmaco4 ppc mpc5xxx tqm5200 spieval_config: unconfig - @$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200 tqc + @./mkconfig -a spieval ppc mpc5xxx tqm5200 TB5200_B_config \ TB5200_config: unconfig - @mkdir -p $(obj)include @[ -z "$(findstring _B,$@)" ] || \ - { echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \ - $(XECHO) "... with MPC5200B processor" ; \ + { echo "#define CONFIG_TQM5200_B" >>include/config.h ; \ + echo "... with MPC5200B processor" ; \ } - @$(MKCONFIG) -n $@ -a TB5200 ppc mpc5xxx tqm5200 tqc + @./mkconfig -n $@ -a TB5200 ppc mpc5xxx tqm5200 MINI5200_config \ EVAL5200_config \ TOP5200_config: unconfig - @mkdir -p $(obj)include - @ echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h - @$(MKCONFIG) -n $@ -a TOP5200 ppc mpc5xxx top5200 emk + @ echo "#define CONFIG_$(@:_config=) 1" >include/config.h + @./mkconfig -n $@ -a TOP5200 ppc mpc5xxx top5200 emk Total5100_config \ Total5200_config \ Total5200_lowboot_config \ Total5200_Rev2_config \ Total5200_Rev2_lowboot_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/total5200 + @ >include/config.h @[ -z "$(findstring 5100,$@)" ] || \ - { echo "#define CONFIG_MGT5100" >>$(obj)include/config.h ; \ - $(XECHO) "... with MGT5100 processor" ; \ + { echo "#define CONFIG_MGT5100" >>include/config.h ; \ + echo "... with MGT5100 processor" ; \ } @[ -z "$(findstring 5200,$@)" ] || \ - { echo "#define CONFIG_MPC5200" >>$(obj)include/config.h ; \ - $(XECHO) "... with MPC5200 processor" ; \ + { echo "#define CONFIG_MPC5200" >>include/config.h ; \ + echo "... with MPC5200 processor" ; \ } @[ -n "$(findstring Rev,$@)" ] || \ - { echo "#define CONFIG_TOTAL5200_REV 1" >>$(obj)include/config.h ; \ - $(XECHO) "... revision 1 board" ; \ + { echo "#define CONFIG_TOTAL5200_REV 1" >>include/config.h ; \ + echo "... revision 1 board" ; \ } @[ -z "$(findstring Rev2_,$@)" ] || \ - { echo "#define CONFIG_TOTAL5200_REV 2" >>$(obj)include/config.h ; \ - $(XECHO) "... revision 2 board" ; \ + { echo "#define CONFIG_TOTAL5200_REV 2" >>include/config.h ; \ + echo "... revision 2 board" ; \ } @[ -z "$(findstring lowboot_,$@)" ] || \ - { echo "TEXT_BASE = 0xFE000000" >$(obj)board/total5200/config.tmp ; \ - $(XECHO) "... with lowboot configuration" ; \ + { echo "TEXT_BASE = 0xFE000000" >board/total5200/config.tmp ; \ + echo "... with lowboot configuration" ; \ } - @$(MKCONFIG) -a Total5200 ppc mpc5xxx total5200 + @./mkconfig -a Total5200 ppc mpc5xxx total5200 -cam5200_config \ -cam5200_niosflash_config \ -fo300_config \ -MiniFAP_config \ -TQM5200S_config \ -TQM5200S_HIGHBOOT_config \ +TQM5200_config \ TQM5200_B_config \ TQM5200_B_HIGHBOOT_config \ -TQM5200_config \ -TQM5200_STK100_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/tqc/tqm5200 - @[ -z "$(findstring cam5200,$@)" ] || \ - { echo "#define CONFIG_CAM5200" >>$(obj)include/config.h ; \ - echo "#define CONFIG_TQM5200S" >>$(obj)include/config.h ; \ - echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \ - $(XECHO) "... TQM5200S on Cam5200" ; \ - } - @[ -z "$(findstring niosflash,$@)" ] || \ - { echo "#define CONFIG_CAM5200_NIOSFLASH" >>$(obj)include/config.h ; \ - $(XECHO) "... with NIOS flash driver" ; \ - } - @[ -z "$(findstring fo300,$@)" ] || \ - { echo "#define CONFIG_FO300" >>$(obj)include/config.h ; \ - $(XECHO) "... TQM5200 on FO300" ; \ - } +TQM5200S_config \ +TQM5200S_HIGHBOOT_config \ +TQM5200_STK100_config \ +cam5200_config \ +MiniFAP_config: unconfig + @ >include/config.h @[ -z "$(findstring MiniFAP,$@)" ] || \ - { echo "#define CONFIG_MINIFAP" >>$(obj)include/config.h ; \ - $(XECHO) "... TQM5200_AC on MiniFAP" ; \ + { echo "#define CONFIG_MINIFAP" >>include/config.h ; \ + echo "... TQM5200_AC on MiniFAP" ; \ + } + @[ -z "$(findstring cam5200,$@)" ] || \ + { echo "#define CONFIG_CAM5200" >>include/config.h ; \ + echo "#define CONFIG_TQM5200S" >>include/config.h ; \ + echo "#define CONFIG_TQM5200_B" >>include/config.h ; \ + echo "... TQM5200S on Cam5200" ; \ } @[ -z "$(findstring STK100,$@)" ] || \ - { echo "#define CONFIG_STK52XX_REV100" >>$(obj)include/config.h ; \ - $(XECHO) "... on a STK52XX.100 base board" ; \ + { echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \ + echo "... on a STK52XX.100 base board" ; \ } @[ -z "$(findstring TQM5200_B,$@)" ] || \ - { echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_TQM5200_B" >>include/config.h ; \ } @[ -z "$(findstring TQM5200S,$@)" ] || \ - { echo "#define CONFIG_TQM5200S" >>$(obj)include/config.h ; \ - echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_TQM5200S" >>include/config.h ; \ + echo "#define CONFIG_TQM5200_B" >>include/config.h ; \ } @[ -z "$(findstring HIGHBOOT,$@)" ] || \ - { echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \ + { echo "TEXT_BASE = 0xFFF00000" >board/tqm5200/config.tmp ; \ } - @$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200 tqc - -uc101_config: unconfig - @$(MKCONFIG) uc101 ppc mpc5xxx uc101 - -v38b_config: unconfig - @$(MKCONFIG) -a v38b ppc mpc5xxx v38b - -######################################################################### -## MPC512x Systems -######################################################################### - -ads5121_config \ -ads5121_rev2_config \ - : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring rev2,$@)" ] ; then \ - echo "#define CONFIG_ADS5121_REV2 1" > $(obj)include/config.h; \ - fi - @$(MKCONFIG) -a ads5121 ppc mpc512x ads5121 - + @./mkconfig -n $@ -a TQM5200 ppc mpc5xxx tqm5200 ######################################################################### ## MPC8xx Systems ######################################################################### -Adder_config \ +Adder_config \ Adder87x_config \ -AdderII_config \ +AdderII_config \ : unconfig - @mkdir -p $(obj)include $(if $(findstring AdderII,$@), \ - @echo "#define CONFIG_MPC852T" > $(obj)include/config.h) - @$(MKCONFIG) -a Adder ppc mpc8xx adder + @echo "#define CONFIG_MPC852T" > include/config.h) + @./mkconfig -a Adder ppc mpc8xx adder -AdderUSB_config: unconfig - @$(MKCONFIG) -a AdderUSB ppc mpc8xx adder - -ADS860_config \ -FADS823_config \ +ADS860_config \ +FADS823_config \ FADS850SAR_config \ MPC86xADS_config \ MPC885ADS_config \ FADS860T_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx fads + @./mkconfig $(@:_config=) ppc mpc8xx fads AMX860_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx amx860 westel + @./mkconfig $(@:_config=) ppc mpc8xx amx860 westel c2mon_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx c2mon + @./mkconfig $(@:_config=) ppc mpc8xx c2mon CCM_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx CCM siemens + @./mkconfig $(@:_config=) ppc mpc8xx CCM siemens cogent_mpc8xx_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx cogent + @./mkconfig $(@:_config=) ppc mpc8xx cogent ELPT860_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx elpt860 LEOX + @./mkconfig $(@:_config=) ppc mpc8xx elpt860 LEOX EP88x_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx ep88x + @./mkconfig $(@:_config=) ppc mpc8xx ep88x ESTEEM192E_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx esteem192e + @./mkconfig $(@:_config=) ppc mpc8xx esteem192e ETX094_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx etx094 + @./mkconfig $(@:_config=) ppc mpc8xx etx094 FLAGADM_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx flagadm + @./mkconfig $(@:_config=) ppc mpc8xx flagadm xtract_GEN860T = $(subst _SC,,$(subst _config,,$1)) GEN860T_SC_config \ GEN860T_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring _SC,$@)" ] || \ - { echo "#define CONFIG_SC" >>$(obj)include/config.h ; \ - $(XECHO) "With reduced H/W feature set (SC)..." ; \ + { echo "#define CONFIG_SC" >>include/config.h ; \ + echo "With reduced H/W feature set (SC)..." ; \ } - @$(MKCONFIG) -a $(call xtract_GEN860T,$@) ppc mpc8xx gen860t + @./mkconfig -a $(call xtract_GEN860T,$@) ppc mpc8xx gen860t GENIETV_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx genietv + @./mkconfig $(@:_config=) ppc mpc8xx genietv GTH_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx gth + @./mkconfig $(@:_config=) ppc mpc8xx gth hermes_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx hermes + @./mkconfig $(@:_config=) ppc mpc8xx hermes HMI10_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc + @./mkconfig $(@:_config=) ppc mpc8xx tqm8xx IAD210_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx IAD210 siemens + @./mkconfig $(@:_config=) ppc mpc8xx IAD210 siemens xtract_ICU862 = $(subst _100MHz,,$(subst _config,,$1)) ICU862_100MHz_config \ ICU862_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring _100MHz,$@)" ] || \ - { echo "#define CONFIG_100MHz" >>$(obj)include/config.h ; \ - $(XECHO) "... with 100MHz system clock" ; \ + { echo "#define CONFIG_100MHz" >>include/config.h ; \ + echo "... with 100MHz system clock" ; \ } - @$(MKCONFIG) -a $(call xtract_ICU862,$@) ppc mpc8xx icu862 + @./mkconfig -a $(call xtract_ICU862,$@) ppc mpc8xx icu862 IP860_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx ip860 + @./mkconfig $(@:_config=) ppc mpc8xx ip860 IVML24_256_config \ IVML24_128_config \ IVML24_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring IVML24_config,$@)" ] || \ - { echo "#define CONFIG_IVML24_16M" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_IVML24_16M" >>include/config.h ; \ } @[ -z "$(findstring IVML24_128_config,$@)" ] || \ - { echo "#define CONFIG_IVML24_32M" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_IVML24_32M" >>include/config.h ; \ } @[ -z "$(findstring IVML24_256_config,$@)" ] || \ - { echo "#define CONFIG_IVML24_64M" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_IVML24_64M" >>include/config.h ; \ } - @$(MKCONFIG) -a IVML24 ppc mpc8xx ivm + @./mkconfig -a IVML24 ppc mpc8xx ivm IVMS8_256_config \ IVMS8_128_config \ IVMS8_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring IVMS8_config,$@)" ] || \ - { echo "#define CONFIG_IVMS8_16M" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_IVMS8_16M" >>include/config.h ; \ } @[ -z "$(findstring IVMS8_128_config,$@)" ] || \ - { echo "#define CONFIG_IVMS8_32M" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_IVMS8_32M" >>include/config.h ; \ } @[ -z "$(findstring IVMS8_256_config,$@)" ] || \ - { echo "#define CONFIG_IVMS8_64M" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_IVMS8_64M" >>include/config.h ; \ } - @$(MKCONFIG) -a IVMS8 ppc mpc8xx ivm + @./mkconfig -a IVMS8 ppc mpc8xx ivm KUP4K_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx kup4k kup + @./mkconfig $(@:_config=) ppc mpc8xx kup4k kup -KUP4X_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx kup4x kup +KUP4X_config : unconfig + @./mkconfig $(@:_config=) ppc mpc8xx kup4x kup LANTEC_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx lantec + @./mkconfig $(@:_config=) ppc mpc8xx lantec lwmon_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx lwmon + @./mkconfig $(@:_config=) ppc mpc8xx lwmon MBX_config \ MBX860T_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx - -mgsuvd_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd + @./mkconfig $(@:_config=) ppc mpc8xx mbx8xx MHPC_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec + @./mkconfig $(@:_config=) ppc mpc8xx mhpc eltec MVS1_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx mvs1 + @./mkconfig $(@:_config=) ppc mpc8xx mvs1 xtract_NETVIA = $(subst _V2,,$(subst _config,,$1)) NETVIA_V2_config \ NETVIA_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring NETVIA_config,$@)" ] || \ - { echo "#define CONFIG_NETVIA_VERSION 1" >>$(obj)include/config.h ; \ - $(XECHO) "... Version 1" ; \ + { echo "#define CONFIG_NETVIA_VERSION 1" >>include/config.h ; \ + echo "... Version 1" ; \ } @[ -z "$(findstring NETVIA_V2_config,$@)" ] || \ - { echo "#define CONFIG_NETVIA_VERSION 2" >>$(obj)include/config.h ; \ - $(XECHO) "... Version 2" ; \ + { echo "#define CONFIG_NETVIA_VERSION 2" >>include/config.h ; \ + echo "... Version 2" ; \ } - @$(MKCONFIG) -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia + @./mkconfig -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia xtract_NETPHONE = $(subst _V2,,$(subst _config,,$1)) NETPHONE_V2_config \ NETPHONE_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring NETPHONE_config,$@)" ] || \ - { echo "#define CONFIG_NETPHONE_VERSION 1" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_NETPHONE_VERSION 1" >>include/config.h ; \ } @[ -z "$(findstring NETPHONE_V2_config,$@)" ] || \ - { echo "#define CONFIG_NETPHONE_VERSION 2" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_NETPHONE_VERSION 2" >>include/config.h ; \ } - @$(MKCONFIG) -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone + @./mkconfig -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone xtract_NETTA = $(subst _SWAPHOOK,,$(subst _6412,,$(subst _ISDN,,$(subst _config,,$1)))) @@ -952,143 +626,143 @@ NETTA_ISDN_6412_config \ NETTA_ISDN_config \ NETTA_6412_config \ NETTA_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring ISDN_,$@)" ] || \ - { echo "#define CONFIG_NETTA_ISDN 1" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_NETTA_ISDN 1" >>include/config.h ; \ } @[ -n "$(findstring ISDN_,$@)" ] || \ - { echo "#undef CONFIG_NETTA_ISDN" >>$(obj)include/config.h ; \ + { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \ } @[ -z "$(findstring 6412_,$@)" ] || \ - { echo "#define CONFIG_NETTA_6412 1" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_NETTA_6412 1" >>include/config.h ; \ } @[ -n "$(findstring 6412_,$@)" ] || \ - { echo "#undef CONFIG_NETTA_6412" >>$(obj)include/config.h ; \ + { echo "#undef CONFIG_NETTA_6412" >>include/config.h ; \ } @[ -z "$(findstring SWAPHOOK_,$@)" ] || \ - { echo "#define CONFIG_NETTA_SWAPHOOK 1" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_NETTA_SWAPHOOK 1" >>include/config.h ; \ } @[ -n "$(findstring SWAPHOOK_,$@)" ] || \ - { echo "#undef CONFIG_NETTA_SWAPHOOK" >>$(obj)include/config.h ; \ + { echo "#undef CONFIG_NETTA_SWAPHOOK" >>include/config.h ; \ } - @$(MKCONFIG) -a $(call xtract_NETTA,$@) ppc mpc8xx netta + @./mkconfig -a $(call xtract_NETTA,$@) ppc mpc8xx netta xtract_NETTA2 = $(subst _V2,,$(subst _config,,$1)) NETTA2_V2_config \ NETTA2_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring NETTA2_config,$@)" ] || \ - { echo "#define CONFIG_NETTA2_VERSION 1" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_NETTA2_VERSION 1" >>include/config.h ; \ } @[ -z "$(findstring NETTA2_V2_config,$@)" ] || \ - { echo "#define CONFIG_NETTA2_VERSION 2" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_NETTA2_VERSION 2" >>include/config.h ; \ } - @$(MKCONFIG) -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2 + @./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2 NC650_Rev1_config \ NC650_Rev2_config \ CP850_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring CP850,$@)" ] || \ - { echo "#define CONFIG_CP850 1" >>$(obj)include/config.h ; \ - echo "#define CONFIG_IDS852_REV2 1" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_CP850 1" >>include/config.h ; \ + echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \ } @[ -z "$(findstring Rev1,$@)" ] || \ - { echo "#define CONFIG_IDS852_REV1 1" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_IDS852_REV1 1" >>include/config.h ; \ } @[ -z "$(findstring Rev2,$@)" ] || \ - { echo "#define CONFIG_IDS852_REV2 1" >>$(obj)include/config.h ; \ + { echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \ } - @$(MKCONFIG) -a NC650 ppc mpc8xx nc650 + @./mkconfig -a NC650 ppc mpc8xx nc650 NX823_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx nx823 + @./mkconfig $(@:_config=) ppc mpc8xx nx823 pcu_e_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx pcu_e siemens + @./mkconfig $(@:_config=) ppc mpc8xx pcu_e siemens QS850_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx qs850 snmc + @./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc QS823_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx qs850 snmc + @./mkconfig $(@:_config=) ppc mpc8xx qs850 snmc QS860T_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx qs860t snmc + @./mkconfig $(@:_config=) ppc mpc8xx qs860t snmc quantum_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx quantum + @./mkconfig $(@:_config=) ppc mpc8xx quantum R360MPI_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx r360mpi + @./mkconfig $(@:_config=) ppc mpc8xx r360mpi RBC823_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx rbc823 + @./mkconfig $(@:_config=) ppc mpc8xx rbc823 RPXClassic_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx RPXClassic + @./mkconfig $(@:_config=) ppc mpc8xx RPXClassic RPXlite_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx RPXlite + @./mkconfig $(@:_config=) ppc mpc8xx RPXlite -RPXlite_DW_64_config \ -RPXlite_DW_LCD_config \ -RPXlite_DW_64_LCD_config \ +RPXlite_DW_64_config \ +RPXlite_DW_LCD_config \ +RPXlite_DW_64_LCD_config \ RPXlite_DW_NVRAM_config \ -RPXlite_DW_NVRAM_64_config \ +RPXlite_DW_NVRAM_64_config \ RPXlite_DW_NVRAM_LCD_config \ -RPXlite_DW_NVRAM_64_LCD_config \ -RPXlite_DW_config: unconfig - @mkdir -p $(obj)include +RPXlite_DW_NVRAM_64_LCD_config \ +RPXlite_DW_config: unconfig + @ >include/config.h @[ -z "$(findstring _64,$@)" ] || \ - { echo "#define RPXlite_64MHz" >>$(obj)include/config.h ; \ - $(XECHO) "... with 64MHz system clock ..."; \ + { echo "#define RPXlite_64MHz" >>include/config.h ; \ + echo "... with 64MHz system clock ..."; \ } @[ -z "$(findstring _LCD,$@)" ] || \ - { echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \ - echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \ - $(XECHO) "... with LCD display ..."; \ + { echo "#define CONFIG_LCD" >>include/config.h ; \ + echo "#define CONFIG_NEC_NL6448BC20" >>include/config.h ; \ + echo "... with LCD display ..."; \ } @[ -z "$(findstring _NVRAM,$@)" ] || \ - { echo "#define CFG_ENV_IS_IN_NVRAM" >>$(obj)include/config.h ; \ - $(XECHO) "... with ENV in NVRAM ..."; \ + { echo "#define CFG_ENV_IS_IN_NVRAM" >>include/config.h ; \ + echo "... with ENV in NVRAM ..."; \ } - @$(MKCONFIG) -a RPXlite_DW ppc mpc8xx RPXlite_dw + @./mkconfig -a RPXlite_DW ppc mpc8xx RPXlite_dw rmu_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx rmu + @./mkconfig $(@:_config=) ppc mpc8xx rmu RRvision_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx RRvision + @./mkconfig $(@:_config=) ppc mpc8xx RRvision RRvision_LCD_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_LCD" >$(obj)include/config.h - @echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h - @$(MKCONFIG) -a RRvision ppc mpc8xx RRvision + @echo "#define CONFIG_LCD" >include/config.h + @echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h + @./mkconfig -a RRvision ppc mpc8xx RRvision SM850_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc + @./mkconfig $(@:_config=) ppc mpc8xx tqm8xx -spc1920_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx spc1920 +spc1920_config: + @./mkconfig $(@:_config=) ppc mpc8xx spc1920 SPD823TS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx spd8xx + @./mkconfig $(@:_config=) ppc mpc8xx spd8xx stxxtc_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc + @./mkconfig $(@:_config=) ppc mpc8xx stxxtc svm_sc8xx_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx svm_sc8xx + @ >include/config.h + @./mkconfig $(@:_config=) ppc mpc8xx svm_sc8xx SXNI855T_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx sixnet + @./mkconfig $(@:_config=) ppc mpc8xx sixnet # EMK MPC8xx based modules TOP860_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx top860 emk + @./mkconfig $(@:_config=) ppc mpc8xx top860 emk # Play some tricks for configuration selection # Only 855 and 860 boards may come with FEC @@ -1111,270 +785,179 @@ TQM860M_config \ TQM862M_config \ TQM866M_config \ TQM885D_config \ -TK885D_config \ virtlab2_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring _LCD,$@)" ] || \ - { echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \ - echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \ - $(XECHO) "... with LCD display" ; \ + { echo "#define CONFIG_LCD" >>include/config.h ; \ + echo "#define CONFIG_NEC_NL6448BC20" >>include/config.h ; \ + echo "... with LCD display" ; \ } - @$(MKCONFIG) -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx tqc + @./mkconfig -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx TTTech_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_LCD" >$(obj)include/config.h - @echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h - @$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx tqc + @echo "#define CONFIG_LCD" >include/config.h + @echo "#define CONFIG_SHARP_LQ104V7DS01" >>include/config.h + @./mkconfig -a TQM823L ppc mpc8xx tqm8xx uc100_config : unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx uc100 + @./mkconfig $(@:_config=) ppc mpc8xx uc100 v37_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_LCD" >$(obj)include/config.h - @echo "#define CONFIG_SHARP_LQ084V1DG21" >>$(obj)include/config.h - @$(MKCONFIG) $(@:_config=) ppc mpc8xx v37 + @echo "#define CONFIG_LCD" >include/config.h + @echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h + @./mkconfig $(@:_config=) ppc mpc8xx v37 wtk_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_LCD" >$(obj)include/config.h - @echo "#define CONFIG_SHARP_LQ065T9DR51U" >>$(obj)include/config.h - @$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx tqc + @echo "#define CONFIG_LCD" >include/config.h + @echo "#define CONFIG_SHARP_LQ065T9DR51U" >>include/config.h + @./mkconfig -a TQM823L ppc mpc8xx tqm8xx ######################################################################### ## PPC4xx Systems ######################################################################### xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1)))))) -acadia_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx acadia amcc - -acadia_nand_config: unconfig - @mkdir -p $(obj)include $(obj)board/amcc/acadia - @mkdir -p $(obj)nand_spl/board/amcc/acadia - @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h - @$(MKCONFIG) -n $@ -a acadia ppc ppc4xx acadia amcc - @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/acadia/config.tmp - @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk - ADCIOP_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd - -alpr_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx alpr prodrive + @./mkconfig $(@:_config=) ppc ppc4xx adciop esd AP1000_config:unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx ap1000 amirix + @./mkconfig $(@:_config=) ppc ppc4xx ap1000 amirix APC405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx apc405 esd + @./mkconfig $(@:_config=) ppc ppc4xx apc405 esd AR405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx ar405 esd + @./mkconfig $(@:_config=) ppc ppc4xx ar405 esd ASH405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx ash405 esd + @./mkconfig $(@:_config=) ppc ppc4xx ash405 esd bamboo_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx bamboo amcc - -bamboo_nand_config: unconfig - @mkdir -p $(obj)include $(obj)board/amcc/bamboo - @mkdir -p $(obj)nand_spl/board/amcc/bamboo - @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h - @$(MKCONFIG) -n $@ -a bamboo ppc ppc4xx bamboo amcc - @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/bamboo/config.tmp - @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + @./mkconfig $(@:_config=) ppc ppc4xx bamboo amcc bubinga_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx bubinga amcc + @./mkconfig $(@:_config=) ppc ppc4xx bubinga amcc CANBT_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd - -# Canyonlands & Glacier use different U-Boot images -canyonlands_config \ -glacier_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \ - tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h - @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc - -canyonlands_nand_config \ -glacier_nand_config: unconfig - @mkdir -p $(obj)include $(obj)board/amcc/canyonlands - @mkdir -p $(obj)nand_spl/board/amcc/canyonlands - @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h - @echo "#define CONFIG_$$(echo $(subst ,,$(@:_nand_config=)) | \ - tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h - @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc - @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/canyonlands/config.tmp - @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + @./mkconfig $(@:_config=) ppc ppc4xx canbt esd CATcenter_config \ CATcenter_25_config \ CATcenter_33_config: unconfig - @mkdir -p $(obj)include - @ echo "/* CATcenter uses PPChameleon Model ME */" > $(obj)include/config.h - @ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> $(obj)include/config.h + @ echo "/* CATcenter uses PPChameleon Model ME */" > include/config.h + @ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> include/config.h @[ -z "$(findstring _25,$@)" ] || \ - { echo "#define CONFIG_PPCHAMELEON_CLK_25" >> $(obj)include/config.h ; \ - $(XECHO) "SysClk = 25MHz" ; \ + { echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \ + echo "SysClk = 25MHz" ; \ } @[ -z "$(findstring _33,$@)" ] || \ - { echo "#define CONFIG_PPCHAMELEON_CLK_33" >> $(obj)include/config.h ; \ - $(XECHO) "SysClk = 33MHz" ; \ + { echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \ + echo "SysClk = 33MHz" ; \ } - @$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave - -CMS700_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx cms700 esd + @./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave CPCI2DP_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd + @./mkconfig $(@:_config=) ppc ppc4xx cpci2dp esd CPCI405_config \ CPCI4052_config \ CPCI405DT_config \ CPCI405AB_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd - @echo "BOARD_REVISION = $(@:_config=)" >> $(obj)include/config.mk + @./mkconfig $(@:_config=) ppc ppc4xx cpci405 esd + @echo "BOARD_REVISION = $(@:_config=)" >>include/config.mk + +CPCI440_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx cpci440 esd CPCIISER4_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd + @./mkconfig $(@:_config=) ppc ppc4xx cpciiser4 esd CRAYL1_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx L1 cray + @./mkconfig $(@:_config=) ppc ppc4xx L1 cray csb272_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx csb272 + @./mkconfig $(@:_config=) ppc ppc4xx csb272 csb472_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx csb472 + @./mkconfig $(@:_config=) ppc ppc4xx csb472 DASA_SIM_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx dasa_sim esd + @./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd DP405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx dp405 esd + @./mkconfig $(@:_config=) ppc ppc4xx dp405 esd DU405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx du405 esd - -DU440_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx du440 esd + @./mkconfig $(@:_config=) ppc ppc4xx du405 esd ebony_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx ebony amcc + @./mkconfig $(@:_config=) ppc ppc4xx ebony amcc ERIC_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx eric + @./mkconfig $(@:_config=) ppc ppc4xx eric EXBITGEN_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx exbitgen + @./mkconfig $(@:_config=) ppc ppc4xx exbitgen G2000_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000 - -hcu4_config: unconfig - @mkdir -p $(obj)board/netstal/common - @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal - -hcu5_config: unconfig - @mkdir -p $(obj)board/netstal/common - @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal + @./mkconfig $(@:_config=) ppc ppc4xx g2000 HH405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd + @./mkconfig $(@:_config=) ppc ppc4xx hh405 esd HUB405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx hub405 esd + @./mkconfig $(@:_config=) ppc ppc4xx hub405 esd JSE_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx jse + @./mkconfig $(@:_config=) ppc ppc4xx jse KAREF_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx karef sandburst - -katmai_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx katmai amcc - -# Kilauea & Haleakala images are identical (recognized via PVR) -kilauea_config \ -haleakala_config: unconfig - @$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc - -kilauea_nand_config \ -haleakala_nand_config: unconfig - @mkdir -p $(obj)include $(obj)board/amcc/kilauea - @mkdir -p $(obj)nand_spl/board/amcc/kilauea - @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h - @$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc - @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/kilauea/config.tmp - @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk - -korat_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx korat + @./mkconfig $(@:_config=) ppc ppc4xx karef sandburst luan_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc - -lwmon5_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5 - -makalu_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx makalu amcc - -mcu25_config: unconfig - @mkdir -p $(obj)board/netstal/common - @$(MKCONFIG) $(@:_config=) ppc ppc4xx mcu25 netstal + @./mkconfig $(@:_config=) ppc ppc4xx luan amcc METROBOX_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst + @./mkconfig $(@:_config=) ppc ppc4xx metrobox sandburst MIP405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx mip405 mpl + @./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl MIP405T_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_MIP405T" >$(obj)include/config.h - @$(XECHO) "Enable subset config for MIP405T" - @$(MKCONFIG) -a MIP405 ppc ppc4xx mip405 mpl + @echo "#define CONFIG_MIP405T" >include/config.h + @echo "Enable subset config for MIP405T" + @./mkconfig -a MIP405 ppc ppc4xx mip405 mpl ML2_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml2 + @./mkconfig $(@:_config=) ppc ppc4xx ml2 ml300_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml300 xilinx + @./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx ocotea_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc + @./mkconfig $(@:_config=) ppc ppc4xx ocotea amcc OCRTC_config \ ORSG_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx ocrtc esd + @./mkconfig $(@:_config=) ppc ppc4xx ocrtc esd p3p440_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx p3p440 prodrive + @./mkconfig $(@:_config=) ppc ppc4xx p3p440 prodrive PCI405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx pci405 esd + @./mkconfig $(@:_config=) ppc ppc4xx pci405 esd pcs440ep_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx pcs440ep + @./mkconfig $(@:_config=) ppc ppc4xx pcs440ep PIP405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx pip405 mpl + @./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl PLU405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx plu405 esd + @./mkconfig $(@:_config=) ppc ppc4xx plu405 esd PMC405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd - -PMC440_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc440 esd + @./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd PPChameleonEVB_config \ PPChameleonEVB_BA_25_config \ @@ -1383,95 +966,66 @@ PPChameleonEVB_HI_25_config \ PPChameleonEVB_BA_33_config \ PPChameleonEVB_ME_33_config \ PPChameleonEVB_HI_33_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring EVB_BA,$@)" ] || \ - { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>$(obj)include/config.h ; \ - $(XECHO) "... BASIC model" ; \ + { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \ + echo "... BASIC model" ; \ } @[ -z "$(findstring EVB_ME,$@)" ] || \ - { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>$(obj)include/config.h ; \ - $(XECHO) "... MEDIUM model" ; \ + { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>include/config.h ; \ + echo "... MEDIUM model" ; \ } @[ -z "$(findstring EVB_HI,$@)" ] || \ - { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>$(obj)include/config.h ; \ - $(XECHO) "... HIGH-END model" ; \ + { echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \ + echo "... HIGH-END model" ; \ } @[ -z "$(findstring _25,$@)" ] || \ - { echo "#define CONFIG_PPCHAMELEON_CLK_25" >>$(obj)include/config.h ; \ - $(XECHO) "SysClk = 25MHz" ; \ + { echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \ + echo "SysClk = 25MHz" ; \ } @[ -z "$(findstring _33,$@)" ] || \ - { echo "#define CONFIG_PPCHAMELEON_CLK_33" >>$(obj)include/config.h ; \ - $(XECHO) "SysClk = 33MHz" ; \ + { echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \ + echo "SysClk = 33MHz" ; \ } - @$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave - -quad100hd_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx quad100hd + @./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave sbc405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405 + @./mkconfig $(@:_config=) ppc ppc4xx sbc405 -sc3_config:unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3 - -sequoia_config \ -rainier_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \ - tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h - @$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc - -sequoia_nand_config \ -rainier_nand_config: unconfig - @mkdir -p $(obj)include $(obj)board/amcc/sequoia - @mkdir -p $(obj)nand_spl/board/amcc/sequoia - @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h - @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \ - tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h - @$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc - @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp - @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk - -taihu_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc - -taishan_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc +sycamore_config: unconfig + @echo "Configuring for sycamore board as subset of walnut..." + @./mkconfig -a walnut ppc ppc4xx walnut amcc VOH405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd + @./mkconfig $(@:_config=) ppc ppc4xx voh405 esd VOM405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx vom405 esd + @./mkconfig $(@:_config=) ppc ppc4xx vom405 esd + +CMS700_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx cms700 esd W7OLMC_config \ W7OLMG_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx w7o + @./mkconfig $(@:_config=) ppc ppc4xx w7o -# Walnut & Sycamore images are identical (recognized via PVR) -walnut_config \ -sycamore_config: unconfig - @$(MKCONFIG) -n $@ -a walnut ppc ppc4xx walnut amcc +walnut_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx walnut amcc WUH405_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd + @./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd XPEDITE1K_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1k + @./mkconfig $(@:_config=) ppc ppc4xx xpedite1k -yosemite_config \ -yellowstone_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \ - tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h - @$(MKCONFIG) -n $@ -a yosemite ppc ppc4xx yosemite amcc +yosemite_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx yosemite amcc + +yellowstone_config: unconfig + @./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc yucca_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc - -zeus_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx zeus + @./mkconfig $(@:_config=) ppc ppc4xx yucca amcc ######################################################################### ## MPC8220 Systems @@ -1479,10 +1033,10 @@ zeus_config: unconfig Alaska8220_config \ Yukon8220_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8220 alaska + @./mkconfig $(@:_config=) ppc mpc8220 alaska sorcery_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8220 sorcery + @./mkconfig $(@:_config=) ppc mpc8220 sorcery ######################################################################### ## MPC824x Systems @@ -1490,152 +1044,133 @@ sorcery_config: unconfig xtract_82xx = $(subst _BIGFLASH,,$(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1)))))) A3000_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x a3000 + @./mkconfig $(@:_config=) ppc mpc824x a3000 barco_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x barco + @./mkconfig $(@:_config=) ppc mpc824x barco BMW_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x bmw + @./mkconfig $(@:_config=) ppc mpc824x bmw CPC45_config \ CPC45_ROMBOOT_config: unconfig - @$(MKCONFIG) $(call xtract_82xx,$@) ppc mpc824x cpc45 - @cd $(obj)include ; \ + @./mkconfig $(call xtract_82xx,$@) ppc mpc824x cpc45 + @cd ./include ; \ if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ echo "CONFIG_BOOT_ROM = y" >> config.mk ; \ - $(XECHO) "... booting from 8-bit flash" ; \ + echo "... booting from 8-bit flash" ; \ else \ echo "CONFIG_BOOT_ROM = n" >> config.mk ; \ - $(XECHO) "... booting from 64-bit flash" ; \ + echo "... booting from 64-bit flash" ; \ fi; \ echo "export CONFIG_BOOT_ROM" >> config.mk; CU824_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x cu824 + @./mkconfig $(@:_config=) ppc mpc824x cu824 debris_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x debris etin + @./mkconfig $(@:_config=) ppc mpc824x debris etin eXalion_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x eXalion + @./mkconfig $(@:_config=) ppc mpc824x eXalion HIDDEN_DRAGON_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x hidden_dragon + @./mkconfig $(@:_config=) ppc mpc824x hidden_dragon kvme080_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x kvme080 etin - -# HDLAN is broken ATM. Should be fixed as soon as hardware is available and as -# time permits. -#linkstation_HDLAN_config \ -# Remove this line when HDLAN is fixed -linkstation_HGLAN_config: unconfig - @mkdir -p $(obj)include - @case $@ in \ - *HGLAN*) echo "#define CONFIG_HGLAN 1" >$(obj)include/config.h; ;; \ - *HDLAN*) echo "#define CONFIG_HLAN 1" >$(obj)include/config.h; ;; \ - esac - @$(MKCONFIG) -n $@ -a linkstation ppc mpc824x linkstation + @./mkconfig $(@:_config=) ppc mpc824x kvme080 etin MOUSSE_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x mousse + @./mkconfig $(@:_config=) ppc mpc824x mousse MUSENKI_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x musenki + @./mkconfig $(@:_config=) ppc mpc824x musenki MVBLUE_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x mvblue + @./mkconfig $(@:_config=) ppc mpc824x mvblue OXC_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x oxc + @./mkconfig $(@:_config=) ppc mpc824x oxc PN62_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x pn62 + @./mkconfig $(@:_config=) ppc mpc824x pn62 Sandpoint8240_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x sandpoint + @./mkconfig $(@:_config=) ppc mpc824x sandpoint Sandpoint8245_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x sandpoint + @./mkconfig $(@:_config=) ppc mpc824x sandpoint sbc8240_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x sbc8240 + @./mkconfig $(@:_config=) ppc mpc824x sbc8240 SL8245_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x sl8245 + @./mkconfig $(@:_config=) ppc mpc824x sl8245 utx8245_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc824x utx8245 + @./mkconfig $(@:_config=) ppc mpc824x utx8245 ######################################################################### ## MPC8260 Systems ######################################################################### atc_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 atc + @./mkconfig $(@:_config=) ppc mpc8260 atc cogent_mpc8260_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 cogent + @./mkconfig $(@:_config=) ppc mpc8260 cogent CPU86_config \ CPU86_ROMBOOT_config: unconfig - @$(MKCONFIG) $(call xtract_82xx,$@) ppc mpc8260 cpu86 - @cd $(obj)include ; \ + @./mkconfig $(call xtract_82xx,$@) ppc mpc8260 cpu86 + @cd ./include ; \ if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ echo "CONFIG_BOOT_ROM = y" >> config.mk ; \ - $(XECHO) "... booting from 8-bit flash" ; \ + echo "... booting from 8-bit flash" ; \ else \ echo "CONFIG_BOOT_ROM = n" >> config.mk ; \ - $(XECHO) "... booting from 64-bit flash" ; \ + echo "... booting from 64-bit flash" ; \ fi; \ echo "export CONFIG_BOOT_ROM" >> config.mk; CPU87_config \ CPU87_ROMBOOT_config: unconfig - @$(MKCONFIG) $(call xtract_82xx,$@) ppc mpc8260 cpu87 - @cd $(obj)include ; \ + @./mkconfig $(call xtract_82xx,$@) ppc mpc8260 cpu87 + @cd ./include ; \ if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ echo "CONFIG_BOOT_ROM = y" >> config.mk ; \ - $(XECHO) "... booting from 8-bit flash" ; \ + echo "... booting from 8-bit flash" ; \ else \ echo "CONFIG_BOOT_ROM = n" >> config.mk ; \ - $(XECHO) "... booting from 64-bit flash" ; \ + echo "... booting from 64-bit flash" ; \ fi; \ echo "export CONFIG_BOOT_ROM" >> config.mk; ep8248_config \ ep8248E_config : unconfig - @$(MKCONFIG) ep8248 ppc mpc8260 ep8248 + @./mkconfig ep8248 ppc mpc8260 ep8248 ep8260_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 ep8260 - -ep82xxm_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 ep82xxm + @./mkconfig $(@:_config=) ppc mpc8260 ep8260 gw8260_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 gw8260 + @./mkconfig $(@:_config=) ppc mpc8260 gw8260 hymod_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 hymod + @./mkconfig $(@:_config=) ppc mpc8260 hymod IDS8247_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 ids8247 + @./mkconfig $(@:_config=) ppc mpc8260 ids8247 IPHASE4539_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 iphase4539 + @./mkconfig $(@:_config=) ppc mpc8260 iphase4539 ISPAN_config \ ISPAN_REVB_config: unconfig - @mkdir -p $(obj)include @if [ "$(findstring _REVB_,$@)" ] ; then \ - echo "#define CFG_REV_B" > $(obj)include/config.h ; \ + echo "#define CFG_REV_B" > include/config.h ; \ fi - @$(MKCONFIG) -a ISPAN ppc mpc8260 ispan - -mgcoge_config : unconfig - @$(MKCONFIG) mgcoge ppc mpc8260 mgcoge + @./mkconfig -a ISPAN ppc mpc8260 ispan MPC8260ADS_config \ MPC8260ADS_lowboot_config \ @@ -1654,23 +1189,21 @@ PQ2FADS-ZU_lowboot_config \ PQ2FADS-ZU_66MHz_config \ PQ2FADS-ZU_66MHz_lowboot_config \ : unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/freescale/mpc8260ads $(if $(findstring PQ2FADS,$@), \ - @echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \ - @echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h) + @echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > include/config.h, \ + @echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > include/config.h) $(if $(findstring MHz,$@), \ - @echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> $(obj)include/config.h, \ + @echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> include/config.h, \ $(if $(findstring VR,$@), \ - @echo "#define CONFIG_8260_CLKIN 66000000" >> $(obj)include/config.h)) + @echo "#define CONFIG_8260_CLKIN 66000000" >> include/config.h)) @[ -z "$(findstring lowboot_,$@)" ] || \ - { echo "TEXT_BASE = 0xFF800000" >$(obj)board/freescale/mpc8260ads/config.tmp ; \ - $(XECHO) "... with lowboot configuration" ; \ + { echo "TEXT_BASE = 0xFF800000" >board/mpc8260ads/config.tmp ; \ + echo "... with lowboot configuration" ; \ } - @$(MKCONFIG) -a MPC8260ADS ppc mpc8260 mpc8260ads freescale + @./mkconfig -a MPC8260ADS ppc mpc8260 mpc8260ads MPC8266ADS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads freescale + @./mkconfig $(@:_config=) ppc mpc8260 mpc8266ads # PM825/PM826 default configuration: small (= 8 MB) Flash / boot from 64-bit flash PM825_config \ @@ -1681,74 +1214,71 @@ PM826_config \ PM826_ROMBOOT_config \ PM826_BIGFLASH_config \ PM826_ROMBOOT_BIGFLASH_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/pm826 @if [ "$(findstring PM825_,$@)" ] ; then \ - echo "#define CONFIG_PCI" >$(obj)include/config.h ; \ + echo "#define CONFIG_PCI" >include/config.h ; \ else \ - >$(obj)include/config.h ; \ + >include/config.h ; \ fi @if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ - $(XECHO) "... booting from 8-bit flash" ; \ - echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h ; \ - echo "TEXT_BASE = 0xFF800000" >$(obj)board/pm826/config.tmp ; \ + echo "... booting from 8-bit flash" ; \ + echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \ + echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \ if [ "$(findstring _BIGFLASH_,$@)" ] ; then \ - $(XECHO) "... with 32 MB Flash" ; \ - echo "#define CONFIG_FLASH_32MB" >>$(obj)include/config.h ; \ + echo "... with 32 MB Flash" ; \ + echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \ fi; \ else \ - $(XECHO) "... booting from 64-bit flash" ; \ + echo "... booting from 64-bit flash" ; \ if [ "$(findstring _BIGFLASH_,$@)" ] ; then \ - $(XECHO) "... with 32 MB Flash" ; \ - echo "#define CONFIG_FLASH_32MB" >>$(obj)include/config.h ; \ - echo "TEXT_BASE = 0x40000000" >$(obj)board/pm826/config.tmp ; \ + echo "... with 32 MB Flash" ; \ + echo "#define CONFIG_FLASH_32MB" >>include/config.h ; \ + echo "TEXT_BASE = 0x40000000" >board/pm826/config.tmp ; \ else \ - echo "TEXT_BASE = 0xFF000000" >$(obj)board/pm826/config.tmp ; \ + echo "TEXT_BASE = 0xFF000000" >board/pm826/config.tmp ; \ fi; \ fi - @$(MKCONFIG) -a PM826 ppc mpc8260 pm826 + @./mkconfig -a PM826 ppc mpc8260 pm826 PM828_config \ PM828_PCI_config \ PM828_ROMBOOT_config \ PM828_ROMBOOT_PCI_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/pm826 @if [ "$(findstring _PCI_,$@)" ] ; then \ - echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ - $(XECHO) "... with PCI enabled" ; \ + echo "#define CONFIG_PCI" >>include/config.h ; \ + echo "... with PCI enabled" ; \ + else \ + >include/config.h ; \ fi @if [ "$(findstring _ROMBOOT_,$@)" ] ; then \ - $(XECHO) "... booting from 8-bit flash" ; \ - echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h ; \ - echo "TEXT_BASE = 0xFF800000" >$(obj)board/pm826/config.tmp ; \ + echo "... booting from 8-bit flash" ; \ + echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \ + echo "TEXT_BASE = 0xFF800000" >board/pm826/config.tmp ; \ fi - @$(MKCONFIG) -a PM828 ppc mpc8260 pm828 + @./mkconfig -a PM828 ppc mpc8260 pm828 ppmc8260_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 ppmc8260 + @./mkconfig $(@:_config=) ppc mpc8260 ppmc8260 Rattler8248_config \ Rattler_config: unconfig - @mkdir -p $(obj)include $(if $(findstring 8248,$@), \ - @echo "#define CONFIG_MPC8248" > $(obj)include/config.h) - @$(MKCONFIG) -a Rattler ppc mpc8260 rattler + @echo "#define CONFIG_MPC8248" > include/config.h) + @./mkconfig -a Rattler ppc mpc8260 rattler RPXsuper_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 rpxsuper + @./mkconfig $(@:_config=) ppc mpc8260 rpxsuper rsdproto_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 rsdproto + @./mkconfig $(@:_config=) ppc mpc8260 rsdproto sacsng_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 sacsng + @./mkconfig $(@:_config=) ppc mpc8260 sacsng sbc8260_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 sbc8260 + @./mkconfig $(@:_config=) ppc mpc8260 sbc8260 SCM_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 SCM siemens + @./mkconfig $(@:_config=) ppc mpc8260 SCM siemens TQM8255_AA_config \ TQM8260_AA_config \ @@ -1761,7 +1291,6 @@ TQM8260_AG_config \ TQM8260_AH_config \ TQM8260_AI_config \ TQM8265_AA_config: unconfig - @mkdir -p $(obj)include @case "$@" in \ TQM8255_AA_config) CTYPE=MPC8255; CFREQ=300; CACHE=no; BMODE=8260;; \ TQM8260_AA_config) CTYPE=MPC8260; CFREQ=200; CACHE=no; BMODE=8260;; \ @@ -1775,550 +1304,205 @@ TQM8265_AA_config: unconfig TQM8260_AI_config) CTYPE=MPC8260; CFREQ=300; CACHE=no; BMODE=60x;; \ TQM8265_AA_config) CTYPE=MPC8265; CFREQ=300; CACHE=no; BMODE=60x;; \ esac; \ + >include/config.h ; \ if [ "$${CTYPE}" != "MPC8260" ] ; then \ - echo "#define CONFIG_$${CTYPE}" >>$(obj)include/config.h ; \ + echo "#define CONFIG_$${CTYPE}" >>include/config.h ; \ fi; \ - echo "#define CONFIG_$${CFREQ}MHz" >>$(obj)include/config.h ; \ + echo "#define CONFIG_$${CFREQ}MHz" >>include/config.h ; \ echo "... with $${CFREQ}MHz system clock" ; \ - if [ "$${CACHE}" = "yes" ] ; then \ - echo "#define CONFIG_L2_CACHE" >>$(obj)include/config.h ; \ - $(XECHO) "... with L2 Cache support" ; \ + if [ "$${CACHE}" == "yes" ] ; then \ + echo "#define CONFIG_L2_CACHE" >>include/config.h ; \ + echo "... with L2 Cache support" ; \ else \ - echo "#undef CONFIG_L2_CACHE" >>$(obj)include/config.h ; \ - $(XECHO) "... without L2 Cache support" ; \ + echo "#undef CONFIG_L2_CACHE" >>include/config.h ; \ + echo "... without L2 Cache support" ; \ fi; \ - if [ "$${BMODE}" = "60x" ] ; then \ - echo "#define CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \ - $(XECHO) "... with 60x Bus Mode" ; \ + if [ "$${BMODE}" == "60x" ] ; then \ + echo "#define CONFIG_BUSMODE_60x" >>include/config.h ; \ + echo "... with 60x Bus Mode" ; \ else \ - echo "#undef CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \ - $(XECHO) "... without 60x Bus Mode" ; \ + echo "#undef CONFIG_BUSMODE_60x" >>include/config.h ; \ + echo "... without 60x Bus Mode" ; \ fi - @$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260 tqc - -TQM8272_config: unconfig - @$(MKCONFIG) TQM8272 ppc mpc8260 tqm8272 tqc + @./mkconfig -a TQM8260 ppc mpc8260 tqm8260 VoVPN-GW_66MHz_config \ VoVPN-GW_100MHz_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > $(obj)include/config.h - @$(MKCONFIG) -a VoVPN-GW ppc mpc8260 vovpn-gw funkwerk + @echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > include/config.h + @./mkconfig -a VoVPN-GW ppc mpc8260 vovpn-gw funkwerk ZPC1900_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8260 zpc1900 + @./mkconfig $(@:_config=) ppc mpc8260 zpc1900 ######################################################################### ## Coldfire ######################################################################### -M52277EVB_config: unconfig - @$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale - -M5235EVB_config \ -M5235EVB_Flash16_config \ -M5235EVB_Flash32_config: unconfig - @case "$@" in \ - M5235EVB_config) FLASH=16;; \ - M5235EVB_Flash16_config) FLASH=16;; \ - M5235EVB_Flash32_config) FLASH=32;; \ - esac; \ - if [ "$${FLASH}" != "16" ] ; then \ - echo "#define NORFLASH_PS32BIT 1" >> $(obj)include/config.h ; \ - echo "TEXT_BASE = 0xFFC00000" > $(obj)board/freescale/m5235evb/config.tmp ; \ - cp $(obj)board/freescale/m5235evb/u-boot.32 $(obj)board/freescale/m5235evb/u-boot.lds ; \ - else \ - echo "TEXT_BASE = 0xFFE00000" > $(obj)board/freescale/m5235evb/config.tmp ; \ - cp $(obj)board/freescale/m5235evb/u-boot.16 $(obj)board/freescale/m5235evb/u-boot.lds ; \ - fi - @$(MKCONFIG) -a M5235EVB m68k mcf523x m5235evb freescale - -M5249EVB_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5249evb freescale - -M5253EVBE_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5253evbe freescale - cobra5272_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 cobra5272 + @./mkconfig $(@:_config=) m68k mcf52x2 cobra5272 EB+MCF-EV123_config : unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/BuS/EB+MCF-EV123 - @echo "TEXT_BASE = 0xFFE00000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk - @$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS + @ >include/config.h + @echo "TEXT_BASE = 0xFFE00000"|tee board/BuS/EB+MCF-EV123/textbase.mk + @./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS EB+MCF-EV123_internal_config : unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/BuS/EB+MCF-EV123 - @echo "TEXT_BASE = 0xF0000000"|tee $(obj)board/BuS/EB+MCF-EV123/textbase.mk - @$(MKCONFIG) EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS - -idmr_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 idmr + @ >include/config.h + @echo "TEXT_BASE = 0xF0000000"|tee board/BuS/EB+MCF-EV123/textbase.mk + @./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS M5271EVB_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5271evb + @./mkconfig $(@:_config=) m68k mcf52x2 m5271evb M5272C3_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3 - -M5275EVB_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5275evb freescale + @./mkconfig $(@:_config=) m68k mcf52x2 m5272c3 M5282EVB_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb - -M5329AFEE_config \ -M5329BFEE_config : unconfig - @case "$@" in \ - M5329AFEE_config) NAND=0;; \ - M5329BFEE_config) NAND=16;; \ - esac; \ - if [ "$${NAND}" != "0" ] ; then \ - echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \ - fi - @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale - -M5373EVB_config : unconfig - @case "$@" in \ - M5373EVB_config) NAND=16;; \ - esac; \ - if [ "$${NAND}" != "0" ] ; then \ - echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \ - fi - @$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale - -M54455EVB_config \ -M54455EVB_atmel_config \ -M54455EVB_intel_config \ -M54455EVB_a33_config \ -M54455EVB_a66_config \ -M54455EVB_i33_config \ -M54455EVB_i66_config : unconfig - @case "$@" in \ - M54455EVB_config) FLASH=ATMEL; FREQ=33333333;; \ - M54455EVB_atmel_config) FLASH=ATMEL; FREQ=33333333;; \ - M54455EVB_intel_config) FLASH=INTEL; FREQ=33333333;; \ - M54455EVB_a33_config) FLASH=ATMEL; FREQ=33333333;; \ - M54455EVB_a66_config) FLASH=ATMEL; FREQ=66666666;; \ - M54455EVB_i33_config) FLASH=INTEL; FREQ=33333333;; \ - M54455EVB_i66_config) FLASH=INTEL; FREQ=66666666;; \ - esac; \ - if [ "$${FLASH}" = "INTEL" ] ; then \ - echo "#undef CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ - echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \ - cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \ - $(XECHO) "... with INTEL boot..." ; \ - else \ - echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \ - echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \ - cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \ - $(XECHO) "... with ATMEL boot..." ; \ - fi; \ - echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \ - $(XECHO) "... with $${FREQ}Hz input clock" - @$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale - -M5475AFE_config \ -M5475BFE_config \ -M5475CFE_config \ -M5475DFE_config \ -M5475EFE_config \ -M5475FFE_config \ -M5475GFE_config : unconfig - @case "$@" in \ - M5475AFE_config) BOOT=2;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \ - M5475BFE_config) BOOT=2;CODE=16;VID=0;USB=0;RAM=64;RAM1=0;; \ - M5475CFE_config) BOOT=2;CODE=16;VID=1;USB=1;RAM=64;RAM1=0;; \ - M5475DFE_config) BOOT=2;CODE=0;VID=0;USB=1;RAM=64;RAM1=0;; \ - M5475EFE_config) BOOT=2;CODE=0;VID=1;USB=1;RAM=64;RAM1=0;; \ - M5475FFE_config) BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \ - M5475GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \ - esac; \ - echo "#define CFG_BUSCLK 133333333" > $(obj)include/config.h ; \ - echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \ - echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \ - if [ "$${RAM1}" != "0" ] ; then \ - echo "#define CFG_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \ - fi; \ - if [ "$${CODE}" != "0" ] ; then \ - echo "#define CFG_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \ - fi; \ - if [ "$${VID}" == "1" ] ; then \ - echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \ - fi; \ - if [ "$${USB}" == "1" ] ; then \ - echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \ - fi - @$(MKCONFIG) -a M5475EVB m68k mcf547x_8x m547xevb freescale - -M5485AFE_config \ -M5485BFE_config \ -M5485CFE_config \ -M5485DFE_config \ -M5485EFE_config \ -M5485FFE_config \ -M5485GFE_config \ -M5485HFE_config : unconfig - @case "$@" in \ - M5485AFE_config) BOOT=2;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \ - M5485BFE_config) BOOT=2;CODE=16;VID=0;USB=0;RAM=64;RAM1=0;; \ - M5485CFE_config) BOOT=2;CODE=16;VID=1;USB=1;RAM=64;RAM1=0;; \ - M5485DFE_config) BOOT=2;CODE=0;VID=0;USB=1;RAM=64;RAM1=0;; \ - M5485EFE_config) BOOT=2;CODE=0;VID=1;USB=1;RAM=64;RAM1=0;; \ - M5485FFE_config) BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \ - M5485GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \ - M5485HFE_config) BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \ - esac; \ - echo "#define CFG_BUSCLK 100000000" > $(obj)include/config.h ; \ - echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \ - echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \ - if [ "$${RAM1}" != "0" ] ; then \ - echo "#define CFG_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \ - fi; \ - if [ "$${CODE}" != "0" ] ; then \ - echo "#define CFG_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \ - fi; \ - if [ "$${VID}" == "1" ] ; then \ - echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \ - fi; \ - if [ "$${USB}" == "1" ] ; then \ - echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \ - fi - @$(MKCONFIG) -a M5485EVB m68k mcf547x_8x m548xevb freescale + @./mkconfig $(@:_config=) m68k mcf52x2 m5282evb TASREG_config : unconfig - @$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd + @./mkconfig $(@:_config=) m68k mcf52x2 tasreg esd + +r5200_config : unconfig + @./mkconfig $(@:_config=) m68k mcf52x2 r5200 ######################################################################### ## MPC83xx Systems ######################################################################### -MPC8313ERDB_33_config \ -MPC8313ERDB_66_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _33_,$@)" ] ; then \ - $(XECHO) -n "...33M ..." ; \ - echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _66_,$@)" ] ; then \ - $(XECHO) -n "...66M..." ; \ - echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \ - fi ; - @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale - -MPC8315ERDB_config: unconfig - @$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale - -MPC8323ERDB_config: unconfig - @$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale - -MPC832XEMDS_config \ -MPC832XEMDS_HOST_33_config \ -MPC832XEMDS_HOST_66_config \ -MPC832XEMDS_SLAVE_config \ -MPC832XEMDS_ATM_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _HOST_,$@)" ] ; then \ - $(XECHO) -n "... PCI HOST " ; \ - echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _SLAVE_,$@)" ] ; then \ - $(XECHO) "...PCI SLAVE 66M" ; \ - echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ - echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _33_,$@)" ] ; then \ - $(XECHO) -n "...33M ..." ; \ - echo "#define PCI_33M" >>$(obj)include/config.h ; \ - echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _66_,$@)" ] ; then \ - $(XECHO) -n "...66M..." ; \ - echo "#define PCI_66M" >>$(obj)include/config.h ; \ - echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _ATM_,$@)" ] ; then \ - $(XECHO) -n "...ATM..." ; \ - echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ - echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \ - fi ; - @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale - -MPC8349EMDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds freescale - -MPC8349ITX_config \ -MPC8349ITX_LOWBOOT_config \ -MPC8349ITXGP_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/freescale/mpc8349itx - @echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h - @if [ "$(findstring GP,$@)" ] ; then \ - echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \ - fi - @if [ "$(findstring LOWBOOT,$@)" ] ; then \ - echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \ - fi - @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale - -MPC8360EMDS_config \ -MPC8360EMDS_HOST_33_config \ -MPC8360EMDS_HOST_66_config \ -MPC8360EMDS_SLAVE_config \ -MPC8360EMDS_ATM_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _HOST_,$@)" ] ; then \ - $(XECHO) -n "... PCI HOST " ; \ - echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _SLAVE_,$@)" ] ; then \ - $(XECHO) "...PCI SLAVE 66M" ; \ - echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ - echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _33_,$@)" ] ; then \ - $(XECHO) -n "...33M ..." ; \ - echo "#define PCI_33M" >>$(obj)include/config.h ; \ - echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _66_,$@)" ] ; then \ - $(XECHO) -n "...66M..." ; \ - echo "#define PCI_66M" >>$(obj)include/config.h ; \ - echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _ATM_,$@)" ] ; then \ - $(XECHO) -n "...ATM..." ; \ - echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \ - echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \ - fi ; - @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale - -MPC8360ERDK_33_config \ -MPC8360ERDK_66_config \ -MPC8360ERDK_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _33_,$@)" ] ; then \ - $(XECHO) -n "... CLKIN 33MHz " ; \ - echo "#define CONFIG_CLKIN_33MHZ" >>$(obj)include/config.h ;\ - fi ; - @$(MKCONFIG) -a MPC8360ERDK ppc mpc83xx mpc8360erdk freescale - -MPC837XEMDS_config \ -MPC837XEMDS_HOST_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _HOST_,$@)" ] ; then \ - $(XECHO) -n "... PCI HOST " ; \ - echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ - fi ; - @$(MKCONFIG) -a MPC837XEMDS ppc mpc83xx mpc837xemds freescale - -MPC837XERDB_config: unconfig - @$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale - -MVBLM7_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 - -sbc8349_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 +MPC8349ADS_config: unconfig + @./mkconfig $(@:_config=) ppc mpc83xx mpc8349ads TQM834x_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc + @./mkconfig $(@:_config=) ppc mpc83xx tqm834x +MPC8349EMDS_config: unconfig + @./mkconfig $(@:_config=) ppc mpc83xx mpc8349emds ######################################################################### ## MPC85xx Systems ######################################################################### -ATUM8548_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548 - MPC8540ADS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale + @./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads MPC8540EVAL_config \ MPC8540EVAL_33_config \ MPC8540EVAL_66_config \ MPC8540EVAL_33_slave_config \ -MPC8540EVAL_66_slave_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _33_,$@)" ] ; then \ - $(XECHO) "... 33 MHz PCI" ; \ +MPC8540EVAL_66_slave_config: unconfig + @echo "" >include/config.h ; \ + if [ "$(findstring _33_,$@)" ] ; then \ + echo -n "... 33 MHz PCI" ; \ else \ - echo "#define CONFIG_SYSCLK_66M" >>$(obj)include/config.h ; \ - $(XECHO) "... 66 MHz PCI" ; \ + echo "#define CONFIG_SYSCLK_66M" >>include/config.h ; \ + echo -n "... 66 MHz PCI" ; \ fi ; \ if [ "$(findstring _slave_,$@)" ] ; then \ - echo "#define CONFIG_PCI_SLAVE" >>$(obj)include/config.h ; \ - $(XECHO) " slave" ; \ + echo "#define CONFIG_PCI_SLAVE" >>include/config.h ; \ + echo " slave" ; \ else \ - $(XECHO) " host" ; \ + echo " host" ; \ fi - @$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval + @./mkconfig -a MPC8540EVAL ppc mpc85xx mpc8540eval MPC8560ADS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads freescale + @./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads -MPC8541CDS_legacy_config \ MPC8541CDS_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _legacy_,$@)" ] ; then \ - echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ - $(XECHO) "... legacy" ; \ - fi - @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds freescale + @./mkconfig $(@:_config=) ppc mpc85xx mpc8541cds cds -MPC8544DS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale - -MPC8548CDS_legacy_config \ MPC8548CDS_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _legacy_,$@)" ] ; then \ - echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ - $(XECHO) "... legacy" ; \ - fi - @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds freescale + @./mkconfig $(@:_config=) ppc mpc85xx mpc8548cds cds -MPC8555CDS_legacy_config \ MPC8555CDS_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _legacy_,$@)" ] ; then \ - echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \ - $(XECHO) "... legacy" ; \ - fi - @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds freescale - -MPC8568MDS_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale + @./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds PM854_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 + @./mkconfig $(@:_config=) ppc mpc85xx pm854 PM856_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm856 + @./mkconfig $(@:_config=) ppc mpc85xx pm856 sbc8540_config \ sbc8540_33_config \ sbc8540_66_config: unconfig - @mkdir -p $(obj)include @if [ "$(findstring _66_,$@)" ] ; then \ - echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \ - $(XECHO) "... 66 MHz PCI" ; \ + echo "#define CONFIG_PCI_66" >>include/config.h ; \ + echo "... 66 MHz PCI" ; \ else \ - $(XECHO) "... 33 MHz PCI" ; \ + >include/config.h ; \ + echo "... 33 MHz PCI" ; \ fi - @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 - -sbc8548_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548 + @./mkconfig -a SBC8540 ppc mpc85xx sbc8560 sbc8560_config \ sbc8560_33_config \ -sbc8560_66_config: unconfig - @mkdir -p $(obj)include +sbc8560_66_config: unconfig @if [ "$(findstring _66_,$@)" ] ; then \ - echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \ - $(XECHO) "... 66 MHz PCI" ; \ + echo "#define CONFIG_PCI_66" >>include/config.h ; \ + echo "... 66 MHz PCI" ; \ else \ - $(XECHO) "... 33 MHz PCI" ; \ + >include/config.h ; \ + echo "... 33 MHz PCI" ; \ fi - @$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560 - -socrates_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates + @./mkconfig -a sbc8560 ppc mpc85xx sbc8560 stxgp3_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 - -stxssa_config \ -stxssa_4M_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _4M_,$@)" ] ; then \ - echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \ - $(XECHO) "... with 4 MiB flash memory" ; \ - fi - @$(MKCONFIG) -a stxssa ppc mpc85xx stxssa + @./mkconfig $(@:_config=) ppc mpc85xx stxgp3 TQM8540_config \ TQM8541_config \ -TQM8548_config \ TQM8555_config \ TQM8560_config: unconfig - @mkdir -p $(obj)include @CTYPE=$(subst TQM,,$(@:_config=)); \ - $(XECHO) "... TQM"$${CTYPE}; \ - echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \ - echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \ - echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \ - echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h; - @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc - -######################################################################### -## MPC86xx Systems -######################################################################### - -MPC8610HPCD_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale - -MPC8641HPCN_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn freescale - -sbc8641d_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d + >include/config.h ; \ + echo "... TQM"$${CTYPE}; \ + echo "#define CONFIG_MPC$${CTYPE}">>include/config.h; \ + echo "#define CONFIG_TQM$${CTYPE}">>include/config.h; \ + echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>include/config.h; \ + echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>include/config.h; \ + echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>include/config.h + @./mkconfig -a TQM85xx ppc mpc85xx tqm85xx ######################################################################### ## 74xx/7xx Systems ######################################################################### AmigaOneG3SE_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx AmigaOneG3SE MAI + @./mkconfig $(@:_config=) ppc 74xx_7xx AmigaOneG3SE MAI BAB7xx_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx bab7xx eltec + @./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec -CPCI750_config: unconfig - @$(MKCONFIG) CPCI750 ppc 74xx_7xx cpci750 esd +CPCI750_config: unconfig + @./mkconfig CPCI750 ppc 74xx_7xx cpci750 esd -DB64360_config: unconfig - @$(MKCONFIG) DB64360 ppc 74xx_7xx db64360 Marvell +DB64360_config: unconfig + @./mkconfig DB64360 ppc 74xx_7xx db64360 Marvell -DB64460_config: unconfig - @$(MKCONFIG) DB64460 ppc 74xx_7xx db64460 Marvell +DB64460_config: unconfig + @./mkconfig DB64460 ppc 74xx_7xx db64460 Marvell ELPPC_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx elppc eltec + @./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec EVB64260_config \ EVB64260_750CX_config: unconfig - @$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260 - -mpc7448hpc2_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2 freescale + @./mkconfig EVB64260 ppc 74xx_7xx evb64260 P3G4_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260 - -p3m750_config \ -p3m7448_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring 750_,$@)" ] ; then \ - echo "#define CONFIG_P3M750" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_P3M7448" >>$(obj)include/config.h ; \ - fi - @$(MKCONFIG) -a p3mx ppc 74xx_7xx p3mx prodrive + @./mkconfig $(@:_config=) ppc 74xx_7xx evb64260 PCIPPC2_config \ PCIPPC6_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx pcippc2 - -ppmc7xx_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx ppmc7xx + @./mkconfig $(@:_config=) ppc 74xx_7xx pcippc2 ZUMA_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260 + @./mkconfig $(@:_config=) ppc 74xx_7xx evb64260 + +ppmc7xx_config: unconfig + @./mkconfig $(@:_config=) ppc 74xx_7xx ppmc7xx #======================================================================== # ARM @@ -2328,64 +1512,42 @@ ZUMA_config: unconfig ######################################################################### assabet_config : unconfig - @$(MKCONFIG) $(@:_config=) arm sa1100 assabet + @./mkconfig $(@:_config=) arm sa1100 assabet dnp1110_config : unconfig - @$(MKCONFIG) $(@:_config=) arm sa1100 dnp1110 + @./mkconfig $(@:_config=) arm sa1100 dnp1110 gcplus_config : unconfig - @$(MKCONFIG) $(@:_config=) arm sa1100 gcplus + @./mkconfig $(@:_config=) arm sa1100 gcplus lart_config : unconfig - @$(MKCONFIG) $(@:_config=) arm sa1100 lart + @./mkconfig $(@:_config=) arm sa1100 lart shannon_config : unconfig - @$(MKCONFIG) $(@:_config=) arm sa1100 shannon + @./mkconfig $(@:_config=) arm sa1100 shannon ######################################################################### ## ARM92xT Systems ######################################################################### -######################################################################### -## Atmel AT91RM9200 Systems -######################################################################### +xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1)))) + +xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1)))) + +xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1))) at91rm9200dk_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200 - -at91sam9261ek_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91sam9 - -at91sam9263ek_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9 - -at91sam9rlek_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9 + @./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200 cmc_pu2_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200 + @./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200 csb637_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t csb637 NULL at91rm9200 - -kb9202_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t kb9202 NULL at91rm9200 - -m501sk_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t m501sk NULL at91rm9200 + @./mkconfig $(@:_config=) arm arm920t csb637 NULL at91rm9200 mp2usb_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200 + @./mkconfig $(@:_config=) arm arm920t mp2usb NULL at91rm9200 -######################################################################### -## Atmel ARM926EJ-S Systems -######################################################################### - -at91cap9adk_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91sam9 - -at91sam9260ek_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91sam9 ######################################################################## ## ARM Integrator boards - see doc/README-integrator for more info. @@ -2395,7 +1557,7 @@ ap966_config \ ap922_config \ ap922_XA10_config \ ap7_config \ -ap720t_config \ +ap720t_config \ ap920t_config \ ap926ejs_config \ ap946es_config: unconfig @@ -2413,35 +1575,35 @@ cp922_XA10_config \ cp1026_config: unconfig @board/integratorcp/split_by_variant.sh $@ -davinci_dvevm_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs dv-evm davinci davinci - -davinci_schmoogie_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci - -davinci_sffsdr_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs sffsdr davinci davinci - -davinci_sonata_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci +kb9202_config : unconfig + @./mkconfig $(@:_config=) arm arm920t kb9202 NULL at91rm9200 lpd7a400_config \ lpd7a404_config: unconfig - @$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x + @./mkconfig $(@:_config=) arm lh7a40x lpd7a40x mx1ads_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t mx1ads NULL imx + @./mkconfig $(@:_config=) arm arm920t mx1ads NULL imx mx1fs2_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx + @./mkconfig $(@:_config=) arm arm920t mx1fs2 NULL imx +netstar_32_config \ netstar_config: unconfig - @$(MKCONFIG) $(@:_config=) arm arm925t netstar + @if [ "$(findstring _32_,$@)" ] ; then \ + echo "... 32MB SDRAM" ; \ + echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>include/config.h ; \ + else \ + echo "... 64MB SDRAM" ; \ + echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>include/config.h ; \ + fi + @./mkconfig -a netstar arm arm925t netstar omap1510inn_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn + @./mkconfig $(@:_config=) arm arm925t omap1510inn -xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1)))) +omap5912osk_config : unconfig + @./mkconfig $(@:_config=) arm arm926ejs omap5912osk NULL omap omap1610inn_config \ omap1610inn_cs0boot_config \ @@ -2451,231 +1613,255 @@ omap1610h2_config \ omap1610h2_cs0boot_config \ omap1610h2_cs3boot_config \ omap1610h2_cs_autoboot_config: unconfig - @mkdir -p $(obj)include @if [ "$(findstring _cs0boot_, $@)" ] ; then \ - echo "#define CONFIG_CS0_BOOT" >> .$(obj)include/config.h ; \ - $(XECHO) "... configured for CS0 boot"; \ + echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \ + echo "... configured for CS0 boot"; \ elif [ "$(findstring _cs_autoboot_, $@)" ] ; then \ - echo "#define CONFIG_CS_AUTOBOOT" >> $(obj)include/config.h ; \ - $(XECHO) "... configured for CS_AUTO boot"; \ + echo "#define CONFIG_CS_AUTOBOOT" >> ./include/config.h ; \ + echo "... configured for CS_AUTO boot"; \ else \ - echo "#define CONFIG_CS3_BOOT" >> $(obj)include/config.h ; \ - $(XECHO) "... configured for CS3 boot"; \ + echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \ + echo "... configured for CS3 boot"; \ fi; - @$(MKCONFIG) -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap + @./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap -omap5912osk_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap +omap1710h3_config : unconfig + @./mkconfig $(@:_config=) arm arm926ejs omap1710h3 -xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1))) +omapv1030gsample_config : unconfig + @./mkconfig $(@:_config=) arm arm926ejs omapv1030gsample omap730p2_config \ omap730p2_cs0boot_config \ omap730p2_cs3boot_config : unconfig - @mkdir -p $(obj)include @if [ "$(findstring _cs0boot_, $@)" ] ; then \ - echo "#define CONFIG_CS0_BOOT" >> $(obj)include/config.h ; \ - $(XECHO) "... configured for CS0 boot"; \ + echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \ + echo "... configured for CS0 boot"; \ else \ - echo "#define CONFIG_CS3_BOOT" >> $(obj)include/config.h ; \ - $(XECHO) "... configured for CS3 boot"; \ + echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \ + echo "... configured for CS3 boot"; \ fi; - @$(MKCONFIG) -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap + @./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2 NULL omap sbc2410x_config: unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 + @./mkconfig $(@:_config=) arm arm920t sbc2410x NULL s3c24x0 scb9328_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t scb9328 NULL imx + @./mkconfig $(@:_config=) arm arm920t scb9328 NULL imx smdk2400_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t smdk2400 NULL s3c24x0 + @./mkconfig $(@:_config=) arm arm920t smdk2400 NULL s3c24x0 smdk2410_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 NULL s3c24x0 + @./mkconfig $(@:_config=) arm arm920t smdk2410 NULL s3c24x0 SX1_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm925t sx1 + @./mkconfig $(@:_config=) arm arm925t sx1 # TRAB default configuration: 8 MB Flash, 32 MB RAM -xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1)))) - trab_config \ trab_bigram_config \ trab_bigflash_config \ trab_old_config: unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)board/trab + @ >include/config.h @[ -z "$(findstring _bigram,$@)" ] || \ - { echo "#define CONFIG_FLASH_8MB" >>$(obj)include/config.h ; \ - echo "#define CONFIG_RAM_32MB" >>$(obj)include/config.h ; \ - $(XECHO) "... with 8 MB Flash, 32 MB RAM" ; \ + { echo "#define CONFIG_FLASH_8MB" >>include/config.h ; \ + echo "#define CONFIG_RAM_32MB" >>include/config.h ; \ + echo "... with 8 MB Flash, 32 MB RAM" ; \ } @[ -z "$(findstring _bigflash,$@)" ] || \ - { echo "#define CONFIG_FLASH_16MB" >>$(obj)include/config.h ; \ - echo "#define CONFIG_RAM_16MB" >>$(obj)include/config.h ; \ - $(XECHO) "... with 16 MB Flash, 16 MB RAM" ; \ - echo "TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \ + { echo "#define CONFIG_FLASH_16MB" >>include/config.h ; \ + echo "#define CONFIG_RAM_16MB" >>include/config.h ; \ + echo "... with 16 MB Flash, 16 MB RAM" ; \ + echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \ } @[ -z "$(findstring _old,$@)" ] || \ - { echo "#define CONFIG_FLASH_8MB" >>$(obj)include/config.h ; \ - echo "#define CONFIG_RAM_16MB" >>$(obj)include/config.h ; \ - $(XECHO) "... with 8 MB Flash, 16 MB RAM" ; \ - echo "TEXT_BASE = 0x0CF40000" >$(obj)board/trab/config.tmp ; \ + { echo "#define CONFIG_FLASH_8MB" >>include/config.h ; \ + echo "#define CONFIG_RAM_16MB" >>include/config.h ; \ + echo "... with 8 MB Flash, 16 MB RAM" ; \ + echo "TEXT_BASE = 0x0CF40000" >board/trab/config.tmp ; \ } - @$(MKCONFIG) -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0 + @./mkconfig -a $(call xtract_trab,$@) arm arm920t trab NULL s3c24x0 VCMA9_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t vcma9 mpl s3c24x0 + @./mkconfig $(@:_config=) arm arm920t vcma9 mpl s3c24x0 -######################################################################### +#======================================================================== # ARM supplied Versatile development boards -######################################################################### - -cm4008_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t cm4008 NULL ks8695 - -cm41xx_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695 - +#======================================================================== versatile_config \ versatileab_config \ versatilepb_config : unconfig @board/versatile/split_by_variant.sh $@ +voiceblue_smallflash_config \ voiceblue_config: unconfig - @$(MKCONFIG) $(@:_config=) arm arm925t voiceblue + @if [ "$(findstring _smallflash_,$@)" ] ; then \ + echo "... boot from lower flash bank" ; \ + echo "#define VOICEBLUE_SMALL_FLASH" >>include/config.h ; \ + echo "VOICEBLUE_SMALL_FLASH=y" >board/voiceblue/config.tmp ; \ + else \ + echo "... boot from upper flash bank" ; \ + >include/config.h ; \ + echo "VOICEBLUE_SMALL_FLASH=n" >board/voiceblue/config.tmp ; \ + fi + @./mkconfig -a voiceblue arm arm925t voiceblue + +cm4008_config : unconfig + @./mkconfig $(@:_config=) arm arm920t cm4008 NULL ks8695 + +cm41xx_config : unconfig + @./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695 + +gth2_config : unconfig + @ >include/config.h + @echo "#define CONFIG_GTH2 1" >>include/config.h + @./mkconfig -a gth2 mips mips gth2 ######################################################################### ## S3C44B0 Systems ######################################################################### B2_config : unconfig - @$(MKCONFIG) $(@:_config=) arm s3c44b0 B2 dave + @./mkconfig $(@:_config=) arm s3c44b0 B2 dave ######################################################################### ## ARM720T Systems ######################################################################### armadillo_config: unconfig - @$(MKCONFIG) $(@:_config=) arm arm720t armadillo + @./mkconfig $(@:_config=) arm arm720t armadillo ep7312_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm720t ep7312 + @./mkconfig $(@:_config=) arm arm720t ep7312 impa7_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm720t impa7 + @./mkconfig $(@:_config=) arm arm720t impa7 modnet50_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm720t modnet50 + @./mkconfig $(@:_config=) arm arm720t modnet50 evb4510_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm720t evb4510 - -lpc2292sodimm_config: unconfig - @$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm NULL lpc2292 - -SMN42_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292 + @./mkconfig $(@:_config=) arm arm720t evb4510 ######################################################################### ## XScale Systems ######################################################################### -actux1_config : unconfig - @$(MKCONFIG) $(@:_config=) arm ixp actux1 - -actux2_config : unconfig - @$(MKCONFIG) $(@:_config=) arm ixp actux2 - -actux3_config : unconfig - @$(MKCONFIG) $(@:_config=) arm ixp actux3 - -actux4_config : unconfig - @$(MKCONFIG) $(@:_config=) arm ixp actux4 +adsvix_config : unconfig + @./mkconfig $(@:_config=) arm pxa adsvix cerf250_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa cerf250 + @./mkconfig $(@:_config=) arm pxa cerf250 cradle_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa cradle + @./mkconfig $(@:_config=) arm pxa cradle csb226_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa csb226 + @./mkconfig $(@:_config=) arm pxa csb226 -delta_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa delta +delta_config : + @./mkconfig $(@:_config=) arm pxa delta innokom_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa innokom + @./mkconfig $(@:_config=) arm pxa innokom ixdp425_config : unconfig - @$(MKCONFIG) $(@:_config=) arm ixp ixdp425 + @./mkconfig $(@:_config=) arm ixp ixdp425 ixdpg425_config : unconfig - @$(MKCONFIG) $(@:_config=) arm ixp ixdp425 + @./mkconfig $(@:_config=) arm ixp ixdp425 lubbock_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa lubbock + @./mkconfig $(@:_config=) arm pxa lubbock pleb2_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa pleb2 + @./mkconfig $(@:_config=) arm pxa pleb2 logodl_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa logodl + @./mkconfig $(@:_config=) arm pxa logodl -pdnb3_config \ -scpu_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring scpu_,$@)" ] ; then \ - echo "#define CONFIG_SCPU" >>$(obj)include/config.h ; \ - $(XECHO) "... on SCPU board variant" ; \ - fi - @$(MKCONFIG) -a pdnb3 arm ixp pdnb3 prodrive +pdnb3_config : unconfig + @./mkconfig $(@:_config=) arm ixp pdnb3 prodrive pxa255_idp_config: unconfig - @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp - -trizepsiv_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv + @./mkconfig $(@:_config=) arm pxa pxa255_idp wepep250_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa wepep250 + @./mkconfig $(@:_config=) arm pxa wepep250 xaeniax_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa xaeniax + @./mkconfig $(@:_config=) arm pxa xaeniax xm250_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa xm250 + @./mkconfig $(@:_config=) arm pxa xm250 xsengine_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa xsengine + @./mkconfig $(@:_config=) arm pxa xsengine zylonite_config : - @$(MKCONFIG) $(@:_config=) arm pxa zylonite + @./mkconfig $(@:_config=) arm pxa zylonite ######################################################################### ## ARM1136 Systems ######################################################################### +xtract_omap2430 = $(subst _gdp,,$(subst _config,,$1)) -apollon_config : unconfig - @mkdir -p $(obj)include - @mkdir -p $(obj)onenand_ipl/board/apollon - @echo "#define CONFIG_ONENAND_U_BOOT" > $(obj)include/config.h - @$(MKCONFIG) $(@:_config=) arm arm1136 apollon NULL omap24xx - @echo "CONFIG_ONENAND_U_BOOT = y" >> $(obj)include/config.mk +omap2420h4_config : unconfig + @./mkconfig $(@:_config=) arm arm1136 omap2420h4 -imx31_litekit_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31 +omap2430sdp_gdp_config \ +omap2430sdp_config : unconfig + @if [ "$(findstring _gdp_, $@)" ] ; then \ + echo "#define OMAP2430_SDP_GDP_CONFIG" >> ./include/config.h ; \ + echo "Configuring for GDP and .. "; \ + fi; + @./mkconfig -a $(call xtract_omap2430,$@) arm arm1136 omap2430sdp + +######################################################################### +## ARM CORTEX Systems +######################################################################### +omap3430sdp_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430sdp -imx31_phycore_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31 +omap3430labrador_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430labrador -mx31ads_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31 +omap3430zoom2_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3430zoom2 + +omap3630zoom3_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3630zoom3 + +omap3630zoom3_emmc_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3630zoom3 + echo "#define CONFIG_STORAGE_EMMC 1" > ./include/config-tmp.h; \ + cat ./include/config.h >> ./include/config-tmp.h; \ + mv ./include/config-tmp.h ./include/config.h; \ + sed -i -e 's/omap3630zoom3_emmc/omap3630zoom3/' ./include/config.h + + +omap3630sdp_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3630sdp + +omap3530overo_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3530overo + +omap3730overo_config : unconfig + @./mkconfig $(@:_config=) arm omap3 omap3730overo + +strasbourg_config \ +strasbourg-debug_config: unconfig + @./mkconfig $(@:_config=) arm omap3 strasbourg + +strasbourg_a2_config \ +strasbourg_a2-debug_config: unconfig + @./mkconfig $(@:_config=) arm omap3 strasbourg + +santiago_config \ +santiago-debug_config: unconfig + @./mkconfig $(@:_config=) arm omap3 santiago -omap2420h4_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx #======================================================================== # i386 @@ -2684,13 +1870,13 @@ omap2420h4_config : unconfig ## AMD SC520 CDP ######################################################################### sc520_cdp_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_cdp + @./mkconfig $(@:_config=) i386 i386 sc520_cdp sc520_spunk_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk + @./mkconfig $(@:_config=) i386 i386 sc520_spunk sc520_spunk_rel_config : unconfig - @$(MKCONFIG) $(@:_config=) i386 i386 sc520_spunk + @./mkconfig $(@:_config=) i386 i386 sc520_spunk #======================================================================== # MIPS @@ -2705,74 +1891,63 @@ incaip_100MHz_config \ incaip_133MHz_config \ incaip_150MHz_config \ incaip_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring _100MHz,$@)" ] || \ - { echo "#define CPU_CLOCK_RATE 100000000" >>$(obj)include/config.h ; \ - $(XECHO) "... with 100MHz system clock" ; \ + { echo "#define CPU_CLOCK_RATE 100000000" >>include/config.h ; \ + echo "... with 100MHz system clock" ; \ } @[ -z "$(findstring _133MHz,$@)" ] || \ - { echo "#define CPU_CLOCK_RATE 133000000" >>$(obj)include/config.h ; \ - $(XECHO) "... with 133MHz system clock" ; \ + { echo "#define CPU_CLOCK_RATE 133000000" >>include/config.h ; \ + echo "... with 133MHz system clock" ; \ } @[ -z "$(findstring _150MHz,$@)" ] || \ - { echo "#define CPU_CLOCK_RATE 150000000" >>$(obj)include/config.h ; \ - $(XECHO) "... with 150MHz system clock" ; \ + { echo "#define CPU_CLOCK_RATE 150000000" >>include/config.h ; \ + echo "... with 150MHz system clock" ; \ } - @$(MKCONFIG) -a $(call xtract_incaip,$@) mips mips incaip + @./mkconfig -a $(call xtract_incaip,$@) mips mips incaip tb0229_config: unconfig - @$(MKCONFIG) $(@:_config=) mips mips tb0229 + @./mkconfig $(@:_config=) mips mips tb0229 ######################################################################### ## MIPS32 AU1X00 ######################################################################### +dbau1000_config : unconfig + @ >include/config.h + @echo "#define CONFIG_DBAU1000 1" >>include/config.h + @./mkconfig -a dbau1x00 mips mips dbau1x00 -dbau1000_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_DBAU1000 1" >$(obj)include/config.h - @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 +dbau1100_config : unconfig + @ >include/config.h + @echo "#define CONFIG_DBAU1100 1" >>include/config.h + @./mkconfig -a dbau1x00 mips mips dbau1x00 -dbau1100_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_DBAU1100 1" >$(obj)include/config.h - @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 - -dbau1500_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_DBAU1500 1" >$(obj)include/config.h - @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 +dbau1500_config : unconfig + @ >include/config.h + @echo "#define CONFIG_DBAU1500 1" >>include/config.h + @./mkconfig -a dbau1x00 mips mips dbau1x00 dbau1550_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h - @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 + @ >include/config.h + @echo "#define CONFIG_DBAU1550 1" >>include/config.h + @./mkconfig -a dbau1x00 mips mips dbau1x00 dbau1550_el_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_DBAU1550 1" >$(obj)include/config.h - @$(MKCONFIG) -a dbau1x00 mips mips dbau1x00 + @ >include/config.h + @echo "#define CONFIG_DBAU1550 1" >>include/config.h + @./mkconfig -a dbau1x00 mips mips dbau1x00 -gth2_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_GTH2 1" >$(obj)include/config.h - @$(MKCONFIG) -a gth2 mips mips gth2 - -pb1000_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_PB1000 1" >$(obj)include/config.h - @$(MKCONFIG) -a pb1x00 mips mips pb1x00 - -qemu_mips_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h - @$(MKCONFIG) -a qemu-mips mips mips qemu-mips +pb1000_config : unconfig + @ >include/config.h + @echo "#define CONFIG_PB1000 1" >>include/config.h + @./mkconfig -a pb1x00 mips mips pb1x00 ######################################################################### ## MIPS64 5Kc ######################################################################### purple_config : unconfig - @$(MKCONFIG) $(@:_config=) mips mips purple + @./mkconfig $(@:_config=) mips mips purple #======================================================================== # Nios @@ -2781,278 +1956,149 @@ purple_config : unconfig ## Nios32 ######################################################################### -ADNPESC1_DNPEVA2_base_32_config \ -ADNPESC1_base_32_config \ -ADNPESC1_config: unconfig - @mkdir -p $(obj)include - @[ -z "$(findstring _DNPEVA2,$@)" ] || \ - { echo "#define CONFIG_DNPEVA2 1" >>$(obj)include/config.h ; \ - $(XECHO) "... DNP/EVA2 configuration" ; \ - } - @[ -z "$(findstring _base_32,$@)" ] || \ - { echo "#define CONFIG_NIOS_BASE_32 1" >>$(obj)include/config.h ; \ - $(XECHO) "... NIOS 'base_32' configuration" ; \ - } - @[ -z "$(findstring ADNPESC1_config,$@)" ] || \ - { echo "#define CONFIG_NIOS_BASE_32 1" >>$(obj)include/config.h ; \ - $(XECHO) "... NIOS 'base_32' configuration (DEFAULT)" ; \ - } - @$(MKCONFIG) -a ADNPESC1 nios nios adnpesc1 ssv - DK1C20_safe_32_config \ DK1C20_standard_32_config \ DK1C20_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring _safe_32,$@)" ] || \ - { echo "#define CONFIG_NIOS_SAFE_32 1" >>$(obj)include/config.h ; \ - $(XECHO) "... NIOS 'safe_32' configuration" ; \ + { echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \ + echo "... NIOS 'safe_32' configuration" ; \ } @[ -z "$(findstring _standard_32,$@)" ] || \ - { echo "#define CONFIG_NIOS_STANDARD_32 1" >>$(obj)include/config.h ; \ - $(XECHO) "... NIOS 'standard_32' configuration" ; \ + { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ + echo "... NIOS 'standard_32' configuration" ; \ } @[ -z "$(findstring DK1C20_config,$@)" ] || \ - { echo "#define CONFIG_NIOS_STANDARD_32 1" >>$(obj)include/config.h ; \ - $(XECHO) "... NIOS 'standard_32' configuration (DEFAULT)" ; \ + { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ + echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \ } - @$(MKCONFIG) -a DK1C20 nios nios dk1c20 altera + @./mkconfig -a DK1C20 nios nios dk1c20 altera DK1S10_safe_32_config \ DK1S10_standard_32_config \ DK1S10_mtx_ldk_20_config \ DK1S10_config: unconfig - @mkdir -p $(obj)include + @ >include/config.h @[ -z "$(findstring _safe_32,$@)" ] || \ - { echo "#define CONFIG_NIOS_SAFE_32 1" >>$(obj)include/config.h ; \ - $(XECHO) "... NIOS 'safe_32' configuration" ; \ + { echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \ + echo "... NIOS 'safe_32' configuration" ; \ } @[ -z "$(findstring _standard_32,$@)" ] || \ - { echo "#define CONFIG_NIOS_STANDARD_32 1" >>$(obj)include/config.h ; \ - $(XECHO) "... NIOS 'standard_32' configuration" ; \ + { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ + echo "... NIOS 'standard_32' configuration" ; \ } @[ -z "$(findstring _mtx_ldk_20,$@)" ] || \ - { echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>$(obj)include/config.h ; \ - $(XECHO) "... NIOS 'mtx_ldk_20' configuration" ; \ + { echo "#define CONFIG_NIOS_MTX_LDK_20 1" >>include/config.h ; \ + echo "... NIOS 'mtx_ldk_20' configuration" ; \ } @[ -z "$(findstring DK1S10_config,$@)" ] || \ - { echo "#define CONFIG_NIOS_STANDARD_32 1" >>$(obj)include/config.h ; \ - $(XECHO) "... NIOS 'standard_32' configuration (DEFAULT)" ; \ + { echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \ + echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \ } - @$(MKCONFIG) -a DK1S10 nios nios dk1s10 altera + @./mkconfig -a DK1S10 nios nios dk1s10 altera + +ADNPESC1_DNPEVA2_base_32_config \ +ADNPESC1_base_32_config \ +ADNPESC1_config: unconfig + @ >include/config.h + @[ -z "$(findstring _DNPEVA2,$@)" ] || \ + { echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \ + echo "... DNP/EVA2 configuration" ; \ + } + @[ -z "$(findstring _base_32,$@)" ] || \ + { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \ + echo "... NIOS 'base_32' configuration" ; \ + } + @[ -z "$(findstring ADNPESC1_config,$@)" ] || \ + { echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \ + echo "... NIOS 'base_32' configuration (DEFAULT)" ; \ + } + @./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv ######################################################################### ## Nios-II ######################################################################### EP1C20_config : unconfig - @$(MKCONFIG) EP1C20 nios2 nios2 ep1c20 altera + @./mkconfig EP1C20 nios2 nios2 ep1c20 altera EP1S10_config : unconfig - @$(MKCONFIG) EP1S10 nios2 nios2 ep1s10 altera + @./mkconfig EP1S10 nios2 nios2 ep1s10 altera EP1S40_config : unconfig - @$(MKCONFIG) EP1S40 nios2 nios2 ep1s40 altera + @./mkconfig EP1S40 nios2 nios2 ep1s40 altera PK1C20_config : unconfig - @$(MKCONFIG) PK1C20 nios2 nios2 pk1c20 psyent + @./mkconfig PK1C20 nios2 nios2 pk1c20 psyent PCI5441_config : unconfig - @$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent + @./mkconfig PCI5441 nios2 nios2 pci5441 psyent #======================================================================== +# MicroBlaze +#======================================================================== +######################################################################### ## Microblaze -#======================================================================== - -ml401_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_ML401 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) microblaze microblaze ml401 xilinx - +######################################################################### suzaku_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_SUZAKU 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno - -xupv2p_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_XUPV2P 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx - -#======================================================================== -# Blackfin -#======================================================================== - -# Analog Devices boards -BFIN_BOARDS = bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit - -$(BFIN_BOARDS:%=%_config) : unconfig - @$(MKCONFIG) $(@:_config=) blackfin blackfin $(@:_config=) - -$(BFIN_BOARDS): - $(MAKE) $@_config - $(MAKE) - -#======================================================================== -# AVR32 -#======================================================================== - -atngw100_config : unconfig - @$(MKCONFIG) $(@:_config=) avr32 at32ap atngw100 atmel at32ap700x - -atstk1002_config : unconfig - @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x - -atstk1003_config : unconfig - @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x - -atstk1004_config : unconfig - @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x - -atstk1006_config : unconfig - @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x - -#======================================================================== -# SH3 (SuperH) -#======================================================================== + @ >include/config.h + @echo "#define CONFIG_SUZAKU 1" >> include/config.h + @./mkconfig -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno ######################################################################### -## sh3 (Renesas SuperH) +## Blackfin ######################################################################### +ezkit533_config : unconfig + @./mkconfig $(@:_config=) blackfin bf533 ezkit533 -mpr2_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_MPR2 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh3 mpr2 +stamp_config : unconfig + @./mkconfig $(@:_config=) blackfin bf533 stamp -ms7720se_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_MS7720SE 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh3 ms7720se - -######################################################################### -## sh4 (Renesas SuperH) -######################################################################### - -MigoR_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h - @./mkconfig -a $(@:_config=) sh sh4 MigoR - -ms7750se_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_MS7750SE 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh4 ms7750se - -ms7722se_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh4 ms7722se - -r2dplus_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h - @./mkconfig -a $(@:_config=) sh sh4 r2dplus - -r7780mp_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h - @./mkconfig -a $(@:_config=) sh sh4 r7780mp - -sh7763rdp_config : unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h - @./mkconfig -a $(@:_config=) sh sh4 sh7763rdp - -#======================================================================== -# SPARC -#======================================================================== - -######################################################################### -## LEON3 -######################################################################### - -# Gaisler GR-XC3S-1500 board -gr_xc3s_1500_config : unconfig - @$(MKCONFIG) $(@:_config=) sparc leon3 gr_xc3s_1500 gaisler - -# Gaisler GR-CPCI-AX2000 board, a General purpose FPGA-AX system -gr_cpci_ax2000_config : unconfig - @$(MKCONFIG) $(@:_config=) sparc leon3 gr_cpci_ax2000 gaisler - -# Gaisler GRLIB template design (GPL SPARC/LEON3) for Altera NIOS -# Development board Stratix II edition, FPGA Device EP2S60. -gr_ep2s60_config: unconfig - @$(MKCONFIG) $(@:_config=) sparc leon3 gr_ep2s60 gaisler - -# Gaisler LEON3 GRSIM simulator -grsim_config : unconfig - @$(MKCONFIG) $(@:_config=) sparc leon3 grsim gaisler - -######################################################################### -## LEON2 -######################################################################### - -# Gaisler LEON2 GRSIM simulator -grsim_leon2_config : unconfig - @$(MKCONFIG) $(@:_config=) sparc leon2 grsim_leon2 gaisler +dspstamp_config : unconfig + @./mkconfig $(@:_config=) blackfin bf533 dsp_stamp ######################################################################### ######################################################################### ######################################################################### clean: - @rm -f $(obj)examples/82559_eeprom $(obj)examples/eepro100_eeprom \ - $(obj)examples/hello_world $(obj)examples/interrupt \ - $(obj)examples/mem_to_mem_idma2intr \ - $(obj)examples/sched $(obj)examples/smc91111_eeprom \ - $(obj)examples/test_burst $(obj)examples/timer - @rm -f $(obj)tools/bmp_logo $(obj)tools/easylogo/easylogo \ - $(obj)tools/env/{fw_printenv,fw_setenv} \ - $(obj)tools/envcrc \ - $(obj)tools/gdb/{astest,gdbcont,gdbsend} \ - $(obj)tools/gen_eth_addr $(obj)tools/img2srec \ - $(obj)tools/mkimage $(obj)tools/mpc86x_clk \ - $(obj)tools/ncb $(obj)tools/ubsha1 - @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \ - $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \ - $(obj)board/trab/trab_fkt $(obj)board/voiceblue/eeprom \ - $(obj)board/{integratorap,integratorcp}/u-boot.lds \ - $(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds \ - $(obj)cpu/blackfin/bootrom-asm-offsets.[chs] - @rm -f $(obj)include/bmp_logo.h - @rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map} - @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map} - @rm -f $(obj)api_examples/demo $(VERSION_FILE) - @find $(OBJTREE) -type f \ + find . -type f \ \( -name 'core' -o -name '*.bak' -o -name '*~' \ - -o -name '*.o' -o -name '*.a' \) -print \ + -o -name '*.o' -o -name '*.a' \) -print \ | xargs rm -f + rm -f examples/hello_world examples/timer \ + examples/eepro100_eeprom examples/sched \ + examples/mem_to_mem_idma2intr examples/82559_eeprom \ + examples/smc91111_eeprom \ + examples/test_burst + rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr + rm -f tools/mpc86x_clk tools/ncb + rm -f tools/easylogo/easylogo tools/bmp_logo + rm -f tools/gdb/astest tools/gdb/gdbcont tools/gdb/gdbsend + rm -f tools/env/fw_printenv tools/env/fw_setenv + rm -f board/cray/L1/bootscript.c board/cray/L1/bootscript.image + rm -f board/netstar/eeprom board/netstar/crcek + rm -f board/netstar/*.srec board/netstar/*.bin + rm -f board/strasbourg/*.image + rm -f board/santiago/*.image + rm -f board/trab/trab_fkt board/voiceblue/eeprom + rm -f board/integratorap/u-boot.lds board/integratorcp/u-boot.lds + rm -f include/bmp_logo.h clobber: clean - @find $(OBJTREE) -type f \( -name .depend \ + find . -type f \( -name .depend \ -o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \ -print0 \ | xargs -0 rm -f - @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \ - $(obj)cscope.* $(obj)*.*~ - @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) - @rm -f $(obj)tools/{crc32.c,environment.c,env/crc32.c,md5.c,sha1.c,inca-swap-bytes} - @rm -f $(obj)tools/{image.c,fdt.c,fdt_ro.c,fdt_rw.c,fdt_strerror.c,zlib.h} - @rm -f $(obj)tools/{fdt_wip.c,libfdt_internal.h} - @rm -f $(obj)cpu/mpc824x/bedbug_603e.c - @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm - @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f - @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -lname "*" -print | xargs rm -f - @[ ! -d $(obj)api_examples ] || find $(obj)api_examples -lname "*" -print | xargs rm -f + rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h + rm -fr *.*~ + rm -f u-boot u-boot.map u-boot.hex $(ALL) + rm -f tools/crc32.c tools/environment.c tools/env/crc32.c + rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c + rm -f include/asm/proc include/asm/arch include/asm -ifeq ($(OBJTREE),$(SRCTREE)) mrproper \ distclean: clobber unconfig -else -mrproper \ -distclean: clobber unconfig - rm -rf $(obj)* -endif backup: F=`basename $(TOPDIR)` ; cd .. ; \ diff --git a/README b/README index d4456e576..e772c1af0 100644 --- a/README +++ b/README @@ -1,5 +1,5 @@ # -# (C) Copyright 2000 - 2008 +# (C) Copyright 2000 - 2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -51,8 +51,7 @@ Makefile have been tested to some extent and can be considered "working". In fact, many of them are used in production systems. In case of problems see the CHANGELOG and CREDITS files to find out -who contributed the specific port. The MAINTAINERS file lists board -maintainers. +who contributed the specific port. Where to get help: @@ -66,22 +65,6 @@ before asking FAQ's. Please see http://lists.sourceforge.net/lists/listinfo/u-boot-users/ -Where to get source code: -========================= - -The U-Boot source code is maintained in the git repository at -git://www.denx.de/git/u-boot.git ; you can browse it online at -http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=summary - -The "snapshot" links on this page allow you to download tarballs of -any version you might be interested in. Official releases are also -available for FTP download from the ftp://ftp.denx.de/pub/u-boot/ -directory. - -Pre-built (and tested) images are available from -ftp://ftp.denx.de/pub/u-boot/images/ - - Where we come from: =================== @@ -94,11 +77,10 @@ Where we come from: * Provide extended interface to Linux boot loader * S-Record download * network boot - * PCMCIA / CompactFlash / ATA disk / SCSI ... boot + * PCMCIA / CompactFLash / ATA disk / SCSI ... boot - create ARMBoot project (http://sourceforge.net/projects/armboot) - add other CPU families (starting with ARM) - create U-Boot project (http://sourceforge.net/projects/u-boot) -- current project page: see http://www.denx.de/wiki/U-Boot Names and Spelling: @@ -150,16 +132,9 @@ Directory Hierarchy: - arm925t Files specific to ARM 925 CPUs - arm926ejs Files specific to ARM 926 CPUs - arm1136 Files specific to ARM 1136 CPUs - - at32ap Files specific to Atmel AVR32 AP CPUs - i386 Files specific to i386 CPUs - ixp Files specific to Intel XScale IXP CPUs - - leon2 Files specific to Gaisler LEON2 SPARC CPU - - leon3 Files specific to Gaisler LEON3 SPARC CPU - mcf52x2 Files specific to Freescale ColdFire MCF52x2 CPUs - - mcf5227x Files specific to Freescale ColdFire MCF5227x CPUs - - mcf532x Files specific to Freescale ColdFire MCF5329 CPUs - - mcf5445x Files specific to Freescale ColdFire MCF5445x CPUs - - mcf547x_8x Files specific to Freescale ColdFire MCF547x_8x CPUs - mips Files specific to MIPS CPUs - mpc5xx Files specific to Freescale MPC5xx CPUs - mpc5xxx Files specific to Freescale MPC5xxx CPUs @@ -181,15 +156,12 @@ Directory Hierarchy: - examples Example code for standalone applications, etc. - include Header Files - lib_arm Files generic to ARM architecture -- lib_avr32 Files generic to AVR32 architecture - lib_generic Files generic to all architectures - lib_i386 Files generic to i386 architecture - lib_m68k Files generic to m68k architecture - lib_mips Files generic to MIPS architecture - lib_nios Files generic to NIOS architecture - lib_ppc Files generic to PowerPC architecture -- lib_sparc Files generic to SPARC architecture -- libfdt Library files to support flattened device trees - net Networking code - post Power On Self Test - rtc Real Time Clock drivers @@ -230,7 +202,7 @@ Example: For a TQM823L module type: cd u-boot make TQM823L_config -For the Cogent platform, you need to specify the CPU type as well; +For the Cogent platform, you need to specify the cpu type as well; e.g. "make cogent_mpc8xx_config". And also configure the cogent directory according to the instructions in cogent/README. @@ -253,12 +225,106 @@ build a config tool - later. The following options need to be configured: -- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX. +- CPU Type: Define exactly one of -- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS. + PowerPC based CPUs: + ------------------- + CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860 + or CONFIG_MPC5xx + or CONFIG_MPC8220 + or CONFIG_MPC824X, CONFIG_MPC8260 + or CONFIG_MPC85xx + or CONFIG_IOP480 + or CONFIG_405GP + or CONFIG_405EP + or CONFIG_440 + or CONFIG_MPC74xx + or CONFIG_750FX + + ARM based CPUs: + --------------- + CONFIG_SA1110 + CONFIG_ARM7 + CONFIG_PXA250 + CONFIG_CPU_MONAHANS + + MicroBlaze based CPUs: + ---------------------- + CONFIG_MICROBLAZE + + Nios-2 based CPUs: + ---------------------- + CONFIG_NIOS2 + + +- Board Type: Define exactly one of + + PowerPC based boards: + --------------------- + + CONFIG_ADCIOP CONFIG_FPS860L CONFIG_OXC + CONFIG_ADS860 CONFIG_GEN860T CONFIG_PCI405 + CONFIG_AMX860 CONFIG_GENIETV CONFIG_PCIPPC2 + CONFIG_AP1000 CONFIG_GTH CONFIG_PCIPPC6 + CONFIG_AR405 CONFIG_gw8260 CONFIG_pcu_e + CONFIG_BAB7xx CONFIG_hermes CONFIG_PIP405 + CONFIG_BC3450 CONFIG_hymod CONFIG_PM826 + CONFIG_c2mon CONFIG_IAD210 CONFIG_ppmc8260 + CONFIG_CANBT CONFIG_ICU862 CONFIG_QS823 + CONFIG_CCM CONFIG_IP860 CONFIG_QS850 + CONFIG_CMI CONFIG_IPHASE4539 CONFIG_QS860T + CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RBC823 + CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXClassic + CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXlite + CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_RPXsuper + CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_rsdproto + CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_sacsng + CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8240 + CONFIG_CSB272 CONFIG_LANTEC CONFIG_Sandpoint8245 + CONFIG_CU824 CONFIG_LITE5200B CONFIG_sbc8260 + CONFIG_DASA_SIM CONFIG_lwmon CONFIG_sbc8560 + CONFIG_DB64360 CONFIG_MBX CONFIG_SM850 + CONFIG_DB64460 CONFIG_MBX860T CONFIG_SPD823TS + CONFIG_DU405 CONFIG_MHPC CONFIG_STXGP3 + CONFIG_DUET_ADS CONFIG_MIP405 CONFIG_SXNI855T + CONFIG_EBONY CONFIG_MOUSSE CONFIG_TQM823L + CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM8260 + CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM850L + CONFIG_ep8260 CONFIG_MPC8540EVAL CONFIG_TQM855L + CONFIG_ERIC CONFIG_MPC8560ADS CONFIG_TQM860L + CONFIG_ESTEEM192E CONFIG_MUSENKI CONFIG_TTTech + CONFIG_ETX094 CONFIG_MVS1 CONFIG_UTX8245 + CONFIG_EVB64260 CONFIG_NETPHONE CONFIG_V37 + CONFIG_FADS823 CONFIG_NETTA CONFIG_W7OLMC + CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMG + CONFIG_FADS860T CONFIG_NX823 CONFIG_WALNUT + CONFIG_FLAGADM CONFIG_OCRTC CONFIG_ZPC1900 + CONFIG_FPS850L CONFIG_ORSG CONFIG_ZUMA + + ARM based boards: + ----------------- + + CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250, + CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110, + CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, + CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, + CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400, + CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, + CONFIG_PLEB2, CONFIG_SHANNON, CONFIG_P2_OMAP730, + CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB, + CONFIG_VCMA9 + + MicroBlaze based boards: + ------------------------ + + CONFIG_SUZAKU + + Nios-2 based boards: + ------------------------ + + CONFIG_PCI5441 CONFIG_PK1C20 + CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40 -- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined) - Define exactly one, e.g. CONFIG_ATSTK1002 - CPU Module Type: (if CONFIG_COGENT is defined) Define exactly one of @@ -278,7 +344,7 @@ The following options need to be configured: - Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined) Define one or more of CONFIG_LCD_HEARTBEAT - update a character position on - the LCD display every second with + the lcd display every second with a "rotator" |\-/|\-/ - Board flavour: (if CONFIG_MPC8260ADS is defined) @@ -293,7 +359,7 @@ The following options need to be configured: Define exactly one of CONFIG_MPC8240, CONFIG_MPC8245 -- 8xx CPU Options: (if using an MPC8xx CPU) +- 8xx CPU Options: (if using an MPC8xx cpu) CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if get_gclk_freq() cannot work e.g. if there is no 32KHz @@ -341,44 +407,46 @@ The following options need to be configured: converts clock data to MHZ before passing it to the Linux kernel. When CONFIG_CLOCKS_IN_MHZ is defined, a definition of - "clocks_in_mhz=1" is automatically included in the + "clocks_in_mhz=1" is automatically included in the default environment. CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only] - When transferring memsize parameter to linux, some versions + When transfering memsize parameter to linux, some versions expect it to be in bytes, others in MB. Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes. - CONFIG_OF_LIBFDT + CONFIG_OF_FLAT_TREE New kernel versions are expecting firmware settings to be - passed using flattened device trees (based on open firmware - concepts). + passed using flat open firmware trees. + The environment variable "disable_of", when set, disables this + functionality. - CONFIG_OF_LIBFDT - * New libfdt-based support - * Adds the "fdt" command - * The bootm command automatically updates the fdt + CONFIG_OF_FLAT_TREE_MAX_SIZE + + The maximum size of the constructed OF tree. OF_CPU - The proper name of the cpus node. OF_SOC - The proper name of the soc node. OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device - boards with QUICC Engines require OF_QE to set UCC MAC - addresses + CONFIG_OF_HAS_BD_T + + The resulting flat device tree will have a copy of the bd_t. + Space should be pre-allocated in the dts for the bd_t. + + CONFIG_OF_HAS_UBOOT_ENV + + The resulting flat device tree will have a copy of u-boot's + environment variables CONFIG_OF_BOARD_SETUP Board code has addition modification that it wants to make to the flat device tree before handing it off to the kernel - CONFIG_OF_BOOT_CPU - - This define fills in the correct boot CPU in the boot - param header, the default value is zero if undefined. - - Serial Ports: CFG_PL010_SERIAL @@ -439,14 +507,14 @@ The following options need to be configured: CFG_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c) CONFIG_CONSOLE_TIME display time/date info in upper right corner - (requires CONFIG_CMD_DATE) + (requires CFG_CMD_DATE) CONFIG_VIDEO_LOGO display Linux logo in upper left corner CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of linux_logo.h for logo. Requires CONFIG_VIDEO_LOGO CONFIG_CONSOLE_EXTRA_INFO - additional board info beside + addional board info beside the logo When CONFIG_CFB_CONSOLE is defined, video console is @@ -516,7 +584,7 @@ The following options need to be configured: The value of these goes into the environment as "ramboot" and "nfsboot" respectively, and can be used as a convenience, when switching between booting from - RAM and NFS. + ram and nfs. - Pre-Boot Commands: CONFIG_PREBOOT @@ -543,95 +611,100 @@ The following options need to be configured: time on others. This setting #define's the initial value of the "loads_echo" environment variable. -- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined) +- Kgdb Serial Baudrate: (if CFG_CMD_KGDB is defined) CONFIG_KGDB_BAUDRATE Select one of the baudrates listed in CFG_BAUDRATE_TABLE, see below. - Monitor Functions: - Monitor commands can be included or excluded - from the build by using the #include files - "config_cmd_all.h" and #undef'ing unwanted - commands, or using "config_cmd_default.h" - and augmenting with additional #define's - for wanted commands. + CONFIG_COMMANDS + Most monitor functions can be selected (or + de-selected) by adjusting the definition of + CONFIG_COMMANDS; to select individual functions, + #define CONFIG_COMMANDS by "OR"ing any of the + following values: - The default command configuration includes all commands - except those marked below with a "*". + #define enables commands: + ------------------------- + CFG_CMD_ASKENV * ask for env variable + CFG_CMD_AUTOSCRIPT Autoscript Support + CFG_CMD_BDI bdinfo + CFG_CMD_BEDBUG * Include BedBug Debugger + CFG_CMD_BMP * BMP support + CFG_CMD_BSP * Board specific commands + CFG_CMD_BOOTD bootd + CFG_CMD_CACHE * icache, dcache + CFG_CMD_CONSOLE coninfo + CFG_CMD_DATE * support for RTC, date/time... + CFG_CMD_DHCP * DHCP support + CFG_CMD_DIAG * Diagnostics + CFG_CMD_DOC * Disk-On-Chip Support + CFG_CMD_DTT * Digital Therm and Thermostat + CFG_CMD_ECHO echo arguments + CFG_CMD_EEPROM * EEPROM read/write support + CFG_CMD_ELF * bootelf, bootvx + CFG_CMD_ENV saveenv + CFG_CMD_FDC * Floppy Disk Support + CFG_CMD_FAT * FAT partition support + CFG_CMD_FDOS * Dos diskette Support + CFG_CMD_FLASH flinfo, erase, protect + CFG_CMD_FPGA FPGA device initialization support + CFG_CMD_HWFLOW * RTS/CTS hw flow control + CFG_CMD_I2C * I2C serial bus support + CFG_CMD_IDE * IDE harddisk support + CFG_CMD_IMI iminfo + CFG_CMD_IMLS List all found images + CFG_CMD_IMMAP * IMMR dump support + CFG_CMD_IRQ * irqinfo + CFG_CMD_ITEST Integer/string test of 2 values + CFG_CMD_JFFS2 * JFFS2 Support + CFG_CMD_KGDB * kgdb + CFG_CMD_LOADB loadb + CFG_CMD_LOADS loads + CFG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, + loop, loopw, mtest + CFG_CMD_MISC Misc functions like sleep etc + CFG_CMD_MMC * MMC memory mapped support + CFG_CMD_MII * MII utility commands + CFG_CMD_NAND * NAND support + CFG_CMD_NET bootp, tftpboot, rarpboot + CFG_CMD_PCI * pciinfo + CFG_CMD_PCMCIA * PCMCIA support + CFG_CMD_PING * send ICMP ECHO_REQUEST to network host + CFG_CMD_PORTIO * Port I/O + CFG_CMD_REGINFO * Register dump + CFG_CMD_RUN run command in env variable + CFG_CMD_SAVES * save S record dump + CFG_CMD_SCSI * SCSI Support + CFG_CMD_SDRAM * print SDRAM configuration information + (requires CFG_CMD_I2C) + CFG_CMD_SETGETDCR Support for DCR Register access (4xx only) + CFG_CMD_SPI * SPI serial bus support + CFG_CMD_USB * USB support + CFG_CMD_VFD * VFD support (TRAB) + CFG_CMD_BSP * Board SPecific functions + CFG_CMD_CDP * Cisco Discover Protocol support + ----------------------------------------------- + CFG_CMD_ALL all - CONFIG_CMD_ASKENV * ask for env variable - CONFIG_CMD_AUTOSCRIPT Autoscript Support - CONFIG_CMD_BDI bdinfo - CONFIG_CMD_BEDBUG * Include BedBug Debugger - CONFIG_CMD_BMP * BMP support - CONFIG_CMD_BSP * Board specific commands - CONFIG_CMD_BOOTD bootd - CONFIG_CMD_CACHE * icache, dcache - CONFIG_CMD_CONSOLE coninfo - CONFIG_CMD_DATE * support for RTC, date/time... - CONFIG_CMD_DHCP * DHCP support - CONFIG_CMD_DIAG * Diagnostics - CONFIG_CMD_DOC * Disk-On-Chip Support - CONFIG_CMD_DTT * Digital Therm and Thermostat - CONFIG_CMD_ECHO echo arguments - CONFIG_CMD_EEPROM * EEPROM read/write support - CONFIG_CMD_ELF * bootelf, bootvx - CONFIG_CMD_ENV saveenv - CONFIG_CMD_FDC * Floppy Disk Support - CONFIG_CMD_FAT * FAT partition support - CONFIG_CMD_FDOS * Dos diskette Support - CONFIG_CMD_FLASH flinfo, erase, protect - CONFIG_CMD_FPGA FPGA device initialization support - CONFIG_CMD_HWFLOW * RTS/CTS hw flow control - CONFIG_CMD_I2C * I2C serial bus support - CONFIG_CMD_IDE * IDE harddisk support - CONFIG_CMD_IMI iminfo - CONFIG_CMD_IMLS List all found images - CONFIG_CMD_IMMAP * IMMR dump support - CONFIG_CMD_IRQ * irqinfo - CONFIG_CMD_ITEST Integer/string test of 2 values - CONFIG_CMD_JFFS2 * JFFS2 Support - CONFIG_CMD_KGDB * kgdb - CONFIG_CMD_LOADB loadb - CONFIG_CMD_LOADS loads - CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, - loop, loopw, mtest - CONFIG_CMD_MISC Misc functions like sleep etc - CONFIG_CMD_MMC * MMC memory mapped support - CONFIG_CMD_MII * MII utility commands - CONFIG_CMD_NAND * NAND support - CONFIG_CMD_NET bootp, tftpboot, rarpboot - CONFIG_CMD_PCI * pciinfo - CONFIG_CMD_PCMCIA * PCMCIA support - CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network - host - CONFIG_CMD_PORTIO * Port I/O - CONFIG_CMD_REGINFO * Register dump - CONFIG_CMD_RUN run command in env variable - CONFIG_CMD_SAVES * save S record dump - CONFIG_CMD_SCSI * SCSI Support - CONFIG_CMD_SDRAM * print SDRAM configuration information - (requires CONFIG_CMD_I2C) - CONFIG_CMD_SETGETDCR Support for DCR Register access - (4xx only) - CONFIG_CMD_SPI * SPI serial bus support - CONFIG_CMD_USB * USB support - CONFIG_CMD_VFD * VFD support (TRAB) - CONFIG_CMD_CDP * Cisco Discover Protocol support - CONFIG_CMD_FSL * Microblaze FSL support + CONFIG_CMD_DFL Default configuration; at the moment + this is includes all commands, except + the ones marked with "*" in the list + above. + If you don't define CONFIG_COMMANDS it defaults to + CONFIG_CMD_DFL in include/cmd_confdefs.h. A board can + override the default settings in the respective + include file. EXAMPLE: If you want all functions except of network support you can write: - #include "config_cmd_all.h" - #undef CONFIG_CMD_NET + #define CONFIG_COMMANDS (CFG_CMD_ALL & ~CFG_CMD_NET) - Other Commands: - fdt (flattened device tree) command: CONFIG_OF_LIBFDT Note: Don't enable the "icache" and "dcache" commands - (configuration option CONFIG_CMD_CACHE) unless you know + (configuration option CFG_CMD_CACHE) unless you know what you (and your U-Boot users) are doing. Data cache cannot be enabled on systems like the 8xx or 8260 (where accesses to the IMMR region must be @@ -659,21 +732,18 @@ The following options need to be configured: - Real-Time Clock: - When CONFIG_CMD_DATE is selected, the type of the RTC + When CFG_CMD_DATE is selected, the type of the RTC has to be selected, too. Define exactly one of the following options: CONFIG_RTC_MPC8xx - use internal RTC of MPC8xx CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC - CONFIG_RTC_MC13783 - use MC13783 RTC CONFIG_RTC_MC146818 - use MC146818 RTC CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC CONFIG_RTC_DS164x - use Dallas DS164x RTC - CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC - CFG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 Note that if the RTC uses I2C, then the I2C interface must also be configured. See I2C Support, below. @@ -683,15 +753,15 @@ The following options need to be configured: When CONFIG_TIMESTAMP is selected, the timestamp (date and time) of an image is printed by image commands like bootm or iminfo. This option is - automatically enabled when you select CONFIG_CMD_DATE . + automatically enabled when you select CFG_CMD_DATE . - Partition Support: CONFIG_MAC_PARTITION and/or CONFIG_DOS_PARTITION and/or CONFIG_ISO_PARTITION - If IDE or SCSI support is enabled (CONFIG_CMD_IDE or - CONFIG_CMD_SCSI) you must configure support for at - least one partition type as well. + If IDE or SCSI support is enabled (CFG_CMD_IDE or + CFG_CMD_SCSI) you must configure support for at least + one partition type as well. - IDE Reset method: CONFIG_IDE_RESET_ROUTINE - this is defined in several @@ -735,12 +805,9 @@ The following options need to be configured: CONFIG_E1000 Support for Intel 8254x gigabit chips. - CONFIG_E1000_FALLBACK_MAC - default MAC for empty EEPROM after production. - CONFIG_EEPRO100 Support for Intel 82557/82559/82559ER chips. - Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM + Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom write routine for first time initialisation. CONFIG_TULIP @@ -780,21 +847,6 @@ The following options need to be configured: Define this to use i/o functions instead of macros (some hardware wont work with macros) - CONFIG_DRIVER_SMC911X - Support for SMSC's LAN911x and LAN921x chips - - CONFIG_DRIVER_SMC911X_BASE - Define this to hold the physical address - of the device (I/O space) - - CONFIG_DRIVER_SMC911X_32_BIT - Define this if data bus is 32 bits - - CONFIG_DRIVER_SMC911X_16_BIT - Define this if data bus is 16 bits. If your processor - automatically converts one 32 bit word to two 16 bit - words you may also try CONFIG_DRIVER_SMC911X_32_BIT. - - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define @@ -811,71 +863,6 @@ The following options need to be configured: CONFIG_USB_CONFIG for differential drivers: 0x00001000 for single ended drivers: 0x00005000 - CFG_USB_EVENT_POLL - May be defined to allow interrupt polling - instead of using asynchronous interrupts - -- USB Device: - Define the below if you wish to use the USB console. - Once firmware is rebuilt from a serial console issue the - command "setenv stdin usbtty; setenv stdout usbtty" and - attach your USB cable. The Unix command "dmesg" should print - it has found a new device. The environment variable usbtty - can be set to gserial or cdc_acm to enable your device to - appear to a USB host as a Linux gserial device or a - Common Device Class Abstract Control Model serial device. - If you select usbtty = gserial you should be able to enumerate - a Linux host by - # modprobe usbserial vendor=0xVendorID product=0xProductID - else if using cdc_acm, simply setting the environment - variable usbtty to be cdc_acm should suffice. The following - might be defined in YourBoardName.h - - CONFIG_USB_DEVICE - Define this to build a UDC device - - CONFIG_USB_TTY - Define this to have a tty type of device available to - talk to the UDC device - - CFG_CONSOLE_IS_IN_ENV - Define this if you want stdin, stdout &/or stderr to - be set to usbtty. - - mpc8xx: - CFG_USB_EXTC_CLK 0xBLAH - Derive USB clock from external clock "blah" - - CFG_USB_EXTC_CLK 0x02 - - CFG_USB_BRG_CLK 0xBLAH - Derive USB clock from brgclk - - CFG_USB_BRG_CLK 0x04 - - If you have a USB-IF assigned VendorID then you may wish to - define your own vendor specific values either in BoardName.h - or directly in usbd_vendor_info.h. If you don't define - CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME, - CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot - should pretend to be a Linux device to it's target host. - - CONFIG_USBD_MANUFACTURER - Define this string as the name of your company for - - CONFIG_USBD_MANUFACTURER "my company" - - CONFIG_USBD_PRODUCT_NAME - Define this string as the name of your product - - CONFIG_USBD_PRODUCT_NAME "acme usb device" - - CONFIG_USBD_VENDORID - Define this as your assigned Vendor ID from the USB - Implementors Forum. This *must* be a genuine Vendor ID - to avoid polluting the USB namespace. - - CONFIG_USBD_VENDORID 0xFFFF - - CONFIG_USBD_PRODUCTID - Define this as the unique Product ID - for your device - - CONFIG_USBD_PRODUCTID 0xFFFF - MMC Support: @@ -883,8 +870,8 @@ The following options need to be configured: enable this define CONFIG_MMC. The MMC can be accessed from the boot prompt by mapping the device to physical memory similar to flash. Command line is - enabled with CONFIG_CMD_MMC. The MMC driver also works with - the FAT fs. This is enabled with CONFIG_CMD_FAT. + enabled with CFG_CMD_MMC. The MMC driver also works with + the FAT fs. This is enabled with CFG_CMD_FAT. - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, @@ -933,7 +920,7 @@ The following options need to be configured: assumed. For the CT69000 and SMI_LYNXEM drivers, videomode is - selected via environment 'videomode'. Two different ways + selected via environment 'videomode'. Two diferent ways are possible: - "videomode=num" 'num' is a standard LiLo mode numbers. Following standard modes are supported (* is default): @@ -948,7 +935,7 @@ The following options need to be configured: (i.e. setenv videomode 317; saveenv; reset;) - "videomode=bootargs" all the video parameters are parsed - from the bootargs. (See drivers/video/videomodes.c) + from the bootargs. (See drivers/videomodes.c) CONFIG_VIDEO_SED13806 @@ -970,10 +957,6 @@ The following options need to be configured: display); also select one of the supported displays by defining one of these: - CONFIG_ATMEL_LCD: - - HITACHI TX09D70VM1CCA, 3.5", 240x320. - CONFIG_NEC_NL6448AC33: NEC NL6448AC33-18. Active, color, single scan. @@ -1056,7 +1039,7 @@ The following options need to be configured: CONFIG_PHY_GIGE If this option is set, support for speed/duplex - detection of gigabit PHY is included. + detection of Gigabit PHY is included. CONFIG_PHY_RESET_DELAY @@ -1075,33 +1058,23 @@ The following options need to be configured: CONFIG_ETH2ADDR CONFIG_ETH3ADDR - Define a default value for Ethernet address to use - for the respective Ethernet interface, in case this + Define a default value for ethernet address to use + for the respective ethernet interface, in case this is not determined automatically. - IP address: CONFIG_IPADDR Define a default value for the IP address to use for - the default Ethernet interface, in case this is not + the default ethernet interface, in case this is not determined through e.g. bootp. - Server IP address: CONFIG_SERVERIP - Defines a default value for the IP address of a TFTP + Defines a default value for theIP address of a TFTP server to contact when using the "tftboot" command. -- Multicast TFTP Mode: - CONFIG_MCAST_TFTP - - Defines whether you want to support multicast TFTP as per - rfc-2090; for example to work with atftp. Lets lots of targets - tftp down the same boot image concurrently. Note: the Ethernet - driver in use must provide a function: mcast() to join/leave a - multicast group. - - CONFIG_BOOTP_RANDOM_DELAY - BOOTP Recovery Mode: CONFIG_BOOTP_RANDOM_DELAY @@ -1113,7 +1086,7 @@ The following options need to be configured: boot, thus flooding the BOOTP server. Defining CONFIG_BOOTP_RANDOM_DELAY causes a random delay to be inserted before sending out BOOTP requests. The - following delays are inserted then: + following delays are insterted then: 1st BOOTP request: delay 0 ... 1 sec 2nd BOOTP request: delay 0 ... 2 sec @@ -1122,24 +1095,10 @@ The following options need to be configured: BOOTP requests: delay 0 ... 8 sec - DHCP Advanced Options: - You can fine tune the DHCP functionality by defining - CONFIG_BOOTP_* symbols: + CONFIG_BOOTP_MASK - CONFIG_BOOTP_SUBNETMASK - CONFIG_BOOTP_GATEWAY - CONFIG_BOOTP_HOSTNAME - CONFIG_BOOTP_NISDOMAIN - CONFIG_BOOTP_BOOTPATH - CONFIG_BOOTP_BOOTFILESIZE - CONFIG_BOOTP_DNS - CONFIG_BOOTP_DNS2 - CONFIG_BOOTP_SEND_HOSTNAME - CONFIG_BOOTP_NTPSERVER - CONFIG_BOOTP_TIMEOFFSET - CONFIG_BOOTP_VENDOREX - - CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip - environment variable, not the BOOTP server. + You can fine tune the DHCP functionality by adding + these flags to the CONFIG_BOOTP_MASK define: CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS serverip from a DHCP server, it is possible that more @@ -1148,28 +1107,15 @@ The following options need to be configured: serverip will be stored in the additional environment variable "dnsip2". The first DNS serverip is always stored in the variable "dnsip", when CONFIG_BOOTP_DNS - is defined. + is added to the CONFIG_BOOTP_MASK. CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable to do a dynamic update of a DNS server. To do this, they need the hostname of the DHCP requester. - If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content - of the "hostname" environment variable is passed as - option 12 to the DHCP server. - - CONFIG_BOOTP_DHCP_REQUEST_DELAY - - A 32bit value in microseconds for a delay between - receiving a "DHCP Offer" and sending the "DHCP Request". - This fixes a problem with certain DHCP servers that don't - respond 100% of the time to a "DHCP request". E.g. On an - AT91RM9200 processor running at 180MHz, this delay needed - to be *at least* 15,000 usec before a Windows Server 2003 - DHCP server would reply 100% of the time. I recommend at - least 50,000 usec to be safe. The alternative is to hope - that one of the retries will be successful but note that - the DHCP timeout and retry process takes a longer than - this delay. + If CONFIG_BOOP_SEND_HOSTNAME is added to the + CONFIG_BOOTP_MASK, the content of the "hostname" + environment variable is passed as option 12 to + the DHCP server. - CDP Options: CONFIG_CDP_DEVICE_ID @@ -1185,7 +1131,7 @@ The following options need to be configured: A printf format string which contains the ascii name of the port. Normally is set to "eth%d" which sets - eth0 for the first Ethernet, eth1 for the second etc. + eth0 for the first ethernet, eth1 for the second etc. CONFIG_CDP_CAPABILITIES @@ -1234,20 +1180,15 @@ The following options need to be configured: These enable I2C serial bus commands. Defining either of (but not both of) CONFIG_HARD_I2C or CONFIG_SOFT_I2C will - include the appropriate I2C driver for the selected CPU. + include the appropriate I2C driver for the selected cpu. This will allow you to use i2c commands at the u-boot - command line (as long as you set CONFIG_CMD_I2C in + command line (as long as you set CFG_CMD_I2C in CONFIG_COMMANDS) and communicate with i2c based realtime clock chips. See common/cmd_i2c.c for a description of the command line interface. - CONFIG_I2C_CMD_TREE is a recommended option that places - all I2C commands under a single 'i2c' root command. The - older 'imm', 'imd', 'iprobe' etc. commands are considered - deprecated and may disappear in the future. - - CONFIG_HARD_I2C selects a hardware I2C controller. + CONFIG_HARD_I2C selects the CPM hardware driver for I2C. CONFIG_SOFT_I2C configures u-boot to use a software (aka bit-banging) driver instead of CPM or similar hardware @@ -1259,10 +1200,10 @@ The following options need to be configured: In both cases you will need to define CFG_I2C_SPEED to be the frequency (in Hz) at which you wish your i2c bus to run and CFG_I2C_SLAVE to be the address of this node (ie - the CPU's i2c node address). + the cpu's i2c node address). Now, the u-boot i2c code for the mpc8xx (cpu/mpc8xx/i2c.c) - sets the CPU up as a master node and so its address should + sets the cpu up as a master node and so its address should therefore be cleared to 0 (See, eg, MPC823e User's Manual p.16-473). So, set CFG_I2C_SLAVE to 0. @@ -1352,52 +1293,6 @@ The following options need to be configured: in u-boot bd_info structure based on u-boot environment variable "i2cfast". (see also i2cfast) - CONFIG_I2C_MULTI_BUS - - This option allows the use of multiple I2C buses, each of which - must have a controller. At any point in time, only one bus is - active. To switch to a different bus, use the 'i2c dev' command. - Note that bus numbering is zero-based. - - CFG_I2C_NOPROBES - - This option specifies a list of I2C devices that will be skipped - when the 'i2c probe' command is issued (or 'iprobe' using the legacy - command). If CONFIG_I2C_MULTI_BUS is set, specify a list of bus-device - pairs. Otherwise, specify a 1D array of device addresses - - e.g. - #undef CONFIG_I2C_MULTI_BUS - #define CFG_I2C_NOPROBES {0x50,0x68} - - will skip addresses 0x50 and 0x68 on a board with one I2C bus - - #define CONFIG_I2C_MULTI_BUS - #define CFG_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} - - will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 - - CFG_SPD_BUS_NUM - - If defined, then this indicates the I2C bus number for DDR SPD. - If not defined, then U-Boot assumes that SPD is on I2C bus 0. - - CFG_RTC_BUS_NUM - - If defined, then this indicates the I2C bus number for the RTC. - If not defined, then U-Boot assumes that RTC is on I2C bus 0. - - CFG_DTT_BUS_NUM - - If defined, then this indicates the I2C bus number for the DTT. - If not defined, then U-Boot assumes that DTT is on I2C bus 0. - - CONFIG_FSL_I2C - - Define this option if you want to use Freescale's I2C driver in - drivers/i2c/fsl_i2c.c. - - - SPI Support: CONFIG_SPI Enables SPI driver (so far only tested with @@ -1419,37 +1314,15 @@ The following options need to be configured: SPI configuration items (port pins to use, etc). For an example, see include/configs/sacsng.h. - CONFIG_HARD_SPI - - Enables a hardware SPI driver for general-purpose reads - and writes. As with CONFIG_SOFT_SPI, the board configuration - must define a list of chip-select function pointers. - Currently supported on some MPC8xxx processors. For an - example, see include/configs/mpc8349emds.h. - - CONFIG_MXC_SPI - - Enables the driver for the SPI controllers on i.MX and MXC - SoCs. Currently only i.MX31 is supported. - -- FPGA Support: CONFIG_FPGA - - Enables FPGA subsystem. - - CONFIG_FPGA_ - - Enables support for specific chip vendors. - (ALTERA, XILINX) - - CONFIG_FPGA_ - - Enables support for FPGA family. - (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX) - - CONFIG_FPGA_COUNT +- FPGA Support: CONFIG_FPGA_COUNT Specify the number of FPGA devices to support. + CONFIG_FPGA + + Used to specify the types of FPGA devices. For example, + #define CONFIG_FPGA CFG_XILINX_VIRTEX2 + CFG_FPGA_PROG_FEEDBACK Enable printing of hash marks during FPGA configuration. @@ -1481,17 +1354,17 @@ The following options need to be configured: Maximum time to wait for the INIT_B line to deassert after PROB_B has been deasserted during a Virtex II FPGA configuration sequence. The default time is 500 - ms. + mS. CFG_FPGA_WAIT_BUSY Maximum time to wait for BUSY to deassert during - Virtex II FPGA configuration. The default is 5 ms. + Virtex II FPGA configuration. The default is 5 mS. CFG_FPGA_WAIT_CONFIG Time to wait after FPGA configuration. The default is - 200 ms. + 200 mS. - Configuration Management: CONFIG_IDENT_STRING @@ -1508,7 +1381,7 @@ The following options need to be configured: protects these variables from casual modification by the user. Once set, these variables are read-only, and write or delete attempts are rejected. You can - change this behaviour: + change this behviour: If CONFIG_ENV_OVERWRITE is #defined in your config file, the write protection for vendor parameters is @@ -1517,7 +1390,7 @@ The following options need to be configured: Alternatively, if you #define _both_ CONFIG_ETHADDR _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default - Ethernet address is installed in the environment, + ethernet address is installed in the environment, which can be changed exactly ONCE by the user. [The serial# is unaffected by this, i. e. it remains read-only.] @@ -1561,7 +1434,7 @@ The following options need to be configured: Define this variable to stop the system in case of a fatal error, so that you have to reset it manually. This is probably NOT a good idea for an embedded - system where you want the system to reboot + system where you want to system to reboot automatically as fast as possible, but it may be useful during development since you can try to debug the conditions that lead to the situation. @@ -1573,19 +1446,11 @@ The following options need to be configured: before giving up the operation. If not defined, a default value of 5 is used. - CONFIG_ARP_TIMEOUT - - Timeout waiting for an ARP reply in milliseconds. - - Command Interpreter: - CONFIG_AUTO_COMPLETE + CFG_AUTO_COMPLETE Enable auto completion of commands using TAB. - Note that this feature has NOT been implemented yet - for the "hush" shell. - - CFG_HUSH_PARSER Define this variable to enable the "hush" shell (from @@ -1628,7 +1493,7 @@ The following options need to be configured: - Commandline Editing and History: CONFIG_CMDLINE_EDITING - Enable editing and History functions for interactive + Enable editiong and History functions for interactive commandline input operations - Default Environment: @@ -1669,7 +1534,7 @@ The following options need to be configured: Adding this option adds support for Xilinx SystemACE chips attached via some sort of local bus. The address - of the chip must also be defined in the + of the chip must alsh be defined in the CFG_SYSTEMACE_BASE macro. For example: #define CONFIG_SYSTEMACE @@ -1708,8 +1573,6 @@ The following options need to be configured: example, some LED's) on your board. At the moment, the following checkpoints are implemented: -Legacy uImage format: - Arg Where When 1 common/cmd_bootm.c before attempting to boot an image -1 common/cmd_bootm.c Image header has bad magic number @@ -1720,146 +1583,51 @@ Legacy uImage format: 4 common/cmd_bootm.c Image data has correct checksum -4 common/cmd_bootm.c Image is for unsupported architecture 5 common/cmd_bootm.c Architecture check OK - -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi) + -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi, standalone) 6 common/cmd_bootm.c Image Type check OK -6 common/cmd_bootm.c gunzip uncompression error -7 common/cmd_bootm.c Unimplemented compression type 7 common/cmd_bootm.c Uncompression OK - 8 common/cmd_bootm.c No uncompress/copy overwrite error + -8 common/cmd_bootm.c Wrong Image Type (not kernel, multi, standalone) + 8 common/cmd_bootm.c Image Type check OK -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX) - - 9 common/image.c Start initial ramdisk verification - -10 common/image.c Ramdisk header has bad magic number - -11 common/image.c Ramdisk header has bad checksum - 10 common/image.c Ramdisk header is OK - -12 common/image.c Ramdisk data has bad checksum - 11 common/image.c Ramdisk data has correct checksum - 12 common/image.c Ramdisk verification complete, start loading - -13 common/image.c Wrong Image Type (not PPC Linux ramdisk) - 13 common/image.c Start multifile image verification - 14 common/image.c No initial ramdisk, no multifile, continue. - - 15 lib_/bootm.c All preparation done, transferring control to OS + 9 common/cmd_bootm.c Start initial ramdisk verification + -10 common/cmd_bootm.c Ramdisk header has bad magic number + -11 common/cmd_bootm.c Ramdisk header has bad checksum + 10 common/cmd_bootm.c Ramdisk header is OK + -12 common/cmd_bootm.c Ramdisk data has bad checksum + 11 common/cmd_bootm.c Ramdisk data has correct checksum + 12 common/cmd_bootm.c Ramdisk verification complete, start loading + -13 common/cmd_bootm.c Wrong Image Type (not PPC Linux Ramdisk) + 13 common/cmd_bootm.c Start multifile image verification + 14 common/cmd_bootm.c No initial ramdisk, no multifile, continue. + 15 common/cmd_bootm.c All preparation done, transferring control to OS -30 lib_ppc/board.c Fatal error, hang the system -31 post/post.c POST test failed, detected by post_output_backlog() -32 post/post.c POST test failed, detected by post_run_single() - 34 common/cmd_doc.c before loading a Image from a DOC device - -35 common/cmd_doc.c Bad usage of "doc" command - 35 common/cmd_doc.c correct usage of "doc" command - -36 common/cmd_doc.c No boot device - 36 common/cmd_doc.c correct boot device - -37 common/cmd_doc.c Unknown Chip ID on boot device - 37 common/cmd_doc.c correct chip ID found, device available - -38 common/cmd_doc.c Read Error on boot device - 38 common/cmd_doc.c reading Image header from DOC device OK - -39 common/cmd_doc.c Image header has bad magic number - 39 common/cmd_doc.c Image header has correct magic number - -40 common/cmd_doc.c Error reading Image from DOC device - 40 common/cmd_doc.c Image header has correct magic number - 41 common/cmd_ide.c before loading a Image from a IDE device - -42 common/cmd_ide.c Bad usage of "ide" command - 42 common/cmd_ide.c correct usage of "ide" command - -43 common/cmd_ide.c No boot device - 43 common/cmd_ide.c boot device found - -44 common/cmd_ide.c Device not available - 44 common/cmd_ide.c Device available - -45 common/cmd_ide.c wrong partition selected - 45 common/cmd_ide.c partition selected - -46 common/cmd_ide.c Unknown partition table - 46 common/cmd_ide.c valid partition table found - -47 common/cmd_ide.c Invalid partition type - 47 common/cmd_ide.c correct partition type - -48 common/cmd_ide.c Error reading Image Header on boot device - 48 common/cmd_ide.c reading Image Header from IDE device OK - -49 common/cmd_ide.c Image header has bad magic number - 49 common/cmd_ide.c Image header has correct magic number - -50 common/cmd_ide.c Image header has bad checksum - 50 common/cmd_ide.c Image header has correct checksum - -51 common/cmd_ide.c Error reading Image from IDE device - 51 common/cmd_ide.c reading Image from IDE device OK - 52 common/cmd_nand.c before loading a Image from a NAND device - -53 common/cmd_nand.c Bad usage of "nand" command - 53 common/cmd_nand.c correct usage of "nand" command - -54 common/cmd_nand.c No boot device - 54 common/cmd_nand.c boot device found - -55 common/cmd_nand.c Unknown Chip ID on boot device - 55 common/cmd_nand.c correct chip ID found, device available - -56 common/cmd_nand.c Error reading Image Header on boot device - 56 common/cmd_nand.c reading Image Header from NAND device OK - -57 common/cmd_nand.c Image header has bad magic number - 57 common/cmd_nand.c Image header has correct magic number - -58 common/cmd_nand.c Error reading Image from NAND device - 58 common/cmd_nand.c reading Image from NAND device OK + -1 common/cmd_doc.c Bad usage of "doc" command + -1 common/cmd_doc.c No boot device + -1 common/cmd_doc.c Unknown Chip ID on boot device + -1 common/cmd_doc.c Read Error on boot device + -1 common/cmd_doc.c Image header has bad magic number - -60 common/env_common.c Environment has a bad CRC, using default + -1 common/cmd_ide.c Bad usage of "ide" command + -1 common/cmd_ide.c No boot device + -1 common/cmd_ide.c Unknown boot device + -1 common/cmd_ide.c Unknown partition table + -1 common/cmd_ide.c Invalid partition type + -1 common/cmd_ide.c Read Error on boot device + -1 common/cmd_ide.c Image header has bad magic number - 64 net/eth.c starting with Ethernet configuration. - -64 net/eth.c no Ethernet found. - 65 net/eth.c Ethernet found. + -1 common/cmd_nand.c Bad usage of "nand" command + -1 common/cmd_nand.c No boot device + -1 common/cmd_nand.c Unknown Chip ID on boot device + -1 common/cmd_nand.c Read Error on boot device + -1 common/cmd_nand.c Image header has bad magic number - -80 common/cmd_net.c usage wrong - 80 common/cmd_net.c before calling NetLoop() - -81 common/cmd_net.c some error in NetLoop() occurred - 81 common/cmd_net.c NetLoop() back without error - -82 common/cmd_net.c size == 0 (File with size 0 loaded) - 82 common/cmd_net.c trying automatic boot - 83 common/cmd_net.c running autoscript - -83 common/cmd_net.c some error in automatic boot or autoscript - 84 common/cmd_net.c end without errors - -FIT uImage format: - - Arg Where When - 100 common/cmd_bootm.c Kernel FIT Image has correct format - -100 common/cmd_bootm.c Kernel FIT Image has incorrect format - 101 common/cmd_bootm.c No Kernel subimage unit name, using configuration - -101 common/cmd_bootm.c Can't get configuration for kernel subimage - 102 common/cmd_bootm.c Kernel unit name specified - -103 common/cmd_bootm.c Can't get kernel subimage node offset - 103 common/cmd_bootm.c Found configuration node - 104 common/cmd_bootm.c Got kernel subimage node offset - -104 common/cmd_bootm.c Kernel subimage hash verification failed - 105 common/cmd_bootm.c Kernel subimage hash verification OK - -105 common/cmd_bootm.c Kernel subimage is for unsupported architecture - 106 common/cmd_bootm.c Architecture check OK - -106 common/cmd_bootm.c Kernel subimage has wrong type - 107 common/cmd_bootm.c Kernel subimage type OK - -107 common/cmd_bootm.c Can't get kernel subimage data/size - 108 common/cmd_bootm.c Got kernel subimage data/size - -108 common/cmd_bootm.c Wrong image type (not legacy, FIT) - -109 common/cmd_bootm.c Can't get kernel subimage type - -110 common/cmd_bootm.c Can't get kernel subimage comp - -111 common/cmd_bootm.c Can't get kernel subimage os - -112 common/cmd_bootm.c Can't get kernel subimage load address - -113 common/cmd_bootm.c Image uncompress/copy overwrite error - - 120 common/image.c Start initial ramdisk verification - -120 common/image.c Ramdisk FIT image has incorrect format - 121 common/image.c Ramdisk FIT image has correct format - 122 common/image.c No ramdisk subimage unit name, using configuration - -122 common/image.c Can't get configuration for ramdisk subimage - 123 common/image.c Ramdisk unit name specified - -124 common/image.c Can't get ramdisk subimage node offset - 125 common/image.c Got ramdisk subimage node offset - -125 common/image.c Ramdisk subimage hash verification failed - 126 common/image.c Ramdisk subimage hash verification OK - -126 common/image.c Ramdisk subimage for unsupported architecture - 127 common/image.c Architecture check OK - -127 common/image.c Can't get ramdisk subimage data/size - 128 common/image.c Got ramdisk subimage data/size - 129 common/image.c Can't get ramdisk load address - -129 common/image.c Got ramdisk load address - - -130 common/cmd_doc.c Incorrect FIT image format - 131 common/cmd_doc.c FIT image format OK - - -140 common/cmd_ide.c Incorrect FIT image format - 141 common/cmd_ide.c FIT image format OK - - -150 common/cmd_nand.c Incorrect FIT image format - 151 common/cmd_nand.c FIT image format OK + -1 common/env_common.c Environment has a bad CRC, using default Modem Support: @@ -1867,7 +1635,7 @@ Modem Support: [so far only for SMDK2400 and TRAB boards] -- Modem support enable: +- Modem support endable: CONFIG_MODEM_SUPPORT - RTS/CTS Flow control enable: @@ -1883,11 +1651,11 @@ Modem Support: There are common interrupt_init() and timer_interrupt() for all PPC archs. interrupt_init() calls interrupt_init_cpu() - for CPU specific initialization. interrupt_init_cpu() + for cpu specific initialization. interrupt_init_cpu() should set decrementer_count to appropriate value. If - CPU resets decrementer automatically after interrupt + cpu resets decrementer automatically after interrupt (ppc4xx) it should set decrementer_count to zero. - timer_interrupt() calls timer_interrupt_cpu() for CPU + timer_interrupt() calls timer_interrupt_cpu() for cpu specific handling. If board has watchdog / status_led / other_activity_monitor it works automatically from general timer_interrupt(). @@ -1897,7 +1665,7 @@ Modem Support: In the target system modem support is enabled when a specific key (key combination) is pressed during power-on. Otherwise U-Boot will boot normally - (autoboot). The key_pressed() function is called from + (autoboot). The key_pressed() fuction is called from board_init(). Currently key_pressed() is a dummy function, returning 1 and thus enabling modem initialization. @@ -1905,7 +1673,7 @@ Modem Support: If there are no modem init strings in the environment, U-Boot proceed to autoboot; the previous output (banner, info printfs) will be - suppressed, though. + supressed, though. See also: doc/README.Modem @@ -1958,27 +1726,6 @@ Configuration Settings: Scratch address used by the alternate memory test You only need to set this if address zero isn't writeable -- CFG_MEM_TOP_HIDE (PPC only): - If CFG_MEM_TOP_HIDE is defined in the board config header, - this specified memory area will get subtracted from the top - (end) of RAM and won't get "touched" at all by U-Boot. By - fixing up gd->ram_size the Linux kernel should gets passed - the now "corrected" memory size and won't touch it either. - This should work for arch/ppc and arch/powerpc. Only Linux - board ports in arch/powerpc with bootwrapper support that - recalculate the memory size from the SDRAM controller setup - will have to get fixed in Linux additionally. - - This option can be used as a workaround for the 440EPx/GRx - CHIP 11 errata where the last 256 bytes in SDRAM shouldn't - be touched. - - WARNING: Please make sure that this value is a multiple of - the Linux page size (normally 4k). If this is not the case, - then the end address of the Linux memory will be located at a - non page size aligned address and this could cause major - problems. - - CFG_TFTP_LOADADDR: Default load address for network file downloads @@ -2019,11 +1766,8 @@ Configuration Settings: - CFG_BOOTMAPSZ: Maximum size of memory mapped by the startup code of the Linux kernel; all data that must be processed by - the Linux kernel (bd_info, boot arguments, FDT blob if - used) must be put below this limit, unless "bootm_low" - enviroment variable is defined and non-zero. In such case - all data for the Linux kernel must be between "bootm_low" - and "bootm_low" + CFG_BOOTMAPSZ. + the Linux kernel (bd_info, boot arguments, eventually + initrd image) must be put below this limit. - CFG_MAX_FLASH_BANKS: Max number of Flash memory banks @@ -2056,8 +1800,8 @@ Configuration Settings: The two-step approach is usually more reliable, since you can check if the download worked before you erase - the flash, but in some situations (when system RAM is - too limited to allow for a temporary copy of the + the flash, but in some situations (when sytem RAM is + too limited to allow for a tempory copy of the downloaded image) this option may be very useful. - CFG_FLASH_CFI: @@ -2068,30 +1812,18 @@ Configuration Settings: This option also enables the building of the cfi_flash driver in the drivers directory -- CFG_FLASH_USE_BUFFER_WRITE - Use buffered writes to flash. - -- CONFIG_FLASH_SPANSION_S29WS_N - s29ws-n MirrorBit flash has non-standard addresses for buffered - write commands. - - CFG_FLASH_QUIET_TEST If this option is defined, the common CFI flash doesn't print it's warning upon not recognized FLASH banks. This is useful, if some of the configured banks are only optionally available. -- CONFIG_FLASH_SHOW_PROGRESS - If defined (must be an integer), print out countdown - digits and dots. Recommended value: 45 (9..1) for 80 - column displays, 15 (3..1) for 40 column displays. - - CFG_RX_ETH_BUFFER: - Defines the number of Ethernet receive buffers. On some - Ethernet controllers it is recommended to set this value + Defines the number of ethernet receive buffers. On some + ethernet controllers it is recommended to set this value to 8 or even higher (EEPRO100 or 405 EMAC), since all buffers can be full shortly after enabling the interface - on high Ethernet traffic. + on high ethernet traffic. Defaults to 4 if not defined. The following definitions that deal with the placement and management @@ -2159,7 +1891,7 @@ following configurations: CFG_ENV_SIZE_REDUND These settings describe a second storage area used to hold - a redundant copy of the environment data, so that there is + a redundand copy of the environment data, so that there is a valid backup copy in case there is a power failure during a "saveenv" operation. @@ -2177,14 +1909,14 @@ accordingly! - CFG_ENV_ADDR: - CFG_ENV_SIZE: - These two #defines are used to determine the memory area you + These two #defines are used to determin the memory area you want to use for environment. It is assumed that this memory can just be read and written to, without any special provision. BE CAREFUL! The first access to the environment happens quite early in U-Boot initalization (when we try to get the setting of for the -console baudrate). You *MUST* have mapped your NVRAM area then, or +console baudrate). You *MUST* have mappend your NVRAM area then, or U-Boot will hang. Please note that even with NVRAM we still use a copy of the @@ -2281,7 +2013,7 @@ to save the current settings. to be a good choice since it makes it far enough from the start of the data area as well as from the stack pointer. -Please note that the environment is read-only until the monitor +Please note that the environment is read-only as long as the monitor has been relocated to RAM and a RAM copy of the environment has been created; also, when using EEPROM you will have to use getenv_r() until then to read environment variables. @@ -2333,14 +2065,14 @@ Low Level (hardware related) configuration options: CFG_ISA_IO_STRIDE - defines the spacing between FDC chipset registers + defines the spacing between fdc chipset registers (default value 1) CFG_ISA_IO_OFFSET defines the offset of register from address. It depends on which part of the data bus is connected to - the FDC chipset. (default value 0) + the fdc chipset. (default value 0) If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and CFG_FDC_DRIVE_NUMBER are undefined, they take their @@ -2429,10 +2161,6 @@ Low Level (hardware related) configuration options: enable I2C microcode relocation patch (MPC8xx); define relocation offset in DPRAM [DSP2] -- CFG_SMC_UCODE_PATCH, CFG_SMC_DPMEM_OFFSET [0x1FC0]: - enable SMC microcode relocation patch (MPC8xx); - define relocation offset in DPRAM [SMC1] - - CFG_SPI_UCODE_PATCH, CFG_SPI_DPMEM_OFFSET [0x1FC0]: enable SPI microcode relocation patch (MPC8xx); define relocation offset in DPRAM [SCC4] @@ -2458,26 +2186,6 @@ Low Level (hardware related) configuration options: CFG_POCMR2_MASK_ATTRIB: (MPC826x only) Overrides the default PCI memory map in cpu/mpc8260/pci.c if set. -- CONFIG_SPD_EEPROM - Get DDR timing information from an I2C EEPROM. Common - with pluggable memory modules such as SODIMMs - - SPD_EEPROM_ADDRESS - I2C address of the SPD EEPROM - -- CFG_SPD_BUS_NUM - If SPD EEPROM is on an I2C bus other than the first - one, specify here. Note that the value must resolve - to something your driver can deal with. - -- CFG_83XX_DDR_USES_CS0 - Only for 83xx systems. If specified, then DDR should - be configured using CS0 and CS1 instead of CS2 and CS3. - -- CFG_83XX_DDR_USES_CS0 - Only for 83xx systems. If specified, then DDR should - be configured using CS0 and CS1 instead of CS2 and CS3. - - CONFIG_ETHER_ON_FEC[12] Define to enable FEC[12] on a 8xx series processor. @@ -2510,7 +2218,7 @@ Low Level (hardware related) configuration options: - CONFIG_LOOPW Add the "loopw" memory command. This only takes effect if - the memory commands are activated globally (CONFIG_CMD_MEM). + the memory commands are activated globally (CFG_CMD_MEM). - CONFIG_MX_CYCLIC Add the "mdc" and "mwc" memory commands. These are cyclic @@ -2524,7 +2232,7 @@ Low Level (hardware related) configuration options: This command will write 12345678 to address 100 all 10 ms. This only takes effect if the memory commands are activated - globally (CONFIG_CMD_MEM). + globally (CFG_CMD_MEM). - CONFIG_SKIP_LOWLEVEL_INIT - CONFIG_SKIP_RELOCATE_UBOOT @@ -2536,42 +2244,68 @@ Low Level (hardware related) configuration options: Normally these variables MUST NOT be defined. The only exception is when U-Boot is loaded (to RAM) by some other boot loader or by a debugger which - performs these initializations itself. + performs these intializations itself. Building the Software: ====================== -Building U-Boot has been tested in several native build environments -and in many different cross environments. Of course we cannot support -all possibly existing versions of cross development tools in all -(potentially obsolete) versions. In case of tool chain problems we -recommend to use the ELDK (see http://www.denx.de/wiki/DULG/ELDK) -which is extensively used to build and test U-Boot. +Building U-Boot has been tested in native PPC environments (on a +PowerBook G3 running LinuxPPC 2000) and in cross environments +(running RedHat 6.x and 7.x Linux on x86, Solaris 2.6 on a SPARC, and +NetBSD 1.5 on x86). -If you are not using a native environment, it is assumed that you -have GNU cross compiling tools available in your path. In this case, -you must set the environment variable CROSS_COMPILE in your shell. -Note that no changes to the Makefile or any other source files are -necessary. For example using the ELDK on a 4xx CPU, please enter: +If you are not using a native PPC environment, it is assumed that you +have the GNU cross compiling tools available in your path and named +with a prefix of "powerpc-linux-". If this is not the case, (e.g. if +you are using Monta Vista's Hard Hat Linux CDK 1.2) you must change +the definition of CROSS_COMPILE in Makefile. For HHL on a 4xx CPU, +change it to: - $ CROSS_COMPILE=ppc_4xx- - $ export CROSS_COMPILE + CROSS_COMPILE = ppc_4xx- -U-Boot is intended to be simple to build. After installing the -sources you must configure U-Boot for one specific board type. This + +U-Boot is intended to be simple to build. After installing the +sources you must configure U-Boot for one specific board type. This is done by typing: make NAME_config -where "NAME_config" is the name of one of the existing configu- -rations; see the main Makefile for supported names. +where "NAME_config" is the name of one of the existing +configurations; the following names are supported: + + ADCIOP_config FPS860L_config omap730p2_config + ADS860_config GEN860T_config pcu_e_config + Alaska8220_config + AR405_config GENIETV_config PIP405_config + at91rm9200dk_config GTH_config QS823_config + CANBT_config hermes_config QS850_config + cmi_mpc5xx_config hymod_config QS860T_config + cogent_common_config IP860_config RPXlite_config + cogent_mpc8260_config IVML24_config RPXlite_DW_config + cogent_mpc8xx_config IVMS8_config RPXsuper_config + CPCI405_config JSE_config rsdproto_config + CPCIISER4_config LANTEC_config Sandpoint8240_config + csb272_config lwmon_config sbc8260_config + CU824_config MBX860T_config sbc8560_33_config + DUET_ADS_config MBX_config sbc8560_66_config + EBONY_config MPC8260ADS_config SM850_config + ELPT860_config MPC8540ADS_config SPD823TS_config + ESTEEM192E_config MPC8540EVAL_config stxgp3_config + ETX094_config MPC8560ADS_config SXNI855T_config + FADS823_config NETVIA_config TQM823L_config + FADS850SAR_config omap1510inn_config TQM850L_config + FADS860T_config omap1610h2_config TQM855L_config + FPS850L_config omap1610inn_config TQM860L_config + omap5912osk_config walnut_config + omap2420h4_config Yukon8220_config + ZPC1900_config Note: for some board special configuration names may exist; check if additional information is available from the board vendor; for instance, the TQM823L systems are available without (standard) or with LCD support. You can select such additional "features" - when choosing the configuration, i. e. + when chosing the configuration, i. e. make TQM823L_config - will configure for a plain TQM823L, i. e. no LCD support @@ -2589,26 +2323,6 @@ images ready for download to / installation on your system: - "u-boot" is an image in ELF binary format - "u-boot.srec" is in Motorola S-Record format -By default the build is performed locally and the objects are saved -in the source directory. One of the two methods can be used to change -this behavior and build U-Boot to some external directory: - -1. Add O= to the make command line invocations: - - make O=/tmp/build distclean - make O=/tmp/build NAME_config - make O=/tmp/build all - -2. Set environment variable BUILD_DIR to point to the desired location: - - export BUILD_DIR=/tmp/build - make distclean - make NAME_config - make all - -Note that the command line "O=" setting overrides the BUILD_DIR environment -variable. - Please be aware that the Makefiles assume you are using GNU make, so for instance on NetBSD you might need to use "gmake" instead of @@ -2641,20 +2355,20 @@ steps: Testing of U-Boot Modifications, Ports to New Hardware, etc.: ============================================================== -If you have modified U-Boot sources (for instance added a new board -or support for new devices, a new CPU, etc.) you are expected to +If you have modified U-Boot sources (for instance added a new board +or support for new devices, a new CPU, etc.) you are expected to provide feedback to the other developers. The feedback normally takes the form of a "patch", i. e. a context diff against a certain (latest -official or latest in the git repository) version of U-Boot sources. +official or latest in CVS) version of U-Boot sources. -But before you submit such a patch, please verify that your modifi- -cation did not break existing code. At least make sure that *ALL* of +But before you submit such a patch, please verify that your modifi- +cation did not break existing code. At least make sure that *ALL* of the supported boards compile WITHOUT ANY compiler warnings. To do so, just run the "MAKEALL" script, which will configure and build U-Boot -for ALL supported system. Be warned, this will take a while. You can -select which (cross) compiler to use by passing a `CROSS_COMPILE' -environment variable to the script, i. e. to use the ELDK cross tools -you can type +for ALL supported system. Be warned, this will take a while. You can +select which (cross) compiler to use by passing a `CROSS_COMPILE' +environment variable to the script, i. e. to use the cross tools from +MontaVista's Hard Hat Linux you can type CROSS_COMPILE=ppc_8xx- MAKEALL @@ -2662,23 +2376,6 @@ or to build on a native PowerPC system you can type CROSS_COMPILE=' ' MAKEALL -When using the MAKEALL script, the default behaviour is to build -U-Boot in the source directory. This location can be changed by -setting the BUILD_DIR environment variable. Also, for each target -built, the MAKEALL script saves two log files (.ERR and -.MAKEALL) in the /LOG directory. This default -location can be changed by setting the MAKEALL_LOGDIR environment -variable. For example: - - export BUILD_DIR=/tmp/build - export MAKEALL_LOGDIR=/tmp/log - CROSS_COMPILE=ppc_8xx- MAKEALL - -With the above settings build objects are saved in the /tmp/build, -log files are saved in the /tmp/log and the source tree remains clean -during the whole build process. - - See also "U-Boot Porting Guide" below. @@ -2768,33 +2465,11 @@ Some configuration options can be set using Environment Variables: bootfile - Name of the image to load with TFTP - bootm_low - Memory range available for image processing in the bootm - command can be restricted. This variable is given as - a hexadecimal number and defines lowest address allowed - for use by the bootm command. See also "bootm_size" - environment variable. Address defined by "bootm_low" is - also the base of the initial memory mapping for the Linux - kernel -- see the description of CFG_BOOTMAPSZ. - - bootm_size - Memory range available for image processing in the bootm - command can be restricted. This variable is given as - a hexadecimal number and defines the size of the region - allowed for use by the bootm command. See also "bootm_low" - environment variable. - autoload - if set to "no" (any string beginning with 'n'), "bootp" will just load perform a lookup of the configuration from the BOOTP server, but not try to load any image using TFTP - autoscript - if set to "yes" commands like "loadb", "loady", - "bootp", "tftpb", "rarpboot" and "nfs" will attempt - to automatically run script images (by internally - calling "autoscript"). - - autoscript_uname - if script image is in a format (FIT) this - variable is used to get script subimage unit name. - autostart - if set to "yes", an image loaded using the "bootp", "rarpboot", "tftpboot" or "diskboot" commands will be automatically started (by internally calling @@ -2868,10 +2543,6 @@ Some configuration options can be set using Environment Variables: => setenv ethact SCC ETHERNET => ping 10.0.0.1 # traffic sent on SCC ETHERNET - ethrotate - When set to "no" U-Boot does not go through all - available network interfaces. - It just stays at the currently selected interface. - netretry - When set to "no" each network operation will either succeed or fail without retrying. When set to "once" the network operation will @@ -2880,9 +2551,6 @@ Some configuration options can be set using Environment Variables: Useful on scripts which control the retry operation themselves. - npe_ucode - see CONFIG_IXP4XX_NPE_EXT_UCOD - if set load address for the NPE microcode - tftpsrcport - If this is set, the value is used for TFTP's UDP source port. @@ -2890,7 +2558,7 @@ Some configuration options can be set using Environment Variables: destination port instead of the Well Know Port 69. vlan - When set to a value < 4095 the traffic over - Ethernet is encapsulated/received over 802.1q + ethernet is encapsulated/received over 802.1q VLAN tagged frames. The following environment variables may be used and automatically @@ -2968,14 +2636,14 @@ General rules: executed anyway. (2) If you execute several variables with one call to run (i. e. - calling run with a list of variables as arguments), any failing + calling run with a list af variables as arguments), any failing command will cause "run" to terminate, i. e. the remaining variables are not executed. Note for Redundant Ethernet Interfaces: ======================================= -Some boards come with redundant Ethernet interfaces; U-Boot supports +Some boards come with redundant ethernet interfaces; U-Boot supports such configurations and is capable of automatic selection of a "working" interface when needed. MAC assignment works as follows: @@ -3009,32 +2677,18 @@ o If neither SROM nor the environment contain a MAC address, an error Image Formats: ============== -U-Boot is capable of booting (and performing other auxiliary operations on) -images in two formats: - -New uImage format (FIT) ------------------------ - -Flexible and powerful format based on Flattened Image Tree -- FIT (similar -to Flattened Device Tree). It allows the use of images with multiple -components (several kernels, ramdisks, etc.), with contents protected by -SHA1, MD5 or CRC32. More details are found in the doc/uImage.FIT directory. - - -Old uImage format ------------------ - -Old image format is based on binary files which can be basically anything, -preceded by a special header; see the definitions in include/image.h for -details; basically, the header defines the following image properties: +The "boot" commands of this monitor operate on "image" files which +can be basicly anything, preceeded by a special header; see the +definitions in include/image.h for details; basicly, the header +defines the following image properties: * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD, 4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks, LynxOS, pSOS, QNX, RTEMS, ARTOS; Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS). -* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86, +* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86, IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; - Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC). + Currently supported: ARM, Intel x86, MIPS, NIOS, PowerPC). * Compression Type (uncompressed, gzip, bzip2) * Load Address * Entry Point @@ -3268,7 +2922,7 @@ TQM8xxL is in the first Flash bank): You can check the success of the download using the 'iminfo' command; -this includes a checksum verification so you can be sure no data +this includes a checksum verification so you can be sure no data corruption happened: => imi 40100000 @@ -3316,7 +2970,7 @@ parameters. You can check and modify this variable using the Memory: 15208k available (700k kernel code, 444k data, 32k init) [c0000000,c1000000] ... -If you want to boot a Linux kernel with initial RAM disk, you pass +If you want to boot a Linux kernel with initial ram disk, you pass the memory addresses of both the kernel and the initrd image (PPBCOOT format!) to the "bootm" command: @@ -3365,55 +3019,6 @@ format!) to the "bootm" command: bash# -Boot Linux and pass a flat device tree: ------------ - -First, U-Boot must be compiled with the appropriate defines. See the section -titled "Linux Kernel Interface" above for a more in depth explanation. The -following is an example of how to start a kernel and pass an updated -flat device tree: - -=> print oftaddr -oftaddr=0x300000 -=> print oft -oft=oftrees/mpc8540ads.dtb -=> tftp $oftaddr $oft -Speed: 1000, full duplex -Using TSEC0 device -TFTP from server 192.168.1.1; our IP address is 192.168.1.101 -Filename 'oftrees/mpc8540ads.dtb'. -Load address: 0x300000 -Loading: # -done -Bytes transferred = 4106 (100a hex) -=> tftp $loadaddr $bootfile -Speed: 1000, full duplex -Using TSEC0 device -TFTP from server 192.168.1.1; our IP address is 192.168.1.2 -Filename 'uImage'. -Load address: 0x200000 -Loading:############ -done -Bytes transferred = 1029407 (fb51f hex) -=> print loadaddr -loadaddr=200000 -=> print oftaddr -oftaddr=0x300000 -=> bootm $loadaddr - $oftaddr -## Booting image at 00200000 ... - Image Name: Linux-2.6.17-dirty - Image Type: PowerPC Linux Kernel Image (gzip compressed) - Data Size: 1029343 Bytes = 1005.2 kB - Load Address: 00000000 - Entry Point: 00000000 - Verifying Checksum ... OK - Uncompressing Kernel Image ... OK -Booting using flat device tree at 0x300000 -Using MPC85xx ADS machine description -Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb -[snip] - - More About U-Boot Image Types: ------------------------------ @@ -3613,7 +3218,7 @@ models provide on-chip memory (like the IMMR area on MPC8xx and MPC826x processors), on others (parts of) the data cache can be locked as (mis-) used as memory, etc. - Chris Hallinan posted a good summary of these issues to the + Chris Hallinan posted a good summary of these issues to the u-boot-users mailing list: Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)? @@ -3626,13 +3231,13 @@ locked as (mis-) used as memory, etc. require any physical RAM backing up the cache. The cleverness is that the cache is being used as a temporary supply of necessary storage before the SDRAM controller is setup. It's - beyond the scope of this list to explain the details, but you + beyond the scope of this list to expain the details, but you can see how this works by studying the cache architecture and operation in the architecture and processor-specific manuals. OCM is On Chip Memory, which I believe the 405GP has 4K. It is another option for the system designer to use as an - initial stack/RAM area prior to SDRAM being available. Either + initial stack/ram area prior to SDRAM being available. Either option should work for you. Using CS 4 should be fine if your board designers haven't used it for something that would cause you grief during the initial boot! It is frequently not @@ -3657,7 +3262,7 @@ code for the initialization procedures: * Initialized global data (data segment) is read-only. Do not attempt to write it. -* Do not use any uninitialized global data (or implicitely initialized +* Do not use any unitialized global data (or implicitely initialized as zero data - BSS segment) at all - this is undefined, initiali- zation is performed later (when relocating to RAM). @@ -3680,7 +3285,7 @@ GCC's implementation. For PowerPC, the following registers have specific use: R1: stack pointer - R2: reserved for system use + R2: TOC pointer R3-R4: parameter passing and return values R5-R10: parameter passing R13: small data area pointer @@ -3689,7 +3294,7 @@ For PowerPC, the following registers have specific use: (U-Boot also uses R14 as internal GOT pointer.) - ==> U-Boot will use R2 to hold a pointer to the global data + ==> U-Boot will use R29 to hold a pointer to the global data Note: on PPC, we could use a static initializer (since the address of the global data structure is known at compile time), @@ -3698,11 +3303,6 @@ For PowerPC, the following registers have specific use: average for all boards 752 bytes for the whole U-Boot image, 624 text + 127 data). -On Blackfin, the normal C ABI (except for P5) is followed as documented here: - http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface - - ==> U-Boot will use P5 to hold a pointer to the global data - On ARM, the following registers are used: R0: function argument word/integer result @@ -3769,7 +3369,7 @@ System Initialization: ---------------------- In the reset configuration, U-Boot starts at the reset entry point -(on most PowerPC systems at address 0x00000100). Because of the reset +(on most PowerPC systens at address 0x00000100). Because of the reset configuration for CS0# this is a mirror of the onboard Flash memory. To be able to re-map memory U-Boot then jumps to its link address. To be able to implement the initialization code in C, a (small!) @@ -3869,19 +3469,12 @@ Coding Standards: ----------------- All contributions to U-Boot should conform to the Linux kernel -coding style; see the file "Documentation/CodingStyle" and the script -"scripts/Lindent" in your Linux kernel source directory. In sources -originating from U-Boot a style corresponding to "Lindent -pcs" (adding -spaces before parameters to function calls) is actually used. +coding style; see the file "Documentation/CodingStyle" in your Linux +kernel source directory. -Source files originating from a different project (for example the -MTD subsystem) are generally exempt from these guidelines and are not -reformated to ease subsequent migration to newer versions of those -sources. - -Please note that U-Boot is implemented in C (and to some small parts in -Assembler); no C++ is used, so please do not use C++ style comments (//) -in your code. +Please note that U-Boot is implemented in C (and to some small parts +in Assembler); no C++ is used, so please do not use C++ style +comments (//) in your code. Please also stick to the following formatting rules: - remove any trailing white space @@ -3903,8 +3496,6 @@ may be rejected, even when they contain important and valuable stuff. Patches shall be sent to the u-boot-users mailing list. -Please see http://www.denx.de/wiki/U-Boot/Patches for details. - When you send a patch, please include the following information with it: @@ -3925,23 +3516,18 @@ it: * If your patch adds new configuration options, don't forget to document these in the README file. -* The patch itself. If you are using git (which is *strongly* - recommended) you can easily generate the patch using the - "git-format-patch". If you then use "git-send-email" to send it to - the U-Boot mailing list, you will avoid most of the common problems - with some other mail clients. +* The patch itself. If you are accessing the CVS repository use "cvs + update; cvs diff -puRN"; else, use "diff -purN OLD NEW". If your + version of diff does not support these options, then get the latest + version of GNU diff. - If you cannot use git, use "diff -purN OLD NEW". If your version of - diff does not support these options, then get the latest version of - GNU diff. + The current directory when running this command shall be the top + level directory of the U-Boot source tree, or it's parent directory + (i. e. please make sure that your patch includes sufficient + directory information for the affected files). - The current directory when running this command shall be the parent - directory of the U-Boot source tree (i. e. please make sure that - your patch includes sufficient directory information for the - affected files). - - We prefer patches as plain text. MIME attachments are discouraged, - and compressed attachments must not be used. + We accept patches as plain text, MIME attachments or as uuencoded + gzipped text. * If one logical set of modifications affects or creates several files, all these changes shall be submitted in a SINGLE patch file. @@ -3968,6 +3554,4 @@ Notes: modification. * Remember that there is a size limit of 40 kB per message on the - u-boot-users mailing list. Bigger patches will be moderated. If - they are reasonable and not bigger than 100 kB, they will be - acknowledged. Even bigger patches should be avoided. + u-boot-users mailing list. Compression may help. diff --git a/arm_config.mk b/arm_config.mk index 73d9625be..c9b12aeec 100644 --- a/arm_config.mk +++ b/arm_config.mk @@ -21,4 +21,4 @@ # MA 02111-1307 USA # -PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ +PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ -mapcs -mabi=apcs-gnu diff --git a/blackfin_config.mk b/blackfin_config.mk index a9a3d1a17..e2747aafe 100644 --- a/blackfin_config.mk +++ b/blackfin_config.mk @@ -21,19 +21,4 @@ # MA 02111-1307 USA # -CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) -CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) - -PLATFORM_RELFLAGS += -ffixed-P5 -PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN - -ifneq (,$(CONFIG_BFIN_CPU)) -PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) -endif - -SYM_PREFIX = _ - -LDR_FLAGS += --use-vmas -ifneq (,$(findstring s,$(MAKEFLAGS))) -LDR_FLAGS += --quiet -endif +PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -D__blackfin__ diff --git a/board/AtmarkTechno/suzaku/Makefile b/board/AtmarkTechno/suzaku/Makefile index 109cec264..7a1706793 100644 --- a/board/AtmarkTechno/suzaku/Makefile +++ b/board/AtmarkTechno/suzaku/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/AtmarkTechno/suzaku/suzaku.c b/board/AtmarkTechno/suzaku/suzaku.c index 267c476f0..afe124a9d 100644 --- a/board/AtmarkTechno/suzaku/suzaku.c +++ b/board/AtmarkTechno/suzaku/suzaku.c @@ -24,7 +24,7 @@ /* This is a board specific file. It's OK to include board specific * header files */ -#include +#include void do_reset(void) { diff --git a/board/AtmarkTechno/suzaku/u-boot.lds b/board/AtmarkTechno/suzaku/u-boot.lds index cb90854a3..00a8ef7ad 100644 --- a/board/AtmarkTechno/suzaku/u-boot.lds +++ b/board/AtmarkTechno/suzaku/u-boot.lds @@ -61,7 +61,6 @@ SECTIONS { __bss_start = .; *(.bss) - __bss_end = .; + __bss_start = .; } - __end = . ; } diff --git a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c index 39c97b1f5..f18313d51 100644 --- a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c +++ b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c @@ -39,53 +39,53 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { - int size, i; + int size,i; size = 0; - MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 - | MCFSDRAMC_DCR_RC ((15 * CFG_CLK) >> 4); -#ifdef CFG_SDRAM_BASE0 + MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 + | MCFSDRAMC_DCR_RC((15 * CFG_CLK)>>4); + #ifdef CFG_SDRAM_BASE0 - MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE0) - | MCFSDRAMC_DACR_CASL (1) - | MCFSDRAMC_DACR_CBM (3) - | MCFSDRAMC_DACR_PS_16; + MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0) + | MCFSDRAMC_DACR_CASL(1) + | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_16); - MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V; + MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M + | MCFSDRAMC_DMR_V; - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; - *(unsigned short *) (CFG_SDRAM_BASE0) = 0xA5A5; - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; - for (i = 0; i < 2000; i++) - asm (" nop"); - mbar_writeLong (MCFSDRAMC_DACR0, - mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS); - *(unsigned int *) (CFG_SDRAM_BASE0 + 0x220) = 0xA5A5; - size += CFG_SDRAM_SIZE * 1024 * 1024; -#endif -#ifdef CFG_SDRAM_BASE1 - MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE1) - | MCFSDRAMC_DACR_CASL (1) - | MCFSDRAMC_DACR_CBM (3) - | MCFSDRAMC_DACR_PS_16; + *(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5; + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; + for (i=0; i < 2000; i++) + asm(" nop"); + mbar_writeLong(MCFSDRAMC_DACR0, mbar_readLong(MCFSDRAMC_DACR0) + | MCFSDRAMC_DACR_IMRS); + *(unsigned int *)(CFG_SDRAM_BASE0 + 0x220) = 0xA5A5; + size += CFG_SDRAM_SIZE * 1024 * 1024; + #endif + #ifdef CFG_SDRAM_BASE1 + MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1) + | MCFSDRAMC_DACR_CASL(1) + | MCFSDRAMC_DACR_CBM(3) + | MCFSDRAMC_DACR_PS_16; - MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V; + MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M + | MCFSDRAMC_DMR_V; - MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP; + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP; - *(unsigned short *) (CFG_SDRAM_BASE1) = 0xA5A5; - MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE; - - for (i = 0; i < 2000; i++) - asm (" nop"); - - MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; - *(unsigned int *) (CFG_SDRAM_BASE1 + 0x220) = 0xA5A5; - size += CFG_SDRAM_SIZE1 * 1024 * 1024; -#endif + *(unsigned short *)(CFG_SDRAM_BASE1) = 0xA5A5; + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE; + for (i=0; i < 2000; i++) + asm(" nop"); + MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; + *(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5; + size += CFG_SDRAM_SIZE1 * 1024 * 1024; + #endif return size; } diff --git a/board/BuS/EB+MCF-EV123/Makefile b/board/BuS/EB+MCF-EV123/Makefile index ceeffa775..0596572d1 100644 --- a/board/BuS/EB+MCF-EV123/Makefile +++ b/board/BuS/EB+MCF-EV123/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o +OBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/BuS/EB+MCF-EV123/VCxK.c b/board/BuS/EB+MCF-EV123/VCxK.c index 4b46b7c9a..493881791 100644 --- a/board/BuS/EB+MCF-EV123/VCxK.c +++ b/board/BuS/EB+MCF-EV123/VCxK.c @@ -66,7 +66,7 @@ int init_vcxk(void) return 1; } -void vcxk_loadimage(ulong source) +void vcxk_loadimage(ulong source) { int cnt; vcxk_acknowledge_wait(); diff --git a/board/BuS/EB+MCF-EV123/VCxK.h b/board/BuS/EB+MCF-EV123/VCxK.h index f591e5c52..74467ba98 100644 --- a/board/BuS/EB+MCF-EV123/VCxK.h +++ b/board/BuS/EB+MCF-EV123/VCxK.h @@ -25,24 +25,24 @@ #define __VCXK_H_ extern int init_vcxk(void); -void vcxk_loadimage(ulong source); +void vcxk_loadimage(ulong source); #define VIDEO_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT -#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR +#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR #define VIDEO_ACKNOWLEDGE_PIN 0x0001 -#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT -#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR +#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT +#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR #define VIDEO_ENABLE_PIN 0x0002 -#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT -#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR +#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT +#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR #define VIDEO_REQUEST_PIN 0x0004 #define VIDEO_Invert_CFG MCFGPIO_PEPAR #define VIDEO_Invert_IO MCFGPIO_PEPAR_PEPA2 -#define VIDEO_INVERT_PORT MCFGPIO_PORTE -#define VIDEO_INVERT_DDR MCFGPIO_DDRE +#define VIDEO_INVERT_PORT MCFGPIO_PORTE +#define VIDEO_INVERT_DDR MCFGPIO_DDRE #define VIDEO_INVERT_PIN MCFGPIO_PORT2 #endif diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.c b/board/BuS/EB+MCF-EV123/cfm_flash.c index 98e563fc5..6ecf0d1f5 100644 --- a/board/BuS/EB+MCF-EV123/cfm_flash.c +++ b/board/BuS/EB+MCF-EV123/cfm_flash.c @@ -60,7 +60,7 @@ void cfm_flash_init (flash_info_t * info) MCFCFM_MCR = 0; MCFCFM_CLKD = CFM_CLK; debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\ - CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ + CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ CFG_CLK); MCFCFM_SACC = 0; MCFCFM_DACC = 0; @@ -173,7 +173,7 @@ int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cn dest = cmf_backdoor_address(addr); while ((cnt>=4) && (rc == ERR_OK)) { - data = *((volatile u32 *) src); + data =*((volatile u32 *) src); *(volatile u32*) dest = data; MCFCFM_CMD = MCFCFM_CMD_PGM; MCFCFM_USTAT = MCFCFM_USTAT_CBEIF; diff --git a/board/BuS/EB+MCF-EV123/config.mk b/board/BuS/EB+MCF-EV123/config.mk index f03e3962d..9fe2fc5da 100644 --- a/board/BuS/EB+MCF-EV123/config.mk +++ b/board/BuS/EB+MCF-EV123/config.mk @@ -22,7 +22,7 @@ # MA 02111-1307 USA # -sinclude $(OBJTREE)/board/$(BOARDDIR)/textbase.mk +sinclude $(TOPDIR)/board/$(BOARDDIR)/textbase.mk ifndef TEXT_BASE TEXT_BASE = 0xFE000000 endif diff --git a/board/BuS/EB+MCF-EV123/flash.c b/board/BuS/EB+MCF-EV123/flash.c index c2a1b6ff6..ba76bef12 100644 --- a/board/BuS/EB+MCF-EV123/flash.c +++ b/board/BuS/EB+MCF-EV123/flash.c @@ -256,7 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) enable_interrupts (); if (cflag) - icache_enable (); + icache_enable (); return rc; } @@ -348,7 +348,7 @@ int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt dest = addr; while ((cnt>=2) && (rc == ERR_OK)) { - data = *((volatile u16 *) src); + data =*((volatile u16 *) src); rc=amd_write_word (info,dest,data); src +=2; dest +=2; diff --git a/board/BuS/EB+MCF-EV123/textbase.mk b/board/BuS/EB+MCF-EV123/textbase.mk index ecde6ed8b..10106f458 100644 --- a/board/BuS/EB+MCF-EV123/textbase.mk +++ b/board/BuS/EB+MCF-EV123/textbase.mk @@ -1 +1 @@ -TEXT_BASE = 0xFFE00000 +TEXT_BASE = 0xF0000000 diff --git a/board/BuS/EB+MCF-EV123/u-boot.lds b/board/BuS/EB+MCF-EV123/u-boot.lds index 4a880e689..d790018d2 100644 --- a/board/BuS/EB+MCF-EV123/u-boot.lds +++ b/board/BuS/EB+MCF-EV123/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -125,7 +126,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { _sbss = .; *(.sbss) *(.scommon) diff --git a/board/LEOX/elpt860/Makefile b/board/LEOX/elpt860/Makefile index 29286919c..3e731636e 100644 --- a/board/LEOX/elpt860/Makefile +++ b/board/LEOX/elpt860/Makefile @@ -4,9 +4,6 @@ # Copyright (C) 2000, 2001, 2002, 2003 # The LEOX team , http://www.leox.org # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # LEOX.org is about the development of free hardware and software resources # for system on chip. # @@ -34,22 +31,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c index 5f506314c..775db738e 100644 --- a/board/LEOX/elpt860/elpt860.c +++ b/board/LEOX/elpt860/elpt860.c @@ -35,7 +35,7 @@ ** ------ ** int board_early_init_f(void) ** int checkboard(void) -** phys_size_t initdram(int board_type) +** long int initdram(int board_type) ** called from 'board_init_f()' into 'common/board.c' ** ** void reset_phy(void) @@ -179,7 +179,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index 7b1440b36..b09fc3390 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -31,6 +31,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -42,11 +43,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -141,7 +142,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug index 357867054..6f5af91fd 100644 --- a/board/LEOX/elpt860/u-boot.lds.debug +++ b/board/LEOX/elpt860/u-boot.lds.debug @@ -31,6 +31,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -42,11 +43,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c index e118563fc..40f41c781 100644 --- a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c +++ b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c @@ -14,7 +14,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -30,49 +30,49 @@ #include "memio.h" #include "via686.h" -__asm__(" .globl send_kb \n " - "send_kb: \n " - " lis r9, 0xfe00 \n " - " \n " - " li r4, 0x10 # retries \n " - " mtctr r4 \n " - " \n " - "idle: \n " - " lbz r4, 0x64(r9) \n " - " andi. r4, r4, 0x02 \n " - " bne idle \n " - - "ready: \n " - " stb r3, 0x60(r9) \n " - " \n " - "check: \n " - " lbz r4, 0x64(r9) \n " - " andi. r4, r4, 0x01 \n " - " beq check \n " - " \n " - " lbz r4, 0x60(r9) \n " - " cmpwi r4, 0xfa \n " - " beq done \n " - - " bdnz idle \n " - - " li r3, 0 \n " - " blr \n " - - "done: \n " - " li r3, 1 \n " - " blr \n " - - ".globl test_kb \n " - "test_kb: \n " - " mflr r10 \n " - " li r3, 0xed \n " - " bl send_kb \n " - " li r3, 0x01 \n " - " bl send_kb \n " - " mtlr r10 \n " - " blr \n " -); +__asm(" .globl send_kb \n + send_kb: \n + lis r9, 0xfe00 \n + \n + li r4, 0x10 # retries \n + mtctr r4 \n + \n + idle: \n + lbz r4, 0x64(r9) \n + andi. r4, r4, 0x02 \n + bne idle \n + \n + ready: \n + stb r3, 0x60(r9) \n + \n + check: \n + lbz r4, 0x64(r9) \n + andi. r4, r4, 0x01 \n + beq check \n + \n + lbz r4, 0x60(r9) \n + cmpwi r4, 0xfa \n + beq done \n + \n + bdnz idle \n + \n + li r3, 0 \n + blr \n + \n + done: \n + li r3, 1 \n + blr \n + \n + .globl test_kb \n + test_kb: \n + mflr r10 \n + li r3, 0xed \n + bl send_kb \n + li r3, 0x01 \n + bl send_kb \n + mtlr r10 \n + blr \n +"); int checkboard (void) @@ -81,7 +81,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long initdram (int board_type) { return articiaS_ram_init (); } diff --git a/board/MAI/AmigaOneG3SE/Makefile b/board/MAI/AmigaOneG3SE/Makefile index fa28d3b49..b1247fe4e 100644 --- a/board/MAI/AmigaOneG3SE/Makefile +++ b/board/MAI/AmigaOneG3SE/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,42 +22,35 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../menu) -$(shell mkdir -p $(obj)../bios_emulator) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \ - via686.o i8259.o ../bios_emulator/x86interface.o \ + via686.o i8259.o ../bios_emulator/x86interface.o \ ../bios_emulator/bios.o ../bios_emulator/glue.o \ interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \ ../menu/cmd_menu.o cmd_boota.o nvram.o -SOBJS = board_asm_init.o memio.o +AOBJS = board_asm_init.o memio.o + +OBJS = $(COBJS) $(AOBJS) EMUDIR = ../bios_emulator/scitech/src/x86emu/ EMUOBJ = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \ $(EMUDIR)ops.o $(EMUDIR)sys.o -EMUSRC = $(EMUOBJ:.o=.c) +EMUSRC = $(EMUOBJ:.o=.c) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -EMUOBJ := $(addprefix $(obj),$(EMUOBJ)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(EMUSRC) - make $(obj)libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE) +$(LIB): .depend $(OBJS) $(EMUSRC) + make libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE) -rm $(LIB) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(EMUOBJ) + $(AR) crv $@ $(OBJS) $(EMUOBJ) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/MAI/AmigaOneG3SE/articiaS_pci.c b/board/MAI/AmigaOneG3SE/articiaS_pci.c index 45b819501..480dae5b9 100644 --- a/board/MAI/AmigaOneG3SE/articiaS_pci.c +++ b/board/MAI/AmigaOneG3SE/articiaS_pci.c @@ -368,11 +368,11 @@ void articiaS_pci_init (void) if (articiaS_init_vga() == -1) { /* If the VGA didn't init and we have stdout set to VGA, reset to serial */ -/* s = getenv("stdout"); */ -/* if (s && strcmp(s, "vga") == 0) */ -/* { */ -/* setenv("stdout", "serial"); */ -/* } */ +/* s = getenv("stdout"); */ +/* if (s && strcmp(s, "vga") == 0) */ +/* { */ +/* setenv("stdout", "serial"); */ +/* } */ } } pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF); diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c index 40c951d06..143bba2f1 100644 --- a/board/MAI/AmigaOneG3SE/cmd_boota.c +++ b/board/MAI/AmigaOneG3SE/cmd_boota.c @@ -119,7 +119,7 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } -#if defined(CONFIG_AMIGAONEG3SE) && defined(CONFIG_CMD_BSP) +#if defined(CONFIG_AMIGAONEG3SE) && (CONFIG_COMMANDS & CFG_CMD_BSP) U_BOOT_CMD( boota, 3, 1, do_boota, "boota - boot an Amiga kernel\n", diff --git a/board/MAI/AmigaOneG3SE/enet.c b/board/MAI/AmigaOneG3SE/enet.c index 5a90cc57d..d4be889ea 100644 --- a/board/MAI/AmigaOneG3SE/enet.c +++ b/board/MAI/AmigaOneG3SE/enet.c @@ -41,57 +41,57 @@ /* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */ -#define TotalReset (0<<11) -#define SelectWindow (1<<11) -#define StartCoax (2<<11) -#define RxDisable (3<<11) -#define RxEnable (4<<11) -#define RxReset (5<<11) -#define UpStall (6<<11) -#define UpUnstall (6<<11)+1 -#define DownStall (6<<11)+2 -#define DownUnstall (6<<11)+3 -#define RxDiscard (8<<11) -#define TxEnable (9<<11) -#define TxDisable (10<<11) -#define TxReset (11<<11) -#define FakeIntr (12<<11) -#define AckIntr (13<<11) -#define SetIntrEnb (14<<11) -#define SetStatusEnb (15<<11) -#define SetRxFilter (16<<11) -#define SetRxThreshold (17<<11) -#define SetTxThreshold (18<<11) -#define SetTxStart (19<<11) -#define StartDMAUp (20<<11) -#define StartDMADown (20<<11)+1 +#define TotalReset (0<<11) +#define SelectWindow (1<<11) +#define StartCoax (2<<11) +#define RxDisable (3<<11) +#define RxEnable (4<<11) +#define RxReset (5<<11) +#define UpStall (6<<11) +#define UpUnstall (6<<11)+1 +#define DownStall (6<<11)+2 +#define DownUnstall (6<<11)+3 +#define RxDiscard (8<<11) +#define TxEnable (9<<11) +#define TxDisable (10<<11) +#define TxReset (11<<11) +#define FakeIntr (12<<11) +#define AckIntr (13<<11) +#define SetIntrEnb (14<<11) +#define SetStatusEnb (15<<11) +#define SetRxFilter (16<<11) +#define SetRxThreshold (17<<11) +#define SetTxThreshold (18<<11) +#define SetTxStart (19<<11) +#define StartDMAUp (20<<11) +#define StartDMADown (20<<11)+1 #define StatsEnable (21<<11) #define StatsDisable (22<<11) -#define StopCoax (23<<11) -#define SetFilterBit (25<<11) +#define StopCoax (23<<11) +#define SetFilterBit (25<<11) /* The SetRxFilter command accepts the following classes */ -#define RxStation 1 +#define RxStation 1 #define RxMulticast 2 #define RxBroadcast 4 -#define RxProm 8 +#define RxProm 8 /* 3Com status word defnitions */ -#define IntLatch 0x0001 -#define HostError 0x0002 -#define TxComplete 0x0004 -#define TxAvailable 0x0008 -#define RxComplete 0x0010 -#define RxEarly 0x0020 -#define IntReq 0x0040 -#define StatsFull 0x0080 -#define DMADone (1<<8) -#define DownComplete (1<<9) -#define UpComplete (1<<10) -#define DMAInProgress (1<<11) /* DMA controller is still busy.*/ -#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/ +#define IntLatch 0x0001 +#define HostError 0x0002 +#define TxComplete 0x0004 +#define TxAvailable 0x0008 +#define RxComplete 0x0010 +#define RxEarly 0x0020 +#define IntReq 0x0040 +#define StatsFull 0x0080 +#define DMADone (1<<8) +#define DownComplete (1<<9) +#define UpComplete (1<<10) +#define DMAInProgress (1<<11) /* DMA controller is still busy.*/ +#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/ /* Polling Registers */ @@ -100,17 +100,17 @@ /* Register window 0 offets */ -#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */ -#define Wn0EepromData 12 /* Window 0: EEPROM results register. */ -#define IntrStatus 0x0E /* Valid in all windows. */ +#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */ +#define Wn0EepromData 12 /* Window 0: EEPROM results register. */ +#define IntrStatus 0x0E /* Valid in all windows. */ /* Register window 0 EEPROM bits */ -#define EEPROM_Read 0x80 -#define EEPROM_WRITE 0x40 -#define EEPROM_ERASE 0xC0 -#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */ -#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */ +#define EEPROM_Read 0x80 +#define EEPROM_WRITE 0x40 +#define EEPROM_ERASE 0xC0 +#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */ +#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */ /* EEPROM locations. */ @@ -129,13 +129,13 @@ /* Register window 1 offsets, the window used in normal operation */ -#define TX_FIFO 0x10 -#define RX_FIFOa 0x10 -#define RxErrors 0x14 -#define RxStatus 0x18 +#define TX_FIFO 0x10 +#define RX_FIFO 0x10 +#define RxErrors 0x14 +#define RxStatus 0x18 #define Timer 0x1A -#define TxStatus 0x1B -#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */ +#define TxStatus 0x1B +#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */ /* Register Window 2 */ @@ -143,63 +143,63 @@ /* Register Window 3: MAC/config bits */ -#define Wn3_Config 0 /* Internal Configuration */ +#define Wn3_Config 0 /* Internal Configuration */ #define Wn3_MAC_Ctrl 6 #define Wn3_Options 8 -#define BFEXT(value, offset, bitcount) \ +#define BFEXT(value, offset, bitcount) \ ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1)) -#define BFINS(lhs, rhs, offset, bitcount) \ - (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ +#define BFINS(lhs, rhs, offset, bitcount) \ + (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ (((rhs) & ((1 << (bitcount)) - 1)) << (offset))) -#define RAM_SIZE(v) BFEXT(v, 0, 3) -#define RAM_WIDTH(v) BFEXT(v, 3, 1) -#define RAM_SPEED(v) BFEXT(v, 4, 2) -#define ROM_SIZE(v) BFEXT(v, 6, 2) -#define RAM_SPLIT(v) BFEXT(v, 16, 2) -#define XCVR(v) BFEXT(v, 20, 4) -#define AUTOSELECT(v) BFEXT(v, 24, 1) +#define RAM_SIZE(v) BFEXT(v, 0, 3) +#define RAM_WIDTH(v) BFEXT(v, 3, 1) +#define RAM_SPEED(v) BFEXT(v, 4, 2) +#define ROM_SIZE(v) BFEXT(v, 6, 2) +#define RAM_SPLIT(v) BFEXT(v, 16, 2) +#define XCVR(v) BFEXT(v, 20, 4) +#define AUTOSELECT(v) BFEXT(v, 24, 1) /* Register Window 4: Xcvr/media bits */ -#define Wn4_FIFODiag 4 -#define Wn4_NetDiag 6 +#define Wn4_FIFODiag 4 +#define Wn4_NetDiag 6 #define Wn4_PhysicalMgmt 8 -#define Wn4_Media 10 +#define Wn4_Media 10 -#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */ -#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */ -#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */ -#define Media_LnkBeat 0x0800 +#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */ +#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */ +#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */ +#define Media_LnkBeat 0x0800 /* Register Window 7: Bus Master control */ -#define Wn7_MasterAddr 0 -#define Wn7_MasterLen 6 -#define Wn7_MasterStatus 12 +#define Wn7_MasterAddr 0 +#define Wn7_MasterLen 6 +#define Wn7_MasterStatus 12 /* Boomerang bus master control registers. */ -#define PktStatus 0x20 +#define PktStatus 0x20 #define DownListPtr 0x24 -#define FragAddr 0x28 -#define FragLen 0x2c -#define TxFreeThreshold 0x2f -#define UpPktStatus 0x30 -#define UpListPtr 0x38 +#define FragAddr 0x28 +#define FragLen 0x2c +#define TxFreeThreshold 0x2f +#define UpPktStatus 0x30 +#define UpListPtr 0x38 /* The Rx and Tx descriptor lists. */ -#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ -#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */ +#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ +#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */ struct rx_desc_3com { - u32 next; /* Last entry points to 0 */ - u32 status; /* FSH -> Frame Start Header */ - u32 addr; /* Up to 63 addr/len pairs possible */ - u32 length; /* Set LAST_FRAG to indicate last pair */ + u32 next; /* Last entry points to 0 */ + u32 status; /* FSH -> Frame Start Header */ + u32 addr; /* Up to 63 addr/len pairs possible */ + u32 length; /* Set LAST_FRAG to indicate last pair */ }; /* Values for the Rx status entry. */ @@ -214,8 +214,8 @@ struct rx_desc_3com { #define UDPChksumValid (1<<31) struct tx_desc_3com { - u32 next; /* Last entry points to 0 */ - u32 status; /* bits 0:12 length, others see below */ + u32 next; /* Last entry points to 0 */ + u32 status; /* bits 0:12 length, others see below */ u32 addr; u32 length; }; @@ -227,7 +227,7 @@ struct tx_desc_3com { #define AddIPChksum 0x02000000 #define AddTCPChksum 0x04000000 #define AddUDPChksum 0x08000000 -#define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */ +#define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */ /* XCVR Types */ @@ -240,19 +240,19 @@ struct tx_desc_3com { #define XCVR_MII 6 #define XCVR_NWAY 8 #define XCVR_ExtMII 9 -#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */ +#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */ -struct descriptor { /* A generic descriptor. */ - u32 next; /* Last entry points to 0 */ - u32 status; /* FSH -> Frame Start Header */ - u32 addr; /* Up to 63 addr/len pairs possible */ - u32 length; /* Set LAST_FRAG to indicate last pair */ +struct descriptor { /* A generic descriptor. */ + u32 next; /* Last entry points to 0 */ + u32 status; /* FSH -> Frame Start Header */ + u32 addr; /* Up to 63 addr/len pairs possible */ + u32 length; /* Set LAST_FRAG to indicate last pair */ }; /* Misc. definitions */ -#define NUM_RX_DESC PKTBUFSRX * 10 -#define NUM_TX_DESC 1 /* Number of TX descriptors */ +#define NUM_RX_DESC PKTBUFSRX * 10 +#define NUM_TX_DESC 1 /* Number of TX descriptors */ #define TOUT_LOOP 1000000 @@ -266,17 +266,17 @@ struct descriptor { /* A generic descriptor. */ #undef ETH_DEBUG #ifdef ETH_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) +#define PRINTF(fmt,args...) printf (fmt ,##args) #else #define PRINTF(fmt,args...) #endif -static struct rx_desc_3com *rx_ring; /* RX descriptor ring */ -static struct tx_desc_3com *tx_ring; /* TX descriptor ring */ -static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN];/* storage for the incoming messages */ -static int rx_next = 0; /* RX descriptor ring pointer */ -static int tx_next = 0; /* TX descriptor ring pointer */ +static struct rx_desc_3com *rx_ring; /* RX descriptor ring */ +static struct tx_desc_3com *tx_ring; /* TX descriptor ring */ +static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN]; /* storage for the incoming messages */ +static int rx_next = 0; /* RX descriptor ring pointer */ +static int tx_next = 0; /* TX descriptor ring pointer */ static int tx_threshold; static void init_rx_ring(struct eth_device* dev); @@ -369,163 +369,171 @@ static int issue_and_wait(struct eth_device* dev, int command) return 0; } -/* Determine network media type and set up 3com accordingly */ +/* Determine network media type and set up 3com accordingly */ /* I think I'm going to start with something known first like 10baseT */ -static int auto_negotiate (struct eth_device *dev) +static int auto_negotiate(struct eth_device* dev) { - int i; + int i; - EL3WINDOW (dev, 1); + EL3WINDOW(dev, 1); - /* Wait for Auto negotiation to complete */ - for (i = 0; i <= 1000; i++) { - if (ETH_INW (dev, 2) & 0x04) - break; - udelay (100); + /* Wait for Auto negotiation to complete */ + for (i = 0; i <= 1000; i++) + { + if (ETH_INW(dev, 2) & 0x04) + break; + udelay(100); - if (i == 1000) { - PRINTF ("Error: Auto negotiation failed\n"); - return 0; - } + if (i == 1000) + { + PRINTF("Error: Auto negotiation failed\n"); + return 0; } + } - return 1; + return 1; } -void eth_interrupt (struct eth_device *dev) +void eth_interrupt(struct eth_device *dev) { - u16 status = ETH_STATUS (dev); + u16 status = ETH_STATUS(dev); - printf ("eth0: status = 0x%04x\n", status); + printf("eth0: status = 0x%04x\n", status); - if (!(status & IntLatch)) - return; + if (!(status & IntLatch)) + return; - if (status & (1 << 6)) { - ETH_CMD (dev, AckIntr | (1 << 6)); - printf ("Acknowledged Interrupt command\n"); - } + if (status & (1<<6)) + { + ETH_CMD(dev, AckIntr | (1<<6)); + printf("Acknowledged Interrupt command\n"); + } - if (status & DownComplete) { - ETH_CMD (dev, AckIntr | DownComplete); - printf ("Acknowledged DownComplete\n"); - } + if (status & DownComplete) + { + ETH_CMD(dev, AckIntr | DownComplete); + printf("Acknowledged DownComplete\n"); + } - if (status & UpComplete) { - ETH_CMD (dev, AckIntr | UpComplete); - printf ("Acknowledged UpComplete\n"); - } + if (status & UpComplete) + { + ETH_CMD(dev, AckIntr | UpComplete); + printf("Acknowledged UpComplete\n"); + } - ETH_CMD (dev, AckIntr | IntLatch); - printf ("Acknowledged IntLatch\n"); + ETH_CMD(dev, AckIntr | IntLatch); + printf("Acknowledged IntLatch\n"); } -int eth_3com_initialize (bd_t * bis) +int eth_3com_initialize(bd_t *bis) { u32 eth_iobase = 0, status; int card_number = 0, ret; - struct eth_device *dev; + struct eth_device* dev; pci_dev_t devno; char *s; - s = getenv ("3com_base"); + s = getenv("3com_base"); /* Find ethernet controller on the PCI bus */ - if ((devno = - pci_find_device (PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, - 0)) < 0) { - PRINTF ("Error: Cannot find the ethernet device on the PCI bus\n"); + if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0) + { + PRINTF("Error: Cannot find the ethernet device on the PCI bus\n"); goto Done; } - if (s) { - unsigned long base = atoi (s); - - pci_write_config_dword (devno, PCI_BASE_ADDRESS_0, - base | 0x01); + if (s) + { + unsigned long base = atoi(s); + pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01); } - ret = pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, ð_iobase); + ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, ð_iobase); eth_iobase &= ~0xf; - PRINTF ("eth: 3Com Found at Address: 0x%x\n", eth_iobase); + PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase); - pci_write_config_dword (devno, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); + pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - /* Check if I/O accesses and Bus Mastering are enabled */ + /* Check if I/O accesses and Bus Mastering are enabled */ - ret = pci_read_config_dword (devno, PCI_COMMAND, &status); + ret = pci_read_config_dword(devno, PCI_COMMAND, &status); - if (!(status & PCI_COMMAND_IO)) { - printf ("Error: Cannot enable IO access.\n"); + if (!(status & PCI_COMMAND_IO)) + { + printf("Error: Cannot enable IO access.\n"); goto Done; } - if (!(status & PCI_COMMAND_MEMORY)) { - printf ("Error: Cannot enable MEMORY access.\n"); + if (!(status & PCI_COMMAND_MEMORY)) + { + printf("Error: Cannot enable MEMORY access.\n"); goto Done; } - if (!(status & PCI_COMMAND_MASTER)) { - printf ("Error: Cannot enable Bus Mastering.\n"); + if (!(status & PCI_COMMAND_MASTER)) + { + printf("Error: Cannot enable Bus Mastering.\n"); goto Done; } - dev = (struct eth_device *) malloc (sizeof (*dev)); /*struct eth_device)); */ + dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */ - sprintf (dev->name, "3Com 3c920c#%d", card_number); + sprintf(dev->name, "3Com 3c920c#%d", card_number); dev->iobase = eth_iobase; - dev->priv = (void *) devno; - dev->init = eth_3com_init; - dev->halt = eth_3com_halt; - dev->send = eth_3com_send; - dev->recv = eth_3com_recv; + dev->priv = (void*) devno; + dev->init = eth_3com_init; + dev->halt = eth_3com_halt; + dev->send = eth_3com_send; + dev->recv = eth_3com_recv; - eth_register (dev); + eth_register(dev); -/* { */ -/* char interrupt; */ -/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */ -/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */ +/* { */ +/* char interrupt; */ +/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */ +/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */ -/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */ -/* irq_install_handler(interrupt, eth_interrupt, dev); */ -/* } */ +/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */ +/* irq_install_handler(interrupt, eth_interrupt, dev); */ +/* } */ card_number++; /* Set the latency timer for value */ - s = getenv ("3com_latency"); - if (s) { - ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER, - (unsigned char) atoi (s)); - } else - ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x0a); + s = getenv("3com_latency"); + if (s) + { + ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s)); + } + else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a); - read_hw_addr (dev, bis); /* get the MAC address from Window 2 */ + read_hw_addr(dev, bis); /* get the MAC address from Window 2*/ /* Reset the ethernet controller */ PRINTF ("Issuing reset command....\n"); - if (!issue_and_wait (dev, TotalReset)) { - printf ("Error: Cannot reset ethernet controller.\n"); + if (!issue_and_wait(dev, TotalReset)) + { + printf("Error: Cannot reset ethernet controller.\n"); goto Done; - } else + } + else PRINTF ("Ethernet controller reset.\n"); /* allocate memory for rx and tx rings */ - if (!(rx_ring = memalign (sizeof (struct rx_desc_3com) * NUM_RX_DESC, 16))) { + if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16))) + { PRINTF ("Cannot allocate memory for RX_RING.....\n"); goto Done; } - if (!(tx_ring = memalign (sizeof (struct tx_desc_3com) * NUM_TX_DESC, 16))) { + if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16))) + { PRINTF ("Cannot allocate memory for TX_RING.....\n"); goto Done; } @@ -535,208 +543,219 @@ Done: } -static int eth_3com_init (struct eth_device *dev, bd_t * bis) +static int eth_3com_init(struct eth_device* dev, bd_t *bis) { int i, status = 0; int tx_cur, loop; u16 status_enable, intr_enable; struct descriptor *ias_cmd; - /* Determine what type of network the machine is connected to */ - /* presently drops the connect to 10Mbps */ + /* Determine what type of network the machine is connected to */ + /* presently drops the connect to 10Mbps */ - if (!auto_negotiate (dev)) { - printf ("Error: Cannot determine network media.\n"); + if (!auto_negotiate(dev)) + { + printf("Error: Cannot determine network media.\n"); goto Done; } - issue_and_wait (dev, TxReset); - issue_and_wait (dev, RxReset | 0x04); + issue_and_wait(dev, TxReset); + issue_and_wait(dev, RxReset|0x04); /* Switch to register set 7 for normal use. */ - EL3WINDOW (dev, 7); + EL3WINDOW(dev, 7); /* Initialize Rx and Tx rings */ - init_rx_ring (dev); - purge_tx_ring (dev); + init_rx_ring(dev); + purge_tx_ring(dev); - ETH_CMD (dev, SetRxFilter | RxStation | RxBroadcast | RxProm); + ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm); - issue_and_wait (dev, SetTxStart | 0x07ff); + issue_and_wait(dev,SetTxStart|0x07ff); /* Below sets which indication bits to be seen. */ - status_enable = - SetStatusEnb | HostError | DownComplete | UpComplete | (1 << - 6); - ETH_CMD (dev, status_enable); + status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6); + ETH_CMD(dev, status_enable); /* Below sets no bits are to cause an interrupt since this is just polling */ - intr_enable = SetIntrEnb; + intr_enable = SetIntrEnb; /* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */ - ETH_CMD (dev, intr_enable); - ETH_OUTB (dev, 127, UpPoll); + ETH_CMD(dev, intr_enable); + ETH_OUTB(dev, 127, UpPoll); /* Ack all pending events, and set active indicator mask */ - ETH_CMD (dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq); - ETH_CMD (dev, intr_enable); + ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq); + ETH_CMD(dev, intr_enable); /* Tell the adapter where the RX ring is located */ - issue_and_wait (dev, UpStall); /* Stall and set the UplistPtr */ - ETH_OUTL (dev, (u32) & rx_ring[rx_next], UpListPtr); - ETH_CMD (dev, RxEnable); /* Enable the receiver. */ - issue_and_wait (dev, UpUnstall); + issue_and_wait(dev,UpStall); /* Stall and set the UplistPtr */ + ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr); + ETH_CMD(dev, RxEnable); /* Enable the receiver. */ + issue_and_wait(dev,UpUnstall); /* Send the Individual Address Setup frame */ - tx_cur = tx_next; - tx_next = ((tx_next + 1) % NUM_TX_DESC); + tx_cur = tx_next; + tx_next = ((tx_next+1) % NUM_TX_DESC); - ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; - ias_cmd->status = cpu_to_le32 (1 << 31); /* set DnIndicate bit. */ - ias_cmd->next = 0; - ias_cmd->addr = cpu_to_le32 ((u32) & bis->bi_enetaddr[0]); - ias_cmd->length = cpu_to_le32 (6 | LAST_FRAG); + ias_cmd = (struct descriptor *)&tx_ring[tx_cur]; + ias_cmd->status = cpu_to_le32(1<<31); /* set DnIndicate bit. */ + ias_cmd->next = 0; + ias_cmd->addr = cpu_to_le32((u32)&bis->bi_enetaddr[0]); + ias_cmd->length = cpu_to_le32(6 | LAST_FRAG); /* Tell the adapter where the TX ring is located */ - ETH_CMD (dev, TxEnable); /* Enable transmitter. */ - issue_and_wait (dev, DownStall); /* Stall and set the DownListPtr. */ - ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr); - issue_and_wait (dev, DownUnstall); - for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) { - if (i >= TOUT_LOOP) { - PRINTF ("TX Ring status (Init): 0x%4x\n", - le32_to_cpu (tx_ring[tx_cur].status)); - PRINTF ("ETH_STATUS: 0x%x\n", ETH_STATUS (dev)); + ETH_CMD(dev, TxEnable); /* Enable transmitter. */ + issue_and_wait(dev, DownStall); /* Stall and set the DownListPtr. */ + ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr); + issue_and_wait(dev, DownUnstall); + for (i=0; !(ETH_STATUS(dev) & DownComplete); i++) + { + if (i >= TOUT_LOOP) + { + PRINTF("TX Ring status (Init): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status)); + PRINTF("ETH_STATUS: 0x%x\n", ETH_STATUS(dev)); goto Done; } } - if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */ - ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */ - issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */ - ETH_OUTL (dev, 0, DownListPtr); - issue_and_wait (dev, DownUnstall); + if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */ + { + ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */ + issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */ + ETH_OUTL(dev, 0, DownListPtr); + issue_and_wait(dev, DownUnstall); } status = 1; + Done: return status; } -int eth_3com_send (struct eth_device *dev, volatile void *packet, int length) +int eth_3com_send(struct eth_device* dev, volatile void *packet, int length) { int i, status = 0; int tx_cur; - if (length <= 0) { - PRINTF ("eth: bad packet size: %d\n", length); + if (length <= 0) + { + PRINTF("eth: bad packet size: %d\n", length); goto Done; } - tx_cur = tx_next; - tx_next = (tx_next + 1) % NUM_TX_DESC; + tx_cur = tx_next; + tx_next = (tx_next+1) % NUM_TX_DESC; - tx_ring[tx_cur].status = cpu_to_le32 (1 << 31); /* set DnIndicate bit */ - tx_ring[tx_cur].next = 0; - tx_ring[tx_cur].addr = cpu_to_le32 (((u32) packet)); - tx_ring[tx_cur].length = cpu_to_le32 (length | LAST_FRAG); + tx_ring[tx_cur].status = cpu_to_le32(1<<31); /* set DnIndicate bit */ + tx_ring[tx_cur].next = 0; + tx_ring[tx_cur].addr = cpu_to_le32(((u32) packet)); + tx_ring[tx_cur].length = cpu_to_le32(length | LAST_FRAG); /* Send the packet */ - issue_and_wait (dev, DownStall); /* stall and set the DownListPtr */ - ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr); - issue_and_wait (dev, DownUnstall); + issue_and_wait(dev, DownStall); /* stall and set the DownListPtr */ + ETH_OUTL(dev, (u32) &tx_ring[tx_cur], DownListPtr); + issue_and_wait(dev, DownUnstall); - for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) { - if (i >= TOUT_LOOP) { - PRINTF ("TX Ring status (send): 0x%4x\n", - le32_to_cpu (tx_ring[tx_cur].status)); + for (i=0; !(ETH_STATUS(dev) & DownComplete); i++) + { + if (i >= TOUT_LOOP) + { + PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status)); goto Done; } } - if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */ - ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */ - issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */ - ETH_OUTL (dev, 0, DownListPtr); - issue_and_wait (dev, DownUnstall); + if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */ + { + ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */ + issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */ + ETH_OUTL(dev, 0, DownListPtr); + issue_and_wait(dev, DownUnstall); } - status = 1; -Done: + status=1; + Done: return status; } -void PrintPacket (uchar * packet, int length) +void PrintPacket (uchar *packet, int length) { - int loop; - uchar *ptr; +int loop; +uchar *ptr; printf ("Printing packet of length %x.\n\n", length); ptr = packet; - for (loop = 1; loop <= length; loop++) { + for (loop = 1; loop <= length; loop++) + { printf ("%2x ", *ptr++); - if ((loop % 40) == 0) + if ((loop % 40)== 0) printf ("\n"); } } -int eth_3com_recv (struct eth_device *dev) +int eth_3com_recv(struct eth_device* dev) { u16 stat = 0; u32 status; int rx_prev, length = 0; - while (!(ETH_STATUS (dev) & UpComplete)) /* wait on receipt of packet */ + while (!(ETH_STATUS(dev) & UpComplete)) /* wait on receipt of packet */ ; - status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */ + status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */ - while (status & (1 << 15)) { + while (status & (1<<15)) + { /* A packet has been received */ - if (status & (1 << 15)) { + if (status & (1<<15)) + { /* A valid frame received */ - length = le32_to_cpu (rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */ + length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */ /* Pass the packet up to the protocol layers */ - NetReceive ((uchar *) - le32_to_cpu (rx_ring[rx_next].addr), - length); - rx_ring[rx_next].status = 0; /* clear the status word */ - ETH_CMD (dev, AckIntr | UpComplete); - issue_and_wait (dev, UpUnstall); - } else if (stat & HostError) { + NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length); + rx_ring[rx_next].status = 0; /* clear the status word */ + ETH_CMD(dev, AckIntr | UpComplete); + issue_and_wait(dev, UpUnstall); + } + else + if (stat & HostError) + { /* There was an error */ - printf ("Rx error status: 0x%4x\n", stat); - init_rx_ring (dev); + printf("Rx error status: 0x%4x\n", stat); + init_rx_ring(dev); goto Done; } rx_prev = rx_next; rx_next = (rx_next + 1) % NUM_RX_DESC; - stat = ETH_STATUS (dev); /* register status */ - status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */ + stat = ETH_STATUS(dev); /* register status */ + status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */ } + Done: return length; } -void eth_3com_halt (struct eth_device *dev) +void eth_3com_halt(struct eth_device* dev) { - if (!(dev->iobase)) { + if (!(dev->iobase)) + { goto Done; } - issue_and_wait (dev, DownStall); /* shut down transmit and receive */ - issue_and_wait (dev, UpStall); - issue_and_wait (dev, RxDisable); - issue_and_wait (dev, TxDisable); + issue_and_wait(dev, DownStall); /* shut down transmit and receive */ + issue_and_wait(dev, UpStall); + issue_and_wait(dev, RxDisable); + issue_and_wait(dev, TxDisable); /* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */ /* free(rx_ring); */ @@ -745,41 +764,41 @@ Done: return; } -static void init_rx_ring (struct eth_device *dev) +static void init_rx_ring(struct eth_device* dev) { int i; - PRINTF ("Initializing rx_ring. rx_buffer = %p\n", rx_buffer); - issue_and_wait (dev, UpStall); + PRINTF("Initializing rx_ring. rx_buffer = %p\n", rx_buffer); + issue_and_wait(dev, UpStall); - for (i = 0; i < NUM_RX_DESC; i++) { - rx_ring[i].next = - cpu_to_le32 (((u32) & - rx_ring[(i + 1) % NUM_RX_DESC])); - rx_ring[i].status = 0; - rx_ring[i].addr = cpu_to_le32 (((u32) & rx_buffer[i][0])); - rx_ring[i].length = cpu_to_le32 (PKTSIZE_ALIGN | LAST_FRAG); + for (i = 0; i < NUM_RX_DESC; i++) + { + rx_ring[i].next = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC])); + rx_ring[i].status = 0; + rx_ring[i].addr = cpu_to_le32(((u32) &rx_buffer[i][0])); + rx_ring[i].length = cpu_to_le32(PKTSIZE_ALIGN | LAST_FRAG); } rx_next = 0; } -static void purge_tx_ring (struct eth_device *dev) +static void purge_tx_ring(struct eth_device* dev) { int i; - PRINTF ("Purging tx_ring.\n"); + PRINTF("Purging tx_ring.\n"); - tx_next = 0; + tx_next = 0; - for (i = 0; i < NUM_TX_DESC; i++) { - tx_ring[i].next = 0; - tx_ring[i].status = 0; - tx_ring[i].addr = 0; - tx_ring[i].length = 0; + for (i = 0; i < NUM_TX_DESC; i++) + { + tx_ring[i].next = 0; + tx_ring[i].status = 0; + tx_ring[i].addr = 0; + tx_ring[i].length = 0; } } -static void read_hw_addr (struct eth_device *dev, bd_t * bis) +static void read_hw_addr(struct eth_device* dev, bd_t *bis) { u8 hw_addr[ETH_ALEN]; unsigned int eeprom[0x40]; @@ -788,77 +807,77 @@ static void read_hw_addr (struct eth_device *dev, bd_t * bis) /* Read the station address from the EEPROM. */ - EL3WINDOW (dev, 0); - for (i = 0; i < 0x40; i++) { - ETH_OUTW (dev, EEPROM_Read + i, Wn0EepromCmd); + EL3WINDOW(dev, 0); + for (i = 0; i < 0x40; i++) + { + ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd); /* Pause for at least 162 us. for the read to take place. */ - for (timer = 10; timer >= 0; timer--) { - udelay (162); - if ((ETH_INW (dev, Wn0EepromCmd) & 0x8000) == 0) + for (timer = 10; timer >= 0; timer--) + { + udelay(162); + if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0) break; } - eeprom[i] = ETH_INW (dev, Wn0EepromData); + eeprom[i] = ETH_INW(dev, Wn0EepromData); } /* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */ for (i = 0; i < 0x21; i++) - checksum ^= eeprom[i]; + checksum ^= eeprom[i]; checksum = (checksum ^ (checksum >> 8)) & 0xff; if (checksum != 0xbb) - printf (" *** INVALID EEPROM CHECKSUM %4.4x *** \n", - checksum); + printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum); - for (i = 0, j = 0; i < 3; i++) { - hw_addr[j++] = (u8) ((eeprom[i + 10] >> 8) & 0xff); - hw_addr[j++] = (u8) (eeprom[i + 10] & 0xff); + for (i = 0, j = 0; i < 3; i++) + { + hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff); + hw_addr[j++] = (u8)(eeprom[i+10] & 0xff); } /* MAC Address is in window 2, write value from EEPROM to window 2 */ - EL3WINDOW (dev, 2); + EL3WINDOW(dev, 2); for (i = 0; i < 6; i++) - ETH_OUTB (dev, hw_addr[i], i); + ETH_OUTB(dev, hw_addr[i], i); - for (j = 0; j < ETH_ALEN; j += 2) { - hw_addr[j] = (u8) (ETH_INW (dev, j) & 0xff); - hw_addr[j + 1] = (u8) ((ETH_INW (dev, j) >> 8) & 0xff); + for (j = 0; j < ETH_ALEN; j+=2) + { + hw_addr[j] = (u8)(ETH_INW(dev, j) & 0xff); + hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff); } - for (i = 0; i < ETH_ALEN; i++) { - if (hw_addr[i] != bis->bi_enetaddr[i]) { -/* printf("Warning: HW address don't match:\n"); */ -/* printf("Address in 3Com Window 2 is " */ -/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ -/* hw_addr[0], hw_addr[1], hw_addr[2], */ -/* hw_addr[3], hw_addr[4], hw_addr[5]); */ -/* printf("Address used by U-Boot is " */ -/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ -/* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */ -/* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */ -/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */ -/* goto Done; */ - char buffer[256]; + for (i=0;ibi_enetaddr[i]) + { +/* printf("Warning: HW address don't match:\n"); */ +/* printf("Address in 3Com Window 2 is " */ +/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ +/* hw_addr[0], hw_addr[1], hw_addr[2], */ +/* hw_addr[3], hw_addr[4], hw_addr[5]); */ +/* printf("Address used by U-Boot is " */ +/* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ +/* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */ +/* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */ +/* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */ +/* goto Done; */ + char buffer[256]; + if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 && + bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 && + bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0) + { - if (bis->bi_enetaddr[0] == 0 - && bis->bi_enetaddr[1] == 0 - && bis->bi_enetaddr[2] == 0 - && bis->bi_enetaddr[3] == 0 - && bis->bi_enetaddr[4] == 0 - && bis->bi_enetaddr[5] == 0) { - - sprintf (buffer, - "%02X:%02X:%02X:%02X:%02X:%02X", - hw_addr[0], hw_addr[1], hw_addr[2], - hw_addr[3], hw_addr[4], hw_addr[5]); - setenv ("ethaddr", buffer); - } + sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X", + hw_addr[0], hw_addr[1], hw_addr[2], + hw_addr[3], hw_addr[4], hw_addr[5]); + setenv("ethaddr", buffer); + } } } - for (i = 0; i < ETH_ALEN; i++) - dev->enetaddr[i] = hw_addr[i]; + for(i=0; ienetaddr[i] = hw_addr[i]; Done: return; diff --git a/board/MAI/AmigaOneG3SE/interrupts.c b/board/MAI/AmigaOneG3SE/interrupts.c index 86b44150d..5b314a8b7 100644 --- a/board/MAI/AmigaOneG3SE/interrupts.c +++ b/board/MAI/AmigaOneG3SE/interrupts.c @@ -176,9 +176,9 @@ external_interrupt(struct pt_regs *regs) else { PRINTF ("\nBogus External Interrupt IRQ %d\n", irq); /* - * turn off the bogus interrupt, otherwise it - * might repeat forever - */ + * turn off the bogus interrupt, otherwise it + * might repeat forever + */ unmask = 0; } diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.c b/board/MAI/AmigaOneG3SE/ps2kbd.c index 724a44db7..cf4f4d0e3 100644 --- a/board/MAI/AmigaOneG3SE/ps2kbd.c +++ b/board/MAI/AmigaOneG3SE/ps2kbd.c @@ -58,7 +58,7 @@ void i8259_unmask_irq(unsigned int irq); #define KBD_STAT_KOBF 0x01 #define KBD_STAT_IBF 0x02 #define KBD_STAT_SYS 0x04 -#define KBD_STAT_CD 0x08 +#define KBD_STAT_CD 0x08 #define KBD_STAT_LOCK 0x10 #define KBD_STAT_MOBF 0x20 #define KBD_STAT_TI_OUT 0x40 @@ -71,50 +71,50 @@ void i8259_unmask_irq(unsigned int irq); * Keyboard Controller Commands */ -#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ -#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ -#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ +#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ +#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ +#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ -#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ -#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ -#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ -#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ -#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ -#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ +#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ +#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ +#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ +#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ +#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ +#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if initiated by the auxiliary device */ -#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ +#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ /* * Keyboard Commands */ -#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ -#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ -#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ -#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */ -#define KBD_CMD_RESET 0xFF /* Reset */ +#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ +#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ +#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ +#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */ +#define KBD_CMD_RESET 0xFF /* Reset */ /* * Keyboard Replies */ -#define KBD_REPLY_POR 0xAA /* Power on reset */ -#define KBD_REPLY_ACK 0xFA /* Command ACK */ -#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ +#define KBD_REPLY_POR 0xAA /* Power on reset */ +#define KBD_REPLY_ACK 0xFA /* Command ACK */ +#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ /* * Status Register Bits */ -#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ -#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ -#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ -#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ -#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ -#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ -#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ -#define KBD_STAT_PERR 0x80 /* Parity error */ +#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ +#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ +#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ +#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ +#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ +#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ +#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ +#define KBD_STAT_PERR 0x80 /* Parity error */ #define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF) @@ -122,24 +122,24 @@ void i8259_unmask_irq(unsigned int irq); * Controller Mode Register Bits */ -#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ -#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ -#define KBD_MODE_SYS 0x04 /* The system flag (?) */ -#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ -#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ +#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ +#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ +#define KBD_MODE_SYS 0x04 /* The system flag (?) */ +#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ +#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ -#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ -#define KBD_MODE_RFU 0x80 +#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ +#define KBD_MODE_RFU 0x80 -#define KDB_DATA_PORT 0x60 +#define KDB_DATA_PORT 0x60 #define KDB_COMMAND_PORT 0x64 -#define LED_SCR 0x01 /* scroll lock led */ -#define LED_CAP 0x04 /* caps lock led */ -#define LED_NUM 0x02 /* num lock led */ +#define LED_SCR 0x01 /* scroll lock led */ +#define LED_CAP 0x04 /* caps lock led */ +#define LED_NUM 0x02 /* num lock led */ -#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ +#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ static volatile char kbd_buffer[KBD_BUFFER_LEN]; @@ -194,22 +194,21 @@ static unsigned char kbd_ctrl_xlate[] = { * Init ******************************************************************/ -int isa_kbd_init (void) +int isa_kbd_init(void) { - char *result; - - result = kbd_initialize (); - if (result != NULL) { - result = kbd_initialize (); + char* result; + result=kbd_initialize(); + if (result != NULL) + { + result = kbd_initialize(); } - if (result == NULL) { - printf ("AT Keyboard initialized\n"); - irq_install_handler (KBD_INTERRUPT, - (interrupt_handler_t *) kbd_interrupt, - NULL); + if(result==NULL) { + printf("AT Keyboard initialized\n"); + irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL); return (1); - } else { - printf ("%s\n", result); + } + else { + printf("%s\n",result); return (-1); } } @@ -226,20 +225,20 @@ int overwrite_console (void) int drv_isa_kbd_init (void) { int error; - device_t kbddev ; + device_t kbddev ; char *stdinname = getenv ("stdin"); - if(isa_kbd_init() == -1) + if(isa_kbd_init()==-1) return -1; - memset (&kbddev, 0, sizeof(kbddev)); - strcpy(kbddev.name, DEVNAME); - kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbddev.putc = NULL ; + memset (&kbddev, 0, sizeof(kbddev)); + strcpy(kbddev.name, DEVNAME); + kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + kbddev.putc = NULL ; kbddev.puts = NULL ; kbddev.getc = kbd_getc ; kbddev.tstc = kbd_testc ; - error = device_register (&kbddev); + error = device_register (&kbddev); if(error==0) { /* check if this is the standard input device */ if(strcmp(stdinname,DEVNAME)==0) { @@ -302,6 +301,7 @@ int kbd_getc(void) } + /* set LEDs */ void kbd_set_leds(void) @@ -322,139 +322,140 @@ void kbd_set_leds(void) kbd_send_data(leds); } -void handle_keyboard_event (unsigned char scancode) + +void handle_keyboard_event(unsigned char scancode) { unsigned char keycode; /* Convert scancode to keycode */ - PRINTF ("scancode %x\n", scancode); - if (scancode == 0xe0) { - e0 = 1; /* special charakters */ + PRINTF("scancode %x\n",scancode); + if(scancode==0xe0) { + e0=1; /* special charakters */ return; } - if (e0 == 1) { - e0 = 0; /* delete flag */ - if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */ - ((scancode & 0x7F) == 0x1D) || /* the right alt key */ - ((scancode & 0x7F) == 0x35) || /* the right '/' key */ - ((scancode & 0x7F) == 0x1C) || /* the right enter key */ - ((scancode) == 0x48) || /* arrow up */ - ((scancode) == 0x50) || /* arrow down */ - ((scancode) == 0x4b) || /* arrow left */ - ((scancode) == 0x4d))) - /* arrow right */ + if(e0==1) { + e0=0; /* delete flag */ + if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */ + ((scancode&0x7F)==0x1D)|| /* the right alt key */ + ((scancode&0x7F)==0x35)|| /* the right '/' key */ + ((scancode&0x7F)==0x1C)|| /* the right enter key */ + ((scancode)==0x48)|| /* arrow up */ + ((scancode)==0x50)|| /* arrow down */ + ((scancode)==0x4b)|| /* arrow left */ + ((scancode)==0x4d))) /* arrow right */ /* we swallow unknown e0 codes */ return; } /* special cntrl keys */ - switch (scancode) { + switch(scancode) + { case 0x48: - kbd_put_queue (27); - kbd_put_queue (91); - kbd_put_queue ('A'); - return; + kbd_put_queue(27); + kbd_put_queue(91); + kbd_put_queue('A'); + return; case 0x50: - kbd_put_queue (27); - kbd_put_queue (91); - kbd_put_queue ('B'); - return; + kbd_put_queue(27); + kbd_put_queue(91); + kbd_put_queue('B'); + return; case 0x4b: - kbd_put_queue (27); - kbd_put_queue (91); - kbd_put_queue ('D'); - return; + kbd_put_queue(27); + kbd_put_queue(91); + kbd_put_queue('D'); + return; case 0x4D: - kbd_put_queue (27); - kbd_put_queue (91); - kbd_put_queue ('C'); - return; - case 0x58: /* F12 key */ - if (ctrl == 1) { - extern int console_changed; - - setenv ("stdin", DEVNAME); - setenv ("stdout", "vga"); - console_changed = 1; - } - return; + kbd_put_queue(27); + kbd_put_queue(91); + kbd_put_queue('C'); + return; + case 0x58: /* F12 key */ + if (ctrl == 1) + { + extern int console_changed; + setenv("stdin", DEVNAME); + setenv("stdout", "vga"); + console_changed = 1; + } + return; case 0x2A: - case 0x36: /* shift pressed */ - shift = 1; - return; /* do nothing else */ - case 0xAA: - case 0xB6: /* shift released */ - shift = 0; - return; /* do nothing else */ - case 0x38: /* alt pressed */ - alt = 1; - return; /* do nothing else */ - case 0xB8: /* alt released */ - alt = 0; - return; /* do nothing else */ - case 0x1d: /* ctrl pressed */ - ctrl = 1; - return; /* do nothing else */ - case 0x9d: /* ctrl released */ - ctrl = 0; - return; /* do nothing else */ - case 0x46: /* scrollock pressed */ - scroll_lock = ~scroll_lock; - kbd_set_leds (); - return; /* do nothing else */ - case 0x3A: /* capslock pressed */ - caps_lock = ~caps_lock; - kbd_set_leds (); - return; - case 0x45: /* numlock pressed */ - num_lock = ~num_lock; - kbd_set_leds (); - return; - case 0xC6: /* scroll lock released */ - case 0xC5: /* num lock released */ - case 0xBA: /* caps lock released */ - return; /* just swallow */ + case 0x36: /* shift pressed */ + shift=1; + return; /* do nothing else */ + case 0xAA: + case 0xB6: /* shift released */ + shift=0; + return; /* do nothing else */ + case 0x38: /* alt pressed */ + alt=1; + return; /* do nothing else */ + case 0xB8: /* alt released */ + alt=0; + return; /* do nothing else */ + case 0x1d: /* ctrl pressed */ + ctrl=1; + return; /* do nothing else */ + case 0x9d: /* ctrl released */ + ctrl=0; + return; /* do nothing else */ + case 0x46: /* scrollock pressed */ + scroll_lock=~scroll_lock; + kbd_set_leds(); + return; /* do nothing else */ + case 0x3A: /* capslock pressed */ + caps_lock=~caps_lock; + kbd_set_leds(); + return; + case 0x45: /* numlock pressed */ + num_lock=~num_lock; + kbd_set_leds(); + return; + case 0xC6: /* scroll lock released */ + case 0xC5: /* num lock released */ + case 0xBA: /* caps lock released */ + return; /* just swallow */ } - if ((scancode & 0x80) == 0x80) /* key released */ + if((scancode&0x80)==0x80) /* key released */ return; /* now, decide which table we need */ - if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown scancode %X\n", scancode); - return; /* swallow it */ + if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow it */ } /* setup plain code first */ - keycode = kbd_plain_xlate[scancode]; - if (caps_lock == 1) { /* caps_lock is pressed, overwrite plain code */ - if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown caps-locked scancode %X\n", scancode); - return; /* swallow it */ + keycode=kbd_plain_xlate[scancode]; + if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown caps-locked scancode %X\n",scancode); + return; /* swallow it */ } - keycode = kbd_shift_xlate[scancode]; - if (keycode < 'A') { /* we only want the alphas capital */ - keycode = kbd_plain_xlate[scancode]; + keycode=kbd_shift_xlate[scancode]; + if(keycode<'A') { /* we only want the alphas capital */ + keycode=kbd_plain_xlate[scancode]; } } - if (shift == 1) { /* shift overwrites caps_lock */ - if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown shifted scancode %X\n", scancode); - return; /* swallow it */ + if(shift==1) { /* shift overwrites caps_lock */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown shifted scancode %X\n",scancode); + return; /* swallow it */ } - keycode = kbd_shift_xlate[scancode]; + keycode=kbd_shift_xlate[scancode]; } - if (ctrl == 1) { /* ctrl overwrites caps_lock and shift */ - if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown ctrl scancode %X\n", scancode); - return; /* swallow it */ + if(ctrl==1) { /* ctrl overwrites caps_lock and shift */ + if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown ctrl scancode %X\n",scancode); + return; /* swallow it */ } - keycode = kbd_ctrl_xlate[scancode]; + keycode=kbd_ctrl_xlate[scancode]; } /* check if valid keycode */ - if (keycode == 0xff) { - PRINTF ("unkown scancode %X\n", scancode); - return; /* swallow unknown codes */ + if(keycode==0xff) { + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow unknown codes */ } - kbd_put_queue (keycode); - PRINTF ("%x\n", keycode); + kbd_put_queue(keycode); + PRINTF("%x\n",keycode); } /* @@ -462,31 +463,34 @@ void handle_keyboard_event (unsigned char scancode) * appropriate action. * */ -unsigned char handle_kbd_event (void) +unsigned char handle_kbd_event(void) { - unsigned char status = kbd_read_status (); + unsigned char status = kbd_read_status(); unsigned int work = 10000; while ((--work > 0) && (status & KBD_STAT_OBF)) { unsigned char scancode; - scancode = kbd_read_input (); + scancode = kbd_read_input(); /* Error bytes must be ignored to make the Synaptics touchpads compaq use work */ /* Ignore error bytes */ - if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) { - if (status & KBD_STAT_MOUSE_OBF); /* not supported: handle_mouse_event(scancode); */ + if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) + { + if (status & KBD_STAT_MOUSE_OBF) + ; /* not supported: handle_mouse_event(scancode); */ else - handle_keyboard_event (scancode); + handle_keyboard_event(scancode); } - status = kbd_read_status (); + status = kbd_read_status(); } if (!work) - PRINTF ("pc_keyb: controller jammed (0x%02X).\n", status); + PRINTF("pc_keyb: controller jammed (0x%02X).\n", status); return status; } + /****************************************************************************** * Lowlevel Part of keyboard section */ @@ -515,7 +519,7 @@ int kbd_read_data(void) int val; unsigned char status; - val = -1; + val=-1; status = kbd_read_status(); if (status & KBD_STAT_OBF) { val = kbd_read_input(); @@ -525,91 +529,90 @@ int kbd_read_data(void) return val; } -int kbd_wait_for_input (void) +int kbd_wait_for_input(void) { unsigned long timeout; int val; timeout = KBD_TIMEOUT; - val = kbd_read_data (); - while (val < 0) { - if (timeout-- == 0) + val=kbd_read_data(); + while(val < 0) + { + if(timeout--==0) return -1; - udelay (1000); - val = kbd_read_data (); + udelay(1000); + val=kbd_read_data(); } return val; } -int kb_wait (void) +int kb_wait(void) { unsigned long timeout = KBC_TIMEOUT * 10; do { - unsigned char status = handle_kbd_event (); - + unsigned char status = handle_kbd_event(); if (!(status & KBD_STAT_IBF)) - return 0; /* ok */ - udelay (1000); + return 0; /* ok */ + udelay(1000); timeout--; } while (timeout); return 1; } -void kbd_write_command_w (int data) +void kbd_write_command_w(int data) { - if (kb_wait ()) - PRINTF ("timeout in kbd_write_command_w\n"); - kbd_write_command (data); + if(kb_wait()) + PRINTF("timeout in kbd_write_command_w\n"); + kbd_write_command(data); } -void kbd_write_output_w (int data) +void kbd_write_output_w(int data) { - if (kb_wait ()) - PRINTF ("timeout in kbd_write_output_w\n"); - kbd_write_output (data); + if(kb_wait()) + PRINTF("timeout in kbd_write_output_w\n"); + kbd_write_output(data); } -void kbd_send_data (unsigned char data) +void kbd_send_data(unsigned char data) { unsigned char status; - - i8259_mask_irq (KBD_INTERRUPT); /* disable interrupt */ - kbd_write_output_w (data); - status = kbd_wait_for_input (); + i8259_mask_irq(KBD_INTERRUPT); /* disable interrupt */ + kbd_write_output_w(data); + status = kbd_wait_for_input(); if (status == KBD_REPLY_ACK) - i8259_unmask_irq (KBD_INTERRUPT); /* enable interrupt */ + i8259_unmask_irq(KBD_INTERRUPT); /* enable interrupt */ } -char *kbd_initialize (void) +char * kbd_initialize(void) { int status; - in_pointer = 0; /* delete in Buffer */ + in_pointer = 0; /* delete in Buffer */ out_pointer = 0; /* * Test the keyboard interface. * This seems to be the only way to get it going. * If the test is successful a x55 is placed in the input buffer. */ - kbd_write_command_w (KBD_CCMD_SELF_TEST); - if (kbd_wait_for_input () != 0x55) + kbd_write_command_w(KBD_CCMD_SELF_TEST); + if (kbd_wait_for_input() != 0x55) return "Kbd: failed self test"; /* * Perform a keyboard interface test. This causes the controller * to test the keyboard clock and data lines. The results of the * test are placed in the input buffer. */ - kbd_write_command_w (KBD_CCMD_KBD_TEST); - if (kbd_wait_for_input () != 0x00) + kbd_write_command_w(KBD_CCMD_KBD_TEST); + if (kbd_wait_for_input() != 0x00) return "Kbd: interface failed self test"; /* * Enable the keyboard by allowing the keyboard clock to run. */ - kbd_write_command_w (KBD_CCMD_KBD_ENABLE); - status = kbd_wait_for_input (); + kbd_write_command_w(KBD_CCMD_KBD_ENABLE); + status = kbd_wait_for_input(); /* * Reset keyboard. If the read times out * then the assumption is that no keyboard is @@ -619,16 +622,17 @@ char *kbd_initialize (void) * Set up to try again if the keyboard asks for RESEND. */ do { - kbd_write_output_w (KBD_CMD_RESET); - status = kbd_wait_for_input (); + kbd_write_output_w(KBD_CMD_RESET); + status = kbd_wait_for_input(); if (status == KBD_REPLY_ACK) break; - if (status != KBD_REPLY_RESEND) { - PRINTF ("status: %X\n", status); + if (status != KBD_REPLY_RESEND) + { + PRINTF("status: %X\n",status); return "Kbd: reset failed, no ACK"; } } while (1); - if (kbd_wait_for_input () != KBD_REPLY_POR) + if (kbd_wait_for_input() != KBD_REPLY_POR) return "Kbd: reset failed, no POR"; /* @@ -638,43 +642,44 @@ char *kbd_initialize (void) * Set up to try again if the keyboard asks for RESEND. */ do { - kbd_write_output_w (KBD_CMD_DISABLE); - status = kbd_wait_for_input (); + kbd_write_output_w(KBD_CMD_DISABLE); + status = kbd_wait_for_input(); if (status == KBD_REPLY_ACK) break; if (status != KBD_REPLY_RESEND) return "Kbd: disable keyboard: no ACK"; } while (1); - kbd_write_command_w (KBD_CCMD_WRITE_MODE); - kbd_write_output_w (KBD_MODE_KBD_INT - | KBD_MODE_SYS - | KBD_MODE_DISABLE_MOUSE | KBD_MODE_KCC); + kbd_write_command_w(KBD_CCMD_WRITE_MODE); + kbd_write_output_w(KBD_MODE_KBD_INT + | KBD_MODE_SYS + | KBD_MODE_DISABLE_MOUSE + | KBD_MODE_KCC); /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */ - kbd_write_command_w (KBD_CCMD_READ_MODE); - if (!(kbd_wait_for_input () & KBD_MODE_KCC)) { + kbd_write_command_w(KBD_CCMD_READ_MODE); + if (!(kbd_wait_for_input() & KBD_MODE_KCC)) { /* * If the controller does not support conversion, * Set the keyboard to scan-code set 1. */ - kbd_write_output_w (0xF0); - kbd_wait_for_input (); - kbd_write_output_w (0x01); - kbd_wait_for_input (); + kbd_write_output_w(0xF0); + kbd_wait_for_input(); + kbd_write_output_w(0x01); + kbd_wait_for_input(); } - kbd_write_output_w (KBD_CMD_ENABLE); - if (kbd_wait_for_input () != KBD_REPLY_ACK) + kbd_write_output_w(KBD_CMD_ENABLE); + if (kbd_wait_for_input() != KBD_REPLY_ACK) return "Kbd: enable keyboard: no ACK"; /* * Finally, set the typematic rate to maximum. */ - kbd_write_output_w (KBD_CMD_SET_RATE); - if (kbd_wait_for_input () != KBD_REPLY_ACK) + kbd_write_output_w(KBD_CMD_SET_RATE); + if (kbd_wait_for_input() != KBD_REPLY_ACK) return "Kbd: Set rate: no ACK"; - kbd_write_output_w (0x00); - if (kbd_wait_for_input () != KBD_REPLY_ACK) + kbd_write_output_w(0x00); + if (kbd_wait_for_input() != KBD_REPLY_ACK) return "Kbd: Set rate: no ACK"; return NULL; } diff --git a/board/MAI/AmigaOneG3SE/start.txt b/board/MAI/AmigaOneG3SE/start.txt index 2526ed24a..e4214622c 100644 --- a/board/MAI/AmigaOneG3SE/start.txt +++ b/board/MAI/AmigaOneG3SE/start.txt @@ -39,11 +39,11 @@ DIM0_TIM_CTL_0 = 0x737d737d (0xc9) /* DRAM timing control for dimm0 & dimm1; set wait one clock */ - /* cycle for next data access */ + /* cycle for next data access */ DIM2_TIM_CTL_0 = 0x737d737d (0xca) /* DRAM timing control for dimm2 & dimm3; set wait one clock */ - /* cycle for next data access */ + /* cycle for next data access */ DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB (0x90) /* set dimm0 bank0 for 128 MB */ diff --git a/board/MAI/AmigaOneG3SE/u-boot.lds b/board/MAI/AmigaOneG3SE/u-boot.lds index 7386ea7a2..b36b3cb45 100644 --- a/board/MAI/AmigaOneG3SE/u-boot.lds +++ b/board/MAI/AmigaOneG3SE/u-boot.lds @@ -29,6 +29,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -40,11 +41,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -127,7 +128,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.c b/board/MAI/AmigaOneG3SE/usb_uhci.c index 26cdcdf76..14e804308 100644 --- a/board/MAI/AmigaOneG3SE/usb_uhci.c +++ b/board/MAI/AmigaOneG3SE/usb_uhci.c @@ -518,11 +518,11 @@ void usb_check_int_chain(void) uhci_td_t *td,*prevtd; for(i=0;i<8;i++) { - prevtd = &td_int[i]; /* the first previous td is the skeleton td */ + prevtd=&td_int[i]; /* the first previous td is the skeleton td */ link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */ td=(uhci_td_t *)link; /* assign it */ /* all interrupt TDs are finally linked to the td_int[0]. - * so we process all until we find the td_int[0]. + * so we process all until we find the td_int[0]. * if int0 chain points to a QH, we're also done */ while(((i>0) && (link != (unsigned long)&td_int[0])) || @@ -595,7 +595,7 @@ int usb_lowlevel_init(void) busdevfunc=pci_find_device(USB_UHCI_VEND_ID,USB_UHCI_DEV_ID,0); /* get PCI Device ID */ - if(busdevfunc == -1) { + if(busdevfunc==-1) { printf("Error USB UHCI (%04X,%04X) not found\n",USB_UHCI_VEND_ID,USB_UHCI_DEV_ID); return -1; } @@ -642,12 +642,12 @@ int usb_lowlevel_init(void) */ int usb_lowlevel_stop(void) { - if(irqvec == -1) + if(irqvec==-1) return 1; irq_free_handler(irqvec); irq_free_handler(0); reset_hc(); - irqvec = -1; + irqvec=-1; return 0; } diff --git a/board/MAI/AmigaOneG3SE/via686.c b/board/MAI/AmigaOneG3SE/via686.c index 2427ce571..3606db82e 100644 --- a/board/MAI/AmigaOneG3SE/via686.c +++ b/board/MAI/AmigaOneG3SE/via686.c @@ -97,7 +97,7 @@ void via_isa_init(pci_dev_t dev, struct pci_config_table *table) pci_write_config_byte(dev, 0x80, 0); pci_write_config_byte(dev, 0x85, 0x01); -/* pci_write_config_byte(dev, 0x77, 0x00); */ +/* pci_write_config_byte(dev, 0x77, 0x00); */ } } @@ -212,7 +212,7 @@ void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_c } __asm (" .globl via_calibrate_time_base \n" - "via_calibrate_time_base: \n" + "via_calibrate_time_base: \n" " lis 9, 0xfe00 \n" " li 0, 0x00 \n" " mttbu 0 \n" @@ -262,9 +262,9 @@ void ide_led(uchar led, uchar status) /* unsigned char c = in_byte(0x92); */ /* if (!status) */ -/* out_byte(0x92, c | 0xC0); */ +/* out_byte(0x92, c | 0xC0); */ /* else */ -/* out_byte(0x92, c & ~0xC0); */ +/* out_byte(0x92, c & ~0xC0); */ } diff --git a/board/MAI/AmigaOneG3SE/video.c b/board/MAI/AmigaOneG3SE/video.c index fc27c6858..f6327f720 100644 --- a/board/MAI/AmigaOneG3SE/video.c +++ b/board/MAI/AmigaOneG3SE/video.c @@ -56,7 +56,6 @@ int video_rows(void); int video_cols(void); char *prompt_string = "=>"; -unsigned char video_get_attr(void); void video_set_color(unsigned char attr) { diff --git a/board/MAI/bios_emulator/bios.c b/board/MAI/bios_emulator/bios.c new file mode 100644 index 000000000..d51eb6469 --- /dev/null +++ b/board/MAI/bios_emulator/bios.c @@ -0,0 +1,335 @@ +/* + * Mostly done after the Scitech Bios emulation + * Written by Hans-Jörg Frieden + * Hyperion Entertainment + */ +#include "x86emu.h" +#include "glue.h" + +#undef DEBUG +#ifdef DEBUG +#define PRINTF(fmt, args...) printf(fmt, ## args) +#else +#define PRINTF(fmt, args...) +#endif + +#define BIOS_SEG 0xFFF0 +#define PCIBIOS_SUCCESSFUL 0 +#define PCIBIOS_DEVICE_NOT_FOUND 0x86 + +typedef unsigned char UBYTE; +typedef unsigned short UWORD; +typedef unsigned long ULONG; + +typedef char BYTE; +typedef short WORT; +typedef long LONG; + +static inline UBYTE read_byte(volatile UBYTE* from) +{ + int x; + asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (UBYTE)x; +} + +static inline void write_byte(volatile UBYTE *to, int x) +{ + asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static inline UWORD read_word_little(volatile UWORD *from) +{ + int x; + asm volatile ("lhbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m" (*from)); + return (UWORD)x; +} + +static inline UWORD read_word_big(volatile UWORD *from) +{ + int x; + asm volatile ("lhz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (UWORD)x; +} + +static inline void write_word_little(volatile UWORD *to, int x) +{ + asm volatile ("sthbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); +} + +static inline void write_word_big(volatile UWORD *to, int x) +{ + asm volatile ("sth %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static inline ULONG read_long_little(volatile ULONG *from) +{ + unsigned long x; + asm volatile ("lwbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m"(*from)); + return (ULONG)x; +} + +static inline ULONG read_long_big(volatile ULONG *from) +{ + unsigned long x; + asm volatile ("lwz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (ULONG)x; +} + +static inline void write_long_little(volatile ULONG *to, ULONG x) +{ + asm volatile ("stwbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); +} + +static inline void write_long_big(volatile ULONG *to, ULONG x) +{ + asm volatile ("stw %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +#define port_to_mem(from) (0xFE000000|(from)) +#define in_byte(from) read_byte( (UBYTE *)port_to_mem(from)) +#define in_word(from) read_word_little((UWORD *)port_to_mem(from)) +#define in_long(from) read_long_little((ULONG *)port_to_mem(from)) +#define out_byte(to, val) write_byte((UBYTE *)port_to_mem(to), val) +#define out_word(to, val) write_word_little((UWORD *)port_to_mem(to), val) +#define out_long(to, val) write_long_little((ULONG *)port_to_mem(to), val) + +static void X86API undefined_intr(int intno) +{ + extern u16 A1_rdw(u32 addr); + if (A1_rdw(intno * 4 + 2) == BIOS_SEG) + { + PRINTF("Undefined interrupt %xh called AX = %xh, BX = %xh, CX = %xh, DX = %xh\n", + intno, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + X86EMU_halt_sys(); + } + else + { + PRINTF("Calling interrupt %xh, AL=%xh, AH=%xh\n", intno, M.x86.R_AL, M.x86.R_AH); + X86EMU_prepareForInt(intno); + } +} + +static void X86API int42(int intno); +static void X86API int15(int intno); + +static void X86API int10(int intno) +{ + if (A1_rdw(intno*4+2) == BIOS_SEG) + int42(intno); + else + { + PRINTF("int10: branching to %04X:%04X, AL=%xh, AH=%xh\n", A1_rdw(intno*4+2), A1_rdw(intno*4), + M.x86.R_AL, M.x86.R_AH); + X86EMU_prepareForInt(intno); + } +} + +static void X86API int1A(int intno) +{ + int device; + + switch(M.x86.R_AX) + { + case 0xB101: /* PCI Bios Present? */ + M.x86.R_AL = 0x00; + M.x86.R_EDX = 0x20494350; + M.x86.R_BX = 0x0210; + M.x86.R_CL = 3; + CLEAR_FLAG(F_CF); + break; + case 0xB102: /* Find device */ + device = mypci_find_device(M.x86.R_DX, M.x86.R_CX, M.x86.R_SI); + if (device != -1) + { + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + M.x86.R_BH = mypci_bus(device); + M.x86.R_BL = mypci_devfn(device); + } + else + { + M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND; + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + break; + case 0xB103: /* Find PCI class code */ + M.x86.R_AH = PCIBIOS_DEVICE_NOT_FOUND; + /*printf("Find by class not yet implmented"); */ + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + break; + case 0xB108: /* read config byte */ + M.x86.R_CL = mypci_read_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("read_config_byte %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_CL); */ + break; + case 0xB109: /* read config word */ + M.x86.R_CX = mypci_read_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("read_config_word %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_CX); */ + break; + case 0xB10A: /* read config dword */ + M.x86.R_ECX = mypci_read_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("read_config_long %x,%x,%x -> %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_ECX); */ + break; + case 0xB10B: /* write config byte */ + mypci_write_cfg_byte(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CL); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("write_config_byte %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_CL); */ + break; + case 0xB10C: /* write config word */ + mypci_write_cfg_word(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_CX); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("write_config_word %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_CX); */ + break; + case 0xB10D: /* write config dword */ + mypci_write_cfg_long(M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, M.x86.R_ECX); + M.x86.R_AH = PCIBIOS_SUCCESSFUL; + CONDITIONAL_SET_FLAG((M.x86.R_AH != PCIBIOS_SUCCESSFUL), F_CF); + /*printf("write_config_long %x,%x,%x <- %x\n", M.x86.R_BH, M.x86.R_BL, M.x86.R_DI, */ + /* M.x86.R_ECX); */ + break; + default: + PRINTF("BIOS int %xh: Unknown function AX=%04xh\n", intno, M.x86.R_AX); + + } +} + +void bios_init(void) +{ + int i; + X86EMU_intrFuncs bios_intr_tab[256]; + + for (i=0; i<256; i++) + { + write_long_little(M.mem_base+i*4, BIOS_SEG<<16); + bios_intr_tab[i] = undefined_intr; + } + + bios_intr_tab[0x10] = int10; + bios_intr_tab[0x1A] = int1A; + bios_intr_tab[0x42] = int42; + bios_intr_tab[0x15] = int15; + + bios_intr_tab[0x6D] = int42; + + X86EMU_setupIntrFuncs(bios_intr_tab); + video_init(); +} + +unsigned char setup_40x25[] = +{ + 0x38, 0x28, 0x2d, 0x0a, 0x1f, 6, 0x19, + 0x1c, 2, 7, 6, 7, 0, 0, 0, 0 +}; + +unsigned char setup_80x25[] = +{ + 0x71, 0x50, 0x5a, 0x0a, 0x1f, 6, 0x19, + 0x1c, 2, 7, 6, 7, 0, 0, 0, 0 +}; + +unsigned char setup_graphics[] = +{ + 0x38, 0x28, 0x20, 0x0a, 0x7f, 6, 0x64, + 0x70, 2, 1, 6, 7, 0, 0, 0, 0 +}; + +unsigned char setup_bw[] = +{ + 0x61, 0x50, 0x52, 0x0f, 0x19, 6, 0x19, + 0x19, 2, 0x0d, 0x0b, 0x0c, 0, 0, 0, 0 +}; + +unsigned char * setup_modes[] = +{ + setup_40x25, /* mode 0: 40x25 bw text */ + setup_40x25, /* mode 1: 40x25 col text */ + setup_80x25, /* mode 2: 80x25 bw text */ + setup_80x25, /* mode 3: 80x25 col text */ + setup_graphics, /* mode 4: 320x200 col graphics */ + setup_graphics, /* mode 5: 320x200 bw graphics */ + setup_graphics, /* mode 6: 640x200 bw graphics */ + setup_bw /* mode 7: 80x25 mono text */ +}; + +unsigned int setup_cols[] = +{ + 40, 40, 80, 80, 40, 40, 80, 80 +}; + +unsigned char setup_modesets[] = +{ + 0x2C, 0x28, 0x2D, 0x29, 0x2A, 0x2E, 0x1E, 0x29 +}; + +unsigned int setup_bufsize[] = +{ + 2048, 2048, 4096, 2096, 16384, 16384, 16384, 4096 +}; + +void bios_set_mode(int mode) +{ + int i; + unsigned char mode_set = setup_modesets[mode]; /* Control register value */ + unsigned char *setup_regs = setup_modes[mode]; /* Register 3D4 Array */ + + /* Switch video off */ + out_byte(0x3D8, mode_set & 0x37); + + /* Set up parameters at 3D4h */ + for (i=0; i<16; i++) + { + out_byte(0x3D4, (unsigned char)i); + out_byte(0x3D5, *setup_regs); + setup_regs++; + } + + /* Enable video */ + out_byte(0x3D8, mode_set); + + /* Set overscan */ + if (mode == 6) out_byte(0x3D9, 0x3F); + else out_byte(0x3D9, 0x30); +} + +static void bios_print_string(void) +{ + extern void video_bios_print_string(char *string, int x, int y, int attr, int count); + char *s = (char *)(M.x86.R_ES<<4) + M.x86.R_BP; + int attr; + if (M.x86.R_AL & 0x02) attr = - 1; + else attr = M.x86.R_BL; + video_bios_print_string(s, M.x86.R_DH, M.x86.R_DL, attr, M.x86.R_CX); +} + +static void X86API int42(int intno) +{ + switch (M.x86.R_AH) + { + case 0x00: + bios_set_mode(M.x86.R_AL); + break; + case 0x13: + bios_print_string(); + break; + default: + PRINTF("Warning: VIDEO BIOS interrupt %xh unimplemented function %xh, AL = %xh\n", + intno, M.x86.R_AH, M.x86.R_AL); + } +} + +static void X86API int15(int intno) +{ + PRINTF("Called interrupt 15h: AX = %xh, BX = %xh, CX = %xh, DX = %xh\n", + M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); +} diff --git a/board/MAI/bios_emulator/glue.c b/board/MAI/bios_emulator/glue.c new file mode 100644 index 000000000..b380f0dfe --- /dev/null +++ b/board/MAI/bios_emulator/glue.c @@ -0,0 +1,515 @@ +#include +#include +#include <74xx_7xx.h> + + +#ifdef DEBUG +#undef DEBUG +#endif + +#ifdef DEBUG +#define PRINTF(format, args...) _printf(format , ## args) +#else +#define PRINTF(format, argc...) +#endif + +static pci_dev_t to_pci(int bus, int devfn) +{ + return PCI_BDF(bus, (devfn>>3), devfn&3); +} + +int mypci_find_device(int vendor, int product, int index) +{ + return pci_find_device(vendor, product, index); +} + +int mypci_bus(int device) +{ + return PCI_BUS(device); +} + +int mypci_devfn(int device) +{ + return (PCI_DEV(device)<<3) | PCI_FUNC(device); +} + + +#define mypci_read_func(type, size) \ +type mypci_read_cfg_##size##(int bus, int devfn, int offset) \ +{ \ + type c; \ + pci_read_config_##size##(to_pci(bus, devfn), offset, &c); \ + return c; \ +} + +#define mypci_write_func(type, size) \ +void mypci_write_cfg_##size##(int bus, int devfn, int offset, int value) \ +{ \ + pci_write_config_##size##(to_pci(bus, devfn), offset, value); \ +} + +mypci_read_func(u8,byte); +mypci_read_func(u16,word); + +mypci_write_func(u8,byte); +mypci_write_func(u16,word); + +u32 mypci_read_cfg_long(int bus, int devfn, int offset) +{ + u32 c; + pci_read_config_dword(to_pci(bus, devfn), offset, &c); + return c; +} + +void mypci_write_cfg_long(int bus, int devfn, int offset, int value) +{ + pci_write_config_dword(to_pci(bus, devfn), offset, value); +} + +void _printf(const char *fmt, ...) +{ + va_list args; + char buf[CFG_PBSIZE]; + + va_start(args, fmt); + (void)vsprintf(buf, fmt, args); + va_end(args); + + printf(buf); +} + +char *_getenv(char *name) +{ + return getenv(name); +} + +unsigned long get_bar_size(pci_dev_t dev, int offset) +{ + u32 bar_back, bar_value; + + /* Save old BAR value */ + pci_read_config_dword(dev, offset, &bar_back); + + /* Write all 1's. */ + pci_write_config_dword(dev, offset, ~0); + + /* Now read back the relevant bits */ + pci_read_config_dword(dev, offset, &bar_value); + + /* Restore original value */ + pci_write_config_dword(dev, offset, bar_back); + + if (bar_value == 0) return 0xFFFFFFFF; /* This BAR is disabled */ + + if ((bar_value & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) + { + /* This is a memory space BAR. Mask it out so we get the size of it */ + return ~(bar_value & PCI_BASE_ADDRESS_MEM_MASK) + 1; + } + + /* Not suitable */ + return 0xFFFFFFFF; +} + +void enable_compatibility_hole(void) +{ + u8 cfg; + pci_dev_t art = PCI_BDF(0,0,0); + + pci_read_config_byte(art, 0x54, &cfg); + /* cfg |= 0x08; */ + cfg |= 0x20; + pci_write_config_byte(art, 0x54, cfg); +} + +void disable_compatibility_hole(void) +{ + u8 cfg; + pci_dev_t art = PCI_BDF(0,0,0); + + pci_read_config_byte(art, 0x54, &cfg); + /* cfg &= ~0x08; */ + cfg &= ~0x20; + pci_write_config_byte(art, 0x54, cfg); +} + +void map_rom(pci_dev_t dev, u32 address) +{ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, address|PCI_ROM_ADDRESS_ENABLE); +} + +void unmap_rom(pci_dev_t dev) +{ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0); +} + +void bat_map(u8 batnum, u32 address, u32 length) +{ + u32 temp = address; + address &= 0xFFFE0000; + temp &= 0x0001FFFF; + length = (length - 1 ) >> 17; + length <<= 2; + + switch (batnum) + { + case 0: + __asm volatile ("mtdbatu 0, %0" : : "r" (address | length | 3)); + __asm volatile ("mtdbatl 0, %0" : : "r" (address | 0x22)); + break; + case 1: + __asm volatile ("mtdbatu 1, %0" : : "r" (address | length | 3)); + __asm volatile ("mtdbatl 1, %0" : : "r" (address | 0x22)); + break; + case 2: + __asm volatile ("mtdbatu 2, %0" : : "r" (address | length | 3)); + __asm volatile ("mtdbatl 2, %0" : : "r" (address | 0x22)); + break; + case 3: + __asm volatile ("mtdbatu 3, %0" : : "r" (address | length | 3)); + __asm volatile ("mtdbatl 3, %0" : : "r" (address | 0x22)); + break; + } +} + +int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size); + +int attempt_map_rom(pci_dev_t dev, void *copy_address) +{ + u32 rom_size = 0; + u32 rom_address = 0; + u32 bar_size = 0; + u32 bar_backup = 0; + int i,j; + void *image = 0; + u32 image_size = 0; + int did_correct = 0; + u32 prefetch_addr = 0; + u32 prefetch_size = 0; + u32 prefetch_idx = 0; + + /* Get the size of the expansion rom */ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0xFFFFFFFF); + pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_size); + if ((rom_size & 0x01) == 0) + { + PRINTF("No ROM\n"); + return 0; + } + + rom_size &= 0xFFFFF800; + rom_size = (~rom_size)+1; + + PRINTF("ROM Size is %dK\n", rom_size/1024); + + /* + * Try to find a place for the ROM. We always attempt to use + * one of the card's bases for this, as this will be in any + * bridge's resource range as well as being free of conflicts + * with other cards. In a graphics card it is very unlikely + * that there won't be any base address that is large enough to + * hold the rom. + * + * FIXME: To work around this, theoretically the largest base + * could be used if none is found in the loop below. + */ + + for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4) + { + bar_size = get_bar_size(dev, i); + PRINTF("PCI_BASE_ADDRESS_%d is %dK large\n", + (i - PCI_BASE_ADDRESS_0)/4, + bar_size/1024); + if (bar_size != 0xFFFFFFFF && bar_size >= rom_size) + { + PRINTF("Found a match for rom size\n"); + pci_read_config_dword(dev, i, &rom_address); + rom_address &= 0xFFFFFFF0; + if (rom_address != 0 && rom_address != 0xFFFFFFF0) break; + } + } + + if (rom_address == 0 || rom_address == 0xFFFFFFF0) + { + PRINTF("No suitable rom address found\n"); + return 0; + } + + /* Disable the BAR */ + pci_read_config_dword(dev, i, &bar_backup); + pci_write_config_dword(dev, i, 0); + + /* Map ROM */ + pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address | PCI_ROM_ADDRESS_ENABLE); + + /* Copy the rom to a place in the emulator space */ + PRINTF("Claiming BAT 2\n"); + bat_map(2, rom_address, rom_size); + /* show_bat_mapping(); */ + + if (0 == find_image(rom_address, rom_size, &image, &image_size)) + { + PRINTF("No x86 BIOS image found\n"); + return 0; + } + + PRINTF("Copying %ld bytes from 0x%lx to 0x%lx\n", (long)image_size, (long)image, (long)copy_address); + + /* memcpy(copy_address, rom_address, rom_size); */ + { + unsigned char *from = (unsigned char *)image; /* rom_address; */ + unsigned char *to = (unsigned char *)copy_address; + for (j=0; j>16, (prefetch_addr+prefetch_size)>>16); */ +/* pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, (prefetch_addr>>16)); */ +/* pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, (prefetch_addr+prefetch_size)>>16); */ + } + + pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, 0x1000); + pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, 0x0000); + + pci_write_config_byte(bridge, 0xD0, 0x0A); + pci_write_config_byte(bridge, 0xD3, 0x04); + + /* + * Set the interrupt pin to 0 + */ +#if 0 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0); + pci_write_config_byte(dev, PCI_INTERRUPT_PIN, 0); +#endif + pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0); + pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0); + + } + } + + /* Finally, enable the card's IO and memory response */ + pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0); + + return 1; +} + +int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size) +{ + int i = 0; + unsigned char *rom = (unsigned char *)rom_address; + /* if (*rom != 0x55 || *(rom+1) != 0xAA) return 0; /* No bios rom this is, yes. */ */ + + for (;;) + { + unsigned short pci_data_offset = *(rom+0x18) + 256 * *(rom+0x19); + unsigned short pci_image_length = (*(rom+pci_data_offset+0x10) + 256 * *(rom+pci_data_offset+0x11)) * 512; + unsigned char pci_image_type = *(rom+pci_data_offset+0x14); + if (*rom != 0x55 || *(rom+1) != 0xAA) + { + PRINTF("Invalid header this is\n"); + return 0; + } + PRINTF("Image %i: Type %d (%s)\n", i++, pci_image_type, + pci_image_type==0 ? "x86" : + pci_image_type==1 ? "OpenFirmware" : + "Unknown"); + if (pci_image_type == 0) + { + *image = rom; + *image_size = pci_image_length; + return 1; + } + + if (*(rom+pci_data_offset+0x15) & 0x80) + { + PRINTF("LAST image encountered, no image found\n"); + return 0; + } + + rom += pci_image_length; + } +} + +void show_bat_mapping(void) +{ + u32 dbat0u, dbat0l, ibat0u, ibat0l; + u32 dbat1u, dbat1l, ibat1u, ibat1l; + u32 dbat2u, dbat2l, ibat2u, ibat2l; + u32 dbat3u, dbat3l, ibat3u, ibat3l; + u32 msr, hid0, l2cr_reg; + + __asm volatile ("mfdbatu %0,0" : "=r" (dbat0u)); + __asm volatile ("mfdbatl %0,0" : "=r" (dbat0l)); + __asm volatile ("mfibatu %0,0" : "=r" (ibat0u)); + __asm volatile ("mfibatl %0,0" : "=r" (ibat0l)); + + __asm volatile ("mfdbatu %0,1" : "=r" (dbat1u)); + __asm volatile ("mfdbatl %0,1" : "=r" (dbat1l)); + __asm volatile ("mfibatu %0,1" : "=r" (ibat1u)); + __asm volatile ("mfibatl %0,1" : "=r" (ibat1l)); + + __asm volatile ("mfdbatu %0,2" : "=r" (dbat2u)); + __asm volatile ("mfdbatl %0,2" : "=r" (dbat2l)); + __asm volatile ("mfibatu %0,2" : "=r" (ibat2u)); + __asm volatile ("mfibatl %0,2" : "=r" (ibat2l)); + + __asm volatile ("mfdbatu %0,3" : "=r" (dbat3u)); + __asm volatile ("mfdbatl %0,3" : "=r" (dbat3l)); + __asm volatile ("mfibatu %0,3" : "=r" (ibat3u)); + __asm volatile ("mfibatl %0,3" : "=r" (ibat3l)); + + __asm volatile ("mfmsr %0" : "=r" (msr)); + __asm volatile ("mfspr %0,1008": "=r" (hid0)); + __asm volatile ("mfspr %0,1017": "=r" (l2cr_reg)); + + printf("dbat0u: %08x dbat0l: %08x ibat0u: %08x ibat0l: %08x\n", + dbat0u, dbat0l, ibat0u, ibat0l); + printf("dbat1u: %08x dbat1l: %08x ibat1u: %08x ibat1l: %08x\n", + dbat1u, dbat1l, ibat1u, ibat1l); + printf("dbat2u: %08x dbat2l: %08x ibat2u: %08x ibat2l: %08x\n", + dbat2u, dbat2l, ibat2u, ibat2l); + printf("dbat3u: %08x dbat3l: %08x ibat3u: %08x ibat3l: %08x\n", + dbat3u, dbat3l, ibat3u, ibat3l); + + printf("\nMSR: %08x HID0: %08x L2CR: %08x \n", msr,hid0, l2cr_reg); +} + + +void remove_init_data(void) +{ + char *s; + + /* Invalidate and disable data cache */ + invalidate_l1_data_cache(); + dcache_disable(); + + s = getenv("x86_cache"); + + if (!s) + { + icache_enable(); + dcache_enable(); + } + else if (s) + { + if (strcmp(s, "dcache")==0) + { + dcache_enable(); + } + else if (strcmp(s, "icache") == 0) + { + icache_enable(); + } + else if (strcmp(s, "on")== 0 || strcmp(s, "both") == 0) + { + dcache_enable(); + icache_enable(); + } + } + + /* show_bat_mapping();*/ +} diff --git a/board/MAI/bios_emulator/glue.h b/board/MAI/bios_emulator/glue.h new file mode 100644 index 000000000..585efe128 --- /dev/null +++ b/board/MAI/bios_emulator/glue.h @@ -0,0 +1,57 @@ +#ifndef GLUE_H +#define GLUE_H + +typedef unsigned int pci_dev_t; + +int mypci_find_device(int vendor, int product, int index); +int mypci_bus(int device); +int mypci_devfn(int device); +unsigned long get_bar_size(pci_dev_t dev, int offset); + +u8 mypci_read_cfg_byte(int bus, int devfn, int offset); +u16 mypci_read_cfg_word(int bus, int devfn, int offset); +u32 mypci_read_cfg_long(int bus, int devfn, int offset); + +void mypci_write_cfg_byte(int bus, int devfn, int offset, u8 value); +void mypci_write_cfg_word(int bus, int devfn, int offset, u16 value); +void mypci_write_cfg_long(int bus, int devfn, int offset, u32 value); + +void _printf(const char *fmt, ...); +char *_getenv(char *name); + +void *malloc(size_t size); +void memset(void *addr, int value, size_t size); +void memcpy(void *to, void *from, size_t numbytes); +int strcmp(char *, char *); + +void enable_compatibility_hole(void); +void disable_compatibility_hole(void); + +void map_rom(pci_dev_t dev, unsigned long address); +void unmap_rom(pci_dev_t dev); +int attempt_map_rom(pci_dev_t dev, void *copy_address); + +#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ +#define PCI_BASE_ADDRESS_SPACE_IO 0x01 +#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 +#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) + +#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ +#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ +#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ +#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ +#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ +#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ +#define PCI_BUS(d) (((d) >> 16) & 0xff) +#define PCI_DEV(d) (((d) >> 11) & 0x1f) +#define PCI_FUNC(d) (((d) >> 8) & 0x7) +#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8) + +#define PCI_ANY_ID (~0) +#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ +#define PCI_ROM_ADDRESS_ENABLE 0x01 + +#define OFF(addr) ((addr) & 0xFFFF) +#define SEG(addr) (((addr)>>4) &0xF000) + +#endif diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake new file mode 100755 index 0000000000000000000000000000000000000000..4d6ccb3f46ee6c0e2ca1e75884595e043b3ec097 GIT binary patch literal 70812 zcmd?SeRx#W)i-=5nMo!vVS)sV8Z>H9P*9?v1c(j^6CxiHnUJ7{uWIm+B1AX`K?n?; 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zO`_5p!tzs)BCJ#eAKbHpRorgHyD1#e{t)et6N_9~h1QP@o1RDe&00OKC2zB{g0!z9yTXmcR$uIOqHs7hpIpI!- zZ|3+a$jz1)?k;>IAI9=*lMT4W;jHCafE#cpU=?5^AOzR}coOhk!0Uhy06zizC*Xeo zUjoMAZ01^kn`bnDRe+6v5PVHxNm0MG95DPEr0;K)gsIHTpcP5pP_?lZ5$=dT=*D4-O|%3x;g*M0Zb`~B8Mi#Qa!11QXvS^-`m}HaMvXSw z9EKe{dz+hl!gl8iH#hr3Xh!+_htv3{2%cp#C!8mFP7juDbZtfTCeCCkyk^K|O5UW!q8tQXp{ zhUkxVvjmXUV|~qs9_x;JlxOw64w}AMzpU?m5R_*x>hZc4kkuQ2-T?I4vq3>dJ;K@? zJ^rsmE1ccJ0cNhOzX!l){qd|~-=xd;yD6i`@p50-5514FPBJneu_Z%ud^{E5|4HO@ zD`TTxOO76&tvaE1x$!=dqnCtU@+ %BC3_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BC3_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BC3_PATH%\BIN\tlink.cfg + +echo Borland C++ 3.1 DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat new file mode 100755 index 000000000..d2939f458 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat @@ -0,0 +1,37 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat new file mode 100755 index 000000000..246517d10 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 16 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink.cfg + +echo Borland C++ 4.5 16 bit DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat new file mode 100755 index 000000000..cbb2c7951 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 32 bit DOS compilation configuration set up (DPMI32). diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat b/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat new file mode 100755 index 000000000..14d7c05b1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP=1 +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 Snap compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat new file mode 100755 index 000000000..50bd3cb5d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat @@ -0,0 +1,46 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC4;%BC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC4;%BC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT=1 +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 32 bit DOS compilation configuration set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat new file mode 100755 index 000000000..4b59fa422 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows VxD mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD=1 +SET USE_TNT= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 32-bit VxD compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat b/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat new file mode 100755 index 000000000..4d799b47b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 16 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_VXD= +SET USE_BC5= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink.cfg + +echo Borland C++ 4.5 16 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat new file mode 100755 index 000000000..a6c199fe9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat @@ -0,0 +1,37 @@ +@echo off +REM Setup for compiling with Borland C++ 4.5 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC4;%BC4_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC4;%BC4_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC4_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_BC5= +SET WIN32_GUI=1 +SET USE_SNAP= +SET BC_LIBBASE=BC4 +PATH %SCITECH_BIN%;%BC4_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC4_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC4_PATH%\BIN\tlink32.cfg + +echo Borland C++ 4.5 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat new file mode 100755 index 000000000..6a0fde2c9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET C_INCLUDE=%BC5_PATH%\INCLUDE +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat new file mode 100755 index 000000000..23b50389d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 16 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink.cfg + +echo Borland C++ 5.0 16 bit DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat new file mode 100755 index 000000000..0521f93ce --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat @@ -0,0 +1,35 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit DOS compilation configuration set up (DPMI32). diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat b/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat new file mode 100755 index 000000000..e3241ffae --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat @@ -0,0 +1,35 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SMX32\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SMX32\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32=1 +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit SMX compilation configuration set up (SMX32). diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat b/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat new file mode 100755 index 000000000..ab3acd23c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP=1 +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 Snap compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat new file mode 100755 index 000000000..4dcc3723b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat @@ -0,0 +1,48 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BC5;%BC5_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BC5;%BC5_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT=1 +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit DOS compilation configuration set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat new file mode 100755 index 000000000..2356911ab --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD=1 +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit Windows (VxD) compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat b/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat new file mode 100755 index 000000000..cd79d86b8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat @@ -0,0 +1,34 @@ + @echo off +REM Setup for compiling with Borland C++ 5.0 in 16 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_VXD= +SET USE_BC5=1 +SET USE_SMX32= +SET USE_SMX16= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink.cfg + +echo Borland C++ 5.0 16 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat new file mode 100755 index 000000000..8b8cec943 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET C_INCLUDE=%BC5_PATH%\INCLUDE +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI=1 +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat b/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat new file mode 100755 index 000000000..ebfeb2eb6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BC5;%BC5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BC5;%BC5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BC5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI=1 +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BC5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BC5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BC5_PATH%\BIN\tlink32.cfg + +echo Borland C++ 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat new file mode 100755 index 000000000..6e0942881 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET C_INCLUDE=%BCB5_PATH%\INCLUDE +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat new file mode 100755 index 000000000..aa13e7dd2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 16 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink.cfg + +echo Borland C++ Builder 5.0 16 bit DOS compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat new file mode 100755 index 000000000..d0017d4cc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat @@ -0,0 +1,35 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit DOS compilation configuration set up (DPMI32). diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat new file mode 100755 index 000000000..2b969a93b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat @@ -0,0 +1,35 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SMX32\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SMX32\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32=1 +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit SMX compilation configuration set up (SMX32). diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat new file mode 100755 index 000000000..d7b8ff20a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP=1 +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 Snap compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat new file mode 100755 index 000000000..1de3601a5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat @@ -0,0 +1,48 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\BCB5;%BCB5_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\BCB5;%BCB5_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_DPMI16= +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD= +SET USE_TNT=1 +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%BC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit DOS compilation configuration set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat new file mode 100755 index 000000000..28de58c3f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\VXD\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\VXD\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_VXD=1 +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit Windows (VxD) compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat new file mode 100755 index 000000000..c30d00408 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat @@ -0,0 +1,34 @@ + @echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 16 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC16.MK +SET USE_DPMI16= +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_VXD= +SET USE_BC5=1 +SET USE_SMX32= +SET USE_SMX16= +SET WIN32_GUI= +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\turboc.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\turboc.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink.cfg + +echo Borland C++ Builder 5.0 16 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat new file mode 100755 index 000000000..18760e112 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET C_INCLUDE=%BCB5_PATH%\INCLUDE +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI=1 +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto createfiles +call win32sdk.bat borland + +:createfiles +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat new file mode 100755 index 000000000..198c1a242 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Borland C++ Builder 5.0 in 32 bit Windows mode. + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\BCB5;%BCB5_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%BCB5_PATH%\INCLUDE; +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\BC32.MK +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_VXD= +SET USE_TNT= +SET USE_SMX32= +SET USE_SMX16= +SET USE_BC5=1 +SET WIN32_GUI=1 +SET USE_SNAP= +SET BC_LIBBASE=BC5 +PATH %SCITECH_BIN%;%BCB5_PATH%\BIN;%DEFPATH%%BC5_CD_PATH% + +REM: Create Borland compile/link configuration scripts +echo -I%INCLUDE% > %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% >> %BCB5_PATH%\BIN\bcc32.cfg +echo -L%LIB% > %BCB5_PATH%\BIN\tlink32.cfg + +echo Borland C++ Builder 5.0 32 bit Windows compilation configuration set up. diff --git a/board/MAI/bios_emulator/scitech/bin/build b/board/MAI/bios_emulator/scitech/bin/build new file mode 100755 index 000000000..ff1973dc8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/build @@ -0,0 +1,22 @@ +#! /bin/sh + +if [ $# -lt 1 ] || ( [ "$1" != gcc-linux ] && [ "$1" != qnx4 ] ) ; then + echo Usage: $0 compiler_name [DMAKE commands] + echo + echo Current compilers: + echo " gcc-linux - GNU C/C++ 2.7 or higher, 32 bit" + echo " qnx4 - Watcom C/C++ 10.6 or higher, 32 bit" + exit 1 +fi + +unset DBG OPT OPT_SIZE BUILD_DLL IMPORT_DLL FPU CHECKS BETA +. ${1}.sh + +shift +dmake $* && exit 0 + +echo ************************************************* +echo * An error occurred while building the library. * +echo ************************************************* +exit 1 + diff --git a/board/MAI/bios_emulator/scitech/bin/build.bat b/board/MAI/bios_emulator/scitech/bin/build.bat new file mode 100755 index 000000000..ee2909363 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/build.bat @@ -0,0 +1,4 @@ +@echo off +rem Disable checked build and build release code +set CHECKED= +call build_it.bat %1 %2 %3 %4 %5 %6 %7 %8 %9 diff --git a/board/MAI/bios_emulator/scitech/bin/build_db.bat b/board/MAI/bios_emulator/scitech/bin/build_db.bat new file mode 100755 index 000000000..2b325293a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/build_db.bat @@ -0,0 +1,4 @@ +@echo off +rem Enable checked build and build debug code +set CHECKED=1 +call build_it.bat %1 %2 %3 %4 %5 %6 %7 %8 %9 diff --git a/board/MAI/bios_emulator/scitech/bin/build_it.bat b/board/MAI/bios_emulator/scitech/bin/build_it.bat new file mode 100755 index 000000000..5a619b445 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/build_it.bat @@ -0,0 +1,432 @@ +@echo off +rem Generic batch file to build a version of the library. This batch file +rem assumes that the correct batch files exist to setup the appropriate +rem compilation environments, and that the DMAKE.EXE program is available +rem somewhere on the path. +rem +rem Builds as release or debug depending on the value of the CHECKED +rem environment variable. + +rem Unset all environment variables that change the compile process +set DBG= +set OPT= +set OPT_SIZE= +set BUILD_DLL= +set IMPORT_DLL= +set FPU= +set CHECKS= +set BETA= + +if %1==bc31-d16 goto bc31-d16 +if %1==bc45-d16 goto bc45-d16 +if %1==bc45-d32 goto bc45-d32 +if %1==bc45-tnt goto bc45-tnt +if %1==bc45-w16 goto bc45-w16 +if %1==bc45-w32 goto bc45-w32 +if %1==bc45-c32 goto bc45-c32 +if %1==bc45-vxd goto bc45-vxd +if %1==bc45-snp goto bc45-snp +if %1==bc50-d16 goto bc50-d16 +if %1==bc50-d32 goto bc50-d32 +if %1==bc50-tnt goto bc50-tnt +if %1==bc50-w16 goto bc50-w16 +if %1==bc50-w32 goto bc50-w32 +if %1==bc50-c32 goto bc50-c32 +if %1==bc50-vxd goto bc50-vxd +if %1==bc50-snp goto bc50-snp +if %1==gcc2-d32 goto gcc2-d32 +if %1==gcc2-w32 goto gcc2-w32 +if %1==gcc2-c32 goto gcc2-c32 +if %1==gcc2-linux goto gcc2-linux +if %1==vc40-d16 goto vc40-d16 +if %1==vc40-tnt goto vc40-tnt +if %1==vc40-w16 goto vc40-w16 +if %1==vc40-w32 goto vc40-w32 +if %1==vc40-c32 goto vc40-c32 +if %1==vc40-drv9x goto vc40-drv9x +if %1==vc40-drvnt goto vc40-drvnt +if %1==vc40-rtt goto vc40-rtt +if %1==vc40-snp goto vc40-snp +if %1==vc50-d16 goto vc50-d16 +if %1==vc50-tnt goto vc50-tnt +if %1==vc50-w16 goto vc50-w16 +if %1==vc50-w32 goto vc50-w32 +if %1==vc50-c32 goto vc50-c32 +if %1==vc50-drv9x goto vc50-drv9x +if %1==vc50-drvnt goto vc50-drvnt +if %1==vc50-rtt goto vc50-rtt +if %1==vc50-snp goto vc50-snp +if %1==vc60-d16 goto vc60-d16 +if %1==vc60-tnt goto vc60-tnt +if %1==vc60-w16 goto vc60-w16 +if %1==vc60-w32 goto vc60-w32 +if %1==vc60-c32 goto vc60-c32 +if %1==vc60-drv9x goto vc60-drv9x +if %1==vc60-drvnt goto vc60-drvnt +if %1==vc60-drvw2k goto vc60-drvw2k +if %1==vc60-rtt goto vc60-rtt +if %1==vc60-snp goto vc60-snp +if %1==wc10ad16 goto wc10ad16 +if %1==wc10ad32 goto wc10ad32 +if %1==wc10atnt goto wc10atnt +if %1==wc10aw16 goto wc10aw16 +if %1==wc10aw32 goto wc10aw32 +if %1==wc10ac32 goto wc10ac32 +if %1==wc10ao32 goto wc10ao32 +if %1==wc10ap32 goto wc10ap32 +if %1==wc10asnp goto wc10asnp +if %1==wc10-d16 goto wc10-d16 +if %1==wc10-d32 goto wc10-d32 +if %1==wc10-tnt goto wc10-tnt +if %1==wc10-w16 goto wc10-w16 +if %1==wc10-w32 goto wc10-w32 +if %1==wc10-c32 goto wc10-c32 +if %1==wc10-o32 goto wc10-o32 +if %1==wc10-p32 goto wc10-p32 +if %1==wc10-snp goto wc10-snp +if %1==wc11-d16 goto wc11-d16 +if %1==wc11-d32 goto wc11-d32 +if %1==wc11-tnt goto wc11-tnt +if %1==wc11-w16 goto wc11-w16 +if %1==wc11-w32 goto wc11-w32 +if %1==wc11-c32 goto wc11-c32 +if %1==wc11-o32 goto wc11-o32 +if %1==wc11-p32 goto wc11-p32 +if %1==wc11-snp goto wc11-snp + +echo Usage: BUILD 'compiler_name' [DMAKE commands] +echo. +echo Where 'compiler_name' is of the form comp-os, where +echo 'comp' defines the compiler and 'os' defines the OS environment. +echo For instance 'bc50-w32' is for Borland C++ 5.0 for Win32. +echo The value of 'comp' can be any of the following: +echo. +echo bc45 - Borland C++ 4.5x +echo bc50 - Borland C++ 5.x +echo vc40 - Visual C++ 4.x +echo vc50 - Visual C++ 5.x +echo vc60 - Visual C++ 6.x +echo wc10 - Watcom C++ 10.6 +echo wc11 - Watcom C++ 11.0 +echo gcc2 - GNU C/C++ 2.9x +echo. +echo The value of 'os' can be one of the following: +echo. +echo d16 - 16-bit DOS +echo d32 - 32-bit DOS +echo w16 - 16-bit Windows GUI mode +echo c32 - 32-bit Windows console mode +echo w32 - 32-bit Windows GUI mode +echo o16 - 16-bit OS/2 console mode +echo o32 - 32-bit OS/2 console mode +echo p32 - 32-bit OS/2 Presentation Manager +echo snp - 32-bit SciTech Snap application +echo linux - 32-bit Linux application +goto end + +rem ------------------------------------------------------------------------- +rem Setup for the specified compiler + +:bc31-d16 +call bc31-d16.bat +goto compileit + +:bc45-d16 +call bc45-d16.bat +goto compileit + +:bc45-d32 +call bc45-d32.bat +goto compileit + +:bc45-tnt +call bc45-tnt.bat +goto compileit + +:bc45-w16 +call bc45-w16.bat +goto compileit + +:bc45-w32 +call bc45-w32.bat +goto compileit + +:bc45-c32 +call bc45-c32.bat +goto compileit + +:bc45-vxd +call bc45-vxd.bat +goto compileit + +:bc50-d16 +call bc50-d16.bat +goto compileit + +:bc50-d32 +call bc50-d32.bat +goto compileit + +:bc50-tnt +call bc50-tnt.bat +goto compileit + +:bc50-w16 +call bc50-w16.bat +goto compileit + +:bc50-w32 +call bc50-w32.bat +goto compileit + +:bc50-c32 +call bc50-c32.bat +goto compileit + +:bc50-vxd +call bc50-vxd.bat +goto compileit + +:gcc2-d32 +call gcc2-d32.bat +goto compileit + +:gcc2-w32 +call gcc2-w32.bat +goto compileit + +:gcc2-c32 +call gcc2-c32.bat +goto compileit + +:gcc2-linux +call gcc2-linux.bat +goto compileit + +:sc70-d16 +call sc70-d16.bat +goto compileit + +:sc70-w16 +call sc70-w16.bat +goto compileit + +:sc70-tnt +call sc70-tnt.bat +goto compileit + +:sc70-w32 +call sc70-w32.bat +goto compileit + +:sc70-c32 +call sc70-c32.bat +goto compileit + +:vc40-d16 +call vc40-d16.bat +goto compileit + +:vc40-tnt +call vc40-tnt.bat +goto compileit + +:vc40-w16 +call vc40-w16.bat +goto compileit + +:vc40-w32 +call vc40-w32.bat +goto compileit + +:vc40-c32 +call vc40-c32.bat +goto compileit + +:vc40-drv9x +call vc40-drv9x.bat +goto compileit + +:vc40-drvnt +call vc40-drvnt.bat +goto compileit + +:vc40-rtt +call vc40-rtt.bat +goto compileit + +:vc50-d16 +call vc50-d16.bat +goto compileit + +:vc50-tnt +call vc50-tnt.bat +goto compileit + +:vc50-w16 +call vc50-w16.bat +goto compileit + +:vc50-w32 +call vc50-w32.bat +goto compileit + +:vc50-c32 +call vc50-c32.bat +goto compileit + +:vc50-drv9x +call vc50-drv9x.bat +goto compileit + +:vc50-drvnt +call vc50-drvnt.bat +goto compileit + +:vc50-rtt +call vc50-rtt.bat +goto compileit + +:vc60-d16 +call vc60-d16.bat +goto compileit + +:vc60-tnt +call vc60-tnt.bat +goto compileit + +:vc60-w16 +call vc60-w16.bat +goto compileit + +:vc60-w32 +call vc60-w32.bat +goto compileit + +:vc60-c32 +call vc60-c32.bat +goto compileit + +:vc60-drv9x +call vc60-drv9x.bat +goto compileit + +:vc60-drvnt +call vc60-drvnt.bat +goto compileit + +:vc60-drvw2k +call vc60-drvw2k.bat +goto compileit + +:vc60-rtt +call vc60-rtt.bat +goto compileit + +:wc10ad16 +call wc10ad16.bat +goto compileit + +:wc10ad32 +call wc10ad32.bat +goto compileit + +:wc10atnt +call wc10atnt.bat +goto compileit + +:wc10aw16 +call wc10aw16.bat +goto compileit + +:wc10aw32 +call wc10aw32.bat +goto compileit + +:wc10ac32 +call wc10ac32.bat +goto compileit + +:wc10ao32 +call wc10ao32.bat +goto compileit + +:wc10ap32 +call wc10ap32.bat +goto compileit + +:wc10-d16 +call wc10-d16.bat +goto compileit + +:wc10-d32 +call wc10-d32.bat +goto compileit + +:wc10-tnt +call wc10-tnt.bat +goto compileit + +:wc10-w16 +call wc10-w16.bat +goto compileit + +:wc10-w32 +call wc10-w32.bat +goto compileit + +:wc10-c32 +call wc10-c32.bat +goto compileit + +:wc10-o32 +call wc10-o32.bat +goto compileit + +:wc10-p32 +call wc10-p32.bat +goto compileit + +:wc11-d16 +call wc11-d16.bat +goto compileit + +:wc11-d32 +call wc11-d32.bat +goto compileit + +:wc11-tnt +call wc11-tnt.bat +goto compileit + +:wc11-w16 +call wc11-w16.bat +goto compileit + +:wc11-w32 +call wc11-w32.bat +goto compileit + +:wc11-c32 +call wc11-c32.bat +goto compileit + +:wc11-o32 +call wc11-o32.bat +goto compileit + +:wc11-p32 +call wc11-p32.bat +goto compileit + +:compileit +k_rm -f *.lib *.a +dmake %2 %3 %4 %5 %6 %7 %8 %9 +if errorlevel 1 goto errorend +goto end + +:errorend +echo ************************************************* +echo * An error occurred while building the library. * +echo ************************************************* +:end diff --git a/board/MAI/bios_emulator/scitech/bin/cddrv.bat b/board/MAI/bios_emulator/scitech/bin/cddrv.bat new file mode 100755 index 000000000..b64f4d746 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/cddrv.bat @@ -0,0 +1,6 @@ +@echo off +%1 +cd %3 +%4 %5 %6 %7 %8 %9 +%2 + diff --git a/board/MAI/bios_emulator/scitech/bin/cdit b/board/MAI/bios_emulator/scitech/bin/cdit new file mode 100755 index 000000000..b22023d54 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/cdit @@ -0,0 +1,10 @@ +#! /bin/sh + +cd $1 +PROG=$2 +shift 2 +rm -f *.lib *.a +$PROG $* +RET=$? +cd .. +exit $RET diff --git a/board/MAI/bios_emulator/scitech/bin/cdit.bat b/board/MAI/bios_emulator/scitech/bin/cdit.bat new file mode 100755 index 000000000..950b64807 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/cdit.bat @@ -0,0 +1,5 @@ +@echo off +cd %1 +k_rm -f *.lib *.a +shift 1 +%1 %2 %3 %4 %5 %6 %7 %8 %9 diff --git a/board/MAI/bios_emulator/scitech/bin/djgpp.env b/board/MAI/bios_emulator/scitech/bin/djgpp.env new file mode 100644 index 000000000..5a2c3d816 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/djgpp.env @@ -0,0 +1,46 @@ +#= Don't edit this line unless you move djgpp.env outside +#= of the djgpp installation directory. If you do move +#= it, set DJDIR to the directory you installed DJGPP in. +#= +DJDIR=%:/>DJGPP% + ++USER=dosuser ++TMPDIR=%DJDIR%/tmp ++EMU387=%DJDIR%/bin/emu387.dxe ++LFN=y + +[bison] +BISON_HAIRY=%DJDIR%/lib/bison.hai +BISON_SIMPLE=%DJDIR%/lib/bison.sim + +[cpp] +CPLUS_INCLUDE_PATH=%/>;CPLUS_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/lang/cxx;%DJDIR%/include;%DJDIR%/contrib/grx20/include +C_INCLUDE_PATH=%/>;C_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/include;%DJDIR%/contrib/grx20/include +OBJCPLUS_INCLUDE_PATH=%/>;OBJCPLUS_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc +OBJC_INCLUDE_PATH=%/>;OBJC_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc + +[gcc] +COMPILER_PATH=%/>;COMPILER_PATH%%DJDIR%/bin +LIBRARY_PATH=%/>;LIBRARY_PATH%%DJDIR%/lib;%DJDIR%/contrib/grx20/lib;%SCITECH%/lib/release/dos32/dj2 + +[info] +INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info +INFO_COLORS=0x1f.0x31 + +[emacs] +INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info + +[less] +LESSBINFMT=*k<%X> +LESSCHARDEF=8bcccbcc12bc5b95.b127.b +LESS=%LESS% -h5$y5$Dd2.0$Du14.0$Ds4.7$Dk9.0$ + +[locate] ++LOCATE_PATH=%DJDIR%/lib/locatedb.dat + +[ls] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: +[dir] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: +[vdir] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: diff --git a/board/MAI/bios_emulator/scitech/bin/djgpp_db.env b/board/MAI/bios_emulator/scitech/bin/djgpp_db.env new file mode 100644 index 000000000..9b792c93e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/djgpp_db.env @@ -0,0 +1,46 @@ +#= Don't edit this line unless you move djgpp.env outside +#= of the djgpp installation directory. If you do move +#= it, set DJDIR to the directory you installed DJGPP in. +#= +DJDIR=%:/>DJGPP% + ++USER=dosuser ++TMPDIR=%DJDIR%/tmp ++EMU387=%DJDIR%/bin/emu387.dxe ++LFN=y + +[bison] +BISON_HAIRY=%DJDIR%/lib/bison.hai +BISON_SIMPLE=%DJDIR%/lib/bison.sim + +[cpp] +CPLUS_INCLUDE_PATH=%/>;CPLUS_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/lang/cxx;%DJDIR%/include;%DJDIR%/contrib/grx20/include +C_INCLUDE_PATH=%/>;C_INCLUDE_PATH%include;%SCITECH%/include;%PRIVATE%/include;.;%DJDIR%/include;%DJDIR%/contrib/grx20/include +OBJCPLUS_INCLUDE_PATH=%/>;OBJCPLUS_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc +OBJC_INCLUDE_PATH=%/>;OBJC_INCLUDE_PATH%%DJDIR%/include;%DJDIR%/lang/objc + +[gcc] +COMPILER_PATH=%/>;COMPILER_PATH%%DJDIR%/bin +LIBRARY_PATH=%/>;LIBRARY_PATH%%DJDIR%/lib;%DJDIR%/contrib/grx20/lib;%SCITECH%/lib/debug/dos32/dj2 + +[info] +INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info +INFO_COLORS=0x1f.0x31 + +[emacs] +INFOPATH=%/>;INFOPATH%%DJDIR%/info;%DJDIR%/gnu/emacs/info + +[less] +LESSBINFMT=*k<%X> +LESSCHARDEF=8bcccbcc12bc5b95.b127.b +LESS=%LESS% -h5$y5$Dd2.0$Du14.0$Ds4.7$Dk9.0$ + +[locate] ++LOCATE_PATH=%DJDIR%/lib/locatedb.dat + +[ls] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: +[dir] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: +[vdir] ++LS_COLORS=no=00:fi=00:di=36:lb=37;07:cd=40;33;01:ex=32:*.cmd=32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.deb=01;31:*.jpg=01;34:*.gif=01;34:*.bmp=01;34:*.ppm=01;34:*.tga=01;34:*.xbm=01;34:*.xpm=01;34:*.tif=01;34:*.mpg=01;37:*.avi=01;37:*.gl=01;37:*.dl=01;37:*~=08:*.bak=08: diff --git a/board/MAI/bios_emulator/scitech/bin/findint3.bat b/board/MAI/bios_emulator/scitech/bin/findint3.bat new file mode 100755 index 000000000..2e1506c2c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/findint3.bat @@ -0,0 +1 @@ +perl c:\scitech\src\perl\findint3.per diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh b/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh new file mode 100755 index 000000000..61ffd9350 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +# Setup for compiling with GCC/G++ for BeOS + +if [ "$CHECKED" = "1" ]; then + echo Checked debug build enabled. +else + echo Release build enabled. +fi + +export MAKESTARTUP=$SCITECH/makedefs/gcc_beos.mk +export INCLUDE="-Iinclude -I$SCITECH/include -I$PRIVATE/include" +export USE_X11=0 +export USE_BEOS=1 + +echo GCC BeOS console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh b/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh new file mode 100755 index 000000000..3816a5dca --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh @@ -0,0 +1,16 @@ +#! /bin/sh + +# Setup for compiling with GCC/G++ for FreeBSD + +if [ "$CHECKED" = "1" ]; then + echo Checked debug build enabled. +else + echo Release build enabled. +fi + +export MAKESTARTUP=$SCITECH/makedefs/gcc_freebsd.mk +export INCLUDE="-Iinclude -I$SCITECH/include -I$PRIVATE/include" +export USE_X11=1 +export USE_FREEBSD=1 + +echo GCC FreeBSD console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh b/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh new file mode 100755 index 000000000..27a4c4906 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh @@ -0,0 +1,19 @@ +#! /bin/sh + +# Setup for compiling with GCC/G++ for Linux + +if [ "$CHECKED" = "1" ]; then + echo Checked debug build enabled. +else + echo Release build enabled. +fi + +export MAKESTARTUP=$SCITECH/makedefs/gcc_linux.mk +export INCLUDE="include;$SCITECH/include;$PRIVATE/include" +export USE_LINUX=1 + +if [ "x$LIBC" = x ]; then + echo "GCC Linux console compilation environment set up (glib)" +else + echo "GCC Linux console compilation environment set up (libc5)" +fi diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat new file mode 100755 index 000000000..13c478369 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup for compiling with GNU C compiler + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2 +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2 +echo Checked debug build enabled. +goto setvars + +:setvars +set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include +set MAKESTARTUP=%SCITECH%\makedefs\gcc_win32.mk +set MAKE_MODE= +set USE_WIN16= +set USE_WIN32=1 +set WIN32_GUI= +set USE_SNAP= +set GCC_LIBBASE=gcc2 +PATH %SCITECH_BIN%;%GCC2_PATH%\NATIVE\BIN;%DEFPATH% + +echo GCC 2.9.x 32-bit Win32 console compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat new file mode 100755 index 000000000..97cb8bda1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat @@ -0,0 +1,28 @@ +@echo off +REM Setup for compiling with DJGPP 2.02 + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\release\dos32\dj2 +%SCITECH%\bin-dos\k_cp %SCITECH%\BIN\DJGPP.ENV %DJ_PATH%\DJGPP.ENV +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\debug\dos32\dj2 +%SCITECH%\bin-dos\k_cp %SCITECH%\BIN\DJGPP_DB.ENV %DJ_PATH%\DJGPP.ENV +echo Checked debug build enabled. +goto setvars + +:setvars +set DJGPP=%DJ_PATH%\DJGPP.ENV +set INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%DJ_PATH%\INCLUDE; +set MAKESTARTUP=%SCITECH%\MAKEDEFS\DJ32.MK +set USE_WIN16= +set USE_WIN32= +set WIN32_GUI= +set USE_SNAP= +set DJ_LIBBASE=dj2 +PATH %SCITECH_BIN%;%DJ_PATH%\BIN;%DEFPATH% + +echo DJGPP 2.02 32-bit DOS compilation environment set up (DPMI). + diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat new file mode 100755 index 000000000..ceb2ab84e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup for compiling with GNU C cross-compiler + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2 +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2 +echo Checked debug build enabled. +goto setvars + +:setvars +set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include +set MAKESTARTUP=%SCITECH%\MAKEDEFS\gcc_linux.mk +set MAKE_MODE=UNIX +set USE_WIN16= +set USE_WIN32= +set WIN32_GUI= +set USE_SNAP= +set GCC_LIBBASE=gcc2 +PATH %SCITECH_BIN%;%GCC2_PATH%\cross-linux\i386-redhat-linux\BIN;%DEFPATH% + +echo GCC 2.9.x 32-bit Linux console cross compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat new file mode 100755 index 000000000..bdb31aaf5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup for compiling with GNU C compiler + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\release\win32\gcc2 +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\debug\win32\gcc2 +echo Checked debug build enabled. +goto setvars + +:setvars +set INCLUDE=include;%SCITECH%\include;%PRIVATE%\include +set MAKESTARTUP=%SCITECH%\makedefs\gcc_win32.mk +set MAKE_MODE= +set USE_WIN16= +set USE_WIN32=1 +set WIN32_GUI=1 +set USE_SNAP= +set GCC_LIBBASE=gcc2 +PATH %SCITECH_BIN%;%GCC2_PATH%\NATIVE\BIN;%DEFPATH% + +echo GCC 2.9.x 32-bit Win32 GUI compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/makelib.bat b/board/MAI/bios_emulator/scitech/bin/makelib.bat new file mode 100755 index 000000000..631673483 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/makelib.bat @@ -0,0 +1,97 @@ +call wc11-d32.bat + +cd c:\private\src\license +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\pm +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\console +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\nucleus +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\zlib +dmake clean +dmake depend +dmake -u install + +cd c:\private\src\graphics\ref2d +dmake clean +dmake depend +dmake -u install +cd c:\private\src\drvlib +dmake clean +dmake depend +dmake -u install + +call wc11-w32.bat + +cd c:\private\src\license +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\pm +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\console +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\nucleus +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\zlib +dmake clean +dmake depend +dmake -u install + +cd c:\private\src\graphics\ref2d +dmake clean +dmake depend +dmake -u install +cd c:\private\src\drvlib +dmake clean +dmake depend +dmake -u install + +call wc10-d32.bat + +cd c:\private\src\license +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\pm +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\console +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\nucleus +dmake clean +dmake depend +dmake -u install +cd c:\scitech\src\zlib +dmake clean +dmake depend +dmake -u install + +cd c:\private\src\graphics\ref2d +dmake clean +dmake depend +dmake -u install +cd c:\private\src\drvlib +dmake clean +dmake depend +dmake -u install + +cd \private\src\graphics\drivers diff --git a/board/MAI/bios_emulator/scitech/bin/meltobjs.sh b/board/MAI/bios_emulator/scitech/bin/meltobjs.sh new file mode 100755 index 000000000..fd1804b70 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/meltobjs.sh @@ -0,0 +1,23 @@ +#! /bin/sh +# +# This script generates a single object file from a set of libraries (*.a files) +# Usage: meltobjs.sh target.o library1.a library2.a ... +# +# (C) SciTech Software, Inc. 1998 +# + +TMPDIR=/tmp/melt$$ +TARGET=$1 +TARGETDIR=$PWD +shift +mkdir $TMPDIR + +cd $TMPDIR + +for a in $* +do + ar x $a +done +ld -r -o $TARGETDIR/$TARGET *.o + +rm -fr $TMPDIR \ No newline at end of file diff --git a/board/MAI/bios_emulator/scitech/bin/ntddk.bat b/board/MAI/bios_emulator/scitech/bin/ntddk.bat new file mode 100755 index 000000000..07c0d7850 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/ntddk.bat @@ -0,0 +1,42 @@ +@echo off +REM: Set up environment variables for Microsoft Windows NT DDK development. +REM: Note that we have hard coded this for Windows NT i386 development. + +SET USE_NTDRV=1 +SET USE_W2KDRV= +SET BASEDIR=%NT_DDKROOT% +SET PATH=%BASEDIR%\bin;%PATH% +SET NTMAKEENV=%BASEDIR%\inc +SET BUILD_MAKE_PROGRAM=nmake.exe +SET BUILD_DEFAULT=-ei -nmake -i +SET BUILD_DEFAULT_TARGETS=-386 +SET _OBJ_DIR=obj +SET NEW_CRTS=1 +SET _NTROOT=%BASEDIR% +SET INCLUDE=%BASEDIR%\inc;%INCLUDE% + +if .%CHECKED%==.1 goto checked + +REM: set up an NT free build environment +SET DDKBUILDENV=free +SET C_DEFINES=-D_IDWBUILD +SET NTDBGFILES=1 +SET NTDEBUG= +SET NTDEBUGTYPE= +SET MSC_OPTIMIZATION= +set LIB=%BASEDIR%\lib\i386\free;%SCITECH_LIB%\LIB\RELEASE\NTDRV\VC6;%MSVCDir%\LIB;. + +goto done + +:checked + +REM: set up an NT checked build environment +SET DDKBUILDENV=checked +SET C_DEFINES=-D_IDWBUILD -DRDRDBG -DSRVDBG +SET NTDBGFILES= +SET NTDEBUG=ntsd +SET NTDEBUGTYPE=both +SET MSC_OPTIMIZATION=/Od /Oi +set LIB=%BASEDIR%\lib\i386\free;%SCITECH_LIB%\LIB\DEBUG\NTDRV\VC6;%MSVCDir%\LIB;. + +:done diff --git a/board/MAI/bios_emulator/scitech/bin/qnx4.sh b/board/MAI/bios_emulator/scitech/bin/qnx4.sh new file mode 100755 index 000000000..843c4d9fb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/qnx4.sh @@ -0,0 +1,18 @@ +#! /bin/sh + +# Setup for compiling with Watcom C/C++ for QNX4 + +if [ "$CHECKED" = "1" ]; then + echo Checked debug build enabled. +else + echo Release build enabled. +fi + +export MAKESTARTUP=$SCITECH/makedefs/qnx4.mk +export INCLUDE="-I$SCITECH/include -I$PRIVATE/include -I/usr/include" +export USE_QNX=1 +export USE_QNX4=1 +export WC_LIBBASE=wc10 + +echo Qnx 4 console compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/qnxnto.sh b/board/MAI/bios_emulator/scitech/bin/qnxnto.sh new file mode 100755 index 000000000..c114f9e33 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/qnxnto.sh @@ -0,0 +1,21 @@ +#! /bin/sh + +# Setup for compiling with Watcom C/C++ for QNX Neutrino + +if [ "$CHECKED" = "1" ]; then + echo Checked debug build enabled. +else + echo Release build enabled. +fi + +if [ X$GCC_PATH = "X" ]; then + export GCC_PATH=/usr/gcc/bin +fi + +export MAKESTARTUP=$SCITECH/makedefs/qnxnto.mk +export INCLUDE="-I$SCITECH/include -I$PRIVATE/include -I/usr/nto/include" +export USE_BIOS=1 # VBIOS lib is tiny under Neutrino, always include it +export USE_QNX=1 +export USE_QNXNTO=1 + +echo Qnx Neutrino console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh new file mode 100755 index 000000000..0a272d6a4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh @@ -0,0 +1,42 @@ +#! /bin/sh + +# BeOS VERSION +# Set the place where SciTech Software is installed, and where each +# of the supported compilers is installed. These environment variables +# are used by the batch files in the SCITECH\BIN directory. +# +# Modify the as appropriate for your compiler configuration (you should +# only need to change things in this batch file). +# +# This version is for a normal BeOS installation. + +# The SCITECH variable points to where batch files, makefile startups, +# include files and source files will be found when compiling. + +export SCITECH=$MGL_ROOT + +# The SCITECH_LIB variable points to where the SciTech libraries live +# for installation and linking. This allows you to have the source and +# include files on local machines for compiling and have the libraries +# located on a common network machine (for network builds). + +export SCITECH_LIB=$SCITECH + +# The PRIVATE variable points to where private source files reside that +# do not live in the public source tree + +export PRIVATE=$HOME/private + +# The following define the locations of all the compilers that you may +# be using. Change them to reflect where you have installed your +# compilers. + +export GCC_PATH=/boot/develop/tools/gnupro/bin + +# Add the Scitech bin path to the current PATH +export PATH=$SCITECH/bin:$SCITECH/bin-beos:$PATH +#if [ "x$LIBC" = x ]; then +# export PATH=$PATH:$SCITECH/bin-beos/glibc +#else +# export PATH=$PATH:$SCITECH/bin-beos/libc +#fi diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh new file mode 100755 index 000000000..c920748a7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh @@ -0,0 +1,37 @@ +#! /bin/sh + +# LINUX VERSION +# Set the place where SciTech Software is installed, and where each +# of the supported compilers is installed. These environment variables +# are used by the batch files in the SCITECH\BIN directory. +# +# Modify the as appropriate for your compiler configuration (you should +# only need to change things in this batch file). +# +# This version is for a normal Linux installation. + +# The SCITECH variable points to where batch files, makefile startups, +# include files and source files will be found when compiling. + +export SCITECH=$MGL_ROOT + +# The SCITECH_LIB variable points to where the SciTech libraries live +# for installation and linking. This allows you to have the source and +# include files on local machines for compiling and have the libraries +# located on a common network machine (for network builds). + +export SCITECH_LIB=$SCITECH + +# The PRIVATE variable points to where private source files reside that +# do not live in the public source tree + +export PRIVATE=$HOME/private + +# The following define the locations of all the compilers that you may +# be using. Change them to reflect where you have installed your +# compilers. + +export GCC_PATH=/usr/bin + +# Add the Scitech bin path to the current PATH +export PATH=$SCITECH/bin:$SCITECH/bin-freebsd:$PATH diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh new file mode 100755 index 000000000..35cbf1dc1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh @@ -0,0 +1,43 @@ +#! /bin/sh + +# LINUX VERSION +# Set the place where SciTech Software is installed, and where each +# of the supported compilers is installed. These environment variables +# are used by the batch files in the SCITECH\BIN directory. +# +# Modify the as appropriate for your compiler configuration (you should +# only need to change things in this batch file). +# +# This version is for a normal Linux installation. + +# The SCITECH variable points to where batch files, makefile startups, +# include files and source files will be found when compiling. + +export SCITECH=$MGL_ROOT + +# The SCITECH_LIB variable points to where the SciTech libraries live +# for installation and linking. This allows you to have the source and +# include files on local machines for compiling and have the libraries +# located on a common network machine (for network builds). + +export SCITECH_LIB=$SCITECH + +# The PRIVATE variable points to where private source files reside that +# do not live in the public source tree + +export PRIVATE=$HOME/private + +# The following define the locations of all the compilers that you may +# be using. Change them to reflect where you have installed your +# compilers. + +export GCC_PATH=/usr/bin +export TEMP=/tmp TMP=/tmp + +# Add the Scitech bin path to the current PATH +export PATH=$SCITECH/bin:$SCITECH/bin-linux:$PATH +if [ "x$LIBC" = x ]; then + export PATH=$SCITECH/bin-linux/glibc:$PATH +else + export PATH=$SCITECH/bin-linux/libc:$PATH +fi diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh new file mode 100755 index 000000000..1d73109ea --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh @@ -0,0 +1,37 @@ +#! /bin/sh + +# QNX 4 VERSION +# Set the place where SciTech Software is installed, and where each +# of the supported compilers is installed. These environment variables +# are used by the batch files in the SCITECH\BIN directory. +# +# Modify the as appropriate for your compiler configuration (you should +# only need to change things in this batch file). +# +# This version is for a normal Linux installation. + +# The SCITECH variable points to where batch files, makefile startups, +# include files and source files will be found when compiling. + +export SCITECH=$MGL_ROOT + +# The SCITECH_LIB variable points to where the SciTech libraries live +# for installation and linking. This allows you to have the source and +# include files on local machines for compiling and have the libraries +# located on a common network machine (for network builds). + +export SCITECH_LIB=$SCITECH + +# The PRIVATE variable points to where private source files reside that +# do not live in the public source tree + +export PRIVATE=$HOME/private + +# The following define the locations of all the compilers that you may +# be using. Change them to reflect where you have installed your +# compilers. + +export WC10_PATH=/usr/watcom/10.6/usr + +# Add the Scitech bin path to the current PATH +export PATH=$SCITECH/bin:$SCITECH/bin-qnx:$PATH diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars.bat b/board/MAI/bios_emulator/scitech/bin/set-vars.bat new file mode 100755 index 000000000..2a2101d4b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/set-vars.bat @@ -0,0 +1,110 @@ +@echo off +REM:========================================================================= +REM: Master batch file to set up all necessary environment variables for +REM: the SciTech makefile utilities. This batch file should be executed +REM: *first* before any other batch files when you start a command shell. +REM: You should not need to modify any batch files except this one to +REM: configure the makefile utilities. +REM:========================================================================= + +REM: Set the place where SciTech Software is installed, and where each +REM: of the supported compilers is installed. These environment variables +REM: are used by the batch files in the SCITECH\BIN directory. +REM: +REM: Modify the as appropriate for your compiler configuration (you should +REM: only need to change things in this batch file). +REM: +REM: This version is for a normal MSDOS installation. + +REM: The SCITECH variable points to where batch files, makefile startups, +REM: include files and source files will be found when compiling. + +SET SCITECH=c:\scitech + +REM: The SCITECH_LIB variable points to where the SciTech libraries live +REM: for installation and linking. This allows you to have the source and +REM: include files on local machines for compiling and have the libraries +REM: located on a common network machine (for network builds). + +SET SCITECH_LIB=%SCITECH% + +REM: The PRIVATE variable points to where private source files reside that +REM: do not live in the public source tree + +SET PRIVATE=c:\private + +REM: The following sets up the path to the SciTech command line utilities +REM: for the development operating system. We select either DOS hosted +REM: tools or Win32 hosted tools depending on whether you are running +REM: on NT or not. Windows 9x users can use the Win32 hosted tools but +REM: they run slower, but you will have long filenames if you do this. + +IF .%OS%==.Windows_NT goto Win32_path +IF NOT .%WINDIR%==. goto Win32_path +SET SCITECH_BIN=%SCITECH%\bin;%SCITECH%\bin-dos +goto path_set + +REM: The following sets up the path to the SciTech command line utilities +REM: for the development operating system. This version uses the Win32 +REM: hosted tools by default, so you can use long filenames. + +:Win32_path +SET SCITECH_BIN=%SCITECH%\bin;%SCITECH%\bin-win32 + +:path_set + +REM: Set the TMP variable for dmake if this is not already set + +SET TMP=%SCITECH% + +REM: Set the following environment variable to use the Netwide Assembler +REM: (NASM) provided with the MGL tools to build all assembler modules. +REM: If you have Turbo Assembler 4.0 or later and you wish to use it, +REM: you can use it by removing the following line. + +SET USE_NASM=1 + +REM: The following is used to set up DDK directories for device driver +REM: development. They can safely be ignored unless you are using the +REM: SciTech makefile utilities to build device drivers. + +SET DDKDRIVE=c: +SET MSSDK=c:\c\win32sdk +SET W95_DDKROOT=c:\c\95ddk +SET W98_DDKROOT=c:\c\98ddk +SET NT_DDKROOT=c:\c\ntddk +SET W2K_DDKROOT=c:\c\2000ddk +SET MASM_ROOT=c:\c\masm611 +SET VTOOLSD=c:\c\vtd95 +SET SOFTICE_PATH=c:\c\sint + +REM: The following define the locations of all the compilers that you may +REM: be using. Change them to reflect where you have installed your +REM: compilers. + +SET BC3_PATH=c:\c\bc3 +SET BC4_PATH=c:\c\bc45 +SET BC5_PATH=c:\c\bc50 +SET BCB5_PATH=c:\c\bcb50 +SET VC_PATH=c:\c\msvc +SET VC4_PATH=c:\c\vc42 +SET VC5_PATH=c:\c\vc50 +SET VC6_PATH=c:\c\vc60 +SET SC70_PATH=c:\c\sc75 +SET WC10A_PATH=c:\c\wc10a +SET WC10_PATH=c:\c\wc10 +SET WC11_PATH=c:\c\wc11 +SET TNT_PATH=c:\c\tnt +SET DJ_PATH=c:\c\djgpp +SET GCC2_PATH=c:\unix\usr + +REM: The following define the locations of the IDE and compiler path +REM: tools for Visual C++. If you do a standard installation, you wont +REM: need to change this. If however you did a custom install and changed +REM: the paths to these directory, you will need to modify this to suit. + +SET VC5_MSDevDir=%VC5_PATH%\sharedide +SET VC5_MSVCDir=%VC5_PATH%\vc +SET VC6_MSDevDir=%VC6_PATH%\common\msdev98 +SET VC6_MSVCDir=%VC6_PATH%\vc98 + diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat new file mode 100755 index 000000000..71f7d8e10 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat @@ -0,0 +1,36 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC4_PATH% +set C_INCLUDE=%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%VC4_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 4.2 32 bit Windows compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat new file mode 100755 index 000000000..9817493e3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat @@ -0,0 +1,27 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC4;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC4;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16 DOS bit compilation environment set up. + diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat new file mode 100755 index 000000000..62e35214e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat @@ -0,0 +1,21 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +REM: First setup for Win32 console development +call vc40-c32.bat > NUL + +REM: Extra stuff to set up for Windows 9x DDK development +set MASTER_MAKE=1 +set DDKROOT=%W95_DDKROOT% +set SDKROOT=%MSSDK% +set C16_ROOT=%VC_PATH% +set C32_ROOT=%VC4_PATH% + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 4.2 Windows 9x driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat new file mode 100755 index 000000000..83b67802d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat @@ -0,0 +1,18 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +REM: First setup for Win32 console development (with Platform SDK) +call vc40-c32.bat sdk > NUL + +REM: Extra stuff to set up for Windows NT DDK development +SET BASEDIR=%NT_DDKROOT% +SET PATH=%NT_DDKROOT%\bin;%PATH% + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 4.2 Windows NT driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat new file mode 100755 index 000000000..7997044f8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC4_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +set INIT=%VC4_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32= +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP=1 +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +echo Visual C++ 4.2 Snap compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat new file mode 100755 index 000000000..b0fc93675 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat @@ -0,0 +1,42 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\COFFLIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\COFFLIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC4_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +set INIT=%VC4_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_TNT= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +echo Visual C++ 4.2 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat new file mode 100755 index 000000000..2849a20e7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC4;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC4;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET VC_LIBBASE=VC4 +SET USE_RTTARGET= +SET USE_SNAP= +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16 bit Windows compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat new file mode 100755 index 000000000..d93a6246e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat @@ -0,0 +1,37 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC4;%VC4_PATH%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC4_PATH% +set C_INCLUDE=%VC4_PATH%\INCLUDE;%TNT_PATH%\INCLUDE; +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%VC4_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 4.2 32 bit Windows compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat new file mode 100755 index 000000000..a420a54ea --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat @@ -0,0 +1,20 @@ +@echo off +REM Setup environment variables for Visual C++ 4.2 32 bit edition + +SET LIB=%VC4_PATH%\LIB;. +SET TOOLROOTDIR=%VC4_PATH% +SET INCLUDE=\xc\include;%VC4_PATH%\INCLUDE +SET INIT=%VC4_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=VC4 +PATH %SCITECH_BIN%;%VC4_PATH%\BIN;%DEFPATH% + +echo Visual C++ 4.2 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat new file mode 100755 index 000000000..62d27b9bc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat @@ -0,0 +1,39 @@ +@echo off +REM Setup environment variables for Visual C++ 5.0 32 bit edition + +SET MSDevDir=%VC5_MSDevDir% +SET MSVCDir=%VC5_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE; +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 5.0 32-bit Windows console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat new file mode 100755 index 000000000..c789c5037 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC5;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC5;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat new file mode 100755 index 000000000..27a4a1439 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat @@ -0,0 +1,21 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +REM: First setup for Win32 console development +call vc60-c32.bat > NUL + +REM: Extra stuff to set up for Windows 9x DDK development +set MASTER_MAKE=1 +set DDKROOT=%W95_DDKROOT% +set SDKROOT=%MSSDK% +set C16_ROOT=%VC_PATH% +set C32_ROOT=%VC6_PATH% + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 6.0 Windows 9x driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat new file mode 100755 index 000000000..17b2f25cc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat @@ -0,0 +1,17 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +REM: First setup for Win32 console development (with Platform SDK) +call vc60-c32.bat sdk > NUL + +REM: Now setup stuff for the NT DDK build environment +call ntddk.bat + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 6.0 Windows NT driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat new file mode 100755 index 000000000..afb2fb186 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat @@ -0,0 +1,30 @@ +@echo off +REM Setup environment variables for Visual C++ 5.0 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC5_PATH%\VC +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC5_PATH%\VC\INCLUDE;%TNT_PATH%\INCLUDE; +set INIT=%VC5_PATH%\VC +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32= +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET=1 +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +echo Visual C++ 5.0 RTTarget-32 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat new file mode 100755 index 000000000..22d2e13c2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat @@ -0,0 +1,33 @@ +@echo off REM Setup environment variables for Visual C++ 5.0 32 bit +edition + +SET MSDevDir=%VC5_MSDevDir% +SET MSVCDir=%VC5_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32= +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP=1 +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +echo Visual C++ 5.0 Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat new file mode 100755 index 000000000..6b0919905 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat @@ -0,0 +1,42 @@ +@echo off +REM Setup environment variables for Visual C++ 5.0 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\COFFLIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC5;%VC5_PATH%\VC\LIB;%TNT_PATH%\COFFLIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC5_PATH%\VC +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC5_PATH%\VC\INCLUDE;%TNT_PATH%\INCLUDE; +set INIT=%VC5_PATH%\VC +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_TNT= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +echo Visual C++ 5.0 32-bit compilation environment set up (with TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat new file mode 100755 index 000000000..52ab495a3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat @@ -0,0 +1,27 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC5;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC5;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16-bit Windows compilation environment set up. + diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat new file mode 100755 index 000000000..07bc5e51d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat @@ -0,0 +1,39 @@ +@echo off +REM Setup environment variables for Visual C++ 5.0 32 bit edition + +SET MSDevDir=%VC5_MSDevDir% +SET MSVCDir=%VC5_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC5;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE; +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 5.0 32-bit Windows console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat new file mode 100755 index 000000000..fe286bd95 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat @@ -0,0 +1,20 @@ +@echo off +REM Setup environment variables for Visual C++ 5.0 32 bit edition + +SET LIB=%VC5_PATH%\VC\LIB;. +SET TOOLROOTDIR=%VC5_PATH%\VC +SET INCLUDE=\xc\include;%VC5_PATH%\VC\INCLUDE +SET INIT=%VC5_PATH%\VC +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc5 +PATH %SCITECH_BIN%;%VC5_PATH%\VC\BIN;%VC5_PATH%\SHAREDIDE\BIN;%DEFPATH% + +echo Visual C++ 5.0 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat new file mode 100755 index 000000000..e98417d61 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat @@ -0,0 +1,39 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +SET MSDevDir=%VC6_MSDevDir% +SET MSVCDir=%VC6_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 6.0 32-bit Windows console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat new file mode 100755 index 000000000..10855e06c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat @@ -0,0 +1,26 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\VC6;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\VC6;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat new file mode 100755 index 000000000..27a4a1439 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat @@ -0,0 +1,21 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +REM: First setup for Win32 console development +call vc60-c32.bat > NUL + +REM: Extra stuff to set up for Windows 9x DDK development +set MASTER_MAKE=1 +set DDKROOT=%W95_DDKROOT% +set SDKROOT=%MSSDK% +set C16_ROOT=%VC_PATH% +set C32_ROOT=%VC6_PATH% + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 6.0 Windows 9x driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat new file mode 100755 index 000000000..17b2f25cc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat @@ -0,0 +1,17 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +REM: First setup for Win32 console development (with Platform SDK) +call vc60-c32.bat sdk > NUL + +REM: Now setup stuff for the NT DDK build environment +call ntddk.bat + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 6.0 Windows NT driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat new file mode 100755 index 000000000..f30429327 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat @@ -0,0 +1,17 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +REM: First setup for Win32 console development (with Platform SDK) +call vc60-c32.bat sdk > NUL + +REM: Now setup stuff for the NT DDK build environment +call w2kddk.bat + +if .%CHECKED%==.1 goto checked_build +echo Release build enabled. +goto done +:checked_build +echo Checked debug build enabled. +goto done +:done +echo Visual C++ 6.0 Windows Windows 2000 driver compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat new file mode 100755 index 000000000..5348ef952 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +SET MSDevDir=%VC6_MSDevDir% +SET MSVCDir=%VC6_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32= +SET WIN32_GUI= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP=1 +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +echo Visual C++ 6.0 Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat new file mode 100755 index 000000000..1d8b5e303 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat @@ -0,0 +1,42 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC6;%VC6_PATH%\VC98\LIB;%TNT_PATH%\COFFLIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\VC6;%VC6_PATH%\VC98\LIB;%TNT_PATH%\COFFLIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC6_PATH%\VC98 +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC6_PATH%\VC98\INCLUDE;%TNT_PATH%\INCLUDE; +set INIT=%VC6_PATH%\VC98 +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_TNT= +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 PATH +%SCITECH_BIN%;%VC6_PATH%\VC98\BIN;%VC6_PATH%\COMMON\MSDEV98\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE= + +echo Visual C++ 6.0 32-bit compilation environment set up (with TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat new file mode 100755 index 000000000..70175c37a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat @@ -0,0 +1,27 @@ +@echo off +REM Setup environment variables for Visual C++ 1.52c 16 bit edition + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\VC6;%VC_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\VC6;%VC_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%VC_PATH% +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%VC_PATH%\INCLUDE; +set INIT=%VC_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%VC_PATH%\BIN;%DEFPATH%%VC_CD_PATH% + +echo Visual C++ 1.52c 16-bit Windows compilation environment set up. + diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat new file mode 100755 index 000000000..2f8e7ab9b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat @@ -0,0 +1,39 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +SET MSDevDir=%VC6_MSDevDir% +SET MSVCDir=%VC6_MSVCDir% + +if .%CHECKED%==.1 goto checked_build +set LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +set LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\VC6;%MSVCDir%\LIB;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +set TOOLROOTDIR=%MSVCDir% +set C_INCLUDE=%MSVCDir%\INCLUDE;%TNT_PATH%\INCLUDE +set INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +set INIT=%MSVCDir% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%MSVCDir%\BIN;%MSDevDir%\BIN;%TNT_PATH%\BIN;%DEFPATH%%VC32_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Visual C++ 6.0 32-bit Windows compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat new file mode 100755 index 000000000..57b23d204 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat @@ -0,0 +1,20 @@ +@echo off +REM Setup environment variables for Visual C++ 6.0 32 bit edition + +SET LIB=%VC6_PATH%\VC98\LIB;. +SET TOOLROOTDIR=%VC6_PATH%\VC98 +SET INCLUDE=\xc\include;%VC6_PATH%\VC98\INCLUDE; +SET INIT=%VC6_PATH%\VC98 +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\VC32.MK +SET USE_TNT= +SET USE_WIN16= +SET USE_WIN32=1 +SET WIN32_GUI=1 +SET USE_VXD= +SET USE_NTDRV= +SET USE_RTTARGET= +SET USE_SNAP= +SET VC_LIBBASE=vc6 +PATH %SCITECH_BIN%;%VC6_PATH%\VC98\BIN;%VC6_PATH%\COMMON\MSDEV98\BIN;%DEFPATH% + +echo Visual C++ 6.0 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/w2kddk.bat b/board/MAI/bios_emulator/scitech/bin/w2kddk.bat new file mode 100755 index 000000000..92858d162 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/w2kddk.bat @@ -0,0 +1,42 @@ +@echo off +REM: Set up environment variables for Microsoft Windows NT DDK development. +REM: Note that we have hard coded this for Windows NT i386 development. + +SET USE_NTDRV=1 +SET USE_W2KDRV=1 +SET BASEDIR=%W2K_DDKROOT% +SET PATH=%BASEDIR%\bin;%PATH% +SET NTMAKEENV=%BASEDIR%\inc +SET BUILD_MAKE_PROGRAM=nmake.exe +SET BUILD_DEFAULT=-ei -nmake -i +SET BUILD_DEFAULT_TARGETS=-386 +SET _OBJ_DIR=obj +SET NEW_CRTS=1 +SET _NTROOT=%BASEDIR% +SET INCLUDE=%BASEDIR%\inc;%BASEDIR%\inc\ddk;%INCLUDE% + +if .%CHECKED%==.1 goto checked + +REM: set up an NT free build environment +SET DDKBUILDENV=free +SET C_DEFINES=-D_IDWBUILD +SET NTDBGFILES=1 +SET NTDEBUG= +SET NTDEBUGTYPE= +SET MSC_OPTIMIZATION= +set LIB=%BASEDIR%\libfre\i386;%SCITECH_LIB%\LIB\RELEASE\W2KDRV\VC6;%MSVCDir%\LIB;. + +goto done + +:checked + +REM: set up an NT checked build environment +SET DDKBUILDENV=checked +SET C_DEFINES=-D_IDWBUILD -DRDRDBG -DSRVDBG +SET NTDBGFILES= +SET NTDEBUG=ntsd +SET NTDEBUGTYPE=both +SET MSC_OPTIMIZATION=/Od /Oi +set LIB=%BASEDIR%\libchk\i386;%SCITECH_LIB%\LIB\DEBUG\W2KDRV\VC6;%MSVCDir%\LIB;. + +:done diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat new file mode 100755 index 000000000..2d738f376 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 Win32 console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat new file mode 100755 index 000000000..5c53a90a1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat @@ -0,0 +1,30 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (DOS4GW) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\WIN; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat new file mode 100755 index 000000000..a5c721052 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (DOS4GW) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 32-bit DOS compilation environment set up (DOS4GW) + diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat new file mode 100755 index 000000000..579dece3b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 16-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os216\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os216\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216=1 +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc10 +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 16-bit OS/2 compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat new file mode 100755 index 000000000..3404b42a0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc10 +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 32-bit OS/2 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat new file mode 100755 index 000000000..57057de36 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI=1 +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc10 +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 32-bit OS/2 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat b/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat new file mode 100755 index 000000000..46f8659ce --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode (QNX 4) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\QNX4\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\QNX;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\QNX4\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\QNX;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\QH; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4=1 +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 32-bit QNX compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat b/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat new file mode 100755 index 000000000..1fde624f1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP=1 +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat b/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat new file mode 100755 index 000000000..d12f042fa --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat @@ -0,0 +1,46 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT;%TNT_PATH%\INCLUDE +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT=1 +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE=1 + +echo Watcom C/C++ 10.6 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat new file mode 100755 index 000000000..e8ba871bb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 16 bit Windows mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\WIN; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 16-bit Windows compilation environment set up. + diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat new file mode 100755 index 000000000..839bdde9c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10;%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10_PATH%\H;%WC10_PATH%\H\NT; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI=1 +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 Win32 GUI compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat b/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat new file mode 100755 index 000000000..fc783d814 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat @@ -0,0 +1,24 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.6 in 32 bit mode + +SET LIB=%WC10_PATH%\LIB386;%WC10_PATH%\LIB386\NT;. +SET EDPATH=%WC10_PATH%\EDDAT +SET INCLUDE=%WC10_PATH%\H;%WC10_PATH%\H\NT; +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI=1 +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC10 +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.6 X11 compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat new file mode 100755 index 000000000..6e0c24d5e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT; +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a Win32 console compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat b/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat new file mode 100755 index 000000000..f9ecb6727 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat @@ -0,0 +1,29 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode (DOS4GW) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC10A;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC10A;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\WIN; +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +SET EDPATH=%WC10A_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat new file mode 100755 index 000000000..d52b79a82 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat @@ -0,0 +1,32 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode (DOS4GW) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H; +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 32-bit DOS compilation environment set up (DOS4GW) diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat b/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat new file mode 100755 index 000000000..ba7351d0d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat @@ -0,0 +1,30 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 16-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os216\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os216\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10A_PATH%\h\os2;%WC10A_PATH%\h +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216=1 +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=wc10 +SET EDPATH=%WC10A_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 16-bit OS/2 compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat new file mode 100755 index 000000000..f3caa5959 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat @@ -0,0 +1,30 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10AA_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10AA_PATH%\h\os2;%WC10AA_PATH%\h +SET WATCOM=%WC10AA_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +SET EDPATH=%WC10AA_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10AA_PATH%\BINNT;%WC10AA6_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 32-bit OS/2 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat new file mode 100755 index 000000000..8d21c62ea --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat @@ -0,0 +1,30 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc10;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc10;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC10_PATH%\h\os2;%WC10_PATH%\h +SET WATCOM=%WC10_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI=1 +SET USE_SNAP= +SET WC_LIBBASE=WC10A +SET EDPATH=%WC10_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10_PATH%\BINNT;%WC10_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 32-bit OS/2 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat b/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat new file mode 100755 index 000000000..28f857c80 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP=1 +SET WC_LIBBASE=WC10A +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a Snap compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat b/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat new file mode 100755 index 000000000..a2b32193e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat @@ -0,0 +1,45 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT;%TNT_PATH%\INCLUDE +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT=1 +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE=1 + +echo Watcom C/C++ 10.0a 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat b/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat new file mode 100755 index 000000000..94011cc33 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 16 bit Windows mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC10A;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC10A;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\WIN; +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +SET EDPATH=%WC10A_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a 16-bit Windows compilation environment set up. + diff --git a/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat b/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat new file mode 100755 index 000000000..1e14dbc9f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 10.0a in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC10A;%WC10A_PATH%\LIB386;%WC10A_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC10A_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC10A_PATH%\H;%WC10A_PATH%\H\NT; +SET WATCOM=%WC10A_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI=1 +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET WC_LIBBASE=WC10A +PATH %SCITECH_BIN%;%WC10A_PATH%\BINNT;%WC10A_PATH%\BINB;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 10.0a Win32 GUI compilation environment set up diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat new file mode 100755 index 000000000..e75312927 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET C_INCLUDE=%WC11_PATH%\H;%WC11_PATH%\H\NT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Watcom C/C++ 11.0 Win32 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat new file mode 100755 index 000000000..4338adaef --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat @@ -0,0 +1,30 @@ +@echo off +REM SETup for compiling with Watcom C/C++ 11.0 in 16 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS16\WC11;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS16\WC11;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\WIN; +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16= +SET USE_WIN32= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +SET EDPATH=%WC11_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 16-bit DOS compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat new file mode 100755 index 000000000..e5a54d4bb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat @@ -0,0 +1,33 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode (DOS4GW) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H; +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 32-bit DOS compilation environment set up (DOS4GW). diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat new file mode 100755 index 000000000..d46754a3c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 16-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os216\wc11;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os216\wc11;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc16.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216=1 +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc11 +SET EDPATH=%WC11_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 16-bit OS/2 compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat new file mode 100755 index 000000000..37f5dc761 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc11;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc11;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc11 +SET EDPATH=%WC11_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 32-bit OS/2 console compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat new file mode 100755 index 000000000..348cbbda8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32-bit OS/2 mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\lib\release\os232\wc11;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\lib\debug\os232\wc11;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\eddat +SET INCLUDE=include;%SCITECH%\include;%PRIVATE%\include;%WC11_PATH%\h\os2;%WC11_PATH%\h +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\makedefs\wc32.mk +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232=1 +SET USE_OS2GUI=1 +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=wc11 +SET EDPATH=%WC11_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 32-bit OS/2 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat b/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat new file mode 100755 index 000000000..1fd60feea --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode (QNX 4) + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\QNX4\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\QNX;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\QNX4\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\QNX;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\QH; +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4=1 +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DJ_PATH%\BIN;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 32-bit QNX compilation environment set up + diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat b/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat new file mode 100755 index 000000000..6d2ac5783 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\SNAP\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\SNAP\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET WIN32_GUI= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP=1 +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 Snap compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat b/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat new file mode 100755 index 000000000..44dbf2484 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat @@ -0,0 +1,46 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode with Phar Lap TNT + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\DOS32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\DOS;%TNT_PATH%\LIB;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\NT;%TNT_PATH%\INCLUDE +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT=1 +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +REM If you set the following to a 1, a TNT DosStyle app will be created. +REM Otherwise a TNT NtStyle app will be created. NtStyle apps will *only* +REM run under real DOS when using our libraries, since we require access +REM to functions that the Win32 API does not support (such as direct access +REM to video memory, calling Int 10h BIOS functions etc). DosStyle apps +REM will however run fine in both DOS and a Win95 DOS box (NT DOS boxes don't +REM work too well). +REM +REM If you are using the RealTime DOS extender, your apps *must* be NtStyle, +REM and hence will never be able to run under Win95 or WinNT, only DOS. + +SET DOSSTYLE=1 + +echo Watcom C/C++ 11.0 32-bit DOS compilation environment set up (TNT). diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat new file mode 100755 index 000000000..e65c70e17 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat @@ -0,0 +1,31 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 16 bit Windows mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN16\WC11;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN16\WC11;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\WIN; +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC16.MK +SET USE_WIN16=1 +SET USE_WIN32= +SET USE_WIN386= +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +SET EDPATH=%WC11_PATH%\EDDAT +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 16-bit Windows compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat new file mode 100755 index 000000000..764cdbd11 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat @@ -0,0 +1,40 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET C_INCLUDE=%WC11_PATH%\H;%WC11_PATH%\H\NT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%C_INCLUDE% +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI=1 +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +REM: Enable Win32 SDK if desired (sdk on command line) +if NOT .%1%==.sdk goto done +call win32sdk.bat + +:done +echo Watcom C/C++ 11.0 Win32 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat b/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat new file mode 100755 index 000000000..c2569a3eb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat @@ -0,0 +1,34 @@ +@echo off +REM Setup for compiling with Watcom C/C++ 11.0 in 32 bit mode + +if .%CHECKED%==.1 goto checked_build +SET LIB=%SCITECH_LIB%\LIB\RELEASE\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Release build enabled. +goto setvars + +:checked_build +SET LIB=%SCITECH_LIB%\LIB\DEBUG\WIN32\WC11;%WC11_PATH%\LIB386;%WC11_PATH%\LIB386\NT;. +echo Checked debug build enabled. +goto setvars + +:setvars +SET EDPATH=%WC11_PATH%\EDDAT +SET INCLUDE=INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%WC11_PATH%\H;%WC11_PATH%\H\NT; +SET WATCOM=%WC11_PATH% +SET MAKESTARTUP=%SCITECH%\MAKEDEFS\WC32.MK +SET USE_TNT= +SET USE_X32= +SET USE_X32VM= +SET USE_WIN16= +SET USE_WIN32=1 +SET USE_WIN386= +SET WIN32_GUI=1 +SET USE_OS216= +SET USE_OS232= +SET USE_OS2GUI= +SET USE_SNAP= +SET USE_QNX4= +SET WC_LIBBASE=WC11 +PATH %SCITECH_BIN%;%WC11_PATH%\BINNT;%WC11_PATH%\BINW;%DEFPATH%%WC_CD_PATH% + +echo Watcom C/C++ 11.0 Win32 GUI compilation environment set up. diff --git a/board/MAI/bios_emulator/scitech/bin/win32sdk.bat b/board/MAI/bios_emulator/scitech/bin/win32sdk.bat new file mode 100755 index 000000000..3c7f017cb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/bin/win32sdk.bat @@ -0,0 +1,20 @@ +@echo off +REM: Set up environment variables for Microsoft Platform SDK development +REM: Note that we have hard coded this for Windows NT i386 development. + +SET MSTOOLS=%MSSDK% +SET DXSDKROOT=%MSTOOLS% +SET INETSDK=%MSTOOLS% +SET BKOFFICE=%MSTOOLS% +SET BASEMAKE=%BKOFFICE%\INCLUDE\BKOffice.Mak +SET INCLUDE=.;INCLUDE;%SCITECH%\INCLUDE;%PRIVATE%\INCLUDE;%MSTOOLS%\INCLUDE;%C_INCLUDE% +if .%1%==.borland goto borland +SET LIB=%MSTOOLS%\LIB;%LIB% +goto notborland +:borland +SET LIB=%MSTOOLS%\LIB\BORLAND;%LIB% +:notborland +SET PATH=%MSTOOLS%\Bin\;%MSTOOLS%\Bin\WinNT;%PATH% +SET CPU=i386 + +echo Microsoft Platform SDK support enbabled. diff --git a/board/MAI/bios_emulator/scitech/include/biosemu.h b/board/MAI/bios_emulator/scitech/include/biosemu.h new file mode 100644 index 000000000..82c33a7c1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/biosemu.h @@ -0,0 +1,154 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for the real mode x86 BIOS emulator, which is +* used to warmboot any number of VGA compatible PCI/AGP +* controllers under any OS, on any processor family that +* supports PCI. We also allow the user application to call +* real mode BIOS functions and Int 10h functions (including +* the VESA BIOS). +* +****************************************************************************/ + +#ifndef __BIOSEMU_H +#define __BIOSEMU_H + +#include "x86emu.h" +#include "pmapi.h" +#include "pcilib.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/**************************************************************************** +REMARKS: +Data structure used to describe the details specific to a particular VGA +controller. This information is used to allow the VGA controller to be +swapped on the fly within the BIOS emulator. + +HEADER: +biosemu.h + +MEMBERS: +pciInfo - PCI device information block for the controller +BIOSImage - Pointer to a read/write copy of the BIOS image +BIOSImageLen - Length of the BIOS image +LowMem - Copy of key low memory areas +****************************************************************************/ +typedef struct { + PCIDeviceInfo *pciInfo; + void *BIOSImage; + ulong BIOSImageLen; + uchar LowMem[1536]; + } BE_VGAInfo; + +/**************************************************************************** +REMARKS: +Data structure used to describe the details for the BIOS emulator system +environment as used by the X86 emulator library. + +HEADER: +biosemu.h + +MEMBERS: +vgaInfo - VGA BIOS information structure +biosmem_base - Base of the BIOS image +biosmem_limit - Limit of the BIOS image +busmem_base - Base of the VGA bus memory +****************************************************************************/ +typedef struct { + BE_VGAInfo vgaInfo; + ulong biosmem_base; + ulong biosmem_limit; + ulong busmem_base; + } BE_sysEnv; + +/**************************************************************************** +REMARKS: +Structure defining all the BIOS Emulator API functions as exported from +the Binary Portable DLL. +{secret} +****************************************************************************/ +typedef struct { + ulong dwSize; + ibool (PMAPIP BE_init)(u32 debugFlags,int memSize,BE_VGAInfo *info); + void (PMAPIP BE_setVGA)(BE_VGAInfo *info); + void (PMAPIP BE_getVGA)(BE_VGAInfo *info); + void * (PMAPIP BE_mapRealPointer)(uint r_seg,uint r_off); + void * (PMAPIP BE_getVESABuf)(uint *len,uint *rseg,uint *roff); + void (PMAPIP BE_callRealMode)(uint seg,uint off,RMREGS *regs,RMSREGS *sregs); + int (PMAPIP BE_int86)(int intno,RMREGS *in,RMREGS *out); + int (PMAPIP BE_int86x)(int intno,RMREGS *in,RMREGS *out,RMSREGS *sregs); + void * reserved1; + void (PMAPIP BE_exit)(void); + } BE_exports; + +/**************************************************************************** +REMARKS: +Function pointer type for the Binary Portable DLL initialisation entry point. +{secret} +****************************************************************************/ +typedef BE_exports * (PMAPIP BE_initLibrary_t)(PM_imports *PMImp); + +#pragma pack() + +/*---------------------------- Global variables ---------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* {secret} Global BIOS emulator system environment */ +extern BE_sysEnv _BE_env; + +/*-------------------------- Function Prototypes --------------------------*/ + +/* BIOS emulator library entry points */ + +ibool PMAPI BE_init(u32 debugFlags,int memSize,BE_VGAInfo *info); +void PMAPI BE_setVGA(BE_VGAInfo *info); +void PMAPI BE_getVGA(BE_VGAInfo *info); +void PMAPI BE_setDebugFlags(u32 debugFlags); +void * PMAPI BE_mapRealPointer(uint r_seg,uint r_off); +void * PMAPI BE_getVESABuf(uint *len,uint *rseg,uint *roff); +void PMAPI BE_callRealMode(uint seg,uint off,RMREGS *regs,RMSREGS *sregs); +int PMAPI BE_int86(int intno,RMREGS *in,RMREGS *out); +int PMAPI BE_int86x(int intno,RMREGS *in,RMREGS *out,RMSREGS *sregs); +void PMAPI BE_exit(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __BIOSEMU_H */ diff --git a/board/MAI/bios_emulator/scitech/include/event.h b/board/MAI/bios_emulator/scitech/include/event.h new file mode 100644 index 000000000..beeac8764 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/event.h @@ -0,0 +1,696 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Header file for the SciTech cross platform event library +* +****************************************************************************/ + +#ifndef __EVENT_H +#define __EVENT_H + +#include "scitech.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/* 'C' calling conventions always */ + +#define EVTAPI _ASMAPI +#define EVTAPIP _ASMAPIP + +/* Event message masks for keyDown events */ + +#define EVT_ASCIIMASK 0x00FF /* ASCII code of key pressed */ +#define EVT_SCANMASK 0xFF00 /* Scan code of key pressed */ +#define EVT_COUNTMASK 0x7FFF0000L /* Count for KEYREPEAT's */ + +/* Macros to extract values from the message fields */ + +#define EVT_asciiCode(m) ( (uchar) (m & EVT_ASCIIMASK) ) +#define EVT_scanCode(m) ( (uchar) ( (m & EVT_SCANMASK) >> 8 ) ) +#define EVT_repeatCount(m) ( (short) ( (m & EVT_COUNTMASK) >> 16 ) ) + +/**************************************************************************** +REMARKS: +Defines the set of ASCII codes reported by the event library functions +in the message field. Use the EVT_asciiCode macro to extract the code +from the event structure. + +HEADER: +event.h +****************************************************************************/ +typedef enum { + ASCII_ctrlA = 0x01, + ASCII_ctrlB = 0x02, + ASCII_ctrlC = 0x03, + ASCII_ctrlD = 0x04, + ASCII_ctrlE = 0x05, + ASCII_ctrlF = 0x06, + ASCII_ctrlG = 0x07, + ASCII_backspace = 0x08, + ASCII_ctrlH = 0x08, + ASCII_tab = 0x09, + ASCII_ctrlI = 0x09, + ASCII_ctrlJ = 0x0A, + ASCII_ctrlK = 0x0B, + ASCII_ctrlL = 0x0C, + ASCII_enter = 0x0D, + ASCII_ctrlM = 0x0D, + ASCII_ctrlN = 0x0E, + ASCII_ctrlO = 0x0F, + ASCII_ctrlP = 0x10, + ASCII_ctrlQ = 0x11, + ASCII_ctrlR = 0x12, + ASCII_ctrlS = 0x13, + ASCII_ctrlT = 0x14, + ASCII_ctrlU = 0x15, + ASCII_ctrlV = 0x16, + ASCII_ctrlW = 0x17, + ASCII_ctrlX = 0x18, + ASCII_ctrlY = 0x19, + ASCII_ctrlZ = 0x1A, + ASCII_esc = 0x1B, + ASCII_space = 0x20, + ASCII_exclamation = 0x21, /* ! */ + ASCII_quote = 0x22, /* " */ + ASCII_pound = 0x23, /* # */ + ASCII_dollar = 0x24, /* $ */ + ASCII_percent = 0x25, /* % */ + ASCII_ampersand = 0x26, /* & */ + ASCII_apostrophe = 0x27, /* ' */ + ASCII_leftBrace = 0x28, /* ( */ + ASCII_rightBrace = 0x29, /* ) */ + ASCII_times = 0x2A, /* * */ + ASCII_plus = 0x2B, /* + */ + ASCII_comma = 0x2C, /* , */ + ASCII_minus = 0x2D, /* - */ + ASCII_period = 0x2E, /* . */ + ASCII_divide = 0x2F, /* / */ + ASCII_0 = 0x30, + ASCII_1 = 0x31, + ASCII_2 = 0x32, + ASCII_3 = 0x33, + ASCII_4 = 0x34, + ASCII_5 = 0x35, + ASCII_6 = 0x36, + ASCII_7 = 0x37, + ASCII_8 = 0x38, + ASCII_9 = 0x39, + ASCII_colon = 0x3A, /* : */ + ASCII_semicolon = 0x3B, /* ; */ + ASCII_lessThan = 0x3C, /* < */ + ASCII_equals = 0x3D, /* = */ + ASCII_greaterThan = 0x3E, /* > */ + ASCII_question = 0x3F, /* ? */ + ASCII_at = 0x40, /* @ */ + ASCII_A = 0x41, + ASCII_B = 0x42, + ASCII_C = 0x43, + ASCII_D = 0x44, + ASCII_E = 0x45, + ASCII_F = 0x46, + ASCII_G = 0x47, + ASCII_H = 0x48, + ASCII_I = 0x49, + ASCII_J = 0x4A, + ASCII_K = 0x4B, + ASCII_L = 0x4C, + ASCII_M = 0x4D, + ASCII_N = 0x4E, + ASCII_O = 0x4F, + ASCII_P = 0x50, + ASCII_Q = 0x51, + ASCII_R = 0x52, + ASCII_S = 0x53, + ASCII_T = 0x54, + ASCII_U = 0x55, + ASCII_V = 0x56, + ASCII_W = 0x57, + ASCII_X = 0x58, + ASCII_Y = 0x59, + ASCII_Z = 0x5A, + ASCII_leftSquareBrace = 0x5B, /* [ */ + ASCII_backSlash = 0x5C, /* \ */ + ASCII_rightSquareBrace = 0x5D, /* ] */ + ASCII_caret = 0x5E, /* ^ */ + ASCII_underscore = 0x5F, /* _ */ + ASCII_leftApostrophe = 0x60, /* ` */ + ASCII_a = 0x61, + ASCII_b = 0x62, + ASCII_c = 0x63, + ASCII_d = 0x64, + ASCII_e = 0x65, + ASCII_f = 0x66, + ASCII_g = 0x67, + ASCII_h = 0x68, + ASCII_i = 0x69, + ASCII_j = 0x6A, + ASCII_k = 0x6B, + ASCII_l = 0x6C, + ASCII_m = 0x6D, + ASCII_n = 0x6E, + ASCII_o = 0x6F, + ASCII_p = 0x70, + ASCII_q = 0x71, + ASCII_r = 0x72, + ASCII_s = 0x73, + ASCII_t = 0x74, + ASCII_u = 0x75, + ASCII_v = 0x76, + ASCII_w = 0x77, + ASCII_x = 0x78, + ASCII_y = 0x79, + ASCII_z = 0x7A, + ASCII_leftCurlyBrace = 0x7B, /* { */ + ASCII_verticalBar = 0x7C, /* | */ + ASCII_rightCurlyBrace = 0x7D, /* } */ + ASCII_tilde = 0x7E /* ~ */ + } EVT_asciiCodesType; + +/**************************************************************************** +REMARKS: +Defines the set of scan codes reported by the event library functions +in the message field. Use the EVT_scanCode macro to extract the code +from the event structure. Note that the scan codes reported will be the +same across all keyboards (assuming the placement of keys on a 101 key US +keyboard), but the translated ASCII values may be different depending on +the country code pages in use. + +NOTE: Scan codes in the event library are not really hardware scan codes, + but rather virtual scan codes as generated by a low level keyboard + interface driver. All virtual codes begin with scan code 0x60 and + range up from there. + +HEADER: +event.h +****************************************************************************/ +typedef enum { + KB_padEnter = 0x60, /* Keypad keys */ + KB_padMinus = 0x4A, + KB_padPlus = 0x4E, + KB_padTimes = 0x37, + KB_padDivide = 0x61, + KB_padLeft = 0x62, + KB_padRight = 0x63, + KB_padUp = 0x64, + KB_padDown = 0x65, + KB_padInsert = 0x66, + KB_padDelete = 0x67, + KB_padHome = 0x68, + KB_padEnd = 0x69, + KB_padPageUp = 0x6A, + KB_padPageDown = 0x6B, + KB_padCenter = 0x4C, + KB_F1 = 0x3B, /* Function keys */ + KB_F2 = 0x3C, + KB_F3 = 0x3D, + KB_F4 = 0x3E, + KB_F5 = 0x3F, + KB_F6 = 0x40, + KB_F7 = 0x41, + KB_F8 = 0x42, + KB_F9 = 0x43, + KB_F10 = 0x44, + KB_F11 = 0x57, + KB_F12 = 0x58, + KB_left = 0x4B, /* Cursor control keys */ + KB_right = 0x4D, + KB_up = 0x48, + KB_down = 0x50, + KB_insert = 0x52, + KB_delete = 0x53, + KB_home = 0x47, + KB_end = 0x4F, + KB_pageUp = 0x49, + KB_pageDown = 0x51, + KB_capsLock = 0x3A, + KB_numLock = 0x45, + KB_scrollLock = 0x46, + KB_leftShift = 0x2A, + KB_rightShift = 0x36, + KB_leftCtrl = 0x1D, + KB_rightCtrl = 0x6C, + KB_leftAlt = 0x38, + KB_rightAlt = 0x6D, + KB_leftWindows = 0x5B, + KB_rightWindows = 0x5C, + KB_menu = 0x5D, + KB_sysReq = 0x54, + KB_esc = 0x01, /* Normal keyboard keys */ + KB_1 = 0x02, + KB_2 = 0x03, + KB_3 = 0x04, + KB_4 = 0x05, + KB_5 = 0x06, + KB_6 = 0x07, + KB_7 = 0x08, + KB_8 = 0x09, + KB_9 = 0x0A, + KB_0 = 0x0B, + KB_minus = 0x0C, + KB_equals = 0x0D, + KB_backSlash = 0x2B, + KB_backspace = 0x0E, + KB_tab = 0x0F, + KB_Q = 0x10, + KB_W = 0x11, + KB_E = 0x12, + KB_R = 0x13, + KB_T = 0x14, + KB_Y = 0x15, + KB_U = 0x16, + KB_I = 0x17, + KB_O = 0x18, + KB_P = 0x19, + KB_leftSquareBrace = 0x1A, + KB_rightSquareBrace = 0x1B, + KB_enter = 0x1C, + KB_A = 0x1E, + KB_S = 0x1F, + KB_D = 0x20, + KB_F = 0x21, + KB_G = 0x22, + KB_H = 0x23, + KB_J = 0x24, + KB_K = 0x25, + KB_L = 0x26, + KB_semicolon = 0x27, + KB_apostrophe = 0x28, + KB_Z = 0x2C, + KB_X = 0x2D, + KB_C = 0x2E, + KB_V = 0x2F, + KB_B = 0x30, + KB_N = 0x31, + KB_M = 0x32, + KB_comma = 0x33, + KB_period = 0x34, + KB_divide = 0x35, + KB_space = 0x39, + KB_tilde = 0x29 + } EVT_scanCodesType; + +/**************************************************************************** +REMARKS: +Defines the mask for the joystick axes that are present + +HEADER: +event.h + +MEMBERS: +EVT_JOY_AXIS_X1 - Joystick 1, X axis is present +EVT_JOY_AXIS_Y1 - Joystick 1, Y axis is present +EVT_JOY_AXIS_X2 - Joystick 2, X axis is present +EVT_JOY_AXIS_Y2 - Joystick 2, Y axis is present +EVT_JOY_AXIS_ALL - Mask for all axes +****************************************************************************/ +typedef enum { + EVT_JOY_AXIS_X1 = 0x00000001, + EVT_JOY_AXIS_Y1 = 0x00000002, + EVT_JOY_AXIS_X2 = 0x00000004, + EVT_JOY_AXIS_Y2 = 0x00000008, + EVT_JOY_AXIS_ALL = 0x0000000F + } EVT_eventJoyAxisType; + +/**************************************************************************** +REMARKS: +Defines the event message masks for joystick events + +HEADER: +event.h + +MEMBERS: +EVT_JOY1_BUTTONA - Joystick 1, button A is down +EVT_JOY1_BUTTONB - Joystick 1, button B is down +EVT_JOY2_BUTTONA - Joystick 2, button A is down +EVT_JOY2_BUTTONB - Joystick 2, button B is down +****************************************************************************/ +typedef enum { + EVT_JOY1_BUTTONA = 0x00000001, + EVT_JOY1_BUTTONB = 0x00000002, + EVT_JOY2_BUTTONA = 0x00000004, + EVT_JOY2_BUTTONB = 0x00000008 + } EVT_eventJoyMaskType; + +/**************************************************************************** +REMARKS: +Defines the event message masks for mouse events + +HEADER: +event.h + +MEMBERS: +EVT_LEFTBMASK - Left button is held down +EVT_RIGHTBMASK - Right button is held down +EVT_MIDDLEBMASK - Middle button is held down +EVT_BOTHBMASK - Both left and right held down together +EVT_ALLBMASK - All buttons pressed +EVT_DBLCLICK - Set if mouse down event was a double click +****************************************************************************/ +typedef enum { + EVT_LEFTBMASK = 0x00000001, + EVT_RIGHTBMASK = 0x00000002, + EVT_MIDDLEBMASK = 0x00000004, + EVT_BOTHBMASK = 0x00000007, + EVT_ALLBMASK = 0x00000007, + EVT_DBLCLICK = 0x00010000 + } EVT_eventMouseMaskType; + +/**************************************************************************** +REMARKS: +Defines the event modifier masks. These are the masks used to extract +the modifier information from the modifiers field of the event_t structure. +Note that the values in the modifiers field represent the values of these +modifier keys at the time the event occurred, not the time you decided +to process the event. + +HEADER: +event.h + +MEMBERS: +EVT_LEFTBUT - Set if left mouse button was down +EVT_RIGHTBUT - Set if right mouse button was down +EVT_MIDDLEBUT - Set if the middle button was down +EVT_RIGHTSHIFT - Set if right shift was down +EVT_LEFTSHIFT - Set if left shift was down +EVT_RIGHTCTRL - Set if right ctrl key was down +EVT_RIGHTALT - Set if right alt key was down +EVT_LEFTCTRL - Set if left ctrl key was down +EVT_LEFTALT - Set if left alt key was down +EVT_SHIFTKEY - Mask for any shift key down +EVT_CTRLSTATE - Set if ctrl key was down +EVT_ALTSTATE - Set if alt key was down +EVT_CAPSLOCK - Caps lock is active +EVT_NUMLOCK - Num lock is active +EVT_SCROLLLOCK - Scroll lock is active +****************************************************************************/ +typedef enum { + EVT_LEFTBUT = 0x00000001, + EVT_RIGHTBUT = 0x00000002, + EVT_MIDDLEBUT = 0x00000004, + EVT_RIGHTSHIFT = 0x00000008, + EVT_LEFTSHIFT = 0x00000010, + EVT_RIGHTCTRL = 0x00000020, + EVT_RIGHTALT = 0x00000040, + EVT_LEFTCTRL = 0x00000080, + EVT_LEFTALT = 0x00000100, + EVT_SHIFTKEY = 0x00000018, + EVT_CTRLSTATE = 0x000000A0, + EVT_ALTSTATE = 0x00000140, + EVT_SCROLLLOCK = 0x00000200, + EVT_NUMLOCK = 0x00000400, + EVT_CAPSLOCK = 0x00000800 + } EVT_eventModMaskType; + +/**************************************************************************** +REMARKS: +Defines the event codes returned in the event_t structures what field. Note +that these are defined as a set of mutually exlusive bit fields, so you +can test for multiple event types using the combined event masks defined +in the EVT_eventMaskType enumeration. + +HEADER: +event.h + +MEMBERS: +EVT_NULLEVT - A null event +EVT_KEYDOWN - Key down event +EVT_KEYREPEAT - Key repeat event +EVT_KEYUP - Key up event +EVT_MOUSEDOWN - Mouse down event +EVT_MOUSEAUTO - Mouse down autorepeat event +EVT_MOUSEUP - Mouse up event +EVT_MOUSEMOVE - Mouse movement event +EVT_JOYCLICK - Joystick button state change event +EVT_JOYMOVE - Joystick movement event +EVT_USEREVT - First user event +****************************************************************************/ +typedef enum { + EVT_NULLEVT = 0x00000000, + EVT_KEYDOWN = 0x00000001, + EVT_KEYREPEAT = 0x00000002, + EVT_KEYUP = 0x00000004, + EVT_MOUSEDOWN = 0x00000008, + EVT_MOUSEAUTO = 0x00000010, + EVT_MOUSEUP = 0x00000020, + EVT_MOUSEMOVE = 0x00000040, + EVT_JOYCLICK = 0x00000080, + EVT_JOYMOVE = 0x00000100, + EVT_USEREVT = 0x00000200 + } EVT_eventType; + +/**************************************************************************** +REMARKS: +Defines the event code masks you can use to test for multiple types of +events, since the event codes are mutually exlusive bit fields. + +HEADER: +event.h + +MEMBERS: +EVT_KEYEVT - Mask for any key event +EVT_MOUSEEVT - Mask for any mouse event +EVT_MOUSECLICK - Mask for any mouse click event +EVT_JOYEVT - Mask for any joystick event +EVT_EVERYEVT - Mask for any event +****************************************************************************/ +typedef enum { + EVT_KEYEVT = (EVT_KEYDOWN | EVT_KEYREPEAT | EVT_KEYUP), + EVT_MOUSEEVT = (EVT_MOUSEDOWN | EVT_MOUSEAUTO | EVT_MOUSEUP | EVT_MOUSEMOVE), + EVT_MOUSECLICK = (EVT_MOUSEDOWN | EVT_MOUSEUP), + EVT_JOYEVT = (EVT_JOYCLICK | EVT_JOYMOVE), + EVT_EVERYEVT = 0x7FFFFFFF + } EVT_eventMaskType; + +/**************************************************************************** +REMARKS: +Structure describing the information contained in an event extracted from +the event queue. + +HEADER: +event.h + +MEMBERS: +which - Window identifier for message for use by high level window manager + code (i.e. MegaVision GUI or Windows API). +what - Type of event that occurred. Will be one of the values defined by + the EVT_eventType enumeration. +when - Time that the event occurred in milliseconds since startup +where_x - X coordinate of the mouse cursor location at the time of the event + (in screen coordinates). For joystick events this represents + the position of the first joystick X axis. +where_y - Y coordinate of the mouse cursor location at the time of the event + (in screen coordinates). For joystick events this represents + the position of the first joystick Y axis. +relative_x - Relative movement of the mouse cursor in the X direction (in + units of mickeys, or 1/200th of an inch). For joystick events + this represents the position of the second joystick X axis. +relative_y - Relative movement of the mouse cursor in the Y direction (in + units of mickeys, or 1/200th of an inch). For joystick events + this represents the position of the second joystick Y axis. +message - Event specific message for the event. For use events this can be + any user specific information. For keyboard events this contains + the ASCII code in bits 0-7, the keyboard scan code in bits 8-15 and + the character repeat count in bits 16-30. You can use the + EVT_asciiCode, EVT_scanCode and EVT_repeatCount macros to extract + this information from the message field. For mouse events this + contains information about which button was pressed, and will be a + combination of the flags defined by the EVT_eventMouseMaskType + enumeration. For joystick events, this conatins information + about which buttons were pressed, and will be a combination of + the flags defined by the EVT_eventJoyMaskType enumeration. +modifiers - Contains additional information about the state of the keyboard + shift modifiers (Ctrl, Alt and Shift keys) when the event + occurred. For mouse events it will also contain the state of + the mouse buttons. Will be a combination of the values defined + by the EVT_eventModMaskType enumeration. +next - Internal use; do not use. +prev - Internal use; do not use. +****************************************************************************/ +typedef struct { + ulong which; + ulong what; + ulong when; + int where_x; + int where_y; + int relative_x; + int relative_y; + ulong message; + ulong modifiers; + int next; + int prev; + } event_t; + +/**************************************************************************** +REMARKS: +Structure describing an entry in the code page table. A table of translation +codes for scan codes to ASCII codes is provided in this table to be used +by the keyboard event libraries. On some OS'es the keyboard translation is +handled by the OS, but for DOS and embedded systems you must register a +different code page translation table if you want to support keyboards +other than the US English keyboard (the default). + +NOTE: Entries in code page tables *must* be in ascending order for the + scan codes as we do a binary search on the tables for the ASCII + code equivalents. + +HEADER: +event.h + +MEMBERS: +scanCode - Scan code to translate (really the virtual scan code). +asciiCode - ASCII code for this scan code. +****************************************************************************/ +typedef struct { + uchar scanCode; + uchar asciiCode; + } codepage_entry_t; + +/**************************************************************************** +REMARKS: +Structure describing a complete code page translation table. The table +contains translation tables for normal keys, shifted keys and ctrl keys. +The Ctrl key always has precedence over the shift table, and the shift +table is used when the shift key is down or the CAPSLOCK key is down. + +HEADER: +event.h + +MEMBERS: +name - Name of the code page table (ie: "US English") +normal - Code page for translating normal keys +normalLen - Length of normal translation table +caps - Code page for translating keys when CAPSLOCK is down +capsLen - Length of CAPSLOCK translation table +shift - Code page for shifted keys (ie: shift key is held down) +shiftLen - Length of shifted translation table +shiftCaps - Code page for shifted keys when CAPSLOCK is down +shiftCapsLen - Length of shifted CAPSLOCK translation table +ctrl - Code page for ctrl'ed keys (ie: ctrl key is held down) +ctrlLen - Length of ctrl'ed translation table +numPad - Code page for NUMLOCK'ed keypad keys +numPadLen - Length of NUMLOCK'ed translation table +****************************************************************************/ +typedef struct { + char name[20]; + codepage_entry_t *normal; + int normalLen; + codepage_entry_t *caps; + int capsLen; + codepage_entry_t *shift; + int shiftLen; + codepage_entry_t *shiftCaps; + int shiftCapsLen; + codepage_entry_t *ctrl; + int ctrlLen; + codepage_entry_t *numPad; + int numPadLen; + } codepage_t; + +/* {secret} */ +typedef ibool (EVTAPIP _EVT_userEventFilter)(event_t *evt); +/* {secret} */ +typedef void (EVTAPIP _EVT_mouseMoveHandler)(int x,int y); +/* {secret} */ +typedef void (EVTAPIP _EVT_heartBeatCallback)(void *params); + +/* Macro to find the size of a static array */ + +#define EVT_ARR_SIZE(a) (sizeof(a)/sizeof((a)[0])) + +#pragma pack() + +/*--------------------------- Global variables ----------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Standard code page tables */ + +extern codepage_t _CP_US_English; + +/*------------------------- Function Prototypes ---------------------------*/ + +/* Public API functions for user applications */ + +ibool EVTAPI EVT_getNext(event_t *evt,ulong mask); +ibool EVTAPI EVT_peekNext(event_t *evt,ulong mask); +ibool EVTAPI EVT_post(ulong which,ulong what,ulong message,ulong modifiers); +void EVTAPI EVT_flush(ulong mask); +void EVTAPI EVT_halt(event_t *evt,ulong mask); +ibool EVTAPI EVT_isKeyDown(uchar scanCode); +void EVTAPI EVT_setMousePos(int x,int y); +void EVTAPI EVT_getMousePos(int *x,int *y); + +/* Function to enable/disable updating of keyboard LED status indicators */ + +void EVTAPI EVT_allowLEDS(ibool enable); + +/* Function to install a custom keyboard code page. Default is US English */ + +codepage_t *EVTAPI EVT_getCodePage(void); +void EVTAPI EVT_setCodePage(codepage_t *page); + +/* Functions for fine grained joystick calibration */ + +void EVTAPI EVT_pollJoystick(void); +int EVTAPI EVT_joyIsPresent(void); +void EVTAPI EVT_joySetUpperLeft(void); +void EVTAPI EVT_joySetLowerRight(void); +void EVTAPI EVT_joySetCenter(void); + +/* Install user supplied event filter callback */ + +void EVTAPI EVT_setUserEventFilter(_EVT_userEventFilter filter); + +/* Install user supplied event heartbeat callback function */ + +void EVTAPI EVT_setHeartBeatCallback(_EVT_heartBeatCallback callback,void *params); +void EVTAPI EVT_getHeartBeatCallback(_EVT_heartBeatCallback *callback,void **params); + +/* Internal functions to initialise and kill the event manager. MGL + * applications should never call these functions directly as the MGL + * libraries do it for you. + */ + +/* {secret} */ +void EVTAPI EVT_init(_EVT_mouseMoveHandler mouseMove); +/* {secret} */ +void EVTAPI EVT_setMouseRange(int xRes,int yRes); +/* {secret} */ +void EVTAPI EVT_suspend(void); +/* {secret} */ +void EVTAPI EVT_resume(void); +/* {secret} */ +void EVTAPI EVT_exit(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif /* __cplusplus */ + +#endif /* __EVENT_H */ diff --git a/board/MAI/bios_emulator/scitech/include/mtrr.h b/board/MAI/bios_emulator/scitech/include/mtrr.h new file mode 100644 index 000000000..b29812c92 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/mtrr.h @@ -0,0 +1,72 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Include file defining the external ring 0 helper functions +* needed by the MTRR module. These functions may be included +* directly for native ring 0 device drivers, or they may +* be calls down to a ring 0 helper device driver where +* appropriate (or the entire MTRR module may be located in +* the device driver if the device driver is 32-bit). +* +****************************************************************************/ + +#ifndef __MTRR_H +#define __MTRR_H + +#include "scitech.h" + +/*--------------------------- Function Prototypes -------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Internal functions (requires ring 0 access or helper functions!) */ + +void MTRR_init(void); +int MTRR_enableWriteCombine(ulong base,ulong size,uint type); + +/* External assembler helper functions */ + +ibool _ASMAPI _MTRR_isRing0(void); +ulong _ASMAPI _MTRR_disableInt(void); +void _ASMAPI _MTRR_restoreInt(ulong flags); +ulong _ASMAPI _MTRR_saveCR4(void); +void _ASMAPI _MTRR_restoreCR4(ulong cr4Val); +uchar _ASMAPI _MTRR_getCx86(uchar reg); +void _ASMAPI _MTRR_setCx86(uchar reg,uchar data); +#ifdef __16BIT__ +void _ASMAPI _MTRR_readMSR(ulong reg, ulong far *eax, ulong far *edx); +#else +void _ASMAPI _MTRR_readMSR(ulong reg, ulong *eax, ulong *edx); +#endif +void _ASMAPI _MTRR_writeMSR(ulong reg, ulong eax, ulong edx); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __MTRR_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pcilib.h b/board/MAI/bios_emulator/scitech/include/pcilib.h new file mode 100644 index 000000000..238f8ef83 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pcilib.h @@ -0,0 +1,413 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Header file for interface routines to the PCI bus. +* +****************************************************************************/ + +#ifndef __PCILIB_H +#define __PCILIB_H + +#include "scitech.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/* Defines for PCIDeviceInfo.HeaderType */ + +typedef enum { + PCI_deviceType = 0x00, + PCI_bridgeType = 0x01, + PCI_cardBusBridgeType = 0x02, + PCI_multiFunctionType = 0x80 + } PCIHeaderTypeFlags; + +/* Defines for PCIDeviceInfo.Command */ + +typedef enum { + PCI_enableIOSpace = 0x0001, + PCI_enableMemorySpace = 0x0002, + PCI_enableBusMaster = 0x0004, + PCI_enableSpecialCylces = 0x0008, + PCI_enableWriteAndInvalidate = 0x0010, + PCI_enableVGACompatiblePalette = 0x0020, + PCI_enableParity = 0x0040, + PCI_enableWaitCycle = 0x0080, + PCI_enableSerr = 0x0100, + PCI_enableFastBackToBack = 0x0200 + } PCICommandFlags; + +/* Defines for PCIDeviceInfo.Status */ + +typedef enum { + PCI_statusCapabilitiesList = 0x0010, + PCI_status66MhzCapable = 0x0020, + PCI_statusUDFSupported = 0x0040, + PCI_statusFastBackToBack = 0x0080, + PCI_statusDataParityDetected = 0x0100, + PCI_statusDevSel = 0x0600, + PCI_statusSignaledTargetAbort = 0x0800, + PCI_statusRecievedTargetAbort = 0x1000, + PCI_statusRecievedMasterAbort = 0x2000, + PCI_statusSignaledSystemError = 0x4000, + PCI_statusDetectedParityError = 0x8000 + } PCIStatusFlags; + +/* PCI capability IDs */ + +typedef enum { + PCI_capsPowerManagement = 0x01, + PCI_capsAGP = 0x02, + PCI_capsMSI = 0x05 + } PCICapsType; + +/* PCI AGP rate definitions */ + +typedef enum { + PCI_AGPRate1X = 0x1, + PCI_AGPRate2X = 0x2, + PCI_AGPRate4X = 0x4 + } PCIAGPRateType; + +/* NOTE: We define all bitfield's as uint's, specifically so that the IBM + * Visual Age C++ compiler does not complain. We need them to be + * 32-bits wide, and this is the width of an unsigned integer, but + * we can't use a ulong to make this explicit or we get errors. + */ + +/* Structure defining a PCI slot identifier */ + +typedef union { + struct { + uint Zero:2; + uint Register:6; + uint Function:3; + uint Device:5; + uint Bus:8; + uint Reserved:7; + uint Enable:1; + } p; + ulong i; + } PCIslot; + +/* Structure defining the regular (type 0) PCI configuration register + * layout. We use this in a union below so we can describe all types of + * PCI configuration spaces with a single structure. + */ + +typedef struct { + ulong BaseAddress10; + ulong BaseAddress14; + ulong BaseAddress18; + ulong BaseAddress1C; + ulong BaseAddress20; + ulong BaseAddress24; + ulong CardbusCISPointer; + ushort SubSystemVendorID; + ushort SubSystemID; + ulong ROMBaseAddress; + uchar CapabilitiesPointer; + uchar reserved1; + uchar reserved2; + uchar reserved3; + ulong reserved4; + uchar InterruptLine; + uchar InterruptPin; + uchar MinimumGrant; + uchar MaximumLatency; + + /* These are not in the actual config space, but we enumerate them */ + ulong BaseAddress10Len; + ulong BaseAddress14Len; + ulong BaseAddress18Len; + ulong BaseAddress1CLen; + ulong BaseAddress20Len; + ulong BaseAddress24Len; + ulong ROMBaseAddressLen; + } PCIType0Info; + +/* Structure defining PCI to PCI bridge (type 1) PCI configuration register + * layout. We use this in a union below so we can describe all types of + * PCI configuration spaces with a single structure. + */ + +typedef struct { + ulong BaseAddress10; + ulong BaseAddress14; + uchar PrimaryBusNumber; + uchar SecondayBusNumber; + uchar SubordinateBusNumber; + uchar SecondaryLatencyTimer; + uchar IOBase; + uchar IOLimit; + ushort SecondaryStatus; + ushort MemoryBase; + ushort MemoryLimit; + ushort PrefetchableMemoryBase; + ushort PrefetchableMemoryLimit; + ulong PrefetchableBaseHi; + ulong PrefetchableLimitHi; + ushort IOBaseHi; + ushort IOLimitHi; + uchar CapabilitiesPointer; + uchar reserved1; + uchar reserved2; + uchar reserved3; + ulong ROMBaseAddress; + uchar InterruptLine; + uchar InterruptPin; + ushort BridgeControl; + } PCIType1Info; + +/* PCI to CardBus bridge (type 2) configuration information */ +typedef struct { + ulong SocketRegistersBaseAddress; + uchar CapabilitiesPointer; + uchar reserved1; + ushort SecondaryStatus; + uchar PrimaryBus; + uchar SecondaryBus; + uchar SubordinateBus; + uchar SecondaryLatency; + struct { + ulong Base; + ulong Limit; + } Range[4]; + uchar InterruptLine; + uchar InterruptPin; + ushort BridgeControl; + } PCIType2Info; + +/* Structure defining the PCI configuration space information for a + * single PCI device on the PCI bus. We enumerate all this information + * for all PCI devices on the bus. + */ + +typedef struct { + ulong dwSize; + PCIslot slot; + ulong mech1; + ushort VendorID; + ushort DeviceID; + ushort Command; + ushort Status; + uchar RevID; + uchar Interface; + uchar SubClass; + uchar BaseClass; + uchar CacheLineSize; + uchar LatencyTimer; + uchar HeaderType; + uchar BIST; + union { + PCIType0Info type0; + PCIType1Info type1; + PCIType2Info type2; + } u; + } PCIDeviceInfo; + +/* PCI Capability header structure. All PCI capabilities have the + * following header. + * + * capsID is used to identify the type of the structure as define above. + * + * next is the offset in PCI configuration space (0x40-0xFC) of the + * next capability structure in the list, or 0x00 if there are no more + * entries. + */ + +typedef struct { + uchar capsID; + uchar next; + } PCICapsHeader; + +/* Structure defining the PCI AGP status register contents */ + +typedef struct { + uint rate:3; + uint rsvd1:1; + uint fastWrite:1; + uint fourGB:1; + uint rsvd2:3; + uint sideBandAddressing:1; + uint rsvd3:14; + uint requestQueueDepthMaximum:8; + } PCIAGPStatus; + +/* Structure defining the PCI AGP command register contents */ + +typedef struct { + uint rate:3; + uint rsvd1:1; + uint fastWriteEnable:1; + uint fourGBEnable:1; + uint rsvd2:2; + uint AGPEnable:1; + uint SBAEnable:1; + uint rsvd3:14; + uint requestQueueDepth:8; + } PCIAGPCommand; + +/* AGP Capability structure */ + +typedef struct { + PCICapsHeader h; + ushort majMin; + PCIAGPStatus AGPStatus; + PCIAGPCommand AGPCommand; + } PCIAGPCapability; + +/* Structure for obtaining the PCI IRQ routing information */ + +typedef struct { + uchar bus; + uchar device; + uchar linkA; + ushort mapA; + uchar linkB; + ushort mapB; + uchar linkC; + ushort mapC; + uchar linkD; + ushort mapD; + uchar slot; + uchar reserved; + } PCIRouteInfo; + +typedef struct { + ushort BufferSize; + PCIRouteInfo *DataBuffer; + } PCIRoutingOptionsBuffer; + +#define NUM_PCI_REG (sizeof(PCIDeviceInfo) / 4) - 10 +#define PCI_BRIDGE_CLASS 0x06 +#define PCI_HOST_BRIDGE_SUBCLASS 0x00 +#define PCI_EARLY_VGA_CLASS 0x00 +#define PCI_EARLY_VGA_SUBCLASS 0x01 +#define PCI_DISPLAY_CLASS 0x03 +#define PCI_DISPLAY_VGA_SUBCLASS 0x00 +#define PCI_DISPLAY_XGA_SUBCLASS 0x01 +#define PCI_DISPLAY_OTHER_SUBCLASS 0x80 +#define PCI_MM_CLASS 0x04 +#define PCI_AUDIO_SUBCLASS 0x01 + +/* Macros to detect specific classes of devices */ + +#define PCI_IS_3DLABS_NONVGA_CLASS(pci) \ + (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_OTHER_SUBCLASS) \ + && ((pci)->VendorID == 0x3D3D || (pci)->VendorID == 0x104C)) + +#define PCI_IS_DISPLAY_CLASS(pci) \ + (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_VGA_SUBCLASS) \ + || ((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_XGA_SUBCLASS) \ + || ((pci)->BaseClass == PCI_EARLY_VGA_CLASS && (pci)->SubClass == PCI_EARLY_VGA_SUBCLASS) \ + || PCI_IS_3DLABS_NONVGA_CLASS(pci)) + +/* Function codes to pass to PCI_accessReg */ + +#define PCI_READ_BYTE 0 +#define PCI_READ_WORD 1 +#define PCI_READ_DWORD 2 +#define PCI_WRITE_BYTE 3 +#define PCI_WRITE_WORD 4 +#define PCI_WRITE_DWORD 5 + +/* Macros to read/write PCI registers. These assume a global PCI array + * of device information. + */ + +#define PCI_readPCIRegB(index,device) \ + PCI_accessReg(index,0,0,&PCI[DeviceIndex[device]]) + +#define PCI_readPCIRegW(index,device) \ + PCI_accessReg(index,0,1,&PCI[DeviceIndex[device]]) + +#define PCI_readPCIRegL(index,device) \ + PCI_accessReg(index,0,2,&PCI[DeviceIndex[device]]) + +#define PCI_writePCIRegB(index,value,device) \ + PCI_accessReg(index,value,3,&PCI[DeviceIndex[device]]) + +#define PCI_writePCIRegW(index,value,device) \ + PCI_accessReg(index,value,4,&PCI[DeviceIndex[device]]) + +#define PCI_writePCIRegL(index,value,device) \ + PCI_accessReg(index,value,5,&PCI[DeviceIndex[device]]) + +#pragma pack() + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Function to determine the number of PCI devices in the system */ + +int _ASMAPI PCI_getNumDevices(void); + +/* Function to enumerate all device on the PCI bus */ + +int _ASMAPI PCI_enumerate(PCIDeviceInfo info[]); + +/* Function to access PCI configuration registers */ + +ulong _ASMAPI PCI_accessReg(int index,ulong value,int func,PCIDeviceInfo *info); + +/* Function to get PCI IRQ routing options for a card */ + +int _ASMAPI PCI_getIRQRoutingOptions(int numDevices,PCIRouteInfo *buffer); + +/* Function to re-route the PCI IRQ setting for a device */ + +ibool _ASMAPI PCI_setHardwareIRQ(PCIDeviceInfo *info,uint intPin,uint IRQ); + +/* Function to generate a special cyle on the specified PCI bus */ + +void _ASMAPI PCI_generateSpecialCyle(uint bus,ulong specialCycleData); + +/* Function to determine the size of a PCI base address register */ + +ulong _ASMAPI PCI_findBARSize(int bar,PCIDeviceInfo *pci); + +/* Function to read a block of PCI configuration space registers */ + +void _ASMAPI PCI_readRegBlock(PCIDeviceInfo *info,int index,void *dst,int count); + +/* Function to write a block of PCI configuration space registers */ + +void _ASMAPI PCI_writeRegBlock(PCIDeviceInfo *info,int index,void *src,int count); + +/* Function to return the 32-bit PCI BIOS entry point */ + +ulong _ASMAPI PCIBIOS_getEntry(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __PCILIB_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pm_help.h b/board/MAI/bios_emulator/scitech/include/pm_help.h new file mode 100644 index 000000000..536a2baac --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pm_help.h @@ -0,0 +1,166 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32, OS/2 +* +* Description: Include file for the SciTech Portability Manager 32-bit +* helper VxD for Windows 9x for and the 16-bit ring 0 +* helper device driver for OS/2. +* +* This file documents all the public services used by the +* SciTech Portability Manager library and SciTech Nucleus +* loader library. +* +****************************************************************************/ + +#ifndef __PMHELP_H +#define __PMHELP_H + +/* Include version information */ + +#include "sdd/sddver.h" +#define PMHELP_Major SDD_RELEASE_MAJOR +#define PMHELP_Minor SDD_RELEASE_MINOR +#define PMHELP_VERSION ((PMHELP_Major << 8) | PMHELP_Minor) + +#ifdef __OS2__ + +/**************************************************************************** +* Public OS/2 Support functions +****************************************************************************/ + +#include "scitech.h" +#include "nucleus/graphics.h" + +/* Name of device driver */ + +#define PMHELP_NAME (PSZ)"sddhelp$" + +/* Main IOCTL function to talk to device driver */ + +#define PMHELP_IOCTL 0x0080 + +/* Macro definition for defining IOCTL function control codes for the SDDHELP + * device driver for OS/2. Similar to that used for the DOS/Win32 version. + */ + +#define PMHELP_CTL_CODE(name,value) \ + PMHELP_##name = value + +typedef enum { + /* Version function used by all drivers */ + PMHELP_CTL_CODE(GETVER ,0x0001), + PMHELP_CTL_CODE(MAPPHYS ,0x0002), + PMHELP_CTL_CODE(ALLOCLOCKED ,0x0003), + PMHELP_CTL_CODE(FREELOCKED ,0x0004), + PMHELP_CTL_CODE(GETGDT32 ,0x0005), + PMHELP_CTL_CODE(MALLOCSHARED ,0x0007), + PMHELP_CTL_CODE(FREESHARED ,0x0008), + PMHELP_CTL_CODE(MAPTOPROCESS ,0x0009), + PMHELP_CTL_CODE(FREEPHYS ,0x000A), + PMHELP_CTL_CODE(FLUSHTLB ,0x000B), + PMHELP_CTL_CODE(SAVECR4 ,0x000C), + PMHELP_CTL_CODE(RESTORECR4 ,0x000D), + PMHELP_CTL_CODE(READMSR ,0x000E), + PMHELP_CTL_CODE(WRITEMSR ,0x000F), + PMHELP_CTL_CODE(GETPHYSICALADDR ,0x0010), + PMHELP_CTL_CODE(GETPHYSICALADDRRANGE ,0x0011), + PMHELP_CTL_CODE(LOCKPAGES ,0x0012), + PMHELP_CTL_CODE(UNLOCKPAGES ,0x0013), + PMHELP_CTL_CODE(GETSHAREDEXP ,0x0042), + PMHELP_CTL_CODE(SETSHAREDEXP ,0x0043), + PMHELP_CTL_CODE(GETSTACKSWITCHRTN ,0x0044), + PMHELP_CTL_CODE(GETBUILDNO ,0x0050), + } PMHELP_ctlCodes; + +#else + +/**************************************************************************** +* Public DOS/Windows Support functions +****************************************************************************/ + +#ifdef DEVICE_MAIN +#include +#define PMHELP_Init_Order (VDD_INIT_ORDER-1) +#define RETURN_LONGS(n) *p->dioc_bytesret = (n) * sizeof(ulong) +#endif /* DEVICE_MAIN */ +#include "scitech.h" +#include "nucleus/graphics.h" + +/* We connect to the SDDHELP.VXD module if it is staticly loaded (as part + * of SciTech Display Doctor), otherwise we dynamically load the PMHELP.VXD + * public helper VxD. + */ + +#define PMHELP_DeviceID 0x0000 +#define SDDHELP_DeviceID 0x3DF8 +#define VXDLDR_DeviceID 0x0027 +#define SDDHELP_MODULE "SDDHELP" +#define SDDHELP_NAME "SDDHELP.VXD" +#define PMHELP_MODULE "PMHELP" +#define PMHELP_NAME "PMHELP.VXD" +#define PMHELP_DDBNAME "pmhelp " +#define SDDHELP_MODULE_PATH "\\\\.\\" SDDHELP_MODULE +#define PMHELP_MODULE_PATH "\\\\.\\" PMHELP_MODULE +#define PMHELP_VXD_PATH "\\\\.\\" PMHELP_NAME + +/* Macro definition for defining IOCTL function control codes for the PMHELP + * device drivers for Windows 9x and NT. This macro is basically derived from + * the CTL_CODE macro in the Windows 2000 DDK, but we hard code it here to + * avoid having to #include any of the Windows 2000 DDK header files. We also + * define both a 16-bit and 32-bit version of the control code within the same + * macro to simplify future additions. + * + * Essentially the Win32 macro would normally expand to the following: + * + * CTL_CODE(FILE_DEVICE_VIDEO,0x800+value,METHOD_BUFFERED,FILE_ANY_ACCESS) + */ + +#define PMHELP_CTL_CODE(name,value) \ + PMHELP_##name = value, \ + PMHELP_##name##32 = ((0x23 << 16) | (0 << 14) | ((0x800+value) << 2) | (0)) + +typedef enum { + /* Include all the control codes. We keep them in a separate header + * file so we can include them in multiple places to make this + * more versatile. + */ + #include "pm_wctl.h" + } PMHELP_ctlCodes; + +/* For real mode VxD calls, we put the function number into the high + * order word of EAX, and a value of 0x4FFF in AX. This allows our + * VxD handler which is set up to handle Int 10's to recognise a native + * PMHELP API call from a real mode DOS program. + */ + +#ifdef REALMODE +#define API_NUM(num) (((ulong)(num) << 16) | 0x4FFF) +#else +#define API_NUM(num) (num) +#endif + +#endif /* !__OS2__ */ + +#endif /* __PMHELP_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pm_wctl.h b/board/MAI/bios_emulator/scitech/include/pm_wctl.h new file mode 100644 index 000000000..20aa15e53 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pm_wctl.h @@ -0,0 +1,75 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32, OS/2 +* +* Description: Header file to define all the control codes for the DOS +* and Win32 device driver API's for calling from ring 3 +* into the ring 0 device drivers. +* +****************************************************************************/ + +/* Version function used by all drivers */ +PMHELP_CTL_CODE(GETVER ,0x0000), + +/* Functions used by obsolete 16-bit DOS TSR */ +PMHELP_CTL_CODE(RDREGB ,0x0003), +PMHELP_CTL_CODE(WRREGB ,0x0004), +PMHELP_CTL_CODE(RDREGW ,0x0005), +PMHELP_CTL_CODE(WRREGW ,0x0006), +PMHELP_CTL_CODE(RDREGL ,0x0008), +PMHELP_CTL_CODE(WRREGL ,0x0009), + +/* Functions used by obsolete WinDirect */ +PMHELP_CTL_CODE(MAPPHYS ,0x000F), +PMHELP_CTL_CODE(GETVESABUF ,0x0013), + +/* Functions used by PM library */ +PMHELP_CTL_CODE(DPMIINT86 ,0x0014), +PMHELP_CTL_CODE(INT86 ,0x0015), +PMHELP_CTL_CODE(INT86X ,0x0016), +PMHELP_CTL_CODE(CALLREALMODE ,0x0017), +PMHELP_CTL_CODE(ALLOCLOCKED ,0x0018), +PMHELP_CTL_CODE(FREELOCKED ,0x0019), +PMHELP_CTL_CODE(ENABLELFBCOMB ,0x001A), +PMHELP_CTL_CODE(GETPHYSICALADDR ,0x001B), +PMHELP_CTL_CODE(MALLOCSHARED ,0x001D), +PMHELP_CTL_CODE(FREESHARED ,0x001F), +PMHELP_CTL_CODE(LOCKDATAPAGES ,0x0020), +PMHELP_CTL_CODE(UNLOCKDATAPAGES ,0x0021), +PMHELP_CTL_CODE(LOCKCODEPAGES ,0x0022), +PMHELP_CTL_CODE(UNLOCKCODEPAGES ,0x0023), +PMHELP_CTL_CODE(GETCALLGATE ,0x0024), +PMHELP_CTL_CODE(SETCNTPATH ,0x0025), +PMHELP_CTL_CODE(GETPDB ,0x0026), +PMHELP_CTL_CODE(FLUSHTLB ,0x0027), +PMHELP_CTL_CODE(GETPHYSICALADDRRANGE ,0x0028), +PMHELP_CTL_CODE(ALLOCPAGE ,0x0029), +PMHELP_CTL_CODE(FREEPAGE ,0x002A), +PMHELP_CTL_CODE(ENABLERING3IOPL ,0x002B), +PMHELP_CTL_CODE(DISABLERING3IOPL ,0x002C), +PMHELP_CTL_CODE(GASETLOCALPATH ,0x002D), +PMHELP_CTL_CODE(GAGETEXPORTS ,0x002E), +PMHELP_CTL_CODE(GATHUNK ,0x002F), +PMHELP_CTL_CODE(SETNUCLEUSPATH ,0x0030), diff --git a/board/MAI/bios_emulator/scitech/include/pmapi.h b/board/MAI/bios_emulator/scitech/include/pmapi.h new file mode 100644 index 000000000..7ddace708 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pmapi.h @@ -0,0 +1,1148 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Header file for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#ifndef __PMAPI_H +#define __PMAPI_H + +#include "scitech.h" +#include "pcilib.h" +#include "ztimerc.h" +#if !defined(__WIN32_VXD__) && !defined(__OS2_VDD__) && !defined(__NT_DRIVER__) +#include +#include +#endif + +/*--------------------------- Macros and Typedefs -------------------------*/ + +/* You will need to define one of the following before you compile this + * library for it to work correctly with the DOS extender that you are + * using when compiling for extended DOS: + * + * TNT - Phar Lap TNT DOS Extender + * DOS4GW - Rational DOS/4GW, DOS/4GW Pro, Causeway and PMODE/W + * DJGPP - DJGPP port of GNU C++ + * + * If none is specified, we will automatically determine which operating + * system is being targetted and the following will be defined (provided by + * scitech.h header file): + * + * __MSDOS16__ - Default for 16 bit MSDOS mode + * __MSDOS32__ - Default for 32 bit MSDOS + * __WINDOWS16__ - Default for 16 bit Windows + * __WINDOWS32__ - Default for 32 bit Windows + * + * One of the following will be defined automatically for you to select + * which memory model is in effect: + * + * REALMODE - 16 bit real mode (large memory model) + * PM286 - 16 protected mode (large memory model) + * PM386 - 32 protected mode (flat memory model) + */ + +#if defined(__UNIX__) && !defined(_MAX_PATH) +#define _MAX_PATH 256 +#endif + +#if defined(TNT) || defined(DOSX) || defined(X32VM) || defined(DPMI32) \ + || defined(DOS4GW) || defined(DJGPP) || defined(__WINDOWS32__) \ + || defined(__MSDOS32__) || defined(__UNIX__) || defined(__WIN32_VXD__) \ + || defined(__32BIT__) || defined(__SMX32__) || defined(__RTTARGET__) +#define PM386 +#elif defined(DPMI16) || defined(__WINDOWS16__) +#define PM286 +#else +#define REALMODE +#endif + +#pragma pack(1) + +/* Provide the typedefs for the PM_int386 functions, which issue native + * interrupts in real or protected mode and can pass extended registers + * around. + */ + +struct _PMDWORDREGS { + ulong eax,ebx,ecx,edx,esi,edi,cflag; + }; + +struct _PMWORDREGS { + ushort ax,ax_hi; + ushort bx,bx_hi; + ushort cx,cx_hi; + ushort dx,dx_hi; + ushort si,si_hi; + ushort di,di_hi; + ushort cflag,cflag_hi; + }; + +struct _PMBYTEREGS { + uchar al, ah; ushort ax_hi; + uchar bl, bh; ushort bx_hi; + uchar cl, ch; ushort cx_hi; + uchar dl, dh; ushort dx_hi; + }; + +typedef union { + struct _PMDWORDREGS e; + struct _PMWORDREGS x; + struct _PMBYTEREGS h; + } PMREGS; + +typedef struct { + ushort es; + ushort cs; + ushort ss; + ushort ds; + ushort fs; + ushort gs; + } PMSREGS; + +/* Provide definitions for the real mode register structures passed to + * the PM_int86() and PM_int86x() routines. Note that we provide our own + * functions to do this for 16-bit code that calls the PM_int386 functions. + */ + +typedef PMREGS RMREGS; +typedef PMSREGS RMSREGS; + +typedef struct { + long edi; + long esi; + long ebp; + long reserved; + long ebx; + long edx; + long ecx; + long eax; + short flags; + short es,ds,fs,gs,ip,cs,sp,ss; + } DPMI_regs; + +#ifdef __MSDOS__ +/* Register structure passed to PM_VxDCall function */ +typedef struct { + ulong eax; + ulong ebx; + ulong ecx; + ulong edx; + ulong esi; + ulong edi; + ushort ds,es; + } VXD_regs; +#endif + +#define PM_MAX_DRIVE 3 +#define PM_MAX_PATH 256 +#define PM_FILE_INVALID (void*)0xFFFFFFFF + +/* Structure for generic directory traversal and management. Also the same + * values are passed to PM_setFileAttr to change the file attributes. + */ + +typedef struct { + ulong dwSize; + ulong attrib; + ulong sizeLo; + ulong sizeHi; + char name[PM_MAX_PATH]; + } PM_findData; + +/* Macro to compute the byte offset of a field in a structure of type type */ + +#define PM_FIELD_OFFSET(type,field) ((long)&(((type*)0)->field)) + +/* Marcto to compute the address of the base of the structure given its type, + * and an address of a field within the structure. + */ + +#define PM_CONTAINING_RECORD(address, type, field) \ + ((type*)( \ + (char*)(address) - \ + (char*)(&((type*)0)->field))) + +/* Flags stored in the PM_findData structure, and also values passed to + * PM_setFileAttr to change the file attributes. + */ + +#define PM_FILE_NORMAL 0x00000000 +#define PM_FILE_READONLY 0x00000001 +#define PM_FILE_DIRECTORY 0x00000002 +#define PM_FILE_ARCHIVE 0x00000004 +#define PM_FILE_HIDDEN 0x00000008 +#define PM_FILE_SYSTEM 0x00000010 + +/* Flags returned by the PM_splitpath function */ + +#define PM_HAS_WILDCARDS 0x01 +#define PM_HAS_EXTENSION 0x02 +#define PM_HAS_FILENAME 0x04 +#define PM_HAS_DIRECTORY 0x08 +#define PM_HAS_DRIVE 0x10 + +/* Structure passed to the PM_setFileTime functions */ +typedef struct { + short sec; /* Seconds */ + short min; /* Minutes */ + short hour; /* Hour (0--23) */ + short day; /* Day of month (1--31) */ + short mon; /* Month (0--11) */ + short year; /* Year (calendar year minus 1900) */ + } PM_time; + +/* Define a macro for creating physical base addresses from segment:offset */ + +#define MK_PHYS(s,o) (((ulong)(s) << 4) + (ulong)(o)) + +/* Define the different types of modes supported. This is a global variable + * that can be used to determine the type at runtime which will contain + * one of these values. + */ + +typedef enum { + PM_realMode, + PM_286, + PM_386 + } PM_mode_enum; + +/* Define types passed to PM_enableWriteCombine */ + +#define PM_MTRR_UNCACHABLE 0 +#define PM_MTRR_WRCOMB 1 +#define PM_MTRR_WRTHROUGH 4 +#define PM_MTRR_WRPROT 5 +#define PM_MTRR_WRBACK 6 +#define PM_MTRR_MAX 6 + +/* Error codes returned by PM_enableWriteCombine */ + +#define PM_MTRR_ERR_OK 0 +#define PM_MTRR_NOT_SUPPORTED -1 +#define PM_MTRR_ERR_PARAMS -2 +#define PM_MTRR_ERR_NOT_4KB_ALIGNED -3 +#define PM_MTRR_ERR_BELOW_1MB -4 +#define PM_MTRR_ERR_NOT_ALIGNED -5 +#define PM_MTRR_ERR_OVERLAP -6 +#define PM_MTRR_ERR_TYPE_MISMATCH -7 +#define PM_MTRR_ERR_NONE_FREE -8 +#define PM_MTRR_ERR_NOWRCOMB -9 +#define PM_MTRR_ERR_NO_OS_SUPPORT -10 + +/* Values passed to the PM_DMACProgram function */ + +#define PM_DMA_READ_ONESHOT 0x44 /* One-shot DMA read */ +#define PM_DMA_WRITE_ONESHOT 0x48 /* One-shot DMA write */ +#define PM_DMA_READ_AUTOINIT 0x54 /* Auto-init DMA read */ +#define PM_DMA_WRITE_AUTOINIT 0x58 /* Auto-init DMA write */ + +/* Flags passed to suspend application callback */ + +#define PM_DEACTIVATE 1 +#define PM_REACTIVATE 2 + +/* Return codes that the application can return from the suspend application + * callback registered with the PM library. See the MGL documentation for + * more details. + */ +#define PM_SUSPEND_APP 0 +#define PM_NO_SUSPEND_APP 1 + +/**************************************************************************** +REMARKS: +This enumeration defines the type values passed to the PM_agpReservePhysical +function, to define how the physical memory mapping should be handled. + +The PM_agpUncached type indicates that the memory should be allocated as +uncached memory. + +The PM_agpWriteCombine type indicates that write combining should be enabled +for physical memory mapping. This is used for framebuffer write combing and +speeds up direct framebuffer writes to the memory. + +The PM_agpIntelDCACHE type indicates that memory should come from the Intel +i81x Display Cache (or DCACHE) memory pool. This flag is specific to the +Intel i810 and i815 controllers, and should not be passed for any other +controller type. + +HEADER: +pmapi.h + +MEMBERS: +PM_agpUncached - Indicates that the memory should be uncached +PM_agpWriteCombine - Indicates that the memory should be write combined +PM_agpIntelDCACHE - Indicates that the memory should come from DCACHE pool +****************************************************************************/ +typedef enum { + PM_agpUncached, + PM_agpWriteCombine, + PM_agpIntelDCACHE + } PM_agpMemoryType; + +/* Defines the size of an system memory page */ + +#define PM_PAGE_SIZE 4096 + +/* Type definition for a physical memory address */ + +typedef unsigned long PM_physAddr; + +/* Define a bad physical address returned by map physical functions */ + +#define PM_BAD_PHYS_ADDRESS 0xFFFFFFFF + +/* Type definition for the 12-byte lock handle for locking linear memory */ + +typedef struct { + ulong h[3]; + } PM_lockHandle; + +/* 'C' calling conventions always */ + +#define PMAPI _ASMAPI +#define PMAPIP _ASMAPIP + +/* Internal typedef to override DPMI_int86 handler */ + +typedef ibool (PMAPIP DPMI_handler_t)(DPMI_regs *regs); +void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler); + +/* Type definitions for a window handle for console modes */ + +#if defined(__DRIVER__) || defined(__WIN32_VXD__) || defined(__NT_DRIVER__) +typedef void *PM_HWND; /* Pointer for portable drivers */ +typedef void *PM_MODULE; /* Module handle for portable drivers */ +#elif defined(__WINDOWS__) +#ifdef DECLARE_HANDLE +typedef HWND PM_HWND; /* Real window handle */ +typedef HINSTANCE PM_MODULE; /* Win32 DLL handle */ +#else +typedef void *PM_HWND; /* Place holder if windows.h not included */ +typedef void *PM_MODULE; /* Place holder if windows.h not included */ +#endif +#elif defined(__USE_X11__) +typedef struct { + Window *window; + Display *display; + } PM_HWND; /* X11 window handle */ +#elif defined(__OS2__) +typedef void *PM_HWND; +typedef void *PM_MODULE; +#elif defined(__LINUX__) +typedef int PM_HWND; /* Console id for fullscreen Linux */ +typedef void *PM_MODULE; +#elif defined(__QNX__) +typedef int PM_HWND; /* Console id for fullscreen QNX */ +typedef void *PM_MODULE; +#elif defined(__RTTARGET__) +typedef int PM_HWND; /* Placeholder for RTTarget-32 */ +typedef void *PM_MODULE; +#elif defined(__REALDOS__) +typedef int PM_HWND; /* Placeholder for fullscreen DOS */ +typedef void *PM_MODULE; /* Placeholder for fullscreen DOS */ +#elif defined(__SMX32__) +typedef int PM_HWND; /* Placeholder for fullscreen SMX */ +typedef void *PM_MODULE; +#elif defined(__SNAP__) +typedef void *PM_HWND; +typedef void *PM_MODULE; +#else +#error PM library not ported to this platform yet! +#endif + +/* Type definition for code pointers */ + +typedef void (*__codePtr)(); + +/* Type definition for a C based interrupt handler */ + +typedef void (PMAPIP PM_intHandler)(void); +typedef ibool (PMAPIP PM_irqHandler)(void); + +/* Hardware IRQ handle used to save and restore the hardware IRQ */ + +typedef void *PM_IRQHandle; + +/* Type definition for the fatal cleanup handler */ + +typedef void (PMAPIP PM_fatalCleanupHandler)(void); + +/* Type defifinition for save state callback function */ + +typedef int (PMAPIP PM_saveState_cb)(int flags); + +/* Type definintion for enum write combined callback function */ + +typedef void (PMAPIP PM_enumWriteCombine_t)(ulong base,ulong length,uint type); + +/* Structure defining all the PM API functions as exported to + * the binary portable DLL's. + */ + +typedef struct { + ulong dwSize; + int (PMAPIP PM_getModeType)(void); + void * (PMAPIP PM_getBIOSPointer)(void); + void * (PMAPIP PM_getA0000Pointer)(void); + void * (PMAPIP PM_mapPhysicalAddr)(ulong base,ulong limit,ibool isCached); + void * (PMAPIP PM_mallocShared)(long size); + void * reserved1; + void (PMAPIP PM_freeShared)(void *ptr); + void * (PMAPIP PM_mapToProcess)(void *linear,ulong limit); + void * (PMAPIP PM_mapRealPointer)(uint r_seg,uint r_off); + void * (PMAPIP PM_allocRealSeg)(uint size,uint *r_seg,uint *r_off); + void (PMAPIP PM_freeRealSeg)(void *mem); + void * (PMAPIP PM_allocLockedMem)(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg); + void (PMAPIP PM_freeLockedMem)(void *p,uint size,ibool contiguous); + void (PMAPIP PM_callRealMode)(uint seg,uint off, RMREGS *regs,RMSREGS *sregs); + int (PMAPIP PM_int86)(int intno, RMREGS *in, RMREGS *out); + int (PMAPIP PM_int86x)(int intno, RMREGS *in, RMREGS *out,RMSREGS *sregs); + void (PMAPIP DPMI_int86)(int intno, DPMI_regs *regs); + void (PMAPIP PM_availableMemory)(ulong *physical,ulong *total); + void * (PMAPIP PM_getVESABuf)(uint *len,uint *rseg,uint *roff); + long (PMAPIP PM_getOSType)(void); + void (PMAPIP PM_fatalError)(const char *msg); + void (PMAPIP PM_setBankA)(int bank); + void (PMAPIP PM_setBankAB)(int bank); + void (PMAPIP PM_setCRTStart)(int x,int y,int waitVRT); + char * (PMAPIP PM_getCurrentPath)(char *path,int maxLen); + const char * (PMAPIP PM_getVBEAFPath)(void); + const char * (PMAPIP PM_getNucleusPath)(void); + const char * (PMAPIP PM_getNucleusConfigPath)(void); + const char * (PMAPIP PM_getUniqueID)(void); + const char * (PMAPIP PM_getMachineName)(void); + ibool (PMAPIP VF_available)(void); + void * (PMAPIP VF_init)(ulong baseAddr,int bankSize,int codeLen,void *bankFunc); + void (PMAPIP VF_exit)(void); + PM_HWND (PMAPIP PM_openConsole)(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen); + int (PMAPIP PM_getConsoleStateSize)(void); + void (PMAPIP PM_saveConsoleState)(void *stateBuf,PM_HWND hwndConsole); + void (PMAPIP PM_restoreConsoleState)(const void *stateBuf,PM_HWND hwndConsole); + void (PMAPIP PM_closeConsole)(PM_HWND hwndConsole); + void (PMAPIP PM_setOSCursorLocation)(int x,int y); + void (PMAPIP PM_setOSScreenWidth)(int width,int height); + int (PMAPIP PM_enableWriteCombine)(ulong base,ulong length,uint type); + void (PMAPIP PM_backslash)(char *filename); + int (PMAPIP PM_lockDataPages)(void *p,uint len,PM_lockHandle *lockHandle); + int (PMAPIP PM_unlockDataPages)(void *p,uint len,PM_lockHandle *lockHandle); + int (PMAPIP PM_lockCodePages)(__codePtr p,uint len,PM_lockHandle *lockHandle); + int (PMAPIP PM_unlockCodePages)(__codePtr p,uint len,PM_lockHandle *lockHandle); + ibool (PMAPIP PM_setRealTimeClockHandler)(PM_intHandler ih,int frequency); + void (PMAPIP PM_setRealTimeClockFrequency)(int frequency); + void (PMAPIP PM_restoreRealTimeClockHandler)(void); + ibool (PMAPIP PM_doBIOSPOST)(ushort axVal,ulong BIOSPhysAddr,void *BIOSPtr,ulong BIOSLen); + char (PMAPIP PM_getBootDrive)(void); + void (PMAPIP PM_freePhysicalAddr)(void *ptr,ulong limit); + uchar (PMAPIP PM_inpb)(int port); + ushort (PMAPIP PM_inpw)(int port); + ulong (PMAPIP PM_inpd)(int port); + void (PMAPIP PM_outpb)(int port,uchar val); + void (PMAPIP PM_outpw)(int port,ushort val); + void (PMAPIP PM_outpd)(int port,ulong val); + void * reserved2; + void (PMAPIP PM_setSuspendAppCallback)(PM_saveState_cb saveState); + ibool (PMAPIP PM_haveBIOSAccess)(void); + int (PMAPIP PM_kbhit)(void); + int (PMAPIP PM_getch)(void); + ibool (PMAPIP PM_findBPD)(const char *dllname,char *bpdpath); + ulong (PMAPIP PM_getPhysicalAddr)(void *p); + void (PMAPIP PM_sleep)(ulong milliseconds); + int (PMAPIP PM_getCOMPort)(int port); + int (PMAPIP PM_getLPTPort)(int port); + PM_MODULE (PMAPIP PM_loadLibrary)(const char *szDLLName); + void * (PMAPIP PM_getProcAddress)(PM_MODULE hModule,const char *szProcName); + void (PMAPIP PM_freeLibrary)(PM_MODULE hModule); + int (PMAPIP PCI_enumerate)(PCIDeviceInfo info[]); + ulong (PMAPIP PCI_accessReg)(int index,ulong value,int func,PCIDeviceInfo *info); + ibool (PMAPIP PCI_setHardwareIRQ)(PCIDeviceInfo *info,uint intPin,uint IRQ); + void (PMAPIP PCI_generateSpecialCyle)(uint bus,ulong specialCycleData); + void * reserved3; + ulong (PMAPIP PCIBIOS_getEntry)(void); + uint (PMAPIP CPU_getProcessorType)(void); + ibool (PMAPIP CPU_haveMMX)(void); + ibool (PMAPIP CPU_have3DNow)(void); + ibool (PMAPIP CPU_haveSSE)(void); + ibool (PMAPIP CPU_haveRDTSC)(void); + ulong (PMAPIP CPU_getProcessorSpeed)(ibool accurate); + void (PMAPIP ZTimerInit)(void); + void (PMAPIP LZTimerOn)(void); + ulong (PMAPIP LZTimerLap)(void); + void (PMAPIP LZTimerOff)(void); + ulong (PMAPIP LZTimerCount)(void); + void (PMAPIP LZTimerOnExt)(LZTimerObject *tm); + ulong (PMAPIP LZTimerLapExt)(LZTimerObject *tm); + void (PMAPIP LZTimerOffExt)(LZTimerObject *tm); + ulong (PMAPIP LZTimerCountExt)(LZTimerObject *tm); + void (PMAPIP ULZTimerOn)(void); + ulong (PMAPIP ULZTimerLap)(void); + void (PMAPIP ULZTimerOff)(void); + ulong (PMAPIP ULZTimerCount)(void); + ulong (PMAPIP ULZReadTime)(void); + ulong (PMAPIP ULZElapsedTime)(ulong start,ulong finish); + void (PMAPIP ULZTimerResolution)(ulong *resolution); + void * (PMAPIP PM_findFirstFile)(const char *filename,PM_findData *findData); + ibool (PMAPIP PM_findNextFile)(void *handle,PM_findData *findData); + void (PMAPIP PM_findClose)(void *handle); + void (PMAPIP PM_makepath)(char *p,const char *drive,const char *dir,const char *name,const char *ext); + int (PMAPIP PM_splitpath)(const char *fn,char *drive,char *dir,char *name,char *ext); + ibool (PMAPIP PM_driveValid)(char drive); + void (PMAPIP PM_getdcwd)(int drive,char *dir,int len); + void (PMAPIP PM_setFileAttr)(const char *filename,uint attrib); + ibool (PMAPIP PM_mkdir)(const char *filename); + ibool (PMAPIP PM_rmdir)(const char *filename); + uint (PMAPIP PM_getFileAttr)(const char *filename); + ibool (PMAPIP PM_getFileTime)(const char *filename,ibool gmtTime,PM_time *time); + ibool (PMAPIP PM_setFileTime)(const char *filename,ibool gmtTime,PM_time *time); + char * (PMAPIP CPU_getProcessorName)(void); + int (PMAPIP PM_getVGAStateSize)(void); + void (PMAPIP PM_saveVGAState)(void *stateBuf); + void (PMAPIP PM_restoreVGAState)(const void *stateBuf); + void (PMAPIP PM_vgaBlankDisplay)(void); + void (PMAPIP PM_vgaUnblankDisplay)(void); + void (PMAPIP PM_blockUntilTimeout)(ulong milliseconds); + void (PMAPIP _PM_add64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); + void (PMAPIP _PM_sub64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); + void (PMAPIP _PM_mul64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); + void (PMAPIP _PM_div64)(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); + void (PMAPIP _PM_shr64)(u32 a_low,s32 a_high,s32 shift,__i64 *result); + void (PMAPIP _PM_sar64)(u32 a_low,s32 a_high,s32 shift,__i64 *result); + void (PMAPIP _PM_shl64)(u32 a_low,s32 a_high,s32 shift,__i64 *result); + void (PMAPIP _PM_neg64)(u32 a_low,s32 a_high,__i64 *result); + ulong (PMAPIP PCI_findBARSize)(int bar,PCIDeviceInfo *pci); + void (PMAPIP PCI_readRegBlock)(PCIDeviceInfo *info,int index,void *dst,int count); + void (PMAPIP PCI_writeRegBlock)(PCIDeviceInfo *info,int index,void *src,int count); + void (PMAPIP PM_flushTLB)(void); + void (PMAPIP PM_useLocalMalloc)(void * (*malloc)(size_t size),void * (*calloc)(size_t nelem,size_t size),void * (*realloc)(void *ptr,size_t size),void (*free)(void *p)); + void * (PMAPIP PM_malloc)(size_t size); + void * (PMAPIP PM_calloc)(size_t nelem,size_t size); + void * (PMAPIP PM_realloc)(void *ptr,size_t size); + void (PMAPIP PM_free)(void *p); + ibool (PMAPIP PM_getPhysicalAddrRange)(void *p,ulong length,ulong *physAddress); + void * (PMAPIP PM_allocPage)(ibool locked); + void (PMAPIP PM_freePage)(void *p); + ulong (PMAPIP PM_agpInit)(void); + void (PMAPIP PM_agpExit)(void); + ibool (PMAPIP PM_agpReservePhysical)(ulong numPages,int type,void **physContext,PM_physAddr *physAddr); + ibool (PMAPIP PM_agpReleasePhysical)(void *physContext); + ibool (PMAPIP PM_agpCommitPhysical)(void *physContext,ulong numPages,ulong startOffset,PM_physAddr *physAddr); + ibool (PMAPIP PM_agpFreePhysical)(void *physContext,ulong numPages,ulong startOffset); + int (PMAPIP PCI_getNumDevices)(void); + void (PMAPIP PM_setLocalBPDPath)(const char *path); + void * (PMAPIP PM_loadDirectDraw)(int device); + void (PMAPIP PM_unloadDirectDraw)(int device); + PM_HWND (PMAPIP PM_getDirectDrawWindow)(void); + void (PMAPIP PM_doSuspendApp)(void); + } PM_imports; + +#pragma pack() + +/*---------------------------- Global variables ---------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +#ifdef __WIN32_VXD__ +#define VESA_BUF_SIZE 1024 +extern uchar *_PM_rmBufAddr; +#endif + +/* {secret} Pointer to global exports structure. + * Should not be used by application programs. + */ +extern PM_imports _VARAPI _PM_imports; + +/* {secret} */ +extern void * (*__PM_malloc)(size_t size); +/* {secret} */ +extern void * (*__PM_calloc)(size_t nelem,size_t size); +/* {secret} */ +extern void * (*__PM_realloc)(void *ptr,size_t size); +/* {secret} */ +extern void (*__PM_free)(void *p); + +/*--------------------------- Function Prototypes -------------------------*/ + +/* Routine to initialise the host side PM library. Note used from DLL's */ + +void PMAPI PM_init(void); + +/* Routine to return either PM_realMode, PM_286 or PM_386 */ + +int PMAPI PM_getModeType(void); + +/* Routine to return a selector to the BIOS data area at segment 0x40 */ + +void * PMAPI PM_getBIOSPointer(void); + +/* Routine to return a linear pointer to the VGA frame buffer memory */ + +void * PMAPI PM_getA0000Pointer(void); + +/* Routines to map/free physical memory into the current DS segment. In + * some environments (32-bit DOS is one), after the mapping has been + * allocated, it cannot be freed. Hence you should only allocate the + * mapping once and cache the value for use by other parts of your + * application. If the mapping cannot be createed, this function will + * return a NULL pointer. + * + * This routine will also work for memory addresses below 1Mb, but the + * mapped address cannot cross the 1Mb boundary. + */ + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached); +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit); + +/* Routine to determine the physical address of a linear address. It is + * up to the caller to ensure the entire address range for a linear + * block of memory is page aligned if that is required. + */ + +ulong PMAPI PM_getPhysicalAddr(void *p); +ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress); + +/* Routines for memory allocation. By default these functions use the regular + * C runtime library malloc/free functions, but you can use the + * PM_useLocalMalloc function to override the default memory allocator with + * your own memory allocator. This will ensure that all memory allocation + * used by SciTech products will use your overridden memory allocator + * functions. + * + * Note that BPD files automatically map the C runtime library + * malloc/calloc/realloc/free calls from inside the BPD to the PM library + * versions by default. + */ + +void PMAPI PM_useLocalMalloc(void * (*malloc)(size_t size),void * (*calloc)(size_t nelem,size_t size),void * (*realloc)(void *ptr,size_t size),void (*free)(void *p)); +void * PMAPI PM_malloc(size_t size); +void * PMAPI PM_calloc(size_t nelem,size_t size); +void * PMAPI PM_realloc(void *ptr,size_t size); +void PMAPI PM_free(void *p); + +/* Routine to allocate a memory block in the global shared region that + * is common to all tasks and accessible from ring 0 code. + */ + +void * PMAPI PM_mallocShared(long size); + +/* Routine to free the allocated shared memory block */ + +void PMAPI PM_freeShared(void *ptr); + +/* Attach a previously allocated linear mapping to a new process */ + +void * PMAPI PM_mapToProcess(void *linear,ulong limit); + +/* Macros to extract byte, word and long values from a char pointer */ + +#define PM_getByte(p) *((volatile uchar*)(p)) +#define PM_getWord(p) *((volatile ushort*)(p)) +#define PM_getLong(p) *((volatile ulong*)(p)) +#define PM_setByte(p,v) PM_getByte(p) = (v) +#define PM_setWord(p,v) PM_getWord(p) = (v) +#define PM_setLong(p,v) PM_getLong(p) = (v) + +/* Routine for accessing a low 1Mb memory block. You dont need to free this + * pointer, but in 16 bit protected mode the selector allocated will be + * re-used the next time this routine is called. + */ + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off); + +/* Routine to allocate a block of conventional memory below the 1Mb + * limit so that it can be accessed from real mode. Ensure that you free + * the segment when you are done with it. + * + * This routine returns a selector and offset to the segment that has been + * allocated, and also returns the real mode segment and offset which can + * be passed to real mode routines. Will return 0 if memory could not be + * allocated. + * + * Please note that with some DOS extenders, memory allocated with the + * following function cannot be freed, hence it will be allocated for the + * life of your program. Thus if you need to call a bunch of different + * real-mode routines in your program, allocate a single large buffer at + * program startup that can be re-used throughout the program execution. + */ + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off); +void PMAPI PM_freeRealSeg(void *mem); + +/* Routine to allocate a block of locked memory, and return both the + * linear and physical addresses of the memory. You should always + * allocate locked memory blocks in page sized chunks (ie: 4K on IA32). + * If the memory is not contiguous, you will need to use the + * PM_getPhysicalAddr function to get the physical address of linear + * pages within the memory block (the returned physical address will be + * for the first address in the memory block only). + */ + +void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg); +void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous); + +/* Routine to allocate and free paged sized blocks of shared memory. + * Addressable from all processes, but not from a ring 0 context + * under OS/2. Note that under OS/2 PM_mapSharedPages must be called + * to map the memory blocks into the shared memory address space + * of each connecting process. + */ + +void * PMAPI PM_allocPage(ibool locked); +void PMAPI PM_freePage(void *p); +#ifdef __OS2__ +void PMAPI PM_mapSharedPages(void); +#endif + +/* Routine to return true if we have access to the BIOS on the host OS */ + +ibool PMAPI PM_haveBIOSAccess(void); + +/* Routine to call a real mode assembly language procedure. Register + * values are passed in and out in the 'regs' and 'sregs' structures. We + * do not provide any method of copying data from the protected mode stack + * to the real mode stack, so if you need to pass data to real mode, you will + * need to write a real mode assembly language hook to recieve the values + * in registers, and to pass the data through a real mode block allocated + * with the PM_allocRealSeg() routine. + */ + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *regs,RMSREGS *sregs); + +/* Routines to generate real mode interrupts using the same interface that + * is used by int86() and int86x() in realmode. This routine is need to + * call certain BIOS and DOS functions that are not supported by some + * DOS extenders. No translation is done on any of the register values, + * so they must be correctly set up and translated by the calling program. + * + * Normally the DOS extenders will allow you to use the normal int86() + * function directly and will pass on unhandled calls to real mode to be + * handled by the real mode handler. However calls to int86x() with real + * mode segment values to be loaded will cause a GPF if used with the + * standard int86x(), so you should use these routines if you know you + * want to call a real mode handler. + */ + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out); +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out,RMSREGS *sregs); + +/* Routine to generate a real mode interrupt. This is identical to the + * above function, but takes a DPMI_regs structure for the registers + * which has a lot more information. It is only available from 32-bit + * protected mode. + */ + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs); + +/* Function to return the amount of available physical and total memory. + * The results of this function are *only* valid before you have made any + * calls to malloc() and free(). If you need to keep track of exactly how + * much memory is currently allocated, you need to call this function to + * get the total amount of memory available and then keep track of + * the available memory every time you call malloc() and free(). + */ + +void PMAPI PM_availableMemory(ulong *physical,ulong *total); + +/* Return the address of a global VESA real mode transfer buffer for use + * by applications. + */ + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff); + +/* Handle fatal error conditions */ + +void PMAPI PM_fatalError(const char *msg); + +/* Function to set a cleanup error handler called when PM_fatalError + * is called. This allows us to the console back into a normal state + * if we get a failure from deep inside a BPD file. This function is + * not exported to BPD files, and is only used by code compiled for the + * OS. + */ + +void PMAPI PM_setFatalErrorCleanup(PM_fatalCleanupHandler cleanup); + +/* Return the OS type flag as defined in */ + +long PMAPI PM_getOSType(void); + +/* Functions to set a VBE bank via an Int 10h */ + +void PMAPI PM_setBankA(int bank); +void PMAPI PM_setBankAB(int bank); +void PMAPI PM_setCRTStart(int x,int y,int waitVRT); + +/* Return the current working directory */ + +char * PMAPI PM_getCurrentPath(char *path,int maxLen); + +/* Return paths to the VBE/AF and Nucleus directories */ + +const char * PMAPI PM_getVBEAFPath(void); +const char * PMAPI PM_getNucleusPath(void); +const char * PMAPI PM_getNucleusConfigPath(void); + +/* Find the path to a binary portable DLL */ + +void PMAPI PM_setLocalBPDPath(const char *path); +ibool PMAPI PM_findBPD(const char *dllname,char *bpdpath); + +/* Returns the drive letter of the boot drive for DOS, OS/2 and Windows */ + +char PMAPI PM_getBootDrive(void); + +/* Return a network unique machine identifier as a string */ + +const char * PMAPI PM_getUniqueID(void); + +/* Return the network machine name as a string */ + +const char * PMAPI PM_getMachineName(void); + +/* Functions to install and remove the virtual linear framebuffer + * emulation code. For unsupported DOS extenders and when running under + * a DPMI host like Windows or OS/2, this function will return a NULL. + */ + +ibool PMAPI VF_available(void); +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc); +void PMAPI VF_exit(void); + +/* Functions to wait for a keypress and read a key for command line + * environments such as DOS, Win32 console and Unix. + */ + +int PMAPI PM_kbhit(void); +int PMAPI PM_getch(void); + +/* Functions to create either a fullscreen or windowed console on the + * desktop, and to allow the resolution of fullscreen consoles to be + * changed on the fly without closing the console. For non-windowed + * environments (such as a Linux or OS/2 fullscreen console), these + * functions enable console graphics mode and restore console text mode. + * + * The suspend application callback is used to allow the application to + * save the state of the fullscreen console mode to allow temporary + * switching to another console or back to the regular GUI desktop. It + * is also called to restore the fullscreen graphics state after the + * fullscreen console regains the focus. + * + * The device parameter allows for the console to be opened on a different + * display controllers (0 is always the primary controller). + */ + +PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen); +int PMAPI PM_getConsoleStateSize(void); +void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole); +void PMAPI PM_setSuspendAppCallback(PM_saveState_cb saveState); +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole); +void PMAPI PM_closeConsole(PM_HWND hwndConsole); + +/* Functions to modify OS console information */ + +void PMAPI PM_setOSCursorLocation(int x,int y); +void PMAPI PM_setOSScreenWidth(int width,int height); + +/* Function to emable Intel PPro/PII write combining */ + +int PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type); +int PMAPI PM_enumWriteCombine(PM_enumWriteCombine_t callback); + +/* Function to add a path separator to the end of a filename (if not present) */ + +void PMAPI PM_backslash(char *filename); + +/* Routines to lock and unlock regions of memory under a virtual memory + * environment. These routines _must_ be used to lock all hardware + * and mouse interrupt handlers installed, _AND_ any global data that + * these handler manipulate, so that they will always be present in memory + * to handle the incoming interrupts. + * + * Note that it is important to call the correct routine depending on + * whether the area being locked is code or data, so that under 32 bit + * PM we will get the selector value correct. + */ + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lockHandle); +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lockHandle); +int PMAPI PM_lockCodePages(__codePtr p,uint len,PM_lockHandle *lockHandle); +int PMAPI PM_unlockCodePages(__codePtr p,uint len,PM_lockHandle *lockHandle); + +/* Routines to install and remove Real Time Clock interrupt handlers. The + * frequency of the real time clock can be changed by calling + * PM_setRealTimeClockFrequeny, and the value can be any power of 2 value + * from 2Hz to 8192Hz. + * + * Note that you _must_ lock the memory containing the interrupt + * handlers with the PM_lockPages() function otherwise you may encounter + * problems in virtual memory environments. + * + * NOTE: User space versions of the PM library should fail these functions. + */ + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih,int frequency); +void PMAPI PM_setRealTimeClockFrequency(int frequency); +void PMAPI PM_restoreRealTimeClockHandler(void); + +/* Routines to install and remove hardware interrupt handlers. + * + * Note that you _must_ lock the memory containing the interrupt + * handlers with the PM_lockPages() function otherwise you may encounter + * problems in virtual memory environments. + * + * NOTE: User space versions of the PM library should fail these functions. + */ + +PM_IRQHandle PMAPI PM_setIRQHandler(int IRQ,PM_irqHandler ih); +void PMAPI PM_restoreIRQHandler(PM_IRQHandle irqHandle); + +/* Functions to program DMA using the legacy ISA DMA controller */ + +void PMAPI PM_DMACEnable(int channel); +void PMAPI PM_DMACDisable(int channel); +void PMAPI PM_DMACProgram(int channel,int mode,ulong bufferPhys,int count); +ulong PMAPI PM_DMACPosition(int channel); + +/* Function to post secondary graphics controllers using the BIOS */ + +ibool PMAPI PM_doBIOSPOST(ushort axVal,ulong BIOSPhysAddr,void *mappedBIOS,ulong BIOSLen); + +/* Function to init the AGP functions and return the AGP aperture size in MB */ + +ulong PMAPI PM_agpInit(void); +void PMAPI PM_agpExit(void); + +/* Functions to reserve and release physical AGP memory ranges */ + +ibool PMAPI PM_agpReservePhysical(ulong numPages,int type,void **physContext,PM_physAddr *physAddr); +ibool PMAPI PM_agpReleasePhysical(void *physContext); + +/* Functions to commit and free physical AGP memory ranges */ + +ibool PMAPI PM_agpCommitPhysical(void *physContext,ulong numPages,ulong startOffset,PM_physAddr *physAddr); +ibool PMAPI PM_agpFreePhysical(void *physContext,ulong numPages,ulong startOffset); + +/* Functions to do I/O port manipulation directly from C code. These + * functions are portable and will work on any processor architecture + * to access I/O space registers on PCI devices. + */ + +uchar PMAPI PM_inpb(int port); +ushort PMAPI PM_inpw(int port); +ulong PMAPI PM_inpd(int port); +void PMAPI PM_outpb(int port,uchar val); +void PMAPI PM_outpw(int port,ushort val); +void PMAPI PM_outpd(int port,ulong val); + +/* Functions to determine the I/O port locations for COM and LPT ports. + * The functions are zero based, so for COM1 or LPT1 pass in a value of 0, + * for COM2 or LPT2 pass in a value of 1 etc. + */ + +int PMAPI PM_getCOMPort(int port); +int PMAPI PM_getLPTPort(int port); + +/* Internal functions that need prototypes */ + +void PMAPI _PM_getRMvect(int intno, long *realisr); +void PMAPI _PM_setRMvect(int intno, long realisr); +void PMAPI _PM_freeMemoryMappings(void); + +/* Function to override the default debug log file location */ + +void PMAPI PM_setDebugLog(const char *logFilePath); + +/* Function to put the process to sleep for the specified milliseconds */ + +void PMAPI PM_sleep(ulong milliseconds); + +/* Function to block until 'milliseconds' have passed since last call */ + +void PMAPI PM_blockUntilTimeout(ulong milliseconds); + +/* Functions for directory traversal and management */ + +void * PMAPI PM_findFirstFile(const char *filename,PM_findData *findData); +ibool PMAPI PM_findNextFile(void *handle,PM_findData *findData); +void PMAPI PM_findClose(void *handle); +void PMAPI PM_makepath(char *p,const char *drive,const char *dir,const char *name,const char *ext); +int PMAPI PM_splitpath(const char *fn,char *drive,char *dir,char *name,char *ext); +ibool PMAPI PM_driveValid(char drive); +void PMAPI PM_getdcwd(int drive,char *dir,int len); +uint PMAPI PM_getFileAttr(const char *filename); +void PMAPI PM_setFileAttr(const char *filename,uint attrib); +ibool PMAPI PM_getFileTime(const char *filename,ibool gmTime,PM_time *time); +ibool PMAPI PM_setFileTime(const char *filename,ibool gmTime,PM_time *time); +ibool PMAPI PM_mkdir(const char *filename); +ibool PMAPI PM_rmdir(const char *filename); + +/* Functions to handle loading OS specific shared libraries */ + +PM_MODULE PMAPI PM_loadLibrary(const char *szDLLName); +void * PMAPI PM_getProcAddress(PM_MODULE hModule,const char *szProcName); +void PMAPI PM_freeLibrary(PM_MODULE hModule); + +/* Functions and macros for 64-bit arithmetic */ + +void PMAPI _PM_add64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); +void PMAPI _PM_sub64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); +void PMAPI _PM_mul64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); +void PMAPI _PM_div64(u32 a_low,s32 a_high,u32 b_low,s32 b_high,__i64 *result); +void PMAPI _PM_shr64(u32 a_low,s32 a_high,s32 shift,__i64 *result); +void PMAPI _PM_sar64(u32 a_low,s32 a_high,s32 shift,__i64 *result); +void PMAPI _PM_shl64(u32 a_low,s32 a_high,s32 shift,__i64 *result); +void PMAPI _PM_neg64(u32 a_low,s32 a_high,__i64 *result); +#ifdef __NATIVE_INT64__ +#define PM_add64(r,a,b) (r) = (a) + (b) +#define PM_add64_32(r,a,b) (r) = (a) + (b) +#define PM_sub64(r,a,b) (r) = (a) - (b) +#define PM_sub64_32(r,a,b) (r) = (a) - (b) +#define PM_mul64(r,a,b) (r) = (a) * (b) +#define PM_mul64_32(r,a,b) (r) = (a) * (b) +#define PM_div64(r,a,b) (r) = (a) / (b) +#define PM_div64_32(r,a,b) (r) = (a) / (b) +#define PM_shr64(r,a,s) (r) = (a) >> (s) +#define PM_sar64(r,a,s) (r) = ((s64)(a)) >> (s) +#define PM_shl64(r,a,s) (r) = (u64)(a) << (s) +#define PM_neg64(r,a,s) (r) = -(a) +#define PM_not64(r,a,s) (r) = ~(a) +#define PM_eq64(a,b) (a) == (b) +#define PM_gt64(a,b) (a) > (b) +#define PM_lt64(a,b) (a) < (b) +#define PM_geq64(a,b) (a) >= (b) +#define PM_leq64(a,b) (a) <= (b) +#define PM_64to32(a) (u32)(a) +#define PM_64tos32(a) (s32)(a) +#define PM_set64(a,b,c) (a) = ((u64)(b) << 32) + (c) +#define PM_set64_32(a,b) (a) = (b) +#else +#define PM_add64(r,a,b) _PM_add64((a).low,(a).high,(b).low,(b).high,&(r)) +#define PM_add64_32(r,a,b) _PM_add64((a).low,(a).high,b,0,&(r)) +#define PM_sub64(r,a,b) _PM_sub64((a).low,(a).high,(b).low,(b).high,&(r)) +#define PM_sub64_32(r,a,b) _PM_sub64((a).low,(a).high,b,0,&(r)) +#define PM_mul64(r,a,b) _PM_mul64((a).low,(a).high,(b).low,(b).high,&(r)) +#define PM_mul64_32(r,a,b) _PM_mul64((a).low,(a).high,b,0,&(r)) +#define PM_div64(r,a,b) _PM_div64((a).low,(a).high,(b).low,(b).high,&(r)) +#define PM_div64_32(r,a,b) _PM_div64((a).low,(a).high,b,0,&(r)) +#define PM_shr64(r,a,s) _PM_shr64((a).low,(a).high,s,&(r)) +#define PM_sar64(r,a,s) _PM_sar64((a).low,(a).high,s,&(r)) +#define PM_shl64(r,a,s) _PM_shl64((a).low,(a).high,s,&(r)) +#define PM_neg64(r,a,s) _PM_neg64((a).low,(a).high,&(r)) +#define PM_not64(r,a,s) (r).low = ~(a).low, (r).high = ~(a).high +#define PM_eq64(a,b) ((a).low == (b).low && (a).high == (b).high) +#define PM_gt64(a,b) (((a).high > (b).high) || ((a).high == (b).high && (a).low > (b).low)) +#define PM_lt64(a,b) (((a).high < (b).high) || ((a).high == (b).high && (a).low < (b).low)) +#define PM_geq64(a,b) (PM_eq64(a,b) || PM_gt64(a,b)) +#define PM_leq64(a,b) (PM_eq64(a,b) || PM_lt64(a,b)) +#define PM_64to32(a) (u32)(a.low) +#define PM_64tos32(a) ((a).high < 0) ? -(a).low : (a).low) +#define PM_set64(a,b,c) (a).high = (b), (a).low = (c) +#define PM_set64_32(a,b) (a).high = 0, (a).low = (b) +#endif + +/* Function to enable IOPL access if required */ + +int PMAPI PM_setIOPL(int iopl); + +/* Function to flush the TLB and CPU caches */ + +void PMAPI PM_flushTLB(void); + +/* DOS specific fucntions */ + +#ifdef __MSDOS__ +uint PMAPI PMHELP_getVersion(void); +void PMAPI PM_VxDCall(VXD_regs *regs); +#endif + +/* Functions to save and restore the VGA hardware state */ + +int PMAPI PM_getVGAStateSize(void); +void PMAPI PM_saveVGAState(void *stateBuf); +void PMAPI PM_restoreVGAState(const void *stateBuf); +void PMAPI PM_vgaBlankDisplay(void); +void PMAPI PM_vgaUnblankDisplay(void); + +/* Functions to load and unload DirectDraw libraries. Only used on + * Windows platforms. + */ + +void * PMAPI PM_loadDirectDraw(int device); +void PMAPI PM_unloadDirectDraw(int device); +PM_HWND PMAPI PM_getDirectDrawWindow(void); +void PMAPI PM_doSuspendApp(void); + +/* Functions to install, start, stop and remove NT services. Valid only + * for Win32 apps running on Windows NT. + */ + +#ifdef __WINDOWS32__ +ulong PMAPI PM_installService(const char *szDriverName,const char *szServiceName,const char *szLoadGroup,ulong dwServiceType); +ulong PMAPI PM_startService(const char *szServiceName); +ulong PMAPI PM_stopService(const char *szServiceName); +ulong PMAPI PM_removeService(const char *szServiceName); +#endif + +/* Routines to generate native interrupts (ie: protected mode interrupts + * for protected mode apps) using an interface the same as that use by + * int86() and int86x() in realmode. These routines are required because + * many 32 bit compilers use different register structures and different + * functions causing major portability headaches. Thus we provide our + * own and solve it all in one fell swoop, and we also get a routine to + * put stuff into 32 bit registers from real mode ;-) + */ + +void PMAPI PM_segread(PMSREGS *sregs); +int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out); +int PMAPI PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs); + +/* Call the X86 emulator or the real BIOS in our test harness */ + +#if defined(TEST_HARNESS) && !defined(PMLIB) +#define PM_mapRealPointer(r_seg,r_off) _PM_imports.PM_mapRealPointer(r_seg,r_off) +#define PM_getVESABuf(len,rseg,roff) _PM_imports.PM_getVESABuf(len,rseg,roff) +#define PM_callRealMode(seg,off,regs,sregs) _PM_imports.PM_callRealMode(seg,off,regs,sregs) +#define PM_int86(intno,in,out) _PM_imports.PM_int86(intno,in,out) +#define PM_int86x(intno,in,out,sregs) _PM_imports.PM_int86x(intno,in,out,sregs) +#endif + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +/* Include OS extensions for interrupt handling */ + +#if defined(__REALDOS__) || defined(__SMX32__) +#include "pmint.h" +#endif + +#endif /* __PMAPI_H */ diff --git a/board/MAI/bios_emulator/scitech/include/pmimp.h b/board/MAI/bios_emulator/scitech/include/pmimp.h new file mode 100644 index 000000000..817f5e6a2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pmimp.h @@ -0,0 +1,193 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Header file declaring all the PM imports structure for the +* current version of the PM library. Included in all code +* that needs to pass the PM imports to BPD files. +* +****************************************************************************/ + +PM_imports _VARAPI _PM_imports = { + sizeof(PM_imports), + PM_getModeType, + PM_getBIOSPointer, + PM_getA0000Pointer, + PM_mapPhysicalAddr, + PM_mallocShared, + NULL, + PM_freeShared, + PM_mapToProcess, + PM_mapRealPointer, + PM_allocRealSeg, + PM_freeRealSeg, + PM_allocLockedMem, + PM_freeLockedMem, + PM_callRealMode, + PM_int86, + PM_int86x, + DPMI_int86, + PM_availableMemory, + PM_getVESABuf, + PM_getOSType, + PM_fatalError, + PM_setBankA, + PM_setBankAB, + PM_setCRTStart, + PM_getCurrentPath, + PM_getVBEAFPath, + PM_getNucleusPath, + PM_getNucleusConfigPath, + PM_getUniqueID, + PM_getMachineName, + VF_available, + VF_init, + VF_exit, + PM_openConsole, + PM_getConsoleStateSize, + PM_saveConsoleState, + PM_restoreConsoleState, + PM_closeConsole, + PM_setOSCursorLocation, + PM_setOSScreenWidth, + PM_enableWriteCombine, + PM_backslash, + PM_lockDataPages, + PM_unlockDataPages, + PM_lockCodePages, + PM_unlockCodePages, + PM_setRealTimeClockHandler, + PM_setRealTimeClockFrequency, + PM_restoreRealTimeClockHandler, + PM_doBIOSPOST, + PM_getBootDrive, + PM_freePhysicalAddr, + PM_inpb, + PM_inpw, + PM_inpd, + PM_outpb, + PM_outpw, + PM_outpd, + NULL, + PM_setSuspendAppCallback, + PM_haveBIOSAccess, + PM_kbhit, + PM_getch, + PM_findBPD, + PM_getPhysicalAddr, + PM_sleep, + PM_getCOMPort, + PM_getLPTPort, + PM_loadLibrary, + PM_getProcAddress, + PM_freeLibrary, + PCI_enumerate, + PCI_accessReg, + PCI_setHardwareIRQ, + PCI_generateSpecialCyle, + NULL, + PCIBIOS_getEntry, + CPU_getProcessorType, + CPU_haveMMX, + CPU_have3DNow, + CPU_haveSSE, + CPU_haveRDTSC, + CPU_getProcessorSpeed, + ZTimerInit, + LZTimerOn, + LZTimerLap, + LZTimerOff, + LZTimerCount, + LZTimerOnExt, + LZTimerLapExt, + LZTimerOffExt, + LZTimerCountExt, + ULZTimerOn, + ULZTimerLap, + ULZTimerOff, + ULZTimerCount, + ULZReadTime, + ULZElapsedTime, + ULZTimerResolution, + PM_findFirstFile, + PM_findNextFile, + PM_findClose, + PM_makepath, + PM_splitpath, + PM_driveValid, + PM_getdcwd, + PM_setFileAttr, + PM_mkdir, + PM_rmdir, + PM_getFileAttr, + PM_getFileTime, + PM_setFileTime, + CPU_getProcessorName, + PM_getVGAStateSize, + PM_saveVGAState, + PM_restoreVGAState, + PM_vgaBlankDisplay, + PM_vgaUnblankDisplay, + PM_blockUntilTimeout, + _PM_add64, + _PM_sub64, + _PM_mul64, + _PM_div64, + _PM_shr64, + _PM_sar64, + _PM_shl64, + _PM_neg64, + PCI_findBARSize, + PCI_readRegBlock, + PCI_writeRegBlock, + PM_flushTLB, + PM_useLocalMalloc, + PM_malloc, + PM_calloc, + PM_realloc, + PM_free, + PM_getPhysicalAddrRange, + PM_allocPage, + PM_freePage, + PM_agpInit, + PM_agpExit, + PM_agpReservePhysical, + PM_agpReleasePhysical, + PM_agpCommitPhysical, + PM_agpFreePhysical, + PCI_getNumDevices, + PM_setLocalBPDPath, +#ifdef __WINDOWS32__ + PM_loadDirectDraw, + PM_unloadDirectDraw, + PM_getDirectDrawWindow, + PM_doSuspendApp, +#else + NULL, + NULL, + NULL, + NULL, +#endif + }; diff --git a/board/MAI/bios_emulator/scitech/include/pmint.h b/board/MAI/bios_emulator/scitech/include/pmint.h new file mode 100644 index 000000000..7d76dad50 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/pmint.h @@ -0,0 +1,211 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Real mode and 16/32 bit Protected Mode +* +* Description: Header file for the interrupt handling extensions to the OS +* Portability Manager Library. These extensions includes +* simplified interrupt handling, allowing all common interrupt +* handlers to be hooked and handled directly with normal C +* functions, both in 16 bit and 32 bit modes. Note however that +* simplified handling does not mean slow performance! All low +* level interrupt handling is done efficiently in assembler +* for speed (well actually necessary to insulate the +* application from the lack of far pointers in 32 bit PM). The +* interrupt handlers currently supported are: +* +* Mouse (0x33 callback) +* Timer Tick (0x8) +* Keyboard (0x9 and 0x15) +* Control C/Break (0x23/0x1B) +* Critical Error (0x24) +* +****************************************************************************/ + +#ifndef __PMINT_H +#define __PMINT_H + +/*--------------------------- Macros and Typedefs -------------------------*/ + +#ifdef __SMX32__ +/* PC interrupts (Ensure consistent with pme.inc) */ +#define PM_IRQ0 0x40 +#define PM_IRQ1 (PM_IRQ0+1) +#define PM_IRQ6 (PM_IRQ0+6) +#define PM_IRQ14 (PM_IRQ0+14) +#endif + +/* Define the different types of interrupt handlers that we support */ + +typedef uint (PMAPIP PM_criticalHandler)(uint axValue,uint diValue); +typedef void (PMAPIP PM_breakHandler)(uint breakHit); +typedef short (PMAPIP PM_key15Handler)(short scanCode); +typedef void (PMAPIP PM_mouseHandler)(uint event, uint butstate,int x,int y,int mickeyX,int mickeyY); + +/* Create a type for representing far pointers in both 16 and 32 bit + * protected mode. + */ + +#ifdef PM386 +typedef struct { + long off; + short sel; + } PMFARPTR; +#define PMNULL {0,0} +#else +typedef void *PMFARPTR; +#define PMNULL NULL +#endif + +/*--------------------------- Function Prototypes -------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Routine to load save default data segment selector value into a code + * segment variable, and another to load the value into the DS register. + */ + +void PMAPI PM_loadDS(void); +void PMAPI PM_saveDS(void); + +/* Routine to install a mouse interrupt handling routine. The + * mouse handler routine is a normal C function, and the PM library + * will take care of passing the correct parameters to the function, + * and switching to a local stack. + * + * Note that you _must_ lock the memory containing the mouse interrupt + * handler with the PM_lockPages() function otherwise you may encounter + * problems in virtual memory environments. + */ + +int PMAPI PM_setMouseHandler(int mask,PM_mouseHandler mh); +void PMAPI PM_restoreMouseHandler(void); + +/* Routine to reset the mouse driver, and re-install the current + * mouse interrupt handler if one was currently installed (since the + * mouse reset will automatically remove this handler. + */ + +void PMAPI PM_resetMouseDriver(int hardReset); + +/* Routine to reset the mouse driver, and re-install the current + * mouse interrupt handler if one was currently installed (since the + * mouse reset will automatically remove this handler. + */ + +void PMAPI PM_resetMouseDriver(int hardReset); + +/* Routines to install and remove timer interrupt handlers. + * + * Note that you _must_ lock the memory containing the interrupt + * handlers with the PM_lockPages() function otherwise you may encounter + * problems in virtual memory environments. + */ + +void PMAPI PM_setTimerHandler(PM_intHandler ih); +void PMAPI PM_chainPrevTimer(void); +void PMAPI PM_restoreTimerHandler(void); + +/* Routines to install and keyboard interrupt handlers. + * + * Note that you _must_ lock the memory containing the interrupt + * handlers with the PM_lockPages() function otherwise you may encounter + * problems in virtual memory environments. + */ + +void PMAPI PM_setKeyHandler(PM_intHandler ih); +void PMAPI PM_chainPrevKey(void); +void PMAPI PM_restoreKeyHandler(void); + +/* Routines to hook and unhook the alternate Int 15h keyboard intercept + * callout routine. Your event handler will need to return the following: + * + * scanCode - Let the BIOS process scan code (chains to previous handler) + * 0 - You have processed the scan code so flush from BIOS + * + * Note that this is not available under all DOS extenders, but does + * work under real mode, DOS4GW and X32-VM. It does not work under the + * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know! + */ + +void PMAPI PM_setKey15Handler(PM_key15Handler ih); +void PMAPI PM_restoreKey15Handler(void); + +/* Routines to install and remove the control c/break interrupt handlers. + * Interrupt handling is performed by the PM/Pro library, and you can call + * the supplied routines to test the status of the Ctrl-C and Ctrl-Break + * flags. If you pass the value TRUE for 'clearFlag' to these routines, + * the internal flags will be reset in order to catch another Ctrl-C or + * Ctrl-Break interrupt. + */ + +void PMAPI PM_installBreakHandler(void); +int PMAPI PM_ctrlCHit(int clearFlag); +int PMAPI PM_ctrlBreakHit(int clearFlag); +void PMAPI PM_restoreBreakHandler(void); + +/* Routine to install an alternate break handler that will call your + * code directly. This is not available under all DOS extenders, but does + * work under real mode, DOS4GW and X32-VM. It does not work under the + * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know! + * + * Note that you should either install one or the other, but not both! + */ + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh); + +/* Routines to install and remove the critical error handler. The interrupt + * is handled by the PM/Pro library, and the operation will always be failed. + * You can check the status of the critical error handler with the + * appropriate function. If you pass the value TRUE for 'clearFlag', the + * internal flag will be reset ready to catch another critical error. + */ + +void PMAPI PM_installCriticalHandler(void); +int PMAPI PM_criticalError(int *axValue, int *diValue, int clearFlag); +void PMAPI PM_restoreCriticalHandler(void); + +/* Routine to install an alternate critical handler that will call your + * code directly. This is not available under all DOS extenders, but does + * work under real mode, DOS4GW and X32-VM. It does not work under the + * PowerPack 32 bit DOS extenders. If you figure out how to do it let us know! + * + * Note that you should either install one or the other, but not both! + */ + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler); + +/* Functions to manage protected mode only interrupt handlers */ + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr); +void PMAPI PM_setPMvect(int intno, PM_intHandler ih); +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __PMINT_H */ diff --git a/board/MAI/bios_emulator/scitech/include/scitech.h b/board/MAI/bios_emulator/scitech/include/scitech.h new file mode 100644 index 000000000..8d5eee944 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/scitech.h @@ -0,0 +1,712 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: General header file for operating system portable code. +* +****************************************************************************/ + +#ifndef __SCITECH_H +#define __SCITECH_H + +/* We have the following defines to identify the compilation environment: + * + * __16BIT__ Compiling for 16 bit code (any environment) + * __32BIT__ Compiling for 32 bit code (any environment) + * __MSDOS__ Compiling for MS-DOS (includes __WINDOWS16__, __WIN386__) + * __REALDOS__ Compiling for MS-DOS (excludes __WINDOWS16__) + * __MSDOS16__ Compiling for 16 bit MS-DOS + * __MSDOS32__ Compiling for 32 bit MS-DOS + * __WINDOWS__ Compiling for Windows + * __WINDOWS16__ Compiling for 16 bit Windows (__MSDOS__ also defined) + * __WINDOWS32__ Compiling for 32 bit Windows + * __WIN32_VXD__ Compiling for a 32-bit C based VxD + * __NT_DRIVER__ Compiling for a 32-bit C based NT device driver + * __OS2__ Compiling for OS/2 + * __OS2_16__ Compiling for 16 bit OS/2 + * __OS2_32__ Compiling for 32 bit OS/2 + * __UNIX__ Compiling for Unix + * __QNX__ Compiling for the QNX realtime OS (Unix compatible) + * __LINUX__ Compiling for the Linux OS (Unix compatible) + * __FREEBSD__ Compiling for the FreeBSD OS (Unix compatible) + * __BEOS__ Compiling for the BeOS (Unix compatible) + * __SMX32__ Compiling for the SMX 32-bit Real Time OS + * __ENEA_OSE__ Compiling for the OSE embedded OS + * __RTTARGET__ Compiling for the RTTarget 32-bit embedded OS + * __MACOS__ Compiling for the MacOS platform (PowerPC) + * __DRIVER__ Compiling for a 32-bit binary compatible driver + * __CONSOLE__ Compiling for a fullscreen OS console mode + * __SNAP__ Compiling as a Snap executeable or dynamic library + * + * __INTEL__ Compiling for Intel CPU's + * __ALPHA__ Compiling for DEC Alpha CPU's + * __MIPS__ Compiling for MIPS CPU's + * __PPC__ Compiling for PowerPC CPU's + * __MC68K__ Compiling for Motorola 680x0 + * + * __BIG_ENDIAN__ Compiling for a big endian processor + * + */ + +#ifdef __SC__ +#if __INTSIZE == 4 +#define __SC386__ +#endif +#endif + +/* Determine some things that are compiler specific */ + +#ifdef __GNUC__ +#ifdef __cplusplus +/* G++ currently fucks this up! */ +#define __cdecl +#define __stdcall +#else +#undef __cdecl +#undef __stdcall +#define __cdecl __attribute__ ((cdecl)) +#define __stdcall __attribute__ ((stdcall)) +#endif +#define __FLAT__ /* GCC is always 32 bit flat model */ +#define __HAS_BOOL__ /* Latest GNU C++ has ibool type */ +#define __HAS_LONG_LONG__ /* GNU C supports long long type */ +#include /* Bring in for definition of NULL */ +#endif + +#ifdef __BORLANDC__ +#if (__BORLANDC__ >= 0x500) || defined(CLASSLIB_DEFS_H) +#define __HAS_BOOL__ /* Borland C++ 5.0 defines ibool type */ +#endif +#if (__BORLANDC__ >= 0x502) && !defined(VTOOLSD) && !defined(__SMX32__) +#define __HAS_INT64__ /* Borland C++ 5.02 supports __int64 type */ +#endif +#endif + +#if defined(_MSC_VER) && !defined(__SC__) && !defined(VTOOLSD) && !defined(__SMX32__) +#define __HAS_INT64__ /* Visual C++ supports __int64 type */ +#endif + +#if defined(__WATCOMC__) && (__WATCOMC__ >= 1100) && !defined(VTOOLSD) && !defined(__SMX32__) +#define __HAS_INT64__ /* Watcom C++ 11.0 supports __int64 type */ +#endif + +/*--------------------------------------------------------------------------- + * Determine the compile time environment. This must be done for each + * supported platform so that we can determine at compile time the target + * environment, hopefully without requiring #define's from the user. + *-------------------------------------------------------------------------*/ + +/* 32-bit binary compatible driver. Compiled as Win32, but as OS neutral */ +#ifdef __DRIVER__ +#ifndef __32BIT__ +#define __32BIT__ +#endif +#undef __WINDOWS__ +#undef _WIN32 +#undef __WIN32__ +#undef __NT__ + +/* 32-bit Snap exe or dll. Compiled as Win32, but as OS neutral */ +#elif defined(__SNAP__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#undef __WINDOWS__ +#undef _WIN32 +#undef __WIN32__ +#undef __NT__ + +/* 32-bit Windows VxD compile environment */ +#elif defined(__vtoolsd_h_) || defined(VTOOLSD) +#include +#define __WIN32_VXD__ +#ifndef __32BIT__ +#define __32BIT__ +#endif +#define _MAX_PATH 256 +#undef __WINDOWS32__ + +/* 32-bit Windows NT driver compile environment: TODO!! */ +#elif defined(__NT_DRIVER__) +#include "ntdriver.h" +#ifndef __32BIT__ +#define __32BIT__ +#endif +#define _MAX_PATH 256 +#undef __WINDOWS32__ + +/* 32-bit SMX compile environment */ +#elif defined(__SMX32__) +#ifndef __MSDOS__ +#define __MSDOS__ +#endif +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif + +/* 32-bit Enea OSE environment */ +#elif defined(__ENEA_OSE__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif + +/* 32-bit RTTarget-32 environment */ +#elif defined(__RTTARGET__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif + +/* 32-bit extended DOS compile environment */ +#elif defined(__MSDOS__) || defined(__MSDOS32__) || defined(__DOS__) || defined(__DPMI32__) || (defined(M_I86) && (!defined(__SC386__) && !defined(M_I386))) || defined(TNT) +#ifndef __MSDOS__ +#define __MSDOS__ +#endif +#if defined(__MSDOS32__) || defined(__386__) || defined(__FLAT__) || defined(__NT__) || defined(__SC386__) +#ifndef __MSDOS32__ +#define __MSDOS32__ +#endif +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __REALDOS__ +#define __REALDOS__ +#endif +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif + +/* 16-bit Windows compile environment */ +#elif (defined(_Windows) || defined(_WINDOWS)) && !defined(__DPMI16__) +#ifndef __16BIT__ +#define __16BIT__ +#endif +#ifndef __WINDOWS16__ +#define __WINDOWS16__ +#endif +#ifndef __WINDOWS__ +#define __WINDOWS__ +#endif +#ifndef __MSDOS__ +#define __MSDOS__ +#endif + +/* 16-bit DOS compile environment */ +#else +#ifndef __16BIT__ +#define __16BIT__ +#endif +#ifndef __MSDOS16__ +#define __MSDOS16__ +#endif +#ifndef __REALDOS__ +#define __REALDOS__ +#endif +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit Windows compile environment */ +#elif defined(WIN32) || defined(_WIN32) || defined(__WIN32__) || defined(__NT__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __WINDOWS32__ +#define __WINDOWS32__ +#endif +#ifndef _WIN32 +#define _WIN32 /* Microsoft Win32 SDK headers use _WIN32 */ +#endif +#ifndef WIN32 +#define WIN32 /* OpenGL headers use WIN32 */ +#endif +#ifndef __WINDOWS__ +#define __WINDOWS__ +#endif + +/* 32-bit OS/2 VDD compile environment */ +/* We're assuming (for now) that CL386 must be used */ +#elif defined(MSDOS) && defined(M_I386) +/* fixes necessary to compile with CL386 */ +#define __cdecl _cdecl +typedef unsigned int size_t; + +#include + +/* This should probably be somewhere else... */ +/* Inline eligible functions (we have no CRT libs for CL386) */ +#pragma intrinsic (strcpy, strcmp, strlen, strcat) +#pragma intrinsic (memcmp, memcpy, memset) + +#define __OS2_VDD__ +#ifndef __32BIT__ +#define __32BIT__ +#endif +#define CCHMAXPATH 256 +#define _MAX_PATH 256 +#ifndef __OS2__ +#define __OS2__ +#endif +#ifndef __OS2_32__ +#define __OS2_32__ +#endif + +/* 16-bit OS/2 compile environment */ +#elif defined(__OS2_16__) +#ifndef __OS2__ +#define __OS2__ +#endif +#ifndef __16BIT__ +#define __16BIT__ +#endif +#ifndef __OS2_PM__ +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit OS/2 compile environment */ +#elif defined(__OS2__) || defined(__OS2_32__) +#ifndef __OS2__ +#define __OS2__ +#endif +#ifndef __OS2_32__ +#define __OS2_32__ +#endif +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __OS2_PM__ +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit QNX compile environment */ +#elif defined(__QNX__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __UNIX__ +#define __UNIX__ +#endif +#ifdef __GNUC__ +#define stricmp strcasecmp +#endif +#if !defined(__PHOTON__) && !defined(__X11__) +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit Linux compile environment */ +#elif defined(__LINUX__) || defined(linux) +#ifndef __LINUX__ +#define __LINUX__ +#endif +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __UNIX__ +#define __UNIX__ +#endif +#ifdef __GNUC__ +#define stricmp strcasecmp +#endif +#ifndef __X11__ +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit FreeBSD compile environment */ +#elif defined(__FREEBSD__) +#ifndef __FREEBSD__ +#define __FREEBSD__ +#endif +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __UNIX__ +#define __UNIX__ +#endif +#ifdef __GNUC__ +#define stricmp strcasecmp +#endif +#ifndef __X11__ +#ifndef __CONSOLE__ +#define __CONSOLE__ +#endif +#endif + +/* 32-bit BeOS compile environment */ +#elif defined(__BEOS__) +#ifndef __32BIT__ +#define __32BIT__ +#endif +#ifndef __UNIX__ +#define __UNIX__ +#endif +#ifdef __GNUC__ +#define stricmp strcasecmp +#endif + +/* Unsupported OS! */ +#else +#error This platform is not currently supported! +#endif + +/* Determine the CPU type that we are compiling for */ + +#if defined(__M_ALPHA) || defined(__ALPHA_) || defined(__ALPHA) || defined(__alpha) +#ifndef __ALPHA__ +#define __ALPHA__ +#endif +#elif defined(__M_PPC) || defined(__POWERC) +#ifndef __PPC__ +#define __PPC__ +#endif +#elif defined(__M_MRX000) +#ifndef __MIPS__ +#define __MIPS__ +#endif +#else +#ifndef __INTEL__ +#define __INTEL__ /* Assume Intel if nothing found */ +#endif +#endif + +/* We have the following defines to define the calling conventions for + * publicly accesible functions: + * + * _PUBAPI - Compiler default calling conventions for all public 'C' functions + * _ASMAPI - Calling conventions for all public assembler functions + * _VARAPI - Modifiers for variables; Watcom C++ mangles C++ globals + * _STDCALL - Win32 __stdcall where possible, __cdecl if not supported + */ + +#if defined(_MSC_VER) && defined(_WIN32) && !defined(__SC__) +#define __PASCAL __stdcall +#else +#define __PASCAL __pascal +#endif + +#if defined(NO_STDCALL) +#define _STDCALL __cdecl +#else +#define _STDCALL __stdcall +#endif + +#ifdef __WATCOMC__ +#if (__WATCOMC__ >= 1050) +#define _VARAPI __cdecl +#else +#define _VARAPI +#endif +#else +#define _VARAPI +#endif + +#if defined(__IBMC__) || defined(__IBMCPP__) +#define PTR_DECL_IN_FRONT +#endif + +/* Define the calling conventions for all public functions. For simplicity + * we define all public functions as __cdecl calling conventions, so that + * they are the same across all compilers and runtime DLL's. + */ + +#define _PUBAPI __cdecl +#define _ASMAPI __cdecl + +/* Determine the syntax for declaring a function pointer with a + * calling conventions override. Most compilers require the calling + * convention to be declared in front of the '*', but others require + * it to be declared after the '*'. We handle both in here depending + * on what the compiler requires. + */ + +#ifdef PTR_DECL_IN_FRONT +#define _PUBAPIP * _PUBAPI +#define _ASMAPIP * _ASMAPI +#else +#define _PUBAPIP _PUBAPI * +#define _ASMAPIP _ASMAPI * +#endif + +/* Useful macros */ + +#define PRIVATE static +#define PUBLIC + +/* This HAS to be 0L for 16-bit real mode code to work!!! */ + +#ifndef NULL +# define _NULL 0L +# define NULL _NULL +#endif + +#ifndef MAX +# define MAX(a,b) ( ((a) > (b)) ? (a) : (b)) +#endif +#ifndef MIN +# define MIN(a,b) ( ((a) < (b)) ? (a) : (b)) +#endif +#ifndef ABS +# define ABS(a) ((a) >= 0 ? (a) : -(a)) +#endif +#ifndef SIGN +# define SIGN(a) ((a) > 0 ? 1 : -1) +#endif + +/* General typedefs */ + +#ifndef __GENDEFS +#define __GENDEFS +#if defined(__BEOS__) +#include +#else +#ifdef __LINUX__ +#include +#ifdef __STRICT_ANSI__ +typedef unsigned short ushort; +typedef unsigned long ulong; +typedef unsigned int uint; +#endif +#ifdef __KERNEL__ +#define __GENDEFS_2 +#endif +#else +#if !(defined(__QNXNTO__) && defined(GENERAL_STRUCT)) +typedef unsigned short ushort; +typedef unsigned long ulong; +#endif +typedef unsigned int uint; +#endif +typedef unsigned char uchar; +#endif +typedef int ibool; /* Integer boolean type */ +#ifdef USE_BOOL /* Only for older code */ +#ifndef __cplusplus +#define bool ibool /* Standard C */ +#else +#ifndef __HAS_BOOL__ +#define bool ibool /* Older C++ compilers */ +#endif +#endif /* __cplusplus */ +#endif /* USE_BOOL */ +#endif /* __GENDEFS */ + +/* More general typedefs compatible with Linux kernel code */ + +#ifndef __GENDEFS_2 +#define __GENDEFS_2 +typedef char s8; +typedef unsigned char u8; +typedef short s16; +typedef unsigned short u16; +#ifdef __16BIT__ +typedef long s32; +typedef unsigned long u32; +#else +typedef int s32; +typedef unsigned int u32; +#endif +typedef struct { + u32 low; + s32 high; + } __i64; +#ifdef __HAS_LONG_LONG__ +#define __NATIVE_INT64__ +typedef long long s64; +typedef unsigned long long u64; +#elif defined(__HAS_INT64__) && !defined(__16BIT__) +#define __NATIVE_INT64__ +typedef __int64 s64; +typedef unsigned __int64 u64; +#else +typedef __i64 s64; +typedef __i64 u64; +#endif +#endif + +/* Boolean truth values */ + +#undef false +#undef true +#undef NO +#undef YES +#undef FALSE +#undef TRUE +#define false 0 +#define true 1 +#define NO 0 +#define YES 1 +#define FALSE 0 +#define TRUE 1 + +/* Inline debugger interrupts for Watcom C++ and Borland C++ */ + +#ifdef __WATCOMC__ +void DebugInt(void); +#pragma aux DebugInt = \ + "int 3"; +void DebugVxD(void); +#pragma aux DebugVxD = \ + "int 1"; +#elif defined(__BORLANDC__) +#define DebugInt() __emit__(0xCC) +#define DebugVxD() {__emit__(0xCD); __emit__(0x01);} +#elif defined(_MSC_VER) +#define DebugInt() _asm int 0x3 +#define DebugVxD() _asm int 0x1 +#elif defined(__GNUC__) +#define DebugInt() asm volatile ("int $0x3") +#define DebugVxD() asm volatile ("int $0x1") +#else +void _ASMAPI DebugInt(void); +void _ASMAPI DebugVxD(void); +#endif + +/* Macros to break once and never break again */ + +#define DebugIntOnce() \ +{ \ + static ibool firstTime = true; \ + if (firstTime) { \ + firstTime = false; \ + DebugInt(); \ + } \ +} + +#define DebugVxDOnce() \ +{ \ + static ibool firstTime = true; \ + if (firstTime) { \ + firstTime = false; \ + DebugVxD(); \ + } \ +} + +/* Macros for linux string compatibility functions */ + +#ifdef __LINUX__ +#define stricmp strcasecmp +#define strnicmp strncasecmp +#endif + +/* Macros for NT driver string compatibility functions */ + +#ifdef __NT_DRIVER__ +#define stricmp _stricmp +#define strnicmp _strnicmp +#endif + +/* Get rid of some helaciously annoying Visual C++ warnings! */ + +#if defined(_MSC_VER) && !defined(__MWERKS__) && !defined(__SC__) +#pragma warning(disable:4761) /* integral size mismatch in argument; conversion supplied */ +#pragma warning(disable:4244) /* conversion from 'unsigned short ' to 'unsigned char ', possible loss of data */ +#pragma warning(disable:4018) /* '<' : signed/unsigned mismatch */ +#pragma warning(disable:4305) /* 'initializing' : truncation from 'const double' to 'float' */ +#endif + +/*--------------------------------------------------------------------------- + * Set of debugging macros used by the libraries. If the debug flag is + * set, they are turned on depending on the setting of the flag. User code + * can override the default functions called when a check fails, and the + * MGL does this so it can restore the system from graphics mode to display + * an error message. These functions also log information to the + * scitech.log file in the root directory of the hard drive when problems + * show up. + * + * If you set the value of CHECKED to be 2, it will also enable code to + * insert hard coded debugger interrupt into the source code at the line of + * code where the check fail. This is useful if you run the code under a + * debugger as it will break inside the debugger before exiting with a + * failure condition. + * + * Also for code compiled to run under Windows, we also call the + * OutputDebugString function to send the message to the system debugger + * such as Soft-ICE or WDEB386. Hence if you get any non-fatal warnings you + * will see those on the debugger terminal as well as in the log file. + *-------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line); +void _CHK_defaultFail(int fatal,const char *msg,const char *cond,const char *file,int line); + +#ifdef CHECKED +# define CHK(x) x +#if CHECKED > 1 +# define CHECK(p) \ + ((p) ? (void)0 : DebugInt(), \ + _CHK_fail(1,"Check failed: '%s', file %s, line %d\n", \ + #p, __FILE__, __LINE__)) +# define WARN(p) \ + ((p) ? (void)0 : DebugInt(), \ + _CHK_fail(0,"Warning: '%s', file %s, line %d\n", \ + #p, __FILE__, __LINE__)) +#else +# define CHECK(p) \ + ((p) ? (void)0 : \ + _CHK_fail(1,"Check failed: '%s', file %s, line %d\n", \ + #p, __FILE__, __LINE__)) +# define WARN(p) \ + ((p) ? (void)0 : \ + _CHK_fail(0,"Warning: '%s', file %s, line %d\n", \ + #p, __FILE__, __LINE__)) +#endif +# define LOGFATAL(msg) \ + _CHK_fail(1,"Fatal error: '%s', file %s, line %d\n", \ + msg, __FILE__, __LINE__) +# define LOGWARN(msg) \ + _CHK_fail(0,"Warning: '%s', file %s, line %d\n", \ + msg, __FILE__, __LINE__) +#else +# define CHK(x) +# define CHECK(p) ((void)0) +# define WARN(p) ((void)0) +# define LOGFATAL(msg) ((void)0) +# define LOGWARN(msg) ((void)0) +#endif + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __SCITECH_H */ diff --git a/board/MAI/bios_emulator/scitech/include/scitech.mac b/board/MAI/bios_emulator/scitech/include/scitech.mac new file mode 100644 index 000000000..27a2fc06e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/scitech.mac @@ -0,0 +1,1321 @@ +;**************************************************************************** +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NetWide Assembler (NASM) or Turbo Assembler (TASM) +;* Environment: Any Intel Environment +;* +;* Description: Macros to provide memory model independant assembly language +;* module for C programming. Supports the large and flat memory +;* models. +;* +;* The defines that you should use when assembling modules that +;* use this macro package are: +;* +;* __LARGE__ Assemble for 16-bit large model +;* __FLAT__ Assemble for 32-bit FLAT memory model +;* __NOU__ No underscore for all external C labels +;* __NOU_VAR__ No underscore for global variables only +;* +;* The default settings are for 16-bit large memory model with +;* leading underscores for symbol names. +;* +;* The main intent of the macro file is to enable programmers +;* to write _one_ set of source that can be assembled to run +;* in either 16 bit real and protected modes or 32 bit +;* protected mode without the need to riddle the code with +;* 'if flatmodel' style conditional assembly (it is still there +;* but nicely hidden by a macro layer that enhances the +;* readability and understandability of the resulting code). +;* +;**************************************************************************** + +; Include the appropriate version in here depending on the assembler. NASM +; appears to always try and parse code, even if it is in a non-compiling +; block of a ifdef expression, and hence crashes if we include the TASM +; macro package in the same header file. Hence we split the macros up into +; two separate header files. + +ifdef __NASM_MAJOR__ + +;============================================================================ +; Macro package when compiling with NASM. +;============================================================================ + +; Turn off underscores for globals if disabled for all externals + +%ifdef __NOU__ +%define __NOU_VAR__ +%endif + +; Define the __WINDOWS__ symbol if we are compiling for any Windows +; environment + +%ifdef __WINDOWS16__ +%define __WINDOWS__ 1 +%endif +%ifdef __WINDOWS32__ +%define __WINDOWS__ 1 +%define __WINDOWS32_386__ 1 +%endif + +; Macros for accessing 'generic' registers + +%ifdef __FLAT__ +%idefine _ax eax +%idefine _bx ebx +%idefine _cx ecx +%idefine _dx edx +%idefine _si esi +%idefine _di edi +%idefine _bp ebp +%idefine _sp esp +%idefine _es +%idefine UCHAR BYTE ; Size of a character +%idefine USHORT WORD ; Size of a short +%idefine UINT DWORD ; Size of an integer +%idefine ULONG DWORD ; Size of a long +%idefine BOOL DWORD ; Size of a boolean +%idefine DPTR DWORD ; Size of a data pointer +%idefine FDPTR FWORD ; Size of a far data pointer +%idefine NDPTR DWORD ; Size of a near data pointer +%idefine CPTR DWORD ; Size of a code pointer +%idefine FCPTR FWORD ; Size of a far code pointer +%idefine NCPTR DWORD ; Size of a near code pointer +%idefine FPTR NEAR ; Distance for function pointers +%idefine DUINT dd ; Declare a integer variable +%idefine intsize 4 +%idefine flatmodel 1 +%else +%idefine _ax ax +%idefine _bx bx +%idefine _cx cx +%idefine _dx dx +%idefine _si si +%idefine _di di +%idefine _bp bp +%idefine _sp sp +%idefine _es es: +%idefine UCHAR BYTE ; Size of a character +%idefine USHORT WORD ; Size of a short +%idefine UINT WORD ; Size of an integer +%idefine ULONG DWORD ; Size of a long +%idefine BOOL WORD ; Size of a boolean +%idefine DPTR DWORD ; Size of a data pointer +%idefine FDPTR DWORD ; Size of a far data pointer +%idefine NDPTR WORD ; Size of a near data pointer +%idefine CPTR DWORD ; Size of a code pointer +%idefine FCPTR DWORD ; Size of a far code pointer +%idefine NCPTR WORD ; Size of a near code pointer +%idefine FPTR FAR ; Distance for function pointers +%idefine DUINT dw ; Declare a integer variable +%idefine intsize 2 +%endif +%idefine invert ~ +%idefine offset +%idefine use_nasm + +; Convert all jumps to near jumps, since NASM does not so this automatically + +%idefine jo jo near +%idefine jno jno near +%idefine jz jz near +%idefine jnz jnz near +%idefine je je near +%idefine jne jne near +%idefine jb jb near +%idefine jbe jbe near +%idefine ja ja near +%idefine jae jae near +%idefine jl jl near +%idefine jle jle near +%idefine jg jg near +%idefine jge jge near +%idefine jc jc near +%idefine jnc jnc near +%idefine js js near +%idefine jns jns near + +%ifdef DOUBLE +%idefine REAL QWORD +%idefine DREAL dq +%else +%idefine REAL DWORD +%idefine DREAL dd +%endif + +; Boolean truth values (same as those in debug.h) + +%idefine False 0 +%idefine True 1 +%idefine No 0 +%idefine Yes 1 +%idefine Yes 1 + +; Macro to be invoked at the start of all modules to set up segments for +; later use. Does nothing for NASM. + +%imacro header 1 +%endmacro + +; Macro to begin a data segment + +%imacro begdataseg 1 +%ifdef __GNUC__ +segment .data public class=DATA use32 flat +%else +%ifdef flatmodel +segment _DATA public align=4 class=DATA use32 flat +%else +segment _DATA public align=4 class=DATA use16 +%endif +%endif +%endmacro + +; Macro to end a data segment + +%imacro enddataseg 1 +%endmacro + +; Macro to begin a code segment + +%imacro begcodeseg 1 +%ifdef __PIC__ +%ifdef __LINUX__ + extern _GLOBAL_OFFSET_TABLE_ +%else + extern __GLOBAL_OFFSET_TABLE_ +%endif +%endif +%ifdef __GNUC__ +segment .text public class=CODE use32 flat +%else +%ifdef flatmodel +segment _TEXT public align=16 class=CODE use32 flat +%else +segment %1_TEXT public align=16 class=CODE use16 +%endif +%endif +%endmacro + +; Macro to begin a near code segment + +%imacro begcodeseg_near 0 +%ifdef __GNUC__ +segment .text public class=CODE use32 flat +%else +%ifdef flatmodel +segment _TEXT public align=16 class=CODE use32 flat +%else +segment _TEXT public align=16 class=CODE use16 +%endif +%endif +%endmacro + +; Macro to end a code segment + +%imacro endcodeseg 1 +%endmacro + +; Macro to end a near code segment + +%imacro endcodeseg_near 0 +%endmacro + +; Macro for an extern C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +%imacro cextern 2 +%ifdef __NOU_VAR__ +extern %1 +%else +extern _%1 +%define %1 _%1 +%endif +%endmacro + +%imacro cexternfunc 2 +%ifdef __NOU__ +extern %1 +%else +extern _%1 +%define %1 _%1 +%endif +%endmacro + +; Macro for a public C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +%imacro cpublic 1 +%ifdef __NOU_VAR__ +global %1 +%1: +%else +global _%1 +_%1: +%define %1 _%1 +%endif +%endmacro + +; Macro for an global C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +%imacro cglobal 1 +%ifdef __NOU_VAR__ +global %1 +%else +global _%1 +%define %1 _%1 +%endif +%endmacro + +; Macro for an global C function symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +%imacro cglobalfunc 1 +%ifdef __PIC__ +global %1:function +%else +%ifdef __NOU__ +global %1 +%else +global _%1 +%define %1 _%1 +%endif +%endif +%endmacro + +; Macro to start a C callable function. This will be a far function for +; 16-bit code, and a near function for 32-bit code. + +%imacro cprocstatic 1 +%push cproc +%1: +%ifdef flatmodel +%stacksize flat +%define ret retn +%else +%stacksize large +%define ret retf +%endif +%assign %$localsize 0 +%endmacro + +%imacro cprocstart 1 +%push cproc + cglobalfunc %1 +%1: +%ifdef flatmodel +%stacksize flat +%define ret retn +%else +%stacksize large +%define ret retf +%endif +%assign %$localsize 0 +%endmacro + +; This macro sets up a procedure to be exported from a 16 bit DLL. Since the +; calling conventions are always _far _pascal for 16 bit DLL's, we actually +; rename this routine with an extra underscore with 'C' calling conventions +; and a small DLL stub will be provided by the high level code to call the +; assembler routine. + +%imacro cprocstartdll16 1 +%ifdef __WINDOWS16__ +cprocstart _%1 +%else +cprocstart %1 +%endif +%endmacro + +; Macro to start a C callable near function. + +%imacro cprocnear 1 +%push cproc + cglobalfunc %1 +%1: +%define ret retn +%ifdef flatmodel +%stacksize flat +%else +%stacksize small +%endif +%assign %$localsize 0 +%endmacro + +; Macro to start a C callable far function. + +%imacro cprocfar 1 +%push cproc + cglobalfunc %1 +%1: +%define ret retf +%ifdef flatmodel +%stacksize flat +%else +%stacksize large +%endif +%assign %$localsize 0 +%endmacro + +; Macro to end a C function + +%imacro cprocend 0 +%pop +%endmacro + +; Macros for entering and exiting C callable functions. Note that we must +; always save and restore the SI and DI registers for C functions, and for +; 32 bit C functions we also need to save and restore EBX and clear the +; direction flag. + +%imacro enter_c 0 + push _bp + mov _bp,_sp +%ifnidn %$localsize,0 + sub _sp,%$localsize +%endif +%ifdef flatmodel + push ebx +%endif + push _si + push _di +%endmacro + +%imacro leave_c 0 + pop _di + pop _si +%ifdef flatmodel + pop ebx + cld +%endif +%ifnidn %$localsize,0 + mov _sp,_bp +%endif + pop _bp +%endmacro + +%imacro use_ebx 0 +%ifdef flatmodel + push ebx +%endif +%endmacro + +%imacro unuse_ebx 0 +%ifdef flatmodel + pop ebx +%endif +%endmacro + +; Macros for saving and restoring the value of DS,ES,FS,GS when it is to +; be used in assembly routines. This evaluates to nothing in the flat memory +; model, but is saves and restores DS in the large memory model. + +%imacro use_ds 0 +%ifndef flatmodel + push ds +%endif +%endmacro + +%imacro unuse_ds 0 +%ifndef flatmodel + pop ds +%endif +%endmacro + +%imacro use_es 0 +%ifndef flatmodel + push es +%endif +%endmacro + +%imacro unuse_es 0 +%ifndef flatmodel + pop es +%endif +%endmacro + +; Macros for loading the address of a data pointer into a segment and +; index register pair. The %imacro explicitly loads DS or ES in the 16 bit +; memory model, or it simply loads the offset into the register in the flat +; memory model since DS and ES always point to all addressable memory. You +; must use the correct _REG (ie: _BX) %imacros for documentation purposes. + +%imacro _lds 2 +%ifdef flatmodel + mov %1,%2 +%else + lds %1,%2 +%endif +%endmacro + +%imacro _les 2 +%ifdef flatmodel + mov %1,%2 +%else + les %1,%2 +%endif +%endmacro + +; Macros for adding and subtracting a value from registers. Two value are +; provided, one for 16 bit modes and another for 32 bit modes (the extended +; register is used in 32 bit modes). + +%imacro _add 3 +%ifdef flatmodel + add e%1, %3 +%else + add %1, %2 +%endif +%endmacro + +%imacro _sub 3 +%ifdef flatmodel + sub e%1, %3 +%else + sub %1, %2 +%endif +%endmacro + +; Macro to clear the high order word for the 32 bit extended registers. +; This is used to convert an unsigned 16 bit value to an unsigned 32 bit +; value, and will evaluate to nothing in 16 bit modes. + +%imacro clrhi 1 +%ifdef flatmodel + movzx e%1,%1 +%endif +%endmacro + +%imacro sgnhi 1 +%ifdef flatmodel + movsx e%1,%1 +%endif +%endmacro + +; Macro to load an extended register with an integer value in either mode + +%imacro loadint 2 +%ifdef flatmodel + mov e%1,%2 +%else + xor e%1,e%1 + mov %1,%2 +%endif +%endmacro + +; Macros to load and store integer values with string instructions + +%imacro LODSINT 0 +%ifdef flatmodel + lodsd +%else + lodsw +%endif +%endmacro + +%imacro STOSINT 0 +%ifdef flatmodel + stosd +%else + stosw +%endif +%endmacro + +; Macros to provide resb, resw, resd compatibility with NASM + +%imacro dclb 1 +times %1 db 0 +%endmacro + +%imacro dclw 1 +times %1 dw 0 +%endmacro + +%imacro dcld 1 +times %1 dd 0 +%endmacro + +; Macro to get the addres of the GOT for Linux/FreeBSD shared +; libraries into the EBX register. + +%imacro get_GOT 1 + call %%getgot +%%getgot: pop %1 + add %1,_GLOBAL_OFFSET_TABLE_+$$-%%getgot wrt ..gotpc +%endmacro + +; Macro to get the address of a *local* variable that is global to +; a single module in a manner that will work correctly when compiled +; into a Linux shared library. Note that this will *not* work for +; variables that are defined as global to all modules. For that +; use the LEA_G macro + +%macro LEA_L 2 +%ifdef __PIC__ + get_GOT %1 + lea %1,[%1+%2 wrt ..gotoff] +%else + lea %1,[%2] +%endif +%endmacro + +; Same macro as above but for global variables public to *all* +; modules. + +%macro LEA_G 2 +%ifdef __PIC__ + get_GOT %1 + mov %1,[%1+%2 wrt ..got] +%else + lea %1,[%2] +%endif +%endmacro + +; macros to declare assembler function stubs for function structures + +%imacro BEGIN_STUBS_DEF 2 +begdataseg _STUBS +%ifdef __NOU_VAR__ +extern %1 +%define STUBS_START %1 +%else +extern _%1 +%define STUBS_START _%1 +%endif +enddataseg _STUBS +begcodeseg _STUBS +%assign off %2 +%endmacro + +%imacro DECLARE_STUB 1 +%ifdef __PIC__ + global %1:function +%1: + get_GOT eax + mov eax,[eax+STUBS_START wrt ..got] + jmp [eax+off] +%else +%ifdef __NOU__ + global %1 +%1: +%else + global _%1 +_%1: +%endif + jmp [DWORD STUBS_START+off] +%endif +%assign off off+4 +%endmacro + +%imacro SKIP_STUB 1 +%assign off off+4 +%endmacro + +%imacro DECLARE_STDCALL 2 +%ifdef STDCALL_MANGLE + global _%1@%2 +_%1@%2: +%else +%ifdef STDCALL_USCORE + global _%1 +_%1: +%else + global %1 +%1: +%endif +%endif + jmp [DWORD STUBS_START+off] +%assign off off+4 +%endmacro + +%imacro END_STUBS_DEF 0 +endcodeseg _STUBS +%endmacro + +; macros to declare assembler import stubs for binary loadable drivers + +%imacro BEGIN_IMPORTS_DEF 1 +BEGIN_STUBS_DEF %1,4 +%endmacro + +%imacro DECLARE_IMP 2 +DECLARE_STUB %1 +%endmacro + +%imacro SKIP_IMP 2 +SKIP_STUB %1 +%endmacro + +%imacro SKIP_IMP2 1 +DECLARE_STUB %1 +%endmacro + +%imacro SKIP_IMP3 1 +SKIP_STUB %1 +%endmacro + +%imacro END_IMPORTS_DEF 0 +END_STUBS_DEF +%endmacro + +else ; __NASM_MAJOR__ + +;============================================================================ +; Macro package when compiling with TASM. +;============================================================================ + +; Turn off underscores for globals if disabled for all externals + +ifdef __NOU__ +__NOU_VAR__ = 1 +endif + +; Define the __WINDOWS__ symbol if we are compiling for any Windows +; environment + +ifdef __WINDOWS16__ +__WINDOWS__ = 1 +endif +ifdef __WINDOWS32__ +__WINDOWS__ = 1 +__WINDOWS32_386__ = 1 +endif +ifdef __WIN386__ +__WINDOWS__ = 1 +__WINDOWS32_386__ = 1 +endif +ifdef __VXD__ +__WINDOWS__ = 1 +__WINDOWS32_386__ = 1 + MASM + .386 + NO_SEGMENTS = 1 + include vmm.inc ; IGNORE DEPEND + include vsegment.inc ; IGNORE DEPEND + IDEAL +endif + +; Macros for accessing 'generic' registers + +ifdef __FLAT__ + _ax EQU eax ; EAX is used for accumulator + _bx EQU ebx ; EBX is used for accumulator + _cx EQU ecx ; ECX is used for looping + _dx EQU edx ; EDX is used for data register + _si EQU esi ; ESI is the source index register + _di EQU edi ; EDI is the destination index register + _bp EQU ebp ; EBP is used for base pointer register + _sp EQU esp ; ESP is used for stack pointer register + _es EQU ; ES and DS are the same in 32 bit PM + typedef UCHAR BYTE ; Size of a character + typedef USHORT WORD ; Size of a short + typedef UINT DWORD ; Size of an integer + typedef ULONG DWORD ; Size of a long + typedef BOOL DWORD ; Size of a boolean + typedef DPTR DWORD ; Size of a data pointer + typedef FDPTR FWORD ; Size of a far data pointer + typedef NDPTR DWORD ; Size of a near data pointer + typedef CPTR DWORD ; Size of a code pointer + typedef FCPTR FWORD ; Size of a far code pointer + typedef NCPTR DWORD ; Size of a near code pointer + typedef DUINT DWORD ; Declare a integer variable + FPTR EQU NEAR ; Distance for function pointers + intsize = 4 ; Size of an integer + flatmodel = 1 ; This is a flat memory model + P386 ; Turn on 386 code generation + MODEL FLAT ; Set up for 32 bit simplified FLAT model +else + _ax EQU ax ; AX is used for accumulator + _bx EQU bx ; BX is used for accumulator + _cx EQU cx ; CX is used for looping + _dx EQU dx ; DX is used for data register + _si EQU si ; SI is the source index register + _di EQU di ; DI is the destination index register + _bp EQU bp ; BP is used for base pointer register + _sp EQU sp ; SP is used for stack pointer register + _es EQU es: ; ES is used for segment override + typedef UCHAR BYTE ; Size of a character + typedef USHORT WORD ; Size of a short + typedef UINT WORD ; Size of an integer + typedef ULONG DWORD ; Size of a long + typedef BOOL WORD ; Size of a boolean + typedef DPTR DWORD ; Size of a data pointer + typedef FDPTR DWORD ; Size of a far data pointer + typedef NDPTR WORD ; Size of a near data pointer + typedef CPTR DWORD ; Size of a code pointer + typedef FCPTR DWORD ; Size of a far code pointer + typedef NCPTR WORD ; Size of a near code pointer + typedef DUINT WORD ; Declare a integer variable + FPTR EQU FAR ; Distance for function pointers + intsize = 2 ; Size of an integer + P386 ; Turn on 386 code generation +endif + invert EQU not + +; Provide a typedef for real floating point numbers + +ifdef DOUBLE +typedef REAL QWORD +typedef DREAL QWORD +else +typedef REAL DWORD +typedef DREAL DWORD +endif + +; Macros to access the floating point stack registers to convert them +; from NASM style to TASM style + +st0 EQU st(0) +st1 EQU st(1) +st2 EQU st(2) +st3 EQU st(3) +st4 EQU st(4) +st5 EQU st(5) +st6 EQU st(6) +st7 EQU st(7) +st8 EQU st(8) + +; Boolean truth values (same as those in debug.h) + +ifndef __VXD__ +False = 0 +True = 1 +No = 0 +Yes = 1 +Yes = 1 +endif + +; Macros for the _DATA data segment. This segment contains initialised data. + +MACRO begdataseg name +ifdef __VXD__ + MASM +VXD_LOCKED_DATA_SEG + IDEAL +else +ifdef flatmodel + DATASEG +else +SEGMENT _DATA DWORD PUBLIC USE16 'DATA' +endif +endif +ENDM + +MACRO enddataseg name +ifdef __VXD__ + MASM +VXD_LOCKED_DATA_ENDS + IDEAL +else +ifndef flatmodel +ENDS _DATA +endif +endif +ENDM + +; Macro for the main code segment. + +MACRO begcodeseg name +ifdef __VXD__ + MASM +VXD_LOCKED_CODE_SEG + IDEAL +else +ifdef flatmodel + CODESEG + ASSUME CS:FLAT,DS:FLAT,SS:FLAT +else +SEGMENT &name&_TEXT PARA PUBLIC USE16 'CODE' + ASSUME CS:&name&_TEXT,DS:_DATA +endif +endif +ENDM + +; Macro for a near code segment + +MACRO begcodeseg_near +ifdef flatmodel + CODESEG + ASSUME CS:FLAT,DS:FLAT,SS:FLAT +else +SEGMENT _TEXT PARA PUBLIC USE16 'CODE' + ASSUME CS:_TEXT,DS:_DATA +endif +ENDM + +MACRO endcodeseg name +ifdef __VXD__ + MASM +VXD_LOCKED_CODE_ENDS + IDEAL +else +ifndef flatmodel +ENDS &name&_TEXT +endif +endif +ENDM + +MACRO endcodeseg_near +ifndef flatmodel +ENDS _TEXT +endif +ENDM + +; Macro to be invoked at the start of all modules to set up segments for +; later use. + +MACRO header name +begdataseg name +enddataseg name +ENDM + +; Macro for an extern C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +MACRO cextern name,size +ifdef __NOU_VAR__ + EXTRN name:size +else + EXTRN _&name&:size +name EQU _&name& +endif +ENDM + +MACRO cexternfunc name,size +ifdef __NOU__ + EXTRN name:size +else + EXTRN _&name&:size +name EQU _&name& +endif +ENDM + +MACRO stdexternfunc name,num_args,size +ifdef STDCALL_MANGLE + EXTRN _&name&@&num_args&:size +name EQU _&name&@&num_args +else + EXTRN name:size +endif +ENDM + +; Macro for a public C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +MACRO cpublic name +ifdef __NOU_VAR__ +name: + PUBLIC name +else +_&name&: + PUBLIC _&name& +name EQU _&name& +endif +ENDM + +; Macro for an global C symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +MACRO cglobal name +ifdef __NOU_VAR__ + PUBLIC name +else + PUBLIC _&name& +name EQU _&name& +endif +ENDM + +; Macro for an global C function symbol. If the C compiler requires leading +; underscores, then the underscores are added to the symbol names, otherwise +; they are left off. The symbol name is referenced in the assembler code +; using the non-underscored symbol name. + +MACRO cglobalfunc name +ifdef __NOU__ + PUBLIC name +else + PUBLIC _&name& +name EQU _&name& +endif +ENDM + +; Macro to start a C callable function. This will be a far function for +; 16-bit code, and a near function for 32-bit code. + +MACRO cprocstatic name ; Set up model independant private proc +ifdef flatmodel +PROC name NEAR +else +PROC name FAR +endif +LocalSize = 0 +ENDM + +MACRO cprocstart name ; Set up model independant proc +ifdef flatmodel +ifdef __NOU__ +PROC name NEAR +else +PROC _&name& NEAR +endif +else +ifdef __NOU__ +PROC name FAR +else +PROC _&name& FAR +endif +endif +LocalSize = 0 + cglobalfunc name +ENDM + +MACRO cprocnear name ; Set up near proc +ifdef __NOU__ +PROC name NEAR +else +PROC _&name& NEAR +endif +LocalSize = 0 + cglobalfunc name +ENDM + +MACRO cprocfar name ; Set up far proc +ifdef __NOU__ +PROC name FAR +else +PROC _&name& FAR +endif +LocalSize = 0 + cglobalfunc name +ENDM + +MACRO cprocend ; End procedure macro +ENDP +ENDM + +; This macro sets up a procedure to be exported from a 16 bit DLL. Since the +; calling conventions are always _far _pascal for 16 bit DLL's, we actually +; rename this routine with an extra underscore with 'C' calling conventions +; and a small DLL stub will be provided by the high level code to call the +; assembler routine. + +MACRO cprocstartdll16 name +ifdef __WINDOWS16__ +cprocstart _&name& +else +cprocstart name +endif +ENDM + +; Macros for entering and exiting C callable functions. Note that we must +; always save and restore the SI and DI registers for C functions, and for +; 32 bit C functions we also need to save and restore EBX and clear the +; direction flag. + +MACRO save_c_regs +ifdef flatmodel + push ebx +endif + push _si + push _di +ENDM + +MACRO enter_c + push _bp + mov _bp,_sp + IFDIFI ,<0> + sub _sp,LocalSize + ENDIF + save_c_regs +ENDM + +MACRO restore_c_regs + pop _di + pop _si +ifdef flatmodel + pop ebx +endif +ENDM + +MACRO leave_c + restore_c_regs + cld + IFDIFI ,<0> + mov _sp,_bp + ENDIF + pop _bp +ENDM + +MACRO use_ebx +ifdef flatmodel + push ebx +endif +ENDM + +MACRO unuse_ebx +ifdef flatmodel + pop ebx +endif +ENDM + +; Macros for saving and restoring the value of DS,ES,FS,GS when it is to +; be used in assembly routines. This evaluates to nothing in the flat memory +; model, but is saves and restores DS in the large memory model. + +MACRO use_ds +ifndef flatmodel + push ds +endif +ENDM + +MACRO unuse_ds +ifndef flatmodel + pop ds +endif +ENDM + +MACRO use_es +ifndef flatmodel + push es +endif +ENDM + +MACRO unuse_es +ifndef flatmodel + pop es +endif +ENDM + +; Macros for loading the address of a data pointer into a segment and +; index register pair. The macro explicitly loads DS or ES in the 16 bit +; memory model, or it simply loads the offset into the register in the flat +; memory model since DS and ES always point to all addressable memory. You +; must use the correct _REG (ie: _BX) macros for documentation purposes. + +MACRO _lds reg, addr +ifdef flatmodel + mov reg,addr +else + lds reg,addr +endif +ENDM + +MACRO _les reg, addr +ifdef flatmodel + mov reg,addr +else + les reg,addr +endif +ENDM + +; Macros for adding and subtracting a value from registers. Two value are +; provided, one for 16 bit modes and another for 32 bit modes (the extended +; register is used in 32 bit modes). + +MACRO _add reg, val16, val32 +ifdef flatmodel + add e®&, val32 +else + add reg, val16 +endif +ENDM + +MACRO _sub reg, val16, val32 +ifdef flatmodel + sub e®&, val32 +else + sub reg, val16 +endif +ENDM + +; Macro to clear the high order word for the 32 bit extended registers. +; This is used to convert an unsigned 16 bit value to an unsigned 32 bit +; value, and will evaluate to nothing in 16 bit modes. + +MACRO clrhi reg +ifdef flatmodel + movzx e®&,reg +endif +ENDM + +MACRO sgnhi reg +ifdef flatmodel + movsx e®&,reg +endif +ENDM + +; Macro to load an extended register with an integer value in either mode + +MACRO loadint reg,val +ifdef flatmodel + mov e®&,val +else + xor e®&,e®& + mov reg,val +endif +ENDM + +; Macros to load and store integer values with string instructions + +MACRO LODSINT +ifdef flatmodel + lodsd +else + lodsw +endif +ENDM + +MACRO STOSINT +ifdef flatmodel + stosd +else + stosw +endif +ENDM + +; Macros to provide resb, resw, resd compatibility with NASM + +MACRO dclb count +db count dup (0) +ENDM + +MACRO dclw count +dw count dup (0) +ENDM + +MACRO dcld count +dd count dup (0) +ENDM + +; Macros to provide resb, resw, resd compatibility with NASM + +MACRO resb count +db count dup (?) +ENDM + +MACRO resw count +dw count dup (?) +ENDM + +MACRO resd count +dd count dup (?) +ENDM + +; Macros to declare assembler stubs for function structures + +MACRO BEGIN_STUBS_DEF name, firstOffset +begdataseg _STUBS +ifdef __NOU_VAR__ + EXTRN name:DWORD +STUBS_START = name +else + EXTRN _&name&:DWORD +name EQU _&name& +STUBS_START = _&name +endif +enddataseg _STUBS +begcodeseg _STUBS +off = firstOffset +ENDM + +MACRO DECLARE_STUB name +ifdef __NOU__ +name: + PUBLIC name +else +_&name: + PUBLIC _&name +endif + jmp [DWORD STUBS_START+off] +off = off + 4 +ENDM + +MACRO SKIP_STUB name +off = off + 4 +ENDM + +MACRO DECLARE_STDCALL name,num_args +ifdef STDCALL_MANGLE +_&name&@&num_args&: + PUBLIC _&name&@&num_args& +else +name: + PUBLIC name +endif + jmp [DWORD STUBS_START+off] +off = off + 4 +ENDM + +MACRO END_STUBS_DEF +endcodeseg _STUBS +ENDM + +MACRO BEGIN_IMPORTS_DEF name +BEGIN_STUBS_DEF name,4 +ENDM + +ifndef LOCAL_DECLARE_IMP +MACRO DECLARE_IMP name, numArgs +DECLARE_STUB name +ENDM + +MACRO SKIP_IMP name +SKIP_STUB name +ENDM + +MACRO SKIP_IMP2 name, numArgs +DECLARE_STUB name +ENDM + +MACRO SKIP_IMP3 name +SKIP_STUB name +ENDM +endif + +MACRO END_IMPORTS_DEF +END_STUBS_DEF +ENDM + +MACRO LEA_L reg,name + lea reg,[name] +ENDM + +MACRO LEA_G reg,name + lea reg,[name] +ENDM + +endif + diff --git a/board/MAI/bios_emulator/scitech/include/x86emu.h b/board/MAI/bios_emulator/scitech/include/x86emu.h new file mode 100644 index 000000000..1d87d4e57 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/x86emu.h @@ -0,0 +1,194 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for public specific functions. +* Any application linking against us should only +* include this header +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMU_H +#define __X86EMU_X86EMU_H + +#ifdef SCITECH +#include "scitech.h" +#define X86API _ASMAPI +#define X86APIP _ASMAPIP +typedef int X86EMU_pioAddr; +#else +#include "x86emu/types.h" +#define X86API +#define X86APIP * +#endif +#include "x86emu/regs.h" + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/**************************************************************************** +REMARKS: +Data structure containing ponters to programmed I/O functions used by the +emulator. This is used so that the user program can hook all programmed +I/O for the emulator to handled as necessary by the user program. By +default the emulator contains simple functions that do not do access the +hardware in any way. To allow the emualtor access the hardware, you will +need to override the programmed I/O functions using the X86EMU_setupPioFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +inb - Function to read a byte from an I/O port +inw - Function to read a word from an I/O port +inl - Function to read a dword from an I/O port +outb - Function to write a byte to an I/O port +outw - Function to write a word to an I/O port +outl - Function to write a dword to an I/O port +****************************************************************************/ +typedef struct { + u8 (X86APIP inb)(X86EMU_pioAddr addr); + u16 (X86APIP inw)(X86EMU_pioAddr addr); + u32 (X86APIP inl)(X86EMU_pioAddr addr); + void (X86APIP outb)(X86EMU_pioAddr addr, u8 val); + void (X86APIP outw)(X86EMU_pioAddr addr, u16 val); + void (X86APIP outl)(X86EMU_pioAddr addr, u32 val); + } X86EMU_pioFuncs; + +/**************************************************************************** +REMARKS: +Data structure containing ponters to memory access functions used by the +emulator. This is used so that the user program can hook all memory +access functions as necessary for the emulator. By default the emulator +contains simple functions that only access the internal memory of the +emulator. If you need specialised functions to handle access to different +types of memory (ie: hardware framebuffer accesses and BIOS memory access +etc), you will need to override this using the X86EMU_setupMemFuncs +function. + +HEADER: +x86emu.h + +MEMBERS: +rdb - Function to read a byte from an address +rdw - Function to read a word from an address +rdl - Function to read a dword from an address +wrb - Function to write a byte to an address +wrw - Function to write a word to an address +wrl - Function to write a dword to an address +****************************************************************************/ +typedef struct { + u8 (X86APIP rdb)(u32 addr); + u16 (X86APIP rdw)(u32 addr); + u32 (X86APIP rdl)(u32 addr); + void (X86APIP wrb)(u32 addr, u8 val); + void (X86APIP wrw)(u32 addr, u16 val); + void (X86APIP wrl)(u32 addr, u32 val); + } X86EMU_memFuncs; + +/**************************************************************************** + Here are the default memory read and write + function in case they are needed as fallbacks. +***************************************************************************/ +extern u8 X86API rdb(u32 addr); +extern u16 X86API rdw(u32 addr); +extern u32 X86API rdl(u32 addr); +extern void X86API wrb(u32 addr, u8 val); +extern void X86API wrw(u32 addr, u16 val); +extern void X86API wrl(u32 addr, u32 val); + +#pragma pack() + +/*--------------------- type definitions -----------------------------------*/ + +typedef void (X86APIP X86EMU_intrFuncs)(int num); +extern X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); +void X86EMU_setupPioFuncs(X86EMU_pioFuncs *funcs); +void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]); +void X86EMU_prepareForInt(int num); + +/* decode.c */ + +void X86EMU_exec(void); +void X86EMU_halt_sys(void); + +#ifdef DEBUG +#define HALT_SYS() \ + printk("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \ + X86EMU_halt_sys() +#else +#define HALT_SYS() X86EMU_halt_sys() +#endif + +/* Debug options */ + +#define DEBUG_DECODE_F 0x0001 /* print decoded instruction */ +#define DEBUG_TRACE_F 0x0002 /* dump regs before/after execution */ +#define DEBUG_STEP_F 0x0004 +#define DEBUG_DISASSEMBLE_F 0x0008 +#define DEBUG_BREAK_F 0x0010 +#define DEBUG_SVC_F 0x0020 +#define DEBUG_SAVE_CS_IP 0x0040 +#define DEBUG_FS_F 0x0080 +#define DEBUG_PROC_F 0x0100 +#define DEBUG_SYSINT_F 0x0200 /* bios system interrupts. */ +#define DEBUG_TRACECALL_F 0x0400 +#define DEBUG_INSTRUMENT_F 0x0800 +#define DEBUG_MEM_TRACE_F 0x1000 +#define DEBUG_IO_TRACE_F 0x2000 +#define DEBUG_TRACECALL_REGS_F 0x4000 +#define DEBUG_DECODE_NOPRINT_F 0x8000 +#define DEBUG_EXIT 0x10000 +#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) + +void X86EMU_trace_regs(void); +void X86EMU_trace_xregs(void); +void X86EMU_dump_memory(u16 seg, u16 off, u32 amt); +int X86EMU_trace_on(void); +int X86EMU_trace_off(void); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMU_H */ diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h b/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h new file mode 100644 index 000000000..777b03cd7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/x86emu/fpu_regs.h @@ -0,0 +1,115 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_REGS_H +#define __X86EMU_FPU_REGS_H + +#ifdef X86_FPU_SUPPORT + +#pragma pack(1) + +/* Basic 8087 register can hold any of the following values: */ + +union x86_fpu_reg_u { + s8 tenbytes[10]; + double dval; + float fval; + s16 sval; + s32 lval; + }; + +struct x86_fpu_reg { + union x86_fpu_reg_u reg; + char tag; + }; + +/* + * Since we are not going to worry about the problems of aliasing + * registers, every time a register is modified, its result type is + * set in the tag fields for that register. If some operation + * attempts to access the type in a way inconsistent with its current + * storage format, then we flag the operation. If common, we'll + * attempt the conversion. + */ + +#define X86_FPU_VALID 0x80 +#define X86_FPU_REGTYP(r) ((r) & 0x7F) + +#define X86_FPU_WORD 0x0 +#define X86_FPU_SHORT 0x1 +#define X86_FPU_LONG 0x2 +#define X86_FPU_FLOAT 0x3 +#define X86_FPU_DOUBLE 0x4 +#define X86_FPU_LDBL 0x5 +#define X86_FPU_BSD 0x6 + +#define X86_FPU_STKTOP 0 + +struct x86_fpu_registers { + struct x86_fpu_reg x86_fpu_stack[8]; + int x86_fpu_flags; + int x86_fpu_config; /* rounding modes, etc. */ + short x86_fpu_tos, x86_fpu_bos; + }; + +#pragma pack() + +/* + * There are two versions of the following macro. + * + * One version is for opcode D9, for which there are more than 32 + * instructions encoded in the second byte of the opcode. + * + * The other version, deals with all the other 7 i87 opcodes, for + * which there are only 32 strings needed to describe the + * instructions. + */ + +#endif /* X86_FPU_SUPPORT */ + +#ifdef DEBUG +# define DECODE_PRINTINSTR32(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<3)+(rh)]); +# define DECODE_PRINTINSTR256(t,mod,rh,rl) \ + DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]); +#else +# define DECODE_PRINTINSTR32(t,mod,rh,rl) +# define DECODE_PRINTINSTR256(t,mod,rh,rl) +#endif + +#endif /* __X86EMU_FPU_REGS_H */ diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/regs.h b/board/MAI/bios_emulator/scitech/include/x86emu/regs.h new file mode 100644 index 000000000..a12017b00 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/x86emu/regs.h @@ -0,0 +1,331 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 register definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_REGS_H +#define __X86EMU_REGS_H + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/* + * General EAX, EBX, ECX, EDX type registers. Note that for + * portability, and speed, the issue of byte swapping is not addressed + * in the registers. All registers are stored in the default format + * available on the host machine. The only critical issue is that the + * registers should line up EXACTLY in the same manner as they do in + * the 386. That is: + * + * EAX & 0xff === AL + * EAX & 0xffff == AX + * + * etc. The result is that alot of the calculations can then be + * done using the native instruction set fully. + */ + +#ifdef __BIG_ENDIAN__ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 filler0, x_reg; + } I16_reg_t; + +typedef struct { + u8 filler0, filler1, h_reg, l_reg; + } I8_reg_t; + +#else /* !__BIG_ENDIAN__ */ + +typedef struct { + u32 e_reg; + } I32_reg_t; + +typedef struct { + u16 x_reg; + } I16_reg_t; + +typedef struct { + u8 l_reg, h_reg; + } I8_reg_t; + +#endif /* BIG_ENDIAN */ + +typedef union { + I32_reg_t I32_reg; + I16_reg_t I16_reg; + I8_reg_t I8_reg; + } i386_general_register; + +struct i386_general_regs { + i386_general_register A, B, C, D; + }; + +typedef struct i386_general_regs Gen_reg_t; + +struct i386_special_regs { + i386_general_register SP, BP, SI, DI, IP; + u32 FLAGS; + }; + +/* + * Segment registers here represent the 16 bit quantities + * CS, DS, ES, SS. + */ + +struct i386_segment_regs { + u16 CS, DS, SS, ES, FS, GS; + }; + +/* 8 bit registers */ +#define R_AH gen.A.I8_reg.h_reg +#define R_AL gen.A.I8_reg.l_reg +#define R_BH gen.B.I8_reg.h_reg +#define R_BL gen.B.I8_reg.l_reg +#define R_CH gen.C.I8_reg.h_reg +#define R_CL gen.C.I8_reg.l_reg +#define R_DH gen.D.I8_reg.h_reg +#define R_DL gen.D.I8_reg.l_reg + +/* 16 bit registers */ +#define R_AX gen.A.I16_reg.x_reg +#define R_BX gen.B.I16_reg.x_reg +#define R_CX gen.C.I16_reg.x_reg +#define R_DX gen.D.I16_reg.x_reg + +/* 32 bit extended registers */ +#define R_EAX gen.A.I32_reg.e_reg +#define R_EBX gen.B.I32_reg.e_reg +#define R_ECX gen.C.I32_reg.e_reg +#define R_EDX gen.D.I32_reg.e_reg + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_SP spc.SP.I16_reg.x_reg +#define R_BP spc.BP.I16_reg.x_reg +#define R_SI spc.SI.I16_reg.x_reg +#define R_DI spc.DI.I16_reg.x_reg +#define R_IP spc.IP.I16_reg.x_reg +#define R_FLG spc.FLAGS + +/* special registers */ +#define R_ESP spc.SP.I32_reg.e_reg +#define R_EBP spc.BP.I32_reg.e_reg +#define R_ESI spc.SI.I32_reg.e_reg +#define R_EDI spc.DI.I32_reg.e_reg +#define R_EIP spc.IP.I32_reg.e_reg +#define R_EFLG spc.FLAGS + +/* segment registers */ +#define R_CS seg.CS +#define R_DS seg.DS +#define R_SS seg.SS +#define R_ES seg.ES +#define R_FS seg.FS +#define R_GS seg.GS + +/* flag conditions */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */ + +/* 80286 and above always have bit#1 set */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */ + +/* + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) + */ +#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) + +/* following bits masked in to a 16bit quantity */ + +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */ + +#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) + +#define CONDITIONAL_SET_FLAG(COND,FLAG) \ + if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) + +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ + +#define F_ALL_CALC 0xff0000 /* All have been calced */ + +/* + * Emulator machine state. + * Segment usage control. + */ +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 + +typedef struct { + struct i386_general_regs gen; + struct i386_special_regs spc; + struct i386_segment_regs seg; + /* + * MODE contains information on: + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits + */ + long mode; + u8 intno; + volatile int intr; /* mask of pending interrupts */ + int debug; +#ifdef DEBUG + int check; + u16 saved_ip; + u16 saved_cs; + int enc_pos; + int enc_str_pos; + char decode_buf[32]; /* encoded byte stream */ + char decoded_buf[256]; /* disassembled strings */ +#endif + } X86EMU_regs; + +/**************************************************************************** +REMARKS: +Structure maintaining the emulator machine state. + +MEMBERS: +x86 - X86 registers +mem_base - Base real mode memory for the emulator +mem_size - Size of the real mode memory block for the emulator +****************************************************************************/ +typedef struct { + X86EMU_regs x86; + unsigned long mem_base; + unsigned long mem_size; + void* private; + } X86EMU_sysEnv; + +#pragma pack() + +/*----------------------------- Global Variables --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* Global emulator machine state. + * + * We keep it global to avoid pointer dereferences in the code for speed. + */ + +extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env + +/*-------------------------- Function Prototypes --------------------------*/ + +/* Function to log information at runtime */ + +/*void printk(const char *fmt, ...); */ + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_REGS_H */ diff --git a/board/MAI/bios_emulator/scitech/include/x86emu/types.h b/board/MAI/bios_emulator/scitech/include/x86emu/types.h new file mode 100644 index 000000000..0a17c547e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/include/x86emu/types.h @@ -0,0 +1,70 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for x86 emulator type definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_TYPES_H +#define __X86EMU_TYPES_H + +#include + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Currently only for Linux/32bit */ +#if defined(__GNUC__) && !defined(NO_LONG_LONG) +#define __HAS_LONG_LONG__ +#endif + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; +#ifdef __HAS_LONG_LONG__ +typedef unsigned long long u64; +#endif + +typedef char s8; +typedef short s16; +typedef long s32; +#ifdef __HAS_LONG_LONG__ +typedef long long s64; +#endif + +/*typedef unsigned int uint;*/ +typedef int sint; + +typedef u16 X86EMU_pioAddr; + +#endif /* __X86EMU_TYPES_H */ diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt new file mode 100644 index 000000000..0d87effa9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc.so/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt new file mode 100644 index 000000000..0d87effa9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/glibc/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt new file mode 100644 index 000000000..0d87effa9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc.so/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt new file mode 100644 index 000000000..0d87effa9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/debug/linux/gcc/libc/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc.so/readme.txt new file mode 100644 index 000000000..0d87effa9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc.so/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt new file mode 100644 index 000000000..0d87effa9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/glibc/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc.so/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc.so/readme.txt new file mode 100644 index 000000000..0d87effa9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc.so/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt new file mode 100644 index 000000000..0d87effa9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/lib/release/linux/gcc/libc/readme.txt @@ -0,0 +1 @@ +This file is just to ensure that the directory is created. diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc16.mk b/board/MAI/bios_emulator/scitech/makedefs/bc16.mk new file mode 100644 index 000000000..aa4fe76a4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/bc16.mk @@ -0,0 +1,137 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Borland C++ 4.x 16 bit version. Supports 16 bit DOS, +# DPMI16 DOS extender and 16 bit Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : USE_WIN16 USE_BC5 BC_LIBBASE USE_WIN95 + +# Default commands for compiling, assembling linking and archiving + CC := bcc + CFLAGS := -ml -H=bcc.sym -i60 -d -dc -4 -f287 +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx +.ELSE + AS := tasm +.ENDIF + ASFLAGS := /t /mx /m /iINCLUDE /iINCLUDE /i$(SCITECH)\INCLUDE + LD := bclink tlink.exe + LDFLAGS := -c + RC := brc + RCFLAGS := +.IF $(USE_BC5) +.IF $(USE_WIN95) + WIN_VERSION := -V4.0 +.ENDIF +.ENDIF + LIBR := tlib + LIBFLAGS := /C /P32 + ILIB := implib + ILIBFLAGS := -c + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -v + LDFLAGS += -v + ASFLAGS += /zi + LIBFLAGS += /P128 +.ELSE + LDFLAGS += -x + ASFLAGS += /q +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -O2 -k- +.ELIF $(OPT_SIZE) + CFLAGS += -O1 -k- +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -DFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + +# Optionally compile as Win16 +.IF $(USE_WIN16) +.IF $(BUILD_DLL) + CFLAGS += -WD -Fs- -DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += -W -Fs- +.ENDIF + DEF_LIBS := import.lib mathwl.lib cwl.lib + DX_ASFLAGS += -D__WINDOWS16__ + LIB_OS = WIN16 +.ELSE + USE_REALDOS := 1 + DEF_LIBS := mathl.lib fp87.lib cl.lib + LIB_OS = DOS16 +.END + +# Place to look for PMODE library files + +.IF $(USE_DPMI16) +PMLIB := dpmi16\pm.lib +.ELSE +PMLIB := pm.lib +.END + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := bc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc3.mk b/board/MAI/bios_emulator/scitech/makedefs/bc3.mk new file mode 100644 index 000000000..133d80edf --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/bc3.mk @@ -0,0 +1,102 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Borland C++ 3.1 version. Supports 16 bit DOS development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Default commands for compiling, assembling linking and archiving + CC := bcc + CFLAGS := -ml -H=bcc.sym -i60 -d +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx +.ELSE + AS := tasm +.ENDIF + ASFLAGS := /t /mx /m /iINCLUDE /i$(SCITECH)\INCLUDE + LD := bclink tlink.exe + LDFLAGS := -c + LIB := tlib + LIBFLAGS := /C + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -v + LDFLAGS += -v + ASFLAGS += /zi + LIBFLAGS += /P128 +.ELSE + LDFLAGS += -x + ASFLAGS += /q +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -3 -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -3 -O1 +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -f287 -DFPU387 + ASFLAGS += -DFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + USE_REALDOS := 1 + +# Define the default libraries to link with + DEF_LIBS := mathl.lib cl.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)\dos16\bc3 + +# Define which file contains our rules + + RULES_MAK := bc3.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/bc32.mk b/board/MAI/bios_emulator/scitech/makedefs/bc32.mk new file mode 100644 index 000000000..246de1dfc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/bc32.mk @@ -0,0 +1,201 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Borland C++ 4.0 32 bit version. Supports Borland's DOS Power +# Pack DPMI32 DOS extender, Phar Lap's TNT DOS Extender and +# 32 bit Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : USE_SMX32 USE_TNT USE_WIN32 USE_BC5 USE_VXD BC_LIBBASE +.IMPORT .IGNORE : VTOOLSD + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := bcc32 +.IF $(USE_VXD) + CFLAGS := -4 -i60 -d -w-stu +.ELSE + CFLAGS := -4 -H=bcc32.sym -i60 -d -w-stu +.ENDIF +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -d__FLAT__ -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx +.ELSE + AS := tasm +.ENDIF + ASFLAGS := /t /mx /m /w-res /w-mcp /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := bclink tlink32.exe + LDFLAGS := -c + RC := brc32 +.IF $(USE_BC5) + WIN_VERSION := -V4.0 + RCFLAGS := -32 +.ELSE + RCFLAGS := -w32 +.ENDIF + LIB := tlib + LIBFLAGS := /C + ILIB := implib + ILIBFLAGS := -c + INTEL_X86 := 1 + NMSYM := $(SOFTICE_PATH)\nmsym.exe + NMSYMFLAGS := /TRANSLATE:source,package,always /PROMPT /SOURCE:$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\win32 + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -v + LDFLAGS += -v + LIBFLAGS += /P256 +.IF $(USE_NASM) + ASFLAGS += -F borland -g +.ELSE + ASFLAGS += /zi +.ENDIF +.ELSE + LDFLAGS += -x + LIBFLAGS += /P128 +.IF $(USE_NASM) + ASFLAGS += -F null +.ELSE + ASFLAGS += /q +.ENDIF +.END + +# Optionally disable nagging warnings if MAX_WARN is not on +.IF $(MAX_WARN) +.ELSE + CFLAGS += -w-aus -w-par -w-hid -w-pia +.ENDIF + +# Optionally turn on optimisations (-5 -O2 breaks BC++ 4.0-4.5 sometimes) +.IF $(OPT) + CFLAGS += -5 -O2 -k- +.ELIF $(OPT_SIZE) + CFLAGS += -5 -O1 -k- +.END + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +# Optionally use Phar Lap's TNT DOS Extender, otherwise use the DOS Power Pack +.IF $(USE_TNT) + CFLAGS += -D__MSDOS__ + DX_CFLAGS += -DTNT + DX_ASFLAGS += -dTNT + LIB_OS = DOS32 + DEF_LIBS := import32.lib cw32.lib dosx32.lib tntapi.lib +.ELIF $(USE_VXD) + LDFLAGS += -n -P- -x + CFLAGS += -RT- -x- -Oi -VC -I$(VTOOLSD)\INCLUDE -DIS_32 -DWANTVXDWRAPS -DVTOOLSD -DWIN40 -DWIN40_OR_LATER -DDEFSEG=1 -zC_LTEXT -zALCODE -zR_LDATA -zTLCODE + DEF_LIBS := $(VTOOLSD)\lib\cfbc440d.lib $(VTOOLSD)\lib\wr0bc440.lib $(VTOOLSD)\lib\wr1bc440.lib $(VTOOLSD)\lib\wr2bc440.lib $(VTOOLSD)\lib\wr3bc440.lib $(VTOOLSD)\lib\rtbc440d.lib + DX_ASFLAGS += -d__VXD__ -d__BORLANDC__=1 -I$(VTOOLSD)\INCLUDE -I$(VTOOLSD)\LIB\INCLUDE + LIB_OS = VXD +.ELIF $(USE_WIN32) +.IF $(WIN32_GUI) +.ELSE + CFLAGS += -D__CONSOLE__ +.ENDIF +.IF $(BUILD_DLL) + CFLAGS += -WD -DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -W -WM +.ENDIF +.IF $(USE_BC5) +.ELSE + CFLAGS += -D_WIN32 +.ENDIF + DEF_LIBS := import32.lib cw32mt.lib + DX_ASFLAGS += -d__WINDOWS32__ + LIB_OS = WIN32 +.ELIF $(USE_SMX32) + CFLAGS += -D__SMX32__ -DPME32 + DX_CFLAGS += + DX_ASFLAGS += -d__SMX32__ -dDPMI32 -dPME32 + USE_REALDOS := 1 + LIB_OS = SMX32 + DEF_LIBS := cw32mt.lib +.ELSE + USE_DPMI32 := 1 + CFLAGS += -D__MSDOS__ + DX_CFLAGS += -WX -DDPMI32 + DX_ASFLAGS += -dDPMI32 + USE_REALDOS := 1 + LIB_OS = DOS32 + DEF_LIBS := +.END + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Place to look for PMODE library files + +.IF $(USE_TNT) +PMLIB := $(LIB_BASE)\tnt\pm.lib +.ELIF $(USE_DPMI32) +PMLIB := $(LIB_BASE)\dpmi32\pm.lib +.ELSE +PMLIB := $(LIB_BASE)\pm.lib +.END + +# Define which file contains our rules + + RULES_MAK := bc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk b/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk new file mode 100644 index 000000000..23aeb7cde --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/bcos2.mk @@ -0,0 +1,137 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Borland C++ 2.0 32-bit OS/2 version. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : USE_OS2GUI BC_LIBBASE + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := bcc + CFLAGS := -w- -4 -H=bcc32.sym -i60 -d +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -d__FLAT__ -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE + AS := tasm + ASFLAGS := /t /mx /m /D__FLAT__ /D__OS2__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := bclink tlink.exe + LDFLAGS := -c + RC := brcc + RCFLAGS := + LIB := tlib + LIBFLAGS := /C /P32 + ILIB := implib + ILIBFLAGS := -c +.IF $(USE_OS2GUI) + CFLAGS += -D__OS2_PM__ +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -v + LDFLAGS += -v + LIBFLAGS += /P128 +.IF $(USE_NASM) + ASFLAGS += -F borland +.ELSE + ASFLAGS += /zi +.ENDIF +.ELSE + LDFLAGS += -x +.IF $(USE_NASM) + ASFLAGS += -F null +.ELSE + ASFLAGS += /q +.ENDIF +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -5 -O2 -k- +.ELIF $(OPT_SIZE) + CFLAGS += -5 -O1 -k- +.END + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +# Optionally use Phar Lap's TNT DOS Extender, otherwise use the DOS Power Pack +.IF $(BUILD_DLL) + CFLAGS += -sd -sm -DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -sm +.ENDIF + DEF_LIBS := os2.lib c2mt.lib + DX_ASFLAGS += -d__OS2__ + LIB_OS = os232 + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(BC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Place to look for PMODE library files + +.IF $(USE_OS2GUI) +DEF_LIBS += pm_pm.lib +.ELSE +DEF_LIBS += pm.lib +.ENDIF + +# Define which file contains our rules + + RULES_MAK := bcos2.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/cl16.mk b/board/MAI/bios_emulator/scitech/makedefs/cl16.mk new file mode 100644 index 000000000..0f29a1521 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/cl16.mk @@ -0,0 +1,132 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Microsoft C 6.0 16 bit version. Supports 16 bit +# OS/2 development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : VC_LIBBASE +.IMPORT .IGNORE : USE_MASM + +# Default commands for compiling, assembling linking and archiving + CC := cl # C-compiler and flags + CFLAGS := /w /Gs + ASFLAGS := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELIF $(USE_MASM) + AS := masm # Assembler and flags + ASFLAGS := /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ELSE + AS := tasm # Assembler and flags +.ENDIF + LD := cl # Loader and flags + LDFLAGS = $(CFLAGS) + RC := rc # WIndows resource compiler + RCFLAGS := + LIB := lib # Librarian + LIBFLAGS := /NOI /NOE + ILIB := implib # Import librarian + ILIBFLAGS := /noignorecase + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += /Zi # Turn on debugging for C compiler + ASFLAGS += /zi # Turn on debugging for assembler +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += /Ox +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += /FPi87 /DFPU387 + ASFLAGS += /DFPU387 /DFPU_REG_RTN +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += /DBETA + ASFLAGS += /DBETA +.END + +# Use a larger stack during linking if requested ???? How the fuck do you +# specify linker options on the CL command line????? + +.IF $(STKSIZE) +.ENDIF + +# Optionally compile for 16 bit Windows +.IF $(USE_WIN16) +.IF $(BUILD_DLL) + CFLAGS += /GD /Alfw /DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += /GA /AL +.ENDIF + DX_ASFLAGS += -D__WINDOWS16__ + LIB_OS = WIN16 +.ELSE + USE_REALDOS := 1 + CFLAGS += /AL + LIB_OS = DOS16 +.END + +# Place to look for PMODE library files + +PMLIB := pm.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := cl16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/cl386.mk b/board/MAI/bios_emulator/scitech/makedefs/cl386.mk new file mode 100644 index 000000000..52157f91f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/cl386.mk @@ -0,0 +1,120 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Microsoft 386 C 6.0 32 bit. Supports 32 bit +# OS/2 development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : CL_LIBBASE USE_VDD +.IMPORT .IGNORE : USE_MASM + +# Default commands for compiling, assembling linking and archiving + CC := cl386 # C-compiler and flags + # NB: The -Zf flag is ABSOLUTELY NECESSARY to compile IBM's OS/2 headers. + # It isn't documented anywhere but obviously adds support for 48-bit + # far pointers (ie. _far is valid in 32-bit code). Great. + CFLAGS := -G3s -Zf -D__386__ + ASFLAGS := /t /mx /m /oi /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELIF $(USE_MASM) + AS := masm # Assembler and flags + ASFLAGS := /t /mx /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ELSE + AS := tasm # Assembler and flags +.ENDIF + LD := link386 # Linker and flags + LDFLAGS = $(CFLAGS) + RC := rc # Windows resource compiler + RCFLAGS := + LIB := lib # Librarian + LIBFLAGS := /NOI /NOE + ILIB := implib # Import librarian + ILIBFLAGS := /noignorecase + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -Zi # Turn on debugging for C compiler + ASFLAGS += /zi # Turn on debugging for assembler +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += /Ox +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += /FPi87 /DFPU387 + ASFLAGS += /DFPU387 /DFPU_REG_RTN +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += /DBETA + ASFLAGS += /DBETA +.END + +# Use a larger stack during linking if requested ???? How the fuck do you +# specify linker options on the CL command line????? + +.IF $(STKSIZE) +.ENDIF + +# Place to look for PMODE library files + +PMLIB := pm.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_OS = os232 + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(CL_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := cl386.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/common.mk b/board/MAI/bios_emulator/scitech/makedefs/common.mk new file mode 100644 index 000000000..d337152e7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/common.mk @@ -0,0 +1,180 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Common makefile targets used by all SciTech Software +# makefiles. This file includes targets for cleaning the +# current directory, and maintaining the source files with +# RCS. +# +############################################################################# + +# Override global OpenGL includes when compiling against MGL version + +.IF $(USE_MGL_OPENGL) +.IF $(UNIX_HOST) +CFLAGS += -I$(SCITECH)/include/mglgl +DEPEND_INC += $(SCITECH)/include/mglgl +.ELSE +CFLAGS += -I$(SCITECH)\include\mglgl +DEPEND_INC += $(SCITECH)\include/mglgl +.ENDIF +.ENDIF + +# Define where to install all compiled DLL files + +.IF $(UNIX_HOST) +.IF $(CHECKED) +DLL_DEST := $(SCITECH_LIB)/redist/debug +.ELSE +DLL_DEST := $(SCITECH_LIB)/redist/release +.ENDIF +.ELSE +.IF $(CHECKED) +DLL_DEST := $(SCITECH_LIB)\redist\debug +.ELSE +DLL_DEST := $(SCITECH_LIB)\redist\release +.ENDIF +.ENDIF + +# Target to build the library and DLL file if specified + +.IF $(LIBFILE) + +lib: $(LIBFILE) + +.IF $(DLLFILE) + +# Build and install a DLL file, or simply build import library and install + +.IF $(BUILD_DLL) + +$(DLLFILE): $(OBJECTS) +$(LIBFILE): $(DLLFILE) +install: $(LIBFILE) $(DLLFILE) + $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) + $(INSTALL) $(DLLFILE) $(DLL_DEST) +.IF $(USE_SOFTICE) + $(INSTALL) $(DLLFILE:s/.dll/.nms) $(DLL_DEST) +.ENDIF +.ELSE + +$(LIBFILE): $(DLL_DEST)\$(DLLFILE) +install: $(LIBFILE) + $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) + +.ENDIF +.ELSE + +.IF $(BUILD_DLL) + +# Build and install a Unix shared library + +$(LIBFILE): $(OBJECTS) +install: $(LIBFILE) + $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) + $(INSTALL) $(LIBFILE) $(DLL_DEST)/$(LIBFILE).$(VERSION) + +.ELSE + +# Build and install a normal library file + +.IF $(USE_DLL) +.ELSE +$(LIBFILE): $(OBJECTS) +install: $(LIBFILE) + $(INSTALL) $(LIBFILE) $(LIB_DEST)$(LIB_EXTENDER) +.ENDIF +.ENDIF +.ENDIF +.ENDIF + +# Build and install a VxD file, including debug information + +.IF $(VXDFILE) +$(VXDFILE:s/.vxd/.dll): $(OBJECTS) +$(VXDFILE): $(VXDFILE:s/.vxd/.dll) +install: $(VXDFILE) + $(INSTALL) $(VXDFILE) $(DLL_DEST) +.IF $(DBG) + $(INSTALL) $(VXDFILE:s/.vxd/.nms) $(DLL_DEST) +.ENDIF +.ENDIF + +# Clean up directory removing all files not needed to make the library. + +__CLEAN_FILES := *.obj *.o *.sym *.bak *.tdk *.swp *.map *.err *.csm *.lib *.aps *.nms *.sys +__CLEAN_FILES += *.~* *.td *.tr *.tr? *.td? *.rws *.res *.exp *.ilk *.pdb *.pch *.a bcc32.* +__CLEAN_FILES += $(LIBCLEAN) +__CLEANEXE_FILES := $(__CLEAN_FILES) *$E *.drv *.rex *.dll *.vxd *.nms *.pel *.smf *.so.* + +.PHONY clean: + @$(RM) -f -S $(mktmp $(__CLEAN_FILES:t"\n")) + +.PHONY cleanexe: + @$(RM) -f -S $(mktmp $(__CLEANEXE_FILES:t"\n")) + +# Define the source directories to find common files + +.IF $(NO_SCITECH_COMMON) +.ELSE +.SOURCE: $(SCITECH)/src/common +.ENDIF + +# Create the include file dependencies using the MKUTIL makedep program if +# the list of dependent object files is defined + +.IF $(DEPEND_OBJ) +depend: + @$(RM) -f makefile.dep +.IF $(DEPEND_SRC) +.IF $(DEPEND_INC) + @makedep -amakefile.dep -r -s -I@$(mktmp $(DEPEND_INC:s/\/\\)) -S@$(mktmp $(DEPEND_SRC:s/\/\\);$(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) +.ELSE + @makedep -amakefile.dep -r -s -S@$(mktmp $(DEPEND_SRC:s/\/\\);$(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) +.ENDIF +.ELSE +.IF $(DEPEND_INC) + @makedep -amakefile.dep -r -s -I@$(mktmp $(DEPEND_INC:s/\/\\)) -S@$(mktmp $(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) +.ELSE + @makedep -amakefile.dep -r -s -S@$(mktmp $(SCITECH)/src/common) @$(mktmp $(DEPEND_OBJ:t"\n")\n) +.ENDIF +.ENDIF + @$(ECHO) Object file dependency information generated. +.ENDIF + +# Set up for compiling Snap executeables and dynamic link libraries + +.IF $(USE_SNAP) +#CFLAGS += -I$(PRIVATE)\include\drvlib -I$(SCITECH)\include\drvlib -D__SNAP__ +CFLAGS += -D__SNAP__ +ASFLAGS += -d__SNAP__ +#EXELIBS += snap$L +.ENDIF + +# Include rule definitions for the compiler + +.INCLUDE: "$(SCITECH)/makedefs/rules/$(RULES_MAK)" + +# Include file dependencies + +.INCLUDE .IGNORE: "makefile.dep" diff --git a/board/MAI/bios_emulator/scitech/makedefs/emx.mk b/board/MAI/bios_emulator/scitech/makedefs/emx.mk new file mode 100644 index 000000000..f569790a3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/emx.mk @@ -0,0 +1,194 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# OS/2 version for EMX/GNU C/C++. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Disable warnings for macros redefined here that were given +# on the command line. +__.SILENT := $(.SILENT) +.SILENT := yes + +# Import enivornment variables that we use common to all compilers +.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB +.IMPORT .IGNORE : DBG OPT OPT_SIZE CRTDLL SHW BETA CHECKED NO_EXCEPT NO_RTTI +.IMPORT .IGNORE : FULLSCREEN SHOW_ARGS + TMPDIR := $(TEMP) + +# Standard file suffix definitions + L := .lib # Libraries + E := .exe # Executables + O := .obj # Objects + A := .asm # Assembler sources + S := .s # GNU assembler sources + P := .cpp # C++ sources + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# Import enivornment variables that we use +.IMPORT .IGNORE : EMX_LIBBASE USE_OS232 USE_OS2GUI + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# DMAKE uses this recipe to remove intermediate targets +.REMOVE :; $(RM) -f $< + +# Turn warnings back to previous setting. +.SILENT := $(__.SILENT) + +# We dont use TABS in our makefiles +.NOTABS := yes + +# Default commands for compiling, assembling linking and archiving. + CC := gcc + CFLAGS := -Zmt -Zomf -Wall -I. -I$(INCLUDE) + CXX := gcc -x c++ -fno-exceptions -fno-rtti +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -F null -d__FLAT__ -d__NOU__ -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE + AS := tasm # Assembler and flags + ASFLAGS := /t /mx /m /oi /D__FLAT__ /D__NOU__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := gcc + LDXX := gcc -x c++ + LDFLAGS := -L. -Zomf -Zmt + LIB := emxomfar + LIBFLAGS := -p32 rcv + + YACC := bison -y + LEX := flex + SED := sed + +# Optionally turn off exceptions and RTTI for C++ code +.IF $(NO_EXCEPT) + CXX += -fno-exceptions +.ENDIF +.IF $(NO_RTTI) + CXX += -fno-rtti +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g +.ELSE +# Without -s, emx always runs LINK386 with the /DEBUG option + CFLAGS += -s + LDFLAGS += -s +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -O6 +.ELIF $(OPT) + CFLAGS += -O3 -fomit-frame-pointer +.ELIF $(OPT_SIZE) + CFLAGS += -Os +.ENDIF + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.ENDIF + +# Disable standard C runtime library +.IF $(NO_RUNTIME) +CFLAGS += -fno-builtin -nostdinc +.ENDIF + +# Link against EMX DLLs (CRTDLL=1) or link with static C runtime libraries +.IF $(CRTDLL) + LDFLAGS += -Zcrtdll +.ELSE + CFLAGS += -Zsys + LDFLAGS += -Zsys +.ENDIF + +# Target environment dependant flags + CFLAGS += -D__OS2_32__ + CFLAGS += -D__OS2__ + ASFLAGS += -d__OS2__ + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)/lib/release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)\OS232\$(EMX_LIBBASE) + LDFLAGS += -L$(LIB_DEST) + +# Build 32-bit OS/2 apps +.IF $(BUILD_DLL) + CFLAGS += -Zdll -DBUILD_DLL + LDFLAGS += -Zdll + ASFLAGS += -dBUILD_DLL +.ELSE +.IF $(USE_OS2GUI) + CFLAGS += -D__OS2_PM__ + LDFLAGS += -Zlinker /PMTYPE:PM +.ELSE +.IF $(FULLSCREEN) + LDFLAGS += -Zlinker /PMTYPE:NOVIO +.ELSE + LDFLAGS += -Zlinker /PMTYPE:VIO +.ENDIF +.ENDIF +.ENDIF + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := emx.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk new file mode 100644 index 000000000..0d62fdf1a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_beos.mk @@ -0,0 +1,161 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# BeOS version for GNU C/C++. +# +############################################################################# + +# Disable warnings for macros redefined here that were given +# on the command line. +__.SILENT := $(.SILENT) +.SILENT := yes + +# Import enivornment variables that we use common to all compilers +.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB +.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_X11 USE_LINUX +.IMPORT .IGNORE : USE_EGCS USE_PGCC STATIC_LIBS LIBC + TMPDIR := $(TEMP) + +# Standard file suffix definitions +# +# NOTE: BeOS does not require any extenion for executeable files, but you +# can use an extension if you wish. We use the .x extension for building +# executeable files so that we can use implicit rules to make the +# makefiles simpler and more portable between systems. When you install +# the files to a local bin directory, you will probably want to remove +# the .x extension. + L := .a # Libraries + E := .x # Executables + O := .o # Objects + A := .asm # Assembler sources + S := .s # GNU assembler sources + P := .cpp # C++ sources + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We use the Unix shell at all times + SHELLFLAGS := -c + +# Definition of $(MAKE) macro for recursive makes. + MAKE = $(MAKECMD) $(MFLAGS) + +# Macro to install a library file + INSTALL := cp + +# DMAKE uses this recipe to remove intermediate targets +.REMOVE :; $(RM) -f $< + +# Turn warnings back to previous setting. +.SILENT := $(__.SILENT) + +# We dont use TABS in our makefiles +.NOTABS := yes + +# Define that we are compiling for BeOS + USE_BEOS := 1 + +# Default commands for compiling, assembling linking and archiving. + CC := gcc + CFLAGS := -Wall -I. -Iinclude $(INCLUDE) + CXX := g++ + AS := nasm + ASFLAGS := -f elf -d__FLAT__ -iinclude -i$(SCITECH)/include -d__NOU__ + LD := gcc + LDFLAGS := -L. + LIB := ar + LIBFLAGS := rcs + +# Link to static libraries if requested +.IF $(STATIC_LIBS) + LDFLAGS += -static +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g +.ELSE +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -O6 +.ELIF $(OPT) + CFLAGS += -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -O1 +.ENDIF + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.ENDIF + +# Disable standard C runtime library + +.IF $(NO_RUNTIME) +CFLAGS += -fno-builtin -nostdinc +.ENDIF + +# Target environment dependant flags + CFLAGS += -D__BEOS__ + ASFLAGS += -d__BEOS__ -d__UNIX__ + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)/lib/release +.ENDIF + +# Define where to install library files +LIB_DEST := $(LIB_BASE_DIR)/beos/gcc +LDFLAGS += -L$(LIB_DEST) + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := gcc_beos.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk new file mode 100644 index 000000000..65589c83a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_dos.mk @@ -0,0 +1,112 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# DJGPP V2 port of GNU C/C++ to DOS with DPMI only. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Override some file suffix definitions + L := .a # Libraries + O := .o # Objects + +# Override the file prefix/suffix definitions for library naming. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# Import enivornment variables that we use +.IMPORT .IGNORE : DJ_LIBBASE + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := gcc # C-compiler and flags + CFLAGS := -Wall + AS := nasm + ASFLAGS := -t -f coff -F null -d__FLAT__ -d__GNUC__ -dSTDCALL_USCORE -iINCLUDE -i$(SCITECH)\INCLUDE + LD := dj_ld # Loader and flags + LDFLAGS := + LIB := ar # Librarian + LIBFLAGS := rs + USE_NASM := 1 + USE_GCC := 1 + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g # Turn on debugging for C compiler +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -O1 +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +# DOS extender dependant flags + DX_CFLAGS += + DX_ASFLAGS += -dDJGPP + USE_REALDOS := 1 + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)\DOS32\$(DJ_LIBBASE) + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := dj32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk new file mode 100644 index 000000000..0cb4b8530 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_freebsd.mk @@ -0,0 +1,174 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Linux version for GNU C/C++. +# +############################################################################# + +# Disable warnings for macros redefined here that were given +# on the command line. +__.SILENT := $(.SILENT) +.SILENT := yes + +# Import enivornment variables that we use common to all compilers +.IMPORT .IGNORE : TEMP SHELL INCLUDE LIB SCITECH PRIVATE SCITECH_LIB +.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA CHECKED USE_X11 USE_FREEBSD +.IMPORT .IGNORE : USE_EGCS USE_PGCC STATIC_LIBS + TMPDIR := $(TEMP) + +# Standard file suffix definitions +# +# NOTE: Linux does not require any extenion for executeable files, but you +# can use an extension if you wish. We use the .x extension for building +# executeable files so that we can use implicit rules to make the +# makefiles simpler and more portable between systems. When you install +# the files to a local bin directory, you will probably want to remove +# the .x extension. + L := .a # Libraries + E := .x # Executables + O := .o # Objects + A := .asm # Assembler sources + S := .s # GNU assembler sources + P := .cpp # C++ sources + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We use the Unix shell at all times + SHELL := /bin/sh + SHELLFLAGS := -c + +# Definition of $(MAKE) macro for recursive makes. + MAKE = $(MAKECMD) $(MFLAGS) + +# Macro to install a library file + INSTALL := cp + +# DMAKE uses this recipe to remove intermediate targets +.REMOVE :; $(RM) -f $< + +# Turn warnings back to previous setting. +.SILENT := $(__.SILENT) + +# We dont use TABS in our makefiles +.NOTABS := yes + +# Define that we are compiling for FreeBSD + USE_LINUX := 1 + +# Default commands for compiling, assembling linking and archiving. +.IF $(USE_EGCS) + CC := egcs +.ELIF $(USE_PGCC) + CC := pgcc +.ELSE + CC := gcc +.ENDIF + CFLAGS := -Wall -I. -Iinclude $(INCLUDE) + CXX := g++ + AS := nasm +# TODO: On earlier versions of FreeBSD (<3.0) a.out is used instead of ELF + ASFLAGS := -f elf -d__FLAT__ -iinclude -i$(SCITECH)/include -d__NOU__ + LD := g++ + LDFLAGS := -L. + LIB := ar + LIBFLAGS := rcs + +# Link to static libraries if requested +.IF $(STATIC_LIBS) + LDFLAGS += -static +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g +.ELSE +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -O6 +.ELIF $(OPT) + CFLAGS += -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -O1 +.ENDIF + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.ENDIF + +# Disable standard C runtime library + +.IF $(NO_RUNTIME) +CFLAGS += -fno-builtin -nostdinc +.ENDIF + +# Compile flag for whether to build X11 or non-X11 lib +.IF $(USE_X11) + CFLAGS += -D__X11__ +.ENDIF + +# Target environment dependant flags + CFLAGS += -D__FREEBSD__ + ASFLAGS += -d__FREEBSD__ -d__UNIX__ + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)/lib/release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)/freebsd/gcc + LDFLAGS += -L$(LIB_DEST) + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := gcc_freebsd.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk new file mode 100644 index 000000000..72c4cedfd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_linux.mk @@ -0,0 +1,180 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Linux version for GNU C/C++. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)/makedefs/startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : GCC2_LIBBASE + +# Override some file suffix definitions + L := .a # Libraries + O := .o # Objects + +# Override the file prefix/suffix definitions for library naming. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Define that we are compiling for Linux + USE_LINUX := 1 + +# Default commands for compiling, assembling linking and archiving. + CC := gcc + CFLAGS := -Wall -I. -Iinclude -I$(SCITECH:s,\,/)/include -I$(PRIVATE:s,\,/)/include + SHOW_CFLAGS := -c + CXX := g++ + AS := nasm + ASFLAGS := -t -f elf -d__FLAT__ -d__GNUC__ -iinclude -i$(SCITECH)/include -d__NOU__ + SHOW_ASFLAGS := -f elf + LD := gcc + LDXX := g++ + LDFLAGS := -L. + LIB := ar + LIBFLAGS := rcs + YACC := bison -y + LEX := flex + SED := sed + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g + SHOW_CFLAGS += -g +.ELSE +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -O6 + SHOW_CFLAGS += -O6 +.ELIF $(OPT) + CFLAGS += -O2 + SHOW_CFLAGS += -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -O1 + SHOW_CFLAGS += -O1 +.ENDIF + +# Optionally turn on direct i387 FPU instructions +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + SHOW_CFLAGS += -DBETA + ASFLAGS += -dBETA + SHOW_ASFLAGS += -dBETA +.ENDIF + +# Disable standard C runtime library + +.IF $(NO_RUNTIME) +CFLAGS += -fno-builtin -nostdinc +.ENDIF + +# Compile flag for whether to build X11 or non-X11 lib +.IF $(USE_X11) + CFLAGS += -D__X11__ +.ENDIF + +# Target environment dependant flags + CFLAGS += -D__LINUX__ + ASFLAGS += -d__LINUX__ -d__UNIX__ + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)/lib/debug +CFLAGS += -DCHECKED=1 +SHOW_CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)/lib/release +.ENDIF + +# Define where to install library files +.IF $(LIBC) + LIB_DEST_SHARED := $(LIB_BASE_DIR)/linux/gcc/libc.so + LIB_DEST_STATIC := $(LIB_BASE_DIR)/linux/gcc/libc +.ELSE + LIB_DEST_SHARED := $(LIB_BASE_DIR)/linux/gcc/glibc.so + LIB_DEST_STATIC := $(LIB_BASE_DIR)/linux/gcc/glibc +.ENDIF + +# Link to static libraries if requested +.IF $(STATIC_LIBS_ALL) + LDFLAGS += -static + STATIC_LIBS := 1 +.ENDIF + +# Link to static libraries if requested +.IF $(STATIC_LIBS) + LDFLAGS += -L$(LIB_DEST_STATIC) +.ELSE + LDFLAGS += -L$(LIB_DEST_SHARED) -L$(LIB_DEST_STATIC) +.ENDIF + +# Optionally enable some dynamic libraries to be built +.IF $(BUILD_DLL) +.IF $(VERSIONMAJ) +.ELSE + VERSIONMAJ := 5 + VERSIONMIN := 0 +.ENDIF + VERSION := $(VERSIONMAJ).$(VERSIONMIN) + LIB := gcc -shared + LIBFLAGS := + L := .so + CFLAGS += -fPIC + SHOW_CFLAGS += -fPIC + ASFLAGS += -D__PIC__ + SHOW_ASFLAGS += -D__PIC__ + LIB_DEST := $(LIB_DEST_SHARED) +.ELSE + LIB_DEST := $(LIB_DEST_STATIC) +.ENDIF + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := gcc_linux.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk b/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk new file mode 100644 index 000000000..21ccf9784 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/gcc_win32.mk @@ -0,0 +1,135 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Cygwin port of GNU C/C++ to Win32. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : GCC2_LIBBASE + +# Override some file suffix definitions + L := .a # Libraries + O := .o # Objects + +# Override the file prefix/suffix definitions for library naming. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := gcc # C-compiler and flags + CFLAGS := -Wall -I. -Iinclude -I$(SCITECH:s,\,/)/include -I$(PRIVATE:s,\,/)/include + SHOW_CFLAGS := -c + CXX := g++ + AS := nasm + ASFLAGS := -t -f coff -F null -d__FLAT__ -d__GNUC__ -dSTDCALL_USCORE -iINCLUDE -i$(SCITECH)\INCLUDE + SHOW_ASFLAGS := -f coff + LD := gcc # Loader and flags + LDXX := g++ +.IF $(WIN32_GUI) + LDFLAGS := -L. -mwindows -e _mainCRTStartup +.ELSE + LDFLAGS := -L. +.ENDIF + RC := windres + RCFLAGS := -O coff + LIB := ar # Librarian + LIBFLAGS := rcs + YACC := bison -y + LEX := flex + SED := sed + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g + SHOW_CFLAGS += -g +.ELSE +# NASM does not support debugging information yet + ASFLAGS += +.ENDIF + +# Optionally turn on optimisations +.IF $(OPT_MAX) + CFLAGS += -O6 + SHOW_CFLAGS += -O6 +.ELIF $(OPT) + CFLAGS += -O2 + SHOW_CFLAGS += -O2 +.ELIF $(OPT_SIZE) + CFLAGS += -O1 + SHOW_CFLAGS += -O1 +.ENDIF + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + SHOW_CFLAGS += -DBETA + ASFLAGS += -dBETA + SHOW_ASFLAGS += -dBETA +.ENDIF + +# DOS extender dependant flags + DX_CFLAGS += + DX_ASFLAGS += -dGCC_WIN32 + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +SHOW_CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_DEST := $(LIB_BASE_DIR)\WIN32\$(GCC2_LIBBASE) + LDFLAGS += -L$(LIB_DEST) + +# Place to look for PMODE library files + +PMLIB := -lpm + +# Define which file contains our rules + + RULES_MAK := gcc_win32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/hc32.mk b/board/MAI/bios_emulator/scitech/makedefs/hc32.mk new file mode 100644 index 000000000..f0b065a47 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/hc32.mk @@ -0,0 +1,113 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Metaware High C/C++ 3.21 32 bit version. Supports Phar Lap's +# TNT DOS Extender. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := hc386 # C-compiler and flags + CFLAGS := +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF + ASFLAGS := /t /mx /m /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE + LD := hc386 + LDFLAGS = $(CFLAGS) + LIB := 386lib # TNT 386|lib Librarian + LIBFLAGS := -TC + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g # Turn on debugging for C compiler + ASFLAGS += /zi # Turn on debugging for assembler +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -586 -O +.ELIF $(OPT_SIZE) + CFLAGS += -586 -O1 +.ELSE + CFLAGS += -O0 +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -DFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + +# DOS extender dependant flags + USE_TNT := 1 + USE_REALDOS := 1 + DX_CFLAGS += -DTNT + DX_ASFLAGS += -DTNT + LDFLAGS += -LH:\TNT\LIB + +# Place to look for PMODE library files + +PMLIB := tnt\pm.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\DOS32\HC + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := hc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj b/board/MAI/bios_emulator/scitech/makedefs/makedefs.prj new file mode 100644 index 0000000000000000000000000000000000000000..edd8809e29703910feeca27a5c3d465461aff1de GIT binary patch literal 9025 zcmeI2`BxKH6vyvn5fm2$6v1tjh#(3itm1-U2pArrH0;vUMUxFRz@~bmtq2E>KBjz2wxHb&M5X-h36E{d4->(@n1hx_?g1b zi3r~)k>4u(j+h7+h@0S|;<=>oG7%E5FySZ4fu9+_Fn%TAZ){zKB!Dr1YrOG0<2vIH z&XP_g5fgq?_HZGM+!q;_l;gO}<`pv2;Rj+8+~B+q=MerRE9oY0-eUL}fTTzbFp&UB zjAX_%_N5SVQVCtt3DOJ#q%mePW-(?Ha1LAPY|Ujn&uT9a@I|&>V(VqLUSaE1#%qk% z*>{R@nm6BPe88J;Fy162zQxwtjCUCCGTvi+#Q2zz!IGJL1X+xEjQNag49wvI-pE0o z?_4$)G8PeVFf{{OF^)6tW!y)Ary2M2<|yL?V~p_t<3Ywl z1bCROM;MRt=3|VYr&oG{4oMb%5NJ=LpGo~?87^#dkSWh!J`Bsc$&`{&4 zlgm8TX1S@Q-m*@v@wjBG+ahlkuF1>%?H)>QA48M14m^xI-Ad{5EHeQZF&Ru1q;4X^ zSXv5Dh9~ay!Hm}{$0e|8yfb9GB5Fis)QGC65!F#6)<%t}i5jskYQ*}e5gVdLY>XOF z8#Q7RUAT9=cX6@oa6qF{D*S%BpJ5u+ z+JuwN{2B0lDvUNdEe;(gvB&2f)DfmTWKDmOWUyIm1x8bKp=4;byV}eS$>4C>Z4S3& zkZHr_YAoQRGm%kvc%ZjST2Q-Ll%tJ%ozK(-l-$cT0v&%No-{SF? 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You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Whether to link in real VBIOS library, or just the stub library + +.IF $(USE_BIOS) +VBIOSLIB := -lvbios +.ELSE +VBIOSLIB := -lvbstubs +.END + +# Implicit generation rules for making object files from source files +%$O: %.c ; $(CC) $(CFLAGS) -c $< +%$O: %$P ; $(CXX) $(CPPFLAGS) -c $< +%$O: %$A ; $(AS) -o $@ $(ASFLAGS) $< + +# Implicit rule for building a library file +%$L: ; $(LIB) $(LIBFLAGS) $@ $& + +# Implicit rule for building an executable file +%$E: ; $(LD) $(LDFLAGS) -o $@ $& $(EXELIBS) $(PMLIB) $(VBIOSLIB) diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk new file mode 100644 index 000000000..b33bcd86a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/sc16.mk @@ -0,0 +1,63 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) $(CFLAGS) -c $< +%$O: %$P ; $(CC) $(CFLAGS) -c $< +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +%$D: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(EXELIBS)) + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN16) +%$E: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(EXELIBS)) +.ELSE +%$E: ; $(LD) $(LDFLAGS) @$(mktmp $(&:s/\/\\) $(PMLIB) $(EXELIBS)) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk new file mode 100644 index 000000000..2231906d6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/sc32.mk @@ -0,0 +1,69 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) $(CFLAGS) -c $< +%$O: %$P ; $(CC) $(CFLAGS) -c $< +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +%$D: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(EXELIBS) kernel32.lib user32.lib gdi32.lib winmm.lib comdlg32.lib advapi32.lib) + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; $(LIB) $(LIBFLAGS) $@ @$(mktmp -+$(?:t" &\n-+")\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_TNT) +%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(PMLIB) $(EXELIBS)) +.ELIF $(USE_WIN32) +%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(EXELIBS) kernel32.lib user32.lib gdi32.lib winmm.lib comdlg32.lib advapi32.lib) +.ELSE +%$E: ; $(LD) $(LDFLAGS) @$(mktmp,$*.lnk $(&:s/\/\\) $(PMLIB) $(EXELIBS)) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk new file mode 100644 index 000000000..1a20319cb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/va32.mk @@ -0,0 +1,82 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) +%$O: %$P ; $(CPP) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building help files +%.hlp: %.ipf; $(IPFC) $(IPFCFLAGS) $< + +# Implicit rule for building a DLL using a response file +.IF $(USE_OS2GUI) +%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.ELSE +%$D: ; $(LD) /nofree /nol @$(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.ENDIF + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; $(LIB) $(LIBFLAGS) @$(mktmp $@-+$(?:t"&\n-+":s/\/\\);) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_OS2GUI) +%$E: ; + rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ELSE +%$E: ; + rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n\n) +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk new file mode 100644 index 000000000..2b4180146 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/va365.mk @@ -0,0 +1,79 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) +%$O: %$P ; $(CPP) -c @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +.IF $(USE_OS2GUI) +%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.ELSE +%$D: ; $(LD) /nofree /nol @$(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.ENDIF + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) /out:$@ $? +.ELIF $(IMPORT_DLL) +%$L: ; $(ILIB) $(ILIBFLAGS) /out:$@ $? +.ELSE +%$L: ; $(LIB) $(LIBFLAGS) /nowarn:86 /out:$@ @$(mktmp $(?:t"\n":s/\/\\)) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_OS2GUI) +%$E: ; + rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n$*.def\n) +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ELSE +%$E: ; + rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) $(&:t"+\n":s/\/\\)\n$@\n$*.map\n$(EXELIBS) $(PMLIB)\n\n) +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk new file mode 100644 index 000000000..6ffc270c0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/vc16.mk @@ -0,0 +1,70 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) /nologo $(CFLAGS) /c $< +%$O: %$P ; $(CC) /nologo $(CFLAGS) /c $< +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +%$D: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) -e$@\n$(&:t"\n":s/\/\\)\n$(EXELIBS)) + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ $? +.ELIF $(IMPORT_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ $? +.ELSE +%$L: ; + @$(RM) $@ + $(LIB) $@ /nologo $(LIBFLAGS) @$(mktmp +$(&:t" &\n+") &\n,\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN16) +%$E: ; rclink $(LD) $(RC) $@ $(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) +#%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(EXELIBS)) +.ELSE +%$E: ; $(LD) @$(mktmp $(LDFLAGS) /Fe$@ $(&:s/\/\\) $(PMLIB) $(EXELIBS)) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk new file mode 100644 index 000000000..97f1a0c16 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/vc32.mk @@ -0,0 +1,122 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Turn on pre-compiled headers as neccessary +.IF $(PRECOMP_HDR) + CFLAGS += -YX"$(PRECOMP_HDR)" +.ENDIF + +# Turn on runtime type information as necessary +.IF $(USE_RTTI) + CFLAGS += /GR +.ENDIF + +# Turn on C++ exception handling as necessary +.IF $(USE_CPPEXCEPT) + CFLAGS += /GX +.ENDIF + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) /nologo @$(mktmp $(CFLAGS:s/\/\\)) /c $(<:s,/,\) +%$O: %$P ; $(CC) /nologo @$(mktmp $(CFLAGS:s/\/\\)) /c $(<:s,/,\) +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rules for building NT device drivers + +%.sys: ; + $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) +.IF $(DBG) +.IF $(USE_SOFTICE) + $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ +.ENDIF +.ENDIF + +# Implicit rule for building a DLL using a response file +.IF $(IMPORT_DLL) +.ELSE +.IF $(NO_RUNTIME) +%$D: ; $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) +.ELSE +%$D: ; + makedef -v $* + $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) +.IF $(DBG) +.IF $(USE_SOFTICE) + $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ +.ENDIF +.ENDIF +.ENDIF +.ENDIF + +# Implicit rule for building a library file using response file. Note that +# we use a special .VCD file that contains the EXPORT definitions for the +# Microsoft compiler, since the LIB utility automatically adds leading +# underscores to exported functions. +.IF $(IMPORT_DLL) +%$L: ; + makedef -v $(?:b) + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) /DEF:$(?:b).def /OUT:$@ +.ELSE +%$L: ; + @$(RM) $@ + $(LIB) $(LIBFLAGS) /out:$@ @$(mktmp $(&:t"\n")\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN32) +%$E: ; + $(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) +.IF $(DBG) +.IF $(USE_SOFTICE) + $(NMSYM) $(NMSYMFLAGS);$(SI_SOURCE) $@ +.ENDIF +.ENDIF +.ELSE +%$E: ; + @$(LD) /nologo @$(mktmp $(LDFLAGS) /Fe$@ $(&:t"\n"s/\/\\) $(PMLIB) $(EXELIBS) $(DEF_LIBS) $(LDENDFLAGS)) +.IF $(DOSSTYLE) + @markphar $@ +.ENDIF +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk new file mode 100644 index 000000000..d1ca9176e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/wc16.mk @@ -0,0 +1,79 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Implicit generation rules for making object files +%$O: %.c ; $(CC) @$(mktmp $(CFLAGS)) $< +%$O: %$P ; $(CPP) @$(mktmp $(CFLAGS)) $< +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS)) $(<:s,/,\) + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ +$? +.ELIF $(IMPORT_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ +$? +.ELSE +%$L: ; + @$(RM) $@ + $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp +$(&:t"\n+":s/\/\\)\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_WIN16) +.IF $(BUILD_DLL) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS windows_dll\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk + @$(RM) -S $(mktmp $*.lnk) +.ELSE +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS windows\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk + @$(RM) -S $(mktmp $*.lnk) +.ENDIF +.ELSE +%$E: ; + @trimlib $(mktmp OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB) $(EXELIBS:t",")) $*.lnk + $(LD) $(LDFLAGS) @$*.lnk + @$(RM) -S $(mktmp $*.lnk) +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk b/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk new file mode 100644 index 000000000..39b8819b2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/rules/wc32.mk @@ -0,0 +1,264 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Rules makefile definitions, which define the rules used to +# build targets. We include them here at the end of the +# makefile so the generic project makefiles can override +# certain things with macros (such as linking C++ programs +# differently). +# +############################################################################# + +# Take out PMLIB if we don't need to link with it + +.IF $(NO_PMLIB) +PMLIB := +.ENDIF + +# Use a larger stack during linking if requested, or use a default stack +# of 200k. The usual default stack provided by Watcom C++ is *way* to small +# for real 32 bit code development. We also need a *huge* stack for OpenGL +# software rendering also! +.IF $(USE_QNX4) + # Not necessary for QNX code. +.ELSE +.IF $(STKSIZE) + LDFLAGS += OP STACK=$(STKSIZE) +.ELSE + LDFLAGS += OP STACK=204800 +.ENDIF +.ENDIF + +# Turn on runtime type information as necessary +.IF $(USE_RTTI) + CPFLAGS += -xr +.ENDIF + +# Optionally turn on pre-compiled headers +.IF $(PRECOMP_HDR) + CFLAGS += -fhq +.ENDIF + +.IF $(USE_QNX) +# Whether to link in real VBIOS library, or just the stub library +.IF $(USE_BIOS) +VBIOSLIB := vbios.lib, +.ELSE +VBIOSLIB := vbstubs.lib, +.END +# Require special privledges for Nucleus programs (requires root access) +.IF $(USE_NUCLEUS) +LDFLAGS += OP PRIV=1 +.ENDIF +.ENDIF + +# Implicit generation rules for making object files +.IF $(WC_LIBBASE) == WC10A +%$O: %.c ; $(CC) $(CFLAGS) $(<:s,/,\) +%$O: %$P ; $(CPP) $(CFLAGS) $(<:s,/,\) +.ELSE +%$O: %.c ; $(CC) @$(mktmp $(CFLAGS:s/\/\\)) $(<:s,/,\) +%$O: %$P ; $(CPP) @$(mktmp $(CPFLAGS:s/\/\\) $(CFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF +.IF $(USE_NASM) +%$O: %$A ; $(AS) @$(mktmp -o $@ $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +%$O: %$A ; $(AS) @$(mktmp $(ASFLAGS:s/\/\\)) $(<:s,/,\) +.ENDIF + +# Implit rule to compile .S assembler files. The first version +# uses GAS directly and the second uses a pre-processor to +# produce NASM code. + +.IF $(USE_GAS) +.IF $(WC_LIBBASE) == WC11 +%$O: %$S ; $(GAS) -c @$(mktmp $(GAS_FLAGS:s/\/\\)) $(<:s,/,\) +.ELSE +# Black magic to build asm sources with Watcom 10.6 (requires sed) +%$O: %$S ; + $(GAS) -c @$(mktmp $(GAS_FLAGS:s/\/\\)) $(<:s,/,\) + wdisasm \\ -a $(*:s,/,\).o > $(*:s,/,\).lst + sed -e "s/\.text/_TEXT/; s/\.data/_DATA/; s/\.bss/_BSS/; s/\.386/\.586/; s/lar *ecx,cx/lar ecx,ecx/" $(*:s,/,\).lst > $(*:s,/,\).asm + wasm \\ $(WFLAGS) -zq -fr=nul -fp3 -fo=$@ $(*:s,/,\).asm + $(RM) -S $(mktmp $(*:s,/,\).o) + $(RM) -S $(mktmp $(*:s,/,\).lst) + $(RM) -S $(mktmp $(*:s,/,\).asm) +.ENDIF +.ELSE +%$O: %$S ; + @gcpp -DNASM_ASSEMBLER -D__WATCOMC__ -EP $(<:s,/,\) > $(*:s,/,\).asm + nasm @$(mktmp -f obj -o $@) $(*:s,/,\).asm + @$(RM) -S $(mktmp $(*:s,/,\).asm) +.ENDIF + +# Special target to build dllstart.asm using Borland TASM +dllstart.obj: dllstart.asm + $(DLL_TASM) @$(mktmp /t /mx /m /D__FLAT__ /i$(SCITECH)\INCLUDE /q) $(PRIVATE)\src\common\dllstart.asm + +# Implicit rule for building resource files +%$R: %.rc ; $(RC) $(RCFLAGS) -r $< + +# Implicit rule for building a DLL using a response file +.IF $(IMPORT_DLL) +.ELSE +.IF $(USE_OS232) +%$D: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2 dll\nN $@\nF $(&:t",\n":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELIF $(USE_WIN32) +%$D: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt_dll\nN $@\nF $(&:t",\n":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELSE +%$D: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS win386\nN $*.rex\nF $(&:t",\n":s/\/\\)\nLIBR $(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk + wbind $* -d -q -n +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ENDIF +.ENDIF + +# Implicit rule for building a library file using response file +.IF $(BUILD_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ +$? +.ELIF $(IMPORT_DLL) +%$L: ; + @$(RM) $@ + $(ILIB) $(ILIBFLAGS) $@ +$? +.ELSE +%$L: ; + @$(RM) $@ + $(LIB) $(LIBFLAGS) $@ @$(mktmp,$*.rsp +$(&:t"\n+":s/\/\\)\n) +.ENDIF + +# Implicit rule for building an executable file using response file +.IF $(USE_X32) +%$E: ; + @trimlib $(mktmp OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk + $(LD) $(LDFLAGS) @$*.lnk + x32fix $@ +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELIF $(USE_OS232) +.IF $(USE_OS2GUI) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2_pm\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ELSE +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS os2v2\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.IF $(LXLITE) + lxlite $@ +.ENDIF +.ENDIF +.ELIF $(USE_SNAP) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(DEFLIBS)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELIF $(USE_WIN32) +.IF $(WIN32_GUI) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS win95\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELSE +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS nt\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(DEFLIBS)$(EXELIBS:t",")) $*.lnk + rclink $(LD) $(RC) $@ $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ENDIF +.ELIF $(USE_WIN386) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet SYS win386\nN $*.rex\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk + rclink $(LD) wbind $*.rex $*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELIF $(USE_TNT) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR dosx32.lib,tntapi.lib,$(PMLIB)$(EXELIBS:t",")) $*.lnk + $(LD) @$*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.IF $(DOSSTYLE) + @markphar $@ +.ENDIF +.ELIF $(USE_QNX4) +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(VBIOSLIB)$(EXELIBS:t",")) $*.lnk + @+if exist $*.exe attrib -s $*.exe > NUL + $(LD) @$*.lnk + @attrib +s $*.exe +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ELSE +%$E: ; + @trimlib $(mktmp $(LDFLAGS) OP quiet\nN $@\nF $(&:t",":s/\/\\)\nLIBR $(PMLIB)$(EXELIBS:t",")) $*.lnk + $(LD) @$*.lnk +.IF $(LEAVE_LINKFILE) +.ELSE + @$(RM) -S $(mktmp *.lnk) +.ENDIF +.ENDIF diff --git a/board/MAI/bios_emulator/scitech/makedefs/sc16.mk b/board/MAI/bios_emulator/scitech/makedefs/sc16.mk new file mode 100644 index 000000000..099ad4552 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/sc16.mk @@ -0,0 +1,128 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Symantec C++ 6.x/7.x 16 bit version. Supports 16 bit DOS +# and 16 bit Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : SC_LIBBASE + +# Default commands for compiling, assembling linking and archiving + CC := sc # C-compiler and flags + CFLAGS := -ml -Jm +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF + ASFLAGS := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE + LD := sc # Loader and flags + LDFLAGS = $(CFLAGS) + RC := rcc # WIndows resource compiler + RCFLAGS := # Mark as Win32 compatible resources + LIB := lib # Librarian + LIBFLAGS := /N /B + ILIB := implib # Import librarian + ILIBFLAGS := + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g # Turn on debugging for C compiler +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -5 -o+all +.ELIF $(OPT_SIZE) + CFLAGS += -5 -o+space +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -ff -DFPU387 + ASFLAGS += -DFPU387 -DFPU_REG_RTN +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + +# User a larger stack if requested + +.IF $(STKSIZE) + LDFLAGS += =$(STKSIZE) +.ENDIF + +# Optionally compile for 16 bit Windows +.IF $(USE_WIN16) +.IF $(BUILD_DLL) + CFLAGS += -WD -DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += -WA +.ENDIF + DX_ASFLAGS += -D__WINDOWS16__ + LIB_OS = WIN16 +.ELSE + USE_REALDOS := 1 + LIB_OS = DOS16 +.END + +# Place to look for PMODE library files + +PMLIB := pm.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(SC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := sc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/sc32.mk b/board/MAI/bios_emulator/scitech/makedefs/sc32.mk new file mode 100644 index 000000000..9ca757088 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/sc32.mk @@ -0,0 +1,178 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Symantec C++ 6.x/7.x 32 bit version. Supports the DOSX +# extender, FlashTek X32 and Phar Lap's TNT DOS Extender +# and 32 bit Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : USE_TNT USE_X32 USE_X32VM SC_LIBBASE + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := sc # C-compiler and flags + CFLAGS := -Jm +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF +.IF $(USE_WIN32) + ASFLAGS := /t /mx /m /D__FLAT__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ELSE + ASFLAGS := /t /mx /m /DES_NOT_DS /D__COMM__ /i$(SCITECH)\INCLUDE +.ENDIF + LD := sc # Loader and flags + LD_FLAGS = + RC := rcc # WIndows resource compiler + RCFLAGS := -32 # Mark as Win32 compatible resources + LIB := lib # Librarian + LIBFLAGS := /N /B + ILIB := implib # Import librarian + ILIBFLAGS := + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -g # Turn on debugging for C compiler (FlashView) +.IF $(USE_TNT) + LDFLAGS += -fullsym # Turn on debugging for TNT 386link linker +.END +.IF $(USE_X32) or $(USE_X32VM) + LDFLAGS += -L/map # Turn on debugging for FlashView debugger +.END +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -5 -o+all +.ELIF $(OPT_SIZE) + CFLAGS += -5 -o+space +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += -ff -DFPU387 + ASFLAGS += -DFPU387 -DFPU_REG_RTN +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + +# User a larger stack if requested + +.IF $(STKSIZE) + LDFLAGS += =$(STKSIZE) +.ENDIF + +.IF $(USE_TNT) # Use Phar Lap's TNT DOS Extender + CFLAGS += -mp + DX_CFLAGS += -DTNT + ASFLAGS += /D__FLAT__ + DX_ASFLAGS += -DTNT + LD := 386link + LDFLAGS += @sc32.dos -exe $@ + LIB_OS = DOS32 +.ELIF $(USE_X32VM) # Use FlashTek X-32VM DOS extender + CFLAGS += -mx + DX_CFLAGS += -DX32VM + ASFLAGS += /D__X386__ + DX_ASFLAGS += -DX32VM + LD := sc + LDFLAGS += $(CFLAGS) x32v.lib + LIB_OS = DOS32 +.ELIF $(USE_X32) # Use FlashTek X-32 DOS extender + CFLAGS += -mx + DX_CFLAGS += -DX32VM + ASFLAGS += /D__X386__ + DX_ASFLAGS += -DX32VM + LD := sc + LDFLAGS += $(CFLAGS) x32.lib + LIB_OS = DOS32 +.ELIF $(USE_WIN32) # Build 32 bit Windows NT app +.IF $(BUILD_DLL) + CFLAGS += -WD -mn + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += -WA -mn +.ENDIF + DX_ASFLAGS += -D__WINDOWS32__ + LIB_OS = WIN32 +.ELSE # Use default Symantec DOSX extender + USE_DOSX := 1 + USE_REALDOS := 1 + CFLAGS += -mx + DX_CFLAGS += -DDOSX + ASFLAGS += /D__X386__ + DX_ASFLAGS += -DDOSX + LD := sc + LDFLAGS += $(CFLAGS) + LIB_OS = DOS32 +.END + +# Place to look for PMODE library files + +.IF $(USE_TNT) +PMLIB := tnt\pm.lib +.ELIF $(USE_X32) +PMLIB := x32\pm.lib +.ELSE +PMLIB := dosx\pm.lib +.END + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(SC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := sc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/startup.mk b/board/MAI/bios_emulator/scitech/makedefs/startup.mk new file mode 100644 index 000000000..d8b2ba2b9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/startup.mk @@ -0,0 +1,161 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Common startup script that defines all variables common to +# all startup scripts. These define the DMAKE runtime +# environment and the values are dependant on the version of +# DMAKE in use. +# +############################################################################# + +# Disable warnings for macros redefined here that were given +# on the command line. +__.SILENT := $(.SILENT) +.SILENT := yes + +# Import enivornment variables that we use common to all compilers +.IMPORT .IGNORE : TEMP SHELL COMSPEC INCLUDE LIB SCITECH PRIVATE SCITECH_LIB +.IMPORT .IGNORE : DBG OPT OPT_SIZE SHW BETA USE_WIN32 FPU BUILD_DLL BUILD_FOR_DLL +.IMPORT .IGNORE : IMPORT_DLL USE_TASMX WIN32_GUI USE_WIN16 USE_NASM CHECKED +.IMPORT .IGNORE : OS2_SHELL SOFTICE_PATH MAX_WARN USE_SOFTICE USE_TASM32 +.IMPORT .IGNORE : DLL_START_TASM USE_SNAP USE_X11 USE_LINUX STATIC_LIBS LIBC +.IMPORT .IGNORE : SHOW_ARGS BOOT_STRAP_DMAKE + TMPDIR := $(TEMP) + +# Determine if the host machine is a Windows/DOS or Unix box +.IF $(COMSPEC) + WIN32_HOST := 1 +.ELSE + USE_NASM := 1 + UNIX_HOST := 1 +.ENDIF + +# Setup to either user NASM or TASM as the assembler +.IF $(USE_NASM) +.ELSE + USE_TASM := 1 +.ENDIF + +.IF $(UNIX_HOST) +# Standard file suffix definitions +# +# NOTE: Linux/Unix does not require any extenion for executeable files, but you +# can use an extension if you wish. We use the .exe extension for building +# executeable files so that we can use implicit rules to make the +# makefiles simpler and more portable between systems (exe also makes it +# easier for cross-compile/debugging situations). When you install +# the files to a local bin directory, you will probably want to remove +# the .exe extension. + L := .a # Libraries + E := .exe # Executables for glibc + O := .o # Objects + A := .asm # Assembler sources + S := .s # GNU assembler sources + P := .cpp # C++ sources + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := lib # LP - Library file prefix (name of file on disk) + LL := -l # Library link prefix (name of library on link command line) + LE := # Library link suffix (extension of library on link command line) + +# We use the Unix shell at all times + SHELL := /bin/sh + SHELLFLAGS := -c + +.ELSE +# Standard file DOS/Win/OS2 suffix definitions + L := .lib # Libraries +.IF $(USE_SNAP) + E := .sxe # Snap Executables + D := .sll # Snap Dynamic Link Library file +.ELSE + E := .exe # Executables + D := .dll # Dynamic Link Library file +.ENDIF + O := .obj # Objects + A := .asm # Assembler sources + P := .cpp # C++ sources + R := .res # Compiled resource file + S := .s # Assyntax.h style assembler + +# File prefix/suffix definitions. The following prefixes are defined, and are +# used primarily to abstract between the Unix style libXX.a naming convention +# and the DOS/Windows/OS2 naming convention of XX.lib. + LP := # LP - Library file prefix (name of file on disk) + LL := # Library link prefix (name of library on link command line) + LE := .lib # Library link suffix (extension of library on link command line) + +# We use the DOS/Win/OS2 style shell at all times + SHELL := $(COMSPEC) + GROUPSHELL := $(SHELL) + SHELLFLAGS := $(SWITCHAR)c + GROUPFLAGS := $(SHELLFLAGS) + SHELLMETAS := *"?<> +.IF $(OS2_SHELL) + GROUPSUFFIX := .cmd +.ELSE + GROUPSUFFIX := .bat +.ENDIF + DIRSEPSTR := \\ + DIVFILE = $(TMPFILE:s,/,\) + +.ENDIF + +# Standard Unix style shell commands. Since these do not exist on +# regular DOS/Win/OS2 installations we use our own '' versions +# instead. To boostrtap a new OS you may wish to use the regular +# unix versions. + +.IF $(BOOT_STRAP_DMAKE) + CP := cp + MD := mkdir + RM := rm + ECHO := echo +.ELSE + CP := k_cp + MD := k_md + RM := k_rm + ECHO := k_echo +.ENDIF + +# Definition of $(MAKE) macro for recursive makes. + MAKE = $(MAKECMD) $(MFLAGS) + +# Macro to install a library file + INSTALL := $(CP) + +# DMAKE uses this recipe to remove intermediate targets +.REMOVE :; $(RM) -f $< + +# Turn warnings back to previous setting. +.SILENT := $(__.SILENT) + +# We dont use TABS in our makefiles +.NOTABS := yes diff --git a/board/MAI/bios_emulator/scitech/makedefs/va32.mk b/board/MAI/bios_emulator/scitech/makedefs/va32.mk new file mode 100644 index 000000000..fbca52392 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/va32.mk @@ -0,0 +1,163 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# IBM VisualAge C++ 3.0 OS/2 32-bit version. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : VA_LIBBASE USE_OS232 USE_OS2GUI FULLSCREEN NOOPT MAX_WARN + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := icc + CPP := icc + CFLAGS := /Q /G5 /Gl+ /Fi /Si /J- /Ss+ /Sp1 /Gm+ /I. +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -F null -d__FLAT__ -dSTDCALL_MANGLE -d__NOU_VAR__ -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx +.ELSE + AS := tasm +.ENDIF + ASFLAGS := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := ilink + LDFLAGS = /noi /exepack:2 /packcode /packdata /align:32 /map /noe + RC := rc + RCFLAGS := -n -x2 + LIB := ilib + LIBFLAGS := /nologo + ILIB := implib + ILIBFLAGS := /nologo + IPFC := ipfc + IPFCFLAGS := + IBMCOBJ := 1 + +# Set the compiler warning level +.IF $(MAX_WARN) + CFLAGS += /W3 +.ELSE + CFLAGS += /W1 +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += /Ti + LDFLAGS += /DE +.ELSE +.IF $(USE_TASM) + ASFLAGS += /q +.ENDIF +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += /Gfi /O /Oi +.ELIF $(OPT_SIZE) + CFLAGS += /Gfi /O /Oc +.ELIF $(NOOPT) + CFLAGS += /O- +.END + +# Optionally turn on direct i387 FPU instructions optimised for Pentium +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +# Build 32-bit OS/2 apps +.IF $(BUILD_DLL) + CFLAGS += /Ge- /DBUILD_DLL + LDFLAGS += /DLL /NOE + ASFLAGS += -dBUILD_DLL +.ELSE +.IF $(USE_OS2GUI) + CFLAGS += -D__OS2_PM__ + LDFLAGS += /PMTYPE:PM +.ELSE +.IF $(FULLSCREEN) + LDFLAGS += /PMTYPE:NOVIO +.ELSE + LDFLAGS += /PMTYPE:VIO +.ENDIF +.ENDIF +.ENDIF + DX_ASFLAGS += -d__OS2__ + LIB_OS = os232 + +# Place to look for PMODE library files + +.IF $(USE_OS2GUI) +.IF $(USE_SDDPMDLL) +#Note: This is OK for now but might need to be changed if the GUI PM library +# were really different +PMLIB := sddpmlib.lib +.ELSE +PMLIB := pm_pm.lib +.ENDIF +.ELSE +.IF $(USE_SDDPMDLL) +PMLIB := sddpmlib.lib +.ELSE +PMLIB := pm.lib +.ENDIF +.ENDIF + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += /DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VA_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := va32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/va365.mk b/board/MAI/bios_emulator/scitech/makedefs/va365.mk new file mode 100644 index 000000000..3a2eccbbc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/va365.mk @@ -0,0 +1,151 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# IBM VisualAge C++ 3.65 OS/2 32-bit version. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : VA_LIBBASE USE_OS232 USE_OS2GUI FULLSCREEN NOOPT MAX_WARN + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := icc + CPP := icc + CFLAGS := /Q /G5l /Fi /Si /J- /Ss+ /Sp1 /Gm+ /I. +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -F null -d__FLAT__ -dSTDCALL_MANGLE -d__NOU_VAR__ -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx +.ELSE + AS := tasm +.ENDIF + ASFLAGS := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /D__NOU_VAR__ /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := ilink + LDFLAGS = /noi /exepack /packcode /packdata /align:32 /map /noe + RC := rc + RCFLAGS := /nologo + LIB := ilib + LIBFLAGS := /nologo + ILIB := implib + ILIBFLAGS := /nologo + IBMCOBJ := 1 + +# Set the compiler warning level +.IF $(MAX_WARN) + CFLAGS += /W3 +.ELSE + CFLAGS += /W1 +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += /Ti + LDFLAGS += /DE +.ELSE +.IF $(USE_TASM) + ASFLAGS += /q +.ENDIF +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += /Gfi /O /Oi +.ELIF $(OPT_SIZE) + CFLAGS += /Gfi /O /Oc +.ELIF $(NOOPT) + CFLAGS += /O- +.END + +# Optionally turn on direct i387 FPU instructions optimised for Pentium +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +# Build 32-bit OS/2 apps +.IF $(BUILD_DLL) + CFLAGS += /Gme- /DBUILD_DLL + LDFLAGS += /DLL /NOE + ASFLAGS += -dBUILD_DLL +.ELSE +.IF $(USE_OS2GUI) + CFLAGS += -D__OS2_PM__ + LDFLAGS += /PMTYPE:PM +.ELSE +.IF $(FULLSCREEN) + LDFLAGS += /PMTYPE:NOVIO +.ELSE + LDFLAGS += /PMTYPE:VIO +.ENDIF +.ENDIF +.ENDIF + DX_ASFLAGS += -d__OS2__ + LIB_OS = os232 + +# Place to look for PMODE library files + +.IF $(USE_OS2GUI) +PMLIB := pm_pm.lib +.ELSE +PMLIB := pm.lib +.ENDIF + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += /DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VA_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := va365.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/vc16.mk b/board/MAI/bios_emulator/scitech/makedefs/vc16.mk new file mode 100644 index 000000000..913bf9c3e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/vc16.mk @@ -0,0 +1,128 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Microsoft Visual C++ 1.x 16 bit version. Supports 16 bit +# DOS and Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : VC_LIBBASE + +# Default commands for compiling, assembling linking and archiving + CC := cl # C-compiler and flags + CFLAGS := /YX /w /G3 /Gs +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF + ASFLAGS := /t /mx /m /D__COMM__ /iINCLUDE /i$(SCITECH)\INCLUDE + LD := cl # Loader and flags + LDFLAGS = $(CFLAGS) + RC := rc # WIndows resource compiler + RCFLAGS := + LIB := lib # Librarian + LIBFLAGS := /NOI /NOE + ILIB := implib # Import librarian + ILIBFLAGS := /noignorecase + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += /Yd /Zi # Turn on debugging for C compiler + ASFLAGS += /zi # Turn on debugging for assembler +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += /Ox +.END + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += /FPi87 /DFPU387 + ASFLAGS += /DFPU387 /DFPU_REG_RTN +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += /DBETA + ASFLAGS += /DBETA +.END + +# Use a larger stack during linking if requested ???? How the fuck do you +# specify linker options on the CL command line????? + +.IF $(STKSIZE) +.ENDIF + +# Optionally compile for 16 bit Windows +.IF $(USE_WIN16) +.IF $(BUILD_DLL) + CFLAGS += /GD /Alfw /DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += /GA /AL +.ENDIF + DX_ASFLAGS += -D__WINDOWS16__ + LIB_OS = WIN16 +.ELSE + USE_REALDOS := 1 + CFLAGS += /AL + LIB_OS = DOS16 +.END + +# Place to look for PMODE library files + +PMLIB := pm.lib + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := vc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/vc32.mk b/board/MAI/bios_emulator/scitech/makedefs/vc32.mk new file mode 100644 index 000000000..11c9071fb --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/vc32.mk @@ -0,0 +1,226 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Microsoft Visual C++ 2.x 32 bit version. Supports Phar Lap +# TNT DOS Extender and 32 bit Windows development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : TNT_PATH VC_LIBBASE DOSSTYLE USE_TNT USE_RTTARGET MSVCDIR +.IMPORT .IGNORE : USE_VXD USE_NTDRV USE_W2KDRV NT_DDKROOT USE_RTTI USE_CPPEXCEPT + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Default commands for compiling, assembling linking and archiving + CC := cl # C-compiler and flags + CFLAGS := +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f win32 -F null -d__FLAT__ -dSTDCALL_MANGLE -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF + ASFLAGS := /t /mx /m /D__FLAT__ /DSTDCALL_MANGLE /iINCLUDE /i$(SCITECH)\INCLUDE +.ENDIF + LD := cl +.IF $(USE_WIN32) + LDFLAGS = $(CFLAGS) +.IF $(USE_NTDRV) + LDENDFLAGS = -link /INCREMENTAL:NO /DRIVER /SUBSYSTEM:NATIVE,4.00 /VERSION:4.00 /MACHINE:I386 /NODEFAULTLIB /DEBUGTYPE:CV /PDB:NONE /ALIGN:0x20 /BASE:0x10000 /ENTRY:DriverEntry@8 + #/MERGE:_page=page /MERGE:_text=.text /MERGE:.rdata=.text +.ELIF $(WIN32_GUI) + LDENDFLAGS = -link /INCREMENTAL:NO /DEF:$(@:b).def /SUBSYSTEM:WINDOWS /MACHINE:I386 /DEBUGTYPE:CV /PDB:NONE +.ELSE + LDENDFLAGS = -link /INCREMENTAL:NO /SUBSYSTEM:CONSOLE /MACHINE:I386 /DEBUGTYPE:CV /PDB:NONE +.ENDIF +.ELSE + LDFLAGS = $(CFLAGS) + LDENDFLAGS := -link -stub:$(TNT_PATH:s/\/\\)\\bin\\gotnt.exe /PDB:NONE +.ENDIF + RC := rc # Watcom resource compiler + RCFLAGS := # Mark as Win32 compatible resources + LIB := lib # Librarian + LIBFLAGS := + ILIB := lib # Import librarian + ILIBFLAGS := /MACHINE:IX86 + INTEL_X86 := 1 + NMSYM := $(SOFTICE_PATH)\nmsym.exe +.IF $(USE_NTDRV) + NMSYMFLAGS := /TRANSLATE:source,package,always /PROMPT /SOURCE:$(MSVCDIR)\crt\src\intel;$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\ntdrv +.ELSE + NMSYMFLAGS := /TRANSLATE:source,package,always /PROMPT /SOURCE:$(SCITECH)\src\pm;$(SCITECH)\src\pm\common;$(SCITECH)\src\pm\win32 +.ENDIF + +# Set the compiler warning level +.IF $(MAX_WARN) + CFLAGS += -W3 +.ELSE + CFLAGS += -W1 +.ENDIF + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += /Yd /Zi # Turn on debugging for C compiler +.IF $(USE_TASM) + ASFLAGS += /zi # Turn on debugging for assembler +.ENDIF +.ELSE +.IF $(USE_TASM) + ASFLAGS += /q # Suppress object records not needed for linking +.ENDIF +.END + +# Optionally turn on optimisations +.IF $(VC_LIBBASE) == vc5 +.IF $(OPT) + CFLAGS += /G6 /O2 /Ox /Oi- +.ELIF $(OPT_SIZE) + CFLAGS += /G6 /O1 +.END +.ELSE +.IF $(OPT) + CFLAGS += /G5 /O2 /Ox +.ELIF $(OPT_SIZE) + CFLAGS += /G5 /O1 +.END +.ENDIF + +# Optionally turn on direct i387 FPU instructions + +.IF $(FPU) + CFLAGS += /DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += /DBETA + ASFLAGS += -dBETA +.END + +# Use a larger stack during linking if requested, or use a default stack +# of 50k. The usual default stack provided by Visual C++ is *way* to small +# for real 32 bit code development. + +.IF $(USE_WIN32) + # Not necessary for Win32 code. +.ELSE +.IF $(STKSIZE) + LDENDFLAGS += /STACK:$(STKSIZE) +.ELSE + LDENDFLAGS += /STACK:51200 +.ENDIF +.ENDIF + +# DOS extender dependant flags +.IF $(USE_NTDRV) # Build 32 bit Windows NT driver + CFLAGS += /LD /Zl /Gy /Gz /GF /D__NT_DRIVER__ /D_X86_=1 /Di386=1 +.IF $(DBG) + CFLAGS += /QIf +.ENDIF + ASFLAGS += + DEF_LIBS := int64.lib ntoskrnl.lib hal.lib + DX_ASFLAGS += -d__NT_DRIVER__ +.IF $(USE_W2KDRV) # Build 32 bit Windows 2000 driver + LIB_OS = W2KDRV +.ELSE + LIB_OS = NTDRV +.ENDIF +.ELIF $(USE_WIN32) # Build 32 bit Windows NT app +.IF $(WIN32_GUI) +.ELSE + CFLAGS += -D__CONSOLE__ +.ENDIF +.IF $(BUILD_DLL) + CFLAGS += /MT /LD /DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.IF $(NO_RUNTIME) + LDENDFLAGS += /NODEFAULTLIB + CFLAGS += /Zl + DEF_LIBS := +.ELSE + DEF_LIBS := kernel32.lib user32.lib gdi32.lib advapi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib ole32.lib oleaut32.lib version.lib winspool.lib uuid.lib odbc32.lib odbccp32.lib wsock32.lib rpcrt4.lib +.ENDIF +.ELSE + CFLAGS += /MT + DEF_LIBS := kernel32.lib user32.lib gdi32.lib advapi32.lib shell32.lib winmm.lib comdlg32.lib comctl32.lib ole32.lib oleaut32.lib version.lib winspool.lib uuid.lib odbc32.lib odbccp32.lib wsock32.lib rpcrt4.lib +.ENDIF + DX_ASFLAGS += -d__WINDOWS32__ + LIB_OS = WIN32 +.ELIF $(USE_RTTARGET) + CFLAGS += -D__RTTARGET__ + DX_CFLAGS += + DX_ASFLAGS += -d__RTTARGET__ + USE_REALDOS := + LIB_OS = RTT32 + DEF_LIBS := cw32mt.lib +.ELSE + USE_TNT := 1 + USE_REALDOS := 1 + CFLAGS += /MT /D__MSDOS32__ + DX_CFLAGS += -DTNT + DX_ASFLAGS += -dTNT + LIB_OS = DOS32 + DEF_LIBS := dosx32.lib tntapi.lib +.ENDIF + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += /DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(VC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Place to look for PMODE library files + +.IF $(USE_TNT) +PMLIB := $(LIB_BASE:s/\/\\)\\tnt\\pm.lib +.ELSE +PMLIB := $(LIB_BASE:s/\/\\)\\pm.lib +.ENDIF + +# Define which file contains our rules + + RULES_MAK := vc32.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/wc16.mk b/board/MAI/bios_emulator/scitech/makedefs/wc16.mk new file mode 100644 index 000000000..e316f4c76 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/wc16.mk @@ -0,0 +1,141 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Watcom C++ 10.x 16 bit version. Supports 16-bit DOS, +# 16-bit Windows development and 16-bit OS/2 development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : WC_LIBBASE USE_WIN16 USE_OS216 USE_OS2GUI + +# Default commands for compiling, assembling linking and archiving + CC := wcc # C-compiler and flags + CPP := wpp # C++-compiler and flags + CFLAGS := -ml-zq-j-w2-s-fh -fhq +.IF $(USE_TASM32) + AS := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx # Assembler and flags +.ELSE + AS := tasm # Assembler and flags +.ENDIF + AS := tasm # Assembler and flags + ASFLAGS := /t /mx /m /D__LARGE__ /iINCLUDE /i$(SCITECH)\INCLUDE + LD := wlink # Loader and flags + LDFLAGS = + RC := wrc # Watcom resource compiler + RCFLAGS := /bt=windows + LIB := wlib # Librarian + LIBFLAGS := -q + ILIB := wlib # Import librarian + ILIBFLAGS := -c + +# Optionally turn on debugging information +.IF $(DBG) + CFLAGS += -d2 # Turn on debugging for C compiler + LIBFLAGS += -p=128 # Larger page size for libraries with debug info! + ASFLAGS += /zi # Turn on debugging for assembler + LDFLAGS += D A # Turn on debugging for linker +.ELSE + ASFLAGS += /q # Suppress object records not needed for linking +.END + +# Optionally turn on optimisations +.IF $(OPT) + CFLAGS += -onatx-5 +.ELIF $(OPT_SIZE) + CFLAGS += -onaslmr-5 +.END + +# Optionally turn on direct i387 FPU instructions optimised for Pentium + +.IF $(FPU) + CFLAGS += -fpi87-fp5-DFPU387 + ASFLAGS += -DFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -DBETA +.END + +# Use a larger stack during linking if requested + +.IF $(STKSIZE) + LDFLAGS += OP STACK=$(STKSIZE) +.ENDIF + +.IF $(USE_OS216) +.IF $(BUILD_DLL) + CFLAGS += -bd-bt=os2-DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += -bt=os2 +.ENDIF + DX_ASFLAGS += -D__OS216__ + LIB_OS = os216 +.ELIF $(USE_WIN16) +.IF $(BUILD_DLL) + CFLAGS += -bd-bt=windows-D_WINDOWS-DBUILD_DLL + ASFLAGS += -DBUILD_DLL +.ELSE + CFLAGS += -bt=windows-D_WINDOWS +.ENDIF + DX_ASFLAGS += -D__WINDOWS16__ + LIB_OS = WIN16 +.ELSE + USE_REALDOS := 1 + LIB_OS = DOS16 +.END + +# Place to look for PMODE library files + +PMLIB := pm.lib, + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(WC_LIBBASE) + LIB_DEST := $(LIB_BASE) + +# Define which file contains our rules + + RULES_MAK := wc16.mk diff --git a/board/MAI/bios_emulator/scitech/makedefs/wc32.mk b/board/MAI/bios_emulator/scitech/makedefs/wc32.mk new file mode 100644 index 000000000..e5175ca9e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/makedefs/wc32.mk @@ -0,0 +1,353 @@ +############################################################################# +# +# SciTech Multi-platform Graphics Library +# +# ======================================================================== +# +# The contents of this file are subject to the SciTech MGL Public +# License Version 1.0 (the "License"); you may not use this file +# except in compliance with the License. You may obtain a copy of +# the License at http://www.scitechsoft.com/mgl-license.txt +# +# Software distributed under the License is distributed on an +# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +# implied. See the License for the specific language governing +# rights and limitations under the License. +# +# The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +# +# The Initial Developer of the Original Code is SciTech Software, Inc. +# All Rights Reserved. +# +# ======================================================================== +# +# Descripton: Generic DMAKE startup makefile definitions file. Assumes +# that the SCITECH environment variable has been set to point +# to where all our stuff is installed. You should not need +# to change anything in this file. +# +# Watcom C++ 10.x 32 bit version. Supports Rational's DOS4GW +# DOS Extender, PMODE/W, Causeway, FlashTek's X32-VM, +# Phar Lap's TNT DOS Extender, 32-bit Windows development and +# 32-bit OS/2 development. +# +############################################################################# + +# Include standard startup script definitions +.IMPORT: SCITECH +.INCLUDE: "$(SCITECH)\makedefs\startup.mk" + +# Import enivornment variables that we use +.IMPORT .IGNORE : USE_TNT USE_X32 USE_X32VM USE_PMODEW STKCALL USE_CAUSEWAY +.IMPORT .IGNORE : USE_WIN386 USE_OS232 USE_OS2GUI WC_LIBBASE NOOPT DOSSTYLE +.IMPORT .IGNORE : OS2_SHELL USE_CODEVIEW USE_DOS32A USE_QNX4 LEAVE_LINKFILE + +# We are compiling for a 32 bit envionment + _32BIT_ := 1 + +# Setup special environment for QNX 4 (Unix'ish) +.IF $(USE_QNX4) + USE_QNX := 1 + L := .a # Libraries + LP := lib # LP - Library file prefix (name of file on disk) + LL := lib # Library link prefix (name of library on link command line) + LE := .a # Library link suffix (extension of library on link command line) +.ENDIF + +# Default commands for compiling, assembling linking and archiving + CC := wcc386 + CPP := wpp386 + CFLAGS := -zq-j-s-fpi87 +.IF $(USE_NASM) + AS := nasm + ASFLAGS := -t -f obj -d__FLAT__ -dSTDCALL_MANGLE -iINCLUDE -i$(SCITECH)\INCLUDE +.ELSE +.IF $(USE_TASM32) + AS := tasm32 + DLL_TASM := tasm32 +.ELIF $(USE_TASMX) + AS := tasmx + DLL_TASM := tasmx +.ELSE + AS := tasm + DLL_TASM := tasm +.ENDIF + ASFLAGS := /t /mx /m /w-res /w-mcp /D__FLAT__ /DSTDCALL_MANGLE /iINCLUDE /i$(SCITECH)\INCLUDE + GAS := gcc + GAS_FLAGS := -D__WATCOMC__ -D__SW_3S -D__SW_S -U__GNUC__ -UDJGPP -U__unix__ -Wall -I. -I$(SCITECH)\include -x assembler-with-cpp +.ENDIF + LD := wlink + LDFLAGS = +.IF $(USE_OS232) + RC := rc +.ELSE + RC := wrc +.ENDIF +.IF $(USE_WIN32) + RCFLAGS := -q /bt=nt +.ELIF $(USE_OS232) +.IF $(USE_OS2GUI) + CFLAGS += -D__OS2_PM__ +.ENDIF +.ELSE + RCFLAGS := -q +.ENDIF + LIB := wlib + LIBFLAGS := -q + ILIB := wlib + ILIBFLAGS := -c + INTEL_X86 := 1 + +# Set the compiler warning level +.IF $(MAX_WARN) + CFLAGS += -w4 +.ELSE + CFLAGS += -w1 +.ENDIF + +# Optionally turn on debugging information (Codeview format) +.IF $(DBG) +.IF $(USE_WIN32) +.IF $(USE_CODEVIEW) + CFLAGS += -d2 -hc + LDFLAGS += D CODEVIEW OPT CVPACK +.ELSE + CFLAGS += -d2 + LDFLAGS += D A +.ENDIF +.ELSE + CFLAGS += -d2 + LDFLAGS += D A +.ENDIF + LIBFLAGS += -p=768 +.IF $(USE_NASM) + ASFLAGS += -F borland -g +.ELSE +.IF $(USE_TASM32) + ASFLAGS += /q # TASM32 fucks up Watcom C++ debug info +.ELIF $(OS2_SHELL) + ASFLAGS += /q # TASM for OS/2 fucks up Watcom C++ debug info +.ELSE + ASFLAGS += /zi +.ENDIF +.ENDIF +.ELSE +.IF $(USE_NASM) + ASFLAGS += -F null +.ELSE + ASFLAGS += /q +.ENDIF +.END + +# Optionally turn on optimisations (with or without stack conventions) +.IF $(STKCALL) +.IF $(OPT) + CFLAGS += -onatx-5s-fp5 +.ELIF $(OPT_SIZE) + CFLAGS += -onaslmr-5s-fp5 +.ELIF $(NOOPT) + CFLAGS += -od-5s +.ELSE + CFLAGS += -3s +.END +.ELSE +.IF $(OPT) + CFLAGS += -onatx-5r-fp5 +.ELIF $(OPT_SIZE) + CFLAGS += -onaslmr-5r-fp5 +.ELIF $(NOOPT) + CFLAGS += -od-5r +.END +.END + +# Optionally turn on direct i387 FPU instructions optimised for Pentium +.IF $(FPU) + CFLAGS += -DFPU387 + ASFLAGS += -dFPU387 +.END + +# Optionally compile a beta release version of a product +.IF $(BETA) + CFLAGS += -DBETA + ASFLAGS += -dBETA +.END + +.IF $(USE_TNT) # Use Phar Lap's TNT DOS Extender + CFLAGS += -bt=nt -DTNT + ASFLAGS += -dTNT + LDFLAGS += SYS NT OP STUB=GOTNT.EXE + LIB_OS = DOS32 +.ELIF $(USE_X32VM) # Use FlashTek X-32VM DOS extender + CFLAGS += -bt=dos + LDFLAGS += SYS X32RV + DX_CFLAGS += -DX32VM + DX_ASFLAGS += -dX32VM + LIB_OS = DOS32 +.ELIF $(USE_X32) # Use FlashTek X-32 DOS extender + CFLAGS += -bt=dos + LDFLAGS += SYS X32R + DX_CFLAGS += -DX32VM + DX_ASFLAGS += -dX32VM + LIB_OS = DOS32 +.ELIF $(USE_QNX4) # Build QNX 4 app + CFLAGS += -bt=qnx386 + LDFLAGS += SYS QNX386FLAT OP CASEEXACT OP OFFSET=40k OP STACK=32k + CFLAGS += -D__QNX__ -D__UNIX__ + ASFLAGS += -d__QNX__ -d__UNIX__ + LIB_OS = QNX4 +.ELIF $(USE_OS232) +.IF $(BUILD_DLL) + CFLAGS += -bm-bd-bt=os2-sg-DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -bm-bt=os2-sg +.ENDIF + DX_ASFLAGS += -d__OS2__ + LIB_OS = os232 +.ELIF $(USE_SNAP) # Build 32 bit Snap app +.IF $(BUILD_DLL) + CFLAGS += -bm-bd-bt=nt-DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -bm-bt=nt-D_WIN32 +.ENDIF + LDFLAGS += OP nodefaultlibs +.IF $(STKCALL) + DEFLIBS := clib3s.lib,math3s.lib,noemu387.lib, +.ELSE + DEFLIBS := clib3r.lib,math3r.lib,noemu387.lib, +.ENDIF + LIB_OS = SNAP +.ELIF $(USE_WIN32) # Build 32 bit Windows NT app +.IF $(WIN32_GUI) +.ELSE + CFLAGS += -D__CONSOLE__ +.ENDIF +.IF $(BUILD_DLL) + CFLAGS += -bm-bd-bt=nt-sg-DBUILD_DLL -D_WIN32 + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -bm-bt=nt-sg-D_WIN32 +.ENDIF + DX_ASFLAGS += -d__WINDOWS32__ + LIB_OS = WIN32 + DEFLIBS := kernel32.lib,user32.lib,gdi32.lib,advapi32.lib,shell32.lib,winmm.lib,comdlg32.lib,comctl32.lib,ole32.lib,oleaut32.lib,version.lib,winspool.lib,uuid.lib,wsock32.lib,rpcrt4.lib, +.ELIF $(USE_WIN386) # Build 32 bit Win386 extended app +.IF $(BUILD_DLL) + CFLAGS += -bd-bt=windows-DBUILD_DLL + ASFLAGS += -dBUILD_DLL +.ELSE + CFLAGS += -bt=windows +.ENDIF + DX_ASFLAGS += -d__WIN386__ + LIB_OS = WIN386 +.ELIF $(USE_PMODEW) # PMODE/W + CFLAGS += -bt=dos + USE_DOS4GW := 1 + USE_REALDOS := 1 + LDFLAGS += SYS PMODEW + DX_CFLAGS += -DDOS4GW + DX_ASFLAGS += -dDOS4GW + LIB_OS = DOS32 +.ELIF $(USE_CAUSEWAY) # Causeway + CFLAGS += -bt=dos + USE_DOS4GW := 1 + USE_REALDOS := 1 + LDFLAGS += SYS CAUSEWAY + DX_CFLAGS += -DDOS4GW + DX_ASFLAGS += -dDOS4GW + LIB_OS = DOS32 +.ELIF $(USE_DOS32A) # DOS32/A + CFLAGS += -bt=dos + USE_DOS4GW := 1 + USE_REALDOS := 1 + LDFLAGS += SYS DOS32A + DX_CFLAGS += -DDOS4GW + DX_ASFLAGS += -dDOS4GW + LIB_OS = DOS32 +.ELSE # Use DOS4GW + CFLAGS += -bt=dos + USE_DOS4GW := 1 + USE_REALDOS := 1 + LDFLAGS += SYS DOS4G + DX_CFLAGS += -DDOS4GW + DX_ASFLAGS += -dDOS4GW + LIB_OS = DOS32 +.END + +# Disable linking to default C runtime library and PM library + +.IF $(NO_RUNTIME) +LDFLAGS += OP nodefaultlibs +DEFLIBS := +.ELSE + +# Place to look for PM library files + +.IF $(USE_SNAP) # Build 32 bit Snap app or dll +PMLIB := +.ELIF $(USE_WIN32) +.IF $(STKCALL) +PMLIB := spm.lib, +.ELSE +PMLIB := pm.lib, +.ENDIF +.ELIF $(USE_OS232) +.IF $(STKCALL) +.IF $(USE_OS2GUI) +PMLIB := spm_pm.lib, +.ELSE +PMLIB := spm.lib, +.ENDIF +.ELSE +.IF $(USE_OS2GUI) +PMLIB := pm_pm.lib, +.ELSE +PMLIB := pm.lib, +.ENDIF +.ENDIF +.ELIF $(USE_QNX4) +.IF $(STKCALL) +PMLIB := libspm.a, +.ELSE +PMLIB := libpm.a, +.ENDIF +.ELIF $(USE_TNT) +.IF $(STKCALL) +PMLIB := tnt\spm.lib, +.ELSE +PMLIB := tnt\pm.lib, +.ENDIF +.ELIF $(USE_X32) +.IF $(STKCALL) +PMLIB := x32\spm.lib, +.ELSE +PMLIB := x32\pm.lib, +.ENDIF +.ELSE +.IF $(STKCALL) +PMLIB := dos4gw\spm.lib, +.ELSE +PMLIB := dos4gw\pm.lib, +.ENDIF +.ENDIF +.ENDIF + +# Define the base directory for library files + +.IF $(CHECKED) +LIB_BASE_DIR := $(SCITECH_LIB)\lib\debug +CFLAGS += -DCHECKED=1 +.ELSE +LIB_BASE_DIR := $(SCITECH_LIB)\lib\release +.ENDIF + +# Define where to install library files + LIB_BASE := $(LIB_BASE_DIR)\$(LIB_OS)\$(WC_LIBBASE) + LIB_DEST := $(LIB_BASE) + + LDFLAGS += op map + +# Define which file contains our rules + + RULES_MAK := wc32.mk diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/besys.c b/board/MAI/bios_emulator/scitech/src/biosemu/besys.c new file mode 100644 index 000000000..1512ce9bf --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/besys.c @@ -0,0 +1,408 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes BIOS emulator I/O and memory access +* functions. +* +****************************************************************************/ + +#include "biosemui.h" + +/*------------------------------- Macros ----------------------------------*/ + +/* Macros to read and write values to x86 bus memory. Replace these as + * necessary if you need to do something special to access memory over + * the bus on a particular processor family. + */ + +#define readb(base,off) *((u8*)((u32)(base) + (off))) +#define readw(base,off) *((u16*)((u32)(base) + (off))) +#define readl(base,off) *((u32*)((u32)(base) + (off))) +#define writeb(v,base,off) *((u8*)((u32)(base) + (off))) = (v) +#define writew(v,base,off) *((u16*)((u32)(base) + (off))) = (v) +#define writel(v,base,off) *((u32*)((u32)(base) + (off))) = (v) + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef DEBUG +# define DEBUG_MEM() (M.x86.debug & DEBUG_MEM_TRACE_F) +#else +# define DEBUG_MEM() +#endif + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Byte value read from emulator memory. + +REMARKS: +Reads a byte value from the emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +u8 X86API BE_rdb( + u32 addr) +{ + u8 val = 0; + + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { + val = *(u8*)(_BE_env.biosmem_base + addr - 0xC0000); + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { + val = readb(_BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size - 1) { +DB( printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { + val = *(u8*)(M.mem_base + addr); + } +DB( if (DEBUG_MEM()) + printk("%#08x 1 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Word value read from emulator memory. + +REMARKS: +Reads a word value from the emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +u16 X86API BE_rdw( + u32 addr) +{ + u16 val = 0; + + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + addr -= 0xC0000; + val = ( *(u8*)(_BE_env.biosmem_base + addr) | + (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8)); + } + else +#endif + val = *(u16*)(_BE_env.biosmem_base + addr - 0xC0000); + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + addr -= 0xA0000; + val = ( readb(_BE_env.busmem_base, addr) | + (readb(_BE_env.busmem_base, addr + 1) << 8)); + } + else +#endif + val = readw(_BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size - 2) { +DB( printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + val = ( *(u8*)(M.mem_base + addr) | + (*(u8*)(M.mem_base + addr + 1) << 8)); + } + else +#endif + val = *(u16*)(M.mem_base + addr); + } +DB( if (DEBUG_MEM()) + printk("%#08x 2 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Long value read from emulator memory. + +REMARKS: +Reads a long value from the emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +u32 X86API BE_rdl( + u32 addr) +{ + u32 val = 0; + + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + addr -= 0xC0000; + val = ( *(u8*)(_BE_env.biosmem_base + addr + 0) | + (*(u8*)(_BE_env.biosmem_base + addr + 1) << 8) | + (*(u8*)(_BE_env.biosmem_base + addr + 2) << 16) | + (*(u8*)(_BE_env.biosmem_base + addr + 3) << 24)); + } + else +#endif + val = *(u32*)(_BE_env.biosmem_base + addr - 0xC0000); + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + addr -= 0xA0000; + val = ( readb(_BE_env.busmem_base, addr) | + (readb(_BE_env.busmem_base, addr + 1) << 8) | + (readb(_BE_env.busmem_base, addr + 2) << 16) | + (readb(_BE_env.busmem_base, addr + 3) << 24)); + } + else +#endif + val = readl(_BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size - 4) { +DB( printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + val = ( *(u8*)(M.mem_base + addr + 0) | + (*(u8*)(M.mem_base + addr + 1) << 8) | + (*(u8*)(M.mem_base + addr + 2) << 16) | + (*(u8*)(M.mem_base + addr + 3) << 24)); + } + else +#endif + val = *(u32*)(M.mem_base + addr); + } +DB( if (DEBUG_MEM()) + printk("%#08x 4 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a byte value to emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +void X86API BE_wrb( + u32 addr, + u8 val) +{ +DB( if (DEBUG_MEM()) + printk("%#08x 1 <- %#x\n", addr, val);) + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { + *(u8*)(_BE_env.biosmem_base + addr - 0xC0000) = val; + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { + writeb(val, _BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size-1) { +DB( printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { + *(u8*)(M.mem_base + addr) = val; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a word value to emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +void X86API BE_wrw( + u32 addr, + u16 val) +{ +DB( if (DEBUG_MEM()) + printk("%#08x 2 <- %#x\n", addr, val);) + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + addr -= 0xC0000; + *(u8*)(_BE_env.biosmem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(_BE_env.biosmem_base + addr + 1) = (val >> 8) & 0xff; + } + else +#endif + *(u16*)(_BE_env.biosmem_base + addr - 0xC0000) = val; + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + addr -= 0xA0000; + writeb(val >> 0, _BE_env.busmem_base, addr); + writeb(val >> 8, _BE_env.busmem_base, addr + 1); + } + else +#endif + writew(val, _BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size-2) { +DB( printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + } + else +#endif + *(u16*)(M.mem_base + addr) = val; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a long value to emulator memory. We have three distinct memory +regions that are handled differently, which this function handles. +****************************************************************************/ +void X86API BE_wrl( + u32 addr, + u32 val) +{ +DB( if (DEBUG_MEM()) + printk("%#08x 4 <- %#x\n", addr, val);) + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + addr -= 0xC0000; + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else +#endif + *(u32*)(M.mem_base + addr - 0xC0000) = val; + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + addr -= 0xA0000; + writeb(val >> 0, _BE_env.busmem_base, addr); + writeb(val >> 8, _BE_env.busmem_base, addr + 1); + writeb(val >> 16, _BE_env.busmem_base, addr + 1); + writeb(val >> 24, _BE_env.busmem_base, addr + 1); + } + else +#endif + writel(val, _BE_env.busmem_base, addr - 0xA0000); + } + else if (addr > M.mem_size-4) { +DB( printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + else { +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else +#endif + *(u32*)(M.mem_base + addr) = val; + } +} + +/* Debug functions to do ISA/PCI bus port I/O */ + +#ifdef DEBUG +#define DEBUG_IO() (M.x86.debug & DEBUG_IO_TRACE_F) + +u8 X86API BE_inb(int port) +{ + u8 val = PM_inpb(port); + if (DEBUG_IO()) + printk("%04X:%04X: inb.%04X -> %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + return val; +} + +u16 X86API BE_inw(int port) +{ + u16 val = PM_inpw(port); + if (DEBUG_IO()) + printk("%04X:%04X: inw.%04X -> %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + return val; +} + +u32 X86API BE_inl(int port) +{ + u32 val = PM_inpd(port); + if (DEBUG_IO()) + printk("%04X:%04X: inl.%04X -> %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + return val; +} + +void X86API BE_outb(int port, u8 val) +{ + if (DEBUG_IO()) + printk("%04X:%04X: outb.%04X <- %02X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + PM_outpb(port,val); +} + +void X86API BE_outw(int port, u16 val) +{ + if (DEBUG_IO()) + printk("%04X:%04X: outw.%04X <- %04X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + PM_outpw(port,val); +} + +void X86API BE_outl(int port, u32 val) +{ + if (DEBUG_IO()) + printk("%04X:%04X: outl.%04X <- %08X\n",M.x86.saved_cs, M.x86.saved_ip, (ushort)port, val); + PM_outpd(port,val); +} +#endif diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/bios.c b/board/MAI/bios_emulator/scitech/src/biosemu/bios.c new file mode 100644 index 000000000..c0f4a4b18 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/bios.c @@ -0,0 +1,250 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Module implementing the BIOS specific functions. +* +****************************************************************************/ + +#include "biosemui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +Handler for undefined interrupts. +****************************************************************************/ +static void X86API undefined_intr( + int intno) +{ + if (BE_rdw(intno * 4 + 2) == BIOS_SEG) + printk("biosEmu: undefined interrupt %xh called!\n",intno); + else + X86EMU_prepareForInt(intno); +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +This function handles the default system BIOS Int 10h (the default is stored +in the Int 42h vector by the system BIOS at bootup). We only need to handle +a small number of special functions used by the BIOS during POST time. +****************************************************************************/ +static void X86API int42( + int intno) +{ + if (M.x86.R_AH == 0x12 && M.x86.R_BL == 0x32) { + if (M.x86.R_AL == 0) { + /* Enable CPU accesses to video memory */ + PM_outpb(0x3c2, PM_inpb(0x3cc) | (u8)0x02); + return; + } + else if (M.x86.R_AL == 1) { + /* Disable CPU accesses to video memory */ + PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8)~0x02); + return; + } +#ifdef DEBUG + else { + printk("biosEmu/bios.int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n",M.x86.R_AL); + } +#endif + } +#ifdef DEBUG + else { + printk("biosEmu/bios.int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n",M.x86.R_AH, M.x86.R_AL, M.x86.R_BL); + } +#endif +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +This function handles the default system BIOS Int 10h. If the POST code +has not yet re-vectored the Int 10h BIOS interrupt vector, we handle this +by simply calling the int42 interrupt handler above. Very early in the +BIOS POST process, the vector gets replaced and we simply let the real +mode interrupt handler process the interrupt. +****************************************************************************/ +static void X86API int10( + int intno) +{ + if (BE_rdw(intno * 4 + 2) == BIOS_SEG) + int42(intno); + else + X86EMU_prepareForInt(intno); +} + +/* Result codes returned by the PCI BIOS */ + +#define SUCCESSFUL 0x00 +#define FUNC_NOT_SUPPORT 0x81 +#define BAD_VENDOR_ID 0x83 +#define DEVICE_NOT_FOUND 0x86 +#define BAD_REGISTER_NUMBER 0x87 +#define SET_FAILED 0x88 +#define BUFFER_TOO_SMALL 0x89 + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number being serviced + +REMARKS: +This function handles the default Int 1Ah interrupt handler for the real +mode code, which provides support for the PCI BIOS functions. Since we only +want to allow the real mode BIOS code *only* see the PCI config space for +its own device, we only return information for the specific PCI config +space that we have passed in to the init function. This solves problems +when using the BIOS to warm boot a secondary adapter when there is an +identical adapter before it on the bus (some BIOS'es get confused in this +case). +****************************************************************************/ +static void X86API int1A( + unused) +{ + u16 pciSlot; + + /* Fail if no PCI device information has been registered */ + if (!_BE_env.vgaInfo.pciInfo) + return; + pciSlot = (u16)(_BE_env.vgaInfo.pciInfo->slot.i >> 8); + switch (M.x86.R_AX) { + case 0xB101: /* PCI bios present? */ + M.x86.R_AL = 0x00; /* no config space/special cycle generation support */ + M.x86.R_EDX = 0x20494350; /* " ICP" */ + M.x86.R_BX = 0x0210; /* Version 2.10 */ + M.x86.R_CL = 0; /* Max bus number in system */ + CLEAR_FLAG(F_CF); + break; + case 0xB102: /* Find PCI device */ + M.x86.R_AH = DEVICE_NOT_FOUND; + if (M.x86.R_DX == _BE_env.vgaInfo.pciInfo->VendorID && + M.x86.R_CX == _BE_env.vgaInfo.pciInfo->DeviceID && + M.x86.R_SI == 0) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_BX = pciSlot; + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB103: /* Find PCI class code */ + M.x86.R_AH = DEVICE_NOT_FOUND; + if (M.x86.R_CL == _BE_env.vgaInfo.pciInfo->Interface && + M.x86.R_CH == _BE_env.vgaInfo.pciInfo->SubClass && + (u8)(M.x86.R_ECX >> 16) == _BE_env.vgaInfo.pciInfo->BaseClass) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_BX = pciSlot; + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB108: /* Read configuration byte */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_CL = (u8)PCI_accessReg(M.x86.R_DI,0,PCI_READ_BYTE,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB109: /* Read configuration word */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_CX = (u16)PCI_accessReg(M.x86.R_DI,0,PCI_READ_WORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10A: /* Read configuration dword */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + M.x86.R_ECX = (u32)PCI_accessReg(M.x86.R_DI,0,PCI_READ_DWORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10B: /* Write configuration byte */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + PCI_accessReg(M.x86.R_DI,M.x86.R_CL,PCI_WRITE_BYTE,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10C: /* Write configuration word */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + PCI_accessReg(M.x86.R_DI,M.x86.R_CX,PCI_WRITE_WORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + case 0xB10D: /* Write configuration dword */ + M.x86.R_AH = BAD_REGISTER_NUMBER; + if (M.x86.R_BX == pciSlot) { + M.x86.R_AH = SUCCESSFUL; + PCI_accessReg(M.x86.R_DI,M.x86.R_ECX,PCI_WRITE_DWORD,_BE_env.vgaInfo.pciInfo); + } + CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF); + break; + default: + printk("biosEmu/bios.int1a: unknown function AX=%#04x\n", M.x86.R_AX); + } +} + +/**************************************************************************** +REMARKS: +This function initialises the BIOS emulation functions for the specific +PCI display device. We insulate the real mode BIOS from any other devices +on the bus, so that it will work correctly thinking that it is the only +device present on the bus (ie: avoiding any adapters present in from of +the device we are trying to control). +****************************************************************************/ +void _BE_bios_init( + u32 *intrTab) +{ + int i; + X86EMU_intrFuncs bios_intr_tab[256]; + + for (i = 0; i < 256; ++i) { + intrTab[i] = BIOS_SEG << 16; + bios_intr_tab[i] = undefined_intr; + } + bios_intr_tab[0x10] = int10; + bios_intr_tab[0x1A] = int1A; + bios_intr_tab[0x42] = int42; + X86EMU_setupIntrFuncs(bios_intr_tab); +} diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c b/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c new file mode 100644 index 000000000..0052709cc --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/biosemu.c @@ -0,0 +1,445 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Module implementing the system specific functions. This +* module is always compiled and linked in the OS depedent +* libraries, and never in a binary portable driver. +* +****************************************************************************/ + +#include "biosemui.h" +#include +#include + +/*------------------------- Global Variables ------------------------------*/ + +BE_sysEnv _BE_env; +#ifdef __DRIVER__ +PM_imports _VARAPI _PM_imports; +#endif +static X86EMU_memFuncs _BE_mem = { + BE_rdb, + BE_rdw, + BE_rdl, + BE_wrb, + BE_wrw, + BE_wrl, + }; +#ifdef DEBUG +static X86EMU_pioFuncs _BE_pio = { + BE_inb, + BE_inw, + BE_inl, + BE_outb, + BE_outw, + BE_outl, + }; +#else +static X86EMU_pioFuncs _BE_pio = { + (void*)PM_inpb, + (void*)PM_inpw, + (void*)PM_inpd, + (void*)PM_outpb, + (void*)PM_outpw, + (void*)PM_outpd, + }; +#endif + +/*-------------------------- Implementation -------------------------------*/ + +#define OFF(addr) (u16)(((addr) >> 0) & 0xffff) +#define SEG(addr) (u16)(((addr) >> 4) & 0xf000) + +/**************************************************************************** +PARAMETERS: +debugFlags - Flags to enable debugging options (debug builds only) +memSize - Amount of memory to allocate for real mode machine +info - Pointer to default VGA device information + +REMARKS: +This functions initialises the BElib, and uses the passed in +BIOS image as the BIOS that is used and emulated at 0xC0000. +****************************************************************************/ +ibool PMAPI BE_init( + u32 debugFlags, + int memSize, + BE_VGAInfo *info) +{ +#ifndef __DRIVER__ + PM_init(); +#endif + memset(&M,0,sizeof(M)); + if (memSize < 20480) + PM_fatalError("Emulator requires at least 20Kb of memory!\n"); + if ((M.mem_base = (unsigned long)malloc(memSize)) == NULL) + PM_fatalError("Out of memory!"); + M.mem_size = memSize; + _BE_env.busmem_base = (ulong)PM_mapPhysicalAddr(0xA0000,0x5FFFF,true); + M.x86.debug = debugFlags; + _BE_bios_init((u32*)info->LowMem); + X86EMU_setupMemFuncs(&_BE_mem); + X86EMU_setupPioFuncs(&_BE_pio); + BE_setVGA(info); + return true; +} + +/**************************************************************************** +PARAMETERS: +debugFlags - Flags to enable debugging options (debug builds only) + +REMARKS: +This function allows the application to enable logging and debug flags +on a function call basis, so we can specifically enable logging only +for specific functions that are causing problems in debug mode. +****************************************************************************/ +void PMAPI BE_setDebugFlags( + u32 debugFlags) +{ + M.x86.debug = debugFlags; +} + +/**************************************************************************** +PARAMETERS: +info - Pointer to VGA device information to make current + +REMARKS: +This function sets the VGA BIOS functions in the emulator to point to the +specific VGA BIOS in use. This includes swapping the BIOS interrupt +vectors, BIOS image and BIOS data area to the new BIOS. This allows the +real mode BIOS to be swapped without resetting the entire emulator. +****************************************************************************/ +void PMAPI BE_setVGA( + BE_VGAInfo *info) +{ + _BE_env.vgaInfo.pciInfo = info->pciInfo; + _BE_env.vgaInfo.BIOSImage = info->BIOSImage; + if (info->BIOSImage) { + _BE_env.biosmem_base = (ulong)info->BIOSImage; + _BE_env.biosmem_limit = 0xC0000 + info->BIOSImageLen-1; + } + else { + _BE_env.biosmem_base = _BE_env.busmem_base + 0x20000; + _BE_env.biosmem_limit = 0xC7FFF; + } + if (*((u32*)info->LowMem) == 0) + _BE_bios_init((u32*)info->LowMem); + memcpy((u8*)M.mem_base,info->LowMem,sizeof(info->LowMem)); +} + +/**************************************************************************** +PARAMETERS: +info - Pointer to VGA device information to retrieve current + +REMARKS: +This function returns the VGA BIOS functions currently active in the +emulator, so they can be restored at a later date. +****************************************************************************/ +void PMAPI BE_getVGA( + BE_VGAInfo *info) +{ + info->pciInfo = _BE_env.vgaInfo.pciInfo; + info->BIOSImage = _BE_env.vgaInfo.BIOSImage; + memcpy(info->LowMem,(u8*)M.mem_base,sizeof(info->LowMem)); +} + +/**************************************************************************** +PARAMETERS: +r_seg - Segment for pointer to convert +r_off - Offset for pointer to convert + +REMARKS: +This function maps a real mode pointer in the emulator memory to a protected +mode pointer that can be used to directly access the memory. + +NOTE: The memory is *always* in little endian format, son on non-x86 + systems you will need to do endian translations to access this + memory. +****************************************************************************/ +void * PMAPI BE_mapRealPointer( + uint r_seg, + uint r_off) +{ + u32 addr = ((u32)r_seg << 4) + r_off; + + if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) { + return (void*)(_BE_env.biosmem_base + addr - 0xC0000); + } + else if (addr >= 0xA0000 && addr <= 0xFFFFF) { + return (void*)(_BE_env.busmem_base + addr - 0xA0000); + } + return (void*)(M.mem_base + addr); +} + +/**************************************************************************** +PARAMETERS: +len - Return the length of the VESA buffer +rseg - Place to store VESA buffer segment +roff - Place to store VESA buffer offset + +REMARKS: +This function returns the address of the VESA transfer buffer in real +mode emulator memory. The VESA transfer buffer is always 1024 bytes long, +and located at 15Kb into the start of the real mode memory (16Kb is where +we put the real mode code we execute for issuing interrupts). + +NOTE: The memory is *always* in little endian format, son on non-x86 + systems you will need to do endian translations to access this + memory. +****************************************************************************/ +void * PMAPI BE_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + *len = 1024; + *rseg = SEG(0x03C00); + *roff = OFF(0x03C00); + return (void*)(M.mem_base + ((u32)*rseg << 4) + *roff); +} + +/**************************************************************************** +REMARKS: +Cleans up and exits the emulator. +****************************************************************************/ +void PMAPI BE_exit(void) +{ + free((void*)M.mem_base); + PM_freePhysicalAddr((void*)_BE_env.busmem_base,0x5FFFF); +} + +/**************************************************************************** +PARAMETERS: +seg - Segment of code to call +off - Offset of code to call +regs - Real mode registers to load +sregs - Real mode segment registers to load + +REMARKS: +This functions calls a real mode far function at the specified address, +and loads all the x86 registers from the passed in registers structure. +On exit the registers returned from the call are returned in the same +structures. +****************************************************************************/ +void PMAPI BE_callRealMode( + uint seg, + uint off, + RMREGS *regs, + RMSREGS *sregs) +{ + M.x86.R_EAX = regs->e.eax; + M.x86.R_EBX = regs->e.ebx; + M.x86.R_ECX = regs->e.ecx; + M.x86.R_EDX = regs->e.edx; + M.x86.R_ESI = regs->e.esi; + M.x86.R_EDI = regs->e.edi; + M.x86.R_DS = sregs->ds; + M.x86.R_ES = sregs->es; + M.x86.R_FS = sregs->fs; + M.x86.R_GS = sregs->gs; + M.x86.R_CS = (u16)seg; + M.x86.R_IP = (u16)off; + M.x86.R_SS = SEG(M.mem_size - 1); + M.x86.R_SP = OFF(M.mem_size - 1); + X86EMU_exec(); + regs->e.cflag = M.x86.R_EFLG & F_CF; + regs->e.eax = M.x86.R_EAX; + regs->e.ebx = M.x86.R_EBX; + regs->e.ecx = M.x86.R_ECX; + regs->e.edx = M.x86.R_EDX; + regs->e.esi = M.x86.R_ESI; + regs->e.edi = M.x86.R_EDI; + sregs->ds = M.x86.R_DS; + sregs->es = M.x86.R_ES; + sregs->fs = M.x86.R_FS; + sregs->gs = M.x86.R_GS; +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number to execute +in - Real mode registers to load +out - Place to store resulting real mode registers + +REMARKS: +This functions calls a real mode interrupt function at the specified address, +and loads all the x86 registers from the passed in registers structure. +On exit the registers returned from the call are returned in out stucture. +****************************************************************************/ +int PMAPI BE_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + M.x86.R_EAX = in->e.eax; + M.x86.R_EBX = in->e.ebx; + M.x86.R_ECX = in->e.ecx; + M.x86.R_EDX = in->e.edx; + M.x86.R_ESI = in->e.esi; + M.x86.R_EDI = in->e.edi; + ((u8*)M.mem_base)[0x4000] = 0xCD; + ((u8*)M.mem_base)[0x4001] = (u8)intno; + ((u8*)M.mem_base)[0x4002] = 0xC3; + M.x86.R_CS = SEG(0x04000); + M.x86.R_IP = OFF(0x04000); + M.x86.R_SS = SEG(M.mem_size - 1); + M.x86.R_SP = OFF(M.mem_size - 1); + X86EMU_exec(); + out->e.cflag = M.x86.R_EFLG & F_CF; + out->e.eax = M.x86.R_EAX; + out->e.ebx = M.x86.R_EBX; + out->e.ecx = M.x86.R_ECX; + out->e.edx = M.x86.R_EDX; + out->e.esi = M.x86.R_ESI; + out->e.edi = M.x86.R_EDI; + return out->x.ax; +} + +/**************************************************************************** +PARAMETERS: +intno - Interrupt number to execute +in - Real mode registers to load +out - Place to store resulting real mode registers +sregs - Real mode segment registers to load + +REMARKS: +This functions calls a real mode interrupt function at the specified address, +and loads all the x86 registers from the passed in registers structure. +On exit the registers returned from the call are returned in out stucture. +****************************************************************************/ +int PMAPI BE_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + M.x86.R_EAX = in->e.eax; + M.x86.R_EBX = in->e.ebx; + M.x86.R_ECX = in->e.ecx; + M.x86.R_EDX = in->e.edx; + M.x86.R_ESI = in->e.esi; + M.x86.R_EDI = in->e.edi; + M.x86.R_DS = sregs->ds; + M.x86.R_ES = sregs->es; + M.x86.R_FS = sregs->fs; + M.x86.R_GS = sregs->gs; + ((u8*)M.mem_base)[0x4000] = 0xCD; + ((u8*)M.mem_base)[0x4001] = (u8)intno; + ((u8*)M.mem_base)[0x4002] = 0xC3; + M.x86.R_CS = SEG(0x04000); + M.x86.R_IP = OFF(0x04000); + M.x86.R_SS = SEG(M.mem_size - 1); + M.x86.R_SP = OFF(M.mem_size - 1); + X86EMU_exec(); + out->e.cflag = M.x86.R_EFLG & F_CF; + out->e.eax = M.x86.R_EAX; + out->e.ebx = M.x86.R_EBX; + out->e.ecx = M.x86.R_ECX; + out->e.edx = M.x86.R_EDX; + out->e.esi = M.x86.R_ESI; + out->e.edi = M.x86.R_EDI; + sregs->ds = M.x86.R_DS; + sregs->es = M.x86.R_ES; + sregs->fs = M.x86.R_FS; + sregs->gs = M.x86.R_GS; + return out->x.ax; +} + +#ifdef __DRIVER__ + +/**************************************************************************** +REMARKS: +Empty log function for binary portable DLL. The BPD is compiled without +debug information, so very little is logged anyway so it is simpler this +way. +****************************************************************************/ +void printk(const char *msg, ...) +{ +} + +/**************************************************************************** +REMARKS: +Fatal error handler called when a non-imported function is called by the +driver. We leave this to a runtime error so that older applications and +shell drivers will work with newer bpd drivers provided no newer functions +are required by the driver itself. If they are, the application or shell +driver needs to be recompiled. +****************************************************************************/ +static void _PM_fatalErrorHandler(void) +{ + PM_fatalError("Unsupported PM_imports import function called! Please re-compile!\n"); +} + +/**************************************************************************** +PARAMETERS: +beImp - BE library imports +beImp - Generic emulator imports + +RETURNS: +Pointer to exported function list + +REMARKS: +This function initialises the BIOS emulator library and returns the list of +loader library exported functions. +{secret} +****************************************************************************/ +BE_exports * _CEXPORT BE_initLibrary( + PM_imports *pmImp) +{ + static BE_exports _BE_exports = { + sizeof(BE_exports), + BE_init, + BE_setVGA, + BE_getVGA, + BE_mapRealPointer, + BE_getVESABuf, + BE_callRealMode, + BE_int86, + BE_int86x, + NULL, + BE_exit, + }; + int i,max; + ulong *p; + + /* Initialize all default imports to point to fatal error handler */ + /* for upwards compatibility. */ + max = sizeof(_PM_imports)/sizeof(BE_initLibrary_t); + for (i = 0,p = (ulong*)&_PM_imports; i < max; i++) + *p++ = (ulong)_PM_fatalErrorHandler; + + /* Now copy all our imported functions */ + memcpy(&_PM_imports,pmImp,MIN(sizeof(_PM_imports),pmImp->dwSize)); + return &_BE_exports; +} + +#endif /* __DRIVER__ */ diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h b/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h new file mode 100644 index 000000000..23edebc95 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/biosemui.h @@ -0,0 +1,79 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Internal header file for the BIOS emulator library. +* +****************************************************************************/ + +#ifndef __BIOSEMUI_H +#define __BIOSEMUI_H + +#include + +/*---------------------- Macros and type definitions ----------------------*/ + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +#define BIOS_SEG 0xfff0 + +#define M _X86EMU_env + +/*-------------------------- Function Prototypes --------------------------*/ + +/* bios.c */ + +void _BE_bios_init(u32 *intrTab); +void _BE_setup_funcs(void); + +/* besys.c */ + +u8 X86API BE_rdb(u32 addr); +u16 X86API BE_rdw(u32 addr); +u32 X86API BE_rdl(u32 addr); +void X86API BE_wrb(u32 addr,u8 val); +void X86API BE_wrw(u32 addr,u16 val); +void X86API BE_wrl(u32 addr,u32 val); +#ifdef DEBUG +u8 X86API BE_inb(int port); +u16 X86API BE_inw(int port); +u32 X86API BE_inl(int port); +void X86API BE_outb(int port, u8 val); +void X86API BE_outw(int port, u16 val); +void X86API BE_outl(int port, u32 val); +#endif + +#endif /* __BIOSEMUI_H */ diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/makefile b/board/MAI/bios_emulator/scitech/src/biosemu/makefile new file mode 100644 index 000000000..80730b299 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/makefile @@ -0,0 +1,99 @@ +############################################################################# +# +# BIOS emulator and interface +# to Realmode X86 Emulator Library +# +# Copyright (C) 1996-1999 SciTech Software, Inc. +# +# ======================================================================== +# +# Permission to use, copy, modify, distribute, and sell this software and +# its documentation for any purpose is hereby granted without fee, +# provided that the above copyright notice appear in all copies and that +# both that copyright notice and this permission notice appear in +# supporting documentation, and that the name of the authors not be used +# in advertising or publicity pertaining to distribution of the software +# without specific, written prior permission. The authors makes no +# representations about the suitability of this software for any purpose. +# It is provided "as is" without express or implied warranty. +# +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# ======================================================================== +# +# Descripton: Generic makefile for the x86emu library. Requires +# the SciTech Software makefile definitions package to be +# installed, which uses the DMAKE make program. +# +############################################################################# + +.IMPORT .IGNORE: DEBUG + +#---------------------------------------------------------------------------- +# Define the lists of object files +#---------------------------------------------------------------------------- + +DLL_OBJS = dllstart$O _pm_imp$O +BIOS_OBJS = biosemu$O bios$O besys$O +X86_OBJS = sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O +CFLAGS += -DSCITECH -I$(SCITECH)\src\x86emu + +.IF $(BUILD_DLL) + +CFLAGS += -I$(PRIVATE)\include\drvlib -I$(SCITECH)\include\drvlib -D__DRIVER__ +ASFLAGS += -d__DRIVER__ +EXELIBS = drvlib$L + +.ELSE + +.IF $(DEBUG) +CFLAGS += -DDEBUG +.ENDIF +OBJECTS = $(BIOS_OBJS) $(X86_OBJS) +LIBCLEAN = *.dll *.lib *.a +LIBFILE = $(LP)biosemu$L + +.ENDIF + +#---------------------------------------------------------------------------- +# Sample test programs +#---------------------------------------------------------------------------- + +all: $(LIBFILE) warmboot$E + +warmboot$E: warmboot$O $(LIBFILE) + +#---------------------------------------------------------------------------- +# Target to build the Binary Portable DLL target +#---------------------------------------------------------------------------- + +biosemu.dll: $(DLL_OBJS) $(BIOS_OBJS) $(X86_OBJS) + +#---------------------------------------------------------------------------- +# Target to build all Intel binary drivers +#---------------------------------------------------------------------------- + +.PHONY mkdrv: + @build wc11-w32 biosemu.dll -u BUILD_DLL=1 NO_RUNTIME=1 OPT=1 + @$(CP) biosemu.dll $(PRIVATE)\nucleus\graphics\biosemu.bpd + @dmake cleanexe + +.PHONY db: + @build wc11-w32 biosemu.dll BUILD_DLL=1 NO_RUNTIME=1 OPT=1 + @$(CP) biosemu.dll $(PRIVATE)\nucleus\graphics\biosemu.bpd + +#---------------------------------------------------------------------------- +# Define the list of object files to create dependency information for +#---------------------------------------------------------------------------- + +DEPEND_OBJ = warmboot$O $(BIOS_OBJS) $(X86_OBJS) $(DLL_OBJS) +DEPEND_SRC = $(SCITECH)/src/x86emu;$(PRIVATE)/src/common +.SOURCE: $(SCITECH)/src/x86emu $(PRIVATE)/src/common + +.INCLUDE: "$(SCITECH)/makedefs/common.mk" diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross b/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross new file mode 100644 index 000000000..914100307 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/makefile.cross @@ -0,0 +1,10 @@ +CC = ppc-elf32-gcc +AR = ppc-elf32-ar + +CFLAGS = -D__DRIVER__ -I../../include -DDEBUG -I. + +BIOS_OBJS = biosemu.o bios.o besys.o +X86_OBJS = sys.o decode.o ops.o prim_ops.o fpu.o debug.o + +libbios.a: $(BIOS_OBJS) + $(AR) rcs libbios.a $(BIOS_OBJS) \ No newline at end of file diff --git a/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c b/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c new file mode 100644 index 000000000..98d5fb8a6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/biosemu/warmboot.c @@ -0,0 +1,569 @@ +/**************************************************************************** +* +* BIOS emulator and interface +* to Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Module to implement warm booting of all PCI/AGP controllers +* on the bus. We use the x86 real mode emulator to run the +* BIOS on the primary and secondary controllers to bring +* the cards up. +* +****************************************************************************/ + +#include +#include +#include +#include +#include "biosemu.h" +#ifndef _MAX_PATH +#define _MAX_PATH 256 +#endif + +/*------------------------- Global Variables ------------------------------*/ + +static PCIDeviceInfo PCI[MAX_PCI_DEVICES]; +static int NumPCI = -1; +static int BridgeIndex[MAX_PCI_DEVICES] = {0}; +static int NumBridges; +static PCIBridgeInfo *AGPBridge = NULL; +static int DeviceIndex[MAX_PCI_DEVICES] = {0}; +static int NumDevices; +static u32 debugFlags = 0; +static BE_VGAInfo VGAInfo[MAX_PCI_DEVICES] = {{0}}; +static ibool useV86 = false; +static ibool forcePost = false; + +/* Length of the BIOS image */ + +#define MAX_BIOSLEN (64 * 1024L) +#define FINAL_BIOSLEN (32 * 1024L) + +/* Macro to determine if the VGA is enabled and responding */ + +#define VGA_NOT_ACTIVE() (forcePost || (PM_inpb(0x3CC) == 0xFF) || ((PM_inpb(0x3CC) & 0x2) == 0)) + +#define ENABLE_DEVICE(device) \ + PCI_writePCIRegB(0x4,PCI[DeviceIndex[device]].Command | 0x7,device) + +#define DISABLE_DEVICE(device) \ + PCI_writePCIRegB(0x4,0,device) + +/* Macros to enable and disable AGP VGA resources */ + +#define ENABLE_AGP_VGA() \ + PCI_accessReg(0x3E,AGPBridge->BridgeControl | 0x8,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge) + +#define DISABLE_AGP_VGA() \ + PCI_accessReg(0x3E,AGPBridge->BridgeControl & ~0x8,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge) + +#define RESTORE_AGP_VGA() \ + PCI_accessReg(0x3E,AGPBridge->BridgeControl,PCI_WRITE_WORD,(PCIDeviceInfo*)AGPBridge) + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +RETURNS: +The address to use to map the secondary BIOS (PCI/AGP devices) + +REMARKS: +Searches all the PCI base address registers for the device looking for a +memory mapping that is large enough to hold our ROM BIOS. We usually end up +finding the framebuffer mapping (usually BAR 0x10), and we use this mapping +to map the BIOS for the device into. We use a mapping that is already +assigned to the device to ensure the memory range will be passed through +by any PCI->PCI or AGP->PCI bridge that may be present. + +NOTE: Usually this function is only used for AGP devices, but it may be + used for PCI devices that have already been POST'ed and the BIOS + ROM base address has been zero'ed out. +****************************************************************************/ +static ulong PCI_findBIOSAddr( + int device) +{ + ulong base,size; + int bar; + + for (bar = 0x10; bar <= 0x14; bar++) { + base = PCI_readPCIRegL(bar,device) & ~0xFF; + if (!(base & 0x1)) { + PCI_writePCIRegL(bar,0xFFFFFFFF,device); + size = PCI_readPCIRegL(bar,device) & ~0xFF; + size = ~size+1; + PCI_writePCIRegL(bar,0,device); + if (size >= MAX_BIOSLEN) + return base; + } + } + return 0; +} + +/**************************************************************************** +REMARKS: +Re-writes the PCI base address registers for the secondary PCI controller +with the values from our initial PCI bus enumeration. This fixes up the +values after we have POST'ed the secondary display controller BIOS, which +may have incorrectly re-programmed the base registers the same as the +primary display controller (the case for identical S3 cards). +****************************************************************************/ +static void _PCI_fixupSecondaryBARs(void) +{ + int i; + + for (i = 0; i < NumDevices; i++) { + PCI_writePCIRegL(0x10,PCI[DeviceIndex[i]].BaseAddress10,i); + PCI_writePCIRegL(0x14,PCI[DeviceIndex[i]].BaseAddress14,i); + PCI_writePCIRegL(0x18,PCI[DeviceIndex[i]].BaseAddress18,i); + PCI_writePCIRegL(0x1C,PCI[DeviceIndex[i]].BaseAddress1C,i); + PCI_writePCIRegL(0x20,PCI[DeviceIndex[i]].BaseAddress20,i); + PCI_writePCIRegL(0x24,PCI[DeviceIndex[i]].BaseAddress24,i); + } +} + +/**************************************************************************** +RETURNS: +True if successfully initialised, false if not. + +REMARKS: +This function executes the BIOS POST code on the controller. We assume that +at this stage the controller has its I/O and memory space enabled and +that all other controllers are in a disabled state. +****************************************************************************/ +static void PCI_doBIOSPOST( + int device, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + RMREGS regs; + RMSREGS sregs; + + /* Determine the value to store in AX for BIOS POST */ + regs.x.ax = (u16)(PCI[DeviceIndex[device]].slot.i >> 8); + if (useV86) { + /* Post the BIOS using the PM functions (ie: v86 mode on Linux) */ + if (!PM_doBIOSPOST(regs.x.ax,BIOSPhysAddr,mappedBIOS,BIOSLen)) { + /* If the PM function fails, this probably means are we are on */ + /* DOS and can't re-map the real mode 0xC0000 region. In thise */ + /* case if the device is the primary, we can use the real */ + /* BIOS at 0xC0000 directly. */ + if (device == 0) + PM_doBIOSPOST(regs.x.ax,0xC0000,mappedBIOS,BIOSLen); + } + } + else { + /* Setup the X86 emulator for the VGA BIOS */ + BE_setVGA(&VGAInfo[device]); + + /* Execute the BIOS POST code */ + BE_callRealMode(0xC000,0x0003,®s,&sregs); + + /* Cleanup and exit */ + BE_getVGA(&VGAInfo[device]); + } +} + +/**************************************************************************** +RETURNS: +True if successfully initialised, false if not. + +REMARKS: +Loads and POST's the secondary controllers BIOS, directly from the BIOS +image we can extract over the PCI bus. +****************************************************************************/ +static ibool PCI_postControllers(void) +{ + int device; + ulong BIOSImageLen,mappedBIOSPhys; + uchar *mappedBIOS,*copyOfBIOS; + char filename[_MAX_PATH]; + FILE *f; + + /* Disable the primary display controller and AGP VGA pass-through */ + DISABLE_DEVICE(0); + if (AGPBridge) + DISABLE_AGP_VGA(); + + /* Now POST all the secondary controllers */ + for (device = 0; device < NumDevices; device++) { + /* Skip the device if it is not enabled (probably an ISA device) */ + if (DeviceIndex[device] == -1) + continue; + + /* Enable secondary display controller. If the secondary controller */ + /* is on the AGP bus, then enable VGA resources for the AGP device. */ + ENABLE_DEVICE(device); + if (AGPBridge && AGPBridge->SecondayBusNumber == PCI[DeviceIndex[device]].slot.p.Bus) + ENABLE_AGP_VGA(); + + /* Check if the controller has already been POST'ed */ + if (VGA_NOT_ACTIVE()) { + /* Find a viable place to map the secondary PCI BIOS image and map it */ + printk("Device %d not enabled, so attempting warm boot it\n", device); + + /* For AGP devices (and PCI devices that do have the ROM base */ + /* address zero'ed out) we have to map the BIOS to a location */ + /* that is passed by the AGP bridge to the bus. Some AGP devices */ + /* have the ROM base address already set up for us, and some */ + /* do not (we map to one of the existing BAR locations in */ + /* this case). */ + mappedBIOS = NULL; + if (PCI[DeviceIndex[device]].ROMBaseAddress != 0) + mappedBIOSPhys = PCI[DeviceIndex[device]].ROMBaseAddress & ~0xF; + else + mappedBIOSPhys = PCI_findBIOSAddr(device); + printk("Mapping BIOS image to 0x%08X\n", mappedBIOSPhys); + mappedBIOS = PM_mapPhysicalAddr(mappedBIOSPhys,MAX_BIOSLEN-1,false); + PCI_writePCIRegL(0x30,mappedBIOSPhys | 0x1,device); + BIOSImageLen = mappedBIOS[2] * 512; + if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) + return false; + memcpy(copyOfBIOS,mappedBIOS,BIOSImageLen); + PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1); + + /* Allocate memory to store copy of BIOS from secondary controllers */ + VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]]; + VGAInfo[device].BIOSImage = copyOfBIOS; + VGAInfo[device].BIOSImageLen = BIOSImageLen; + + /* Restore device mappings */ + PCI_writePCIRegL(0x30,PCI[DeviceIndex[device]].ROMBaseAddress,device); + PCI_writePCIRegL(0x10,PCI[DeviceIndex[device]].BaseAddress10,device); + PCI_writePCIRegL(0x14,PCI[DeviceIndex[device]].BaseAddress14,device); + + /* Now execute the BIOS POST for the device */ + if (copyOfBIOS[0] == 0x55 && copyOfBIOS[1] == 0xAA) { + printk("Executing BIOS POST for controller.\n"); + PCI_doBIOSPOST(device,mappedBIOSPhys,copyOfBIOS,BIOSImageLen); + } + + /* Reset the size of the BIOS image to the final size */ + VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN; + + /* Save the BIOS and interrupt vector information to disk */ + sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device); + if ((f = fopen(filename,"wb")) != NULL) { + fwrite(copyOfBIOS,1,FINAL_BIOSLEN,f); + fwrite(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f); + fclose(f); + } + } + else { + /* Allocate memory to store copy of BIOS from secondary controllers */ + if ((copyOfBIOS = malloc(FINAL_BIOSLEN)) == NULL) + return false; + VGAInfo[device].pciInfo = &PCI[DeviceIndex[device]]; + VGAInfo[device].BIOSImage = copyOfBIOS; + VGAInfo[device].BIOSImageLen = FINAL_BIOSLEN; + + /* Load the BIOS and interrupt vector information from disk */ + sprintf(filename,"%s/bios.%02d",PM_getNucleusConfigPath(),device); + if ((f = fopen(filename,"rb")) != NULL) { + fread(copyOfBIOS,1,FINAL_BIOSLEN,f); + fread(VGAInfo[device].LowMem,1,sizeof(VGAInfo[device].LowMem),f); + fclose(f); + } + } + + /* Fix up all the secondary PCI base address registers */ + /* (restores them all from the values we read previously) */ + _PCI_fixupSecondaryBARs(); + + /* Disable the secondary controller and AGP VGA pass-through */ + DISABLE_DEVICE(device); + if (AGPBridge) + DISABLE_AGP_VGA(); + } + + /* Reenable primary display controller and reset AGP bridge control */ + if (AGPBridge) + RESTORE_AGP_VGA(); + ENABLE_DEVICE(0); + + /* Free physical BIOS image mapping */ + PM_freePhysicalAddr(mappedBIOS,MAX_BIOSLEN-1); + + /* Restore the X86 emulator BIOS info to primary controller */ + if (!useV86) + BE_setVGA(&VGAInfo[0]); + return true; +} + +/**************************************************************************** +REMARKS: +Enumerates the PCI bus and dumps the PCI configuration information to the +log file. +****************************************************************************/ +static void EnumeratePCI(void) +{ + int i,index; + PCIBridgeInfo *info; + + printk("Displaying enumeration of PCI bus (%d devices, %d display devices)\n", + NumPCI, NumDevices); + for (index = 0; index < NumDevices; index++) + printk(" Display device %d is PCI device %d\n",index,DeviceIndex[index]); + printk("\n"); + printk("Bus Slot Fnc DeviceID SubSystem Rev Class IRQ Int Cmd\n"); + for (i = 0; i < NumPCI; i++) { + printk("%2d %2d %2d %04X:%04X %04X:%04X %02X %02X:%02X %02X %02X %04X ", + PCI[i].slot.p.Bus, + PCI[i].slot.p.Device, + PCI[i].slot.p.Function, + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].SubSystemVendorID, + PCI[i].SubSystemID, + PCI[i].RevID, + PCI[i].BaseClass, + PCI[i].SubClass, + PCI[i].InterruptLine, + PCI[i].InterruptPin, + PCI[i].Command); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } + printk("\n"); + printk("DeviceID Stat Ifc Cch Lat Hdr BIST\n"); + for (i = 0; i < NumPCI; i++) { + printk("%04X:%04X %04X %02X %02X %02X %02X %02X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].Status, + PCI[i].Interface, + PCI[i].CacheLineSize, + PCI[i].LatencyTimer, + PCI[i].HeaderType, + PCI[i].BIST); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } + printk("\n"); + printk("DeviceID Base10h Base14h Base18h Base1Ch Base20h Base24h ROMBase\n"); + for (i = 0; i < NumPCI; i++) { + printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].BaseAddress10, + PCI[i].BaseAddress14, + PCI[i].BaseAddress18, + PCI[i].BaseAddress1C, + PCI[i].BaseAddress20, + PCI[i].BaseAddress24, + PCI[i].ROMBaseAddress); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } + printk("\n"); + printk("DeviceID BAR10Len BAR14Len BAR18Len BAR1CLen BAR20Len BAR24Len ROMLen\n"); + for (i = 0; i < NumPCI; i++) { + printk("%04X:%04X %08X %08X %08X %08X %08X %08X %08X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].BaseAddress10Len, + PCI[i].BaseAddress14Len, + PCI[i].BaseAddress18Len, + PCI[i].BaseAddress1CLen, + PCI[i].BaseAddress20Len, + PCI[i].BaseAddress24Len, + PCI[i].ROMBaseAddressLen); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printk("<- %d\n", index); + else + printk("\n"); + } + printk("\n"); + printk("Displaying enumeration of %d bridge devices\n",NumBridges); + printk("\n"); + printk("DeviceID P# S# B# IOB IOL MemBase MemLimit PreBase PreLimit Ctrl\n"); + for (i = 0; i < NumBridges; i++) { + info = (PCIBridgeInfo*)&PCI[BridgeIndex[i]]; + printk("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n", + info->VendorID, + info->DeviceID, + info->PrimaryBusNumber, + info->SecondayBusNumber, + info->SubordinateBusNumber, + ((u16)info->IOBase << 8) & 0xF000, + info->IOLimit ? + ((u16)info->IOLimit << 8) | 0xFFF : 0, + ((u32)info->MemoryBase << 16) & 0xFFF00000, + info->MemoryLimit ? + ((u32)info->MemoryLimit << 16) | 0xFFFFF : 0, + ((u32)info->PrefetchableMemoryBase << 16) & 0xFFF00000, + info->PrefetchableMemoryLimit ? + ((u32)info->PrefetchableMemoryLimit << 16) | 0xFFFFF : 0, + info->BridgeControl); + } + printk("\n"); +} + +/**************************************************************************** +RETURNS: +Number of display devices found. + +REMARKS: +This function enumerates the number of available display devices on the +PCI bus, and returns the number found. +****************************************************************************/ +static int PCI_enumerateDevices(void) +{ + int i,j; + PCIBridgeInfo *info; + + /* If this is the first time we have been called, enumerate all */ + /* devices on the PCI bus. */ + if (NumPCI == -1) { + for (i = 0; i < MAX_PCI_DEVICES; i++) + PCI[i].dwSize = sizeof(PCI[i]); + if ((NumPCI = PCI_enumerate(PCI,MAX_PCI_DEVICES)) == 0) + return -1; + + /* Build a list of all PCI bridge devices */ + for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { + if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) { + if (NumBridges < MAX_PCI_DEVICES) + BridgeIndex[NumBridges++] = i; + } + } + + /* Now build a list of all display class devices */ + for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { + if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { + if ((PCI[i].Command & 0x3) == 0x3) { + DeviceIndex[0] = i; + } + else { + if (NumDevices < MAX_PCI_DEVICES) + DeviceIndex[NumDevices++] = i; + } + if (PCI[i].slot.p.Bus != 0) { + /* This device is on a different bus than the primary */ + /* PCI bus, so it is probably an AGP device. Find the */ + /* AGP bus device that controls that bus so we can */ + /* control it. */ + for (j = 0; j < NumBridges; j++) { + info = (PCIBridgeInfo*)&PCI[BridgeIndex[j]]; + if (info->SecondayBusNumber == PCI[i].slot.p.Bus) { + AGPBridge = info; + break; + } + } + } + } + } + + /* Enumerate all PCI and bridge devices to log file */ + EnumeratePCI(); + } + return NumDevices; +} + +FILE *logfile; + +void printk(const char *fmt, ...) +{ + va_list argptr; + va_start(argptr, fmt); + vfprintf(logfile, fmt, argptr); + fflush(logfile); + va_end(argptr); +} + +int main(int argc,char *argv[]) +{ + while (argc > 1) { + if (stricmp(argv[1],"-usev86") == 0) { + useV86 = true; + } + else if (stricmp(argv[1],"-force") == 0) { + forcePost = true; + } +#ifdef DEBUG + else if (stricmp(argv[1],"-decode") == 0) { + debugFlags |= DEBUG_DECODE_F; + } + else if (stricmp(argv[1],"-iotrace") == 0) { + debugFlags |= DEBUG_IO_TRACE_F; + } +#endif + else { + printf("Usage: warmboot [-usev86] [-force] [-decode] [-iotrace]\n"); + exit(-1); + } + argc--; + argv++; + } + if ((logfile = fopen("warmboot.log","w")) == NULL) + exit(1); + + PM_init(); + if (!useV86) { + /* Initialise the x86 BIOS emulator */ + BE_init(false,debugFlags,65536,&VGAInfo[0]); + } + + /* Enumerate all devices (which POST's them at the same time) */ + if (PCI_enumerateDevices() < 1) { + printk("No PCI display devices found!\n"); + return -1; + } + + /* Post all the display controller BIOS'es */ + PCI_postControllers(); + + /* Cleanup and exit the emulator */ + if (!useV86) + BE_exit(); + fclose(logfile); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm new file mode 100644 index 000000000..61a9024ab --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/_aa_imp.asm @@ -0,0 +1,51 @@ +;**************************************************************************** +;* +;* SciTech Nucleus Audio Architecture +;* +;* Copyright (C) 1991-1998 SciTech Software, Inc. +;* All rights reserved. +;* +;* ====================================================================== +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* | | +;* |This copyrighted computer code contains proprietary technology | +;* |owned by SciTech Software, Inc., located at 505 Wall Street, | +;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +;* | | +;* |The contents of this file are subject to the SciTech Nucleus | +;* |License; you may *not* use this file or related software except in | +;* |compliance with the License. You may obtain a copy of the License | +;* |at http://www.scitechsoft.com/nucleus-license.txt | +;* | | +;* |Software distributed under the License is distributed on an | +;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +;* |implied. See the License for the specific language governing | +;* |rights and limitations under the License. | +;* | | +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* ====================================================================== +;* +;* Language: TASM 4.0 or NASM +;* Environment: IBM PC 32 bit Protected Mode. +;* +;* Description: Module to implement the import stubs for all the Nucleus +;* Audio API functions for Intel binary compatible drivers. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +BEGIN_IMPORTS_DEF _AA_exports +SKIP_IMP AA_status ; Implemented in C code +SKIP_IMP AA_errorMsg ; Implemented in C code +SKIP_IMP AA_getDaysLeft ; Implemented in C code +SKIP_IMP AA_registerLicense ; Implemented in C code +SKIP_IMP AA_enumerateDevices ; Implemented in C code +SKIP_IMP AA_loadDriver ; Implemented in C code +DECLARE_IMP AA_unloadDriver +DECLARE_IMP AA_saveOptions +END_IMPORTS_DEF + + END diff --git a/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm new file mode 100644 index 000000000..531760043 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/_ga_imp.asm @@ -0,0 +1,136 @@ +;**************************************************************************** +;* +;* SciTech Nucleus Graphics Architecture +;* +;* Copyright (C) 1991-1998 SciTech Software, Inc. +;* All rights reserved. +;* +;* ====================================================================== +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* | | +;* |This copyrighted computer code contains proprietary technology | +;* |owned by SciTech Software, Inc., located at 505 Wall Street, | +;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +;* | | +;* |The contents of this file are subject to the SciTech Nucleus | +;* |License; you may *not* use this file or related software except in | +;* |compliance with the License. You may obtain a copy of the License | +;* |at http://www.scitechsoft.com/nucleus-license.txt | +;* | | +;* |Software distributed under the License is distributed on an | +;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +;* |implied. See the License for the specific language governing | +;* |rights and limitations under the License. | +;* | | +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* ====================================================================== +;* +;* Language: TASM 4.0 or NASM +;* Environment: IBM PC 32 bit Protected Mode. +;* +;* Description: Module to implement the import stubs for all the Nucleus +;* Graphics API functions for Intel binary compatible drivers. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +BEGIN_IMPORTS_DEF __GA_exports +SKIP_IMP GA_status,0 ; Implemented in C code +SKIP_IMP GA_errorMsg,1 ; Implemented in C code +SKIP_IMP GA_getDaysLeft,1 ; Implemented in C code +SKIP_IMP GA_registerLicense,2 ; Implemented in C code +SKIP_IMP GA_enumerateDevices,1 ; Implemented in C code +SKIP_IMP GA_loadDriver,2 ; Implemented in C code +DECLARE_IMP GA_setActiveDevice,1 +SKIP_IMP GA_reserved1,0 ; Implemented in C code +DECLARE_IMP GA_unloadDriver,1 +DECLARE_IMP REF2D_loadDriver,6 +DECLARE_IMP REF2D_unloadDriver,2 +DECLARE_IMP GA_loadRef2d,5 +DECLARE_IMP GA_unloadRef2d,1 +DECLARE_IMP GA_softStereoInit,1 +DECLARE_IMP GA_softStereoOn,0 +DECLARE_IMP GA_softStereoScheduleFlip,2 +DECLARE_IMP GA_softStereoGetFlipStatus,0 +DECLARE_IMP GA_softStereoWaitTillFlipped,0 +DECLARE_IMP GA_softStereoOff,0 +DECLARE_IMP GA_softStereoExit,0 +DECLARE_IMP GA_saveModeProfile,2 +DECLARE_IMP GA_saveOptions,2 +DECLARE_IMP GA_saveCRTCTimings,1 +DECLARE_IMP GA_restoreCRTCTimings,1 +DECLARE_IMP DDC_init,1 +DECLARE_IMP DDC_readEDID,5 +DECLARE_IMP EDID_parse,3 +DECLARE_IMP MCS_begin,1 +DECLARE_IMP MCS_getCapabilitiesString,2 +DECLARE_IMP MCS_isControlSupported,1 +DECLARE_IMP MCS_enableControl,2 +DECLARE_IMP MCS_getControlMax,2 +DECLARE_IMP MCS_getControlValue,2 +DECLARE_IMP MCS_getControlValues,3 +DECLARE_IMP MCS_setControlValue,2 +DECLARE_IMP MCS_setControlValues,3 +DECLARE_IMP MCS_resetControl,1 +DECLARE_IMP MCS_saveCurrentSettings,0 +DECLARE_IMP MCS_getTimingReport,3 +DECLARE_IMP MCS_getSelfTestReport,3 +DECLARE_IMP MCS_end,0 +SKIP_IMP GA_loadInGUI,1 ; Implemented in C code +DECLARE_IMP DDC_writeEDID,6 +DECLARE_IMP GA_useDoubleScan,1 +DECLARE_IMP GA_getMaxRefreshRate,4 +DECLARE_IMP GA_computeCRTCTimings,6 +DECLARE_IMP GA_addMode,5 +DECLARE_IMP GA_addRefresh,5 +DECLARE_IMP GA_delMode,5 +DECLARE_IMP N_getLogName,0 +SKIP_IMP2 N_log +DECLARE_IMP MDBX_getErrCode,0 +DECLARE_IMP MDBX_getErrorMsg,0 +DECLARE_IMP MDBX_open,1 +DECLARE_IMP MDBX_close,0 +DECLARE_IMP MDBX_first,1 +DECLARE_IMP MDBX_last,1 +DECLARE_IMP MDBX_next,1 +DECLARE_IMP MDBX_prev,1 +DECLARE_IMP MDBX_insert,1 +DECLARE_IMP MDBX_update,1 +DECLARE_IMP MDBX_flush,0 +DECLARE_IMP MDBX_importINF,2 +SKIP_IMP GA_getGlobalOptions,2 ; Implemented in C code +DECLARE_IMP GA_setGlobalOptions,1 +DECLARE_IMP GA_saveGlobalOptions,1 +DECLARE_IMP GA_getInternalName,1 +DECLARE_IMP GA_getNucleusConfigPath,0 +DECLARE_IMP GA_getFakePCIID,0 +SKIP_IMP GA_loadLibrary,3 ; Implemented in C code +SKIP_IMP GA_isOEMVersion,1 ; Implemented in C code +DECLARE_IMP GA_isLiteVersion,1 +DECLARE_IMP GA_getDisplaySerialNo,1 +DECLARE_IMP GA_getDisplayUserName,1 +SKIP_IMP GA_getCurrentDriver,1 ; Implemented in C code +SKIP_IMP GA_getCurrentRef2d,1 ; Implemented in C code +SKIP_IMP GA_getLicensedDevices,1 ; Implemented in C code +DECLARE_IMP DDC_initExt,2 +DECLARE_IMP MCS_beginExt,2 +DECLARE_IMP GA_loadRegionMgr,3 +DECLARE_IMP GA_unloadRegionMgr,1 +DECLARE_IMP GA_getProcAddress,2 +DECLARE_IMP GA_enableVBEMode,5 +DECLARE_IMP GA_disableVBEMode,5 +DECLARE_IMP GA_loadModeProfile,2 +DECLARE_IMP GA_getCRTCTimings,4 +DECLARE_IMP GA_setCRTCTimings,4 +DECLARE_IMP GA_setDefaultRefresh,6 +DECLARE_IMP GA_saveMonitorInfo,2 +DECLARE_IMP GA_detectPnPMonitor,3 +SKIP_IMP3 GA_queryFunctions +SKIP_IMP3 REF2D_queryFunctions +END_IMPORTS_DEF + + END + diff --git a/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm b/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm new file mode 100644 index 000000000..0194a62f9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/_gatimer.asm @@ -0,0 +1,248 @@ +;**************************************************************************** +;* +;* SciTech Nucleus Graphics Architecture +;* +;* Copyright (C) 1991-1998 SciTech Software, Inc. +;* All rights reserved. +;* +;* ====================================================================== +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* | | +;* |This copyrighted computer code contains proprietary technology | +;* |owned by SciTech Software, Inc., located at 505 Wall Street, | +;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +;* | | +;* |The contents of this file are subject to the SciTech Nucleus | +;* |License; you may *not* use this file or related software except in | +;* |compliance with the License. You may obtain a copy of the License | +;* |at http://www.scitechsoft.com/nucleus-license.txt | +;* | | +;* |Software distributed under the License is distributed on an | +;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +;* |implied. See the License for the specific language governing | +;* |rights and limitations under the License. | +;* | | +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* ====================================================================== +;* +;* Language: 80386 Assembler, NASM or TASM +;* Environment: IBM PC 32 bit Protected Mode. +;* +;* Description: Assembly support functions for the Nucleus library for +;* the high resolution timing support functions provided by +;* the Intel Pentium and compatible processors. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _gatimer + +begcodeseg _gatimer + +ifdef USE_NASM +%macro mCPU_ID 0 +db 00Fh,0A2h +%endmacro +else +MACRO mCPU_ID +db 00Fh,0A2h +ENDM +endif + +ifdef USE_NASM +%macro mRDTSC 0 +db 00Fh,031h +%endmacro +else +MACRO mRDTSC +db 00Fh,031h +ENDM +endif + +;---------------------------------------------------------------------------- +; bool _GA_haveCPUID(void) +;---------------------------------------------------------------------------- +; Determines if we have support for the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _GA_haveCPUID + + enter_c + pushfd ; Get original EFLAGS + pop eax + mov ecx, eax + xor eax, 200000h ; Flip ID bit in EFLAGS + push eax ; Save new EFLAGS value on stack + popfd ; Replace current EFLAGS value + pushfd ; Get new EFLAGS + pop eax ; Store new EFLAGS in EAX + xor eax, ecx ; Can not toggle ID bit, + jnz @@1 ; Processor=80486 + mov eax,0 ; We dont have CPUID support + jmp @@Done +@@1: mov eax,1 ; We have CPUID support +@@Done: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uint _GA_getCPUIDFeatures(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _GA_getCPUIDFeatures + + enter_c + + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax, 1 ; Make sure 1 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + xor eax, eax + inc eax + mCPU_ID ; Get family/model/stepping/features + mov eax, edx +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; void _GA_readTimeStamp(GA_largeInteger *time) +;---------------------------------------------------------------------------- +; Reads the time stamp counter and returns the 64-bit result. +;---------------------------------------------------------------------------- +cprocstart _GA_readTimeStamp + + mRDTSC + mov ecx,[esp+4] ; Access directly without stack frame + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; N_uint32 GA_TimerDifference(GA_largeInteger *a,GA_largeInteger *b) +;---------------------------------------------------------------------------- +; Computes the difference between two 64-bit numbers (a-b) +;---------------------------------------------------------------------------- +cprocstart GA_TimerDifference + + ARG a:DPTR, b:DPTR, t:DPTR + + enter_c + + mov ecx,[a] + mov eax,[ecx] ; EAX := b.low + mov ecx,[b] + sub eax,[ecx] + mov edx,eax ; EDX := low difference + mov ecx,[a] + mov eax,[ecx+4] ; ECX := b.high + mov ecx,[b] + sbb eax,[ecx+4] ; EAX := high difference + mov eax,edx ; Return low part + + leave_c + ret + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY_TIMER 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +else +macro DELAY_TIMER + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +endif + +;---------------------------------------------------------------------------- +; void _OS_delay8253(N_uint32 microSeconds); +;---------------------------------------------------------------------------- +; Delays for the specified number of microseconds, by directly programming +; the 8253 timer chips. +;---------------------------------------------------------------------------- +cprocstart _OS_delay8253 + + ARG microSec:UINT + + enter_c + +; Start timer 2 counting + + mov _ax,[microSec] ; EAX := count in microseconds + mov ecx,1196 + mul ecx + mov ecx,1000 + div ecx + mov ecx,eax ; ECX := count in timer ticks + in al,61h + or al,1 + out 61h,al + +; Set the timer 2 count to 0 again to start the timing interval. + + mov al,10110100b ; set up to load initial (timer 2) + out 43h,al ; timer count + DELAY_TIMER + sub al,al + out 42h,al ; load count lsb + DELAY_TIMER + out 42h,al ; load count msb + xor di,di ; Allow max 64K loop iterations + +@@LoopStart: + dec di ; This is a guard against the possibility that + jz @@LoopEnd ; someone eg. stopped the timer behind our back. + ; After 64K iterations we bail out no matter what + ; (and hope it wasn't too soon) + mov al,00000000b ; latch timer 0 + out 43h,al + DELAY_TIMER + in al,42h ; least significant byte + DELAY_TIMER + mov ah,al + in al,42h ; most significant byte + xchg ah,al + neg ax ; Convert from countdown remaining + ; to elapsed count + cmp ax,cx ; Has delay expired? + jb @@LoopStart ; No, so loop till done + +; Stop timer 2 from counting +@@LoopEnd: + in al,61H + and al,0FEh + out 61H,al + +; Some programs have a problem if we change the control port; better change it +; to something they expect (mode 3 - square wave generator)... + mov al,0B6h + out 43h,al + + leave_c + ret + +cprocend + +endcodeseg _gatimer + + END + diff --git a/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm b/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm new file mode 100644 index 000000000..d4b11790a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/_pm_imp.asm @@ -0,0 +1,195 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* Copyright (C) 1991-1998 SciTech Software, Inc. +;* All rights reserved. +;* +;* ====================================================================== +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* | | +;* |This copyrighted computer code contains proprietary technology | +;* |owned by SciTech Software, Inc., located at 505 Wall Street, | +;* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +;* | | +;* |The contents of this file are subject to the SciTech Nucleus | +;* |License; you may *not* use this file or related software except in | +;* |compliance with the License. You may obtain a copy of the License | +;* |at http://www.scitechsoft.com/nucleus-license.txt | +;* | | +;* |Software distributed under the License is distributed on an | +;* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +;* |implied. See the License for the specific language governing | +;* |rights and limitations under the License. | +;* | | +;* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +;* ====================================================================== +;* +;* Language: TASM 4.0 or NASM +;* Environment: IBM PC 32 bit Protected Mode. +;* +;* Description: Module to implement the import stubs for all the PM +;* API functions for Intel binary portable drivers. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +BEGIN_IMPORTS_DEF _PM_imports +DECLARE_IMP PM_getModeType,0 +DECLARE_IMP PM_getBIOSPointer,0 +DECLARE_IMP PM_getA0000Pointer,0 +DECLARE_IMP PM_mapPhysicalAddr,0 +DECLARE_IMP PM_mallocShared,0 +SKIP_IMP _PM_reserved1,0 +DECLARE_IMP PM_freeShared,0 +DECLARE_IMP PM_mapToProcess,0 +DECLARE_IMP PM_mapRealPointer,0 +DECLARE_IMP PM_allocRealSeg,0 +DECLARE_IMP PM_freeRealSeg,0 +DECLARE_IMP PM_allocLockedMem,0 +DECLARE_IMP PM_freeLockedMem,0 +DECLARE_IMP PM_callRealMode,0 +DECLARE_IMP PM_int86,0 +DECLARE_IMP PM_int86x,0 +DECLARE_IMP DPMI_int86,0 +DECLARE_IMP PM_availableMemory,0 +DECLARE_IMP PM_getVESABuf,0 +DECLARE_IMP PM_getOSType,0 +DECLARE_IMP PM_fatalError,0 +DECLARE_IMP PM_setBankA,0 +DECLARE_IMP PM_setBankAB,0 +DECLARE_IMP PM_setCRTStart,0 +DECLARE_IMP PM_getCurrentPat,0 +DECLARE_IMP PM_getVBEAFPath,0 +DECLARE_IMP PM_getNucleusPath,0 +DECLARE_IMP PM_getNucleusConfigPath,0 +DECLARE_IMP PM_getUniqueID,0 +DECLARE_IMP PM_getMachineName,0 +DECLARE_IMP VF_available,0 +DECLARE_IMP VF_init,0 +DECLARE_IMP VF_exit,0 +DECLARE_IMP PM_openConsole,0 +DECLARE_IMP PM_getConsoleStateSize,0 +DECLARE_IMP PM_saveConsoleState,0 +DECLARE_IMP PM_restoreConsoleState,0 +DECLARE_IMP PM_closeConsole,0 +DECLARE_IMP PM_setOSCursorLocation,0 +DECLARE_IMP PM_setOSScreenWidth,0 +DECLARE_IMP PM_enableWriteCombine,0 +DECLARE_IMP PM_backslash,0 +DECLARE_IMP PM_lockDataPages,0 +DECLARE_IMP PM_unlockDataPages,0 +DECLARE_IMP PM_lockCodePages,0 +DECLARE_IMP PM_unlockCodePages,0 +DECLARE_IMP PM_setRealTimeClockHandler,0 +DECLARE_IMP PM_setRealTimeClockFrequency,0 +DECLARE_IMP PM_restoreRealTimeClockHandler,0 +DECLARE_IMP PM_doBIOSPOST,0 +DECLARE_IMP PM_getBootDrive,0 +DECLARE_IMP PM_freePhysicalAddr,0 +DECLARE_IMP PM_inpb,0 +DECLARE_IMP PM_inpw,0 +DECLARE_IMP PM_inpd,0 +DECLARE_IMP PM_outpb,0 +DECLARE_IMP PM_outpw,0 +DECLARE_IMP PM_outpd,0 +SKIP_IMP _PM_reserved2,0 +DECLARE_IMP PM_setSuspendAppCallback,0 +DECLARE_IMP PM_haveBIOSAccess,0 +DECLARE_IMP PM_kbhit,0 +DECLARE_IMP PM_getch,0 +DECLARE_IMP PM_findBPD,0 +DECLARE_IMP PM_getPhysicalAddr,0 +DECLARE_IMP PM_sleep,0 +DECLARE_IMP PM_getCOMPort,0 +DECLARE_IMP PM_getLPTPort,0 +DECLARE_IMP PM_loadLibrary,0 +DECLARE_IMP PM_getProcAddress,0 +DECLARE_IMP PM_freeLibrary,0 +DECLARE_IMP PCI_enumerate,0 +DECLARE_IMP PCI_accessReg,0 +DECLARE_IMP PCI_setHardwareIRQ,0 +DECLARE_IMP PCI_generateSpecialCyle,0 +SKIP_IMP _PM_reserved3,0 +DECLARE_IMP PCIBIOS_getEntry,0 +DECLARE_IMP CPU_getProcessorType,0 +DECLARE_IMP CPU_haveMMX,0 +DECLARE_IMP CPU_have3DNow,0 +DECLARE_IMP CPU_haveSSE,0 +DECLARE_IMP CPU_haveRDTSC,0 +DECLARE_IMP CPU_getProcessorSpeed,0 +DECLARE_IMP ZTimerInit,0 +DECLARE_IMP LZTimerOn,0 +DECLARE_IMP LZTimerLap,0 +DECLARE_IMP LZTimerOff,0 +DECLARE_IMP LZTimerCount,0 +DECLARE_IMP LZTimerOnExt,0 +DECLARE_IMP LZTimerLapExt,0 +DECLARE_IMP LZTimerOffExt,0 +DECLARE_IMP LZTimerCountExt,0 +DECLARE_IMP ULZTimerOn,0 +DECLARE_IMP ULZTimerLap,0 +DECLARE_IMP ULZTimerOff,0 +DECLARE_IMP ULZTimerCount,0 +DECLARE_IMP ULZReadTime,0 +DECLARE_IMP ULZElapsedTime,0 +DECLARE_IMP ULZTimerResolution,0 +DECLARE_IMP PM_findFirstFile,0 +DECLARE_IMP PM_findNextFile,0 +DECLARE_IMP PM_findClose,0 +DECLARE_IMP PM_makepath,0 +DECLARE_IMP PM_splitpath,0 +DECLARE_IMP PM_driveValid,0 +DECLARE_IMP PM_getdcwd,0 +DECLARE_IMP PM_setFileAttr,0 +DECLARE_IMP PM_mkdir,0 +DECLARE_IMP PM_rmdir,0 +DECLARE_IMP PM_getFileAttr,0 +DECLARE_IMP PM_getFileTime,0 +DECLARE_IMP PM_setFileTime,0 +DECLARE_IMP CPU_getProcessorName,0 +DECLARE_IMP PM_getVGAStateSize,0 +DECLARE_IMP PM_saveVGAState,0 +DECLARE_IMP PM_restoreVGAState,0 +DECLARE_IMP PM_vgaBlankDisplay,0 +DECLARE_IMP PM_vgaUnblankDisplay,0 +DECLARE_IMP PM_blockUntilTimeout,0 +DECLARE_IMP _PM_add64,0 +DECLARE_IMP _PM_sub64,0 +DECLARE_IMP _PM_mul64,0 +DECLARE_IMP _PM_div64,0 +DECLARE_IMP _PM_shr64,0 +DECLARE_IMP _PM_sar64,0 +DECLARE_IMP _PM_shl64,0 +DECLARE_IMP _PM_neg64,0 +DECLARE_IMP PCI_findBARSize,0 +DECLARE_IMP PCI_readRegBlock,0 +DECLARE_IMP PCI_writeRegBlock,0 +DECLARE_IMP PM_flushTLB,0 +DECLARE_IMP PM_useLocalMalloc,0 +DECLARE_IMP PM_malloc,0 +DECLARE_IMP PM_calloc,0 +DECLARE_IMP PM_realloc,0 +DECLARE_IMP PM_free,0 +DECLARE_IMP PM_getPhysicalAddrRange,0 +DECLARE_IMP PM_allocPage,0 +DECLARE_IMP PM_freePage,0 +DECLARE_IMP PM_agpInit,0 +DECLARE_IMP PM_agpExit,0 +DECLARE_IMP PM_agpReservePhysical,0 +DECLARE_IMP PM_agpReleasePhysical,0 +DECLARE_IMP PM_agpCommitPhysical,0 +DECLARE_IMP PM_agpFreePhysical,0 +DECLARE_IMP PCI_getNumDevices,0 +DECLARE_IMP PM_setLocalBPDPath,0 +DECLARE_IMP PM_loadDirectDraw,0 +DECLARE_IMP PM_unloadDirectDraw,0 +DECLARE_IMP PM_getDirectDrawWindow,0 +DECLARE_IMP PM_doSuspendApp,0 +END_IMPORTS_DEF + + END + diff --git a/board/MAI/bios_emulator/scitech/src/common/aabeos.c b/board/MAI/bios_emulator/scitech/src/common/aabeos.c new file mode 100644 index 000000000..ad5698a40 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aabeos.c @@ -0,0 +1,92 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Linux operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + (void)device; + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timeval t; + gettimeofday(&t, NULL); + value->low = t.tv_sec*1000000 + t.tv_usec; + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aados.c b/board/MAI/bios_emulator/scitech/src/common/aados.c new file mode 100644 index 000000000..342d2f33a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aados.c @@ -0,0 +1,64 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: MSDOS +* +* Description: OS specific Nucleus Graphics Architecture services for +* the MSDOS operating system. +* +****************************************************************************/ + +#include "pm_help.h" +#include "pmapi.h" +#include +#include +#include + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the DOS +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aalib.c b/board/MAI/bios_emulator/scitech/src/common/aalib.c new file mode 100644 index 000000000..5003b2229 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aalib.c @@ -0,0 +1,225 @@ +/**************************************************************************** +* +* SciTech Nucleus Audio Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Any 32-bit protected mode environment +* +* Description: C module for the Graphics Accelerator Driver API. Uses +* the SciTech PM library for interfacing with DOS +* extender specific functions. +* +****************************************************************************/ + +#include "nucleus/audio.h" +#ifdef __WIN32_VXD__ +#include "sdd/sddhelp.h" +#else +#include +#include +#endif + +/*---------------------------- Global Variables ---------------------------*/ + +#ifdef TEST_HARNESS +extern PM_imports _VARAPI _PM_imports; +#else +AA_exports _VARAPI _AA_exports; +static int loaded = false; +static PE_MODULE *hModBPD = NULL; + +#ifdef __DRIVER__ +extern PM_imports _PM_imports; +#else +#include "pmimp.h" +#endif + +static N_imports _N_imports = { + sizeof(N_imports), + _OS_delay, + }; + +#ifdef __DRIVER__ +extern AA_imports _AA_imports; +#else +static AA_imports _AA_imports = { + sizeof(AA_imports), + }; +#endif +#endif + +/*----------------------------- Implementation ----------------------------*/ + +#define DLL_NAME "audio.bpd" + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Fatal error handler for non-exported AA_exports. +****************************************************************************/ +static void _AA_fatalErrorHandler(void) +{ + PM_fatalError("Unsupported Nucleus export function called! Please upgrade your copy of Nucleus!\n"); +} + +/**************************************************************************** +REMARKS: +Loads the Nucleus binary portable DLL into memory and initilises it. +****************************************************************************/ +static ibool LoadDriver(void) +{ + AA_initLibrary_t AA_initLibrary; + AA_exports *aaExp; + char filename[PM_MAX_PATH]; + char bpdpath[PM_MAX_PATH]; + int i,max; + ulong *p; + + /* Check if we have already loaded the driver */ + if (loaded) + return true; + PM_init(); + _AA_exports.dwSize = sizeof(_AA_exports); + + /* Open the BPD file */ + if (!PM_findBPD(DLL_NAME,bpdpath)) + return false; + strcpy(filename,bpdpath); + strcat(filename,DLL_NAME); + if ((hModBPD = PE_loadLibrary(filename,false)) == NULL) + return false; + if ((AA_initLibrary = (AA_initLibrary_t)PE_getProcAddress(hModBPD,"_AA_initLibrary")) == NULL) + return false; + bpdpath[strlen(bpdpath)-1] = 0; + if (strcmp(bpdpath,PM_getNucleusPath()) == 0) + strcpy(bpdpath,PM_getNucleusConfigPath()); + else { + PM_backslash(bpdpath); + strcat(bpdpath,"config"); + } + if ((aaExp = AA_initLibrary(bpdpath,filename,&_PM_imports,&_N_imports,&_AA_imports)) == NULL) + PM_fatalError("AA_initLibrary failed!\n"); + + /* Initialize all default imports to point to fatal error handler + * for upwards compatibility, and copy the exported functions. + */ + max = sizeof(_AA_exports)/sizeof(AA_initLibrary_t); + for (i = 0,p = (ulong*)&_AA_exports; i < max; i++) + *p++ = (ulong)_AA_fatalErrorHandler; + memcpy(&_AA_exports,aaExp,MIN(sizeof(_AA_exports),aaExp->dwSize)); + loaded = true; + return true; +} + +/* The following are stub entry points that the application calls to + * initialise the Nucleus loader library, and we use this to load our + * driver DLL from disk and initialise the library using it. + */ + +/* {secret} */ +int NAPI AA_status(void) +{ + if (!loaded) + return nDriverNotFound; + return _AA_exports.AA_status(); +} + +/* {secret} */ +const char * NAPI AA_errorMsg( + N_int32 status) +{ + if (!loaded) + return "Unable to load Nucleus device driver!"; + return _AA_exports.AA_errorMsg(status); +} + +/* {secret} */ +int NAPI AA_getDaysLeft(void) +{ + if (!LoadDriver()) + return -1; + return _AA_exports.AA_getDaysLeft(); +} + +/* {secret} */ +int NAPI AA_registerLicense(uchar *license) +{ + if (!LoadDriver()) + return 0; + return _AA_exports.AA_registerLicense(license); +} + +/* {secret} */ +int NAPI AA_enumerateDevices(void) +{ + if (!LoadDriver()) + return 0; + return _AA_exports.AA_enumerateDevices(); +} + +/* {secret} */ +AA_devCtx * NAPI AA_loadDriver(N_int32 deviceIndex) +{ + if (!LoadDriver()) + return NULL; + return _AA_exports.AA_loadDriver(deviceIndex); +} +#endif + +typedef struct { + N_uint32 low; + N_uint32 high; + } AA_largeInteger; + +void NAPI _OS_delay8253(N_uint32 microSeconds); +ibool NAPI _GA_haveCPUID(void); +uint NAPI _GA_getCPUIDFeatures(void); +void NAPI _GA_readTimeStamp(AA_largeInteger *time); +#define CPU_HaveRDTSC 0x00000010 + +/**************************************************************************** +REMARKS: +This function delays for the specified number of microseconds +****************************************************************************/ +void NAPI _OS_delay( + N_uint32 microSeconds) +{ + static ibool inited = false; + LZTimerObject tm; + + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + if (!inited) { + ZTimerInit(); + inited = true; + } + LZTimerOnExt(&tm); + while (LZTimerLapExt(&tm) < microSeconds) + ; + LZTimerOnExt(&tm); + } + else + _OS_delay8253(microSeconds); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aalinux.c b/board/MAI/bios_emulator/scitech/src/common/aalinux.c new file mode 100644 index 000000000..d3d468ed0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aalinux.c @@ -0,0 +1,94 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Linux operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +/*---------------------------- Global Variables ---------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + (void)device; + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timeval t; + gettimeofday(&t, NULL); + value->low = t.tv_sec*1000000 + t.tv_usec; + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aaos2.c b/board/MAI/bios_emulator/scitech/src/common/aaos2.c new file mode 100644 index 000000000..0ec8c9fcf --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aaos2.c @@ -0,0 +1,124 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: OS/2 32-bit +* +* Description: OS specific Nucleus Graphics Architecture services for +* the OS/2 operating system environments. +* +****************************************************************************/ + +#include "pm_help.h" +#define INCL_DOSERRORS +#define INCL_DOS +#define INCL_SUB +#define INCL_VIO +#define INCL_KBD +#include + +/*---------------------------- Global Variables ---------------------------*/ + +static HFILE hSDDHelp; +static ulong outLen; /* Must not cross 64Kb boundary! */ +static ulong result; /* Must not cross 64Kb boundary! */ +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +This function returns a pointer to the common graphics driver loaded in the +helper VxD. The memory for the VxD is shared between all processes via +the VxD, so that the VxD, 16-bit code and 32-bit code all see the same +state when accessing the graphics binary portable driver. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + /* Initialise the PM library and connect to our runtime DLL's */ + PM_init(); + + /* Open our helper device driver */ + if (DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0, + FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, + NULL)) + PM_fatalError("Unable to open SDDHELP$ helper device driver!"); + outLen = sizeof(result); + DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,PMHELP_GETSHAREDINFO, + NULL, 0, NULL, + &result, outLen, &outLen); + DosClose(hSDDHelp); + if (result) { + /* We have found the shared Nucleus packet. Because not all processes + * map to SDDPMI.DLL, we need to ensure that we connect to this + * DLL so that it gets mapped into our address space (that is + * where the shared Nucleus packet is located). Simply doing a + * DosLoadModule on it is enough for this. + */ + HMODULE hModSDDPMI; + char buf[80]; + DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"SDDPMI.DLL",&hModSDDPMI); + } + return (GA_sharedInfo*)result; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + DosTmrQueryTime((QWORD*)value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aaqnx.c b/board/MAI/bios_emulator/scitech/src/common/aaqnx.c new file mode 100644 index 000000000..13531be99 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aaqnx.c @@ -0,0 +1,95 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: OS specific Nucleus Graphics Architecture services for +* the QNX operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +/*---------------------------- Global Variables ---------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + (void)device; + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timespec ts; + + clock_gettime(CLOCK_REALTIME, &ts); + value->low = (ts.tv_nsec / 1000 + ts.tv_sec * 1000000); + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aartt.c b/board/MAI/bios_emulator/scitech/src/common/aartt.c new file mode 100644 index 000000000..1a5a67a4e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aartt.c @@ -0,0 +1,89 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the RTTarget-32 operating system environments. +* +****************************************************************************/ + +#include "nucleus/graphics.h" + +/*------------------------- Global Variables ------------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + (void)device; + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aasmx.c b/board/MAI/bios_emulator/scitech/src/common/aasmx.c new file mode 100644 index 000000000..163060f71 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aasmx.c @@ -0,0 +1,83 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: smx32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the smx32 platform -- no vxD support. +* +****************************************************************************/ + +#include "pmapi.h" +#include "nucleus/graphics.h" + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + (void)device; + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aavxd.c b/board/MAI/bios_emulator/scitech/src/common/aavxd.c new file mode 100644 index 000000000..221b02bd9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aavxd.c @@ -0,0 +1,90 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Win32 VxD +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Win32 VxD's. +* +****************************************************************************/ + +#include "sdd/sddhelp.h" + +/*------------------------- Global Variables ------------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Return the internal shared info structure. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + static GA_sharedInfo shared = {0,-1}; + return &shared; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + } + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + VTD_Get_Real_Time(&value->high,&value->low); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/aawin32.c b/board/MAI/bios_emulator/scitech/src/common/aawin32.c new file mode 100644 index 000000000..541df4ac5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/aawin32.c @@ -0,0 +1,264 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Win32 operating system environments. +* +****************************************************************************/ + +#include "pm_help.h" +#include "pmapi.h" +#include +#include +#include +#define STRICT +#define WIN32_LEAN_AND_MEAN +#include + +/*------------------------- Global Variables ------------------------------*/ + +#if GA_MAX_DEVICES > 4 +#error GA_MAX_DEVICES has changed! +#endif + +static ibool haveRDTSC; +static GA_largeInteger countFreq; +static GA_loadDriver_t ORG_GA_loadDriver; +extern HANDLE _PM_hDevice; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +DESCRIPTION: +Get the current graphics driver imports from the VxD + +REMARKS: +This function returns a pointer to the common graphics driver loaded in the +helper VxD. The memory for the VxD is shared between all processes via +the VxD, so that the VxD, 16-bit code and 32-bit code all see the same +state when accessing the graphics binary portable driver. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + DWORD inBuf[1]; /* Buffer to send data to VxD */ + DWORD outBuf[2]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + PM_init(); + inBuf[0] = device; + if (DeviceIoControl(_PM_hDevice, PMHELP_GETSHAREDINFO32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) { + return (GA_sharedInfo*)outBuf[0]; + } + return NULL; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp) +{ + (void)gaExp; + return false; +} + +/**************************************************************************** +REMARKS: +This function initialises the software stereo module by either calling +the Nucleus libraries directly, or calling into the VxD if we are running +on the shared Nucleus libraries loaded by the Windows VxD. +****************************************************************************/ +static ibool NAPI _GA_softStereoInit( + GA_devCtx *dc) +{ + if (_PM_hDevice) { + DWORD inBuf[1]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)dc; + if (DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOINIT32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) { + return outBuf[0]; + } + } + return false; +} + +/**************************************************************************** +REMARKS: +This function turns on software stereo mode, either directly or via the VxD. +****************************************************************************/ +static void NAPI _GA_softStereoOn(void) +{ + if (_PM_hDevice) { + DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOON32, NULL, 0, + NULL, 0, NULL, NULL); + } +} + +/**************************************************************************** +REMARKS: +This function schedules a software stereo mode page flip, either directly +or via the VxD. +****************************************************************************/ +static void NAPI _GA_softStereoScheduleFlip( + N_uint32 leftAddr, + N_uint32 rightAddr) +{ + if (_PM_hDevice) { + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)leftAddr; + inBuf[1] = (ulong)rightAddr; + DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOFLIP32, inBuf, sizeof(inBuf), + NULL, 0, &count, NULL); + } +} + +/**************************************************************************** +REMARKS: +This function turns off software stereo mode, either directly or via the VxD. +****************************************************************************/ +static N_int32 NAPI _GA_softStereoGetFlipStatus(void) +{ + if (_PM_hDevice) { + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOFLIPSTATUS32, NULL, 0, + outBuf, sizeof(outBuf), &count, NULL)) { + return outBuf[0]; + } + } + return 0; +} + +/**************************************************************************** +REMARKS: +This function turns off software stereo mode, either directly or via the VxD. +****************************************************************************/ +static void NAPI _GA_softStereoWaitTillFlipped(void) +{ + while (!_GA_softStereoGetFlipStatus()) + ; +} + +/**************************************************************************** +REMARKS: +This function turns off software stereo mode, either directly or via the VxD. +****************************************************************************/ +static void NAPI _GA_softStereoOff(void) +{ + if (_PM_hDevice) { + DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOOFF32, NULL, 0, + NULL, 0, NULL, NULL); + } +} + +/**************************************************************************** +REMARKS: +This function disable the software stereo handler, either directly or via +the VxD. +****************************************************************************/ +static void NAPI _GA_softStereoExit(void) +{ + if (_PM_hDevice) { + DeviceIoControl(_PM_hDevice, PMHELP_GASTEREOEXIT32, NULL, 0, + NULL, 0, NULL, NULL); + } +} + +/**************************************************************************** +REMARKS: +We hook this function in here so that we can avoid the memory detect and +other destructive sequences in the drivers if we are loading the driver +from a Win32 application (our display drivers in contrast load them inside +the VxD directly, but the control panel applets use this function). +****************************************************************************/ +static GA_devCtx * NAPI _GA_loadDriver( + N_int32 deviceIndex, + N_int32 shared) +{ + GA_devCtx *dc; + DWORD inBuf[1]; + DWORD outBuf[1]; + N_int32 totalMemory = 0,oldIOPL; + + if (deviceIndex >= GA_MAX_DEVICES) + PM_fatalError("DeviceIndex too large in GA_loadDriver!"); + PM_init(); + inBuf[0] = deviceIndex; + if (DeviceIoControl(_PM_hDevice, PMHELP_GETMEMSIZE32, + inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), NULL, NULL)) + totalMemory = outBuf[0]; + if (totalMemory == 0) + totalMemory = 8192; + _GA_exports.GA_forceMemSize(totalMemory,shared); + oldIOPL = PM_setIOPL(3); + dc = ORG_GA_loadDriver(deviceIndex,shared); + PM_setIOPL(oldIOPL); + return dc; +} + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + return true; + } + else if (QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq)) { + haveRDTSC = false; + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + QueryPerformanceCounter((LARGE_INTEGER*)value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/agplib.c b/board/MAI/bios_emulator/scitech/src/common/agplib.c new file mode 100644 index 000000000..476eedc87 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/agplib.c @@ -0,0 +1,219 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Any 32-bit protected mode environment +* +* Description: C module for the Graphics Accelerator Driver API. Uses +* the SciTech PM library for interfacing with DOS +* extender specific functions. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include "nucleus/agp.h" + +/*---------------------------- Global Variables ---------------------------*/ + +#ifndef DEBUG_AGP_DRIVER +static AGP_exports _AGP_exports; +static int loaded = false; +static PE_MODULE *hModBPD = NULL; + +static N_imports _N_imports = { + sizeof(N_imports), + _OS_delay, + }; + +static AGP_imports _AGP_imports = { + sizeof(AGP_imports), + }; +#endif + +#include "pmimp.h" + +/*----------------------------- Implementation ----------------------------*/ + +#define DLL_NAME "agp.bpd" + +#ifndef DEBUG_AGP_DRIVER +/**************************************************************************** +REMARKS: +Fatal error handler for non-exported GA_exports. +****************************************************************************/ +static void _AGP_fatalErrorHandler(void) +{ + PM_fatalError("Unsupported AGP export function called! Please upgrade your copy of AGP!\n"); +} + +/**************************************************************************** +PARAMETERS: +shared - True to load the driver into shared memory. + +REMARKS: +Loads the Nucleus binary portable DLL into memory and initilises it. +****************************************************************************/ +static ibool LoadDriver(void) +{ + AGP_initLibrary_t AGP_initLibrary; + AGP_exports *agpExp; + char filename[PM_MAX_PATH]; + char bpdpath[PM_MAX_PATH]; + int i,max; + ulong *p; + + /* Check if we have already loaded the driver */ + if (loaded) + return true; + PM_init(); + + /* Open the BPD file */ + if (!PM_findBPD(DLL_NAME,bpdpath)) + return false; + strcpy(filename,bpdpath); + strcat(filename,DLL_NAME); + if ((hModBPD = PE_loadLibrary(filename,false)) == NULL) + return false; + if ((AGP_initLibrary = (AGP_initLibrary_t)PE_getProcAddress(hModBPD,"_AGP_initLibrary")) == NULL) + return false; + bpdpath[strlen(bpdpath)-1] = 0; + if (strcmp(bpdpath,PM_getNucleusPath()) == 0) + strcpy(bpdpath,PM_getNucleusConfigPath()); + else { + PM_backslash(bpdpath); + strcat(bpdpath,"config"); + } + if ((agpExp = AGP_initLibrary(bpdpath,filename,GA_getSystemPMImports(),&_N_imports,&_AGP_imports)) == NULL) + PM_fatalError("AGP_initLibrary failed!\n"); + _AGP_exports.dwSize = sizeof(_AGP_exports); + max = sizeof(_AGP_exports)/sizeof(AGP_initLibrary_t); + for (i = 0,p = (ulong*)&_AGP_exports; i < max; i++) + *p++ = (ulong)_AGP_fatalErrorHandler; + memcpy(&_AGP_exports,agpExp,MIN(sizeof(_AGP_exports),agpExp->dwSize)); + loaded = true; + return true; +} + +/* The following are stub entry points that the application calls to + * initialise the Nucleus loader library, and we use this to load our + * driver DLL from disk and initialise the library using it. + */ + +/* {secret} */ +int NAPI AGP_status(void) +{ + if (!loaded) + return nDriverNotFound; + return _AGP_exports.AGP_status(); +} + +/* {secret} */ +const char * NAPI AGP_errorMsg( + N_int32 status) +{ + if (!loaded) + return "Unable to load Nucleus device driver!"; + return _AGP_exports.AGP_errorMsg(status); +} + +/* {secret} */ +AGP_devCtx * NAPI AGP_loadDriver(N_int32 deviceIndex) +{ + if (!LoadDriver()) + return NULL; + return _AGP_exports.AGP_loadDriver(deviceIndex); +} + +/* {secret} */ +void NAPI AGP_unloadDriver( + AGP_devCtx *dc) +{ + if (loaded) + _AGP_exports.AGP_unloadDriver(dc); +} + +/* {secret} */ +void NAPI AGP_getGlobalOptions( + AGP_globalOptions *options) +{ + if (LoadDriver()) + _AGP_exports.AGP_getGlobalOptions(options); +} + +/* {secret} */ +void NAPI AGP_setGlobalOptions( + AGP_globalOptions *options) +{ + if (LoadDriver()) + _AGP_exports.AGP_setGlobalOptions(options); +} + +/* {secret} */ +void NAPI AGP_saveGlobalOptions( + AGP_globalOptions *options) +{ + if (loaded) + _AGP_exports.AGP_saveGlobalOptions(options); +} +#endif + +/* {secret} */ +void NAPI _OS_delay8253(N_uint32 microSeconds); + +/**************************************************************************** +REMARKS: +This function delays for the specified number of microseconds +****************************************************************************/ +void NAPI _OS_delay( + N_uint32 microSeconds) +{ + static ibool inited = false; + static ibool haveRDTSC; + LZTimerObject tm; + + if (!inited) { +#ifndef __WIN32_VXD__ + /* This has been causing problems in VxD's for some reason, so for now */ + /* we avoid using it. */ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + ZTimerInit(); + haveRDTSC = true; + } + else +#endif + haveRDTSC = false; + inited = true; + } + if (haveRDTSC) { + LZTimerOnExt(&tm); + while (LZTimerLapExt(&tm) < microSeconds) + ; + LZTimerOnExt(&tm); + } + else + _OS_delay8253(microSeconds); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/center.c b/board/MAI/bios_emulator/scitech/src/common/center.c new file mode 100644 index 000000000..68e17c2a9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/center.c @@ -0,0 +1,122 @@ +/**************************************************************************** +* +* Display Doctor Windows Interface Code +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code is a proprietary trade secret of | +* |SciTech Software, Inc., located at 505 Wall Street, Chico, CA 95928 | +* |USA (www.scitechsoft.com). ANY UNAUTHORIZED POSSESSION, USE, | +* |VIEWING, COPYING, MODIFICATION OR DISSEMINATION OF THIS CODE IS | +* |STRICTLY PROHIBITED BY LAW. Unless you have current, express | +* |written authorization from SciTech to possess or use this code, you | +* |may be subject to civil and/or criminal penalties. | +* | | +* |If you received this code in error or you would like to report | +* |improper use, please immediately contact SciTech Software, Inc. at | +* |530-894-8400. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: C++ 3.0 +* Environment: Win16 +* +* Description: Dialog driven configuration program for UniVBE and +* WinDirect Professional products. +* +****************************************************************************/ + +#include "center.h" + +/*------------------------------ Implementation ---------------------------*/ + +void _EXPORT CenterWindow(HWND hWndCenter, HWND parent, BOOL repaint) +/**************************************************************************** +* +* Function: CenterWindow +* Parameters: hWndCenter - Window to center +* parent - Handle for parent window +* repaint - true if window should be re-painted +* +* Description: Centers the specified window within the bounds of the +* specified parent window. If the parent window is NULL, then +* we center it using the Desktop window. +* +****************************************************************************/ +{ + HWND hWndParent = (parent ? parent : GetDesktopWindow()); + RECT RectParent; + RECT RectCenter; + int CenterX,CenterY,Height,Width; + + GetWindowRect(hWndParent, &RectParent); + GetWindowRect(hWndCenter, &RectCenter); + + Width = (RectCenter.right - RectCenter.left); + Height = (RectCenter.bottom - RectCenter.top); + CenterX = ((RectParent.right - RectParent.left) - Width) / 2; + CenterY = ((RectParent.bottom - RectParent.top) - Height) / 2; + + if ((CenterX < 0) || (CenterY < 0)) { + /* The Center Window is smaller than the parent window. */ + if (hWndParent != GetDesktopWindow()) { + /* If the parent window is not the desktop use the desktop size. */ + CenterX = (GetSystemMetrics(SM_CXSCREEN) - Width) / 2; + CenterY = (GetSystemMetrics(SM_CYSCREEN) - Height) / 2; + } + CenterX = (CenterX < 0) ? 0: CenterX; + CenterY = (CenterY < 0) ? 0: CenterY; + } + else { + CenterX += RectParent.left; + CenterY += RectParent.top; + } + + /* Copy the values into RectCenter */ + RectCenter.left = CenterX; + RectCenter.right = CenterX + Width; + RectCenter.top = CenterY; + RectCenter.bottom = CenterY + Height; + + /* Move the window to the new location */ + MoveWindow(hWndCenter, RectCenter.left, RectCenter.top, + (RectCenter.right - RectCenter.left), + (RectCenter.bottom - RectCenter.top), repaint); +} + +void _EXPORT CenterLogo(HWND hWndLogo, HWND hWndParent, int CenterY) +/**************************************************************************** +* +* Function: CenterLogo +* Parameters: hWndLogo - Window to center +* hWndParent - Handle for parent window +* CenterY - Top coordinate for logo +* +* Description: Centers the specified window within the bounds of the +* specified parent window in the horizontal direction only. +* +****************************************************************************/ +{ + RECT RectParent; + RECT RectCenter; + int CenterX,Height,Width; + + GetWindowRect(hWndParent, &RectParent); + GetWindowRect(hWndLogo, &RectCenter); + Width = (RectCenter.right - RectCenter.left); + Height = (RectCenter.bottom - RectCenter.top); + CenterX = ((RectParent.right - RectParent.left) - Width) / 2; + + /* Copy the values into RectCenter */ + RectCenter.left = CenterX; + RectCenter.right = CenterX + Width; + RectCenter.top = CenterY; + RectCenter.bottom = CenterY + Height; + + /* Move the window to the new location */ + MoveWindow(hWndLogo, RectCenter.left, RectCenter.top, + (RectCenter.right - RectCenter.left), + (RectCenter.bottom - RectCenter.top), false); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/cmdline.c b/board/MAI/bios_emulator/scitech/src/common/cmdline.c new file mode 100644 index 000000000..531e5e131 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/cmdline.c @@ -0,0 +1,428 @@ +/**************************************************************************** +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: This module contains code to parse the command line, +* extracting options and parameters in standard System V +* style. +* +****************************************************************************/ + +#include +#include +#include +#include "cmdline.h" + +/*------------------------- Global variables ------------------------------*/ + +int nextargv = 1; /* Index into argv array */ +char *nextchar = NULL; /* Pointer to next character */ + +/*-------------------------- Implementation -------------------------------*/ + +#define IS_SWITCH_CHAR(c) ((c) == '-') +#define IS_NOT_SWITCH_CHAR(c) ((c) != '-') + +/**************************************************************************** +DESCRIPTION: +Parse the command line for specific options + +HEADER: +cmdline.h + +PARAMETERS: +argc - Value passed to program through argc variable +argv - Pointer to the argv array passed to the program +format - A string representing the expected format of the command line +argument - Pointer to optional argument on command line + +RETURNS: +Character code representing the next option parsed from the command line by +getcmdopt. Returns ALLDONE (-1) when there are no more parameters to be parsed +on the command line, PARAMETER (-2) when the argument being parsed is a +parameter and not an option switch and lastly INVALID (-3) if an error +occured while parsing the command line. + +REMARKS: +Function to parse the command line option switches in UNIX System V style. +When getcmdopt is called, it returns the character code of the next valid +option that is parsed from the command line as specified by the Format +string. The format string should be in the following form: + + "abcd:e:f:" + +where a,b and c represent single switch style options and the character +code returned by getcmdopt is the only value returned. Also d, e and f +represent options that expect arguments immediately after them on the +command line. The argument that follows the option on the command line is +returned via a reference in the pointer argument. Thus a valid command line +for this format string might be: + + myprogram -adlines -b -f format infile outfile + +where a and b will be returned as single character options with no argument, +while d is returned with the argument lines and f is returned with the +argument format. + +When getcmdopt returns with PARAMETER (we attempted to parse a paramter, not +an option), the global variable NextArgv will hold an index in the argv +array to the argument on the command line AFTER the options, ie in the +above example the string 'infile'. If the parameter is successfully used, +NextArgv should be incremented and getcmdopt can be called again to parse any +more options. Thus you can also have options interspersed throught the +command line. eg: + + myprogram -adlines infile -b outfile -f format + +can be made to be a valid form of the above command line. +****************************************************************************/ +int getcmdopt( + int argc, + char **argv, + char *format, + char **argument) +{ + char ch; + char *formatchar; + + if (argc > nextargv) { + if (nextchar == NULL) { + nextchar = argv[nextargv]; /* Index next argument */ + if (nextchar == NULL) { + nextargv++; + return ALLDONE; /* No more options */ + } + if (IS_NOT_SWITCH_CHAR(*nextchar)) { + nextchar = NULL; + return PARAMETER; /* We have a parameter */ + } + nextchar++; /* Move past switch operator */ + if (IS_SWITCH_CHAR(*nextchar)) { + nextchar = NULL; + return INVALID; /* Ignore rest of line */ + } + } + if ((ch = *(nextchar++)) == 0) { + nextchar = NULL; + return INVALID; /* No options on line */ + } + + if (ch == ':' || (formatchar = strchr(format, ch)) == NULL) + return INVALID; + + if (*(++formatchar) == ':') { /* Expect an argument after option */ + nextargv++; + if (*nextchar == 0) { + if (argc <= nextargv) + return INVALID; + nextchar = argv[nextargv++]; + } + *argument = nextchar; + nextchar = NULL; + } + else { /* We have a switch style option */ + if (*nextchar == 0) { + nextargv++; + nextchar = NULL; + } + *argument = NULL; + } + return ch; /* return the option specifier */ + } + nextchar = NULL; + nextargv++; + return ALLDONE; /* no arguments on command line */ +} + +/**************************************************************************** +PARAMETERS: +optarr - Description for the option we are parsing +argument - String to parse + +RETURNS: +INVALID on error, ALLDONE on success. + +REMARKS: +Parses the argument string depending on the type of argument that is +expected, filling in the argument for that option. Note that to parse a +string, we simply return a pointer to argument. +****************************************************************************/ +static int parse_option( + Option *optarr, + char *argument) +{ + int num_read; + + switch ((int)(optarr->type)) { + case OPT_INTEGER: + num_read = sscanf(argument,"%d",(int*)optarr->arg); + break; + case OPT_HEX: + num_read = sscanf(argument,"%x",(int*)optarr->arg); + break; + case OPT_OCTAL: + num_read = sscanf(argument,"%o",(int*)optarr->arg); + break; + case OPT_UNSIGNED: + num_read = sscanf(argument,"%u",(uint*)optarr->arg); + break; + case OPT_LINTEGER: + num_read = sscanf(argument,"%ld",(long*)optarr->arg); + break; + case OPT_LHEX: + num_read = sscanf(argument,"%lx",(long*)optarr->arg); + break; + case OPT_LOCTAL: + num_read = sscanf(argument,"%lo",(long*)optarr->arg); + break; + case OPT_LUNSIGNED: + num_read = sscanf(argument,"%lu",(ulong*)optarr->arg); + break; + case OPT_FLOAT: + num_read = sscanf(argument,"%f",(float*)optarr->arg); + break; + case OPT_DOUBLE: + num_read = sscanf(argument,"%lf",(double*)optarr->arg); + break; + case OPT_LDOUBLE: + num_read = sscanf(argument,"%Lf",(long double*)optarr->arg); + break; + case OPT_STRING: + num_read = 1; /* This always works */ + *((char**)optarr->arg) = argument; + break; + default: + return INVALID; + } + + if (num_read == 0) + return INVALID; + else + return ALLDONE; +} + +/**************************************************************************** +HEADER: +cmdline.h + +PARAMETERS: +argc - Number of arguments on command line +argv - Array of command line arguments +num_opt - Number of options in option array +optarr - Array to specify how to parse the command line +do_param - Routine to handle a command line parameter + +RETURNS: +ALLDONE, INVALID or HELP + +REMARKS: +Function to parse the command line according to a table of options. This +routine calls getcmdopt above to parse each individual option and attempts +to parse each option into a variable of the specified type. The routine +can parse integers and long integers in either decimal, octal, hexadecimal +notation, unsigned integers and unsigned longs, strings and option switches. +Option switches are simply boolean variables that get turned on if the +switch was parsed. + +Parameters are extracted from the command line by calling a user supplied +routine do_param() to handle each parameter as it is encountered. The +routine do_param() should accept a pointer to the parameter on the command +line and an integer representing how many parameters have been encountered +(ie: 1 if this is the first parameter, 10 if it is the 10th etc), and return +ALLDONE upon successfully parsing it or INVALID if the parameter was invalid. + +We return either ALLDONE if all the options were successfully parsed, +INVALID if an invalid option was encountered or HELP if any of -h, -H or +-? were present on the command line. +****************************************************************************/ +int getargs( + int argc, + char *argv[], + int num_opt, + Option optarr[], + int (*do_param)( + char *param, + int num)) +{ + int i,opt; + char *argument; + int param_num = 1; + char cmdstr[MAXARG*2 + 4]; + + /* Build the command string from the array of options */ + + strcpy(cmdstr,"hH?"); + for (i = 0,opt = 3; i < num_opt; i++,opt++) { + cmdstr[opt] = optarr[i].opt; + if (optarr[i].type != OPT_SWITCH) { + cmdstr[++opt] = ':'; + } + } + cmdstr[opt] = '\0'; + + for (;;) { + opt = getcmdopt(argc,argv,cmdstr,&argument); + switch (opt) { + case 'H': + case 'h': + case '?': + return HELP; + case ALLDONE: + return ALLDONE; + case INVALID: + return INVALID; + case PARAMETER: + if (do_param == NULL) + return INVALID; + if (do_param(argv[nextargv],param_num) == INVALID) + return INVALID; + nextargv++; + param_num++; + break; + default: + + /* Search for the option in the option array. We are + * guaranteed to find it. + */ + + for (i = 0; i < num_opt; i++) { + if (optarr[i].opt == opt) + break; + } + if (optarr[i].type == OPT_SWITCH) + *((ibool*)optarr[i].arg) = true; + else { + if (parse_option(&optarr[i],argument) == INVALID) + return INVALID; + } + break; + } + } +} + +/**************************************************************************** +HEADER: +cmdline.h + +PARAMETERS: +num_opt - Number of options in the table +optarr - Table of option descriptions + +REMARKS: +Prints the description of each option in a standard format to the standard +output device. The description for each option is obtained from the table +of options. +****************************************************************************/ +void print_desc( + int num_opt, + Option optarr[]) +{ + int i; + + for (i = 0; i < num_opt; i++) { + if (optarr[i].type == OPT_SWITCH) + printf(" -%c %s\n",optarr[i].opt,optarr[i].desc); + else + printf(" -%c %s\n",optarr[i].opt,optarr[i].desc); + } +} + +/**************************************************************************** +HEADER: +cmdline.h + +PARAMETERS: +moduleName - Module name for program +cmdLine - Command line to parse +pargc - Pointer to 'argc' parameter +pargv - Pointer to 'argv' parameter +maxArgc - Maximum argv array index + +REMARKS: +Parses a command line from a single string into the C style 'argc' and +'argv' format. Most useful for Windows programs where the command line +is passed in verbatim. +****************************************************************************/ +int parse_commandline( + char *moduleName, + char *cmdLine, + int *pargc, + char *argv[], + int maxArgv) +{ + static char str[512]; + static char filename[260]; + char *prevWord = NULL; + ibool inQuote = FALSE; + ibool noStrip = FALSE; + int argc; + + argc = 0; + strcpy(filename,moduleName); + argv[argc++] = filename; + cmdLine = strncpy(str, cmdLine, sizeof(str)-1); + while (*cmdLine) { + switch (*cmdLine) { + case '"' : + if (prevWord != NULL) { + if (inQuote) { + if (!noStrip) + *cmdLine = '\0'; + argv [argc++] = prevWord; + prevWord = NULL; + } + else + noStrip = TRUE; + } + inQuote = !inQuote; + break; + case ' ' : + case '\t' : + if (!inQuote) { + if (prevWord != NULL) { + *cmdLine = '\0'; + argv [argc++] = prevWord; + prevWord = NULL; + noStrip = FALSE; + } + } + break; + default : + if (prevWord == NULL) + prevWord = cmdLine; + break; + } + if (argc >= maxArgv - 1) + break; + cmdLine++; + } + + if ((prevWord != NULL || (inQuote && prevWord != NULL)) && argc < maxArgv - 1) { + *cmdLine = '\0'; + argv [argc++] = prevWord; + } + argv[argc] = NULL; + + /* Return updated parameters */ + return (*pargc = argc); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gabeos.c b/board/MAI/bios_emulator/scitech/src/common/gabeos.c new file mode 100644 index 000000000..a934bd1cf --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gabeos.c @@ -0,0 +1,146 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Linux operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + /* TODO: We may very well want to provide a system shared library */ + /* that eports the PM functions required by the Nucleus library */ + /* for BeOS here. That will eliminate fatal errors loading new */ + /* drivers on BeOS! */ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timeval t; + gettimeofday(&t, NULL); + value->low = t.tv_sec*1000000 + t.tv_usec; + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gados.c b/board/MAI/bios_emulator/scitech/src/common/gados.c new file mode 100644 index 000000000..d2be77694 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gados.c @@ -0,0 +1,135 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: MSDOS +* +* Description: OS specific Nucleus Graphics Architecture services for +* the MSDOS operating system. +* +****************************************************************************/ + +#include "pm_help.h" +#include "pmapi.h" +#include +#include +#include + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +Nothing to do here for DOS. Basically since DOS has no system wide shared +library mechanism we are essentially screwed if the binary API changes. +By default for 32-bit DOS apps the local Nucleus drivers should always be +used in preference to the system wide Nucleus drivers. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#if !defined(TEST_HARNESS) && !defined(VBETEST) +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the DOS +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/galib.c b/board/MAI/bios_emulator/scitech/src/common/galib.c new file mode 100644 index 000000000..f2eacc3d2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/galib.c @@ -0,0 +1,268 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Any 32-bit protected mode environment +* +* Description: C module for the Graphics Accelerator Driver API. Uses +* the SciTech PM library for interfacing with DOS +* extender specific functions. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) +#include "sdd/sddhelp.h" +#else +#include +#include +#endif + +/*---------------------------- Global Variables ---------------------------*/ + +#ifndef TEST_HARNESS +GA_exports _VARAPI __GA_exports; +static int loaded = false; +static PE_MODULE *hModBPD = NULL; + +static N_imports _N_imports = { + sizeof(N_imports), + _OS_delay, + }; + +static GA_imports _GA_imports = { + sizeof(GA_imports), + GA_getSharedInfo, + GA_TimerInit, + GA_TimerRead, + GA_TimerDifference, + }; +#endif + +/*----------------------------- Implementation ----------------------------*/ + +#define DLL_NAME "graphics.bpd" + +/**************************************************************************** +REMARKS: +This function is no longer used but we must implement it and return NULL +for compatibility with older binary drivers. +****************************************************************************/ +GA_sharedInfo * NAPI GA_getSharedInfo( + int device) +{ + return NULL; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Fatal error handler for non-exported GA_exports. +****************************************************************************/ +static void _GA_fatalErrorHandler(void) +{ + PM_fatalError("Unsupported Nucleus export function called! Please upgrade your copy of Nucleus!\n"); +} + +/**************************************************************************** +PARAMETERS: +shared - True to load the driver into shared memory. + +REMARKS: +Loads the Nucleus binary portable DLL into memory and initilises it. +****************************************************************************/ +static ibool LoadDriver( + ibool shared) +{ + GA_initLibrary_t GA_initLibrary; + GA_exports *gaExp; + char filename[PM_MAX_PATH]; + char bpdpath[PM_MAX_PATH]; + int i,max; + ulong *p; + + /* Check if we have already loaded the driver */ + if (loaded) + return true; + PM_init(); + + /* First try to see if we can find the system wide shared exports + * if they are available. Under OS/2 this connects to our global + * shared Nucleus loader in SDDPMI.DLL. + */ + __GA_exports.dwSize = sizeof(__GA_exports); + if (GA_getSharedExports(&__GA_exports,shared)) + return loaded = true; + + /* Open the BPD file */ + if (!PM_findBPD(DLL_NAME,bpdpath)) + return false; + strcpy(filename,bpdpath); + strcat(filename,DLL_NAME); + if ((hModBPD = PE_loadLibrary(filename,shared)) == NULL) + return false; + if ((GA_initLibrary = (GA_initLibrary_t)PE_getProcAddress(hModBPD,"_GA_initLibrary")) == NULL) + return false; + bpdpath[strlen(bpdpath)-1] = 0; + if (strcmp(bpdpath,PM_getNucleusPath()) == 0) + strcpy(bpdpath,PM_getNucleusConfigPath()); + else { + PM_backslash(bpdpath); + strcat(bpdpath,"config"); + } + if ((gaExp = GA_initLibrary(shared,bpdpath,filename,GA_getSystemPMImports(),&_N_imports,&_GA_imports)) == NULL) + PM_fatalError("GA_initLibrary failed!\n"); + + /* Initialize all default imports to point to fatal error handler + * for upwards compatibility, and copy the exported functions. + */ + max = sizeof(__GA_exports)/sizeof(GA_initLibrary_t); + for (i = 0,p = (ulong*)&__GA_exports; i < max; i++) + *p++ = (ulong)_GA_fatalErrorHandler; + memcpy(&__GA_exports,gaExp,MIN(sizeof(__GA_exports),gaExp->dwSize)); + loaded = true; + return true; +} + +/* The following are stub entry points that the application calls to + * initialise the Nucleus loader library, and we use this to load our + * driver DLL from disk and initialise the library using it. + */ + +/* {secret} */ +int NAPI GA_status(void) +{ + if (!loaded) + return nDriverNotFound; + return __GA_exports.GA_status(); +} + +/* {secret} */ +const char * NAPI GA_errorMsg( + N_int32 status) +{ + if (!loaded) + return "Unable to load Nucleus device driver!"; + return __GA_exports.GA_errorMsg(status); +} + +/* {secret} */ +int NAPI GA_getDaysLeft(N_int32 shared) +{ + if (!LoadDriver(shared)) + return -1; + return __GA_exports.GA_getDaysLeft(shared); +} + +/* {secret} */ +int NAPI GA_registerLicense(uchar *license,N_int32 shared) +{ + if (!LoadDriver(shared)) + return 0; + return __GA_exports.GA_registerLicense(license,shared); +} + +/* {secret} */ +ibool NAPI GA_loadInGUI(N_int32 shared) +{ + if (!LoadDriver(shared)) + return false; + return __GA_exports.GA_loadInGUI(shared); +} + +/* {secret} */ +int NAPI GA_enumerateDevices(N_int32 shared) +{ + if (!LoadDriver(shared)) + return 0; + return __GA_exports.GA_enumerateDevices(shared); +} + +/* {secret} */ +GA_devCtx * NAPI GA_loadDriver(N_int32 deviceIndex,N_int32 shared) +{ + if (!LoadDriver(shared)) + return NULL; + return __GA_exports.GA_loadDriver(deviceIndex,shared); +} + +/* {secret} */ +void NAPI GA_getGlobalOptions( + GA_globalOptions *options, + ibool shared) +{ + if (LoadDriver(shared)) + __GA_exports.GA_getGlobalOptions(options,shared); +} + +/* {secret} */ +PE_MODULE * NAPI GA_loadLibrary( + const char *szBPDName, + ulong *size, + ibool shared) +{ + if (!LoadDriver(shared)) + return NULL; + return __GA_exports.GA_loadLibrary(szBPDName,size,shared); +} + +/* {secret} */ +GA_devCtx * NAPI GA_getCurrentDriver( + N_int32 deviceIndex) +{ + /* Bail for older drivers that didn't export this function! */ + if (!__GA_exports.GA_getCurrentDriver) + return NULL; + return __GA_exports.GA_getCurrentDriver(deviceIndex); +} + +/* {secret} */ +REF2D_driver * NAPI GA_getCurrentRef2d( + N_int32 deviceIndex) +{ + /* Bail for older drivers that didn't export this function! */ + if (!__GA_exports.GA_getCurrentRef2d) + return NULL; + return __GA_exports.GA_getCurrentRef2d(deviceIndex); +} + +/* {secret} */ +int NAPI GA_isOEMVersion(ibool shared) +{ + if (!LoadDriver(shared)) + return 0; + return __GA_exports.GA_isOEMVersion(shared); +} + +/* {secret} */ +N_uint32 * NAPI GA_getLicensedDevices(ibool shared) +{ + if (!LoadDriver(shared)) + return 0; + return __GA_exports.GA_getLicensedDevices(shared); +} +#endif diff --git a/board/MAI/bios_emulator/scitech/src/common/galinux.c b/board/MAI/bios_emulator/scitech/src/common/galinux.c new file mode 100644 index 000000000..47e4e8581 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/galinux.c @@ -0,0 +1,148 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Linux operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +/*---------------------------- Global Variables ---------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + /* TODO: We may very well want to provide a system shared library */ + /* that eports the PM functions required by the Nucleus library */ + /* for Linux here. That will eliminate fatal errors loading new */ + /* drivers on Linux! */ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timeval t; + gettimeofday(&t, NULL); + value->low = t.tv_sec*1000000 + t.tv_usec; + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gantdrv.c b/board/MAI/bios_emulator/scitech/src/common/gantdrv.c new file mode 100644 index 000000000..050f73767 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gantdrv.c @@ -0,0 +1,136 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: NT device driver +* +* Description: OS specific Nucleus Graphics Architecture services for +* the NT device drivers. +* +****************************************************************************/ + +#include "sdd/sddhelp.h" + +/*------------------------- Global Variables ------------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +Nothing special for this OS. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + } + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + KeQuerySystemTime((LARGE_INTEGER*)value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gaos2.c b/board/MAI/bios_emulator/scitech/src/common/gaos2.c new file mode 100644 index 000000000..26e6503e5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gaos2.c @@ -0,0 +1,248 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: OS/2 32-bit +* +* Description: OS specific Nucleus Graphics Architecture services for +* the OS/2 operating system environments. +* +****************************************************************************/ + +#include "pm_help.h" +#define INCL_DOSERRORS +#define INCL_DOS +#define INCL_SUB +#define INCL_VIO +#define INCL_KBD +#include + +/*--------------------------- Global variables ----------------------------*/ + +static ibool haveRDTSC = false; +static ulong parms[3]; /* Must not cross 64Kb boundary! */ +static ulong result[4]; /* Must not cross 64Kb boundary! */ + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +func - Helper device driver function to call + +RETURNS: +First return value from the device driver in parmsOut[0] + +REMARKS: +Function to open our helper device driver, call it and close the file +handle. Note that we have to open the device driver for every call because +of two problems: + + 1. We cannot open a single file handle in a DLL that is shared amongst + programs, since every process must have it's own open file handle. + + 2. For some reason there appears to be a limit of about 12 open file + handles on a device driver in the system. Hence when we open more + than about 12 file handles things start to go very strange. + +Hence we simply open the file handle every time that we need to call the +device driver to work around these problems. +****************************************************************************/ +static ulong CallSDDHelp( + int func) +{ + static ulong inLen; /* Must not cross 64Kb boundary! */ + static ulong outLen; /* Must not cross 64Kb boundary! */ + HFILE hSDDHelp; + + /* If this code in here fails, we are screwed! Many of our drivers + * use this code and don't have a C library, so we simply assume we + * can't fail here. + */ + DosOpen(PMHELP_NAME,&hSDDHelp,&result[0],0,0, + FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, + NULL); + DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,func, + &parms, inLen = sizeof(parms), &inLen, + &result, outLen = sizeof(result), &outLen); + DosClose(hSDDHelp); + return result[0]; +} + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +For OS/2 we don't need to do anything special because Nucleus is always +loaded via the shared SDDPMI driver when SDD is loaded so we don't need +a system wide PM library imports function. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +PARAMETERS: +gaExp - Place to store the exported functions +shared - True if connecting to the shared, global Nucleus driver + +REMARKS: +For OS/2 if SDD is loaded we *always* connect to the shared Nucleus functions +contained within the SDDPMI driver. This allows the Nucleus functions contained +within this driver to be utilised by all Nucleus apps in the system and +maintains a consistent state between versions. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + /* In test harness mode, we need to load a local copy of Nucleus */ +#if !defined (TEST_HARNESS) || defined (DEBUG_SDDPMI) + HMODULE hModSDDPMI; + char buf[80]; + GA_exports *exp; + + /* Initialise the PM library and connect to our runtime DLL's */ + PM_init(); + if (CallSDDHelp(PMHELP_GETSHAREDEXP) != 0) { + /* We have found the shared Nucleus exports. Because not all processes + * map to SDDPMI.DLL, we need to ensure that we connect to this + * DLL so that it gets mapped into our address space (that is + * where the shared Nucleus loader code is located). Simply doing a + * DosLoadModule on it is enough for this. + */ + DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"SDDPMI.DLL",&hModSDDPMI); + exp = (GA_exports*)result[0]; + memcpy(gaExp,exp,MIN(gaExp->dwSize,exp->dwSize)); + return true; + } +#endif + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + DosTmrQueryTime((QWORD*)value); +} + +/**************************************************************************** +REMARKS: +On OS/2, we need special memory allocation functions if we build SDDPMI in +test harness mode. But if we build GATest etc. in test mode, we want to use +the normal C runtime functions, so route them back here. +****************************************************************************/ + +#if defined (TEST_HARNESS) && !defined (DEBUG_SDDPMI) + +/* Undefine these macros first or we'll recurse to hell! */ +#undef malloc +#undef calloc +#undef realloc +#undef free + +void *SDDPMI_malloc(size_t size) { + return malloc(size); +} + +void *SDDPMI_calloc(size_t num, size_t size) { + return calloc(num, size); +} + +void SDDPMI_free(void *ptr) { + free(ptr); +} + +void *SDDPMI_realloc(void *ptr, size_t size) { + return realloc(ptr, size); +} + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/common/gaqnx.c b/board/MAI/bios_emulator/scitech/src/common/gaqnx.c new file mode 100644 index 000000000..525d66286 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gaqnx.c @@ -0,0 +1,149 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: OS specific Nucleus Graphics Architecture services for +* the QNX operating system. +* +****************************************************************************/ + +#include "nucleus/graphics.h" +#include + +/*---------------------------- Global Variables ---------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + /* TODO: We may very well want to provide a system shared library */ + /* that eports the PM functions required by the Nucleus library */ + /* for QNX here. That will eliminate fatal errors loading new */ + /* drivers on QNX! */ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + haveRDTSC = true; + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else { + struct timespec ts; + + clock_gettime(CLOCK_REALTIME, &ts); + value->low = (ts.tv_nsec / 1000 + ts.tv_sec * 1000000); + value->high = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gartt.c b/board/MAI/bios_emulator/scitech/src/common/gartt.c new file mode 100644 index 000000000..3a41f59c1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gartt.c @@ -0,0 +1,139 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the RTTarget-32 operating system environments. +* +****************************************************************************/ + +#include "nucleus/graphics.h" + +/*------------------------- Global Variables ------------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gasmx.c b/board/MAI/bios_emulator/scitech/src/common/gasmx.c new file mode 100644 index 000000000..ae31941f4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gasmx.c @@ -0,0 +1,133 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: smx32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the smx32 platform -- no vxD support. +* +****************************************************************************/ + +#include "pmapi.h" +#include "nucleus/graphics.h" + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + _GA_readTimeStamp(value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gavxd.c b/board/MAI/bios_emulator/scitech/src/common/gavxd.c new file mode 100644 index 000000000..fc8ba8d65 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gavxd.c @@ -0,0 +1,136 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Win32 VxD +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Win32 VxD's. +* +****************************************************************************/ + +#include "sdd/sddhelp.h" + +/*------------------------- Global Variables ------------------------------*/ + +static ibool haveRDTSC; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + PM_setLocalBPDPath(path); +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +Nothing special for this OS. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + return &_PM_imports; +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + (void)gaExp; + (void)shared; + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + } + return true; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + VTD_Get_Real_Time(&value->high,&value->low); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gawin32.c b/board/MAI/bios_emulator/scitech/src/common/gawin32.c new file mode 100644 index 000000000..69443344f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gawin32.c @@ -0,0 +1,255 @@ +/**************************************************************************** +* +* SciTech Nucleus Graphics Architecture +* +* Copyright (C) 1991-1998 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code contains proprietary technology | +* |owned by SciTech Software, Inc., located at 505 Wall Street, | +* |Chico, CA 95928 USA (http://www.scitechsoft.com). | +* | | +* |The contents of this file are subject to the SciTech Nucleus | +* |License; you may *not* use this file or related software except in | +* |compliance with the License. You may obtain a copy of the License | +* |at http://www.scitechsoft.com/nucleus-license.txt | +* | | +* |Software distributed under the License is distributed on an | +* |"AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | +* |implied. See the License for the specific language governing | +* |rights and limitations under the License. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: OS specific Nucleus Graphics Architecture services for +* the Win32 operating system environments. +* +****************************************************************************/ + +#include "pm_help.h" +#include "pmapi.h" +#include +#include +#include +#define STRICT +#define WIN32_LEAN_AND_MEAN +#include + +/*------------------------- Global Variables ------------------------------*/ + +#define DLL_NAME "nga_w32.dll" + +extern HANDLE _PM_hDevice; +static HMODULE hModDLL = NULL; +static ibool useRing0Driver = false; +static ibool haveRDTSC; +static GA_largeInteger countFreq; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Loads the shared "nga_w32.dll" library from disk and connects to it. This +library is *always* located in the same directory as the Nucleus +graphics.bpd file. +****************************************************************************/ +static ibool LoadSharedDLL(void) +{ + char filename[PM_MAX_PATH]; + char bpdpath[PM_MAX_PATH]; + + /* Check if we have already loaded the DLL */ + if (hModDLL) + return true; + PM_init(); + + /* Open the DLL file */ + if (!PM_findBPD(DLL_NAME,bpdpath)) + return false; + strcpy(filename,bpdpath); + strcat(filename,DLL_NAME); + if ((hModDLL = LoadLibrary(filename)) == NULL) + return false; + return true; +} + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. + +Note that for Win32 we also call into the loaded PMHELP device driver +as necessary to change the local Nucleus path for system wide Nucleus +drivers. +****************************************************************************/ +void NAPI GA_setLocalPath( + const char *path) +{ + DWORD inBuf[1]; + DWORD outBuf[1],outCnt; + + PM_setLocalBPDPath(path); + if (_PM_hDevice != INVALID_HANDLE_VALUE) { + inBuf[0] = (DWORD)path; + DeviceIoControl(_PM_hDevice, PMHELP_GASETLOCALPATH32, + inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &outCnt, NULL); + } +} + +/**************************************************************************** +RETURNS: +Pointer to the system wide PM library imports, or the internal version if none + +REMARKS: +In order to support deploying new Nucleus drivers that may require updated +PM library functions, we check here to see if there is a system wide version +of the PM functions available. If so we return those functions for use with +the system wide Nucleus drivers, otherwise the compiled in version of the PM +library is used with the application local version of Nucleus. +****************************************************************************/ +PM_imports * NAPI GA_getSystemPMImports(void) +{ + PM_imports * pmImp; + PM_imports * (NAPIP _GA_getSystemPMImports)(void); + + if (LoadSharedDLL()) { + /* Note that Visual C++ build DLL's with only a single underscore in front + * of the exported name while Watcom C provides two of them. We check for + * both to allow working with either compiled DLL. + */ + if ((_GA_getSystemPMImports = (void*)GetProcAddress(hModDLL,"_GA_getSystemPMImports")) != NULL) { + if ((_GA_getSystemPMImports = (void*)GetProcAddress(hModDLL,"__GA_getSystemPMImports")) != NULL) { + pmImp = _GA_getSystemPMImports(); + memcpy(&_PM_imports,pmImp,MIN(_PM_imports.dwSize,pmImp->dwSize)); + return pmImp; + } + } + } + return &_PM_imports; +} + +/**************************************************************************** +PARAMETERS: +gaExp - Place to store the exported functions +shared - True if connecting to the shared, global Nucleus driver + +REMARKS: +For Win32 if we are connecting to the shared, global Nucleus driver (loaded +at ring 0) then we need to load a special nga_w32.dll library which contains +thunks to call down into the Ring 0 device driver as necessary. If we are +connecting to the application local Nucleus drivers (ie: Nucleus on DirectDraw +emulation layer) then we do nothing here. +****************************************************************************/ +ibool NAPI GA_getSharedExports( + GA_exports *gaExp, + ibool shared) +{ + GA_exports * exp; + GA_exports * (NAPIP _GA_getSystemGAExports)(void); + + useRing0Driver = false; + if (shared) { + if (!LoadSharedDLL()) + PM_fatalError("Unable to load " DLL_NAME "!"); + if ((_GA_getSystemGAExports = (void*)GetProcAddress(hModDLL,"_GA_getSystemGAExports")) == NULL) + if ((_GA_getSystemGAExports = (void*)GetProcAddress(hModDLL,"__GA_getSystemGAExports")) == NULL) + PM_fatalError("Unable to load " DLL_NAME "!"); + exp = _GA_getSystemGAExports(); + memcpy(gaExp,exp,MIN(gaExp->dwSize,exp->dwSize)); + useRing0Driver = true; + return true; + } + return false; +} + +#ifndef TEST_HARNESS +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI GA_queryFunctions( + GA_devCtx *dc, + N_uint32 id, + void _FAR_ *funcs) +{ + static ibool (NAPIP _GA_queryFunctions)(GA_devCtx *dc,N_uint32 id,void _FAR_ *funcs) = NULL; + + if (useRing0Driver) { + /* Call the version in nga_w32.dll if it is loaded */ + if (!_GA_queryFunctions) { + if ((_GA_queryFunctions = (void*)GetProcAddress(hModDLL,"_GA_queryFunctions")) == NULL) + if ((_GA_queryFunctions = (void*)GetProcAddress(hModDLL,"__GA_queryFunctions")) == NULL) + PM_fatalError("Unable to get exports from " DLL_NAME "!"); + } + return _GA_queryFunctions(dc,id,funcs); + } + return __GA_exports.GA_queryFunctions(dc,id,funcs); +} + +/**************************************************************************** +REMARKS: +Nothing special for this OS +****************************************************************************/ +ibool NAPI REF2D_queryFunctions( + REF2D_driver *ref2d, + N_uint32 id, + void _FAR_ *funcs) +{ + static ibool (NAPIP _REF2D_queryFunctions)(REF2D_driver *ref2d,N_uint32 id,void _FAR_ *funcs) = NULL; + + if (useRing0Driver) { + /* Call the version in nga_w32.dll if it is loaded */ + if (!_REF2D_queryFunctions) { + if ((_REF2D_queryFunctions = (void*)GetProcAddress(hModDLL,"_REF2D_queryFunctions")) == NULL) + if ((_REF2D_queryFunctions = (void*)GetProcAddress(hModDLL,"__REF2D_queryFunctions")) == NULL) + PM_fatalError("Unable to get exports from " DLL_NAME "!"); + } + return _REF2D_queryFunctions(ref2d,id,funcs); + } + return __GA_exports.REF2D_queryFunctions(ref2d,id,funcs); +} +#endif + +/**************************************************************************** +REMARKS: +This function initialises the high precision timing functions for the +Nucleus loader library. +****************************************************************************/ +ibool NAPI GA_TimerInit(void) +{ + if (_GA_haveCPUID() && (_GA_getCPUIDFeatures() & CPU_HaveRDTSC) != 0) { + haveRDTSC = true; + return true; + } + else if (QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq)) { + haveRDTSC = false; + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +This function reads the high resolution timer. +****************************************************************************/ +void NAPI GA_TimerRead( + GA_largeInteger *value) +{ + if (haveRDTSC) + _GA_readTimeStamp(value); + else + QueryPerformanceCounter((LARGE_INTEGER*)value); +} diff --git a/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c b/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c new file mode 100644 index 000000000..1d547e9ab --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/gtfcalc.c @@ -0,0 +1,436 @@ +/**************************************************************************** +* +* VESA Generalized Timing Formula (GTF) +* Version 1.1 +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Developed by: SciTech Software, Inc. +* +* Language: ANSI C +* Environment: Any. +* +* Description: C module for generating GTF compatible timings given a set +* of input requirements. Translated from the original GTF +* 1.14 spreadsheet definition. +* +* Compile with #define TESTING to build a command line test +* program. +* +* NOTE: The code in here has been written for clarity and +* to follow the original GTF spec as closely as +* possible. +* +****************************************************************************/ + +#include "gtf.h" +#ifndef __WIN32_VXD__ +#include +#include +#include +#include +#include +#endif + +/*------------------------- Global Variables ------------------------------*/ + +static GTF_constants GC = { + 1.8, /* Margin size as percentage of display */ + 8, /* Character cell granularity */ + 1, /* Minimum front porch in lines/chars */ + 3, /* Width of V sync in lines */ + 8, /* Width of H sync as percent of total */ + 550, /* Minimum vertical sync + back porch (us) */ + 600, /* Blanking formula gradient */ + 40, /* Blanking formula offset */ + 128, /* Blanking formula scaling factor */ + 20, /* Blanking formula scaling factor weight */ + }; + +/*-------------------------- Implementation -------------------------------*/ + +#ifdef __WIN32_VXD__ +/* These functions are not supported in a VxD, so we stub them out so this + * module will at least compile. Calling the functions in here will do + * something wierd! + */ +double sqrt(double x) +{ return x; } + +double floor(double x) +{ return x; } + +double pow(double x,double y) +{ return x*y; } +#endif + +static double round(double v) +{ + return floor(v + 0.5); +} + +static void GetInternalConstants(GTF_constants *c) +/**************************************************************************** +* +* Function: GetInternalConstants +* Parameters: c - Place to store the internal constants +* +* Description: Calculates the rounded, internal set of GTF constants. +* These constants are different to the real GTF constants +* that can be set up for the monitor. The calculations to +* get these real constants are defined in the 'Work Area' +* after the constants are defined in the Excel spreadsheet. +* +****************************************************************************/ +{ + c->margin = GC.margin; + c->cellGran = round(GC.cellGran); + c->minPorch = round(GC.minPorch); + c->vSyncRqd = round(GC.vSyncRqd); + c->hSync = GC.hSync; + c->minVSyncBP = GC.minVSyncBP; + if (GC.k == 0) + c->k = 0.001; + else + c->k = GC.k; + c->m = (c->k / 256) * GC.m; + c->c = (GC.c - GC.j) * (c->k / 256) + GC.j; + c->j = GC.j; +} + +void GTF_calcTimings(double hPixels,double vLines,double freq, + int type,ibool wantMargins,ibool wantInterlace,GTF_timings *t) +/**************************************************************************** +* +* Function: GTF_calcTimings +* Parameters: hPixels - X resolution +* vLines - Y resolution +* freq - Frequency (Hz, KHz or MHz depending on type) +* type - 1 - vertical, 2 - horizontal, 3 - dot clock +* margins - True if margins should be generated +* interlace - True if interlaced timings to be generated +* t - Place to store the resulting timings +* +* Description: Calculates a set of GTF timing parameters given a specified +* resolution and vertical frequency. The horizontal frequency +* and dot clock will be automatically generated by this +* routines. +* +* For interlaced modes the CRTC parameters are calculated for +* a single field, so will be half what would be used in +* a non-interlaced mode. +* +****************************************************************************/ +{ + double interlace,vFieldRate,hPeriod; + double topMarginLines,botMarginLines; + double leftMarginPixels,rightMarginPixels; + double hPeriodEst,vSyncBP,vBackPorch; + double vTotalLines,vFieldRateEst; + double hTotalPixels,hTotalActivePixels,hBlankPixels; + double idealDutyCycle,hSyncWidth,hSyncBP,hBackPorch; + double idealHPeriod; + double vFreq,hFreq,dotClock; + GTF_constants c; + + /* Get rounded GTF constants used for internal calculations */ + GetInternalConstants(&c); + + /* Move input parameters into appropriate variables */ + vFreq = hFreq = dotClock = freq; + + /* Round pixels to character cell granularity */ + hPixels = round(hPixels / c.cellGran) * c.cellGran; + + /* For interlaced mode halve the vertical parameters, and double + * the required field refresh rate. + */ + vFieldRate = vFreq; + interlace = 0; + if (wantInterlace) + dotClock *= 2; + + /* Determine the lines for margins */ + if (wantMargins) { + topMarginLines = round(c.margin / 100 * vLines); + botMarginLines = round(c.margin / 100 * vLines); + } + else { + topMarginLines = 0; + botMarginLines = 0; + } + + if (type != GTF_lockPF) { + if (type == GTF_lockVF) { + /* Estimate the horizontal period */ + hPeriodEst = ((1/vFieldRate) - (c.minVSyncBP/1000000)) / + (vLines + (2*topMarginLines) + c.minPorch + interlace) * 1000000; + + /* Find the number of lines in vSync + back porch */ + vSyncBP = round(c.minVSyncBP / hPeriodEst); + } + else if (type == GTF_lockHF) { + /* Find the number of lines in vSync + back porch */ + vSyncBP = round((c.minVSyncBP * hFreq) / 1000); + } + + /* Find the number of lines in the V back porch alone */ + vBackPorch = vSyncBP - c.vSyncRqd; + + /* Find the total number of lines in the vertical period */ + vTotalLines = vLines + topMarginLines + botMarginLines + vSyncBP + + interlace + c.minPorch; + + if (type == GTF_lockVF) { + /* Estimate the vertical frequency */ + vFieldRateEst = 1000000 / (hPeriodEst * vTotalLines); + + /* Find the actual horizontal period */ + hPeriod = (hPeriodEst * vFieldRateEst) / vFieldRate; + + /* Find the actual vertical field frequency */ + vFieldRate = 1000000 / (hPeriod * vTotalLines); + } + else if (type == GTF_lockHF) { + /* Find the actual vertical field frequency */ + vFieldRate = (hFreq / vTotalLines) * 1000; + } + } + + /* Find the number of pixels in the left and right margins */ + if (wantMargins) { + leftMarginPixels = round(hPixels * c.margin) / (100 * c.cellGran); + rightMarginPixels = round(hPixels * c.margin) / (100 * c.cellGran); + } + else { + leftMarginPixels = 0; + rightMarginPixels = 0; + } + + /* Find the total number of active pixels in image + margins */ + hTotalActivePixels = hPixels + leftMarginPixels + rightMarginPixels; + + if (type == GTF_lockVF) { + /* Find the ideal blanking duty cycle */ + idealDutyCycle = c.c - ((c.m * hPeriod) / 1000); + } + else if (type == GTF_lockHF) { + /* Find the ideal blanking duty cycle */ + idealDutyCycle = c.c - (c.m / hFreq); + } + else if (type == GTF_lockPF) { + /* Find ideal horizontal period from blanking duty cycle formula */ + idealHPeriod = (((c.c - 100) + (sqrt((pow(100-c.c,2)) + + (0.4 * c.m * (hTotalActivePixels + rightMarginPixels + + leftMarginPixels) / dotClock)))) / (2 * c.m)) * 1000; + + /* Find the ideal blanking duty cycle */ + idealDutyCycle = c.c - ((c.m * idealHPeriod) / 1000); + } + + /* Find the number of pixels in blanking time */ + hBlankPixels = round((hTotalActivePixels * idealDutyCycle) / + ((100 - idealDutyCycle) * c.cellGran)) * c.cellGran; + + /* Find the total number of pixels */ + hTotalPixels = hTotalActivePixels + hBlankPixels; + + /* Find the horizontal back porch */ + hBackPorch = round((hBlankPixels / 2) / c.cellGran) * c.cellGran; + + /* Find the horizontal sync width */ + hSyncWidth = round(((c.hSync/100) * hTotalPixels) / c.cellGran) * c.cellGran; + + /* Find the horizontal sync + back porch */ + hSyncBP = hBackPorch + hSyncWidth; + + if (type == GTF_lockPF) { + /* Find the horizontal frequency */ + hFreq = (dotClock / hTotalPixels) * 1000; + + /* Find the number of lines in vSync + back porch */ + vSyncBP = round((c.minVSyncBP * hFreq) / 1000); + + /* Find the number of lines in the V back porch alone */ + vBackPorch = vSyncBP - c.vSyncRqd; + + /* Find the total number of lines in the vertical period */ + vTotalLines = vLines + topMarginLines + botMarginLines + vSyncBP + + interlace + c.minPorch; + + /* Find the actual vertical field frequency */ + vFieldRate = (hFreq / vTotalLines) * 1000; + } + else { + if (type == GTF_lockVF) { + /* Find the horizontal frequency */ + hFreq = 1000 / hPeriod; + } + else if (type == GTF_lockHF) { + /* Find the horizontal frequency */ + hPeriod = 1000 / hFreq; + } + + /* Find the pixel clock frequency */ + dotClock = hTotalPixels / hPeriod; + } + + /* Return the computed frequencies */ + t->vFreq = vFieldRate; + t->hFreq = hFreq; + t->dotClock = dotClock; + + /* Determine the vertical timing parameters */ + t->h.hTotal = (int)hTotalPixels; + t->h.hDisp = (int)hTotalActivePixels; + t->h.hSyncStart = t->h.hTotal - (int)hSyncBP; + t->h.hSyncEnd = t->h.hTotal - (int)hBackPorch; + t->h.hFrontPorch = t->h.hSyncStart - t->h.hDisp; + t->h.hSyncWidth = (int)hSyncWidth; + t->h.hBackPorch = (int)hBackPorch; + + /* Determine the vertical timing parameters */ + t->v.vTotal = (int)vTotalLines; + t->v.vDisp = (int)vLines; + t->v.vSyncStart = t->v.vTotal - (int)vSyncBP; + t->v.vSyncEnd = t->v.vTotal - (int)vBackPorch; + t->v.vFrontPorch = t->v.vSyncStart - t->v.vDisp; + t->v.vSyncWidth = (int)c.vSyncRqd; + t->v.vBackPorch = (int)vBackPorch; + if (wantInterlace) { + /* Halve the timings for interlaced modes */ + t->v.vTotal /= 2; + t->v.vDisp /= 2; + t->v.vSyncStart /= 2; + t->v.vSyncEnd /= 2; + t->v.vFrontPorch /= 2; + t->v.vSyncWidth /= 2; + t->v.vBackPorch /= 2; + t->dotClock /= 2; + } + + /* Mark as GTF timing using the sync polarities */ + t->interlace = (wantInterlace) ? 'I' : 'N'; + t->hSyncPol = '-'; + t->vSyncPol = '+'; +} + +void GTF_getConstants(GTF_constants *constants) +{ *constants = GC; } + +void GTF_setConstants(GTF_constants *constants) +{ GC = *constants; } + +#ifdef TESTING_GTF + +void main(int argc,char *argv[]) +{ + FILE *f; + double xPixels,yPixels,freq; + ibool interlace; + GTF_timings t; + + if (argc != 5 && argc != 6) { + printf("Usage: GTFCALC [[Hz] [KHz] [MHz]] [I]\n"); + printf("\n"); + printf("where is the horizontal resolution of the mode, is the\n"); + printf("vertical resolution of the mode. The value will be the frequency to\n"); + printf("drive the calculations, and will be either the vertical frequency (in Hz)\n"); + printf("the horizontal frequency (in KHz) or the dot clock (in MHz). To generate\n"); + printf("timings for an interlaced mode, add 'I' to the end of the command line.\n"); + printf("\n"); + printf("For example to generate timings for 640x480 at 60Hz vertical:\n"); + printf("\n"); + printf(" GTFCALC 640 480 60 Hz\n"); + printf("\n"); + printf("For example to generate timings for 640x480 at 31.5KHz horizontal:\n"); + printf("\n"); + printf(" GTFCALC 640 480 31.5 KHz\n"); + printf("\n"); + printf("For example to generate timings for 640x480 with a 25.175Mhz dot clock:\n"); + printf("\n"); + printf(" GTFCALC 640 480 25.175 MHz\n"); + printf("\n"); + printf("GTFCALC will print a summary of the results found, and dump the CRTC\n"); + printf("values to the UVCONFIG.CRT file in the format used by SciTech Display Doctor.\n"); + exit(1); + } + + /* Get values from command line */ + xPixels = atof(argv[1]); + yPixels = atof(argv[2]); + freq = atof(argv[3]); + interlace = ((argc == 6) && (argv[5][0] == 'I')); + + /* Compute the CRTC timings */ + if (toupper(argv[4][0]) == 'H') + GTF_calcTimings(xPixels,yPixels,freq,GTF_lockVF,false,interlace,&t); + else if (toupper(argv[4][0]) == 'K') + GTF_calcTimings(xPixels,yPixels,freq,GTF_lockHF,false,interlace,&t); + else if (toupper(argv[4][0]) == 'M') + GTF_calcTimings(xPixels,yPixels,freq,GTF_lockPF,false,interlace,&t); + else { + printf("Unknown command line!\n"); + exit(1); + } + + /* Dump summary info to standard output */ + printf("CRTC values for %.0fx%.0f @ %.2f %s\n", xPixels, yPixels, freq, argv[4]); + printf("\n"); + printf(" hTotal = %-4d vTotal = %-4d\n", + t.h.hTotal, t.v.vTotal); + printf(" hDisp = %-4d vDisp = %-4d\n", + t.h.hDisp, t.v.vDisp); + printf(" hSyncStart = %-4d vSyncStart = %-4d\n", + t.h.hSyncStart, t.v.vSyncStart); + printf(" hSyncEnd = %-4d vSyncEnd = %-4d\n", + t.h.hSyncEnd, t.v.vSyncEnd); + printf(" hFrontPorch = %-4d vFrontPorch = %-4d\n", + t.h.hFrontPorch, t.v.vFrontPorch); + printf(" hSyncWidth = %-4d vSyncWidth = %-4d\n", + t.h.hSyncWidth, t.v.vSyncWidth); + printf(" hBackPorch = %-4d vBackPorch = %-4d\n", + t.h.hBackPorch, t.v.vBackPorch); + printf("\n"); + printf(" Interlaced = %s\n", (t.interlace == 'I') ? "Yes" : "No"); + printf(" H sync pol = %c\n", t.hSyncPol); + printf(" V sync pol = %c\n", t.vSyncPol); + printf("\n"); + printf(" Vert freq = %.2f Hz\n", t.vFreq); + printf(" Horiz freq = %.2f KHz\n", t.hFreq); + printf(" Dot Clock = %.2f Mhz\n", t.dotClock); + + /* Dump to file in format used by SciTech Display Doctor */ + if ((f = fopen("UVCONFIG.CRT","w")) != NULL) { + fprintf(f, "[%.0f %.0f]\n", xPixels, yPixels); + fprintf(f, "%d %d %d %d '%c' %s\n", + t.h.hTotal, t.h.hDisp, + t.h.hSyncStart, t.h.hSyncEnd, + t.hSyncPol, (t.interlace == 'I') ? "I" : "NI"); + fprintf(f, "%d %d %d %d '%c'\n", + t.v.vTotal, t.v.vDisp, + t.v.vSyncStart, t.v.vSyncEnd, + t.vSyncPol); + fprintf(f, "%.2f\n", t.dotClock); + fclose(f); + } +} + +#endif /* TESTING */ diff --git a/board/MAI/bios_emulator/scitech/src/common/libcimp.c b/board/MAI/bios_emulator/scitech/src/common/libcimp.c new file mode 100644 index 000000000..ab73ad578 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/libcimp.c @@ -0,0 +1,827 @@ +/**************************************************************************** +* +* SciTech MGL Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module to implement a the OS specific side of the Binary +* Portable DLL C runtime library. The functions in here +* are imported into the Binary Portable DLL's to implement +* OS specific services. +* +****************************************************************************/ + +#include "pmapi.h" +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) +#include "drvlib/peloader.h" +#include "drvlib/attrib.h" +#include "drvlib/libc/init.h" +#define __BUILDING_PE_LOADER__ +#include "drvlib/libc/file.h" +#if defined(__WIN32_VXD__) +#include "vxdfile.h" +#endif +#else +#include +#include +#include +#include +#include +#include +#include +#if defined(__GNUC__) || defined(__UNIX__) +#include +#include +#include +#else +#include +#endif +#include "drvlib/attrib.h" +#include "drvlib/libc/init.h" +#define __BUILDING_PE_LOADER__ +#include "drvlib/libc/file.h" +#if defined(__WINDOWS__) || defined(TNT) || defined(__RTTARGET__) +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#endif +#ifdef __MSDOS__ +#include +#endif +#ifdef __OS2__ +#define INCL_DOS +#define INCL_DOSERRORS +#define INCL_SUB +#include +#endif +#endif + +/* No text or binary modes for Unix */ + +#ifndef O_BINARY +#define O_BINARY 0 +#define O_TEXT 0 +#endif + +/*--------------------------- Global variables ----------------------------*/ + +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) +#define MAX_FILES 16 +static FILE *openHandles[MAX_FILES] = {NULL}; +#endif + +/* stub functions */ +void _CDECL stub_abort(void); +int _CDECL stub_atexit(void (*)(void)); +void * _CDECL stub_calloc(size_t _nelem, size_t _size); +void _CDECL stub_exit(int _status); +void _CDECL stub_free(void *_ptr); +char * _CDECL stub_getenv(const char *_name); +void * _CDECL stub_malloc(size_t _size); +void * _CDECL stub_realloc(void *_ptr, size_t _size); +int _CDECL stub_system(const char *_s); +int _CDECL stub_putenv(const char *_val); + +/* stub functions */ +int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode); +int _CDECL stub_access(const char *_path, int _amode); +int _CDECL stub_close(int _fildes); +off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence); +size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte); +int _CDECL stub_unlink(const char *_path); +size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte); +int _CDECL stub_isatty(int _fildes); + +/* stub functions */ +int _CDECL stub_remove(const char *_filename); +int _CDECL stub_rename(const char *_old, const char *_new); + +/* stub functions */ +time_t _CDECL stub_time(time_t *_tod); + +/* stub functions */ +int _CDECL stub_raise(int); +void * _CDECL stub_signal(int, void *); + +/* functions */ +#define stub_OS_setfileattr _OS_setfileattr +#define stub_OS_getcurrentdate _OS_getcurrentdate + +LIBC_imports _VARAPI ___imports = { + sizeof(LIBC_imports), + + /* exports */ + stub_abort, + stub_atexit, + stub_calloc, + stub_exit, + stub_free, + stub_getenv, + stub_malloc, + stub_realloc, + stub_system, + stub_putenv, + + /* exports */ + stub_open, + stub_access, + stub_close, + stub_lseek, + stub_read, + stub_unlink, + stub_write, + stub_isatty, + + /* exports */ + stub_remove, + stub_rename, + + /* functions */ + stub_raise, + stub_signal, + + /* exports */ + stub_time, + + /* exports */ + stub_OS_setfileattr, + stub_OS_getcurrentdate, + }; + +/*---------------------- Stub function implementation ---------------------*/ + +/* stub functions */ +void _CDECL stub_abort(void) +{ +#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__) + abort(); +#endif +} + +int _CDECL stub_atexit(void (*func)(void)) +{ +#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__) + return atexit((void(*)(void))func); +#else + return -1; +#endif +} + +void * _CDECL stub_calloc(size_t _nelem, size_t _size) +{ return __PM_calloc(_nelem,_size); } + +void _CDECL stub_exit(int _status) +{ +#if !defined( __WIN32_VXD__) && !defined(__NT_DRIVER__) + exit(_status); +#endif +} + +void _CDECL stub_free(void *_ptr) +{ __PM_free(_ptr); } + +char * _CDECL stub_getenv(const char *_name) +{ +#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__) + return NULL; +#else + return getenv(_name); +#endif +} + +void * _CDECL stub_malloc(size_t _size) +{ return __PM_malloc(_size); } + +void * _CDECL stub_realloc(void *_ptr, size_t _size) +{ return __PM_realloc(_ptr,_size); } + +int _CDECL stub_system(const char *_s) +{ +#if defined(__WINDOWS__) || defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__) || defined(__RTTARGET__) + (void)_s; + return -1; +#else + return system(_s); +#endif +} + +int _CDECL stub_putenv(const char *_val) +{ +#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__) + return -1; +#else + return putenv((char*)_val); +#endif +} + +time_t _CDECL stub_time(time_t *_tod) +{ +#if defined( __WIN32_VXD__) || defined(__NT_DRIVER__) + return 0; +#else + return time(_tod); +#endif +} + +#if defined(__MSDOS__) + +#if defined(TNT) && defined(_MSC_VER) + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ SetFileAttributes((LPSTR)filename, (DWORD)attrib); } + +#else + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ _dos_setfileattr(filename,attrib); } + +#endif + +#elif defined(__WIN32_VXD__) + +#define USE_LOCAL_FILEIO +#define USE_LOCAL_GETDATE + +/* stub functions */ +int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) +{ + char mode[10]; + int i; + + /* Find an empty file handle to use */ + for (i = 3; i < MAX_FILES; i++) { + if (!openHandles[i]) + break; + } + if (openHandles[i]) + return -1; + + /* Find the open flags to use */ + if (_oflag & ___O_TRUNC) + strcpy(mode,"w"); + else if (_oflag & ___O_CREAT) + strcpy(mode,"a"); + else + strcpy(mode,"r"); + if (_oflag & ___O_BINARY) + strcat(mode,"b"); + if (_oflag & ___O_TEXT) + strcat(mode,"t"); + + /* Open the file and store the file handle */ + if ((openHandles[i] = fopen(_path,mode)) == NULL) + return -1; + return i; +} + +int _CDECL stub_access(const char *_path, int _amode) +{ return -1; } + +int _CDECL stub_close(int _fildes) +{ + if (_fildes >= 3 && openHandles[_fildes]) { + fclose(openHandles[_fildes]); + openHandles[_fildes] = NULL; + } + return 0; +} + +off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) +{ + if (_fildes >= 3) { + fseek(openHandles[_fildes],_offset,_whence); + return ftell(openHandles[_fildes]); + } + return 0; +} + +size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) +{ + if (_fildes >= 3) + return fread(_buf,1,_nbyte,openHandles[_fildes]); + return 0; +} + +int _CDECL stub_unlink(const char *_path) +{ + WORD error; + + if (initComplete) { + if (R0_DeleteFile((char*)_path,0,&error)) + return 0; + return -1; + } + else + return i_remove(_path); +} + +size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) +{ + if (_fildes >= 3) + return fwrite(_buf,1,_nbyte,openHandles[_fildes]); + return _nbyte; +} + +int _CDECL stub_isatty(int _fildes) +{ return 0; } + +/* stub functions */ +int _CDECL stub_remove(const char *_filename) +{ return stub_unlink(_filename); } + +int _CDECL stub_rename(const char *_old, const char *_new) +{ return -1; } + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ + WORD error; + if (initComplete) + R0_SetFileAttributes((char*)filename,attrib,&error); +} + +/* Return the current date in days since 1/1/1980 */ +ulong _CDECL _OS_getcurrentdate(void) +{ + DWORD date; + VTD_Get_Date_And_Time(&date); + return date; +} + +#elif defined(__NT_DRIVER__) + +#define USE_LOCAL_FILEIO +#define USE_LOCAL_GETDATE + +/* stub functions */ +int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) +{ + char mode[10]; + int i; + + /* Find an empty file handle to use */ + for (i = 3; i < MAX_FILES; i++) { + if (!openHandles[i]) + break; + } + if (openHandles[i]) + return -1; + + /* Find the open flags to use */ + if (_oflag & ___O_TRUNC) + strcpy(mode,"w"); + else if (_oflag & ___O_CREAT) + strcpy(mode,"a"); + else + strcpy(mode,"r"); + if (_oflag & ___O_BINARY) + strcat(mode,"b"); + if (_oflag & ___O_TEXT) + strcat(mode,"t"); + + /* Open the file and store the file handle */ + if ((openHandles[i] = fopen(_path,mode)) == NULL) + return -1; + return i; +} + +int _CDECL stub_close(int _fildes) +{ + if (_fildes >= 3 && openHandles[_fildes]) { + fclose(openHandles[_fildes]); + openHandles[_fildes] = NULL; + } + return 0; +} + +off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) +{ + if (_fildes >= 3) { + fseek(openHandles[_fildes],_offset,_whence); + return ftell(openHandles[_fildes]); + } + return 0; +} + +size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) +{ + if (_fildes >= 3) + return fread(_buf,1,_nbyte,openHandles[_fildes]); + return 0; +} + +size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) +{ + if (_fildes >= 3) + return fwrite(_buf,1,_nbyte,openHandles[_fildes]); + return _nbyte; +} + +int _CDECL stub_access(const char *_path, int _amode) +{ return -1; } + +int _CDECL stub_isatty(int _fildes) +{ return 0; } + +int _CDECL stub_unlink(const char *_path) +{ + /* TODO: Implement this! */ + return -1; +} + +/* stub functions */ +int _CDECL stub_remove(const char *_filename) +{ return stub_unlink(_filename); } + +int _CDECL stub_rename(const char *_old, const char *_new) +{ + /* TODO: Implement this! */ + return -1; +} + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ + uint _attr = 0; + if (attrib & __A_RDONLY) + _attr |= FILE_ATTRIBUTE_READONLY; + if (attrib & __A_HIDDEN) + _attr |= FILE_ATTRIBUTE_HIDDEN; + if (attrib & __A_SYSTEM) + _attr |= FILE_ATTRIBUTE_SYSTEM; + PM_setFileAttr(filename,_attr); +} + +/* Return the current date in days since 1/1/1980 */ +ulong _CDECL _OS_getcurrentdate(void) +{ + TIME_FIELDS tm; + _int64 count,count_1_1_1980; + + tm.Year = 1980; + tm.Month = 1; + tm.Day = 1; + tm.Hour = 0; + tm.Minute = 0; + tm.Second = 0; + tm.Milliseconds = 0; + tm.Weekday = 0; + RtlTimeFieldsToTime(&tm,(PLARGE_INTEGER)&count_1_1_1980); + KeQuerySystemTime((PLARGE_INTEGER)&count); + return (ulong)( (count - count_1_1_1980) / ((_int64)24 * (_int64)3600 * (_int64)10000000) ); +} + +#elif defined(__WINDOWS32__) || defined(__RTTARGET__) + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ SetFileAttributes((LPSTR)filename, (DWORD)attrib); } + +#elif defined(__OS2__) + +#define USE_LOCAL_FILEIO + +#ifndef W_OK +#define W_OK 0x02 +#endif + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ + FILESTATUS3 s; + if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s))) + return; + s.attrFile = attrib; + DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s),0L); +} + +/* stub functions */ + +#define BUF_SIZE 4096 + +/* Note: the implementation of the standard Unix-ish handle-based I/O isn't + * complete - but that wasn't the intent either. Note also that we + * don't presently support text file I/O, so all text files end + * up in Unix format (and are not translated!). + */ +int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) +{ + HFILE handle; + ULONG error, actiontaken, openflag, openmode; + char path[PM_MAX_PATH]; + + /* Determine open flags */ + if (_oflag & ___O_CREAT) { + if (_oflag & ___O_EXCL) + openflag = OPEN_ACTION_FAIL_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; + else if (_oflag & ___O_TRUNC) + openflag = OPEN_ACTION_REPLACE_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; + else + openflag = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; + } + else if (_oflag & ___O_TRUNC) + openflag = OPEN_ACTION_REPLACE_IF_EXISTS; + else + openflag = OPEN_ACTION_OPEN_IF_EXISTS; + + /* Determine open mode flags */ + if (_oflag & ___O_RDONLY) + openmode = OPEN_ACCESS_READONLY | OPEN_SHARE_DENYNONE; + else if (_oflag & ___O_WRONLY) + openmode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_DENYWRITE; + else + openmode = OPEN_ACCESS_READWRITE | OPEN_SHARE_DENYWRITE; + + /* Copy the path to a variable on the stack. We need to do this + * for OS/2 as when the drivers are loaded into shared kernel + * memory, we can't pass an address from that memory range to + * this function. + */ + strcpy(path,_path); + if (DosOpen(path, &handle, &actiontaken, 0, FILE_NORMAL, + openflag, openmode, NULL) != NO_ERROR) + return -1; + + /* Handle append mode of operation */ + if (_oflag & ___O_APPEND) { + if (DosSetFilePtr(handle, 0, FILE_END, &error) != NO_ERROR) + return -1; + } + return handle; +} + +int _CDECL stub_access(const char *_path, int _amode) +{ + char path[PM_MAX_PATH]; + FILESTATUS fs; + + /* Copy the path to a variable on the stack. We need to do this + * for OS/2 as when the drivers are loaded into shared kernel + * memory, we can't pass an address from that memory range to + * this function. + */ + strcpy(path,_path); + if (DosQueryPathInfo(path, FIL_STANDARD, &fs, sizeof(fs)) != NO_ERROR) + return -1; + if ((_amode & W_OK) && (fs.attrFile & FILE_READONLY)) + return -1; + return 0; +} + +int _CDECL stub_close(int _fildes) +{ + if (DosClose(_fildes) != NO_ERROR) + return -1; + return 0; +} + +off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) +{ + ULONG cbActual, origin; + + switch (_whence) { + case SEEK_CUR: + origin = FILE_CURRENT; + break; + case SEEK_END: + origin = FILE_END; + break; + default: + origin = FILE_BEGIN; + } + if (DosSetFilePtr(_fildes, _offset, origin, &cbActual) != NO_ERROR) + return -1; + return cbActual; +} + +size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) +{ + ULONG cbActual = 0,cbRead; + uchar *p = _buf; + uchar file_io_buf[BUF_SIZE]; + + /* We need to perform the physical read in chunks into a + * a temporary static buffer, since the buffer passed in may be + * in kernel space and will cause DosRead to bail internally. + */ + while (_nbyte > BUF_SIZE) { + if (DosRead(_fildes, file_io_buf, BUF_SIZE, &cbRead) != NO_ERROR) + return -1; + cbActual += cbRead; + memcpy(p,file_io_buf,BUF_SIZE); + p += BUF_SIZE; + _nbyte -= BUF_SIZE; + } + if (_nbyte) { + if (DosRead(_fildes, file_io_buf, _nbyte, &cbRead) != NO_ERROR) + return -1; + cbActual += cbRead; + memcpy(p,file_io_buf,_nbyte); + } + return cbActual; +} + +size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) +{ + ULONG cbActual = 0,cbWrite; + uchar *p = (PVOID)_buf; + uchar file_io_buf[BUF_SIZE]; + + /* We need to perform the physical write in chunks from a + * a temporary static buffer, since the buffer passed in may be + * in kernel space and will cause DosWrite to bail internally. + */ + while (_nbyte > BUF_SIZE) { + memcpy(file_io_buf,p,BUF_SIZE); + if (DosWrite(_fildes, file_io_buf, BUF_SIZE, &cbWrite) != NO_ERROR) + return -1; + cbActual += cbWrite; + p += BUF_SIZE; + _nbyte -= BUF_SIZE; + } + if (_nbyte) { + memcpy(file_io_buf,p,_nbyte); + if (DosWrite(_fildes, file_io_buf, _nbyte, &cbWrite) != NO_ERROR) + return -1; + cbActual += cbWrite; + } + return cbActual; +} + +int _CDECL stub_unlink(const char *_path) +{ + char path[PM_MAX_PATH]; + + /* Copy the path to a variable on the stack. We need to do this + * for OS/2 as when the drivers are loaded into shared kernel + * memory, we can't pass an address from that memory range to + * this function. + */ + strcpy(path,_path); + if (DosDelete(path) != NO_ERROR) + return -1; + return 0; +} + +int _CDECL stub_isatty(int _fildes) +{ + ULONG htype, flags; + + if (DosQueryHType(_fildes, &htype, &flags) != NO_ERROR) + return 0; + return ((htype & 0xFF) == HANDTYPE_DEVICE); +} + +/* stub functions */ +int _CDECL stub_remove(const char *_path) +{ + char path[PM_MAX_PATH]; + + /* Copy the path to a variable on the stack. We need to do this + * for OS/2 as when the drivers are loaded into shared kernel + * memory, we can't pass an address from that memory range to + * this function. + */ + strcpy(path,_path); + if (DosDelete(path) != NO_ERROR) + return -1; + return 0; +} + +int _CDECL stub_rename(const char *_old, const char *_new) +{ + char old[PM_MAX_PATH]; + char new[PM_MAX_PATH]; + + /* Copy the path to a variable on the stack. We need to do this + * for OS/2 as when the drivers are loaded into shared kernel + * memory, we can't pass an address from that memory range to + * this function. + */ + strcpy(old,_old); + strcpy(new,_new); + if (DosMove(old, new) != NO_ERROR) + return -1; + return 0; +} + +#else + +void _CDECL _OS_setfileattr(const char *filename,unsigned attrib) +{ /* Unable to set hidden, system attributes on Unix. */ } + +#endif + +#ifndef USE_LOCAL_FILEIO + +/* stub functions */ +int _CDECL stub_open(const char *_path, int _oflag, unsigned _mode) +{ + int oflag_tab[] = { + ___O_RDONLY, O_RDONLY, + ___O_WRONLY, O_WRONLY, + ___O_RDWR, O_RDWR, + ___O_BINARY, O_BINARY, + ___O_TEXT, O_TEXT, + ___O_CREAT, O_CREAT, + ___O_EXCL, O_EXCL, + ___O_TRUNC, O_TRUNC, + ___O_APPEND, O_APPEND, + }; + int i,oflag = 0; + + /* Translate the oflag's to the OS dependent versions */ + for (i = 0; i < sizeof(oflag_tab) / sizeof(int); i += 2) { + if (_oflag & oflag_tab[i]) + oflag |= oflag_tab[i+1]; + } + return open(_path,oflag,_mode); +} + +int _CDECL stub_access(const char *_path, int _amode) +{ return access(_path,_amode); } + +int _CDECL stub_close(int _fildes) +{ return close(_fildes); } + +off_t _CDECL stub_lseek(int _fildes, off_t _offset, int _whence) +{ return lseek(_fildes,_offset,_whence); } + +size_t _CDECL stub_read(int _fildes, void *_buf, size_t _nbyte) +{ return read(_fildes,_buf,_nbyte); } + +int _CDECL stub_unlink(const char *_path) +{ return unlink(_path); } + +size_t _CDECL stub_write(int _fildes, const void *_buf, size_t _nbyte) +{ return write(_fildes,_buf,_nbyte); } + +int _CDECL stub_isatty(int _fildes) +{ return isatty(_fildes); } + +/* stub functions */ +int _CDECL stub_remove(const char *_filename) +{ return remove(_filename); } + +int _CDECL stub_rename(const char *_old, const char *_new) +{ return rename(_old,_new); } + +#endif + +#ifndef USE_LOCAL_GETDATE + +/* Return the current date in days since 1/1/1980 */ +ulong _CDECL _OS_getcurrentdate(void) +{ + struct tm refTime; + refTime.tm_year = 80; + refTime.tm_mon = 0; + refTime.tm_mday = 1; + refTime.tm_hour = 0; + refTime.tm_min = 0; + refTime.tm_sec = 0; + refTime.tm_isdst = -1; + return (time(NULL) - mktime(&refTime)) / (24 * 3600L); +} + +#endif + +int _CDECL stub_raise(int sig) +{ +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__) + return -1; +#else + return raise(sig); +#endif +} + +#ifdef __WINDOWS32__ +typedef void (*__code_ptr)(int); +#else +typedef void (*__code_ptr)(); +#endif + +void * _CDECL stub_signal(int sig, void *handler) +{ +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) || defined(__SMX32__) + return NULL; +#else + return (void*)signal(sig,(__code_ptr)handler); +#endif +} diff --git a/board/MAI/bios_emulator/scitech/src/common/makefile b/board/MAI/bios_emulator/scitech/src/common/makefile new file mode 100644 index 000000000..5aac0381b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/makefile @@ -0,0 +1,18 @@ +############################################################################# +# +# Copyright (C) 1996 SciTech Software. +# All rights reserved. +# +# Descripton: Makefile for UniVBE(tm), UniPOWER(tm), UVBELib(tm) and +# DPMSLib library files. Requires Borland C++ 4.52 to build +# some components. +# +# $Date: 2002/10/02 15:35:20 $ $Author: hfrieden $ +# +############################################################################# + +CFLAGS += -DTESTING_GTF + +gtfcalc$E: gtfcalc$O + +.INCLUDE: "$(SCITECH)/makedefs/common.mk" diff --git a/board/MAI/bios_emulator/scitech/src/common/peloader.c b/board/MAI/bios_emulator/scitech/src/common/peloader.c new file mode 100644 index 000000000..a134bb012 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/peloader.c @@ -0,0 +1,586 @@ +/**************************************************************************** +* +* SciTech MGL Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module to implement a simple Portable Binary DLL loader +* library. This library can be used to load PE DLL's under +* any Intel based OS, provided the DLL's do not have any +* imports in the import table. +* +* NOTE: This loader module expects the DLL's to be built with +* Watcom C++ and may produce unexpected results with +* DLL's linked by another compiler. +* +****************************************************************************/ + +#include "drvlib/peloader.h" +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "drvlib/libc/init.h" +#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#endif +#include "drvlib/pe.h" + +/*--------------------------- Global variables ----------------------------*/ + +static int result = PE_ok; + +/*------------------------- Implementation --------------------------------*/ + +/**************************************************************************** +PARAMETERS: +f - Handle to open file to read driver from +startOffset - Offset to the start of the driver within the file + +RETURNS: +Handle to loaded PE DLL, or NULL on failure. + +REMARKS: +This function loads a Portable Binary DLL library from disk, relocates +the code and returns a handle to the loaded library. This function is the +same as the regular PE_loadLibrary except that it take a handle to an +open file and an offset within that file for the DLL to load. +****************************************************************************/ +static int PE_readHeader( + FILE *f, + long startOffset, + FILE_HDR *filehdr, + OPTIONAL_HDR *opthdr) +{ + EXE_HDR exehdr; + ulong offset,signature; + + /* Read the EXE header and check for valid header signature */ + result = PE_invalidDLLImage; + fseek(f, startOffset, SEEK_SET); + if (fread(&exehdr, 1, sizeof(exehdr), f) != sizeof(exehdr)) + return false; + if (exehdr.signature != 0x5A4D) + return false; + + /* Now seek to the start of the PE header defined at offset 0x3C + * in the MS-DOS EXE header, and read the signature and check it. + */ + fseek(f, startOffset+0x3C, SEEK_SET); + if (fread(&offset, 1, sizeof(offset), f) != sizeof(offset)) + return false; + fseek(f, startOffset+offset, SEEK_SET); + if (fread(&signature, 1, sizeof(signature), f) != sizeof(signature)) + return false; + if (signature != 0x00004550) + return false; + + /* Now read the PE file header and check that it is correct */ + if (fread(filehdr, 1, sizeof(*filehdr), f) != sizeof(*filehdr)) + return false; + if (filehdr->Machine != IMAGE_FILE_MACHINE_I386) + return false; + if (!(filehdr->Characteristics & IMAGE_FILE_32BIT_MACHINE)) + return false; + if (!(filehdr->Characteristics & IMAGE_FILE_DLL)) + return false; + if (fread(opthdr, 1, sizeof(*opthdr), f) != sizeof(*opthdr)) + return false; + if (opthdr->Magic != 0x10B) + return false; + + /* Success, so return true! */ + return true; +} + +/**************************************************************************** +PARAMETERS: +f - Handle to open file to read driver from +startOffset - Offset to the start of the driver within the file + +RETURNS: +Size of the DLL file on disk, or -1 on error + +REMARKS: +This function scans the headers for a Portable Binary DLL to determine the +length of the DLL file on disk. +{secret} +****************************************************************************/ +ulong PEAPI PE_getFileSize( + FILE *f, + ulong startOffset) +{ + FILE_HDR filehdr; + OPTIONAL_HDR opthdr; + SECTION_HDR secthdr; + ulong size; + int i; + + /* Read the PE file headers from disk */ + if (!PE_readHeader(f,startOffset,&filehdr,&opthdr)) + return 0xFFFFFFFF; + + /* Scan all the section headers summing up the total size */ + size = opthdr.SizeOfHeaders; + for (i = 0; i < filehdr.NumberOfSections; i++) { + if (fread(§hdr, 1, sizeof(secthdr), f) != sizeof(secthdr)) + return 0xFFFFFFFF; + size += secthdr.SizeOfRawData; + } + return size; +} + +/**************************************************************************** +DESCRIPTION: +Loads a Portable Binary DLL into memory from an open file + +HEADER: +peloader.h + +PARAMETERS: +f - Handle to open file to read driver from +startOffset - Offset to the start of the driver within the file +size - Place to store the size of the driver loaded +shared - True to load module into shared memory + +RETURNS: +Handle to loaded PE DLL, or NULL on failure. + +REMARKS: +This function loads a Portable Binary DLL library from disk, relocates +the code and returns a handle to the loaded library. This function is the +same as the regular PE_loadLibrary except that it take a handle to an +open file and an offset within that file for the DLL to load. + +SEE ALSO: +PE_loadLibrary, PE_getProcAddress, PE_freeLibrary +****************************************************************************/ +PE_MODULE * PEAPI PE_loadLibraryExt( + FILE *f, + ulong startOffset, + ulong *size, + ibool shared) +{ + FILE_HDR filehdr; + OPTIONAL_HDR opthdr; + SECTION_HDR secthdr; + ulong offset,pageOffset; + ulong text_off,text_addr,text_size; + ulong data_off,data_addr,data_size,data_end; + ulong export_off,export_addr,export_size,export_end; + ulong reloc_off,reloc_size; + ulong image_size; + int i,delta,numFixups; + ushort relocType,*fixup; + PE_MODULE *hMod = NULL; + void *reloc = NULL; + BASE_RELOCATION *baseReloc; + InitLibC_t InitLibC; + + /* Read the PE file headers from disk */ + if (!PE_readHeader(f,startOffset,&filehdr,&opthdr)) + return NULL; + + /* Scan all the section headers and find the necessary sections */ + text_off = data_off = reloc_off = export_off = 0; + text_addr = text_size = 0; + data_addr = data_size = data_end = 0; + export_addr = export_size = export_end = 0; + reloc_size = 0; + for (i = 0; i < filehdr.NumberOfSections; i++) { + if (fread(§hdr, 1, sizeof(secthdr), f) != sizeof(secthdr)) + goto Error; + if (strcmp(secthdr.Name, ".edata") == 0 || strcmp(secthdr.Name, ".rdata") == 0) { + /* Exports section */ + export_off = secthdr.PointerToRawData; + export_addr = secthdr.VirtualAddress; + export_size = secthdr.SizeOfRawData; + export_end = export_addr + export_size; + } + else if (strcmp(secthdr.Name, ".idata") == 0) { + /* Imports section, ignore */ + } + else if (strcmp(secthdr.Name, ".reloc") == 0) { + /* Relocations section */ + reloc_off = secthdr.PointerToRawData; + reloc_size = secthdr.SizeOfRawData; + } + else if (!text_off && secthdr.Characteristics & IMAGE_SCN_CNT_CODE) { + /* Code section */ + text_off = secthdr.PointerToRawData; + text_addr = secthdr.VirtualAddress; + text_size = secthdr.SizeOfRawData; + } + else if (!data_off && secthdr.Characteristics & IMAGE_SCN_CNT_INITIALIZED_DATA) { + /* Data section */ + data_off = secthdr.PointerToRawData; + data_addr = secthdr.VirtualAddress; + data_size = secthdr.SizeOfRawData; + data_end = data_addr + data_size; + } + } + + /* Check to make sure that we have all the sections we need */ + if (!text_off || !data_off || !export_off || !reloc_off) { + result = PE_invalidDLLImage; + goto Error; + } + + /* Find the size of the image to load allocate memory for it */ + image_size = MAX(export_end,data_end) - text_addr; + *size = sizeof(PE_MODULE) + image_size + 4096; + if (shared) + hMod = PM_mallocShared(*size); + else + hMod = PM_malloc(*size); + reloc = PM_malloc(reloc_size); + if (!hMod || !reloc) { + result = PE_outOfMemory; + goto Error; + } + + hMod->text = (uchar*)ROUND_4K((ulong)hMod + sizeof(PE_MODULE)); + hMod->data = (uchar*)((ulong)hMod->text + (data_addr - text_addr)); + hMod->export = (uchar*)((ulong)hMod->text + (export_addr - text_addr)); + hMod->textBase = text_addr; + hMod->dataBase = data_addr; + hMod->exportBase = export_addr; + hMod->exportDir = opthdr.DataDirectory[0].RelVirtualAddress - export_addr; + hMod->shared = shared; + + /* Now read the section images from disk */ + result = PE_invalidDLLImage; + fseek(f, startOffset+text_off, SEEK_SET); + if (fread(hMod->text, 1, text_size, f) != text_size) + goto Error; + fseek(f, startOffset+data_off, SEEK_SET); + if (fread(hMod->data, 1, data_size, f) != data_size) + goto Error; + fseek(f, startOffset+export_off, SEEK_SET); + if (fread(hMod->export, 1, export_size, f) != export_size) + goto Error; + fseek(f, startOffset+reloc_off, SEEK_SET); + if (fread(reloc, 1, reloc_size, f) != reloc_size) + goto Error; + + /* Now perform relocations on all sections in the image */ + delta = (ulong)hMod->text - opthdr.ImageBase - text_addr; + baseReloc = (BASE_RELOCATION*)reloc; + for (;;) { + /* Check for termination condition */ + if (!baseReloc->PageRVA || !baseReloc->BlockSize) + break; + + /* Do fixups */ + pageOffset = baseReloc->PageRVA - hMod->textBase; + numFixups = (baseReloc->BlockSize - sizeof(BASE_RELOCATION)) / sizeof(ushort); + fixup = (ushort*)(baseReloc + 1); + for (i = 0; i < numFixups; i++) { + relocType = *fixup >> 12; + if (relocType) { + offset = pageOffset + (*fixup & 0x0FFF); + *(ulong*)(hMod->text + offset) += delta; + } + fixup++; + } + + /* Move to next relocation block */ + baseReloc = (BASE_RELOCATION*)((ulong)baseReloc + baseReloc->BlockSize); + } + + /* Initialise the C runtime library for the loaded DLL */ + result = PE_unableToInitLibC; + if ((InitLibC = (InitLibC_t)PE_getProcAddress(hMod,"_InitLibC")) == NULL) + goto Error; + if (!InitLibC(&___imports,PM_getOSType())) + goto Error; + + /* Clean up, close the file and return the loaded module handle */ + PM_free(reloc); + result = PE_ok; + return hMod; + +Error: + if (shared) + PM_freeShared(hMod); + else + PM_free(hMod); + PM_free(reloc); + return NULL; +} + +/**************************************************************************** +DESCRIPTION: +Loads a Portable Binary DLL into memory + +HEADER: +peloader.h + +PARAMETERS: +szDLLName - Name of the PE DLL library to load +shared - True to load module into shared memory + +RETURNS: +Handle to loaded PE DLL, or NULL on failure. + +REMARKS: +This function loads a Portable Binary DLL library from disk, relocates +the code and returns a handle to the loaded library. This function +will only work on DLL's that do not have any imports, since we don't +resolve import dependencies in this function. + +SEE ALSO: +PE_getProcAddress, PE_freeLibrary +****************************************************************************/ +PE_MODULE * PEAPI PE_loadLibrary( + const char *szDLLName, + ibool shared) +{ + PE_MODULE *hMod; + +#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) + if (!shared) { + PM_MODULE hInst; + InitLibC_t InitLibC; + + /* For Win32 if are building checked libraries for debugging, we use + * the real Win32 DLL functions so that we can debug the resulting DLL + * files with the Win32 debuggers. Note that we can't do this if + * we need to load the files into a shared memory context. + */ + if ((hInst = PM_loadLibrary(szDLLName)) == NULL) { + result = PE_fileNotFound; + return NULL; + } + + /* Initialise the C runtime library for the loaded DLL */ + result = PE_unableToInitLibC; + if ((InitLibC = (void*)PM_getProcAddress(hInst,"_InitLibC")) == NULL) + return NULL; + if (!InitLibC(&___imports,PM_getOSType())) + return NULL; + + /* Allocate the PE_MODULE structure */ + if ((hMod = PM_malloc(sizeof(*hMod))) == NULL) + return NULL; + hMod->text = (void*)hInst; + hMod->shared = -1; + + /* DLL loaded successfully so return module handle */ + result = PE_ok; + return hMod; + } + else +#endif + { + FILE *f; + ulong size; + + /* Attempt to open the file on disk */ + if (shared < 0) + shared = 0; + if ((f = fopen(szDLLName,"rb")) == NULL) { + result = PE_fileNotFound; + return NULL; + } + hMod = PE_loadLibraryExt(f,0,&size,shared); + fclose(f); + return hMod; + } +} + +/**************************************************************************** +DESCRIPTION: +Loads a Portable Binary DLL into memory + +HEADER: +peloader.h + +PARAMETERS: +szDLLName - Name of the PE DLL library to load +shared - True to load module into shared memory + +RETURNS: +Handle to loaded PE DLL, or NULL on failure. + +REMARKS: +This function is the same as the regular PE_loadLibrary function, except +that it looks for the drivers in the MGL_ROOT/drivers directory or a +/drivers directory relative to the current directory. + +SEE ALSO: +PE_loadLibraryMGL, PE_getProcAddress, PE_freeLibrary +****************************************************************************/ +PE_MODULE * PEAPI PE_loadLibraryMGL( + const char *szDLLName, + ibool shared) +{ +#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) + PE_MODULE *hMod; +#endif + char path[256] = ""; + + /* We look in the 'drivers' directory, optionally under the MGL_ROOT + * environment variable directory. + */ +#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) + if (getenv("MGL_ROOT")) { + strcpy(path,getenv("MGL_ROOT")); + PM_backslash(path); + } + strcat(path,"drivers"); + PM_backslash(path); + strcat(path,szDLLName); + if ((hMod = PE_loadLibrary(path,shared)) != NULL) + return hMod; +#endif + strcpy(path,"drivers"); + PM_backslash(path); + strcat(path,szDLLName); + return PE_loadLibrary(path,shared); +} + +/**************************************************************************** +DESCRIPTION: +Gets a function address from a Portable Binary DLL + +HEADER: +peloader.h + +PARAMETERS: +hModule - Handle to a loaded PE DLL library +szProcName - Name of the function to get the address of + +RETURNS: +Pointer to the function, or NULL on failure. + +REMARKS: +This function searches for the named, exported function in a loaded PE +DLL library, and returns the address of the function. If the function is +not found in the library, this function return NULL. + +SEE ALSO: +PE_loadLibrary, PE_freeLibrary +****************************************************************************/ +void * PEAPI PE_getProcAddress( + PE_MODULE *hModule, + const char *szProcName) +{ +#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) + if (hModule->shared == -1) + return (void*)PM_getProcAddress(hModule->text,szProcName); + else +#endif + { + uint i; + EXPORT_DIRECTORY *exports; + ulong funcOffset; + ulong *AddressTable; + ulong *NameTable; + ushort *OrdinalTable; + char *name; + + /* Find the address of the export tables from the export section */ + if (!hModule) + return NULL; + exports = (EXPORT_DIRECTORY*)(hModule->export + hModule->exportDir); + AddressTable = (ulong*)(hModule->export + exports->AddressTableRVA - hModule->exportBase); + NameTable = (ulong*)(hModule->export + exports->NameTableRVA - hModule->exportBase); + OrdinalTable = (ushort*)(hModule->export + exports->OrdinalTableRVA - hModule->exportBase); + + /* Search the export name table to find the function name */ + for (i = 0; i < exports->NumberOfNamePointers; i++) { + name = (char*)(hModule->export + NameTable[i] - hModule->exportBase); + if (strcmp(name,szProcName) == 0) + break; + } + if (i == exports->NumberOfNamePointers) + return NULL; + funcOffset = AddressTable[OrdinalTable[i]]; + if (!funcOffset) + return NULL; + return (void*)(hModule->text + funcOffset - hModule->textBase); + } +} + +/**************************************************************************** +DESCRIPTION: +Frees a loaded Portable Binary DLL + +HEADER: +peloader.h + +PARAMETERS: +hModule - Handle to a loaded PE DLL library to free + +REMARKS: +This function frees a loaded PE DLL library from memory. + +SEE ALSO: +PE_getProcAddress, PE_loadLibrary +****************************************************************************/ +void PEAPI PE_freeLibrary( + PE_MODULE *hModule) +{ + TerminateLibC_t TerminateLibC; + +#if (defined(__WINDOWS32__) || defined(__DRIVER__)) && defined(CHECKED) + if (hModule->shared == -1) { + /* Run the C runtime library exit code on module unload */ + if ((TerminateLibC = (TerminateLibC_t)PM_getProcAddress(hModule->text,"_TerminateLibC")) != NULL) + TerminateLibC(); + PM_freeLibrary(hModule->text); + PM_free(hModule); + } + else +#endif + { + if (hModule) { + /* Run the C runtime library exit code on module unload */ + if ((TerminateLibC = (TerminateLibC_t)PE_getProcAddress(hModule,"_TerminateLibC")) != NULL) + TerminateLibC(); + if (hModule->shared) + PM_freeShared(hModule); + else + PM_free(hModule); + } + } +} + +/**************************************************************************** +DESCRIPTION: +Returns the error code for the last operation + +HEADER: +peloader.h + +RETURNS: +Error code for the last operation. + +SEE ALSO: +PE_getProcAddress, PE_loadLibrary +****************************************************************************/ +int PEAPI PE_getError(void) +{ + return result; +} diff --git a/board/MAI/bios_emulator/scitech/src/common/vesavbe.c b/board/MAI/bios_emulator/scitech/src/common/vesavbe.c new file mode 100644 index 000000000..a669e5c29 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/common/vesavbe.c @@ -0,0 +1,1214 @@ +/**************************************************************************** +* +* The SuperVGA Kit - UniVBE Software Development Kit +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: IBM PC Real Mode and 16/32 bit Protected Mode. +* +* Description: Module to implement a C callable interface to the standard +* VESA VBE routines. You should rip out this module and use it +* directly in your own applications, or you can use the +* high level SDK functions. +* +* MUST be compiled in the LARGE or FLAT models. +* +****************************************************************************/ + +#include +#include +#include +#include "vesavbe.h" +#include "pmapi.h" +#include "drvlib/os/os.h" + +/*---------------------------- Global Variables ---------------------------*/ + +#define VBE_SUCCESS 0x004F +#define MAX_LIN_PTRS 10 + +static uint VESABuf_len = 1024;/* Length of the VESABuf buffer */ +static ibool haveRiva128; /* True if we have a Riva128 */ +static VBE_state defState = {0}; /* Default state buffer */ +static VBE_state *state = &defState; /* Pointer to current buffer */ +static int VBE_shared = 0; +#ifndef REALMODE +static char localBuf[512]; /* Global PM string translate buf */ +#define MAX_LOCAL_BUF &localBuf[511] +#endif + +/*----------------------------- Implementation ----------------------------*/ + +/* static function in WinDirect for passing 32-bit registers to BIOS */ +int PMAPI WD_int386(int intno, RMREGS *in, RMREGS *out); + +void VBEAPI VBE_init(void) +/**************************************************************************** +* +* Function: VBE_init +* +* Description: Initialises the VBE transfer buffer in real mode DC.memory. +* This routine is called by the VESAVBE module every time +* it needs to use the transfer buffer, so we simply allocate +* it once and then return. +* +****************************************************************************/ +{ + if (!state->VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((state->VESABuf_ptr = PM_getVESABuf(&VESABuf_len, &state->VESABuf_rseg, &state->VESABuf_roff)) == NULL) + PM_fatalError("VESAVBE.C: Real mode memory allocation failed!"); + } +} + +void * VBEAPI VBE_getRMBuf(uint *len,uint *rseg,uint *roff) +/**************************************************************************** +* +* Function: VBE_getRMBuf +* +* Description: This function returns the location and length of the real +* mode memory buffer for calling real mode functions. +* +****************************************************************************/ +{ + *len = VESABuf_len; + *rseg = state->VESABuf_rseg; + *roff = state->VESABuf_roff; + return state->VESABuf_ptr; +} + +void VBEAPI VBE_setStateBuffer(VBE_state *s) +/**************************************************************************** +* +* Function: VBE_setStateBuffer +* +* Description: This functions sets the internal state buffer for the +* VBE module to the passed in buffer. By default the internal +* global buffer is used, but you must use separate buffers +* for each device in a multi-controller environment. +* +****************************************************************************/ +{ + state = s; +} + +void VBEAPI VBE_callESDI(RMREGS *regs, void *buffer, int size) +/**************************************************************************** +* +* Function: VBE_callESDI +* Parameters: regs - Registers to load when calling VBE +* buffer - Buffer to copy VBE info block to +* size - Size of buffer to fill +* +* Description: Calls the VESA VBE and passes in a buffer for the VBE to +* store information in, which is then copied into the users +* buffer space. This works in protected mode as the buffer +* passed to the VESA VBE is allocated in conventional +* memory, and is then copied into the users memory block. +* +****************************************************************************/ +{ + RMSREGS sregs; + + if (!state->VESABuf_ptr) + PM_fatalError("You *MUST* call VBE_init() before you can call the VESAVBE.C module!"); + sregs.es = (ushort)state->VESABuf_rseg; + regs->x.di = (ushort)state->VESABuf_roff; + memcpy(state->VESABuf_ptr, buffer, size); + PM_int86x(0x10, regs, regs, &sregs); + memcpy(buffer, state->VESABuf_ptr, size); +} + +#ifndef REALMODE +static char *VBE_copyStrToLocal(char *p,char *realPtr,char *max) +/**************************************************************************** +* +* Function: VBE_copyStrToLocal +* Parameters: p - Flat model buffer to copy to +* realPtr - Real mode pointer to copy +* Returns: Pointer to the next byte after string +* +* Description: Copies the string from the real mode location pointed to +* by 'realPtr' into the flat model buffer pointed to by +* 'p'. We return a pointer to the next byte past the copied +* string. +* +****************************************************************************/ +{ + uchar *v; + + v = PM_mapRealPointer((uint)((ulong)realPtr >> 16), (uint)((ulong)realPtr & 0xFFFF)); + while (*v != 0 && p < max) + *p++ = *v++; + *p++ = 0; + return p; +} + +static void VBE_copyShortToLocal(ushort *p,ushort *realPtr) +/**************************************************************************** +* +* Function: VBE_copyShortToLocal +* Parameters: p - Flat model buffer to copy to +* realPtr - Real mode pointer to copy +* +* Description: Copies the mode table from real mode memory to the flat +* model buffer. +* +****************************************************************************/ +{ + ushort *v; + + v = PM_mapRealPointer((uint)((ulong)realPtr >> 16),(uint)((ulong)realPtr & 0xFFFF)); + while (*v != 0xFFFF) + *p++ = *v++; + *p = 0xFFFF; +} +#endif + +int VBEAPI VBE_detectEXT(VBE_vgaInfo *vgaInfo,ibool forceUniVBE) +/**************************************************************************** +* +* Function: VBE_detect +* Parameters: vgaInfo - Place to store the VGA information block +* Returns: VBE version number, or 0 if not detected. +* +* Description: Detects if a VESA VBE is out there and functioning +* correctly. If we detect a VBE interface we return the +* VGAInfoBlock returned by the VBE and the VBE version number. +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F00; /* Get SuperVGA information */ + if (forceUniVBE) { + regs.x.bx = 0x1234; + regs.x.cx = 0x4321; + } + else { + regs.x.bx = 0; + regs.x.cx = 0; + } + strncpy(vgaInfo->VESASignature,"VBE2",4); + VBE_callESDI(®s, vgaInfo, sizeof(*vgaInfo)); + if (regs.x.ax != VBE_SUCCESS) + return 0; + if (strncmp(vgaInfo->VESASignature,"VESA",4) != 0) + return 0; + + /* Check for bogus BIOSes that return a VBE version number that is + * not correct, and fix it up. We also check the OemVendorNamePtr for a + * valid value, and if it is invalid then we also reset to VBE 1.2. + */ + if (vgaInfo->VESAVersion >= 0x200 && vgaInfo->OemVendorNamePtr == 0) + vgaInfo->VESAVersion = 0x102; +#ifndef REALMODE + /* Relocate all the indirect information (mode tables, OEM strings + * etc) from the low 1Mb memory region into a static buffer in + * our default data segment. We do this to insulate the application + * from mapping the strings from real mode to protected mode. + */ + { + char *p,*p2; + p2 = VBE_copyStrToLocal(localBuf,vgaInfo->OemStringPtr,MAX_LOCAL_BUF); + vgaInfo->OemStringPtr = localBuf; + if (vgaInfo->VESAVersion >= 0x200) { + p = VBE_copyStrToLocal(p2,vgaInfo->OemVendorNamePtr,MAX_LOCAL_BUF); + vgaInfo->OemVendorNamePtr = p2; + p2 = VBE_copyStrToLocal(p,vgaInfo->OemProductNamePtr,MAX_LOCAL_BUF); + vgaInfo->OemProductNamePtr = p; + p = VBE_copyStrToLocal(p2,vgaInfo->OemProductRevPtr,MAX_LOCAL_BUF); + vgaInfo->OemProductRevPtr = p2; + VBE_copyShortToLocal((ushort*)p,vgaInfo->VideoModePtr); + vgaInfo->VideoModePtr = (ushort*)p; + } + else { + VBE_copyShortToLocal((ushort*)p2,vgaInfo->VideoModePtr); + vgaInfo->VideoModePtr = (ushort*)p2; + } + } +#endif + state->VBEMemory = vgaInfo->TotalMemory * 64; + + /* Check for Riva128 based cards since they have broken triple buffering + * and stereo support. + */ + haveRiva128 = false; + if (vgaInfo->VESAVersion >= 0x300 && + (strstr(vgaInfo->OemStringPtr,"NVidia") != NULL || + strstr(vgaInfo->OemStringPtr,"Riva") != NULL)) { + haveRiva128 = true; + } + + /* Check for Matrox G400 cards which claim to be VBE 3.0 + * compliant yet they don't implement the refresh rate control + * functions. + */ + if (vgaInfo->VESAVersion >= 0x300 && (strcmp(vgaInfo->OemProductNamePtr,"Matrox G400") == 0)) + vgaInfo->VESAVersion = 0x200; + return (state->VBEVersion = vgaInfo->VESAVersion); +} + +int VBEAPI VBE_detect(VBE_vgaInfo *vgaInfo) +/**************************************************************************** +* +* Function: VBE_detect +* Parameters: vgaInfo - Place to store the VGA information block +* Returns: VBE version number, or 0 if not detected. +* +* Description: Detects if a VESA VBE is out there and functioning +* correctly. If we detect a VBE interface we return the +* VGAInfoBlock returned by the VBE and the VBE version number. +* +****************************************************************************/ +{ + return VBE_detectEXT(vgaInfo,false); +} + +ibool VBEAPI VBE_getModeInfo(int mode,VBE_modeInfo *modeInfo) +/**************************************************************************** +* +* Function: VBE_getModeInfo +* Parameters: mode - VBE mode to get information for +* modeInfo - Place to store VBE mode information +* Returns: True on success, false if function failed. +* +* Description: Obtains information about a specific video mode from the +* VBE. You should use this function to find the video mode +* you wish to set, as the new VBE 2.0 mode numbers may be +* completely arbitrary. +* +****************************************************************************/ +{ + RMREGS regs; + int bits; + + regs.x.ax = 0x4F01; /* Get mode information */ + regs.x.cx = (ushort)mode; + VBE_callESDI(®s, modeInfo, sizeof(*modeInfo)); + if (regs.x.ax != VBE_SUCCESS) + return false; + if ((modeInfo->ModeAttributes & vbeMdAvailable) == 0) + return false; + + /* Map out triple buffer and stereo flags for NVidia Riva128 + * chips. + */ + if (haveRiva128) { + modeInfo->ModeAttributes &= ~vbeMdTripleBuf; + modeInfo->ModeAttributes &= ~vbeMdStereo; + } + + /* Support old style RGB definitions for VBE 1.1 BIOSes */ + bits = modeInfo->BitsPerPixel; + if (modeInfo->MemoryModel == vbeMemPK && bits > 8) { + modeInfo->MemoryModel = vbeMemRGB; + switch (bits) { + case 15: + modeInfo->RedMaskSize = 5; + modeInfo->RedFieldPosition = 10; + modeInfo->GreenMaskSize = 5; + modeInfo->GreenFieldPosition = 5; + modeInfo->BlueMaskSize = 5; + modeInfo->BlueFieldPosition = 0; + modeInfo->RsvdMaskSize = 1; + modeInfo->RsvdFieldPosition = 15; + break; + case 16: + modeInfo->RedMaskSize = 5; + modeInfo->RedFieldPosition = 11; + modeInfo->GreenMaskSize = 5; + modeInfo->GreenFieldPosition = 5; + modeInfo->BlueMaskSize = 5; + modeInfo->BlueFieldPosition = 0; + modeInfo->RsvdMaskSize = 0; + modeInfo->RsvdFieldPosition = 0; + break; + case 24: + modeInfo->RedMaskSize = 8; + modeInfo->RedFieldPosition = 16; + modeInfo->GreenMaskSize = 8; + modeInfo->GreenFieldPosition = 8; + modeInfo->BlueMaskSize = 8; + modeInfo->BlueFieldPosition = 0; + modeInfo->RsvdMaskSize = 0; + modeInfo->RsvdFieldPosition = 0; + break; + } + } + + /* Convert the 32k direct color modes of VBE 1.2+ BIOSes to + * be recognised as 15 bits per pixel modes. + */ + if (bits == 16 && modeInfo->RsvdMaskSize == 1) + modeInfo->BitsPerPixel = 15; + + /* Fix up bogus BIOS'es that report incorrect reserved pixel masks + * for 32K color modes. Quite a number of BIOS'es have this problem, + * and this affects our OS/2 drivers in VBE fallback mode. + */ + if (bits == 15 && (modeInfo->RsvdMaskSize != 1 || modeInfo->RsvdFieldPosition != 15)) { + modeInfo->RsvdMaskSize = 1; + modeInfo->RsvdFieldPosition = 15; + } + return true; +} + +long VBEAPI VBE_getPageSize(VBE_modeInfo *mi) +/**************************************************************************** +* +* Function: VBE_getPageSize +* Parameters: mi - Pointer to mode information block +* Returns: Caculated page size in bytes rounded to correct boundary +* +* Description: Computes the page size in bytes for the specified mode +* information block, rounded up to the appropriate boundary +* (8k, 16k, 32k or 64k). Pages >= 64k in size are always +* rounded to the nearest 64k boundary (so the start of a +* page is always bank aligned). +* +****************************************************************************/ +{ + long size; + + size = (long)mi->BytesPerScanLine * (long)mi->YResolution; + if (mi->BitsPerPixel == 4) { + /* We have a 16 color video mode, so round up the page size to + * 8k, 16k, 32k or 64k boundaries depending on how large it is. + */ + + size = (size + 0x1FFFL) & 0xFFFFE000L; + if (size != 0x2000) { + size = (size + 0x3FFFL) & 0xFFFFC000L; + if (size != 0x4000) { + size = (size + 0x7FFFL) & 0xFFFF8000L; + if (size != 0x8000) + size = (size + 0xFFFFL) & 0xFFFF0000L; + } + } + } + else size = (size + 0xFFFFL) & 0xFFFF0000L; + return size; +} + +ibool VBEAPI VBE_setVideoModeExt(int mode,VBE_CRTCInfo *crtc) +/**************************************************************************** +* +* Function: VBE_setVideoModeExt +* Parameters: mode - SuperVGA video mode to set. +* Returns: True if the mode was set, false if not. +* +* Description: Attempts to set the specified video mode. This version +* includes support for the VBE/Core 3.0 refresh rate control +* mechanism. +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion < 0x200 && mode < 0x100) { + /* Some VBE implementations barf terribly if you try to set non-VBE + * video modes with the VBE set mode call. VBE 2.0 implementations + * must be able to handle this. + */ + regs.h.al = (ushort)mode; + regs.h.ah = 0; + PM_int86(0x10,®s,®s); + } + else { + if (state->VBEVersion < 0x300 && (mode & vbeRefreshCtrl)) + return false; + regs.x.ax = 0x4F02; + regs.x.bx = (ushort)mode; + if ((mode & vbeRefreshCtrl) && crtc) + VBE_callESDI(®s, crtc, sizeof(*crtc)); + else + PM_int86(0x10,®s,®s); + if (regs.x.ax != VBE_SUCCESS) + return false; + } + return true; +} + +ibool VBEAPI VBE_setVideoMode(int mode) +/**************************************************************************** +* +* Function: VBE_setVideoMode +* Parameters: mode - SuperVGA video mode to set. +* Returns: True if the mode was set, false if not. +* +* Description: Attempts to set the specified video mode. +* +****************************************************************************/ +{ + return VBE_setVideoModeExt(mode,NULL); +} + +int VBEAPI VBE_getVideoMode(void) +/**************************************************************************** +* +* Function: VBE_getVideoMode +* Returns: Current video mode +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F03; + PM_int86(0x10,®s,®s); + if (regs.x.ax != VBE_SUCCESS) + return -1; + return regs.x.bx; +} + +ibool VBEAPI VBE_setBank(int window,int bank) +/**************************************************************************** +* +* Function: VBE_setBank +* Parameters: window - Window to set +* bank - Bank number to set window to +* Returns: True on success, false on failure. +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F05; + regs.h.bh = 0; + regs.h.bl = window; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; +} + +int VBEAPI VBE_getBank(int window) +/**************************************************************************** +* +* Function: VBE_setBank +* Parameters: window - Window to read +* Returns: Bank number for the window (-1 on failure) +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F05; + regs.h.bh = 1; + regs.h.bl = window; + PM_int86(0x10,®s,®s); + if (regs.x.ax != VBE_SUCCESS) + return -1; + return regs.x.dx; +} + +ibool VBEAPI VBE_setPixelsPerLine(int pixelsPerLine,int *newBytes, + int *newPixels,int *maxScanlines) +/**************************************************************************** +* +* Function: VBE_setPixelsPerLine +* Parameters: pixelsPerLine - Pixels per scanline +* newBytes - Storage for bytes per line value set +* newPixels - Storage for pixels per line value set +* maxScanLines - Storage for maximum number of scanlines +* Returns: True on success, false on failure +* +* Description: Sets the scanline length for the video mode to the specified +* number of pixels per scanline. If you need more granularity +* in TrueColor modes, use the VBE_setBytesPerLine routine +* (only valid for VBE 2.0). +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F06; + regs.h.bl = 0; + regs.x.cx = pixelsPerLine; + PM_int86(0x10,®s,®s); + *newBytes = regs.x.bx; + *newPixels = regs.x.cx; + *maxScanlines = regs.x.dx; + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_setBytesPerLine(int bytesPerLine,int *newBytes, + int *newPixels,int *maxScanlines) +/**************************************************************************** +* +* Function: VBE_setBytesPerLine +* Parameters: pixelsPerLine - Pixels per scanline +* newBytes - Storage for bytes per line value set +* newPixels - Storage for pixels per line value set +* maxScanLines - Storage for maximum number of scanlines +* Returns: True on success, false on failure +* +* Description: Sets the scanline length for the video mode to the specified +* number of bytes per scanline (valid for VBE 2.0 only). +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F06; + regs.h.bl = 2; + regs.x.cx = bytesPerLine; + PM_int86(0x10,®s,®s); + *newBytes = regs.x.bx; + *newPixels = regs.x.cx; + *maxScanlines = regs.x.dx; + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_getScanlineLength(int *bytesPerLine,int *pixelsPerLine, + int *maxScanlines) +/**************************************************************************** +* +* Function: VBE_getScanlineLength +* Parameters: bytesPerLine - Storage for bytes per scanline +* pixelsPerLine - Storage for pixels per scanline +* maxScanLines - Storage for maximum number of scanlines +* Returns: True on success, false on failure +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F06; + regs.h.bl = 1; + PM_int86(0x10,®s,®s); + *bytesPerLine = regs.x.bx; + *pixelsPerLine = regs.x.cx; + *maxScanlines = regs.x.dx; + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_getMaxScanlineLength(int *maxBytes,int *maxPixels) +/**************************************************************************** +* +* Function: VBE_getMaxScanlineLength +* Parameters: maxBytes - Maximum scanline width in bytes +* maxPixels - Maximum scanline width in pixels +* Returns: True if successful, false if function failed +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F06; + regs.h.bl = 3; + PM_int86(0x10,®s,®s); + *maxBytes = regs.x.bx; + *maxPixels = regs.x.cx; + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_setDisplayStart(int x,int y,ibool waitVRT) +/**************************************************************************** +* +* Function: VBE_setDisplayStart +* Parameters: x,y - Position of the first pixel to display +* waitVRT - True to wait for retrace, false if not +* Returns: True if function was successful. +* +* Description: Sets the new starting display position to implement +* hardware scrolling. +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F07; + if (waitVRT) + regs.x.bx = 0x80; + else regs.x.bx = 0x00; + regs.x.cx = x; + regs.x.dx = y; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_getDisplayStart(int *x,int *y) +/**************************************************************************** +* +* Function: VBE_getDisplayStart +* Parameters: x,y - Place to store starting address value +* Returns: True if function was successful. +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F07; + regs.x.bx = 0x01; + PM_int86(0x10,®s,®s); + *x = regs.x.cx; + *y = regs.x.dx; + return regs.x.ax == VBE_SUCCESS; +} + +ibool VBEAPI VBE_setDisplayStartAlt(ulong startAddr,ibool waitVRT) +/**************************************************************************** +* +* Function: VBE_setDisplayStartAlt +* Parameters: startAddr - 32-bit starting address in display memory +* waitVRT - True to wait for vertical retrace, false if not +* Returns: True if function was successful, false if not supported. +* +* Description: Sets the new starting display position to the specified +* 32-bit display start address. Note that this function is +* different the the version above, since it takes a 32-bit +* byte offset in video memory as the starting address which +* gives the programmer maximum control over the stat address. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F07; + regs.x.bx = waitVRT ? 0x82 : 0x02; + regs.e.ecx = startAddr; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; + } + return false; +} + +int VBEAPI VBE_getDisplayStartStatus(void) +/**************************************************************************** +* +* Function: VBE_getDisplayStartStatus +* Returns: 0 if last flip not occurred, 1 if already flipped +* -1 if not supported +* +* Description: Returns the status of the previous display start request. +* If this function is supported the programmer can implement +* hardware triple buffering using this function. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F07; + regs.x.bx = 0x0004; + PM_int86(0x10,®s,®s); + if (regs.x.ax == VBE_SUCCESS) + return (regs.x.cx != 0); + } + return -1; +} + +ibool VBEAPI VBE_enableStereoMode(void) +/**************************************************************************** +* +* Function: VBE_enableStereoMode +* Returns: True if stereo mode enabled, false if not supported. +* +* Description: Puts the system into hardware stereo mode for LC shutter +* glasses, where the display swaps between two display start +* addresses every vertical retrace. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F07; + regs.x.bx = 0x0005; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; + } + return false; +} + +ibool VBEAPI VBE_disableStereoMode(void) +/**************************************************************************** +* +* Function: VBE_disableStereoMode +* Returns: True if stereo mode disabled, false if not supported. +* +* Description: Puts the system back into normal, non-stereo display mode +* after having stereo mode enabled. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F07; + regs.x.bx = 0x0006; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; + } + return false; +} + +ibool VBEAPI VBE_setStereoDisplayStart(ulong leftAddr,ulong rightAddr, + ibool waitVRT) +/**************************************************************************** +* +* Function: VBE_setStereoDisplayStart +* Parameters: leftAddr - 32-bit start address for left image +* rightAddr - 32-bit start address for right image +* waitVRT - True to wait for vertical retrace, false if not +* Returns: True if function was successful, false if not supported. +* +* Description: Sets the new starting display position to the specified +* 32-bit display start address. Note that this function is +* different the the version above, since it takes a 32-bit +* byte offset in video memory as the starting address which +* gives the programmer maximum control over the stat address. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F07; + regs.x.bx = waitVRT ? 0x83 : 0x03; + regs.e.ecx = leftAddr; + regs.e.edx = rightAddr; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; + } + return false; +} + +ulong VBEAPI VBE_getClosestClock(ushort mode,ulong pixelClock) +/**************************************************************************** +* +* Function: VBE_getClosestClock +* Parameters: mode - VBE mode to be used (include vbeLinearBuffer) +* pixelClock - Desired pixel clock +* Returns: Closest pixel clock to desired clock (-1 if not supported) +* +* Description: Calls the VBE/Core 3.0 interface to determine the closest +* pixel clock to the requested value. The BIOS will always +* search for a pixel clock that is no more than 1% below the +* requested clock or somewhere higher than the clock. If the +* clock is higher note that it may well be many Mhz higher +* that requested and the application will have to check that +* the returned value is suitable for it's needs. This function +* returns the actual pixel clock that will be programmed by +* the hardware. +* +* Note that if the pixel clock will be used with a linear +* framebuffer mode, make sure you pass in the linear +* framebuffer flag to this function. +* +* NOTE: Requires VBE/Core 3.0 +* +****************************************************************************/ +{ + RMREGS regs; + + if (state->VBEVersion >= 0x300) { + regs.x.ax = 0x4F0B; + regs.h.bl = 0x00; + regs.e.ecx = pixelClock; + regs.x.dx = mode; + PM_int86(0x10,®s,®s); + if (regs.x.ax == VBE_SUCCESS) + return regs.e.ecx; + } + return -1; +} + +ibool VBEAPI VBE_setDACWidth(int width) +/**************************************************************************** +* +* Function: VBE_setDACWidth +* Parameters: width - Width to set the DAC to +* Returns: True on success, false on failure +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F08; + regs.h.bl = 0x00; + regs.h.bh = width; + PM_int86(0x10,®s,®s); + return regs.x.ax == VBE_SUCCESS; +} + +int VBEAPI VBE_getDACWidth(void) +/**************************************************************************** +* +* Function: VBE_getDACWidth +* Returns: Current width of the palette DAC +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F08; + regs.h.bl = 0x01; + PM_int86(0x10,®s,®s); + if (regs.x.ax != VBE_SUCCESS) + return -1; + return regs.h.bh; +} + +ibool VBEAPI VBE_setPalette(int start,int num,VBE_palette *pal,ibool waitVRT) +/**************************************************************************** +* +* Function: VBE_setPalette +* Parameters: start - Starting palette index to program +* num - Number of palette indexes to program +* pal - Palette buffer containing values +* waitVRT - Wait for vertical retrace flag +* Returns: True on success, false on failure +* +* Description: Sets a block of palette registers by calling the VBE 2.0 +* BIOS. This function will fail on VBE 1.2 implementations. +* +****************************************************************************/ +{ + RMREGS regs; + + regs.x.ax = 0x4F09; + regs.h.bl = waitVRT ? 0x80 : 0x00; + regs.x.cx = num; + regs.x.dx = start; + VBE_callESDI(®s, pal, sizeof(VBE_palette) * num); + return regs.x.ax == VBE_SUCCESS; +} + +void * VBEAPI VBE_getBankedPointer(VBE_modeInfo *modeInfo) +/**************************************************************************** +* +* Function: VBE_getBankedPointer +* Parameters: modeInfo - Mode info block for video mode +* Returns: Selector to the linear framebuffer (0 on failure) +* +* Description: Returns a near pointer to the VGA framebuffer area. +* +****************************************************************************/ +{ + /* We just map the pointer every time, since the pointer will always + * be in real mode memory, so we wont actually be mapping any real + * memory. + * + * NOTE: We cannot currently map a near pointer to the banked frame + * buffer for Watcom Win386, so we create a 16:16 far pointer to + * the video memory. All the assembler code will render to the + * video memory by loading the selector rather than using a + * near pointer. + */ + ulong seg = (ushort)modeInfo->WinASegment; + if (seg != 0) { + if (seg == 0xA000) + return (void*)PM_getA0000Pointer(); + else + return (void*)PM_mapPhysicalAddr(seg << 4,0xFFFF,true); + } + return NULL; +} + +#ifndef REALMODE + +void * VBEAPI VBE_getLinearPointer(VBE_modeInfo *modeInfo) +/**************************************************************************** +* +* Function: VBE_getLinearPointer +* Parameters: modeInfo - Mode info block for video mode +* Returns: Selector to the linear framebuffer (0 on failure) +* +* Description: Returns a near pointer to the linear framebuffer for the video +* mode. +* +****************************************************************************/ +{ + static ulong physPtr[MAX_LIN_PTRS] = {0}; + static void *linPtr[MAX_LIN_PTRS] = {0}; + static int numPtrs = 0; + int i; + + /* Search for an already mapped pointer */ + for (i = 0; i < numPtrs; i++) { + if (physPtr[i] == modeInfo->PhysBasePtr) + return linPtr[i]; + } + if (numPtrs < MAX_LIN_PTRS) { + physPtr[numPtrs] = modeInfo->PhysBasePtr; + linPtr[numPtrs] = PM_mapPhysicalAddr(modeInfo->PhysBasePtr,(state->VBEMemory * 1024L)-1,true); + return linPtr[numPtrs++]; + } + return NULL; +} + +static void InitPMCode(void) +/**************************************************************************** +* +* Function: InitPMCode - 32 bit protected mode version +* +* Description: Finds the address of and relocates the protected mode +* code block from the VBE 2.0 into a local memory block. The +* memory block is allocated with malloc() and must be freed +* with VBE_freePMCode() after graphics processing is complete. +* +* Note that this buffer _must_ be recopied after each mode set, +* as the routines will change depending on the underlying +* video mode. +* +****************************************************************************/ +{ + RMREGS regs; + RMSREGS sregs; + uchar *code; + int pmLen; + + if (!state->pmInfo && state->VBEVersion >= 0x200) { + regs.x.ax = 0x4F0A; + regs.x.bx = 0; + PM_int86x(0x10,®s,®s,&sregs); + if (regs.x.ax != VBE_SUCCESS) + return; + if (VBE_shared) + state->pmInfo = PM_mallocShared(regs.x.cx); + else + state->pmInfo = PM_malloc(regs.x.cx); + if (state->pmInfo == NULL) + return; + state->pmInfo32 = state->pmInfo; + pmLen = regs.x.cx; + + /* Relocate the block into our local data segment */ + code = PM_mapRealPointer(sregs.es,regs.x.di); + memcpy(state->pmInfo,code,pmLen); + + /* Now do a sanity check on the information we recieve to ensure + * that is is correct. Some BIOS return totally bogus information + * in here (Matrox is one)! Under DOS this works OK, but under OS/2 + * we are screwed. + */ + if (state->pmInfo->setWindow >= pmLen || + state->pmInfo->setDisplayStart >= pmLen || + state->pmInfo->setPalette >= pmLen || + state->pmInfo->IOPrivInfo >= pmLen) { + if (VBE_shared) + PM_freeShared(state->pmInfo); + else + PM_free(state->pmInfo); + state->pmInfo32 = state->pmInfo = NULL; + return; + } + + /* Read the IO priveledge info and determine if we need to + * pass a selector to MMIO registers to the bank switch code. + * Since we no longer support selector allocation, we no longer + * support this mechanism so we disable the protected mode + * interface in this case. + */ + if (state->pmInfo->IOPrivInfo && !state->MMIOSel) { + ushort *p = (ushort*)((uchar*)state->pmInfo + state->pmInfo->IOPrivInfo); + while (*p != 0xFFFF) + p++; + p++; + if (*p != 0xFFFF) + VBE_freePMCode(); + } + } +} + +void * VBEAPI VBE_getSetBank(void) +/**************************************************************************** +* +* Function: VBE_getSetBank +* Returns: Pointer to the 32 VBE 2.0 bit bank switching routine. +* +****************************************************************************/ +{ + if (state->VBEVersion >= 0x200) { + InitPMCode(); + if (state->pmInfo) + return (uchar*)state->pmInfo + state->pmInfo->setWindow; + } + return NULL; +} + +void * VBEAPI VBE_getSetDisplayStart(void) +/**************************************************************************** +* +* Function: VBE_getSetDisplayStart +* Returns: Pointer to the 32 VBE 2.0 bit CRT start address routine. +* +****************************************************************************/ +{ + if (state->VBEVersion >= 0x200) { + InitPMCode(); + if (state->pmInfo) + return (uchar*)state->pmInfo + state->pmInfo->setDisplayStart; + } + return NULL; +} + +void * VBEAPI VBE_getSetPalette(void) +/**************************************************************************** +* +* Function: VBE_getSetPalette +* Returns: Pointer to the 32 VBE 2.0 bit palette programming routine. +* +****************************************************************************/ +{ + if (state->VBEVersion >= 0x200) { + InitPMCode(); + if (state->pmInfo) + return (uchar*)state->pmInfo + state->pmInfo->setPalette; + } + return NULL; +} + +void VBEAPI VBE_freePMCode(void) +/**************************************************************************** +* +* Function: VBE_freePMCode +* +* Description: This routine frees the protected mode code blocks that +* we copied from the VBE 2.0 interface. This routine must +* be after you have finished graphics processing to free up +* the memory occupied by the routines. This is necessary +* because the PM info memory block must be re-copied after +* every video mode set from the VBE 2.0 implementation. +* +****************************************************************************/ +{ + if (state->pmInfo) { + if (VBE_shared) + PM_freeShared(state->pmInfo); + else + PM_free(state->pmInfo); + state->pmInfo = NULL; + state->pmInfo32 = NULL; + } +} + +void VBEAPI VBE_sharePMCode(void) +/**************************************************************************** +* +* Function: VBE_sharePMCode +* +* Description: Enables internal sharing of the PM code buffer for OS/2. +* +****************************************************************************/ +{ + VBE_shared = true; +} + +/* Set of code stubs used to build the final bank switch code */ + +#define VBE20_adjustOffset 7 + +static uchar VBE20A_bankFunc32_Start[] = { + 0x53,0x51, /* push ebx,ecx */ + 0x8B,0xD0, /* mov edx,eax */ + 0x33,0xDB, /* xor ebx,ebx */ + 0xB1,0x00, /* mov cl,0 */ + 0xD2,0xE2, /* shl dl,cl */ + }; + +static uchar VBE20_bankFunc32_End[] = { + 0x59,0x5B, /* pop ecx,ebx */ + }; + +static uchar bankFunc32[100]; + +#define copy(p,b,a) memcpy(b,a,sizeof(a)); (p) = (b) + sizeof(a) + +ibool VBEAPI VBE_getBankFunc32(int *codeLen,void **bankFunc,int dualBanks, + int bankAdjust) +/**************************************************************************** +* +* Function: VBE_getBankFunc32 +* Parameters: codeLen - Place to store length of code +* bankFunc - Place to store pointer to bank switch code +* dualBanks - True if dual banks are in effect +* bankAdjust - Bank shift adjustment factor +* Returns: True on success, false if not compatible. +* +* Description: Creates a local 32 bit bank switch function from the +* VBE 2.0 bank switch code that is compatible with the +* virtual flat framebuffer devices (does not have a return +* instruction at the end and takes the bank number in EAX +* not EDX). Note that this 32 bit code cannot include int 10h +* instructions, so we can only do this if we have VBE 2.0 +* or later. +* +* Note that we need to know the length of the 32 bit +* bank switch function, which the standard VBE 2.0 spec +* does not provide. In order to support this we have +* extended the VBE 2.0 state->pmInfo structure in UniVBE 5.2 in a +* way to support this, and we hope that this will become +* a VBE 2.0 ammendment. +* +* Note also that we cannot run the linear framebuffer +* emulation code with bank switching routines that require +* a selector to the memory mapped registers passed in ES. +* +****************************************************************************/ +{ + int len; + uchar *code; + uchar *p; + + InitPMCode(); + if (state->VBEVersion >= 0x200 && state->pmInfo32 && !state->MMIOSel) { + code = (uchar*)state->pmInfo32 + state->pmInfo32->setWindow; + if (state->pmInfo32->extensionSig == VBE20_EXT_SIG) + len = state->pmInfo32->setWindowLen-1; + else { + /* We are running on a system without the UniVBE 5.2 extension. + * We do as best we can by scanning through the code for the + * ret function to determine the length. This is not foolproof, + * but is the best we can do. + */ + p = code; + while (*p != 0xC3) + p++; + len = p - code; + } + if ((len + sizeof(VBE20A_bankFunc32_Start) + sizeof(VBE20_bankFunc32_End)) > sizeof(bankFunc32)) + PM_fatalError("32-bit bank switch function too long!"); + copy(p,bankFunc32,VBE20A_bankFunc32_Start); + memcpy(p,code,len); + p += len; + copy(p,p,VBE20_bankFunc32_End); + *codeLen = p - bankFunc32; + bankFunc32[VBE20_adjustOffset] = (uchar)bankAdjust; + *bankFunc = bankFunc32; + return true; + } + return false; +} + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c new file mode 100644 index 000000000..cb3afe20c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/cpuinfo.c @@ -0,0 +1,80 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: Module to implement OS specific services to measure the +* CPU frequency. +* +****************************************************************************/ + +#include + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Increase the thread priority to maximum, if possible. +****************************************************************************/ +static int SetMaxThreadPriority(void) +{ + thread_id thid = find_thread(NULL); + thread_info tinfo; + get_thread_info(thid, &tinfo); + set_thread_priority(thid, B_REAL_TIME_PRIORITY); + return tinfo.priority; +} + +/**************************************************************************** +REMARKS: +Restore the original thread priority. +****************************************************************************/ +static void RestoreThreadPriority( + int priority) +{ + thread_id thid = find_thread(NULL); + set_thread_priority(thid, priority); +} + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + /* TODO: Return the frequency of the counter in here. You should try to */ + /* normalise this value to be around 100,000 ticks per second. */ + freq->low = 1000000; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. + +TODO: Implement this to read the counter. It should be done as a macro + for accuracy. +****************************************************************************/ +#define GetCounter(t) { *((bigtime_t*) t) = system_time(); } diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/event.c b/board/MAI/bios_emulator/scitech/src/pm/beos/event.c new file mode 100644 index 000000000..93c6c0a8f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/event.c @@ -0,0 +1,199 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: BeOS +* +* Description: BeOS implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under non-DOS systems */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + /* TODO: Implement this for your OS! */ +} + +/**************************************************************************** +REMARKS: +Pumps all messages in the application message queue into our event queue. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + /* TODO: The purpose of this function is to read all keyboard and mouse */ + /* events from the OS specific event queue, translate them and post */ + /* them into the SciTech event queue. */ + /* */ + /* NOTE: There are a couple of important things that this function must */ + /* take care of: */ + /* */ + /* 1. Support for KEYDOWN, KEYREPEAT and KEYUP is required. */ + /* */ + /* 2. Support for reading hardware scan code as well as ASCII */ + /* translated values is required. Games use the scan codes rather */ + /* than ASCII values. Scan codes go into the high order byte of the */ + /* keyboard message field. */ + /* */ + /* 3. Support for at least reading mouse motion data (mickeys) from the */ + /* mouse is required. Using the mickey values, we can then translate */ + /* to mouse cursor coordinates scaled to the range of the current */ + /* graphics display mode. Mouse values are scaled based on the */ + /* global 'rangeX' and 'rangeY'. */ + /* */ + /* 4. Support for a timestamp for the events is required, which is */ + /* defined as the number of milliseconds since some event (usually */ + /* system startup). This is the timestamp when the event occurred */ + /* (ie: at interrupt time) not when it was stuff into the SciTech */ + /* event queue. */ + /* */ + /* 5. Support for mouse double click events. If the OS has a native */ + /* mechanism to determine this, it should be used. Otherwise the */ + /* time stamp information will be used by the generic event code */ + /* to generate double click events. */ +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + /* Initialise the event queue */ + _mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* TODO: Do any OS specific initialisation here */ + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* TODO: Do any OS specific cleanup in here */ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h new file mode 100644 index 000000000..043d73ecd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/oshdr.h @@ -0,0 +1,32 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: BeOS +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +/* This is where you include OS specific headers for the event handling */ +/* library. */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c b/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c new file mode 100644 index 000000000..2dcb1b81f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/pm.c @@ -0,0 +1,539 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: BeOS +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include +#include +#include + +/* TODO: Include any BeOS specific headers here! */ + +/*--------------------------- Global variables ----------------------------*/ + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +void PMAPI PM_init(void) +{ + /* TODO: Do any initialisation in here. This includes getting IOPL */ + /* access for the process calling PM_init. This will get called */ + /* more than once. */ + + /* TODO: If you support the supplied MTRR register stuff (you need to */ + /* be at ring 0 for this!), you should initialise it in here. */ + +/* MTRR_init(); */ +} + +long PMAPI PM_getOSType(void) +{ return _OS_BEOS; } + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '/') { + s[pos] = '/'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + /* TODO: If you are running in a GUI environment without a console, */ + /* this needs to be changed to bring up a fatal error message */ + /* box and terminate the program. */ + if (fatalErrorCleanup) + fatalErrorCleanup(); + fprintf(stderr,"%s\n", msg); + exit(1); +} + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) +{ + /* No BIOS access for the BeOS */ + return NULL; +} + +int PMAPI PM_kbhit(void) +{ + /* TODO: This function checks if a key is available to be read. This */ + /* should be implemented, but is mostly used by the test programs */ + /* these days. */ + return true; +} + +int PMAPI PM_getch(void) +{ + /* TODO: This returns the ASCII code of the key pressed. This */ + /* should be implemented, but is mostly used by the test programs */ + /* these days. */ + return 0xD; +} + +int PMAPI PM_openConsole(void) +{ + /* TODO: Opens up a fullscreen console for graphics output. If your */ + /* console does not have graphics/text modes, this can be left */ + /* empty. The main purpose of this is to disable console switching */ + /* when in graphics modes if you can switch away from fullscreen */ + /* consoles (if you want to allow switching, this can be done */ + /* elsewhere with a full save/restore state of the graphics mode). */ + return 0; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + /* TODO: Returns the size of the console state buffer used to save the */ + /* state of the console before going into graphics mode. This is */ + /* used to restore the console back to normal when we are done. */ + return 1; +} + +void PMAPI PM_saveConsoleState(void *stateBuf,int console_id) +{ + /* TODO: Saves the state of the console into the state buffer. This is */ + /* used to restore the console back to normal when we are done. */ + /* We will always restore 80x25 text mode after being in graphics */ + /* mode, so if restoring text mode is all you need to do this can */ + /* be left empty. */ +} + +void PMAPI PM_restoreConsoleState(const void *stateBuf,int console_id) +{ + /* TODO: Restore the state of the console from the state buffer. This is */ + /* used to restore the console back to normal when we are done. */ + /* We will always restore 80x25 text mode after being in graphics */ + /* mode, so if restoring text mode is all you need to do this can */ + /* be left empty. */ +} + +void PMAPI PM_closeConsole(int console_id) +{ + /* TODO: Close the console when we are done, going back to text mode. */ +} + +void PM_setOSCursorLocation(int x,int y) +{ + /* TODO: Set the OS console cursor location to the new value. This is */ + /* generally used for new OS ports (used mostly for DOS). */ +} + +void PM_setOSScreenWidth(int width,int height) +{ + /* TODO: Set the OS console screen width. This is generally unused for */ + /* new OS ports. */ +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency) +{ + /* TODO: Install a real time clock interrupt handler. Normally this */ + /* will not be supported from most OS'es in user land, so an */ + /* alternative mechanism is needed to enable software stereo. */ + /* Hence leave this unimplemented unless you have a high priority */ + /* mechanism to call the 32-bit callback when the real time clock */ + /* interrupt fires. */ + return false; +} + +void PMAPI PM_setRealTimeClockFrequency(int frequency) +{ + /* TODO: Set the real time clock interrupt frequency. Used for stereo */ + /* LC shutter glasses when doing software stereo. Usually sets */ + /* the frequency to around 2048 Hz. */ +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* TODO: Restores the real time clock handler. */ +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +char PMAPI PM_getBootDrive(void) +{ return '/'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return PM_getNucleusConfigPath(); } + +const char * PMAPI PM_getNucleusPath(void) +{ + char *env = getenv("NUCLEUS_PATH"); + return env ? env : "/usr/lib/nucleus"; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ + /* TODO: Return a unique ID for the machine. If a unique ID is not */ + /* available, return the machine name. */ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +const char * PMAPI PM_getMachineName(void) +{ + /* TODO: Return the network machine name for the machine. */ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +void * PMAPI PM_getBIOSPointer(void) +{ + /* No BIOS access on the BeOS */ + return NULL; +} + +void * PMAPI PM_getA0000Pointer(void) +{ + static void *bankPtr; + if (!bankPtr) + bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); + return bankPtr; +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + /* TODO: This function maps a physical memory address to a linear */ + /* address in the address space of the calling process. */ + + /* NOTE: This function *must* be able to handle any phsyical base */ + /* address, and hence you will have to handle rounding of */ + /* the physical base address to a page boundary (ie: 4Kb on */ + /* x86 CPU's) to be able to properly map in the memory */ + /* region. */ + + /* NOTE: If possible the isCached bit should be used to ensure that */ + /* the PCD (Page Cache Disable) and PWT (Page Write Through) */ + /* bits are set to disable caching for a memory mapping used */ + /* for MMIO register access. We also disable caching using */ + /* the MTRR registers for Pentium Pro and later chipsets so if */ + /* MTRR support is enabled for your OS then you can safely ignore */ + /* the isCached flag and always enable caching in the page */ + /* tables. */ + return NULL; +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + /* TODO: This function will free a physical memory mapping previously */ + /* allocated with PM_mapPhysicalAddr() if at all possible. If */ + /* you can't free physical memory mappings, simply do nothing. */ +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* TODO: Put the process to sleep for milliseconds */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +void * PMAPI PM_mallocShared(long size) +{ + /* TODO: This is used to allocate memory that is shared between process */ + /* that all access the common Nucleus drivers via a common display */ + /* driver DLL. If your OS does not support shared memory (or if */ + /* the display driver does not need to allocate shared memory */ + /* for each process address space), this should just call PM_malloc. */ + return PM_malloc(size); +} + +void PMAPI PM_freeShared(void *ptr) +{ + /* TODO: Free the shared memory block. This will be called in the context */ + /* of the original calling process that allocated the shared */ + /* memory with PM_mallocShared. Simply call free if you do not */ + /* need this. */ + PM_free(ptr); +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ + /* TODO: This function is used to map a physical memory mapping */ + /* previously allocated with PM_mapPhysicalAddr into the */ + /* address space of the calling process. If the memory mapping */ + /* allocated by PM_mapPhysicalAddr is global to all processes, */ + /* simply return the pointer. */ + return base; +} + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + /* No BIOS access on the BeOS */ + return NULL; +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + /* No BIOS access on the BeOS */ + return NULL; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + /* No BIOS access on the BeOS */ +} + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + /* No BIOS access on the BeOS */ +} + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + /* No BIOS access on the BeOS */ + return 0; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + /* No BIOS access on the BeOS */ + return 0; +} + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, + RMSREGS *sregs) +{ + /* No BIOS access on the BeOS */ +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + /* TODO: Report the amount of available memory, both the amount of */ + /* physical memory left and the amount of virtual memory left. */ + /* If the OS does not provide these services, report 0's. */ + *physical = *total = 0; +} + +void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16Meg) +{ + /* TODO: Allocate a block of locked, physical memory of the specified */ + /* size. This is used for bus master operations. If this is not */ + /* supported by the OS, return NULL and bus mastering will not */ + /* be used. */ + return NULL; +} + +void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) +{ + /* TODO: Free a memory block allocated with PM_allocLockedMem. */ +} + +void PMAPI PM_setBankA(int bank) +{ + /* No BIOS access on the BeOS */ +} + +void PMAPI PM_setBankAB(int bank) +{ + /* No BIOS access on the BeOS */ +} + +void PMAPI PM_setCRTStart(int x,int y,int waitVRT) +{ + /* No BIOS access on the BeOS */ +} + +ibool PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type) +{ + /* TODO: This function should enable Pentium Pro and Pentium II MTRR */ + /* write combining for the passed in physical memory base address */ + /* and length. Normally this is done via calls to an OS specific */ + /* device driver as this can only be done at ring 0. */ + /* */ + /* NOTE: This is a *very* important function to implement! If you do */ + /* not implement, graphics performance on the latest Intel chips */ + /* will be severly impaired. For sample code that can be used */ + /* directly in a ring 0 device driver, see the MSDOS implementation */ + /* which includes assembler code to do this directly (if the */ + /* program is running at ring 0). */ + return false; +} + +ibool PMAPI PM_doBIOSPOST(ushort axVal,ulong BIOSPhysAddr,void *mappedBIOS) +{ + /* TODO: This function is used to run the BIOS POST code on a secondary */ + /* controller to initialise it for use. This is not necessary */ + /* for multi-controller operation, but it will make it a lot */ + /* more convenicent for end users (otherwise they have to boot */ + /* the system once with the secondary controller as primary, and */ + /* then boot with both controllers installed). */ + /* */ + /* Even if you don't support full BIOS access, it would be */ + /* adviseable to be able to POST the secondary controllers in the */ + /* system using this function as a minimum requirement. Some */ + /* graphics hardware has registers that contain values that only */ + /* the BIOS knows about, which makes bring up a card from cold */ + /* reset difficult if the BIOS has not POST'ed it. */ + return false; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +ulong PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + ulong handle, + PM_findData *findData) +{ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + ulong handle) +{ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + if (drive == 3) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + (void)drive; + getcwd(dir,len); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + /* TODO: Set the file attributes for a file */ + (void)filename; + (void)attrib; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c new file mode 100644 index 000000000..579ef2c95 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c new file mode 100644 index 000000000..a528b7317 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/beos/ztimer.c @@ -0,0 +1,111 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void _ZTimerInit(void) +{ + /* TODO: Do any specific internal initialisation in here */ +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +static void _LZTimerOn( + LZTimerObject *tm) +{ + /* TODO: Start the Zen Timer counting. This should be a macro if */ + /* possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +static ulong _LZTimerLap( + LZTimerObject *tm) +{ + /* TODO: Compute the lap time between the current time and when the */ + /* timer was started. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Stop the Zen Timer counting. +****************************************************************************/ +static void _LZTimerOff( + LZTimerObject *tm) +{ + /* TODO: Stop the timer counting. Should be a macro if possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time in microseconds between start and end timings. +****************************************************************************/ +static ulong _LZTimerCount( + LZTimerObject *tm) +{ + /* TODO: Compute the elapsed time and return it. Always microseconds. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1 + +/**************************************************************************** +REMARKS: +Read the Long Period timer from the OS +****************************************************************************/ +static ulong _ULZReadTime(void) +{ + /* TODO: Read the long period timer from the OS. The resolution of this */ + /* timer should be around 1/20 of a second for timing long */ + /* periods if possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong _ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c b/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c new file mode 100644 index 000000000..9aa871423 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/codepage/us_eng.c @@ -0,0 +1,285 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Keyboard translation code pages for US English keyboards. +* +****************************************************************************/ + +#include "event.h" + +/*--------------------------- Global variables ----------------------------*/ + +/* This table is used for all normal key translations, and is the fallback + * table if the key is not found in any of the other translation tables. + * If the code is not found in this table, the ASCII code is set to 0 to + * indicate that there is no ASCII code equivalent for this key. + */ +static codepage_entry_t US_normal[] = { + {0x01, 0x1B}, + {0x02, '1'}, + {0x03, '2'}, + {0x04, '3'}, + {0x05, '4'}, + {0x06, '5'}, + {0x07, '6'}, + {0x08, '7'}, + {0x09, '8'}, + {0x0A, '9'}, + {0x0B, '0'}, + {0x0C, '-'}, + {0x0D, '='}, + {0x0E, 0x08}, + {0x0F, 0x09}, + {0x10, 'q'}, + {0x11, 'w'}, + {0x12, 'e'}, + {0x13, 'r'}, + {0x14, 't'}, + {0x15, 'y'}, + {0x16, 'u'}, + {0x17, 'i'}, + {0x18, 'o'}, + {0x19, 'p'}, + {0x1A, '['}, + {0x1B, ']'}, + {0x1C, 0x0D}, + {0x1E, 'a'}, + {0x1F, 's'}, + {0x20, 'd'}, + {0x21, 'f'}, + {0x22, 'g'}, + {0x23, 'h'}, + {0x24, 'j'}, + {0x25, 'k'}, + {0x26, 'l'}, + {0x27, ';'}, + {0x28, '\''}, + {0x29, '`'}, + {0x2B, '\\'}, + {0x2C, 'z'}, + {0x2D, 'x'}, + {0x2E, 'c'}, + {0x2F, 'v'}, + {0x30, 'b'}, + {0x31, 'n'}, + {0x32, 'm'}, + {0x33, ','}, + {0x34, '.'}, + {0x35, '/'}, + {0x37, '*'}, /* Keypad */ + {0x39, ' '}, + {0x4A, '-'}, /* Keypad */ + {0x4E, '+'}, /* Keypad */ + {0x60, 0x0D}, /* Keypad */ + {0x61, '/'}, /* Keypad */ + }; + +/* This table is used for when CAPSLOCK is active and the shift or ctrl + * keys are not down. If the code is not found in this table, the normal + * table above is then searched. + */ +static codepage_entry_t US_caps[] = { + {0x10, 'Q'}, + {0x11, 'W'}, + {0x12, 'E'}, + {0x13, 'R'}, + {0x14, 'T'}, + {0x15, 'Y'}, + {0x16, 'U'}, + {0x17, 'I'}, + {0x18, 'O'}, + {0x19, 'P'}, + {0x1E, 'A'}, + {0x1F, 'S'}, + {0x20, 'D'}, + {0x21, 'F'}, + {0x22, 'G'}, + {0x23, 'H'}, + {0x24, 'J'}, + {0x25, 'K'}, + {0x26, 'L'}, + {0x2C, 'Z'}, + {0x2D, 'X'}, + {0x2E, 'C'}, + {0x2F, 'V'}, + {0x30, 'B'}, + {0x31, 'N'}, + {0x32, 'M'}, + }; + +/* This table is used for when shift key is down, but the ctrl key is not + * down and CAPSLOCK is not active. If the code is not found in this table, + * the normal table above is then searched. + */ +static codepage_entry_t US_shift[] = { + {0x02, '!'}, + {0x03, '@'}, + {0x04, '#'}, + {0x05, '$'}, + {0x06, '%'}, + {0x07, '^'}, + {0x08, '&'}, + {0x09, '*'}, + {0x0A, '('}, + {0x0B, ')'}, + {0x0C, '_'}, + {0x0D, '+'}, + {0x10, 'Q'}, + {0x11, 'W'}, + {0x12, 'E'}, + {0x13, 'R'}, + {0x14, 'T'}, + {0x15, 'Y'}, + {0x16, 'U'}, + {0x17, 'I'}, + {0x18, 'O'}, + {0x19, 'P'}, + {0x1A, '{'}, + {0x1B, '}'}, + {0x1E, 'A'}, + {0x1F, 'S'}, + {0x20, 'D'}, + {0x21, 'F'}, + {0x22, 'G'}, + {0x23, 'H'}, + {0x24, 'J'}, + {0x25, 'K'}, + {0x26, 'L'}, + {0x27, ':'}, + {0x28, '"'}, + {0x29, '~'}, + {0x2B, '|'}, + {0x2C, 'Z'}, + {0x2D, 'X'}, + {0x2E, 'C'}, + {0x2F, 'V'}, + {0x30, 'B'}, + {0x31, 'N'}, + {0x32, 'M'}, + {0x33, '<'}, + {0x34, '>'}, + {0x35, '?'}, + }; + +/* This table is used for when CAPSLOCK is active and the shift key is + * down, but the ctrl key is not. If the code is not found in this table, + * the shift table above is then searched. + */ +static codepage_entry_t US_shiftCaps[] = { + {0x10, 'q'}, + {0x11, 'w'}, + {0x12, 'e'}, + {0x13, 'r'}, + {0x14, 't'}, + {0x15, 'y'}, + {0x16, 'u'}, + {0x17, 'i'}, + {0x18, 'o'}, + {0x19, 'p'}, + {0x1E, 'a'}, + {0x1F, 's'}, + {0x20, 'd'}, + {0x21, 'f'}, + {0x22, 'g'}, + {0x23, 'h'}, + {0x24, 'j'}, + {0x25, 'k'}, + {0x26, 'l'}, + {0x2C, 'z'}, + {0x2D, 'x'}, + {0x2E, 'c'}, + {0x2F, 'v'}, + {0x30, 'b'}, + {0x31, 'n'}, + {0x32, 'm'}, + }; + +/* This table is used for all key translations when the ctrl key is down, + * regardless of the state of the shift key and CAPSLOCK. If the code is + * not found in this table, the ASCII code is set to 0 to indicate that + * there is no ASCII code equivalent for this key. + */ +static codepage_entry_t US_ctrl[] = { + {0x01, 0x1B}, + {0x06, 0x1E}, + {0x0C, 0x1F}, + {0x0E, 0x7F}, + {0x10, 0x11}, + {0x11, 0x17}, + {0x12, 0x05}, + {0x13, 0x12}, + {0x14, 0x14}, + {0x15, 0x19}, + {0x16, 0x16}, + {0x17, 0x09}, + {0x18, 0x0F}, + {0x19, 0x10}, + {0x1A, 0x1B}, + {0x1B, 0x1D}, + {0x1C, 0x0A}, + {0x1E, 0x01}, + {0x1F, 0x13}, + {0x20, 0x04}, + {0x21, 0x06}, + {0x22, 0x07}, + {0x23, 0x08}, + {0x24, 0x0A}, + {0x25, 0x0B}, + {0x26, 0x0C}, + {0x2B, 0x1C}, + {0x2C, 0x1A}, + {0x2D, 0x18}, + {0x2E, 0x03}, + {0x2F, 0x16}, + {0x30, 0x02}, + {0x31, 0x0E}, + {0x32, 0x0D}, + {0x39, ' '}, + }; + +static codepage_entry_t US_numPad[] = { + {0x4C, '5'}, + {0x62, '4'}, + {0x63, '6'}, + {0x64, '8'}, + {0x65, '2'}, + {0x66, '0'}, + {0x67, '.'}, + {0x68, '7'}, + {0x69, '1'}, + {0x6A, '9'}, + {0x6B, '3'}, + }; + +codepage_t _CP_US_English = { + "US English", + US_normal, EVT_ARR_SIZE(US_normal), + US_caps, EVT_ARR_SIZE(US_caps), + US_shift, EVT_ARR_SIZE(US_shift), + US_shiftCaps, EVT_ARR_SIZE(US_shiftCaps), + US_ctrl, EVT_ARR_SIZE(US_ctrl), + US_numPad, EVT_ARR_SIZE(US_numPad), + }; diff --git a/board/MAI/bios_emulator/scitech/src/pm/common.c b/board/MAI/bios_emulator/scitech/src/pm/common.c new file mode 100644 index 000000000..d5a8e8f1c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common.c @@ -0,0 +1,480 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module containing code common to all platforms. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#if defined(__WIN32_VXD__) || defined(__OS2_VDD__) || defined(__NT_DRIVER__) +#include "sdd/sddhelp.h" +#else +#include +#include +#include +#endif + +/*---------------------------- Global variables ---------------------------*/ + +/* {secret} */ +long _VARAPI ___drv_os_type = _OS_UNSUPPORTED; +static char localBPDPath[PM_MAX_PATH] = ""; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +path - Local path to the Nucleus BPD driver files. + +REMARKS: +This function is used by the application program to override the location +of the Nucleus driver files that are loaded. Normally the loader code +will look in the system Nucleus directories first, then in the 'drivers' +directory relative to the current working directory, and finally relative +to the MGL_ROOT environment variable. By default the local BPD path is +always set to the current directory if not initialised. +****************************************************************************/ +void PMAPI PM_setLocalBPDPath( + const char *path) +{ + PM_init(); + strncpy(localBPDPath,path,sizeof(localBPDPath)); + localBPDPath[sizeof(localBPDPath)-1] = 0; +} + +/**************************************************************************** +PARAMETERS: +bpdpath - Place to store the actual path to the file +cachedpath - Place to store the cached BPD driver path +trypath - Path to try to find the BPD file in +subpath - Optional sub path to append to trypath +dllname - Name of the Binary Portable DLL to load + +RETURNS: +True if found, false if not. + +REMARKS: +Trys the specified path to see if the BPD file can be found or not. If so, +the path used is returned in bpdpath and cachedpath. +****************************************************************************/ +static ibool TryPath( + char *bpdpath, + char *cachedpath, + const char *trypath, + const char *subpath, + const char *dllname) +{ + char filename[256]; + FILE *f; + + strcpy(bpdpath, trypath); + PM_backslash(bpdpath); + strcat(bpdpath,subpath); + PM_backslash(bpdpath); + strcpy(filename,bpdpath); + strcat(filename,dllname); + if ((f = fopen(filename,"rb")) == NULL) + return false; + if (cachedpath) + strcpy(cachedpath,bpdpath); + fclose(f); + return true; +} + +/**************************************************************************** +RETURNS: +True if local override enabled, false if not. + +REMARKS: +Tests to see if the local override option is enabled, and if so it will +look for the Nucleus drivers in the local application directories in +preference to the Nucleus system directories. +****************************************************************************/ +static ibool GetLocalOverride(void) +{ + char filename[256]; + FILE *f; + static ibool local_override = -1; + + if (local_override == -1) { + local_override = false; + strcpy(filename,PM_getNucleusPath()); + PM_backslash(filename); + strcat(filename,"graphics.ini"); + if ((f = fopen(filename,"r")) != NULL) { + while (!feof(f) && fgets(filename,sizeof(filename),f)) { + if (strnicmp(filename,"uselocal",8) == 0) { + local_override = ((*(filename+9) - '0') == 1); + break; + } + } + fclose(f); + } + } + return local_override; +} + +/**************************************************************************** +DESCRIPTION: +Sets the location of the debug log file. + +HEADER: +pmapi.h + +PARAMETERS: +dllname - Name of the Binary Portable DLL to load +bpdpath - Place to store the actual path to the file + +RETURNS: +True if found, false if not. + +REMARKS: +Finds the location of a specific Binary Portable DLL, by searching all +the standard SciTech Nucleus driver locations. +****************************************************************************/ +ibool PMAPI PM_findBPD( + const char *dllname, + char *bpdpath) +{ + static char cachedpath[PM_MAX_PATH] = ""; + + /* On the first call determine the path to the Nucleus drivers */ + if (cachedpath[0] == 0) { + /* First try in the global system Nucleus driver path if + * the local override setting is not enabled. + */ + PM_init(); + if (!GetLocalOverride()) { + if (TryPath(bpdpath,cachedpath,PM_getNucleusPath(),"",dllname)) + return true; + } + + /* Next try in the local application directory if available */ + if (localBPDPath[0] != 0) { + if (TryPath(bpdpath,cachedpath,localBPDPath,"",dllname)) + return true; + } + else { +#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) + char *mgl_root; + if ((mgl_root = getenv("MGL_ROOT")) != NULL) { + if (TryPath(bpdpath,cachedpath,mgl_root,"drivers",dllname)) + return true; + } +#endif + PM_getCurrentPath(bpdpath,PM_MAX_PATH); + if (TryPath(bpdpath,cachedpath,bpdpath,"drivers",dllname)) + return true; + } + + /* Finally try in the global system path again so that we + * will still find the drivers in the global system path if + * the local override option is on, but the application does + * not have any local override drivers. + */ + if (TryPath(bpdpath,cachedpath,PM_getNucleusPath(),"",dllname)) + return true; + + /* Whoops, we can't find the BPD file! */ + return false; + } + + /* Always try in the previously discovered path */ + return TryPath(bpdpath,NULL,cachedpath,"",dllname); +} + +/**************************************************************************** +REMARKS: +Copies a string into another, and returns dest + strlen(src). +****************************************************************************/ +static char *_stpcpy( + char *_dest, + const char *_src) +{ + if (!_dest || !_src) + return 0; + while ((*_dest++ = *_src++) != 0) + ; + return --_dest; +} + +/**************************************************************************** +REMARKS: +Copies a string into another, stopping at the maximum length. The string +is properly terminated (unlike strncpy). +****************************************************************************/ +static void safe_strncpy( + char *dst, + const char *src, + unsigned maxlen) +{ + if (dst) { + if(strlen(src) >= maxlen) { + strncpy(dst, src, maxlen); + dst[maxlen] = 0; + } + else + strcpy(dst, src); + } +} + +/**************************************************************************** +REMARKS: +Determins if the dot separator is present in the string. +****************************************************************************/ +static int findDot( + char *p) +{ + if (*(p-1) == '.') + p--; + switch (*--p) { + case ':': + if (*(p-2) != '\0') + break; + case '/': + case '\\': + case '\0': + return true; + } + return false; +} + +/**************************************************************************** +DESCRIPTION: +Make a full pathname from split components. + +HEADER: +pmapi.h + +PARAMETERS: +path - Place to store full path +drive - Drive component for path +dir - Directory component for path +name - Filename component for path +ext - Extension component for path + +REMARKS: +Function to make a full pathname from split components. Under Unix the +drive component will usually be empty. If the drive, dir, name, or ext +parameters are null or empty, they are not inserted in the path string. +Otherwise, if the drive doesn't end with a colon, one is inserted in the +path. If the dir doesn't end in a slash, one is inserted in the path. +If the ext doesn't start with a dot, one is inserted in the path. + +The maximum sizes for the path string is given by the constant PM_MAX_PATH, +which includes space for the null-terminator. + +SEE ALSO: +PM_splitPath +****************************************************************************/ +void PMAPI PM_makepath( + char *path, + const char *drive, + const char *dir, + const char *name, + const char *ext) +{ + if (drive && *drive) { + *path++ = *drive; + *path++ = ':'; + } + if (dir && *dir) { + path = _stpcpy(path,dir); + if (*(path-1) != '\\' && *(path-1) != '/') +#ifdef __UNIX__ + *path++ = '/'; +#else + *path++ = '\\'; +#endif + } + if (name) + path = _stpcpy(path,name); + if (ext && *ext) { + if (*ext != '.') + *path++ = '.'; + path = _stpcpy(path,ext); + } + *path = 0; +} + +/**************************************************************************** +DESCRIPTION: +Split a full pathname into components. + +HEADER: +pmapi.h + +PARAMETERS: +path - Full path to split +drive - Drive component for path +dir - Directory component for path +name - Filename component for path +ext - Extension component for path + +RETURNS: +Flags indicating what components were parsed. + +REMARKS: +Function to split a full pathmame into separate components in the form + + X:\DIR\SUBDIR\NAME.EXT + +and splits path into its four components. It then stores those components +in the strings pointed to by drive, dir, name and ext. (Each component is +required but can be a NULL, which means the corresponding component will be +parsed but not stored). + +The maximum sizes for these strings are given by the constants PM_MAX_DRIVE +and PM_MAX_PATH. PM_MAX_DRIVE is always 4, and PM_MAX_PATH is usually at +least 256 characters. Under Unix the dir, name and ext components may be +up to the full path in length. + +SEE ALSO: +PM_makePath +****************************************************************************/ +int PMAPI PM_splitpath( + const char *path, + char *drive, + char *dir, + char *name, + char *ext) +{ + char *p; + int temp,ret; + char buf[PM_MAX_PATH+2]; + + /* Set all string to default value zero */ + ret = 0; + if (drive) *drive = 0; + if (dir) *dir = 0; + if (name) *name = 0; + if (ext) *ext = 0; + + /* Copy filename into template up to PM_MAX_PATH characters */ + p = buf; + if ((temp = strlen(path)) > PM_MAX_PATH) + temp = PM_MAX_PATH; + *p++ = 0; + strncpy(p, path, temp); + *(p += temp) = 0; + + /* Split the filename and fill corresponding nonzero pointers */ + temp = 0; + for (;;) { + switch (*--p) { + case '.': + if (!temp && (*(p+1) == '\0')) + temp = findDot(p); + if ((!temp) && ((ret & PM_HAS_EXTENSION) == 0)) { + ret |= PM_HAS_EXTENSION; + safe_strncpy(ext, p, PM_MAX_PATH - 1); + *p = 0; + } + continue; + case ':': + if (p != &buf[2]) + continue; + case '\0': + if (temp) { + if (*++p) + ret |= PM_HAS_DIRECTORY; + safe_strncpy(dir, p, PM_MAX_PATH - 1); + *p-- = 0; + break; + } + case '/': + case '\\': + if (!temp) { + temp++; + if (*++p) + ret |= PM_HAS_FILENAME; + safe_strncpy(name, p, PM_MAX_PATH - 1); + *p-- = 0; + if (*p == 0 || (*p == ':' && p == &buf[2])) + break; + } + continue; + case '*': + case '?': + if (!temp) + ret |= PM_HAS_WILDCARDS; + default: + continue; + } + break; + } + if (*p == ':') { + if (buf[1]) + ret |= PM_HAS_DRIVE; + safe_strncpy(drive, &buf[1], PM_MAX_DRIVE - 1); + } + return ret; +} + +/**************************************************************************** +DESCRIPTION: +Block until a specific time has elapsed since the last call + +HEADER: +pmapi.h + +PARAMETERS: +milliseconds - Number of milliseconds for delay + +REMARKS: +This function will block the calling thread or process until the specified +number of milliseconds have passed since the /last/ call to this function. +The first time this function is called, it will return immediately. On +subsquent calls it will block until the specified time has elapsed, or it +will return immediately if the time has already elapsed. + +This function is useful to provide constant time functionality in a +program, such as a frame rate limiter for graphics applications etc. + +SEE ALSO: +PM_sleep +****************************************************************************/ +void PMAPI PM_blockUntilTimeout( + ulong milliseconds) +{ + ulong microseconds = milliseconds * 1000L,msDelay; + static LZTimerObject tm; + static ibool firstTime = true; + + if (firstTime) { + firstTime = false; + LZTimerOnExt(&tm); + } + else { + if ((msDelay = (microseconds - LZTimerLapExt(&tm)) / 1000L) > 0) + PM_sleep(msDelay); + while (LZTimerLapExt(&tm) < microseconds) + ; + LZTimerOffExt(&tm); + LZTimerOnExt(&tm); + } +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm new file mode 100644 index 000000000..60ebed713 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_cpuinfo.asm @@ -0,0 +1,600 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NASM or TASM Assembler +;* Environment: Intel 32 bit Protected Mode. +;* +;* Description: Code to determine the Intel processor type. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" + +header _cpuinfo + +begdataseg _cpuinfo ; Start of data segment + +cache_id db "01234567890123456" +intel_id db "GenuineIntel" ; Intel vendor ID +cyrix_id db "CyrixInstead" ; Cyrix vendor ID +amd_id db "AuthenticAMD" ; AMD vendor ID +idt_id db "CentaurHauls" ; IDT vendor ID + +CPU_IDT EQU 01000h ; Flag for IDT processors +CPU_Cyrix EQU 02000h ; Flag for Cyrix processors +CPU_AMD EQU 04000h ; Flag for AMD processors +CPU_Intel EQU 08000h ; Flag for Intel processors + +enddataseg _cpuinfo + +begcodeseg _cpuinfo ; Start of code segment + +ifdef USE_NASM +%macro mCPU_ID 0 +db 00Fh,0A2h +%endmacro +else +MACRO mCPU_ID +db 00Fh,0A2h +ENDM +endif + +ifdef USE_NASM +%macro mRDTSC 0 +db 00Fh,031h +%endmacro +else +MACRO mRDTSC +db 00Fh,031h +ENDM +endif + +;---------------------------------------------------------------------------- +; bool _CPU_check80386(void) +;---------------------------------------------------------------------------- +; Determines if we have an i386 processor. +;---------------------------------------------------------------------------- +cprocstart _CPU_check80386 + + enter_c + + xor edx,edx ; EDX = 0, not an 80386 + mov bx, sp +ifdef USE_NASM + and sp, ~3 +else + and sp, not 3 +endif + pushfd ; Push original EFLAGS + pop eax ; Get original EFLAGS + mov ecx, eax ; Save original EFLAGS + xor eax, 40000h ; Flip AC bit in EFLAGS + push eax ; Save new EFLAGS value on + ; stack + popfd ; Replace current EFLAGS value + pushfd ; Get new EFLAGS + pop eax ; Store new EFLAGS in EAX + xor eax, ecx ; Can't toggle AC bit, + ; processor=80386 + jnz @@Done ; Jump if not an 80386 processor + inc edx ; We have an 80386 + +@@Done: push ecx + popfd + mov sp, bx + mov eax, edx + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; bool _CPU_check80486(void) +;---------------------------------------------------------------------------- +; Determines if we have an i486 processor. +;---------------------------------------------------------------------------- +cprocstart _CPU_check80486 + + enter_c + +; Distinguish between the i486 and Pentium by the ability to set the ID flag +; in the EFLAGS register. If the ID flag is set, then we can use the CPUID +; instruction to determine the final version of the chip. Otherwise we +; simply have an 80486. + +; Distinguish between the i486 and Pentium by the ability to set the ID flag +; in the EFLAGS register. If the ID flag is set, then we can use the CPUID +; instruction to determine the final version of the chip. Otherwise we +; simply have an 80486. + + pushfd ; Get original EFLAGS + pop eax + mov ecx, eax + xor eax, 200000h ; Flip ID bit in EFLAGS + push eax ; Save new EFLAGS value on stack + popfd ; Replace current EFLAGS value + pushfd ; Get new EFLAGS + pop eax ; Store new EFLAGS in EAX + xor eax, ecx ; Can not toggle ID bit, + jnz @@1 ; Processor=80486 + mov eax,1 ; We dont have a Pentium + jmp @@Done +@@1: mov eax,0 ; We have Pentium or later +@@Done: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; bool _CPU_checkClone(void) +;---------------------------------------------------------------------------- +; Checks if the i386 or i486 processor is a clone or genuine Intel. +;---------------------------------------------------------------------------- +cprocstart _CPU_checkClone + + enter_c + + mov ax,5555h ; Check to make sure this is a 32-bit processor + xor dx,dx + mov cx,2h + div cx ; Perform Division + clc + jnz @@NoClone + jmp @@Clone +@@NoClone: + stc +@@Clone: + pushfd + pop eax ; Get the flags + and eax,1 + xor eax,1 ; EAX=0 is probably Intel, EAX=1 is a Clone + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; bool _CPU_haveCPUID(void) +;---------------------------------------------------------------------------- +; Determines if we have support for the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_haveCPUID + + enter_c + +ifdef flatmodel + pushfd ; Get original EFLAGS + pop eax + mov ecx, eax + xor eax, 200000h ; Flip ID bit in EFLAGS + push eax ; Save new EFLAGS value on stack + popfd ; Replace current EFLAGS value + pushfd ; Get new EFLAGS + pop eax ; Store new EFLAGS in EAX + xor eax, ecx ; Can not toggle ID bit, + jnz @@1 ; Processor=80486 + mov eax,0 ; We dont have CPUID support + jmp @@Done +@@1: mov eax,1 ; We have CPUID support +else + mov eax,0 ; CPUID requires 32-bit pmode +endif +@@Done: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_checkCPUID(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_checkCPUID + + enter_c + + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax, 1 ; Make sure 1 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + xor eax,eax ; Assume vendor is unknown + +; Check for GenuineIntel processors + + LEA_L esi,intel_id + cmp [DWORD esi], ebx + jne @@NotIntel + cmp [DWORD esi+4], edx + jne @@NotIntel + cmp [DWORD esi+8], ecx + jne @@NotIntel + mov eax,CPU_Intel ; Flag that we have GenuineIntel + jmp @@FoundVendor + +; Check for CyrixInstead processors + +@@NotIntel: + LEA_L esi,cyrix_id + cmp [DWORD esi], ebx + jne @@NotCyrix + cmp [DWORD esi+4], edx + jne @@NotCyrix + cmp [DWORD esi+8], ecx + jne @@NotCyrix + mov eax,CPU_Cyrix ; Flag that we have CyrixInstead + jmp @@FoundVendor + +; Check for AuthenticAMD processors + +@@NotCyrix: + LEA_L esi,amd_id + cmp [DWORD esi], ebx + jne @@NotAMD + cmp [DWORD esi+4], edx + jne @@NotAMD + cmp [DWORD esi+8], ecx + jne @@NotAMD + mov eax,CPU_AMD ; Flag that we have AuthenticAMD + jmp @@FoundVendor + +; Check for CentaurHauls processors + +@@NotAMD: + LEA_L esi,idt_id + cmp [DWORD esi], ebx + jne @@NotIDT + cmp [DWORD esi+4], edx + jne @@NotIDT + cmp [DWORD esi+8], ecx + jne @@NotIDT + mov eax,CPU_IDT ; Flag that we have AuthenticIDT + jmp @@FoundVendor + +@@NotIDT: + +@@FoundVendor: + push eax + xor eax, eax + inc eax + mCPU_ID ; Get family/model/stepping/features + and eax, 0F00h + shr eax, 8 ; Isolate family + and eax, 0Fh + pop ecx + or eax,ecx ; Combine in the clone flag +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_getCPUIDModel(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_getCPUIDModel + + enter_c + + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax, 1 ; Make sure 1 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + xor eax, eax + inc eax + mCPU_ID ; Get family/model/stepping/features + and eax, 0F0h + shr eax, 4 ; Isolate model +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_getCPUIDStepping(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_getCPUIDStepping + + enter_c + + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax, 1 ; Make sure 1 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + xor eax, eax + inc eax + mCPU_ID ; Get family/model/stepping/features + and eax, 00Fh ; Isolate stepping +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_getCPUIDFeatures(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_getCPUIDFeatures + + enter_c + + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax, 1 ; Make sure 1 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + xor eax, eax + inc eax + mCPU_ID ; Get family/model/stepping/features + mov eax, edx +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_getCacheSize(void) +;---------------------------------------------------------------------------- +; Determines the CPU cache size for Intel processors +;---------------------------------------------------------------------------- +cprocstart _CPU_getCacheSize + + enter_c + xor eax, eax ; Set up for CPUID instruction + mCPU_ID ; Get and save vendor ID + cmp eax,2 ; Make sure 2 is valid input for CPUID + jl @@Fail ; We dont have the CPUID instruction + mov eax,2 + mCPU_ID ; Get cache descriptors + LEA_L esi,cache_id ; Get address of cache ID (-fPIC aware) + shr eax,8 + mov [esi+0],eax + mov [esi+3],ebx + mov [esi+7],ecx + mov [esi+11],edx + xor eax,eax + LEA_L esi,cache_id ; Get address of cache ID (-fPIC aware) + mov edi,15 +@@ScanLoop: + cmp [BYTE esi],41h + mov eax,128 + je @@Done + cmp [BYTE esi],42h + mov eax,256 + je @@Done + cmp [BYTE esi],43h + mov eax,512 + je @@Done + cmp [BYTE esi],44h + mov eax,1024 + je @@Done + cmp [BYTE esi],45h + mov eax,2048 + je @@Done + inc esi + dec edi + jnz @@ScanLoop + +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; uint _CPU_have3DNow(void) +;---------------------------------------------------------------------------- +; Determines the CPU type using the CPUID instruction. +;---------------------------------------------------------------------------- +cprocstart _CPU_have3DNow + + enter_c + + mov eax,80000000h ; Query for extended functions + mCPU_ID ; Get extended function limit + cmp eax,80000001h + jbe @@Fail ; Nope, we dont have function 800000001h + mov eax,80000001h ; Setup extended function 800000001h + mCPU_ID ; and get the information + test edx,80000000h ; Bit 31 is set if 3DNow! present + jz @@Fail ; Nope, we dont have 3DNow support + mov eax,1 ; Yep, we have 3DNow! support! +@@Done: leave_c + ret + +@@Fail: xor eax,eax + jmp @@Done + +cprocend + +;---------------------------------------------------------------------------- +; ulong _CPU_quickRDTSC(void) +;---------------------------------------------------------------------------- +; Reads the time stamp counter and returns the low order 32-bits +;---------------------------------------------------------------------------- +cprocstart _CPU_quickRDTSC + + mRDTSC + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _CPU_runBSFLoop(ulong interations) +;---------------------------------------------------------------------------- +; Runs a loop of BSF instructions for the specified number of iterations +;---------------------------------------------------------------------------- +cprocstart _CPU_runBSFLoop + + ARG iterations:ULONG + + push _bp + mov _bp,_sp + push _bx + + mov edx,[iterations] + mov eax,80000000h + mov ebx,edx + + ALIGN 4 + +@@loop: bsf ecx,eax + dec ebx + jnz @@loop + + pop _bx + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _CPU_readTimeStamp(CPU_largeInteger *time); +;---------------------------------------------------------------------------- +; Reads the time stamp counter and returns the 64-bit result. +;---------------------------------------------------------------------------- +cprocstart _CPU_readTimeStamp + + mRDTSC + mov ecx,[esp+4] ; Access directly without stack frame + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _CPU_diffTime64(CPU_largeInteger *t1,CPU_largeInteger *t2,CPU_largeInteger *t) +;---------------------------------------------------------------------------- +; Computes the difference between two 64-bit numbers. +;---------------------------------------------------------------------------- +cprocstart _CPU_diffTime64 + + ARG t1:DPTR, t2:DPTR, t:DPTR + + enter_c + + mov ecx,[t2] + mov eax,[ecx] ; EAX := t2.low + mov ecx,[t1] + sub eax,[ecx] + mov edx,eax ; EDX := low difference + mov ecx,[t2] + mov eax,[ecx+4] ; ECX := t2.high + mov ecx,[t1] + sbb eax,[ecx+4] ; EAX := high difference + + mov ebx,[t] ; Store the result + mov [ebx],edx ; Store low part + mov [ebx+4],eax ; Store high part + mov eax,edx ; Return low part +ifndef flatmodel + shld edx,eax,16 ; Return in DX:AX +endif + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _CPU_calcMicroSec(CPU_largeInteger *count,ulong freq); +;---------------------------------------------------------------------------- +; Computes the value in microseconds for the elapsed time with maximum +; precision. The formula we use is: +; +; us = (((diff * 0x100000) / freq) * 1000000) / 0x100000) +; +; The power of two multiple before the first divide allows us to scale the +; 64-bit difference using simple shifts, and then the divide brings the +; final result into the range to fit into a 32-bit integer. +;---------------------------------------------------------------------------- +cprocstart _CPU_calcMicroSec + + ARG count:DPTR, freq:ULONG + + enter_c + + mov ecx,[count] + mov eax,[ecx] ; EAX := low part + mov edx,[ecx+4] ; EDX := high part + shld edx,eax,20 + shl eax,20 ; diff * 0x100000 + div [DWORD freq] ; (diff * 0x100000) / freq + mov ecx,1000000 + xor edx,edx + mul ecx ; ((diff * 0x100000) / freq) * 1000000) + shrd eax,edx,20 ; ((diff * 0x100000) / freq) * 1000000) / 0x100000 +ifndef flatmodel + shld edx,eax,16 ; Return in DX:AX +endif + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _CPU_mulDiv(ulong a,ulong b,ulong c); +;---------------------------------------------------------------------------- +; Computes the following with 64-bit integer precision: +; +; result = (a * b) / c +; +;---------------------------------------------------------------------------- +cprocstart _CPU_mulDiv + + ARG a:ULONG, b:ULONG, c:ULONG + + enter_c + mov eax,[a] + imul [ULONG b] + idiv [ULONG c] +ifndef flatmodel + shld edx,eax,16 ; Return in DX:AX +endif + leave_c + ret + +cprocend + +endcodeseg _cpuinfo + + END diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm new file mode 100644 index 000000000..2b6e1e8b5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_dma.asm @@ -0,0 +1,246 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 16/32 bit Ring 0 device driver +;* +;* Description: Assembler support routines for ISA DMA controller. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _dma ; Set up memory model + +begdataseg _dma ; Start of data segment + +cpublic _PM_DMADataStart + +; DMA register I/O addresses for channels 0-7 (except 4) + +DMAC_page db 087h,083h,081h,082h, -1,08Bh,089h,08Ah +DMAC_addr db 000h,002h,004h,006h, -1,0C4h,0C8h,0CCh +DMAC_cnt db 001h,003h,005h,007h, -1,0C6h,0CAh,0CEh +DMAC_mask db 00Ah,00Ah,00Ah,00Ah, -1,0D4h,0D4h,0D4h +DMAC_mode db 00Bh,00Bh,00Bh,00Bh, -1,0D6h,0D6h,0D6h +DMAC_FF db 00Ch,00Ch,00Ch,00Ch, -1,0D8h,0D8h,0D8h + +cpublic _PM_DMADataEnd + +enddataseg _dma + +begcodeseg _dma ; Start of code segment + +ifdef flatmodel + +cpublic _PM_DMACodeStart + +;---------------------------------------------------------------------------- +; void PM_DMACDisable(int channel); +;---------------------------------------------------------------------------- +; Masks DMA channel, inhibiting DMA transfers +;---------------------------------------------------------------------------- +cprocstart PM_DMACDisable + + ARG channel:UINT + + push ebp + mov ebp,esp + mov ecx,[channel] ; ECX indexes DMAC register tables + mov dh,0 ; DH = 0 for DMAC register port access + mov al,cl + and al,11b + or al,100b ; AL = (channel & 3) | "set mask bit" + mov dl,[DMAC_mask+ecx] + out dx,al + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_DMACEnable(int channel); +;---------------------------------------------------------------------------- +; Unmasks DMA channel, enabling DMA transfers +;---------------------------------------------------------------------------- +cprocstart PM_DMACEnable + + ARG channel:UINT + + push ebp + mov ebp,esp + mov ecx,[channel] ; ECX indexes DMAC register tables + mov dh,0 ; DH = 0 for DMAC register port access + mov al,cl + and al,11b ; AL = (channel & 3), "set mask bit"=0 + mov dl,[DMAC_mask+ecx] + out dx,al + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_DMACProgram(int channel,int mode,ulong bufferPhys,int count); +;---------------------------------------------------------------------------- +; Purpose: Program DMA controller to perform transfer from first 16MB +; based on previously selected mode and channel. DMA transfer may be enabled +; by subsequent call to PM_DMACEnable. +; +; Entry: channel - DMA channel in use (0-7) +; mode - Selected DMAMODE type for transfer +; buffer - 32-bit physical address of DMA buffer +; count - DMA byte count (1-65536 bytes) +;---------------------------------------------------------------------------- +cprocstart PM_DMACProgram + + ARG channel:UINT, mode:UINT, bufferPhys:ULONG, count:UINT + + enter_c + pushfd + cli ; Disable interrupts + +; Mask DMA channel to disable it + + mov ebx,[channel] ; EBX indexes DMAC register tables + mov dh,0 ; DH = 0 for DMAC register port access + mov al,bl + and al,11b + or al,100b ; AL = (channel & 3) | "set mask bit" + mov dl,[DMAC_mask+ebx] + out dx,al + +; Generate IOW to clear FF toggle state + + mov al,0 + mov dl,[DMAC_FF+ebx] + out dx,al + +; Compute buffer address to program + + mov eax,[bufferPhys] ; AX := DMA address offset + mov ecx,eax + shr ecx,16 ; CL := bufferPhys >> 16 (DMA page) + mov esi,[count] ; ESI = # of bytes to transfer + cmp ebx,4 ; 16-bit channel? + jb @@WriteDMAC ; No, program DMAC + shr eax,1 ; Yes, convert address and count + shr esi,1 ; to 16-bit, 128K/page format + +; Set the DMA address word (bits 0-15) + +@@WriteDMAC: + mov dl,[DMAC_addr+ebx] + out dx,al + mov al,ah + out dx,al + +; Set DMA transfer count + + mov eax,esi + dec eax ; ESI = # of bytes to transfer - 1 + mov dl,[DMAC_cnt+ebx] + out dx,al + mov al,ah + out dx,al + +; Set DMA page byte (bits 16-23) + + mov al,cl + mov dl,[DMAC_page+ebx] + out dx,al + +; Set the DMA channel mode + + mov al,bl + and al,11b + or al,[BYTE mode] ; EAX = (channel & 3) | mode + mov dl,[DMAC_mode+ebx] + out dx,al + + pop eax ; SMP safe interrupt state restore! + test eax,200h + jz @@1 + sti +@@1: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong PMAPI PM_DMACPosition(int channel); +;---------------------------------------------------------------------------- +; Returns the current position in a dma transfer. Interrupts should be +; disabled before calling this function. +;---------------------------------------------------------------------------- +cprocstart PM_DMACPosition + + ARG channel:UINT + + enter_c + mov ecx,[channel] ; ECX indexes DMAC register tables + mov dh,0 ; DH = 0 for DMAC register port access + +; Generate IOW to clear FF toggle state + + mov al,0 + mov dl,[DMAC_FF+ebx] + out dx,al + xor eax,eax + xor ecx,ecx + +; Now read the current position for the channel + +@@ReadLoop: + mov dl,[DMAC_cnt+ebx] + out dx,al + in al,dx + mov cl,al + in al,dx + mov ch,al ; ECX := first count read + in al,dx + mov ah,al + in al,dx + xchg al,ah ; EAX := second count read + sub ecx,eax + cmp ecx,40h + jg @@ReadLoop + cmp ebx,4 ; 16-bit channel? + jb @@Exit ; No, we are done + shl eax,1 ; Yes, adjust to byte address + +@@Exit: leave_c + ret + +cprocend + + +cpublic _PM_DMACodeEnd + +endif + +endcodeseg _dma + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm new file mode 100644 index 000000000..fdec1b58d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_int64.asm @@ -0,0 +1,309 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NASM or TASM Assembler +;* Environment: Intel 32 bit Protected Mode. +;* +;* Description: Code for 64-bit arhithmetic +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" + +header _int64 + +begcodeseg _int64 ; Start of code segment + +a_low EQU 04h ; Access a_low directly on stack +a_high EQU 08h ; Access a_high directly on stack +b_low EQU 0Ch ; Access b_low directly on stack +shift EQU 0Ch ; Access shift directly on stack +result_2 EQU 0Ch ; Access result directly on stack +b_high EQU 10h ; Access b_high directly on stack +result_3 EQU 10h ; Access result directly on stack +result_4 EQU 14h ; Access result directly on stack + +;---------------------------------------------------------------------------- +; void _PM_add64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result); +;---------------------------------------------------------------------------- +; Adds two 64-bit numbers. +;---------------------------------------------------------------------------- +cprocstart _PM_add64 + + mov eax,[esp+a_low] + add eax,[esp+b_low] + mov edx,[esp+a_high] + adc edx,[esp+b_high] + mov ecx,[esp+result_4] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_sub64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result); +;---------------------------------------------------------------------------- +; Subtracts two 64-bit numbers. +;---------------------------------------------------------------------------- +cprocstart _PM_sub64 + + mov eax,[esp+a_low] + sub eax,[esp+b_low] + mov edx,[esp+a_high] + sbb edx,[esp+b_high] + mov ecx,[esp+result_4] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_mul64(u32 a_high,u32 a_low,u32 b_high,u32 b_low,__u64 *result); +;---------------------------------------------------------------------------- +; Multiples two 64-bit numbers. +;---------------------------------------------------------------------------- +cprocstart _PM_mul64 + + mov eax,[esp+a_high] + mov ecx,[esp+b_high] + or ecx,eax + mov ecx,[esp+b_low] + jnz @@FullMultiply + mov eax,[esp+a_low] ; EDX:EAX = b.low * a.low + mul ecx + mov ecx,[esp+result_4] + mov [ecx],eax + mov [ecx+4],edx + ret + +@@FullMultiply: + push ebx + mul ecx ; EDX:EAX = a.high * b.low + mov ebx,eax + mov eax,[esp+a_low+4] + mul [DWORD esp+b_high+4] ; EDX:EAX = b.high * a.low + add ebx,eax + mov eax,[esp+a_low+4] + mul ecx ; EDX:EAX = a.low * b.low + add edx,ebx + pop ebx + mov ecx,[esp+result_4] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_div64(u32 a_low,u32 a_high,u32 b_low,u32 b_high,__u64 *result); +;---------------------------------------------------------------------------- +; Divides two 64-bit numbers. +;---------------------------------------------------------------------------- +cprocstart _PM_div64 + + push edi + push esi + push ebx + xor edi,edi + mov eax,[esp+a_high+0Ch] + or eax,eax + jns @@ANotNeg + +; Dividend is negative, so negate it and save result for later + + inc edi + mov edx,[esp+a_low+0Ch] + neg eax + neg edx + sbb eax,0 + mov [esp+a_high+0Ch],eax + mov [esp+a_low+0Ch],edx + +@@ANotNeg: + mov eax,[esp+b_high+0Ch] + or eax,eax + jns @@BNotNeg + +; Divisor is negative, so negate it and save result for later + + inc edi + mov edx,[esp+b_low+0Ch] + neg eax + neg edx + sbb eax,0 + mov [esp+b_high+0Ch],eax + mov [esp+b_low+0Ch],edx + +@@BNotNeg: + or eax,eax + jnz @@BHighNotZero + +; b.high is zero, so handle this faster + + mov ecx,[esp+b_low+0Ch] + mov eax,[esp+a_high+0Ch] + xor edx,edx + div ecx + mov ebx,eax + mov eax,[esp+a_low+0Ch] + div ecx + mov edx,ebx + jmp @@BHighZero + +@@BHighNotZero: + mov ebx,eax + mov ecx,[esp+b_low+0Ch] + mov edx,[esp+a_high+0Ch] + mov eax,[esp+a_low+0Ch] + +; Shift values right until b.high becomes zero + +@@ShiftLoop: + shr ebx,1 + rcr ecx,1 + shr edx,1 + rcr eax,1 + or ebx,ebx + jnz @@ShiftLoop + +; Now complete the divide process + + div ecx + mov esi,eax + mul [DWORD esp+b_high+0Ch] + mov ecx,eax + mov eax,[esp+b_low+0Ch] + mul esi + add edx,ecx + jb @@8 + cmp edx,[esp+a_high+0Ch] + ja @@8 + jb @@9 + cmp eax,[esp+a_low+0Ch] + jbe @@9 +@@8: dec esi +@@9: xor edx,edx + mov eax,esi + +@@BHighZero: + dec edi + jnz @@Done + +; The result needs to be negated as either a or b was negative + + neg edx + neg eax + sbb edx,0 + +@@Done: pop ebx + pop esi + pop edi + mov ecx,[esp+result_4] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; __i64 _PM_shr64(u32 a_low,s32 a_high,s32 shift,__u64 *result); +;---------------------------------------------------------------------------- +; Shift a 64-bit number right +;---------------------------------------------------------------------------- +cprocstart _PM_shr64 + + mov eax,[esp+a_low] + mov edx,[esp+a_high] + mov cl,[esp+shift] + shrd edx,eax,cl + mov ecx,[esp+result_3] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; __i64 _PM_sar64(u32 a_low,s32 a_high,s32 shift,__u64 *result); +;---------------------------------------------------------------------------- +; Shift a 64-bit number right (signed) +;---------------------------------------------------------------------------- +cprocstart _PM_sar64 + + mov eax,[esp+a_low] + mov edx,[esp+a_high] + mov cl,[esp+shift] + sar edx,cl + rcr eax,cl + mov ecx,[esp+result_3] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; __i64 _PM_shl64(u32 a_low,s32 a_high,s32 shift,__u64 *result); +;---------------------------------------------------------------------------- +; Shift a 64-bit number left +;---------------------------------------------------------------------------- +cprocstart _PM_shl64 + + mov eax,[esp+a_low] + mov edx,[esp+a_high] + mov cl,[esp+shift] + shld edx,eax,cl + mov ecx,[esp+result_3] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; __i64 _PM_neg64(u32 a_low,s32 a_high,__u64 *result); +;---------------------------------------------------------------------------- +; Shift a 64-bit number left +;---------------------------------------------------------------------------- +cprocstart _PM_neg64 + + mov eax,[esp+a_low] + mov edx,[esp+a_high] + neg eax + neg edx + sbb eax,0 + mov ecx,[esp+result_2] + mov [ecx],eax + mov [ecx+4],edx + ret + +cprocend + + +endcodeseg _int64 + + END diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm new file mode 100644 index 000000000..0ff1ecf55 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_joy.asm @@ -0,0 +1,230 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler +;* Environment: Intel x86, any OS +;* +;* Description: Assembly language support routines for reading analogue +;* joysticks. +;* +;**************************************************************************** + + ideal + +include "scitech.mac" ; Memory model macros + +ifdef flatmodel + +header _joy ; Set up memory model + +begcodeseg _joy ; Start of code segment + +;---------------------------------------------------------------------------- +; initTimer +;---------------------------------------------------------------------------- +; Sets up 8253 timer 2 (PC speaker) to start timing, but not produce output. +;---------------------------------------------------------------------------- +cprocstatic initTimer + +; Start timer 2 counting + + in al,61h + and al,0FDh ; Disable speaker output (just in case) + or al,1 + out 61h,al + +; Set the timer 2 count to 0 again to start the timing interval. + + mov al,10110100b ; set up to load initial (timer 2) + out 43h,al ; timer count + sub al,al + out 42h,al ; load count lsb + out 42h,al ; load count msb + ret + +cprocend + +;---------------------------------------------------------------------------- +; readTimer2 +;---------------------------------------------------------------------------- +; Reads the number of ticks from the 8253 timer chip using channel 2 (PC +; speaker). This is non-destructive and does not screw up other libraries. +;---------------------------------------------------------------------------- +cprocstatic readTimer + + xor al,al ; Latch timer 0 command + out 43h,al ; Latch timer + in al,42h ; least significant byte + mov ah,al + in al,42h ; most significant byte + xchg ah,al + and eax,0FFFFh + ret + +cprocend + +;---------------------------------------------------------------------------- +; exitTimer +;---------------------------------------------------------------------------- +; Stops the 8253 timer 2 (PC speaker) counting +;---------------------------------------------------------------------------- +cprocstatic exitTimer + +; Stop timer 2 from counting + + push eax + in al,61h + and al,0FEh + out 61h,al + +; Some programs have a problem if we change the control port; better change it +; to something they expect (mode 3 - square wave generator)... + mov al,0B6h + out 43h,al + + pop eax + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _EVT_readJoyAxis(int jmask,int *axis); +;---------------------------------------------------------------------------- +; Function to poll the joystick to read the current axis positions. +;---------------------------------------------------------------------------- +cprocstart _EVT_readJoyAxis + + ARG jmask:UINT, axis:DPTR + + LOCAL firstTick:UINT, lastTick:UINT, totalTicks:UINT = LocalSize + + enter_c + + mov ebx,[jmask] + mov edi,[axis] + mov ecx,(1193180/100) + and ebx,01111b ; Mask out supported axes + mov dx,201h ; DX := joystick I/O port + call initTimer ; Start timer 2 counting + call readTimer ; Returns counter in EAX + mov [lastTick],eax + +@@WaitStable: + in al,dx + and al,bl ; Wait for the axes in question to be + jz @@Stable ; done reading... + call readTimer ; Returns counter in EAX + xchg eax,[lastTick] + cmp eax,[lastTick] + jb @@1 + sub eax,[lastTick] +@@1: add [totalTicks],eax + cmp [totalTicks],ecx ; Check for timeout + jae @@Stable + jmp @@WaitStable + +@@Stable: + mov al,0FFh + out dx,al ; Start joystick reading + call initTimer ; Start timer 2 counting + call readTimer ; Returns counter in EAX + mov [firstTick],eax ; Store initial count + mov [lastTick],eax + mov [DWORD totalTicks],0 + cli + +@@PollLoop: + in al,dx ; Read Joystick port + not al + and al,bl ; Mask off channels we don't want to read + jnz @@AxisFlipped ; See if any of the channels flipped + call readTimer ; Returns counter in EAX + xchg eax,[lastTick] + cmp eax,[lastTick] + jb @@2 + sub eax,[lastTick] +@@2: add [totalTicks],eax + cmp [totalTicks],ecx ; Check for timeout + jae @@TimedOut + jmp @@PollLoop + +@@AxisFlipped: + xor esi,esi + mov ah,1 + test al,ah + jnz @@StoreCount ; Joystick 1, X axis flipped + add esi,4 + mov ah,2 + test al,ah + jnz @@StoreCount ; Joystick 1, Y axis flipped + add esi,4 + mov ah,4 + test al,ah + jnz @@StoreCount ; Joystick 2, X axis flipped + add esi,4 ; Joystick 2, Y axis flipped + mov ah,8 + +@@StoreCount: + or bh,ah ; Indicate this axis is active + xor bl,ah ; Unmark the channels that just tripped + call readTimer ; Returns counter in EAX + xchg eax,[lastTick] + cmp eax,[lastTick] + jb @@3 + sub eax,[lastTick] +@@3: add [totalTicks],eax + mov eax,[totalTicks] + mov [edi+esi],eax ; Record the time this channel flipped + cmp bl,0 ; If there are more channels to read, + jne @@PollLoop ; keep looping + +@@TimedOut: + sti + call exitTimer ; Stop timer 2 counting + movzx eax,bh ; Return the mask of working axes + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _EVT_readJoyButtons(void); +;---------------------------------------------------------------------------- +; Function to poll the current joystick buttons +;---------------------------------------------------------------------------- +cprocstart _EVT_readJoyButtons + + mov dx,0201h + in al,dx + shr al,4 + not al + and eax,0Fh + ret + +cprocend + +endcodeseg _joy + +endif + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm new file mode 100644 index 000000000..1e0a6966c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_mtrr.asm @@ -0,0 +1,272 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 16/32 bit Ring 0 device driver +;* +;* Description: Assembler support routines for the Memory Type Range Register +;* (MTRR) module. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _mtrr ; Set up memory model + +begdataseg _mtrr + +ifdef DOS4GW + cextern _PM_haveCauseWay,UINT +endif + +enddataseg _mtrr + +begcodeseg _mtrr ; Start of code segment + +P586 + +;---------------------------------------------------------------------------- +; ibool _MTRR_isRing0(void); +;---------------------------------------------------------------------------- +; Checks to see if we are running at ring 0. This check is only relevant +; for 32-bit DOS4GW and compatible programs. If we are not running under +; DOS4GW, then we simply assume we are a ring 0 device driver. +;---------------------------------------------------------------------------- +cprocnear _MTRR_isRing0 + +; Are we running under CauseWay? + +ifdef DOS4GW + enter_c + mov ax,cs + and eax,3 + xor eax,3 + jnz @@Exit + +; CauseWay runs the apps at ring 3, but implements support for specific +; ring 0 instructions that we need to get stuff done under real DOS. + + mov eax,1 + cmp [UINT _PM_haveCauseWay],0 + jnz @@Exit +@@Fail: xor eax,eax +@@Exit: leave_c + ret +else +ifdef __SMX32__ + mov eax,1 ; SMX is ring 0! + ret +else +ifdef __VXD__ + mov eax,1 ; VxD is ring 0! + ret +else +ifdef __NT_DRIVER__ + mov eax,1 ; NT/W2K is ring 0! + ret +else +else + xor eax,eax ; Assume ring 3 for 32-bit DOS + ret +endif +endif +endif +endif + +cprocend + +;---------------------------------------------------------------------------- +; ulong _MTRR_disableInt(void); +;---------------------------------------------------------------------------- +; Return processor interrupt status and disable interrupts. +;---------------------------------------------------------------------------- +cprocstart _MTRR_disableInt + + pushfd ; Put flag word on stack + cli ; Disable interrupts! + pop eax ; deposit flag word in return register + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_restoreInt(ulong ps); +;---------------------------------------------------------------------------- +; Restore processor interrupt status. +;---------------------------------------------------------------------------- +cprocstart _MTRR_restoreInt + + ARG ps:ULONG + + push ebp + mov ebp,esp ; Set up stack frame + mov ecx,[ps] + test ecx,200h ; SMP safe interrupt flag restore! + jz @@1 + sti +@@1: pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _MTRR_saveCR4(void); +;---------------------------------------------------------------------------- +; Save the value of CR4 and clear the Page Global Enable (bit 7). We also +; disable and flush the caches. +;---------------------------------------------------------------------------- +cprocstart _MTRR_saveCR4 + + enter_c + +; Save value of CR4 and clear Page Global Enable (bit 7) + + mov ebx,cr4 + mov eax,ebx + and al,7Fh + mov cr4,eax + +; Disable and flush caches + + mov eax,cr0 + or eax,40000000h + wbinvd + mov cr0,eax + wbinvd + +; Return value from CR4 + + mov eax,ebx + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_restoreCR4(ulong cr4Val) +;---------------------------------------------------------------------------- +; Save the value of CR4 and clear the Page Global Enable (bit 7). We also +; disable and flush the caches. +;---------------------------------------------------------------------------- +cprocstart _MTRR_restoreCR4 + + ARG cr4Val:ULONG + + enter_c + +; Enable caches + + mov eax,cr0 + and eax,0BFFFFFFFh + mov cr0,eax + mov eax,[cr4Val] + mov cr4,eax + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_getCx86(uchar reg); +;---------------------------------------------------------------------------- +; Read a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_getCx86 + + ARG reg:UCHAR + + enter_c + mov al,[reg] + out 22h,al + in al,23h + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_setCx86(uchar reg,uchar val); +;---------------------------------------------------------------------------- +; Write a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_setCx86 + + ARG reg:UCHAR, val:UCHAR + + enter_c + mov al,[reg] + out 22h,al + mov al,[val] + out 23h,al + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_readMSR(uong reg, ulong FAR *eax, ulong FAR *edx); +;---------------------------------------------------------------------------- +; Writes the specific Machine Status Register used on the newer Intel +; Pentium Pro and Pentium II motherboards. +;---------------------------------------------------------------------------- +cprocnear _MTRR_readMSR + + ARG reg:ULONG, v_eax:DPTR, v_edx:DPTR + + enter_c + mov ecx,[reg] + rdmsr + mov ebx,[v_eax] + mov [ebx],eax + mov ebx,[v_edx] + mov [ebx],edx + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_writeMSR(uong reg, ulong eax, ulong edx); +;---------------------------------------------------------------------------- +; Writes the specific Machine Status Register used on the newer Intel +; Pentium Pro and Pentium II motherboards. +;---------------------------------------------------------------------------- +cprocnear _MTRR_writeMSR + + ARG reg:ULONG, v_eax:ULONG, v_edx:ULONG + + enter_c + mov ecx,[reg] + mov eax,[v_eax] + mov edx,[v_edx] + wrmsr + leave_c + ret + +cprocend + +endcodeseg _mtrr + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm b/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm new file mode 100644 index 000000000..5b8dbcc73 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/_pcihelp.asm @@ -0,0 +1,358 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: Any +;* +;* Description: Helper assembler functions for PCI access module. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pcilib + +begcodeseg _pcilib + +ifdef flatmodel + +;---------------------------------------------------------------------------- +; uchar _ASMAPI _BIOS32_service( +; ulong service, +; ulong func, +; ulong *physBase, +; ulong *length, +; ulong *serviceOffset, +; PCIBIOS_entry entry); +;---------------------------------------------------------------------------- +; Call the BIOS32 services directory +;---------------------------------------------------------------------------- +cprocstart _BIOS32_service + + ARG service:ULONG, func:ULONG, physBase:DPTR, len:DPTR, off:DPTR, entry:QWORD + + enter_c + mov eax,[service] + mov ebx,[func] +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif + mov esi,[physBase] + mov [esi],ebx + mov esi,[len] + mov [esi],ecx + mov esi,[off] + mov [esi],edx + leave_c + ret + +cprocend + +endif + +;---------------------------------------------------------------------------- +; ushort _ASMAPI _PCIBIOS_isPresent(ulong i_eax,ulong *o_edx,ushort *oeax, +; uchar *o_cl,PCIBIOS_entry entry) +;---------------------------------------------------------------------------- +; Call the PCI BIOS to determine if it is present. +;---------------------------------------------------------------------------- +cprocstart _PCIBIOS_isPresent + + ARG i_eax:ULONG, o_edx:DPTR, oeax:DPTR, o_cl:DPTR, entry:QWORD + + enter_c + mov eax,[i_eax] +ifdef flatmodel +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif +else + int 1Ah +endif + _les _si,[o_edx] + mov [_ES _si],edx + _les _si,[oeax] + mov [_ES _si],ax + _les _si,[o_cl] + mov [_ES _si],cl + mov ax,bx + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _PCIBIOS_service(ulong r_eax,ulong r_ebx,ulong r_edi,ulong r_ecx, +; PCIBIOS_entry entry) +;---------------------------------------------------------------------------- +; Call the PCI BIOS services, either via the 32-bit protected mode entry +; point or via the Int 1Ah 16-bit interrupt. +;---------------------------------------------------------------------------- +cprocstart _PCIBIOS_service + + ARG r_eax:ULONG, r_ebx:ULONG, r_edi:ULONG, r_ecx:ULONG, entry:QWORD + + enter_c + mov eax,[r_eax] + mov ebx,[r_ebx] + mov edi,[r_edi] + mov ecx,[r_ecx] +ifdef flatmodel +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif +else + int 1Ah +endif + mov eax,ecx +ifndef flatmodel + shld edx,eax,16 ; Return result in DX:AX +endif + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _PCIBIOS_getRouting(PCIRoutingOptionsBuffer *buf,PCIBIOS_entry entry); +;---------------------------------------------------------------------------- +; Get the routing options for PCI devices +;---------------------------------------------------------------------------- +cprocstart _PCIBIOS_getRouting + + ARG buf:DPTR, entry:QWORD + + enter_c + mov eax,0B10Eh + mov bx,0 + _les _di,[buf] +ifdef flatmodel +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif +else + int 1Ah +endif + movzx eax,ah + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ibool _PCIBIOS_setIRQ(int busDev,int intPin,int IRQ,PCIBIOS_entry entry); +;---------------------------------------------------------------------------- +; Change the IRQ routing for the PCI device +;---------------------------------------------------------------------------- +cprocstart _PCIBIOS_setIRQ + + ARG busDev:UINT, intPin:UINT, IRQ:UINT, entry:QWORD + + enter_c + mov eax,0B10Fh + mov bx,[USHORT busDev] + mov cl,[BYTE intPin] + mov ch,[BYTE IRQ] +ifdef flatmodel +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif +else + int 1Ah +endif + mov eax,1 + jnc @@1 + xor eax,eax ; Function failed! +@@1: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _PCIBIOS_specialCycle(int bus,ulong data,PCIBIOS_entry entry); +;---------------------------------------------------------------------------- +; Generate a special cycle via the PCI BIOS. +;---------------------------------------------------------------------------- +cprocstart _PCIBIOS_specialCycle + + ARG bus:UINT, data:ULONG, entry:QWORD + + enter_c + mov eax,0B106h + mov bh,[BYTE bus] + mov ecx,[data] +ifdef flatmodel +ifdef USE_NASM + call far dword [entry] +else + call [FWORD entry] +endif +else + int 1Ah +endif + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ushort _PCI_getCS(void) +;---------------------------------------------------------------------------- +cprocstart _PCI_getCS + + mov ax,cs + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_inpb(int port) +;---------------------------------------------------------------------------- +; Reads a byte from the specified port +;---------------------------------------------------------------------------- +cprocstart PM_inpb + + ARG port:UINT + + push _bp + mov _bp,_sp + xor _ax,_ax + mov _dx,[port] + in al,dx + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_inpw(int port) +;---------------------------------------------------------------------------- +; Reads a word from the specified port +;---------------------------------------------------------------------------- +cprocstart PM_inpw + + ARG port:UINT + + push _bp + mov _bp,_sp + xor _ax,_ax + mov _dx,[port] + in ax,dx + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong PM_inpd(int port) +;---------------------------------------------------------------------------- +; Reads a word from the specified port +;---------------------------------------------------------------------------- +cprocstart PM_inpd + + ARG port:UINT + + push _bp + mov _bp,_sp + mov _dx,[port] + in eax,dx +ifndef flatmodel + shld edx,eax,16 ; DX:AX = result +endif + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_outpb(int port,int value) +;---------------------------------------------------------------------------- +; Write a byte to the specified port. +;---------------------------------------------------------------------------- +cprocstart PM_outpb + + ARG port:UINT, value:UINT + + push _bp + mov _bp,_sp + mov _dx,[port] + mov _ax,[value] + out dx,al + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_outpw(int port,int value) +;---------------------------------------------------------------------------- +; Write a word to the specified port. +;---------------------------------------------------------------------------- +cprocstart PM_outpw + + ARG port:UINT, value:UINT + + push _bp + mov _bp,_sp + mov _dx,[port] + mov _ax,[value] + out dx,ax + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_outpd(int port,ulong value) +;---------------------------------------------------------------------------- +; Write a word to the specified port. +;---------------------------------------------------------------------------- +cprocstart PM_outpd + + ARG port:UINT, value:ULONG + + push _bp + mov _bp,_sp + mov _dx,[port] + mov eax,[value] + out dx,eax + pop _bp + ret + +cprocend + +endcodeseg _pcilib + + END diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/agp.c b/board/MAI/bios_emulator/scitech/src/pm/common/agp.c new file mode 100644 index 000000000..d53bc88e1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/agp.c @@ -0,0 +1,189 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Ring 0 device driver +* +* Description: Generic module to implement AGP support functions using the +* SciTech Nucleus AGP support drivers. If the OS provides +* native AGP support, this module should *NOT* be used. Instead +* wrappers should be placed around the OS support functions +* to implement this functionality. +* +****************************************************************************/ + +#include "pmapi.h" +#ifndef REALMODE +#include "nucleus/agp.h" + +/*--------------------------- Global variables ----------------------------*/ + +static AGP_devCtx *agp; +static AGP_driverFuncs driver; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +RETURNS: +Size of AGP aperture in MB on success, 0 on failure. + +REMARKS: +This function initialises the AGP driver in the system and returns the +size of the available AGP aperture in megabytes. +****************************************************************************/ +ulong PMAPI PM_agpInit(void) +{ + if ((agp = AGP_loadDriver(0)) == NULL) + return 0; + driver.dwSize = sizeof(driver); + if (!agp->QueryFunctions(AGP_GET_DRIVERFUNCS,&driver)) + return 0; + switch (driver.GetApertureSize()) { + case agpSize4MB: return 4; + case agpSize8MB: return 8; + case agpSize16MB: return 16; + case agpSize32MB: return 32; + case agpSize64MB: return 64; + case agpSize128MB: return 128; + case agpSize256MB: return 256; + case agpSize512MB: return 512; + case agpSize1GB: return 1024; + case agpSize2GB: return 2048; + } + return 0; +} + +/**************************************************************************** +REMARKS: +This function closes down the loaded AGP driver. +****************************************************************************/ +void PMAPI PM_agpExit(void) +{ + AGP_unloadDriver(agp); +} + +/**************************************************************************** +PARAMETERS: +numPages - Number of memory pages that should be reserved +type - Type of memory to allocate +physContext - Returns the physical context handle for the mapping +physAddr - Returns the physical address for the mapping + +RETURNS: +True on success, false on failure. + +REMARKS: +This function reserves a range of physical memory addresses on the system +bus which the AGP controller will respond to. If this function succeeds, +the AGP controller can respond to the reserved physical address range on +the bus. However you must first call AGP_commitPhysical to cause this memory +to actually be committed for use before it can be accessed. +****************************************************************************/ +ibool PMAPI PM_agpReservePhysical( + ulong numPages, + int type, + void **physContext, + PM_physAddr *physAddr) +{ + switch (type) { + case PM_agpUncached: + type = agpUncached; + break; + case PM_agpWriteCombine: + type = agpWriteCombine; + break; + case PM_agpIntelDCACHE: + type = agpIntelDCACHE; + break; + default: + return false; + } + return driver.ReservePhysical(numPages,type,physContext,physAddr) == nOK; +} + +/**************************************************************************** +PARAMETERS: +physContext - Physical AGP context to release + +RETURNS: +True on success, false on failure. + +REMARKS: +This function releases a range of physical memory addresses on the system +bus which the AGP controller will respond to. All committed memory for +the physical address range covered by the context will be released. +****************************************************************************/ +ibool PMAPI PM_agpReleasePhysical( + void *physContext) +{ + return driver.ReleasePhysical(physContext) == nOK; +} + +/**************************************************************************** +PARAMETERS: +physContext - Physical AGP context to commit memory for +numPages - Number of pages to be committed +startOffset - Offset in pages into the reserved physical context +physAddr - Returns the physical address of the committed memory + +RETURNS: +True on success, false on failure. + +REMARKS: +This function commits into the specified physical context that was previously +reserved by a call to ReservePhysical. You can use the startOffset and +numPages parameters to only commit portions of the reserved memory range at +a time. +****************************************************************************/ +ibool PMAPI PM_agpCommitPhysical( + void *physContext, + ulong numPages, + ulong startOffset, + PM_physAddr *physAddr) +{ + return driver.CommitPhysical(physContext,numPages,startOffset,physAddr) == nOK; +} + +/**************************************************************************** +PARAMETERS: +physContext - Physical AGP context to free memory for +numPages - Number of pages to be freed +startOffset - Offset in pages into the reserved physical context + +RETURNS: +True on success, false on failure. + +REMARKS: +This function frees memory previously committed by the CommitPhysical +function. Note that you can free a portion of a memory range that was +previously committed if you wish. +****************************************************************************/ +ibool PMAPI PM_agpFreePhysical( + void *physContext, + ulong numPages, + ulong startOffset) +{ + return driver.FreePhysical(physContext,numPages,startOffset) == nOK; +} + +#endif /* !REALMODE */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c b/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c new file mode 100644 index 000000000..36867bdba --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c @@ -0,0 +1,449 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Direct keyboard event handling module. This module contains +* code to process raw scan code information, convert it to +* virtual scan codes and do code page translation to ASCII +* for different international keyboard layouts. +* +****************************************************************************/ + +/*---------------------------- Implementation -----------------------------*/ + +/**************************************************************************** +PARAMETERS: +scanCode - Keyboard scan code to translate +table - Code page table to search +count - Number of entries in the code page table + +REMARKS: +This function translates the scan codes from keyboard scan codes to ASCII +codes using a binary search on the code page table. +****************************************************************************/ +static uchar translateScan( + uchar scanCode, + codepage_entry_t *table, + int count) +{ + codepage_entry_t *test; + int n,pivot,val; + + for (n = count; n > 0; ) { + pivot = n >> 1; + test = table + pivot; + val = scanCode - test->scanCode; + if (val < 0) + n = pivot; + else if (val == 0) + return test->asciiCode; + else { + table = test + 1; + n -= pivot + 1; + } + } + return 0; +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +{secret} +****************************************************************************/ +void _EVT_maskKeyCode( + event_t *evt) +{ + int ascii,scan = EVT_scanCode(evt->message); + + evt->message &= ~0xFF; + if (evt->modifiers & EVT_NUMLOCK) { + if ((ascii = translateScan(scan,EVT.codePage->numPad,EVT.codePage->numPadLen)) != 0) { + evt->message |= ascii; + return; + } + } + if (evt->modifiers & EVT_CTRLSTATE) { + evt->message |= translateScan(scan,EVT.codePage->ctrl,EVT.codePage->ctrlLen); + return; + } + if (evt->modifiers & EVT_CAPSLOCK) { + if (evt->modifiers & EVT_SHIFTKEY) { + if ((ascii = translateScan(scan,EVT.codePage->shiftCaps,EVT.codePage->shiftCapsLen)) != 0) { + evt->message |= ascii; + return; + } + } + else { + if ((ascii = translateScan(scan,EVT.codePage->caps,EVT.codePage->capsLen)) != 0) { + evt->message |= ascii; + return; + } + } + } + if (evt->modifiers & EVT_SHIFTKEY) { + if ((ascii = translateScan(scan,EVT.codePage->shift,EVT.codePage->shiftLen)) != 0) { + evt->message |= ascii; + return; + } + } + evt->message |= translateScan(scan,EVT.codePage->normal,EVT.codePage->normalLen); +} + +/**************************************************************************** +REMARKS: +Returns true if the key with the specified scan code is being held down. +****************************************************************************/ +static ibool _EVT_isKeyDown( + uchar scanCode) +{ + if (scanCode > 0x7F) + return false; + else + return EVT.keyTable[scanCode] != 0; +} + +/**************************************************************************** +PARAMETERS: +what - Event code +message - Event message (ASCII code and scan code) + +REMARKS: +Adds a new keyboard event to the event queue. This routine is called from +within the keyboard interrupt subroutine! + +NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, + and we leave them OFF the entire time. +****************************************************************************/ +static void addKeyEvent( + uint what, + uint message) +{ + event_t evt; + + if (EVT.count < EVENTQSIZE) { + /* Save information in event record */ + evt.when = _EVT_getTicks(); + evt.what = what; + evt.message = message | 0x10000UL; + evt.where_x = 0; + evt.where_y = 0; + evt.relative_x = 0; + evt.relative_y = 0; + evt.modifiers = EVT.keyModifiers; + if (evt.what == EVT_KEYREPEAT) { + if (EVT.oldKey != -1) + EVT.evtq[EVT.oldKey].message += 0x10000UL; + else { + EVT.oldKey = EVT.freeHead; + addEvent(&evt); /* Add to tail of event queue */ + } + } + else { +#ifdef __QNX__ + _EVT_maskKeyCode(&evt); +#endif + addEvent(&evt); /* Add to tail of event queue */ + } + EVT.oldMove = -1; + } +} + +/**************************************************************************** +REMARKS: +This function waits for the keyboard controller to set the ready-for-write +bit. +****************************************************************************/ +static int kbWaitForWriteReady(void) +{ + int timeout = 8192; + while ((timeout > 0) && (PM_inpb(0x64) & 0x02)) + timeout--; + return (timeout > 0); +} + +/**************************************************************************** +REMARKS: +This function waits for the keyboard controller to set the ready-for-read +bit. +****************************************************************************/ +static int kbWaitForReadReady(void) +{ + int timeout = 8192; + while ((timeout > 0) && (!(PM_inpb(0x64) & 0x01))) + timeout--; + return (timeout > 0); +} + +/**************************************************************************** +PARAMETERS: +data - Data to send to the keyboard + +REMARKS: +This function sends a data byte to the keyboard controller. +****************************************************************************/ +static int kbSendData( + uchar data) +{ + int resends = 4; + int timeout, temp; + + do { + if (!kbWaitForWriteReady()) + return 0; + PM_outpb(0x60,data); + timeout = 8192; + while (--timeout > 0) { + if (!kbWaitForReadReady()) + return 0; + temp = PM_inpb(0x60); + if (temp == 0xFA) + return 1; + if (temp == 0xFE) + break; + } + } while ((resends-- > 0) && (timeout > 0)); + return 0; +} + +/**************************************************************************** +PARAMETERS: +modifiers - Keyboard modifier flags + +REMARKS: +This function re-programs the LED's on the keyboard to the values stored +in the passed in modifier flags. If the 'allowLEDS' flag is false, this +function does nothing. +****************************************************************************/ +static void setLEDS( + uint modifiers) +{ + if (EVT.allowLEDS) { + if (!kbSendData(0xED) || !kbSendData((modifiers>>9) & 7)) { + kbSendData(0xF4); + } + } +} + +/**************************************************************************** +REMARKS: +Function to process raw scan codes read from the keyboard controller. + +NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, + and we leave them OFF the entire time. +{secret} +****************************************************************************/ +void processRawScanCode( + int scan) +{ + static int pauseLoop = 0; + static int extended = 0; + int what; + + if (pauseLoop) { + /* Skip scan codes until the pause key sequence has been read */ + pauseLoop--; + } + else if (scan == 0xE0) { + /* This signals the start of an extended scan code sequence */ + extended = 1; + } + else if (scan == 0xE1) { + /* The Pause key sends a strange scan code sequence, which is: + * + * E1 1D 52 E1 9D D2 + * + * However there is never any release code nor any auto-repeat for + * this key. For this reason we simply ignore the key and skip the + * next 5 scan codes read from the keyboard. + */ + pauseLoop = 5; + } + else { + /* Process the scan code normally (it may be an extended code + * however!). Bit 7 means key was released, and bits 0-6 are the + * scan code. + */ + what = (scan & 0x80) ? EVT_KEYUP : EVT_KEYDOWN; + scan &= 0x7F; + if (extended) { + extended = 0; + if (scan == 0x2A || scan == 0x36) { + /* Ignore these extended scan code sequences. These are + * used by the keyboard controller to wrap around certain + * key sequences for the keypad (and when NUMLOCK is down + * internally). + */ + return; + } + + /* Convert extended codes for key sequences that we map to + * virtual scan codes so the user can detect them in their + * code. + */ + switch (scan) { + case KB_leftCtrl: scan = KB_rightCtrl; break; + case KB_leftAlt: scan = KB_rightAlt; break; + case KB_divide: scan = KB_padDivide; break; + case KB_enter: scan = KB_padEnter; break; + case KB_padTimes: scan = KB_sysReq; break; + } + } + else { + /* Convert regular scan codes for key sequences that we map to + * virtual scan codes so the user can detect them in their + * code. + */ + switch (scan) { + case KB_left: scan = KB_padLeft; break; + case KB_right: scan = KB_padRight; break; + case KB_up: scan = KB_padUp; break; + case KB_down: scan = KB_padDown; break; + case KB_insert: scan = KB_padInsert; break; + case KB_delete: scan = KB_padDelete; break; + case KB_home: scan = KB_padHome; break; + case KB_end: scan = KB_padEnd; break; + case KB_pageUp: scan = KB_padPageUp; break; + case KB_pageDown: scan = KB_padPageDown; break; + } + } + + /* Determine if the key is an UP, DOWN or REPEAT and maintain the + * up/down status of all keys in our global key array. + */ + if (what == EVT_KEYDOWN) { + if (EVT.keyTable[scan]) + what = EVT_KEYREPEAT; + else + EVT.keyTable[scan] = scan; + } + else { + EVT.keyTable[scan] = 0; + } + + /* Handle shift key modifiers */ + if (what != EVT_KEYREPEAT) { + switch (scan) { + case KB_capsLock: + if (what == EVT_KEYDOWN) + EVT.keyModifiers ^= EVT_CAPSLOCK; + setLEDS(EVT.keyModifiers); + break; + case KB_numLock: + if (what == EVT_KEYDOWN) + EVT.keyModifiers ^= EVT_NUMLOCK; + setLEDS(EVT.keyModifiers); + break; + case KB_scrollLock: + if (what == EVT_KEYDOWN) + EVT.keyModifiers ^= EVT_SCROLLLOCK; + setLEDS(EVT.keyModifiers); + break; + case KB_leftShift: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_LEFTSHIFT; + else + EVT.keyModifiers |= EVT_LEFTSHIFT; + break; + case KB_rightShift: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_RIGHTSHIFT; + else + EVT.keyModifiers |= EVT_RIGHTSHIFT; + break; + case KB_leftCtrl: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_LEFTCTRL; + else + EVT.keyModifiers |= EVT_LEFTCTRL; + break; + case KB_rightCtrl: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_RIGHTCTRL; + else + EVT.keyModifiers |= EVT_RIGHTCTRL; + break; + case KB_leftAlt: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_LEFTALT; + else + EVT.keyModifiers |= EVT_LEFTALT; + break; + case KB_rightAlt: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_RIGHTALT; + else + EVT.keyModifiers |= EVT_RIGHTALT; + break; +#ifdef SUPPORT_CTRL_ALT_DEL + case KB_delete: + if ((EVT.keyModifiers & EVT_CTRLSTATE) && (EVT.keyModifiers & EVT_ALTSTATE)) + Reboot(); + break; +#endif + } + } + + /* Add the untranslated key code to the event queue. All + * translation to ASCII from the key codes occurs when the key + * is extracted from the queue, saving time in the low level + * interrupt handler. + */ + addKeyEvent(what,scan << 8); + } +} + +/**************************************************************************** +DESCRIPTION: +Enables/disables the update of the keyboard LED status indicators. + +HEADER: +event.h + +PARAMETERS: +enable - True to enable, false to disable + +REMARKS: +Enables the update of the keyboard LED status indicators. Sometimes it may +be convenient in the application to turn off the updating of the LED +status indicators (such as if a game is using the CAPSLOCK key for some +function). Passing in a value of FALSE to this function will turn off all +the LEDS, and stop updating them when the internal status changes (note +however that internally we still keep track of the toggle key status!). +****************************************************************************/ +void EVTAPI EVT_allowLEDS( + ibool enable) +{ + EVT.allowLEDS = true; + if (enable) + setLEDS(EVT.keyModifiers); + else + setLEDS(0); + EVT.allowLEDS = enable; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c b/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c new file mode 100644 index 000000000..83ef22113 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/malloc.c @@ -0,0 +1,205 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module for implementing the PM library overrideable memory +* allocator functions. +* +****************************************************************************/ + +#include "pmapi.h" + +/*--------------------------- Global variables ----------------------------*/ + +void * (*__PM_malloc)(size_t size) = malloc; +void * (*__PM_calloc)(size_t nelem,size_t size) = calloc; +void * (*__PM_realloc)(void *ptr,size_t size) = realloc; +void (*__PM_free)(void *p) = free; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +DESCRIPTION: +Use local memory allocation routines. + +HEADER: +pmapi.h + +PARAMETERS: +malloc - Pointer to new malloc routine to use +calloc - Pointer to new caalloc routine to use +realloc - Pointer to new realloc routine to use +free - Pointer to new free routine to use + +REMARKS: +Tells the PM library to use a set of user specified memory allocation +routines instead of using the normal malloc/calloc/realloc/free standard +C library functions. This is useful if you wish to use a third party +debugging malloc library or perhaps a set of faster memory allocation +functions with the PM library, or any apps that use the PM library (such as +the MGL). Once you have registered your memory allocation routines, all +calls to PM_malloc, PM_calloc, PM_realloc and PM_free will be revectored to +your local memory allocation routines. + +This is also useful if you need to keep track of just how much physical +memory your program has been using. You can use the PM_availableMemory +function to find out how much physical memory is available when the program +starts, and then you can use your own local memory allocation routines to +keep track of how much memory has been used and freed. + +NOTE: This function should be called right at the start of your application, + before you initialise any other components or libraries. + +NOTE: Code compiled into Binary Portable DLL's and Drivers automatically + end up calling these functions via the BPD C runtime library. + +SEE ALSO: +PM_malloc, PM_calloc, PM_realloc, PM_free, PM_availableMemory +****************************************************************************/ +void PMAPI PM_useLocalMalloc( + void * (*malloc)(size_t size), + void * (*calloc)(size_t nelem,size_t size), + void * (*realloc)(void *ptr,size_t size), + void (*free)(void *p)) +{ + __PM_malloc = malloc; + __PM_calloc = calloc; + __PM_realloc = realloc; + __PM_free = free; +} + +/**************************************************************************** +DESCRIPTION: +Allocate a block of memory. + +HEADER: +pmapi.h + +PARAMETERS: +size - Size of block to allocate in bytes + +RETURNS: +Pointer to allocated block, or NULL if out of memory. + +REMARKS: +Allocates a block of memory of length size. If you have changed the memory +allocation routines with the PM_useLocalMalloc function, then calls to this +function will actually make calls to the local memory allocation routines +that you have registered. + +SEE ALSO: +PM_calloc, PM_realloc, PM_free, PM_useLocalMalloc +****************************************************************************/ +void * PMAPI PM_malloc( + size_t size) +{ + return __PM_malloc(size); +} + +/**************************************************************************** +DESCRIPTION: +Allocate and clear a large memory block. + +HEADER: +pmapi.h + +PARAMETERS: +nelem - number of contiguous size-byte units to allocate +size - size of unit in bytes + +RETURNS: +Pointer to allocated memory if successful, NULL if out of memory. + +REMARKS: +Allocates a block of memory of length (size * nelem), and clears the +allocated area with zeros (0). If you have changed the memory allocation +routines with the PM_useLocalMalloc function, then calls to this function +will actually make calls to the local memory allocation routines that you +have registered. + +SEE ALSO: +PM_malloc, PM_realloc, PM_free, PM_useLocalMalloc +****************************************************************************/ +void * PMAPI PM_calloc( + size_t nelem, + size_t size) +{ + return __PM_calloc(nelem,size); +} + +/**************************************************************************** +DESCRIPTION: +Re-allocate a block of memory + +HEADER: +pmapi.h + +PARAMETERS: +ptr - Pointer to block to resize +size - size of unit in bytes + +RETURNS: +Pointer to allocated memory if successful, NULL if out of memory. + +REMARKS: +This function reallocates a block of memory that has been previously been +allocated to the new of size. The new size may be smaller or larger than +the original block of memory. If you have changed the memory allocation +routines with the PM_useLocalMalloc function, then calls to this function +will actually make calls to the local memory allocation routines that you +have registered. + +SEE ALSO: +PM_malloc, PM_calloc, PM_free, PM_useLocalMalloc +****************************************************************************/ +void * PMAPI PM_realloc( + void *ptr, + size_t size) +{ + return __PM_realloc(ptr,size); +} + +/**************************************************************************** +DESCRIPTION: +Frees a block of memory. + +HEADER: +pmapi.h + +PARAMETERS: +p - Pointer to memory block to free + +REMARKS: +Frees a block of memory previously allocated with either PM_malloc, +PM_calloc or PM_realloc. + +SEE ALSO: +PM_malloc, PM_calloc, PM_realloc, PM_useLocalMalloc +****************************************************************************/ +void PMAPI PM_free( + void *p) +{ + __PM_free(p); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c b/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c new file mode 100644 index 000000000..eed5f45c9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c @@ -0,0 +1,867 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Heavily based on code copyright (C) Richard Gooch +* +* Language: ANSI C +* Environment: 32-bit Ring 0 device driver +* +* Description: Generic Memory Type Range Register (MTRR) functions to +* manipulate the MTRR registers on supported CPU's. This code +* *must* run at ring 0, so you can't normally include this +* code directly in normal applications (the except is DOS4GW +* apps which run at ring 0 under real DOS). Thus this code +* will normally be compiled into a ring 0 device driver for +* the target operating system. +* +****************************************************************************/ + +#include "pmapi.h" +#include "ztimerc.h" +#include "mtrr.h" + +#ifndef REALMODE + +/*--------------------------- Global variables ----------------------------*/ + +/* Intel pre-defined MTRR registers */ + +#define NUM_FIXED_RANGES 88 +#define INTEL_cap_MSR 0x0FE +#define INTEL_defType_MSR 0x2FF +#define INTEL_fix64K_00000_MSR 0x250 +#define INTEL_fix16K_80000_MSR 0x258 +#define INTEL_fix16K_A0000_MSR 0x259 +#define INTEL_fix4K_C0000_MSR 0x268 +#define INTEL_fix4K_C8000_MSR 0x269 +#define INTEL_fix4K_D0000_MSR 0x26A +#define INTEL_fix4K_D8000_MSR 0x26B +#define INTEL_fix4K_E0000_MSR 0x26C +#define INTEL_fix4K_E8000_MSR 0x26D +#define INTEL_fix4K_F0000_MSR 0x26E +#define INTEL_fix4K_F8000_MSR 0x26F + +/* Macros to find the address of a paricular MSR register */ + +#define INTEL_physBase_MSR(reg) (0x200 + 2 * (reg)) +#define INTEL_physMask_MSR(reg) (0x200 + 2 * (reg) + 1) + +/* Cyrix CPU configuration register indexes */ +#define CX86_CCR0 0xC0 +#define CX86_CCR1 0xC1 +#define CX86_CCR2 0xC2 +#define CX86_CCR3 0xC3 +#define CX86_CCR4 0xE8 +#define CX86_CCR5 0xE9 +#define CX86_CCR6 0xEA +#define CX86_DIR0 0xFE +#define CX86_DIR1 0xFF +#define CX86_ARR_BASE 0xC4 +#define CX86_RCR_BASE 0xDC + +/* Structure to maintain machine state while updating MTRR registers */ + +typedef struct { + ulong flags; + ulong defTypeLo; + ulong defTypeHi; + ulong cr4Val; + ulong ccr3; + } MTRRContext; + +static int numMTRR = -1; +static int cpuFamily,cpuType,cpuStepping; +static void (*getMTRR)(uint reg,ulong *base,ulong *size,int *type) = NULL; +static void (*setMTRR)(uint reg,ulong base,ulong size,int type) = NULL; +static int (*getFreeRegion)(ulong base,ulong size) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +RETURNS: +Returns non-zero if we have the write-combining memory type +****************************************************************************/ +static int MTRR_haveWriteCombine(void) +{ + ulong config,dummy; + + switch (cpuFamily) { + case CPU_AMD: + if (cpuType < CPU_AMDAthlon) { + /* AMD K6-2 stepping 8 and later support the MTRR registers. + * The earlier K6-2 steppings (300Mhz models) do not + * support MTRR's. + */ + if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8)) + return 0; + return 1; + } + /* Fall through for AMD Athlon which uses P6 style MTRR's */ + case CPU_Intel: + _MTRR_readMSR(INTEL_cap_MSR,&config,&dummy); + return (config & (1 << 10)); + case CPU_Cyrix: + /* Cyrix 6x86 and later support the MTRR registers */ + if (cpuType < CPU_Cyrix6x86) + return 0; + return 1; + } + return 0; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region + +RETURNS: +The index of the region on success, else -1 on error. + +REMARKS: +Generic function to find the location of a free MTRR register to be used +for creating a new mapping. +****************************************************************************/ +static int GENERIC_getFreeRegion( + ulong base, + ulong size) +{ + int i,ltype; + ulong lbase,lsize; + + for (i = 0; i < numMTRR; i++) { + getMTRR(i,&lbase,&lsize,<ype); + if (lsize < 1) + return i; + } + (void)base; + (void)size; + return -1; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region + +RETURNS: +The index of the region on success, else -1 on error. + +REMARKS: +Generic function to find the location of a free MTRR register to be used +for creating a new mapping. +****************************************************************************/ +static int AMDK6_getFreeRegion( + ulong base, + ulong size) +{ + int i,ltype; + ulong lbase,lsize; + + for (i = 0; i < numMTRR; i++) { + getMTRR(i,&lbase,&lsize,<ype); + if (lsize < 1) + return i; + } + (void)base; + (void)size; + return -1; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region + +RETURNS: +The index of the region on success, else -1 on error. + +REMARKS: +Cyrix specific function to find the location of a free MTRR register to be +used for creating a new mapping. +****************************************************************************/ +static int CYRIX_getFreeRegion( + ulong base, + ulong size) +{ + int i,ltype; + ulong lbase, lsize; + + if (size > 0x2000000UL) { + /* If we are to set up a region >32M then look at ARR7 immediately */ + getMTRR(7,&lbase,&lsize,<ype); + if (lsize < 1) + return 7; + } + else { + /* Check ARR0-6 registers */ + for (i = 0; i < 7; i++) { + getMTRR(i,&lbase,&lsize,<ype); + if (lsize < 1) + return i; + } + /* Try ARR7 but its size must be at least 256K */ + getMTRR(7,&lbase,&lsize,<ype); + if ((lsize < 1) && (size >= 0x40000)) + return i; + } + (void)base; + return -1; +} + +/**************************************************************************** +PARAMETERS: +c - Place to store the machine context across the call + +REMARKS: +Puts the processor into a state where MTRRs can be safely updated +****************************************************************************/ +static void MTRR_beginUpdate( + MTRRContext *c) +{ + c->flags = _MTRR_disableInt(); + if (cpuFamily != CPU_AMD || (cpuFamily == CPU_AMD && cpuType >= CPU_AMDAthlon)) { + switch (cpuFamily) { + case CPU_Intel: + case CPU_AMD: + /* Disable MTRRs, and set the default type to uncached */ + c->cr4Val = _MTRR_saveCR4(); + _MTRR_readMSR(INTEL_defType_MSR,&c->defTypeLo,&c->defTypeHi); + _MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo & 0xF300UL,c->defTypeHi); + break; + case CPU_Cyrix: + c->ccr3 = _MTRR_getCx86(CX86_CCR3); + _MTRR_setCx86(CX86_CCR3, (uchar)((c->ccr3 & 0x0F) | 0x10)); + break; + } + } +} + +/**************************************************************************** +PARAMETERS: +c - Place to restore the machine context from + +REMARKS: +Restores the processor after updating any of the registers +****************************************************************************/ +static void MTRR_endUpdate( + MTRRContext *c) +{ + if (cpuFamily != CPU_AMD || (cpuFamily == CPU_AMD && cpuType >= CPU_AMDAthlon)) { + PM_flushTLB(); + switch (cpuFamily) { + case CPU_Intel: + case CPU_AMD: + _MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo,c->defTypeHi); + _MTRR_restoreCR4(c->cr4Val); + break; + case CPU_Cyrix: + _MTRR_setCx86(CX86_CCR3,(uchar)c->ccr3); + break; + } + } + + /* Re-enable interrupts (if enabled previously) */ + _MTRR_restoreInt(c->flags); +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to read +base - Place to store the starting physical base address of the region +size - Place to store the size in bytes of the region +type - Place to store the type of the MTRR register + +REMARKS: +Intel specific function to read the value of a specific MTRR register. +****************************************************************************/ +static void INTEL_getMTRR( + uint reg, + ulong *base, + ulong *size, + int *type) +{ + ulong hi,maskLo,baseLo; + + _MTRR_readMSR(INTEL_physMask_MSR(reg),&maskLo,&hi); + if ((maskLo & 0x800) == 0) { + /* MTRR is disabled, so it is free */ + *base = 0; + *size = 0; + *type = 0; + return; + } + _MTRR_readMSR(INTEL_physBase_MSR(reg),&baseLo,&hi); + maskLo = (maskLo & 0xFFFFF000UL); + *size = ~(maskLo - 1); + *base = (baseLo & 0xFFFFF000UL); + *type = (baseLo & 0xFF); +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to set +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +REMARKS: +Intel specific function to set the value of a specific MTRR register to +the passed in base, size and type. +****************************************************************************/ +static void INTEL_setMTRR( + uint reg, + ulong base, + ulong size, + int type) +{ + MTRRContext c; + + MTRR_beginUpdate(&c); + if (size == 0) { + /* The invalid bit is kept in the mask, so we simply clear the + * relevant mask register to disable a range. + */ + _MTRR_writeMSR(INTEL_physMask_MSR(reg),0,0); + } + else { + _MTRR_writeMSR(INTEL_physBase_MSR(reg),base | type,0); + _MTRR_writeMSR(INTEL_physMask_MSR(reg),~(size - 1) | 0x800,0); + } + MTRR_endUpdate(&c); +} + +/**************************************************************************** +REMARKS: +Disabled banked write combing for Intel processors. We always disable this +because it invariably causes problems with older hardware. +****************************************************************************/ +static void INTEL_disableBankedWriteCombine(void) +{ + MTRRContext c; + + MTRR_beginUpdate(&c); + _MTRR_writeMSR(INTEL_fix16K_A0000_MSR,0,0); + MTRR_endUpdate(&c); +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to set +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +REMARKS: +Intel specific function to set the value of a specific MTRR register to +the passed in base, size and type. +****************************************************************************/ +static void AMD_getMTRR( + uint reg, + ulong *base, + ulong *size, + int *type) +{ + ulong low,high; + + /* Upper dword is region 1, lower is region 0 */ + _MTRR_readMSR(0xC0000085, &low, &high); + if (reg == 1) + low = high; + + /* Find the base and type for the region */ + *base = low & 0xFFFE0000; + *type = 0; + if (low & 1) + *type = PM_MTRR_UNCACHABLE; + if (low & 2) + *type = PM_MTRR_WRCOMB; + if ((low & 3) == 0) { + *size = 0; + return; + } + + /* This needs a little explaining. The size is stored as an + * inverted mask of bits of 128K granularity 15 bits long offset + * 2 bits + * + * So to get a size we do invert the mask and add 1 to the lowest + * mask bit (4 as its 2 bits in). This gives us a size we then shift + * to turn into 128K blocks + * + * eg 111 1111 1111 1100 is 512K + * + * invert 000 0000 0000 0011 + * +1 000 0000 0000 0100 + * *128K ... + */ + low = (~low) & 0x0FFFC; + *size = (low + 4) << 15; +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to set +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +REMARKS: +Intel specific function to set the value of a specific MTRR register to +the passed in base, size and type. +****************************************************************************/ +static void AMD_setMTRR( + uint reg, + ulong base, + ulong size, + int type) +{ + ulong low,high,newVal; + MTRRContext c; + + MTRR_beginUpdate(&c); + _MTRR_readMSR(0xC0000085, &low, &high); + if (size == 0) { + /* Clear register to disable */ + if (reg) + high = 0; + else + low = 0; + } + else { + /* Set the register to the base (already shifted for us), the + * type (off by one) and an inverted bitmask of the size + * The size is the only odd bit. We are fed say 512K + * We invert this and we get 111 1111 1111 1011 but + * if you subtract one and invert you get the desired + * 111 1111 1111 1100 mask + */ + newVal = (((~(size-1)) >> 15) & 0x0001FFFC) | base | (type+1); + if (reg) + high = newVal; + else + low = newVal; + } + + /* The writeback rule is quite specific. See the manual. Its + * disable local interrupts, write back the cache, set the MTRR + */ + PM_flushTLB(); + _MTRR_writeMSR(0xC0000085, low, high); + MTRR_endUpdate(&c); +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to set +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +REMARKS: +Intel specific function to set the value of a specific MTRR register to +the passed in base, size and type. +****************************************************************************/ +static void CYRIX_getMTRR( + uint reg, + ulong *base, + ulong *size, + int *type) +{ + MTRRContext c; + uchar arr = CX86_ARR_BASE + reg*3; + uchar rcr,shift; + + /* Save flags and disable interrupts */ + MTRR_beginUpdate(&c); + ((uchar*)base)[3] = _MTRR_getCx86(arr); + ((uchar*)base)[2] = _MTRR_getCx86((uchar)(arr+1)); + ((uchar*)base)[1] = _MTRR_getCx86((uchar)(arr+2)); + rcr = _MTRR_getCx86((uchar)(CX86_RCR_BASE + reg)); + MTRR_endUpdate(&c); + + /* Enable interrupts if it was enabled previously */ + shift = ((uchar*)base)[1] & 0x0f; + *base &= 0xFFFFF000UL; + + /* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7 + * Note: shift==0xF means 4G, this is unsupported. + */ + if (shift) + *size = (reg < 7 ? 0x800UL : 0x20000UL) << shift; + else + *size = 0; + + /* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */ + if (reg < 7) { + switch (rcr) { + case 1: *type = PM_MTRR_UNCACHABLE; break; + case 8: *type = PM_MTRR_WRBACK; break; + case 9: *type = PM_MTRR_WRCOMB; break; + case 24: + default: *type = PM_MTRR_WRTHROUGH; break; + } + } + else { + switch (rcr) { + case 0: *type = PM_MTRR_UNCACHABLE; break; + case 8: *type = PM_MTRR_WRCOMB; break; + case 9: *type = PM_MTRR_WRBACK; break; + case 25: + default: *type = PM_MTRR_WRTHROUGH; break; + } + } +} + +/**************************************************************************** +PARAMETERS: +reg - MTRR register to set +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +REMARKS: +Intel specific function to set the value of a specific MTRR register to +the passed in base, size and type. +****************************************************************************/ +static void CYRIX_setMTRR( + uint reg, + ulong base, + ulong size, + int type) +{ + MTRRContext c; + uchar arr = CX86_ARR_BASE + reg*3; + uchar arr_type,arr_size; + + /* Count down from 32M (ARR0-ARR6) or from 2G (ARR7) */ + size >>= (reg < 7 ? 12 : 18); + size &= 0x7FFF; /* Make sure arr_size <= 14 */ + for (arr_size = 0; size; arr_size++, size >>= 1) + ; + if (reg < 7) { + switch (type) { + case PM_MTRR_UNCACHABLE: arr_type = 1; break; + case PM_MTRR_WRCOMB: arr_type = 9; break; + case PM_MTRR_WRTHROUGH: arr_type = 24; break; + default: arr_type = 8; break; + } + } + else { + switch (type) { + case PM_MTRR_UNCACHABLE: arr_type = 0; break; + case PM_MTRR_WRCOMB: arr_type = 8; break; + case PM_MTRR_WRTHROUGH: arr_type = 25; break; + default: arr_type = 9; break; + } + } + MTRR_beginUpdate(&c); + _MTRR_setCx86((uchar)arr, ((uchar*)&base)[3]); + _MTRR_setCx86((uchar)(arr+1), ((uchar*)&base)[2]); + _MTRR_setCx86((uchar)(arr+2), (uchar)((((uchar*)&base)[1]) | arr_size)); + _MTRR_setCx86((uchar)(CX86_RCR_BASE + reg), (uchar)arr_type); + MTRR_endUpdate(&c); +} + +/**************************************************************************** +REMARKS: +On Cyrix 6x86(MX) and MII the ARR3 is special: it has connection +with the SMM (System Management Mode) mode. So we need the following: +Check whether SMI_LOCK (CCR3 bit 0) is set + if it is set, ARR3 cannot be changed (it cannot be changed until the + next processor reset) + if it is reset, then we can change it, set all the needed bits: + - disable access to SMM memory through ARR3 range (CCR1 bit 7 reset) + - disable access to SMM memory (CCR1 bit 2 reset) + - disable SMM mode (CCR1 bit 1 reset) + - disable write protection of ARR3 (CCR6 bit 1 reset) + - (maybe) disable ARR3 +Just to be sure, we enable ARR usage by the processor (CCR5 bit 5 set) +****************************************************************************/ +static void CYRIX_initARR(void) +{ + MTRRContext c; + uchar ccr[7]; + int ccrc[7] = { 0, 0, 0, 0, 0, 0, 0 }; + + /* Begin updating */ + MTRR_beginUpdate(&c); + + /* Save all CCRs locally */ + ccr[0] = _MTRR_getCx86(CX86_CCR0); + ccr[1] = _MTRR_getCx86(CX86_CCR1); + ccr[2] = _MTRR_getCx86(CX86_CCR2); + ccr[3] = (uchar)c.ccr3; + ccr[4] = _MTRR_getCx86(CX86_CCR4); + ccr[5] = _MTRR_getCx86(CX86_CCR5); + ccr[6] = _MTRR_getCx86(CX86_CCR6); + if (ccr[3] & 1) + ccrc[3] = 1; + else { + /* Disable SMM mode (bit 1), access to SMM memory (bit 2) and + * access to SMM memory through ARR3 (bit 7). + */ + if (ccr[6] & 0x02) { + ccr[6] &= 0xFD; + ccrc[6] = 1; /* Disable write protection of ARR3. */ + _MTRR_setCx86(CX86_CCR6,ccr[6]); + } + } + + /* If we changed CCR1 in memory, change it in the processor, too. */ + if (ccrc[1]) + _MTRR_setCx86(CX86_CCR1,ccr[1]); + + /* Enable ARR usage by the processor */ + if (!(ccr[5] & 0x20)) { + ccr[5] |= 0x20; + ccrc[5] = 1; + _MTRR_setCx86(CX86_CCR5,ccr[5]); + } + + /* We are finished updating */ + MTRR_endUpdate(&c); +} + +/**************************************************************************** +REMARKS: +Initialise the MTRR module, by detecting the processor type and determining +if the processor supports the MTRR functionality. +****************************************************************************/ +void MTRR_init(void) +{ + int i,cpu,ltype; + ulong eax,edx,lbase,lsize; + + /* Check that we have a compatible CPU */ + if (numMTRR == -1) { + numMTRR = 0; + if (!_MTRR_isRing0()) + return; + cpu = CPU_getProcessorType(); + cpuFamily = cpu & CPU_familyMask; + cpuType = cpu & CPU_mask; + cpuStepping = (cpu & CPU_steppingMask) >> CPU_steppingShift; + switch (cpuFamily) { + case CPU_Intel: + /* Intel Pentium Pro and later support the MTRR registers */ + if (cpuType < CPU_PentiumPro) + return; + _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx); + numMTRR = eax & 0xFF; + getMTRR = INTEL_getMTRR; + setMTRR = INTEL_setMTRR; + getFreeRegion = GENERIC_getFreeRegion; + INTEL_disableBankedWriteCombine(); + break; + case CPU_AMD: + /* AMD K6-2 and later support the MTRR registers */ + if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8)) + return; + if (cpuType < CPU_AMDAthlon) { + numMTRR = 2; /* AMD CPU's have 2 MTRR's */ + getMTRR = AMD_getMTRR; + setMTRR = AMD_setMTRR; + getFreeRegion = AMDK6_getFreeRegion; + + /* For some reason some IBM systems with K6-2 processors + * have write combined enabled for the system BIOS + * region from 0xE0000 to 0xFFFFFF. We need *both* MTRR's + * for our own graphics drivers, so if we detect any + * regions below the 1Meg boundary, we remove them + * so we can use this MTRR register ourselves. + */ + for (i = 0; i < numMTRR; i++) { + getMTRR(i,&lbase,&lsize,<ype); + if (lbase < 0x100000) + setMTRR(i,0,0,0); + } + } + else { + /* AMD Athlon uses P6 style MTRR's */ + _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx); + numMTRR = eax & 0xFF; + getMTRR = INTEL_getMTRR; + setMTRR = INTEL_setMTRR; + getFreeRegion = GENERIC_getFreeRegion; + INTEL_disableBankedWriteCombine(); + } + break; + case CPU_Cyrix: + /* Cyrix 6x86 and later support the MTRR registers */ + if (cpuType < CPU_Cyrix6x86 || cpuType >= CPU_CyrixMediaGX) + return; + numMTRR = 8; /* Cyrix CPU's have 8 ARR's */ + getMTRR = CYRIX_getMTRR; + setMTRR = CYRIX_setMTRR; + getFreeRegion = CYRIX_getFreeRegion; + CYRIX_initARR(); + break; + default: + return; + } + } +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int MTRR_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ + int i; + int ltype; + ulong lbase,lsize,last; + + /* Check that we have a CPU that supports MTRR's and type is valid */ + if (numMTRR <= 0) { + if (!_MTRR_isRing0()) + return PM_MTRR_ERR_NO_OS_SUPPORT; + return PM_MTRR_NOT_SUPPORTED; + } + if (type >= PM_MTRR_MAX) + return PM_MTRR_ERR_PARAMS; + + /* If the type is WC, check that this processor supports it */ + if (!MTRR_haveWriteCombine()) + return PM_MTRR_ERR_NOWRCOMB; + + /* Adjust the boundaries depending on the CPU type */ + switch (cpuFamily) { + case CPU_AMD: + if (cpuType < CPU_AMDAthlon) { + /* Apply the K6 block alignment and size rules. In order: + * o Uncached or gathering only + * o 128K or bigger block + * o Power of 2 block + * o base suitably aligned to the power + */ + if (type > PM_MTRR_WRCOMB && (size < (1 << 17) || (size & ~(size-1))-size || (base & (size-1)))) + return PM_MTRR_ERR_NOT_ALIGNED; + break; + } + /* Fall through for AMD Athlon which uses P6 style MTRR's */ + case CPU_Intel: + case CPU_Cyrix: + if ((base & 0xFFF) || (size & 0xFFF)) { + /* Base and size must be multiples of 4Kb */ + return PM_MTRR_ERR_NOT_4KB_ALIGNED; + } + if (base < 0x100000) { + /* Base must be >= 1Mb */ + return PM_MTRR_ERR_BELOW_1MB; + } + + /* Check upper bits of base and last are equal and lower bits + * are 0 for base and 1 for last + */ + last = base + size - 1; + for (lbase = base; !(lbase & 1) && (last & 1); lbase = lbase >> 1, last = last >> 1) + ; + if (lbase != last) { + /* Base is not aligned on the correct boundary */ + return PM_MTRR_ERR_NOT_ALIGNED; + } + break; + default: + return PM_MTRR_NOT_SUPPORTED; + } + + /* Search for existing MTRR */ + for (i = 0; i < numMTRR; ++i) { + getMTRR(i,&lbase,&lsize,<ype); + if (lbase == 0 && lsize == 0) + continue; + if (base > lbase + (lsize-1)) + continue; + if ((base < lbase) && (base+size-1 < lbase)) + continue; + + /* Check that we don't overlap an existing region */ + if (type != PM_MTRR_UNCACHABLE) { + if ((base < lbase) || (base+size-1 > lbase+lsize-1)) + return PM_MTRR_ERR_OVERLAP; + } + else if (base == lbase && size == lsize) { + /* The region already exists so leave it alone */ + return PM_MTRR_ERR_OK; + } + + /* New region is enclosed by an existing region, so only allow + * a new type to be created if we are setting a region to be + * uncacheable (such as MMIO registers within a framebuffer). + */ + if (ltype != (int)type) { + if (type == PM_MTRR_UNCACHABLE) + continue; + return PM_MTRR_ERR_TYPE_MISMATCH; + } + return PM_MTRR_ERR_OK; + } + + /* Search for an empty MTRR */ + if ((i = getFreeRegion(base,size)) < 0) + return PM_MTRR_ERR_NONE_FREE; + setMTRR(i,base,size,type); + return PM_MTRR_ERR_OK; +} + +/**************************************************************************** +PARAMETERS: +callback - Function to callback with write combine information + +REMARKS: +Function to enumerate all write combine regions currently enabled for the +processor. +****************************************************************************/ +int PMAPI PM_enumWriteCombine( + PM_enumWriteCombine_t callback) +{ + int i,ltype; + ulong lbase,lsize; + + /* Check that we have a CPU that supports MTRR's and type is valid */ + if (numMTRR <= 0) { + if (!_MTRR_isRing0()) + return PM_MTRR_ERR_NO_OS_SUPPORT; + return PM_MTRR_NOT_SUPPORTED; + } + + /* Enumerate all existing MTRR's */ + for (i = 0; i < numMTRR; ++i) { + getMTRR(i,&lbase,&lsize,<ype); + callback(lbase,lsize,ltype); + } + return PM_MTRR_ERR_OK; +} +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c b/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c new file mode 100644 index 000000000..1d542fc5d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c @@ -0,0 +1,747 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module for interfacing to the PCI bus and configuration +* space registers. +* +****************************************************************************/ + +#include "pmapi.h" +#include "pcilib.h" +#if !defined(__WIN32_VXD__) && !defined(__NT_DRIVER__) +#include +#endif + +/*---------------------- Macros and type definitions ----------------------*/ + +#pragma pack(1) + +/* Length of the memory mapping for the PCI BIOS */ + +#define BIOS_LIMIT (128 * 1024L - 1) + +/* Macros for accessing the PCI BIOS functions from 32-bit protected mode */ + +#define BIOS32_SIGNATURE (((ulong)'_' << 0) + ((ulong)'3' << 8) + ((ulong)'2' << 16) + ((ulong)'_' << 24)) +#define PCI_SIGNATURE (((ulong)'P' << 0) + ((ulong)'C' << 8) + ((ulong)'I' << 16) + ((ulong)' ' << 24)) +#define PCI_SERVICE (((ulong)'$' << 0) + ((ulong)'P' << 8) + ((ulong)'C' << 16) + ((ulong)'I' << 24)) +#define PCI_BIOS_PRESENT 0xB101 +#define FIND_PCI_DEVICE 0xB102 +#define FIND_PCI_CLASS 0xB103 +#define GENERATE_SPECIAL 0xB106 +#define READ_CONFIG_BYTE 0xB108 +#define READ_CONFIG_WORD 0xB109 +#define READ_CONFIG_DWORD 0xB10A +#define WRITE_CONFIG_BYTE 0xB10B +#define WRITE_CONFIG_WORD 0xB10C +#define WRITE_CONFIG_DWORD 0xB10D +#define GET_IRQ_ROUTING_OPT 0xB10E +#define SET_PCI_IRQ 0xB10F + +/* This is the standard structure used to identify the entry point to the + * BIOS32 Service Directory, as documented in PCI 2.1 BIOS Specicition. + */ + +typedef union { + struct { + ulong signature; /* _32_ */ + ulong entry; /* 32 bit physical address */ + uchar revision; /* Revision level, 0 */ + uchar length; /* Length in paragraphs should be 01 */ + uchar checksum; /* All bytes must add up to zero */ + uchar reserved[5]; /* Must be zero */ + } fields; + char chars[16]; + } PCI_bios32; + +/* Structure for a far pointer to call the PCI BIOS services with */ + +typedef struct { + ulong address; + ushort segment; + } PCIBIOS_entry; + +/* Macros to copy a structure that includes dwSize members */ + +#define COPY_STRUCTURE(d,s) memcpy(d,s,MIN((s)->dwSize,(d)->dwSize)) + +#pragma pack() + +/*--------------------------- Global variables ----------------------------*/ + +static uchar *BIOSImage = NULL; /* BIOS image mapping */ +static int PCIBIOSVersion = -1;/* PCI BIOS version */ +static PCIBIOS_entry PCIEntry; /* PCI services entry point */ +static ulong PCIPhysEntry = 0; /* Physical address */ + +/*----------------------------- Implementation ----------------------------*/ + +/* External assembler helper functions */ + +uchar _ASMAPI _BIOS32_service(ulong service,ulong function,ulong *physBase,ulong *length,ulong *serviceOffset,PCIBIOS_entry entry); +ushort _ASMAPI _PCIBIOS_isPresent(ulong i_eax,ulong *o_edx,ushort *o_ax,uchar *o_cl,PCIBIOS_entry entry); +ulong _ASMAPI _PCIBIOS_service(ulong r_eax,ulong r_ebx,ulong r_edi,ulong r_ecx,PCIBIOS_entry entry); +int _ASMAPI _PCIBIOS_getRouting(PCIRoutingOptionsBuffer *buf,PCIBIOS_entry entry); +ibool _ASMAPI _PCIBIOS_setIRQ(int busDev,int intPin,int IRQ,PCIBIOS_entry entry); +ulong _ASMAPI _PCIBIOS_specialCycle(int bus,ulong data,PCIBIOS_entry entry); +ushort _ASMAPI _PCI_getCS(void); + +/**************************************************************************** +REMARKS: +This functions returns the physical address of the PCI BIOS entry point. +****************************************************************************/ +ulong _ASMAPI PCIBIOS_getEntry(void) +{ return PCIPhysEntry; } + +/**************************************************************************** +PARAMETERS: +hwType - Place to store the PCI hardware access mechanism flags +lastBus - Place to store the index of the last PCI bus in the system + +RETURNS: +Version number of the PCI BIOS found. + +REMARKS: +This function determines if the PCI BIOS is present in the system, and if +so returns the information returned by the PCI BIOS detect function. +****************************************************************************/ +static int PCIBIOS_detect( + uchar *hwType, + uchar *lastBus) +{ + ulong signature; + ushort stat,version; + +#ifndef __16BIT__ + PCIBIOS_entry BIOSEntry = {0}; + uchar *BIOSEnd; + PCI_bios32 *BIOSDir; + ulong physBase,length,offset; + + /* Bail if we have already detected no BIOS is present */ + if (PCIBIOSVersion == 0) + return 0; + + /* First scan the memory from 0xE0000 to 0xFFFFF looking for the + * BIOS32 service directory, so we can determine if we can call it + * from 32-bit protected mode. + */ + if (PCIBIOSVersion == -1) { + PCIBIOSVersion = 0; + BIOSImage = PM_mapPhysicalAddr(0xE0000,BIOS_LIMIT,false); + if (!BIOSImage) + return 0; + BIOSEnd = BIOSImage + 0x20000; + for (BIOSDir = (PCI_bios32*)BIOSImage; BIOSDir < (PCI_bios32*)BIOSEnd; BIOSDir++) { + uchar sum; + int i,length; + + if (BIOSDir->fields.signature != BIOS32_SIGNATURE) + continue; + length = BIOSDir->fields.length * 16; + if (!length) + continue; + for (sum = i = 0; i < length ; i++) + sum += BIOSDir->chars[i]; + if (sum != 0) + continue; + BIOSEntry.address = (ulong)BIOSImage + (BIOSDir->fields.entry - 0xE0000); + BIOSEntry.segment = _PCI_getCS(); + break; + } + + /* If we found the BIOS32 directory, call it to get the address of the + * PCI services. + */ + if (BIOSEntry.address == 0) + return 0; + if (_BIOS32_service(PCI_SERVICE,0,&physBase,&length,&offset,BIOSEntry) != 0) + return 0; + PCIPhysEntry = physBase + offset; + PCIEntry.address = (ulong)BIOSImage + (PCIPhysEntry - 0xE0000); + PCIEntry.segment = _PCI_getCS(); + } +#endif + /* We found the BIOS entry, so now do the version check */ + version = _PCIBIOS_isPresent(PCI_BIOS_PRESENT,&signature,&stat,lastBus,PCIEntry); + if (version > 0 && ((stat >> 8) == 0) && signature == PCI_SIGNATURE) { + *hwType = stat & 0xFF; + return PCIBIOSVersion = version; + } + return 0; +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to check against +index - Index of the current device to check + +RETURNS: +True if the device is a duplicate, false if not. + +REMARKS: +This function goes through the list of all devices preceeding the newly +found device in the info structure, and checks that the device is not a +duplicate of a previous device. Some devices incorrectly enumerate +themselves at different function addresses so we check here to exclude +those cases. +****************************************************************************/ +static ibool CheckDuplicate( + PCIDeviceInfo *info, + PCIDeviceInfo *prev) +{ + /* Ignore devices with a vendor ID of 0 */ + if (info->VendorID == 0) + return true; + + /* NOTE: We only check against the current device on + * the bus to ensure that we do not exclude + * multiple controllers of the same device ID. + */ + if (info->slot.p.Bus == prev->slot.p.Bus && + info->slot.p.Device == prev->slot.p.Device && + info->DeviceID == prev->DeviceID) + return true; + return false; +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to fill in +maxDevices - Maximum number of of devices to enumerate into array + +RETURNS: +Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. + +REMARKS: +Function to enumerate all available devices on the PCI bus into an array +of configuration information blocks. +****************************************************************************/ +static int PCI_enumerateMech1( + PCIDeviceInfo info[]) +{ + int bus,device,function,i,numFound = 0; + ulong *lp,tmp; + PCIslot slot = {{0,0,0,0,0,0,1}}; + PCIDeviceInfo pci,prev = {0}; + + /* Try PCI access mechanism 1 */ + PM_outpb(0xCFB,0x01); + tmp = PM_inpd(0xCF8); + PM_outpd(0xCF8,slot.i); + if ((PM_inpd(0xCF8) == slot.i) && (PM_inpd(0xCFC) != 0xFFFFFFFFUL)) { + /* PCI access mechanism 1 - the preferred mechanism */ + for (bus = 0; bus < 8; bus++) { + slot.p.Bus = bus; + for (device = 0; device < 32; device++) { + slot.p.Device = device; + for (function = 0; function < 8; function++) { + slot.p.Function = function; + slot.p.Register = 0; + PM_outpd(0xCF8,slot.i); + if (PM_inpd(0xCFC) != 0xFFFFFFFFUL) { + memset(&pci,0,sizeof(pci)); + pci.dwSize = sizeof(pci); + pci.mech1 = 1; + pci.slot = slot; + lp = (ulong*)&(pci.VendorID); + for (i = 0; i < NUM_PCI_REG; i++, lp++) { + slot.p.Register = i; + PM_outpd(0xCF8,slot.i); + *lp = PM_inpd(0xCFC); + } + if (!CheckDuplicate(&pci,&prev)) { + if (info) + COPY_STRUCTURE(&info[numFound],&pci); + ++numFound; + } + prev = pci; + } + } + } + } + + /* Disable PCI config cycle on exit */ + PM_outpd(0xCF8,0); + return numFound; + } + PM_outpd(0xCF8,tmp); + + /* No hardware access mechanism 1 found */ + return 0; +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to fill in +maxDevices - Maximum number of of devices to enumerate into array + +RETURNS: +Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. + +REMARKS: +Function to enumerate all available devices on the PCI bus into an array +of configuration information blocks. +****************************************************************************/ +static int PCI_enumerateMech2( + PCIDeviceInfo info[]) +{ + int bus,device,function,i,numFound = 0; + ushort deviceIO; + ulong *lp; + PCIslot slot = {{0,0,0,0,0,0,1}}; + PCIDeviceInfo pci,prev = {0}; + + /* Try PCI access mechanism 2 */ + PM_outpb(0xCFB,0x00); + PM_outpb(0xCF8,0x00); + PM_outpb(0xCFA,0x00); + if (PM_inpb(0xCF8) == 0x00 && PM_inpb(0xCFB) == 0x00) { + /* PCI access mechanism 2 - the older mechanism for legacy busses */ + for (bus = 0; bus < 2; bus++) { + slot.p.Bus = bus; + PM_outpb(0xCFA,(uchar)bus); + for (device = 0; device < 16; device++) { + slot.p.Device = device; + deviceIO = 0xC000 + (device << 8); + for (function = 0; function < 8; function++) { + slot.p.Function = function; + slot.p.Register = 0; + PM_outpb(0xCF8,(uchar)((function << 1) | 0x10)); + if (PM_inpd(deviceIO) != 0xFFFFFFFFUL) { + memset(&pci,0,sizeof(pci)); + pci.dwSize = sizeof(pci); + pci.mech1 = 0; + pci.slot = slot; + lp = (ulong*)&(pci.VendorID); + for (i = 0; i < NUM_PCI_REG; i++, lp++) { + slot.p.Register = i; + *lp = PM_inpd(deviceIO + (i << 2)); + } + if (!CheckDuplicate(&pci,&prev)) { + if (info) + COPY_STRUCTURE(&info[numFound],&pci); + ++numFound; + } + prev = pci; + } + } + } + } + + /* Disable PCI config cycle on exit */ + PM_outpb(0xCF8,0); + return numFound; + } + + /* No hardware access mechanism 2 found */ + return 0; +} + +/**************************************************************************** +REMARKS: +This functions reads a configuration dword via the PCI BIOS. +****************************************************************************/ +static ulong PCIBIOS_readDWORD( + int index, + ulong slot) +{ + return (ulong)_PCIBIOS_service(READ_CONFIG_DWORD,slot >> 8,index,0,PCIEntry); +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to fill in +maxDevices - Maximum number of of devices to enumerate into array + +RETURNS: +Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. + +REMARKS: +Function to enumerate all available devices on the PCI bus into an array +of configuration information blocks. +****************************************************************************/ +static int PCI_enumerateBIOS( + PCIDeviceInfo info[]) +{ + uchar hwType,lastBus; + int bus,device,function,i,numFound = 0; + ulong *lp; + PCIslot slot = {{0,0,0,0,0,0,1}}; + PCIDeviceInfo pci,prev = {0}; + + if (PCIBIOS_detect(&hwType,&lastBus)) { + /* PCI BIOS access - the ultimate fallback */ + for (bus = 0; bus <= lastBus; bus++) { + slot.p.Bus = bus; + for (device = 0; device < 32; device++) { + slot.p.Device = device; + for (function = 0; function < 8; function++) { + slot.p.Function = function; + if (PCIBIOS_readDWORD(0,slot.i) != 0xFFFFFFFFUL) { + memset(&pci,0,sizeof(pci)); + pci.dwSize = sizeof(pci); + pci.mech1 = 2; + pci.slot = slot; + lp = (ulong*)&(pci.VendorID); + for (i = 0; i < NUM_PCI_REG; i++, lp++) + *lp = PCIBIOS_readDWORD(i << 2,slot.i); + if (!CheckDuplicate(&pci,&prev)) { + if (info) + COPY_STRUCTURE(&info[numFound],&pci); + ++numFound; + } + prev = pci; + } + } + } + } + } + + /* Return number of devices found */ + return numFound; +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to fill in +maxDevices - Maximum number of of devices to enumerate into array + +RETURNS: +Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. + +REMARKS: +Function to enumerate all available devices on the PCI bus into an array +of configuration information blocks. +****************************************************************************/ +int _ASMAPI PCI_enumerate( + PCIDeviceInfo info[]) +{ + int numFound; + + /* First try via the direct access mechanisms which are faster if we + * have them (nearly always). The BIOS is used as a fallback, and for + * stuff we can't do directly. + */ + if ((numFound = PCI_enumerateMech1(info)) == 0) { + if ((numFound = PCI_enumerateMech2(info)) == 0) { + if ((numFound = PCI_enumerateBIOS(info)) == 0) + return 0; + } + } + return numFound; +} + +/**************************************************************************** +PARAMETERS: +info - Array of PCIDeviceInfo structures to fill in +maxDevices - Maximum number of of devices to enumerate into array + +RETURNS: +Number of PCI devices found and enumerated on the PCI bus, 0 if not PCI. + +REMARKS: +Function to enumerate all available devices on the PCI bus into an array +of configuration information blocks. +****************************************************************************/ +int _ASMAPI PCI_getNumDevices(void) +{ + return PCI_enumerate(NULL); +} + +/**************************************************************************** +PARAMETERS: +bar - Base address to measure +pci - PCI device to access + +RETURNS: +Size of the PCI base address in bytes + +REMARKS: +This function measures the size of the PCI base address register in bytes, +by writing all F's to the register, and reading the value back. The size +of the base address is determines by the bits that are hardwired to zero's. +****************************************************************************/ +ulong _ASMAPI PCI_findBARSize( + int bar, + PCIDeviceInfo *pci) +{ + ulong base,size = 0; + + base = PCI_accessReg(bar,0,PCI_READ_DWORD,pci); + if (base && !(base & 0x1)) { + /* For some strange reason some devices don't properly decode + * their base address registers (Intel PCI/PCI bridges!), and + * we read completely bogus values. We check for that here + * and clear out those BAR's. + * + * We check for that here because at least the low 12 bits + * of the address range must be zeros, since the page size + * on IA32 processors is always 4Kb. + */ + if ((base & 0xFFF) == 0) { + PCI_accessReg(bar,0xFFFFFFFF,PCI_WRITE_DWORD,pci); + size = PCI_accessReg(bar,0,PCI_READ_DWORD,pci) & ~0xFF; + size = ~size+1; + PCI_accessReg(bar,base,PCI_WRITE_DWORD,pci); + } + } + pci->slot.p.Register = 0; + return size; +} + +/**************************************************************************** +PARAMETERS: +index - DWORD index of the register to access +value - Value to write to the register for write access +func - Function to implement + +RETURNS: +The value read from the register for read operations + +REMARKS: +The function code are defined as follows + +code - function +0 - Read BYTE +1 - Read WORD +2 - Read DWORD +3 - Write BYTE +4 - Write WORD +5 - Write DWORD +****************************************************************************/ +ulong _ASMAPI PCI_accessReg( + int index, + ulong value, + int func, + PCIDeviceInfo *info) +{ + int iobase; + + if (info->mech1 == 2) { + /* Use PCI BIOS access since we dont have direct hardware access */ + switch (func) { + case PCI_READ_BYTE: + return (uchar)_PCIBIOS_service(READ_CONFIG_BYTE,info->slot.i >> 8,index,0,PCIEntry); + case PCI_READ_WORD: + return (ushort)_PCIBIOS_service(READ_CONFIG_WORD,info->slot.i >> 8,index,0,PCIEntry); + case PCI_READ_DWORD: + return (ulong)_PCIBIOS_service(READ_CONFIG_DWORD,info->slot.i >> 8,index,0,PCIEntry); + case PCI_WRITE_BYTE: + _PCIBIOS_service(WRITE_CONFIG_BYTE,info->slot.i >> 8,index,value,PCIEntry); + break; + case PCI_WRITE_WORD: + _PCIBIOS_service(WRITE_CONFIG_WORD,info->slot.i >> 8,index,value,PCIEntry); + break; + case PCI_WRITE_DWORD: + _PCIBIOS_service(WRITE_CONFIG_DWORD,info->slot.i >> 8,index,value,PCIEntry); + break; + } + } + else { + /* Use direct hardware access mechanisms */ + if (info->mech1) { + /* PCI access mechanism 1 */ + iobase = 0xCFC + (index & 3); + info->slot.p.Register = index >> 2; + PM_outpd(0xCF8,info->slot.i); + } + else { + /* PCI access mechanism 2 */ + PM_outpb(0xCF8,(uchar)((info->slot.p.Function << 1) | 0x10)); + PM_outpb(0xCFA,(uchar)info->slot.p.Bus); + iobase = 0xC000 + (info->slot.p.Device << 8) + index; + } + switch (func) { + case PCI_READ_BYTE: + case PCI_READ_WORD: + case PCI_READ_DWORD: value = PM_inpd(iobase); break; + case PCI_WRITE_BYTE: PM_outpb(iobase,(uchar)value); break; + case PCI_WRITE_WORD: PM_outpw(iobase,(ushort)value); break; + case PCI_WRITE_DWORD: PM_outpd(iobase,(ulong)value); break; + } + PM_outpd(0xCF8,0); + } + return value; +} + +/**************************************************************************** +PARAMETERS: +numDevices - Number of devices to query info for + +RETURNS: +0 on success, -1 on error, number of devices to enumerate if numDevices = 0 + +REMARKS: +This function reads the PCI routing information. If you pass a value of +0 for numDevices, this function will return with the number of devices +needed in the routing buffer that will be filled in by the BIOS. +****************************************************************************/ +ibool _ASMAPI PCI_getIRQRoutingOptions( + int numDevices, + PCIRouteInfo *buffer) +{ + PCIRoutingOptionsBuffer buf; + int ret; + + if (PCIPhysEntry) { + buf.BufferSize = numDevices * sizeof(PCIRouteInfo); + buf.DataBuffer = buffer; + if ((ret = _PCIBIOS_getRouting(&buf,PCIEntry)) == 0x89) + return buf.BufferSize / sizeof(PCIRouteInfo); + if (ret != 0) + return -1; + return 0; + } + + /* We currently only support this via the PCI BIOS functions */ + return -1; +} + +/**************************************************************************** +PARAMETERS: +info - PCI device information for the specified device +intPin - Value to store in the PCI InterruptPin register +IRQ - New ISA IRQ to map the PCI interrupt to (0-15) + +RETURNS: +True on success, or false if this function failed. + +REMARKS: +This function changes the PCI IRQ routing for the specified device to the +desired PCI interrupt and the desired ISA bus compatible IRQ. This function +may not be supported by the PCI BIOS, in which case this function will +fail. +****************************************************************************/ +ibool _ASMAPI PCI_setHardwareIRQ( + PCIDeviceInfo *info, + uint intPin, + uint IRQ) +{ + if (PCIPhysEntry) { + if (_PCIBIOS_setIRQ(info->slot.i >> 8,intPin,IRQ,PCIEntry)) { + info->u.type0.InterruptPin = intPin; + info->u.type0.InterruptLine = IRQ; + return true; + } + return false; + } + + /* We currently only support this via the PCI BIOS functions */ + return false; +} + +/**************************************************************************** +PARAMETERS: +bus - Bus number to generate the special cycle for +specialCycleData - Data to send for the special cyle + +REMARKS: +This function generates a special cycle on the specified bus using with +the specified data. +****************************************************************************/ +void _ASMAPI PCI_generateSpecialCyle( + uint bus, + ulong specialCycleData) +{ + if (PCIPhysEntry) + _PCIBIOS_specialCycle(bus,specialCycleData,PCIEntry); + /* We currently only support this via the PCI BIOS functions */ +} + +/**************************************************************************** +PARAMETERS: +info - PCI device information block for device to access +index - Index of register to start reading from +dst - Place to store the values read from configuration space +count - Count of bytes to read from configuration space + +REMARKS: +This function is used to read a block of PCI configuration space registers +from the configuration space into the passed in data block. This function +will properly handle reading non-DWORD aligned data from the configuration +space correctly. +****************************************************************************/ +void _ASMAPI PCI_readRegBlock( + PCIDeviceInfo *info, + int index, + void *dst, + int count) +{ + uchar *pb; + ulong *pd; + int i; + int startCount = (index & 3); + int middleCount = (count - startCount) >> 2; + int endCount = count - middleCount * 4 - startCount; + + for (i = 0,pb = dst; i < startCount; i++, index++) { + *pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info); + } + for (i = 0,pd = (ulong*)pb; i < middleCount; i++, index += 4) { + *pd++ = (ulong)PCI_accessReg(index,0,PCI_READ_DWORD,info); + } + for (i = 0,pb = (uchar*)pd; i < endCount; i++, index++) { + *pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info); + } +} + +/**************************************************************************** +PARAMETERS: +info - PCI device information block for device to access +index - Index of register to start reading from +dst - Place to store the values read from configuration space +count - Count of bytes to read from configuration space + +REMARKS: +This function is used to write a block of PCI configuration space registers +to the configuration space from the passed in data block. This function +will properly handle writing non-DWORD aligned data to the configuration +space correctly. +****************************************************************************/ +void _ASMAPI PCI_writeRegBlock( + PCIDeviceInfo *info, + int index, + void *src, + int count) +{ + uchar *pb; + ulong *pd; + int i; + int startCount = (index & 3); + int middleCount = (count - startCount) >> 2; + int endCount = count - middleCount * 4 - startCount; + + for (i = 0,pb = src; i < startCount; i++, index++) { + PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info); + } + for (i = 0,pd = (ulong*)pb; i < middleCount; i++, index += 4) { + PCI_accessReg(index,*pd++,PCI_WRITE_DWORD,info); + } + for (i = 0,pb = (uchar*)pd; i < endCount; i++, index++) { + PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info); + } +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c b/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c new file mode 100644 index 000000000..c3a66a7c1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c @@ -0,0 +1,306 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module containing Unix I/O functions. +* +****************************************************************************/ + +#include "pmapi.h" +#include +#include +#include +#include +#include +#include + +/*----------------------------- Implementation ----------------------------*/ + +/* {secret} */ +typedef struct { + DIR *d; + char path[PM_MAX_PATH]; + char mask[PM_MAX_PATH]; + } PM_findHandle; + +/**************************************************************************** +REMARKS: +Internal function to convert the find data to the generic interface. +****************************************************************************/ +static void convertFindData( + PM_findData *findData, + struct dirent *blk, + const char *path) +{ + ulong dwSize = findData->dwSize; + struct stat st; + char filename[PM_MAX_PATH]; + + memset(findData,0,findData->dwSize); + findData->dwSize = dwSize; + strcpy(filename,path); + PM_backslash(filename); + strcat(filename,blk->d_name); + stat(filename,&st); + if (!(st.st_mode & S_IWRITE)) + findData->attrib |= PM_FILE_READONLY; + if (st.st_mode & S_IFDIR) + findData->attrib |= PM_FILE_DIRECTORY; + findData->sizeLo = st.st_size; + findData->sizeHi = 0; + strncpy(findData->name,blk->d_name,PM_MAX_PATH); + findData->name[PM_MAX_PATH-1] = 0; +} + +/**************************************************************************** +REMARKS: +Determines if a file name matches the passed in pattern. +****************************************************************************/ +static ibool filematch( + char *pattern, + char *dirpath, + struct dirent *dire) +{ + struct stat st; + int i = 0,j = 0,lastchar = '\0'; + char fullpath[PM_MAX_PATH]; + + strcpy(fullpath,dirpath); + PM_backslash(fullpath); + strcat(fullpath, dire->d_name); + if (stat(fullpath, &st) != 0) + return false; + for (; i < (int)strlen(dire->d_name) && j < (int)strlen(pattern); i++, j++) { + if (pattern[j] == '*' && lastchar != '\\') { + if (pattern[j+1] == '\0') + return true; + while (dire->d_name[i++] != pattern[j+1]) { + if (dire->d_name[i] == '\0') + return false; + } + i -= 2; + } + else if (dire->d_name[i] != pattern[j] && + !(pattern[j] == '?' && lastchar != '\\')) + return false; + lastchar = pattern[i]; + } + if (j == (int)strlen(pattern) && i == (int)strlen(dire->d_name)) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void * PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + PM_findHandle *d; + struct dirent *dire; + char name[PM_MAX_PATH]; + char ext[PM_MAX_PATH]; + + if ((d = PM_malloc(sizeof(*d))) == NULL) + return PM_FILE_INVALID; + PM_splitpath(filename,NULL,d->path,name,ext); + strcpy(d->mask,name); + strcat(d->mask,ext); + if (strlen(d->path) == 0) + strcpy(d->path, "."); + if (d->path[strlen(d->path)-1] == '/') + d->path[strlen(d->path)-1] = 0; + if ((d->d = opendir(d->path)) != NULL) { + while ((dire = readdir(d->d)) != NULL) { + if (filematch(d->mask,d->path,dire)) { + convertFindData(findData,dire,d->path); + return d; + } + } + closedir(d->d); + } + PM_free(d); + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + PM_findHandle *d = handle; + struct dirent *dire; + + while ((dire = readdir(d->d)) != NULL) { + if (filematch(d->mask,d->path,dire)) { + convertFindData(findData,dire,d->path); + return true; + } + } + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + PM_findHandle *d = handle; + + closedir(d->d); + free(d); +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + if (drive == 3) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + (void)drive; + getcwd(dir,len); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + struct stat st; + mode_t mode; + + stat(filename,&st); + mode = st.st_mode; + if (attrib & PM_FILE_READONLY) + mode &= ~S_IWRITE; + else + mode |= S_IWRITE; + chmod(filename,mode); +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + struct stat st; + + stat(filename,&st); + if (st.st_mode & S_IWRITE) + return 0; + return PM_FILE_READONLY; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + return mkdir(filename,0x1FF) == 0; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return rmdir(filename) == 0; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_getFileTime not implemented yet!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_setFileTime not implemented yet!"); + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c b/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c new file mode 100644 index 000000000..8056e9a33 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c @@ -0,0 +1,377 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Portions copyright (C) Josh Vanderhoof +* +* Language: ANSI C +* Environment: Any +* +* Description: Functions to save and restore the VGA hardware state. +* +****************************************************************************/ + +#include "pmapi.h" +#if defined(__WIN32_VXD__) || defined(__NT_DRIVER__) +#include "sdd/sddhelp.h" +#else +#include +#endif + +/*--------------------------- Global variables ----------------------------*/ + +/* VGA index register ports */ +#define CRT_I 0x3D4 /* CRT Controller Index */ +#define ATT_IW 0x3C0 /* Attribute Controller Index & Data */ +#define GRA_I 0x3CE /* Graphics Controller Index */ +#define SEQ_I 0x3C4 /* Sequencer Index */ + +/* VGA data register ports */ +#define CRT_D 0x3D5 /* CRT Controller Data Register */ +#define ATT_R 0x3C1 /* Attribute Controller Data Read Register */ +#define GRA_D 0x3CF /* Graphics Controller Data Register */ +#define SEQ_D 0x3C5 /* Sequencer Data Register */ +#define MIS_R 0x3CC /* Misc Output Read Register */ +#define MIS_W 0x3C2 /* Misc Output Write Register */ +#define IS1_R 0x3DA /* Input Status Register 1 */ +#define PEL_IW 0x3C8 /* PEL Write Index */ +#define PEL_IR 0x3C7 /* PEL Read Index */ +#define PEL_D 0x3C9 /* PEL Data Register */ + +/* standard VGA indexes max counts */ +#define CRT_C 24 /* 24 CRT Controller Registers */ +#define ATT_C 21 /* 21 Attribute Controller Registers */ +#define GRA_C 9 /* 9 Graphics Controller Registers */ +#define SEQ_C 5 /* 5 Sequencer Registers */ +#define MIS_C 1 /* 1 Misc Output Register */ +#define PAL_C 768 /* 768 Palette Registers */ +#define FONT_C 8192 /* Total size of character generator RAM */ + +/* VGA registers saving indexes */ +#define CRT 0 /* CRT Controller Registers start */ +#define ATT (CRT+CRT_C) /* Attribute Controller Registers start */ +#define GRA (ATT+ATT_C) /* Graphics Controller Registers start */ +#define SEQ (GRA+GRA_C) /* Sequencer Registers */ +#define MIS (SEQ+SEQ_C) /* General Registers */ +#define PAL (MIS+MIS_C) /* VGA Palette Registers */ +#define FONT (PAL+PAL_C) /* VGA font data */ + +/* Macros for port I/O with arguments reversed */ + +#define _port_out(v,p) PM_outpb(p,(uchar)(v)) +#define _port_in(p) PM_inpb(p) + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Returns the size of the VGA state buffer. +****************************************************************************/ +int PMAPI PM_getVGAStateSize(void) +{ + return CRT_C + ATT_C + GRA_C + SEQ_C + MIS_C + PAL_C + FONT_C; +} + +/**************************************************************************** +REMARKS: +Delay for a short period of time. +****************************************************************************/ +static void vga_delay(void) +{ + int i; + + /* For the loop here we program the POST register. The length of this + * delay is dependant only on ISA bus speed, but it is enough for + * what we need. + */ + for (i = 0; i <= 10; i++) + PM_outpb(0x80, 0); +} + +/**************************************************************************** +PARAMETERS: +port - I/O port to read value from +index - Port index to read + +RETURNS: +Byte read from 'port' register 'index'. +****************************************************************************/ +static ushort vga_rdinx( + ushort port, + ushort index) +{ + PM_outpb(port,(uchar)index); + return PM_inpb(port+1); +} + +/**************************************************************************** +PARAMETERS: +port - I/O port to write to +index - Port index to write +value - Byte to write to port + +REMARKS: +Writes a byte value to the 'port' register 'index'. +****************************************************************************/ +static void vga_wrinx( + ushort port, + ushort index, + ushort value) +{ + PM_outpb(port,(uchar)index); + PM_outpb(port+1,(uchar)value); +} + +/**************************************************************************** +REMARKS: +Save the color palette values +****************************************************************************/ +static void vga_savepalette( + uchar *pal) +{ + int i; + + _port_out(0, PEL_IR); + for (i = 0; i < 768; i++) { + vga_delay(); + *pal++ = _port_in(PEL_D); + } +} + +/**************************************************************************** +REMARKS: +Restore the color palette values +****************************************************************************/ +static void vga_restorepalette( + const uchar *pal) +{ + int i; + + /* restore saved palette */ + _port_out(0, PEL_IW); + for (i = 0; i < 768; i++) { + vga_delay(); + _port_out(*pal++, PEL_D); + } +} + +/**************************************************************************** +REMARKS: +Read the font data from the VGA character generator RAM +****************************************************************************/ +static void vga_saveFont( + uchar *data) +{ + uchar *A0000Ptr = PM_getA0000Pointer(); + uchar save[7]; + + /* Enable access to character generator RAM */ + save[0] = (uchar)vga_rdinx(SEQ_I,0x00); + save[1] = (uchar)vga_rdinx(SEQ_I,0x02); + save[2] = (uchar)vga_rdinx(SEQ_I,0x04); + save[3] = (uchar)vga_rdinx(SEQ_I,0x00); + save[4] = (uchar)vga_rdinx(GRA_I,0x04); + save[5] = (uchar)vga_rdinx(GRA_I,0x05); + save[6] = (uchar)vga_rdinx(GRA_I,0x06); + vga_wrinx(SEQ_I,0x00,0x01); + vga_wrinx(SEQ_I,0x02,0x04); + vga_wrinx(SEQ_I,0x04,0x07); + vga_wrinx(SEQ_I,0x00,0x03); + vga_wrinx(GRA_I,0x04,0x02); + vga_wrinx(GRA_I,0x05,0x00); + vga_wrinx(GRA_I,0x06,0x00); + + /* Copy character generator RAM */ + memcpy(data,A0000Ptr,FONT_C); + + /* Restore VGA state */ + vga_wrinx(SEQ_I,0x00,save[0]); + vga_wrinx(SEQ_I,0x02,save[1]); + vga_wrinx(SEQ_I,0x04,save[2]); + vga_wrinx(SEQ_I,0x00,save[3]); + vga_wrinx(GRA_I,0x04,save[4]); + vga_wrinx(GRA_I,0x05,save[5]); + vga_wrinx(GRA_I,0x06,save[6]); +} + +/**************************************************************************** +REMARKS: +Downloads the font data to the VGA character generator RAM +****************************************************************************/ +static void vga_restoreFont( + const uchar *data) +{ + uchar *A0000Ptr = PM_getA0000Pointer(); + + /* Enable access to character generator RAM */ + vga_wrinx(SEQ_I,0x00,0x01); + vga_wrinx(SEQ_I,0x02,0x04); + vga_wrinx(SEQ_I,0x04,0x07); + vga_wrinx(SEQ_I,0x00,0x03); + vga_wrinx(GRA_I,0x04,0x02); + vga_wrinx(GRA_I,0x05,0x00); + vga_wrinx(GRA_I,0x06,0x00); + + /* Copy font back to character generator RAM */ + memcpy(A0000Ptr,data,FONT_C); +} + +/**************************************************************************** +REMARKS: +Save the state of all VGA compatible registers +****************************************************************************/ +void PMAPI PM_saveVGAState( + void *stateBuf) +{ + uchar *regs = stateBuf; + int i; + + /* Save state of VGA registers */ + for (i = 0; i < CRT_C; i++) { + _port_out(i, CRT_I); + regs[CRT + i] = _port_in(CRT_D); + } + for (i = 0; i < ATT_C; i++) { + _port_in(IS1_R); + vga_delay(); + _port_out(i, ATT_IW); + vga_delay(); + regs[ATT + i] = _port_in(ATT_R); + vga_delay(); + } + for (i = 0; i < GRA_C; i++) { + _port_out(i, GRA_I); + regs[GRA + i] = _port_in(GRA_D); + } + for (i = 0; i < SEQ_C; i++) { + _port_out(i, SEQ_I); + regs[SEQ + i] = _port_in(SEQ_D); + } + regs[MIS] = _port_in(MIS_R); + + /* Save the VGA palette values */ + vga_savepalette(®s[PAL]); + + /* Save the VGA character generator RAM */ + vga_saveFont(®s[FONT]); + + /* Turn the VGA display back on */ + PM_vgaUnblankDisplay(); +} + +/**************************************************************************** +REMARKS: +Retore the state of all VGA compatible registers +****************************************************************************/ +void PMAPI PM_restoreVGAState( + const void *stateBuf) +{ + const uchar *regs = stateBuf; + int i; + + /* Blank the display before we start the restore */ + PM_vgaBlankDisplay(); + + /* Restore the VGA character generator RAM */ + vga_restoreFont(®s[FONT]); + + /* Restore the VGA palette values */ + vga_restorepalette(®s[PAL]); + + /* Restore the state of the VGA compatible registers */ + _port_out(regs[MIS], MIS_W); + + /* Delay to allow clock change to settle */ + for (i = 0; i < 10; i++) + vga_delay(); + + /* Synchronous reset on */ + _port_out(0x00,SEQ_I); + _port_out(0x01,SEQ_D); + + /* Write seqeuencer registers */ + _port_out(1, SEQ_I); + _port_out(regs[SEQ + 1] | 0x20, SEQ_D); + for (i = 2; i < SEQ_C; i++) { + _port_out(i, SEQ_I); + _port_out(regs[SEQ + i], SEQ_D); + } + + /* Synchronous reset off */ + _port_out(0x00,SEQ_I); + _port_out(0x03,SEQ_D); + + /* Deprotect CRT registers 0-7 and write CRTC */ + _port_out(0x11, CRT_I); + _port_out(_port_in(CRT_D) & 0x7F, CRT_D); + for (i = 0; i < CRT_C; i++) { + _port_out(i, CRT_I); + _port_out(regs[CRT + i], CRT_D); + } + for (i = 0; i < GRA_C; i++) { + _port_out(i, GRA_I); + _port_out(regs[GRA + i], GRA_D); + } + for (i = 0; i < ATT_C; i++) { + _port_in(IS1_R); /* reset flip-flop */ + vga_delay(); + _port_out(i, ATT_IW); + vga_delay(); + _port_out(regs[ATT + i], ATT_IW); + vga_delay(); + } + + /* Ensure the VGA screen is turned on */ + PM_vgaUnblankDisplay(); +} + +/**************************************************************************** +REMARKS: +Disables the VGA display for screen output making it blank. +****************************************************************************/ +void PMAPI PM_vgaBlankDisplay(void) +{ + /* Turn screen off */ + _port_out(0x01, SEQ_I); + _port_out(_port_in(SEQ_D) | 0x20, SEQ_D); + + /* Disable video output */ + _port_in(IS1_R); + vga_delay(); + _port_out(0x00, ATT_IW); +} + +/**************************************************************************** +REMARKS: +Enables the VGA display for screen output. +****************************************************************************/ +void PMAPI PM_vgaUnblankDisplay(void) +{ + /* Turn screen back on */ + _port_out(0x01, SEQ_I); + _port_out(_port_in(SEQ_D) & 0xDF, SEQ_D); + + /* Enable video output */ + _port_in(IS1_R); + vga_delay(); + _port_out(0x20, ATT_IW); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c new file mode 100644 index 000000000..ac62e81c1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/cpuinfo.c @@ -0,0 +1,808 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Main module to implement the Zen Timer support functions. +* +****************************************************************************/ + +#include "ztimer.h" +#include "pmapi.h" +#include "oshdr.h" +#if !defined(__WIN32_VXD__) && !defined(__OS2_VDD__) && !defined(__NT_DRIVER__) +#include +#include +#endif + +/*----------------------------- Implementation ----------------------------*/ + +/* External Intel assembler functions */ +#ifdef __INTEL__ +/* {secret} */ +ibool _ASMAPI _CPU_haveCPUID(void); +/* {secret} */ +ibool _ASMAPI _CPU_check80386(void); +/* {secret} */ +ibool _ASMAPI _CPU_check80486(void); +/* {secret} */ +uint _ASMAPI _CPU_checkCPUID(void); +/* {secret} */ +uint _ASMAPI _CPU_getCPUIDModel(void); +/* {secret} */ +uint _ASMAPI _CPU_getCPUIDStepping(void); +/* {secret} */ +uint _ASMAPI _CPU_getCPUIDFeatures(void); +/* {secret} */ +uint _ASMAPI _CPU_getCacheSize(void); +/* {secret} */ +uint _ASMAPI _CPU_have3DNow(void); +/* {secret} */ +ibool _ASMAPI _CPU_checkClone(void); +/* {secret} */ +void _ASMAPI _CPU_readTimeStamp(CPU_largeInteger *time); +/* {secret} */ +void _ASMAPI _CPU_runBSFLoop(ulong iterations); +/* {secret} */ +ulong _ASMAPI _CPU_mulDiv(ulong a,ulong b,ulong c); +/* {secret} */ +void ZTimerQuickInit(void); +#define CPU_HaveMMX 0x00800000 +#define CPU_HaveRDTSC 0x00000010 +#define CPU_HaveSSE 0x02000000 +#endif + +#if defined(__SMX32__) +#include "smx/cpuinfo.c" +#elif defined(__RTTARGET__) +#include "rttarget/cpuinfo.c" +#elif defined(__REALDOS__) +#include "dos/cpuinfo.c" +#elif defined(__NT_DRIVER__) +#include "ntdrv/cpuinfo.c" +#elif defined(__WIN32_VXD__) +#include "vxd/cpuinfo.c" +#elif defined(__WINDOWS32__) +#include "win32/cpuinfo.c" +#elif defined(__OS2_VDD__) +#include "vdd/cpuinfo.c" +#elif defined(__OS2__) +#include "os2/cpuinfo.c" +#elif defined(__LINUX__) +#include "linux/cpuinfo.c" +#elif defined(__QNX__) +#include "qnx/cpuinfo.c" +#elif defined(__BEOS__) +#include "beos/cpuinfo.c" +#else +#error CPU library not ported to this platform yet! +#endif + +/*------------------------ Public interface routines ----------------------*/ + +/**************************************************************************** +REMARKS: +Read an I/O port location. +****************************************************************************/ +static uchar rdinx( + int port, + int index) +{ + PM_outpb(port,(uchar)index); + return PM_inpb(port+1); +} + +/**************************************************************************** +REMARKS: +Write an I/O port location. +****************************************************************************/ +static void wrinx( + ushort port, + ushort index, + ushort value) +{ + PM_outpb(port,(uchar)index); + PM_outpb(port+1,(uchar)value); +} + +/**************************************************************************** +REMARKS: +Enables the Cyrix CPUID instruction to properly detect MediaGX and 6x86 +processors. +****************************************************************************/ +static void _CPU_enableCyrixCPUID(void) +{ + uchar ccr3; + + PM_init(); + ccr3 = rdinx(0x22,0xC3); + wrinx(0x22,0xC3,(uchar)(ccr3 | 0x10)); + wrinx(0x22,0xE8,(uchar)(rdinx(0x22,0xE8) | 0x80)); + wrinx(0x22,0xC3,ccr3); +} + +/**************************************************************************** +DESCRIPTION: +Returns the type of processor in the system. + +HEADER: +ztimer.h + +RETURNS: +Numerical identifier for the installed processor + +REMARKS: +Returns the type of processor in the system. Note that if the CPU is an +unknown Pentium family processor that we don't have an enumeration for, +the return value will be greater than or equal to the value of CPU_UnkPentium +(depending on the value returned by the CPUID instruction). + +SEE ALSO: +CPU_getProcessorSpeed, CPU_haveMMX, CPU_getProcessorName +****************************************************************************/ +uint ZAPI CPU_getProcessorType(void) +{ +#if defined(__INTEL__) + uint cpu,vendor,model,cacheSize; + static ibool firstTime = true; + + if (_CPU_haveCPUID()) { + cpu = _CPU_checkCPUID(); + vendor = cpu & ~CPU_mask; + if (vendor == CPU_Intel) { + /* Check for Intel processors */ + switch (cpu & CPU_mask) { + case 4: cpu = CPU_i486; break; + case 5: cpu = CPU_Pentium; break; + case 6: + if ((model = _CPU_getCPUIDModel()) == 1) + cpu = CPU_PentiumPro; + else if (model <= 6) { + cacheSize = _CPU_getCacheSize(); + if ((model == 5 && cacheSize == 0) || + (model == 5 && cacheSize == 256) || + (model == 6 && cacheSize == 128)) + cpu = CPU_Celeron; + else + cpu = CPU_PentiumII; + } + else if (model >= 7) { + /* Model 7 == Pentium III */ + /* Model 8 == Celeron/Pentium III Coppermine */ + cacheSize = _CPU_getCacheSize(); + if ((model == 8 && cacheSize == 128)) + cpu = CPU_Celeron; + else + cpu = CPU_PentiumIII; + } + break; + default: + cpu = CPU_UnkIntel; + } + } + else if (vendor == CPU_Cyrix) { + /* Check for Cyrix processors */ + switch (cpu & CPU_mask) { + case 4: + if ((model = _CPU_getCPUIDModel()) == 4) + cpu = CPU_CyrixMediaGX; + else + cpu = CPU_UnkCyrix; + break; + case 5: + if ((model = _CPU_getCPUIDModel()) == 2) + cpu = CPU_Cyrix6x86; + else if (model == 4) + cpu = CPU_CyrixMediaGXm; + else + cpu = CPU_UnkCyrix; + break; + case 6: + if ((model = _CPU_getCPUIDModel()) <= 1) + cpu = CPU_Cyrix6x86MX; + else + cpu = CPU_UnkCyrix; + break; + default: + cpu = CPU_UnkCyrix; + } + } + else if (vendor == CPU_AMD) { + /* Check for AMD processors */ + switch (cpu & CPU_mask) { + case 4: + if ((model = _CPU_getCPUIDModel()) == 0) + cpu = CPU_AMDAm5x86; + else + cpu = CPU_AMDAm486; + break; + case 5: + if ((model = _CPU_getCPUIDModel()) <= 3) + cpu = CPU_AMDK5; + else if (model <= 7) + cpu = CPU_AMDK6; + else if (model == 8) + cpu = CPU_AMDK6_2; + else if (model == 9) + cpu = CPU_AMDK6_III; + else if (model == 13) { + if (_CPU_getCPUIDStepping() <= 3) + cpu = CPU_AMDK6_IIIplus; + else + cpu = CPU_AMDK6_2plus; + } + else + cpu = CPU_UnkAMD; + break; + case 6: + if ((model = _CPU_getCPUIDModel()) == 3) + cpu = CPU_AMDDuron; + else + cpu = CPU_AMDAthlon; + break; + default: + cpu = CPU_UnkAMD; + } + } + else if (vendor == CPU_IDT) { + /* Check for IDT WinChip processors */ + switch (cpu & CPU_mask) { + case 5: + if ((model = _CPU_getCPUIDModel()) <= 4) + cpu = CPU_WinChipC6; + else if (model == 8) + cpu = CPU_WinChip2; + else + cpu = CPU_UnkIDT; + break; + default: + cpu = CPU_UnkIDT; + } + } + else { + /* Assume a Pentium compatible Intel clone */ + cpu = CPU_Pentium; + } + return cpu | vendor | (_CPU_getCPUIDStepping() << CPU_steppingShift); + } + else { + if (_CPU_check80386()) + cpu = CPU_i386; + else if (_CPU_check80486()) { + /* If we get here we may have a Cyrix processor so we can try + * enabling the CPUID instruction and trying again. + */ + if (firstTime) { + firstTime = false; + _CPU_enableCyrixCPUID(); + return CPU_getProcessorType(); + } + cpu = CPU_i486; + } + else + cpu = CPU_Pentium; + if (!_CPU_checkClone()) + return cpu | CPU_Intel; + return cpu; + } +#elif defined(__ALPHA__) + return CPU_Alpha; +#elif defined(__MIPS__) + return CPU_Mips; +#elif defined(__PPC__) + return CPU_PowerPC; +#endif +} + +/**************************************************************************** +DESCRIPTION: +Returns true if the processor supports Intel MMX extensions. + +HEADER: +ztimer.h + +RETURNS: +True if MMX is available, false if not. + +REMARKS: +This function determines if the processor supports the Intel MMX extended +instruction set. + +SEE ALSO: +CPU_getProcessorType, CPU_getProcessorSpeed, CPU_have3DNow, CPU_haveSSE, +CPU_getProcessorName +****************************************************************************/ +ibool ZAPI CPU_haveMMX(void) +{ +#ifdef __INTEL__ + if (_CPU_haveCPUID()) + return (_CPU_getCPUIDFeatures() & CPU_HaveMMX) != 0; + return false; +#else + return false; +#endif +} + +/**************************************************************************** +DESCRIPTION: +Returns true if the processor supports AMD 3DNow! extensions. + +HEADER: +ztimer.h + +RETURNS: +True if 3DNow! is available, false if not. + +REMARKS: +This function determines if the processor supports the AMD 3DNow! extended +instruction set. + +SEE ALSO: +CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_haveSSE, +CPU_getProcessorName +****************************************************************************/ +ibool ZAPI CPU_have3DNow(void) +{ +#ifdef __INTEL__ + if (_CPU_haveCPUID()) + return _CPU_have3DNow(); + return false; +#else + return false; +#endif +} + +/**************************************************************************** +DESCRIPTION: +Returns true if the processor supports Intel KNI extensions. + +HEADER: +ztimer.h + +RETURNS: +True if Intel KNI is available, false if not. + +REMARKS: +This function determines if the processor supports the Intel KNI extended +instruction set. + +SEE ALSO: +CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_have3DNow, +CPU_getProcessorName +****************************************************************************/ +ibool ZAPI CPU_haveSSE(void) +{ +#ifdef __INTEL__ + if (_CPU_haveCPUID()) + return (_CPU_getCPUIDFeatures() & CPU_HaveSSE) != 0; + return false; +#else + return false; +#endif +} + +/**************************************************************************** +RETURNS: +True if the RTSC instruction is available, false if not. + +REMARKS: +This function determines if the processor supports the Intel RDTSC +instruction, for high precision timing. If the processor is not an Intel or +Intel clone CPU, this function will always return false. + +DESCRIPTION: +Returns true if the processor supports RDTSC extensions. + +HEADER: +ztimer.h + +RETURNS: +True if RTSC is available, false if not. + +REMARKS: +This function determines if the processor supports the RDTSC instruction +for reading the processor time stamp counter. + +SEE ALSO: +CPU_getProcessorType, CPU_getProcessorSpeed, CPU_haveMMX, CPU_have3DNow, +CPU_getProcessorName +****************************************************************************/ +ibool ZAPI CPU_haveRDTSC(void) +{ +#ifdef __INTEL__ + if (_CPU_haveCPUID()) + return (_CPU_getCPUIDFeatures() & CPU_HaveRDTSC) != 0; + return false; +#else + return false; +#endif +} + +#ifdef __INTEL__ + +#define ITERATIONS 16000 +#define SAMPLINGS 2 +#define INNER_LOOPS 400 + +/**************************************************************************** +REMARKS: +If processor does not support time stamp reading, but is at least a 386 or +above, utilize method of timing a loop of BSF instructions which take a +known number of cycles to run on i386(tm), i486(tm), and Pentium(R) +processors. +****************************************************************************/ +static ulong GetBSFCpuSpeed( + ulong cycles) +{ + CPU_largeInteger t0,t1,count_freq; + ulong ticks; /* Microseconds elapsed during test */ + ulong current; /* Variable to store time elapsed */ + int i,j,iPriority; + ulong lowest = (ulong)-1; + + iPriority = SetMaxThreadPriority(); + GetCounterFrequency(&count_freq); + for (i = 0; i < SAMPLINGS; i++) { + GetCounter(&t0); + for (j = 0; j < INNER_LOOPS; j++) + _CPU_runBSFLoop(ITERATIONS); + GetCounter(&t1); + current = t1.low - t0.low; + if (current < lowest) + lowest = current; + } + RestoreThreadPriority(iPriority); + + /* Compute frequency */ + ticks = _CPU_mulDiv(lowest,1000000,count_freq.low); + if ((ticks % count_freq.low) > (count_freq.low/2)) + ticks++; /* Round up if necessary */ + if (ticks == 0) + return 0; + return ((cycles*INNER_LOOPS)/ticks); +} + +#define TOLERANCE 1 + +/**************************************************************************** +REMARKS: +On processors supporting the Read Time Stamp opcode, compare elapsed +time on the High-Resolution Counter with elapsed cycles on the Time +Stamp Register. + +The inner loop runs up to 20 times oruntil the average of the previous +three calculated frequencies is within 1 MHz of each of the individual +calculated frequencies. This resampling increases the accuracy of the +results since outside factors could affect this calculation. +****************************************************************************/ +static ulong GetRDTSCCpuSpeed( + ibool accurate) +{ + CPU_largeInteger t0,t1,s0,s1,count_freq; + u64 stamp0, stamp1, ticks0, ticks1; + u64 total_cycles, cycles, hz, freq; + u64 total_ticks, ticks; + int tries,iPriority; + ulong maxCount; + + PM_set64_32(total_cycles,0); + PM_set64_32(total_ticks,0); + maxCount = accurate ? 600000 : 30000; + iPriority = SetMaxThreadPriority(); + GetCounterFrequency(&count_freq); + PM_set64(freq,count_freq.high,count_freq.low); + for (tries = 0; tries < 3; tries++) { + /* Loop until 100 ticks have passed since last read of hi-res + * counter. This accounts for overhead later. + */ + GetCounter(&t0); + t1.low = t0.low; + t1.high = t0.high; + while ((t1.low - t0.low) < 100) { + GetCounter(&t1); + _CPU_readTimeStamp(&s0); + } + + /* Loop until 30000 ticks have passed since last read of hi-res counter. + * This allows for elapsed time for sampling. For a hi-res frequency + * of 1MHz, this is about 0.03 of a second. The frequency reported + * by the OS dependent code should be tuned to provide a good + * sample period depending on the accuracy of the OS timers (ie: + * if the accuracy is lower, lower the frequency to spend more time + * in the inner loop to get better accuracy). + */ + t0.low = t1.low; + t0.high = t1.high; + while ((t1.low - t0.low) < maxCount) { + GetCounter(&t1); + _CPU_readTimeStamp(&s1); + } + + /* Find the difference during the timing loop */ + PM_set64(stamp0,s0.high,s0.low); + PM_set64(stamp1,s1.high,s1.low); + PM_set64(ticks0,t0.high,t0.low); + PM_set64(ticks1,t1.high,t1.low); + PM_sub64(cycles,stamp1,stamp0); + PM_sub64(ticks,ticks1,ticks0); + + /* Sum up the results */ + PM_add64(total_ticks,total_ticks,ticks); + PM_add64(total_cycles,total_cycles,cycles); + } + RestoreThreadPriority(iPriority); + + /* Compute frequency in Hz */ + PM_mul64(hz,total_cycles,freq); + PM_div64(hz,hz,total_ticks); + return PM_64to32(hz); +} + +#endif /* __INTEL__ */ + +/**************************************************************************** +DESCRIPTION: +Returns the speed of the processor in MHz. + +HEADER: +ztimer.h + +PARAMETERS: +accurate - True of the speed should be measured accurately + +RETURNS: +Processor speed in MHz. + +REMARKS: +This function returns the speed of the CPU in MHz. Note that if the speed +cannot be determined, this function will return 0. + +If the accurate parameter is set to true, this function will spend longer +profiling the speed of the CPU, and will not round the CPU speed that is +reported. This is important for highly accurate timing using the Pentium +RDTSC instruction, but it does take a lot longer for the profiling to +produce accurate results. + +SEE ALSO: +CPU_getProcessorSpeedInHz, CPU_getProcessorType, CPU_haveMMX, +CPU_getProcessorName +****************************************************************************/ +ulong ZAPI CPU_getProcessorSpeed( + ibool accurate) +{ +#if defined(__INTEL__) + /* Number of cycles needed to execute a single BSF instruction on i386+ + * processors. + */ + ulong cpuSpeed; + uint i; + static ulong intel_cycles[] = { + 115,47,43, + }; + static ulong cyrix_cycles[] = { + 38,38,52,52, + }; + static ulong amd_cycles[] = { + 49, + }; + static ulong known_speeds[] = { + 1000,950,900,850,800,750,700,650,600,550,500,450,433,400,350, + 333,300,266,233,200,166,150,133,120,100,90,75,66,60,50,33,20,0, + }; + + if (CPU_haveRDTSC()) { + cpuSpeed = (GetRDTSCCpuSpeed(accurate) + 500000) / 1000000; + } + else { + int type = CPU_getProcessorType(); + int processor = type & CPU_mask; + int vendor = type & CPU_familyMask; + if (vendor == CPU_Intel) + cpuSpeed = GetBSFCpuSpeed(ITERATIONS * intel_cycles[processor - CPU_i386]); + else if (vendor == CPU_Cyrix) + cpuSpeed = GetBSFCpuSpeed(ITERATIONS * cyrix_cycles[processor - CPU_Cyrix6x86]); + else if (vendor == CPU_AMD) + cpuSpeed = GetBSFCpuSpeed(ITERATIONS * amd_cycles[0]); + else + return 0; + } + + /* Now normalise the results given known processors speeds, if the + * speed we measure is within 2MHz of the expected values + */ + if (!accurate) { + for (i = 0; known_speeds[i] != 0; i++) { + if (cpuSpeed >= (known_speeds[i]-3) && cpuSpeed <= (known_speeds[i]+3)) { + return known_speeds[i]; + } + } + } + return cpuSpeed; +#else + return 0; +#endif +} + +/**************************************************************************** +DESCRIPTION: +Returns the speed of the processor in Hz. + +HEADER: +ztimer.h + +RETURNS: +Accurate processor speed in Hz. + +REMARKS: +This function returns the accurate speed of the CPU in Hz. Note that if the +speed cannot be determined, this function will return 0. + +This function is similar to the CPU_getProcessorSpeed function, except that +it attempts to accurately measure the CPU speed in Hz. This is used +internally in the Zen Timer libraries to provide accurate real world timing +information. This is important for highly accurate timing using the Pentium +RDTSC instruction, but it does take a lot longer for the profiling to +produce accurate results. + +SEE ALSO: +CPU_getProcessorSpeed, CPU_getProcessorType, CPU_haveMMX, +CPU_getProcessorName +****************************************************************************/ +ulong ZAPI CPU_getProcessorSpeedInHZ( + ibool accurate) +{ +#if defined(__INTEL__) + if (CPU_haveRDTSC()) { + return GetRDTSCCpuSpeed(accurate); + } + return CPU_getProcessorSpeed(false) * 1000000; +#else + return 0; +#endif +} + +/**************************************************************************** +DESCRIPTION: +Returns a string defining the speed and name of the processor. + +HEADER: +ztimer.h + +RETURNS: +Processor name string. + +REMARKS: +This function returns an English string describing the speed and name of the +CPU. + +SEE ALSO: +CPU_getProcessorType, CPU_haveMMX, CPU_getProcessorName +****************************************************************************/ +char * ZAPI CPU_getProcessorName(void) +{ +#if defined(__INTEL__) + static int cpu,speed = -1; + static char name[80]; + + if (speed == -1) { + cpu = CPU_getProcessorType(); + speed = CPU_getProcessorSpeed(false); + } + sprintf(name,"%d MHz ", speed); + switch (cpu & CPU_mask) { + case CPU_i386: + strcat(name,"Intel i386 processor"); + break; + case CPU_i486: + strcat(name,"Intel i486 processor"); + break; + case CPU_Pentium: + strcat(name,"Intel Pentium processor"); + break; + case CPU_PentiumPro: + strcat(name,"Intel Pentium Pro processor"); + break; + case CPU_PentiumII: + strcat(name,"Intel Pentium II processor"); + break; + case CPU_Celeron: + strcat(name,"Intel Celeron processor"); + break; + case CPU_PentiumIII: + strcat(name,"Intel Pentium III processor"); + break; + case CPU_UnkIntel: + strcat(name,"Unknown Intel processor"); + break; + case CPU_Cyrix6x86: + strcat(name,"Cyrix 6x86 processor"); + break; + case CPU_Cyrix6x86MX: + strcat(name,"Cyrix 6x86MX processor"); + break; + case CPU_CyrixMediaGX: + strcat(name,"Cyrix MediaGX processor"); + break; + case CPU_CyrixMediaGXm: + strcat(name,"Cyrix MediaGXm processor"); + break; + case CPU_UnkCyrix: + strcat(name,"Unknown Cyrix processor"); + break; + case CPU_AMDAm486: + strcat(name,"AMD Am486 processor"); + break; + case CPU_AMDAm5x86: + strcat(name,"AMD Am5x86 processor"); + break; + case CPU_AMDK5: + strcat(name,"AMD K5 processor"); + break; + case CPU_AMDK6: + strcat(name,"AMD K6 processor"); + break; + case CPU_AMDK6_2: + strcat(name,"AMD K6-2 processor"); + break; + case CPU_AMDK6_III: + strcat(name,"AMD K6-III processor"); + break; + case CPU_AMDK6_2plus: + strcat(name,"AMD K6-2+ processor"); + break; + case CPU_AMDK6_IIIplus: + strcat(name,"AMD K6-III+ processor"); + break; + case CPU_UnkAMD: + strcat(name,"Unknown AMD processor"); + break; + case CPU_AMDAthlon: + strcat(name,"AMD Athlon processor"); + break; + case CPU_AMDDuron: + strcat(name,"AMD Duron processor"); + break; + case CPU_WinChipC6: + strcat(name,"IDT WinChip C6 processor"); + break; + case CPU_WinChip2: + strcat(name,"IDT WinChip 2 processor"); + break; + case CPU_UnkIDT: + strcat(name,"Unknown IDT processor"); + break; + default: + strcat(name,"Unknown processor"); + } + if (CPU_haveMMX()) + strcat(name," with MMX(R)"); + if (CPU_have3DNow()) + strcat(name,", 3DNow!(R)"); + if (CPU_haveSSE()) + strcat(name,", SSE(R)"); + return name; +#else + return "Unknown"; +#endif +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/debug.c b/board/MAI/bios_emulator/scitech/src/pm/debug.c new file mode 100644 index 000000000..751bf098f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/debug.c @@ -0,0 +1,107 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Main module containing debug checking features. +* +****************************************************************************/ + +#include "pmapi.h" +#ifdef __WIN32_VXD__ +#include "vxdfile.h" +#elif defined(__NT_DRIVER__) +#include "ntdriver.h" +#elif defined(__OS2_VDD__) +#include "vddfile.h" +#else +#include +#include +#include +#endif + +/*---------------------------- Global variables ---------------------------*/ + +/* {secret} */ +void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line) = _CHK_defaultFail; +static char logFile[256] = ""; + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef CHECKED +void _CHK_defaultFail( + int fatal, + const char *msg, + const char *cond, + const char *file, + int line) +{ + FILE *f; + char buf[256]; + + if (logFile[0] == 0) { + strcpy(logFile,PM_getNucleusPath()); + PM_backslash(logFile); + strcat(logFile,"scitech.log"); + } + if ((f = fopen(logFile,"a+")) != NULL) { +#if defined(__WIN32_VXD__) || defined(__OS2_VDD__) || defined(__NT_DRIVER__) + sprintf(buf,msg,cond,file,line); + fwrite(buf,1,strlen(buf),f); +#else + fprintf(f,msg,cond,file,line); +#endif + fclose(f); + } + if (fatal) { + sprintf(buf,"Check failed: check '%s' for details", logFile); + PM_fatalError(buf); + } +} +#endif + +/**************************************************************************** +DESCRIPTION: +Sets the location of the debug log file. + +HEADER: +pmapi.h + +PARAMETERS: +logFilePath - Full file and path name to debug log file. + +REMARKS: +Sets the name and location of the debug log file. The debug log file is +created and written to when runtime checks, warnings and failure conditions +are logged to disk when code is compiled in CHECKED mode. By default the +log file is called 'scitech.log' and goes into the current SciTech Nucleus +path for the application. You can use this function to set the filename +and location of the debug log file to your own application specific +directory. +****************************************************************************/ +void PMAPI PM_setDebugLog( + const char *logFilePath) +{ + strcpy(logFile,logFilePath); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm new file mode 100644 index 000000000..36dcaab67 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_event.asm @@ -0,0 +1,194 @@ +;**************************************************************************** +;* +;* SciTech Multi-platform Graphics Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler +;* Environment: IBM PC (MS DOS) +;* +;* Description: Assembly language support routines for the event module. +;* +;**************************************************************************** + + ideal + +include "scitech.mac" ; Memory model macros + +ifdef flatmodel + +header _event ; Set up memory model + +begdataseg _event + + cextern _EVT_biosPtr,DPTR + +ifdef USE_NASM +%define KB_HEAD WORD esi+01Ah ; Keyboard buffer head in BIOS data area +%define KB_TAIL WORD esi+01Ch ; Keyboard buffer tail in BIOS data area +%define KB_START WORD esi+080h ; Start of keyboard buffer in BIOS data area +%define KB_END WORD esi+082h ; End of keyboard buffer in BIOS data area +else +KB_HEAD EQU WORD esi+01Ah ; Keyboard buffer head in BIOS data area +KB_TAIL EQU WORD esi+01Ch ; Keyboard buffer tail in BIOS data area +KB_START EQU WORD esi+080h ; Start of keyboard buffer in BIOS data area +KB_END EQU WORD esi+082h ; End of keyboard buffer in BIOS data area +endif + +enddataseg _event + +begcodeseg _event ; Start of code segment + + cpublic _EVT_codeStart + +;---------------------------------------------------------------------------- +; int _EVT_getKeyCode(void) +;---------------------------------------------------------------------------- +; Returns the key code for the next available key by extracting it from +; the BIOS keyboard buffer. +;---------------------------------------------------------------------------- +cprocstart _EVT_getKeyCode + + enter_c + + mov esi,[_EVT_biosPtr] + xor ebx,ebx + xor eax,eax + mov bx,[KB_HEAD] + cmp bx,[KB_TAIL] + jz @@Done + xor eax,eax + mov ax,[esi+ebx] ; EAX := character from keyboard buffer + inc _bx + inc _bx + cmp bx,[KB_END] ; Hit the end of the keyboard buffer? + jl @@1 + mov bx,[KB_START] +@@1: mov [KB_HEAD],bx ; Update keyboard buffer head pointer + +@@Done: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _EVT_pumpMessages(void) +;---------------------------------------------------------------------------- +; This function would normally do nothing, however due to strange bugs +; in the Windows 3.1 and OS/2 DOS boxes, we don't get any hardware keyboard +; interrupts unless we periodically call the BIOS keyboard functions. Hence +; this function gets called every time that we check for events, and works +; around this problem (in essence it tells the DOS VDM to pump the +; keyboard events to our program ;-). +; +; Note that this bug is not present under Win 9x DOS boxes. +;---------------------------------------------------------------------------- +cprocstart _EVT_pumpMessages + + mov ah,11h ; Function - Check keyboard status + int 16h ; Call BIOS + + mov ax, 0Bh ; Reset Move Mouse + int 33h + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _EVT_disableInt(void); +;---------------------------------------------------------------------------- +; Return processor interrupt status and disable interrupts. +;---------------------------------------------------------------------------- +cprocstart _EVT_disableInt + + pushf ; Put flag word on stack + cli ; Disable interrupts! + pop eax ; deposit flag word in return register + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _EVT_restoreInt(int ps); +;---------------------------------------------------------------------------- +; Restore processor interrupt status. +;---------------------------------------------------------------------------- +cprocstart _EVT_restoreInt + + ARG ps:UINT + + push ebp + mov ebp,esp ; Set up stack frame + push [DWORD ps] + popf ; Restore processor status (and interrupts) + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; int EVT_rdinx(int port,int index) +;---------------------------------------------------------------------------- +; Reads an indexed register value from an I/O port. +;---------------------------------------------------------------------------- +cprocstart EVT_rdinx + + ARG port:UINT, index:UINT + + push ebp + mov ebp,esp + mov edx,[port] + mov al,[BYTE index] + out dx,al + inc dx + in al,dx + movzx eax,al + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void EVT_wrinx(int port,int index,int value) +;---------------------------------------------------------------------------- +; Writes an indexed register value to an I/O port. +;---------------------------------------------------------------------------- +cprocstart EVT_wrinx + + ARG port:UINT, index:UINT, value:UINT + + push ebp + mov ebp,esp + mov edx,[port] + mov al,[BYTE index] + mov ah,[BYTE value] + out dx,ax + pop ebp + ret + +cprocend + + cpublic _EVT_codeEnd + +endcodeseg _event + +endif + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm new file mode 100644 index 000000000..a4a9c7916 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_lztimer.asm @@ -0,0 +1,438 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NASM or TASM Assembler +;* Environment: IBM PC (MS DOS) +;* +;* Description: Uses the 8253 timer and the BIOS time-of-day count to time +;* the performance of code that takes less than an hour to +;* execute. +;* +;* The routines in this package only works with interrupts +;* enabled, and in fact will explicitly turn interrupts on +;* in order to ensure we get accurate results from the timer. +;* +;* Externally 'C' callable routines: +;* +;* LZ_timerOn: Saves the BIOS time of day count and starts the +;* long period Zen Timer. +;* +;* LZ_timerLap: Latches the current count, and keeps the timer running +;* +;* LZ_timerOff: Stops the long-period Zen Timer and saves the timer +;* count and the BIOS time of day count. +;* +;* LZ_timerCount: Returns an unsigned long representing the timed count +;* in microseconds. If more than an hour passed during +;* the timing interval, LZ_timerCount will return the +;* value 0xFFFFFFFF (an invalid count). +;* +;* Note: If either more than an hour passes between calls to LZ_timerOn +;* and LZ_timerOff, an error is reported. For timing code that takes +;* more than a few minutes to execute, use the low resolution +;* Ultra Long Period Zen Timer code, which should be accurate +;* enough for most purposes. +;* +;* Note: Each block of code being timed should ideally be run several +;* times, with at least two similar readings required to +;* establish a true measurement, in order to eliminate any +;* variability caused by interrupts. +;* +;* Note: Interrupts must not be disabled for more than 54 ms at a +;* stretch during the timing interval. Because interrupts are +;* enabled, key, mice, and other devices that generate interrupts +;* should not be used during the timing interval. +;* +;* Note: Any extra code running off the timer interrupt (such as +;* some memory resident utilities) will increase the time +;* measured by the Zen Timer. +;* +;* Note: These routines can introduce inaccuracies of up to a few +;* tenths of a second into the system clock count for each +;* code section being timed. Consequently, it's a good idea to +;* reboot at the conclusion of timing sessions. (The +;* battery-backed clock, if any, is not affected by the Zen +;* timer.) +;* +;* All registers and all flags are preserved by all routines, except +;* interrupts which are always turned on +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" + +;**************************************************************************** +; +; Equates used by long period Zen Timer +; +;**************************************************************************** + +; Base address of 8253 timer chip + +BASE_8253 equ 40h + +; The address of the timer 0 count registers in the 8253 + +TIMER_0_8253 equ BASE_8253 + 0 + +; The address of the mode register in the 8253 + +MODE_8253 equ BASE_8253 + 3 + +; The address of the BIOS timer count variable in the BIOS data area. + +TIMER_COUNT equ 6Ch + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +endif + +header _lztimer + +begdataseg _lztimer + + cextern _ZTimerBIOSPtr,DPTR + +StartBIOSCount dd 0 ; Starting BIOS count dword +EndBIOSCount dd 0 ; Ending BIOS count dword +EndTimedCount dw 0 ; Timer 0 count at the end of timing period + +enddataseg _lztimer + +begcodeseg _lztimer ; Start of code segment + +;---------------------------------------------------------------------------- +; void LZ_timerOn(void); +;---------------------------------------------------------------------------- +; Starts the Long period Zen timer counting. +;---------------------------------------------------------------------------- +cprocstart LZ_timerOn + +; Set the timer 0 of the 8253 to mode 2 (divide-by-N), to cause +; linear counting rather than count-by-two counting. Also stops +; timer 0 until the timer count is loaded, except on PS/2 computers. + + mov al,00110100b ; mode 2 + out MODE_8253,al + +; Set the timer count to 0, so we know we won't get another timer +; interrupt right away. Note: this introduces an inaccuracy of up to 54 ms +; in the system clock count each time it is executed. + + DELAY + sub al,al + out TIMER_0_8253,al ; lsb + DELAY + out TIMER_0_8253,al ; msb + +; Store the timing start BIOS count + + use_es +ifdef flatmodel + mov ebx,[_ZTimerBIOSPtr] +else + les bx,[_ZTimerBIOSPtr] +endif + cli ; No interrupts while we grab the count + mov eax,[_ES _bx+TIMER_COUNT] + sti + mov [StartBIOSCount],eax + unuse_es + +; Set the timer count to 0 again to start the timing interval. + + mov al,00110100b ; set up to load initial + out MODE_8253,al ; timer count + DELAY + sub al,al + out TIMER_0_8253,al ; load count lsb + DELAY + out TIMER_0_8253,al ; load count msb + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void LZ_timerOff(void); +;---------------------------------------------------------------------------- +; Stops the long period Zen timer and saves count. +;---------------------------------------------------------------------------- +cprocstart LZ_timerOff + +; Latch the timer count. + + mov al,00000000b ; latch timer 0 + out MODE_8253,al + cli ; Stop the BIOS count + +; Read the BIOS count. (Since interrupts are disabled, the BIOS +; count won't change). + + use_es +ifdef flatmodel + mov ebx,[_ZTimerBIOSPtr] +else + les bx,[_ZTimerBIOSPtr] +endif + mov eax,[_ES _bx+TIMER_COUNT] + mov [EndBIOSCount],eax + unuse_es + +; Read out the count we latched earlier. + + in al,TIMER_0_8253 ; least significant byte + DELAY + mov ah,al + in al,TIMER_0_8253 ; most significant byte + xchg ah,al + neg ax ; Convert from countdown remaining + ; to elapsed count + mov [EndTimedCount],ax + sti ; Let the BIOS count continue + + ret + +cprocend + +;---------------------------------------------------------------------------- +; unsigned long LZ_timerLap(void) +;---------------------------------------------------------------------------- +; Latches the current count and converts it to a microsecond timing value, +; but leaves the timer still running. We dont check for and overflow, +; where the time has gone over an hour in this routine, since we want it +; to execute as fast as possible. +;---------------------------------------------------------------------------- +cprocstart LZ_timerLap + + push ebx ; Save EBX for 32 bit code + +; Latch the timer count. + + mov al,00000000b ; latch timer 0 + out MODE_8253,al + cli ; Stop the BIOS count + +; Read the BIOS count. (Since interrupts are disabled, the BIOS +; count wont change). + + use_es +ifdef flatmodel + mov ebx,[_ZTimerBIOSPtr] +else + les bx,[_ZTimerBIOSPtr] +endif + mov eax,[_ES _bx+TIMER_COUNT] + mov [EndBIOSCount],eax + unuse_es + +; Read out the count we latched earlier. + + in al,TIMER_0_8253 ; least significant byte + DELAY + mov ah,al + in al,TIMER_0_8253 ; most significant byte + xchg ah,al + neg ax ; Convert from countdown remaining + ; to elapsed count + mov [EndTimedCount],ax + sti ; Let the BIOS count continue + +; See if a midnight boundary has passed and adjust the finishing BIOS +; count by the number of ticks in 24 hours. We wont be able to detect +; more than 24 hours, but at least we can time across a midnight +; boundary + + mov eax,[EndBIOSCount] ; Is end < start? + cmp eax,[StartBIOSCount] + jae @@CalcBIOSTime ; No, calculate the time taken + +; Adjust the finishing time by adding the number of ticks in 24 hours +; (1573040). + + add [DWORD EndBIOSCount],1800B0h + +; Convert the BIOS time to microseconds + +@@CalcBIOSTime: + mov ax,[WORD EndBIOSCount] + sub ax,[WORD StartBIOSCount] + mov dx,54925 ; Number of microseconds each + ; BIOS count represents. + mul dx + mov bx,ax ; set aside BIOS count in + mov cx,dx ; microseconds + +; Convert timer count to microseconds + + push _si + mov ax,[EndTimedCount] + mov si,8381 + mul si + mov si,10000 + div si ; * 0.8381 = * 8381 / 10000 + pop _si + +; Add the timer and BIOS counts together to get an overall time in +; microseconds. + + add ax,bx + adc cx,0 +ifdef flatmodel + shl ecx,16 + mov cx,ax + mov eax,ecx ; EAX := timer count +else + mov dx,cx +endif + pop ebx ; Restore EBX for 32 bit code + ret + +cprocend + +;---------------------------------------------------------------------------- +; unsigned long LZ_timerCount(void); +;---------------------------------------------------------------------------- +; Returns an unsigned long representing the net time in microseconds. +; +; If an hour has passed while timing, we return 0xFFFFFFFF as the count +; (which is not a possible count in itself). +;---------------------------------------------------------------------------- +cprocstart LZ_timerCount + + push ebx ; Save EBX for 32 bit code + +; See if a midnight boundary has passed and adjust the finishing BIOS +; count by the number of ticks in 24 hours. We wont be able to detect +; more than 24 hours, but at least we can time across a midnight +; boundary + + mov eax,[EndBIOSCount] ; Is end < start? + cmp eax,[StartBIOSCount] + jae @@CheckForHour ; No, check for hour passing + +; Adjust the finishing time by adding the number of ticks in 24 hours +; (1573040). + + add [DWORD EndBIOSCount],1800B0h + +; See if more than an hour passed during timing. If so, notify the user. + +@@CheckForHour: + mov ax,[WORD StartBIOSCount+2] + cmp ax,[WORD EndBIOSCount+2] + jz @@CalcBIOSTime ; Hour count didn't change, so + ; everything is fine + + inc ax + cmp ax,[WORD EndBIOSCount+2] + jnz @@TestTooLong ; Two hour boundaries passed, so the + ; results are no good + mov ax,[WORD EndBIOSCount] + cmp ax,[WORD StartBIOSCount] + jb @@CalcBIOSTime ; a single hour boundary passed. That's + ; OK, so long as the total time wasn't + ; more than an hour. + +; Over an hour elapsed passed during timing, which renders +; the results invalid. Notify the user. This misses the case where a +; multiple of 24 hours has passed, but we'll rely on the perspicacity of +; the user to detect that case :-). + +@@TestTooLong: +ifdef flatmodel + mov eax,0FFFFFFFFh +else + mov ax,0FFFFh + mov dx,0FFFFh +endif + jmp short @@Done + +; Convert the BIOS time to microseconds + +@@CalcBIOSTime: + mov ax,[WORD EndBIOSCount] + sub ax,[WORD StartBIOSCount] + mov dx,54925 ; Number of microseconds each + ; BIOS count represents. + mul dx + mov bx,ax ; set aside BIOS count in + mov cx,dx ; microseconds + +; Convert timer count to microseconds + + push _si + mov ax,[EndTimedCount] + mov si,8381 + mul si + mov si,10000 + div si ; * 0.8381 = * 8381 / 10000 + pop _si + +; Add the timer and BIOS counts together to get an overall time in +; microseconds. + + add ax,bx + adc cx,0 +ifdef flatmodel + shl ecx,16 + mov cx,ax + mov eax,ecx ; EAX := timer count +else + mov dx,cx +endif + +@@Done: pop ebx ; Restore EBX for 32 bit code + ret + +cprocend + +cprocstart LZ_disable + cli + ret +cprocend + +cprocstart LZ_enable + sti + ret +cprocend + +endcodeseg _lztimer + + END diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm new file mode 100644 index 000000000..42b5cf369 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_pm.asm @@ -0,0 +1,656 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: IBM PC Real mode and 16/32 bit protected mode +;* +;* Description: Low level assembly support for the PM library specific to +;* MSDOS. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pmdos ; Set up memory model + +begdataseg _pmdos + +ifndef flatmodel + +struc rmregs_s +ax dw ? +ax_high dw ? +bx dw ? +bx_high dw ? +cx dw ? +cx_high dw ? +dx dw ? +dx_high dw ? +si dw ? +si_high dw ? +di dw ? +di_high dw ? +cflag dw ? +cflag_high dw ? +ends rmregs_s +RMREGS = (rmregs_s PTR es:bx) + +struc rmsregs_s +es dw ? +cs dw ? +ss dw ? +ds dw ? +ends rmsregs_s +RMSREGS = (rmsregs_s PTR es:bx) + +endif ; !flatmodel + +ifdef flatmodel + cextern _PM_savedDS,USHORT + cextern _PM_VXD_off,UINT + cextern _PM_VXD_sel,UINT +ifdef DOS4GW + cextern _PM_haveCauseWay,UINT +endif +endif +intel_id db "GenuineIntel" ; Intel vendor ID + +PMHELP_GETPDB EQU 0026h +PMHELP_FLUSHTLB EQU 0027h + +enddataseg _pmdos + +P586 + +begcodeseg _pmdos ; Start of code segment + +ifndef flatmodel + +;---------------------------------------------------------------------------- +; void PM_callRealMode(unsigned s,unsigned o, RMREGS *regs, +; RMSREGS *sregs) +;---------------------------------------------------------------------------- +; Calls a real mode procedure, loading the appropriate registers values +; from the passed in structures. Only the DS and ES register are loaded +; from the SREGS structure. +;---------------------------------------------------------------------------- +cprocstart PM_callRealMode + + ARG s:WORD, o:WORD, regs:DWORD, sregs:DWORD + + LOCAL addr:DWORD, bxVal:WORD, esVal:WORD, flags:WORD = LocalSize + + enter_c + push ds + push es + + mov ax,[o] ; Build the address to call in 'addr' + mov [WORD addr],ax + mov ax,[s] + mov [WORD addr+2],ax + + les bx,[sregs] + mov ax,[RMSREGS.ds] + mov ds,ax ; DS := passed in value + mov ax,[RMSREGS.es] + mov [esVal],ax + les bx,[regs] + mov ax,[RMREGS.bx] + mov [bxVal],ax + mov ax,[RMREGS.ax] ; AX := passed in value + mov cx,[RMREGS.cx] ; CX := passed in value + mov dx,[RMREGS.dx] ; DX := passed in value + mov si,[RMREGS.si] ; SI := passed in value + mov di,[RMREGS.di] ; DI := passed in value + push bp + push [esVal] + pop es ; ES := passed in value + mov bx,[bxVal] ; BX := passed in value + + call [addr] ; Call the specified routine + + pushf ; Save flags for later + pop [flags] + + pop bp + push es + pop [esVal] + push bx + pop [bxVal] + les bx,[sregs] + push ds + pop [RMSREGS.ds] ; Save value of DS + push [esVal] + pop [RMSREGS.es] ; Save value of ES + les bx,[regs] + mov [RMREGS.ax],ax ; Save value of AX + mov [RMREGS.cx],cx ; Save value of CX + mov [RMREGS.dx],dx ; Save value of DX + mov [RMREGS.si],si ; Save value of SI + mov [RMREGS.di],di ; Save value of DI + mov ax,[flags] ; Return flags + and ax,1h ; Isolate carry flag + mov [RMREGS.cflag],ax ; Save carry flag status + mov ax,[bxVal] + mov [RMREGS.bx],ax ; Save value of BX + + pop es + pop ds + leave_c + ret + +cprocend + +endif + +;---------------------------------------------------------------------------- +; void PM_segread(PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Read the current value of all segment registers +;---------------------------------------------------------------------------- +cprocstartdll16 PM_segread + + ARG sregs:DPTR + + enter_c + + mov ax,es + _les _si,[sregs] + mov [_ES _si],ax + mov [_ES _si+2],cs + mov [_ES _si+4],ss + mov [_ES _si+6],ds + mov [_ES _si+8],fs + mov [_ES _si+10],gs + + leave_c + ret + +cprocend + +; Create a table of the 256 different interrupt calls that we can jump +; into + +ifdef USE_NASM + +%assign intno 0 + +intTable: +%rep 256 + db 0CDh + db intno +%assign intno intno + 1 + ret + nop +%endrep + +else + +intno = 0 + +intTable: + REPT 256 + db 0CDh + db intno +intno = intno + 1 + ret + nop + ENDM + +endif + +;---------------------------------------------------------------------------- +; _PM_genInt - Generate the appropriate interrupt +;---------------------------------------------------------------------------- +cprocnear _PM_genInt + + push _ax ; Save _ax + push _bx ; Save _bx +ifdef flatmodel + mov ebx,[UINT esp+12] ; EBX := interrupt number +else + mov bx,sp ; Make sure ESP is zeroed + mov bx,[UINT ss:bx+6] ; BX := interrupt number +endif + mov _ax,offset intTable ; Point to interrupt generation table + shl _bx,2 ; _BX := index into table + add _ax,_bx ; _AX := pointer to interrupt code +ifdef flatmodel + xchg eax,[esp+4] ; Restore eax, and set for int +else + mov bx,sp + xchg ax,[ss:bx+2] ; Restore ax, and set for int +endif + pop _bx ; restore _bx + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Issues a software interrupt in protected mode. This routine has been +; written to allow user programs to load CS and DS with different values +; other than the default. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_int386x + + ARG intno:UINT, inptr:DPTR, outptr:DPTR, sregs:DPTR + + LOCAL flags:UINT, sv_ds:UINT, sv_esi:ULONG = LocalSize + + enter_c + push ds + push es ; Save segment registers + push fs + push gs + + _lds _si,[sregs] ; DS:_SI -> Load segment registers + mov es,[_si] + mov bx,[_si+6] + mov [sv_ds],_bx ; Save value of user DS on stack + mov fs,[_si+8] + mov gs,[_si+10] + + _lds _si,[inptr] ; Load CPU registers + mov eax,[_si] + mov ebx,[_si+4] + mov ecx,[_si+8] + mov edx,[_si+12] + mov edi,[_si+20] + mov esi,[_si+16] + + push ds ; Save value of DS + push _bp ; Some interrupts trash this! + clc ; Generate the interrupt + push [UINT intno] + mov ds,[WORD sv_ds] ; Set value of user's DS selector + call _PM_genInt + pop _bp ; Pop intno from stack (flags unchanged) + pop _bp ; Restore value of stack frame pointer + pop ds ; Restore value of DS + + pushf ; Save flags for later + pop [UINT flags] + push esi ; Save ESI for later + pop [DWORD sv_esi] + push ds ; Save DS for later + pop [UINT sv_ds] + + _lds _si,[outptr] ; Save CPU registers + mov [_si],eax + mov [_si+4],ebx + mov [_si+8],ecx + mov [_si+12],edx + push [DWORD sv_esi] + pop [DWORD _si+16] + mov [_si+20],edi + + mov _bx,[flags] ; Return flags + and ebx,1h ; Isolate carry flag + mov [_si+24],ebx ; Save carry flag status + + _lds _si,[sregs] ; Save segment registers + mov [_si],es + mov _bx,[sv_ds] + mov [_si+6],bx ; Get returned DS from stack + mov [_si+8],fs + mov [_si+10],gs + + pop gs ; Restore segment registers + pop fs + pop es + pop ds + leave_c + ret + +cprocend + +ifndef flatmodel +_PM_savedDS dw _DATA ; Saved value of DS +endif + +;---------------------------------------------------------------------------- +; void PM_saveDS(void) +;---------------------------------------------------------------------------- +; Save the value of DS into a section of the code segment, so that we can +; quickly load this value at a later date in the PM_loadDS() routine from +; inside interrupt handlers etc. The method to do this is different +; depending on the DOS extender being used. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_saveDS + +ifdef flatmodel + mov [_PM_savedDS],ds ; Store away in data segment +endif + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_loadDS(void) +;---------------------------------------------------------------------------- +; Routine to load the DS register with the default value for the current +; DOS extender. Only the DS register is loaded, not the ES register, so +; if you wish to call C code, you will need to also load the ES register +; in 32 bit protected mode. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_loadDS + + mov ds,[cs:_PM_savedDS] ; We can access the proper DS through CS + ret + +cprocend + +ifdef flatmodel + +;---------------------------------------------------------------------------- +; ibool DPMI_allocateCallback(void (*pmcode)(), void *rmregs, long *RMCB) +;---------------------------------------------------------------------------- +cprocstart _DPMI_allocateCallback + + ARG pmcode:CPTR, rmregs:DPTR, RMCB:DPTR + + enter_c + push ds + push es + + push cs + pop ds + mov esi,[pmcode] ; DS:ESI -> protected mode code to call + mov edi,[rmregs] ; ES:EDI -> real mode register buffer + mov ax,303h ; AX := allocate realmode callback function + int 31h + mov eax,0 ; Return failure! + jc @@Fail + + mov eax,[RMCB] + shl ecx,16 + mov cx,dx + mov [es:eax],ecx ; Return real mode address + mov eax,1 ; Return success! + +@@Fail: pop es + pop ds + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void DPMI_freeCallback(long RMCB) +;---------------------------------------------------------------------------- +cprocstart _DPMI_freeCallback + + ARG RMCB:ULONG + + enter_c + + mov cx,[WORD RMCB+2] + mov dx,[WORD RMCB] ; CX:DX := real mode callback + mov ax,304h + int 31h + + leave_c + ret + +cprocend + +endif + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; uchar _PM_readCMOS(int index) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_readCMOS + + ARG index:UINT + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + in al,71h + mov ah,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + sti + mov al,ah ; Return value in AL + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_writeCMOS(int index,uchar value) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_writeCMOS + + ARG index:UINT, value:UCHAR + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + mov al,[value] + out 71h,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + sti + popfd + pop _bp + ret + +cprocend + +ifdef flatmodel + +;---------------------------------------------------------------------------- +; int _PM_pagingEnabled(void) +;---------------------------------------------------------------------------- +; Returns 1 if paging is enabled, 0 if not or -1 if not at ring 0 +;---------------------------------------------------------------------------- +cprocstart _PM_pagingEnabled + + mov eax,-1 +ifdef DOS4GW + mov cx,cs + and ecx,3 + jz @@Ring0 + cmp [UINT _PM_haveCauseWay],0 + jnz @@Ring0 + jmp @@Exit + +@@Ring0: + mov eax,cr0 ; Load CR0 + shr eax,31 ; Isolate paging enabled bit +endif +@@Exit: ret + +cprocend + +;---------------------------------------------------------------------------- +; _PM_getPDB - Return the Page Table Directory Base address +;---------------------------------------------------------------------------- +cprocstart _PM_getPDB + +ifdef DOS4GW + mov ax,cs + and eax,3 + jz @@Ring0 + cmp [UINT _PM_haveCauseWay],0 + jnz @@Ring0 +endif + +; Call VxD if running at ring 3 in a DOS box + + cmp [WORD _PM_VXD_sel],0 + jz @@Fail + mov eax,PMHELP_GETPDB +ifdef USE_NASM + call far dword [_PM_VXD_off] +else + call [FCPTR _PM_VXD_off] +endif + ret + +@@Ring0: +ifdef DOS4GW + mov eax,cr3 + and eax,0FFFFF000h + ret +endif +@@Fail: xor eax,eax + ret + +cprocend + +;---------------------------------------------------------------------------- +; PM_flushTLB - Flush the Translation Lookaside buffer +;---------------------------------------------------------------------------- +cprocstart PM_flushTLB + + mov ax,cs + and eax,3 + jz @@Ring0 +ifdef DOS4GW + cmp [UINT _PM_haveCauseWay],0 + jnz @@Ring0 +endif + +; Call VxD if running at ring 3 in a DOS box + + cmp [WORD _PM_VXD_sel],0 + jz @@Fail + mov eax,PMHELP_FLUSHTLB +ifdef USE_NASM + call far dword [_PM_VXD_off] +else + call [FCPTR _PM_VXD_off] +endif + ret + +@@Ring0: +ifdef DOS4GW + wbinvd ; Flush the CPU cache + mov eax,cr3 + mov cr3,eax ; Flush the TLB +endif +@@Fail: ret + +cprocend + +endif + +;---------------------------------------------------------------------------- +; void _PM_VxDCall(VXD_regs far *r,uint off,uint sel); +;---------------------------------------------------------------------------- +cprocstart _PM_VxDCall + + ARG r:DPTR, off:UINT, sel:UINT + + enter_c + +; Load all registers from the registers structure + + mov ebx,[r] + mov eax,[ebx+0] + mov ecx,[ebx+8] + mov edx,[ebx+12] + mov esi,[ebx+16] + mov edi,[ebx+20] + mov ebx,[ebx+4] ; Trashes BX structure pointer! + +; Call the VxD entry point (on stack) + +ifdef USE_NASM + call far dword [off] +else + call [FCPTR off] +endif + +; Save all registers back in the structure + + push ebx ; Push EBX onto stack for later + mov ebx,[r] + mov [ebx+0],eax + mov [ebx+8],ecx + mov [ebx+12],edx + mov [ebx+16],esi + mov [ebx+20],edi + pop [DWORD ebx+4] ; Save value of EBX from stack + + leave_c + ret + +cprocend + +endcodeseg _pmdos + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm new file mode 100644 index 000000000..5c741f346 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_pmdos.asm @@ -0,0 +1,1105 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: IBM PC Real mode and 16/32 bit protected mode +;* +;* Description: Low level assembly support for the PM library specific to +;* MSDOS interrupt handling. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pmdos ; Set up memory model + +; Define the size of our local stacks. For real mode code they cant be +; that big, but for 32 bit protected mode code we can make them nice and +; large so that complex C functions can be used. + +ifdef flatmodel +MOUSE_STACK EQU 4096 +TIMER_STACK EQU 4096 +KEY_STACK EQU 1024 +INT10_STACK EQU 1024 +IRQ_STACK EQU 1024 +else +MOUSE_STACK EQU 1024 +TIMER_STACK EQU 512 +KEY_STACK EQU 256 +INT10_STACK EQU 256 +IRQ_STACK EQU 256 +endif + +ifdef USE_NASM + +; Macro to load DS and ES registers with correct value. + +%imacro LOAD_DS 0 +%ifdef flatmodel + mov ds,[cs:_PM_savedDS] + mov es,[cs:_PM_savedDS] +%else + push ax + mov ax,_DATA + mov ds,ax + pop ax +%endif +%endmacro + +; Note that interrupts we disable interrupts during the following stack +; %imacro for correct operation, but we do not enable them again. Normally +; these %imacros are used within interrupt handlers so interrupts should +; already be off. We turn them back on explicitly later if the user code +; needs them to be back on. + +; Macro to switch to a new local stack. + +%imacro NEWSTK 1 + cli + mov [seg_%1],ss + mov [ptr_%1],_sp + mov [TempSeg],ds + mov ss,[TempSeg] + mov _sp,offset %1 +%endmacro + +; %imacro to switch back to the old stack. + +%imacro RESTSTK 1 + cli + mov ss,[seg_%1] + mov _sp,[ptr_%1] +%endmacro + +; %imacro to swap the current stack with the one saved away. + +%imacro SWAPSTK 1 + cli + mov ax,ss + xchg ax,[seg_%1] + mov ss,ax + xchg _sp,[ptr_%1] +%endmacro + +else + +; Macro to load DS and ES registers with correct value. + +MACRO LOAD_DS +ifdef flatmodel + mov ds,[cs:_PM_savedDS] + mov es,[cs:_PM_savedDS] +else + push ax + mov ax,_DATA + mov ds,ax + pop ax +endif +ENDM + +; Note that interrupts we disable interrupts during the following stack +; macro for correct operation, but we do not enable them again. Normally +; these macros are used within interrupt handlers so interrupts should +; already be off. We turn them back on explicitly later if the user code +; needs them to be back on. + +; Macro to switch to a new local stack. + +MACRO NEWSTK stkname + cli + mov [seg_&stkname&],ss + mov [ptr_&stkname&],_sp + mov [TempSeg],ds + mov ss,[TempSeg] + mov _sp,offset stkname +ENDM + +; Macro to switch back to the old stack. + +MACRO RESTSTK stkname + cli + mov ss,[seg_&stkname&] + mov _sp,[ptr_&stkname&] +ENDM + +; Macro to swap the current stack with the one saved away. + +MACRO SWAPSTK stkname + cli + mov ax,ss + xchg ax,[seg_&stkname&] + mov ss,ax + xchg _sp,[ptr_&stkname&] +ENDM + +endif + +begdataseg _pmdos + +ifdef flatmodel + cextern _PM_savedDS,USHORT +endif + cextern _PM_critHandler,CPTR + cextern _PM_breakHandler,CPTR + cextern _PM_timerHandler,CPTR + cextern _PM_rtcHandler,CPTR + cextern _PM_keyHandler,CPTR + cextern _PM_key15Handler,CPTR + cextern _PM_mouseHandler,CPTR + cextern _PM_int10Handler,CPTR + + cextern _PM_ctrlCPtr,DPTR + cextern _PM_ctrlBPtr,DPTR + cextern _PM_critPtr,DPTR + + cextern _PM_prevTimer,FCPTR + cextern _PM_prevRTC,FCPTR + cextern _PM_prevKey,FCPTR + cextern _PM_prevKey15,FCPTR + cextern _PM_prevBreak,FCPTR + cextern _PM_prevCtrlC,FCPTR + cextern _PM_prevCritical,FCPTR + cextern _PM_prevRealTimer,ULONG + cextern _PM_prevRealRTC,ULONG + cextern _PM_prevRealKey,ULONG + cextern _PM_prevRealKey15,ULONG + cextern _PM_prevRealInt10,ULONG + +cpublic _PM_pmdosDataStart + +; Allocate space for all of the local stacks that we need. These stacks +; are not very large, but should be large enough for most purposes +; (generally you want to handle these interrupts quickly, simply storing +; the information for later and then returning). If you need bigger +; stacks then change the appropriate value in here. + + ALIGN 4 + dclb MOUSE_STACK ; Space for local stack (small) +MsStack: ; Stack starts at end! +ptr_MsStack DUINT 0 ; Place to store old stack offset +seg_MsStack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb INT10_STACK ; Space for local stack (small) +Int10Stack: ; Stack starts at end! +ptr_Int10Stack DUINT 0 ; Place to store old stack offset +seg_Int10Stack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb TIMER_STACK ; Space for local stack (small) +TmStack: ; Stack starts at end! +ptr_TmStack DUINT 0 ; Place to store old stack offset +seg_TmStack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb TIMER_STACK ; Space for local stack (small) +RtcStack: ; Stack starts at end! +ptr_RtcStack DUINT 0 ; Place to store old stack offset +seg_RtcStack dw 0 ; Place to store old stack segment +RtcInside dw 0 ; Are we still handling current interrupt + + ALIGN 4 + dclb KEY_STACK ; Space for local stack (small) +KyStack: ; Stack starts at end! +ptr_KyStack DUINT 0 ; Place to store old stack offset +seg_KyStack dw 0 ; Place to store old stack segment +KyInside dw 0 ; Are we still handling current interrupt + + ALIGN 4 + dclb KEY_STACK ; Space for local stack (small) +Ky15Stack: ; Stack starts at end! +ptr_Ky15Stack DUINT 0 ; Place to store old stack offset +seg_Ky15Stack dw 0 ; Place to store old stack segment + +TempSeg dw 0 ; Place to store stack segment + +cpublic _PM_pmdosDataEnd + +enddataseg _pmdos + +begcodeseg _pmdos ; Start of code segment + +cpublic _PM_pmdosCodeStart + +;---------------------------------------------------------------------------- +; PM_mouseISR - Mouse interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Interrupt subroutine called by the mouse driver upon interrupts, to +; dispatch control to high level C based subroutines. Interrupts are on +; when we call the user code. +; +; It is _extremely_ important to save the state of the extended registers +; as these may well be trashed by the routines called from here and not +; restored correctly by the mouse interface module. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. For mouse handlers this is not a +; problem, as the mouse driver arbitrates calls to the user mouse +; handler for us. +; +; Entry: AX - Condition mask giving reason for call +; BX - Mouse button state +; CX - Horizontal cursor coordinate +; DX - Vertical cursor coordinate +; SI - Horizontal mickey value +; DI - Vertical mickey value +; +;---------------------------------------------------------------------------- +ifdef DJGPP +cprocstart _PM_mouseISR +else +cprocfar _PM_mouseISR +endif + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + NEWSTK MsStack ; Switch to local stack + +; Call the installed high level C code routine + + clrhi dx ; Clear out high order values + clrhi cx + clrhi bx + clrhi ax + sgnhi si + sgnhi di + + push _di + push _si + push _dx + push _cx + push _bx + push _ax + sti ; Enable interrupts + call [CPTR _PM_mouseHandler] + _add sp,12,24 + + RESTSTK MsStack ; Restore previous stack + + popad ; Restore all extended registers + pop es + pop ds + ret ; We are done!! + +cprocend + +;---------------------------------------------------------------------------- +; PM_timerISR - Timer interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the timer interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible, since a timer overrun will simply hang the +; system. +;---------------------------------------------------------------------------- +cprocfar _PM_timerISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + + NEWSTK TmStack ; Switch to local stack + call [CPTR _PM_timerHandler] + RESTSTK TmStack ; Restore previous stack + + popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; PM_chainPrevTimer - Chain to previous timer interrupt and return +;---------------------------------------------------------------------------- +; Chains to the previous timer interrupt routine and returns control +; back to the high level interrupt handler. +;---------------------------------------------------------------------------- +cprocstart PM_chainPrevTimer + +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealTimer] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax + ret +else + SWAPSTK TmStack ; Swap back to previous stack + pushf ; Save state of interrupt flag + pushf ; Push flags on stack to simulate interrupt +ifdef USE_NASM + call far dword [_PM_prevTimer] +else + call [_PM_prevTimer] +endif + popf ; Restore state of interrupt flag + SWAPSTK TmStack ; Swap back to C stack again + ret +endif + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; PM_rtcISR - Real time clock interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the timer interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible, since a timer overrun will simply hang the +; system. +;---------------------------------------------------------------------------- +cprocfar _PM_rtcISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + +; Clear priority interrupt controller and re-enable interrupts so we +; dont lock things up for long. + + mov al,20h + out 0A0h,al + out 020h,al + +; Clear real-time clock timeout + + in al,70h ; Read CMOS index register + push _ax ; and save for later + IODELAYN 3 + mov al,0Ch + out 70h,al + IODELAYN 5 + in al,71h + +; Call the C interrupt handler function + + LOAD_DS ; Load DS register + cmp [BYTE RtcInside],1 ; Check for mutual exclusion + je @@Exit + mov [BYTE RtcInside],1 + NEWSTK RtcStack ; Switch to local stack + sti ; Re-enable interrupts + call [CPTR _PM_rtcHandler] + RESTSTK RtcStack ; Restore previous stack + mov [BYTE RtcInside],0 + +@@Exit: pop _ax + out 70h,al ; Restore CMOS index register + popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +cprocend + +ifdef flatmodel +;---------------------------------------------------------------------------- +; PM_irqISRTemplate - Hardware interrupt handler IRQ template +;---------------------------------------------------------------------------- +; Hardware interrupt handler for any interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible. +;---------------------------------------------------------------------------- +cprocfar _PM_irqISRTemplate + + push ebx + mov ebx,0 ; Relocation adjustment factor + jmp __IRQEntry + +; Global variables stored in the IRQ thunk code segment + +_CHandler dd 0 ; Pointer to C interrupt handler +_PrevIRQ dd 0 ; Previous IRQ handler + dd 0 +_IRQ dd 0 ; IRQ we are hooked for +ptr_IRQStack DUINT 0 ; Place to store old stack offset +seg_IRQStack dw 0 ; Place to store old stack segment +_Inside db 0 ; Mutual exclusion flag + ALIGN 4 + dclb IRQ_STACK ; Space for local stack +_IRQStack: ; Stack starts at end! + +; Check for and reject spurious IRQ 7 signals + +__IRQEntry: + cmp [BYTE cs:ebx+_IRQ],7 ; Spurious IRQs occur only on IRQ 7 + jmp @@ValidIRQ + push eax + mov al,1011b ; OCW3: read ISR + out 20h,al ; (Intel Peripheral Components, 1991, + in al,20h ; p. 3-188) + shl al,1 ; Set C = bit 7 (IRQ 7) of ISR register + pop eax + jc @@ValidIRQ + iret ; Return from interrupt + +; Save all registers for duration of IRQ handler + +@@ValidIRQ: + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + LOAD_DS ; Load DS register + +; Send an EOI to the PIC + + mov al,20h ; Send EOI to PIC + cmp [BYTE ebx+_IRQ],8 ; Clear PIC1 first if IRQ >= 8 + jb @@1 + out 0A0h,al +@@1: out 20h,al + +; Check for mutual exclusion + + cmp [BYTE ebx+_Inside],1 + je @@ChainOldHandler + mov [BYTE ebx+_Inside],1 + +; Call the C interrupt handler function + + mov [ebx+seg_IRQStack],ss ; Switch to local stack + mov [ebx+ptr_IRQStack],esp + mov [TempSeg],ds + mov ss,[TempSeg] + lea esp,[ebx+_IRQStack] + sti ; Re-enable interrupts + push ebx + call [DWORD ebx+_CHandler] + pop ebx + cli + mov ss,[ebx+seg_IRQStack] ; Restore previous stack + mov esp,[ebx+ptr_IRQStack] + or eax,eax + jz @@ChainOldHandler ; Chain if not handled for shared IRQ + +@@Exit: mov [BYTE ebx+_Inside],0 + popad ; Restore all extended registers + pop es + pop ds + pop ebx + iret ; Return from interrupt + +@@ChainOldHandler: + cmp [DWORD ebx+_PrevIRQ],0 + jz @@Exit + mov [BYTE ebx+_Inside],0 + mov eax,[DWORD ebx+_PrevIRQ] + mov ebx,[DWORD ebx+_PrevIRQ+4] + mov [DWORD _PrevIRQ],eax + mov [DWORD _PrevIRQ+4],ebx + popad ; Restore all extended registers + pop es + pop ds + pop ebx + jmp [cs:_PrevIRQ] ; Chain to previous IRQ handler + +cprocend +cpublic _PM_irqISRTemplateEnd +endif + +;---------------------------------------------------------------------------- +; PM_keyISR - keyboard interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the keyboard interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. However we ensure within this routine +; mutual exclusion to the keyboard handling routine. +;---------------------------------------------------------------------------- +cprocfar _PM_keyISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + + cmp [BYTE KyInside],1 ; Check for mutual exclusion + je @@Reissued + + mov [BYTE KyInside],1 + NEWSTK KyStack ; Switch to local stack + call [CPTR _PM_keyHandler] ; Call C code + RESTSTK KyStack ; Restore previous stack + mov [BYTE KyInside],0 + +@@Exit: popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +; When the BIOS keyboard handler needs to change the SHIFT status lights +; on the keyboard, in the process of doing this the keyboard controller +; re-issues another interrupt, while the current handler is still executing. +; If we recieve another interrupt while still handling the current one, +; then simply chain directly to the previous handler. +; +; Note that for most DOS extenders, the real mode interrupt handler that we +; install takes care of this for us. + +@@Reissued: +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax +else + pushf +ifdef USE_NASM + call far dword [_PM_prevKey] +else + call [_PM_prevKey] +endif +endif + jmp @@Exit + +cprocend + +;---------------------------------------------------------------------------- +; PM_chainPrevkey - Chain to previous key interrupt and return +;---------------------------------------------------------------------------- +; Chains to the previous key interrupt routine and returns control +; back to the high level interrupt handler. +;---------------------------------------------------------------------------- +cprocstart PM_chainPrevKey + +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax + ret +else + +; YIKES! For some strange reason, when execution returns from the +; previous keyboard handler, interrupts are re-enabled!! Since we expect +; interrupts to remain off during the duration of our handler, this can +; cause havoc. However our stack macros always turn off interrupts, so they +; will be off when we exit this routine. Obviously there is a tiny weeny +; window when interrupts will be enabled, but there is nothing we can +; do about this. + + SWAPSTK KyStack ; Swap back to previous stack + pushf ; Push flags on stack to simulate interrupt +ifdef USE_NASM + call far dword [_PM_prevKey] +else + call [_PM_prevKey] +endif + SWAPSTK KyStack ; Swap back to C stack again + ret +endif + +cprocend + +;---------------------------------------------------------------------------- +; PM_key15ISR - Int 15h keyboard interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; This routine gets called if we have been called to handle the Int 15h +; keyboard interrupt callout from real mode. +; +; Entry: AX - Hardware scan code to process +; Exit: AX - Hardware scan code to process (0 to ignore) +;---------------------------------------------------------------------------- +cprocfar _PM_key15ISR + + push ds + push es + LOAD_DS + cmp ah,4Fh + jnz @@NotOurs ; Quit if not keyboard callout + + pushad + cld ; Clear direction flag + xor ah,ah ; AX := scan code + NEWSTK Ky15Stack ; Switch to local stack + push _ax + call [CPTR _PM_key15Handler] ; Call C code + _add sp,2,4 + RESTSTK Ky15Stack ; Restore previous stack + test ax,ax + jz @@1 + stc ; Set carry to process as normal + jmp @@2 +@@1: clc ; Clear carry to ignore scan code +@@2: popad + jmp @@Exit ; We are done + +@@NotOurs: +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey15] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax +else + pushf +ifdef USE_NASM + call far dword [_PM_prevKey15] +else + call [_PM_prevKey15] +endif +endif +@@Exit: pop es + pop ds +ifdef flatmodel + retf 4 +else + retf 2 +endif + +cprocend + +;---------------------------------------------------------------------------- +; PM_breakISR - Control Break interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the Ctrl-Break interrupt. We simply set +; the Ctrl-Break flag to a 1 and leave (note that this is accessed through +; a far pointer, as it may well be located in conventional memory). +;---------------------------------------------------------------------------- +cprocfar _PM_breakISR + + sti + push ds ; Save value of DS + push es + push _bx + + LOAD_DS ; Load DS register +ifdef flatmodel + mov ebx,[_PM_ctrlBPtr] +else + les bx,[_PM_ctrlBPtr] +endif + mov [UINT _ES _bx],1 + +; Run alternate break handler code if installed + + cmp [CPTR _PM_breakHandler],0 + je @@Exit + + pushad + mov _ax,1 + push _ax + call [CPTR _PM_breakHandler] ; Call C code + pop _ax + popad + +@@Exit: pop _bx + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; int PM_ctrlBreakHit(int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the Ctrl-Break flag and possibly clears it. +;---------------------------------------------------------------------------- +cprocstart PM_ctrlBreakHit + + ARG clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es +ifdef flatmodel + mov ebx,[_PM_ctrlBPtr] +else + les bx,[_PM_ctrlBPtr] +endif + cli ; No interrupts thanks! + mov _ax,[_ES _bx] + test [BYTE clearFlag],1 + jz @@Done + mov [UINT _ES _bx],0 + +@@Done: pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; PM_ctrlCISR - Control Break interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the Ctrl-C interrupt. We simply set +; the Ctrl-C flag to a 1 and leave (note that this is accessed through +; a far pointer, as it may well be located in conventional memory). +;---------------------------------------------------------------------------- +cprocfar _PM_ctrlCISR + + sti + push ds ; Save value of DS + push es + push _bx + + LOAD_DS ; Load DS register +ifdef flatmodel + mov ebx,[_PM_ctrlCPtr] +else + les bx,[_PM_ctrlCPtr] +endif + mov [UINT _ES _bx],1 + +; Run alternate break handler code if installed + + cmp [CPTR _PM_breakHandler],0 + je @@Exit + + pushad + mov _ax,0 + push _ax + call [CPTR _PM_breakHandler] ; Call C code + pop _ax + popad + +@@Exit: pop _bx + pop es + pop ds + iret ; Return from interrupt + iretd + +cprocend + +;---------------------------------------------------------------------------- +; int PM_ctrlCHit(int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the Ctrl-C flag and possibly clears it. +;---------------------------------------------------------------------------- +cprocstart PM_ctrlCHit + + ARG clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es +ifdef flatmodel + mov ebx,[_PM_ctrlCPtr] +else + les bx,[_PM_ctrlCPtr] +endif + cli ; No interrupts thanks! + mov _ax,[_ES _bx] + test [BYTE clearFlag],1 + jz @@Done + mov [UINT _ES _bx],0 + +@@Done: + pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; PM_criticalISR - Control Error handler interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Interrupt handler for the MSDOS Critical Error interrupt, to dispatch +; control to high level C based subroutines. We save the state of all +; registers in this routine, and switch to a local stack. We also pass +; the values of the AX and DI registers to the as pointers, so that the +; values can be modified before returning to MSDOS. +;---------------------------------------------------------------------------- +cprocfar _PM_criticalISR + + sti + push ds ; Save value of DS + push es + push _bx ; Save register values changed + cld ; Clear direction flag + + LOAD_DS ; Load DS register +ifdef flatmodel + mov ebx,[_PM_critPtr] +else + les bx,[_PM_critPtr] +endif + mov [_ES _bx],ax + mov [_ES _bx+2],di + +; Run alternate critical handler code if installed + + cmp [CPTR _PM_critHandler],0 + je @@NoAltHandler + + pushad + push _di + push _ax + call [CPTR _PM_critHandler] ; Call C code + _add sp,4,8 + popad + + pop _bx + pop es + pop ds + iret ; Return from interrupt + +@@NoAltHandler: + mov ax,3 ; Tell MSDOS to fail the operation + pop _bx + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; int PM_criticalError(int *axVal,int *diVal,int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the critical error flags, and the values that +; MSDOS passed in the AX and DI registers to our handler. +;---------------------------------------------------------------------------- +cprocstart PM_criticalError + + ARG axVal:DPTR, diVal:DPTR, clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es +ifdef flatmodel + mov ebx,[_PM_critPtr] +else + les bx,[_PM_critPtr] +endif + cli ; No interrupts thanks! + xor _ax,_ax + xor _di,_di + mov ax,[_ES _bx] + mov di,[_ES _bx+2] + test [BYTE clearFlag],1 + jz @@NoClear + mov [ULONG _ES _bx],0 +@@NoClear: + _les _bx,[axVal] + mov [_ES _bx],_ax + _les _bx,[diVal] + mov [_ES _bx],_di + pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setMouseHandler(int mask, PM_mouseHandler mh) +;---------------------------------------------------------------------------- +cprocstart _PM_setMouseHandler + + ARG mouseMask:UINT + + enter_c + push es + + mov ax,0Ch ; AX := Function 12 - install interrupt sub + mov _cx,[mouseMask] ; CX := mouse mask + mov _dx,offset _PM_mouseISR + push cs + pop es ; ES:_DX -> mouse handler + int 33h ; Call mouse driver + + pop es + leave_c + ret + +cprocend + +ifdef flatmodel + +;---------------------------------------------------------------------------- +; void PM_mousePMCB(void) +;---------------------------------------------------------------------------- +; Mouse realmode callback routine. Upon entry to this routine, we recieve +; the following from the DPMI server: +; +; Entry: DS:_SI -> Real mode stack at time of call +; ES:_DI -> Real mode register data structure +; SS:_SP -> Locked protected mode stack to use +;---------------------------------------------------------------------------- +cprocfar _PM_mousePMCB + + pushad + mov eax,[es:_di+1Ch] ; Load register values from real mode + mov ebx,[es:_di+10h] + mov ecx,[es:_di+18h] + mov edx,[es:_di+14h] + mov esi,[es:_di+04h] + mov edi,[es:_di] + call _PM_mouseISR ; Call the mouse handler + popad + + mov ax,[ds:_si] + mov [es:_di+2Ah],ax ; Plug in return IP address + mov ax,[ds:_si+2] + mov [es:_di+2Ch],ax ; Plug in return CS value + add [WORD es:_di+2Eh],4 ; Remove return address from stack + iret ; Go back to real mode! + +cprocend + +;---------------------------------------------------------------------------- +; void PM_int10PMCB(void) +;---------------------------------------------------------------------------- +; int10 realmode callback routine. Upon entry to this routine, we recieve +; the following from the DPMI server: +; +; Entry: DS:ESI -> Real mode stack at time of call +; ES:EDI -> Real mode register data structure +; SS:ESP -> Locked protected mode stack to use +;---------------------------------------------------------------------------- +cprocfar _PM_int10PMCB + + pushad + push ds + push es + push fs + + pushfd + pop eax + mov [es:edi+20h],ax ; Save return flag status + mov ax,[ds:esi] + mov [es:edi+2Ah],ax ; Plug in return IP address + mov ax,[ds:esi+2] + mov [es:edi+2Ch],ax ; Plug in return CS value + add [WORD es:edi+2Eh],4 ; Remove return address from stack + +; Call the install int10 handler in protected mode. This function gets called +; with DS set to the current data selector, and ES:EDI pointing the the +; real mode DPMI register structure at the time of the interrupt. The +; handle must be written in assembler to be able to extract the real mode +; register values from the structure + + push es + pop fs ; FS:EDI -> real mode registers + LOAD_DS + NEWSTK Int10Stack ; Switch to local stack + + call [_PM_int10Handler] + + RESTSTK Int10Stack ; Restore previous stack + pop fs + pop es + pop ds + popad + iret ; Go back to real mode! + +cprocend + +endif + +cpublic _PM_pmdosCodeEnd + +endcodeseg _pmdos + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm b/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm new file mode 100644 index 000000000..34985a9d8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/_vflat.asm @@ -0,0 +1,652 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Based on original code Copyright 1994 Otto Chrons +;* +;* Language: 80386 Assembler, TASM 4.0 or later +;* Environment: IBM PC 32 bit protected mode +;* +;* Description: Low level page fault handler for virtual linear framebuffers. +;* +;**************************************************************************** + + IDEAL + JUMPS + +include "scitech.mac" ; Memory model macros + +header _vflat ; Set up memory model + +VFLAT_START EQU 0F0000000h +VFLAT_END EQU 0F03FFFFFh +PAGE_PRESENT EQU 1 +PAGE_NOTPRESENT EQU 0 +PAGE_READ EQU 0 +PAGE_WRITE EQU 2 + +ifdef DOS4GW + +;---------------------------------------------------------------------------- +; DOS4G/W flat linear framebuffer emulation. +;---------------------------------------------------------------------------- + +begdataseg _vflat + +; Near pointers to the page directory base and our page tables. All of +; this memory is always located in the first Mb of DOS memory. + +PDBR dd 0 ; Page directory base register (CR3) +accessPageAddr dd 0 +accessPageTable dd 0 + +; CauseWay page directory & 1st page table linear addresses. + +CauseWayDIRLinear dd 0 +CauseWay1stLinear dd 0 + +; Place to store a copy of the original Page Table Directory before we +; intialised our virtual buffer code. + +pageDirectory: resd 1024 ; Saved page table directory + +ValidCS dw 0 ; Valid CS for page faults +Ring0CS dw 0 ; Our ring 0 code selector +LastPage dd 0 ; Last page we mapped in +BankFuncBuf: resb 101 ; Place to store bank switch code +BankFuncPtr dd offset BankFuncBuf + +INT14Gate: +INT14Offset dd 0 ; eip of original vector +INT14Selector dw 0 ; cs of original vector + + cextern _PM_savedDS,USHORT + cextern VF_haveCauseWay,BOOL + +enddataseg _vflat + +begcodeseg _vflat ; Start of code segment + + cextern VF_malloc,FPTR + +;---------------------------------------------------------------------------- +; PF_handler64k - Page fault handler for 64k banks +;---------------------------------------------------------------------------- +; The handler below is a 32 bit ring 0 page fault handler. It receives +; control immediately after any page fault or after an IRQ6 (hardware +; interrupt). This provides the fastest possible handling of page faults +; since it jump directly here. If this is a page fault, the number +; immediately on the stack will be an error code, at offset 4 will be +; the eip of the faulting instruction, at offset 8 will be the cs of the +; faulting instruction. If it is a hardware interrupt, it will not have +; the error code and the eflags will be at offset 8. +;---------------------------------------------------------------------------- +cprocfar PF_handler64k + +; Check if this is a processor exeception or a page fault + + push eax + mov ax,[cs:ValidCS] ; Use CS override to access data + cmp [ss:esp+12],ax ; Is this a page fault? + jne @@ToOldHandler ; Nope, jump to the previous handler + +; Get address of page fault and check if within our handlers range + + mov eax,cr2 ; EBX has page fault linear address + cmp eax,VFLAT_START ; Is the fault less than ours? + jb @@ToOldHandler ; Yep, go to previous handler + cmp eax,VFLAT_END ; Is the fault more than ours? + jae @@ToOldHandler ; Yep, go to previous handler + +; This is our page fault, so we need to handle it + + pushad + push ds + push es + mov ebx,eax ; EBX := page fault address + and ebx,invert 0FFFFh ; Mask to 64k bank boundary + mov ds,[cs:_PM_savedDS]; Load segment registers + mov es,[cs:_PM_savedDS] + +; Map in the page table for our virtual framebuffer area for modification + + mov edi,[PDBR] ; EDI points to page directory + mov edx,ebx ; EDX = linear address + shr edx,22 ; EDX = offset to page directory + mov edx,[edx*4+edi] ; EDX = physical page table address + mov eax,edx + mov edx,[accessPageTable] + or eax,7 + mov [edx],eax + mov eax,cr3 + mov cr3,eax ; Update page table cache + +; Mark all pages valid for the new page fault area + + mov esi,ebx ; ESI := linear address for page + shr esi,10 + and esi,0FFFh ; Offset into page table + add esi,[accessPageAddr] +ifdef USE_NASM +%assign off 0 +%rep 16 + or [DWORD esi+off],0000000001h ; Enable pages +%assign off off+4 +%endrep +else +off = 0 +REPT 16 + or [DWORD esi+off],0000000001h ; Enable pages +off = off+4 +ENDM +endif + +; Mark all pages invalid for the previously mapped area + + xchg esi,[LastPage] ; Save last page for next page fault + test esi,esi + jz @@DoneMapping ; Dont update if first time round +ifdef USE_NASM +%assign off 0 +%rep 16 + or [DWORD esi+off],0FFFFFFFEh ; Disable pages +%assign off off+4 +%endrep +else +off = 0 +REPT 16 + and [DWORD esi+off],0FFFFFFFEh ; Disable pages +off = off+4 +ENDM +endif + +@@DoneMapping: + mov eax,cr3 + mov cr3,eax ; Flush the TLB + +; Now program the new SuperVGA starting bank address + + mov eax,ebx ; EAX := page fault address + shr eax,16 + and eax,0FFh ; Mask to 0-255 + call [BankFuncPtr] ; Call the bank switch function + + pop es + pop ds + popad + pop eax + add esp,4 ; Pop the error code from stack + iretd ; Return to faulting instruction + +@@ToOldHandler: + pop eax +ifdef USE_NASM + jmp far dword [cs:INT14Gate]; Chain to previous handler +else + jmp [FWORD cs:INT14Gate]; Chain to previous handler +endif + +cprocend + +;---------------------------------------------------------------------------- +; PF_handler4k - Page fault handler for 4k banks +;---------------------------------------------------------------------------- +; The handler below is a 32 bit ring 0 page fault handler. It receives +; control immediately after any page fault or after an IRQ6 (hardware +; interrupt). This provides the fastest possible handling of page faults +; since it jump directly here. If this is a page fault, the number +; immediately on the stack will be an error code, at offset 4 will be +; the eip of the faulting instruction, at offset 8 will be the cs of the +; faulting instruction. If it is a hardware interrupt, it will not have +; the error code and the eflags will be at offset 8. +;---------------------------------------------------------------------------- +cprocfar PF_handler4k + +; Fill in when we have tested all the 64Kb code + +ifdef USE_NASM + jmp far dword [cs:INT14Gate]; Chain to previous handler +else + jmp [FWORD cs:INT14Gate]; Chain to previous handler +endif + +cprocend + +;---------------------------------------------------------------------------- +; void InstallFaultHandler(void *baseAddr,int bankSize) +;---------------------------------------------------------------------------- +; Installes the page fault handler directly int the interrupt descriptor +; table for maximum performance. This of course requires ring 0 access, +; but none of this stuff will run without ring 0! +;---------------------------------------------------------------------------- +cprocstart InstallFaultHandler + + ARG baseAddr:ULONG, bankSize:UINT + + enter_c + + mov [DWORD LastPage],0 ; No pages have been mapped + mov ax,cs + mov [ValidCS],ax ; Save CS value for page faults + +; Put address of our page fault handler into the IDT directly + + sub esp,6 ; Allocate space on stack +ifdef USE_NASM + sidt [ss:esp] ; Store pointer to IDT +else + sidt [FWORD ss:esp] ; Store pointer to IDT +endif + pop ax ; add esp,2 + pop eax ; Absolute address of IDT + add eax,14*8 ; Point to Int #14 + +; Note that Interrupt gates do not have the high and low word of the +; offset in adjacent words in memory, there are 4 bytes separating them. + + mov ecx,[eax] ; Get cs and low 16 bits of offset + mov edx,[eax+6] ; Get high 16 bits of offset in dx + shl edx,16 + mov dx,cx ; edx has offset + mov [INT14Offset],edx ; Save offset + shr ecx,16 + mov [INT14Selector],cx ; Save original cs + mov [eax+2],cs ; Install new cs + mov edx,offset PF_handler64k + cmp [UINT bankSize],4 + jne @@1 + mov edx,offset PF_handler4k +@@1: mov [eax],dx ; Install low word of offset + shr edx,16 + mov [eax+6],dx ; Install high word of offset + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void RemoveFaultHandler(void) +;---------------------------------------------------------------------------- +; Closes down the virtual framebuffer services and restores the previous +; page fault handler. +;---------------------------------------------------------------------------- +cprocstart RemoveFaultHandler + + enter_c + +; Remove page fault handler from IDT + + sub esp,6 ; Allocate space on stack +ifdef USE_NASM + sidt [ss:esp] ; Store pointer to IDT +else + sidt [FWORD ss:esp] ; Store pointer to IDT +endif + + pop ax ; add esp,2 + pop eax ; Absolute address of IDT + add eax,14*8 ; Point to Int #14 + mov cx,[INT14Selector] + mov [eax+2],cx ; Restore original CS + mov edx,[INT14Offset] + mov [eax],dx ; Install low word of offset + shr edx,16 + mov [eax+6],dx ; Install high word of offset + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void InstallBankFunc(int codeLen,void *bankFunc) +;---------------------------------------------------------------------------- +; Installs the bank switch function by relocating it into our data segment +; and making it into a callable function. We do it this way to make the +; code identical to the way that the VflatD devices work under Windows. +;---------------------------------------------------------------------------- +cprocstart InstallBankFunc + + ARG codeLen:UINT, bankFunc:DPTR + + enter_c + + mov esi,[bankFunc] ; Copy the code into buffer + mov edi,offset BankFuncBuf + mov ecx,[codeLen] + rep movsb + mov [BYTE edi],0C3h ; Terminate the function with a near ret + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int InitPaging(void) +;---------------------------------------------------------------------------- +; Initializes paging system. If paging is not enabled, builds a page table +; directory and page tables for physical memory +; +; Exit: 0 - Successful +; -1 - Couldn't initialize paging mechanism +;---------------------------------------------------------------------------- +cprocstart InitPaging + + push ebx + push ecx + push edx + push esi + push edi + +; Are we running under CauseWay? + + mov ax,0FFF9h + int 31h + jc @@NotCauseway + cmp ecx,"CAUS" + jnz @@NotCauseway + cmp edx,"EWAY" + jnz @@NotCauseway + + mov [BOOL VF_haveCauseWay],1 + mov [CauseWayDIRLinear],esi + mov [CauseWay1stLinear],edi + +; Check for DPMI + + mov ax,0ff00h + push es + int 31h + pop es + shr edi,2 + and edi,3 + cmp edi,2 + jz @@ErrExit ; Not supported under DPMI + + mov eax,[CauseWayDIRLinear] + jmp @@CopyCR3 + +@@NotCauseway: + mov ax,cs + test ax,3 ; Which ring are we running + jnz @@ErrExit ; Needs zero ring to access + ; page tables (CR3) + mov eax,cr0 ; Load CR0 + test eax,80000000h ; Is paging enabled? + jz @@ErrExit ; No, we must have paging! + + mov eax,cr3 ; Load directory address + and eax,0FFFFF000h + +@@CopyCR3: + mov [PDBR],eax ; Save it + mov esi,eax + mov edi,offset pageDirectory + mov ecx,1024 + cld + rep movsd ; Copy the original page table directory + cmp [DWORD accessPageAddr],0; Check if we have allocated page + jne @@HaveRealMem ; table already (we cant free it) + + mov eax,0100h ; DPMI DOS allocate + mov ebx,8192/16 + int 31h ; Allocate 8192 bytes + and eax,0FFFFh + shl eax,4 ; EAX points to newly allocated memory + add eax,4095 + and eax,0FFFFF000h ; Page align + mov [accessPageAddr],eax + +@@HaveRealMem: + mov eax,[accessPageAddr] ; EAX -> page table in 1st Mb + shr eax,12 + and eax,3FFh ; Page table offset + shl eax,2 + cmp [BOOL VF_haveCauseWay],0 + jz @@NotCW0 + mov ebx,[CauseWay1stLinear] + jmp @@Put1st + +@@NotCW0: + mov ebx,[PDBR] + mov ebx,[ebx] + and ebx,0FFFFF000h ; Page table for 1st megabyte + +@@Put1st: + add eax,ebx + mov [accessPageTable],eax + sub eax,eax ; No error + jmp @@Exit + +@@ErrExit: + mov eax,-1 + +@@Exit: pop edi + pop esi + pop edx + pop ecx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void ClosePaging(void) +;---------------------------------------------------------------------------- +; Closes the paging system +;---------------------------------------------------------------------------- +cprocstart ClosePaging + + push eax + push ecx + push edx + push esi + push edi + + mov eax,[accessPageAddr] + call AccessPage ; Restore AccessPage mapping + mov edi,[PDBR] + mov esi,offset pageDirectory + mov ecx,1024 + cld + rep movsd ; Restore the original page table directory + +@@Exit: pop edi + pop esi + pop edx + pop ecx + pop eax + ret + +cprocend + +;---------------------------------------------------------------------------- +; long AccessPage(long phys) +;---------------------------------------------------------------------------- +; Maps a known page to given physical memory +; Entry: EAX - Physical memory +; Exit: EAX - Linear memory address of mapped phys mem +;---------------------------------------------------------------------------- +cprocstatic AccessPage + + push edx + mov edx,[accessPageTable] + or eax,7 + mov [edx],eax + mov eax,cr3 + mov cr3,eax ; Update page table cache + mov eax,[accessPageAddr] + pop edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; long GetPhysicalAddress(long linear) +;---------------------------------------------------------------------------- +; Returns the physical address of linear address +; Entry: EAX - Linear address to convert +; Exit: EAX - Physical address +;---------------------------------------------------------------------------- +cprocstatic GetPhysicalAddress + + push ebx + push edx + mov edx,eax + shr edx,22 ; EDX is the directory offset + mov ebx,[PDBR] + mov edx,[edx*4+ebx] ; Load page table address + push eax + mov eax,edx + call AccessPage ; Access the page table + mov edx,eax + pop eax + shr eax,12 + and eax,03FFh ; EAX offset into page table + mov eax,[edx+eax*4] ; Load physical address + and eax,0FFFFF000h + pop edx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void CreatePageTable(long pageDEntry) +;---------------------------------------------------------------------------- +; Creates a page table for specific address (4MB) +; Entry: EAX - Page directory entry (top 10-bits of address) +;---------------------------------------------------------------------------- +cprocstatic CreatePageTable + + push ebx + push ecx + push edx + push edi + mov ebx,eax ; Save address + mov eax,8192 + push eax + call VF_malloc ; Allocate page table directory + add esp,4 + add eax,0FFFh + and eax,0FFFFF000h ; Page align (4KB) + mov edi,eax ; Save page table linear address + sub eax,eax ; Fill with zero + mov ecx,1024 + cld + rep stosd ; Clear page table + sub edi,4096 + mov eax,edi + call GetPhysicalAddress + mov edx,[PDBR] + or eax,7 ; Present/write/user bit + mov [edx+ebx*4],eax ; Save physical address into page directory + mov eax,cr3 + mov cr3,eax ; Update page table cache + pop edi + pop edx + pop ecx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags); +;---------------------------------------------------------------------------- +; Maps physical memory into linear memory +; Entry: pAddr - Physical address +; lAddr - Linear address +; pages - Number of 4K pages to map +; flags - Page flags +; bit 0 = present +; bit 1 = Read(0)/Write(1) +;---------------------------------------------------------------------------- +cprocstart MapPhysical2Linear + + ARG pAddr:ULONG, lAddr:ULONG, pages:UINT, pflags:UINT + + enter_c + + and [ULONG pAddr],0FFFFF000h; Page boundary + and [ULONG lAddr],0FFFFF000h; Page boundary + mov ecx,[pflags] + and ecx,11b ; Just two bits + or ecx,100b ; Supervisor bit + mov [pflags],ecx + + mov edx,[lAddr] + shr edx,22 ; EDX = Directory + mov esi,[PDBR] + mov edi,[pages] ; EDI page count + mov ebx,[lAddr] + +@@CreateLoop: + mov ecx,[esi+edx*4] ; Load page table address + test ecx,1 ; Is it present? + jnz @@TableOK + mov eax,edx + call CreatePageTable ; Create a page table +@@TableOK: + mov eax,ebx + shr eax,12 + and eax,3FFh + sub eax,1024 + neg eax ; EAX = page count in this table + inc edx ; Next table + mov ebx,0 ; Next time we'll map 1K pages + sub edi,eax ; Subtract mapped pages from page count + jns @@CreateLoop ; Create more tables if necessary + + mov ecx,[pages] ; ECX = Page count + mov esi,[lAddr] + shr esi,12 ; Offset part isn't needed + mov edi,[pAddr] +@@MappingLoop: + mov eax,esi + shr eax,10 ; EAX = offset to page directory + mov ebx,[PDBR] + mov eax,[eax*4+ebx] ; EAX = page table address + call AccessPage + mov ebx,esi + and ebx,3FFh ; EBX = offset to page table + mov edx,edi + add edi,4096 ; Next physical address + inc esi ; Next linear page + or edx,[pflags] ; Update flags... + mov [eax+ebx*4],edx ; Store page table entry + loop @@MappingLoop + mov eax,cr3 + mov cr3,eax ; Update page table cache + + leave_c + ret + +cprocend + +endcodeseg _vflat + +endif + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c new file mode 100644 index 000000000..ee117c78e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/cpuinfo.c @@ -0,0 +1,72 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: DOS +* +* Description: MSDOS specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/* External timing function */ + +void __ZTimerInit(void); + +/**************************************************************************** +REMARKS: +Do nothing for DOS because we don't have thread priorities. +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +Do nothing for DOS because we don't have thread priorities. +****************************************************************************/ +#define RestoreThreadPriority(i) (void)(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + ulong resolution; + + __ZTimerInit(); + ULZTimerResolution(&resolution); + freq->low = (ulong)(10000000000.0 / resolution); + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + (t)->low = ULZReadTime() * 10000L; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/event.c b/board/MAI/bios_emulator/scitech/src/pm/dos/event.c new file mode 100644 index 000000000..a969d111b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/event.c @@ -0,0 +1,494 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit DOS +* +* Description: 32-bit DOS implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*--------------------------- Global variables ----------------------------*/ + +ibool _VARAPI _EVT_useEvents = true; /* True to use event handling */ +ibool _VARAPI _EVT_installed = 0; /* Event handers installed? */ +uchar _VARAPI *_EVT_biosPtr = NULL; /* Pointer to the BIOS data area */ +static ibool haveMouse = false; /* True if we have a mouse */ + +/*---------------------------- Implementation -----------------------------*/ + +/* External assembler functions */ + +void EVTAPI _EVT_pollJoystick(void); +uint EVTAPI _EVT_disableInt(void); +uint EVTAPI _EVT_restoreInt(uint flags); +void EVTAPI _EVT_codeStart(void); +void EVTAPI _EVT_codeEnd(void); +void EVTAPI _EVT_cCodeStart(void); +void EVTAPI _EVT_cCodeEnd(void); +int EVTAPI _EVT_getKeyCode(void); +void EVTAPI _EVT_pumpMessages(void); +int EVTAPI EVT_rdinx(int port,int index); +void EVTAPI EVT_wrinx(int port,int index,int value); + +#ifdef NO_KEYBOARD_INTERRUPT +/**************************************************************************** +REMARKS: +This function is used to pump all keyboard messages from the BIOS keyboard +handler into our event queue. This can be used to avoid using the +installable keyboard handler if this is causing problems. +****************************************************************************/ +static void EVTAPI _EVT_pumpMessages(void) +{ + RMREGS regs; + uint key,ps; + + /* Since the keyboard ISR has not been installed if NO_IDE_BUG has + * been defined, we first check for any pending keyboard events + * here, and if there are some insert them into the event queue to + * be picked up later - what a kludge. + */ + while ((key = _EVT_getKeyCode()) != 0) { + ps = _EVT_disableInt(); + addKeyEvent(EVT_KEYDOWN, key); + _EVT_restoreInt(ps); + } + + regs.x.ax = 0x0B; /* Reset Move Mouse */ + PM_int86(0x33,®s,®s); +} +#endif + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + return (ulong)PM_getLong(_EVT_biosPtr+0x6C) * 55UL; +} + +/**************************************************************************** +REMARKS: +Reboots the machine from DOS (warm boot) +****************************************************************************/ +static void Reboot(void) +{ + PMREGS regs; + PMSREGS sregs; + + ushort *rebootType = PM_mapRealPointer(0x40,0x72); + *rebootType = 0x1234; + PM_callRealMode(0xFFFF,0x0000,®s,&sregs); +} + +/**************************************************************************** +REMARKS: +Include generic raw scancode keyboard module. +****************************************************************************/ +#define SUPPORT_CTRL_ALT_DEL +#include "common/keyboard.c" + +/**************************************************************************** +REMARKS: +This function fools the DOS mouse driver into thinking that it is running +in graphics mode, rather than text mode so we always get virtual coordinates +correctly rather than character coordinates. +****************************************************************************/ +int _EVT_foolMouse(void) +{ + int oldmode = PM_getByte(_EVT_biosPtr+0x49); + PM_setByte(_EVT_biosPtr+0x49,0x10); + oldmode |= (EVT_rdinx(0x3C4,0x2) << 8); + return oldmode; +} + +/**************************************************************************** +REMARKS: +This function unfools the DOS mouse driver after we have finished calling it. +****************************************************************************/ +void _EVT_unfoolMouse( + int oldmode) +{ + PM_setByte(_EVT_biosPtr+0x49,oldmode); + + /* Some mouse drivers reset the plane mask register for VGA plane 4 + * modes, which screws up the display on some VGA compatible controllers + * in SuperVGA modes. We reset the value back again in here to solve + * the problem. + */ + EVT_wrinx(0x3C4,0x2,oldmode >> 8); +} + +/**************************************************************************** +REMARKS: +Determines if we have a mouse attached and functioning. +****************************************************************************/ +static ibool detectMouse(void) +{ + RMREGS regs; + RMSREGS sregs; + uchar *p; + ibool retval; + + regs.x.ax = 0x3533; /* Get interrupt vector 0x33 */ + PM_int86x(0x21,®s,®s,&sregs); + + /* Check that interrupt vector 0x33 is not a zero, and that the first + * instruction in the interrupt vector is not an IRET instruction + */ + p = PM_mapRealPointer(sregs.es, regs.x.bx); + retval = ((sregs.es != 0) || (regs.x.bx != 0)) && (PM_getByte(p) != 207); + return retval; +} + +/**************************************************************************** +PARAMETERS: +what - Event code +message - Event message +x,y - Mouse position at time of event +but_stat - Mouse button status at time of event + +REMARKS: +Adds a new mouse event to the event queue. This routine is called from within +the mouse interrupt subroutine, so it must be efficient. + +NOTE: Interrupts MUST be OFF while this routine is called to ensure we have + mutually exclusive access to our internal data structures for + interrupt driven systems (like under DOS). +****************************************************************************/ +static void addMouseEvent( + uint what, + uint message, + int x, + int y, + int mickeyX, + int mickeyY, + uint but_stat) +{ + event_t evt; + + if (EVT.count < EVENTQSIZE) { + /* Save information in event record. */ + evt.when = _EVT_getTicks(); + evt.what = what; + evt.message = message; + evt.modifiers = but_stat; + evt.where_x = x; /* Save mouse event position */ + evt.where_y = y; + evt.relative_x = mickeyX; + evt.relative_y = mickeyY; + evt.modifiers |= EVT.keyModifiers; + addEvent(&evt); /* Add to tail of event queue */ + } +} + +/**************************************************************************** +PARAMETERS: +mask - Event mask +butstate - Button state +x - Mouse x coordinate +y - Mouse y coordinate + +REMARKS: +Mouse event handling routine. This gets called when a mouse event occurs, +and we call the addMouseEvent() routine to add the appropriate mouse event +to the event queue. + +Note: Interrupts are ON when this routine is called by the mouse driver code. +****************************************************************************/ +static void EVTAPI mouseISR( + uint mask, + uint butstate, + int x, + int y, + int mickeyX, + int mickeyY) +{ + uint ps; + uint buttonMask; + + if (mask & 1) { + /* Save the current mouse coordinates */ + EVT.mx = x; EVT.my = y; + + /* If the last event was a movement event, then modify the last + * event rather than post a new one, so that the queue will not + * become saturated. Before we modify the data structures, we + * MUST ensure that interrupts are off. + */ + ps = _EVT_disableInt(); + if (EVT.oldMove != -1) { + EVT.evtq[EVT.oldMove].where_x = x; /* Modify existing one */ + EVT.evtq[EVT.oldMove].where_y = y; + EVT.evtq[EVT.oldMove].relative_x += mickeyX; + EVT.evtq[EVT.oldMove].relative_y += mickeyY; + } + else { + EVT.oldMove = EVT.freeHead; /* Save id of this move event */ + addMouseEvent(EVT_MOUSEMOVE,0,x,y,mickeyX,mickeyY,butstate); + } + _EVT_restoreInt(ps); + } + if (mask & 0x2A) { + ps = _EVT_disableInt(); + buttonMask = 0; + if (mask & 2) buttonMask |= EVT_LEFTBMASK; + if (mask & 8) buttonMask |= EVT_RIGHTBMASK; + if (mask & 32) buttonMask |= EVT_MIDDLEBMASK; + addMouseEvent(EVT_MOUSEDOWN,buttonMask,x,y,0,0,butstate); + EVT.oldMove = -1; + _EVT_restoreInt(ps); + } + if (mask & 0x54) { + ps = _EVT_disableInt(); + buttonMask = 0; + if (mask & 2) buttonMask |= EVT_LEFTBMASK; + if (mask & 8) buttonMask |= EVT_RIGHTBMASK; + if (mask & 32) buttonMask |= EVT_MIDDLEBMASK; + addMouseEvent(EVT_MOUSEUP,buttonMask,x,y,0,0,butstate); + EVT.oldMove = -1; + _EVT_restoreInt(ps); + } + EVT.oldKey = -1; +} + +/**************************************************************************** +REMARKS: +Keyboard interrupt handler function. + +NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, + and we leave them OFF the entire time. +****************************************************************************/ +static void EVTAPI keyboardISR(void) +{ + processRawScanCode(PM_inpb(0x60)); + PM_outpb(0x20,0x20); +} + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + int i; + + PM_init(); + EVT.mouseMove = mouseMove; + _EVT_biosPtr = PM_getBIOSPointer(); + EVT_resume(); + + /* Grab all characters pending in the keyboard buffer and stuff + * them into our event buffer. This allows us to pick up any keypresses + * while the program is initialising. + */ + while ((i = _EVT_getKeyCode()) != 0) + addKeyEvent(EVT_KEYDOWN,i); +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVTAPI EVT_resume(void) +{ + static int locked = 0; + int stat; + uchar mods; + PM_lockHandle lh; /* Unused in DOS */ + + if (_EVT_useEvents) { + /* Initialise the event queue and enable our interrupt handlers */ + initEventQueue(); +#ifndef NO_KEYBOARD_INTERRUPT + PM_setKeyHandler(keyboardISR); +#endif +#ifndef NO_MOUSE_INTERRUPT + if ((haveMouse = detectMouse()) != 0) { + int oldmode = _EVT_foolMouse(); + PM_setMouseHandler(0xFFFF,mouseISR); + _EVT_unfoolMouse(oldmode); + } +#endif + + /* Read the keyboard modifier flags from the BIOS to get the + * correct initialisation state. The only state we care about is + * the correct toggle state flags such as SCROLLLOCK, NUMLOCK and + * CAPSLOCK. + */ + EVT.keyModifiers = 0; + mods = PM_getByte(_EVT_biosPtr+0x17); + if (mods & 0x10) + EVT.keyModifiers |= EVT_SCROLLLOCK; + if (mods & 0x20) + EVT.keyModifiers |= EVT_NUMLOCK; + if (mods & 0x40) + EVT.keyModifiers |= EVT_CAPSLOCK; + + /* Lock all of the code and data used by our protected mode interrupt + * handling routines, so that it will continue to work correctly + * under real mode. + */ + if (!locked) { + /* It is difficult to ensure that we lock our global data, so we + * do this by taking the address of a variable locking all data + * 2Kb on either side. This should properly cover the global data + * used by the module (the other alternative is to declare the + * variables in assembler, in which case we know it will be + * correct). + */ + stat = !PM_lockDataPages(&EVT,sizeof(EVT),&lh); + stat |= !PM_lockDataPages(&_EVT_biosPtr,sizeof(_EVT_biosPtr),&lh); + stat |= !PM_lockCodePages((__codePtr)_EVT_cCodeStart,(int)_EVT_cCodeEnd-(int)_EVT_cCodeStart,&lh); + stat |= !PM_lockCodePages((__codePtr)_EVT_codeStart,(int)_EVT_codeEnd-(int)_EVT_codeStart,&lh); + if (stat) { + PM_fatalError("Page locking services failed - interrupt handling not safe!"); + exit(1); + } + locked = 1; + } + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); + _EVT_installed = true; + } +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + RMREGS regs; + + if (haveMouse) { + int oldmode = _EVT_foolMouse(); + PM_resetMouseDriver(1); + regs.x.ax = 7; /* Mouse function 7 - Set horizontal min and max */ + regs.x.cx = 0; + regs.x.dx = xRes; + PM_int86(0x33,®s,®s); + regs.x.ax = 8; /* Mouse function 8 - Set vertical min and max */ + regs.x.cx = 0; + regs.x.dx = yRes; + PM_int86(0x33,®s,®s); + _EVT_unfoolMouse(oldmode); + } +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +void _EVT_setMousePos( + int *x, + int *y) +{ + RMREGS regs; + + if (haveMouse) { + int oldmode = _EVT_foolMouse(); + regs.x.ax = 4; /* Mouse function 4 - Set mouse position */ + regs.x.cx = *x; /* New horizontal coordinate */ + regs.x.dx = *y; /* New vertical coordinate */ + PM_int86(0x33,®s,®s); + _EVT_unfoolMouse(oldmode); + } +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVTAPI EVT_suspend(void) +{ + uchar mods; + + if (_EVT_installed) { + /* Restore the interrupt handlers */ + PM_restoreKeyHandler(); + if (haveMouse) + PM_restoreMouseHandler(); + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* Set the keyboard modifier flags in the BIOS to our values */ + EVT_allowLEDS(true); + mods = PM_getByte(_EVT_biosPtr+0x17) & ~0x70; + if (EVT.keyModifiers & EVT_SCROLLLOCK) + mods |= 0x10; + if (EVT.keyModifiers & EVT_NUMLOCK) + mods |= 0x20; + if (EVT.keyModifiers & EVT_CAPSLOCK) + mods |= 0x40; + PM_setByte(_EVT_biosPtr+0x17,mods); + + /* Flag that we are no longer installed */ + _EVT_installed = false; + } +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVTAPI EVT_exit(void) +{ + EVT_suspend(); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h new file mode 100644 index 000000000..35e8e00f7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/oshdr.h @@ -0,0 +1,29 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit DOS +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c b/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c new file mode 100644 index 000000000..2ad9e34f9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/pm.c @@ -0,0 +1,2243 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 16/32 bit DOS +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "ztimerc.h" +#include "mtrr.h" +#include "pm_help.h" +#include +#include +#include +#include +#include +#ifdef __GNUC__ +#include +#include +#include +#else +#include +#endif +#ifdef __BORLANDC__ +#pragma warn -par +#endif + +/*--------------------------- Global variables ----------------------------*/ + +typedef struct { + int oldMode; + int old50Lines; + } DOS_stateBuf; + +#define MAX_RM_BLOCKS 10 + +static struct { + void *p; + uint tag; + } rmBlocks[MAX_RM_BLOCKS]; + +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +static void (PMAPIP fatalErrorCleanup)(void) = NULL; +ushort _VARAPI _PM_savedDS = 0; +#ifdef DOS4GW +static ulong PDB = 0,*pPDB = NULL; +#endif +#ifndef REALMODE +static char VXD_name[] = PMHELP_NAME; +static char VXD_module[] = PMHELP_MODULE; +static char VXD_DDBName[] = PMHELP_DDBNAME; +static uint VXD_version = -1; +static uint VXD_loadOff = 0; +static uint VXD_loadSel = 0; +uint _VARAPI _PM_VXD_off = 0; +uint _VARAPI _PM_VXD_sel = 0; +int _VARAPI _PM_haveCauseWay = -1; + +/* Memory mapping cache */ + +#define MAX_MEMORY_MAPPINGS 100 +typedef struct { + ulong physical; + ulong linear; + ulong limit; + } mmapping; +static mmapping maps[MAX_MEMORY_MAPPINGS] = {0}; +static int numMaps = 0; + +/* Page sized block cache */ + +#define PAGES_PER_BLOCK 100 +#define FREELIST_NEXT(p) (*(void**)(p)) +typedef struct pageblock { + struct pageblock *next; + struct pageblock *prev; + void *freeListStart; + void *freeList; + void *freeListEnd; + int freeCount; + } pageblock; +static pageblock *pageBlocks = NULL; +#endif + +/* Start of all page tables in CauseWay */ + +#define CW_PAGE_TABLE_START (1024UL*4096UL*1023UL) + +/*----------------------------- Implementation ----------------------------*/ + +/* External assembler functions */ + +ulong _ASMAPI _PM_getPDB(void); +int _ASMAPI _PM_pagingEnabled(void); +void _ASMAPI _PM_VxDCall(VXD_regs *regs,uint off,uint sel); + +#ifndef REALMODE +/**************************************************************************** +REMARKS: +Exit function to unload the dynamically loaded VxD +****************************************************************************/ +static void UnloadVxD(void) +{ + PMSREGS sregs; + VXD_regs r; + + r.eax = 2; + r.ebx = 0; + r.edx = (uint)VXD_module; + PM_segread(&sregs); +#ifdef __16BIT__ + r.ds = ((ulong)VXD_module) >> 16; +#else + r.ds = sregs.ds; +#endif + r.es = sregs.es; + _PM_VxDCall(&r,VXD_loadOff,VXD_loadSel); +} + +/**************************************************************************** +REMARKS: +External function to call the PMHELP helper VxD. +****************************************************************************/ +void PMAPI PM_VxDCall( + VXD_regs *regs) +{ + if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) + _PM_VxDCall(regs,_PM_VXD_off,_PM_VXD_sel); +} + +/**************************************************************************** +RETURNS: +BCD coded version number of the VxD, or 0 if not loaded (ie: 0x202 - 2.2) + +REMARKS: +This function gets the version number for the VxD that we have connected to. +****************************************************************************/ +uint PMAPI PMHELP_getVersion(void) +{ + VXD_regs r; + + /* Call the helper VxD to determine the version number */ + if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) { + memset(&r,0,sizeof(r)); + r.eax = API_NUM(PMHELP_GETVER); + _PM_VxDCall(&r,_PM_VXD_off,_PM_VXD_sel); + return VXD_version = (uint)r.eax; + } + return VXD_version = 0; +} + +/**************************************************************************** +DESCRIPTION: +Connects to the helper VxD and returns the version number + +RETURNS: +True if the VxD was found and loaded, false otherwise. + +REMARKS: +This function connects to the VxD (loading it if it is dynamically loadable) +and returns the version number of the VxD. +****************************************************************************/ +static ibool PMHELP_connect(void) +{ + PMREGS regs; + PMSREGS sregs; + VXD_regs r; + + /* Bail early if we have alread connected */ + if (VXD_version != -1) + return VXD_version != 0; + + /* Get the static SDDHELP.VXD entry point if available */ + PM_segread(&sregs); + regs.x.ax = 0x1684; + regs.x.bx = SDDHELP_DeviceID; + regs.x.di = 0; + sregs.es = 0; + PM_int386x(0x2F,®s,®s,&sregs); + _PM_VXD_sel = sregs.es; + _PM_VXD_off = regs.x.di; + if (_PM_VXD_sel != 0 || _PM_VXD_off != 0) { + if (PMHELP_getVersion() >= PMHELP_VERSION) + return true; + } + + /* If we get here, then either SDDHELP.VXD is not loaded, or it is an + * earlier version. In this case try to dynamically load the PMHELP.VXD + * helper VxD instead. + */ + PM_segread(&sregs); + regs.x.ax = 0x1684; + regs.x.bx = VXDLDR_DeviceID; + regs.x.di = 0; + sregs.es = 0; + PM_int386x(0x2F,®s,®s,&sregs); + VXD_loadSel = sregs.es; + VXD_loadOff = regs.x.di; + if (VXD_loadSel == 0 && VXD_loadOff == 0) + return VXD_version = 0; + r.eax = 1; + r.ebx = 0; + r.edx = (uint)VXD_name; + PM_segread(&sregs); + r.ds = sregs.ds; + r.es = sregs.es; + _PM_VxDCall(&r,VXD_loadOff,VXD_loadSel); + if (r.eax != 0) + return VXD_version = 0; + + /* Get the dynamic VxD entry point so we can call it */ + atexit(UnloadVxD); + PM_segread(&sregs); + regs.x.ax = 0x1684; + regs.x.bx = 0; + regs.e.edi = (uint)VXD_DDBName; + PM_int386x(0x2F,®s,®s,&sregs); + _PM_VXD_sel = sregs.es; + _PM_VXD_off = regs.x.di; + if (_PM_VXD_sel == 0 && _PM_VXD_off == 0) + return VXD_version = 0; + if (PMHELP_getVersion() >= PMHELP_VERSION) + return true; + return VXD_version = 0; +} +#endif + +/**************************************************************************** +REMARKS: +Initialise the PM library. First we try to connect to a static SDDHELP.VXD +helper VxD, and check that it is a version we can use. If not we try to +dynamically load the PMHELP.VXD helper VxD +****************************************************************************/ +void PMAPI PM_init(void) +{ +#ifndef REALMODE + PMREGS regs; + + /* Check if we are running under CauseWay under real DOS */ + if (_PM_haveCauseWay == -1) { + /* Check if we are running under DPMI in which case we will not be + * able to use our special ring 0 CauseWay functions. + */ + _PM_haveCauseWay = false; + regs.x.ax = 0xFF00; + PM_int386(0x31,®s,®s); + if (regs.x.cflag || !(regs.e.edi & 8)) { + /* We are not under DPMI, so now check if CauseWay is active */ + regs.x.ax = 0xFFF9; + PM_int386(0x31,®s,®s); + if (!regs.x.cflag && regs.e.ecx == 0x43415553 && regs.e.edx == 0x45574159) + _PM_haveCauseWay = true; + } + + /* Now connect to PMHELP.VXD and initialise MTRR module */ + if (!PMHELP_connect()) + MTRR_init(); + } +#endif +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ +#ifndef REALMODE + VXD_regs regs; + + if (PMHELP_connect()) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_ENABLELFBCOMB); + regs.ebx = base; + regs.ecx = size; + regs.edx = type; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return regs.eax; + } + return MTRR_enableWriteCombine(base,size,type); +#else + return PM_MTRR_NOT_SUPPORTED; +#endif +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return true; } + +long PMAPI PM_getOSType(void) +{ return _OS_DOS; } + +int PMAPI PM_getModeType(void) +{ +#if defined(REALMODE) + return PM_realMode; +#elif defined(PM286) + return PM_286; +#elif defined(PM386) + return PM_386; +#endif +} + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + fprintf(stderr,"%s\n", msg); + exit(1); +} + +static void ExitVBEBuf(void) +{ + if (VESABuf_ptr) + PM_freeRealSeg(VESABuf_ptr); + VESABuf_ptr = 0; +} + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) +{ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + atexit(ExitVBEBuf); + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out) +{ + PMSREGS sregs; + PM_segread(&sregs); + return PM_int386x(intno,in,out,&sregs); +} + +/* Routines to set and get the real mode interrupt vectors, by making + * direct real mode calls to DOS and bypassing the DOS extenders API. + * This is the safest way to handle this, as some servers try to be + * smart about changing real mode vectors. + */ + +void PMAPI _PM_getRMvect(int intno, long *realisr) +{ + RMREGS regs; + RMSREGS sregs; + + PM_saveDS(); + regs.h.ah = 0x35; + regs.h.al = intno; + PM_int86x(0x21, ®s, ®s, &sregs); + *realisr = ((long)sregs.es << 16) | regs.x.bx; +} + +void PMAPI _PM_setRMvect(int intno, long realisr) +{ + RMREGS regs; + RMSREGS sregs; + + PM_saveDS(); + regs.h.ah = 0x25; + regs.h.al = intno; + sregs.ds = (int)(realisr >> 16); + regs.x.dx = (int)(realisr & 0xFFFF); + PM_int86x(0x21, ®s, ®s, &sregs); +} + +void PMAPI _PM_addRealModeBlock(void *mem,uint tag) +{ + int i; + + for (i = 0; i < MAX_RM_BLOCKS; i++) { + if (rmBlocks[i].p == NULL) { + rmBlocks[i].p = mem; + rmBlocks[i].tag = tag; + return; + } + } + PM_fatalError("To many real mode memory block allocations!"); +} + +uint PMAPI _PM_findRealModeBlock(void *mem) +{ + int i; + + for (i = 0; i < MAX_RM_BLOCKS; i++) { + if (rmBlocks[i].p == mem) + return rmBlocks[i].tag; + } + PM_fatalError("Could not find prior real mode memory block allocation!"); + return 0; +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +char PMAPI PM_getBootDrive(void) +{ return 'C'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return "c:\\"; } + +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[256]; + char *env; + + if ((env = getenv("NUCLEUS_PATH")) != NULL) + return env; + if ((env = getenv("WINBOOTDIR")) != NULL) { + /* Running in a Windows 9x DOS box or DOS mode */ + strcpy(path,env); + strcat(path,"\\system\\nucleus"); + return path; + } + if ((env = getenv("SystemRoot")) != NULL) { + /* Running in an NT/2K DOS box */ + strcpy(path,env); + strcat(path,"\\system32\\nucleus"); + return path; + } + return "c:\\nucleus"; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ return "DOS"; } + +const char * PMAPI PM_getMachineName(void) +{ return "DOS"; } + +int PMAPI PM_kbhit(void) +{ + return kbhit(); +} + +int PMAPI PM_getch(void) +{ + return getch(); +} + +PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen) +{ + /* Not used for DOS */ + (void)hwndUser; + (void)device; + (void)xRes; + (void)yRes; + (void)bpp; + (void)fullScreen; + return 0; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + return sizeof(DOS_stateBuf); +} + +void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole) +{ + RMREGS regs; + DOS_stateBuf *sb = stateBuf; + + /* Save the old video mode state */ + regs.h.ah = 0x0F; + PM_int86(0x10,®s,®s); + sb->oldMode = regs.h.al & 0x7F; + sb->old50Lines = false; + if (sb->oldMode == 0x3) { + regs.x.ax = 0x1130; + regs.x.bx = 0; + regs.x.dx = 0; + PM_int86(0x10,®s,®s); + sb->old50Lines = (regs.h.dl == 42 || regs.h.dl == 49); + } + (void)hwndConsole; +} + +void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) +{ + /* Not used for DOS */ + (void)saveState; +} + +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) +{ + RMREGS regs; + const DOS_stateBuf *sb = stateBuf; + + /* Retore 50 line mode if set */ + if (sb->old50Lines) { + regs.x.ax = 0x1112; + regs.x.bx = 0; + PM_int86(0x10,®s,®s); + } + (void)hwndConsole; +} + +void PMAPI PM_closeConsole(PM_HWND hwndConsole) +{ + /* Not used for DOS */ + (void)hwndConsole; +} + +void PMAPI PM_setOSCursorLocation(int x,int y) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x50,x); + PM_setByte(_biosPtr+0x51,y); +} + +void PMAPI PM_setOSScreenWidth(int width,int height) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setWord(_biosPtr+0x4A,width); + PM_setWord(_biosPtr+0x4C,width*2); + PM_setByte(_biosPtr+0x84,height-1); + if (height > 25) { + PM_setWord(_biosPtr+0x60,0x0607); + PM_setByte(_biosPtr+0x85,0x08); + } + else { + PM_setWord(_biosPtr+0x60,0x0D0E); + PM_setByte(_biosPtr+0x85,0x016); + } +} + +void * PMAPI PM_mallocShared(long size) +{ + return PM_malloc(size); +} + +void PMAPI PM_freeShared(void *ptr) +{ + PM_free(ptr); +} + +#define GetRMVect(intno,isr) *(isr) = ((ulong*)rmZeroPtr)[intno] +#define SetRMVect(intno,isr) ((ulong*)rmZeroPtr)[intno] = (isr) + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + static int firstTime = true; + static uchar *rmZeroPtr; + long Current10,Current6D,Current42; + RMREGS regs; + RMSREGS sregs; + + /* Create a zero memory mapping for us to use */ + if (firstTime) { + rmZeroPtr = PM_mapPhysicalAddr(0,0x7FFF,true); + firstTime = false; + } + + /* Remap the secondary BIOS to 0xC0000 physical */ + if (BIOSPhysAddr != 0xC0000L || BIOSLen > 32768) { + /* DOS cannot virtually remap the BIOS, so we can only work if all + * the secondary controllers are identical, and we then use the + * BIOS on the first controller for all the remaining controllers. + * + * For OS'es that do virtual memory, and remapping of 0xC0000 + * physical (perhaps a copy on write mapping) should be all that + * is needed. + */ + return false; + } + + /* Save current handlers of int 10h and 6Dh */ + GetRMVect(0x10,&Current10); + GetRMVect(0x6D,&Current6D); + + /* POST the secondary BIOS */ + GetRMVect(0x42,&Current42); + SetRMVect(0x10,Current42); /* Restore int 10h to STD-BIOS */ + regs.x.ax = axVal; + PM_callRealMode(0xC000,0x0003,®s,&sregs); + + /* Restore current handlers */ + SetRMVect(0x10,Current10); + SetRMVect(0x6D,Current6D); + + /* Second the primary BIOS mappin 1:1 for 0xC0000 physical */ + if (BIOSPhysAddr != 0xC0000L) { + /* DOS does not support this */ + (void)mappedBIOS; + } + return true; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + ulong microseconds = milliseconds * 1000L; + LZTimerObject tm; + + LZTimerOnExt(&tm); + while (LZTimerLapExt(&tm) < microseconds) + ; + LZTimerOffExt(&tm); +} + +int PMAPI PM_getCOMPort(int port) +{ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + (void)hModule; +} + +int PMAPI PM_setIOPL( + int level) +{ + return level; +} + +/**************************************************************************** +REMARKS: +Internal function to convert the find data to the generic interface. +****************************************************************************/ +static void convertFindData( + PM_findData *findData, + struct find_t *blk) +{ + ulong dwSize = findData->dwSize; + + memset(findData,0,findData->dwSize); + findData->dwSize = dwSize; + if (blk->attrib & _A_RDONLY) + findData->attrib |= PM_FILE_READONLY; + if (blk->attrib & _A_SUBDIR) + findData->attrib |= PM_FILE_DIRECTORY; + if (blk->attrib & _A_ARCH) + findData->attrib |= PM_FILE_ARCHIVE; + if (blk->attrib & _A_HIDDEN) + findData->attrib |= PM_FILE_HIDDEN; + if (blk->attrib & _A_SYSTEM) + findData->attrib |= PM_FILE_SYSTEM; + findData->sizeLo = blk->size; + strncpy(findData->name,blk->name,PM_MAX_PATH); + findData->name[PM_MAX_PATH-1] = 0; +} + +#define FIND_MASK (_A_RDONLY | _A_ARCH | _A_SUBDIR | _A_HIDDEN | _A_SYSTEM) + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void * PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + struct find_t *blk; + + if ((blk = PM_malloc(sizeof(*blk))) == NULL) + return PM_FILE_INVALID; + if (_dos_findfirst((char*)filename,FIND_MASK,blk) == 0) { + convertFindData(findData,blk); + return blk; + } + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + struct find_t *blk = handle; + + if (_dos_findnext(blk) == 0) { + convertFindData(findData,blk); + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + PM_free(handle); +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + RMREGS regs; + regs.h.dl = (uchar)(drive - 'A' + 1); + regs.h.ah = 0x36; /* Get disk information service */ + PM_int86(0x21,®s,®s); + return regs.x.ax != 0xFFFF; /* AX = 0xFFFF if disk is invalid */ +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + uint oldDrive,maxDrives; + _dos_getdrive(&oldDrive); + _dos_setdrive(drive,&maxDrives); + getcwd(dir,len); + _dos_setdrive(oldDrive,&maxDrives); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ +#if defined(TNT) && defined(_MSC_VER) + DWORD attr = 0; + + if (attrib & PM_FILE_READONLY) + attr |= FILE_ATTRIBUTE_READONLY; + if (attrib & PM_FILE_ARCHIVE) + attr |= FILE_ATTRIBUTE_ARCHIVE; + if (attrib & PM_FILE_HIDDEN) + attr |= FILE_ATTRIBUTE_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + attr |= FILE_ATTRIBUTE_SYSTEM; + SetFileAttributes((LPSTR)filename, attr); +#else + uint attr = 0; + + if (attrib & PM_FILE_READONLY) + attr |= _A_RDONLY; + if (attrib & PM_FILE_ARCHIVE) + attr |= _A_ARCH; + if (attrib & PM_FILE_HIDDEN) + attr |= _A_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + attr |= _A_SYSTEM; + _dos_setfileattr(filename,attr); +#endif +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ +#ifdef __GNUC__ + return mkdir(filename,S_IRUSR) == 0; +#else + return mkdir(filename) == 0; +#endif +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return rmdir(filename) == 0; +} + +/*-------------------------------------------------------------------------*/ +/* Generic DPMI routines common to 16/32 bit code */ +/*-------------------------------------------------------------------------*/ + +#ifndef REALMODE +ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit) +{ + PMREGS r; + int i; + ulong baseAddr,baseOfs,roundedLimit; + + /* We can't map memory below 1Mb, but the linear address are already + * mapped 1:1 for this memory anyway so we just return the base address. + */ + if (physAddr < 0x100000L) + return physAddr; + + /* Search table of existing mappings to see if we have already mapped + * a region of memory that will serve this purpose. We do this because + * DPMI 0.9 does not allow us to free physical memory mappings, and if + * the mappings get re-used in the program we want to avoid allocating + * more mappings than necessary. + */ + for (i = 0; i < numMaps; i++) { + if (maps[i].physical == physAddr && maps[i].limit == limit) + return maps[i].linear; + } + + /* Find a free slot in our physical memory mapping table */ + for (i = 0; i < numMaps; i++) { + if (maps[i].limit == 0) + break; + } + if (i == numMaps) { + i = numMaps++; + if (i == MAX_MEMORY_MAPPINGS) + return NULL; + } + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to DPMI as some extenders + * will fail the calls unless this is the case. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + baseOfs = physAddr & 4095; + baseAddr = physAddr & ~4095; + roundedLimit = ((limit+baseOfs+1+4095) & ~4095)-1; + r.x.ax = 0x800; + r.x.bx = baseAddr >> 16; + r.x.cx = baseAddr & 0xFFFF; + r.x.si = roundedLimit >> 16; + r.x.di = roundedLimit & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0xFFFFFFFFUL; + maps[i].physical = physAddr; + maps[i].limit = limit; + maps[i].linear = ((ulong)r.x.bx << 16) + r.x.cx + baseOfs; + return maps[i].linear; +} + +int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr) +{ + PMREGS r; + + r.x.ax = 7; /* DPMI set selector base address */ + r.x.bx = sel; + r.x.cx = linAddr >> 16; + r.x.dx = linAddr & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0; + return 1; +} + +ulong PMAPI DPMI_getSelectorBase(ushort sel) +{ + PMREGS r; + + r.x.ax = 6; /* DPMI get selector base address */ + r.x.bx = sel; + PM_int386(0x31, &r, &r); + return ((ulong)r.x.cx << 16) + r.x.dx; +} + +int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit) +{ + PMREGS r; + + r.x.ax = 8; /* DPMI set selector limit */ + r.x.bx = sel; + r.x.cx = limit >> 16; + r.x.dx = limit & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0; + return 1; +} + +uint PMAPI DPMI_createSelector(ulong base,ulong limit) +{ + uint sel; + PMREGS r; + + /* Allocate 1 descriptor */ + r.x.ax = 0; + r.x.cx = 1; + PM_int386(0x31, &r, &r); + if (r.x.cflag) return 0; + sel = r.x.ax; + + /* Set the descriptor access rights (for a 32 bit page granular + * segment). + */ + if (limit >= 0x10000L) { + r.x.ax = 9; + r.x.bx = sel; + r.x.cx = 0x40F3; + PM_int386(0x31, &r, &r); + } + + /* Map physical memory and create selector */ + if ((base = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFFUL) + return 0; + if (!DPMI_setSelectorBase(sel,base)) + return 0; + if (!DPMI_setSelectorLimit(sel,limit)) + return 0; + return sel; +} + +void PMAPI DPMI_freeSelector(uint sel) +{ + PMREGS r; + + r.x.ax = 1; + r.x.bx = sel; + PM_int386(0x31, &r, &r); +} + +int PMAPI DPMI_lockLinearPages(ulong linear,ulong len) +{ + PMREGS r; + + r.x.ax = 0x600; /* DPMI Lock Linear Region */ + r.x.bx = (linear >> 16); /* Linear address in BX:CX */ + r.x.cx = (linear & 0xFFFF); + r.x.si = (len >> 16); /* Length in SI:DI */ + r.x.di = (len & 0xFFFF); + PM_int386(0x31, &r, &r); + return (!r.x.cflag); +} + +int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len) +{ + PMREGS r; + + r.x.ax = 0x601; /* DPMI Unlock Linear Region */ + r.x.bx = (linear >> 16); /* Linear address in BX:CX */ + r.x.cx = (linear & 0xFFFF); + r.x.si = (len >> 16); /* Length in SI:DI */ + r.x.di = (len & 0xFFFF); + PM_int386(0x31, &r, &r); + return (!r.x.cflag); +} + +/**************************************************************************** +REMARKS: +Adjust the page table caching bits directly. Requires ring 0 access and +only works with DOS4GW and compatible extenders (CauseWay also works since +it has direct support for the ring 0 instructions we need from ring 3). Will +not work in a DOS box, but we call into the ring 0 helper VxD so we should +never get here in a DOS box anyway (assuming the VxD is present). If we +do get here and we are in windows, this code will be skipped. +****************************************************************************/ +static void PM_adjustPageTables( + ulong linear, + ulong limit, + ibool isCached) +{ +#ifdef DOS4GW + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong andMask,orMask,pageTable,*pPageTable; + + andMask = ~0x18; + orMask = (isCached) ? 0x00 : 0x18; + if (_PM_pagingEnabled() == 1 && (PDB = _PM_getPDB()) != 0) { + if (_PM_haveCauseWay) { + /* CauseWay is a little different in the page table handling. + * The code that we use for DOS4G/W does not appear to work + * with CauseWay correctly as it does not appear to allow us + * to map the page tables directly. Instead we can directly + * access the page table entries in extended memory where + * CauseWay always locates them (starting at 1024*4096*1023) + */ + startPage = (linear >> 12); + endPage = ((linear+limit) >> 12); + pPageTable = (ulong*)CW_PAGE_TABLE_START; + for (iPage = startPage; iPage <= endPage; iPage++) + pPageTable[iPage] = (pPageTable[iPage] & andMask) | orMask; + } + else { + pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF); + if (pPDB) { + startPDB = (linear >> 22) & 0x3FF; + startPage = (linear >> 12) & 0x3FF; + endPDB = ((linear+limit) >> 22) & 0x3FF; + endPage = ((linear+limit) >> 12) & 0x3FF; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + pageTable = pPDB[iPDB] & ~0xFFF; + pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF); + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FF; + for (iPage = start; iPage <= end; iPage++) + pPageTable[iPage] = (pPageTable[iPage] & andMask) | orMask; + } + } + } + PM_flushTLB(); + } +#endif +} + +void * PMAPI DPMI_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + PMSREGS sregs; + ulong linAddr; + ulong DSBaseAddr; + + /* Get the base address for the default DS selector */ + PM_segread(&sregs); + DSBaseAddr = DPMI_getSelectorBase(sregs.ds); + if ((base < 0x100000) && (DSBaseAddr == 0)) { + /* DS is zero based, so we can directly access the first 1Mb of + * system memory (like under DOS4GW). + */ + return (void*)base; + } + + /* Map the memory to a linear address using DPMI function 0x800 */ + if ((linAddr = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFF) { + if (base >= 0x100000) + return NULL; + /* If the linear address mapping fails but we are trying to + * map an area in the first 1Mb of system memory, then we must + * be running under a Windows or OS/2 DOS box. Under these + * environments we can use the segment wrap around as a fallback + * measure, as this does work properly. + */ + linAddr = base; + } + + /* Now expand the default DS selector to 4Gb so we can access it */ + if (!DPMI_setSelectorLimit(sregs.ds,0xFFFFFFFFUL)) + return NULL; + + /* Finally enable caching for the page tables that we just mapped in, + * since DOS4GW and PMODE/W create the page table entries without + * caching enabled which hurts the performance of the linear framebuffer + * as it disables write combining on Pentium Pro and above processors. + * + * For those processors cache disabling is better handled through the + * MTRR registers anyway (we can write combine a region but disable + * caching) so that MMIO register regions do not screw up. + */ + if (DSBaseAddr == 0) + PM_adjustPageTables(linAddr,limit,isCached); + + /* Now return the base address of the memory into the default DS */ + return (void*)(linAddr - DSBaseAddr); +} + +#if defined(PM386) + +/* Some DOS extender implementations do not directly support calling a + * real mode procedure from protected mode. However we can simulate what + * we need temporarily hooking the INT 6Ah vector with a small real mode + * stub that will call our real mode code for us. + */ + +static uchar int6AHandler[] = { + 0x00,0x00,0x00,0x00, /* __PMODE_callReal variable */ + 0xFB, /* sti */ + 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PMODE_callReal] */ + 0xCF, /* iretf */ + }; +static uchar *crPtr = NULL; /* Pointer to of int 6A handler */ +static uint crRSeg,crROff; /* Real mode seg:offset of handler */ + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, + RMSREGS *sregs) +{ + uchar *p; + uint oldSeg,oldOff; + + if (!crPtr) { + /* Allocate and copy the memory block only once */ + crPtr = PM_allocRealSeg(sizeof(int6AHandler), &crRSeg, &crROff); + memcpy(crPtr,int6AHandler,sizeof(int6AHandler)); + } + PM_setWord(crPtr,off); /* Plug in address to call */ + PM_setWord(crPtr+2,seg); + p = PM_mapRealPointer(0,0x6A * 4); + oldOff = PM_getWord(p); /* Save old handler address */ + oldSeg = PM_getWord(p+2); + PM_setWord(p,crROff+4); /* Hook 6A handler */ + PM_setWord(p+2,crRSeg); + PM_int86x(0x6A, in, in, sregs); /* Call real mode code */ + PM_setWord(p,oldOff); /* Restore old handler */ + PM_setWord(p+2,oldSeg); +} + +#endif /* PM386 */ + +#endif /* !REALMODE */ + +/**************************************************************************** +REMARKS: +Allocates a block of locked, physically contiguous memory. The memory +may be required to be below the 16Meg boundary. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16Meg) +{ + uchar *p,*roundedP; + uint r_seg,r_off; + uint roundedSize = (size + 4 + 0xFFF) & ~0xFFF; + PM_lockHandle lh; /* Unused in DOS */ +#ifndef REALMODE + VXD_regs regs; + + /* If we have connected to our helper VxD in a Windows DOS box, use the + * helper VxD services to allocate the memory that we need. + */ + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_ALLOCLOCKED); + regs.ebx = size; + regs.ecx = (ulong)physAddr; + regs.edx = contiguous | (below16Meg << 8); + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return (void*)regs.eax; + } + + /* If the memory is not contiguous, we simply need to allocate it + * using regular memory allocation services, and lock it down + * in memory. + * + * For contiguous memory blocks, the only way to guarantee contiguous physical + * memory addresses under DOS is to allocate the memory below the + * 1Meg boundary as real mode memory. + * + * Note that we must page align the memory block, and we also must + * keep track of the non-aligned pointer so we can properly free + * it later. Hence we actually allocate 4 bytes more than the + * size rounded up to the next 4K boundary. + */ + if (!contiguous) + p = PM_malloc(roundedSize); + else +#endif + p = PM_allocRealSeg(roundedSize,&r_seg,&r_off); + if (p == NULL) + return NULL; + roundedP = (void*)(((ulong)p + 0xFFF) & ~0xFFF); + *((ulong*)(roundedP + size)) = (ulong)p; + PM_lockDataPages(roundedP,size,&lh); + if ((*physAddr = PM_getPhysicalAddr(roundedP)) == 0xFFFFFFFF) { + PM_freeLockedMem(roundedP,size,contiguous); + return NULL; + } + + /* Disable caching for the memory since it is probably a DMA buffer */ +#ifndef REALMODE + PM_adjustPageTables((ulong)roundedP,size-1,false); +#endif + return roundedP; +} + +/**************************************************************************** +REMARKS: +Free a block of locked memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) +{ +#ifndef REALMODE + VXD_regs regs; + PM_lockHandle lh; /* Unused in DOS */ + + if (!p) + return; + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_FREELOCKED); + regs.ebx = (ulong)p; + regs.ecx = size; + regs.edx = contiguous; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return; + } + PM_unlockDataPages(p,size,&lh); + if (!contiguous) + free(*((void**)((uchar*)p + size))); + else +#endif + PM_freeRealSeg(*((void**)((char*)p + size))); +} + +#ifndef REALMODE +/**************************************************************************** +REMARKS: +Allocates a new block of pages for the page block manager. +****************************************************************************/ +static pageblock *PM_addNewPageBlock(void) +{ + int i,size; + pageblock *newBlock; + char *p,*next; + + /* Allocate memory for the new page block, and add to head of list */ + size = PAGES_PER_BLOCK * PM_PAGE_SIZE + (PM_PAGE_SIZE-1) + sizeof(pageblock); + if ((newBlock = PM_malloc(size)) == NULL) + return NULL; + newBlock->prev = NULL; + newBlock->next = pageBlocks; + if (pageBlocks) + pageBlocks->prev = newBlock; + pageBlocks = newBlock; + + /* Initialise the page aligned free list for the page block */ + newBlock->freeCount = PAGES_PER_BLOCK; + newBlock->freeList = p = (char*)(((ulong)(newBlock + 1) + (PM_PAGE_SIZE-1)) & ~(PM_PAGE_SIZE-1)); + newBlock->freeListStart = newBlock->freeList; + newBlock->freeListEnd = p + (PAGES_PER_BLOCK-1) * PM_PAGE_SIZE; + for (i = 0; i < PAGES_PER_BLOCK; i++,p = next) + FREELIST_NEXT(p) = next = p + PM_PAGE_SIZE; + FREELIST_NEXT(p - PM_PAGE_SIZE) = NULL; + return newBlock; +} +#endif + +/**************************************************************************** +REMARKS: +Allocates a page aligned and page sized block of memory +****************************************************************************/ +void * PMAPI PM_allocPage( + ibool locked) +{ +#ifndef REALMODE + VXD_regs regs; + pageblock *block; + void *p; + PM_lockHandle lh; /* Unused in DOS */ + + /* Call the helper VxD for this service if we are running in a DOS box */ + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_ALLOCPAGE); + regs.ebx = locked; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return (void*)regs.eax; + } + + /* Scan the block list looking for any free blocks. Allocate a new + * page block if no free blocks are found. + */ + for (block = pageBlocks; block != NULL; block = block->next) { + if (block->freeCount) + break; + } + if (block == NULL && (block = PM_addNewPageBlock()) == NULL) + return NULL; + block->freeCount--; + p = block->freeList; + block->freeList = FREELIST_NEXT(p); + if (locked) + PM_lockDataPages(p,PM_PAGE_SIZE,&lh); + return p; +#else + return NULL; +#endif +} + +/**************************************************************************** +REMARKS: +Free a page aligned and page sized block of memory +****************************************************************************/ +void PMAPI PM_freePage( + void *p) +{ +#ifndef REALMODE + VXD_regs regs; + pageblock *block; + + /* Call the helper VxD for this service if we are running in a DOS box */ + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_FREEPAGE); + regs.ebx = (ulong)p; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return; + } + + /* First find the page block that this page belongs to */ + for (block = pageBlocks; block != NULL; block = block->next) { + if (p >= block->freeListStart && p <= block->freeListEnd) + break; + } + CHECK(block != NULL); + + /* Now free the block by adding it to the free list */ + FREELIST_NEXT(p) = block->freeList; + block->freeList = p; + if (++block->freeCount == PAGES_PER_BLOCK) { + /* If all pages in the page block are now free, free the entire + * page block itself. + */ + if (block == pageBlocks) { + /* Delete from head */ + pageBlocks = block->next; + if (block->next) + block->next->prev = NULL; + } + else { + /* Delete from middle of list */ + CHECK(block->prev != NULL); + block->prev->next = block->next; + if (block->next) + block->next->prev = block->prev; + } + PM_free(block); + } +#else + (void)p; +#endif +} + +/*-------------------------------------------------------------------------*/ +/* DOS Real Mode support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef REALMODE + +#ifndef MK_FP +#define MK_FP(s,o) ( (void far *)( ((ulong)(s) << 16) + \ + (ulong)(o) )) +#endif + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ return MK_FP(r_seg,r_off); } + +void * PMAPI PM_getBIOSPointer(void) +{ + return MK_FP(0x40,0); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + return MK_FP(0xA000,0); +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + uint sel = base >> 4; + uint off = base & 0xF; + limit = limit; + return MK_FP(sel,off); +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ ptr = ptr; } + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + return ((((ulong)p >> 16) << 4) + (ushort)p); +} + +ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) +{ return false; } + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + /* Call malloc() to allocate the memory for us */ + void *p = PM_malloc(size); + *r_seg = FP_SEG(p); + *r_off = FP_OFF(p); + return p; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + if (mem) PM_free(mem); +} + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + return PM_int386(intno,in,out); +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + return PM_int386x(intno,in,out,sregs); +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + PMREGS regs; + + regs.h.ah = 0x48; + regs.x.bx = 0xFFFF; + PM_int86(0x21,®s,®s); + *physical = *total = regs.x.bx * 16UL; +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Phar Lap TNT DOS Extender support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef TNT + +#include +#include +#include + +static uchar *zeroPtr = NULL; + +void * PMAPI PM_getBIOSPointer(void) +{ + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); + return (void*)(zeroPtr + 0x400); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + static void *bankPtr; + if (!bankPtr) + bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); + return bankPtr; +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + CONFIG_INF config; + ULONG offset; + int err; + ulong baseAddr,baseOfs,newLimit; + VXD_regs regs; + + /* If we have connected to our helper VxD in a Windows DOS box, use + * the helper VxD services to map memory instead of the DPMI services. + * We do this because the helper VxD can properly disable caching + * where necessary, which we can only do directly here if we are + * running at ring 0 (ie: under real DOS). + */ + if (VXD_version == -1) + PM_init(); + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_MAPPHYS); + regs.ebx = base; + regs.ecx = limit; + regs.edx = isCached; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return (void*)regs.eax; + } + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to TNT. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + baseOfs = base & 4095; + baseAddr = base & ~4095; + newLimit = ((limit+baseOfs+1+4095) & ~4095)-1; + _dx_config_inf(&config, (UCHAR*)&config); + err = _dx_map_phys(config.c_ds_sel,baseAddr,(newLimit + 4095) / 4096,&offset); + if (err == 130) { + /* If the TNT function failed, we are running in a DPMI environment + * and this function does not work. However we know how to handle + * DPMI properly, so we use our generic DPMI functions to do + * what the TNT runtime libraries can't. + */ + return DPMI_mapPhysicalAddr(base,limit,isCached); + } + if (err == 0) + return (void*)(offset + baseOfs); + return NULL; +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ return 0xFFFFFFFFUL; } + +ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) +{ return false; } + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF); + return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + USHORT addr,t; + void *p; + + if (_dx_real_alloc((size + 0xF) >> 4,&addr,&t) != 0) + return 0; + *r_seg = addr; /* Real mode segment address */ + *r_off = 0; /* Real mode segment offset */ + p = PM_mapRealPointer(*r_seg,*r_off); + _PM_addRealModeBlock(p,addr); + return p; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + if (mem) _dx_real_free(_PM_findRealModeBlock(mem)); +} + +#define INDPMI(reg) rmregs.reg = regs->reg +#define OUTDPMI(reg) regs->reg = rmregs.reg + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + SWI_REGS rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + INDPMI(eax); INDPMI(ebx); INDPMI(ecx); INDPMI(edx); INDPMI(esi); INDPMI(edi); + + _dx_real_int(intno,&rmregs); + + OUTDPMI(eax); OUTDPMI(ebx); OUTDPMI(ecx); OUTDPMI(edx); OUTDPMI(esi); OUTDPMI(edi); + regs->flags = rmregs.flags; +} + +#define IN(reg) rmregs.reg = in->e.reg +#define OUT(reg) out->e.reg = rmregs.reg + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + SWI_REGS rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + + _dx_real_int(intno,&rmregs); + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + SWI_REGS rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + rmregs.es = sregs->es; + rmregs.ds = sregs->ds; + + _dx_real_int(intno,&rmregs); + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + sregs->es = rmregs.es; + sregs->cs = rmregs.cs; + sregs->ss = rmregs.ss; + sregs->ds = rmregs.ds; + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + PMREGS r; + uint data[25]; + + r.x.ax = 0x2520; /* Get free memory info */ + r.x.bx = 0; + r.e.edx = (uint)data; + PM_int386(0x21, &r, &r); + *physical = data[21] * 4096; + *total = data[23] * 4096; +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Symantec C++ DOSX and FlashTek X-32/X-32VM support */ +/*-------------------------------------------------------------------------*/ + +#if defined(DOSX) || defined(X32VM) + +#ifdef X32VM +#include + +#define _x386_mk_protected_ptr(p) _x32_mk_protected_ptr((void*)p) +#define _x386_free_protected_ptr(p) _x32_free_protected_ptr(p) +#define _x386_zero_base_ptr _x32_zero_base_ptr +#else +extern void *_x386_zero_base_ptr; +#endif + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + return (void*)((ulong)_x386_zero_base_ptr + MK_PHYS(r_seg,r_off)); +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + PMREGS r; + + r.h.ah = 0x48; /* DOS function 48h - allocate mem */ + r.x.bx = (size + 0xF) >> 4; /* Number of paragraphs to allocate */ + PM_int386(0x21, &r, &r); /* Call DOS extender */ + if (r.x.cflag) + return 0; /* Could not allocate the memory */ + *r_seg = r.e.eax; + *r_off = 0; + return PM_mapRealPointer(*r_seg,*r_off); +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + /* Cannot de-allocate this memory */ + mem = mem; +} + +#pragma pack(1) + +typedef struct { + ushort intno; + ushort ds; + ushort es; + ushort fs; + ushort gs; + ulong eax; + ulong edx; + } _RMREGS; + +#pragma pack() + +#define IN(reg) regs.e.reg = in->e.reg +#define OUT(reg) out->e.reg = regs.e.reg + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + _RMREGS rmregs; + PMREGS regs; + PMSREGS pmsregs; + + rmregs.intno = intno; + rmregs.eax = in->e.eax; + rmregs.edx = in->e.edx; + IN(ebx); IN(ecx); IN(esi); IN(edi); + regs.x.ax = 0x2511; + regs.e.edx = (uint)(&rmregs); + PM_segread(&pmsregs); + PM_int386x(0x21,®s,®s,&pmsregs); + + OUT(eax); OUT(ebx); OUT(ecx); OUT(esi); OUT(edi); + out->x.dx = rmregs.edx; + out->x.cflag = regs.x.cflag; + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, RMSREGS *sregs) +{ + _RMREGS rmregs; + PMREGS regs; + PMSREGS pmsregs; + + rmregs.intno = intno; + rmregs.eax = in->e.eax; + rmregs.edx = in->e.edx; + rmregs.es = sregs->es; + rmregs.ds = sregs->ds; + IN(ebx); IN(ecx); IN(esi); IN(edi); + regs.x.ax = 0x2511; + regs.e.edx = (uint)(&rmregs); + PM_segread(&pmsregs); + PM_int386x(0x21,®s,®s,&pmsregs); + + OUT(eax); OUT(ebx); OUT(ecx); OUT(esi); OUT(edi); + sregs->es = rmregs.es; + sregs->ds = rmregs.ds; + out->x.dx = rmregs.edx; + out->x.cflag = regs.x.cflag; + return out->x.ax; +} + +void * PMAPI PM_getBIOSPointer(void) +{ + return (void*)((ulong)_x386_zero_base_ptr + 0x400); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + return (void*)((ulong)_x386_zero_base_ptr + 0xA0000); +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + VXD_regs regs; + + /* If we have connected to our helper VxD in a Windows DOS box, use + * the helper VxD services to map memory instead of the DPMI services. + * We do this because the helper VxD can properly disable caching + * where necessary, which we can only do directly here if we are + * running at ring 0 (ie: under real DOS). + */ + if (VXD_version == -1) + PM_init(); + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_MAPPHYS); + regs.ebx = base; + regs.ecx = limit; + regs.edx = isCached; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return (void*)regs.eax; + } + + if (base > 0x100000) + return _x386_map_physical_address((void*)base,limit); + return (void*)((ulong)_x386_zero_base_ptr + base); +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + /* Mapping cannot be freed */ +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ return 0xFFFFFFFFUL; } + +ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) +{ return false; } + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +ulong _cdecl _X32_getPhysMem(void); + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + PMREGS regs; + + /* Get total memory available, including virtual memory */ + regs.x.ax = 0x350B; + PM_int386(0x21,®s,®s); + *total = regs.e.eax; + + /* Get physical memory available */ + *physical = _X32_getPhysMem(); + if (*physical > *total) + *physical = *total; +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Borland's DPMI32, Watcom DOS4GW and DJGPP DPMI support routines */ +/*-------------------------------------------------------------------------*/ + +#if defined(DPMI32) || defined(DOS4GW) || defined(DJGPP) + +void * PMAPI PM_getBIOSPointer(void) +{ + return PM_mapPhysicalAddr(0x400,0xFFFF,true); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + VXD_regs regs; + +#ifdef DJGPP + /* Enable near pointers for DJGPP V2 */ + __djgpp_nearptr_enable(); +#endif + /* If we have connected to our helper VxD in a Windows DOS box, use + * the helper VxD services to map memory instead of the DPMI services. + * We do this because the helper VxD can properly disable caching + * where necessary, which we can only do directly here if we are + * running at ring 0 (ie: under real DOS). + */ + if (VXD_version == -1) + PM_init(); + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_MAPPHYS); + regs.ebx = base; + regs.ecx = limit; + regs.edx = isCached; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return (void*)regs.eax; + } + return DPMI_mapPhysicalAddr(base,limit,isCached); +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + /* Mapping cannot be freed */ + (void)ptr; + (void)limit; +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + ulong physAddr; + if (!PM_getPhysicalAddrRange(p,1,&physAddr)) + return 0xFFFFFFFF; + return physAddr | ((ulong)p & 0xFFF); +} + +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + VXD_regs regs; + ulong pte; + PMSREGS sregs; + ulong DSBaseAddr; + + /* If we have connected to our helper VxD in a Windows DOS box, use the + * helper VxD services to find the physical address of an address. + */ + if (VXD_version) { + memset(®s,0,sizeof(regs)); + regs.eax = API_NUM(PMHELP_GETPHYSICALADDRRANGE); + regs.ebx = (ulong)p; + regs.ecx = (ulong)length; + regs.edx = (ulong)physAddress; + _PM_VxDCall(®s,_PM_VXD_off,_PM_VXD_sel); + return regs.eax; + } + + /* Find base address for default DS selector */ + PM_segread(&sregs); + DSBaseAddr = DPMI_getSelectorBase(sregs.ds); + + /* Otherwise directly access the page tables to determine the + * physical memory address. Note that we touch the memory before + * calling, otherwise the memory may not be paged in correctly. + */ + pte = *((ulong*)p); +#ifdef DOS4GW + if (_PM_pagingEnabled() == 0) { + int count; + ulong linAddr = (ulong)p; + + /* When paging is disabled physical=linear */ + for (count = (length+0xFFF) >> 12; count > 0; count--) { + *physAddress++ = linAddr; + linAddr += 4096; + } + return true; + } + else if ((PDB = _PM_getPDB()) != 0 && DSBaseAddr == 0) { + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong pageTable,*pPageTable,linAddr = (ulong)p; + ulong limit = length-1; + + pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF); + if (pPDB) { + startPDB = (linAddr >> 22) & 0x3FFL; + startPage = (linAddr >> 12) & 0x3FFL; + endPDB = ((linAddr+limit) >> 22) & 0x3FFL; + endPage = ((linAddr+limit) >> 12) & 0x3FFL; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + pageTable = pPDB[iPDB] & ~0xFFFL; + pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF); + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FFL; + for (iPage = start; iPage <= end; iPage++) + *physAddress++ = (pPageTable[iPage] & ~0xFFF); + } + return true; + } + } +#endif + return false; +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ + (void)limit; + return (void*)base; +} + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + static uchar *zeroPtr = NULL; + + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); + return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + PMREGS r; + void *p; + + r.x.ax = 0x100; /* DPMI allocate DOS memory */ + r.x.bx = (size + 0xF) >> 4; /* number of paragraphs */ + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return NULL; /* DPMI call failed */ + *r_seg = r.x.ax; /* Real mode segment */ + *r_off = 0; + p = PM_mapRealPointer(*r_seg,*r_off); + _PM_addRealModeBlock(p,r.x.dx); + return p; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + PMREGS r; + + if (mem) { + r.x.ax = 0x101; /* DPMI free DOS memory */ + r.x.dx = _PM_findRealModeBlock(mem);/* DX := selector from 0x100 */ + PM_int386(0x31, &r, &r); + } +} + +static DPMI_handler_t DPMI_int10 = NULL; + +void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler) +{ + DPMI_int10 = handler; +} + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + PMREGS r; + PMSREGS sr; + + if (intno == 0x10 && DPMI_int10) { + if (DPMI_int10(regs)) + return; + } + PM_segread(&sr); + r.x.ax = 0x300; /* DPMI issue real interrupt */ + r.h.bl = intno; + r.h.bh = 0; + r.x.cx = 0; + sr.es = sr.ds; + r.e.edi = (uint)regs; + PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ +} + +#define IN(reg) rmregs.reg = in->e.reg +#define OUT(reg) out->e.reg = rmregs.reg + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + + DPMI_int86(intno,&rmregs); /* DPMI issue real interrupt */ + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + rmregs.es = sregs->es; + rmregs.ds = sregs->ds; + + DPMI_int86(intno,&rmregs); /* DPMI issue real interrupt */ + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + sregs->es = rmregs.es; + sregs->cs = rmregs.cs; + sregs->ss = rmregs.ss; + sregs->ds = rmregs.ds; + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +#pragma pack(1) + +typedef struct { + uint LargestBlockAvail; + uint MaxUnlockedPage; + uint LargestLockablePage; + uint LinAddrSpace; + uint NumFreePagesAvail; + uint NumPhysicalPagesFree; + uint TotalPhysicalPages; + uint FreeLinAddrSpace; + uint SizeOfPageFile; + uint res[3]; + } MemInfo; + +#pragma pack() + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + PMREGS r; + PMSREGS sr; + MemInfo memInfo; + + PM_segread(&sr); + r.x.ax = 0x500; /* DPMI get free memory info */ + sr.es = sr.ds; + r.e.edi = (uint)&memInfo; + PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ + *physical = memInfo.NumPhysicalPagesFree * 4096; + *total = memInfo.LargestBlockAvail; + if (*total < *physical) + *physical = *total; +} + +#endif + +#ifndef __16BIT__ + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankA( + int bank) +{ + DPMI_regs regs; + memset(®s, 0, sizeof(regs)); + regs.eax = 0x4F05; + regs.ebx = 0x0000; + regs.edx = bank; + DPMI_int86(0x10,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankAB( + int bank) +{ + DPMI_regs regs; + memset(®s, 0, sizeof(regs)); + regs.eax = 0x4F05; + regs.ebx = 0x0000; + regs.edx = bank; + DPMI_int86(0x10,®s); + regs.eax = 0x4F05; + regs.ebx = 0x0001; + regs.edx = bank; + DPMI_int86(0x10,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display start address. +****************************************************************************/ +void PMAPI PM_setCRTStart( + int x, + int y, + int waitVRT) +{ + DPMI_regs regs; + memset(®s, 0, sizeof(regs)); + regs.eax = 0x4F07; + regs.ebx = waitVRT; + regs.ecx = x; + regs.edx = y; + DPMI_int86(0x10,®s); +} + +#endif + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + /* TODO: Implement this! */ + return 0; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c b/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c new file mode 100644 index 000000000..eecc2daed --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/pmdos.c @@ -0,0 +1,1637 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 16/32 bit DOS +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include +#include +#include +#include + +/*--------------------------- Global variables ----------------------------*/ + +#ifndef REALMODE +static int globalDataStart; +#endif + +PM_criticalHandler _VARAPI _PM_critHandler = NULL; +PM_breakHandler _VARAPI _PM_breakHandler = NULL; +PM_intHandler _VARAPI _PM_timerHandler = NULL; +PM_intHandler _VARAPI _PM_rtcHandler = NULL; +PM_intHandler _VARAPI _PM_keyHandler = NULL; +PM_key15Handler _VARAPI _PM_key15Handler = NULL; +PM_mouseHandler _VARAPI _PM_mouseHandler = NULL; +PM_intHandler _VARAPI _PM_int10Handler = NULL; +int _VARAPI _PM_mouseMask; + +uchar * _VARAPI _PM_ctrlCPtr; /* Location of Ctrl-C flag */ +uchar * _VARAPI _PM_ctrlBPtr; /* Location of Ctrl-Break flag */ +uchar * _VARAPI _PM_critPtr; /* Location of Critical error Bf*/ +PMFARPTR _VARAPI _PM_prevTimer = PMNULL; /* Previous timer handler */ +PMFARPTR _VARAPI _PM_prevRTC = PMNULL; /* Previous RTC handler */ +PMFARPTR _VARAPI _PM_prevKey = PMNULL; /* Previous key handler */ +PMFARPTR _VARAPI _PM_prevKey15 = PMNULL; /* Previous key15 handler */ +PMFARPTR _VARAPI _PM_prevBreak = PMNULL; /* Previous break handler */ +PMFARPTR _VARAPI _PM_prevCtrlC = PMNULL; /* Previous CtrlC handler */ +PMFARPTR _VARAPI _PM_prevCritical = PMNULL; /* Previous critical handler */ +long _VARAPI _PM_prevRealTimer; /* Previous real mode timer */ +long _VARAPI _PM_prevRealRTC; /* Previous real mode RTC */ +long _VARAPI _PM_prevRealKey; /* Previous real mode key */ +long _VARAPI _PM_prevRealKey15; /* Previous real mode key15 */ +long _VARAPI _PM_prevRealInt10; /* Previous real mode int 10h */ +static uchar _PM_oldCMOSRegA; /* CMOS register A contents */ +static uchar _PM_oldCMOSRegB; /* CMOS register B contents */ +static uchar _PM_oldRTCPIC2; /* Mask value for RTC IRQ8 */ + +/* Structure to maintain information about hardware interrupt handlers, + * include a copy of the hardware IRQ assembler thunk (one for each + * hooked interrupt handler). + */ + +typedef struct { + uchar IRQ; + uchar IRQVect; + uchar prevPIC; + uchar prevPIC2; + PMFARPTR prevHandler; + long prevRealhandler; + uchar thunk[1]; + /* IRQ assembler thunk follows ... */ + } _PM_IRQHandle; + +/*----------------------------- Implementation ----------------------------*/ + +/* Globals for locking interrupt handlers in _pmdos.asm */ + +#ifndef REALMODE +extern int _VARAPI _PM_pmdosDataStart; +extern int _VARAPI _PM_pmdosDataEnd; +extern int _VARAPI _PM_DMADataStart; +extern int _VARAPI _PM_DMADataEnd; +void _ASMAPI _PM_pmdosCodeStart(void); +void _ASMAPI _PM_pmdosCodeEnd(void); +void _ASMAPI _PM_DMACodeStart(void); +void _ASMAPI _PM_DMACodeEnd(void); +#endif + +/* Protected mode interrupt handlers, also called by PM callbacks below */ + +void _ASMAPI _PM_timerISR(void); +void _ASMAPI _PM_rtcISR(void); +void _ASMAPI _PM_irqISRTemplate(void); +void _ASMAPI _PM_irqISRTemplateEnd(void); +void _ASMAPI _PM_keyISR(void); +void _ASMAPI _PM_key15ISR(void); +void _ASMAPI _PM_breakISR(void); +void _ASMAPI _PM_ctrlCISR(void); +void _ASMAPI _PM_criticalISR(void); +void _ASMAPI _PM_mouseISR(void); +void _ASMAPI _PM_int10PMCB(void); + +/* Protected mode DPMI callback handlers */ + +void _ASMAPI _PM_mousePMCB(void); + +/* Routine to install a mouse handler function */ + +void _ASMAPI _PM_setMouseHandler(int mask); + +/* Routine to allocate DPMI real mode callback routines */ + +ibool _ASMAPI _DPMI_allocateCallback(void (_ASMAPI *pmcode)(),void *rmregs,long *RMCB); +void _ASMAPI _DPMI_freeCallback(long RMCB); + +/* DPMI helper functions in PMLITE.C */ + +ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit); +int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr); +ulong PMAPI DPMI_getSelectorBase(ushort sel); +int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit); +uint PMAPI DPMI_createSelector(ulong base,ulong limit); +void PMAPI DPMI_freeSelector(uint sel); +int PMAPI DPMI_lockLinearPages(ulong linear,ulong len); +int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len); + +/* Functions to read and write CMOS registers */ + +uchar PMAPI _PM_readCMOS(int index); +void PMAPI _PM_writeCMOS(int index,uchar value); + +/*-------------------------------------------------------------------------*/ +/* Generic routines common to all environments */ +/*-------------------------------------------------------------------------*/ + +void PMAPI PM_resetMouseDriver(int hardReset) +{ + RMREGS regs; + PM_mouseHandler oldHandler = _PM_mouseHandler; + + PM_restoreMouseHandler(); + regs.x.ax = hardReset ? 0 : 33; + PM_int86(0x33, ®s, ®s); + if (oldHandler) + PM_setMouseHandler(_PM_mouseMask, oldHandler); +} + +void PMAPI PM_setRealTimeClockFrequency(int frequency) +{ + static short convert[] = { + 8192, + 4096, + 2048, + 1024, + 512, + 256, + 128, + 64, + 32, + 16, + 8, + 4, + 2, + -1, + }; + int i; + + /* First clear any pending RTC timeout if not cleared */ + _PM_readCMOS(0x0C); + if (frequency == 0) { + /* Disable RTC timout */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F); + } + else { + /* Convert frequency value to RTC clock indexes */ + for (i = 0; convert[i] != -1; i++) { + if (convert[i] == frequency) + break; + } + + /* Set RTC timout value and enable timeout */ + _PM_writeCMOS(0x0A,0x20 | (i+3)); + _PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40); + } +} + +#ifndef REALMODE + +static void PMAPI lockPMHandlers(void) +{ + static int locked = 0; + int stat; + PM_lockHandle lh; /* Unused in DOS */ + + /* Lock all of the code and data used by our protected mode interrupt + * handling routines, so that it will continue to work correctly + * under real mode. + */ + if (!locked) { + PM_saveDS(); + stat = !PM_lockDataPages(&globalDataStart-2048,4096,&lh); + stat |= !PM_lockDataPages(&_PM_pmdosDataStart,(int)&_PM_pmdosDataEnd - (int)&_PM_pmdosDataStart,&lh); + stat |= !PM_lockCodePages((__codePtr)_PM_pmdosCodeStart,(int)_PM_pmdosCodeEnd-(int)_PM_pmdosCodeStart,&lh); + stat |= !PM_lockDataPages(&_PM_DMADataStart,(int)&_PM_DMADataEnd - (int)&_PM_DMADataStart,&lh); + stat |= !PM_lockCodePages((__codePtr)_PM_DMACodeStart,(int)_PM_DMACodeEnd-(int)_PM_DMACodeStart,&lh); + if (stat) { + printf("Page locking services failed - interrupt handling not safe!\n"); + exit(1); + } + locked = 1; + } +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* DOS Real Mode support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef REALMODE + +#ifndef MK_FP +#define MK_FP(s,o) ( (void far *)( ((ulong)(s) << 16) + \ + (ulong)(o) )) +#endif + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + PM_saveDS(); + _PM_mouseHandler = mh; + _PM_setMouseHandler(_PM_mouseMask = mask); + return 1; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + union REGS regs; + + if (_PM_mouseHandler) { + regs.x.ax = 33; + int86(0x33, ®s, ®s); + _PM_mouseHandler = NULL; + } +} + +void PMAPI PM_setTimerHandler(PM_intHandler th) +{ + _PM_getRMvect(0x8, (long*)&_PM_prevTimer); + _PM_timerHandler = th; + _PM_setRMvect(0x8, (long)_PM_timerISR); +} + +void PMAPI PM_restoreTimerHandler(void) +{ + if (_PM_timerHandler) { + _PM_setRMvect(0x8, (long)_PM_prevTimer); + _PM_timerHandler = NULL; + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + _PM_getRMvect(0x70, (long*)&_PM_prevRTC); + _PM_rtcHandler = th; + _PM_setRMvect(0x70, (long)_PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); + + /* Restore the interrupt vector */ + _PM_setRMvect(0x70, (long)_PM_prevRTC); + _PM_rtcHandler = NULL; + } +} + +void PMAPI PM_setKeyHandler(PM_intHandler kh) +{ + _PM_getRMvect(0x9, (long*)&_PM_prevKey); + _PM_keyHandler = kh; + _PM_setRMvect(0x9, (long)_PM_keyISR); +} + +void PMAPI PM_restoreKeyHandler(void) +{ + if (_PM_keyHandler) { + _PM_setRMvect(0x9, (long)_PM_prevKey); + _PM_keyHandler = NULL; + } +} + +void PMAPI PM_setKey15Handler(PM_key15Handler kh) +{ + _PM_getRMvect(0x15, (long*)&_PM_prevKey15); + _PM_key15Handler = kh; + _PM_setRMvect(0x15, (long)_PM_key15ISR); +} + +void PMAPI PM_restoreKey15Handler(void) +{ + if (_PM_key15Handler) { + _PM_setRMvect(0x15, (long)_PM_prevKey15); + _PM_key15Handler = NULL; + } +} + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) +{ + static int ctrlCFlag,ctrlBFlag; + + _PM_ctrlCPtr = (uchar*)&ctrlCFlag; + _PM_ctrlBPtr = (uchar*)&ctrlBFlag; + _PM_getRMvect(0x1B, (long*)&_PM_prevBreak); + _PM_getRMvect(0x23, (long*)&_PM_prevCtrlC); + _PM_breakHandler = bh; + _PM_setRMvect(0x1B, (long)_PM_breakISR); + _PM_setRMvect(0x23, (long)_PM_ctrlCISR); +} + +void PMAPI PM_installBreakHandler(void) +{ + PM_installAltBreakHandler(NULL); +} + +void PMAPI PM_restoreBreakHandler(void) +{ + if (_PM_prevBreak) { + _PM_setRMvect(0x1B, (long)_PM_prevBreak); + _PM_setRMvect(0x23, (long)_PM_prevCtrlC); + _PM_prevBreak = NULL; + _PM_breakHandler = NULL; + } +} + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) +{ + static short critBuf[2]; + + _PM_critPtr = (uchar*)critBuf; + _PM_getRMvect(0x24, (long*)&_PM_prevCritical); + _PM_critHandler = ch; + _PM_setRMvect(0x24, (long)_PM_criticalISR); +} + +void PMAPI PM_installCriticalHandler(void) +{ + PM_installAltCriticalHandler(NULL); +} + +void PMAPI PM_restoreCriticalHandler(void) +{ + if (_PM_prevCritical) { + _PM_setRMvect(0x24, (long)_PM_prevCritical); + _PM_prevCritical = NULL; + _PM_critHandler = NULL; + } +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; /* Do nothing for real mode */ + return 1; +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; /* Do nothing for real mode */ + return 1; +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; /* Do nothing for real mode */ + return 1; +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; /* Do nothing for real mode */ + return 1; +} + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + long t; + _PM_getRMvect(intno,&t); + *isr = (void*)t; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PM_saveDS(); + _PM_setRMvect(intno,(long)isr); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + _PM_setRMvect(intno,(long)isr); +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Phar Lap TNT DOS Extender support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef TNT + +#include +#include +#include + +static long prevRealBreak; /* Previous real mode break handler */ +static long prevRealCtrlC; /* Previous real mode CtrlC handler */ +static long prevRealCritical; /* Prev real mode critical handler */ +static uchar *mousePtr; + +/* The following real mode routine is used to call a 32 bit protected + * mode FAR function from real mode. We use this for passing up control + * from the real mode mouse callback to our protected mode code. + */ + +static UCHAR realHandler[] = { /* Real mode code generic handler */ + 0x00,0x00,0x00,0x00, /* __PM_callProtp */ + 0x00,0x00, /* __PM_protCS */ + 0x00,0x00,0x00,0x00, /* __PM_protHandler */ + 0x66,0x60, /* pushad */ + 0x1E, /* push ds */ + 0x6A,0x00, /* push 0 */ + 0x6A,0x00, /* push 0 */ + 0x2E,0xFF,0x36,0x04,0x00, /* push [cs:__PM_protCS] */ + 0x66,0x2E,0xFF,0x36,0x06,0x00, /* push [cs:__PM_protHandler] */ + 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PM_callProtp] */ + 0x83,0xC4,0x0A, /* add sp,10 */ + 0x1F, /* pop ds */ + 0x66,0x61, /* popad */ + 0xCB, /* retf */ + }; + +/* The following functions installs the above realmode callback mechanism + * in real mode memory for calling the protected mode routine. + */ + +uchar * installCallback(void (PMAPI *pmCB)(),uint *rseg, uint *roff) +{ + CONFIG_INF config; + REALPTR realBufAdr,callProtp; + ULONG bufSize; + FARPTR protBufAdr; + uchar *p; + + /* Get address of real mode routine to call up to protected mode */ + _dx_rmlink_get(&callProtp, &realBufAdr, &bufSize, &protBufAdr); + _dx_config_inf(&config, (UCHAR*)&config); + + /* Fill in the values in the real mode code segment so that it will + * call the correct routine. + */ + *((REALPTR*)&realHandler[0]) = callProtp; + *((USHORT*)&realHandler[4]) = config.c_cs_sel; + *((ULONG*)&realHandler[6]) = (ULONG)pmCB; + + /* Copy the real mode handler to real mode memory */ + if ((p = PM_allocRealSeg(sizeof(realHandler),rseg,roff)) == NULL) + return NULL; + memcpy(p,realHandler,sizeof(realHandler)); + + /* Skip past global variabls in real mode code segment */ + *roff += 0x0A; + return p; +} + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + RMREGS regs; + RMSREGS sregs; + uint rseg,roff; + + lockPMHandlers(); /* Ensure our handlers are locked */ + + if ((mousePtr = installCallback(_PM_mouseISR, &rseg, &roff)) == NULL) + return 0; + _PM_mouseHandler = mh; + + /* Install the real mode mouse handler */ + sregs.es = rseg; + regs.x.dx = roff; + regs.x.cx = _PM_mouseMask = mask; + regs.x.ax = 0xC; + PM_int86x(0x33, ®s, ®s, &sregs); + return 1; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + RMREGS regs; + + if (_PM_mouseHandler) { + regs.x.ax = 33; + PM_int86(0x33, ®s, ®s); + PM_freeRealSeg(mousePtr); + _PM_mouseHandler = NULL; + } +} + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + FARPTR ph; + + _dx_pmiv_get(intno, &ph); + isr->sel = FP_SEL(ph); + isr->off = FP_OFF(ph); +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + CONFIG_INF config; + FARPTR ph; + + PM_saveDS(); + _dx_config_inf(&config, (UCHAR*)&config); + FP_SET(ph,(uint)isr,config.c_cs_sel); + _dx_pmiv_set(intno,ph); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + FARPTR ph; + + FP_SET(ph,isr.off,isr.sel); + _dx_pmiv_set(intno,ph); +} + +static void getISR(int intno, PMFARPTR *pmisr, long *realisr) +{ + PM_getPMvect(intno,pmisr); + _PM_getRMvect(intno, realisr); +} + +static void restoreISR(int intno, PMFARPTR pmisr, long realisr) +{ + _PM_setRMvect(intno,realisr); + PM_restorePMvect(intno,pmisr); +} + +static void setISR(int intno, void (PMAPI *isr)()) +{ + CONFIG_INF config; + FARPTR ph; + + lockPMHandlers(); /* Ensure our handlers are locked */ + + _dx_config_inf(&config, (UCHAR*)&config); + FP_SET(ph,(uint)isr,config.c_cs_sel); + _dx_apmiv_set(intno,ph); +} + +void PMAPI PM_setTimerHandler(PM_intHandler th) +{ + getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer); + _PM_timerHandler = th; + setISR(0x8, _PM_timerISR); +} + +void PMAPI PM_restoreTimerHandler(void) +{ + if (_PM_timerHandler) { + restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer); + _PM_timerHandler = NULL; + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); + _PM_rtcHandler = th; + setISR(0x70, _PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); + + /* Restore the interrupt vector */ + restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); + _PM_rtcHandler = NULL; + } +} + +void PMAPI PM_setKeyHandler(PM_intHandler kh) +{ + getISR(0x9, &_PM_prevKey, &_PM_prevRealKey); + _PM_keyHandler = kh; + setISR(0x9, _PM_keyISR); +} + +void PMAPI PM_restoreKeyHandler(void) +{ + if (_PM_keyHandler) { + restoreISR(0x9, _PM_prevKey, _PM_prevRealKey); + _PM_keyHandler = NULL; + } +} + +void PMAPI PM_setKey15Handler(PM_key15Handler kh) +{ + getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); + _PM_key15Handler = kh; + setISR(0x15, _PM_key15ISR); +} + +void PMAPI PM_restoreKey15Handler(void) +{ + if (_PM_key15Handler) { + restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); + _PM_key15Handler = NULL; + } +} + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) +{ + static int ctrlCFlag,ctrlBFlag; + + _PM_ctrlCPtr = (uchar*)&ctrlCFlag; + _PM_ctrlBPtr = (uchar*)&ctrlBFlag; + getISR(0x1B, &_PM_prevBreak, &prevRealBreak); + getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); + _PM_breakHandler = bh; + setISR(0x1B, _PM_breakISR); + setISR(0x23, _PM_ctrlCISR); +} + +void PMAPI PM_installBreakHandler(void) +{ + PM_installAltBreakHandler(NULL); +} + +void PMAPI PM_restoreBreakHandler(void) +{ + if (_PM_prevBreak.sel) { + restoreISR(0x1B, _PM_prevBreak, prevRealBreak); + restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); + _PM_prevBreak.sel = 0; + _PM_breakHandler = NULL; + } +} + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) +{ + static short critBuf[2]; + + _PM_critPtr = (uchar*)critBuf; + getISR(0x24, &_PM_prevCritical, &prevRealCritical); + _PM_critHandler = ch; + setISR(0x24, _PM_criticalISR); +} + +void PMAPI PM_installCriticalHandler(void) +{ + PM_installAltCriticalHandler(NULL); +} + +void PMAPI PM_restoreCriticalHandler(void) +{ + if (_PM_prevCritical.sel) { + restoreISR(0x24, _PM_prevCritical, prevRealCritical); + _PM_prevCritical.sel = 0; + _PM_critHandler = NULL; + } +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + return (_dx_lock_pgsn(p,len) == 0); +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + return (_dx_ulock_pgsn(p,len) == 0); +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + CONFIG_INF config; + FARPTR fp; + + _dx_config_inf(&config, (UCHAR*)&config); + FP_SET(fp,p,config.c_cs_sel); + return (_dx_lock_pgs(fp,len) == 0); +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + CONFIG_INF config; + FARPTR fp; + + _dx_config_inf(&config, (UCHAR*)&config); + FP_SET(fp,p,config.c_cs_sel); + return (_dx_ulock_pgs(fp,len) == 0); +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Symantec C++ DOSX and FlashTek X-32/X-32VM support */ +/*-------------------------------------------------------------------------*/ + +#if defined(DOSX) || defined(X32VM) + +#ifdef X32VM +#include +#endif + +static long prevRealBreak; /* Previous real mode break handler */ +static long prevRealCtrlC; /* Previous real mode CtrlC handler */ +static long prevRealCritical; /* Prev real mode critical handler */ + +static uint mouseSel = 0,mouseOff; + +/* The following real mode routine is used to call a 32 bit protected + * mode FAR function from real mode. We use this for passing up control + * from the real mode mouse callback to our protected mode code. + */ + +static char realHandler[] = { /* Real mode code generic handler */ + 0x00,0x00,0x00,0x00, /* __PM_callProtp */ + 0x00,0x00, /* __PM_protCS */ + 0x00,0x00,0x00,0x00, /* __PM_protHandler */ + 0x1E, /* push ds */ + 0x6A,0x00, /* push 0 */ + 0x6A,0x00, /* push 0 */ + 0x2E,0xFF,0x36,0x04,0x00, /* push [cs:__PM_protCS] */ + 0x66,0x2E,0xFF,0x36,0x06,0x00, /* push [cs:__PM_protHandler] */ + 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PM_callProtp] */ + 0x83,0xC4,0x0A, /* add sp,10 */ + 0x1F, /* pop ds */ + 0xCB, /* retf */ + }; + +/* The following functions installs the above realmode callback mechanism + * in real mode memory for calling the protected mode routine. + */ + +int installCallback(void (PMAPI *pmCB)(),uint *psel, uint *poff, + uint *rseg, uint *roff) +{ + PMREGS regs; + PMSREGS sregs; + + regs.x.ax = 0x250D; + PM_segread(&sregs); + PM_int386x(0x21,®s,®s,&sregs); /* Get RM callback address */ + + /* Fill in the values in the real mode code segment so that it will + * call the correct routine. + */ + *((ulong*)&realHandler[0]) = regs.e.eax; + *((ushort*)&realHandler[4]) = sregs.cs; + *((ulong*)&realHandler[6]) = (ulong)pmCB; + + /* Copy the real mode handler to real mode memory (only allocate the + * buffer once since we cant dealloate it with X32). + */ + if (*psel == 0) { + if (!PM_allocRealSeg(sizeof(realHandler),psel,poff,rseg,roff)) + return 0; + } + PM_memcpyfn(*psel,*poff,realHandler,sizeof(realHandler)); + + /* Skip past global variables in real mode code segment */ + *roff += 0x0A; + return 1; +} + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + RMREGS regs; + RMSREGS sregs; + uint rseg,roff; + + lockPMHandlers(); /* Ensure our handlers are locked */ + + if (!installCallback(_PM_mouseISR, &mouseSel, &mouseOff, &rseg, &roff)) + return 0; + _PM_mouseHandler = mh; + + /* Install the real mode mouse handler */ + sregs.es = rseg; + regs.x.dx = roff; + regs.x.cx = _PM_mouseMask = mask; + regs.x.ax = 0xC; + PM_int86x(0x33, ®s, ®s, &sregs); + return 1; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + RMREGS regs; + + if (_PM_mouseHandler) { + regs.x.ax = 33; + PM_int86(0x33, ®s, ®s); + _PM_mouseHandler = NULL; + } +} + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_segread(&sregs); + regs.x.ax = 0x2502; /* Get PM interrupt vector */ + regs.x.cx = intno; + PM_int386x(0x21, ®s, ®s, &sregs); + isr->sel = sregs.es; + isr->off = regs.e.ebx; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PMFARPTR pmisr; + PMSREGS sregs; + + PM_saveDS(); + PM_segread(&sregs); + pmisr.sel = sregs.cs; + pmisr.off = (uint)isr; + PM_restorePMvect(intno, pmisr); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_segread(&sregs); + regs.x.ax = 0x2505; /* Set PM interrupt vector */ + regs.x.cx = intno; + sregs.ds = isr.sel; + regs.e.edx = isr.off; + PM_int386x(0x21, ®s, ®s, &sregs); +} + +static void getISR(int intno, PMFARPTR *pmisr, long *realisr) +{ + PM_getPMvect(intno,pmisr); + _PM_getRMvect(intno,realisr); +} + +static void restoreISR(int intno, PMFARPTR pmisr, long realisr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_segread(&sregs); + regs.x.ax = 0x2507; /* Set real and PM vectors */ + regs.x.cx = intno; + sregs.ds = pmisr.sel; + regs.e.edx = pmisr.off; + regs.e.ebx = realisr; + PM_int386x(0x21, ®s, ®s, &sregs); +} + +static void setISR(int intno, void *isr) +{ + PMREGS regs; + PMSREGS sregs; + + lockPMHandlers(); /* Ensure our handlers are locked */ + + PM_segread(&sregs); + regs.x.ax = 0x2506; /* Hook real and protected vectors */ + regs.x.cx = intno; + sregs.ds = sregs.cs; + regs.e.edx = (uint)isr; + PM_int386x(0x21, ®s, ®s, &sregs); +} + +void PMAPI PM_setTimerHandler(PM_intHandler th) +{ + getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer); + _PM_timerHandler = th; + setISR(0x8, _PM_timerISR); +} + +void PMAPI PM_restoreTimerHandler(void) +{ + if (_PM_timerHandler) { + restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer); + _PM_timerHandler = NULL; + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); + _PM_rtcHandler = th; + setISR(0x70, _PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); + + /* Restore the interrupt vector */ + restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); + _PM_rtcHandler = NULL; + } +} + +void PMAPI PM_setKeyHandler(PM_intHandler kh) +{ + getISR(0x9, &_PM_prevKey, &_PM_prevRealKey); + _PM_keyHandler = kh; + setISR(0x9, _PM_keyISR); +} + +void PMAPI PM_restoreKeyHandler(void) +{ + if (_PM_keyHandler) { + restoreISR(0x9, _PM_prevKey, _PM_prevRealKey); + _PM_keyHandler = NULL; + } +} + +void PMAPI PM_setKey15Handler(PM_key15Handler kh) +{ + getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); + _PM_key15Handler = kh; + setISR(0x15, _PM_key15ISR); +} + +void PMAPI PM_restoreKey15Handler(void) +{ + if (_PM_key15Handler) { + restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); + _PM_key15Handler = NULL; + } +} + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) +{ + static int ctrlCFlag,ctrlBFlag; + + _PM_ctrlCPtr = (uchar*)&ctrlCFlag; + _PM_ctrlBPtr = (uchar*)&ctrlBFlag; + getISR(0x1B, &_PM_prevBreak, &prevRealBreak); + getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); + _PM_breakHandler = bh; + setISR(0x1B, _PM_breakISR); + setISR(0x23, _PM_ctrlCISR); +} + +void PMAPI PM_installBreakHandler(void) +{ + PM_installAltBreakHandler(NULL); +} + +void PMAPI PM_restoreBreakHandler(void) +{ + if (_PM_prevBreak.sel) { + restoreISR(0x1B, _PM_prevBreak, prevRealBreak); + restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); + _PM_prevBreak.sel = 0; + _PM_breakHandler = NULL; + } +} + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) +{ + static short critBuf[2]; + + _PM_critPtr = (uchar*)critBuf; + getISR(0x24, &_PM_prevCritical, &prevRealCritical); + _PM_critHandler = ch; + setISR(0x24, _PM_criticalISR); +} + +void PMAPI PM_installCriticalHandler(void) +{ + PM_installAltCriticalHandler(NULL); +} + +void PMAPI PM_restoreCriticalHandler(void) +{ + if (_PM_prevCritical.sel) { + restoreISR(0x24, _PM_prevCritical, prevRealCritical); + _PM_prevCritical.sel = 0; + _PM_critHandler = NULL; + } +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + return (_x386_memlock(p,len) == 0); +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + return (_x386_memunlock(p,len) == 0); +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + return (_x386_memlock(p,len) == 0); +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + return (_x386_memunlock(p,len) == 0); +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Borland's DPMI32 DOS Power Pack Extender support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef DPMI32 +#define GENERIC_DPMI32 /* Use generic 32 bit DPMI routines */ + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + PMREGS regs; + + regs.x.ax = 0x204; + regs.h.bl = intno; + PM_int386(0x31,®s,®s); + isr->sel = regs.x.cx; + isr->off = regs.e.edx; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PMSREGS sregs; + PMREGS regs; + + PM_saveDS(); + regs.x.ax = 0x205; /* Set protected mode vector */ + regs.h.bl = intno; + PM_segread(&sregs); + regs.x.cx = sregs.cs; + regs.e.edx = (uint)isr; + PM_int386(0x31,®s,®s); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + PMREGS regs; + + regs.x.ax = 0x205; + regs.h.bl = intno; + regs.x.cx = isr.sel; + regs.e.edx = isr.off; + PM_int386(0x31,®s,®s); +} +#endif + +/*-------------------------------------------------------------------------*/ +/* Watcom C/C++ with Rational DOS/4GW support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef DOS4GW +#define GENERIC_DPMI32 /* Use generic 32 bit DPMI routines */ + +#define MOUSE_SUPPORTED /* DOS4GW directly supports mouse */ + +/* We use the normal DOS services to save and restore interrupts handlers + * for Watcom C++, because using the direct DPMI functions does not + * appear to work properly. At least if we use the DPMI functions, we + * dont get the auto-passup feature that we need to correctly trap + * real and protected mode interrupts without installing Bi-model + * interrupt handlers. + */ + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_segread(&sregs); + regs.h.ah = 0x35; + regs.h.al = intno; + PM_int386x(0x21,®s,®s,&sregs); + isr->sel = sregs.es; + isr->off = regs.e.ebx; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_saveDS(); + PM_segread(&sregs); + regs.h.ah = 0x25; + regs.h.al = intno; + sregs.ds = sregs.cs; + regs.e.edx = (uint)isr; + PM_int386x(0x21,®s,®s,&sregs); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + PMREGS regs; + PMSREGS sregs; + + PM_segread(&sregs); + regs.h.ah = 0x25; + regs.h.al = intno; + sregs.ds = isr.sel; + regs.e.edx = isr.off; + PM_int386x(0x21,®s,®s,&sregs); +} + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + lockPMHandlers(); /* Ensure our handlers are locked */ + + _PM_mouseHandler = mh; + _PM_setMouseHandler(_PM_mouseMask = mask); + return 1; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + PMREGS regs; + + if (_PM_mouseHandler) { + regs.x.ax = 33; + PM_int386(0x33, ®s, ®s); + _PM_mouseHandler = NULL; + } +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* DJGPP port of GNU C++ support. */ +/*-------------------------------------------------------------------------*/ + +#ifdef DJGPP +#define GENERIC_DPMI32 /* Use generic 32 bit DPMI routines */ + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + PMREGS regs; + + regs.x.ax = 0x204; + regs.h.bl = intno; + PM_int386(0x31,®s,®s); + isr->sel = regs.x.cx; + isr->off = regs.e.edx; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PMSREGS sregs; + PMREGS regs; + + PM_saveDS(); + regs.x.ax = 0x205; /* Set protected mode vector */ + regs.h.bl = intno; + PM_segread(&sregs); + regs.x.cx = sregs.cs; + regs.e.edx = (uint)isr; + PM_int386(0x31,®s,®s); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + PMREGS regs; + + regs.x.ax = 0x205; + regs.h.bl = intno; + regs.x.cx = isr.sel; + regs.e.edx = isr.off; + PM_int386(0x31,®s,®s); +} + +#endif + +/*-------------------------------------------------------------------------*/ +/* Generic 32 bit DPMI routines */ +/*-------------------------------------------------------------------------*/ + +#if defined(GENERIC_DPMI32) + +static long prevRealBreak; /* Previous real mode break handler */ +static long prevRealCtrlC; /* Previous real mode CtrlC handler */ +static long prevRealCritical; /* Prev real mode critical handler */ + +#ifndef MOUSE_SUPPORTED + +/* The following real mode routine is used to call a 32 bit protected + * mode FAR function from real mode. We use this for passing up control + * from the real mode mouse callback to our protected mode code. + */ + +static long mouseRMCB; /* Mouse real mode callback address */ +static uchar *mousePtr; +static char mouseRegs[0x32]; /* Real mode regs for mouse callback */ +static uchar mouseHandler[] = { + 0x00,0x00,0x00,0x00, /* _realRMCB */ + 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:_realRMCB] */ + 0xCB, /* retf */ + }; + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + RMREGS regs; + RMSREGS sregs; + uint rseg,roff; + + lockPMHandlers(); /* Ensure our handlers are locked */ + + /* Copy the real mode handler to real mode memory */ + if ((mousePtr = PM_allocRealSeg(sizeof(mouseHandler),&rseg,&roff)) == NULL) + return 0; + memcpy(mousePtr,mouseHandler,sizeof(mouseHandler)); + if (!_DPMI_allocateCallback(_PM_mousePMCB, mouseRegs, &mouseRMCB)) + PM_fatalError("Unable to allocate real mode callback!\n"); + PM_setLong(mousePtr,mouseRMCB); + + /* Install the real mode mouse handler */ + _PM_mouseHandler = mh; + sregs.es = rseg; + regs.x.dx = roff+4; + regs.x.cx = _PM_mouseMask = mask; + regs.x.ax = 0xC; + PM_int86x(0x33, ®s, ®s, &sregs); + return 1; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + RMREGS regs; + + if (_PM_mouseHandler) { + regs.x.ax = 33; + PM_int86(0x33, ®s, ®s); + PM_freeRealSeg(mousePtr); + _DPMI_freeCallback(mouseRMCB); + _PM_mouseHandler = NULL; + } +} + +#endif + +static void getISR(int intno, PMFARPTR *pmisr, long *realisr) +{ + PM_getPMvect(intno,pmisr); + _PM_getRMvect(intno,realisr); +} + +static void restoreISR(int intno, PMFARPTR pmisr, long realisr) +{ + _PM_setRMvect(intno,realisr); + PM_restorePMvect(intno,pmisr); +} + +static void setISR(int intno, void (* PMAPI pmisr)()) +{ + lockPMHandlers(); /* Ensure our handlers are locked */ + PM_setPMvect(intno,pmisr); +} + +void PMAPI PM_setTimerHandler(PM_intHandler th) +{ + getISR(0x8, &_PM_prevTimer, &_PM_prevRealTimer); + _PM_timerHandler = th; + setISR(0x8, _PM_timerISR); +} + +void PMAPI PM_restoreTimerHandler(void) +{ + if (_PM_timerHandler) { + restoreISR(0x8, _PM_prevTimer, _PM_prevRealTimer); + _PM_timerHandler = NULL; + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); + _PM_rtcHandler = th; + setISR(0x70, _PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); + + /* Restore the interrupt vector */ + restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); + _PM_rtcHandler = NULL; + } +} + +PM_IRQHandle PMAPI PM_setIRQHandler( + int IRQ, + PM_irqHandler ih) +{ + int thunkSize,PICmask,chainPrevious; + ulong offsetAdjust; + _PM_IRQHandle *handle; + + thunkSize = (ulong)_PM_irqISRTemplateEnd - (ulong)_PM_irqISRTemplate; + if ((handle = PM_malloc(sizeof(_PM_IRQHandle) + thunkSize)) == NULL) + return NULL; + handle->IRQ = IRQ; + handle->prevPIC = PM_inpb(0x21); + handle->prevPIC2 = PM_inpb(0xA1); + if (IRQ < 8) { + handle->IRQVect = (IRQ + 8); + PICmask = (1 << IRQ); + chainPrevious = ((handle->prevPIC & PICmask) == 0); + } + else { + handle->IRQVect = (0x60 + IRQ + 8); + PICmask = ((1 << IRQ) | 0x4); + chainPrevious = ((handle->prevPIC2 & (PICmask >> 8)) == 0); + } + + /* Copy and setup the assembler thunk */ + offsetAdjust = (ulong)handle->thunk - (ulong)_PM_irqISRTemplate; + memcpy(handle->thunk,_PM_irqISRTemplate,thunkSize); + *((ulong*)&handle->thunk[2]) = offsetAdjust; + *((ulong*)&handle->thunk[11+0]) = (ulong)ih; + if (chainPrevious) { + *((ulong*)&handle->thunk[11+4]) = handle->prevHandler.off; + *((ulong*)&handle->thunk[11+8]) = handle->prevHandler.sel; + } + else { + *((ulong*)&handle->thunk[11+4]) = 0; + *((ulong*)&handle->thunk[11+8]) = 0; + } + *((ulong*)&handle->thunk[11+12]) = IRQ; + + /* Set the real time clock interrupt handler */ + getISR(handle->IRQVect, &handle->prevHandler, &handle->prevRealhandler); + setISR(handle->IRQVect, (PM_intHandler)handle->thunk); + + /* Unmask the IRQ in the PIC */ + PM_outpb(0xA1,handle->prevPIC2 & ~(PICmask >> 8)); + PM_outpb(0x21,handle->prevPIC & ~PICmask); + return handle; +} + +void PMAPI PM_restoreIRQHandler( + PM_IRQHandle irqHandle) +{ + int PICmask; + _PM_IRQHandle *handle = irqHandle; + + /* Restore PIC mask for the interrupt */ + if (handle->IRQ < 8) + PICmask = (1 << handle->IRQ); + else + PICmask = ((1 << handle->IRQ) | 0x4); + PM_outpb(0xA1,(PM_inpb(0xA1) & ~(PICmask >> 8)) | (handle->prevPIC2 & (PICmask >> 8))); + PM_outpb(0x21,(PM_inpb(0x21) & ~PICmask) | (handle->prevPIC & PICmask)); + + /* Restore the interrupt vector */ + restoreISR(handle->IRQVect, handle->prevHandler, handle->prevRealhandler); + + /* Finally free the thunk */ + PM_free(handle); +} + +void PMAPI PM_setKeyHandler(PM_intHandler kh) +{ + getISR(0x9, &_PM_prevKey, &_PM_prevRealKey); + _PM_keyHandler = kh; + setISR(0x9, _PM_keyISR); +} + +void PMAPI PM_restoreKeyHandler(void) +{ + if (_PM_keyHandler) { + restoreISR(0x9, _PM_prevKey, _PM_prevRealKey); + _PM_keyHandler = NULL; + } +} + +void PMAPI PM_setKey15Handler(PM_key15Handler kh) +{ + getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); + _PM_key15Handler = kh; + setISR(0x15, _PM_key15ISR); +} + +void PMAPI PM_restoreKey15Handler(void) +{ + if (_PM_key15Handler) { + restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); + _PM_key15Handler = NULL; + } +} + +/* Real mode Ctrl-C and Ctrl-Break handler. This handler simply sets a + * flag in the real mode code segment and exit. We save the location + * of this flag in real mode memory so that both the real mode and + * protected mode code will be modifying the same flags. + */ + +#ifndef DOS4GW +static uchar ctrlHandler[] = { + 0x00,0x00,0x00,0x00, /* ctrlBFlag */ + 0x66,0x2E,0xC7,0x06,0x00,0x00, + 0x01,0x00,0x00,0x00, /* mov [cs:ctrlBFlag],1 */ + 0xCF, /* iretf */ + }; +#endif + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) +{ +#ifndef DOS4GW + uint rseg,roff; +#else + static int ctrlCFlag,ctrlBFlag; + + _PM_ctrlCPtr = (uchar*)&ctrlCFlag; + _PM_ctrlBPtr = (uchar*)&ctrlBFlag; +#endif + + getISR(0x1B, &_PM_prevBreak, &prevRealBreak); + getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); + _PM_breakHandler = bh; + setISR(0x1B, _PM_breakISR); + setISR(0x23, _PM_ctrlCISR); + +#ifndef DOS4GW + /* Hook the real mode vectors for these handlers, as these are not + * normally reflected by the DPMI server up to protected mode + */ + _PM_ctrlBPtr = PM_allocRealSeg(sizeof(ctrlHandler)*2, &rseg, &roff); + memcpy(_PM_ctrlBPtr,ctrlHandler,sizeof(ctrlHandler)); + memcpy(_PM_ctrlBPtr+sizeof(ctrlHandler),ctrlHandler,sizeof(ctrlHandler)); + _PM_ctrlCPtr = _PM_ctrlBPtr + sizeof(ctrlHandler); + _PM_setRMvect(0x1B,((long)rseg << 16) | (roff+4)); + _PM_setRMvect(0x23,((long)rseg << 16) | (roff+sizeof(ctrlHandler)+4)); +#endif +} + +void PMAPI PM_installBreakHandler(void) +{ + PM_installAltBreakHandler(NULL); +} + +void PMAPI PM_restoreBreakHandler(void) +{ + if (_PM_prevBreak.sel) { + restoreISR(0x1B, _PM_prevBreak, prevRealBreak); + restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); + _PM_prevBreak.sel = 0; + _PM_breakHandler = NULL; +#ifndef DOS4GW + PM_freeRealSeg(_PM_ctrlBPtr); +#endif + } +} + +/* Real mode Critical Error handler. This handler simply saves the AX and + * DI values in the real mode code segment and exits. We save the location + * of this flag in real mode memory so that both the real mode and + * protected mode code will be modifying the same flags. + */ + +#ifndef DOS4GW +static uchar criticalHandler[] = { + 0x00,0x00, /* axCode */ + 0x00,0x00, /* diCode */ + 0x2E,0xA3,0x00,0x00, /* mov [cs:axCode],ax */ + 0x2E,0x89,0x3E,0x02,0x00, /* mov [cs:diCode],di */ + 0xB8,0x03,0x00, /* mov ax,3 */ + 0xCF, /* iretf */ + }; +#endif + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) +{ +#ifndef DOS4GW + uint rseg,roff; +#else + static short critBuf[2]; + + _PM_critPtr = (uchar*)critBuf; +#endif + + getISR(0x24, &_PM_prevCritical, &prevRealCritical); + _PM_critHandler = ch; + setISR(0x24, _PM_criticalISR); + +#ifndef DOS4GW + /* Hook the real mode vector, as this is not normally reflected by the + * DPMI server up to protected mode. + */ + _PM_critPtr = PM_allocRealSeg(sizeof(criticalHandler)*2, &rseg, &roff); + memcpy(_PM_critPtr,criticalHandler,sizeof(criticalHandler)); + _PM_setRMvect(0x24,((long)rseg << 16) | (roff+4)); +#endif +} + +void PMAPI PM_installCriticalHandler(void) +{ + PM_installAltCriticalHandler(NULL); +} + +void PMAPI PM_restoreCriticalHandler(void) +{ + if (_PM_prevCritical.sel) { + restoreISR(0x24, _PM_prevCritical, prevRealCritical); + PM_freeRealSeg(_PM_critPtr); + _PM_prevCritical.sel = 0; + _PM_critHandler = NULL; + } +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.cs),len); +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.cs),len); +} + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c new file mode 100644 index 000000000..c3e9b6c33 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/vflat.c @@ -0,0 +1,251 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit DOS +* +* Description: Main C module for the VFlat framebuffer routines. The page +* fault handler is always installed to handle up to a 4Mb +* framebuffer with a window size of 4Kb or 64Kb in size. +* +****************************************************************************/ + +#include "pmapi.h" +#include +#include + +/*-------------------------------------------------------------------------*/ +/* DOS4G/W, PMODE/W and CauseWay support. */ +/*-------------------------------------------------------------------------*/ + +#if defined(DOS4GW) + +#define VFLAT_START_ADDR 0xF0000000U +#define VFLAT_END_ADDR 0xF03FFFFFU +#define VFLAT_LIMIT (VFLAT_END_ADDR - VFLAT_START_ADDR) +#define PAGE_PRESENT 1 +#define PAGE_NOTPRESENT 0 +#define PAGE_READ 0 +#define PAGE_WRITE 2 + +PRIVATE ibool installed = false; +PRIVATE ibool haveDPMI = false; +PUBLIC ibool _ASMAPI VF_haveCauseWay = false; +PUBLIC uchar * _ASMAPI VF_zeroPtr = NULL; + +/* Low level assembler code */ + +int _ASMAPI InitPaging(void); +void _ASMAPI ClosePaging(void); +void _ASMAPI MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags); +void _ASMAPI InstallFaultHandler(ulong baseAddr,int bankSize); +void _ASMAPI RemoveFaultHandler(void); +void _ASMAPI InstallBankFunc(int codeLen,void *bankFunc); + +void * _ASMAPI VF_malloc(uint size) +{ return PM_malloc(size); } + +void _ASMAPI VF_free(void *p) +{ PM_free(p); } + +PRIVATE ibool CheckDPMI(void) +/**************************************************************************** +* +* Function: CheckDPMI +* Returns: True if we are running under DPMI +* +****************************************************************************/ +{ + PMREGS regs; + + if (haveDPMI) + return true; + + /* Check if we are running under DPMI in which case we will not be + * able to install our page fault handlers. We can however use the + * DVA.386 or VFLATD.386 virtual device drivers if they are present. + */ + regs.x.ax = 0xFF00; + PM_int386(0x31,®s,®s); + if (!regs.x.cflag && (regs.e.edi & 8)) + return (haveDPMI = true); + return false; +} + +ibool PMAPI VF_available(void) +/**************************************************************************** +* +* Function: VF_available +* Returns: True if virtual buffer is available, false if not. +* +****************************************************************************/ +{ + if (!VF_zeroPtr) + VF_zeroPtr = PM_mapPhysicalAddr(0,0xFFFFFFFF,true); + if (CheckDPMI()) + return false; + + /* Standard DOS4GW, PMODE/W and Causeway */ + if (InitPaging() == -1) + return false; + ClosePaging(); + return true; +} + +void * PMAPI InitDPMI(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +/**************************************************************************** +* +* Function: InitDOS4GW +* Parameters: baseAddr - Base address of framebuffer bank window +* bankSize - Physical size of banks in Kb (4 or 64) +* codeLen - Length of 32 bit bank switch function +* bankFunc - Pointer to protected mode bank function +* Returns: Near pointer to virtual framebuffer, or NULL on failure. +* +* Description: Installs the virtual linear framebuffer handling for +* DPMI environments. This requires the DVA.386 or VFLATD.386 +* virtual device drivers to be installed and functioning. +* +****************************************************************************/ +{ + (void)baseAddr; + (void)bankSize; + (void)codeLen; + (void)bankFunc; + return NULL; +} + +void * PMAPI InitDOS4GW(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +/**************************************************************************** +* +* Function: InitDOS4GW +* Parameters: baseAddr - Base address of framebuffer bank window +* bankSize - Physical size of banks in Kb (4 or 64) +* codeLen - Length of 32 bit bank switch function +* bankFunc - Pointer to protected mode bank function +* Returns: Near pointer to virtual framebuffer, or NULL on failure. +* +* Description: Installs the virtual linear framebuffer handling for +* the DOS4GW extender. +* +****************************************************************************/ +{ + int i; + + if (InitPaging() == -1) + return NULL; /* Cannot do hardware paging! */ + + /* Map 4MB of video memory into linear address space (read/write) */ + if (bankSize == 64) { + for (i = 0; i < 64; i++) { + MapPhysical2Linear(baseAddr,VFLAT_START_ADDR+(i<<16),16, + PAGE_WRITE | PAGE_NOTPRESENT); + } + } + else { + for (i = 0; i < 1024; i++) { + MapPhysical2Linear(baseAddr,VFLAT_START_ADDR+(i<<12),1, + PAGE_WRITE | PAGE_NOTPRESENT); + } + } + + /* Install our page fault handler and banks switch function */ + InstallFaultHandler(baseAddr,bankSize); + InstallBankFunc(codeLen,bankFunc); + installed = true; + return (void*)VFLAT_START_ADDR; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +/**************************************************************************** +* +* Function: VF_init +* Parameters: baseAddr - Base address of framebuffer bank window +* bankSize - Physical size of banks in Kb (4 or 64) +* codeLen - Length of 32 bit bank switch function +* bankFunc - Pointer to protected mode bank function +* Returns: Near pointer to virtual framebuffer, or NULL on failure. +* +* Description: Installs the virtual linear framebuffer handling. +* +****************************************************************************/ +{ + if (installed) + return (void*)VFLAT_START_ADDR; + if (codeLen > 100) + return NULL; /* Bank function is too large! */ + if (!VF_zeroPtr) + VF_zeroPtr = PM_mapPhysicalAddr(0,0xFFFFFFFF,true); + if (CheckDPMI()) + return InitDPMI(baseAddr,bankSize,codeLen,bankFunc); + return InitDOS4GW(baseAddr,bankSize,codeLen,bankFunc); +} + +void PMAPI VF_exit(void) +/**************************************************************************** +* +* Function: VF_exit +* +* Description: Closes down the virtual framebuffer services and +* restores the previous page fault handler. +* +****************************************************************************/ +{ + if (installed) { + if (haveDPMI) { + /* DPMI support */ + } + else { + /* Standard DOS4GW and PMODE/W support */ + RemoveFaultHandler(); + ClosePaging(); + } + installed = false; + } +} + +/*-------------------------------------------------------------------------*/ +/* Support mapped out for other compilers. */ +/*-------------------------------------------------------------------------*/ + +#else + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + (void)baseAddr; + (void)bankSize; + (void)codeLen; + (void)bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c new file mode 100644 index 000000000..53ab16cf4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/dos/ztimer.c @@ -0,0 +1,111 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: MSDOS +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + + +/*---------------------------- Global variables ---------------------------*/ + +uchar * _VARAPI _ZTimerBIOSPtr; + +/*----------------------------- Implementation ----------------------------*/ + +/* External assembler functions */ + +void _ASMAPI LZ_timerOn(void); +ulong _ASMAPI LZ_timerLap(void); +void _ASMAPI LZ_timerOff(void); +ulong _ASMAPI LZ_timerCount(void); +void _ASMAPI LZ_disable(void); +void _ASMAPI LZ_enable(void); + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ + _ZTimerBIOSPtr = PM_getBIOSPointer(); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOn(tm) LZ_timerOn() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerLap(tm) LZ_timerLap() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) LZ_timerOff() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerCount(tm) LZ_timerCount() + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 54925 + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the BIOS timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + ulong ticks; + LZ_disable(); /* Turn of interrupts */ + ticks = PM_getLong(_ZTimerBIOSPtr+0x6C); + LZ_enable(); /* Turn on interrupts again */ + return ticks; +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ + if (finish < start) + finish += 1573040L; /* Number of ticks in 24 hours */ + return finish - start; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/event.c b/board/MAI/bios_emulator/scitech/src/pm/event.c new file mode 100644 index 000000000..b6f458654 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/event.c @@ -0,0 +1,1115 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Main implementation for the SciTech cross platform event +* library. This module contains all the generic cross platform +* code, and pulls in modules specific to each target OS +* environment. +* +****************************************************************************/ + +#include "event.h" +#include "pmapi.h" +#include +#include +#include +#include +#include +#include "oshdr.h" + +/*--------------------------- Global variables ----------------------------*/ + +#define EVENTQSIZE 100 /* Number of events in event queue */ +#define JOY_NUM_AXES 4 /* Number of joystick axes supported */ + +static struct { + int mx,my; /* Current mouse position */ + int head; /* Head of event queue */ + int tail; /* Tail of event queue */ + int freeHead; /* Head of free list */ + int count; /* No. of items currently in queue */ + event_t evtq[EVENTQSIZE]; /* The queue structure itself */ + int oldMove; /* Previous movement event */ + int oldKey; /* Previous key repeat event */ + int oldJoyMove; /* Previous joystick movement event */ + int joyMask; /* Mask of joystick axes present */ + int joyMin[JOY_NUM_AXES]; + int joyCenter[JOY_NUM_AXES]; + int joyMax[JOY_NUM_AXES]; + int joyPrev[JOY_NUM_AXES]; + int joyButState; + ulong doubleClick; + ulong autoRepeat; + ulong autoDelay; + ulong autoTicks; + ulong doubleClickThresh; + ulong firstAuto; + int autoMouse_x; + int autoMouse_y; + event_t downMouse; + ulong keyModifiers; /* Current keyboard modifiers */ + uchar keyTable[128]; /* Table of key up/down flags */ + ibool allowLEDS; /* True if LEDS should change */ + _EVT_userEventFilter userEventCallback; + _EVT_mouseMoveHandler mouseMove; + _EVT_heartBeatCallback heartBeat; + void *heartBeatParams; + codepage_t *codePage; + } EVT; + +/*---------------------------- Implementation -----------------------------*/ + +#if defined(__REALDOS__) || defined(__SMX32__) +/* {secret} */ +void EVTAPI _EVT_cCodeStart(void) {} +#endif + +/* External assembler functions */ + +int EVTAPI _EVT_readJoyAxis(int mask,int *axis); +int EVTAPI _EVT_readJoyButtons(void); + +/* Forward declaration */ + +ulong _EVT_getTicks(void); + +/**************************************************************************** +PARAMETERS: +evt - Event to add to the event queue + +REMARKS: +Adds an event to the event queue by tacking it onto the tail of the event +queue. This routine assumes that at least one spot is available on the +freeList for the event to be inserted. + +NOTE: Interrupts MUST be OFF while this routine is called to ensure we have + mutually exclusive access to our internal data structures for + interrupt driven systems (like under DOS). +****************************************************************************/ +static void addEvent( + event_t *evt) +{ + int evtID; + + /* Check for mouse double click events */ + if (evt->what & EVT_MOUSEEVT) { + EVT.autoMouse_x = evt->where_x; + EVT.autoMouse_y = evt->where_y; + if ((evt->what & EVT_MOUSEDOWN) && !(evt->message & EVT_DBLCLICK)) { + /* Determine if the last mouse event was a double click event */ + uint diff_x = ABS(evt->where_x - EVT.downMouse.where_x); + uint diff_y = ABS(evt->where_y - EVT.downMouse.where_y); + if ((evt->message == EVT.downMouse.message) + && ((evt->when - EVT.downMouse.when) <= EVT.doubleClick) + && (diff_x <= EVT.doubleClickThresh) + && (diff_y <= EVT.doubleClickThresh)) { + evt->message |= EVT_DBLCLICK; + EVT.downMouse = *evt; + EVT.downMouse.when = 0; + } + else + EVT.downMouse = *evt; + EVT.autoTicks = _EVT_getTicks(); + } + else if (evt->what & EVT_MOUSEUP) { + EVT.downMouse.what = EVT_NULLEVT; + EVT.firstAuto = true; + } + } + + /* Call user supplied callback to modify the event if desired */ + if (EVT.userEventCallback) { + if (!EVT.userEventCallback(evt)) + return; + } + + /* Get spot to place the event from the free list */ + evtID = EVT.freeHead; + EVT.freeHead = EVT.evtq[EVT.freeHead].next; + + /* Add to the EVT.tail of the event queue */ + evt->next = -1; + evt->prev = EVT.tail; + if (EVT.tail != -1) + EVT.evtq[EVT.tail].next = evtID; + else + EVT.head = evtID; + EVT.tail = evtID; + EVT.evtq[evtID] = *evt; + EVT.count++; +} + +/**************************************************************************** +REMARKS: +Internal function to initialise the event queue to the empty state. +****************************************************************************/ +static void initEventQueue(void) +{ + int i; + + /* Build free list, and initialize global data structures */ + for (i = 0; i < EVENTQSIZE; i++) + EVT.evtq[i].next = i+1; + EVT.evtq[EVENTQSIZE-1].next = -1; /* Terminate list */ + EVT.count = EVT.freeHead = 0; + EVT.head = EVT.tail = -1; + EVT.oldMove = -1; + EVT.oldKey = -1; + EVT.oldJoyMove = -1; + EVT.joyButState = 0; + EVT.mx = EVT.my = 0; + EVT.keyModifiers = 0; + EVT.allowLEDS = true; + + /* Set default values for mouse double click and mouse auto events */ + EVT.doubleClick = 440; + EVT.autoRepeat = 55; + EVT.autoDelay = 330; + EVT.autoTicks = 0; + EVT.doubleClickThresh = 5; + EVT.firstAuto = true; + EVT.autoMouse_x = EVT.autoMouse_y = 0; + memset(&EVT.downMouse,0,sizeof(EVT.downMouse)); + + /* Setup default pointers for event library */ + EVT.userEventCallback = NULL; + EVT.codePage = &_CP_US_English; + + /* Initialise the joystick module and do basic calibration (which assumes + * the joystick is centered. + */ + EVT.joyMask = EVT_joyIsPresent(); +} + +#if defined(NEED_SCALE_JOY_AXIS) || !defined(USE_OS_JOYSTICK) +/**************************************************************************** +REMARKS: +This function scales a joystick axis value to normalised form. +****************************************************************************/ +static int scaleJoyAxis( + int raw, + int axis) +{ + int scaled,range; + + /* Make sure the joystick is calibrated properly */ + if (EVT.joyCenter[axis] - EVT.joyMin[axis] < 5) + return raw; + if (EVT.joyMax[axis] - EVT.joyCenter[axis] < 5) + return raw; + + /* Now scale the coordinates to -128 to 127 */ + raw -= EVT.joyCenter[axis]; + if (raw < 0) + range = EVT.joyCenter[axis]-EVT.joyMin[axis]; + else + range = EVT.joyMax[axis]-EVT.joyCenter[axis]; + scaled = (raw * 128) / range; + if (scaled < -128) + scaled = -128; + if (scaled > 127) + scaled = 127; + return scaled; +} +#endif + +#if defined(__SMX32__) +#include "smx/event.c" +#elif defined(__RTTARGET__) +#include "rttarget/event.c" +#elif defined(__REALDOS__) +#include "dos/event.c" +#elif defined(__WINDOWS32__) +#include "win32/event.c" +#elif defined(__OS2__) +#if defined(__OS2_PM__) +#include "os2pm/event.c" +#else +#include "os2/event.c" +#endif +#elif defined(__LINUX__) +#if defined(__USE_X11__) +#include "x11/event.c" +#else +#include "linux/event.c" +#endif +#elif defined(__QNX__) +#if defined(__USE_PHOTON__) +#include "photon/event.c" +#elif defined(__USE_X11__) +#include "x11/event.c" +#else +#include "qnx/event.c" +#endif +#elif defined(__BEOS__) +#include "beos/event.c" +#else +#error Event library not ported to this platform yet! +#endif + +/*------------------------ Public interface routines ----------------------*/ + +/* If USE_OS_JOYSTICK is defined, the OS specific libraries will implement + * the joystick code rather than using the generic OS portable version. + */ + +#ifndef USE_OS_JOYSTICK +/**************************************************************************** +DESCRIPTION: +Returns the mask indicating what joystick axes are attached. + +HEADER: +event.h + +REMARKS: +This function is used to detect the attached joysticks, and determine +what axes are present and functioning. This function will re-detect any +attached joysticks when it is called, so if the user forgot to attach +the joystick when the application started, you can call this function to +re-detect any newly attached joysticks. + +SEE ALSO: +EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +int EVTAPI EVT_joyIsPresent(void) +{ + int mask,i; + + memset(EVT.joyMin,0,sizeof(EVT.joyMin)); + memset(EVT.joyCenter,0,sizeof(EVT.joyCenter)); + memset(EVT.joyMax,0,sizeof(EVT.joyMax)); + memset(EVT.joyPrev,0,sizeof(EVT.joyPrev)); + EVT.joyButState = 0; +#ifdef __LINUX__ + PM_init(); +#endif + mask = _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); + if (mask) { + for (i = 0; i < JOY_NUM_AXES; i++) + EVT.joyMax[i] = EVT.joyCenter[i]*2; + } + return mask; +} + +/**************************************************************************** +DESCRIPTION: +Polls the joystick for position and button information. + +HEADER: +event.h + +REMARKS: +This routine is used to poll analogue joysticks for button and position +information. It should be called once for each main loop of the user +application, just before processing all pending events via EVT_getNext. +All information polled from the joystick will be posted to the event +queue for later retrieval. + +Note: Most analogue joysticks will provide readings that change even + though the joystick has not moved. Hence if you call this routine + you will likely get an EVT_JOYMOVE event every time through your + event loop. + +SEE ALSO: +EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight, +EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_pollJoystick(void) +{ + event_t evt; + int i,axis[JOY_NUM_AXES],newButState,mask,moved,ps; + + if (EVT.joyMask) { + /* Read joystick axes and post movement events if they have + * changed since the last time we polled. Until the events are + * actually flushed, we keep modifying the same joystick movement + * event, so you won't get multiple movement event + */ + mask = _EVT_readJoyAxis(EVT.joyMask,axis); + newButState = _EVT_readJoyButtons(); + moved = false; + for (i = 0; i < JOY_NUM_AXES; i++) { + if (mask & (EVT_JOY_AXIS_X1 << i)) + axis[i] = scaleJoyAxis(axis[i],i); + else + axis[i] = EVT.joyPrev[i]; + if (axis[i] != EVT.joyPrev[i]) + moved = true; + } + if (moved) { + memcpy(EVT.joyPrev,axis,sizeof(EVT.joyPrev)); + ps = _EVT_disableInt(); + if (EVT.oldJoyMove != -1) { + /* Modify the existing joystick movement event */ + EVT.evtq[EVT.oldJoyMove].message = newButState; + EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; + EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; + EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; + EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; + } + else if (EVT.count < EVENTQSIZE) { + /* Add a new joystick movement event */ + EVT.oldJoyMove = EVT.freeHead; + memset(&evt,0,sizeof(evt)); + evt.what = EVT_JOYMOVE; + evt.message = EVT.joyButState; + evt.where_x = EVT.joyPrev[0]; + evt.where_y = EVT.joyPrev[1]; + evt.relative_x = EVT.joyPrev[2]; + evt.relative_y = EVT.joyPrev[3]; + addEvent(&evt); + } + _EVT_restoreInt(ps); + } + + /* Read the joystick buttons, and post events to reflect the change + * in state for the joystick buttons. + */ + if (newButState != EVT.joyButState) { + if (EVT.count < EVENTQSIZE) { + /* Add a new joystick click event */ + ps = _EVT_disableInt(); + memset(&evt,0,sizeof(evt)); + evt.what = EVT_JOYCLICK; + evt.message = newButState; + EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; + EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; + EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; + EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; + addEvent(&evt); + _EVT_restoreInt(ps); + } + EVT.joyButState = newButState; + } + } +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick upper left position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the upper left +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetUpperLeft(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMin); +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick lower right position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the lower right +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetLowerRight(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMax); +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick center position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the center +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter +****************************************************************************/ +void EVTAPI EVT_joySetCenter(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); +} +#endif + +/**************************************************************************** +DESCRIPTION: +Posts a user defined event to the event queue + +HEADER: +event.h + +RETURNS: +True if event was posted, false if event queue is full. + +PARAMETERS: +what - Type code for message to post +message - Event specific message to post +modifiers - Event specific modifier flags to post + +REMARKS: +This routine is used to post user defined events to the event queue. + +SEE ALSO: +EVT_flush, EVT_getNext, EVT_peekNext, EVT_halt +****************************************************************************/ +ibool EVTAPI EVT_post( + ulong which, + ulong what, + ulong message, + ulong modifiers) +{ + event_t evt; + uint ps; + + if (EVT.count < EVENTQSIZE) { + /* Save information in event record */ + ps = _EVT_disableInt(); + evt.which = which; + evt.when = _EVT_getTicks(); + evt.what = what; + evt.message = message; + evt.modifiers = modifiers; + addEvent(&evt); /* Add to EVT.tail of event queue */ + _EVT_restoreInt(ps); + return true; + } + else + return false; +} + +/**************************************************************************** +DESCRIPTION: +Flushes all events of a specified type from the event queue. + +PARAMETERS: +mask - Mask specifying the types of events that should be removed + +HEADER: +event.h + +REMARKS: +Flushes (removes) all pending events of the specified type from the event +queue. You may combine the masks for different event types with a simple +logical OR. + +SEE ALSO: +EVT_getNext, EVT_halt, EVT_peekNext +****************************************************************************/ +void EVTAPI EVT_flush( + ulong mask) +{ + event_t evt; + + do { /* Flush all events */ + EVT_getNext(&evt,mask); + } while (evt.what != EVT_NULLEVT); +} + +/**************************************************************************** +DESCRIPTION: +Halts until and event of the specified type is recieved. + +HEADER: +event.h + +PARAMETERS: +evt - Pointer to +mask - Mask specifying the types of events that should be removed + +REMARKS: +This functions halts exceution until an event of the specified type is +recieved into the event queue. It does not flush the event queue of events +before performing the busy loop. However this function does throw away +any events other than the ones you have requested via the event mask, to +avoid the event queue filling up with unwanted events (like EVT_KEYUP or +EVT_MOUSEMOVE events). + +SEE ALSO: +EVT_getNext, EVT_flush, EVT_peekNext +****************************************************************************/ +void EVTAPI EVT_halt( + event_t *evt, + ulong mask) +{ + do { /* Wait for an event */ + if (mask & (EVT_JOYEVT)) + EVT_pollJoystick(); + EVT_getNext(evt,EVT_EVERYEVT); + } while (!(evt->what & mask)); +} + +/**************************************************************************** +DESCRIPTION: +Peeks at the next pending event in the event queue. + +HEADER: +event.h + +RETURNS: +True if an event is pending, false if not. + +PARAMETERS: +evt - Pointer to structure to return the event info in +mask - Mask specifying the types of events that should be removed + +REMARKS: +Peeks at the next pending event of the specified type in the event queue. The +mask parameter is used to specify the type of events to be peeked at, and +can be any logical combination of any of the flags defined by the +EVT_eventType enumeration. + +In contrast to EVT_getNext, the event is not removed from the event queue. +You may combine the masks for different event types with a simple logical OR. + +SEE ALSO: +EVT_flush, EVT_getNext, EVT_halt +****************************************************************************/ +ibool EVTAPI EVT_peekNext( + event_t *evt, + ulong mask) +{ + int evtID; + uint ps; + + if (EVT.heartBeat) + EVT.heartBeat(EVT.heartBeatParams); + _EVT_pumpMessages(); /* Pump all messages into queue */ + EVT.mouseMove(EVT.mx,EVT.my); /* Move the mouse cursor */ + evt->what = EVT_NULLEVT; /* Default to null event */ + if (EVT.count) { + /* It is possible that an event be posted while we are trying + * to access the event queue. This would create problems since + * we may end up with invalid data for our event queue pointers. To + * alleviate this, all interrupts are suspended while we manipulate + * our pointers. + */ + ps = _EVT_disableInt(); /* disable interrupts */ + for (evtID = EVT.head; evtID != -1; evtID = EVT.evtq[evtID].next) { + if (EVT.evtq[evtID].what & mask) + break; /* Found an event */ + } + if (evtID == -1) { + _EVT_restoreInt(ps); + return false; /* Event was not found */ + } + *evt = EVT.evtq[evtID]; /* Return the event */ + _EVT_restoreInt(ps); + if (evt->what & EVT_KEYEVT) + _EVT_maskKeyCode(evt); + } + return evt->what != EVT_NULLEVT; +} + +/**************************************************************************** +DESCRIPTION: +Retrieves the next pending event from the event queue. + +PARAMETERS: +evt - Pointer to structure to return the event info in +mask - Mask specifying the types of events that should be removed + +HEADER: +event.h + +RETURNS: +True if an event was pending, false if not. + +REMARKS: +Retrieves the next pending event from the event queue, and stores it in a +event_t structure. The mask parameter is used to specify the type of events +to be removed, and can be any logical combination of any of the flags defined +by the EVT_eventType enumeration. + +The what field of the event contains the event code of the event that was +extracted. All application specific events should begin with the EVT_USEREVT +code and build from there. Since the event code is stored in an integer, +there is a maximum of 32 different event codes that can be distinguished. +You can store extra information about the event in the message field to +distinguish between events of the same class (for instance the button used in +a EVT_MOUSEDOWN event). + +If an event of the specified type was not in the event queue, the what field +of the event will be set to NULLEVT, and the return value will return false. + +Note: You should /always/ use the EVT_EVERYEVT mask for extracting events + from your main event loop handler. Using a mask for only a specific + type of event for long periods of time will cause the event queue to + fill up with events of the type you are ignoring, eventually causing + the application to hang when the event queue becomes full. + +SEE ALSO: +EVT_flush, EVT_halt, EVT_peekNext +****************************************************************************/ +ibool EVTAPI EVT_getNext( + event_t *evt, + ulong mask) +{ + int evtID,next,prev; + uint ps; + + if (EVT.heartBeat) + EVT.heartBeat(EVT.heartBeatParams); + _EVT_pumpMessages(); /* Pump all messages into queue */ + EVT.mouseMove(EVT.mx,EVT.my); /* Move the mouse cursor */ + evt->what = EVT_NULLEVT; /* Default to null event */ + if (EVT.count) { + /* It is possible that an event be posted while we are trying + * to access the event queue. This would create problems since + * we may end up with invalid data for our event queue pointers. To + * alleviate this, all interrupts are suspended while we manipulate + * our pointers. + */ + ps = _EVT_disableInt(); /* disable interrupts */ + for (evtID = EVT.head; evtID != -1; evtID = EVT.evtq[evtID].next) { + if (EVT.evtq[evtID].what & mask) + break; /* Found an event */ + } + if (evtID == -1) { + _EVT_restoreInt(ps); + return false; /* Event was not found */ + } + next = EVT.evtq[evtID].next; + prev = EVT.evtq[evtID].prev; + if (prev != -1) + EVT.evtq[prev].next = next; + else + EVT.head = next; + if (next != -1) + EVT.evtq[next].prev = prev; + else + EVT.tail = prev; + *evt = EVT.evtq[evtID]; /* Return the event */ + EVT.evtq[evtID].next = EVT.freeHead; /* and return to free list */ + EVT.freeHead = evtID; + EVT.count--; + if (evt->what == EVT_MOUSEMOVE) + EVT.oldMove = -1; + if (evt->what == EVT_KEYREPEAT) + EVT.oldKey = -1; + if (evt->what == EVT_JOYMOVE) + EVT.oldJoyMove = -1; + _EVT_restoreInt(ps); /* enable interrupts */ + if (evt->what & EVT_KEYEVT) + _EVT_maskKeyCode(evt); + } + + /* If there is no event pending, check if we should generate an auto + * mouse down event if the mouse is still currently down. + */ + if (evt->what == EVT_NULLEVT && EVT.autoRepeat && (mask & EVT_MOUSEAUTO) && (EVT.downMouse.what & EVT_MOUSEDOWN)) { + ulong ticks = _EVT_getTicks(); + if ((ticks - EVT.autoTicks) >= (EVT.autoRepeat + (EVT.firstAuto ? EVT.autoDelay : 0))) { + evt->what = EVT_MOUSEAUTO; + evt->message = EVT.downMouse.message; + evt->modifiers = EVT.downMouse.modifiers; + evt->where_x = EVT.autoMouse_x; + evt->where_y = EVT.autoMouse_y; + evt->relative_x = 0; + evt->relative_y = 0; + EVT.autoTicks = evt->when = ticks; + EVT.firstAuto = false; + } + } + return evt->what != EVT_NULLEVT; +} + +/**************************************************************************** +DESCRIPTION: +Installs a user supplied event filter callback for event handling. + +HEADER: +event.h + +PARAMETERS: +userEventFilter - Address of user supplied event filter callback + +REMARKS: +This function allows the application programmer to install an event filter +callback for event handling. Once you install your callback, the MGL +event handling routines will call your callback with a pointer to the +new event that will be placed into the event queue. Your callback can the +modify the contents of the event before it is placed into the queue (for +instance adding custom information or perhaps high precision timing +information). + +If your callback returns FALSE, the event will be ignore and will not be +posted to the event queue. You should always return true from your event +callback unless you plan to use the events immediately that they are +recieved. + +Note: Your event callback may be called in response to a hardware + interrupt and will be executing in the context of the hardware + interrupt handler under MSDOS (ie: keyboard interrupt or mouse + interrupt). For this reason the code pages for the callback that + you register must be locked in memory with the PM_lockCodePages + function. You must also lock down any data pages that your function + needs to reference as well. + +Note: You can also use this filter callback to process events at the + time they are activated by the user (ie: when the user hits the + key or moves the mouse), but make sure your code runs as fast as + possible as it will be executing inside the context of an interrupt + handler on some systems. + +SEE ALSO: +EVT_getNext, EVT_peekNext +****************************************************************************/ +void EVTAPI EVT_setUserEventFilter( + _EVT_userEventFilter filter) +{ + EVT.userEventCallback = filter; +} + +/**************************************************************************** +DESCRIPTION: +Installs a user supplied event heartbeat callback function. + +HEADER: +event.h + +PARAMETERS: +callback - Address of user supplied event heartbeat callback +params - Parameters to pass to the event heartbeat function + +REMARKS: +This function allows the application programmer to install an event heatbeat +function that gets called every time that EVT_getNext or EVT_peekNext +is called. This is primarily useful for simulating text mode cursors inside +event handling code when running in graphics modes as opposed to hardware +text modes. + +SEE ALSO: +EVT_getNext, EVT_peekNext, EVT_getHeartBeatCallback +****************************************************************************/ +void EVTAPI EVT_setHeartBeatCallback( + _EVT_heartBeatCallback callback, + void *params) +{ + EVT.heartBeat = callback; + EVT.heartBeatParams = params; +} + + +/**************************************************************************** +DESCRIPTION: +Returns the current user supplied event heartbeat callback function. + +HEADER: +event.h + +PARAMETERS: +callback - Place to store the address of user supplied event heartbeat callback +params - Place to store the parameters to pass to the event heartbeat function + +REMARKS: +This function retrieves the current event heatbeat function that gets called +every time that EVT_getNext or EVT_peekNext is called. + +SEE ALSO: +EVT_getNext, EVT_peekNext, EVT_setHeartBeatCallback +****************************************************************************/ +void EVTAPI EVT_getHeartBeatCallback( + _EVT_heartBeatCallback *callback, + void **params) +{ + *callback = EVT.heartBeat; + *params = EVT.heartBeatParams; +} + +/**************************************************************************** +DESCRIPTION: +Determines if a specified key is currently down. + +PARAMETERS: +scanCode - Scan code to test + +RETURNS: +True of the specified key is currently held down. + +HEADER: +event.h + +REMARKS: +This function determines if a specified key is currently down at the +time that the call is made. You simply need to pass in the scan code of +the key that you wish to test, and the MGL will tell you if it is currently +down or not. The MGL does this by keeping track of the up and down state +of all the keys. +****************************************************************************/ +ibool EVTAPI EVT_isKeyDown( + uchar scanCode) +{ + return _EVT_isKeyDown(scanCode); +} + +/**************************************************************************** +DESCRIPTION: +Set the mouse position for the event module + +PARAMETERS: +x - X coordinate to move the mouse cursor position to +y - Y coordinate to move the mouse cursor position to + +HEADER: +event.h + +REMARKS: +This function moves the mouse cursor position for the event module to the +specified location. + +SEE ALSO: +EVT_getMousePos +****************************************************************************/ +void EVTAPI EVT_setMousePos( + int x, + int y) +{ + EVT.mx = x; + EVT.my = y; + _EVT_setMousePos(&EVT.mx,&EVT.my); + EVT.mouseMove(EVT.mx,EVT.my); +} + +/**************************************************************************** +DESCRIPTION: +Returns the current mouse cursor location. + +HEADER: +event.h + +PARAMETERS: +x - Place to store value for mouse x coordinate (screen coordinates) +y - Place to store value for mouse y coordinate (screen coordinates) + +REMARKS: +Obtains the current mouse cursor position in screen coordinates. Normally the +mouse cursor location is tracked using the mouse movement events that are +posted to the event queue when the mouse moves, however this routine +provides an alternative method of polling the mouse cursor location. + +SEE ALSO: +EVT_setMousePos +****************************************************************************/ +void EVTAPI EVT_getMousePos( + int *x, + int *y) +{ + *x = EVT.mx; + *y = EVT.my; +} + +/**************************************************************************** +DESCRIPTION: +Returns the currently active code page for translation of keyboard characters. + +HEADER: +event.h + +RETURNS: +Pointer to the currently active code page translation table. + +REMARKS: +This function is returns a pointer to the currently active code page +translation table. See EVT_setCodePage for more information. + +SEE ALSO: +EVT_setCodePage +****************************************************************************/ +codepage_t * EVTAPI EVT_getCodePage(void) +{ + return EVT.codePage; +} + +/**************************************************************************** +DESCRIPTION: +Sets the currently active code page for translation of keyboard characters. + +HEADER: +event.h + +PARAMETERS: +page - New code page to make active + +REMARKS: +This function is used to set a new code page translation table that is used +to translate virtual scan code values to ASCII characters for different +keyboard configurations. The default is usually US English, although if +possible the PM library will auto-detect the correct code page translation +for the target OS if OS services are available to determine what type of +keyboard is currently attached. + +SEE ALSO: +EVT_getCodePage +****************************************************************************/ +void EVTAPI EVT_setCodePage( + codepage_t *page) +{ + EVT.codePage = page; +} + +/* The following contains fake C prototypes and documentation for the + * macro functions in the event.h header file. These exist soley so + * that DocJet will correctly pull in the documentation for these functions. + */ +#ifdef INCLUDE_DOC_FUNCTIONS + +/**************************************************************************** +DESCRIPTION: +Macro to extract the ASCII code from a message. + +PARAMETERS: +message - Message to extract ASCII code from + +RETURNS: +ASCII code extracted from the message. + +HEADER: +event.h + +REMARKS: +Macro to extract the ASCII code from the message field of the event_t +structure. You pass the message field to the macro as the parameter and +the ASCII code is the result, for example: + + event_t EVT.myEvent; + uchar code; + code = EVT_asciiCode(EVT.myEvent.message); + +SEE ALSO: +EVT_scanCode, EVT_repeatCount +****************************************************************************/ +uchar EVT_asciiCode( + ulong message); + +/**************************************************************************** +DESCRIPTION: +Macro to extract the keyboard scan code from a message. + +HEADER: +event.h + +PARAMETERS: +message - Message to extract scan code from + +RETURNS: +Keyboard scan code extracted from the message. + +REMARKS: +Macro to extract the keyboard scan code from the message field of the event +structure. You pass the message field to the macro as the parameter and +the scan code is the result, for example: + + event_t EVT.myEvent; + uchar code; + code = EVT_scanCode(EVT.myEvent.message); + +NOTE: Scan codes in the event library are not really hardware scan codes, + but rather virtual scan codes as generated by a low level keyboard + interface driver. All virtual scan code values are defined by the + EVT_scanCodesType enumeration, and will be identical across all + supports OS'es and platforms. + +SEE ALSO: +EVT_asciiCode, EVT_repeatCount +****************************************************************************/ +uchar EVT_scanCode( + ulong message); + +/**************************************************************************** +DESCRIPTION: +Macro to extract the repeat count from a message. + +HEADER: +event.h + +PARAMETERS: +message - Message to extract repeat count from + +RETURNS: +Repeat count extracted from the message. + +REMARKS: +Macro to extract the repeat count from the message field of the event +structure. The repeat count is the number of times that the key repeated +before there was another keyboard event to be place in the queue, and +allows the event handling code to avoid keyboard buffer overflow +conditions when a single key is held down by the user. If you are processing +a key repeat code, you will probably want to check this field to see how +many key repeats you should process for this message. + +SEE ALSO: +EVT_asciiCode, EVT_repeatCount +****************************************************************************/ +short EVT_repeatCount( + ulong message); + +#endif /* DOC FUNCTIONS */ + +#if defined(__REALDOS__) || defined(__SMX32__) +/* {secret} */ +void EVTAPI _EVT_cCodeEnd(void) {} +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c new file mode 100644 index 000000000..e88d21095 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/cpuinfo.c @@ -0,0 +1,68 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: Linux specific code for the CPU detection module. +* +****************************************************************************/ + +#include + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +TODO: We should implement this for Linux! +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +TODO: We should implement this for Linux! +****************************************************************************/ +#define RestoreThreadPriority(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + freq->low = 1000000; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + struct timeval tv; \ + gettimeofday(&tv,NULL); \ + (t)->low = tv.tv_sec*1000000 + tv.tv_usec; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/event.c b/board/MAI/bios_emulator/scitech/src/pm/linux/event.c new file mode 100644 index 000000000..ce3873209 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/event.c @@ -0,0 +1,1360 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: Linux fullscreen console implementation for the SciTech +* cross platform event library. +* Portions ripped straigth from the gpm source code for mouse +* handling. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +extern int _PM_console_fd; +static ushort keyUpMsg[256] = {0}; +static int _EVT_mouse_fd = 0; +static int range_x, range_y; +static int opt_baud = 1200, opt_sample = 100; +#ifdef USE_OS_JOYSTICK +static short *axis0 = NULL, *axis1 = NULL; +static uchar *buts0 = NULL, *buts1 = NULL; +static int joystick0_fd = 0, joystick1_fd = 0; +static int js_version = 0; +#endif + +/* This defines the supported mouse drivers */ + +typedef enum { + EVT_noMouse = -1, + EVT_microsoft = 0, + EVT_ps2, + EVT_mousesystems, + EVT_gpm, + EVT_MMseries, + EVT_logitech, + EVT_busmouse, + EVT_mouseman, + EVT_intellimouse, + EVT_intellimouse_ps2, + } mouse_drivers_t; + +static mouse_drivers_t mouse_driver = EVT_noMouse; +static char mouse_dev[20] = "/dev/mouse"; + +typedef struct { + char *name; + int flags; + void (*init)(void); + uchar proto[4]; + int packet_len; + int read; + } mouse_info; + +#define STD_FLG (CREAD | CLOCAL | HUPCL) + +static void _EVT_mouse_init(void); +static void _EVT_logitech_init(void); +static void _EVT_pnpmouse_init(void); + +mouse_info mouse_infos[] = { + {"Microsoft", CS7 | B1200 | STD_FLG, _EVT_mouse_init, {0x40, 0x40, 0x40, 0x00}, 3, 1}, + {"PS2", STD_FLG, NULL, {0xc0, 0x00, 0x00, 0x00}, 3, 1}, + {"MouseSystems", CS8 | CSTOPB | STD_FLG, _EVT_mouse_init, {0xf8, 0x80, 0x00, 0x00}, 5, 5}, + {"GPM", CS8 | CSTOPB | STD_FLG, NULL, {0xf8, 0x80, 0x00, 0x00}, 5, 5}, + {"MMSeries", CS8 | PARENB | PARODD | STD_FLG, _EVT_mouse_init, {0xe0, 0x80, 0x80, 0x00}, 3, 1}, + {"Logitech", CS8 | CSTOPB | STD_FLG, _EVT_logitech_init, {0xe0, 0x80, 0x80, 0x00}, 3, 3}, + {"BusMouse", STD_FLG, NULL, {0xf8, 0x80, 0x00, 0x00}, 3, 3}, + {"MouseMan", CS7 | STD_FLG, _EVT_mouse_init, {0x40, 0x40, 0x40, 0x00}, 3, 1}, + {"IntelliMouse", CS7 | STD_FLG, _EVT_pnpmouse_init, {0xc0, 0x40, 0xc0, 0x00}, 4, 1}, + {"IMPS2", CS7 | STD_FLG, NULL, {0xc0, 0x40, 0xc0, 0x00}, 4, 1}, /* ? */ + }; + +#define NB_MICE (sizeof(mouse_infos)/sizeof(mouse_info)) + +/* The name of the environment variables that are used to change the defaults above */ + +#define ENV_MOUSEDRV "MGL_MOUSEDRV" +#define ENV_MOUSEDEV "MGL_MOUSEDEV" +#define ENV_MOUSESPD "MGL_MOUSESPD" +#define ENV_JOYDEV0 "MGL_JOYDEV1" +#define ENV_JOYDEV1 "MGL_JOYDEV2" + +/* Scancode mappings on Linux for special keys */ + +typedef struct { + int scan; + int map; + } keymap; + +/* TODO: Fix this and set it up so we can do a binary search! */ + +keymap keymaps[] = { + {96, KB_padEnter}, + {74, KB_padMinus}, + {78, KB_padPlus}, + {55, KB_padTimes}, + {98, KB_padDivide}, + {71, KB_padHome}, + {72, KB_padUp}, + {73, KB_padPageUp}, + {75, KB_padLeft}, + {76, KB_padCenter}, + {77, KB_padRight}, + {79, KB_padEnd}, + {80, KB_padDown}, + {81, KB_padPageDown}, + {82, KB_padInsert}, + {83, KB_padDelete}, + {105,KB_left}, + {108,KB_down}, + {106,KB_right}, + {103,KB_up}, + {110,KB_insert}, + {102,KB_home}, + {104,KB_pageUp}, + {111,KB_delete}, + {107,KB_end}, + {109,KB_pageDown}, + {125,KB_leftWindows}, + {126,KB_rightWindows}, + {127,KB_menu}, + {100,KB_rightAlt}, + {97,KB_rightCtrl}, + }; + +/* And the keypad with num lock turned on (changes the ASCII code only) */ + +keymap keypad[] = { + {71, ASCII_7}, + {72, ASCII_8}, + {73, ASCII_9}, + {75, ASCII_4}, + {76, ASCII_5}, + {77, ASCII_6}, + {79, ASCII_1}, + {80, ASCII_2}, + {81, ASCII_3}, + {82, ASCII_0}, + {83, ASCII_period}, + }; + +#define NB_KEYMAPS (sizeof(keymaps)/sizeof(keymaps[0])) +#define NB_KEYPAD (sizeof(keypad)/sizeof(keypad[0])) + +typedef struct { + int sample; + char code[2]; + } sample_rate; + +sample_rate sampletab[]={ + { 0,"O"}, + { 15,"J"}, + { 27,"K"}, + { 42,"L"}, + { 60,"R"}, + { 85,"M"}, + {125,"Q"}, + {1E9,"N"}, + }; + +/* Number of keycodes to read at a time from the console */ + +#define KBDREADBUFFERSIZE 32 + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under Linux */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flaps) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + static uint starttime = 0; + struct timeval t; + + gettimeofday(&t, NULL); + if (starttime == 0) + starttime = t.tv_sec * 1000 + (t.tv_usec/1000); + return ((t.tv_sec * 1000 + (t.tv_usec/1000)) - starttime); +} + +/**************************************************************************** +REMARKS: +Small Unix function that checks for availability on a file using select() +****************************************************************************/ +static ibool dataReady( + int fd) +{ + static struct timeval t = { 0L, 0L }; + fd_set fds; + + FD_ZERO(&fds); + FD_SET(fd, &fds); + return select(fd+1, &fds, NULL, NULL, &t) > 0; +} + +/**************************************************************************** +REMARKS: +Reads mouse data according to the selected mouse driver. +****************************************************************************/ +static ibool readMouseData( + int *buttons, + int *dx, + int *dy) +{ + static uchar data[32],prev = 0; + int cnt = 0,ret; + mouse_info *drv; + + /* Read the first byte to check for the protocol */ + drv = &mouse_infos[mouse_driver]; + if (read(_EVT_mouse_fd, data, drv->read) != drv->read) { + perror("read"); + return false; + } + if ((data[0] & drv->proto[0]) != drv->proto[1]) + return false; + + /* Load a whole protocol packet */ + cnt += drv->read; + while (cnt < drv->packet_len) { + ret = read(_EVT_mouse_fd, data+cnt, drv->read); + if (ret == drv->read) + cnt += ret; + else { + perror("read"); + return false; + } + } + if ((data[1] & drv->proto[2]) != drv->proto[3]) + return false; + + /* Now decode the protocol packet */ + switch (mouse_driver) { + case EVT_microsoft: + if (data[0] == 0x40 && !(prev|data[1]|data[2])) + *buttons = 2; /* Third button on MS compatible mouse */ + else + *buttons= ((data[0] & 0x20) >> 3) | ((data[0] & 0x10) >> 4); + prev = *buttons; + *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F)); + *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F)); + break; + case EVT_ps2: + *buttons = !!(data[0]&1) * 4 + !!(data[0]&2) * 1 + !!(data[0]&4) * 2; + if (data[1] != 0) + *dx = (data[0] & 0x10) ? data[1]-256 : data[1]; + else + *dx = 0; + if (data[2] != 0) + *dy = -((data[0] & 0x20) ? data[2]-256 : data[2]); + else + *dy = 0; + break; + case EVT_mousesystems: case EVT_gpm: + *buttons = (~data[0]) & 0x07; + *dx = (char)(data[1]) + (char)(data[3]); + *dy = -((char)(data[2]) + (char)(data[4])); + break; + case EVT_logitech: + *buttons= data[0] & 0x07; + *dx = (data[0] & 0x10) ? data[1] : - data[1]; + *dy = (data[0] & 0x08) ? - data[2] : data[2]; + break; + case EVT_busmouse: + *buttons= (~data[0]) & 0x07; + *dx = (char)data[1]; + *dy = -(char)data[2]; + break; + case EVT_MMseries: + *buttons = data[0] & 0x07; + *dx = (data[0] & 0x10) ? data[1] : - data[1]; + *dy = (data[0] & 0x08) ? - data[2] : data[2]; + break; + case EVT_intellimouse: + *buttons = ((data[0] & 0x20) >> 3) /* left */ + | ((data[3] & 0x10) >> 3) /* middle */ + | ((data[0] & 0x10) >> 4); /* right */ + *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F)); + *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F)); + break; + case EVT_intellimouse_ps2: + *buttons = (data[0] & 0x04) >> 1 /* Middle */ + | (data[0] & 0x02) >> 1 /* Right */ + | (data[0] & 0x01) << 2; /* Left */ + *dx = (data[0] & 0x10) ? data[1]-256 : data[1]; + *dy = (data[0] & 0x20) ? -(data[2]-256) : -data[2]; + break; + case EVT_mouseman: { + static int getextra; + static uchar prev=0; + uchar b; + + /* The damned MouseMan has 3/4 bytes packets. The extra byte + * is only there if the middle button is active. + * I get the extra byte as a packet with magic numbers in it. + * and then switch to 4-byte mode. + */ + if (data[1] == 0xAA && data[2] == 0x55) { + /* Got unexpected fourth byte */ + if ((b = (*data>>4)) > 0x3) + return false; /* just a sanity check */ + *dx = *dy = 0; + drv->packet_len=4; + getextra=0; + } + else { + /* Got 3/4, as expected */ + /* Motion is independent of packetlen... */ + *dx = (char)(((data[0] & 0x03) << 6) | (data[1] & 0x3F)); + *dy = (char)(((data[0] & 0x0C) << 4) | (data[2] & 0x3F)); + prev = ((data[0] & 0x20) >> 3) | ((data[0] & 0x10) >> 4); + if (drv->packet_len==4) + b = data[3]>>4; + } + if (drv->packet_len == 4) { + if (b == 0) { + drv->packet_len = 3; + getextra = 1; + } + else { + if (b & 0x2) + prev |= 2; + } + } + *buttons = prev; + + /* This "chord-middle" behaviour was reported by David A. van Leeuwen */ + if (((prev ^ *buttons) & 5) == 5) + *buttons = *buttons ? 2 : 0; + prev = *buttons; + break; + } + case EVT_noMouse: + return false; + break; + } + return true; +} + +/**************************************************************************** +REMARKS: +Map a keypress via the key mapping table +****************************************************************************/ +static int getKeyMapping( + keymap *tab, + int nb, + int key) +{ + int i; + + for(i = 0; i < nb; i++) { + if (tab[i].scan == key) + return tab[i].map; + } + return key; +} + +#ifdef USE_OS_JOYSTICK + +static char js0_axes = 0, js0_buttons = 0; +static char js1_axes = 0, js1_buttons = 0; +static char joystick0_dev[20] = "/dev/js0"; +static char joystick1_dev[20] = "/dev/js1"; + +/**************************************************************************** +REMARKS: +Create a joystick event from the joystick data +****************************************************************************/ +static void makeJoyEvent( + event_t *evt) +{ + evt->message = 0; + if (buts0 && axis0) { + if (buts0[0]) evt->message |= EVT_JOY1_BUTTONA; + if (buts0[1]) evt->message |= EVT_JOY1_BUTTONB; + evt->where_x = axis0[0]; + evt->where_y = axis0[1]; + } + else + evt->where_x = evt->where_y = 0; + if (buts1 && axis1) { + if (buts1[0]) evt->message |= EVT_JOY2_BUTTONA; + if (buts1[1]) evt->message |= EVT_JOY2_BUTTONB; + evt->where_x = axis1[0]; + evt->where_y = axis1[1]; + } + else + evt->where_x = evt->where_y = 0; +} + +/**************************************************************************** +REMARKS: +Read the joystick axis data +****************************************************************************/ +int EVTAPI _EVT_readJoyAxis( + int jmask, + int *axis) +{ + int mask = 0; + + if ((js_version & ~0xffff) == 0) { + /* Old 0.x driver */ + struct JS_DATA_TYPE js; + if (joystick0_fd && read(joystick0_fd, &js, JS_RETURN) == JS_RETURN) { + if (jmask & EVT_JOY_AXIS_X1) + axis[0] = js.x; + if (jmask & EVT_JOY_AXIS_Y1) + axis[1] = js.y; + mask |= EVT_JOY_AXIS_X1|EVT_JOY_AXIS_Y1; + } + if (joystick1_fd && read(joystick1_fd, &js, JS_RETURN) == JS_RETURN) { + if (jmask & EVT_JOY_AXIS_X2) + axis[2] = js.x; + if (jmask & EVT_JOY_AXIS_Y2) + axis[3] = js.y; + mask |= EVT_JOY_AXIS_X2|EVT_JOY_AXIS_Y2; + } + } + else { + if (axis0) { + if (jmask & EVT_JOY_AXIS_X1) + axis[0] = axis0[0]; + if (jmask & EVT_JOY_AXIS_Y1) + axis[1] = axis0[1]; + mask |= EVT_JOY_AXIS_X1 | EVT_JOY_AXIS_Y1; + } + if (axis1) { + if (jmask & EVT_JOY_AXIS_X2) + axis[2] = axis1[0]; + if (jmask & EVT_JOY_AXIS_Y2) + axis[3] = axis1[1]; + mask |= EVT_JOY_AXIS_X2 | EVT_JOY_AXIS_Y2; + } + } + return mask; +} + +/**************************************************************************** +REMARKS: +Read the joystick button data +****************************************************************************/ +int EVTAPI _EVT_readJoyButtons(void) +{ + int buts = 0; + + if ((js_version & ~0xffff) == 0) { + /* Old 0.x driver */ + struct JS_DATA_TYPE js; + if (joystick0_fd && read(joystick0_fd, &js, JS_RETURN) == JS_RETURN) + buts = js.buttons; + if (joystick1_fd && read(joystick1_fd, &js, JS_RETURN) == JS_RETURN) + buts |= js.buttons << 2; + } + else { + if (buts0) + buts |= EVT_JOY1_BUTTONA*buts0[0] + EVT_JOY1_BUTTONB*buts0[1]; + if (buts1) + buts |= EVT_JOY2_BUTTONA*buts1[0] + EVT_JOY2_BUTTONB*buts1[1]; + } + return buts; +} + +/**************************************************************************** +DESCRIPTION: +Returns the mask indicating what joystick axes are attached. + +HEADER: +event.h + +REMARKS: +This function is used to detect the attached joysticks, and determine +what axes are present and functioning. This function will re-detect any +attached joysticks when it is called, so if the user forgot to attach +the joystick when the application started, you can call this function to +re-detect any newly attached joysticks. + +SEE ALSO: +EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +int EVTAPI EVT_joyIsPresent(void) +{ + static int mask = 0; + int i; + char *tmp, name0[128], name1[128]; + static ibool inited = false; + + if (inited) + return mask; + memset(EVT.joyMin,0,sizeof(EVT.joyMin)); + memset(EVT.joyCenter,0,sizeof(EVT.joyCenter)); + memset(EVT.joyMax,0,sizeof(EVT.joyMax)); + memset(EVT.joyPrev,0,sizeof(EVT.joyPrev)); + EVT.joyButState = 0; + if ((tmp = getenv(ENV_JOYDEV0)) != NULL) + strcpy(joystick0_dev,tmp); + if ((tmp = getenv(ENV_JOYDEV1)) != NULL) + strcpy(joystick1_dev,tmp); + if ((joystick0_fd = open(joystick0_dev, O_RDONLY)) < 0) + joystick0_fd = 0; + if ((joystick1_fd = open(joystick1_dev, O_RDONLY)) < 0) + joystick1_fd = 0; + if (!joystick0_fd && !joystick1_fd) /* No joysticks detected */ + return 0; + inited = true; + if (ioctl(joystick0_fd ? joystick0_fd : joystick1_fd, JSIOCGVERSION, &js_version) < 0) + return 0; + + /* Initialise joystick 0 */ + if (joystick0_fd) { + ioctl(joystick0_fd, JSIOCGNAME(sizeof(name0)), name0); + if (js_version & ~0xffff) { + struct js_event js; + + ioctl(joystick0_fd, JSIOCGAXES, &js0_axes); + ioctl(joystick0_fd, JSIOCGBUTTONS, &js0_buttons); + axis0 = PM_calloc((int)js0_axes, sizeof(short)); + buts0 = PM_malloc((int)js0_buttons); + /* Read the initial events */ + while(dataReady(joystick0_fd) + && read(joystick0_fd, &js, sizeof(struct js_event)) == sizeof(struct js_event) + && (js.type & JS_EVENT_INIT) + ) { + if (js.type & JS_EVENT_BUTTON) + buts0[js.number] = js.value; + else if (js.type & JS_EVENT_AXIS) + axis0[js.number] = scaleJoyAxis(js.value,js.number); + } + } + else { + js0_axes = 2; + js0_buttons = 2; + axis0 = PM_calloc((int)js0_axes, sizeof(short)); + buts0 = PM_malloc((int)js0_buttons); + } + } + + /* Initialise joystick 1 */ + if (joystick1_fd) { + ioctl(joystick1_fd, JSIOCGNAME(sizeof(name1)), name1); + if (js_version & ~0xffff) { + struct js_event js; + + ioctl(joystick1_fd, JSIOCGAXES, &js1_axes); + ioctl(joystick1_fd, JSIOCGBUTTONS, &js1_buttons); + axis1 = PM_calloc((int)js1_axes, sizeof(short)); + buts1 = PM_malloc((int)js1_buttons); + /* Read the initial events */ + while(dataReady(joystick1_fd) + && read(joystick1_fd, &js, sizeof(struct js_event))==sizeof(struct js_event) + && (js.type & JS_EVENT_INIT) + ) { + if (js.type & JS_EVENT_BUTTON) + buts1[js.number] = js.value; + else if (js.type & JS_EVENT_AXIS) + axis1[js.number] = scaleJoyAxis(js.value,js.number<<2); + } + } + else { + js1_axes = 2; + js1_buttons = 2; + axis1 = PM_calloc((int)js1_axes, sizeof(short)); + buts1 = PM_malloc((int)js1_buttons); + } + } + +#ifdef CHECKED + fprintf(stderr,"Using joystick driver version %d.%d.%d\n", + js_version >> 16, (js_version >> 8) & 0xff, js_version & 0xff); + if (joystick0_fd) + fprintf(stderr,"Joystick 1 (%s): %s\n", joystick0_dev, name0); + if (joystick1_fd) + fprintf(stderr,"Joystick 2 (%s): %s\n", joystick1_dev, name1); +#endif + mask = _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); + if (mask) { + for (i = 0; i < JOY_NUM_AXES; i++) + EVT.joyMax[i] = EVT.joyCenter[i]*2; + } + return mask; +} + +/**************************************************************************** +DESCRIPTION: +Polls the joystick for position and button information. + +HEADER: +event.h + +REMARKS: +This routine is used to poll analogue joysticks for button and position +information. It should be called once for each main loop of the user +application, just before processing all pending events via EVT_getNext. +All information polled from the joystick will be posted to the event +queue for later retrieval. + +Note: Most analogue joysticks will provide readings that change even + though the joystick has not moved. Hence if you call this routine + you will likely get an EVT_JOYMOVE event every time through your + event loop. + +SEE ALSO: +EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight, +EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_pollJoystick(void) +{ + event_t evt; + int i,axis[JOY_NUM_AXES],newButState,mask,moved,ps; + + if ((js_version & ~0xFFFF) == 0 && EVT.joyMask) { + /* Read joystick axes and post movement events if they have + * changed since the last time we polled. Until the events are + * actually flushed, we keep modifying the same joystick movement + * event, so you won't get multiple movement event + */ + mask = _EVT_readJoyAxis(EVT.joyMask,axis); + newButState = _EVT_readJoyButtons(); + moved = false; + for (i = 0; i < JOY_NUM_AXES; i++) { + if (mask & (EVT_JOY_AXIS_X1 << i)) + axis[i] = scaleJoyAxis(axis[i],i); + else + axis[i] = EVT.joyPrev[i]; + if (axis[i] != EVT.joyPrev[i]) + moved = true; + } + if (moved) { + memcpy(EVT.joyPrev,axis,sizeof(EVT.joyPrev)); + ps = _EVT_disableInt(); + if (EVT.oldJoyMove != -1) { + /* Modify the existing joystick movement event */ + EVT.evtq[EVT.oldJoyMove].message = newButState; + EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; + EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; + EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; + EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; + } + else if (EVT.count < EVENTQSIZE) { + /* Add a new joystick movement event */ + EVT.oldJoyMove = EVT.freeHead; + memset(&evt,0,sizeof(evt)); + evt.what = EVT_JOYMOVE; + evt.message = EVT.joyButState; + evt.where_x = EVT.joyPrev[0]; + evt.where_y = EVT.joyPrev[1]; + evt.relative_x = EVT.joyPrev[2]; + evt.relative_y = EVT.joyPrev[3]; + addEvent(&evt); + } + _EVT_restoreInt(ps); + } + + /* Read the joystick buttons, and post events to reflect the change + * in state for the joystick buttons. + */ + if (newButState != EVT.joyButState) { + if (EVT.count < EVENTQSIZE) { + /* Add a new joystick movement event */ + ps = _EVT_disableInt(); + memset(&evt,0,sizeof(evt)); + evt.what = EVT_JOYCLICK; + evt.message = newButState; + EVT.evtq[EVT.oldJoyMove].where_x = EVT.joyPrev[0]; + EVT.evtq[EVT.oldJoyMove].where_y = EVT.joyPrev[1]; + EVT.evtq[EVT.oldJoyMove].relative_x = EVT.joyPrev[2]; + EVT.evtq[EVT.oldJoyMove].relative_y = EVT.joyPrev[3]; + addEvent(&evt); + _EVT_restoreInt(ps); + } + EVT.joyButState = newButState; + } + } +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick upper left position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the upper left +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetUpperLeft(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMin); +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick lower right position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the lower right +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetLowerRight(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyMax); +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick center position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the center +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter +****************************************************************************/ +void EVTAPI EVT_joySetCenter(void) +{ + _EVT_readJoyAxis(EVT_JOY_AXIS_ALL,EVT.joyCenter); +} +#endif + +/**************************************************************************** +REMARKS: +Pumps all messages in the message queue from Linux into our event queue. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + event_t evt; + int i,numkeys, c; + ibool release; + static struct kbentry ke; + static char buf[KBDREADBUFFERSIZE]; + static ushort repeatKey[128] = {0}; + + /* Poll keyboard events */ + while (dataReady(_PM_console_fd) && (numkeys = read(_PM_console_fd, buf, KBDREADBUFFERSIZE)) > 0) { + for (i = 0; i < numkeys; i++) { + c = buf[i]; + release = c & 0x80; + c &= 0x7F; + + /* TODO: This is wrong! We need this to be the time stamp at */ + /* ** interrupt ** time!! One solution would be to */ + /* put the keyboard and mouse polling loops into */ + /* a separate thread that can block on I/O to the */ + /* necessay file descriptor. */ + evt.when = _EVT_getTicks(); + + if (release) { + /* Key released */ + evt.what = EVT_KEYUP; + switch (c) { + case KB_leftShift: + _PM_modifiers &= ~EVT_LEFTSHIFT; + break; + case KB_rightShift: + _PM_modifiers &= ~EVT_RIGHTSHIFT; + break; + case 29: + _PM_modifiers &= ~(EVT_LEFTCTRL|EVT_CTRLSTATE); + break; + case 97: /* Control */ + _PM_modifiers &= ~EVT_CTRLSTATE; + break; + case 56: + _PM_modifiers &= ~(EVT_LEFTALT|EVT_ALTSTATE); + break; + case 100: + _PM_modifiers &= ~EVT_ALTSTATE; + break; + default: + } + evt.modifiers = _PM_modifiers; + evt.message = keyUpMsg[c]; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + keyUpMsg[c] = 0; + repeatKey[c] = 0; + } + else { + /* Key pressed */ + evt.what = EVT_KEYDOWN; + switch (c) { + case KB_leftShift: + _PM_modifiers |= EVT_LEFTSHIFT; + break; + case KB_rightShift: + _PM_modifiers |= EVT_RIGHTSHIFT; + break; + case 29: + _PM_modifiers |= EVT_LEFTCTRL|EVT_CTRLSTATE; + break; + case 97: /* Control */ + _PM_modifiers |= EVT_CTRLSTATE; + break; + case 56: + _PM_modifiers |= EVT_LEFTALT|EVT_ALTSTATE; + break; + case 100: + _PM_modifiers |= EVT_ALTSTATE; + break; + case KB_capsLock: /* Caps Lock */ + _PM_leds ^= LED_CAP; + ioctl(_PM_console_fd, KDSETLED, _PM_leds); + break; + case KB_numLock: /* Num Lock */ + _PM_leds ^= LED_NUM; + ioctl(_PM_console_fd, KDSETLED, _PM_leds); + break; + case KB_scrollLock: /* Scroll Lock */ + _PM_leds ^= LED_SCR; + ioctl(_PM_console_fd, KDSETLED, _PM_leds); + break; + default: + } + evt.modifiers = _PM_modifiers; + if (keyUpMsg[c]) { + evt.what = EVT_KEYREPEAT; + evt.message = keyUpMsg[c] | (repeatKey[c]++ << 16); + } + else { + int asc; + + evt.message = getKeyMapping(keymaps, NB_KEYMAPS, c) << 8; + ke.kb_index = c; + ke.kb_table = 0; + if ((_PM_modifiers & EVT_SHIFTKEY) || (_PM_leds & LED_CAP)) + ke.kb_table |= K_SHIFTTAB; + if (_PM_modifiers & (EVT_LEFTALT | EVT_ALTSTATE)) + ke.kb_table |= K_ALTTAB; + if (ioctl(_PM_console_fd, KDGKBENT, (unsigned long)&ke)<0) + perror("ioctl(KDGKBENT)"); + if ((_PM_leds & LED_NUM) && (getKeyMapping(keypad, NB_KEYPAD, c)!=c)) { + asc = getKeyMapping(keypad, NB_KEYPAD, c); + } + else { + switch (c) { + case 14: + asc = ASCII_backspace; + break; + case 15: + asc = ASCII_tab; + break; + case 28: + case 96: + asc = ASCII_enter; + break; + case 1: + asc = ASCII_esc; + default: + asc = ke.kb_value & 0xFF; + if (asc < 0x1B) + asc = 0; + break; + } + } + if ((_PM_modifiers & (EVT_CTRLSTATE|EVT_LEFTCTRL)) && isalpha(asc)) + evt.message |= toupper(asc) - 'A' + 1; + else + evt.message |= asc; + keyUpMsg[c] = evt.message; + repeatKey[c]++; + } + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + } + } + + /* Poll mouse events */ + if (_EVT_mouse_fd) { + int dx, dy, buts; + static int oldbuts; + + while (dataReady(_EVT_mouse_fd)) { + if (readMouseData(&buts, &dx, &dy)) { + EVT.mx += dx; + EVT.my += dy; + if (EVT.mx < 0) EVT.mx = 0; + if (EVT.my < 0) EVT.my = 0; + if (EVT.mx > range_x) EVT.mx = range_x; + if (EVT.my > range_y) EVT.my = range_y; + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = dx; + evt.relative_y = dy; + + /* TODO: This is wrong! We need this to be the time stamp at */ + /* ** interrupt ** time!! One solution would be to */ + /* put the keyboard and mouse polling loops into */ + /* a separate thread that can block on I/O to the */ + /* necessay file descriptor. */ + evt.when = _EVT_getTicks(); + evt.modifiers = _PM_modifiers; + if (buts & 4) + evt.modifiers |= EVT_LEFTBUT; + if (buts & 1) + evt.modifiers |= EVT_RIGHTBUT; + if (buts & 2) + evt.modifiers |= EVT_MIDDLEBUT; + + /* Left click events */ + if ((buts&4) != (oldbuts&4)) { + if (buts&4) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_LEFTBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Right click events */ + if ((buts&1) != (oldbuts&1)) { + if (buts&1) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_RIGHTBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Middle click events */ + if ((buts&2) != (oldbuts&2)) { + if (buts&2) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_MIDDLEBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Mouse movement event */ + if (dx || dy) { + evt.what = EVT_MOUSEMOVE; + evt.message = 0; + if (EVT.oldMove != -1) { + /* Modify existing movement event */ + EVT.evtq[EVT.oldMove].where_x = evt.where_x; + EVT.evtq[EVT.oldMove].where_y = evt.where_y; + } + else { + /* Save id of this movement event */ + EVT.oldMove = EVT.freeHead; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + } + oldbuts = buts; + } + } + } + +#ifdef USE_OS_JOYSTICK + /* Poll joystick events using the 1.x joystick driver API in the 2.2 kernels */ + if (js_version & ~0xffff) { + static struct js_event js; + + /* Read joystick axis 0 */ + evt.when = 0; + evt.modifiers = _PM_modifiers; + if (joystick0_fd && dataReady(joystick0_fd) && + read(joystick0_fd, &js, sizeof(js)) == sizeof(js)) { + if (js.type & JS_EVENT_BUTTON) { + if (js.number < 2) { /* Only 2 buttons for now :( */ + buts0[js.number] = js.value; + evt.what = EVT_JOYCLICK; + makeJoyEvent(&evt); + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + } + else if (js.type & JS_EVENT_AXIS) { + axis0[js.number] = scaleJoyAxis(js.value,js.number); + evt.what = EVT_JOYMOVE; + if (EVT.oldJoyMove != -1) { + makeJoyEvent(&EVT.evtq[EVT.oldJoyMove]); + } + else if (EVT.count < EVENTQSIZE) { + EVT.oldJoyMove = EVT.freeHead; + makeJoyEvent(&evt); + addEvent(&evt); + } + } + } + + /* Read joystick axis 1 */ + if (joystick1_fd && dataReady(joystick1_fd) && + read(joystick1_fd, &js, sizeof(js))==sizeof(js)) { + if (js.type & JS_EVENT_BUTTON) { + if (js.number < 2) { /* Only 2 buttons for now :( */ + buts1[js.number] = js.value; + evt.what = EVT_JOYCLICK; + makeJoyEvent(&evt); + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + } + else if (js.type & JS_EVENT_AXIS) { + axis1[js.number] = scaleJoyAxis(js.value,js.number<<2); + evt.what = EVT_JOYMOVE; + if (EVT.oldJoyMove != -1) { + makeJoyEvent(&EVT.evtq[EVT.oldJoyMove]); + } + else if (EVT.count < EVENTQSIZE) { + EVT.oldJoyMove = EVT.freeHead; + makeJoyEvent(&evt); + addEvent(&evt); + } + } + } + } +#endif +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift _PM_modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Set the speed of the serial port +****************************************************************************/ +static int setspeed( + int fd, + int old, + int new, + unsigned short flags) +{ + struct termios tty; + char *c; + + tcgetattr(fd, &tty); + tty.c_iflag = IGNBRK | IGNPAR; + tty.c_oflag = 0; + tty.c_lflag = 0; + tty.c_line = 0; + tty.c_cc[VTIME] = 0; + tty.c_cc[VMIN] = 1; + switch (old) { + case 9600: tty.c_cflag = flags | B9600; break; + case 4800: tty.c_cflag = flags | B4800; break; + case 2400: tty.c_cflag = flags | B2400; break; + case 1200: + default: tty.c_cflag = flags | B1200; break; + } + tcsetattr(fd, TCSAFLUSH, &tty); + switch (new) { + case 9600: c = "*q"; tty.c_cflag = flags | B9600; break; + case 4800: c = "*p"; tty.c_cflag = flags | B4800; break; + case 2400: c = "*o"; tty.c_cflag = flags | B2400; break; + case 1200: + default: c = "*n"; tty.c_cflag = flags | B1200; break; + } + write(fd, c, 2); + usleep(100000); + tcsetattr(fd, TCSAFLUSH, &tty); + return 0; +} + +/**************************************************************************** +REMARKS: +Generic mouse driver init code +****************************************************************************/ +static void _EVT_mouse_init(void) +{ + int i; + + /* Change from any available speed to the chosen one */ + for (i = 9600; i >= 1200; i /= 2) + setspeed(_EVT_mouse_fd, i, opt_baud, mouse_infos[mouse_driver].flags); +} + +/**************************************************************************** +REMARKS: +Logitech mouse driver init code +****************************************************************************/ +static void _EVT_logitech_init(void) +{ + int i; + struct stat buf; + int busmouse; + + /* is this a serial- or a bus- mouse? */ + if (fstat(_EVT_mouse_fd,&buf) == -1) + perror("fstat"); + i = MAJOR(buf.st_rdev); + if (stat("/dev/ttyS0",&buf) == -1) + perror("stat"); + busmouse=(i != MAJOR(buf.st_rdev)); + + /* Fix the howmany field, so that serial mice have 1, while busmice have 3 */ + mouse_infos[mouse_driver].read = busmouse ? 3 : 1; + + /* Change from any available speed to the chosen one */ + for (i = 9600; i >= 1200; i /= 2) + setspeed(_EVT_mouse_fd, i, opt_baud, mouse_infos[mouse_driver].flags); + + /* This stuff is peculiar of logitech mice, also for the serial ones */ + write(_EVT_mouse_fd, "S", 1); + setspeed(_EVT_mouse_fd, opt_baud, opt_baud,CS8 |PARENB |PARODD |CREAD |CLOCAL |HUPCL); + + /* Configure the sample rate */ + for (i = 0; opt_sample <= sampletab[i].sample; i++) + ; + write(_EVT_mouse_fd,sampletab[i].code,1); +} + +/**************************************************************************** +REMARKS: +Microsoft Intellimouse init code +****************************************************************************/ +static void _EVT_pnpmouse_init(void) +{ + struct termios tty; + + tcgetattr(_EVT_mouse_fd, &tty); + tty.c_iflag = IGNBRK | IGNPAR; + tty.c_oflag = 0; + tty.c_lflag = 0; + tty.c_line = 0; + tty.c_cc[VTIME] = 0; + tty.c_cc[VMIN] = 1; + tty.c_cflag = mouse_infos[mouse_driver].flags | B1200; + tcsetattr(_EVT_mouse_fd, TCSAFLUSH, &tty); /* set parameters */ +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + int i; + char *tmp; + + /* Initialise the event queue */ + EVT.mouseMove = mouseMove; + initEventQueue(); + for (i = 0; i < 256; i++) + keyUpMsg[i] = 0; + + /* Keyboard initialization */ + if (_PM_console_fd == -1) + PM_fatalError("You must first call PM_openConsole to use the EVT functions!"); + _PM_keyboard_rawmode(); + fcntl(_PM_console_fd,F_SETFL,fcntl(_PM_console_fd,F_GETFL) | O_NONBLOCK); + + /* Mouse initialization */ + if ((tmp = getenv(ENV_MOUSEDRV)) != NULL) { + for (i = 0; i < NB_MICE; i++) { + if (!strcasecmp(tmp, mouse_infos[i].name)) { + mouse_driver = i; + break; + } + } + if (i == NB_MICE) { + fprintf(stderr,"Unknown mouse driver: %s\n", tmp); + mouse_driver = EVT_noMouse; + _EVT_mouse_fd = 0; + } + } + if (mouse_driver != EVT_noMouse) { + if (mouse_driver == EVT_gpm) + strcpy(mouse_dev,"/dev/gpmdata"); + if ((tmp = getenv(ENV_MOUSEDEV)) != NULL) + strcpy(mouse_dev,tmp); +#ifdef CHECKED + fprintf(stderr,"Using the %s MGL mouse driver on %s.\n", mouse_infos[mouse_driver].name, mouse_dev); +#endif + if ((_EVT_mouse_fd = open(mouse_dev, O_RDWR)) < 0) { + perror("open"); + fprintf(stderr, "Unable to open mouse device %s, dropping mouse support.\n", mouse_dev); + sleep(1); + mouse_driver = EVT_noMouse; + _EVT_mouse_fd = 0; + } + else { + char c; + + /* Init and flush the mouse pending input queue */ + if (mouse_infos[mouse_driver].init) + mouse_infos[mouse_driver].init(); + while(dataReady(_EVT_mouse_fd) && read(_EVT_mouse_fd, &c, 1) == 1) + ; + } + } +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + range_x = xRes; + range_y = yRes; +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +#define _EVT_setMousePos(x,y) + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for Linux */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for Linux */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + _PM_restore_kb_mode(); + if (_EVT_mouse_fd) { + close(_EVT_mouse_fd); + _EVT_mouse_fd = 0; + } +#ifdef USE_OS_JOYSTICK + if (joystick0_fd) { + close(joystick0_fd); + free(axis0); + free(buts0); + joystick0_fd = 0; + } + if (joystick1_fd) { + close(joystick1_fd); + free(axis1); + free(buts1); + joystick1_fd = 0; + } +#endif +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga b/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga new file mode 100644 index 000000000..c0358a0f8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/event.svga @@ -0,0 +1,1058 @@ +/**************************************************************************** +* +* The SuperVGA Kit - UniVBE Software Development Kit +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: IBM PC (MS DOS) +* +* Description: Routines to provide a Linux event queue, which automatically +* handles keyboard and mouse events for the Linux compatability +* libraries. Based on the event handling code in the MGL. +* +****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pm.h" +#include "vesavbe.h" +#include "wdirect.h" + +/*--------------------------- Global variables ----------------------------*/ + +#define EVENTQSIZE 100 /* Number of events in event queue */ + +static int head = -1; /* Head of event queue */ +static int tail = -1; /* Tail of event queue */ +static int freeHead = -1; /* Head of free list */ +static int count = 0; /* No. of items currently in queue */ +static WD_event evtq[EVENTQSIZE]; /* The queue structure itself */ +static int oldMove = -1; /* Previous movement event */ +static int oldKey = -1; /* Previous key repeat event */ +static int mx,my; /* Current mouse position */ +static int xRes,yRes; /* Screen resolution coordinates */ +static void *stateBuf; /* Pointer to console state buffer */ +static int conn; /* GPM file descriptor for mouse handling */ +static int tty_fd; /* File descriptor for /dev/console */ +extern int tty_vc; /* Virtual console ID, from the PM/Pro library */ +static ibool key_down[128]; /* State of all keyboard keys */ +static struct termios old_conf; /* Saved terminal configuration */ +static int oldkbmode; /* and previous keyboard mode */ +struct vt_mode oldvtmode; /* Old virtual terminal mode */ +static int old_flags; /* Old flags for fcntl */ +static ulong key_modifiers; /* Keyboard modifiers */ +static int forbid_vt_release=0;/* Flag to forbid release of VT */ +static int forbid_vt_acquire=0;/* Flag to forbid cature of VT */ +static int oldmode; /* Old SVGA mode saved for VT switch*/ +static int initmode; /* Initial text mode */ +static ibool installed = false; /* True if we are installed */ +static void (_ASMAPI *moveCursor)(int x,int y) = NULL; +static int (_ASMAPI *suspendAppCallback)(int flags) = NULL; + +#if 0 +/* Keyboard Translation table from scancodes to ASCII */ + +static uchar keyTable[128] = +"\0\0331234567890-=\010" +"\011qwertyuiop[]\015" +"\0asdfghjkl;'`\0\\" +"zxcvbnm,./\0*\0 \0" +"\0\0\0\0\0\0\0\0\0\0\0\0" /* Function keys */ +"789-456+1230.\0\0\0\0\0" /* Keypad keys */ +"\0\0\0\0\0\0\0\015\0/"; + +static uchar keyTableShifted[128] = +"\0\033!@#$%^&*()_+\010" +"\011QWERTYUIOP{}\015" +"\0ASDFGHJKL:\"~\0|" +"ZXCVBNM<>?\0*\0 \0" +"\0\0\0\0\0\0\0\0\0\0\0\0" /* Function keys */ +"789-456+1230.\0\0\0\0\0" /* Keypad keys */ +"\0\0\0\0\0\0\0\015\0/"; +#endif + +/* Macros to keep track of the CAPS and NUM lock states */ + +#define EVT_CAPSSTATE 0x0100 +#define EVT_NUMSTATE 0x0200 + +/* Helper macros for dealing with timers */ + +#define TICKS_TO_USEC(t) ((t)*65536.0/1.193180) +#define USEC_TO_TICKS(u) ((u)*1.193180/65536.0) + +/* Number of keycodes to read at a time from the console */ + +#define KBDREADBUFFERSIZE 32 + +/*---------------------------- Implementation -----------------------------*/ + +/**************************************************************************** +REMARKS: +Returns the current time stamp in units of 18.2 ticks per second. +****************************************************************************/ +static ulong getTimeStamp(void) +{ + return (ulong)(clock() / (CLOCKS_PER_SEC / 18.2)); +} + +/**************************************************************************** +PARAMETERS: +evt - Event to place onto event queue + +REMARKS: +Adds an event to the event queue by tacking it onto the tail of the event +queue. This routine assumes that at least one spot is available on the +freeList for the event to be inserted. +****************************************************************************/ +static void addEvent( + WD_event *evt) +{ + int evtID; + + /* Get spot to place the event from the free list */ + evtID = freeHead; + freeHead = evtq[freeHead].next; + + /* Add to the tail of the event queue */ + evt->next = -1; + evt->prev = tail; + if (tail != -1) + evtq[tail].next = evtID; + else + head = evtID; + tail = evtID; + evtq[evtID] = *evt; + count++; +} + +/**************************************************************************** +PARAMETERS: +what - Event code +message - Event message +modifiers - keyboard modifiers +x - Mouse X position at time of event +y - Mouse Y position at time of event +but_stat - Mouse button status at time of event + +REMARKS: +Adds a new mouse event to the event queue. This routine is called from +within the mouse interrupt subroutine, so it must be efficient. +****************************************************************************/ +static void addMouseEvent( + uint what, + uint message, + int x, + int y, + uint but_stat) +{ + WD_event evt; + + if (count < EVENTQSIZE) { + evt.what = what; + evt.when = getTimeStamp(); + evt.message = message; + evt.modifiers = but_stat | key_modifiers; + evt.where_x = x; + evt.where_y = y; + fprintf(stderr, "(%d,%d), buttons %ld\n", x,y, evt.modifiers); + addEvent(&evt); /* Add to tail of event queue */ + } +} + +/**************************************************************************** +PARAMETERS: +scancode - Raw keyboard scan code +modifiers - Keyboard modifiers flags + +REMARKS: +Converts the raw scan code into the appropriate ASCII code using the scan +code and the keyboard modifier flags. +****************************************************************************/ +static ulong getKeyMessage( + uint scancode, + ulong modifiers) +{ + ushort code = scancode << 8; + ushort ascii; + struct kbentry ke; + + ke.kb_index = scancode; + + /* Find the basic ASCII code for the scan code */ + if (modifiers & EVT_CAPSSTATE) { + if (modifiers & EVT_SHIFTKEY) + ke.kb_table = K_NORMTAB; + // ascii = tolower(keyTableShifted[scancode]); + else + ke.kb_table = K_SHIFTTAB; + // ascii = toupper(keyTable[scancode]); + } + else { + if (modifiers & EVT_SHIFTKEY) + ke.kb_table = K_SHIFTTAB; + // ascii = keyTableShifted[scancode]; + else + ke.kb_table = K_NORMTAB; + // ascii = keyTable[scancode]; + } + if(modifiers & EVT_ALTSTATE) + ke.kb_table |= K_ALTTAB; + + if (ioctl(tty_fd, KDGKBENT, (unsigned long)&ke)) { + fprintf(stderr, "KDGKBENT at index %d in table %d: ", + scancode, ke.kb_table); + return 0; + } + ascii = ke.kb_value; + + /* Add ASCII code if key is not alt'ed or ctrl'ed */ + if (!(modifiers & (EVT_ALTSTATE | EVT_CTRLSTATE))) + code |= ascii; + + return code; +} + +/**************************************************************************** +PARAMETERS: +what - Event code +scancode - Raw scancode of keyboard event to add + +REMARKS: +Adds a new keyboard event to the event queue. We only take KEYUP and +KEYDOWN event codes, however if a key is already down we convert the KEYDOWN +to a KEYREPEAT. +****************************************************************************/ +static void addKeyEvent( + uint what, + uint scancode) +{ + WD_event evt; + + if (count < EVENTQSIZE) { + evt.what = what; + evt.when = getTimeStamp(); + evt.message = getKeyMessage(scancode,key_modifiers) | 0x10000UL; + evt.where_x = evt.where_y = 0; + evt.modifiers = key_modifiers; + if (evt.what == EVT_KEYUP) + key_down[scancode] = false; + else if (evt.what == EVT_KEYDOWN) { + if (key_down[scancode]) { + if (oldKey != -1) { + evtq[oldKey].message += 0x10000UL; + } + else { + evt.what = EVT_KEYREPEAT; + oldKey = freeHead; + addEvent(&evt); + oldMove = -1; + } + return; + } + key_down[scancode] = true; + } + + addEvent(&evt); + oldMove = -1; + } +} + +/**************************************************************************** +PARAMETERS: +sig - Signal being sent to this signal handler + +REMARKS: +Signal handler for the timer. This routine takes care of periodically +posting timer events to the event queue. +****************************************************************************/ +void timerHandler( + int sig) +{ + WD_event evt; + + if (sig == SIGALRM) { + if (count < EVENTQSIZE) { + evt.when = getTimeStamp(); + evt.what = EVT_TIMERTICK; + evt.message = 0; + evt.where_x = evt.where_y = 0; + evt.modifiers = 0; + addEvent(&evt); + oldMove = -1; + oldKey = -1; + } + signal(SIGALRM, timerHandler); + } +} + +/**************************************************************************** +REMARKS: +Restore the terminal to normal operation on exit +****************************************************************************/ +static void restore_term(void) +{ + RMREGS regs; + + if (installed) { + /* Restore text mode and the state of the console */ + regs.x.ax = 0x3; + PM_int86(0x10,®s,®s); + PM_restoreConsoleState(stateBuf,tty_fd); + + /* Restore console to normal operation */ + ioctl(tty_fd, VT_SETMODE, &oldvtmode); + ioctl(tty_fd, KDSKBMODE, oldkbmode); + tcsetattr(tty_fd, TCSAFLUSH, &old_conf); + fcntl(tty_fd,F_SETFL,old_flags &= ~O_NONBLOCK); + PM_closeConsole(tty_fd); + + /* Close the mouse driver */ + close(conn); + + /* Flag that we are not no longer installed */ + installed = false; + } +} + +/**************************************************************************** +REMARKS: +Signal handler to capture forced program termination conditions so that +we can clean up properly. +****************************************************************************/ +static void exitHandler(int sig) +{ + exit(-1); +} + +/**************************************************************************** +REMARKS: +Sleep until the virtual terminal is active +****************************************************************************/ +void wait_vt_active(void) +{ + while (ioctl(tty_fd, VT_WAITACTIVE, tty_vc) < 0) { + if ((errno != EAGAIN) && (errno != EINTR)) { + perror("ioctl(VT_WAITACTIVE)"); + exit(1); + } + usleep(150000); + } +} + +/**************************************************************************** +REMARKS: +Signal handler called when our virtual terminal has been released and we are +losing the active focus. +****************************************************************************/ +static void release_vt_signal(int n) +{ + forbid_vt_acquire = 1; + if (forbid_vt_release) { + forbid_vt_acquire = 0; + ioctl(tty_fd, VT_RELDISP, 0); + return; + } + + // TODO: Call the user supplied suspendAppCallback and restore text + // mode (saving the existing mode so we can restore it). + // + // Also if the suspendAppCallback is NULL then we have to + // ignore the switch request! + if(suspendAppCallback){ + oldmode = VBE_getVideoMode(); + suspendAppCallback(true); + VBE_setVideoMode(initmode); + } + + ioctl(tty_fd, VT_RELDISP, 1); + forbid_vt_acquire = 0; + wait_vt_active(); +} + +/**************************************************************************** +REMARKS: +Signal handler called when our virtual terminal has been re-aquired and we +are now regaiing the active focus. +****************************************************************************/ +static void acquire_vt_signal(int n) +{ + forbid_vt_release = 1; + if (forbid_vt_acquire) { + forbid_vt_release = 0; + return; + } + + // TODO: Restore the old display mode, call the user suspendAppCallback + // and and we will be back in graphics mode. + + if(suspendAppCallback){ + VBE_setVideoMode(oldmode); + suspendAppCallback(false); + } + + ioctl(tty_fd, VT_RELDISP, VT_ACKACQ); + forbid_vt_release = 0; +} + +/**************************************************************************** +REMARKS: +Function to set the action for a specific signal to call our signal handler. +****************************************************************************/ +static void set_sigaction(int sig,void (*handler)(int)) +{ + struct sigaction siga; + + siga.sa_handler = handler; + siga.sa_flags = SA_RESTART; + memset(&(siga.sa_mask), 0, sizeof(sigset_t)); + sigaction(sig, &siga, NULL); +} + +/**************************************************************************** +REMARKS: +Function to take over control of VT switching so that we can capture +virtual terminal release and aquire signals, allowing us to properly +support VT switching while in graphics modes. +****************************************************************************/ +static void take_vt_control(void) +{ + struct vt_mode vtmode; + + ioctl(tty_fd, VT_GETMODE, &vtmode); + oldvtmode = vtmode; + vtmode.mode = VT_PROCESS; + vtmode.relsig = SIGUSR1; + vtmode.acqsig = SIGUSR2; + set_sigaction(SIGUSR1, release_vt_signal); + set_sigaction(SIGUSR2, acquire_vt_signal); + ioctl(tty_fd, VT_SETMODE, &oldvtmode); +} + +/**************************************************************************** +REMARKS: +Set the shift keyboard LED's based on the current keyboard modifiers flags. +****************************************************************************/ +static void updateLEDStatus(void) +{ + int state = 0; + if (key_modifiers & EVT_CAPSSTATE) + state |= LED_CAP; + if (key_modifiers & EVT_NUMSTATE) + state |= LED_NUM; + ioctl(tty_fd,KDSETLED,state); +} + +/**************************************************************************** +PARAMETERS: +scancode - Raw scan code to handle + +REMARKS: +Handles the shift key modifiers and keeps track of the shift key states +so that we can return the correct ASCII codes for the keyboard. +****************************************************************************/ +static void toggleModifiers( + int scancode) +{ + static int caps_down = 0,num_down = 0; + + if (scancode & 0x80) { + /* Handle key-release function */ + scancode &= 0x7F; + if (scancode == 0x2A || scancode == 0x36) + key_modifiers &= ~EVT_SHIFTKEY; + else if (scancode == 0x1D || scancode == 0x61) + key_modifiers &= ~EVT_CTRLSTATE; + else if (scancode == 0x38 || scancode == 0x64) + key_modifiers &= ~EVT_ALTSTATE; + else if (scancode == 0x3A) + caps_down = false; + else if (scancode == 0x45) + num_down = false; + } + else { + /* Handle key-down function */ + scancode &= 0x7F; + if (scancode == 0x2A || scancode == 0x36) + key_modifiers |= EVT_SHIFTKEY; + else if (scancode == 0x1D || scancode == 0x61) + key_modifiers |= EVT_CTRLSTATE; + else if (scancode == 0x38 || scancode == 0x64) + key_modifiers |= EVT_ALTSTATE; + else if (scancode == 0x3A) { + if (!caps_down) { + key_modifiers ^= EVT_CAPSSTATE; + updateLEDStatus(); + } + caps_down = true; + } + else if (scancode == 0x45) { + if (!num_down) { + key_modifiers ^= EVT_NUMSTATE; + updateLEDStatus(); + } + num_down = true; + } + } +} + +/*************************************************************************** +REMARKS: +Returns the number of bits that have changed from 0 to 1 +(a negative value means the number of bits that have changed from 1 to 0) + **************************************************************************/ +static int compareBits(short a, short b) +{ + int ret = 0; + if( (a&1) != (b&1) ) ret += (b&1) ? 1 : -1; + if( (a&2) != (b&2) ) ret += (b&2) ? 1 : -1; + if( (a&4) != (b&4) ) ret += (b&4) ? 1 : -1; + return ret; +} + +/*************************************************************************** +REMARKS: +Turns off all keyboard state because we can't rely on them anymore as soon +as we switch VT's +***************************************************************************/ +static void keyboard_clearstate(void) +{ + key_modifiers = 0; + memset(key_down, 0, sizeof(key_down)); +} + +/**************************************************************************** +REMARKS: +Pumps all events from the console event queue into the WinDirect event queue. +****************************************************************************/ +static void pumpEvents(void) +{ + static uchar buf[KBDREADBUFFERSIZE]; + static char data[5]; + static int old_buts, old_mx, old_my; + static struct timeval t; + fd_set fds; + int numkeys,i; + int dx, dy, buts; + + /* Read all pending keypresses from keyboard buffer and process */ + while ((numkeys = read(tty_fd, buf, KBDREADBUFFERSIZE)) > 0) { + for (i = 0; i < numkeys; i++) { + toggleModifiers(buf[i]); + if (key_modifiers & EVT_ALTSTATE){ + int fkey = 0; + + // Do VT switching here for Alt+Fx keypresses + switch(buf[i] & 0x7F){ + case 59 ... 68: /* F1 to F10 */ + fkey = (buf[i] & 0x7F) - 58; + break; + case 87: /* F11 */ + case 88: /* F12 */ + fkey = (buf[i] & 0x7F) - 76; + break; + } + if(fkey){ + struct vt_stat vts; + ioctl(tty_fd, VT_GETSTATE, &vts); + + if(fkey != vts.v_active){ + keyboard_clearstate(); + ioctl(tty_fd, VT_ACTIVATE, fkey); + } + } + } + + if (buf[i] & 0x80) + addKeyEvent(EVT_KEYUP,buf[i] & 0x7F); + else + addKeyEvent(EVT_KEYDOWN,buf[i] & 0x7F); + } + + // TODO: If we want to handle VC switching we will need to do it + // in here so that we can switch away from the VC and then + // switch back to it later. Right now VC switching is disabled + // and in order to enable it we need to save/restore the state + // of the graphics screen (using the suspendAppCallback and + // saving/restoring the state of the current display mode). + + } + + /* Read all pending mouse events and process them */ + if(conn > 0){ + FD_ZERO(&fds); + FD_SET(conn, &fds); + t.tv_sec = t.tv_usec = 0L; + while (select(conn+1, &fds, NULL, NULL, &t) > 0) { + if(read(conn, data, 5) == 5){ + buts = (~data[0]) & 0x07; + dx = (char)(data[1]) + (char)(data[3]); + dy = -((char)(data[2]) + (char)(data[4])); + + mx += dx; my += dy; + + if (dx || dy) + addMouseEvent(EVT_MOUSEMOVE, 0, mx, my, buts); + + if (buts != old_buts){ + int c = compareBits(buts,old_buts); + if(c>0) + addMouseEvent(EVT_MOUSEDOWN, 0, mx, my, buts); + else if(c<0) + addMouseEvent(EVT_MOUSEUP, 0, mx, my, buts); + } + old_mx = mx; old_my = my; + old_buts = buts; + FD_SET(conn, &fds); + t.tv_sec = t.tv_usec = 0L; + } + } + } +} + +/*------------------------ Public interface routines ----------------------*/ + +/**************************************************************************** +PARAMETERS: +which - Which code for event to post +what - Event code for event to post +message - Event message +modifiers - Shift key/mouse button modifiers + +RETURNS: +True if the event was posted, false if queue is full. + +REMARKS: +Posts an event to the event queue. This routine can be used to post any type +of event into the queue. +****************************************************************************/ +ibool _WDAPI WD_postEvent( + ulong which, + uint what, + ulong message, + ulong modifiers) +{ + WD_event evt; + + if (count < EVENTQSIZE) { + /* Save information in event record */ + evt.which = which; + evt.what = what; + evt.when = getTimeStamp(); + evt.message = message; + evt.modifiers = modifiers; + addEvent(&evt); /* Add to tail of event queue */ + return true; + } + else + return false; +} + +/**************************************************************************** +PARAMETERS: +mask - Event mask to use + +REMARKS: +Flushes all the event specified in 'mask' from the event queue. +****************************************************************************/ +void _WDAPI WD_flushEvent( + uint mask) +{ + WD_event evt; + + do { /* Flush all events */ + WD_getEvent(&evt,mask); + } while (evt.what != EVT_NULLEVT); +} + +/**************************************************************************** +PARAMETERS: +evt - Place to store event +mask - Event mask to use + +REMARKS: +Halts program execution until a specified event occurs. The event is +returned. All pending events not in the specified mask will be ignored and +removed from the queue. +****************************************************************************/ +void _WDAPI WD_haltEvent( + WD_event *evt, + uint mask) +{ + do { /* Wait for an event */ + WD_getEvent(evt,EVT_EVERYEVT); + } while (!(evt->what & mask)); +} + +/**************************************************************************** +PARAMETERS: +evt - Place to store event +mask - Event mask to use + +RETURNS: +True if an event was pending. + +REMARKS: +Retrieves the next pending event defined in 'mask' from the event queue. +The event queue is adjusted to reflect the new state after the event has +been removed. +****************************************************************************/ +ibool _WDAPI WD_getEvent( + WD_event *evt, + uint mask) +{ + int evtID,next,prev; + + pumpEvents(); + if (moveCursor) + moveCursor(mx,my); /* Move the mouse cursor */ + evt->what = EVT_NULLEVT; /* Default to null event */ + + if (count) { + for (evtID = head; evtID != -1; evtID = evtq[evtID].next) { + if (evtq[evtID].what & mask) + break; /* Found an event */ + } + if (evtID == -1) + return false; /* Event was not found */ + next = evtq[evtID].next; + prev = evtq[evtID].prev; + if (prev != -1) + evtq[prev].next = next; + else + head = next; + if (next != -1) + evtq[next].prev = prev; + else + tail = prev; + *evt = evtq[evtID]; /* Return the event */ + evtq[evtID].next = freeHead; /* and return to free list */ + freeHead = evtID; + count--; + if (evt->what == EVT_MOUSEMOVE) + oldMove = -1; + if (evt->what == EVT_KEYREPEAT) + oldKey = -1; + } + return evt->what != EVT_NULLEVT; +} + +/**************************************************************************** +PARAMETERS: +evt - Place to store event +mask - Event mask to use + +RETURNS: +True if an event is pending. + +REMARKS: +Peeks at the next pending event defined in 'mask' in the event queue. The +event is not removed from the event queue. +****************************************************************************/ +ibool _WDAPI WD_peekEvent( + WD_event *evt, + uint mask) +{ + int evtID; + + pumpEvents(); + if (moveCursor) + moveCursor(mx,my); /* Move the mouse cursor */ + evt->what = EVT_NULLEVT; /* Default to null event */ + + if (count) { + for (evtID = head; evtID != -1; evtID = evtq[evtID].next) { + if (evtq[evtID].what & mask) + break; /* Found an event */ + } + if (evtID == -1) + return false; /* Event was not found */ + + *evt = evtq[evtID]; /* Return the event */ + } + return evt->what != EVT_NULLEVT; +} + +/**************************************************************************** +PARAMETERS: +hwndMain - Handle to main window +_xRes - X resolution of graphics mode to be used +_yRes - Y resolulion of graphics mode to be used + +RETURNS: +Handle to the fullscreen event window if (we return hwndMain on Linux) + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling +ISR to be called whenever any button's are pressed or released. We also +build the free list of events in the event queue. +****************************************************************************/ +WD_HWND _WDAPI WD_startFullScreen( + WD_HWND hwndMain, + int _xRes, + int _yRes) +{ + int i; + struct termios conf; + if (!installed) { + Gpm_Connect gpm; + + /* Build free list, and initialise global data structures */ + for (i = 0; i < EVENTQSIZE; i++) + evtq[i].next = i+1; + evtq[EVENTQSIZE-1].next = -1; /* Terminate list */ + count = freeHead = 0; + head = tail = -1; + oldMove = -1; + oldKey = -1; + xRes = _xRes; + yRes = _yRes; + + /* Open the console device and initialise it for raw mode */ + tty_fd = PM_openConsole(); + + /* Wait until virtual terminal is active and take over control */ + wait_vt_active(); + take_vt_control(); + + /* Initialise keyboard handling to raw mode */ + if (ioctl(tty_fd, KDGKBMODE, &oldkbmode)) { + printf("WD_startFullScreen: cannot get keyboard mode.\n"); + exit(-1); + } + old_flags = fcntl(tty_fd,F_GETFL); + fcntl(tty_fd,F_SETFL,old_flags |= O_NONBLOCK); + tcgetattr(tty_fd, &conf); + old_conf = conf; + conf.c_lflag &= ~(ICANON | ECHO | ECHOE | ECHOK | ECHONL | NOFLSH | ISIG); + conf.c_iflag &= ~(ISTRIP | IGNCR | ICRNL | INLCR | BRKINT | PARMRK | INPCK | IUCLC | IXON | IXOFF); + conf.c_iflag |= (IGNBRK | IGNPAR); + conf.c_cc[VMIN] = 1; + conf.c_cc[VTIME] = 0; + conf.c_cc[VSUSP] = 0; + tcsetattr(tty_fd, TCSAFLUSH, &conf); + ioctl(tty_fd, KDSKBMODE, K_MEDIUMRAW); + + /* Clear the keyboard state information */ + memset(key_down, 0, sizeof(key_down)); + ioctl(tty_fd,KDSETLED,key_modifiers = 0); + + /* Initialize the mouse connection + The user *MUST* run gpm with the option -R for this to work (or have a MouseSystems mouse) + */ + if(Gpm_Open(&gpm,0) > 0){ /* GPM available */ + if ((conn = open(GPM_NODE_FIFO,O_RDONLY|O_SYNC)) < 0) + fprintf(stderr,"WD_startFullScreen: Can't open mouse connection.\n"); + }else{ + fprintf(stderr,"Warning: when not using gpm -R, only MouseSystems mice are currently supported.\n"); + if ((conn = open("/dev/mouse",O_RDONLY|O_SYNC)) < 0) + fprintf(stderr,"WD_startFullScreen: Can't open /dev/mouse.\n"); + } + Gpm_Close(); + + /* TODO: Scale the mouse coordinates to the specific resolution */ + + /* Save the state of the console */ + if ((stateBuf = malloc(PM_getConsoleStateSize())) == NULL) { + printf("Out of memory!\n"); + exit(-1); + } + PM_saveConsoleState(stateBuf,tty_fd); + initmode = VBE_getVideoMode(); + + /* Initialize the signal handler for timer events */ + signal(SIGALRM, timerHandler); + + /* Capture termination signals so we can clean up properly */ + signal(SIGTERM, exitHandler); + signal(SIGINT, exitHandler); + signal(SIGQUIT, exitHandler); + atexit(restore_term); + + /* Signal that we are installed */ + installed = true; + } + return hwndMain; +} + +/**************************************************************************** +REMARKS: +Lets the library know when fullscreen graphics mode has been initialized so +that we can properly scale the mouse driver coordinates. +****************************************************************************/ +void _WDAPI WD_inFullScreen(void) +{ + /* Nothing to do in here */ +} + +/**************************************************************************** +REMARKS: +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void _WDAPI WD_restoreGDI(void) +{ + restore_term(); +} + +/**************************************************************************** +PARAMETERS: +ticks - Number of ticks between timer tick messages + +RETURNS: +Previous value for the timer tick event spacing. + +REMARKS: +The event module will automatically generate periodic timer tick events for +you, with 'ticks' between each event posting. If you set the value of +'ticks' to 0, the timer tick events are turned off. +****************************************************************************/ +int _WDAPI WD_setTimerTick( + int ticks) +{ + int old; + struct itimerval tim; + long ms = TICKS_TO_USEC(ticks); + + getitimer(ITIMER_REAL, &tim); + old = USEC_TO_TICKS(tim.it_value.tv_sec*1000000.0 + tim.it_value.tv_usec); + tim.it_interval.tv_sec = ms / 1000000; + tim.it_interval.tv_usec = ms % 1000000; + setitimer(ITIMER_REAL, &tim, NULL); + return old; +} + +/**************************************************************************** +PARAMETERS: +saveState - Address of suspend app callback to register + +REMARKS: +Registers a user application supplied suspend application callback so that +we can properly handle virtual terminal switching. +****************************************************************************/ +void _WDAPI WD_setSuspendAppCallback( + int (_ASMAPI *saveState)(int flags)) +{ + suspendAppCallback = saveState; +} + +/**************************************************************************** +PARAMETERS: +x - New X coordinate to move the mouse cursor to +y - New Y coordinate to move the mouse cursor to + +REMARKS: +Moves to mouse cursor to the specified coordinate. +****************************************************************************/ +void _WDAPI WD_setMousePos( + int x, + int y) +{ + mx = x; + my = y; +} + +/**************************************************************************** +PARAMETERS: +x - Place to store X coordinate of mouse cursor +y - Place to store Y coordinate of mouse cursor + +REMARKS: +Reads the current mouse cursor location int *screen* coordinates. +****************************************************************************/ +void _WDAPI WD_getMousePos( + int *x, + int *y) +{ + *x = mx; + *y = my; +} + +/**************************************************************************** +PARAMETERS: +mcb - Address of mouse callback function + +REMARKS: +Registers an application supplied mouse callback function that is called +whenever the mouse cursor moves. +****************************************************************************/ +void _WDAPI WD_setMouseCallback( + void (_ASMAPI *mcb)(int x,int y)) +{ + moveCursor = mcb; +} + +/**************************************************************************** +PARAMETERS: +xRes - New X resolution of graphics mode +yRes - New Y resolution of graphics mode + +REMARKS: +This is called to inform the event handling code that the screen resolution +has changed so that the mouse coordinates can be scaled appropriately. +****************************************************************************/ +void _WDAPI WD_changeResolution( + int xRes, + int yRes) +{ + // Gpm_FitValues(xRes, yRes); // ?? +} + +/**************************************************************************** +PARAMETERS: +scancode - Scan code to check if a key is down + +REMARKS: +Determines if a particular key is down based on the scan code for the key. +****************************************************************************/ +ibool _WDAPI WD_isKeyDown( + uchar scancode) +{ + return key_down[scancode]; +} + +/**************************************************************************** +REMARKS: +Determines if the application needs to run in safe mode. Not necessary for +anything but broken Windows 95 display drivers so we return false for +Linux. +****************************************************************************/ +int _WDAPI WD_isSafeMode(void) +{ + return false; +} + + diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h new file mode 100644 index 000000000..eadedfb13 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/oshdr.h @@ -0,0 +1,60 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: Include all the OS specific header files. +* +****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef USE_OS_JOYSTICK +#include +#endif +#include +#include +#include +#include +#include + +/* Internal global variables */ + +extern int _PM_console_fd,_PM_leds,_PM_modifiers; + +/* Internal function prototypes */ + +void _PM_restore_kb_mode(void); +void _PM_keyboard_rawmode(void); + +/* Linux needs the generic joystick scaling code */ + +#define NEED_SCALE_JOY_AXIS diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c b/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c new file mode 100644 index 000000000..c12a83500 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/pm.c @@ -0,0 +1,1809 @@ +;/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Portions copyright (C) Josh Vanderhoof +* +* Language: ANSI C +* Environment: Linux +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef ENABLE_MTRR +#include +#endif +#include +#ifdef __GLIBC__ +#include +#endif + +/*--------------------------- Global variables ----------------------------*/ + +#define REAL_MEM_BASE ((void *)0x10000) +#define REAL_MEM_SIZE 0x10000 +#define REAL_MEM_BLOCKS 0x100 +#define DEFAULT_VM86_FLAGS (IF_MASK | IOPL_MASK) +#define DEFAULT_STACK_SIZE 0x1000 +#define RETURN_TO_32_INT 255 + +/* Quick and dirty fix for vm86() syscall from lrmi 0.6 */ +static int +vm86(struct vm86_struct *vm) + { + int r; +#ifdef __PIC__ + asm volatile ( + "pushl %%ebx\n\t" + "movl %2, %%ebx\n\t" + "int $0x80\n\t" + "popl %%ebx" + : "=a" (r) + : "0" (113), "r" (vm)); +#else + asm volatile ( + "int $0x80" + : "=a" (r) + : "0" (113), "b" (vm)); +#endif + return r; + } + + +static struct { + int ready; + unsigned short ret_seg, ret_off; + unsigned short stack_seg, stack_off; + struct vm86_struct vm; + } context = {0}; + +struct mem_block { + unsigned int size : 20; + unsigned int free : 1; + }; + +static struct { + int ready; + int count; + struct mem_block blocks[REAL_MEM_BLOCKS]; + } mem_info = {0}; + +int _PM_console_fd = -1; +int _PM_leds = 0,_PM_modifiers = 0; +static ibool inited = false; +static int tty_vc = 0; +static int console_count = 0; +static int startup_vc; +static int fd_mem = 0; +static ibool in_raw_mode = false; +#ifdef ENABLE_MTRR +static int mtrr_fd; +#endif +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +#ifdef TRACE_IO +static ulong traceAddr; +#endif + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef TRACE_IO +extern void printk(char *msg,...); +#endif + +static inline void port_out(int value, int port) +{ +#ifdef TRACE_IO + printk("%04X:%04X: outb.%04X <- %02X\n", traceAddr >> 16, traceAddr & 0xFFFF, (ushort)port, (uchar)value); +#endif + asm volatile ("outb %0,%1" + ::"a" ((unsigned char) value), "d"((unsigned short) port)); +} + +static inline void port_outw(int value, int port) +{ +#ifdef TRACE_IO + printk("%04X:%04X: outw.%04X <- %04X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ushort)value); +#endif + asm volatile ("outw %0,%1" + ::"a" ((unsigned short) value), "d"((unsigned short) port)); +} + +static inline void port_outl(int value, int port) +{ +#ifdef TRACE_IO + printk("%04X:%04X: outl.%04X <- %08X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ulong)value); +#endif + asm volatile ("outl %0,%1" + ::"a" ((unsigned long) value), "d"((unsigned short) port)); +} + +static inline unsigned int port_in(int port) +{ + unsigned char value; + asm volatile ("inb %1,%0" + :"=a" ((unsigned char)value) + :"d"((unsigned short) port)); +#ifdef TRACE_IO + printk("%04X:%04X: inb.%04X -> %02X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (uchar)value); +#endif + return value; +} + +static inline unsigned int port_inw(int port) +{ + unsigned short value; + asm volatile ("inw %1,%0" + :"=a" ((unsigned short)value) + :"d"((unsigned short) port)); +#ifdef TRACE_IO + printk("%04X:%04X: inw.%04X -> %04X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ushort)value); +#endif + return value; +} + +static inline unsigned int port_inl(int port) +{ + unsigned long value; + asm volatile ("inl %1,%0" + :"=a" ((unsigned long)value) + :"d"((unsigned short) port)); +#ifdef TRACE_IO + printk("%04X:%04X: inl.%04X -> %08X\n", traceAddr >> 16,traceAddr & 0xFFFF, (ushort)port, (ulong)value); +#endif + return value; +} + +static int real_mem_init(void) +{ + void *m; + int fd_zero; + + if (mem_info.ready) + return 1; + + if ((fd_zero = open("/dev/zero", O_RDONLY)) == -1) + PM_fatalError("You must have root privledges to run this program!"); + if ((m = mmap((void *)REAL_MEM_BASE, REAL_MEM_SIZE, + PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_FIXED | MAP_PRIVATE, fd_zero, 0)) == (void *)-1) { + close(fd_zero); + PM_fatalError("You must have root privledges to run this program!"); + } + mem_info.ready = 1; + mem_info.count = 1; + mem_info.blocks[0].size = REAL_MEM_SIZE; + mem_info.blocks[0].free = 1; + return 1; +} + +static void insert_block(int i) +{ + memmove( + mem_info.blocks + i + 1, + mem_info.blocks + i, + (mem_info.count - i) * sizeof(struct mem_block)); + mem_info.count++; +} + +static void delete_block(int i) +{ + mem_info.count--; + + memmove( + mem_info.blocks + i, + mem_info.blocks + i + 1, + (mem_info.count - i) * sizeof(struct mem_block)); +} + +static inline void set_bit(unsigned int bit, void *array) +{ + unsigned char *a = array; + a[bit / 8] |= (1 << (bit % 8)); +} + +static inline unsigned int get_int_seg(int i) +{ + return *(unsigned short *)(i * 4 + 2); +} + +static inline unsigned int get_int_off(int i) +{ + return *(unsigned short *)(i * 4); +} + +static inline void pushw(unsigned short i) +{ + struct vm86_regs *r = &context.vm.regs; + r->esp -= 2; + *(unsigned short *)(((unsigned int)r->ss << 4) + r->esp) = i; +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return true; } + +void PMAPI PM_init(void) +{ + void *m; + uint r_seg,r_off; + + if (inited) + return; + + /* Map the Interrupt Vectors (0x0 - 0x400) + BIOS data (0x400 - 0x502) + * and the physical framebuffer and ROM images from (0xa0000 - 0x100000) + */ + real_mem_init(); + if (!fd_mem && (fd_mem = open("/dev/mem", O_RDWR)) == -1) { + PM_fatalError("You must have root privileges to run this program!"); + } + if ((m = mmap((void *)0, 0x502, + PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_FIXED | MAP_PRIVATE, fd_mem, 0)) == (void *)-1) { + PM_fatalError("You must have root privileges to run this program!"); + } + if ((m = mmap((void *)0xA0000, 0xC0000 - 0xA0000, + PROT_READ | PROT_WRITE, + MAP_FIXED | MAP_SHARED, fd_mem, 0xA0000)) == (void *)-1) { + PM_fatalError("You must have root privileges to run this program!"); + } + if ((m = mmap((void *)0xC0000, 0xD0000 - 0xC0000, + PROT_READ | PROT_WRITE | PROT_EXEC, + MAP_FIXED | MAP_PRIVATE, fd_mem, 0xC0000)) == (void *)-1) { + PM_fatalError("You must have root privileges to run this program!"); + } + if ((m = mmap((void *)0xD0000, 0x100000 - 0xD0000, + PROT_READ | PROT_WRITE, + MAP_FIXED | MAP_SHARED, fd_mem, 0xD0000)) == (void *)-1) { + PM_fatalError("You must have root privileges to run this program!"); + } + inited = 1; + + /* Allocate a stack */ + m = PM_allocRealSeg(DEFAULT_STACK_SIZE,&r_seg,&r_off); + context.stack_seg = r_seg; + context.stack_off = r_off+DEFAULT_STACK_SIZE; + + /* Allocate the return to 32 bit routine */ + m = PM_allocRealSeg(2,&r_seg,&r_off); + context.ret_seg = r_seg; + context.ret_off = r_off; + ((uchar*)m)[0] = 0xCD; /* int opcode */ + ((uchar*)m)[1] = RETURN_TO_32_INT; + memset(&context.vm, 0, sizeof(context.vm)); + + /* Enable kernel emulation of all ints except RETURN_TO_32_INT */ + memset(&context.vm.int_revectored, 0, sizeof(context.vm.int_revectored)); + set_bit(RETURN_TO_32_INT, &context.vm.int_revectored); + context.ready = 1; +#ifdef ENABLE_MTRR + mtrr_fd = open("/dev/cpu/mtrr", O_RDWR, 0); + if (mtrr_fd < 0) + mtrr_fd = open("/proc/mtrr", O_RDWR, 0); +#endif + /* Enable I/O permissions to directly access I/O ports. We break the + * allocation into two parts, one for the ports from 0-0x3FF and + * another for the remaining ports up to 0xFFFF. Standard Linux kernels + * only allow the first 0x400 ports to be enabled, so to enable all + * 65536 ports you need a patched kernel that will enable the full + * 8Kb I/O permissions bitmap. + */ +#ifndef TRACE_IO + ioperm(0x0,0x400,1); + ioperm(0x400,0x10000-0x400,1); +#endif + iopl(3); +} + +long PMAPI PM_getOSType(void) +{ return _OS_LINUX; } + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '/') { + s[pos] = '/'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + fprintf(stderr,"%s\n", msg); + fflush(stderr); + exit(1); +} + +static void ExitVBEBuf(void) +{ + if (VESABuf_ptr) + PM_freeRealSeg(VESABuf_ptr); + VESABuf_ptr = 0; +} + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) +{ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + atexit(ExitVBEBuf); + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +/* New raw console based getch and kbhit functions */ + +#define KB_CAPS LED_CAP /* 4 */ +#define KB_NUMLOCK LED_NUM /* 2 */ +#define KB_SCROLL LED_SCR /* 1 */ +#define KB_SHIFT 8 +#define KB_CONTROL 16 +#define KB_ALT 32 + +/* Structure used to save the keyboard mode to disk. We save it to disk + * so that we can properly restore the mode later if the program crashed. + */ + +typedef struct { + struct termios termios; + int kb_mode; + int leds; + int flags; + int startup_vc; + } keyboard_mode; + +/* Name of the file used to save keyboard mode information */ + +#define KBMODE_DAT "kbmode.dat" + +/**************************************************************************** +REMARKS: +Open the keyboard mode file on disk. +****************************************************************************/ +static FILE *open_kb_mode( + char *mode, + char *path) +{ + if (!PM_findBPD("graphics.bpd",path)) + return NULL; + PM_backslash(path); + strcat(path,KBMODE_DAT); + return fopen(path,mode); +} + +/**************************************************************************** +REMARKS: +Restore the keyboard to normal mode +****************************************************************************/ +void _PM_restore_kb_mode(void) +{ + FILE *kbmode; + keyboard_mode mode; + char path[PM_MAX_PATH]; + + if (_PM_console_fd != -1 && (kbmode = open_kb_mode("rb",path)) != NULL) { + if (fread(&mode,1,sizeof(mode),kbmode) == sizeof(mode)) { + if (mode.startup_vc > 0) + ioctl(_PM_console_fd, VT_ACTIVATE, mode.startup_vc); + ioctl(_PM_console_fd, KDSKBMODE, mode.kb_mode); + ioctl(_PM_console_fd, KDSETLED, mode.leds); + tcsetattr(_PM_console_fd, TCSAFLUSH, &mode.termios); + fcntl(_PM_console_fd,F_SETFL,mode.flags); + } + fclose(kbmode); + unlink(path); + in_raw_mode = false; + } +} + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _PM_abort( + int signo) +{ + char buf[80]; + + sprintf(buf,"Terminating on signal %d",signo); + _PM_restore_kb_mode(); + PM_fatalError(buf); +} + +/**************************************************************************** +REMARKS: +Put the keyboard into raw mode +****************************************************************************/ +void _PM_keyboard_rawmode(void) +{ + struct termios conf; + FILE *kbmode; + keyboard_mode mode; + char path[PM_MAX_PATH]; + int i; + static int sig_list[] = { + SIGHUP, + SIGINT, + SIGQUIT, + SIGILL, + SIGTRAP, + SIGABRT, + SIGIOT, + SIGBUS, + SIGFPE, + SIGKILL, + SIGSEGV, + SIGTERM, + }; + + if ((kbmode = open_kb_mode("rb",path)) == NULL) { + if ((kbmode = open_kb_mode("wb",path)) == NULL) + PM_fatalError("Unable to open kbmode.dat file for writing!"); + if (ioctl(_PM_console_fd, KDGKBMODE, &mode.kb_mode)) + perror("KDGKBMODE"); + ioctl(_PM_console_fd, KDGETLED, &mode.leds); + _PM_leds = mode.leds & 0xF; + _PM_modifiers = 0; + tcgetattr(_PM_console_fd, &mode.termios); + conf = mode.termios; + conf.c_lflag &= ~(ICANON | ECHO | ISIG); + conf.c_iflag &= ~(ISTRIP | IGNCR | ICRNL | INLCR | BRKINT | PARMRK | INPCK | IUCLC | IXON | IXOFF); + conf.c_iflag |= (IGNBRK | IGNPAR); + conf.c_cc[VMIN] = 1; + conf.c_cc[VTIME] = 0; + conf.c_cc[VSUSP] = 0; + tcsetattr(_PM_console_fd, TCSAFLUSH, &conf); + mode.flags = fcntl(_PM_console_fd,F_GETFL); + if (ioctl(_PM_console_fd, KDSKBMODE, K_MEDIUMRAW)) + perror("KDSKBMODE"); + atexit(_PM_restore_kb_mode); + for (i = 0; i < sizeof(sig_list)/sizeof(sig_list[0]); i++) + signal(sig_list[i], _PM_abort); + mode.startup_vc = startup_vc; + if (fwrite(&mode,1,sizeof(mode),kbmode) != sizeof(mode)) + PM_fatalError("Error writing kbmode.dat!"); + fclose(kbmode); + in_raw_mode = true; + } +} + +int PMAPI PM_kbhit(void) +{ + fd_set s; + struct timeval tv = { 0, 0 }; + + if (console_count == 0) + PM_fatalError("You *must* open a console before using PM_kbhit!"); + if (!in_raw_mode) + _PM_keyboard_rawmode(); + FD_ZERO(&s); + FD_SET(_PM_console_fd, &s); + return select(_PM_console_fd+1, &s, NULL, NULL, &tv) > 0; +} + +int PMAPI PM_getch(void) +{ + static uchar c; + int release; + static struct kbentry ke; + + if (console_count == 0) + PM_fatalError("You *must* open a console before using PM_getch!"); + if (!in_raw_mode) + _PM_keyboard_rawmode(); + while (read(_PM_console_fd, &c, 1) > 0) { + release = c & 0x80; + c &= 0x7F; + if (release) { + switch(c){ + case 42: case 54: /* Shift */ + _PM_modifiers &= ~KB_SHIFT; + break; + case 29: case 97: /* Control */ + _PM_modifiers &= ~KB_CONTROL; + break; + case 56: case 100: /* Alt / AltGr */ + _PM_modifiers &= ~KB_ALT; + break; + } + continue; + } + switch (c) { + case 42: case 54: /* Shift */ + _PM_modifiers |= KB_SHIFT; + break; + case 29: case 97: /* Control */ + _PM_modifiers |= KB_CONTROL; + break; + case 56: case 100: /* Alt / AltGr */ + _PM_modifiers |= KB_ALT; + break; + case 58: /* Caps Lock */ + _PM_modifiers ^= KB_CAPS; + ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7); + break; + case 69: /* Num Lock */ + _PM_modifiers ^= KB_NUMLOCK; + ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7); + break; + case 70: /* Scroll Lock */ + _PM_modifiers ^= KB_SCROLL; + ioctl(_PM_console_fd, KDSETLED, _PM_modifiers & 7); + break; + case 28: + return 0x1C; + default: + ke.kb_index = c; + ke.kb_table = 0; + if ((_PM_modifiers & KB_SHIFT) || (_PM_modifiers & KB_CAPS)) + ke.kb_table |= K_SHIFTTAB; + if (_PM_modifiers & KB_ALT) + ke.kb_table |= K_ALTTAB; + ioctl(_PM_console_fd, KDGKBENT, (ulong)&ke); + c = ke.kb_value & 0xFF; + return c; + } + } + return 0; +} + +/**************************************************************************** +REMARKS: +Sleep until the virtual terminal is active +****************************************************************************/ +static void wait_vt_active( + int _PM_console_fd) +{ + while (ioctl(_PM_console_fd, VT_WAITACTIVE, tty_vc) < 0) { + if ((errno != EAGAIN) && (errno != EINTR)) { + perror("ioctl(VT_WAITACTIVE)"); + exit(1); + } + usleep(150000); + } +} + +/**************************************************************************** +REMARKS: +Checks the owner of the specified virtual console. +****************************************************************************/ +static int check_owner( + int vc) +{ + struct stat sbuf; + char fname[30]; + + sprintf(fname, "/dev/tty%d", vc); + if ((stat(fname, &sbuf) >= 0) && (getuid() == sbuf.st_uid)) + return 1; + printf("You must be the owner of the current console to use this program.\n"); + return 0; +} + +/**************************************************************************** +REMARKS: +Checks if the console is currently in graphics mode, and if so we forcibly +restore it back to text mode again. This handles the case when a Nucleus or +MGL program crashes and leaves the console in graphics mode. Running the +textmode utility (or any other Nucleus/MGL program) via a telnet session +into the machine will restore it back to normal. +****************************************************************************/ +static void restore_text_console( + int console_id) +{ + if (ioctl(console_id, KDSETMODE, KD_TEXT) < 0) + LOGWARN("ioctl(KDSETMODE) failed"); + _PM_restore_kb_mode(); +} + +/**************************************************************************** +REMARKS: +Opens up the console device for output by finding an appropriate virutal +console that we can run on. +****************************************************************************/ +PM_HWND PMAPI PM_openConsole( + PM_HWND hwndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ + struct vt_mode vtm; + struct vt_stat vts; + struct stat sbuf; + char fname[30]; + + /* Check if we have already opened the console */ + if (console_count++) + return _PM_console_fd; + + /* Now, it would be great if we could use /dev/tty and see what it is + * connected to. Alas, we cannot find out reliably what VC /dev/tty is + * bound to. Thus we parse stdin through stderr for a reliable VC. + */ + startup_vc = 0; + for (_PM_console_fd = 0; _PM_console_fd < 3; _PM_console_fd++) { + if (fstat(_PM_console_fd, &sbuf) < 0) + continue; + if (ioctl(_PM_console_fd, VT_GETMODE, &vtm) < 0) + continue; + if ((sbuf.st_rdev & 0xFF00) != 0x400) + continue; + if (!(sbuf.st_rdev & 0xFF)) + continue; + tty_vc = sbuf.st_rdev & 0xFF; + restore_text_console(_PM_console_fd); + return _PM_console_fd; + } + if ((_PM_console_fd = open("/dev/console", O_RDWR)) < 0) { + printf("open_dev_console: can't open /dev/console \n"); + exit(1); + } + if (ioctl(_PM_console_fd, VT_OPENQRY, &tty_vc) < 0) + goto Error; + if (tty_vc <= 0) + goto Error; + sprintf(fname, "/dev/tty%d", tty_vc); + close(_PM_console_fd); + + /* Change our control terminal */ + setsid(); + + /* We must use RDWR to allow for output... */ + if (((_PM_console_fd = open(fname, O_RDWR)) >= 0) && + (ioctl(_PM_console_fd, VT_GETSTATE, &vts) >= 0)) { + if (!check_owner(vts.v_active)) + goto Error; + restore_text_console(_PM_console_fd); + + /* Success, redirect all stdios */ + fflush(stdin); + fflush(stdout); + fflush(stderr); + close(0); + close(1); + close(2); + dup(_PM_console_fd); + dup(_PM_console_fd); + dup(_PM_console_fd); + + /* clear screen and switch to it */ + fwrite("\e[H\e[J", 6, 1, stderr); + fflush(stderr); + if (tty_vc != vts.v_active) { + startup_vc = vts.v_active; + ioctl(_PM_console_fd, VT_ACTIVATE, tty_vc); + wait_vt_active(_PM_console_fd); + } + } + return _PM_console_fd; + +Error: + if (_PM_console_fd > 2) + close(_PM_console_fd); + console_count = 0; + PM_fatalError( + "Not running in a graphics capable console,\n" + "and unable to find one.\n"); + return -1; +} + +#define FONT_C 0x10000 /* 64KB for font data */ + +/**************************************************************************** +REMARKS: +Returns the size of the console state buffer. +****************************************************************************/ +int PMAPI PM_getConsoleStateSize(void) +{ + if (!inited) + PM_init(); + return PM_getVGAStateSize() + FONT_C*2; +} + +/**************************************************************************** +REMARKS: +Save the state of the Linux console. +****************************************************************************/ +void PMAPI PM_saveConsoleState(void *stateBuf,int console_id) +{ + uchar *regs = stateBuf; + + /* Save the current console font */ + if (ioctl(console_id,GIO_FONT,®s[PM_getVGAStateSize()]) < 0) + perror("ioctl(GIO_FONT)"); + + /* Inform the Linux console that we are going into graphics mode */ + if (ioctl(console_id, KDSETMODE, KD_GRAPHICS) < 0) + perror("ioctl(KDSETMODE)"); + + /* Save state of VGA registers */ + PM_saveVGAState(stateBuf); +} + +void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) +{ + /* TODO: Implement support for allowing console switching! */ +} + +/**************************************************************************** +REMARKS: +Restore the state of the Linux console. +****************************************************************************/ +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND console_id) +{ + const uchar *regs = stateBuf; + + /* Restore the state of the VGA compatible registers */ + PM_restoreVGAState(stateBuf); + + /* Inform the Linux console that we are back from graphics modes */ + if (ioctl(console_id, KDSETMODE, KD_TEXT) < 0) + LOGWARN("ioctl(KDSETMODE) failed"); + + /* Restore the old console font */ + if (ioctl(console_id,PIO_FONT,®s[PM_getVGAStateSize()]) < 0) + LOGWARN("ioctl(KDSETMODE) failed"); + + /* Coming back from graphics mode on Linux also restored the previous + * text mode console contents, so we need to clear the screen to get + * around this since the cursor does not get homed by our code. + */ + fflush(stdout); + fflush(stderr); + printf("\033[H\033[J"); + fflush(stdout); +} + +/**************************************************************************** +REMARKS: +Close the Linux console and put it back to normal. +****************************************************************************/ +void PMAPI PM_closeConsole(PM_HWND _PM_console_fd) +{ + /* Restore console to normal operation */ + if (--console_count == 0) { + /* Re-activate the original virtual console */ + if (startup_vc > 0) + ioctl(_PM_console_fd, VT_ACTIVATE, startup_vc); + + /* Close the console file descriptor */ + if (_PM_console_fd > 2) + close(_PM_console_fd); + _PM_console_fd = -1; + } +} + +void PM_setOSCursorLocation(int x,int y) +{ + /* Nothing to do in here */ +} + +/**************************************************************************** +REMARKS: +Set the screen width and height for the Linux console. +****************************************************************************/ +void PM_setOSScreenWidth(int width,int height) +{ + struct winsize ws; + struct vt_sizes vs; + + /* Resize the software terminal */ + ws.ws_col = width; + ws.ws_row = height; + ioctl(_PM_console_fd, TIOCSWINSZ, &ws); + + /* And the hardware */ + vs.v_rows = height; + vs.v_cols = width; + vs.v_scrollsize = 0; + ioctl(_PM_console_fd, VT_RESIZE, &vs); +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency) +{ + /* TODO: Implement this for Linux */ + return false; +} + +void PMAPI PM_setRealTimeClockFrequency(int frequency) +{ + /* TODO: Implement this for Linux */ +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* TODO: Implement this for Linux */ +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +char PMAPI PM_getBootDrive(void) +{ return '/'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return PM_getNucleusConfigPath(); } + +const char * PMAPI PM_getNucleusPath(void) +{ + char *env = getenv("NUCLEUS_PATH"); + return env ? env : "/usr/lib/nucleus"; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +const char * PMAPI PM_getMachineName(void) +{ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +void * PMAPI PM_getBIOSPointer(void) +{ + static uchar *zeroPtr = NULL; + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); + return (void*)(zeroPtr + 0x400); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + /* PM_init maps in the 0xA0000 framebuffer region 1:1 with our + * address mapping, so we can return the address here. + */ + if (!inited) + PM_init(); + return (void*)(0xA0000); +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + uchar *p; + ulong baseAddr,baseOfs; + + if (!inited) + PM_init(); + if (base >= 0xA0000 && base < 0x100000) + return (void*)base; + if (!fd_mem && (fd_mem = open("/dev/mem", O_RDWR)) == -1) + return NULL; + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to mmap. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + baseOfs = base & 4095; + baseAddr = base & ~4095; + limit = ((limit+baseOfs+1+4095) & ~4095)-1; + if ((p = mmap(0, limit+1, + PROT_READ | PROT_WRITE, MAP_SHARED, + fd_mem, baseAddr)) == (void *)-1) + return NULL; + return (void*)(p+baseOfs); +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + if ((ulong)ptr >= 0x100000) + munmap(ptr,limit+1); +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +ibool PMAPI PM_getPhysicalAddrRange(void *p,ulong length,ulong *physAddress) +{ + /* TODO: This function should find a range of physical addresses */ + /* for a linear address. */ + return false; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* TODO: Put the process to sleep for milliseconds */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +void * PMAPI PM_mallocShared(long size) +{ + return PM_malloc(size); +} + +void PMAPI PM_freeShared(void *ptr) +{ + PM_free(ptr); +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + /* PM_init maps in the 0xA0000-0x100000 region 1:1 with our + * address mapping, as well as all memory blocks in a 1:1 address + * mapping so we can simply return the physical address in here. + */ + if (!inited) + PM_init(); + return (void*)MK_PHYS(r_seg,r_off); +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + int i; + char *r = (char *)REAL_MEM_BASE; + + if (!inited) + PM_init(); + if (!mem_info.ready) + return NULL; + if (mem_info.count == REAL_MEM_BLOCKS) + return NULL; + size = (size + 15) & ~15; + for (i = 0; i < mem_info.count; i++) { + if (mem_info.blocks[i].free && size < mem_info.blocks[i].size) { + insert_block(i); + mem_info.blocks[i].size = size; + mem_info.blocks[i].free = 0; + mem_info.blocks[i + 1].size -= size; + *r_seg = (uint)(r) >> 4; + *r_off = (uint)(r) & 0xF; + return (void *)r; + } + r += mem_info.blocks[i].size; + } + return NULL; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + int i; + char *r = (char *)REAL_MEM_BASE; + + if (!mem_info.ready) + return; + i = 0; + while (mem != (void *)r) { + r += mem_info.blocks[i].size; + i++; + if (i == mem_info.count) + return; + } + mem_info.blocks[i].free = 1; + if (i + 1 < mem_info.count && mem_info.blocks[i + 1].free) { + mem_info.blocks[i].size += mem_info.blocks[i + 1].size; + delete_block(i + 1); + } + if (i - 1 >= 0 && mem_info.blocks[i - 1].free) { + mem_info.blocks[i - 1].size += mem_info.blocks[i].size; + delete_block(i); + } +} + +#define DIRECTION_FLAG (1 << 10) + +static void em_ins(int size) +{ + unsigned int edx, edi; + + edx = context.vm.regs.edx & 0xffff; + edi = context.vm.regs.edi & 0xffff; + edi += (unsigned int)context.vm.regs.ds << 4; + if (context.vm.regs.eflags & DIRECTION_FLAG) { + if (size == 4) + asm volatile ("std; insl; cld" + : "=D" (edi) : "d" (edx), "0" (edi)); + else if (size == 2) + asm volatile ("std; insw; cld" + : "=D" (edi) : "d" (edx), "0" (edi)); + else + asm volatile ("std; insb; cld" + : "=D" (edi) : "d" (edx), "0" (edi)); + } + else { + if (size == 4) + asm volatile ("cld; insl" + : "=D" (edi) : "d" (edx), "0" (edi)); + else if (size == 2) + asm volatile ("cld; insw" + : "=D" (edi) : "d" (edx), "0" (edi)); + else + asm volatile ("cld; insb" + : "=D" (edi) : "d" (edx), "0" (edi)); + } + edi -= (unsigned int)context.vm.regs.ds << 4; + context.vm.regs.edi &= 0xffff0000; + context.vm.regs.edi |= edi & 0xffff; +} + +static void em_rep_ins(int size) +{ + unsigned int ecx, edx, edi; + + ecx = context.vm.regs.ecx & 0xffff; + edx = context.vm.regs.edx & 0xffff; + edi = context.vm.regs.edi & 0xffff; + edi += (unsigned int)context.vm.regs.ds << 4; + if (context.vm.regs.eflags & DIRECTION_FLAG) { + if (size == 4) + asm volatile ("std; rep; insl; cld" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + else if (size == 2) + asm volatile ("std; rep; insw; cld" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + else + asm volatile ("std; rep; insb; cld" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + } + else { + if (size == 4) + asm volatile ("cld; rep; insl" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + else if (size == 2) + asm volatile ("cld; rep; insw" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + else + asm volatile ("cld; rep; insb" + : "=D" (edi), "=c" (ecx) + : "d" (edx), "0" (edi), "1" (ecx)); + } + + edi -= (unsigned int)context.vm.regs.ds << 4; + context.vm.regs.edi &= 0xffff0000; + context.vm.regs.edi |= edi & 0xffff; + context.vm.regs.ecx &= 0xffff0000; + context.vm.regs.ecx |= ecx & 0xffff; +} + +static void em_outs(int size) +{ + unsigned int edx, esi; + + edx = context.vm.regs.edx & 0xffff; + esi = context.vm.regs.esi & 0xffff; + esi += (unsigned int)context.vm.regs.ds << 4; + if (context.vm.regs.eflags & DIRECTION_FLAG) { + if (size == 4) + asm volatile ("std; outsl; cld" + : "=S" (esi) : "d" (edx), "0" (esi)); + else if (size == 2) + asm volatile ("std; outsw; cld" + : "=S" (esi) : "d" (edx), "0" (esi)); + else + asm volatile ("std; outsb; cld" + : "=S" (esi) : "d" (edx), "0" (esi)); + } + else { + if (size == 4) + asm volatile ("cld; outsl" + : "=S" (esi) : "d" (edx), "0" (esi)); + else if (size == 2) + asm volatile ("cld; outsw" + : "=S" (esi) : "d" (edx), "0" (esi)); + else + asm volatile ("cld; outsb" + : "=S" (esi) : "d" (edx), "0" (esi)); + } + + esi -= (unsigned int)context.vm.regs.ds << 4; + context.vm.regs.esi &= 0xffff0000; + context.vm.regs.esi |= esi & 0xffff; +} + +static void em_rep_outs(int size) +{ + unsigned int ecx, edx, esi; + + ecx = context.vm.regs.ecx & 0xffff; + edx = context.vm.regs.edx & 0xffff; + esi = context.vm.regs.esi & 0xffff; + esi += (unsigned int)context.vm.regs.ds << 4; + if (context.vm.regs.eflags & DIRECTION_FLAG) { + if (size == 4) + asm volatile ("std; rep; outsl; cld" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + else if (size == 2) + asm volatile ("std; rep; outsw; cld" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + else + asm volatile ("std; rep; outsb; cld" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + } + else { + if (size == 4) + asm volatile ("cld; rep; outsl" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + else if (size == 2) + asm volatile ("cld; rep; outsw" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + else + asm volatile ("cld; rep; outsb" + : "=S" (esi), "=c" (ecx) + : "d" (edx), "0" (esi), "1" (ecx)); + } + + esi -= (unsigned int)context.vm.regs.ds << 4; + context.vm.regs.esi &= 0xffff0000; + context.vm.regs.esi |= esi & 0xffff; + context.vm.regs.ecx &= 0xffff0000; + context.vm.regs.ecx |= ecx & 0xffff; +} + +static int emulate(void) +{ + unsigned char *insn; + struct { + unsigned int size : 1; + unsigned int rep : 1; + } prefix = { 0, 0 }; + int i = 0; + + insn = (unsigned char *)((unsigned int)context.vm.regs.cs << 4); + insn += context.vm.regs.eip; + + while (1) { +#ifdef TRACE_IO + traceAddr = ((ulong)context.vm.regs.cs << 16) + context.vm.regs.eip + i; +#endif + if (insn[i] == 0x66) { + prefix.size = 1 - prefix.size; + i++; + } + else if (insn[i] == 0xf3) { + prefix.rep = 1; + i++; + } + else if (insn[i] == 0xf0 || insn[i] == 0xf2 + || insn[i] == 0x26 || insn[i] == 0x2e + || insn[i] == 0x36 || insn[i] == 0x3e + || insn[i] == 0x64 || insn[i] == 0x65 + || insn[i] == 0x67) { + /* these prefixes are just ignored */ + i++; + } + else if (insn[i] == 0x6c) { + if (prefix.rep) + em_rep_ins(1); + else + em_ins(1); + i++; + break; + } + else if (insn[i] == 0x6d) { + if (prefix.rep) { + if (prefix.size) + em_rep_ins(4); + else + em_rep_ins(2); + } + else { + if (prefix.size) + em_ins(4); + else + em_ins(2); + } + i++; + break; + } + else if (insn[i] == 0x6e) { + if (prefix.rep) + em_rep_outs(1); + else + em_outs(1); + i++; + break; + } + else if (insn[i] == 0x6f) { + if (prefix.rep) { + if (prefix.size) + em_rep_outs(4); + else + em_rep_outs(2); + } + else { + if (prefix.size) + em_outs(4); + else + em_outs(2); + } + i++; + break; + } + else if (insn[i] == 0xec) { + *((uchar*)&context.vm.regs.eax) = port_in(context.vm.regs.edx); + i++; + break; + } + else if (insn[i] == 0xed) { + if (prefix.size) + *((ulong*)&context.vm.regs.eax) = port_inl(context.vm.regs.edx); + else + *((ushort*)&context.vm.regs.eax) = port_inw(context.vm.regs.edx); + i++; + break; + } + else if (insn[i] == 0xee) { + port_out(context.vm.regs.eax,context.vm.regs.edx); + i++; + break; + } + else if (insn[i] == 0xef) { + if (prefix.size) + port_outl(context.vm.regs.eax,context.vm.regs.edx); + else + port_outw(context.vm.regs.eax,context.vm.regs.edx); + i++; + break; + } + else + return 0; + } + + context.vm.regs.eip += i; + return 1; +} + +static void debug_info(int vret) +{ + int i; + unsigned char *p; + + fputs("vm86() failed\n", stderr); + fprintf(stderr, "return = 0x%x\n", vret); + fprintf(stderr, "eax = 0x%08lx\n", context.vm.regs.eax); + fprintf(stderr, "ebx = 0x%08lx\n", context.vm.regs.ebx); + fprintf(stderr, "ecx = 0x%08lx\n", context.vm.regs.ecx); + fprintf(stderr, "edx = 0x%08lx\n", context.vm.regs.edx); + fprintf(stderr, "esi = 0x%08lx\n", context.vm.regs.esi); + fprintf(stderr, "edi = 0x%08lx\n", context.vm.regs.edi); + fprintf(stderr, "ebp = 0x%08lx\n", context.vm.regs.ebp); + fprintf(stderr, "eip = 0x%08lx\n", context.vm.regs.eip); + fprintf(stderr, "cs = 0x%04x\n", context.vm.regs.cs); + fprintf(stderr, "esp = 0x%08lx\n", context.vm.regs.esp); + fprintf(stderr, "ss = 0x%04x\n", context.vm.regs.ss); + fprintf(stderr, "ds = 0x%04x\n", context.vm.regs.ds); + fprintf(stderr, "es = 0x%04x\n", context.vm.regs.es); + fprintf(stderr, "fs = 0x%04x\n", context.vm.regs.fs); + fprintf(stderr, "gs = 0x%04x\n", context.vm.regs.gs); + fprintf(stderr, "eflags = 0x%08lx\n", context.vm.regs.eflags); + fputs("cs:ip = [ ", stderr); + p = (unsigned char *)((context.vm.regs.cs << 4) + (context.vm.regs.eip & 0xffff)); + for (i = 0; i < 16; ++i) + fprintf(stderr, "%02x ", (unsigned int)p[i]); + fputs("]\n", stderr); + fflush(stderr); +} + +static int run_vm86(void) +{ + unsigned int vret; + + for (;;) { + vret = vm86(&context.vm); + if (VM86_TYPE(vret) == VM86_INTx) { + unsigned int v = VM86_ARG(vret); + if (v == RETURN_TO_32_INT) + return 1; + pushw(context.vm.regs.eflags); + pushw(context.vm.regs.cs); + pushw(context.vm.regs.eip); + context.vm.regs.cs = get_int_seg(v); + context.vm.regs.eip = get_int_off(v); + context.vm.regs.eflags &= ~(VIF_MASK | TF_MASK); + continue; + } + if (VM86_TYPE(vret) != VM86_UNKNOWN) + break; + if (!emulate()) + break; + } + debug_info(vret); + return 0; +} + +#define IND(ereg) context.vm.regs.ereg = regs->ereg +#define OUTD(ereg) regs->ereg = context.vm.regs.ereg + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + IND(eax); IND(ebx); IND(ecx); IND(edx); IND(esi); IND(edi); + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(intno); + context.vm.regs.eip = get_int_off(intno); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); + OUTD(eax); OUTD(ebx); OUTD(ecx); OUTD(edx); OUTD(esi); OUTD(edi); + regs->flags = context.vm.regs.eflags; +} + +#define IN(ereg) context.vm.regs.ereg = in->e.ereg +#define OUT(ereg) out->e.ereg = context.vm.regs.ereg + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(intno); + context.vm.regs.eip = get_int_off(intno); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + out->x.cflag = context.vm.regs.eflags & 1; + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + if (!inited) + PM_init(); + if (intno == 0x21) { + time_t today = time(NULL); + struct tm *t; + t = localtime(&today); + out->x.cx = t->tm_year + 1900; + out->h.dh = t->tm_mon + 1; + out->h.dl = t->tm_mday; + } + else { + unsigned int seg, off; + seg = get_int_seg(intno); + off = get_int_off(intno); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = seg; + context.vm.regs.eip = off; + context.vm.regs.es = sregs->es; + context.vm.regs.ds = sregs->ds; + context.vm.regs.fs = sregs->fs; + context.vm.regs.gs = sregs->gs; + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + sregs->es = context.vm.regs.es; + sregs->ds = context.vm.regs.ds; + sregs->fs = context.vm.regs.fs; + sregs->gs = context.vm.regs.gs; + out->x.cflag = context.vm.regs.eflags & 1; + } + return out->e.eax; +} + +#define OUTR(ereg) in->e.ereg = context.vm.regs.ereg + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, + RMSREGS *sregs) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = seg; + context.vm.regs.eip = off; + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + context.vm.regs.es = sregs->es; + context.vm.regs.ds = sregs->ds; + context.vm.regs.fs = sregs->fs; + context.vm.regs.gs = sregs->gs; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); + OUTR(eax); OUTR(ebx); OUTR(ecx); OUTR(edx); OUTR(esi); OUTR(edi); + sregs->es = context.vm.regs.es; + sregs->ds = context.vm.regs.ds; + sregs->fs = context.vm.regs.fs; + sregs->gs = context.vm.regs.gs; + in->x.cflag = context.vm.regs.eflags & 1; +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + FILE *mem = fopen("/proc/meminfo","r"); + char buf[1024]; + + fgets(buf,1024,mem); + fgets(buf,1024,mem); + sscanf(buf,"Mem: %*d %*d %ld", physical); + fgets(buf,1024,mem); + sscanf(buf,"Swap: %*d %*d %ld", total); + fclose(mem); + *total += *physical; +} + +void * PMAPI PM_allocLockedMem(uint size,ulong *physAddr,ibool contiguous,ibool below16M) +{ + /* TODO: Implement this for Linux */ + return NULL; +} + +void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) +{ + /* TODO: Implement this for Linux */ +} + +void * PMAPI PM_allocPage( + ibool locked) +{ + /* TODO: Implement this for Linux */ + return NULL; +} + +void PMAPI PM_freePage( + void *p) +{ + /* TODO: Implement this for Linux */ +} + +void PMAPI PM_setBankA(int bank) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + context.vm.regs.eax = 0x4F05; + context.vm.regs.ebx = 0x0000; + context.vm.regs.edx = bank; + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(0x10); + context.vm.regs.eip = get_int_off(0x10); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); +} + +void PMAPI PM_setBankAB(int bank) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + context.vm.regs.eax = 0x4F05; + context.vm.regs.ebx = 0x0000; + context.vm.regs.edx = bank; + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(0x10); + context.vm.regs.eip = get_int_off(0x10); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); + context.vm.regs.eax = 0x4F05; + context.vm.regs.ebx = 0x0001; + context.vm.regs.edx = bank; + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(0x10); + context.vm.regs.eip = get_int_off(0x10); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); +} + +void PMAPI PM_setCRTStart(int x,int y,int waitVRT) +{ + if (!inited) + PM_init(); + memset(&context.vm.regs, 0, sizeof(context.vm.regs)); + context.vm.regs.eax = 0x4F07; + context.vm.regs.ebx = waitVRT; + context.vm.regs.ecx = x; + context.vm.regs.edx = y; + context.vm.regs.eflags = DEFAULT_VM86_FLAGS; + context.vm.regs.cs = get_int_seg(0x10); + context.vm.regs.eip = get_int_off(0x10); + context.vm.regs.ss = context.stack_seg; + context.vm.regs.esp = context.stack_off; + pushw(DEFAULT_VM86_FLAGS); + pushw(context.ret_seg); + pushw(context.ret_off); + run_vm86(); +} + +int PMAPI PM_enableWriteCombine(ulong base,ulong length,uint type) +{ +#ifdef ENABLE_MTRR + struct mtrr_sentry sentry; + + if (mtrr_fd < 0) + return PM_MTRR_ERR_NO_OS_SUPPORT; + sentry.base = base; + sentry.size = length; + sentry.type = type; + if (ioctl(mtrr_fd, MTRRIOC_ADD_ENTRY, &sentry) == -1) { + /* TODO: Need to decode MTRR error codes!! */ + return PM_MTRR_NOT_SUPPORTED; + } + return PM_MTRR_ERR_OK; +#else + return PM_MTRR_ERR_NO_OS_SUPPORT; +#endif +} + +/**************************************************************************** +PARAMETERS: +callback - Function to callback with write combine information + +REMARKS: +Function to enumerate all write combine regions currently enabled for the +processor. +****************************************************************************/ +int PMAPI PM_enumWriteCombine( + PM_enumWriteCombine_t callback) +{ +#ifdef ENABLE_MTRR + struct mtrr_gentry gentry; + + if (mtrr_fd < 0) + return PM_MTRR_ERR_NO_OS_SUPPORT; + + for (gentry.regnum = 0; ioctl (mtrr_fd, MTRRIOC_GET_ENTRY, &gentry) == 0; + ++gentry.regnum) { + if (gentry.size > 0) { + /* WARNING: This code assumes that the types in pmapi.h match the ones */ + /* in the Linux kernel (mtrr.h) */ + callback(gentry.base, gentry.size, gentry.type); + } + } + + return PM_MTRR_ERR_OK; +#else + return PM_MTRR_ERR_NO_OS_SUPPORT; +#endif +} + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *copyOfBIOS, + ulong BIOSLen) +{ + char *bios_ptr = (char*)0xC0000; + char *old_bios; + ulong Current10, Current6D, *rvec = 0; + RMREGS regs; + RMSREGS sregs; + + /* The BIOS is mapped to 0xC0000 with a private memory mapping enabled + * which means we have a copy on write scheme. Hence we simply copy + * the secondary BIOS image over the top of the old one. + */ + if (!inited) + PM_init(); + if ((old_bios = PM_malloc(BIOSLen)) == NULL) + return false; + if (BIOSPhysAddr != 0xC0000) { + memcpy(old_bios,bios_ptr,BIOSLen); + memcpy(bios_ptr,copyOfBIOS,BIOSLen); + } + + /* The interrupt vectors should already be mmap()'ed from 0-0x400 in PM_init */ + Current10 = rvec[0x10]; + Current6D = rvec[0x6D]; + + /* POST the secondary BIOS */ + rvec[0x10] = rvec[0x42]; /* Restore int 10h to STD-BIOS */ + regs.x.ax = axVal; + PM_callRealMode(0xC000,0x0003,®s,&sregs); + + /* Restore interrupt vectors */ + rvec[0x10] = Current10; + rvec[0x6D] = Current6D; + + /* Restore original BIOS image */ + if (BIOSPhysAddr != 0xC0000) + memcpy(bios_ptr,old_bios,BIOSLen); + PM_free(old_bios); + return true; +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* TODO: Implement this to load shared libraries! */ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* TODO: Implement this! */ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* TODO: Implement this! */ + (void)hModule; +} + +int PMAPI PM_setIOPL( + int level) +{ + /* TODO: Move the IOPL switching into this function!! */ + return level; +} + +void PMAPI PM_flushTLB(void) +{ + /* Do nothing on Linux. */ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c new file mode 100644 index 000000000..579ef2c95 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c new file mode 100644 index 000000000..1b9bae28a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/linux/ztimer.c @@ -0,0 +1,95 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux +* +* Description: Linux specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ +} + +/**************************************************************************** +REMARKS: +Use the gettimeofday() function to get microsecond precision (probably less +though) +****************************************************************************/ +static inline ulong __ULZReadTime(void) +{ + struct timeval t; + gettimeofday(&t, NULL); + return t.tv_sec*1000000 + t.tv_usec; +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +#define __LZTimerOn(tm) tm->start.low = __ULZReadTime() + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +#define __LZTimerLap(tm) (__ULZReadTime() - tm->start.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) tm->end.low = __ULZReadTime() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerCount(tm) (tm->end.low - tm->start.low) + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1 + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/makefile b/board/MAI/bios_emulator/scitech/src/pm/makefile new file mode 100644 index 000000000..265f0e36d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/makefile @@ -0,0 +1,290 @@ +############################################################################# +# +# Copyright (C) 1996 SciTech Software. +# All rights reserved. +# +# Descripton: Generic makefile for the PM library. Builds the library +# file and all test programs. +# +############################################################################# + +.IMPORT .IGNORE : DEBUG_AGP_DRIVER TEST_HARNESS DEBUG_SDDPMI + +#---------------------------------------------------------------------------- +# Add DOS extender dependant flags to command line +#---------------------------------------------------------------------------- + +CFLAGS += $(DX_CFLAGS) +ASFLAGS += $(DX_ASFLAGS) +NO_PMLIB := 1 + +#---------------------------------------------------------------------------- +# Include definitions specific for the target system +#---------------------------------------------------------------------------- + +.IF $(USE_VXD) + +# Building for Win32 VxD (minimal PM library implementation) + +LIBNAME = pm +OBJECTS = pm$O vflat$O ztimer$O cpuinfo$O mtrr$O fileio$O pcilib$O \ + agp$O malloc$O vgastate$O gavxd$O _pm$O _mtrr$O _cpuinfo$O \ + _int64$O _pcihelp$O +DEPEND_SRC := vxd;common;codepage;tests +.SOURCE: vxd common codepage tests + +.ELIF $(USE_NTDRV) + +# Building for NT device drivers (minimal PM library implementation) + +LIBNAME = pm +OBJECTS = pm$O vflat$O ztimer$O cpuinfo$O mtrr$O mem$O irq$O int86$O \ + stdio$O stdlib$O pcilib$O agp$O malloc$O vgastate$O gantdrv$O \ + _pm$O _mtrr$O _cpuinfo$O _int64$O _pcihelp$O _irq$O +DEPEND_SRC := ntdrv;common;codepage;tests +.SOURCE: ntdrv common codepage tests + +.ELIF $(USE_WIN32) + +# Building for Win32 + +CFLAGS += -DUSE_OS_JOYSTICK +LIBNAME = pm +OBJECTS = pm$O vflat$O event$O ddraw$O ztimer$O cpuinfo$O pcilib$O \ + agp$O malloc$O vgastate$O gawin32$O ntservc$O _joy$O _cpuinfo$O \ + _int64$O _pcihelp$O +DEPEND_SRC := win32;common;codepage;tests +.SOURCE: win32 common codepage tests + +.ELIF $(USE_OS232) + +# Building for OS/2 + +.IF $(USE_OS2GUI) +LIBNAME = pm_pm +.ELSE +LIBNAME = pm +.ENDIF +OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ + agp$O malloc$O vgastate$O gaos2$O _pmos2$O _joy$O _cpuinfo$O \ + _int64$O _pcihelp$O dossctl$O +DEPEND_SRC := os2;common;codepage;tests +.SOURCE: os2 common codepage tests + +.ELIF $(USE_QNX) + +# Building for QNX + +USE_BIOS := 1 +.IF $(USE_PHOTON) +LIBNAME = pm_ph +.ELIF $(USE_X11) +LIBNAME = pm_x11 +.ELSE +LIBNAME = pm +.ENDIF +OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ + agp$O malloc$O mtrrqnx$O unixio$O vgastate$O gaqnx$O _joy$O \ + _mtrrqnx$O _cpuinfo$O _int64$O _pcihelp$O +DEPEND_SRC := qnx;common;codepage;tests +.SOURCE: qnx common codepage tests + +# Indicate that this program uses Nucleus device drivers (so needs I/O access) +USE_NUCLEUS := 1 + +.ELIF $(USE_LINUX) + +# Building for Linux + +CFLAGS += -DENABLE_MTRR -DUSE_OS_JOYSTICK +.IF $(USE_X11) +LIBNAME = pm_x11 +.ELSE +LIBNAME = pm +.ENDIF +OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O pcilib$O \ + agp$O malloc$O unixio$O vgastate$O galinux$O _cpuinfo$O \ + _int64$O _pcihelp$O +DEPEND_SRC := linux;common;codepage;tests;x11 +.SOURCE: linux common codepage tests x11 + +# Building a shared library +.IF $(SOFILE) +LIB := ld +LIBFLAGS := -r -o +CFLAGS += -fPIC +.ENDIF + +.ELIF $(USE_BEOS) + +# Building for BeOS GUI + +LIBNAME = pm +OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O pcilib$O \ + agp$O malloc$O vgastate$O gabeos$O _joy$O _cpuinfo$O \ + _int64$O _pcihelp$O +DEPEND_SRC := beos;common;codepage;tests +.SOURCE: beos common codepage tests + +.ELIF $(USE_SMX32) + +# Building for SMX + +LIBNAME = pm +OBJECTS = pm$O pmsmx$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ + agp$O malloc$O vgastate$O gasmx$O _pm$O _pmsmx$O _mtrr$O _event$O \ + _joy$O _cpuinfo$O _int64$O _pcihelp$O _lztimer$O +DEPEND_SRC := smx;common;codepage;tests +.SOURCE: smx common codepage tests + +.ELIF $(USE_RTTARGET) + +# Building for RTTarget-32 + +LIBNAME = pm +OBJECTS = pm$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O pcilib$O \ + agp$O malloc$O vgastate$O gartt$O _mtrr$O _joy$O _cpuinfo$O \ + _int64$O _pcihelp$O +DEPEND_SRC := rttarget;common;codepage;tests +.SOURCE: rttarget common codepage tests + +.ELSE + +# Building for MSDOS + +LIBNAME = pm +OBJECTS = pm$O pmdos$O vflat$O event$O ztimer$O cpuinfo$O mtrr$O \ + agp$O malloc$O pcilib$O vgastate$O gados$O \ + _pm$O _pmdos$O _mtrr$O _vflat$O _event$O _joy$O _pcihelp$O \ + _cpuinfo$O _int64$O _lztimer$O _dma$O +DEPEND_SRC := dos;common;codepage;tests +.SOURCE: dos common codepage tests + +.ENDIF + +# Object modules for keyboard code pages + +OBJECTS += us_eng$O + +# Common object modules + +OBJECTS += common$O +.IF $(CHECKED) +OBJECTS += debug$O +.ENDIF + +# Nucleus loader library object modules. Note that when compiling a test harness +# library we need to exclude the Nucleus loader library. + +.IF $(TEST_HARNESS) +CFLAGS += -DTEST_HARNESS -DPMLIB +LIBNAME = pm_test +.ELSE +OBJECTS += galib$O _ga_imp$O +.ENDIF + +.IF $(DEBUG_SDDPMI) +CFLAGS += -DDEBUG_SDDPMI +.ENDIF + +# AGP library object modules + +.IF $(DEBUG_AGP_DRIVER) +CFLAGS += -DDEBUG_AGP_DRIVER +OBJECTS += agplib$O +.ELSE +OBJECTS += agplib$O peloader$O libcimp$O _gatimer$O +.ENDIF + +#---------------------------------------------------------------------------- +# Name of library and generic object files required to build it +#---------------------------------------------------------------------------- + +.IF $(STKCALL) +LIBFILE = s$(LP)$(LIBNAME)$L +.ELSE +LIBFILE = $(LP)$(LIBNAME)$L +.ENDIF +LIBCLEAN = *.lib *.a + +#---------------------------------------------------------------------------- +# Change destination for library file depending the extender being used. This +# is only necessary for DOS extender since the file go into a subdirectory +# in the normal library directory, one for each supported extender. Other +# OS'es put the file into the regular library directory, since there is +# only one per OS in this case. +#---------------------------------------------------------------------------- + +MK_PMODE = 1 + +.IF $(TEST_HARNESS) +LIB_DEST := $(LIB_BASE) +.ELIF $(USE_TNT) +LIB_DEST := $(LIB_BASE)\tnt +.ELIF $(USE_DOS4GW) +LIB_DEST := $(LIB_BASE)\dos4gw +.ELIF $(USE_X32) +LIB_DEST := $(LIB_BASE)\x32 +.ELIF $(USE_DPMI16) +LIB_DEST := $(LIB_BASE)\dpmi16 +.ELIF $(USE_DPMI32) +LIB_DEST := $(LIB_BASE)\dpmi32 +.ELIF $(USE_DOSX) +LIB_DEST := $(LIB_BASE)\dosx +.END + +#---------------------------------------------------------------------------- +# Names of all executable files built +#---------------------------------------------------------------------------- + +.IF $(USE_REALDOS) +EXEFILES = memtest$E biosptr$E video$E isvesa$E callreal$E \ + mouse$E tick$E key$E key15$E brk$E altbrk$E \ + critical$E altcrit$E vftest$E rtc$E getch$E \ + cpu$E timerc$E timercpp$E showpci$E uswc$E block$E +.ELSE +EXEFILES = memtest$E video$E isvesa$E callreal$E vftest$E getch$E \ + cpu$E timerc$E timercpp$E showpci$E uswc$E block$E \ + save$E restore$E +.ENDIF + +all: $(EXEFILES) + +$(EXEFILES): $(LIBFILE) + +memtest$E: memtest$O +biosptr$E: biosptr$O +video$E: video$O +isvesa$E: isvesa$O +mouse$E: mouse$O +tick$E: tick$O +key$E: key$O +key15$E: key15$O +brk$E: brk$O +altbrk$E: altbrk$O +critical$E: critical$O +altcrit$E: altcrit$O +callreal$E: callreal$O +vftest$E: vftest$O +rtc$E: rtc$O +getch$E: getch$O +cpu$E: cpu$O +timerc$E: timerc$O +timercpp$E: timercpp$O +showpci$E: showpci$O +uswc$E: uswc$O +block$E: block$O +save$E: save$O +restore$E: restore$O +test$E: test$O _test$O + +#---------------------------------------------------------------------------- +# Define the list of object files to create dependency information for +#---------------------------------------------------------------------------- + +DEPEND_OBJ := $(OBJECTS) memtest$O biosptr$O video$O isvesa$O mouse$O \ + tick$O key$O key$O brk$O altbrk$O critical$O altcrit$O \ + callreal$O vftest$O getch$O timercpp$O + +.INCLUDE: "$(SCITECH)/makedefs/common.mk" + diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm new file mode 100644 index 000000000..11824a0af --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_irq.asm @@ -0,0 +1,288 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 32-bit Windows NT device driver +;* +;* Description: Low level assembly support for the PM library specific to +;* Windows NT device drivers. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _irq ; Set up memory model + +begdataseg _irq + + cextern _PM_rtcHandler,CPTR + cextern _PM_prevRTC,FCPTR + +RtcInside dw 0 ; Are we still handling current interrupt +sidtBuf df 0 ; Buffer for sidt instruction + +enddataseg _irq + +begcodeseg _irq ; Start of code segment + +cpublic _PM_irqCodeStart + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; PM_rtcISR - Real time clock interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the timer interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible, since a timer overrun will simply hang the +; system. +;---------------------------------------------------------------------------- +cprocfar _PM_rtcISR + +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +; If we enable interrupts and call into any C based interrupt handling code, +; we need to setup a bunch of important information for the NT kernel. The +; code below takes care of this housekeeping for us (see Undocumented NT for +; details). If we don't do this housekeeping and interrupts are enabled, +; the kernel will become very unstable and crash within 10 seconds or so. +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + pushad + pushfd + push fs + + mov ebx,00000030h + mov fs,bx + sub esp,50h + mov ebp,esp + +; Setup the exception frame to NULL + + mov ebx,[DWORD cs:0FFDFF000h] + mov [DWORD ds:0FFDFF000h], 0FFFFFFFFh + mov [DWORD ebp],ebx + +; Save away the existing KSS ebp + + mov esi,[DWORD cs:0FFDFF124h] + mov ebx,[DWORD esi+00000128h] + mov [DWORD ebp+4h],ebx + mov [DWORD esi+00000128h],ebp + +; Save away the kernel time and the thread mode (kernel/user) + + mov edi,[DWORD esi+00000137h] + mov [DWORD ebp+8h],edi + +; Set the thread mode (kernel/user) based on the code selector + + mov ebx,[DWORD ebp+7Ch] + and ebx,01 + mov [BYTE esi+00000137h],bl + +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +; End of special interrupt Prolog code +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +; Clear priority interrupt controller and re-enable interrupts so we +; dont lock things up for long. + + mov al,20h + out 0A0h,al + out 020h,al + +; Clear real-time clock timeout + + in al,70h ; Read CMOS index register + push eax ; and save for later + IODELAYN 3 + mov al,0Ch + out 70h,al + IODELAYN 5 + in al,71h + +; Call the C interrupt handler function + + cmp [BYTE RtcInside],1 ; Check for mutual exclusion + je @@Exit + mov [BYTE RtcInside],1 + sti ; Enable interrupts + cld ; Clear direction flag for C code + call [CPTR _PM_rtcHandler] + cli ; Disable interrupts on exit! + mov [BYTE RtcInside],0 + +@@Exit: pop eax + out 70h,al ; Restore CMOS index register + +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +; Start of special epilog code to restore stuff on exit from handler +;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + +; Restore the KSS ebp + + mov esi,[DWORD cs:0FFDFF124h] + mov ebx,[DWORD ebp+4] + mov [DWORD esi+00000128h],ebx + +; Restore the exception frame + + mov ebx,[DWORD ebp] + mov [DWORD fs:00000000],ebx + +; Restore the thread mode + + mov ebx,[DWORD ebp+8h] + mov esi,[DWORD fs:00000124h] + mov [BYTE esi+00000137h],bl + add esp, 50h + pop fs + popfd + popad + +; Return from interrupt + + iret + +cprocend + +cpublic _PM_irqCodeEnd + +;---------------------------------------------------------------------------- +; void _PM_getISR(int irq,PMFARPTR *handler); +;---------------------------------------------------------------------------- +; Function to return the specific IRQ handler direct from the IDT. +;---------------------------------------------------------------------------- +cprocstart _PM_getISR + + ARG idtEntry:UINT, handler:DPTR + + enter_c 0 + mov ecx,[handler] ; Get address of handler to fill in + sidt [sidtBuf] ; Get IDTR register into sidtBuf + mov eax,[DWORD sidtBuf+2] ; Get address of IDT into EAX + mov ebx,[idtEntry] + lea eax,[eax+ebx*8] ; Get entry in the IDT + movzx edx,[WORD eax+6] ; Get high order 16-bits + shl edx,16 ; Move into top 16-bits of address + mov dx,[WORD eax] ; Get low order 16-bits + mov [DWORD ecx],edx ; Store linear address of handler + mov dx,[WORD eax+2] ; Get selector value + mov [WORD ecx+4],dx ; Store selector value + leave_c + ret + +cprocend _PM_getISR + +;---------------------------------------------------------------------------- +; void _PM_setISR(int irq,void *handler); +;---------------------------------------------------------------------------- +; Function to set the specific IRQ handler direct in the IDT. +;---------------------------------------------------------------------------- +cprocstart _PM_setISR + + ARG irq:UINT, handler:CPTR + + enter_c 0 + mov ecx,[handler] ; Get address of new handler + mov dx,cs ; Get selector for new handler + sidt [sidtBuf] ; Get IDTR register into sidtBuf + mov eax,[DWORD sidtBuf+2] ; Get address of IDT into EAX + mov ebx,[idtEntry] + lea eax,[eax+ebx*8] ; Get entry in the IDT + cli + mov [WORD eax+2],dx ; Store code segment selector + mov [WORD eax],cx ; Store low order bits of handler + shr ecx,16 + mov [WORD eax+6],cx ; Store high order bits of handler + sti + leave_c + ret + +cprocend _PM_setISR + +;---------------------------------------------------------------------------- +; void _PM_restoreISR(int irq,PMFARPTR *handler); +;---------------------------------------------------------------------------- +; Function to set the specific IRQ handler direct in the IDT. +;---------------------------------------------------------------------------- +cprocstart _PM_restoreISR + + ARG irq:UINT, handler:CPTR + + enter_c 0 + mov ecx,[handler] + mov dx,[WORD ecx+4] ; Get selector for old handler + mov ecx,[DWORD ecx] ; Get address of old handler + sidt [sidtBuf] ; Get IDTR register into sidtBuf + mov eax,[DWORD sidtBuf+2] ; Get address of IDT into EAX + mov ebx,[idtEntry] + lea eax,[eax+ebx*8] ; Get entry in the IDT + cli + mov [WORD eax+2],dx ; Store code segment selector + mov [WORD eax],cx ; Store low order bits of handler + shr ecx,16 + mov [WORD eax+6],cx ; Store high order bits of handler + sti + leave_c + ret + +cprocend _PM_restoreISR + +endcodeseg _irq + + END ; End of module + diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm new file mode 100644 index 000000000..6cb276d25 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/_pm.asm @@ -0,0 +1,281 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 32-bit Windows NT device driver +;* +;* Description: Low level assembly support for the PM library specific to +;* Windows NT device drivers. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pm ; Set up memory model + +P586 + +begdataseg + +; Watcom C++ externals required to link when compiling floating point +; C code. They are not actually used in the code because we compile with +; inline floating point instructions, however the compiler still generates +; the references in the object modules. + +__8087 dd 0 + PUBLIC __8087 +__imthread: +__fltused: +_fltused_ dd 0 + PUBLIC __imthread + PUBLIC _fltused_ + PUBLIC __fltused + +enddataseg + +begcodeseg _pm ; Start of code segment + +;---------------------------------------------------------------------------- +; void PM_segread(PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Read the current value of all segment registers +;---------------------------------------------------------------------------- +cprocstart PM_segread + + ARG sregs:DPTR + + enter_c + + mov ax,es + _les _si,[sregs] + mov [_ES _si],ax + mov [_ES _si+2],cs + mov [_ES _si+4],ss + mov [_ES _si+6],ds + mov [_ES _si+8],fs + mov [_ES _si+10],gs + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Issues a software interrupt in protected mode. This routine has been +; written to allow user programs to load CS and DS with different values +; other than the default. +;---------------------------------------------------------------------------- +cprocstart PM_int386x + +; Not used for NT device drivers + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankA(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankA + +; Not used for NT device drivers + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankAB(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankAB + +; Not used for NT device drivers + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setCRTStart(int x,int y,int waitVRT) +;---------------------------------------------------------------------------- +cprocstart PM_setCRTStart + +; Not used for NT device drivers + + ret + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; uchar _PM_readCMOS(int index) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_readCMOS + + ARG index:UINT + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + in al,71h + mov ah,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + mov al,ah ; Return value in AL + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_writeCMOS(int index,uchar value) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_writeCMOS + + ARG index:UINT, value:UCHAR + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + mov al,[value] + out 71h,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; double _ftol(double f) +;---------------------------------------------------------------------------- +; Calls to __ftol are generated by the Borland C++ compiler for code +; that needs to convert a floating point type to an integral type. +; +; Input: floating point number on the top of the '87. +; +; Output: a (signed or unsigned) long in EAX +; All other registers preserved. +;----------------------------------------------------------------------- +cprocstart _ftol + + LOCAL temp1:WORD, temp2:QWORD = LocalSize + + push ebp + mov ebp,esp + sub esp,LocalSize + + fstcw [temp1] ; save the control word + fwait + mov al,[BYTE temp1+1] + or [BYTE temp1+1],0Ch ; set rounding control to chop + fldcw [temp1] + fistp [temp2] ; convert to 64-bit integer + mov [BYTE temp1+1],al + fldcw [temp1] ; restore the control word + mov eax,[DWORD temp2] ; return LS 32 bits + mov edx,[DWORD temp2+4] ; MS 32 bits + + mov esp,ebp + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; _PM_getPDB - Return the Page Table Directory Base address +;---------------------------------------------------------------------------- +cprocstart _PM_getPDB + + mov eax,cr3 + and eax,0FFFFF000h + ret + +cprocend + +;---------------------------------------------------------------------------- +; Flush the Translation Lookaside buffer +;---------------------------------------------------------------------------- +cprocstart PM_flushTLB + + wbinvd ; Flush the CPU cache + mov eax,cr3 + mov cr3,eax ; Flush the TLB + ret + +cprocend + +endcodeseg _pm + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c new file mode 100644 index 000000000..d15b07c29 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/cpuinfo.c @@ -0,0 +1,64 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: VxD specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Do nothing for VxD's +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +Do nothing for VxD's +****************************************************************************/ +#define RestoreThreadPriority(i) (void)(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + KeQueryPerformanceCounter((LARGE_INTEGER*)freq); +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL); \ + (t)->low = lt.LowPart; \ + (t)->high = lt.HighPart; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c new file mode 100644 index 000000000..c82648b78 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/int86.c @@ -0,0 +1,251 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT device drivers. +* +* Description: Implementation for the real mode software interrupt +* handling functions. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" +#include "oshdr.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +We do have limited BIOS access under Windows NT device drivers. +****************************************************************************/ +ibool PMAPI PM_haveBIOSAccess(void) +{ + /* Return false unless we have full buffer passing! */ + return false; +} + +/**************************************************************************** +PARAMETERS: +len - Place to store the length of the buffer +rseg - Place to store the real mode segment of the buffer +roff - Place to store the real mode offset of the buffer + +REMARKS: +This function returns the address and length of the global VESA transfer +buffer that is used for communicating with the VESA BIOS functions from +Win16 and Win32 programs under Windows. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + /* No buffers supported under Windows NT (Windows XP has them however if */ + /* we ever decide to support this!) */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Issue a protected mode software interrupt. +****************************************************************************/ +int PMAPI PM_int386( + int intno, + PMREGS *in, + PMREGS *out) +{ + PMSREGS sregs; + PM_segread(&sregs); + return PM_int386x(intno,in,out,&sregs); +} + +/**************************************************************************** +REMARKS: +Map a real mode pointer to a protected mode pointer. +****************************************************************************/ +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + /* Not used for Windows NT drivers! */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Allocate a block of real mode memory +****************************************************************************/ +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + /* Not supported in NT drivers */ + (void)size; + (void)r_seg; + (void)r_off; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of real mode memory. +****************************************************************************/ +void PMAPI PM_freeRealSeg( + void *mem) +{ + /* Not supported in NT drivers */ + (void)mem; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt (parameters in DPMI compatible structure) +****************************************************************************/ +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + /* Not used in NT drivers */ +} + +/**************************************************************************** +REMARKS: +Call a V86 real mode function with the specified register values +loaded before the call. The call returns with a far ret. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *regs, + RMSREGS *sregs) +{ + /* TODO!! */ +#if 0 + CLIENT_STRUCT saveRegs; + + /* Bail if we do not have BIOS access (ie: the VxD was dynamically + * loaded, and not statically loaded. + */ + if (!_PM_haveBIOS) + return; + + TRACE("SDDHELP: Entering PM_callRealMode()\n"); + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,regs,sregs); + Simulate_Far_Call(seg, off); + Resume_Exec(); + ReadV86Registers(&saveRegs,regs,sregs); + End_Nest_Exec(); + TRACE("SDDHELP: Exiting PM_callRealMode()\n"); +#endif +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + /* TODO!! */ +#if 0 + RMSREGS sregs = {0}; + CLIENT_STRUCT saveRegs; + ushort oldDisable; + + /* Disable pass-up to our VxD handler so we directly call BIOS */ + TRACE("SDDHELP: Entering PM_int86()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,in,&sregs); + Exec_Int(intno); + ReadV86Registers(&saveRegs,out,&sregs); + End_Nest_Exec(); + + /* Re-enable pass-up to our VxD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; + + TRACE("SDDHELP: Exiting PM_int86()\n"); +#else + *out = *in; +#endif + return out->x.ax; +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + /* TODO!! */ +#if 0 + CLIENT_STRUCT saveRegs; + ushort oldDisable; + + /* Bail if we do not have BIOS access (ie: the VxD was dynamically + * loaded, and not statically loaded. + */ + if (!_PM_haveBIOS) { + *out = *in; + return out->x.ax; + } + + /* Disable pass-up to our VxD handler so we directly call BIOS */ + TRACE("SDDHELP: Entering PM_int86x()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,in,sregs); + Exec_Int(intno); + ReadV86Registers(&saveRegs,out,sregs); + End_Nest_Exec(); + + /* Re-enable pass-up to our VxD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; + + TRACE("SDDHELP: Exiting PM_int86x()\n"); +#else + *out = *in; +#endif + return out->x.ax; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c new file mode 100644 index 000000000..9cd52047b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/irq.c @@ -0,0 +1,142 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT device drivers. +* +* Description: Implementation for the NT driver IRQ management functions +* for the PM library. +* +****************************************************************************/ + +#include "pmapi.h" +#include "pmint.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" +#include "oshdr.h" + +/*--------------------------- Global variables ----------------------------*/ + +static int globalDataStart; +static uchar _PM_oldCMOSRegA; +static uchar _PM_oldCMOSRegB; +static uchar _PM_oldRTCPIC2; +static ulong RTC_idtEntry; +PM_intHandler _PM_rtcHandler = NULL; +PMFARPTR _VARAPI _PM_prevRTC = PMNULL; + +/*----------------------------- Implementation ----------------------------*/ + +/* Functions to read and write CMOS registers */ + +uchar _ASMAPI _PM_readCMOS(int index); +void _ASMAPI _PM_writeCMOS(int index,uchar value); +void _ASMAPI _PM_rtcISR(void); +void _ASMAPI _PM_getISR(int irq,PMFARPTR *handler); +void _ASMAPI _PM_setISR(int irq,void *handler); +void _ASMAPI _PM_restoreISR(int irq,PMFARPTR *handler); +void _ASMAPI _PM_irqCodeStart(void); +void _ASMAPI _PM_irqCodeEnd(void); + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + static short convert[] = { + 8192, + 4096, + 2048, + 1024, + 512, + 256, + 128, + 64, + 32, + 16, + 8, + 4, + 2, + -1, + }; + int i; + + /* First clear any pending RTC timeout if not cleared */ + _PM_readCMOS(0x0C); + if (frequency == 0) { + /* Disable RTC timout */ + _PM_writeCMOS(0x0A,(uchar)_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,(uchar)(_PM_oldCMOSRegB & 0x0F)); + } + else { + /* Convert frequency value to RTC clock indexes */ + for (i = 0; convert[i] != -1; i++) { + if (convert[i] == frequency) + break; + } + + /* Set RTC timout value and enable timeout */ + _PM_writeCMOS(0x0A,(uchar)(0x20 | (i+3))); + _PM_writeCMOS(0x0B,(uchar)((_PM_oldCMOSRegB & 0x0F) | 0x40)); + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + static ibool locked = false; + + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Install the interrupt handler */ + RTC_idtEntry = 0x38; + _PM_getISR(RTC_idtEntry, &_PM_prevRTC); + _PM_rtcHandler = th; + _PM_setISR(RTC_idtEntry, _PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,(uchar)(_PM_oldRTCPIC2 & 0xFE)); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(uchar)((PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE))); + + /* Restore the interrupt vector */ + _PM_restoreISR(RTC_idtEntry, &_PM_prevRTC); + _PM_rtcHandler = NULL; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c new file mode 100644 index 000000000..3128c6ae3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/mem.c @@ -0,0 +1,518 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT device drivers. +* +* Description: Implementation for the NT driver memory management functions +* for the PM library. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" +#include "oshdr.h" + +/*--------------------------- Global variables ----------------------------*/ + +#define MAX_MEMORY_SHARED 100 +#define MAX_MEMORY_MAPPINGS 100 +#define MAX_MEMORY_LOCKED 100 + +typedef struct { + void *linear; + ulong length; + PMDL pMdl; + } memshared; + +typedef struct { + void *linear; + void *mmIoMapped; + ulong length; + PMDL pMdl; + } memlocked; + +typedef struct { + ulong physical; + ulong linear; + ulong length; + ibool isCached; + } mmapping; + +static int numMappings = 0; +static memshared shared[MAX_MEMORY_MAPPINGS] = {0}; +static mmapping maps[MAX_MEMORY_MAPPINGS]; +static memlocked locked[MAX_MEMORY_LOCKED]; + +/*----------------------------- Implementation ----------------------------*/ + +ulong PMAPI _PM_getPDB(void); + +/* Page table entry flags */ + +#define PAGE_FLAGS_PRESENT 0x00000001 +#define PAGE_FLAGS_WRITEABLE 0x00000002 +#define PAGE_FLAGS_USER 0x00000004 +#define PAGE_FLAGS_WRITE_THROUGH 0x00000008 +#define PAGE_FLAGS_CACHE_DISABLE 0x00000010 +#define PAGE_FLAGS_ACCESSED 0x00000020 +#define PAGE_FLAGS_DIRTY 0x00000040 +#define PAGE_FLAGS_4MB 0x00000080 + +/**************************************************************************** +PARAMETERS: +base - Physical base address of the memory to maps in +limit - Limit of physical memory to region to maps in + +RETURNS: +Linear address of the newly mapped memory. + +REMARKS: +Maps a physical memory range to a linear memory range. +****************************************************************************/ +static ulong _PM_mapPhysicalToLinear( + ulong base, + ulong limit, + ibool isCached) +{ + ulong length = limit+1; + PHYSICAL_ADDRESS paIoBase = {0}; + + /* NT loves large Ints */ + paIoBase = RtlConvertUlongToLargeInteger( base ); + + /* Map IO space into Kernel */ + if (isCached) + return (ULONG)MmMapIoSpace(paIoBase, length, MmCached ); + else + return (ULONG)MmMapIoSpace(paIoBase, length, MmNonCached ); +} + +/**************************************************************************** +REMARKS: +Adjust the page table caching bits directly. Requires ring 0 access and +only works with DOS4GW and compatible extenders (CauseWay also works since +it has direct support for the ring 0 instructions we need from ring 3). Will +not work in a DOS box, but we call into the ring 0 helper VxD so we should +never get here in a DOS box anyway (assuming the VxD is present). If we +do get here and we are in windows, this code will be skipped. +****************************************************************************/ +static void _PM_adjustPageTables( + ulong linear, + ulong limit, + ibool isGlobal, + ibool isCached) +{ + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong pageTable,*pPDB,*pPageTable; + ulong mask = 0xFFFFFFFF; + ulong bits = 0x00000000; + + /* Enable user level access for page table entry */ + if (isGlobal) { + mask &= ~PAGE_FLAGS_USER; + bits |= PAGE_FLAGS_USER; + } + + /* Disable PCD bit if page table entry should be uncached */ + if (!isCached) { + mask &= ~(PAGE_FLAGS_CACHE_DISABLE | PAGE_FLAGS_WRITE_THROUGH); + bits |= (PAGE_FLAGS_CACHE_DISABLE | PAGE_FLAGS_WRITE_THROUGH); + } + + pPDB = (ulong*)_PM_mapPhysicalToLinear(_PM_getPDB(),0xFFF,true); + if (pPDB) { + startPDB = (linear >> 22) & 0x3FF; + startPage = (linear >> 12) & 0x3FF; + endPDB = ((linear+limit) >> 22) & 0x3FF; + endPage = ((linear+limit) >> 12) & 0x3FF; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + /* Set the bits in the page directory entry - required as per */ + /* Pentium 4 manual. This also takes care of the 4MB page entries */ + pPDB[iPDB] = (pPDB[iPDB] & mask) | bits; + if (!(pPDB[iPDB] & PAGE_FLAGS_4MB)) { + /* If we are dealing with 4KB pages then we need to iterate */ + /* through each of the page table entries */ + pageTable = pPDB[iPDB] & ~0xFFF; + pPageTable = (ulong*)_PM_mapPhysicalToLinear(pageTable,0xFFF,true); + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FF; + for (iPage = start; iPage <= end; iPage++) { + pPageTable[iPage] = (pPageTable[iPage] & mask) | bits; + } + MmUnmapIoSpace(pPageTable,0xFFF); + } + } + MmUnmapIoSpace(pPDB,0xFFF); + PM_flushTLB(); + } +} + +/**************************************************************************** +REMARKS: +Allocate a block of shared memory. For NT we allocate shared memory +as locked, global memory that is accessible from any memory context +(including interrupt time context), which allows us to load our important +data structure and code such that we can access it directly from a ring +0 interrupt context. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + int i; + + /* First find a free slot in our shared memory table */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].linear == 0) + break; + } + if (i == MAX_MEMORY_SHARED) + return NULL; + + /* Allocate the paged pool */ + shared[i].linear = ExAllocatePool(PagedPool, size); + + /* Create a list to manage this allocation */ + shared[i].pMdl = IoAllocateMdl(shared[i].linear,size,FALSE,FALSE,(PIRP) NULL); + + /* Lock this allocation in memory */ + MmProbeAndLockPages(shared[i].pMdl,KernelMode,IoModifyAccess); + + /* Modify bits to grant user access */ + _PM_adjustPageTables((ulong)shared[i].linear, size, true, true); + return (void*)shared[i].linear; +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory +****************************************************************************/ +void PMAPI PM_freeShared( + void *p) +{ + int i; + + /* Find a shared memory block in our table and free it */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].linear == p) { + /* Unlock what we locked */ + MmUnlockPages(shared[i].pMdl); + + /* Free our MDL */ + IoFreeMdl(shared[i].pMdl); + + /* Free our mem */ + ExFreePool(shared[i].linear); + + /* Flag that is entry is available */ + shared[i].linear = 0; + break; + } + } +} + +/**************************************************************************** +REMARKS: +Map a physical address to a linear address in the callers process. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + ulong linear,length = limit+1; + int i; + + /* Search table of existing mappings to see if we have already mapped */ + /* a region of memory that will serve this purpose. */ + for (i = 0; i < numMappings; i++) { + if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached) { + _PM_adjustPageTables((ulong)maps[i].linear, maps[i].length, true, isCached); + return (void*)maps[i].linear; + } + } + if (numMappings == MAX_MEMORY_MAPPINGS) + return NULL; + + /* We did not find any previously mapped memory region, so maps it in. */ + if ((linear = _PM_mapPhysicalToLinear(base,limit,isCached)) == 0xFFFFFFFF) + return NULL; + maps[numMappings].physical = base; + maps[numMappings].length = length; + maps[numMappings].linear = linear; + maps[numMappings].isCached = isCached; + numMappings++; + + /* Grant user access to this I/O space */ + _PM_adjustPageTables((ulong)linear, length, true, isCached); + return (void*)linear; +} + +/**************************************************************************** +REMARKS: +Free a physical address mapping allocated by PM_mapPhysicalAddr. +****************************************************************************/ +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + /* We don't free the memory mappings in here because we cache all */ + /* the memory mappings we create in the system for later use. */ +} + +/**************************************************************************** +REMARKS: +Called when the device driver unloads to free all the page table mappings! +****************************************************************************/ +void PMAPI _PM_freeMemoryMappings(void) +{ + int i; + + for (i = 0; i < numMappings; i++) + MmUnmapIoSpace((void *)maps[i].linear,maps[i].length); +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ulong PMAPI PM_getPhysicalAddr( + void *p) +{ + PHYSICAL_ADDRESS paOurAddress; + + paOurAddress = MmGetPhysicalAddress(p); + return paOurAddress.LowPart; +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + int i; + ulong linear = (ulong)p & ~0xFFF; + + for (i = (length + 0xFFF) >> 12; i > 0; i--) { + if ((*physAddress++ = PM_getPhysicalAddr((void*)linear)) == 0xFFFFFFFF) + return false; + linear += 4096; + } + return true; +} + +/**************************************************************************** +REMARKS: +Allocates a block of locked physical memory. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + int i; + PHYSICAL_ADDRESS paOurAddress; + + /* First find a free slot in our shared memory table */ + for (i = 0; i < MAX_MEMORY_LOCKED; i++) { + if (locked[i].linear == 0) + break; + } + if (i == MAX_MEMORY_LOCKED) + return NULL; + + /* HighestAcceptableAddress - Specifies the highest valid physical address */ + /* the driver can use. For example, if a device can only reference physical */ + /* memory in the lower 16MB, this value would be set to 0x00000000FFFFFF. */ + paOurAddress.HighPart = 0; + if (below16M) + paOurAddress.LowPart = 0x00FFFFFF; + else + paOurAddress.LowPart = 0xFFFFFFFF; + + if (contiguous) { + /* Allocate from the non-paged pool (unfortunately 4MB pages) */ + locked[i].linear = MmAllocateContiguousMemory(size, paOurAddress); + if (!locked[i].linear) + return NULL; + + /* Flag no MDL */ + locked[i].pMdl = NULL; + + /* Map the physical address for the memory so we can manage */ + /* the page tables in 4KB chunks mapped into user space. */ + + /* TODO: Map this with the physical address to the linear addresss */ + locked[i].mmIoMapped = locked[i].linear; + + /* Modify bits to grant user access, flag not cached */ + _PM_adjustPageTables((ulong)locked[i].mmIoMapped, size, true, false); + return (void*)locked[i].mmIoMapped; + } + else { + /* Allocate from the paged pool */ + locked[i].linear = ExAllocatePool(PagedPool, size); + if (!locked[i].linear) + return NULL; + + /* Create a list to manage this allocation */ + locked[i].pMdl = IoAllocateMdl(locked[i].linear,size,FALSE,FALSE,(PIRP) NULL); + + /* Lock this allocation in memory */ + MmProbeAndLockPages(locked[i].pMdl,KernelMode,IoModifyAccess); + + /* Modify bits to grant user access, flag not cached */ + _PM_adjustPageTables((ulong)locked[i].linear, size, true, false); + return (void*)locked[i].linear; + } +} + +/**************************************************************************** +REMARKS: +Frees a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + int i; + + /* Find a locked memory block in our table and free it */ + for (i = 0; i < MAX_MEMORY_LOCKED; i++) { + if (locked[i].linear == p) { + /* An Mdl indicates that we used the paged pool, and locked it, */ + /* so now we have to unlock, free the MDL, and free paged */ + if (locked[i].pMdl) { + /* Unlock what we locked and free the Mdl */ + MmUnlockPages(locked[i].pMdl); + IoFreeMdl(locked[i].pMdl); + ExFreePool(locked[i].linear); + } + else { + /* TODO: Free the mmIoMap mapping for the memory! */ + + /* Free non-paged pool */ + MmFreeContiguousMemory(locked[i].linear); + } + + /* Flag that is entry is available */ + locked[i].linear = 0; + break; + } + } +} + +/**************************************************************************** +REMARKS: +Allocates a page aligned and page sized block of memory +****************************************************************************/ +void * PMAPI PM_allocPage( + ibool locked) +{ + /* Allocate the memory from the non-paged pool if we want the memory */ + /* to be locked. */ + return ExAllocatePool( + locked ? NonPagedPoolCacheAligned : PagedPoolCacheAligned, + PAGE_SIZE); +} + +/**************************************************************************** +REMARKS: +Free a page aligned and page sized block of memory +****************************************************************************/ +void PMAPI PM_freePage( + void *p) +{ + if (p) ExFreePool(p); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockDataPages( + void *p, + uint len, + PM_lockHandle *lh) +{ + MDL *pMdl; + + /* Create a list to manage this allocation */ + if ((pMdl = IoAllocateMdl(p,len,FALSE,FALSE,(PIRP)NULL)) == NULL) + return false; + + /* Lock this allocation in memory */ + MmProbeAndLockPages(pMdl,KernelMode,IoModifyAccess); + *((PMDL*)(&lh->h)) = pMdl; + return true; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockDataPages( + void *p, + uint len, + PM_lockHandle *lh) +{ + if (p && lh) { + /* Unlock what we locked */ + MDL *pMdl = *((PMDL*)(&lh->h)); + MmUnlockPages(pMdl); + IoFreeMdl(pMdl); + } + return true; +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lh) +{ + return PM_lockDataPages((void*)p,len,lh); +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lh) +{ + return PM_unlockDataPages((void*)p,len,lh); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h new file mode 100644 index 000000000..65b7bae23 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/oshdr.h @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT drivers +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#ifndef __NTDRV_OSHDR_H +#define __NTDRV_OSHDR_H + +/*--------------------------- Macros and Typedefs -------------------------*/ + +/*---------------------------- Global variables ---------------------------*/ + +/*--------------------------- Function Prototypes -------------------------*/ + +/* Internal unicode string handling functions */ + +UNICODE_STRING * _PM_CStringToUnicodeString(const char *cstr); +void _PM_FreeUnicodeString(UNICODE_STRING *uniStr); + +#endif /* __NTDRV_OSHDR_H */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c new file mode 100644 index 000000000..c6606314c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/pm.c @@ -0,0 +1,933 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT device drivers. +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" +#include "oshdr.h" + +/*--------------------------- Global variables ----------------------------*/ + +char _PM_cntPath[PM_MAX_PATH] = ""; +char _PM_nucleusPath[PM_MAX_PATH] = ""; +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +static char *szNTWindowsKey = "\\REGISTRY\\Machine\\Software\\Microsoft\\Windows NT\\CurrentVersion"; +static char *szNTSystemRoot = "SystemRoot"; +static char *szMachineNameKey = "\\REGISTRY\\Machine\\System\\CurrentControlSet\\control\\ComputerName\\ComputerName"; +static char *szMachineNameKeyNT = "\\REGISTRY\\Machine\\System\\CurrentControlSet\\control\\ComputerName\\ActiveComputerName"; +static char *szMachineName = "ComputerName"; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the PM library. +****************************************************************************/ +void PMAPI PM_init(void) +{ + /* Initialiase the MTRR module */ + MTRR_init(); +} + +/**************************************************************************** +REMARKS: +Return the operating system type identifier. +****************************************************************************/ +long PMAPI PM_getOSType(void) +{ + return _OS_WINNTDRV; +} + +/**************************************************************************** +REMARKS: +Return the runtime type identifier. +****************************************************************************/ +int PMAPI PM_getModeType(void) +{ + return PM_386; +} + +/**************************************************************************** +REMARKS: +Add a file directory separator to the end of the filename. +****************************************************************************/ +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +/**************************************************************************** +REMARKS: +Add a user defined PM_fatalError cleanup function. +****************************************************************************/ +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +/**************************************************************************** +REMARKS: +Handle fatal errors internally in the driver. +****************************************************************************/ +void PMAPI PM_fatalError( + const char *msg) +{ + ULONG BugCheckCode = 0; + ULONG MoreBugCheckData[4] = {0}; + char *p; + ULONG len; + + if (fatalErrorCleanup) + fatalErrorCleanup(); + +#ifdef DBG /* Send output to debugger, just return so as not to force a reboot */ +#pragma message("INFO: building for debug, PM_fatalError() re-routed") + DBGMSG2("SDDHELP> PM_fatalError(): ERROR: %s\n", msg); + return ; +#endif + /* KeBugCheckEx brings down the system in a controlled */ + /* manner when the caller discovers an unrecoverable */ + /* inconsistency that would corrupt the system if */ + /* the caller continued to run. */ + /* */ + /* hack - dump the first 20 chars in hex using the variables */ + /* provided - Each ULONG is equal to four characters... */ + for(len = 0; len < 20; len++) + if (msg[len] == (char)0) + break; + + /* This looks bad but it's quick and reliable... */ + p = (char *)&BugCheckCode; + if(len > 0) p[3] = msg[0]; + if(len > 1) p[2] = msg[1]; + if(len > 2) p[1] = msg[2]; + if(len > 3) p[0] = msg[3]; + + p = (char *)&MoreBugCheckData[0]; + if(len > 4) p[3] = msg[4]; + if(len > 5) p[2] = msg[5]; + if(len > 6) p[1] = msg[6]; + if(len > 7) p[0] = msg[7]; + + p = (char *)&MoreBugCheckData[1]; + if(len > 8) p[3] = msg[8]; + if(len > 9) p[2] = msg[9]; + if(len > 10) p[1] = msg[10]; + if(len > 11) p[0] = msg[11]; + + p = (char *)&MoreBugCheckData[2]; + if(len > 12) p[3] = msg[12]; + if(len > 13) p[2] = msg[13]; + if(len > 14) p[1] = msg[14]; + if(len > 15) p[0] = msg[15]; + + p = (char *)&MoreBugCheckData[3]; + if(len > 16) p[3] = msg[16]; + if(len > 17) p[2] = msg[17]; + if(len > 18) p[1] = msg[18]; + if(len > 19) p[0] = msg[19]; + + /* Halt the system! */ + KeBugCheckEx(BugCheckCode, MoreBugCheckData[0], MoreBugCheckData[1], MoreBugCheckData[2], MoreBugCheckData[3]); +} + +/**************************************************************************** +REMARKS: +Return the current operating system path or working directory. +****************************************************************************/ +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + strncpy(path,_PM_cntPath,maxLen); + path[maxLen-1] = 0; + return path; +} + +/**************************************************************************** +PARAMETERS: +szKey - Key to query (can contain version number formatting) +szValue - Value to get information for +value - Place to store the registry key data read +size - Size of the string buffer to read into + +RETURNS: +true if the key was found, false if not. +****************************************************************************/ +static ibool REG_queryString( + char *szKey, + const char *szValue, + char *value, + DWORD size) +{ + ibool status; + NTSTATUS rval; + ULONG length; + HANDLE Handle; + OBJECT_ATTRIBUTES keyAttributes; + UNICODE_STRING *uniKey = NULL; + UNICODE_STRING *uniValue = NULL; + PKEY_VALUE_FULL_INFORMATION fullInfo = NULL; + STRING stringdata; + UNICODE_STRING unidata; + + /* Convert strings to UniCode */ + status = false; + if ((uniKey = _PM_CStringToUnicodeString(szKey)) == NULL) + goto Exit; + if ((uniValue = _PM_CStringToUnicodeString(szValue)) == NULL) + goto Exit; + + /* Open the key */ + InitializeObjectAttributes( &keyAttributes, + uniKey, + OBJ_CASE_INSENSITIVE, + NULL, + NULL ); + rval = ZwOpenKey( &Handle, + KEY_ALL_ACCESS, + &keyAttributes ); + if (!NT_SUCCESS(rval)) + goto Exit; + + /* Query the value */ + length = sizeof (KEY_VALUE_FULL_INFORMATION) + + size * sizeof(WCHAR); + if ((fullInfo = ExAllocatePool (PagedPool, length)) == NULL) + goto Exit; + RtlZeroMemory(fullInfo, length); + rval = ZwQueryValueKey (Handle, + uniValue, + KeyValueFullInformation, + fullInfo, + length, + &length); + if (NT_SUCCESS (rval)) { + /* Create the UniCode string so we can convert it */ + unidata.Buffer = (PWCHAR)(((PCHAR)fullInfo) + fullInfo->DataOffset); + unidata.Length = (USHORT)fullInfo->DataLength; + unidata.MaximumLength = (USHORT)fullInfo->DataLength + sizeof(WCHAR); + + /* Convert unicode univalue to ansi string. */ + rval = RtlUnicodeStringToAnsiString(&stringdata, &unidata, TRUE); + if (NT_SUCCESS(rval)) { + strcpy(value,stringdata.Buffer); + status = true; + } + } + +Exit: + if (fullInfo) ExFreePool(fullInfo); + if (uniKey) _PM_FreeUnicodeString(uniKey); + if (uniValue) _PM_FreeUnicodeString(uniValue); + return status; +} + +/**************************************************************************** +REMARKS: +Return the drive letter for the boot drive. +****************************************************************************/ +char PMAPI PM_getBootDrive(void) +{ + char path[256]; + if (REG_queryString(szNTWindowsKey,szNTSystemRoot,path,sizeof(path))) + return 'c'; + return path[0]; +} + +/**************************************************************************** +REMARKS: +Return the path to the VBE/AF driver files. +****************************************************************************/ +const char * PMAPI PM_getVBEAFPath(void) +{ + return "c:\\"; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus driver files. +****************************************************************************/ +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[256]; + + if (strlen(_PM_nucleusPath) > 0) { + strcpy(path,_PM_nucleusPath); + PM_backslash(path); + return path; + } + if (!REG_queryString(szNTWindowsKey,szNTSystemRoot,path,sizeof(path))) + strcpy(path,"c:\\winnt"); + PM_backslash(path); + strcat(path,"system32\\nucleus"); + return path; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus configuration files. +****************************************************************************/ +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +/**************************************************************************** +REMARKS: +Return a unique identifier for the machine if possible. +****************************************************************************/ +const char * PMAPI PM_getUniqueID(void) +{ + return PM_getMachineName(); +} + +/**************************************************************************** +REMARKS: +Get the name of the machine on the network. +****************************************************************************/ +const char * PMAPI PM_getMachineName(void) +{ + static char name[256]; + + if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name))) + return name; + if (REG_queryString(szMachineNameKeyNT,szMachineName,name,sizeof(name))) + return name; + return "Unknown"; +} + +/**************************************************************************** +REMARKS: +Check if a key has been pressed. +****************************************************************************/ +int PMAPI PM_kbhit(void) +{ + /* Not used in NT drivers */ + return true; +} + +/**************************************************************************** +REMARKS: +Wait for and return the next keypress. +****************************************************************************/ +int PMAPI PM_getch(void) +{ + /* Not used in NT drivers */ + return 0xD; +} + +/**************************************************************************** +REMARKS: +Open a console for output to the screen, creating the main event handling +window if necessary. +****************************************************************************/ +PM_HWND PMAPI PM_openConsole( + PM_HWND hwndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ + /* Not used in NT drivers */ + (void)hwndUser; + (void)device; + (void)xRes; + (void)yRes; + (void)bpp; + (void)fullScreen; + return NULL; +} + +/**************************************************************************** +REMARKS: +Find the size of the console state buffer. +****************************************************************************/ +int PMAPI PM_getConsoleStateSize(void) +{ + /* Not used in NT drivers */ + return 1; +} + +/**************************************************************************** +REMARKS: +Save the state of the console. +****************************************************************************/ +void PMAPI PM_saveConsoleState( + void *stateBuf, + PM_HWND hwndConsole) +{ + /* Not used in NT drivers */ + (void)stateBuf; + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Set the suspend application callback for the fullscreen console. +****************************************************************************/ +void PMAPI PM_setSuspendAppCallback( + PM_saveState_cb saveState) +{ + /* Not used in NT drivers */ + (void)saveState; +} + +/**************************************************************************** +REMARKS: +Restore the console state. +****************************************************************************/ +void PMAPI PM_restoreConsoleState( + const void *stateBuf, + PM_HWND hwndConsole) +{ + /* Not used in NT drivers */ + (void)stateBuf; + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Close the fullscreen console. +****************************************************************************/ +void PMAPI PM_closeConsole( + PM_HWND hwndConsole) +{ + /* Not used in NT drivers */ + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Set the location of the OS console cursor. +****************************************************************************/ +void PMAPI PM_setOSCursorLocation( + int x, + int y) +{ + /* Nothing to do for Windows */ + (void)x; + (void)y; +} + +/**************************************************************************** +REMARKS: +Set the width of the OS console. +****************************************************************************/ +void PMAPI PM_setOSScreenWidth( + int width, + int height) +{ + /* Nothing to do for Windows */ + (void)width; + (void)height; +} + +/**************************************************************************** +REMARKS: +Maps a shared memory block into process address space. Does nothing since +the memory blocks are already globally mapped into all processes. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + /* Not used anymore */ + (void)base; + (void)limit; + return NULL; +} + +/**************************************************************************** +REMARKS: +Execute the POST on the secondary BIOS for a controller. +****************************************************************************/ +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + /* This may not be possible in NT and should be done by the OS anyway */ + (void)axVal; + (void)BIOSPhysAddr; + (void)mappedBIOS; + (void)BIOSLen; + return false; +} + +/**************************************************************************** +REMARKS: +Return a pointer to the real mode BIOS data area. +****************************************************************************/ +void * PMAPI PM_getBIOSPointer(void) +{ + /* Note that on NT this probably does not do what we expect! */ + return PM_mapPhysicalAddr(0x400, 0x1000, true); +} + +/**************************************************************************** +REMARKS: +Return a pointer to 0xA0000 physical VGA graphics framebuffer. +****************************************************************************/ +void * PMAPI PM_getA0000Pointer(void) +{ + return PM_mapPhysicalAddr(0xA0000,0xFFFF,false); +} + +/**************************************************************************** +REMARKS: +Sleep for the specified number of milliseconds. +****************************************************************************/ +void PMAPI PM_sleep( + ulong milliseconds) +{ + /* We never use this in NT drivers */ + (void)milliseconds; +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified COM port. +****************************************************************************/ +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + case 2: return 0x3E8; + case 3: return 0x2E8; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified LPT port. +****************************************************************************/ +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Returns available memory. Not possible under Windows. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* Not used in NT drivers */ + (void)szDLLName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* Not used in NT drivers */ + (void)hModule; + (void)szProcName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* Not used in NT drivers */ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + /* TODO: This function should start a directory enumeration search */ + /* given the filename (with wildcards). The data should be */ + /* converted and returned in the findData standard form. */ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + /* TODO: This function should find the next file in directory enumeration */ + /* search given the search criteria defined in the call to */ + /* PM_findFirstFile. The data should be converted and returned */ + /* in the findData standard form. */ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + /* TODO: This function should close the find process. This may do */ + /* nothing for some OS'es. */ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + /* Not supported in NT drivers */ + (void)drive; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + /* Not supported in NT drivers */ + (void)drive; + (void)dir; + (void)len; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ + return MTRR_enableWriteCombine(base,size,type); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + NTSTATUS status; + ACCESS_MASK DesiredAccess = GENERIC_READ | GENERIC_WRITE; + OBJECT_ATTRIBUTES ObjectAttributes; + ULONG ShareAccess = FILE_SHARE_READ; + ULONG CreateDisposition = FILE_OPEN; + HANDLE FileHandle = NULL; + UNICODE_STRING *uniFile = NULL; + IO_STATUS_BLOCK IoStatusBlock; + FILE_BASIC_INFORMATION FileBasic; + char kernelFilename[PM_MAX_PATH+5]; + ULONG FileAttributes = 0; + + /* Convert file attribute flags */ + if (attrib & PM_FILE_READONLY) + FileAttributes |= FILE_ATTRIBUTE_READONLY; + if (attrib & PM_FILE_ARCHIVE) + FileAttributes |= FILE_ATTRIBUTE_ARCHIVE; + if (attrib & PM_FILE_HIDDEN) + FileAttributes |= FILE_ATTRIBUTE_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + FileAttributes |= FILE_ATTRIBUTE_SYSTEM; + + /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */ + strcpy(kernelFilename, "\\??\\"); + strcat(kernelFilename, filename); + + /* Convert filename string to ansi string */ + if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL) + goto Exit; + + /* Must open a file to query it's attributes */ + InitializeObjectAttributes (&ObjectAttributes, + uniFile, + OBJ_CASE_INSENSITIVE, + NULL, + NULL ); + status = ZwCreateFile( &FileHandle, + DesiredAccess | SYNCHRONIZE, + &ObjectAttributes, + &IoStatusBlock, + NULL, /*AllocationSize OPTIONAL, */ + FILE_ATTRIBUTE_NORMAL, + ShareAccess, + CreateDisposition, + FILE_RANDOM_ACCESS, /*CreateOptions, */ + NULL, /*EaBuffer OPTIONAL, */ + 0 /*EaLength (required if EaBuffer) */ + ); + if (!NT_SUCCESS (status)) + goto Exit; + + /* Query timestamps */ + status = ZwQueryInformationFile(FileHandle, + &IoStatusBlock, + &FileBasic, + sizeof(FILE_BASIC_INFORMATION), + FileBasicInformation + ); + if (!NT_SUCCESS (status)) + goto Exit; + + /* Change the four bits we change */ + FileBasic.FileAttributes &= ~(FILE_ATTRIBUTE_READONLY | FILE_ATTRIBUTE_ARCHIVE + | FILE_ATTRIBUTE_HIDDEN | FILE_ATTRIBUTE_SYSTEM); + FileBasic.FileAttributes |= FileAttributes; + + /* Set timestamps */ + ZwSetInformationFile( FileHandle, + &IoStatusBlock, + &FileBasic, + sizeof(FILE_BASIC_INFORMATION), + FileBasicInformation + ); + +Exit: + if (FileHandle) ZwClose(FileHandle); + if (uniFile) _PM_FreeUnicodeString(uniFile); + return; +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + NTSTATUS status; + ACCESS_MASK DesiredAccess = GENERIC_READ | GENERIC_WRITE; + OBJECT_ATTRIBUTES ObjectAttributes; + ULONG ShareAccess = FILE_SHARE_READ; + ULONG CreateDisposition = FILE_OPEN; + HANDLE FileHandle = NULL; + UNICODE_STRING *uniFile = NULL; + IO_STATUS_BLOCK IoStatusBlock; + FILE_BASIC_INFORMATION FileBasic; + char kernelFilename[PM_MAX_PATH+5]; + ULONG FileAttributes = 0; + uint retval = 0; + + /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */ + strcpy(kernelFilename, "\\??\\"); + strcat(kernelFilename, filename); + + /* Convert filename string to ansi string */ + if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL) + goto Exit; + + /* Must open a file to query it's attributes */ + InitializeObjectAttributes (&ObjectAttributes, + uniFile, + OBJ_CASE_INSENSITIVE, + NULL, + NULL ); + status = ZwCreateFile( &FileHandle, + DesiredAccess | SYNCHRONIZE, + &ObjectAttributes, + &IoStatusBlock, + NULL, /*AllocationSize OPTIONAL, */ + FILE_ATTRIBUTE_NORMAL, + ShareAccess, + CreateDisposition, + FILE_RANDOM_ACCESS, /*CreateOptions, */ + NULL, /*EaBuffer OPTIONAL, */ + 0 /*EaLength (required if EaBuffer) */ + ); + if (!NT_SUCCESS (status)) + goto Exit; + + /* Query timestamps */ + status = ZwQueryInformationFile(FileHandle, + &IoStatusBlock, + &FileBasic, + sizeof(FILE_BASIC_INFORMATION), + FileBasicInformation + ); + if (!NT_SUCCESS (status)) + goto Exit; + + /* Translate the file attributes */ + if (FileBasic.FileAttributes & FILE_ATTRIBUTE_READONLY) + retval |= PM_FILE_READONLY; + if (FileBasic.FileAttributes & FILE_ATTRIBUTE_ARCHIVE) + retval |= PM_FILE_ARCHIVE; + if (FileBasic.FileAttributes & FILE_ATTRIBUTE_HIDDEN) + retval |= PM_FILE_HIDDEN; + if (FileBasic.FileAttributes & FILE_ATTRIBUTE_SYSTEM) + retval |= PM_FILE_SYSTEM; + +Exit: + if (FileHandle) ZwClose(FileHandle); + if (uniFile) _PM_FreeUnicodeString(uniFile); + return retval; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + /* Not supported in NT drivers */ + (void)filename; + return false; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + /* Not supported in NT drivers */ + (void)filename; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* Not supported in NT drivers */ + (void)filename; + (void)gmTime; + (void)time; + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* Not supported in NT drivers */ + (void)filename; + (void)gmTime; + (void)time; + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c new file mode 100644 index 000000000..658f1c80a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdio.c @@ -0,0 +1,330 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT driver +* +* Description: C library compatible I/O functions for use within a Windows +* NT driver. +* +****************************************************************************/ + +#include "pmapi.h" +#include "oshdr.h" + +/*------------------------ Main Code Implementation -----------------------*/ + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fopen function. +****************************************************************************/ +FILE * fopen( + const char *filename, + const char *mode) +{ + ACCESS_MASK DesiredAccess; /* for ZwCreateFile... */ + OBJECT_ATTRIBUTES ObjectAttributes; + ULONG ShareAccess; + ULONG CreateDisposition; + NTSTATUS status; + HANDLE FileHandle; + UNICODE_STRING *uniFile = NULL; + PWCHAR bufFile = NULL; + IO_STATUS_BLOCK IoStatusBlock; + FILE_STANDARD_INFORMATION FileInformation; + FILE_POSITION_INFORMATION FilePosition; + char kernelFilename[PM_MAX_PATH+5]; + FILE *f; + + /* Add prefix for addressing the file system. "\??\" is short for "\DosDevices\" */ + strcpy(kernelFilename, "\\??\\"); + strcat(kernelFilename, filename); + if ((f = PM_malloc(sizeof(FILE))) == NULL) + goto Error; + f->offset = 0; + f->text = (mode[1] == 't' || mode[2] == 't'); + f->writemode = (mode[0] == 'w') || (mode[0] == 'a'); + if (mode[0] == 'r') { + /* omode = OPEN_ACCESS_READONLY | OPEN_SHARE_COMPATIBLE; */ + /* action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_FAIL; */ + DesiredAccess = GENERIC_READ; + ShareAccess = FILE_SHARE_READ | FILE_SHARE_WRITE; + CreateDisposition = FILE_OPEN; + } + else if (mode[0] == 'w') { + /* omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_COMPATIBLE; */ + /* action = ACTION_IFEXISTS_TRUNCATE | ACTION_IFNOTEXISTS_CREATE; */ + DesiredAccess = GENERIC_WRITE; + ShareAccess = FILE_SHARE_READ | FILE_SHARE_WRITE; + CreateDisposition = FILE_SUPERSEDE; + } + else { + /* omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_COMPATIBLE; */ + /* action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_CREATE; */ + DesiredAccess = GENERIC_READ | GENERIC_WRITE; + ShareAccess = FILE_SHARE_READ; + CreateDisposition = FILE_OPEN_IF; + } + + /* Convert filename string to ansi string and then to UniCode string */ + if ((uniFile = _PM_CStringToUnicodeString(kernelFilename)) == NULL) + return NULL; + + /* Create the file */ + InitializeObjectAttributes (&ObjectAttributes, + uniFile, + OBJ_CASE_INSENSITIVE, + NULL, + NULL); + status = ZwCreateFile( &FileHandle, + DesiredAccess | SYNCHRONIZE, + &ObjectAttributes, + &IoStatusBlock, + NULL, /* AllocationSize OPTIONAL, */ + FILE_ATTRIBUTE_NORMAL, + ShareAccess, + CreateDisposition, + FILE_RANDOM_ACCESS, /* CreateOptions, */ + NULL, /* EaBuffer OPTIONAL, */ + 0 /* EaLength (required if EaBuffer) */ + ); + if (!NT_SUCCESS (status)) + goto Error; + f->handle = (int)FileHandle; + + /* Determine size of the file */ + status = ZwQueryInformationFile( FileHandle, + &IoStatusBlock, + &FileInformation, + sizeof(FILE_STANDARD_INFORMATION), + FileStandardInformation + ); + if (!NT_SUCCESS (status)) + goto Error; + f->filesize = FileInformation.EndOfFile.LowPart; + + /* Move to the end of the file if we are appending */ + if (mode[0] == 'a') { + FilePosition.CurrentByteOffset.HighPart = 0; + FilePosition.CurrentByteOffset.LowPart = f->filesize; + status = ZwSetInformationFile( FileHandle, + &IoStatusBlock, + &FilePosition, + sizeof(FILE_POSITION_INFORMATION), + FilePositionInformation + ); + if (!NT_SUCCESS (status)) + goto Error; + } + return f; + +Error: + if (f) PM_free(f); + if (uniFile) _PM_FreeUnicodeString(uniFile); + return NULL; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fread function. +****************************************************************************/ +size_t fread( + void *ptr, + size_t size, + size_t n, + FILE *f) +{ + NTSTATUS status; + IO_STATUS_BLOCK IoStatusBlock; + LARGE_INTEGER ByteOffset; + + /* Read any extra bytes from the file */ + ByteOffset.HighPart = 0; + ByteOffset.LowPart = f->offset; + status = ZwReadFile( (HANDLE)f->handle, + NULL, /*IN HANDLE Event OPTIONAL, */ + NULL, /* IN PIO_APC_ROUTINE ApcRoutine OPTIONAL, */ + NULL, /* IN PVOID ApcContext OPTIONAL, */ + &IoStatusBlock, + ptr, /* OUT PVOID Buffer, */ + size * n, /*IN ULONG Length, */ + &ByteOffset, /*OPTIONAL, */ + NULL /*IN PULONG Key OPTIONAL */ + ); + if (!NT_SUCCESS (status)) + return 0; + f->offset += IoStatusBlock.Information; + return IoStatusBlock.Information / size; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fwrite function. +****************************************************************************/ +size_t fwrite( + const void *ptr, + size_t size, + size_t n, + FILE *f) +{ + NTSTATUS status; + IO_STATUS_BLOCK IoStatusBlock; + LARGE_INTEGER ByteOffset; + + if (!f->writemode) + return 0; + ByteOffset.HighPart = 0; + ByteOffset.LowPart = f->offset; + status = ZwWriteFile( (HANDLE)f->handle, + NULL, /*IN HANDLE Event OPTIONAL, */ + NULL, /* IN PIO_APC_ROUTINE ApcRoutine OPTIONAL, */ + NULL, /* IN PVOID ApcContext OPTIONAL, */ + &IoStatusBlock, + (void*)ptr, /* OUT PVOID Buffer, */ + size * n, /*IN ULONG Length, */ + &ByteOffset, /*OPTIONAL, */ + NULL /*IN PULONG Key OPTIONAL */ + ); + if (!NT_SUCCESS (status)) + return 0; + f->offset += IoStatusBlock.Information; + if (f->offset > f->filesize) + f->filesize = f->offset; + return IoStatusBlock.Information / size; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fflush function. +****************************************************************************/ +int fflush( + FILE *f) +{ + /* Nothing to do here as we are not doing buffered I/O */ + (void)f; + return 0; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fseek function. +****************************************************************************/ +int fseek( + FILE *f, + long int offset, + int whence) +{ + NTSTATUS status; + FILE_POSITION_INFORMATION FilePosition; + IO_STATUS_BLOCK IoStatusBlock; + + if (whence == 0) + f->offset = offset; + else if (whence == 1) + f->offset += offset; + else if (whence == 2) + f->offset = f->filesize + offset; + FilePosition.CurrentByteOffset.HighPart = 0; + FilePosition.CurrentByteOffset.LowPart = f->offset; + status = ZwSetInformationFile( (HANDLE)f->handle, + &IoStatusBlock, + &FilePosition, + sizeof(FILE_POSITION_INFORMATION), + FilePositionInformation + ); + if (!NT_SUCCESS (status)) + return -1; + return 0; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C ftell function. +****************************************************************************/ +long ftell( + FILE *f) +{ + return f->offset; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C feof function. +****************************************************************************/ +int feof( + FILE *f) +{ + return (f->offset == f->filesize); +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fgets function. +****************************************************************************/ +char *fgets( + char *s, + int n, + FILE *f) +{ + int len; + char *cs; + + /* Read the entire buffer into memory (our functions are unbuffered!) */ + if ((len = fread(s,1,n,f)) == 0) + return NULL; + + /* Search for '\n' or end of string */ + if (n > len) + n = len; + cs = s; + while (--n > 0) { + if (*cs == '\n') + break; + cs++; + } + *cs = '\0'; + return s; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fputs function. +****************************************************************************/ +int fputs( + const char *s, + FILE *f) +{ + return fwrite(s,1,strlen(s),f); +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fclose function. +****************************************************************************/ +int fclose( + FILE *f) +{ + ZwClose((HANDLE)f->handle); + PM_free(f); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c new file mode 100644 index 000000000..bbf0cbf4a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/stdlib.c @@ -0,0 +1,139 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows NT driver +* +* Description: C library compatible stdlib.h functions for use within a +* Windows NT driver. +* +****************************************************************************/ + +#include "pmapi.h" +#include "oshdr.h" + +/*------------------------ Main Code Implementation -----------------------*/ + +/**************************************************************************** +REMARKS: +PM_malloc override function for Nucleus drivers loaded in NT drivers's. +****************************************************************************/ +void * malloc( + size_t size) +{ + return PM_mallocShared(size); +} + +/**************************************************************************** +REMARKS: +calloc library function for Nucleus drivers loaded in NT drivers's. +****************************************************************************/ +void * calloc( + size_t nelem, + size_t size) +{ + void *p = PM_mallocShared(nelem * size); + if (p) + memset(p,0,nelem * size); + return p; +} + +/**************************************************************************** +REMARKS: +PM_realloc override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void * realloc( + void *ptr, + size_t size) +{ + void *p = PM_mallocShared(size); + if (p) { + memcpy(p,ptr,size); + PM_freeShared(ptr); + } + return p; +} + +/**************************************************************************** +REMARKS: +PM_free override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void free( + void *p) +{ + PM_freeShared(p); +} + +/**************************************************************************** +PARAMETERS: +cstr - C style ANSI string to convert + +RETURNS: +Pointer to the UniCode string structure or NULL on failure to allocate memory + +REMARKS: +Converts a C style string to a UniCode string structure that can be passed +directly to NT kernel functions. +****************************************************************************/ +UNICODE_STRING *_PM_CStringToUnicodeString( + const char *cstr) +{ + int length; + ANSI_STRING ansiStr; + UNICODE_STRING *uniStr; + + /* Allocate memory for the string structure */ + if ((uniStr = ExAllocatePool(NonPagedPool, sizeof(UNICODE_STRING))) == NULL) + return NULL; + + /* Allocate memory for the wide string itself */ + length = (strlen(cstr) * sizeof(WCHAR)) + sizeof(WCHAR); + if ((uniStr->Buffer = ExAllocatePool(NonPagedPool, length)) == NULL) { + ExFreePool(uniStr); + return NULL; + } + RtlZeroMemory(uniStr->Buffer, length); + uniStr->Length = 0; + uniStr->MaximumLength = (USHORT)length; + + /* Convert filename string to ansi string and then to UniCode string */ + RtlInitAnsiString(&ansiStr, cstr); + RtlAnsiStringToUnicodeString(uniStr, &ansiStr, FALSE); + return uniStr; +} + +/**************************************************************************** +PARAMETERS: +uniStr - UniCode string structure to free + +REMARKS: +Frees a string allocated by the above _PM_CStringToUnicodeString function. +****************************************************************************/ +void _PM_FreeUnicodeString( + UNICODE_STRING *uniStr) +{ + if (uniStr) { + ExFreePool(uniStr->Buffer); + ExFreePool(uniStr); + } +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c new file mode 100644 index 000000000..901ce1cf0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/vflat.c @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c new file mode 100644 index 000000000..f4c4bd41b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ntdrv/ztimer.c @@ -0,0 +1,123 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static CPU_largeInteger countFreq; +static ulong start,finish; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +static void __ZTimerInit(void) +{ + KeQueryPerformanceCounter((LARGE_INTEGER*)&countFreq); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static void __LZTimerOn( + LZTimerObject *tm) +{ + LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL); + tm->start.low = lt.LowPart; + tm->start.high = lt.HighPart; +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + LARGE_INTEGER tmLap = KeQueryPerformanceCounter(NULL); + CPU_largeInteger tmCount; + + _CPU_diffTime64(&tm->start,(CPU_largeInteger*)&tmLap,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static void __LZTimerOff( + LZTimerObject *tm) +{ + LARGE_INTEGER lt = KeQueryPerformanceCounter(NULL); + tm->end.low = lt.LowPart; + tm->end.high = lt.HighPart; +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1 + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the BIOS timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + LARGE_INTEGER count; + KeQuerySystemTime(&count); + return (ulong)(*((_int64*)&count) / 10); +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm b/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm new file mode 100644 index 000000000..761f0f42e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/_pmos2.asm @@ -0,0 +1,180 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: OS/2 32 bit protected mode +;* +;* Description: Low level assembly support for the PM library specific +;* to OS/2 +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pmos2 ; Set up memory model + +begdataseg _pmos2 + + cglobal _PM_ioentry + cglobal _PM_gdt +_PM_ioentry dd 0 ; Offset to call gate +_PM_gdt dw 0 ; Selector to call gate + +enddataseg _pmos2 + +begcodeseg _pmos2 ; Start of code segment + +;---------------------------------------------------------------------------- +; int PM_setIOPL(int iopl) +;---------------------------------------------------------------------------- +; Change the IOPL level for the 32-bit task. Returns the previous level +; so it can be restored for the task correctly. +;---------------------------------------------------------------------------- +cprocstart PM_setIOPL + + ARG iopl:UINT + + enter_c + pushfd ; Save the old EFLAGS for later + mov ecx,[iopl] ; ECX := IOPL level + xor ebx,ebx ; Change IOPL level function code (0) +ifdef USE_NASM + call far dword [_PM_ioentry] +else + call [FWORD _PM_ioentry] +endif + pop eax + and eax,0011000000000000b + shr eax,12 + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_setGDTSelLimit(ushort selector, ulong limit); +;---------------------------------------------------------------------------- +; Change the GDT selector limit to given value. Used to change selector +; limits to address the entire system address space. +;---------------------------------------------------------------------------- +cprocstart _PM_setGDTSelLimit + + ARG selector:USHORT, limit:UINT + + enter_c + sub esp,20 ; Make room for selector data on stack + mov ecx,esp ; ECX := selector data structure + mov bx,[selector] ; Fill out the data structure + and bx,0FFF8h ; Kick out the LDT/GDT and DPL bits + mov [WORD ecx],bx + mov ebx,[limit] + mov [DWORD ecx+4],ebx + mov ebx,5 ; Set GDT selector limit function code +ifdef USE_NASM + call far dword [_PM_ioentry] +else + call [FWORD _PM_ioentry] +endif + add esp,20 + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_getCx86(uchar reg); +;---------------------------------------------------------------------------- +; Read a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_getCx86 + + ARG reg:UCHAR + + enter_c + mov al,[reg] + out 22h,al + in al,23h + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_setCx86(uchar reg,uchar val); +;---------------------------------------------------------------------------- +; Write a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_setCx86 + + ARG reg:UCHAR, val:UCHAR + + enter_c + mov al,[reg] + out 22h,al + mov al,[val] + out 23h,al + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _MTRR_disableInt(void); +;---------------------------------------------------------------------------- +; Return processor interrupt status and disable interrupts. +;---------------------------------------------------------------------------- +cprocstart _MTRR_disableInt + +; Do nothing! + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_restoreInt(ulong ps); +;---------------------------------------------------------------------------- +; Restore processor interrupt status. +;---------------------------------------------------------------------------- +cprocstart _MTRR_restoreInt + +; Do nothing! + ret + +cprocend + +;---------------------------------------------------------------------------- +; void DebugInt(void) +;---------------------------------------------------------------------------- +cprocstart DebugInt + + int 3 + ret + +cprocend + +endcodeseg _pmos2 + + END ; End of module + diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c new file mode 100644 index 000000000..7de400d06 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/cpuinfo.c @@ -0,0 +1,66 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: OS/2 +* +* Description: OS/2 specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +TODO: This should be implemented for OS/2! +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +TODO: This should be implemented for OS/2! +****************************************************************************/ +#define RestoreThreadPriority(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + freq->low = 100000; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + ULONG count; \ + DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) ); \ + (t)->low = count * 100; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj b/board/MAI/bios_emulator/scitech/src/pm/os2/dossctl.obj new file mode 100644 index 0000000000000000000000000000000000000000..5533346410ec6f20314d8a61bb302753005160fc GIT binary patch literal 59 zcmZqRX5e(mFAlCOb}q?z(jmpruz-;fA;RI}AMEVt;}e|2e7}Q(;lRI;$FDQ3-*hoC HFq8lQPdgO> literal 0 HcmV?d00001 diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/event.c b/board/MAI/bios_emulator/scitech/src/pm/os2/event.c new file mode 100644 index 000000000..91cc19b91 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/event.c @@ -0,0 +1,565 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: IBM PC (OS/2) +* +* Description: OS/2 implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +/* Define generous keyboard monitor circular buffer size to minimize + * the danger of losing keystrokes + */ +#define KEYBUFSIZE (EVENTQSIZE + 10) + +static int oldMouseState; /* Old mouse state */ +static ulong oldKeyMessage; /* Old keyboard state */ +static ushort keyUpMsg[256] = {0}; /* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ +HMOU _EVT_hMouse; /* Handle to the mouse driver */ +HMONITOR _EVT_hKbdMon; /* Handle to the keyboard driver */ +TID kbdMonTID = 0; /* Keyboard monitor thread ID */ +HEV hevStart; /* Start event semaphore handle */ +BOOL bMonRunning; /* Flag set if monitor thread OK */ +HMTX hmtxKeyBuf; /* Mutex protecting key buffer */ +KEYPACKET keyMonPkts[KEYBUFSIZE]; /* Array of monitor key packets */ +int kpHead = 0; /* Key packet buffer head */ +int kpTail = 0; /* Key packet buffer tail */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under OS/2 */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + ULONG count; + DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) ); + return count; +} + +/**************************************************************************** +REMARKS: +Converts a mickey movement value to a pixel adjustment value. +****************************************************************************/ +static int MickeyToPixel( + int mickey) +{ + /* TODO: We can add some code in here to handle 'acceleration' for */ + /* the mouse cursor. For now just use the mickeys. */ + return mickey; +} + +/* Some useful defines any typedefs used in the keyboard handling */ +#define KEY_RELEASE 0x40 + +/**************************************************************************** +REMARKS: +Pumps all messages in the message queue from OS/2 into our event queue. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + KBDINFO keyInfo; /* Must not cross a 64K boundary */ + KBDKEYINFO key; /* Must not cross a 64K boundary */ + MOUQUEINFO mqueue; /* Must not cross a 64K boundary */ + MOUEVENTINFO mouse; /* Must not cross a 64K boundary */ + ushort mWait; /* Must not cross a 64K boundary */ + KEYPACKET kp; /* Must not cross a 64K boundary */ + event_t evt; + int scan; + ibool noInput = TRUE; /* Flag to determine if any input was available */ + + /* First of all, check if we should do any session switch work */ + __PM_checkConsoleSwitch(); + + /* Pump all keyboard messages from our circular buffer */ + for (;;) { + /* Check that the monitor thread is still running */ + if (!bMonRunning) + PM_fatalError("Keyboard monitor thread died!"); + + /* Protect keypacket buffer with mutex */ + DosRequestMutexSem(hmtxKeyBuf, SEM_INDEFINITE_WAIT); + if (kpHead == kpTail) { + DosReleaseMutexSem(hmtxKeyBuf); + break; + } + + noInput = FALSE; + + /* Read packet from circular buffer and remove it */ + memcpy(&kp, &keyMonPkts[kpTail], sizeof(KEYPACKET)); + if (++kpTail == KEYBUFSIZE) + kpTail = 0; + DosReleaseMutexSem(hmtxKeyBuf); + + /* Compensate for the 0xE0 character */ + if (kp.XlatedScan && kp.XlatedChar == 0xE0) + kp.XlatedChar = 0; + + /* Determine type of keyboard event */ + memset(&evt,0,sizeof(evt)); + if (kp.KbdDDFlagWord & KEY_RELEASE) + evt.what = EVT_KEYUP; + else + evt.what = EVT_KEYDOWN; + + /* Convert keyboard codes */ + scan = kp.MonFlagWord >> 8; + if (evt.what == EVT_KEYUP) { + /* Get message for keyup code from table of cached down values */ + evt.message = keyUpMsg[scan]; + keyUpMsg[scan] = 0; + oldKeyMessage = -1; + } + else { + evt.message = ((ulong)scan << 8) | kp.XlatedChar; + if (evt.message == keyUpMsg[scan]) { + evt.what = EVT_KEYREPEAT; + evt.message |= 0x10000; + } + oldKeyMessage = evt.message & 0x0FFFF; + keyUpMsg[scan] = (ushort)evt.message; + } + + /* Convert shift state modifiers */ + if (kp.u.ShiftState & 0x0001) + evt.modifiers |= EVT_RIGHTSHIFT; + if (kp.u.ShiftState & 0x0002) + evt.modifiers |= EVT_LEFTSHIFT; + if (kp.u.ShiftState & 0x0100) + evt.modifiers |= EVT_LEFTCTRL; + if (kp.u.ShiftState & 0x0200) + evt.modifiers |= EVT_LEFTALT; + if (kp.u.ShiftState & 0x0400) + evt.modifiers |= EVT_RIGHTCTRL; + if (kp.u.ShiftState & 0x0800) + evt.modifiers |= EVT_RIGHTALT; + EVT.oldMove = -1; + + /* Add time stamp and add the event to the queue */ + evt.when = key.time; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Don't just flush because that terminally confuses the monitor */ + do { + KbdCharIn(&key, IO_NOWAIT, 0); + } while (key.fbStatus & KBDTRF_FINAL_CHAR_IN); + + /* Pump all mouse messages */ + KbdGetStatus(&keyInfo,0); + /* Check return code - mouse may not be operational!! */ + if (MouGetNumQueEl(&mqueue,_EVT_hMouse) == NO_ERROR) { + while (mqueue.cEvents) { + while (mqueue.cEvents--) { + memset(&evt,0,sizeof(evt)); + mWait = MOU_NOWAIT; + MouReadEventQue(&mouse,&mWait,_EVT_hMouse); + + /* Update the mouse position. We get the mouse coordinates + * in mickeys so we have to translate these into pixels and + * move our mouse position. If we don't do this, OS/2 gives + * us the coordinates in character positions since it still + * thinks we are in text mode! + */ + EVT.mx += MickeyToPixel(mouse.col); + EVT.my += MickeyToPixel(mouse.row); + if (EVT.mx < 0) EVT.mx = 0; + if (EVT.my < 0) EVT.my = 0; + if (EVT.mx > rangeX) EVT.mx = rangeX; + if (EVT.my > rangeY) EVT.my = rangeY; + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = mouse.col; + evt.relative_y = mouse.row; + evt.when = key.time; + if (mouse.fs & (MOUSE_BN1_DOWN | MOUSE_MOTION_WITH_BN1_DOWN)) + evt.modifiers |= EVT_LEFTBUT; + if (mouse.fs & (MOUSE_BN2_DOWN | MOUSE_MOTION_WITH_BN2_DOWN)) + evt.modifiers |= EVT_RIGHTBUT; + if (mouse.fs & (MOUSE_BN3_DOWN | MOUSE_MOTION_WITH_BN3_DOWN)) + evt.modifiers |= EVT_MIDDLEBUT; + if (keyInfo.fsState & 0x0001) + evt.modifiers |= EVT_RIGHTSHIFT; + if (keyInfo.fsState & 0x0002) + evt.modifiers |= EVT_LEFTSHIFT; + if (keyInfo.fsState & 0x0100) + evt.modifiers |= EVT_LEFTCTRL; + if (keyInfo.fsState & 0x0200) + evt.modifiers |= EVT_LEFTALT; + if (keyInfo.fsState & 0x0400) + evt.modifiers |= EVT_RIGHTCTRL; + if (keyInfo.fsState & 0x0800) + evt.modifiers |= EVT_RIGHTALT; + + /* Check for left mouse click events */ + /* 0x06 == (MOUSE_BN1_DOWN | MOUSE_MOTION_WITH_BN1_DOWN) */ + if (((mouse.fs & 0x0006) && !(oldMouseState & 0x0006)) + || (!(mouse.fs & 0x0006) && (oldMouseState & 0x0006))) { + if (mouse.fs & 0x0006) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_LEFTBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Check for right mouse click events */ + /* 0x0018 == (MOUSE_BN2_DOWN | MOUSE_MOTION_WITH_BN2_DOWN) */ + if (((mouse.fs & 0x0018) && !(oldMouseState & 0x0018)) + || (!(mouse.fs & 0x0018) && (oldMouseState & 0x0018))) { + if (mouse.fs & 0x0018) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_RIGHTBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Check for middle mouse click events */ + /* 0x0060 == (MOUSE_BN3_DOWN | MOUSE_MOTION_WITH_BN3_DOWN) */ + if (((mouse.fs & 0x0060) && !(oldMouseState & 0x0060)) + || (!(mouse.fs & 0x0060) && (oldMouseState & 0x0060))) { + if (mouse.fs & 0x0060) + evt.what = EVT_MOUSEDOWN; + else + evt.what = EVT_MOUSEUP; + evt.message = EVT_MIDDLEBMASK; + EVT.oldMove = -1; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + + /* Check for mouse movement event */ + if (mouse.fs & 0x002B) { + evt.what = EVT_MOUSEMOVE; + if (EVT.oldMove != -1) { + EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */ + EVT.evtq[EVT.oldMove].where_y = evt.where_y; + } + else { + EVT.oldMove = EVT.freeHead; /* Save id of this move event */ + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + } + + /* Save current mouse state */ + oldMouseState = mouse.fs; + } + MouGetNumQueEl(&mqueue,_EVT_hMouse); + } + noInput = FALSE; + } + + /* If there was no input available, give up the current timeslice + * Note: DosSleep(0) will effectively do nothing if no other thread is ready. Hence + * DosSleep(0) will still use 100% CPU _but_ should not interfere with other programs. + */ + if (noInput) + DosSleep(0); +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Keyboard monitor thread. Needed to catch both keyup and keydown events. +****************************************************************************/ +static void _kbdMonThread( + void *params) +{ + APIRET rc; + KEYPACKET kp; + USHORT count = sizeof(KEYPACKET); + MONBUF monInbuf; + MONBUF monOutbuf; + int kpNew; + + /* Raise thread priority for higher responsiveness */ + DosSetPriority(PRTYS_THREAD, PRTYC_TIMECRITICAL, 0, 0); + monInbuf.cb = sizeof(monInbuf) - sizeof(monInbuf.cb); + monOutbuf.cb = sizeof(monOutbuf) - sizeof(monOutbuf.cb); + bMonRunning = FALSE; + + /* Register the buffers to be used for monitoring for current session */ + if (DosMonReg(_EVT_hKbdMon, &monInbuf, (ULONG*)&monOutbuf,MONITOR_END, -1)) { + DosPostEventSem(hevStart); /* unblock the main thread */ + return; + } + + /* Unblock the main thread and tell it we're OK*/ + bMonRunning = TRUE; + DosPostEventSem(hevStart); + while (bMonRunning) { /* Start an endless loop */ + /* Read data from keyboard driver */ + rc = DosMonRead((PBYTE)&monInbuf, IO_WAIT, (PBYTE)&kp, (PUSHORT)&count); + if (rc) { +#ifdef CHECKED + if (bMonRunning) + printf("Error in DosMonRead, rc = %ld\n", rc); +#endif + bMonRunning = FALSE; + return; + } + + /* Pass FLUSH packets immediately */ + if (kp.MonFlagWord & 4) { +#ifdef CHECKED + printf("Flush packet!\n"); +#endif + DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count); + continue; + } + + /*TODO: to be removed */ + /* Skip extended scancodes & some others */ + if (((kp.MonFlagWord >> 8) == 0xE0) || ((kp.KbdDDFlagWord & 0x0F) == 0x0F)) { + DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count); + continue; + } + +/* printf("RawScan = %X, XlatedScan = %X, fbStatus = %X, KbdDDFlags = %X\n", */ +/* kp.MonFlagWord >> 8, kp.XlatedScan, kp.u.ShiftState, kp.KbdDDFlagWord); */ + + /* Protect access to buffer with mutex semaphore */ + rc = DosRequestMutexSem(hmtxKeyBuf, 1000); + if (rc) { +#ifdef CHECKED + printf("Can't get access to mutex, rc = %ld\n", rc); +#endif + bMonRunning = FALSE; + return; + } + + /* Store packet in circular buffer, drop it if it's full */ + kpNew = kpHead + 1; + if (kpNew == KEYBUFSIZE) + kpNew = 0; + if (kpNew != kpTail) { + memcpy(&keyMonPkts[kpHead], &kp, sizeof(KEYPACKET)); + /* TODO: fix this! */ + /* Convert break to make code */ + keyMonPkts[kpHead].MonFlagWord &= 0x7FFF; + kpHead = kpNew; + } + DosReleaseMutexSem(hmtxKeyBuf); + + /* Finally write the packet */ + rc = DosMonWrite((PBYTE)&monOutbuf, (PBYTE)&kp, count); + if (rc) { +#ifdef CHECKED + if (bMonRunning) + printf("Error in DosMonWrite, rc = %ld\n", rc); +#endif + bMonRunning = FALSE; + return; + } + } + (void)params; +} + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort( + int signal) +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + ushort stat; + + /* Initialise the event queue */ + PM_init(); + EVT.mouseMove = mouseMove; + initEventQueue(); + oldMouseState = 0; + oldKeyMessage = 0; + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* Open the mouse driver, and set it up to report events in mickeys */ + MouOpen(NULL,&_EVT_hMouse); + stat = 0x7F; + MouSetEventMask(&stat,_EVT_hMouse); + stat = (MOU_NODRAW | MOU_MICKEYS) << 8; + MouSetDevStatus(&stat,_EVT_hMouse); + + /* Open the keyboard monitor */ + if (DosMonOpen((PSZ)"KBD$", &_EVT_hKbdMon)) + PM_fatalError("Unable to open keyboard monitor!"); + + /* Create event semaphore, the monitor will post it when it's initalized */ + if (DosCreateEventSem(NULL, &hevStart, 0, FALSE)) + PM_fatalError("Unable to create event semaphore!"); + + /* Create mutex semaphore protecting the keypacket buffer */ + if (DosCreateMutexSem(NULL, &hmtxKeyBuf, 0, FALSE)) + PM_fatalError("Unable to create mutex semaphore!"); + + /* Start keyboard monitor thread, use 32K stack */ + kbdMonTID = _beginthread(_kbdMonThread, NULL, 0x8000, NULL); + + /* Now block until the monitor thread is up and running */ + /* Give the thread one second */ + DosWaitEventSem(hevStart, 1000); + if (!bMonRunning) { /* Check the thread is OK */ + DosMonClose(_EVT_hKbdMon); + PM_fatalError("Keyboard monitor thread didn't initialize!"); + } + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +#define _EVT_setMousePos(x,y) + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for OS/2 */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for OS/2 */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + APIRET rc; + + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* Close the mouse driver */ + MouClose(_EVT_hMouse); + + /* Stop the keyboard monitor thread and close the monitor */ + bMonRunning = FALSE; + rc = DosKillThread(kbdMonTID); +#ifdef CHECKED + if (rc) + printf("DosKillThread failed, rc = %ld\n", rc); +#endif + rc = DosMonClose(_EVT_hKbdMon); +#ifdef CHECKED + if (rc) { + printf("DosMonClose failed, rc = %ld\n", rc); + } +#endif + DosCloseEventSem(hevStart); + DosCloseMutexSem(hmtxKeyBuf); + KbdFlushBuffer(0); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h b/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h new file mode 100644 index 000000000..28d39fba4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/mon.h @@ -0,0 +1,165 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 +* +* Description: Include file to include all OS/2 keyboard monitor stuff. +* +****************************************************************************/ + +/* Monitors stuff */ + +#define MONITOR_DEFAULT 0x0000 +#define MONITOR_BEGIN 1 +#define MONITOR_END 2 + +typedef SHANDLE HMONITOR; +typedef HMONITOR *PHMONITOR; + +typedef struct _KEYPACKET { + USHORT MonFlagWord; + UCHAR XlatedChar; + UCHAR XlatedScan; + UCHAR DBCSStatus; + UCHAR DBCSShift; + + union + { + USHORT ShiftState; + USHORT LayerIndex; + } u; + + ULONG Milliseconds; + USHORT KbdDDFlagWord; +} KEYPACKET; + +typedef struct _MLNPACKET { + USHORT MonFlagWord; + USHORT IOCTL; + USHORT CPId; + USHORT CPIndex; + ULONG Reserved; + USHORT KbdDDFlagWord; +} MLNPACKET; + +/* DBCSStatus */ + +#define SF_SHIFTS 1 /* If set to 1, shift status returned without a character */ +#define SF_NOTCHAR 2 /* 0 - Scan code is a character */ + /* 1 - Scan code is not a character; */ + /* instead it is an extended key code from the keyboard. */ +#define SF_IMMEDIATE 32 /* If set to 1, immediate conversion requested */ +#define SF_TYPEMASK 192 /* Has the following values: */ + /* 00 - Undefined */ + /* 01 - Final character; interim character flag is turned off */ + /* 10 - Interim character */ + /* 11 - Final character; interim character flag is turned on. */ +/* MonFlagWord */ + +#define MF_OPEN 1 /* open */ +#define MF_CLOSE 2 /* close */ +#define MF_FLUSH 4 /* is flush packet */ + +/* KbdDDFlagWord */ + +#define KF_NOTSQPACKET 1024 /* Don't put this packet in SQ buffer */ +#define KF_ACCENTEDKEY 512 /* Key was translated using previous accent. */ +#define KF_MULTIMAKE 256 /* Key was repeated make of a toggle key. */ +#define KF_SECONDARYKEY 128 /* Previous scan code was the E0 prefix code. */ +#define KF_KEYBREAK 64 /* This is the break of the key. */ +#define KF_KEYTYPEMASK 63 /* Isolates the Key Type field of DDFlags. */ +#define KF_UNDEFKEY 63 /* Key packet is undefined */ +#define KF_SYSREQKEY 23 /* This key packet is the SysReq key (4990) */ +#define KF_PRINTFLUSHKEY 22 /* This packet is Ct-Alt-PrtScr */ +#define KF_PSPRINTECHOKEY 21 /* This packet is Ctl-P */ +#define KF_PRINTECHOKEY 20 /* This packet is Ctl-PrtScr */ +#define KF_PRTSCRKEY 19 /* This packet is PrtScr */ +#define KF_PSBREAKKEY 18 /* This packet is Ctl-C */ +#define KF_BREAKKEY 17 /* This packet is Ctl-Break */ +#define KF_ACCENTKEY 16 /* This packet is an accent key */ +#define KF_XRORPNOT 13 /* This packet is a Read or Peek Notification Pct. */ +#define KF_MLNOTIFICATION 14 /* packet is a Multi-Layer NLS packet */ +#define KF_HOTKEYPACKET 12 /* This packet is the hot key. */ +#define KF_BADKEYCOMBO 11 /* Accent/char combo undefined, beep only. */ +#define KF_WAKEUPKEY 10 /* This packet is one following PAUSEKEY */ +#define KF_PSPAUSEKEY 9 /* This packet is Ctl-S */ +#define KF_PAUSEKEY 8 /* This packet is Ctl-Numlock or PAUSE */ +#define KF_SHIFTMASK 7 /* Key is a shift Key */ +#define KF_DUMPKEY 6 /* This packet is Ctl-Numlock-NumLock */ +#define KF_REBOOTKEY 5 /* This packet is Ctl-Alt-Del */ +#define KF_RESENDCODE 4 /* This packet is resend code from controller */ +#define KF_OVERRUNCODE 3 /* This packet is overrun code from controller */ +#define KF_SECPREFIXCODE 2 /* This packet is E0/E1 scan code */ +#define KF_ACKCODE 1 /* This packet is ack code from keyboard */ + + +typedef struct _MONBUF { + USHORT cb; + KEYPACKET Buffer; + BYTE Reserved[20]; +} MONBUF; + +#define RS_SYSREG 32768 /* Bit 15 SysReq key down */ +#define RS_CAPSLOCK 16384 /* Bit 14 Caps Lock key down */ +#define RS_NUMLOCK 8192 /* Bit 13 NumLock key down */ +#define RS_SCROLLLOCK 4096 /* Bit 12 Scroll Lock key down */ +#define RS_RALT 2048 /* Bit 11 Right Alt key down */ +#define RS_RCONTROL 1024 /* Bit 10 Right Ctrl key down */ +#define RS_LALT 512 /* Bit 9 Left Alt key down */ +#define RS_LCONTROL 256 /* Bit 8 Left Ctrl key down */ +#define RS_INSERT 128 /* Bit 7 Insert on */ +#define RS_CAPS 64 /* Bit 6 Caps Lock on */ +#define RS_NUM 32 /* Bit 5 NumLock on */ +#define RS_SCROLL 16 /* Bit 4 Scroll Lock on */ +#define RS_ALT 8 /* Bit 3 Either Alt key down */ +#define RS_CONTROL 4 /* Bit 2 Either Ctrl key down */ +#define RS_LSHIFT 2 /* Bit 1 Left Shift key down */ +#define RS_RSHIFT 1 /* Bit 0 Right Shift key down */ + + +#define CS_RCONTROL 91 /* Right Control */ +#define CS_LSHIFT 42 /* Left Shift */ +#define CS_RSHIFT 54 /* Right Shift */ +#define CS_LALT 56 /* Left Alt */ +#define CS_RALT 94 /* Right Alt */ + + +/* DosMon* prototypes */ +#ifdef __EMX__ + #define APIRET16 USHORT + #define APIENTRY16 +#else + #define DosMonOpen DOS16MONOPEN + #define DosMonClose DOS16MONCLOSE + #define DosMonReg DOS16MONREG + #define DosMonRead DOS16MONREAD + #define DosMonWrite DOS16MONWRITE + #define DosGetInfoSeg DOS16GETINFOSEG +#endif + +APIRET16 APIENTRY16 DosMonOpen (PSZ pszDevName, PHMONITOR phmon); +APIRET16 APIENTRY16 DosMonClose (HMONITOR hmon); +APIRET16 APIENTRY16 DosMonReg (HMONITOR hmon, MONBUF *pbInBuf, /*MONBUF*/ULONG *pbOutBuf, USHORT fPosition, USHORT usIndex); +APIRET16 APIENTRY16 DosMonRead (PBYTE pbInBuf, USHORT fWait, PBYTE pbDataBuf, PUSHORT pcbData); +APIRET16 APIENTRY16 DosMonWrite (PBYTE pbOutBuf, PBYTE pbDataBuf, USHORT cbData); diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h new file mode 100644 index 000000000..e7aa1c676 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/oshdr.h @@ -0,0 +1,41 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#define INCL_DOSPROFILE +#define INCL_DOSERRORS +#define INCL_DOS +#define INCL_SUB +#define INCL_VIO +#define INCL_KBD +#include +#include +#include "os2/mon.h" + +void __PM_checkConsoleSwitch(void); diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c b/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c new file mode 100644 index 000000000..756eead1d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/pm.c @@ -0,0 +1,2008 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "pm_help.h" +#include "mtrr.h" +#include +#include +#include +#include +#ifndef __EMX__ +#include +#endif +#define INCL_DOSERRORS +#define INCL_DOS +#define INCL_SUB +#define INCL_VIO +#define INCL_KBD +#include + +/* Semaphore for communication with our background daemon */ +#define SHAREDSEM ((PSZ)"\\SEM32\\SDD\\DAEMON") +#define DAEMON_NAME "SDDDAEMN.EXE" + +/*--------------------------- Global variables ----------------------------*/ + +/* Public structures used to communicate with VIDEOPMI for implementing + * the ability to call the real mode BIOS functions. + */ + +typedef struct _VIDEOMODEINFO { + ULONG miModeId; + USHORT usType; + USHORT usInt10ModeSet; + USHORT usXResolution; + USHORT usYResolution; + ULONG ulBufferAddress; + ULONG ulApertureSize; + BYTE bBitsPerPixel; + BYTE bBitPlanes; + BYTE bXCharSize; + BYTE bYCharSize; + USHORT usBytesPerScanLine; + USHORT usTextRows; + ULONG ulPageLength; + ULONG ulSaveSize; + BYTE bVrtRefresh; + BYTE bHrtRefresh; + BYTE bVrtPolPos; + BYTE bHrtPolPos; + CHAR bRedMaskSize; + CHAR bRedFieldPosition; + CHAR bGreenMaskSize; + CHAR bGreenFieldPosition; + CHAR bBlueMaskSize; + CHAR bBlueFieldPosition; + CHAR bRsvdMaskSize; + CHAR bRsvdFieldPosition; + ULONG ulColors; + ULONG ulReserved[3]; + } VIDEOMODEINFO, FAR *PVIDEOMODEINFO; + +typedef struct _ADAPTERINFO { + ULONG ulAdapterID; + CHAR szOEMString[128]; + CHAR szDACString[128]; + CHAR szRevision[128]; + ULONG ulTotalMemory; + ULONG ulMMIOBaseAddress; + ULONG ulPIOBaseAddress; + BYTE bBusType; + BYTE bEndian; + USHORT usDeviceBusID; + USHORT usVendorBusID; + USHORT SlotID; + } ADAPTERINFO, FAR *PADAPTERINFO; + +typedef struct _VIDEO_ADAPTER { + void *hvideo; + ADAPTERINFO Adapter; + VIDEOMODEINFO ModeInfo; + } VIDEO_ADAPTER, FAR *PVIDEO_ADAPTER; + +/* PMIREQUEST_SOFTWAREINT structures from OS/2 DDK */ + +typedef struct { + ULONG ulFlags; /* VDM initialization type */ +#define VDM_POSTLOAD 0x1 /* adapter just loaded, used internally for initialization */ +#define VDM_INITIALIZE 0x2 /* force initialization of a permanently open VDM, even if previously initialized */ +#define VDM_TERMINATE_POSTINITIALIZE 0x6 /*start VDM with initialization, but close it afterwards (includes VDM_INITIALIZE) */ +#define VDM_QUERY_CAPABILITY 0x10 /* query the current int 10 capability */ +#define VDM_FULL_VDM_CREATED 0x20 /* a full VDM is created */ +#define VDM_MINI_VDM_CREATED 0x40 /* a mini VDM is created */ +#define VDM_MINI_VDM_SUPPORTED 0x80 /* mini VDM support is available */ + PCHAR szName; /* VDM initialization program */ + PCHAR szArgs; /* VDM initialization arguments */ + }INITVDM; + +typedef struct { + BYTE bBufferType; +#define BUFFER_NONE 0 +#define INPUT_BUFFER 1 +#define OUTPUT_BUFFER 2 + BYTE bReserved; + BYTE bSelCRF; + BYTE bOffCRF; + PVOID pAddress; + ULONG ulSize; + } BUFFER, *PBUFFER; + +typedef struct vcrf_s { + ULONG reg_eax; + ULONG reg_ebx; + ULONG reg_ecx; + ULONG reg_edx; + ULONG reg_ebp; + ULONG reg_esi; + ULONG reg_edi; + ULONG reg_ds; + ULONG reg_es; + ULONG reg_fs; + ULONG reg_gs; + ULONG reg_cs; + ULONG reg_eip; + ULONG reg_eflag; + ULONG reg_ss; + ULONG reg_esp; + } VCRF; + +typedef struct { + ULONG ulBIOSIntNo; + VCRF aCRF; + BUFFER pB[2]; + } INTCRF; + +#define PMIREQUEST_LOADPMIFILE 21 +#define PMIREQUEST_IDENTIFYADAPTER 22 +#define PMIREQUEST_SOFTWAREINT 23 + +#ifdef PTR_DECL_IN_FRONT +#define EXPENTRYP * EXPENTRY +#else +#define EXPENTRYP EXPENTRY * +#endif + +/* Entry point to VIDEOPMI32Request. This may be overridden by external + * code that has already loaded VIDEOPMI to avoid loading it twice. + */ + +APIRET (EXPENTRYP PM_VIDEOPMI32Request)(PVIDEO_ADAPTER, ULONG, PVOID, PVOID) = NULL; +static ibool haveInt10 = -1; /* True if we have Int 10 support */ +static ibool useVPMI = true; /* False if VIDEOPMI unavailable */ +static VIDEO_ADAPTER Adapter; /* Video adapter for VIDEOPMI */ +static uchar RMBuf[1024]; /* Fake real mode transfer buffer */ +static uint VESABuf_len = 1024;/* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL;/* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +static uchar * lowMem = NULL; +static ibool isSessionSwitching = false; +static ulong parmsIn[4]; /* Must not cross 64Kb boundary! */ +static ulong parmsOut[4]; /* Must not cross 64Kb boundary! */ +extern ushort _PM_gdt; +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/* DosSysCtl prototype. It is not declared in the headers but it is in the + * standard import libraries (DOSCALLS.876). Funny. + */ +APIRET APIENTRY DosSysCtl(ULONG ulFunction, PVOID pvData); + +/* This is the stack size for the threads that track the session switch event */ +#define SESSION_SWITCH_STACK_SIZE 32768 + +typedef struct { + VIOMODEINFO vmi; + USHORT CursorX; + USHORT CursorY; + UCHAR FrameBuffer[1]; + } CONSOLE_SAVE; + +typedef struct _SESWITCHREC { + /* The following variable is volatile because of PM_SUSPEND_APP */ + volatile int Flags; /* -1 or PM_DEACTIVATE or PM_REACTIVATE */ + PM_saveState_cb Callback; /* Save/restore context callback */ + HMTX Mutex; /* Exclusive access mutex */ + HEV Event; /* Posted after callback is called */ + } SESWITCHREC; + +/* Page sized block cache */ + +#define PAGES_PER_BLOCK 32 +#define PAGE_BLOCK_SIZE (PAGES_PER_BLOCK * PM_PAGE_SIZE + (PM_PAGE_SIZE-1) + sizeof(pageblock)) +#define FREELIST_NEXT(p) (*(void**)(p)) +typedef struct pageblock { + struct pageblock *next; + struct pageblock *prev; + void *freeListStart; + void *freeList; + void *freeListEnd; + int freeCount; + PM_lockHandle lockHandle; + } pageblock; + +static pageblock *pageBlocks = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +func - Helper device driver function to call + +RETURNS: +First return value from the device driver in parmsOut[0] + +REMARKS: +Function to open our helper device driver, call it and close the file +handle. Note that we have to open the device driver for every call because +of two problems: + + 1. We cannot open a single file handle in a DLL that is shared amongst + programs, since every process must have it's own open file handle. + + 2. For some reason there appears to be a limit of about 12 open file + handles on a device driver in the system. Hence when we open more + than about 12 file handles things start to go very strange. + +Hence we simply open the file handle every time that we need to call the +device driver to work around these problems. +****************************************************************************/ +static ulong CallSDDHelp( + int func) +{ + static ulong inLen; /* Must not cross 64Kb boundary! */ + static ulong outLen; /* Must not cross 64Kb boundary! */ + HFILE hSDDHelp; + ULONG rc; + ulong result; + + if ((rc = DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0, + FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, + NULL)) != 0) { + if (rc == 4) { /* Did we run out of file handles? */ + ULONG ulNewFHs; + LONG lAddFHs = 5; + + if (DosSetRelMaxFH(&lAddFHs, &ulNewFHs) != 0) + PM_fatalError("Failed to raise the file handles limit!"); + else { + if ((rc = DosOpen(PMHELP_NAME,&hSDDHelp,&result,0,0, + FILE_OPEN, OPEN_SHARE_DENYNONE | OPEN_ACCESS_READWRITE, + NULL)) != 0) { + PM_fatalError("Unable to open SDDHELP$ helper device driver! (#2)"); + } + } + } + else + PM_fatalError("Unable to open SDDHELP$ helper device driver!"); + } + if (DosDevIOCtl(hSDDHelp,PMHELP_IOCTL,func, + &parmsIn, inLen = sizeof(parmsIn), &inLen, + &parmsOut, outLen = sizeof(parmsOut), &outLen) != 0) + PM_fatalError("Failure calling SDDHELP$ helper device driver!"); + DosClose(hSDDHelp); + return parmsOut[0]; +} + +/**************************************************************************** +REMARKS: +Determine if we're running on a DBCS system. +****************************************************************************/ +ibool __IsDBCSSystem(void) +{ + CHAR achDBCSInfo[12]; + COUNTRYCODE ccStruct = {0, 0}; + + memset(achDBCSInfo, 0, 12); + + /* Get the DBCS vector - if it's not empty, we're on DBCS */ + DosQueryDBCSEnv(sizeof(achDBCSInfo), &ccStruct, achDBCSInfo); + if (achDBCSInfo[0] != 0) + return true; + else + return false; +} + +/**************************************************************************** +REMARKS: +Determine if PMSHELL is running - if it isn't, we can't use certain calls +****************************************************************************/ +ibool __isShellLoaded(void) +{ + PVOID ptr; + + if (DosGetNamedSharedMem(&ptr, (PSZ)"\\SHAREMEM\\PMGLOBAL.MEM", PAG_READ) == NO_ERROR) { + DosFreeMem(ptr); + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +Initialise the PM library and connect to our helper device driver. If we +cannot connect to our helper device driver, we bail out with an error +message. +****************************************************************************/ +void PMAPI PM_init(void) +{ + if (!lowMem) { + /* Obtain the 32->16 callgate from the device driver to enable IOPL */ + if ((_PM_gdt = CallSDDHelp(PMHELP_GETGDT32)) == 0) + PM_fatalError("Unable to obtain call gate selector!"); + + PM_setIOPL(3); + + /* Map the first Mb of physical memory into lowMem */ + if ((lowMem = PM_mapPhysicalAddr(0,0xFFFFF,true)) == NULL) + PM_fatalError("Unable to map first Mb physical memory!"); + + /* Initialise the MTRR interface functions */ + MTRR_init(); + } +} + +/**************************************************************************** +REMARKS: +Initialise the PM library for BIOS access via VIDEOPMI. This should work +with any GRADD driver, including SDD/2. +****************************************************************************/ +static ibool InitInt10(void) +{ + HMODULE hModGENPMI,hModSDDPMI,hModVideoPMI; + CHAR buf[80],path[_MAX_PATH]; + HEV hevDaemon = NULLHANDLE; + RESULTCODES resCodes; + + if (haveInt10 == -1) { + /* Connect to VIDEOPMI and get entry point. Note that we only + * do this if GENPMI or SDDPMI are already loaded, since we need + * a GRADD based driver for this to work. + */ + PM_init(); + haveInt10 = false; + if (DosQueryModuleHandle((PSZ)"GENPMI.DLL",&hModGENPMI) != 0) + hModGENPMI = NULLHANDLE; + if (DosQueryModuleHandle((PSZ)"SDDPMI.DLL",&hModSDDPMI) != 0) + hModSDDPMI = NULLHANDLE; + if (hModGENPMI || hModSDDPMI) { + if (DosLoadModule((PSZ)buf,sizeof(buf),(PSZ)"VIDEOPMI.DLL",&hModVideoPMI) == 0) { + if (DosQueryProcAddr(hModVideoPMI,0,(PSZ)"VIDEOPMI32Request",(void*)&PM_VIDEOPMI32Request) != 0) + PM_fatalError("Unable to get VIDEOPMI32Request entry point!"); + strcpy(path,"X:\\OS2\\SVGADATA.PMI"); + path[0] = PM_getBootDrive(); + if (PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_LOADPMIFILE,path,NULL) != 0) { + DosFreeModule(hModVideoPMI); + PM_VIDEOPMI32Request = NULL; + haveInt10 = false; + } + else { + /* Attempt to initialise the full VDM in the system. This will only + * work if VPRPMI.SYS is loaded, but it provides support for passing + * values in ES/DS/ESI/EDI between the BIOS which does not work with + * kernel VDM's in fixpacks earlier than FP15. FP15 and later and + * the new Warp 4.51 and Warp Server convenience packs should work + * fine with the kernel mini-VDM. + * + * Also the full VDM is the only solution for really old kernels + * (but GRADD won't run on them so this is superfluous ;-). + */ + INITVDM InitVDM = {VDM_INITIALIZE,NULL,NULL}; + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&InitVDM,NULL); + haveInt10 = true; + } + } + } + else { + /* A GRADD driver isn't loaded, hence we can't use VIDEOPMI. But we will try + * to access the mini-VDM directly, first verifying that the support is + * available in the kernel (it should be for kernels that support GRADD). + * This may be needed in a command line boot or if non-GRADD driver is + * used (Matrox or classic VGA). + * Note: because of problems with mini-VDM support in the kernel, we have to + * spawn a daemon process that will do the actual mini-VDM access for us. + */ + /* Try to open shared semaphore to see if our daemon is already up */ + if (DosOpenEventSem(SHAREDSEM, &hevDaemon) == NO_ERROR) { + if (DosWaitEventSem(hevDaemon, 1) == NO_ERROR) { + /* If semaphore is posted, all is well */ + useVPMI = false; + haveInt10 = true; + } + } + else { + /* Create shared event semaphore */ + if (DosCreateEventSem(SHAREDSEM, &hevDaemon, DC_SEM_SHARED, FALSE) == NO_ERROR) { + PM_findBPD(DAEMON_NAME, path); + strcat(path, DAEMON_NAME); + if (DosExecPgm(buf, sizeof(buf), EXEC_BACKGROUND, (PSZ)DAEMON_NAME, + NULL, &resCodes, (PSZ)path) == NO_ERROR) { + /* The daemon was successfully spawned, now give it a sec to come up */ + if (DosWaitEventSem(hevDaemon, 2000) == NO_ERROR) { + /* It's up! */ + useVPMI = false; + haveInt10 = true; + } + } + } + } + } + } + return haveInt10; +} + +/**************************************************************************** +REMARKS: +We "probably" have BIOS access under OS/2 but we have to verify/initialize it +first. +****************************************************************************/ +ibool PMAPI PM_haveBIOSAccess(void) +{ + return InitInt10(); +} + +/**************************************************************************** +REMARKS: +Return the operating system type identifier. +****************************************************************************/ +long PMAPI PM_getOSType(void) +{ + return _OS_OS2; +} + +/**************************************************************************** +REMARKS: +Return the runtime type identifier. +****************************************************************************/ +int PMAPI PM_getModeType(void) +{ + return PM_386; +} + +/**************************************************************************** +REMARKS: +Add a file directory separator to the end of the filename. +****************************************************************************/ +void PMAPI PM_backslash( + char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +/**************************************************************************** +REMARKS: +Add a user defined PM_fatalError cleanup function. +****************************************************************************/ +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +/**************************************************************************** +REMARKS: +Report a fatal error condition and halt the program. +****************************************************************************/ +void PMAPI PM_fatalError( + const char *msg) +{ + /* Be prepare to be called recursively (failed to fail situation :-) */ + static int fatalErrorCount = 0; + if (fatalErrorCount++ == 0) { + if (fatalErrorCleanup) + fatalErrorCleanup(); + } + fprintf(stderr,"%s\n", msg); + exit(1); +} + +/**************************************************************************** +REMARKS: +Allocate the real mode VESA transfer buffer for communicating with the BIOS. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +/**************************************************************************** +REMARKS: +Check if a key has been pressed. +****************************************************************************/ +int PMAPI PM_kbhit(void) +{ + KBDKEYINFO key; /* Must not cross a 64K boundary */ + + KbdPeek(&key, 0); + return (key.fbStatus & KBDTRF_FINAL_CHAR_IN); +} + +/**************************************************************************** +REMARKS: +Wait for and return the next keypress. +****************************************************************************/ +int PMAPI PM_getch(void) +{ + KBDKEYINFO key; /* Must not cross a 64K boundary */ + + KbdCharIn(&key,IO_WAIT,0); + return key.chChar; +} + +/**************************************************************************** +REMARKS: +Open a fullscreen console for output to the screen. This requires that +the application be a fullscreen VIO program. +****************************************************************************/ +PM_HWND PMAPI PM_openConsole( + PM_HWND hwndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ + (void)hwndUser; + (void)device; + (void)xRes; + (void)yRes; + (void)bpp; + (void)fullScreen; + return 0; +} + +/**************************************************************************** +REMARKS: +Find the size of the console state buffer. +****************************************************************************/ +int PMAPI PM_getConsoleStateSize(void) +{ + VIOMODEINFO vmi; + vmi.cb = sizeof (VIOMODEINFO); + VioGetMode (&vmi, (HVIO)0); + return sizeof (CONSOLE_SAVE) - 1 + vmi.col * vmi.row * 2; +} + +/**************************************************************************** +REMARKS: +Save the state of the console. +****************************************************************************/ +void PMAPI PM_saveConsoleState( + void *stateBuf, + PM_HWND hwndConsole) +{ + USHORT fblen; + CONSOLE_SAVE *cs = (CONSOLE_SAVE*)stateBuf; + VIOMODEINFO vmi; + + /* The reason for the VIOMODEINFO juggling is 16-bit code. Because the user + * allocates the state buffer, cd->vmi might be crossing the 64K boundary and + * the 16-bit API would fail. If we create another copy on stack, the compiler + * should ensure that the 64K boundary will not be crossed (it adjusts the stack + * if it should cross). + */ + vmi.cb = sizeof(VIOMODEINFO); + VioGetMode(&vmi,(HVIO)0); + memcpy(&cs->vmi, &vmi, sizeof(VIOMODEINFO)); + VioGetCurPos(&cs->CursorY, &cs->CursorX, (HVIO)0); + fblen = cs->vmi.col * cs->vmi.row * 2; + VioReadCellStr((PCH)cs->FrameBuffer, &fblen, 0, 0, (HVIO)0); +} + +/* Global variable to communicate between threads */ +static SESWITCHREC SesSwitchRec = { -1 }; + +/**************************************************************************** +REMARKS: +Called by external routines at least once per frame to check whenever a +session save/restore should be performed. Since we receive such notifications +asyncronously, we can't perform all required operations at that time. +****************************************************************************/ +void __PM_checkConsoleSwitch(void) +{ + int Flags, Mode; + PM_saveState_cb Callback; + + /* Quick optimized path for most common case */ + if (SesSwitchRec.Flags == -1) + return; + +again: + if (DosRequestMutexSem(SesSwitchRec.Mutex, 100)) + return; + Flags = SesSwitchRec.Flags; + Callback = SesSwitchRec.Callback; + SesSwitchRec.Flags = -1; + DosReleaseMutexSem(SesSwitchRec.Mutex); + + isSessionSwitching = true; /* Prevent VIO calls */ + Mode = Callback(Flags); + isSessionSwitching = false; + DosPostEventSem(SesSwitchRec.Event); + if (Flags == PM_DEACTIVATE && Mode == PM_SUSPEND_APP) + /* Suspend application until we switch back to our application */ + for (;;) { + DosSleep (500); + /* SesSwitchRec.Flags is volatile so optimizer + * won't load it into a register + */ + if (SesSwitchRec.Flags != -1) + goto again; + } +} + +/**************************************************************************** +REMARKS: +Waits until main thread processes the session switch event. +****************************************************************************/ +static void _PM_SessionSwitchEvent( + PM_saveState_cb saveState, + int flags) +{ + ULONG Count; + + if (DosRequestMutexSem(SesSwitchRec.Mutex, 10000)) + return; + + /* We're going to wait on that semaphore */ + DosResetEventSem(SesSwitchRec.Event, &Count); + SesSwitchRec.Callback = saveState; + SesSwitchRec.Flags = flags; + DosReleaseMutexSem(SesSwitchRec.Mutex); + + /* Now wait until all required operations are complete */ + DosWaitEventSem (SesSwitchRec.Event, 10000); +} + +/**************************************************************************** +REMARKS: +This is the thread responsible for tracking switches back to our +fullscreen session. +****************************************************************************/ +static void _PM_ConsoleSwitch( + PM_saveState_cb saveState) +{ + USHORT NotifyType; + + for (;;) { + if (VioModeWait(VMWR_POPUP, &NotifyType, 0) != 0) + break; + _PM_SessionSwitchEvent(saveState, PM_REACTIVATE); + } + VioModeUndo(UNDOI_RELEASEOWNER, UNDOK_ERRORCODE, (HVIO)0); +} + +/**************************************************************************** +REMARKS: +This is the thread responsible for tracking screen popups (usually fatal +error handler uses them). +****************************************************************************/ +static void _PM_ConsolePopup( + PM_saveState_cb saveState) +{ + USHORT NotifyType; + for (;;) { + if (VioSavRedrawWait(VSRWI_SAVEANDREDRAW, &NotifyType, 0) != 0) + break; + if (NotifyType == VSRWN_SAVE) + _PM_SessionSwitchEvent(saveState, PM_DEACTIVATE); + else if (NotifyType == VSRWN_REDRAW) + _PM_SessionSwitchEvent(saveState, PM_REACTIVATE); + } + VioSavRedrawUndo(UNDOI_RELEASEOWNER, UNDOK_ERRORCODE, (HVIO)0); +} + +/**************************************************************************** +REMARKS: +Set the suspend application callback for the fullscreen console. +****************************************************************************/ +void PMAPI PM_setSuspendAppCallback( + PM_saveState_cb saveState) +{ + /* If PM isn't loaded, this stuff will cause crashes! */ + if (__isShellLoaded()) { + if (saveState) { + /* Create the threads responsible for tracking console switches */ + SesSwitchRec.Flags = -1; + DosCreateMutexSem(NULL, &SesSwitchRec.Mutex, 0, FALSE); + DosCreateEventSem(NULL, &SesSwitchRec.Event, 0, FALSE); + _beginthread ((void(*)(void*))_PM_ConsoleSwitch,NULL,SESSION_SWITCH_STACK_SIZE, (void*)saveState); + _beginthread ((void(*)(void*))_PM_ConsolePopup,NULL,SESSION_SWITCH_STACK_SIZE, (void*)saveState); + } + else { + /* Kill the threads responsible for tracking console switches */ + VioModeUndo(UNDOI_RELEASEOWNER, UNDOK_TERMINATE, (HVIO)0); + VioSavRedrawUndo(UNDOI_RELEASEOWNER, UNDOK_TERMINATE, (HVIO)0); + DosCloseEventSem(SesSwitchRec.Event); + DosCloseMutexSem(SesSwitchRec.Mutex); + } + } +} + +/**************************************************************************** +REMARKS: +Restore the console state. +****************************************************************************/ +void PMAPI PM_restoreConsoleState( + const void *stateBuf, + PM_HWND hwndConsole) +{ + CONSOLE_SAVE *cs = (CONSOLE_SAVE *)stateBuf; + VIOMODEINFO vmi; + + if (!cs) + return; + + memcpy(&vmi, &cs->vmi, sizeof (VIOMODEINFO)); + VioSetMode(&vmi, (HVIO)0); + VioSetCurPos(cs->CursorY, cs->CursorX, (HVIO)0); + VioWrtCellStr((PCH)cs->FrameBuffer, cs->vmi.col * cs->vmi.row * 2,0, 0, (HVIO)0); +} + +/**************************************************************************** +REMARKS: +Close the fullscreen console. +****************************************************************************/ +void PMAPI PM_closeConsole( + PM_HWND hwndConsole) +{ + /* Kill the threads responsible for tracking console switches */ + PM_setSuspendAppCallback(NULL); + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Set the location of the OS console cursor. +****************************************************************************/ +void PM_setOSCursorLocation( + int x, + int y) +{ + /* If session switch is in progress, calling into VIO causes deadlocks! */ + /* Also this call to VIO screws up our console library on DBCS boxes... */ + if (!isSessionSwitching && !__IsDBCSSystem()) + VioSetCurPos(y,x,0); +} + +/**************************************************************************** +REMARKS: +Set the width of the OS console. +****************************************************************************/ +void PM_setOSScreenWidth( + int width, + int height) +{ + /* Nothing to do in here */ + (void)width; + (void)height; +} + +/**************************************************************************** +REMARKS: +Set the real time clock handler (used for software stereo modes). +****************************************************************************/ +ibool PMAPI PM_setRealTimeClockHandler( + PM_intHandler ih, + int frequency) +{ + /* TODO: Implement this! */ + (void)ih; + (void)frequency; + return false; +} + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + /* TODO: Implement this! */ + (void)frequency; +} + +/**************************************************************************** +REMARKS: +Restore the original real time clock handler. +****************************************************************************/ +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* TODO: Implement this! */ +} + +/**************************************************************************** +REMARKS: +Return the current operating system path or working directory. +****************************************************************************/ +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +/**************************************************************************** +REMARKS: +Return the drive letter for the boot drive. +****************************************************************************/ +char PMAPI PM_getBootDrive(void) +{ + ulong boot = 3; + DosQuerySysInfo(QSV_BOOT_DRIVE,QSV_BOOT_DRIVE,&boot,sizeof(boot)); + return (char)('a' + boot - 1); +} + +/**************************************************************************** +REMARKS: +Return the path to the VBE/AF driver files. +****************************************************************************/ +const char * PMAPI PM_getVBEAFPath(void) +{ + static char path[CCHMAXPATH]; + strcpy(path,"x:\\"); + path[0] = PM_getBootDrive(); + return path; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus driver files. +****************************************************************************/ +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[CCHMAXPATH]; + if (getenv("NUCLEUS_PATH") != NULL) + return getenv("NUCLEUS_PATH"); + strcpy(path,"x:\\os2\\drivers"); + path[0] = PM_getBootDrive(); + PM_backslash(path); + strcat(path,"nucleus"); + return path; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus configuration files. +****************************************************************************/ +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[CCHMAXPATH]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +/**************************************************************************** +REMARKS: +Return a unique identifier for the machine if possible. +****************************************************************************/ +const char * PMAPI PM_getUniqueID(void) +{ + return PM_getMachineName(); +} + +/**************************************************************************** +REMARKS: +Get the name of the machine on the network. +****************************************************************************/ +const char * PMAPI PM_getMachineName(void) +{ + static char name[40],*env; + + if ((env = getenv("HOSTNAME")) != NULL) { + strncpy(name,env,sizeof(name)); + name[sizeof(name)-1] = 0; + return name; + } + return "OS2"; +} + +/**************************************************************************** +REMARKS: +Return a pointer to the real mode BIOS data area. +****************************************************************************/ +void * PMAPI PM_getBIOSPointer(void) +{ + PM_init(); + return lowMem + 0x400; +} + +/**************************************************************************** +REMARKS: +Return a pointer to 0xA0000 physical VGA graphics framebuffer. +****************************************************************************/ +void * PMAPI PM_getA0000Pointer(void) +{ + PM_init(); + return lowMem + 0xA0000; +} + +/**************************************************************************** +REMARKS: +Map a physical address to a linear address in the callers process. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + ulong baseAddr,baseOfs,linear; + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to mmap. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + baseOfs = base & 4095; + baseAddr = base & ~4095; + limit = ((limit+baseOfs+1+4095) & ~4095)-1; + parmsIn[0] = baseAddr; + parmsIn[1] = limit; + parmsIn[2] = isCached; + if ((linear = CallSDDHelp(PMHELP_MAPPHYS)) == 0) + return NULL; + return (void*)(linear + baseOfs); +} + +/**************************************************************************** +REMARKS: +Free a physical address mapping allocated by PM_mapPhysicalAddr. +****************************************************************************/ +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + parmsIn[0] = (ulong)ptr; + parmsIn[1] = limit; + CallSDDHelp(PMHELP_FREEPHYS); +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ulong PMAPI PM_getPhysicalAddr( + void *p) +{ + parmsIn[0] = (ulong)p; + return CallSDDHelp(PMHELP_GETPHYSICALADDR); +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + parmsIn[0] = (ulong)p; + parmsIn[1] = (ulong)length; + parmsIn[2] = (ulong)physAddress; + return CallSDDHelp(PMHELP_GETPHYSICALADDRRANGE); +} + +/**************************************************************************** +REMARKS: +Sleep for the specified number of milliseconds. +****************************************************************************/ +void PMAPI PM_sleep( + ulong milliseconds) +{ + DosSleep(milliseconds); +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified COM port. +****************************************************************************/ +int PMAPI PM_getCOMPort( + int port) +{ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified LPT port. +****************************************************************************/ +int PMAPI PM_getLPTPort( + int port) +{ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of shared memory. For Win9x we allocate shared memory +as locked, global memory that is accessible from any memory context +(including interrupt time context), which allows us to load our important +data structure and code such that we can access it directly from a ring +0 interrupt context. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + parmsIn[0] = size; + return (void*)CallSDDHelp(PMHELP_MALLOCSHARED); +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory. +****************************************************************************/ +void PMAPI PM_freeShared( + void *ptr) +{ + parmsIn[0] = (ulong)ptr; + CallSDDHelp(PMHELP_FREESHARED); +} + +/**************************************************************************** +REMARKS: +Map a linear memory address to the calling process address space. The +address will have been allocated in another process using the +PM_mapPhysicalAddr function. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + ulong baseAddr,baseOfs; + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to mmap. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + baseOfs = (ulong)base & 4095; + baseAddr = (ulong)base & ~4095; + limit = ((limit+baseOfs+1+4095) & ~4095)-1; + parmsIn[0] = (ulong)baseAddr; + parmsIn[1] = limit; + return (void*)(CallSDDHelp(PMHELP_MAPTOPROCESS)+baseOfs); +} + +/**************************************************************************** +REMARKS: +Map a real mode pointer to a protected mode pointer. +****************************************************************************/ +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + if (r_seg == 0xFFFF) + return &RMBuf[r_off]; + return lowMem + MK_PHYS(r_seg,r_off); +} + +/**************************************************************************** +REMARKS: +Allocate a block of real mode memory +****************************************************************************/ +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + if (size > sizeof(RMBuf)) + return NULL; + *r_seg = 0xFFFF; + *r_off = 0x0000; + return &RMBuf; +} + +/**************************************************************************** +REMARKS: +Free a block of real mode memory. +****************************************************************************/ +void PMAPI PM_freeRealSeg( + void *mem) +{ + /* Nothing to do in here */ + (void)mem; +} + +#define INDPMI(reg) rmregs.aCRF.reg_##reg = regs->reg +#define OUTDPMI(reg) regs->reg = rmregs.aCRF.reg_##reg + +#define REG_OFFSET(field) (((ULONG)&(((VCRF*)0)->field)) / sizeof(ULONG)) + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt (parameters in DPMI compatible structure) +****************************************************************************/ +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + INTCRF rmregs; + ulong eax = 0; + + if (!InitInt10()) + return; + memset(&rmregs, 0, sizeof(rmregs)); + rmregs.ulBIOSIntNo = intno; + INDPMI(eax); INDPMI(ebx); INDPMI(ecx); INDPMI(edx); INDPMI(esi); INDPMI(edi); + rmregs.aCRF.reg_ds = regs->ds; + rmregs.aCRF.reg_es = regs->es; + if (intno == 0x10) { + eax = rmregs.aCRF.reg_eax; + switch (eax & 0xFFFF) { + case 0x4F00: + /* We have to hack the way this function works, due to + * some bugs in the IBM mini-VDM BIOS support. Specifically + * we need to make the input buffer and output buffer the + * 'same' buffer, and that ES:SI points to the output + * buffer (ignored by the BIOS). The data will end up + * being returned in the input buffer, except for the + * first four bytes ('VESA') that will not be returned. + */ + rmregs.pB[0].bBufferType = INPUT_BUFFER; + rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); + rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); + rmregs.pB[0].pAddress = RMBuf; + rmregs.pB[0].ulSize = 4; + rmregs.pB[1].bBufferType = OUTPUT_BUFFER; + rmregs.pB[1].bSelCRF = REG_OFFSET(reg_es); + rmregs.pB[1].bOffCRF = REG_OFFSET(reg_esi); + rmregs.pB[1].pAddress = ((PBYTE)RMBuf)+4; + rmregs.pB[1].ulSize = 512-4; + break; + case 0x4F01: + rmregs.pB[0].bBufferType = OUTPUT_BUFFER; + rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); + rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); + rmregs.pB[0].pAddress = RMBuf; + rmregs.pB[0].ulSize = 256; + break; + case 0x4F02: + rmregs.pB[0].bBufferType = INPUT_BUFFER; + rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); + rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); + rmregs.pB[0].pAddress = RMBuf; + rmregs.pB[0].ulSize = 256; + break; + case 0x4F09: + rmregs.pB[0].bBufferType = INPUT_BUFFER; + rmregs.pB[0].bSelCRF = REG_OFFSET(reg_es); + rmregs.pB[0].bOffCRF = REG_OFFSET(reg_edi); + rmregs.pB[0].pAddress = RMBuf; + rmregs.pB[0].ulSize = 1024; + break; + case 0x4F0A: + /* Due to bugs in the mini-VDM in OS/2, the 0x4F0A protected + * mode interface functions will not work (we never get any + * selectors returned), so we fail this function here. The + * rest of the VBE/Core driver will work properly if this + * function is failed, because the VBE 2.0 and 3.0 specs + * allow for this. + */ + regs->eax = 0x014F; + return; + } + } + if (useVPMI) + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,NULL,&rmregs); + else { + DosSysCtl(6, &rmregs); + } + + OUTDPMI(eax); OUTDPMI(ebx); OUTDPMI(ecx); OUTDPMI(edx); OUTDPMI(esi); OUTDPMI(edi); + if (((regs->eax & 0xFFFF) == 0x004F) && ((eax & 0xFFFF) == 0x4F00)) { + /* Hack to fix up the missing 'VESA' string for mini-VDM */ + memcpy(RMBuf,"VESA",4); + } + regs->ds = rmregs.aCRF.reg_ds; + regs->es = rmregs.aCRF.reg_es; + regs->flags = rmregs.aCRF.reg_eflag; +} + +#define IN(reg) rmregs.reg = in->e.reg +#define OUT(reg) out->e.reg = rmregs.reg + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + DPMI_int86(intno,&rmregs); + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + rmregs.es = sregs->es; + rmregs.ds = sregs->ds; + DPMI_int86(intno,&rmregs); + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + sregs->es = rmregs.es; + sregs->cs = rmregs.cs; + sregs->ss = rmregs.ss; + sregs->ds = rmregs.ds; + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +/**************************************************************************** +REMARKS: +Call a real mode far function. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *in, + RMSREGS *sregs) +{ + PM_fatalError("PM_callRealMode not supported on OS/2!"); +} + +/**************************************************************************** +REMARKS: +Return the amount of available memory. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + /* Unable to get reliable values from OS/2 for this */ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of locked, physical memory for DMA operations. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + parmsIn[0] = size; + parmsIn[1] = contiguous; + parmsIn[2] = below16M; + CallSDDHelp(PMHELP_ALLOCLOCKED); + *physAddr = parmsOut[1]; + return (void*)parmsOut[0]; +} + +/**************************************************************************** +REMARKS: +Free a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + parmsIn[0] = (ulong)p; + CallSDDHelp(PMHELP_FREELOCKED); +} + +/**************************************************************************** +REMARKS: +Allocates a new block of pages for the page block manager. +****************************************************************************/ +static pageblock *PM_addNewPageBlock(void) +{ + int i; + pageblock *newBlock; + char *p,*next; + + /* Allocate memory for the new page block, and add to head of list */ + if (DosAllocSharedMem((void**)&newBlock,NULL,PAGE_BLOCK_SIZE,OBJ_GETTABLE | PAG_READ | PAG_WRITE | PAG_COMMIT)) + return NULL; + if (!PM_lockDataPages(newBlock,PAGE_BLOCK_SIZE,&newBlock->lockHandle)) + return NULL; + newBlock->prev = NULL; + newBlock->next = pageBlocks; + if (pageBlocks) + pageBlocks->prev = newBlock; + pageBlocks = newBlock; + + /* Initialise the page aligned free list for the page block */ + newBlock->freeCount = PAGES_PER_BLOCK; + newBlock->freeList = p = (char*)(((ulong)(newBlock + 1) + (PM_PAGE_SIZE-1)) & ~(PM_PAGE_SIZE-1)); + newBlock->freeListStart = newBlock->freeList; + newBlock->freeListEnd = p + (PAGES_PER_BLOCK-1) * PM_PAGE_SIZE; + for (i = 0; i < PAGES_PER_BLOCK; i++,p = next) + FREELIST_NEXT(p) = next = p + PM_PAGE_SIZE; + FREELIST_NEXT(p - PM_PAGE_SIZE) = NULL; + return newBlock; +} + +/**************************************************************************** +REMARKS: +Allocates a page aligned and page sized block of memory +****************************************************************************/ +void * PMAPI PM_allocPage( + ibool locked) +{ + pageblock *block; + void *p; + + /* Scan the block list looking for any free blocks. Allocate a new + * page block if no free blocks are found. + */ + for (block = pageBlocks; block != NULL; block = block->next) { + if (block->freeCount) + break; + } + if (block == NULL && (block = PM_addNewPageBlock()) == NULL) + return NULL; + block->freeCount--; + p = block->freeList; + block->freeList = FREELIST_NEXT(p); + (void)locked; + return p; +} + +/**************************************************************************** +REMARKS: +Free a page aligned and page sized block of memory +****************************************************************************/ +void PMAPI PM_freePage( + void *p) +{ + pageblock *block; + + /* First find the page block that this page belongs to */ + for (block = pageBlocks; block != NULL; block = block->next) { + if (p >= block->freeListStart && p <= block->freeListEnd) + break; + } + CHECK(block != NULL); + + /* Now free the block by adding it to the free list */ + FREELIST_NEXT(p) = block->freeList; + block->freeList = p; + if (++block->freeCount == PAGES_PER_BLOCK) { + /* If all pages in the page block are now free, free the entire + * page block itself. + */ + if (block == pageBlocks) { + /* Delete from head */ + pageBlocks = block->next; + if (block->next) + block->next->prev = NULL; + } + else { + /* Delete from middle of list */ + CHECK(block->prev != NULL); + block->prev->next = block->next; + if (block->next) + block->next->prev = block->prev; + } + + /* Unlock the memory and free it */ + PM_unlockDataPages(block,PAGE_BLOCK_SIZE,&block->lockHandle); + DosFreeMem(block); + } +} + +/**************************************************************************** +REMARKS: +Map in all the shared memory blocks for managing the memory pages above. +****************************************************************************/ +void PMAPI PM_mapSharedPages(void) +{ + pageblock *block; + + /* Map all the page blocks above into the shared memory for process */ + for (block = pageBlocks; block != NULL; block = block->next) { + DosGetSharedMem(block, PAG_READ | PAG_WRITE); + } +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockDataPages( + void *p, + uint len, + PM_lockHandle *lockHandle) +{ + parmsIn[0] = (ulong)p; + parmsIn[1] = len; + CallSDDHelp(PMHELP_LOCKPAGES); + lockHandle->h[0] = parmsOut[1]; + lockHandle->h[1] = parmsOut[2]; + lockHandle->h[2] = parmsOut[3]; + return parmsOut[0]; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockDataPages( + void *p, + uint len, + PM_lockHandle *lockHandle) +{ + parmsIn[0] = lockHandle->h[0]; + parmsIn[1] = lockHandle->h[1]; + parmsIn[2] = lockHandle->h[2]; + return CallSDDHelp(PMHELP_UNLOCKPAGES); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lockHandle) +{ + parmsIn[0] = (ulong)p; + parmsIn[1] = len; + CallSDDHelp(PMHELP_LOCKPAGES); + lockHandle->h[0] = parmsOut[1]; + lockHandle->h[1] = parmsOut[2]; + lockHandle->h[2] = parmsOut[3]; + return parmsOut[0]; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lockHandle) +{ + parmsIn[0] = lockHandle->h[0]; + parmsIn[1] = lockHandle->h[1]; + parmsIn[2] = lockHandle->h[2]; + return CallSDDHelp(PMHELP_UNLOCKPAGES); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankA( + int bank) +{ + INTCRF rmregs; + + if (!InitInt10()) + return; + memset(&rmregs, 0, sizeof(rmregs)); + rmregs.ulBIOSIntNo = 0x10; + rmregs.aCRF.reg_eax = 0x4F05; + rmregs.aCRF.reg_ebx = 0x0000; + rmregs.aCRF.reg_edx = bank; + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankAB( + int bank) +{ + INTCRF rmregs; + + if (!InitInt10()) + return; + memset(&rmregs, 0, sizeof(rmregs)); + rmregs.ulBIOSIntNo = 0x10; + rmregs.aCRF.reg_eax = 0x4F05; + rmregs.aCRF.reg_ebx = 0x0000; + rmregs.aCRF.reg_edx = bank; + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); + rmregs.ulBIOSIntNo = 0x10; + rmregs.aCRF.reg_eax = 0x4F05; + rmregs.aCRF.reg_ebx = 0x0001; + rmregs.aCRF.reg_edx = bank; + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display start address. +****************************************************************************/ +void PMAPI PM_setCRTStart( + int x, + int y, + int waitVRT) +{ + INTCRF rmregs; + + if (!InitInt10()) + return; + memset(&rmregs, 0, sizeof(rmregs)); + rmregs.ulBIOSIntNo = 0x10; + rmregs.aCRF.reg_eax = 0x4F07; + rmregs.aCRF.reg_ebx = waitVRT; + rmregs.aCRF.reg_ecx = x; + rmregs.aCRF.reg_edx = y; + PM_VIDEOPMI32Request(&Adapter,PMIREQUEST_SOFTWAREINT,&rmregs,NULL); +} + +/**************************************************************************** +REMARKS: +Execute the POST on the secondary BIOS for a controller. +****************************************************************************/ +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + (void)axVal; + (void)BIOSPhysAddr; + (void)mappedBIOS; + (void)BIOSLen; + return false; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ + return MTRR_enableWriteCombine(base,size,type); +} + +/* TODO: Move the MTRR helper stuff into the call gate, or better yet */ +/* entirely into the ring 0 helper driver!! */ + +/* MTRR helper functions. To make it easier to implement the MTRR support + * under OS/2, we simply put our ring 0 helper functions into the + * helper device driver rather than the entire MTRR module. This makes + * it easier to maintain the MTRR support since we don't need to deal + * with 16-bit ring 0 code in the MTRR library. + */ + +/**************************************************************************** +REMARKS: +Flush the translation lookaside buffer. +****************************************************************************/ +void PMAPI PM_flushTLB(void) +{ + CallSDDHelp(PMHELP_FLUSHTLB); +} + +/**************************************************************************** +REMARKS: +Return true if ring 0 (or if we can call the helpers functions at ring 0) +****************************************************************************/ +ibool _ASMAPI _MTRR_isRing0(void) +{ + return true; +} + +/**************************************************************************** +REMARKS: +Read and return the value of the CR4 register +****************************************************************************/ +ulong _ASMAPI _MTRR_saveCR4(void) +{ + return CallSDDHelp(PMHELP_SAVECR4); +} + +/**************************************************************************** +REMARKS: +Restore the value of the CR4 register +****************************************************************************/ +void _ASMAPI _MTRR_restoreCR4(ulong cr4Val) +{ + parmsIn[0] = cr4Val; + CallSDDHelp(PMHELP_RESTORECR4); +} + +/**************************************************************************** +REMARKS: +Read a machine status register for the CPU. +****************************************************************************/ +void _ASMAPI _MTRR_readMSR( + ulong reg, + ulong *eax, + ulong *edx) +{ + parmsIn[0] = reg; + CallSDDHelp(PMHELP_READMSR); + *eax = parmsOut[0]; + *edx = parmsOut[1]; +} + +/**************************************************************************** +REMARKS: +Write a machine status register for the CPU. +****************************************************************************/ +void _ASMAPI _MTRR_writeMSR( + ulong reg, + ulong eax, + ulong edx) +{ + parmsIn[0] = reg; + parmsIn[1] = eax; + parmsIn[2] = edx; + CallSDDHelp(PMHELP_WRITEMSR); +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* TODO: Implement this to load shared libraries! */ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* TODO: Implement this! */ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* TODO: Implement this! */ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Internal function to convert the find data to the generic interface. +****************************************************************************/ +static void convertFindData( + PM_findData *findData, + FILEFINDBUF3 *blk) +{ + ulong dwSize = findData->dwSize; + + memset(findData,0,findData->dwSize); + findData->dwSize = dwSize; + if (blk->attrFile & FILE_READONLY) + findData->attrib |= PM_FILE_READONLY; + if (blk->attrFile & FILE_DIRECTORY) + findData->attrib |= PM_FILE_DIRECTORY; + if (blk->attrFile & FILE_ARCHIVED) + findData->attrib |= PM_FILE_ARCHIVE; + if (blk->attrFile & FILE_HIDDEN) + findData->attrib |= PM_FILE_HIDDEN; + if (blk->attrFile & FILE_SYSTEM) + findData->attrib |= PM_FILE_SYSTEM; + findData->sizeLo = blk->cbFile; + findData->sizeHi = 0; + strncpy(findData->name,blk->achName,PM_MAX_PATH); + findData->name[PM_MAX_PATH-1] = 0; +} + +#define FIND_MASK (FILE_ARCHIVED | FILE_DIRECTORY | FILE_SYSTEM | FILE_HIDDEN | FILE_READONLY) + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + FILEFINDBUF3 blk; + HDIR hdir = HDIR_CREATE; + ulong count = 1; + + if (DosFindFirst((PSZ)filename,&hdir,FIND_MASK,&blk,sizeof(blk),&count,FIL_STANDARD) == NO_ERROR) { + convertFindData(findData,&blk); + return (void*)hdir; + } + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + FILEFINDBUF3 blk; + ulong count = 1; + + if (DosFindNext((HDIR)handle,&blk,sizeof(blk),&count) == NO_ERROR) { + convertFindData(findData,&blk); + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + DosFindClose((HDIR)handle); +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 0 - Current drive + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + ulong cntDisk,cntDriveMap; + ibool valid; + + DosQueryCurrentDisk(&cntDisk,&cntDriveMap); + valid = (DosSetDefaultDisk(drive) == NO_ERROR); + DosSetDefaultDisk(cntDisk); + return valid; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + ulong length = len; + + DosQueryCurrentDir(drive, (PSZ)dir, &length); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + FILESTATUS3 s; + + if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s))) + return; + s.attrFile = 0; + if (attrib & PM_FILE_READONLY) + s.attrFile |= FILE_READONLY; + if (attrib & PM_FILE_ARCHIVE) + s.attrFile |= FILE_ARCHIVED; + if (attrib & PM_FILE_HIDDEN) + s.attrFile |= FILE_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + s.attrFile |= FILE_SYSTEM; + DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&s,sizeof(s),0L); +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + FILESTATUS3 fs3; + uint retval = 0; + + if (DosQueryPathInfo((PSZ)filename, FIL_STANDARD, &fs3, sizeof(FILESTATUS3))) + return 0; + if (fs3.attrFile & FILE_READONLY) + retval |= PM_FILE_READONLY; + if (fs3.attrFile & FILE_ARCHIVED) + retval |= PM_FILE_ARCHIVE; + if (fs3.attrFile & FILE_HIDDEN) + retval |= PM_FILE_HIDDEN; + if (fs3.attrFile & FILE_SYSTEM) + retval |= PM_FILE_SYSTEM; + return retval; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + return DosCreateDir((PSZ)filename,NULL) == NO_ERROR; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return DosDeleteDir((PSZ)filename) == NO_ERROR; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + FILESTATUS3 fs3; + struct tm tc; + struct tm *ret; + time_t tt; + + if (DosQueryPathInfo((PSZ)filename, FIL_STANDARD, &fs3, sizeof(FILESTATUS3))) + return false; + if (gmTime) { + tc.tm_year = fs3.fdateLastWrite.year + 80; + tc.tm_mon = fs3.fdateLastWrite.month - 1; + tc.tm_mday = fs3.fdateLastWrite.day; + tc.tm_hour = fs3.ftimeLastWrite.hours; + tc.tm_min = fs3.ftimeLastWrite.minutes; + tc.tm_sec = fs3.ftimeLastWrite.twosecs * 2; + if((tt = mktime(&tc)) == -1) + return false; + if(!(ret = gmtime(&tt))) + return false; + time->sec = ret->tm_sec; + time->day = ret->tm_mday; + time->mon = ret->tm_mon + 1; + time->year = ret->tm_year - 80; + time->min = ret->tm_min; + time->hour = ret->tm_hour; + } + else { + time->sec = fs3.ftimeLastWrite.twosecs * 2; + time->day = fs3.fdateLastWrite.day; + time->mon = fs3.fdateLastWrite.month; + time->year = fs3.fdateLastWrite.year; + time->min = fs3.ftimeLastWrite.minutes; + time->hour = fs3.ftimeLastWrite.hours; + } + return true; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + FILESTATUS3 fs3; + struct tm tc; + struct tm *ret; + time_t tt; + + if (DosQueryPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&fs3,sizeof(fs3))) + return false; + if (gmTime) { + tc.tm_year = time->year + 80; + tc.tm_mon = time->mon - 1; + tc.tm_mday = time->day; + tc.tm_hour = time->hour; + tc.tm_min = time->min; + tc.tm_sec = time->sec; + if((tt = mktime(&tc)) == -1) + return false; + ret = localtime(&tt); + fs3.ftimeLastWrite.twosecs = ret->tm_sec / 2; + fs3.fdateLastWrite.day = ret->tm_mday; + fs3.fdateLastWrite.month = ret->tm_mon + 1; + fs3.fdateLastWrite.year = ret->tm_year - 80; + fs3.ftimeLastWrite.minutes = ret->tm_min; + fs3.ftimeLastWrite.hours = ret->tm_hour; + } + else { + fs3.ftimeLastWrite.twosecs = time->sec / 2; + fs3.fdateLastWrite.day = time->day; + fs3.fdateLastWrite.month = time->mon; + fs3.fdateLastWrite.year = time->year; + fs3.ftimeLastWrite.minutes = time->min; + fs3.ftimeLastWrite.hours = time->hour; + } + memcpy(&fs3.fdateLastAccess, &fs3.fdateLastWrite, sizeof(FDATE)); + memcpy(&fs3.fdateCreation, &fs3.fdateLastWrite, sizeof(FDATE)); + memcpy(&fs3.ftimeLastAccess, &fs3.ftimeLastWrite, sizeof(FTIME)); + memcpy(&fs3.ftimeCreation, &fs3.ftimeLastWrite, sizeof(FTIME)); + DosSetPathInfo((PSZ)filename,FIL_STANDARD,(PVOID)&fs3,sizeof(FILESTATUS3),0L); + return true; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c new file mode 100644 index 000000000..579ef2c95 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c new file mode 100644 index 000000000..30ffe4340 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2/ztimer.c @@ -0,0 +1,110 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: OS/2 +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static ulong frequency; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ + DosTmrQueryFreq(&frequency); +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +#define __LZTimerOn(tm) DosTmrQueryTime((QWORD*)&tm->start) + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + CPU_largeInteger tmLap,tmCount; + + DosTmrQueryTime((QWORD*)&tmLap); + _CPU_diffTime64(&tm->start,&tmLap,&tmCount); + return _CPU_calcMicroSec(&tmCount,frequency); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) DosTmrQueryTime((QWORD*)&tm->end) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,frequency); +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1000 + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the BIOS timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + ULONG count; + DosQuerySysInfo( QSV_MS_COUNT, QSV_MS_COUNT, &count, sizeof(ULONG) ); + return count; +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c b/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c new file mode 100644 index 000000000..7af20a956 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2pm/event.c @@ -0,0 +1,170 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: IBM PC (OS/2) +* +* Description: OS/2 implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static int oldMouseState; /* Old mouse state */ +static ulong oldKeyMessage; /* Old keyboard state */ +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ +HMOU _EVT_hMouse; /* Handle to the mouse driver */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under OS/2 */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +Pumps all messages in the message queue from OS/2 into our event queue. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + /* TODO: Implement this for OS/2 Presentation Manager apps! */ +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + /* Initialise the event queue */ + EVT.mouseMove = mouseMove; + initEventQueue(); + oldMouseState = 0; + oldKeyMessage = 0; + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* TODO: OS/2 PM specific initialisation code! */ + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for OS/2 */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for OS/2 */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* TODO: OS/2 PM specific exit code */ +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +#define _EVT_setMousePos(x,y) diff --git a/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h new file mode 100644 index 000000000..0b69f8222 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/os2pm/oshdr.h @@ -0,0 +1,36 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#define INCL_DOSERRORS +#define INCL_DOS +#define INCL_SUB +#define INCL_VIO +#define INCL_KBD +#include diff --git a/board/MAI/bios_emulator/scitech/src/pm/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/oshdr.h new file mode 100644 index 000000000..404e5c93c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/oshdr.h @@ -0,0 +1,70 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Header file to pull in OS specific headers for the target +* OS environment. +* +****************************************************************************/ + +#if defined(__SMX32__) +#include "smx/oshdr.h" +#elif defined(__RTTARGET__) +#include "rttarget/oshdr.h" +#elif defined(__REALDOS__) +#include "dos/oshdr.h" +#elif defined(__WIN32_VXD__) +#include "vxd/oshdr.h" +#elif defined(__NT_DRIVER__) +#include "ntdrv/oshdr.h" +#elif defined(__WINDOWS32__) +#include "win32/oshdr.h" +#elif defined(__OS2_VDD__) +#include "vxd/oshdr.h" +#elif defined(__OS2__) +#if defined(__OS2_PM__) +#include "os2pm/oshdr.h" +#else +#include "os2/oshdr.h" +#endif +#elif defined(__LINUX__) +#if defined(__USE_X11__) +#include "x11/oshdr.h" +#else +#include "linux/oshdr.h" +#endif +#elif defined(__QNX__) +#if defined(__USE_PHOTON__) +#include "photon/oshdr.h" +#elif defined(__USE_X11__) +#include "x11/oshdr.h" +#else +#include "qnx/oshdr.h" +#endif +#elif defined(__BEOS__) +#include "beos/oshdr.h" +#else +#error PM library not ported to this platform yet! +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/photon/event.c b/board/MAI/bios_emulator/scitech/src/pm/photon/event.c new file mode 100644 index 000000000..581da16fd --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/photon/event.c @@ -0,0 +1,268 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX Photon GUI +* +* Description: QNX fullscreen console implementation for the SciTech +* cross platform event library. +* +****************************************************************************/ + +/*--------------------------- Global variables ----------------------------*/ + +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under Linux */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +static ibool _EVT_isKeyDown( + uchar scancode) +{ + return (KeyState[(scancode & 0xf8) >> 3] & (1 << (scancode & 0x7)) ? + true : false); +} + +/**************************************************************************** +REMARKS: +Retrieves all events from the mouse/keyboard event queue and stuffs them +into the MGL event queue for further processing. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + int pid; + uint msg, but_stat, message; + uchar evt[sizeof (PhEvent_t) + 1024]; + PhEvent_t *event = (void *)evt; + PhKeyEvent_t *key; + PhPointerEvent_t *mouse; + static int extended; + event_t _evt; + + while (count < EVENTQSIZE) { + uint mods = 0, keyp = 0; + + pid = Creceive(0, &msg, sizeof (msg)); + + if (pid == -1) + return; + + if (PhEventRead(pid, event, sizeof (evt)) == Ph_EVENT_MSG) { + memset(&evt, 0, sizeof (evt)); + if (event->type == Ph_EV_KEY) { + key = PhGetData(event); + + if (key->key_flags & KEY_SCAN_VALID) { + keyp = key->key_scan; + if (key->key_flags & KEY_DOWN) + KeyState[(keyp & 0xf800) >> 11] + |= 1 << ((keyp & 0x700) >> 8); + else + KeyState[(keyp & 0xf800) >> 11] + &= ~(1 << ((keyp & 0x700) >> 8)); + } + if ((key->key_flags & KEY_SYM_VALID) || extended) + keyp |= key->key_sym; + + /* No way to tell left from right... */ + if (key->key_mods & KEYMOD_SHIFT) + mods = (EVT_LEFTSHIFT | EVT_RIGHTSHIFT); + if (key->key_mods & KEYMOD_CTRL) + mods |= (EVT_CTRLSTATE | EVT_LEFTCTRL); + if (key->key_mods & KEYMOD_ALT) + mods |= (EVT_ALTSTATE | EVT_LEFTALT); + + _evt.when = evt->timestamp; + if (key->key_flags & KEY_REPEAT) { + _evt.what = EVT_KEYREPEAT; + _evt.message = 0x10000; + } + else if (key->key_flags & KEY_DOWN) + _evt.what = EVT_KEYDOWN; + else + _evt.what = EVT_KEYUP; + _evt.modifiers = mods; + _evt.message |= keyp; + + addEvent(&_evt); + + switch(key->key_scan & 0xff00) { + case 0xe000: + extended = 1; + break; + case 0xe001: + extended = 2; + break; + default: + if (extended) + extended--; + } + } + else if (event->type & Ph_EV_PTR_ALL) { + but_stat = message = 0; + mouse = PhGetData(event); + + if (mouse->button_state & Ph_BUTTON_3) + but_stat = EVT_LEFTBUT; + if (mouse->buttons & Ph_BUTTON_3) + message = EVT_LEFTBMASK; + + if (mouse->button_state & Ph_BUTTON_1) + but_stat |= EVT_RIGHTBUT; + if (mouse->buttons & Ph_BUTTON_1) + message |= EVT_RIGHTBMASK; + + _evt.when = evt->timestamp; + if (event->type & Ph_EV_PTR_MOTION) { + _evt.what = EVT_MOUSEMOVE; + _evt.where_x = mouse->pos.x; + _evt.where_y = mouse->pos.y; + _evt.modifiers = but_stat; + addEvent(&_evt); + } + if (event->type & Ph_EV_BUT_PRESS) + _evt.what = EVT_MOUSEDOWN; + else + _evt.what = EVT_MOUSEUP; + _evt.where_x = mouse->pos.x; + _evt.where_y = mouse->pos.y; + _evt.modifiers = but_stat; + _evt.message = message; + addEvent(&_evt); + } + } + else + return; + } +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort( + int signo) +{ + char buf[80]; + + EVT_exit(); + sprintf(buf,"Terminating on signal %d",signo); + PM_fatalError(buf); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + int i; + + /* Initialise the event queue */ + _mouseMove = mouseMove; + initEventQueue(); + memset((void *)KeyState, 0, sizeof (KeyState)); + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + /* TODO: Need to call Input to change the coordinates that it returns */ + /* for mouse events!! */ +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for Photon */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for Photon */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h new file mode 100644 index 000000000..3c72563de --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/photon/oshdr.h @@ -0,0 +1,38 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX Photon GUI +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include diff --git a/board/MAI/bios_emulator/scitech/src/pm/pm.vpw b/board/MAI/bios_emulator/scitech/src/pm/pm.vpw new file mode 100644 index 000000000..a37ae7da6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pm.vpw @@ -0,0 +1,43 @@ +[Dependencies] +[CurrentProject] +curproj=pmlinux.vpj +[ProjectFiles] +pmcommon.vpj +pmdos.vpj +pmlinux.vpj +pmqnx.vpj +pmvxd.vpj +pmwin32.vpj +z_samples.vpj +..\a-global includes.vpj +[TreeExpansion] +"..\a-global includes.vpj" 0 +pmcommon.vpj 0 +pmdos.vpj 0 +pmlinux.vpj 0 +pmqnx.vpj 0 +pmvxd.vpj 0 +pmwin32.vpj 0 +z_samples.vpj 1 1 +[State] +SCREEN: 1280 1024 0 0 960 746 0 0 M 0 0 0 0 977 631 +CWD: C:\scitech\src\pm +FILEHIST: 9 +C:\scitech\makedefs\gcc_win32.mk +C:\scitech\bin\gcc2-w32.bat +C:\scitech\bin\gcc2-c32.bat +C:\scitech\bin\gcc2-linux.bat +C:\scitech\makedefs\gcc_linux.mk +C:\scitech\src\pm\linux\event.c +C:\scitech\src\pm\linux\oshdr.h +C:\scitech\src\pm\event.c +C:\scitech\src\pm\pmlinux.vpj +[ProjectDates] +pmcommon.vpj=20010517164335290 +pmdos.vpj=20010517164335290 +pmlinux.vpj=20010620175829812 +pmqnx.vpj=20010517164335290 +pmvxd.vpj=20010517164335306 +pmwin32.vpj=20010517164335306 +z_samples.vpj=20010517164335306 +..\a-global includes.vpj=20010517164334978 diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj new file mode 100644 index 000000000..6fe436b06 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmcommon.vpj @@ -0,0 +1,45 @@ +[COMPILER] +version=5.0b +MACRO=\n +activeconfig=,wc10-d32 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\nOther Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n*.*\n +FILTERASSOCIATEFILETYPES=0 0 0 0 +FILTERAPPCOMMAND=\n\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|hide|:Compile:&Compile, +make=concur|capture|hide|clear|saveall|:Build:&Build, +rebuild=concur|capture|hide|clear|saveall|:Rebuild:&Rebuild, +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +common.c +cpuinfo.c +debug.c +event.c +makefile +oshdr.h +ztimer.c +..\common\agplib.c +codepage\us_eng.c +common\_cpuinfo.asm +common\_dma.asm +common\_int64.asm +common\_joy.asm +common\_mtrr.asm +common\_pcilib.asm +common\agp.c +common\keyboard.c +common\malloc.c +common\mtrr.c +common\pcilib.c +common\unixio.c +common\vgastate.c +[ASSOCIATION] +[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj new file mode 100644 index 000000000..78111d247 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmdos.vpj @@ -0,0 +1,41 @@ +[SciTech] +compiler=wc10- +targetos=d32 +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,TEST_HARNESS=1 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|clear|:Compile:&Compile,dmake %n.obj -u %b +make=concur|capture|clear|saveall|:Build:&Build,dmake install %b +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u %b +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +dos\_event.asm +dos\_lztimer.asm +dos\_pm.asm +dos\_pmdos.asm +dos\_vflat.asm +dos\cpuinfo.c +dos\event.c +dos\oshdr.h +dos\pm.c +dos\pmdos.c +dos\vflat.c +dos\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] +config=,NORMAL_BUILD=1 +config=,TEST_HARNESS=1 diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj new file mode 100644 index 000000000..95b7160a8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmlinux.vpj @@ -0,0 +1,35 @@ +[SciTech] +compiler=gcc2- +targetos=linux +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +activeconfig=,install BUILD_DLL=1 +compile=concur|capture|clear|:Compile:&Compile,dmake %n.o -u +make=concur|capture|clear|saveall|:Build:&Build,dmake %b +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake -u %b +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +linux\cpuinfo.c +linux\event.c +linux\oshdr.h +linux\pm.c +linux\vflat.c +linux\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] +config=,install BUILD_DLL=1 +config=,install diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj new file mode 100644 index 000000000..74dfb4611 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmntdrv.vpj @@ -0,0 +1,39 @@ +[SciTech] +compiler=vc60- +targetos=drvw2k +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,wc10-d32 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|:Compile:&Compile,dmake %n.obj +make=concur|capture|clear|saveall|:Build:&Build,dmake install +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|hide|savenone|:Clean Directory:&Clean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +..\..\include\ntdriver.h +ntdrv\_pm.asm +ntdrv\cpuinfo.c +ntdrv\int86.c +ntdrv\irq.c +ntdrv\mem.c +ntdrv\oshdr.h +ntdrv\pm.c +ntdrv\stdio.c +ntdrv\stdlib.c +ntdrv\vflat.c +ntdrv\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj new file mode 100644 index 000000000..0aea8c1c2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmqnx.vpj @@ -0,0 +1,35 @@ +[SciTech] +compiler=wc10- +targetos=qnx +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,wc10-d32 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|clear|:Compile:&Compile,dmake %n.obj +make=concur|capture|clear|saveall|:Build:&Build,dmake install +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:C&lean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +qnx\_mtrrqnx.asm +qnx\cpuinfo.c +qnx\event.c +qnx\mtrrqnx.c +qnx\oshdr.h +qnx\pm.c +qnx\vflat.c +qnx\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj new file mode 100644 index 000000000..6c263fd55 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmvxd.vpj @@ -0,0 +1,34 @@ +[SciTech] +compiler=bc50- +targetos=vxd +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,wc10-d32 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|nochangedir|:Compile:&Compile,dmake %n.obj +make=concur|capture|clear|saveall|nochangedir|:Build:&Build,dmake install +rebuild=concur|capture|clear|saveall|nochangedir|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u +debug=concur|capture|hide|savenone|nochangedir|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|hide|savenone|nochangedir|:Clean Directory:&Clean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +vxd\_pm.asm +vxd\cpuinfo.c +vxd\fileio.c +vxd\oshdr.h +vxd\pm.c +vxd\vflat.c +vxd\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj b/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj new file mode 100644 index 000000000..43f03ea96 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/pmwin32.vpj @@ -0,0 +1,35 @@ +[SciTech] +compiler=vc60- +targetos=c32 +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,wc10-d32 +FILTERNAME=Source Files\nInclude Files\nAssembler Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n*.h\n*.asm\n +FILTERASSOCIATEFILETYPES=0 0 0 +FILTERAPPCOMMAND=\n\n\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|:Compile:&Compile,dmake %n.obj +make=concur|capture|clear|saveall|:Build:&Build,dmake install +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake cleanexe & dmake install -u +debug=concur|capture|hide|savenone|:Debug:&Debug, +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|:User 1:User 1, +user2=hide|:User 2:User 2, +usertool_clean_directory=concur|capture|savenone|:Clean Directory:&Clean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +win32\_pmwin32.asm +win32\cpuinfo.c +win32\ddraw.c +win32\event.c +win32\oshdr.h +win32\pm.c +win32\vflat.c +win32\ztimer.c +[ASSOCIATION] +[CONFIGURATIONS] diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm b/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm new file mode 100644 index 000000000..5a3fe105e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/_mtrrqnx.asm @@ -0,0 +1,226 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NASM +;* Environment: QNX +;* +;* Description: Assembler support routines for the Memory Type Range Register +;* (MTRR) module for QNX. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _mtrrqnx ; Set up memory model + +begdataseg _mtrrqnx ; Start of code segment + +ifdef USE_NASM +%define R0_FLUSH_TLB 0 +%define R0_SAVE_CR4 1 +%define R0_RESTORE_CR4 2 +%define R0_READ_MSR 3 +%define R0_WRITE_MSR 4 +else +R0_FLUSH_TLB EQU 0 +R0_SAVE_CR4 EQU 1 +R0_RESTORE_CR4 EQU 2 +R0_READ_MSR EQU 3 +R0_WRITE_MSR EQU 4 +endif + +cpublic _PM_R0 +_PM_R0_service dd 0 +_PM_R0_reg dd 0 +_PM_R0_eax dd 0 +_PM_R0_edx dd 0 + +enddataseg _mtrrqnx ; Start of code segment + +begcodeseg _mtrrqnx ; Start of code segment + +P586 + +;---------------------------------------------------------------------------- +; ulong _MTRR_disableInt(void); +;---------------------------------------------------------------------------- +; Return processor interrupt status and disable interrupts. +;---------------------------------------------------------------------------- +cprocstart _MTRR_disableInt + + pushfd ; Put flag word on stack +; cli ; Disable interrupts! + pop eax ; deposit flag word in return register + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _MTRR_restoreInt(ulong ps); +;---------------------------------------------------------------------------- +; Restore processor interrupt status. +;---------------------------------------------------------------------------- +cprocstart _MTRR_restoreInt + + ARG ps:ULONG + + push ebp + mov ebp,esp ; Set up stack frame + push [ULONG ps] + popfd ; Restore processor status (and interrupts) + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_getCx86(uchar reg); +;---------------------------------------------------------------------------- +; Read a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_getCx86 + + ARG reg:UCHAR + + enter_c + mov al,[reg] + out 22h,al + in al,23h + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; uchar _MTRR_setCx86(uchar reg,uchar val); +;---------------------------------------------------------------------------- +; Write a Cyrix CPU indexed register +;---------------------------------------------------------------------------- +cprocstart _MTRR_setCx86 + + ARG reg:UCHAR, val:UCHAR + + enter_c + mov al,[reg] + out 22h,al + mov al,[val] + out 23h,al + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; ulong _PM_ring0_isr(void); +;---------------------------------------------------------------------------- +; Ring 0 clock interrupt handler that we use to execute the MTRR support +; code. +;---------------------------------------------------------------------------- +cprocnear _PM_ring0_isr + +;-------------------------------------------------------- +; void PM_flushTLB(void); +;-------------------------------------------------------- + pushad + cmp [DWORD _PM_R0_service],R0_FLUSH_TLB + jne @@1 + wbinvd ; Flush the CPU cache + mov eax,cr3 + mov cr3,eax ; Flush the TLB + jmp @@Exit + +;-------------------------------------------------------- +; ulong _MTRR_saveCR4(void); +;-------------------------------------------------------- +@@1: cmp [DWORD _PM_R0_service],R0_SAVE_CR4 + jne @@2 + +; Save value of CR4 and clear Page Global Enable (bit 7) + + mov ebx,cr4 + mov eax,ebx + and al,7Fh + mov cr4,eax + +; Disable and flush caches + + mov eax,cr0 + or eax,40000000h + wbinvd + mov cr0,eax + wbinvd + +; Return value from CR4 + + mov [_PM_R0_reg],ebx + jmp @@Exit + +;-------------------------------------------------------- +; void _MTRR_restoreCR4(ulong cr4Val) +;-------------------------------------------------------- +@@2: cmp [DWORD _PM_R0_service],R0_RESTORE_CR4 + jne @@3 + + mov eax,cr0 + and eax,0BFFFFFFFh + mov cr0,eax + mov eax,[_PM_R0_reg] + mov cr4,eax + jmp @@Exit + +;-------------------------------------------------------- +; void _MTRR_readMSR(int reg, ulong FAR *eax, ulong FAR *edx); +;-------------------------------------------------------- +@@3: cmp [DWORD _PM_R0_service],R0_READ_MSR + jne @@4 + + mov ecx,[_PM_R0_reg] + rdmsr + mov [_PM_R0_eax],eax + mov [_PM_R0_edx],edx + jmp @@Exit + +;-------------------------------------------------------- +; void _MTRR_writeMSR(int reg, ulong eax, ulong edx); +;-------------------------------------------------------- +@@4: cmp [DWORD _PM_R0_service],R0_WRITE_MSR + jne @@Exit + + mov ecx,[_PM_R0_reg] + mov eax,[_PM_R0_eax] + mov edx,[_PM_R0_edx] + wrmsr + jmp @@Exit + +@@Exit: mov [DWORD _PM_R0_service],-1 + popad + mov eax,0 + retf + +cprocend + +endcodeseg _mtrrqnx + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c new file mode 100644 index 000000000..a8782542b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/cpuinfo.c @@ -0,0 +1,64 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: QNX specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +TODO: We should implement this for QNX! +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +TODO: We should implement this for QNX! +****************************************************************************/ +#define RestoreThreadPriority(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + freq->low = CLOCKS_PER_SEC * 1000; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + (t)->low = clock() * 1000; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c new file mode 100644 index 000000000..45cd51445 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/event.c @@ -0,0 +1,601 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: QNX fullscreen console implementation for the SciTech +* cross platform event library. +* +****************************************************************************/ + +#include +#include + +/*--------------------------- Global variables ----------------------------*/ + +#ifndef __QNXNTO__ +static struct _mouse_ctrl *_PM_mouse_ctl; +static int _PM_keyboard_fd = -1; +/*static int _PM_modifiers, _PM_leds; */ +#else +static int kbd_fd = -1, mouse_fd = -1; +#endif +static int kill_pid = 0; +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +#define TIME_TO_MSEC(__t) ((__t).tv_nsec / 1000000 + (__t).tv_sec * 1000) + +#define LED_NUM 1 +#define LED_CAP 2 +#define LED_SCR 4 + +/* Scancode mappings on QNX for special keys */ + +typedef struct { + int scan; + int map; + } keymap; + +/* TODO: Fix this and set it up so we can do a binary search! */ + +keymap keymaps[] = { + {96, KB_padEnter}, + {74, KB_padMinus}, + {78, KB_padPlus}, + {55, KB_padTimes}, + {98, KB_padDivide}, + {71, KB_padHome}, + {72, KB_padUp}, + {73, KB_padPageUp}, + {75, KB_padLeft}, + {76, KB_padCenter}, + {77, KB_padRight}, + {79, KB_padEnd}, + {80, KB_padDown}, + {81, KB_padPageDown}, + {82, KB_padInsert}, + {83, KB_padDelete}, + {105,KB_left}, + {108,KB_down}, + {106,KB_right}, + {103,KB_up}, + {110,KB_insert}, + {102,KB_home}, + {104,KB_pageUp}, + {111,KB_delete}, + {107,KB_end}, + {109,KB_pageDown}, + {125,KB_leftWindows}, + {126,KB_rightWindows}, + {127,KB_menu}, + {100,KB_rightAlt}, + {97,KB_rightCtrl}, + }; + +/* And the keypad with num lock turned on (changes the ASCII code only) */ + +keymap keypad[] = { + {71, ASCII_7}, + {72, ASCII_8}, + {73, ASCII_9}, + {75, ASCII_4}, + {76, ASCII_5}, + {77, ASCII_6}, + {79, ASCII_1}, + {80, ASCII_2}, + {81, ASCII_3}, + {82, ASCII_0}, + {83, ASCII_period}, + }; + +#define NB_KEYMAPS (sizeof(keymaps)/sizeof(keymaps[0])) +#define NB_KEYPAD (sizeof(keypad)/sizeof(keypad[0])) + +/*---------------------------- Implementation -----------------------------*/ + +/**************************************************************************** +REMARKS: +Include generic raw scancode keyboard module. +****************************************************************************/ +#include "common/keyboard.c" + +/* These are not used under QNX */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + struct timespec t; + clock_gettime(CLOCK_REALTIME,&t); + return (t.tv_nsec / 1000000 + t.tv_sec * 1000); +} + +/**************************************************************************** +REMARKS: +Converts a mickey movement value to a pixel adjustment value. +****************************************************************************/ +static int MickeyToPixel( + int mickey) +{ + /* TODO: We can add some code in here to handle 'acceleration' for */ + /* the mouse cursor. For now just use the mickeys. */ + return mickey; +} + +#ifdef __QNXNTO__ +/**************************************************************************** +REMARKS: +Retrieves all events from the mouse/keyboard event queue and stuffs them +into the MGL event queue for further processing. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + int rc1, rc2; + struct _keyboard_packet key; + struct _mouse_packet ms; + static long old_buttons = 0; + uint message = 0, but_stat = 0, mods = 0; + event_t evt; + + while (EVT.count < EVENTQSIZE) { + rc1 = read(kbd_fd, (void *)&key, sizeof(key)); + if (rc1 == -1) { + if (errno == EAGAIN) + rc1 = 0; + else { + perror("getEvents"); + PM_fatalError("Keyboard error"); + } + } + if (rc1 > 0) { + memset(&evt, 0, sizeof(evt)); + if (key.data.modifiers & KEYMOD_SHIFT) + mods |= EVT_LEFTSHIFT; + if (key.data.modifiers & KEYMOD_CTRL) + mods |= EVT_CTRLSTATE; + if (key.data.modifiers & KEYMOD_ALT) + mods |= EVT_ALTSTATE; + + /* Now store the keyboard event data */ + evt.when = TIME_TO_MSEC(key.time); + if (key.data.flags & KEY_SCAN_VALID) + evt.message |= (key.data.key_scan & 0x7F) << 8; + if ((key.data.flags & KEY_SYM_VALID) && + (((key.data.key_sym & 0xff00) == 0xf000 && + (key.data.key_sym & 0xff) < 0x20) || + key.data.key_sym < 0x80)) + evt.message |= (key.data.key_sym & 0xFF); + evt.modifiers = mods; + if (key.data.flags & KEY_DOWN) { + evt.what = EVT_KEYDOWN; + keyUpMsg[evt.message >> 8] = (ushort)evt.message; + } + else if (key.data.flags & KEY_REPEAT) { + evt.message |= 0x10000; + evt.what = EVT_KEYREPEAT; + } + else { + evt.what = EVT_KEYUP; + evt.message = keyUpMsg[evt.message >> 8]; + if (evt.message == 0) + continue; + keyUpMsg[evt.message >> 8] = 0; + } + + /* Now add the new event to the event queue */ + addEvent(&evt); + } + rc2 = read(mouse_fd, (void *)&ms, sizeof (ms)); + if (rc2 == -1) { + if (errno == EAGAIN) + rc2 = 0; + else { + perror("getEvents"); + PM_fatalError("Mouse error"); + } + } + if (rc2 > 0) { + memset(&evt, 0, sizeof(evt)); + ms.hdr.buttons &= + (_POINTER_BUTTON_LEFT | _POINTER_BUTTON_RIGHT); + if (ms.hdr.buttons & _POINTER_BUTTON_LEFT) + but_stat = EVT_LEFTBUT; + if ((ms.hdr.buttons & _POINTER_BUTTON_LEFT) != + (old_buttons & _POINTER_BUTTON_LEFT)) + message = EVT_LEFTBMASK; + if (ms.hdr.buttons & _POINTER_BUTTON_RIGHT) + but_stat |= EVT_RIGHTBUT; + if ((ms.hdr.buttons & _POINTER_BUTTON_RIGHT) != + (old_buttons & _POINTER_BUTTON_RIGHT)) + message |= EVT_RIGHTBMASK; + if (ms.dx || ms.dy) { + ms.dy = -ms.dy; + EVT.mx += MickeyToPixel(ms.dx); + EVT.my += MickeyToPixel(ms.dy); + if (EVT.mx < 0) EVT.mx = 0; + if (EVT.my < 0) EVT.my = 0; + if (EVT.mx > rangeX) EVT.mx = rangeX; + if (EVT.my > rangeY) EVT.my = rangeY; + evt.what = EVT_MOUSEMOVE; + evt.when = TIME_TO_MSEC(ms.hdr.time); + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = ms.dx; + evt.relative_y = ms.dy; + evt.modifiers = but_stat; + addEvent(&evt); + } + evt.what = ms.hdr.buttons < old_buttons ? + EVT_MOUSEUP : EVT_MOUSEDOWN; + evt.when = TIME_TO_MSEC(ms.hdr.time); + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = ms.dx; + evt.relative_y = ms.dy; + evt.modifiers = but_stat; + evt.message = message; + if (ms.hdr.buttons != old_buttons) { + addEvent(&evt); + old_buttons = ms.hdr.buttons; + } + } + if (rc1 + rc2 == 0) + break; + } +} +#else +/**************************************************************************** +REMARKS: +Retrieves all events from the mouse/keyboard event queue and stuffs them +into the MGL event queue for further processing. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + struct mouse_event ev; + int rc; + static long old_buttons = 0; + uint message = 0, but_stat = 0; + event_t evt; + char buf[32]; + int numkeys, i; + + /* Poll keyboard events */ + while ((numkeys = read(_PM_keyboard_fd, buf, sizeof buf)) > 0) { + for (i = 0; i < numkeys; i++) { + processRawScanCode(buf[i]); + } + } + + if (_PM_mouse_ctl == NULL) + return; + + /* Gobble pending mouse events */ + while (EVT.count < EVENTQSIZE) { + rc = mouse_read(_PM_mouse_ctl, &ev, 1, 0, NULL); + if (rc == -1) { + perror("getEvents"); + PM_fatalError("Mouse error (Input terminated?)"); + } + if (rc == 0) + break; + + message = 0, but_stat = 0; + memset(&evt, 0, sizeof(evt)); + + ev.buttons &= (_MOUSE_LEFT | _MOUSE_RIGHT); + if (ev.buttons & _MOUSE_LEFT) + but_stat = EVT_LEFTBUT; + if ((ev.buttons & _MOUSE_LEFT) != (old_buttons & _MOUSE_LEFT)) + message = EVT_LEFTBMASK; + if (ev.buttons & _MOUSE_RIGHT) + but_stat |= EVT_RIGHTBUT; + if ((ev.buttons & _MOUSE_RIGHT) != (old_buttons & _MOUSE_RIGHT)) + message |= EVT_RIGHTBMASK; + if (ev.dx || ev.dy) { + ev.dy = -ev.dy; + EVT.mx += MickeyToPixel(ev.dx); + EVT.my += MickeyToPixel(ev.dy); + if (EVT.mx < 0) EVT.mx = 0; + if (EVT.my < 0) EVT.my = 0; + if (EVT.mx > rangeX) EVT.mx = rangeX; + if (EVT.my > rangeY) EVT.my = rangeY; + evt.what = EVT_MOUSEMOVE; + evt.when = ev.timestamp*100; + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = ev.dx; + evt.relative_y = ev.dy; + evt.modifiers = but_stat; + addEvent(&evt); + } + evt.what = ev.buttons < old_buttons ? EVT_MOUSEUP : EVT_MOUSEDOWN; + evt.when = ev.timestamp*100; + evt.where_x = EVT.mx; + evt.where_y = EVT.my; + evt.relative_x = ev.dx; + evt.relative_y = ev.dy; + evt.modifiers = but_stat; + evt.message = message; + if (ev.buttons != old_buttons) { + addEvent(&evt); + old_buttons = ev.buttons; + } + } +} +#endif /* __QNXNTO__ */ + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort( + int signo) +{ + char buf[80]; + + EVT_exit(); + sprintf(buf,"Terminating on signal %d",signo); + PM_fatalError(buf); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + int i; + struct stat st; + char *iarg[16]; +#ifdef __QNXNTO__ + char buf[128]; + FILE *p; + int argno,len; +#endif + +#ifdef __QNXNTO__ + ThreadCtl(_NTO_TCTL_IO, 0); /* So joystick code won't blow up */ +#endif + + /* Initialise the event queue */ + EVT.mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + +#ifdef __QNXNTO__ + /* + * User may already have input running with the right parameters. + * Thus they could start input at boot time, using the output of + * inputtrap, passing the the -r flag to make it run as a resource + * manager. + */ + if ((mouse_fd = open("/dev/mouse0", O_RDONLY | O_NONBLOCK)) < 0) { + /* Run inputtrap to get the args for input */ + if ((p = popen("inputtrap", "r")) == NULL) + PM_fatalError("Error running 'inputtrap'"); + fgets(buf, sizeof(buf), p); + pclose(p); + + /* Build the argument list */ + len = strlen(buf); + iarg[0] = buf; + for (i = 0, argno = 0; i < len && argno < 15;) { + if (argno == 1) { + /* + * Add flags to input's arg list. + * '-r' means run as resource + * manager, providing the /dev/mouse + * and /dev/keyboard interfaces. + * '-P' supresses the /dev/photon + * mechanism. + */ + iarg[argno++] = "-Pr"; + continue; + } + while (buf[i] == ' ') + i++; + if (buf[i] == '\0' || buf[i] == '\n') + break; + iarg[argno++] = &buf[i]; + while (buf[i] != ' ' + && buf[i] != '\0' && buf[i] != '\n') + i++; + buf[i++] = '\0'; + } + iarg[argno] = NULL; + + if ((kill_pid = spawnvp(P_NOWAITO, iarg[0], iarg)) == -1) { + perror("spawning input resmgr"); + PM_fatalError("Could not start input resmgr"); + } + for (i = 0; i < 10; i++) { + if (stat("/dev/mouse0", &st) == 0) + break; + sleep(1); + } + if ((mouse_fd = open("/dev/mouse0", O_RDONLY|O_NONBLOCK)) < 0) { + perror("/dev/mouse0"); + PM_fatalError("Could not open /dev/mouse0"); + } + } + if ((kbd_fd = open("/dev/keyboard0", O_RDONLY|O_NONBLOCK)) < 0) { + perror("/dev/keyboard0"); + PM_fatalError("Could not open /dev/keyboard0"); + } +#else + /* Connect to Input/Mouse for event handling */ + if (_PM_mouse_ctl == NULL) { + _PM_mouse_ctl = mouse_open(0, "/dev/mouse", 0); + + /* "Mouse" is not running; attempt to start it */ + if (_PM_mouse_ctl == NULL) { + iarg[0] = "mousetrap"; + iarg[1] = "start"; + iarg[2] = NULL; + if ((kill_pid = spawnvp(P_NOWAITO, iarg[0], (void*)iarg)) == -1) + perror("spawn (mousetrap)"); + else { + for (i = 0; i < 10; i++) { + if (stat("/dev/mouse", &st) == 0) + break; + sleep(1); + } + _PM_mouse_ctl = mouse_open(0, "/dev/mouse", 0); + } + } + } + if (_PM_keyboard_fd == -1) + _PM_keyboard_fd = open("/dev/kbd", O_RDONLY|O_NONBLOCK); +#endif + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +#define _EVT_setMousePos(x,y) + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for QNX */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for QNX */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ +#ifdef __QNXNTO__ + char c; + int flags; + + if (kbd_fd != -1) { + close(kbd_fd); + kbd_fd = -1; + } + if (mouse_fd != -1) { + close(mouse_fd); + mouse_fd = -1; + } +#endif + + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + +#ifndef __QNXNTO__ + /* Kill the Input/Mouse driver if we have spawned it */ + if (_PM_mouse_ctl != NULL) { + struct _fd_entry fde; + uint pid = 0; + + /* Find out the pid of the mouse driver */ + if (kill_pid > 0) { + if (qnx_fd_query(0, + 0, _PM_mouse_ctl->fd, &fde) != -1) + pid = fde.pid; + } + mouse_close(_PM_mouse_ctl); + _PM_mouse_ctl = NULL; + + if (pid > 0) { + /* For some reasons the PID's are different under QNX4, + * so we use the old mechanism to kill the mouse server. + */ + kill(pid, SIGTERM); + kill_pid = 0; + } + } +#endif + if (kill_pid > 0) { + kill(kill_pid, SIGTERM); + kill_pid = 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c new file mode 100644 index 000000000..f960c7571 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/mtrrqnx.c @@ -0,0 +1,182 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: MTRR helper functions module. To make it easier to implement +* the MTRR support under QNX, we simply put our ring 0 helper +* functions into stubs that run them at ring 0 using whatever +* mechanism is available. +* +****************************************************************************/ + +#include "pmapi.h" +#include +#include +#include +#ifdef __QNXNTO__ +#include +#include +#else +#include +#include +#endif + +/*--------------------------- Global variables ----------------------------*/ + +#define R0_FLUSH_TLB 0 +#define R0_SAVE_CR4 1 +#define R0_RESTORE_CR4 2 +#define R0_READ_MSR 3 +#define R0_WRITE_MSR 4 + +typedef struct { + int service; + int reg; + ulong eax; + ulong edx; + } R0_data; + +extern volatile R0_data _PM_R0; + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef __QNXNTO__ +const struct sigevent * _ASMAPI _PM_ring0_isr(void *arg, int id); +#else +pid_t far _ASMAPI _PM_ring0_isr(); +#endif + +/**************************************************************************** +REMARKS: +Return true if ring 0 (or if we can call the helpers functions at ring 0) +****************************************************************************/ +ibool _ASMAPI _MTRR_isRing0(void) +{ +#ifdef __QNXNTO__ + return false; /* Not implemented yet! */ +#else + return true; +#endif +} + +/**************************************************************************** +REMARKS: +Function to execute a service at ring 0. This is done using the clock +interrupt handler since the code we attach to it will always run at ring 0. +****************************************************************************/ +static void CallRing0(void) +{ +#ifdef __QNXNTO__ + uint clock_intno = SYSPAGE_ENTRY(qtime)->intr; +#else + uint clock_intno = 0; /* clock irq */ +#endif + int intrid; + +#ifdef __QNXNTO__ + mlock((void*)&_PM_R0, sizeof(_PM_R0)); + ThreadCtl(_NTO_TCTL_IO, 0); +#endif +#ifdef __QNXNTO__ + if ((intrid = InterruptAttach(_NTO_INTR_CLASS_EXTERNAL | clock_intno, + _PM_ring0_isr, (void*)&_PM_R0, sizeof(_PM_R0), _NTO_INTR_FLAGS_END)) == -1) { +#else + if ((intrid = qnx_hint_attach(clock_intno, _PM_ring0_isr, FP_SEG(&_PM_R0))) == -1) { +#endif + perror("Attach"); + exit(-1); + } + while (_PM_R0.service != -1) + ; +#ifdef __QNXNTO__ + InterruptDetachId(intrid); +#else + qnx_hint_detach(intrid); +#endif +} + +/**************************************************************************** +REMARKS: +Flush the translation lookaside buffer. +****************************************************************************/ +void PMAPI PM_flushTLB(void) +{ + _PM_R0.service = R0_FLUSH_TLB; + CallRing0(); +} + +/**************************************************************************** +REMARKS: +Read and return the value of the CR4 register +****************************************************************************/ +ulong _ASMAPI _MTRR_saveCR4(void) +{ + _PM_R0.service = R0_SAVE_CR4; + CallRing0(); + return _PM_R0.reg; +} + +/**************************************************************************** +REMARKS: +Restore the value of the CR4 register +****************************************************************************/ +void _ASMAPI _MTRR_restoreCR4(ulong cr4Val) +{ + _PM_R0.service = R0_RESTORE_CR4; + _PM_R0.reg = cr4Val; + CallRing0(); +} + +/**************************************************************************** +REMARKS: +Read a machine status register for the CPU. +****************************************************************************/ +void _ASMAPI _MTRR_readMSR( + int reg, + ulong *eax, + ulong *edx) +{ + _PM_R0.service = R0_READ_MSR; + _PM_R0.reg = reg; + CallRing0(); + *eax = _PM_R0.eax; + *edx = _PM_R0.edx; +} + +/**************************************************************************** +REMARKS: +Write a machine status register for the CPU. +****************************************************************************/ +void _ASMAPI _MTRR_writeMSR( + int reg, + ulong eax, + ulong edx) +{ + _PM_R0.service = R0_WRITE_MSR; + _PM_R0.reg = reg; + _PM_R0.eax = eax; + _PM_R0.edx = edx; + CallRing0(); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h new file mode 100644 index 000000000..096119304 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/oshdr.h @@ -0,0 +1,103 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#include +#include +#include +#include +#ifndef __QNXNTO__ +#include +#include +#include +#include +#else +#include + +/* Things 'borrowed' from photon/keycodes.h */ + +/* + * Keyboard modifiers + */ +#define KEYMODBIT_SHIFT 0 +#define KEYMODBIT_CTRL 1 +#define KEYMODBIT_ALT 2 +#define KEYMODBIT_ALTGR 3 +#define KEYMODBIT_SHL3 4 +#define KEYMODBIT_MOD6 5 +#define KEYMODBIT_MOD7 6 +#define KEYMODBIT_MOD8 7 + +#define KEYMODBIT_SHIFT_LOCK 8 +#define KEYMODBIT_CTRL_LOCK 9 +#define KEYMODBIT_ALT_LOCK 10 +#define KEYMODBIT_ALTGR_LOCK 11 +#define KEYMODBIT_SHL3_LOCK 12 +#define KEYMODBIT_MOD6_LOCK 13 +#define KEYMODBIT_MOD7_LOCK 14 +#define KEYMODBIT_MOD8_LOCK 15 + +#define KEYMODBIT_CAPS_LOCK 16 +#define KEYMODBIT_NUM_LOCK 17 +#define KEYMODBIT_SCROLL_LOCK 18 + +#define KEYMOD_SHIFT (1 << KEYMODBIT_SHIFT) +#define KEYMOD_CTRL (1 << KEYMODBIT_CTRL) +#define KEYMOD_ALT (1 << KEYMODBIT_ALT) +#define KEYMOD_ALTGR (1 << KEYMODBIT_ALTGR) +#define KEYMOD_SHL3 (1 << KEYMODBIT_SHL3) +#define KEYMOD_MOD6 (1 << KEYMODBIT_MOD6) +#define KEYMOD_MOD7 (1 << KEYMODBIT_MOD7) +#define KEYMOD_MOD8 (1 << KEYMODBIT_MOD8) + +#define KEYMOD_SHIFT_LOCK (1 << KEYMODBIT_SHIFT_LOCK) +#define KEYMOD_CTRL_LOCK (1 << KEYMODBIT_CTRL_LOCK) +#define KEYMOD_ALT_LOCK (1 << KEYMODBIT_ALT_LOCK) +#define KEYMOD_ALTGR_LOCK (1 << KEYMODBIT_ALTGR_LOCK) +#define KEYMOD_SHL3_LOCK (1 << KEYMODBIT_SHL3_LOCK) +#define KEYMOD_MOD6_LOCK (1 << KEYMODBIT_MOD6_LOCK) +#define KEYMOD_MOD7_LOCK (1 << KEYMODBIT_MOD7_LOCK) +#define KEYMOD_MOD8_LOCK (1 << KEYMODBIT_MOD8_LOCK) + +#define KEYMOD_CAPS_LOCK (1 << KEYMODBIT_CAPS_LOCK) +#define KEYMOD_NUM_LOCK (1 << KEYMODBIT_NUM_LOCK) +#define KEYMOD_SCROLL_LOCK (1 << KEYMODBIT_SCROLL_LOCK) + +/* + * Keyboard flags + */ +#define KEY_DOWN 0x00000001 /* Key was pressed down */ +#define KEY_REPEAT 0x00000002 /* Key was repeated */ +#define KEY_SCAN_VALID 0x00000020 /* Scancode is valid */ +#define KEY_SYM_VALID 0x00000040 /* Key symbol is valid */ +#define KEY_CAP_VALID 0x00000080 /* Key cap is valid */ +#define KEY_DEAD 0x40000000 /* Key symbol is a DEAD key */ +#define KEY_OEM_CAP 0x80000000 /* Key cap is an OEM scan code from keyboard */ + +#endif /* __QNXNTO__ */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c new file mode 100644 index 000000000..c993ee083 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/pm.c @@ -0,0 +1,891 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "mtrr.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qnx/vbios.h" +#ifndef __QNXNTO__ +#include +#include +#include +#include +#else +#include +#include +#endif + +/*--------------------------- Global variables ----------------------------*/ + +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +static VBIOSregs_t *VRegs = NULL; /* Pointer to VBIOS registers */ +static int raw_count = 0; +static struct _console_ctrl *cc = NULL; +static int console_count = 0; +static int rmbuf_inuse = 0; + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +void PMAPI PM_init(void) +{ + char *force; + + if (VRegs == NULL) { +#ifdef __QNXNTO__ + ThreadCtl(_NTO_TCTL_IO, 0); /* Get IO privilidge */ +#endif + force = getenv("VBIOS_METHOD"); + VRegs = VBIOSinit(force ? atoi(force) : 0); + } +#ifndef __QNXNTO__ + MTRR_init(); +#endif +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return VRegs != NULL; } + +long PMAPI PM_getOSType(void) +{ return _OS_QNX; } + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '/') { + s[pos] = '/'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + fprintf(stderr,"%s\n", msg); + exit(1); +} + +static void ExitVBEBuf(void) +{ + if (VESABuf_ptr) + PM_freeRealSeg(VESABuf_ptr); + VESABuf_ptr = 0; +} + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) +{ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + atexit(ExitVBEBuf); + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +static int term_raw(void) +{ + struct termios termios_p; + + if (raw_count++ > 0) + return 0; + + /* Go into "raw" input mode */ + if (tcgetattr(STDIN_FILENO, &termios_p)) + return -1; + + termios_p.c_cc[VMIN] = 1; + termios_p.c_cc[VTIME] = 0; + termios_p.c_lflag &= ~( ECHO|ICANON|ISIG|ECHOE|ECHOK|ECHONL); + tcsetattr(STDIN_FILENO, TCSADRAIN, &termios_p); + return 0; +} + +static void term_restore(void) +{ + struct termios termios_p; + + if (raw_count-- != 1) + return; + + tcgetattr(STDIN_FILENO, &termios_p); + termios_p.c_lflag |= (ECHO|ICANON|ISIG|ECHOE|ECHOK|ECHONL); + termios_p.c_oflag |= (OPOST); + tcsetattr(STDIN_FILENO, TCSADRAIN, &termios_p); +} + +int PMAPI PM_kbhit(void) +{ + int blocking, c; + + if (term_raw() == -1) + return 0; + + /* Go into non blocking mode */ + blocking = fcntl(STDIN_FILENO, F_GETFL) | O_NONBLOCK; + fcntl(STDIN_FILENO, F_SETFL, blocking); + c = getc(stdin); + + /* restore blocking mode */ + fcntl(STDIN_FILENO, F_SETFL, blocking & ~O_NONBLOCK); + term_restore(); + if (c != EOF) { + ungetc(c, stdin); + return c; + } + clearerr(stdin); + return 0; +} + +int PMAPI PM_getch(void) +{ + int c; + + if (term_raw() == -1) + return (0); + c = getc(stdin); +#if defined(__QNX__) && !defined(__QNXNTO__) + if (c == 0xA) + c = 0x0D; + else if (c == 0x7F) + c = 0x08; +#endif + term_restore(); + return c; +} + +PM_HWND PMAPI PM_openConsole( + PM_HWND hwndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ +#ifndef __QNXNTO__ + int fd; + + if (console_count++) + return 0; + if ((fd = open("/dev/con1", O_RDWR)) == -1) + return -1; + cc = console_open(fd, O_RDWR); + close(fd); + if (cc == NULL) + return -1; +#endif + return 1; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + return PM_getVGAStateSize() + sizeof(int) * 3; +} + +void PMAPI PM_saveConsoleState(void *stateBuf,int console_id) +{ +#ifdef __QNXNTO__ + int fd; + int flags; + + if ((fd = open("/dev/con1", O_RDWR)) == -1) + return; + flags = _CONCTL_INVISIBLE_CHG | _CONCTL_INVISIBLE; + devctl(fd, DCMD_CHR_SERCTL, &flags, sizeof flags, 0); + close(fd); +#else + uchar *buf = &((uchar*)stateBuf)[PM_getVGAStateSize()]; + + /* Save QNX 4 console state */ + console_read(cc, -1, 0, NULL, 0, + (int *)buf+1, (int *)buf+2, NULL); + *(int *)buf = console_ctrl(cc, -1, + CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE, + CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE); + + /* Save state of VGA registers */ + PM_saveVGAState(stateBuf); +#endif +} + +void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) +{ + /* TODO: Implement support for console switching if possible */ +} + +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) +{ +#ifdef __QNXNTO__ + int fd; + int flags; + + if ((fd = open("/dev/con1", O_RDWR)) == -1) + return; + flags = _CONCTL_INVISIBLE_CHG; + devctl(fd, DCMD_CHR_SERCTL, &flags, sizeof flags, 0); + close(fd); +#else + uchar *buf = &((uchar*)stateBuf)[PM_getVGAStateSize()]; + + /* Restore the state of the VGA compatible registers */ + PM_restoreVGAState(stateBuf); + + /* Restore QNX 4 console state */ + console_ctrl(cc, -1, *(int *)buf, + CONSOLE_NORESIZE | CONSOLE_NOSWITCH | CONSOLE_INVISIBLE); + console_write(cc, -1, 0, NULL, 0, + (int *)buf+1, (int *)buf+2, NULL); +#endif +} + +void PMAPI PM_closeConsole(PM_HWND hwndConsole) +{ +#ifndef __QNXNTO__ + if (--console_count == 0) { + console_close(cc); + cc = NULL; + } +#endif +} + +void PM_setOSCursorLocation(int x,int y) +{ + if (!cc) + return; +#ifndef __QNXNTO__ + console_write(cc, -1, 0, NULL, 0, &y, &x, NULL); +#endif +} + +void PM_setOSScreenWidth(int width,int height) +{ +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler ih, int frequency) +{ + /* TODO: Implement this for QNX */ + return false; +} + +void PMAPI PM_setRealTimeClockFrequency(int frequency) +{ + /* TODO: Implement this for QNX */ +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* TODO: Implement this for QNX */ +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +char PMAPI PM_getBootDrive(void) +{ return '/'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return PM_getNucleusConfigPath(); } + +const char * PMAPI PM_getNucleusPath(void) +{ + char *env = getenv("NUCLEUS_PATH"); +#ifdef __QNXNTO__ +#ifdef __X86__ + return env ? env : "/nto/scitech/x86/bin"; +#elif defined (__PPC__) + return env ? env : "/nto/scitech/ppcbe/bin"; +#elif defined (__MIPS__) +#ifdef __BIGENDIAN__ + return env ? env : "/nto/scitech/mipsbe/bin"; +#else + return env ? env : "/nto/scitech/mipsle/bin"; +#endif +#elif defined (__SH__) +#ifdef __BIGENDIAN__ + return env ? env : "/nto/scitech/shbe/bin"; +#else + return env ? env : "/nto/scitech/shle/bin"; +#endif +#elif defined (__ARM__) + return env ? env : "/nto/scitech/armle/bin"; +#endif +#else /* QNX 4 */ + return env ? env : "/qnx4/scitech/bin"; +#endif +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[512]; + char *env; +#ifdef __QNXNTO__ + char temp[64]; + gethostname(temp, sizeof (temp)); + temp[sizeof (temp) - 1] = '\0'; /* Paranoid */ + sprintf(path,"/etc/config/scitech/%s/config", temp); +#else + sprintf(path,"/etc/config/scitech/%d/config", getnid()); +#endif + if ((env = getenv("NUCLEUS_PATH")) != NULL) { + strcpy(path,env); + PM_backslash(path); + strcat(path,"config"); + } + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ + static char buf[128]; +#ifdef __QNXNTO__ + gethostname(buf, sizeof (buf)); +#else + sprintf(buf,"node%d", getnid()); +#endif + return buf; +} + +const char * PMAPI PM_getMachineName(void) +{ + static char buf[128]; +#ifdef __QNXNTO__ + gethostname(buf, sizeof (buf)); +#else + sprintf(buf,"node%d", getnid()); +#endif + return buf; +} + +void * PMAPI PM_getBIOSPointer(void) +{ + return PM_mapRealPointer(0, 0x400); +} + +void * PMAPI PM_getA0000Pointer(void) +{ + static void *ptr = NULL; + void *freeptr; + unsigned offset, i, maplen; + + if (ptr != NULL) + return ptr; + + /* Some trickery is required to get the linear address 64K aligned */ + for (i = 0; i < 5; i++) { + ptr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); + offset = 0x10000 - ((unsigned)ptr % 0x10000); + if (!offset) + break; + munmap(ptr, 0x10000); + maplen = 0x10000 + offset; + freeptr = PM_mapPhysicalAddr(0xA0000-offset, maplen-1,true); + ptr = (void *)(offset + (unsigned)freeptr); + if (0x10000 - ((unsigned)ptr % 0x10000)) + break; + munmap(freeptr, maplen); + } + if (i == 5) { + printf("Could not get a 64K aligned linear address for A0000 region\n"); + exit(1); + } + return ptr; +} + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + uchar_t *p; + unsigned o; + unsigned prot = PROT_READ|PROT_WRITE|(isCached?0:PROT_NOCACHE); +#ifdef __PAGESIZE + int pagesize = __PAGESIZE; +#else + int pagesize = 4096; +#endif + int rounddown = base % pagesize; +#ifndef __QNXNTO__ + static int __VidFD = -1; +#endif + + if (rounddown) { + if (base < rounddown) + return NULL; + base -= rounddown; + limit += rounddown; + } + +#ifndef __QNXNTO__ + if (__VidFD < 0) { + if ((__VidFD = shm_open( "Physical", O_RDWR, 0777 )) == -1) { + perror( "Cannot open Physical memory" ); + exit(1); + } + } + o = base & 0xFFF; + limit = (limit + o + 0xFFF) & ~0xFFF; + if ((int)(p = mmap( 0, limit, prot, MAP_SHARED, + __VidFD, base )) == -1 ) { + return NULL; + } + p += o; +#else + if ((p = mmap(0, limit, prot, MAP_PHYS | MAP_SHARED, + NOFD, base)) == MAP_FAILED) { + return (void *)-1; + } +#endif + return (p + rounddown); +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + munmap(ptr,limit+1); +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + /* TODO: Implement this! */ + return false; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* TODO: Put the process to sleep for milliseconds */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +void * PMAPI PM_mallocShared(long size) +{ + return PM_malloc(size); +} + +void PMAPI PM_freeShared(void *ptr) +{ + PM_free(ptr); +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + void *p; + + PM_init(); + + if ((p = VBIOSgetmemptr(r_seg, r_off, VRegs)) == (void *)-1) + return NULL; + return p; +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + if (size > 1024) { + printf("PM_allocRealSeg: can't handle %d bytes\n", size); + return 0; + } + if (rmbuf_inuse != 0) { + printf("PM_allocRealSeg: transfer area already in use\n"); + return 0; + } + PM_init(); + rmbuf_inuse = 1; + *r_seg = VBIOS_TransBufVSeg(VRegs); + *r_off = VBIOS_TransBufVOff(VRegs); + return (void*)VBIOS_TransBufPtr(VRegs); +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + if (rmbuf_inuse == 0) { + printf("PM_freeRealSeg: nothing was allocated\n"); + return; + } + rmbuf_inuse = 0; +} + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + PM_init(); + if (VRegs == NULL) + return; + + VRegs->l.eax = regs->eax; + VRegs->l.ebx = regs->ebx; + VRegs->l.ecx = regs->ecx; + VRegs->l.edx = regs->edx; + VRegs->l.esi = regs->esi; + VRegs->l.edi = regs->edi; + + VBIOSint(intno, VRegs, 1024); + + regs->eax = VRegs->l.eax; + regs->ebx = VRegs->l.ebx; + regs->ecx = VRegs->l.ecx; + regs->edx = VRegs->l.edx; + regs->esi = VRegs->l.esi; + regs->edi = VRegs->l.edi; + regs->flags = VRegs->w.flags & 0x1; +} + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + PM_init(); + if (VRegs == NULL) + return 0; + + VRegs->l.eax = in->e.eax; + VRegs->l.ebx = in->e.ebx; + VRegs->l.ecx = in->e.ecx; + VRegs->l.edx = in->e.edx; + VRegs->l.esi = in->e.esi; + VRegs->l.edi = in->e.edi; + + VBIOSint(intno, VRegs, 1024); + + out->e.eax = VRegs->l.eax; + out->e.ebx = VRegs->l.ebx; + out->e.ecx = VRegs->l.ecx; + out->e.edx = VRegs->l.edx; + out->e.esi = VRegs->l.esi; + out->e.edi = VRegs->l.edi; + out->x.cflag = VRegs->w.flags & 0x1; + + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + PM_init(); + if (VRegs == NULL) + return 0; + + if (intno == 0x21) { + time_t today = time(NULL); + struct tm *t; + t = localtime(&today); + out->x.cx = t->tm_year + 1900; + out->h.dh = t->tm_mon + 1; + out->h.dl = t->tm_mday; + return 0; + } + else { + VRegs->l.eax = in->e.eax; + VRegs->l.ebx = in->e.ebx; + VRegs->l.ecx = in->e.ecx; + VRegs->l.edx = in->e.edx; + VRegs->l.esi = in->e.esi; + VRegs->l.edi = in->e.edi; + VRegs->w.es = sregs->es; + VRegs->w.ds = sregs->ds; + + VBIOSint(intno, VRegs, 1024); + + out->e.eax = VRegs->l.eax; + out->e.ebx = VRegs->l.ebx; + out->e.ecx = VRegs->l.ecx; + out->e.edx = VRegs->l.edx; + out->e.esi = VRegs->l.esi; + out->e.edi = VRegs->l.edi; + out->x.cflag = VRegs->w.flags & 0x1; + sregs->es = VRegs->w.es; + sregs->ds = VRegs->w.ds; + + return out->x.ax; + } +} + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, + RMSREGS *sregs) +{ + PM_init(); + if (VRegs == NULL) + return; + + VRegs->l.eax = in->e.eax; + VRegs->l.ebx = in->e.ebx; + VRegs->l.ecx = in->e.ecx; + VRegs->l.edx = in->e.edx; + VRegs->l.esi = in->e.esi; + VRegs->l.edi = in->e.edi; + VRegs->w.es = sregs->es; + VRegs->w.ds = sregs->ds; + + VBIOScall(seg, off, VRegs, 1024); + + in->e.eax = VRegs->l.eax; + in->e.ebx = VRegs->l.ebx; + in->e.ecx = VRegs->l.ecx; + in->e.edx = VRegs->l.edx; + in->e.esi = VRegs->l.esi; + in->e.edi = VRegs->l.edi; + in->x.cflag = VRegs->w.flags & 0x1; + sregs->es = VRegs->w.es; + sregs->ds = VRegs->w.ds; +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ +#ifndef __QNXNTO__ + *physical = *total = _memavl(); +#endif +} + +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + /* TODO: Implement this on QNX */ + return NULL; +} + +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + /* TODO: Implement this on QNX */ +} + +void * PMAPI PM_allocPage( + ibool locked) +{ + /* TODO: Implement this on QNX */ + return NULL; +} + +void PMAPI PM_freePage( + void *p) +{ + /* TODO: Implement this on QNX */ +} + +void PMAPI PM_setBankA(int bank) +{ + PM_init(); + if (VRegs == NULL) + return; + + VRegs->l.eax = 0x4F05; + VRegs->l.ebx = 0x0000; + VRegs->l.edx = bank; + VBIOSint(0x10, VRegs, 1024); +} + +void PMAPI PM_setBankAB(int bank) +{ + PM_init(); + if (VRegs == NULL) + return; + + VRegs->l.eax = 0x4F05; + VRegs->l.ebx = 0x0000; + VRegs->l.edx = bank; + VBIOSint(0x10, VRegs, 1024); + + VRegs->l.eax = 0x4F05; + VRegs->l.ebx = 0x0001; + VRegs->l.edx = bank; + VBIOSint(0x10, VRegs, 1024); +} + +void PMAPI PM_setCRTStart(int x,int y,int waitVRT) +{ + PM_init(); + if (VRegs == NULL) + return; + + VRegs->l.eax = 0x4F07; + VRegs->l.ebx = waitVRT; + VRegs->l.ecx = x; + VRegs->l.edx = y; + VBIOSint(0x10, VRegs, 1024); +} + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *copyOfBIOS, + ulong BIOSLen) +{ + (void)axVal; + (void)BIOSPhysAddr; + (void)copyOfBIOS; + (void)BIOSLen; + return false; +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + p = p; len = len; + return 1; +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* TODO: Implement this to load shared libraries! */ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* TODO: Implement this! */ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* TODO: Implement this! */ + (void)hModule; +} + +int PMAPI PM_setIOPL( + int level) +{ + /* QNX handles IOPL selection at the program link level. */ + return level; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ +#ifndef __QNXNTO__ + return MTRR_enableWriteCombine(base,size,type); +#else + return PM_MTRR_NOT_SUPPORTED; +#endif +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c new file mode 100644 index 000000000..579ef2c95 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c new file mode 100644 index 000000000..d2740971f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/qnx/ztimer.c @@ -0,0 +1,91 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: QNX +* +* Description: QNX specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ +} + +/**************************************************************************** +REMARKS: +Use the gettimeofday() function to get microsecond precision (probably less +though) +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + struct timespec ts; + clock_gettime(CLOCK_REALTIME, &ts); + return (ts.tv_nsec / 1000 + ts.tv_sec * 1000000); +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +#define __LZTimerOn(tm) tm->start.low = __ULZReadTime() + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +#define __LZTimerLap(tm) (__ULZReadTime() - tm->start.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) tm->end.low = __ULZReadTime() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerCount(tm) (tm->end.low - tm->start.low) + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1 + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c new file mode 100644 index 000000000..4f32c3e88 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/cpuinfo.c @@ -0,0 +1,94 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: Module to implement OS specific services to measure the +* CPU frequency. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static ibool havePerformanceCounter; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Increase the thread priority to maximum, if possible. +****************************************************************************/ +static int SetMaxThreadPriority(void) +{ + int oldPriority; + HANDLE hThread = GetCurrentThread(); + + oldPriority = GetThreadPriority(hThread); + if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) + SetThreadPriority(hThread, THREAD_PRIORITY_TIME_CRITICAL); + return oldPriority; +} + +/**************************************************************************** +REMARKS: +Restore the original thread priority. +****************************************************************************/ +static void RestoreThreadPriority( + int oldPriority) +{ + HANDLE hThread = GetCurrentThread(); + + if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) + SetThreadPriority(hThread, oldPriority); +} + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + if (!QueryPerformanceFrequency((LARGE_INTEGER*)freq)) { + havePerformanceCounter = false; + freq->low = 100000; + freq->high = 0; + } + else + havePerformanceCounter = true; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + if (havePerformanceCounter) \ + QueryPerformanceCounter((LARGE_INTEGER*)t); \ + else { \ + (t)->low = timeGetTime() * 100; \ + (t)->high = 0; \ + } \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c new file mode 100644 index 000000000..962a14a3c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/event.c @@ -0,0 +1,287 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: Win32 implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static ushort keyUpMsg[256] = {0}; /* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under Win32 */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ return timeGetTime(); } + +/**************************************************************************** +REMARKS: +Pumps all messages in the message queue from Win32 into our event queue. +****************************************************************************/ +void _EVT_pumpMessages(void) +{ + MSG msg; + MSG charMsg; + event_t evt; + + while (PeekMessage(&msg,NULL,0,0,PM_REMOVE)) { + memset(&evt,0,sizeof(evt)); + switch (msg.message) { + case WM_MOUSEMOVE: + evt.what = EVT_MOUSEMOVE; + break; + case WM_LBUTTONDBLCLK: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_LEFTBMASK | EVT_DBLCLICK; + break; + case WM_LBUTTONDOWN: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_LEFTBMASK; + break; + case WM_LBUTTONUP: + evt.what = EVT_MOUSEUP; + evt.message = EVT_LEFTBMASK; + break; + case WM_RBUTTONDBLCLK: + evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK; + evt.message = EVT_RIGHTBMASK; + break; + case WM_RBUTTONDOWN: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_RIGHTBMASK; + break; + case WM_RBUTTONUP: + evt.what = EVT_MOUSEUP; + evt.message = EVT_RIGHTBMASK; + break; + case WM_KEYDOWN: + case WM_SYSKEYDOWN: + if (HIWORD(msg.lParam) & KF_REPEAT) { + evt.what = EVT_KEYREPEAT; + } + else { + evt.what = EVT_KEYDOWN; + } + break; + case WM_KEYUP: + case WM_SYSKEYUP: + evt.what = EVT_KEYUP; + break; + } + + /* Convert mouse event modifier flags */ + if (evt.what & EVT_MOUSEEVT) { + evt.where_x = msg.pt.x; + evt.where_y = msg.pt.y; + if (evt.what == EVT_MOUSEMOVE) { + if (oldMove != -1) { + evtq[oldMove].where_x = evt.where_x;/* Modify existing one */ + evtq[oldMove].where_y = evt.where_y; + evt.what = 0; + } + else { + oldMove = freeHead; /* Save id of this move event */ + } + } + else + oldMove = -1; + if (msg.wParam & MK_LBUTTON) + evt.modifiers |= EVT_LEFTBUT; + if (msg.wParam & MK_RBUTTON) + evt.modifiers |= EVT_RIGHTBUT; + if (msg.wParam & MK_SHIFT) + evt.modifiers |= EVT_SHIFTKEY; + if (msg.wParam & MK_CONTROL) + evt.modifiers |= EVT_CTRLSTATE; + } + + /* Convert keyboard codes */ + TranslateMessage(&msg); + if (evt.what & EVT_KEYEVT) { + int scanCode = (msg.lParam >> 16) & 0xFF; + if (evt.what == EVT_KEYUP) { + /* Get message for keyup code from table of cached down values */ + evt.message = keyUpMsg[scanCode]; + keyUpMsg[scanCode] = 0; + } + else { + if (PeekMessage(&charMsg,NULL,WM_CHAR,WM_CHAR,PM_REMOVE)) + evt.message = charMsg.wParam; + if (PeekMessage(&charMsg,NULL,WM_SYSCHAR,WM_SYSCHAR,PM_REMOVE)) + evt.message = charMsg.wParam; + evt.message |= ((msg.lParam >> 8) & 0xFF00); + keyUpMsg[scanCode] = (ushort)evt.message; + } + if (evt.what == EVT_KEYREPEAT) + evt.message |= (msg.lParam << 16); + if (HIWORD(msg.lParam) & KF_ALTDOWN) + evt.modifiers |= EVT_ALTSTATE; + if (GetKeyState(VK_SHIFT) & 0x8000U) + evt.modifiers |= EVT_SHIFTKEY; + if (GetKeyState(VK_CONTROL) & 0x8000U) + evt.modifiers |= EVT_CTRLSTATE; + oldMove = -1; + } + + if (evt.what != 0) { + /* Add time stamp and add the event to the queue */ + evt.when = msg.time; + if (count < EVENTQSIZE) { + addEvent(&evt); + } + } + DispatchMessage(&msg); + } +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + /* Initialise the event queue */ + _mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +void _EVT_setMousePos( + int *x, + int *y) +{ + SetCursorPos(*x,*y); +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for Win32 */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for Win32 */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h new file mode 100644 index 000000000..1352dadad --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/oshdr.h @@ -0,0 +1,34 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#include diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c new file mode 100644 index 000000000..47d7ed6ab --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/pm.c @@ -0,0 +1,701 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include +#include +#include +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#include +#ifdef __BORLANDC__ +#pragma warn -par +#endif + +/*--------------------------- Global variables ----------------------------*/ + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +void MTRR_init(void); + +/**************************************************************************** +REMARKS: +Initialise the PM library. +****************************************************************************/ +void PMAPI PM_init(void) +{ + /* TODO: dO any special init code in here. */ + MTRR_init(); +} + +/**************************************************************************** +REMARKS: +Return the operating system type identifier. +****************************************************************************/ +long PMAPI PM_getOSType(void) +{ + return _OS_RTTARGET; +} + +/**************************************************************************** +REMARKS: +Return the runtime type identifier. +****************************************************************************/ +int PMAPI PM_getModeType(void) +{ + return PM_386; +} + +/**************************************************************************** +REMARKS: +Add a file directory separator to the end of the filename. +****************************************************************************/ +void PMAPI PM_backslash( + char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +/**************************************************************************** +REMARKS: +Add a user defined PM_fatalError cleanup function. +****************************************************************************/ +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +/**************************************************************************** +REMARKS: +Report a fatal error condition and halt the program. +****************************************************************************/ +void PMAPI PM_fatalError( + const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + /* TODO: Display a fatal error message and exit! */ +/* MessageBox(NULL,msg,"Fatal Error!", MB_ICONEXCLAMATION); */ + exit(1); +} + +/**************************************************************************** +REMARKS: +Allocate the real mode VESA transfer buffer for communicating with the BIOS. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + /* No BIOS access for the RTTarget */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Check if a key has been pressed. +****************************************************************************/ +int PMAPI PM_kbhit(void) +{ + /* TODO: Need to check if a key is waiting on the keyboard queue */ + return true; +} + +/**************************************************************************** +REMARKS: +Wait for and return the next keypress. +****************************************************************************/ +int PMAPI PM_getch(void) +{ + /* TODO: Need to obtain the next keypress, and block until one is hit */ + return 0xD; +} + +/**************************************************************************** +REMARKS: +Set the location of the OS console cursor. +****************************************************************************/ +void PM_setOSCursorLocation( + int x, + int y) +{ + /* Nothing to do for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Set the width of the OS console. +****************************************************************************/ +void PM_setOSScreenWidth( + int width, + int height) +{ + /* Nothing to do for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Set the real time clock handler (used for software stereo modes). +****************************************************************************/ +ibool PMAPI PM_setRealTimeClockHandler( + PM_intHandler ih, + int frequency) +{ + /* Not supported for RTTarget-32 */ + return false; +} + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + /* Not supported under RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Restore the original real time clock handler. +****************************************************************************/ +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* Not supported under RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Return the current operating system path or working directory. +****************************************************************************/ +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +/**************************************************************************** +REMARKS: +Return the drive letter for the boot drive. +****************************************************************************/ +char PMAPI PM_getBootDrive(void) +{ + return 'c'; +} + +/**************************************************************************** +REMARKS: +Return the path to the VBE/AF driver files. +****************************************************************************/ +const char * PMAPI PM_getVBEAFPath(void) +{ + return "c:\\"; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus driver files. +****************************************************************************/ +const char * PMAPI PM_getNucleusPath(void) +{ + /* TODO: Point this at the path when the Nucleus drivers will be found */ + return "c:\\nucleus"; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus configuration files. +****************************************************************************/ +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +/**************************************************************************** +REMARKS: +Return a unique identifier for the machine if possible. +****************************************************************************/ +const char * PMAPI PM_getUniqueID(void) +{ + return PM_getMachineName(); +} + +/**************************************************************************** +REMARKS: +Get the name of the machine on the network. +****************************************************************************/ +const char * PMAPI PM_getMachineName(void) +{ + /* Not necessary for RTTarget-32 */ + return "Unknown"; +} + +/**************************************************************************** +REMARKS: +Return a pointer to the real mode BIOS data area. +****************************************************************************/ +void * PMAPI PM_getBIOSPointer(void) +{ + /* Not used for RTTarget-32 */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Return a pointer to 0xA0000 physical VGA graphics framebuffer. +****************************************************************************/ +void * PMAPI PM_getA0000Pointer(void) +{ + static void *bankPtr; + if (!bankPtr) + bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); + return bankPtr; +} + +/**************************************************************************** +REMARKS: +Map a physical address to a linear address in the callers process. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + /* TODO: Map a physical memory address to a linear address */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a physical address mapping allocated by PM_mapPhysicalAddr. +****************************************************************************/ +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + /* TODO: Free the physical address mapping */ +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + Sleep(milliseconds); +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of (unnamed) shared memory. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + return PM_malloc(size); +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory. +****************************************************************************/ +void PMAPI PM_freeShared( + void *ptr) +{ + PM_free(ptr); +} + +/**************************************************************************** +REMARKS: +Map a linear memory address to the calling process address space. The +address will have been allocated in another process using the +PM_mapPhysicalAddr function. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + return base; +} + +/**************************************************************************** +REMARKS: +Map a real mode pointer to a protected mode pointer. +****************************************************************************/ +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + /* Not used for RTTarget-32 */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Allocate a block of real mode memory +****************************************************************************/ +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + /* Not used for RTTarget-32 */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of real mode memory. +****************************************************************************/ +void PMAPI PM_freeRealSeg( + void *mem) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt (parameters in DPMI compatible structure) +****************************************************************************/ +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + /* Not used for RTTarget-32 */ + return 0; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + /* Not used for RTTarget-32 */ + return 0; +} + +/**************************************************************************** +REMARKS: +Call a real mode far function. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *in, + RMSREGS *sregs) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Return the amount of available memory. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + /* TODO: Figure out how to determine the available memory. Not entirely */ + /* critical so returning 0 is OK. */ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of locked, physical memory for DMA operations. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + /* TODO: Allocate a block of locked, phsyically contigous memory for DMA */ + return 0; +} + +/**************************************************************************** +REMARKS: +Free a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + + ibool contiguous) +{ + /* TODO: Free a locked memory buffer */ +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankA( + int bank) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankAB( + int bank) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display start address. +****************************************************************************/ +void PMAPI PM_setCRTStart( + int x, + int y, + int waitVRT) +{ + /* Not used for RTTarget-32 */ +} + +/**************************************************************************** +REMARKS: +Execute the POST on the secondary BIOS for a controller. +****************************************************************************/ +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS) +{ + /* Not used for RTTarget-32 */ + return false; +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* TODO: Implement this to load shared libraries! */ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* TODO: Implement this! */ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* TODO: Implement this! */ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +ulong PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + /* TODO: This function should start a directory enumeration search */ + /* given the filename (with wildcards). The data should be */ + /* converted and returned in the findData standard form. */ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + ulong handle, + PM_findData *findData) +{ + /* TODO: This function should find the next file in directory enumeration */ + /* search given the search criteria defined in the call to */ + /* PM_findFirstFile. The data should be converted and returned */ + /* in the findData standard form. */ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + ulong handle) +{ + /* TODO: This function should close the find process. This may do */ + /* nothing for some OS'es. */ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + if (drive == 3) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + (void)drive; + getcwd(dir,len); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + /* TODO: Set the file attributes for a file */ + (void)filename; + (void)attrib; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + return mkdir(filename) == 0; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return rmdir(filename) == 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c new file mode 100644 index 000000000..dd9dfe682 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/vflat.c @@ -0,0 +1,48 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" +#ifdef __BORLANDC__ +#pragma warn -par +#endif + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c new file mode 100644 index 000000000..80c184dff --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/rttarget/ztimer.c @@ -0,0 +1,136 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: RTTarget-32 +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static CPU_largeInteger countFreq; +static ibool havePerformanceCounter; +static ulong start,finish; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ +#ifdef NO_ASSEMBLER + havePerformanceCounter = false; +#else + havePerformanceCounter = QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq); +#endif +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOn( + LZTimerObject *tm) +{ + if (havePerformanceCounter) + QueryPerformanceCounter((LARGE_INTEGER*)&tm->start); + else + tm->start.low = timeGetTime(); +} + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + CPU_largeInteger tmLap,tmCount; + + if (havePerformanceCounter) { + QueryPerformanceCounter((LARGE_INTEGER*)&tmLap); + _CPU_diffTime64(&tm->start,&tmLap,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); + } + else { + tmLap.low = timeGetTime(); + return (tmLap.low - tm->start.low) * 1000L; + } +} + +/**************************************************************************** +REMARKS: +Stop the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOff( + LZTimerObject *tm) +{ + if (havePerformanceCounter) + QueryPerformanceCounter((LARGE_INTEGER*)&tm->end); + else + tm->end.low = timeGetTime(); +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time in microseconds between start and end timings. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + + if (havePerformanceCounter) { + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); + } + else + return (tm->end.low - tm->start.low) * 1000L; +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1000 + +/**************************************************************************** +REMARKS: +Read the Long Period timer from the OS +****************************************************************************/ +static ulong __ULZReadTime(void) +{ return timeGetTime(); } + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm new file mode 100644 index 000000000..da62b1f71 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_event.asm @@ -0,0 +1,175 @@ +;**************************************************************************** +;* +;* SciTech Multi-platform Graphics Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler +;* Environment: IBM PC (MS DOS) +;* +;* Description: Assembly language support routines for the event module. +;* +;**************************************************************************** + + ideal + +include "scitech.mac" ; Memory model macros + +ifdef flatmodel + +header _event ; Set up memory model + +begdataseg _event + + cextern _EVT_biosPtr,DPTR + + cpublic _EVT_dataStart + +ifdef USE_NASM +%define KB_HEAD WORD esi+01Ah ; Keyboard buffer head in BIOS data area +%define KB_TAIL WORD esi+01Ch ; Keyboard buffer tail in BIOS data area +%define KB_START WORD esi+080h ; Start of keyboard buffer in BIOS data area +%define KB_END WORD esi+082h ; End of keyboard buffer in BIOS data area +else +KB_HEAD EQU WORD esi+01Ah ; Keyboard buffer head in BIOS data area +KB_TAIL EQU WORD esi+01Ch ; Keyboard buffer tail in BIOS data area +KB_START EQU WORD esi+080h ; Start of keyboard buffer in BIOS data area +KB_END EQU WORD esi+082h ; End of keyboard buffer in BIOS data area +endif + + cpublic _EVT_dataEnd + +enddataseg _event + +begcodeseg _event ; Start of code segment + + cpublic _EVT_codeStart + +;---------------------------------------------------------------------------- +; int _EVT_getKeyCode(void) +;---------------------------------------------------------------------------- +; Returns the key code for the next available key by extracting it from +; the BIOS keyboard buffer. +;---------------------------------------------------------------------------- +cprocstart _EVT_getKeyCode + + enter_c + + mov esi,[_EVT_biosPtr] + xor ebx,ebx + xor eax,eax + mov bx,[KB_HEAD] + cmp bx,[KB_TAIL] + jz @@Done + xor eax,eax + mov ax,[esi+ebx] ; EAX := character from keyboard buffer + inc _bx + inc _bx + cmp bx,[KB_END] ; Hit the end of the keyboard buffer? + jl @@1 + mov bx,[KB_START] +@@1: mov [KB_HEAD],bx ; Update keyboard buffer head pointer + +@@Done: leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _EVT_disableInt(void); +;---------------------------------------------------------------------------- +; Return processor interrupt status and disable interrupts. +;---------------------------------------------------------------------------- +cprocstart _EVT_disableInt + + pushf ; Put flag word on stack + cli ; Disable interrupts! + pop eax ; deposit flag word in return register + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _EVT_restoreInt(int ps); +;---------------------------------------------------------------------------- +; Restore processor interrupt status. +;---------------------------------------------------------------------------- +cprocstart _EVT_restoreInt + + ARG ps:UINT + + push ebp + mov ebp,esp ; Set up stack frame + push [DWORD ps] + popf ; Restore processor status (and interrupts) + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; int EVT_rdinx(int port,int index) +;---------------------------------------------------------------------------- +; Reads an indexed register value from an I/O port. +;---------------------------------------------------------------------------- +cprocstart EVT_rdinx + + ARG port:UINT, index:UINT + + push ebp + mov ebp,esp + mov edx,[port] + mov al,[BYTE index] + out dx,al + inc dx + in al,dx + movzx eax,al + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void EVT_wrinx(int port,int index,int value) +;---------------------------------------------------------------------------- +; Writes an indexed register value to an I/O port. +;---------------------------------------------------------------------------- +cprocstart EVT_wrinx + + ARG port:UINT, index:UINT, value:UINT + + push ebp + mov ebp,esp + mov edx,[port] + mov al,[BYTE index] + mov ah,[BYTE value] + out dx,ax + pop ebp + ret + +cprocend + + cpublic _EVT_codeEnd + +endcodeseg _event + +endif + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm new file mode 100644 index 000000000..068eea65d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_lztimer.asm @@ -0,0 +1,58 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: NASM or TASM Assembler +;* Environment: smx 32 bit intel CPU +;* +;* Description: SMX does not support 486's, so this module is not necessary. +;* +;* All registers and all flags are preserved by all routines, except +;* interrupts which are always turned on +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" + +header _lztimer + +begdataseg _lztimer + +enddataseg _lztimer + +begcodeseg _lztimer ; Start of code segment + +cprocstart LZ_disable + cli + ret +cprocend + +cprocstart LZ_enable + sti + ret +cprocend + +endcodeseg _lztimer + + END diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm new file mode 100644 index 000000000..1c7cb2186 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_pm.asm @@ -0,0 +1,448 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 32-bit SMX embedded systems development +;* +;* Description: Low level assembly support for the PM library specific to +;* SMX. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pm ; Set up memory model + +begdataseg _pm + + cextern _PM_savedDS,USHORT + +intel_id db "GenuineIntel" ; Intel vendor ID + +enddataseg _pm + +begcodeseg _pm ; Start of code segment + +;---------------------------------------------------------------------------- +; void PM_segread(PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Read the current value of all segment registers +;---------------------------------------------------------------------------- +cprocstartdll16 PM_segread + + ARG sregs:DPTR + + enter_c + + mov ax,es + _les _si,[sregs] + mov [_ES _si],ax + mov [_ES _si+2],cs + mov [_ES _si+4],ss + mov [_ES _si+6],ds + mov [_ES _si+8],fs + mov [_ES _si+10],gs + + leave_c + ret + +cprocend + +; Create a table of the 256 different interrupt calls that we can jump +; into + +ifdef USE_NASM + +%assign intno 0 + +intTable: +%rep 256 + db 0CDh + db intno +%assign intno intno + 1 + ret + nop +%endrep + +else + +intno = 0 + +intTable: + REPT 256 + db 0CDh + db intno +intno = intno + 1 + ret + nop + ENDM + +endif + +;---------------------------------------------------------------------------- +; _PM_genInt - Generate the appropriate interrupt +;---------------------------------------------------------------------------- +cprocnear _PM_genInt + + push _ax ; Save _ax + push _bx ; Save _bx + mov ebx,[UINT esp+12] ; EBX := interrupt number + mov _ax,offset intTable ; Point to interrupt generation table + shl _bx,2 ; _BX := index into table + add _ax,_bx ; _AX := pointer to interrupt code + xchg eax,[esp+4] ; Restore eax, and set for int + pop _bx ; restore _bx + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Issues a software interrupt in protected mode. This routine has been +; written to allow user programs to load CS and DS with different values +; other than the default. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_int386x + + ARG intno:UINT, inptr:DPTR, outptr:DPTR, sregs:DPTR + + LOCAL flags:UINT, sv_ds:UINT, sv_esi:ULONG = LocalSize + + enter_c + push ds + push es ; Save segment registers + push fs + push gs + + _lds _si,[sregs] ; DS:_SI -> Load segment registers + mov es,[_si] + mov bx,[_si+6] + mov [sv_ds],_bx ; Save value of user DS on stack + mov fs,[_si+8] + mov gs,[_si+10] + + _lds _si,[inptr] ; Load CPU registers + mov eax,[_si] + mov ebx,[_si+4] + mov ecx,[_si+8] + mov edx,[_si+12] + mov edi,[_si+20] + mov esi,[_si+16] + + push ds ; Save value of DS + push _bp ; Some interrupts trash this! + clc ; Generate the interrupt + push [UINT intno] + mov ds,[WORD sv_ds] ; Set value of user's DS selector + call _PM_genInt + pop _bp ; Pop intno from stack (flags unchanged) + pop _bp ; Restore value of stack frame pointer + pop ds ; Restore value of DS + + pushf ; Save flags for later + pop [UINT flags] + push esi ; Save ESI for later + pop [DWORD sv_esi] + push ds ; Save DS for later + pop [UINT sv_ds] + + _lds _si,[outptr] ; Save CPU registers + mov [_si],eax + mov [_si+4],ebx + mov [_si+8],ecx + mov [_si+12],edx + push [DWORD sv_esi] + pop [DWORD _si+16] + mov [_si+20],edi + + mov _bx,[flags] ; Return flags + and ebx,1h ; Isolate carry flag + mov [_si+24],ebx ; Save carry flag status + + _lds _si,[sregs] ; Save segment registers + mov [_si],es + mov _bx,[sv_ds] + mov [_si+6],bx ; Get returned DS from stack + mov [_si+8],fs + mov [_si+10],gs + + pop gs ; Restore segment registers + pop fs + pop es + pop ds + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_saveDS(void) +;---------------------------------------------------------------------------- +; Save the value of DS into a section of the code segment, so that we can +; quickly load this value at a later date in the PM_loadDS() routine from +; inside interrupt handlers etc. The method to do this is different +; depending on the DOS extender being used. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_saveDS + + mov [_PM_savedDS],ds ; Store away in data segment + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_loadDS(void) +;---------------------------------------------------------------------------- +; Routine to load the DS register with the default value for the current +; DOS extender. Only the DS register is loaded, not the ES register, so +; if you wish to call C code, you will need to also load the ES register +; in 32 bit protected mode. +;---------------------------------------------------------------------------- +cprocstartdll16 PM_loadDS + + mov ds,[cs:_PM_savedDS] ; We can access the proper DS through CS + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankA(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankA + + ARG bank:UINT + + push ebp + mov ebp,esp + push ebx + mov _bx,0 + mov _ax,4F05h + mov _dx,[bank] + int 10h + pop ebx + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankAB(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankAB + + ARG bank:UINT + + push ebp + mov ebp,esp + push ebx + mov _bx,0 + mov _ax,4F05h + mov _dx,[bank] + int 10h + mov _bx,1 + mov _ax,4F05h + mov _dx,[bank] + int 10h + pop ebx + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setCRTStart(int x,int y,int waitVRT) +;---------------------------------------------------------------------------- +cprocstart PM_setCRTStart + + ARG x:UINT, y:UINT, waitVRT:UINT + + push ebp + mov ebp,esp + push ebx + mov _bx,[waitVRT] + mov _cx,[x] + mov _dx,[y] + mov _ax,4F07h + int 10h + pop ebx + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; int _PM_inp(int port) +;---------------------------------------------------------------------------- +; Reads a byte from the specified port +;---------------------------------------------------------------------------- +cprocstart _PM_inp + + ARG port:UINT + + push _bp + mov _bp,_sp + xor _ax,_ax + mov _dx,[port] + in al,dx + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_outp(int port,int value) +;---------------------------------------------------------------------------- +; Write a byte to the specified port. +;---------------------------------------------------------------------------- +cprocstart _PM_outp + + ARG port:UINT, value:UINT + + push _bp + mov _bp,_sp + mov _dx,[port] + mov _ax,[value] + out dx,al + pop _bp + ret + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; uchar _PM_readCMOS(int index) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_readCMOS + + ARG index:UINT + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + in al,71h + mov ah,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + sti + mov al,ah ; Return value in AL + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_writeCMOS(int index,uchar value) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_writeCMOS + + ARG index:UINT, value:UCHAR + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + mov al,[value] + out 71h,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + sti + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; _PM_getPDB - Return the Page Table Directory Base address +;---------------------------------------------------------------------------- +cprocstart _PM_getPDB + + mov eax,cr3 + and eax,0FFFFF000h + ret + +cprocend + +;---------------------------------------------------------------------------- +; _PM_flushTLB - Flush the Translation Lookaside buffer +;---------------------------------------------------------------------------- +cprocstart PM_flushTLB + + wbinvd ; Flush the CPU cache + mov eax,cr3 + mov cr3,eax ; Flush the TLB + ret + +cprocend + +endcodeseg _pm + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm new file mode 100644 index 000000000..8352ce30c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_pmsmx.asm @@ -0,0 +1,933 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 32-bit SMX embedded systems development +;* +;* Description: Low level assembly support for the PM library specific to +;* SMX interrupt handling. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pmsmx ; Set up memory model + +; Define the size of our local stacks. For real mode code they cant be +; that big, but for 32 bit protected mode code we can make them nice and +; large so that complex C functions can be used. + +MOUSE_STACK EQU 4096 +TIMER_STACK EQU 4096 +KEY_STACK EQU 1024 +INT10_STACK EQU 1024 + +ifdef USE_NASM + +; Macro to load DS and ES registers with correct value. + +%imacro LOAD_DS 0 + mov ds,[cs:_PM_savedDS] + mov es,[cs:_PM_savedDS] +%endmacro + +; Note that interrupts we disable interrupts during the following stack +; %imacro for correct operation, but we do not enable them again. Normally +; these %imacros are used within interrupt handlers so interrupts should +; already be off. We turn them back on explicitly later if the user code +; needs them to be back on. + +; Macro to switch to a new local stack. + +%imacro NEWSTK 1 + cli + mov [seg_%1],ss + mov [ptr_%1],_sp + mov [TempSeg],ds + mov ss,[TempSeg] + mov _sp,offset %1 +%endmacro + +; %imacro to switch back to the old stack. + +%imacro RESTSTK 1 + cli + mov ss,[seg_%1] + mov _sp,[ptr_%1] +%endmacro + +; %imacro to swap the current stack with the one saved away. + +%imacro SWAPSTK 1 + cli + mov ax,ss + xchg ax,[seg_%1] + mov ss,ax + xchg _sp,[ptr_%1] +%endmacro + +else + +; Macro to load DS and ES registers with correct value. + +MACRO LOAD_DS + mov ds,[cs:_PM_savedDS] + mov es,[cs:_PM_savedDS] +ENDM + +; Note that interrupts we disable interrupts during the following stack +; macro for correct operation, but we do not enable them again. Normally +; these macros are used within interrupt handlers so interrupts should +; already be off. We turn them back on explicitly later if the user code +; needs them to be back on. + +; Macro to switch to a new local stack. + +MACRO NEWSTK stkname + cli + mov [seg_&stkname&],ss + mov [ptr_&stkname&],_sp + mov [TempSeg],ds + mov ss,[TempSeg] + mov _sp,offset stkname +ENDM + +; Macro to switch back to the old stack. + +MACRO RESTSTK stkname + cli + mov ss,[seg_&stkname&] + mov _sp,[ptr_&stkname&] +ENDM + +; Macro to swap the current stack with the one saved away. + +MACRO SWAPSTK stkname + cli + mov ax,ss + xchg ax,[seg_&stkname&] + mov ss,ax + xchg _sp,[ptr_&stkname&] +ENDM + +endif + +begdataseg _pmsmx + + cextern _PM_savedDS,USHORT + cextern _PM_critHandler,CPTR + cextern _PM_breakHandler,CPTR + cextern _PM_timerHandler,CPTR + cextern _PM_rtcHandler,CPTR + cextern _PM_keyHandler,CPTR + cextern _PM_key15Handler,CPTR + cextern _PM_mouseHandler,CPTR + cextern _PM_int10Handler,CPTR + + cextern _PM_ctrlCPtr,DPTR + cextern _PM_ctrlBPtr,DPTR + cextern _PM_critPtr,DPTR + + cextern _PM_prevTimer,FCPTR + cextern _PM_prevRTC,FCPTR + cextern _PM_prevKey,FCPTR + cextern _PM_prevKey15,FCPTR + cextern _PM_prevBreak,FCPTR + cextern _PM_prevCtrlC,FCPTR + cextern _PM_prevCritical,FCPTR + cextern _PM_prevRealTimer,ULONG + cextern _PM_prevRealRTC,ULONG + cextern _PM_prevRealKey,ULONG + cextern _PM_prevRealKey15,ULONG + cextern _PM_prevRealInt10,ULONG + +cpublic _PM_pmsmxDataStart + +; Allocate space for all of the local stacks that we need. These stacks +; are not very large, but should be large enough for most purposes +; (generally you want to handle these interrupts quickly, simply storing +; the information for later and then returning). If you need bigger +; stacks then change the appropriate value in here. + + ALIGN 4 + dclb MOUSE_STACK ; Space for local stack (small) +MsStack: ; Stack starts at end! +ptr_MsStack DUINT 0 ; Place to store old stack offset +seg_MsStack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb INT10_STACK ; Space for local stack (small) +Int10Stack: ; Stack starts at end! +ptr_Int10Stack DUINT 0 ; Place to store old stack offset +seg_Int10Stack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb TIMER_STACK ; Space for local stack (small) +TmStack: ; Stack starts at end! +ptr_TmStack DUINT 0 ; Place to store old stack offset +seg_TmStack dw 0 ; Place to store old stack segment + + ALIGN 4 + dclb TIMER_STACK ; Space for local stack (small) +RtcStack: ; Stack starts at end! +ptr_RtcStack DUINT 0 ; Place to store old stack offset +seg_RtcStack dw 0 ; Place to store old stack segment +RtcInside dw 0 ; Are we still handling current interrupt + + ALIGN 4 + dclb KEY_STACK ; Space for local stack (small) +KyStack: ; Stack starts at end! +ptr_KyStack DUINT 0 ; Place to store old stack offset +seg_KyStack dw 0 ; Place to store old stack segment +KyInside dw 0 ; Are we still handling current interrupt + + ALIGN 4 + dclb KEY_STACK ; Space for local stack (small) +Ky15Stack: ; Stack starts at end! +ptr_Ky15Stack DUINT 0 ; Place to store old stack offset +seg_Ky15Stack dw 0 ; Place to store old stack segment + +TempSeg dw 0 ; Place to store stack segment + +cpublic _PM_pmsmxDataEnd + +enddataseg _pmsmx + +begcodeseg _pmsmx ; Start of code segment + +cpublic _PM_pmsmxCodeStart + +;---------------------------------------------------------------------------- +; PM_mouseISR - Mouse interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Interrupt subroutine called by the mouse driver upon interrupts, to +; dispatch control to high level C based subroutines. Interrupts are on +; when we call the user code. +; +; It is _extremely_ important to save the state of the extended registers +; as these may well be trashed by the routines called from here and not +; restored correctly by the mouse interface module. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. For mouse handlers this is not a +; problem, as the mouse driver arbitrates calls to the user mouse +; handler for us. +; +; Entry: AX - Condition mask giving reason for call +; BX - Mouse button state +; CX - Horizontal cursor coordinate +; DX - Vertical cursor coordinate +; SI - Horizontal mickey value +; DI - Vertical mickey value +; +;---------------------------------------------------------------------------- +cprocfar _PM_mouseISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + NEWSTK MsStack ; Switch to local stack + +; Call the installed high level C code routine + + clrhi dx ; Clear out high order values + clrhi cx + clrhi bx + clrhi ax + sgnhi si + sgnhi di + + push _di + push _si + push _dx + push _cx + push _bx + push _ax + sti ; Enable interrupts + call [CPTR _PM_mouseHandler] + _add sp,12,24 + + RESTSTK MsStack ; Restore previous stack + + popad ; Restore all extended registers + pop es + pop ds + ret ; We are done!! + +cprocend + +;---------------------------------------------------------------------------- +; PM_timerISR - Timer interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the timer interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible, since a timer overrun will simply hang the +; system. +;---------------------------------------------------------------------------- +cprocfar _PM_timerISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + + NEWSTK TmStack ; Switch to local stack + call [CPTR _PM_timerHandler] + RESTSTK TmStack ; Restore previous stack + + popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; PM_chainPrevTimer - Chain to previous timer interrupt and return +;---------------------------------------------------------------------------- +; Chains to the previous timer interrupt routine and returns control +; back to the high level interrupt handler. +;---------------------------------------------------------------------------- +cprocstart PM_chainPrevTimer + +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealTimer] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax + ret +else + SWAPSTK TmStack ; Swap back to previous stack + pushf ; Save state of interrupt flag + pushf ; Push flags on stack to simulate interrupt +ifdef USE_NASM + call far dword [_PM_prevTimer] +else + call [_PM_prevTimer] +endif + popf ; Restore state of interrupt flag + SWAPSTK TmStack ; Swap back to C stack again + ret +endif + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; PM_rtcISR - Real time clock interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the timer interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. Make sure your C code executes as +; quickly as possible, since a timer overrun will simply hang the +; system. +;---------------------------------------------------------------------------- +cprocfar _PM_rtcISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + +; Clear priority interrupt controller and re-enable interrupts so we +; dont lock things up for long. + + mov al,20h + out 0A0h,al + out 020h,al + +; Clear real-time clock timeout + + in al,70h ; Read CMOS index register + push _ax ; and save for later + IODELAYN 3 + mov al,0Ch + out 70h,al + IODELAYN 5 + in al,71h + +; Call the C interrupt handler function + + LOAD_DS ; Load DS register + cmp [BYTE RtcInside],1 ; Check for mutual exclusion + je @@Exit + mov [BYTE RtcInside],1 + sti ; Re-enable interrupts + NEWSTK RtcStack ; Switch to local stack + call [CPTR _PM_rtcHandler] + RESTSTK RtcStack ; Restore previous stack + mov [BYTE RtcInside],0 + +@@Exit: pop _ax + out 70h,al ; Restore CMOS index register + popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; PM_keyISR - keyboard interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the keyboard interrupt, to dispatch control +; to high level C based subroutines. We save the state of all registers +; in this routine, and switch to a local stack. Interrupts are *off* +; when we call the user code. +; +; NOTE: This routine switches to a local stack before calling any C code, +; and hence is _not_ re-entrant. However we ensure within this routine +; mutual exclusion to the keyboard handling routine. +;---------------------------------------------------------------------------- +cprocfar _PM_keyISR + + push ds ; Save value of DS + push es + pushad ; Save _all_ extended registers + cld ; Clear direction flag + + LOAD_DS ; Load DS register + + cmp [BYTE KyInside],1 ; Check for mutual exclusion + je @@Reissued + + mov [BYTE KyInside],1 + NEWSTK KyStack ; Switch to local stack + call [CPTR _PM_keyHandler] ; Call C code + RESTSTK KyStack ; Restore previous stack + mov [BYTE KyInside],0 + +@@Exit: popad ; Restore all extended registers + pop es + pop ds + iret ; Return from interrupt + +; When the BIOS keyboard handler needs to change the SHIFT status lights +; on the keyboard, in the process of doing this the keyboard controller +; re-issues another interrupt, while the current handler is still executing. +; If we recieve another interrupt while still handling the current one, +; then simply chain directly to the previous handler. +; +; Note that for most DOS extenders, the real mode interrupt handler that we +; install takes care of this for us. + +@@Reissued: +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax +else + pushf +ifdef USE_NASM + call far dword [_PM_prevKey] +else + call [_PM_prevKey] +endif +endif + jmp @@Exit + +cprocend + +;---------------------------------------------------------------------------- +; PM_chainPrevkey - Chain to previous key interrupt and return +;---------------------------------------------------------------------------- +; Chains to the previous key interrupt routine and returns control +; back to the high level interrupt handler. +;---------------------------------------------------------------------------- +cprocstart PM_chainPrevKey + +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax + ret +else + +; YIKES! For some strange reason, when execution returns from the +; previous keyboard handler, interrupts are re-enabled!! Since we expect +; interrupts to remain off during the duration of our handler, this can +; cause havoc. However our stack macros always turn off interrupts, so they +; will be off when we exit this routine. Obviously there is a tiny weeny +; window when interrupts will be enabled, but there is nothing we can +; do about this. + + SWAPSTK KyStack ; Swap back to previous stack + pushf ; Push flags on stack to simulate interrupt +ifdef USE_NASM + call far dword [_PM_prevKey] +else + call [_PM_prevKey] +endif + SWAPSTK KyStack ; Swap back to C stack again + ret +endif + +cprocend + +;---------------------------------------------------------------------------- +; PM_key15ISR - Int 15h keyboard interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; This routine gets called if we have been called to handle the Int 15h +; keyboard interrupt callout from real mode. +; +; Entry: AX - Hardware scan code to process +; Exit: AX - Hardware scan code to process (0 to ignore) +;---------------------------------------------------------------------------- +cprocfar _PM_key15ISR + + push ds + push es + LOAD_DS + cmp ah,4Fh + jnz @@NotOurs ; Quit if not keyboard callout + + pushad + cld ; Clear direction flag + xor ah,ah ; AX := scan code + NEWSTK Ky15Stack ; Switch to local stack + push _ax + call [CPTR _PM_key15Handler] ; Call C code + _add sp,2,4 + RESTSTK Ky15Stack ; Restore previous stack + test ax,ax + jz @@1 + stc ; Set carry to process as normal + jmp @@2 +@@1: clc ; Clear carry to ignore scan code +@@2: popad + jmp @@Exit ; We are done + +@@NotOurs: +ifdef TNT + push eax + push ebx + push ecx + pushfd ; Push flags on stack to simulate interrupt + mov ax,250Eh ; Call real mode procedure function + mov ebx,[_PM_prevRealKey15] + mov ecx,1 ; Copy real mode flags to real mode stack + int 21h ; Call the real mode code + popfd + pop ecx + pop ebx + pop eax +else + pushf +ifdef USE_NASM + call far dword [_PM_prevKey15] +else + call [_PM_prevKey15] +endif +endif +@@Exit: pop es + pop ds + retf 4 + +cprocend + +;---------------------------------------------------------------------------- +; PM_breakISR - Control Break interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the Ctrl-Break interrupt. We simply set +; the Ctrl-Break flag to a 1 and leave (note that this is accessed through +; a far pointer, as it may well be located in conventional memory). +;---------------------------------------------------------------------------- +cprocfar _PM_breakISR + + sti + push ds ; Save value of DS + push es + push _bx + + LOAD_DS ; Load DS register + mov ebx,[_PM_ctrlBPtr] + mov [UINT _ES _bx],1 + +; Run alternate break handler code if installed + + cmp [CPTR _PM_breakHandler],0 + je @@Exit + + pushad + mov _ax,1 + push _ax + call [CPTR _PM_breakHandler] ; Call C code + pop _ax + popad + +@@Exit: pop _bx + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; int PM_ctrlBreakHit(int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the Ctrl-Break flag and possibly clears it. +;---------------------------------------------------------------------------- +cprocstart PM_ctrlBreakHit + + ARG clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es + mov ebx,[_PM_ctrlBPtr] + cli ; No interrupts thanks! + mov _ax,[_ES _bx] + test [BYTE clearFlag],1 + jz @@Done + mov [UINT _ES _bx],0 + +@@Done: pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; PM_ctrlCISR - Control Break interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Hardware interrupt handler for the Ctrl-C interrupt. We simply set +; the Ctrl-C flag to a 1 and leave (note that this is accessed through +; a far pointer, as it may well be located in conventional memory). +;---------------------------------------------------------------------------- +cprocfar _PM_ctrlCISR + + sti + push ds ; Save value of DS + push es + push _bx + + LOAD_DS ; Load DS register + mov ebx,[_PM_ctrlCPtr] + mov [UINT _ES _bx],1 + +; Run alternate break handler code if installed + + cmp [CPTR _PM_breakHandler],0 + je @@Exit + + pushad + mov _ax,0 + push _ax + call [CPTR _PM_breakHandler] ; Call C code + pop _ax + popad + +@@Exit: pop _bx + pop es + pop ds + iret ; Return from interrupt + iretd + +cprocend + +;---------------------------------------------------------------------------- +; int PM_ctrlCHit(int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the Ctrl-C flag and possibly clears it. +;---------------------------------------------------------------------------- +cprocstart PM_ctrlCHit + + ARG clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es + mov ebx,[_PM_ctrlCPtr] + cli ; No interrupts thanks! + mov _ax,[_ES _bx] + test [BYTE clearFlag],1 + jz @@Done + mov [UINT _ES _bx],0 + +@@Done: + pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; PM_criticalISR - Control Error handler interrupt subroutine dispatcher +;---------------------------------------------------------------------------- +; Interrupt handler for the MSDOS Critical Error interrupt, to dispatch +; control to high level C based subroutines. We save the state of all +; registers in this routine, and switch to a local stack. We also pass +; the values of the AX and DI registers to the as pointers, so that the +; values can be modified before returning to MSDOS. +;---------------------------------------------------------------------------- +cprocfar _PM_criticalISR + + sti + push ds ; Save value of DS + push es + push _bx ; Save register values changed + cld ; Clear direction flag + + LOAD_DS ; Load DS register + mov ebx,[_PM_critPtr] + mov [_ES _bx],ax + mov [_ES _bx+2],di + +; Run alternate critical handler code if installed + + cmp [CPTR _PM_critHandler],0 + je @@NoAltHandler + + pushad + push _di + push _ax + call [CPTR _PM_critHandler] ; Call C code + _add sp,4,8 + popad + + pop _bx + pop es + pop ds + iret ; Return from interrupt + +@@NoAltHandler: + mov ax,3 ; Tell MSDOS to fail the operation + pop _bx + pop es + pop ds + iret ; Return from interrupt + +cprocend + +;---------------------------------------------------------------------------- +; int PM_criticalError(int *axVal,int *diVal,int clearFlag) +;---------------------------------------------------------------------------- +; Returns the current state of the critical error flags, and the values that +; MSDOS passed in the AX and DI registers to our handler. +;---------------------------------------------------------------------------- +cprocstart PM_criticalError + + ARG axVal:DPTR, diVal:DPTR, clearFlag:UINT + + enter_c + pushf ; Save interrupt status + push es + mov ebx,[_PM_critPtr] + cli ; No interrupts thanks! + xor _ax,_ax + xor _di,_di + mov ax,[_ES _bx] + mov di,[_ES _bx+2] + test [BYTE clearFlag],1 + jz @@NoClear + mov [ULONG _ES _bx],0 +@@NoClear: + _les _bx,[axVal] + mov [_ES _bx],_ax + _les _bx,[diVal] + mov [_ES _bx],_di + pop es + popf ; Restore interrupt status + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setMouseHandler(int mask, PM_mouseHandler mh) +;---------------------------------------------------------------------------- +cprocstart _PM_setMouseHandler + + ARG mouseMask:UINT + + enter_c + push es + + mov ax,0Ch ; AX := Function 12 - install interrupt sub + mov _cx,[mouseMask] ; CX := mouse mask + mov _dx,offset _PM_mouseISR + push cs + pop es ; ES:_DX -> mouse handler + int 33h ; Call mouse driver + + pop es + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_mousePMCB(void) +;---------------------------------------------------------------------------- +; Mouse realmode callback routine. Upon entry to this routine, we recieve +; the following from the DPMI server: +; +; Entry: DS:_SI -> Real mode stack at time of call +; ES:_DI -> Real mode register data structure +; SS:_SP -> Locked protected mode stack to use +;---------------------------------------------------------------------------- +cprocfar _PM_mousePMCB + + pushad + mov eax,[es:_di+1Ch] ; Load register values from real mode + mov ebx,[es:_di+10h] + mov ecx,[es:_di+18h] + mov edx,[es:_di+14h] + mov esi,[es:_di+04h] + mov edi,[es:_di] + call _PM_mouseISR ; Call the mouse handler + popad + + mov ax,[ds:_si] + mov [es:_di+2Ah],ax ; Plug in return IP address + mov ax,[ds:_si+2] + mov [es:_di+2Ch],ax ; Plug in return CS value + add [WORD es:_di+2Eh],4 ; Remove return address from stack + iret ; Go back to real mode! + +cprocend + +;---------------------------------------------------------------------------- +; void PM_int10PMCB(void) +;---------------------------------------------------------------------------- +; int10 realmode callback routine. Upon entry to this routine, we recieve +; the following from the DPMI server: +; +; Entry: DS:ESI -> Real mode stack at time of call +; ES:EDI -> Real mode register data structure +; SS:ESP -> Locked protected mode stack to use +;---------------------------------------------------------------------------- +cprocfar _PM_int10PMCB + + pushad + push ds + push es + push fs + + pushfd + pop eax + mov [es:edi+20h],ax ; Save return flag status + mov ax,[ds:esi] + mov [es:edi+2Ah],ax ; Plug in return IP address + mov ax,[ds:esi+2] + mov [es:edi+2Ch],ax ; Plug in return CS value + add [WORD es:edi+2Eh],4 ; Remove return address from stack + +; Call the install int10 handler in protected mode. This function gets called +; with DS set to the current data selector, and ES:EDI pointing the the +; real mode DPMI register structure at the time of the interrupt. The +; handle must be written in assembler to be able to extract the real mode +; register values from the structure + + push es + pop fs ; FS:EDI -> real mode registers + LOAD_DS + NEWSTK Int10Stack ; Switch to local stack + + call [_PM_int10Handler] + + RESTSTK Int10Stack ; Restore previous stack + pop fs + pop es + pop ds + popad + iret ; Go back to real mode! + +cprocend + +cpublic _PM_pmsmxCodeEnd + +endcodeseg _pmsmx + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm b/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm new file mode 100644 index 000000000..34985a9d8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/_vflat.asm @@ -0,0 +1,652 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Based on original code Copyright 1994 Otto Chrons +;* +;* Language: 80386 Assembler, TASM 4.0 or later +;* Environment: IBM PC 32 bit protected mode +;* +;* Description: Low level page fault handler for virtual linear framebuffers. +;* +;**************************************************************************** + + IDEAL + JUMPS + +include "scitech.mac" ; Memory model macros + +header _vflat ; Set up memory model + +VFLAT_START EQU 0F0000000h +VFLAT_END EQU 0F03FFFFFh +PAGE_PRESENT EQU 1 +PAGE_NOTPRESENT EQU 0 +PAGE_READ EQU 0 +PAGE_WRITE EQU 2 + +ifdef DOS4GW + +;---------------------------------------------------------------------------- +; DOS4G/W flat linear framebuffer emulation. +;---------------------------------------------------------------------------- + +begdataseg _vflat + +; Near pointers to the page directory base and our page tables. All of +; this memory is always located in the first Mb of DOS memory. + +PDBR dd 0 ; Page directory base register (CR3) +accessPageAddr dd 0 +accessPageTable dd 0 + +; CauseWay page directory & 1st page table linear addresses. + +CauseWayDIRLinear dd 0 +CauseWay1stLinear dd 0 + +; Place to store a copy of the original Page Table Directory before we +; intialised our virtual buffer code. + +pageDirectory: resd 1024 ; Saved page table directory + +ValidCS dw 0 ; Valid CS for page faults +Ring0CS dw 0 ; Our ring 0 code selector +LastPage dd 0 ; Last page we mapped in +BankFuncBuf: resb 101 ; Place to store bank switch code +BankFuncPtr dd offset BankFuncBuf + +INT14Gate: +INT14Offset dd 0 ; eip of original vector +INT14Selector dw 0 ; cs of original vector + + cextern _PM_savedDS,USHORT + cextern VF_haveCauseWay,BOOL + +enddataseg _vflat + +begcodeseg _vflat ; Start of code segment + + cextern VF_malloc,FPTR + +;---------------------------------------------------------------------------- +; PF_handler64k - Page fault handler for 64k banks +;---------------------------------------------------------------------------- +; The handler below is a 32 bit ring 0 page fault handler. It receives +; control immediately after any page fault or after an IRQ6 (hardware +; interrupt). This provides the fastest possible handling of page faults +; since it jump directly here. If this is a page fault, the number +; immediately on the stack will be an error code, at offset 4 will be +; the eip of the faulting instruction, at offset 8 will be the cs of the +; faulting instruction. If it is a hardware interrupt, it will not have +; the error code and the eflags will be at offset 8. +;---------------------------------------------------------------------------- +cprocfar PF_handler64k + +; Check if this is a processor exeception or a page fault + + push eax + mov ax,[cs:ValidCS] ; Use CS override to access data + cmp [ss:esp+12],ax ; Is this a page fault? + jne @@ToOldHandler ; Nope, jump to the previous handler + +; Get address of page fault and check if within our handlers range + + mov eax,cr2 ; EBX has page fault linear address + cmp eax,VFLAT_START ; Is the fault less than ours? + jb @@ToOldHandler ; Yep, go to previous handler + cmp eax,VFLAT_END ; Is the fault more than ours? + jae @@ToOldHandler ; Yep, go to previous handler + +; This is our page fault, so we need to handle it + + pushad + push ds + push es + mov ebx,eax ; EBX := page fault address + and ebx,invert 0FFFFh ; Mask to 64k bank boundary + mov ds,[cs:_PM_savedDS]; Load segment registers + mov es,[cs:_PM_savedDS] + +; Map in the page table for our virtual framebuffer area for modification + + mov edi,[PDBR] ; EDI points to page directory + mov edx,ebx ; EDX = linear address + shr edx,22 ; EDX = offset to page directory + mov edx,[edx*4+edi] ; EDX = physical page table address + mov eax,edx + mov edx,[accessPageTable] + or eax,7 + mov [edx],eax + mov eax,cr3 + mov cr3,eax ; Update page table cache + +; Mark all pages valid for the new page fault area + + mov esi,ebx ; ESI := linear address for page + shr esi,10 + and esi,0FFFh ; Offset into page table + add esi,[accessPageAddr] +ifdef USE_NASM +%assign off 0 +%rep 16 + or [DWORD esi+off],0000000001h ; Enable pages +%assign off off+4 +%endrep +else +off = 0 +REPT 16 + or [DWORD esi+off],0000000001h ; Enable pages +off = off+4 +ENDM +endif + +; Mark all pages invalid for the previously mapped area + + xchg esi,[LastPage] ; Save last page for next page fault + test esi,esi + jz @@DoneMapping ; Dont update if first time round +ifdef USE_NASM +%assign off 0 +%rep 16 + or [DWORD esi+off],0FFFFFFFEh ; Disable pages +%assign off off+4 +%endrep +else +off = 0 +REPT 16 + and [DWORD esi+off],0FFFFFFFEh ; Disable pages +off = off+4 +ENDM +endif + +@@DoneMapping: + mov eax,cr3 + mov cr3,eax ; Flush the TLB + +; Now program the new SuperVGA starting bank address + + mov eax,ebx ; EAX := page fault address + shr eax,16 + and eax,0FFh ; Mask to 0-255 + call [BankFuncPtr] ; Call the bank switch function + + pop es + pop ds + popad + pop eax + add esp,4 ; Pop the error code from stack + iretd ; Return to faulting instruction + +@@ToOldHandler: + pop eax +ifdef USE_NASM + jmp far dword [cs:INT14Gate]; Chain to previous handler +else + jmp [FWORD cs:INT14Gate]; Chain to previous handler +endif + +cprocend + +;---------------------------------------------------------------------------- +; PF_handler4k - Page fault handler for 4k banks +;---------------------------------------------------------------------------- +; The handler below is a 32 bit ring 0 page fault handler. It receives +; control immediately after any page fault or after an IRQ6 (hardware +; interrupt). This provides the fastest possible handling of page faults +; since it jump directly here. If this is a page fault, the number +; immediately on the stack will be an error code, at offset 4 will be +; the eip of the faulting instruction, at offset 8 will be the cs of the +; faulting instruction. If it is a hardware interrupt, it will not have +; the error code and the eflags will be at offset 8. +;---------------------------------------------------------------------------- +cprocfar PF_handler4k + +; Fill in when we have tested all the 64Kb code + +ifdef USE_NASM + jmp far dword [cs:INT14Gate]; Chain to previous handler +else + jmp [FWORD cs:INT14Gate]; Chain to previous handler +endif + +cprocend + +;---------------------------------------------------------------------------- +; void InstallFaultHandler(void *baseAddr,int bankSize) +;---------------------------------------------------------------------------- +; Installes the page fault handler directly int the interrupt descriptor +; table for maximum performance. This of course requires ring 0 access, +; but none of this stuff will run without ring 0! +;---------------------------------------------------------------------------- +cprocstart InstallFaultHandler + + ARG baseAddr:ULONG, bankSize:UINT + + enter_c + + mov [DWORD LastPage],0 ; No pages have been mapped + mov ax,cs + mov [ValidCS],ax ; Save CS value for page faults + +; Put address of our page fault handler into the IDT directly + + sub esp,6 ; Allocate space on stack +ifdef USE_NASM + sidt [ss:esp] ; Store pointer to IDT +else + sidt [FWORD ss:esp] ; Store pointer to IDT +endif + pop ax ; add esp,2 + pop eax ; Absolute address of IDT + add eax,14*8 ; Point to Int #14 + +; Note that Interrupt gates do not have the high and low word of the +; offset in adjacent words in memory, there are 4 bytes separating them. + + mov ecx,[eax] ; Get cs and low 16 bits of offset + mov edx,[eax+6] ; Get high 16 bits of offset in dx + shl edx,16 + mov dx,cx ; edx has offset + mov [INT14Offset],edx ; Save offset + shr ecx,16 + mov [INT14Selector],cx ; Save original cs + mov [eax+2],cs ; Install new cs + mov edx,offset PF_handler64k + cmp [UINT bankSize],4 + jne @@1 + mov edx,offset PF_handler4k +@@1: mov [eax],dx ; Install low word of offset + shr edx,16 + mov [eax+6],dx ; Install high word of offset + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void RemoveFaultHandler(void) +;---------------------------------------------------------------------------- +; Closes down the virtual framebuffer services and restores the previous +; page fault handler. +;---------------------------------------------------------------------------- +cprocstart RemoveFaultHandler + + enter_c + +; Remove page fault handler from IDT + + sub esp,6 ; Allocate space on stack +ifdef USE_NASM + sidt [ss:esp] ; Store pointer to IDT +else + sidt [FWORD ss:esp] ; Store pointer to IDT +endif + + pop ax ; add esp,2 + pop eax ; Absolute address of IDT + add eax,14*8 ; Point to Int #14 + mov cx,[INT14Selector] + mov [eax+2],cx ; Restore original CS + mov edx,[INT14Offset] + mov [eax],dx ; Install low word of offset + shr edx,16 + mov [eax+6],dx ; Install high word of offset + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; void InstallBankFunc(int codeLen,void *bankFunc) +;---------------------------------------------------------------------------- +; Installs the bank switch function by relocating it into our data segment +; and making it into a callable function. We do it this way to make the +; code identical to the way that the VflatD devices work under Windows. +;---------------------------------------------------------------------------- +cprocstart InstallBankFunc + + ARG codeLen:UINT, bankFunc:DPTR + + enter_c + + mov esi,[bankFunc] ; Copy the code into buffer + mov edi,offset BankFuncBuf + mov ecx,[codeLen] + rep movsb + mov [BYTE edi],0C3h ; Terminate the function with a near ret + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int InitPaging(void) +;---------------------------------------------------------------------------- +; Initializes paging system. If paging is not enabled, builds a page table +; directory and page tables for physical memory +; +; Exit: 0 - Successful +; -1 - Couldn't initialize paging mechanism +;---------------------------------------------------------------------------- +cprocstart InitPaging + + push ebx + push ecx + push edx + push esi + push edi + +; Are we running under CauseWay? + + mov ax,0FFF9h + int 31h + jc @@NotCauseway + cmp ecx,"CAUS" + jnz @@NotCauseway + cmp edx,"EWAY" + jnz @@NotCauseway + + mov [BOOL VF_haveCauseWay],1 + mov [CauseWayDIRLinear],esi + mov [CauseWay1stLinear],edi + +; Check for DPMI + + mov ax,0ff00h + push es + int 31h + pop es + shr edi,2 + and edi,3 + cmp edi,2 + jz @@ErrExit ; Not supported under DPMI + + mov eax,[CauseWayDIRLinear] + jmp @@CopyCR3 + +@@NotCauseway: + mov ax,cs + test ax,3 ; Which ring are we running + jnz @@ErrExit ; Needs zero ring to access + ; page tables (CR3) + mov eax,cr0 ; Load CR0 + test eax,80000000h ; Is paging enabled? + jz @@ErrExit ; No, we must have paging! + + mov eax,cr3 ; Load directory address + and eax,0FFFFF000h + +@@CopyCR3: + mov [PDBR],eax ; Save it + mov esi,eax + mov edi,offset pageDirectory + mov ecx,1024 + cld + rep movsd ; Copy the original page table directory + cmp [DWORD accessPageAddr],0; Check if we have allocated page + jne @@HaveRealMem ; table already (we cant free it) + + mov eax,0100h ; DPMI DOS allocate + mov ebx,8192/16 + int 31h ; Allocate 8192 bytes + and eax,0FFFFh + shl eax,4 ; EAX points to newly allocated memory + add eax,4095 + and eax,0FFFFF000h ; Page align + mov [accessPageAddr],eax + +@@HaveRealMem: + mov eax,[accessPageAddr] ; EAX -> page table in 1st Mb + shr eax,12 + and eax,3FFh ; Page table offset + shl eax,2 + cmp [BOOL VF_haveCauseWay],0 + jz @@NotCW0 + mov ebx,[CauseWay1stLinear] + jmp @@Put1st + +@@NotCW0: + mov ebx,[PDBR] + mov ebx,[ebx] + and ebx,0FFFFF000h ; Page table for 1st megabyte + +@@Put1st: + add eax,ebx + mov [accessPageTable],eax + sub eax,eax ; No error + jmp @@Exit + +@@ErrExit: + mov eax,-1 + +@@Exit: pop edi + pop esi + pop edx + pop ecx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void ClosePaging(void) +;---------------------------------------------------------------------------- +; Closes the paging system +;---------------------------------------------------------------------------- +cprocstart ClosePaging + + push eax + push ecx + push edx + push esi + push edi + + mov eax,[accessPageAddr] + call AccessPage ; Restore AccessPage mapping + mov edi,[PDBR] + mov esi,offset pageDirectory + mov ecx,1024 + cld + rep movsd ; Restore the original page table directory + +@@Exit: pop edi + pop esi + pop edx + pop ecx + pop eax + ret + +cprocend + +;---------------------------------------------------------------------------- +; long AccessPage(long phys) +;---------------------------------------------------------------------------- +; Maps a known page to given physical memory +; Entry: EAX - Physical memory +; Exit: EAX - Linear memory address of mapped phys mem +;---------------------------------------------------------------------------- +cprocstatic AccessPage + + push edx + mov edx,[accessPageTable] + or eax,7 + mov [edx],eax + mov eax,cr3 + mov cr3,eax ; Update page table cache + mov eax,[accessPageAddr] + pop edx + ret + +cprocend + +;---------------------------------------------------------------------------- +; long GetPhysicalAddress(long linear) +;---------------------------------------------------------------------------- +; Returns the physical address of linear address +; Entry: EAX - Linear address to convert +; Exit: EAX - Physical address +;---------------------------------------------------------------------------- +cprocstatic GetPhysicalAddress + + push ebx + push edx + mov edx,eax + shr edx,22 ; EDX is the directory offset + mov ebx,[PDBR] + mov edx,[edx*4+ebx] ; Load page table address + push eax + mov eax,edx + call AccessPage ; Access the page table + mov edx,eax + pop eax + shr eax,12 + and eax,03FFh ; EAX offset into page table + mov eax,[edx+eax*4] ; Load physical address + and eax,0FFFFF000h + pop edx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void CreatePageTable(long pageDEntry) +;---------------------------------------------------------------------------- +; Creates a page table for specific address (4MB) +; Entry: EAX - Page directory entry (top 10-bits of address) +;---------------------------------------------------------------------------- +cprocstatic CreatePageTable + + push ebx + push ecx + push edx + push edi + mov ebx,eax ; Save address + mov eax,8192 + push eax + call VF_malloc ; Allocate page table directory + add esp,4 + add eax,0FFFh + and eax,0FFFFF000h ; Page align (4KB) + mov edi,eax ; Save page table linear address + sub eax,eax ; Fill with zero + mov ecx,1024 + cld + rep stosd ; Clear page table + sub edi,4096 + mov eax,edi + call GetPhysicalAddress + mov edx,[PDBR] + or eax,7 ; Present/write/user bit + mov [edx+ebx*4],eax ; Save physical address into page directory + mov eax,cr3 + mov cr3,eax ; Update page table cache + pop edi + pop edx + pop ecx + pop ebx + ret + +cprocend + +;---------------------------------------------------------------------------- +; void MapPhysical2Linear(ulong pAddr, ulong lAddr, int pages, int flags); +;---------------------------------------------------------------------------- +; Maps physical memory into linear memory +; Entry: pAddr - Physical address +; lAddr - Linear address +; pages - Number of 4K pages to map +; flags - Page flags +; bit 0 = present +; bit 1 = Read(0)/Write(1) +;---------------------------------------------------------------------------- +cprocstart MapPhysical2Linear + + ARG pAddr:ULONG, lAddr:ULONG, pages:UINT, pflags:UINT + + enter_c + + and [ULONG pAddr],0FFFFF000h; Page boundary + and [ULONG lAddr],0FFFFF000h; Page boundary + mov ecx,[pflags] + and ecx,11b ; Just two bits + or ecx,100b ; Supervisor bit + mov [pflags],ecx + + mov edx,[lAddr] + shr edx,22 ; EDX = Directory + mov esi,[PDBR] + mov edi,[pages] ; EDI page count + mov ebx,[lAddr] + +@@CreateLoop: + mov ecx,[esi+edx*4] ; Load page table address + test ecx,1 ; Is it present? + jnz @@TableOK + mov eax,edx + call CreatePageTable ; Create a page table +@@TableOK: + mov eax,ebx + shr eax,12 + and eax,3FFh + sub eax,1024 + neg eax ; EAX = page count in this table + inc edx ; Next table + mov ebx,0 ; Next time we'll map 1K pages + sub edi,eax ; Subtract mapped pages from page count + jns @@CreateLoop ; Create more tables if necessary + + mov ecx,[pages] ; ECX = Page count + mov esi,[lAddr] + shr esi,12 ; Offset part isn't needed + mov edi,[pAddr] +@@MappingLoop: + mov eax,esi + shr eax,10 ; EAX = offset to page directory + mov ebx,[PDBR] + mov eax,[eax*4+ebx] ; EAX = page table address + call AccessPage + mov ebx,esi + and ebx,3FFh ; EBX = offset to page table + mov edx,edi + add edi,4096 ; Next physical address + inc esi ; Next linear page + or edx,[pflags] ; Update flags... + mov [eax+ebx*4],edx ; Store page table entry + loop @@MappingLoop + mov eax,cr3 + mov cr3,eax ; Update page table cache + + leave_c + ret + +cprocend + +endcodeseg _vflat + +endif + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c new file mode 100644 index 000000000..5447e574e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/cpuinfo.c @@ -0,0 +1,72 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit SMX embedded systems development. +* +* Description: SMX specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/* External timing function */ + +void __ZTimerInit(void); + +/**************************************************************************** +REMARKS: +Do nothing for DOS because we don't have thread priorities. +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +Do nothing for DOS because we don't have thread priorities. +****************************************************************************/ +#define RestoreThreadPriority(i) (void)(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + ulong resolution; + + __ZTimerInit(); + ULZTimerResolution(&resolution); + freq->low = (ulong)(10000000000.0 / resolution); + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + (t)->low = ULZReadTime() * 10000L; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/event.c b/board/MAI/bios_emulator/scitech/src/pm/smx/event.c new file mode 100644 index 000000000..533c2615b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/event.c @@ -0,0 +1,368 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit SMX embedded systems development +* +* Description: 32-bit SMX implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +#include "smx/ps2mouse.h" + +/*--------------------------- Global variables ----------------------------*/ + +ibool _VARAPI _EVT_useEvents = true; /* True to use event handling */ +ibool _VARAPI _EVT_installed = 0; /* Event handers installed? */ +uchar _VARAPI *_EVT_biosPtr = NULL; /* Pointer to the BIOS data area */ +static ibool haveMouse = false; /* True if we have a mouse */ + +/*---------------------------- Implementation -----------------------------*/ + +/* External assembler functions */ + +void EVTAPI _EVT_pollJoystick(void); +uint EVTAPI _EVT_disableInt(void); +uint EVTAPI _EVT_restoreInt(uint flags); +void EVTAPI _EVT_codeStart(void); +void EVTAPI _EVT_codeEnd(void); +void EVTAPI _EVT_cCodeStart(void); +void EVTAPI _EVT_cCodeEnd(void); +int EVTAPI _EVT_getKeyCode(void); +int EVTAPI EVT_rdinx(int port,int index); +void EVTAPI EVT_wrinx(int port,int index,int value); + +/**************************************************************************** +REMARKS: +Do nothing for DOS, because we are fully interrupt driven. +****************************************************************************/ +#define _EVT_pumpMessages() + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + return (ulong)PM_getLong(_EVT_biosPtr+0x6C) * 55UL; +} + +/**************************************************************************** +REMARKS: +Include generic raw scancode keyboard module. +****************************************************************************/ +#include "common/keyboard.c" + +/**************************************************************************** +REMARKS: +Determines if we have a mouse attached and functioning. +****************************************************************************/ +static ibool detectMouse(void) +{ + return(ps2Query()); +} + +/**************************************************************************** +PARAMETERS: +what - Event code +message - Event message +x,y - Mouse position at time of event +but_stat - Mouse button status at time of event + +REMARKS: +Adds a new mouse event to the event queue. This routine is called from within +the mouse interrupt subroutine, so it must be efficient. + +NOTE: Interrupts MUST be OFF while this routine is called to ensure we have + mutually exclusive access to our internal data structures for + interrupt driven systems (like under DOS). +****************************************************************************/ +static void addMouseEvent( + uint what, + uint message, + int x, + int y, + int mickeyX, + int mickeyY, + uint but_stat) +{ + event_t evt; + + if (EVT.count < EVENTQSIZE) { + /* Save information in event record. */ + evt.when = _EVT_getTicks(); + evt.what = what; + evt.message = message; + evt.modifiers = but_stat; + evt.where_x = x; /* Save mouse event position */ + evt.where_y = y; + evt.relative_x = mickeyX; + evt.relative_y = mickeyY; + evt.modifiers |= EVT.keyModifiers; + addEvent(&evt); /* Add to tail of event queue */ + } +} + +/**************************************************************************** +PARAMETERS: +mask - Event mask +butstate - Button state +x - Mouse x coordinate +y - Mouse y coordinate + +REMARKS: +Mouse event handling routine. This gets called when a mouse event occurs, +and we call the addMouseEvent() routine to add the appropriate mouse event +to the event queue. + +Note: Interrupts are ON when this routine is called by the mouse driver code. +/*AM: NOTE: This function has not actually been ported from DOS yet and should not */ +/*AM: be installed until it is. */ +****************************************************************************/ +static void EVTAPI mouseISR( + uint mask, + uint butstate, + int x, + int y, + int mickeyX, + int mickeyY) +{ + RMREGS regs; + uint ps; + + if (mask & 1) { + /* Save the current mouse coordinates */ + EVT.mx = x; EVT.my = y; + + /* If the last event was a movement event, then modify the last + * event rather than post a new one, so that the queue will not + * become saturated. Before we modify the data structures, we + * MUST ensure that interrupts are off. + */ + ps = _EVT_disableInt(); + if (EVT.oldMove != -1) { + EVT.evtq[EVT.oldMove].where_x = x; /* Modify existing one */ + EVT.evtq[EVT.oldMove].where_y = y; + EVT.evtq[EVT.oldMove].relative_x += mickeyX; + EVT.evtq[EVT.oldMove].relative_y += mickeyY; + } + else { + EVT.oldMove = EVT.freeHead; /* Save id of this move event */ + addMouseEvent(EVT_MOUSEMOVE,0,x,y,mickeyX,mickeyY,butstate); + } + _EVT_restoreInt(ps); + } + if (mask & 0x2A) { + ps = _EVT_disableInt(); + addMouseEvent(EVT_MOUSEDOWN,mask >> 1,x,y,0,0,butstate); + EVT.oldMove = -1; + _EVT_restoreInt(ps); + } + if (mask & 0x54) { + ps = _EVT_disableInt(); + addMouseEvent(EVT_MOUSEUP,mask >> 2,x,y,0,0,butstate); + EVT.oldMove = -1; + _EVT_restoreInt(ps); + } + EVT.oldKey = -1; +} + +/**************************************************************************** +REMARKS: +Keyboard interrupt handler function. + +NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, + and we leave them OFF the entire time. This has been modified to work + in conjunction with smx keyboard handler. +****************************************************************************/ +static void EVTAPI keyboardISR(void) +{ + PM_chainPrevKey(); + processRawScanCode(PM_inpb(0x60)); + PM_outpb(0x20,0x20); +} + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + int i; + + EVT.mouseMove = mouseMove; + _EVT_biosPtr = PM_getBIOSPointer(); + EVT_resume(); +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVTAPI EVT_resume(void) +{ + static int locked = 0; + int stat; + uchar mods; + PM_lockHandle lh; + + if (_EVT_useEvents) { + /* Initialise the event queue and enable our interrupt handlers */ + initEventQueue(); + PM_setKeyHandler(keyboardISR); + if ((haveMouse = detectMouse()) != 0) + PM_setMouseHandler(0xFFFF,mouseISR); + + /* Read the keyboard modifier flags from the BIOS to get the + * correct initialisation state. The only state we care about is + * the correct toggle state flags such as SCROLLLOCK, NUMLOCK and + * CAPSLOCK. + */ + EVT.keyModifiers = 0; + mods = PM_getByte(_EVT_biosPtr+0x17); + if (mods & 0x10) + EVT.keyModifiers |= EVT_SCROLLLOCK; + if (mods & 0x20) + EVT.keyModifiers |= EVT_NUMLOCK; + if (mods & 0x40) + EVT.keyModifiers |= EVT_CAPSLOCK; + + /* Lock all of the code and data used by our protected mode interrupt + * handling routines, so that it will continue to work correctly + * under real mode. + */ + if (!locked) { + /* It is difficult to ensure that we lock our global data, so we + * do this by taking the address of a variable locking all data + * 2Kb on either side. This should properly cover the global data + * used by the module (the other alternative is to declare the + * variables in assembler, in which case we know it will be + * correct). + */ + stat = !PM_lockDataPages(&EVT,sizeof(EVT),&lh); + stat |= !PM_lockDataPages(&_EVT_biosPtr,sizeof(_EVT_biosPtr),&lh); + stat |= !PM_lockCodePages((__codePtr)_EVT_cCodeStart,(int)_EVT_cCodeEnd-(int)_EVT_cCodeStart,&lh); + stat |= !PM_lockCodePages((__codePtr)_EVT_codeStart,(int)_EVT_codeEnd-(int)_EVT_codeStart,&lh); + if (stat) { + PM_fatalError("Page locking services failed - interrupt handling not safe!"); + exit(1); + } + locked = 1; + } + + _EVT_installed = true; + } +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + if (haveMouse) { + ps2MouseStop(); + ps2MouseStart( 0, xRes, 0, yRes, -1, -1, -1); + } +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +void _EVT_setMousePos( + int *x, + int *y) +{ + if (haveMouse) + ps2MouseMove(*x, *y); +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVTAPI EVT_suspend(void) +{ + uchar mods; + + if (_EVT_installed) { + PM_restoreKeyHandler(); + if (haveMouse) + PM_restoreMouseHandler(); + + /* Set the keyboard modifier flags in the BIOS to our values */ + EVT_allowLEDS(true); + mods = PM_getByte(_EVT_biosPtr+0x17) & ~0x70; + if (EVT.keyModifiers & EVT_SCROLLLOCK) + mods |= 0x10; + if (EVT.keyModifiers & EVT_NUMLOCK) + mods |= 0x20; + if (EVT.keyModifiers & EVT_CAPSLOCK) + mods |= 0x40; + PM_setByte(_EVT_biosPtr+0x17,mods); + + /* Flag that we are no longer installed */ + _EVT_installed = false; + } +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVTAPI EVT_exit(void) +{ + EVT_suspend(); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h new file mode 100644 index 000000000..3ff8daa2a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/oshdr.h @@ -0,0 +1,29 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit SMX embedded systems development. +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c b/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c new file mode 100644 index 000000000..99ee3d4be --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/pm.c @@ -0,0 +1,1187 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32 bit SMX embedded systems development. +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "ztimerc.h" +#include "event.h" +#include "mtrr.h" +#include "pm_help.h" +#include +#include +#include +#include +#include +#ifdef __GNUC__ +#include +#include +#include +#else +#include +#endif +#ifdef __BORLANDC__ +#pragma warn -par +#endif + +/*--------------------------- Global variables ----------------------------*/ + +typedef struct { + int oldMode; + int old50Lines; + } DOS_stateBuf; + +#define MAX_RM_BLOCKS 10 + +static struct { + void *p; + uint tag; + } rmBlocks[MAX_RM_BLOCKS]; + +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +static void (PMAPIP fatalErrorCleanup)(void) = NULL; +ushort _VARAPI _PM_savedDS = 0; +static ulong PDB = 0,*pPDB = NULL; +static uint VXD_version = -1; + +/*----------------------------- Implementation ----------------------------*/ + +ulong _ASMAPI _PM_getPDB(void); +void _ASMAPI _PM_VxDCall(VXD_regs *regs,uint off,uint sel); + +/**************************************************************************** +REMARKS: +External function to call the PMHELP helper VxD. +****************************************************************************/ +void PMAPI PM_VxDCall( + VXD_regs *regs) +{ +} + +/**************************************************************************** +RETURNS: +BCD coded version number of the VxD, or 0 if not loaded (ie: 0x202 - 2.2) + +REMARKS: +This function gets the version number for the VxD that we have connected to. +****************************************************************************/ +uint PMAPI PMHELP_getVersion(void) +{ + return VXD_version = 0; +} + +void PMAPI PM_init(void) +{ +#ifndef REALMODE + MTRR_init(); +#endif +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ +#ifndef REALMODE + return MTRR_enableWriteCombine(base,size,type); +#else + return PM_MTRR_NOT_SUPPORTED; +#endif +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return false; } + +long PMAPI PM_getOSType(void) +{ return _OS_SMX; } + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void MGLOutput(char *); + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + MGLOutput(msg); +/* No support for fprintf() under smx currently! */ +/* fprintf(stderr,"%s\n", msg); */ + exit(1); +} + +static void ExitVBEBuf(void) +{ + if (VESABuf_ptr) + PM_freeRealSeg(VESABuf_ptr); + VESABuf_ptr = 0; +} + +void * PMAPI PM_getVESABuf(uint *len,uint *rseg,uint *roff) +{ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + atexit(ExitVBEBuf); + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out) +{ + PMSREGS sregs; + PM_segread(&sregs); + return PM_int386x(intno,in,out,&sregs); +} + +/* Routines to set and get the real mode interrupt vectors, by making + * direct real mode calls to DOS and bypassing the DOS extenders API. + * This is the safest way to handle this, as some servers try to be + * smart about changing real mode vectors. + */ + +void PMAPI _PM_getRMvect(int intno, long *realisr) +{ + RMREGS regs; + RMSREGS sregs; + + PM_saveDS(); + regs.h.ah = 0x35; + regs.h.al = intno; + PM_int86x(0x21, ®s, ®s, &sregs); + *realisr = ((long)sregs.es << 16) | regs.x.bx; +} + +void PMAPI _PM_setRMvect(int intno, long realisr) +{ + RMREGS regs; + RMSREGS sregs; + + PM_saveDS(); + regs.h.ah = 0x25; + regs.h.al = intno; + sregs.ds = (int)(realisr >> 16); + regs.x.dx = (int)(realisr & 0xFFFF); + PM_int86x(0x21, ®s, ®s, &sregs); +} + +void PMAPI _PM_addRealModeBlock(void *mem,uint tag) +{ + int i; + + for (i = 0; i < MAX_RM_BLOCKS; i++) { + if (rmBlocks[i].p == NULL) { + rmBlocks[i].p = mem; + rmBlocks[i].tag = tag; + return; + } + } + PM_fatalError("To many real mode memory block allocations!"); +} + +uint PMAPI _PM_findRealModeBlock(void *mem) +{ + int i; + + for (i = 0; i < MAX_RM_BLOCKS; i++) { + if (rmBlocks[i].p == mem) + return rmBlocks[i].tag; + } + PM_fatalError("Could not find prior real mode memory block allocation!"); + return 0; +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +char PMAPI PM_getBootDrive(void) +{ return 'C'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return "c:\\"; } + +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[256]; + char *env; + + if ((env = getenv("NUCLEUS_PATH")) != NULL) + return env; + return "c:\\nucleus"; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ return "SMX"; } + +const char * PMAPI PM_getMachineName(void) +{ return "SMX"; } + +int PMAPI PM_kbhit(void) +{ + int hit; + event_t evt; + + hit = EVT_peekNext(&evt,EVT_KEYDOWN | EVT_KEYREPEAT); + EVT_flush(~(EVT_KEYDOWN | EVT_KEYREPEAT)); + return hit; +} + +int PMAPI PM_getch(void) +{ + event_t evt; + + EVT_halt(&evt,EVT_KEYDOWN); + return EVT_asciiCode(evt.message); +} + +PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen) +{ + /* Not used for SMX */ + (void)hwndUser; + (void)device; + (void)xRes; + (void)yRes; + (void)bpp; + (void)fullScreen; + return 0; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + return sizeof(DOS_stateBuf); +} + +void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole) +{ + RMREGS regs; + DOS_stateBuf *sb = stateBuf; + + /* Save the old video mode state */ + regs.h.ah = 0x0F; + PM_int86(0x10,®s,®s); + sb->oldMode = regs.h.al & 0x7F; + sb->old50Lines = false; + if (sb->oldMode == 0x3) { + regs.x.ax = 0x1130; + regs.x.bx = 0; + regs.x.dx = 0; + PM_int86(0x10,®s,®s); + sb->old50Lines = (regs.h.dl == 42 || regs.h.dl == 49); + } + (void)hwndConsole; +} + +void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) +{ + /* Not used for SMX */ + (void)saveState; +} + +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) +{ + RMREGS regs; + const DOS_stateBuf *sb = stateBuf; + + /* Retore 50 line mode if set */ + if (sb->old50Lines) { + regs.x.ax = 0x1112; + regs.x.bx = 0; + PM_int86(0x10,®s,®s); + } + (void)hwndConsole; +} + +void PMAPI PM_closeConsole(PM_HWND hwndConsole) +{ + /* Not used for SMX */ + (void)hwndConsole; +} + +void PMAPI PM_setOSCursorLocation(int x,int y) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x50,x); + PM_setByte(_biosPtr+0x51,y); +} + +void PMAPI PM_setOSScreenWidth(int width,int height) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setWord(_biosPtr+0x4A,width); + PM_setWord(_biosPtr+0x4C,width*2); + PM_setByte(_biosPtr+0x84,height-1); + if (height > 25) { + PM_setWord(_biosPtr+0x60,0x0607); + PM_setByte(_biosPtr+0x85,0x08); + } + else { + PM_setWord(_biosPtr+0x60,0x0D0E); + PM_setByte(_biosPtr+0x85,0x016); + } +} + +void * PMAPI PM_mallocShared(long size) +{ + return PM_malloc(size); +} + +void PMAPI PM_freeShared(void *ptr) +{ + PM_free(ptr); +} + +#define GetRMVect(intno,isr) *(isr) = ((ulong*)rmZeroPtr)[intno] +#define SetRMVect(intno,isr) ((ulong*)rmZeroPtr)[intno] = (isr) + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + static int firstTime = true; + static uchar *rmZeroPtr; + long Current10,Current6D,Current42; + RMREGS regs; + RMSREGS sregs; + + /* Create a zero memory mapping for us to use */ + if (firstTime) { + rmZeroPtr = PM_mapPhysicalAddr(0,0x7FFF,true); + firstTime = false; + } + + /* Remap the secondary BIOS to 0xC0000 physical */ + if (BIOSPhysAddr != 0xC0000L || BIOSLen > 32768) { + /* SMX cannot virtually remap the BIOS, so we can only work if all + * the secondary controllers are identical, and we then use the + * BIOS on the first controller for all the remaining controllers. + * + * For OS'es that do virtual memory, and remapping of 0xC0000 + * physical (perhaps a copy on write mapping) should be all that + * is needed. + */ + return false; + } + + /* Save current handlers of int 10h and 6Dh */ + GetRMVect(0x10,&Current10); + GetRMVect(0x6D,&Current6D); + + /* POST the secondary BIOS */ + GetRMVect(0x42,&Current42); + SetRMVect(0x10,Current42); /* Restore int 10h to STD-BIOS */ + regs.x.ax = axVal; + PM_callRealMode(0xC000,0x0003,®s,&sregs); + + /* Restore current handlers */ + SetRMVect(0x10,Current10); + SetRMVect(0x6D,Current6D); + + /* Second the primary BIOS mappin 1:1 for 0xC0000 physical */ + if (BIOSPhysAddr != 0xC0000L) { + /* SMX does not support this */ + (void)mappedBIOS; + } + return true; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + ulong microseconds = milliseconds * 1000L; + LZTimerObject tm; + + LZTimerOnExt(&tm); + while (LZTimerLapExt(&tm) < microseconds) + ; + LZTimerOffExt(&tm); +} + +int PMAPI PM_getCOMPort(int port) +{ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + (void)szDLLName; + return NULL; +} + +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + (void)hModule; + (void)szProcName; + return NULL; +} + +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + (void)hModule; +} + +int PMAPI PM_setIOPL( + int level) +{ + return level; +} + +/**************************************************************************** +REMARKS: +Internal function to convert the find data to the generic interface. +****************************************************************************/ +static void convertFindData( + PM_findData *findData, + struct find_t *blk) +{ + ulong dwSize = findData->dwSize; + + memset(findData,0,findData->dwSize); + findData->dwSize = dwSize; + if (blk->attrib & _A_RDONLY) + findData->attrib |= PM_FILE_READONLY; + if (blk->attrib & _A_SUBDIR) + findData->attrib |= PM_FILE_DIRECTORY; + if (blk->attrib & _A_ARCH) + findData->attrib |= PM_FILE_ARCHIVE; + if (blk->attrib & _A_HIDDEN) + findData->attrib |= PM_FILE_HIDDEN; + if (blk->attrib & _A_SYSTEM) + findData->attrib |= PM_FILE_SYSTEM; + findData->sizeLo = blk->size; + strncpy(findData->name,blk->name,PM_MAX_PATH); + findData->name[PM_MAX_PATH-1] = 0; +} + +#define FIND_MASK (_A_RDONLY | _A_ARCH | _A_SUBDIR | _A_HIDDEN | _A_SYSTEM) + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void * PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + struct find_t *blk; + + if ((blk = PM_malloc(sizeof(*blk))) == NULL) + return PM_FILE_INVALID; + if (_dos_findfirst((char*)filename,FIND_MASK,blk) == 0) { + convertFindData(findData,blk); + return blk; + } + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + struct find_t *blk = handle; + + if (_dos_findnext(blk) == 0) { + convertFindData(findData,blk); + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + PM_free(handle); +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + RMREGS regs; + regs.h.dl = (uchar)(drive - 'A' + 1); + regs.h.ah = 0x36; /* Get disk information service */ + PM_int86(0x21,®s,®s); + return regs.x.ax != 0xFFFF; /* AX = 0xFFFF if disk is invalid */ +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + uint oldDrive,maxDrives; + _dos_getdrive(&oldDrive); + _dos_setdrive(drive,&maxDrives); + getcwd(dir,len); + _dos_setdrive(oldDrive,&maxDrives); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ +#if defined(TNT) && defined(_MSC_VER) + DWORD attr = 0; + + if (attrib & PM_FILE_READONLY) + attr |= FILE_ATTRIBUTE_READONLY; + if (attrib & PM_FILE_ARCHIVE) + attr |= FILE_ATTRIBUTE_ARCHIVE; + if (attrib & PM_FILE_HIDDEN) + attr |= FILE_ATTRIBUTE_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + attr |= FILE_ATTRIBUTE_SYSTEM; + SetFileAttributes((LPSTR)filename, attr); +#else + uint attr = 0; + + if (attrib & PM_FILE_READONLY) + attr |= _A_RDONLY; + if (attrib & PM_FILE_ARCHIVE) + attr |= _A_ARCH; + if (attrib & PM_FILE_HIDDEN) + attr |= _A_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + attr |= _A_SYSTEM; + _dos_setfileattr(filename,attr); +#endif +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ +#ifdef __GNUC__ + return mkdir(filename,S_IRUSR) == 0; +#else +/*AM: return mkdir(filename) == 0; */ + return(false); +#endif +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ +/*AM: return rmdir(filename) == 0; */ + return(false); +} + +/**************************************************************************** +REMARKS: +Allocates a block of locked, physically contiguous memory. The memory +may be required to be below the 16Meg boundary. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + void *p; + uint r_seg,r_off; + PM_lockHandle lh; + + /* Under DOS the only way to know the physical memory address is to + * allocate the memory below the 1Meg boundary as real mode memory. + * We also allocate 4095 bytes more memory than we need, so we can + * properly page align the start of the memory block for DMA operations. + */ + if (size > 4096) + return NULL; + if ((p = PM_allocRealSeg((size + 0xFFF) & ~0xFFF,&r_seg,&r_off)) == NULL) + return NULL; + *physAddr = ((r_seg << 4) + r_off + 0xFFF) & ~0xFFF; + PM_lockDataPages(p,size*2,&lh); + return p; +} + +void PMAPI PM_freeLockedMem(void *p,uint size,ibool contiguous) +{ + (void)size; + PM_freeRealSeg(p); +} + +/*-------------------------------------------------------------------------*/ +/* Generic DPMI routines common to 16/32 bit code */ +/*-------------------------------------------------------------------------*/ + +ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit) +{ + PMREGS r; + ulong physOfs; + + if (physAddr < 0x100000L) { + /* We can't map memory below 1Mb, but the linear address are already + * mapped 1:1 for this memory anyway so we just return the base address. + */ + return physAddr; + } + + /* Round the physical address to a 4Kb boundary and the limit to a + * 4Kb-1 boundary before passing the values to DPMI as some extenders + * will fail the calls unless this is the case. If we round the + * physical address, then we also add an extra offset into the address + * that we return. + */ + physOfs = physAddr & 4095; + physAddr = physAddr & ~4095; + limit = ((limit+physOfs+1+4095) & ~4095)-1; + + r.x.ax = 0x800; /* DPMI map physical to linear */ + r.x.bx = physAddr >> 16; + r.x.cx = physAddr & 0xFFFF; + r.x.si = limit >> 16; + r.x.di = limit & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0xFFFFFFFFUL; + return ((ulong)r.x.bx << 16) + r.x.cx + physOfs; +} + +int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr) +{ + PMREGS r; + + r.x.ax = 7; /* DPMI set selector base address */ + r.x.bx = sel; + r.x.cx = linAddr >> 16; + r.x.dx = linAddr & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0; + return 1; +} + +ulong PMAPI DPMI_getSelectorBase(ushort sel) +{ + PMREGS r; + + r.x.ax = 6; /* DPMI get selector base address */ + r.x.bx = sel; + PM_int386(0x31, &r, &r); + return ((ulong)r.x.cx << 16) + r.x.dx; +} + +int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit) +{ + PMREGS r; + + r.x.ax = 8; /* DPMI set selector limit */ + r.x.bx = sel; + r.x.cx = limit >> 16; + r.x.dx = limit & 0xFFFF; + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return 0; + return 1; +} + +uint PMAPI DPMI_createSelector(ulong base,ulong limit) +{ + uint sel; + PMREGS r; + + /* Allocate 1 descriptor */ + r.x.ax = 0; + r.x.cx = 1; + PM_int386(0x31, &r, &r); + if (r.x.cflag) return 0; + sel = r.x.ax; + + /* Set the descriptor access rights (for a 32 bit page granular + * segment, ring 0). + */ + r.x.ax = 9; + r.x.bx = sel; + r.x.cx = 0x4093; + PM_int386(0x31, &r, &r); + + /* Map physical memory and create selector */ + if ((base = DPMI_mapPhysicalToLinear(base,limit)) == 0xFFFFFFFFUL) + return 0; + if (!DPMI_setSelectorBase(sel,base)) + return 0; + if (!DPMI_setSelectorLimit(sel,limit)) + return 0; + return sel; +} + +void PMAPI DPMI_freeSelector(uint sel) +{ + PMREGS r; + + r.x.ax = 1; + r.x.bx = sel; + PM_int386(0x31, &r, &r); +} + +int PMAPI DPMI_lockLinearPages(ulong linear,ulong len) +{ + PMREGS r; + + r.x.ax = 0x600; /* DPMI Lock Linear Region */ + r.x.bx = (linear >> 16); /* Linear address in BX:CX */ + r.x.cx = (linear & 0xFFFF); + r.x.si = (len >> 16); /* Length in SI:DI */ + r.x.di = (len & 0xFFFF); + PM_int386(0x31, &r, &r); + return (!r.x.cflag); +} + +int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len) +{ + PMREGS r; + + r.x.ax = 0x601; /* DPMI Unlock Linear Region */ + r.x.bx = (linear >> 16); /* Linear address in BX:CX */ + r.x.cx = (linear & 0xFFFF); + r.x.si = (len >> 16); /* Length in SI:DI */ + r.x.di = (len & 0xFFFF); + PM_int386(0x31, &r, &r); + return (!r.x.cflag); +} + +void * PMAPI DPMI_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ + PMSREGS sregs; + ulong linAddr; + ulong DSBaseAddr; + + /* Get the base address for the default DS selector */ + PM_segread(&sregs); + DSBaseAddr = DPMI_getSelectorBase(sregs.ds); + if ((base < 0x100000) && (DSBaseAddr == 0)) { + /* DS is zero based, so we can directly access the first 1Mb of + * system memory (like under DOS4GW). + */ + return (void*)base; + } + + /* Map the memory to a linear address using DPMI function 0x800 */ + if ((linAddr = DPMI_mapPhysicalToLinear(base,limit)) == 0) { + if (base >= 0x100000) + return NULL; + /* If the linear address mapping fails but we are trying to + * map an area in the first 1Mb of system memory, then we must + * be running under a Windows or OS/2 DOS box. Under these + * environments we can use the segment wrap around as a fallback + * measure, as this does work properly. + */ + linAddr = base; + } + + /* Now expand the default DS selector to 4Gb so we can access it */ + if (!DPMI_setSelectorLimit(sregs.ds,0xFFFFFFFFUL)) + return NULL; + + /* Finally enable caching for the page tables that we just mapped in, + * since DOS4GW and PMODE/W create the page table entries without + * caching enabled which hurts the performance of the linear framebuffer + * as it disables write combining on Pentium Pro and above processors. + * + * For those processors cache disabling is better handled through the + * MTRR registers anyway (we can write combine a region but disable + * caching) so that MMIO register regions do not screw up. + */ + if (isCached) { + if ((PDB = _PM_getPDB()) != 0 && DSBaseAddr == 0) { + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong pageTable,*pPageTable; + if (!pPDB) { + if (PDB >= 0x100000) + pPDB = (ulong*)DPMI_mapPhysicalToLinear(PDB,0xFFF); + else + pPDB = (ulong*)PDB; + } + if (pPDB) { + startPDB = (linAddr >> 22) & 0x3FF; + startPage = (linAddr >> 12) & 0x3FF; + endPDB = ((linAddr+limit) >> 22) & 0x3FF; + endPage = ((linAddr+limit) >> 12) & 0x3FF; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + pageTable = pPDB[iPDB] & ~0xFFF; + if (pageTable >= 0x100000) + pPageTable = (ulong*)DPMI_mapPhysicalToLinear(pageTable,0xFFF); + else + pPageTable = (ulong*)pageTable; + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FF; + for (iPage = start; iPage <= end; iPage++) + pPageTable[iPage] &= ~0x18; + } + } + } + } + + /* Now return the base address of the memory into the default DS */ + return (void*)(linAddr - DSBaseAddr); +} + +/* Some DOS extender implementations do not directly support calling a + * real mode procedure from protected mode. However we can simulate what + * we need temporarily hooking the INT 6Ah vector with a small real mode + * stub that will call our real mode code for us. + */ + +static uchar int6AHandler[] = { + 0x00,0x00,0x00,0x00, /* __PMODE_callReal variable */ + 0xFB, /* sti */ + 0x2E,0xFF,0x1E,0x00,0x00, /* call [cs:__PMODE_callReal] */ + 0xCF, /* iretf */ + }; +static uchar *crPtr = NULL; /* Pointer to of int 6A handler */ +static uint crRSeg,crROff; /* Real mode seg:offset of handler */ + +void PMAPI PM_callRealMode(uint seg,uint off, RMREGS *in, + RMSREGS *sregs) +{ + uchar *p; + uint oldSeg,oldOff; + + if (!crPtr) { + /* Allocate and copy the memory block only once */ + crPtr = PM_allocRealSeg(sizeof(int6AHandler), &crRSeg, &crROff); + memcpy(crPtr,int6AHandler,sizeof(int6AHandler)); + } + PM_setWord(crPtr,off); /* Plug in address to call */ + PM_setWord(crPtr+2,seg); + p = PM_mapRealPointer(0,0x6A * 4); + oldOff = PM_getWord(p); /* Save old handler address */ + oldSeg = PM_getWord(p+2); + PM_setWord(p,crROff+4); /* Hook 6A handler */ + PM_setWord(p+2,crRSeg); + PM_int86x(0x6A, in, in, sregs); /* Call real mode code */ + PM_setWord(p,oldOff); /* Restore old handler */ + PM_setWord(p+2,oldSeg); +} + +void * PMAPI PM_getBIOSPointer(void) +{ return PM_mapPhysicalAddr(0x400,0xFFFF,true); } + +void * PMAPI PM_getA0000Pointer(void) +{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); } + +void * PMAPI PM_mapPhysicalAddr(ulong base,ulong limit,ibool isCached) +{ return DPMI_mapPhysicalAddr(base,limit,isCached); } + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + /* Mapping cannot be free */ +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + (void)p; + return 0xFFFFFFFFUL; +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ + (void)limit; + return (void*)base; +} + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ + static uchar *zeroPtr = NULL; + + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); + return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); +} + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ + PMREGS r; + void *p; + + r.x.ax = 0x100; /* DPMI allocate DOS memory */ + r.x.bx = (size + 0xF) >> 4; /* number of paragraphs */ + PM_int386(0x31, &r, &r); + if (r.x.cflag) + return NULL; /* DPMI call failed */ + *r_seg = r.x.ax; /* Real mode segment */ + *r_off = 0; + p = PM_mapRealPointer(*r_seg,*r_off); + _PM_addRealModeBlock(p,r.x.dx); + return p; +} + +void PMAPI PM_freeRealSeg(void *mem) +{ + PMREGS r; + + r.x.ax = 0x101; /* DPMI free DOS memory */ + r.x.dx = _PM_findRealModeBlock(mem);/* DX := selector from 0x100 */ + PM_int386(0x31, &r, &r); +} + +static DPMI_handler_t DPMI_int10 = NULL; + +void PMAPI DPMI_setInt10Handler(DPMI_handler_t handler) +{ + DPMI_int10 = handler; +} + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + PMREGS r; + PMSREGS sr; + + if (intno == 0x10 && DPMI_int10) { + if (DPMI_int10(regs)) + return; + } + PM_segread(&sr); + r.x.ax = 0x300; /* DPMI issue real interrupt */ + r.h.bl = intno; + r.h.bh = 0; + r.x.cx = 0; + sr.es = sr.ds; + r.e.edi = (uint)regs; + PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ +} + +#define IN(reg) rmregs.reg = in->e.reg +#define OUT(reg) out->e.reg = rmregs.reg + +int PMAPI PM_int86(int intno, RMREGS *in, RMREGS *out) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + +/* These real mode ints may cause crashes. */ +/*AM: DPMI_int86(intno,&rmregs); /###* DPMI issue real interrupt */ + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +int PMAPI PM_int86x(int intno, RMREGS *in, RMREGS *out, + RMSREGS *sregs) +{ + DPMI_regs rmregs; + + memset(&rmregs, 0, sizeof(rmregs)); + IN(eax); IN(ebx); IN(ecx); IN(edx); IN(esi); IN(edi); + rmregs.es = sregs->es; + rmregs.ds = sregs->ds; + +/*AM: DPMI_int86(intno,&rmregs); /###* DPMI issue real interrupt */ + + OUT(eax); OUT(ebx); OUT(ecx); OUT(edx); OUT(esi); OUT(edi); + sregs->es = rmregs.es; + sregs->cs = rmregs.cs; + sregs->ss = rmregs.ss; + sregs->ds = rmregs.ds; + out->x.cflag = rmregs.flags & 0x1; + return out->x.ax; +} + +#pragma pack(1) + +typedef struct { + uint LargestBlockAvail; + uint MaxUnlockedPage; + uint LargestLockablePage; + uint LinAddrSpace; + uint NumFreePagesAvail; + uint NumPhysicalPagesFree; + uint TotalPhysicalPages; + uint FreeLinAddrSpace; + uint SizeOfPageFile; + uint res[3]; + } MemInfo; + +#pragma pack() + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ + PMREGS r; + PMSREGS sr; + MemInfo memInfo; + + PM_segread(&sr); + r.x.ax = 0x500; /* DPMI get free memory info */ + sr.es = sr.ds; + r.e.edi = (uint)&memInfo; + PM_int386x(0x31, &r, &r, &sr); /* Issue the interrupt */ + *physical = memInfo.NumPhysicalPagesFree * 4096; + *total = memInfo.LargestBlockAvail; + if (*total < *physical) + *physical = *total; +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + /* TODO: Implement this! */ + return 0; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c b/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c new file mode 100644 index 000000000..98e31bc63 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/pmsmx.c @@ -0,0 +1,471 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit SMX embedded systems development +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include +#include +#include +#include +#include "smx/ps2mouse.h" + +/*--------------------------- Global variables ----------------------------*/ + +static int globalDataStart; + +PM_criticalHandler _VARAPI _PM_critHandler = NULL; +PM_breakHandler _VARAPI _PM_breakHandler = NULL; +PM_intHandler _VARAPI _PM_timerHandler = NULL; +PM_intHandler _VARAPI _PM_rtcHandler = NULL; +PM_intHandler _VARAPI _PM_keyHandler = NULL; +PM_key15Handler _VARAPI _PM_key15Handler = NULL; +PM_mouseHandler _VARAPI _PM_mouseHandler = NULL; +PM_intHandler _VARAPI _PM_int10Handler = NULL; +int _VARAPI _PM_mouseMask; + +uchar * _VARAPI _PM_ctrlCPtr; /* Location of Ctrl-C flag */ +uchar * _VARAPI _PM_ctrlBPtr; /* Location of Ctrl-Break flag */ +uchar * _VARAPI _PM_critPtr; /* Location of Critical error Bf*/ +PMFARPTR _VARAPI _PM_prevTimer = PMNULL; /* Previous timer handler */ +PMFARPTR _VARAPI _PM_prevRTC = PMNULL; /* Previous RTC handler */ +PMFARPTR _VARAPI _PM_prevKey = PMNULL; /* Previous key handler */ +PMFARPTR _VARAPI _PM_prevKey15 = PMNULL; /* Previous key15 handler */ +PMFARPTR _VARAPI _PM_prevBreak = PMNULL; /* Previous break handler */ +PMFARPTR _VARAPI _PM_prevCtrlC = PMNULL; /* Previous CtrlC handler */ +PMFARPTR _VARAPI _PM_prevCritical = PMNULL; /* Previous critical handler */ +long _VARAPI _PM_prevRealTimer; /* Previous real mode timer */ +long _VARAPI _PM_prevRealRTC; /* Previous real mode RTC */ +long _VARAPI _PM_prevRealKey; /* Previous real mode key */ +long _VARAPI _PM_prevRealKey15; /* Previous real mode key15 */ +long _VARAPI _PM_prevRealInt10; /* Previous real mode int 10h */ +static uchar _PM_oldCMOSRegA; /* CMOS register A contents */ +static uchar _PM_oldCMOSRegB; /* CMOS register B contents */ +static uchar _PM_oldRTCPIC2; /* Mask value for RTC IRQ8 */ + +/*----------------------------- Implementation ----------------------------*/ + +/* Globals for locking interrupt handlers in _pmsmx.asm */ + +extern int _ASMAPI _PM_pmsmxDataStart; +extern int _ASMAPI _PM_pmsmxDataEnd; +void _ASMAPI _PM_pmsmxCodeStart(void); +void _ASMAPI _PM_pmsmxCodeEnd(void); + +/* Protected mode interrupt handlers, also called by PM callbacks below */ + +void _ASMAPI _PM_timerISR(void); +void _ASMAPI _PM_rtcISR(void); +void _ASMAPI _PM_keyISR(void); +void _ASMAPI _PM_key15ISR(void); +void _ASMAPI _PM_breakISR(void); +void _ASMAPI _PM_ctrlCISR(void); +void _ASMAPI _PM_criticalISR(void); +void _ASMAPI _PM_mouseISR(void); +void _ASMAPI _PM_int10PMCB(void); + +/* Protected mode DPMI callback handlers */ + +void _ASMAPI _PM_mousePMCB(void); + +/* Routine to install a mouse handler function */ + +void _ASMAPI _PM_setMouseHandler(int mask); + +/* Routine to allocate DPMI real mode callback routines */ + +void _ASMAPI _DPMI_allocateCallback(void (_ASMAPI *pmcode)(),void *rmregs,long *RMCB); +void _ASMAPI _DPMI_freeCallback(long RMCB); + +/* DPMI helper functions in PMLITE.C */ + +ulong PMAPI DPMI_mapPhysicalToLinear(ulong physAddr,ulong limit); +int PMAPI DPMI_setSelectorBase(ushort sel,ulong linAddr); +ulong PMAPI DPMI_getSelectorBase(ushort sel); +int PMAPI DPMI_setSelectorLimit(ushort sel,ulong limit); +uint PMAPI DPMI_createSelector(ulong base,ulong limit); +void PMAPI DPMI_freeSelector(uint sel); +int PMAPI DPMI_lockLinearPages(ulong linear,ulong len); +int PMAPI DPMI_unlockLinearPages(ulong linear,ulong len); + +/* Functions to read and write CMOS registers */ + +uchar PMAPI _PM_readCMOS(int index); +void PMAPI _PM_writeCMOS(int index,uchar value); + +/*-------------------------------------------------------------------------*/ +/* Generic routines common to all environments */ +/*-------------------------------------------------------------------------*/ + +void PMAPI PM_resetMouseDriver(int hardReset) +{ + ps2MouseReset(); +} + +void PMAPI PM_setRealTimeClockFrequency(int frequency) +{ + static short convert[] = { + 8192, + 4096, + 2048, + 1024, + 512, + 256, + 128, + 64, + 32, + 16, + 8, + 4, + 2, + -1, + }; + int i; + + /* First clear any pending RTC timeout if not cleared */ + _PM_readCMOS(0x0C); + if (frequency == 0) { + /* Disable RTC timout */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F); + } + else { + /* Convert frequency value to RTC clock indexes */ + for (i = 0; convert[i] != -1; i++) { + if (convert[i] == frequency) + break; + } + + /* Set RTC timout value and enable timeout */ + _PM_writeCMOS(0x0A,(_PM_oldCMOSRegA & 0xF0) | (i+3)); + _PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40); + } +} + +static void PMAPI lockPMHandlers(void) +{ + static int locked = 0; + int stat = 0; + PM_lockHandle lh; + + /* Lock all of the code and data used by our protected mode interrupt + * handling routines, so that it will continue to work correctly + * under real mode. + */ + if (!locked) { + PM_saveDS(); + stat = !PM_lockDataPages(&globalDataStart-2048,4096,&lh); + stat |= !PM_lockDataPages(&_PM_pmsmxDataStart,(int)&_PM_pmsmxDataEnd - (int)&_PM_pmsmxDataStart,&lh); + stat |= !PM_lockCodePages((__codePtr)_PM_pmsmxCodeStart,(int)_PM_pmsmxCodeEnd-(int)_PM_pmsmxCodeStart,&lh); + if (stat) { + printf("Page locking services failed - interrupt handling not safe!\n"); + exit(1); + } + locked = 1; + } +} + +void PMAPI PM_getPMvect(int intno, PMFARPTR *isr) +{ + PMREGS regs; + + regs.x.ax = 0x204; + regs.h.bl = intno; + PM_int386(0x31,®s,®s); + isr->sel = regs.x.cx; + isr->off = regs.e.edx; +} + +void PMAPI PM_setPMvect(int intno, PM_intHandler isr) +{ + PMSREGS sregs; + PMREGS regs; + + PM_saveDS(); + regs.x.ax = 0x205; /* Set protected mode vector */ + regs.h.bl = intno; + PM_segread(&sregs); + regs.x.cx = sregs.cs; + regs.e.edx = (uint)isr; + PM_int386(0x31,®s,®s); +} + +void PMAPI PM_restorePMvect(int intno, PMFARPTR isr) +{ + PMREGS regs; + + regs.x.ax = 0x205; + regs.h.bl = intno; + regs.x.cx = isr.sel; + regs.e.edx = isr.off; + PM_int386(0x31,®s,®s); +} + +static long prevRealBreak; /* Previous real mode break handler */ +static long prevRealCtrlC; /* Previous real mode CtrlC handler */ +static long prevRealCritical; /* Prev real mode critical handler */ + +int PMAPI PM_setMouseHandler(int mask, PM_mouseHandler mh) +{ + lockPMHandlers(); /* Ensure our handlers are locked */ + + _PM_mouseHandler = mh; + return 0; +} + +void PMAPI PM_restoreMouseHandler(void) +{ + if (_PM_mouseHandler) + _PM_mouseHandler = NULL; +} + +static void getISR(int intno, PMFARPTR *pmisr, long *realisr) +{ + PM_getPMvect(intno,pmisr); +} + +static void restoreISR(int intno, PMFARPTR pmisr, long realisr) +{ + PM_restorePMvect(intno,pmisr); +} + +static void setISR(int intno, void (* PMAPI pmisr)()) +{ + lockPMHandlers(); /* Ensure our handlers are locked */ + PM_setPMvect(intno,pmisr); +} + +void PMAPI PM_setTimerHandler(PM_intHandler th) +{ + getISR(PM_IRQ0, &_PM_prevTimer, &_PM_prevRealTimer); + _PM_timerHandler = th; + setISR(PM_IRQ0, _PM_timerISR); +} + +void PMAPI PM_restoreTimerHandler(void) +{ + if (_PM_timerHandler) { + restoreISR(PM_IRQ0, _PM_prevTimer, _PM_prevRealTimer); + _PM_timerHandler = NULL; + } +} + +ibool PMAPI PM_setRealTimeClockHandler(PM_intHandler th,int frequency) +{ + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + getISR(0x70, &_PM_prevRTC, &_PM_prevRealRTC); + _PM_rtcHandler = th; + setISR(0x70, _PM_rtcISR); + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC2 */ + _PM_oldRTCPIC2 = PM_inpb(0xA1); + PM_outpb(0xA1,_PM_oldRTCPIC2 & 0xFE); + return true; +} + +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (_PM_rtcHandler) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + PM_outpb(0xA1,(PM_inpb(0xA1) & 0xFE) | (_PM_oldRTCPIC2 & ~0xFE)); + + /* Restore the interrupt vector */ + restoreISR(0x70, _PM_prevRTC, _PM_prevRealRTC); + _PM_rtcHandler = NULL; + } +} + +void PMAPI PM_setKeyHandler(PM_intHandler kh) +{ + getISR(PM_IRQ1, &_PM_prevKey, &_PM_prevRealKey); + _PM_keyHandler = kh; + setISR(PM_IRQ1, _PM_keyISR); +} + +void PMAPI PM_restoreKeyHandler(void) +{ + if (_PM_keyHandler) { + restoreISR(PM_IRQ1, _PM_prevKey, _PM_prevRealKey); + _PM_keyHandler = NULL; + } +} + +void PMAPI PM_setKey15Handler(PM_key15Handler kh) +{ + getISR(0x15, &_PM_prevKey15, &_PM_prevRealKey15); + _PM_key15Handler = kh; + setISR(0x15, _PM_key15ISR); +} + +void PMAPI PM_restoreKey15Handler(void) +{ + if (_PM_key15Handler) { + restoreISR(0x15, _PM_prevKey15, _PM_prevRealKey15); + _PM_key15Handler = NULL; + } +} + +/* Real mode Ctrl-C and Ctrl-Break handler. This handler simply sets a + * flag in the real mode code segment and exit. We save the location + * of this flag in real mode memory so that both the real mode and + * protected mode code will be modifying the same flags. + */ + +static uchar ctrlHandler[] = { + 0x00,0x00,0x00,0x00, /* ctrlBFlag */ + 0x66,0x2E,0xC7,0x06,0x00,0x00, + 0x01,0x00,0x00,0x00, /* mov [cs:ctrlBFlag],1 */ + 0xCF, /* iretf */ + }; + +void PMAPI PM_installAltBreakHandler(PM_breakHandler bh) +{ + uint rseg,roff; + + getISR(0x1B, &_PM_prevBreak, &prevRealBreak); + getISR(0x23, &_PM_prevCtrlC, &prevRealCtrlC); + _PM_breakHandler = bh; + setISR(0x1B, _PM_breakISR); + setISR(0x23, _PM_ctrlCISR); + + /* Hook the real mode vectors for these handlers, as these are not + * normally reflected by the DPMI server up to protected mode + */ + _PM_ctrlBPtr = PM_allocRealSeg(sizeof(ctrlHandler)*2, &rseg, &roff); + memcpy(_PM_ctrlBPtr,ctrlHandler,sizeof(ctrlHandler)); + memcpy(_PM_ctrlBPtr+sizeof(ctrlHandler),ctrlHandler,sizeof(ctrlHandler)); + _PM_ctrlCPtr = _PM_ctrlBPtr + sizeof(ctrlHandler); + _PM_setRMvect(0x1B,((long)rseg << 16) | (roff+4)); + _PM_setRMvect(0x23,((long)rseg << 16) | (roff+sizeof(ctrlHandler)+4)); +} + +void PMAPI PM_installBreakHandler(void) +{ + PM_installAltBreakHandler(NULL); +} + +void PMAPI PM_restoreBreakHandler(void) +{ + if (_PM_prevBreak.sel) { + restoreISR(0x1B, _PM_prevBreak, prevRealBreak); + restoreISR(0x23, _PM_prevCtrlC, prevRealCtrlC); + _PM_prevBreak.sel = 0; + _PM_breakHandler = NULL; + PM_freeRealSeg(_PM_ctrlBPtr); + } +} + +/* Real mode Critical Error handler. This handler simply saves the AX and + * DI values in the real mode code segment and exits. We save the location + * of this flag in real mode memory so that both the real mode and + * protected mode code will be modifying the same flags. + */ + +static uchar criticalHandler[] = { + 0x00,0x00, /* axCode */ + 0x00,0x00, /* diCode */ + 0x2E,0xA3,0x00,0x00, /* mov [cs:axCode],ax */ + 0x2E,0x89,0x3E,0x02,0x00, /* mov [cs:diCode],di */ + 0xB8,0x03,0x00, /* mov ax,3 */ + 0xCF, /* iretf */ + }; + +void PMAPI PM_installAltCriticalHandler(PM_criticalHandler ch) +{ + uint rseg,roff; + + getISR(0x24, &_PM_prevCritical, &prevRealCritical); + _PM_critHandler = ch; + setISR(0x24, _PM_criticalISR); + + /* Hook the real mode vector, as this is not normally reflected by the + * DPMI server up to protected mode. + */ + _PM_critPtr = PM_allocRealSeg(sizeof(criticalHandler)*2, &rseg, &roff); + memcpy(_PM_critPtr,criticalHandler,sizeof(criticalHandler)); + _PM_setRMvect(0x24,((long)rseg << 16) | (roff+4)); +} + +void PMAPI PM_installCriticalHandler(void) +{ + PM_installAltCriticalHandler(NULL); +} + +void PMAPI PM_restoreCriticalHandler(void) +{ + if (_PM_prevCritical.sel) { + restoreISR(0x24, _PM_prevCritical, prevRealCritical); + PM_freeRealSeg(_PM_critPtr); + _PM_prevCritical.sel = 0; + _PM_critHandler = NULL; + } +} + +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_lockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); +} + +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_unlockLinearPages((uint)p + DPMI_getSelectorBase(sregs.ds),len); +} + +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); +/*AM: causes minor glitch with */ +/*AM: older versions pmEasy which don't allow DPMI 06 on */ +/*AM: Code selector 0x0C -- assume base is 0 which it should be. */ + return DPMI_lockLinearPages((uint)p,len); +} + +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + PMSREGS sregs; + PM_segread(&sregs); + return DPMI_unlockLinearPages((uint)p,len); +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c new file mode 100644 index 000000000..579ef2c95 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c new file mode 100644 index 000000000..794119282 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/smx/ztimer.c @@ -0,0 +1,115 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit SMX embedded systems development +* +* Description: OS specific implementation for the Zen Timer functions. +* LZTimer not supported for smx (as needed for i486 processors), only +* ULZTimer is supported at this time. +* +****************************************************************************/ + +/*---------------------------- Global smx variables -----------------------*/ + +extern ulong _cdecl etime; /* elapsed time */ +extern ulong _cdecl xticks_per_second(void); + +/*----------------------------- Implementation ----------------------------*/ + +/* External assembler functions */ + +void _ASMAPI LZ_disable(void); +void _ASMAPI LZ_enable(void); + + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ +} + +ulong reterr(void) +{ + PM_fatalError("Zen Timer not supported for smx."); + return(0); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOn(tm) PM_fatalError("Zen Timer not supported for smx.") + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerLap(tm) reterr() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) PM_fatalError("Zen Timer not supported for smx.") + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerCount(tm) reterr() + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as seconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION (ulong)(1000000/xticks_per_second()) + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the smx timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + ulong ticks; + LZ_disable(); /* Turn of interrupts */ + ticks = etime; + LZ_enable(); /* Turn on interrupts again */ + return ticks; +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ + if (finish < start) + finish += xticks_per_second() * 3600 *24; /* Number of ticks in 24 hours */ + return finish - start; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c new file mode 100644 index 000000000..0615e9016 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/cpuinfo.c @@ -0,0 +1,79 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: Module to implement OS specific services to measure the +* CPU frequency. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Increase the thread priority to maximum, if possible. +****************************************************************************/ +static int SetMaxThreadPriority(void) +{ + /* TODO: If you have thread priorities, increase it to maximum for the */ + /* thread for timing the CPU frequency. */ + return oldPriority; +} + +/**************************************************************************** +REMARKS: +Restore the original thread priority. +****************************************************************************/ +static void RestoreThreadPriority( + int priority) +{ + /* TODO: Restore the original thread priority on exit. */ +} + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + /* TODO: Return the frequency of the counter in here. You should try to */ + /* normalise this value to be around 100,000 ticks per second. */ + freq->low = 0; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. + +TODO: Implement this to read the counter. It should be done as a macro + for accuracy. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + (t)->low = 0; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/event.c b/board/MAI/bios_emulator/scitech/src/pm/stub/event.c new file mode 100644 index 000000000..204c49254 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/event.c @@ -0,0 +1,199 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: **** implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under non-DOS systems */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + /* TODO: Implement this for your OS! */ +} + +/**************************************************************************** +REMARKS: +Pumps all messages in the application message queue into our event queue. +****************************************************************************/ +static void _EVT_pumpMessages(void) +{ + /* TODO: The purpose of this function is to read all keyboard and mouse */ + /* events from the OS specific event queue, translate them and post */ + /* them into the SciTech event queue. */ + /* */ + /* NOTE: There are a couple of important things that this function must */ + /* take care of: */ + /* */ + /* 1. Support for KEYDOWN, KEYREPEAT and KEYUP is required. */ + /* */ + /* 2. Support for reading hardware scan code as well as ASCII */ + /* translated values is required. Games use the scan codes rather */ + /* than ASCII values. Scan codes go into the high order byte of the */ + /* keyboard message field. */ + /* */ + /* 3. Support for at least reading mouse motion data (mickeys) from the */ + /* mouse is required. Using the mickey values, we can then translate */ + /* to mouse cursor coordinates scaled to the range of the current */ + /* graphics display mode. Mouse values are scaled based on the */ + /* global 'rangeX' and 'rangeY'. */ + /* */ + /* 4. Support for a timestamp for the events is required, which is */ + /* defined as the number of milliseconds since some event (usually */ + /* system startup). This is the timestamp when the event occurred */ + /* (ie: at interrupt time) not when it was stuff into the SciTech */ + /* event queue. */ + /* */ + /* 5. Support for mouse double click events. If the OS has a native */ + /* mechanism to determine this, it should be used. Otherwise the */ + /* time stamp information will be used by the generic event code */ + /* to generate double click events. */ +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + /* Initialise the event queue */ + _mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* TODO: Do any OS specific initialisation here */ + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* TODO: Do any OS specific cleanup in here */ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h new file mode 100644 index 000000000..1395cbc3c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/oshdr.h @@ -0,0 +1,33 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: BeOS +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +/* TODO: This is where you include OS specific headers for the event handling */ +/* library. You may leave this empty if you have no OS specific headers */ +/* to include. */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c b/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c new file mode 100644 index 000000000..5f278c32d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/pm.c @@ -0,0 +1,980 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include +#include +#include + +/* TODO: Include any OS specific headers here! */ + +/*--------------------------- Global variables ----------------------------*/ + +/* TODO: If you support access to the BIOS, the following VESABuf globals */ +/* keep track of a single VESA transfer buffer. If you don't support */ +/* access to the BIOS, remove these variables. */ + +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL; /* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the PM library. +****************************************************************************/ +void PMAPI PM_init(void) +{ + /* TODO: Do any initialisation in here. This includes getting IOPL */ + /* access for the process calling PM_init. This will get called */ + /* more than once. */ + + /* TODO: If you support the supplied MTRR register stuff (you need to */ + /* be at ring 0 for this!), you should initialise it in here. */ + +/* MTRR_init(); */ +} + +/**************************************************************************** +REMARKS: +Return the operating system type identifier. +****************************************************************************/ +long PMAPI PM_getOSType(void) +{ + /* TODO: Change this to return the define for your OS from drvlib/os.h */ + return _OS_MYOS; +} + +/**************************************************************************** +REMARKS: +Return the runtime type identifier (always PM_386 for protected mode) +****************************************************************************/ +int PMAPI PM_getModeType(void) +{ return PM_386; } + +/**************************************************************************** +REMARKS: +Add a file directory separator to the end of the filename. +****************************************************************************/ +void PMAPI PM_backslash( + char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '/') { + s[pos] = '/'; + s[pos+1] = '\0'; + } +} + +/**************************************************************************** +REMARKS: +Add a user defined PM_fatalError cleanup function. +****************************************************************************/ +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +/**************************************************************************** +REMARKS: +Report a fatal error condition and halt the program. +****************************************************************************/ +void PMAPI PM_fatalError( + const char *msg) +{ + /* TODO: If you are running in a GUI environment without a console, */ + /* this needs to be changed to bring up a fatal error message */ + /* box and terminate the program. */ + if (fatalErrorCleanup) + fatalErrorCleanup(); + fprintf(stderr,"%s\n", msg); + exit(1); +} + +/**************************************************************************** +REMARKS: +Exit handler to kill the VESA transfer buffer. +****************************************************************************/ +static void ExitVBEBuf(void) +{ + /* TODO: If you do not have BIOS access, remove this function. */ + if (VESABuf_ptr) + PM_freeRealSeg(VESABuf_ptr); + VESABuf_ptr = 0; +} + +/**************************************************************************** +REMARKS: +Allocate the real mode VESA transfer buffer for communicating with the BIOS. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + /* TODO: If you do not have BIOS access, simply delete the guts of */ + /* this function and return NULL. */ + if (!VESABuf_ptr) { + /* Allocate a global buffer for communicating with the VESA VBE */ + if ((VESABuf_ptr = PM_allocRealSeg(VESABuf_len, &VESABuf_rseg, &VESABuf_roff)) == NULL) + return NULL; + atexit(ExitVBEBuf); + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +/**************************************************************************** +REMARKS: +Check if a key has been pressed. +****************************************************************************/ +int PMAPI PM_kbhit(void) +{ + /* TODO: This function checks if a key is available to be read. This */ + /* should be implemented, but is mostly used by the test programs */ + /* these days. */ + return true; +} + +/**************************************************************************** +REMARKS: +Wait for and return the next keypress. +****************************************************************************/ +int PMAPI PM_getch(void) +{ + /* TODO: This returns the ASCII code of the key pressed. This */ + /* should be implemented, but is mostly used by the test programs */ + /* these days. */ + return 0xD; +} + +/**************************************************************************** +REMARKS: +Open a fullscreen console mode for output. +****************************************************************************/ +int PMAPI PM_openConsole(void) +{ + /* TODO: Opens up a fullscreen console for graphics output. If your */ + /* console does not have graphics/text modes, this can be left */ + /* empty. The main purpose of this is to disable console switching */ + /* when in graphics modes if you can switch away from fullscreen */ + /* consoles (if you want to allow switching, this can be done */ + /* elsewhere with a full save/restore state of the graphics mode). */ + return 0; +} + +/**************************************************************************** +REMARKS: +Return the size of the state buffer used to save the console state. +****************************************************************************/ +int PMAPI PM_getConsoleStateSize(void) +{ + /* TODO: Returns the size of the console state buffer used to save the */ + /* state of the console before going into graphics mode. This is */ + /* used to restore the console back to normal when we are done. */ + return 1; +} + +/**************************************************************************** +REMARKS: +Save the state of the console into the state buffer. +****************************************************************************/ +void PMAPI PM_saveConsoleState( + void *stateBuf, + int console_id) +{ + /* TODO: Saves the state of the console into the state buffer. This is */ + /* used to restore the console back to normal when we are done. */ + /* We will always restore 80x25 text mode after being in graphics */ + /* mode, so if restoring text mode is all you need to do this can */ + /* be left empty. */ +} + +/**************************************************************************** +REMARKS: +Restore the state of the console from the state buffer. +****************************************************************************/ +void PMAPI PM_restoreConsoleState( + const void *stateBuf, + int console_id) +{ + /* TODO: Restore the state of the console from the state buffer. This is */ + /* used to restore the console back to normal when we are done. */ + /* We will always restore 80x25 text mode after being in graphics */ + /* mode, so if restoring text mode is all you need to do this can */ + /* be left empty. */ +} + +/**************************************************************************** +REMARKS: +Close the console and return to non-fullscreen console mode. +****************************************************************************/ +void PMAPI PM_closeConsole( + int console_id) +{ + /* TODO: Close the console when we are done, going back to text mode. */ +} + +/**************************************************************************** +REMARKS: +Set the location of the OS console cursor. +****************************************************************************/ +void PM_setOSCursorLocation( + int x, + int y) +{ + /* TODO: Set the OS console cursor location to the new value. This is */ + /* generally used for new OS ports (used mostly for DOS). */ +} + +/**************************************************************************** +REMARKS: +Set the width of the OS console. +****************************************************************************/ +void PM_setOSScreenWidth( + int width, + int height) +{ + /* TODO: Set the OS console screen width. This is generally unused for */ + /* new OS ports. */ +} + +/**************************************************************************** +REMARKS: +Set the real time clock handler (used for software stereo modes). +****************************************************************************/ +ibool PMAPI PM_setRealTimeClockHandler( + PM_intHandler ih, + int frequency) +{ + /* TODO: Install a real time clock interrupt handler. Normally this */ + /* will not be supported from most OS'es in user land, so an */ + /* alternative mechanism is needed to enable software stereo. */ + /* Hence leave this unimplemented unless you have a high priority */ + /* mechanism to call the 32-bit callback when the real time clock */ + /* interrupt fires. */ + return false; +} + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + /* TODO: Set the real time clock interrupt frequency. Used for stereo */ + /* LC shutter glasses when doing software stereo. Usually sets */ + /* the frequency to around 2048 Hz. */ +} + +/**************************************************************************** +REMARKS: +Restore the original real time clock handler. +****************************************************************************/ +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* TODO: Restores the real time clock handler. */ +} + +/**************************************************************************** +REMARKS: +Return the current operating system path or working directory. +****************************************************************************/ +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +/**************************************************************************** +REMARKS: +Return the drive letter for the boot drive. +****************************************************************************/ +char PMAPI PM_getBootDrive(void) +{ + /* TODO: Return the boot drive letter for the OS. Normally this is 'c' */ + /* for DOS based OS'es and '/' for Unices. */ + return '/'; +} + +/**************************************************************************** +REMARKS: +Return the path to the VBE/AF driver files (legacy and not used). +****************************************************************************/ +const char * PMAPI PM_getVBEAFPath(void) +{ + return PM_getNucleusConfigPath(); +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus driver files. +****************************************************************************/ +const char * PMAPI PM_getNucleusPath(void) +{ + /* TODO: Change this to the default path to Nucleus driver files. The */ + /* following is the default for Unices. */ + char *env = getenv("NUCLEUS_PATH"); + return env ? env : "/usr/lib/nucleus"; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus configuration files. +****************************************************************************/ +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +/**************************************************************************** +REMARKS: +Return a unique identifier for the machine if possible. +****************************************************************************/ +const char * PMAPI PM_getUniqueID(void) +{ + /* TODO: Return a unique ID for the machine. If a unique ID is not */ + /* available, return the machine name. */ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +/**************************************************************************** +REMARKS: +Get the name of the machine on the network. +****************************************************************************/ +const char * PMAPI PM_getMachineName(void) +{ + /* TODO: Return the network machine name for the machine. */ + static char buf[128]; + gethostname(buf, 128); + return buf; +} + +/**************************************************************************** +REMARKS: +Return a pointer to the real mode BIOS data area. +****************************************************************************/ +void * PMAPI PM_getBIOSPointer(void) +{ + /* TODO: This returns a pointer to the real mode BIOS data area. If you */ + /* do not support BIOS access, you can simply return NULL here. */ + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF,true); + return (void*)(zeroPtr + 0x400); +} + +/**************************************************************************** +REMARKS: +Return a pointer to 0xA0000 physical VGA graphics framebuffer. +****************************************************************************/ +void * PMAPI PM_getA0000Pointer(void) +{ + static void *bankPtr; + if (!bankPtr) + bankPtr = PM_mapPhysicalAddr(0xA0000,0xFFFF,true); + return bankPtr; +} + +/**************************************************************************** +REMARKS: +Map a physical address to a linear address in the callers process. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + /* TODO: This function maps a physical memory address to a linear */ + /* address in the address space of the calling process. */ + + /* NOTE: This function *must* be able to handle any phsyical base */ + /* address, and hence you will have to handle rounding of */ + /* the physical base address to a page boundary (ie: 4Kb on */ + /* x86 CPU's) to be able to properly map in the memory */ + /* region. */ + + /* NOTE: If possible the isCached bit should be used to ensure that */ + /* the PCD (Page Cache Disable) and PWT (Page Write Through) */ + /* bits are set to disable caching for a memory mapping used */ + /* for MMIO register access. We also disable caching using */ + /* the MTRR registers for Pentium Pro and later chipsets so if */ + /* MTRR support is enabled for your OS then you can safely ignore */ + /* the isCached flag and always enable caching in the page */ + /* tables. */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a physical address mapping allocated by PM_mapPhysicalAddr. +****************************************************************************/ +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + /* TODO: This function will free a physical memory mapping previously */ + /* allocated with PM_mapPhysicalAddr() if at all possible. If */ + /* you can't free physical memory mappings, simply do nothing. */ +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* TODO: Put the process to sleep for milliseconds */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of (unnamed) shared memory. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + /* TODO: This is used to allocate memory that is shared between process */ + /* that all access the common Nucleus drivers via a common display */ + /* driver DLL. If your OS does not support shared memory (or if */ + /* the display driver does not need to allocate shared memory */ + /* for each process address space), this should just call PM_malloc. */ + return PM_malloc(size); +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory. +****************************************************************************/ +void PMAPI PM_freeShared( + void *ptr) +{ + /* TODO: Free the shared memory block. This will be called in the context */ + /* of the original calling process that allocated the shared */ + /* memory with PM_mallocShared. Simply call PM_free if you do not */ + /* need this. */ + PM_free(ptr); +} + +/**************************************************************************** +REMARKS: +Map a linear memory address to the calling process address space. The +address will have been allocated in another process using the +PM_mapPhysicalAddr function. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + /* TODO: This function is used to map a physical memory mapping */ + /* previously allocated with PM_mapPhysicalAddr into the */ + /* address space of the calling process. If the memory mapping */ + /* allocated by PM_mapPhysicalAddr is global to all processes, */ + /* simply return the pointer. */ + + /* NOTE: This function must also handle rounding to page boundaries, */ + /* since this function is used to map in shared memory buffers */ + /* allocated with PM_mapPhysicalAddr(). Hence if you aligned */ + /* the physical address above, then you also need to do it here. */ + return base; +} + +/**************************************************************************** +REMARKS: +Map a real mode pointer to a protected mode pointer. +****************************************************************************/ +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + /* TODO: This function maps a real mode memory pointer into the */ + /* calling processes address space as a 32-bit near pointer. If */ + /* you do not support BIOS access, simply return NULL here. */ + if (!zeroPtr) + zeroPtr = PM_mapPhysicalAddr(0,0xFFFFF); + return (void*)(zeroPtr + MK_PHYS(r_seg,r_off)); +} + +/**************************************************************************** +REMARKS: +Allocate a block of real mode memory +****************************************************************************/ +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + /* TODO: This function allocates a block of real mode memory for the */ + /* calling process used to communicate with real mode BIOS */ + /* functions. If you do not support BIOS access, simply return */ + /* NULL here. */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of real mode memory. +****************************************************************************/ +void PMAPI PM_freeRealSeg( + void *mem) +{ + /* TODO: Frees a previously allocated real mode memory block. If you */ + /* do not support BIOS access, this function should be empty. */ +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt (parameters in DPMI compatible structure) +****************************************************************************/ +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + /* TODO: This function calls the real mode BIOS using the passed in */ + /* register structure. If you do not support real mode BIOS */ + /* access, this function should be empty. */ +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + /* TODO: This function calls the real mode BIOS using the passed in */ + /* register structure. If you do not support real mode BIOS */ + /* access, this function should return 0. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + /* TODO: This function calls the real mode BIOS using the passed in */ + /* register structure. If you do not support real mode BIOS */ + /* access, this function should return 0. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Call a real mode far function. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *in, + RMSREGS *sregs) +{ + /* TODO: This function calls a real mode far function with a far call. */ + /* If you do not support BIOS access, this function should be */ + /* empty. */ +} + +/**************************************************************************** +REMARKS: +Return the amount of available memory. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + /* TODO: Report the amount of available memory, both the amount of */ + /* physical memory left and the amount of virtual memory left. */ + /* If the OS does not provide these services, report 0's. */ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of locked, physical memory for DMA operations. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + /* TODO: Allocate a block of locked, physical memory of the specified */ + /* size. This is used for bus master operations. If this is not */ + /* supported by the OS, return NULL and bus mastering will not */ + /* be used. */ + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + /* TODO: Free a memory block allocated with PM_allocLockedMem. */ +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankA( + int bank) +{ + RMREGS regs; + + /* TODO: This does a bank switch function by calling the real mode */ + /* VESA BIOS. If you do not support BIOS access, this function should */ + /* be empty. */ + regs.x.ax = 0x4F05; + regs.x.bx = 0x0000; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankAB( + int bank) +{ + RMREGS regs; + + /* TODO: This does a bank switch function by calling the real mode */ + /* VESA BIOS. If you do not support BIOS access, this function should */ + /* be empty. */ + regs.x.ax = 0x4F05; + regs.x.bx = 0x0000; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); + regs.x.ax = 0x4F05; + regs.x.bx = 0x0001; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display start address. +****************************************************************************/ +void PMAPI PM_setCRTStart( + int x, + int y, + int waitVRT) +{ + RMREGS regs; + + /* TODO: This changes the display start address by calling the real mode */ + /* VESA BIOS. If you do not support BIOS access, this function */ + /* should be empty. */ + regs.x.ax = 0x4F07; + regs.x.bx = waitVRT; + regs.x.cx = x; + regs.x.dx = y; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Enable write combining for the memory region. +****************************************************************************/ +ibool PMAPI PM_enableWriteCombine( + ulong base, + ulong length, + uint type) +{ + /* TODO: This function should enable Pentium Pro and Pentium II MTRR */ + /* write combining for the passed in physical memory base address */ + /* and length. Normally this is done via calls to an OS specific */ + /* device driver as this can only be done at ring 0. */ + /* */ + /* NOTE: This is a *very* important function to implement! If you do */ + /* not implement, graphics performance on the latest Intel chips */ + /* will be severly impaired. For sample code that can be used */ + /* directly in a ring 0 device driver, see the MSDOS implementation */ + /* which includes assembler code to do this directly (if the */ + /* program is running at ring 0). */ + return false; +} + +/**************************************************************************** +REMARKS: +Execute the POST on the secondary BIOS for a controller. +****************************************************************************/ +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS) +{ + /* TODO: This function is used to run the BIOS POST code on a secondary */ + /* controller to initialise it for use. This is not necessary */ + /* for multi-controller operation, but it will make it a lot */ + /* more convenicent for end users (otherwise they have to boot */ + /* the system once with the secondary controller as primary, and */ + /* then boot with both controllers installed). */ + /* */ + /* Even if you don't support full BIOS access, it would be */ + /* adviseable to be able to POST the secondary controllers in the */ + /* system using this function as a minimum requirement. Some */ + /* graphics hardware has registers that contain values that only */ + /* the BIOS knows about, which makes bring up a card from cold */ + /* reset difficult if the BIOS has not POST'ed it. */ + return false; +} + +/**************************************************************************** +REMARKS: +Load an OS specific shared library or DLL. If the OS does not support +shared libraries, simply return NULL. +****************************************************************************/ +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + /* TODO: This function should load a native shared library from disk */ + /* given the path to the library. */ + (void)szDLLName; + return NULL; +} + +/**************************************************************************** +REMARKS: +Get the address of a named procedure from a shared library. +****************************************************************************/ +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + /* TODO: This function should return the address of a named procedure */ + /* from a native shared library. */ + (void)hModule; + (void)szProcName; + return NULL; +} + +/**************************************************************************** +REMARKS: +Unload a shared library. +****************************************************************************/ +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + /* TODO: This function free a previously loaded native shared library. */ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Enable requested I/O privledge level (usually only to set to a value of +3, and then restore it back again). If the OS is protected this function +must be implemented in order to enable I/O port access for ring 3 +applications. The function should return the IOPL level active before +the switch occurred so it can be properly restored. +****************************************************************************/ +int PMAPI PM_setIOPL( + int level) +{ + /* TODO: This function should enable IOPL for the task (if IOPL is */ + /* not always enabled for the app through some other means). */ + return level; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + /* TODO: This function should start a directory enumeration search */ + /* given the filename (with wildcards). The data should be */ + /* converted and returned in the findData standard form. */ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + /* TODO: This function should find the next file in directory enumeration */ + /* search given the search criteria defined in the call to */ + /* PM_findFirstFile. The data should be converted and returned */ + /* in the findData standard form. */ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + /* TODO: This function should close the find process. This may do */ + /* nothing for some OS'es. */ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + if (drive == 3) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + (void)drive; + getcwd(dir,len); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + /* TODO: Set the file attributes for a file */ + (void)filename; + (void)attrib; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + return mkdir(filename) == 0; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return rmdir(filename) == 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c new file mode 100644 index 000000000..579ef2c95 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/vflat.c @@ -0,0 +1,49 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + baseAddr = baseAddr; + bankSize = bankSize; + codeLen = codeLen; + bankFunc = bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c new file mode 100644 index 000000000..820e29239 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/stub/ztimer.c @@ -0,0 +1,111 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: *** TODO: ADD YOUR OS ENVIRONMENT NAME HERE *** +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ + /* TODO: Do any specific internal initialisation in here */ +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOn( + LZTimerObject *tm) +{ + /* TODO: Start the Zen Timer counting. This should be a macro if */ + /* possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + /* TODO: Compute the lap time between the current time and when the */ + /* timer was started. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Stop the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOff( + LZTimerObject *tm) +{ + /* TODO: Stop the timer counting. Should be a macro if possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time in microseconds between start and end timings. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + /* TODO: Compute the elapsed time and return it. Always microseconds. */ + return 0; +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1 + +/**************************************************************************** +REMARKS: +Read the Long Period timer from the OS +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + /* TODO: Read the long period timer from the OS. The resolution of this */ + /* timer should be around 1/20 of a second for timing long */ + /* periods if possible. */ +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c b/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c new file mode 100644 index 000000000..ba9026274 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/altbrk.c @@ -0,0 +1,90 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* control C/break interrupt handler. Note that this +* alternate version does not work with all extenders. +* +* Functions tested: PM_installAltBreakHandler() +* PM_restoreBreakHandler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile int breakHit = false; +volatile int ctrlCHit = false; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +void PMAPI breakHandler(uint bHit) +{ + if (bHit) + breakHit = true; + else + ctrlCHit = true; +} + +int main(void) +{ + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + PM_installAltBreakHandler(breakHandler); + printf("Control C/Break interrupt handler installed\n"); + while (1) { + if (ctrlCHit) { + printf("Code termimated with Ctrl-C.\n"); + break; + } + if (breakHit) { + printf("Code termimated with Ctrl-Break.\n"); + break; + } + if (PM_kbhit() && PM_getch() == 0x1B) { + printf("No break code detected!\n"); + break; + } + printf("Hit Ctrl-C or Ctrl-Break to exit!\n"); + } + + PM_restoreBreakHandler(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c b/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c new file mode 100644 index 000000000..e13730758 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/altcrit.c @@ -0,0 +1,85 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* critical error handler. +* +* Functions tested: PM_installCriticalHandler() +* PM_criticalError() +* PM_restoreCriticalHandler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile uint criticalError = false; +volatile uint axValue; +volatile uint diValue; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +uint PMAPI criticalHandler(uint axVal,uint diVal) +{ + criticalError = true; + axValue = axVal; + diValue = diVal; + return 3; /* Tell MS-DOS to fail the operation */ +} + +int main(void) +{ + FILE *f; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + PM_installAltCriticalHandler(criticalHandler); + printf("Critical Error handler installed - trying to read from A: drive...\n"); + f = fopen("a:\bog.bog","rb"); + if (f) fclose(f); + if (criticalError) { + printf("Critical error occured on INT 21h function %02X!\n", + axValue >> 8); + } + else + printf("Critical error was not caught!\n"); + PM_restoreCriticalHandler(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c b/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c new file mode 100644 index 000000000..5fa338248 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/biosptr.c @@ -0,0 +1,92 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to manipulate the +* BIOS data area from protected mode using the PM +* library. Compile and link with the appropriate command +* line for your DOS extender. +* +* Functions tested: PM_getBIOSSelector() +* PM_getLong() +* PM_getByte() +* PM_getWord() +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +/* Macros to obtain values from the BIOS data area */ + +#define TICKS() PM_getLong(bios+0x6C) +#define KB_STAT PM_getByte(bios+0x17) +#define KB_HEAD PM_getWord(bios+0x1A) +#define KB_TAIL PM_getWord(bios+0x1C) + +/* Macros for working with the keyboard buffer */ + +#define KB_HIT() (KB_HEAD != KB_TAIL) +#define CTRL() (KB_STAT & 4) +#define SHIFT() (KB_STAT & 2) +#define ESC 0x1B + +/* Selector for BIOS data area */ + +uchar *bios; + +int main(void) +{ + int c,done = 0; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + bios = PM_getBIOSPointer(); + printf("Hit any key to test, Ctrl-Shift-Esc to quit\n"); + while (!done) { + if (KB_HIT()) { + c = PM_getch(); + if (c == 0) PM_getch(); + printf("TIME=%-8lX ST=%02X CHAR=%02X ", TICKS(), KB_STAT, c); + printf("\n"); + if ((c == ESC) && SHIFT() && CTRL())/* Ctrl-Shift-Esc */ + break; + } + } + + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/block.c b/board/MAI/bios_emulator/scitech/src/pm/tests/block.c new file mode 100644 index 000000000..15d503c0d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/block.c @@ -0,0 +1,69 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Test program for the PM_blockUntilTimeout function. +* +****************************************************************************/ + +#include +#include "pmapi.h" + +#define DELAY_MSECS 1100 +#define LOOPS 5 + +/*-------------------------- Implementation -------------------------------*/ + +/* The following routine takes a long count in microseconds and outputs + * a string representing the count in seconds. It could be modified to + * return a pointer to a static string representing the count rather + * than printing it out. + */ + +void ReportTime(ulong count) +{ + ulong secs; + + secs = count / 1000000L; + count = count - secs * 1000000L; + printf("Time taken: %lu.%06lu seconds\n",secs,count); +} + +int main(void) +{ + int i; + + printf("Detecting processor information ..."); + fflush(stdout); + printf("\n\n%s\n", CPU_getProcessorName()); + ZTimerInit(); + LZTimerOn(); + for (i = 0; i < LOOPS; i++) { + PM_blockUntilTimeout(DELAY_MSECS); + ReportTime(LZTimerLap()); + } + LZTimerOff(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c b/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c new file mode 100644 index 000000000..10b644656 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/brk.c @@ -0,0 +1,78 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* control C/break interrupt handler. +* +* Functions tested: PM_installBreakHandler() +* PM_ctrlCHit() +* PM_ctrlBreakHit() +* PM_restoreBreakHandler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +int main(void) +{ + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + PM_installBreakHandler(); + printf("Control C/Break interrupt handler installed\n"); + while (1) { + if (PM_ctrlCHit(1)) { + printf("Code termimated with Ctrl-C.\n"); + break; + } + if (PM_ctrlBreakHit(1)) { + printf("Code termimated with Ctrl-Break.\n"); + break; + } + if (PM_kbhit() && PM_getch() == 0x1B) { + printf("No break code detected!\n"); + break; + } + printf("Hit Ctrl-C or Ctrl-Break to exit!\n"); + } + + PM_restoreBreakHandler(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c b/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c new file mode 100644 index 000000000..4d37cab46 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/callreal.c @@ -0,0 +1,107 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to call a real mode +* procedure. We simply copy a terribly simple assembly +* language routine into a real mode block that we allocate, +* and then attempt to call the routine and verify that it +* was successful. +* +* Functions tested: PM_allocRealSeg() +* PM_freeRealSeg() +* PM_callRealMode() +* +****************************************************************************/ + +#include +#include +#include +#include "pmapi.h" + +/* Block of real mode code we will eventually call */ + +static unsigned char realModeCode[] = { + 0x93, /* xchg ax,bx */ + 0x87, 0xCA, /* xchg cx,dx */ + 0xCB /* retf */ + }; + +int main(void) +{ + RMREGS regs; + RMSREGS sregs; + uchar *p; + unsigned r_seg,r_off; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Allocate a the block of real mode memory */ + if ((p = PM_allocRealSeg(sizeof(realModeCode), &r_seg, &r_off)) == NULL) { + printf("Unable to allocate real mode memory!\n"); + exit(1); + } + + /* Copy the real mode code */ + memcpy(p,realModeCode,sizeof(realModeCode)); + + /* Now call the real mode code */ + regs.x.ax = 1; + regs.x.bx = 2; + regs.x.cx = 3; + regs.x.dx = 4; + regs.x.si = 5; + regs.x.di = 6; + sregs.es = 7; + sregs.ds = 8; + PM_callRealMode(r_seg,r_off,®s,&sregs); + if (regs.x.ax != 2 || regs.x.bx != 1 || regs.x.cx != 4 || regs.x.dx != 3 + || regs.x.si != 5 || regs.x.di != 6 || sregs.es != 7 + || sregs.ds != 8) { + printf("Real mode call failed!\n"); + printf("\n"); + printf("ax = %04X, bx = %04X, cx = %04X, dx = %04X\n", + regs.x.ax,regs.x.bx,regs.x.cx,regs.x.dx); + printf("si = %04X, di = %04X, es = %04X, ds = %04X\n", + regs.x.si,regs.x.di,sregs.es,sregs.ds); + } + else + printf("Real mode call succeeded!\n"); + + /* Free the memory we allocated */ + PM_freeRealSeg(p); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c b/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c new file mode 100644 index 000000000..5933ac9f7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/checks.c @@ -0,0 +1,100 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Main module for building checked builds of products with +* assertions and trace code. +* +****************************************************************************/ + +#include "scitech.h" +#include +#include +#include +#ifdef __WINDOWS__ +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#endif + +#ifdef CHECKED + +/*---------------------------- Global variables ---------------------------*/ + +#define LOGFILE "\\scitech.log" + +void (*_CHK_fail)(int fatal,const char *msg,const char *cond,const char *file,int line) = _CHK_defaultFail; + +/*---------------------------- Implementation -----------------------------*/ + +/**************************************************************************** +DESCRIPTION: +Handles fatal error and warning conditions for checked builds. + +HEADER: +scitech.h + +REMARKS: +This function is called whenever an inline check or warning fails in any +of the SciTech runtime libraries. Warning conditions simply cause the +condition to be logged to the log file and send to the system debugger +under Window. Fatal error conditions do all of the above, and then +terminate the program with a fatal error conditions. + +This handler may be overriden by the user code if necessary to replace it +with a different handler (the MGL for instance overrides this and replaces +it with a handler that does an MGL_exit() before terminating the application +so that it will clean up correctly. +****************************************************************************/ +void _CHK_defaultFail( + int fatal, + const char *msg, + const char *cond, + const char *file, + int line) +{ + char buf[256]; + FILE *log = fopen(LOGFILE, "at+"); + + sprintf(buf,msg,cond,file,line); + if (log) { + fputs(buf,log); + fflush(log); + fclose(log); +#ifdef __WINDOWS__ + OutputDebugStr(buf); +#endif + } + if (fatal) { +#ifdef __WINDOWS__ + MessageBox(NULL, buf,"Fatal Error!",MB_ICONEXCLAMATION); +#else + fputs(buf,stderr); +#endif + exit(-1); + } +} + +#endif /* CHECKED */ diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c b/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c new file mode 100644 index 000000000..30e5dd30d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/cpu.c @@ -0,0 +1,46 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Test program for the CPU detection code. +* +****************************************************************************/ + +#include "ztimer.h" +#include "pmapi.h" +#include +#include + +/*----------------------------- Implementation ----------------------------*/ + +int main(void) +{ + printf("Detecting processor information ..."); + fflush(stdout); + printf("\n\n%s\n", CPU_getProcessorName()); + if (CPU_haveRDTSC()) + printf("\nProcessor supports Read Time Stamp Counter performance timer.\n"); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c b/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c new file mode 100644 index 000000000..60f1251a5 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/critical.c @@ -0,0 +1,70 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* critical error handler. +* +* Functions tested: PM_installAltCriticalHandler() +* PM_restoreCriticalHandler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +int main(void) +{ + FILE *f; + int axcode,dicode; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + PM_installCriticalHandler(); + printf("Critical Error handler installed - trying to read from A: drive...\n"); + f = fopen("a:\bog.bog","rb"); + if (f) fclose(f); + if (PM_criticalError(&axcode,&dicode,1)) { + printf("Critical error occured on INT 21h function %02X!\n", + axcode >> 8); + } + else printf("Critical error was not caught!\n"); + PM_restoreCriticalHandler(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c b/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c new file mode 100644 index 000000000..06c2180ce --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/getch.c @@ -0,0 +1,501 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Test program to test out the cross platform event handling +* library. +* +****************************************************************************/ + +#include +#include +#include +#include "pmapi.h" +#include "event.h" + +/* Translation table for key codes */ + +typedef struct { + int code; + char *name; + } KeyEntry; + +KeyEntry ASCIICodes[] = { + {ASCII_ctrlA ,"ASCII_ctrlA"}, + {ASCII_ctrlB ,"ASCII_ctrlB"}, + {ASCII_ctrlC ,"ASCII_ctrlC"}, + {ASCII_ctrlD ,"ASCII_ctrlD"}, + {ASCII_ctrlE ,"ASCII_ctrlE"}, + {ASCII_ctrlF ,"ASCII_ctrlF"}, + {ASCII_ctrlG ,"ASCII_ctrlG"}, + {ASCII_backspace ,"ASCII_backspace"}, + {ASCII_ctrlH ,"ASCII_ctrlH"}, + {ASCII_tab ,"ASCII_tab"}, + {ASCII_ctrlI ,"ASCII_ctrlI"}, + {ASCII_ctrlJ ,"ASCII_ctrlJ"}, + {ASCII_ctrlK ,"ASCII_ctrlK"}, + {ASCII_ctrlL ,"ASCII_ctrlL"}, + {ASCII_enter ,"ASCII_enter"}, + {ASCII_ctrlM ,"ASCII_ctrlM"}, + {ASCII_ctrlN ,"ASCII_ctrlN"}, + {ASCII_ctrlO ,"ASCII_ctrlO"}, + {ASCII_ctrlP ,"ASCII_ctrlP"}, + {ASCII_ctrlQ ,"ASCII_ctrlQ"}, + {ASCII_ctrlR ,"ASCII_ctrlR"}, + {ASCII_ctrlS ,"ASCII_ctrlS"}, + {ASCII_ctrlT ,"ASCII_ctrlT"}, + {ASCII_ctrlU ,"ASCII_ctrlU"}, + {ASCII_ctrlV ,"ASCII_ctrlV"}, + {ASCII_ctrlW ,"ASCII_ctrlW"}, + {ASCII_ctrlX ,"ASCII_ctrlX"}, + {ASCII_ctrlY ,"ASCII_ctrlY"}, + {ASCII_ctrlZ ,"ASCII_ctrlZ"}, + {ASCII_esc ,"ASCII_esc"}, + {ASCII_space ,"ASCII_space"}, + {ASCII_exclamation ,"ASCII_exclamation"}, + {ASCII_quote ,"ASCII_quote"}, + {ASCII_pound ,"ASCII_pound"}, + {ASCII_dollar ,"ASCII_dollar"}, + {ASCII_percent ,"ASCII_percent"}, + {ASCII_ampersand ,"ASCII_ampersand"}, + {ASCII_apostrophe ,"ASCII_apostrophe"}, + {ASCII_leftBrace ,"ASCII_leftBrace"}, + {ASCII_rightBrace ,"ASCII_rightBrace"}, + {ASCII_times ,"ASCII_times"}, + {ASCII_plus ,"ASCII_plus"}, + {ASCII_comma ,"ASCII_comma"}, + {ASCII_minus ,"ASCII_minus"}, + {ASCII_period ,"ASCII_period"}, + {ASCII_divide ,"ASCII_divide"}, + {ASCII_0 ,"ASCII_0"}, + {ASCII_1 ,"ASCII_1"}, + {ASCII_2 ,"ASCII_2"}, + {ASCII_3 ,"ASCII_3"}, + {ASCII_4 ,"ASCII_4"}, + {ASCII_5 ,"ASCII_5"}, + {ASCII_6 ,"ASCII_6"}, + {ASCII_7 ,"ASCII_7"}, + {ASCII_8 ,"ASCII_8"}, + {ASCII_9 ,"ASCII_9"}, + {ASCII_colon ,"ASCII_colon"}, + {ASCII_semicolon ,"ASCII_semicolon"}, + {ASCII_lessThan ,"ASCII_lessThan"}, + {ASCII_equals ,"ASCII_equals"}, + {ASCII_greaterThan ,"ASCII_greaterThan"}, + {ASCII_question ,"ASCII_question"}, + {ASCII_at ,"ASCII_at"}, + {ASCII_A ,"ASCII_A"}, + {ASCII_B ,"ASCII_B"}, + {ASCII_C ,"ASCII_C"}, + {ASCII_D ,"ASCII_D"}, + {ASCII_E ,"ASCII_E"}, + {ASCII_F ,"ASCII_F"}, + {ASCII_G ,"ASCII_G"}, + {ASCII_H ,"ASCII_H"}, + {ASCII_I ,"ASCII_I"}, + {ASCII_J ,"ASCII_J"}, + {ASCII_K ,"ASCII_K"}, + {ASCII_L ,"ASCII_L"}, + {ASCII_M ,"ASCII_M"}, + {ASCII_N ,"ASCII_N"}, + {ASCII_O ,"ASCII_O"}, + {ASCII_P ,"ASCII_P"}, + {ASCII_Q ,"ASCII_Q"}, + {ASCII_R ,"ASCII_R"}, + {ASCII_S ,"ASCII_S"}, + {ASCII_T ,"ASCII_T"}, + {ASCII_U ,"ASCII_U"}, + {ASCII_V ,"ASCII_V"}, + {ASCII_W ,"ASCII_W"}, + {ASCII_X ,"ASCII_X"}, + {ASCII_Y ,"ASCII_Y"}, + {ASCII_Z ,"ASCII_Z"}, + {ASCII_leftSquareBrace ,"ASCII_leftSquareBrace"}, + {ASCII_backSlash ,"ASCII_backSlash"}, + {ASCII_rightSquareBrace ,"ASCII_rightSquareBrace"}, + {ASCII_caret ,"ASCII_caret"}, + {ASCII_underscore ,"ASCII_underscore"}, + {ASCII_leftApostrophe ,"ASCII_leftApostrophe"}, + {ASCII_a ,"ASCII_a"}, + {ASCII_b ,"ASCII_b"}, + {ASCII_c ,"ASCII_c"}, + {ASCII_d ,"ASCII_d"}, + {ASCII_e ,"ASCII_e"}, + {ASCII_f ,"ASCII_f"}, + {ASCII_g ,"ASCII_g"}, + {ASCII_h ,"ASCII_h"}, + {ASCII_i ,"ASCII_i"}, + {ASCII_j ,"ASCII_j"}, + {ASCII_k ,"ASCII_k"}, + {ASCII_l ,"ASCII_l"}, + {ASCII_m ,"ASCII_m"}, + {ASCII_n ,"ASCII_n"}, + {ASCII_o ,"ASCII_o"}, + {ASCII_p ,"ASCII_p"}, + {ASCII_q ,"ASCII_q"}, + {ASCII_r ,"ASCII_r"}, + {ASCII_s ,"ASCII_s"}, + {ASCII_t ,"ASCII_t"}, + {ASCII_u ,"ASCII_u"}, + {ASCII_v ,"ASCII_v"}, + {ASCII_w ,"ASCII_w"}, + {ASCII_x ,"ASCII_x"}, + {ASCII_y ,"ASCII_y"}, + {ASCII_z ,"ASCII_z"}, + {ASCII_leftCurlyBrace ,"ASCII_leftCurlyBrace"}, + {ASCII_verticalBar ,"ASCII_verticalBar"}, + {ASCII_rightCurlyBrace ,"ASCII_rightCurlyBrace"}, + {ASCII_tilde ,"ASCII_tilde"}, + {0 ,"ASCII_unknown"}, + }; + +KeyEntry ScanCodes[] = { + {KB_padEnter ,"KB_padEnter"}, + {KB_padMinus ,"KB_padMinus"}, + {KB_padPlus ,"KB_padPlus"}, + {KB_padTimes ,"KB_padTimes"}, + {KB_padDivide ,"KB_padDivide"}, + {KB_padLeft ,"KB_padLeft"}, + {KB_padRight ,"KB_padRight"}, + {KB_padUp ,"KB_padUp"}, + {KB_padDown ,"KB_padDown"}, + {KB_padInsert ,"KB_padInsert"}, + {KB_padDelete ,"KB_padDelete"}, + {KB_padHome ,"KB_padHome"}, + {KB_padEnd ,"KB_padEnd"}, + {KB_padPageUp ,"KB_padPageUp"}, + {KB_padPageDown ,"KB_padPageDown"}, + {KB_padCenter ,"KB_padCenter"}, + {KB_F1 ,"KB_F1"}, + {KB_F2 ,"KB_F2"}, + {KB_F3 ,"KB_F3"}, + {KB_F4 ,"KB_F4"}, + {KB_F5 ,"KB_F5"}, + {KB_F6 ,"KB_F6"}, + {KB_F7 ,"KB_F7"}, + {KB_F8 ,"KB_F8"}, + {KB_F9 ,"KB_F9"}, + {KB_F10 ,"KB_F10"}, + {KB_F11 ,"KB_F11"}, + {KB_F12 ,"KB_F12"}, + {KB_left ,"KB_left"}, + {KB_right ,"KB_right"}, + {KB_up ,"KB_up"}, + {KB_down ,"KB_down"}, + {KB_insert ,"KB_insert"}, + {KB_delete ,"KB_delete"}, + {KB_home ,"KB_home"}, + {KB_end ,"KB_end"}, + {KB_pageUp ,"KB_pageUp"}, + {KB_pageDown ,"KB_pageDown"}, + {KB_capsLock ,"KB_capsLock"}, + {KB_numLock ,"KB_numLock"}, + {KB_scrollLock ,"KB_scrollLock"}, + {KB_leftShift ,"KB_leftShift"}, + {KB_rightShift ,"KB_rightShift"}, + {KB_leftCtrl ,"KB_leftCtrl"}, + {KB_rightCtrl ,"KB_rightCtrl"}, + {KB_leftAlt ,"KB_leftAlt"}, + {KB_rightAlt ,"KB_rightAlt"}, + {KB_leftWindows ,"KB_leftWindows"}, + {KB_rightWindows ,"KB_rightWindows"}, + {KB_menu ,"KB_menu"}, + {KB_sysReq ,"KB_sysReq"}, + {KB_esc ,"KB_esc"}, + {KB_1 ,"KB_1"}, + {KB_2 ,"KB_2"}, + {KB_3 ,"KB_3"}, + {KB_4 ,"KB_4"}, + {KB_5 ,"KB_5"}, + {KB_6 ,"KB_6"}, + {KB_7 ,"KB_7"}, + {KB_8 ,"KB_8"}, + {KB_9 ,"KB_9"}, + {KB_0 ,"KB_0"}, + {KB_minus ,"KB_minus"}, + {KB_equals ,"KB_equals"}, + {KB_backSlash ,"KB_backSlash"}, + {KB_backspace ,"KB_backspace"}, + {KB_tab ,"KB_tab"}, + {KB_Q ,"KB_Q"}, + {KB_W ,"KB_W"}, + {KB_E ,"KB_E"}, + {KB_R ,"KB_R"}, + {KB_T ,"KB_T"}, + {KB_Y ,"KB_Y"}, + {KB_U ,"KB_U"}, + {KB_I ,"KB_I"}, + {KB_O ,"KB_O"}, + {KB_P ,"KB_P"}, + {KB_leftSquareBrace ,"KB_leftSquareBrace"}, + {KB_rightSquareBrace ,"KB_rightSquareBrace"}, + {KB_enter ,"KB_enter"}, + {KB_A ,"KB_A"}, + {KB_S ,"KB_S"}, + {KB_D ,"KB_D"}, + {KB_F ,"KB_F"}, + {KB_G ,"KB_G"}, + {KB_H ,"KB_H"}, + {KB_J ,"KB_J"}, + {KB_K ,"KB_K"}, + {KB_L ,"KB_L"}, + {KB_semicolon ,"KB_semicolon"}, + {KB_apostrophe ,"KB_apostrophe"}, + {KB_Z ,"KB_Z"}, + {KB_X ,"KB_X"}, + {KB_C ,"KB_C"}, + {KB_V ,"KB_V"}, + {KB_B ,"KB_B"}, + {KB_N ,"KB_N"}, + {KB_M ,"KB_M"}, + {KB_comma ,"KB_comma"}, + {KB_period ,"KB_period"}, + {KB_divide ,"KB_divide"}, + {KB_space ,"KB_space"}, + {KB_tilde ,"KB_tilde"}, + {0 ,"KB_unknown"}, + }; + +/**************************************************************************** +PARAMETERS: +x - X coordinate of the mouse cursor position (screen coordinates) +y - Y coordinate of the mouse cursor position (screen coordinates) + +REMARKS: +This gets called periodically to move the mouse. It will get called when +the mouse may not have actually moved, so check if it has before redrawing +it. +****************************************************************************/ +void EVTAPI moveMouse( + int x, + int y) +{ +} + +/**************************************************************************** +PARAMETERS: +code - Code to translate +keys - Table of translation key values to look up + +REMARKS: +Simple function to look up the printable name for the keyboard code. +****************************************************************************/ +KeyEntry *FindKey( + int code, + KeyEntry *keys) +{ + KeyEntry *key; + + for (key = keys; key->code != 0; key++) { + if (key->code == code) + break; + } + return key; +} + +/**************************************************************************** +PARAMETERS: +evt - Event to display modifiers for + +REMARKS: +Function to display shift modifiers flags +****************************************************************************/ +void DisplayModifiers( + event_t *evt) +{ + if (evt->modifiers & EVT_LEFTBUT) + printf(", LBUT"); + if (evt->modifiers & EVT_RIGHTBUT) + printf(", RBUT"); + if (evt->modifiers & EVT_MIDDLEBUT) + printf(", MBUT"); + if (evt->modifiers & EVT_SHIFTKEY) { + if (evt->modifiers & EVT_LEFTSHIFT) + printf(", LSHIFT"); + if (evt->modifiers & EVT_RIGHTSHIFT) + printf(", RSHIFT"); + } + if (evt->modifiers & EVT_CTRLSTATE) { + if (evt->modifiers & EVT_LEFTCTRL) + printf(", LCTRL"); + if (evt->modifiers & EVT_RIGHTCTRL) + printf(", RCTRL"); + } + if (evt->modifiers & EVT_ALTSTATE) { + if (evt->modifiers & EVT_LEFTALT) + printf(", LALT"); + if (evt->modifiers & EVT_RIGHTALT) + printf(", RALT"); + } +} + +/**************************************************************************** +PARAMETERS: +msg - Message to display for type of event +evt - Event to display + +REMARKS: +Function to display the status of the keyboard event to the screen. +****************************************************************************/ +void DisplayKey( + char *msg, + event_t *evt) +{ + KeyEntry *ascii,*scan; + char ch = EVT_asciiCode(evt->message); + + ascii = FindKey(ch,ASCIICodes); + scan = FindKey(EVT_scanCode(evt->message),ScanCodes); + printf("%s: 0x%04X -> %s, %s, '%c'", + msg, (int)evt->message & 0xFFFF, scan->name, ascii->name, isprint(ch) ? ch : ' '); + DisplayModifiers(evt); + printf("\n"); +} + +/**************************************************************************** +PARAMETERS: +msg - Message to display for type of event +evt - Event to display + +REMARKS: +Function to display the status of the mouse event to the screen. +****************************************************************************/ +void DisplayMouse( + char *msg, + event_t *evt) +{ + printf("%s: ", msg); + if (evt->message & EVT_LEFTBMASK) + printf("LEFT "); + if (evt->message & EVT_RIGHTBMASK) + printf("RIGHT "); + if (evt->message & EVT_MIDDLEBMASK) + printf("MIDDLE "); + printf("abs(%d,%d), rel(%d,%d)", evt->where_x, evt->where_y, evt->relative_x, evt->relative_y); + DisplayModifiers(evt); + if (evt->message & EVT_DBLCLICK) + printf(", DBLCLICK"); + printf("\n"); +} + +/**************************************************************************** +PARAMETERS: +msg - Message to display for type of event +evt - Event to display + +REMARKS: +Function to display the status of the joystick event to the screen. +****************************************************************************/ +void DisplayJoy( + char *msg, + event_t *evt) +{ + printf("%s: Joy1(%4d,%4d,%c%c), Joy2(%4d,%4d,%c%c)\n", msg, + evt->where_x,evt->where_y, + (evt->message & EVT_JOY1_BUTTONA) ? 'A' : 'a', + (evt->message & EVT_JOY1_BUTTONB) ? 'B' : 'b', + evt->relative_x,evt->relative_y, + (evt->message & EVT_JOY2_BUTTONA) ? 'A' : 'a', + (evt->message & EVT_JOY2_BUTTONB) ? 'B' : 'b'); +} + +/**************************************************************************** +REMARKS: +Joystick calibration routine +****************************************************************************/ +void CalibrateJoy(void) +{ + event_t evt; + if(EVT_joyIsPresent()){ + printf("Joystick Calibration\nMove the joystick to the upper left corner and press any button.\n"); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_joySetUpperLeft(); + printf("Move the joystick to the lower right corner and press any button.\n"); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_joySetLowerRight(); + printf("Move the joystick to center position and press any button.\n"); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_halt(&evt, EVT_JOYCLICK); + EVT_joySetCenter(); + printf("Joystick calibrated\n"); + } +} + +/**************************************************************************** +REMARKS: +Main program entry point +****************************************************************************/ +int main(void) +{ + event_t evt; + ibool done = false; + PM_HWND hwndConsole; + + hwndConsole = PM_openConsole(0,0,0,0,0,true); + EVT_init(&moveMouse); + EVT_setMouseRange(1024,768); + CalibrateJoy(); + do { + EVT_pollJoystick(); + if (EVT_getNext(&evt,EVT_EVERYEVT)) { + switch (evt.what) { + case EVT_KEYDOWN: + DisplayKey("EVT_KEYDOWN ", &evt); + if (EVT_scanCode(evt.message) == KB_esc) + done = true; + break; + case EVT_KEYREPEAT: + DisplayKey("EVT_KEYREPEAT", &evt); + break; + case EVT_KEYUP: + DisplayKey("EVT_KEYUP ", &evt); + break; + case EVT_MOUSEDOWN: + DisplayMouse("EVT_MOUSEDOWN", &evt); + break; + case EVT_MOUSEAUTO: + DisplayMouse("EVT_MOUSEAUTO", &evt); + break; + case EVT_MOUSEUP: + DisplayMouse("EVT_MOUSEUP ", &evt); + break; + case EVT_MOUSEMOVE: + DisplayMouse("EVT_MOUSEMOVE", &evt); + break; + case EVT_JOYCLICK: + DisplayJoy("EVT_JOYCLICK ", &evt); + break; + case EVT_JOYMOVE: + DisplayJoy("EVT_JOYMOVE ", &evt); + break; + } + } + } while (!done); + EVT_exit(); + PM_closeConsole(hwndConsole); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c b/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c new file mode 100644 index 000000000..67ad2456e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/isvesa.c @@ -0,0 +1,110 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to allocate real mode +* memory and to call real mode interrupt handlers such as +* the VESA VBE BIOS from protected mode. Compile and link +* with the appropriate command line for your DOS extender. +* +* Functions tested: PM_getVESABuf() +* PM_mapRealPointer() +* PM_int86x() +* +****************************************************************************/ + +#include +#include +#include +#include "pmapi.h" + +/* SuperVGA information block */ + +#pragma pack(1) + +typedef struct { + char VESASignature[4]; /* 'VESA' 4 byte signature */ + short VESAVersion; /* VBE version number */ + ulong OEMStringPtr; /* Far pointer to OEM string */ + ulong Capabilities; /* Capabilities of video card */ + ulong VideoModePtr; /* Far pointer to supported modes */ + short TotalMemory; /* Number of 64kb memory blocks */ + char reserved[236]; /* Pad to 256 byte block size */ + } VgaInfoBlock; + +#pragma pack() + +int main(void) +{ + RMREGS regs; + RMSREGS sregs; + VgaInfoBlock vgaInfo; + ushort *mode; + uint vgLen; + uchar *vgPtr; + unsigned r_vgseg,r_vgoff; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Allocate a 256 byte block of real memory for communicating with + * the VESA BIOS. + */ + if ((vgPtr = PM_getVESABuf(&vgLen,&r_vgseg,&r_vgoff)) == NULL) { + printf("Unable to allocate VESA memory buffer!\n"); + exit(1); + } + + /* Call the VESA VBE to see if it is out there */ + regs.x.ax = 0x4F00; + regs.x.di = r_vgoff; + sregs.es = r_vgseg; + memcpy(vgPtr,"VBE2",4); + PM_int86x(0x10, ®s, ®s, &sregs); + memcpy(&vgaInfo,vgPtr,sizeof(VgaInfoBlock)); + if (regs.x.ax == 0x4F && strncmp(vgaInfo.VESASignature,"VESA",4) == 0) { + printf("VESA VBE version %d.%d BIOS detected\n\n", + vgaInfo.VESAVersion >> 8, vgaInfo.VESAVersion & 0xF); + printf("Available video modes:\n"); + mode = PM_mapRealPointer(vgaInfo.VideoModePtr >> 16, vgaInfo.VideoModePtr & 0xFFFF); + while (*mode != 0xFFFF) { + printf(" %04hXh (%08X)\n", *mode, (int)mode); + mode++; + } + } + else + printf("VESA VBE not found\n"); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/key.c b/board/MAI/bios_emulator/scitech/src/pm/tests/key.c new file mode 100644 index 000000000..dba88853c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/key.c @@ -0,0 +1,92 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* keyboard interrupt handler. +* +* Functions tested: PM_setKeyHandler() +* PM_chainPrevKey() +* PM_restoreKeyHandler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile long count = 0; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +void PMAPI keyHandler(void) +{ + count++; + PM_chainPrevKey(); /* Chain to previous handler */ +} + +int main(void) +{ + int ch; + PM_lockHandle lh; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Install our timer handler and lock handler pages in memory. It is + * difficult to get the size of a function in C, but we know our + * function is well less than 100 bytes (and an entire 4k page will + * need to be locked by the server anyway). + */ + PM_lockCodePages((__codePtr)keyHandler,100,&lh); + PM_lockDataPages((void*)&count,sizeof(count),&lh); + PM_installBreakHandler(); /* We *DONT* want Ctrl-Breaks! */ + PM_setKeyHandler(keyHandler); + printf("Keyboard interrupt handler installed - Type some characters and\n"); + printf("hit ESC to exit\n"); + while ((ch = PM_getch()) != 0x1B) { + printf("%c", ch); + fflush(stdout); + } + + PM_restoreKeyHandler(); + PM_restoreBreakHandler(); + PM_unlockDataPages((void*)&count,sizeof(count),&lh); + PM_unlockCodePages((__codePtr)keyHandler,100,&lh); + printf("\n\nKeyboard handler was called %ld times\n", count); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c b/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c new file mode 100644 index 000000000..b0b94be9c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/key15.c @@ -0,0 +1,96 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* keyboard Int 15h interrupt handler. This is an alternate +* way to intercept scancodes from the keyboard by hooking +* the Int 15h keyboard intercept callout. +* +* Functions tested: PM_setKey15Handler() +* PM_restoreKey15Handler() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile long count = 0; +volatile short lastScanCode = 0; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +short PMAPI keyHandler(short scanCode) +{ + count++; + lastScanCode = scanCode; + return scanCode; /* Let BIOS process as normal */ +} + +int main(void) +{ + int ch; + PM_lockHandle lh; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Install our timer handler and lock handler pages in memory. It is + * difficult to get the size of a function in C, but we know our + * function is well less than 100 bytes (and an entire 4k page will + * need to be locked by the server anyway). + */ + PM_lockCodePages((__codePtr)keyHandler,100,&lh); + PM_lockDataPages((void*)&count,sizeof(count),&lh); + PM_installBreakHandler(); /* We *DONT* want Ctrl-Break's! */ + PM_setKey15Handler(keyHandler); + printf("Keyboard interrupt handler installed - Type some characters and\n"); + printf("hit ESC to exit\n"); + while ((ch = PM_getch()) != 0x1B) { + printf("%c", ch); + fflush(stdout); + } + + PM_restoreKey15Handler(); + PM_restoreBreakHandler(); + PM_unlockDataPages((void*)&count,sizeof(count),&lh); + PM_unlockCodePages((__codePtr)keyHandler,100,&lh); + printf("\n\nKeyboard handler was called %ld times\n", count); + printf("Last scan code %04X\n", lastScanCode); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c b/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c new file mode 100644 index 000000000..a2c655b4a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/memtest.c @@ -0,0 +1,106 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to determine just how much memory can be +* allocated with the compiler in use. Compile and link +* with the appropriate command line for your DOS extender. +* +* Functions tested: PM_malloc() +* PM_availableMemory() +* +* +****************************************************************************/ + +#include +#include +#include +#include +#include "pmapi.h" + +#ifdef __16BIT__ +#define MAXALLOC 64 +#else +#define MAXALLOC 2000 +#endif + +int main(void) +{ + int i; + ulong allocs; + ulong physical,total; + char *p,*pa[MAXALLOC]; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + printf("Memory available at start:\n"); + PM_availableMemory(&physical,&total); + printf(" Physical memory: %ld Kb\n", physical / 1024); + printf(" Total (including virtual): %ld Kb\n", total / 1024); + printf("\n"); + for (allocs = i = 0; i < MAXALLOC; i++) { + if ((pa[i] = PM_malloc(10*1024)) != 0) { /* in 10k blocks */ + p = pa[allocs]; + memset(p, 0, 10*1024); /* touch every byte */ + *p = 'x'; /* do something, anything with */ + p[1023] = 'y'; /* the allocated memory */ + allocs++; + printf("Allocated %lu bytes\r", 10*(allocs << 10)); + } + else break; + if (PM_kbhit() && (PM_getch() == 0x1B)) + break; + } + + printf("\n\nAllocated total of %lu bytes\n", 10 * (allocs << 10)); + + printf("\nMemory available at end:\n"); + PM_availableMemory(&physical,&total); + printf(" Physical memory: %ld Kb\n", physical / 1024); + printf(" Total (including virtual): %ld Kb\n", total / 1024); + + for (i = allocs-1; i >= 0; i--) + PM_free(pa[i]); + + printf("\nMemory available after freeing all blocks (note that under protected mode\n"); + printf("this will most likely not be correct after freeing blocks):\n\n"); + PM_availableMemory(&physical,&total); + printf(" Physical memory: %ld Kb\n", physical / 1024); + printf(" Total (including virtual): %ld Kb\n", total / 1024); + + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c b/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c new file mode 100644 index 000000000..2765a0d1c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/mouse.c @@ -0,0 +1,109 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install an assembly +* language mouse interrupt handler. We use assembly language +* as it must be a far function and should swap to a local +* 32 bit stack if it is going to call any C based code (which +* we do in this example). +* +* Functions tested: PM_installMouseHandler() +* PM_int86() +* +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile long count = 0; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +void PMAPI mouseHandler( + uint mask, + uint butstate, + int x, + int y, + int mickeyX, + int mickeyY) +{ + mask = mask; /* We dont use any of the parameters */ + butstate = butstate; + x = x; + y = y; + mickeyX = mickeyX; + mickeyY = mickeyY; + count++; +} + +int main(void) +{ + RMREGS regs; + PM_lockHandle lh; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + regs.x.ax = 33; /* Mouse function 33 - Software reset */ + PM_int86(0x33,®s,®s); + if (regs.x.bx == 0) { + printf("No mouse installed.\n"); + exit(1); + } + + /* Install our mouse handler and lock handler pages in memory. It is + * difficult to get the size of a function in C, but we know our + * function is well less than 100 bytes (and an entire 4k page will + * need to be locked by the server anyway). + */ + PM_lockCodePages((__codePtr)mouseHandler,100,&lh); + PM_lockDataPages((void*)&count,sizeof(count),&lh); + if (!PM_setMouseHandler(0xFFFF, mouseHandler)) { + printf("Unable to install mouse handler!\n"); + exit(1); + } + printf("Mouse handler installed - Hit any key to exit\n"); + PM_getch(); + + PM_restoreMouseHandler(); + PM_unlockDataPages((void*)&count,sizeof(count),&lh); + PM_unlockCodePages((__codePtr)mouseHandler,100,&lh); + printf("Mouse handler was called %ld times\n", count); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c b/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c new file mode 100644 index 000000000..e00be750e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/restore.c @@ -0,0 +1,81 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux/QNX +* +* Description: Program to restore the console state state from a previously +* saved state if the program crashed while the console +* was in graphics mode. +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +void setVideoMode(int mode) +{ + RMREGS r; + + r.x.ax = mode; + PM_int86(0x10, &r, &r); +} + +int main(void) +{ + PM_HWND hwndConsole; + ulong stateSize; + void *stateBuf; + FILE *f; + + /* Write the saved console state buffer to disk */ + if ((f = fopen("/etc/pmsave.dat","rb")) == NULL) { + printf("Unable to open /etc/pmsave.dat for reading!\n"); + return -1; + } + fread(&stateSize,1,sizeof(stateSize),f); + if (stateSize != PM_getConsoleStateSize()) { + printf("Size mismatch in /etc/pmsave.dat!\n"); + return -1; + } + if ((stateBuf = PM_malloc(stateSize)) == NULL) { + printf("Unable to allocate console state buffer!\n"); + return -1; + } + fread(stateBuf,1,stateSize,f); + fclose(f); + + /* Open the console */ + hwndConsole = PM_openConsole(0,0,0,0,0,true); + + /* Forcibly set 80x25 text mode using the BIOS */ + setVideoMode(0x3); + + /* Restore the previous console state */ + PM_restoreConsoleState(stateBuf,0); + PM_closeConsole(hwndConsole); + PM_free(stateBuf); + printf("Console state successfully restored from /etc/pmsave.dat\n"); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c new file mode 100644 index 000000000..acef9226a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/rtc.c @@ -0,0 +1,92 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* Real Time Clock interrupt handler. +* +* Functions tested: PM_setRealTimeClockHandler() +* PM_restoreRealTimeClockHandler() +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile long count = 0; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +void PMAPI RTCHandler(void) +{ + count++; +} + +int main(void) +{ + long oldCount; + PM_lockHandle lh; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Install our timer handler and lock handler pages in memory. It is + * difficult to get the size of a function in C, but we know our + * function is well less than 100 bytes (and an entire 4k page will + * need to be locked by the server anyway). + */ + PM_lockCodePages((__codePtr)RTCHandler,100,&lh); + PM_lockDataPages((void*)&count,sizeof(count),&lh); + PM_installBreakHandler(); /* We *DONT* want Ctrl-Breaks! */ + PM_setRealTimeClockHandler(RTCHandler,128); + printf("RealTimeClock interrupt handler installed - Hit ESC to exit\n"); + oldCount = count; + while (1) { + if (PM_kbhit() && (PM_getch() == 0x1B)) + break; + if (count != oldCount) { + printf("Tick, Tock: %ld\n", count); + oldCount = count; + } + } + + PM_restoreRealTimeClockHandler(); + PM_restoreBreakHandler(); + PM_unlockDataPages((void*)&count,sizeof(count),&lh); + PM_unlockCodePages((__codePtr)RTCHandler,100,&lh); + printf("RealTimeClock handler was called %ld times\n", count); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/save.c b/board/MAI/bios_emulator/scitech/src/pm/tests/save.c new file mode 100644 index 000000000..f7324562f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/save.c @@ -0,0 +1,69 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Linux/QNX +* +* Description: Program to save the console state state so that it can +* be later restored if the program crashed while the console +* was in graphics mode. +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +int main(void) +{ + PM_HWND hwndConsole; + ulong stateSize; + void *stateBuf; + FILE *f; + + /* Allocate a buffer to save console state and save the state */ + hwndConsole = PM_openConsole(0,0,0,0,0,true); + stateSize = PM_getConsoleStateSize(); + if ((stateBuf = PM_malloc(stateSize)) == NULL) { + PM_closeConsole(hwndConsole); + printf("Unable to allocate console state buffer!\n"); + return -1; + } + PM_saveConsoleState(stateBuf,0); + + /* Restore the console state on exit */ + PM_restoreConsoleState(stateBuf,0); + PM_closeConsole(hwndConsole); + + /* Write the saved console state buffer to disk */ + if ((f = fopen("/etc/pmsave.dat","wb")) == NULL) + printf("Unable to open /etc/pmsave/dat for writing!\n"); + else { + fwrite(&stateSize,1,sizeof(stateSize),f); + fwrite(stateBuf,1,stateSize,f); + fclose(f); + printf("Console state successfully saved to /etc/pmsave.dat\n"); + } + PM_free(stateBuf); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c b/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c new file mode 100644 index 000000000..be275e1a0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/showpci.c @@ -0,0 +1,253 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to test the PCI library functions. +* +****************************************************************************/ + +#include "pmapi.h" +#include "pcilib.h" +#include +#include +#include +#include + +/*------------------------- Global Variables ------------------------------*/ + +static int NumPCI = -1; +static PCIDeviceInfo *PCI; +static int *BridgeIndex; +static int *DeviceIndex; +static int NumBridges; +static PCIDeviceInfo *AGPBridge = NULL; +static int NumDevices; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +REMARKS: +Enumerates the PCI bus and dumps the PCI configuration information to the +log file. +****************************************************************************/ +static void EnumeratePCI(void) +{ + int i,index; + PCIDeviceInfo *info; + + printf("Displaying enumeration of PCI bus (%d devices, %d display devices)\n", + NumPCI, NumDevices); + for (index = 0; index < NumDevices; index++) + printf(" Display device %d is PCI device %d\n",index,DeviceIndex[index]); + printf("\n"); + printf("Bus Slot Fnc DeviceID SubSystem Rev Class IRQ Int Cmd\n"); + for (i = 0; i < NumPCI; i++) { + printf("%2d %2d %2d %04X:%04X %04X:%04X %02X %02X:%02X %02X %02X %04X ", + PCI[i].slot.p.Bus, + PCI[i].slot.p.Device, + PCI[i].slot.p.Function, + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].u.type0.SubSystemVendorID, + PCI[i].u.type0.SubSystemID, + PCI[i].RevID, + PCI[i].BaseClass, + PCI[i].SubClass, + PCI[i].u.type0.InterruptLine, + PCI[i].u.type0.InterruptPin, + PCI[i].Command); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printf("<- %d\n", index); + else + printf("\n"); + } + printf("\n"); + printf("DeviceID Stat Ifc Cch Lat Hdr BIST\n"); + for (i = 0; i < NumPCI; i++) { + printf("%04X:%04X %04X %02X %02X %02X %02X %02X ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].Status, + PCI[i].Interface, + PCI[i].CacheLineSize, + PCI[i].LatencyTimer, + PCI[i].HeaderType, + PCI[i].BIST); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printf("<- %d\n", index); + else + printf("\n"); + } + printf("\n"); + printf("DeviceID Base10h Base14h Base18h Base1Ch Base20h Base24h ROMBase\n"); + for (i = 0; i < NumPCI; i++) { + printf("%04X:%04X %08lX %08lX %08lX %08lX %08lX %08lX %08lX ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].u.type0.BaseAddress10, + PCI[i].u.type0.BaseAddress14, + PCI[i].u.type0.BaseAddress18, + PCI[i].u.type0.BaseAddress1C, + PCI[i].u.type0.BaseAddress20, + PCI[i].u.type0.BaseAddress24, + PCI[i].u.type0.ROMBaseAddress); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printf("<- %d\n", index); + else + printf("\n"); + } + printf("\n"); + printf("DeviceID BAR10Len BAR14Len BAR18Len BAR1CLen BAR20Len BAR24Len ROMLen\n"); + for (i = 0; i < NumPCI; i++) { + printf("%04X:%04X %08lX %08lX %08lX %08lX %08lX %08lX %08lX ", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].u.type0.BaseAddress10Len, + PCI[i].u.type0.BaseAddress14Len, + PCI[i].u.type0.BaseAddress18Len, + PCI[i].u.type0.BaseAddress1CLen, + PCI[i].u.type0.BaseAddress20Len, + PCI[i].u.type0.BaseAddress24Len, + PCI[i].u.type0.ROMBaseAddressLen); + for (index = 0; index < NumDevices; index++) { + if (DeviceIndex[index] == i) + break; + } + if (index < NumDevices) + printf("<- %d\n", index); + else + printf("\n"); + } + printf("\n"); + printf("Displaying enumeration of %d bridge devices\n",NumBridges); + printf("\n"); + printf("DeviceID P# S# B# IOB IOL MemBase MemLimit PreBase PreLimit Ctrl\n"); + for (i = 0; i < NumBridges; i++) { + info = (PCIDeviceInfo*)&PCI[BridgeIndex[i]]; + printf("%04X:%04X %02X %02X %02X %04X %04X %08X %08X %08X %08X %04X\n", + info->VendorID, + info->DeviceID, + info->u.type1.PrimaryBusNumber, + info->u.type1.SecondayBusNumber, + info->u.type1.SubordinateBusNumber, + ((u16)info->u.type1.IOBase << 8) & 0xF000, + info->u.type1.IOLimit ? + ((u16)info->u.type1.IOLimit << 8) | 0xFFF : 0, + ((u32)info->u.type1.MemoryBase << 16) & 0xFFF00000, + info->u.type1.MemoryLimit ? + ((u32)info->u.type1.MemoryLimit << 16) | 0xFFFFF : 0, + ((u32)info->u.type1.PrefetchableMemoryBase << 16) & 0xFFF00000, + info->u.type1.PrefetchableMemoryLimit ? + ((u32)info->u.type1.PrefetchableMemoryLimit << 16) | 0xFFFFF : 0, + info->u.type1.BridgeControl); + } + printf("\n"); +} + +/**************************************************************************** +RETURNS: +Number of display devices found. + +REMARKS: +This function enumerates the number of available display devices on the +PCI bus, and returns the number found. +****************************************************************************/ +static int PCI_enumerateDevices(void) +{ + int i,j; + PCIDeviceInfo *info; + + /* If this is the first time we have been called, enumerate all */ + /* devices on the PCI bus. */ + if (NumPCI == -1) { + if ((NumPCI = PCI_getNumDevices()) == 0) + return -1; + PCI = malloc(NumPCI * sizeof(PCI[0])); + BridgeIndex = malloc(NumPCI * sizeof(BridgeIndex[0])); + DeviceIndex = malloc(NumPCI * sizeof(DeviceIndex[0])); + if (!PCI || !BridgeIndex || !DeviceIndex) + return -1; + for (i = 0; i < NumPCI; i++) + PCI[i].dwSize = sizeof(PCI[i]); + if (PCI_enumerate(PCI) == 0) + return -1; + + /* Build a list of all PCI bridge devices */ + for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { + if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) + BridgeIndex[NumBridges++] = i; + } + + /* Now build a list of all display class devices */ + for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { + if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { + if ((PCI[i].Command & 0x3) == 0x3) + DeviceIndex[0] = i; + else + DeviceIndex[NumDevices++] = i; + if (PCI[i].slot.p.Bus != 0) { + /* This device is on a different bus than the primary */ + /* PCI bus, so it is probably an AGP device. Find the */ + /* AGP bus device that controls that bus so we can */ + /* control it. */ + for (j = 0; j < NumBridges; j++) { + info = (PCIDeviceInfo*)&PCI[BridgeIndex[j]]; + if (info->u.type1.SecondayBusNumber == PCI[i].slot.p.Bus) { + AGPBridge = info; + break; + } + } + } + } + } + + /* Enumerate all PCI and bridge devices to standard output */ + EnumeratePCI(); + } + return NumDevices; +} + +int main(void) +{ + /* Enumerate all PCI devices */ + PM_init(); + if (PCI_enumerateDevices() < 1) { + printf("No PCI display devices found!\n"); + return -1; + } + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c b/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c new file mode 100644 index 000000000..378725ebe --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/tick.c @@ -0,0 +1,94 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to install a C based +* timer interrupt handler. +* +* Functions tested: PM_setTimerHandler() +* PM_chainPrevTimer(); +* PM_restoreTimerHandler() +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +volatile long count = 0; + +#pragma off (check_stack) /* No stack checking under Watcom */ + +void PMAPI timerHandler(void) +{ + PM_chainPrevTimer(); /* Chain to previous handler */ + count++; +} + +int main(void) +{ + long oldCount; + PM_lockHandle lh; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + /* Install our timer handler and lock handler pages in memory. It is + * difficult to get the size of a function in C, but we know our + * function is well less than 100 bytes (and an entire 4k page will + * need to be locked by the server anyway). + */ + PM_lockCodePages((__codePtr)timerHandler,100,&lh); + PM_lockDataPages((void*)&count,sizeof(count),&lh); + PM_installBreakHandler(); /* We *DONT* want Ctrl-Breaks! */ + PM_setTimerHandler(timerHandler); + printf("Timer interrupt handler installed - Hit ESC to exit\n"); + oldCount = count; + while (1) { + if (PM_kbhit() && (PM_getch() == 0x1B)) + break; + if (count != oldCount) { + printf("Tick, Tock: %ld\n", count); + oldCount = count; + } + } + + PM_restoreTimerHandler(); + PM_restoreBreakHandler(); + PM_unlockDataPages((void*)&count,sizeof(count),&lh); + PM_unlockCodePages((__codePtr)timerHandler,100,&lh); + printf("Timer handler was called %ld times\n", count); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c new file mode 100644 index 000000000..7fa77b77b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/timerc.c @@ -0,0 +1,87 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Test program for the Zen Timer Library. +* +****************************************************************************/ + +#include +#include "pmapi.h" +#include "ztimer.h" + +#define DELAY_SECS 10 + +/*-------------------------- Implementation -------------------------------*/ + +/* The following routine takes a long count in microseconds and outputs + * a string representing the count in seconds. It could be modified to + * return a pointer to a static string representing the count rather + * than printing it out. + */ + +void ReportTime(ulong count) +{ + ulong secs; + + secs = count / 1000000L; + count = count - secs * 1000000L; + printf("Time taken: %lu.%06lu seconds\n",secs,count); +} + +int i,j; /* NON register variables! */ + +int main(void) +{ +#ifdef LONG_TEST + ulong start,finish; +#endif + + printf("Processor type: %d %ld MHz\n", CPU_getProcessorType(), CPU_getProcessorSpeed(true)); + + ZTimerInit(); + + /* Test the long period Zen Timer (we don't check for overflow coz + * it would take tooooo long!) + */ + + LZTimerOn(); + for (j = 0; j < 10; j++) + for (i = 0; i < 20000; i++) + i = i; + LZTimerOff(); + ReportTime(LZTimerCount()); + + /* Test the ultra long period Zen Timer */ +#ifdef LONG_TEST + start = ULZReadTime(); + delay(DELAY_SECS * 1000); + finish = ULZReadTime(); + printf("Delay of %d secs took %d 1/10ths of a second\n", + DELAY_SECS,ULZElapsedTime(start,finish)); +#endif + + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp b/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp new file mode 100644 index 000000000..1258a4bb1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/timercpp.cpp @@ -0,0 +1,107 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: C++ 3.0 +* Environment: Any +* +* Description: Test program for the Zen Timer Library C++ interface. +* +****************************************************************************/ + +#include +#include "pmapi.h" +#include "ztimer.h" + +/*-------------------------- Implementation -------------------------------*/ + +int i,j,k; /* NON register variables! */ + +void dummy() {} + +int main(void) +{ + LZTimer ltimer; + ULZTimer ultimer; + + ZTimerInit(); + + /* Test the long period Zen Timer (we don't check for overflow coz + * it would take tooooo long!) + */ + + cout << endl; + ultimer.restart(); + ltimer.start(); + for (j = 0; j < 10; j++) + for (i = 0; i < 20000; i++) + dummy(); + ltimer.stop(); + ultimer.stop(); + cout << "LCount: " << ltimer.count() << endl; + cout << "Time: " << ltimer << " secs\n"; + cout << "ULCount: " << ultimer.count() << endl; + cout << "ULTime: " << ultimer << " secs\n"; + + cout << endl << "Timing ... \n"; + ultimer.restart(); + ltimer.restart(); + for (j = 0; j < 200; j++) + for (i = 0; i < 20000; i++) + dummy(); + ltimer.stop(); + ultimer.stop(); + cout << "LCount: " << ltimer.count() << endl; + cout << "Time: " << ltimer << " secs\n"; + cout << "ULCount: " << ultimer.count() << endl; + cout << "ULTime: " << ultimer << " secs\n"; + + /* Test the lap function of the long period Zen Timer */ + + cout << endl << "Timing ... \n"; + ultimer.restart(); + ltimer.restart(); + for (j = 0; j < 20; j++) { + for (k = 0; k < 10; k++) + for (i = 0; i < 20000; i++) + dummy(); + cout << "lap: " << ltimer.lap() << endl; + } + ltimer.stop(); + ultimer.stop(); + cout << "LCount: " << ltimer.count() << endl; + cout << "Time: " << ltimer << " secs\n"; + cout << "ULCount: " << ultimer.count() << endl; + cout << "ULTime: " << ultimer << " secs\n"; + +#ifdef LONG_TEST + /* Test the ultra long period Zen Timer */ + + ultimer.start(); + delay(DELAY_SECS * 1000); + ultimer.stop(); + cout << "Delay of " << DELAY_SECS << " secs took " << ultimer.count() + << " 1/10ths of a second\n"; + cout << "Time: " << ultimer << " secs\n"; +#endif + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c b/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c new file mode 100644 index 000000000..f0c7bd631 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/uswc.c @@ -0,0 +1,311 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Simple test program to test the write combine functions. +* +* Note that this program should never be used in a production +* environment, because write combining needs to be handled +* with more intimate knowledge of the display hardware than +* you can obtain by simply examining the PCI configuration +* space. +* +****************************************************************************/ + +#include "pmapi.h" +#include "pcilib.h" +#include +#include +#include +#include + +/*------------------------- Global Variables ------------------------------*/ + +static int NumPCI = -1; +static PCIDeviceInfo *PCI; +static int *BridgeIndex; +static int *DeviceIndex; +static int NumBridges; +static PCIDeviceInfo *AGPBridge = NULL; +static int NumDevices; + +/*-------------------------- Implementation -------------------------------*/ + +/**************************************************************************** +RETURNS: +Number of display devices found. + +REMARKS: +This function enumerates the number of available display devices on the +PCI bus, and returns the number found. +****************************************************************************/ +static int PCI_enumerateDevices(void) +{ + int i,j; + PCIDeviceInfo *info; + + /* If this is the first time we have been called, enumerate all */ + /* devices on the PCI bus. */ + if (NumPCI == -1) { + if ((NumPCI = PCI_getNumDevices()) == 0) + return -1; + PCI = malloc(NumPCI * sizeof(PCI[0])); + BridgeIndex = malloc(NumPCI * sizeof(BridgeIndex[0])); + DeviceIndex = malloc(NumPCI * sizeof(DeviceIndex[0])); + if (!PCI || !BridgeIndex || !DeviceIndex) + return -1; + for (i = 0; i < NumPCI; i++) + PCI[i].dwSize = sizeof(PCI[i]); + if (PCI_enumerate(PCI) == 0) + return -1; + + /* Build a list of all PCI bridge devices */ + for (i = 0,NumBridges = 0,BridgeIndex[0] = -1; i < NumPCI; i++) { + if (PCI[i].BaseClass == PCI_BRIDGE_CLASS) + BridgeIndex[NumBridges++] = i; + } + + /* Now build a list of all display class devices */ + for (i = 0,NumDevices = 1,DeviceIndex[0] = -1; i < NumPCI; i++) { + if (PCI_IS_DISPLAY_CLASS(&PCI[i])) { + if ((PCI[i].Command & 0x3) == 0x3) + DeviceIndex[0] = i; + else + DeviceIndex[NumDevices++] = i; + if (PCI[i].slot.p.Bus != 0) { + /* This device is on a different bus than the primary */ + /* PCI bus, so it is probably an AGP device. Find the */ + /* AGP bus device that controls that bus so we can */ + /* control it. */ + for (j = 0; j < NumBridges; j++) { + info = (PCIDeviceInfo*)&PCI[BridgeIndex[j]]; + if (info->u.type1.SecondayBusNumber == PCI[i].slot.p.Bus) { + AGPBridge = info; + break; + } + } + } + } + } + } + return NumDevices; +} + +/**************************************************************************** +REMARKS: +Enumerates useful information about attached display devices. +****************************************************************************/ +static void ShowDisplayDevices(void) +{ + int i,index; + + printf("Displaying enumeration of %d PCI display devices\n", NumDevices); + printf("\n"); + printf("DeviceID SubSystem Base10h (length ) Base14h (length )\n"); + for (index = 0; index < NumDevices; index++) { + i = DeviceIndex[index]; + printf("%04X:%04X %04X:%04X %08lX (%6ld KB) %08lX (%6ld KB)\n", + PCI[i].VendorID, + PCI[i].DeviceID, + PCI[i].u.type0.SubSystemVendorID, + PCI[i].u.type0.SubSystemID, + PCI[i].u.type0.BaseAddress10, + PCI[i].u.type0.BaseAddress10Len / 1024, + PCI[i].u.type0.BaseAddress14, + PCI[i].u.type0.BaseAddress14Len / 1024); + } + printf("\n"); +} + +/**************************************************************************** +REMARKS: +Dumps the value for a write combine region to the display. +****************************************************************************/ +static char *DecodeWCType( + uint type) +{ + static char *names[] = { + "UNCACHABLE", + "WRCOMB", + "UNKNOWN", + "UNKNOWN", + "WRTHROUGH", + "WRPROT", + "WRBACK", + }; + if (type <= PM_MTRR_MAX) + return names[type]; + return "UNKNOWN"; +} + +/**************************************************************************** +REMARKS: +Dumps the value for a write combine region to the display. +****************************************************************************/ +static void PMAPI EnumWriteCombine( + ulong base, + ulong length, + uint type) +{ + printf("%08lX %-10ld %s\n", base, length / 1024, DecodeWCType(type)); +} + +/**************************************************************************** +PARAMETERS: +err - Error to log + +REMARKS: +Function to log an error message if the MTRR write combining attempt failed. +****************************************************************************/ +static void LogMTRRError( + int err) +{ + if (err == PM_MTRR_ERR_OK) + return; + switch (err) { + case PM_MTRR_NOT_SUPPORTED: + printf("Failed: MTRR is not supported by host CPU\n"); + break; + case PM_MTRR_ERR_PARAMS: + printf("Failed: Invalid parameters passed to PM_enableWriteCombined!\n"); + break; + case PM_MTRR_ERR_NOT_4KB_ALIGNED: + printf("Failed: Address is not 4Kb aligned!\n"); + break; + case PM_MTRR_ERR_BELOW_1MB: + printf("Failed: Addresses below 1Mb cannot be write combined!\n"); + break; + case PM_MTRR_ERR_NOT_ALIGNED: + printf("Failed: Address is not correctly aligned for processor!\n"); + break; + case PM_MTRR_ERR_OVERLAP: + printf("Failed: Address overlaps an existing region!\n"); + break; + case PM_MTRR_ERR_TYPE_MISMATCH: + printf("Failed: Adress is contained with existing region, but type is different!\n"); + break; + case PM_MTRR_ERR_NONE_FREE: + printf("Failed: Out of MTRR registers!\n"); + break; + case PM_MTRR_ERR_NOWRCOMB: + printf("Failed: This processor does not support write combining!\n"); + break; + case PM_MTRR_ERR_NO_OS_SUPPORT: + printf("Failed: MTRR is not supported by host OS\n"); + break; + default: + printf("Failed: UNKNOWN ERROR!\n"); + break; + } + exit(-1); +} + +/**************************************************************************** +REMARKS: +Shows all write combine regions. +****************************************************************************/ +static void ShowWriteCombine(void) +{ + printf("Base Length(KB) Type\n"); + LogMTRRError(PM_enumWriteCombine(EnumWriteCombine)); + printf("\n"); +} + +/**************************************************************************** +REMARKS: +Dumps the value for a write combine region to the display. +****************************************************************************/ +static void EnableWriteCombine(void) +{ + int i,index; + + for (index = 0; index < NumDevices; index++) { + i = DeviceIndex[index]; + if (PCI[i].u.type0.BaseAddress10 & 0x8) { + LogMTRRError(PM_enableWriteCombine( + PCI[i].u.type0.BaseAddress10 & 0xFFFFFFF0, + PCI[i].u.type0.BaseAddress10Len, + PM_MTRR_WRCOMB)); + } + if (PCI[i].u.type0.BaseAddress14 & 0x8) { + LogMTRRError(PM_enableWriteCombine( + PCI[i].u.type0.BaseAddress14 & 0xFFFFFFF0, + PCI[i].u.type0.BaseAddress14Len, + PM_MTRR_WRCOMB)); + } + } + printf("\n"); + ShowDisplayDevices(); + ShowWriteCombine(); +} + +/**************************************************************************** +REMARKS: +Dumps the value for a write combine region to the display. +****************************************************************************/ +static void DisableWriteCombine(void) +{ + int i,index; + + for (index = 0; index < NumDevices; index++) { + i = DeviceIndex[index]; + if (PCI[i].u.type0.BaseAddress10 & 0x8) { + LogMTRRError(PM_enableWriteCombine( + PCI[i].u.type0.BaseAddress10 & 0xFFFFFFF0, + PCI[i].u.type0.BaseAddress10Len, + PM_MTRR_UNCACHABLE)); + } + if (PCI[i].u.type0.BaseAddress14 & 0x8) { + LogMTRRError(PM_enableWriteCombine( + PCI[i].u.type0.BaseAddress14 & 0xFFFFFFF0, + PCI[i].u.type0.BaseAddress14Len, + PM_MTRR_UNCACHABLE)); + } + } + printf("\n"); + ShowDisplayDevices(); + ShowWriteCombine(); +} + +int main(int argc,char *argv[]) +{ + PM_init(); + if (PCI_enumerateDevices() < 1) { + printf("No PCI display devices found!\n"); + return -1; + } + if (argc < 2) { + printf("usage: uswc [-show -on -off]\n\n"); + ShowDisplayDevices(); + return -1; + } + if (stricmp(argv[1],"-show") == 0) + ShowWriteCombine(); + else if (stricmp(argv[1],"-on") == 0) + EnableWriteCombine(); + else if (stricmp(argv[1],"-off") == 0) + DisableWriteCombine(); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c b/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c new file mode 100644 index 000000000..b7e3bb784 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/vftest.c @@ -0,0 +1,78 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Filename: $Workfile$ +* Version: $Revision: 1.1 $ +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to test the VFlat virtual framebuffer functions. +* +* Functions tested: VF_available() +* VF_init() +* VF_exit() +* +* $Date: 2002/10/02 15:35:21 $ $Author: hfrieden $ +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +uchar code[] = { + 0xC3, /* ret */ + }; + +int main(void) +{ + void *vfBuffer; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + if (!VF_available()) { + printf("Virtual Linear Framebuffer not available.\n"); + exit(1); + } + + vfBuffer = VF_init(0xA0000,64,sizeof(code),code); + if (!vfBuffer) { + printf("Failure to initialise Virtual Linear Framebuffer!\n"); + exit(1); + } + VF_exit(); + printf("Virtual Linear Framebuffer set up successfully!\n"); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/tests/video.c b/board/MAI/bios_emulator/scitech/src/pm/tests/video.c new file mode 100644 index 000000000..92adcddd4 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/tests/video.c @@ -0,0 +1,199 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: any +* +* Description: Test program to check the ability to generate real mode +* interrupts and to be able to obtain direct access to the +* video memory from protected mode. Compile and link with +* the appropriate command line for your DOS extender. +* +* Functions tested: PM_getBIOSSelector() +* PM_mapPhysicalAddr() +* PM_int86() +* +****************************************************************************/ + +#include +#include +#include "pmapi.h" + +uchar *bios; /* Pointer to BIOS data area */ +uchar *videoPtr; /* Pointer to VGA framebuffer */ +void *stateBuf; /* Console state save buffer */ + +/* Routine to return the current video mode number */ + +int getVideoMode(void) +{ + return PM_getByte(bios+0x49); +} + +/* Routine to set a specified video mode */ + +void setVideoMode(int mode) +{ + RMREGS r; + + r.x.ax = mode; + PM_int86(0x10, &r, &r); +} + +/* Routine to clear a rectangular region on the display by calling the + * video BIOS. + */ + +void clearScreen(int startx, int starty, int endx, int endy, unsigned char attr) +{ + RMREGS r; + + r.x.ax = 0x0600; + r.h.bh = attr; + r.h.cl = startx; + r.h.ch = starty; + r.h.dl = endx; + r.h.dh = endy; + PM_int86(0x10, &r, &r); +} + +/* Routine to fill a rectangular region on the display using direct + * video writes. + */ + +#define SCREEN(x,y) (videoPtr + ((y) * 160) + ((x) << 1)) + +void fill(int startx, int starty, int endx, int endy, unsigned char c, + unsigned char attr) +{ + unsigned char *v; + int x,y; + + for (y = starty; y <= endy; y++) { + v = SCREEN(startx,y); + for (x = startx; x <= endx; x++) { + *v++ = c; + *v++ = attr; + } + } +} + +/* Routine to display a single character using direct video writes */ + +void writeChar(int x, int y, unsigned char c, unsigned char attr) +{ + unsigned char *v = SCREEN(x,y); + *v++ = c; + *v = attr; +} + +/* Routine to draw a border around a rectangular area using direct video + * writes. + */ + +static unsigned char border_chars[] = { + 186, 205, 201, 187, 200, 188 /* double box chars */ + }; + +void border(int startx, int starty, int endx, int endy, unsigned char attr) +{ + unsigned char *v; + unsigned char *b; + int i; + + b = border_chars; + + for (i = starty+1; i < endy; i++) { + writeChar(startx, i, *b, attr); + writeChar(endx, i, *b, attr); + } + b++; + for (i = startx+1, v = SCREEN(startx+1, starty); i < endx; i++) { + *v++ = *b; + *v++ = attr; + } + for (i = startx+1, v = SCREEN(startx+1, endy); i < endx; i++) { + *v++ = *b; + *v++ = attr; + } + b++; + writeChar(startx, starty, *b++, attr); + writeChar(endx, starty, *b++, attr); + writeChar(startx, endy, *b++, attr); + writeChar(endx, endy, *b++, attr); +} + +int main(void) +{ + int orgMode; + PM_HWND hwndConsole; + + printf("Program running in "); + switch (PM_getModeType()) { + case PM_realMode: + printf("real mode.\n\n"); + break; + case PM_286: + printf("16 bit protected mode.\n\n"); + break; + case PM_386: + printf("32 bit protected mode.\n\n"); + break; + } + + hwndConsole = PM_openConsole(0,0,0,0,0,true); + printf("Hit any key to start 80x25 text mode and perform some direct video output.\n"); + PM_getch(); + + /* Allocate a buffer to save console state and save the state */ + if ((stateBuf = PM_malloc(PM_getConsoleStateSize())) == NULL) { + printf("Unable to allocate console state buffer!\n"); + exit(1); + } + PM_saveConsoleState(stateBuf,0); + bios = PM_getBIOSPointer(); + orgMode = getVideoMode(); + setVideoMode(0x3); + if ((videoPtr = PM_mapPhysicalAddr(0xB8000,0xFFFF,true)) == NULL) { + printf("Unable to obtain pointer to framebuffer!\n"); + exit(1); + } + + /* Draw some text on the screen */ + fill(0, 0, 79, 24, 176, 0x1E); + border(0, 0, 79, 24, 0x1F); + PM_getch(); + clearScreen(0, 0, 79, 24, 0x7); + + /* Restore the console state on exit */ + PM_restoreConsoleState(stateBuf,0); + PM_free(stateBuf); + PM_closeConsole(hwndConsole); + + /* Display useful status information */ + printf("\n"); + printf("Original Video Mode = %02X\n", orgMode); + printf("BIOS Pointer = %08X\n", (int)bios); + printf("Video Memory = %08X\n", (int)videoPtr); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c new file mode 100644 index 000000000..3460b7245 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/cpuinfo.c @@ -0,0 +1,66 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 VDD +* +* Description: VDD specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Do nothing for VDD's +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +Do nothing for VDD's +****************************************************************************/ +#define RestoreThreadPriority(i) (void)(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + freq->low = 100000; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + ULONG count; \ + count = VDHQuerySysValue(0, VDHGSV_MSECSBOOT); \ + (t)->low = count * 100; \ + (t)->high = 0; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c new file mode 100644 index 000000000..93742de91 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/fileio.c @@ -0,0 +1,359 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 VDD +* +* Description: C library compatible I/O functions for use within a VDD. +* +****************************************************************************/ + +#include "pmapi.h" +#include "vddfile.h" + +/*------------------------ Main Code Implementation -----------------------*/ + +#define EOF -1 + +/* NB: none of the file VDHs are available during the DOS session */ +/* initialzation context! */ + +/* Macros for Open/Close APIs to allow using this module in both VDDs and */ +/* normal OS/2 applications. Unfortunately VDHRead/Write/Seek don't map to */ +/* their Dos* counterparts so cleanly. */ +#ifdef __OS2_VDD__ +#define _OS2Open VDHOpen +#define _OS2Close VDHClose +#else +#define _OS2Open DosOpen +#define _OS2Close DosClose +#endif + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C fopen function. +****************************************************************************/ +FILE * fopen( + const char *filename, + const char *mode) +{ + FILE *f = PM_malloc(sizeof(FILE)); + long oldpos; + ULONG rc, ulAction; + ULONG omode, oflags; + + if (f != NULL) { + f->offset = 0; + f->text = (mode[1] == 't' || mode[2] == 't'); + f->writemode = (mode[0] == 'w') || (mode[0] == 'a'); + f->unputc = EOF; + f->endp = f->buf + sizeof(f->buf); + f->curp = f->startp = f->buf; + + if (mode[0] == 'r') { + #ifdef __OS2_VDD__ + omode = VDHOPEN_ACCESS_READONLY | VDHOPEN_SHARE_DENYNONE; + oflags = VDHOPEN_ACTION_OPEN_IF_EXISTS | VDHOPEN_ACTION_FAIL_IF_NEW; + #else + omode = OPEN_ACCESS_READONLY | OPEN_SHARE_DENYNONE; + oflags = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_FAIL_IF_NEW; + #endif + } + else if (mode[0] == 'w') { + #ifdef __OS2_VDD__ + omode = VDHOPEN_ACCESS_WRITEONLY | VDHOPEN_SHARE_DENYWRITE; + oflags = VDHOPEN_ACTION_REPLACE_IF_EXISTS | VDHOPEN_ACTION_CREATE_IF_NEW; + #else + omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_DENYWRITE; + oflags = OPEN_ACTION_REPLACE_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; + #endif + } + else { + #ifdef __OS2_VDD__ + omode = VDHOPEN_ACCESS_READWRITE | VDHOPEN_SHARE_DENYWRITE; + oflags = VDHOPEN_ACTION_OPEN_IF_EXISTS | VDHOPEN_ACTION_CREATE_IF_NEW; + #else + omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_DENYWRITE; + oflags = OPEN_ACTION_OPEN_IF_EXISTS | OPEN_ACTION_CREATE_IF_NEW; + #endif + } + rc = _OS2Open((PSZ)filename, (PHFILE)&f->handle, &ulAction, 0, VDHOPEN_FILE_NORMAL, oflags, omode, NULL); + if (rc != 0) { + PM_free(f); + return NULL; + } + + #ifdef __OS2_VDD__ + f->filesize = VDHSeek((HFILE)f->handle, 0, VDHSK_END_OF_FILE); + #else + rc = DosSetFilePtr((HFILE)f->handle, 0, FILE_END, &f->filesize); + #endif + + if (mode[0] == 'a') + fseek(f,0,2); + } + return f; +} + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C fread function. Note that unlike Windows VxDs, +OS/2 VDDs are not limited to 64K reads or writes. +****************************************************************************/ +size_t fread( + void *ptr, + size_t size, + size_t n, + FILE *f) +{ + char *buf = ptr; + int bytes,readbytes,totalbytes = 0; + + /* First copy any data already read into our buffer */ + if ((bytes = (f->curp - f->startp)) > 0) { + memcpy(buf,f->curp,bytes); + f->startp = f->curp = f->buf; + buf += bytes; + totalbytes += bytes; + bytes = (size * n) - bytes; + } + else + bytes = size * n; + if (bytes) { + #ifdef __OS2_VDD__ + readbytes = VDHRead((HFILE)f->handle, buf, bytes); + #else + DosRead((HFILE)f->handle, buf, bytes, &readbytes); + #endif + totalbytes += readbytes; + f->offset += readbytes; + } + return totalbytes / size; +} + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C fwrite function. +****************************************************************************/ +size_t fwrite( + void *ptr, + size_t size, + size_t n, + FILE *f) +{ + char *buf = ptr; + int bytes,writtenbytes,totalbytes = 0; + + /* Flush anything already in the buffer */ + if (!f->writemode) + return 0; + fflush(f); + bytes = size * n; + #ifdef __OS2_VDD__ + writtenbytes = VDHWrite((HFILE)f->handle, buf, bytes); + #else + DosWrite((HFILE)f->handle, buf, bytes, &writtenbytes); + #endif + totalbytes += writtenbytes; + f->offset += writtenbytes; + if (f->offset > f->filesize) + f->filesize = f->offset; + return totalbytes / size; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fflush function. +****************************************************************************/ +int fflush( + FILE *f) +{ + ULONG bytes; + + /* First copy any data already written into our buffer */ + if (f->writemode && (bytes = (f->curp - f->startp)) > 0) { + #ifdef __OS2_VDD__ + bytes = VDHWrite((HFILE)f->handle, f->startp, bytes); + #else + DosWrite((HFILE)f->handle, f->startp, bytes, &bytes); + #endif + f->offset += bytes; + if (f->offset > f->filesize) + f->filesize = f->offset; + f->startp = f->curp = f->buf; + } + return 0; +} + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C fseek function. +****************************************************************************/ +int fseek( + FILE *f, + long int offset, + int whence) +{ + fflush(f); + + if (whence == 0) + f->offset = offset; + else if (whence == 1) + f->offset += offset; + else if (whence == 2) + f->offset = f->filesize + offset; + + #ifdef __OS2_VDD__ + VDHSeek((HFILE)f->handle, f->offset, VDHSK_ABSOLUTE); + #else + DosSetFilePtr((HFILE)f->handle, f->offset, FILE_BEGIN, NULL); + #endif + + return 0; +} + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C ftell function. +****************************************************************************/ +long ftell( + FILE *f) +{ + long offset; + + offset = (f->curp - f->startp); + offset += f->offset; + return offset; +} + +/**************************************************************************** +REMARKS: +VDD implementation of the ANSI C feof function. +****************************************************************************/ +int feof( + FILE *f) +{ + return (f->offset == f->filesize); +} + +/**************************************************************************** +REMARKS: +Read a single character from the input file buffer, including translation +of the character in text transation modes. +****************************************************************************/ +static int __getc( + FILE *f) +{ + int c; + + if (f->unputc != EOF) { + c = f->unputc; + f->unputc = EOF; + } + else { + if (f->startp == f->curp) { + int bytes = fread(f->buf,1,sizeof(f->buf),f); + if (bytes == 0) + return EOF; + f->curp = f->startp + bytes; + } + c = *f->startp++; + if (f->text && c == '\r') { + int nc = __getc(f); + if (nc != '\n') + f->unputc = nc; + } + } + return c; +} + +/**************************************************************************** +REMARKS: +Write a single character from to input buffer, including translation of the +character in text transation modes. +****************************************************************************/ +static int __putc(int c,FILE *f) +{ + int count = 1; + if (f->text && c == '\n') { + __putc('\r',f); + count = 2; + } + if (f->curp == f->endp) + fflush(f); + *f->curp++ = c; + return count; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fgets function. +****************************************************************************/ +char *fgets( + char *s, + int n, + FILE *f) +{ + int c = 0; + char *cs; + + cs = s; + while (--n > 0 && (c = __getc(f)) != EOF) { + *cs++ = c; + if (c == '\n') + break; + } + if (c == EOF && cs == s) + return NULL; + *cs = '\0'; + return s; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fputs function. +****************************************************************************/ +int fputs( + const char *s, + FILE *f) +{ + int r = 0; + int c; + + while ((c = *s++) != 0) + r = __putc(c, f); + return r; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fclose function. +****************************************************************************/ +int fclose( + FILE *f) +{ + fflush(f); + _OS2Close((HFILE)f->handle); + PM_free(f); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h new file mode 100644 index 000000000..03286bdc2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/oshdr.h @@ -0,0 +1,29 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 VDD +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c new file mode 100644 index 000000000..6688babd0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/pm.c @@ -0,0 +1,1050 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 VDD +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" + +#define TRACE(a) + +/*--------------------------- Global variables ----------------------------*/ + +#define MAX_MEMORY_SHARED 100 +#define MAX_MEMORY_MAPPINGS 100 + +/* TODO: I think the global and linear members will be the same, but not sure yet. */ +typedef struct { + void *linear; + ulong global; + ulong length; + int npages; + } memshared; + +typedef struct { + ulong physical; + ulong linear; + ulong length; + int npages; + ibool isCached; + } mmapping; + +static int numMappings = 0; +static memshared shared[MAX_MEMORY_MAPPINGS] = {0}; +static mmapping maps[MAX_MEMORY_MAPPINGS]; +ibool _PM_haveBIOS = TRUE; +char _PM_cntPath[PM_MAX_PATH] = ""; /* there just isn't any */ +uchar *_PM_rmBufAddr = NULL; +ushort _VARAPI PM_savedDS = 0; /* why can't I use the underscore prefix? */ + +HVDHSEM hevFarCallRet = NULL; +HVDHSEM hevIRet = NULL; +HHOOK hhookUserReturnHook = NULL; +HHOOK hhookUserIRetHook = NULL; + +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +/* Functions to read and write CMOS registers */ + +ulong PMAPI _PM_getPDB(void); +uchar PMAPI _PM_readCMOS(int index); +void PMAPI _PM_writeCMOS(int index,uchar value); + +VOID HOOKENTRY UserReturnHook(PVOID pRefData, PCRF pcrf); +VOID HOOKENTRY UserIRetHook(PVOID pRefData, PCRF pcrf); + +void PMAPI PM_init(void) +{ + MTRR_init(); + + /* Initialize VDD-specific data */ + /* Note: PM_init must be (obviously) called in VDM task context! */ + VDHCreateSem(&hevFarCallRet, VDH_EVENTSEM); + VDHCreateSem(&hevIRet, VDH_EVENTSEM); + hhookUserReturnHook = VDHAllocHook(VDH_RETURN_HOOK, (PFNARM)UserReturnHook, 0); + hhookUserIRetHook = VDHAllocHook(VDH_RETURN_HOOK, (PFNARM)UserIRetHook, 0); + + if ((hevIRet == NULL) || (hevFarCallRet == NULL) || + (hhookUserReturnHook == NULL) || (hhookUserIRetHook == NULL)) { + /* something failed, we can't go on */ + /* TODO: take some action here! */ + } +} + +/* Do some cleaning up */ +void PMAPI PM_exit(void) +{ + /* Note: Hooks allocated during or after VDM creation are deallocated automatically */ + if (hevIRet != NULL) + VDHDestroySem(hevIRet); + + if (hevFarCallRet != NULL) + VDHDestroySem(hevFarCallRet); +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return _PM_haveBIOS; } + +long PMAPI PM_getOSType(void) +{ return /*_OS_OS2VDD*/ _OS_OS2; } /*FIX!! */ + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); +/* Fatal_Error_Handler(msg,0); TODO: implement somehow! */ +} + +/**************************************************************************** +PARAMETERS: +len - Place to store the length of the buffer +rseg - Place to store the real mode segment of the buffer +roff - Place to store the real mode offset of the buffer + +REMARKS: +This function returns the address and length of the global VESA transfer +buffer. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + if (_PM_rmBufAddr) { + *len = 0; /*VESA_BUF_SIZE; */ + *rseg = (ulong)(_PM_rmBufAddr) >> 4; + *roff = (ulong)(_PM_rmBufAddr) & 0xF; + return _PM_rmBufAddr; + } + return NULL; +} + +int PMAPI PM_int386(int intno, PMREGS *in, PMREGS *out) +{ + /* Unused in VDDs */ + return 0; +} + +char * PMAPI PM_getCurrentPath(char *path,int maxLen) +{ + strncpy(path, _PM_cntPath, maxLen); + path[maxLen - 1] = 0; + return path; +} + +char PMAPI PM_getBootDrive(void) +{ + ulong boot = 3; + boot = VDHQuerySysValue(0, VDHGSV_BOOTDRV); + return (char)('a' + boot - 1); +} + +const char * PMAPI PM_getVBEAFPath(void) +{ + static char path[CCHMAXPATH]; + strcpy(path,"x:\\"); + path[0] = PM_getBootDrive(); + return path; +} + +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[CCHMAXPATH]; + strcpy(path,"x:\\os2\\drivers"); + path[0] = PM_getBootDrive(); + PM_backslash(path); + strcat(path,"nucleus"); + return path; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ return PM_getMachineName(); } + +const char * PMAPI PM_getMachineName(void) +{ + return "Unknown"; +} + +int PMAPI PM_kbhit(void) +{ return 1; } + +int PMAPI PM_getch(void) +{ return 0; } + +PM_HWND PMAPI PM_openConsole(PM_HWND hwndUser,int device,int xRes,int yRes,int bpp,ibool fullScreen) +{ + /* Unused in VDDs */ + return NULL; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + /* Unused in VDDs */ + return 1; +} + +void PMAPI PM_saveConsoleState(void *stateBuf,PM_HWND hwndConsole) +{ + /* Unused in VDDs */ +} + +void PMAPI PM_setSuspendAppCallback(int (_ASMAPIP saveState)(int flags)) +{ + /* Unused in VDDs */ +} + +void PMAPI PM_restoreConsoleState(const void *stateBuf,PM_HWND hwndConsole) +{ + /* Unused in VDDs */ +} + +void PMAPI PM_closeConsole(PM_HWND hwndConsole) +{ + /* Unused in VDDs */ +} + +void PMAPI PM_setOSCursorLocation(int x,int y) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x50,x); + PM_setByte(_biosPtr+0x51,y); +} + +void PMAPI PM_setOSScreenWidth(int width,int height) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x4A,width); + PM_setByte(_biosPtr+0x84,height-1); +} + +/**************************************************************************** +REMARKS: +Allocate a block of shared memory. For OS/2 VDD we allocate shared memory +as locked, global memory that is accessible from any memory context +(including interrupt time context), which allows us to load our important +data structure and code such that we can access it directly from a ring +0 interrupt context. +****************************************************************************/ +void * PMAPI PM_mallocShared(long size) +{ + ULONG nPages = (size + 0xFFF) >> 12; + int i; + + /* First find a free slot in our shared memory table */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].linear == 0) + break; + } + if (i < MAX_MEMORY_SHARED) { + shared[i].linear = VDHAllocPages(NULL, nPages, VDHAP_SYSTEM | VDHAP_FIXED); + shared[i].npages = nPages; + shared[i].global = (ULONG)shared[i].linear; + return (void*)shared[i].global; + } + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory +****************************************************************************/ +void PMAPI PM_freeShared(void *p) +{ + int i; + + /* Find a shared memory block in our table and free it */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].global == (ulong)p) { + VDHFreePages(shared[i].linear); + shared[i].linear = 0; + break; + } + } +} + +void * PMAPI PM_mapToProcess(void *base,ulong limit) +{ return (void*)base; } + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + /* TODO: Figure out how to do this */ + return false; +} + +void * PMAPI PM_getBIOSPointer(void) +{ return (void*)0x400; } + +void * PMAPI PM_getA0000Pointer(void) +{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); } + +/**************************************************************************** +PARAMETERS: +base - Physical base address of the memory to maps in +limit - Limit of physical memory to region to maps in + +RETURNS: +Linear address of the newly mapped memory. + +REMARKS: +Maps a physical memory range to a linear memory range. +****************************************************************************/ +ulong MapPhysicalToLinear( + ulong base, + ulong limit, + int *npages) +{ + ulong linear,length = limit+1; + int i,ppage,flags; +#if 0 + ppage = base >> 12; + *npages = (length + (base & 0xFFF) + 4095) >> 12; + flags = PR_FIXED | PR_STATIC; + if (base == 0xA0000) { + /* We require the linear address to be aligned to a 64Kb boundary + * for mapping the banked framebuffer (so we can do efficient + * carry checking for bank changes in the assembler code). The only + * way to ensure this is to force the linear address to be aligned + * to a 4Mb boundary. + */ + flags |= PR_4MEG; + } + if ((linear = (ulong)PageReserve(PR_SYSTEM,*npages,flags)) == (ulong)-1) + return 0; + if (!PageCommitPhys(linear >> 12,*npages,ppage,PC_INCR | PC_USER | PC_WRITEABLE)) + return 0; +#endif + return linear + (base & 0xFFF); +} + +/**************************************************************************** +PARAMETERS: +base - Physical base address of the memory to map in +limit - Limit of physical memory to region to map in +isCached - True if the memory should be cached, false if not + +RETURNS: +Linear address of the newly mapped memory. + +REMARKS: +This function maps physical memory to linear memory, which can then be used +to create a selector or used directly from 32-bit protected mode programs. +This is better than DPMI 0x800, since it allows you to maps physical +memory below 1Mb, which gets this memory out of the way of the Windows VxD's +sticky paws. + +NOTE: If the memory is not expected to be cached, this function will + directly re-program the PCD (Page Cache Disable) bit in the + page tables. There does not appear to be a mechanism in the VMM + to control this bit via the regular interface. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + ulong linear,length = limit+1; + int i,npages; + ulong PDB,*pPDB; + + /* Search table of existing mappings to see if we have already mapped + * a region of memory that will serve this purpose. + */ + for (i = 0; i < numMappings; i++) { + if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached) + return (void*)maps[i].linear; + } + if (numMappings == MAX_MEMORY_MAPPINGS) + return NULL; + + /* We did not find any previously mapped memory region, so map it in. + * Note that we do not use MapPhysToLinear, since this function appears + * to have problems mapping memory in the 1Mb physical address space. + * Hence we use PageReserve and PageCommitPhys. + */ + if ((linear = MapPhysicalToLinear(base,limit,&npages)) == 0) + return NULL; + maps[numMappings].physical = base; + maps[numMappings].length = length; + maps[numMappings].linear = linear; + maps[numMappings].npages = npages; + maps[numMappings].isCached = isCached; + numMappings++; + +#if 0 + /* Finally disable caching where necessary */ + if (!isCached && (PDB = _PM_getPDB()) != 0) { + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong pageTable,*pPageTable; + + if (PDB >= 0x100000) + pPDB = (ulong*)MapPhysicalToLinear(PDB,0xFFF,&npages); + else + pPDB = (ulong*)PDB; + if (pPDB) { + startPDB = (linear >> 22) & 0x3FF; + startPage = (linear >> 12) & 0x3FF; + endPDB = ((linear+limit) >> 22) & 0x3FF; + endPage = ((linear+limit) >> 12) & 0x3FF; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + pageTable = pPDB[iPDB] & ~0xFFF; + if (pageTable >= 0x100000) + pPageTable = (ulong*)MapPhysicalToLinear(pageTable,0xFFF,&npages); + else + pPageTable = (ulong*)pageTable; + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FF; + for (iPage = start; iPage <= end; iPage++) + pPageTable[iPage] |= 0x10; + PageFree((ulong)pPageTable,PR_STATIC); + } + PageFree((ulong)pPDB,PR_STATIC); + } + } +#endif + return (void*)linear; +} + +void PMAPI PM_freePhysicalAddr(void *ptr,ulong limit) +{ + /* We never free the mappings */ +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* We never sleep in a VDD */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +ulong PMAPI PM_getPhysicalAddr(void *p) +{ + /* TODO: This function should find the physical address of a linear */ + /* address. */ + return 0xFFFFFFFFUL; +} + +void PMAPI _PM_freeMemoryMappings(void) +{ + int i; +/* for (i = 0; i < numMappings; i++) */ +/* PageFree(maps[i].linear,PR_STATIC); */ +} + +void * PMAPI PM_mapRealPointer(uint r_seg,uint r_off) +{ return (void*)MK_PHYS(r_seg,r_off); } + +void * PMAPI PM_allocRealSeg(uint size,uint *r_seg,uint *r_off) +{ return NULL; } + +void PMAPI PM_freeRealSeg(void *mem) +{ } + +void PMAPI DPMI_int86(int intno, DPMI_regs *regs) +{ + /* Unsed in VDDs */ +} + +/**************************************************************************** +REMARKS: +Load the V86 registers in the client state, and save the original state +before loading the registers. +****************************************************************************/ +static void LoadV86Registers( + PCRF saveRegs, + RMREGS *in, + RMSREGS *sregs) +{ + PCRF pcrf; /* current client register frame */ + + /* get pointer to registers */ + pcrf = (PCRF)VDHQuerySysValue(CURRENT_VDM, VDHLSV_PCRF); + + /* Note: We could do VDHPushRegs instead but this should be safer as it */ + /* doesn't rely on the VDM session having enough free stack space. */ + *saveRegs = *pcrf; /* save all registers */ + + pcrf->crf_eax = in->e.eax; /* load new values */ + pcrf->crf_ebx = in->e.ebx; + pcrf->crf_ecx = in->e.ecx; + pcrf->crf_edx = in->e.edx; + pcrf->crf_esi = in->e.esi; + pcrf->crf_edi = in->e.edi; + pcrf->crf_es = sregs->es; + pcrf->crf_ds = sregs->ds; + +} + +/**************************************************************************** +REMARKS: +Read the V86 registers from the client state and restore the original state. +****************************************************************************/ +static void ReadV86Registers( + PCRF saveRegs, + RMREGS *out, + RMSREGS *sregs) +{ + PCRF pcrf; /* current client register frame */ + + /* get pointer to registers */ + pcrf = (PCRF)VDHQuerySysValue(CURRENT_VDM, VDHLSV_PCRF); + + /* read new register values */ + out->e.eax = pcrf->crf_eax; + out->e.ebx = pcrf->crf_ebx; + out->e.ecx = pcrf->crf_ecx; + out->e.edx = pcrf->crf_edx; + out->e.esi = pcrf->crf_esi; + out->e.edi = pcrf->crf_edi; + sregs->es = pcrf->crf_es; + sregs->ds = pcrf->crf_ds; + + /* restore original client registers */ + *pcrf = *saveRegs; +} + +/**************************************************************************** +REMARKS: Used for far calls into V86 code +****************************************************************************/ +VOID HOOKENTRY UserReturnHook( + PVOID pRefData, + PCRF pcrf ) +{ + VDHPostEventSem(hevFarCallRet); +} + +/**************************************************************************** +REMARKS: Used for calling BIOS interrupts +****************************************************************************/ +VOID HOOKENTRY UserIRetHook( + PVOID pRefData, + PCRF pcrf ) +{ + VDHPostEventSem(hevIRet); +} + +/**************************************************************************** +REMARKS: +Call a V86 real mode function with the specified register values +loaded before the call. The call returns with a far ret. +Must be called from within a DOS session context! +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *regs, + RMSREGS *sregs) +{ + CRF saveRegs; + FPFN fnAddress; + ULONG rc; + + TRACE("SDDHELP: Entering PM_callRealMode()\n"); + LoadV86Registers(SSToDS(&saveRegs),regs,sregs); + + /* set up return hook for call */ + rc = VDHArmReturnHook(hhookUserReturnHook, VDHARH_CSEIP_HOOK); + + VDHResetEventSem(hevFarCallRet); + + /* the address is a 16:32 pointer */ + OFFSETOF32(fnAddress) = off; + SEGMENTOF32(fnAddress) = seg; + rc = VDHPushFarCall(fnAddress); + VDHYield(0); + + /* wait until the V86 call returns - our return hook posts the semaphore */ + rc = VDHWaitEventSem(hevFarCallRet, SEM_INDEFINITE_WAIT); + + ReadV86Registers(SSToDS(&saveRegs),regs,sregs); + TRACE("SDDHELP: Exiting PM_callRealMode()\n"); +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +Must be called from within a DOS session context! +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + RMSREGS sregs = {0}; + CRF saveRegs; + ushort oldDisable; + ULONG rc; + + memset(SSToDS(&sregs), 0, sizeof(sregs)); + +#if 0 /* do we need this?? */ + /* Disable pass-up to our VDD handler so we directly call BIOS */ + TRACE("SDDHELP: Entering PM_int86()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } +#endif + + LoadV86Registers(SSToDS(&saveRegs), in, SSToDS(&sregs)); + + VDHResetEventSem(hevIRet); + rc = VDHPushInt(intno); + + /* set up return hook for interrupt */ + rc = VDHArmReturnHook(hhookUserIRetHook, VDHARH_NORMAL_IRET); + + VDHYield(0); + + /* wait until the V86 IRETs - our return hook posts the semaphore */ + rc = VDHWaitEventSem(hevIRet, 5000); /*SEM_INDEFINITE_WAIT); */ + + ReadV86Registers(SSToDS(&saveRegs), out, SSToDS(&sregs)); + +#if 0 + /* Re-enable pass-up to our VDD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; +#endif + + TRACE("SDDHELP: Exiting PM_int86()\n"); + return out->x.ax; + +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + CRF saveRegs; + ushort oldDisable; + ULONG rc; + +#if 0 + /* Disable pass-up to our VxD handler so we directly call BIOS */ + TRACE("SDDHELP: Entering PM_int86x()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } +#endif + LoadV86Registers(SSToDS(&saveRegs), in, sregs); + + VDHResetEventSem(hevIRet); + rc = VDHPushInt(intno); + + /* set up return hook for interrupt */ + rc = VDHArmReturnHook(hhookUserIRetHook, VDHARH_NORMAL_IRET); + + VDHYield(0); + + /* wait until the V86 IRETs - our return hook posts the semaphore */ + rc = VDHWaitEventSem(hevIRet, 5000); /*SEM_INDEFINITE_WAIT); */ + + ReadV86Registers(SSToDS(&saveRegs), out, sregs); + +#if 0 + /* Re-enable pass-up to our VxD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; +#endif + + TRACE("SDDHELP: Exiting PM_int86x()\n"); + return out->x.ax; +} + +void PMAPI PM_availableMemory(ulong *physical,ulong *total) +{ *physical = *total = 0; } + +/**************************************************************************** +REMARKS: +Allocates a block of locked physical memory. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + ULONG flags = VDHAP_SYSTEM; + ULONG nPages = (size + 0xFFF) >> 12; + + flags |= (physAddr != NULL) ? VDHAP_PHYSICAL : VDHAP_FIXED; + + return VDHAllocPages(physAddr, nPages, VDHAP_SYSTEM | VDHAP_PHYSICAL); +} + +/**************************************************************************** +REMARKS: +Frees a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + if (p) + VDHFreePages((PVOID)p); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + ULONG lockHandle; + + /* TODO: the lock handle is essential for the unlock operation!! */ + lockHandle = VDHLockMem(p, len, 0, (PVOID)VDHLM_NO_ADDR, NULL); + + if (lockHandle != NULL) + return 0; + else + return 1; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + /* TODO: implement - use a table of lock handles? */ + /* VDHUnlockPages(lockHandle); */ + return 0; +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + return PM_lockDataPages((void*)p,len,lh); +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + return PM_unlockDataPages((void*)p,len,lh); +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VDD +****************************************************************************/ +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + (void)szDLLName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VDD +****************************************************************************/ +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + (void)hModule; + (void)szProcName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VDD +****************************************************************************/ +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + /* TODO: This function should start a directory enumeration search */ + /* given the filename (with wildcards). The data should be */ + /* converted and returned in the findData standard form. */ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + /* TODO: This function should find the next file in directory enumeration */ + /* search given the search criteria defined in the call to */ + /* PM_findFirstFile. The data should be converted and returned */ + /* in the findData standard form. */ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + /* TODO: This function should close the find process. This may do */ + /* nothing for some OS'es. */ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + /* Not applicable in a VDD */ + (void)drive; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + /* Not applicable in a VDD */ + (void)drive; + (void)dir; + (void)len; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ + return MTRR_enableWriteCombine(base,size,type); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + /* TODO: Implement this ? */ + (void)filename; + (void)attrib; + PM_fatalError("PM_setFileAttr not implemented!"); +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + /* TODO: Implement this ? */ + (void)filename; + PM_fatalError("PM_getFileAttr not implemented!"); + return 0; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + /* TODO: Implement this ? */ + (void)filename; + PM_fatalError("PM_mkdir not implemented!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + /* TODO: Implement this ? */ + (void)filename; + PM_fatalError("PM_rmdir not implemented!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this ? */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_getFileTime not implemented!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this ? */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_setFileTime not implemented!"); + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c new file mode 100644 index 000000000..21639281a --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/vflat.c @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c new file mode 100644 index 000000000..631f6558e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vdd/ztimer.c @@ -0,0 +1,103 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit OS/2 VDD +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static ulong frequency = 1193180; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +#define __ZTimerInit() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOn(tm) VTD_Get_Real_Time(&tm->start.high,&tm->start.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + CPU_largeInteger lap,count; + VTD_Get_Real_Time(&lap.high,&lap.low); + _CPU_diffTime64(&tm->start,&lap,&count); + return _CPU_calcMicroSec(&count,frequency); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) VTD_Get_Real_Time(&tm->end.high,&tm->end.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,frequency); +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1000 + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the BIOS timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + return VDHQuerySysValue(0, VDHGSV_MSECSBOOT); +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm b/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm new file mode 100644 index 000000000..64a7cecb2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/_pm.asm @@ -0,0 +1,299 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: 32-bit Windows VxD +;* +;* Description: Low level assembly support for the PM library specific to +;* Windows VxDs. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pm ; Set up memory model + +begdataseg _pm + + cextern _PM_savedDS,USHORT + +enddataseg _pm + +P586 + +begcodeseg _pm ; Start of code segment + +;---------------------------------------------------------------------------- +; void PM_segread(PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Read the current value of all segment registers +;---------------------------------------------------------------------------- +cprocstart PM_segread + + ARG sregs:DPTR + + enter_c + + mov ax,es + _les _si,[sregs] + mov [_ES _si],ax + mov [_ES _si+2],cs + mov [_ES _si+4],ss + mov [_ES _si+6],ds + mov [_ES _si+8],fs + mov [_ES _si+10],gs + + leave_c + ret + +cprocend + +;---------------------------------------------------------------------------- +; int PM_int386x(int intno, PMREGS *in, PMREGS *out,PMSREGS *sregs) +;---------------------------------------------------------------------------- +; Issues a software interrupt in protected mode. This routine has been +; written to allow user programs to load CS and DS with different values +; other than the default. +;---------------------------------------------------------------------------- +cprocstart PM_int386x + +; Not used for VxDs + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_saveDS(void) +;---------------------------------------------------------------------------- +; Save the value of DS into a section of the code segment, so that we can +; quickly load this value at a later date in the PM_loadDS() routine from +; inside interrupt handlers etc. The method to do this is different +; depending on the DOS extender being used. +;---------------------------------------------------------------------------- +cprocstart PM_saveDS + + mov [_PM_savedDS],ds ; Store away in data segment + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_loadDS(void) +;---------------------------------------------------------------------------- +; Routine to load the DS register with the default value for the current +; DOS extender. Only the DS register is loaded, not the ES register, so +; if you wish to call C code, you will need to also load the ES register +; in 32 bit protected mode. +;---------------------------------------------------------------------------- +cprocstart PM_loadDS + + mov ds,[cs:_PM_savedDS] ; We can access the proper DS through CS + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankA(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankA + +; Not used for VxDs + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setBankAB(int bank) +;---------------------------------------------------------------------------- +cprocstart PM_setBankAB + +; Not used for VxDs + + ret + +cprocend + +;---------------------------------------------------------------------------- +; void PM_setCRTStart(int x,int y,int waitVRT) +;---------------------------------------------------------------------------- +cprocstart PM_setCRTStart + +; Not used for VxDs + + ret + +cprocend + +; Macro to delay briefly to ensure that enough time has elapsed between +; successive I/O accesses so that the device being accessed can respond +; to both accesses even on a very fast PC. + +ifdef USE_NASM +%macro DELAY 0 + jmp short $+2 + jmp short $+2 + jmp short $+2 +%endmacro +%macro IODELAYN 1 +%rep %1 + DELAY +%endrep +%endmacro +else +macro DELAY + jmp short $+2 + jmp short $+2 + jmp short $+2 +endm +macro IODELAYN N + rept N + DELAY + endm +endm +endif + +;---------------------------------------------------------------------------- +; uchar _PM_readCMOS(int index) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_readCMOS + + ARG index:UINT + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + in al,71h + mov ah,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + mov al,ah ; Return value in AL + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; void _PM_writeCMOS(int index,uchar value) +;---------------------------------------------------------------------------- +; Read the value of a specific CMOS register. We do this with both +; normal interrupts and NMI disabled. +;---------------------------------------------------------------------------- +cprocstart _PM_writeCMOS + + ARG index:UINT, value:UCHAR + + push _bp + mov _bp,_sp + pushfd + mov al,[BYTE index] + or al,80h ; Add disable NMI flag + cli + out 70h,al + IODELAYN 5 + mov al,[value] + out 71h,al + xor al,al + IODELAYN 5 + out 70h,al ; Re-enable NMI + popfd + pop _bp + ret + +cprocend + +;---------------------------------------------------------------------------- +; double _ftol(double f) +;---------------------------------------------------------------------------- +; Calls to __ftol are generated by the Borland C++ compiler for code +; that needs to convert a floating point type to an integral type. +; +; Input: floating point number on the top of the '87. +; +; Output: a (signed or unsigned) long in EAX +; All other registers preserved. +;----------------------------------------------------------------------- +cprocstart _ftol + + LOCAL temp1:WORD, temp2:QWORD = LocalSize + + push ebp + mov ebp,esp + sub esp,LocalSize + + fstcw [temp1] ; save the control word + fwait + mov al,[BYTE temp1+1] + or [BYTE temp1+1],0Ch ; set rounding control to chop + fldcw [temp1] + fistp [temp2] ; convert to 64-bit integer + mov [BYTE temp1+1],al + fldcw [temp1] ; restore the control word + mov eax,[DWORD temp2] ; return LS 32 bits + mov edx,[DWORD temp2+4] ; MS 32 bits + + mov esp,ebp + pop ebp + ret + +cprocend + +;---------------------------------------------------------------------------- +; _PM_getPDB - Return the Page Table Directory Base address +;---------------------------------------------------------------------------- +cprocstart _PM_getPDB + + mov eax,cr3 + and eax,0FFFFF000h + ret + +cprocend + +;---------------------------------------------------------------------------- +; Flush the Translation Lookaside buffer +;---------------------------------------------------------------------------- +cprocstart PM_flushTLB + + wbinvd ; Flush the CPU cache + mov eax,cr3 + mov cr3,eax ; Flush the TLB + ret + +cprocend + +endcodeseg _pm + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c new file mode 100644 index 000000000..3c7eaaeaa --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/cpuinfo.c @@ -0,0 +1,66 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: VxD specific code for the CPU detection module. +* +****************************************************************************/ + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Do nothing for VxD's +****************************************************************************/ +#define SetMaxThreadPriority() 0 + +/**************************************************************************** +REMARKS: +Do nothing for VxD's +****************************************************************************/ +#define RestoreThreadPriority(i) (void)(i) + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + freq->low = 1193180; + freq->high = 0; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + CPU_largeInteger count; \ + VTD_Get_Real_Time(&count.high,&count.low); \ + (t)->low = count.low; \ + (t)->high = count.high; \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c new file mode 100644 index 000000000..3c6ce9920 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/fileio.c @@ -0,0 +1,304 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: C library compatible I/O functions for use within a VxD. +* +****************************************************************************/ + +#include "pmapi.h" +#include "vxdfile.h" + +/*------------------------ Main Code Implementation -----------------------*/ + +#define EOF -1 + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fopen function. +****************************************************************************/ +FILE * fopen( + const char *filename, + const char *mode) +{ + FILE *f = PM_malloc(sizeof(FILE)); + long oldpos; + + if (f) { + f->offset = 0; + f->text = (mode[1] == 't' || mode[2] == 't'); + f->writemode = (mode[0] == 'w') || (mode[0] == 'a'); + if (initComplete) { + WORD omode,error; + BYTE action; + + if (mode[0] == 'r') { + omode = OPEN_ACCESS_READONLY | OPEN_SHARE_COMPATIBLE; + action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_FAIL; + } + else if (mode[0] == 'w') { + omode = OPEN_ACCESS_WRITEONLY | OPEN_SHARE_COMPATIBLE; + action = ACTION_IFEXISTS_TRUNCATE | ACTION_IFNOTEXISTS_CREATE; + } + else { + omode = OPEN_ACCESS_READWRITE | OPEN_SHARE_COMPATIBLE; + action = ACTION_IFEXISTS_OPEN | ACTION_IFNOTEXISTS_CREATE; + } + f->handle = (int)R0_OpenCreateFile(false,(char*)filename,omode,ATTR_NORMAL,action,0,&error,&action); + if (f->handle == 0) { + PM_free(f); + return NULL; + } + f->filesize = R0_GetFileSize((HANDLE)f->handle,&error); + if (mode[0] == 'a') + fseek(f,0,2); + } + else { + int oflag,pmode; + + if (mode[0] == 'r') { + pmode = _S_IREAD; + oflag = _O_RDONLY; + } + else if (mode[0] == 'w') { + pmode = _S_IWRITE; + oflag = _O_WRONLY | _O_CREAT | _O_TRUNC; + } + else { + pmode = _S_IWRITE; + oflag = _O_RDWR | _O_CREAT | _O_APPEND; + } + if (f->text) + oflag |= _O_TEXT; + else + oflag |= _O_BINARY; + if ((f->handle = i_open(filename,oflag,pmode)) == -1) { + PM_free(f); + return NULL; + } + oldpos = i_lseek(f->handle,0,1); + f->filesize = i_lseek(f->handle,0,2); + i_lseek(f->handle,oldpos,0); + } + } + return f; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fread function. Note that the VxD file I/O +functions are layered on DOS, so can only read up to 64K at a time. Since +we are expected to handle much larger chunks than this, we handle larger +blocks automatically in here. +****************************************************************************/ +size_t fread( + void *ptr, + size_t size, + size_t n, + FILE *f) +{ + char *buf = ptr; + WORD error; + int bytes = size * n; + int readbytes,totalbytes = 0; + + while (bytes > 0x10000) { + if (initComplete) { + readbytes = R0_ReadFile(false,(HANDLE)f->handle,buf,0x8000,f->offset,&error); + readbytes += R0_ReadFile(false,(HANDLE)f->handle,buf+0x8000,0x8000,f->offset+0x8000,&error); + } + else { + readbytes = i_read(f->handle,buf,0x8000); + readbytes += i_read(f->handle,buf+0x8000,0x8000); + } + totalbytes += readbytes; + f->offset += readbytes; + buf += 0x10000; + bytes -= 0x10000; + } + if (bytes) { + if (initComplete) + readbytes = R0_ReadFile(false,(HANDLE)f->handle,buf,bytes,f->offset,&error); + else + readbytes = i_read(f->handle,buf,bytes); + totalbytes += readbytes; + f->offset += readbytes; + } + return totalbytes / size; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fwrite function. Note that the VxD file I/O +functions are layered on DOS, so can only read up to 64K at a time. Since +we are expected to handle much larger chunks than this, we handle larger +blocks automatically in here. +****************************************************************************/ +size_t fwrite( + const void *ptr, + size_t size, + size_t n, + FILE *f) +{ + const char *buf = ptr; + WORD error; + int bytes = size * n; + int writtenbytes,totalbytes = 0; + + if (!f->writemode) + return 0; + while (bytes > 0x10000) { + if (initComplete) { + writtenbytes = R0_WriteFile(false,(HANDLE)f->handle,buf,0x8000,f->offset,&error); + writtenbytes += R0_WriteFile(false,(HANDLE)f->handle,buf+0x8000,0x8000,f->offset+0x8000,&error); + } + else { + writtenbytes = i_write(f->handle,buf,0x8000); + writtenbytes += i_write(f->handle,buf+0x8000,0x8000); + } + totalbytes += writtenbytes; + f->offset += writtenbytes; + buf += 0x10000; + bytes -= 0x10000; + } + if (initComplete) + writtenbytes = R0_WriteFile(false,(HANDLE)f->handle,buf,bytes,f->offset,&error); + else + writtenbytes = i_write(f->handle,buf,bytes); + totalbytes += writtenbytes; + f->offset += writtenbytes; + if (f->offset > f->filesize) + f->filesize = f->offset; + return totalbytes / size; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fflush function. +****************************************************************************/ +int fflush( + FILE *f) +{ + /* Nothing to do since we are not doing buffered file I/O */ + (void)f; + return 0; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fseek function. +****************************************************************************/ +int fseek( + FILE *f, + long int offset, + int whence) +{ + if (whence == 0) + f->offset = offset; + else if (whence == 1) + f->offset += offset; + else if (whence == 2) + f->offset = f->filesize + offset; + if (!initComplete) + i_lseek(f->handle,f->offset,0); + return 0; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C ftell function. +****************************************************************************/ +long ftell( + FILE *f) +{ + return f->offset; +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C feof function. +****************************************************************************/ +int feof( + FILE *f) +{ + return (f->offset == f->filesize); +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fgets function. +****************************************************************************/ +char *fgets( + char *s, + int n, + FILE *f) +{ + int len; + char *cs; + + /* Read the entire buffer into memory (our functions are unbuffered!) */ + if ((len = fread(s,1,n,f)) == 0) + return NULL; + + /* Search for '\n' or end of string */ + if (n > len) + n = len; + cs = s; + while (--n > 0) { + if (*cs == '\n') + break; + cs++; + } + *cs = '\0'; + return s; +} + +/**************************************************************************** +REMARKS: +NT driver implementation of the ANSI C fputs function. +****************************************************************************/ +int fputs( + const char *s, + FILE *f) +{ + return fwrite(s,1,strlen(s),f); +} + +/**************************************************************************** +REMARKS: +VxD implementation of the ANSI C fclose function. +****************************************************************************/ +int fclose( + FILE *f) +{ + WORD error; + + if (initComplete) + R0_CloseFile((HANDLE)f->handle,&error); + else + i_close(f->handle); + PM_free(f); + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h new file mode 100644 index 000000000..7efc0f9f8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/oshdr.h @@ -0,0 +1,29 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c new file mode 100644 index 000000000..4cb7f19ed --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/pm.c @@ -0,0 +1,1359 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "sdd/sddhelp.h" +#include "mtrr.h" + +/*--------------------------- Global variables ----------------------------*/ + +#define MAX_MEMORY_SHARED 100 +#define MAX_MEMORY_MAPPINGS 100 + +typedef struct { + void *linear; + ulong global; + ulong length; + int npages; + } memshared; + +typedef struct { + ulong physical; + ulong linear; + ulong length; + int npages; + ibool isCached; + } mmapping; + +static int numMappings = 0; +static memshared shared[MAX_MEMORY_MAPPINGS] = {0}; +static mmapping maps[MAX_MEMORY_MAPPINGS]; +extern ibool _PM_haveBIOS; +char _PM_cntPath[PM_MAX_PATH] = ""; +char _PM_nucleusPath[PM_MAX_PATH] = ""; +uchar *_PM_rmBufAddr = NULL; +ushort _VARAPI _PM_savedDS = 0; +static uchar _PM_oldCMOSRegA; +static uchar _PM_oldCMOSRegB; +PM_intHandler _PM_rtcHandler = NULL; +IRQHANDLE RTCIRQHandle = 0; +VPICD_HWInt_THUNK RTCInt_Thunk; + +static char *szWindowsKey = "Software\\Microsoft\\Windows\\CurrentVersion"; +static char *szSystemRoot = "SystemRoot"; +static char *szMachineNameKey = "System\\CurrentControlSet\\control\\ComputerName\\ComputerName"; +static char *szMachineName = "ComputerName"; +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +/*----------------------------- Implementation ----------------------------*/ + +/* Functions to read and write CMOS registers */ + +ulong PMAPI _PM_getPDB(void); +uchar PMAPI _PM_readCMOS(int index); +void PMAPI _PM_writeCMOS(int index,uchar value); + +/**************************************************************************** +REMARKS: +PM_malloc override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void * VXD_malloc( + size_t size) +{ + return PM_mallocShared(size); +} + +/**************************************************************************** +REMARKS: +PM_calloc override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void * VXD_calloc( + size_t nelem, + size_t size) +{ + void *p = PM_mallocShared(nelem * size); + if (p) + memset(p,0,nelem * size); + return p; +} + +/**************************************************************************** +REMARKS: +PM_realloc override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void * VXD_realloc( + void *ptr, + size_t size) +{ + void *p = PM_mallocShared(size); + if (p) { + memcpy(p,ptr,size); + PM_freeShared(ptr); + } + return p; +} + +/**************************************************************************** +REMARKS: +PM_free override function for Nucleus drivers loaded in VxD's. +****************************************************************************/ +void VXD_free( + void *p) +{ + PM_freeShared(p); +} + +/**************************************************************************** +REMARKS: +Initialise the PM library. +****************************************************************************/ +void PMAPI PM_init(void) +{ + /* Override the default memory allocators for all Nucleus drivers + * loaded in SDDHELP/PMHELP. We do this so that we can ensure all memory + * dynamically allocated by Nucleus drivers and internal C runtime + * library functions are shared memory blocks that all processes + * connecting to SDDHELP can see. + */ + PM_useLocalMalloc(VXD_malloc,VXD_calloc,VXD_realloc,VXD_free); + + /* Initialiase the MTRR module */ + MTRR_init(); +} + +ibool PMAPI PM_haveBIOSAccess(void) +{ return _PM_haveBIOS; } + +long PMAPI PM_getOSType(void) +{ return _OS_WIN32VXD; } + +int PMAPI PM_getModeType(void) +{ return PM_386; } + +void PMAPI PM_backslash(char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +void PMAPI PM_fatalError(const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + Fatal_Error_Handler(msg,0); +} + +/**************************************************************************** +PARAMETERS: +len - Place to store the length of the buffer +rseg - Place to store the real mode segment of the buffer +roff - Place to store the real mode offset of the buffer + +REMARKS: +This function returns the address and length of the global VESA transfer +buffer that is used for communicating with the VESA BIOS functions from +Win16 and Win32 programs under Windows. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + /* If the VxD is dynamically loaded we will not have a real mode + * transfer buffer to return, so we fail the call. + */ + if (_PM_rmBufAddr) { + *len = VESA_BUF_SIZE; + *rseg = (ulong)(_PM_rmBufAddr) >> 4; + *roff = (ulong)(_PM_rmBufAddr) & 0xF; + return _PM_rmBufAddr; + } + return NULL; +} + +int PMAPI PM_int386( + int intno, + PMREGS *in, + PMREGS *out) +{ + /* Unused in VxDs */ + return 0; +} + +void PMAPI _PM_getRMvect( + int intno, + long *realisr) +{ + WORD seg; + DWORD off; + + Get_V86_Int_Vector(intno,&seg,&off); + *realisr = ((long)seg << 16) | (off & 0xFFFF); +} + +void PMAPI _PM_setRMvect( + int intno, + long realisr) +{ + Set_V86_Int_Vector(intno,realisr >> 16,realisr & 0xFFFF); +} + +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + strncpy(path,_PM_cntPath,maxLen); + path[maxLen-1] = 0; + return path; +} + +char PMAPI PM_getBootDrive(void) +{ return 'c'; } + +const char * PMAPI PM_getVBEAFPath(void) +{ return "c:\\"; } + +/**************************************************************************** +PARAMETERS: +szKey - Key to query (can contain version number formatting) +szValue - Value to get information for +value - Place to store the registry key data read +size - Size of the string buffer to read into + +RETURNS: +true if the key was found, false if not. +****************************************************************************/ +static ibool REG_queryString( + char *szKey, + char *szValue, + char *value, + ulong size) +{ + HKEY hKey; + ulong type; + ibool status = false; + + memset(value,0,sizeof(value)); + if (RegOpenKey(HKEY_LOCAL_MACHINE,szKey,&hKey) == ERROR_SUCCESS) { + if (RegQueryValueEx(hKey,(PCHAR)szValue,(ulong*)NULL,(ulong*)&type,value,(ulong*)&size) == ERROR_SUCCESS) + status = true; + RegCloseKey(hKey); + } + return status; +} + +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[256]; + + if (strlen(_PM_nucleusPath) > 0) { + strcpy(path,_PM_nucleusPath); + PM_backslash(path); + return path; + } + if (!REG_queryString(szWindowsKey,szSystemRoot,path,sizeof(path))) + strcpy(path,"c:\\windows"); + PM_backslash(path); + strcat(path,"system\\nucleus"); + return path; +} + +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +const char * PMAPI PM_getUniqueID(void) +{ return PM_getMachineName(); } + +const char * PMAPI PM_getMachineName(void) +{ + static char name[256]; + if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name))) + return name; + return "Unknown"; +} + +int PMAPI PM_kbhit(void) +{ return 1; } + +int PMAPI PM_getch(void) +{ return 0; } + +PM_HWND PMAPI PM_openConsole( + PM_HWND hwndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ + /* Unused in VxDs */ + return NULL; +} + +int PMAPI PM_getConsoleStateSize(void) +{ + /* Unused in VxDs */ + return 1; +} + +void PMAPI PM_saveConsoleState( + void *stateBuf, + PM_HWND hwndConsole) +{ + /* Unused in VxDs */ +} + +void PMAPI PM_setSuspendAppCallback( + int (_ASMAPIP saveState)( + int flags)) +{ + /* Unused in VxDs */ +} + +void PMAPI PM_restoreConsoleState( + const void *stateBuf, + PM_HWND hwndConsole) +{ + /* Unused in VxDs */ +} + +void PMAPI PM_closeConsole( + PM_HWND hwndConsole) +{ + /* Unused in VxDs */ +} + +void PM_setOSCursorLocation( + int x, + int y) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x50,x); + PM_setByte(_biosPtr+0x51,y); +} + +void PM_setOSScreenWidth( + int width, + int height) +{ + uchar *_biosPtr = PM_getBIOSPointer(); + PM_setByte(_biosPtr+0x4A,width); + PM_setByte(_biosPtr+0x84,height-1); +} + +/**************************************************************************** +REMARKS: +Allocate a block of shared memory. For Win9x we allocate shared memory +as locked, global memory that is accessible from any memory context +(including interrupt time context), which allows us to load our important +data structure and code such that we can access it directly from a ring +0 interrupt context. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + MEMHANDLE hMem; + DWORD pgNum,nPages = (size + 0xFFF) >> 12; + int i; + + /* First find a free slot in our shared memory table */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].linear == 0) + break; + } + if (i < MAX_MEMORY_SHARED) { + PageAllocate(nPages,PG_SYS,0,0,0,0,NULL,0,&hMem,&shared[i].linear); + shared[i].npages = nPages; + pgNum = (ulong)shared[i].linear >> 12; + shared[i].global = LinPageLock(pgNum,nPages,PAGEMAPGLOBAL); + return (void*)shared[i].global; + } + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory +****************************************************************************/ +void PMAPI PM_freeShared(void *p) +{ + int i; + + /* Find a shared memory block in our table and free it */ + for (i = 0; i < MAX_MEMORY_SHARED; i++) { + if (shared[i].global == (ulong)p) { + LinPageUnLock(shared[i].global >> 12,shared[i].npages,PAGEMAPGLOBAL); + PageFree((ulong)shared[i].linear,0); + shared[i].linear = 0; + break; + } + } +} + +/**************************************************************************** +REMARKS: +Maps a shared memory block into process address space. Does nothing since +the memory blocks are already globally7 mapped into all processes. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + return (void*)base; +} + +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + /* TODO: Figure out how to do this */ + return false; +} + +void * PMAPI PM_getBIOSPointer(void) +{ return (void*)0x400; } + +void * PMAPI PM_getA0000Pointer(void) +{ return PM_mapPhysicalAddr(0xA0000,0xFFFF,true); } + +/**************************************************************************** +PARAMETERS: +base - Physical base address of the memory to maps in +limit - Limit of physical memory to region to maps in + +RETURNS: +Linear address of the newly mapped memory. + +REMARKS: +Maps a physical memory range to a linear memory range. +****************************************************************************/ +ulong _PM_mapPhysicalToLinear( + ulong base, + ulong limit, + int *npages) +{ + ulong linear,length = limit+1; + int i,ppage,flags; + + if (base < 0x100000) { + /* Windows 9x is zero based for the first meg of memory */ + return base; + } + ppage = base >> 12; + *npages = (length + (base & 0xFFF) + 4095) >> 12; + flags = PR_FIXED | PR_STATIC; + if (base == 0xA0000) { + /* We require the linear address to be aligned to a 64Kb boundary + * for mapping the banked framebuffer (so we can do efficient + * carry checking for bank changes in the assembler code). The only + * way to ensure this is to force the linear address to be aligned + * to a 4Mb boundary. + */ + flags |= PR_4MEG; + } + if ((linear = (ulong)PageReserve(PR_SYSTEM,*npages,flags)) == (ulong)-1) + return 0xFFFFFFFF; + if (!PageCommitPhys(linear >> 12,*npages,ppage,PC_INCR | PC_USER | PC_WRITEABLE)) + return 0xFFFFFFFF; + return linear + (base & 0xFFF); +} + +/* Page table flags */ + +#define PAGE_FLAGS_PRESENT 0x00000001 +#define PAGE_FLAGS_WRITEABLE 0x00000002 +#define PAGE_FLAGS_USER 0x00000004 +#define PAGE_FLAGS_WRITE_THROUGH 0x00000008 +#define PAGE_FLAGS_CACHE_DISABLE 0x00000010 +#define PAGE_FLAGS_ACCESSED 0x00000020 +#define PAGE_FLAGS_DIRTY 0x00000040 +#define PAGE_FLAGS_4MB 0x00000080 + +/**************************************************************************** +PARAMETERS: +base - Physical base address of the memory to maps in +limit - Limit of physical memory to region to maps in +isCached - True if the memory should be cached, false if not + +RETURNS: +Linear address of the newly mapped memory. + +REMARKS: +This function maps physical memory to linear memory, which can then be used +to create a selector or used directly from 32-bit protected mode programs. +This is better than DPMI 0x800, since it allows you to maps physical +memory below 1Mb, which gets this memory out of the way of the Windows VDD's +sticky paws. + +NOTE: If the memory is not expected to be cached, this function will + directly re-program the PCD (Page Cache Disable) bit in the + page tables. There does not appear to be a mechanism in the VMM + to control this bit via the regular interface. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + ulong linear,length = limit+1; + int i,npages; + ulong PDB,*pPDB; + + /* Search table of existing mappings to see if we have already mapped + * a region of memory that will serve this purpose. + */ + for (i = 0; i < numMappings; i++) { + if (maps[i].physical == base && maps[i].length == length && maps[i].isCached == isCached) + return (void*)maps[i].linear; + } + if (numMappings == MAX_MEMORY_MAPPINGS) + return NULL; + + /* We did not find any previously mapped memory region, so maps it in. + * Note that we do not use MapPhysToLinear, since this function appears + * to have problems mapping memory in the 1Mb physical address space. + * Hence we use PageReserve and PageCommitPhys. + */ + if ((linear = _PM_mapPhysicalToLinear(base,limit,&npages)) == 0xFFFFFFFF) + return NULL; + maps[numMappings].physical = base; + maps[numMappings].length = length; + maps[numMappings].linear = linear; + maps[numMappings].npages = npages; + maps[numMappings].isCached = isCached; + numMappings++; + + /* Finally disable caching where necessary */ + if (!isCached && (PDB = _PM_getPDB()) != 0) { + int startPDB,endPDB,iPDB,startPage,endPage,start,end,iPage; + ulong pageTable,*pPageTable; + pPDB = (ulong*)_PM_mapPhysicalToLinear(PDB,0xFFF,&npages); + if (pPDB) { + startPDB = (linear >> 22) & 0x3FF; + startPage = (linear >> 12) & 0x3FF; + endPDB = ((linear+limit) >> 22) & 0x3FF; + endPage = ((linear+limit) >> 12) & 0x3FF; + for (iPDB = startPDB; iPDB <= endPDB; iPDB++) { + /* Set the bits in the page directory entry - required as per */ + /* Pentium 4 manual. This also takes care of the 4MB page entries */ + pPDB[iPDB] = pPDB[iPDB] |= (PAGE_FLAGS_WRITE_THROUGH | PAGE_FLAGS_CACHE_DISABLE); + if (!(pPDB[iPDB] & PAGE_FLAGS_4MB)) { + /* If we are dealing with 4KB pages then we need to iterate */ + /* through each of the page table entries */ + pageTable = pPDB[iPDB] & ~0xFFF; + pPageTable = (ulong*)_PM_mapPhysicalToLinear(pageTable,0xFFF,&npages); + start = (iPDB == startPDB) ? startPage : 0; + end = (iPDB == endPDB) ? endPage : 0x3FF; + for (iPage = start; iPage <= end; iPage++) + pPageTable[iPage] |= (PAGE_FLAGS_WRITE_THROUGH | PAGE_FLAGS_CACHE_DISABLE); + PageFree((ulong)pPageTable,PR_STATIC); + } + } + PageFree((ulong)pPDB,PR_STATIC); + PM_flushTLB(); + } + } + return (void*)linear; +} + +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + /* We never free the mappings */ +} + +void PMAPI PM_sleep(ulong milliseconds) +{ + /* We never sleep in a VxD */ +} + +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + case 2: return 0x3E8; + case 3: return 0x2E8; + } + return 0; +} + +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +ulong PMAPI PM_getPhysicalAddr( + void *p) +{ + DWORD pte; + + /* Touch the memory before calling CopyPageTable. For some reason */ + /* we need to do this on Windows 9x, otherwise the memory may not */ + /* be paged in correctly. Of course if the passed in pointer is */ + /* invalid, this function will fault, but we shouldn't be passed bogus */ + /* pointers anyway ;-) */ + pte = *((ulong*)p); + + /* Return assembled address value only if VMM service succeeds */ + if (CopyPageTable(((DWORD)p) >> 12, 1, (PVOID*)&pte, 0)) + return (pte & ~0xFFF) | (((DWORD)p) & 0xFFF); + + /* Return failure to the caller! */ + return 0xFFFFFFFFUL; +} + +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + int i; + ulong linear = (ulong)p & ~0xFFF; + + for (i = (length + 0xFFF) >> 12; i > 0; i--) { + if ((*physAddress++ = PM_getPhysicalAddr((void*)linear)) == 0xFFFFFFFF) + return false; + linear += 4096; + } + return true; +} + +void PMAPI _PM_freeMemoryMappings(void) +{ + int i; + for (i = 0; i < numMappings; i++) + PageFree(maps[i].linear,PR_STATIC); +} + +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + return (void*)MK_PHYS(r_seg,r_off); +} + +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + return NULL; +} + +void PMAPI PM_freeRealSeg( + void *mem) +{ +} + +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + /* Unsed in VxD's */ +} + +/**************************************************************************** +REMARKS: +Load the V86 registers in the client state, and save the original state +before loading the registers. +****************************************************************************/ +static void LoadV86Registers( + CLIENT_STRUCT *saveRegs, + RMREGS *in, + RMSREGS *sregs) +{ + CLIENT_STRUCT newRegs; + + Save_Client_State(saveRegs); + newRegs = *saveRegs; + newRegs.CRS.Client_EAX = in->e.eax; + newRegs.CRS.Client_EBX = in->e.ebx; + newRegs.CRS.Client_ECX = in->e.ecx; + newRegs.CRS.Client_EDX = in->e.edx; + newRegs.CRS.Client_ESI = in->e.esi; + newRegs.CRS.Client_EDI = in->e.edi; + newRegs.CRS.Client_ES = sregs->es; + newRegs.CRS.Client_DS = sregs->ds; + Restore_Client_State(&newRegs); +} + +/**************************************************************************** +REMARKS: +Read the V86 registers from the client state and restore the original state. +****************************************************************************/ +static void ReadV86Registers( + CLIENT_STRUCT *saveRegs, + RMREGS *out, + RMSREGS *sregs) +{ + CLIENT_STRUCT newRegs; + + Save_Client_State(&newRegs); + out->e.eax = newRegs.CRS.Client_EAX; + out->e.ebx = newRegs.CRS.Client_EBX; + out->e.ecx = newRegs.CRS.Client_ECX; + out->e.edx = newRegs.CRS.Client_EDX; + out->e.esi = newRegs.CRS.Client_ESI; + out->e.edi = newRegs.CRS.Client_EDI; + sregs->es = newRegs.CRS.Client_ES; + sregs->ds = newRegs.CRS.Client_DS; + Restore_Client_State(saveRegs); +} + +/**************************************************************************** +REMARKS: +Call a V86 real mode function with the specified register values +loaded before the call. The call returns with a far ret. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *regs, + RMSREGS *sregs) +{ + CLIENT_STRUCT saveRegs; + + /* Bail if we do not have BIOS access (ie: the VxD was dynamically + * loaded, and not statically loaded. + */ + if (!_PM_haveBIOS) + return; + + _TRACE("SDDHELP: Entering PM_callRealMode()\n"); + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,regs,sregs); + Simulate_Far_Call(seg, off); + Resume_Exec(); + ReadV86Registers(&saveRegs,regs,sregs); + End_Nest_Exec(); + _TRACE("SDDHELP: Exiting PM_callRealMode()\n"); +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + RMSREGS sregs = {0}; + CLIENT_STRUCT saveRegs; + ushort oldDisable; + + /* Bail if we do not have BIOS access (ie: the VxD was dynamically + * loaded, and not statically loaded. + */ + if (!_PM_haveBIOS) { + *out = *in; + return out->x.ax; + } + + /* Disable pass-up to our VxD handler so we directly call BIOS */ + _TRACE("SDDHELP: Entering PM_int86()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,in,&sregs); + Exec_Int(intno); + ReadV86Registers(&saveRegs,out,&sregs); + End_Nest_Exec(); + + /* Re-enable pass-up to our VxD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; + + _TRACE("SDDHELP: Exiting PM_int86()\n"); + return out->x.ax; +} + +/**************************************************************************** +REMARKS: +Issue a V86 real mode interrupt with the specified register values +loaded before the interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + CLIENT_STRUCT saveRegs; + ushort oldDisable; + + /* Bail if we do not have BIOS access (ie: the VxD was dynamically + * loaded, and not statically loaded. + */ + if (!_PM_haveBIOS) { + *out = *in; + return out->x.ax; + } + + /* Disable pass-up to our VxD handler so we directly call BIOS */ + _TRACE("SDDHELP: Entering PM_int86x()\n"); + if (disableTSRFlag) { + oldDisable = *disableTSRFlag; + *disableTSRFlag = 0; + } + Begin_Nest_V86_Exec(); + LoadV86Registers(&saveRegs,in,sregs); + Exec_Int(intno); + ReadV86Registers(&saveRegs,out,sregs); + End_Nest_Exec(); + + /* Re-enable pass-up to our VxD handler if previously enabled */ + if (disableTSRFlag) + *disableTSRFlag = oldDisable; + + _TRACE("SDDHELP: Exiting PM_int86x()\n"); + return out->x.ax; +} + +/**************************************************************************** +REMARKS: +Returns available memory. Not possible under Windows. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +Allocates a block of locked physical memory. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + MEMHANDLE hMem; + DWORD nPages = (size + 0xFFF) >> 12; + DWORD flags = PAGEFIXED | PAGEUSEALIGN | (contiguous ? PAGECONTIG : 0); + DWORD maxPhys = below16M ? 0x00FFFFFF : 0xFFFFFFFF; + void *p; + + /* TODO: This may need to be modified if the memory needs to be globally */ + /* accessible. Check how we implemented PM_mallocShared() as we */ + /* may need to do something similar in here. */ + PageAllocate(nPages,PG_SYS,0,0,0,maxPhys,physAddr,flags,&hMem,&p); + + /* TODO: We may need to modify the memory blocks to disable caching via */ + /* the page tables (PCD|PWT) since DMA memory blocks *cannot* be */ + /* cached! */ + return p; +} + +/**************************************************************************** +REMARKS: +Frees a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + if (p) + PageFree((ulong)p,0); +} + +/**************************************************************************** +REMARKS: +Allocates a page aligned and page sized block of memory +****************************************************************************/ +void * PMAPI PM_allocPage( + ibool locked) +{ + MEMHANDLE hMem; + void *p; + + /* TODO: This will need to be modified if the memory needs to be globally */ + /* accessible. Check how we implemented PM_mallocShared() as we */ + /* may need to do something similar in here. */ + PageAllocate(1,PG_SYS,0,0,0,0,0,PAGEFIXED,&hMem,&p); + return p; +} + +/**************************************************************************** +REMARKS: +Free a page aligned and page sized block of memory +****************************************************************************/ +void PMAPI PM_freePage( + void *p) +{ + if (p) + PageFree((ulong)p,0); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockDataPages( + void *p, + uint len, + PM_lockHandle *lh) +{ + DWORD pgNum = (ulong)p >> 12; + DWORD nPages = (len + (ulong)p - (pgNum << 12) + 0xFFF) >> 12; + return LinPageLock(pgNum,nPages,0); +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockDataPages( + void *p, + uint len, + PM_lockHandle *lh) +{ + DWORD pgNum = (ulong)p >> 12; + DWORD nPages = (len + (ulong)p - (pgNum << 12) + 0xFFF) >> 12; + return LinPageUnLock(pgNum,nPages,0); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lh) +{ + return PM_lockDataPages((void*)p,len,lh); +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockCodePages( + void (*p)(), + uint len, + PM_lockHandle *lh) +{ + return PM_unlockDataPages((void*)p,len,lh); +} + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + static short convert[] = { + 8192, + 4096, + 2048, + 1024, + 512, + 256, + 128, + 64, + 32, + 16, + 8, + 4, + 2, + -1, + }; + int i; + + /* First clear any pending RTC timeout if not cleared */ + _PM_readCMOS(0x0C); + if (frequency == 0) { + /* Disable RTC timout */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB & 0x0F); + } + else { + /* Convert frequency value to RTC clock indexes */ + for (i = 0; convert[i] != -1; i++) { + if (convert[i] == frequency) + break; + } + + /* Set RTC timout value and enable timeout */ + _PM_writeCMOS(0x0A,0x20 | (i+3)); + _PM_writeCMOS(0x0B,(_PM_oldCMOSRegB & 0x0F) | 0x40); + } +} + +/**************************************************************************** +REMARKS: +Real time clock interrupt handler, which calls the user registered C code. +****************************************************************************/ +static BOOL __stdcall RTCInt_Handler( + VMHANDLE hVM, + IRQHANDLE hIRQ) +{ + static char inside = 0; + + /* Clear priority interrupt controller and re-enable interrupts so we + * dont lock things up for long. + */ + VPICD_Phys_EOI(hIRQ); + + /* Clear real-time clock timeout */ + _PM_readCMOS(0x0C); + + /* Now call the C based interrupt handler (but check for mutual + * exclusion since we may still be servicing an old interrupt when a + * new one comes along; if that happens we ignore the old one). + */ + if (!inside) { + inside = 1; + enable(); + _PM_rtcHandler(); + inside = 0; + } + return TRUE; +} + +/**************************************************************************** +REMARKS: +Set the real time clock handler (used for software stereo modes). +****************************************************************************/ +ibool PMAPI PM_setRealTimeClockHandler( + PM_intHandler ih, + int frequency) +{ + struct VPICD_IRQ_Descriptor IRQdesc; + + /* Save the old CMOS real time clock values */ + _PM_oldCMOSRegA = _PM_readCMOS(0x0A); + _PM_oldCMOSRegB = _PM_readCMOS(0x0B); + + /* Set the real time clock interrupt handler */ + CHECK(ih != NULL); + _PM_rtcHandler = ih; + IRQdesc.VID_IRQ_Number = 0x8; + IRQdesc.VID_Options = 0; + IRQdesc.VID_Hw_Int_Proc = (DWORD)VPICD_Thunk_HWInt(RTCInt_Handler, &RTCInt_Thunk); + IRQdesc.VID_EOI_Proc = 0; + IRQdesc.VID_Virt_Int_Proc = 0; + IRQdesc.VID_Mask_Change_Proc= 0; + IRQdesc.VID_IRET_Proc = 0; + IRQdesc.VID_IRET_Time_Out = 500; + if ((RTCIRQHandle = VPICD_Virtualize_IRQ(&IRQdesc)) == 0) + return false; + + /* Program the real time clock default frequency */ + PM_setRealTimeClockFrequency(frequency); + + /* Unmask IRQ8 in the PIC */ + VPICD_Physically_Unmask(RTCIRQHandle); + return true; +} + +/**************************************************************************** +REMARKS: +Restore the original real time clock handler. +****************************************************************************/ +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + if (RTCIRQHandle) { + /* Restore CMOS registers and mask RTC clock */ + _PM_writeCMOS(0x0A,_PM_oldCMOSRegA); + _PM_writeCMOS(0x0B,_PM_oldCMOSRegB); + + /* Restore the interrupt vector */ + VPICD_Set_Auto_Masking(RTCIRQHandle); + VPICD_Force_Default_Behavior(RTCIRQHandle); + RTCIRQHandle = 0; + } +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + (void)szDLLName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + (void)hModule; + (void)szProcName; + return NULL; +} + +/**************************************************************************** +REMARKS: +OS specific shared libraries not supported inside a VxD +****************************************************************************/ +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + (void)hModule; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + /* TODO: This function should start a directory enumeration search */ + /* given the filename (with wildcards). The data should be */ + /* converted and returned in the findData standard form. */ + (void)filename; + (void)findData; + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + /* TODO: This function should find the next file in directory enumeration */ + /* search given the search criteria defined in the call to */ + /* PM_findFirstFile. The data should be converted and returned */ + /* in the findData standard form. */ + (void)handle; + (void)findData; + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + /* TODO: This function should close the find process. This may do */ + /* nothing for some OS'es. */ + (void)handle; +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + /* Not supported in a VxD */ + (void)drive; + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + /* Not supported in a VxD */ + (void)drive; + (void)dir; + (void)len; +} + +/**************************************************************************** +PARAMETERS: +base - The starting physical base address of the region +size - The size in bytes of the region +type - Type to place into the MTRR register + +RETURNS: +Error code describing the result. + +REMARKS: +Function to enable write combining for the specified region of memory. +****************************************************************************/ +int PMAPI PM_enableWriteCombine( + ulong base, + ulong size, + uint type) +{ + return MTRR_enableWriteCombine(base,size,type); +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + /* TODO: Implement this */ + (void)filename; + (void)attrib; + PM_fatalError("PM_setFileAttr not implemented yet!"); +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + /* TODO: Implement this */ + (void)filename; + PM_fatalError("PM_getFileAttr not implemented yet!"); + return 0; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + /* TODO: Implement this */ + (void)filename; + PM_fatalError("PM_mkdir not implemented yet!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + /* TODO: Implement this */ + (void)filename; + PM_fatalError("PM_rmdir not implemented yet!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_getFileTime not implemented yet!"); + return false; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + /* TODO: Implement this! */ + (void)filename; + (void)gmTime; + (void)time; + PM_fatalError("PM_setFileTime not implemented yet!"); + return false; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c new file mode 100644 index 000000000..901ce1cf0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/vflat.c @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init(ulong baseAddr,int bankSize,int codeLen,void *bankFunc) +{ + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c new file mode 100644 index 000000000..76df48c38 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/vxd/ztimer.c @@ -0,0 +1,105 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: 32-bit Windows VxD +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static ulong frequency = 1193180; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +#define __ZTimerInit() + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOn(tm) VTD_Get_Real_Time(&tm->start.high,&tm->start.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + CPU_largeInteger lap,count; + VTD_Get_Real_Time(&lap.high,&lap.low); + _CPU_diffTime64(&tm->start,&lap,&count); + return _CPU_calcMicroSec(&count,frequency); +} + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +#define __LZTimerOff(tm) VTD_Get_Real_Time(&tm->end.high,&tm->end.low) + +/**************************************************************************** +REMARKS: +Call the assembler Zen Timer functions to do the timing. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,frequency); +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1000 + +/**************************************************************************** +REMARKS: +Read the Long Period timer value from the BIOS timer tick. +****************************************************************************/ +static ulong __ULZReadTime(void) +{ + CPU_largeInteger count; + VTD_Get_Real_Time(&count.high,&count.low); + return (count.low * 1000.0 / frequency); +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm b/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm new file mode 100644 index 000000000..7c242b572 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/_pmwin32.asm @@ -0,0 +1,78 @@ +;**************************************************************************** +;* +;* SciTech OS Portability Manager Library +;* +;* ======================================================================== +;* +;* The contents of this file are subject to the SciTech MGL Public +;* License Version 1.0 (the "License"); you may not use this file +;* except in compliance with the License. You may obtain a copy of +;* the License at http://www.scitechsoft.com/mgl-license.txt +;* +;* Software distributed under the License is distributed on an +;* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +;* implied. See the License for the specific language governing +;* rights and limitations under the License. +;* +;* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +;* +;* The Initial Developer of the Original Code is SciTech Software, Inc. +;* All Rights Reserved. +;* +;* ======================================================================== +;* +;* Language: 80386 Assembler, TASM 4.0 or NASM +;* Environment: Win32 +;* +;* Description: Low level assembly support for the PM library specific +;* to Windows. +;* +;**************************************************************************** + + IDEAL + +include "scitech.mac" ; Memory model macros + +header _pmwin32 ; Set up memory model + +begdataseg _pmwin32 + + cglobal _PM_ioentry + cglobal _PM_gdt +_PM_ioentry dd 0 ; Offset to call gate +_PM_gdt dw 0 ; Selector to call gate + +enddataseg _pmwin32 + +begcodeseg _pmwin32 ; Start of code segment + +;---------------------------------------------------------------------------- +; int PM_setIOPL(int iopl) +;---------------------------------------------------------------------------- +; Change the IOPL level for the 32-bit task. Returns the previous level +; so it can be restored for the task correctly. +;---------------------------------------------------------------------------- +cprocstart _PM_setIOPLViaCallGate + + ARG iopl:UINT + + enter_c + pushfd ; Save the old EFLAGS for later + mov ecx,[iopl] ; ECX := IOPL level + xor ebx,ebx ; Change IOPL level function code +ifdef USE_NASM + call far dword [_PM_ioentry] +else + call [FWORD _PM_ioentry] +endif + pop eax + and eax,0011000000000000b + shr eax,12 + leave_c + ret + +cprocend + +endcodeseg _pmwin32 + + END ; End of module diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c b/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c new file mode 100644 index 000000000..7da975205 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/cpuinfo.c @@ -0,0 +1,94 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: Module to implement OS specific services to measure the +* CPU frequency. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static ibool havePerformanceCounter; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Increase the thread priority to maximum, if possible. +****************************************************************************/ +static int SetMaxThreadPriority(void) +{ + int oldPriority; + HANDLE hThread = GetCurrentThread(); + + oldPriority = GetThreadPriority(hThread); + if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) + SetThreadPriority(hThread, THREAD_PRIORITY_TIME_CRITICAL); + return oldPriority; +} + +/**************************************************************************** +REMARKS: +Restore the original thread priority. +****************************************************************************/ +static void RestoreThreadPriority( + int oldPriority) +{ + HANDLE hThread = GetCurrentThread(); + + if (oldPriority != THREAD_PRIORITY_ERROR_RETURN) + SetThreadPriority(hThread, oldPriority); +} + +/**************************************************************************** +REMARKS: +Initialise the counter and return the frequency of the counter. +****************************************************************************/ +static void GetCounterFrequency( + CPU_largeInteger *freq) +{ + if (!QueryPerformanceFrequency((LARGE_INTEGER*)freq)) { + havePerformanceCounter = false; + freq->low = 100000; + freq->high = 0; + } + else + havePerformanceCounter = true; +} + +/**************************************************************************** +REMARKS: +Read the counter and return the counter value. +****************************************************************************/ +#define GetCounter(t) \ +{ \ + if (havePerformanceCounter) \ + QueryPerformanceCounter((LARGE_INTEGER*)t); \ + else { \ + (t)->low = timeGetTime() * 100; \ + (t)->high = 0; \ + } \ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c new file mode 100644 index 000000000..d6c3f60e8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/ddraw.c @@ -0,0 +1,582 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: Win32 implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +#include "event.h" +#include "pmapi.h" +#include "win32/oshdr.h" +#include "nucleus/graphics.h" + +/*---------------------------- Global Variables ---------------------------*/ + +/* Publicly accessible variables */ + +int _PM_deskX,_PM_deskY;/* Desktop dimentions */ +HWND _PM_hwndConsole; /* Window handle for console */ +#ifdef __INTEL__ +uint _PM_cw_default; /* Default FPU control word */ +#endif + +/* Private internal variables */ + +static HINSTANCE hInstApp = NULL;/* Application instance handle */ +static HWND hwndUser = NULL;/* User window handle */ +static HINSTANCE hInstDD = NULL; /* Handle to DirectDraw DLL */ +static LPDIRECTDRAW lpDD = NULL; /* DirectDraw object */ +static LONG oldWndStyle; /* Info about old user window */ +static LONG oldExWndStyle; /* Info about old user window */ +static int oldWinPosX; /* Old window position X coordinate */ +static int oldWinPosY; /* Old window pisition Y coordinate */ +static int oldWinSizeX; /* Old window size X */ +static int oldWinSizeY; /* Old window size Y */ +static WNDPROC oldWinProc = NULL; +static PM_saveState_cb suspendApp = NULL; +static ibool waitActive = false; +static ibool isFullScreen = false; +static ibool backInGDI = false; + +/* Internal strings */ + +static char *szWinClassName = "SciTechDirectDrawWindow"; +static char *szAutoPlayKey = "Software\\Microsoft\\Windows\\CurrentVersion\\Policies\\Explorer"; +static char *szAutoPlayValue = "NoDriveTypeAutoRun"; + +/* Dynalinks to DirectDraw functions */ + +static HRESULT (WINAPI *pDirectDrawCreate)(GUID FAR *lpGUID, LPDIRECTDRAW FAR *lplpDD, IUnknown FAR *pUnkOuter); + +/*---------------------------- Implementation -----------------------------*/ + +/**************************************************************************** +REMARKS: +Temporarily disables AutoPlay operation while we are running in fullscreen +graphics modes. +****************************************************************************/ +static void DisableAutoPlay(void) +{ + DWORD dwAutoPlay,dwSize = sizeof(dwAutoPlay); + HKEY hKey; + + if (RegOpenKeyEx(HKEY_CURRENT_USER,szAutoPlayKey,0,KEY_EXECUTE | KEY_WRITE,&hKey) == ERROR_SUCCESS) { + RegQueryValueEx(hKey,szAutoPlayValue,NULL,NULL,(void*)&dwAutoPlay,&dwSize); + dwAutoPlay |= AUTOPLAY_DRIVE_CDROM; + RegSetValueEx(hKey,szAutoPlayValue,0,REG_DWORD,(void*)&dwAutoPlay,dwSize); + RegCloseKey(hKey); + } +} + +/**************************************************************************** +REMARKS: +Re-enables AutoPlay operation when we return to regular GDI mode. +****************************************************************************/ +static void RestoreAutoPlay(void) +{ + DWORD dwAutoPlay,dwSize = sizeof(dwAutoPlay); + HKEY hKey; + + if (RegOpenKeyEx(HKEY_CURRENT_USER,szAutoPlayKey,0,KEY_EXECUTE | KEY_WRITE,&hKey) == ERROR_SUCCESS) { + RegQueryValueEx(hKey,szAutoPlayValue,NULL,NULL,(void*)&dwAutoPlay,&dwSize); + dwAutoPlay &= ~AUTOPLAY_DRIVE_CDROM; + RegSetValueEx(hKey,szAutoPlayValue,0,REG_DWORD,(void*)&dwAutoPlay,dwSize); + RegCloseKey(hKey); + } +} + +/**************************************************************************** +REMARKS: +Suspends the application by switching back to the GDI desktop, allowing +normal application code to be processed, and then waiting for the +application activate command to bring us back to fullscreen mode with our +window minimised. +****************************************************************************/ +static void LeaveFullScreen(void) +{ + int retCode = PM_SUSPEND_APP; + + if (backInGDI) + return; + if (suspendApp) + retCode = suspendApp(PM_DEACTIVATE); + RestoreAutoPlay(); + backInGDI = true; + + /* Now process messages normally until we are re-activated */ + waitActive = true; + if (retCode != PM_NO_SUSPEND_APP) { + while (waitActive) { + _EVT_pumpMessages(); + Sleep(200); + } + } +} + +/**************************************************************************** +REMARKS: +Reactivate all the surfaces for DirectDraw and set the system back up for +fullscreen rendering. +****************************************************************************/ +static void RestoreFullScreen(void) +{ + static ibool firstTime = true; + + if (firstTime) { + /* Clear the message queue while waiting for the surfaces to be + * restored. + */ + firstTime = false; + while (1) { + /* Continue looping until out application has been restored + * and we have reset the display mode. + */ + _EVT_pumpMessages(); + if (GetActiveWindow() == _PM_hwndConsole) { + if (suspendApp) + suspendApp(PM_REACTIVATE); + DisableAutoPlay(); + backInGDI = false; + waitActive = false; + firstTime = true; + return; + } + Sleep(200); + } + } +} + +/**************************************************************************** +REMARKS: +This function suspends the application by switching back to the GDI desktop, +allowing normal application code to be processed and then waiting for the +application activate command to bring us back to fullscreen mode with our +window minimised. + +This version only gets called if we have not captured the screen switch in +our activate message loops and will occur if the DirectDraw drivers lose a +surface for some reason while rendering. This should not normally happen, +but it is included just to be sure (it can happen on WinNT/2000 if the user +hits the Ctrl-Alt-Del key combination). Note that this code will always +spin loop, and we cannot disable the spin looping from this version (ie: +if the user hits Ctrl-Alt-Del under WinNT/2000 the application main loop +will cease to be executed until the user switches back to the application). +****************************************************************************/ +void PMAPI PM_doSuspendApp(void) +{ + static ibool firstTime = true; + + /* Call system DLL version if found */ + if (_PM_imports.PM_doSuspendApp != PM_doSuspendApp) { + _PM_imports.PM_doSuspendApp(); + return; + } + + if (firstTime) { + if (suspendApp) + suspendApp(PM_DEACTIVATE); + RestoreAutoPlay(); + firstTime = false; + backInGDI = true; + } + RestoreFullScreen(); + firstTime = true; +} + +/**************************************************************************** +REMARKS: +Main Window proc for the full screen DirectDraw Window that we create while +running in full screen mode. Here we capture all mouse and keyboard events +for the window and plug them into our event queue. +****************************************************************************/ +static LONG CALLBACK PM_winProc( + HWND hwnd, + UINT msg, + WPARAM wParam, + LONG lParam) +{ + switch (msg) { + case WM_SYSCHAR: + /* Stop Alt-Space from pausing our application */ + return 0; + case WM_KEYDOWN: + case WM_SYSKEYDOWN: + if (HIWORD(lParam) & KF_REPEAT) { + if (msg == WM_SYSKEYDOWN) + return 0; + break; + } + /* Fall through for keydown events */ + case WM_KEYUP: + case WM_SYSKEYUP: + if (msg == WM_SYSKEYDOWN || msg == WM_SYSKEYUP) { + if ((HIWORD(lParam) & KF_ALTDOWN) && wParam == VK_RETURN) + break; + /* We ignore the remainder of the system keys to stop the + * system menu from being activated from the keyboard and pausing + * our app while fullscreen (ie: pressing the Alt key). + */ + return 0; + } + break; + case WM_SYSCOMMAND: + switch (wParam & ~0x0F) { + case SC_SCREENSAVE: + case SC_MONITORPOWER: + /* Ignore screensaver requests in fullscreen modes */ + return 0; + } + break; + case WM_SIZE: + if (waitActive && backInGDI && (wParam != SIZE_MINIMIZED)) { + /* Start the re-activation process */ + PostMessage(hwnd,WM_DO_SUSPEND_APP,WM_PM_RESTORE_FULLSCREEN,0); + } + else if (!waitActive && isFullScreen && !backInGDI && (wParam == SIZE_MINIMIZED)) { + /* Start the de-activation process */ + PostMessage(hwnd,WM_DO_SUSPEND_APP,WM_PM_LEAVE_FULLSCREEN,0); + } + break; + case WM_DO_SUSPEND_APP: + switch (wParam) { + case WM_PM_RESTORE_FULLSCREEN: + RestoreFullScreen(); + break; + case WM_PM_LEAVE_FULLSCREEN: + LeaveFullScreen(); + break; + } + return 0; + } + if (oldWinProc) + return oldWinProc(hwnd,msg,wParam,lParam); + return DefWindowProc(hwnd,msg,wParam,lParam); +} + +/**************************************************************************** +PARAMETERS: +hwnd - User window to convert +width - Window of the fullscreen window +height - Height of the fullscreen window + +RETURNS: +Handle to converted fullscreen Window. + +REMARKS: +This function takes the original user window handle and modifies the size, +position and attributes for the window to convert it into a fullscreen +window that we can use. +****************************************************************************/ +static PM_HWND _PM_convertUserWindow( + HWND hwnd, + int width, + int height) +{ + RECT window; + + GetWindowRect(hwnd,&window); + oldWinPosX = window.left; + oldWinPosY = window.top; + oldWinSizeX = window.right - window.left; + oldWinSizeY = window.bottom - window.top; + oldWndStyle = SetWindowLong(hwnd,GWL_STYLE,WS_POPUP | WS_SYSMENU); + oldExWndStyle = SetWindowLong(hwnd,GWL_EXSTYLE,WS_EX_APPWINDOW); + ShowWindow(hwnd,SW_SHOW); + MoveWindow(hwnd,0,0,width,height,TRUE); + SetWindowPos(hwnd,HWND_TOPMOST,0,0,0,0,SWP_NOMOVE | SWP_NOSIZE); + oldWinProc = (WNDPROC)SetWindowLong(hwnd,GWL_WNDPROC, (LPARAM)PM_winProc); + return hwnd; +} + +/**************************************************************************** +PARAMETERS: +hwnd - User window to restore + +REMARKS: +This function restores the original attributes of the user window and put's +it back into it's original state before it was converted to a fullscreen +window. +****************************************************************************/ +static void _PM_restoreUserWindow( + HWND hwnd) +{ + SetWindowLong(hwnd,GWL_WNDPROC, (LPARAM)oldWinProc); + SetWindowLong(hwnd,GWL_EXSTYLE,oldExWndStyle); + SetWindowLong(hwnd,GWL_STYLE,oldWndStyle); + SetWindowPos(hwnd,HWND_NOTOPMOST,0,0,0,0,SWP_NOMOVE | SWP_NOSIZE); + ShowWindow(hwnd,SW_SHOW); + MoveWindow(hwnd,oldWinPosX,oldWinPosY,oldWinSizeX,oldWinSizeY,TRUE); + oldWinProc = NULL; +} + +/**************************************************************************** +PARAMETERS: +device - Index of the device to load DirectDraw for (0 for primary) + +REMARKS: +Attempts to dynamically load the DirectDraw DLL's and create the DirectDraw +objects that we need. +****************************************************************************/ +void * PMAPI PM_loadDirectDraw( + int device) +{ + HDC hdc; + int bits; + + /* Call system DLL version if found */ + if (_PM_imports.PM_loadDirectDraw != PM_loadDirectDraw) + return _PM_imports.PM_loadDirectDraw(device); + + /* TODO: Handle multi-monitor!! */ + if (device != 0) + return NULL; + + /* Load the DirectDraw DLL if not presently loaded */ + GET_DEFAULT_CW(); + if (!hInstDD) { + hdc = GetDC(NULL); + bits = GetDeviceCaps(hdc,BITSPIXEL); + ReleaseDC(NULL,hdc); + if (bits < 8) + return NULL; + if ((hInstDD = LoadLibrary("ddraw.dll")) == NULL) + return NULL; + pDirectDrawCreate = (void*)GetProcAddress(hInstDD,"DirectDrawCreate"); + if (!pDirectDrawCreate) + return NULL; + } + + /* Create the DirectDraw object */ + if (!lpDD && pDirectDrawCreate(NULL, &lpDD, NULL) != DD_OK) { + lpDD = NULL; + return NULL; + } + RESET_DEFAULT_CW(); + return lpDD; +} + +/**************************************************************************** +PARAMETERS: +device - Index of the device to unload DirectDraw for (0 for primary) + +REMARKS: +Frees any DirectDraw objects for the device. We never actually explicitly +unload the ddraw.dll library, since unloading and reloading it is +unnecessary since we only want to unload it when the application exits and +that happens automatically. +****************************************************************************/ +void PMAPI PM_unloadDirectDraw( + int device) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_unloadDirectDraw != PM_unloadDirectDraw) { + _PM_imports.PM_unloadDirectDraw(device); + return; + } + if (lpDD) { + IDirectDraw_Release(lpDD); + lpDD = NULL; + } + (void)device; +} + +/**************************************************************************** +REMARKS: +Open a console for output to the screen, creating the main event handling +window if necessary. +****************************************************************************/ +PM_HWND PMAPI PM_openConsole( + PM_HWND hWndUser, + int device, + int xRes, + int yRes, + int bpp, + ibool fullScreen) +{ + WNDCLASS cls; + static ibool classRegistered = false; + + /* Call system DLL version if found */ + GA_getSystemPMImports(); + if (_PM_imports.PM_openConsole != PM_openConsole) { + if (fullScreen) { + _PM_deskX = xRes; + _PM_deskY = yRes; + } + return _PM_imports.PM_openConsole(hWndUser,device,xRes,yRes,bpp,fullScreen); + } + + /* Create the fullscreen window if necessary */ + hwndUser = hWndUser; + if (fullScreen) { + if (!classRegistered) { + /* Create a Window class for the fullscreen window in here, since + * we need to register one that will do all our event handling for + * us. + */ + hInstApp = GetModuleHandle(NULL); + cls.hCursor = LoadCursor(NULL,IDC_ARROW); + cls.hIcon = LoadIcon(hInstApp,MAKEINTRESOURCE(1)); + cls.lpszMenuName = NULL; + cls.lpszClassName = szWinClassName; + cls.hbrBackground = GetStockObject(BLACK_BRUSH); + cls.hInstance = hInstApp; + cls.style = CS_DBLCLKS; + cls.lpfnWndProc = PM_winProc; + cls.cbWndExtra = 0; + cls.cbClsExtra = 0; + if (!RegisterClass(&cls)) + return NULL; + classRegistered = true; + } + _PM_deskX = xRes; + _PM_deskY = yRes; + if (!hwndUser) { + char windowTitle[80]; + if (LoadString(hInstApp,1,windowTitle,sizeof(windowTitle)) == 0) + strcpy(windowTitle,"MGL Fullscreen Application"); + _PM_hwndConsole = CreateWindowEx(WS_EX_APPWINDOW,szWinClassName, + windowTitle,WS_POPUP | WS_SYSMENU,0,0,xRes,yRes, + NULL,NULL,hInstApp,NULL); + } + else { + _PM_hwndConsole = _PM_convertUserWindow(hwndUser,xRes,yRes); + } + ShowCursor(false); + isFullScreen = true; + } + else { + _PM_hwndConsole = hwndUser; + isFullScreen = false; + } + SetFocus(_PM_hwndConsole); + SetForegroundWindow(_PM_hwndConsole); + DisableAutoPlay(); + (void)bpp; + return _PM_hwndConsole; +} + +/**************************************************************************** +REMARKS: +Find the size of the console state buffer. +****************************************************************************/ +int PMAPI PM_getConsoleStateSize(void) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_getConsoleStateSize != PM_getConsoleStateSize) + return _PM_imports.PM_getConsoleStateSize(); + + /* Not used in Windows */ + return 1; +} + +/**************************************************************************** +REMARKS: +Save the state of the console. +****************************************************************************/ +void PMAPI PM_saveConsoleState( + void *stateBuf, + PM_HWND hwndConsole) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_saveConsoleState != PM_saveConsoleState) { + _PM_imports.PM_saveConsoleState(stateBuf,hwndConsole); + return; + } + + /* Not used in Windows */ + (void)stateBuf; + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Set the suspend application callback for the fullscreen console. +****************************************************************************/ +void PMAPI PM_setSuspendAppCallback( + PM_saveState_cb saveState) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_setSuspendAppCallback != PM_setSuspendAppCallback) { + _PM_imports.PM_setSuspendAppCallback(saveState); + return; + } + suspendApp = saveState; +} + +/**************************************************************************** +REMARKS: +Restore the console state. +****************************************************************************/ +void PMAPI PM_restoreConsoleState( + const void *stateBuf, + PM_HWND hwndConsole) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_restoreConsoleState != PM_restoreConsoleState) { + _PM_imports.PM_restoreConsoleState(stateBuf,hwndConsole); + return; + } + + /* Not used in Windows */ + (void)stateBuf; + (void)hwndConsole; +} + +/**************************************************************************** +REMARKS: +Close the fullscreen console. +****************************************************************************/ +void PMAPI PM_closeConsole( + PM_HWND hwndConsole) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_closeConsole != PM_closeConsole) { + _PM_imports.PM_closeConsole(hwndConsole); + return; + } + ShowCursor(true); + RestoreAutoPlay(); + if (hwndUser) + _PM_restoreUserWindow(hwndConsole); + else + DestroyWindow(hwndConsole); + hwndUser = NULL; + _PM_hwndConsole = NULL; +} + +/**************************************************************************** +REMARKS: +Return the DirectDraw window handle used by the application. +****************************************************************************/ +PM_HWND PMAPI PM_getDirectDrawWindow(void) +{ + /* Call system DLL version if found */ + if (_PM_imports.PM_getDirectDrawWindow != PM_getDirectDrawWindow) + return _PM_imports.PM_getDirectDrawWindow(); + return _PM_hwndConsole; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/event.c b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c new file mode 100644 index 000000000..6388052ce --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/event.c @@ -0,0 +1,459 @@ +/**************************************************************************** +* +* SciTech Multi-platform Graphics Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: Win32 implementation for the SciTech cross platform +* event library. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static ushort keyUpMsg[256] = {0}; /* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under Win32 */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) (void)(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ return timeGetTime(); } + +/**************************************************************************** +REMARKS: +Pumps all messages in the message queue from Win32 into our event queue. +****************************************************************************/ +void _EVT_pumpMessages(void) +{ + MSG msg; + MSG charMsg; + event_t evt; + + /* TODO: Add support for DirectInput! We can't support relative mouse */ + /* movement motion counters without DirectInput ;-(. */ + while (PeekMessage(&msg,NULL,0,0,PM_REMOVE)) { + memset(&evt,0,sizeof(evt)); + switch (msg.message) { + case WM_MOUSEMOVE: + evt.what = EVT_MOUSEMOVE; + break; + case WM_LBUTTONDBLCLK: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_LEFTBMASK | EVT_DBLCLICK; + break; + case WM_LBUTTONDOWN: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_LEFTBMASK; + break; + case WM_LBUTTONUP: + evt.what = EVT_MOUSEUP; + evt.message = EVT_LEFTBMASK; + break; + case WM_RBUTTONDBLCLK: + evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK; + evt.message = EVT_RIGHTBMASK; + break; + case WM_RBUTTONDOWN: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_RIGHTBMASK; + break; + case WM_RBUTTONUP: + evt.what = EVT_MOUSEUP; + evt.message = EVT_RIGHTBMASK; + break; + case WM_MBUTTONDBLCLK: + evt.what = EVT_MOUSEDOWN | EVT_DBLCLICK; + evt.message = EVT_MIDDLEBMASK; + break; + case WM_MBUTTONDOWN: + evt.what = EVT_MOUSEDOWN; + evt.message = EVT_MIDDLEBMASK; + break; + case WM_MBUTTONUP: + evt.what = EVT_MOUSEUP; + evt.message = EVT_MIDDLEBMASK; + break; + case WM_KEYDOWN: + case WM_SYSKEYDOWN: + if (HIWORD(msg.lParam) & KF_REPEAT) { + evt.what = EVT_KEYREPEAT; + } + else { + evt.what = EVT_KEYDOWN; + } + break; + case WM_KEYUP: + case WM_SYSKEYUP: + evt.what = EVT_KEYUP; + break; + } + + /* Convert mouse event modifier flags */ + if (evt.what & EVT_MOUSEEVT) { + if (_PM_deskX) { + evt.where_x = ((long)msg.pt.x * rangeX) / _PM_deskX; + evt.where_y = ((long)msg.pt.y * rangeY) / _PM_deskY; + } + else { + ScreenToClient(_PM_hwndConsole, &msg.pt); + evt.where_x = msg.pt.x; + evt.where_y = msg.pt.y; + } + if (evt.what == EVT_MOUSEMOVE) { + /* Save the current mouse position */ + EVT.mx = evt.where_x; + EVT.my = evt.where_y; + if (EVT.oldMove != -1) { + EVT.evtq[EVT.oldMove].where_x = evt.where_x;/* Modify existing one */ + EVT.evtq[EVT.oldMove].where_y = evt.where_y; +/* EVT.evtq[EVT.oldMove].relative_x += mickeyX; / / TODO! */ +/* EVT.evtq[EVT.oldMove].relative_y += mickeyY; / / TODO! */ + evt.what = 0; + } + else { + EVT.oldMove = EVT.freeHead; /* Save id of this move event */ +/* evt.relative_x = mickeyX; / / TODO! */ +/* evt.relative_y = mickeyY; / / TODO! */ + } + } + else + EVT.oldMove = -1; + if (msg.wParam & MK_LBUTTON) + evt.modifiers |= EVT_LEFTBUT; + if (msg.wParam & MK_RBUTTON) + evt.modifiers |= EVT_RIGHTBUT; + if (msg.wParam & MK_MBUTTON) + evt.modifiers |= EVT_MIDDLEBUT; + if (msg.wParam & MK_SHIFT) + evt.modifiers |= EVT_SHIFTKEY; + if (msg.wParam & MK_CONTROL) + evt.modifiers |= EVT_CTRLSTATE; + } + + /* Convert keyboard codes */ + TranslateMessage(&msg); + if (evt.what & EVT_KEYEVT) { + int scanCode = (msg.lParam >> 16) & 0xFF; + if (evt.what == EVT_KEYUP) { + /* Get message for keyup code from table of cached down values */ + evt.message = keyUpMsg[scanCode]; + keyUpMsg[scanCode] = 0; + } + else { + if (PeekMessage(&charMsg,NULL,WM_CHAR,WM_CHAR,PM_REMOVE)) + evt.message = charMsg.wParam; + if (PeekMessage(&charMsg,NULL,WM_SYSCHAR,WM_SYSCHAR,PM_REMOVE)) + evt.message = charMsg.wParam; + evt.message |= ((msg.lParam >> 8) & 0xFF00); + keyUpMsg[scanCode] = (ushort)evt.message; + } + if (evt.what == EVT_KEYREPEAT) + evt.message |= (msg.lParam << 16); + if (HIWORD(msg.lParam) & KF_ALTDOWN) + evt.modifiers |= EVT_ALTSTATE; + if (GetKeyState(VK_SHIFT) & 0x8000U) + evt.modifiers |= EVT_SHIFTKEY; + if (GetKeyState(VK_CONTROL) & 0x8000U) + evt.modifiers |= EVT_CTRLSTATE; + EVT.oldMove = -1; + } + + if (evt.what != 0) { + /* Add time stamp and add the event to the queue */ + evt.when = msg.time; + if (EVT.count < EVENTQSIZE) + addEvent(&evt); + } + DispatchMessage(&msg); + } +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort( + int signal) +{ + (void)signal; + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +void EVTAPI EVT_init( + _EVT_mouseMoveHandler mouseMove) +{ + /* Initialise the event queue */ + EVT.mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS +Modifes the mouse coordinates as necessary if scaling to OS coordinates, +and sets the OS mouse cursor position. +****************************************************************************/ +void _EVT_setMousePos( + int *x, + int *y) +{ + /* Scale coordinates up to desktop coordinates first */ + int scaledX = (*x * _PM_deskX) / rangeX; + int scaledY = (*y * _PM_deskY) / rangeY; + + /* Scale coordinates back to screen coordinates again */ + *x = (scaledX * rangeX) / _PM_deskX; + *y = (scaledY * rangeY) / _PM_deskY; + SetCursorPos(scaledX,scaledY); +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for Win32 */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for Win32 */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); +} + +/**************************************************************************** +DESCRIPTION: +Returns the mask indicating what joystick axes are attached. + +HEADER: +event.h + +REMARKS: +This function is used to detect the attached joysticks, and determine +what axes are present and functioning. This function will re-detect any +attached joysticks when it is called, so if the user forgot to attach +the joystick when the application started, you can call this function to +re-detect any newly attached joysticks. + +SEE ALSO: +EVT_joySetLowerRight, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +int EVTAPI EVT_joyIsPresent(void) +{ + /* TODO: Implement joystick code based on DirectX! */ + return 0; +} + +/**************************************************************************** +DESCRIPTION: +Polls the joystick for position and button information. + +HEADER: +event.h + +REMARKS: +This routine is used to poll analogue joysticks for button and position +information. It should be called once for each main loop of the user +application, just before processing all pending events via EVT_getNext. +All information polled from the joystick will be posted to the event +queue for later retrieval. + +Note: Most analogue joysticks will provide readings that change even + though the joystick has not moved. Hence if you call this routine + you will likely get an EVT_JOYMOVE event every time through your + event loop. + +SEE ALSO: +EVT_getNext, EVT_peekNext, EVT_joySetUpperLeft, EVT_joySetLowerRight, +EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_pollJoystick(void) +{ +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick upper left position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the upper left +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetUpperLeft(void) +{ +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick lower right position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the lower right +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetCenter, EVT_joyIsPresent +****************************************************************************/ +void EVTAPI EVT_joySetLowerRight(void) +{ +} + +/**************************************************************************** +DESCRIPTION: +Calibrates the joystick center position + +HEADER: +event.h + +REMARKS: +This function can be used to zero in on better joystick calibration factors, +which may work better than the default simplistic calibration (which assumes +the joystick is centered when the event library is initialised). +To use this function, ask the user to hold the stick in the center +position and then have them press a key or button. and then call this +function. This function will then read the joystick and update the +calibration factors. + +Usually, assuming that the stick was centered when the event library was +initialized, you really only need to call EVT_joySetLowerRight since the +upper left position is usually always 0,0 on most joysticks. However, the +safest procedure is to call all three calibration functions. + +SEE ALSO: +EVT_joySetUpperLeft, EVT_joySetLowerRight, EVT_joySetCenter +****************************************************************************/ +void EVTAPI EVT_joySetCenter(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c new file mode 100644 index 000000000..59d9aa0c7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/ntservc.c @@ -0,0 +1,258 @@ +/**************************************************************************** +* +* SciTech Display Doctor +* +* Copyright (C) 1991-2001 SciTech Software, Inc. +* All rights reserved. +* +* ====================================================================== +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* | | +* |This copyrighted computer code is a proprietary trade secret of | +* |SciTech Software, Inc., located at 505 Wall Street, Chico, CA 95928 | +* |USA (www.scitechsoft.com). ANY UNAUTHORIZED POSSESSION, USE, | +* |VIEWING, COPYING, MODIFICATION OR DISSEMINATION OF THIS CODE IS | +* |STRICTLY PROHIBITED BY LAW. Unless you have current, express | +* |written authorization from SciTech to possess or use this code, you | +* |may be subject to civil and/or criminal penalties. | +* | | +* |If you received this code in error or you would like to report | +* |improper use, please immediately contact SciTech Software, Inc. at | +* |530-894-8400. | +* | | +* |REMOVAL OR MODIFICATION OF THIS HEADER IS STRICTLY PROHIBITED BY LAW| +* ====================================================================== +* +* Language: ANSI C +* Environment: Windows NT, Windows 2K or Windows XP. +* +* Description: Main module to do the installation of the SDD and GLDirect +* device driver components under Windows NT/2K/XP. +* +****************************************************************************/ + +#include "pmapi.h" +#include "win32/oshdr.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +szDriverName - Actual name of the driver to install in the system +szServiceName - Name of the service to create +szLoadGroup - Load group for the driver (NULL for normal drivers) +dwServiceType - Service type to create + +RETURNS: +True on success, false on failure. + +REMARKS: +This function does all the work to install the driver into the system. +The driver is not however activated; for that you must use the Start_SddFilt +function. +****************************************************************************/ +ulong PMAPI PM_installService( + const char *szDriverName, + const char *szServiceName, + const char *szLoadGroup, + ulong dwServiceType) +{ + SC_HANDLE scmHandle; + SC_HANDLE driverHandle; + char szDriverPath[MAX_PATH]; + HKEY key; + char keyPath[MAX_PATH]; + ulong status; + + /* Obtain a handle to the service control manager requesting all access */ + if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) + return GetLastError(); + + /* Find the path to the driver in system directory */ + GetSystemDirectory(szDriverPath, sizeof(szDriverPath)); + strcat(szDriverPath, "\\drivers\\"); + strcat(szDriverPath, szDriverName); + + /* Create the service with the Service Control Manager. */ + driverHandle = CreateService(scmHandle, + szServiceName, + szServiceName, + SERVICE_ALL_ACCESS, + dwServiceType, + SERVICE_BOOT_START, + SERVICE_ERROR_NORMAL, + szDriverPath, + szLoadGroup, + NULL, + NULL, + NULL, + NULL); + + /* Check to see if the driver could actually be installed. */ + if (!driverHandle) { + status = GetLastError(); + CloseServiceHandle(scmHandle); + return status; + } + + /* Get a handle to the key for driver so that it can be altered in the */ + /* next step. */ + strcpy(keyPath, "SYSTEM\\CurrentControlSet\\Services\\"); + strcat(keyPath, szServiceName); + if ((status = RegOpenKeyEx(HKEY_LOCAL_MACHINE,keyPath,0,KEY_ALL_ACCESS,&key)) != ERROR_SUCCESS) { + /* A problem has occured. Delete the service so that it is not installed. */ + status = GetLastError(); + DeleteService(driverHandle); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + + /* Delete the ImagePath value in the newly created key so that the */ + /* system looks for the driver in the normal location. */ + if ((status = RegDeleteValue(key, "ImagePath")) != ERROR_SUCCESS) { + /* A problem has occurred. Delete the service so that it is not */ + /* installed and will not try to start. */ + RegCloseKey(key); + DeleteService(driverHandle); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + + /* Clean up and exit */ + RegCloseKey(key); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return ERROR_SUCCESS; +} + +/**************************************************************************** +PARAMETERS: +szServiceName - Name of the service to start + +RETURNS: +True on success, false on failure. + +REMARKS: +This function is used to start the specified service and make it active. +****************************************************************************/ +ulong PMAPI PM_startService( + const char *szServiceName) +{ + SC_HANDLE scmHandle; + SC_HANDLE driverHandle; + SERVICE_STATUS serviceStatus; + ulong status; + + /* Obtain a handle to the service control manager requesting all access */ + if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) + return GetLastError(); + + /* Open the service with the Service Control Manager. */ + if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) { + status = GetLastError(); + CloseServiceHandle(scmHandle); + return status; + } + + /* Start the service */ + if (!StartService(driverHandle,0,NULL)) { + status = GetLastError(); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + + /* Query the service to make sure it is there */ + if (!QueryServiceStatus(driverHandle,&serviceStatus)) { + status = GetLastError(); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return ERROR_SUCCESS; +} + +/**************************************************************************** +PARAMETERS: +szServiceName - Name of the service to stop + +RETURNS: +True on success, false on failure. + +REMARKS: +This function is used to stop the specified service and disable it. +****************************************************************************/ +ulong PMAPI PM_stopService( + const char *szServiceName) +{ + SC_HANDLE scmHandle; + SC_HANDLE driverHandle; + SERVICE_STATUS serviceStatus; + ulong status; + + /* Obtain a handle to the service control manager requesting all access */ + if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) + return GetLastError(); + + /* Open the service with the Service Control Manager. */ + if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) { + status = GetLastError(); + CloseServiceHandle(scmHandle); + return status; + } + + /* Stop the service from running */ + if (!ControlService(driverHandle, SERVICE_CONTROL_STOP, &serviceStatus)) { + status = GetLastError(); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return ERROR_SUCCESS; +} + +/**************************************************************************** +PARAMETERS: +szServiceName - Name of the service to remove + +RETURNS: +True on success, false on failure. + +REMARKS: +This function is used to remove a service completely from the system. +****************************************************************************/ +ulong PMAPI PM_removeService( + const char *szServiceName) +{ + SC_HANDLE scmHandle; + SC_HANDLE driverHandle; + ulong status; + + /* Obtain a handle to the service control manager requesting all access */ + if ((scmHandle = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS)) == NULL) + return GetLastError(); + + /* Open the service with the Service Control Manager. */ + if ((driverHandle = OpenService(scmHandle,szServiceName,SERVICE_ALL_ACCESS)) == NULL) { + status = GetLastError(); + CloseServiceHandle(scmHandle); + return status; + } + + /* Remove the service */ + if (!DeleteService(driverHandle)) { + status = GetLastError(); + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return status; + } + CloseServiceHandle(driverHandle); + CloseServiceHandle(scmHandle); + return ERROR_SUCCESS; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h new file mode 100644 index 000000000..0c59e9006 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/oshdr.h @@ -0,0 +1,79 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#include +#include +#define NONAMELESSUNION +#include "pm/ddraw.h" + +/* Macros to save and restore the default control word. Windows 9x has + * some bugs in it such that calls to load any DLL's which load 16-bit + * DLL's cause the floating point control word to get trashed. We fix + * this by saving and restoring the control word across problematic + * calls. + */ + +#if defined(__INTEL__) +#define GET_DEFAULT_CW() \ +{ \ + if (_PM_cw_default == 0) \ + _PM_cw_default = _control87(0,0); \ +} +#define RESET_DEFAULT_CW() \ + _control87(_PM_cw_default,0xFFFFFFFF) +#else +#define GET_DEFAULT_CW() +#define RESET_DEFAULT_CW() +#endif + +/* Custom window messages */ + +#define WM_DO_SUSPEND_APP WM_USER +#define WM_PM_LEAVE_FULLSCREEN 0 +#define WM_PM_RESTORE_FULLSCREEN 1 + +/* Macro for disabling AutoPlay on a use system */ + +#define AUTOPLAY_DRIVE_CDROM 0x20 + +/*--------------------------- Global Variables ----------------------------*/ + +#ifdef __INTEL__ +extern uint _PM_cw_default; /* Default FPU control word */ +#endif +extern int _PM_deskX,_PM_deskY; /* Desktop dimensions */ +extern HWND _PM_hwndConsole; /* Window handle for console */ + +/*-------------------------- Internal Functions ---------------------------*/ + +void _EVT_pumpMessages(void); diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c b/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c new file mode 100644 index 000000000..1ffdbccab --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/pm.c @@ -0,0 +1,1459 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: Implementation for the OS Portability Manager Library, which +* contains functions to implement OS specific services in a +* generic, cross platform API. Porting the OS Portability +* Manager library is the first step to porting any SciTech +* products to a new platform. +* +****************************************************************************/ + +#define WIN32_LEAN_AND_MEAN +#define STRICT +#include +#include +#include +#include +#include +#include +#include "pmapi.h" +#include "drvlib/os/os.h" +#include "pm_help.h" + +/*--------------------------- Global variables ----------------------------*/ + +ibool _PM_haveWinNT; /* True if we are running on NT */ +static uint VESABuf_len = 1024; /* Length of the VESABuf buffer */ +static void *VESABuf_ptr = NULL;/* Near pointer to VESABuf */ +static uint VESABuf_rseg; /* Real mode segment of VESABuf */ +static uint VESABuf_roff; /* Real mode offset of VESABuf */ +HANDLE _PM_hDevice = NULL; /* Handle to Win32 VxD */ +static ibool inited = false; /* Flags if we are initialised */ +static void (PMAPIP fatalErrorCleanup)(void) = NULL; + +static char *szMachineNameKey = "System\\CurrentControlSet\\control\\ComputerName\\ComputerName"; +static char *szMachineNameKeyNT = "System\\CurrentControlSet\\control\\ComputerName\\ActiveComputerName"; +static char *szMachineName = "ComputerName"; + +/*----------------------------- Implementation ----------------------------*/ + +/* Macro to check for a valid, loaded version of PMHELP. We check this + * on demand when we need these services rather than when PM_init() is + * called because if we are running on DirectDraw we don't need PMHELP.VXD. + */ + +#define CHECK_FOR_PMHELP() \ +{ \ + if (_PM_hDevice == INVALID_HANDLE_VALUE) \ + if (_PM_haveWinNT) \ + PM_fatalError("Unable to connect to PMHELP.SYS or SDDHELP.SYS!"); \ + else \ + PM_fatalError("Unable to connect to PMHELP.VXD or SDDHELP.VXD!"); \ +} + +/**************************************************************************** +REMARKS: +Initialise the PM library and connect to our helper device driver. If we +cannot connect to our helper device driver, we bail out with an error +message. Our Windows 9x VxD is dynamically loadable, so it can be loaded +after the system has started. +****************************************************************************/ +void PMAPI PM_init(void) +{ + DWORD inBuf[1]; /* Buffer to receive data from VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + char cntPath[PM_MAX_PATH]; + char *env; + + /* Create a file handle for the static VxD if possible, otherwise + * dynamically load the PMHELP helper VxD. Note that if an old version + * of SDD is loaded, we use the PMHELP VxD instead. + */ + if (!inited) { + /* Determine if we are running under Windows NT or not and + * set the global OS type variable. + */ + _PM_haveWinNT = false; + if ((GetVersion() & 0x80000000UL) == 0) + _PM_haveWinNT = true; + ___drv_os_type = (_PM_haveWinNT) ? _OS_WINNT : _OS_WIN95; + + /* Now try to connect to SDDHELP.VXD or SDDHELP.SYS */ + _PM_hDevice = CreateFile(SDDHELP_MODULE_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0); + if (_PM_hDevice != INVALID_HANDLE_VALUE) { + if (!DeviceIoControl(_PM_hDevice, PMHELP_GETVER32, NULL, 0, + outBuf, sizeof(outBuf), &count, NULL) || outBuf[0] < PMHELP_VERSION) { + /* Old version of SDDHELP loaded, so use PMHELP instead */ + CloseHandle(_PM_hDevice); + _PM_hDevice = INVALID_HANDLE_VALUE; + } + } + if (_PM_hDevice == INVALID_HANDLE_VALUE) { + /* First try to see if there is a currently loaded PMHELP driver. + * This is usually the case when we are running under Windows NT/2K. + */ + _PM_hDevice = CreateFile(PMHELP_MODULE_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0); + if (_PM_hDevice == INVALID_HANDLE_VALUE) { + /* The driver was not staticly loaded, so try creating a file handle + * to a dynamic version of the VxD if possible. Note that on WinNT/2K we + * cannot support dynamically loading the drivers. + */ + _PM_hDevice = CreateFile(PMHELP_VXD_PATH, 0,0,0, CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0); + } + } + if (_PM_hDevice != INVALID_HANDLE_VALUE) { + /* Call the driver to determine the version number */ + if (!DeviceIoControl(_PM_hDevice, PMHELP_GETVER32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL) || outBuf[0] < PMHELP_VERSION) { + if (_PM_haveWinNT) + PM_fatalError("Older version of PMHELP.SYS found!"); + else + PM_fatalError("Older version of PMHELP.VXD found!"); + } + + /* Now set the current path inside the VxD so it knows what the + * current directory is for loading Nucleus drivers. + */ + inBuf[0] = (ulong)PM_getCurrentPath(cntPath,sizeof(cntPath)); + if (!DeviceIoControl(_PM_hDevice, PMHELP_SETCNTPATH32, inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &count, NULL)) + PM_fatalError("Unable to set VxD current path!"); + + /* Now pass down the NUCLEUS_PATH environment variable to the device + * driver so it can use this value if it is found. + */ + if ((env = getenv("NUCLEUS_PATH")) != NULL) { + inBuf[0] = (ulong)env; + if (!DeviceIoControl(_PM_hDevice, PMHELP_SETNUCLEUSPATH32, inBuf, sizeof(inBuf), outBuf, sizeof(outBuf), &count, NULL)) + PM_fatalError("Unable to set VxD Nucleus path!"); + } + + /* Enable IOPL for ring-3 code by default if driver is present */ + if (_PM_haveWinNT) + PM_setIOPL(3); + } + + /* Indicate that we have been initialised */ + inited = true; + } +} + +/**************************************************************************** +REMARKS: +We do have BIOS access under Windows 9x, but not under Windows NT. +****************************************************************************/ +int PMAPI PM_setIOPL( + int iopl) +{ + DWORD inBuf[1]; /* Buffer to receive data from VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + static int cntIOPL = 0; + int oldIOPL = cntIOPL; + + /* Enable I/O by adjusting the I/O permissions map on Windows NT */ + if (_PM_haveWinNT) { + CHECK_FOR_PMHELP(); + if (iopl == 3) + DeviceIoControl(_PM_hDevice, PMHELP_ENABLERING3IOPL, inBuf, sizeof(inBuf),outBuf, sizeof(outBuf), &count, NULL); + else + DeviceIoControl(_PM_hDevice, PMHELP_DISABLERING3IOPL, inBuf, sizeof(inBuf),outBuf, sizeof(outBuf), &count, NULL); + cntIOPL = iopl; + return oldIOPL; + } + + /* We always have IOPL on Windows 9x */ + return 3; +} + +/**************************************************************************** +REMARKS: +We do have BIOS access under Windows 9x, but not under Windows NT. +****************************************************************************/ +ibool PMAPI PM_haveBIOSAccess(void) +{ + if (PM_getOSType() == _OS_WINNT) + return false; + else + return _PM_hDevice != INVALID_HANDLE_VALUE; +} + +/**************************************************************************** +REMARKS: +Return the operating system type identifier. +****************************************************************************/ +long PMAPI PM_getOSType(void) +{ + if ((GetVersion() & 0x80000000UL) == 0) + return ___drv_os_type = _OS_WINNT; + else + return ___drv_os_type = _OS_WIN95; +} + +/**************************************************************************** +REMARKS: +Return the runtime type identifier. +****************************************************************************/ +int PMAPI PM_getModeType(void) +{ + return PM_386; +} + +/**************************************************************************** +REMARKS: +Add a file directory separator to the end of the filename. +****************************************************************************/ +void PMAPI PM_backslash( + char *s) +{ + uint pos = strlen(s); + if (s[pos-1] != '\\') { + s[pos] = '\\'; + s[pos+1] = '\0'; + } +} + +/**************************************************************************** +REMARKS: +Add a user defined PM_fatalError cleanup function. +****************************************************************************/ +void PMAPI PM_setFatalErrorCleanup( + void (PMAPIP cleanup)(void)) +{ + fatalErrorCleanup = cleanup; +} + +/**************************************************************************** +REMARKS: +Report a fatal error condition and halt the program. +****************************************************************************/ +void PMAPI PM_fatalError( + const char *msg) +{ + if (fatalErrorCleanup) + fatalErrorCleanup(); + MessageBox(NULL,msg,"Fatal Error!", MB_ICONEXCLAMATION); + exit(1); +} + +/**************************************************************************** +REMARKS: +Allocate the real mode VESA transfer buffer for communicating with the BIOS. +****************************************************************************/ +void * PMAPI PM_getVESABuf( + uint *len, + uint *rseg, + uint *roff) +{ + DWORD outBuf[4]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + /* We require the helper VxD to be loaded staticly in order to support + * the VESA transfer buffer. We do not support dynamically allocating + * real mode memory buffers from Win32 programs (we need a 16-bit DLL + * for this, and Windows 9x becomes very unstable if you free the + * memory blocks out of order). + */ + if (!inited) + PM_init(); + if (!VESABuf_ptr) { + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_GETVESABUF32, NULL, 0, + outBuf, sizeof(outBuf), &count, NULL)) { + if (!outBuf[0]) + return NULL; + VESABuf_ptr = (void*)outBuf[0]; + VESABuf_len = outBuf[1]; + VESABuf_rseg = outBuf[2]; + VESABuf_roff = outBuf[3]; + } + } + *len = VESABuf_len; + *rseg = VESABuf_rseg; + *roff = VESABuf_roff; + return VESABuf_ptr; +} + +/**************************************************************************** +REMARKS: +Check if a key has been pressed. +****************************************************************************/ +int PMAPI PM_kbhit(void) +{ + /* Not used in Windows */ + return true; +} + +/**************************************************************************** +REMARKS: +Wait for and return the next keypress. +****************************************************************************/ +int PMAPI PM_getch(void) +{ + /* Not used in Windows */ + return 0xD; +} + +/**************************************************************************** +REMARKS: +Set the location of the OS console cursor. +****************************************************************************/ +void PM_setOSCursorLocation( + int x, + int y) +{ + /* Nothing to do for Windows */ + (void)x; + (void)y; +} + +/**************************************************************************** +REMARKS: +Set the width of the OS console. +****************************************************************************/ +void PM_setOSScreenWidth( + int width, + int height) +{ + /* Nothing to do for Windows */ + (void)width; + (void)height; +} + +/**************************************************************************** +REMARKS: +Set the real time clock handler (used for software stereo modes). +****************************************************************************/ +ibool PMAPI PM_setRealTimeClockHandler( + PM_intHandler ih, + int frequency) +{ + /* We do not support this from Win32 programs. Rather the VxD handles + * this stuff it will take care of hooking the stereo flip functions at + * the VxD level. + */ + (void)ih; + (void)frequency; + return false; +} + +/**************************************************************************** +REMARKS: +Set the real time clock frequency (for stereo modes). +****************************************************************************/ +void PMAPI PM_setRealTimeClockFrequency( + int frequency) +{ + /* Not supported under Win32 */ + (void)frequency; +} + +/**************************************************************************** +REMARKS: +Restore the original real time clock handler. +****************************************************************************/ +void PMAPI PM_restoreRealTimeClockHandler(void) +{ + /* Not supported under Win32 */ +} + +/**************************************************************************** +REMARKS: +Return the current operating system path or working directory. +****************************************************************************/ +char * PMAPI PM_getCurrentPath( + char *path, + int maxLen) +{ + return getcwd(path,maxLen); +} + +/**************************************************************************** +REMARKS: +Query a string from the registry (extended version). +****************************************************************************/ +static ibool REG_queryStringEx( + HKEY hKey, + const char *szValue, + char *value, + ulong size) +{ + DWORD type; + + if (RegQueryValueEx(hKey,(PCHAR)szValue,(PDWORD)NULL,(PDWORD)&type,(LPBYTE)value,(PDWORD)&size) == ERROR_SUCCESS) + return true; + return false; +} + +/**************************************************************************** +REMARKS: +Query a string from the registry. +****************************************************************************/ +static ibool REG_queryString( + const char *szKey, + const char *szValue, + char *value, + DWORD size) +{ + HKEY hKey; + ibool status = false; + + memset(value,0,sizeof(value)); + if (RegOpenKey(HKEY_LOCAL_MACHINE,szKey,&hKey) == ERROR_SUCCESS) { + status = REG_queryStringEx(hKey,szValue,value,size); + RegCloseKey(hKey); + } + return status; +} + +/**************************************************************************** +REMARKS: +Return the drive letter for the boot drive. +****************************************************************************/ +char PMAPI PM_getBootDrive(void) +{ + static char path[256]; + GetSystemDirectory(path,sizeof(path)); + return path[0]; +} + +/**************************************************************************** +REMARKS: +Return the path to the VBE/AF driver files. +****************************************************************************/ +const char * PMAPI PM_getVBEAFPath(void) +{ + return "c:\\"; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus driver files. +****************************************************************************/ +const char * PMAPI PM_getNucleusPath(void) +{ + static char path[256]; + char *env; + + if ((env = getenv("NUCLEUS_PATH")) != NULL) + return env; + GetSystemDirectory(path,sizeof(path)); + strcat(path,"\\nucleus"); + return path; +} + +/**************************************************************************** +REMARKS: +Return the path to the Nucleus configuration files. +****************************************************************************/ +const char * PMAPI PM_getNucleusConfigPath(void) +{ + static char path[256]; + strcpy(path,PM_getNucleusPath()); + PM_backslash(path); + strcat(path,"config"); + return path; +} + +/**************************************************************************** +REMARKS: +Return a unique identifier for the machine if possible. +****************************************************************************/ +const char * PMAPI PM_getUniqueID(void) +{ + return PM_getMachineName(); +} + +/**************************************************************************** +REMARKS: +Get the name of the machine on the network. +****************************************************************************/ +const char * PMAPI PM_getMachineName(void) +{ + static char name[256]; + + if (REG_queryString(szMachineNameKey,szMachineName,name,sizeof(name))) + return name; + if (REG_queryString(szMachineNameKeyNT,szMachineName,name,sizeof(name))) + return name; + return "Unknown"; +} + +/**************************************************************************** +REMARKS: +Return a pointer to the real mode BIOS data area. +****************************************************************************/ +void * PMAPI PM_getBIOSPointer(void) +{ + if (_PM_haveWinNT) { + /* On Windows NT we have to map it physically directly */ + return PM_mapPhysicalAddr(0x400, 0x1000, true); + } + else { + /* For Windows 9x we can access this memory directly */ + return (void*)0x400; + } +} + +/**************************************************************************** +REMARKS: +Return a pointer to 0xA0000 physical VGA graphics framebuffer. +****************************************************************************/ +void * PMAPI PM_getA0000Pointer(void) +{ + if (_PM_haveWinNT) { + /* On Windows NT we have to map it physically directly */ + return PM_mapPhysicalAddr(0xA0000, 0x0FFFF, false); + } + else { + /* Always use the 0xA0000 linear address so that we will use + * whatever page table mappings are set up for us (ie: for virtual + * bank switching. + */ + return (void*)0xA0000; + } +} + +/**************************************************************************** +REMARKS: +Map a physical address to a linear address in the callers process. +****************************************************************************/ +void * PMAPI PM_mapPhysicalAddr( + ulong base, + ulong limit, + ibool isCached) +{ + DWORD inBuf[3]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = base; + inBuf[1] = limit; + inBuf[2] = isCached; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_MAPPHYS32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return (void*)outBuf[0]; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a physical address mapping allocated by PM_mapPhysicalAddr. +****************************************************************************/ +void PMAPI PM_freePhysicalAddr( + void *ptr, + ulong limit) +{ + /* We never free the mappings under Win32 (the VxD tracks them and + * reissues the same mappings until the system is rebooted). + */ + (void)ptr; + (void)limit; +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ulong PMAPI PM_getPhysicalAddr( + void *p) +{ + DWORD inBuf[1]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = (ulong)p; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_GETPHYSICALADDR32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0xFFFFFFFFUL; +} + +/**************************************************************************** +REMARKS: +Find the physical address of a linear memory address in current process. +****************************************************************************/ +ibool PMAPI PM_getPhysicalAddrRange( + void *p, + ulong length, + ulong *physAddress) +{ + DWORD inBuf[3]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = (ulong)p; + inBuf[1] = (ulong)length; + inBuf[2] = (ulong)physAddress; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_GETPHYSICALADDRRANGE32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return false; +} + +/**************************************************************************** +REMARKS: +Sleep for the specified number of milliseconds. +****************************************************************************/ +void PMAPI PM_sleep( + ulong milliseconds) +{ + Sleep(milliseconds); +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified COM port. +****************************************************************************/ +int PMAPI PM_getCOMPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3F8; + case 1: return 0x2F8; + case 2: return 0x3E8; + case 3: return 0x2E8; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Return the base I/O port for the specified LPT port. +****************************************************************************/ +int PMAPI PM_getLPTPort(int port) +{ + /* TODO: Re-code this to determine real values using the Plug and Play */ + /* manager for the OS. */ + switch (port) { + case 0: return 0x3BC; + case 1: return 0x378; + case 2: return 0x278; + } + return 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of shared memory. For Win9x we allocate shared memory +as locked, global memory that is accessible from any memory context +(including interrupt time context), which allows us to load our important +data structure and code such that we can access it directly from a ring +0 interrupt context. +****************************************************************************/ +void * PMAPI PM_mallocShared( + long size) +{ + DWORD inBuf[1]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = size; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_MALLOCSHARED32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return (void*)outBuf[0]; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of shared memory. +****************************************************************************/ +void PMAPI PM_freeShared( + void *ptr) +{ + DWORD inBuf[1]; /* Buffer to send data to VxD */ + + inBuf[0] = (ulong)ptr; + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_FREESHARED32, inBuf, sizeof(inBuf), NULL, 0, NULL, NULL); +} + +/**************************************************************************** +REMARKS: +Map a linear memory address to the calling process address space. The +address will have been allocated in another process using the +PM_mapPhysicalAddr function. +****************************************************************************/ +void * PMAPI PM_mapToProcess( + void *base, + ulong limit) +{ + (void)base; + (void)limit; + return base; +} + +/**************************************************************************** +REMARKS: +Map a real mode pointer to a protected mode pointer. +****************************************************************************/ +void * PMAPI PM_mapRealPointer( + uint r_seg, + uint r_off) +{ + return (void*)(MK_PHYS(r_seg,r_off)); +} + +/**************************************************************************** +REMARKS: +Allocate a block of real mode memory +****************************************************************************/ +void * PMAPI PM_allocRealSeg( + uint size, + uint *r_seg, + uint *r_off) +{ + /* We do not support dynamically allocating real mode memory buffers + * from Win32 programs (we need a 16-bit DLL for this, and Windows + * 9x becomes very unstable if you free the memory blocks out of order). + */ + (void)size; + (void)r_seg; + (void)r_off; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of real mode memory. +****************************************************************************/ +void PMAPI PM_freeRealSeg( + void *mem) +{ + /* Not supported in Windows */ + (void)mem; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt (parameters in DPMI compatible structure) +****************************************************************************/ +void PMAPI DPMI_int86( + int intno, + DPMI_regs *regs) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = intno; + inBuf[1] = (ulong)regs; + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_DPMIINT8632, inBuf, sizeof(inBuf), + NULL, 0, &count, NULL); +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86( + int intno, + RMREGS *in, + RMREGS *out) +{ + DWORD inBuf[3]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = intno; + inBuf[1] = (ulong)in; + inBuf[2] = (ulong)out; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_INT8632, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Issue a real mode interrupt. +****************************************************************************/ +int PMAPI PM_int86x( + int intno, + RMREGS *in, + RMREGS *out, + RMSREGS *sregs) +{ + DWORD inBuf[4]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = intno; + inBuf[1] = (ulong)in; + inBuf[2] = (ulong)out; + inBuf[3] = (ulong)sregs; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_INT86X32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Call a real mode far function. +****************************************************************************/ +void PMAPI PM_callRealMode( + uint seg, + uint off, + RMREGS *in, + RMSREGS *sregs) +{ + DWORD inBuf[4]; /* Buffer to send data to VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = seg; + inBuf[1] = off; + inBuf[2] = (ulong)in; + inBuf[3] = (ulong)sregs; + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_CALLREALMODE32, inBuf, sizeof(inBuf), + NULL, 0, &count, NULL); +} + +/**************************************************************************** +REMARKS: +Return the amount of available memory. +****************************************************************************/ +void PMAPI PM_availableMemory( + ulong *physical, + ulong *total) +{ + /* We don't support this under Win32 at the moment */ + *physical = *total = 0; +} + +/**************************************************************************** +REMARKS: +Allocate a block of locked, physical memory for DMA operations. +****************************************************************************/ +void * PMAPI PM_allocLockedMem( + uint size, + ulong *physAddr, + ibool contiguous, + ibool below16M) +{ + DWORD inBuf[4]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = size; + inBuf[1] = (ulong)physAddr; + inBuf[2] = (ulong)contiguous; + inBuf[3] = (ulong)below16M; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_ALLOCLOCKED32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return (void*)outBuf[0]; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a block of locked physical memory. +****************************************************************************/ +void PMAPI PM_freeLockedMem( + void *p, + uint size, + ibool contiguous) +{ + DWORD inBuf[3]; /* Buffer to send data to VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = (ulong)p; + inBuf[1] = size; + inBuf[2] = contiguous; + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_FREELOCKED32, inBuf, sizeof(inBuf), + NULL, 0, &count, NULL); +} + +/**************************************************************************** +REMARKS: +Allocates a page aligned and page sized block of memory +****************************************************************************/ +void * PMAPI PM_allocPage( + ibool locked) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = locked; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_ALLOCPAGE32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return (void*)outBuf[0]; + return NULL; +} + +/**************************************************************************** +REMARKS: +Free a page aligned and page sized block of memory +****************************************************************************/ +void PMAPI PM_freePage( + void *p) +{ + DWORD inBuf[1]; /* Buffer to send data to VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = (ulong)p; + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_FREEPAGE32, inBuf, sizeof(inBuf), + NULL, 0, &count, NULL); +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)p; + inBuf[1] = len; + inBuf[2] = (ulong)lh; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_LOCKDATAPAGES32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockDataPages(void *p,uint len,PM_lockHandle *lh) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)p; + inBuf[1] = len; + inBuf[2] = (ulong)lh; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_UNLOCKDATAPAGES32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Lock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_lockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)p; + inBuf[1] = len; + inBuf[2] = (ulong)lh; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_LOCKCODEPAGES32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Unlock linear memory so it won't be paged. +****************************************************************************/ +int PMAPI PM_unlockCodePages(void (*p)(),uint len,PM_lockHandle *lh) +{ + DWORD inBuf[2]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + inBuf[0] = (ulong)p; + inBuf[1] = len; + inBuf[2] = (ulong)lh; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_UNLOCKCODEPAGES32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankA( + int bank) +{ + RMREGS regs; + regs.x.ax = 0x4F05; + regs.x.bx = 0x0000; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display banks. +****************************************************************************/ +void PMAPI PM_setBankAB( + int bank) +{ + RMREGS regs; + regs.x.ax = 0x4F05; + regs.x.bx = 0x0000; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); + regs.x.ax = 0x4F05; + regs.x.bx = 0x0001; + regs.x.dx = bank; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Call the VBE/Core software interrupt to change display start address. +****************************************************************************/ +void PMAPI PM_setCRTStart( + int x, + int y, + int waitVRT) +{ + RMREGS regs; + regs.x.ax = 0x4F07; + regs.x.bx = waitVRT; + regs.x.cx = x; + regs.x.dx = y; + PM_int86(0x10,®s,®s); +} + +/**************************************************************************** +REMARKS: +Enable write combining for the memory region. +****************************************************************************/ +ibool PMAPI PM_enableWriteCombine( + ulong base, + ulong length, + uint type) +{ + DWORD inBuf[3]; /* Buffer to send data to VxD */ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + if (!inited) + PM_init(); + inBuf[0] = base; + inBuf[1] = length; + inBuf[2] = type; + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_ENABLELFBCOMB32, inBuf, sizeof(inBuf), + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return false; +} + +/**************************************************************************** +REMARKS: +Get the page directory base register value +****************************************************************************/ +ulong PMAPI _PM_getPDB(void) +{ + DWORD outBuf[1]; /* Buffer to receive data from VxD */ + DWORD count; /* Count of bytes returned from VxD */ + + CHECK_FOR_PMHELP(); + if (DeviceIoControl(_PM_hDevice, PMHELP_GETPDB32, NULL, 0, + outBuf, sizeof(outBuf), &count, NULL)) + return outBuf[0]; + return 0; +} + +/**************************************************************************** +REMARKS: +Flush the translation lookaside buffer. +****************************************************************************/ +void PMAPI PM_flushTLB(void) +{ + CHECK_FOR_PMHELP(); + DeviceIoControl(_PM_hDevice, PMHELP_FLUSHTLB32, NULL, 0, NULL, 0, NULL, NULL); +} + +/**************************************************************************** +REMARKS: +Execute the POST on the secondary BIOS for a controller. +****************************************************************************/ +ibool PMAPI PM_doBIOSPOST( + ushort axVal, + ulong BIOSPhysAddr, + void *mappedBIOS, + ulong BIOSLen) +{ + /* This is never done by Win32 programs, but rather done by the VxD + * when the system boots. + */ + (void)axVal; + (void)BIOSPhysAddr; + (void)mappedBIOS; + (void)BIOSLen; + return false; +} + +/**************************************************************************** +REMARKS: +Load an OS specific shared library or DLL. If the OS does not support +shared libraries, simply return NULL. +****************************************************************************/ +PM_MODULE PMAPI PM_loadLibrary( + const char *szDLLName) +{ + return (PM_MODULE)LoadLibrary(szDLLName); +} + +/**************************************************************************** +REMARKS: +Get the address of a named procedure from a shared library. +****************************************************************************/ +void * PMAPI PM_getProcAddress( + PM_MODULE hModule, + const char *szProcName) +{ + return (void*)GetProcAddress((HINSTANCE)hModule,szProcName); +} + +/**************************************************************************** +REMARKS: +Unload a shared library. +****************************************************************************/ +void PMAPI PM_freeLibrary( + PM_MODULE hModule) +{ + FreeLibrary((HINSTANCE)hModule); +} + +/**************************************************************************** +REMARKS: +Internal function to convert the find data to the generic interface. +****************************************************************************/ +static void convertFindData( + PM_findData *findData, + WIN32_FIND_DATA *blk) +{ + ulong dwSize = findData->dwSize; + + memset(findData,0,findData->dwSize); + findData->dwSize = dwSize; + if (blk->dwFileAttributes & FILE_ATTRIBUTE_READONLY) + findData->attrib |= PM_FILE_READONLY; + if (blk->dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) + findData->attrib |= PM_FILE_DIRECTORY; + if (blk->dwFileAttributes & FILE_ATTRIBUTE_ARCHIVE) + findData->attrib |= PM_FILE_ARCHIVE; + if (blk->dwFileAttributes & FILE_ATTRIBUTE_HIDDEN) + findData->attrib |= PM_FILE_HIDDEN; + if (blk->dwFileAttributes & FILE_ATTRIBUTE_SYSTEM) + findData->attrib |= PM_FILE_SYSTEM; + findData->sizeLo = blk->nFileSizeLow; + findData->sizeHi = blk->nFileSizeHigh; + strncpy(findData->name,blk->cFileName,PM_MAX_PATH); + findData->name[PM_MAX_PATH-1] = 0; +} + +/**************************************************************************** +REMARKS: +Function to find the first file matching a search criteria in a directory. +****************************************************************************/ +void *PMAPI PM_findFirstFile( + const char *filename, + PM_findData *findData) +{ + WIN32_FIND_DATA blk; + HANDLE hfile; + + if ((hfile = FindFirstFile(filename,&blk)) != INVALID_HANDLE_VALUE) { + convertFindData(findData,&blk); + return (void*)hfile; + } + return PM_FILE_INVALID; +} + +/**************************************************************************** +REMARKS: +Function to find the next file matching a search criteria in a directory. +****************************************************************************/ +ibool PMAPI PM_findNextFile( + void *handle, + PM_findData *findData) +{ + WIN32_FIND_DATA blk; + + if (FindNextFile((HANDLE)handle,&blk)) { + convertFindData(findData,&blk); + return true; + } + return false; +} + +/**************************************************************************** +REMARKS: +Function to close the find process +****************************************************************************/ +void PMAPI PM_findClose( + void *handle) +{ + FindClose((HANDLE)handle); +} + +/**************************************************************************** +REMARKS: +Function to determine if a drive is a valid drive or not. Under Unix this +function will return false for anything except a value of 3 (considered +the root drive, and equivalent to C: for non-Unix systems). The drive +numbering is: + + 1 - Drive A: + 2 - Drive B: + 3 - Drive C: + etc + +****************************************************************************/ +ibool PMAPI PM_driveValid( + char drive) +{ + char buf[5]; + int type; + + sprintf(buf,"%c:\\", drive); + return ((type = GetDriveType(buf)) != 0 && type != 1); +} + +/**************************************************************************** +REMARKS: +Function to get the current working directory for the specififed drive. +Under Unix this will always return the current working directory regardless +of what the value of 'drive' is. +****************************************************************************/ +void PMAPI PM_getdcwd( + int drive, + char *dir, + int len) +{ + /* NT stores the current directory for drive N in the magic environment */ + /* variable =N: so we simply look for that environment variable. */ + char envname[4]; + + envname[0] = '='; + envname[1] = drive - 1 + 'A'; + envname[2] = ':'; + envname[3] = '\0'; + if (GetEnvironmentVariable(envname,dir,len) == 0) { + /* The current directory or the drive has not been set yet, so */ + /* simply set it to the root. */ + dir[0] = envname[1]; + dir[1] = ':'; + dir[2] = '\\'; + dir[3] = '\0'; + SetEnvironmentVariable(envname,dir); + } +} + +/**************************************************************************** +REMARKS: +Function to change the file attributes for a specific file. +****************************************************************************/ +void PMAPI PM_setFileAttr( + const char *filename, + uint attrib) +{ + DWORD attr = 0; + + if (attrib & PM_FILE_READONLY) + attr |= FILE_ATTRIBUTE_READONLY; + if (attrib & PM_FILE_ARCHIVE) + attr |= FILE_ATTRIBUTE_ARCHIVE; + if (attrib & PM_FILE_HIDDEN) + attr |= FILE_ATTRIBUTE_HIDDEN; + if (attrib & PM_FILE_SYSTEM) + attr |= FILE_ATTRIBUTE_SYSTEM; + SetFileAttributes((LPSTR)filename, attr); +} + +/**************************************************************************** +REMARKS: +Function to get the file attributes for a specific file. +****************************************************************************/ +uint PMAPI PM_getFileAttr( + const char *filename) +{ + DWORD attr = GetFileAttributes(filename); + uint attrib = 0; + + if (attr & FILE_ATTRIBUTE_READONLY) + attrib |= PM_FILE_READONLY; + if (attr & FILE_ATTRIBUTE_ARCHIVE) + attrib |= PM_FILE_ARCHIVE; + if (attr & FILE_ATTRIBUTE_HIDDEN) + attrib |= PM_FILE_HIDDEN; + if (attr & FILE_ATTRIBUTE_SYSTEM) + attrib |= PM_FILE_SYSTEM; + return attrib; +} + +/**************************************************************************** +REMARKS: +Function to create a directory. +****************************************************************************/ +ibool PMAPI PM_mkdir( + const char *filename) +{ + return CreateDirectory(filename,NULL); +} + +/**************************************************************************** +REMARKS: +Function to remove a directory. +****************************************************************************/ +ibool PMAPI PM_rmdir( + const char *filename) +{ + return RemoveDirectory(filename); +} + +/**************************************************************************** +REMARKS: +Function to get the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_getFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + HFILE f; + OFSTRUCT of; + FILETIME utcTime,localTime; + SYSTEMTIME sysTime; + ibool status = false; + + of.cBytes = sizeof(of); + if ((f = OpenFile(filename,&of,OF_READ)) == HFILE_ERROR) + return false; + if (!GetFileTime((HANDLE)f,NULL,NULL,&utcTime)) + goto Exit; + if (!gmTime) { + if (!FileTimeToLocalFileTime(&utcTime,&localTime)) + goto Exit; + } + else + localTime = utcTime; + if (!FileTimeToSystemTime(&localTime,&sysTime)) + goto Exit; + time->year = sysTime.wYear; + time->mon = sysTime.wMonth-1; + time->day = sysTime.wYear; + time->hour = sysTime.wHour; + time->min = sysTime.wMinute; + time->sec = sysTime.wSecond; + status = true; + +Exit: + CloseHandle((HANDLE)f); + return status; +} + +/**************************************************************************** +REMARKS: +Function to set the file time and date for a specific file. +****************************************************************************/ +ibool PMAPI PM_setFileTime( + const char *filename, + ibool gmTime, + PM_time *time) +{ + HFILE f; + OFSTRUCT of; + FILETIME utcTime,localTime; + SYSTEMTIME sysTime; + ibool status = false; + + of.cBytes = sizeof(of); + if ((f = OpenFile(filename,&of,OF_WRITE)) == HFILE_ERROR) + return false; + sysTime.wYear = time->year; + sysTime.wMonth = time->mon+1; + sysTime.wYear = time->day; + sysTime.wHour = time->hour; + sysTime.wMinute = time->min; + sysTime.wSecond = time->sec; + if (!SystemTimeToFileTime(&sysTime,&localTime)) + goto Exit; + if (!gmTime) { + if (!LocalFileTimeToFileTime(&localTime,&utcTime)) + goto Exit; + } + else + utcTime = localTime; + if (!SetFileTime((HANDLE)f,NULL,NULL,&utcTime)) + goto Exit; + status = true; + +Exit: + CloseHandle((HANDLE)f); + return status; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c b/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c new file mode 100644 index 000000000..70491cdb8 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/vflat.c @@ -0,0 +1,53 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Dummy module; no virtual framebuffer for this OS +* +****************************************************************************/ + +#include "pmapi.h" + +ibool PMAPI VF_available(void) +{ + return false; +} + +void * PMAPI VF_init( + ulong baseAddr, + int bankSize, + int codeLen, + void *bankFunc) +{ + (void)baseAddr; + (void)bankSize; + (void)codeLen; + (void)bankFunc; + return NULL; +} + +void PMAPI VF_exit(void) +{ +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c new file mode 100644 index 000000000..5a901a442 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/win32/ztimer.c @@ -0,0 +1,136 @@ +/**************************************************************************** +* +* Ultra Long Period Timer +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Win32 +* +* Description: OS specific implementation for the Zen Timer functions. +* +****************************************************************************/ + +/*---------------------------- Global variables ---------------------------*/ + +static CPU_largeInteger countFreq; +static ibool havePerformanceCounter; +static ulong start,finish; + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Initialise the Zen Timer module internals. +****************************************************************************/ +void __ZTimerInit(void) +{ +#ifdef NO_ASSEMBLER + havePerformanceCounter = false; +#else + havePerformanceCounter = QueryPerformanceFrequency((LARGE_INTEGER*)&countFreq); +#endif +} + +/**************************************************************************** +REMARKS: +Start the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOn( + LZTimerObject *tm) +{ + if (havePerformanceCounter) + QueryPerformanceCounter((LARGE_INTEGER*)&tm->start); + else + tm->start.low = timeGetTime(); +} + +/**************************************************************************** +REMARKS: +Compute the lap time since the timer was started. +****************************************************************************/ +static ulong __LZTimerLap( + LZTimerObject *tm) +{ + CPU_largeInteger tmLap,tmCount; + + if (havePerformanceCounter) { + QueryPerformanceCounter((LARGE_INTEGER*)&tmLap); + _CPU_diffTime64(&tm->start,&tmLap,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); + } + else { + tmLap.low = timeGetTime(); + return (tmLap.low - tm->start.low) * 1000L; + } +} + +/**************************************************************************** +REMARKS: +Stop the Zen Timer counting. +****************************************************************************/ +static void __LZTimerOff( + LZTimerObject *tm) +{ + if (havePerformanceCounter) + QueryPerformanceCounter((LARGE_INTEGER*)&tm->end); + else + tm->end.low = timeGetTime(); +} + +/**************************************************************************** +REMARKS: +Compute the elapsed time in microseconds between start and end timings. +****************************************************************************/ +static ulong __LZTimerCount( + LZTimerObject *tm) +{ + CPU_largeInteger tmCount; + + if (havePerformanceCounter) { + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,countFreq.low); + } + else + return (tm->end.low - tm->start.low) * 1000L; +} + +/**************************************************************************** +REMARKS: +Define the resolution of the long period timer as microseconds per timer tick. +****************************************************************************/ +#define ULZTIMER_RESOLUTION 1000 + +/**************************************************************************** +REMARKS: +Read the Long Period timer from the OS +****************************************************************************/ +static ulong __ULZReadTime(void) +{ return timeGetTime(); } + +/**************************************************************************** +REMARKS: +Compute the elapsed time from the BIOS timer tick. Note that we check to see +whether a midnight boundary has passed, and if so adjust the finish time to +account for this. We cannot detect if more that one midnight boundary has +passed, so if this happens we will be generating erronous results. +****************************************************************************/ +ulong __ULZElapsedTime(ulong start,ulong finish) +{ return finish - start; } diff --git a/board/MAI/bios_emulator/scitech/src/pm/x11/event.c b/board/MAI/bios_emulator/scitech/src/pm/x11/event.c new file mode 100644 index 000000000..b34bfac22 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/x11/event.c @@ -0,0 +1,307 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Unix / X11 +* +* Description: X11 event queue implementation for the MGL. +* This can be used both for windowed and fullscreen (DGA) modes. +* +****************************************************************************/ + +/*---------------------------- Global Variables ---------------------------*/ + +static ushort keyUpMsg[256] = {0};/* Table of key up messages */ +static int rangeX,rangeY; /* Range of mouse coordinates */ + +static Display *_EVT_dpy; +static Window _EVT_win; + +typedef struct { + int keycode; + int scancode; +} xkeymap; + +xkeymap xkeymaps[] = { + { 9, KB_esc}, + {24, KB_Q}, + {25, KB_W}, + {26, KB_E}, + {27, KB_R}, + {28, KB_T}, + {29, KB_Y}, + {30, KB_U}, + {31, KB_I}, + {32, KB_O}, + {33, KB_P}, +}; + +/*---------------------------- Implementation -----------------------------*/ + +/* These are not used under non-DOS systems */ +#define _EVT_disableInt() 1 +#define _EVT_restoreInt(flags) + +/**************************************************************************** +PARAMETERS: +scanCode - Scan code to test + +REMARKS: +This macro determines if a specified key is currently down at the +time that the call is made. +****************************************************************************/ +#define _EVT_isKeyDown(scanCode) (keyUpMsg[scanCode] != 0) + +/**************************************************************************** +REMARKS: +This function is used to return the number of ticks since system +startup in milliseconds. This should be the same value that is placed into +the time stamp fields of events, and is used to implement auto mouse down +events. +****************************************************************************/ +ulong _EVT_getTicks(void) +{ + static unsigned starttime = 0; + struct timeval t; + + gettimeofday(&t, NULL); + if (starttime == 0) + starttime = t.tv_sec * 1000 + (t.tv_usec/1000); + return ((t.tv_sec * 1000 + (t.tv_usec/1000)) - starttime); +} + +static int getScancode(int keycode) +{ + return keycode-8; +} + +/**************************************************************************** +REMARKS: +Pumps all messages in the application message queue into our event queue. +****************************************************************************/ +#ifdef X11_CORE +static void _EVT_pumpX11Messages(void) +#else +static void _EVT_pumpMessages(void) +#endif +{ + /* TODO: The purpose of this function is to read all keyboard and mouse */ + /* events from the OS specific event queue, translate them and post */ + /* them into the SciTech event queue. */ + event_t evt; + XEvent ev; + static int old_mx = 0, old_my = 0, buts = 0, c; + char buf[2]; + + while (XPending(_EVT_dpy) && XNextEvent(_EVT_dpy,&ev)) { + evt.when = _MGL_getTicks(); + + switch(ev.type){ + case KeyPress: + c = getScancode(ev.xkey.keycode); + evt.what = EVT_KEYDOWN; + evt.message = c << 8; + XLookupString(&ev.xkey, buf, 2, NULL, NULL); + evt.message |= buf[0]; + break; + case KeyRelease: + c = getScancode(ev.xkey.keycode); + evt.what = EVT_KEYUP; + evt.message = keyUpMsg[c]; + if(count < EVENTQSIZE) + addEvent(&evt); + keyUpMsg[c] = 0; + repeatKey[c] = 0; + break; + case ButtonPress: + evt.what = EVT_MOUSEDOWN; + if(ev.xbutton.button == 1){ + buts |= EVT_LEFTBUT; + evt.message = EVT_LEFTBMASK; + }else if(ev.xbutton.button == 2){ + buts |= EVT_MIDDLEBUT; + evt.message = EVT_MIDDLEBMASK; + }else if(ev.xbutton.button == 3){ + buts |= EVT_RIGHTBUT; + evt.message = EVT_RIGHTBMASK; + } + evt.modifiers = modifiers | buts; + + break; + case ButtonRelease: + evt.what = EVT_MOUSEUP; + if(ev.xbutton.button == 1){ + buts &= ~EVT_LEFTBUT; + evt.message = EVT_LEFTBMASK; + }else if(ev.xbutton.button == 2){ + buts &= ~EVT_MIDDLEBUT; + evt.message = EVT_MIDDLEBMASK; + }else if(ev.xbutton.button == 3){ + buts &= ~EVT_RIGHTBUT; + evt.message = EVT_RIGHTBMASK; + } + evt.modifiers = modifiers | buts; + + break; + case MotionNotify: + evt.what = EVT_MOUSEMOVE; + evt.where_x = ev.xmotion.x; + evt.where_y = ev.xmotion.y; + evt.relative_x = evt.where_x - old_mx; + evt.relative_y = evt.where_y - old_my; + old_mx = evt.where_x; + old_my = evt.where_y; + break; + } + if (count < EVENTQSIZE) + addEvent(&evt); + } + +} + +/**************************************************************************** +REMARKS: +This macro/function is used to converts the scan codes reported by the +keyboard to our event libraries normalised format. We only have one scan +code for the 'A' key, and use shift modifiers to determine if it is a +Ctrl-F1, Alt-F1 etc. The raw scan codes from the keyboard work this way, +but the OS gives us 'cooked' scan codes, we have to translate them back +to the raw format. +****************************************************************************/ +#define _EVT_maskKeyCode(evt) + +/**************************************************************************** +REMARKS: +Safely abort the event module upon catching a fatal error. +****************************************************************************/ +void _EVT_abort() +{ + EVT_exit(); + PM_fatalError("Unhandled exception!"); +} + +/**************************************************************************** +PARAMETERS: +mouseMove - Callback function to call wheneve the mouse needs to be moved + +REMARKS: +Initiliase the event handling module. Here we install our mouse handling ISR +to be called whenever any button's are pressed or released. We also build +the free list of events in the event queue. + +We use handler number 2 of the mouse libraries interrupt handlers for our +event handling routines. +****************************************************************************/ +#ifdef X11_CORE +void EVTAPI EVT_initX11( +#else +void EVTAPI EVT_init( +#endif + _EVT_mouseMoveHandler mouseMove) +{ + int result, i,j,k; + XDeviceInfoPtr list,slist; + + /* Initialise the event queue */ + _mouseMove = mouseMove; + initEventQueue(); + memset(keyUpMsg,0,sizeof(keyUpMsg)); + + + /* query server for input extensions */ + result =XQueryExtension(_EVT_dpy,"XInputExtension",&i,&j,&k); + if(!result) { + fprintf(stderr,"Your server doesn't support XInput Extensions\n"); + fprintf(stderr,"X11 Joystick disabled\n"); + } + list = XListInputDevices(_EVT_dpy,&result); + if (!list) { + fprintf(stderr,"No extended input devices found !!\n"); + fprintf(stderr,"X11 Joystick disabled\n"); + } + + + /* Catch program termination signals so we can clean up properly */ + signal(SIGABRT, _EVT_abort); + signal(SIGFPE, _EVT_abort); + signal(SIGINT, _EVT_abort); +} + +/**************************************************************************** +REMARKS +Changes the range of coordinates returned by the mouse functions to the +specified range of values. This is used when changing between graphics +modes set the range of mouse coordinates for the new display mode. +****************************************************************************/ +void EVTAPI EVT_setMouseRange( + int xRes, + int yRes) +{ + rangeX = xRes; + rangeY = yRes; +} + +/**************************************************************************** +REMARKS: +Initiailises the internal event handling modules. The EVT_suspend function +can be called to suspend event handling (such as when shelling out to DOS), +and this function can be used to resume it again later. +****************************************************************************/ +void EVT_resume(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Suspends all of our event handling operations. This is also used to +de-install the event handling code. +****************************************************************************/ +void EVT_suspend(void) +{ + /* Do nothing for non DOS systems */ +} + +/**************************************************************************** +REMARKS +Exits the event module for program terminatation. +****************************************************************************/ +void EVT_exit(void) +{ + /* Restore signal handlers */ + signal(SIGABRT, SIG_DFL); + signal(SIGFPE, SIG_DFL); + signal(SIGINT, SIG_DFL); + + /* TODO: Do any OS specific cleanup in here */ +} + +/**************************************************************************** +REMARKS +Sets the current X11 display +****************************************************************************/ +void EVT_setX11Display(Display *dpy, Window win) +{ + _EVT_dpy = dpy; + _EVT_win = win; +} diff --git a/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h b/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h new file mode 100644 index 000000000..45d7451be --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/x11/oshdr.h @@ -0,0 +1,38 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: BeOS +* +* Description: Include file to include all OS specific header files. +* +****************************************************************************/ + +#include +#include +#include +#include +#ifdef USE_OS_JOYSTICK +#include +#include +#endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj b/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj new file mode 100644 index 000000000..b62579818 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/z_samples.vpj @@ -0,0 +1,74 @@ +[SciTech] +compiler=wc10- +targetos=d32 +[COMPILER] +version=5.0b +MACRO=enable_current_compiler\n +activeconfig=,getch.exe +FILTERNAME=Source Files\n +FILTERPATTERN=*.c;*.cpp;*.cxx;*.prg;*.pas;*.dpr;*.bas;*.java;*.sc;*.e;*.cob;*.html;*.rc\n +FILTERASSOCIATEFILETYPES=0 +FILTERAPPCOMMAND=\n +vcsproject=SCC:Perforce SCM://depot +vcslocalpath=SCC:Perforce SCM:c:\ +compile=concur|capture|:Compile:&Compile,dmake %n.obj +make=concur|capture|clear|saveall|:Build:&Build,dmake %b +rebuild=concur|capture|clear|saveall|:Rebuild:&Rebuild,dmake -u %b +debug=concur|capture|savenone|nochangedir|:Debug:&Debug,wdn %b +execute=hide|savenone|nochangedir|:Execute:E&xecute, +user1=hide|nochangedir|:User 1:User 1, +user2=hide|nochangedir|:User 2:User 2, +usertool_build_all=concur|capture|clear|savenone|:Build All:Build All,dmake all +usertool_rebuild_all=concur|capture|clear|savenone|:Rebuild All:Rebuild All,dmake -u all +usertool_clean_directory=concur|capture|savenone|:Clean Directory:&Clean Directory,dmake cleanexe +workingdir=. +includedirs=%(SCITECH)\include;%(PRIVATE)\include +reffile= +[FILES] +tests\altbrk.c +tests\altcrit.c +tests\biosptr.c +tests\block.c +tests\brk.c +tests\callreal.c +tests\checks.c +tests\cpu.c +tests\critical.c +tests\getch.c +tests\isvesa.c +tests\key.c +tests\key15.c +tests\memtest.c +tests\mouse.c +tests\rtc.c +tests\showpci.c +tests\tick.c +tests\timerc.c +tests\timercpp.cpp +tests\uswc.c +tests\vftest.c +tests\video.c +[ASSOCIATION] +[CONFIGURATIONS] +config=,altbrk.exe +config=,altcrit.exe +config=,biosptr.exe +config=,block.exe +config=,brk.exe +config=,callreal.exe +config=,cpu.exe +config=,critical.exe +config=,getch.exe +config=,isvesa.exe +config=,key.exe +config=,key15.exe +config=,memtest.exe +config=,mouse.exe +config=,rtc.exe +config=,showpci.exe +config=,tick.exe +config=,timerc.exe +config=,timercpp.exe +config=,uswc.exe +config=,vftest.exe +config=,video.exe diff --git a/board/MAI/bios_emulator/scitech/src/pm/ztimer.c b/board/MAI/bios_emulator/scitech/src/pm/ztimer.c new file mode 100644 index 000000000..5acf7b1f0 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/pm/ztimer.c @@ -0,0 +1,516 @@ +/**************************************************************************** +* +* SciTech OS Portability Manager Library +* +* ======================================================================== +* +* The contents of this file are subject to the SciTech MGL Public +* License Version 1.0 (the "License"); you may not use this file +* except in compliance with the License. You may obtain a copy of +* the License at http://www.scitechsoft.com/mgl-license.txt +* +* Software distributed under the License is distributed on an +* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or +* implied. See the License for the specific language governing +* rights and limitations under the License. +* +* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc. +* +* The Initial Developer of the Original Code is SciTech Software, Inc. +* All Rights Reserved. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* +* Description: Module to implement high precision timing on each OS. +* +****************************************************************************/ + +#include "ztimer.h" +#include "pmapi.h" +#include "oshdr.h" + +/*---------------------------- Global variables ---------------------------*/ + +static LZTimerObject LZTimer; +static ulong start,finish; +#ifdef __INTEL__ +static long cpuSpeed = -1; +static ibool haveRDTSC = false; +#endif + +/*----------------------------- Implementation ----------------------------*/ + +/* External Intel assembler functions */ +#ifdef __INTEL__ +/* {secret} */ +void _ASMAPI _CPU_readTimeStamp(CPU_largeInteger *time); +/* {secret} */ +ulong _ASMAPI _CPU_diffTime64(CPU_largeInteger *t1,CPU_largeInteger *t2,CPU_largeInteger *t); +/* {secret} */ +ulong _ASMAPI _CPU_calcMicroSec(CPU_largeInteger *count,ulong freq); +#endif + +#if defined(__SMX32__) +#include "smx/ztimer.c" +#elif defined(__RTTARGET__) +#include "rttarget/ztimer.c" +#elif defined(__REALDOS__) +#include "dos/ztimer.c" +#elif defined(__NT_DRIVER__) +#include "ntdrv/ztimer.c" +#elif defined(__WIN32_VXD__) +#include "vxd/ztimer.c" +#elif defined(__WINDOWS32__) +#include "win32/ztimer.c" +#elif defined(__OS2_VDD__) +#include "vdd/ztimer.c" +#elif defined(__OS2__) +#include "os2/ztimer.c" +#elif defined(__LINUX__) +#include "linux/ztimer.c" +#elif defined(__QNX__) +#include "qnx/ztimer.c" +#elif defined(__BEOS__) +#include "beos/ztimer.c" +#else +#error Timer library not ported to this platform yet! +#endif + +/*------------------------ Public interface routines ----------------------*/ + +/**************************************************************************** +DESCRIPTION: +Initializes the Zen Timer library (extended) + +PARAMETERS: +accurate - True of the speed should be measured accurately + +HEADER: +ztimer.h + +REMARKS: +This function initializes the Zen Timer library, and /must/ be called before +any of the remaining Zen Timer library functions are called. The accurate +parameter is used to determine whether highly accurate timing should be +used or not. If high accuracy is needed, more time is spent profiling the +actual speed of the CPU so that we can obtain highly accurate timing +results, but the time spent in the initialisation routine will be +significantly longer (on the order of 5 seconds). +****************************************************************************/ +void ZAPI ZTimerInitExt( + ibool accurate) +{ + if (cpuSpeed == -1) { + __ZTimerInit(); +#ifdef __INTEL__ + cpuSpeed = CPU_getProcessorSpeedInHZ(accurate); + haveRDTSC = CPU_haveRDTSC() && (cpuSpeed > 0); +#endif + } +} + +/**************************************************************************** +DESCRIPTION: +Initializes the Zen Timer library. + +HEADER: +ztimer.h + +REMARKS: +This function initializes the Zen Timer library, and /must/ be called before +any of the remaining Zen Timer library functions are called. +****************************************************************************/ +void ZAPI ZTimerInit(void) +{ + ZTimerInitExt(false); +} + +/**************************************************************************** +DESCRIPTION: +Starts the Long Period Zen Timer counting. + +HEADER: +ztimer.h + +PARAMETERS: +tm - Timer object to start timing with + +REMARKS: +Starts the Long Period Zen Timer counting. Once you have started the timer, +you can stop it with LZTimerOff or you can latch the current count with +LZTimerLap. + +The Long Period Zen Timer uses a number of different high precision timing +mechanisms to obtain microsecond accurate timings results whenever possible. +The following different techniques are used depending on the operating +system, runtime environment and CPU on the target machine. If the target +system has a Pentium CPU installed which supports the Read Time Stamp +Counter instruction (RDTSC), the Zen Timer library will use this to +obtain the maximum timing precision available. + +Under 32-bit Windows, if the Pentium RDTSC instruction is not available, we +first try to use the Win32 QueryPerformanceCounter API, and if that is not +available we fall back on the timeGetTime API which is always supported. + +Under 32-bit DOS, if the Pentium RDTSC instruction is not available, we +then do all timing using the old style 8253 timer chip. The 8253 timer +routines provide highly accurate timings results in pure DOS mode, however +in a DOS box under Windows or other Operating Systems the virtualization +of the timer can produce inaccurate results. + +Note: Because the Long Period Zen Timer stores the results in a 32-bit + unsigned integer, you can only time periods of up to 2^32 microseconds, + or about 1hr 20mins. For timing longer periods use the Ultra Long + Period Zen Timer. + +SEE ALSO: +LZTimerOff, LZTimerLap, LZTimerCount +****************************************************************************/ +void ZAPI LZTimerOnExt( + LZTimerObject *tm) +{ +#ifdef __INTEL__ + if (haveRDTSC) { + _CPU_readTimeStamp(&tm->start); + } + else +#endif + __LZTimerOn(tm); +} + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Long Period Zen Timer and keeps it +running. + +HEADER: +ztimer.h + +PARAMETERS: +tm - Timer object to do lap timing with + +RETURNS: +Count that has elapsed in microseconds. + +REMARKS: +Returns the current count that has elapsed since the last call to +LZTimerOn in microseconds. The time continues to run after this function is +called so you can call this function repeatedly. + +SEE ALSO: +LZTimerOn, LZTimerOff, LZTimerCount +****************************************************************************/ +ulong ZAPI LZTimerLapExt( + LZTimerObject *tm) +{ +#ifdef __INTEL__ + CPU_largeInteger tmLap,tmCount; + + if (haveRDTSC) { + _CPU_readTimeStamp(&tmLap); + _CPU_diffTime64(&tm->start,&tmLap,&tmCount); + return _CPU_calcMicroSec(&tmCount,cpuSpeed); + } + else +#endif + return __LZTimerLap(tm); +} + +/**************************************************************************** +DESCRIPTION: +Stops the Long Period Zen Timer counting. + +HEADER: +ztimer.h + +PARAMETERS: +tm - Timer object to stop timing with + +REMARKS: +Stops the Long Period Zen Timer counting and latches the count. Once you +have stopped the timer you can read the count with LZTimerCount. If you need +highly accurate timing, you should use the on and off functions rather than +the lap function since the lap function does not subtract the overhead of +the function calls from the timed count. + +SEE ALSO: +LZTimerOn, LZTimerLap, LZTimerCount +****************************************************************************/ +void ZAPI LZTimerOffExt( + LZTimerObject *tm) +{ +#ifdef __INTEL__ + if (haveRDTSC) { + _CPU_readTimeStamp(&tm->end); + } + else +#endif + __LZTimerOff(tm); +} + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Long Period Zen Timer. + +HEADER: +ztimer.h + +PARAMETERS: +tm - Timer object to compute the elapsed time with. + +RETURNS: +Count that has elapsed in microseconds. + +REMARKS: +Returns the current count that has elapsed between calls to +LZTimerOn and LZTimerOff in microseconds. + +SEE ALSO: +LZTimerOn, LZTimerOff, LZTimerLap +****************************************************************************/ +ulong ZAPI LZTimerCountExt( + LZTimerObject *tm) +{ +#ifdef __INTEL__ + CPU_largeInteger tmCount; + + if (haveRDTSC) { + _CPU_diffTime64(&tm->start,&tm->end,&tmCount); + return _CPU_calcMicroSec(&tmCount,cpuSpeed); + } + else +#endif + return __LZTimerCount(tm); +} + +/**************************************************************************** +DESCRIPTION: +Starts the Long Period Zen Timer counting. + +HEADER: +ztimer.h + +REMARKS: +Obsolete function. You should use the LZTimerOnExt function instead +which allows for multiple timers running at the same time. +****************************************************************************/ +void ZAPI LZTimerOn(void) +{ LZTimerOnExt(&LZTimer); } + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Long Period Zen Timer and keeps it +running. + +HEADER: +ztimer.h + +RETURNS: +Count that has elapsed in microseconds. + +REMARKS: +Obsolete function. You should use the LZTimerLapExt function instead +which allows for multiple timers running at the same time. +****************************************************************************/ +ulong ZAPI LZTimerLap(void) +{ return LZTimerLapExt(&LZTimer); } + +/**************************************************************************** +DESCRIPTION: +Stops the Long Period Zen Timer counting. + +HEADER: +ztimer.h + +REMARKS: +Obsolete function. You should use the LZTimerOffExt function instead +which allows for multiple timers running at the same time. +****************************************************************************/ +void ZAPI LZTimerOff(void) +{ LZTimerOffExt(&LZTimer); } + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Long Period Zen Timer. + +HEADER: +ztimer.h + +RETURNS: +Count that has elapsed in microseconds. + +REMARKS: +Obsolete function. You should use the LZTimerCountExt function instead +which allows for multiple timers running at the same time. +****************************************************************************/ +ulong ZAPI LZTimerCount(void) +{ return LZTimerCountExt(&LZTimer); } + +/**************************************************************************** +DESCRIPTION: +Starts the Ultra Long Period Zen Timer counting. + +HEADER: +ztimer.h + +REMARKS: +Starts the Ultra Long Period Zen Timer counting. Once you have started the +timer, you can stop it with ULZTimerOff or you can latch the current count +with ULZTimerLap. + +The Ultra Long Period Zen Timer uses the available operating system services +to obtain accurate timings results with as much precision as the operating +system provides, but with enough granularity to time longer periods of +time than the Long Period Zen Timer. Note that the resolution of the timer +ticks is not constant between different platforms, and you should use the +ULZTimerResolution function to determine the number of seconds in a single +tick of the timer, and use this to convert the timer counts to seconds. + +Under 32-bit Windows, we use the timeGetTime function which provides a +resolution of 1 millisecond (0.001 of a second). Given that the timer +count is returned as an unsigned 32-bit integer, this we can time intervals +that are a maximum of 2^32 milliseconds in length (or about 1,200 hours or +50 days!). + +Under 32-bit DOS, we use the system timer tick which runs at 18.2 times per +second. Given that the timer count is returned as an unsigned 32-bit integer, +this we can time intervals that are a maximum of 2^32 * (1/18.2) in length +(or about 65,550 hours or 2731 days!). + +SEE ALSO: +ULZTimerOff, ULZTimerLap, ULZTimerCount, ULZElapsedTime, ULZReadTime +****************************************************************************/ +void ZAPI ULZTimerOn(void) +{ start = __ULZReadTime(); } + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Ultra Long Period Zen Timer and keeps it +running. + +HEADER: +ztimer.h + +RETURNS: +Count that has elapsed in resolution counts. + +REMARKS: +Returns the current count that has elapsed since the last call to +ULZTimerOn in microseconds. The time continues to run after this function is +called so you can call this function repeatedly. + +SEE ALSO: +ULZTimerOn, ULZTimerOff, ULZTimerCount +****************************************************************************/ +ulong ZAPI ULZTimerLap(void) +{ return (__ULZReadTime() - start); } + +/**************************************************************************** +DESCRIPTION: +Stops the Long Period Zen Timer counting. + +HEADER: +ztimer.h + +REMARKS: +Stops the Ultra Long Period Zen Timer counting and latches the count. Once +you have stopped the timer you can read the count with ULZTimerCount. + +SEE ALSO: +ULZTimerOn, ULZTimerLap, ULZTimerCount +****************************************************************************/ +void ZAPI ULZTimerOff(void) +{ finish = __ULZReadTime(); } + +/**************************************************************************** +DESCRIPTION: +Returns the current count for the Ultra Long Period Zen Timer. + +HEADER: +ztimer.h + +RETURNS: +Count that has elapsed in resolution counts. + +REMARKS: +Returns the current count that has elapsed between calls to +ULZTimerOn and ULZTimerOff in resolution counts. + +SEE ALSO: +ULZTimerOn, ULZTimerOff, ULZTimerLap, ULZTimerResolution +****************************************************************************/ +ulong ZAPI ULZTimerCount(void) +{ return (finish - start); } + +/**************************************************************************** +DESCRIPTION: +Reads the current time from the Ultra Long Period Zen Timer. + +HEADER: +ztimer.h + +RETURNS: +Current timer value in resolution counts. + +REMARKS: +Reads the current Ultra Long Period Zen Timer and returns it’s current +count. You can use the ULZElapsedTime function to find the elapsed time +between two timer count readings. + +SEE ALSO: +ULZElapsedTime, ULZTimerResolution +****************************************************************************/ +ulong ZAPI ULZReadTime(void) +{ return __ULZReadTime(); } + +/**************************************************************************** +DESCRIPTION: +Compute the elapsed time between two timer counts. + +HEADER: +ztimer.h + +PARAMETERS: +start - Starting time for elapsed count +finish - Ending time for elapsed count + +RETURNS: +Elapsed timer in resolution counts. + +REMARKS: +Returns the elapsed time for the Ultra Long Period Zen Timer in units of the +timers resolution (1/18th of a second under DOS). This function correctly +computes the difference even if a midnight boundary has been crossed +during the timing period. + +SEE ALSO: +ULZReadTime, ULZTimerResolution +****************************************************************************/ +ulong ZAPI ULZElapsedTime( + ulong start, + ulong finish) +{ return __ULZElapsedTime(start,finish); } + +/**************************************************************************** +DESCRIPTION: +Returns the resolution of the Ultra Long Period Zen Timer. + +HEADER: +ztimer.h + +PARAMETERS: +resolution - Place to store the timer in microseconds per timer count. + +REMARKS: +Returns the resolution of the Ultra Long Period Zen Timer as a 32-bit +integer value measured in microseconds per timer count. + +SEE ALSO: +ULZReadTime, ULZElapsedTime, ULZTimerCount +****************************************************************************/ +void ZAPI ULZTimerResolution( + ulong *resolution) +{ *resolution = ULZTIMER_RESOLUTION; } diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h b/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h new file mode 100644 index 000000000..77c545aef --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/AsmMacros.h @@ -0,0 +1,450 @@ +/* $XConsortium: AsmMacros.h /main/13 1996/10/25 11:33:12 kaleb $ */ +/* + * (c) Copyright 1993,1994 by David Wexelblat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID WEXELBLAT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of David Wexelblat shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from David Wexelblat. + * + */ +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * This software is furnished under license and may be used and copied only in + * accordance with the following terms and conditions. Subject to these + * conditions, you may download, copy, install, use, modify and distribute + * this software in source and/or binary form. No title or ownership is + * transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce and retain + * this copyright notice and list of conditions as they appear in the source + * file. + * + * 2) No right is granted to use any trade name, trademark, or logo of Digital + * Equipment Corporation. Neither the "Digital Equipment Corporation" name + * nor any trademark or logo of Digital Equipment Corporation may be used + * to endorse or promote products derived from this software without the + * prior written permission of Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied warranties, + * including but not limited to, any implied warranties of merchantability, + * fitness for a particular purpose, or non-infringement are disclaimed. In + * no event shall DIGITAL be liable for any damages whatsoever, and in + * particular, DIGITAL shall not be liable for special, indirect, + * consequential, or incidental damages or damages for + * lost profits, loss of revenue or loss of use, whether such damages arise + * in contract, + * negligence, tort, under statute, in equity, at law or otherwise, even if + * advised of the possibility of such damage. + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/SuperProbe/AsmMacros.h,v 3.14 1999/09/25 14:36:58 dawes Exp $ */ + +#if defined(__GNUC__) +#if defined(linux) && (defined(__alpha__) || defined(__ia64__)) +#undef inb +#define inb _inb +#undef inw +#define inw _inw +#undef inl +#define inl _inl +#undef outb +#define outb(p,v) _outb((v),(p)) +#undef outw +#define outw(p,v) _outw((v),(p)) +#undef outl +#define outl(p,v) _outl((v),(p)) +#else +#if defined(__sparc__) +#ifndef ASI_PL +#define ASI_PL 0x88 +#endif + +static __inline__ void +outb(port, val) +unsigned long port; +char val; +{ + __asm__ __volatile__("stba %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ void +outw(port, val) +unsigned long port; +char val; +{ + __asm__ __volatile__("stha %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ void +outl(port, val) +unsigned long port; +char val; +{ + __asm__ __volatile__("sta %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ unsigned int +inb(port) +unsigned long port; +{ + unsigned char ret; + __asm__ __volatile__("lduba [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int +inw(port) +unsigned long port; +{ + unsigned char ret; + __asm__ __volatile__("lduha [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int +inl(port) +unsigned long port; +{ + unsigned char ret; + __asm__ __volatile__("lda [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} +#else +#ifdef __arm32__ +unsigned int IOPortBase; /* Memory mapped I/O port area */ + +static __inline__ void +outb(port, val) + short port; + char val; +{ + if ((unsigned short)port >= 0x400) return; + + *(volatile unsigned char*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ void +outw(port, val) + short port; + short val; +{ + if ((unsigned short)port >= 0x400) return; + + *(volatile unsigned short*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ void +outl(port, val) + short port; + int val; +{ + if ((unsigned short)port >= 0x400) return; + + *(volatile unsigned long*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ unsigned int +inb(port) + short port; +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + + return(*(volatile unsigned char*)(((unsigned short)(port))+IOPortBase)); +} + +static __inline__ unsigned int +inw(port) + short port; +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + + return(*(volatile unsigned short*)(((unsigned short)(port))+IOPortBase)); +} + +static __inline__ unsigned int +inl(port) + short port; +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + + return(*(volatile unsigned long*)(((unsigned short)(port))+IOPortBase)); +} +#else /* __arm32__ */ +#if defined(Lynx) && defined(__powerpc__) +extern unsigned char *ioBase; + +static volatile void +eieio() +{ + __asm__ __volatile__ ("eieio"); +} + +static void +outb(port, value) +short port; +unsigned char value; +{ + *(uchar *)(ioBase + port) = value; eieio(); +} + +static void +outw(port, value) +short port; +unsigned short value; +{ + *(unsigned short *)(ioBase + port) = value; eieio(); +} + +static void +outl(port, value) +short port; +unsigned long value; +{ + *(unsigned long *)(ioBase + port) = value; eieio(); +} + +static unsigned char +inb(port) +short port; +{ + unsigned char val; + + val = *((unsigned char *)(ioBase + port)); eieio(); + return(val); +} + +static unsigned short +inw(port) +short port; +{ + unsigned short val; + + val = *((unsigned short *)(ioBase + port)); eieio(); + return(val); +} + +static unsigned long +inl(port) +short port; +{ + unsigned long val; + + val = *((unsigned long *)(ioBase + port)); eieio(); + return(val); +} + +#else +#if defined(__FreeBSD__) && defined(__alpha__) + +#include + +extern void outb(u_int32_t port, u_int8_t val); +extern void outw(u_int32_t port, u_int16_t val); +extern void outl(u_int32_t port, u_int32_t val); +extern u_int8_t inb(u_int32_t port); +extern u_int16_t inw(u_int32_t port); +extern u_int32_t inl(u_int32_t port); + +#else +#ifdef GCCUSESGAS +static __inline__ void +outb(port, val) +short port; +char val; +{ + __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ void +outw(port, val) +short port; +short val; +{ + __asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ void +outl(port, val) +short port; +unsigned int val; +{ + __asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port)); +} + +static __inline__ unsigned int +inb(port) +short port; +{ + unsigned char ret; + __asm__ __volatile__("inb %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inw(port) +short port; +{ + unsigned short ret; + __asm__ __volatile__("inw %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inl(port) +short port; +{ + unsigned int ret; + __asm__ __volatile__("inl %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +#else /* GCCUSESGAS */ + +static __inline__ void +outb(port, val) + short port; + char val; +{ + __asm__ __volatile__("out%B0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ void +outw(port, val) + short port; + short val; +{ + __asm__ __volatile__("out%W0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ void +outl(port, val) + short port; + unsigned int val; +{ + __asm__ __volatile__("out%L0 (%1)" : :"a" (val), "d" (port)); +} + +static __inline__ unsigned int +inb(port) + short port; +{ + unsigned int ret; + __asm__ __volatile__("in%B0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inw(port) + short port; +{ + unsigned int ret; + __asm__ __volatile__("in%W0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int +inl(port) + short port; +{ + unsigned int ret; + __asm__ __volatile__("in%L0 (%1)" : + "=a" (ret) : + "d" (port)); + return ret; +} + +#endif /* GCCUSESGAS */ +#endif /* Lynx && __powerpc__ */ +#endif /* arm32 */ +#endif /* linux && __sparc__ */ +#endif /* linux && __alpha__ */ +#endif /* __FreeBSD__ && __alpha__ */ + +#if defined(linux) || defined(__arm32__) || (defined(Lynx) && defined(__powerpc__)) + +#define intr_disable() +#define intr_enable() + +#else + +static __inline__ void +intr_disable() +{ + __asm__ __volatile__("cli"); +} + +static __inline__ void +intr_enable() +{ + __asm__ __volatile__("sti"); +} + +#endif /* else !linux && !__arm32__ */ + +#else /* __GNUC__ */ + +#if defined(_MINIX) && defined(_ACK) + +/* inb, outb, inw and outw are defined in the library */ +/* ... but I've no idea if the same is true for inl & outl */ + +u8_t inb(U16_t); +void outb(U16_t, U8_t); +u16_t inw(U16_t); +void outw(U16_t, U16_t); +u32_t inl(U16_t); +void outl(U16_t, U32_t); + +#else /* not _MINIX and _ACK */ + +# if defined(__STDC__) && (__STDC__ == 1) +# ifndef NCR +# define asm __asm +# endif +# endif +# ifdef SVR4 +# include +# ifndef __USLC__ +# define __USLC__ +# endif +# endif +#ifndef SCO325 +# include +#else +# include "../common/scoasm.h" +#endif +#define intr_disable() asm("cli") +#define intr_enable() asm("sti") + +#endif /* _MINIX and _ACK */ +#endif /* __GNUC__ */ diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/README b/board/MAI/bios_emulator/scitech/src/v86bios/README new file mode 100644 index 000000000..cb65674b2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/README @@ -0,0 +1,32 @@ + +This is a preliminary version of a VGA softbooter for LINUX. + +It makes use of the of the vm86() call and is therefore only +usable on ix86 systems. +There are plans to port this program to use a x86 emulator +like x86emu. Also it may be ported to other operating systems. + +So far it has been tested on a small number of cards. It might +well be that it will fail on your card. + +If you need to make modifications to the programs to be able +to boot your card please let the author know. + +So far there is no command line interface. All options need +to be hardcoded. You can do this by editing debug.h. You can +turn on a bunch of debug output. Other options allow you to +boot the primary card (CONFIG_ACTIVE_DEVICE), save the bios +to a file (SAVE_BIOS), and map the original system bios +(MAP_SYS_BIOS). + +The author wants to thank + Hans Lermen (dosemu) + and + Kendall Bennett (x86emu) +for their support. + +Parts of the code - especially in v86.c and io.c - are based on code +taken from dosemu. Parts of the code in int.c are based on code taken +from x86emu + +Egbert Eich. diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr b/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr new file mode 100644 index 000000000..9d2a80d7d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/awk.scr @@ -0,0 +1,15 @@ +/.*\(0x3da.*/||/.*\(0x3ba.*/ { + if (v_3da != 1) print "_v_retrace_"; + v_3da = 1; + next; + } +/.*\(0x42.*/||/.*\(0x43.*/ { + if (v_4x != 1) print "_timer_"; + v_4x = 1; + next; +} +{ + print; + v_3da = 0; + v_4x = 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c b/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c new file mode 100644 index 000000000..6b12dff4f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/cbios.c @@ -0,0 +1,415 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(__alpha__) || defined (__ia64__) +#include +#elif defined(HAVE_SYS_PERM) +#include +#endif +#include "debug.h" +#include "v86bios.h" +#include "pci.h" +#include "AsmMacros.h" + +#define SIZE 0x100000 +#define VRAM_START 0xA0000 +#define VRAM_SIZE 0x1FFFF +#define V_BIOS_SIZE 0x1FFFF +#define BIOS_START 0x7C00 /* default BIOS entry */ +#define BIOS_MEM 0x600 + +CARD8 code[] = { 0xcd, 0x10, 0xf4 }; +struct config Config; + +static int map(void); +static void unmap(void); +static void runBIOS(int argc, char **argv); +static int map_vram(void); +static void unmap_vram(void); +static int copy_vbios(memType base); +static int copy_sys_bios(void); +static CARD32 setup_int_vect(void); +static void update_bios_vars(void); +static int chksum(CARD8 *start); +static void setup_bios_regs(i86biosRegsPtr regs, int argc, char **argv); +static void print_regs(i86biosRegsPtr regs); +void dprint(unsigned long start, unsigned long size); + +void loadCodeToMem(unsigned char *ptr, CARD8 *code); + +static int vram_mapped = 0; +static char* bios_var; + + +int +main(int argc,char **argv) +{ + CARD32 vbios_base; + + Config.PrintPort = PRINT_PORT; + Config.IoStatistics = IO_STATISTICS; + Config.PrintIrq = PRINT_IRQ; + Config.PrintPci = PRINT_PCI; + Config.ShowAllDev = SHOW_ALL_DEV; + Config.PrintIp = PRINT_IP; + Config.SaveBios = SAVE_BIOS; + Config.Trace = TRACE; + Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY; + Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE; + Config.MapSysBios = MAP_SYS_BIOS; + Config.Resort = RESORT; + Config.FixRom = FIX_ROM; + Config.NoConsole = NO_CONSOLE; + Config.Verbose = VERBOSE; + + if (!map()) + exit(1); + if (!copy_sys_bios()) + exit(1); + if (!(vbios_base = setup_int_vect())) + exit(1); + if (!map_vram()) + exit(1); + if (!copy_vbios(vbios_base)) + exit(1); + + iopl(3); + setup_io(); + runBIOS(argc,argv); + update_bios_vars(); + unmap_vram(); + iopl(0); + unmap(); + printf("done !\n"); + exit (1); +} + +int +map(void) +{ + void* mem; + + mem = mmap(0, (size_t)SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, + MAP_FIXED | MAP_PRIVATE | MAP_ANON, + -1, 0 ); + if (mem != 0) { + perror("anonymous map"); + return (0); + } + memset(mem,0,SIZE); + + loadCodeToMem((unsigned char *) BIOS_START, code); + return (1); +} + +static int +copy_sys_bios(void) +{ +#define SYS_BIOS 0xF0000 + int mem_fd; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS) + goto Error; + if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF) + goto Error; + + close(mem_fd); + return (1); + +Error: + perror("sys_bios"); + close(mem_fd); + return (0); +} + +static int +map_vram(void) +{ + int mem_fd; + +#ifdef __ia64__ + if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) +#else + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) +#endif + { + perror("opening memory"); + return 0; + } + +#ifndef __alpha__ + if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, + mem_fd, VRAM_START) == (void *) -1) +#else + if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */ + if (!_bus_base_sparse()) sparse_shift = 0; + if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift), + PROT_READ | PROT_WRITE, + MAP_SHARED, + mem_fd, (VRAM_START << sparse_shift) + | _bus_base_sparse())) == (void *) -1) +#endif + { + perror("mmap error in map_hardware_ram"); + close(mem_fd); + return (0); + } + vram_mapped = 1; + close(mem_fd); + return (1); +} + +static int +copy_vbios(memType v_base) +{ + int mem_fd; + unsigned char *tmp; + int size; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) v_base, SEEK_SET) != (off_t) v_base) { + fprintf(stderr,"Cannot lseek\n"); + goto Error; + } + tmp = (unsigned char *)malloc(3); + if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + if (lseek(mem_fd,(off_t) v_base,SEEK_SET) != (off_t) v_base) + goto Error; + + if (*tmp != 0x55 || *(tmp+1) != 0xAA ) { + fprintf(stderr,"No bios found at: 0x%lx\n",v_base); + goto Error; + } +#ifdef DEBUG + dprint((unsigned long)tmp,0x100); +#endif + size = *(tmp+2) * 512; + + if (read(mem_fd, (char *)v_base, (size_t) size) != (size_t) size) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + free(tmp); + close(mem_fd); + if (!chksum((CARD8*)v_base)) + return (0); + + return (1); + +Error: + perror("v_bios"); + close(mem_fd); + return (0); +} + +static void +unmap(void) +{ + munmap(0,SIZE); +} + +static void +unmap_vram(void) +{ + if (!vram_mapped) return; + + munmap((void*)VRAM_START,VRAM_SIZE); + vram_mapped = 0; +} + +static void +runBIOS(int argc, char ** argv) +{ + i86biosRegs bRegs; +#ifdef V86BIOS_DEBUG + printf("starting BIOS\n"); +#endif + setup_bios_regs(&bRegs, argc, argv); + do_x86(BIOS_START,&bRegs); + print_regs(&bRegs); +#ifdef V86BIOS_DEBUG + printf("done\n"); +#endif +} + +static CARD32 +setup_int_vect(void) +{ + int mem_fd; + CARD32 vbase; + void *map; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if ((map = mmap((void *) 0, (size_t) 0x2000, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, + mem_fd, 0)) == (void *)-1) { + perror("mmap error in map_hardware_ram"); + close(mem_fd); + return (0); + } + + close(mem_fd); + memcpy(0,map,BIOS_MEM); + munmap(map,0x2000); + /* + * create a backup copy of the bios variables to write back the + * modified values + */ + bios_var = (char *)malloc(BIOS_MEM); + memcpy(bios_var,0,BIOS_MEM); + + vbase = (*((CARD16*)(0x10 << 2) + 1)) << 4; + fprintf(stderr,"vbase: 0x%x\n",vbase); + return vbase; +} + +static void +update_bios_vars(void) +{ + int mem_fd; + void *map; + memType i; + +#ifdef __ia64__ + if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) +#else + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) +#endif + { + perror("opening memory"); + return; + } + + if ((map = mmap((void *) 0, (size_t) 0x2000, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, + mem_fd, 0)) == (void *)-1) { + perror("mmap error in map_hardware_ram"); + close(mem_fd); + return; + } + + for (i = 0; i < BIOS_MEM; i++) { + if (bios_var[i] != *(CARD8*)i) + *((CARD8*)map + i) = *(CARD8*)i; + } + + munmap(map,0x2000); + close(mem_fd); +} + + +static void +setup_bios_regs(i86biosRegsPtr regs, int argc, char **argv) +{ + int c; + + regs->ax = 0; + regs->bx = 0; + regs->cx = 0; + regs->dx = 0; + regs->es = 0; + regs->di = 0; + opterr = 0; + while ((c = getopt(argc,argv,"a:b:c:d:e:i:")) != EOF) { + switch (c) { + case 'a': + regs->ax = strtol(optarg,NULL,0); + break; + case 'b': + regs->bx = strtol(optarg,NULL,0); + break; + case 'c': + regs->cx = strtol(optarg,NULL,0); + break; + case 'd': + regs->dx = strtol(optarg,NULL,0); + break; + case 'e': + regs->es = strtol(optarg,NULL,0); + break; + case 'i': + regs->di = strtol(optarg,NULL,0); + break; + } + } +} + + +static int +chksum(CARD8 *start) +{ + CARD16 size; + CARD8 val = 0; + int i; + + size = *(start+2) * 512; + for (i = 0; iax, + (CARD16)regs->bx,(CARD16)regs->cx,(CARD16)regs->dx, + (CARD16)regs->es,(CARD16)regs->di); +} + +void +loadCodeToMem(unsigned char *ptr, CARD8 code[]) +{ + int i; + CARD8 val; + + for ( i=0;;i++) { + val = code[i]; + *ptr++ = val; + if (val == 0xf4) break; + } + return; +} + +void +dprint(unsigned long start, unsigned long size) +{ + int i,j; + char *c = (char *)start; + + for (j = 0; j < (size >> 4); j++) { + printf ("\n0x%lx: ",(unsigned long)c); + for (i = 0; i<16; i++) + printf("%x ",(unsigned char) (*(c++))); + } + printf("\n"); +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/command.c b/board/MAI/bios_emulator/scitech/src/v86bios/command.c new file mode 100644 index 000000000..e2bce6df1 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/command.c @@ -0,0 +1,38 @@ +#include +#include +#include +#include + +#define PROMPT ">" + + +void +getline(char *buf,int *num,int max_num) +{ + static int line_len = 0; + static char *line = NULL; + static char *line_pointer = NULL; + static int len = 0; + int tmp_len; + char *buff; + + if (len <= 0) { + buff = readline(PROMPT); + add_history(buff); + + if ((tmp_len = strlen(buff)) > line_len) { + free(line); + line = malloc(tmp_len); + line_len = tmp_len; + } + sprintf(line,"%s\n",buff); + free(buff); + line_pointer = line; + len = strlen(line); + } + + *num = max_num > len? len : max_num; + strncpy(buf,line_pointer,*num); + line_pointer = line_pointer + *num; + len = len - *num; +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/console.c b/board/MAI/bios_emulator/scitech/src/v86bios/console.c new file mode 100644 index 000000000..5e9c924b6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/console.c @@ -0,0 +1,95 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include "debug.h" +#include "v86bios.h" + +console +open_console(void) +{ + int fd; + int VTno; + char VTname[11]; + console Con = {-1,-1}; + struct vt_stat vts; + + if (NO_CONSOLE) + return Con; + + if ((fd = open("/dev/tty0",O_WRONLY,0)) < 0) + return Con; + + if ((ioctl(fd, VT_OPENQRY, &VTno) < 0) || (VTno == -1)) { + fprintf(stderr,"cannot get a vt\n"); + return Con; + } + + close(fd); + sprintf(VTname,"/dev/tty%i",VTno); + + if ((fd = open(VTname, O_RDWR|O_NDELAY, 0)) < 0) { + fprintf(stderr,"cannot open console\n"); + return Con; + } + + if (ioctl(fd, VT_GETSTATE, &vts) == 0) + Con.vt = vts.v_active; + + if (ioctl(fd, VT_ACTIVATE, VTno) != 0) { + fprintf(stderr,"cannot activate console\n"); + close(fd); + return Con; + } + if (ioctl(fd, VT_WAITACTIVE, VTno) != 0) { + fprintf(stderr,"wait for active console failed\n"); + close(fd); + return Con; + } +#if 0 + if (ioctl(fd, KDSETMODE, KD_GRAPHICS) < 0) { + close(fd); + return Con; + } +#endif + Con.fd = fd; + return Con; +} + +void +close_console(console Con) +{ + if (Con.fd == -1) + return; + +#if 0 + ioctl(Con.fd, KDSETMODE, KD_TEXT); +#endif + if (Con.vt >=0) + ioctl(Con.fd, VT_ACTIVATE, Con.vt); + + close(Con.fd); +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/debug.h b/board/MAI/bios_emulator/scitech/src/v86bios/debug.h new file mode 100644 index 000000000..c5c906b62 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/debug.h @@ -0,0 +1,60 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +/*#define V86BIOS_DEBUG */ + +/* + * uncomment the following if needed + * should be command line options + */ + +#define PRINT_PORT 0 +#define IO_STATISTICS 0 +#define PRINT_IRQ 0 +#define PRINT_PCI 1 +#define PRINT_IP 0 /* print IP address with PIO information */ +#define TRACE 0 /* turn on debugger in x86emu */ + /* requires x86emu compiled with -DDEBUG */ + +/* + * these should not be here. + * Should be converted to command line options. + */ +#define CONFIG_ACTIVE_ONLY 0 +#define CONFIG_ACTIVE_DEVICE 1 +#define SAVE_BIOS 0 +#define MAP_SYS_BIOS 1 +#define RESORT 1 +#define FIX_ROM 0 +#define NO_CONSOLE 0 +#define SHOW_ALL_DEV 0 +#define VERBOSE 0 + +/*#define V_BIOS 0xe0000 */ +/*#define V_BIOS 0xe4000 */ + + +#if (PRINT_IO == 1) && (PRINT_PORT == 0) +# define PRINT_IO 0 +#endif +#if (IO_STATISTICS == 1) && (PRINT_PORT == 0) +# define IO_STATISTICS 0 +#endif diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards b/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards new file mode 100644 index 000000000..943d44ede --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/happy_cards @@ -0,0 +1,76 @@ +What I had to do to make cards happy: + +1. Tseng ET4000 W32P +This card wants to call the original system BIOS video routines. +It sets the int 0x42 vector to F000:F065, the entry point to the +system bios video routines. +CAVE: don't catch int 0x42 and use the vbios int 0x10 routines. +At early stage during initialization they call int 0x42. This +causes an infinite loop. + +2. ATi Mach64 Rage IIc AGP +This card does similar things like the Tseng ET4000 W32P. +However it doesn't have the problem with the ininite loop. + +3. Elsa Victory II-A16 AGP Banshee +This card is very clever: It knows it is an AGP card. Therefore +it knows it is behind a PCI-PCI bridge. It also knows that noone +else is behind this bridge. Therefore it start reprogramming the +bridge! For this it assumes the AGP bridge is on bus 1. + +4. Elsa Gloria Synergy 8 ViVo AGP PM2 +This card likes to see a complete interrupt vector table. If +we fill this table with 0 the VBIOS detects this and quits +initialization. + +5. Dimond Viper 330 AGP NVIDIA Riva 128. +This card has a similar problem like the Elsa Gloria. It wants +to read the system BIOS date at 0xffffd. + +6. Matrox Mystique PCI +This card reads the IO port 0x62. If it doesn't like what it sees +it loops forever. To keep the card happy put 0xfc into 0xffffe. +This location holds the system model id. 0xfc means IBM-AT. + One can make an interesting observation: this card likes to know +with whom it has to share the system. Therefore it accesses PCI +config space of all the other cards. It does this bypassing the +PCI BIOS by reading the PCI access ports directly. + +7. Matrox G100 AGP +This card has the same problem as the Mystique. + +Apperantly this works now. However not all combinations of cards are +checked, yet. + +Further notes: +the IO register 0x42-0x43 as well as 0x61-0x63 are of special interest +for many graphic cards. They should be emulated. +The so called "Industry Standard BIOS Entry Points" to int 0x42 (0xFF065) +and to int 0x1a (0xFFE6E) should be filled with useful code. This code +needs to return as if it was called as int. +The subvendor ID PCI registers might cause problems. On some chipsets +they are programmed in a non-obivous non-PCI conformant way. +V_Bioses are seen to modify the following int: +0x10 (default video), 0x1f(font table), 0x42(copy of default video), +0x43 (??), 0x6d (copy of default video - same as 0x10?) + +TODO: +Int 0x6d needs to be done. +All interrupts where there is no default industry standard entry point +should point to an unused location in the 0xF000 segmant (possibly +0xF0000). This way they could be trapped. A trap handler for +a. int 0x42 and int 0x1a needs to be implemented. +The default "industry entry point" for video and PCI (0xFFE6E) should +also be implemented. (any others?) They should either be routed to +int 0x42(0x6d?) (video) and 0x1A (PCI) or some other interrupts to +trap them. Mapping of system bios might not be a good idea. Maybe +the system bios area should just be filled with "hlt" to trap any +access there. +Handling of timer IO registers 0x42, 0x43 and IO registers 0x61, 0x62. + +Find documentation: +- on interrupt vector table +- on industry standard entry points to the system bios +- on IO registers 0x61 and 0x62 + + diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/hexdump b/board/MAI/bios_emulator/scitech/src/v86bios/hexdump new file mode 100644 index 000000000..4f359e5ed --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/hexdump @@ -0,0 +1,3 @@ +"%06.6_ax " 16/1 "%02x " +" " 16/1 "%_p" +"\n" diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/int.c b/board/MAI/bios_emulator/scitech/src/v86bios/int.c new file mode 100644 index 000000000..3504c6cc3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/int.c @@ -0,0 +1,238 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "debug.h" +#if defined(__alpha__) || defined (__ia64__) +#include +#endif + +#include "v86bios.h" +#include "AsmMacros.h" +#include "pci.h" + +static int int1A_handler(struct regs86 *regs); +static int int42_handler(int num, struct regs86 *regs); + +int +int_handler(int num, struct regs86 *regs) +{ + switch (num) { + case 0x10: + case 0x42: + return (int42_handler(num,regs)); + case 0x1A: + return (int1A_handler(regs)); + default: + return 0; + } + return 0; +} + +static int +int42_handler(int num,struct regs86 *regs) +{ + unsigned char c; + CARD32 val; + + i_printf("int 0x%x: ax:0x%lx bx:0x%lx cx:0x%lx dx:0x%lx\n",num, + regs->eax,regs->ebx, regs->ecx, regs->edx); + + /* + * video bios has modified these - + * leave it to the video bios to do this + */ + + val = getIntVect(num); + if (val != 0xF000F065) + return 0; + + if ((regs->ebx & 0xff) == 0x32) { + switch (regs->eax & 0xFFFF) { + case 0x1200: + i_printf("enabling video\n"); + c = inb(0x3cc); + c |= 0x02; + outb(0x3c2,c); + return 1; + case 0x1201: + i_printf("disabling video\n"); + c = inb(0x3cc); + c &= ~0x02; + outb(0x3c2,c); + return 1; + default: + } + } + if (num == 0x42) + return 1; + else + return 0; +} + +#define SUCCESSFUL 0x00 +#define DEVICE_NOT_FOUND 0x86 +#define BAD_REGISTER_NUMBER 0x87 + +static int +int1A_handler(struct regs86 *regs) +{ + CARD32 Slot; + PciStructPtr pPci; + + if (! CurrentPci) return 0; /* oops */ + + i_printf("int 0x1a: ax=0x%lx bx=0x%lx cx=0x%lx dx=0x%lx di=0x%lx" + " si=0x%lx\n", regs->eax,regs->ebx,regs->ecx,regs->edx, + regs->edi,regs->esi); + switch (regs->eax & 0xFFFF) { + case 0xb101: + regs->eax &= 0xFF00; /* no config space/special cycle support */ + regs->edx = 0x20494350; /* " ICP" */ + regs->ebx = 0x0210; /* Version 2.10 */ + regs->ecx &= 0xFF00; + regs->ecx |= (pciMaxBus & 0xFF); /* Max bus number in system */ + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + i_printf("ax=0x%lx dx=0x%lx bx=0x%lx cx=0x%lx flags=0x%lx\n", + regs->eax,regs->edx,regs->ebx,regs->ecx,regs->eflags); + return 1; + case 0xb102: + if (((regs->edx & 0xFFFF) == CurrentPci->VendorID) && + ((regs->ecx & 0xFFFF) == CurrentPci->DeviceID) && + (regs->esi == 0)) { + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + regs->ebx = pciSlotBX(CurrentPci); + } + else if (Config.ShowAllDev && + (pPci = findPciDevice(regs->edx,regs->ecx,regs->esi)) != NULL) { + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + regs->ebx = pciSlotBX(pPci); + } else { + regs->eax = (regs->eax & 0x00FF) | (DEVICE_NOT_FOUND << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx bx=0x%lx flags=0x%lx\n", + regs->eax,regs->ebx,regs->eflags); + return 1; + case 0xb103: + if (((regs->ecx & 0xFF) == CurrentPci->Interface) && + (((regs->ecx & 0xFF00) >> 8) == CurrentPci->SubClass) && + (((regs->ecx & 0xFFFF0000) >> 16) == CurrentPci->BaseClass) && + ((regs->esi & 0xff) == 0)) { + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->ebx = pciSlotBX(CurrentPci); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } + else if (Config.ShowAllDev + && (pPci = findPciClass(regs->ecx & 0xFF, (regs->ecx & 0xff00) >> 8, + (regs->ecx & 0xffff0000) >> 16, regs->esi)) != NULL) { + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->ebx = pciSlotBX(pPci); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (DEVICE_NOT_FOUND << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx flags=0x%lx\n",regs->eax,regs->eflags); + return 1; + case 0xb108: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + regs->ecx &= 0xFFFFFF00; + regs->ecx |= PciRead8(regs->edi,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n", + regs->eax,regs->ecx,regs->eflags); + return 1; + case 0xb109: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + regs->ecx &= 0xFFFF0000; + regs->ecx |= PciRead16(regs->edi,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n", + regs->eax,regs->ecx,regs->eflags); + return 1; + case 0xb10a: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + regs->ecx &= 0; + regs->ecx |= PciRead32(regs->edi,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx cx=0x%lx flags=0x%lx\n", + regs->eax,regs->ecx,regs->eflags); + return 1; + case 0xb10b: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + PciWrite8(regs->edi,(CARD8)regs->ecx,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags); + return 1; + case 0xb10c: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + PciWrite16(regs->edi,(CARD16)regs->ecx,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags); + return 1; + case 0xb10d: + i_printf("Slot=0x%x\n",CurrentPci->Slot.l); + if ((Slot = findPci(regs->ebx))) { + PciWrite32(regs->edi,(CARD32)regs->ecx,Slot); + regs->eax = (regs->eax & 0x00FF) | (SUCCESSFUL << 8); + regs->eflags &= ~((unsigned long)0x01); /* clear carry flag */ + } else { + regs->eax = (regs->eax & 0x00FF) | (BAD_REGISTER_NUMBER << 8); + regs->eflags |= ((unsigned long)0x01); /* set carry flag */ + } + i_printf("ax=0x%lx flags=0x%lx\n", regs->eax,regs->eflags); + return 1; + default: + return 0; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/io.c b/board/MAI/bios_emulator/scitech/src/v86bios/io.c new file mode 100644 index 000000000..f35b43e9b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/io.c @@ -0,0 +1,257 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "debug.h" + +#include +#if defined(__alpha__) || defined (__ia64__) +#include +#endif +#include "AsmMacros.h" +#include "v86bios.h" +#include "pci.h" + +int r_inb = 0, r_inw = 0, r_inl = 0, r_outb = 0, r_outw = 0, r_outl = 0; +int in_b = 0, in_w = 0, in_l = 0, out_b = 0, out_w = 0, out_l = 0; + + +int +port_rep_inb(CARD16 port, CARD8 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD8 *dst = base; + + p_printf(" rep_insb(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_inb++; + while (count--) { + *dst = inb(port); + dst += inc; + } + return (dst-base); +} + +int +port_rep_inw(CARD16 port, CARD16 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD16 *dst = base; + + p_printf(" rep_insw(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_inw++; + while (count--) { + *dst = inw(port); + dst += inc; + } + return (dst-base); +} + +int +port_rep_inl(CARD16 port, CARD32 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD32 *dst = base; + + p_printf(" rep_insl(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_inl++; + while (count--) { + *dst = inl(port); + dst += inc; + } + return (dst-base); +} + +int +port_rep_outb(CARD16 port, CARD8 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD8 *dst = base; + + p_printf(" rep_outb(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_outb++; + while (count--) { + outb(port,*dst); + dst += inc; + } + return (dst-base); +} + +int +port_rep_outw(CARD16 port, CARD16 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD16 *dst = base; + + p_printf(" rep_outw(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_outw++; + while (count--) { + outw(port,*dst); + dst += inc; + } + return (dst-base); +} + +int +port_rep_outl(CARD16 port, CARD32 *base, int d_f, CARD32 count) +{ + register int inc = d_f ? -1 : 1; + CARD32 *dst = base; + + p_printf(" rep_outl(%#x) %d bytes at %p %s", + port, count, base, d_f?"up":"down"); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + r_outl++; + while (count--) { + outl(port,*dst); + dst += inc; + } + return (dst-base); +} + +CARD8 +p_inb(CARD16 port) +{ + CARD8 val = 0; + in_b++; + val = inb(port); + p_printf(" inb(%#x) = %2.2x",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + return val; +} + +CARD16 +p_inw(CARD16 port) +{ + CARD16 val = 0; + in_w++; + val = inw(port); + p_printf(" inw(%#x) = %4.4x",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + return val; +} + +CARD32 +p_inl(CARD16 port) +{ + CARD32 val = 0; + in_l++; +#ifdef NEED_PCI_IO + if (cfg1in(port,&val)) + return val; + else +#endif + val = inl(port); + p_printf(" inl(%#x) = %8.8x",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + return val; +} + +void +p_outb(CARD16 port, CARD8 val) +{ + out_b++; + p_printf(" outb(%#x, %2.2x)",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + outb(port,val); +} + +void +p_outw(CARD16 port, CARD16 val) +{ + out_w++; + p_printf(" outw(%#x, %4.4x)",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + + outw(port,val); +} + +void +p_outl(CARD16 port, CARD32 val) +{ + out_l++; + p_printf(" outl(%#x, %8.8x)",port,val); + if (Config.PrintIp) + p_printf(" %x\n",getIP()); + else p_printf("\n"); + +#ifdef NEED_PCI_IO + if (cfg1out(port,val)) + return; +#endif + outl(port,val); +} + +void +io_statistics(void) +{ + p_printf("rep: inb: %i, inw: %i, inl: %i, outb: %i, outw: %i, outl: %i\n", + r_inb,r_inw,r_inl,r_outb,r_outw,r_outl); + p_printf("inb: %i, inw: %i, inl: %i, outb: %i, outw: %i, outl: %i\n", + in_b,in_w,in_l,out_b,out_w,out_l); +} + +void +clear_stat(void) +{ + r_inb = r_inw = r_inl = r_outb = r_outw = r_outl = 0; + in_b = in_w = in_l = out_b = out_w = out_l = 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/lex.l b/board/MAI/bios_emulator/scitech/src/v86bios/lex.l new file mode 100644 index 000000000..3a3391c7b --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/lex.l @@ -0,0 +1,79 @@ +%{ +#include "parser.h" + +#include +#include + + void getline(char *buf,int *num,int max_num); + +#define YY_INPUT(buf,result,max_size) {\ + getline(buf,&result,max_size);\ + } + + void + yyerror (char *s) + { + printf ("%s\n", s); + } + +%} + +DIGIT [0-9a-fA-F] + +%% + +"0x"?{DIGIT}+ { yylval = strtol(yytext,NULL,0); return TOK_NUM; } +"ax" { return TOK_REG_AX; } +"bx" { return TOK_REG_BX; } +"cx" { return TOK_REG_CX; } +"dx" { return TOK_REG_DX; } +"di" { return TOK_REG_SI; } +"si" { return TOK_REG_DI; } +"ds" { return TOK_SEG_DS; } +"es" { return TOK_SEG_ES; } +":" { return TOK_SEP;} +"$"{DIGIT}{1,2} { yylval = strtol(yytext+1,NULL,0); return TOK_VAR; } +"$mem" { return TOK_VAR_MEM; } +[ \t]+ +"#".*[\n] { return TOK_END; } +"boot" { return TOK_COMMAND_BOOT; } +"do" { return TOK_COMMAND_EXEC; } +"\"".*"\"" { yylval = (unsigned long) yytext; return TOK_STRING; } +"byte" { return TOK_BYTE; } +"word" { return TOK_WORD; } +"long" { return TOK_LONG; } +"setmem" { return TOK_COMMAND_MEMSET; } +"dumpmem" { return TOK_COMMAND_MEMDUMP; } +"quit" { return TOK_COMMAND_QUIT; } +"\n" { return TOK_END; } +"select" { return TOK_SELECT; } +"isa" { return TOK_ISA; } +"pci" { return TOK_PCI; } +"pport" { return TOK_PRINT_PORT; } +"iostat" { return TOK_IOSTAT; } +"pirq" { return TOK_PRINT_IRQ; } +"ppci" { return TOK_PPCI; } +"pip" { return TOK_PIP; } +"trace" { return TOK_TRACE; } +"on" { return TOK_ON; } +"off" { return TOK_OFF; } +"verbose" { return TOK_VERBOSE; } +"log" { return TOK_LOG; } +"print" { return TOK_STDOUT; } +"clstat" { return TOK_CLSTAT; } +"hlt" { return TOK_HLT; } +"del" { return TOK_DEL; } +"ioperm" { return TOK_IOPERM; } +"lpci" { return TOK_DUMP_PCI; } +"bootbios" { return TOK_BOOT_BIOS; } +"?" { return '?'; } +. { return TOK_ERROR; } + +%% + + + + + + + diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/main.c b/board/MAI/bios_emulator/scitech/src/v86bios/main.c new file mode 100644 index 000000000..15f91150f --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/main.c @@ -0,0 +1,616 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#define DELETE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(__alpha__) || defined (__ia64__) +#include +#elif defined(HAVE_SYS_PERM) +#include +#endif +#include "debug.h" +#include "v86bios.h" +#include "pci.h" +#include "AsmMacros.h" + +#define SIZE 0x100000 +#define VRAM_START 0xA0000 +#define VRAM_SIZE 0x1FFFF +#define V_BIOS_SIZE 0x1FFFF +#define BIOS_START 0x7C00 /* default BIOS entry */ + +/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0, 0xf4 }; */ +#define VB_X(x) (V_BIOS >> x) & 0xFF +CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xf4 }; +/*CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xb8, 0x03, 0x00, */ +/*0xcd, 0x10, 0xf4 }; */ +/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0 ,0xf4 }; */ + +static void sig_handler(int); +static int map(void); +static void unmap(void); +static void bootBIOS(CARD16 ax); +static int map_vram(void); +static void unmap_vram(void); +static int copy_vbios(void); +static int copy_sys_bios(void); +static void save_bios_to_file(void); +static int setup_system_bios(void); +static void setup_int_vect(void); +static int chksum(CARD8 *start); +static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax); + +void loadCodeToMem(unsigned char *ptr, CARD8 *code); +void dprint(unsigned long start, unsigned long size); + +static int vram_mapped = 0; +static CARD8 save_msr; +static CARD8 save_pos102; +static CARD8 save_vse; +static CARD8 save_46e8; +console Console; +struct config Config; + + +int +main(void) +{ + int Active_is_Pci = 0; +#ifdef DELETE + Config.PrintPort = PRINT_PORT; + Config.IoStatistics = IO_STATISTICS; + Config.PrintIrq = PRINT_IRQ; + Config.PrintPci = PRINT_PCI; + Config.ShowAllDev = SHOW_ALL_DEV; + Config.PrintIp = PRINT_IP; + Config.SaveBios = SAVE_BIOS; + Config.Trace = TRACE; + Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY; + Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE; + Config.MapSysBios = MAP_SYS_BIOS; + Config.Resort = RESORT; + Config.FixRom = FIX_ROM; + Config.NoConsole = NO_CONSOLE; + Config.Verbose = VERBOSE; + + if (!map()) + exit(1); + + if (!setup_system_bios()) + exit(1); + + iopl(3); + setup_io(); + + scan_pci(); + if (!CurrentPci && !Config.ConfigActiveDevice && !Config.ConfigActiveOnly) + exit (1); +#endif + Console = open_console(); + + if (Config.ConfigActiveOnly) { + CARD16 ax; + int activePci = 0; + int error = 0; + + while (CurrentPci) { + if (CurrentPci->active) { + activePci = 1; + if (!(mapPciRom(NULL) && chksum((CARD8*)V_BIOS))) + error = 1; + break; + } + CurrentPci = CurrentPci->next; + } + ax = ((CARD16)(CurrentPci->bus) << 8) + | (CurrentPci->dev << 3) | (CurrentPci->func & 0x7); + P_printf("ax: 0x%x\n",ax); + setup_int_vect(); + if (!error && (activePci || copy_vbios())) { + + if (Config.SaveBios) save_bios_to_file(); + if (map_vram()) { + printf("initializing ISA\n"); + bootBIOS(0); + } + } + unmap_vram(); + sleep(1); + } else { + /* disable primary card */ + save_msr = inb(0x3CC); + save_vse = inb(0x3C3); + save_46e8 = inb(0x46e8); + save_pos102 = inb(0x102); + + signal(2,sig_handler); + signal(11,sig_handler); + + outb(0x3C2,~(CARD8)0x03 & save_msr); + outb(0x3C3,~(CARD8)0x01 & save_vse); + outb(0x46e8, ~(CARD8)0x08 & save_46e8); + outb(0x102, ~(CARD8)0x01 & save_pos102); + + pciVideoDisable(); + + while (CurrentPci) { + CARD16 ax; + + if (CurrentPci->active) { + Active_is_Pci = 1; + if (!Config.ConfigActiveDevice) { + CurrentPci = CurrentPci->next; + continue; + } + } + + EnableCurrent(); + + if (CurrentPci->active) { + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + } + + /* clear interrupt vectors */ + setup_int_vect(); + + ax = ((CARD16)(CurrentPci->bus) << 8) + | (CurrentPci->dev << 3) | (CurrentPci->func & 0x7); + P_printf("ax: 0x%x\n",ax); + + if (!((mapPciRom(NULL) && chksum((CARD8*)V_BIOS)) + || (CurrentPci->active && copy_vbios()))) { + CurrentPci = CurrentPci->next; + continue; + } + if (!map_vram()) { + CurrentPci = CurrentPci->next; + continue; + } + if (Config.SaveBios) save_bios_to_file(); + printf("initializing PCI bus: %i dev: %i func: %i\n",CurrentPci->bus, + CurrentPci->dev,CurrentPci->func); + bootBIOS(ax); + unmap_vram(); + + CurrentPci = CurrentPci->next; + } + + /* We have an ISA device - configure if requested */ + if (!Active_is_Pci && Config.ConfigActiveDevice) { + pciVideoDisable(); + + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + + setup_int_vect(); + if (copy_vbios()) { + + if (Config.SaveBios) save_bios_to_file(); + if (map_vram()) { + printf("initializing ISA\n"); + bootBIOS(0); + } + } + + unmap_vram(); + sleep(1); + } + + pciVideoRestore(); + + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + } + + close_console(Console); +#ifdef DELETE + iopl(0); + unmap(); + + printf("done !\n"); +#endif + if (Config.IoStatistics) + io_statistics(); +#ifdef DELETE + exit(0); +#endif +} + +int +map(void) +{ + void* mem; + + mem = mmap(0, (size_t)SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, + MAP_FIXED | MAP_PRIVATE | MAP_ANON, + -1, 0 ); + if (mem != 0) { + perror("anonymous map"); + return (0); + } + memset(mem,0,SIZE); + + loadCodeToMem((unsigned char *) BIOS_START, code); + return (1); +} + +static void +unmap(void) +{ + munmap(0,SIZE); +} + +static void +bootBIOS(CARD16 ax) +{ + i86biosRegs bRegs; +#ifdef V86BIOS_DEBUG + printf("starting BIOS\n"); +#endif + setup_bios_regs(&bRegs, ax); + do_x86(BIOS_START,&bRegs); +#ifdef V86BIOS_DEBUG + printf("done\n"); +#endif +} + +static int +map_vram(void) +{ + int mem_fd; + +#ifdef __ia64__ + if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) +#else + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) +#endif + { + perror("opening memory"); + return 0; + } + +#ifndef __alpha__ + if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, + mem_fd, VRAM_START) == (void *) -1) +#else + if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */ + if (!_bus_base_sparse()) sparse_shift = 0; + if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift), + PROT_READ | PROT_WRITE, + MAP_SHARED, + mem_fd, (VRAM_START << sparse_shift) + | _bus_base_sparse())) == (void *) -1) +#endif + { + perror("mmap error in map_hardware_ram"); + close(mem_fd); + return (0); + } + vram_mapped = 1; + close(mem_fd); + return (1); +} + +static void +unmap_vram(void) +{ + if (!vram_mapped) return; + + munmap((void*)VRAM_START,VRAM_SIZE); + vram_mapped = 0; +} + +static int +copy_vbios(void) +{ + int mem_fd; + unsigned char *tmp; + int size; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) V_BIOS, SEEK_SET) != (off_t) V_BIOS) { + fprintf(stderr,"Cannot lseek\n"); + goto Error; + } + tmp = (unsigned char *)malloc(3); + if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + if (lseek(mem_fd,(off_t) V_BIOS,SEEK_SET) != (off_t) V_BIOS) + goto Error; + + if (*tmp != 0x55 || *(tmp+1) != 0xAA ) { +#ifdef DEBUG + dprint((unsigned long)tmp,0x100); +#endif + fprintf(stderr,"No bios found at: 0x%x\n",V_BIOS); + goto Error; + } + size = *(tmp+2) * 512; + + if (read(mem_fd, (char *)V_BIOS, (size_t) size) != (size_t) size) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + free(tmp); + close(mem_fd); + if (!chksum((CARD8)V_BIOS)) + return (0); + + return (1); + +Error: + perror("v_bios"); + close(mem_fd); + return (0); +} + +static int +copy_sys_bios(void) +{ +#define SYS_BIOS 0xF0000 + int mem_fd; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS) + goto Error; + if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF) + goto Error; + + close(mem_fd); + return (1); + +Error: + perror("sys_bios"); + close(mem_fd); + return (0); +} + +void +loadCodeToMem(unsigned char *ptr, CARD8 code[]) +{ + int i; + CARD8 val; + + for ( i=0;;i++) { + val = code[i]; + *ptr++ = val; + if (val == 0xf4) break; + } + return; +} + +void +dprint(unsigned long start, unsigned long size) +{ + int i,j; + char *c = (char *)start; + + for (j = 0; j < (size >> 4); j++) { + char *d = c; + printf("\n0x%lx: ",(unsigned long)c); + for (i = 0; i<16; i++) + printf("%2.2x ",(unsigned char) (*(c++))); + c = d; + for (i = 0; i<16; i++) { + printf("%c",((((CARD8)(*c)) > 32) && (((CARD8)(*c)) < 128)) ? + (unsigned char) (*(c)): '.'); + c++; + } + } + printf("\n"); +} + +static void +save_bios_to_file(void) +{ + static int num = 0; + int size, count; + char file_name[256]; + int fd; + + sprintf(file_name,"bios_%i.fil",num); + if ((fd = open(file_name,O_WRONLY | O_CREAT | O_TRUNC,00644)) == -1) + return; + size = (*(unsigned char*)(V_BIOS + 2)) * 512; +#ifdef V86BIOS_DEBUG + dprint(V_BIOS,20); +#endif + if ((count = write(fd,(void *)(V_BIOS),size)) != size) + fprintf(stderr,"only saved %i of %i bytes\n",size,count); + num++; +} + +static void +sig_handler(int unused) +{ + fflush(stdout); + fflush(stderr); + + /* put system back in a save state */ + unmap_vram(); + pciVideoRestore(); + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + + close_console(Console); + iopl(0); + unmap(); + + exit(1); +} + +/* + * For initialization we just pass ax to the BIOS. + * PCI BIOSes need this. All other register are set 0. + */ +static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax) +{ + regs->ax = ax; + regs->bx = 0; + regs->cx = 0; + regs->dx = 0; + regs->es = 0; + regs->di = 0; +} + +/* + * here we are really paranoid about faking a "real" + * BIOS. Most of this information was pulled from + * dosem. + */ +static void +setup_int_vect(void) +{ + const CARD16 cs = 0x0000; + const CARD16 ip = 0x0; + int i; + + /* let the int vects point to the SYS_BIOS seg */ + for (i=0; i<0x80; i++) { + ((CARD16*)0)[i<<1] = ip; + ((CARD16*)0)[(i<<1)+1] = cs; + } + /* video interrupts default location */ + ((CARD16*)0)[(0x42<<1)+1] = 0xf000; + ((CARD16*)0)[0x42<<1] = 0xf065; + ((CARD16*)0)[(0x10<<1)+1] = 0xf000; + ((CARD16*)0)[0x10<<1] = 0xf065; + /* video param table default location (int 1d) */ + ((CARD16*)0)[(0x1d<<1)+1] = 0xf000; + ((CARD16*)0)[0x1d<<1] = 0xf0A4; + /* font tables default location (int 1F) */ + ((CARD16*)0)[(0x1f<<1)+1] = 0xf000; + ((CARD16*)0)[0x1f<<1] = 0xfa6e; + + /* int 11 default location */ + ((CARD16*)0)[(0x11<1)+1] = 0xf000; + ((CARD16*)0)[0x11<<1] = 0xf84d; + /* int 12 default location */ + ((CARD16*)0)[(0x12<<1)+1] = 0xf000; + ((CARD16*)0)[0x12<<1] = 0xf841; + /* int 15 default location */ + ((CARD16*)0)[(0x15<<1)+1] = 0xf000; + ((CARD16*)0)[0x15<<1] = 0xf859; + /* int 1A default location */ + ((CARD16*)0)[(0x1a<<1)+1] = 0xf000; + ((CARD16*)0)[0x1a<<1] = 0xff6e; + /* int 05 default location */ + ((CARD16*)0)[(0x05<<1)+1] = 0xf000; + ((CARD16*)0)[0x05<<1] = 0xff54; + /* int 08 default location */ + ((CARD16*)0)[(0x8<<1)+1] = 0xf000; + ((CARD16*)0)[0x8<<1] = 0xfea5; + /* int 13 default location (fdd) */ + ((CARD16*)0)[(0x13<<1)+1] = 0xf000; + ((CARD16*)0)[0x13<<1] = 0xec59; + /* int 0E default location */ + ((CARD16*)0)[(0xe<<1)+1] = 0xf000; + ((CARD16*)0)[0xe<<1] = 0xef57; + /* int 17 default location */ + ((CARD16*)0)[(0x17<<1)+1] = 0xf000; + ((CARD16*)0)[0x17<<1] = 0xefd2; + /* fdd table default location (int 1e) */ + ((CARD16*)0)[(0x1e<<1)+1] = 0xf000; + ((CARD16*)0)[0x1e<<1] = 0xefc7; +} + +static int +setup_system_bios(void) +{ + char *date = "06/01/99"; + char *eisa_ident = "PCI/ISA"; + +#if MAP_SYS_BIOS + if (!copy_sys_bios()) return 0; + return 1; +#endif +/* memset((void *)0xF0000,0xf4,0xfff7); */ + + /* + * we trap the "industry standard entry points" to the BIOS + * and all other locations by filling them with "hlt" + * TODO: implement hlt-handler for these + */ + memset((void *)0xF0000,0xf4,0x10000); + + /* + * TODO: we should copy the fdd table (0xfec59-0xfec5b) + * the video parameter table (0xf0ac-0xf0fb) + * and the font tables (0xfa6e-0xfe6d) + * from the original bios here + */ + + /* set bios date */ + strcpy((char *)0xFFFF5,date); + /* set up eisa ident string */ + strcpy((char *)0xFFFD9,eisa_ident); + /* write system model id for IBM-AT */ + ((char *)0)[0xFFFFE] = 0xfc; + + return 1; +} + +static int +chksum(CARD8 *start) +{ + CARD16 size; + CARD8 val = 0; + int i; + + size = *(start+2) * 512; + for (i = 0; i= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + shift = (addr & 0x3) * 8; + result = *(vuip) ((unsigned long)vram_map + (addr << sparse_shift)); + result >>= shift; + return 0xffUL & result; + } else +#endif + return rdb(addr); +} + +CARD16 +mem_rw(CARD32 addr) +{ + unsigned long result, shift; +#if 1 + if (addr >= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + shift = (addr & 0x2) * 8; + result = *(vuip)((unsigned long)vram_map+(addr<>= shift; + return 0xffffUL & result; + } else +#endif + return rdw(addr); +} + +CARD32 +mem_rl(CARD32 addr) +{ + unsigned long result; +#if 1 + if (addr >= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + result = *(vuip)((unsigned long)vram_map+(addr<= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + *(vuip) ((unsigned long)vram_map + (addr << sparse_shift)) = b * 0x01010101; + mem_barrier(); + } else +#endif + wrb(addr,val); +} + +void +mem_ww(CARD32 addr, CARD16 val) +{ + unsigned int w = val & 0xffffU; +#if 1 + if (addr >= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + *(vuip)((unsigned long)vram_map+(addr<= 0xA0000 && addr <= 0xBFFFF) { + addr -= 0xA0000; + *(vuip)((unsigned long)vram_map+(addr< +#include +#include "v86bios.h" +#include "pci.h" + +#define YYSTYPE unsigned long + +#define MAX_VAR 0x20 + + CARD32 var[MAX_VAR]; + CARD32 var_mem; + + +i86biosRegs regs = { 00 }; + +enum mem_type { BYTE, WORD, LONG, STRING }; +union mem_val { + CARD32 integer; + char *ptr; +} rec; + +struct mem { + enum mem_type type; + union mem_val val; + struct mem *next; +}; + + +struct device Device = {FALSE,NONE,{0}}; + +extern void yyerror(char *s); +extern int yylex( void ); + +static void boot(void); +static void dump_mem(CARD32 addr, int len); +static void exec_int(int num); +static void *add_to_list(enum mem_type type, union mem_val *rec, void *next); +static void do_list(struct mem *list, memType addr); +static char * normalize_string(char *ptr); +%} + +%token TOK_NUM +%token TOK_REG_AX +%token TOK_REG_BX +%token TOK_REG_CX +%token TOK_REG_DX +%token TOK_REG_DI +%token TOK_REG_SI +%token TOK_SEG_DS +%token TOK_SEG_ES +%token TOK_SEP +%token TOK_VAR +%token TOK_VAR_MEM +%token TOK_COMMAND_BOOT +%token TOK_COMMAND_EXEC +%token TOK_SELECT +%token TOK_STRING +%token TOK_MODIFIER_BYTE +%token TOK_MODIFIER_WORD +%token TOK_MODIFIER_LONG +%token TOK_MODIFIER_MEMSET +%token TOK_COMMAND_MEMSET +%token TOK_COMMAND_MEMDUMP +%token TOK_COMMAND_QUIT +%token TOK_ERROR +%token TOK_END +%token TOK_ISA +%token TOK_PCI +%token TOK_BYTE +%token TOK_WORD +%token TOK_LONG +%token TOK_PRINT_PORT +%token TOK_IOSTAT +%token TOK_PRINT_IRQ +%token TOK_PPCI +%token TOK_PIP +%token TOK_TRACE +%token TOK_ON +%token TOK_OFF +%token TOK_VERBOSE +%token TOK_LOG +%token TOK_LOGOFF +%token TOK_CLSTAT +%token TOK_STDOUT +%token TOK_HLT +%token TOK_DEL +%token TOK_IOPERM +%token TOK_DUMP_PCI +%token TOK_BOOT_BIOS +%% +input: | input line +line: end | com_reg | com_var | com_select + | com_boot | com_memset | com_memdump | com_quit + | com_exec | hlp | config | verbose | logging | print | clstat + | com_hlt | ioperm | list_pci | boot_bios + | error end { printf("unknown command\n"); } +; +end: TOK_END +; +com_reg: reg_off val end { *(CARD16*)$1 = $2 & 0xffff; } + | reg_seg TOK_SEP reg_off val end { + *(CARD16*)$1 = ($4 & 0xf0000) >> 4; + *(CARD16*)$3 = ($4 & 0x0ffff); + } + | reg_off '?' end { printf("0x%x\n",*(CARD16*)$1);} + | reg_seg TOK_SEP reg_off '?' end + { printf("0x%x:0x%x\n",*(CARD16*)$1, + *(CARD16*)$3); } +; +register_read: reg_seg TOK_SEP reg_off { $$ = (((*(CARD16*)$1) << 4) + | ((*(CARD16*)$3) & 0xffff)); + } + | reg_off { $$ = ((*(CARD16*)$1) & 0xffff); } +; +reg_off: TOK_REG_AX { $$ = (unsigned long)&(regs.ax); } + | TOK_REG_BX { $$ = (unsigned long)&(regs.bx); } + | TOK_REG_CX { $$ = (unsigned long)&(regs.cx); } + | TOK_REG_DX { $$ = (unsigned long)&(regs.dx); } + | TOK_REG_DI { $$ = (unsigned long)&(regs.di); } + | TOK_REG_SI { $$ = (unsigned long)&(regs.si); } +; +reg_seg: TOK_SEG_DS { $$ = (unsigned long)&(regs.ds); } + | TOK_SEG_ES { $$ = (unsigned long)&(regs.es); } +; +com_var: TOK_VAR_MEM '?' end { printf("var mem: 0x%x\n",var_mem); } + | TOK_VAR '?' end { if ($1 < MAX_VAR) + printf("var[%i]: 0x%x\n",(int)$1,var[$1]); + else + printf("var index %i out of range\n",(int)$1); } + | TOK_VAR_MEM val end { var_mem = $2; } + | TOK_VAR val end { if ($1 <= MAX_VAR) + var[$1] = $2; + else + printf("var index %i out of range\n",(int)$1); } + | TOK_VAR error end { printf("$i val\n"); } + | TOK_VAR_MEM error end { printf("$i val\n"); } +; +com_boot: TOK_COMMAND_BOOT end { boot(); } + TOK_COMMAND_BOOT error end { boot(); } +; +com_select: TOK_SELECT TOK_ISA end { Device.booted = FALSE; + Device.type = ISA; + CurrentPci = NULL; } + | TOK_SELECT TOK_PCI val TOK_SEP val TOK_SEP val end + { Device.booted = FALSE; + Device.type = PCI; + Device.loc.pci.bus = $3; + Device.loc.pci.dev = $5; + Device.loc.pci.func = $7; } + | TOK_SELECT '?' end + { switch (Device.type) { + case ISA: + printf("isa\n"); + break; + case PCI: + printf("pci: %x:%x:%x\n",Device.loc.pci.bus, + Device.loc.pci.dev, + Device.loc.pci.func); + break; + default: + printf("no device selected\n"); + break; + } + } + | TOK_SELECT error end { printf("select ? | isa " + "| pci:bus:dev:func\n"); } +; +com_quit: TOK_COMMAND_QUIT end { return 0; } + | TOK_COMMAND_QUIT error end { logoff(); return 0; } +; +com_exec: TOK_COMMAND_EXEC end { exec_int(0x10); } + | TOK_COMMAND_EXEC val end { exec_int($2); } + | TOK_COMMAND_EXEC error end { exec_int(0x10); } +; +com_memdump: TOK_COMMAND_MEMDUMP val val end { dump_mem($2,$3); } + | TOK_COMMAND_MEMDUMP error end { printf("memdump start len\n"); } + + +; +com_memset: TOK_COMMAND_MEMSET val list end { do_list((struct mem*)$3,$2);} + | TOK_COMMAND_MEMSET error end { printf("setmem addr [byte val] " + "[word val] [long val] " + "[\"string\"]\n"); } +; +list: { $$ = 0; } + | TOK_BYTE val list { rec.integer = $2; + $$ = (unsigned long)add_to_list(BYTE,&rec,(void*)$3); } + | TOK_WORD val list { rec.integer = $2; + $$ = (unsigned long) add_to_list(WORD,&rec,(void*)$3); } + | TOK_LONG val list { rec.integer = $2; + $$ = (unsigned long) add_to_list(LONG,&rec,(void*)$3); } + | TOK_STRING list { rec.ptr = (void*)$1; + $$ = (unsigned long) add_to_list(STRING,&rec,(void*)$2); } +; +val: TOK_VAR { if ($1 > MAX_VAR) { + printf("variable index out of range\n"); + $$=0; + } else + $$ = var[$1]; } + | TOK_NUM { $$ = $1; } + | register_read +; +bool: TOK_ON { $$ = 1; } + | TOK_OFF { $$ = 0; } +; +config: TOK_PRINT_PORT bool end { Config.PrintPort = $2; } + | TOK_PRINT_PORT '?' end { printf("print port %s\n", + Config.PrintPort?"on":"off"); } + | TOK_PRINT_PORT error end { printf("pport on | off | ?\n") } + | TOK_PRINT_IRQ bool end { Config.PrintIrq = $2; } + | TOK_PRINT_IRQ '?' end { printf("print irq %s\n", + Config.PrintIrq?"on":"off"); } + | TOK_PRINT_IRQ error end { printf("pirq on | off | ?\n") } + | TOK_PPCI bool end { Config.PrintPci = $2; } + | TOK_PPCI '?' end { printf("print PCI %s\n", + Config.PrintPci?"on":"off"); } + | TOK_PPCI error end { printf("ppci on | off | ?\n") } + | TOK_PIP bool end { Config.PrintIp = $2; } + | TOK_PIP '?' end { printf("printip %s\n", + Config.PrintIp?"on":"off"); } + | TOK_PIP error end { printf("pip on | off | ?\n") } + | TOK_IOSTAT bool end { Config.IoStatistics = $2; } + | TOK_IOSTAT '?' end { printf("io statistics %s\n", + Config.IoStatistics?"on":"off"); } + | TOK_IOSTAT error end { printf("iostat on | off | ?\n") } + | TOK_TRACE bool end { Config.Trace = $2; } + | TOK_TRACE '?' end { printf("trace %s\n", + Config.Trace ?"on":"off"); } + | TOK_TRACE error end { printf("trace on | off | ?\n") } +; +verbose: TOK_VERBOSE val end { Config.Verbose = $2; } + | TOK_VERBOSE '?' end { printf("verbose: %i\n", + Config.Verbose); } + | TOK_VERBOSE error end { printf("verbose val | ?\n"); } +; +logging: TOK_LOG TOK_STRING end { logon(normalize_string((char*)$2)); } + | TOK_LOG '?' end { if (logging) printf("logfile: %s\n", + logfile); + else printf("no logging\n?"); } + | TOK_LOG TOK_OFF end { logoff(); } + | TOK_LOG error end { printf("log \"\" | ? |" + " off\n"); } +; +clstat: TOK_CLSTAT end { clear_stat(); } + | TOK_CLSTAT error end { printf("clstat\n"); } +; +print: TOK_STDOUT bool end { nostdout = !$2; } + | TOK_STDOUT '?' end { printf("print %s\n",nostdout ? + "no":"yes"); } + | TOK_STDOUT error end { printf("print on | off\n"); } +; +com_hlt: TOK_HLT val end { add_hlt($2); } + | TOK_HLT TOK_DEL val end { del_hlt($3); } + | TOK_HLT TOK_DEL end { del_hlt(21); } + | TOK_HLT '?' end { list_hlt(); } + | TOK_HLT error end { printf( + "hlt val | del [val] | ?\n"); } +; +ioperm: TOK_IOPERM val val val end { int i,max; + if ($2 >= 0) { + max = $2 + $3 - 1; + if (max > IOPERM_BITS) + max = IOPERM_BITS; + for (i = $2;i <= max; i++) + ioperm_list[i] + = $4>0 ? 1 : 0; + } + } + | TOK_IOPERM '?' end { int i,start; + for (i=0; i <= IOPERM_BITS; i++) { + if (ioperm_list[i]) { + start = i; + for (; i <= IOPERM_BITS; i++) + if (!ioperm_list[i]) { + printf("ioperm on in " + "0x%x+0x%x\n", start,i-start); + break; + } + } + } + } + | TOK_IOPERM error end { printf("ioperm start len val\n"); } +; +list_pci: TOK_DUMP_PCI end { list_pci(); } + | TOK_DUMP_PCI error end { list_pci(); } +; +boot_bios: TOK_BOOT_BIOS '?' end { if (!BootBios) printf("No Boot BIOS\n"); + else printf("BootBIOS from: %i:%i:%i\n", + BootBios->bus, BootBios->dev, + BootBios->func); } + | TOK_BOOT_BIOS error end { printf ("bootbios bus:dev:num\n"); } +; +hlp: '?' { printf("Command list:\n"); + printf(" select isa | pci bus:dev:func\n"); + printf(" boot\n"); + printf(" seg:reg val | reg val \n"); + printf(" $x val | $mem val\n"); + printf(" setmem addr list; addr := val\n"); + printf(" dumpmem addr len; addr,len := val\n"); + printf(" do [val]\n"); + printf(" quit\n"); + printf(" ?\n"); + printf(" seg := ds | es;" + " reg := ax | bx | cx | dx | si \n"); + printf(" val := var | | seg:reg | seg\n"); + printf(" var := $x | $mem; x := 0..20\n"); + printf(" list := byte val | word val | long val " + "| \"string\"\n"); + printf(" pport on | off | ?\n"); + printf(" ppci on | off | ?\n"); + printf(" pirq on | off | ?\n"); + printf(" pip on | off | ?\n"); + printf(" trace on | off | ?\n"); + printf(" iostat on | off | ?\n"); + printf(" verbose val\n"); + printf(" log \"\" | off | ?\n"); + printf(" print on | off\n"); + printf(" hlt val | del [val] | ?\n"); + printf(" clstat\n"); + printf(" lpci\n"); + printf ("bootbios ?\n"); +} +; + +%% + +static void +dump_mem(CARD32 addr, int len) +{ + dprint(addr,len); +} + +static void +exec_int(int num) +{ + if (num == 0x10) { /* video interrupt */ + if (Device.type == NONE) { + CurrentPci = PciList; + while (CurrentPci) { + if (CurrentPci->active) + break; + CurrentPci = CurrentPci->next; + } + if (!CurrentPci) + Device.type = ISA; + else { + Device.type = PCI; + Device.loc.pci.dev = CurrentPci->dev; + Device.loc.pci.bus = CurrentPci->bus; + Device.loc.pci.func = CurrentPci->func; + } + } + if (Device.type != ISA) { + if (!Device.booted) { + if (!CurrentPci || (Device.type == PCI + && (!CurrentPci->active + && (Device.loc.pci.dev != CurrentPci->dev + || Device.loc.pci.bus != CurrentPci->bus + || Device.loc.pci.func != CurrentPci->func)))) { + printf("boot the device fist\n"); + return; + } + } + } else + CurrentPci = NULL; + } else { + Device.booted = FALSE; /* we need this for sanity! */ + } + + runINT(num,®s); +} + +static void +boot(void) +{ + if (Device.type == NONE) { + printf("select a device fist\n"); + return; + } + + call_boot(&Device); +} + +static void * +add_to_list(enum mem_type type, union mem_val *rec, void *next) +{ + struct mem *mem_rec = (struct mem *) malloc(sizeof(mem_rec)); + + mem_rec->type = type; + mem_rec->next = next; + + switch (type) { + case BYTE: + case WORD: + case LONG: + mem_rec->val.integer = rec->integer; + break; + case STRING: + mem_rec->val.ptr = normalize_string(rec->ptr); + break; + } + return mem_rec; +} + +static int +validRange(int addr,int len) +{ + int end = addr + len; + + if (addr < 0x1000 || end > 0xc0000) + return 0; + return 1; +} + +static void +do_list(struct mem *list, memType addr) +{ + struct mem *prev; + int len; + + while (list) { + switch (list->type) { + case BYTE: + if (!validRange(addr,1)) goto error; + *(CARD8*)addr = list->val.integer; + addr =+ 1; + break; + case WORD: + if (!validRange(addr,2)) goto error; + *(CARD16*)addr = list->val.integer; + addr =+ 2; + break; + case LONG: + if (!validRange(addr,4)) goto error; + *(CARD32*)addr = list->val.integer; + addr =+ 4; + break; + case STRING: + len = strlen((char*)list->val.ptr); + if (!validRange(addr,len)) goto error; + memcpy((CARD8*)addr,(void*)list->val.ptr,len); + addr =+ len; + free(list->val.ptr); + break; + } + prev = list; + list = list->next; + free(prev); + continue; + error: + printf("address out of range\n"); + while (list) { + prev = list; + list = list->next; + free(prev); + } + break; + } +} + +static char * +normalize_string(char *ptr) +{ + int i = 0, j = 0, c = 0, esc= 0; + int size; + char *mem_ptr; + + size = strlen(ptr); + mem_ptr = malloc(size); + while (1) { + switch (*(ptr + i)) { + case '\\': + if (esc) { + *(mem_ptr + j++) = *(ptr + i); + esc = 0; + } else + esc = 1; + break; + case '\"': + if (esc) { + *(mem_ptr + j++) = *(ptr + i); + esc = 0; + } else + c++; + break; + default: + *(mem_ptr + j++) = *(ptr + i); + break; + } + if (c > 1) { + *(mem_ptr + j) = '\0'; + break; + } + i++; + } + return mem_ptr; +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/pci.c b/board/MAI/bios_emulator/scitech/src/v86bios/pci.c new file mode 100644 index 000000000..b58a57195 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/pci.c @@ -0,0 +1,902 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "debug.h" +#include +#include +#include +#include +#include +#include +#include +#include +#if defined (__alpha__) || defined (__ia64__) +#include +#endif +#include "AsmMacros.h" + +#include "pci.h" + +/* + * I'm rather simple mindend - therefore I do a poor man's + * pci scan without all the fancy stuff that is done in + * scanpci. However that's all we need. + */ + +PciStructPtr PciStruct = NULL; +PciBusPtr PciBuses = NULL; +PciStructPtr CurrentPci = NULL; +PciStructPtr PciList = NULL; +PciStructPtr BootBios = NULL; +int pciMaxBus = 0; + +static CARD32 PciCfg1Addr; + +static void readConfigSpaceCfg1(CARD32 bus, CARD32 dev, CARD32 func, + CARD32 *reg); +static int checkSlotCfg1(CARD32 bus, CARD32 dev, CARD32 func); +static int checkSlotCfg2(CARD32 bus, int dev); +static void readConfigSpaceCfg2(CARD32 bus, int dev, CARD32 *reg); +static CARD8 interpretConfigSpace(CARD32 *reg, int busidx, + CARD8 dev, CARD8 func); +static CARD32 findBIOSMap(PciStructPtr pciP, CARD32 *biosSize); +static void restoreMem(PciStructPtr pciP); + + +#ifdef __alpha__ +#define PCI_BUS_FROM_TAG(tag) (((tag) & 0x00ff0000) >> 16) +#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00) >> 8) + +#include + +CARD32 +axpPciCfgRead(CARD32 tag) +{ + int bus, dfn; + CARD32 val = 0xffffffff; + + bus = PCI_BUS_FROM_TAG(tag); + dfn = PCI_DFN_FROM_TAG(tag); + + syscall(__NR_pciconfig_read, bus, dfn, tag & 0xff, 4, &val); + return(val); +} + +void +axpPciCfgWrite(CARD32 tag, CARD32 val) +{ + int bus, dfn; + + bus = PCI_BUS_FROM_TAG(tag); + dfn = PCI_DFN_FROM_TAG(tag); + + syscall(__NR_pciconfig_write, bus, dfn, tag & 0xff, 4, &val); +} + +static CARD32 (*readPci)(CARD32 reg) = axpPciCfgRead; +static void (*writePci)(CARD32 reg, CARD32 val) = axpPciCfgWrite; +#else +static CARD32 readPciCfg1(CARD32 reg); +static void writePciCfg1(CARD32 reg, CARD32 val); +static CARD32 readPciCfg2(CARD32 reg); +static void writePciCfg2(CARD32 reg, CARD32 val); + +static CARD32 (*readPci)(CARD32 reg) = readPciCfg1; +static void (*writePci)(CARD32 reg, CARD32 val) = writePciCfg1; +#endif + +#if defined(__alpha__) || defined(__sparc__) +#define PCI_EN 0x00000000 +#else +#define PCI_EN 0x80000000 +#endif + + +static int numbus; +static int hostbridges = 1; +static unsigned long pciMinMemReg = ~0; + + +void +scan_pci(void) +{ + unsigned short configtype; + + CARD32 reg[64]; + int busidx; + CARD8 cardnum; + CARD8 func; + int idx; + + int i; + PciStructPtr pci1; + PciBusPtr pci_b1,pci_b2; + +#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc__) || defined(__ia64__) + configtype = 1; +#else + CARD8 tmp1, tmp2; + CARD32 tmp32_1, tmp32_2; + outb(PCI_MODE2_ENABLE_REG, 0x00); + outb(PCI_MODE2_FORWARD_REG, 0x00); + tmp1 = inb(PCI_MODE2_ENABLE_REG); + tmp2 = inb(PCI_MODE2_FORWARD_REG); + if ((tmp1 == 0x00) && (tmp2 == 0x00)) { + configtype = 2; + readPci = readPciCfg2; + writePci = writePciCfg2; + P_printf("PCI says configuration type 2\n"); + } else { + tmp32_1 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, PCI_EN); + tmp32_2 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, tmp32_1); + if (tmp32_2 == PCI_EN) { + configtype = 1; + P_printf("PCI says configuration type 1\n"); + } else { + P_printf("No PCI !\n"); + return; + } + } +#endif + + if (configtype == 1) { + P_printf("PCI probing configuration type 1\n"); + busidx = 0; + numbus = 1; + idx = 0; + do { + P_printf("\nProbing for devices on PCI bus %d:\n", busidx); + for (cardnum = 0; cardnum < MAX_DEV_PER_VENDOR_CFG1; cardnum++) { + func = 0; + do { + /* loop over the different functions, if present */ + if (!checkSlotCfg1(busidx,cardnum,func)) + break; + readConfigSpaceCfg1(busidx,cardnum,func,reg); + + func = interpretConfigSpace(reg,busidx, + cardnum,func); + + if (idx++ > MAX_PCI_DEVICES) + continue; + } while (func < 8); + } + } while (++busidx < PCI_MAXBUS); +#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc__) || defined(__ia64__) + /* don't use outl() ;-) */ +#else + outl(PCI_MODE1_ADDRESS_REG, 0); +#endif + } else { + int slot; + + P_printf("PCI probing configuration type 2\n"); + busidx = 0; + numbus = 1; + idx = 0; + do { + for (slot=0xc0; slot<0xd0; i++) { + if (!checkSlotCfg2(busidx,slot)) + break; + readConfigSpaceCfg2(busidx,slot,reg); + + interpretConfigSpace(reg,busidx, + slot,0); + if (idx++ > MAX_PCI_DEVICES) + continue; + } + } while (++busidx < PCI_MAXBUS); + } + + + pciMaxBus = numbus - 1; + P_printf("Number of buses in system: %i\n",pciMaxBus + 1); + P_printf("Min PCI mem address: 0x%lx\n",pciMinMemReg); + + /* link buses */ + pci_b1 = PciBuses; + while (pci_b1) { + pci_b2 = PciBuses; + pci_b1->pBus = NULL; + while (pci_b2) { + if (pci_b1->primary == pci_b2->secondary) + pci_b1->pBus = pci_b2; + pci_b2 = pci_b2->next; + } + pci_b1 = pci_b1->next; + } + pci1 = PciStruct; + while (pci1) { + pci_b2 = PciBuses; + pci1->pBus = NULL; + while (pci_b2) { + if (pci1->bus == pci_b2->secondary) + pci1->pBus = pci_b2; + pci_b2 = pci_b2->next; + } + pci1 = pci1->next; + } + if (RESORT) { + PciStructPtr tmp = PciStruct, tmp1; + PciStruct = NULL; + while (tmp) { + tmp1 = tmp->next; + tmp->next = PciStruct; + PciStruct = tmp; + tmp = tmp1; + } + } + PciList = CurrentPci = PciStruct; +} + +#ifndef __alpha__ +static CARD32 +readPciCfg1(CARD32 reg) +{ + CARD32 val; + + outl(PCI_MODE1_ADDRESS_REG, reg); + val = inl(PCI_MODE1_DATA_REG); + outl(PCI_MODE1_ADDRESS_REG, 0); + P_printf("reading: 0x%x from 0x%x\n",val,reg); + return val; +} + +static void +writePciCfg1(CARD32 reg, CARD32 val) +{ + P_printf("writing: 0x%x to 0x%x\n",val,reg); + outl(PCI_MODE1_ADDRESS_REG, reg); + outl(PCI_MODE1_DATA_REG,val); + outl(PCI_MODE1_ADDRESS_REG, 0); +} + +static CARD32 +readPciCfg2(CARD32 reg) +{ + CARD32 val; + CARD8 bus = (reg >> 16) & 0xff; + CARD8 dev = (reg >> 11) & 0x1f; + CARD8 num = reg & 0xff; + + outb(PCI_MODE2_ENABLE_REG, 0xF1); + outb(PCI_MODE2_FORWARD_REG, bus); + val = inl((dev << 8) + num); + outb(PCI_MODE2_ENABLE_REG, 0x00); + P_printf("reading: 0x%x from 0x%x\n",val,reg); + return val; +} + +static void +writePciCfg2(CARD32 reg, CARD32 val) +{ + CARD8 bus = (reg >> 16) & 0xff; + CARD8 dev = (reg >> 11) & 0x1f; + CARD8 num = reg & 0xff; + + P_printf("writing: 0x%x to 0x%x\n",val,reg); + outb(PCI_MODE2_ENABLE_REG, 0xF1); + outb(PCI_MODE2_FORWARD_REG, bus); + outl((dev << 8) + num,val); + outb(PCI_MODE2_ENABLE_REG, 0x00); +} +#endif + +void +pciVideoDisable(void) +{ + /* disable VGA routing on bridges */ + PciBusPtr pbp = PciBuses; + PciStructPtr pcp = PciStruct; + + while (pbp) { + writePci(pbp->Slot.l | 0x3c, pbp->bctl & ~(CARD32)(8<<16)); + pbp = pbp->next; + } + /* disable display devices */ + while (pcp) { + writePci(pcp->Slot.l | 0x04, pcp->cmd_st & ~(CARD32)3); + writePci(pcp->Slot.l | 0x30, pcp->RomBase & ~(CARD32)1); + pcp = pcp->next; + } +} + +void +pciVideoRestore(void) +{ + /* disable VGA routing on bridges */ + PciBusPtr pbp = PciBuses; + PciStructPtr pcp = PciStruct; + + while (pbp) { + writePci(pbp->Slot.l | 0x3c, pbp->bctl); + pbp = pbp->next; + } + /* disable display devices */ + while (pcp) { + writePci(pcp->Slot.l | 0x04, pcp->cmd_st); + writePci(pcp->Slot.l | 0x30, pcp->RomBase); + pcp = pcp->next; + } +} + +void +EnableCurrent() +{ + PciBusPtr pbp; + PciStructPtr pcp = CurrentPci; + + pciVideoDisable(); + + pbp = pcp->pBus; + while (pbp) { /* enable bridges */ + writePci(pbp->Slot.l | 0x3c, pbp->bctl | (CARD32)(8<<16)); + pbp = pbp->pBus; + } + writePci(pcp->Slot.l | 0x04, pcp->cmd_st | (CARD32)3); + writePci(pcp->Slot.l | 0x30, pcp->RomBase | (CARD32)1); +} + +CARD8 +PciRead8(int offset, CARD32 Slot) +{ + int shift = offset & 0x3; + offset = offset & 0xFC; + return ((readPci(Slot | offset) >> (shift << 3)) & 0xff); +} + +CARD16 +PciRead16(int offset, CARD32 Slot) +{ + int shift = offset & 0x2; + offset = offset & 0xFC; + return ((readPci(Slot | offset) >> (shift << 3)) & 0xffff); +} + +CARD32 +PciRead32(int offset, CARD32 Slot) +{ + offset = offset & 0xFC; + return (readPci(Slot | offset)); +} + +void +PciWrite8(int offset, CARD8 byte, CARD32 Slot) +{ + CARD32 val; + int shift = offset & 0x3; + offset = offset & 0xFC; + val = readPci(Slot | offset); + val &= ~(CARD32)(0xff << (shift << 3)); + val |= byte << (shift << 3); + writePci(Slot | offset, val); +} + +void +PciWrite16(int offset, CARD16 word, CARD32 Slot) +{ + CARD32 val; + int shift = offset & 0x2; + offset = offset & 0xFC; + val = readPci(Slot | offset); + val &= ~(CARD32)(0xffff << (shift << 3)); + val |= word << (shift << 3); + writePci(Slot | offset, val); +} + +void +PciWrite32(int offset, CARD32 lg, CARD32 Slot) +{ + offset = offset & 0xFC; + writePci(Slot | offset, lg); +} + +int +mapPciRom(PciStructPtr pciP) +{ + unsigned long RomBase = 0; + int mem_fd; + unsigned char *mem, *ptr; + unsigned char *scratch = NULL; + int length = 0; + CARD32 biosSize = 0x1000000; + CARD32 enablePci; + + if (!pciP) + pciP = CurrentPci; + + if (FIX_ROM) { + RomBase = findBIOSMap(pciP, &biosSize); + if (!RomBase) { + fprintf(stderr,"Cannot remap BIOS of %i:%i:%i " + "- trying preset address\n",pciP->bus,pciP->dev, + pciP->func); + RomBase = pciP->RomBase & ~(CARD32)0xFF; + } + } else { + RomBase = pciP->RomBase & ~(CARD32)0xFF; + if (~RomBase + 1 < biosSize || !RomBase) + RomBase = findBIOSMap(pciP, &biosSize); + } + + P_printf("RomBase: 0x%lx\n",RomBase); + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + restoreMem(pciP); + return (0); + } + + PciWrite32(0x30,RomBase | 1,pciP->Slot.l); + +#ifdef __alpha__ + mem = ptr = (unsigned char *)mmap(0, biosSize, PROT_READ, + MAP_SHARED, mem_fd, RomBase | _bus_base()); +#else + mem = ptr = (unsigned char *)mmap(0, biosSize, PROT_READ, + MAP_SHARED, mem_fd, RomBase); +#endif + if (pciP != CurrentPci) { + enablePci = PciRead32(0x4,pciP->Slot.l); + PciWrite32(0x4,enablePci | 0x2,pciP->Slot.l); + } + +#ifdef PRINT_PCI + dprint((unsigned long)ptr,0x30); +#endif + while ( *ptr == 0x55 && *(ptr+1) == 0xAA) { + unsigned short data_off = *(ptr+0x18) | (*(ptr+0x19)<< 8); + unsigned char *data = ptr + data_off; + unsigned char type; + int i; + + if (*data!='P' || *(data+1)!='C' || *(data+2)!='I' || *(data+3)!='R') { + break; + } + type = *(data + 0x14); + P_printf("data segment in BIOS: 0x%x, type: 0x%x ",data_off,type); + + if (type != 0) { /* not PC-AT image: find next one */ + unsigned int image_length; + unsigned char indicator = *(data + 0x15); + if (indicator & 0x80) /* last image */ + break; + image_length = (*(data + 0x10) + | (*(data + 0x11) << 8)) << 9; + P_printf("data image length: 0x%x, ind: 0x%x\n", + image_length,indicator); + ptr = ptr + image_length; + continue; + } + /* OK, we have a PC Image */ + length = (*(ptr + 2) << 9); + P_printf("BIOS length: 0x%x\n",length); + scratch = (unsigned char *)malloc(length); + /* don't use memcpy() here: Reading from bus! */ + for (i=0;iSlot.l); + + /* unmap/close/disable PCI bios mem */ + munmap(mem, biosSize); + close(mem_fd); + /* disable and restore mapping */ + writePci(pciP->Slot.l | 0x30, pciP->RomBase & ~(CARD32)1); + + if (scratch && length) { + memcpy((unsigned char *)V_BIOS, scratch, length); + free(scratch); + } + + restoreMem(pciP); + return length; +} + +CARD32 +findPci(CARD16 slotBX) +{ + CARD32 slot = slotBX << 8; + + if (slot == (CurrentPci->Slot.l & ~PCI_EN)) + return (CurrentPci->Slot.l | PCI_EN); + else { +#if !SHOW_ALL_DEV + PciBusPtr pBus = CurrentPci->pBus; + while (pBus) { + /* fprintf(stderr,"slot: 0x%x bridge: 0x%x\n",slot, pBus->Slot.l); */ + if (slot == (pBus->Slot.l & ~PCI_EN)) + return pBus->Slot.l | PCI_EN; + pBus = pBus->next; + } +#else + PciStructPtr pPci = PciStruct; + while (pPci) { + /*fprintf(stderr,"slot: 0x%x bridge: 0x%x\n",slot, pPci->Slot.l); */ + if (slot == (pPci->Slot.l & ~PCI_EN)) + return pPci->Slot.l | PCI_EN; + pPci = pPci->next; + } +#endif + } + return 0; +} + +CARD16 +pciSlotBX(PciStructPtr pPci) +{ + return (CARD16)((pPci->Slot.l >> 8) & 0xFFFF); +} + +PciStructPtr +findPciDevice(CARD16 vendorID, CARD16 deviceID, char n) +{ + PciStructPtr pPci = CurrentPci; + n++; + + while (pPci) { + if ((pPci->VendorID == vendorID) && (pPci->DeviceID == deviceID)) { + if (!(--n)) break; + } + pPci = pPci->next; + } + return pPci; +} + +PciStructPtr +findPciClass(CARD8 intf, CARD8 subClass, CARD16 class, char n) +{ + PciStructPtr pPci = CurrentPci; + n++; + + while (pPci) { + if ((pPci->Interface == intf) && (pPci->SubClass == subClass) + && (pPci->BaseClass == class)) { + if (!(--n)) break; + } + pPci = pPci->next; + } + return pPci; +} + +static void +readConfigSpaceCfg1(CARD32 bus, CARD32 dev, CARD32 func, CARD32 *reg) +{ + CARD32 config_cmd = PCI_EN | (bus<<16) | + (dev<<11) | (func<<8); + int i; + + for (i = 0; i<64;i+=4) { +#ifdef __alpha__ + reg[i] = axpPciCfgRead(config_cmd | i); +#else + outl(PCI_MODE1_ADDRESS_REG, config_cmd | i); + reg[i] = inl(PCI_MODE1_DATA_REG); +#endif + +#ifdef V86BIOS_DEBUG + P_printf("0x%lx\n",reg[i]); +#endif + } +} + +static int +checkSlotCfg1(CARD32 bus, CARD32 dev, CARD32 func) +{ + CARD32 config_cmd = PCI_EN | (bus<<16) | + (dev<<11) | (func<<8); + CARD32 reg; +#ifdef __alpha__ + reg = axpPciCfgRead(config_cmd); +#else + outl(PCI_MODE1_ADDRESS_REG, config_cmd); + reg = inl(PCI_MODE1_DATA_REG); +#endif + if (reg != 0xFFFFFFFF) + return 1; + else + return 0; +} + +static int +checkSlotCfg2(CARD32 bus, int dev) +{ + CARD32 val; + + outb(PCI_MODE2_ENABLE_REG, 0xF1); + outb(PCI_MODE2_FORWARD_REG, bus); + val = inl(dev << 8); + outb(PCI_MODE2_FORWARD_REG, 0x00); + outb(PCI_MODE2_ENABLE_REG, 0x00); + if (val == 0xFFFFFFFF) + return 0; + if (val == 0xF0F0F0F0) + return 0; + return 1; +} + +static void +readConfigSpaceCfg2(CARD32 bus, int dev, CARD32 *reg) +{ + int i; + + outb(PCI_MODE2_ENABLE_REG, 0xF1); + outb(PCI_MODE2_FORWARD_REG, bus); + for (i = 0; i<64;i+=4) { + reg[i] = inl((dev << 8) + i); +#ifdef V86BIOS_DEBUG + P_printf("0x%lx\n",reg[i]); +#endif + } + outb(PCI_MODE2_ENABLE_REG, 0x00); +} + +static CARD8 +interpretConfigSpace(CARD32 *reg, int busidx, CARD8 dev, CARD8 func) +{ + CARD32 config_cmd; + CARD16 vendor, device; + CARD8 baseclass, subclass; + CARD8 primary, secondary; + CARD8 header, interface; + int i; + + config_cmd = PCI_EN | busidx<<16 | + (dev<<11) | (func<<8); + + for (i = 0x10; i < 0x28; i+=4) { + if (IS_MEM32(reg[i])) + if ((reg[i] & 0xFFFFFFF0) < pciMinMemReg) + pciMinMemReg = (reg[i] & 0xFFFFFFF0); +#ifdef __alpha__ + if (IS_MEM64(reg[i])) { + unsigned long addr = reg[i] | + (unsigned long)(reg[i+4]) << 32; + if ((addr & ~0xfL) < pciMinMemReg) + pciMinMemReg = (addr & ~0xfL); + i+=4; + } +#endif + } + vendor = reg[0] & 0xFFFF; + device = reg[0] >> 16; + P_printf("bus: %i card: %i func %i reg0: 0x%x ", busidx,dev,func,reg[0]); + baseclass = reg[8] >> 24; + subclass = (reg[8] >> 16) & 0xFF; + interface = (reg[8] >> 8) & 0xFF; + + header = (reg[0x0c] >> 16) & 0xff; + P_printf("bc 0x%x, sub 0x%x, if 0x%x, hdr 0x%x\n", + baseclass,subclass,interface,header); + if (BRIDGE_CLASS(baseclass)) { + if (BRIDGE_PCI_CLASS(subclass)) { + PciBusPtr pbp = malloc(sizeof(PciBusRec)); + P_printf("Pci-Pci Bridge found; "); + primary = reg[0x18] & 0xFF; + secondary = (reg[0x18] >> 8) & 0xFF; + P_printf("primary: 0x%x secondary: 0x%x\n", + primary,secondary); + pbp->bctl = reg[0x3c]; + pbp->primary = primary; + pbp->secondary = secondary; + pbp->Slot.l = config_cmd; + pbp->next = PciBuses; + PciBuses = pbp; + numbus++; + } else if (BRIDGE_HOST_CLASS(subclass) + && (hostbridges++ > 1)) { + numbus++; + } + } else if (VIDEO_CLASS(baseclass,subclass)) { + PciStructPtr pcp = malloc(sizeof(PciStructRec)); + P_printf("Display adapter found\n"); + pcp->RomBase = reg[0x30]; + pcp->cmd_st = reg[4]; + pcp->active = (reg[4] & 0x03) == 3 ? 1 : 0; + pcp->VendorID = vendor; + pcp->DeviceID = device; + pcp->Interface = interface; + pcp->BaseClass = baseclass; + pcp->SubClass = subclass; + pcp->Slot.l = config_cmd; + pcp->bus = busidx; + pcp->dev = dev; + pcp->func = func; + pcp->next = PciStruct; + PciStruct = pcp; + } + if ((func == 0) + && ((header & PCI_MULTIFUNC_DEV) == 0)) + func = 8; + else + func++; + return func; +} + +static CARD32 remapMEM_val; +static int remapMEM_num; + +static int /* map it on some other video device */ +remapMem(PciStructPtr pciP, int num, CARD32 size) +{ + PciStructPtr pciPtr = PciStruct; + int i; + CARD32 org; + CARD32 val; + CARD32 size_n; + + org = PciRead32(num + 0x10,pciP->Slot.l); + + while (pciPtr) { + for (i = 0; i < 20; i=i+4) { + + val = PciRead32(i + 0x10,pciPtr->Slot.l); + /* don't map it on itself */ + if ((org & 0xfffffff0) == (val & 0xfffffff0)) + continue; + if (val && !(val & 1)) + PciWrite32(i + 0x10,0xffffffff,pciPtr->Slot.l); + else + continue; + size_n = PciRead32(i + 0x10,pciPtr->Slot.l); + PciWrite32(i + 0x10,val,pciPtr->Slot.l); + size_n = ~(CARD32)(size_n & 0xfffffff0) + 1; + + if (size_n >= size) { + PciWrite32(num + 0x10,val,pciP->Slot.l); + return 1; + } + } + pciPtr = pciPtr->next; + } + /* last resort: try to go below lowest PCI mem address */ + val = ((pciMinMemReg & ~(CARD32)(size - 1)) - size); + if (val > 0x7fffffff) { + PciWrite32(num + 0x10,val, pciP->Slot.l); + return 1; + } + + return 0; +} + +static void +restoreMem(PciStructPtr pciP) +{ + if (remapMEM_val == 0) return; + PciWrite32(remapMEM_num + 0x10,remapMEM_val,pciP->Slot.l); + return; +} + +static CARD32 +findBIOSMap(PciStructPtr pciP, CARD32 *biosSize) +{ + PciStructPtr pciPtr = PciStruct; + int i; + CARD32 val; + CARD32 size; + + PciWrite32(0x30,0xffffffff,pciP->Slot.l); + *biosSize = PciRead32(0x30,pciP->Slot.l); + P_printf("bios size: 0x%x\n",*biosSize); + PciWrite32(0x30,pciP->RomBase,pciP->Slot.l); + *biosSize = ~(*biosSize & 0xFFFFFF00) + 1; + P_printf("bios size masked: 0x%x\n",*biosSize); + if (*biosSize > (1024 * 1024 * 16)) { + *biosSize = 1024 * 1024 * 16; + P_printf("fixing broken BIOS size: 0x%x\n",*biosSize); + } + while (pciPtr) { + if (pciPtr->bus != pciP->bus) { + pciPtr = pciPtr->next; + continue; + } + for (i = 0; i < 20; i=i+4) { + + val = PciRead32(i + 0x10,pciPtr->Slot.l); + if (!(val & 1)) + + PciWrite32(i + 0x10,0xffffffff,pciPtr->Slot.l); + else + continue; + size = PciRead32(i + 0x10,pciPtr->Slot.l); + PciWrite32(i + 0x10,val,pciPtr->Slot.l); + size = ~(CARD32)(size & 0xFFFFFFF0) + 1; +#ifdef V86_BIOS_DEBUG + P_printf("size: 0x%x\n",size); +#endif + if (size >= *biosSize) { + if (pciP == pciPtr) { /* if same device remap ram*/ + if (!(remapMem(pciP,i,size))) + continue; + remapMEM_val = val; + remapMEM_num = i; + } else { + remapMEM_val = 0; + } + return val & 0xFFFFFF00; + } + } + pciPtr = pciPtr->next; + } + remapMEM_val = 0; + /* very last resort */ + if (pciP->bus == 0 && (pciMinMemReg > *biosSize)) + return (pciMinMemReg - size) & ~(size - 1); + + return 0; +} + +int +cfg1out(CARD16 addr, CARD32 val) +{ + if (addr == 0xCF8) { + PciCfg1Addr = val; + return 1; + } else if (addr == 0xCFC) { + writePci(PciCfg1Addr, val); + return 1; + } + return 0; +} + +int +cfg1in(CARD16 addr, CARD32 *val) +{ + if (addr == 0xCF8) { + *val = PciCfg1Addr; + return 1; + } else if (addr == 0xCFC) { + *val = readPci(PciCfg1Addr); + return 1; + } + return 0; +} + +void +list_pci(void) +{ + PciStructPtr pci = PciList; + + while (pci) { + printf("[0x%x:0x%x:0x%x] vendor: 0x%4.4x dev: 0x%4.4x class: 0x%4.4x" + " subclass: 0x%4.4x\n",pci->bus,pci->dev,pci->func, + pci->VendorID,pci->DeviceID,pci->BaseClass,pci->SubClass); + pci = pci->next; + } +} + +PciStructPtr +findPciByIDs(int bus, int dev, int func) +{ + PciStructPtr pciP = PciList; + + while (pciP) { + if (pciP->bus == bus && pciP->dev == dev && pciP->func == func) + return pciP; + pciP = pciP->next; + } + return NULL; +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/pci.h b/board/MAI/bios_emulator/scitech/src/v86bios/pci.h new file mode 100644 index 000000000..58ad52202 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/pci.h @@ -0,0 +1,127 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "v86bios.h" + +#ifndef V86_PCI_H +#define V86_PCI_H + +typedef union { + struct { + unsigned int zero:2; + unsigned int reg:6; + unsigned int func:3; + unsigned int dev:5; + unsigned int bus:8; + unsigned int reserved:7; + unsigned int enable:1; + } pci; + CARD32 l; +} PciSlot; + +typedef struct pciBusRec { + CARD8 primary; + CARD8 secondary; + CARD32 bctl; + PciSlot Slot; + struct pciBusRec *next; + struct pciBusRec *pBus; +} PciBusRec, *PciBusPtr; + +typedef struct pciStructRec { + CARD16 VendorID; + CARD16 DeviceID; + CARD8 Interface; + CARD8 BaseClass; + CARD8 SubClass; + CARD32 RomBase; + CARD32 bus; + CARD8 dev; + CARD8 func; + CARD32 cmd_st; + int active; + PciSlot Slot; + struct pciStructRec *next; + PciBusPtr pBus; +} PciStructRec , *PciStructPtr; + + +extern PciStructPtr CurrentPci; +extern PciStructPtr PciList; +extern PciStructPtr BootBios; +extern int pciMaxBus; + +extern CARD32 findPci(CARD16 slotBX); +extern CARD16 pciSlotBX(PciStructPtr); +PciStructPtr findPciDevice(CARD16 vendorID, CARD16 deviceID, char n); +PciStructPtr findPciClass(CARD8 intf, CARD8 subClass, CARD16 class, char n); + +extern CARD8 PciRead8(int offset, CARD32 slot); +extern CARD16 PciRead16(int offset, CARD32 slot); +extern CARD32 PciRead32(int offset, CARD32 slot); + +extern void PciWrite8(int offset,CARD8 byte, CARD32 slot); +extern void PciWrite16(int offset,CARD16 word, CARD32 slot); +extern void PciWrite32(int offset,CARD32 lg, CARD32 slot); + +extern void scan_pci(void); +extern void pciVideoDisable(void); +extern void pciVideoRestore(void); +extern void EnableCurrent(void); +extern int mapPciRom(PciStructPtr pciP); +extern int cfg1out(CARD16 addr, CARD32 val); +extern int cfg1in(CARD16 addr, CARD32 *val); +extern void list_pci(void); +extern PciStructPtr findPciByIDs(int bus, int dev, int func); + +#define PCI_MODE2_ENABLE_REG 0xCF8 +#define PCI_MODE2_FORWARD_REG 0xCFA +#define PCI_MODE1_ADDRESS_REG 0xCF8 +#define PCI_MODE1_DATA_REG 0xCFC +#if defined(__alpha__) || defined(__sparc__) +#define PCI_EN 0x00000000 +#else +#define PCI_EN 0x80000000 +#endif +#define MAX_DEV_PER_VENDOR_CFG1 32 +#define BRIDGE_CLASS(x) (x == 0x06) +#define BRIDGE_PCI_CLASS(x) (x == 0x04) +#define BRIDGE_HOST_CLASS(x) (x == 0x00) +#define PCI_CLASS_PREHISTORIC 0x00 +#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01 +#define PCI_CLASS_DISPLAY 0x03 +#define PCI_SUBCLASS_DISPLAY_VGA 0x00 +#define PCI_SUBCLASS_DISPLAY_XGA 0x01 +#define PCI_SUBCLASS_DISPLAY_MISC 0x80 +#define VIDEO_CLASS(b,s) \ + (((b) == PCI_CLASS_PREHISTORIC && (s) == PCI_SUBCLASS_PREHISTORIC_VGA) || \ + ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_VGA) ||\ + ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_XGA) ||\ + ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_MISC)) +#define PCI_MULTIFUNC_DEV 0x80 +#define MAX_PCI_DEVICES 64 +#define PCI_MAXBUS 16 +#define PCI_IS_MEM 0x00000001 +#define MAX_PCI_ROM_SIZE (1024 * 1024 * 16) + +#define IS_MEM32(x) ((x & 0x7) == 0 && x != 0) +#define IS_MEM64(x) ((x & 0x7) == 0x4) +#endif diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86.c b/board/MAI/bios_emulator/scitech/src/v86bios/v86.c new file mode 100644 index 000000000..4deed044c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/v86.c @@ -0,0 +1,562 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "debug.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include "v86bios.h" +#include "AsmMacros.h" + +struct vm86_struct vm86s; + +static int vm86_GP_fault(void); +static int vm86_do_int(int num); +static void dump_code(void); +static void dump_registers(void); +static void stack_trace(void); +static int vm86_rep(struct vm86_struct *ptr); + +#define CPU_REG(x) (vm86s.regs.##x) +#define CPU_REG_LW(reg) (*((CARD16 *)&CPU_REG(reg))) +#define CPU_REG_HW(reg) (*((CARD16 *)&CPU_REG(reg) + 1)) +#define CPU_REG_LB(reg) (*(CARD8 *)&CPU_REG(e##reg)) +#define SEG_ADR(type, seg, reg) type((CPU_REG_LW(seg) << 4) \ + + CPU_REG_LW(e##reg)) +#define DF (1 << 10) + +struct pio P; + + +void +setup_io(void) +{ + if (!Config.PrintPort && !Config.IoStatistics) { + P.inb = (CARD8(*)(CARD16))inb; + P.inw = (CARD16(*)(CARD16))inw; + P.inl = (CARD32(*)(CARD16))inl; + P.outb = (void(*)(CARD16,CARD8))outb; + P.outw = (void(*)(CARD16,CARD16))outw; + P.outl = (void(*)(CARD16,CARD32))outl; + } else { + P.inb = p_inb; + P.inw = p_inw; + P.inl = p_inl; + P.outb = p_outb; + P.outw = p_outw; + P.outl = p_outl; + } +} + + +static void +setup_vm86(unsigned long bios_start, i86biosRegsPtr regs) +{ + CARD32 eip; + CARD16 cs; + + vm86s.flags = VM86_SCREEN_BITMAP; + vm86s.flags = 0; + vm86s.screen_bitmap = 0; + vm86s.cpu_type = CPU_586; + memset(&vm86s.int_revectored, 0xff,sizeof(vm86s.int_revectored)) ; + memset(&vm86s.int21_revectored, 0xff,sizeof(vm86s.int21_revectored)) ; + + eip = bios_start & 0xFFFF; + cs = (bios_start & 0xFF0000) >> 4; + + CPU_REG(eax) = regs->ax; + CPU_REG(ebx) = regs->bx; + CPU_REG(ecx) = regs->cx; + CPU_REG(edx) = regs->dx; + CPU_REG(esi) = 0; + CPU_REG(edi) = regs->di; + CPU_REG(ebp) = 0; + CPU_REG(eip) = eip; + CPU_REG(cs) = cs; + CPU_REG(esp) = 0x100; + CPU_REG(ss) = 0x30; /* This is the standard pc bios stack */ + CPU_REG(es) = regs->es; + CPU_REG(ds) = 0x40; /* standard pc ds */ + CPU_REG(fs) = 0; + CPU_REG(gs) = 0; + CPU_REG(eflags) |= (VIF_MASK | VIP_MASK); +} + +void +collect_bios_regs(i86biosRegsPtr regs) +{ + regs->ax = CPU_REG(eax); + regs->bx = CPU_REG(ebx); + regs->cx = CPU_REG(ecx); + regs->dx = CPU_REG(edx); + regs->es = CPU_REG(es); + regs->ds = CPU_REG(ds); + regs->di = CPU_REG(edi); + regs->si = CPU_REG(esi); +} + +static int +do_vm86(void) +{ + int retval; + +#ifdef V86BIOS_DEBUG + dump_registers(); +#endif +/* retval = SYS_vm86old(&vm86s); */ +/* retval = syscall(SYS_vm86old,&vm86s); */ + + retval = vm86_rep(&vm86s); + + switch (VM86_TYPE(retval)) { + case VM86_UNKNOWN: + if (!vm86_GP_fault()) return 0; + break; + case VM86_STI: + fprintf(stderr,"vm86_sti :-((\n"); + stack_trace(); + dump_code(); + return 0; + case VM86_INTx: + if (!vm86_do_int(VM86_ARG(retval))) { + fprintf(stderr,"\nUnknown vm86_int: %X\n\n",VM86_ARG(retval)); + dump_registers(); + return 0; + } + /* I'm not sure yet what to do if we can handle ints */ + break; + case VM86_SIGNAL: + fprintf(stderr,"received signal\n"); + return 0; + default: + fprintf(stderr,"unknown type(0x%x)=0x%x\n", + VM86_ARG(retval),VM86_TYPE(retval)); + dump_registers(); + dump_code(); + stack_trace(); + return 0; + } + + return 1; +} + +static jmp_buf x86_esc; +static void +vmexit(int unused) +{ + longjmp(x86_esc,1); +} + +void +do_x86(unsigned long bios_start, i86biosRegsPtr regs) +{ + static void (*org_handler)(int); + + setup_vm86(bios_start, regs); + if (setjmp(x86_esc) == 0) { + org_handler = signal(2,vmexit); + while(do_vm86()) {}; + signal(2,org_handler); + collect_bios_regs(regs); + } else { + signal(2,org_handler); + printf("interrupted at 0x%x\n",((CARD16)CPU_REG(cs)) << 4 + | (CARD16)CPU_REG(eip)); + } +} + +/* get the linear address */ +#define LIN_PREF_SI ((pref_seg << 4) + CPU_REG_LW(esi)) + +#define LWECX (prefix66 ^ prefix67 ? CPU_REG(ecx) : CPU_REG_LW(ecx)) + +static int +vm86_GP_fault(void) +{ + unsigned char *csp, *lina; + CARD32 org_eip; + int pref_seg; + int done,is_rep,prefix66,prefix67; + + + csp = lina = SEG_ADR((unsigned char *), cs, ip); +#ifdef V86BIOS_DEBUG + printf("exception: \n"); + dump_code(); +#endif + + is_rep = 0; + prefix66 = prefix67 = 0; + pref_seg = -1; + + /* eat up prefixes */ + done = 0; + do { + switch (*(csp++)) { + case 0x66: /* operand prefix */ prefix66=1; break; + case 0x67: /* address prefix */ prefix67=1; break; + case 0x2e: /* CS */ pref_seg=CPU_REG(cs); break; + case 0x3e: /* DS */ pref_seg=CPU_REG(ds); break; + case 0x26: /* ES */ pref_seg=CPU_REG(es); break; + case 0x36: /* SS */ pref_seg=CPU_REG(ss); break; + case 0x65: /* GS */ pref_seg=CPU_REG(gs); break; + case 0x64: /* FS */ pref_seg=CPU_REG(fs); break; + case 0xf2: /* repnz */ + case 0xf3: /* rep */ is_rep=1; break; + default: done=1; + } + } while (!done); + csp--; /* oops one too many */ + org_eip = CPU_REG(eip); + CPU_REG_LW(eip) += (csp - lina); + + switch (*csp) { + + case 0x6c: /* insb */ + /* NOTE: ES can't be overwritten; prefixes 66,67 should use esi,edi,ecx + * but is anyone using extended regs in real mode? */ + /* WARNING: no test for DI wrapping! */ + CPU_REG_LW(edi) += port_rep_inb(CPU_REG_LW(edx), + SEG_ADR((CARD8 *),es,di), + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + if (is_rep) LWECX = 0; + CPU_REG_LW(eip)++; + break; + + case 0x6d: /* (rep) insw / insd */ + /* NOTE: ES can't be overwritten */ + /* WARNING: no test for _DI wrapping! */ + if (prefix66) { + CPU_REG_LW(edi) += port_rep_inl(CPU_REG_LW(edx), + SEG_ADR((CARD32 *),es,di), + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + } + else { + CPU_REG_LW(edi) += port_rep_inw(CPU_REG_LW(edx), + SEG_ADR((CARD16 *),es,di), + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + } + if (is_rep) LWECX = 0; + CPU_REG_LW(eip)++; + break; + + case 0x6e: /* (rep) outsb */ + if (pref_seg < 0) pref_seg = CPU_REG_LW(ds); + /* WARNING: no test for _SI wrapping! */ + CPU_REG_LW(esi) += port_rep_outb(CPU_REG_LW(edx),(CARD8*)LIN_PREF_SI, + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + if (is_rep) LWECX = 0; + CPU_REG_LW(eip)++; + break; + + case 0x6f: /* (rep) outsw / outsd */ + if (pref_seg < 0) pref_seg = CPU_REG_LW(ds); + /* WARNING: no test for _SI wrapping! */ + if (prefix66) { + CPU_REG_LW(esi) += port_rep_outl(CPU_REG_LW(edx), + (CARD32 *)LIN_PREF_SI, + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + } + else { + CPU_REG_LW(esi) += port_rep_outw(CPU_REG_LW(edx), + (CARD16 *)LIN_PREF_SI, + CPU_REG_LW(eflags)&DF, + (is_rep? LWECX:1)); + } + if (is_rep) LWECX = 0; + CPU_REG_LW(eip)++; + break; + + case 0xe5: /* inw xx, inl xx */ + if (prefix66) CPU_REG(eax) = P.inl((int) csp[1]); + else CPU_REG_LW(eax) = P.inw((int) csp[1]); + CPU_REG_LW(eip) += 2; + break; + case 0xe4: /* inb xx */ + CPU_REG_LW(eax) &= ~(CARD32)0xff; + CPU_REG_LB(ax) |= P.inb((int) csp[1]); + CPU_REG_LW(eip) += 2; + break; + case 0xed: /* inw dx, inl dx */ + if (prefix66) CPU_REG(eax) = P.inl(CPU_REG_LW(edx)); + else CPU_REG_LW(eax) = P.inw(CPU_REG_LW(edx)); + CPU_REG_LW(eip) += 1; + break; + case 0xec: /* inb dx */ + CPU_REG_LW(eax) &= ~(CARD32)0xff; + CPU_REG_LB(ax) |= P.inb(CPU_REG_LW(edx)); + CPU_REG_LW(eip) += 1; + break; + + case 0xe7: /* outw xx */ + if (prefix66) P.outl((int)csp[1], CPU_REG(eax)); + else P.outw((int)csp[1], CPU_REG_LW(eax)); + CPU_REG_LW(eip) += 2; + break; + case 0xe6: /* outb xx */ + P.outb((int) csp[1], CPU_REG_LB(ax)); + CPU_REG_LW(eip) += 2; + break; + case 0xef: /* outw dx */ + if (prefix66) P.outl(CPU_REG_LW(edx), CPU_REG(eax)); + else P.outw(CPU_REG_LW(edx), CPU_REG_LW(eax)); + CPU_REG_LW(eip) += 1; + break; + case 0xee: /* outb dx */ + P.outb(CPU_REG_LW(edx), CPU_REG_LB(ax)); + CPU_REG_LW(eip) += 1; + break; + + case 0xf4: +#ifdef V86BIOS_DEBUG + printf("hlt at %p\n", lina); +#endif + return 0; + + case 0x0f: + fprintf(stderr,"CPU 0x0f Trap at eip=0x%lx\n",CPU_REG(eip)); + goto op0ferr; + break; + + case 0xf0: /* lock */ + default: + fprintf(stderr,"unknown reason for exception\n"); + dump_registers(); + stack_trace(); + op0ferr: + dump_code(); + fprintf(stderr,"cannot continue\n"); + return 0; + } /* end of switch() */ + return 1; +} + +static int +vm86_do_int(int num) +{ + int val; + struct regs86 regs; + + i_printf("int 0x%x received: ax:0x%lx",num,CPU_REG(eax)); + if (Config.PrintIp) + i_printf(" at: 0x%x\n",getIP()); + else + i_printf("\n"); + + /* try to run bios interrupt */ + + /* if not installed fall back */ +#define COPY(x) regs.##x = CPU_REG(x) +#define COPY_R(x) CPU_REG(x) = regs.##x + + COPY(eax); + COPY(ebx); + COPY(ecx); + COPY(edx); + COPY(esi); + COPY(edi); + COPY(ebp); + COPY(eip); + COPY(esp); + COPY(cs); + COPY(ss); + COPY(ds); + COPY(es); + COPY(fs); + COPY(gs); + COPY(eflags); + + if (!(val = int_handler(num,®s))) + if (!(val = run_bios_int(num,®s))) + return val; + + COPY_R(eax); + COPY_R(ebx); + COPY_R(ecx); + COPY_R(edx); + COPY_R(esi); + COPY_R(edi); + COPY_R(ebp); + COPY_R(eip); + COPY_R(esp); + COPY_R(cs); + COPY_R(ss); + COPY_R(ds); + COPY_R(es); + COPY_R(fs); + COPY_R(gs); + COPY_R(eflags); + + return val; +#undef COPY +#undef COPY_R +} + +static void +dump_code(void) +{ + int i; + unsigned char *lina = SEG_ADR((unsigned char *), cs, ip); + + fprintf(stderr,"code at 0x%8.8x: ",(CARD32)lina); + for (i=0; i<0x10; i++) + fprintf(stderr,"%2.2x ",*(lina + i)); + fprintf(stderr,"\n "); + for (; i<0x20; i++) + fprintf(stderr,"%2.2x ",*(lina + i)); + fprintf(stderr,"\n"); +} + +#define PRINT(x) fprintf(stderr,#x":%4.4x ",CPU_REG_LW(x)) +#define PRINT_FLAGS(x) fprintf(stderr,#x":%8.8x ",CPU_REG_LW(x)) +static void +dump_registers(void) +{ + PRINT(eip); + PRINT(eax); + PRINT(ebx); + PRINT(ecx); + PRINT(edx); + PRINT(esi); + PRINT(edi); + PRINT(ebp); + fprintf(stderr,"\n"); + PRINT(esp); + PRINT(cs); + PRINT(ss); + PRINT(es); + PRINT(ds); + PRINT(fs); + PRINT(gs); + PRINT_FLAGS(eflags); + fprintf(stderr,"\n"); +} + +static void +stack_trace(void) +{ + int i; + unsigned char *stack = SEG_ADR((unsigned char *), ss, sp); + + fprintf(stderr,"stack at 0x%8.8lx:\n",(unsigned long)stack); + for (i=0; i < 0x10; i++) + fprintf(stderr,"%2.2x ",*(stack + i)); + fprintf(stderr,"\n"); + +} + +static int +vm86_rep(struct vm86_struct *ptr) +{ + + int __res; + + __asm__ __volatile__("int $0x80\n" + :"=a" (__res):"a" ((int)113), + "b" ((struct vm86_struct *)ptr)); + + if ((__res) < 0) { + errno = -__res; + __res=-1; + } + else errno = 0; + return __res; +} + +#define pushw(base, ptr, val) \ +__asm__ __volatile__( \ + "decw %w0\n\t" \ + "movb %h2,(%1,%0)\n\t" \ + "decw %w0\n\t" \ + "movb %b2,(%1,%0)" \ + : "=r" (ptr) \ + : "r" (base), "q" (val), "0" (ptr)) + +int +run_bios_int(int num, struct regs86 *regs) +{ + CARD16 *ssp; + CARD32 sp; + CARD32 eflags; + +#ifdef V86BIOS_DEBUG + static int firsttime = 1; +#endif + /* check if bios vector is initialized */ + if (((CARD16*)0)[(num<<1)+1] == 0x0000) { /* SYS_BIOS_SEG ?*/ +#ifdef V86BIOS_DEBUG + i_printf("card BIOS not loaded\n"); +#endif + return 0; + } + +#ifdef V86BIOS_DEBUG + if (firsttime) { + dprint(0,0x3D0); + firsttime = 0; + } +#endif + + i_printf("calling card BIOS at: "); + ssp = (CARD16*)(CPU_REG(ss)<<4); + sp = (CARD32) CPU_REG_LW(esp); + + eflags = regs->eflags; + eflags = ((eflags & VIF_MASK) != 0) + ? (eflags | IF_MASK) : (eflags & ~(CARD32) IF_MASK); + pushw(ssp, sp, eflags); + pushw(ssp, sp, regs->cs); + pushw(ssp, sp, (CARD16)regs->eip); + regs->esp -= 6; + regs->cs = ((CARD16 *) 0)[(num << 1) + 1]; + regs->eip = (regs->eip & 0xFFFF0000) | ((CARD16 *) 0)[num << 1]; + i_printf("0x%x:%lx\n",regs->cs,regs->eip); +#ifdef V86BIOS_DEBUG + dump_code(); +#endif + regs->eflags = regs->eflags + & ~(VIF_MASK | TF_MASK | IF_MASK | NT_MASK); + return 1; +} + +CARD32 +getIntVect(int num) +{ + return ((CARD32*)0)[num]; +} + +CARD32 +getIP(void) +{ + return (CPU_REG(cs) << 4) + CPU_REG(eip); +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c new file mode 100644 index 000000000..101c1f26e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.c @@ -0,0 +1,933 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#define DELETE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(__alpha__) || defined (__ia64__) +#include +#elif defined(HAVE_SYS_PERM) +#include +#endif +#include "debug.h" +#include "v86bios.h" +#include "pci.h" +#include "AsmMacros.h" + +#define SIZE 0x100000 +#define VRAM_START 0xA0000 +#define VRAM_SIZE 0x1FFFF +#define V_BIOS_SIZE 0x1FFFF +#define BIOS_START 0x7C00 /* default BIOS entry */ +#define BIOS_MEM 0x600 + +/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0, 0xf4 }; */ +#define VB_X(x) (V_BIOS >> x) & 0xFF +CARD8 code[] = { 6, 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xf4 }; +/*CARD8 code[] = { 0x9a, 0x03, 0x00, 0x00, VB_X(12), 0xb8, 0x03, 0x00, */ +/*0xcd, 0x10, 0xf4 }; */ +/*CARD8 code[] = { 0xb8 , 0xf0 , 0xf0 ,0xf4 }; */ + +int ioperm_list[IOPERM_BITS] = {0,}; + +static void sig_handler(int); +static int map(void); +static void unmap(void); +static void bootBIOS(CARD16 ax); +static int map_vram(void); +static void unmap_vram(void); +static int copy_vbios(memType v_base); +static int copy_sys_bios(void); +static void save_bios_to_file(void); +static int setup_system_bios(void); +static CARD32 setup_int_vect(void); +#ifdef __ia32__ +static CARD32 setup_primary_int_vect(void); +#endif +static int chksum(CARD8 *start); +static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax); +static void print_regs(i86biosRegsPtr regs); +static void print_usage(void); +static void set_hlt(Bool set); +static void set_ioperm(void); + +extern void yyparse(); + +void loadCodeToMem(unsigned char *ptr, CARD8 *code); +void dprint(unsigned long start, unsigned long size); + +static int vram_mapped = 0; +static char* bios_var = NULL; +static CARD8 save_msr; +static CARD8 save_pos102; +static CARD8 save_vse; +static CARD8 save_46e8; +static haltpoints hltp[20] = { {0, 0}, }; + +console Console = {-1,-1}; +struct config Config; + +int main(int argc,char **argv) +{ + int c; + + Config.PrintPort = PRINT_PORT; + Config.IoStatistics = IO_STATISTICS; + Config.PrintIrq = PRINT_IRQ; + Config.PrintPci = PRINT_PCI; + Config.ShowAllDev = SHOW_ALL_DEV; + Config.PrintIp = PRINT_IP; + Config.SaveBios = SAVE_BIOS; + Config.Trace = TRACE; + Config.ConfigActiveOnly = CONFIG_ACTIVE_ONLY; /* boot */ + Config.ConfigActiveDevice = CONFIG_ACTIVE_DEVICE; /* boot */ + Config.MapSysBios = MAP_SYS_BIOS; + Config.Resort = RESORT; /* boot */ + Config.FixRom = FIX_ROM; + Config.NoConsole = NO_CONSOLE; + Config.BootOnly = FALSE; + Config.Verbose = VERBOSE; + + opterr = 0; + while ((c = getopt(argc,argv,"psicaPStAdbrfnv:?")) != EOF) { + switch(c) { + case 'p': + Config.PrintPort = TRUE; + break; + case 's': + Config.IoStatistics = TRUE; + break; + case 'i': + Config.PrintIrq = TRUE; + break; + case 'c': + Config.PrintPci = TRUE; + break; + case 'a': + Config.ShowAllDev = TRUE; + break; + case 'P': + Config.PrintIp = TRUE; + break; + case 'S': + Config.SaveBios = TRUE; + break; + case 't': + Config.Trace = TRUE; + break; + case 'A': + Config.ConfigActiveOnly = TRUE; + break; + case 'd': + Config.ConfigActiveDevice = TRUE; + break; + case 'b': + Config.MapSysBios = TRUE; + break; + case 'r': + Config.Resort = TRUE; + break; + case 'f': + Config.FixRom = TRUE; + break; + case 'n': + Config.NoConsole = TRUE; + break; + case 'v': + Config.Verbose = strtol(optarg,NULL,0); + break; + case '?': + print_usage(); + break; + default: + break; + } + } + + + if (!map()) + exit(1); + + if (!setup_system_bios()) + exit(1); + + iopl(3); + + scan_pci(); + + save_msr = inb(0x3CC); + save_vse = inb(0x3C3); + save_46e8 = inb(0x46e8); + save_pos102 = inb(0x102); + + if (Config.BootOnly) { + + if (!CurrentPci && !Config.ConfigActiveDevice + && !Config.ConfigActiveOnly) { + iopl(0); + unmap(); + exit (1); + } + call_boot(NULL); + } else { + using_history(); + yyparse(); + } + + unmap(); + + pciVideoRestore(); + + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + + iopl(0); + + close_console(Console); + + exit(0); +} + + +void +call_boot(struct device *dev) +{ + int Active_is_Pci = 0; + CARD32 vbios_base; + + CurrentPci = PciList; + Console = open_console(); + + set_ioperm(); + + + signal(2,sig_handler); + signal(11,sig_handler); + + /* disable primary card */ + pciVideoRestore(); /* reset PCI state to see primary card */ + outb(0x3C2,~(CARD8)0x03 & save_msr); + outb(0x3C3,~(CARD8)0x01 & save_vse); + outb(0x46e8, ~(CARD8)0x08 & save_46e8); + outb(0x102, ~(CARD8)0x01 & save_pos102); + + pciVideoDisable(); + + while (CurrentPci) { + CARD16 ax; + + if (CurrentPci->active) { + Active_is_Pci = 1; + if (!Config.ConfigActiveDevice && !dev) { + CurrentPci = CurrentPci->next; + continue; + } + } else if (Config.ConfigActiveOnly && !dev) { + CurrentPci = CurrentPci->next; + continue; + } + if (dev && ((dev->type != PCI) + || (dev->type == PCI + && (dev->loc.pci.dev != CurrentPci->dev + || dev->loc.pci.bus != CurrentPci->bus + || dev->loc.pci.func != CurrentPci->func)))) { + CurrentPci = CurrentPci->next; + continue; + } + + EnableCurrent(); + + if (CurrentPci->active) { + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + } + + /* clear interrupt vectors */ +#ifdef __ia32__ + vbios_base = CurrentPci->active ? setup_primary_int_vect() + : setup_int_vect(); +#else + vbios_base = setup_int_vect(); +#endif + ax = ((CARD16)(CurrentPci->bus) << 8) + | (CurrentPci->dev << 3) | (CurrentPci->func & 0x7); + if (Config.Verbose > 1) P_printf("ax: 0x%x\n",ax); + + BootBios = findPciByIDs(CurrentPci->bus,CurrentPci->dev, + CurrentPci->func); + if (!((mapPciRom(BootBios) && chksum((CARD8*)V_BIOS)) + || (CurrentPci->active && copy_vbios(vbios_base)))) { + CurrentPci = CurrentPci->next; + continue; + } + if (!map_vram()) { + CurrentPci = CurrentPci->next; + continue; + } + if (Config.SaveBios) save_bios_to_file(); + printf("initializing PCI bus: %i dev: %i func: %i\n",CurrentPci->bus, + CurrentPci->dev,CurrentPci->func); + bootBIOS(ax); + unmap_vram(); + + if (CurrentPci->active) + close_console(Console); + + if (dev) return; + + CurrentPci = CurrentPci->next; + } + + /* We have an ISA device - configure if requested */ + if (!Active_is_Pci /* no isa card in system! */ + && ((!dev && (Config.ConfigActiveDevice || Config.ConfigActiveOnly)) + || (dev && dev->type == ISA))) { + + pciVideoDisable(); + + if (!dev || dev->type == ISA) { + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + +#ifdef __ia32__ + vbios_base = setup_primary_int_vect(); +#else + vbios_base = setup_int_vect(); +#endif + if (copy_vbios(vbios_base)) { + + if (Config.SaveBios) save_bios_to_file(); + if (map_vram()) { + printf("initializing ISA bus\n"); + bootBIOS(0); + } + } + + unmap_vram(); + sleep(1); + close_console(Console); + } + } + + +} + +int +map(void) +{ + void* mem; + mem = mmap(0, (size_t)SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, + MAP_FIXED | MAP_PRIVATE | MAP_ANON, + -1, 0 ); + if (mem != 0) { + perror("anonymous map"); + return (0); + } + memset(mem,0,SIZE); + + return (1); +} + +static void +unmap(void) +{ + munmap(0,SIZE); +} + +static void +bootBIOS(CARD16 ax) +{ + i86biosRegs bRegs; +#ifdef V86BIOS_DEBUG + printf("starting BIOS\n"); +#endif + setup_io(); + setup_bios_regs(&bRegs, ax); + loadCodeToMem((unsigned char *) BIOS_START, code); + do_x86(BIOS_START,&bRegs); +#ifdef V86BIOS_DEBUG + printf("done\n"); +#endif +} + +static int +map_vram(void) +{ + int mem_fd; + +#ifdef __ia64__ + if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) +#else + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) +#endif + { + perror("opening memory"); + return 0; + } + +#ifdef __alpha__ + if (!_bus_base()) sparse_shift = 7; /* Uh, oh, JENSEN... */ + if (!_bus_base_sparse()) sparse_shift = 0; + if ((vram_map = mmap(0,(size_t) (VRAM_SIZE << sparse_shift), + PROT_READ | PROT_WRITE, + MAP_SHARED, + mem_fd, (VRAM_START << sparse_shift) + | _bus_base_sparse())) == (void *) -1) +#else + if (mmap((void *) VRAM_START, (size_t) VRAM_SIZE, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED | MAP_FIXED, + mem_fd, VRAM_START) == (void *) -1) +#endif + { + perror("mmap error in map_hardware_ram (1)"); + close(mem_fd); + return (0); + } + vram_mapped = 1; + close(mem_fd); + return (1); +} + +static void +unmap_vram(void) +{ + if (!vram_mapped) return; + + munmap((void*)VRAM_START,VRAM_SIZE); + vram_mapped = 0; +} + +static int +copy_vbios(memType v_base) +{ + int mem_fd; + unsigned char *tmp; + int size; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) v_base, SEEK_SET) != (off_t) v_base) { + fprintf(stderr,"Cannot lseek\n"); + goto Error; + } + tmp = (unsigned char *)malloc(3); + if (read(mem_fd, (char *)tmp, (size_t) 3) != (size_t) 3) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + if (lseek(mem_fd,(off_t) v_base,SEEK_SET) != (off_t) v_base) + goto Error; + + if (*tmp != 0x55 || *(tmp+1) != 0xAA ) { + fprintf(stderr,"No bios found at: 0x%lx\n",v_base); + goto Error; + } +#ifdef DEBUG + dprint((unsigned long)tmp,0x100); +#endif + size = *(tmp+2) * 512; + + if (read(mem_fd, (char *)v_base, (size_t) size) != (size_t) size) { + fprintf(stderr,"Cannot read\n"); + goto Error; + } + free(tmp); + close(mem_fd); + if (!chksum((CARD8*)v_base)) + return (0); + + return (1); + +Error: + perror("v_bios"); + close(mem_fd); + return (0); +} + +static int +copy_sys_bios(void) +{ +#define SYS_BIOS 0xF0000 + int mem_fd; + + if ((mem_fd = open(MEM_FILE,O_RDONLY))<0) { + perror("opening memory"); + return (0); + } + + if (lseek(mem_fd,(off_t) SYS_BIOS,SEEK_SET) != (off_t) SYS_BIOS) + goto Error; + if (read(mem_fd, (char *)SYS_BIOS, (size_t) 0xFFFF) != (size_t) 0xFFFF) + goto Error; + + close(mem_fd); + return (1); + +Error: + perror("sys_bios"); + close(mem_fd); + return (0); +} + +void +loadCodeToMem(unsigned char *ptr, CARD8 code[]) +{ + int i; + CARD8 val; + int size = code[0]; + + for ( i=1;i<=size;i++) { + val = code[i]; + *ptr++ = val; + } + return; +} + +void +dprint(unsigned long start, unsigned long size) +{ + int i,j; + char *c = (char *)start; + + for (j = 0; j < (size >> 4); j++) { + char *d = c; + printf("\n0x%lx: ",(unsigned long)c); + for (i = 0; i<16; i++) + printf("%2.2x ",(unsigned char) (*(c++))); + c = d; + for (i = 0; i<16; i++) { + printf("%c",((((CARD8)(*c)) > 32) && (((CARD8)(*c)) < 128)) ? + (unsigned char) (*(c)): '.'); + c++; + } + } + printf("\n"); +} + +static void +save_bios_to_file(void) +{ + static int num = 0; + int size, count; + char file_name[256]; + int fd; + + sprintf(file_name,"bios_%i.fil",num); + if ((fd = open(file_name,O_WRONLY | O_CREAT | O_TRUNC,00644)) == -1) + return; + size = (*(unsigned char*)(V_BIOS + 2)) * 512; +#ifdef V86BIOS_DEBUG + dprint(V_BIOS,20); +#endif + if ((count = write(fd,(void *)(V_BIOS),size)) != size) + fprintf(stderr,"only saved %i of %i bytes\n",size,count); + num++; +} + +static void +sig_handler(int unused) +{ + fflush(stdout); + fflush(stderr); + + /* put system back in a save state */ + unmap_vram(); + pciVideoRestore(); + outb(0x102, save_pos102); + outb(0x46e8, save_46e8); + outb(0x3C3, save_vse); + outb(0x3C2, save_msr); + + close_console(Console); + iopl(0); + unmap(); + + exit(1); +} + +/* + * For initialization we just pass ax to the BIOS. + * PCI BIOSes need this. All other register are set 0. + */ +static void setup_bios_regs(i86biosRegsPtr regs, CARD32 ax) +{ + regs->ax = ax; + regs->bx = 0; + regs->cx = 0; + regs->dx = 0; + regs->es = 0; + regs->ds = 0x40; /* standard pc ds */ + regs->si = 0; + regs->di = 0; +} + +/* + * here we are really paranoid about faking a "real" + * BIOS. Most of this information was pulled from + * dosem. + */ + +#ifdef __ia32__ +static CARD32 +setup_primary_int_vect(void) +{ + int mem_fd; + CARD32 vbase; + void *map; + + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) + { + perror("opening memory"); + return (0); + } + + if ((map = mmap((void *) 0, (size_t) 0x2000, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, + mem_fd, 0)) == (void *)-1) { + perror("mmap error in map_hardware_ram (2)"); + close(mem_fd); + return (0); + } + + close(mem_fd); + memcpy(0,map,BIOS_MEM); + munmap(map,0x2000); + /* + * create a backup copy of the bios variables to write back the + * modified values + */ + if (!bios_var) + bios_var = (char *)malloc(BIOS_MEM); + memcpy(bios_var,0,BIOS_MEM); + + vbase = (*((CARD16*)(0x10 << 2) + 1)) << 4; + if (Config.Verbose > 0) printf("vbase: 0x%x\n",vbase); + return vbase; +} +#endif + +static CARD32 +setup_int_vect(void) +{ + const CARD16 cs = 0x0; + const CARD16 ip = 0x0; + int i; + + /* let the int vects point to the SYS_BIOS seg */ + for (i=0; i<0x80; i++) { + ((CARD16*)0)[i<<1] = ip; + ((CARD16*)0)[(i<<1)+1] = cs; + } + /* video interrupts default location */ + ((CARD16*)0)[(0x42<<1)+1] = 0xf000; + ((CARD16*)0)[0x42<<1] = 0xf065; + ((CARD16*)0)[(0x10<<1)+1] = 0xf000; + ((CARD16*)0)[0x10<<1] = 0xf065; + /* video param table default location (int 1d) */ + ((CARD16*)0)[(0x1d<<1)+1] = 0xf000; + ((CARD16*)0)[0x1d<<1] = 0xf0A4; + /* font tables default location (int 1F) */ + ((CARD16*)0)[(0x1f<<1)+1] = 0xf000; + ((CARD16*)0)[0x1f<<1] = 0xfa6e; + + /* int 11 default location */ + ((CARD16*)0)[(0x11<<1)+1] = 0xf000; + ((CARD16*)0)[0x11<<1] = 0xf84d; + /* int 12 default location */ + ((CARD16*)0)[(0x12<<1)+1] = 0xf000; + ((CARD16*)0)[0x12<<1] = 0xf841; + /* int 15 default location */ + ((CARD16*)0)[(0x15<<1)+1] = 0xf000; + ((CARD16*)0)[0x15<<1] = 0xf859; + /* int 1A default location */ + ((CARD16*)0)[(0x1a<<1)+1] = 0xf000; + ((CARD16*)0)[0x1a<<1] = 0xff6e; + /* int 05 default location */ + ((CARD16*)0)[(0x05<<1)+1] = 0xf000; + ((CARD16*)0)[0x05<<1] = 0xff54; + /* int 08 default location */ + ((CARD16*)0)[(0x8<<1)+1] = 0xf000; + ((CARD16*)0)[0x8<<1] = 0xfea5; + /* int 13 default location (fdd) */ + ((CARD16*)0)[(0x13<<1)+1] = 0xf000; + ((CARD16*)0)[0x13<<1] = 0xec59; + /* int 0E default location */ + ((CARD16*)0)[(0xe<<1)+1] = 0xf000; + ((CARD16*)0)[0xe<<1] = 0xef57; + /* int 17 default location */ + ((CARD16*)0)[(0x17<<1)+1] = 0xf000; + ((CARD16*)0)[0x17<<1] = 0xefd2; + /* fdd table default location (int 1e) */ + ((CARD16*)0)[(0x1e<<1)+1] = 0xf000; + ((CARD16*)0)[0x1e<<1] = 0xefc7; + return V_BIOS; +} + +static int +setup_system_bios(void) +{ + char *date = "06/01/99"; + char *eisa_ident = "PCI/ISA"; + + if (Config.MapSysBios) { + + if (!copy_sys_bios()) return 0; + return 1; + + } else { + +/* memset((void *)0xF0000,0xf4,0xfff7); */ + + /* + * we trap the "industry standard entry points" to the BIOS + * and all other locations by filling them with "hlt" + * TODO: implement hlt-handler for these + */ + memset((void *)0xF0000,0xf4,0x10000); + + /* + * TODO: we should copy the fdd table (0xfec59-0xfec5b) + * the video parameter table (0xf0ac-0xf0fb) + * and the font tables (0xfa6e-0xfe6d) + * from the original bios here + */ + + /* set bios date */ + strcpy((char *)0xFFFF5,date); + /* set up eisa ident string */ + strcpy((char *)0xFFFD9,eisa_ident); + /* write system model id for IBM-AT */ + ((char *)0)[0xFFFFE] = 0xfc; + + return 1; + } + +} + +static void +update_bios_vars(void) +{ + int mem_fd; + void *map; + memType i; + +#ifdef __ia64__ + if ((mem_fd = open(MEM_FILE,O_RDWR | O_SYNC))<0) +#else + if ((mem_fd = open(MEM_FILE,O_RDWR))<0) +#endif + { + perror("opening memory"); + return; + } + + if ((map = mmap((void *) 0, (size_t) 0x2000, + PROT_EXEC | PROT_READ | PROT_WRITE, MAP_SHARED, + mem_fd, 0)) == (void *)-1) { + perror("mmap error in map_hardware_ram (3)"); + close(mem_fd); + return; + } + + for (i = 0; i < BIOS_MEM; i++) { + if (bios_var[i] != *(CARD8*)i) + *((CARD8*)map + i) = *(CARD8*)i; + } + + munmap(map,0x2000); + close(mem_fd); +} + +static int +chksum(CARD8 *start) +{ + CARD16 size; + CARD8 val = 0; + int i; + + size = *(start+2) * 512; + for (i = 0; iactive)) || !isVideo) { + CARD32 vbios_base; + +#ifdef __ia32__ + if (!(vbios_base = setup_primary_int_vect())) +#else + if (!(vbios_base = setup_int_vect())) +#endif + return; + if (!copy_vbios(vbios_base)) + return; + } + + if (!map_vram()) + return; + +#ifdef V86BIOS_DEBUG + printf("starting BIOS\n"); +#endif + loadCodeToMem((unsigned char *) BIOS_START, code_int); + setup_io(); + print_regs(Regs); + set_ioperm(); + set_hlt(TRUE); + do_x86(BIOS_START,Regs); + set_hlt(FALSE); + print_regs(Regs); + +#ifdef V86BIOS_DEBUG + printf("done\n"); +#endif + + if ((isVideo && (!CurrentPci || CurrentPci->active)) || !isVideo) + update_bios_vars(); +} + +static void +print_regs(i86biosRegsPtr regs) +{ + printf("ax=%x bx=%x cx=%x dx=%x ds=%x es=%x di=%x si=%x\n", + (CARD16)regs->ax,(CARD16)regs->bx,(CARD16)regs->cx,(CARD16)regs->dx, + (CARD16)regs->ds,(CARD16)regs->es,(CARD16)regs->di, + (CARD16)regs->si); +} + +static void +print_usage(void) +{ +} + +void +add_hlt(unsigned long val) +{ + int i; + + if (val < BIOS_MEM || (val > VRAM_START && val < (VRAM_START + VRAM_SIZE)) + || val >= SIZE) { + printf("address out of range\n"); + return; + } + + for (i=0; i<20; i++) { + if (hltp[i].address == 0) { + hltp[i].address = (void*)val; + break; + } + } + if (i == 20) printf("no more hltpoints available\n"); +} + +void +del_hlt(int val) +{ + if (val == 21) { /* delete all */ + int i; + printf("clearing all hltpoints\n"); + for (i=0; i <20; i++) + hltp[i].address = NULL; + } else if (val >= 0 && val <20) + hltp[val].address = NULL; + else printf("hltpoint %i out of range: valid range 0-19\n",val); +} + +void +list_hlt() +{ + int i; + for (i=0; i<20; i++) + if (hltp[i].address) + printf("hltpoint[%i]: 0x%lx\n",i,(unsigned long)hltp[i].address); +} + +static void +set_hlt(Bool set) +{ + int i; + for (i=0; i<20; i++) + if (hltp[i].address) { + if (set) { + hltp[i].orgval = *(CARD8*)hltp[i].address; + *(CARD8*)hltp[i].address = 0xf4; + } else + *(CARD8*)hltp[i].address = hltp[i].orgval; + } +} + +static void +set_ioperm(void) +{ + int i, start; + + ioperm(0,IOPERM_BITS,0); + + for (i = 0; i < IOPERM_BITS;i++) + if (ioperm_list[i]) { + start = i; + for (;i < IOPERM_BITS; i++) { + if (!ioperm_list[i]) { + ioperm(start,i - start, 1); + break; + } + } + } +} diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h new file mode 100644 index 000000000..a8f3f8e64 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/v86bios.h @@ -0,0 +1,214 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef V86_BIOS_H +#define V86_BIOS_H + +#if defined (__i386__) || defined (__i486__) || defined (__i586__) || defined (__i686__) || defined (__k6__) +# ifndef __ia32__ +# define __ia32__ +# endif +#endif + +#include + +#define p_printf(f,a...) do {if (Config.PrintPort) lprintf(f,##a);} \ + while(0) +#define i_printf(f,a...) do {if (Config.PrintIrq) lprintf(f,##a);} \ + while(0) +#define P_printf(f,a...) do {if (Config.PrintPci) lprintf(f,##a);} \ + while(0) + +typedef unsigned char CARD8; +typedef unsigned short CARD16; +typedef unsigned int CARD32; +#if defined (__alpha__) || defined (__ia64__) +typedef unsigned long memType; +#else +typedef unsigned int memType; +#endif + +typedef int Bool; + +#define FALSE 0 +#define TRUE 1 + +struct config { + Bool PrintPort; + Bool IoStatistics; + Bool PrintIrq; + Bool PrintPci; + Bool ShowAllDev; + Bool PrintIp; + Bool SaveBios; + Bool Trace; + Bool ConfigActiveOnly; + Bool ConfigActiveDevice; + Bool MapSysBios; + Bool Resort; + Bool FixRom; + Bool NoConsole; + Bool BootOnly; + int Verbose; +}; + +struct pio { + CARD8 (*inb)(CARD16); + CARD16 (*inw)(CARD16); + CARD32 (*inl)(CARD16); + void (*outb)(CARD16,CARD8); + void (*outw)(CARD16,CARD16); + void (*outl)(CARD16,CARD32); +}; + +struct regs86 { + long ebx; + long ecx; + long edx; + long esi; + long edi; + long ebp; + long eax; + long eip; + long esp; + unsigned short cs; + unsigned short ss; + unsigned short es; + unsigned short ds; + unsigned short fs; + unsigned short gs; + long eflags; +}; + +typedef struct { + CARD32 ax; + CARD32 bx; + CARD32 cx; + CARD32 dx; + CARD32 cs; + CARD32 es; + CARD32 ds; + CARD32 si; + CARD32 di; +} i86biosRegs, *i86biosRegsPtr; + +typedef struct { + int fd; + int vt; +} console; + +typedef struct { + void* address; + CARD8 orgval; +} haltpoints; + +enum dev_type { NONE, ISA, PCI }; +struct device { + Bool booted; + enum dev_type type; + union { + int none; + struct pci { + int bus; + int dev; + int func; + } pci; + } loc; +}; + +extern struct device Device; + +#ifdef __alpha__ +unsigned long _bus_base(void); +extern void* vram_map; +extern int sparse_shift; +#endif + +extern struct pio P; +extern struct config Config; +#define IOPERM_BITS 1024 +extern int ioperm_list[IOPERM_BITS]; + +extern void setup_io(void); +extern void do_x86(unsigned long bios_start,i86biosRegsPtr regs); +extern int run_bios_int(int num, struct regs86 *regs); +extern CARD32 getIntVect(int num); +CARD32 getIP(void); + +extern void call_boot(struct device *dev); +extern void runINT(int num,i86biosRegsPtr Regs); +extern void add_hlt(unsigned long addr); +extern void del_hlt(int addr); +extern void list_hlt(); + +extern int port_rep_inb(CARD16 port, CARD8 *base, int d_f, CARD32 count); +extern int port_rep_inw(CARD16 port, CARD16 *base, int d_f, CARD32 count); +extern int port_rep_inl(CARD16 port, CARD32 *base, int d_f, CARD32 count); +extern int port_rep_outb(CARD16 port, CARD8 *base, int d_f, CARD32 count); +extern int port_rep_outw(CARD16 port, CARD16 *base, int d_f, CARD32 count); +extern int port_rep_outl(CARD16 port, CARD32 *base, int d_f, CARD32 count); +extern CARD8 p_inb(CARD16 port); +extern CARD16 p_inw(CARD16 port); +extern CARD32 p_inl(CARD16 port); +extern void p_outb(CARD16 port, CARD8 val); +extern void p_outw(CARD16 port, CARD16 val); +extern void p_outl(CARD16 port, CARD32 val); +#ifdef __alpha__ +extern CARD8 a_inb(CARD16 port); +extern CARD16 a_inw(CARD16 port); +extern void a_outb(CARD16 port, CARD8 val); +extern void a_outw(CARD16 port, CARD16 val); +#endif +#ifdef __alpha__ +CARD8 mem_rb(CARD32 addr); +CARD16 mem_rw(CARD32 addr); +CARD32 mem_rl(CARD32 addr); +void mem_wb(CARD32 addr, CARD8 val); +void mem_ww(CARD32 addr, CARD16 val); +void mem_wl(CARD32 addr, CARD32 val); +#endif +extern void io_statistics(void); +extern void clear_stat(void); +extern int int_handler(int num, struct regs86 *regs); + +extern console open_console(void); +extern void close_console(console); + +extern void dprint(unsigned long start, unsigned long size); + +extern Bool logging; +extern Bool nostdout; +extern char* logfile; +extern void logon(void* ptr); +extern void logoff(); +extern void lprintf(const char *f, ...); + +#define MEM_FILE "/dev/mem" +#define DEFAULT_V_BIOS 0xc0000 +#ifndef V_BIOS +#define V_BIOS DEFAULT_V_BIOS +#endif + +#ifdef __alpha__ +#define NEED_PCI_IO +#endif + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/working_cards b/board/MAI/bios_emulator/scitech/src/v86bios/working_cards new file mode 100644 index 000000000..7753f2495 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/working_cards @@ -0,0 +1,7 @@ +David Monro: Trident TGUI 9440 + Virge/VX (Diamond Stealth 3D 3400) + Riva TNT (Diamond Viper V550) no vbios? +Jarno Paananen : Guillemot Maxigamer Xentor 32 + (NVIDIA TNT2 Ultra) + Creative Graphics Blaster Exxtreme + (Permedia 2) diff --git a/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c b/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c new file mode 100644 index 000000000..b5c99d7a7 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/v86bios/x86emu.c @@ -0,0 +1,316 @@ +/* + * Copyright 1999 Egbert Eich + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of the authors not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. The authors makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ +#include "debug.h" + +#define IF_MASK 0x00000200 +#define VIF_MASK 0x00080000 /* virtual interrupt flag */ +#define VIP_MASK 0x00100000 /* virtual interrupt pending */ + +#include +#include +#include +/*#include */ +#include +#include +#include +#include +#ifdef __alpha__ +#include +#endif +#include +#include +#include "AsmMacros.h" +#include "v86bios.h" +# define DEBUG +#include "x86emu.h" +#undef DEBUG + +#define M _X86EMU_env +#define CPU_REG(reg) M.x86.R_##reg + +struct pio P; + +void +setup_io(void) +{ + if (!Config.PrintPort && !Config.IoStatistics) { + +#if defined (__i386__) + P.inb = (u8(*)(u16))inb; + P.inw = (u16(*)(u16))inw; + P.outb = (void(*)(u16,u8))outb; + P.outw = (void(*)(u16,u16))outw; +#else + P.inb = p_inb; + P.inw = p_inw; + P.outb = p_outb; + P.outw = p_outw; +#endif +#if defined (__i386__) && ! defined(NEED_PCI_IO) + P.inl = (u32(*)(u16))inl; + P.outl = (void(*)(u16,u32))outl; +#else + P.inl = p_inl; + P.outl = p_outl; +#endif + } else { + P.inb = p_inb; + P.inw = p_inw; + P.inl = p_inl; + P.outb = p_outb; + P.outw = p_outw; + P.outl = p_outl; + } +} + +void +x86emu_do_int(int num) +{ + struct regs86 regs; + + i_printf("int 0x%x received: ax:0x%x",num,CPU_REG(AX)); + if (Config.PrintIp) + i_printf(" at: 0x%x\n",getIP()); + else + i_printf("\n"); + + /* try to run bios interrupt */ + + /* if not installed fall back */ +#define COPY(x,y) regs.y = M.x86.x +#define COPY_R(x,y) M.x86.x = regs.y + + COPY(R_EAX,eax); + COPY(R_EBX,ebx); + COPY(R_ECX,ecx); + COPY(R_EDX,edx); + COPY(R_ESI,esi); + COPY(R_EDI,edi); + COPY(R_EBP,ebp); + COPY(R_EIP,eip); + COPY(R_ESP,esp); + COPY(R_CS,cs); + COPY(R_SS,ss); + COPY(R_DS,ds); + COPY(R_ES,es); + COPY(R_FS,fs); + COPY(R_GS,gs); + COPY(R_EFLG,eflags); + + if (!(int_handler(num,®s))) { + if (!run_bios_int(num,®s)) + goto unknown_int; + else + return; + } + + COPY_R(R_EAX,eax); + COPY_R(R_EBX,ebx); + COPY_R(R_ECX,ecx); + COPY_R(R_EDX,edx); + COPY_R(R_ESI,esi); + COPY_R(R_EDI,edi); + COPY_R(R_EBP,ebp); + COPY_R(R_EIP,eip); + COPY_R(R_ESP,esp); + COPY_R(R_CS,cs); + COPY_R(R_SS,ss); + COPY_R(R_DS,ds); + COPY_R(R_ES,es); + COPY_R(R_FS,fs); + COPY_R(R_GS,gs); + COPY_R(R_EFLG,eflags); + return; + + unknown_int: + fprintf(stderr,"\nUnknown vm86_int: %X\n\n",num); + X86EMU_halt_sys(); + return; + +#undef COPY +#undef COPY_R +} + +void +setup_x86emu(unsigned long bios_start, i86biosRegsPtr regs) +{ + int i; + CARD32 eip; + CARD16 cs; + X86EMU_intrFuncs intFuncs[256]; + + X86EMU_pioFuncs pioFuncs = { + (u8(*)(u16))P.inb, + (u16(*)(u16))P.inw, + (u32(*)(u16))P.inl, + (void(*)(u16,u8))P.outb, + (void(*)(u16,u16))P.outw, + (void(*)(u16,u32))P.outl + }; +#ifdef __alpha__ + X86EMU_memFuncs memFuncs = { + (u8(*)(u32))mem_rb, + (u16(*)(u32))mem_rw, + (u32(*)(u32))mem_rl, + (void(*)(u32,u8))mem_wb, + (void(*)(u32,u16))mem_ww, + (void(*)(u32,u32))mem_wl + }; +#endif + M.mem_base = 0; + M.mem_size = 1024*1024 + 1024; + /* M.x86.debug = DEBUG_DISASSEMBLE_F | DEBUG_TRACE_F | DEBUG_DECODE_F; */ + /* M.x86.debug |= DEBUG_DECODE_F | DEBUG_TRACE_F; */ +/* + * For single step tracing compile x86emu with option -DDEBUG + */ + M.x86.debug = 0; + if (Config.PrintIp) + M.x86.debug = DEBUG_SAVE_CS_IP; + + if (Config.Trace) + X86EMU_trace_on(); + + X86EMU_setupPioFuncs(&pioFuncs); +#ifdef __alpha__ + X86EMU_setupMemFuncs(&memFuncs); +#endif + for (i=0;i<256;i++) + intFuncs[i] = x86emu_do_int; + X86EMU_setupIntrFuncs(intFuncs); + + eip = bios_start & 0xFFFF; + cs = (bios_start & 0xFF0000) >> 4; + + CPU_REG(EAX) = regs->ax; + CPU_REG(EBX) = regs->bx; + CPU_REG(ECX) = regs->cx; + CPU_REG(EDX) = regs->dx; + CPU_REG(ESI) = regs->si; + CPU_REG(EDI) = regs->di; + CPU_REG(EBP) = 0; + CPU_REG(EIP) = eip; + CPU_REG(CS) = cs; + CPU_REG(SP) = 0x100; + CPU_REG(SS) = 0x30; /* This is the standard pc bios stack */ + CPU_REG(ES) = regs->es; + CPU_REG(DS) = regs->ds; + CPU_REG(FS) = 0; + CPU_REG(GS) = 0; + CPU_REG(EFLG) |= (VIF_MASK | VIP_MASK | IF_MASK | 0x2); +} + +void +collect_bios_regs(i86biosRegsPtr regs) +{ + regs->ax = CPU_REG(EAX); + regs->bx = CPU_REG(EBX); + regs->cx = CPU_REG(ECX); + regs->dx = CPU_REG(EDX); + regs->es = CPU_REG(ES); + regs->ds = CPU_REG(DS); + regs->di = CPU_REG(EDI); + regs->si = CPU_REG(ESI); +} + +static void +do_x86emu(void) +{ + X86EMU_exec(); +} + +static jmp_buf x86_esc; +static void +vmexit(int unused) +{ + longjmp(x86_esc,1); +} + +void +do_x86(unsigned long bios_start, i86biosRegsPtr regs) +{ + static void (*org_handler)(int); + + setup_x86emu(bios_start,regs); + if (setjmp(x86_esc) == 0) { + org_handler = signal(2,vmexit); + do_x86emu(); + signal(2,org_handler); + collect_bios_regs(regs); + } else { + signal(2,org_handler); + printf("interrupted at 0x%x\n",((CARD16)CPU_REG(CS)) << 4 + | (CARD16)CPU_REG(EIP)); + } +} + +int +run_bios_int(int num, struct regs86 *regs) +{ +#ifdef V86BIOS_DEBUG + static int firsttime = 1; +#endif + /* check if bios vector is initialized */ + if (((CARD16*)0)[(num<<1)+1] == 0x0000) { /* SYS_BIOS_SEG ?*/ +#ifdef V86BIOS_DEBUG + i_printf("card BIOS not loaded\n"); +#endif + return 0; + } + +#ifdef V86BIOS_DEBUG + if (firsttime) { + dprint(0,0x3D0); + firsttime = 0; + } +#endif + + i_printf("calling card BIOS at: "); + i_printf("0x%x:%x\n",((CARD16 *) 0)[(num << 1) + 1], + (CARD32)((CARD16 *) 0)[num << 1]); + X86EMU_prepareForInt(num); + + return 1; +} + +CARD32 +getIntVect(int num) +{ + return ((CARD32*)0)[num]; +} +#if 0 +void +printk(const char *fmt, ...) +{ + va_list argptr; + va_start(argptr, fmt); + vfprintf(stdout, fmt, argptr); + fflush(stdout); + va_end(argptr); +} +#endif + +CARD32 +getIP(void) +{ + return (M.x86.saved_cs << 4) + M.x86.saved_ip; +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE b/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE new file mode 100644 index 000000000..a3ede4a87 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/LICENSE @@ -0,0 +1,17 @@ + License information + ------------------- + +The x86emu library is under a BSD style license, comaptible +with the XFree86 and X licenses used by XFree86. The +original x86emu libraries were under the GNU General Public +License. Due to license incompatibilities between the GPL +and the XFree86 license, the original authors of the code +decided to allow a license change. If you have submitted +code to the original x86emu project, and you don't agree +with the license change, please contact us and let you +know. Your code will be removed to comply with your wishes. + +If you have any questions about this, please send email to +x86emu@linuxlabs.com or KendallB@scitechsoft.com for +clarification. + diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/debug.c b/board/MAI/bios_emulator/scitech/src/x86emu/debug.c new file mode 100644 index 000000000..235e6ac14 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/debug.c @@ -0,0 +1,443 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to handle debugging of the +* emulator. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" +#include +#include + +/*----------------------------- Implementation ----------------------------*/ + +#ifdef DEBUG + +static void print_encoded_bytes (u16 s, u16 o); +static void print_decoded_instruction (void); +static int parse_line (char *s, int *ps, int *n); + +/* should look something like debug's output. */ +void X86EMU_trace_regs (void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_regs(); + } + if (DEBUG_DECODE() && ! DEBUG_DECODE_NOPRINT()) { + printk("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); + } +} + +void X86EMU_trace_xregs (void) +{ + if (DEBUG_TRACE()) { + x86emu_dump_xregs(); + } +} + +void x86emu_just_disassemble (void) +{ + /* + * This routine called if the flag DEBUG_DISASSEMBLE is set kind + * of a hack! + */ + printk("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); +} + +static void disassemble_forward (u16 seg, u16 off, int n) +{ + X86EMU_sysEnv tregs; + int i; + u8 op1; + /* + * hack, hack, hack. What we do is use the exact machinery set up + * for execution, except that now there is an additional state + * flag associated with the "execution", and we are using a copy + * of the register struct. All the major opcodes, once fully + * decoded, have the following two steps: TRACE_REGS(r,m); + * SINGLE_STEP(r,m); which disappear if DEBUG is not defined to + * the preprocessor. The TRACE_REGS macro expands to: + * + * if (debug&DEBUG_DISASSEMBLE) + * {just_disassemble(); goto EndOfInstruction;} + * if (debug&DEBUG_TRACE) trace_regs(r,m); + * + * ...... and at the last line of the routine. + * + * EndOfInstruction: end_instr(); + * + * Up to the point where TRACE_REG is expanded, NO modifications + * are done to any register EXCEPT the IP register, for fetch and + * decoding purposes. + * + * This was done for an entirely different reason, but makes a + * nice way to get the system to help debug codes. + */ + tregs = M; + tregs.x86.R_IP = off; + tregs.x86.R_CS = seg; + + /* reset the decoding buffers */ + tregs.x86.enc_str_pos = 0; + tregs.x86.enc_pos = 0; + + /* turn on the "disassemble only, no execute" flag */ + tregs.x86.debug |= DEBUG_DISASSEMBLE_F; + + /* DUMP NEXT n instructions to screen in straight_line fashion */ + /* + * This looks like the regular instruction fetch stream, except + * that when this occurs, each fetched opcode, upon seeing the + * DEBUG_DISASSEMBLE flag set, exits immediately after decoding + * the instruction. XXX --- CHECK THAT MEM IS NOT AFFECTED!!! + * Note the use of a copy of the register structure... + */ + for (i=0; i 256) return; + seg = fetch_data_word_abs(0,iv*4); + off = fetch_data_word_abs(0,iv*4+2); + printk("%04x:%04x ", seg, off); +} + +void X86EMU_dump_memory (u16 seg, u16 off, u32 amt) +{ + u32 start = off & 0xfffffff0; + u32 end = (off+16) & 0xfffffff0; + u32 i; + u32 current; + + current = start; + while (end <= off + amt) { + printk("%04x:%04x ", seg, start); + for (i=start; i< off; i++) + printk(" "); + for ( ; i< end; i++) + printk("%02x ", fetch_data_byte_abs(seg,i)); + printk("\n"); + start = end; + end = start + 16; + } +} + +void x86emu_single_step (void) +{ + char s[1024]; + int ps[10]; + int ntok; + int cmd; + int done; + int segment; + int offset; + static int breakpoint; + static int noDecode = 1; + + char *p; + + if (DEBUG_BREAK()) { + if (M.x86.saved_ip != breakpoint) { + return; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + M.x86.debug |= DEBUG_TRACE_F; + M.x86.debug &= ~DEBUG_BREAK_F; + print_decoded_instruction (); + X86EMU_trace_regs(); + } + } + + done=0; + offset = M.x86.saved_ip; + while (!done) { + printk("-"); + /*p = fgets(s, 1023, stdin); */ + cons_gets(s); + cmd = parse_line(s, ps, &ntok); + switch(cmd) { + case 'u': + disassemble_forward(M.x86.saved_cs,(u16)offset,10); + break; + case 'd': + if (ntok == 2) { + segment = M.x86.saved_cs; + offset = ps[1]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else if (ntok == 3) { + segment = ps[1]; + offset = ps[2]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else { + segment = M.x86.saved_cs; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } + break; + case 'c': + M.x86.debug ^= DEBUG_TRACECALL_F; + break; + case 's': + M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; + break; + case 'r': + X86EMU_trace_regs(); + break; + case 'x': + X86EMU_trace_xregs(); + break; + case 'g': + if (ntok == 2) { + breakpoint = ps[1]; + printk("breakpoint set to 0x%X\n", breakpoint); + if (noDecode) { + M.x86.debug |= DEBUG_DECODE_NOPRINT_F; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + } + M.x86.debug &= ~DEBUG_TRACE_F; + M.x86.debug |= DEBUG_BREAK_F; + done = 1; + } + break; + case 'q': + M.x86.debug |= DEBUG_EXIT; + return; + case 'P': + noDecode = (noDecode)?0:1; + printk("Toggled decoding to %s\n",(noDecode)?"FALSE":"TRUE"); + break; + case 't': + case 0: + done = 1; + break; + } + } +} + +int X86EMU_trace_on(void) +{ + return M.x86.debug |= DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F; +} + +int X86EMU_trace_off(void) +{ + return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F); +} + +static int parse_line (char *s, int *ps, int *n) +{ + int cmd; + + *n = 0; + while(*s == ' ' || *s == '\t') s++; + ps[*n] = *s; + switch (*s) { + case '\n': + *n += 1; + return 0; + default: + cmd = *s; + *n += 1; + } + + while (1) { + while (*s != ' ' && *s != '\t' && *s != '\n') s++; + + if (*s == '\n') + return cmd; + + while(*s == ' ' || *s == '\t') s++; + + ps[*n]=atoi(s); + /*sscanf(s,"%x",&ps[*n]); */ + *n += 1; + } +} + +#endif /* DEBUG */ + +void x86emu_dump_stack(void) +{ + int i; + printk("Stack: "); + for (i = 0; i<16; i++) + { + u8 x = fetch_data_byte_abs(M.x86.R_SS, M.x86.R_SP + i); + printk("%02x ", (int)x); + } + printk("\n"); +} + +void x86emu_dump_regs (void) +{ + printk("\tAX=%04x ", M.x86.R_AX ); + printk("BX=%04x ", M.x86.R_BX ); + printk("CX=%04x ", M.x86.R_CX ); + printk("DX=%04x ", M.x86.R_DX ); + printk("SP=%04x ", M.x86.R_SP ); + printk("BP=%04x ", M.x86.R_BP ); + printk("SI=%04x ", M.x86.R_SI ); + printk("DI=%04x\n", M.x86.R_DI ); + printk("\tDS=%04x ", M.x86.R_DS ); + printk("ES=%04x ", M.x86.R_ES ); + printk("SS=%04x ", M.x86.R_SS ); + printk("CS=%04x ", M.x86.R_CS ); + printk("IP=%04x ", M.x86.R_IP ); + if (ACCESS_FLAG(F_OF)) printk("OV "); /* CHECKED... */ + else printk("NV "); + if (ACCESS_FLAG(F_DF)) printk("DN "); + else printk("UP "); + if (ACCESS_FLAG(F_IF)) printk("EI "); + else printk("DI "); + if (ACCESS_FLAG(F_SF)) printk("NG "); + else printk("PL "); + if (ACCESS_FLAG(F_ZF)) printk("ZR "); + else printk("NZ "); + if (ACCESS_FLAG(F_AF)) printk("AC "); + else printk("NA "); + if (ACCESS_FLAG(F_PF)) printk("PE "); + else printk("PO "); + if (ACCESS_FLAG(F_CF)) printk("CY "); + else printk("NC "); + printk("\n"); + /*x86emu_dump_stack(); */ +} + +void x86emu_dump_xregs (void) +{ + printk("\tEAX=%08x ", M.x86.R_EAX ); + printk("EBX=%08x ", M.x86.R_EBX ); + printk("ECX=%08x ", M.x86.R_ECX ); + printk("EDX=%08x \n", M.x86.R_EDX ); + printk("\tESP=%08x ", M.x86.R_ESP ); + printk("EBP=%08x ", M.x86.R_EBP ); + printk("ESI=%08x ", M.x86.R_ESI ); + printk("EDI=%08x\n", M.x86.R_EDI ); + printk("\tDS=%04x ", M.x86.R_DS ); + printk("ES=%04x ", M.x86.R_ES ); + printk("SS=%04x ", M.x86.R_SS ); + printk("CS=%04x ", M.x86.R_CS ); + printk("EIP=%08x\n\t", M.x86.R_EIP ); + if (ACCESS_FLAG(F_OF)) printk("OV "); /* CHECKED... */ + else printk("NV "); + if (ACCESS_FLAG(F_DF)) printk("DN "); + else printk("UP "); + if (ACCESS_FLAG(F_IF)) printk("EI "); + else printk("DI "); + if (ACCESS_FLAG(F_SF)) printk("NG "); + else printk("PL "); + if (ACCESS_FLAG(F_ZF)) printk("ZR "); + else printk("NZ "); + if (ACCESS_FLAG(F_AF)) printk("AC "); + else printk("NA "); + if (ACCESS_FLAG(F_PF)) printk("PE "); + else printk("PO "); + if (ACCESS_FLAG(F_CF)) printk("CY "); + else printk("NC "); + printk("\n"); +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/decode.c b/board/MAI/bios_emulator/scitech/src/x86emu/decode.c new file mode 100644 index 000000000..832b1f5f2 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/decode.c @@ -0,0 +1,970 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* instruction decoding and accessess of immediate data via IP. etc. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +REMARKS: +Handles any pending asychronous interrupts. +****************************************************************************/ +static void x86emu_intr_handle(void) +{ + u8 intno; + + if (M.x86.intr & INTR_SYNCH) { + intno = M.x86.intno; + if (_X86EMU_intrTab[intno]) { + (*_X86EMU_intrTab[intno])(intno); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intno * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intno * 4); + M.x86.intr = 0; + } + } +} + +/**************************************************************************** +PARAMETERS: +intrnum - Interrupt number to raise + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. +****************************************************************************/ +void x86emu_intr_raise( + u8 intrnum) +{ + M.x86.intno = intrnum; + M.x86.intr |= INTR_SYNCH; +} + +/**************************************************************************** +REMARKS: +Main execution loop for the emulator. We return from here when the system +halts, which is normally caused by a stack fault when we return from the +original real mode call. +****************************************************************************/ +void X86EMU_exec(void) +{ + u8 op1; + + M.x86.intr = 0; + DB(x86emu_end_instr();) + + for (;;) { + DB(if (CHECK_IP_FETCH()) x86emu_check_ip_access();) + /* If debugging, save the IP and CS values. */ + SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); + INC_DECODED_INST_LEN(1); + if (M.x86.intr) { + if (M.x86.intr & INTR_HALTED) { + DB( printk("halted\n"); X86EMU_trace_regs();) + return; + } + if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(); + } + } + op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + (*x86emu_optab[op1])(op1); + if (M.x86.debug & DEBUG_EXIT) { + M.x86.debug &= ~DEBUG_EXIT; + return; + } + } +} + +/**************************************************************************** +REMARKS: +Halts the system by setting the halted system flag. +****************************************************************************/ +void X86EMU_halt_sys(void) +{ + M.x86.intr |= INTR_HALTED; +} + +/**************************************************************************** +PARAMETERS: +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte + +REMARKS: +Raise the specified interrupt to be handled before the execution of the +next instruction. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +void fetch_decode_modrm( + int *mod, + int *regh, + int *regl) +{ + int fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + *mod = (fetched >> 6) & 0x03; + *regh = (fetched >> 3) & 0x07; + *regl = (fetched >> 0) & 0x07; +} + +/**************************************************************************** +RETURNS: +Immediate byte value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdb) is already inline! +****************************************************************************/ +u8 fetch_byte_imm(void) +{ + u8 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate word value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u16 fetch_word_imm(void) +{ + u16 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 2; + INC_DECODED_INST_LEN(2); + return fetched; +} + +/**************************************************************************** +RETURNS: +Immediate lone value read from instruction queue + +REMARKS: +This function returns the immediate byte from the instruction queue, and +moves the instruction pointer to the next value. + +NOTE: Do not inline this function, as (*sys_rdw) is already inline! +****************************************************************************/ +u32 fetch_long_imm(void) +{ + u32 fetched; + +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); + M.x86.R_IP += 4; + INC_DECODED_INST_LEN(4); + return fetched; +} + +/**************************************************************************** +RETURNS: +Value of the default data segment + +REMARKS: +Inline function that returns the default data segment for the current +instruction. + +On the x86 processor, the default segment is not always DS if there is +no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to +addresses relative to SS (ie: on the stack). So, at the minimum, all +decodings of addressing modes would have to set/clear a bit describing +whether the access is relative to DS or SS. That is the function of the +cpu-state-varible M.x86.mode. There are several potential states: + + repe prefix seen (handled elsewhere) + repne prefix seen (ditto) + + cs segment override + ds segment override + es segment override + fs segment override + gs segment override + ss segment override + + ds/ss select (in absense of override) + +Each of the above 7 items are handled with a bit in the mode field. +****************************************************************************/ +_INLINE u32 get_data_segment(void) +{ +#define GET_SEGMENT(segment) + switch (M.x86.mode & SYSMODE_SEGMASK) { + case 0: /* default case: use ds register */ + case SYSMODE_SEGOVR_DS: + case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: + return M.x86.R_DS; + case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ + return M.x86.R_SS; + case SYSMODE_SEGOVR_CS: + case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: + return M.x86.R_CS; + case SYSMODE_SEGOVR_ES: + case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: + return M.x86.R_ES; + case SYSMODE_SEGOVR_FS: + case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: + return M.x86.R_FS; + case SYSMODE_SEGOVR_GS: + case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: + return M.x86.R_GS; + case SYSMODE_SEGOVR_SS: + case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: + return M.x86.R_SS; + default: +#ifdef DEBUG + printk("error: should not happen: multiple overrides.\n"); +#endif + HALT_SYS(); + return 0; + } +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte( + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdb)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word( + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdw)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long( + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + return (*sys_rdl)((get_data_segment() << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Byte value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u8 fetch_data_byte_abs( + uint segment, + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdb)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Word value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u16 fetch_data_word_abs( + uint segment, + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdw)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to load data from +offset - Offset to load data from + +RETURNS: +Long value read from the absolute memory location. + +NOTE: Do not inline this function as (*sys_rdX) is already inline! +****************************************************************************/ +u32 fetch_data_long_abs( + uint segment, + uint offset) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + return (*sys_rdl)(((u32)segment << 4) + offset); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte( + uint offset, + u8 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrb)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word( + uint offset, + u16 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrw)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an segmented memory location. The segment used is +the current 'default' segment, which may have been overridden. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long( + uint offset, + u32 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access((u16)get_data_segment(), offset); +#endif + (*sys_wrl)((get_data_segment() << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a byte value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_byte_abs( + uint segment, + uint offset, + u8 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrb)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a word value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_word_abs( + uint segment, + uint offset, + u16 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrw)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +segment - Segment to store data at +offset - Offset to store data at +val - Value to store + +REMARKS: +Writes a long value to an absolute memory location. + +NOTE: Do not inline this function as (*sys_wrX) is already inline! +****************************************************************************/ +void store_data_long_abs( + uint segment, + uint offset, + u32 val) +{ +#ifdef DEBUG + if (CHECK_DATA_ACCESS()) + x86emu_check_data_access(segment, offset); +#endif + (*sys_wrl)(((u32)segment << 4) + offset, val); +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for byte operands. Also enables the decoding of instructions. +****************************************************************************/ +u8* decode_rm_byte_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AL"); + return &M.x86.R_AL; + case 1: + DECODE_PRINTF("CL"); + return &M.x86.R_CL; + case 2: + DECODE_PRINTF("DL"); + return &M.x86.R_DL; + case 3: + DECODE_PRINTF("BL"); + return &M.x86.R_BL; + case 4: + DECODE_PRINTF("AH"); + return &M.x86.R_AH; + case 5: + DECODE_PRINTF("CH"); + return &M.x86.R_CH; + case 6: + DECODE_PRINTF("DH"); + return &M.x86.R_DH; + case 7: + DECODE_PRINTF("BH"); + return &M.x86.R_BH; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_word_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("AX"); + return &M.x86.R_AX; + case 1: + DECODE_PRINTF("CX"); + return &M.x86.R_CX; + case 2: + DECODE_PRINTF("DX"); + return &M.x86.R_DX; + case 3: + DECODE_PRINTF("BX"); + return &M.x86.R_BX; + case 4: + DECODE_PRINTF("SP"); + return &M.x86.R_SP; + case 5: + DECODE_PRINTF("BP"); + return &M.x86.R_BP; + case 6: + DECODE_PRINTF("SI"); + return &M.x86.R_SI; + case 7: + DECODE_PRINTF("DI"); + return &M.x86.R_DI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for dword operands. Also enables the decoding of instructions. +****************************************************************************/ +u32* decode_rm_long_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("EAX"); + return &M.x86.R_EAX; + case 1: + DECODE_PRINTF("ECX"); + return &M.x86.R_ECX; + case 2: + DECODE_PRINTF("EDX"); + return &M.x86.R_EDX; + case 3: + DECODE_PRINTF("EBX"); + return &M.x86.R_EBX; + case 4: + DECODE_PRINTF("ESP"); + return &M.x86.R_ESP; + case 5: + DECODE_PRINTF("EBP"); + return &M.x86.R_EBP; + case 6: + DECODE_PRINTF("ESI"); + return &M.x86.R_ESI; + case 7: + DECODE_PRINTF("EDI"); + return &M.x86.R_EDI; + } + HALT_SYS(); + return NULL; /* NOTREACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +reg - Register to decode + +RETURNS: +Pointer to the appropriate register + +REMARKS: +Return a pointer to the register given by the R/RM field of the +modrm byte, for word operands, modified from above for the weirdo +special case of segreg operands. Also enables the decoding of instructions. +****************************************************************************/ +u16* decode_rm_seg_register( + int reg) +{ + switch (reg) { + case 0: + DECODE_PRINTF("ES"); + return &M.x86.R_ES; + case 1: + DECODE_PRINTF("CS"); + return &M.x86.R_CS; + case 2: + DECODE_PRINTF("SS"); + return &M.x86.R_SS; + case 3: + DECODE_PRINTF("DS"); + return &M.x86.R_DS; + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF("ILLEGAL SEGREG"); + break; + } + HALT_SYS(); + return NULL; /* NOT REACHED OR REACHED ON ERROR */ +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=00 addressing. Also enables the +decoding of instructions. + +NOTE: The code which specifies the corresponding segment (ds vs ss) + below in the case of [BP+..]. The assumption here is that at the + point that this subroutine is called, the bit corresponding to + SYSMODE_SEG_DS_SS will be zero. After every instruction + except the segment override instructions, this bit (as well + as any bits indicating segment overrides) will be clear. So + if a SS access is needed, set this bit. Otherwise, DS access + occurs (unless any of the segment override bits are set). +****************************************************************************/ +unsigned decode_rm00_address( + int rm) +{ + unsigned offset; + + if (M.x86.mode & SYSMODE_PREFIX_ADDR) + { + switch (rm) { + case 0: + DECODE_PRINTF("[EAX]"); + return M.x86.R_EAX; + case 1: + DECODE_PRINTF("[ECX]"); + return M.x86.R_ECX; + case 2: + DECODE_PRINTF("[EDX]"); +/* M.x86.mode |= SYSMODE_SEG_DS_SS; */ + return M.x86.R_EDX; + case 3: + DECODE_PRINTF("[EBX]"); +/* M.x86.mode |= SYSMODE_SEG_DS_SS; */ + return M.x86.R_EBX; + case 4: + printk("Unsupported SIB encoding\n"); + HALT_SYS(); + return 0; + case 5: + offset = fetch_long_imm(); + DECODE_PRINTF2("[%08x]", offset); + return offset; + case 6: + DECODE_PRINTF("[ESI]"); + return M.x86.R_ESI; + case 7: + DECODE_PRINTF("[EDI]"); + return M.x86.R_EDI; + } + } + else + { + switch (rm) { + case 0: + DECODE_PRINTF("[BX+SI]"); + return M.x86.R_BX + M.x86.R_SI; + case 1: + DECODE_PRINTF("[BX+DI]"); + return M.x86.R_BX + M.x86.R_DI; + case 2: + DECODE_PRINTF("[BP+SI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_BP + M.x86.R_SI; + case 3: + DECODE_PRINTF("[BP+DI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_BP + M.x86.R_DI; + case 4: + DECODE_PRINTF("[SI]"); + return M.x86.R_SI; + case 5: + DECODE_PRINTF("[DI]"); + return M.x86.R_DI; + case 6: + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]", offset); + return offset; + case 7: + DECODE_PRINTF("[BX]"); + return M.x86.R_BX; + } + } + HALT_SYS(); + return 0; +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=01 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +unsigned decode_rm01_address( + int rm) +{ + int displacement = (s8)fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_ADDR) + { + switch (rm) + { + case 0: + DECODE_PRINTF2("%d[EAX}", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: + printk("Unsupported SIB addressing mode\n"); + HALT_SYS(); + return 0; + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + } + else + { + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return M.x86.R_BX + M.x86.R_SI + displacement; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return M.x86.R_BX + M.x86.R_DI + displacement; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_BP + M.x86.R_SI + displacement; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_BP + M.x86.R_DI + displacement; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return M.x86.R_SI + displacement; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return M.x86.R_DI + displacement; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return M.x86.R_BP + displacement; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return M.x86.R_BX + displacement; + } + HALT_SYS(); + } + return 0; /* SHOULD NOT HAPPEN */ +} + +/**************************************************************************** +PARAMETERS: +rm - RM value to decode + +RETURNS: +Offset in memory for the address decoding + +REMARKS: +Return the offset given by mod=10 addressing. Also enables the +decoding of instructions. +****************************************************************************/ +unsigned decode_rm10_address( + int rm) +{ + if (M.x86.mode & SYSMODE_PREFIX_ADDR) + { + int displacement = (s32)fetch_long_imm(); + switch (rm) + { + case 0: + DECODE_PRINTF2("%d[EAX}", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: + printk("Unsupported SIB addressing mode\n"); + HALT_SYS(); + return 0; + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } + } + else + { + int displacement = (s16)fetch_word_imm(); + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } + } + HALT_SYS(); + return 0; + /*NOTREACHED */ +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c b/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c new file mode 100644 index 000000000..7f7c345b3 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/fpu.c @@ -0,0 +1,945 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the decoding and +* emulation of the FPU instructions. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/* opcode=0xd8 */ +void x86emuOp_esc_coprocess_d8(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ESC D8\n"); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +static char *x86emu_fpu_op_d9_tab[] = { + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", + + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", + + "FLD\tDWORD PTR ", "ESC_D9\t", "FST\tDWORD PTR ", "FSTP\tDWORD PTR ", + "FLDENV\t", "FLDCW\t", "FSTENV\t", "FSTCW\t", +}; + +static char *x86emu_fpu_op_d9_tab1[] = { + "FLD\t", "FLD\t", "FLD\t", "FLD\t", + "FLD\t", "FLD\t", "FLD\t", "FLD\t", + + "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", + "FXCH\t", "FXCH\t", "FXCH\t", "FXCH\t", + + "FNOP", "ESC_D9", "ESC_D9", "ESC_D9", + "ESC_D9", "ESC_D9", "ESC_D9", "ESC_D9", + + "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", + "FSTP\t", "FSTP\t", "FSTP\t", "FSTP\t", + + "FCHS", "FABS", "ESC_D9", "ESC_D9", + "FTST", "FXAM", "ESC_D9", "ESC_D9", + + "FLD1", "FLDL2T", "FLDL2E", "FLDPI", + "FLDLG2", "FLDLN2", "FLDZ", "ESC_D9", + + "F2XM1", "FYL2X", "FPTAN", "FPATAN", + "FXTRACT", "ESC_D9", "FDECSTP", "FINCSTP", + + "FPREM", "FYL2XP1", "FSQRT", "ESC_D9", + "FRNDINT", "FSCALE", "ESC_D9", "ESC_D9", +}; + +#endif /* DEBUG */ + +/* opcode=0xd9 */ +void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (mod != 3) { + DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); + } else { + DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); + } +#endif + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + if (rh < 4) { + DECODE_PRINTF2("ST(%d)\n", stkelem); + } else { + DECODE_PRINTF("\n"); + } + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); + break; + case 1: + x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); + break; + case 2: + switch (rl) { + case 0: + x86emu_fpu_R_nop(); + break; + default: + x86emu_fpu_illegal(); + break; + } + case 3: + x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); + break; + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); + break; + default: + /* 2,3,6,7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 5: + switch (rl) { + case 0: + x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); + break; + default: + /* 7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 6: + switch (rl) { + case 0: + x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_R_decstp(); + break; + case 7: + x86emu_fpu_R_incstp(); + break; + } + break; + + case 7: + switch (rl) { + case 0: + x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); + break; + case 6: + case 7: + default: + x86emu_fpu_illegal(); + break; + } + break; + + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); + break; + case 4: + x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); + break; + } + } + } +#endif /* X86EMU_FPU_PRESENT */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +char *x86emu_fpu_op_da_tab[] = { + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "FIADD\tDWORD PTR ", "FIMUL\tDWORD PTR ", "FICOM\tDWORD PTR ", + "FICOMP\tDWORD PTR ", + "FISUB\tDWORD PTR ", "FISUBR\tDWORD PTR ", "FIDIV\tDWORD PTR ", + "FIDIVR\tDWORD PTR ", + + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", +}; + +#endif /* DEBUG */ + +/* opcode=0xda */ +void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_da_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + x86emu_fpu_illegal(); + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); + break; + case 2: + x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); + break; + case 5: + x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); + break; + case 6: + x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); + break; + case 7: + x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +char *x86emu_fpu_op_db_tab[] = { + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", + + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", + + "FILD\tDWORD PTR ", "ESC_DB\t19", "FIST\tDWORD PTR ", "FISTP\tDWORD PTR ", + "ESC_DB\t1C", "FLD\tTBYTE PTR ", "ESC_DB\t1E", "FSTP\tTBYTE PTR ", +}; + +#endif /* DEBUG */ + +/* opcode=0xdb */ +void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (mod != 3) { + DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); + } else if (rh == 4) { /* === 11 10 0 nnn */ + switch (rl) { + case 0: + DECODE_PRINTF("FENI\n"); + break; + case 1: + DECODE_PRINTF("FDISI\n"); + break; + case 2: + DECODE_PRINTF("FCLEX\n"); + break; + case 3: + DECODE_PRINTF("FINIT\n"); + break; + } + } else { + DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); + } +#endif /* DEBUG */ + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + break; + case 1: + destoffset = decode_rm01_address(rl); + break; + case 2: + destoffset = decode_rm10_address(rl); + break; + case 3: /* register to register */ + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_feni(); + break; + case 1: + x86emu_fpu_R_fdisi(); + break; + case 2: + x86emu_fpu_R_fclex(); + break; + case 3: + x86emu_fpu_R_finit(); + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_illegal(); + break; + case 5: + x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); + break; + case 6: + x86emu_fpu_illegal(); + break; + case 7: + x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG +char *x86emu_fpu_op_dc_tab[] = { + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\tQWORD PTR ", "FMUL\tQWORD PTR ", "FCOM\tQWORD PTR ", + "FCOMP\tQWORD PTR ", + "FSUB\tQWORD PTR ", "FSUBR\tQWORD PTR ", "FDIV\tQWORD PTR ", + "FDIVR\tQWORD PTR ", + + "FADD\t", "FMUL\t", "FCOM\t", "FCOMP\t", + "FSUBR\t", "FSUB\t", "FDIVR\t", "FDIV\t", +}; +#endif /* DEBUG */ + +/* opcode=0xdc */ +void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_dc_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + /* execute */ + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); + break; + case 2: + x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); + break; + case 5: + x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); + break; + case 6: + x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); + break; + case 7: + x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +static char *x86emu_fpu_op_dd_tab[] = { + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FLD\tQWORD PTR ", "ESC_DD\t29,", "FST\tQWORD PTR ", "FSTP\tQWORD PTR ", + "FRSTOR\t", "ESC_DD\t2D,", "FSAVE\t", "FSTSW\t", + + "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", + "ESC_DD\t2C,", "ESC_DD\t2D,", "ESC_DD\t2E,", "ESC_DD\t2F,", +}; + +#endif /* DEBUG */ + +/* opcode=0xdd */ +void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_dd_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +static char *x86emu_fpu_op_de_tab[] = +{ + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FIADD\tWORD PTR ", "FIMUL\tWORD PTR ", "FICOM\tWORD PTR ", + "FICOMP\tWORD PTR ", + "FISUB\tWORD PTR ", "FISUBR\tWORD PTR ", "FIDIV\tWORD PTR ", + "FIDIVR\tWORD PTR ", + + "FADDP\t", "FMULP\t", "FCOMP\t", "FCOMPP\t", + "FSUBRP\t", "FSUBP\t", "FDIVRP\t", "FDIVP\t", +}; + +#endif /* DEBUG */ + +/* opcode=0xde */ +void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_de_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + if (stkelem == 1) + x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); + else + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); + break; + case 2: + x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} + +#ifdef DEBUG + +static char *x86emu_fpu_op_df_tab[] = { + /* mod == 00 */ + "FILD\tWORD PTR ", "ESC_DF\t39\n", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 01 */ + "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 10 */ + "FILD\tWORD PTR ", "ESC_DF\t39 ", "FIST\tWORD PTR ", "FISTP\tWORD PTR ", + "FBLD\tTBYTE PTR ", "FILD\tQWORD PTR ", "FBSTP\tTBYTE PTR ", + "FISTP\tQWORD PTR ", + + /* mod == 11 */ + "FFREE\t", "FXCH\t", "FST\t", "FSTP\t", + "ESC_DF\t3C,", "ESC_DF\t3D,", "ESC_DF\t3E,", "ESC_DF\t3F," +}; + +#endif /* DEBUG */ + +/* opcode=0xdf */ +void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 stkelem; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_df_tab, mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d)\n", stkelem); + break; + } +#ifdef X86EMU_FPU_PRESENT + switch (mod) { + case 3: + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); + break; + case 5: + x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); + break; + case 6: + x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); + break; + case 7: + x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); + break; + } + } +#endif + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR_NO_TRACE(); +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile b/board/MAI/bios_emulator/scitech/src/x86emu/makefile new file mode 100644 index 000000000..8ce2e9e84 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile @@ -0,0 +1,63 @@ +############################################################################# +# +# Realmode X86 Emulator Library +# +# Copyright (C) 1996-1999 SciTech Software, Inc. +# +# ======================================================================== +# +# Permission to use, copy, modify, distribute, and sell this software and +# its documentation for any purpose is hereby granted without fee, +# provided that the above copyright notice appear in all copies and that +# both that copyright notice and this permission notice appear in +# supporting documentation, and that the name of the authors not be used +# in advertising or publicity pertaining to distribution of the software +# without specific, written prior permission. The authors makes no +# representations about the suitability of this software for any purpose. +# It is provided "as is" without express or implied warranty. +# +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# ======================================================================== +# +# Descripton: Generic makefile for the x86emu library. Requires +# the SciTech Software makefile definitions package to be +# installed, which uses the DMAKE make program. +# +############################################################################# + +.IMPORT .IGNORE: DEBUG + +#---------------------------------------------------------------------------- +# Define the lists of object files +#---------------------------------------------------------------------------- + +OBJECTS = sys$O decode$O ops$O ops2$O prim_ops$O fpu$O debug$O +CFLAGS += -DSCITECH +.IF $(DEBUG) +CFLAGS += -DDEBUG +.ENDIF +LIBCLEAN = *.dll *.lib *.a +LIBFILE = $(LP)x86emu$L + +#---------------------------------------------------------------------------- +# Sample test programs +#---------------------------------------------------------------------------- + +all: $(LIBFILE) + +validate$E: validate$O $(LIBFILE) + +#---------------------------------------------------------------------------- +# Define the list of object files to create dependency information for +#---------------------------------------------------------------------------- + +DEPEND_OBJ = validate$O $(OBJECTS) + +.INCLUDE: "$(SCITECH)/makedefs/common.mk" diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross new file mode 100644 index 000000000..0bce9a96e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.cross @@ -0,0 +1,82 @@ +############################################################################# +# +# Realmode X86 Emulator Library +# +# Copyright (C) 1996-1999 SciTech Software, Inc. +# +# ======================================================================== +# +# Permission to use, copy, modify, distribute, and sell this software and +# its documentation for any purpose is hereby granted without fee, +# provided that the above copyright notice appear in all copies and that +# both that copyright notice and this permission notice appear in +# supporting documentation, and that the name of the authors not be used +# in advertising or publicity pertaining to distribution of the software +# without specific, written prior permission. The authors makes no +# representations about the suitability of this software for any purpose. +# It is provided "as is" without express or implied warranty. +# +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# ======================================================================== +# +# Descripton: Linux specific makefile for the x86emu library. +# +############################################################################# + +CC = $(CROSS_COMPILE)gcc +AR = $(CROSS_COMPILE)ar + +TARGETLIB = libx86emu.a +TARGETDEBUGLIB =libx86emud.a + +OBJS=\ +decode.o \ +fpu.o \ +ops.o \ +ops2.o \ +prim_ops.o \ +sys.o + +DEBUGOBJS=debug.d \ + decode.d \ + fpu.d \ + ops.d \ + ops2.d \ + prim_ops.d \ + sys.d + +.SUFFIXES: .d + +all: $(TARGETLIB) $(TARGETDEBUGLIB) + +$(TARGETLIB): $(OBJS) + $(AR) rv $(TARGETLIB) $(OBJS) + +$(TARGETDEBUGLIB): $(DEBUGOBJS) + $(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS) + +INCS = -I. -Ix86emu -I../../include +CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char -fomit-frame-pointer -fPIC -ffixed-r14 -meabi +CDEBUGFLAGS = -DDEBUG + +.c.o: + $(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c + +.c.d: + $(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c + +.cpp.o: + $(CC) -c $(CFLAGS) $(INCS) $*.cpp + +clean: + rm -f *.a *.o *.d + +validate: validate.o libx86emu.a + $(CC) -o validate validate.o -lx86emu -L. diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux new file mode 100644 index 000000000..f74b88d4c --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.linux @@ -0,0 +1,81 @@ +############################################################################# +# +# Realmode X86 Emulator Library +# +# Copyright (C) 1996-1999 SciTech Software, Inc. +# +# ======================================================================== +# +# Permission to use, copy, modify, distribute, and sell this software and +# its documentation for any purpose is hereby granted without fee, +# provided that the above copyright notice appear in all copies and that +# both that copyright notice and this permission notice appear in +# supporting documentation, and that the name of the authors not be used +# in advertising or publicity pertaining to distribution of the software +# without specific, written prior permission. The authors makes no +# representations about the suitability of this software for any purpose. +# It is provided "as is" without express or implied warranty. +# +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# ======================================================================== +# +# Descripton: Linux specific makefile for the x86emu library. +# +############################################################################# + +TARGETLIB = libx86emu.a +TARGETDEBUGLIB =libx86emud.a + +OBJS=\ +decode.o \ +fpu.o \ +ops.o \ +ops2.o \ +prim_ops.o \ +pregs.o \ +sys.o + +DEBUGOBJS=debug.d \ + decode.d \ + fpu.d \ + ops.d \ + ops2.d \ + prim_ops.d \ + pregs.d \ + sys.d + +.SUFFIXES: .d + +all: $(TARGETLIB) $(TARGETDEBUGLIB) + +$(TARGETLIB): $(OBJS) + ar rv $(TARGETLIB) $(OBJS) + +$(TARGETDEBUGLIB): $(DEBUGOBJS) + ar rv $(TARGETDEBUGLIB) $(DEBUGOBJS) + +INCS = -I. -Ix86emu -I../../include +CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG +CDEBUGFLAGS = -DDEBUG + +.c.o: + gcc -g -O -Wall -c $(CFLAGS) $(INCS) $*.c + +.c.d: + gcc -g -O -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c + +.cpp.o: + gcc -c $(CFLAGS) $(INCS) $*.cpp + +clean: + rm -f *.a *.o *.d + +validate: validate.o libx86emu.a + gcc -o validate validate.o -lx86emu -L. diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot new file mode 100644 index 000000000..af9ae1f58 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot @@ -0,0 +1,80 @@ +############################################################################# +# +# Realmode X86 Emulator Library +# +# Copyright (C) 1996-1999 SciTech Software, Inc. +# +# ======================================================================== +# +# Permission to use, copy, modify, distribute, and sell this software and +# its documentation for any purpose is hereby granted without fee, +# provided that the above copyright notice appear in all copies and that +# both that copyright notice and this permission notice appear in +# supporting documentation, and that the name of the authors not be used +# in advertising or publicity pertaining to distribution of the software +# without specific, written prior permission. The authors makes no +# representations about the suitability of this software for any purpose. +# It is provided "as is" without express or implied warranty. +# +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# ======================================================================== +# +# Descripton: Linux specific makefile for the x86emu library. +# +############################################################################# +CC = $(CROSS_COMPILE)gcc +AR = $(CROSS_COMPILE)ar +TARGETLIB = libx86emu.a +TARGETDEBUGLIB =libx86emud.a + +OBJS=\ +decode.o \ +fpu.o \ +ops.o \ +ops2.o \ +prim_ops.o \ +sys.o + +DEBUGOBJS=debug.d \ + decode.d \ + fpu.d \ + ops.d \ + ops2.d \ + prim_ops.d \ + sys.d + +.SUFFIXES: .d + +all: $(TARGETLIB) $(TARGETDEBUGLIB) + +$(TARGETLIB): $(OBJS) + $(AR) rv $(TARGETLIB) $(OBJS) + +$(TARGETDEBUGLIB): $(DEBUGOBJS) + $(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS) + +INCS = -I. -Ix86emu -I../../include +CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char -fomit-frame-pointer -fPIC -ffixed-r14 -meabi +CDEBUGFLAGS = -DDEBUG + +.c.o: + $(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c + +.c.d: + $(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c + +.cpp.o: + $(CC) -c $(CFLAGS) $(INCS) $*.cpp + +clean: + rm -f *.a *.o *.d + +validate: validate.o libx86emu.a + $(CC) -o validate validate.o -lx86emu -L. diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/ops.c b/board/MAI/bios_emulator/scitech/src/x86emu/ops.c new file mode 100644 index 000000000..2d4f93eee --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/ops.c @@ -0,0 +1,11701 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 processor instructions. +* +* There are approximately 250 subroutines in here, which correspond +* to the 256 byte-"opcodes" found on the 8086. The table which +* dispatches this is found in the files optab.[ch]. +* +* Each opcode proc has a comment preceeding it which gives it's table +* address. Several opcodes are missing (undefined) in the table. +* +* Each proc includes information for decoding (DECODE_PRINTF and +* DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc +* functions (START_OF_INSTR, END_OF_INSTR). +* +* Many of the procedures are *VERY* similar in coding. This has +* allowed for a very large amount of code to be generated in a fairly +* short amount of time (i.e. cut, paste, and modify). The result is +* that much of the code below could have been folded into subroutines +* for a large reduction in size of this file. The downside would be +* that there would be a penalty in execution speed. The file could +* also have been *MUCH* larger by inlining certain functions which +* were called. This could have resulted even faster execution. The +* prime directive I used to decide whether to inline the code or to +* modularize it, was basically: 1) no unnecessary subroutine calls, +* 2) no routines more than about 200 lines in size, and 3) modularize +* any code that I might not get right the first time. The fetch_* +* subroutines fall into the latter category. The The decode_* fall +* into the second category. The coding of the "switch(mod){ .... }" +* in many of the subroutines below falls into the first category. +* Especially, the coding of {add,and,or,sub,...}_{byte,word} +* subroutines are an especially glaring case of the third guideline. +* Since so much of the code is cloned from other modules (compare +* opcode #00 to opcode #01), making the basic operations subroutine +* calls is especially important; otherwise mistakes in coding an +* "add" would represent a nightmare in maintenance. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +void x86emuOp_illegal_op( + u8 op1) +{ + START_OF_INSTR(); + DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-1,op1); + HALT_SYS(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x00 +****************************************************************************/ +void x86emuOp_add_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x01 +****************************************************************************/ +void x86emuOp_add_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = add_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x02 +****************************************************************************/ +void x86emuOp_add_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x03 +****************************************************************************/ +void x86emuOp_add_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = add_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x04 +****************************************************************************/ +void x86emuOp_add_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADD\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = add_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x05 +****************************************************************************/ +void x86emuOp_add_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("ADD\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("ADD\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = add_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = add_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x06 +****************************************************************************/ +void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tES\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_ES); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x07 +****************************************************************************/ +void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tES\n"); + TRACE_AND_STEP(); + M.x86.R_ES = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x08 +****************************************************************************/ +void x86emuOp_or_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x09 +****************************************************************************/ +void x86emuOp_or_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = or_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0a +****************************************************************************/ +void x86emuOp_or_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0b +****************************************************************************/ +void x86emuOp_or_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("OR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = or_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0c +****************************************************************************/ +void x86emuOp_or_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("OR\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = or_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0d +****************************************************************************/ +void x86emuOp_or_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OR\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("OR\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = or_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = or_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0e +****************************************************************************/ +void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tCS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f. Escape for two-byte opcode (286 or better) +****************************************************************************/ +void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + INC_DECODED_INST_LEN(1); + (*x86emu_optab2[op2])(op2); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x10 +****************************************************************************/ +void x86emuOp_adc_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x11 +****************************************************************************/ +void x86emuOp_adc_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = adc_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x12 +****************************************************************************/ +void x86emuOp_adc_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x13 +****************************************************************************/ +void x86emuOp_adc_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = adc_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x14 +****************************************************************************/ +void x86emuOp_adc_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("ADC\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = adc_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x15 +****************************************************************************/ +void x86emuOp_adc_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("ADC\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("ADC\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = adc_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = adc_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x16 +****************************************************************************/ +void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tSS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_SS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x17 +****************************************************************************/ +void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tSS\n"); + TRACE_AND_STEP(); + M.x86.R_SS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x18 +****************************************************************************/ +void x86emuOp_sbb_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x19 +****************************************************************************/ +void x86emuOp_sbb_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sbb_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1a +****************************************************************************/ +void x86emuOp_sbb_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1b +****************************************************************************/ +void x86emuOp_sbb_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sbb_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1c +****************************************************************************/ +void x86emuOp_sbb_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SBB\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = sbb_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1d +****************************************************************************/ +void x86emuOp_sbb_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SBB\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("SBB\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = sbb_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = sbb_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1e +****************************************************************************/ +void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tDS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_DS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x1f +****************************************************************************/ +void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tDS\n"); + TRACE_AND_STEP(); + M.x86.R_DS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x20 +****************************************************************************/ +void x86emuOp_and_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x21 +****************************************************************************/ +void x86emuOp_and_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = and_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x22 +****************************************************************************/ +void x86emuOp_and_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x23 +****************************************************************************/ +void x86emuOp_and_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("AND\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + break; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + break; + } + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = and_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x24 +****************************************************************************/ +void x86emuOp_and_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("AND\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = and_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x25 +****************************************************************************/ +void x86emuOp_and_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("AND\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("AND\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = and_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = and_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x26 +****************************************************************************/ +void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ES:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_ES; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x27 +****************************************************************************/ +void x86emuOp_daa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAA\n"); + TRACE_AND_STEP(); + M.x86.R_AL = daa_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x28 +****************************************************************************/ +void x86emuOp_sub_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x29 +****************************************************************************/ +void x86emuOp_sub_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = sub_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2a +****************************************************************************/ +void x86emuOp_sub_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2b +****************************************************************************/ +void x86emuOp_sub_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = sub_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2c +****************************************************************************/ +void x86emuOp_sub_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("SUB\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = sub_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2d +****************************************************************************/ +void x86emuOp_sub_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SUB\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("SUB\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = sub_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = sub_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2e +****************************************************************************/ +void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("CS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_CS; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x2f +****************************************************************************/ +void x86emuOp_das(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DAS\n"); + TRACE_AND_STEP(); + M.x86.R_AL = das_byte(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x30 +****************************************************************************/ +void x86emuOp_xor_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_byte(destval, *srcreg); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x31 +****************************************************************************/ +void x86emuOp_xor_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_long(destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = xor_word(destval, *srcreg); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x32 +****************************************************************************/ +void x86emuOp_xor_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x33 +****************************************************************************/ +void x86emuOp_xor_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = xor_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x34 +****************************************************************************/ +void x86emuOp_xor_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("XOR\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + M.x86.R_AL = xor_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x35 +****************************************************************************/ +void x86emuOp_xor_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XOR\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("XOR\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = xor_long(M.x86.R_EAX, srcval); + } else { + M.x86.R_AX = xor_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x36 +****************************************************************************/ +void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_SS; + /* no DECODE_CLEAR_SEGOVR ! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x37 +****************************************************************************/ +void x86emuOp_aaa(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAA\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aaa_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x38 +****************************************************************************/ +void x86emuOp_cmp_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg, *srcreg; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(destval, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x39 +****************************************************************************/ +void x86emuOp_cmp_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(destval, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3a +****************************************************************************/ +void x86emuOp_cmp_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, srcval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3b +****************************************************************************/ +void x86emuOp_cmp_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, srcval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + cmp_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3c +****************************************************************************/ +void x86emuOp_cmp_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("CMP\tAL,"); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + cmp_byte(M.x86.R_AL, srcval); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3d +****************************************************************************/ +void x86emuOp_cmp_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMP\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("CMP\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + cmp_long(M.x86.R_EAX, srcval); + } else { + cmp_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3e +****************************************************************************/ +void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_DS; + /* NO DECODE_CLEAR_SEGOVR! */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x3f +****************************************************************************/ +void x86emuOp_aas(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("AAS\n"); + TRACE_AND_STEP(); + M.x86.R_AX = aas_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x40 +****************************************************************************/ +void x86emuOp_inc_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEAX\n"); + } else { + DECODE_PRINTF("INC\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = inc_long(M.x86.R_EAX); + } else { + M.x86.R_AX = inc_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x41 +****************************************************************************/ +void x86emuOp_inc_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tECX\n"); + } else { + DECODE_PRINTF("INC\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = inc_long(M.x86.R_ECX); + } else { + M.x86.R_CX = inc_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x42 +****************************************************************************/ +void x86emuOp_inc_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEDX\n"); + } else { + DECODE_PRINTF("INC\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = inc_long(M.x86.R_EDX); + } else { + M.x86.R_DX = inc_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x43 +****************************************************************************/ +void x86emuOp_inc_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEBX\n"); + } else { + DECODE_PRINTF("INC\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = inc_long(M.x86.R_EBX); + } else { + M.x86.R_BX = inc_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x44 +****************************************************************************/ +void x86emuOp_inc_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tESP\n"); + } else { + DECODE_PRINTF("INC\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = inc_long(M.x86.R_ESP); + } else { + M.x86.R_SP = inc_word(M.x86.R_SP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x45 +****************************************************************************/ +void x86emuOp_inc_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEBP\n"); + } else { + DECODE_PRINTF("INC\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = inc_long(M.x86.R_EBP); + } else { + M.x86.R_BP = inc_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x46 +****************************************************************************/ +void x86emuOp_inc_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tESI\n"); + } else { + DECODE_PRINTF("INC\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = inc_long(M.x86.R_ESI); + } else { + M.x86.R_SI = inc_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x47 +****************************************************************************/ +void x86emuOp_inc_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tEDI\n"); + } else { + DECODE_PRINTF("INC\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = inc_long(M.x86.R_EDI); + } else { + M.x86.R_DI = inc_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x48 +****************************************************************************/ +void x86emuOp_dec_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEAX\n"); + } else { + DECODE_PRINTF("DEC\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = dec_long(M.x86.R_EAX); + } else { + M.x86.R_AX = dec_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x49 +****************************************************************************/ +void x86emuOp_dec_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tECX\n"); + } else { + DECODE_PRINTF("DEC\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = dec_long(M.x86.R_ECX); + } else { + M.x86.R_CX = dec_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4a +****************************************************************************/ +void x86emuOp_dec_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEDX\n"); + } else { + DECODE_PRINTF("DEC\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = dec_long(M.x86.R_EDX); + } else { + M.x86.R_DX = dec_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4b +****************************************************************************/ +void x86emuOp_dec_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEBX\n"); + } else { + DECODE_PRINTF("DEC\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = dec_long(M.x86.R_EBX); + } else { + M.x86.R_BX = dec_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4c +****************************************************************************/ +void x86emuOp_dec_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tESP\n"); + } else { + DECODE_PRINTF("DEC\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = dec_long(M.x86.R_ESP); + } else { + M.x86.R_SP = dec_word(M.x86.R_SP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4d +****************************************************************************/ +void x86emuOp_dec_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEBP\n"); + } else { + DECODE_PRINTF("DEC\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = dec_long(M.x86.R_EBP); + } else { + M.x86.R_BP = dec_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4e +****************************************************************************/ +void x86emuOp_dec_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tESI\n"); + } else { + DECODE_PRINTF("DEC\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = dec_long(M.x86.R_ESI); + } else { + M.x86.R_SI = dec_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x4f +****************************************************************************/ +void x86emuOp_dec_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tEDI\n"); + } else { + DECODE_PRINTF("DEC\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = dec_long(M.x86.R_EDI); + } else { + M.x86.R_DI = dec_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x50 +****************************************************************************/ +void x86emuOp_push_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEAX\n"); + } else { + DECODE_PRINTF("PUSH\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EAX); + } else { + push_word(M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x51 +****************************************************************************/ +void x86emuOp_push_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tECX\n"); + } else { + DECODE_PRINTF("PUSH\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ECX); + } else { + push_word(M.x86.R_CX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x52 +****************************************************************************/ +void x86emuOp_push_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEDX\n"); + } else { + DECODE_PRINTF("PUSH\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EDX); + } else { + push_word(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x53 +****************************************************************************/ +void x86emuOp_push_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEBX\n"); + } else { + DECODE_PRINTF("PUSH\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EBX); + } else { + push_word(M.x86.R_BX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x54 +****************************************************************************/ +void x86emuOp_push_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tESP\n"); + } else { + DECODE_PRINTF("PUSH\tSP\n"); + } + TRACE_AND_STEP(); + /* Always push (E)SP, since we are emulating an i386 and above + * processor. This is necessary as some BIOS'es use this to check + * what type of processor is in the system. + */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ESP); + } else { + push_word((u16)(M.x86.R_SP)); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x55 +****************************************************************************/ +void x86emuOp_push_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEBP\n"); + } else { + DECODE_PRINTF("PUSH\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EBP); + } else { + push_word(M.x86.R_BP); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x56 +****************************************************************************/ +void x86emuOp_push_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tESI\n"); + } else { + DECODE_PRINTF("PUSH\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_ESI); + } else { + push_word(M.x86.R_SI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x57 +****************************************************************************/ +void x86emuOp_push_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSH\tEDI\n"); + } else { + DECODE_PRINTF("PUSH\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EDI); + } else { + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x58 +****************************************************************************/ +void x86emuOp_pop_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEAX\n"); + } else { + DECODE_PRINTF("POP\tAX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x59 +****************************************************************************/ +void x86emuOp_pop_CX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tECX\n"); + } else { + DECODE_PRINTF("POP\tCX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = pop_long(); + } else { + M.x86.R_CX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5a +****************************************************************************/ +void x86emuOp_pop_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEDX\n"); + } else { + DECODE_PRINTF("POP\tDX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = pop_long(); + } else { + M.x86.R_DX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5b +****************************************************************************/ +void x86emuOp_pop_BX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEBX\n"); + } else { + DECODE_PRINTF("POP\tBX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = pop_long(); + } else { + M.x86.R_BX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5c +****************************************************************************/ +void x86emuOp_pop_SP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tESP\n"); + } else { + DECODE_PRINTF("POP\tSP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = pop_long(); + } else { + M.x86.R_SP = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5d +****************************************************************************/ +void x86emuOp_pop_BP(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEBP\n"); + } else { + DECODE_PRINTF("POP\tBP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = pop_long(); + } else { + M.x86.R_BP = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5e +****************************************************************************/ +void x86emuOp_pop_SI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tESI\n"); + } else { + DECODE_PRINTF("POP\tSI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = pop_long(); + } else { + M.x86.R_SI = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x5f +****************************************************************************/ +void x86emuOp_pop_DI(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POP\tEDI\n"); + } else { + DECODE_PRINTF("POP\tDI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + } else { + M.x86.R_DI = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x60 +****************************************************************************/ +void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHAD\n"); + } else { + DECODE_PRINTF("PUSHA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 old_sp = M.x86.R_ESP; + + push_long(M.x86.R_EAX); + push_long(M.x86.R_ECX); + push_long(M.x86.R_EDX); + push_long(M.x86.R_EBX); + push_long(old_sp); + push_long(M.x86.R_EBP); + push_long(M.x86.R_ESI); + push_long(M.x86.R_EDI); + } else { + u16 old_sp = M.x86.R_SP; + + push_word(M.x86.R_AX); + push_word(M.x86.R_CX); + push_word(M.x86.R_DX); + push_word(M.x86.R_BX); + push_word(old_sp); + push_word(M.x86.R_BP); + push_word(M.x86.R_SI); + push_word(M.x86.R_DI); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x61 +****************************************************************************/ +void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPAD\n"); + } else { + DECODE_PRINTF("POPA\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = pop_long(); + M.x86.R_ESI = pop_long(); + M.x86.R_EBP = pop_long(); + M.x86.R_ESP += 4; /* skip ESP */ + M.x86.R_EBX = pop_long(); + M.x86.R_EDX = pop_long(); + M.x86.R_ECX = pop_long(); + M.x86.R_EAX = pop_long(); + } else { + M.x86.R_DI = pop_word(); + M.x86.R_SI = pop_word(); + M.x86.R_BP = pop_word(); + M.x86.R_SP += 2; /* skip SP */ + M.x86.R_BX = pop_word(); + M.x86.R_DX = pop_word(); + M.x86.R_CX = pop_word(); + M.x86.R_AX = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ + +/**************************************************************************** +REMARKS: +Handles opcode 0x64 +****************************************************************************/ +void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("FS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_FS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x65 +****************************************************************************/ +void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("GS:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_SEGOVR_GS; + /* + * note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4 + * opcode subroutines we do not want to do this. + */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x66 - prefix for 32-bit register +****************************************************************************/ +void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("DATA:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_DATA; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x67 - prefix for 32-bit address +****************************************************************************/ +void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("ADDR:\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_ADDR; + /* note no DECODE_CLEAR_SEGOVR here. */ + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x68 +****************************************************************************/ +void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 imm; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + imm = fetch_long_imm(); + } else { + imm = fetch_word_imm(); + } + DECODE_PRINTF2("PUSH\t%x\n", imm); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(imm); + } else { + push_word((u16)imm); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x69 +****************************************************************************/ +void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6a +****************************************************************************/ +void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 imm; + + START_OF_INSTR(); + imm = (s8)fetch_byte_imm(); + DECODE_PRINTF2("PUSH\t%d\n", imm); + TRACE_AND_STEP(); + push_word(imm); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6b +****************************************************************************/ +void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + s8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6c +****************************************************************************/ +void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("INSB\n"); + ins(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6d +****************************************************************************/ +void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INSD\n"); + ins(4); + } else { + DECODE_PRINTF("INSW\n"); + ins(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6e +****************************************************************************/ +void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUTSB\n"); + outs(1); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x6f +****************************************************************************/ +void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUTSD\n"); + outs(4); + } else { + DECODE_PRINTF("OUTSW\n"); + outs(2); + } + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x70 +****************************************************************************/ +void x86emuOp_jump_near_O(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JO\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x71 +****************************************************************************/ +void x86emuOp_jump_near_NO(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if overflow is not set */ + START_OF_INSTR(); + DECODE_PRINTF("JNO\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_OF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x72 +****************************************************************************/ +void x86emuOp_jump_near_B(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JB\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_CF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x73 +****************************************************************************/ +void x86emuOp_jump_near_NB(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is clear. */ + START_OF_INSTR(); + DECODE_PRINTF("JNB\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_CF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x74 +****************************************************************************/ +void x86emuOp_jump_near_Z(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if zero flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x75 +****************************************************************************/ +void x86emuOp_jump_near_NZ(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if zero flag is clear. */ + START_OF_INSTR(); + DECODE_PRINTF("JNZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x76 +****************************************************************************/ +void x86emuOp_jump_near_BE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is set or if the zero + flag is set. */ + START_OF_INSTR(); + DECODE_PRINTF("JBE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x77 +****************************************************************************/ +void x86emuOp_jump_near_NBE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if carry flag is clear and if the zero + flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNBE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF))) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x78 +****************************************************************************/ +void x86emuOp_jump_near_S(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if sign flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JS\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_SF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x79 +****************************************************************************/ +void x86emuOp_jump_near_NS(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if sign flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNS\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_SF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7a +****************************************************************************/ +void x86emuOp_jump_near_P(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if parity flag is set (even parity) */ + START_OF_INSTR(); + DECODE_PRINTF("JP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_PF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7b +****************************************************************************/ +void x86emuOp_jump_near_NP(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + + /* jump to byte offset if parity flag is clear (odd parity) */ + START_OF_INSTR(); + DECODE_PRINTF("JNP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (!ACCESS_FLAG(F_PF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7c +****************************************************************************/ +void x86emuOp_jump_near_L(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag. */ + START_OF_INSTR(); + DECODE_PRINTF("JL\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if (sf ^ of) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7d +****************************************************************************/ +void x86emuOp_jump_near_NL(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag. */ + START_OF_INSTR(); + DECODE_PRINTF("JNL\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + /* note: inverse of above, but using == instead of xor. */ + if (sf == of) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7e +****************************************************************************/ +void x86emuOp_jump_near_LE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag not equal to overflow flag + or the zero flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JLE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if ((sf ^ of) || ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x7f +****************************************************************************/ +void x86emuOp_jump_near_NLE(u8 X86EMU_UNUSED(op1)) +{ + s8 offset; + u16 target; + int sf, of; + + /* jump to byte offset if sign flag equal to overflow flag. + and the zero flag is clear */ + START_OF_INSTR(); + DECODE_PRINTF("JNLE\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + (s16)offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + sf = ACCESS_FLAG(F_SF) != 0; + of = ACCESS_FLAG(F_OF) != 0; + if ((sf == of) && !ACCESS_FLAG(F_ZF)) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u8 (*opc80_byte_operation[])(u8 d, u8 s) = +{ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x80 +****************************************************************************/ +void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc80_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u16 (*opc81_word_operation[])(u16 d, u16 s) = +{ + add_word, /*00 */ + or_word, /*01 */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ + sub_word, /*05 */ + xor_word, /*06 */ + cmp_word, /*07 */ +}; + +static u32 (*opc81_long_operation[])(u32 d, u32 s) = +{ + add_long, /*00 */ + or_long, /*01 */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ + sub_long, /*05 */ + xor_long, /*06 */ + cmp_long, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x81 +****************************************************************************/ +void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* + * Know operation, decode the mod byte to find the addressing + * mode. + */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc81_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u8 (*opc82_byte_operation[])(u8 s, u8 d) = +{ + add_byte, /*00 */ + or_byte, /*01 */ /*YYY UNUSED ???? */ + adc_byte, /*02 */ + sbb_byte, /*03 */ + and_byte, /*04 */ /*YYY UNUSED ???? */ + sub_byte, /*05 */ + xor_byte, /*06 */ /*YYY UNUSED ???? */ + cmp_byte, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x82 +****************************************************************************/ +void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + u8 destval; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc82_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +static u16 (*opc83_word_operation[])(u16 s, u16 d) = +{ + add_word, /*00 */ + or_word, /*01 */ /*YYY UNUSED ???? */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ /*YYY UNUSED ???? */ + sub_word, /*05 */ + xor_word, /*06 */ /*YYY UNUSED ???? */ + cmp_word, /*07 */ +}; + +static u32 (*opc83_long_operation[])(u32 s, u32 d) = +{ + add_long, /*00 */ + or_long, /*01 */ /*YYY UNUSED ???? */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ /*YYY UNUSED ???? */ + sub_long, /*05 */ + xor_long, /*06 */ /*YYY UNUSED ???? */ + cmp_long, /*07 */ +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0x83 +****************************************************************************/ +void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Weirdo special case instruction format. Part of the opcode + * held below in "RH". Doubly nested case would result, except + * that the decoded instruction Similar to opcode 81, except that + * the immediate byte is sign extended to a word length. + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*opc83_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x84 +****************************************************************************/ +void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(*destreg, *srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x85 +****************************************************************************/ +void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(*destreg, *srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x86 +****************************************************************************/ +void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + u8 destval; + u8 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x87 +****************************************************************************/ +void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("XCHG\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 tmp; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } else { + u16 *destreg,*srcreg; + u16 tmp; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x88 +****************************************************************************/ +void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x89 +****************************************************************************/ +void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8a +****************************************************************************/ +void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg, *srcreg; + uint srcoffset; + u8 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8b +****************************************************************************/ +void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8c +****************************************************************************/ +void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint destoffset; + u16 destval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8d +****************************************************************************/ +void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *srcreg; + uint destoffset; + +/* + * TODO: Need to handle address size prefix! + * + * lea eax,[eax+ebx*2] ?? + */ + + START_OF_INSTR(); + DECODE_PRINTF("LEA\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + break; + case 1: + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + break; + case 2: + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + break; + case 3: /* register to register */ + /* undefined. Do nothing. */ + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8e +****************************************************************************/ +void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u16 *destreg, *srcreg; + uint srcoffset; + u16 srcval; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + /* + * Clean up, and reset all the R_xSP pointers to the correct + * locations. This is about 3x too much overhead (doing all the + * segreg ptrs when only one is needed, but this instruction + * *cannot* be that common, and this isn't too much work anyway. + */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x8f +****************************************************************************/ +void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("POP\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_long(); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_word(); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x90 +****************************************************************************/ +void x86emuOp_nop(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("NOP\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x91 +****************************************************************************/ +void x86emuOp_xchg_word_AX_CX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ECX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,CX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ECX; + M.x86.R_ECX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_CX; + M.x86.R_CX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x92 +****************************************************************************/ +void x86emuOp_xchg_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EDX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EDX; + M.x86.R_EDX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_DX; + M.x86.R_DX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x93 +****************************************************************************/ +void x86emuOp_xchg_word_AX_BX(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EBX\n"); + } else { + DECODE_PRINTF("XCHG\tAX,BX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EBX; + M.x86.R_EBX = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_BX; + M.x86.R_BX = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x94 +****************************************************************************/ +void x86emuOp_xchg_word_AX_SP(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ESP\n"); + } else { + DECODE_PRINTF("XCHG\tAX,SP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ESP; + M.x86.R_ESP = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_SP; + M.x86.R_SP = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x95 +****************************************************************************/ +void x86emuOp_xchg_word_AX_BP(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EBP\n"); + } else { + DECODE_PRINTF("XCHG\tAX,BP\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EBP; + M.x86.R_EBP = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_BP; + M.x86.R_BP = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x96 +****************************************************************************/ +void x86emuOp_xchg_word_AX_SI(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,ESI\n"); + } else { + DECODE_PRINTF("XCHG\tAX,SI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_ESI; + M.x86.R_ESI = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_SI; + M.x86.R_SI = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x97 +****************************************************************************/ +void x86emuOp_xchg_word_AX_DI(u8 X86EMU_UNUSED(op1)) +{ + u32 tmp; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("XCHG\tEAX,EDI\n"); + } else { + DECODE_PRINTF("XCHG\tAX,DI\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + tmp = M.x86.R_EAX; + M.x86.R_EAX = M.x86.R_EDI; + M.x86.R_EDI = tmp; + } else { + tmp = M.x86.R_AX; + M.x86.R_AX = M.x86.R_DI; + M.x86.R_DI = (u16)tmp; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x98 +****************************************************************************/ +void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CWDE\n"); + } else { + DECODE_PRINTF("CBW\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_AX & 0x8000) { + M.x86.R_EAX |= 0xffff0000; + } else { + M.x86.R_EAX &= 0x0000ffff; + } + } else { + if (M.x86.R_AL & 0x80) { + M.x86.R_AH = 0xff; + } else { + M.x86.R_AH = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x99 +****************************************************************************/ +void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CDQ\n"); + } else { + DECODE_PRINTF("CWD\n"); + } + DECODE_PRINTF("CWD\n"); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.R_EAX & 0x80000000) { + M.x86.R_EDX = 0xffffffff; + } else { + M.x86.R_EDX = 0x0; + } + } else { + if (M.x86.R_AX & 0x8000) { + M.x86.R_DX = 0xffff; + } else { + M.x86.R_DX = 0x0; + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9a +****************************************************************************/ +void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 farseg, faroff; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + faroff = fetch_word_imm(); + farseg = fetch_word_imm(); + DECODE_PRINTF2("%04x:", farseg); + DECODE_PRINTF2("%04x\n", faroff); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); + + /* XXX + * + * Hooked interrupt vectors calling into our "BIOS" will cause + * problems unless all intersegment stuff is checked for BIOS + * access. Check needed here. For moment, let it alone. + */ + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = farseg; + push_word(M.x86.R_IP); + M.x86.R_IP = faroff; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9b +****************************************************************************/ +void x86emuOp_wait(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("WAIT"); + TRACE_AND_STEP(); + /* NADA. */ + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9c +****************************************************************************/ +void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) +{ + u32 flags; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("PUSHFD\n"); + } else { + DECODE_PRINTF("PUSHF\n"); + } + TRACE_AND_STEP(); + + /* clear out *all* bits not representing flags, and turn on real bits */ + flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(flags); + } else { + push_word((u16)flags); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9d +****************************************************************************/ +void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("POPFD\n"); + } else { + DECODE_PRINTF("POPF\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EFLG = pop_long(); + } else { + M.x86.R_FLG = pop_word(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9e +****************************************************************************/ +void x86emuOp_sahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("SAHF\n"); + TRACE_AND_STEP(); + /* clear the lower bits of the flag register */ + M.x86.R_FLG &= 0xffffff00; + /* or in the AH register into the flags register */ + M.x86.R_FLG |= M.x86.R_AH; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x9f +****************************************************************************/ +void x86emuOp_lahf(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LAHF\n"); + TRACE_AND_STEP(); + M.x86.R_AH = (u8)(M.x86.R_FLG & 0xff); + /*undocumented TC++ behavior??? Nope. It's documented, but + you have too look real hard to notice it. */ + M.x86.R_AH |= 0x2; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa0 +****************************************************************************/ +void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]\n", offset); + TRACE_AND_STEP(); + M.x86.R_AL = fetch_data_byte(offset); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa1 +****************************************************************************/ +void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); + } else { + DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(offset); + } else { + M.x86.R_AX = fetch_data_word(offset); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa2 +****************************************************************************/ +void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x],AL\n", offset); + TRACE_AND_STEP(); + store_data_byte(offset, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa3 +****************************************************************************/ +void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 offset; + + START_OF_INSTR(); + offset = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); + } else { + DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long(offset, M.x86.R_EAX); + } else { + store_data_word(offset, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa4 +****************************************************************************/ +void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) +{ + u8 val; + u32 count; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("MOVS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + val = fetch_data_byte(M.x86.R_SI); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa5 +****************************************************************************/ +void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val; + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOVS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("MOVS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(M.x86.R_SI); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); + } else { + val = fetch_data_word(M.x86.R_SI); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa6 +****************************************************************************/ +void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val1, val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("CMPS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa7 +****************************************************************************/ +void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) +{ + u32 val1,val2; + int inc; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("CMPS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("CMPS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa8 +****************************************************************************/ +void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + int imm; + + START_OF_INSTR(); + DECODE_PRINTF("TEST\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%04x\n", imm); + TRACE_AND_STEP(); + test_byte(M.x86.R_AL, (u8)imm); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xa9 +****************************************************************************/ +void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("TEST\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("TEST\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + test_long(M.x86.R_EAX, srcval); + } else { + test_word(M.x86.R_AX, (u16)srcval); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaa +****************************************************************************/ +void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("STOS\tBYTE\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + TRACE_AND_STEP(); + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xab +****************************************************************************/ +void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("STOS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("STOS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); + } else { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xac +****************************************************************************/ +void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) +{ + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("LODS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xad +****************************************************************************/ +void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 count; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("LODS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("LODS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + count = 1; + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } + while (count--) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(M.x86.R_SI); + } else { + M.x86.R_AX = fetch_data_word(M.x86.R_SI); + } + M.x86.R_SI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xae +****************************************************************************/ +void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) +{ + s8 val2; + int inc; + + START_OF_INSTR(); + DECODE_PRINTF("SCAS\tBYTE\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -1; + else + inc = 1; + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xaf +****************************************************************************/ +void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) +{ + int inc; + u32 val; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("SCAS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; + } else { + DECODE_PRINTF("SCAS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_REPE) { + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; + } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + } else { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_DI += inc; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb0 +****************************************************************************/ +void x86emuOp_mov_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_AL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb1 +****************************************************************************/ +void x86emuOp_mov_byte_CL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tCL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_CL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb2 +****************************************************************************/ +void x86emuOp_mov_byte_DL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tDL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_DL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb3 +****************************************************************************/ +void x86emuOp_mov_byte_BL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tBL,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_BL = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb4 +****************************************************************************/ +void x86emuOp_mov_byte_AH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tAH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_AH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb5 +****************************************************************************/ +void x86emuOp_mov_byte_CH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tCH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_CH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb6 +****************************************************************************/ +void x86emuOp_mov_byte_DH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tDH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_DH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb7 +****************************************************************************/ +void x86emuOp_mov_byte_BH_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\tBH,"); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + M.x86.R_BH = imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb8 +****************************************************************************/ +void x86emuOp_mov_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEAX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tAX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = srcval; + } else { + M.x86.R_AX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xb9 +****************************************************************************/ +void x86emuOp_mov_word_CX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tECX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tCX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = srcval; + } else { + M.x86.R_CX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xba +****************************************************************************/ +void x86emuOp_mov_word_DX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEDX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tDX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDX = srcval; + } else { + M.x86.R_DX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbb +****************************************************************************/ +void x86emuOp_mov_word_BX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEBX,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tBX,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBX = srcval; + } else { + M.x86.R_BX = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbc +****************************************************************************/ +void x86emuOp_mov_word_SP_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tESP,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tSP,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESP = srcval; + } else { + M.x86.R_SP = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbd +****************************************************************************/ +void x86emuOp_mov_word_BP_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEBP,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tBP,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EBP = srcval; + } else { + M.x86.R_BP = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbe +****************************************************************************/ +void x86emuOp_mov_word_SI_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tESI,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tSI,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ESI = srcval; + } else { + M.x86.R_SI = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xbf +****************************************************************************/ +void x86emuOp_mov_word_DI_IMM(u8 X86EMU_UNUSED(op1)) +{ + u32 srcval; + + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("MOV\tEDI,"); + srcval = fetch_long_imm(); + } else { + DECODE_PRINTF("MOV\tDI,"); + srcval = fetch_word_imm(); + } + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EDI = srcval; + } else { + M.x86.R_DI = (u16)srcval; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* used by opcodes c0, d0, and d2. */ +static u8(*opcD0_byte_operation[])(u8 d, u8 s) = +{ + rol_byte, + ror_byte, + rcl_byte, + rcr_byte, + shl_byte, + shr_byte, + shl_byte, /* sal_byte === shl_byte by definition */ + sar_byte, +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0xc0 +****************************************************************************/ +void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* used by opcodes c1, d1, and d3. */ +static u16(*opcD1_word_operation[])(u16 s, u8 d) = +{ + rol_word, + ror_word, + rcl_word, + rcr_word, + shl_word, + shr_word, + shl_word, /* sal_byte === shl_byte by definition */ + sar_word, +}; + +/* used by opcodes c1, d1, and d3. */ +static u32 (*opcD1_long_operation[])(u32 s, u8 d) = +{ + rol_long, + ror_long, + rcl_long, + rcr_long, + shl_long, + shr_long, + shl_long, /* sal_byte === shl_byte by definition */ + sar_long, +}; + +/**************************************************************************** +REMARKS: +Handles opcode 0xc1 +****************************************************************************/ +void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc2 +****************************************************************************/ +void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RET\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc3 +****************************************************************************/ +void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RET\n"); + RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc4 +****************************************************************************/ +void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LES\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc5 +****************************************************************************/ +void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LDS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc6 +****************************************************************************/ +void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 imm; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc7 +****************************************************************************/ +void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOV\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + if (rh != 0) { + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } else { + u16 *destreg; + u16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc8 +****************************************************************************/ +void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) +{ + u16 local,frame_pointer; + u8 nesting; + int i; + + START_OF_INSTR(); + local = fetch_word_imm(); + nesting = fetch_byte_imm(); + DECODE_PRINTF2("ENTER %x\n", local); + DECODE_PRINTF2(",%x\n", nesting); + TRACE_AND_STEP(); + push_word(M.x86.R_BP); + frame_pointer = M.x86.R_SP; + if (nesting > 0) { + for (i = 1; i < nesting; i++) { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + } + push_word(frame_pointer); + } + M.x86.R_BP = frame_pointer; + M.x86.R_SP = (u16)(M.x86.R_SP - local); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xc9 +****************************************************************************/ +void x86emuOp_leave(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LEAVE\n"); + TRACE_AND_STEP(); + M.x86.R_SP = M.x86.R_BP; + M.x86.R_BP = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xca +****************************************************************************/ +void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 imm; + + START_OF_INSTR(); + DECODE_PRINTF("RETF\t"); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_SP += imm; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcb +****************************************************************************/ +void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("RETF\n"); + RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip); + TRACE_AND_STEP(); + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcc +****************************************************************************/ +void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) +{ + u16 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("INT 3\n"); + tmp = (u16) mem_access_word(3 * 4 + 2); + /* access the segment register */ + TRACE_AND_STEP(); + if (_X86EMU_intrTab[3]) { + (*_X86EMU_intrTab[3])(3); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(3 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(3 * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcd +****************************************************************************/ +void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 tmp; + u8 intnum; + + START_OF_INSTR(); + DECODE_PRINTF("INT\t"); + intnum = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", intnum); + tmp = mem_access_word(intnum * 4 + 2); + TRACE_AND_STEP(); + if (_X86EMU_intrTab[intnum]) { + (*_X86EMU_intrTab[intnum])(intnum); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intnum * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intnum * 4); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xce +****************************************************************************/ +void x86emuOp_into(u8 X86EMU_UNUSED(op1)) +{ + u16 tmp; + + START_OF_INSTR(); + DECODE_PRINTF("INTO\n"); + TRACE_AND_STEP(); + if (ACCESS_FLAG(F_OF)) { + tmp = mem_access_word(4 * 4 + 2); + if (_X86EMU_intrTab[4]) { + (*_X86EMU_intrTab[4])(4); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(4 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(4 * 4); + } + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xcf +****************************************************************************/ +void x86emuOp_iret(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IRET\n"); + + TRACE_AND_STEP(); + + M.x86.R_IP = pop_word(); + M.x86.R_CS = pop_word(); + M.x86.R_FLG = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd0 +****************************************************************************/ +void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, 1); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd1 +****************************************************************************/ +void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (*destreg, 1); + *destreg = destval; + } else { + u16 destval; + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (*destreg, 1); + *destreg = destval; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd2 +****************************************************************************/ +void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd3 +****************************************************************************/ +void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + u8 amt; + + /* + * Yet another weirdo special case instruction format. Part of + * the opcode held below in "RH". Doubly nested case would + * result, except that the decoded instruction + */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } + } +#endif + /* know operation, decode the mod byte to find the addressing + mode. */ + amt = M.x86.R_CL; + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd4 +****************************************************************************/ +void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAM\n"); + a = fetch_byte_imm(); /* this is a stupid encoding. */ + if (a != 10) { + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); + } + TRACE_AND_STEP(); + /* note the type change here --- returning AL and AH in AX. */ + M.x86.R_AX = aam_word(M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xd5 +****************************************************************************/ +void x86emuOp_aad(u8 X86EMU_UNUSED(op1)) +{ + u8 a; + + START_OF_INSTR(); + DECODE_PRINTF("AAD\n"); + a = fetch_byte_imm(); + TRACE_AND_STEP(); + M.x86.R_AX = aad_word(M.x86.R_AX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* opcode 0xd6 ILLEGAL OPCODE */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xd7 +****************************************************************************/ +void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) +{ + u16 addr; + + START_OF_INSTR(); + DECODE_PRINTF("XLAT\n"); + TRACE_AND_STEP(); + addr = (u16)(M.x86.R_BX + (u8)M.x86.R_AL); + M.x86.R_AL = fetch_data_byte(addr); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/* instuctions D8 .. DF are in i87_ops.c */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xe0 +****************************************************************************/ +void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPNE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe1 +****************************************************************************/ +void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOPE\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe2 +****************************************************************************/ +void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("LOOP\t"); + ip = (s8) fetch_byte_imm(); + ip += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_CX -= 1; + if (M.x86.R_CX != 0) + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe3 +****************************************************************************/ +void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + /* jump to byte offset if overflow flag is set */ + START_OF_INSTR(); + DECODE_PRINTF("JCXZ\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + if (M.x86.R_CX == 0) + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe4 +****************************************************************************/ +void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(port); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe5 +****************************************************************************/ +void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("IN\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("EAX,%x\n", port); + } else { + DECODE_PRINTF2("AX,%x\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(port); + } else { + M.x86.R_AX = (*sys_inw)(port); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe6 +****************************************************************************/ +void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + DECODE_PRINTF2("%x,AL\n", port); + TRACE_AND_STEP(); + (*sys_outb)(port, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe7 +****************************************************************************/ +void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) +{ + u8 port; + + START_OF_INSTR(); + DECODE_PRINTF("OUT\t"); + port = (u8) fetch_byte_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF2("%x,EAX\n", port); + } else { + DECODE_PRINTF2("%x,AX\n", port); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(port, M.x86.R_EAX); + } else { + (*sys_outw)(port, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe8 +****************************************************************************/ +void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + s16 ip; + + START_OF_INSTR(); + DECODE_PRINTF("CALL\t"); + ip = (s16) fetch_word_imm(); + ip += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", ip); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, ""); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xe9 +****************************************************************************/ +void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) +{ + int ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + ip = (s16)fetch_word_imm(); + ip += (s16)M.x86.R_IP; + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_IP = (u16)ip; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xea +****************************************************************************/ +void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 cs, ip; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\tFAR "); + ip = fetch_word_imm(); + cs = fetch_word_imm(); + DECODE_PRINTF2("%04x:", cs); + DECODE_PRINTF2("%04x\n", ip); + TRACE_AND_STEP(); + M.x86.R_IP = ip; + M.x86.R_CS = cs; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xeb +****************************************************************************/ +void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1)) +{ + u16 target; + s8 offset; + + START_OF_INSTR(); + DECODE_PRINTF("JMP\t"); + offset = (s8)fetch_byte_imm(); + target = (u16)(M.x86.R_IP + offset); + DECODE_PRINTF2("%x\n", target); + TRACE_AND_STEP(); + M.x86.R_IP = target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xec +****************************************************************************/ +void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("IN\tAL,DX\n"); + TRACE_AND_STEP(); + M.x86.R_AL = (*sys_inb)(M.x86.R_DX); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xed +****************************************************************************/ +void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("IN\tEAX,DX\n"); + } else { + DECODE_PRINTF("IN\tAX,DX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); + } else { + M.x86.R_AX = (*sys_inw)(M.x86.R_DX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xee +****************************************************************************/ +void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("OUT\tDX,AL\n"); + TRACE_AND_STEP(); + (*sys_outb)(M.x86.R_DX, M.x86.R_AL); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xef +****************************************************************************/ +void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("OUT\tDX,EAX\n"); + } else { + DECODE_PRINTF("OUT\tDX,AX\n"); + } + TRACE_AND_STEP(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); + } else { + (*sys_outw)(M.x86.R_DX, M.x86.R_AX); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf0 +****************************************************************************/ +void x86emuOp_lock(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("LOCK:\n"); + TRACE_AND_STEP(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*opcode 0xf1 ILLEGAL OPERATION */ + +/**************************************************************************** +REMARKS: +Handles opcode 0xf2 +****************************************************************************/ +void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPNE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPNE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf3 +****************************************************************************/ +void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("REPE\n"); + TRACE_AND_STEP(); + M.x86.mode |= SYSMODE_PREFIX_REPE; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf4 +****************************************************************************/ +void x86emuOp_halt(u8 X86EMU_UNUSED(op1)) +{ + START_OF_INSTR(); + DECODE_PRINTF("HALT\n"); + TRACE_AND_STEP(); + HALT_SYS(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf5 +****************************************************************************/ +void x86emuOp_cmc(u8 X86EMU_UNUSED(op1)) +{ + /* complement the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CMC\n"); + TRACE_AND_STEP(); + TOGGLE_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf6 +****************************************************************************/ +void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + u8 *destreg; + uint destoffset; + u8 destval, srcval; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: /* mod=00 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==00 */ + case 1: /* mod=01 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==01 */ + case 2: /* mod=10 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("NEG\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("MUL\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("IMUL\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("DIV\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + div_byte(destval); + break; + case 7: + DECODE_PRINTF("IDIV\tBYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + break; /* end mod==10 */ + case 3: /* mod=11 */ + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_byte(*destreg); + break; + case 3: + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_byte(*destreg); + break; + case 4: + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(*destreg); + break; + case 6: + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(*destreg); + break; + case 7: + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(*destreg); + break; + } + break; /* end mod==11 */ + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf7 +****************************************************************************/ +void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rl, rh; + uint destoffset; + + /* long, drawn out code follows. Double switch for a total + of 32 cases. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: /* mod=00 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==00 */ + case 1: /* mod=01 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=01 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==01 */ + case 2: /* mod=10 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,srcval; + + DECODE_PRINTF("TEST\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + test_long(destval, srcval); + } else { + u16 destval,srcval; + + DECODE_PRINTF("TEST\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + test_word(destval, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=10 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NOT\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NOT\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("NEG\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("NEG\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("MUL\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + mul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("MUL\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + mul_word(destval); + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IMUL\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + imul_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IMUL\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + imul_word(destval); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DIV\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + div_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("DIV\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + div_word(destval); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("IDIV\tDWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + idiv_long(destval); + } else { + u16 destval; + + DECODE_PRINTF("IDIV\tWORD PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + idiv_word(destval); + } + break; + } + break; /* end mod==10 */ + case 3: /* mod=11 */ + switch (rh) { + case 0: /* test word imm */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(*destreg, srcval); + } else { + u16 *destreg; + u16 srcval; + + DECODE_PRINTF("TEST\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(*destreg, srcval); + } + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("NOT\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_word(*destreg); + } + break; + case 3: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("NEG\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_word(*destreg); + } + break; + case 4: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(*destreg); /*!!! */ + } else { + u16 *destreg; + + DECODE_PRINTF("MUL\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(*destreg); /*!!! */ + } + break; + case 5: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("IMUL\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(*destreg); + } + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("DIV\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(*destreg); + } + break; + case 7: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(*destreg); + } else { + u16 *destreg; + + DECODE_PRINTF("IDIV\t"); + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(*destreg); + } + break; + } + break; /* end mod==11 */ + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf8 +****************************************************************************/ +void x86emuOp_clc(u8 X86EMU_UNUSED(op1)) +{ + /* clear the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("CLC\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xf9 +****************************************************************************/ +void x86emuOp_stc(u8 X86EMU_UNUSED(op1)) +{ + /* set the carry flag. */ + START_OF_INSTR(); + DECODE_PRINTF("STC\n"); + TRACE_AND_STEP(); + SET_FLAG(F_CF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfa +****************************************************************************/ +void x86emuOp_cli(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLI\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfb +****************************************************************************/ +void x86emuOp_sti(u8 X86EMU_UNUSED(op1)) +{ + /* enable interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STI\n"); + TRACE_AND_STEP(); + SET_FLAG(F_IF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfc +****************************************************************************/ +void x86emuOp_cld(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("CLD\n"); + TRACE_AND_STEP(); + CLEAR_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfd +****************************************************************************/ +void x86emuOp_std(u8 X86EMU_UNUSED(op1)) +{ + /* clear interrupts. */ + START_OF_INSTR(); + DECODE_PRINTF("STD\n"); + TRACE_AND_STEP(); + SET_FLAG(F_DF); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xfe +****************************************************************************/ +void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + u8 destval; + uint destoffset; + u8 *destreg; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("INC\t"); + break; + case 1: + DECODE_PRINTF("DEC\t"); + break; + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + HALT_SYS(); + break; + } + } +#endif + switch (mod) { + case 0: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: /* dec word ptr ... */ + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 1: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 2: + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = inc_byte(destval); + store_data_byte(destoffset, destval); + break; + case 1: + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = dec_byte(destval); + store_data_byte(destoffset, destval); + break; + } + break; + case 3: + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + TRACE_AND_STEP(); + *destreg = inc_byte(*destreg); + break; + case 1: + TRACE_AND_STEP(); + *destreg = dec_byte(*destreg); + break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0xff +****************************************************************************/ +void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) +{ + int mod, rh, rl; + uint destoffset = 0; + u16 *destreg; + u16 destval,destval2; + + /* Yet another special case instruction. */ + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); +#ifdef DEBUG + if (DEBUG_DECODE()) { + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tDWORD PTR "); + } else { + DECODE_PRINTF("INC\tWORD PTR "); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tDWORD PTR "); + } else { + DECODE_PRINTF("DEC\tWORD PTR "); + } + break; + case 2: + DECODE_PRINTF("CALL\t "); + break; + case 3: + DECODE_PRINTF("CALL\tFAR "); + break; + case 4: + DECODE_PRINTF("JMP\t"); + break; + case 5: + DECODE_PRINTF("JMP\tFAR "); + break; + case 6: + DECODE_PRINTF("PUSH\t"); + break; + case 7: + DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + HALT_SYS(); + break; + } + } +#endif + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: /* dec word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 1: + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 2: + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } + break; + case 3: + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_word(*destreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_word(*destreg); + } + break; + case 2: /* call word ptr ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + break; + case 3: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + + case 4: /* jmp ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + M.x86.R_IP = (u16) (*destreg); + break; + case 5: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*destreg); + } + break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Single byte operation code table: + **************************************************************************/ +void (*x86emu_optab[256])(u8) = +{ +/* 0x00 */ x86emuOp_add_byte_RM_R, +/* 0x01 */ x86emuOp_add_word_RM_R, +/* 0x02 */ x86emuOp_add_byte_R_RM, +/* 0x03 */ x86emuOp_add_word_R_RM, +/* 0x04 */ x86emuOp_add_byte_AL_IMM, +/* 0x05 */ x86emuOp_add_word_AX_IMM, +/* 0x06 */ x86emuOp_push_ES, +/* 0x07 */ x86emuOp_pop_ES, + +/* 0x08 */ x86emuOp_or_byte_RM_R, +/* 0x09 */ x86emuOp_or_word_RM_R, +/* 0x0a */ x86emuOp_or_byte_R_RM, +/* 0x0b */ x86emuOp_or_word_R_RM, +/* 0x0c */ x86emuOp_or_byte_AL_IMM, +/* 0x0d */ x86emuOp_or_word_AX_IMM, +/* 0x0e */ x86emuOp_push_CS, +/* 0x0f */ x86emuOp_two_byte, + +/* 0x10 */ x86emuOp_adc_byte_RM_R, +/* 0x11 */ x86emuOp_adc_word_RM_R, +/* 0x12 */ x86emuOp_adc_byte_R_RM, +/* 0x13 */ x86emuOp_adc_word_R_RM, +/* 0x14 */ x86emuOp_adc_byte_AL_IMM, +/* 0x15 */ x86emuOp_adc_word_AX_IMM, +/* 0x16 */ x86emuOp_push_SS, +/* 0x17 */ x86emuOp_pop_SS, + +/* 0x18 */ x86emuOp_sbb_byte_RM_R, +/* 0x19 */ x86emuOp_sbb_word_RM_R, +/* 0x1a */ x86emuOp_sbb_byte_R_RM, +/* 0x1b */ x86emuOp_sbb_word_R_RM, +/* 0x1c */ x86emuOp_sbb_byte_AL_IMM, +/* 0x1d */ x86emuOp_sbb_word_AX_IMM, +/* 0x1e */ x86emuOp_push_DS, +/* 0x1f */ x86emuOp_pop_DS, + +/* 0x20 */ x86emuOp_and_byte_RM_R, +/* 0x21 */ x86emuOp_and_word_RM_R, +/* 0x22 */ x86emuOp_and_byte_R_RM, +/* 0x23 */ x86emuOp_and_word_R_RM, +/* 0x24 */ x86emuOp_and_byte_AL_IMM, +/* 0x25 */ x86emuOp_and_word_AX_IMM, +/* 0x26 */ x86emuOp_segovr_ES, +/* 0x27 */ x86emuOp_daa, + +/* 0x28 */ x86emuOp_sub_byte_RM_R, +/* 0x29 */ x86emuOp_sub_word_RM_R, +/* 0x2a */ x86emuOp_sub_byte_R_RM, +/* 0x2b */ x86emuOp_sub_word_R_RM, +/* 0x2c */ x86emuOp_sub_byte_AL_IMM, +/* 0x2d */ x86emuOp_sub_word_AX_IMM, +/* 0x2e */ x86emuOp_segovr_CS, +/* 0x2f */ x86emuOp_das, + +/* 0x30 */ x86emuOp_xor_byte_RM_R, +/* 0x31 */ x86emuOp_xor_word_RM_R, +/* 0x32 */ x86emuOp_xor_byte_R_RM, +/* 0x33 */ x86emuOp_xor_word_R_RM, +/* 0x34 */ x86emuOp_xor_byte_AL_IMM, +/* 0x35 */ x86emuOp_xor_word_AX_IMM, +/* 0x36 */ x86emuOp_segovr_SS, +/* 0x37 */ x86emuOp_aaa, + +/* 0x38 */ x86emuOp_cmp_byte_RM_R, +/* 0x39 */ x86emuOp_cmp_word_RM_R, +/* 0x3a */ x86emuOp_cmp_byte_R_RM, +/* 0x3b */ x86emuOp_cmp_word_R_RM, +/* 0x3c */ x86emuOp_cmp_byte_AL_IMM, +/* 0x3d */ x86emuOp_cmp_word_AX_IMM, +/* 0x3e */ x86emuOp_segovr_DS, +/* 0x3f */ x86emuOp_aas, + +/* 0x40 */ x86emuOp_inc_AX, +/* 0x41 */ x86emuOp_inc_CX, +/* 0x42 */ x86emuOp_inc_DX, +/* 0x43 */ x86emuOp_inc_BX, +/* 0x44 */ x86emuOp_inc_SP, +/* 0x45 */ x86emuOp_inc_BP, +/* 0x46 */ x86emuOp_inc_SI, +/* 0x47 */ x86emuOp_inc_DI, + +/* 0x48 */ x86emuOp_dec_AX, +/* 0x49 */ x86emuOp_dec_CX, +/* 0x4a */ x86emuOp_dec_DX, +/* 0x4b */ x86emuOp_dec_BX, +/* 0x4c */ x86emuOp_dec_SP, +/* 0x4d */ x86emuOp_dec_BP, +/* 0x4e */ x86emuOp_dec_SI, +/* 0x4f */ x86emuOp_dec_DI, + +/* 0x50 */ x86emuOp_push_AX, +/* 0x51 */ x86emuOp_push_CX, +/* 0x52 */ x86emuOp_push_DX, +/* 0x53 */ x86emuOp_push_BX, +/* 0x54 */ x86emuOp_push_SP, +/* 0x55 */ x86emuOp_push_BP, +/* 0x56 */ x86emuOp_push_SI, +/* 0x57 */ x86emuOp_push_DI, + +/* 0x58 */ x86emuOp_pop_AX, +/* 0x59 */ x86emuOp_pop_CX, +/* 0x5a */ x86emuOp_pop_DX, +/* 0x5b */ x86emuOp_pop_BX, +/* 0x5c */ x86emuOp_pop_SP, +/* 0x5d */ x86emuOp_pop_BP, +/* 0x5e */ x86emuOp_pop_SI, +/* 0x5f */ x86emuOp_pop_DI, + +/* 0x60 */ x86emuOp_push_all, +/* 0x61 */ x86emuOp_pop_all, +/* 0x62 */ x86emuOp_illegal_op, /* bound */ +/* 0x63 */ x86emuOp_illegal_op, /* arpl */ +/* 0x64 */ x86emuOp_segovr_FS, +/* 0x65 */ x86emuOp_segovr_GS, +/* 0x66 */ x86emuOp_prefix_data, +/* 0x67 */ x86emuOp_prefix_addr, + +/* 0x68 */ x86emuOp_push_word_IMM, +/* 0x69 */ x86emuOp_imul_word_IMM, +/* 0x6a */ x86emuOp_push_byte_IMM, +/* 0x6b */ x86emuOp_imul_byte_IMM, +/* 0x6c */ x86emuOp_ins_byte, +/* 0x6d */ x86emuOp_ins_word, +/* 0x6e */ x86emuOp_outs_byte, +/* 0x6f */ x86emuOp_outs_word, + +/* 0x70 */ x86emuOp_jump_near_O, +/* 0x71 */ x86emuOp_jump_near_NO, +/* 0x72 */ x86emuOp_jump_near_B, +/* 0x73 */ x86emuOp_jump_near_NB, +/* 0x74 */ x86emuOp_jump_near_Z, +/* 0x75 */ x86emuOp_jump_near_NZ, +/* 0x76 */ x86emuOp_jump_near_BE, +/* 0x77 */ x86emuOp_jump_near_NBE, + +/* 0x78 */ x86emuOp_jump_near_S, +/* 0x79 */ x86emuOp_jump_near_NS, +/* 0x7a */ x86emuOp_jump_near_P, +/* 0x7b */ x86emuOp_jump_near_NP, +/* 0x7c */ x86emuOp_jump_near_L, +/* 0x7d */ x86emuOp_jump_near_NL, +/* 0x7e */ x86emuOp_jump_near_LE, +/* 0x7f */ x86emuOp_jump_near_NLE, + +/* 0x80 */ x86emuOp_opc80_byte_RM_IMM, +/* 0x81 */ x86emuOp_opc81_word_RM_IMM, +/* 0x82 */ x86emuOp_opc82_byte_RM_IMM, +/* 0x83 */ x86emuOp_opc83_word_RM_IMM, +/* 0x84 */ x86emuOp_test_byte_RM_R, +/* 0x85 */ x86emuOp_test_word_RM_R, +/* 0x86 */ x86emuOp_xchg_byte_RM_R, +/* 0x87 */ x86emuOp_xchg_word_RM_R, + +/* 0x88 */ x86emuOp_mov_byte_RM_R, +/* 0x89 */ x86emuOp_mov_word_RM_R, +/* 0x8a */ x86emuOp_mov_byte_R_RM, +/* 0x8b */ x86emuOp_mov_word_R_RM, +/* 0x8c */ x86emuOp_mov_word_RM_SR, +/* 0x8d */ x86emuOp_lea_word_R_M, +/* 0x8e */ x86emuOp_mov_word_SR_RM, +/* 0x8f */ x86emuOp_pop_RM, + +/* 0x90 */ x86emuOp_nop, +/* 0x91 */ x86emuOp_xchg_word_AX_CX, +/* 0x92 */ x86emuOp_xchg_word_AX_DX, +/* 0x93 */ x86emuOp_xchg_word_AX_BX, +/* 0x94 */ x86emuOp_xchg_word_AX_SP, +/* 0x95 */ x86emuOp_xchg_word_AX_BP, +/* 0x96 */ x86emuOp_xchg_word_AX_SI, +/* 0x97 */ x86emuOp_xchg_word_AX_DI, + +/* 0x98 */ x86emuOp_cbw, +/* 0x99 */ x86emuOp_cwd, +/* 0x9a */ x86emuOp_call_far_IMM, +/* 0x9b */ x86emuOp_wait, +/* 0x9c */ x86emuOp_pushf_word, +/* 0x9d */ x86emuOp_popf_word, +/* 0x9e */ x86emuOp_sahf, +/* 0x9f */ x86emuOp_lahf, + +/* 0xa0 */ x86emuOp_mov_AL_M_IMM, +/* 0xa1 */ x86emuOp_mov_AX_M_IMM, +/* 0xa2 */ x86emuOp_mov_M_AL_IMM, +/* 0xa3 */ x86emuOp_mov_M_AX_IMM, +/* 0xa4 */ x86emuOp_movs_byte, +/* 0xa5 */ x86emuOp_movs_word, +/* 0xa6 */ x86emuOp_cmps_byte, +/* 0xa7 */ x86emuOp_cmps_word, +/* 0xa8 */ x86emuOp_test_AL_IMM, +/* 0xa9 */ x86emuOp_test_AX_IMM, +/* 0xaa */ x86emuOp_stos_byte, +/* 0xab */ x86emuOp_stos_word, +/* 0xac */ x86emuOp_lods_byte, +/* 0xad */ x86emuOp_lods_word, +/* 0xac */ x86emuOp_scas_byte, +/* 0xad */ x86emuOp_scas_word, + + +/* 0xb0 */ x86emuOp_mov_byte_AL_IMM, +/* 0xb1 */ x86emuOp_mov_byte_CL_IMM, +/* 0xb2 */ x86emuOp_mov_byte_DL_IMM, +/* 0xb3 */ x86emuOp_mov_byte_BL_IMM, +/* 0xb4 */ x86emuOp_mov_byte_AH_IMM, +/* 0xb5 */ x86emuOp_mov_byte_CH_IMM, +/* 0xb6 */ x86emuOp_mov_byte_DH_IMM, +/* 0xb7 */ x86emuOp_mov_byte_BH_IMM, + +/* 0xb8 */ x86emuOp_mov_word_AX_IMM, +/* 0xb9 */ x86emuOp_mov_word_CX_IMM, +/* 0xba */ x86emuOp_mov_word_DX_IMM, +/* 0xbb */ x86emuOp_mov_word_BX_IMM, +/* 0xbc */ x86emuOp_mov_word_SP_IMM, +/* 0xbd */ x86emuOp_mov_word_BP_IMM, +/* 0xbe */ x86emuOp_mov_word_SI_IMM, +/* 0xbf */ x86emuOp_mov_word_DI_IMM, + +/* 0xc0 */ x86emuOp_opcC0_byte_RM_MEM, +/* 0xc1 */ x86emuOp_opcC1_word_RM_MEM, +/* 0xc2 */ x86emuOp_ret_near_IMM, +/* 0xc3 */ x86emuOp_ret_near, +/* 0xc4 */ x86emuOp_les_R_IMM, +/* 0xc5 */ x86emuOp_lds_R_IMM, +/* 0xc6 */ x86emuOp_mov_byte_RM_IMM, +/* 0xc7 */ x86emuOp_mov_word_RM_IMM, +/* 0xc8 */ x86emuOp_enter, +/* 0xc9 */ x86emuOp_leave, +/* 0xca */ x86emuOp_ret_far_IMM, +/* 0xcb */ x86emuOp_ret_far, +/* 0xcc */ x86emuOp_int3, +/* 0xcd */ x86emuOp_int_IMM, +/* 0xce */ x86emuOp_into, +/* 0xcf */ x86emuOp_iret, + +/* 0xd0 */ x86emuOp_opcD0_byte_RM_1, +/* 0xd1 */ x86emuOp_opcD1_word_RM_1, +/* 0xd2 */ x86emuOp_opcD2_byte_RM_CL, +/* 0xd3 */ x86emuOp_opcD3_word_RM_CL, +/* 0xd4 */ x86emuOp_aam, +/* 0xd5 */ x86emuOp_aad, +/* 0xd6 */ x86emuOp_illegal_op, /* Undocumented SETALC instruction */ +/* 0xd7 */ x86emuOp_xlat, +/* 0xd8 */ x86emuOp_esc_coprocess_d8, +/* 0xd9 */ x86emuOp_esc_coprocess_d9, +/* 0xda */ x86emuOp_esc_coprocess_da, +/* 0xdb */ x86emuOp_esc_coprocess_db, +/* 0xdc */ x86emuOp_esc_coprocess_dc, +/* 0xdd */ x86emuOp_esc_coprocess_dd, +/* 0xde */ x86emuOp_esc_coprocess_de, +/* 0xdf */ x86emuOp_esc_coprocess_df, + +/* 0xe0 */ x86emuOp_loopne, +/* 0xe1 */ x86emuOp_loope, +/* 0xe2 */ x86emuOp_loop, +/* 0xe3 */ x86emuOp_jcxz, +/* 0xe4 */ x86emuOp_in_byte_AL_IMM, +/* 0xe5 */ x86emuOp_in_word_AX_IMM, +/* 0xe6 */ x86emuOp_out_byte_IMM_AL, +/* 0xe7 */ x86emuOp_out_word_IMM_AX, + +/* 0xe8 */ x86emuOp_call_near_IMM, +/* 0xe9 */ x86emuOp_jump_near_IMM, +/* 0xea */ x86emuOp_jump_far_IMM, +/* 0xeb */ x86emuOp_jump_byte_IMM, +/* 0xec */ x86emuOp_in_byte_AL_DX, +/* 0xed */ x86emuOp_in_word_AX_DX, +/* 0xee */ x86emuOp_out_byte_DX_AL, +/* 0xef */ x86emuOp_out_word_DX_AX, + +/* 0xf0 */ x86emuOp_lock, +/* 0xf1 */ x86emuOp_illegal_op, +/* 0xf2 */ x86emuOp_repne, +/* 0xf3 */ x86emuOp_repe, +/* 0xf4 */ x86emuOp_halt, +/* 0xf5 */ x86emuOp_cmc, +/* 0xf6 */ x86emuOp_opcF6_byte_RM, +/* 0xf7 */ x86emuOp_opcF7_word_RM, + +/* 0xf8 */ x86emuOp_clc, +/* 0xf9 */ x86emuOp_stc, +/* 0xfa */ x86emuOp_cli, +/* 0xfb */ x86emuOp_sti, +/* 0xfc */ x86emuOp_cld, +/* 0xfd */ x86emuOp_std, +/* 0xfe */ x86emuOp_opcFE_byte_RM, +/* 0xff */ x86emuOp_opcFF_word_RM, +}; + +void tables_relocate(unsigned int offset) +{ + int i; + for (i=0; i<8; i++) + { + opc80_byte_operation[i] -= offset; + opc81_word_operation[i] -= offset; + opc81_long_operation[i] -= offset; + + opc82_byte_operation[i] -= offset; + opc83_word_operation[i] -= offset; + opc83_long_operation[i] -= offset; + + opcD0_byte_operation[i] -= offset; + opcD1_word_operation[i] -= offset; + opcD1_long_operation[i] -= offset; + } +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c b/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c new file mode 100644 index 000000000..d381307fa --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/ops2.c @@ -0,0 +1,2800 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 extended two-byte processor +* instructions. +* +****************************************************************************/ + +#include "x86emu/x86emui.h" + +/*----------------------------- Implementation ----------------------------*/ + +/**************************************************************************** +PARAMETERS: +op1 - Instruction op code + +REMARKS: +Handles illegal opcodes. +****************************************************************************/ +void x86emuOp2_illegal_op( + u8 op2) +{ + START_OF_INSTR(); + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-2,op2); + HALT_SYS(); + END_OF_INSTR(); +} + +#define xorl(a,b) ((a) && !(b)) || (!(a) && (b)) + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x80-0x8F +****************************************************************************/ +void x86emuOp2_long_jump(u8 op2) +{ + s32 target; + char *name = 0; + int cond = 0; + + /* conditional jump to word offset. */ + START_OF_INSTR(); + switch (op2) { + case 0x80: + name = "JO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x81: + name = "JNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x82: + name = "JB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x83: + name = "JNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x84: + name = "JZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x85: + name = "JNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x86: + name = "JBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x87: + name = "JNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x88: + name = "JS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x89: + name = "JNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x8a: + name = "JP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x8b: + name = "JNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x8c: + name = "JL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x8d: + name = "JNL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x8e: + name = "JLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x8f: + name = "JNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + target = (s16) fetch_word_imm(); + target += (s16) M.x86.R_IP; + DECODE_PRINTF2("%04x\n", target); + TRACE_AND_STEP(); + if (cond) + M.x86.R_IP = (u16)target; + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0x90-0x9F +****************************************************************************/ +void x86emuOp2_set_byte(u8 op2) +{ + int mod, rl, rh; + uint destoffset; + u8 *destreg; + char *name = 0; + int cond = 0; + + START_OF_INSTR(); + switch (op2) { + case 0x90: + name = "SETO\t"; + cond = ACCESS_FLAG(F_OF); + break; + case 0x91: + name = "SETNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; + case 0x92: + name = "SETB\t"; + cond = ACCESS_FLAG(F_CF); + break; + case 0x93: + name = "SETNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; + case 0x94: + name = "SETZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; + case 0x95: + name = "SETNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; + case 0x96: + name = "SETBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; + case 0x97: + name = "SETNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; + case 0x98: + name = "SETS\t"; + cond = ACCESS_FLAG(F_SF); + break; + case 0x99: + name = "SETNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; + case 0x9a: + name = "SETP\t"; + cond = ACCESS_FLAG(F_PF); + break; + case 0x9b: + name = "SETNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; + case 0x9c: + name = "SETL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9d: + name = "SETNL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; + case 0x9e: + name = "SETLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + case 0x9f: + name = "SETNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; + } + DECODE_PRINTF(name); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destoffset = decode_rm00_address(rl); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 1: + destoffset = decode_rm01_address(rl); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 2: + destoffset = decode_rm10_address(rl); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + break; + case 3: /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + TRACE_AND_STEP(); + *destreg = cond ? 0x01 : 0x00; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa0 +****************************************************************************/ +void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tFS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_FS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa1 +****************************************************************************/ +void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tFS\n"); + TRACE_AND_STEP(); + M.x86.R_FS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa3 +****************************************************************************/ +void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BT\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } else { + u16 *srcreg,*shiftreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa4 +****************************************************************************/ +void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,shift); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa5 +****************************************************************************/ +void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa8 +****************************************************************************/ +void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("PUSH\tGS\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_GS); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xa9 +****************************************************************************/ +void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2)) +{ + START_OF_INSTR(); + DECODE_PRINTF("POP\tGS\n"); + TRACE_AND_STEP(); + M.x86.R_GS = pop_word(); + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xaa +****************************************************************************/ +void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xac +****************************************************************************/ +void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + u8 shift; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,shift); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xad +****************************************************************************/ +void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint destoffset; + + START_OF_INSTR(); + DECODE_PRINTF("SHLD\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + destoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xaf +****************************************************************************/ +void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("IMUL\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_long(srcoffset); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_long(srcoffset); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_long(srcoffset); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + res = (s16)*destreg * (s16)*srcreg; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb2 +****************************************************************************/ +void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LSS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb3 +****************************************************************************/ +void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTR\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb4 +****************************************************************************/ +void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LFS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb5 +****************************************************************************/ +void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rh, rl; + u16 *dstreg; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("LGS\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 1: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 2: + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + break; + case 3: /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb6 +****************************************************************************/ +void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xb7 +****************************************************************************/ +void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVZX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xba +****************************************************************************/ +void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit; + + START_OF_INSTR(); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (rh) { + case 3: + DECODE_PRINTF("BT\t"); + break; + case 4: + DECODE_PRINTF("BTS\t"); + break; + case 5: + DECODE_PRINTF("BTR\t"); + break; + case 6: + DECODE_PRINTF("BTC\t"); + break; + default: + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", + M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); + HALT_SYS(); + } + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_long(srcoffset, srcval | mask); + break; + case 5: + store_data_long(srcoffset, srcval & ~mask); + break; + case 6: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_word(srcoffset, srcval | mask); + break; + case 5: + store_data_word(srcoffset, srcval & ~mask); + break; + case 6: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_long(srcoffset, srcval | mask); + break; + case 5: + store_data_long(srcoffset, srcval & ~mask); + break; + case 6: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_word(srcoffset, srcval | mask); + break; + case 5: + store_data_word(srcoffset, srcval & ~mask); + break; + case 6: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + u8 shift; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_long(srcoffset, srcval | mask); + break; + case 5: + store_data_long(srcoffset, srcval & ~mask); + break; + case 6: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + u8 shift; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 4: + store_data_word(srcoffset, srcval | mask); + break; + case 5: + store_data_word(srcoffset, srcval & ~mask); + break; + case 6: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 mask; + u8 shift; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 4: + *srcreg |= mask; + break; + case 5: + *srcreg &= ~mask; + break; + case 6: + *srcreg ^= mask; + break; + default: + break; + } + } else { + u16 *srcreg; + u16 mask; + u8 shift; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + TRACE_AND_STEP(); + bit = shift & 0xF; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 4: + *srcreg |= mask; + break; + case 5: + *srcreg &= ~mask; + break; + case 6: + *srcreg ^= mask; + break; + default: + break; + } + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbb +****************************************************************************/ +void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + int bit,disp; + + START_OF_INSTR(); + DECODE_PRINTF("BTC\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbc +****************************************************************************/ +void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSF\n"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch(mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg, *dstreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((*srcreg >> *dstreg) & 1) break; + } else { + u16 *srcreg, *dstreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((*srcreg >> *dstreg) & 1) break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbd +****************************************************************************/ +void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("BSF\n"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch(mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm00_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm01_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcoffset = decode_rm10_address(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg, *dstreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((*srcreg >> *dstreg) & 1) break; + } else { + u16 *srcreg, *dstreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((*srcreg >> *dstreg) & 1) break; + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbe +****************************************************************************/ +void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 2: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + break; + case 3: /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s8)*srcreg); + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s16)((s8)*srcreg); + } + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/**************************************************************************** +REMARKS: +Handles opcode 0x0f,0xbf +****************************************************************************/ +void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) +{ + int mod, rl, rh; + uint srcoffset; + u32 *destreg; + u32 srcval; + u16 *srcreg; + + START_OF_INSTR(); + DECODE_PRINTF("MOVSX\t"); + FETCH_DECODE_MODRM(mod, rh, rl); + switch (mod) { + case 0: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm00_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 1: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm01_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 2: + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rm10_address(rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + break; + case 3: /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s16)*srcreg); + break; + } + DECODE_CLEAR_SEGOVR(); + END_OF_INSTR(); +} + +/*************************************************************************** + * Double byte operation code table: + **************************************************************************/ +void (*x86emu_optab2[256])(u8) = +{ +/* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ +/* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ +/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ +/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ +/* 0x04 */ x86emuOp2_illegal_op, +/* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ +/* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ +/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ +/* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ +/* 0x0a */ x86emuOp2_illegal_op, +/* 0x0b */ x86emuOp2_illegal_op, +/* 0x0c */ x86emuOp2_illegal_op, +/* 0x0d */ x86emuOp2_illegal_op, +/* 0x0e */ x86emuOp2_illegal_op, +/* 0x0f */ x86emuOp2_illegal_op, + +/* 0x10 */ x86emuOp2_illegal_op, +/* 0x11 */ x86emuOp2_illegal_op, +/* 0x12 */ x86emuOp2_illegal_op, +/* 0x13 */ x86emuOp2_illegal_op, +/* 0x14 */ x86emuOp2_illegal_op, +/* 0x15 */ x86emuOp2_illegal_op, +/* 0x16 */ x86emuOp2_illegal_op, +/* 0x17 */ x86emuOp2_illegal_op, +/* 0x18 */ x86emuOp2_illegal_op, +/* 0x19 */ x86emuOp2_illegal_op, +/* 0x1a */ x86emuOp2_illegal_op, +/* 0x1b */ x86emuOp2_illegal_op, +/* 0x1c */ x86emuOp2_illegal_op, +/* 0x1d */ x86emuOp2_illegal_op, +/* 0x1e */ x86emuOp2_illegal_op, +/* 0x1f */ x86emuOp2_illegal_op, + +/* 0x20 */ x86emuOp2_illegal_op, /* mov reg32,creg (ring 0 PM) */ +/* 0x21 */ x86emuOp2_illegal_op, /* mov reg32,dreg (ring 0 PM) */ +/* 0x22 */ x86emuOp2_illegal_op, /* mov creg,reg32 (ring 0 PM) */ +/* 0x23 */ x86emuOp2_illegal_op, /* mov dreg,reg32 (ring 0 PM) */ +/* 0x24 */ x86emuOp2_illegal_op, /* mov reg32,treg (ring 0 PM) */ +/* 0x25 */ x86emuOp2_illegal_op, +/* 0x26 */ x86emuOp2_illegal_op, /* mov treg,reg32 (ring 0 PM) */ +/* 0x27 */ x86emuOp2_illegal_op, +/* 0x28 */ x86emuOp2_illegal_op, +/* 0x29 */ x86emuOp2_illegal_op, +/* 0x2a */ x86emuOp2_illegal_op, +/* 0x2b */ x86emuOp2_illegal_op, +/* 0x2c */ x86emuOp2_illegal_op, +/* 0x2d */ x86emuOp2_illegal_op, +/* 0x2e */ x86emuOp2_illegal_op, +/* 0x2f */ x86emuOp2_illegal_op, + +/* 0x30 */ x86emuOp2_illegal_op, +/* 0x31 */ x86emuOp2_illegal_op, +/* 0x32 */ x86emuOp2_illegal_op, +/* 0x33 */ x86emuOp2_illegal_op, +/* 0x34 */ x86emuOp2_illegal_op, +/* 0x35 */ x86emuOp2_illegal_op, +/* 0x36 */ x86emuOp2_illegal_op, +/* 0x37 */ x86emuOp2_illegal_op, +/* 0x38 */ x86emuOp2_illegal_op, +/* 0x39 */ x86emuOp2_illegal_op, +/* 0x3a */ x86emuOp2_illegal_op, +/* 0x3b */ x86emuOp2_illegal_op, +/* 0x3c */ x86emuOp2_illegal_op, +/* 0x3d */ x86emuOp2_illegal_op, +/* 0x3e */ x86emuOp2_illegal_op, +/* 0x3f */ x86emuOp2_illegal_op, + +/* 0x40 */ x86emuOp2_illegal_op, +/* 0x41 */ x86emuOp2_illegal_op, +/* 0x42 */ x86emuOp2_illegal_op, +/* 0x43 */ x86emuOp2_illegal_op, +/* 0x44 */ x86emuOp2_illegal_op, +/* 0x45 */ x86emuOp2_illegal_op, +/* 0x46 */ x86emuOp2_illegal_op, +/* 0x47 */ x86emuOp2_illegal_op, +/* 0x48 */ x86emuOp2_illegal_op, +/* 0x49 */ x86emuOp2_illegal_op, +/* 0x4a */ x86emuOp2_illegal_op, +/* 0x4b */ x86emuOp2_illegal_op, +/* 0x4c */ x86emuOp2_illegal_op, +/* 0x4d */ x86emuOp2_illegal_op, +/* 0x4e */ x86emuOp2_illegal_op, +/* 0x4f */ x86emuOp2_illegal_op, + +/* 0x50 */ x86emuOp2_illegal_op, +/* 0x51 */ x86emuOp2_illegal_op, +/* 0x52 */ x86emuOp2_illegal_op, +/* 0x53 */ x86emuOp2_illegal_op, +/* 0x54 */ x86emuOp2_illegal_op, +/* 0x55 */ x86emuOp2_illegal_op, +/* 0x56 */ x86emuOp2_illegal_op, +/* 0x57 */ x86emuOp2_illegal_op, +/* 0x58 */ x86emuOp2_illegal_op, +/* 0x59 */ x86emuOp2_illegal_op, +/* 0x5a */ x86emuOp2_illegal_op, +/* 0x5b */ x86emuOp2_illegal_op, +/* 0x5c */ x86emuOp2_illegal_op, +/* 0x5d */ x86emuOp2_illegal_op, +/* 0x5e */ x86emuOp2_illegal_op, +/* 0x5f */ x86emuOp2_illegal_op, + +/* 0x60 */ x86emuOp2_illegal_op, +/* 0x61 */ x86emuOp2_illegal_op, +/* 0x62 */ x86emuOp2_illegal_op, +/* 0x63 */ x86emuOp2_illegal_op, +/* 0x64 */ x86emuOp2_illegal_op, +/* 0x65 */ x86emuOp2_illegal_op, +/* 0x66 */ x86emuOp2_illegal_op, +/* 0x67 */ x86emuOp2_illegal_op, +/* 0x68 */ x86emuOp2_illegal_op, +/* 0x69 */ x86emuOp2_illegal_op, +/* 0x6a */ x86emuOp2_illegal_op, +/* 0x6b */ x86emuOp2_illegal_op, +/* 0x6c */ x86emuOp2_illegal_op, +/* 0x6d */ x86emuOp2_illegal_op, +/* 0x6e */ x86emuOp2_illegal_op, +/* 0x6f */ x86emuOp2_illegal_op, + +/* 0x70 */ x86emuOp2_illegal_op, +/* 0x71 */ x86emuOp2_illegal_op, +/* 0x72 */ x86emuOp2_illegal_op, +/* 0x73 */ x86emuOp2_illegal_op, +/* 0x74 */ x86emuOp2_illegal_op, +/* 0x75 */ x86emuOp2_illegal_op, +/* 0x76 */ x86emuOp2_illegal_op, +/* 0x77 */ x86emuOp2_illegal_op, +/* 0x78 */ x86emuOp2_illegal_op, +/* 0x79 */ x86emuOp2_illegal_op, +/* 0x7a */ x86emuOp2_illegal_op, +/* 0x7b */ x86emuOp2_illegal_op, +/* 0x7c */ x86emuOp2_illegal_op, +/* 0x7d */ x86emuOp2_illegal_op, +/* 0x7e */ x86emuOp2_illegal_op, +/* 0x7f */ x86emuOp2_illegal_op, + +/* 0x80 */ x86emuOp2_long_jump, +/* 0x81 */ x86emuOp2_long_jump, +/* 0x82 */ x86emuOp2_long_jump, +/* 0x83 */ x86emuOp2_long_jump, +/* 0x84 */ x86emuOp2_long_jump, +/* 0x85 */ x86emuOp2_long_jump, +/* 0x86 */ x86emuOp2_long_jump, +/* 0x87 */ x86emuOp2_long_jump, +/* 0x88 */ x86emuOp2_long_jump, +/* 0x89 */ x86emuOp2_long_jump, +/* 0x8a */ x86emuOp2_long_jump, +/* 0x8b */ x86emuOp2_long_jump, +/* 0x8c */ x86emuOp2_long_jump, +/* 0x8d */ x86emuOp2_long_jump, +/* 0x8e */ x86emuOp2_long_jump, +/* 0x8f */ x86emuOp2_long_jump, + +/* 0x90 */ x86emuOp2_set_byte, +/* 0x91 */ x86emuOp2_set_byte, +/* 0x92 */ x86emuOp2_set_byte, +/* 0x93 */ x86emuOp2_set_byte, +/* 0x94 */ x86emuOp2_set_byte, +/* 0x95 */ x86emuOp2_set_byte, +/* 0x96 */ x86emuOp2_set_byte, +/* 0x97 */ x86emuOp2_set_byte, +/* 0x98 */ x86emuOp2_set_byte, +/* 0x99 */ x86emuOp2_set_byte, +/* 0x9a */ x86emuOp2_set_byte, +/* 0x9b */ x86emuOp2_set_byte, +/* 0x9c */ x86emuOp2_set_byte, +/* 0x9d */ x86emuOp2_set_byte, +/* 0x9e */ x86emuOp2_set_byte, +/* 0x9f */ x86emuOp2_set_byte, + +/* 0xa0 */ x86emuOp2_push_FS, +/* 0xa1 */ x86emuOp2_pop_FS, +/* 0xa2 */ x86emuOp2_illegal_op, +/* 0xa3 */ x86emuOp2_bt_R, +/* 0xa4 */ x86emuOp2_shld_IMM, +/* 0xa5 */ x86emuOp2_shld_CL, +/* 0xa6 */ x86emuOp2_illegal_op, +/* 0xa7 */ x86emuOp2_illegal_op, +/* 0xa8 */ x86emuOp2_push_GS, +/* 0xa9 */ x86emuOp2_pop_GS, +/* 0xaa */ x86emuOp2_illegal_op, +/* 0xab */ x86emuOp2_bt_R, +/* 0xac */ x86emuOp2_shrd_IMM, +/* 0xad */ x86emuOp2_shrd_CL, +/* 0xae */ x86emuOp2_illegal_op, +/* 0xaf */ x86emuOp2_imul_R_RM, + +/* 0xb0 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb1 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */ +/* 0xb2 */ x86emuOp2_lss_R_IMM, +/* 0xb3 */ x86emuOp2_btr_R, +/* 0xb4 */ x86emuOp2_lfs_R_IMM, +/* 0xb5 */ x86emuOp2_lgs_R_IMM, +/* 0xb6 */ x86emuOp2_movzx_byte_R_RM, +/* 0xb7 */ x86emuOp2_movzx_word_R_RM, +/* 0xb8 */ x86emuOp2_illegal_op, +/* 0xb9 */ x86emuOp2_illegal_op, +/* 0xba */ x86emuOp2_btX_I, +/* 0xbb */ x86emuOp2_btc_R, +/* 0xbc */ x86emuOp2_bsf, +/* 0xbd */ x86emuOp2_bsr, +/* 0xbe */ x86emuOp2_movsx_byte_R_RM, +/* 0xbf */ x86emuOp2_movsx_word_R_RM, + +/* 0xc0 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc1 */ x86emuOp2_illegal_op, /* TODO: xadd */ +/* 0xc2 */ x86emuOp2_illegal_op, +/* 0xc3 */ x86emuOp2_illegal_op, +/* 0xc4 */ x86emuOp2_illegal_op, +/* 0xc5 */ x86emuOp2_illegal_op, +/* 0xc6 */ x86emuOp2_illegal_op, +/* 0xc7 */ x86emuOp2_illegal_op, +/* 0xc8 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xc9 */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xca */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcb */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcc */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcd */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xce */ x86emuOp2_illegal_op, /* TODO: bswap */ +/* 0xcf */ x86emuOp2_illegal_op, /* TODO: bswap */ + +/* 0xd0 */ x86emuOp2_illegal_op, +/* 0xd1 */ x86emuOp2_illegal_op, +/* 0xd2 */ x86emuOp2_illegal_op, +/* 0xd3 */ x86emuOp2_illegal_op, +/* 0xd4 */ x86emuOp2_illegal_op, +/* 0xd5 */ x86emuOp2_illegal_op, +/* 0xd6 */ x86emuOp2_illegal_op, +/* 0xd7 */ x86emuOp2_illegal_op, +/* 0xd8 */ x86emuOp2_illegal_op, +/* 0xd9 */ x86emuOp2_illegal_op, +/* 0xda */ x86emuOp2_illegal_op, +/* 0xdb */ x86emuOp2_illegal_op, +/* 0xdc */ x86emuOp2_illegal_op, +/* 0xdd */ x86emuOp2_illegal_op, +/* 0xde */ x86emuOp2_illegal_op, +/* 0xdf */ x86emuOp2_illegal_op, + +/* 0xe0 */ x86emuOp2_illegal_op, +/* 0xe1 */ x86emuOp2_illegal_op, +/* 0xe2 */ x86emuOp2_illegal_op, +/* 0xe3 */ x86emuOp2_illegal_op, +/* 0xe4 */ x86emuOp2_illegal_op, +/* 0xe5 */ x86emuOp2_illegal_op, +/* 0xe6 */ x86emuOp2_illegal_op, +/* 0xe7 */ x86emuOp2_illegal_op, +/* 0xe8 */ x86emuOp2_illegal_op, +/* 0xe9 */ x86emuOp2_illegal_op, +/* 0xea */ x86emuOp2_illegal_op, +/* 0xeb */ x86emuOp2_illegal_op, +/* 0xec */ x86emuOp2_illegal_op, +/* 0xed */ x86emuOp2_illegal_op, +/* 0xee */ x86emuOp2_illegal_op, +/* 0xef */ x86emuOp2_illegal_op, + +/* 0xf0 */ x86emuOp2_illegal_op, +/* 0xf1 */ x86emuOp2_illegal_op, +/* 0xf2 */ x86emuOp2_illegal_op, +/* 0xf3 */ x86emuOp2_illegal_op, +/* 0xf4 */ x86emuOp2_illegal_op, +/* 0xf5 */ x86emuOp2_illegal_op, +/* 0xf6 */ x86emuOp2_illegal_op, +/* 0xf7 */ x86emuOp2_illegal_op, +/* 0xf8 */ x86emuOp2_illegal_op, +/* 0xf9 */ x86emuOp2_illegal_op, +/* 0xfa */ x86emuOp2_illegal_op, +/* 0xfb */ x86emuOp2_illegal_op, +/* 0xfc */ x86emuOp2_illegal_op, +/* 0xfd */ x86emuOp2_illegal_op, +/* 0xfe */ x86emuOp2_illegal_op, +/* 0xff */ x86emuOp2_illegal_op, +}; diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c b/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c new file mode 100644 index 000000000..72b1bf287 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/prim_ops.c @@ -0,0 +1,2914 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file contains the code to implement the primitive +* machine operations used by the emulation code in ops.c +* +* Carry Chain Calculation +* +* This represents a somewhat expensive calculation which is +* apparently required to emulate the setting of the OF and AF flag. +* The latter is not so important, but the former is. The overflow +* flag is the XOR of the top two bits of the carry chain for an +* addition (similar for subtraction). Since we do not want to +* simulate the addition in a bitwise manner, we try to calculate the +* carry chain given the two operands and the result. +* +* So, given the following table, which represents the addition of two +* bits, we can derive a formula for the carry chain. +* +* a b cin r cout +* 0 0 0 0 0 +* 0 0 1 1 0 +* 0 1 0 1 0 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 1 +* 1 1 0 0 1 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 1 1 +* 1 | 0 0 1 0 +* +* By inspection, one gets: cc = ab + r'(a + b) +* +* That represents alot of operations, but NO CHOICE.... +* +* Borrow Chain Calculation. +* +* The following table represents the subtraction of two bits, from +* which we can derive a formula for the borrow chain. +* +* a b bin r bout +* 0 0 0 0 0 +* 0 0 1 1 1 +* 0 1 0 1 1 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 0 +* 1 1 0 0 0 +* 1 1 1 1 1 +* +* Construction of table for cout: +* +* ab +* r \ 00 01 11 10 +* |------------------ +* 0 | 0 1 0 0 +* 1 | 1 1 1 0 +* +* By inspection, one gets: bc = a'b + r(a' + b) +* +****************************************************************************/ + +#define PRIM_OPS_NO_REDEFINE_ASM +#include "x86emu/x86emui.h" + +/*------------------------- Global Variables ------------------------------*/ + +#ifndef __HAVE_INLINE_ASSEMBLER__ + +static u32 x86emu_parity_tab[8] = +{ + 0x96696996, + 0x69969669, + 0x69969669, + 0x96696996, + 0x69969669, + 0x96696996, + 0x96696996, + 0x69969669, +}; + +#endif + +#define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) +#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) + +/*----------------------------- Implementation ----------------------------*/ + +#ifndef __HAVE_INLINE_ASSEMBLER__ + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aaa_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d += 0x6; + d += 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAA instruction and side effects. +****************************************************************************/ +u16 aas_word(u16 d) +{ + u16 res; + if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { + d -= 0x6; + d -= 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + } + res = (u16)(d & 0xFF0F); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AAD instruction and side effects. +****************************************************************************/ +u16 aad_word(u16 d) +{ + u16 l; + u8 hb, lb; + + hb = (u8)((d >> 8) & 0xff); + lb = (u8)((d & 0xff)); + l = (u16)((lb + 10 * hb) & 0xFF); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the AAM instruction and side effects. +****************************************************************************/ +u16 aam_word(u8 d) +{ + u16 h, l; + + h = (u16)(d / 10); + l = (u16)(d % 10); + l |= (u16)(h << 8); + + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(l & 0x80, F_SF); + CONDITIONAL_SET_FLAG(l == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(l & 0xff), F_PF); + return l; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u8 adc_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u16 adc_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + if (ACCESS_FLAG(F_CF)) + res = 1 + d + s; + else + res = d + s; + + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADC instruction and side effects. +****************************************************************************/ +u32 adc_long(u32 d, u32 s) +{ + register u32 lo; /* all operands in native machine order */ + register u32 hi; + register u32 res; + register u32 cc; + + if (ACCESS_FLAG(F_CF)) { + lo = 1 + (d & 0xFFFF) + (s & 0xFFFF); + res = 1 + d + s; + } + else { + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + } + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u8 add_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x100, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u16 add_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + s; + CONDITIONAL_SET_FLAG(res & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ADD instruction and side effects. +****************************************************************************/ +u32 add_long(u32 d, u32 s) +{ + register u32 lo; /* all operands in native machine order */ + register u32 hi; + register u32 res; + register u32 cc; + + lo = (d & 0xFFFF) + (s & 0xFFFF); + res = d + s; + hi = (lo >> 16) + (d >> 16) + (s >> 16); + + CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (s & d) | ((~res) & (s | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u8 and_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u16 and_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the AND instruction and side effects. +****************************************************************************/ +u32 and_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + /* set the flags */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u8 cmp_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CLEAR_FLAG(F_CF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u16 cmp_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the CMP instruction and side effects. +****************************************************************************/ +u32 cmp_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DAA instruction and side effects. +****************************************************************************/ +u8 daa_byte(u8 d) +{ + u32 res = d; + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + res += 6; + SET_FLAG(F_AF); + } + if (res > 0x9F || ACCESS_FLAG(F_CF)) { + res += 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xFF) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DAS instruction and side effects. +****************************************************************************/ +u8 das_byte(u8 d) +{ + if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { + d -= 6; + SET_FLAG(F_AF); + } + if (d > 0x9F || ACCESS_FLAG(F_CF)) { + d -= 0x60; + SET_FLAG(F_CF); + } + CONDITIONAL_SET_FLAG(d & 0x80, F_SF); + CONDITIONAL_SET_FLAG(d == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(d & 0xff), F_PF); + return d; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u8 dec_byte(u8 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on sub_byte, uses s==1. */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u16 dec_word(u16 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + /* based on the sub_byte routine, with s==1 */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the DEC instruction and side effects. +****************************************************************************/ +u32 dec_long(u32 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - 1; + + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | 1)) | (~d & 1); + /* carry flag unchanged */ + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u8 inc_byte(u8 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = ((1 & d) | (~res)) & (1 | d); + CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u16 inc_word(u16 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the INC instruction and side effects. +****************************************************************************/ +u32 inc_long(u32 d) +{ + register u32 res; /* all operands in native machine order */ + register u32 cc; + + res = d + 1; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the carry chain SEE NOTE AT TOP. */ + cc = (1 & d) | ((~res) & (1 | d)); + CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF); + CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 or_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d | s; + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 or_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d | s; + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 or_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d | s; + + /* set the carry flag to be bit 8 */ + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u8 neg_byte(u8 s) +{ + register u8 res; + register u8 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u8)-s; + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u16 neg_word(u16 s) +{ + register u16 res; + register u16 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u16)-s; + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the OR instruction and side effects. +****************************************************************************/ +u32 neg_long(u32 s) +{ + register u32 res; + register u32 bc; + + CONDITIONAL_SET_FLAG(s != 0, F_CF); + res = (u32)-s; + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain --- modified such that d=0. + substitutiing d=0 into bc= res&(~d|s)|(~d&s); + (the one used for sub) and simplifying, since ~d=0xff..., + ~d|s == 0xffff..., and res&0xfff... == res. Similarly + ~d&s == s. So the simplified result is: */ + bc = res | s; + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u8 not_byte(u8 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u16 not_word(u16 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the NOT instruction and side effects. +****************************************************************************/ +u32 not_long(u32 s) +{ + return ~s; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u8 rcl_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask, cf; + + /* s is the rotate distance. It varies from 0 - 8. */ + /* have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + want to rotate through the carry by "s" bits. We could + loop, but that's inefficient. So the width is 9, + and we split into three parts: + + The new carry flag (was B_n) + the stuff in B_n-1 .. B_0 + the stuff in B_7 .. B_n+1 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the MSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(8-n) + 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 + 3) B_(n-1) <- cf + 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(8-n) */ + cf = (d >> (8 - cnt)) & 0x1; + + /* get the low stuff which rotated + into the range B_7 .. B_cnt */ + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ + /* note that the right hand side done by the mask */ + res = (d << cnt) & 0xff; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (9 - cnt)) & mask; + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(n-1) <- cf */ + res |= 1 << (cnt - 1); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized this expression since it appears to + be causing OF to be misset */ + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), + F_OF); + + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u16 rcl_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask, cf; + + res = d; + if ((cnt = s % 17) != 0) { + cf = (d >> (16 - cnt)) & 0x1; + res = (d << cnt) & 0xffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (17 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), + F_OF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCL instruction and side effects. +****************************************************************************/ +u32 rcl_long(u32 d, u8 s) +{ + register u32 res, cnt, mask, cf; + + res = d; + if ((cnt = s % 33) != 0) { + cf = (d >> (32 - cnt)) & 0x1; + res = (d << cnt) & 0xffffffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (33 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), + F_OF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u8 rcr_byte(u8 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 + + The new rotate is done mod 9, and given this, + for a rotation of n bits (mod 9) the new carry flag is + then located n bits from the LSB. The low part is + then shifted up cnt bits, and the high part is or'd + in. Using CAPS for new values, and lowercase for the + original values, this can be expressed as: + + IF n > 0 + 1) CF <- b_(n-1) + 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 3) B_(8-n) <- cf + 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) + */ + res = d; + if ((cnt = s % 9) != 0) { + /* extract the new CARRY FLAG. */ + /* CF <- b_(n-1) */ + if (cnt == 1) { + cf = d & 0x1; + /* note hackery here. Access_flag(..) evaluates to either + 0 if flag not set + non-zero if flag is set. + doing access_flag(..) != 0 casts that into either + 0..1 in any representation of the flags register + (i.e. packed bit array or unpacked.) + */ + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ + /* note that the right hand side done by the mask + This is effectively done by shifting the + object to the right. The result must be masked, + in case the object came in and was treated + as a negative number. Needed??? */ + + mask = (1 << (8 - cnt)) - 1; + res = (d >> cnt) & mask; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + res |= (d << (9 - cnt)); + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(8-n) <- cf */ + res |= 1 << (8 - cnt); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized... */ + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), + F_OF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u16 rcr_word(u16 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 17) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (16 - cnt)) - 1; + res = (d >> cnt) & mask; + res |= (d << (17 - cnt)); + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (16 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), + F_OF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the RCR instruction and side effects. +****************************************************************************/ +u32 rcr_long(u32 d, u8 s) +{ + u32 res, cnt; + u32 mask, cf, ocf = 0; + + /* rotate right through carry */ + res = d; + if ((cnt = s % 33) != 0) { + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (32 - cnt)) - 1; + res = (d >> cnt) & mask; + if (cnt != 1) + res |= (d << (33 - cnt)); + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (32 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), + F_OF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u8 rol_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask; + + /* rotate left */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + CF B_7 ... B_0 + + The new rotate is done mod 8. + Much simpler than the "rcl" or "rcr" operations. + + IF n > 0 + 1) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) + 2) B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) + */ + res = d; + if ((cnt = s % 8) != 0) { + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ + res = (d << cnt); + + /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ + mask = (1 << cnt) - 1; + res |= (d >> (8 - cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of CF and the most significant bit. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 6) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u16 rol_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (16 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 14) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROL instruction and side effects. +****************************************************************************/ +u32 rol_long(u32 d, u8 s) +{ + register u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (32 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 30) & 0x2)), + F_OF); + } if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u8 ror_byte(u8 d, u8 s) +{ + register unsigned int res, cnt, mask; + + /* rotate right */ + /* + s is the rotate distance. It varies from 0 - 8. + d is the byte object rotated. + + have + + B_7 ... B_0 + + The rotate is done mod 8. + + IF n > 0 + 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) + */ + res = d; + if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ + /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ + res = (d << (8 - cnt)); + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ + mask = (1 << (8 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of the two most significant bits. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u16 ror_word(u16 d, u8 s) +{ + register unsigned int res, cnt, mask; + + res = d; + if ((cnt = s % 16) != 0) { + res = (d << (16 - cnt)); + mask = (1 << (16 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the ROR instruction and side effects. +****************************************************************************/ +u32 ror_long(u32 d, u8 s) +{ + register u32 res, cnt, mask; + + res = d; + if ((cnt = s % 32) != 0) { + res = (d << (32 - cnt)); + mask = (1 << (32 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); + } else if (s != 0) { + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u8 shl_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + + /* last bit shifted out goes into carry flag */ + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (8 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u8) d; + } + + if (cnt == 1) { + /* Needs simplification. */ + CONDITIONAL_SET_FLAG( + (((res & 0x80) == 0x80) ^ + (ACCESS_FLAG(F_CF) != 0)), + /* was (M.x86.R_FLG&F_CF)==F_CF)), */ + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u16 shl_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u16) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG( + (((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), + F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHL instruction and side effects. +****************************************************************************/ +u32 shl_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u8 shr_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 8) { + cnt = s % 8; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = (u8) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u16 shr_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHR instruction and side effects. +****************************************************************************/ +u32 shr_long(u32 d, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u8 sar_byte(u8 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + res = d; + sf = d & 0x80; + cnt = s % 8; + if (cnt > 0 && cnt < 8) { + mask = (1 << (8 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + } else if (cnt >= 8) { + if (sf) { + res = 0xff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u16 sar_word(u16 d, u8 s) +{ + unsigned int cnt, res, cf, mask, sf; + + sf = d & 0x8000; + cnt = s % 16; + res = d; + if (cnt > 0 && cnt < 16) { + mask = (1 << (16 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 16) { + if (sf) { + res = 0xffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SAR instruction and side effects. +****************************************************************************/ +u32 sar_long(u32 d, u8 s) +{ + u32 cnt, res, cf, mask, sf; + + sf = d & 0x80000000; + cnt = s % 32; + res = d; + if (cnt > 0 && cnt < 32) { + mask = (1 << (32 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else if (cnt >= 32) { + if (sf) { + res = 0xffffffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u16 shld_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + res = (d << cnt) | (fill >> (16-cnt)); + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHLD instruction and side effects. +****************************************************************************/ +u32 shld_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + res = (d << cnt) | (fill >> (32-cnt)); + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u16 shrd_word (u16 d, u16 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 16) { + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SHRD instruction and side effects. +****************************************************************************/ +u32 shrd_long (u32 d, u32 fill, u8 s) +{ + unsigned int cnt, res, cf; + + if (s < 32) { + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } + } else { + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u8 sbb_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u16 sbb_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SBB instruction and side effects. +****************************************************************************/ +u32 sbb_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + if (ACCESS_FLAG(F_CF)) + res = d - s - 1; + else + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u8 sub_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG((res & 0xff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u8)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u16 sub_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return (u16)res; +} + +/**************************************************************************** +REMARKS: +Implements the SUB instruction and side effects. +****************************************************************************/ +u32 sub_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + register u32 bc; + + res = d - s; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG((res & 0xffffffff) == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + + /* calculate the borrow chain. See note at top */ + bc = (res & (~d | s)) | (~d & s); + CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF); + CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_byte(u8 d, u8 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_word(u16 d, u16 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the TEST instruction and side effects. +****************************************************************************/ +void test_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d & s; + + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + /* AF == dont care */ + CLEAR_FLAG(F_CF); +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u8 xor_byte(u8 d, u8 s) +{ + register u8 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u16 xor_word(u16 d, u16 s) +{ + register u16 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x8000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the XOR instruction and side effects. +****************************************************************************/ +u32 xor_long(u32 d, u32 s) +{ + register u32 res; /* all operands in native machine order */ + + res = d ^ s; + CLEAR_FLAG(F_OF); + CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF); + CONDITIONAL_SET_FLAG(res == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(res & 0xff), F_PF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + return res; +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_byte(u8 s) +{ + s16 res = (s16)((s8)M.x86.R_AL * (s8)s); + + M.x86.R_AX = res; + if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || + ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_word(u16 s) +{ + s32 res = (s16)M.x86.R_AX * (s16)s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x00) || + ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 res = (s32)d * (s32)s; + + *res_lo = (u32)res; + *res_hi = (u32)(res >> 32); +#else + u32 d_lo,d_hi,d_sign; + u32 s_lo,s_hi,s_sign; + u32 rlo_lo,rlo_hi,rhi_lo; + + if ((d_sign = d & 0x80000000) != 0) + d = -d; + d_lo = d & 0xFFFF; + d_hi = d >> 16; + if ((s_sign = s & 0x80000000) != 0) + s = -s; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = d_lo * s_lo; + rlo_hi = (d_hi * s_lo + d_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = d_hi * s_hi + (rlo_hi >> 16); + *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + *res_hi = rhi_lo; + if (d_sign != s_sign) { + d = ~*res_lo; + s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); + *res_lo = ~*res_lo+1; + *res_hi = ~*res_hi+(s >> 16); + } +#endif +} + +/**************************************************************************** +REMARKS: +Implements the IMUL instruction and side effects. +****************************************************************************/ +void imul_long(u32 s) +{ + imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); + if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00) || + ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_byte(u8 s) +{ + u16 res = (u16)(M.x86.R_AL * s); + + M.x86.R_AX = res; + if (M.x86.R_AH == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_word(u16 s) +{ + u32 res = M.x86.R_AX * s; + + M.x86.R_AX = (u16)res; + M.x86.R_DX = (u16)(res >> 16); + if (M.x86.R_DX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the MUL instruction and side effects. +****************************************************************************/ +void mul_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 res = (u32)M.x86.R_EAX * (u32)s; + + M.x86.R_EAX = (u32)res; + M.x86.R_EDX = (u32)(res >> 32); +#else + u32 a,a_lo,a_hi; + u32 s_lo,s_hi; + u32 rlo_lo,rlo_hi,rhi_lo; + + a = M.x86.R_EAX; + a_lo = a & 0xFFFF; + a_hi = a >> 16; + s_lo = s & 0xFFFF; + s_hi = s >> 16; + rlo_lo = a_lo * s_lo; + rlo_hi = (a_hi * s_lo + a_lo * s_hi) + (rlo_lo >> 16); + rhi_lo = a_hi * s_hi + (rlo_hi >> 16); + M.x86.R_EAX = (rlo_hi << 16) | (rlo_lo & 0xFFFF); + M.x86.R_EDX = rhi_lo; +#endif + + if (M.x86.R_EDX == 0) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_byte(u8 s) +{ + s32 dvd, div, mod; + + dvd = (s16)M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s8)s; + mod = dvd % (s8)s; + if (abs(div) > 0x7f) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (s8) div; + M.x86.R_AH = (s8) mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_word(u16 s) +{ + s32 dvd, div, mod; + + dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s16)s; + mod = dvd % (s16)s; + if (abs(div) > 0x7fff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the IDIV instruction and side effects. +****************************************************************************/ +void idiv_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + s64 dvd, div, mod; + + dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (s32)s; + mod = dvd % (s32)s; + if (abs(div) > 0x7fffffff) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + u32 abs_s = s & 0x7FFFFFFF; + u32 abs_h_dvd = h_dvd & 0x7FFFFFFF; + u32 h_s = abs_s >> 1; + u32 l_s = abs_s << 31; + int counter = 31; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (abs_h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = abs_s << (--counter); + continue; + } else { + abs_h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = abs_s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (abs_h_dvd || (l_dvd > abs_s)) { + x86emu_intr_raise(0); + return; + } + /* sign */ + div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); + mod = l_dvd; + +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_byte(u8 s) +{ + u32 dvd, div, mod; + + dvd = M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u8)s; + mod = dvd % (u8)s; + if (abs(div) > 0xff) { + x86emu_intr_raise(0); + return; + } + M.x86.R_AL = (u8)div; + M.x86.R_AH = (u8)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_word(u16 s) +{ + u32 dvd, div, mod; + + dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u16)s; + mod = dvd % (u16)s; + if (abs(div) > 0xffff) { + x86emu_intr_raise(0); + return; + } + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_SF); + CONDITIONAL_SET_FLAG(div == 0, F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_AX = (u16)div; + M.x86.R_DX = (u16)mod; +} + +/**************************************************************************** +REMARKS: +Implements the DIV instruction and side effects. +****************************************************************************/ +void div_long(u32 s) +{ +#ifdef __HAS_LONG_LONG__ + u64 dvd, div, mod; + + dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; + if (s == 0) { + x86emu_intr_raise(0); + return; + } + div = dvd / (u32)s; + mod = dvd % (u32)s; + if (abs(div) > 0xffffffff) { + x86emu_intr_raise(0); + return; + } +#else + s32 div = 0, mod; + s32 h_dvd = M.x86.R_EDX; + u32 l_dvd = M.x86.R_EAX; + + u32 h_s = s; + u32 l_s = 0; + int counter = 32; + int carry; + + if (s == 0) { + x86emu_intr_raise(0); + return; + } + do { + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = s << (--counter); + continue; + } else { + h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = s << (--counter); + div |= 1; + continue; + } + + } while (counter > -1); + /* overflow */ + if (h_dvd || (l_dvd > s)) { + x86emu_intr_raise(0); + return; + } + mod = l_dvd; +#endif + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_ZF); + CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF); + + M.x86.R_EAX = (u32)div; + M.x86.R_EDX = (u32)mod; +} + +#endif /* __HAVE_INLINE_ASSEMBLER__ */ + +/**************************************************************************** +REMARKS: +Implements the IN string instruction and side effects. +****************************************************************************/ +void ins(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* in until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + switch (size) { + case 1: + while (count--) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inb)(M.x86.R_DX)); + M.x86.R_DI += inc; + } + break; + + case 2: + while (count--) { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inw)(M.x86.R_DX)); + M.x86.R_DI += inc; + } + break; + case 4: + while (count--) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inl)(M.x86.R_DX)); + M.x86.R_DI += inc; + break; + } + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inb)(M.x86.R_DX)); + break; + case 2: + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inw)(M.x86.R_DX)); + break; + case 4: + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, + (*sys_inl)(M.x86.R_DX)); + break; + } + M.x86.R_DI += inc; + } +} + +/**************************************************************************** +REMARKS: +Implements the OUT string instruction and side effects. +****************************************************************************/ +void outs(int size) +{ + int inc = size; + + if (ACCESS_FLAG(F_DF)) { + inc = -size; + } + if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { + /* dont care whether REPE or REPNE */ + /* out until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + switch (size) { + case 1: + while (count--) { + (*sys_outb)(M.x86.R_DX, + fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + } + break; + + case 2: + while (count--) { + (*sys_outw)(M.x86.R_DX, + fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + } + break; + case 4: + while (count--) { + (*sys_outl)(M.x86.R_DX, + fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); + M.x86.R_SI += inc; + break; + } + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + } else { + switch (size) { + case 1: + (*sys_outb)(M.x86.R_DX, + fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI)); + break; + case 2: + (*sys_outw)(M.x86.R_DX, + fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI)); + break; + case 4: + (*sys_outl)(M.x86.R_DX, + fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI)); + break; + } + M.x86.R_SI += inc; + } +} + +/**************************************************************************** +PARAMETERS: +addr - Address to fetch word from + +REMARKS: +Fetches a word from emulator memory using an absolute address. +****************************************************************************/ +u16 mem_access_word(int addr) +{ +DB( if (CHECK_MEM_ACCESS()) + x86emu_check_mem_access(addr);) + return (*sys_rdw)(addr); +} + +/**************************************************************************** +REMARKS: +Pushes a word onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_word(u16 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 2; + (*sys_wrw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pushes a long onto the stack. + +NOTE: Do not inline this, as (*sys_wrX) is already inline! +****************************************************************************/ +void push_long(u32 w) +{ +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + M.x86.R_SP -= 4; + (*sys_wrl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w); +} + +/**************************************************************************** +REMARKS: +Pops a word from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u16 pop_word(void) +{ + register u16 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 2; + return res; +} + +/**************************************************************************** +REMARKS: +Pops a long from the stack. + +NOTE: Do not inline this, as (*sys_rdX) is already inline! +****************************************************************************/ +u32 pop_long(void) +{ + register u32 res; + +DB( if (CHECK_SP_ACCESS()) + x86emu_check_sp_access();) + res = (*sys_rdl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP); + M.x86.R_SP += 4; + return res; +} + +#ifdef __HAVE_INLINE_ASSEMBLER__ + +u16 aaa_word (u16 d) +{ return aaa_word_asm(&M.x86.R_EFLG,d); } + +u16 aas_word (u16 d) +{ return aas_word_asm(&M.x86.R_EFLG,d); } + +u16 aad_word (u16 d) +{ return aad_word_asm(&M.x86.R_EFLG,d); } + +u16 aam_word (u8 d) +{ return aam_word_asm(&M.x86.R_EFLG,d); } + +u8 adc_byte (u8 d, u8 s) +{ return adc_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 adc_word (u16 d, u16 s) +{ return adc_word_asm(&M.x86.R_EFLG,d,s); } + +u32 adc_long (u32 d, u32 s) +{ return adc_long_asm(&M.x86.R_EFLG,d,s); } + +u8 add_byte (u8 d, u8 s) +{ return add_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 add_word (u16 d, u16 s) +{ return add_word_asm(&M.x86.R_EFLG,d,s); } + +u32 add_long (u32 d, u32 s) +{ return add_long_asm(&M.x86.R_EFLG,d,s); } + +u8 and_byte (u8 d, u8 s) +{ return and_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 and_word (u16 d, u16 s) +{ return and_word_asm(&M.x86.R_EFLG,d,s); } + +u32 and_long (u32 d, u32 s) +{ return and_long_asm(&M.x86.R_EFLG,d,s); } + +u8 cmp_byte (u8 d, u8 s) +{ return cmp_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 cmp_word (u16 d, u16 s) +{ return cmp_word_asm(&M.x86.R_EFLG,d,s); } + +u32 cmp_long (u32 d, u32 s) +{ return cmp_long_asm(&M.x86.R_EFLG,d,s); } + +u8 daa_byte (u8 d) +{ return daa_byte_asm(&M.x86.R_EFLG,d); } + +u8 das_byte (u8 d) +{ return das_byte_asm(&M.x86.R_EFLG,d); } + +u8 dec_byte (u8 d) +{ return dec_byte_asm(&M.x86.R_EFLG,d); } + +u16 dec_word (u16 d) +{ return dec_word_asm(&M.x86.R_EFLG,d); } + +u32 dec_long (u32 d) +{ return dec_long_asm(&M.x86.R_EFLG,d); } + +u8 inc_byte (u8 d) +{ return inc_byte_asm(&M.x86.R_EFLG,d); } + +u16 inc_word (u16 d) +{ return inc_word_asm(&M.x86.R_EFLG,d); } + +u32 inc_long (u32 d) +{ return inc_long_asm(&M.x86.R_EFLG,d); } + +u8 or_byte (u8 d, u8 s) +{ return or_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 or_word (u16 d, u16 s) +{ return or_word_asm(&M.x86.R_EFLG,d,s); } + +u32 or_long (u32 d, u32 s) +{ return or_long_asm(&M.x86.R_EFLG,d,s); } + +u8 neg_byte (u8 s) +{ return neg_byte_asm(&M.x86.R_EFLG,s); } + +u16 neg_word (u16 s) +{ return neg_word_asm(&M.x86.R_EFLG,s); } + +u32 neg_long (u32 s) +{ return neg_long_asm(&M.x86.R_EFLG,s); } + +u8 not_byte (u8 s) +{ return not_byte_asm(&M.x86.R_EFLG,s); } + +u16 not_word (u16 s) +{ return not_word_asm(&M.x86.R_EFLG,s); } + +u32 not_long (u32 s) +{ return not_long_asm(&M.x86.R_EFLG,s); } + +u8 rcl_byte (u8 d, u8 s) +{ return rcl_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 rcl_word (u16 d, u8 s) +{ return rcl_word_asm(&M.x86.R_EFLG,d,s); } + +u32 rcl_long (u32 d, u8 s) +{ return rcl_long_asm(&M.x86.R_EFLG,d,s); } + +u8 rcr_byte (u8 d, u8 s) +{ return rcr_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 rcr_word (u16 d, u8 s) +{ return rcr_word_asm(&M.x86.R_EFLG,d,s); } + +u32 rcr_long (u32 d, u8 s) +{ return rcr_long_asm(&M.x86.R_EFLG,d,s); } + +u8 rol_byte (u8 d, u8 s) +{ return rol_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 rol_word (u16 d, u8 s) +{ return rol_word_asm(&M.x86.R_EFLG,d,s); } + +u32 rol_long (u32 d, u8 s) +{ return rol_long_asm(&M.x86.R_EFLG,d,s); } + +u8 ror_byte (u8 d, u8 s) +{ return ror_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 ror_word (u16 d, u8 s) +{ return ror_word_asm(&M.x86.R_EFLG,d,s); } + +u32 ror_long (u32 d, u8 s) +{ return ror_long_asm(&M.x86.R_EFLG,d,s); } + +u8 shl_byte (u8 d, u8 s) +{ return shl_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 shl_word (u16 d, u8 s) +{ return shl_word_asm(&M.x86.R_EFLG,d,s); } + +u32 shl_long (u32 d, u8 s) +{ return shl_long_asm(&M.x86.R_EFLG,d,s); } + +u8 shr_byte (u8 d, u8 s) +{ return shr_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 shr_word (u16 d, u8 s) +{ return shr_word_asm(&M.x86.R_EFLG,d,s); } + +u32 shr_long (u32 d, u8 s) +{ return shr_long_asm(&M.x86.R_EFLG,d,s); } + +u8 sar_byte (u8 d, u8 s) +{ return sar_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 sar_word (u16 d, u8 s) +{ return sar_word_asm(&M.x86.R_EFLG,d,s); } + +u32 sar_long (u32 d, u8 s) +{ return sar_long_asm(&M.x86.R_EFLG,d,s); } + +u16 shld_word (u16 d, u16 fill, u8 s) +{ return shld_word_asm(&M.x86.R_EFLG,d,fill,s); } + +u32 shld_long (u32 d, u32 fill, u8 s) +{ return shld_long_asm(&M.x86.R_EFLG,d,fill,s); } + +u16 shrd_word (u16 d, u16 fill, u8 s) +{ return shrd_word_asm(&M.x86.R_EFLG,d,fill,s); } + +u32 shrd_long (u32 d, u32 fill, u8 s) +{ return shrd_long_asm(&M.x86.R_EFLG,d,fill,s); } + +u8 sbb_byte (u8 d, u8 s) +{ return sbb_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 sbb_word (u16 d, u16 s) +{ return sbb_word_asm(&M.x86.R_EFLG,d,s); } + +u32 sbb_long (u32 d, u32 s) +{ return sbb_long_asm(&M.x86.R_EFLG,d,s); } + +u8 sub_byte (u8 d, u8 s) +{ return sub_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 sub_word (u16 d, u16 s) +{ return sub_word_asm(&M.x86.R_EFLG,d,s); } + +u32 sub_long (u32 d, u32 s) +{ return sub_long_asm(&M.x86.R_EFLG,d,s); } + +void test_byte (u8 d, u8 s) +{ test_byte_asm(&M.x86.R_EFLG,d,s); } + +void test_word (u16 d, u16 s) +{ test_word_asm(&M.x86.R_EFLG,d,s); } + +void test_long (u32 d, u32 s) +{ test_long_asm(&M.x86.R_EFLG,d,s); } + +u8 xor_byte (u8 d, u8 s) +{ return xor_byte_asm(&M.x86.R_EFLG,d,s); } + +u16 xor_word (u16 d, u16 s) +{ return xor_word_asm(&M.x86.R_EFLG,d,s); } + +u32 xor_long (u32 d, u32 s) +{ return xor_long_asm(&M.x86.R_EFLG,d,s); } + +void imul_byte (u8 s) +{ imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s); } + +void imul_word (u16 s) +{ imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s); } + +void imul_long (u32 s) +{ imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); } + +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) +{ imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s); } + +void mul_byte (u8 s) +{ mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s); } + +void mul_word (u16 s) +{ mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s); } + +void mul_long (u32 s) +{ mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); } + +void idiv_byte (u8 s) +{ idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s); } + +void idiv_word (u16 s) +{ idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s); } + +void idiv_long (u32 s) +{ idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); } + +void div_byte (u8 s) +{ div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s); } + +void div_word (u16 s) +{ div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s); } + +void div_long (u32 s) +{ div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s); } + +#endif diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/sys.c b/board/MAI/bios_emulator/scitech/src/x86emu/sys.c new file mode 100644 index 000000000..afe58f864 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/sys.c @@ -0,0 +1,658 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: This file includes subroutines which are related to +* programmed I/O and memory access. Included in this module +* are default functions with limited usefulness. For real +* uses these functions will most likely be overriden by the +* user library. +* +****************************************************************************/ + +#include "x86emu.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/prim_ops.h" +#include + +/*------------------------- Global Variables ------------------------------*/ + +X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */ +X86EMU_intrFuncs _X86EMU_intrTab[256]; + +/*----------------------------- Implementation ----------------------------*/ +#ifdef __alpha__ +/* to cope with broken egcs-1.1.2 :-(((( */ + +/* + * inline functions to do unaligned accesses + * from linux/include/asm-alpha/unaligned.h + */ + +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ + +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; +#endif + +static __inline__ unsigned long ldq_u(unsigned long * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extql %0,%2,%0\n\t" + "extqh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(7+(char *) r11))); + return r1 | r2; +#endif +} + +static __inline__ unsigned long ldl_u(unsigned int * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extll %0,%2,%0\n\t" + "extlh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(3+(char *) r11))); + return r1 | r2; +#endif +} + +static __inline__ unsigned long ldw_u(unsigned short * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +#else + unsigned long r1,r2; + __asm__("ldq_u %0,%3\n\t" + "ldq_u %1,%4\n\t" + "extwl %0,%2,%0\n\t" + "extwh %1,%2,%1" + :"=&r" (r1), "=&r" (r2) + :"r" (r11), + "m" (*r11), + "m" (*(const unsigned long *)(1+(char *) r11))); + return r1 | r2; +#endif +} + +/* + * Elemental unaligned stores + */ + +static __inline__ void stq_u(unsigned long r5, unsigned long * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "insqh %6,%7,%5\n\t" + "insql %6,%7,%4\n\t" + "mskqh %3,%7,%3\n\t" + "mskql %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(7+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +static __inline__ void stl_u(unsigned long r5, unsigned int * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inslh %6,%7,%5\n\t" + "insll %6,%7,%4\n\t" + "msklh %3,%7,%3\n\t" + "mskll %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(3+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +static __inline__ void stw_u(unsigned long r5, unsigned short * r11) +{ +#if __GNUC__ > 2 || __GNUC_MINOR__ >= 91 + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +#else + unsigned long r1,r2,r3,r4; + + __asm__("ldq_u %3,%1\n\t" + "ldq_u %2,%0\n\t" + "inswh %6,%7,%5\n\t" + "inswl %6,%7,%4\n\t" + "mskwh %3,%7,%3\n\t" + "mskwl %2,%7,%2\n\t" + "bis %3,%5,%3\n\t" + "bis %2,%4,%2\n\t" + "stq_u %3,%1\n\t" + "stq_u %2,%0" + :"=m" (*r11), + "=m" (*(unsigned long *)(1+(char *) r11)), + "=&r" (r1), "=&r" (r2), "=&r" (r3), "=&r" (r4) + :"r" (r5), "r" (r11)); +#endif +} + +#elif defined (__ia64__) +/* + * EGCS 1.1 knows about arbitrary unaligned loads. Define some + * packed structures to talk about such things with. + */ +struct __una_u64 { unsigned long x __attribute__((packed)); }; +struct __una_u32 { unsigned int x __attribute__((packed)); }; +struct __una_u16 { unsigned short x __attribute__((packed)); }; + +static __inline__ unsigned long +__uldq (const unsigned long * r11) +{ + const struct __una_u64 *ptr = (const struct __una_u64 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +uldl (const unsigned int * r11) +{ + const struct __una_u32 *ptr = (const struct __una_u32 *) r11; + return ptr->x; +} + +static __inline__ unsigned long +uldw (const unsigned short * r11) +{ + const struct __una_u16 *ptr = (const struct __una_u16 *) r11; + return ptr->x; +} + +static __inline__ void +ustq (unsigned long r5, unsigned long * r11) +{ + struct __una_u64 *ptr = (struct __una_u64 *) r11; + ptr->x = r5; +} + +static __inline__ void +ustl (unsigned long r5, unsigned int * r11) +{ + struct __una_u32 *ptr = (struct __una_u32 *) r11; + ptr->x = r5; +} + +static __inline__ void +ustw (unsigned long r5, unsigned short * r11) +{ + struct __una_u16 *ptr = (struct __una_u16 *) r11; + ptr->x = r5; +} + +#endif + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Byte value read from emulator memory. + +REMARKS: +Reads a byte value from the emulator memory. +****************************************************************************/ +u8 X86API rdb( + u32 addr) +{ + u8 val; + + if (addr > M.mem_size - 1) { + DB(printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + val = *(u8*)(M.mem_base + addr); +DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 1 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Word value read from emulator memory. + +REMARKS: +Reads a word value from the emulator memory. +****************************************************************************/ +u16 X86API rdw( + u32 addr) +{ + u16 val = 0; + + if (addr > M.mem_size - 2) { + DB(printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + val = (*(u8*)(M.mem_base + addr) | + (*(u8*)(M.mem_base + addr + 1) << 8)); + } + else +#endif +#ifdef __alpha__ + val = ldw_u((u16*)(M.mem_base + addr)); +#elif defined (__ia64__) + val = uldw((u16*)(M.mem_base + addr)); +#else + val = *(u16*)(M.mem_base + addr); +#endif + DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 2 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read + +RETURNS: +Long value read from emulator memory. +REMARKS: +Reads a long value from the emulator memory. +****************************************************************************/ +u32 X86API rdl( + u32 addr) +{ + u32 val = 0; + + if (addr > M.mem_size - 4) { + DB(printk("mem_read: address %#lx out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x3) { + val = (*(u8*)(M.mem_base + addr + 0) | + (*(u8*)(M.mem_base + addr + 1) << 8) | + (*(u8*)(M.mem_base + addr + 2) << 16) | + (*(u8*)(M.mem_base + addr + 3) << 24)); + } + else +#endif +#ifdef __alpha__ + val = ldl_u((u32*)(M.mem_base + addr)); +#elif defined (__ia64__) + val = uldl((u32*)(M.mem_base + addr)); +#else + val = *(u32*)(M.mem_base + addr); +#endif +DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 4 -> %#x\n", addr, val);) + return val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a byte value to emulator memory. +****************************************************************************/ +void X86API wrb( + u32 addr, + u8 val) +{ +DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 1 <- %#x\n", addr, val);) + if (addr > M.mem_size - 1) { + DB(printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } + *(u8*)(M.mem_base + addr) = val; +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a word value to emulator memory. +****************************************************************************/ +void X86API wrw( + u32 addr, + u16 val) +{ +DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 2 <- %#x\n", addr, val);) + if (addr > M.mem_size - 2) { + DB(printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + } + else +#endif +#ifdef __alpha__ + stw_u(val,(u16*)(M.mem_base + addr)); +#elif defined (__ia64__) + ustw(val,(u16*)(M.mem_base + addr)); +#else + *(u16*)(M.mem_base + addr) = val; +#endif +} + +/**************************************************************************** +PARAMETERS: +addr - Emulator memory address to read +val - Value to store + +REMARKS: +Writes a long value to emulator memory. +****************************************************************************/ +void X86API wrl( + u32 addr, + u32 val) +{ +DB( if (DEBUG_MEM_TRACE()) + printk("%#08x 4 <- %#x\n", addr, val);) + if (addr > M.mem_size - 4) { + DB(printk("mem_write: address %#lx out of range!\n", addr);) + HALT_SYS(); + } +#ifdef __BIG_ENDIAN__ + if (addr & 0x1) { + *(u8*)(M.mem_base + addr + 0) = (val >> 0) & 0xff; + *(u8*)(M.mem_base + addr + 1) = (val >> 8) & 0xff; + *(u8*)(M.mem_base + addr + 2) = (val >> 16) & 0xff; + *(u8*)(M.mem_base + addr + 3) = (val >> 24) & 0xff; + } + else +#endif +#ifdef __alpha__ + stl_u(val,(u32*)(M.mem_base + addr)); +#elif defined (__ia64__) + ustl(val,(u32*)(M.mem_base + addr)); +#else + *(u32*)(M.mem_base + addr) = val; +#endif +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO byte read function. Doesn't perform real inb. +****************************************************************************/ +static u8 X86API p_inb( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + printk("inb %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO word read function. Doesn't perform real inw. +****************************************************************************/ +static u16 X86API p_inw( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + printk("inw %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to read +RETURN: +0 +REMARKS: +Default PIO long read function. Doesn't perform real inl. +****************************************************************************/ +static u32 X86API p_inl( + X86EMU_pioAddr addr) +{ +DB( if (DEBUG_IO_TRACE()) + printk("inl %#04x \n", addr);) + return 0; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO byte write function. Doesn't perform real outb. +****************************************************************************/ +static void X86API p_outb( + X86EMU_pioAddr addr, + u8 val) +{ +DB( if (DEBUG_IO_TRACE()) + printk("outb %#02x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO word write function. Doesn't perform real outw. +****************************************************************************/ +static void X86API p_outw( + X86EMU_pioAddr addr, + u16 val) +{ +DB( if (DEBUG_IO_TRACE()) + printk("outw %#04x -> %#04x \n", val, addr);) + return; +} + +/**************************************************************************** +PARAMETERS: +addr - PIO address to write +val - Value to store +REMARKS: +Default PIO ;ong write function. Doesn't perform real outl. +****************************************************************************/ +static void X86API p_outl( + X86EMU_pioAddr addr, + u32 val) +{ +DB( if (DEBUG_IO_TRACE()) + printk("outl %#08x -> %#04x \n", val, addr);) + return; +} + +/*------------------------- Global Variables ------------------------------*/ + +u8 (X86APIP sys_rdb)(u32 addr) = rdb; +u16 (X86APIP sys_rdw)(u32 addr) = rdw; +u32 (X86APIP sys_rdl)(u32 addr) = rdl; +void (X86APIP sys_wrb)(u32 addr,u8 val) = wrb; +void (X86APIP sys_wrw)(u32 addr,u16 val) = wrw; +void (X86APIP sys_wrl)(u32 addr,u32 val) = wrl; +u8 (X86APIP sys_inb)(X86EMU_pioAddr addr) = p_inb; +u16 (X86APIP sys_inw)(X86EMU_pioAddr addr) = p_inw; +u32 (X86APIP sys_inl)(X86EMU_pioAddr addr) = p_inl; +void (X86APIP sys_outb)(X86EMU_pioAddr addr, u8 val) = p_outb; +void (X86APIP sys_outw)(X86EMU_pioAddr addr, u16 val) = p_outw; +void (X86APIP sys_outl)(X86EMU_pioAddr addr, u32 val) = p_outl; + +/*----------------------------- Setup -------------------------------------*/ + +/**************************************************************************** +PARAMETERS: +funcs - New memory function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +memory space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupMemFuncs( + X86EMU_memFuncs *funcs) +{ + sys_rdb = funcs->rdb; + sys_rdw = funcs->rdw; + sys_rdl = funcs->rdl; + sys_wrb = funcs->wrb; + sys_wrw = funcs->wrw; + sys_wrl = funcs->wrl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New programmed I/O function pointers to make active + +REMARKS: +This function is used to set the pointers to functions which access +I/O space, allowing the user application to override these functions +and hook them out as necessary for their application. +****************************************************************************/ +void X86EMU_setupPioFuncs( + X86EMU_pioFuncs *funcs) +{ + sys_inb = funcs->inb; + sys_inw = funcs->inw; + sys_inl = funcs->inl; + sys_outb = funcs->outb; + sys_outw = funcs->outw; + sys_outl = funcs->outl; +} + +/**************************************************************************** +PARAMETERS: +funcs - New interrupt vector table to make active + +REMARKS: +This function is used to set the pointers to functions which handle +interrupt processing in the emulator, allowing the user application to +hook interrupts as necessary for their application. Any interrupts that +are not hooked by the user application, and reflected and handled internally +in the emulator via the interrupt vector table. This allows the application +to get control when the code being emulated executes specific software +interrupts. +****************************************************************************/ +void X86EMU_setupIntrFuncs( + X86EMU_intrFuncs funcs[]) +{ + int i; + + for (i=0; i < 256; i++) + _X86EMU_intrTab[i] = NULL; + if (funcs) { + for (i = 0; i < 256; i++) + _X86EMU_intrTab[i] = funcs[i]; + } +} + +/**************************************************************************** +PARAMETERS: +int - New software interrupt to prepare for + +REMARKS: +This function is used to set up the emulator state to exceute a software +interrupt. This can be used by the user application code to allow an +interrupt to be hooked, examined and then reflected back to the emulator +so that the code in the emulator will continue processing the software +interrupt as per normal. This essentially allows system code to actively +hook and handle certain software interrupts as necessary. +****************************************************************************/ +void X86EMU_prepareForInt( + int num) +{ + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(num * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(num * 4); + M.x86.intr = 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/validate.c b/board/MAI/bios_emulator/scitech/src/x86emu/validate.c new file mode 100644 index 000000000..c951301f9 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/validate.c @@ -0,0 +1,765 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: Watcom C 10.6 or later +* Environment: 32-bit DOS +* Developer: Kendall Bennett +* +* Description: Program to validate the x86 emulator library for +* correctness. We run the emulator primitive operations +* functions against the real x86 CPU, and compare the result +* and flags to ensure correctness. +* +* We use inline assembler to compile and build this program. +* +****************************************************************************/ + +#include +#include +#include +#include +#include "x86emu.h" +#include "x86emu/prim_asm.h" + +/*-------------------------- Implementation -------------------------------*/ + +#define true 1 +#define false 0 + +#define ALL_FLAGS (F_CF | F_PF | F_AF | F_ZF | F_SF | F_OF) + +#define VAL_START_BINARY(parm_type,res_type,dmax,smax,dincr,sincr) \ +{ \ + parm_type d,s; \ + res_type r,r_asm; \ + ulong flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < dmax; d += dincr) { \ + for (s = 0; s < smax; s += sincr) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { + +#define VAL_TEST_BINARY(name) \ + r_asm = name##_asm(&flags,d,s); \ + r = name(d,s); \ + if (r != r_asm || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { + +#define VAL_TEST_BINARY_VOID(name) \ + name##_asm(&flags,d,s); \ + name(d,s); \ + r = r_asm = 0; \ + if (M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { + +#define VAL_FAIL_BYTE_BYTE_BINARY(name) \ + if (failed) \ + printk("fail\n"); \ + printk("0x%02X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ + r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%02X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_FAIL_WORD_WORD_BINARY(name) \ + if (failed) \ + printk("fail\n"); \ + printk("0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ + r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_FAIL_LONG_LONG_BINARY(name) \ + if (failed) \ + printk("fail\n"); \ + printk("0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ + r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_END_BINARY() \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_BYTE_BYTE_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u8,u8,0xFF,0xFF,1,1) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_BYTE_BYTE_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_WORD_WORD_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u16,u16,0xFF00,0xFF00,0x100,0x100) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_WORD_WORD_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_LONG_LONG_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_LONG_LONG_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_VOID_BYTE_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u8,u8,0xFF,0xFF,1,1) \ + VAL_TEST_BINARY_VOID(name) \ + VAL_FAIL_BYTE_BYTE_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_VOID_WORD_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u16,u16,0xFF00,0xFF00,0x100,0x100) \ + VAL_TEST_BINARY_VOID(name) \ + VAL_FAIL_WORD_WORD_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_VOID_LONG_BINARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000) \ + VAL_TEST_BINARY_VOID(name) \ + VAL_FAIL_LONG_LONG_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_BYTE_ROTATE(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u8,u8,0xFF,8,1,1) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_BYTE_BYTE_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_WORD_ROTATE(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u16,u16,0xFF00,16,0x100,1) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_WORD_WORD_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_LONG_ROTATE(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_BINARY(u32,u32,0xFF000000,32,0x1000000,1) \ + VAL_TEST_BINARY(name) \ + VAL_FAIL_LONG_LONG_BINARY(name) \ + VAL_END_BINARY() + +#define VAL_START_TERNARY(parm_type,res_type,dmax,smax,dincr,sincr,maxshift)\ +{ \ + parm_type d,s; \ + res_type r,r_asm; \ + u8 shift; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < dmax; d += dincr) { \ + for (s = 0; s < smax; s += sincr) { \ + for (shift = 0; shift < maxshift; shift += 1) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { + +#define VAL_TEST_TERNARY(name) \ + r_asm = name##_asm(&flags,d,s,shift); \ + r = name(d,s,shift); \ + if (r != r_asm || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { + +#define VAL_FAIL_WORD_WORD_TERNARY(name) \ + if (failed) \ + printk("fail\n"); \ + printk("0x%04X = %-15s(0x%04X,0x%04X,%d), flags = %s -> %s\n", \ + r, #name, d, s, shift, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X = %-15s(0x%04X,0x%04X,%d), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, shift, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_FAIL_LONG_LONG_TERNARY(name) \ + if (failed) \ + printk("fail\n"); \ + printk("0x%08X = %-15s(0x%08X,0x%08X,%d), flags = %s -> %s\n", \ + r, #name, d, s, shift, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%08X = %-15s(0x%08X,0x%08X,%d), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, shift, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_END_TERNARY() \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_WORD_ROTATE_DBL(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_TERNARY(u16,u16,0xFF00,0xFF00,0x100,0x100,16) \ + VAL_TEST_TERNARY(name) \ + VAL_FAIL_WORD_WORD_TERNARY(name) \ + VAL_END_TERNARY() + +#define VAL_LONG_ROTATE_DBL(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_TERNARY(u32,u32,0xFF000000,0xFF000000,0x1000000,0x1000000,32) \ + VAL_TEST_TERNARY(name) \ + VAL_FAIL_LONG_LONG_TERNARY(name) \ + VAL_END_TERNARY() + +#define VAL_START_UNARY(parm_type,max,incr) \ +{ \ + parm_type d,r,r_asm; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < max; d += incr) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { + +#define VAL_TEST_UNARY(name) \ + r_asm = name##_asm(&flags,d); \ + r = name(d); \ + if (r != r_asm || M.x86.R_EFLG != flags) { \ + failed = true; + +#define VAL_FAIL_BYTE_UNARY(name) \ + printk("fail\n"); \ + printk("0x%02X = %-15s(0x%02X), flags = %s -> %s\n", \ + r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%02X = %-15s(0x%02X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_FAIL_WORD_UNARY(name) \ + printk("fail\n"); \ + printk("0x%04X = %-15s(0x%04X), flags = %s -> %s\n", \ + r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X = %-15s(0x%04X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_FAIL_LONG_UNARY(name) \ + printk("fail\n"); \ + printk("0x%08X = %-15s(0x%08X), flags = %s -> %s\n", \ + r, #name, d, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%08X = %-15s(0x%08X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, print_flags(buf1,inflags), print_flags(buf2,flags)); + +#define VAL_END_UNARY() \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | ALL_FLAGS; \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_BYTE_UNARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_UNARY(u8,0xFF,0x1) \ + VAL_TEST_UNARY(name) \ + VAL_FAIL_BYTE_UNARY(name) \ + VAL_END_UNARY() + +#define VAL_WORD_UNARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_UNARY(u16,0xFF00,0x100) \ + VAL_TEST_UNARY(name) \ + VAL_FAIL_WORD_UNARY(name) \ + VAL_END_UNARY() + +#define VAL_WORD_BYTE_UNARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_UNARY(u16,0xFF,0x1) \ + VAL_TEST_UNARY(name) \ + VAL_FAIL_WORD_UNARY(name) \ + VAL_END_UNARY() + +#define VAL_LONG_UNARY(name) \ + printk("Validating %s ... ", #name); \ + VAL_START_UNARY(u32,0xFF000000,0x1000000) \ + VAL_TEST_UNARY(name) \ + VAL_FAIL_LONG_UNARY(name) \ + VAL_END_UNARY() + +#define VAL_BYTE_MUL(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u8 d,s; \ + u16 r,r_asm; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF; d += 1) { \ + for (s = 0; s < 0xFF; s += 1) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + name##_asm(&flags,&r_asm,d,s); \ + M.x86.R_AL = d; \ + name(s); \ + r = M.x86.R_AX; \ + if (r != r_asm || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%04X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ + r, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X = %-15s(0x%02X,0x%02X), flags = %s -> %s\n", \ + r_asm, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_WORD_MUL(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u16 d,s; \ + u16 r_lo,r_asm_lo; \ + u16 r_hi,r_asm_hi; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF00; d += 0x100) { \ + for (s = 0; s < 0xFF00; s += 0x100) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + name##_asm(&flags,&r_asm_lo,&r_asm_hi,d,s); \ + M.x86.R_AX = d; \ + name(s); \ + r_lo = M.x86.R_AX; \ + r_hi = M.x86.R_DX; \ + if (r_lo != r_asm_lo || r_hi != r_asm_hi || M.x86.R_EFLG != flags)\ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%04X:0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ + r_hi,r_lo, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X:0x%04X = %-15s(0x%04X,0x%04X), flags = %s -> %s\n", \ + r_asm_hi,r_asm_lo, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_LONG_MUL(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u32 d,s; \ + u32 r_lo,r_asm_lo; \ + u32 r_hi,r_asm_hi; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF000000; d += 0x1000000) { \ + for (s = 0; s < 0xFF000000; s += 0x1000000) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + name##_asm(&flags,&r_asm_lo,&r_asm_hi,d,s); \ + M.x86.R_EAX = d; \ + name(s); \ + r_lo = M.x86.R_EAX; \ + r_hi = M.x86.R_EDX; \ + if (r_lo != r_asm_lo || r_hi != r_asm_hi || M.x86.R_EFLG != flags)\ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%08X:0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ + r_hi,r_lo, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%08X:0x%08X = %-15s(0x%08X,0x%08X), flags = %s -> %s\n", \ + r_asm_hi,r_asm_lo, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_BYTE_DIV(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u16 d,s; \ + u8 r_quot,r_rem,r_asm_quot,r_asm_rem; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF00; d += 0x100) { \ + for (s = 1; s < 0xFF; s += 1) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + M.x86.intr = 0; \ + M.x86.R_AX = d; \ + name(s); \ + r_quot = M.x86.R_AL; \ + r_rem = M.x86.R_AH; \ + if (M.x86.intr & INTR_SYNCH) \ + continue; \ + name##_asm(&flags,&r_asm_quot,&r_asm_rem,d,s); \ + if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%02X:0x%02X = %-15s(0x%04X,0x%02X), flags = %s -> %s\n", \ + r_quot, r_rem, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%02X:0x%02X = %-15s(0x%04X,0x%02X), flags = %s -> %s\n", \ + r_asm_quot, r_asm_rem, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_WORD_DIV(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u32 d,s; \ + u16 r_quot,r_rem,r_asm_quot,r_asm_rem; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF000000; d += 0x1000000) { \ + for (s = 0x100; s < 0xFF00; s += 0x100) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + M.x86.intr = 0; \ + M.x86.R_AX = d & 0xFFFF; \ + M.x86.R_DX = d >> 16; \ + name(s); \ + r_quot = M.x86.R_AX; \ + r_rem = M.x86.R_DX; \ + if (M.x86.intr & INTR_SYNCH) \ + continue; \ + name##_asm(&flags,&r_asm_quot,&r_asm_rem,d & 0xFFFF,d >> 16,s);\ + if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%04X:0x%04X = %-15s(0x%08X,0x%04X), flags = %s -> %s\n", \ + r_quot, r_rem, #name, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%04X:0x%04X = %-15s(0x%08X,0x%04X), flags = %s -> %s\n", \ + r_asm_quot, r_asm_rem, #name"_asm", d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +#define VAL_LONG_DIV(name) \ + printk("Validating %s ... ", #name); \ +{ \ + u32 d,s; \ + u32 r_quot,r_rem,r_asm_quot,r_asm_rem; \ + u32 flags,inflags; \ + int f,failed = false; \ + char buf1[80],buf2[80]; \ + for (d = 0; d < 0xFF000000; d += 0x1000000) { \ + for (s = 0x100; s < 0xFF00; s += 0x100) { \ + M.x86.R_EFLG = inflags = flags = def_flags; \ + for (f = 0; f < 2; f++) { \ + M.x86.intr = 0; \ + M.x86.R_EAX = d; \ + M.x86.R_EDX = 0; \ + name(s); \ + r_quot = M.x86.R_EAX; \ + r_rem = M.x86.R_EDX; \ + if (M.x86.intr & INTR_SYNCH) \ + continue; \ + name##_asm(&flags,&r_asm_quot,&r_asm_rem,d,0,s); \ + if (r_quot != r_asm_quot || r_rem != r_asm_rem || M.x86.R_EFLG != flags) \ + failed = true; \ + if (failed || trace) { \ + if (failed) \ + printk("fail\n"); \ + printk("0x%08X:0x%08X = %-15s(0x%08X:0x%08X,0x%08X), flags = %s -> %s\n", \ + r_quot, r_rem, #name, 0, d, s, print_flags(buf1,inflags), print_flags(buf2,M.x86.R_EFLG)); \ + printk("0x%08X:0x%08X = %-15s(0x%08X:0x%08X,0x%08X), flags = %s -> %s\n", \ + r_asm_quot, r_asm_rem, #name"_asm", 0, d, s, print_flags(buf1,inflags), print_flags(buf2,flags)); \ + } \ + M.x86.R_EFLG = inflags = flags = def_flags | (ALL_FLAGS & ~F_OF); \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (failed) \ + break; \ + } \ + if (!failed) \ + printk("passed\n"); \ +} + +void printk(const char *fmt, ...) +{ + va_list argptr; + va_start(argptr, fmt); + vfprintf(stdout, fmt, argptr); + fflush(stdout); + va_end(argptr); +} + +char * print_flags(char *buf,ulong flags) +{ + char *separator = ""; + + buf[0] = 0; + if (flags & F_CF) { + strcat(buf,separator); + strcat(buf,"CF"); + separator = ","; + } + if (flags & F_PF) { + strcat(buf,separator); + strcat(buf,"PF"); + separator = ","; + } + if (flags & F_AF) { + strcat(buf,separator); + strcat(buf,"AF"); + separator = ","; + } + if (flags & F_ZF) { + strcat(buf,separator); + strcat(buf,"ZF"); + separator = ","; + } + if (flags & F_SF) { + strcat(buf,separator); + strcat(buf,"SF"); + separator = ","; + } + if (flags & F_OF) { + strcat(buf,separator); + strcat(buf,"OF"); + separator = ","; + } + if (separator[0] == 0) + strcpy(buf,"None"); + return buf; +} + +int main(int argc) +{ + ulong def_flags; + int trace = false; + + if (argc > 1) + trace = true; + memset(&M, 0, sizeof(M)); + def_flags = get_flags_asm() & ~ALL_FLAGS; + + VAL_WORD_UNARY(aaa_word); + VAL_WORD_UNARY(aas_word); + + VAL_WORD_UNARY(aad_word); + VAL_WORD_UNARY(aam_word); + + VAL_BYTE_BYTE_BINARY(adc_byte); + VAL_WORD_WORD_BINARY(adc_word); + VAL_LONG_LONG_BINARY(adc_long); + + VAL_BYTE_BYTE_BINARY(add_byte); + VAL_WORD_WORD_BINARY(add_word); + VAL_LONG_LONG_BINARY(add_long); + + VAL_BYTE_BYTE_BINARY(and_byte); + VAL_WORD_WORD_BINARY(and_word); + VAL_LONG_LONG_BINARY(and_long); + + VAL_BYTE_BYTE_BINARY(cmp_byte); + VAL_WORD_WORD_BINARY(cmp_word); + VAL_LONG_LONG_BINARY(cmp_long); + + VAL_BYTE_UNARY(daa_byte); + VAL_BYTE_UNARY(das_byte); /* Fails for 0x9A (out of range anyway) */ + + VAL_BYTE_UNARY(dec_byte); + VAL_WORD_UNARY(dec_word); + VAL_LONG_UNARY(dec_long); + + VAL_BYTE_UNARY(inc_byte); + VAL_WORD_UNARY(inc_word); + VAL_LONG_UNARY(inc_long); + + VAL_BYTE_BYTE_BINARY(or_byte); + VAL_WORD_WORD_BINARY(or_word); + VAL_LONG_LONG_BINARY(or_long); + + VAL_BYTE_UNARY(neg_byte); + VAL_WORD_UNARY(neg_word); + VAL_LONG_UNARY(neg_long); + + VAL_BYTE_UNARY(not_byte); + VAL_WORD_UNARY(not_word); + VAL_LONG_UNARY(not_long); + + VAL_BYTE_ROTATE(rcl_byte); + VAL_WORD_ROTATE(rcl_word); + VAL_LONG_ROTATE(rcl_long); + + VAL_BYTE_ROTATE(rcr_byte); + VAL_WORD_ROTATE(rcr_word); + VAL_LONG_ROTATE(rcr_long); + + VAL_BYTE_ROTATE(rol_byte); + VAL_WORD_ROTATE(rol_word); + VAL_LONG_ROTATE(rol_long); + + VAL_BYTE_ROTATE(ror_byte); + VAL_WORD_ROTATE(ror_word); + VAL_LONG_ROTATE(ror_long); + + VAL_BYTE_ROTATE(shl_byte); + VAL_WORD_ROTATE(shl_word); + VAL_LONG_ROTATE(shl_long); + + VAL_BYTE_ROTATE(shr_byte); + VAL_WORD_ROTATE(shr_word); + VAL_LONG_ROTATE(shr_long); + + VAL_BYTE_ROTATE(sar_byte); + VAL_WORD_ROTATE(sar_word); + VAL_LONG_ROTATE(sar_long); + + VAL_WORD_ROTATE_DBL(shld_word); + VAL_LONG_ROTATE_DBL(shld_long); + + VAL_WORD_ROTATE_DBL(shrd_word); + VAL_LONG_ROTATE_DBL(shrd_long); + + VAL_BYTE_BYTE_BINARY(sbb_byte); + VAL_WORD_WORD_BINARY(sbb_word); + VAL_LONG_LONG_BINARY(sbb_long); + + VAL_BYTE_BYTE_BINARY(sub_byte); + VAL_WORD_WORD_BINARY(sub_word); + VAL_LONG_LONG_BINARY(sub_long); + + VAL_BYTE_BYTE_BINARY(xor_byte); + VAL_WORD_WORD_BINARY(xor_word); + VAL_LONG_LONG_BINARY(xor_long); + + VAL_VOID_BYTE_BINARY(test_byte); + VAL_VOID_WORD_BINARY(test_word); + VAL_VOID_LONG_BINARY(test_long); + + VAL_BYTE_MUL(imul_byte); + VAL_WORD_MUL(imul_word); + VAL_LONG_MUL(imul_long); + + VAL_BYTE_MUL(mul_byte); + VAL_WORD_MUL(mul_word); + VAL_LONG_MUL(mul_long); + + VAL_BYTE_DIV(idiv_byte); + VAL_WORD_DIV(idiv_word); + VAL_LONG_DIV(idiv_long); + + VAL_BYTE_DIV(div_byte); + VAL_WORD_DIV(div_word); + VAL_LONG_DIV(div_long); + + return 0; +} diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h new file mode 100644 index 000000000..9a4a096c6 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/debug.h @@ -0,0 +1,210 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for debug definitions. +* +****************************************************************************/ + +#ifndef __X86EMU_DEBUG_H +#define __X86EMU_DEBUG_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* checks to be enabled for "runtime" */ + +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ + +#ifdef DEBUG +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +#else +# define CHECK_IP_FETCH() +# define CHECK_SP_ACCESS() +# define CHECK_MEM_ACCESS() +# define CHECK_DATA_ACCESS() +#endif + +#ifdef DEBUG +# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_CS_IP) + +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) +# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) +# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) +# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) +#else +# define DEBUG_INSTRUMENT() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 +# define DEBUG_DISASSEMBLE() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 +# define DEBUG_TRACECALL() 0 +# define DEBUG_TRACECALLREGS() 0 +# define DEBUG_SYS() 0 +# define DEBUG_MEM_TRACE() 0 +# define DEBUG_IO_TRACE() 0 +# define DEBUG_DECODE_NOPRINT() 0 +#endif + +#ifdef DEBUG + +# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ + x86emu_decode_printf(x) +# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ + x86emu_decode_printf2(x,y) + +/* + * The following allow us to look at the bytes of an instruction. The + * first INCR_INSTRN_LEN, is called everytime bytes are consumed in + * the decoding process. The SAVE_IP_CS is called initially when the + * major opcode of the instruction is accessed. + */ +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ + x86emu_inc_decoded_inst_len(x) + +#define SAVE_IP_CS(x,y) \ + if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ + } +#else +# define INC_DECODED_INST_LEN(x) +# define DECODE_PRINTF(x) +# define DECODE_PRINTF2(x,y) +# define SAVE_IP_CS(x,y) +#endif + +#ifdef DEBUG +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ + if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() +#else +# define TRACE_REGS() +#endif + +#ifdef DEBUG +# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() +#else +# define SINGLE_STEP() +#endif + +#define TRACE_AND_STEP() \ + TRACE_REGS(); \ + SINGLE_STEP() + +#ifdef DEBUG +# define START_OF_INSTR() +# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); +# define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); +#else +# define START_OF_INSTR() +# define END_OF_INSTR() +# define END_OF_INSTR_NO_TRACE() +#endif + +#ifdef DEBUG +# define CALL_TRACE(u,v,w,x,s) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); +# define RETURN_TRACE(n,u,v) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: %s\n",u,v,n); +#else +# define CALL_TRACE(u,v,w,x,s) +# define RETURN_TRACE(n,u,v) +#endif + +#ifdef DEBUG +#define DB(x) x +#else +#define DB(x) +#endif + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern void x86emu_inc_decoded_inst_len (int x); +extern void x86emu_decode_printf (char *x); +extern void x86emu_decode_printf2 (char *x, int y); +extern void x86emu_just_disassemble (void); +extern void x86emu_single_step (void); +extern void x86emu_end_instr (void); +extern void x86emu_dump_regs (void); +extern void x86emu_dump_xregs (void); +extern void x86emu_print_int_vect (u16 iv); +extern void x86emu_instrument_instruction (void); +extern void x86emu_check_ip_access (void); +extern void x86emu_check_sp_access (void); +extern void x86emu_check_mem_access (u32 p); +extern void x86emu_check_data_access (uint s, uint o); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DEBUG_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h new file mode 100644 index 000000000..321a34539 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/decode.h @@ -0,0 +1,87 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for instruction decoding logic. +* +****************************************************************************/ + +#ifndef __X86EMU_DECODE_H +#define __X86EMU_DECODE_H + +/*---------------------- Macros and type definitions ----------------------*/ + +/* Instruction Decoding Stuff */ + +#define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl) +#define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) +#define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) +#define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) +#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK + +/*-------------------------- Function Prototypes --------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +void x86emu_intr_raise (u8 type); +void fetch_decode_modrm (int *mod,int *regh,int *regl); +u8 fetch_byte_imm (void); +u16 fetch_word_imm (void); +u32 fetch_long_imm (void); +u8 fetch_data_byte (uint offset); +u8 fetch_data_byte_abs (uint segment, uint offset); +u16 fetch_data_word (uint offset); +u16 fetch_data_word_abs (uint segment, uint offset); +u32 fetch_data_long (uint offset); +u32 fetch_data_long_abs (uint segment, uint offset); +void store_data_byte (uint offset, u8 val); +void store_data_byte_abs (uint segment, uint offset, u8 val); +void store_data_word (uint offset, u16 val); +void store_data_word_abs (uint segment, uint offset, u16 val); +void store_data_long (uint offset, u32 val); +void store_data_long_abs (uint segment, uint offset, u32 val); +u8* decode_rm_byte_register(int reg); +u16* decode_rm_word_register(int reg); +u32* decode_rm_long_register(int reg); +u16* decode_rm_seg_register(int reg); +unsigned decode_rm00_address(int rm); +unsigned decode_rm01_address(int rm); +unsigned decode_rm10_address(int rm); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_DECODE_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h new file mode 100644 index 000000000..5fb271463 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/fpu.h @@ -0,0 +1,61 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for FPU instruction decoding. +* +****************************************************************************/ + +#ifndef __X86EMU_FPU_H +#define __X86EMU_FPU_H + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +/* these have to be defined, whether 8087 support compiled in or not. */ + +extern void x86emuOp_esc_coprocess_d8 (u8 op1); +extern void x86emuOp_esc_coprocess_d9 (u8 op1); +extern void x86emuOp_esc_coprocess_da (u8 op1); +extern void x86emuOp_esc_coprocess_db (u8 op1); +extern void x86emuOp_esc_coprocess_dc (u8 op1); +extern void x86emuOp_esc_coprocess_dd (u8 op1); +extern void x86emuOp_esc_coprocess_de (u8 op1); +extern void x86emuOp_esc_coprocess_df (u8 op1); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_FPU_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h new file mode 100644 index 000000000..65ea67654 --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/ops.h @@ -0,0 +1,45 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for operand decoding functions. +* +****************************************************************************/ + +#ifndef __X86EMU_OPS_H +#define __X86EMU_OPS_H + +extern void (*x86emu_optab[0x100])(u8 op1); +extern void (*x86emu_optab2[0x100])(u8 op2); + +#endif /* __X86EMU_OPS_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h new file mode 100644 index 000000000..e023cf88d --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_asm.h @@ -0,0 +1,970 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: Watcom C++ 10.6 or later +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Inline assembler versions of the primitive operand +* functions for faster performance. At the moment this is +* x86 inline assembler, but these functions could be replaced +* with native inline assembler for each supported processor +* platform. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_ASM_H +#define __X86EMU_PRIM_ASM_H + +#ifdef __WATCOMC__ + +#ifndef VALIDATE +#define __HAVE_INLINE_ASSEMBLER__ +#endif + +u32 get_flags_asm(void); +#pragma aux get_flags_asm = \ + "pushf" \ + "pop eax" \ + value [eax] \ + modify exact [eax]; + +u16 aaa_word_asm(u32 *flags,u16 d); +#pragma aux aaa_word_asm = \ + "push [edi]" \ + "popf" \ + "aaa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aas_word_asm(u32 *flags,u16 d); +#pragma aux aas_word_asm = \ + "push [edi]" \ + "popf" \ + "aas" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aad_word_asm(u32 *flags,u16 d); +#pragma aux aad_word_asm = \ + "push [edi]" \ + "popf" \ + "aad" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u16 aam_word_asm(u32 *flags,u8 d); +#pragma aux aam_word_asm = \ + "push [edi]" \ + "popf" \ + "aam" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [ax] \ + modify exact [ax]; + +u8 adc_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux adc_byte_asm = \ + "push [edi]" \ + "popf" \ + "adc al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 adc_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux adc_word_asm = \ + "push [edi]" \ + "popf" \ + "adc ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 adc_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux adc_long_asm = \ + "push [edi]" \ + "popf" \ + "adc eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 add_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux add_byte_asm = \ + "push [edi]" \ + "popf" \ + "add al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 add_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux add_word_asm = \ + "push [edi]" \ + "popf" \ + "add ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 add_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux add_long_asm = \ + "push [edi]" \ + "popf" \ + "add eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 and_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux and_byte_asm = \ + "push [edi]" \ + "popf" \ + "and al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 and_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux and_word_asm = \ + "push [edi]" \ + "popf" \ + "and ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 and_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux and_long_asm = \ + "push [edi]" \ + "popf" \ + "and eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 cmp_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux cmp_byte_asm = \ + "push [edi]" \ + "popf" \ + "cmp al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 cmp_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux cmp_word_asm = \ + "push [edi]" \ + "popf" \ + "cmp ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 cmp_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux cmp_long_asm = \ + "push [edi]" \ + "popf" \ + "cmp eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 daa_byte_asm(u32 *flags,u8 d); +#pragma aux daa_byte_asm = \ + "push [edi]" \ + "popf" \ + "daa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u8 das_byte_asm(u32 *flags,u8 d); +#pragma aux das_byte_asm = \ + "push [edi]" \ + "popf" \ + "das" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u8 dec_byte_asm(u32 *flags,u8 d); +#pragma aux dec_byte_asm = \ + "push [edi]" \ + "popf" \ + "dec al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 dec_word_asm(u32 *flags,u16 d); +#pragma aux dec_word_asm = \ + "push [edi]" \ + "popf" \ + "dec ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 dec_long_asm(u32 *flags,u32 d); +#pragma aux dec_long_asm = \ + "push [edi]" \ + "popf" \ + "dec eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 inc_byte_asm(u32 *flags,u8 d); +#pragma aux inc_byte_asm = \ + "push [edi]" \ + "popf" \ + "inc al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 inc_word_asm(u32 *flags,u16 d); +#pragma aux inc_word_asm = \ + "push [edi]" \ + "popf" \ + "inc ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 inc_long_asm(u32 *flags,u32 d); +#pragma aux inc_long_asm = \ + "push [edi]" \ + "popf" \ + "inc eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 or_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux or_byte_asm = \ + "push [edi]" \ + "popf" \ + "or al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 or_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux or_word_asm = \ + "push [edi]" \ + "popf" \ + "or ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 or_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux or_long_asm = \ + "push [edi]" \ + "popf" \ + "or eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 neg_byte_asm(u32 *flags,u8 d); +#pragma aux neg_byte_asm = \ + "push [edi]" \ + "popf" \ + "neg al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 neg_word_asm(u32 *flags,u16 d); +#pragma aux neg_word_asm = \ + "push [edi]" \ + "popf" \ + "neg ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 neg_long_asm(u32 *flags,u32 d); +#pragma aux neg_long_asm = \ + "push [edi]" \ + "popf" \ + "neg eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 not_byte_asm(u32 *flags,u8 d); +#pragma aux not_byte_asm = \ + "push [edi]" \ + "popf" \ + "not al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ + modify exact [al]; + +u16 not_word_asm(u32 *flags,u16 d); +#pragma aux not_word_asm = \ + "push [edi]" \ + "popf" \ + "not ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ + modify exact [ax]; + +u32 not_long_asm(u32 *flags,u32 d); +#pragma aux not_long_asm = \ + "push [edi]" \ + "popf" \ + "not eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ + modify exact [eax]; + +u8 rcl_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rcl_byte_asm = \ + "push [edi]" \ + "popf" \ + "rcl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rcl_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rcl_word_asm = \ + "push [edi]" \ + "popf" \ + "rcl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rcl_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rcl_long_asm = \ + "push [edi]" \ + "popf" \ + "rcl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 rcr_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rcr_byte_asm = \ + "push [edi]" \ + "popf" \ + "rcr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rcr_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rcr_word_asm = \ + "push [edi]" \ + "popf" \ + "rcr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rcr_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rcr_long_asm = \ + "push [edi]" \ + "popf" \ + "rcr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 rol_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux rol_byte_asm = \ + "push [edi]" \ + "popf" \ + "rol al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 rol_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux rol_word_asm = \ + "push [edi]" \ + "popf" \ + "rol ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 rol_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux rol_long_asm = \ + "push [edi]" \ + "popf" \ + "rol eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 ror_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux ror_byte_asm = \ + "push [edi]" \ + "popf" \ + "ror al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 ror_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux ror_word_asm = \ + "push [edi]" \ + "popf" \ + "ror ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 ror_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux ror_long_asm = \ + "push [edi]" \ + "popf" \ + "ror eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 shl_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux shl_byte_asm = \ + "push [edi]" \ + "popf" \ + "shl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 shl_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux shl_word_asm = \ + "push [edi]" \ + "popf" \ + "shl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 shl_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux shl_long_asm = \ + "push [edi]" \ + "popf" \ + "shl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 shr_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux shr_byte_asm = \ + "push [edi]" \ + "popf" \ + "shr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 shr_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux shr_word_asm = \ + "push [edi]" \ + "popf" \ + "shr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 shr_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux shr_long_asm = \ + "push [edi]" \ + "popf" \ + "shr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u8 sar_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sar_byte_asm = \ + "push [edi]" \ + "popf" \ + "sar al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ + modify exact [al cl]; + +u16 sar_word_asm(u32 *flags,u16 d, u8 s); +#pragma aux sar_word_asm = \ + "push [edi]" \ + "popf" \ + "sar ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ + modify exact [ax cl]; + +u32 sar_long_asm(u32 *flags,u32 d, u8 s); +#pragma aux sar_long_asm = \ + "push [edi]" \ + "popf" \ + "sar eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ + modify exact [eax cl]; + +u16 shld_word_asm(u32 *flags,u16 d, u16 fill, u8 s); +#pragma aux shld_word_asm = \ + "push [edi]" \ + "popf" \ + "shld ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ + modify exact [ax dx cl]; + +u32 shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s); +#pragma aux shld_long_asm = \ + "push [edi]" \ + "popf" \ + "shld eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ + modify exact [eax edx cl]; + +u16 shrd_word_asm(u32 *flags,u16 d, u16 fill, u8 s); +#pragma aux shrd_word_asm = \ + "push [edi]" \ + "popf" \ + "shrd ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ + modify exact [ax dx cl]; + +u32 shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s); +#pragma aux shrd_long_asm = \ + "push [edi]" \ + "popf" \ + "shrd eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ + modify exact [eax edx cl]; + +u8 sbb_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sbb_byte_asm = \ + "push [edi]" \ + "popf" \ + "sbb al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 sbb_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux sbb_word_asm = \ + "push [edi]" \ + "popf" \ + "sbb ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 sbb_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux sbb_long_asm = \ + "push [edi]" \ + "popf" \ + "sbb eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +u8 sub_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux sub_byte_asm = \ + "push [edi]" \ + "popf" \ + "sub al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 sub_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux sub_word_asm = \ + "push [edi]" \ + "popf" \ + "sub ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 sub_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux sub_long_asm = \ + "push [edi]" \ + "popf" \ + "sub eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +void test_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux test_byte_asm = \ + "push [edi]" \ + "popf" \ + "test al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + modify exact [al bl]; + +void test_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux test_word_asm = \ + "push [edi]" \ + "popf" \ + "test ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + modify exact [ax bx]; + +void test_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux test_long_asm = \ + "push [edi]" \ + "popf" \ + "test eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + modify exact [eax ebx]; + +u8 xor_byte_asm(u32 *flags,u8 d, u8 s); +#pragma aux xor_byte_asm = \ + "push [edi]" \ + "popf" \ + "xor al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ + modify exact [al bl]; + +u16 xor_word_asm(u32 *flags,u16 d, u16 s); +#pragma aux xor_word_asm = \ + "push [edi]" \ + "popf" \ + "xor ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ + modify exact [ax bx]; + +u32 xor_long_asm(u32 *flags,u32 d, u32 s); +#pragma aux xor_long_asm = \ + "push [edi]" \ + "popf" \ + "xor eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ + modify exact [eax ebx]; + +void imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); +#pragma aux imul_byte_asm = \ + "push [edi]" \ + "popf" \ + "imul bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + parm [edi] [esi] [al] [bl] \ + modify exact [esi ax bl]; + +void imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); +#pragma aux imul_word_asm = \ + "push [edi]" \ + "popf" \ + "imul bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [bx]\ + modify exact [esi edi ax bx dx]; + +void imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); +#pragma aux imul_long_asm = \ + "push [edi]" \ + "popf" \ + "imul ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [ebx] \ + modify exact [esi edi eax ebx edx]; + +void mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); +#pragma aux mul_byte_asm = \ + "push [edi]" \ + "popf" \ + "mul bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + parm [edi] [esi] [al] [bl] \ + modify exact [esi ax bl]; + +void mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); +#pragma aux mul_word_asm = \ + "push [edi]" \ + "popf" \ + "mul bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [bx]\ + modify exact [esi edi ax bx dx]; + +void mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); +#pragma aux mul_long_asm = \ + "push [edi]" \ + "popf" \ + "mul ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [ebx] \ + modify exact [esi edi eax ebx edx]; + +void idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); +#pragma aux idiv_byte_asm = \ + "push [edi]" \ + "popf" \ + "idiv bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],al" \ + "mov [ecx],ah" \ + parm [edi] [esi] [ecx] [ax] [bl]\ + modify exact [esi edi ax bl]; + +void idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); +#pragma aux idiv_word_asm = \ + "push [edi]" \ + "popf" \ + "idiv bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [dx] [bx]\ + modify exact [esi edi ax dx bx]; + +void idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); +#pragma aux idiv_long_asm = \ + "push [edi]" \ + "popf" \ + "idiv ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ + modify exact [esi edi eax edx ebx]; + +void div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); +#pragma aux div_byte_asm = \ + "push [edi]" \ + "popf" \ + "div bl" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],al" \ + "mov [ecx],ah" \ + parm [edi] [esi] [ecx] [ax] [bl]\ + modify exact [esi edi ax bl]; + +void div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); +#pragma aux div_word_asm = \ + "push [edi]" \ + "popf" \ + "div bx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],ax" \ + "mov [ecx],dx" \ + parm [edi] [esi] [ecx] [ax] [dx] [bx]\ + modify exact [esi edi ax dx bx]; + +void div_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); +#pragma aux div_long_asm = \ + "push [edi]" \ + "popf" \ + "div ebx" \ + "pushf" \ + "pop [edi]" \ + "mov [esi],eax" \ + "mov [ecx],edx" \ + parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ + modify exact [esi edi eax edx ebx]; + +#endif + +#endif /* __X86EMU_PRIM_ASM_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h new file mode 100644 index 000000000..1633fe1fa --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/prim_ops.h @@ -0,0 +1,231 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for primitive operation functions. +* +****************************************************************************/ + +#ifndef __X86EMU_PRIM_OPS_H +#define __X86EMU_PRIM_OPS_H + +#include "x86emu/prim_asm.h" + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +u16 aaa_word (u16 d); +u16 aas_word (u16 d); +u16 aad_word (u16 d); +u16 aam_word (u8 d); +u8 adc_byte (u8 d, u8 s); +u16 adc_word (u16 d, u16 s); +u32 adc_long (u32 d, u32 s); +u8 add_byte (u8 d, u8 s); +u16 add_word (u16 d, u16 s); +u32 add_long (u32 d, u32 s); +u8 and_byte (u8 d, u8 s); +u16 and_word (u16 d, u16 s); +u32 and_long (u32 d, u32 s); +u8 cmp_byte (u8 d, u8 s); +u16 cmp_word (u16 d, u16 s); +u32 cmp_long (u32 d, u32 s); +u8 daa_byte (u8 d); +u8 das_byte (u8 d); +u8 dec_byte (u8 d); +u16 dec_word (u16 d); +u32 dec_long (u32 d); +u8 inc_byte (u8 d); +u16 inc_word (u16 d); +u32 inc_long (u32 d); +u8 or_byte (u8 d, u8 s); +u16 or_word (u16 d, u16 s); +u32 or_long (u32 d, u32 s); +u8 neg_byte (u8 s); +u16 neg_word (u16 s); +u32 neg_long (u32 s); +u8 not_byte (u8 s); +u16 not_word (u16 s); +u32 not_long (u32 s); +u8 rcl_byte (u8 d, u8 s); +u16 rcl_word (u16 d, u8 s); +u32 rcl_long (u32 d, u8 s); +u8 rcr_byte (u8 d, u8 s); +u16 rcr_word (u16 d, u8 s); +u32 rcr_long (u32 d, u8 s); +u8 rol_byte (u8 d, u8 s); +u16 rol_word (u16 d, u8 s); +u32 rol_long (u32 d, u8 s); +u8 ror_byte (u8 d, u8 s); +u16 ror_word (u16 d, u8 s); +u32 ror_long (u32 d, u8 s); +u8 shl_byte (u8 d, u8 s); +u16 shl_word (u16 d, u8 s); +u32 shl_long (u32 d, u8 s); +u8 shr_byte (u8 d, u8 s); +u16 shr_word (u16 d, u8 s); +u32 shr_long (u32 d, u8 s); +u8 sar_byte (u8 d, u8 s); +u16 sar_word (u16 d, u8 s); +u32 sar_long (u32 d, u8 s); +u16 shld_word (u16 d, u16 fill, u8 s); +u32 shld_long (u32 d, u32 fill, u8 s); +u16 shrd_word (u16 d, u16 fill, u8 s); +u32 shrd_long (u32 d, u32 fill, u8 s); +u8 sbb_byte (u8 d, u8 s); +u16 sbb_word (u16 d, u16 s); +u32 sbb_long (u32 d, u32 s); +u8 sub_byte (u8 d, u8 s); +u16 sub_word (u16 d, u16 s); +u32 sub_long (u32 d, u32 s); +void test_byte (u8 d, u8 s); +void test_word (u16 d, u16 s); +void test_long (u32 d, u32 s); +u8 xor_byte (u8 d, u8 s); +u16 xor_word (u16 d, u16 s); +u32 xor_long (u32 d, u32 s); +void imul_byte (u8 s); +void imul_word (u16 s); +void imul_long (u32 s); +void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); +void mul_byte (u8 s); +void mul_word (u16 s); +void mul_long (u32 s); +void idiv_byte (u8 s); +void idiv_word (u16 s); +void idiv_long (u32 s); +void div_byte (u8 s); +void div_word (u16 s); +void div_long (u32 s); +void ins (int size); +void outs (int size); +u16 mem_access_word (int addr); +void push_word (u16 w); +void push_long (u32 w); +u16 pop_word (void); +u32 pop_long (void); + +#if defined(__HAVE_INLINE_ASSEMBLER__) && !defined(PRIM_OPS_NO_REDEFINE_ASM) + +#define aaa_word(d) aaa_word_asm(&M.x86.R_EFLG,d) +#define aas_word(d) aas_word_asm(&M.x86.R_EFLG,d) +#define aad_word(d) aad_word_asm(&M.x86.R_EFLG,d) +#define aam_word(d) aam_word_asm(&M.x86.R_EFLG,d) +#define adc_byte(d,s) adc_byte_asm(&M.x86.R_EFLG,d,s) +#define adc_word(d,s) adc_word_asm(&M.x86.R_EFLG,d,s) +#define adc_long(d,s) adc_long_asm(&M.x86.R_EFLG,d,s) +#define add_byte(d,s) add_byte_asm(&M.x86.R_EFLG,d,s) +#define add_word(d,s) add_word_asm(&M.x86.R_EFLG,d,s) +#define add_long(d,s) add_long_asm(&M.x86.R_EFLG,d,s) +#define and_byte(d,s) and_byte_asm(&M.x86.R_EFLG,d,s) +#define and_word(d,s) and_word_asm(&M.x86.R_EFLG,d,s) +#define and_long(d,s) and_long_asm(&M.x86.R_EFLG,d,s) +#define cmp_byte(d,s) cmp_byte_asm(&M.x86.R_EFLG,d,s) +#define cmp_word(d,s) cmp_word_asm(&M.x86.R_EFLG,d,s) +#define cmp_long(d,s) cmp_long_asm(&M.x86.R_EFLG,d,s) +#define daa_byte(d) daa_byte_asm(&M.x86.R_EFLG,d) +#define das_byte(d) das_byte_asm(&M.x86.R_EFLG,d) +#define dec_byte(d) dec_byte_asm(&M.x86.R_EFLG,d) +#define dec_word(d) dec_word_asm(&M.x86.R_EFLG,d) +#define dec_long(d) dec_long_asm(&M.x86.R_EFLG,d) +#define inc_byte(d) inc_byte_asm(&M.x86.R_EFLG,d) +#define inc_word(d) inc_word_asm(&M.x86.R_EFLG,d) +#define inc_long(d) inc_long_asm(&M.x86.R_EFLG,d) +#define or_byte(d,s) or_byte_asm(&M.x86.R_EFLG,d,s) +#define or_word(d,s) or_word_asm(&M.x86.R_EFLG,d,s) +#define or_long(d,s) or_long_asm(&M.x86.R_EFLG,d,s) +#define neg_byte(s) neg_byte_asm(&M.x86.R_EFLG,s) +#define neg_word(s) neg_word_asm(&M.x86.R_EFLG,s) +#define neg_long(s) neg_long_asm(&M.x86.R_EFLG,s) +#define not_byte(s) not_byte_asm(&M.x86.R_EFLG,s) +#define not_word(s) not_word_asm(&M.x86.R_EFLG,s) +#define not_long(s) not_long_asm(&M.x86.R_EFLG,s) +#define rcl_byte(d,s) rcl_byte_asm(&M.x86.R_EFLG,d,s) +#define rcl_word(d,s) rcl_word_asm(&M.x86.R_EFLG,d,s) +#define rcl_long(d,s) rcl_long_asm(&M.x86.R_EFLG,d,s) +#define rcr_byte(d,s) rcr_byte_asm(&M.x86.R_EFLG,d,s) +#define rcr_word(d,s) rcr_word_asm(&M.x86.R_EFLG,d,s) +#define rcr_long(d,s) rcr_long_asm(&M.x86.R_EFLG,d,s) +#define rol_byte(d,s) rol_byte_asm(&M.x86.R_EFLG,d,s) +#define rol_word(d,s) rol_word_asm(&M.x86.R_EFLG,d,s) +#define rol_long(d,s) rol_long_asm(&M.x86.R_EFLG,d,s) +#define ror_byte(d,s) ror_byte_asm(&M.x86.R_EFLG,d,s) +#define ror_word(d,s) ror_word_asm(&M.x86.R_EFLG,d,s) +#define ror_long(d,s) ror_long_asm(&M.x86.R_EFLG,d,s) +#define shl_byte(d,s) shl_byte_asm(&M.x86.R_EFLG,d,s) +#define shl_word(d,s) shl_word_asm(&M.x86.R_EFLG,d,s) +#define shl_long(d,s) shl_long_asm(&M.x86.R_EFLG,d,s) +#define shr_byte(d,s) shr_byte_asm(&M.x86.R_EFLG,d,s) +#define shr_word(d,s) shr_word_asm(&M.x86.R_EFLG,d,s) +#define shr_long(d,s) shr_long_asm(&M.x86.R_EFLG,d,s) +#define sar_byte(d,s) sar_byte_asm(&M.x86.R_EFLG,d,s) +#define sar_word(d,s) sar_word_asm(&M.x86.R_EFLG,d,s) +#define sar_long(d,s) sar_long_asm(&M.x86.R_EFLG,d,s) +#define shld_word(d,fill,s) shld_word_asm(&M.x86.R_EFLG,d,fill,s) +#define shld_long(d,fill,s) shld_long_asm(&M.x86.R_EFLG,d,fill,s) +#define shrd_word(d,fill,s) shrd_word_asm(&M.x86.R_EFLG,d,fill,s) +#define shrd_long(d,fill,s) shrd_long_asm(&M.x86.R_EFLG,d,fill,s) +#define sbb_byte(d,s) sbb_byte_asm(&M.x86.R_EFLG,d,s) +#define sbb_word(d,s) sbb_word_asm(&M.x86.R_EFLG,d,s) +#define sbb_long(d,s) sbb_long_asm(&M.x86.R_EFLG,d,s) +#define sub_byte(d,s) sub_byte_asm(&M.x86.R_EFLG,d,s) +#define sub_word(d,s) sub_word_asm(&M.x86.R_EFLG,d,s) +#define sub_long(d,s) sub_long_asm(&M.x86.R_EFLG,d,s) +#define test_byte(d,s) test_byte_asm(&M.x86.R_EFLG,d,s) +#define test_word(d,s) test_word_asm(&M.x86.R_EFLG,d,s) +#define test_long(d,s) test_long_asm(&M.x86.R_EFLG,d,s) +#define xor_byte(d,s) xor_byte_asm(&M.x86.R_EFLG,d,s) +#define xor_word(d,s) xor_word_asm(&M.x86.R_EFLG,d,s) +#define xor_long(d,s) xor_long_asm(&M.x86.R_EFLG,d,s) +#define imul_byte(s) imul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s) +#define imul_word(s) imul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s) +#define imul_long(s) imul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s) +#define imul_long_direct(res_lo,res_hi,d,s) imul_long_asm(&M.x86.R_EFLG,res_lo,res_hi,d,s) +#define mul_byte(s) mul_byte_asm(&M.x86.R_EFLG,&M.x86.R_AX,M.x86.R_AL,s) +#define mul_word(s) mul_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,s) +#define mul_long(s) mul_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s) +#define idiv_byte(s) idiv_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s) +#define idiv_word(s) idiv_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s) +#define idiv_long(s) idiv_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s) +#define div_byte(s) div_byte_asm(&M.x86.R_EFLG,&M.x86.R_AL,&M.x86.R_AH,M.x86.R_AX,s) +#define div_word(s) div_word_asm(&M.x86.R_EFLG,&M.x86.R_AX,&M.x86.R_DX,M.x86.R_AX,M.x86.R_DX,s) +#define div_long(s) div_long_asm(&M.x86.R_EFLG,&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,M.x86.R_EDX,s) + +#endif + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_PRIM_OPS_H */ diff --git a/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h new file mode 100644 index 000000000..bff49039e --- /dev/null +++ b/board/MAI/bios_emulator/scitech/src/x86emu/x86emu/x86emui.h @@ -0,0 +1,98 @@ +/**************************************************************************** +* +* Realmode X86 Emulator Library +* +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich +* +* ======================================================================== +* +* Permission to use, copy, modify, distribute, and sell this software and +* its documentation for any purpose is hereby granted without fee, +* provided that the above copyright notice appear in all copies and that +* both that copyright notice and this permission notice appear in +* supporting documentation, and that the name of the authors not be used +* in advertising or publicity pertaining to distribution of the software +* without specific, written prior permission. The authors makes no +* representations about the suitability of this software for any purpose. +* It is provided "as is" without express or implied warranty. +* +* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO +* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR +* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF +* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +* PERFORMANCE OF THIS SOFTWARE. +* +* ======================================================================== +* +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett +* +* Description: Header file for system specific functions. These functions +* are always compiled and linked in the OS depedent libraries, +* and never in a binary portable driver. +* +****************************************************************************/ + +#ifndef __X86EMU_X86EMUI_H +#define __X86EMU_X86EMUI_H + +/* If we are compiling in C++ mode, we can compile some functions as + * inline to increase performance (however the code size increases quite + * dramatically in this case). + */ + +#if defined(__cplusplus) && !defined(_NO_INLINE) +#define _INLINE inline +#else +#define _INLINE static +#endif + +/* Get rid of unused parameters in C++ compilation mode */ + +#ifdef __cplusplus +#define X86EMU_UNUSED(v) +#else +#define X86EMU_UNUSED(v) v +#endif + +#include "x86emu.h" +#include "x86emu/regs.h" +#include "x86emu/debug.h" +#include "x86emu/decode.h" +#include "x86emu/ops.h" +#include "x86emu/prim_ops.h" +#include "x86emu/fpu.h" +#include "x86emu/fpu_regs.h" +#include +#include + +/*--------------------------- Inline Functions ----------------------------*/ + +#ifdef __cplusplus +extern "C" { /* Use "C" linkage when in C++ mode */ +#endif + +extern u8 (X86APIP sys_rdb)(u32 addr); +extern u16 (X86APIP sys_rdw)(u32 addr); +extern u32 (X86APIP sys_rdl)(u32 addr); +extern void (X86APIP sys_wrb)(u32 addr,u8 val); +extern void (X86APIP sys_wrw)(u32 addr,u16 val); +extern void (X86APIP sys_wrl)(u32 addr,u32 val); + +extern u8 (X86APIP sys_inb)(X86EMU_pioAddr addr); +extern u16 (X86APIP sys_inw)(X86EMU_pioAddr addr); +extern u32 (X86APIP sys_inl)(X86EMU_pioAddr addr); +extern void (X86APIP sys_outb)(X86EMU_pioAddr addr,u8 val); +extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val); +extern void (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val); + +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ +#endif + +#endif /* __X86EMU_X86EMUI_H */ diff --git a/board/MAI/bios_emulator/x86interface.c b/board/MAI/bios_emulator/x86interface.c new file mode 100644 index 000000000..909cb3cf9 --- /dev/null +++ b/board/MAI/bios_emulator/x86interface.c @@ -0,0 +1,814 @@ +#include "x86emu.h" +#include "glue.h" + + +/* + * This isn't nice, but there are a lot of incompatibilities in the U-Boot and scitech include + * files that this is the only really workable solution. + * Might be cleaned out later. + */ + +#ifdef DEBUG +#undef DEBUG +#endif + +#undef IO_LOGGING +#undef MEM_LOGGING + +#ifdef IO_LOGGING +#define LOGIO(port, format, args...) if (dolog(port)) _printf(format , ## args) +#else +#define LOGIO(port, format, args...) +#endif + +#ifdef MEM_LOGGIN +#define LOGMEM(format, args...) _printf(format , ## args) +#else +#define LOGMEM(format, args...) +#endif + +#ifdef DEBUG +#define PRINTF(format, args...) _printf(format , ## args) +#else +#define PRINTF(format, argc...) +#endif + +typedef unsigned char UBYTE; +typedef unsigned short UWORD; +typedef unsigned long ULONG; + +typedef char BYTE; +typedef short WORT; +typedef long LONG; + +#define EMULATOR_MEM_SIZE (1024*1024) +#define EMULATOR_BIOS_OFFSET 0xC0000 +#define EMULATOR_STRAP_OFFSET 0x30000 +#define EMULATOR_STACK_OFFSET 0x20000 +#define EMULATOR_LOGO_OFFSET 0x40000 /* If you change this, change the strap code, too */ +#define VIDEO_BASE (void *)0xFD0B8000 + +extern char *getenv(char *); +extern int tstc(void); +extern int getc(void); +extern unsigned char video_get_attr(void); + +int atoi(char *string) +{ + int res = 0; + while (*string>='0' && *string <='9') + { + res *= 10; + res += *string-'0'; + string++; + } + + return res; +} + +void cons_gets(char *buffer) +{ + int i = 0; + char c = 0; + + buffer[0] = 0; + if (getenv("x86_runthru")) return; /*FIXME: */ + while (c != 0x0D && c != 0x0A) + { + while (!tstc()); + c = getc(); + if (c>=32 && c < 127) + { + buffer[i] = c; + i++; + buffer[i] = 0; + putc(c); + } + else + { + if (c == 0x08) + { + if (i>0) i--; + buffer[i] = 0; + } + } + } + buffer[i] = '\n'; + buffer[i+1] = 0; +} + +char *bios_date = "08/14/02"; +UBYTE model = 0xFC; +UBYTE submodel = 0x00; + +static inline UBYTE read_byte(volatile UBYTE* from) +{ + int x; + asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (UBYTE)x; +} + +static inline void write_byte(volatile UBYTE *to, int x) +{ + asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static inline UWORD read_word_little(volatile UWORD *from) +{ + int x; + asm volatile ("lhbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m" (*from)); + return (UWORD)x; +} + +static inline UWORD read_word_big(volatile UWORD *from) +{ + int x; + asm volatile ("lhz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (UWORD)x; +} + +static inline void write_word_little(volatile UWORD *to, int x) +{ + asm volatile ("sthbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); +} + +static inline void write_word_big(volatile UWORD *to, int x) +{ + asm volatile ("sth %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static inline ULONG read_long_little(volatile ULONG *from) +{ + unsigned long x; + asm volatile ("lwbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m"(*from)); + return (ULONG)x; +} + +static inline ULONG read_long_big(volatile ULONG *from) +{ + unsigned long x; + asm volatile ("lwz %0,%1\n eieio" : "=r" (x) : "m" (*from)); + return (ULONG)x; +} + +static inline void write_long_little(volatile ULONG *to, ULONG x) +{ + asm volatile ("stwbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to)); +} + +static inline void write_long_big(volatile ULONG *to, ULONG x) +{ + asm volatile ("stw %1,%0\n eieio" : "=m" (*to) : "r" (x)); +} + +static int log_init = 0; +static int log_do = 0; +static int log_low = 0; + +int dolog(int port) +{ + if (log_init && log_do) + { + if (log_low && port > 0x400) return 0; + return 1; + } + + if (!log_init) + { + log_init = 1; + log_do = (getenv("x86_logio") != (char *)0); + log_low = (getenv("x86_loglow") != (char *)0); + if (log_do) + { + if (log_low && port > 0x400) return 0; + return 1; + } + } + return 0; +} + +/* Converts an emulator address to a physical address. */ +/* Handles all special cases (bios date, model etc), and might need work */ +u32 memaddr(u32 addr) +{ +/* if (addr >= 0xF0000 && addr < 0xFFFFF) printf("WARNING: Segment F access (0x%x)\n", addr); */ +/* printf("MemAddr=%p\n", addr); */ + if (addr >= 0xA0000 && addr < 0xC0000) + return 0xFD000000 + addr; + else if (addr >= 0xFFFF5 && addr < 0xFFFFE) + { + return (u32)bios_date+addr-0xFFFF5; + } + else if (addr == 0xFFFFE) + return (u32)&model; + else if (addr == 0xFFFFF) + return (u32)&submodel; + else if (addr >= 0x80000000) + { + /*printf("Warning: High memory access at 0x%x\n", addr); */ + return addr; + } + else + return (u32)M.mem_base+addr; +} + +u8 A1_rdb(u32 addr) +{ + u8 a = read_byte((UBYTE *)memaddr(addr)); + LOGMEM("rdb: %x -> %x\n", addr, a); + return a; +} + +u16 A1_rdw(u32 addr) +{ + u16 a = read_word_little((UWORD *)memaddr(addr)); + LOGMEM("rdw: %x -> %x\n", addr, a); + return a; +} + +u32 A1_rdl(u32 addr) +{ + u32 a = read_long_little((ULONG *)memaddr(addr)); + LOGMEM("rdl: %x -> %x\n", addr, a); + return a; +} + +void A1_wrb(u32 addr, u8 val) +{ + LOGMEM("wrb: %x <- %x\n", addr, val); + write_byte((UBYTE *)memaddr(addr), val); +} + +void A1_wrw(u32 addr, u16 val) +{ + LOGMEM("wrw: %x <- %x\n", addr, val); + write_word_little((UWORD *)memaddr(addr), val); +} + +void A1_wrl(u32 addr, u32 val) +{ + LOGMEM("wrl: %x <- %x\n", addr, val); + write_long_little((ULONG *)memaddr(addr), val); +} + +X86EMU_memFuncs _A1_mem = +{ + A1_rdb, + A1_rdw, + A1_rdl, + A1_wrb, + A1_wrw, + A1_wrl, +}; + +#define ARTICIAS_PCI_CFGADDR 0xfec00cf8 +#define ARTICIAS_PCI_CFGDATA 0xfee00cfc +#define IOBASE 0xFE000000 + +#define in_byte(from) read_byte( (UBYTE *)port_to_mem(from)) +#define in_word(from) read_word_little((UWORD *)port_to_mem(from)) +#define in_long(from) read_long_little((ULONG *)port_to_mem(from)) +#define out_byte(to, val) write_byte((UBYTE *)port_to_mem(to), val) +#define out_word(to, val) write_word_little((UWORD *)port_to_mem(to), val) +#define out_long(to, val) write_long_little((ULONG *)port_to_mem(to), val) + +u32 port_to_mem(int port) +{ + if (port >= 0xCFC && port <= 0xCFF) return 0xFEE00000+port; + else if (port >= 0xCF8 && port <= 0xCFB) return 0xFEC00000+port; + else return IOBASE + port; +} + +u8 A1_inb(int port) +{ + u8 a; + /*if (port == 0x3BA) return 0; */ + a = in_byte(port); + LOGIO(port, "inb: %Xh -> %d (%Xh)\n", port, a, a); + return a; +} + +u16 A1_inw(int port) +{ + u16 a = in_word(port); + LOGIO(port, "inw: %Xh -> %d (%Xh)\n", port, a, a); + return a; +} + +u32 A1_inl(int port) +{ + u32 a = in_long(port); + LOGIO(port, "inl: %Xh -> %d (%Xh)\n", port, a, a); + return a; +} + +void A1_outb(int port, u8 val) +{ + LOGIO(port, "outb: %Xh <- %d (%Xh)\n", port, val, val); +/* if (port == 0xCF8) port = 0xCFB; + else if (port == 0xCF9) port = 0xCFA; + else if (port == 0xCFA) port = 0xCF9; + else if (port == 0xCFB) port = 0xCF8;*/ + out_byte(port, val); +} + +void A1_outw(int port, u16 val) +{ + LOGIO(port, "outw: %Xh <- %d (%Xh)\n", port, val, val); + out_word(port, val); +} + +void A1_outl(int port, u32 val) +{ + LOGIO(port, "outl: %Xh <- %d (%Xh)\n", port, val, val); + out_long(port, val); +} + +X86EMU_pioFuncs _A1_pio = +{ + A1_inb, + A1_inw, + A1_inl, + A1_outb, + A1_outw, + A1_outl, +}; + +static int reloced_ops = 0; + +void reloc_ops(void *reloc_addr) +{ + extern void (*x86emu_optab[256])(u8); + extern void (*x86emu_optab2[256])(u8); + extern void tables_relocate(unsigned int offset); + int i; + unsigned long delta; + if (reloced_ops == 1) return; + reloced_ops = 1; + + delta = TEXT_BASE - (unsigned long)reloc_addr; + + for (i=0; i<256; i++) + { + x86emu_optab[i] -= delta; + x86emu_optab2[i] -= delta; + } + + _A1_mem.rdb = A1_rdb; + _A1_mem.rdw = A1_rdw; + _A1_mem.rdl = A1_rdl; + _A1_mem.wrb = A1_wrb; + _A1_mem.wrw = A1_wrw; + _A1_mem.wrl = A1_wrl; + + _A1_pio.inb = A1_inb; + _A1_pio.inw = A1_inw; + _A1_pio.inl = A1_inl; + _A1_pio.outb = A1_outb; + _A1_pio.outw = A1_outw; + _A1_pio.outl = A1_outl; + + tables_relocate(delta); + +} + + +#define ANY_KEY(text) \ + printf(text); \ + while (!tstc()); + + +unsigned char more_strap[] = { + 0xb4, 0x0, 0xb0, 0x2, 0xcd, 0x10, +}; +#define MORE_STRAP_BYTES 6 /* Additional bytes of strap code */ + + +unsigned char *done_msg="VGA Initialized\0"; + +int execute_bios(pci_dev_t gr_dev, void *reloc_addr) +{ + extern void bios_init(void); + extern void remove_init_data(void); + extern int video_rows(void); + extern int video_cols(void); + extern int video_size(int, int); + u8 *strap; + unsigned char *logo; + u8 cfg; + int i; + char c; + char *s; +#ifdef EASTEREGG + int easteregg_active = 0; +#endif + char *pal_reset; + u8 *fb; + unsigned char *msg; + unsigned char current_attr; + + PRINTF("Trying to remove init data\n"); + remove_init_data(); + PRINTF("Removed init data from cache, now in RAM\n"); + + reloc_ops(reloc_addr); + PRINTF("Attempting to run emulator on %02x:%02x:%02x\n", + PCI_BUS(gr_dev), PCI_DEV(gr_dev), PCI_FUNC(gr_dev)); + + /* Enable compatibility hole for emulator access to frame buffer */ + PRINTF("Enabling compatibility hole\n"); + enable_compatibility_hole(); + + /* Allocate memory */ + /* FIXME: We shouldn't use this much memory really. */ + memset(&M, 0, sizeof(X86EMU_sysEnv)); + M.mem_base = malloc(EMULATOR_MEM_SIZE); + M.mem_size = EMULATOR_MEM_SIZE; + + if (!M.mem_base) + { + PRINTF("Unable to allocate one megabyte for emulator\n"); + return 0; + } + + if (attempt_map_rom(gr_dev, M.mem_base + EMULATOR_BIOS_OFFSET) == 0) + { + PRINTF("Error mapping rom. Emulation terminated\n"); + return 0; + } + +#if 1 /*def DEBUG*/ + s = getenv("x86_ask_start"); + if (s) + { + printf("Press 'q' to skip initialization, 'd' for dry init\n'i' for i/o session"); + while (!tstc()); + c = getc(); + if (c == 'q') return 0; + if (c == 'd') + { + extern void bios_set_mode(int mode); + bios_set_mode(0x03); + return 0; + } + if (c == 'i') do_inout(); + } + + +#endif + +#ifdef EASTEREGG +/* if (tstc()) + { + if (getc() == 'c') + { + easteregg_active = 1; + } + } +*/ + if (getenv("easteregg")) + { + easteregg_active = 1; + } + + if (easteregg_active) + { + /* Yay! */ + setenv("x86_mode", "1"); + setenv("vga_fg_color", "11"); + setenv("vga_bg_color", "1"); + easteregg_active = 1; + } +#endif + + strap = (u8*)M.mem_base + EMULATOR_STRAP_OFFSET; + + { + char *m = getenv("x86_mode"); + if (m) + { + more_strap[3] = atoi(m); + if (more_strap[3] == 1) video_size(40, 25); + else video_size(80, 25); + } + } + + /* + * Poke the strap routine. This might need a bit of extending + * if there is a mode switch involved, i.e. we want to int10 + * afterwards to set a different graphics mode, or alternatively + * there might be a different start address requirement if the + * ROM doesn't have an x86 image in its first image. + */ + + PRINTF("Poking strap...\n"); + + /* FAR CALL c000:0003 */ + *strap++ = 0x9A; *strap++ = 0x03; *strap++ = 0x00; + *strap++ = 0x00; *strap++ = 0xC0; + +#if 1 + /* insert additional strap code */ + for (i=0; i < MORE_STRAP_BYTES; i++) + { + *strap++ = more_strap[i]; + } +#endif + /* HALT */ + *strap++ = 0xF4; + + PRINTF("Setting up logo data\n"); + logo = (unsigned char *)M.mem_base + EMULATOR_LOGO_OFFSET; + for (i=0; i<16; i++) + { + *logo++ = 0xFF; + } + + /* + * Setup the init parameters. + * Per PCI specs, AH must contain the bus and AL + * must contain the devfn, encoded as (dev<<3)|fn + */ + + /* Execution starts here */ + M.x86.R_CS = SEG(EMULATOR_STRAP_OFFSET); + M.x86.R_IP = OFF(EMULATOR_STRAP_OFFSET); + + /* Stack at top of ram */ + M.x86.R_SS = SEG(EMULATOR_STACK_OFFSET); + M.x86.R_SP = OFF(EMULATOR_STACK_OFFSET); + + /* Input parameters */ + M.x86.R_AH = PCI_BUS(gr_dev); + M.x86.R_AL = (PCI_DEV(gr_dev)<<3) | PCI_FUNC(gr_dev); + + /* Set the I/O and memory access functions */ + X86EMU_setupMemFuncs(&_A1_mem); + X86EMU_setupPioFuncs(&_A1_pio); + + /* Enable timer 2 */ + cfg = in_byte(0x61); /* Get Misc control */ + cfg |= 0x01; /* Enable timer 2 */ + out_byte(0x61, cfg); /* output again */ + + /* Set up the timers */ + out_byte(0x43, 0x54); + out_byte(0x41, 0x18); + + out_byte(0x43, 0x36); + out_byte(0x40, 0x00); + out_byte(0x40, 0x00); + + out_byte(0x43, 0xb6); + out_byte(0x42, 0x31); + out_byte(0x42, 0x13); + + /* Init the "BIOS". */ + bios_init(); + + /* Video Card Reset */ + out_byte(0x3D8, 0); + out_byte(0x3B8, 1); + (void)in_byte(0x3BA); + (void)in_byte(0x3DA); + out_byte(0x3C0, 0); + out_byte(0x61, 0xFC); + +#ifdef DEBUG + s = _getenv("x86_singlestep"); + if (s && strcmp(s, "on")==0) + { + PRINTF("Enabling single stepping for debug\n"); + X86EMU_trace_on(); + } +#endif + + /* Ready set go... */ + PRINTF("Running emulator\n"); + X86EMU_exec(); + PRINTF("Done running emulator\n"); + +/* FIXME: Remove me */ + pal_reset = getenv("x86_palette_reset"); + if (pal_reset && strcmp(pal_reset, "on") == 0) + { + PRINTF("Palette reset\n"); + /*(void)in_byte(0x3da); */ + /*out_byte(0x3c0, 0); */ + + out_byte(0x3C8, 0); + out_byte(0x3C9, 0); + out_byte(0x3C9, 0); + out_byte(0x3C9, 0); + for (i=0; i<254; i++) + { + out_byte(0x3C9, 63); + out_byte(0x3C9, 63); + out_byte(0x3C9, 63); + } + + out_byte(0x3c0, 0x20); + } +/* FIXME: remove me */ +#ifdef EASTEREGG + if (easteregg_active) + { + extern void video_easteregg(void); + video_easteregg(); + } +#endif +/* + current_attr = video_get_attr(); + fb = (u8 *)VIDEO_BASE; + for (i=0; iused = 0; +} + +void menu_layout (menu_t *menu) +{ diff --git a/board/MAI/menu/menu.h b/board/MAI/menu/menu.h new file mode 100644 index 000000000..8aebb7de5 --- /dev/null +++ b/board/MAI/menu/menu.h @@ -0,0 +1,174 @@ +#ifndef MENU_H +#define MENU_H + +/* A single menu */ +typedef void (*menu_finish_callback)(struct menu_s *menu); + +typedef struct menu_s +{ + char *name; /* Menu name */ + int num_options; /* Number of options in this menu */ + int flags; /* Various flags - see below */ + int option_align; /* Aligns options to a field width of this much characters if != 0 */ + + struct menu_option_s **options; /* Pointer to this menu's options */ + menu_finish_callback callback; /* Called when the menu closes */ +} menu_t; + +/* + * type: Type of the option (see below) + * name: Name to display for this option + * help: Optional help string + * id : optional id number + * sys : pointer for system-specific data, init to NULL and don't touch + */ + +#define OPTION_PREAMBLE \ + int type; \ + char *name; \ + char *help; \ + int id; \ + void *sys; \ + + +/* + * Menu option types. + * There are a number of different layouts for menu options depending + * on their types. Currently there are the following possibilities: + * + * Submenu: + * This entry links to a new menu. + * + * Boolean: + * A simple on/off toggle entry. Booleans can be either yes/no, 0/1 or on/off. + * Optionally, this entry can enable/disable a set of other options. An example would + * be to enable/disable on-board USB, and if enabled give access to further options like + * irq settings, base address etc. + * + * Text: + * A single line/limited number of characters text entry box. Text can be restricted + * to a certain charset (digits/hex digits/all/custom). Result is also available as an + * int if numeric. + * + * Selection: + * One-of-many type of selection entry. User may choose on of a set of strings, which + * maps to a specific value for the variable. + * + * Routine: + * Selecting this calls an entry-specific routine. This can be used for saving contents etc. + * + * Custom: + * Display and behaviour of this entry is defined by a set of callbacks. + */ + +#define MENU_SUBMENU_TYPE 0 +typedef struct menu_submenu_s +{ + OPTION_PREAMBLE + + menu_t * submenu; /* Pointer to the submenu */ +} menu_submenu_t; + +#define MENU_BOOLEAN_TYPE 1 +typedef struct menu_boolean_s +{ + OPTION_PREAMBLE + + char *variable; /* Name of the variable to getenv()/setenv() */ + int subtype; /* Subtype (on/off, 0/1, yes/no, enable/disable), see below */ + int mutex; /* Bit mask of options to enable/disable. Bit 0 is the option + immediately following this one, bit 1 is the next one etc. + bit 7 = 0 means to disable when this option is off, + bit 7 = 1 means to disable when this option is on. + An option is disabled when the type field's upper bit is set */ +} menu_boolean_t; + +/* BOOLEAN Menu flags */ +#define MENU_BOOLEAN_ONOFF 0x01 +#define MENU_BOOLEAN_01 0x02 +#define MENU_BOOLEAN_YESNO 0x03 +#define MENU_BOOLEAN_ENDIS 0x04 +#define MENU_BOOLEAN_TYPE_MASK 0x07 + + +#define MENU_TEXT_TYPE 2 +typedef struct menu_text_s +{ + OPTION_PREAMBLE + + char *variable; /* Name of the variable to getenv()/setenv() */ + int maxchars; /* Max number of characters */ + char *charset; /* Optional charset to use */ + int flags; /* Flags - see below */ +} menu_text_t; + +/* TEXT entry menu flags */ +#define MENU_TEXT_NUMERIC 0x01 +#define MENU_TEXT_HEXADECIMAL 0x02 +#define MENU_TEXT_FREE 0x03 +#define MENU_TEXT_TYPE_MASK 0x07 + + +#define MENU_SELECTION_TYPE 3 +typedef struct menu_select_option_s +{ + char *map_from; /* Map this variable contents ... */ + char *map_to; /* ... to this menu text and vice versa */ +} menu_select_option_t; + +typedef struct menu_select_s +{ + OPTION_PREAMBLE + + int num_options; /* Number of mappings */ + menu_select_option_t **options; + /* Option list array */ +} menu_select_t; + + +#define MENU_ROUTINE_TYPE 4 +typedef void (*menu_routine_callback)(struct menu_routine_s *); + +typedef struct menu_routine_s +{ + OPTION_PREAMBLE + menu_routine_callback callback; + /* routine to be called */ + void *user_data; /* User data, don't care for system */ +} menu_routine_t; + + +#define MENU_CUSTOM_TYPE 5 +typedef void (*menu_custom_draw)(struct menu_custom_s *); +typedef void (*menu_custom_key)(struct menu_custom_s *, int); + +typedef struct menu_custom_s +{ + OPTION_PREAMBLE + menu_custom_draw drawfunc; + menu_custom_key keyfunc; + void *user_data; +} menu_custom_t; + +/* + * The menu option superstructure + */ +typedef struct menu_option_s +{ + union + { + menu_submenu_t m_sub_menu; + menu_boolean_t m_boolean; + menu_text_t m_text; + menu_select_t m_select; + menu_routine_t m_routine; + }; +} menu_option_t; + +/* Init the menu system. Returns <0 on error */ +int menu_init(menu_t *root); + +/* Execute a single menu. Returns <0 on error */ +int menu_do(menu_t *menu); + +#endif diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt index 290aed90a..391d49a11 100644 --- a/board/Marvell/common/bootseq.txt +++ b/board/Marvell/common/bootseq.txt @@ -56,7 +56,7 @@ in_flash: setup stack pointer (r1) setup GOT call cpu_init_f - debug leds + debug leds board_init_f: (common/board.c) board_early_init_f: remap gt regs? @@ -74,7 +74,7 @@ in_flash: dram_size() setup PCI slave memory mappings setup SCS - setup monitor + setup monitor alloc board info struct init bd struct relocate_code: (cpu/mpc7xxx/start.S) diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c index 3603372d0..a8add8567 100644 --- a/board/Marvell/common/flash.c +++ b/board/Marvell/common/flash.c @@ -23,7 +23,7 @@ /* * flash.c - flash support for the 512k, 8bit boot flash - and the 8MB 32bit extra flash on the DB64360 + and the 8MB 32bit extra flash on the DB64360 * most of this file was based on the existing U-Boot * flash drivers. * diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 01efbea77..6a1d4d7f5 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -145,7 +145,7 @@ void serial_puts (const char *s) } } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) void kgdb_serial_init (void) { } @@ -169,4 +169,4 @@ void kgdb_interruptible (int yes) { return; } -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile index 641a0ab86..768ccddbb 100644 --- a/board/Marvell/db64360/Makefile +++ b/board/Marvell/db64360/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2001 # Josh Huber , Mission Critical Linux, Inc. # @@ -25,30 +22,23 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a SOBJS = ../common/misc.o -COBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ +OBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ sdram_init.o ../common/intel_flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c index 923d95555..d8acd3195 100644 --- a/board/Marvell/db64360/mpsc.c +++ b/board/Marvell/db64360/mpsc.c @@ -425,7 +425,7 @@ void mpsc_sdma_init (void) (MV64360_SDMA_WIN_ACCESS_FULL << (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); -/* Setup MPSC internal address space base address */ +/* Setup MPSC internal address space base address */ GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); /* no high address remap*/ diff --git a/board/Marvell/db64360/mpsc.h b/board/Marvell/db64360/mpsc.h index 4b537eadc..f95f8c0f4 100644 --- a/board/Marvell/db64360/mpsc.h +++ b/board/Marvell/db64360/mpsc.h @@ -67,9 +67,9 @@ extern int (*mpsc_test_char)(void); #define TX_STOP 0x00010000 #define RX_ENABLE 0x00000080 -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) +#define SDMA_RX_ABORT (1 << 15) +#define SDMA_TX_ABORT (1 << 31) +#define MPSC_TX_ABORT (1 << 7) #define MPSC_RX_ABORT (1 << 23) #define MPSC_ENTER_HUNT (1 << 31) diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c index dfc0bf7d3..e5a87ad29 100644 --- a/board/Marvell/db64360/mv_eth.c +++ b/board/Marvell/db64360/mv_eth.c @@ -1391,7 +1391,7 @@ u32 mv_get_internal_sram_base (void) * port_phy_addr). * * INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct * * OUTPUT: * See description. @@ -1551,7 +1551,7 @@ static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) * ether_init_rx_desc_ring for Rx queues). * * INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct * * OUTPUT: * Ethernet port is ready to receive and transmit. @@ -1641,7 +1641,7 @@ static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) * INPUT: * ETH_PORT eth_port_num Port number. * char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. +* ETH_QUEUE queue Rx queue number for this MAC address. * * OUTPUT: * Set MAC address low and high registers. also calls eth_port_uc_addr() @@ -1679,10 +1679,10 @@ static void eth_port_uc_addr_set (ETH_PORT eth_port_num, * parameters. * * INPUT: -* ETH_PORT eth_port_num Port number. +* ETH_PORT eth_port_num Port number. * unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * This function add/removes MAC addresses from the port unicast address @@ -1761,10 +1761,10 @@ static bool eth_port_uc_addr (ETH_PORT eth_port_num, * In this case, the function calculates the CRC-8bit value and calls * eth_port_omc_addr() routine to set the Other Multicast Table. * INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_PORT eth_port_num Port number. +* unsigned char *p_addr Unicast MAC Address. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * See description. @@ -1895,10 +1895,10 @@ static void eth_port_mc_addr (ETH_PORT eth_port_num, * according to the argument given. * * INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_PORT eth_port_num Port number. +* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * See description. @@ -1959,10 +1959,10 @@ static bool eth_port_smc_addr (ETH_PORT eth_port_num, * CRC-8 argument given. * * INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_PORT eth_port_num Port number. +* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * See description. @@ -2203,7 +2203,7 @@ static bool ethernet_phy_reset (ETH_PORT eth_port_num) * eth_port_reset - Reset Ethernet port * * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and + * This routine resets the chip by aborting any SDMA engine activity and * clearing the MIB counters. The Receiver and the Transmit unit are in * idle state after this command is performed and the port is disabled. * @@ -2556,9 +2556,9 @@ static void eth_set_access_control (ETH_PORT eth_port_num, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer + * ETH_QUEUE rx_queue Number of Rx queue. + * int rx_desc_num Number of Rx descriptors + * int rx_buff_size Size of Rx buffer * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. * unsigned int rx_buff_base_addr Rx buffer memory area base addr. * @@ -2650,9 +2650,9 @@ static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer + * ETH_QUEUE tx_queue Number of Tx queue. + * int tx_desc_num Number of Tx descriptors + * int tx_buff_size Size of Tx buffer * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. * unsigned int tx_buff_base_addr Tx buffer memory area base addr. * @@ -2745,7 +2745,7 @@ static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. + * ETH_QUEUE tx_queue Number of Tx queue. * PKT_INFO *p_pkt_info User packet buffer. * * OUTPUT: @@ -2861,7 +2861,7 @@ static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. + * ETH_QUEUE tx_queue Number of Tx queue. * PKT_INFO *p_pkt_info User packet buffer. * * OUTPUT: @@ -2930,7 +2930,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * * eth_port_receive - Get received information from Rx ring. * * DESCRIPTION: - * This routine returns the received data to the caller. There is no + * This routine returns the received data to the caller. There is no * data copying during routine operation. All information is returned * using pointer to packet information struct passed from the caller. * If the routine exhausts Rx ring resources then the resource error flag @@ -2938,7 +2938,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. + * ETH_QUEUE rx_queue Number of Rx queue. * PKT_INFO *p_pkt_info User packet buffer. * * OUTPUT: @@ -2980,7 +2980,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, /* Nothing to receive... */ if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ +/* DP(printf("Rx: command_status: %08x\n", command_status)); */ D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); /* DP(printf("\nETH_END_OF_JOB ...\n"));*/ return ETH_END_OF_JOB; @@ -3019,7 +3019,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. + * ETH_QUEUE rx_queue Number of Rx queue. * PKT_INFO *p_pkt_info Information on the returned buffer. * * OUTPUT: diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c index ecadaf271..f04aaf9a6 100644 --- a/board/Marvell/db64360/sdram_init.c +++ b/board/Marvell/db64360/sdram_init.c @@ -1728,7 +1728,7 @@ long int dram_size (long int *base, long int maxsize) /* ppcboot interface function to SDRAM init - this is where all the * controlling logic happens */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; diff --git a/board/Marvell/db64360/u-boot.lds b/board/Marvell/db64360/u-boot.lds index 1a95755ab..d89eb6cff 100644 --- a/board/Marvell/db64360/u-boot.lds +++ b/board/Marvell/db64360/u-boot.lds @@ -26,6 +26,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -37,11 +38,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -125,7 +126,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile index 641a0ab86..768ccddbb 100644 --- a/board/Marvell/db64460/Makefile +++ b/board/Marvell/db64460/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2001 # Josh Huber , Mission Critical Linux, Inc. # @@ -25,30 +22,23 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a SOBJS = ../common/misc.o -COBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ +OBJS = $(BOARD).o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ sdram_init.o ../common/intel_flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c index 359b83140..b783aff8d 100644 --- a/board/Marvell/db64460/mpsc.c +++ b/board/Marvell/db64460/mpsc.c @@ -425,7 +425,7 @@ void mpsc_sdma_init (void) (MV64460_SDMA_WIN_ACCESS_FULL << (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); -/* Setup MPSC internal address space base address */ +/* Setup MPSC internal address space base address */ GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); /* no high address remap*/ diff --git a/board/Marvell/db64460/mpsc.h b/board/Marvell/db64460/mpsc.h index b8462cb68..3cc0c0f7a 100644 --- a/board/Marvell/db64460/mpsc.h +++ b/board/Marvell/db64460/mpsc.h @@ -67,9 +67,9 @@ extern int (*mpsc_test_char)(void); #define TX_STOP 0x00010000 #define RX_ENABLE 0x00000080 -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) +#define SDMA_RX_ABORT (1 << 15) +#define SDMA_TX_ABORT (1 << 31) +#define MPSC_TX_ABORT (1 << 7) #define MPSC_RX_ABORT (1 << 23) #define MPSC_ENTER_HUNT (1 << 31) diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c index 0458164ef..b2c7835a5 100644 --- a/board/Marvell/db64460/mv_eth.c +++ b/board/Marvell/db64460/mv_eth.c @@ -1390,7 +1390,7 @@ u32 mv_get_internal_sram_base (void) * port_phy_addr). * * INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct * * OUTPUT: * See description. @@ -1550,7 +1550,7 @@ static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) * ether_init_rx_desc_ring for Rx queues). * * INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct * * OUTPUT: * Ethernet port is ready to receive and transmit. @@ -1640,7 +1640,7 @@ static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) * INPUT: * ETH_PORT eth_port_num Port number. * char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. +* ETH_QUEUE queue Rx queue number for this MAC address. * * OUTPUT: * Set MAC address low and high registers. also calls eth_port_uc_addr() @@ -1678,10 +1678,10 @@ static void eth_port_uc_addr_set (ETH_PORT eth_port_num, * parameters. * * INPUT: -* ETH_PORT eth_port_num Port number. +* ETH_PORT eth_port_num Port number. * unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * This function add/removes MAC addresses from the port unicast address @@ -1760,10 +1760,10 @@ static bool eth_port_uc_addr (ETH_PORT eth_port_num, * In this case, the function calculates the CRC-8bit value and calls * eth_port_omc_addr() routine to set the Other Multicast Table. * INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_PORT eth_port_num Port number. +* unsigned char *p_addr Unicast MAC Address. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * See description. @@ -1894,10 +1894,10 @@ static void eth_port_mc_addr (ETH_PORT eth_port_num, * according to the argument given. * * INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_PORT eth_port_num Port number. +* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * See description. @@ -1958,10 +1958,10 @@ static bool eth_port_smc_addr (ETH_PORT eth_port_num, * CRC-8 argument given. * * INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_PORT eth_port_num Port number. +* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * See description. @@ -2202,7 +2202,7 @@ static bool ethernet_phy_reset (ETH_PORT eth_port_num) * eth_port_reset - Reset Ethernet port * * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and + * This routine resets the chip by aborting any SDMA engine activity and * clearing the MIB counters. The Receiver and the Transmit unit are in * idle state after this command is performed and the port is disabled. * @@ -2555,9 +2555,9 @@ static void eth_set_access_control (ETH_PORT eth_port_num, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer + * ETH_QUEUE rx_queue Number of Rx queue. + * int rx_desc_num Number of Rx descriptors + * int rx_buff_size Size of Rx buffer * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. * unsigned int rx_buff_base_addr Rx buffer memory area base addr. * @@ -2649,9 +2649,9 @@ static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer + * ETH_QUEUE tx_queue Number of Tx queue. + * int tx_desc_num Number of Tx descriptors + * int tx_buff_size Size of Tx buffer * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. * unsigned int tx_buff_base_addr Tx buffer memory area base addr. * @@ -2744,7 +2744,7 @@ static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. + * ETH_QUEUE tx_queue Number of Tx queue. * PKT_INFO *p_pkt_info User packet buffer. * * OUTPUT: @@ -2860,7 +2860,7 @@ static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. + * ETH_QUEUE tx_queue Number of Tx queue. * PKT_INFO *p_pkt_info User packet buffer. * * OUTPUT: @@ -2929,7 +2929,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * * eth_port_receive - Get received information from Rx ring. * * DESCRIPTION: - * This routine returns the received data to the caller. There is no + * This routine returns the received data to the caller. There is no * data copying during routine operation. All information is returned * using pointer to packet information struct passed from the caller. * If the routine exhausts Rx ring resources then the resource error flag @@ -2937,7 +2937,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. + * ETH_QUEUE rx_queue Number of Rx queue. * PKT_INFO *p_pkt_info User packet buffer. * * OUTPUT: @@ -2979,7 +2979,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, /* Nothing to receive... */ if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ +/* DP(printf("Rx: command_status: %08x\n", command_status)); */ D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); /* DP(printf("\nETH_END_OF_JOB ...\n"));*/ return ETH_END_OF_JOB; @@ -3018,7 +3018,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. + * ETH_QUEUE rx_queue Number of Rx queue. * PKT_INFO *p_pkt_info Information on the returned buffer. * * OUTPUT: diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c index f36f3484a..176220232 100644 --- a/board/Marvell/db64460/sdram_init.c +++ b/board/Marvell/db64460/sdram_init.c @@ -1737,7 +1737,7 @@ long int dram_size (long int *base, long int maxsize) /* ppcboot interface function to SDRAM init - this is where all the * controlling logic happens */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; diff --git a/board/Marvell/db64460/u-boot.lds b/board/Marvell/db64460/u-boot.lds index 1a95755ab..d89eb6cff 100644 --- a/board/Marvell/db64460/u-boot.lds +++ b/board/Marvell/db64460/u-boot.lds @@ -26,6 +26,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -37,11 +38,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -125,7 +126,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/RPXClassic/Makefile b/board/RPXClassic/Makefile index 19ea3ed3e..93907babe 100644 --- a/board/RPXClassic/Makefile +++ b/board/RPXClassic/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o eccx.o +OBJS = $(BOARD).o flash.o eccx.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c index 804635a4a..49cb8ad24 100644 --- a/board/RPXClassic/RPXClassic.c +++ b/board/RPXClassic/RPXClassic.c @@ -165,7 +165,7 @@ void rpxclassic_init (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index 1f9a191d4..049f9901f 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -129,7 +130,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index c33581d25..ddd4678ee 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/RPXlite/Makefile b/board/RPXlite/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/RPXlite/Makefile +++ b/board/RPXlite/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c index bca31e4c8..f37e07b92 100644 --- a/board/RPXlite/RPXlite.c +++ b/board/RPXlite/RPXlite.c @@ -102,7 +102,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c index 659d60a2d..846794df3 100644 --- a/board/RPXlite/flash.c +++ b/board/RPXlite/flash.c @@ -31,7 +31,7 @@ * are not tested. * * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? + * does not use AM29LV800 flash memory exist ? * I don't know... */ diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds index 1f9a191d4..049f9901f 100644 --- a/board/RPXlite/u-boot.lds +++ b/board/RPXlite/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -129,7 +130,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug index c33581d25..ddd4678ee 100644 --- a/board/RPXlite/u-boot.lds.debug +++ b/board/RPXlite/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/RPXlite_dw/Makefile b/board/RPXlite_dw/Makefile index cf07cf40f..d45702091 100644 --- a/board/RPXlite_dw/Makefile +++ b/board/RPXlite_dw/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c index d6fabf04e..237c58af3 100644 --- a/board/RPXlite_dw/RPXlite_dw.c +++ b/board/RPXlite_dw/RPXlite_dw.c @@ -104,7 +104,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -124,7 +124,7 @@ phys_size_t initdram (int board_type) memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ /*Disable Periodic timer A. */ - udelay(200); + udelay(200); /* perform SDRAM initializsation sequence */ diff --git a/board/RPXlite_dw/flash.c b/board/RPXlite_dw/flash.c index 41cb036bb..1cbd53719 100644 --- a/board/RPXlite_dw/flash.c +++ b/board/RPXlite_dw/flash.c @@ -31,7 +31,7 @@ * are not tested. * * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? + * does not use AM29LV800 flash memory exist ? * I don't know... */ @@ -178,8 +178,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) value = addr[0] ; switch (value & 0x00FF00FF) { - case AMD_MANUFACT: /* AMD_MANUFACT =0x00010001 in flash.h */ - info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */ + case AMD_MANUFACT: /* AMD_MANUFACT=0x00010001 in flash.h. */ + info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/ break; case FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds index 2ee12069d..a9c88f648 100644 --- a/board/RPXlite_dw/u-boot.lds +++ b/board/RPXlite_dw/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -129,7 +130,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug index f6d153763..c0cf1cb74 100644 --- a/board/RPXlite_dw/u-boot.lds.debug +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/RRvision/Makefile b/board/RRvision/Makefile index cf07cf40f..fdc6fd53e 100644 --- a/board/RRvision/Makefile +++ b/board/RRvision/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c index c0b772d72..f46bb9e8e 100644 --- a/board/RRvision/RRvision.c +++ b/board/RRvision/RRvision.c @@ -110,7 +110,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds index 9e767ee40..1d6288fea 100644 --- a/board/RRvision/u-boot.lds +++ b/board/RRvision/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -131,7 +132,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/a3000/Makefile b/board/a3000/Makefile index dcb190703..5fde36271 100644 --- a/board/a3000/Makefile +++ b/board/a3000/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c index c1eceaa2f..ab707ae97 100644 --- a/board/a3000/a3000.c +++ b/board/a3000/a3000.c @@ -38,7 +38,7 @@ int checkboard (void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long size; long new_bank0_end; @@ -82,7 +82,7 @@ static struct pci_config_table pci_a3000_config_table[] = { PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */ + PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */ pci_cfgfunc_config_device, { PCI_ENET2_IOADDR, PCI_ENET2_MEMADDR, PCI_COMMAND_IO | diff --git a/board/a3000/u-boot.lds b/board/a3000/u-boot.lds new file mode 100644 index 000000000..acb9ffda3 --- /dev/null +++ b/board/a3000/u-boot.lds @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/adder/Makefile b/board/adder/Makefile index 6b3706daa..9123a8026 100644 --- a/board/adder/Makefile +++ b/board/adder/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # Copyright (C) 2004 Arabella Software Ltd. # Yuli Barcohen # @@ -26,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o +OBJS := $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/adder/adder.c b/board/adder/adder.c index e8a5737f5..aa7815848 100644 --- a/board/adder/adder.c +++ b/board/adder/adder.c @@ -26,9 +26,6 @@ #include #include -#if defined(CONFIG_OF_LIBFDT) - #include -#endif /* * SDRAM is single Samsung K4S643232F-T70 chip (8MB) @@ -65,7 +62,7 @@ static uint sdram_table[] = { 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04 }; -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long int msize; volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; @@ -114,11 +111,3 @@ int checkboard( void ) return 0; } - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - -} -#endif diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds index 25aaa7d8f..66c324625 100644 --- a/board/adder/u-boot.lds +++ b/board/adder/u-boot.lds @@ -33,11 +33,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -112,7 +112,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/adsvix/Makefile b/board/adsvix/Makefile new file mode 100644 index 000000000..24d5d062b --- /dev/null +++ b/board/adsvix/Makefile @@ -0,0 +1,48 @@ + +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := adsvix.o pcmcia.o +SOBJS := lowlevel_init.o pxavoltage.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/adsvix/adsvix.c b/board/adsvix/adsvix.c new file mode 100644 index 000000000..c430d634e --- /dev/null +++ b/board/adsvix/adsvix.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of ADSVIX-Board */ + gd->bd->bi_arch_number = 620; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa000003c; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stderr", "serial"); + return 0; +} + + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/adsvix/config.mk b/board/adsvix/config.mk new file mode 100644 index 000000000..98be4ebe0 --- /dev/null +++ b/board/adsvix/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1700000 diff --git a/board/adsvix/lowlevel_init.S b/board/adsvix/lowlevel_init.S new file mode 100644 index 000000000..8dea71c35 --- /dev/null +++ b/board/adsvix/lowlevel_init.S @@ -0,0 +1,466 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + bic r4, r4, #MDREFR_K2FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CFG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + +setvoltage: + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/adsvix/pcmcia.c b/board/adsvix/pcmcia.c new file mode 100644 index 000000000..ba5be0139 --- /dev/null +++ b/board/adsvix/pcmcia.c @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void pcmcia_power_on(void) +{ +#if 0 + if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */ + GPCR(81) = GPIO_bit(81); + GPSR(82) = GPIO_bit(82); + } + else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */ + GPCR(81) = GPIO_bit(81); + GPCR(82) = GPIO_bit(82); + } +#else +#warning "Board will only supply 5V, wait for next HW spin for selectable power" + /* 5.0V */ + GPCR(81) = GPIO_bit(81); + GPCR(82) = GPIO_bit(82); +#endif + + udelay(300000); + + /* reset the card */ + GPSR(52) = GPIO_bit(52); + + /* enable PCMCIA */ + GPCR(83) = GPIO_bit(83); + + /* clear reset */ + udelay(10); + GPCR(52) = GPIO_bit(52); + + udelay(20000); +} + +void pcmcia_power_off(void) +{ + /* 0V */ + GPSR(81) = GPIO_bit(81); + GPSR(82) = GPIO_bit(82); + /* disable PCMCIA */ + GPSR(83) = GPIO_bit(83); +} diff --git a/board/adsvix/pxavoltage.S b/board/adsvix/pxavoltage.S new file mode 100644 index 000000000..2fe1cabd7 --- /dev/null +++ b/board/adsvix/pxavoltage.S @@ -0,0 +1,230 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define LTC1663_ADDR 0x20 + +#define LTC1663_SY 0x01 /* Sync ACK */ +#define LTC1663_SD 0x04 /* shutdown */ +#define LTC1663_BG 0x04 /* Internal Voltage Ref */ + +#define VOLT_1_55 18 /* DAC value for 1.55V */ + + .global initPXAvoltage + +@ Set the voltage to 1.55V early in the boot process so we can run +@ at a high clock speed and boot quickly. Note that this is necessary +@ because the reset button does not reset the CPU voltage, so if the +@ voltage was low (say 0.85V) then the CPU would crash without this +@ routine + +@ This routine clobbers r0-r4 + +initializei2c: + + ldr r2, =CKEN + ldr r3, [r2] + orr r3, r3, #CKEN15_PWRI2C + str r3, [r2] + + ldr r2, =PCFR + ldr r3, [r2] + orr r3, r3, #PCFR_PI2C_EN + str r3, [r2] + + /* delay for about 250msec + */ + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC0000 + +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + ldr r0, =PWRICR + ldr r1, [r0] + bic r1, r1, #(ICR_MA | ICR_START | ICR_STOP) + str r1, [r0] + + orr r1, r1, #ICR_UR + str r1, [r0] + + ldr r2, =PWRISR + ldr r3, =0x7ff + str r3, [r2] + + bic r1, r1, #ICR_UR + str r1, [r0] + + mov r1, #(ICR_GCD | ICR_SCLE) + str r1, [r0] + + orr r1, r1, #ICR_IUE + str r1, [r0] + + orr r1, r1, #ICR_FM + str r1, [r0] + + /* delay for about 1msec + */ + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC00 + +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + mov pc, lr + +sendbytei2c: + ldr r3, =PWRIDBR + str r0, [r3] + ldr r3, =PWRICR + ldr r0, [r3] + orr r0, r0, r1 + bic r0, r0, r2 + str r0, [r3] + orr r0, r0, #ICR_TB + str r0, [r3] + + mov r2, #0x100000 + +waitfortxemptyi2c: + + ldr r0, =PWRISR + ldr r1, [r0] + + /* take it from the top if we don't get empty after a while */ + subs r2, r2, #1 + moveq lr, r4 + beq initPXAvoltage + + tst r1, #ISR_ITE + + beq waitfortxemptyi2c + + orr r1, r1, #ISR_ITE + str r1, [r0] + + mov pc, lr + +initPXAvoltage: + + mov r4, lr + + bl setleds + + bl initializei2c + + bl setleds + + /* now send the real message to set the correct voltage */ + ldr r0, =LTC1663_ADDR + mov r0, r0, LSL #1 + mov r1, #ICR_START + ldr r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK) + bl sendbytei2c + + bl setleds + + mov r0, #LTC1663_BG + mov r1, #0 + mov r2, #(ICR_STOP | ICR_START) + bl sendbytei2c + + bl setleds + + ldr r0, =VOLT_1_55 + and r0, r0, #0xff + mov r1, #0 + mov r2, #(ICR_STOP | ICR_START) + bl sendbytei2c + + bl setleds + + ldr r0, =VOLT_1_55 + mov r0, r0, ASR #8 + and r0, r0, #0xff + mov r1, #ICR_STOP + mov r2, #ICR_START + bl sendbytei2c + + bl setleds + + @ delay a little for the volatage to stablize + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC0 + +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + mov pc, r4 + +setleds: + mov pc, lr + + ldr r5, =0x40e00058 + ldr r3, [r5] + bic r3, r3, #0x3 + str r3, [r5] + ldr r5, =0x40e0000c + ldr r3, [r5] + orr r3, r3, #0x00010000 + str r3, [r5] + + @ inner loop + mov r0, #0x2 +1: + + ldr r5, =0x40e00018 + mov r3, #0x00010000 + str r3, [r5] + + @ outer loop + mov r3, #0x00F00000 +2: + subs r3, r3, #1 + bne 2b + + ldr r5, =0x40e00024 + mov r3, #0x00010000 + str r3, [r5] + + @ outer loop + mov r3, #0x00F00000 +3: + subs r3, r3, #1 + bne 3b + + subs r0, r0, #1 + bne 1b + + mov pc, lr diff --git a/board/adsvix/u-boot.lds b/board/adsvix/u-boot.lds new file mode 100644 index 000000000..f0102391b --- /dev/null +++ b/board/adsvix/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/alaska/Makefile b/board/alaska/Makefile index 5297e8143..a4c1d2e9a 100644 --- a/board/alaska/Makefile +++ b/board/alaska/Makefile @@ -1,5 +1,4 @@ -# -# (C) Copyright 2003-2006 +# (C) Copyright 2003-2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +22,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o flash.o +OBJS := $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c index 49a8f712b..93874b24f 100644 --- a/board/alaska/alaska.c +++ b/board/alaska/alaska.c @@ -131,14 +131,14 @@ void setupBat (ulong size) mtspr (DBAT7U, batu); } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong size; size = dramSetup (); /* if iCache ad dCache is defined */ -#if defined(CONFIG_CMD_CACHE) +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) /* setupBat(size);*/ #endif diff --git a/board/alaska/flash.c b/board/alaska/flash.c index 715616063..383491f56 100644 --- a/board/alaska/flash.c +++ b/board/alaska/flash.c @@ -670,7 +670,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong)addr, (ulong)*addr); + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); return (2); } /* Disable interrupts which might cause a timeout here */ @@ -712,7 +712,7 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest) for (i = 0; i < WR_BLOCK; i++) if ((*dstaddr++ & 0xff) != 0xff) { printf ("not erased at %08lx (%lx)\n", - (ulong)dstaddr, (ulong)*dstaddr); + (ulong) dstaddr, *dstaddr); return (2); } diff --git a/board/alaska/u-boot.lds b/board/alaska/u-boot.lds new file mode 100644 index 000000000..889bc77d2 --- /dev/null +++ b/board/alaska/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8220/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/altera/dk1c20/Makefile b/board/altera/dk1c20/Makefile index 60ac6e6b7..9182a4ecf 100644 --- a/board/altera/dk1c20/Makefile +++ b/board/altera/dk1c20/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o misc.o -COBJS := $(BOARD).o flash.o misc.o SOBJS = vectors.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/altera/dk1c20/dk1c20.c b/board/altera/dk1c20/dk1c20.c index 46695bea9..98ee7a71c 100644 --- a/board/altera/dk1c20/dk1c20.c +++ b/board/altera/dk1c20/dk1c20.c @@ -50,12 +50,12 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (0); } -#if defined(CONFIG_CMD_IDE) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) int ide_preinit (void) { nios_pio_t *present = (nios_pio_t *) CFG_CF_PRESENT; @@ -78,4 +78,4 @@ int ide_preinit (void) return 0; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ diff --git a/board/altera/dk1c20/u-boot.lds b/board/altera/dk1c20/u-boot.lds index be7795274..8b01f45e5 100644 --- a/board/altera/dk1c20/u-boot.lds +++ b/board/altera/dk1c20/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS __bss_start = .; . = ALIGN(4); - .bss (NOLOAD) : + .bss : { *(.bss) } diff --git a/board/altera/dk1s10/Makefile b/board/altera/dk1s10/Makefile index 60ac6e6b7..9182a4ecf 100644 --- a/board/altera/dk1s10/Makefile +++ b/board/altera/dk1s10/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o misc.o -COBJS := $(BOARD).o flash.o misc.o SOBJS = vectors.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/altera/dk1s10/dk1s10.c b/board/altera/dk1s10/dk1s10.c index 64d591e71..c45e7f15d 100644 --- a/board/altera/dk1s10/dk1s10.c +++ b/board/altera/dk1s10/dk1s10.c @@ -54,7 +54,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (0); } diff --git a/board/altera/dk1s10/u-boot.lds b/board/altera/dk1s10/u-boot.lds index be7795274..8b01f45e5 100644 --- a/board/altera/dk1s10/u-boot.lds +++ b/board/altera/dk1s10/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS __bss_start = .; . = ALIGN(4); - .bss (NOLOAD) : + .bss : { *(.bss) } diff --git a/board/altera/ep1c20/Makefile b/board/altera/ep1c20/Makefile index acad2aad8..a92b25833 100644 --- a/board/altera/ep1c20/Makefile +++ b/board/altera/ep1c20/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -12,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -22,34 +22,29 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a COMOBJS := ../common/AMDLV065D.o ../common/epled.o -COBJS := $(BOARD).o $(COMOBJS) +OBJS := $(BOARD).o $(COMOBJS) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SOBJS = -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/altera/ep1c20/ep1c20.c b/board/altera/ep1c20/ep1c20.c index c5bfb85a7..29491391e 100644 --- a/board/altera/ep1c20/ep1c20.c +++ b/board/altera/ep1c20/ep1c20.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (0); } diff --git a/board/altera/ep1c20/u-boot.lds b/board/altera/ep1c20/u-boot.lds index 73dfe9d76..b99b82c82 100644 --- a/board/altera/ep1c20/u-boot.lds +++ b/board/altera/ep1c20/u-boot.lds @@ -87,7 +87,7 @@ SECTIONS * bss follows. We keep it adjacent to simplify init code. */ __bss_start = .; - .sbss (NOLOAD) : + .sbss : { *(.sbss) *(.sbss.*) @@ -95,7 +95,7 @@ SECTIONS *(.scommon) } . = ALIGN(4); - .bss (NOLOAD) : + .bss : { *(.bss) *(.bss.*) diff --git a/board/altera/ep1s10/Makefile b/board/altera/ep1s10/Makefile index acad2aad8..a92b25833 100644 --- a/board/altera/ep1s10/Makefile +++ b/board/altera/ep1s10/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -12,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -22,34 +22,29 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a COMOBJS := ../common/AMDLV065D.o ../common/epled.o -COBJS := $(BOARD).o $(COMOBJS) +OBJS := $(BOARD).o $(COMOBJS) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SOBJS = -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/altera/ep1s10/ep1s10.c b/board/altera/ep1s10/ep1s10.c index de9bf42bd..9c7e28e68 100644 --- a/board/altera/ep1s10/ep1s10.c +++ b/board/altera/ep1s10/ep1s10.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (0); } diff --git a/board/altera/ep1s10/u-boot.lds b/board/altera/ep1s10/u-boot.lds index 73dfe9d76..b99b82c82 100644 --- a/board/altera/ep1s10/u-boot.lds +++ b/board/altera/ep1s10/u-boot.lds @@ -87,7 +87,7 @@ SECTIONS * bss follows. We keep it adjacent to simplify init code. */ __bss_start = .; - .sbss (NOLOAD) : + .sbss : { *(.sbss) *(.sbss.*) @@ -95,7 +95,7 @@ SECTIONS *(.scommon) } . = ALIGN(4); - .bss (NOLOAD) : + .bss : { *(.bss) *(.bss.*) diff --git a/board/altera/ep1s40/Makefile b/board/altera/ep1s40/Makefile index acad2aad8..a92b25833 100644 --- a/board/altera/ep1s40/Makefile +++ b/board/altera/ep1s40/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -12,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -22,34 +22,29 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a COMOBJS := ../common/AMDLV065D.o ../common/epled.o -COBJS := $(BOARD).o $(COMOBJS) +OBJS := $(BOARD).o $(COMOBJS) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SOBJS = -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/altera/ep1s40/ep1s40.c b/board/altera/ep1s40/ep1s40.c index c0eca17b9..cb7555047 100644 --- a/board/altera/ep1s40/ep1s40.c +++ b/board/altera/ep1s40/ep1s40.c @@ -29,7 +29,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (0); } diff --git a/board/altera/ep1s40/u-boot.lds b/board/altera/ep1s40/u-boot.lds index 73dfe9d76..b99b82c82 100644 --- a/board/altera/ep1s40/u-boot.lds +++ b/board/altera/ep1s40/u-boot.lds @@ -87,7 +87,7 @@ SECTIONS * bss follows. We keep it adjacent to simplify init code. */ __bss_start = .; - .sbss (NOLOAD) : + .sbss : { *(.sbss) *(.sbss.*) @@ -95,7 +95,7 @@ SECTIONS *(.scommon) } . = ALIGN(4); - .bss (NOLOAD) : + .bss : { *(.bss) *(.bss.*) diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile index 064979988..5654f91a8 100644 --- a/board/amcc/bamboo/Makefile +++ b/board/amcc/bamboo/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2007 +# (C) Copyright 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o +OBJS += flash.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index f4157017f..c93ba6e3c 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005-2007 + * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -23,7 +23,6 @@ #include #include -#include #include #include #include "bamboo.h" @@ -32,170 +31,9 @@ void ext_bus_cntlr_init(void); void configure_ppc440ep_pins(void); int is_nand_selected(void); -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) -/************************************************************************* - * - * Bamboo has one bank onboard sdram (plus DIMM) - * - * Fixed memory is composed of : - * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, - * 13 row add bits, 10 column add bits (but 12 row used only). - * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, - * 12 row add bits, 10 column add bits. - * Prepare a subset (only the used ones) of SPD data - * - * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of - * the corresponding bank is divided by 2 due to number of Row addresses - * 12 in the ECC module - * - * Assumes: 64 MB, ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -const unsigned char cfg_simulate_spd_eeprom[128] = { - 0x80, /* number of SPD bytes used: 128 */ - 0x08, /* total number bytes in SPD device = 256 */ - 0x07, /* DDR ram */ -#ifdef CONFIG_DDR_ECC - 0x0C, /* num Row Addr: 12 */ -#else - 0x0D, /* num Row Addr: 13 */ -#endif - 0x09, /* numColAddr: 9 */ - 0x01, /* numBanks: 1 */ - 0x20, /* Module data width: 32 bits */ - 0x00, /* Module data width continued: +0 */ - 0x04, /* 2.5 Volt */ - 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ - 0x00, /* SDRAM Access from clock */ -#ifdef CONFIG_DDR_ECC - 0x02, /* ECC ON : 02 OFF : 00 */ -#else - 0x00, /* ECC ON : 02 OFF : 00 */ -#endif - 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */ - 0, - 0, - 0x01, /* wcsbc = 1 */ - 0, - 0, - 0x0C, /* casBit (2,2.5) */ - 0, - 0, - 0x00, /* not registered: 0 registered : 0x02*/ - 0, - 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */ - 0, - 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */ - 0, - 0x50, /* tRpNs = 20 ns */ - 0, - 0x50, /* tRcdNs = 20 ns */ - 45, /* tRasNs */ -#ifdef CONFIG_DDR_ECC - 0x08, /* bankSizeID: 32MB */ -#else - 0x10, /* bankSizeID: 64MB */ -#endif - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0 -}; -#endif +unsigned char cfg_simulate_spd_eeprom[128]; +gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; #if 0 { /* GPIO Alternate1 Alternate2 Alternate3 */ { @@ -280,86 +118,86 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { #define EBC0_BNAP_SMALL_FLASH \ EBC0_BNAP_BME_DISABLED | \ EBC0_BNAP_TWT_ENCODE(6) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(3) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(3) | \ + EBC0_BNAP_TH_ENCODE(1) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_WRITEONLY | \ EBC0_BNAP_PEN_DISABLED #define EBC0_BNCR_SMALL_FLASH_CS0 \ - EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_8BIT #define EBC0_BNCR_SMALL_FLASH_CS4 \ - EBC0_BNCR_BAS_ENCODE(0x87F00000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0x87F00000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_8BIT /* Large Flash or SRAM */ #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(8) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(1) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_RW | \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(8) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(1) | \ + EBC0_BNAP_TH_ENCODE(2) | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_RW | \ EBC0_BNAP_PEN_DISABLED -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ - EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ + EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_16BIT -#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ - EBC0_BNCR_BAS_ENCODE(0x87800000) | \ - EBC0_BNCR_BS_8MB | \ - EBC0_BNCR_BU_RW | \ +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ + EBC0_BNCR_BAS_ENCODE(0x87800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_16BIT /* NVRAM - FPGA */ #define EBC0_BNAP_NVRAM_FPGA \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(9) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(1) | \ - EBC0_BNAP_WBN_ENCODE(1) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(2) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_DELAYED | \ - EBC0_BNAP_BEM_WRITEONLY | \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(9) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(0) | \ + EBC0_BNAP_TH_ENCODE(2) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_WRITEONLY | \ EBC0_BNAP_PEN_DISABLED #define EBC0_BNCR_NVRAM_FPGA_CS5 \ - EBC0_BNCR_BAS_ENCODE(0x80000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0x80000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_8BIT /* Nand Flash */ #define EBC0_BNAP_NAND_FLASH \ - EBC0_BNAP_BME_DISABLED | \ - EBC0_BNAP_TWT_ENCODE(3) | \ - EBC0_BNAP_CSN_ENCODE(0) | \ - EBC0_BNAP_OEN_ENCODE(0) | \ - EBC0_BNAP_WBN_ENCODE(0) | \ - EBC0_BNAP_WBF_ENCODE(0) | \ - EBC0_BNAP_TH_ENCODE(1) | \ - EBC0_BNAP_RE_ENABLED | \ - EBC0_BNAP_SOR_NOT_DELAYED | \ - EBC0_BNAP_BEM_RW | \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(3) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(0) | \ + EBC0_BNAP_WBN_ENCODE(0) | \ + EBC0_BNAP_WBF_ENCODE(0) | \ + EBC0_BNAP_TH_ENCODE(1) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_NOT_DELAYED | \ + EBC0_BNAP_BEM_RW | \ EBC0_BNAP_PEN_DISABLED @@ -367,22 +205,22 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { /* NAND0 */ #define EBC0_BNCR_NAND_FLASH_CS1 \ - EBC0_BNCR_BAS_ENCODE(0x90000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0x90000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_32BIT /* NAND1 - Bank2 */ #define EBC0_BNCR_NAND_FLASH_CS2 \ - EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0x94000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_32BIT /* NAND1 - Bank3 */ #define EBC0_BNCR_NAND_FLASH_CS3 \ - EBC0_BNCR_BAS_ENCODE(0x94000000) | \ - EBC0_BNCR_BS_1MB | \ - EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BAS_ENCODE(0x94000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ EBC0_BNCR_BW_32BIT int board_early_init_f(void) @@ -438,6 +276,87 @@ int board_early_init_f(void) return 0; } +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +/*----------------------------------------------------------------------------+ + | nand_reset. + | Reset Nand flash + | This routine will abort previous cmd + +----------------------------------------------------------------------------*/ +int nand_reset(ulong addr) +{ + int wait=0, stat=0; + + out8(addr + NAND_CMD_REG, NAND0_CMD_RESET); + out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS); + + while ((stat != 0xc0) && (wait != 0xffff)) { + stat = in8(addr + NAND_DATA_REG); + wait++; + } + + if (stat == 0xc0) { + return 0; + } else { + printf("NAND Reset timeout.\n"); + return -1; + } +} + +void board_nand_set_device(int cs, ulong addr) +{ + /* Set NandFlash Core Configuration Register */ + out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24)); + + switch (cs) { + case 1: + /* ------- + * NAND0 + * ------- + * K9F1208U0A : 4 addr cyc, 1 col + 3 Row + * Set NDF1CR - Enable External CS1 in NAND FLASH controller + */ + out32(addr + NAND_CR1_REG, 0x80002222); + break; + + case 2: + /* ------- + * NAND1 + * ------- + * K9K2G0B : 5 addr cyc, 2 col + 3 Row + * Set NDF2CR : Enable External CS2 in NAND FLASH controller + */ + out32(addr + NAND_CR2_REG, 0xC0007777); + break; + } + + /* Perform Reset Command */ + if (nand_reset(addr) != 0) + return; +} + +void nand_init(void) +{ + board_nand_set_device(1, CFG_NAND_ADDR); + + nand_probe(CFG_NAND_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } + +#if 0 /* NAND1 not supported yet */ + board_nand_set_device(2, CFG_NAND2_ADDR); + + nand_probe(CFG_NAND2_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +#endif +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ + int checkboard(void) { char *s = getenv("serial#"); @@ -452,20 +371,113 @@ int checkboard(void) return (0); } - -phys_size_t initdram (int board_type) +/************************************************************************* + * + * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM) + * + * Fixed memory is composed of : + * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, + * 13 row add bits, 10 column add bits (but 12 row used only). + * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, + * 12 row add bits, 10 column add bits. + * Prepare a subset (only the used ones) of SPD data + * + * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of + * the corresponding bank is divided by 2 due to number of Row addresses + * 12 in the ECC module + * + * Assumes: 64 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +static void init_spd_array(void) { -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) - long dram_size; + cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */ + cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */ + +#ifdef CONFIG_DDR_ECC + cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */ + cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */ + cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */ +#else + cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */ + cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */ + cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */ +#endif + + cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */ + cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */ + cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */ + cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */ + cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/ + cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */ + cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */ + cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */ + cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */ + cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */ + + cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */ + + cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */ + + cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ + cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */ + cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */ + cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */ +} + +long int initdram (int board_type) +{ + long dram_size = 0; + + /* + * First write simulated values in eeprom array for onboard bank 0 + */ + init_spd_array(); dram_size = spd_sdram(); return dram_size; -#else - return CFG_MBYTES_SDRAM << 20; -#endif } +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + /************************************************************************* * pci_pre_init * @@ -478,7 +490,7 @@ phys_size_t initdram (int board_type) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -519,7 +531,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* * pci_target_init @@ -949,11 +961,11 @@ void ext_bus_cntlr_init(void) /*------------------------------------------------------------------------- */ case BOOT_FROM_NAND_FLASH0: /*------------------------------------------------------------------------- */ - ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH; - ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; + ebc0_cs0_bnap_value = 0; + ebc0_cs0_bncr_value = 0; - ebc0_cs1_bnap_value = 0; - ebc0_cs1_bncr_value = 0; + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; ebc0_cs2_bnap_value = 0; ebc0_cs2_bncr_value = 0; ebc0_cs3_bnap_value = 0; @@ -1273,7 +1285,7 @@ void uart_selection_in_fpga(uart_config_nb_t uart_config) /*----------------------------------------------------------------------------+ | init_default_gpio +----------------------------------------------------------------------------*/ -void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX]) +void init_default_gpio(void) { int i; @@ -1343,7 +1355,7 @@ void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX]) | +----------------------------------------------------------------------------*/ -void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX]) +void update_uart_ios(uart_config_nb_t uart_config) { switch (uart_config) { @@ -1471,16 +1483,16 @@ void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO /*----------------------------------------------------------------------------+ | update_ndfc_ios(void). +----------------------------------------------------------------------------*/ -void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) +void update_ndfc_ios(void) { /* Update GPIO Configuration Table */ gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */ gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1; +#if 0 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; -#if 0 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */ gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; #endif @@ -1489,7 +1501,7 @@ void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) /*----------------------------------------------------------------------------+ | update_zii_ios(void). +----------------------------------------------------------------------------*/ -void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) +void update_zii_ios(void) { /* Update GPIO Configuration Table */ gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */ @@ -1539,7 +1551,7 @@ void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) /*----------------------------------------------------------------------------+ | update_uic_0_3_irq_ios(). +----------------------------------------------------------------------------*/ -void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) +void update_uic_0_3_irq_ios(void) { gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */ gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1; @@ -1557,7 +1569,7 @@ void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) /*----------------------------------------------------------------------------+ | update_uic_4_9_irq_ios(). +----------------------------------------------------------------------------*/ -void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) +void update_uic_4_9_irq_ios(void) { gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1; @@ -1578,7 +1590,7 @@ void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) /*----------------------------------------------------------------------------+ | update_dma_a_b_ios(). +----------------------------------------------------------------------------*/ -void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) +void update_dma_a_b_ios(void) { gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */ gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2; @@ -1599,7 +1611,7 @@ void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) /*----------------------------------------------------------------------------+ | update_dma_c_d_ios(). +----------------------------------------------------------------------------*/ -void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) +void update_dma_c_d_ios(void) { gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */ gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2; @@ -1624,7 +1636,7 @@ void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) /*----------------------------------------------------------------------------+ | update_ebc_master_ios(). +----------------------------------------------------------------------------*/ -void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) +void update_ebc_master_ios(void) { gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */ gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1; @@ -1642,7 +1654,7 @@ void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) /*----------------------------------------------------------------------------+ | update_usb2_device_ios(). +----------------------------------------------------------------------------*/ -void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) +void update_usb2_device_ios(void) { gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */ gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2; @@ -1673,21 +1685,20 @@ void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) /*----------------------------------------------------------------------------+ | update_pci_patch_ios(). +----------------------------------------------------------------------------*/ -void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX]) +void update_pci_patch_ios(void) { gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; } /*----------------------------------------------------------------------------+ - | set_chip_gpio_configuration(unsigned char gpio_core, - | gpio_param_s (*gpio_tab)[GPIO_MAX]) + | set_chip_gpio_configuration(unsigned char gpio_core) | Put the core impacted by clock modification and sharing in reset. | Config the select registers to resolve the sharing depending of the config. | Configure the GPIO registers. | +----------------------------------------------------------------------------*/ -void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX]) +void set_chip_gpio_configuration(unsigned char gpio_core) { unsigned char i=0, j=0, reg_offset = 0; unsigned long gpio_reg, gpio_core_add; @@ -1841,12 +1852,11 @@ void configure_ppc440ep_pins(void) CORE_NOT_SELECTED /* PCI_PATCH */ }; - gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; /* Table Default Initialisation + FPGA Access */ - init_default_gpio(gpio_tab); - set_chip_gpio_configuration(GPIO0, gpio_tab); - set_chip_gpio_configuration(GPIO1, gpio_tab); + init_default_gpio(); + set_chip_gpio_configuration(GPIO0); + set_chip_gpio_configuration(GPIO1); /* Update Table */ force_bup_core_selection(ppc440ep_core_selection, &config_val); @@ -1881,7 +1891,7 @@ void configure_ppc440ep_pins(void) /* UIC 0:3 Selection */ if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED) { - update_uic_0_3_irq_ios(gpio_tab); + update_uic_0_3_irq_ios(); dma_a_b_unselect_in_fpga(); } @@ -1889,21 +1899,21 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL; - update_uic_4_9_irq_ios(gpio_tab); + update_uic_4_9_irq_ios(); } /* DMA AB Selection */ if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL; - update_dma_a_b_ios(gpio_tab); + update_dma_a_b_ios(); dma_a_b_selection_in_fpga(); } /* DMA CD Selection */ if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED) { - update_dma_c_d_ios(gpio_tab); + update_dma_c_d_ios(); dma_c_d_selection_in_fpga(); } @@ -1912,14 +1922,14 @@ void configure_ppc440ep_pins(void) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_ebc_master_ios(gpio_tab); + update_ebc_master_ios(); } /* PCI Patch Enable */ if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED) { sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; - update_pci_patch_ios(gpio_tab); + update_pci_patch_ios(); } /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */ @@ -1935,7 +1945,7 @@ void configure_ppc440ep_pins(void) /* USB2.0 Device Selection */ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) { - update_usb2_device_ios(gpio_tab); + update_usb2_device_ios(); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; @@ -1968,23 +1978,14 @@ void configure_ppc440ep_pins(void) /* NAND Flash Selection */ if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) { - update_ndfc_ios(gpio_tab); + update_ndfc_ios(); -#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_CHIPSELGAT_EN1 | SDR0_CUST0_CHIPSELGAT_EN2); -#else - mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | - SDR0_CUST0_NDFC_ENABLE | - SDR0_CUST0_NDFC_BW_8_BIT | - SDR0_CUST0_NDFC_ARE_MASK | - SDR0_CUST0_CHIPSELGAT_EN0 | - SDR0_CUST0_CHIPSELGAT_EN2); -#endif ndfc_selection_in_fpga(); } @@ -1997,7 +1998,7 @@ void configure_ppc440ep_pins(void) /* MII Selection */ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) { - update_zii_ios(gpio_tab); + update_zii_ios(); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; mtsdr(sdr_mfr, sdr0_mfr); @@ -2008,7 +2009,7 @@ void configure_ppc440ep_pins(void) /* RMII Selection */ if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) { - update_zii_ios(gpio_tab); + update_zii_ios(); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; mtsdr(sdr_mfr, sdr0_mfr); @@ -2019,7 +2020,7 @@ void configure_ppc440ep_pins(void) /* SMII Selection */ if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) { - update_zii_ios(gpio_tab); + update_zii_ios(); mfsdr(sdr_mfr, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; mtsdr(sdr_mfr, sdr0_mfr); @@ -2056,7 +2057,7 @@ void configure_ppc440ep_pins(void) sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; break; } - update_uart_ios(uart_configuration, gpio_tab); + update_uart_ios(uart_configuration); /* UART Selection in all cases */ uart_selection_in_fpga(uart_configuration); @@ -2078,8 +2079,8 @@ void configure_ppc440ep_pins(void) /* Perform effective access to hardware */ mtsdr(sdr_pfc1, sdr0_pfc1); - set_chip_gpio_configuration(GPIO0, gpio_tab); - set_chip_gpio_configuration(GPIO1, gpio_tab); + set_chip_gpio_configuration(GPIO0); + set_chip_gpio_configuration(GPIO1); /* USB2.0 Device Reset must be done after GPIO setting */ if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h index 447486297..1ce6366da 100644 --- a/board/amcc/bamboo/bamboo.h +++ b/board/amcc/bamboo/bamboo.h @@ -264,9 +264,19 @@ #define TRUE 1 #define FALSE 0 +#define GPIO_GROUP_MAX 2 +#define GPIO_MAX 32 +#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ +#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ +#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ +#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ +#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ + /* For the other GPIO number, you must shift */ + #define GPIO0 0 #define GPIO1 1 + /*#define MAX_SELECTION_NB CORE_NB */ #define MAX_CORE_SELECT_NB 22 diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk index b46527dcc..9d7f4c310 100644 --- a/board/amcc/bamboo/config.mk +++ b/board/amcc/bamboo/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2007 +# (C) Copyright 2002-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -21,11 +21,7 @@ # MA 02111-1307 USA # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifndef TEXT_BASE TEXT_BASE = 0xFFFA0000 -endif PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c index 8a2e832cf..a30ab7ada 100644 --- a/board/amcc/bamboo/flash.c +++ b/board/amcc/bamboo/flash.c @@ -53,7 +53,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ - {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */ + {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */ {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/ {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/ {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ @@ -134,10 +134,10 @@ unsigned long flash_init(void) flash_info[i].size = 0; /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) + if (flash_addr_table[index][i] == 0) { continue; + } - DEBUGF("Detection bank %d...\n", i); /* call flash_get_size() to initialize sector address */ size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], &flash_info[i]); diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S index f4d2ae3f4..7820107aa 100644 --- a/board/amcc/bamboo/init.S +++ b/board/amcc/bamboo/init.S @@ -1,31 +1,74 @@ /* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ #include #include -#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + /************************************************************************** * TLB TABLE @@ -37,67 +80,34 @@ * Pointer to the table is returned in r1 * *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab + + .section .bootpg,"ax" + .globl tlbtab tlbtab: - tlbtab_start + tlbtab_start - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ -#ifndef CONFIG_NAND_SPL - tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G) -#else - tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G) - tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) -#endif + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) - /* PCI base & peripherals */ - tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) - tlbentry(CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I) - tlbentry(CFG_NAND_ADDR, SZ_4K, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I) + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) - /* PCI */ - tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I) + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I ) - /* USB 2.0 Device */ - tlbentry(CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I) - - tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 0) -#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00@h - ori r5,r5,TLB00@l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01@h - ori r5,r5,TLB01@l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02@h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif + tlbtab_end diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds index 25d917a4f..176900ec2 100644 --- a/board/amcc/bamboo/u-boot.lds +++ b/board/amcc/bamboo/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -43,11 +44,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -67,7 +68,19 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/bamboo/init.o (.text) - board/amcc/bamboo/bamboo.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -132,7 +145,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) @@ -140,6 +153,8 @@ SECTIONS *(COMMON) } + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + _end = . ; PROVIDE (end = .); } diff --git a/board/amcc/bubinga/Makefile b/board/amcc/bubinga/Makefile index 1939d5168..f5bda5519 100644 --- a/board/amcc/bubinga/Makefile +++ b/board/amcc/bubinga/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index 74a2a1c21..fe6ce8a6d 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -20,12 +20,10 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +long int spd_sdram(void); #include #include -#include - -long int spd_sdram(void); int board_early_init_f(void) { @@ -36,15 +34,6 @@ int board_early_init_f(void) mtdcr(uictr, 0x00000010); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - /* - * Configure CPC0_PCI to enable PerWE as output - * and enable the internal PCI arbiter if selected - */ - if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB) - mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); - else - mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN); - return 0; } @@ -66,14 +55,30 @@ int checkboard(void) return (0); } +/* + * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! + */ +void sdram_init(void) +{ + return; +} + /* ------------------------------------------------------------------------- initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of the necessary info for SDRAM controller configuration ------------------------------------------------------------------------- */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { long int ret; ret = spd_sdram(); return ret; } + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("test: xxx MB - ok\n"); + + return (0); +} diff --git a/board/amcc/bubinga/u-boot.lds b/board/amcc/bubinga/u-boot.lds index d52b51ae1..be030923b 100644 --- a/board/amcc/bubinga/u-boot.lds +++ b/board/amcc/bubinga/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -61,6 +62,19 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -124,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c index eba0511f2..3a50b095c 100644 --- a/board/amcc/common/flash.c +++ b/board/amcc/common/flash.c @@ -35,7 +35,7 @@ #include #include -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -76,9 +76,6 @@ void flash_print_info(flash_info_t * info) case FLASH_MAN_SST: printf("SST "); break; - case FLASH_MAN_MX: - printf ("MACRONIX "); - break; default: printf("Unknown Vendor "); break; @@ -127,9 +124,6 @@ void flash_print_info(flash_info_t * info) case FLASH_STMW320DT: printf ("M29W320DT (32 M, top sector)\n"); break; - case FLASH_MXLV320T: - printf ("MXLV320T (32 Mbit, top sector)\n"); - break; default: printf("Unknown Chip Type\n"); break; @@ -223,75 +217,75 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) return (0); /* no or unknown flash */ } - value = addr2[1]; /* device ID */ + value = addr2[1]; /* device ID */ DEBUGF("\nFLASH DEVICEID: %x\n", value); switch (value) { case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: info->flash_id += FLASH_AM040; info->sector_count = 8; - info->size = 0x0080000; /* => 512 KiB */ + info->size = 0x0080000; /* => 512 ko */ break; case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: info->flash_id += FLASH_AM040; info->sector_count = 8; - info->size = 0x0080000; /* => 512 KiB */ + info->size = 0x0080000; /* => 512 ko */ break; case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: info->flash_id += FLASH_AM040; info->sector_count = 8; - info->size = 0x0080000; /* => 512 KiB */ + info->size = 0x0080000; /* => 512 ko */ break; case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: info->flash_id += FLASH_AMD016; info->sector_count = 32; - info->size = 0x00200000; /* => 2 MiB */ - break; + info->size = 0x00200000; + break; /* => 2 MB */ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: info->flash_id += FLASH_AMDLV033C; info->sector_count = 64; - info->size = 0x00400000; /* => 4 MiB */ - break; + info->size = 0x00400000; + break; /* => 4 MB */ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; - info->size = 0x00080000; /* => 512 KiB */ - break; + info->size = 0x00080000; + break; /* => 0.5 MB */ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; - info->size = 0x00080000; /* => 512 KiB */ - break; + info->size = 0x00080000; + break; /* => 0.5 MB */ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; - info->size = 0x00100000; /* => 1 MiB */ - break; + info->size = 0x00100000; + break; /* => 1 MB */ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; - info->size = 0x00100000; /* => 1 MiB */ - break; + info->size = 0x00100000; + break; /* => 1 MB */ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; - info->size = 0x00200000; /* => 2 MiB */ - break; + info->size = 0x00200000; + break; /* => 2 MB */ case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; - info->size = 0x00200000; /* => 2 MiB */ - break; + info->size = 0x00200000; + break; /* => 2 MB */ default: info->flash_id = FLASH_UNKNOWN; @@ -306,7 +300,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) info->start[i] = base + (i * 0x00010000); } else { if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ + /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; info->start[1] = base + 0x00004000; info->start[2] = base + 0x00006000; @@ -316,7 +310,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) base + (i * 0x00010000) - 0x00030000; } } else { - /* set sector offsets for top boot block type */ + /* set sector offsets for top boot block type */ i = info->sector_count - 1; info->start[i--] = base + info->size - 0x00004000; info->start[i--] = base + info->size - 0x00006000; @@ -381,7 +375,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { return flash_erase_2(info, s_first, s_last); } else { @@ -562,7 +555,6 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) { if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { return write_word_2(info, dest, data); } else { @@ -656,9 +648,6 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; - case (CFG_FLASH_WORD_SIZE) MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; default: info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; @@ -666,7 +655,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) return (0); /* no or unknown flash */ } - value = addr2[1]; /* device ID */ + value = addr2[1]; /* device ID */ DEBUGF("\nFLASH DEVICEID: %x\n", value); @@ -675,23 +664,17 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MiB */ + info->size = 0x00400000; break; /* => 4 MB */ case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; - info->size = 0x00400000; break; /* => 4 MiB */ + info->size = 0x00400000; break; /* => 4 MB */ case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: info->flash_id += FLASH_STMW320DT; info->sector_count = 67; - info->size = 0x00400000; break; /* => 4 MiB */ - - case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T: - info->flash_id += FLASH_MXLV320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ + info->size = 0x00400000; break; /* => 4 MB */ default: info->flash_id = FLASH_UNKNOWN; @@ -728,44 +711,23 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) --i; info->start[i] = base; } - } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) { - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; - info->start[i--] = base + info->size - 0x00010000; - - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; } else { if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ + /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000a000; - info->start[6] = base + 0x0000c000; - info->start[7] = base + 0x0000e000; - for (i = 8; i < info->sector_count; i++) { + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { info->start[i] = - base + ((i-7) * 0x00010000); + base + (i * 0x00010000) - 0x00030000; } } else { - /* set sector offsets for top boot block type */ + /* set sector offsets for top boot block type */ i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00002000; info->start[i--] = base + info->size - 0x00004000; info->start[i--] = base + info->size - 0x00006000; info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000a000; - info->start[i--] = base + info->size - 0x0000c000; - info->start[i--] = base + info->size - 0x0000e000; for (; i >= 0; i--) { info->start[i] = base + i * 0x00010000; } diff --git a/board/amcc/ebony/Makefile b/board/amcc/ebony/Makefile index 6ab1a26b1..4a3927be7 100644 --- a/board/amcc/ebony/Makefile +++ b/board/amcc/ebony/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index 9bcdf5997..dcafac950 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -104,7 +104,7 @@ int checkboard(void) return (0); } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { long dram_size = 0; @@ -116,6 +116,36 @@ phys_size_t initdram(int board_type) return dram_size; } +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. @@ -177,14 +207,14 @@ long int fixed_sdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) int pci_pre_init(struct pci_controller *hose) { unsigned long strap; /*--------------------------------------------------------------------------+ - * The ebony board is always configured as the host & requires the - * PCI arbiter to be enabled. + * The ebony board is always configured as the host & requires the + * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ strap = mfdcr(cpc0_strp1); if ((strap & 0x00100000) == 0) { @@ -194,7 +224,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S index c86076e80..cc8f8b444 100644 --- a/board/amcc/ebony/init.S +++ b/board/amcc/ebony/init.S @@ -22,7 +22,53 @@ #include #include -#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + /************************************************************************** * TLB TABLE @@ -35,23 +81,16 @@ * *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab + .section .bootpg,"ax" + .globl tlbtab tlbtab: - tlbtab_start - - tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X) - tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X) - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I) - tlbtab_end + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/amcc/ebony/u-boot.lds b/board/amcc/ebony/u-boot.lds index 6be4bd102..5a1c5b1af 100644 --- a/board/amcc/ebony/u-boot.lds +++ b/board/amcc/ebony/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -43,11 +44,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -67,6 +68,19 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/ebony/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -131,7 +145,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile index 6ab1a26b1..5654f91a8 100644 --- a/board/amcc/luan/Makefile +++ b/board/amcc/luan/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o +OBJS += flash.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S index d5ee117df..7830ebdfa 100644 --- a/board/amcc/luan/init.S +++ b/board/amcc/luan/init.S @@ -1,31 +1,73 @@ /* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Copyright (C) 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ #include #include -#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + /************************************************************************** * TLB TABLE @@ -38,37 +80,53 @@ * *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab + .section .bootpg,"ax" + .globl tlbtab tlbtab: - tlbtab_start + tlbtab_start - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G) +#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */ + /* large flash */ + tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) - tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) +#else /* else booting from small flash */ + tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ + tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) +#endif - /* internal ram (l2 cache) */ - tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I) + tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I ) - /* peripherals at f0000000 */ - tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I) +#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */ + tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) +#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */ + tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) +#elif (CFG_SMALL_FLASH == 0xfff00000) + tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) +#else + #error DONT KNOW SRAM LOCATION +#endif - /* PCI */ - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I) - tlbtab_end + /* internal ram (l2 cache) */ + tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I ) + + /* peripherals at f0000000 */ + tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ +#if (CONFIG_COMMANDS & CFG_CMD_PCI) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I ) +#endif + tlbtab_end diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index b14b6e1b5..06a57f6c4 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -39,7 +39,7 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ************************************************************************/ int board_early_init_f(void) { - u32 mfr; + volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; mtebc( pb0ap, 0x03800000 ); /* set chip selects */ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ @@ -66,9 +66,7 @@ int board_early_init_f(void) mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0xffffffff ); - mfsdr(sdr_mfr, mfr); - mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(sdr_mfr, mfr); + x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */ return 0; } @@ -81,18 +79,7 @@ int board_early_init_f(void) int misc_init_r(void) { volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; - - /* set modes of operation */ - x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | - EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; - /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ - x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; - - /* put Ethernet+PHY in reset */ - x->ethuart &= ~EPLD2_RESET_ETH_N; - udelay(10000); - /* take Ethernet+PHY out of reset */ - x->ethuart |= EPLD2_RESET_ETH_N; + x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */ return 0; } @@ -117,14 +104,150 @@ int checkboard(void) return 0; } -/* - * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -u32 ddr_clktr(u32 default_val) { - return (SDRAM_CLKTR_CLKP_180_DEG_ADV); + +/************************************************************************* + * long int fixed_sdram() + * + ************************************************************************/ +static long int fixed_sdram(void) +{ /* DDR2 init from BDI2000 script */ + mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */ + mtdcr( 0x11, 0x84000000 ); + mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */ + mtdcr( 0x11, 0x2D122000 ); + mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */ + mtdcr( 0x11, 0x00800026 ); + mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */ + mtdcr( 0x11, 0x82000800 ); + mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */ + mtdcr( 0x11, 0x80000000 ); + mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */ + mtdcr( 0x11, 0x00000201 ); + mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */ + mtdcr( 0x11, 0x00000201 ); + mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */ + mtdcr( 0x11, 0x08200000 ); + mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */ + mtdcr( 0x11, 0x80201000 ); + mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */ + mtdcr( 0x11, 0x42103242 ); + mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */ + mtdcr( 0x11, 0x0C100D14 ); + mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */ + mtdcr( 0x11, 0x00000642 ); + mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */ + mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */ + + mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */ + mtdcr( 0x11, 0x81b80000 ); + mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */ + mtdcr( 0x11, 0x82100400 ); + mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */ + mtdcr( 0x11, 0x80820000 ); + mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */ + mtdcr( 0x11, 0x80830000 ); + mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */ + mtdcr( 0x11, 0x80810000 ); + mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */ + mtdcr( 0x11, 0x80800542 ); + mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */ + mtdcr( 0x11, 0x82100400 ); + mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */ + mtdcr( 0x11, 0x80800442 ); + mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */ + mtdcr( 0x11, 0x80810380 ); + mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */ + mtdcr( 0x11, 0x80810000 ); + udelay( 10*1000 ); + + mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */ + mtdcr( 0x11, 0x28000000 ); /* set DC_EN */ + udelay( 100*1000 ); + + mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */ + mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */ + + mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */ + mtdcr( 0x11, 0x00000000 ); + mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */ + mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */ + mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */ + mtdcr( 0x11, 0x00000200 ); + + return 512 << 20; } + +/************************************************************************* + * long int initdram + * + ************************************************************************/ +long int initdram( int board_type ) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (0); +#else + dram_size = fixed_sdram (); +#endif + + return dram_size; +} + + +/************************************************************************* + * int testdram() + * + ************************************************************************/ +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *) 0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + + return 0; +} +#endif + + /************************************************************************* * pci_pre_init * @@ -137,7 +260,7 @@ u32 ddr_clktr(u32 default_val) { * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) int pci_pre_init( struct pci_controller *hose ) { unsigned long strap; @@ -155,7 +278,7 @@ int pci_pre_init( struct pci_controller *hose ) return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds index 791178517..d122f499f 100644 --- a/board/amcc/luan/u-boot.lds +++ b/board/amcc/luan/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -43,11 +44,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -67,6 +68,19 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/luan/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -131,7 +145,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/amcc/ocotea/Makefile b/board/amcc/ocotea/Makefile index 6ab1a26b1..af223d2c5 100644 --- a/board/amcc/ocotea/Makefile +++ b/board/amcc/ocotea/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend *~ ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S index d211c710b..e33427a10 100644 --- a/board/amcc/ocotea/init.S +++ b/board/amcc/ocotea/init.S @@ -1,28 +1,74 @@ /* - * Copyright (C) 2002 Scott McNutt - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ +* Copyright (C) 2002 Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ #include #include -#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + /************************************************************************** * TLB TABLE @@ -35,23 +81,17 @@ * *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab + .section .bootpg,"ax" + .globl tlbtab tlbtab: - tlbtab_start - - tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X) - tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X) - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I) - tlbtab_end + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index eea1e1e17..3f6d2042d 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -201,7 +201,7 @@ int checkboard (void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long dram_size = 0; @@ -214,6 +214,36 @@ phys_size_t initdram (int board_type) } +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + #if !defined(CONFIG_SPD_EEPROM) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. @@ -276,7 +306,7 @@ long int fixed_sdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -293,7 +323,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds index 298aba82d..316fee88c 100644 --- a/board/amcc/ocotea/u-boot.lds +++ b/board/amcc/ocotea/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -43,11 +44,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -67,6 +68,19 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/ocotea/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -131,7 +145,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/amcc/walnut/Makefile b/board/amcc/walnut/Makefile index 1939d5168..f5bda5519 100644 --- a/board/amcc/walnut/Makefile +++ b/board/amcc/walnut/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/amcc/walnut/u-boot.lds b/board/amcc/walnut/u-boot.lds index 5d07e4438..1dcbab5a2 100644 --- a/board/amcc/walnut/u-boot.lds +++ b/board/amcc/walnut/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -61,6 +62,19 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -125,7 +139,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c index 28dcb66eb..292e02609 100644 --- a/board/amcc/walnut/walnut.c +++ b/board/amcc/walnut/walnut.c @@ -85,11 +85,27 @@ int checkboard(void) return (0); } +/* + * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! + */ +void sdram_init(void) +{ + return; +} + /* * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of * the necessary info for SDRAM controller configuration */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { return spd_sdram(); } + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("test: xxx MB - ok\n"); + + return (0); +} diff --git a/board/amcc/yellowstone/Makefile b/board/amcc/yellowstone/Makefile new file mode 100644 index 000000000..47116d367 --- /dev/null +++ b/board/amcc/yellowstone/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/yellowstone/config.mk b/board/amcc/yellowstone/config.mk new file mode 100644 index 000000000..4ab0ea008 --- /dev/null +++ b/board/amcc/yellowstone/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/yellowstone/init.S b/board/amcc/yellowstone/init.S new file mode 100644 index 000000000..425ad0868 --- /dev/null +++ b/board/amcc/yellowstone/init.S @@ -0,0 +1,112 @@ +/* +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/amcc/yellowstone/u-boot.lds b/board/amcc/yellowstone/u-boot.lds new file mode 100644 index 000000000..a0ba44de8 --- /dev/null +++ b/board/amcc/yellowstone/u-boot.lds @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/yellowstone/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c new file mode 100644 index 000000000..92dc9d4c0 --- /dev/null +++ b/board/amcc/yellowstone/yellowstone.c @@ -0,0 +1,554 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +int board_early_init_f(void) +{ + register uint reg; + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + mtdcr(ebccfga, xbcfg); + reg = mfdcr(ebccfgd); + mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + + mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ + mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */ + + mtebc(pb1ap, 0x00000000); + mtebc(pb1cr, 0x00000000); + + mtebc(pb2ap, 0x04814500); + /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ + + mtebc(pb3ap, 0x00000000); + mtebc(pb3cr, 0x00000000); + + mtebc(pb4ap, 0x00000000); + mtebc(pb4cr, 0x00000000); + + mtebc(pb5ap, 0x00000000); + mtebc(pb5cr, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + /*CPLD cs */ + /*setup Address lines for flash size 64Meg. */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000); + + /*setup emac */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); + out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); + + /*UART1 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); + out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); + + /* external interrupts IRQ0...3 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); + out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); + +#if 0 /* test-only */ + /*setup USB 2.0 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); + out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); +#endif + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /*-------------------------------------------------------------------- + * Setup other serial configuration + *-------------------------------------------------------------------*/ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + + /*clear tmrclk divisor */ + *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; + + /*enable ethernet */ + *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; + +#if 0 /* test-only */ + /*enable usb 1.1 fs device and remove usb 2.0 reset */ + *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; +#endif + + /*get rid of flash write protect */ + *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; + + return 0; +} + +int misc_init_r (void) +{ + uint pbcr; + int size_val = 0; + + /* Re-do sizing to get full correct info */ + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtdcr(ebccfga, pb0cr); + mtdcr(ebccfgd, pbcr); + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * sdram_init -- doesn't use serial presence detect. + * + * Assumes: 256 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +#define NUM_TRIES 64 +#define NUM_READS 10 + +void sdram_tr1_set(int ram_address, int* tr1_value) +{ + int i; + int j, k; + volatile unsigned int* ram_pointer = (unsigned int*)ram_address; + int first_good = -1, last_bad = 0x1ff; + + unsigned long test[NUM_TRIES] = { + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; + + /* go through all possible SDRAM0_TR1[RDCT] values */ + for (i=0; i<=0x1ff; i++) { + /* set the current value for TR1 */ + mtsdram(mem_tr1, (0x80800800 | i)); + + /* write values */ + for (j=0; j PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Bamboo is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * hw_watchdog_reset + * + * This routine is called to reset (keep alive) the watchdog timer + * + ************************************************************************/ +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + +} +#endif diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile index b93f2c389..47116d367 100644 --- a/board/amcc/yosemite/Makefile +++ b/board/amcc/yosemite/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o +OBJS = $(BOARD).o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/amcc/yosemite/u-boot.lds b/board/amcc/yosemite/u-boot.lds index c12aad7e3..a9a7b0af6 100644 --- a/board/amcc/yosemite/u-boot.lds +++ b/board/amcc/yosemite/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -43,11 +44,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -67,6 +68,19 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/yosemite/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -131,7 +145,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 05be40acd..7f2e71820 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -1,6 +1,4 @@ /* - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -24,10 +22,7 @@ #include #include #include -#include #include -#include -#include DECLARE_GLOBAL_DATA_PTR; @@ -44,6 +39,24 @@ int board_early_init_f(void) reg = mfdcr(ebccfgd); mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ + mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */ + + mtebc(pb1ap, 0x00000000); + mtebc(pb1cr, 0x00000000); + + mtebc(pb2ap, 0x04814500); + /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ + + mtebc(pb3ap, 0x00000000); + mtebc(pb3cr, 0x00000000); + + mtebc(pb4ap, 0x00000000); + mtebc(pb4cr, 0x00000000); + + mtebc(pb5ap, 0x00000000); + mtebc(pb5cr, 0x00000000); + /*-------------------------------------------------------------------- * Setup the GPIO pins *-------------------------------------------------------------------*/ @@ -70,14 +83,12 @@ int board_early_init_f(void) out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00); out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); -#ifdef CONFIG_440EP /*setup USB 2.0 */ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); -#endif /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -112,10 +123,8 @@ int board_early_init_f(void) /*enable ethernet */ *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; -#ifdef CONFIG_440EP /*enable usb 1.1 fs device and remove usb 2.0 reset */ *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; -#endif /*get rid of flash write protect */ *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; @@ -177,19 +186,8 @@ int misc_init_r (void) int checkboard(void) { char *s = getenv("serial#"); - u8 rev; - u8 val; -#ifdef CONFIG_440EP printf("Board: Yosemite - AMCC PPC440EP Evaluation Board"); -#else - printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); -#endif - - rev = in_8((void *)(CFG_BCSR_BASE + 0)); - val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN; - printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); - if (s != NULL) { puts(", serial# "); puts(s); @@ -200,7 +198,7 @@ int checkboard(void) } /************************************************************************* - * initdram -- doesn't use serial presence detect. + * sdram_init -- doesn't use serial presence detect. * * Assumes: 256 MB, ECC, non-registered * PLB @ 133 MHz @@ -281,7 +279,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -phys_size_t initdram(int board) +void sdram_init(void) { register uint reg; int tr1_bank1, tr1_bank2; @@ -327,11 +325,57 @@ phys_size_t initdram(int board) sdram_tr1_set(0x00000000, &tr1_bank1); sdram_tr1_set(0x08000000, &tr1_bank2); - mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800)); + mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) ); +} +/************************************************************************* + * long int initdram + * + ************************************************************************/ +long int initdram(int board) +{ + sdram_init(); return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */ } +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + /************************************************************************* * pci_pre_init * @@ -344,7 +388,7 @@ phys_size_t initdram(int board) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -385,7 +429,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* * pci_target_init @@ -504,9 +548,3 @@ void hw_watchdog_reset(void) } #endif - -void board_reset(void) -{ - /* give reset to BCSR */ - *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; -} diff --git a/board/amcc/yucca/Makefile b/board/amcc/yucca/Makefile index 0ff522c31..c85fa3107 100644 --- a/board/amcc/yucca/Makefile +++ b/board/amcc/yucca/Makefile @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o cmd_yucca.o +OBJS = $(BOARD).o flash.o cmd_yucca.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend *~ ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index 67e8f8f3a..cb2893668 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -1,7 +1,4 @@ /* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * * Copyright (C) 2002 Scott McNutt * * See file CREDITS for list of people who contributed to this @@ -22,10 +19,56 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +/* port to AMCC 440SPE evaluatioon board - SG April 12,2005 */ #include #include -#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID )) +#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn)) +#define TLB2(a) ((a) & 0x00000fbf) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ;\ +0: mflr r0 ;\ + mtlr r1 ;\ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) /************************************************************************** * TLB TABLE @@ -39,83 +82,23 @@ *************************************************************************/ .section .bootpg,"ax" + .globl tlbtab -/************************************************************************** - * TLB table for revA - *************************************************************************/ - .globl tlbtabA -tlbtabA: +tlbtab: tlbtab_start + tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G) - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ + tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) - tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) + tlbentry(CFG_FPGA_BASE,SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) - tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_OPER_FLASH,SZ_16M,0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - - tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbtab_end - -/************************************************************************** - * TLB table for revB - * - * Notice: revB of the 440SPe chip is very strict about PLB real addresses - * and ranges to be mapped for config space: it seems to only work with - * d_nnnn_nnnn range (hangs the core upon config transaction attempts when - * set otherwise) while revA uses c_nnnn_nnnn. - *************************************************************************/ - .globl tlbtabB -tlbtabB: - tlbtab_start - - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G) - - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR(2) detection - * routine. - */ - - tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) - tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) - - tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) - - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - - tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbtab_end diff --git a/board/amcc/yucca/u-boot.lds b/board/amcc/yucca/u-boot.lds index 4477cd8a8..9df4f925c 100644 --- a/board/amcc/yucca/u-boot.lds +++ b/board/amcc/yucca/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -67,6 +68,19 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/yucca/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -131,7 +145,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/amcc/yucca/u-boot.lds.debug b/board/amcc/yucca/u-boot.lds.debug new file mode 100644 index 000000000..474f92216 --- /dev/null +++ b/board/amcc/yucca/u-boot.lds.debug @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/yucca/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 660889365..ce1312cf7 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -21,23 +21,24 @@ * MA 02111-1307 USA * * Port to AMCC-440SPE Evaluation Board SOP - April 2005 - * - * PCIe supporting routines derived from Linux 440SPe PCIe driver. */ #include #include -#include #include -#include -#include - +#include #include "yucca.h" -DECLARE_GLOBAL_DATA_PTR; - void fpga_init (void); +void get_sys_info(PPC440_SYS_INFO *board_cfg ); +int compare_to_true(char *str ); +char *remove_l_w_space(char *in_str ); +char *remove_t_w_space(char *in_str ); +int get_console_port(void); +unsigned long ppcMfcpr(unsigned long cpr_reg); +unsigned long ppcMfsdr(unsigned long sdr_reg); + #define DEBUG_ENV #ifdef DEBUG_ENV #define DEBUGF(fmt,args...) printf(fmt ,##args) @@ -209,7 +210,7 @@ int board_early_init_f (void) | +-------------------------------------------------------------------*/ /* Read Pin Strap Register in PPC440SP */ - mfsdr(SDR0_PINSTP, sdr0_pinstp); + sdr0_pinstp = ppcMfsdr(SDR0_PINSTP); bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK; switch (bootstrap_settings) { @@ -234,7 +235,7 @@ int board_early_init_f (void) * Boot Settings in IIC EEprom address 0x50 or 0x54 * Read Serial Device Strap Register1 in PPC440SPe */ - mfsdr(SDR0_SDSTP1, sdr0_sdstp1); + sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1); boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK; ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK; @@ -529,10 +530,10 @@ int board_early_init_f (void) mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ - mfsdr(sdr_mfr, mfr); - mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(sdr_mfr, mfr); - + /* SDR0_MFR should be part of Ethernet init */ + mfsdr (sdr_mfr, mfr); + mfr &= ~SDR0_MFR_ECS_MASK; + /*mtsdr(sdr_mfr, mfr);*/ fpga_init(); return 0; @@ -552,40 +553,290 @@ int checkboard (void) return 0; } -/* - * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -static int ppc440spe_rev_a(void) +static long int yucca_probe_for_dimms(void) { - if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA)) - return 1; - else - return 0; + long int dimm_installed[MAXDIMMS]; + long int dimm_num, probe_result; + long int dimms_found = 0; + uchar dimm_addr = IIC0_DIMM0_ADDR; + + for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { + /* check if there is a chip at the dimm address */ + switch (dimm_num) { + case 0: + dimm_addr = IIC0_DIMM0_ADDR; + break; + case 1: + dimm_addr = IIC0_DIMM1_ADDR; + break; + } + probe_result = i2c_probe(dimm_addr); + + if (probe_result == 0) { + dimm_installed[dimm_num] = TRUE; + dimms_found++; + debug("DIMM slot %d: DDR2 SDRAM detected\n",dimm_num); + } else { + dimm_installed[dimm_num] = FALSE; + debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num); + } + } + + if (dimms_found == 0) { + printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); + hang(); + } + + if (dimm_installed[0] != TRUE) { + printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n"); + printf(" Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n"); + hang(); + } + + return dimms_found; } -u32 ddr_wrdtr(u32 default_val) { - /* - * Yucca boards with 440SPe rev. A need a slightly different setup - * for the MCIF0_WRDTR register. - */ - if (ppc440spe_rev_a()) - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV); +/************************************************************************* + * init SDRAM controller with fixed value + * the initialization values are for 2x MICRON DDR2 + * PN: MT18HTF6472DY-53EB2 + * 512MB, DDR2, 533, CL4, ECC, REG + ************************************************************************/ +static long int fixed_sdram(void) +{ + long int yucca_dimms = 0; - return default_val; + yucca_dimms = yucca_probe_for_dimms(); + + /* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT */ + mtdcr( 0x10, 0x00000021 ); + mtdcr( 0x11, 0x84000000 ); + + /* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2 */ + mtdcr( 0x10, 0x00000020 ); + mtdcr( 0x11, 0x2D122000 ); + + /* SET MCIF0_CODT Die Termination On */ + mtdcr( 0x10, 0x00000026 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x2A800021 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x02800021 ); + + /* On-Die Termination for Bank 0 */ + mtdcr( 0x10, 0x00000022 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x18000000 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x06000000 ); + + /* On-Die Termination for Bank 1 */ + mtdcr( 0x10, 0x00000023 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x18000000 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x01800000 ); + + /* On-Die Termination for Bank 2 */ + mtdcr( 0x10, 0x00000024 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x01800000 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x00000000 ); + + /* On-Die Termination for Bank 3 */ + mtdcr( 0x10, 0x00000025 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x01800000 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x00000000 ); + + /* Refresh Time register (0x30) Refresh every 7.8125uS */ + mtdcr( 0x10, 0x00000030 ); + mtdcr( 0x11, 0x08200000 ); + + /* SET MCIF0_MMODE CL 4 */ + mtdcr( 0x10, 0x00000088 ); + mtdcr( 0x11, 0x00000642 ); + + /* MCIF0_MEMODE */ + mtdcr( 0x10, 0x00000089 ); + mtdcr( 0x11, 0x00000004 ); + + /*SET MCIF0_MB0CF */ + mtdcr( 0x10, 0x00000040 ); + mtdcr( 0x11, 0x00000201 ); + + /* SET MCIF0_MB1CF */ + mtdcr( 0x10, 0x00000044 ); + mtdcr( 0x11, 0x00000201 ); + + /* SET MCIF0_MB2CF */ + mtdcr( 0x10, 0x00000048 ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x00000201 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x00000000 ); + + /* SET MCIF0_MB3CF */ + mtdcr( 0x10, 0x0000004c ); + if (yucca_dimms == 2) + mtdcr( 0x11, 0x00000201 ); + else if (yucca_dimms == 1) + mtdcr( 0x11, 0x00000000 ); + + /* SET MCIF0_INITPLR0 # NOP */ + mtdcr( 0x10, 0x00000050 ); + mtdcr( 0x11, 0xB5380000 ); + + /* SET MCIF0_INITPLR1 # PRE */ + mtdcr( 0x10, 0x00000051 ); + mtdcr( 0x11, 0x82100400 ); + + /* SET MCIF0_INITPLR2 # EMR2 */ + mtdcr( 0x10, 0x00000052 ); + mtdcr( 0x11, 0x80820000 ); + + /* SET MCIF0_INITPLR3 # EMR3 */ + mtdcr( 0x10, 0x00000053 ); + mtdcr( 0x11, 0x80830000 ); + + /* SET MCIF0_INITPLR4 # EMR DLL ENABLE */ + mtdcr( 0x10, 0x00000054 ); + mtdcr( 0x11, 0x80810000 ); + + /* SET MCIF0_INITPLR5 # MR DLL RESET */ + mtdcr( 0x10, 0x00000055 ); + mtdcr( 0x11, 0x80800542 ); + + /* SET MCIF0_INITPLR6 # PRE */ + mtdcr( 0x10, 0x00000056 ); + mtdcr( 0x11, 0x82100400 ); + + /* SET MCIF0_INITPLR7 # Refresh */ + mtdcr( 0x10, 0x00000057 ); + mtdcr( 0x11, 0x8A080000 ); + + /* SET MCIF0_INITPLR8 # Refresh */ + mtdcr( 0x10, 0x00000058 ); + mtdcr( 0x11, 0x8A080000 ); + + /* SET MCIF0_INITPLR9 # Refresh */ + mtdcr( 0x10, 0x00000059 ); + mtdcr( 0x11, 0x8A080000 ); + + /* SET MCIF0_INITPLR10 # Refresh */ + mtdcr( 0x10, 0x0000005A ); + mtdcr( 0x11, 0x8A080000 ); + + /* SET MCIF0_INITPLR11 # MR */ + mtdcr( 0x10, 0x0000005B ); + mtdcr( 0x11, 0x80800442 ); + + /* SET MCIF0_INITPLR12 # EMR OCD Default*/ + mtdcr( 0x10, 0x0000005C ); + mtdcr( 0x11, 0x80810380 ); + + /* SET MCIF0_INITPLR13 # EMR OCD Exit */ + mtdcr( 0x10, 0x0000005D ); + mtdcr( 0x11, 0x80810000 ); + + /* 0x80: Adv Addr clock by 180 deg */ + mtdcr( 0x10, 0x00000080 ); + mtdcr( 0x11, 0x80000000 ); + + /* 0x21: Exit self refresh, set DC_EN */ + mtdcr( 0x10, 0x00000021 ); + mtdcr( 0x11, 0x28000000 ); + + /* 0x81: Write DQS Adv 90 + Fractional DQS Delay */ + mtdcr( 0x10, 0x00000081 ); + mtdcr( 0x11, 0x80000800 ); + + /* MCIF0_SDTR1 */ + mtdcr( 0x10, 0x00000085 ); + mtdcr( 0x11, 0x80201000 ); + + /* MCIF0_SDTR2 */ + mtdcr( 0x10, 0x00000086 ); + mtdcr( 0x11, 0x42103242 ); + + /* MCIF0_SDTR3 */ + mtdcr( 0x10, 0x00000087 ); + mtdcr( 0x11, 0x0C100D14 ); + + /* SET MQ0_B0BAS base addr 00000000 / 256MB */ + mtdcr( 0x40, 0x0000F800 ); + + /* SET MQ0_B1BAS base addr 10000000 / 256MB */ + mtdcr( 0x41, 0x0400F800 ); + + /* SET MQ0_B2BAS base addr 20000000 / 256MB */ + if (yucca_dimms == 2) + mtdcr( 0x42, 0x0800F800 ); + else if (yucca_dimms == 1) + mtdcr( 0x42, 0x00000000 ); + + /* SET MQ0_B3BAS base addr 30000000 / 256MB */ + if (yucca_dimms == 2) + mtdcr( 0x43, 0x0C00F800 ); + else if (yucca_dimms == 1) + mtdcr( 0x43, 0x00000000 ); + + /* SDRAM_RQDC */ + mtdcr( 0x10, 0x00000070 ); + mtdcr( 0x11, 0x8000003F ); + + /* SDRAM_RDCC */ + mtdcr( 0x10, 0x00000078 ); + mtdcr( 0x11, 0x80000000 ); + + /* SDRAM_RFDC */ + mtdcr( 0x10, 0x00000074 ); + mtdcr( 0x11, 0x00000220 ); + + return (yucca_dimms * 512) << 20; } -u32 ddr_clktr(u32 default_val) { - /* - * Yucca boards with 440SPe rev. A need a slightly different setup - * for the MCIF0_CLKTR register. - */ - if (ppc440spe_rev_a()) - return (SDRAM_CLKTR_CLKP_180_DEG_ADV); +long int initdram (int board_type) +{ + long dram_size = 0; - return default_val; + dram_size = fixed_sdram(); + + return dram_size; } +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x08000000; + uint *p; + + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + return 0; +} +#endif + /************************************************************************* * pci_pre_init * @@ -598,7 +849,7 @@ u32 ddr_clktr(u32 default_val) { * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -615,7 +866,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* * pci_target_init @@ -628,6 +879,8 @@ int pci_pre_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { + DECLARE_GLOBAL_DATA_PTR; + /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ @@ -655,7 +908,6 @@ void pci_target_init(struct pci_controller * hose ) } #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ -#if defined(CONFIG_PCI) /************************************************************************* * is_pci_host * @@ -671,209 +923,12 @@ void pci_target_init(struct pci_controller * hose ) * * ************************************************************************/ +#if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { /* The yucca board is always configured as host. */ return 1; } - -int yucca_pcie_card_present(int port) -{ - u16 reg; - - reg = in_be16((u16 *)FPGA_REG1C); - switch(port) { - case 0: - return !(reg & FPGA_REG1C_PE0_PRSNT); - case 1: - return !(reg & FPGA_REG1C_PE1_PRSNT); - case 2: - return !(reg & FPGA_REG1C_PE2_PRSNT); - default: - return 0; - } -} - -/* - * For the given slot, set rootpoint mode, send power to the slot, - * turn on the green LED and turn off the yellow LED, enable the clock - * and turn off reset. - */ -void yucca_setup_pcie_fpga_rootpoint(int port) -{ - u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; - - switch(port) { - case 0: - rootpoint = FPGA_REG1C_PE0_ROOTPOINT; - endpoint = 0; - power = FPGA_REG1A_PE0_PWRON; - green_led = FPGA_REG1A_PE0_GLED; - clock = FPGA_REG1A_PE0_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE0_YLED; - reset_off = FPGA_REG1C_PE0_PERST; - break; - case 1: - rootpoint = 0; - endpoint = FPGA_REG1C_PE1_ENDPOINT; - power = FPGA_REG1A_PE1_PWRON; - green_led = FPGA_REG1A_PE1_GLED; - clock = FPGA_REG1A_PE1_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE1_YLED; - reset_off = FPGA_REG1C_PE1_PERST; - break; - case 2: - rootpoint = 0; - endpoint = FPGA_REG1C_PE2_ENDPOINT; - power = FPGA_REG1A_PE2_PWRON; - green_led = FPGA_REG1A_PE2_GLED; - clock = FPGA_REG1A_PE2_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE2_YLED; - reset_off = FPGA_REG1C_PE2_PERST; - break; - - default: - return; - } - - out_be16((u16 *)FPGA_REG1A, - ~(power | clock | green_led) & - (yellow_led | in_be16((u16 *)FPGA_REG1A))); - - out_be16((u16 *)FPGA_REG1C, - ~(endpoint | reset_off) & - (rootpoint | in_be16((u16 *)FPGA_REG1C))); - /* - * Leave device in reset for a while after powering on the - * slot to give it a chance to initialize. - */ - udelay(250 * 1000); - - out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C)); -} -/* - * For the given slot, set endpoint mode, send power to the slot, - * turn on the green LED and turn off the yellow LED, enable the clock - * .In end point mode reset bit is read only. - */ -void yucca_setup_pcie_fpga_endpoint(int port) -{ - u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; - - switch(port) { - case 0: - rootpoint = FPGA_REG1C_PE0_ROOTPOINT; - endpoint = 0; - power = FPGA_REG1A_PE0_PWRON; - green_led = FPGA_REG1A_PE0_GLED; - clock = FPGA_REG1A_PE0_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE0_YLED; - reset_off = FPGA_REG1C_PE0_PERST; - break; - case 1: - rootpoint = 0; - endpoint = FPGA_REG1C_PE1_ENDPOINT; - power = FPGA_REG1A_PE1_PWRON; - green_led = FPGA_REG1A_PE1_GLED; - clock = FPGA_REG1A_PE1_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE1_YLED; - reset_off = FPGA_REG1C_PE1_PERST; - break; - case 2: - rootpoint = 0; - endpoint = FPGA_REG1C_PE2_ENDPOINT; - power = FPGA_REG1A_PE2_PWRON; - green_led = FPGA_REG1A_PE2_GLED; - clock = FPGA_REG1A_PE2_REFCLK_ENABLE; - yellow_led = FPGA_REG1A_PE2_YLED; - reset_off = FPGA_REG1C_PE2_PERST; - break; - - default: - return; - } - - out_be16((u16 *)FPGA_REG1A, - ~(power | clock | green_led) & - (yellow_led | in_be16((u16 *)FPGA_REG1A))); - - out_be16((u16 *)FPGA_REG1C, - ~(rootpoint | reset_off) & - (endpoint | in_be16((u16 *)FPGA_REG1C))); -} - -static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; - -void pcie_setup_hoses(int busno) -{ - struct pci_controller *hose; - int i, bus; - int ret = 0; - char *env; - unsigned int delay; - - /* - * assume we're called after the PCIX hose is initialized, which takes - * bus ID 0 and therefore start numbering PCIe's from 1. - */ - bus = busno; - for (i = 0; i <= 2; i++) { - /* Check for yucca card presence */ - if (!yucca_pcie_card_present(i)) - continue; - - if (is_end_point(i)) { - yucca_setup_pcie_fpga_endpoint(i); - ret = ppc4xx_init_pcie_endport(i); - } else { - yucca_setup_pcie_fpga_rootpoint(i); - ret = ppc4xx_init_pcie_rootport(i); - } - if (ret) { - printf("PCIE%d: initialization as %s failed\n", i, - is_end_point(i) ? "endpoint" : "root-complex"); - continue; - } - - hose = &pcie_hose[i]; - hose->first_busno = bus; - hose->last_busno = bus; - hose->current_busno = bus; - - /* setup mem resource */ - pci_set_region(hose->regions + 0, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMSIZE, - PCI_REGION_MEM); - hose->region_count = 1; - pci_register_hose(hose); - - if (is_end_point(i)) { - ppc4xx_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ - } else { - ppc4xx_setup_pcie_rootpoint(hose, i); - env = getenv("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul(env, NULL, 10); - if (delay > 5) - printf("Warning, expect noticable delay before " - "PCIe scan due to 'pciscandelay' value!\n"); - mdelay(delay * 1000); - } - - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; - } - } -} #endif /* defined(CONFIG_PCI) */ int misc_init_f (void) @@ -1000,3 +1055,42 @@ int onboard_pci_arbiter_selected(int core_pci) #endif return (BOARD_OPTION_NOT_SELECTED); } + +/*---------------------------------------------------------------------------+ + | ppcMfcpr. + +---------------------------------------------------------------------------*/ +unsigned long ppcMfcpr(unsigned long cpr_reg) +{ + unsigned long msr; + unsigned long cpr_cfgaddr_temp; + unsigned long cpr_value; + + msr = (mfmsr () & ~(MSR_EE)); + cpr_cfgaddr_temp = mfdcr(CPR0_CFGADDR); + mtdcr(CPR0_CFGADDR, cpr_reg); + cpr_value = mfdcr(CPR0_CFGDATA); + mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp); + mtmsr(msr); + + return (cpr_value); +} + +/*----------------------------------------------------------------------------+ +| Indirect Access of the System DCR's (SDR) +| ppcMfsdr ++----------------------------------------------------------------------------*/ +unsigned long ppcMfsdr(unsigned long sdr_reg) +{ + unsigned long msr; + unsigned long sdr_cfgaddr_temp; + unsigned long sdr_value; + + msr = (mfmsr () & ~(MSR_EE)); + sdr_cfgaddr_temp = mfdcr(SDR0_CFGADDR); + mtdcr(SDR0_CFGADDR, sdr_reg); + sdr_value = mfdcr(SDR0_CFGDATA); + mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp); + mtmsr(msr); + + return (sdr_value); +} diff --git a/board/amcc/yucca/yucca.h b/board/amcc/yucca/yucca.h index 4d13021f3..66f75847d 100644 --- a/board/amcc/yucca/yucca.h +++ b/board/amcc/yucca/yucca.h @@ -60,9 +60,6 @@ extern "C" { #define NUM_TLB_ENTRIES 64 -/* MICRON SPD JEDEC ID Code (first byte) - SPD data byte [64] */ -#define MICRON_SPD_JEDEC_ID 0x2c - /*----------------------------------------------------------------------------+ | TLB specific defines. +----------------------------------------------------------------------------*/ diff --git a/board/amirix/ap1000/Makefile b/board/amirix/ap1000/Makefile index d0729348a..4e1ef217c 100644 --- a/board/amirix/ap1000/Makefile +++ b/board/amirix/ap1000/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o +OBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c index 55277e72d..7d11b29b5 100644 --- a/board/amirix/ap1000/ap1000.c +++ b/board/amirix/ap1000/ap1000.c @@ -133,7 +133,7 @@ int checkboard (void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { char *s = getenv ("dramsize"); diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S index 65f13e17a..3aaa5c2f1 100644 --- a/board/amirix/ap1000/init.S +++ b/board/amirix/ap1000/init.S @@ -28,3 +28,7 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr + + .globl sdram_init +sdram_init: + blr diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c index 508e88040..c6ee77281 100644 --- a/board/amirix/ap1000/serial.c +++ b/board/amirix/ap1000/serial.c @@ -19,9 +19,9 @@ * */ -#include #include #include +#include #include #include @@ -84,7 +84,7 @@ void serial_puts (const char *s) } } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) void kgdb_serial_init (void) { } @@ -108,4 +108,4 @@ void kgdb_interruptible (int yes) { return; } -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds index a939e0331..109e7fe3e 100644 --- a/board/amirix/ap1000/u-boot.lds +++ b/board/amirix/ap1000/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -60,7 +61,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -132,7 +133,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/armadillo/Makefile b/board/armadillo/Makefile index b18e42bff..52ea7f28d 100644 --- a/board/armadillo/Makefile +++ b/board/armadillo/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2002 # Sysgo Real-Time Solutions, GmbH # Marius Groeger @@ -27,29 +24,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := armadillo.o flash.o +OBJS := armadillo.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c index 8518856cb..037a6430d 100644 --- a/board/armadillo/flash.c +++ b/board/armadillo/flash.c @@ -279,7 +279,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) int i, rc; wp = (addr & ~1); /* get lower word aligned address */ - printf ("Writing %lu short data to 0x%lx from 0x%p.\n ", cnt, wp, src); + printf ("Writing %d short data to 0x%p from 0x%p.\n ", cnt, wp, src); /* * handle unaligned start bytes diff --git a/board/armadillo/lowlevel_init.S b/board/armadillo/lowlevel_init.S index e7d373d27..6cf642611 100644 --- a/board/armadillo/lowlevel_init.S +++ b/board/armadillo/lowlevel_init.S @@ -29,8 +29,8 @@ /* some parameters for the board */ /* setting up the memory */ -#define SRAM_START 0x60000000 -#define SRAM_SIZE 0x0000c000 +#define SRAM_START 0x60000000 +#define SRAM_SIZE 0x0000c000 .globl lowlevel_init lowlevel_init: diff --git a/board/armadillo/u-boot.lds b/board/armadillo/u-boot.lds index 418101ff8..64d946c43 100644 --- a/board/armadillo/u-boot.lds +++ b/board/armadillo/u-boot.lds @@ -50,6 +50,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/assabet/Makefile b/board/assabet/Makefile index 03f0762a3..c49f1b460 100644 --- a/board/assabet/Makefile +++ b/board/assabet/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # 2004 (c) MontaVista Software, Inc. @@ -25,29 +25,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := assabet.o +OBJS := assabet.o SOBJS := setup.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/assabet/assabet.c b/board/assabet/assabet.c index 6f02db29b..4f84a5811 100644 --- a/board/assabet/assabet.c +++ b/board/assabet/assabet.c @@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ECSR_PWRDWN 0x04 #define ECSR_INT 0x02 #define SMC_IO_SHIFT 2 -#define NCR_0 (*((volatile u_char *)(0x100000a0))) +#define NCR_0 (*((volatile u_char *)(0x100000a0))) #define NCR_ENET_OSC_EN (1<<3) static inline u8 diff --git a/board/assabet/u-boot.lds b/board/assabet/u-boot.lds index 3f52f0431..7a3a9b8fc 100644 --- a/board/assabet/u-boot.lds +++ b/board/assabet/u-boot.lds @@ -53,6 +53,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/at91rm9200dk/Makefile b/board/at91rm9200dk/Makefile new file mode 100644 index 000000000..ec77da9de --- /dev/null +++ b/board/at91rm9200dk/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := at91rm9200dk.o at45.o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/at91rm9200dk/at45.c b/board/at91rm9200dk/at45.c new file mode 100644 index 000000000..f886fe482 --- /dev/null +++ b/board/at91rm9200dk/at45.c @@ -0,0 +1,621 @@ +/* Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#ifdef CONFIG_HAS_DATAFLASH +#include + +#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to +the Continuous Array Read function */ + +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define AT91C_TIMEOUT_WRDY 200000 +#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ +#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ + +void AT91F_SpiInit(void) { + +/*-------------------------------------------------------------------*/ +/* SPI DataFlash Init */ +/*-------------------------------------------------------------------*/ + /* Configure PIOs */ + AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | + AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | + AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; + /* Enable CLock */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; + + /* Reset the SPI */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; + + /* Configure SPI in Master Mode with No CS selected !!! */ + AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; + + /* Configure CS0 and CS3 */ + *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & + DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + + *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & + DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + +} + +void AT91F_SpiEnable(int cs) { + switch(cs) { + case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); + break; + case 3: /* Configure SPI CS3 for Serial DataFlash Card */ + /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ + AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ + /* Clear Output */ + AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; + /* Configure PCS */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); + break; + } + + /* SPI_Enable */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; +} + +/*----------------------------------------------------------------------------*/ +/* \fn AT91F_SpiWrite */ +/* \brief Set the PDC registers for a transfert */ +/*----------------------------------------------------------------------------*/ +unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) +{ + unsigned int timeout; + + pDesc->state = BUSY; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + + /* Initialize the Transmit and Receive Pointer */ + AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; + AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; + + /* Intialize the Transmit and Receive Counters */ + AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; + AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; + + if ( pDesc->tx_data_size != 0 ) { + /* Initialize the Next Transmit and Next Receive Pointer */ + AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; + AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; + + /* Intialize the Next Transmit and Next Receive Counters */ + AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; + AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + timeout = 0; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; + while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + pDesc->state = IDLE; + + if (timeout >= CFG_SPI_WRITE_TOUT){ + printf("Error Timeout\n\r"); + return DATAFLASH_ERROR; + } + + return DATAFLASH_OK; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashSendCommand */ +/* \brief Generic function to send a command to the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashSendCommand( + AT91PS_DataFlash pDataFlash, + unsigned char OpCode, + unsigned int CmdSize, + unsigned int DataflashAddress) +{ + unsigned int adr; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* process the address to obtain page address and byte address */ + adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); + + /* fill the command buffer */ + pDataFlash->pDataFlashDesc->command[0] = OpCode; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); + } else { + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; + pDataFlash->pDataFlashDesc->command[4] = 0; + } + pDataFlash->pDataFlashDesc->command[5] = 0; + pDataFlash->pDataFlashDesc->command[6] = 0; + pDataFlash->pDataFlashDesc->command[7] = 0; + + /* Initialize the SpiData structure for the spi write fuction */ + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; + + /* send the command and read the data */ + return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashGetStatus */ +/* \brief Read the status register of the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) +{ + AT91S_DataFlashStatus status; + + /* if a transfert is in progress ==> return 0 */ + if( (pDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* first send the read status command (D7H) */ + pDesc->command[0] = DB_STATUS; + pDesc->command[1] = 0; + + pDesc->DataFlash_state = GET_STATUS; + pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ + pDesc->tx_cmd_pt = pDesc->command ; + pDesc->rx_cmd_pt = pDesc->command ; + pDesc->rx_cmd_size = 2 ; + pDesc->tx_cmd_size = 2 ; + status = AT91F_SpiWrite (pDesc); + + pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); + + return status; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashWaitReady */ +/* \brief wait for dataflash ready (bit7 of the status register == 1) */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) +{ + pDataFlashDesc->DataFlash_state = IDLE; + + do { + AT91F_DataFlashGetStatus(pDataFlashDesc); + timeout--; + } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); + + if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) + return DATAFLASH_ERROR; + + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashContinuousRead */ +/* Object : Continuous stream Read */ +/* Input Parameters : DataFlash Service */ +/* : = dataflash address */ +/* : <*dataBuffer> = data buffer pointer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( + AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead ) +{ + AT91S_DataFlashStatus status; + /* Test the size to read in the device */ + if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; + + status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); + /* Send the command to the dataflash */ + return(status); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashPagePgmBuf */ +/* Object : Main memory page program through buffer 1 or buffer 2 */ +/* Input Parameters : DataFlash Service */ +/* : <*src> = Source buffer */ +/* : = dataflash destination address */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int SizeToWrite) +{ + int cmdsize; + pDataFlash->pDataFlashDesc->tx_data_pt = src ; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; + pDataFlash->pDataFlashDesc->rx_data_pt = src; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; + + cmdsize = 4; + /* Send the command to the dataflash */ + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_MainMemoryToBufferTransfert */ +/* Object : Read a page in the SRAM Buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); +} + + +/*----------------------------------------------------------------------------- */ +/* Function Name : AT91F_DataFlashWriteBuffer */ +/* Object : Write data to the internal sram buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : = command to write buffer1 or buffer2 */ +/* : <*dataBuffer> = data buffer to write */ +/* : = address in the internal buffer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite ) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) + return DATAFLASH_BAD_COMMAND; + + /* buffer address must be lower than page size */ + if (bufferAddress > pDataFlash->pDevice->pages_size) + return DATAFLASH_BAD_ADDRESS; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* Send first Write Command */ + pDataFlash->pDataFlashDesc->command[0] = BufferCommand; + pDataFlash->pDataFlashDesc->command[1] = 0; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[2] = 0; + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; + cmdsize = 5; + } else { + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; + pDataFlash->pDataFlashDesc->command[4] = 0; + cmdsize = 4; + } + + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; + + return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_PageErase */ +/* Object : Erase a page */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PageErase( + AT91PS_DataFlash pDataFlash, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_BlockErase */ +/* Object : Erase a Block */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_BlockErase( + AT91PS_DataFlash pDataFlash, + unsigned int block) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_WriteBufferToMain */ +/* Object : Write buffer to the main memory */ +/* Input Parameters : DataFlash Service */ +/* : = command to send to buffer1 or buffer2 */ +/* : = main memory address */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_WriteBufferToMain ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int dest ) +{ + int cmdsize; + /* Test if the buffer command is correct */ + if ((BufferCommand != DB_BUF1_PAGE_PGM) && + (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && + (BufferCommand != DB_BUF2_PAGE_PGM) && + (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + /* Send the command to the dataflash */ + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_PartialPageWrite */ +/* Object : Erase partielly a page */ +/* Input Parameters : = page number */ +/* : = adr to begin the fading */ +/* : = Number of bytes to erase */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PartialPageWrite ( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int size) +{ + unsigned int page; + unsigned int AdrInPage; + + page = dest / (pDataFlash->pDevice->pages_size); + AdrInPage = dest % (pDataFlash->pDevice->pages_size); + + /* Read the contents of the page in the Sram Buffer */ + AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + /*Update the SRAM buffer */ + AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Erase page if a 128 Mbits device */ + if (pDataFlash->pDevice->pages_number >= 16384) { + AT91F_PageErase(pDataFlash, page); + /* Rewrite the modified Sram Buffer in the main memory */ + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + } + + /* Rewrite the modified Sram Buffer in the main memory */ + return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashWrite */ +/* Object : */ +/* Input Parameters : <*src> = Source buffer */ +/* : = dataflash adress */ +/* : = data buffer size */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWrite( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ) +{ + unsigned int length; + unsigned int page; + unsigned int status; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + /* If destination does not fit a page start address */ + if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { + length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); + + if (size < length) + length = size; + + if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= length; + dest += length; + src += length; + } + + while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { + /* program dataflash page */ + page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); + + status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + status = AT91F_PageErase(pDataFlash, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + if (!status) + return DATAFLASH_ERROR; + + status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); + if(!status) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= pDataFlash->pDevice->pages_size ; + dest += pDataFlash->pDevice->pages_size ; + src += pDataFlash->pDevice->pages_size ; + } + + /* If still some bytes to read */ + if ( size > 0 ) { + /* program dataflash page */ + if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + } + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashRead */ +/* Object : Read a block in dataflash */ +/* Input Parameters : */ +/* Return value : */ +/*------------------------------------------------------------------------------*/ +int AT91F_DataFlashRead( + AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, + char *buffer) +{ + unsigned long SizeToRead; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + while (size) { + SizeToRead = (size < 0x8000)? size:0x8000; + + if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK) + return -1; + + size -= SizeToRead; + addr += SizeToRead; + buffer += SizeToRead; + } + + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataflashProbe */ +/* Object : */ +/* Input Parameters : */ +/* Return value : Dataflash status register */ +/*------------------------------------------------------------------------------*/ +int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) +{ + AT91F_SpiEnable(cs); + AT91F_DataFlashGetStatus(pDesc); + return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); +} + +#endif diff --git a/board/at91rm9200dk/at91rm9200dk.c b/board/at91rm9200dk/at91rm9200dk.c new file mode 100644 index 000000000..002981a76 --- /dev/null +++ b/board/at91rm9200dk/at91rm9200dk.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + /* Enable Ctrlc */ + console_init_f (); + + /* Correct IRDA resistor problem */ + /* Set PA23_TXD in Output */ + ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of AT91RM9200DK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_DRIVER_ETHER +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* + * Name: + * at91rm9200_GetPhyInterface + * Description: + * Initialise the interface functions to the PHY + * Arguments: + * None + * Return value: + * None + */ +void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) +{ + p_phyops->Init = dm9161_InitPhy; + p_phyops->IsPhyConnected = dm9161_IsPhyConnected; + p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; + p_phyops->AutoNegotiate = dm9161_AutoNegotiate; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif /* CONFIG_DRIVER_ETHER */ + +/* + * Disk On Chip (NAND) Millenium initialization. + * The NAND lives in the CS2* space + */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +extern ulong nand_probe (ulong physadr); + +#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ +void nand_init (void) +{ + /* Setup Smart Media, fitst enable the address range of CS3 */ + *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia; + /* set the bus interface characteristics based on + tDS Data Set up Time 30 - ns + tDH Data Hold Time 20 - ns + tALS ALE Set up Time 20 - ns + 16ns at 60 MHz ~= 3 */ +/*memory mapping structures */ +#define SM_ID_RWH (5 << 28) +#define SM_RWH (1 << 28) +#define SM_RWS (0 << 24) +#define SM_TDF (1 << 8) +#define SM_NWS (3) + AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS | + AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 | + SM_TDF | AT91C_SMC2_WSEN | SM_NWS); + + /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */ + *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | + AT91C_PC3_BFBAA_SMWE; + *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | + AT91C_PC3_BFBAA_SMWE; + + /* Configure PC2 as input (signal READY of the SmartMedia) */ + *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */ + *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */ + + /* Configure PB1 as input (signal Card Detect of the SmartMedia) */ + *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */ + *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */ + + /* PIOB and PIOC clock enabling */ + *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; + *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; + + if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1) + printf (" No SmartMedia card inserted\n"); +#ifdef DEBUG + printf (" SmartMedia card inserted\n"); + + printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE); +#endif + printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20); +} +#endif diff --git a/board/at91rm9200dk/config.mk b/board/at91rm9200dk/config.mk new file mode 100644 index 000000000..9ce161e55 --- /dev/null +++ b/board/at91rm9200dk/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x21f00000 diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c new file mode 100644 index 000000000..0513d61d7 --- /dev/null +++ b/board/at91rm9200dk/flash.c @@ -0,0 +1,502 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +ulong myflush(void); + + +/* Flash Organization Structure */ +typedef struct OrgDef +{ + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgAT49BV16x4[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 2, 32*1024 }, /* 2 * 32 kBytes sectors */ + { 30, 64*1024 }, /* 30 * 64 kBytes sectors */ +}; + +OrgDef OrgAT49BV16x4A[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 31, 64*1024 }, /* 31 * 64 kBytes sectors */ +}; + +OrgDef OrgAT49BV6416[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ +}; + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/* AT49BV1614A Codes */ +#define FLASH_CODE1 0xAA +#define FLASH_CODE2 0x55 +#define ID_IN_CODE 0x90 +#define ID_OUT_CODE 0xF0 + + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 +#define CMD_SECTOR_UNLOCK 0x0070 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1))) + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ +void flash_identification (flash_info_t * info) +{ + volatile u16 manuf_code, device_code, add_device_code; + + MEM_FLASH_ADDR1 = FLASH_CODE1; + MEM_FLASH_ADDR2 = FLASH_CODE2; + MEM_FLASH_ADDR1 = ID_IN_CODE; + + manuf_code = *(volatile u16 *) CFG_FLASH_BASE; + device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2); + add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1)); + + MEM_FLASH_ADDR1 = FLASH_CODE1; + MEM_FLASH_ADDR2 = FLASH_CODE2; + MEM_FLASH_ADDR1 = ID_OUT_CODE; + + /* Vendor type */ + info->flash_id = ATM_MANUFACT & FLASH_VENDMASK; + printf ("Atmel: "); + + if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) { + + if ((add_device_code & FLASH_TYPEMASK) == + (ATM_ID_BV1614A & FLASH_TYPEMASK)) { + info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK; + printf ("AT49BV1614A (16Mbit)\n"); + } else { /* AT49BV1614 Flash */ + info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK; + printf ("AT49BV1614 (16Mbit)\n"); + } + + } else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) { + info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK; + printf ("AT49BV6416 (64Mbit)\n"); + } +} + +ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks) +{ + int i, nb_sectors = 0; + + for (i=0; istart[sector]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + *addr = CMD_SECTOR_UNLOCK; +} + + +ulong flash_init (void) +{ + int i, j, k; + unsigned int flash_nb_blocks, sector; + unsigned int start_address; + OrgDef *pOrgDef; + + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_identification (&flash_info[i]); + + if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV1614 & FLASH_TYPEMASK)) { + + pOrgDef = OrgAT49BV16x4; + flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef); + } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */ + + pOrgDef = OrgAT49BV16x4A; + flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef); + } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ + + pOrgDef = OrgAT49BV6416; + flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef); + } else { + flash_nb_blocks = 0; + pOrgDef = OrgAT49BV16x4; + } + + flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks); + memset (flash_info[i].protect, 0, flash_info[i].sector_count); + + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + + sector = 0; + start_address = flashbase; + flash_info[i].size = 0; + + for (j = 0; j < flash_nb_blocks; j++) { + for (k = 0; k < pOrgDef[j].sector_number; k++) { + flash_info[i].start[sector++] = start_address; + start_address += pOrgDef[j].sector_size; + flash_info[i].size += pOrgDef[j].sector_size; + } + } + + size += flash_info[i].size; + + if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ + + /* Unlock all sectors at reset */ + for (j=0; jflash_id & FLASH_VENDMASK) { + case (ATM_MANUFACT & FLASH_VENDMASK): + printf ("Atmel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (ATM_ID_BV1614 & FLASH_TYPEMASK): + printf ("AT49BV1614 (16Mbit)\n"); + break; + case (ATM_ID_BV1614A & FLASH_TYPEMASK): + printf ("AT49BV1614A (16Mbit)\n"); + break; + case (ATM_ID_BV6416 & FLASH_TYPEMASK): + printf ("AT49BV6416 (64Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + return; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip1; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (ATM_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + volatile u16 *addr = (volatile u16 *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + } while (!chip1); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile u16 *addr = (volatile u16 *) dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + int chip1; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + chip1 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + } while (!chip1); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + }; + + if ((int) src & 1) { + printf ("unaligned source not supported\n"); + return ERR_ALIGN; + }; + + wp = addr; + + while (cnt >= 2) { + data = *((volatile u16 *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 1) { + data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << + 8); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + }; + + return ERR_OK; +} diff --git a/board/at91rm9200dk/u-boot.lds b/board/at91rm9200dk/u-boot.lds new file mode 100644 index 000000000..f4fbf969c --- /dev/null +++ b/board/at91rm9200dk/u-boot.lds @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/atc/Makefile b/board/atc/Makefile index 4b9cd7b82..7573a0c77 100644 --- a/board/atc/Makefile +++ b/board/atc/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ti113x.o +OBJS = $(BOARD).o flash.o ti113x.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/atc/atc.c b/board/atc/atc.c index 79527f438..d2c6b3bfc 100644 --- a/board/atc/atc.c +++ b/board/atc/atc.c @@ -340,7 +340,7 @@ int misc_init_r(void) return (0); } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; @@ -379,7 +379,7 @@ phys_size_t initdram (int board_type) return (psize); } -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) extern void doc_probe (ulong physadr); void doc_init (void) { diff --git a/board/atc/ti113x.c b/board/atc/ti113x.c index e112eca85..d5e935c40 100644 --- a/board/atc/ti113x.c +++ b/board/atc/ti113x.c @@ -591,7 +591,7 @@ exit: return rc; } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_off (void) { printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); diff --git a/board/atc/u-boot.lds b/board/atc/u-boot.lds new file mode 100644 index 000000000..eee83d099 --- /dev/null +++ b/board/atc/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/barco/Makefile b/board/barco/Makefile index 5aa02d4a7..d6bbf2f29 100644 --- a/board/barco/Makefile +++ b/board/barco/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/barco/barco.c b/board/barco/barco.c index f8b2084c4..becbd0abd 100644 --- a/board/barco/barco.c +++ b/board/barco/barco.c @@ -83,7 +83,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long size; long new_bank0_end; @@ -177,7 +177,7 @@ unsigned update_flash (unsigned char *buf) write_flash ((char *)buf, (*buf) & 0xFE); *((unsigned char *)0xFF800000) = 0xF0; udelay (100); - printf ("buf [%#010x] %#010x\n", (unsigned)buf, (*buf)); + printf ("buf [%#010x] %#010x\n", buf, (*buf)); /* XXX - fall through??? */ case BOOT_WORKING : return BOOT_WORKING; @@ -273,10 +273,10 @@ void barcobcd_boot (void) /* give length of the kernel image to bootm */ sprintf (bootm_args[0],"%x",start->size); /* give address of the kernel image to bootm */ - sprintf (bootm_args[1],"%x",(unsigned)buf); + sprintf (bootm_args[1],"%x",buf); printf ("flash address: %#10x\n",start->address+8); - printf ("buf address: %#10x\n",(unsigned)buf); + printf ("buf address: %#10x\n",buf); /* aha, we reserve 8 bytes here... */ for (cnt = 0; cnt < start->size ; cnt++) { diff --git a/board/barco/barco_svc.h b/board/barco/barco_svc.h index bd924f2b1..088f61e74 100644 --- a/board/barco/barco_svc.h +++ b/board/barco/barco_svc.h @@ -59,7 +59,7 @@ typedef struct SBootInfo { /* barcohydra.c */ int checkboard(void); -phys_size_t initdram(int board_type); +long int initdram(int board_type); void pci_init_board(void); void check_flash(void); int write_flash(char *addr, char value); diff --git a/board/barco/speed.h b/board/barco/speed.h index e883dfb2e..46860e840 100644 --- a/board/barco/speed.h +++ b/board/barco/speed.h @@ -52,10 +52,10 @@ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 * * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock + * GCLK CPU clock * SPEED_TMR2_PS prescaler */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ /*----------------------------------------------------------------------- * Timer value for PIT diff --git a/board/barco/u-boot.lds b/board/barco/u-boot.lds new file mode 100644 index 000000000..7bf8531ab --- /dev/null +++ b/board/barco/u-boot.lds @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/bc3450/Makefile b/board/bc3450/Makefile index 9c1d0cc56..4dec44fd2 100644 --- a/board/bc3450/Makefile +++ b/board/bc3450/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o cmd_bc3450.o +OBJS := $(BOARD).o cmd_bc3450.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c index a728dc64d..0d865186a 100644 --- a/board/bc3450/bc3450.c +++ b/board/bc3450/bc3450.c @@ -104,7 +104,7 @@ static void sdram_start (int hi_addr) */ #if defined(CONFIG_MPC5200) -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; @@ -205,7 +205,7 @@ phys_size_t initdram (int board_type) #elif defined(CONFIG_MGT5100) -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT @@ -294,7 +294,8 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) +#define GPIO_PSC1_4 0x01000000UL void init_ide_reset (void) { @@ -310,12 +311,12 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; } } -#endif +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ #ifdef CONFIG_POST /* diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c index 48bc65de2..6bbe4e6a5 100644 --- a/board/bc3450/cmd_bc3450.c +++ b/board/bc3450/cmd_bc3450.c @@ -30,7 +30,7 @@ /* * BC3450 specific commands */ -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) #undef DEBUG #ifdef DEBUG @@ -69,7 +69,7 @@ struct therm { #define SM501_POWER_MODE0_GATE 0x00000040UL #define SM501_POWER_MODE1_GATE 0x00000048UL #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL -#define SM501_GPIO_DATA_LOW 0x00010000UL +#define SM501_GPIO_DATA_LOW 0x00010000UL #define SM501_GPIO_DATA_HIGH 0x00010004UL #define SM501_GPIO_DATA_DIR_LOW 0x00010008UL #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL @@ -189,7 +189,7 @@ int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (rc > 0x0F) return -1; - printf ("0x%lx\n", rc); + printf ("0x%x\n", rc); return 0; } @@ -824,4 +824,4 @@ U_BOOT_CMD (test, 2, 1, cmd_test, "test - unit test routines\n", "\n" "test unit-off\n" " - turns off the BC3450 unit\n" " WARNING: Unsaved environment variables will be lost!\n"); -#endif +#endif /* CFG_CMD_BSP */ diff --git a/board/bc3450/u-boot.lds b/board/bc3450/u-boot.lds new file mode 100644 index 000000000..93b98a8f5 --- /dev/null +++ b/board/bc3450/u-boot.lds @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/bmw/Makefile b/board/bmw/Makefile index ac85cc350..621640b00 100644 --- a/board/bmw/Makefile +++ b/board/bmw/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2002 # James F. Dougherty, Broadcom Corporation, jfd@broadcom.com # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -27,24 +24,20 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o +OBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o SOBJS = early_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/bmw/README b/board/bmw/README index 1f04b1b8a..70bc81362 100644 --- a/board/bmw/README +++ b/board/bmw/README @@ -89,7 +89,7 @@ Interrupt Mappings BMW uses MPC8245 discrete mode interrupts. With the following hardwired mappings: -BCM5701 10/100/1000 Ethernet IRQ1 +BCM5701 10/100/1000 Ethernet IRQ1 CompactPCI Interrupt A IRQ2 RTC/Watchdog Interrupt IRQ3 Internal NS16552 UART IRQ4 diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c index 043143163..485e050b1 100644 --- a/board/bmw/bmw.c +++ b/board/bmw/bmw.c @@ -51,7 +51,7 @@ int checkboard(void) return 0; } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { return 64*1024*1024; } diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S index 57a06a91f..e6400c308 100644 --- a/board/bmw/early_init.S +++ b/board/bmw/early_init.S @@ -246,7 +246,7 @@ early_init_f: #if 1 /* Turn off floating point (remove to keep FP on) */ andi. r3, r3, 0 sync - mtmsr r3 + mtmsr r3 isync #endif @@ -1137,7 +1137,7 @@ early_init_f: /* delay */ lis r7, 1 mtctr r7 -label1: bdnz label1 +label1: bdnz label1 /* Set memgo bit */ /* MCCR1 */ @@ -1151,7 +1151,7 @@ label1: bdnz label1 /* delay again */ lis r7, 1 mtctr r7 -label2: bdnz label2 +label2: bdnz label2 #if 0 /* DEBUG: Infinite loop, write then read */ loop: diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c index a1a85d0fc..d72c861a1 100644 --- a/board/bmw/m48t59y.c +++ b/board/bmw/m48t59y.c @@ -278,7 +278,7 @@ void m48_watchdog_arm(int usec) /* * U-Boot RTC support. */ -int +void rtc_get( struct rtc_time *tmp ) { m48_tod_get(&tmp->tm_year, @@ -295,8 +295,6 @@ rtc_get( struct rtc_time *tmp ) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); #endif - - return 0; } void diff --git a/board/bmw/u-boot.lds b/board/bmw/u-boot.lds new file mode 100644 index 000000000..eaee3fdef --- /dev/null +++ b/board/bmw/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/c2mon/Makefile b/board/c2mon/Makefile index 2b10b0c51..7b2b54582 100644 --- a/board/c2mon/Makefile +++ b/board/c2mon/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o pcmcia.o +OBJS = $(BOARD).o flash.o pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c index 7d2f746f4..ca8eb0cb0 100644 --- a/board/c2mon/c2mon.c +++ b/board/c2mon/c2mon.c @@ -108,7 +108,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c index 57846b10c..5e50c4d9b 100644 --- a/board/c2mon/pcmcia.c +++ b/board/c2mon/pcmcia.c @@ -4,11 +4,11 @@ #undef CONFIG_PCMCIA -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -165,7 +165,7 @@ int pcmcia_hardware_enable(int slot) } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { volatile immap_t *immap; @@ -193,7 +193,7 @@ int pcmcia_hardware_disable(int slot) return (0); } -#endif +#endif /* CFG_CMD_PCMCIA */ int pcmcia_voltage_set(int slot, int vcc, int vpp) @@ -235,14 +235,14 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) sreg |= TPS2211_VPPD0 | TPS2211_VPPD1; /* VAVPP always Hi-Z */ switch(vcc) { - case 0: break; /* Switch off */ + case 0: break; /* Switch off */ case 33: sreg |= TPS2211_VCCD0; /* Switch on 3.3V */ sreg &= ~TPS2211_VCCD1; break; case 50: sreg &= ~TPS2211_VCCD0; /* Switch on 5.0V */ sreg |= TPS2211_VCCD1; break; - default: goto done; + default: goto done; } /* Checking supported voltages */ diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds index 10b38ec35..cdf550f67 100644 --- a/board/c2mon/u-boot.lds +++ b/board/c2mon/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug index 85072feda..3165d5634 100644 --- a/board/c2mon/u-boot.lds.debug +++ b/board/c2mon/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/canmb/Makefile b/board/canmb/Makefile index b6b67d8e7..607833f8b 100644 --- a/board/canmb/Makefile +++ b/board/canmb/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2005-2006 +# (C) Copyright 2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,33 +22,26 @@ # include $(TOPDIR)/config.mk -#ifneq ($(OBJTREE),$(SRCTREE)) -#$(shell mkdir -p $(obj)../common) -#endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o +OBJS := $(BOARD).o #../common/flash.o ../common/vpd.o ../common/am79c874.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c index d3711d077..1782b314f 100644 --- a/board/canmb/canmb.c +++ b/board/canmb/canmb.c @@ -82,7 +82,7 @@ static void sdram_start (int hi_addr) */ #if defined(CONFIG_MPC5200) -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; @@ -185,7 +185,7 @@ phys_size_t initdram (int board_type) #elif defined(CONFIG_MGT5100) -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT diff --git a/board/canmb/u-boot.lds b/board/canmb/u-boot.lds new file mode 100644 index 000000000..88dc118e8 --- /dev/null +++ b/board/canmb/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cds/common/cadmus.c b/board/cds/common/cadmus.c new file mode 100644 index 000000000..5f86de5af --- /dev/null +++ b/board/cds/common/cadmus.c @@ -0,0 +1,95 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include + + +/* + * CADMUS Board System Registers + */ +#ifndef CFG_CADMUS_BASE_REG +#define CFG_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) +#endif + +typedef struct cadmus_reg { + u_char cm_ver; /* Board version */ + u_char cm_csr; /* General control/status */ + u_char cm_rst; /* Reset control */ + u_char cm_hsclk; /* High speed clock */ + u_char cm_hsxclk; /* High speed clock extended */ + u_char cm_led; /* LED data */ + u_char cm_pci; /* PCI control/status */ + u_char cm_dma; /* DMA control */ + u_char cm_reserved[248]; /* Total 256 bytes */ +} cadmus_reg_t; + + +unsigned int +get_board_version(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + + return cadmus->cm_ver; +} + + +unsigned long +get_clock_freq(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + + uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ + + if (pci1_speed == 0) { + return 33000000; + } else if (pci1_speed == 1) { + return 66000000; + } else { + /* Really, unknown. Be safe? */ + return 33000000; + } +} + + +unsigned int +get_pci_slot(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + + /* + * PCI slot in USER bits CSR[6:7] by convention. + */ + return ((cadmus->cm_csr >> 6) & 0x3) + 1; +} + + +unsigned int +get_pci_dual(void) +{ + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + + /* + * PCI DUAL in CM_PCI[3] + */ + return cadmus->cm_pci & 0x10; +} diff --git a/board/cds/common/cadmus.h b/board/cds/common/cadmus.h new file mode 100644 index 000000000..217ea6425 --- /dev/null +++ b/board/cds/common/cadmus.h @@ -0,0 +1,54 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CADMUS_H_ +#define __CADMUS_H_ + + +/* + * CADMUS Board System Register interface. + */ + +/* + * Returns board version register. + */ +extern unsigned int get_board_version(void); + +/* + * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ. + */ +extern unsigned long get_clock_freq(void); + + +/* + * Returns 1 - 4, as found in the USER CSR[6:7] bits. + */ +extern unsigned int get_pci_slot(void); + + +/* + * Returns PCI DUAL as found in CM_PCI[3]. + */ +extern unsigned int get_pci_dual(void); + + +#endif /* __CADMUS_H_ */ diff --git a/board/cds/common/eeprom.c b/board/cds/common/eeprom.c new file mode 100644 index 000000000..5034e0ca2 --- /dev/null +++ b/board/cds/common/eeprom.c @@ -0,0 +1,60 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + +#include "eeprom.h" + + +typedef struct { + char idee_pcbid[4]; /* "CCID" for CDC v1.X */ + u8 idee_major; + u8 idee_minor; + char idee_serial[10]; + char idee_errata[2]; + char idee_date[8]; /* yyyymmdd */ + /* The rest of the EEPROM space is reserved */ +} id_eeprom_t; + + +unsigned int +get_cpu_board_revision(void) +{ + uint major = 0; + uint minor = 0; + + id_eeprom_t id_eeprom; + + i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, + (uchar *) &id_eeprom, sizeof(id_eeprom)); + + major = id_eeprom.idee_major; + minor = id_eeprom.idee_minor; + + if (major == 0xff && minor == 0xff) { + major = minor = 0; + } + + return MPC85XX_CPU_BOARD_REV(major,minor); +} diff --git a/board/cds/common/eeprom.h b/board/cds/common/eeprom.h new file mode 100644 index 000000000..12a078904 --- /dev/null +++ b/board/cds/common/eeprom.h @@ -0,0 +1,50 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __EEPROM_H_ +#define __EEPROM_H_ + + +/* + * EEPROM Board System Register interface. + */ + + +/* + * CPU Board Revision + */ +#define MPC85XX_CPU_BOARD_REV(maj, min) ((((maj)&0xff) << 8) | ((min) & 0xff)) +#define MPC85XX_CPU_BOARD_MAJOR(rev) (((rev) >> 8) & 0xff) +#define MPC85XX_CPU_BOARD_MINOR(rev) ((rev) & 0xff) + +#define MPC85XX_CPU_BOARD_REV_UNKNOWN MPC85XX_CPU_BOARD_REV(0,0) +#define MPC85XX_CPU_BOARD_REV_1_0 MPC85XX_CPU_BOARD_REV(1,0) +#define MPC85XX_CPU_BOARD_REV_1_1 MPC85XX_CPU_BOARD_REV(1,1) + +/* + * Returns CPU board revision register as a 16-bit value with + * the Major in the high byte, and Minor in the low byte. + */ +extern unsigned int get_cpu_board_revision(void); + + +#endif /* __CADMUS_H_ */ diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile new file mode 100644 index 000000000..0d4abbd71 --- /dev/null +++ b/board/cds/mpc8541cds/Makefile @@ -0,0 +1,51 @@ +# +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o \ + ../common/cadmus.o \ + ../common/eeprom.o + +SOBJS := init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cds/mpc8541cds/config.mk b/board/cds/mpc8541cds/config.mk new file mode 100644 index 000000000..17cc8bce9 --- /dev/null +++ b/board/cds/mpc8541cds/config.mk @@ -0,0 +1,30 @@ +# +# Copyright 2004 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8541cds board +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8541=1 diff --git a/board/cds/mpc8541cds/init.S b/board/cds/mpc8541cds/init.S new file mode 100644 index 000000000..53dcd0d76 --- /dev/null +++ b/board/cds/mpc8541cds/init.S @@ -0,0 +1,255 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright 2002,2003, Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) + .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ +#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long 6 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 + entry_end diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c new file mode 100644 index 000000000..6b8aa68f5 --- /dev/null +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -0,0 +1,504 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/cadmus.h" +#include "../common/eeprom.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + /* PCI slot in USER bits CSR[6:7] by convention. */ + uint pci_slot = get_pci_slot (); + + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + + uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + uint cpu_board_rev = get_cpu_board_revision (); + + printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", + get_board_version (), pci_slot); + + printf ("CPU Board Revision %d.%d (0x%04x)\n", + MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), + MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); + + printf (" PCI1: %d bit, %s MHz, %s\n", + (pci1_32) ? 32 : 64, + (pci1_speed == 33000000) ? "33" : + (pci1_speed == 66000000) ? "66" : "unknown", + pci1_clk_sel ? "sync" : "async"); + + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } + + /* + * Initialize local bus. + */ + local_bus_init (); + + return 0; +} + +long int +initdram(int board_type) +{ + long dram_size = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur= &immap->im_gur; + + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay(200); + } +#endif + dram_size = spd_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + uint temp_lbcdll; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr |= 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + + } else { + lbc->lcrr &= (~0x8000000); /* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void +sdram_init(void) +{ +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + + uint idx; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + uint cpu_board_rev; + uint lsdmr_common; + + puts(" SDRAM: "); + + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + asm("msync"); + + lbc->br2 = CFG_BR2_PRELIM; + asm("msync"); + + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("msync"); + + /* + * Determine which address lines to use baed on CPU board rev. + */ + cpu_board_rev = get_cpu_board_revision(); + lsdmr_common = CFG_LBC_LSDMR_COMMON; + if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + } else { + /* + * Assume something unable to identify itself is + * really old, and likely has lines 16/17 mapped. + */ + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + } + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, + CFG_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) + +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxcds_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxcds_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif +} diff --git a/board/cds/mpc8541cds/u-boot.lds b/board/cds/mpc8541cds/u-boot.lds new file mode 100644 index 000000000..1bea0074f --- /dev/null +++ b/board/cds/mpc8541cds/u-boot.lds @@ -0,0 +1,149 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/cds/mpc8541cds/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/cds/mpc8541cds/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile new file mode 100644 index 000000000..0d4abbd71 --- /dev/null +++ b/board/cds/mpc8548cds/Makefile @@ -0,0 +1,51 @@ +# +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o \ + ../common/cadmus.o \ + ../common/eeprom.o + +SOBJS := init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk new file mode 100644 index 000000000..242a67620 --- /dev/null +++ b/board/cds/mpc8548cds/config.mk @@ -0,0 +1,30 @@ +# +# Copyright 2004 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8548cds board +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S new file mode 100644 index 000000000..53dcd0d76 --- /dev/null +++ b/board/cds/mpc8548cds/init.S @@ -0,0 +1,255 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright 2002,2003, Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) + .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ +#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long 6 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 + entry_end diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c new file mode 100644 index 000000000..5bc08900a --- /dev/null +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -0,0 +1,329 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#include "../common/cadmus.h" +#include "../common/eeprom.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + /* PCI slot in USER bits CSR[6:7] by convention. */ + uint pci_slot = get_pci_slot (); + + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + + uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + uint cpu_board_rev = get_cpu_board_revision (); + + printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", + get_board_version (), pci_slot); + + printf ("CPU Board Revision %d.%d (0x%04x)\n", + MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), + MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); + + printf (" PCI1: %d bit, %s MHz, %s\n", + (pci1_32) ? 32 : 64, + (pci1_speed == 33000000) ? "33" : + (pci1_speed == 66000000) ? "66" : "unknown", + pci1_clk_sel ? "sync" : "async"); + + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } + + /* + * Initialize local bus. + */ + local_bus_init (); + + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + + return 0; +} + +long int +initdram(int board_type) +{ + long dram_size = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur= &immap->im_gur; + + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay(200); + } +#endif + dram_size = spd_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + clkdiv = (lbc->lcrr & 0x0f) * 2; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + gur->lbiuiplldcr1 = 0x00078080; + if (clkdiv == 16) { + gur->lbiuiplldcr0 = 0x7c0f1bf0; + } else if (clkdiv == 8) { + gur->lbiuiplldcr0 = 0x6c0f1bf0; + } else if (clkdiv == 4) { + gur->lbiuiplldcr0 = 0x5c0f1bf0; + } + + lbc->lcrr |= 0x00030000; + + asm("sync;isync;msync"); +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void +sdram_init(void) +{ +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + + uint idx; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + uint cpu_board_rev; + uint lsdmr_common; + + puts(" SDRAM: "); + + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + asm("msync"); + + lbc->br2 = CFG_BR2_PRELIM; + asm("msync"); + + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("msync"); + + /* + * MPC8548 uses "new" 15-16 style addressing. + */ + cpu_board_rev = get_cpu_board_revision(); + lsdmr_common = CFG_LBC_LSDMR_COMMON; + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, + CFG_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) + +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxcds_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxcds_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif +} diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds new file mode 100644 index 000000000..2c8fe9603 --- /dev/null +++ b/board/cds/mpc8548cds/u-boot.lds @@ -0,0 +1,149 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/cds/mpc8548cds/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/cds/mpc8548cds/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile new file mode 100644 index 000000000..0d4abbd71 --- /dev/null +++ b/board/cds/mpc8555cds/Makefile @@ -0,0 +1,51 @@ +# +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o \ + ../common/cadmus.o \ + ../common/eeprom.o + +SOBJS := init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cds/mpc8555cds/config.mk b/board/cds/mpc8555cds/config.mk new file mode 100644 index 000000000..5dcaa774d --- /dev/null +++ b/board/cds/mpc8555cds/config.mk @@ -0,0 +1,30 @@ +# +# Copyright 2004 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8555cds board +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8555=1 diff --git a/board/cds/mpc8555cds/init.S b/board/cds/mpc8555cds/init.S new file mode 100644 index 000000000..53dcd0d76 --- /dev/null +++ b/board/cds/mpc8555cds/init.S @@ -0,0 +1,255 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright 2002,2003, Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) + .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ +#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long 6 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 + entry_end diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c new file mode 100644 index 000000000..18adf5b9e --- /dev/null +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -0,0 +1,501 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/cadmus.h" +#include "../common/eeprom.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + /* PCI slot in USER bits CSR[6:7] by convention. */ + uint pci_slot = get_pci_slot (); + + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + + uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + uint cpu_board_rev = get_cpu_board_revision (); + + printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", + get_board_version (), pci_slot); + + printf ("CPU Board Revision %d.%d (0x%04x)\n", + MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), + MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); + + printf (" PCI1: %d bit, %s MHz, %s\n", + (pci1_32) ? 32 : 64, + (pci1_speed == 33000000) ? "33" : + (pci1_speed == 66000000) ? "66" : "unknown", + pci1_clk_sel ? "sync" : "async"); + + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } + + /* + * Initialize local bus. + */ + local_bus_init (); + + return 0; +} + +long int +initdram(int board_type) +{ + long dram_size = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur= &immap->im_gur; + + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay(200); + } +#endif + dram_size = spd_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + uint temp_lbcdll; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr |= 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr &= (~0x80000000); /* DLL Enabled */ + + } else { + lbc->lcrr &= (~0x8000000); /* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void +sdram_init(void) +{ +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + + uint idx; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + uint cpu_board_rev; + uint lsdmr_common; + + puts(" SDRAM: "); + + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + asm("msync"); + + lbc->br2 = CFG_BR2_PRELIM; + asm("msync"); + + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("msync"); + + /* + * Determine which address lines to use baed on CPU board rev. + */ + cpu_board_rev = get_cpu_board_revision(); + lsdmr_common = CFG_LBC_LSDMR_COMMON; + if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + } else { + /* + * Assume something unable to identify itself is + * really old, and likely has lines 16/17 mapped. + */ + lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + } + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, + CFG_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) + +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxcds_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxcds_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif +} diff --git a/board/cds/mpc8555cds/u-boot.lds b/board/cds/mpc8555cds/u-boot.lds new file mode 100644 index 000000000..2aa2ad78f --- /dev/null +++ b/board/cds/mpc8555cds/u-boot.lds @@ -0,0 +1,149 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/cds/mpc8555cds/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/cds/mpc8555cds/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cerf250/Makefile b/board/cerf250/Makefile index a806b1849..83e3ba458 100644 --- a/board/cerf250/Makefile +++ b/board/cerf250/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := cerf250.o flash.o +OBJS := cerf250.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/cerf250/lowlevel_init.S b/board/cerf250/lowlevel_init.S index ad3c59f9f..c9b68d7ff 100644 --- a/board/cerf250/lowlevel_init.S +++ b/board/cerf250/lowlevel_init.S @@ -40,7 +40,7 @@ DRAM_SIZE: .long CFG_DRAM_SIZE /* - * Memory setup + * Memory setup */ .globl lowlevel_init @@ -48,69 +48,69 @@ lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] /* ---------------------------------------------------------------- */ /* Enable memory interface */ @@ -126,19 +126,19 @@ lowlevel_init: /* FIXME: can be optimized later */ /* ---------------------------------------------------------------- */ - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ 1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b + ldr r2, [r3] + cmp r4, r2 + bgt 1b mem_init: - ldr r1, =MEMC_BASE /* get memory controller base addr. */ + ldr r1, =MEMC_BASE /* get memory controller base addr. */ /* ---------------------------------------------------------------- */ /* Step 2a: Initialize Asynchronous static memory controller */ @@ -147,58 +147,58 @@ mem_init: /* MSC registers: timing, bus width, mem type */ /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ /* that data latches */ /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] /* ---------------------------------------------------------------- */ /* Step 2b: Initialize Card Interface */ /* ---------------------------------------------------------------- */ /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] /* ---------------------------------------------------------------- */ /* Step 2c: Write FLYCNFG FIXME: what's that??? */ @@ -212,16 +212,16 @@ mem_init: /* Before accessing MDREFR we need a valid DRI field, so we set */ /* this to power on defaults + DRI field, set SDRAM clocks free running */ - ldr r3, =CFG_MDREFR_VAL - ldr r2, =0xFFF - and r3, r3, r2 + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 - ldr r0, [r1, #MDREFR_OFFSET] - bic r0, r0, r2 - bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE) - orr r0, r0, r3 + ldr r0, [r1, #MDREFR_OFFSET] + bic r0, r0, r2 + bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE) + orr r0, r0, r3 - str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ /* ---------------------------------------------------------------- */ @@ -244,18 +244,18 @@ mem_init: /* set MDREFR according to user define with exception of a few bits */ ldr r4, =CFG_MDREFR_VAL - ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\ + ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\ MDREFR_K2RUN |MDREFR_K2DB2) - and r4, r4, r2 - bic r0, r0, r2 - orr r0, r0, r4 + and r4, r4, r2 + bic r0, r0, r2 + orr r0, r0, r4 str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r0, [r1, #MDREFR_OFFSET] /* Step 4b: de-assert MDREFR:SLFRSH. */ - bic r0, r0, #(MDREFR_SLFRSH) + bic r0, r0, #(MDREFR_SLFRSH) str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r0, [r1, #MDREFR_OFFSET] @@ -263,10 +263,10 @@ mem_init: /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */ ldr r4, =CFG_MDREFR_VAL - ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \ - MDREFR_K1FREE | MDREFR_K2FREE) - and r4, r4, r2 - orr r0, r0, r4 + ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \ + MDREFR_K1FREE | MDREFR_K2FREE) + and r4, r4, r2 + orr r0, r0, r4 str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r0, [r1, #MDREFR_OFFSET] @@ -274,9 +274,9 @@ mem_init: /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ /* configure but not enable each SDRAM partition pair. */ - ldr r4, =CFG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ ldr r4, [r1, #MDCNFG_OFFSET] @@ -284,15 +284,15 @@ mem_init: /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ /* 100..200 µsec. */ - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ /* so 0x300 should be plenty */ 1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b + ldr r2, [r3] + cmp r4, r2 + bgt 1b /* Step 4f: Trigger a number (usually 8) refresh cycles by */ @@ -301,16 +301,16 @@ mem_init: /* documented in SDRAM data sheets. The address(es) used */ /* for this purpose must not be cacheable. */ - ldr r3, =CFG_DRAM_BASE + ldr r3, =CFG_DRAM_BASE .rept 8 - str r2, [r3] + str r2, [r3] .endr /* Step 4g: Write MDCNFG with enable bits asserted */ /* (MDCNFG:DEx set to 1). */ ldr r3, [r1, #MDCNFG_OFFSET] - orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) str r3, [r1, #MDCNFG_OFFSET] /* Step 4h: Write MDMRS. */ @@ -378,27 +378,27 @@ initclks: /* ---------------------------------------------------------------- */ /* Save SDRAM size */ - ldr r1, =DRAM_SIZE - str r8, [r1] + ldr r1, =DRAM_SIZE + str r8, [r1] /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] /* FIXME */ #define NODEBUG #ifdef NODEBUG /*Disable software and data breakpoints */ - mov r0,#0 - mcr p15,0,r0,c14,c8,0 /* ibcr0 */ - mcr p15,0,r0,c14,c9,0 /* ibcr1 */ - mcr p15,0,r0,c14,c4,0 /* dbcon */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ /*Enable all debug functionality */ - mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 /* dcsr */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ #endif @@ -408,4 +408,4 @@ initclks: endlowlevel_init: - mov pc, lr + mov pc, lr diff --git a/board/cerf250/u-boot.lds b/board/cerf250/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/cerf250/u-boot.lds +++ b/board/cerf250/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile index cd3f962f2..c66dd716c 100644 --- a/board/cm4008/Makefile +++ b/board/cm4008/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := cm4008.o flash.o +OBJS := cm4008.o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/cm4008/u-boot.lds b/board/cm4008/u-boot.lds index 3d38f2340..ec09fa23c 100644 --- a/board/cm4008/u-boot.lds +++ b/board/cm4008/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile index 952a8ae21..f0d345198 100644 --- a/board/cm41xx/Makefile +++ b/board/cm41xx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := cm41xx.o flash.o +OBJS := cm41xx.o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/cm41xx/u-boot.lds b/board/cm41xx/u-boot.lds index 3d38f2340..ec09fa23c 100644 --- a/board/cm41xx/u-boot.lds +++ b/board/cm41xx/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/cmc_pu2/Makefile b/board/cmc_pu2/Makefile index 9745ebd37..d0def0552 100644 --- a/board/cmc_pu2/Makefile +++ b/board/cmc_pu2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o +OBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/cmc_pu2/at45.c b/board/cmc_pu2/at45.c new file mode 100644 index 000000000..3c0013216 --- /dev/null +++ b/board/cmc_pu2/at45.c @@ -0,0 +1,621 @@ +/* Driver for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#ifdef CONFIG_HAS_DATAFLASH +#include + +#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to +the Continuous Array Read function */ + +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define AT91C_TIMEOUT_WRDY 200000 +#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ +#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ + +void AT91F_SpiInit(void) { + +/*-------------------------------------------------------------------*/ +/* SPI DataFlash Init */ +/*-------------------------------------------------------------------*/ + /* Configure PIOs */ + AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | + AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; + AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 | + AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK; + /* Enable CLock */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI; + + /* Reset the SPI */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST; + + /* Configure SPI in Master Mode with No CS selected !!! */ + AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; + + /* Configure CS0 and CS3 */ + *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & + DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + + *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & + DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); + +} + +void AT91F_SpiEnable(int cs) { + switch(cs) { + case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS); + break; + case 3: /* Configure SPI CS3 for Serial DataFlash Card */ + /* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */ + AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */ + AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */ + /* Clear Output */ + AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7; + /* Configure PCS */ + AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF; + AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS); + break; + } + + /* SPI_Enable */ + AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; +} + +/*----------------------------------------------------------------------------*/ +/* \fn AT91F_SpiWrite */ +/* \brief Set the PDC registers for a transfert */ +/*----------------------------------------------------------------------------*/ +unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc ) +{ + unsigned int timeout; + + pDesc->state = BUSY; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + + /* Initialize the Transmit and Receive Pointer */ + AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ; + AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ; + + /* Intialize the Transmit and Receive Counters */ + AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size; + AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size; + + if ( pDesc->tx_data_size != 0 ) { + /* Initialize the Next Transmit and Next Receive Pointer */ + AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ; + AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ; + + /* Intialize the Next Transmit and Next Receive Counters */ + AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ; + AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ; + } + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked(); + timeout = 0; + + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN; + while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT)); + AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS; + pDesc->state = IDLE; + + if (timeout >= CFG_SPI_WRITE_TOUT){ + printf("Error Timeout\n\r"); + return DATAFLASH_ERROR; + } + + return DATAFLASH_OK; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashSendCommand */ +/* \brief Generic function to send a command to the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashSendCommand( + AT91PS_DataFlash pDataFlash, + unsigned char OpCode, + unsigned int CmdSize, + unsigned int DataflashAddress) +{ + unsigned int adr; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* process the address to obtain page address and byte address */ + adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size)); + + /* fill the command buffer */ + pDataFlash->pDataFlashDesc->command[0] = OpCode; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24); + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF); + } else { + pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16); + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8); + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ; + pDataFlash->pDataFlashDesc->command[4] = 0; + } + pDataFlash->pDataFlashDesc->command[5] = 0; + pDataFlash->pDataFlashDesc->command[6] = 0; + pDataFlash->pDataFlashDesc->command[7] = 0; + + /* Initialize the SpiData structure for the spi write fuction */ + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ; + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ; + + /* send the command and read the data */ + return AT91F_SpiWrite (pDataFlash->pDataFlashDesc); +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashGetStatus */ +/* \brief Read the status register of the dataflash */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc) +{ + AT91S_DataFlashStatus status; + + /* if a transfert is in progress ==> return 0 */ + if( (pDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* first send the read status command (D7H) */ + pDesc->command[0] = DB_STATUS; + pDesc->command[1] = 0; + + pDesc->DataFlash_state = GET_STATUS; + pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */ + pDesc->tx_cmd_pt = pDesc->command ; + pDesc->rx_cmd_pt = pDesc->command ; + pDesc->rx_cmd_size = 2 ; + pDesc->tx_cmd_size = 2 ; + status = AT91F_SpiWrite (pDesc); + + pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1); + + return status; +} + + +/*----------------------------------------------------------------------*/ +/* \fn AT91F_DataFlashWaitReady */ +/* \brief wait for dataflash ready (bit7 of the status register == 1) */ +/*----------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout) +{ + pDataFlashDesc->DataFlash_state = IDLE; + + do { + AT91F_DataFlashGetStatus(pDataFlashDesc); + timeout--; + } while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) ); + + if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) + return DATAFLASH_ERROR; + + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashContinuousRead */ +/* Object : Continuous stream Read */ +/* Input Parameters : DataFlash Service */ +/* : = dataflash address */ +/* : <*dataBuffer> = data buffer pointer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashContinuousRead ( + AT91PS_DataFlash pDataFlash, + int src, + unsigned char *dataBuffer, + int sizeToRead ) +{ + AT91S_DataFlashStatus status; + /* Test the size to read in the device */ + if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer; + pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead; + + status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src); + /* Send the command to the dataflash */ + return(status); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashPagePgmBuf */ +/* Object : Main memory page program through buffer 1 or buffer 2 */ +/* Input Parameters : DataFlash Service */ +/* : <*src> = Source buffer */ +/* : = dataflash destination address */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int SizeToWrite) +{ + int cmdsize; + pDataFlash->pDataFlashDesc->tx_data_pt = src ; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; + pDataFlash->pDataFlashDesc->rx_data_pt = src; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite; + + cmdsize = 4; + /* Send the command to the dataflash */ + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_MainMemoryToBufferTransfert */ +/* Object : Read a page in the SRAM Buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF)) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size)); +} + + +/*----------------------------------------------------------------------------- */ +/* Function Name : AT91F_DataFlashWriteBuffer */ +/* Object : Write data to the internal sram buffer 1 or 2 */ +/* Input Parameters : DataFlash Service */ +/* : = command to write buffer1 or buffer2 */ +/* : <*dataBuffer> = data buffer to write */ +/* : = address in the internal buffer */ +/* : = data buffer size */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned char *dataBuffer, + unsigned int bufferAddress, + int SizeToWrite ) +{ + int cmdsize; + /* Test if the buffer command is legal */ + if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE)) + return DATAFLASH_BAD_COMMAND; + + /* buffer address must be lower than page size */ + if (bufferAddress > pDataFlash->pDevice->pages_size) + return DATAFLASH_BAD_ADDRESS; + + if ( (pDataFlash->pDataFlashDesc->state) != IDLE) + return DATAFLASH_BUSY; + + /* Send first Write Command */ + pDataFlash->pDataFlashDesc->command[0] = BufferCommand; + pDataFlash->pDataFlashDesc->command[1] = 0; + if (pDataFlash->pDevice->pages_number >= 16384) { + pDataFlash->pDataFlashDesc->command[2] = 0; + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; + pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; + cmdsize = 5; + } else { + pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ; + pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ; + pDataFlash->pDataFlashDesc->command[4] = 0; + cmdsize = 4; + } + + pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ; + pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ; + pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ; + + pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ; + pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ; + pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ; + pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ; + + return AT91F_SpiWrite(pDataFlash->pDataFlashDesc); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_PageErase */ +/* Object : Erase a page */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PageErase( + AT91PS_DataFlash pDataFlash, + unsigned int page) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_BlockErase */ +/* Object : Erase a Block */ +/* Input Parameters : DataFlash Service */ +/* : Page concerned */ +/* : */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_BlockErase( + AT91PS_DataFlash pDataFlash, + unsigned int block) +{ + int cmdsize; + /* Test if the buffer command is legal */ + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size)); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_WriteBufferToMain */ +/* Object : Write buffer to the main memory */ +/* Input Parameters : DataFlash Service */ +/* : = command to send to buffer1 or buffer2 */ +/* : = main memory address */ +/* Return value : State of the dataflash */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_WriteBufferToMain ( + AT91PS_DataFlash pDataFlash, + unsigned char BufferCommand, + unsigned int dest ) +{ + int cmdsize; + /* Test if the buffer command is correct */ + if ((BufferCommand != DB_BUF1_PAGE_PGM) && + (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) && + (BufferCommand != DB_BUF2_PAGE_PGM) && + (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) ) + return DATAFLASH_BAD_COMMAND; + + /* no data to transmit or receive */ + pDataFlash->pDataFlashDesc->tx_data_size = 0; + + cmdsize = 4; + if (pDataFlash->pDevice->pages_number >= 16384) + cmdsize = 5; + /* Send the command to the dataflash */ + return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest)); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_PartialPageWrite */ +/* Object : Erase partielly a page */ +/* Input Parameters : = page number */ +/* : = adr to begin the fading */ +/* : = Number of bytes to erase */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_PartialPageWrite ( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + unsigned int dest, + unsigned int size) +{ + unsigned int page; + unsigned int AdrInPage; + + page = dest / (pDataFlash->pDevice->pages_size); + AdrInPage = dest % (pDataFlash->pDevice->pages_size); + + /* Read the contents of the page in the Sram Buffer */ + AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + /*Update the SRAM buffer */ + AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size); + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Erase page if a 128 Mbits device */ + if (pDataFlash->pDevice->pages_number >= 16384) { + AT91F_PageErase(pDataFlash, page); + /* Rewrite the modified Sram Buffer in the main memory */ + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + } + + /* Rewrite the modified Sram Buffer in the main memory */ + return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size))); +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashWrite */ +/* Object : */ +/* Input Parameters : <*src> = Source buffer */ +/* : = dataflash adress */ +/* : = data buffer size */ +/*------------------------------------------------------------------------------*/ +AT91S_DataFlashStatus AT91F_DataFlashWrite( + AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ) +{ + unsigned int length; + unsigned int page; + unsigned int status; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number))) + return DATAFLASH_MEMORY_OVERFLOW; + + /* If destination does not fit a page start address */ + if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) { + length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size))); + + if (size < length) + length = size; + + if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length)) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= length; + dest += length; + src += length; + } + + while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) { + /* program dataflash page */ + page = (unsigned int)dest / (pDataFlash->pDevice->pages_size); + + status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + status = AT91F_PageErase(pDataFlash, page); + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + if (!status) + return DATAFLASH_ERROR; + + status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest); + if(!status) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + + /* Update size, source and destination pointers */ + size -= pDataFlash->pDevice->pages_size ; + dest += pDataFlash->pDevice->pages_size ; + src += pDataFlash->pDevice->pages_size ; + } + + /* If still some bytes to read */ + if ( size > 0 ) { + /* program dataflash page */ + if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) ) + return DATAFLASH_ERROR; + + AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY); + } + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataFlashRead */ +/* Object : Read a block in dataflash */ +/* Input Parameters : */ +/* Return value : */ +/*------------------------------------------------------------------------------*/ +int AT91F_DataFlashRead( + AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, + char *buffer) +{ + unsigned long SizeToRead; + + AT91F_SpiEnable(pDataFlash->pDevice->cs); + + if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + while (size) { + SizeToRead = (size < 0x8000)? size:0x8000; + + if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK) + return -1; + + if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK) + return -1; + + size -= SizeToRead; + addr += SizeToRead; + buffer += SizeToRead; + } + + return DATAFLASH_OK; +} + + +/*------------------------------------------------------------------------------*/ +/* Function Name : AT91F_DataflashProbe */ +/* Object : */ +/* Input Parameters : */ +/* Return value : Dataflash status register */ +/*------------------------------------------------------------------------------*/ +int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc) +{ + AT91F_SpiEnable(cs); + AT91F_DataFlashGetStatus(pDesc); + return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C); +} + +#endif diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c index 3ad756de1..9ae3c42be 100644 --- a/board/cmc_pu2/cmc_pu2.c +++ b/board/cmc_pu2/cmc_pu2.c @@ -73,7 +73,7 @@ int board_init (void) pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 | AT91C_PIO_PC2 | AT91C_PIO_PC3; pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 | - AT91C_PIO_PC2 | AT91C_PIO_PC3; + AT91C_PIO_PC2 | AT91C_PIO_PC3; /* * On CMC-PU2 board configure PB3-PB6 to input without pull ups to @@ -155,7 +155,7 @@ int hw_detect (void) } #ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) /* * Name: @@ -175,5 +175,5 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) p_phyops->AutoNegotiate = dm9161_AutoNegotiate; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ #endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/cmc_pu2/u-boot.lds b/board/cmc_pu2/u-boot.lds index 14cd22800..f4fbf969c 100644 --- a/board/cmc_pu2/u-boot.lds +++ b/board/cmc_pu2/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/cmi/Makefile b/board/cmi/Makefile index aeebb9ecb..2324d8772 100644 --- a/board/cmi/Makefile +++ b/board/cmi/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de +# (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de +# # # See file CREDITS for list of people who contributed to this # project. @@ -23,28 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := flash.o cmi.o +OBJS := flash.o cmi.o +SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c index 8501cae21..cbf34f785 100644 --- a/board/cmi/cmi.c +++ b/board/cmi/cmi.c @@ -62,7 +62,7 @@ int checkboard(void) /* * Get RAM size. */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { return (SRAM_SIZE); /* We currently have a static size adapted for cmi board. */ } diff --git a/board/cmi/flash.c b/board/cmi/flash.c index f57d8ecfe..f7c25f428 100644 --- a/board/cmi/flash.c +++ b/board/cmi/flash.c @@ -25,7 +25,7 @@ * File: flash.c * * Discription: This Driver is for 28F320J3A, 28F640J3A and - * 28F128J3A Intel flashs working in 16 Bit mode. + * 28F128J3A Intel flashs working in 16 Bit mode. * They are single bank flashs. * * Most of this code is taken from existing u-boot @@ -67,9 +67,9 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* * Local function prototypes */ -static ulong flash_get_size (vu_short *addr, flash_info_t *info); -static int write_short (flash_info_t *info, ulong dest, ushort data); -static void flash_get_offsets (ulong base, flash_info_t *info); +static ulong flash_get_size (vu_short *addr, flash_info_t *info); +static int write_short (flash_info_t *info, ulong dest, ushort data); +static void flash_get_offsets (ulong base, flash_info_t *info); /* * Initialize flash diff --git a/board/cmi/u-boot.lds b/board/cmi/u-boot.lds new file mode 100644 index 000000000..5b03fef66 --- /dev/null +++ b/board/cmi/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de + * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +/* . = env_start; + .ppcenv : + { + common/environment.o (.ppcenv) + } +*/ +} diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile index be704b76f..e5d844631 100644 --- a/board/cobra5272/Makefile +++ b/board/cobra5272/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o mii.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index b92855050..26adb4abb 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -22,7 +22,8 @@ */ #include -#include +#include +#include int checkboard (void) @@ -32,9 +33,9 @@ int checkboard (void) return 0; }; -phys_size_t initdram (int board_type) +long int initdram (int board_type) { - volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM); + volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR); sdp->sdram_sdtr = 0xf539; sdp->sdram_sdcr = 0x4211; diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds index f99a236a3..872f09439 100644 --- a/board/cobra5272/u-boot.lds +++ b/board/cobra5272/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { _sbss = .; *(.sbss) *(.scommon) diff --git a/board/cogent/Makefile b/board/cogent/Makefile index afa134558..4084c7ebe 100644 --- a/board/cogent/Makefile +++ b/board/cogent/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o +OBJS := mb.o flash.o dipsw.o lcd.o serial.o # pci.o rtc.o par.o kbm.o +SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/cogent/config.mk b/board/cogent/config.mk index 35a5ed3d0..ee779394b 100644 --- a/board/cogent/config.mk +++ b/board/cogent/config.mk @@ -29,5 +29,3 @@ TEXT_BASE = 0xfff00000 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) - -LDSCRIPT := $(SRCTREE)/board/cogent/u-boot.lds diff --git a/board/cogent/lcd.h b/board/cogent/lcd.h index 9e6157ee6..1056eea47 100644 --- a/board/cogent/lcd.h +++ b/board/cogent/lcd.h @@ -70,7 +70,7 @@ /* LCD status values */ #define LCD_OK 0x00 -#define LCD_ERR 0x01 +#define LCD_ERR 0x01 #define LCD_LINE0 0x00 #define LCD_LINE1 0x40 diff --git a/board/cogent/mb.c b/board/cogent/mb.c index 619aea3c0..917132b3f 100644 --- a/board/cogent/mb.c +++ b/board/cogent/mb.c @@ -233,7 +233,7 @@ int misc_init_f (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { #ifdef CONFIG_CMA111 return (32L * 1024L * 1024L); diff --git a/board/cogent/serial.c b/board/cogent/serial.c index d9c27beee..2b595a85a 100644 --- a/board/cogent/serial.c +++ b/board/cogent/serial.c @@ -90,7 +90,7 @@ int serial_tstc (void) #endif /* CONS_NONE */ -#if defined(CONFIG_CMD_KGDB) && \ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && \ defined(CONFIG_KGDB_NONE) #if CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index 59d62e101..5ce2694cb 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -116,7 +117,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug index c33581d25..ddd4678ee 100644 --- a/board/cogent/u-boot.lds.debug +++ b/board/cogent/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/cpc45/Makefile b/board/cpc45/Makefile index 374fdd765..ccb811bd4 100644 --- a/board/cpc45/Makefile +++ b/board/cpc45/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o plx9030.o pd67290.o +OBJS = $(BOARD).o flash.o plx9030.o pd67290.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c index f4e867ce7..51b008591 100644 --- a/board/cpc45/cpc45.c +++ b/board/cpc45/cpc45.c @@ -61,7 +61,7 @@ int checkboard(void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { int m, row, col, bank, i, ref; unsigned long start, end; @@ -240,7 +240,7 @@ int sysControlDisplay (int digit, /* number of digit 0..7 */ return (0); } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #ifdef CFG_PCMCIA_MEM_ADDR volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR; @@ -257,7 +257,7 @@ int pcmcia_init(void) return rc; } -#endif +#endif /* CFG_CMD_PCMCIA */ # ifdef CONFIG_IDE_LED void ide_led (uchar led, uchar status) diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c index d8f4be516..6ca3e7bd7 100644 --- a/board/cpc45/pd67290.c +++ b/board/cpc45/pd67290.c @@ -772,7 +772,7 @@ exit: return rc; } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_off (void) { printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n"); diff --git a/board/cpc45/plx9030.c b/board/cpc45/plx9030.c index 3711ccbd3..99ec39af7 100644 --- a/board/cpc45/plx9030.c +++ b/board/cpc45/plx9030.c @@ -54,7 +54,7 @@ registers (CS3) on CPC45. /* PLX9030 register offsets */ #define P9030_LAS0RR 0x00 -#define P9030_LAS1RR 0x04 +#define P9030_LAS1RR 0x04 #define P9030_LAS2RR 0x08 #define P9030_LAS3RR 0x0c #define P9030_EROMRR 0x10 @@ -72,8 +72,8 @@ registers (CS3) on CPC45. #define P9030_CS1BASE 0x40 #define P9030_CS2BASE 0x44 #define P9030_CS3BASE 0x48 -#define P9030_INTCSR 0x4c -#define P9030_CNTRL 0x50 +#define P9030_INTCSR 0x4c +#define P9030_CNTRL 0x50 #define P9030_GPIOC 0x54 /* typedefs */ diff --git a/board/cpc45/u-boot.lds b/board/cpc45/u-boot.lds new file mode 100644 index 000000000..9ea26aa26 --- /dev/null +++ b/board/cpc45/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cpu86/Makefile b/board/cpu86/Makefile index dcb190703..7a2014d46 100644 --- a/board/cpu86/Makefile +++ b/board/cpu86/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c index 9e76c72d3..3eb5b3542 100644 --- a/board/cpu86/cpu86.c +++ b/board/cpu86/cpu86.c @@ -273,7 +273,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; @@ -312,7 +312,7 @@ phys_size_t initdram (int board_type) return (psize); } -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) extern void doc_probe (ulong physadr); void doc_init (void) { diff --git a/board/cpu86/u-boot.lds b/board/cpu86/u-boot.lds new file mode 100644 index 000000000..05f29c6ed --- /dev/null +++ b/board/cpu86/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cpu87/Makefile b/board/cpu87/Makefile index dcb190703..26f53ede4 100644 --- a/board/cpu87/Makefile +++ b/board/cpu87/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c index f5a5de5d8..e8c2614eb 100644 --- a/board/cpu87/cpu87.c +++ b/board/cpu87/cpu87.c @@ -274,7 +274,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; @@ -294,15 +294,15 @@ phys_size_t initdram (int board_type) */ size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, (uchar *) CFG_SDRAM_BASE); - + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, (uchar *) CFG_SDRAM_BASE); - + size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL, (uchar *) CFG_SDRAM_BASE); - + psize = max(size8,max(size9,size10)); - + if (psize == size8) { psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, (uchar *) CFG_SDRAM_BASE); @@ -321,7 +321,7 @@ phys_size_t initdram (int board_type) return (psize); } -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) extern void doc_probe (ulong physadr); void doc_init (void) { diff --git a/board/cpu87/u-boot.lds b/board/cpu87/u-boot.lds new file mode 100644 index 000000000..fb7e665b6 --- /dev/null +++ b/board/cpu87/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cradle/Makefile b/board/cradle/Makefile index 1ae785db5..265d50043 100644 --- a/board/cradle/Makefile +++ b/board/cradle/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := cradle.o flash.o +OBJS := cradle.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/cradle/u-boot.lds b/board/cradle/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/cradle/u-boot.lds +++ b/board/cradle/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index f0dfa07fd..a7114eb07 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -23,7 +23,7 @@ #include #include -#include <4xx_i2c.h> +#include <405gp_i2c.h> #include #include #include @@ -139,15 +139,8 @@ int misc_init_r (void) struct rtc_time tm; char bootcmd[32]; - hdr = (image_header_t *) (CFG_MONITOR_BASE - image_get_header_size ()); -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - timestamp = (time_t)image_get_time (hdr); + hdr = (image_header_t *) (CFG_MONITOR_BASE - sizeof (image_header_t)); + timestamp = (time_t) hdr->ih_time; to_tm (timestamp, &tm); printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); @@ -170,16 +163,16 @@ int misc_init_r (void) } /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (L1_MEMSIZE); } /* ------------------------------------------------------------------------- */ /* stubs so we can print dates w/o any nvram RTC.*/ -int rtc_get (struct rtc_time *tmp) +void rtc_get (struct rtc_time *tmp) { - return 0; + return; } void rtc_set (struct rtc_time *tmp) { diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h index c3a0b8f5e..1b4182448 100644 --- a/board/cray/L1/L1.h +++ b/board/cray/L1/L1.h @@ -26,7 +26,7 @@ * * Start Address Length * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash ----------------- - * | Failsafe Linux Image | (1M) + * | Failsafe Linux Image | (1M) * +=======================+ 0xFFD0_0000 * | (Reserved FlashFiles) | (1M) * +=======================+ 0xFFE0_0000 @@ -36,7 +36,7 @@ * | U N U S E D | * | | * +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes) - * | environment settings | (64k) + * | environment settings | (64k) * +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes) * | U-Boot | 0xFFFE_0040 _start of U-Boot * | | 0xFFFE_FFFC reset vector - branch to _start diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile index 21b513c29..bfe0922eb 100644 --- a/board/cray/L1/Makefile +++ b/board/cray/L1/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,41 +23,35 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - # HACK: depend needs bootscript.c, which needs tools/mkimage, which is not # built in the depend stage. So... put bootscript.o here, not in OBJS -$(LIB): $(OBJS) $(SOBJS) $(obj)bootscript.o - $(AR) $(ARFLAGS) $@ $^ +$(LIB): $(OBJS) $(SOBJS) bootscript.o + $(AR) crv $@ $^ clean: - rm -f $(SOBJS) $(OBJS) $(obj)bootscript.c \ - $(obj)bootscript.image $(obj)bootscript.o + rm -f $(SOBJS) $(OBJS) bootscript.c bootscript.image bootscript.o distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend -$(obj)$(BOARD).o : $(src)$(BOARD).c $(obj)bootscript.o +$(BOARD).o : $(BOARD).c bootscript.o -$(obj)bootscript.c: $(obj)bootscript.image +bootscript.c: bootscript.image od -t x1 -v -A x $^ | awk -f x2c.awk > $@ -$(obj)bootscript.image: $(src)bootscript.hush $(src)Makefile - -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $(src)bootscript.hush $@ +bootscript.image: bootscript.hush Makefile + -$(TOPDIR)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d bootscript.hush $@ ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index 4b6b3f400..72a10d3a1 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -134,3 +134,14 @@ ext_bus_cntlr_init: mtdcr ebccfgd,r4 blr + +/*----------------------------------------------------------------------------- */ +/* Function: sdram_init */ +/* Description: Configures SDRAM memory banks. */ +/* NOTE: for CrayL1 we have ECC memory, so enable it. */ +/*....now done in C in L1.c:init_sdram for readability. */ +/*----------------------------------------------------------------------------- */ + .globl sdram_init + +sdram_init: + blr diff --git a/board/cray/L1/u-boot.lds b/board/cray/L1/u-boot.lds index a6bbef3dc..cf4bbb921 100644 --- a/board/cray/L1/u-boot.lds +++ b/board/cray/L1/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -39,11 +40,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -65,7 +66,7 @@ SECTIONS board/cray/L1/init.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -140,7 +141,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug index 0552994f4..1608f8cda 100644 --- a/board/cray/L1/u-boot.lds.debug +++ b/board/cray/L1/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/csb226/Makefile b/board/csb226/Makefile index c12dbea9c..5b311a945 100644 --- a/board/csb226/Makefile +++ b/board/csb226/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := csb226.o flash.o +OBJS := csb226.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/csb226/lowlevel_init.S b/board/csb226/lowlevel_init.S index 4c9f10ffb..aa9dcba6f 100644 --- a/board/csb226/lowlevel_init.S +++ b/board/csb226/lowlevel_init.S @@ -43,7 +43,7 @@ _TEXT_BASE: /* - * Memory setup + * Memory setup */ .globl lowlevel_init @@ -129,8 +129,8 @@ lowlevel_init: /*loop: */ /* */ /* ldr r0, =0xB0070001 */ -/* ldr r1, =_LED */ -/* str r0, [r1] / hex display */ +/* ldr r1, =_LED */ +/* str r0, [r1] / hex display */ /* ---------------------------------------------------------------- */ @@ -239,7 +239,7 @@ mem_init: /* Before accessing MDREFR we need a valid DRI field, so we set */ /* this to power on defaults + DRI field. */ - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CFG_MDREFR_VAL ldr r2, =0xFFF and r3, r3, r2 ldr r4, =0x03ca4000 diff --git a/board/csb226/u-boot.lds b/board/csb226/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/csb226/u-boot.lds +++ b/board/csb226/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/csb272/Makefile b/board/csb272/Makefile index 6d42bff75..926e06503 100644 --- a/board/csb272/Makefile +++ b/board/csb272/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,32 +23,29 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -#COBJS = $(BOARD).o flash.o -#COBJS = $(BOARD).o strataflash.o -COBJS = $(BOARD).o +#OBJS = $(BOARD).o flash.o +#OBJS = $(BOARD).o strataflash.o +OBJS = $(BOARD).o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 5a585ae37..24c6f0d98 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -27,8 +27,6 @@ #include #include -void sdram_init(void); - /* * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator * @@ -120,19 +118,12 @@ int checkboard(void) * configured by initialization code * */ -phys_size_t initdram (int board_type) +long initdram (int board_type) { ulong tot_size; ulong bank_size; ulong tmp; - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in cpu/ppc4xx - */ - sdram_init(); - tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/csb272/u-boot.lds b/board/csb272/u-boot.lds index 947fbd638..d75d6d1ce 100644 --- a/board/csb272/u-boot.lds +++ b/board/csb272/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -65,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -141,7 +142,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/csb472/Makefile b/board/csb472/Makefile index 6d42bff75..926e06503 100644 --- a/board/csb472/Makefile +++ b/board/csb472/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,32 +23,29 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -#COBJS = $(BOARD).o flash.o -#COBJS = $(BOARD).o strataflash.o -COBJS = $(BOARD).o +#OBJS = $(BOARD).o flash.o +#OBJS = $(BOARD).o strataflash.o +OBJS = $(BOARD).o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 9dc130efc..833bbce92 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -27,8 +27,6 @@ #include #include -void sdram_init(void); - /* * board_early_init_f: do early board initialization * @@ -88,19 +86,12 @@ int checkboard(void) * configured by initialization code * */ -phys_size_t initdram (int board_type) +long initdram (int board_type) { ulong tot_size; ulong bank_size; ulong tmp; - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in cpu/ppc4xx - */ - sdram_init(); - tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/csb472/u-boot.lds b/board/csb472/u-boot.lds index de3643eed..14ac3fb4f 100644 --- a/board/csb472/u-boot.lds +++ b/board/csb472/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -65,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -141,7 +142,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/csb637/Makefile b/board/csb637/Makefile index ab28434a3..61d5a35dd 100644 --- a/board/csb637/Makefile +++ b/board/csb637/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := csb637.o +OBJS := csb637.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/csb637/csb637.c b/board/csb637/csb637.c index fbc3c87c5..aeb1a138d 100644 --- a/board/csb637/csb637.c +++ b/board/csb637/csb637.c @@ -57,7 +57,7 @@ int dram_init (void) } #ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) /* * Name: @@ -77,5 +77,5 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) p_phyops->AutoNegotiate = bcm5221_AutoNegotiate; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ #endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/csb637/u-boot.lds b/board/csb637/u-boot.lds index 3b7977672..76df6b2af 100644 --- a/board/csb637/u-boot.lds +++ b/board/csb637/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/cu824/Makefile b/board/cu824/Makefile index dcb190703..7a2014d46 100644 --- a/board/cu824/Makefile +++ b/board/cu824/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c index ecf632894..3edd27a3e 100644 --- a/board/cu824/cu824.c +++ b/board/cu824/cu824.c @@ -45,7 +45,7 @@ int checkboard (void) return 0; } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { long size; long new_bank0_end; diff --git a/board/cu824/u-boot.lds b/board/cu824/u-boot.lds new file mode 100644 index 000000000..7be85e441 --- /dev/null +++ b/board/cu824/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/dave/B2/B2.c b/board/dave/B2/B2.c index ec742adc7..64fe948fc 100644 --- a/board/dave/B2/B2.c +++ b/board/dave/B2/B2.c @@ -78,16 +78,16 @@ int board_init (void) INTCON = 0x05; /* - Configure chip ethernet interrupt as High level - Port G EINT 0-7 EINT0 -> CHIP ETHERNET + Configure chip ethernet interrupt as High level + Port G EINT 0-7 EINT0 -> CHIP ETHERNET */ temp = EXTINT; - temp &= ~0x7; + temp &= ~0x7; temp |= 0x1; /*LEVEL_HIGH*/ EXTINT = temp; /* - Reset SMSC LAN91C96 chip + Reset SMSC LAN91C96 chip */ temp= PCONF; temp |= 0x00000040; diff --git a/board/dave/B2/Makefile b/board/dave/B2/Makefile index e70d2c8e3..548fd528b 100644 --- a/board/dave/B2/Makefile +++ b/board/dave/B2/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2002 # Sysgo Real-Time Solutions, GmbH # Marius Groeger @@ -27,29 +24,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := B2.o flash.o +OBJS := B2.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/dave/B2/u-boot.lds b/board/dave/B2/u-boot.lds index 8c10d47ae..e10ac437e 100644 --- a/board/dave/B2/u-boot.lds +++ b/board/dave/B2/u-boot.lds @@ -53,6 +53,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile index 1869f8cee..581a5802b 100644 --- a/board/dave/PPChameleonEVB/Makefile +++ b/board/dave/PPChameleonEVB/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o nand.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o nand.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index c9b288a41..e8302d9fc 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -203,7 +203,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c index 09c0b043e..40a827c3e 100644 --- a/board/dave/PPChameleonEVB/nand.c +++ b/board/dave/PPChameleonEVB/nand.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include @@ -105,7 +105,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init(struct nand_chip *nand) { nand->hwcontrol = ppchameleonevb_hwcontrol; @@ -113,6 +113,5 @@ int board_nand_init(struct nand_chip *nand) nand->eccmode = NAND_ECC_SOFT; nand->chip_delay = NAND_BIG_DELAY_US; nand->options = NAND_SAMSUNG_LP_OPTIONS; - return 0; } -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index 3037a049c..481d29187 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -135,7 +136,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/dbau1x00/Makefile b/board/dbau1x00/Makefile index afe02c27c..d9b0e2d25 100644 --- a/board/dbau1x00/Makefile +++ b/board/dbau1x00/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,23 +23,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o SOBJS = lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c index 629dc317e..d29e8d591 100644 --- a/board/dbau1x00/dbau1x00.c +++ b/board/dbau1x00/dbau1x00.c @@ -25,9 +25,8 @@ #include #include #include -#include -phys_size_t initdram(int board_type) +long int initdram(int board_type) { /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ @@ -52,7 +51,7 @@ int checkboard (void) *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - proc_id = read_c0_prid(); + proc_id = read_32bit_cp0_register(CP0_PRID); switch (proc_id >> 24) { case 0: @@ -78,9 +77,6 @@ int checkboard (void) default: printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); } - - set_io_port_base(0); - #ifdef CONFIG_IDE_PCMCIA /* Enable 3.3 V on slot 0 ( VCC ) No 5V */ diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 13e6bfcf3..14a78465f 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -1,6 +1,7 @@ /* Memory sub-system initialization code */ #include +#include #include #include #include @@ -585,5 +586,5 @@ noCacheJump: sw t1, 0(t0) sync - jr ra + j ra nop diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 1e1c5590d..10c991798 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -43,28 +43,27 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = .; - _gp = ALIGN(16) + 0x7ff0; + . = ALIGN(4); + .sdata : { *(.sdata) } - .got : { - __got_start = .; - *(.got) - __got_end = .; - } + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; .sdata : { *(.sdata) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; . = ALIGN(4); - .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .sbss : { *(.sbss) } + .bss : { *(.bss) } uboot_end = .; } diff --git a/board/delta/Makefile b/board/delta/Makefile index 648e00c31..e744eec2e 100644 --- a/board/delta/Makefile +++ b/board/delta/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,29 +24,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := delta.o nand.o +OBJS := delta.o nand.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/delta/delta.c b/board/delta/delta.c index 6e227748b..b127ac8ca 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -1,6 +1,10 @@ /* - * (C) Copyright 2006 - * DENX Software Engineering + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger * * See file CREDITS for list of people who contributed to this * project. @@ -94,6 +98,7 @@ int board_late_init(void) return 0; } + /* * Magic Key Handling, mainly copied from board/lwmon/lwmon.c */ @@ -319,12 +324,6 @@ static void init_DA9030() return; } - val = 0x80; - if(i2c_write(addr, IRQ_MASK_B, 1, &val, 1)) { - printf("Error accessing DA9030 via i2c.\n"); - return; - } - i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */ i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */ i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */ diff --git a/board/delta/nand.c b/board/delta/nand.c index 5024056bc..fe648fc1f 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -22,7 +22,7 @@ #include -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #if !defined(CFG_NAND_LEGACY) #include @@ -254,7 +254,7 @@ static unsigned long dfc_wait_event(unsigned long event) break; } if(get_delta(start) > timeout) { - DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event); + DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event); return 0xff000000; } @@ -448,7 +448,7 @@ static void dfc_gpio_init(void) * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init(struct nand_chip *nand) { unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; @@ -576,7 +576,6 @@ int board_nand_init(struct nand_chip *nand) nand->cmdfunc = dfc_cmdfunc; nand->autooob = &delta_oob; nand->badblock_pattern = &delta_bbt_descr; - return 0; } #else diff --git a/board/delta/u-boot.lds b/board/delta/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/delta/u-boot.lds +++ b/board/delta/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/dnp1110/Makefile b/board/dnp1110/Makefile index c56e9d1e8..eaa38bc3c 100644 --- a/board/dnp1110/Makefile +++ b/board/dnp1110/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := dnp1110.o flash.o +OBJS := dnp1110.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/dnp1110/u-boot.lds b/board/dnp1110/u-boot.lds index 6bd06270a..258bece23 100644 --- a/board/dnp1110/u-boot.lds +++ b/board/dnp1110/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/eXalion/Makefile b/board/eXalion/Makefile index 98601a3f3..cfbf465bb 100644 --- a/board/eXalion/Makefile +++ b/board/eXalion/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o +OBJS = $(BOARD).o +SOBJS = -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c index 385b498d0..2e3f51998 100644 --- a/board/eXalion/eXalion.c +++ b/board/eXalion/eXalion.c @@ -52,7 +52,7 @@ int checkflash (void) return (0); } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { int i, cnt; volatile uchar *base = CFG_SDRAM_BASE; diff --git a/board/eXalion/u-boot.lds b/board/eXalion/u-boot.lds new file mode 100644 index 000000000..eaee3fdef --- /dev/null +++ b/board/eXalion/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/eltec/bab7xx/Makefile b/board/eltec/bab7xx/Makefile index 1e76d25f7..7d8ed26b5 100644 --- a/board/eltec/bab7xx/Makefile +++ b/board/eltec/bab7xx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,30 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o +OBJS = $(BOARD).o flash.o pci.o misc.o el_srom.o dc_srom.o l2cache.o SOBJS = asm_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c index af5235237..555475e4d 100644 --- a/board/eltec/bab7xx/bab7xx.c +++ b/board/eltec/bab7xx/bab7xx.c @@ -162,7 +162,7 @@ long int dram_size (int board_type) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return dram_size (board_type); } diff --git a/board/eltec/bab7xx/u-boot.lds b/board/eltec/bab7xx/u-boot.lds index 1a95755ab..d89eb6cff 100644 --- a/board/eltec/bab7xx/u-boot.lds +++ b/board/eltec/bab7xx/u-boot.lds @@ -26,6 +26,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -37,11 +38,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -125,7 +126,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/eltec/elppc/Makefile b/board/eltec/elppc/Makefile index 24cbfeee3..76b2cfe62 100644 --- a/board/eltec/elppc/Makefile +++ b/board/eltec/elppc/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,30 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o +OBJS = $(BOARD).o flash.o pci.o misc.o mpc107_i2c.o eepro100_srom.o SOBJS = asm_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/eltec/elppc/eepro100_srom.c b/board/eltec/elppc/eepro100_srom.c index 4a9da542f..f021c50cd 100644 --- a/board/eltec/elppc/eepro100_srom.c +++ b/board/eltec/elppc/eepro100_srom.c @@ -31,83 +31,82 @@ #include #include "srom.h" -extern int eepro100_write_eeprom (struct eth_device *dev, - int location, int addr_len, - unsigned short data); +extern int eepro100_write_eeprom (struct eth_device* dev, + int location, int addr_len, unsigned short data); /*----------------------------------------------------------------------------*/ unsigned short eepro100_srom_checksum (unsigned short *sromdata) { - unsigned short sum = 0; - unsigned int i; + unsigned short sum = 0; + unsigned int i; - for (i = 0; i < (EE_SIZE - 1); i++) { - sum += sromdata[i]; - } - return (EE_CHECKSUM - sum); + for (i = 0; i < (EE_SIZE-1); i++) + { + sum += sromdata[i]; + } + return (EE_CHECKSUM - sum); } /*----------------------------------------------------------------------------*/ int eepro100_srom_store (unsigned short *source) { - int count; - struct eth_device onboard_dev; + int count; + struct eth_device onboard_dev; - /* get onboard network iobase */ - pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0, - (unsigned int *) &onboard_dev.iobase); - onboard_dev.iobase &= ~0xf; + /* get onboard network iobase */ + pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0, + (unsigned int *)&onboard_dev.iobase); + onboard_dev.iobase &= ~0xf; - source[63] = eepro100_srom_checksum (source); + source[63] = eepro100_srom_checksum (source); - for (count = 0; count < EE_SIZE; count++) { - if (eepro100_write_eeprom ((struct eth_device *) &onboard_dev, - count, EE_ADDR_BITS, - SROM_SHORT (source)) == -1) { - return -1; - } - source++; - } - return 0; + for (count=0; count < EE_SIZE; count++) + { + if ( eepro100_write_eeprom ((struct eth_device*)&onboard_dev, + count, EE_ADDR_BITS, SROM_SHORT(source)) == -1 ) + return -1; + source++; + } + return 0; } /*----------------------------------------------------------------------------*/ #ifdef EEPRO100_SROM_CHECK -extern int read_eeprom (struct eth_device *dev, int location, int addr_len); +extern int read_eeprom (struct eth_device* dev, int location, int addr_len); void eepro100_srom_load (unsigned short *destination) { - int count; - struct eth_device onboard_dev; - + int count; + struct eth_device onboard_dev; #ifdef DEBUG - int lr = 0; - - printf ("eepro100_srom_download:\n"); + int lr = 0; + printf ("eepro100_srom_download:\n"); #endif - /* get onboard network iobase */ - pci_read_config_dword (PCI_BDF (0, 0x10, 0), PCI_BASE_ADDRESS_0, - &onboard_dev.iobase); - onboard_dev.iobase &= ~0xf; + /* get onboard network iobase */ + pci_read_config_dword(PCI_BDF(0,0x10,0), PCI_BASE_ADDRESS_0, + &onboard_dev.iobase); + onboard_dev.iobase &= ~0xf; - memset (destination, 0x65, 128); + memset (destination, 0x65, 128); - for (count = 0; count < 0x40; count++) { - *destination++ = read_eeprom ((struct eth_device *) &onboard_dev, - count, EE_ADDR_BITS); + for (count=0; count < 0x40; count++) + { + *destination++ = read_eeprom (struct eth_device*)&onboard_dev, + count, EE_ADDR_BITS); #ifdef DEBUG - printf ("%04x ", *(destination - 1)); - if (lr++ == 7) { - printf ("\n"); - lr = 0; - } -#endif + printf ("%04x ", *(destination - 1)); + if (lr++ == 7) + { + printf("\n"); + lr = 0; } +#endif + } } #endif /* EEPRO100_SROM_CHECK */ diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c index 1b70605e2..108adb13d 100644 --- a/board/eltec/elppc/elppc.c +++ b/board/eltec/elppc/elppc.c @@ -104,7 +104,7 @@ long int dram_size (int board_type) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return dram_size (board_type); } diff --git a/board/eltec/elppc/u-boot.lds b/board/eltec/elppc/u-boot.lds index 1a95755ab..d89eb6cff 100644 --- a/board/eltec/elppc/u-boot.lds +++ b/board/eltec/elppc/u-boot.lds @@ -26,6 +26,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -37,11 +38,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -125,7 +126,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/eltec/mhpc/Makefile b/board/eltec/mhpc/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/eltec/mhpc/Makefile +++ b/board/eltec/mhpc/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c index 3666791e9..0ffbdf0e5 100644 --- a/board/eltec/mhpc/mhpc.c +++ b/board/eltec/mhpc/mhpc.c @@ -251,7 +251,7 @@ int misc_init_r (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds index 85117aa56..7099fc40d 100644 --- a/board/eltec/mhpc/u-boot.lds +++ b/board/eltec/mhpc/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -118,7 +119,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug index 85072feda..3165d5634 100644 --- a/board/eltec/mhpc/u-boot.lds.debug +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile index 86b887029..986608bb1 100644 --- a/board/emk/top5200/Makefile +++ b/board/emk/top5200/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,32 +23,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o +OBJS := $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c index 27886261c..4508438ca 100644 --- a/board/emk/top5200/top5200.c +++ b/board/emk/top5200/top5200.c @@ -32,7 +32,7 @@ * initialize SDRAM/DDRAM controller. * TBD: get data from I2C EEPROM *****************************************************************************/ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT @@ -184,13 +184,15 @@ void pci_init_board(void) /***************************************************************************** * provide the IDE Reset Function *****************************************************************************/ -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL void init_ide_reset (void) { debug ("init_ide_reset\n"); - /* Configure PSC1_4 as GPIO output for ATA reset */ + /* Configure PSC1_4 as GPIO output for ATA reset */ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; } @@ -200,9 +202,9 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; } } -#endif +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/emk/top5200/u-boot.lds b/board/emk/top5200/u-boot.lds new file mode 100644 index 000000000..f23432ecf --- /dev/null +++ b/board/emk/top5200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/emk/top860/Makefile b/board/emk/top860/Makefile index 88abd76c5..a74dd2fa2 100644 --- a/board/emk/top860/Makefile +++ b/board/emk/top860/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,26 +22,19 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o +OBJS = $(BOARD).o ../common/flash.o ../common/vpd.o ../common/am79c874.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c index aca4991f5..84afaaa2b 100644 --- a/board/emk/top860/top860.c +++ b/board/emk/top860/top860.c @@ -76,7 +76,7 @@ int checkboard (void) /***************************************************************************** * Initialize DRAM controller *****************************************************************************/ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds index 97ef89a40..b3747e424 100644 --- a/board/emk/top860/u-boot.lds +++ b/board/emk/top860/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -118,7 +119,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug index 5d97095c1..580575a5a 100644 --- a/board/emk/top860/u-boot.lds.debug +++ b/board/emk/top860/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/ep7312/Makefile b/board/ep7312/Makefile index 776a444ee..c53a3c7a0 100644 --- a/board/ep7312/Makefile +++ b/board/ep7312/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2002 # Sysgo Real-Time Solutions, GmbH # Marius Groeger @@ -27,29 +24,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := ep7312.o flash.o +OBJS := ep7312.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/ep7312/u-boot.lds b/board/ep7312/u-boot.lds index 4a89cebaa..1122d7521 100644 --- a/board/ep7312/u-boot.lds +++ b/board/ep7312/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile index dc40d9b94..8b1099319 100644 --- a/board/ep8248/Makefile +++ b/board/ep8248/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o +OBJS := $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c index 4cfb2acc8..69975caa2 100644 --- a/board/ep8248/ep8248.c +++ b/board/ep8248/ep8248.c @@ -208,7 +208,7 @@ int board_early_init_f (void) return 0; } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { vu_char *bcsr = (vu_char *)CFG_BCSR; long int msize = 16L << (bcsr[2] & 3); diff --git a/board/ep8248/u-boot.lds b/board/ep8248/u-boot.lds new file mode 100644 index 000000000..18c4b46f4 --- /dev/null +++ b/board/ep8248/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/ep8260/Makefile b/board/ep8260/Makefile index b8bf32034..477e5eede 100644 --- a/board/ep8260/Makefile +++ b/board/ep8260/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o mii_phy.o +OBJS = $(BOARD).o flash.o mii_phy.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/ep8260/ep8260.c b/board/ep8260/ep8260.c index 0e43c6df9..b9e1df43d 100644 --- a/board/ep8260/ep8260.c +++ b/board/ep8260/ep8260.c @@ -243,7 +243,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/ep8260/flash.c b/board/ep8260/flash.c index 966a34526..278d606b3 100644 --- a/board/ep8260/flash.c +++ b/board/ep8260/flash.c @@ -72,7 +72,7 @@ ulong flash_get_size( ulong baseaddr, flash_info_t *info ) info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; info->size = 0; - return (0); /* no or unknown flash */ + return (0); /* no or unknown flash */ } flashtest_h = V_ULONG(baseaddr + 8); /* device ID */ @@ -91,11 +91,11 @@ ulong flash_get_size( ulong baseaddr, flash_info_t *info ) case AMD_ID_LV640U: /* AMDLV640 and AMDLV641 have same ID */ info->flash_id += FLASH_AMLV640U; info->sector_count = 128; - info->size = 0x02000000; /* 4 * 8 MB = 32 MB */ + info->size = 0x02000000; /* 4 * 8 MB = 32 MB */ break; default: info->flash_id = FLASH_UNKNOWN; - return(0); /* no or unknown flash */ + return(0); /* no or unknown flash */ } if(flashtest_h == AMD_ID_LV640U) { diff --git a/board/ep8260/u-boot.lds b/board/ep8260/u-boot.lds new file mode 100644 index 000000000..4250e83f7 --- /dev/null +++ b/board/ep8260/u-boot.lds @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2001, 2002, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/opt/cross/lib); SEARCH_DIR(/opt/cross/powerpc-linux/lib); +/* SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); */ +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) +/* common/environment.o(.text) */ + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ep88x/Makefile b/board/ep88x/Makefile index 6b3706daa..9123a8026 100644 --- a/board/ep88x/Makefile +++ b/board/ep88x/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # Copyright (C) 2004 Arabella Software Ltd. # Yuli Barcohen # @@ -26,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o +OBJS := $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/ep88x/ep88x.c b/board/ep88x/ep88x.c index 92e5f0c12..5f57f36bb 100644 --- a/board/ep88x/ep88x.c +++ b/board/ep88x/ep88x.c @@ -86,7 +86,7 @@ int board_early_init_f (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long int msize; volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds index 354514233..1d2a7d764 100644 --- a/board/ep88x/u-boot.lds +++ b/board/ep88x/u-boot.lds @@ -33,11 +33,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -109,7 +109,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/eric/Makefile b/board/eric/Makefile index 81a455202..f55e7e2f8 100644 --- a/board/eric/Makefile +++ b/board/eric/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/eric/eric.c b/board/eric/eric.c index 972d485b5..5413ae15c 100644 --- a/board/eric/eric.c +++ b/board/eric/eric.c @@ -31,8 +31,6 @@ #define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */ #define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */ -void sdram_init(void); - int board_early_init_f (void) { @@ -121,7 +119,7 @@ int checkboard (void) */ /* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { #ifndef CONFIG_ERIC int i; @@ -129,12 +127,6 @@ phys_size_t initdram (int board_type) int TotalSize; #endif - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in cpu/ppc4xx - */ - sdram_init(); #ifdef CONFIG_ERIC /* diff --git a/board/eric/flash.c b/board/eric/flash.c index 2c7d2a08c..c08a76026 100644 --- a/board/eric/flash.c +++ b/board/eric/flash.c @@ -564,17 +564,17 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) info->flash_id += FLASH_28F320J3A; info->sector_count = 32; info->size = 0x00400000; - break; /* => 32 MBit */ + break; /* => 32 MBit */ case (INTEL_ID_28F640J3A & FLASH_ID_MASK): info->flash_id += FLASH_28F640J3A; info->sector_count = 64; info->size = 0x00800000; - break; /* => 64 MBit */ + break; /* => 64 MBit */ case (INTEL_ID_28F128J3A & FLASH_ID_MASK): info->flash_id += FLASH_28F128J3A; info->sector_count = 128; info->size = 0x01000000; - break; /* => 128 MBit */ + break; /* => 128 MBit */ default: /* FIXME*/ @@ -981,151 +981,148 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * 2 - Flash not erased */ #ifndef CFG_FLASH_16BIT -static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t *info, ulong dest, ulong data) { - vu_long *addr = (vu_long *) (info->start[0]); - ulong start, barf; + vu_long *addr = (vu_long*)(info->start[0]); + ulong start,barf; int flag; /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { + if ((*((vu_long *)dest) & data) != data) { return (2); } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + flag = disable_interrupts(); - if (info->flash_id > FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - } else { - /* intel stuff */ - *addr = 0x00400040; - } - *((vu_long *) dest) = data; + if(info->flash_id > FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + } else { + /* intel stuff */ + *addr = 0x00400040; + } + *((vu_long *)dest) = data; /* re-enable interrupts if necessary */ if (flag) - enable_interrupts (); + enable_interrupts(); /* data polling for D7 */ start = get_timer (0); - if (info->flash_id > FLASH_AMD_COMP) { + if(info->flash_id > FLASH_AMD_COMP) { - while ((*((vu_long *) dest) & 0x00800080) != - (data & 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); } - - } else { - - while (!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - - if (addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if (barf) { - barf >>= 16; - } else { - barf = addr[0] & 0x0000003A; - } - printf ("\nFlash write error at address %lx\n", - (unsigned long) dest); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if (barf & 0x0010) - printf ("Programming error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - return (2); - } - - - } - - return (0); - } + } else { + + while(!(addr[0] & 0x00800080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + + if( addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if( barf ) { + barf >>=16; + } else { + barf = addr[0] & 0x0000003A; + } + printf("\nFlash write error at address %lx\n",(unsigned long)dest); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if(barf & 0x0010) printf("Programming error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + return(2); + } + + + } + + return (0); + +} + #else -static int write_short (flash_info_t * info, ulong dest, ushort data) +static int write_short (flash_info_t *info, ulong dest, ushort data) { - vu_short *addr = (vu_short *) (info->start[0]); - ulong start, barf; + vu_short *addr = (vu_short*)(info->start[0]); + ulong start,barf; int flag; /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *) dest) & data) != data) { + if ((*((vu_short *)dest) & data) != data) { return (2); } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + flag = disable_interrupts(); - if (info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - } else { - /* intel stuff */ - *addr = 0x00D0; - *addr = 0x0040; - } - *((vu_short *) dest) = data; + if(info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x00A0; + } else { + /* intel stuff */ + *addr = 0x00D0; + *addr = 0x0040; + } + *((vu_short *)dest) = data; /* re-enable interrupts if necessary */ if (flag) - enable_interrupts (); + enable_interrupts(); /* data polling for D7 */ start = get_timer (0); - if (info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } + if(info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); } - - } else { - /* intel stuff */ - while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) - return (1); - } - - if (addr[0] & 0x003A) { /* check for error */ - barf = addr[0] & 0x003A; - printf ("\nFlash write error at address %lx\n", - (unsigned long) dest); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if (barf & 0x0010) - printf ("Programming error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - return (2); - } - *addr = 0x00B0; - *addr = 0x0070; - while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) - return (1); - } - *addr = 0x00FF; } + + } else { + /* intel stuff */ + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + } + + if( addr[0] & 0x003A) { /* check for error */ + barf = addr[0] & 0x003A; + printf("\nFlash write error at address %lx\n",(unsigned long)dest); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if(barf & 0x0010) printf("Programming error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + return(2); + } + *addr = 0x00B0; + *addr = 0x0070; + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + } + + *addr = 0x00FF; + + } + return (0); + } + + #endif -/*-----------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------- + */ diff --git a/board/eric/u-boot.lds b/board/eric/u-boot.lds index 00e35a6b8..4a0e5b4ae 100644 --- a/board/eric/u-boot.lds +++ b/board/eric/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -65,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -140,7 +141,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile index 0fadf814e..67cf29b32 100644 --- a/board/esd/adciop/Makefile +++ b/board/esd/adciop/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,32 +23,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/pci.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/pci.o $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/adciop/adciop.c b/board/esd/adciop/adciop.c index 0f655b78a..7a11a12ce 100644 --- a/board/esd/adciop/adciop.c +++ b/board/esd/adciop/adciop.c @@ -79,7 +79,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (16 * 1024 * 1024); } diff --git a/board/esd/adciop/u-boot.lds b/board/esd/adciop/u-boot.lds index db65fe69b..ef937dd01 100644 --- a/board/esd/adciop/u-boot.lds +++ b/board/esd/adciop/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -126,7 +127,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile index 911460655..8529ec70c 100644 --- a/board/esd/apc405/Makefile +++ b/board/esd/apc405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,34 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o \ - ../common/misc.o \ - ../common/auto_update.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o strataflash.o ../common/misc.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 83657c8d5..078df001e 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -1,7 +1,4 @@ /* - * (C) Copyright 2005-2008 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * * (C) Copyright 2001-2003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * @@ -26,22 +23,17 @@ #include #include -#include #include #include -#include -#include -#include DECLARE_GLOBAL_DATA_PTR; -#undef FPGA_DEBUG +#if 0 +#define FPGA_DEBUG +#endif extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern void lxt971_no_sleep(void); -extern ulong flash_get_size (ulong base, int banknum); - -int flash_banks = CFG_MAX_FLASH_BANKS_DETECT; /* fpga configuration data - gzip compressed and generated by bin2c */ const unsigned char fpgadata[] = @@ -54,94 +46,82 @@ const unsigned char fpgadata[] = */ #include "../common/fpga.c" + /* Prototypes */ int gunzip(void *, int, unsigned char *, unsigned long *); + #ifdef CONFIG_LCD_USED /* logo bitmap data - gzip compressed and generated by bin2c */ unsigned char logo_bmp[] = { -#include "logo_640_480_24bpp.c" +#include CFG_LCD_LOGO_NAME }; /* * include common lcd code (for esd boards) */ #include "../common/lcd.c" -#include "../common/s1d13505_640_480_16bpp.h" -#include "../common/s1d13806_640_480_16bpp.h" + +#include CFG_LCD_HEADER_NAME #endif /* CONFIG_LCD_USED */ -/* - * include common auto-update code (for esd boards) - */ -#include "../common/auto_update.h" - -au_image_t au_image[] = { - {"preinst.img", 0, -1, AU_SCRIPT}, - {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT}, - {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT}, - {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT}, - {"work.img", 0xfe500000, 0x01400000, AU_NOR}, - {"data.img", 0xff900000, 0x00580000, AU_NOR}, - {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT}, - {"postinst.img", 0, 0, AU_SCRIPT}, -}; - -int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); int board_revision(void) { unsigned long cntrl0Reg; - volatile unsigned long value; + unsigned long value; /* * Get version of APC405 board from GPIO's */ - /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */ + /* + * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) + */ cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03800000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000); + mtdcr(cntrl0, cntrl0Reg | 0x03000000); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); + udelay(1000); /* wait some time before reading input */ + value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ - /* wait some time before reading input */ - udelay(1000); - - /* get config bits */ - value = in_be32((void*)GPIO0_IR) & 0x001c0000; /* * Restore GPIO settings */ mtdcr(cntrl0, cntrl0Reg); switch (value) { - case 0x001c0000: - /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */ - return 2; - case 0x000c0000: - /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */ - return 3; case 0x00180000: - /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */ - return 6; - case 0x00140000: - /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */ - return 8; + /* CS2==1 && CS3==1 -> version <= 1.2 */ + return 2; + case 0x00080000: + /* CS2==0 && CS3==1 -> version 1.3 */ + return 3; +#if 0 /* not yet manufactured ! */ + case 0x00100000: + /* CS2==1 && CS3==0 -> version 1.4 */ + return 4; + case 0x00000000: + /* CS2==0 && CS3==0 -> version 1.5 */ + return 5; +#endif default: /* should not be reached! */ return 0; } } + int board_early_init_f (void) { /* - * First pull fpga-prg pin low, to disable fpga logic + * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) */ - out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ - out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ - out_be32((void*)GPIO0_OR, 0); /* pull prg low */ + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ + out32(GPIO0_OR, 0); /* pull prg low */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -160,61 +140,48 @@ int board_early_init_f (void) mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0 */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks + * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ - - /* - * New boards have a single 32MB flash connected to CS0 - * instead of two 16MB flashes on CS0+1. - */ - if (board_revision() >= 8) { - /* disable CS1 */ - mtebc(pb1ap, 0); - mtebc(pb1cr, 0); - - /* resize CS0 to 32MB */ - mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8); - mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8); - } +#if 1 /* test-only */ + mtebc (epcr, 0xa8400000); /* ebc always driven */ +#else + mtebc (epcr, 0x28400000); /* ebc in high-z */ +#endif return 0; } -int board_early_init_r(void) -{ - if (gd->board_type >= 8) - flash_banks = 1; - return 0; +/* ------------------------------------------------------------------------- */ + +int misc_init_f (void) +{ + return 0; /* dummy implementation */ } -#define FUJI_BASE 0xf0100200 -#define LCDBL_PWM 0xa0 -#define LCDBL_PWMMIN 0xa4 -#define LCDBL_PWMMAX 0xa8 -int misc_init_r(void) +int misc_init_r (void) { - u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); - u8 *duart0_mcr = (u8 *)(DUART0_BA + 4); - u8 *duart1_mcr = (u8 *)(DUART1_BA + 4); + volatile unsigned short *fpga_mode = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned short *fpga_ctrl2 = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); + volatile unsigned char *duart0_mcr = + (unsigned char *)((ulong)DUART0_BA + 4); + volatile unsigned char *duart1_mcr = + (unsigned char *)((ulong)DUART1_BA + 4); + volatile unsigned short *fuji_lcdbl_pwm = + (unsigned short *)((ulong)0xf0100200 + 0xa0); unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; unsigned long cntrl0Reg; - char *str; - uchar *logo_addr; - ulong logo_size; - ushort minb, maxb; - int result; /* * Setup GPIO pins (CS6+CS7 as GPIO) @@ -223,9 +190,9 @@ int misc_init_r(void) mtdcr(cntrl0, cntrl0Reg | 0x00300000); dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf("GUNZIP ERROR - must RESET board to recover\n"); - do_reset(NULL, 0, 0, NULL); + if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf ("GUNZIP ERROR - must RESET board to recover\n"); + do_reset (NULL, 0, 0, NULL); } status = fpga_boot(dst, len); @@ -233,34 +200,31 @@ int misc_init_r(void) printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: " - "INIT not low after asserting PROGRAM*)\n "); + printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: " - "INIT not high after deasserting PROGRAM*)\n "); + printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: - printf("(Timeout: " - "DONE not high after programming FPGA)\n "); + printf("(Timeout: DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; - for (i = 0; i < 4; i++) { + for (i=0; i<4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); - index += len + 3; + index += len+3; } - putc('\n'); + putc ('\n'); /* delayed reboot */ - for (i = 20; i > 0; i--) { + for (i=20; i>0; i--) { printf("Rebooting in %2d seconds \r",i); - for (index = 0; index < 1000; index++) + for (index=0;index<1000;index++) udelay(1000); } - putc('\n'); + putc ('\n'); do_reset(NULL, 0, 0, NULL); } @@ -271,12 +235,12 @@ int misc_init_r(void) /* display infos on fpgaimage */ index = 15; - for (i = 0; i < 4; i++) { + for (i=0; i<4; i++) { len = dst[index]; - printf("%s ", &(dst[index + 1])); - index += len + 3; + printf("%s ", &(dst[index+1])); + index += len+3; } - putc('\n'); + putc ('\n'); free(dst); @@ -291,122 +255,51 @@ int misc_init_r(void) /* * Write board revision in FPGA */ - out_be16(fpga_ctrl2, - (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f)); + *fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f); /* * Enable power on PS/2 interface (with reset) */ - out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET); + *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET; for (i=0;i<100;i++) udelay(1000); udelay(1000); - out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET); + *fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET; /* * Enable interrupts in exar duart mcr[3] */ - out_8(duart0_mcr, 0x08); - out_8(duart1_mcr, 0x08); + *duart0_mcr = 0x08; + *duart1_mcr = 0x08; /* * Init lcd interface and display logo */ - str = getenv("splashimage"); - if (str) { - logo_addr = (uchar *)simple_strtoul(str, NULL, 16); - logo_size = CFG_VIDEO_LOGO_MAX_SIZE; - } else { - logo_addr = logo_bmp; - logo_size = sizeof(logo_bmp); - } - - if (gd->board_type >= 6) { - result = lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, - regs_13505_640_480_16bpp, - sizeof(regs_13505_640_480_16bpp) / - sizeof(regs_13505_640_480_16bpp[0]), - logo_addr, logo_size); - if (result && str) { - /* retry with internal image */ - logo_addr = logo_bmp; - logo_size = sizeof(logo_bmp); - lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, - regs_13505_640_480_16bpp, - sizeof(regs_13505_640_480_16bpp) / - sizeof(regs_13505_640_480_16bpp[0]), - logo_addr, logo_size); - } - } else { - result = lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp) / - sizeof(regs_13806_640_480_16bpp[0]), - logo_addr, logo_size); - if (result && str) { - /* retry with internal image */ - logo_addr = logo_bmp; - logo_size = sizeof(logo_bmp); - lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp) / - sizeof(regs_13806_640_480_16bpp[0]), - logo_addr, logo_size); - } - } + lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + regs_13806_640_480_16bpp, + sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), + logo_bmp, sizeof(logo_bmp)); /* * Reset microcontroller and setup backlight PWM controller */ - out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014); + *fpga_mode |= 0x0014; for (i=0;i<10;i++) udelay(1000); - out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c); - - minb = 0; - maxb = 0xff; - str = getenv("lcdbl"); - if (str) { - minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff; - if (str && (*str=',')) { - str++; - maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff; - } else - minb = 0; - - out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb); - out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb); - - printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb); - } - out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff); - - /* - * fix environment for field updated units - */ - if (getenv("altbootcmd") == NULL) { - setenv("usb_load", CFG_USB_LOAD_COMMAND); - setenv("usbargs", CFG_USB_ARGS); - setenv("bootcmd", CONFIG_BOOTCOMMAND); - setenv("usb_self", CFG_USB_SELF_COMMAND); - setenv("bootlimit", CFG_BOOTLIMIT); - setenv("altbootcmd", CFG_ALT_BOOTCOMMAND); - saveenv(); - } + *fpga_mode |= 0x001c; + *fuji_lcdbl_pwm = 0x00ff; return (0); } + /* * Check Board Identity: */ + int checkboard (void) { - char str[64]; + unsigned char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); puts ("Board: "); @@ -418,76 +311,62 @@ int checkboard (void) } gd->board_type = board_revision(); - printf(", Rev. 1.%ld\n", gd->board_type); + printf(", Rev 1.%ld\n", gd->board_type); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); return 0; } -phys_size_t initdram (int board_type) +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) { unsigned long val; mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + #ifdef CONFIG_IDE_RESET + void ide_set_reset(int on) { - u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + volatile unsigned short *fpga_mode = + (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); /* * Assert or deassert CompactFlash Reset Pin */ - if (on) { - out_be16(fpga_mode, - in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET); - } else { - out_be16(fpga_mode, - in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET); + if (on) { /* assert RESET */ + *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + } else { /* release RESET */ + *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; } } + #endif /* CONFIG_IDE_RESET */ -void reset_phy(void) -{ - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -} - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) -int usb_board_init(void) -{ - return 0; -} - -int usb_board_stop(void) -{ - unsigned short tmp; - int i; - - /* - * reset PCI bus - * This is required to make some very old Linux OHCI driver - * work after U-Boot has used the OHCI controller. - */ - pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp); - pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000)); - - for (i = 0; i < 100; i++) - udelay(1000); - - pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp); - return 0; -} - -int usb_board_init_fail(void) -{ - usb_board_stop(); - return 0; -} -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ +/* ------------------------------------------------------------------------- */ diff --git a/board/esd/apc405/fpgadata.c b/board/esd/apc405/fpgadata.c index 0b4664e87..c31625a99 100644 --- a/board/esd/apc405/fpgadata.c +++ b/board/esd/apc405/fpgadata.c @@ -1,2004 +1,2280 @@ - 0x1f,0x8b,0x08,0x08,0x49,0xe1,0xdb,0x46,0x00,0x03,0x61,0x62,0x67,0x34,0x30,0x35, - 0x5f,0x31,0x5f,0x30,0x33,0x2e,0x62,0x69,0x74,0x00,0xed,0xfd,0x7d,0x7c,0x14,0xd7, - 0x75,0x3f,0x8e,0x9f,0xb9,0x33,0x12,0xa3,0xdd,0x95,0x76,0xf4,0xe4,0xac,0x6d,0x20, - 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0xe0,0x87,0x53,0xbe,0x00,0x1c,0xe4,0xf1,0x0f,0xa1,0x79,0x01,0x58,0xa0,0x0b,0x96, + 0x85,0x37,0xaf,0x33,0x07,0x78,0x1a,0x8d,0x70,0x8a,0xda,0x05,0x20,0x8a,0x82,0x38, + 0xc2,0xdf,0x79,0x01,0x48,0xa5,0x32,0x7e,0xa2,0x79,0x01,0x28,0xa3,0x3b,0xde,0xd2, + 0x9a,0xf7,0x39,0x07,0x08,0xc0,0xb2,0xa7,0xb5,0x49,0x5e,0xe7,0xde,0xef,0xac,0x00, + 0x28,0x70,0xfb,0x5a,0xd1,0xbc,0x00,0x8c,0x75,0xcb,0xc6,0x51,0xbb,0x00,0x5c,0xc5, + 0x0d,0x3a,0xc8,0x5f,0x78,0x01,0xb8,0x81,0xc9,0xdd,0x94,0x5d,0xb5,0x3a,0x17,0x80, + 0x76,0xed,0xcd,0x55,0xd6,0xb6,0x6a,0x17,0x80,0xb1,0xea,0xdb,0x50,0xf3,0x02,0xc0, + 0x47,0xed,0xa5,0xa9,0x73,0x01,0x78,0xb2,0xf6,0x26,0x55,0xb5,0x00,0xd0,0xde,0xb6, + 0x3a,0x17,0x00,0x3e,0xa5,0x5e,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, @@ -558,8 +231,5 @@ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0xe0,0x4f,0xc5,0xff,0x02,0x04,0xc4,0x15,0x0c,0x36,0xb4, - 0x04,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xea,0xfc,0x03,0x26, + 0x84,0x0a,0xd6,0x36,0x10,0x0e,0x00, diff --git a/board/esd/apc405/strataflash.c b/board/esd/apc405/strataflash.c new file mode 100644 index 000000000..ad7a71dc4 --- /dev/null +++ b/board/esd/apc405/strataflash.c @@ -0,0 +1,789 @@ +/* + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for ppcboot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + +#define FLASH_MAN_CFI 0x01000000 + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char * cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ + +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) +{ + return ((uchar *)(info->start[sect] + (offset * info->portwidth))); +} +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uchar offset) +{ + uchar *cp; + cp = flash_make_addr(info, 0, offset); + return (cp[info->portwidth - 1]); +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); + +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | + (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); + +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + int i; + unsigned long address; + + + /* The flash is positioned back to back, with the demultiplexing of the chip + * based on the A24 address line. + * + */ + + address = CFG_FLASH_BASE; + size = 0; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) + (void)flash_real_protect(&flash_info[0], i, 1); +#endif +#else + /* monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + - CFG_MONITOR_LEN, + - 1, &flash_info[1]); +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if( info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + + if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3 ), (info->chipwidth << 3 )); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + int k; + int size; + int erased; + volatile unsigned long *flash; + + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; kstart[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); +#else + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); +#endif + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for(i=0;iportwidth) && (cnt > 0) ; i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *)cp)); + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while(cnt >= info->portwidth) { + i = info->buffer_size > cnt? cnt: info->buffer_size; + if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -=i; + } +#else + /* handle the aligned part */ + while(cnt >= info->portwidth) { + cword.l = 0; + for(i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; iportwidth; ++i, ++cp) { + flash_add_byte(info, & cword, (*(uchar *)cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if(prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, + prot?"protect":"unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if(prot == 0) { + int i; + for(i = 0 ; isector_count; i++) { + if(info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + + return retcode; +} +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer(start) > info->erase_blk_tout) { + printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + int retcode; + retcode = flash_status_check(info, sector, tout, prompt); + if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt,info->start[sector]); + if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ + printf("Command Sequence Error.\n"); + } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ + printf("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { + printf("Locking Error\n"); + } + if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ + printf("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + printf("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return retcode; +} +/*----------------------------------------------------------------------- + */ +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) +{ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) +{ + int i; + uchar *cp = (uchar *)cmdbuf; + for(i=0; i< info->portwidth; i++) + *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} +/*----------------------------------------------------------------------- + */ +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +*/ +static int flash_detect_cfi(flash_info_t * info) +{ + + for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; + info->portwidth <<= 1) { + for(info->chipwidth =FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } + return 0; +} +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t * info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if(flash_detect_cfi(info)){ +#ifdef DEBUG_FLASH + printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif + size_ratio = info->portwidth / info->chipwidth; + num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); +#ifdef DEBUG_FLASH + printf("found %d erase regions\n", num_erase_regions); +#endif + sect_cnt = 0; + sector = base; + for(i = 0 ; i < num_erase_regions; i++) { + if(i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); + erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) +1; + for(j = 0; j< erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *)dest; + + + /* Check if Flash is (sufficiently) erased */ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if(!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if(flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector(flash_info_t *info, ulong addr) +{ + int sector; + for(sector = info->sector_count - 1; sector >= 0; sector--) { + if(addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *)dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if((retcode = flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar)cnt-1); + while(cnt-- > 0) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check(info, sector, info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/apc405/u-boot.lds b/board/esd/apc405/u-boot.lds index 21547ac27..f7a20d1da 100644 --- a/board/esd/apc405/u-boot.lds +++ b/board/esd/apc405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile index ba92b24c8..a60495a59 100644 --- a/board/esd/ar405/Makefile +++ b/board/esd/ar405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,32 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index 3abcfe690..dfead3363 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -190,6 +190,28 @@ int checkboard (void) return 0; } +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + #if 1 /* test-only: some internal test routines... */ /* diff --git a/board/esd/ar405/u-boot.lds b/board/esd/ar405/u-boot.lds index b072bbb3e..3b9aa7c5d 100644 --- a/board/esd/ar405/u-boot.lds +++ b/board/esd/ar405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -151,7 +152,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile index 98acb4b77..a60495a59 100644 --- a/board/esd/ash405/Makefile +++ b/board/esd/ash405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,34 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 25360a656..84fc3a01d 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -23,7 +23,6 @@ #include #include -#include #include #include @@ -34,7 +33,6 @@ #endif extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -extern void lxt971_no_sleep(void); /* fpga configuration data - gzip compressed and generated by bin2c */ const unsigned char fpgadata[] = @@ -166,11 +164,17 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + /* * Enable interrupts in exar duart mcr[3] */ @@ -207,24 +211,42 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } /* ------------------------------------------------------------------------- */ -void reset_phy(void) +int testdram (void) { -#ifdef CONFIG_LXT971_NO_SLEEP - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); } + +/* ------------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif diff --git a/board/esd/ash405/u-boot.lds b/board/esd/ash405/u-boot.lds index 644174a46..95854f293 100644 --- a/board/esd/ash405/u-boot.lds +++ b/board/esd/ash405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -136,7 +137,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/canbt/Makefile b/board/esd/canbt/Makefile index ba92b24c8..a60495a59 100644 --- a/board/esd/canbt/Makefile +++ b/board/esd/canbt/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,32 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 30fa605ab..055a39773 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -181,3 +181,22 @@ int checkboard (void) return 0; } + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + return (16 * 1024 * 1024); +} + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/esd/canbt/u-boot.lds b/board/esd/canbt/u-boot.lds index e66db5d23..ff15b3fef 100644 --- a/board/esd/canbt/u-boot.lds +++ b/board/esd/canbt/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -149,7 +150,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile index 1093c5275..a11ee82aa 100644 --- a/board/esd/cms700/Makefile +++ b/board/esd/cms700/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,40 +22,30 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a # Objects for Xilinx JTAG programming (CPLD) CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - $(CPLD) \ - ../common/esd405ep_nand.o \ - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index ba27c030b..cb0471073 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005-2007 + * (C) Copyright 2005 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -23,7 +23,6 @@ #include #include -#include #include #include @@ -69,9 +68,9 @@ int board_early_init_f (void) /* * Reset CPLD via GPIO12 (CS3) pin */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET); udelay(1000); /* wait 1ms */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET); udelay(1000); /* wait 1ms */ return 0; @@ -92,10 +91,16 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - /* + /* * Setup and enable EEPROM write protection */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); return (0); } @@ -141,13 +146,18 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } @@ -170,17 +180,17 @@ int eeprom_write_enable (unsigned dev_addr, int state) switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); break; } } @@ -225,6 +235,19 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, /* ------------------------------------------------------------------------- */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif + void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/cms700/u-boot.lds b/board/esd/cms700/u-boot.lds index 21547ac27..f7a20d1da 100644 --- a/board/esd/cms700/u-boot.lds +++ b/board/esd/cms700/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 7e6eea0f1..5cd342332 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -24,132 +24,162 @@ #include +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) +#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support! +#endif + #include #include #include -#if defined(CFG_NAND_LEGACY) #include -#endif #include -#include #include "auto_update.h" #ifdef CONFIG_AUTO_UPDATE -#if !defined(CONFIG_CMD_FAT) -#error "must define CONFIG_CMD_FAT" +#if !(CONFIG_COMMANDS & CFG_CMD_FAT) +#error "must define CFG_CMD_FAT" #endif extern au_image_t au_image[]; extern int N_AU_IMAGES; -/* where to load files into memory */ -#define LOAD_ADDR ((unsigned char *)0x100000) -#define MAX_LOADSZ 0x1c00000 +#define AU_DEBUG +#undef AU_DEBUG + +#undef debug +#ifdef AU_DEBUG +#define debug(fmt,args...) printf (fmt ,##args) +#else +#define debug(fmt,args...) +#endif /* AU_DEBUG */ + + +#define LOAD_ADDR ((unsigned char *)0x100000) /* where to load files into memory */ +#define MAX_LOADSZ 0x1e00000 /* externals */ extern int fat_register_device(block_dev_desc_t *, int); extern int file_fat_detectfs(void); extern long file_fat_read(const char *, void *, unsigned long); -long do_fat_read (const char *filename, void *buffer, - unsigned long maxsize, int dols); +long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, int dols); +#ifdef CONFIG_VFD +extern int trab_vfd (ulong); +extern int transfer_pic(unsigned char, unsigned char *, int, int); +#endif extern int flash_sect_erase(ulong, ulong); extern int flash_sect_protect (int, ulong, ulong); extern int flash_write (char *, ulong, ulong); +/* change char* to void* to shutup the compiler */ +extern block_dev_desc_t *get_dev (char*, int); -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) /* references to names in cmd_nand.c */ #define NANDRW_READ 0x01 #define NANDRW_WRITE 0x00 #define NANDRW_JFFS2 0x02 #define NANDRW_JFFS2_SKIP 0x04 extern struct nand_chip nand_dev_desc[]; -extern int nand_legacy_rw(struct nand_chip* nand, int cmd, - size_t start, size_t len, - size_t * retlen, u_char * buf); -extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, - size_t len, int clean); -#endif +extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, + size_t * retlen, u_char * buf); +extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) */ extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; + int au_check_cksum_valid(int i, long nbytes) { image_header_t *hdr; + unsigned long checksum; hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - if ((au_image[i].type == AU_FIRMWARE) && - (au_image[i].size != image_get_data_size (hdr))) { + if ((au_image[i].type == AU_FIRMWARE) && (au_image[i].size != ntohl(hdr->ih_size))) { printf ("Image %s has wrong size\n", au_image[i].name); return -1; } - if (nbytes != (image_get_image_size (hdr))) { + if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) { printf ("Image %s bad total SIZE\n", au_image[i].name); return -1; } - /* check the data CRC */ - if (!image_check_dcrc (hdr)) { + checksum = ntohl(hdr->ih_dcrc); + + if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) + != checksum) { printf ("Image %s bad data checksum\n", au_image[i].name); return -1; } return 0; } + int au_check_header_valid(int i, long nbytes) { image_header_t *hdr; unsigned long checksum; hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - /* check the easy ones first */ - if (nbytes < image_get_header_size ()) { +#undef CHECK_VALID_DEBUG +#ifdef CHECK_VALID_DEBUG + printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC); + printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_PPC); + printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes); + printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL); +#endif + if (nbytes < sizeof(*hdr)) + { printf ("Image %s bad header SIZE\n", au_image[i].name); return -1; } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) { + if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC) + { printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name); return -1; } - if (!image_check_hcrc (hdr)) { + /* check the hdr CRC */ + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) { printf ("Image %s bad header checksum\n", au_image[i].name); return -1; } + hdr->ih_hcrc = htonl(checksum); /* check the type - could do this all in one gigantic if() */ - if (((au_image[i].type & AU_TYPEMASK) == AU_FIRMWARE) && - !image_check_type (hdr, IH_TYPE_FIRMWARE)) { + if ((au_image[i].type == AU_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) { printf ("Image %s wrong type\n", au_image[i].name); return -1; } - if (((au_image[i].type & AU_TYPEMASK) == AU_SCRIPT) && - !image_check_type (hdr, IH_TYPE_SCRIPT)) { + if ((au_image[i].type == AU_SCRIPT) && (hdr->ih_type != IH_TYPE_SCRIPT)) { printf ("Image %s wrong type\n", au_image[i].name); return -1; } /* recycle checksum */ - checksum = image_get_data_size (hdr); + checksum = ntohl(hdr->ih_size); + +#if 0 /* test-only */ + /* for kernel and app the image header must also fit into flash */ + if (idx != IDX_DISK) + checksum += sizeof(*hdr); + /* check the size does not exceed space in flash. HUSH scripts */ + /* all have ausize[] set to 0 */ + if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { + printf ("Image %s is bigger than FLASH\n", au_image[i].name); + return -1; + } +#endif return 0; } + int au_do_update(int i, long sz) { image_header_t *hdr; @@ -158,28 +188,22 @@ int au_do_update(int i, long sz) int off, rc; uint nbytes; int k; -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) int total; #endif hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - switch (au_image[i].type & AU_TYPEMASK) { + switch (au_image[i].type) { case AU_SCRIPT: printf("Executing script %s\n", au_image[i].name); /* execute a script */ - if (image_check_type (hdr, IH_TYPE_SCRIPT)) { - addr = (char *)((char *)hdr + image_get_header_size ()); + if (hdr->ih_type == IH_TYPE_SCRIPT) { + addr = (char *)((char *)hdr + sizeof(*hdr)); /* stick a NULL at the end of the script, otherwise */ /* parse_string_outer() runs off the end. */ - addr[image_get_data_size (hdr)] = 0; + addr[ntohl(hdr->ih_size)] = 0; addr += 8; /* @@ -210,43 +234,38 @@ int au_do_update(int i, long sz) */ if (au_image[i].type == AU_FIRMWARE) { char *orig = (char*)start; - char *new = (char *)((char *)hdr + - image_get_header_size ()); - nbytes = image_get_data_size (hdr); + char *new = (char *)((char *)hdr + sizeof(*hdr)); + nbytes = ntohl(hdr->ih_size); - while (--nbytes) { + while(--nbytes) { if (*orig++ != *new++) { break; } } if (!nbytes) { - printf ("Skipping firmware update - " - "images are identical\n"); + printf("Skipping firmware update - images are identical\n"); break; } } /* unprotect the address range */ - if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) || - (au_image[i].type == AU_FIRMWARE)) { - flash_sect_protect (0, start, end); + /* this assumes that ONLY the firmware is protected! */ + if (au_image[i].type == AU_FIRMWARE) { + flash_sect_protect(0, start, end); } /* * erase the address range. */ if (au_image[i].type != AU_NAND) { - printf ("Updating NOR FLASH with image %s\n", - au_image[i].name); + printf("Updating NOR FLASH with image %s\n", au_image[i].name); debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase (start, end); + flash_sect_erase(start, end); } else { -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) - printf ("Updating NAND FLASH with image %s\n", - au_image[i].name); +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) + printf("Updating NAND FLASH with image %s\n", au_image[i].name); debug ("nand_legacy_erase(%lx, %lx);\n", start, end); - rc = nand_legacy_erase (nand_dev_desc, start, - end - start + 1, 0); + rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0); debug ("nand_legacy_erase returned %x\n", rc); #endif } @@ -256,38 +275,30 @@ int au_do_update(int i, long sz) /* strip the header - except for the kernel and ramdisk */ if (au_image[i].type != AU_FIRMWARE) { addr = (char *)hdr; - off = image_get_header_size (); - nbytes = image_get_image_size (hdr); + off = sizeof(*hdr); + nbytes = sizeof(*hdr) + ntohl(hdr->ih_size); } else { - addr = (char *)((char *)hdr + image_get_header_size ()); + addr = (char *)((char *)hdr + sizeof(*hdr)); off = 0; - nbytes = image_get_data_size (hdr); + nbytes = ntohl(hdr->ih_size); } /* * copy the data from RAM to FLASH */ if (au_image[i].type != AU_NAND) { - debug ("flash_write(%p, %lx, %x)\n", - addr, start, nbytes); - rc = flash_write ((char *)addr, start, - (nbytes + 1) & ~1); + debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); + rc = flash_write((char *)addr, start, nbytes); } else { -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) - debug ("nand_legacy_rw(%p, %lx, %x)\n", - addr, start, nbytes); - rc = nand_legacy_rw (nand_dev_desc, - NANDRW_WRITE | NANDRW_JFFS2, - start, nbytes, (size_t *)&total, - (uchar *)addr); - debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", - rc, total, nbytes); -#else - rc = -1; +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) + debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes); + rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, + start, nbytes, (size_t *)&total, (uchar *)addr); + debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); #endif } if (rc != 0) { - printf ("Flashing failed due to error %d\n", rc); + printf("Flashing failed due to error %d\n", rc); return -1; } @@ -295,30 +306,23 @@ int au_do_update(int i, long sz) * check the dcrc of the copy */ if (au_image[i].type != AU_NAND) { - rc = crc32 (0, (uchar *)(start + off), - image_get_data_size (hdr)); + rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)); } else { -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) - rc = nand_legacy_rw (nand_dev_desc, - NANDRW_READ | NANDRW_JFFS2 | - NANDRW_JFFS2_SKIP, - start, nbytes, (size_t *)&total, - (uchar *)addr); - rc = crc32 (0, (uchar *)(addr + off), - image_get_data_size (hdr)); +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) + rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, + start, nbytes, (size_t *)&total, (uchar *)addr); + rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size)); #endif } - if (rc != image_get_dcrc (hdr)) { - printf ("Image %s Bad Data Checksum After COPY\n", - au_image[i].name); + if (rc != ntohl(hdr->ih_dcrc)) { + printf ("Image %s Bad Data Checksum After COPY\n", au_image[i].name); return -1; } /* protect the address range */ /* this assumes that ONLY the firmware is protected! */ - if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) || - (au_image[i].type == AU_FIRMWARE)) { - flash_sect_protect (1, start, end); + if (au_image[i].type == AU_FIRMWARE) { + flash_sect_protect(1, start, end); } break; @@ -330,6 +334,7 @@ int au_do_update(int i, long sz) return 0; } + static void process_macros (const char *input, char *output) { char c, prev; @@ -343,17 +348,16 @@ static void process_macros (const char *input, char *output) #ifdef DEBUG_PARSER char *output_start = output; - printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", - strlen(input), input); + printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen(input), input); #endif - prev = '\0'; /* previous character */ + prev = '\0'; /* previous character */ while (inputcnt && outputcnt) { c = *input++; inputcnt--; - if (state != 3) { + if (state!=3) { /* remove one level of escape characters */ if ((c == '\\') && (prev != '\\')) { if (inputcnt-- == 0) @@ -364,7 +368,7 @@ static void process_macros (const char *input, char *output) } switch (state) { - case 0: /* Waiting for (unescaped) $ */ + case 0: /* Waiting for (unescaped) $ */ if ((c == '\'') && (prev != '\\')) { state = 3; break; @@ -376,7 +380,7 @@ static void process_macros (const char *input, char *output) outputcnt--; } break; - case 1: /* Waiting for ( */ + case 1: /* Waiting for ( */ if (c == '(' || c == '{') { state++; varname_start = input; @@ -395,8 +399,7 @@ static void process_macros (const char *input, char *output) if (c == ')' || c == '}') { int i; char envname[CFG_CBSIZE], *envval; - /* Varname # of chars */ - int envcnt = input - varname_start - 1; + int envcnt = input-varname_start-1; /* Varname # of chars */ /* Get the varname */ for (i = 0; i < envcnt; i++) { @@ -434,10 +437,11 @@ static void process_macros (const char *input, char *output) #ifdef DEBUG_PARSER printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", - strlen (output_start), output_start); + strlen(output_start), output_start); #endif } + /* * this is called from board_init() after the hardware has been set up * and is usable. That seems like a good time to do this. @@ -445,84 +449,84 @@ static void process_macros (const char *input, char *output) */ int do_auto_update(void) { - block_dev_desc_t *stor_dev = NULL; + block_dev_desc_t *stor_dev; long sz; int i, res, cnt, old_ctrlc, got_ctrlc; char buffer[32]; char str[80]; - int n; - if (ide_dev_desc[0].type != DEV_TYPE_UNKNOWN) { - stor_dev = get_dev ("ide", 0); - if (stor_dev == NULL) { - debug ("ide: unknown device\n"); - return -1; - } + /* + * Check whether a CompactFlash is inserted + */ + if (ide_dev_desc[0].type == DEV_TYPE_UNKNOWN) { + return -1; /* no disk detected! */ } - if (fat_register_device (stor_dev, 1) != 0) { - debug ("Unable to register ide disk 0:1\n"); + /* check whether it has a partition table */ + stor_dev = get_dev("ide", 0); + if (stor_dev == NULL) { + debug ("Uknown device type\n"); + return -1; + } + if (fat_register_device(stor_dev, 1) != 0) { + debug ("Unable to register ide disk 0:1 for fatls\n"); return -1; } /* * Check if magic file is present */ - if ((n = do_fat_read (AU_MAGIC_FILE, buffer, - sizeof(buffer), LS_NO)) <= 0) { - debug ("No auto_update magic file (n=%d)\n", n); + if (do_fat_read(AU_MAGIC_FILE, buffer, sizeof(buffer), LS_NO) <= 0) { return -1; } #ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show (1); + board_auto_update_show(1); #endif puts("\nAutoUpdate Disk detected! Trying to update system...\n"); /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc (0); + old_ctrlc = disable_ctrlc(0); /* just loop thru all the possible files */ for (i = 0; i < N_AU_IMAGES; i++) { /* * Try to expand the environment var in the fname */ - process_macros (au_image[i].name, str); - strcpy (au_image[i].name, str); + process_macros(au_image[i].name, str); + strcpy(au_image[i].name, str); printf("Reading %s ...", au_image[i].name); /* just read the header */ - sz = do_fat_read (au_image[i].name, LOAD_ADDR, - image_get_header_size (), LS_NO); + sz = do_fat_read(au_image[i].name, LOAD_ADDR, sizeof(image_header_t), LS_NO); debug ("read %s sz %ld hdr %d\n", - au_image[i].name, sz, image_get_header_size ()); - if (sz <= 0 || sz < image_get_header_size ()) { + au_image[i].name, sz, sizeof(image_header_t)); + if (sz <= 0 || sz < sizeof(image_header_t)) { puts(" not found\n"); continue; } - if (au_check_header_valid (i, sz) < 0) { + if (au_check_header_valid(i, sz) < 0) { puts(" header not valid\n"); continue; } - sz = do_fat_read (au_image[i].name, LOAD_ADDR, - MAX_LOADSZ, LS_NO); + sz = do_fat_read(au_image[i].name, LOAD_ADDR, MAX_LOADSZ, LS_NO); debug ("read %s sz %ld hdr %d\n", - au_image[i].name, sz, image_get_header_size ()); - if (sz <= 0 || sz <= image_get_header_size ()) { + au_image[i].name, sz, sizeof(image_header_t)); + if (sz <= 0 || sz <= sizeof(image_header_t)) { puts(" not found\n"); continue; } - if (au_check_cksum_valid (i, sz) < 0) { + if (au_check_cksum_valid(i, sz) < 0) { puts(" checksum not valid\n"); continue; } puts(" done\n"); do { - res = au_do_update (i, sz); + res = au_do_update(i, sz); /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc ()) { - clear_ctrlc (); + if (ctrlc() || had_ctrlc()) { + clear_ctrlc(); if (res < 0) got_ctrlc = 1; break; @@ -532,16 +536,17 @@ int do_auto_update(void) } /* restore the old state */ - disable_ctrlc (old_ctrlc); + disable_ctrlc(old_ctrlc); puts("AutoUpdate finished\n\n"); #ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show (0); + board_auto_update_show(0); #endif return 0; } + int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { do_auto_update(); diff --git a/board/esd/common/auto_update.h b/board/esd/common/auto_update.h index 3ed0e1637..e2af3c7b1 100644 --- a/board/esd/common/auto_update.h +++ b/board/esd/common/auto_update.h @@ -29,21 +29,16 @@ #define AU_MAGIC_FILE "__auto_update" -#define AU_TYPEMASK 0x000000ff -#define AU_FLAGMASK 0xffff0000 - -#define AU_PROTECT 0x80000000 - -#define AU_SCRIPT 0x01 -#define AU_FIRMWARE (0x02 | AU_PROTECT) -#define AU_NOR 0x03 -#define AU_NAND 0x04 +#define AU_SCRIPT 1 +#define AU_FIRMWARE 2 +#define AU_NOR 3 +#define AU_NAND 4 struct au_image_s { char name[80]; ulong start; ulong size; - ulong type; + int type; }; typedef struct au_image_s au_image_t; diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index d88b3876d..bf796ff9d 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -24,7 +24,7 @@ #include #include -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) extern int do_bootm (cmd_tbl_t *, int, int, char *[]); extern int do_autoscript (cmd_tbl_t *, int, int, char *[]); diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c index bda361ead..dca10be1b 100644 --- a/board/esd/common/flash.c +++ b/board/esd/common/flash.c @@ -22,9 +22,7 @@ */ #include -#ifdef __PPC__ #include -#endif #include flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c index 9e2be7eaf..ad5640269 100644 --- a/board/esd/common/fpga.c +++ b/board/esd/common/fpga.c @@ -37,22 +37,22 @@ #define MAX_ONES 226 #ifdef CFG_FPGA_PRG -# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output) */ -# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */ -# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */ -# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */ -# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */ +# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/ +# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */ +# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */ +# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */ +# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */ #else -# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ -# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ -# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ -# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ -# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ +# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ +# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ +# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ +# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ +# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ #endif -#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ -#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ -#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ +#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ +#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ +#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ #ifndef SET_FPGA # define SET_FPGA(data) out32(GPIO0_OR, data) @@ -76,13 +76,13 @@ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set data to 1 */ \ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ #define FPGA_WRITE_0 { \ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_HIGH); /* set clock to 0 */ \ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_LOW | FPGA_DATA_LOW); /* set data to 0 */ \ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_LOW); /* set clock to 1 */ \ - SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ #ifndef FPGA_DONE_STATE # define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE) @@ -92,182 +92,191 @@ #endif -static int fpga_boot (const unsigned char *fpgadata, int size) +static int fpga_boot(unsigned char *fpgadata, int size) { - int i, index, len; - int count; - unsigned char b; - + int i,index,len; + int count; #ifdef CFG_FPGA_SPARTAN2 - int j; + int j; #else - int bit; + unsigned char b; + int bit; #endif - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - DBG ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } + /* display infos on fpgaimage */ + index = 15; + for (i=0; i<4; i++) + { + len = fpgadata[index]; + DBG("FPGA: %s\n", &(fpgadata[index+1])); + index += len+3; + } #ifdef CFG_FPGA_SPARTAN2 - /* search for preamble 0xFFFFFFFF */ - while (1) { - if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) - && (fpgadata[index + 2] == 0xff) - && (fpgadata[index + 3] == 0xff)) - break; /* preamble found */ - else - index++; - } + /* search for preamble 0xFFFFFFFF */ + while (1) + { + if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) && + (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff)) + break; /* preamble found */ + else + index++; + } #else - /* search for preamble 0xFF2X */ - for (index = 0; index < size - 1; index++) { - if ((fpgadata[index] == 0xff) - && ((fpgadata[index + 1] & 0xf0) == 0x30)) - break; - } - index += 2; + /* search for preamble 0xFF2X */ + for (index = 0; index < size-1 ; index++) + { + if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30)) + break; + } + index += 2; #endif - DBG ("FPGA: configdata starts at position 0x%x\n", index); - DBG ("FPGA: length of fpga-data %d\n", size - index); + DBG("FPGA: configdata starts at position 0x%x\n",index); + DBG("FPGA: length of fpga-data %d\n", size-index); - /* - * Setup port pins for fpga programming - */ + /* + * Setup port pins for fpga programming + */ #ifndef CONFIG_M5249 - out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ #endif - SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */ - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - /* - * Init fpga by asserting and deasserting PROGRAM* - */ - SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */ + /* + * Init fpga by asserting and deasserting PROGRAM* + */ + SET_FPGA(FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog active */ - /* Wait for FPGA init line low */ - count = 0; - while (FPGA_INIT_STATE) { - udelay (1000); /* wait 1ms */ - /* Check for timeout - 100us max, so use 3ms */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_LOW; - } + /* Wait for FPGA init line low */ + count = 0; + while (FPGA_INIT_STATE) + { + udelay(1000); /* wait 1ms */ + /* Check for timeout - 100us max, so use 3ms */ + if (count++ > 3) + { + DBG("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_INIT_LOW; } + } - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - /* deassert PROGRAM* */ - SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */ + /* deassert PROGRAM* */ + SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set prog inactive */ - /* Wait for FPGA end of init period . */ - count = 0; - while (!(FPGA_INIT_STATE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_INIT_HIGH; - } + /* Wait for FPGA end of init period . */ + count = 0; + while (!(FPGA_INIT_STATE)) + { + udelay(1000); /* wait 1ms */ + /* Check for timeout */ + if (count++ > 3) + { + DBG("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_INIT_HIGH; } + } - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - DBG ("write configuration data into fpga\n"); - /* write configuration-data into fpga... */ + DBG("write configuration data into fpga\n"); + /* write configuration-data into fpga... */ #ifdef CFG_FPGA_SPARTAN2 - /* - * Load uncompressed image into fpga - */ - for (i = index; i < size; i++) { - b = fpgadata[i]; - for (j = 0; j < 8; j++) { - if ((b & 0x80) == 0x80) { - FPGA_WRITE_1; - } else { - FPGA_WRITE_0; - } - b <<= 1; - } + /* + * Load uncompressed image into fpga + */ + for (i=index; i= 1) && (b <= MAX_ONES)) { - for (bit = 0; bit < b; bit++) { - FPGA_WRITE_1; - } - FPGA_WRITE_0; - } else if (b == (MAX_ONES + 1)) { - for (bit = 1; bit < b; bit++) { - FPGA_WRITE_1; - } - } else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { - for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { - FPGA_WRITE_0; - } - FPGA_WRITE_1; - } else if (b == 255) { - FPGA_WRITE_1; - } + for (i=index; i= 1) && (b <= MAX_ONES)) + { + for(bit=0; bit= (MAX_ONES+2)) && (b <= 254)) + { + for(bit=0; bit<(b-(MAX_ONES+2)); bit++) + { + FPGA_WRITE_0; + } + FPGA_WRITE_1; + } + else if (b == 255) + { + FPGA_WRITE_1; + } + } #endif - DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE"); - DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT"); + DBG("%s, ",(FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE" ); + DBG("%s\n",(FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT" ); - /* - * Check if fpga's DONE signal - correctly booted ? - */ + /* + * Check if fpga's DONE signal - correctly booted ? + */ - /* Wait for FPGA end of programming period . */ - count = 0; - while (!(FPGA_DONE_STATE)) { - udelay (1000); /* wait 1ms */ - /* Check for timeout */ - if (count++ > 3) { - DBG ("FPGA: Booting failed!\n"); - return ERROR_FPGA_PRG_DONE; - } + /* Wait for FPGA end of programming period . */ + count = 0; + while (!(FPGA_DONE_STATE)) + { + udelay(1000); /* wait 1ms */ + /* Check for timeout */ + if (count++ > 3) + { + DBG("FPGA: Booting failed!\n"); + return ERROR_FPGA_PRG_DONE; } + } - DBG ("FPGA: Booting successful!\n"); - return 0; + DBG("FPGA: Booting successful!\n"); + return 0; } diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index c23dc81a2..196171ce5 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -24,7 +24,6 @@ * MA 02111-1307 USA */ -#include "asm/io.h" #include "lcd.h" @@ -37,64 +36,46 @@ int lcd_depth; unsigned char *glob_lcd_reg; unsigned char *glob_lcd_mem; -#if defined(CFG_LCD_ENDIAN) +#ifdef CFG_LCD_ENDIAN void lcd_setup(int lcd, int config) { if (lcd == 0) { /* * Set endianess and reset lcd controller 0 (small) */ - - /* set reset to low */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */ udelay(10); /* wait 10us */ if (config == 1) { - /* big-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ } else { - /* little-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ } udelay(10); /* wait 10us */ - /* set reset to high */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */ } else { /* * Set endianess and reset lcd controller 1 (big) */ - - /* set reset to low */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */ udelay(10); /* wait 10us */ if (config == 1) { - /* big-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ } else { - /* little-endian */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ } udelay(10); /* wait 10us */ - /* set reset to high */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */ } /* * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */ } -#endif /* CFG_LCD_ENDIAN */ +#endif /* #ifdef CFG_LCD_ENDIAN */ -int lcd_bmp(uchar *logo_bmp) +void lcd_bmp(uchar *logo_bmp) { int i; uchar *ptr; @@ -113,23 +94,21 @@ int lcd_bmp(uchar *logo_bmp) * Check for bmp mark 'BM' */ if (*(ushort *)logo_bmp != 0x424d) { + /* * Decompress bmp image */ len = CFG_VIDEO_LOGO_MAX_SIZE; dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); if (dst == NULL) { - printf("Error: malloc for gunzip failed!\n"); - return 1; + printf("Error: malloc in gunzip failed!\n"); + return; } - if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, - (uchar *)logo_bmp, &len) != 0) { - free(dst); - return 1; + if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) { + return; } if (len == CFG_VIDEO_LOGO_MAX_SIZE) { - printf("Image could be truncated" - " (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); + printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); } /* @@ -138,7 +117,7 @@ int lcd_bmp(uchar *logo_bmp) if (*(ushort *)dst != 0x424d) { printf("LCD: Unknown image format!\n"); free(dst); - return 1; + return; } } else { /* @@ -173,9 +152,10 @@ int lcd_bmp(uchar *logo_bmp) break; default: printf("LCD: Unknown bpp (%d) im image!\n", bpp); - if ((dst != NULL) && (dst != (uchar *)logo_bmp)) + if ((dst != NULL) && (dst != (uchar *)logo_bmp)) { free(dst); - return 1; + } + return; } printf(" (%d*%d, %dbpp)\n", width, height, bpp); @@ -184,7 +164,7 @@ int lcd_bmp(uchar *logo_bmp) */ if ((colors <= 256) && (lcd_depth <= 8)) { ptr = (unsigned char *)(dst + 14 + 40); - for (i = 0; i < colors; i++) { + for (i=0; i> 3; g = *bmp++ >> 2; r = *bmp++ >> 3; - val = ((r & 0x1f) << 11) | - ((g & 0x3f) << 5) | - (b & 0x1f); + val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); *ptr2++ = val; } } else if (bpp == 8) { - for (x = 0; x < line_size; x++) { + for (x=0; x> 3; g = *ptr++ >> 2; r = *ptr++ >> 3; - val = ((r & 0x1f) << 11) | - ((g & 0x3f) << 5) | - (b & 0x1f); + val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); *ptr2++ = val; } } } else { - for (x = 0; x < line_size; x++) + for (x=0; xusage); return 1; @@ -352,22 +314,19 @@ int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr = simple_strtoul(argv[1], NULL, 16); -#ifdef CONFIG_VIDEO_SM501 str = getenv("bd_type"); if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) { /* * SM501 available, use standard bmp command */ - return video_display_bitmap(addr, 0, 0); + return (video_display_bitmap(addr, 0, 0)); } else { /* * No SM501 available, use esd epson bmp command */ - return lcd_bmp((uchar *)addr); + lcd_bmp((uchar *)addr); + return 0; } -#else - return lcd_bmp((uchar *)addr); -#endif } U_BOOT_CMD( @@ -375,3 +334,4 @@ U_BOOT_CMD( "esdbmp - display BMP image\n", " - display image\n" ); +#endif diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile index 9a5607f69..88b0ae343 100644 --- a/board/esd/cpci2dp/Makefile +++ b/board/esd/cpci2dp/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,32 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 54de0b806..36bf329f8 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -117,7 +117,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; diff --git a/board/esd/cpci2dp/u-boot.lds b/board/esd/cpci2dp/u-boot.lds index 21547ac27..f7a20d1da 100644 --- a/board/esd/cpci2dp/u-boot.lds +++ b/board/esd/cpci2dp/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile index 3867bd809..9340a32a5 100644 --- a/board/esd/cpci405/Makefile +++ b/board/esd/cpci405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,32 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index b856705ff..f80361081 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -23,15 +23,13 @@ #include #include -#include #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ #if 0 #define FPGA_DEBUG #endif @@ -54,6 +52,8 @@ const unsigned char fpgadata[] = * include common fpga code (for esd boards) */ #include "../common/fpga.c" + + #include "../common/auto_update.h" #ifdef CONFIG_CPCI405AB @@ -86,11 +86,13 @@ au_image_t au_image[] = { int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); + /* Prototypes */ int cpci405_version(void); int gunzip(void *, int, unsigned char *, unsigned long *); void lxt971_no_sleep(void); + int board_early_init_f (void) { #ifndef CONFIG_CPCI405_VER2 @@ -109,10 +111,10 @@ int board_early_init_f (void) /* * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ - out32(GPIO0_OR, 0); /* pull prg low */ + out32(GPIO0_OR, 0); /* pull prg low */ /* * Boot onboard FPGA @@ -174,48 +176,47 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ -#ifdef CONFIG_CPCI405_6U + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ if (cpci405_version() == 3) { - mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ + mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ } else { - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ } -#else - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ -#endif - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; } + /* ------------------------------------------------------------------------- */ int ctermm2(void) { #ifdef CONFIG_CPCI405_VER2 - return 0; /* no, board is cpci405 */ + return 0; /* no, board is cpci405 */ #else if ((*(unsigned char *)0xf0000400 == 0x00) && (*(unsigned char *)0xf0000401 == 0x01)) - return 0; /* no, board is cpci405 */ + return 0; /* no, board is cpci405 */ else - return -1; /* yes, board is cterm-m2 */ + return -1; /* yes, board is cterm-m2 */ #endif } + int cpci405_host(void) { if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - return -1; /* yes, board is cpci405 host */ + return -1; /* yes, board is cpci405 host */ else - return 0; /* no, board is cpci405 adapter */ + return 0; /* no, board is cpci405 adapter */ } + int cpci405_version(void) { unsigned long cntrl0Reg; @@ -226,10 +227,10 @@ int cpci405_version(void) */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); + udelay(1000); /* wait some time before reading input */ + value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ /* * Restore GPIO settings @@ -244,7 +245,7 @@ int cpci405_version(void) /* CS2==0 && CS3==1 -> version 2 */ return 2; case 0x00100000: - /* CS2==1 && CS3==0 -> version 3 or 6U board */ + /* CS2==1 && CS3==0 -> version 3 */ return 3; case 0x00000000: /* CS2==0 && CS3==0 -> version 4 */ @@ -255,11 +256,13 @@ int cpci405_version(void) } } + int misc_init_f (void) { return 0; /* dummy implementation */ } + int misc_init_r (void) { unsigned long cntrl0Reg; @@ -280,6 +283,7 @@ int misc_init_r (void) * On CPCI-405 version 2 the environment is saved in eeprom! * FPGA can be gzip compressed (malloc) and booted this late. */ + if (cpci405_version() >= 2) { /* * Setup GPIO pins (CS6+CS7 as GPIO) @@ -350,7 +354,6 @@ int misc_init_r (void) SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ -#ifdef CONFIG_CPCI405_6U if (cpci405_version() == 3) { volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR; @@ -372,7 +375,6 @@ int misc_init_r (void) udelay(100); *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET); } -#endif } else { puts("\n*** U-Boot Version does not match Board Version!\n"); @@ -423,6 +425,7 @@ int misc_init_r (void) return (0); } + /* * Check Board Identity: */ @@ -478,7 +481,7 @@ int checkboard (void) } #ifndef CONFIG_CPCI405_VER2 - puts ("\nFPGA: "); + puts ("\nFPGA: "); /* display infos on fpgaimage */ index = 15; @@ -490,30 +493,40 @@ int checkboard (void) #endif putc ('\n'); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + return 0; } /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP +/* ------------------------------------------------------------------------- */ - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); } /* ------------------------------------------------------------------------- */ @@ -538,47 +551,14 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_CPCI405_VER2 */ -#if defined(CONFIG_PCI) -void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) -{ - unsigned char int_line = 0xff; - - /* - * Write pci interrupt line register (cpci405 specific) - */ - switch (PCI_DEV(dev) & 0x03) { - case 0: - int_line = 27 + 2; - break; - case 1: - int_line = 27 + 3; - break; - case 2: - int_line = 27 + 0; - break; - case 3: - int_line = 27 + 1; - break; - } - - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); -} - -int pci_pre_init(struct pci_controller *hose) -{ - hose->fixup_irq = cpci405_pci_fixup_irq; - return 1; -} -#endif /* defined(CONFIG_PCI) */ - #ifdef CONFIG_CPCI405AB -#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ +#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ |= CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ +#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ &= ~CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \ +#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \ & CFG_FPGA_MODE_1WIRE) /* @@ -601,6 +581,7 @@ int OWTouchReset(void) return result; } + /* * Send 1 a 1-wire write bit. * Provide 10us recovery time. @@ -626,6 +607,7 @@ void OWWriteBit(int bit) } } + /* * Read a bit from the 1-wire bus and return it. * Provide 10us recovery time. @@ -645,6 +627,7 @@ int OWReadBit(void) return result; } + void OWWriteByte(int data) { int loop; @@ -655,6 +638,7 @@ void OWWriteByte(int data) } } + int OWReadByte(void) { int loop, result = 0; @@ -669,6 +653,7 @@ int OWReadByte(void) return result; } + int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { volatile unsigned short val; @@ -709,6 +694,7 @@ U_BOOT_CMD( NULL ); + #define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ #define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds index 21547ac27..f7a20d1da 100644 --- a/board/esd/cpci405/u-boot.lds +++ b/board/esd/cpci405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/cpci440/Makefile b/board/esd/cpci440/Makefile new file mode 100644 index 000000000..84d44fbf4 --- /dev/null +++ b/board/esd/cpci440/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o strataflash.o ../common/misc.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/esd/cpci440/config.mk b/board/esd/cpci440/config.mk new file mode 100644 index 000000000..8e5f63fe4 --- /dev/null +++ b/board/esd/cpci440/config.mk @@ -0,0 +1,45 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0xFFFE0000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFFC0000 +#TEXT_BASE = 0x01fc0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/esd/cpci440/cpci440.c b/board/esd/cpci440/cpci440.c new file mode 100644 index 000000000..43d8a3b3b --- /dev/null +++ b/board/esd/cpci440/cpci440.c @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2002 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include + + +extern void lxt971_no_sleep(void); + + +long int fixed_sdram( void ); + +int board_early_init_f (void) +{ + uint reg; + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + mtdcr( ebccfga, xbcfg ); + reg = mfdcr( ebccfgd ); + mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */ + + mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */ + mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */ + /* test-only: other regs still missing... */ + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr( uic0sr, 0xffffffff ); /* clear all */ + mtdcr( uic0er, 0x00000000 ); /* disable all */ + mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */ + mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */ + mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */ + mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */ + mtdcr( uic0sr, 0xffffffff ); /* clear all */ + + mtdcr( uic1sr, 0xffffffff ); /* clear all */ + mtdcr( uic1er, 0x00000000 ); /* disable all */ + mtdcr( uic1cr, 0x00000000 ); /* all non-critical */ + mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */ + mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */ + mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */ + mtdcr( uic1sr, 0xffffffff ); /* clear all */ + + return 0; +} + + +int checkboard (void) +{ + sys_info_t sysinfo; + get_sys_info(&sysinfo); + + printf("Board: esd CPCI-440\n"); + printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000); + printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000); + printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000); + printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000); + printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + + return (0); +} + + +long int initdram (int board_type) +{ + long dram_size = 0; + + dram_size = fixed_sdram(); + return dram_size; +} + + +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + * + * Assumes: 64 MB, non-ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +long int fixed_sdram( void ) +{ + uint reg; + +#if 1 /* test-only */ + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */ + mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */ + mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */ + mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */ + mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/ + mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + /* RA=10 RD=3 */ + mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */ + udelay( 400 ); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */ + for(;;) + { + mfsdram( mem_mcsts, reg ); + if( reg & 0x80000000 ) + break; + } + + return( 64 * 1024 * 1024 ); /* 64 MB */ +#else + return( 32 * 1024 * 1024 ); /* 64 MB */ +#endif +} diff --git a/board/esd/cpci440/init.S b/board/esd/cpci440/init.S new file mode 100644 index 000000000..82f37fd99 --- /dev/null +++ b/board/esd/cpci440/init.S @@ -0,0 +1,94 @@ +/* +* Copyright (C) 2002 Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X ) + tlbtab_end diff --git a/board/esd/cpci440/strataflash.c b/board/esd/cpci440/strataflash.c new file mode 100644 index 000000000..2f055c20d --- /dev/null +++ b/board/esd/cpci440/strataflash.c @@ -0,0 +1,755 @@ +/* + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + + +#define FLASH_MAN_CFI 0x01000000 + + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char * cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +/*----------------------------------------------------------------------- + * Functions + */ + + +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) +{ + return ((uchar *)(info->start[sect] + (offset * info->portwidth))); +} +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uchar offset) +{ + uchar *cp; + cp = flash_make_addr(info, 0, offset); + return (cp[info->portwidth - 1]); +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); + +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | + (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); + +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + int i; + unsigned long address; + + + /* The flash is positioned back to back, with the demultiplexing of the chip + * based on the A24 address line. + * + */ + + address = CFG_FLASH_BASE; + size = 0; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) + (void)flash_real_protect(&flash_info[0], i, 1); +#endif +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if( info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + + if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3 ), (info->chipwidth << 3 )); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n"); + printf (" %08lX%5s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for(i=0;iportwidth) && (cnt > 0) ; i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *)cp)); + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while(cnt >= info->portwidth) { + i = info->buffer_size > cnt? cnt: info->buffer_size; + if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -=i; + } +#else + /* handle the aligned part */ + while(cnt >= info->portwidth) { + cword.l = 0; + for(i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; iportwidth; ++i, ++cp) { + flash_add_byte(info, & cword, (*(uchar *)cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if(prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, + prot?"protect":"unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if(prot == 0) { + int i; + for(i = 0 ; isector_count; i++) { + if(info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + + return retcode; +} +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer(start) > info->erase_blk_tout) { + printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + int retcode; + retcode = flash_status_check(info, sector, tout, prompt); + if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt,info->start[sector]); + if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ + printf("Command Sequence Error.\n"); + } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ + printf("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { + printf("Locking Error\n"); + } + if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ + printf("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + printf("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return retcode; +} +/*----------------------------------------------------------------------- + */ +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) +{ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) +{ + int i; + uchar *cp = (uchar *)cmdbuf; + for(i=0; i< info->portwidth; i++) + *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} +/*----------------------------------------------------------------------- + */ +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * + */ +static int flash_detect_cfi(flash_info_t * info) +{ + + for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; + info->portwidth <<= 1) { + for(info->chipwidth =FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } + return 0; +} +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t * info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + if(flash_detect_cfi(info)){ +#ifdef DEBUG_FLASH + printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif + size_ratio = info->portwidth / info->chipwidth; + num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); +#ifdef DEBUG_FLASH + printf("found %d erase regions\n", num_erase_regions); +#endif + sect_cnt = 0; + sector = base; + for(i = 0 ; i < num_erase_regions; i++) { + if(i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); + erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) +1; + for(j = 0; j< erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *)dest; + + + /* Check if Flash is (sufficiently) erased */ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if(!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if(flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector(flash_info_t *info, ulong addr) +{ + int sector; + for(sector = info->sector_count - 1; sector >= 0; sector--) { + if(addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *)dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if((retcode = flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar)cnt-1); + while(cnt-- > 0) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check(info, sector, info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci440/u-boot.lds b/board/esd/cpci440/u-boot.lds new file mode 100644 index 000000000..57220d385 --- /dev/null +++ b/board/esd/cpci440/u-boot.lds @@ -0,0 +1,159 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : +/* .resetvec 0x01FFFFFC :*/ + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : +/* .bootpg 0x01FFF000 :*/ + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/esd/cpci440/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile index 4a640f663..2ca73a99e 100644 --- a/board/esd/cpci5200/Makefile +++ b/board/esd/cpci5200/Makefile @@ -1,5 +1,6 @@ + # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,38 +23,31 @@ # include $(TOPDIR)/config.mk -# ifneq ($(OBJTREE),$(SRCTREE)) -# $(shell mkdir -p $(obj)../common/xilinx_jtag) -# endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a # Objects for Xilinx JTAG programming (CPLD) # CPLD = ../common/xilinx_jtag/lenval.o \ -# ../common/xilinx_jtag/micro.o \ -# ../common/xilinx_jtag/ports.o +# ../common/xilinx_jtag/micro.o \ +# ../common/xilinx_jtag/ports.o -# COBJS = $(BOARD).o flash.o $(CPLD) -COBJS = $(BOARD).o strataflash.o +# OBJS = $(BOARD).o flash.o $(CPLD) +OBJS = $(BOARD).o strataflash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/esd/cpci5200/config.mk b/board/esd/cpci5200/config.mk index 170779d6c..07b5de188 100644 --- a/board/esd/cpci5200/config.mk +++ b/board/esd/cpci5200/config.mk @@ -32,7 +32,7 @@ # 0x00100000 boot from RAM (for testing only) # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE ## Standard: boot high diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c index 20130acfe..6c98f13fb 100644 --- a/board/esd/cpci5200/cpci5200.c +++ b/board/esd/cpci5200/cpci5200.c @@ -84,7 +84,7 @@ static void sdram_start(int hi_addr) * is something else than 0x00000000. */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { ulong dramsize = 0; ulong test1, test2; @@ -191,12 +191,15 @@ static struct pci_controller hose; extern void pci_mpc5xxx_init(struct pci_controller *); -void pci_init_board(void) { +void pci_init_board(void + ) { pci_mpc5xxx_init(&hose); } #endif -#if defined(CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL void init_ide_reset(void) { @@ -212,12 +215,12 @@ void ide_set_reset(int idereset) debug("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; } } -#endif +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ #define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) #define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) @@ -239,7 +242,7 @@ void init_ata_reset(void) debug("init_ata_reset\n"); /* Configure GPIO_WU6 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; __asm__ volatile ("sync"); diff --git a/board/esd/cpci5200/u-boot.lds b/board/esd/cpci5200/u-boot.lds new file mode 100644 index 000000000..f23432ecf --- /dev/null +++ b/board/esd/cpci5200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile index 4379cfc74..cd38b2d8d 100644 --- a/board/esd/cpci750/Makefile +++ b/board/esd/cpci750/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2001 # Josh Huber , Mission Critical Linux, Inc. # @@ -25,30 +22,23 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../../Marvell/common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a SOBJS = misc.o -COBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \ +OBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \ mv_eth.o mpsc.o i2c.o \ sdram_init.o ide.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 298aa6a19..dbed59717 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -29,7 +29,6 @@ */ #include -#include #include <74xx_7xx.h> #include "../../Marvell/include/memory.h" #include "../../Marvell/include/pci.h" @@ -55,71 +54,6 @@ #define DP(x) #endif -static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */ - {"PCI0DLL_1 "}, /* 30 */ - {"PCI0DLL_0 "}, /* 29 */ - {"PCI1DLL_2 "}, /* 28 */ - {"PCI1DLL_1 "}, /* 27 */ - {"PCI1DLL_0 "}, /* 26 */ - {"BbEP2En "}, /* 25 */ - {"SDRAMRdDataDel"}, /* 24 */ - {"SDRAMRdDel "}, /* 23 */ - {"SDRAMSync "}, /* 22 */ - {"SDRAMPipeSel_1"}, /* 21 */ - {"SDRAMPipeSel_0"}, /* 20 */ - {"SDRAMAddDel "}, /* 19 */ - {"SDRAMClkSel "}, /* 18 */ - {"Reserved(1!) "}, /* 17 */ - {"PCIRty "}, /* 16 */ - {"BootCSWidth_1 "}, /* 15 */ - {"BootCSWidth_0 "}, /* 14 */ - {"PCI1PadsCal "}, /* 13 */ - {"PCI0PadsCal "}, /* 12 */ - {"MultiMVId_1 "}, /* 11 */ - {"MultiMVId_0 "}, /* 10 */ - {"MultiGTEn "}, /* 09 */ - {"Int60xArb "}, /* 08 */ - {"CPUBusConfig_1"}, /* 07 */ - {"CPUBusConfig_0"}, /* 06 */ - {"DefIntSpc "}, /* 05 */ - {0 }, /* 04 */ - {"SROMAdd_1 "}, /* 03 */ - {"SROMAdd_0 "}, /* 02 */ - {"DRAMPadCal "}, /* 01 */ - {"SInitEn "}, /* 00 */ - {0 }, /* 31 */ - {0 }, /* 30 */ - {0 }, /* 29 */ - {0 }, /* 28 */ - {0 }, /* 27 */ - {0 }, /* 26 */ - {0 }, /* 25 */ - {0 }, /* 24 */ - {0 }, /* 23 */ - {0 }, /* 22 */ - {"JTAGCalBy "}, /* 21 */ - {"GB2Sel "}, /* 20 */ - {"GB1Sel "}, /* 19 */ - {"DRAMPLL_MDiv_5"}, /* 18 */ - {"DRAMPLL_MDiv_4"}, /* 17 */ - {"DRAMPLL_MDiv_3"}, /* 16 */ - {"DRAMPLL_MDiv_2"}, /* 15 */ - {"DRAMPLL_MDiv_1"}, /* 14 */ - {"DRAMPLL_MDiv_0"}, /* 13 */ - {"GB0Sel "}, /* 12 */ - {"DRAMPLLPU "}, /* 11 */ - {"DRAMPLL_HIKVCO"}, /* 10 */ - {"DRAMPLLNP "}, /* 09 */ - {"DRAMPLL_NDiv_7"}, /* 08 */ - {"DRAMPLL_NDiv_6"}, /* 07 */ - {"CPUPadCal "}, /* 06 */ - {"DRAMPLL_NDiv_5"}, /* 05 */ - {"DRAMPLL_NDiv_4"}, /* 04 */ - {"DRAMPLL_NDiv_3"}, /* 03 */ - {"DRAMPLL_NDiv_2"}, /* 02 */ - {"DRAMPLL_NDiv_1"}, /* 01 */ - {"DRAMPLL_NDiv_0"}}; /* 00 */ - extern void flush_data_cache (void); extern void invalidate_l1_instruction_cache (void); extern flash_info_t flash_info[]; @@ -431,12 +365,12 @@ int misc_init_r () dcache_lock (); #endif if (flash_info[3].size < CFG_FLASH_INCREMENT) { - unsigned int flash_offset; + unsigned int flash_offset; unsigned int l; flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size; for (l = 0; l < CFG_MAX_FLASH_SECT; l++) { - if (flash_info[3].start[l] != 0) { + if (flash_info[3].start[l] != 0) { flash_info[3].start[l] += flash_offset; } } @@ -568,7 +502,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) { asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0"); /* Clobbers fr0 */ + : : : "fr0"); /* Clobbers fr0 */ return; } @@ -646,9 +580,9 @@ int mem_test_data (void) move64 (&(pattern[i]), pmem); move64 (pmem, &temp64); - /* hi = (temp64>>32) & 0xffffffff; */ - /* lo = temp64 & 0xffffffff; */ - /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ + /* hi = (temp64>>32) & 0xffffffff; */ + /* lo = temp64 & 0xffffffff; */ + /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */ hi = (pattern[i] >> 32) & 0xffffffff; lo = pattern[i] & 0xffffffff; @@ -921,11 +855,11 @@ int testdram (void) } #endif /* CFG_DRAM_TEST */ -/* ronen - the below functions are used by the bootm function */ +/* ronen - the below functions are used by the bootm function */ /* - we map the base register to fbe00000 (same mapping as in the LSP) */ /* - we turn off the RX gig dmas - to prevent the dma from overunning */ -/* the kernel data areas. */ -/* - we diable and invalidate the icache and dcache. */ +/* the kernel data areas. */ +/* - we diable and invalidate the icache and dcache. */ void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc) { u32 temp; @@ -965,38 +899,3 @@ void board_prebootm_init () flush_data_cache (); dcache_disable (); } - -int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int reset_sample_low; - unsigned int reset_sample_high; - unsigned int l, l1, l2; - - GT_REG_READ(0x3c4, &reset_sample_low); - GT_REG_READ(0x3d4, &reset_sample_high); - printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high); - - l2 = 0; - for (l=0; l<63; l++) { - if (show_config_tab[l][0] != 0) { - printf("%14s:%1x ", show_config_tab[l], - ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01); - l2++; - if ((l2 % 4) == 0) - printf("\n"); - } else { - l1++; - } - if (l == 32) - reset_sample_low = reset_sample_high; - } - printf("\n"); - - return(0); -} - -U_BOOT_CMD( - show_config, 1, 1, do_show_config, - "show_config - Show Marvell strapping register\n", - "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n" - ); diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index 0adafe2d0..bea99ce8e 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -25,7 +25,7 @@ #include -#if defined(CONFIG_CMD_IDE) +#ifdef CFG_CMD_IDE #include #include #include @@ -43,8 +43,6 @@ int ide_preinit (void) ide_bus_offset[l] = -ATA_STATUS; } devbusfn = pci_find_device (0x1103, 0x0004, 0); - if (devbusfn == -1) - devbusfn = pci_find_device (0x1095, 0x3114, 0); if (devbusfn != -1) { status = 0; diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c index fa8d3bda9..25c10e062 100644 --- a/board/esd/cpci750/mpsc.c +++ b/board/esd/cpci750/mpsc.c @@ -426,7 +426,7 @@ void mpsc_sdma_init (void) (MV64360_SDMA_WIN_ACCESS_FULL << (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); -/* Setup MPSC internal address space base address */ +/* Setup MPSC internal address space base address */ GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); /* no high address remap*/ diff --git a/board/esd/cpci750/mpsc.h b/board/esd/cpci750/mpsc.h index aa0f862ee..a03d1cc0f 100644 --- a/board/esd/cpci750/mpsc.h +++ b/board/esd/cpci750/mpsc.h @@ -67,9 +67,9 @@ extern int (*mpsc_test_char)(void); #define TX_STOP 0x00010000 #define RX_ENABLE 0x00000080 -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) +#define SDMA_RX_ABORT (1 << 15) +#define SDMA_TX_ABORT (1 << 31) +#define MPSC_TX_ABORT (1 << 7) #define MPSC_RX_ABORT (1 << 23) #define MPSC_ENTER_HUNT (1 << 31) diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c index 1c215277c..bc84ef08e 100644 --- a/board/esd/cpci750/mv_eth.c +++ b/board/esd/cpci750/mv_eth.c @@ -1392,7 +1392,7 @@ u32 mv_get_internal_sram_base (void) * port_phy_addr). * * INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct * * OUTPUT: * See description. @@ -1552,7 +1552,7 @@ static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) * ether_init_rx_desc_ring for Rx queues). * * INPUT: -* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct +* ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct * * OUTPUT: * Ethernet port is ready to receive and transmit. @@ -1642,7 +1642,7 @@ static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) * INPUT: * ETH_PORT eth_port_num Port number. * char * p_addr Address to be set -* ETH_QUEUE queue Rx queue number for this MAC address. +* ETH_QUEUE queue Rx queue number for this MAC address. * * OUTPUT: * Set MAC address low and high registers. also calls eth_port_uc_addr() @@ -1680,10 +1680,10 @@ static void eth_port_uc_addr_set (ETH_PORT eth_port_num, * parameters. * * INPUT: -* ETH_PORT eth_port_num Port number. +* ETH_PORT eth_port_num Port number. * unsigned char uc_nibble Unicast MAC Address last nibble. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * This function add/removes MAC addresses from the port unicast address @@ -1762,10 +1762,10 @@ static bool eth_port_uc_addr (ETH_PORT eth_port_num, * In this case, the function calculates the CRC-8bit value and calls * eth_port_omc_addr() routine to set the Other Multicast Table. * INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char *p_addr Unicast MAC Address. -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_PORT eth_port_num Port number. +* unsigned char *p_addr Unicast MAC Address. +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * See description. @@ -1896,10 +1896,10 @@ static void eth_port_mc_addr (ETH_PORT eth_port_num, * according to the argument given. * * INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_PORT eth_port_num Port number. +* unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * See description. @@ -1960,10 +1960,10 @@ static bool eth_port_smc_addr (ETH_PORT eth_port_num, * CRC-8 argument given. * * INPUT: -* ETH_PORT eth_port_num Port number. -* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -* ETH_QUEUE queue Rx queue number for this MAC address. -* int option 0 = Add, 1 = remove address. +* ETH_PORT eth_port_num Port number. +* unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). +* ETH_QUEUE queue Rx queue number for this MAC address. +* int option 0 = Add, 1 = remove address. * * OUTPUT: * See description. @@ -2204,7 +2204,7 @@ static bool ethernet_phy_reset (ETH_PORT eth_port_num) * eth_port_reset - Reset Ethernet port * * DESCRIPTION: - * This routine resets the chip by aborting any SDMA engine activity and + * This routine resets the chip by aborting any SDMA engine activity and * clearing the MIB counters. The Receiver and the Transmit unit are in * idle state after this command is performed and the port is disabled. * @@ -2557,9 +2557,9 @@ static void eth_set_access_control (ETH_PORT eth_port_num, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. - * int rx_desc_num Number of Rx descriptors - * int rx_buff_size Size of Rx buffer + * ETH_QUEUE rx_queue Number of Rx queue. + * int rx_desc_num Number of Rx descriptors + * int rx_buff_size Size of Rx buffer * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. * unsigned int rx_buff_base_addr Rx buffer memory area base addr. * @@ -2651,9 +2651,9 @@ static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. - * int tx_desc_num Number of Tx descriptors - * int tx_buff_size Size of Tx buffer + * ETH_QUEUE tx_queue Number of Tx queue. + * int tx_desc_num Number of Tx descriptors + * int tx_buff_size Size of Tx buffer * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. * unsigned int tx_buff_base_addr Tx buffer memory area base addr. * @@ -2746,7 +2746,7 @@ static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. + * ETH_QUEUE tx_queue Number of Tx queue. * PKT_INFO *p_pkt_info User packet buffer. * * OUTPUT: @@ -2862,7 +2862,7 @@ static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE tx_queue Number of Tx queue. + * ETH_QUEUE tx_queue Number of Tx queue. * PKT_INFO *p_pkt_info User packet buffer. * * OUTPUT: @@ -2931,7 +2931,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * * eth_port_receive - Get received information from Rx ring. * * DESCRIPTION: - * This routine returns the received data to the caller. There is no + * This routine returns the received data to the caller. There is no * data copying during routine operation. All information is returned * using pointer to packet information struct passed from the caller. * If the routine exhausts Rx ring resources then the resource error flag @@ -2939,7 +2939,7 @@ static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. + * ETH_QUEUE rx_queue Number of Rx queue. * PKT_INFO *p_pkt_info User packet buffer. * * OUTPUT: @@ -2981,7 +2981,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, /* Nothing to receive... */ if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { -/* DP(printf("Rx: command_status: %08x\n", command_status)); */ +/* DP(printf("Rx: command_status: %08x\n", command_status)); */ D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); /* DP(printf("\nETH_END_OF_JOB ...\n"));*/ return ETH_END_OF_JOB; @@ -3020,7 +3020,7 @@ static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, * * INPUT: * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. - * ETH_QUEUE rx_queue Number of Rx queue. + * ETH_QUEUE rx_queue Number of Rx queue. * PKT_INFO *p_pkt_info Information on the returned buffer. * * OUTPUT: diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index 0291937e0..6bdfc1d1c 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -106,7 +106,7 @@ memory_map_bank(unsigned int bankNo, return 0; } -#define GB (1 << 30) +#define GB (1 << 30) /* much of this code is based on (or is) the code in the pip405 port */ /* thanks go to the authors of said port - Josh */ @@ -134,85 +134,86 @@ typedef enum _max_CL_supported_SD {SD_CL_1=1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL /* SDRAM/DDR information struct */ -typedef struct _gtMemoryDimmInfo { - MEMORY_TYPE memoryType; - unsigned int numOfRowAddresses; - unsigned int numOfColAddresses; - unsigned int numOfModuleBanks; - unsigned int dataWidth; - VOLTAGE_INTERFACE voltageInterface; - unsigned int errorCheckType; /* ECC , PARITY.. */ - unsigned int sdramWidth; /* 4,8,16 or 32 */ ; - unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ - unsigned int minClkDelay; - unsigned int burstLengthSupported; - unsigned int numOfBanksOnEachDevice; - unsigned int suportedCasLatencies; - unsigned int RefreshInterval; - unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ - unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ - MAX_CL_SUPPORTED_DDR maxClSupported_DDR; - MAX_CL_SUPPORTED_SD maxClSupported_SD; - unsigned int moduleBankDensity; - /* module attributes (true for yes) */ - bool bufferedAddrAndControlInputs; - bool registeredAddrAndControlInputs; - bool onCardPLL; - bool bufferedDQMBinputs; - bool registeredDQMBinputs; - bool differentialClockInput; - bool redundantRowAddressing; +typedef struct _gtMemoryDimmInfo +{ + MEMORY_TYPE memoryType; + unsigned int numOfRowAddresses; + unsigned int numOfColAddresses; + unsigned int numOfModuleBanks; + unsigned int dataWidth; + VOLTAGE_INTERFACE voltageInterface; + unsigned int errorCheckType; /* ECC , PARITY..*/ + unsigned int sdramWidth; /* 4,8,16 or 32 */; + unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ + unsigned int minClkDelay; + unsigned int burstLengthSupported; + unsigned int numOfBanksOnEachDevice; + unsigned int suportedCasLatencies; + unsigned int RefreshInterval; + unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ + unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns)*/ + MAX_CL_SUPPORTED_DDR maxClSupported_DDR; + MAX_CL_SUPPORTED_SD maxClSupported_SD; + unsigned int moduleBankDensity; + /* module attributes (true for yes) */ + bool bufferedAddrAndControlInputs; + bool registeredAddrAndControlInputs; + bool onCardPLL; + bool bufferedDQMBinputs; + bool registeredDQMBinputs; + bool differentialClockInput; + bool redundantRowAddressing; - /* module general attributes */ - bool suportedAutoPreCharge; - bool suportedPreChargeAll; - bool suportedEarlyRasPreCharge; - bool suportedWrite1ReadBurst; - bool suported5PercentLowVCC; - bool suported5PercentUpperVCC; - /* module timing parameters */ - unsigned int minRasToCasDelay; - unsigned int minRowActiveRowActiveDelay; - unsigned int minRasPulseWidth; - unsigned int minRowPrechargeTime; /* measured in ns */ + /* module general attributes */ + bool suportedAutoPreCharge; + bool suportedPreChargeAll; + bool suportedEarlyRasPreCharge; + bool suportedWrite1ReadBurst; + bool suported5PercentLowVCC; + bool suported5PercentUpperVCC; + /* module timing parameters */ + unsigned int minRasToCasDelay; + unsigned int minRowActiveRowActiveDelay; + unsigned int minRasPulseWidth; + unsigned int minRowPrechargeTime; /* measured in ns */ - int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ - int addrAndCommandSetupTime; /* (measured in ns/100) */ - int dataInputSetupTime; /* LoP left of point (measured in ns) */ - int dataInputHoldTime; /* LoP left of point (measured in ns) */ + int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ + int addrAndCommandSetupTime; /* (measured in ns/100) */ + int dataInputSetupTime; /* LoP left of point (measured in ns) */ + int dataInputHoldTime; /* LoP left of point (measured in ns) */ /* tAC times for highest 2nd and 3rd highest CAS Latency values */ - unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ - unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ + unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns)*/ + unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns)*/ + unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ + unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns)*/ - unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns)*/ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns)*/ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ - unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ + unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns)*/ - /* Parameters calculated from - the extracted DIMM information */ - unsigned int size; - unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ - unsigned int numberOfDevices; - uchar drb_size; /* DRAM size in n*64Mbit */ - uchar slot; /* Slot Number this module is inserted in */ - uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ + /* Parameters calculated from + the extracted DIMM information */ + unsigned int size; + unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ + unsigned int numberOfDevices; + uchar drb_size; /* DRAM size in n*64Mbit */ + uchar slot; /* Slot Number this module is inserted in */ + uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ #ifdef DEBUG - uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ - uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ - uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ - unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ - unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ - unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ - uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ + uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ + uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ + uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ + unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ + unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ + unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ + uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ #endif } AUX_MEM_DIMM_INFO; @@ -363,31 +364,31 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { dimmInfo->manufactura[i] = data[64 + i]; } - printf ("\nThis RAM-Module is produced by: %s\n", + printf ("\nThis RAM-Module is produced by: %s\n", dimmInfo->manufactura); /* find Manul-ID of Dimm Module */ for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { dimmInfo->modul_id[i] = data[73 + i]; } - printf ("The Module-ID of this RAM-Module is: %s\n", + printf ("The Module-ID of this RAM-Module is: %s\n", dimmInfo->modul_id); /* find Vendor-Data of Dimm Module */ for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { dimmInfo->vendor_data[i] = data[99 + i]; } - printf ("Vendor Data of this RAM-Module is: %s\n", + printf ("Vendor Data of this RAM-Module is: %s\n", dimmInfo->vendor_data); /* find modul_serial_no of Dimm Module */ dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); - printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", + printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); /* find Manufac-Data of Dimm Module */ dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); - printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ + printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ /* find modul_revision of Dimm Module */ dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); @@ -395,7 +396,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /* find manufac_place of Dimm Module */ dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); - printf ("manufac_place of this RAM-Module is: %d\n", + printf ("manufac_place of this RAM-Module is: %d\n", dimmInfo->manufac_place); #endif @@ -425,11 +426,11 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) #ifdef DEBUG if (dimmInfo->memoryType == 0) DP (printf - ("Dram_type in slot %d is: SDRAM\n", + ("Dram_type in slot %d is: SDRAM\n", dimmInfo->slot)); if (dimmInfo->memoryType == 1) DP (printf - ("Dram_type in slot %d is: DDRAM\n", + ("Dram_type in slot %d is: DDRAM\n", dimmInfo->slot)); #endif break; @@ -438,7 +439,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; DP (printf - ("Module Number of row addresses: %d\n", + ("Module Number of row addresses: %d\n", dimmInfo->numOfRowAddresses)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -446,7 +447,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; DP (printf - ("Module Number of col addresses: %d\n", + ("Module Number of col addresses: %d\n", dimmInfo->numOfColAddresses)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -462,7 +463,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; DP (printf - ("Module Data Width: %d\n", + ("Module Data Width: %d\n", dimmInfo->dataWidth)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -517,7 +518,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; DP (printf - ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", + ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", leftOfPoint, rightOfPoint)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -532,7 +533,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; DP (printf - ("Clock To Data Out: %d.%2d [ns]\n", + ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ break; @@ -542,7 +543,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; DP (printf - ("Error Check Type (0=NONE): %d\n", + ("Error Check Type (0=NONE): %d\n", dimmInfo->errorCheckType)); break; #endif @@ -559,7 +560,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; DP (printf - ("Sdram Width: %d\n", + ("Sdram Width: %d\n", dimmInfo->sdramWidth)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -567,7 +568,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; DP (printf - ("Error Check Data Width: %d\n", + ("Error Check Data Width: %d\n", dimmInfo->errorCheckDataWidth)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -575,7 +576,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; DP (printf - ("Minimum Clock Delay: %d\n", + ("Minimum Clock Delay: %d\n", dimmInfo->minClkDelay)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -584,7 +585,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /******-******-******-******* * bit3 | bit2 | bit1 | bit0 * *******-******-******-******* - burst length = * 8 | 4 | 2 | 1 * + burst length = * 8 | 4 | 2 | 1 * ***************************** If for example bit0 and bit2 are set, the burst @@ -593,7 +594,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->burstLengthSupported = data[i]; #ifdef DEBUG DP (printf - ("Burst Length Supported: ")); + ("Burst Length Supported: ")); if (dimmInfo->burstLengthSupported & 0x01) DP (printf ("1, ")); if (dimmInfo->burstLengthSupported & 0x02) @@ -610,7 +611,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; DP (printf - ("Number Of Banks On Each Chip: %d\n", + ("Number Of Banks On Each Chip: %d\n", dimmInfo->numOfBanksOnEachDevice)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -621,24 +622,24 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) *******-******-******-******-******-******-******-******* * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * *******-******-******-******-******-******-******-******* - CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * + CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ********************************************************* SDRAM: *******-******-******-******-******-******-******-******* * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * *******-******-******-******-******-******-******-******* - CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * + CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ********************************************************/ dimmInfo->suportedCasLatencies = data[i]; #ifdef DEBUG DP (printf - ("Suported Cas Latencies: (CL) ")); + ("Suported Cas Latencies: (CL) ")); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) DP (printf - ("%d, ", + ("%d, ", k + 1)); } @@ -737,7 +738,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) maxCASlatencySupported_RoP = 0; DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> @@ -745,7 +746,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ - dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ + dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ DP (printf ("Max. Cas Latencies (SD): %d\n", dimmInfo-> @@ -885,7 +886,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) (" - lower VCC tolerance: 5 Percent \n")); else DP (printf - (" - lower VCC tolerance: 10 Percent \n")); + (" - lower VCC tolerance: 10 Percent \n")); if (dimmInfo->suported5PercentUpperVCC == 1) DP (printf @@ -985,7 +986,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", tmemclk, tmemclk / 100, tmemclk % 100)); DP (printf - ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", + ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1004,7 +1005,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) (dimmInfo->minRowActiveRowActiveDelay + (tmemclk - 1)) / tmemclk; DP (printf - ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", + ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1023,7 +1024,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) (dimmInfo->minRowActiveRowActiveDelay + (tmemclk - 1)) / tmemclk; DP (printf - ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", + ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", leftOfPoint, rightOfPoint, trp_clocks)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1034,7 +1035,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) (NSto10PS (data[i]) + (tmemclk - 1)) / tmemclk; DP (printf - ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", + ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", dimmInfo->minRasPulseWidth, tras_clocks)); break; @@ -1043,7 +1044,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) case 31: /* Module Bank Density */ dimmInfo->moduleBankDensity = data[i]; DP (printf - ("Module Bank Density: %d\n", + ("Module Bank Density: %d\n", dimmInfo->moduleBankDensity)); #ifdef DEBUG DP (printf @@ -1094,7 +1095,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->addrAndCommandSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; DP (printf - ("Address And Command Setup Time [ns]: %d.%d\n", + ("Address And Command Setup Time [ns]: %d.%d\n", sign * leftOfPoint, rightOfPoint)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1121,7 +1122,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; DP (printf - ("Address And Command Hold Time [ns]: %d.%d\n", + ("Address And Command Hold Time [ns]: %d.%d\n", sign * leftOfPoint, rightOfPoint)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1148,7 +1149,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->dataInputSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; DP (printf - ("Data Input Setup Time [ns]: %d.%d\n", + ("Data Input Setup Time [ns]: %d.%d\n", sign * leftOfPoint, rightOfPoint)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1175,7 +1176,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->dataInputHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; DP (printf - ("Data Input Hold Time [ns]: %d.%d\n\n", + ("Data Input Hold Time [ns]: %d.%d\n\n", sign * leftOfPoint, rightOfPoint)); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1211,7 +1212,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); tmp *= dimmInfo->numOfModuleBanks; tmp *= dimmInfo->sdramWidth; - tmp = tmp >> 24; /* div by 0x4000000 (64M) */ + tmp = tmp >> 24; /* div by 0x4000000 (64M) */ dimmInfo->drb_size = (uchar) tmp; DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); @@ -1251,7 +1252,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /* sets up the GT properly with information passed in */ int setup_sdram (AUX_MEM_DIMM_INFO * info) { - ulong tmp; + ulong tmp, check; ulong tmp_sdram_mode = 0; /* 0x141c */ ulong tmp_dunit_control_low = 0; /* 0x1404 */ int i; @@ -1327,7 +1328,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) DP (printf ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", tmp_sdram_mode, tmp_dunit_control_low)); - } else { /* clk sync. bypassed */ + } else { /* clk sync. bypassed */ tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ @@ -1344,7 +1345,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) DP (printf ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", tmp_sdram_mode, tmp_dunit_control_low)); - } else { /* Not sync. */ + } else { /* Not sync. */ tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */ tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ @@ -1503,8 +1504,6 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ { - int l, l1; - i = info->slot; DP (printf ("\n*** Running a MRS cycle for bank %d ***\n", i)); @@ -1512,39 +1511,20 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* map the bank */ memory_map_bank (i, 0, GB / 4); #if 1 /* test only */ - - tmp = GTREGREAD (SDRAM_MODE); - GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0); - GT_REG_WRITE (SDRAM_OPERATION, 0x4); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); - } - - GT_REG_WRITE (SDRAM_MODE, tmp | 0x80); + /* set SDRAM mode */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); - } - l1 = 0; - for (l=0;l<200;l++) - l1 += GTREGREAD (SDRAM_OPERATION); + check = GTREGREAD (SDRAM_OPERATION); + DP (printf + ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", + check)); - GT_REG_WRITE (SDRAM_MODE, tmp); - GT_REG_WRITE (SDRAM_OPERATION, 0x3); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); - } /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0x5); - while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); - } - + GT_REG_WRITE (SDRAM_OPERATION, 0); + check = GTREGREAD (SDRAM_OPERATION); + DP (printf + ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", + check)); #endif /* test only */ /* unmap the bank */ memory_map_bank (i, 0, 0); @@ -1570,8 +1550,8 @@ dram_size(long int *base, long int maxsize) for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) { addr = base + cnt; /* pointer arith! */ - save1 = *addr; /* save contents of addr */ - save2 = *b; /* save contents of base */ + save1=*addr; /* save contents of addr */ + save2=*b; /* save contents of base */ *addr=cnt; /* write cnt to addr */ *b=0; /* put null at base */ @@ -1602,7 +1582,7 @@ dram_size(long int *base, long int maxsize) /* ppcboot interface function to SDRAM init - this is where all the * controlling logic happens */ -phys_size_t +long int initdram(int board_type) { int s0 = 0, s1 = 0; @@ -1676,16 +1656,16 @@ initdram(int board_type) } /* *************************************************************************************** -! * SDRAM INIT * -! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * -! * This procedure fits only the Atlantis * -! * * +! * SDRAM INIT * +! * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * +! * This procedure fits only the Atlantis * +! * * ! *************************************************************************************** */ /* *************************************************************************************** -! * DFCDL initialize MV643xx Design Considerations * -! * * +! * DFCDL initialize MV643xx Design Considerations * +! * * ! *************************************************************************************** */ int set_dfcdlInit (void) { diff --git a/board/esd/cpci750/serial.c b/board/esd/cpci750/serial.c index e1af37e1d..ba32ac12a 100644 --- a/board/esd/cpci750/serial.c +++ b/board/esd/cpci750/serial.c @@ -80,7 +80,7 @@ void serial_puts (const char *s) } } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) void kgdb_serial_init (void) { } @@ -104,4 +104,4 @@ void kgdb_interruptible (int yes) { return; } -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/board/esd/cpci750/strataflash.c b/board/esd/cpci750/strataflash.c new file mode 100644 index 000000000..c22fe5df1 --- /dev/null +++ b/board/esd/cpci750/strataflash.c @@ -0,0 +1,763 @@ +/* + * (C) Copyright 2002 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#undef DEBUG_FLASH +/* + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + + +#define FLASH_MAN_CFI 0x01000000 + + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; +} cfiword_t; + +typedef union { + unsigned char * cp; + unsigned short *wp; + unsigned long *lp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +/*----------------------------------------------------------------------- + * Functions + */ + + +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); +static int flash_detect_cfi(flash_info_t * info); +static ulong flash_get_size (ulong base, int banknum); +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); +#endif +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) +{ + return ((uchar *)(info->start[sect] + (offset * info->portwidth))); +} +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar(flash_info_t * info, uchar offset) +{ + uchar *cp; + cp = flash_make_addr(info, 0, offset); + return (cp[info->portwidth - 1]); +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); + +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long(flash_info_t * info, int sect, uchar offset) +{ + uchar * addr; + + addr = flash_make_addr(info, sect, offset); + return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | + (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); + +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size; + int i; + unsigned long address; + + + /* The flash is positioned back to back, with the demultiplexing of the chip + * based on the A24 address line. + * + */ + + address = CFG_FLASH_BASE; + size = 0; + + /* Init: no FLASHes known */ + for (i=0; i= CFG_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) + (void)flash_real_protect(&flash_info[0], i, 1); +#endif +#endif + + return (size); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + int sect; + + if( info->flash_id != FLASH_MAN_CFI) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + printf ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + + if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + printf("."); + } + } + printf (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + printf ("missing or unknown FLASH type\n"); + return; + } + + printf("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3 ), (info->chipwidth << 3 )); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n"); + printf (" %08lX%5s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for(i=0;iportwidth) && (cnt > 0) ; i++) { + flash_add_byte(info, &cword, *src++); + cnt--; + cp++; + } + for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte(info, &cword, (*(uchar *)cp)); + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp = cp; + } + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + while(cnt >= info->portwidth) { + i = info->buffer_size > cnt? cnt: info->buffer_size; + if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) + return rc; + wp += i; + src += i; + cnt -=i; + } +#else + /* handle the aligned part */ + while(cnt >= info->portwidth) { + cword.l = 0; + for(i = 0; i < info->portwidth; i++) { + flash_add_byte(info, &cword, *src++); + } + if((rc = flash_write_cfiword(info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i=0, cp=wp; (iportwidth) && (cnt>0); ++i, ++cp) { + flash_add_byte(info, &cword, *src++); + --cnt; + } + for (; iportwidth; ++i, ++cp) { + flash_add_byte(info, & cword, (*(uchar *)cp)); + } + + return flash_write_cfiword(info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); + if(prot) + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, + prot?"protect":"unprotect")) == 0) { + + info->protect[sector] = prot; + /* Intel's unprotect unprotects all locking */ + if(prot == 0) { + int i; + for(i = 0 ; isector_count; i++) { + if(info->protect[i]) + flash_real_protect(info, i, 1); + } + } + } + + return retcode; +} +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + ulong start; + + /* Wait for command completion */ + start = get_timer (0); + while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { + if (get_timer(start) > info->erase_blk_tout) { + printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return ERR_TIMOUT; + } + } + return ERR_OK; +} +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) +{ + int retcode; + retcode = flash_status_check(info, sector, tout, prompt); + if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf("Flash %s error at address %lx\n", prompt,info->start[sector]); + if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ + printf("Command Sequence Error.\n"); + } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ + printf("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { + printf("Locking Error\n"); + } + if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ + printf("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) + printf("Vpp Low Error.\n"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); + return retcode; +} +/*----------------------------------------------------------------------- + */ +static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) +{ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: + cword->w = (cword->w << 8) | c; + break; + case FLASH_CFI_32BIT: + cword->l = (cword->l << 8) | c; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) +{ + int i; + uchar *cp = (uchar *)cmdbuf; + for(i=0; i< info->portwidth; i++) + *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; +} + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + addr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *addr.cp = cword.c; + break; + case FLASH_CFI_16BIT: + *addr.wp = cword.w; + break; + case FLASH_CFI_32BIT: + *addr.lp = cword.l; + break; + } +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + retval = (cptr.lp[0] == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} +/*----------------------------------------------------------------------- + */ +static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + cptr.cp = flash_make_addr(info, sect, offset); + flash_make_cmd(info, cmd, &cword); + switch(info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * + */ +static int flash_detect_cfi(flash_info_t * info) +{ + + for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; + info->portwidth <<= 1) { + for(info->chipwidth =FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && + flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) + return 1; + } + } + return 0; +} +/* + * The following code cannot be run from FLASH! + * + */ +static ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t * info = &flash_info[banknum]; + int i, j; + int sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio = 0; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; + + info->start[0] = base; + + invalidate_dcache_range(base, base+0x400); + + if(flash_detect_cfi(info)){ + + size_ratio = info->portwidth / info->chipwidth; + num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); + + sect_cnt = 0; + sector = base; + for(i = 0 ; i < num_erase_regions; i++) { + if(i > NUM_ERASE_REGIONS) { + printf("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); + erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) +1; + for(j = 0; j< erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); + info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); + info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; + info->flash_id = FLASH_MAN_CFI; + } + + flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); +#ifdef DEBUG_FLASH + printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ +#endif +#ifdef DEBUG_FLASH + printf("found %d erase regions\n", num_erase_regions); +#endif +#ifdef DEBUG_FLASH + printf("size=%08x sectors=%08x \n", info->size, info->sector_count); +#endif + return(info->size); +} + + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) +{ + + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr(info, 0, 0); + cptr.cp = (uchar *)dest; + + + /* Check if Flash is (sufficiently) erased */ + switch(info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + default: + return 2; + } + if(!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); + + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + } + + /* re-enable interrupts if necessary */ + if(flag) + enable_interrupts(); + + return flash_full_status_check(info, 0, info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static int find_sector(flash_info_t *info, ulong addr) +{ + int sector; + for(sector = info->sector_count - 1; sector >= 0; sector--) { + if(addr >= info->start[sector]) + break; + } + return sector; +} + +static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) +{ + + int sector; + int cnt; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + + src.cp = cp; + dst.cp = (uchar *)dest; + sector = find_sector(info, dest); + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + if((retcode = flash_status_check(info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + break; + default: + return ERR_INVAL; + break; + } + flash_write_cmd(info, sector, 0, (uchar)cnt-1); + while(cnt-- > 0) { + switch(info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + default: + return ERR_INVAL; + break; + } + } + flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check(info, sector, info->buffer_write_tout, + "buffer write"); + } + flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); + return retcode; +} +#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci750/u-boot.lds b/board/esd/cpci750/u-boot.lds index 1a95755ab..d89eb6cff 100644 --- a/board/esd/cpci750/u-boot.lds +++ b/board/esd/cpci750/u-boot.lds @@ -26,6 +26,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -37,11 +38,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -125,7 +126,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile index ba92b24c8..a60495a59 100644 --- a/board/esd/cpciiser4/Makefile +++ b/board/esd/cpciiser4/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,32 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c index 204117edf..fcb8cbbe7 100644 --- a/board/esd/cpciiser4/cpciiser4.c +++ b/board/esd/cpciiser4/cpciiser4.c @@ -186,7 +186,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (16 * 1024 * 1024); } diff --git a/board/esd/cpciiser4/u-boot.lds b/board/esd/cpciiser4/u-boot.lds index 21547ac27..f7a20d1da 100644 --- a/board/esd/cpciiser4/u-boot.lds +++ b/board/esd/cpciiser4/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile index d736af8b9..e3b1c872b 100644 --- a/board/esd/dasa_sim/Makefile +++ b/board/esd/dasa_sim/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,32 +23,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c index fb0c77e56..2f8ab1a47 100644 --- a/board/esd/dasa_sim/dasa_sim.c +++ b/board/esd/dasa_sim/dasa_sim.c @@ -206,7 +206,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (16 * 1024 * 1024); } diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index 67d72f77f..fef5b5243 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/iop480_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -152,7 +153,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile index 86bd4461d..a11ee82aa 100644 --- a/board/esd/dp405/Makefile +++ b/board/esd/dp405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,37 +22,30 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a # Objects for Xilinx JTAG programming (CPLD) CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index bb3baa477..240ab78aa 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -122,7 +122,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; diff --git a/board/esd/dp405/u-boot.lds b/board/esd/dp405/u-boot.lds index d70d37934..43f776579 100644 --- a/board/esd/dp405/u-boot.lds +++ b/board/esd/dp405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -138,7 +139,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile index ba92b24c8..5ec4a4fd4 100644 --- a/board/esd/du405/Makefile +++ b/board/esd/du405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,32 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 78ae4ba67..a019ce421 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -25,7 +25,7 @@ #include "du405.h" #include #include -#include <4xx_i2c.h> +#include <405gp_i2c.h> #include DECLARE_GLOBAL_DATA_PTR; @@ -200,7 +200,7 @@ int checkboard (void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (16 * 1024 * 1024); } diff --git a/board/esd/du405/u-boot.lds b/board/esd/du405/u-boot.lds index 46ef7e72a..1cf375fef 100644 --- a/board/esd/du405/u-boot.lds +++ b/board/esd/du405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile index c57d90cf6..9340a32a5 100644 --- a/board/esd/hh405/Makefile +++ b/board/esd/hh405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,35 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - ../common/auto_update.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 802491a31..ea344c0f2 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -5,7 +5,7 @@ * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * (C) Copyright 2006-2007 + * (C) Copyright 2006 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -471,11 +471,17 @@ int misc_init_r (void) */ *fpga_ctrl |= gd->board_type & 0x0003; - /* + /* * Setup and enable EEPROM write protection */ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + /* * Reset touch-screen controller */ @@ -644,7 +650,7 @@ int checkboard (void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; @@ -684,6 +690,20 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif + + #if defined(CFG_EEPROM_WREN) /* Input: I2C address of EEPROM device to enable. * -1: deliver current state diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds index 21547ac27..f7a20d1da 100644 --- a/board/esd/hh405/u-boot.lds +++ b/board/esd/hh405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile index 98acb4b77..a60495a59 100644 --- a/board/esd/hub405/Makefile +++ b/board/esd/hub405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,34 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index 03b87c9df..1e0accbe0 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -152,6 +152,12 @@ int misc_init_r (void) out32(GPIO0_OR, val); + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + /* * check board type and setup AP power */ @@ -229,12 +235,40 @@ int checkboard (void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } + + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif diff --git a/board/esd/hub405/u-boot.lds b/board/esd/hub405/u-boot.lds index f21c7aad4..98338e935 100644 --- a/board/esd/hub405/u-boot.lds +++ b/board/esd/hub405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile index edf3c5686..b3039c634 100644 --- a/board/esd/ocrtc/Makefile +++ b/board/esd/ocrtc/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,32 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o cmd_ocrtc.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c index f83dfe870..ffbb4addd 100644 --- a/board/esd/ocrtc/cmd_ocrtc.c +++ b/board/esd/ocrtc/cmd_ocrtc.c @@ -25,10 +25,10 @@ #include #include #include -#include +#include <405gp_pci.h> -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) /* * Set device number on pci board diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c index 7b0edd595..261b8a54d 100644 --- a/board/esd/ocrtc/ocrtc.c +++ b/board/esd/ocrtc/ocrtc.c @@ -101,7 +101,7 @@ int checkboard (void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; diff --git a/board/esd/ocrtc/u-boot.lds b/board/esd/ocrtc/u-boot.lds index 5fb969944..476b4a055 100644 --- a/board/esd/ocrtc/u-boot.lds +++ b/board/esd/ocrtc/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile index 862e88d39..6db564f86 100644 --- a/board/esd/pci405/Makefile +++ b/board/esd/pci405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,34 +22,27 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../common/misc.o cmd_pci405.o +OBJS = $(BOARD).o flash.o ../common/misc.o cmd_pci405.o SOBJS = writeibm.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) -# $(AR) $(ARFLAGS) $@ $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +# $(AR) crv $@ $(OBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index 5c717e253..0315c3d97 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -27,13 +27,13 @@ #include #include #include -#include +#include <405gp_pci.h> #include #include "pci405.h" -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) extern int do_bootm (cmd_tbl_t *, int, int, char *[]); extern int do_bootvx (cmd_tbl_t *, int, int, char *[]); @@ -735,7 +735,7 @@ U_BOOT_CMD( ); -#define SECTOR_SIZE 32 /* 32 byte cache line */ +#define SECTOR_SIZE 32 /* 32 byte cache line */ #define SECTOR_MASK 0x1F void my_flush_dcache(ulong lcl_addr, ulong count) diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index f740d595b..e5d2273f0 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include <405gp_pci.h> #include "pci405.h" @@ -358,7 +358,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; diff --git a/board/esd/pci405/u-boot.lds b/board/esd/pci405/u-boot.lds index 21547ac27..f7a20d1da 100644 --- a/board/esd/pci405/u-boot.lds +++ b/board/esd/pci405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile index efd24feef..603bbe283 100644 --- a/board/esd/pf5200/Makefile +++ b/board/esd/pf5200/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,38 +23,31 @@ # include $(TOPDIR)/config.mk -# ifneq ($(OBJTREE),$(SRCTREE)) -# $(shell mkdir -p $(obj)../common/xilinx_jtag) -# endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a # Objects for Xilinx JTAG programming (CPLD) # CPLD = ../common/xilinx_jtag/lenval.o \ -# ../common/xilinx_jtag/micro.o \ -# ../common/xilinx_jtag/ports.o +# ../common/xilinx_jtag/micro.o \ +# ../common/xilinx_jtag/ports.o -# COBJS = $(BOARD).o flash.o $(CPLD) -COBJS = $(BOARD).o flash.o +# OBJS = $(BOARD).o flash.o $(CPLD) +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/esd/pf5200/config.mk b/board/esd/pf5200/config.mk index 170779d6c..07b5de188 100644 --- a/board/esd/pf5200/config.mk +++ b/board/esd/pf5200/config.mk @@ -32,7 +32,7 @@ # 0x00100000 boot from RAM (for testing only) # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE ## Standard: boot high diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c index 7970f8988..2b47012cf 100644 --- a/board/esd/pf5200/pf5200.c +++ b/board/esd/pf5200/pf5200.c @@ -84,7 +84,7 @@ static void sdram_start(int hi_addr) * is something else than 0x00000000. */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { ulong dramsize = 0; ulong test1, test2; @@ -191,12 +191,15 @@ static struct pci_controller hose; extern void pci_mpc5xxx_init(struct pci_controller *); -void pci_init_board(void) { +void pci_init_board(void + ) { pci_mpc5xxx_init(&hose); } #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL void init_ide_reset(void) { @@ -212,12 +215,12 @@ void ide_set_reset(int idereset) debug("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; } } -#endif +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ #define MPC5XXX_SIMPLEIO_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) #define MPC5XXX_SIMPLEIO_GPIO_DIR (MPC5XXX_GPIO + 0x000C) @@ -239,7 +242,7 @@ void init_power_switch(void) debug("init_power_switch\n"); /* Configure GPIO_WU6 as GPIO output for ATA reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_WU6; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_WU6; __asm__ volatile ("sync"); @@ -269,10 +272,10 @@ void power_set_reset(int power) debug("ide_set_reset(%d)\n", power); if (power) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_WU6; *(vu_long *) MPC5XXX_INTERRUPT_GPIO_DATA_OUTPUT &= ~GPIO_USB9; } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WU6; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_WU6; if ((*(vu_long *) MPC5XXX_INTERRUPT_GPIO_STATUS & GPIO_USB9S) == 0) { *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= diff --git a/board/esd/pf5200/u-boot.lds b/board/esd/pf5200/u-boot.lds new file mode 100644 index 000000000..f23432ecf --- /dev/null +++ b/board/esd/pf5200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile index c57d90cf6..9340a32a5 100644 --- a/board/esd/plu405/Makefile +++ b/board/esd/plu405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,35 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - ../common/auto_update.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/plu405/fpgadata.c b/board/esd/plu405/fpgadata.c index dc8c88b0e..f6656c150 100644 --- a/board/esd/plu405/fpgadata.c +++ b/board/esd/plu405/fpgadata.c @@ -1,1179 +1,1160 @@ - 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0xb6,0x74,0xd1,0x16,0x77,0x3c,0x98,0x2d,0x40,0x47,0x77,0x50,0x06,0xbb,0xe8,0x92, + 0x04,0x73,0x6d,0x22,0x07,0xb8,0x8f,0x0b,0x60,0x46,0x0b,0x81,0xf2,0x43,0xa8,0x02, + 0xc6,0x06,0xa1,0x99,0xb5,0xe4,0x18,0xe8,0x74,0x18,0x23,0x35,0x7e,0xce,0x78,0xee, + 0x8a,0xae,0xd1,0xf2,0xc7,0x1b,0x6e,0x81,0xbb,0x22,0x75,0xda,0x09,0x0a,0xaa,0xef, + 0x42,0x6b,0x28,0x98,0x4f,0x41,0x94,0x81,0x45,0xb7,0x70,0xf6,0x87,0xde,0xaf,0xb6, + 0xa5,0xbd,0xbe,0x70,0x47,0x63,0xfc,0xad,0x4e,0x97,0x06,0x50,0xb0,0x81,0x02,0x70, + 0xf8,0x80,0xbb,0xa2,0x6f,0xb4,0xf9,0xe1,0xf4,0x95,0x2b,0x19,0x3f,0xfc,0xc9,0x7d, + 0x37,0x1a,0xfc,0x70,0xaf,0xc1,0x0f,0x7f,0xc3,0xc0,0x8a,0xff,0x69,0xdf,0xfe,0x51, + 0x10,0x86,0xa1,0x38,0x8e,0x47,0xfc,0x83,0x83,0x9b,0xbb,0x8b,0x1e,0x20,0xce,0x1d, + 0x2a,0x38,0xb9,0xd4,0xdd,0xbb,0x68,0x3d,0x82,0x78,0x01,0x3d,0x8d,0x17,0x10,0x5c, + 0x45,0x70,0xd0,0xbd,0x20,0x0e,0x52,0xfb,0x5e,0x5b,0x6d,0x1d,0x0a,0xed,0xa0,0x20, + 0xdf,0xcf,0xd2,0x10,0x92,0xf0,0x96,0xc0,0xef,0x51,0x92,0xa9,0xdf,0xb8,0x69,0x3e, + 0x74,0xfc,0xa9,0xe4,0xc3,0xf0,0xe1,0x6a,0x30,0x0b,0xe2,0x7c,0xb8,0x0f,0x83,0x30, + 0x97,0xc7,0xca,0xd2,0x58,0x78,0x5d,0x45,0xc7,0xde,0x93,0xa0,0x38,0xd8,0x4c,0x64, + 0xa0,0xf9,0x50,0x67,0xe6,0xd9,0xf5,0x1a,0x0b,0x6f,0x67,0x29,0x23,0x0d,0x8a,0xbe, + 0x0e,0xe2,0x7c,0x28,0x33,0xb9,0xbc,0xea,0xa4,0xf9,0xb0,0xdf,0xf3,0x8e,0xeb,0xa1, + 0xac,0x5f,0x78,0xbb,0xae,0x6c,0x7c,0x45,0xcd,0xea,0xd5,0xdb,0xa8,0xc5,0x8a,0xae, + 0x75,0xf4,0x1d,0x77,0xaa,0x9f,0x02,0x00,0x00,0x00,0xe0,0xdf,0x69,0xef,0xd0,0xa0, + 0x77,0x00,0x00,0x00,0x00,0x50,0x4c,0x7b,0x87,0x16,0xbd,0x03,0x00,0x00,0x00,0x80, + 0x62,0xda,0x3b,0xb4,0xb5,0x77,0xf8,0x75,0x29,0x00,0x00,0x00,0x00,0xbe,0xc8,0xca, + 0xfb,0x38,0x73,0xb8,0x58,0xb3,0x94,0x57,0x2b,0x75,0x6b,0x46,0xa5,0xff,0x27,0x24, + 0x7b,0x9b,0xd6,0x6c,0x6b,0xef,0x33,0x4f,0xb3,0xcf,0x75,0x4f,0xaa,0x75,0xf0,0xc5, + 0xf1,0x33,0x01,0x00, diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index fc71e9a2a..37b92fb65 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -23,7 +23,6 @@ #include #include -#include #include #include @@ -32,8 +31,6 @@ #define FPGA_DEBUG #endif -DECLARE_GLOBAL_DATA_PTR; - extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern void lxt971_no_sleep(void); @@ -109,18 +106,14 @@ int misc_init_f (void) int misc_init_r (void) { - unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); + volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); + volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - dst = malloc(CFG_FPGA_MAX_SIZE); if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); @@ -184,28 +177,22 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ /* * Set NAND-FLASH GPIO signals to default */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE); - - /* - * Setup EEPROM write protection - */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); /* * Enable interrupts in exar duart mcr[3] */ - out_8(duart0_mcr, 0x08); - out_8(duart1_mcr, 0x08); + *duart0_mcr = 0x08; + *duart1_mcr = 0x08; return (0); } @@ -228,21 +215,41 @@ int checkboard (void) } putc ('\n'); + + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + + #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { @@ -261,84 +268,27 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} #endif -} -#if defined(CFG_EEPROM_WREN) -/* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) +#ifdef CONFIG_AUTO_UPDATE_SHOW +void board_auto_update_show(int au_active) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { - return -1; + if (au_active) { + printf("\n Dies ist die board-funktion: Updating!!!\n"); } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP)); - break; - } + printf("\n Dies ist die board-funktion: Updating done!!!\n"); } - return state; } - -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", - NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds index d70d37934..43f776579 100644 --- a/board/esd/plu405/u-boot.lds +++ b/board/esd/plu405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -138,7 +139,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile index 12c1ba730..741e4aacd 100644 --- a/board/esd/pmc405/Makefile +++ b/board/esd/pmc405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,37 +22,30 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a # Objects for Xilinx JTAG programming (CPLD) CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -COBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 326d56035..7499671aa 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -157,7 +157,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds index 81ee614f6..e84d69ebb 100644 --- a/board/esd/pmc405/u-boot.lds +++ b/board/esd/pmc405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -136,7 +137,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/tasreg/Makefile b/board/esd/tasreg/Makefile index cf07cf40f..e5d844631 100644 --- a/board/esd/tasreg/Makefile +++ b/board/esd/tasreg/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c index fabb7464f..16724005b 100644 --- a/board/esd/tasreg/tasreg.c +++ b/board/esd/tasreg/tasreg.c @@ -77,7 +77,7 @@ int checkboard (void) { }; -phys_size_t initdram (int board_type) { +long int initdram (int board_type) { unsigned long junk = 0xa5a59696; /* diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds index afdb7202c..a803b1cba 100644 --- a/board/esd/tasreg/u-boot.lds +++ b/board/esd/tasreg/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -130,7 +131,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { _sbss = .; *(.sbss) *(.scommon) diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile index 98acb4b77..a60495a59 100644 --- a/board/esd/voh405/Makefile +++ b/board/esd/voh405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,34 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/voh405/u-boot.lds b/board/esd/voh405/u-boot.lds index d70d37934..43f776579 100644 --- a/board/esd/voh405/u-boot.lds +++ b/board/esd/voh405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -138,7 +139,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 52534220a..22995b502 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -22,7 +22,6 @@ */ #include -#include #include #include #include @@ -113,11 +112,11 @@ int misc_init_f (void) int misc_init_r (void) { - unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); - unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); - unsigned short *lcd_contrast = + volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); + volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); + volatile unsigned short *lcd_contrast = (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4); - unsigned short *lcd_backlight = + volatile unsigned short *lcd_backlight = (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6); unsigned char *dst; ulong len = sizeof(fpgadata); @@ -181,37 +180,31 @@ int misc_init_r (void) /* * Reset FPGA via FPGA_INIT pin */ - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */ udelay(1000); /* wait 1ms */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */ + out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */ udelay(1000); /* wait 1ms */ /* * Reset external DUARTs */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ /* * Set NAND-FLASH GPIO signals to default */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE); - - /* - * Setup EEPROM write protection - */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); /* * Enable interrupts in exar duart mcr[3] */ - out_8(duart0_mcr, 0x08); - out_8(duart1_mcr, 0x08); + *duart0_mcr = 0x08; + *duart1_mcr = 0x08; /* * Init lcd interface and display logo @@ -253,23 +246,17 @@ int misc_init_r (void) /* * Set invert bit in small lcd controller */ - out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2), - in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01); + *(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01; /* * Set default contrast voltage on epson vga controller */ - out_be16(lcd_contrast, 0x4646); + *lcd_contrast = 0x4646; /* * Enable backlight */ - out_be16(lcd_backlight, 0xffff); - - /* - * Enable external I2C bus - */ - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON); + *lcd_backlight = 0xffff; return (0); } @@ -300,12 +287,17 @@ int checkboard (void) putc ('\n'); + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); + return 0; } /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; @@ -349,85 +341,16 @@ void ide_set_reset(int on) } #endif /* CONFIG_IDE_RESET */ -#if defined(CONFIG_RESET_PHY_R) -void reset_phy(void) -{ -#ifdef CONFIG_LXT971_NO_SLEEP - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); -#endif +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } } #endif - -#if defined(CFG_EEPROM_WREN) -/* Input: I2C address of EEPROM device to enable. - * -1: deliver current state - * 0: disable write - * 1: enable write - * Returns: -1: wrong device address - * 0: dis-/en- able done - * 0/1: current state if was -1. - */ -int eeprom_write_enable (unsigned dev_addr, int state) -{ - if (CFG_I2C_EEPROM_ADDR != dev_addr) { - return -1; - } else { - switch (state) { - case 1: - /* Enable write access, clear bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP); - state = 0; - break; - case 0: - /* Disable write access, set bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); - state = 0; - break; - default: - /* Read current status back. */ - state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP)); - break; - } - } - return state; -} - -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int query = argc == 1; - int state = 0; - - if (query) { - /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); - if (state < 0) { - puts ("Query of write access state failed.\n"); - } else { - printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); - state = 0; - } - } else { - if ('0' == argv[1][0]) { - /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); - } else { - /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); - } - if (state < 0) { - puts ("Setup of write access state failed.\n"); - } - } - - return state; -} - -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", - NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile index 86bd4461d..a11ee82aa 100644 --- a/board/esd/vom405/Makefile +++ b/board/esd/vom405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,37 +22,30 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a # Objects for Xilinx JTAG programming (CPLD) CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ ../common/xilinx_jtag/ports.o -COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/vom405/u-boot.lds b/board/esd/vom405/u-boot.lds index 21547ac27..f7a20d1da 100644 --- a/board/esd/vom405/u-boot.lds +++ b/board/esd/vom405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index af8efcff3..8be552e2e 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -129,7 +129,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile index 98acb4b77..a60495a59 100644 --- a/board/esd/wuh405/Makefile +++ b/board/esd/wuh405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,34 +22,25 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o \ - ../common/misc.o \ - ../common/esd405ep_nand.o \ - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o flash.o ../common/misc.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esd/wuh405/u-boot.lds b/board/esd/wuh405/u-boot.lds index 644174a46..95854f293 100644 --- a/board/esd/wuh405/u-boot.lds +++ b/board/esd/wuh405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -136,7 +137,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index 0590fc78f..5a1a3f3e8 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -169,6 +169,12 @@ int misc_init_r (void) out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ + /* + * Set NAND-FLASH GPIO signals to default + */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + /* * Enable interrupts in exar duart mcr[3] */ @@ -205,12 +211,42 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long val; mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } + +/* ------------------------------------------------------------------------- */ + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif diff --git a/board/esteem192e/Makefile b/board/esteem192e/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/esteem192e/Makefile +++ b/board/esteem192e/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/esteem192e/esteem192e.c b/board/esteem192e/esteem192e.c index f3c8662cd..3959eead2 100644 --- a/board/esteem192e/esteem192e.c +++ b/board/esteem192e/esteem192e.c @@ -101,7 +101,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/esteem192e/flash.c b/board/esteem192e/flash.c index d5eb2019b..5465deaf9 100644 --- a/board/esteem192e/flash.c +++ b/board/esteem192e/flash.c @@ -24,7 +24,7 @@ #include #include -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ #ifdef CONFIG_FLASH_16BIT #define FLASH_WORD_SIZE unsigned short @@ -38,101 +38,97 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ * Functions */ -ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info); - +ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); #ifndef CONFIG_FLASH_16BIT -static int write_word (flash_info_t * info, ulong dest, ulong data); +static int write_word (flash_info_t *info, ulong dest, ulong data); #else -static int write_short (flash_info_t * info, ulong dest, ushort data); +static int write_short (flash_info_t *info, ulong dest, ushort data); #endif /*int flash_write (uchar *, ulong, ulong); */ /*flash_info_t *addr2info (ulong); */ -static void flash_get_offsets (ulong base, flash_info_t * info); +static void flash_get_offsets (ulong base, flash_info_t *info); /*----------------------------------------------------------------------- */ unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i size_b0) { printf ("## ERROR: " "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1 << 20, size_b0, size_b0 << 20); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; return (0); } /* Remap FLASH according to real size */ memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801; /* (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */ + memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801; /* (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;*/ /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE, - &flash_info[0]); + size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE, + &flash_info[0]); flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); #if CFG_MONITOR_BASE >= CFG_FLASH_BASE /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = - CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = - (CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK); - /*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; */ + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = (CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK); + /*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V;*/ /* Re-do sizing to get full correct info */ - size_b1 = - flash_get_size ((volatile FLASH_WORD_SIZE - *) (CFG_FLASH_BASE + size_b0), - &flash_info[1]); + size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); #if CFG_MONITOR_BASE >= CFG_FLASH_BASE /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - - 1, &flash_info[1]); + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); #endif } else { - memctl->memc_br1 = 0; /* invalidate bank */ + memctl->memc_br1 = 0; /* invalidate bank */ flash_info[1].flash_id = FLASH_UNKNOWN; flash_info[1].sector_count = -1; @@ -146,112 +142,110 @@ unsigned long flash_init (void) /*----------------------------------------------------------------------- */ -static void flash_get_offsets (ulong base, flash_info_t * info) +static void flash_get_offsets (ulong base, flash_info_t *info) { int i; /* set up sector start adress table */ if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { #ifndef CONFIG_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x000E0000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x00060000; - } + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00008000; + info->start[3] = base + 0x0000C000; + info->start[4] = base + 0x00010000; + info->start[5] = base + 0x00014000; + info->start[6] = base + 0x00018000; + info->start[7] = base + 0x0001C000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x000E0000; } + } + else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } #else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00070000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000A000; + info->start[6] = base + 0x0000C000; + info->start[7] = base + 0x0000E000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00070000; } + } + else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } #endif } else { - /* set sector offsets for top boot block type */ + /* set sector offsets for top boot block type */ i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { #ifndef CONFIG_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00014000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x0001C000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; } + + } else { + + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } #else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - - } else { - - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000A000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x0000E000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; } + + } else { + + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } #endif } @@ -260,12 +254,12 @@ static void flash_get_offsets (ulong base, flash_info_t * info) /*----------------------------------------------------------------------- */ -void flash_print_info (flash_info_t * info) +void flash_print_info (flash_info_t *info) { int i; uchar *boottype; - uchar botboot[] = ", bottom boot sect)\n"; - uchar topboot[] = ", top boot sector)\n"; + uchar botboot[]=", bottom boot sect)\n"; + uchar topboot[]=", top boot sector)\n"; if (info->flash_id == FLASH_UNKNOWN) { printf ("missing or unknown FLASH type\n"); @@ -273,100 +267,73 @@ void flash_print_info (flash_info_t * info) } switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; } - if (info->flash_id & 0x0001) { - boottype = botboot; + if (info->flash_id & 0x0001 ) { + boottype = botboot; } else { - boottype = topboot; + boottype = topboot; } switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: - printf ("AM29LV400B (4 Mbit%s", boottype); - break; - case FLASH_AM400T: - printf ("AM29LV400T (4 Mbit%s", boottype); - break; - case FLASH_AM800B: - printf ("AM29LV800B (8 Mbit%s", boottype); - break; - case FLASH_AM800T: - printf ("AM29LV800T (8 Mbit%s", boottype); - break; - case FLASH_AM160B: - printf ("AM29LV160B (16 Mbit%s", boottype); - break; - case FLASH_AM160T: - printf ("AM29LV160T (16 Mbit%s", boottype); - break; - case FLASH_AM320B: - printf ("AM29LV320B (32 Mbit%s", boottype); - break; - case FLASH_AM320T: - printf ("AM29LV320T (32 Mbit%s", boottype); - break; - case FLASH_INTEL800B: - printf ("INTEL28F800B (8 Mbit%s", boottype); - break; - case FLASH_INTEL800T: - printf ("INTEL28F800T (8 Mbit%s", boottype); - break; - case FLASH_INTEL160B: - printf ("INTEL28F160B (16 Mbit%s", boottype); - break; - case FLASH_INTEL160T: - printf ("INTEL28F160T (16 Mbit%s", boottype); - break; - case FLASH_INTEL320B: - printf ("INTEL28F320B (32 Mbit%s", boottype); - break; - case FLASH_INTEL320T: - printf ("INTEL28F320T (32 Mbit%s", boottype); - break; + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit%s",boottype); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit%s",boottype); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit%s",boottype); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit%s",boottype); + break; + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit%s",boottype); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit%s",boottype); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit%s",boottype); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit%s",boottype); + break; + case FLASH_INTEL800B: printf ("INTEL28F800B (8 Mbit%s",boottype); + break; + case FLASH_INTEL800T: printf ("INTEL28F800T (8 Mbit%s",boottype); + break; + case FLASH_INTEL160B: printf ("INTEL28F160B (16 Mbit%s",boottype); + break; + case FLASH_INTEL160T: printf ("INTEL28F160T (16 Mbit%s",boottype); + break; + case FLASH_INTEL320B: printf ("INTEL28F320B (32 Mbit%s",boottype); + break; + case FLASH_INTEL320T: printf ("INTEL28F320T (32 Mbit%s",boottype); + break; -#if 0 /* enable when devices are available */ +#if 0 /* enable when devices are available */ - case FLASH_INTEL640B: - printf ("INTEL28F640B (64 Mbit%s", boottype); - break; - case FLASH_INTEL640T: - printf ("INTEL28F640T (64 Mbit%s", boottype); - break; + case FLASH_INTEL640B: printf ("INTEL28F640B (64 Mbit%s",boottype); + break; + case FLASH_INTEL640T: printf ("INTEL28F640T (64 Mbit%s",boottype); + break; #endif - default: - printf ("Unknown Chip Type\n"); - break; + default: printf ("Unknown Chip Type\n"); + break; } printf (" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { + for (i=0; isector_count; ++i) { if ((i % 5) == 0) printf ("\n "); printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); + info->start[i], + info->protect[i] ? " (RO)" : " " + ); } printf ("\n"); return; @@ -382,10 +349,10 @@ void flash_print_info (flash_info_t * info) /* * The following code cannot be run from FLASH! */ -ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) +ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) { short i; - ulong base = (ulong) addr; + ulong base = (ulong)addr; FLASH_WORD_SIZE value; /* Write auto select command: read Manufacturer ID */ @@ -400,7 +367,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) */ addr[0x0000] = 0x00900090; - if (addr[0x0000] != 0x00890089) { + if(addr[0x0000] != 0x00890089){ addr[0x0555] = 0x00AA00AA; addr[0x02AA] = 0x00550055; addr[0x0555] = 0x00900090; @@ -414,7 +381,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) addr[0x0000] = 0x0090; - if (addr[0x0000] != 0x0089) { + if(addr[0x0000] != 0x0089){ addr[0x0555] = 0x00AA; addr[0x02AA] = 0x0055; addr[0x0555] = 0x0090; @@ -442,11 +409,11 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; info->size = 0; - return (0); /* no or unknown flash */ + return (0); /* no or unknown flash */ } - value = addr[1]; /* device ID */ + value = addr[1]; /* device ID */ switch (value) { @@ -454,208 +421,206 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00100000; - break; /* => 1 MB */ + break; /* => 1 MB */ case (AMD_ID_LV400B & FLASH_ID_MASK): info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00100000; - break; /* => 1 MB */ + break; /* => 1 MB */ case (AMD_ID_LV800T & FLASH_ID_MASK): info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00200000; - break; /* => 2 MB */ + break; /* => 2 MB */ case (AMD_ID_LV800B & FLASH_ID_MASK): info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00200000; - break; /* => 2 MB */ + break; /* => 2 MB */ case (AMD_ID_LV160T & FLASH_ID_MASK): info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00400000; - break; /* => 4 MB */ + break; /* => 4 MB */ case (AMD_ID_LV160B & FLASH_ID_MASK): info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ + break; /* => 4 MB */ +#if 0 /* enable when device IDs are available */ case (AMD_ID_LV320T & FLASH_ID_MASK): info->flash_id += FLASH_AM320T; info->sector_count = 67; info->size = 0x00800000; - break; /* => 8 MB */ + break; /* => 8 MB */ case (AMD_ID_LV320B & FLASH_ID_MASK): info->flash_id += FLASH_AM320B; info->sector_count = 67; info->size = 0x00800000; - break; /* => 8 MB */ + break; /* => 8 MB */ #endif case (INTEL_ID_28F800B3T & FLASH_ID_MASK): info->flash_id += FLASH_INTEL800T; info->sector_count = 23; info->size = 0x00200000; - break; /* => 2 MB */ + break; /* => 2 MB */ case (INTEL_ID_28F800B3B & FLASH_ID_MASK): info->flash_id += FLASH_INTEL800B; info->sector_count = 23; info->size = 0x00200000; - break; /* => 2 MB */ + break; /* => 2 MB */ case (INTEL_ID_28F160B3T & FLASH_ID_MASK): info->flash_id += FLASH_INTEL160T; info->sector_count = 39; info->size = 0x00400000; - break; /* => 4 MB */ + break; /* => 4 MB */ case (INTEL_ID_28F160B3B & FLASH_ID_MASK): info->flash_id += FLASH_INTEL160B; info->sector_count = 39; info->size = 0x00400000; - break; /* => 4 MB */ + break; /* => 4 MB */ case (INTEL_ID_28F320B3T & FLASH_ID_MASK): info->flash_id += FLASH_INTEL320T; info->sector_count = 71; info->size = 0x00800000; - break; /* => 8 MB */ + break; /* => 8 MB */ case (INTEL_ID_28F320B3B & FLASH_ID_MASK): info->flash_id += FLASH_AM320B; info->sector_count = 71; info->size = 0x00800000; - break; /* => 8 MB */ + break; /* => 8 MB */ -#if 0 /* enable when devices are available */ +#if 0 /* enable when devices are available */ case (INTEL_ID_28F320B3T & FLASH_ID_MASK): info->flash_id += FLASH_INTEL320T; info->sector_count = 135; info->size = 0x01000000; - break; /* => 16 MB */ + break; /* => 16 MB */ case (INTEL_ID_28F320B3B & FLASH_ID_MASK): info->flash_id += FLASH_AM320B; info->sector_count = 135; info->size = 0x01000000; - break; /* => 16 MB */ + break; /* => 16 MB */ #endif default: info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ + return (0); /* => no or unknown flash */ } /* set up sector start adress table */ if (info->flash_id & FLASH_BTYPE) { - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { #ifndef CONFIG_FLASH_16BIT - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00008000; - info->start[3] = base + 0x0000C000; - info->start[4] = base + 0x00010000; - info->start[5] = base + 0x00014000; - info->start[6] = base + 0x00018000; - info->start[7] = base + 0x0001C000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x000E0000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00020000) - 0x00060000; - } + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00008000; + info->start[3] = base + 0x0000C000; + info->start[4] = base + 0x00010000; + info->start[5] = base + 0x00014000; + info->start[6] = base + 0x00018000; + info->start[7] = base + 0x0001C000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x000E0000; } + } + else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + } #else - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00002000; - info->start[2] = base + 0x00004000; - info->start[3] = base + 0x00006000; - info->start[4] = base + 0x00008000; - info->start[5] = base + 0x0000A000; - info->start[6] = base + 0x0000C000; - info->start[7] = base + 0x0000E000; - for (i = 8; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00070000; - } - } else { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = - base + (i * 0x00010000) - 0x00030000; - } + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00002000; + info->start[2] = base + 0x00004000; + info->start[3] = base + 0x00006000; + info->start[4] = base + 0x00008000; + info->start[5] = base + 0x0000A000; + info->start[6] = base + 0x0000C000; + info->start[7] = base + 0x0000E000; + for (i = 8; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00070000; } + } + else { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } #endif } else { - /* set sector offsets for top boot block type */ + /* set sector offsets for top boot block type */ i = info->sector_count - 1; - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { #ifndef CONFIG_FLASH_16BIT - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00014000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x0001C000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - - } else { - - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + info->start[i--] = base + info->size - 0x00014000; + info->start[i--] = base + info->size - 0x00018000; + info->start[i--] = base + info->size - 0x0001C000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; } + + } else { + + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + } #else - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - - } else { - - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000A000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x0000E000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; } + + } else { + + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } #endif } @@ -663,7 +628,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr = (volatile FLASH_WORD_SIZE *) (info->start[i]); + addr = (volatile FLASH_WORD_SIZE *)(info->start[i]); info->protect[i] = addr[2] & 1; } @@ -671,11 +636,11 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) * Prevent writes to uninitialized FLASH. */ if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) { - *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){ + *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ } else { - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ + *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ } } @@ -686,11 +651,10 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) /*----------------------------------------------------------------------- */ -int flash_erase (flash_info_t * info, int s_first, int s_last) +int flash_erase (flash_info_t *info, int s_first, int s_last) { - volatile FLASH_WORD_SIZE *addr = - (volatile FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); int flag, prot, sect, l_sect, barf; ulong start, now, last; int rcode = 0; @@ -706,20 +670,21 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) if ((info->flash_id == FLASH_UNKNOWN) || ((info->flash_id > FLASH_AMD_COMP) && - ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) { + ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){ printf ("Can't erase unknown flash type - aborted\n"); return 1; } prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { + for (sect=s_first; sect<=s_last; ++sect) { if (info->protect[sect]) { prot++; } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); } else { printf ("\n"); } @@ -727,111 +692,109 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) l_sect = -1; /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - if (info->flash_id < FLASH_AMD_COMP) { + flag = disable_interrupts(); + if(info->flash_id < FLASH_AMD_COMP) { #ifndef CONFIG_FLASH_16BIT - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; #else - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0080; + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; #endif - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); + addr[0] = (0x00300030 & FLASH_ID_MASK); + l_sect = sect; } + } - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]); - while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) != - (0x00800080 & FLASH_ID_MASK)) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } + start = get_timer (0); + last = start; + addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); + while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != + (0x00800080&FLASH_ID_MASK) ) + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } - DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { +DONE: + /* reset to read mode */ + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + } else { - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - barf = 0; + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + barf = 0; #ifndef CONFIG_FLASH_16BIT - addr = (vu_long *) (info->start[sect]); - addr[0] = 0x00200020; - addr[0] = 0x00D000D0; - while (!(addr[0] & 0x00800080)); /* wait for error or finish */ - if (addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if (barf) { - barf >>= 16; - } else { - barf = addr[0] & 0x0000003A; - } + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00200020; + addr[0] = 0x00D000D0; + while(!(addr[0] & 0x00800080)); /* wait for error or finish */ + if( addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if( barf ) { + barf >>=16; + } else { + barf = addr[0] & 0x0000003A; } -#else - addr = (vu_short *) (info->start[sect]); - addr[0] = 0x0020; - addr[0] = 0x00D0; - while (!(addr[0] & 0x0080)); /* wait for error or finish */ - if (addr[0] & 0x003A) /* check for error */ - barf = addr[0] & 0x003A; -#endif - if (barf) { - printf ("\nFlash error in sector at %lx\n", (unsigned long) addr); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if ((barf & 0x0030) == 0x0030) - printf ("Command Sequence error.\n"); - if ((barf & 0x0030) == 0x0020) - printf ("Block Erase error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - rcode = 1; - } else - printf ("."); - l_sect = sect; } - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - +#else + addr = (vu_short*)(info->start[sect]); + addr[0] = 0x0020; + addr[0] = 0x00D0; + while(!(addr[0] & 0x0080)); /* wait for error or finish */ + if( addr[0] & 0x003A) /* check for error */ + barf = addr[0] & 0x003A; +#endif + if(barf) { + printf("\nFlash error in sector at %lx\n",(unsigned long)addr); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if((barf & 0x0030) == 0x0030) + printf("Command Sequence error.\n"); + if((barf & 0x0030) == 0x0020) + printf("Block Erase error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + rcode = 1; + } else printf("."); + l_sect = sect; } + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ } + + } printf (" done\n"); return rcode; } @@ -846,7 +809,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) * 2 - Flash not erased */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { #ifndef CONFIG_FLASH_16BIT ulong cp, wp, data; @@ -867,19 +830,19 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) */ if ((l = addr - wp) != 0) { data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); + for (i=0, cp=wp; i 0; ++i) { + for (; i<4 && cnt>0; ++i) { data = (data << 8) | *src++; --cnt; ++cp; } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); } - if ((rc = write_word (info, wp, data)) != 0) { + if ((rc = write_word(info, wp, data)) != 0) { return (rc); } wp += 4; @@ -890,13 +853,13 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) */ while (cnt >= 4) { data = 0; - for (i = 0; i < 4; ++i) { + for (i=0; i<4; ++i) { data = (data << 8) | *src++; } - if ((rc = write_word (info, wp, data)) != 0) { + if ((rc = write_word(info, wp, data)) != 0) { return (rc); } - wp += 4; + wp += 4; cnt -= 4; } @@ -908,15 +871,15 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) * handle unaligned tail bytes */ data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { data = (data << 8) | *src++; --cnt; } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); } - return (write_word (info, wp, data)); + return (write_word(info, wp, data)); #else wp = (addr & ~1); /* get lower word aligned address */ @@ -928,7 +891,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) data = 0; data = (data << 8) | *src++; --cnt; - if ((rc = write_short (info, wp, data)) != 0) { + if ((rc = write_short(info, wp, data)) != 0) { return (rc); } wp += 2; @@ -940,7 +903,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) /* l = 0; used for debuging */ while (cnt >= 2) { data = 0; - for (i = 0; i < 2; ++i) { + for (i=0; i<2; ++i) { data = (data << 8) | *src++; } @@ -949,10 +912,10 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) l = 1; } used for debuging */ - if ((rc = write_short (info, wp, data)) != 0) { + if ((rc = write_short(info, wp, data)) != 0) { return (rc); } - wp += 2; + wp += 2; cnt -= 2; } @@ -964,15 +927,15 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) * handle unaligned tail bytes */ data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { data = (data << 8) | *src++; --cnt; } - for (; i < 2; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); + for (; i<2; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); } - return (write_short (info, wp, data)); + return (write_short(info, wp, data)); #endif @@ -985,151 +948,148 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) * 2 - Flash not erased */ #ifndef CONFIG_FLASH_16BIT -static int write_word (flash_info_t * info, ulong dest, ulong data) +static int write_word (flash_info_t *info, ulong dest, ulong data) { - vu_long *addr = (vu_long *) (info->start[0]); - ulong start, barf; + vu_long *addr = (vu_long*)(info->start[0]); + ulong start,barf; int flag; /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & data) != data) { + if ((*((vu_long *)dest) & data) != data) { return (2); } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + flag = disable_interrupts(); - if (info->flash_id > FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - } else { - /* intel stuff */ - *addr = 0x00400040; - } - *((vu_long *) dest) = data; + if(info->flash_id > FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + } else { + /* intel stuff */ + *addr = 0x00400040; + } + *((vu_long *)dest) = data; /* re-enable interrupts if necessary */ if (flag) - enable_interrupts (); + enable_interrupts(); /* data polling for D7 */ start = get_timer (0); - if (info->flash_id > FLASH_AMD_COMP) { + if(info->flash_id > FLASH_AMD_COMP) { - while ((*((vu_long *) dest) & 0x00800080) != - (data & 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); } - - } else { - - while (!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - - if (addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if (barf) { - barf >>= 16; - } else { - barf = addr[0] & 0x0000003A; - } - printf ("\nFlash write error at address %lx\n", (unsigned long) dest); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if (barf & 0x0010) - printf ("Programming error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - return (2); - } - - - } - - return (0); - } + } else { + + while(!(addr[0] & 0x00800080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + + if( addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if( barf ) { + barf >>=16; + } else { + barf = addr[0] & 0x0000003A; + } + printf("\nFlash write error at address %lx\n",(unsigned long)dest); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if(barf & 0x0010) printf("Programming error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + return(2); + } + + + } + + return (0); + +} + #else -static int write_short (flash_info_t * info, ulong dest, ushort data) +static int write_short (flash_info_t *info, ulong dest, ushort data) { - vu_short *addr = (vu_short *) (info->start[0]); - ulong start, barf; + vu_short *addr = (vu_short*)(info->start[0]); + ulong start,barf; int flag; /* Check if Flash is (sufficiently) erased */ - if ((*((vu_short *) dest) & data) != data) { + if ((*((vu_short *)dest) & data) != data) { return (2); } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + flag = disable_interrupts(); - if (info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - } else { - /* intel stuff */ - *addr = 0x00D0; - *addr = 0x0040; - } - *((vu_short *) dest) = data; + if(info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x00A0; + } else { + /* intel stuff */ + *addr = 0x00D0; + *addr = 0x0040; + } + *((vu_short *)dest) = data; /* re-enable interrupts if necessary */ if (flag) - enable_interrupts (); + enable_interrupts(); /* data polling for D7 */ start = get_timer (0); - if (info->flash_id < FLASH_AMD_COMP) { - /* AMD stuff */ - while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } + if(info->flash_id < FLASH_AMD_COMP) { + /* AMD stuff */ + while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); } - - } else { - /* intel stuff */ - while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) - return (1); - } - - if (addr[0] & 0x003A) { /* check for error */ - barf = addr[0] & 0x003A; - printf ("\nFlash write error at address %lx\n", - (unsigned long) dest); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if (barf & 0x0010) - printf ("Programming error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - return (2); - } - *addr = 0x00B0; - *addr = 0x0070; - while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) - return (1); - } - *addr = 0x00FF; } + + } else { + /* intel stuff */ + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + } + + if( addr[0] & 0x003A) { /* check for error */ + barf = addr[0] & 0x003A; + printf("\nFlash write error at address %lx\n",(unsigned long)dest); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if(barf & 0x0010) printf("Programming error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + return(2); + } + *addr = 0x00B0; + *addr = 0x0070; + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + } + + *addr = 0x00FF; + + } + return (0); + } + #endif -/*-----------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------- + */ diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index acaf4e34f..4c541bf5c 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/etin/debris/Makefile b/board/etin/debris/Makefile index fdf773691..305a1bfeb 100644 --- a/board/etin/debris/Makefile +++ b/board/etin/debris/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o phantom.o +OBJS = $(BOARD).o flash.o phantom.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c index 763760fd2..08ed635f3 100644 --- a/board/etin/debris/debris.c +++ b/board/etin/debris/debris.c @@ -43,7 +43,7 @@ int checkboard (void) return 0; } -#if 0 /* NOT USED */ +#if 0 /* NOT USED */ int checkflash (void) { /* TODO: XXX XXX XXX */ @@ -53,7 +53,7 @@ int checkflash (void) } #endif -phys_size_t initdram (int board_type) +long int initdram (int board_type) { int m, row, col, bank, i; unsigned long start, end; diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c index 263da6b7c..0b81fc0c3 100644 --- a/board/etin/debris/phantom.c +++ b/board/etin/debris/phantom.c @@ -18,7 +18,7 @@ #include #include -#if defined(CONFIG_CMD_DATE) +#if (CONFIG_COMMANDS & CFG_CMD_DATE) #define RTC_BASE (CFG_NVRAM_BASE_ADDR + 0x7fff8) @@ -182,7 +182,7 @@ static int get_century_flag(void) return flag; } -int rtc_get( struct rtc_time *tmp) +void rtc_get( struct rtc_time *tmp) { if (phantom_flag < 0) phantom_flag = get_phantom_flag(); @@ -250,8 +250,6 @@ int rtc_get( struct rtc_time *tmp) tmp->tm_yday = 0; tmp->tm_isdst= 0; } - - return 0; } void rtc_set( struct rtc_time *tmp ) diff --git a/board/etin/debris/speed.h b/board/etin/debris/speed.h index 3f32a143c..b66393bec 100644 --- a/board/etin/debris/speed.h +++ b/board/etin/debris/speed.h @@ -28,10 +28,10 @@ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 * * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock + * GCLK CPU clock * SPEED_TMR2_PS prescaler */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ /*----------------------------------------------------------------------- * Timer value for PIT diff --git a/board/etin/debris/u-boot.lds b/board/etin/debris/u-boot.lds new file mode 100644 index 000000000..c742bcd24 --- /dev/null +++ b/board/etin/debris/u-boot.lds @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/etin/kvme080/Makefile b/board/etin/kvme080/Makefile index 18b735061..303ccfaf3 100644 --- a/board/etin/kvme080/Makefile +++ b/board/etin/kvme080/Makefile @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o multiverse.o +OBJS = $(BOARD).o multiverse.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c index bfd6854c5..de62fa097 100644 --- a/board/etin/kvme080/kvme080.c +++ b/board/etin/kvme080/kvme080.c @@ -93,7 +93,7 @@ unsigned long setdram(int m, int row, int col, int bank) return (1 << (col + row + 3) ) * bank * m; } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { unsigned int msr; long int size = 0; diff --git a/board/etin/kvme080/u-boot.lds b/board/etin/kvme080/u-boot.lds new file mode 100644 index 000000000..dda368763 --- /dev/null +++ b/board/etin/kvme080/u-boot.lds @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2001-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/etx094/Makefile b/board/etx094/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/etx094/Makefile +++ b/board/etx094/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c index 7806519e3..eb58b5d52 100644 --- a/board/etx094/etx094.c +++ b/board/etx094/etx094.c @@ -125,7 +125,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds index 5313bd40a..c50db8f8c 100644 --- a/board/etx094/u-boot.lds +++ b/board/etx094/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -130,7 +131,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/etx094/u-boot.lds.debug b/board/etx094/u-boot.lds.debug index 06115ead8..e4d8b1091 100644 --- a/board/etx094/u-boot.lds.debug +++ b/board/etx094/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/evb4510/Makefile b/board/evb4510/Makefile index 3ab1aa038..10850a95e 100644 --- a/board/evb4510/Makefile +++ b/board/evb4510/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := evb4510.o flash.o +OBJS := evb4510.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/evb4510/u-boot.lds b/board/evb4510/u-boot.lds index b3c2bf950..5b70a40aa 100644 --- a/board/evb4510/u-boot.lds +++ b/board/evb4510/u-boot.lds @@ -51,7 +51,7 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/board/evb64260/Makefile b/board/evb64260/Makefile index aa39bafab..c493d6cf9 100644 --- a/board/evb64260/Makefile +++ b/board/evb64260/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2001 # Josh Huber , Mission Critical Linux, Inc. # @@ -26,25 +23,22 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a SOBJS = misc.o -COBJS = $(BOARD).o flash.o serial.o memory.o pci.o \ +OBJS = $(BOARD).o flash.o serial.o memory.o pci.o \ eth.o eth_addrtbl.o mpsc.o i2c.o \ sdram_init.o zuma_pbb.o intel_flash.o zuma_pbb_mbox.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt index 290aed90a..391d49a11 100644 --- a/board/evb64260/bootseq.txt +++ b/board/evb64260/bootseq.txt @@ -56,7 +56,7 @@ in_flash: setup stack pointer (r1) setup GOT call cpu_init_f - debug leds + debug leds board_init_f: (common/board.c) board_early_init_f: remap gt regs? @@ -74,7 +74,7 @@ in_flash: dram_size() setup PCI slave memory mappings setup SCS - setup monitor + setup monitor alloc board info struct init bd struct relocate_code: (cpu/mpc7xxx/start.S) diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index fa5b6d4a9..eafa48bc6 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -31,7 +31,7 @@ Skeleton NIC driver for Etherboot #include "eth.h" #include "eth_addrtbl.h" -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) #define GT6426x_ETH_BUF_SIZE 1536 @@ -163,7 +163,7 @@ gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr) int eth_len=0; char *eth_data; - eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)]; + eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)]; INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1)); @@ -252,7 +252,7 @@ gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s) #ifdef DEBUG unsigned int old_command_stat,old_psr; #endif - eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn]; + eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn]; /* wait for tx to be ready */ INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1)); @@ -529,7 +529,7 @@ gt6426x_eth_probe(void *v, bd_t *bis) #endif /* 31 28 27 24 23 20 19 16 - * 0000 0000 0000 0000 [0004] + * 0000 0000 0000 0000 [0004] * 15 12 11 8 7 4 3 0 * 1000 1101 0000 0000 [4d00] * 20 - 0=MII 1=RMII @@ -797,11 +797,11 @@ gt6426x_eth_initialize(bd_t *bis) eth_register(dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register(dev->name, gt6426x_miiphy_read, gt6426x_miiphy_write); #endif } } -#endif +#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */ diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c index 3b338c72e..98ac7f63d 100644 --- a/board/evb64260/mpsc.c +++ b/board/evb64260/mpsc.c @@ -259,7 +259,7 @@ char mpsc_getchar (void) int mpsc_test_char(void) { - volatile unsigned int *p = &rx_desc_base[rx_desc_index*8]; + volatile unsigned int *p=&rx_desc_base[rx_desc_index*8]; INVALIDATE_DCACHE(&p[1], &p[2]); @@ -309,9 +309,9 @@ mpsc_init(int baud) /* COMM_MPSC CONFIG */ #ifdef SOFTWARE_CACHE_MANAGEMENT - galmpsc_set_snoop(CHANNEL, 0); /* disable snoop */ + galmpsc_set_snoop(CHANNEL, 0); /* disable snoop */ #else - galmpsc_set_snoop(CHANNEL, 1); /* enable snoop */ + galmpsc_set_snoop(CHANNEL, 1); /* enable snoop */ #endif return 0; diff --git a/board/evb64260/mpsc.h b/board/evb64260/mpsc.h index c71258ca4..54b642a83 100644 --- a/board/evb64260/mpsc.h +++ b/board/evb64260/mpsc.h @@ -55,9 +55,9 @@ extern int (*mpsc_putchar)(char ch); #define TX_STOP 0x00010000 #define RX_ENABLE 0x00000080 -#define SDMA_RX_ABORT (1 << 15) -#define SDMA_TX_ABORT (1 << 31) -#define MPSC_TX_ABORT (1 << 7) +#define SDMA_RX_ABORT (1 << 15) +#define SDMA_TX_ABORT (1 << 31) +#define MPSC_TX_ABORT (1 << 7) #define MPSC_RX_ABORT (1 << 23) #define MPSC_ENTER_HUNT (1 << 31) diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c index 9ae446544..fae6d1090 100644 --- a/board/evb64260/sdram_init.c +++ b/board/evb64260/sdram_init.c @@ -524,7 +524,7 @@ static long int dram_size (long int *base, long int maxsize) /* U-Boot interface function to SDRAM init - this is where all the * controlling logic happens */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong checkbank[4] = {[0 ... 3] = 0 }; int bank_no; diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c index f1bcab3f0..191445c69 100644 --- a/board/evb64260/serial.c +++ b/board/evb64260/serial.c @@ -153,7 +153,7 @@ serial_puts (const char *s) } } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) void kgdb_serial_init(void) { @@ -182,4 +182,4 @@ kgdb_interruptible (int yes) { return; } -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds index 1a95755ab..d89eb6cff 100644 --- a/board/evb64260/u-boot.lds +++ b/board/evb64260/u-boot.lds @@ -26,6 +26,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -37,11 +38,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -125,7 +126,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c index 296e4619c..d64025afd 100644 --- a/board/evb64260/zuma_pbb.c +++ b/board/evb64260/zuma_pbb.c @@ -1,7 +1,7 @@ #include #include -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) #include #endif @@ -166,7 +166,7 @@ void zuma_init_pbb (void) } -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) static int last_cmd = 4; /* write increment */ static int last_size = 64; @@ -217,4 +217,4 @@ U_BOOT_CMD( " - init zuma mbox\n" ); -#endif +#endif /* CFG_CMD_BSP */ diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c index 6f5df6e80..2b9a469f8 100644 --- a/board/evb64260/zuma_pbb_mbox.c +++ b/board/evb64260/zuma_pbb_mbox.c @@ -148,7 +148,7 @@ zuma_mbox_setenv(void) } /** - * zuma_mbox_init: + * zuma_mbox_init: */ int zuma_mbox_init(void) diff --git a/board/exbitgen/Makefile b/board/exbitgen/Makefile index 4f752a86b..34bd4b209 100644 --- a/board/exbitgen/Makefile +++ b/board/exbitgen/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,30 +23,27 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index dc07d3df0..39a97225f 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -1,10 +1,8 @@ -#include #include #include +#include #include "exbitgen.h" -void sdram_init(void); - /* ************************************************************************ */ int board_early_init_f (void) /* ------------------------------------------------------------------------ -- @@ -71,7 +69,7 @@ int checkboard (void) } /* ************************************************************************ */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) /* ------------------------------------------------------------------------ -- * Purpose : Determines size of mounted DRAM. * Remarks : Size is determined by reading SDRAM configuration registers as @@ -85,13 +83,6 @@ phys_size_t initdram (int board_type) ulong bank_size; ulong tmp; - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in cpu/ppc4xx - */ - sdram_init(); - tot_size = 0; mtdcr (memcfga, mem_mb0cf); diff --git a/board/exbitgen/exbitgen.h b/board/exbitgen/exbitgen.h index dceaf6dbc..058ad48ea 100644 --- a/board/exbitgen/exbitgen.h +++ b/board/exbitgen/exbitgen.h @@ -25,15 +25,15 @@ #define CPLD_BASE 0x10000000 /* t.b.m. */ -#define DEBUG_LEDS_ADDR CPLD_BASE + 0x01 -#define HW_ID_ADDR CPLD_BASE + 0x02 -#define DIP_SWITCH_ADDR CPLD_BASE + 0x04 -#define PHY_CTRL_ADDR CPLD_BASE + 0x05 -#define SPI_OUT_ADDR CPLD_BASE + 0x07 -#define SPI_IN_ADDR CPLD_BASE + 0x08 -#define MDIO_OUT_ADDR CPLD_BASE + 0x09 -#define MDIO_IN_ADDR CPLD_BASE + 0x0A -#define MISC_OUT_ADDR CPLD_BASE + 0x0B +#define DEBUG_LEDS_ADDR CPLD_BASE + 0x01 +#define HW_ID_ADDR CPLD_BASE + 0x02 +#define DIP_SWITCH_ADDR CPLD_BASE + 0x04 +#define PHY_CTRL_ADDR CPLD_BASE + 0x05 +#define SPI_OUT_ADDR CPLD_BASE + 0x07 +#define SPI_IN_ADDR CPLD_BASE + 0x08 +#define MDIO_OUT_ADDR CPLD_BASE + 0x09 +#define MDIO_IN_ADDR CPLD_BASE + 0x0A +#define MISC_OUT_ADDR CPLD_BASE + 0x0B /* Addresses used on I2C bus */ #define LM75_CHIP_ADDR 0x9C diff --git a/board/exbitgen/flash.c b/board/exbitgen/flash.c index 4dd538287..ae88994b2 100644 --- a/board/exbitgen/flash.c +++ b/board/exbitgen/flash.c @@ -28,10 +28,10 @@ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com */ -#include #include #include #include +#include flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S index 71aefb97c..0e6cd04ba 100644 --- a/board/exbitgen/init.S +++ b/board/exbitgen/init.S @@ -184,11 +184,11 @@ ext_bus_cntlr_init: ori r3, r3, HW_ID_ADDR@l lbz r3,0x0000(r3) cmpi 0, r3, 1 /* if (HW_ID==1) */ - beq setup_h2evalboard /* then jump */ + beq setup_h2evalboard /* then jump */ cmpi 0, r3, 2 /* if (HW_ID==2) */ - beq setup_genieboard /* then jump */ + beq setup_genieboard /* then jump */ cmpi 0, r3, 3 /* if (HW_ID==3) */ - beq setup_genieboard /* then jump */ + beq setup_genieboard /* then jump */ setup_genieboard: /*--------------------------------------------------------------- */ diff --git a/board/exbitgen/u-boot.lds b/board/exbitgen/u-boot.lds index e4faa446e..d5dea8238 100644 --- a/board/exbitgen/u-boot.lds +++ b/board/exbitgen/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -65,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -138,7 +139,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/ezkit533/Makefile b/board/ezkit533/Makefile new file mode 100644 index 000000000..c9b3c9280 --- /dev/null +++ b/board/ezkit533/Makefile @@ -0,0 +1,44 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ezkit533.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/ezkit533/config.mk b/board/ezkit533/config.mk new file mode 100644 index 000000000..36c9f997d --- /dev/null +++ b/board/ezkit533/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x01FC0000 +PLATFORM_CPPFLAGS += -I$(TOPDIR) diff --git a/board/ezkit533/ezkit533.c b/board/ezkit533/ezkit533.c new file mode 100644 index 000000000..8d6c8de70 --- /dev/null +++ b/board/ezkit533/ezkit533.c @@ -0,0 +1,72 @@ +/* + * U-boot - ezkit533.c + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_MISC_INIT_R) +#include "psd4256.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); + printf("Board: ADI BF533 EZ-Kit Lite board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + printf(" Richard Klingler \n"); + return 0; +} + +long int initdram(int board_type) +{ +#ifdef DEBUG + int brate; + char *tmp = getenv("baudrate"); + brate = simple_strtoul(tmp, NULL, 16); + printf("Serial Port initialized with Baud rate = %x\n",brate); + printf("SDRAM attributes:\n"); + printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" + "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", + 3, 3, 6, 2, 3); + printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); + printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20); +#endif + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; + return CFG_MAX_RAM_SIZE; +} + +#if defined(CONFIG_MISC_INIT_R) +/* miscellaneous platform dependent initialisations */ +int misc_init_r(void) +{ + /* Set direction bits for Video en/decoder reset as output */ + *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST; + /* Deactivate Video en/decoder reset lines */ + *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST; +} +#endif diff --git a/board/ezkit533/flash-defines.h b/board/ezkit533/flash-defines.h new file mode 100644 index 000000000..8f9dff5de --- /dev/null +++ b/board/ezkit533/flash-defines.h @@ -0,0 +1,130 @@ +/* + * U-boot - flash-defines.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FLASHDEFINES_H__ +#define __FLASHDEFINES_H__ + +#include + +#define V_ULONG(a) (*(volatile unsigned long *)( a )) +#define V_BYTE(a) (*(volatile unsigned char *)( a )) +#define TRUE 0x1 +#define FALSE 0x0 +#define BUFFER_SIZE 0x80000 +#define NO_COMMAND 0 +#define GET_CODES 1 +#define RESET 2 +#define WRITE 3 +#define FILL 4 +#define ERASE_ALL 5 +#define ERASE_SECT 6 +#define READ 7 +#define GET_SECTNUM 8 +#define FLASH_START_L 0x0000 +#define FLASH_START_H 0x2000 +#define FLASH_TOT_SECT 40 +#define FLASH_SIZE 0x220000 +#define FLASH_MAN_ST 2 +#define CFG_FLASH0_BASE 0x20000000 +#define RESET_VAL 0xF0 + + +asm("#define FLASH_START_L 0x0000"); +asm("#define FLASH_START_H 0x2000"); + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +int get_codes(void); +int poll_toggle_bit(long lOffset); +void reset_flash(void); +int erase_flash(void); +int erase_block_flash(int,unsigned long); +void unlock_flash(long lOffset); +int write_data(long lStart, long lCount, long lStride, int *pnData); +int FillData(long lStart, long lCount, long lStride, int *pnData); +int read_data(long lStart, long lCount, long lStride, int *pnData); +int read_flash(long nOffset, int *pnValue); +int write_flash(long nOffset, int nValue); +void get_sector_number(long lOffset, int *pnSector); +int GetSectorProtectionStatus(flash_info_t * info, int nSector); +int GetOffset(int nBlock); +int AFP_NumSectors = 40; +long AFP_SectorSize1 = 0x10000; +int AFP_SectorSize2 = 0x4000; + +#define WRITESEQ1 0x0AAA +#define WRITESEQ2 0x0554 +#define WRITESEQ3 0x0AAA +#define WRITESEQ4 0x0AAA +#define WRITESEQ5 0x0554 +#define WRITESEQ6 0x0AAA +#define WRITEDATA1 0xaa +#define WRITEDATA2 0x55 +#define WRITEDATA3 0x80 +#define WRITEDATA4 0xaa +#define WRITEDATA5 0x55 +#define WRITEDATA6 0x10 +#define PriFlashABegin 0 +#define SecFlashABegin 32 +#define SecFlashBBegin 36 +#define PriFlashAOff 0x0 +#define PriFlashBOff 0x100000 +#define SecFlashAOff 0x200000 +#define SecFlashBOff 0x280000 +#define INVALIDLOCNSTART 0x20270000 +#define INVALIDLOCNEND 0x20280000 +#define BlockEraseVal 0x30 +#define UNLOCKDATA1 0xaa +#define UNLOCKDATA2 0x55 +#define UNLOCKDATA3 0xa0 +#define GETCODEDATA1 0xaa +#define GETCODEDATA2 0x55 +#define GETCODEDATA3 0x90 +#define SecFlashASec1Off 0x200000 +#define SecFlashASec2Off 0x204000 +#define SecFlashASec3Off 0x206000 +#define SecFlashASec4Off 0x208000 +#define SecFlashAEndOff 0x210000 +#define SecFlashBSec1Off 0x280000 +#define SecFlashBSec2Off 0x284000 +#define SecFlashBSec3Off 0x286000 +#define SecFlashBSec4Off 0x288000 +#define SecFlashBEndOff 0x290000 + +#define SECT32 32 +#define SECT33 33 +#define SECT34 34 +#define SECT35 35 +#define SECT36 36 +#define SECT37 37 +#define SECT38 38 +#define SECT39 39 + +#define FLASH_SUCCESS 0 +#define FLASH_FAIL -1 + +#endif diff --git a/board/ezkit533/flash.c b/board/ezkit533/flash.c new file mode 100644 index 000000000..b0a0796b8 --- /dev/null +++ b/board/ezkit533/flash.c @@ -0,0 +1,476 @@ +/* + * U-boot - flash.c Flash driver for PSD4256GV + * + * Copyright (c) 2005 blackfin.uclinux.org + * This file is based on BF533EzFlash.c originally written by Analog Devices, Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "flash-defines.h" + +void flash_reset(void) +{ + reset_flash(); +} + +unsigned long flash_get_size(ulong baseaddr, flash_info_t * info, + int bank_flag) +{ + int id = 0, i = 0; + static int FlagDev = 1; + + id = get_codes(); + if(FlagDev) { +#ifdef DEBUG + printf("Device ID of the Flash is %x\n", id); +#endif + FlagDev = 0; + } + info->flash_id = id; + + switch (bank_flag) { + case 0: + for (i = PriFlashABegin; i < SecFlashABegin; i++) + info->start[i] = (baseaddr + (i * AFP_SectorSize1)); + info->size = 0x200000; + info->sector_count = 32; + break; + case 1: + info->start[0] = baseaddr + SecFlashASec1Off; + info->start[1] = baseaddr + SecFlashASec2Off; + info->start[2] = baseaddr + SecFlashASec3Off; + info->start[3] = baseaddr + SecFlashASec4Off; + info->size = 0x10000; + info->sector_count = 4; + break; + case 2: + info->start[0] = baseaddr + SecFlashBSec1Off; + info->start[1] = baseaddr + SecFlashBSec2Off; + info->start[2] = baseaddr + SecFlashBSec3Off; + info->start[3] = baseaddr + SecFlashBSec4Off; + info->size = 0x10000; + info->sector_count = 4; + break; + } + return (info->size); +} + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1, size_b2; + int i; + + size_b0 = size_b1 = size_b2 = 0; +#ifdef DEBUG + printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE); + printf("Memory Map for the Flash\n"); + printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n"); + printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n"); + printf("0x20200000 - 0x2020FFFF Flash A Secondary (64KB)\n"); + printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n"); + printf("Please type command flinfo for information on Sectors \n"); +#endif + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0); + size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1); + size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2); + + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + (void)flash_protect(FLAG_PROTECT_SET,CFG_FLASH0_BASE,(flash_info[0].start[2] - 1),&flash_info[0]); + + return (size_b0 + size_b1 + size_b2); +} + +void flash_print_info(flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id) { + case FLASH_PSD4256GV: + printf("ST Microelectronics "); + break; + default: + printf("Unknown Vendor "); + break; + } + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf("\n"); + return; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + int cnt = 0,i; + int prot,sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + else + printf ("\n"); + + cnt = s_last - s_first + 1; + + if (cnt == FLASH_TOT_SECT) { + printf("Erasing flash, Please Wait \n"); + if(erase_flash() < 0) { + printf("Erasing flash failed \n"); + return FLASH_FAIL; + } + } else { + printf("Erasing Flash locations, Please Wait\n"); + for (i = s_first; i <= s_last; i++) { + if (info->protect[i] == 0) { /* not protected */ + if(erase_block_flash(i, info->start[i]) < 0) { + printf("Error Sector erasing \n"); + return FLASH_FAIL; + } + } + } + } + return FLASH_SUCCESS; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int ret; + + ret = write_data(addr, cnt, 1, (int *) src); + if(ret == FLASH_FAIL) + return ERR_NOT_ERASED; + return FLASH_SUCCESS; +} + + +int write_data(long lStart, long lCount, long lStride, int *pnData) +{ + long i = 0; + int j = 0; + unsigned long ulOffset = lStart - CFG_FLASH_BASE; + int d; + int iShift = 0; + int iNumWords = 2; + int nLeftover = lCount % 4; + int nSector = 0; + + for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { + for (iShift = 0, j = 0; (j < iNumWords); + j++, ulOffset += (lStride * 2)) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) { + printf("Invalid locations, Try writing to another location \n"); + return FLASH_FAIL; + } + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset,&d); + if(d != 0xffff) { + printf("Flash not erased at offset 0x%x Please erase to reprogram \n",ulOffset); + return FLASH_FAIL; + } + unlock_flash(ulOffset); + if(write_flash(ulOffset, (pnData[i] >> iShift)) < 0) { + printf("Error programming the flash \n"); + return FLASH_FAIL; + } + iShift += 16; + } + } + if (nLeftover > 0) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset,&d); + if(d != 0xffff) { + printf("Flash already programmed. Please erase to reprogram \n"); + printf("uloffset = 0x%x \t d = 0x%x\n",ulOffset,d); + return FLASH_FAIL; + } + unlock_flash(ulOffset); + if(write_flash(ulOffset, pnData[i]) < 0) { + printf("Error programming the flash \n"); + return FLASH_FAIL; + } + } + return FLASH_SUCCESS; +} + +int read_data(long ulStart, long lCount, long lStride, int *pnData) +{ + long i = 0; + int j = 0; + long ulOffset = ulStart; + int iShift = 0; + int iNumWords = 2; + int nLeftover = lCount % 4; + int nHi, nLow; + int nSector = 0; + + for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) { + for (iShift = 0, j = 0; j < iNumWords; j += 2) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset, &nLow); + ulOffset += (lStride * 2); + read_flash(ulOffset, &nHi); + ulOffset += (lStride * 2); + pnData[i] = (nHi << 16) | nLow; + } + } + if (nLeftover > 0) { + if ((ulOffset >= INVALIDLOCNSTART) + && (ulOffset < INVALIDLOCNEND)) + return FLASH_FAIL; + + get_sector_number(ulOffset, &nSector); + read_flash(ulOffset, &pnData[i]); + } + return FLASH_SUCCESS; +} + +int write_flash(long nOffset, int nValue) +{ + long addr; + + addr = (CFG_FLASH_BASE + nOffset); + asm("ssync;"); + *(unsigned volatile short *) addr = nValue; + asm("ssync;"); + if(poll_toggle_bit(nOffset) < 0) + return FLASH_FAIL; + return FLASH_SUCCESS; +} + +int read_flash(long nOffset, int *pnValue) +{ + int nValue = 0x0; + long addr = (CFG_FLASH_BASE + nOffset); + + if (nOffset != 0x2) + reset_flash(); + asm("ssync;"); + nValue = *(volatile unsigned short *) addr; + asm("ssync;"); + *pnValue = nValue; + return TRUE; +} + +int poll_toggle_bit(long lOffset) +{ + unsigned int u1,u2; + unsigned long timeout = 0xFFFFFFFF; + volatile unsigned long *FB = (volatile unsigned long *)(0x20000000 + lOffset); + while(1) { + if(timeout < 0) + break; + u1 = *(volatile unsigned short *)FB; + u2 = *(volatile unsigned short *)FB; + if((u1 & 0x0040) == (u2 & 0x0040)) + return FLASH_SUCCESS; + if((u2 & 0x0020) == 0x0000) + continue; + u1 = *(volatile unsigned short *)FB; + if((u2 & 0x0040) == (u1 & 0x0040)) + return FLASH_SUCCESS; + else { + reset_flash(); + return FLASH_FAIL; + } + timeout--; + } + printf("Time out occured \n"); + if(timeout <0) return FLASH_FAIL; +} + +void reset_flash(void) +{ + write_flash(WRITESEQ1, RESET_VAL); + /* Wait for 10 micro seconds */ + udelay(10); +} + +int erase_flash(void) +{ + write_flash(WRITESEQ1, WRITEDATA1); + write_flash(WRITESEQ2, WRITEDATA2); + write_flash(WRITESEQ3, WRITEDATA3); + write_flash(WRITESEQ4, WRITEDATA4); + write_flash(WRITESEQ5, WRITEDATA5); + write_flash(WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(0x0000) < 0) + return FLASH_FAIL; + + write_flash(SecFlashAOff + WRITESEQ1, WRITEDATA1); + write_flash(SecFlashAOff + WRITESEQ2, WRITEDATA2); + write_flash(SecFlashAOff + WRITESEQ3, WRITEDATA3); + write_flash(SecFlashAOff + WRITESEQ4, WRITEDATA4); + write_flash(SecFlashAOff + WRITESEQ5, WRITEDATA5); + write_flash(SecFlashAOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(SecFlashASec1Off) < 0) + return FLASH_FAIL; + + write_flash(PriFlashBOff + WRITESEQ1, WRITEDATA1); + write_flash(PriFlashBOff + WRITESEQ2, WRITEDATA2); + write_flash(PriFlashBOff + WRITESEQ3, WRITEDATA3); + write_flash(PriFlashBOff + WRITESEQ4, WRITEDATA4); + write_flash(PriFlashBOff + WRITESEQ5, WRITEDATA5); + write_flash(PriFlashBOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(PriFlashBOff) <0) + return FLASH_FAIL; + + write_flash(SecFlashBOff + WRITESEQ1, WRITEDATA1); + write_flash(SecFlashBOff + WRITESEQ2, WRITEDATA2); + write_flash(SecFlashBOff + WRITESEQ3, WRITEDATA3); + write_flash(SecFlashBOff + WRITESEQ4, WRITEDATA4); + write_flash(SecFlashBOff + WRITESEQ5, WRITEDATA5); + write_flash(SecFlashBOff + WRITESEQ6, WRITEDATA6); + + if(poll_toggle_bit(SecFlashBOff) < 0) + return FLASH_FAIL; + + return FLASH_SUCCESS; +} + +int erase_block_flash(int nBlock, unsigned long address) +{ + long ulSectorOff = 0x0; + + if ((nBlock < 0) || (nBlock > AFP_NumSectors)) + return FALSE; + + ulSectorOff = (address - CFG_FLASH_BASE); + + write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1); + write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2); + write_flash((WRITESEQ3 | ulSectorOff), WRITEDATA3); + write_flash((WRITESEQ4 | ulSectorOff), WRITEDATA4); + write_flash((WRITESEQ5 | ulSectorOff), WRITEDATA5); + + write_flash(ulSectorOff, BlockEraseVal); + + if(poll_toggle_bit(ulSectorOff) < 0) + return FLASH_FAIL; + + return FLASH_SUCCESS; +} + +void unlock_flash(long ulOffset) +{ + unsigned long ulOffsetAddr = ulOffset; + ulOffsetAddr &= 0xFFFF0000; + + write_flash((WRITESEQ1 | ulOffsetAddr), UNLOCKDATA1); + write_flash((WRITESEQ2 | ulOffsetAddr), UNLOCKDATA2); + write_flash((WRITESEQ3 | ulOffsetAddr), UNLOCKDATA3); +} + +int get_codes() +{ + int dev_id = 0; + + write_flash(WRITESEQ1, GETCODEDATA1); + write_flash(WRITESEQ2, GETCODEDATA2); + write_flash(WRITESEQ3, GETCODEDATA3); + + read_flash(0x0002, &dev_id); + dev_id &= 0x00FF; + + reset_flash(); + + return dev_id; +} + +void get_sector_number(long ulOffset, int *pnSector) +{ + int nSector = 0; + + if (ulOffset >= SecFlashAOff) { + if ((ulOffset < SecFlashASec1Off) + && (ulOffset < SecFlashASec2Off)) { + nSector = SECT32; + } else if ((ulOffset >= SecFlashASec2Off) + && (ulOffset < SecFlashASec3Off)) { + nSector = SECT33; + } else if ((ulOffset >= SecFlashASec3Off) + && (ulOffset < SecFlashASec4Off)) { + nSector = SECT34; + } else if ((ulOffset >= SecFlashASec4Off) + && (ulOffset < SecFlashAEndOff)) { + nSector = SECT35; + } + } else if (ulOffset >= SecFlashBOff) { + if ((ulOffset < SecFlashBSec1Off) + && (ulOffset < SecFlashBSec2Off)) { + nSector = SECT36; + } + if ((ulOffset < SecFlashBSec2Off) + && (ulOffset < SecFlashBSec3Off)) { + nSector = SECT37; + } + if ((ulOffset < SecFlashBSec3Off) + && (ulOffset < SecFlashBSec4Off)) { + nSector = SECT38; + } + if ((ulOffset < SecFlashBSec4Off) + && (ulOffset < SecFlashBEndOff)) { + nSector = SECT39; + } + } else if ((ulOffset >= PriFlashAOff) && (ulOffset < SecFlashAOff)) { + nSector = ulOffset & 0xffff0000; + nSector = ulOffset >> 16; + nSector = nSector & 0x000ff; + } + + if ((nSector >= 0) && (nSector < AFP_NumSectors)) { + *pnSector = nSector; + } +} diff --git a/board/ezkit533/psd4256.h b/board/ezkit533/psd4256.h new file mode 100644 index 000000000..01f656601 --- /dev/null +++ b/board/ezkit533/psd4256.h @@ -0,0 +1,67 @@ +/* + * U-boot - psd4256.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Flash A/B Port A configuration registers. + * Addresses are offset values to CFG_FLASH1_BASE + * for Flash A and CFG_FLASH2_BASE for Flash B. + */ + +#define PSD_PORTA_DIN 0x070000 +#define PSD_PORTA_DOUT 0x070004 +#define PSD_PORTA_DIR 0x070006 + +/* + * Flash A/B Port B configuration registers + * Addresses are offset values to CFG_FLASH1_BASE + * for Flash A and CFG_FLASH2_BASE for Flash B. + */ + +#define PSD_PORTB_DIN 0x070001 +#define PSD_PORTB_DOUT 0x070005 +#define PSD_PORTB_DIR 0x070007 + +/* + * Flash A Port A Bit definitions + */ + +#define PSDA_PPICLK1 0x20 /* PPI Clock select bit 1 */ +#define PSDA_PPICLK0 0x10 /* PPI Clock select bit 0 */ +#define PSDA_VDEC_RST 0x08 /* Video decoder reset, 0 = RESET */ +#define PSDA_VENC_RST 0x04 /* Video encoder reset, 0 = RESET */ +#define PSDA_CODEC_RST 0x01 /* Codec reset, 0 = RESET */ + +/* + * Flash A Port B Bit definitions + */ + +#define PSDA_LED9 0x20 /* LED 9, 1 = LED ON */ +#define PSDA_LED8 0x10 /* LED 8, 1 = LED ON */ +#define PSDA_LED7 0x08 /* LED 7, 1 = LED ON */ +#define PSDA_LED6 0x04 /* LED 6, 1 = LED ON */ +#define PSDA_LED5 0x02 /* LED 5, 1 = LED ON */ +#define PSDA_LED4 0x01 /* LED 4, 1 = LED ON */ diff --git a/board/ezkit533/u-boot.lds b/board/ezkit533/u-boot.lds new file mode 100644 index 000000000..10203ff89 --- /dev/null +++ b/board/ezkit533/u-boot.lds @@ -0,0 +1,148 @@ +/* + * U-boot - u-boot.lds + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(bfin) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector before the environment sector. If it throws */ + /* an error during compilation remove an object here to get */ + /* it linked after the configuration sector. */ + + cpu/bf533/start.o (.text) + cpu/bf533/start1.o (.text) + cpu/bf533/traps.o (.text) + cpu/bf533/interrupt.o (.text) + cpu/bf533/serial.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + board/ezkit533/ezkit533.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/fads/Makefile b/board/fads/Makefile index 667c6afbc..7fc88ee82 100644 --- a/board/fads/Makefile +++ b/board/fads/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o lamp.o pcmcia.o +OBJS = $(BOARD).o flash.o lamp.o pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/fads/fads.c b/board/fads/fads.c index 9e601df1b..7b04af56c 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -600,7 +600,7 @@ static int initsdram(uint base, uint *noMbytes) /* ========================================================================= */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { uint sdramsz = 0; /* size of sdram in Mbytes */ uint base = 0; /* base of dram in bytes */ @@ -778,7 +778,7 @@ int checkboard (void) /* ========================================================================= */ -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #ifdef CFG_PCMCIA_MEM_ADDR volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR; @@ -921,7 +921,7 @@ int pcmcia_init(void) return 0; } -#endif +#endif /* CFG_CMD_PCMCIA */ /* ========================================================================= */ diff --git a/board/fads/fads.h b/board/fads/fads.h index 0a8b98352..41f18b5cf 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -71,10 +71,7 @@ #undef CONFIG_BOOTARGS #undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if !defined(CONFIG_MPC885ADS) #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#endif /* * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options: @@ -96,36 +93,23 @@ #ifdef CONFIG_FEC_ENET #define CFG_DISCOVER_PHY -#define CONFIG_MII_INIT 1 #endif +#ifndef CONFIG_COMMANDS +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ + | CFG_CMD_IMMAP \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_MII \ + | CFG_CMD_PCMCIA \ + | CFG_CMD_PING \ + ) +#endif /* !CONFIG_COMMANDS */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -#if !defined(FADS_COMMANDS_ALREADY_DEFINED) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_PING - -#endif - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -134,7 +118,7 @@ #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* #undef to save memory */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -143,7 +127,7 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -176,7 +160,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ -#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ +#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ /* * 2048 SDRAM rows * 1000 factor s -> ms @@ -195,7 +179,7 @@ #if (CFG_SDRAM_SIZE) #define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ #else -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ +#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ #endif /* CFG_SDRAM_SIZE */ /* @@ -230,11 +214,10 @@ #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ #define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ #define CFG_DIRECT_FLASH_TFTP -#if defined(CONFIG_CMD_JFFS2) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) /* * JFFS2 partitions @@ -255,7 +238,7 @@ */ #define CFG_JFFS2_SORT_FRAGMENTS -#endif +#endif /* CFG_CMD_JFFS2 */ /*----------------------------------------------------------------------- * Cache Configuration @@ -266,7 +249,7 @@ /*----------------------------------------------------------------------- * I2C configuration */ -#if defined(CONFIG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ #define CFG_I2C_SLAVE 0x7F @@ -458,6 +441,10 @@ */ #define NR_8259_INTS 0 +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + /*----------------------------------------------------------------------- * PCMCIA stuff *----------------------------------------------------------------------- @@ -480,7 +467,7 @@ #define CONFIG_ISO_PARTITION 1 #undef CONFIG_ATAPI -#if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */ +#if 0 /* does not make sense when CFG_CMD_IDE is not enabled, too */ #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ #endif #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ diff --git a/board/fads/flash.c b/board/fads/flash.c index 7cda3a412..f0fb62127 100644 --- a/board/fads/flash.c +++ b/board/fads/flash.c @@ -90,7 +90,7 @@ unsigned long flash_init (void) default: pd_size = 0; or_am = 0xFFE00000; - printf("## Unsupported flash detected by BCSR: 0x%08lX\n", bcsr[2]); + printf("## Unsupported flash detected by BCSR: 0x%08X\n", bcsr[2]); } total_size = 0; diff --git a/board/fads/pcmcia.c b/board/fads/pcmcia.c index 99fe0b4fb..978c16b94 100644 --- a/board/fads/pcmcia.c +++ b/board/fads/pcmcia.c @@ -4,11 +4,11 @@ #undef CONFIG_PCMCIA -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -62,7 +62,7 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) *((uint *)BCSR1) |= reg; #endif - *((uint *)BCSR1) |= reg << 20; + *((uint *)BCSR1) |= reg << 20; return 0; } @@ -73,12 +73,12 @@ int pcmcia_hardware_enable(int slot) return 0; } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { *((uint *)BCSR1) &= ~BCSR1_PCCEN; return 0; } -#endif +#endif /* CFG_CMD_PCMCIA */ #endif /* CONFIG_PCMCIA */ diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds index c7571e499..21a2d9e32 100644 --- a/board/fads/u-boot.lds +++ b/board/fads/u-boot.lds @@ -31,11 +31,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -118,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/fads/u-boot.lds.debug b/board/fads/u-boot.lds.debug index fd2245f57..650572d4d 100644 --- a/board/fads/u-boot.lds.debug +++ b/board/fads/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/flagadm/Makefile b/board/flagadm/Makefile index dcb190703..7a2014d46 100644 --- a/board/flagadm/Makefile +++ b/board/flagadm/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c index 7caedc99a..9c553676e 100644 --- a/board/flagadm/flagadm.c +++ b/board/flagadm/flagadm.c @@ -96,7 +96,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds index f0984126b..04995ea75 100644 --- a/board/flagadm/u-boot.lds +++ b/board/flagadm/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -117,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug index 85072feda..3165d5634 100644 --- a/board/flagadm/u-boot.lds.debug +++ b/board/flagadm/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/funkwerk/vovpn-gw/Makefile b/board/funkwerk/vovpn-gw/Makefile index 493422d39..f77cc60a9 100644 --- a/board/funkwerk/vovpn-gw/Makefile +++ b/board/funkwerk/vovpn-gw/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o flash.o m88e6060.o +OBJS := $(BOARD).o flash.o m88e6060.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/funkwerk/vovpn-gw/m88e6060.c b/board/funkwerk/vovpn-gw/m88e6060.c index 58b5b6eb1..03a03d0af 100644 --- a/board/funkwerk/vovpn-gw/m88e6060.c +++ b/board/funkwerk/vovpn-gw/m88e6060.c @@ -31,7 +31,7 @@ #include "m88e6060.h" -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) static int prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 }; static int phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 }; diff --git a/board/funkwerk/vovpn-gw/u-boot.lds b/board/funkwerk/vovpn-gw/u-boot.lds new file mode 100644 index 000000000..bf8048d27 --- /dev/null +++ b/board/funkwerk/vovpn-gw/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c index 1c3f627a4..97f81eefc 100644 --- a/board/funkwerk/vovpn-gw/vovpn-gw.c +++ b/board/funkwerk/vovpn-gw/vovpn-gw.c @@ -184,7 +184,7 @@ const iop_conf_t iop_conf_tab[4][32] = { void reset_phy (void) { volatile ioport_t *iop; -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) int i; unsigned short val; #endif @@ -193,7 +193,7 @@ void reset_phy (void) /* Reset the PHY */ iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */ -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) udelay(20000); iop->pdat |= 0x00080000; for (i=0; i<100; i++) { @@ -318,7 +318,7 @@ do_reset (void *cmdtp, int flag, int argc, char *argv[]) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) -phys_size_t initdram (int board_type) +long int initdram (int board_type) { #ifndef CFG_RAMBOOT volatile immap_t *immap; diff --git a/board/g2000/Makefile b/board/g2000/Makefile index 1c60447e8..5471d1363 100644 --- a/board/g2000/Makefile +++ b/board/g2000/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o strataflash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o strataflash.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 647f4b705..39b5c701e 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -73,7 +73,7 @@ int misc_init_f (void) int misc_init_r (void) { -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) /* * Set NAND-FLASH GPIO signals to default */ @@ -131,7 +131,7 @@ long int init_sdram_static_settings(void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long int ret; @@ -149,7 +149,42 @@ phys_size_t initdram (int board_type) } -#if defined(CONFIG_CMD_NAND) +#if 1 /* test-only */ +void sdram_init(void) +{ + init_sdram_static_settings(); +} +#endif + + +#if 0 /* test-only */ +long int initdram (int board_type) +{ + unsigned long val; + + mtdcr(memcfga, mem_mb0cf); + val = mfdcr(memcfgd); + +#if 0 + printf("\nmb0cf=%x\n", val); /* test-only */ + printf("strap=%x\n", mfdcr(strap)); /* test-only */ +#endif + + return (4*1024*1024 << ((val & 0x000e0000) >> 17)); +} +#endif + + +int testdram (void) +{ + /* TODO: XXX XXX XXX */ + printf ("test: 16 MB - ok\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/g2000/u-boot.lds b/board/g2000/u-boot.lds index d70d37934..43f776579 100644 --- a/board/g2000/u-boot.lds +++ b/board/g2000/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -138,7 +139,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/gcplus/Makefile b/board/gcplus/Makefile index 7bc636bb9..1954d661c 100644 --- a/board/gcplus/Makefile +++ b/board/gcplus/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # 2003 (c) MontaVista Software, Inc. @@ -25,29 +25,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := gcplus.o flash.o +OBJS := gcplus.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/gcplus/u-boot.lds b/board/gcplus/u-boot.lds index 5ab680181..9900a57c0 100644 --- a/board/gcplus/u-boot.lds +++ b/board/gcplus/u-boot.lds @@ -53,6 +53,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/gen860t/Makefile b/board/gen860t/Makefile index fd34cb0db..dd7ecf128 100644 --- a/board/gen860t/Makefile +++ b/board/gen860t/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o beeper.o fpga.o ioport.o +OBJS = $(BOARD).o flash.o beeper.o fpga.o ioport.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/gen860t/README b/board/gen860t/README index e20680db0..7205afb4d 100644 --- a/board/gen860t/README +++ b/board/gen860t/README @@ -142,3 +142,5 @@ Sr. Staff Engineer Microvision, Inc. + +vim: set ts=4 sw=4 tw=78: diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c index b4c2c8988..46fe66ba6 100644 --- a/board/gen860t/beeper.c +++ b/board/gen860t/beeper.c @@ -34,6 +34,7 @@ * drives the amplifier input. */ + /* * Initialize beeper-related hardware. Initialize timer 1 for use with * the beeper. Use 66 Mhz internal clock with prescale of 33 to get @@ -41,59 +42,66 @@ * FIXME: we should really compute the prescale based on the reported * core clock frequency. */ -void init_beeper (void) +void +init_beeper(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1; immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK) - | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN; + | TMR_OM | TMR_FRR | TMR_ICLK_IN_GEN; immap->im_cpmtimer.cpmt_tcn1 = 0; immap->im_cpmtimer.cpmt_ter1 = 0xffff; immap->im_cpmtimer.cpmt_tgcr |= TGCR_RST1; } + /* * Set beeper frequency. Max allowed frequency is 2.5 KHz. This limit * is mostly arbitrary, but the beeper isn't really much good beyond this * frequency. */ -void set_beeper_frequency (uint frequency) +void +set_beeper_frequency(uint frequency) { #define FREQ_LIMIT 2500 - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; /* * Compute timer ticks given desired frequency. The timer is set up * to count 0.5 uS per tick and it takes two ticks per cycle (Hz). */ - if (frequency > FREQ_LIMIT) - frequency = FREQ_LIMIT; - frequency = 1000000 / frequency; - immap->im_cpmtimer.cpmt_trr1 = (ushort) frequency; + if (frequency > FREQ_LIMIT) frequency = FREQ_LIMIT; + frequency = 1000000/frequency; + immap->im_cpmtimer.cpmt_trr1 = (ushort)frequency; } + /* * Turn the beeper on */ -void beeper_on (void) +void +beeper_on(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1; } + /* * Turn the beeper off */ -void beeper_off (void) +void +beeper_off(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1; } + /* * Increase or decrease the beeper volume. Volume can be set * from off to full in 64 steps. To increase volume, the output @@ -102,71 +110,75 @@ void beeper_off (void) * change pin mode to tristate) then output a high to go back to * tristate. */ -void set_beeper_volume (int steps) +void +set_beeper_volume(int steps) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; int i; if (steps >= 0) { for (i = 0; i < (steps >= 64 ? 64 : steps); i++) { immap->im_cpm.cp_pbodr &= ~(0x80000000 >> 19); - udelay (1); + udelay(1); immap->im_cpm.cp_pbodr |= (0x80000000 >> 19); - udelay (1); + udelay(1); } - } else { + } + else { for (i = 0; i > (steps <= -64 ? -64 : steps); i--) { immap->im_cpm.cp_pbdat &= ~(0x80000000 >> 19); - udelay (1); + udelay(1); immap->im_cpm.cp_pbdat |= (0x80000000 >> 19); - udelay (1); + udelay(1); } } } + /* * Check the environment to see if the beeper needs beeping. * Controlled by a sequence of the form: * freq/delta volume/on time/off time;... where: - * freq = frequency in Hz (0 - 2500) + * freq = frequency in Hz (0 - 2500) * delta volume = volume steps up or down (-64 <= vol <= 64) * on time = time in mS * off time = time in mS * * Return 1 on success, 0 on failure */ -int do_beeper (char *sequence) +int +do_beeper(char *sequence) { #define DELIMITER ';' - int args[4]; - int i; - int val; - char *p = sequence; - char *tp; +int args[4]; +int i; +int val; +char *p = sequence; +char *tp; /* * Parse the control sequence. This is a really simple parser * without any real error checking. You can probably blow it * up really easily. */ - if (*p == '\0' || !isdigit (*p)) { - printf ("%s:%d: null or invalid string (%s)\n", - __FILE__, __LINE__, p); + if (*p == '\0' || !isdigit(*p)) { + printf("%s:%d: null or invalid string (%s)\n", + __FILE__, __LINE__, p); return 0; } i = 0; while (*p != '\0') { while (*p != DELIMITER) { - if (i > 3) - i = 0; - val = (int) simple_strtol (p, &tp, 0); + if (i > 3) i = 0; + val = (int) simple_strtol(p, &tp, 0); if (tp == p) { - printf ("%s:%d: no digits or bad format\n", - __FILE__, __LINE__); + printf("%s:%d: no digits or bad format\n", + __FILE__,__LINE__); return 0; - } else { + } + else { args[i] = val; } @@ -183,17 +195,19 @@ int do_beeper (char *sequence) */ #if 0 for (i = 0; i < 4; i++) { - printf ("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, - args[i]); + printf("%s:%d:arg %d = %d\n", __FILE__, __LINE__, i, args[i]); } - printf ("\n"); + printf("\n"); #endif - set_beeper_frequency (args[0]); - set_beeper_volume (args[1]); - beeper_on (); - udelay (1000 * args[2]); - beeper_off (); - udelay (1000 * args[3]); + + set_beeper_frequency(args[0]); + set_beeper_volume(args[1]); + beeper_on(); + udelay(1000 * args[2]); + beeper_off(); + udelay(1000 * args[3]); } return 1; } + +/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/beeper.h b/board/gen860t/beeper.h index 125b90f4b..535ee6c4d 100644 --- a/board/gen860t/beeper.h +++ b/board/gen860t/beeper.h @@ -27,3 +27,5 @@ void beeper_on(void); void beeper_off(void); void set_beeper_volume(int steps); int do_beeper(char *sequence); + +/* vim: set ts=4 tw=78 sw=4: */ diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c index 13faaf39f..ec32d07db 100644 --- a/board/gen860t/flash.c +++ b/board/gen860t/flash.c @@ -156,9 +156,9 @@ flash_init (void) * Monitor protection is ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); #endif #ifdef CFG_ENV_IS_IN_FLASH @@ -166,9 +166,9 @@ flash_init (void) * Environment protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); #endif PRINTF("## Final Flash bank size: 0x%08lx\n",size_b0); @@ -190,14 +190,14 @@ flash_get_offsets (ulong base, flash_info_t *info) switch (info->flash_id & FLASH_VENDMASK) { case FLASH_MAN_INTEL: - for (i = 0; i < info->sector_count; i++) { + for (i = 0; i < info->sector_count; i++) { info->start[i] = base; base += 1024 * 128; - } - return; + } + return; default: - printf ("Don't know sector offsets for FLASH" + printf ("Don't know sector offsets for FLASH" " type 0x%lx\n", info->flash_id); return; } @@ -436,7 +436,7 @@ write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p, * We assume that the block does not cross a boundary (we'll check before * calling this function). */ - for (i = 0; i < info_p->sector_count; ++i) { + for (i = 0; i < info_p->sector_count; ++i) { if ( ((ulong)dest_p >= info_p->start[i]) && ((ulong)dest_p < (info_p->start[i] + blocksize)) ) { PRINTF("%s:%d: Dest addr 0x%p is in block %d @ 0x%.8lx\n", diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index 1e6bdf1cc..2ba7e0e42 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_FPGA) +#if (CONFIG_FPGA) #if 0 #define GEN860T_FPGA_DEBUG @@ -376,3 +376,5 @@ int fpga_busy_fn (int cookie) return 0; } #endif + +/* vim: set ts=4 tw=78 sw=4: */ diff --git a/board/gen860t/fpga.h b/board/gen860t/fpga.h index 18deb739b..01967a42f 100644 --- a/board/gen860t/fpga.h +++ b/board/gen860t/fpga.h @@ -41,3 +41,5 @@ extern int fpga_busy_fn(int cookie); extern int fpga_abort_fn(int cookie ); extern int fpga_pre_config_fn(int cookie ); extern int fpga_post_config_fn(int cookie ); + +/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index e3d0e435d..eb7322100 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; #include #endif -#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII) +#if defined(CFG_CMD_MII) && defined(CONFIG_MII) #include #endif @@ -158,7 +158,7 @@ int checkboard (void) /* * Initialize SDRAM */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; @@ -222,7 +222,7 @@ phys_size_t initdram (int board_type) * Disk On Chip (DOC) Millenium initialization. * The DOC lives in the CS2* space */ -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) extern void doc_probe (ulong physadr); void doc_init (void) @@ -250,11 +250,11 @@ int misc_init_r (void) config_mpc8xx_ioports (immr); -#if defined(CONFIG_CMD_MII) +#if (CONFIG_COMMANDS & CFG_CMD_MII) mii_init (); #endif -#if defined(CONFIG_FPGA) +#if (CONFIG_FPGA) gen860t_init_fpga (); #endif return 0; diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c index d8c3006a6..1fc95455a 100644 --- a/board/gen860t/ioport.c +++ b/board/gen860t/ioport.c @@ -43,10 +43,10 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* * Port A configuration * Pin Signal Type Active Initial state - * PA7 fpgaProgramLowOut Out Low High - * PA1 fpgaCoreVoltageFailLow In Low N/A + * PA7 fpgaProgramLowOut Out Low High + * PA1 fpgaCoreVoltageFailLow In Low N/A */ - { /* conf ppar psor pdir podr pdat pint function */ + { /* conf ppar psor pdir podr pdat pint function */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* No pin */ /* PA15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ @@ -83,7 +83,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { * PB23 batteryOkSig In High X * PB31 pulseCatcherClr Out High 0 */ - { /* conf ppar psor pdir podr pdat pint function */ + { /* conf ppar psor pdir podr pdat pint function */ #if !defined(CONFIG_SC) /* PB31 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ #else @@ -116,7 +116,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { #if !defined(CONFIG_SC) /* PB14 */ { 1, 0, 0, 0, 0, 0, 0 } /* docBusyLow */ #else - /* PB14 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ + /* PB14 */ { 0, 0, 0, 0, 0, 0, 0 } /* */ #endif }, @@ -132,7 +132,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { * PC12 systemBitOkIn In High X * PC15 selfDreqLow In Low X */ - { /* conf ppar psor pdir podr pdat pint function */ + { /* conf ppar psor pdir podr pdat pint function */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PC15 */ { 1, 0, 0, 0, 0, 0, 0 }, /* selfDreqLowIn */ @@ -141,7 +141,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { #if !defined(CONFIG_SC) /* PC12 */ { 1, 0, 0, 0, 0, 0, 0 }, /* systemBitOkIn */ #else - /* PC12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ + /* PC12 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ #endif /* PC11 */ { 1, 0, 0, 1, 0, 1, 0 }, /* fpgaResetLowOut */ #if !defined(CONFIG_SC) @@ -173,7 +173,7 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { /* * Port D configuration */ - { /* conf ppar psor pdir podr pdat pint function */ + { /* conf ppar psor pdir podr pdat pint function */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* N/A */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ /* PD15 */ { 0, 0, 0, 0, 0, 0, 0 }, /* */ diff --git a/board/gen860t/ioport.h b/board/gen860t/ioport.h index 3af0bc998..34a2d7b1d 100644 --- a/board/gen860t/ioport.h +++ b/board/gen860t/ioport.h @@ -40,3 +40,5 @@ typedef struct { } mpc8xx_iop_conf_t; extern void config_mpc8xx_ioports(volatile immap_t *immr); + +/* vim: set ts=4 tw=78 sw=4: */ diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds index bb03d3aac..7926a2e09 100644 --- a/board/gen860t/u-boot-flashenv.lds +++ b/board/gen860t/u-boot-flashenv.lds @@ -25,6 +25,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); SECTIONS { /* @@ -36,11 +37,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -119,7 +120,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index d33aa2ea1..1df481751 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -24,6 +24,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); SECTIONS { /* @@ -35,11 +36,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -120,7 +121,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/genietv/Makefile b/board/genietv/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/genietv/Makefile +++ b/board/genietv/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/genietv/flash.c b/board/genietv/flash.c index 7292c9c12..1c1728bb4 100644 --- a/board/genietv/flash.c +++ b/board/genietv/flash.c @@ -131,11 +131,11 @@ void flash_print_info (flash_info_t *info) if (info->size >> 20) { printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, + info->size >> 20, info->sector_count); } else { printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, + info->size >> 10, info->sector_count); } @@ -213,7 +213,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x00080000; - break; /* => 512Kb */ + break; /* => 512Kb */ default: info->flash_id = FLASH_UNKNOWN; @@ -448,7 +448,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* re-enable interrupts if necessary */ if (flag) - enable_interrupts(); + enable_interrupts(); /* data polling for D7 */ start = get_timer (0); diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c index fc2116967..5f8c8997e 100644 --- a/board/genietv/genietv.c +++ b/board/genietv/genietv.c @@ -118,7 +118,7 @@ static void PrintState (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *im = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &im->im_memctl; @@ -267,7 +267,7 @@ static long int dram_size (long int mbmr_value, long int *base, return (size); } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #ifdef CFG_PCMCIA_MEM_ADDR volatile unsigned char *pcmcia_mem = (unsigned char *) CFG_PCMCIA_MEM_ADDR; @@ -357,4 +357,4 @@ int pcmcia_init (void) return 0; } -#endif +#endif /* CFG_CMD_PCMCIA */ diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index 3573608d2..f48b9ad2a 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -127,7 +128,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug index 8dedba814..e843df6a0 100644 --- a/board/genietv/u-boot.lds.debug +++ b/board/genietv/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/gth/Makefile b/board/gth/Makefile index 4b5c528a0..48f74cd94 100644 --- a/board/gth/Makefile +++ b/board/gth/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ee_access.o pcmcia.o +OBJS = $(BOARD).o flash.o ee_access.o pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/gth/flash.c b/board/gth/flash.c index 11e105e58..41a5c50b0 100644 --- a/board/gth/flash.c +++ b/board/gth/flash.c @@ -75,7 +75,7 @@ unsigned long flash_init (void) if (size_b1 > size_b0) { printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20,size_b0, size_b0<<20); + size_b1, size_b1<<20,size_b0, size_b0<<20); flash_info[0].flash_id = FLASH_UNKNOWN; flash_info[1].flash_id = FLASH_UNKNOWN; diff --git a/board/gth/gth.c b/board/gth/gth.c index 788a6a094..b1fcbf5cc 100644 --- a/board/gth/gth.c +++ b/board/gth/gth.c @@ -265,7 +265,7 @@ int initsdram (uint base, uint * noMbytes) #endif } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { u32 *i; u32 j; diff --git a/board/gth/pcmcia.c b/board/gth/pcmcia.c index cffcbde89..fce549263 100644 --- a/board/gth/pcmcia.c +++ b/board/gth/pcmcia.c @@ -4,11 +4,11 @@ #undef CONFIG_PCMCIA -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -83,7 +83,7 @@ int pcmcia_hardware_enable (int slot) return 0; } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { return 0; /* No hardware to disable */ diff --git a/board/gth/u-boot.lds b/board/gth/u-boot.lds index 95f94454d..8ac4bdad0 100644 --- a/board/gth/u-boot.lds +++ b/board/gth/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -117,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/gth2/Makefile b/board/gth2/Makefile index 097ffec35..8ef3a51d8 100644 --- a/board/gth2/Makefile +++ b/board/gth2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2005-2006 +# (C) Copyright 2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,23 +23,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o ee_access.o +OBJS = $(BOARD).o flash.o ee_access.o SOBJS = lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c index cea65c677..ffeaf587b 100644 --- a/board/gth2/gth2.c +++ b/board/gth2/gth2.c @@ -26,17 +26,18 @@ #include #include #include -#include #include #include "ee_access.h" static int wdi_status = 0; +unsigned long mips_io_port_base = 0; + #define SDRAM_SIZE ((64*1024*1024)-(12*4096)) -#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096)) +#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096)) void inline log_serial_char(char c){ char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER; @@ -83,7 +84,7 @@ void hw_watchdog_reset(void){ } } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ @@ -135,7 +136,7 @@ int checkboard (void) *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - proc_id = read_c0_prid(); + proc_id = read_32bit_cp0_register(CP0_PRID); switch (proc_id >> 24) { case 0: @@ -146,9 +147,6 @@ int checkboard (void) default: printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); } - - set_io_port_base(0); - #ifdef CONFIG_IDE_PCMCIA /* PCMCIA is on a 36 bit physical address. We need to map it into a 32 bit addresses */ @@ -431,7 +429,7 @@ int misc_init_r(void){ (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) { printf ("*** ethernet addr invalid, using default ***\n"); } else { - setenv ("ethaddr", (char *)Rx); + setenv ("ethaddr", Rx); } return (0); } diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S index 4c4f0ebd2..983ff704a 100644 --- a/board/gth2/lowlevel_init.S +++ b/board/gth2/lowlevel_init.S @@ -1,6 +1,7 @@ /* Memory sub-system initialization code */ #include +#include #include #include #include @@ -412,9 +413,7 @@ noCacheJump: j clearmem nop -#if 0 .globl memtest -#endif memtest: /* Fill memory with address */ li t0, 0x80000000 @@ -435,9 +434,7 @@ mt1: lw t2, 0(t0) bne t1, zero, mt1 nop nop -#if 0 .globl clearmem -#endif clearmem: /* Clear memory */ li t0, 0x80000000 @@ -449,7 +446,7 @@ mtc: sw zero, 0(t0) nop nop memtestend: - jr ra + j ra nop memhang: diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds index 8265130ff..8ba0b6d4c 100644 --- a/board/gth2/u-boot.lds +++ b/board/gth2/u-boot.lds @@ -43,28 +43,26 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = .; - _gp = ALIGN(16) + 0x7ff0; + . = ALIGN(4); + .sdata : { *(.sdata) } - .got : { - __got_start = .; - *(.got) - __got_end = .; - } + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; .sdata : { *(.sdata) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; . = ALIGN(4); - .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .sbss : { *(.sbss) } + .bss : { *(.bss) } uboot_end = .; } diff --git a/board/gw8260/Makefile b/board/gw8260/Makefile index cb3c566d3..827a6ac5f 100644 --- a/board/gw8260/Makefile +++ b/board/gw8260/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := gw8260.o flash.o +OBJS := gw8260.o flash.o SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/gw8260/gw8260.c b/board/gw8260/gw8260.c index 42c9e0d10..2719a9585 100644 --- a/board/gw8260/gw8260.c +++ b/board/gw8260/gw8260.c @@ -606,7 +606,7 @@ int testdram (void) /* */ /* */ /*********************************************************************/ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/gw8260/u-boot.lds b/board/gw8260/u-boot.lds new file mode 100644 index 000000000..ab65cb11f --- /dev/null +++ b/board/gw8260/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/hermes/Makefile b/board/hermes/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/hermes/Makefile +++ b/board/hermes/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c index f9b57204f..a523db1a4 100644 --- a/board/hermes/hermes.c +++ b/board/hermes/hermes.c @@ -134,7 +134,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -597,7 +597,6 @@ void show_boot_progress (int status) { volatile immap_t *immr = (immap_t *) CFG_IMMR; - if (status < -32) status = -1; /* let things compatible */ status ^= 0x0F; status = (status & 0x0F) << 14; immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status; diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index 5f5fb0d58..ef53ab7a0 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug index 41d603f7e..a961fa47b 100644 --- a/board/hermes/u-boot.lds.debug +++ b/board/hermes/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/hidden_dragon/Makefile b/board/hidden_dragon/Makefile index 5aa02d4a7..b9f1df685 100644 --- a/board/hidden_dragon/Makefile +++ b/board/hidden_dragon/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/hidden_dragon/hidden_dragon.c b/board/hidden_dragon/hidden_dragon.c index 5713a3384..daab8334e 100644 --- a/board/hidden_dragon/hidden_dragon.c +++ b/board/hidden_dragon/hidden_dragon.c @@ -44,7 +44,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/hidden_dragon/speed.h b/board/hidden_dragon/speed.h index 3f32a143c..b66393bec 100644 --- a/board/hidden_dragon/speed.h +++ b/board/hidden_dragon/speed.h @@ -28,10 +28,10 @@ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 * * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock + * GCLK CPU clock * SPEED_TMR2_PS prescaler */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ /*----------------------------------------------------------------------- * Timer value for PIT diff --git a/board/hidden_dragon/u-boot.lds b/board/hidden_dragon/u-boot.lds new file mode 100644 index 000000000..2a5cd2ebd --- /dev/null +++ b/board/hidden_dragon/u-boot.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/hmi1001/Makefile b/board/hmi1001/Makefile index 442e2d0df..ed36ea717 100644 --- a/board/hmi1001/Makefile +++ b/board/hmi1001/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o +OBJS := $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/hmi1001/config.mk b/board/hmi1001/config.mk index 4fe18316e..51e8e84c5 100644 --- a/board/hmi1001/config.mk +++ b/board/hmi1001/config.mk @@ -39,4 +39,3 @@ TEXT_BASE = 0xFFF00000 endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board -LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c index 8cfd75bd8..237e86316 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/hmi1001/hmi1001.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2008 + * (C) Copyright 2003-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2004 @@ -30,7 +30,6 @@ #include #include #include -#include #include #ifndef CFG_RAMBOOT @@ -80,12 +79,11 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT ulong test1, test2; - uint svr, pvr; /* setup SDRAM chip selects */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ @@ -105,9 +103,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -149,24 +147,6 @@ phys_size_t initdram (int board_type) #endif /* CFG_RAMBOOT */ - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - /* return dramsize + dramsize2; */ return dramsize; } @@ -199,7 +179,7 @@ struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) return kbd_data; } -static int compare_magic (const struct kbd_data_t *kbd_data, char *str) +static int compare_magic (const struct kbd_data_t *kbd_data, uchar *str) { char s1 = str[0]; char s2; @@ -242,11 +222,11 @@ static int compare_magic (const struct kbd_data_t *kbd_data, char *str) return 0; } -static char *key_match (const struct kbd_data_t *kbd_data) +static uchar *key_match (const struct kbd_data_t *kbd_data) { - char magic[sizeof (kbd_magic_prefix) + 1]; - char *suffix; - char *kbd_magic_keys; + uchar magic[sizeof (kbd_magic_prefix) + 1]; + uchar *suffix; + uchar *kbd_magic_keys; /* * The following string defines the characters that can be appended @@ -267,7 +247,7 @@ static char *key_match (const struct kbd_data_t *kbd_data) sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); if (compare_magic(kbd_data, getenv(magic)) == 0) { - char cmd_name[sizeof (kbd_command_prefix) + 1]; + uchar cmd_name[sizeof (kbd_command_prefix) + 1]; char *cmd; sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); @@ -287,7 +267,7 @@ int misc_init_r (void) #ifdef CONFIG_PREBOOT struct kbd_data_t kbd_data; /* Decode keys */ - char *str = strdup (key_match (get_keys (&kbd_data))); + uchar *str = strdup (key_match (get_keys (&kbd_data))); /* Set or delete definition */ setenv ("preboot", str); free (str); diff --git a/board/hmi1001/u-boot.lds b/board/hmi1001/u-boot.lds new file mode 100644 index 000000000..123a14c5a --- /dev/null +++ b/board/hmi1001/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xxx/start.o (.text) + cpu/mpc5xxx/traps.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/hymod/Makefile b/board/hymod/Makefile index 1fb7e79aa..b52af9a71 100644 --- a/board/hymod/Makefile +++ b/board/hymod/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o +OBJS = $(BOARD).o flash.o bsp.o eeprom.o fetch.o input.o env.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c index 12f140201..6868f260c 100644 --- a/board/hymod/bsp.c +++ b/board/hymod/bsp.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; * Board Special Commands: FPGA load/store, EEPROM erase */ -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) #define LOAD_SUCCESS 0 #define LOAD_FAIL_NOCONF 1 @@ -402,4 +402,6 @@ do_htest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } -#endif +#endif /* CFG_CMD_BSP */ + +/* ------------------------------------------------------------------------- */ diff --git a/board/hymod/config.mk b/board/hymod/config.mk index 2df321fdd..0a9985f33 100644 --- a/board/hymod/config.mk +++ b/board/hymod/config.mk @@ -30,5 +30,3 @@ TEXT_BASE = 0x40000000 PLATFORM_CPPFLAGS += -I$(TOPDIR) OBJCFLAGS = --remove-section=.ppcenv - -LDSCRIPT := $(SRCTREE)/board/hymod/u-boot.lds diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c index 91aaab1b0..5e98e9edb 100644 --- a/board/hymod/hymod.c +++ b/board/hymod/hymod.c @@ -86,7 +86,7 @@ const iop_conf_t iop_conf_tab[4][32] = { { 1, 0, 0, 1, 0, 0 }, /* PA03: VM ENABLE */ { 1, 0, 0, 0, 1, 0 }, /* PA02: VM DONE */ { 1, 0, 0, 1, 1, 0 }, /* PA01: VM INIT */ - { 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */ + { 1, 0, 0, 1, 0, 0 } /* PA00: VM ~PROG */ }, /* Port B configuration */ @@ -364,7 +364,7 @@ misc_init_f (void) /* ------------------------------------------------------------------------- */ -phys_size_t +long initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; @@ -414,10 +414,10 @@ initdram (int board_type) /* ------------------------------------------------------------------------- */ /* miscellaneous initialisations after relocation into ram (misc_init_r) */ -/* */ +/* */ /* loads the data in the main board and mezzanine board eeproms into */ /* the hymod configuration struct stored in the board information area. */ -/* */ +/* */ /* if the contents of either eeprom is invalid, prompts for a serial */ /* number (and an ethernet address if required) then fetches a file */ /* containing information to be stored in the eeprom from the tftp server */ diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index cb7b4ea06..337a3954d 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -130,7 +131,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug index c33581d25..ddd4678ee 100644 --- a/board/hymod/u-boot.lds.debug +++ b/board/hymod/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/icecube/Makefile b/board/icecube/Makefile index c94e24fc6..eb5ed591a 100644 --- a/board/icecube/Makefile +++ b/board/icecube/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,28 +24,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o flash.o +OBJS := $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/icecube/config.mk b/board/icecube/config.mk index 170779d6c..07b5de188 100644 --- a/board/icecube/config.mk +++ b/board/icecube/config.mk @@ -32,7 +32,7 @@ # 0x00100000 boot from RAM (for testing only) # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE ## Standard: boot high diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 760db7368..4f056b2fa 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -28,7 +28,6 @@ #include #include #include -#include #if defined(CONFIG_LITE5200B) #include "mt46v32m16.h" @@ -39,53 +38,6 @@ #include "mt48lc16m16a2-75.h" # endif #endif - -#ifdef CONFIG_LITE5200B_PM -/* u-boot part of low-power mode implementation */ -#define SAVED_ADDR (*(void **)0x00000000) -#define PSC2_4 0x02 - -void lite5200b_wakeup(void) -{ - unsigned char wakeup_pin; - void (*linux_wakeup)(void); - - /* check PSC2_4, if it's down "QT" is signaling we have a wakeup - * from low power mode */ - *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4; - __asm__ volatile ("sync"); - - wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I; - if (wakeup_pin & PSC2_4) - return; - - /* acknowledge to "QT" - * by holding pin at 1 for 10 uS */ - *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4; - __asm__ volatile ("sync"); - *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4; - __asm__ volatile ("sync"); - udelay(10); - - /* put ram out of self-refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */ - __asm__ volatile ("sync"); - *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */ - __asm__ volatile ("sync"); - *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */ - __asm__ volatile ("sync"); - udelay(10); /* wait a bit */ - - /* jump back to linux kernel code */ - linux_wakeup = SAVED_ADDR; - printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n", - linux_wakeup); - linux_wakeup(); -} -#else -#define lite5200b_wakeup() -#endif - #ifndef CFG_RAMBOOT static void sdram_start (int hi_addr) { @@ -134,7 +86,7 @@ static void sdram_start (int hi_addr) */ #if defined(CONFIG_MPC5200) -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; @@ -252,14 +204,12 @@ phys_size_t initdram (int board_type) __asm__ volatile ("sync"); } - lite5200b_wakeup(); - return dramsize + dramsize2; } #elif defined(CONFIG_MGT5100) -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT @@ -356,17 +306,19 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL void init_ide_reset (void) { debug ("init_ide_reset\n"); - /* Configure PSC1_4 as GPIO output for ATA reset */ + /* Configure PSC1_4 as GPIO output for ATA reset */ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; } void ide_set_reset (int idereset) @@ -374,19 +326,11 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; /* Make a delay. MPC5200 spec says 25 usec min */ udelay(500000); } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; } } -#endif - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} -#endif +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/icecube/u-boot.lds b/board/icecube/u-boot.lds new file mode 100644 index 000000000..f23432ecf --- /dev/null +++ b/board/icecube/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/icu862/Makefile b/board/icu862/Makefile index 2b10b0c51..7b2b54582 100644 --- a/board/icu862/Makefile +++ b/board/icu862/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o pcmcia.o +OBJS = $(BOARD).o flash.o pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c index 18aa8bf6d..8da9d1c9a 100644 --- a/board/icu862/icu862.c +++ b/board/icu862/icu862.c @@ -94,7 +94,7 @@ static long int dram_size (long int, long int *, long int); /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c index 20922d8a4..20f653ba2 100644 --- a/board/icu862/pcmcia.c +++ b/board/icu862/pcmcia.c @@ -4,11 +4,11 @@ #undef CONFIG_PCMCIA -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -155,7 +155,7 @@ int pcmcia_hardware_enable(int slot) } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { volatile immap_t *immap; @@ -183,7 +183,7 @@ int pcmcia_hardware_disable(int slot) return (0); } -#endif +#endif /* CFG_CMD_PCMCIA */ int pcmcia_voltage_set(int slot, int vcc, int vpp) @@ -223,10 +223,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) reg = cp->cp_pbdat; switch(vcc) { - case 0: break; /* Switch off */ + case 0: break; /* Switch off */ case 33: reg &= ~TPS2205_VCC3; break; /* Switch on 3.3V */ case 50: reg &= ~TPS2205_VCC5; break; /* Switch on 5.0V */ - default: goto done; + default: goto done; } /* Checking supported voltages */ diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index be4bf7278..4bc50c50c 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -131,7 +132,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug index 7a7a40c23..87f228bee 100644 --- a/board/icu862/u-boot.lds.debug +++ b/board/icu862/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/ids8247/Makefile b/board/ids8247/Makefile index 4c9634c97..cfef750ec 100644 --- a/board/ids8247/Makefile +++ b/board/ids8247/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2005 # Heiko Schocher, DENX Software Engineering, # @@ -26,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index 065014a11..7b9a83d0f 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -25,12 +25,6 @@ #include #include -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#include -#endif - DECLARE_GLOBAL_DATA_PTR; /* @@ -44,12 +38,12 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port A configuration */ { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ + /* PA31 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 COL */ + /* PA30 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 CRS */ + /* PA29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ + /* PA28 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ + /* PA27 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ + /* PA26 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ /* PA25 */ { 0, 0, 0, 0, 1, 0 }, /* 8247_P0 */ #if defined(CONFIG_SOFT_I2C) /* PA24 */ { 1, 0, 0, 0, 1, 1 }, /* I2C_SDA2 */ @@ -59,14 +53,14 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */ #endif /* PA22 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_DCD */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ /* PA13 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_RTS */ /* PA12 */ { 0, 0, 0, 0, 1, 0 }, /* SMC2_CTS */ /* PA11 */ { 0, 0, 0, 1, 1, 0 }, /* SMC2_DTR */ @@ -85,20 +79,20 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port B configuration */ { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ @@ -129,8 +123,8 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ /* PC25 */ { 0, 1, 1, 0, 0, 0 }, /* SYNC_IN */ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */ - /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ @@ -186,7 +180,7 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 1, 0, 0, 1, 0, 1 }, /* MII_MDIO */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* MII_MDIO */ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ @@ -230,7 +224,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * mapped by the controller. That means, that the initial mapping has * to be (at least) twice as large as the maximum expected size. */ - maxsize = (1 + (~orx | 0x7fff))/* / 2*/; + maxsize = (1 + (~orx | 0x7fff)) / 2; sdmr_ptr = &memctl->memc_psdmr; orx_ptr = &memctl->memc_or2; @@ -276,7 +270,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, return (size); } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; @@ -306,7 +300,7 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0xff800000; } -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) extern ulong nand_probe (ulong physadr); @@ -321,27 +315,4 @@ nand_init (void) printf ("%4lu MB\n", totlen >>20); } -#endif /* CONFIG_CMD_NAND */ - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -/* - * update "memory" property in the blob - */ -void ft_blob_update(void *blob, bd_t *bd) -{ - int ret; - - ret = fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); - - if (ret < 0) { - printf("ft_blob_update(): cannot set /memory/reg " - "property err:%s\n", fdt_strerror(ret)); - } -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup( blob, bd); - ft_blob_update(blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ +#endif /* CFG_CMD_NAND */ diff --git a/board/ids8247/u-boot.lds b/board/ids8247/u-boot.lds new file mode 100644 index 000000000..788aed3c6 --- /dev/null +++ b/board/ids8247/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Heiko Schocher, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/impa7/Makefile b/board/impa7/Makefile index 4cb13b74a..08543f94f 100644 --- a/board/impa7/Makefile +++ b/board/impa7/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := impa7.o flash.o +OBJS := impa7.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/impa7/u-boot.lds b/board/impa7/u-boot.lds index 4a89cebaa..1122d7521 100644 --- a/board/impa7/u-boot.lds +++ b/board/impa7/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/incaip/Makefile b/board/incaip/Makefile index afe02c27c..d9b0e2d25 100644 --- a/board/incaip/Makefile +++ b/board/incaip/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,23 +23,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o SOBJS = lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c index ac7ad8f29..b5d9e0049 100644 --- a/board/incaip/incaip.c +++ b/board/incaip/incaip.c @@ -25,16 +25,10 @@ #include #include #include -#include -#include + extern uint incaip_get_cpuclk(void); -void _machine_restart(void) -{ - *INCA_IP_WDT_RST_REQ = 0x3f; -} - static ulong max_sdram_size(void) { /* The only supported SDRAM data width is 16bit. @@ -53,7 +47,7 @@ static ulong max_sdram_size(void) return size; } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0; ulong size, max_size = 0; @@ -63,7 +57,7 @@ phys_size_t initdram(int board_type) /* Can't probe for RAM size unless we are running from Flash. */ - if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1)) + if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1)) { return max_sdram_size(); } @@ -91,6 +85,7 @@ phys_size_t initdram(int board_type) int checkboard (void) { + unsigned long chipid = *INCA_IP_WDT_CHIPID; int part_num; @@ -112,7 +107,5 @@ int checkboard (void) printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000); - set_io_port_base(0); - return 0; } diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S index fe525ec70..14d738aa1 100644 --- a/board/incaip/lowlevel_init.S +++ b/board/incaip/lowlevel_init.S @@ -23,6 +23,7 @@ */ #include +#include #include @@ -104,7 +105,7 @@ __ebu_init: li t2, 0x684143FD sw t2, EBU_BUSCON1(t1) 3: - jr ra + j ra nop .end ebu_init @@ -169,7 +170,7 @@ __cgu_init: li t2, 0x80000001 sw t2, CGU_MUXCR(t1) 5: - jr ra + j ra nop .end cgu_init @@ -265,7 +266,7 @@ __sdram_init: li t2, 0x00000001 sw t2, MC_CTRLENA(t1) - jr ra + j ra nop .end sdram_init @@ -275,12 +276,6 @@ __sdram_init: .ent lowlevel_init lowlevel_init: - /* Disable Watchdog. - */ - la t9, disable_incaip_wdt - jalr t9 - nop - /* EBU, CGU and SDRAM Initialization. */ li a0, CPU_CLOCK_RATE @@ -297,7 +292,7 @@ lowlevel_init: nop move ra, t0 - jr ra + j ra nop .end lowlevel_init diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 1e1c5590d..10c991798 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -43,28 +43,27 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = .; - _gp = ALIGN(16) + 0x7ff0; + . = ALIGN(4); + .sdata : { *(.sdata) } - .got : { - __got_start = .; - *(.got) - __got_end = .; - } + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; .sdata : { *(.sdata) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; . = ALIGN(4); - .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .sbss : { *(.sbss) } + .bss : { *(.bss) } uboot_end = .; } diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile index 442e2d0df..bf832927c 100644 --- a/board/inka4x0/Makefile +++ b/board/inka4x0/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o +OBJS := $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/inka4x0/config.mk b/board/inka4x0/config.mk index fc70efeee..cb19a7dae 100644 --- a/board/inka4x0/config.mk +++ b/board/inka4x0/config.mk @@ -39,4 +39,3 @@ TEXT_BASE = 0xFFE00000 endif PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board -LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot-customlayout.lds diff --git a/board/inka4x0/flash.c b/board/inka4x0/flash.c new file mode 100644 index 000000000..b13865530 --- /dev/null +++ b/board/inka4x0/flash.c @@ -0,0 +1,432 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * CPU to flash interface is 8-bit, so make declaration accordingly + */ +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + extern void flash_preinit(void); + ulong flashbase = CFG_FLASH_BASE; + + flash_preinit(); + + /* Init: no FLASHes known */ + memset(&flash_info[0], 0, sizeof(flash_info_t)); + + flash_info[0].size = + flash_get_size((FPW *)flashbase, &flash_info[0]); + + size = flash_info[0].size; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && info->start[0] <= base && + base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM116DB: + printf ("AM29LV116DB (16Mbit, bottom boot sect)\n"); + break; + case FLASH_AMLV128U: + printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); + break; + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + int i; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(100); + switch (addr[0] & 0xff) { + + case (uchar)AMD_MANUFACT: + debug ("Manufacturer: AMD (Spansion)\n"); + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + debug ("Manufacturer: Intel (not supported yet)\n"); + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { + + case (uchar)AMD_ID_LV116DB: + debug ("Chip: AM29LV116DB\n"); + info->flash_id += FLASH_AM116DB; + info->sector_count = 35; + info->size = 0x00200000; + /* + * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all + * the other ones are 64 kB + */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for( i = 4; i < info->sector_count; i++ ) + info->start[i] = + base + (i * (64 << 10)) - 0x00030000; + break; /* => 2 MB */ + + case (FPW)AMD_ID_LV160B: + debug ("Chip: AM29LV160MB\n"); + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + /* + * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all + * the other ones are 64 kB + */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for( i = 4; i < info->sector_count; i++ ) + info->start[i] = + base + (i * 2 * (64 << 10)) - 0x00060000; + break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + } + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + FPWV *addr = (FPWV*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + debug ("flash_erase: first: %d last: %d\n", s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = (FPW)0x00AA00AA; + addr[0x02AA] = (FPW)0x00550055; + addr[0x0555] = (FPW)0x00800080; + addr[0x0555] = (FPW)0x00AA00AA; + addr[0x02AA] = (FPW)0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (FPWV*)(info->start[sect]); + addr[0] = (FPW)0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (FPWV*)(info->start[l_sect]); + while ((addr[0] & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (FPWV*)info->start[0]; + addr[0] = (FPW)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + int i, rc = 0; + + for (i = 0; i < cnt; i++) + if ((rc = write_word_amd(info, (FPW *)(addr+i), src[i])) != 0) { + return (rc); + } + + return rc; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + return (1); + } + } + return (0); +} diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index a2e35ff0f..29878f9b4 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -31,18 +31,10 @@ #include #include -#if defined(CONFIG_DDR_MT46V16M16) +#if defined(CONFIG_MPC5200_DDR) #include "mt46v16m16-75.h" -#elif defined(CONFIG_SDR_MT48LC16M16A2) -#include "mt48lc16m16a2-75.h" -#elif defined(CONFIG_DDR_MT46V32M16) -#include "mt46v32m16.h" -#elif defined(CONFIG_DDR_HYB25D512160BF) -#include "hyb25d512160bf.h" -#elif defined(CONFIG_DDR_K4H511638C) -#include "k4h511638c.h" #else -#error "INKA4x0 SDRAM: invalid chip type specified!" +#include "mt48lc16m16a2-75.h" #endif #ifndef CFG_RAMBOOT @@ -92,11 +84,11 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT - long test1, test2; + ulong test1, test2; /* setup SDRAM chip selects */ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ @@ -116,9 +108,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -149,8 +141,18 @@ phys_size_t initdram (int board_type) } else { dramsize = 0; } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + #endif /* CFG_RAMBOOT */ +/* return dramsize + dramsize2; */ return dramsize; } @@ -171,9 +173,12 @@ void flash_preinit(void) *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } +#define GPIO_WKUP_7 0x80000000UL +#define GPIO_PSC3_9 0x04000000UL + int misc_init_f (void) { - char tmp[10]; + uchar tmp[10]; int i, br; i = getenv_r("brightness", tmp, sizeof(tmp)); @@ -213,13 +218,13 @@ int misc_init_f (void) *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000; /* Set LR mirror bit because it is low-active */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WKUP_7; + *(vu_long *)MPC5XXX_WU_GPIO_DATA |= GPIO_WKUP_7; /* * Reset Coral-P graphics controller */ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC3_9; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC3_9; return 0; } @@ -234,7 +239,9 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#define GPIO_PSC1_4 0x01000000UL void init_ide_reset (void) { @@ -244,7 +251,7 @@ void init_ide_reset (void) *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; /* Deassert reset */ - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; } void ide_set_reset (int idereset) @@ -252,11 +259,11 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); if (idereset) { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; /* Make a delay. MPC5200 spec says 25 usec min */ udelay(500000); } else { - *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; } } -#endif +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h index a78e50e7c..f650faaa1 100644 --- a/board/inka4x0/mt46v16m16-75.h +++ b/board/inka4x0/mt46v16m16-75.h @@ -23,10 +23,15 @@ #define SDRAM_DDR 1 /* is DDR */ +#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714F0F00 +#define SDRAM_CONTROL 0x714f0f00 #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h index 15477259c..13a97ac46 100644 --- a/board/inka4x0/mt48lc16m16a2-75.h +++ b/board/inka4x0/mt48lc16m16a2-75.h @@ -21,10 +21,27 @@ * MA 02111-1307 USA */ -#define SDRAM_DDR 0 /* is SDR */ +#define SDRAM_DDR 1 /* is SDR */ +#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 +/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 +/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ +/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ #define SDRAM_CONFIG2 0x8AD70000 +/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/inka4x0/u-boot.lds b/board/inka4x0/u-boot.lds new file mode 100644 index 000000000..123a14c5a --- /dev/null +++ b/board/inka4x0/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xxx/start.o (.text) + cpu/mpc5xxx/traps.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/innokom/Makefile b/board/innokom/Makefile index afae21724..73f6a7442 100644 --- a/board/innokom/Makefile +++ b/board/innokom/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := innokom.o flash.o +OBJS := innokom.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/innokom/flash.c b/board/innokom/flash.c index 8fc6e5bd9..298acc86a 100644 --- a/board/innokom/flash.c +++ b/board/innokom/flash.c @@ -88,8 +88,8 @@ ulong flash_init(void) for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); + (INTEL_MANUFACT & FLASH_VENDMASK) | + (INTEL_ID_28F128J3 & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; flash_info[i].sector_count = CFG_MAX_FLASH_SECT; memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); @@ -350,7 +350,7 @@ static int write_word (flash_info_t *info, ulong dest, ushort data) * @param info: * @param src: source of copy transaction * @param addr: where to copy to - * @param cnt: number of bytes to copy + * @param cnt: number of bytes to copy * * @return error code */ diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c index c2b88ae16..7f8f47c3a 100644 --- a/board/innokom/innokom.c +++ b/board/innokom/innokom.c @@ -72,7 +72,7 @@ int i2c_init_board(void) int misc_init_r(void) { - char *str; + uchar *str; /* determine if the software update key is pressed during startup */ if (GPLR0 & 0x00000800) { diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S index 4c9f10ffb..aa9dcba6f 100644 --- a/board/innokom/lowlevel_init.S +++ b/board/innokom/lowlevel_init.S @@ -43,7 +43,7 @@ _TEXT_BASE: /* - * Memory setup + * Memory setup */ .globl lowlevel_init @@ -129,8 +129,8 @@ lowlevel_init: /*loop: */ /* */ /* ldr r0, =0xB0070001 */ -/* ldr r1, =_LED */ -/* str r0, [r1] / hex display */ +/* ldr r1, =_LED */ +/* str r0, [r1] / hex display */ /* ---------------------------------------------------------------- */ @@ -239,7 +239,7 @@ mem_init: /* Before accessing MDREFR we need a valid DRI field, so we set */ /* this to power on defaults + DRI field. */ - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CFG_MDREFR_VAL ldr r2, =0xFFF and r3, r3, r2 ldr r4, =0x03ca4000 diff --git a/board/innokom/u-boot.lds b/board/innokom/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/innokom/u-boot.lds +++ b/board/innokom/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/integratorap/Makefile b/board/integratorap/Makefile index f78de3a10..358df6251 100644 --- a/board/integratorap/Makefile +++ b/board/integratorap/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2004 @@ -27,29 +27,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := integratorap.o flash.o +OBJS := integratorap.o flash.o SOBJS := lowlevel_init.o memsetup.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/integratorap/config.mk b/board/integratorap/config.mk index e4c5c3b57..25b79b3e7 100644 --- a/board/integratorap/config.mk +++ b/board/integratorap/config.mk @@ -3,9 +3,3 @@ # TEXT_BASE = 0x01000000 - -ifneq ($(OBJTREE),$(SRCTREE)) -# We are building u-boot in a separate directory, use generated -# .lds script from OBJTREE directory. -LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds -endif diff --git a/board/integratorap/memsetup.S b/board/integratorap/memsetup.S index da43cb6a7..dfdc7848f 100644 --- a/board/integratorap/memsetup.S +++ b/board/integratorap/memsetup.S @@ -20,7 +20,7 @@ * MA 02111-1307 USA */ /* - * Memory setup + * Memory setup * - the reset defaults are assumed sufficient */ diff --git a/board/integratorap/split_by_variant.sh b/board/integratorap/split_by_variant.sh index 8c54250ec..9f71babf3 100755 --- a/board/integratorap/split_by_variant.sh +++ b/board/integratorap/split_by_variant.sh @@ -3,7 +3,7 @@ # Set the platform defines # --------------------------------------------------------- echo -n "/* Integrator configuration implied " > tmp.fil -echo " by Makefile target */" >> tmp.fil +echo " by Makefile target */" >> tmp.fil echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil echo " /* Integrator board */" >> tmp.fil echo -n "#define CONFIG_ARCH_INTEGRATOR" >> tmp.fil @@ -14,7 +14,7 @@ echo " 1 /* Integrator/AP */" >> tmp.fil cpu="arm_intcm" variant="unknown core module" -if [ "$1" = "" ] +if [ "$1" == "" ] then echo "$0:: No parameters - using arm_intcm" else @@ -42,22 +42,22 @@ else ap720t_config) cpu="arm720t" - echo -n "#define CONFIG_CM720T" >> tmp.fil - echo " 1 /* CPU core is ARM720T */ " >> tmp.fil + echo -n "#define CONFIG_CM720T" >> tmp.fil + echo " 1 /* CPU core is ARM720T */ " >> tmp.fil variant="Core module CM720T" ;; ap922_XA10_config) cpu="arm_intcm" variant="unported core module CM922T_XA10" - echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil - echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil + echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil + echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil ;; ap920t_config) cpu="arm920t" variant="Core module CM920T" - echo -n "#define CONFIG_CM920T" >> tmp.fil + echo -n "#define CONFIG_CM920T" >> tmp.fil echo " 1 /* CPU core is ARM920T */" >> tmp.fil ;; @@ -84,36 +84,33 @@ else esac fi -if [ "$cpu" = "arm_intcm" ] +if [ "$cpu" == "arm_intcm" ] then echo "/* Core module undefined/not ported */" >> tmp.fil echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil - echo -n " /* CM may not have " >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil echo "multiple SSRAM mapping */" >> tmp.fil - echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil - echo -n " /* CM may not support SPD " >> tmp.fil + echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil + echo -n " /* CM may not support SPD " >> tmp.fil echo "query */" >> tmp.fil - echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil + echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil echo -n " /* CM may not support " >> tmp.fil - echo "remapping */" >> tmp.fil - echo -n "#undef CONFIG_CM_INIT " >> tmp.fil + echo "remapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_INIT " >> tmp.fil echo -n " /* CM may not have " >> tmp.fil echo "initialization reg */" >> tmp.fil - echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil - echo " /* CM may not have TCRAM */" >> tmp.fil + echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil + echo " /* CM may not have TCRAM */" >> tmp.fil fi - -mkdir -p ${obj}include -mkdir -p ${obj}board/integratorap -mv tmp.fil ${obj}include/config.h +mv tmp.fil ./include/config.h # --------------------------------------------------------- # Ensure correct core object loaded first in U-Boot image # --------------------------------------------------------- -sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' ${src}board/integratorap/u-boot.lds.template > ${obj}board/integratorap/u-boot.lds +sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorap/u-boot.lds.template > board/integratorap/u-boot.lds # --------------------------------------------------------- # Complete the configuration # --------------------------------------------------------- -$MKCONFIG -a integratorap arm $cpu integratorap; +./mkconfig -a integratorap arm $cpu integratorap; echo "Variant:: $variant with core $cpu" diff --git a/board/integratorcp/Makefile b/board/integratorcp/Makefile index 9201accb2..3d589fcd5 100644 --- a/board/integratorcp/Makefile +++ b/board/integratorcp/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := integratorcp.o flash.o +OBJS := integratorcp.o flash.o SOBJS := lowlevel_init.o memsetup.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/integratorcp/config.mk b/board/integratorcp/config.mk index e4c5c3b57..25b79b3e7 100644 --- a/board/integratorcp/config.mk +++ b/board/integratorcp/config.mk @@ -3,9 +3,3 @@ # TEXT_BASE = 0x01000000 - -ifneq ($(OBJTREE),$(SRCTREE)) -# We are building u-boot in a separate directory, use generated -# .lds script from OBJTREE directory. -LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds -endif diff --git a/board/integratorcp/flash.c b/board/integratorcp/flash.c index 59961cdab..4d6eff0bf 100644 --- a/board/integratorcp/flash.c +++ b/board/integratorcp/flash.c @@ -73,7 +73,7 @@ OrgDef OrgIntel_28F256L18T[] = { }; /* CP control register base address */ -#define CPCR_BASE 0xCB000000 +#define CPCR_BASE 0xCB000000 #define CPCR_EXTRABANK 0x8 #define CPCR_FLASHSIZE 0x4 #define CPCR_FLWREN 0x2 @@ -393,7 +393,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = (FPW) 0x00D000D0; } else { #ifdef DEBUG - printf ("Timeout,0x%08lx\n", status); + printf ("Timeout,0x%08x\n", status); #else printf("Timeout\n"); #endif @@ -515,7 +515,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); return (2); } @@ -542,7 +542,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) #ifdef DEBUG *addr = (FPW) 0x00700070; status = *addr; - printf("## status=0x%08lx, addr=0x%p\n", status, addr); + printf("## status=0x%08x, addr=0x%08x\n", status, addr); #endif *addr = (FPW) 0x00500050; /* clear status register cmd */ *addr = (FPW) 0x00FF00FF; /* restore read mode */ diff --git a/board/integratorcp/memsetup.S b/board/integratorcp/memsetup.S index da43cb6a7..dfdc7848f 100644 --- a/board/integratorcp/memsetup.S +++ b/board/integratorcp/memsetup.S @@ -20,7 +20,7 @@ * MA 02111-1307 USA */ /* - * Memory setup + * Memory setup * - the reset defaults are assumed sufficient */ diff --git a/board/integratorcp/split_by_variant.sh b/board/integratorcp/split_by_variant.sh index 3f0a447e4..3a354339d 100755 --- a/board/integratorcp/split_by_variant.sh +++ b/board/integratorcp/split_by_variant.sh @@ -3,16 +3,16 @@ # Set the platform defines # --------------------------------------------------------- echo -n "/* Integrator configuration implied " > tmp.fil -echo " by Makefile target */" >> tmp.fil -echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil -echo " /* Integrator board */" >> tmp.fil +echo " by Makefile target */" >> tmp.fil +echo -n "#define CONFIG_INTEGRATOR" >> tmp.fil +echo " /* Integrator board */" >> tmp.fil echo -n "#define CONFIG_ARCH_CINTEGRATOR" >> tmp.fil -echo " 1 /* Integrator/CP */" >> tmp.fil +echo " 1 /* Integrator/CP */" >> tmp.fil cpu="arm_intcm" variant="unknown core module" -if [ "$1" = "" ] +if [ "$1" == "" ] then echo "$0:: No parameters - using arm_intcm" else @@ -36,14 +36,14 @@ else cp922_XA10_config) cpu="arm_intcm" variant="unported core module CM922T_XA10" - echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil - echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil + echo -n "#define CONFIG_CM922T_XA10" >> tmp.fil + echo " 1 /* CPU core is ARM922T_XA10 */" >> tmp.fil ;; cp920t_config) cpu="arm920t" variant="Core module CM920T" - echo -n "#define CONFIG_CM920T" >> tmp.fil + echo -n "#define CONFIG_CM920T" >> tmp.fil echo " 1 /* CPU core is ARM920T */" >> tmp.fil ;; @@ -79,36 +79,33 @@ else fi -if [ "$cpu" = "arm_intcm" ] +if [ "$cpu" == "arm_intcm" ] then echo "/* Core module undefined/not ported */" >> tmp.fil - echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil + echo "#define CONFIG_ARM_INTCM 1" >> tmp.fil echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM" >> tmp.fil - echo -n " /* CM may not have " >> tmp.fil - echo "multiple SSRAM mapping */" >> tmp.fil - echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil - echo -n " /* CM may not support SPD " >> tmp.fil - echo "query */" >> tmp.fil - echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil - echo -n " /* CM may not support " >> tmp.fil - echo "remapping */" >> tmp.fil - echo -n "#undef CONFIG_CM_INIT " >> tmp.fil - echo -n " /* CM may not have " >> tmp.fil - echo "initialization reg */" >> tmp.fil - echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil - echo " /* CM may not have TCRAM */" >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil + echo "multiple SSRAM mapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_SPD_DETECT " >> tmp.fil + echo -n " /* CM may not support SPD " >> tmp.fil + echo "query */" >> tmp.fil + echo -n "#undef CONFIG_CM_REMAP " >> tmp.fil + echo -n " /* CM may not support " >> tmp.fil + echo "remapping */" >> tmp.fil + echo -n "#undef CONFIG_CM_INIT " >> tmp.fil + echo -n " /* CM may not have " >> tmp.fil + echo "initialization reg */" >> tmp.fil + echo -n "#undef CONFIG_CM_TCRAM " >> tmp.fil + echo " /* CM may not have TCRAM */" >> tmp.fil fi - -mkdir -p ${obj}include -mkdir -p ${obj}board/integratorcp -mv tmp.fil ${obj}include/config.h +mv tmp.fil ./include/config.h # --------------------------------------------------------- # Ensure correct core object loaded first in U-Boot image # --------------------------------------------------------- -sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' ${src}board/integratorcp/u-boot.lds.template > ${obj}board/integratorcp/u-boot.lds +sed -r 's/CPU_FILE/cpu\/'$cpu'\/start.o/; s/#.*//' board/integratorcp/u-boot.lds.template > board/integratorcp/u-boot.lds # --------------------------------------------------------- # Complete the configuration # --------------------------------------------------------- -$MKCONFIG -a integratorcp arm $cpu integratorcp; +./mkconfig -a integratorcp arm $cpu integratorcp; echo "Variant:: $variant with core $cpu" diff --git a/board/ip860/Makefile b/board/ip860/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/ip860/Makefile +++ b/board/ip860/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c index 375cd4d26..9dd809b67 100644 --- a/board/ip860/ip860.c +++ b/board/ip860/ip860.c @@ -137,7 +137,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds index ef8829793..8cb250443 100644 --- a/board/ip860/u-boot.lds +++ b/board/ip860/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug index ad685e6f8..43d2b3bd6 100644 --- a/board/ip860/u-boot.lds.debug +++ b/board/ip860/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/iphase4539/Makefile b/board/iphase4539/Makefile index 877afde1c..19da5d065 100644 --- a/board/iphase4539/Makefile +++ b/board/iphase4539/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2002 Wolfgang Grandegger # # See file CREDITS for list of people who contributed to this @@ -25,28 +22,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o flash.o +OBJS := $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/iphase4539/iphase4539.c b/board/iphase4539/iphase4539.c index e5d0254a1..0ca9cf513 100644 --- a/board/iphase4539/iphase4539.c +++ b/board/iphase4539/iphase4539.c @@ -193,7 +193,7 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/iphase4539/u-boot.lds b/board/iphase4539/u-boot.lds new file mode 100644 index 000000000..4ea01eab6 --- /dev/null +++ b/board/iphase4539/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ispan/Makefile b/board/ispan/Makefile index 6b3706daa..9123a8026 100644 --- a/board/ispan/Makefile +++ b/board/ispan/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # Copyright (C) 2004 Arabella Software Ltd. # Yuli Barcohen # @@ -26,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o +OBJS := $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c index 12fb91fb8..d39b8cd53 100644 --- a/board/ispan/ispan.c +++ b/board/ispan/ispan.c @@ -356,7 +356,7 @@ static int hwc_board_type (char **str) return id; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long maxsize = hwc_main_sdram_size(); diff --git a/board/ispan/u-boot.lds b/board/ispan/u-boot.lds new file mode 100644 index 000000000..bf8048d27 --- /dev/null +++ b/board/ispan/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/ivm/Makefile b/board/ivm/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/ivm/Makefile +++ b/board/ivm/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c index 4882f0450..7927ea9a5 100644 --- a/board/ivm/ivm.c +++ b/board/ivm/ivm.c @@ -159,7 +159,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds index d7f360f3b..fdeabc59e 100644 --- a/board/ivm/u-boot.lds +++ b/board/ivm/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -117,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug index 995fc8327..3214f3f0c 100644 --- a/board/ivm/u-boot.lds.debug +++ b/board/ivm/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/ixdp425/Makefile b/board/ixdp425/Makefile index efeb31dba..59d6964a4 100644 --- a/board/ixdp425/Makefile +++ b/board/ixdp425/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := ixdp425.o +OBJS := ixdp425.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/ixdp425/config.mk b/board/ixdp425/config.mk index ecff8d741..34205864c 100644 --- a/board/ixdp425/config.mk +++ b/board/ixdp425/config.mk @@ -1,2 +1,4 @@ -# TEXT_BASE = 0x00f80000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/ixdp425/flash.c b/board/ixdp425/flash.c index 704dea863..1d958c8c1 100644 --- a/board/ixdp425/flash.c +++ b/board/ixdp425/flash.c @@ -35,19 +35,19 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ #define FLASH_PORT_WIDTH16 #ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) x +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) x #else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) #endif -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV -#define mb() __asm__ __volatile__ ("" : : : "memory") +#define mb() __asm__ __volatile__ ("" : : : "memory") /*----------------------------------------------------------------------- * Functions diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c index e0d763780..eaf7cdefe 100644 --- a/board/ixdp425/ixdp425.c +++ b/board/ixdp425/ixdp425.c @@ -38,6 +38,11 @@ DECLARE_GLOBAL_DATA_PTR; /* * Miscelaneous platform dependent initialisations */ +int board_post_init (void) +{ + return (0); +} + int board_init (void) { /* arch number of IXDP */ @@ -107,7 +112,7 @@ int dram_init (void) return (0); } -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) +#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined(CONFIG_PCI) extern struct pci_controller hose; extern void pci_ixp_init(struct pci_controller * hose); diff --git a/board/ixdp425/u-boot.lds b/board/ixdp425/u-boot.lds index 58393d0af..e2ceac722 100644 --- a/board/ixdp425/u-boot.lds +++ b/board/ixdp425/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/jse/Makefile b/board/jse/Makefile index 6be03ac54..0da27b696 100644 --- a/board/jse/Makefile +++ b/board/jse/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # Copyright 2004 Picture Elements, Inc. # Stephen Williams # @@ -23,29 +20,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o sdram.o flash.o host_bridge.o +OBJS = $(BOARD).o sdram.o flash.o host_bridge.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/jse/init.S b/board/jse/init.S index c564ed3c9..231cd1caf 100644 --- a/board/jse/init.S +++ b/board/jse/init.S @@ -93,3 +93,13 @@ ext_bus_cntlr_init: mtdcr ebccfgd,r4 blr + + +/*----------------------------------------------------------------------- */ +/* Function: sdram_init */ +/* Description: This function is called by cpu/ppc4xx/start.S code */ +/* to get the SDRAM initialized. */ +/*----------------------------------------------------------------------- */ + .globl sdram_init +sdram_init: + blr diff --git a/board/jse/sdram.c b/board/jse/sdram.c index 8ba6c454f..9060d979d 100644 --- a/board/jse/sdram.c +++ b/board/jse/sdram.c @@ -30,7 +30,7 @@ * in lib_ppc/board.c to initialize the memory and return what I * found. */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { /* Configure the SDRAMS */ diff --git a/board/jse/u-boot.lds b/board/jse/u-boot.lds index 7e060cbfd..60c111539 100644 --- a/board/jse/u-boot.lds +++ b/board/jse/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -130,7 +131,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/kb9202/Makefile b/board/kb9202/Makefile index 363f6657e..f36d88dc3 100644 --- a/board/kb9202/Makefile +++ b/board/kb9202/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -26,28 +26,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := kb9202.o +OBJS := kb9202.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/kb9202/kb9202.c b/board/kb9202/kb9202.c index 59ed8ff60..ec51dca91 100644 --- a/board/kb9202/kb9202.c +++ b/board/kb9202/kb9202.c @@ -65,7 +65,7 @@ int dram_init (void) } #ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac); UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac); @@ -90,5 +90,5 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) p_phyops->AutoNegotiate = lxt972_AutoNegotiate; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ #endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/kb9202/u-boot.lds b/board/kb9202/u-boot.lds index 3b7977672..76df6b2af 100644 --- a/board/kb9202/u-boot.lds +++ b/board/kb9202/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/kup/Makefile b/board/kup/Makefile index 957b3d313..071f0d2ac 100644 --- a/board/kup/Makefile +++ b/board/kup/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o kup.o +OBJS = $(BOARD).o flash.o kup.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/kup/common/pcmcia.c b/board/kup/common/pcmcia.c index 8f0cf17b9..1f61a0ecd 100644 --- a/board/kup/common/pcmcia.c +++ b/board/kup/common/pcmcia.c @@ -4,11 +4,11 @@ #undef CONFIG_PCMCIA -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -115,7 +115,7 @@ int pcmcia_hardware_enable(int slot) } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { volatile immap_t *immap; @@ -144,7 +144,7 @@ int pcmcia_hardware_disable(int slot) return (0); } -#endif +#endif /* CFG_CMD_PCMCIA */ int pcmcia_voltage_set(int slot, int vcc, int vpp) @@ -188,7 +188,7 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) cp->cp_pbdat |= KUP4K_PCMCIA_B_3V3; /* active low */ switch(vcc) { - case 0: break; + case 0: break; case 33: cp->cp_pbdat &= ~KUP4K_PCMCIA_B_3V3; debug ("PCMCIA powered at 3.3V\n"); diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile index 4727a5b1b..4a3954c38 100644 --- a/board/kup/kup4k/Makefile +++ b/board/kup/kup4k/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,26 +22,19 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o +OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index 66d618072..4e377a142 100644 --- a/board/kup/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -137,7 +137,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index 2e9169c16..8625999df 100644 --- a/board/kup/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -131,7 +132,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index f6d153763..c0cf1cb74 100644 --- a/board/kup/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile index 4727a5b1b..4a3954c38 100644 --- a/board/kup/kup4x/Makefile +++ b/board/kup/kup4x/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,26 +22,19 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o +OBJS = $(BOARD).o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c index f07ef1870..cd9ed13d6 100644 --- a/board/kup/kup4x/kup4x.c +++ b/board/kup/kup4x/kup4x.c @@ -134,7 +134,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds index 2e9169c16..8625999df 100644 --- a/board/kup/kup4x/u-boot.lds +++ b/board/kup/kup4x/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -131,7 +132,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug index f6d153763..c0cf1cb74 100644 --- a/board/kup/kup4x/u-boot.lds.debug +++ b/board/kup/kup4x/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/lantec/Makefile b/board/lantec/Makefile index dcb190703..7a2014d46 100644 --- a/board/lantec/Makefile +++ b/board/lantec/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c index 46f4da9e6..417dbbb05 100644 --- a/board/lantec/lantec.c +++ b/board/lantec/lantec.c @@ -109,7 +109,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds index 2d266434f..29ecabd9b 100644 --- a/board/lantec/u-boot.lds +++ b/board/lantec/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug index 7dc4408c6..65b25b926 100644 --- a/board/lantec/u-boot.lds.debug +++ b/board/lantec/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/lart/Makefile b/board/lart/Makefile index 9eeaa990b..550aa1dac 100644 --- a/board/lart/Makefile +++ b/board/lart/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := lart.o flash.o +OBJS := lart.o flash.o SOBJS := flashasm.o lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/lart/u-boot.lds b/board/lart/u-boot.lds index 6bd06270a..258bece23 100644 --- a/board/lart/u-boot.lds +++ b/board/lart/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/logodl/Makefile b/board/logodl/Makefile index 0795b6b2a..c7cde7d57 100644 --- a/board/logodl/Makefile +++ b/board/logodl/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := logodl.o flash.o +OBJS := logodl.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/logodl/flash.c b/board/logodl/flash.c index 0807b8091..a9477314d 100644 --- a/board/logodl/flash.c +++ b/board/logodl/flash.c @@ -593,7 +593,7 @@ int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * @param info: * @param src: source of copy transaction * @param addr: where to copy to - * @param cnt: number of bytes to copy + * @param cnt: number of bytes to copy * * @return error code */ diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c index 897787bcf..14fd28f56 100644 --- a/board/logodl/logodl.c +++ b/board/logodl/logodl.c @@ -107,7 +107,6 @@ void logodl_set_led(int led, int state) void show_boot_progress (int status) { - if (status < -32) status = -1; /* let things compatible */ /* switch(status) { case 1: logodl_set_led(0,1); break; diff --git a/board/logodl/lowlevel_init.S b/board/logodl/lowlevel_init.S index 4c9f10ffb..aa9dcba6f 100644 --- a/board/logodl/lowlevel_init.S +++ b/board/logodl/lowlevel_init.S @@ -43,7 +43,7 @@ _TEXT_BASE: /* - * Memory setup + * Memory setup */ .globl lowlevel_init @@ -129,8 +129,8 @@ lowlevel_init: /*loop: */ /* */ /* ldr r0, =0xB0070001 */ -/* ldr r1, =_LED */ -/* str r0, [r1] / hex display */ +/* ldr r1, =_LED */ +/* str r0, [r1] / hex display */ /* ---------------------------------------------------------------- */ @@ -239,7 +239,7 @@ mem_init: /* Before accessing MDREFR we need a valid DRI field, so we set */ /* this to power on defaults + DRI field. */ - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CFG_MDREFR_VAL ldr r2, =0xFFF and r3, r3, r2 ldr r4, =0x03ca4000 diff --git a/board/logodl/u-boot.lds b/board/logodl/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/logodl/u-boot.lds +++ b/board/logodl/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/lpd7a40x/Makefile b/board/lpd7a40x/Makefile index 446fd5bb8..ebe14df1b 100644 --- a/board/lpd7a40x/Makefile +++ b/board/lpd7a40x/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := lpd7a40x.o flash.o +OBJS := lpd7a40x.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/lpd7a40x/lowlevel_init.S b/board/lpd7a40x/lowlevel_init.S index 780b931be..b3ed55ce3 100644 --- a/board/lpd7a40x/lowlevel_init.S +++ b/board/lpd7a40x/lowlevel_init.S @@ -38,7 +38,7 @@ #define BCRX_IDCY_SHIFT (0) /* Bank0 Async Flash */ -#define BCR0 (0x80002000) +#define BCR0 (0x80002000) #define BCR0_FLASH (BCRX_MW_32 | (0x08< $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/lubbock/lowlevel_init.S b/board/lubbock/lowlevel_init.S index 2a9bcbf49..15276e89d 100644 --- a/board/lubbock/lowlevel_init.S +++ b/board/lubbock/lowlevel_init.S @@ -40,7 +40,7 @@ DRAM_SIZE: .long CFG_DRAM_SIZE /* - * Memory setup + * Memory setup */ .globl lowlevel_init diff --git a/board/lubbock/u-boot.lds b/board/lubbock/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/lubbock/u-boot.lds +++ b/board/lubbock/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/lwmon/Makefile b/board/lwmon/Makefile index 2b10b0c51..7b2b54582 100644 --- a/board/lwmon/Makefile +++ b/board/lwmon/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o pcmcia.o +OBJS = $(BOARD).o flash.o pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c index 4a2d8e4a4..9e8ea2db1 100644 --- a/board/lwmon/lwmon.c +++ b/board/lwmon/lwmon.c @@ -192,7 +192,7 @@ int checkboard (void) } /*********************************************************************** -F* Function: phys_size_t initdram (int board_type) P*A*Z* +F* Function: long int initdram (int board_type) P*A*Z* * P* Parameters: int board_type P* - Usually type of the board - ignored here. @@ -209,7 +209,7 @@ D* Design: wd@denx.de C* Coding: wd@denx.de V* Verification: dzu@denx.de ***********************************************************************/ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; @@ -761,7 +761,7 @@ static uchar *key_match (uchar *kbd_data) /*---------------Board Special Commands: PIC read/write ---------------*/ -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) /*********************************************************************** F* Function: int do_pic (cmd_tbl_t *cmdtp, int flag, F* int argc, char *argv[]) P*A*Z* @@ -960,7 +960,7 @@ U_BOOT_CMD( "lsb - print current setting\n" ); -#endif +#endif /* CFG_CMD_BSP */ /*----------------------------- Utilities -----------------------------*/ /*********************************************************************** diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c index 8825bd971..2349286bb 100644 --- a/board/lwmon/pcmcia.c +++ b/board/lwmon/pcmcia.c @@ -5,11 +5,11 @@ #undef CONFIG_PCMCIA -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -127,7 +127,7 @@ int pcmcia_hardware_enable(int slot) } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { volatile immap_t *immap; @@ -166,7 +166,7 @@ int pcmcia_hardware_disable(int slot) return (0); } -#endif +#endif /* CFG_CMD_PCMCIA */ int pcmcia_voltage_set(int slot, int vcc, int vpp) @@ -204,10 +204,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) val = 0; switch(vcc) { - case 0: break; + case 0: break; case 33: val = MAX1604_VCC_35; break; - case 50: break; - default: goto done; + case 50: break; + default: goto done; } /* Checking supported voltages */ diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds index bc1ea7372..6505d4556 100644 --- a/board/lwmon/u-boot.lds +++ b/board/lwmon/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -117,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug index 2ee823745..828afbbce 100644 --- a/board/lwmon/u-boot.lds.debug +++ b/board/lwmon/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/m5271evb/Makefile b/board/m5271evb/Makefile index 2ec71ee1d..34de983e3 100644 --- a/board/m5271evb/Makefile +++ b/board/m5271evb/Makefile @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o mii.o +OBJS = $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/m5271evb/m5271evb.c b/board/m5271evb/m5271evb.c index e089d5f02..c26c91d1b 100644 --- a/board/m5271evb/m5271evb.c +++ b/board/m5271evb/m5271evb.c @@ -22,14 +22,15 @@ */ #include -#include +#include +#include int checkboard (void) { puts ("Board: Freescale M5271EVB\n"); return 0; }; -phys_size_t initdram (int board_type) { +long int initdram (int board_type) { int i; diff --git a/board/m5271evb/u-boot.lds b/board/m5271evb/u-boot.lds index c07d02383..69f31793a 100644 --- a/board/m5271evb/u-boot.lds +++ b/board/m5271evb/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ GROUP(libgcc.a) @@ -34,11 +35,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -129,7 +130,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { _sbss = .; *(.sbss) *(.scommon) diff --git a/board/m5272c3/Makefile b/board/m5272c3/Makefile index be704b76f..e5d844631 100644 --- a/board/m5272c3/Makefile +++ b/board/m5272c3/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o mii.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/m5272c3/m5272c3.c b/board/m5272c3/m5272c3.c index d17cb2ef9..0dfeaf24f 100644 --- a/board/m5272c3/m5272c3.c +++ b/board/m5272c3/m5272c3.c @@ -22,17 +22,18 @@ */ #include -#include +#include +#include int checkboard (void) { puts ("Board: "); - puts ("Freescale MCF5272C3 EVB\n"); + puts("MOTOROLA MCF5272C3 EVB\n"); return 0; }; -phys_size_t initdram (int board_type) { - volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM); +long int initdram (int board_type) { + volatile sdramctrl_t * sdp = (sdramctrl_t *)(CFG_MBAR + MCFSIM_SDCR); sdp->sdram_sdtr = 0xf539; sdp->sdram_sdcr = 0x4211; diff --git a/board/m5272c3/u-boot.lds b/board/m5272c3/u-boot.lds index 8420c91a7..f7dc07090 100644 --- a/board/m5272c3/u-boot.lds +++ b/board/m5272c3/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { _sbss = .; *(.sbss) *(.scommon) diff --git a/board/m5282evb/Makefile b/board/m5282evb/Makefile index 2ec71ee1d..e5d844631 100644 --- a/board/m5282evb/Makefile +++ b/board/m5282evb/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o mii.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/m5282evb/config.mk b/board/m5282evb/config.mk index 0aa236122..848430736 100644 --- a/board/m5282evb/config.mk +++ b/board/m5282evb/config.mk @@ -22,4 +22,4 @@ # MA 02111-1307 USA # -TEXT_BASE = 0xFFE00000 +TEXT_BASE = 0x20000 diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c new file mode 100644 index 000000000..36a7c310f --- /dev/null +++ b/board/m5282evb/flash.c @@ -0,0 +1,378 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#define PHYS_FLASH_1 CFG_FLASH_BASE +#define FLASH_BANK_SIZE 0x200000 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (AMD_ID_PL160CB & FLASH_TYPEMASK): + printf ("AM29PL160CB (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done: + return; +} + + +unsigned long flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (AMD_ID_PL160CB & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured to many flash banks!\n"); + + for (j = 0; j < flash_info[i].sector_count; j++) { + if (j == 0) { + /* 1st is 16 KiB */ + flash_info[i].start[j] = flashbase; + } + if ((j >= 1) && (j <= 2)) { + /* 2nd and 3rd are 8 KiB */ + flash_info[i].start[j] = + flashbase + 0x4000 + 0x2000 * (j - 1); + } + if (j == 3) { + /* 4th is 32 KiB */ + flash_info[i].start[j] = flashbase + 0x8000; + } + if ((j >= 4) && (j <= 34)) { + /* rest is 256 KiB */ + flash_info[i].start[j] = + flashbase + 0x10000 + 0x10000 * (j - + 4); + } + } + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + 0xffff, &flash_info[0]); + + return size; +} + + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip1; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + printf ("\n"); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + if (info->protect[sect] == 0) { /* not protected */ + volatile u16 *addr = + (volatile u16 *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 + && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + } while (!chip1); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + /* allow flash to settle - wait 10 ms */ + udelay (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile u16 *addr = (volatile u16 *) dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + int chip1; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + /* wait until flash is ready */ + chip1 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + } while (!chip1); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + } + +#if 0 + if (cnt & 1) { + printf ("odd transfer sizes not supported\n"); + return ERR_ALIGN; + } +#endif + + wp = addr; + + if (addr & 1) { + data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) + src); + if ((rc = write_word (info, wp - 1, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + while (cnt >= 2) { + data = *((volatile u16 *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 1) { + data = (*((volatile u8 *) src) << 8) | + *((volatile u8 *) (wp + 1)); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + return ERR_OK; +} diff --git a/board/m5282evb/m5282evb.c b/board/m5282evb/m5282evb.c index 50e5e7736..a08af68ae 100644 --- a/board/m5282evb/m5282evb.c +++ b/board/m5282evb/m5282evb.c @@ -22,72 +22,14 @@ */ #include -#include - -DECLARE_GLOBAL_DATA_PTR; int checkboard (void) { - puts ("Board: Freescale M5282EVB Evaluation Board\n"); + puts ("MOTOROLA M5272EVB Evaluation Board\n"); return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { - u32 dramsize, i, dramclk; - - dramsize = CFG_SDRAM_SIZE * 0x100000; - for (i = 0x13; i < 0x20; i++) { - if (dramsize == (1 << i)) - break; - } - i--; - - if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) - { - dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); - - /* Initialize DRAM Control Register: DCR */ - MCFSDRAMC_DCR = (0 - | MCFSDRAMC_DCR_RTIM_6 - | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); - - /* Initialize DACR0 */ - MCFSDRAMC_DACR0 = (0 - | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE) - | MCFSDRAMC_DACR_CASL(1) - | MCFSDRAMC_DACR_CBM(3) - | MCFSDRAMC_DACR_PS_32); - - /* Initialize DMR0 */ - MCFSDRAMC_DMR0 = (0 - | ((dramsize - 1) & 0xFFFC0000) - | MCFSDRAMC_DMR_V); - - /* Set IP (bit 3) in DACR */ - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; - - /* Wait 30ns to allow banks to precharge */ - for (i = 0; i < 5; i++) { - asm ("nop"); - } - - /* Write to this block to initiate precharge */ - *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; - - /* Set RE (bit 15) in DACR */ - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; - - /* Wait for at least 8 auto refresh cycles to occur */ - for (i = 0; i < 2000; i++) { - asm(" nop"); - } - - /* Finish the configuration by issuing the IMRS. */ - MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; - - /* Write to the SDRAM Mode Register */ - *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; - } - return dramsize; + return 0x1000000; } diff --git a/board/m5282evb/u-boot.lds b/board/m5282evb/u-boot.lds index dd2666b76..c461d20e5 100644 --- a/board/m5282evb/u-boot.lds +++ b/board/m5282evb/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -127,7 +128,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { _sbss = .; *(.sbss) *(.scommon) diff --git a/board/mbx8xx/Makefile b/board/mbx8xx/Makefile index d30cc62ac..e4d10994e 100644 --- a/board/mbx8xx/Makefile +++ b/board/mbx8xx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o vpd.o pcmcia.o +OBJS = $(BOARD).o flash.o vpd.o pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c index 414d87919..9a9bf809e 100644 --- a/board/mbx8xx/mbx8xx.c +++ b/board/mbx8xx/mbx8xx.c @@ -304,7 +304,7 @@ static ulong get_ramsize (dimm_t * dimm) return size; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c index a02c84845..132a68806 100644 --- a/board/mbx8xx/pcmcia.c +++ b/board/mbx8xx/pcmcia.c @@ -6,11 +6,11 @@ #undef CONFIG_PCMCIA -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -156,11 +156,11 @@ int pcmcia_hardware_enable (int slot) return (0); } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_hardware_disable (int slot) { return 0; /* No hardware to disable */ } -#endif +#endif /* CFG_CMD_PCMCIA */ #endif /* CONFIG_PCMCIA */ diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds index 2998e835e..1400cea15 100644 --- a/board/mbx8xx/u-boot.lds +++ b/board/mbx8xx/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -117,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug index fd2245f57..650572d4d 100644 --- a/board/mbx8xx/u-boot.lds.debug +++ b/board/mbx8xx/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile index e6e81ce3c..7fdc088e9 100644 --- a/board/mcc200/Makefile +++ b/board/mcc200/Makefile @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o lcd.o auto_update.o +OBJS := $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/mcc200/config.mk b/board/mcc200/config.mk index d0f9289fe..a8225598c 100644 --- a/board/mcc200/config.mk +++ b/board/mcc200/config.mk @@ -22,7 +22,7 @@ # # -# MCC200, PRS200 boards: +# MCC200 board: # # Valid values for TEXT_BASE are: # @@ -31,7 +31,7 @@ # 0x00100000 boot from RAM (for testing only) # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE ## Standard: boot low diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 77ee3d7ed..167dc0f84 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -27,7 +27,6 @@ #include #include #include -#include /* Two MT48LC8M32B2 for 32 MB */ /* #include "mt48lc8m32b2-6-7.h" */ @@ -44,7 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[]; /* FLASH chips info */ -extern int do_auto_update(void); ulong flash_get_size (ulong base, int banknum); #ifndef CFG_RAMBOOT @@ -92,15 +90,14 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE - * is something else than 0x00000000. + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; - uint svr, pvr; #ifndef CFG_RAMBOOT ulong test1, test2; @@ -195,39 +192,17 @@ phys_size_t initdram (int board_type) #endif /* CFG_RAMBOOT */ - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - return dramsize + dramsize2; } int checkboard (void) { -#if defined(CONFIG_PRS200) - puts ("Board: PRS200\n"); -#else puts ("Board: MCC200\n"); -#endif return 0; } int misc_init_r (void) { - ulong flash_sup_end, snum; - /* * Adjust flash start and offset to detected values */ @@ -282,17 +257,8 @@ int misc_init_r (void) (flash_info[0].start[0] - 1) + flash_info[0].size, &flash_info[0]); *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); - printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n"); - flash_info[0].size = 32 << 20; - for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); - flash_info[0].start[snum] < flash_sup_end; - snum++); - flash_info[0].sector_count = snum; } -#ifdef CONFIG_AUTO_UPDATE - do_auto_update(); -#endif return (0); } @@ -307,7 +273,7 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) void init_ide_reset (void) { @@ -320,9 +286,9 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); } -#endif +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) extern void doc_probe (ulong physadr); void doc_init (void) { diff --git a/board/mcc200/u-boot.lds b/board/mcc200/u-boot.lds new file mode 100644 index 000000000..4fdea6b78 --- /dev/null +++ b/board/mcc200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ml2/Makefile b/board/ml2/Makefile index 2a9366656..40c60b1b3 100644 --- a/board/ml2/Makefile +++ b/board/ml2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o serial.o +OBJS = $(BOARD).o flash.o serial.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/ml2/flash.c b/board/ml2/flash.c index ad0f0752b..87cb1ff18 100644 --- a/board/ml2/flash.c +++ b/board/ml2/flash.c @@ -222,7 +222,7 @@ static int write_word (flash_info_t *info, ulong dest, unsigned long long data) unsigned long long result; int rc = ERR_OK; - result = *addr; + result=*addr; if ((result & data) != data) return ERR_NOT_ERASED; @@ -234,7 +234,7 @@ static int write_word (flash_info_t *info, ulong dest, unsigned long long data) eieio(); do { - result = *addr; + result=*addr; } while(~result & BIT_BUSY); *addr=CMD_READ_ARRAY; @@ -275,7 +275,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { } while(cnt>=8) { - data = *((unsigned long long *)src); + data=*((unsigned long long *)src); if ((rc = write_word(info, wp, data)) != 0) return rc; src+=8; diff --git a/board/ml2/init.S b/board/ml2/init.S index 9064d3b66..80f98c5bd 100644 --- a/board/ml2/init.S +++ b/board/ml2/init.S @@ -28,3 +28,7 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr + + .globl sdram_init +sdram_init: + blr diff --git a/board/ml2/ml2.c b/board/ml2/ml2.c index 981e1decd..f32e512d4 100644 --- a/board/ml2/ml2.c +++ b/board/ml2/ml2.c @@ -53,7 +53,7 @@ int checkboard (void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return 32 * 1024 * 1024; } diff --git a/board/ml2/serial.c b/board/ml2/serial.c index c18815bf8..74687f12c 100644 --- a/board/ml2/serial.c +++ b/board/ml2/serial.c @@ -19,9 +19,9 @@ * */ -#include #include #include +#include #include #include @@ -88,7 +88,7 @@ void serial_puts (const char *s) } } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) void kgdb_serial_init (void) { } @@ -112,4 +112,4 @@ void kgdb_interruptible (int yes) { return; } -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds index c9406ad7f..f8e9e3374 100644 --- a/board/ml2/u-boot.lds +++ b/board/ml2/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -60,7 +61,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -135,7 +136,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/ml2/u-boot.lds.debug b/board/ml2/u-boot.lds.debug index 0552994f4..1608f8cda 100644 --- a/board/ml2/u-boot.lds.debug +++ b/board/ml2/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/modnet50/Makefile b/board/modnet50/Makefile index bee5a8668..ab2c376ff 100644 --- a/board/modnet50/Makefile +++ b/board/modnet50/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := modnet50.o flash.o +OBJS := modnet50.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/modnet50/u-boot.lds b/board/modnet50/u-boot.lds index b3c2bf950..5b70a40aa 100644 --- a/board/modnet50/u-boot.lds +++ b/board/modnet50/u-boot.lds @@ -51,7 +51,7 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/board/mousse/Makefile b/board/mousse/Makefile index 3e719f0cc..ddc5546e7 100644 --- a/board/mousse/Makefile +++ b/board/mousse/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,21 +24,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o m48t59y.o pci.o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o m48t59y.o pci.o flash.o -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/mousse/config.mk b/board/mousse/config.mk index 933e6b32a..64cffa4ee 100644 --- a/board/mousse/config.mk +++ b/board/mousse/config.mk @@ -26,5 +26,3 @@ # TEXT_BASE = 0xFFF00000 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) - -LDSCRIPT := $(SRCTREE)/board/mousse/u-boot.lds diff --git a/board/mousse/m48t59y.c b/board/mousse/m48t59y.c index 2c1e6cf8b..37a624419 100644 --- a/board/mousse/m48t59y.c +++ b/board/mousse/m48t59y.c @@ -278,7 +278,7 @@ void m48_watchdog_arm(int usec) /* * U-Boot RTC support. */ -int +void rtc_get( struct rtc_time *tmp ) { m48_tod_get(&tmp->tm_year, @@ -295,8 +295,6 @@ rtc_get( struct rtc_time *tmp ) tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); #endif - - return 0; } void diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c index f8f152976..7208a17c1 100644 --- a/board/mousse/mousse.c +++ b/board/mousse/mousse.c @@ -55,7 +55,7 @@ int checkflash (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return CFG_RAM_SIZE; } diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index 86a1d85ed..57358b8a4 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -117,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram index 46b98a04a..eb47ae670 100644 --- a/board/mousse/u-boot.lds.ram +++ b/board/mousse/u-boot.lds.ram @@ -22,11 +22,12 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); MEMORY { - ram (!rx) : org = 0x00000000 , LENGTH = 8M - code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000) - rom (rx) : org = 0xfff00000 , LENGTH = 512K + ram (!rx) : org = 0x00000000 , LENGTH = 8M + code (!rx) : org = 0x00002000 , LENGTH = (4M - 0x2000) + rom (rx) : org = 0xfff00000 , LENGTH = 512K } SECTIONS diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom index 3ba7c3c9a..5a5722e81 100644 --- a/board/mousse/u-boot.lds.rom +++ b/board/mousse/u-boot.lds.rom @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/mp2usb/Makefile b/board/mp2usb/Makefile index 67efd725d..b6ea3cf47 100644 --- a/board/mp2usb/Makefile +++ b/board/mp2usb/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := mp2usb.o flash.o +OBJS := mp2usb.o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/mp2usb/flash.c b/board/mp2usb/flash.c index c19d445e2..89ced163b 100644 --- a/board/mp2usb/flash.c +++ b/board/mp2usb/flash.c @@ -426,7 +426,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr); + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); return (2); } /* diff --git a/board/mp2usb/mp2usb.c b/board/mp2usb/mp2usb.c index dcda699dc..486d44c20 100644 --- a/board/mp2usb/mp2usb.c +++ b/board/mp2usb/mp2usb.c @@ -61,7 +61,7 @@ int dram_init (void) } #ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) /* * Name: @@ -81,5 +81,5 @@ void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) p_phyops->AutoNegotiate = dm9161_AutoNegotiate; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ #endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/mp2usb/u-boot.lds b/board/mp2usb/u-boot.lds index 3b7977672..76df6b2af 100644 --- a/board/mp2usb/u-boot.lds +++ b/board/mp2usb/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/mpc8260ads/Makefile b/board/mpc8260ads/Makefile new file mode 100644 index 000000000..cc519d1e2 --- /dev/null +++ b/board/mpc8260ads/Makefile @@ -0,0 +1,47 @@ + +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8260ads/config.mk b/board/mpc8260ads/config.mk new file mode 100644 index 000000000..eb6f7c9d1 --- /dev/null +++ b/board/mpc8260ads/config.mk @@ -0,0 +1,37 @@ +# +# (C) Copyright 2001-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com +# +# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8260ADS, MPC8266ADS, and PQ2FADS-ZU/VR boards +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +endif diff --git a/board/mpc8260ads/flash.c b/board/mpc8260ads/flash.c new file mode 100644 index 000000000..59997aac4 --- /dev/null +++ b/board/mpc8260ads/flash.c @@ -0,0 +1,492 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Add support the Sharp chips on the mpc8260ads. + * I started with board/ip860/flash.c and made changes I found in + * the MTD project by David Schleef. + * + * (C) Copyright 2003 Arabella Software Ltd. + * Yuli Barcohen + * Re-written to support multi-bank flash SIMMs. + * Added support for real protection and JFFS2. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* Intel-compatible flash ID */ +#define INTEL_COMPAT 0x89898989 +#define INTEL_ALT 0xB0B0B0B0 + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x10101010 +#define INTEL_ERASE 0x20202020 +#define INTEL_CLEAR 0x50505050 +#define INTEL_LOCKBIT 0x60606060 +#define INTEL_PROTECT 0x01010101 +#define INTEL_STATUS 0x70707070 +#define INTEL_READID 0x90909090 +#define INTEL_CONFIRM 0xD0D0D0D0 +#define INTEL_RESET 0xFFFFFFFF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x80808080 +#define INTEL_OK 0x80808080 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.) + * Up to 32MB of flash supported (up to 4 banks.) + * BCSR is used for flash presence detect (page 4-65 of the User's Manual) + * + * The following code can not run from flash! + */ +unsigned long flash_init (void) +{ + ulong size = 0, sect_start, sect_size = 0, bank_size; + ushort sect_count = 0; + int i, j, nbanks; + vu_long *addr = (vu_long *)CFG_FLASH_BASE; + vu_long *bcsr = (vu_long *)CFG_BCSR; + + switch (bcsr[2] & 0xF) { + case 0: + nbanks = 4; + break; + case 1: + nbanks = 2; + break; + case 2: + nbanks = 1; + break; + default: /* Unsupported configurations */ + nbanks = CFG_MAX_FLASH_BANKS; + } + + if (nbanks > CFG_MAX_FLASH_BANKS) + nbanks = CFG_MAX_FLASH_BANKS; + + for (i = 0; i < nbanks; i++) { + *addr = INTEL_READID; /* Read Intelligent Identifier */ + if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) { + switch (addr[1]) { + case SHARP_ID_28F016SCL: + case SHARP_ID_28F016SCZ: + flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; + sect_count = 32; + sect_size = 0x40000; + break; + default: + flash_info[i].flash_id = FLASH_UNKNOWN; + sect_count = CFG_MAX_FLASH_SECT; + sect_size = + CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT; + } + } + else + flash_info[i].flash_id = FLASH_UNKNOWN; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n", + addr[0], addr[1], (ulong)addr); + size = 0; + *addr = INTEL_RESET; /* Reset bank to Read Array mode */ + break; + } + flash_info[i].sector_count = sect_count; + flash_info[i].size = bank_size = sect_size * sect_count; + size += bank_size; + sect_start = (ulong)addr; + for (j = 0; j < sect_count; j++) { + addr = (vu_long *)sect_start; + flash_info[i].start[j] = sect_start; + flash_info[i].protect[j] = (addr[2] == 0x01010101); + sect_start += sect_size; + } + *addr = INTEL_RESET; /* Reset bank to Read Array mode */ + addr = (vu_long *)sect_start; + } + + if (size == 0) { /* Unknown flash, fill with hard-coded values */ + sect_start = CFG_FLASH_BASE; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS; + flash_info[i].sector_count = sect_count; + for (j = 0; j < sect_count; j++) { + flash_info[i].start[j] = sect_start; + flash_info[i].protect[j] = 0; + sect_start += sect_size; + } + } + size = CFG_FLASH_SIZE; + } + else + for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].size = 0; + flash_info[i].sector_count = 0; + } + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_SHARP: printf ("Sharp "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); + break; + case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); + break; + case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); + break; + case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) + && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + + last = start = get_timer (0); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Clear Status Register */ + *addr = INTEL_CLEAR; + /* Single Block Erase Command */ + *addr = INTEL_ERASE; + /* Confirm */ + *addr = INTEL_CONFIRM; + + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr = INTEL_CONFIRM; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = INTEL_RESET; /* reset bank */ + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + if (*addr != INTEL_OK) { + printf("Block erase failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + *addr = INTEL_RESET; /* reset bank */ + return 1; + } + + /* reset to read mode */ + *addr = INTEL_RESET; + } + } + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + ulong start; + int rc = 0; + int flag; + vu_long *addr = (vu_long *)dest; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + + *addr = INTEL_CLEAR; /* Clear status register */ + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = INTEL_PROGRAM; + + /* Write Data */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + printf("Write timed out\n"); + rc = 1; + break; + } + } + if (*addr != INTEL_OK) { + printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr); + rc = 1; + } + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + rc = write_word(info, wp, data); + + return rc; +} + +/*----------------------------------------------------------------------- + * Set/Clear sector's lock bit, returns: + * 0 - OK + * 1 - Error (timeout, voltage problems, etc.) + */ +int flash_real_protect(flash_info_t *info, long sector, int prot) +{ + ulong start; + int i; + int rc = 0; + vu_long *addr = (vu_long *)(info->start[sector]); + int flag = disable_interrupts(); + + *addr = INTEL_CLEAR; /* Clear status register */ + if (prot) { /* Set sector lock bit */ + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + } + else { /* Clear sector lock bit */ + *addr = INTEL_LOCKBIT; /* All sectors lock bits */ + *addr = INTEL_CONFIRM; /* clear */ + } + + start = get_timer(0); + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + printf("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + + if (*addr != INTEL_OK) { + printf("Flash lock bit operation failed at %08X, CSR=%08X\n", + (uint)addr, (uint)*addr); + rc = 1; + } + + if (!rc) + info->protect[sector] = prot; + + /* + * Clear lock bit command clears all sectors lock bits, so + * we have to restore lock bits of protected sectors. + */ + if (!prot) + for (i = 0; i < info->sector_count; i++) + if (info->protect[i]) { + addr = (vu_long *)(info->start[i]); + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + udelay(CFG_FLASH_LOCK_TOUT * 1000); + } + + if (flag) + enable_interrupts(); + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c new file mode 100644 index 000000000..93550e2ad --- /dev/null +++ b/board/mpc8260ads/mpc8260ads.c @@ -0,0 +1,546 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified during 2001 by + * Advanced Communications Technologies (Australia) Pty. Ltd. + * Howard Walker, Tuong Vu-Dinh + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Added support for the 16M dram simm on the 8260ads boards + * + * (C) Copyright 2003-2004 Arabella Software Ltd. + * Yuli Barcohen + * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init. + * + * Copyright (c) 2005 MontaVista Software, Inc. + * Vitaly Bordug + * Added support for PCI. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_PCI +#include +#endif + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) +#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3) + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */ + /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */ + /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ +#if CONFIG_ADSTYPE == CFG_8272ADS + /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */ + /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */ +#else + /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ + /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ +#if CONFIG_ADSTYPE == CFG_8272ADS + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ +#else + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ +#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +void reset_phy (void) +{ + vu_long *bcsr = (vu_long *)CFG_BCSR; + + /* Reset the PHY */ +#if CFG_PHY_ADDR == 0 + bcsr[1] &= ~(FETHIEN1 | FETH1_RST); + udelay(2); + bcsr[1] |= FETH1_RST; +#else + bcsr[3] &= ~(FETHIEN2 | FETH2_RST); + udelay(2); + bcsr[3] |= FETH2_RST; +#endif /* CFG_PHY_ADDR == 0 */ + udelay(1000); +#ifdef CONFIG_MII +#if CONFIG_ADSTYPE >= CFG_PQ2FADS + /* + * Do not bypass Rx/Tx (de)scrambler (fix configuration error) + * Enable autonegotiation. + */ + bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610); + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#else + /* + * Ethernet PHY is configured (by means of configuration pins) + * to work at 10Mb/s only. We reconfigure it using MII + * to advertise all capabilities, including 100Mb/s, and + * restart autonegotiation. + */ + + /* Advertise all capabilities */ + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1); + + /* Do not bypass Rx/Tx (de)scrambler */ + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000); + + bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ +#endif /* CONFIG_MII */ +} + +#ifdef CONFIG_PCI +typedef struct pci_ic_s { + unsigned long pci_int_stat; + unsigned long pci_int_mask; +}pci_ic_t; +#endif + +int board_early_init_f (void) +{ + vu_long *bcsr = (vu_long *)CFG_BCSR; + +#ifdef CONFIG_PCI + volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT; + + /* mask alll the PCI interrupts */ + pci_ic->pci_int_mask |= 0xfff00000; +#endif +#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1) + bcsr[1] &= ~RS232EN_1; +#endif +#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1) + bcsr[1] &= ~RS232EN_2; +#endif + +#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */ +#if CONFIG_ADSTYPE == CFG_PQ2FADS + if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */ +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + { + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; + immap->im_siu_conf.sc_siumcr = + (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) + | SIUMCR_LBPC01; + } +#endif /* CONFIG_ADSTYPE != CFG_8260ADS */ + + return 0; +} + +#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1) + +long int initdram (int board_type) +{ +#if CONFIG_ADSTYPE == CFG_PQ2FADS + long int msize = 32; +#elif CONFIG_ADSTYPE == CFG_8272ADS + long int msize = 64; +#else + long int msize = 16; +#endif + +#ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar *ramaddr, c = 0xff; + uint or; + uint psdmr; + uint psrt; + + int i; + + immap->im_siu_conf.sc_ppc_acr = 0x00000002; + immap->im_siu_conf.sc_ppc_alrh = 0x01267893; + immap->im_siu_conf.sc_tescr1 = 0x00004000; + + memctl->memc_mptpr = CFG_MPTPR; +#ifdef CFG_LSDRAM_BASE + /* + Initialise local bus SDRAM only if the pins + are configured as local bus pins and not as PCI. + The configuration is determined by the HRCW. + */ + if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { + memctl->memc_lsrt = CFG_LSRT; +#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */ + memctl->memc_or3 = 0xFF803280; + memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861; +#else /* CS4 */ + memctl->memc_or4 = 0xFFC01480; + memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; +#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ + memctl->memc_lsdmr = CFG_LSDMR | 0x28000000; + ramaddr = (uchar *) CFG_LSDRAM_BASE; + *ramaddr = c; + memctl->memc_lsdmr = CFG_LSDMR | 0x08000000; + for (i = 0; i < 8; i++) + *ramaddr = c; + memctl->memc_lsdmr = CFG_LSDMR | 0x18000000; + *ramaddr = c; + memctl->memc_lsdmr = CFG_LSDMR | 0x40000000; + } +#endif /* CFG_LSDRAM_BASE */ + + /* Init 60x bus SDRAM */ +#ifdef CONFIG_SPD_EEPROM + { + spd_eeprom_t spd; + uint pbi, bsel, rowst, lsb, tmp; + + i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd)); + + /* Bank-based interleaving is not supported for physical bank + sizes greater than 128MB which is encoded as 0x20 in SPD + */ + pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI; + msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */ + or = ~(msize - 1) << 20; /* SDAM */ + switch (spd.nbanks) { /* BPD */ + case 2: + bsel = 1; + break; + case 4: + bsel = 2; + or |= 0x00002000; + break; + case 8: + bsel = 3; + or |= 0x00004000; + break; + } + lsb = 3; /* For 64-bit port, lsb is 3 bits */ + + if (pbi) { /* Bus partition depends on interleaving */ + rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb); + or |= (rowst << 9); /* ROWST */ + } else { + rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb); + or |= ((rowst * 2 - 12) << 9); /* ROWST */ + } + or |= ((spd.nrow_addr - 9) << 6); /* NUMR */ + + psdmr = (pbi << 31); /* PBI */ + /* Bus multiplexing parameters */ + tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */ + psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */ + psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */ + + tmp = (31 - lsb - 10) - tmp; + /* Pin connected to SDA10 is (31 - lsb - 10). + rowst is multiplexed over (32 - (lsb + spd.nrow_addr)), + so (rowst + tmp) alternates with AP. + */ + if (pbi) /* Table 10-7 */ + psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */ + else + psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */ + + /* SDRAM device-specific parameters */ + tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */ + switch (tmp) { /* RFRC */ + case 1: + case 2: + psdmr |= (1 << 15); + break; + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + psdmr |= ((tmp - 2) << 15); + break; + default: + psdmr |= (7 << 15); + } + psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */ + psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */ + /* BL=0 because for 64-bit SDRAM burst length must be 4 */ + /* LDOTOPRE ??? */ + for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++) + tmp >>= 1; + switch (i) { /* WRC */ + case 0: + case 1: + psdmr |= (1 << 4); + break; + case 2: + case 3: + psdmr |= (i << 4); + break; + } + /* EAMUX=0 - no external address multiplexing */ + /* BUFCMD=0 - no external buffers */ + for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++) + tmp >>= 1; + psdmr |= i; /* CL */ + + switch (spd.refresh & 0x7F) { + case 1: + tmp = 3900; + break; + case 2: + tmp = 7800; + break; + case 3: + tmp = 31300; + break; + case 4: + tmp = 62500; + break; + case 5: + tmp = 125000; + break; + default: + tmp = 15625; + } + psrt = tmp / (1000000000 / CONFIG_8260_CLKIN * + ((memctl->memc_mptpr >> 8) + 1)) - 1; +#ifdef SPD_DEBUG + printf ("\nDIMM type: %-18.18s\n", spd.mpart); + printf ("SPD size: %d\n", spd.info_size); + printf ("EEPROM size: %d\n", 1 << spd.chip_size); + printf ("Memory type: %d\n", spd.mem_type); + printf ("Row addr: %d\n", spd.nrow_addr); + printf ("Column addr: %d\n", spd.ncol_addr); + printf ("# of rows: %d\n", spd.nrows); + printf ("Row density: %d\n", spd.row_dens); + printf ("# of banks: %d\n", spd.nbanks); + printf ("Data width: %d\n", + 256 * spd.dataw_msb + spd.dataw_lsb); + printf ("Chip width: %d\n", spd.primw); + printf ("Refresh rate: %02X\n", spd.refresh); + printf ("CAS latencies: %02X\n", spd.cas_lat); + printf ("Write latencies: %02X\n", spd.write_lat); + printf ("tRP: %d\n", spd.trp); + printf ("tRCD: %d\n", spd.trcd); + + printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt); +#endif /* SPD_DEBUG */ + } +#else /* !CONFIG_SPD_EEPROM */ + or = CFG_OR2; + psdmr = CFG_PSDMR; + psrt = CFG_PSRT; +#endif /* CONFIG_SPD_EEPROM */ + memctl->memc_psrt = psrt; + memctl->memc_or2 = or; + memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041; + ramaddr = (uchar *) CFG_SDRAM_BASE; + memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */ + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */ + *ramaddr = c; +#endif /* CFG_RAMBOOT */ + + /* return total 60x bus SDRAM size */ + return (msize * 1024 * 1024); +} + +int checkboard (void) +{ +#if CONFIG_ADSTYPE == CFG_8260ADS + puts ("Board: Motorola MPC8260ADS\n"); +#elif CONFIG_ADSTYPE == CFG_8266ADS + puts ("Board: Motorola MPC8266ADS\n"); +#elif CONFIG_ADSTYPE == CFG_PQ2FADS + puts ("Board: Motorola PQ2FADS-ZU\n"); +#elif CONFIG_ADSTYPE == CFG_8272ADS + puts ("Board: Motorola MPC8272ADS\n"); +#else + puts ("Board: unknown\n"); +#endif + return 0; +} + +#ifdef CONFIG_PCI +struct pci_controller hose; + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif diff --git a/board/mpc8260ads/u-boot.lds b/board/mpc8260ads/u-boot.lds new file mode 100644 index 000000000..bf8048d27 --- /dev/null +++ b/board/mpc8260ads/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/mpc8266ads/Makefile b/board/mpc8266ads/Makefile new file mode 100644 index 000000000..cd0f40bcd --- /dev/null +++ b/board/mpc8266ads/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8266ads/config.mk b/board/mpc8266ads/config.mk new file mode 100644 index 000000000..ecc2a7db6 --- /dev/null +++ b/board/mpc8266ads/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Stuart Hughes, Lineo Inc, stuarth@lineo.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8260ads board +# + +TEXT_BASE = 0xfe000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/mpc8266ads/flash.c b/board/mpc8266ads/flash.c new file mode 100644 index 000000000..9512c72a0 --- /dev/null +++ b/board/mpc8266ads/flash.c @@ -0,0 +1,509 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Add support the Sharp chips on the mpc8260ads. + * I started with board/ip860/flash.c and made changes I found in + * the MTD project by David Schleef. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static int clear_block_lock_bit(vu_long * addr); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ +#ifndef CONFIG_MPC8266ADS + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; +#endif + unsigned long size; + int i; + + /* Init: enable write, + * or we cannot even write flash commands + */ +#ifndef CONFIG_MPC8266ADS + bcsr->bd_ctrl |= BD_CTRL_FLWE; +#endif + + + for (i=0; imemc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) | + (memctl->memc_br1 & ~(BR_BA_MSK)); +#endif + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_SHARP: printf ("Sharp "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); + break; + case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); + break; + case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); + break; + case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + ulong sector_offset; + + /* Write "Intelligent Identifier" command: read Manufacturer ID */ + *addr = 0x90909090; + + value = addr[0] & 0x00FF00FF; + switch (value) { + case MT_MANUFACT: /* SHARP, MT or => Intel */ + case INTEL_ALT_MANU: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + printf("unknown manufacturer: %x\n", (unsigned int)value); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + switch (value) { + case (INTEL_ID_28F016S): + info->flash_id += FLASH_28F016SV; + info->sector_count = 32; + info->size = 0x00400000; + sector_offset = 0x20000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F160S3): + info->flash_id += FLASH_28F160S3; + info->sector_count = 32; + info->size = 0x00400000; + sector_offset = 0x20000; + break; /* => 2x2 MB */ + + case (INTEL_ID_28F320S3): + info->flash_id += FLASH_28F320S3; + info->sector_count = 64; + info->size = 0x00800000; + sector_offset = 0x20000; + break; /* => 2x4 MB */ + + case SHARP_ID_28F016SCL: + case SHARP_ID_28F016SCZ: + info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; + info->sector_count = 32; + info->size = 0x00800000; + sector_offset = 0x40000; + break; /* => 4x2 MB */ + + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += sector_offset; + /* don't know how to check sector protection */ + info->protect[i] = 0; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_long *)info->start[0]; + + *addr = 0xFFFFFF; /* reset bank to read array mode */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) + && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + /* Make Sure Block Lock Bit is not set. */ + if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ + return 1; + } + + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_long *addr = (vu_long *)(info->start[sect]); + + last = start = get_timer (0); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Reset Array */ + *addr = 0xffffffff; + /* Clear Status Register */ + *addr = 0x50505050; + /* Single Block Erase Command */ + *addr = 0x20202020; + /* Confirm */ + *addr = 0xD0D0D0D0; + + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr = 0xD0D0D0D0; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + while ((*addr & 0x80808080) != 0x80808080) { + if(*addr & 0x20202020){ + printf("Error in Block Erase - Lock Bit may be set!\n"); + printf("Status Register = 0x%X\n", (uint)*addr); + *addr = 0xFFFFFFFF; /* reset bank */ + return 1; + } + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + + /* reset to read mode */ + *addr = 0xFFFFFFFF; + } + } + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong start, csr; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = 0x10101010; + + /* Write Data */ + *addr = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + flag = 0; + while (((csr = *addr) & 0x80808080) != 0x80808080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x40404040) { + printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + + /* Clear Status Registers Command */ + *addr = 0x50505050; + /* Reset to read array mode */ + *addr = 0xFFFFFFFF; + + return (flag); +} + +/*----------------------------------------------------------------------- + * Clear Block Lock Bit, returns: + * 0 - OK + * 1 - Timeout + */ + +static int clear_block_lock_bit(vu_long * addr) +{ + ulong start, now; + + /* Reset Array */ + *addr = 0xffffffff; + /* Clear Status Register */ + *addr = 0x50505050; + + *addr = 0x60606060; + *addr = 0xd0d0d0d0; + + start = get_timer (0); + while(*addr != 0x80808080){ + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout on clearing Block Lock Bit\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + return 1; + } + } + return 0; +} diff --git a/board/mpc8266ads/mpc8266ads.c b/board/mpc8266ads/mpc8266ads.c new file mode 100644 index 000000000..8f7273c41 --- /dev/null +++ b/board/mpc8266ads/mpc8266ads.c @@ -0,0 +1,586 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified during 2001 by + * Advanced Communications Technologies (Australia) Pty. Ltd. + * Howard Walker, Tuong Vu-Dinh + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Added support for the 16M dram simm on the 8260ads boards + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* + * PBI Page Based Interleaving + * PSDMR_PBI page based interleaving + * 0 bank based interleaving + * External Address Multiplexing (EAMUX) adds a clock to address cycles + * (this can help with marginal board layouts) + * PSDMR_EAMUX adds a clock + * 0 no extra clock + * Buffer Command (BUFCMD) adds a clock to command cycles. + * PSDMR_BUFCMD adds a clock + * 0 no extra clock + */ +#define CONFIG_PBI 0 +#define PESSIMISTIC_SDRAM 0 +#define EAMUX 0 /* EST requires EAMUX */ +#define BUFCMD 0 + + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +typedef struct bscr_ { + unsigned long bcsr0; + unsigned long bcsr1; + unsigned long bcsr2; + unsigned long bcsr3; + unsigned long bcsr4; + unsigned long bcsr5; + unsigned long bcsr6; + unsigned long bcsr7; +} bcsr_t; + +typedef struct pci_ic_s { + unsigned long pci_int_stat; + unsigned long pci_int_mask; +} pci_ic_t; + +void reset_phy(void) +{ + volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; + + /* reset the FEC port */ + bcsr->bcsr1 &= ~FETH_RST; + bcsr->bcsr1 |= FETH_RST; +} + + +int board_early_init_f (void) +{ + volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; + volatile pci_ic_t *pci_ic = (pci_ic_t *) CFG_PCI_INT; + + bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2; + + /* mask all PCI interrupts */ + pci_ic->pci_int_mask |= 0xfff00000; + + return 0; +} + +int checkboard(void) +{ + puts ("Board: Motorola MPC8266ADS\n"); + return 0; +} + +long int initdram(int board_type) +{ + /* Autoinit part stolen from board/sacsng/sacsng.c */ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + volatile uchar c = 0xff; + volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8); + uint psdmr = CFG_PSDMR; + int i; + + uint psrt = 0x21; /* for no SPD */ + uint chipselects = 1; /* for no SPD */ + uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ + uint or = CFG_OR2_PRELIM; /* for no SPD */ + uint data_width; + uint rows; + uint banks; + uint cols; + uint caslatency; + uint width; + uint rowst; + uint sdam; + uint bsma; + uint sda10; + u_char spd_size; + u_char data; + u_char cksum; + int j; + + /* Keep the compiler from complaining about potentially uninitialized vars */ + data_width = rows = banks = cols = caslatency = 0; + + /* + * Read the SDRAM SPD EEPROM via I2C. + */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); + spd_size = data; + cksum = data; + for(j = 1; j < 64; j++) + { /* read only the checksummed bytes */ + /* note: the I2C address autoincrements when alen == 0 */ + i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1); + /*printf("addr %d = 0x%02x\n", j, data);*/ + if(j == 5) chipselects = data & 0x0F; + else if(j == 6) data_width = data; + else if(j == 7) data_width |= data << 8; + else if(j == 3) rows = data & 0x0F; + else if(j == 4) cols = data & 0x0F; + else if(j == 12) + { + /* + * Refresh rate: this assumes the prescaler is set to + * approximately 0.39uSec per tick and the target refresh period + * is about 85% of maximum. + */ + switch(data & 0x7F) + { + default: + case 0: psrt = 0x21; /* 15.625uS */ break; + case 1: psrt = 0x07; /* 3.9uS */ break; + case 2: psrt = 0x0F; /* 7.8uS */ break; + case 3: psrt = 0x43; /* 31.3uS */ break; + case 4: psrt = 0x87; /* 62.5uS */ break; + case 5: psrt = 0xFF; /* 125uS */ break; + } + } + else if(j == 17) banks = data; + else if(j == 18) + { + caslatency = 3; /* default CL */ +# if(PESSIMISTIC_SDRAM) + if((data & 0x04) != 0) caslatency = 3; + else if((data & 0x02) != 0) caslatency = 2; + else if((data & 0x01) != 0) caslatency = 1; +# else + if((data & 0x01) != 0) caslatency = 1; + else if((data & 0x02) != 0) caslatency = 2; + else if((data & 0x04) != 0) caslatency = 3; +# endif + else + { + printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n", + data); + } + } + else if(j == 63) + { + if(data != cksum) + { + printf ("WARNING: Configuration data checksum failure:" + " is 0x%02x, calculated 0x%02x\n", + data, cksum); + } + } + cksum += data; + } + + /* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */ + if(caslatency < 2) { + printf("CL was %d, forcing to 2\n", caslatency); + caslatency = 2; + } + if(rows > 14) { + printf("This doesn't look good, rows = %d, should be <= 14\n", rows); + rows = 14; + } + if(cols > 11) { + printf("This doesn't look good, columns = %d, should be <= 11\n", cols); + cols = 11; + } + + if((data_width != 64) && (data_width != 72)) + { + printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n", + data_width); + } + width = 3; /* 2^3 = 8 bytes = 64 bits wide */ + /* + * Convert banks into log2(banks) + */ + if (banks == 2) banks = 1; + else if(banks == 4) banks = 2; + else if(banks == 8) banks = 3; + + + sdram_size = 1 << (rows + cols + banks + width); + /* hack for high density memory (512MB per CS) */ + /* !!!!! Will ONLY work with Page Based Interleave !!!!! + ( PSDMR[PBI] = 1 ) + */ + /* mamory actually has 11 column addresses, but the memory controller + doesn't really care. + the calculations that follow will however move the rows so that + they are muxed one bit off if you use 11 bit columns. + The solution is to tell the memory controller the correct size of the memory + but change the number of columns to 10 afterwards. + The 11th column addre will still be mucxed correctly onto the bus. + + Also be aware that the MPC8266ADS board Rev B has not connected + Row addres 13 to anything. + + The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126) + */ + if (cols > 10) + cols = 10; + +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + rowst = ((32 - 6) - (rows + cols + width)) * 2; +#else + rowst = 32 - (rows + banks + cols + width); +#endif + + or = ~(sdram_size - 1) | /* SDAM address mask */ + ((banks-1) << 13) | /* banks per device */ + (rowst << 9) | /* rowst */ + ((rows - 9) << 6); /* numr */ + + + /*printf("memctl->memc_or2 = 0x%08x\n", or);*/ + + /* + * SDAM specifies the number of columns that are multiplexed + * (reference AN2165/D), defined to be (columns - 6) for page + * interleave, (columns - 8) for bank interleave. + * + * BSMA is 14 - max(rows, cols). The bank select lines come + * into play above the highest "address" line going into the + * the SDRAM. + */ +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + sdam = cols - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam + 2; +#else + sdam = cols + banks - 8; + bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols); + sda10 = sdam; +#endif +#if(PESSIMISTIC_SDRAM) + psdmr = (CONFIG_PBI |\ + PSDMR_RFEN |\ + PSDMR_RFRC_16_CLK |\ + PSDMR_PRETOACT_8W |\ + PSDMR_ACTTORW_8W |\ + PSDMR_WRC_4C |\ + PSDMR_EAMUX |\ + PSDMR_BUFCMD) |\ + caslatency |\ + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ + (sdam << 24) |\ + (bsma << 21) |\ + (sda10 << 18); +#else + psdmr = (CONFIG_PBI |\ + PSDMR_RFEN |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \ + PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \ + PSDMR_WRC_1C | /* 1 clock + 7nSec */ + EAMUX |\ + BUFCMD) |\ + caslatency |\ + ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \ + (sdam << 24) |\ + (bsma << 21) |\ + (sda10 << 18); +#endif + /*printf("psdmr = 0x%08x\n", psdmr);*/ + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * Quote from Micron MT48LC8M16A2 data sheet: + * + * "...the SDRAM requires a 100uS delay prior to issuing any + * command other than a COMMAND INHIBIT or NOP. Starting at some + * point during this 100uS period and continuing at least through + * the end of this period, COMMAND INHIBIT or NOP commands should + * be applied." + * + * "Once the 100uS delay has been satisfied with at least one COMMAND + * INHIBIT or NOP command having been applied, a /PRECHARGE command/ + * should be applied. All banks must then be precharged, thereby + * placing the device in the all banks idle state." + * + * "Once in the idle state, /two/ AUTO REFRESH cycles must be + * performed. After the AUTO REFRESH cycles are complete, the + * SDRAM is ready for mode register programming." + * + * (/emphasis/ mine, gvb) + * + * The way I interpret this, Micron start up sequence is: + * 1. Issue a PRECHARGE-BANK command (initial precharge) + * 2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged") + * 3. Issue two (presumably, doing eight is OK) CBR REFRESH commands + * 4. Issue a MODE-SET command to initialize the mode register + * + * -------- + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = psrt; + + memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = or; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + + /* + * Do it a second time for the second set of chips if the DIMM has + * two chip selects (double sided). + */ + if(chipselects > 1) + { + ramaddr += sdram_size; + + memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size; + memctl->memc_or3 = or; + + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; + *ramaddr = c; + + memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *ramaddr = c; + } + + /* print info */ + printf("SDRAM configuration read from SPD\n"); + printf("\tSize per side = %dMB\n", sdram_size >> 20); + printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width); + printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency); +#if(CONFIG_PBI == 0) /* bank-based interleaving */ + printf(", Using Bank Based Interleave\n"); +#else + printf(", Using Page Based Interleave\n"); +#endif + printf("\tTotal size: "); + + /* this delay only needed for original 16MB DIMM... + * Not needed for any other memory configuration */ + if ((sdram_size * chipselects) == (16 *1024 *1024)) + udelay (250000); + return (sdram_size * chipselects); + /*return (16 * 1024 * 1024);*/ +} + + +#ifdef CONFIG_PCI +struct pci_controller hose; + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif diff --git a/board/mpc8266ads/u-boot.lds b/board/mpc8266ads/u-boot.lds new file mode 100644 index 000000000..2220758cb --- /dev/null +++ b/board/mpc8266ads/u-boot.lds @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpc8349ads/Makefile b/board/mpc8349ads/Makefile new file mode 100644 index 000000000..4327b0d3e --- /dev/null +++ b/board/mpc8349ads/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8349ads/config.mk b/board/mpc8349ads/config.mk new file mode 100644 index 000000000..4602169ec --- /dev/null +++ b/board/mpc8349ads/config.mk @@ -0,0 +1,27 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC83xxADS +# + +TEXT_BASE = 0xFE700000 diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c new file mode 100644 index 000000000..da8d3d7e8 --- /dev/null +++ b/board/mpc8349ads/mpc8349ads.c @@ -0,0 +1,276 @@ +/* + * Copyright Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_PCI) +#include +#endif +#if defined(CONFIG_SPD_EEPROM) +#include +#endif +int fixed_sdram(void); +void sdram_init(void); + +int board_early_init_f (void) +{ + volatile u8* bcsr = (volatile u8*)CFG_BCSR; + + /* Enable flash write */ + bcsr[1] &= ~0x01; + + return 0; +} + + +#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) + +long int initdram (int board_type) +{ + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(NULL); +#else + msize = fixed_sdram(); +#endif + /* + * Initialize SDRAM if it is on local bus. + */ + sdram_init(); + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size>>1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); +#if (CFG_DDR_SIZE != 256) +#warning Currenly any ddr size other than 256 is not supported +#endif + + im->ddr.csbnds[0].csbnds = 0x00100017; + im->ddr.csbnds[1].csbnds = 0x0018001f; + im->ddr.csbnds[2].csbnds = 0x00000007; + im->ddr.csbnds[3].csbnds = 0x0008000f; + im->ddr.cs_config[0] = CFG_DDR_CONFIG; + im->ddr.cs_config[1] = CFG_DDR_CONFIG; + im->ddr.cs_config[2] = CFG_DDR_CONFIG; + im->ddr.cs_config[3] = CFG_DDR_CONFIG; + im->ddr.timing_cfg_1 = + 3 << TIMING_CFG1_PRETOACT_SHIFT | + 7 << TIMING_CFG1_ACTTOPRE_SHIFT | + 3 << TIMING_CFG1_ACTTORW_SHIFT | + 4 << TIMING_CFG1_CASLAT_SHIFT | + 3 << TIMING_CFG1_REFREC_SHIFT | + 3 << TIMING_CFG1_WRREC_SHIFT | + 2 << TIMING_CFG1_ACTTOACT_SHIFT | + 1 << TIMING_CFG1_WRTORD_SHIFT; + im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT; + im->ddr.sdram_cfg = + SDRAM_CFG_SREN +#if defined(CONFIG_DDR_2T_TIMING) + | SDRAM_CFG_2T_EN +#endif + | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; + im->ddr.sdram_mode = + 0x2000 << SDRAM_MODE_ESD_SHIFT | + 0x0162 << SDRAM_MODE_SD_SHIFT; + + im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT | + 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT; + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} +#endif/*!CFG_SPD_EEPROM*/ + + +int checkboard (void) +{ + puts("Board: Freescale MPC8349ADS\n"); + return 0; +} + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxads_config_table[] = { + {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMON_MEMORY | PCI_COMMAND_MASTER + } }, + {} +} +#endif + + +volatile static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxads_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxads_config_table, +#endif + } +}; +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc83xx_init(volatile struct pci_controller *hose); + + pci_mpc83xx_init(hose); +#endif /* CONFIG_PCI */ +} + +/* + * if MPC8349ADS is soldered with SDRAM + */ +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void +sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile lbus8349_t *lbc= &immap->lbus; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts("\n SDRAM on Local Bus: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers, already done in cpu_init.c + */ + + /*setup mtrpt, lsrt and lbcr for LB bus*/ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + + /* + * Configure the SDRAM controller Machine Mode Register. + */ + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/ + + lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/ + asm("sync"); + /*1 times*/ + *sdram_addr = 0xff; + udelay(100); + /*2 times*/ + *sdram_addr = 0xff; + udelay(100); + /*3 times*/ + *sdram_addr = 0xff; + udelay(100); + /*4 times*/ + *sdram_addr = 0xff; + udelay(100); + /*5 times*/ + *sdram_addr = 0xff; + udelay(100); + /*6 times*/ + *sdram_addr = 0xff; + udelay(100); + /*7 times*/ + *sdram_addr = 0xff; + udelay(100); + /*8 times*/ + *sdram_addr = 0xff; + udelay(100); + + /* 0x58636733;mode register write operation */ + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); +} +#else +void +sdram_init(void) +{ + put("SDRAM on Local Bus is NOT available!\n"); +} +#endif diff --git a/board/mpc8349ads/u-boot.lds b/board/mpc8349ads/u-boot.lds new file mode 100644 index 000000000..020cfa66f --- /dev/null +++ b/board/mpc8349ads/u-boot.lds @@ -0,0 +1,122 @@ +/* + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/mpc8349emds/Makefile b/board/mpc8349emds/Makefile new file mode 100644 index 000000000..38bbb6732 --- /dev/null +++ b/board/mpc8349emds/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8349emds/config.mk b/board/mpc8349emds/config.mk new file mode 100644 index 000000000..edf64d150 --- /dev/null +++ b/board/mpc8349emds/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC8349EMDS +# + +TEXT_BASE = 0xFE000000 diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c new file mode 100644 index 000000000..b5ccb5360 --- /dev/null +++ b/board/mpc8349emds/mpc8349emds.c @@ -0,0 +1,566 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_SPD_EEPROM) +#include +#endif +int fixed_sdram(void); +void sdram_init(void); + +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX) +void ddr_enable_ecc(unsigned int dram_size); +#endif + +int board_early_init_f (void) +{ + volatile u8* bcsr = (volatile u8*)CFG_BCSR; + + /* Enable flash write */ + bcsr[1] &= ~0x01; + +#ifdef CFG_USE_MPC834XSYS_USB_PHY + /* Use USB PHY on SYS board */ + bcsr[5] |= 0x02; +#endif + + return 0; +} + +#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) + +long int initdram (int board_type) +{ + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + puts("Initializing\n"); + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(); +#else + msize = fixed_sdram(); +#endif + /* + * Initialize SDRAM if it is on local bus. + */ + sdram_init(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(msize * 1024 * 1024); +#endif + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size>>1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); + +#if (CFG_DDR_SIZE != 256) +#warning Currenly any ddr size other than 256 is not supported +#endif + im->ddr.csbnds[2].csbnds = 0x0000000f; + im->ddr.cs_config[2] = CFG_DDR_CONFIG; + + /* currently we use only one CS, so disable the other banks */ + im->ddr.cs_config[0] = 0; + im->ddr.cs_config[1] = 0; + im->ddr.cs_config[3] = 0; + + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + + im->ddr.sdram_cfg = + SDRAM_CFG_SREN +#if defined(CONFIG_DDR_2T_TIMING) + | SDRAM_CFG_2T_EN +#endif + | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; +#if defined (CONFIG_DDR_32BIT) + /* for 32-bit mode burst length is 8 */ + im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); +#endif + im->ddr.sdram_mode = CFG_DDR_MODE; + + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + udelay(200); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + return msize; +} +#endif/*!CFG_SPD_EEPROM*/ + + +int checkboard (void) +{ + puts("Board: Freescale MPC8349EMDS\n"); + return 0; +} + +/* + * if MPC8349EMDS is soldered with SDRAM + */ +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile lbus8349_t *lbc= &immap->lbus; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts("\n SDRAM on Local Bus: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers, already done in cpu_init.c + */ + + /* setup mtrpt, lsrt and lbcr for LB bus */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + + /* + * Configure the SDRAM controller Machine Mode Register. + */ + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + + lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + asm("sync"); + /*1 times*/ + *sdram_addr = 0xff; + udelay(100); + /*2 times*/ + *sdram_addr = 0xff; + udelay(100); + /*3 times*/ + *sdram_addr = 0xff; + udelay(100); + /*4 times*/ + *sdram_addr = 0xff; + udelay(100); + /*5 times*/ + *sdram_addr = 0xff; + udelay(100); + /*6 times*/ + *sdram_addr = 0xff; + udelay(100); + /*7 times*/ + *sdram_addr = 0xff; + udelay(100); + /*8 times*/ + *sdram_addr = 0xff; + udelay(100); + + /* 0x58636733; mode register write operation */ + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); +} +#else +void sdram_init(void) +{ + put("SDRAM on Local Bus is NOT available!\n"); +} +#endif + +#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) +/* + * ECC user commands + */ +void ecc_print_status(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile ddr8349_t *ddr = &immap->ddr; + + printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF"); + + /* Interrupts */ + printf("Memory Error Interrupt Enable:\n"); + printf(" Multiple-Bit Error Interrupt Enable: %d\n", + (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0); + printf(" Single-Bit Error Interrupt Enable: %d\n", + (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0); + printf(" Memory Select Error Interrupt Enable: %d\n\n", + (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0); + + /* Error disable */ + printf("Memory Error Disable:\n"); + printf(" Multiple-Bit Error Disable: %d\n", + (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0); + printf(" Sinle-Bit Error Disable: %d\n", + (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0); + printf(" Memory Select Error Disable: %d\n\n", + (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0); + + /* Error injection */ + printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n", + ddr->data_err_inject_hi, ddr->data_err_inject_lo); + + printf("Memory Data Path Error Injection Mask ECC:\n"); + printf(" ECC Mirror Byte: %d\n", + (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0); + printf(" ECC Injection Enable: %d\n", + (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0); + printf(" ECC Error Injection Mask: 0x%02x\n\n", + ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM); + + /* SBE counter/threshold */ + printf("Memory Single-Bit Error Management (0..255):\n"); + printf(" Single-Bit Error Threshold: %d\n", + (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT); + printf(" Single-Bit Error Counter: %d\n\n", + (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT); + + /* Error detect */ + printf("Memory Error Detect:\n"); + printf(" Multiple Memory Errors: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0); + printf(" Multiple-Bit Error: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0); + printf(" Single-Bit Error: %d\n", + (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0); + printf(" Memory Select Error: %d\n\n", + (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0); + + /* Capture data */ + printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address); + printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n", + ddr->capture_data_hi, ddr->capture_data_lo); + printf("Memory Data Path Read Capture ECC: 0x%02x\n\n", + ddr->capture_ecc & CAPTURE_ECC_ECE); + + printf("Memory Error Attributes Capture:\n"); + printf(" Data Beat Number: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT); + printf(" Transaction Size: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT); + printf(" Transaction Source: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT); + printf(" Transaction Type: %d\n", + (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT); + printf(" Error Information Valid: %d\n\n", + ddr->capture_attributes & ECC_CAPT_ATTR_VLD); +} + +int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile ddr8349_t *ddr = &immap->ddr; + volatile u32 val; + u64 *addr, count, val64; + register u64 *i; + + if (argc > 4) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (argc == 2) { + if (strcmp(argv[1], "status") == 0) { + ecc_print_status(); + return 0; + } else if (strcmp(argv[1], "captureclear") == 0) { + ddr->capture_address = 0; + ddr->capture_data_hi = 0; + ddr->capture_data_lo = 0; + ddr->capture_ecc = 0; + ddr->capture_attributes = 0; + return 0; + } + } + + if (argc == 3) { + if (strcmp(argv[1], "sbecnt") == 0) { + val = simple_strtoul(argv[2], NULL, 10); + if (val > 255) { + printf("Incorrect Counter value, should be 0..255\n"); + return 1; + } + + val = (val << ECC_ERROR_MAN_SBEC_SHIFT); + val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET); + + ddr->err_sbe = val; + return 0; + } else if (strcmp(argv[1], "sbethr") == 0) { + val = simple_strtoul(argv[2], NULL, 10); + if (val > 255) { + printf("Incorrect Counter value, should be 0..255\n"); + return 1; + } + + val = (val << ECC_ERROR_MAN_SBET_SHIFT); + val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC); + + ddr->err_sbe = val; + return 0; + } else if (strcmp(argv[1], "errdisable") == 0) { + val = ddr->err_disable; + + if (strcmp(argv[2], "+sbe") == 0) { + val |= ECC_ERROR_DISABLE_SBED; + } else if (strcmp(argv[2], "+mbe") == 0) { + val |= ECC_ERROR_DISABLE_MBED; + } else if (strcmp(argv[2], "+mse") == 0) { + val |= ECC_ERROR_DISABLE_MSED; + } else if (strcmp(argv[2], "+all") == 0) { + val |= (ECC_ERROR_DISABLE_SBED | + ECC_ERROR_DISABLE_MBED | + ECC_ERROR_DISABLE_MSED); + } else if (strcmp(argv[2], "-sbe") == 0) { + val &= ~ECC_ERROR_DISABLE_SBED; + } else if (strcmp(argv[2], "-mbe") == 0) { + val &= ~ECC_ERROR_DISABLE_MBED; + } else if (strcmp(argv[2], "-mse") == 0) { + val &= ~ECC_ERROR_DISABLE_MSED; + } else if (strcmp(argv[2], "-all") == 0) { + val &= ~(ECC_ERROR_DISABLE_SBED | + ECC_ERROR_DISABLE_MBED | + ECC_ERROR_DISABLE_MSED); + } else { + printf("Incorrect err_disable field\n"); + return 1; + } + + ddr->err_disable = val; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + return 0; + } else if (strcmp(argv[1], "errdetectclr") == 0) { + val = ddr->err_detect; + + if (strcmp(argv[2], "mme") == 0) { + val |= ECC_ERROR_DETECT_MME; + } else if (strcmp(argv[2], "sbe") == 0) { + val |= ECC_ERROR_DETECT_SBE; + } else if (strcmp(argv[2], "mbe") == 0) { + val |= ECC_ERROR_DETECT_MBE; + } else if (strcmp(argv[2], "mse") == 0) { + val |= ECC_ERROR_DETECT_MSE; + } else if (strcmp(argv[2], "all") == 0) { + val |= (ECC_ERROR_DETECT_MME | + ECC_ERROR_DETECT_MBE | + ECC_ERROR_DETECT_SBE | + ECC_ERROR_DETECT_MSE); + } else { + printf("Incorrect err_detect field\n"); + return 1; + } + + ddr->err_detect = val; + return 0; + } else if (strcmp(argv[1], "injectdatahi") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + + ddr->data_err_inject_hi = val; + return 0; + } else if (strcmp(argv[1], "injectdatalo") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + + ddr->data_err_inject_lo = val; + return 0; + } else if (strcmp(argv[1], "injectecc") == 0) { + val = simple_strtoul(argv[2], NULL, 16); + if (val > 0xff) { + printf("Incorrect ECC inject mask, should be 0x00..0xff\n"); + return 1; + } + val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM); + + ddr->ecc_err_inject = val; + return 0; + } else if (strcmp(argv[1], "inject") == 0) { + val = ddr->ecc_err_inject; + + if (strcmp(argv[2], "en") == 0) + val |= ECC_ERR_INJECT_EIEN; + else if (strcmp(argv[2], "dis") == 0) + val &= ~ECC_ERR_INJECT_EIEN; + else + printf("Incorrect command\n"); + + ddr->ecc_err_inject = val; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + return 0; + } else if (strcmp(argv[1], "mirror") == 0) { + val = ddr->ecc_err_inject; + + if (strcmp(argv[2], "en") == 0) + val |= ECC_ERR_INJECT_EMB; + else if (strcmp(argv[2], "dis") == 0) + val &= ~ECC_ERR_INJECT_EMB; + else + printf("Incorrect command\n"); + + ddr->ecc_err_inject = val; + return 0; + } + } + + if (argc == 4) { + if (strcmp(argv[1], "test") == 0) { + addr = (u64 *)simple_strtoul(argv[2], NULL, 16); + count = simple_strtoul(argv[3], NULL, 16); + + if ((u32)addr % 8) { + printf("Address not alligned on double word boundary\n"); + return 1; + } + + disable_interrupts(); + icache_disable(); + + for (i = addr; i < addr + count; i++) { + /* enable injects */ + ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + + /* write memory location injecting errors */ + *i = 0x1122334455667788ULL; + __asm__ __volatile__ ("sync"); + + /* disable injects */ + ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + + /* read data, this generates ECC error */ + val64 = *i; + __asm__ __volatile__ ("sync"); + + /* disable errors for ECC */ + ddr->err_disable |= ~ECC_ERROR_ENABLE; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + + /* re-initialize memory, write the location again + * NOT injecting errors this time */ + *i = 0xcafecafecafecafeULL; + __asm__ __volatile__ ("sync"); + + /* enable errors for ECC */ + ddr->err_disable &= ECC_ERROR_ENABLE; + __asm__ __volatile__ ("sync"); + __asm__ __volatile__ ("isync"); + } + + icache_enable(); + enable_interrupts(); + + return 0; + } + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + ecc, 4, 0, do_ecc, + "ecc - support for DDR ECC features\n", + "status - print out status info\n" + "ecc captureclear - clear capture regs data\n" + "ecc sbecnt - set Single-Bit Error counter\n" + "ecc sbethr - set Single-Bit Threshold\n" + "ecc errdisable - clear/set disable Memory Error Disable, flag:\n" + " [-|+]sbe - Single-Bit Error\n" + " [-|+]mbe - Multiple-Bit Error\n" + " [-|+]mse - Memory Select Error\n" + " [-|+]all - all errors\n" + "ecc errdetectclr - clear Memory Error Detect, flag:\n" + " mme - Multiple Memory Errors\n" + " sbe - Single-Bit Error\n" + " mbe - Multiple-Bit Error\n" + " mse - Memory Select Error\n" + " all - all errors\n" + "ecc injectdatahi - set Memory Data Path Error Injection Mask High\n" + "ecc injectdatalo - set Memory Data Path Error Injection Mask Low\n" + "ecc injectecc - set ECC Error Injection Mask\n" + "ecc inject - enable/disable error injection\n" + "ecc mirror - enable/disable mirror byte\n" + "ecc test - test mem region:\n" + " - enables injects\n" + " - writes pattern injecting errors\n" + " - disables injects\n" + " - reads pattern back, generates error\n" + " - re-inits memory" +); +#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */ diff --git a/board/mpc8349emds/pci.c b/board/mpc8349emds/pci.c new file mode 100644 index 000000000..63e440557 --- /dev/null +++ b/board/mpc8349emds/pci.c @@ -0,0 +1,382 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_PCI + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc8349emds_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } + }, + {} +}; +#endif + +static struct pci_controller pci_hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349emds_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc8349emds_config_table, +#endif + } +}; + +/************************************************************************** + * + * pib_init() -- initialize the PCA9555PW IO expander on the PIB board + * + */ +void +pib_init(void) +{ + u8 val8; + /* + * Assign PIB PMC slot to desired PCI bus + */ + mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET); + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + val8 = 0; + i2c_write(0x23, 0x6, 1, &val8, 1); + i2c_write(0x23, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x23, 0x2, 1, &val8, 1); + i2c_write(0x23, 0x3, 1, &val8, 1); + + val8 = 0; + i2c_write(0x26, 0x6, 1, &val8, 1); + val8 = 0x34; + i2c_write(0x26, 0x7, 1, &val8, 1); +#if defined(PCI_64BIT) + val8 = 0xf4; /* PMC2:PCI1/64-bit */ +#elif defined(PCI_ALL_PCI1) + val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */ +#elif defined(PCI_ONE_PCI1) + val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */ +#else + val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */ +#endif + i2c_write(0x26, 0x2, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x26, 0x3, 1, &val8, 1); + val8 = 0; + i2c_write(0x27, 0x6, 1, &val8, 1); + i2c_write(0x27, 0x7, 1, &val8, 1); + val8 = 0xff; + i2c_write(0x27, 0x2, 1, &val8, 1); + val8 = 0xef; + i2c_write(0x27, 0x3, 1, &val8, 1); + asm("eieio"); + +#if defined(PCI_64BIT) + printf("PCI1: 64-bit on PMC2\n"); +#elif defined(PCI_ALL_PCI1) + printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n"); +#elif defined(PCI_ONE_PCI1) + printf("PCI1: 32-bit on PMC1\n"); + printf("PCI2: 32-bit on PMC2, PMC3\n"); +#else + printf("PCI1: 32-bit on PMC1, PMC2\n"); + printf("PCI2: 32-bit on PMC3\n"); +#endif +} + +/************************************************************************** + * pci_init_board() + * + * NOTICE: PCI2 is not currently supported + * + */ +void +pci_init_board(void) +{ + volatile immap_t * immr; + volatile clk8349_t * clk; + volatile law8349_t * pci_law; + volatile pot8349_t * pci_pot; + volatile pcictrl8349_t * pci_ctrl; + volatile pciconf8349_t * pci_conf; + u16 reg16; + u32 reg32; + u32 dev; + struct pci_controller * hose; + + immr = (immap_t *)CFG_IMMRBAR; + clk = (clk8349_t *)&immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + + hose = &pci_hose[0]; + + pib_init(); + + /* + * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode + */ + + reg32 = clk->occr; + udelay(2000); + clk->occr = 0xff000000; + udelay(2000); + + /* + * Release PCI RST Output signal + */ + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + +#ifdef CONFIG_MPC83XX_PCI2 + pci_ctrl[1].gcr = 0; + udelay(2000); + pci_ctrl[1].gcr = 1; +#endif + + /* We need to wait at least a 1sec based on PCI specs */ + { + int i; + + for (i = 0; i < 1000; ++i) + udelay (1000); + } + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI1 mem space - prefetch */ + pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI1 IO space */ + pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI1 mmio - non-prefetch mem space */ + pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM|PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MMIO_BASE, + CFG_PCI1_MMIO_PHYS, + CFG_PCI1_MMIO_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMRBAR+0x8300), + (CFG_IMMRBAR+0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); + +#ifdef CONFIG_MPC83XX_PCI2 + hose = &pci_hose[1]; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI2 mem space - prefetch */ + pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); + + /* PCI2 IO space */ + pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); + + /* PCI2 mmio - non-prefetch mem space */ + pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[1].pitar1 = 0x0; + pci_ctrl[1].pibar1 = 0x0; + pci_ctrl[1].piebar1 = 0x0; + pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); + + hose->first_busno = pci_hose[0].last_busno + 1; + hose->last_busno = 0xff; + + /* PCI memory prefetch space */ + pci_set_region(hose->regions + 0, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM|PCI_REGION_PREFETCH); + + /* PCI memory space */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MMIO_BASE, + CFG_PCI2_MMIO_PHYS, + CFG_PCI2_MMIO_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 3, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + gd->ram_size, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 4; + + pci_setup_indirect(hose, + (CFG_IMMRBAR+0x8380), + (CFG_IMMRBAR+0x8384)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + dev = PCI_BDF(hose->first_busno, 0, 0); + pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +#endif + +} + +#endif /* CONFIG_PCI */ diff --git a/board/mpc8349emds/u-boot.lds b/board/mpc8349emds/u-boot.lds new file mode 100644 index 000000000..937c87a27 --- /dev/null +++ b/board/mpc8349emds/u-boot.lds @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/mpc8540ads/Makefile b/board/mpc8540ads/Makefile new file mode 100644 index 000000000..5d8ea3494 --- /dev/null +++ b/board/mpc8540ads/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8540ads/config.mk b/board/mpc8540ads/config.mk new file mode 100644 index 000000000..92f893197 --- /dev/null +++ b/board/mpc8540ads/config.mk @@ -0,0 +1,33 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8540ads board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/mpc8540ads/init.S b/board/mpc8540ads/init.S new file mode 100644 index 000000000..242cb9fbc --- /dev/null +++ b/board/mpc8540ads/init.S @@ -0,0 +1,280 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xf8000000 16K BCSR registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) + .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + .long TLB1_MAS0(1, 8, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1, 9, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c new file mode 100644 index 000000000..d0eb6904a --- /dev/null +++ b/board/mpc8540ads/mpc8540ads.c @@ -0,0 +1,344 @@ + /* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); +long int fixed_sdram(void); + + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + puts("Board: ADS\n"); + +#ifdef CONFIG_PCI + printf(" PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf(" PCI1: disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init(); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + uint temp_ddrdll = 0; + + /* + * Work around to stabilize DDR DLL + */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); + } +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM. + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize Local Bus + */ + +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr(); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + + +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void +sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc= &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts(" SDRAM: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + lbc->br2 = CFG_BR2_PRELIM; + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("sync"); + + /* + * Configure the SDRAM controller. + */ + lbc->lsdmr = CFG_LBC_LSDMR_1; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_3; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ + #ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE; + ddr->sdram_interval = CFG_DDR_INTERVAL; + #if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000000D; + ddr->err_sbe = 0x00ff0000; + #endif + asm("sync;isync;msync"); + udelay(500); + #if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + #else + ddr->sdram_cfg = CFG_DDR_CONTROL; + #endif + asm("sync; isync; msync"); + udelay(500); + #endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxads_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxads_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif /* CONFIG_PCI */ +} diff --git a/board/mpc8540ads/u-boot.lds b/board/mpc8540ads/u-boot.lds new file mode 100644 index 000000000..e7a88cfa4 --- /dev/null +++ b/board/mpc8540ads/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2002,2003, Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/mpc8540ads/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/mpc8540ads/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile index 325d6d572..6f1995e08 100644 --- a/board/mpc8540eval/Makefile +++ b/board/mpc8540eval/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,27 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o flash.o law.o tlb.o +OBJS := $(BOARD).o flash.o +#OBJS := $(BOARD).o flash.o $(BOARD)_slave.o +SOBJS := init.o +#SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/mpc8540eval/flash.c b/board/mpc8540eval/flash.c index 79eb04ca8..7300a041a 100644 --- a/board/mpc8540eval/flash.c +++ b/board/mpc8540eval/flash.c @@ -591,7 +591,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) cnt -= FLASH_BLOCK_SIZE; if (((count-cnt)>>10)>temp) { temp=(count-cnt)>>10; - printf("\r%lu KB",temp); + printf("\r%d KB",temp); } } printf("\n"); @@ -699,8 +699,7 @@ static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt) } } if (csr & 0x4040) { - printf ("CSR indicates write error (%04lx) at %08lx\n", - csr, (ulong)addr); + printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr); flag = 1; } /* Clear Status Registers Command */ @@ -757,8 +756,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data) } } if (csr & 0x4040) { - printf ("CSR indicates write error (%04lx) at %08lx\n", - csr, (ulong)addr); + printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr); flag = 1; } /* Clear Status Registers Command */ diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S new file mode 100644 index 000000000..8c2ca65a9 --- /dev/null +++ b/board/mpc8540eval/init.S @@ -0,0 +1,178 @@ +/* +* Copyright (C) 2002,2003, Motorola Inc. +* Xianghua Xiao +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include +#include + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +/* TLB1 entries configuration: */ + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + .long 0x0a /* the following data table uses a few of 16 TLB entries */ + + .long TLB1_MAS0(1,1,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + #if defined(CFG_FLASH_PORT_WIDTH_16) + .long TLB1_MAS0(1,2,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) + .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,3,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) + .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1) + #else + .long TLB1_MAS0(1,2,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M) + .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,3,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + #endif + + #if !defined(CONFIG_SPD_EEPROM) + .long TLB1_MAS0(1,4,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) + .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,5,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) + .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + #else + .long TLB1_MAS0(1,4,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,5,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + #endif + + .long TLB1_MAS0(1,6,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) + #if defined(CONFIG_RAM_AS_FLASH) + .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + #else + .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) + #endif + .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,7,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) + #ifdef CONFIG_L2_INIT_RAM + .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) + #else + .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) + #endif + .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,8,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,9,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) + .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + .long TLB1_MAS0(1,15,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + #else + .long TLB1_MAS0(1,15,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + #endif + entry_end + +/* LAW(Local Access Window) configuration: + * 0000_0000-0800_0000: DDR(128M) -or- larger + * f000_0000-f3ff_ffff: PCI(256M) + * f400_0000-f7ff_ffff: RapidIO(128M) + * f800_0000-ffff_ffff: localbus(128M) + * f800_0000-fbff_ffff: LBC SDRAM(64M) + * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M) + * fdf0_0000-fdff_ffff: CCSRBAR(1M) + * fe00_0000-ffff_ffff: Flash(32M) + * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access + * Window. + * Note: If flash is 8M at default position(last 8M),no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#if !defined(CONFIG_RAM_AS_FLASH) +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR2 0 +#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x03 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 + entry_end diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 1ac333c81..3b3c8ed26 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -26,14 +26,17 @@ #include #include #include -#include +#include + +extern long int spd_sdram (void); long int fixed_sdram (void); int board_pre_init (void) { #if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; pci->peer &= 0xffffffdf; /* disable master abort */ #endif @@ -61,17 +64,18 @@ int checkboard (void) return (0); } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long dram_size = 0; - + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc= &immap->im_lbc; sys_info_t sysinfo; uint temp_lbcdll = 0; #endif #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur= &immap->im_gur; #endif #if defined(CONFIG_DDR_DLL) @@ -134,7 +138,8 @@ phys_size_t initdram (int board_type) * enable errors */ uint *p = 0; uint i = 0; - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } @@ -217,7 +222,8 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; diff --git a/board/mpc8540eval/u-boot.lds b/board/mpc8540eval/u-boot.lds index dadfc7dee..0755d0166 100644 --- a/board/mpc8540eval/u-boot.lds +++ b/board/mpc8540eval/u-boot.lds @@ -25,6 +25,7 @@ * Boot page and reset vector is put at that end of the 512K block. */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -35,11 +36,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -55,6 +56,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) + board/mpc8540eval/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) @@ -127,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) @@ -141,6 +143,7 @@ SECTIONS .bootpg : { cpu/mpc85xx/start.o (.bootpg) + board/mpc8540eval/init.o (.bootpg) } = 0xffff . = (. & 0xFFF80000) + 0x0007FFFC; diff --git a/board/mpc8560ads/Makefile b/board/mpc8560ads/Makefile new file mode 100644 index 000000000..5d8ea3494 --- /dev/null +++ b/board/mpc8560ads/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8560ads/config.mk b/board/mpc8560ads/config.mk new file mode 100644 index 000000000..9aef2bb16 --- /dev/null +++ b/board/mpc8560ads/config.mk @@ -0,0 +1,32 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,2003 Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8560ads board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/mpc8560ads/init.S b/board/mpc8560ads/init.S new file mode 100644 index 000000000..242cb9fbc --- /dev/null +++ b/board/mpc8560ads/init.S @@ -0,0 +1,280 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xf8000000 16K BCSR registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) + .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + .long TLB1_MAS0(1, 8, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1, 9, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c new file mode 100644 index 000000000..25f69a0bf --- /dev/null +++ b/board/mpc8560ads/mpc8560ads.c @@ -0,0 +1,546 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); +long int fixed_sdram(void); + + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + + +/* + * MPC8560ADS Board Status & Control Registers + */ +typedef struct bcsr_ { + volatile unsigned char bcsr0; + volatile unsigned char bcsr1; + volatile unsigned char bcsr2; + volatile unsigned char bcsr3; + volatile unsigned char bcsr4; + volatile unsigned char bcsr5; +} bcsr_t; + + +int board_early_init_f (void) +{ + return 0; +} + +void reset_phy (void) +{ +#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ + volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR; +#endif + /* reset Giga bit Ethernet port if needed here */ + + /* reset the CPM FEC port */ +#if (CONFIG_ETHER_INDEX == 2) + bcsr->bcsr2 &= ~FETH2_RST; + udelay(2); + bcsr->bcsr2 |= FETH2_RST; + udelay(1000); +#elif (CONFIG_ETHER_INDEX == 3) + bcsr->bcsr3 &= ~FETH3_RST; + udelay(2); + bcsr->bcsr3 |= FETH3_RST; + udelay(1000); +#endif +#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) + /* reset PHY */ + miiphy_reset("FCC1 ETHERNET", 0x0); + + /* change PHY address to 0x02 */ + bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); + + bb_miiphy_write(NULL, 0x02, PHY_BMCR, + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); +#endif /* CONFIG_MII */ +} + + +int checkboard (void) +{ + puts("Board: ADS\n"); + +#ifdef CONFIG_PCI + printf(" PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf(" PCI1: disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init(); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + uint temp_ddrdll = 0; + + /* + * Work around to stabilize DDR DLL + */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); + } +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM. + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize Local Bus + */ + +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr(); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + + +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void +sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc= &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts(" SDRAM: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + lbc->br2 = CFG_BR2_PRELIM; + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("sync"); + + /* + * Configure the SDRAM controller. + */ + lbc->lsdmr = CFG_LBC_LSDMR_1; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_3; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; + asm("sync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); +} + + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ + #ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE; + ddr->sdram_interval = CFG_DDR_INTERVAL; + #if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000000D; + ddr->err_sbe = 0x00ff0000; + #endif + asm("sync;isync;msync"); + udelay(500); + #if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + #else + ddr->sdram_cfg = CFG_DDR_CONTROL; + #endif + asm("sync; isync; msync"); + udelay(500); + #endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxads_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxads_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif /* CONFIG_PCI */ +} diff --git a/board/mpc8560ads/u-boot.lds b/board/mpc8560ads/u-boot.lds new file mode 100644 index 000000000..8dcee1f10 --- /dev/null +++ b/board/mpc8560ads/u-boot.lds @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2002,2003,Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/mpc8560ads/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/mpc8560ads/init.o (.text) + cpu/mpc85xx/commproc.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/serial_scc.o (.text) + cpu/mpc85xx/ether_fcc.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/i2c.o (.text) + cpu/mpc85xx/spd_sdram.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 24ce80785..06d021a02 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -36,11 +36,11 @@ #ifdef CONFIG_PIP405 #include "../pip405/pip405.h" -#include +#include <405gp_pci.h> #endif #ifdef CONFIG_MIP405 #include "../mip405/mip405.h" -#include +#include <405gp_pci.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -57,6 +57,9 @@ extern int mem_test(ulong start, ulong ramsize, int quiet); extern flash_info_t flash_info[]; /* info for FLASH chips */ +static image_header_t header; + + static int mpl_prg(uchar *src, ulong size) { @@ -74,7 +77,7 @@ mpl_prg(uchar *src, ulong size) info = &flash_info[0]; #if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI) - if (uimage_to_cpu (magic[0]) != IH_MAGIC) { + if (ntohl(magic[0]) != IH_MAGIC) { puts("Bad Magic number\n"); return -1; } @@ -176,54 +179,52 @@ mpl_prg(uchar *src, ulong size) static int mpl_prg_image(uchar *ld_addr) { - unsigned long len; + unsigned long len, checksum; uchar *data; - image_header_t *hdr = (image_header_t *)ld_addr; + image_header_t *hdr = &header; int rc; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if (!image_check_magic (hdr)) { + /* Copy header so we can blank CRC field for re-calculation */ + memcpy (&header, (char *)ld_addr, sizeof(image_header_t)); + if (ntohl(hdr->ih_magic) != IH_MAGIC) { puts("Bad Magic Number\n"); return 1; } - image_print_contents (hdr); - if (!image_check_os (hdr, IH_OS_U_BOOT)) { + print_image_hdr(hdr); + if (hdr->ih_os != IH_OS_U_BOOT) { puts("No U-Boot Image\n"); return 1; } - if (!image_check_type (hdr, IH_TYPE_FIRMWARE)) { + if (hdr->ih_type != IH_TYPE_FIRMWARE) { puts("No Firmware Image\n"); return 1; } - if (!image_check_hcrc (hdr)) { + data = (uchar *)&header; + len = sizeof(image_header_t); + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + if (crc32 (0, (uchar *)data, len) != checksum) { puts("Bad Header Checksum\n"); return 1; } + data = ld_addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); puts("Verifying Checksum ... "); - if (!image_check_dcrc (hdr)) { + if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { puts("Bad Data CRC\n"); return 1; } puts("OK\n"); - data = (uchar *)image_get_data (hdr); - len = image_get_data_size (hdr); - - if (image_get_comp (hdr) != IH_COMP_NONE) { + if (hdr->ih_comp != IH_COMP_NONE) { uchar *buf; /* reserve space for uncompressed image */ if ((buf = malloc(IMAGE_SIZE)) == NULL) { - puts("Insufficient space for decompression\n"); + puts("Insufficient space for decompression\n"); return 1; } - switch (image_get_comp (hdr)) { + switch (hdr->ih_comp) { case IH_COMP_GZIP: puts("Uncompressing (GZIP) ... "); rc = gunzip ((void *)(buf), IMAGE_SIZE, data, &len); @@ -252,8 +253,7 @@ mpl_prg_image(uchar *ld_addr) break; #endif default: - printf ("Unimplemented compression type %d\n", - image_get_comp (hdr)); + printf ("Unimplemented compression type %d\n", hdr->ih_comp); free(buf); return 1; } @@ -357,8 +357,8 @@ void copy_old_env(ulong size) unsigned off; uchar *name, *value; - name = &name_buf[0]; - value = &value_buf[0]; + name=&name_buf[0]; + value=&value_buf[0]; len=size; off = sizeof(long); while (len > off) { @@ -377,8 +377,8 @@ void copy_old_env(ulong size) if(c == '\0') break; } while(len > off); - name = &name_buf[0]; - value = &value_buf[0]; + name=&name_buf[0]; + value=&value_buf[0]; if(strncmp((char *)name,"baudrate",8)!=0) { setenv((char *)name,(char *)value); } @@ -461,7 +461,7 @@ void show_stdio_dev(void) int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong size,src,ld_addr; + ulong size,src,ld_addr; int result; #if !defined(CONFIG_PATI) backup_t back; @@ -471,13 +471,13 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (strcmp(argv[1], "flash") == 0) { -#if defined(CONFIG_CMD_FDC) +#if (CONFIG_COMMANDS & CFG_CMD_FDC) if (strcmp(argv[2], "floppy") == 0) { - char *local_args[3]; + char *local_args[3]; extern int do_fdcboot (cmd_tbl_t *, int, int, char *[]); puts("\nupdating bootloader image from floppy\n"); local_args[0] = argv[0]; - if(argc==4) { + if(argc==4) { local_args[1] = argv[3]; local_args[2] = NULL; ld_addr=simple_strtoul(argv[3], NULL, 16); @@ -491,9 +491,9 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) result=mpl_prg_image((uchar *)ld_addr); return result; } -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_FDC) */ if (strcmp(argv[2], "mem") == 0) { - if(argc==4) { + if(argc==4) { ld_addr=simple_strtoul(argv[3], NULL, 16); } else { @@ -524,7 +524,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) src&=0xfff00000; size=0; do { - size++; + size++; printf("\n\nPass %ld\n",size); mem_test(CFG_MEMTEST_START,src,1); if(ctrlc()) @@ -538,7 +538,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if !defined(CONFIG_PATI) if (strcmp(argv[1], "clearenvvalues") == 0) { - if (strcmp(argv[2], "yes") == 0) + if (strcmp(argv[2], "yes") == 0) { clear_env_values(); return 0; @@ -564,7 +564,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) extern void doc_probe(ulong physadr); void doc_init (void) { @@ -587,7 +587,7 @@ extern int get_boot_mode(void); void video_get_info_str (int line_number, char *info) { /* init video info strings for graphic console */ - PPC4xx_SYS_INFO sys_info; + PPC405_SYS_INFO sys_info; char rev; int i,boot; unsigned long pvr; @@ -636,12 +636,12 @@ void video_get_info_str (int line_number, char *info) ++s; break; } - buf[i++] = *s; + buf[i++]=*s; } sprintf(&buf[i]," SN "); i+=4; for (; s < e; ++s) { - buf[i++] = *s; + buf[i++]=*s; } buf[i++]=0; } diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h index 46573da1f..8f2ec03f6 100644 --- a/board/mpl/common/common_util.h +++ b/board/mpl/common/common_util.h @@ -26,7 +26,7 @@ typedef struct { char signature[4]; - char serial_name[17]; /* "MIP405_1000xxxxx" */ + char serial_name[17]; /* "MIP405_1000xxxxx" */ char eth_addr[21]; /* "00:60:C2:0a:00:00" */ } backup_t; @@ -39,7 +39,7 @@ void get_backup_values(backup_t *buf); void show_stdio_dev(void); void check_env(void); -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) void doc_init (void); #endif diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index eb2702b6d..fd430083e 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -47,7 +47,7 @@ #if defined(CONFIG_PIP405) #include "../pip405/pip405.h" #endif -#include +#include <405gp_pci.h> #else /* defined(CONFIG_PATI) */ #include #endif @@ -160,7 +160,7 @@ unsigned long flash_init (void) unsigned long size_b1,flashcr,size_reg; int mode; extern char version_string; - char *p = &version_string; + char *p=&version_string; /* Since we are relocated, we can set-up the CS finally */ setup_cs_reloc(); @@ -398,7 +398,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) return (0); /* no or unknown flash */ } value = addr2[1]; /* device ID */ - /* printf("Device value %x\n",value); */ + /* printf("Device value %x\n",value); */ switch (value) { case (FLASH_WORD_SIZE)AMD_ID_F040B: info->flash_id += FLASH_AM040; diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c index b20b9532b..7724e241d 100644 --- a/board/mpl/common/kbd.c +++ b/board/mpl/common/kbd.c @@ -53,63 +53,63 @@ void enable_8259A_irq(unsigned int irq); #define KBD_STAT_KOBF 0x01 #define KBD_STAT_IBF 0x02 #define KBD_STAT_SYS 0x04 -#define KBD_STAT_CD 0x08 +#define KBD_STAT_CD 0x08 #define KBD_STAT_LOCK 0x10 #define KBD_STAT_MOBF 0x20 -#define KBD_STAT_TI_OUT 0x40 -#define KBD_STAT_PARERR 0x80 +#define KBD_STAT_TI_OUT 0x40 +#define KBD_STAT_PARERR 0x80 -#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */ -#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */ -#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */ +#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */ +#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */ +#define KBD_TIMEOUT 2000 /* Timeout in ms for keyboard command acknowledge */ /* * Keyboard Controller Commands */ -#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ -#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ -#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ +#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */ +#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */ +#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */ #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */ -#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ -#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ -#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ -#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ -#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ -#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ +#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */ +#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */ +#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */ +#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */ +#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */ +#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */ #define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if initiated by the auxiliary device */ -#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ +#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */ /* * Keyboard Commands */ -#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ -#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ -#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ -#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */ -#define KBD_CMD_RESET 0xFF /* Reset */ +#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ +#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */ +#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */ +#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */ +#define KBD_CMD_RESET 0xFF /* Reset */ /* * Keyboard Replies */ -#define KBD_REPLY_POR 0xAA /* Power on reset */ -#define KBD_REPLY_ACK 0xFA /* Command ACK */ -#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ +#define KBD_REPLY_POR 0xAA /* Power on reset */ +#define KBD_REPLY_ACK 0xFA /* Command ACK */ +#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */ /* * Status Register Bits */ -#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ -#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ -#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ -#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ -#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ -#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ -#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ -#define KBD_STAT_PERR 0x80 /* Parity error */ +#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */ +#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */ +#define KBD_STAT_SELFTEST 0x04 /* Self test successful */ +#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */ +#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */ +#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */ +#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */ +#define KBD_STAT_PERR 0x80 /* Parity error */ #define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF) @@ -117,24 +117,24 @@ void enable_8259A_irq(unsigned int irq); * Controller Mode Register Bits */ -#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ -#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ -#define KBD_MODE_SYS 0x04 /* The system flag (?) */ -#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ -#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ +#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */ +#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */ +#define KBD_MODE_SYS 0x04 /* The system flag (?) */ +#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */ +#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */ #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */ -#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ -#define KBD_MODE_RFU 0x80 +#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ +#define KBD_MODE_RFU 0x80 -#define KDB_DATA_PORT 0x60 +#define KDB_DATA_PORT 0x60 #define KDB_COMMAND_PORT 0x64 -#define LED_SCR 0x01 /* scroll lock led */ -#define LED_CAP 0x04 /* caps lock led */ -#define LED_NUM 0x02 /* num lock led */ +#define LED_SCR 0x01 /* scroll lock led */ +#define LED_CAP 0x04 /* caps lock led */ +#define LED_NUM 0x02 /* num lock led */ -#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ +#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ static volatile char kbd_buffer[KBD_BUFFER_LEN]; @@ -197,7 +197,8 @@ int isa_kbd_init(void) irq_install_handler(25, (interrupt_handler_t *)handle_isa_int, NULL); isa_irq_install_handler(KBD_INTERRUPT, (interrupt_handler_t *)kbd_interrupt, NULL); return (1); - } else { + } + else { printf("%s\n",result); return (-1); } @@ -215,20 +216,20 @@ int overwrite_console (void) int drv_isa_kbd_init (void) { int error; - device_t kbddev ; + device_t kbddev ; char *stdinname = getenv ("stdin"); if(isa_kbd_init()==-1) return -1; - memset (&kbddev, 0, sizeof(kbddev)); - strcpy(kbddev.name, DEVNAME); - kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - kbddev.putc = NULL ; + memset (&kbddev, 0, sizeof(kbddev)); + strcpy(kbddev.name, DEVNAME); + kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + kbddev.putc = NULL ; kbddev.puts = NULL ; kbddev.getc = kbd_getc ; kbddev.tstc = kbd_testc ; - error = device_register (&kbddev); + error = device_register (&kbddev); if(error==0) { /* check if this is the standard input device */ if(strcmp(stdinname,DEVNAME)==0) { @@ -312,106 +313,106 @@ void kbd_set_leds(void) } -void handle_keyboard_event (unsigned char scancode) +void handle_keyboard_event(unsigned char scancode) { unsigned char keycode; /* Convert scancode to keycode */ - PRINTF ("scancode %x\n", scancode); - if (scancode == 0xe0) { - e0 = 1; /* special charakters */ + PRINTF("scancode %x\n",scancode); + if(scancode==0xe0) { + e0=1; /* special charakters */ return; } - if (e0 == 1) { - e0 = 0; /* delete flag */ - if (!(((scancode & 0x7F) == 0x38) || /* the right ctrl key */ - ((scancode & 0x7F) == 0x1D) || /* the right alt key */ - ((scancode & 0x7F) == 0x35) || /* the right '/' key */ - ((scancode & 0x7F) == 0x1C))) - /* the right enter key */ + if(e0==1) { + e0=0; /* delete flag */ + if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */ + ((scancode&0x7F)==0x1D)|| /* the right alt key */ + ((scancode&0x7F)==0x35)|| /* the right '/' key */ + ((scancode&0x7F)==0x1C) )) /* the right enter key */ /* we swallow unknown e0 codes */ return; } /* special cntrl keys */ - switch (scancode) { - case 0x2A: - case 0x36: /* shift pressed */ - shift = 1; - return; /* do nothing else */ - case 0xAA: - case 0xB6: /* shift released */ - shift = 0; - return; /* do nothing else */ - case 0x38: /* alt pressed */ - alt = 1; - return; /* do nothing else */ - case 0xB8: /* alt released */ - alt = 0; - return; /* do nothing else */ - case 0x1d: /* ctrl pressed */ - ctrl = 1; - return; /* do nothing else */ - case 0x9d: /* ctrl released */ - ctrl = 0; - return; /* do nothing else */ - case 0x46: /* scrollock pressed */ - scroll_lock = ~scroll_lock; - kbd_set_leds (); - return; /* do nothing else */ - case 0x3A: /* capslock pressed */ - caps_lock = ~caps_lock; - kbd_set_leds (); - return; - case 0x45: /* numlock pressed */ - num_lock = ~num_lock; - kbd_set_leds (); - return; - case 0xC6: /* scroll lock released */ - case 0xC5: /* num lock released */ - case 0xBA: /* caps lock released */ - return; /* just swallow */ + switch(scancode) + { + case 0x2A: + case 0x36: /* shift pressed */ + shift=1; + return; /* do nothing else */ + case 0xAA: + case 0xB6: /* shift released */ + shift=0; + return; /* do nothing else */ + case 0x38: /* alt pressed */ + alt=1; + return; /* do nothing else */ + case 0xB8: /* alt released */ + alt=0; + return; /* do nothing else */ + case 0x1d: /* ctrl pressed */ + ctrl=1; + return; /* do nothing else */ + case 0x9d: /* ctrl released */ + ctrl=0; + return; /* do nothing else */ + case 0x46: /* scrollock pressed */ + scroll_lock=~scroll_lock; + kbd_set_leds(); + return; /* do nothing else */ + case 0x3A: /* capslock pressed */ + caps_lock=~caps_lock; + kbd_set_leds(); + return; + case 0x45: /* numlock pressed */ + num_lock=~num_lock; + kbd_set_leds(); + return; + case 0xC6: /* scroll lock released */ + case 0xC5: /* num lock released */ + case 0xBA: /* caps lock released */ + return; /* just swallow */ } - if ((scancode & 0x80) == 0x80) /* key released */ + if((scancode&0x80)==0x80) /* key released */ return; /* now, decide which table we need */ - if (scancode > (sizeof (kbd_plain_xlate) / sizeof (kbd_plain_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown scancode %X\n", scancode); - return; /* swallow it */ + if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow it */ } /* setup plain code first */ - keycode = kbd_plain_xlate[scancode]; - if (caps_lock == 1) { /* caps_lock is pressed, overwrite plain code */ - if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown caps-locked scancode %X\n", scancode); - return; /* swallow it */ + keycode=kbd_plain_xlate[scancode]; + if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown caps-locked scancode %X\n",scancode); + return; /* swallow it */ } - keycode = kbd_shift_xlate[scancode]; - if (keycode < 'A') { /* we only want the alphas capital */ - keycode = kbd_plain_xlate[scancode]; + keycode=kbd_shift_xlate[scancode]; + if(keycode<'A') { /* we only want the alphas capital */ + keycode=kbd_plain_xlate[scancode]; } } - if (shift == 1) { /* shift overwrites caps_lock */ - if (scancode > (sizeof (kbd_shift_xlate) / sizeof (kbd_shift_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown shifted scancode %X\n", scancode); - return; /* swallow it */ + if(shift==1) { /* shift overwrites caps_lock */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown shifted scancode %X\n",scancode); + return; /* swallow it */ } - keycode = kbd_shift_xlate[scancode]; + keycode=kbd_shift_xlate[scancode]; } - if (ctrl == 1) { /* ctrl overwrites caps_lock and shift */ - if (scancode > (sizeof (kbd_ctrl_xlate) / sizeof (kbd_ctrl_xlate[0]))) { /* scancode not in list */ - PRINTF ("unkown ctrl scancode %X\n", scancode); - return; /* swallow it */ + if(ctrl==1) { /* ctrl overwrites caps_lock and shift */ + if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown ctrl scancode %X\n",scancode); + return; /* swallow it */ } - keycode = kbd_ctrl_xlate[scancode]; + keycode=kbd_ctrl_xlate[scancode]; } /* check if valid keycode */ - if (keycode == 0xff) { - PRINTF ("unkown scancode %X\n", scancode); - return; /* swallow unknown codes */ + if(keycode==0xff) { + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow unknown codes */ } - kbd_put_queue (keycode); - PRINTF ("%x\n", keycode); + kbd_put_queue(keycode); + PRINTF("%x\n",keycode); } /* @@ -475,7 +476,7 @@ int kbd_read_data(void) int val; unsigned char status; - val = -1; + val=-1; status = kbd_read_status(); if (status & KBD_STAT_OBF) { val = kbd_read_input(); @@ -582,7 +583,8 @@ char * kbd_initialize(void) status = kbd_wait_for_input(); if (status == KBD_REPLY_ACK) break; - if (status != KBD_REPLY_RESEND) { + if (status != KBD_REPLY_RESEND) + { PRINTF("status: %X\n",status); return "Kbd: reset failed, no ACK"; } diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c index 1393ea15a..ff1190ab2 100644 --- a/board/mpl/common/memtst.c +++ b/board/mpl/common/memtst.c @@ -48,16 +48,16 @@ int testdram (void) #include #include -#include <4xx_i2c.h> +#include <405gp_i2c.h> DECLARE_GLOBAL_DATA_PTR; #define FALSE 0 #define TRUE 1 -#define TEST_QUIET 8 -#define TEST_SHOW_PROG 4 -#define TEST_SHOW_ERR 2 +#define TEST_QUIET 8 +#define TEST_SHOW_PROG 4 +#define TEST_SHOW_ERR 2 #define TEST_SHOW_ALL 1 #define TESTPAT1 0xAA55AA55 @@ -473,19 +473,19 @@ void mem_test_reloc(void) unsigned long addr; int i; for (i=0; i< TEST_STAGES; i++) { - addr = (ulong) (test_stage[i].test_write) + gd->reloc_off; + addr = (ulong) (test_stage[i].test_write) + gd->reloc_off; test_stage[i].test_write= (void (*) (unsigned long startaddr, unsigned long size, unsigned long *pat))addr; - addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off; + addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off; test_stage[i].test_write_desc=(char *)addr; - if(test_stage[i].test_check1) { + if(test_stage[i].test_check1) { addr = (ulong) (test_stage[i].test_check1) + gd->reloc_off; test_stage[i].test_check1= (void *(*) (int mode, unsigned long startaddr, unsigned long size, unsigned long *pat))addr; } - if(test_stage[i].test_check2) { + if(test_stage[i].test_check2) { addr = (ulong) (test_stage[i].test_check2) + gd->reloc_off; test_stage[i].test_check2= (void *(*) (int mode, unsigned long startaddr, diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c index bfd642892..bde14beeb 100644 --- a/board/mpl/common/pci.c +++ b/board/mpl/common/pci.c @@ -97,7 +97,7 @@ static void reloc_pci_cfg_table(struct pci_config_table *table) unsigned long addr; for (; table && table->vendor; table++) { - addr = (ulong) (table->config_device) + gd->reloc_off; + addr = (ulong) (table->config_device) + gd->reloc_off; #ifdef DEBUG printf ("device \"%d\": 0x%08lx => 0x%08lx\n", table->device, (ulong) (table->config_device), addr); diff --git a/board/mpl/common/pci_parts.h b/board/mpl/common/pci_parts.h index 7bca961c5..60008e2b2 100644 --- a/board/mpl/common/pci_parts.h +++ b/board/mpl/common/pci_parts.h @@ -80,9 +80,9 @@ */ struct pci_pip405_config_entry { - int index; /* address */ - unsigned long val; /* value */ - int width; /* data size */ + int index; /* address */ + unsigned long val; /* value */ + int width; /* data size */ }; extern void pci_pip405_write_regs(struct pci_controller *, @@ -95,37 +95,37 @@ static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = { {PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */ {PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */ {PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */ - {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */ + {PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */ #if defined(CONFIG_PIP405) - {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */ - {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */ + {PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */ + {PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */ #endif {PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */ - { } /* end of device table */ + { } /* end of device table */ }; /* PIIX4 IDE Controller Function 1 */ static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = { {PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */ - {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ + {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ #if !defined(CONFIG_MIP405T) {PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */ #else {PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */ #endif - { } /* end of device table */ + { } /* end of device table */ }; /* PIIX4 USB Controller Function 2 */ static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = { #if !defined(CONFIG_MIP405T) - {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */ + {PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */ {PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */ - {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */ - {0xC0, 0x2000, 2}, /* Legacy support */ + {PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */ + {0xC0, 0x2000, 2}, /* Legacy support */ {PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */ #endif - { } /* end of device table */ + { } /* end of device table */ }; /* PIIX4 Power Management Function 3 */ @@ -133,12 +133,12 @@ static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = { {PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */ {PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */ {PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */ - {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ - { } /* end of device table */ + {PCI_COMMAND, 0x0001, 2}, /* enable IO access */ + { } /* end of device table */ }; /* PPC405 Dummy only used to prevent autosetup on this host bridge */ static struct pci_pip405_config_entry ppc405_dummy[] = { - { } /* end of device table */ + { } /* end of device table */ }; void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, @@ -146,13 +146,13 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, static struct pci_config_table pci_pip405_config_table[]={ - {PCI_VENDOR_ID_IBM, /* 405 dummy */ + {PCI_VENDOR_ID_IBM, /* 405 dummy */ PCI_DEVICE_ID_IBM_405GP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0, pci_pip405_write_regs, {(unsigned long) ppc405_dummy}}, - {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */ + {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */ PCI_DEVICE_ID_INTEL_82371AB_0, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0, diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index 666b999e3..84c91c44b 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -536,11 +536,11 @@ void usb_check_int_chain(void) uhci_td_t *td,*prevtd; for(i=0;i<8;i++) { - prevtd = &td_int[i]; /* the first previous td is the skeleton td */ + prevtd=&td_int[i]; /* the first previous td is the skeleton td */ link=swap_32(td_int[i].link) & 0xfffffff0; /* next in chain */ td=(uhci_td_t *)link; /* assign it */ /* all interrupt TDs are finally linked to the td_int[0]. - * so we process all until we find the td_int[0]. + * so we process all until we find the td_int[0]. * if int0 chain points to a QH, we're also done */ while(((i>0) && (link != (unsigned long)&td_int[0])) || @@ -638,7 +638,7 @@ int usb_lowlevel_stop(void) return 1; irq_free_handler(irqvec); reset_hc(); - irqvec = -1; + irqvec=-1; return 0; } diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile index 53bf84658..9276f64ff 100644 --- a/board/mpl/mip405/Makefile +++ b/board/mpl/mip405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,35 +22,28 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \ +OBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \ ../common/usb_uhci.o ../common/memtst.o ../common/common_util.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c index 6ad95b5dd..6fbc5859c 100644 --- a/board/mpl/mip405/cmd_mip405.c +++ b/board/mpl/mip405/cmd_mip405.c @@ -38,19 +38,19 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong led_on; + ulong led_on; if (strcmp(argv[1], "info") == 0) { print_mip405_info(); - return 0; - } - if (strcmp(argv[1], "led") == 0) + return 0; + } + if (strcmp(argv[1], "led") == 0) { led_on = (ulong)simple_strtoul(argv[2], NULL, 10); user_led0(led_on); return 0; - } + } return (do_mplcommon(cmdtp, flag, argc, argv)); } U_BOOT_CMD( diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index f00a871df..3351b5b84 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -178,6 +178,19 @@ ext_bus_cntlr_init: nop /* pass2 DCR errata #8 */ blr +/*----------------------------------------------------------------------------- + * Function: sdram_init + * Description: Configures the internal SRAM memory. and setup the + * Stackpointer in it. + *----------------------------------------------------------------------------- */ + .globl sdram_init + +sdram_init: + + + blr + + #if defined(CONFIG_BOOT_PCI) .section .bootpg,"ax" .globl _start_pci diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index cf0afd1ad..34f328999 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -65,7 +65,7 @@ #include #include "mip405.h" #include -#include <4xx_i2c.h> +#include <405gp_i2c.h> #include #include "../common/common_util.h" #include @@ -73,6 +73,9 @@ DECLARE_GLOBAL_DATA_PTR; +extern block_dev_desc_t * scsi_get_dev(int dev); +extern block_dev_desc_t * ide_get_dev(int dev); + #undef SDRAM_DEBUG #define ENABLE_ECC /* for ecc boards */ #define FALSE 0 @@ -89,12 +92,12 @@ extern ldiv_t ldiv (long int __numer, long int __denom); #endif -#define PLD_PART_REG PER_PLD_ADDR + 0 -#define PLD_VERS_REG PER_PLD_ADDR + 1 -#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 -#define PLD_IRQ_REG PER_PLD_ADDR + 3 -#define PLD_COM_MODE_REG PER_PLD_ADDR + 4 -#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 +#define PLD_PART_REG PER_PLD_ADDR + 0 +#define PLD_VERS_REG PER_PLD_ADDR + 1 +#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2 +#define PLD_IRQ_REG PER_PLD_ADDR + 3 +#define PLD_COM_MODE_REG PER_PLD_ADDR + 4 +#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5 #define MEGA_BYTE (1024*1024) @@ -620,7 +623,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ static int test_dram (unsigned long ramsize); -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long bank_reg[4], tmp, bank_size; diff --git a/board/mpl/mip405/mip405.h b/board/mpl/mip405/mip405.h index fd7e78a45..b1d91deec 100644 --- a/board/mpl/mip405/mip405.h +++ b/board/mpl/mip405/mip405.h @@ -35,7 +35,7 @@ void user_led0(unsigned char on); #endif /* timings */ /* PLD (CS7) */ -#define PLD_BME 0 /* Burst disable */ +#define PLD_BME 0 /* Burst disable */ #define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */ #define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define PLD_OEN 1 /* Cycles from CS low to OE low */ @@ -46,7 +46,7 @@ void user_led0(unsigned char on); #define PLD_SOR 1 /* Sample on Ready disabled */ #define PLD_BEM 0 /* Byte Write only active on Write cycles */ #define PLD_PEN 0 /* Parity disable */ -#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \ +#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \ (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ @@ -62,7 +62,7 @@ void user_led0(unsigned char on); #define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024)) /* Dummy CS to get the board revision */ -#define BOARD_BME 0 /* Burst disable */ +#define BOARD_BME 0 /* Burst disable */ #define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ #define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define BOARD_OEN 1 /* Cycles from CS low to OE low */ @@ -73,7 +73,7 @@ void user_led0(unsigned char on); #define BOARD_SOR 1 /* Sample on Ready disabled */ #define BOARD_BEM 0 /* Byte Write only active on Write cycles */ #define BOARD_PEN 0 /* Parity disable */ -#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \ +#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \ (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ @@ -86,7 +86,7 @@ void user_led0(unsigned char on); /* UART0 CS2 */ -#define UART0_BME 0 /* Burst disable */ +#define UART0_BME 0 /* Burst disable */ #define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */ #define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define UART0_OEN 1 /* Cycles from CS low to OE low */ @@ -97,7 +97,7 @@ void user_led0(unsigned char on); #define UART0_SOR 1 /* Sample on Ready disabled */ #define UART0_BEM 0 /* Byte Write only active on Write cycles */ #define UART0_PEN 0 /* Parity disable */ -#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \ +#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \ (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ @@ -115,10 +115,10 @@ void user_led0(unsigned char on); /* Flash CS0 or CS 1 */ /* 0x7F8FFE80 slowest timing at all... */ -#define FLASH_BME_B 1 /* Burst enable */ +#define FLASH_BME_B 1 /* Burst enable */ #define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ #define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define FLASH_BME 0 /* Burst disable */ +#define FLASH_BME 0 /* Burst disable */ #define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ #define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define FLASH_OEN 1 /* Cycles from CS low to OE low */ @@ -130,10 +130,10 @@ void user_led0(unsigned char on); #define FLASH_BEM 0 /* Byte Write only active on Write cycles */ #define FLASH_PEN 0 /* Parity disable */ /* Access Parameter Register for non Boot */ -#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ +#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) /* Access Parameter Register for Boot */ -#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ +#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ @@ -149,10 +149,10 @@ void user_led0(unsigned char on); /* MPS CS1 or CS0 */ /* Boot CS: */ -#define MPS_BME_B 1 /* Burst enable */ +#define MPS_BME_B 1 /* Burst enable */ #define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ #define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define MPS_BME 0 /* Burst disable */ +#define MPS_BME 0 /* Burst disable */ #define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ #define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define MPS_OEN 1 /* Cycles from CS low to OE low */ @@ -164,10 +164,10 @@ void user_led0(unsigned char on); #define MPS_BEM 0 /* Byte Write only active on Write cycles */ #define MPS_PEN 0 /* Parity disable */ /* Access Parameter Register for non Boot */ -#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ +#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) /* Access Parameter Register for Boot */ -#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ +#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds index 7932b9fc0..ad5f2739c 100644 --- a/board/mpl/mip405/u-boot.lds +++ b/board/mpl/mip405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -42,11 +43,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -69,7 +70,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -144,7 +145,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile index adeba69ee..1a9ce1211 100644 --- a/board/mpl/pati/Makefile +++ b/board/mpl/pati/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de +# (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de +# # # See file CREDITS for list of people who contributed to this # project. @@ -22,33 +22,27 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o +OBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o #### cmd_pati.o +SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c index 91683a38d..98429c033 100644 --- a/board/mpl/pati/cmd_pati.c +++ b/board/mpl/pati/cmd_pati.c @@ -360,12 +360,12 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (strcmp(argv[1], "info") == 0) { show_pld_regs(); - return 0; + return 0; } if (strcmp(argv[1], "pci") == 0) { display_pci_regs(); - return 0; + return 0; } if (strcmp(argv[1], "led") == 0) { @@ -377,7 +377,7 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else user_led1(led_on); return 0; - } + } #if defined(CFG_PCI_CON_DEVICE) if (strcmp(argv[1], "con") == 0) { pci_con_connect(); diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index 475741d2a..0355b65b8 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -149,7 +149,7 @@ extern void mem_test_reloc(void); /* * Get RAM size. */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { unsigned char board_rev; unsigned long reg; @@ -484,7 +484,7 @@ int pci_con_getc(void) else diff=r_ptr-w_ptr; if((diff<(REC_BUFFER_SIZE-4)) && buff_full) { - /* clear Mail box */ + /* clear Mail box */ buff_full=0; PCICON_SET_REG(PCICON_RECEIVE_REG,0L); } diff --git a/board/mpl/pati/pati.h b/board/mpl/pati/pati.h index 86c7a41cc..d5217724d 100644 --- a/board/mpl/pati/pati.h +++ b/board/mpl/pati/pati.h @@ -89,7 +89,7 @@ #define SDRAM_CAL 9 #define SDRAM_RCD 10 #define SDRAM_WREQ 11 -#define SDRAM_PR 12 +#define SDRAM_PR 12 #define SDRAM_RC 13 #define SDRAM_LMR 14 #define SDRAM_IIP 19 @@ -128,7 +128,7 @@ #define SDRAM_MUX0 9 #define SDRAM_MUX1 10 #define SDRAM_PDIS 11 -#define SDRAM_RES1 12 +#define SDRAM_RES1 12 #define SDRAM_RES2 13 #define SDRAM_RES3 14 #define SDRAM_RES4 19 @@ -177,7 +177,7 @@ #define SDRAM_RES5 9 #define SDRAM_CFG1 10 #define SDRAM_CFG2 11 -#define SDRAM_CFG3 12 +#define SDRAM_CFG3 12 #define SDRAM_RES6 13 #define SDRAM_CFG5 14 #define SDRAM_CFG6 19 @@ -214,7 +214,7 @@ * MISC Defines ***************************************************************/ -#define PCI_VENDOR_ID_MPL 0x18E6 +#define PCI_VENDOR_ID_MPL 0x18E6 #define PCI_DEVICE_ID_PATI 0x00DA #if defined(CONFIG_MIP405) @@ -269,12 +269,12 @@ /* Config Area */ #define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */ -#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */ +#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */ /* Attributes */ -#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_CFG_BURST 0 /* No Burst */ -#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */ +#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ +#define PATI_LOC_CFG_BURST 0 /* No Burst */ +#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */ +#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */ #define PATI_LOC_CFG_SPACE0_ATTR ( \ PATI_LOC_CFG_BUS_SIZE | \ @@ -295,10 +295,10 @@ #define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */ #define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */ /* Attributes */ -#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ -#define PATI_LOC_SDRAM_BURST 0 /* No Burst */ -#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */ -#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */ +#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ +#define PATI_LOC_SDRAM_BURST 0 /* No Burst */ +#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */ +#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */ /* should never be used */ #define PATI_LOC_SDRAM_SPACE0_ATTR ( \ @@ -319,10 +319,10 @@ #define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */ #define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */ /* Attributes */ -#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */ -#define PATI_LOC_FLASH_BURST 0 /* No Burst */ -#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */ -#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */ +#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */ +#define PATI_LOC_FLASH_BURST 0 /* No Burst */ +#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */ +#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */ /* should never be used */ #define PATI_LOC_FLASH_SPACE0_ATTR ( \ @@ -343,7 +343,7 @@ #define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */ #define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */ /* Attributes */ -#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ +#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */ #define PATI_LOC_CPU_BURST 0 /* No Burst */ #define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */ #define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */ @@ -393,9 +393,9 @@ #define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF)) -#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) +#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) #define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY)) -#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE)) +#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE)) /*************************************************** * Direct Master Config @@ -404,12 +404,12 @@ #define PATI_BUS_MASTER 1 -#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */ -#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */ +#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */ +#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */ -#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */ -#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */ -#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */ +#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */ +#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */ +#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */ #define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000 #define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008 #define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000 diff --git a/board/mpl/pati/pci_eeprom.h b/board/mpl/pati/pci_eeprom.h index af34b86c3..96588089e 100644 --- a/board/mpl/pati/pci_eeprom.h +++ b/board/mpl/pati/pci_eeprom.h @@ -35,57 +35,57 @@ typedef struct pci_eeprom_t { } pci_eeprom; static pci_eeprom pati_eeprom[] = { - { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */ - { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */ - { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */ - { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */ - { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */ - { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */ - { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */ - { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */ - { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */ - { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */ - { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */ - { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */ - { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */ - { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */ - { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */ - { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */ - { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */ - { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */ - { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */ - { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */ - { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */ - { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */ - { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */ - { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */ - { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */ - { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */ - { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */ - { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */ - { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */ - { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */ - { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */ - { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */ - { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/ - { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */ - { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */ - { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */ - { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */ - { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */ - { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */ - { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */ - { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */ - { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */ - { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */ - { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */ - { 0x58,0x0000 }, /* Reserved Reserved */ - { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */ - { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */ - { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/ - { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */ - { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */ - { 0xFFFF,0xFFFF} /* terminaror */ + { 0x00,PCI_DEVICE_ID_PATI }, /* PCI Device ID PCIIDR[31:16] */ + { 0x02,PCI_VENDOR_ID_MPL }, /* PCI Vendor ID PCIIDR[15:0] */ + { 0x04,PCI_CLASS_PROCESSOR_POWERPC }, /* PCI Class Code PCICCR[23:8] */ + { 0x06,0x00BA }, /* PCI Class Code / PCI Revision ID PCICCR[7:0] / PCIREV[7:0] */ + { 0x08,0x0007 }, /* PCI Maximum Latency / PCI Minimum Grant PCIMLR[7:0] / PCIMGR[7:0] */ + { 0x0A,0x0100 }, /* PCI Interrupt Pin / PCI Interrupt Line PCIIPR[7:0] / PCIILR[7:0] */ + { 0x0C,0x0000 }, /* MSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[31:16] */ + { 0x0E,0x0000 }, /* LSW of Mailbox 0 (User Defined) PCI9056_MAILBOX0[15:0] */ + { 0x10,0x0000 }, /* MSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[31:16] */ + { 0x12,0x0000 }, /* LSW of Mailbox 1 (User Defined) PCI9056_MAILBOX1[15:0] */ + { 0x14,HIGH_WORD(PATI_LOC_CFG_MASK) }, /* MSW of Direct Slave Local Address Space 0 Range LAS0RR[31:16] */ + { 0x16,LOW_WORD(PATI_LOC_CFG_MASK) }, /* LSW of Direct Slave Local Address Space 0 Range LAS0RR[15:0] */ + { 0x18,HIGH_WORD(PATI_LOC_CFG_ADDR) }, /* MSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[31:16] (CFG) */ + { 0x1A,LOW_WORD(PATI_LOC_CFG_ADDR)|1 }, /* LSW of Direct Slave Local Address Space 0 Local Base Address (Remap) LAS0BA[15:2, 0], Reserved [1] */ + { 0x1C,0x0000 }, /* MSW of Mode/DMA Arbitration MARBR[31, 29:16] or DMAARB[31, 29:16], Reserved [30] */ + { 0x1E,0x0000 }, /* LSW of Mode/DMA Arbitration MARBR[15:0] or DMAARB[15:0] */ + { 0x20,0x0030 }, /* Local Miscellaneous Control 2 / Serial EEPROM WP Addr Boundary LMISC2[5:0], Res[7:6] / PROT_AREA[6:0], Res[7] */ + { 0x22,0x0510 }, /* Local Miscellaneous Control 1 / Local Bus Big/Little Endian Descriptor LMISC1[7:0] / BIGEND[7:0] */ + { 0x24,0x0000 }, /* MSW of Direct Slave Expansion ROM Range EROMRR[31:16] */ + { 0x26,0x0000 }, /* LSW of Direct Slave Expansion ROM Range EROMRR[15:11, 0], Reserved [10:1] */ + { 0x28,0x0000 }, /* MSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[31:16] */ + { 0x2A,0x0000 }, /* LSW of Direct Slave Expansion ROM Local Base Address (Remap) and BREQo Control EROMBA[15:11, 5:0], Reserved [10:6] */ + { 0x2C,(0x4243 | HIGH_WORD((PATI_LOC_CFG_SPACE0_ATTR))) }, /* MSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[31:16] */ + { 0x2E,LOW_WORD(PATI_LOC_CFG_SPACE0_ATTR) }, /* LSW of Local Address Space 0/Expansion ROM Bus Region Descriptor LBRD0[15:0] */ + { 0x30,HIGH_WORD(PATI_DMASTER_MASK) }, /* MSW of Local Range for Direct Master-to-PCI DMRR[31:16] */ + { 0x32,LOW_WORD(PATI_DMASTER_MASK) }, /* LSW of Local Range for Direct Master-to-PCI (Reserved) DMRR[15:0] */ + { 0x34,HIGH_WORD(PATI_DMASTER_ADDR) }, /* MSW of Local Base Address for Direct Master-to-PCI Memory DMLBAM[31:16] */ + { 0x36,LOW_WORD(PATI_DMASTER_ADDR) }, /* LSW of Local Base Address for Direct Master-to-PCI Memory (Reserved) DMLBAM[15:0] */ + { 0x38,0x0000 }, /* MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration DMLBAI[31:16] */ + { 0x3A,0x0000 }, /* LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration (Reserved) DMLBAI[15:0] */ + { 0x3C,0x0000 }, /* MSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[31:16] */ + { 0x3E,0x0000 }, /* LSW of PCI Base Address (Remap) for Direct Master-to-PCI Memory DMPBAM[15:0] */ + { 0x40,0x0000 }, /* MSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[31, 23:16] Reserved [30:24]*/ + { 0x42,0x0000 }, /* LSW of PCI Configuration Address for Direct Master-to-PCI I/O Configuration DMCFGA[15:0] */ + { 0x44,0x0000 }, /* PCI Subsystem ID PCISID[15:0] */ + { 0x46,0x0000 }, /* PCI Subsystem Vendor ID PCISVID[15:0] */ + { 0x48,HIGH_WORD(PATI_LOC_SDRAM_MASK) }, /* MSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[31:16] */ + { 0x4A,LOW_WORD(PATI_LOC_SDRAM_MASK) }, /* LSW of Direct Slave Local Address Space 1 Range (1 MB) LAS1RR[15:0] */ + { 0x4C,HIGH_WORD(PATI_LOC_SDRAM_ADDR) }, /* MSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[31:16] (SDRAM) */ + { 0x4E,LOW_WORD(PATI_LOC_SDRAM_ADDR) | 0x1 }, /* LSW of Direct Slave Local Address Space 1 Local Base Address (Remap) LAS1BA[15:2, 0], Reserved [1] */ + { 0x50,HIGH_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* MSW of Local Address Space 1 Bus Region Descriptor LBRD1[31:16] */ + { 0x52,LOW_WORD(PATI_LOC_SDRAM_SPACE1_ATTR) }, /* LSW of Local Address Space 1 Bus Region Descriptor (Reserved) LBRD1[15:0] */ + { 0x54,0x0000 }, /* Hot Swap Control/Status (Reserved) Reserved */ + { 0x56,0x0000 }, /* Hot Swap Next Capability Pointer / Hot Swap Control HS_NEXT[7:0] / HS_CNTL[7:0] */ + { 0x58,0x0000 }, /* Reserved Reserved */ + { 0x5A,0x0000 }, /* PCI Arbiter Control PCIARB[3:0], Reserved [15:4] */ + { 0x5C,0x0000 }, /* Power Management Capabilities PMC[15:9, 2:0] */ + { 0x5E,0x0000 }, /* Power Management Next Capability Pointer (Reserved) / Power Management Capability ID (Reserved) Reserved*/ + { 0x60,0x0000 }, /* Power Management Data / PMCSR Bridge Support Extension (Reserved) PMDATA[7:0] / Reserved */ + { 0x62,0x0000 }, /* Power Management Control/Status PMCSR[14:8] */ + { 0xFFFF,0xFFFF} /* terminaror */ }; #define PATI_EEPROM_LAST_OFFSET 0x64 #endif /* #ifndef __PCI_EEPROM_H_ */ diff --git a/board/mpl/pati/u-boot.lds b/board/mpl/pati/u-boot.lds new file mode 100644 index 000000000..5b03fef66 --- /dev/null +++ b/board/mpl/pati/u-boot.lds @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2001 Wolfgang Denk, DENX Software Engineering, wd@denx.de + * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc5xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +/* . = env_start; + .ppcenv : + { + common/environment.o (.ppcenv) + } +*/ +} diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile index 590c7da5b..a818d08a5 100644 --- a/board/mpl/pip405/Makefile +++ b/board/mpl/pip405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,13 +22,10 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o \ +OBJS = $(BOARD).o \ ../common/flash.o cmd_pip405.o ../common/pci.o \ ../common/isa.o ../common/kbd.o \ ../common/usb_uhci.o \ @@ -36,24 +33,20 @@ COBJS = $(BOARD).o \ SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c index 945e5c958..1bf4d7bd8 100644 --- a/board/mpl/pip405/cmd_pip405.c +++ b/board/mpl/pip405/cmd_pip405.c @@ -38,14 +38,14 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong led_on,led_nr; + ulong led_on,led_nr; if (strcmp(argv[1], "info") == 0) { print_pip405_info(); - return 0; - } - if (strcmp(argv[1], "led") == 0) + return 0; + } + if (strcmp(argv[1], "led") == 0) { led_nr = (ulong)simple_strtoul(argv[2], NULL, 10); led_on = (ulong)simple_strtoul(argv[3], NULL, 10); @@ -54,7 +54,7 @@ int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else user_led1(led_on); return 0; - } + } return (do_mplcommon(cmdtp, flag, argc, argv)); } diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 838432525..39f2ea534 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -175,6 +175,19 @@ nop /* pass2 DCR errata #8 */ blr +/*----------------------------------------------------------------------------- + * Function: sdram_init + * Description: Configures the internal SRAM memory. and setup the + * Stackpointer in it. + *----------------------------------------------------------------------------- */ + .globl sdram_init + +sdram_init: + + + blr + + #if defined(CONFIG_BOOT_PCI) .section .bootpg,"ax" .globl _start_pci diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index 6cba892e7..38286081a 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -608,7 +608,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ static int test_dram (unsigned long ramsize); -phys_size_t initdram (int board_type) +long int initdram (int board_type) { unsigned long bank_reg[4], tmp, bank_size; int i, ds; diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h index 5815786eb..b41c5bb28 100644 --- a/board/mpl/pip405/pip405.h +++ b/board/mpl/pip405/pip405.h @@ -56,7 +56,7 @@ void user_led1(unsigned char on); /* timings */ /* CS Config register (CS7) */ -#define CONFIG_PORT_BME 0 /* Burst disable */ +#define CONFIG_PORT_BME 0 /* Burst disable */ #define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */ #define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */ @@ -67,7 +67,7 @@ void user_led1(unsigned char on); #define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */ #define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */ #define CONFIG_PORT_PEN 0 /* Parity disable */ -#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \ +#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \ (CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ @@ -80,10 +80,10 @@ void user_led1(unsigned char on); /* Flash CS0 or CS 1 */ /* 0x7F8FFE80 slowest timing at all... */ -#define FLASH_BME_B 1 /* Burst enable */ +#define FLASH_BME_B 1 /* Burst enable */ #define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */ #define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define FLASH_BME 0 /* Burst disable */ +#define FLASH_BME 0 /* Burst disable */ #define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ #define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define FLASH_OEN 1 /* Cycles from CS low to OE low */ @@ -95,10 +95,10 @@ void user_led1(unsigned char on); #define FLASH_BEM 0 /* Byte Write only active on Write cycles */ #define FLASH_PEN 0 /* Parity disable */ /* Access Parameter Register for non Boot */ -#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ +#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) /* Access Parameter Register for Boot */ -#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ +#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \ (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ @@ -114,10 +114,10 @@ void user_led1(unsigned char on); /* MPS CS1 or CS0 */ /* Boot CS: */ -#define MPS_BME_B 1 /* Burst enable */ +#define MPS_BME_B 1 /* Burst enable */ #define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */ #define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */ -#define MPS_BME 0 /* Burst disable */ +#define MPS_BME 0 /* Burst disable */ #define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */ #define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */ #define MPS_OEN 1 /* Cycles from CS low to OE low */ @@ -129,10 +129,10 @@ void user_led1(unsigned char on); #define MPS_BEM 0 /* Byte Write only active on Write cycles */ #define MPS_PEN 0 /* Parity disable */ /* Access Parameter Register for non Boot */ -#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ +#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) /* Access Parameter Register for Boot */ -#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ +#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \ (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5)) /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds index fb710649a..11819a4fc 100644 --- a/board/mpl/pip405/u-boot.lds +++ b/board/mpl/pip405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -65,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -139,7 +140,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index 0552994f4..1608f8cda 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 10bcb3b0a..304c965d1 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,35 +22,28 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := vcma9.o flash.o cmd_vcma9.o -COBJS += ../common/common_util.o ../common/memtst.o +OBJS := vcma9.o flash.o cmd_vcma9.o +OBJS += ../common/common_util.o ../common/memtst.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index d3629c589..44b411255 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -31,7 +31,7 @@ #include "../common/common_util.h" #if defined(CONFIG_DRIVER_CS8900) -#include <../drivers/net/cs8900.h> +#include <../drivers/cs8900.h> static uchar cs8900_chksum(ushort data) { @@ -40,8 +40,6 @@ static uchar cs8900_chksum(ushort data) #endif -DECLARE_GLOBAL_DATA_PTR; - extern void print_vcma9_info(void); extern int vcma9_cantest(int); extern int vcma9_nandtest(void); @@ -55,11 +53,13 @@ extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { + DECLARE_GLOBAL_DATA_PTR; + if (strcmp(argv[1], "info") == 0) { print_vcma9_info(); - return 0; - } + return 0; + } #if defined(CONFIG_DRIVER_CS8900) if (strcmp(argv[1], "cs8900") == 0) { if (strcmp(argv[2], "read") == 0) { diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c index d15a19115..ccfe1768f 100644 --- a/board/mpl/vcma9/flash.c +++ b/board/mpl/vcma9/flash.c @@ -290,7 +290,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) * Copy memory to flash */ -static int write_hword (flash_info_t * info, ulong dest, ushort data) +volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) { vu_short *addr = (vu_short *) dest; ushort result; diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index e3af07309..a02335314 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -39,92 +39,92 @@ #define SDRAM_REG 0x2C000106 /* BWSCON */ -#define DW8 (0x0) -#define DW16 (0x1) -#define DW32 (0x2) -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) /* BANKSIZE */ #define BURST_EN (0x1<<7) -#define B1_BWSCON (DW16) -#define B2_BWSCON (DW32) -#define B3_BWSCON (DW32) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW8 + UBLB) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) +#define B1_BWSCON (DW16) +#define B2_BWSCON (DW32) +#define B3_BWSCON (DW32) +#define B4_BWSCON (DW16 + WAIT + UBLB) +#define B5_BWSCON (DW8 + UBLB) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) /* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x1 /* 1clk */ +#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x1 /* 1clk */ /*#define B0_Tcos 0x0 0clk */ -#define B0_Tacc 0x7 /* 14clk */ +#define B0_Tacc 0x7 /* 14clk */ /*#define B0_Tacc 0x5 8clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* page mode is not used */ -#define B0_PMC 0x0 /* page mode disabled */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 /* page mode is not used */ +#define B0_PMC 0x0 /* page mode disabled */ /* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x1 /* 1clk */ +#define B1_Tacs 0x0 /* 0clk */ +#define B1_Tcos 0x1 /* 1clk */ /*#define B1_Tcos 0x0 0clk */ #define B1_Tacc 0x7 /* 14clk */ /*#define B1_Tacc 0x5 8clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 /* page mode is not used */ -#define B1_PMC 0x0 /* page mode disabled */ +#define B1_Tcoh 0x0 /* 0clk */ +#define B1_Tah 0x0 /* 0clk */ +#define B1_Tacp 0x0 /* page mode is not used */ +#define B1_PMC 0x0 /* page mode disabled */ -#define B2_Tacs 0x3 /* 4clk */ -#define B2_Tcos 0x3 /* 4clk */ -#define B2_Tacc 0x7 /* 14clk */ -#define B2_Tcoh 0x3 /* 4clk */ -#define B2_Tah 0x3 /* 4clk */ -#define B2_Tacp 0x0 /* page mode is not used */ -#define B2_PMC 0x0 /* page mode disabled */ +#define B2_Tacs 0x3 /* 4clk */ +#define B2_Tcos 0x3 /* 4clk */ +#define B2_Tacc 0x7 /* 14clk */ +#define B2_Tcoh 0x3 /* 4clk */ +#define B2_Tah 0x3 /* 4clk */ +#define B2_Tacp 0x0 /* page mode is not used */ +#define B2_PMC 0x0 /* page mode disabled */ -#define B3_Tacs 0x3 /* 4clk */ -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 /* 14clk */ -#define B3_Tcoh 0x3 /* 4clk */ -#define B3_Tah 0x3 /* 4clk */ -#define B3_Tacp 0x0 /* page mode is not used */ -#define B3_PMC 0x0 /* page mode disabled */ +#define B3_Tacs 0x3 /* 4clk */ +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 /* 14clk */ +#define B3_Tcoh 0x3 /* 4clk */ +#define B3_Tah 0x3 /* 4clk */ +#define B3_Tacp 0x0 /* page mode is not used */ +#define B3_PMC 0x0 /* page mode disabled */ -#define B4_Tacs 0x3 /* 4clk */ -#define B4_Tcos 0x1 /* 1clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x1 /* 1clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 /* page mode is not used */ -#define B4_PMC 0x0 /* page mode disabled */ +#define B4_Tacs 0x3 /* 4clk */ +#define B4_Tcos 0x1 /* 1clk */ +#define B4_Tacc 0x7 /* 14clk */ +#define B4_Tcoh 0x1 /* 1clk */ +#define B4_Tah 0x0 /* 0clk */ +#define B4_Tacp 0x0 /* page mode is not used */ +#define B4_PMC 0x0 /* page mode disabled */ -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x3 /* 4clk */ -#define B5_Tacc 0x5 /* 8clk */ -#define B5_Tcoh 0x2 /* 2clk */ -#define B5_Tah 0x1 /* 1clk */ -#define B5_Tacp 0x0 /* page mode is not used */ -#define B5_PMC 0x0 /* page mode disabled */ +#define B5_Tacs 0x0 /* 0clk */ +#define B5_Tcos 0x3 /* 4clk */ +#define B5_Tacc 0x5 /* 8clk */ +#define B5_Tcoh 0x2 /* 2clk */ +#define B5_Tah 0x1 /* 1clk */ +#define B5_Tacp 0x0 /* page mode is not used */ +#define B5_PMC 0x0 /* page mode disabled */ -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ -#define B6_SCAN 0x2 /* 10bit */ +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x1 /* 3clk */ +#define B6_SCAN 0x2 /* 10bit */ -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ -#define B7_SCAN 0x2 /* 10bit */ +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 3clk */ +#define B7_SCAN 0x2 /* 10bit */ /* REFRESH parameter */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x0 /* 2clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x2 /* 3clk */ +#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ /**************************************/ _TEXT_BASE: diff --git a/board/mpl/vcma9/u-boot.lds b/board/mpl/vcma9/u-boot.lds index 14cd22800..f4fbf969c 100644 --- a/board/mpl/vcma9/u-boot.lds +++ b/board/mpl/vcma9/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index a4c463a31..0d2003d2f 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -132,7 +132,7 @@ int board_init(void) /* * NAND flash initialization. */ -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) extern ulong nand_probe(ulong physadr); @@ -288,7 +288,7 @@ int dram_init(void) int checkboard(void) { - char s[50]; + unsigned char s[50]; int i; backup_t *b = (backup_t *) s; @@ -337,7 +337,7 @@ int overwrite_console(void) ************************************************************************/ void print_vcma9_info(void) { - char s[50]; + unsigned char s[50]; int i; if ((i = getenv_r("serial#", s, 32)) < 0) { diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 220b7053b..c0167d516 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -31,7 +31,7 @@ extern int mem_test(unsigned long start, unsigned long ramsize,int mode); void print_vcma9_info(void); -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) typedef enum { NFCE_LOW, NFCE_HIGH @@ -128,7 +128,7 @@ typedef struct { } /*__attribute__((__packed__))*/ VCMA9_PLD; #define VCMA9_PLD_BASE 0x2C000100 -static inline VCMA9_PLD * VCMA9_GetBase_PLD(void) +static inline VCMA9_PLD * const VCMA9_GetBase_PLD(void) { return (VCMA9_PLD * const)VCMA9_PLD_BASE; } diff --git a/board/musenki/Makefile b/board/musenki/Makefile index dcb190703..24dc0264f 100644 --- a/board/musenki/Makefile +++ b/board/musenki/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o +SOBJS = -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c index b2b70e756..88ef83ac1 100644 --- a/board/musenki/musenki.c +++ b/board/musenki/musenki.c @@ -35,7 +35,7 @@ int checkboard (void) } -#if 0 /* NOT USED */ +#if 0 /* NOT USED */ int checkflash (void) { /* TODO: XXX XXX XXX */ @@ -45,7 +45,7 @@ int checkflash (void) } #endif -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/musenki/u-boot.lds b/board/musenki/u-boot.lds new file mode 100644 index 000000000..7c051095f --- /dev/null +++ b/board/musenki/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mvblue/Makefile b/board/mvblue/Makefile index dcb190703..24dc0264f 100644 --- a/board/mvblue/Makefile +++ b/board/mvblue/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o +SOBJS = -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/mvblue/flash.c b/board/mvblue/flash.c index 0c0738cf2..8df573aa0 100644 --- a/board/mvblue/flash.c +++ b/board/mvblue/flash.c @@ -337,9 +337,9 @@ static ulong flash_get_size (vu_long *address, flash_info_t *info) #define ERASE_DATA4 ERASE_DATA1 #define ERASE_DATA5 ERASE_DATA2 -#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK) -#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK) -#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK) +#define ERASE_SECTOR_DATA (0x00300030 & FLASH_DATA_MASK) +#define ERASE_CHIP_DATA (0x00100010 & FLASH_DATA_MASK) +#define ERASE_CONFIRM_DATA (0x00800080 & FLASH_DATA_MASK) int flash_erase (flash_info_t *info, int s_first, int s_last) { @@ -559,7 +559,7 @@ static int write_char (flash_info_t *info, ulong dest, uchar data) return (1); } } - mvdebug (("-write_byte\n")); + mvdebug (("-write_byte\n")); return (0); } @@ -577,7 +577,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) mvdebug (("+write_word : 0x%08lx @ 0x%08lx\n", data, dest)); for ( i=0; (i < 4) && (result == 0); i++, dest+=1 ) result = write_char (info, dest, (data >> (8*(3-i))) & 0xff ); - mvdebug (("-write_word\n")); + mvdebug (("-write_word\n")); return result; } /*---------------------------------------------------------------- */ diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c index a979102ab..ee8f3e301 100644 --- a/board/mvblue/mvblue.c +++ b/board/mvblue/mvblue.c @@ -76,7 +76,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds new file mode 100644 index 000000000..7c051095f --- /dev/null +++ b/board/mvblue/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mvs1/Makefile b/board/mvs1/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/mvs1/Makefile +++ b/board/mvs1/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/mvs1/flash.c b/board/mvs1/flash.c index a52fe55b0..084594358 100644 --- a/board/mvs1/flash.c +++ b/board/mvs1/flash.c @@ -649,7 +649,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) } } - mvdebug (("-write_word\n")); + mvdebug (("-write_word\n")); return (0); } #else /* CONFIG_MVS_16BIT_FLASH */ @@ -691,7 +691,7 @@ static int write_halfword (flash_info_t *info, ulong dest, ushort data) return (1); } } - mvdebug (("-write_halfword\n")); + mvdebug (("-write_halfword\n")); return (0); } diff --git a/board/mvs1/mvs1.c b/board/mvs1/mvs1.c index 58b84f5ae..f8a8cb757 100644 --- a/board/mvs1/mvs1.c +++ b/board/mvs1/mvs1.c @@ -136,7 +136,7 @@ static void test_dram (unsigned long *start, unsigned long *end) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/mvs1/u-boot.lds b/board/mvs1/u-boot.lds index 55a9c3ae8..a04de3d85 100644 --- a/board/mvs1/u-boot.lds +++ b/board/mvs1/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -132,7 +133,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/mvs1/u-boot.lds.debug b/board/mvs1/u-boot.lds.debug index c33581d25..ddd4678ee 100644 --- a/board/mvs1/u-boot.lds.debug +++ b/board/mvs1/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/mx1ads/Makefile b/board/mx1ads/Makefile index b68b1bdd2..3e805feb4 100644 --- a/board/mx1ads/Makefile +++ b/board/mx1ads/Makefile @@ -1,9 +1,6 @@ # # board/mx1ads/Makefile # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (c) Copyright 2004 # Techware Information Technology, Inc. # http://www.techware.com.tw/ @@ -27,29 +24,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := mx1ads.o syncflash.o +OBJS := mx1ads.o syncflash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/mx1ads/lowlevel_init.S b/board/mx1ads/lowlevel_init.S index 6967fb2b4..09c260d64 100644 --- a/board/mx1ads/lowlevel_init.S +++ b/board/mx1ads/lowlevel_init.S @@ -35,7 +35,7 @@ _TEXT_BASE: .globl lowlevel_init lowlevel_init: -/* memory controller init */ +/* memory controller init */ ldr r1, =SDCTL0 @@ -50,7 +50,7 @@ lowlevel_init: ldr r3, =0x8200000 ldr r2, [r3] -/* Set AutoRefresh Command */ +/* Set AutoRefresh Command */ ldr r3, =0xA2120200 str r3, [r1] @@ -65,17 +65,17 @@ lowlevel_init: ldr r2, [r3] ldr r2, [r3] -/* Set Mode Register */ +/* Set Mode Register */ ldr r3, =0xB2120200 str r3, [r1] /* Issue Mode Register Command */ - ldr r3, =0x08111800 /* Mode Register Value */ + ldr r3, =0x08111800 /* Mode Register Value */ ldr r2, [r3] /* Set Normal Mode */ ldr r3, =0x82124200 str r3, [r1] -/* everything is fine now */ +/* everything is fine now */ mov pc, lr diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c index ba152e2e8..abf2fd51e 100644 --- a/board/mx1ads/mx1ads.c +++ b/board/mx1ads/mx1ads.c @@ -85,8 +85,8 @@ int board_init (void) GPCR = 0x000003AB; /* I/O pad driving strength */ - /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ -/* MX1_CS1L = 0x11110601; */ + /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ +/* MX1_CS1L = 0x11110601; */ MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c index fae9fbb39..eb7fde507 100644 --- a/board/mx1ads/syncflash.c +++ b/board/mx1ads/syncflash.c @@ -40,13 +40,13 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ #define SYNCFLASH_A10 (0x00100000) #define CMD_NORMAL (0x81020300) /* Normal Mode */ -#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ -#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ -#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ -#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ +#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ +#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ +#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ +#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ #define CMD_PROGRAM (CMD_NORMAL + 0x70000000) -#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ +#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ /* LCR Command */ #define LCR_READSTATUS (0x0001C000) /* 0x70 */ @@ -55,22 +55,22 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ #define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ #define LCR_SR_CLEAR (0x00014000) /* 0x50 */ -/* Get Status register */ +/* Get Status register */ u32 SF_SR(void) { u32 tmp,tmp1; reg_SFCTL = CMD_PROGRAM; - tmp = __REG(CFG_FLASH_BASE); + tmp = __REG(CFG_FLASH_BASE); reg_SFCTL = CMD_NORMAL; - reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ - tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR); + reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ + tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR); return tmp; } -/* check if SyncFlash is ready */ +/* check if SyncFlash is ready */ u8 SF_Ready(void) { u32 tmp; @@ -84,19 +84,19 @@ u8 SF_Ready(void) { printf ("SyncFlash Error code %08x\n",tmp); }; - if (tmp == 0x00800080) /* Test Bit 7 of SR */ + if (tmp == 0x00800080) /* Test Bit 7 of SR */ return 1; else return 0; } -/* Issue the precharge all command */ +/* Issue the precharge all command */ void SF_PrechargeAll(void) { u32 tmp; - reg_SFCTL = CMD_PREC; /* Set Precharge Command */ - tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */ + reg_SFCTL = CMD_PREC; /* Set Precharge Command */ + tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */ } /* set SyncFlash to normal mode */ @@ -107,21 +107,21 @@ void SF_Normal(void) { reg_SFCTL = CMD_NORMAL; } -/* Erase SyncFlash */ +/* Erase SyncFlash */ void SF_Erase(u32 RowAddress) { u32 tmp; reg_SFCTL = CMD_NORMAL; - tmp = __REG(RowAddress); + tmp = __REG(RowAddress); reg_SFCTL = CMD_PREC; - tmp = __REG(RowAddress); + tmp = __REG(RowAddress); - reg_SFCTL = CMD_LCR; /* Set LCR mode */ - __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ + reg_SFCTL = CMD_LCR; /* Set LCR mode */ + __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ - reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ - __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ + reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ + __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ while(!SF_Ready()); } @@ -132,8 +132,8 @@ void SF_NvmodeErase(void) { reg_SFCTL = CMD_LCR; /* Set to LCR mode */ __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ + reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ + __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ while(!SF_Ready()); } @@ -141,11 +141,11 @@ void SF_NvmodeErase(void) { void SF_NvmodeWrite(void) { SF_PrechargeAll(); - reg_SFCTL = CMD_LCR; /* Set to LCR mode */ + reg_SFCTL = CMD_LCR; /* Set to LCR mode */ __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ + reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ + __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ } /****************************************************************************************/ @@ -156,19 +156,19 @@ ulong flash_init(void) { /* Turn on CSD1 for negating RESETSF of SyncFLash */ - reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ + reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ udelay(200); - reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ - tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ + reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ + tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ SF_Normal(); i = 0; - flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; + flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; - flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].size = FLASH_BANK_SIZE; flash_info[i].sector_count = CFG_MAX_FLASH_SECT; memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); diff --git a/board/mx1ads/u-boot.lds b/board/mx1ads/u-boot.lds index f2f8afca1..8438f99f7 100644 --- a/board/mx1ads/u-boot.lds +++ b/board/mx1ads/u-boot.lds @@ -53,6 +53,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/mx1fs2/Makefile b/board/mx1fs2/Makefile index f81f7acd5..9e3bca14c 100644 --- a/board/mx1fs2/Makefile +++ b/board/mx1fs2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := mx1fs2.o flash.o +OBJS := mx1fs2.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c index 73ce8957e..38063106e 100644 --- a/board/mx1fs2/flash.c +++ b/board/mx1fs2/flash.c @@ -173,7 +173,7 @@ flash_print_info(flash_info_t * info) int i; uchar *boottype; uchar *bootletter; - char *fmt; + uchar *fmt; uchar botbootletter[] = "B"; uchar topbootletter[] = "T"; uchar botboottype[] = "bottom boot sector"; @@ -612,7 +612,7 @@ bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) * @param info: * @param src: source of copy transaction * @param addr: where to copy to - * @param cnt: number of bytes to copy + * @param cnt: number of bytes to copy * * @return error code */ diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S index 4b2cb487a..8211beb3f 100644 --- a/board/mx1fs2/lowlevel_init.S +++ b/board/mx1fs2/lowlevel_init.S @@ -166,22 +166,22 @@ lowlevel_init: ldr r1,=0x00221000 /* adr of SDCTRL0 */ ldr r0,=0x92120200 str r0,[r1,#0] /* put in precharge command mode */ - ldr r2,=0x08200000 /* adr for precharge cmd */ + ldr r2,=0x08200000 /* adr for precharge cmd */ ldr r0,[r2,#0] /* precharge */ ldr r0,=0xA2120200 ldr r2,=0x08000000 /* start of SDRAM */ str r0,[r1,#0] /* put in auto-refresh mode */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ + ldr r0,[r2,#0] /* auto-refresh */ ldr r0,=0xB2120200 ldr r2,=0x08111800 str r0,[r1,#0] /* setup for mode register of SDRAM */ - ldr r0,[r2,#0] /* program mode register */ + ldr r0,[r2,#0] /* program mode register */ ldr r0,=0x82124267 str r0,[r1,#0] /* back to normal operation */ diff --git a/board/mx1fs2/mx1fs2.c b/board/mx1fs2/mx1fs2.c index 90a33c249..1c026f0f7 100644 --- a/board/mx1fs2/mx1fs2.c +++ b/board/mx1fs2/mx1fs2.c @@ -48,7 +48,7 @@ static void logo_init(void) imx_gpio_mode(PD14_PF_FLM_VSYNC); imx_gpio_mode(PD13_PF_LP_HSYNC); imx_gpio_mode(PD6_PF_LSCLK); - imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_DR); + imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_GPIO); imx_gpio_mode(PD11_PF_CONTRAST); imx_gpio_mode(PD10_PF_SPL_SPR); diff --git a/board/mx1fs2/u-boot.lds b/board/mx1fs2/u-boot.lds index 46ed451ee..1d1669cde 100644 --- a/board/mx1fs2/u-boot.lds +++ b/board/mx1fs2/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/nc650/Makefile b/board/nc650/Makefile index e4006e7bd..8dc4934f7 100644 --- a/board/nc650/Makefile +++ b/board/nc650/Makefile @@ -1,6 +1,6 @@ # # (C) Copyright 2006 Detlev Zundel, dzu@denx.de -# (C) Copyright 2004-2006 +# (C) Copyright 2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,22 +24,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o nand.o flash.o +OBJS = $(BOARD).o nand.o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/nc650/config.mk b/board/nc650/config.mk index 9d9b89260..5b2284aec 100644 --- a/board/nc650/config.mk +++ b/board/nc650/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de +# (C) Copyright 2006 Detlev Zundel, dzu@denx.de # (C) Copyright 2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -27,3 +27,4 @@ # TEXT_BASE = 0x40700000 +BOARDLIBS = drivers/nand/libnand.a diff --git a/board/nc650/nand.c b/board/nc650/nand.c index 8617f7445..de54386dd 100644 --- a/board/nc650/nand.c +++ b/board/nc650/nand.c @@ -24,7 +24,7 @@ #include -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include @@ -106,13 +106,12 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd) * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init(struct nand_chip *nand) { nand->hwcontrol = nc650_hwcontrol; nand->eccmode = NAND_ECC_SOFT; nand->chip_delay = 12; /* nand->options = NAND_SAMSUNG_LP_OPTIONS;*/ - return 0; } -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c index 657abc46d..8a6b5b00a 100644 --- a/board/nc650/nc650.c +++ b/board/nc650/nc650.c @@ -128,7 +128,7 @@ static long int dram_size (long int, long int *, long int); /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -177,14 +177,16 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); udelay (1000); diff --git a/board/nc650/u-boot.lds b/board/nc650/u-boot.lds index 09a442aee..ca449181e 100644 --- a/board/nc650/u-boot.lds +++ b/board/nc650/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -116,7 +117,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/nc650/u-boot.lds.debug b/board/nc650/u-boot.lds.debug index 079a55abe..2228a2005 100644 --- a/board/nc650/u-boot.lds.debug +++ b/board/nc650/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/netphone/Makefile b/board/netphone/Makefile index df7d3123b..b3c1797e2 100644 --- a/board/netphone/Makefile +++ b/board/netphone/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o phone_console.o +OBJS = $(BOARD).o flash.o phone_console.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c index 38eb7c811..297de97a5 100644 --- a/board/netphone/netphone.c +++ b/board/netphone/netphone.c @@ -404,7 +404,7 @@ void check_ram(unsigned int addr, unsigned int size) } } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -597,7 +597,7 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include @@ -691,7 +691,7 @@ int last_stage_init(void) i = CFG_HZ * 2; while (i > 0) { - if (tstc()) { + if (tstc()) { getc(); break; } diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds index 271102b77..9f2901c86 100644 --- a/board/netphone/u-boot.lds +++ b/board/netphone/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,10 +34,10 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } @@ -49,8 +50,8 @@ SECTIONS .rel.plt : { *(.rel.plt) } .rela.plt : { *(.rela.plt) } .init : { *(.init) } - .plt : { *(.plt) } - .text : + .plt : { *(.plt) } + .text : { cpu/mpc8xx/start.o (.text) cpu/mpc8xx/traps.o (.text) @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug index 5bf1a6628..004e7fd35 100644 --- a/board/netphone/u-boot.lds.debug +++ b/board/netphone/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/netstar/Makefile b/board/netstar/Makefile index 8d911b845..3a205017f 100644 --- a/board/netstar/Makefile +++ b/board/netstar/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2005 # Ladislav Michl, 2N Telekomunikace, michl@2n.cz # @@ -26,71 +23,63 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := netstar.o flash.o nand.o +OBJS := netstar.o flash.o nand.o SOBJS := setup.o crcek.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c \ - eeprom_start.S -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) LOAD_ADDR = 0x10400000 LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds -lnk = $(if $(obj),$(obj),.) HOST_CFLAGS = -Wall -pedantic -I$(TOPDIR)/include -all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \ - $(obj)crcek.srec $(obj)crcek.bin $(obj)crcit +all: $(LIB) eeprom.srec eeprom.bin crcek.srec crcek.bin crcit $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ + $(AR) crv $@ $^ -$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o - cd $(lnk) && $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ - -o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \ - -L$(obj)../../examples -lstubs \ - -L$(obj)../../lib_generic -lgeneric \ +eeprom.srec: eeprom.o eeprom_start.o + $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ + -o $(<:.o=) -e $(<:.o=) $^ \ + -L../../examples -lstubs \ + -L../../lib_generic -lgeneric \ -L$(gcclibdir) -lgcc $(OBJCOPY) -O srec $(<:.o=) $@ -$(obj)eeprom.bin: $(obj)eeprom.srec +eeprom.bin: eeprom.srec $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null -$(obj)crcek.srec: $(obj)crcek.o +crcek.srec: crcek.o $(LD) -g -Ttext 0x00000000 \ - -o $(<:.o=) -e crcek $^ + -o $(<:.o=) -e $(<:.o=) $^ $(OBJCOPY) -O srec $(<:.o=) $@ -$(obj)crcek.bin: $(obj)crcek.srec +crcek.bin: crcek.srec $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null -$(obj)crcit: $(obj)crcit.o $(obj)crc32.o +crcit: crcit.o crc32.o $(HOSTCC) $(HOST_CFLAGS) -o $@ $^ -$(obj)crcit.o: crcit.c - $(HOSTCC) $(HOST_CFLAGS) -o $@ -c $< +crcit.o: crcit.c + $(HOSTCC) $(HOST_CFLAGS) -c $< -$(obj)crc32.o: $(OBJTREE)/tools/crc32.c - $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -o $@ -c $< +crc32.o: $(TOPDIR)/tools/crc32.c + $(HOSTCC) $(HOST_CFLAGS) -DUSE_HOSTCC -c $< clean: - rm -f $(SOBJS) $(OBJS) $(obj)eeprom $(obj)eeprom.srec \ - $(obj)eeprom.bin $(obj)crcek $(obj)crcek.srec \ - $(obj)crcek.bin + rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin \ + crcek crcek.srec crcek.bin distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S index af3566218..a74abf9a0 100644 --- a/board/netstar/crcek.S +++ b/board/netstar/crcek.S @@ -33,7 +33,7 @@ ldr r4, [r3, r4, lsl#2] eor r0, r4, r0, lsr#8 subs r2, r2, #0x1 - bne 1b + bne 1b eor r0, r0, r5 .endm @@ -58,7 +58,7 @@ mov \reg, #0x100000 3: subs \reg, \reg, #0x1 - bne 3b + bne 3b .endm .text diff --git a/board/netstar/crcit b/board/netstar/crcit new file mode 100644 index 0000000000000000000000000000000000000000..203645d039fd0bada99c4c22f8a254cac039effb GIT binary patch literal 11370 zcmeI2dw5jE`Nt=_xj`;0S0fi)6=*2U8ZJf@(G4NwKqGfb1$0@mn;V;K*zC$hqG*h= zMragiv8`xJX=$~TJK+`*KryyT2muoAMbJc00-_CS-QWA2Gn1S>2~QvUJiq@s$=T1m z@4WBKJ9EyNGw1S5YWi41NC=b3z#e9hmWEroO8sT5pf?wVZUl>DR@RU8X5pj>qs_`o zKs6^>DXNx?6m~{pDDnoOFj&=$U|&^Yk}^UN?X@MV$f~UCsfv<}nYaReh_zmn*Y}*n z^^zk*919H*Trd5gh9B!C)V)+cCRio{la&2K->~%+_4YMbNrG$zn3?~!k&gxGCSCG6 zkgx2a8dUbM@{HtgRm~)&-(>RRafeg^5gvN&drQ}>_je~QljRZ)*cr+-#-2Hx6u?iTj<>GX&jsem@E zy^PbR)58u4&6ttVB^OIJ0sJy-rVx%U)RMEMzuYR-QZGR_L{Ryfz!7 zU7UeEn#2m69*^6@3cVh$+vj2nJULz`%PjEZ<3^|0hFXSN(0MwM+yAu%96~+oPohbve7$q%P%*Hlgj{wTMpiv0 za4g9r_ZN;W?QyqJ*yC6dyN0`zYxLsO=Uq?`!nhd8J09*Pd7P8oit;P}g~l zULIS}H){0SbE8?K$2lOAQhX({u{-ss@j3iFN^L8}2O|#z?z`UA!~z3u&~F)~zyQeE zaBDgrpfun!$QX*I8ZKXej3H>M>O$A)u3>jT*nnN=2ze>uG&&TCrul7sIn}|%9KM@R*pkukyh3i zOD)_e!`LXLVGSk|Q%WkmhCmG;8VpBkS~_Yn#l@y8{!6|jGVV{3Qfg94YQ5&n%uK4I zGE(t}#gIBsOXZ=h<-UvWh4myUr1}61)s5^&)x?Slz1_;uN3DfOK%EvnlU$|6`}f3j5ksr5>6Q9aye!Tk}9dle#jwy2(w_0xA(3dK(GHa7j6LM@$6q3(~aK!^6Be~lifi(3M|?)#ob@XwJf z`hGcrGN`IF6}vKiR`mglB@Jbwzvw%~?`tkD`p)3%M}ahBboihur6U?&qE1oNO)rrz znS}bXT1{Tz12Cd-Ff~(B>6;)5OiC%Ej-FSR`xt+sc$U&U&5d@s>4p^op`@6erkbd`n+hXX$z=ul`u2mI5o?851y zEKhAwhM0hH3h4I}+(rOWmjl3SFj#z3gNpwsCY3TJ@NS^HQhXpX{eerK>$4tDo-Jk@nsD$> z$9^2uFp6qO_dEKV6u+xKO;~;Vr!OB659Oc>O4T<;n$MKwxdC5XV+I{~N@?HzN+}tp zm%^p^VB7)4e>pkO|pJmR>aXFc)!m6TGHJ0>duiI^Q z**#g#&cX!CkXDm~Cwaxw3+-9X2hACtj2y3dR>G6!C!L9-05}j_Jeu+GX0Aixdo8#TbI!Uu3hC=0}fqwDi-`h`RPUA9Zkp1 zgUcFfe+3Rs-_9@FdzWl_8gfKJ`KRD3{q~iC4%3c);C1uHTu_<6^Gon-as^-N71f>O zcTSftp2>rL^0vAg;GvSE#o*6YySjsw>*qPZ#W&~v8@y8O#N@^%&JN*s0u8Qk>}i%U zs>?UvS22;x!S~JiBf%$3IqBfVs^rVIk@F#;Onb)9R|Cs+so(AHRXnQ$dSv!Y~bdG==Z?>O;MY` z7niv21-qta{~Ua~pS=nkm5{j|EK5Gk518=zr!WPxJ?7fg;Ezqmu7duOP4mG!w{6E- zhON7}?@e%6U3nw;`|5~=;P9KQ3%Fu^r(c3`t7HEO?vBZQ222>0hqVs-mCNx87&1HK z6Y$35dGo-zc2{4pKG9hMPGEDdgP*SocY#l>3+V$^-H3b+oN=(rSKxaM8=c^!rXAhD z&&n%G!6nOfeg~fGcV;d)F5zTP@XIAfUk07&b>D(Nw{LzF{AlvF2SG2}vlhINxVsKa zUUzOhcw$vOZjD&p!6SbFzrAt%D45%nlLCI%kk4-^$1cnIE99E;IVZuwgwQeIrGCa? zpe?=gU%=`mF=xPs=7&uJ|B`I@5oj_+@vHO;=ICn31GZ)3){AW^aht(Tb(uTCH!s>h z0%LEUeF9uv-7pBedv(o5aO?ULhrruLZFvlQHfE~@965XM4)Cw8U6r7@xcqZ)`<8vb z2BR-*H-f*e-Q)!yNIUi!__qbMZ-6}qo(ctvdz~%>yG3Pu3_d^7@f!GWZe9$yerE1s zFzRsZMevP4rLtN>FgcH9OYTd{Et z*tquiaq#JtM}7w$++RNeoO1o#MDSYH?jvBKZt8>nQ)6ZqC2d}Qk9|A6_$QcX1yv6=^uy=9h9`LPN_W&^ILiQAJ z)q?1MfX1|_-Qdn%hP%Og2Zl`tD@N{m7mSbEyBU0S=GMVrXzrHT;GY5~_JczX*K7kz z*EIYD?6=|UEO6s~$8W%a*E6nwzg?T_13RzGGk|{%@AO;nk)+tmU`bYl2kbsWeT?+n z_j&86^yAkb_v{Z_4E?(u5+iNz`EL_FMy*j)LjEx zww%cZ^NUa334YkC;#qLkz@1-%|6H)q4K7IA5eI%UGjbVNklQ5yelRjT6Pz6t(iIG> zasC3#*)X>SJQ|p12U8EbdVvcsbbbr`qBiCPIITEz0=R#R@d402FzZj?zk1E70Uu4v z83&$PkpD0^KKIB5@bt{%4Pa)}IV;#avi^Q>>V`dk2H#z?`z-j(;mv7aQ(#*n*!TM0 zz2HmxcYOdRuG}&e{NviK{lT!LnqA<^@Dm?`gJzta2JXvhxCgW>&fEf)kGCHL4Slj7 z2VWcP{xNueMbuXCcPpX~fPKz|%>GNLBoo=38NhIvli3>ty96wYqv*+h05d5rp&+F~ASo`mX|k6nKt~H6_Q!ySy4n^5RwAEAjV<;aJYo1;ligHM;32Rp*sZgahS?Wbt{Mih2{Gcb6g;^o;XM13L zv=wN524gi?Noso*TWM6~aIU5GlR=d`3;9Jse$r5$AN<6gLNB3?E?p1A^AXvrdSM{P zEkekAGNgQYsFiD^ewmOXg&jXwDc?!RvVFQq;OAquu%~h2vK*IYAuFO>xc~n{K4;do zR3Y}uM}lVszYzRhFgD!EJ?{{-2tF*RtCls3=iz!iOG`<4&>T;Xe+QX|S?JF^G%;~_ z;_x9u&GA#54zptSn$z**SS?Mse-N!T|L5`pN6b>VD9>x3%Pe>@%b6{6^k~-UDPWd- zx7TS&9z8C>YtLeqYGfAK_x5MtWGmA6Zmg%wQIc?bv@|6;^WO&`4LTXS&ZUz-no%Xz(3~JC#)zFWH z*R9qww~(we+%UR-At#)ha$aBtD@l}u0`sFb$@5t1?x9QsZPLH5!AcU| z%WyEWiq_xI)|{Hb;s@6n>2EbyNn*?@6bhHx=1DpK$a-*5#T+R8=NIj<=qz}~`H#w+b4r%^fPOexEGlRrtO zGPCg4$1l_@gEFXF`Y#jn>N3%woTp{``u^wX{N=n~E*#`_0wTs)@4tX_7?W_?kmPl) z3;|P;->CC%6#k83A@ZO6cj)}_ z8UU$9`0Lx#%X`QcyIRIC-y_TS%W@qm4yV@RSH|@&`D*(w-u}*6d{`&Jr`pG(RlL4LVzkI)E7LJL0c9zzRncK2FhnoS>1naxgyrIq?!FrkuJ6Qi4>267$@4@!H zTJM*F^|vv3eg^B?zJmzXi<3aBq`Z;7^XVuV8CGNMld<)yowhO@#|FB)d`DdGWC_m4 zP*{)BWeo_Ht_LSIzq$8!YNw;#_`uD^{%()&nl8primTndQ0y07T=XLw{d9Lr)?tV+Xu9{d)PitG{lvA&l?fdmMl_AdNs9^gl z(swkT)wj?eA$ zgycuZrKsPd>B?+)Fk!QMJoZI4XTAe{EOgtl?fH(jrZNhB+)RA7rmKNJ #include -#include "../drivers/net/smc91111.h" +#include "../drivers/smc91111.h" #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE diff --git a/board/netstar/eeprom.lds b/board/netstar/eeprom.lds index 89b0a8209..317550dba 100644 --- a/board/netstar/eeprom.lds +++ b/board/netstar/eeprom.lds @@ -46,6 +46,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/netstar/eeprom_start.S b/board/netstar/eeprom_start.S index 130648585..75d9f0558 100644 --- a/board/netstar/eeprom_start.S +++ b/board/netstar/eeprom_start.S @@ -29,7 +29,7 @@ _start: b eeprom ldr r4, [r3, r4, lsl#2] eor r0, r4, r0, lsr#8 subs r2, r2, #0x1 - bne 1b + bne 1b eor r0, r0, r5 .endm @@ -58,7 +58,7 @@ _start: b eeprom mov \reg, #0x1000 3: subs \reg, \reg, #0x1 - bne 3b + bne 3b .endm .text diff --git a/board/netstar/nand.c b/board/netstar/nand.c index b76d2a332..f470c1a01 100644 --- a/board/netstar/nand.c +++ b/board/netstar/nand.c @@ -22,7 +22,7 @@ #include -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include @@ -45,12 +45,22 @@ static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd) this->IO_ADDR_W = (void *) IO_ADDR_W; } -int board_nand_init(struct nand_chip *nand) +/* + * chip R/B detection + */ +/*** +static int netstar_nand_ready(struct mtd_info *mtd) +{ + return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02; +} +***/ + +void board_nand_init(struct nand_chip *nand) { nand->options = NAND_SAMSUNG_LP_OPTIONS; nand->eccmode = NAND_ECC_SOFT; nand->hwcontrol = netstar_nand_hwcontrol; - nand->chip_delay = 400; - return 0; +/* nand->dev_ready = netstar_nand_ready; */ + nand->chip_delay = 18; } #endif diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c index f52afe50c..d6b620c8c 100644 --- a/board/netstar/netstar.c +++ b/board/netstar/netstar.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* arch number of NetStar board */ - gd->bd->bi_arch_number = MACH_TYPE_NETSTAR; + gd->bd->bi_arch_number = 692; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x10000100; diff --git a/board/netstar/setup.S b/board/netstar/setup.S index 3c2d46797..5dacc9cc4 100644 --- a/board/netstar/setup.S +++ b/board/netstar/setup.S @@ -277,7 +277,7 @@ ulocking: mov r0, #0x4000 sdelay: subs r0, r0, #0x1 - bne sdelay + bne sdelay /* back to arch calling code */ mov pc, lr diff --git a/board/netstar/u-boot.lds b/board/netstar/u-boot.lds index 39646e6e8..8317f72d0 100644 --- a/board/netstar/u-boot.lds +++ b/board/netstar/u-boot.lds @@ -50,6 +50,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/netta/Makefile b/board/netta/Makefile index 96374ba3f..ee200c2d2 100644 --- a/board/netta/Makefile +++ b/board/netta/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o dsp.o codec.o pcmcia.o +OBJS = $(BOARD).o flash.o dsp.o codec.o pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/netta/dsp.c b/board/netta/dsp.c index 3739e16d6..66e0b85e6 100644 --- a/board/netta/dsp.c +++ b/board/netta/dsp.c @@ -1031,7 +1031,7 @@ const struct host_init hi_default = { .clk_divider = { [0] = 47, /* must be 2048Hz */ - [1] = 47, + [1] = 47, }, .initmode = 1, diff --git a/board/netta/netta.c b/board/netta/netta.c index 1183f33ef..4923e3add 100644 --- a/board/netta/netta.c +++ b/board/netta/netta.c @@ -337,7 +337,7 @@ void check_ram(unsigned int addr, unsigned int size) } } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -555,7 +555,7 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) #include @@ -570,7 +570,7 @@ void nand_init(void) } #endif -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_init(void) { diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c index 66e6e511e..a3709f7f7 100644 --- a/board/netta/pcmcia.c +++ b/board/netta/pcmcia.c @@ -4,11 +4,11 @@ #undef CONFIG_PCMCIA -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -231,12 +231,12 @@ int pcmcia_hardware_enable(int slot) (reg&PCMCIA_VS2(slot))?"n":"ff"); if ((pipr & mask) == mask) { - set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ - set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */ + set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ + set_vccd(0, 0); set_vccd(1, 1); /* 5V on, 3V off */ puts (" 5.0V card found: "); } else { - set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ - set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */ + set_vppd(0, 1); set_vppd(1, 1); /* VAVPP => Hi-Z */ + set_vccd(0, 1); set_vccd(1, 0); /* 5V off, 3V on */ puts (" 3.3V card found: "); } @@ -244,7 +244,7 @@ int pcmcia_hardware_enable(int slot) for (i=0; i<5000; ++i) { if (!get_oc()) { printf (" *** Overcurrent - Safety shutdown ***\n"); - set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */ + set_vccd(0, 0); set_vccd(1, 0); /* VAVPP => Hi-Z */ return (1); } udelay (100); @@ -264,7 +264,7 @@ int pcmcia_hardware_enable(int slot) } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { volatile immap_t *immap; @@ -291,7 +291,7 @@ int pcmcia_hardware_disable(int slot) return (0); } -#endif +#endif /* CFG_CMD_PCMCIA */ int pcmcia_voltage_set(int slot, int vcc, int vpp) diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds index f560189c0..9f2901c86 100644 --- a/board/netta/u-boot.lds +++ b/board/netta/u-boot.lds @@ -22,21 +22,22 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS { /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; - .interp : { *(.interp) } + .interp : { *(.interp) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } @@ -49,8 +50,8 @@ SECTIONS .rel.plt : { *(.rel.plt) } .rela.plt : { *(.rela.plt) } .init : { *(.init) } - .plt : { *(.plt) } - .text : + .plt : { *(.plt) } + .text : { cpu/mpc8xx/start.o (.text) cpu/mpc8xx/traps.o (.text) @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug index 5bf1a6628..004e7fd35 100644 --- a/board/netta/u-boot.lds.debug +++ b/board/netta/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/netta2/Makefile b/board/netta2/Makefile index cf07cf40f..d45702091 100644 --- a/board/netta2/Makefile +++ b/board/netta2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index a97c14cee..3ca7bd3c8 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -402,7 +402,7 @@ void check_ram(unsigned int addr, unsigned int size) } } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -595,7 +595,7 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds index f560189c0..9f2901c86 100644 --- a/board/netta2/u-boot.lds +++ b/board/netta2/u-boot.lds @@ -22,21 +22,22 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS { /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; - .interp : { *(.interp) } + .interp : { *(.interp) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } @@ -49,8 +50,8 @@ SECTIONS .rel.plt : { *(.rel.plt) } .rela.plt : { *(.rela.plt) } .init : { *(.init) } - .plt : { *(.plt) } - .text : + .plt : { *(.plt) } + .text : { cpu/mpc8xx/start.o (.text) cpu/mpc8xx/traps.o (.text) @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug index 5bf1a6628..004e7fd35 100644 --- a/board/netta2/u-boot.lds.debug +++ b/board/netta2/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/netvia/Makefile b/board/netvia/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/netvia/Makefile +++ b/board/netvia/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c index 4140bac86..3e6c61663 100644 --- a/board/netvia/netvia.c +++ b/board/netvia/netvia.c @@ -245,7 +245,7 @@ int checkboard(void) #define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23)) #define MCR_MCLF_MASK MCR_MCLF(15) -phys_size_t initdram(int board_type) +long int initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -416,7 +416,7 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index b4f210e48..dc69db6ad 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -22,21 +22,22 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS { /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; - .interp : { *(.interp) } + .interp : { *(.interp) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } @@ -49,8 +50,8 @@ SECTIONS .rel.plt : { *(.rel.plt) } .rela.plt : { *(.rela.plt) } .init : { *(.init) } - .plt : { *(.plt) } - .text : + .plt : { *(.plt) } + .text : { cpu/mpc8xx/start.o (.text) cpu/mpc8xx/traps.o (.text) @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug index 1014ec6e8..96569bfd9 100644 --- a/board/netvia/u-boot.lds.debug +++ b/board/netvia/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/ns9750dev/Makefile b/board/ns9750dev/Makefile index 2ffed99f7..fb4333c19 100644 --- a/board/ns9750dev/Makefile +++ b/board/ns9750dev/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := ns9750dev.o flash.o led.o +OBJS := ns9750dev.o flash.o led.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/ns9750dev/ns9750dev.c b/board/ns9750dev/ns9750dev.c index fc46244c7..1dd348a0c 100644 --- a/board/ns9750dev/ns9750dev.c +++ b/board/ns9750dev/ns9750dev.c @@ -102,7 +102,7 @@ void flash__init (void) /************************************************************* Routine:ether__init Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. + for the EEPROM load to complete. *************************************************************/ void ether__init (void) { diff --git a/board/ns9750dev/u-boot.lds b/board/ns9750dev/u-boot.lds index a3de6ac61..8ebb6519f 100644 --- a/board/ns9750dev/u-boot.lds +++ b/board/ns9750dev/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = . ; } diff --git a/board/nx823/Makefile b/board/nx823/Makefile index dcb190703..7a2014d46 100644 --- a/board/nx823/Makefile +++ b/board/nx823/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c index 18840ff48..4a426ec49 100644 --- a/board/nx823/nx823.c +++ b/board/nx823/nx823.c @@ -157,7 +157,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds index 85117aa56..7099fc40d 100644 --- a/board/nx823/u-boot.lds +++ b/board/nx823/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -118,7 +119,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug index 85072feda..3165d5634 100644 --- a/board/nx823/u-boot.lds.debug +++ b/board/nx823/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/o2dnt/Makefile b/board/o2dnt/Makefile index 58afd7b65..2eb4366bf 100644 --- a/board/o2dnt/Makefile +++ b/board/o2dnt/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2005-2006 +# (C) Copyright 2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,28 +24,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o flash.o +OBJS := $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/o2dnt/flash.c b/board/o2dnt/flash.c index 349086ffb..037d28732 100644 --- a/board/o2dnt/flash.c +++ b/board/o2dnt/flash.c @@ -411,7 +411,7 @@ static int write_data (flash_info_t *info, FPWV *dest, FPW data) /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); return (2); } /* Disable interrupts which might cause a timeout here */ diff --git a/board/o2dnt/o2dnt.c b/board/o2dnt/o2dnt.c index a4eed3a43..81a27002f 100644 --- a/board/o2dnt/o2dnt.c +++ b/board/o2dnt/o2dnt.c @@ -67,7 +67,7 @@ static void sdram_start (int hi_addr) * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE * is something else than 0x00000000. */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; diff --git a/board/o2dnt/u-boot.lds b/board/o2dnt/u-boot.lds new file mode 100644 index 000000000..88dc118e8 --- /dev/null +++ b/board/o2dnt/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/omap1510inn/Makefile b/board/omap1510inn/Makefile index cd222dbc1..902b24ea1 100644 --- a/board/omap1510inn/Makefile +++ b/board/omap1510inn/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := omap1510innovator.o +OBJS := omap1510innovator.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/omap1510inn/u-boot.lds b/board/omap1510inn/u-boot.lds index e0c7920df..b6d16190f 100644 --- a/board/omap1510inn/u-boot.lds +++ b/board/omap1510inn/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/omap1610inn/Makefile b/board/omap1610inn/Makefile index 1adcad64e..456010232 100644 --- a/board/omap1610inn/Makefile +++ b/board/omap1610inn/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := omap1610innovator.o flash.o +OBJS := omap1610innovator.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/omap1610inn/lowlevel_init.S b/board/omap1610inn/lowlevel_init.S index e4ed9f3c6..cc8347fa1 100644 --- a/board/omap1610inn/lowlevel_init.S +++ b/board/omap1610inn/lowlevel_init.S @@ -58,7 +58,7 @@ lowlevel_init: str r1, [r0] /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * + * Set up ARM CLM registers (IDLECT2) * *------------------------------------------------------*/ ldr r0, REG_ARM_IDLECT2 ldr r1, VAL_ARM_IDLECT2 @@ -123,7 +123,7 @@ lock_end: /*------------------------------------------------------* * Turn off the watchdog during init... * - *------------------------------------------------------*/ + *------------------------------------------------------*/ disable_wd: ldr r0, REG_WATCHDOG ldr r1, WATCHDOG_VAL1 @@ -156,13 +156,13 @@ watch2Wait: * and branch to appropriate initialization code. */ /* Load physical SDRAM base. */ - mov r0, #0x10000000 + mov r0, #0x10000000 /* Get current execution location. */ - mov r1, pc + mov r1, pc /* Compare. */ - cmp r1, r0 + cmp r1, r0 /* Skip over EMIF-fast initialization if running from SDRAM. */ - bge skip_sdram + bge skip_sdram /* * Delay for SDRAM initialization. @@ -170,7 +170,7 @@ watch2Wait: mov r3, #0x1800 /* value should be checked */ 3: subs r3, r3, #0x1 /* Decrement count */ - bne 3b + bne 3b /* @@ -270,7 +270,7 @@ common_tc: #ifdef CONFIG_H2_OMAP1610 /* inserting additional 2 clock cycle hold time for LAN */ ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED + ldr r1, VAL_TC_EMIFS_CS1_ADVANCED str r1, [r0] #endif /* Start MPU Timer 1 */ diff --git a/board/omap1610inn/omap1610innovator.c b/board/omap1610inn/omap1610innovator.c index 2e04ad4bd..8dbe686a8 100644 --- a/board/omap1610inn/omap1610innovator.c +++ b/board/omap1610inn/omap1610innovator.c @@ -116,7 +116,7 @@ void flash__init (void) /************************************************************* Routine:ether__init Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. + for the EEPROM load to complete. *************************************************************/ void ether__init (void) { @@ -162,7 +162,7 @@ int dram_init (void) /****************************************************** Routine: set_muxconf_regs Description: Setting up the configuration Mux registers - specific to the hardware + specific to the hardware *******************************************************/ void set_muxconf_regs (void) { diff --git a/board/omap1610inn/u-boot.lds b/board/omap1610inn/u-boot.lds index a4fcd1a9b..710b2a2d6 100644 --- a/board/omap1610inn/u-boot.lds +++ b/board/omap1610inn/u-boot.lds @@ -47,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/omap1710h3/Makefile b/board/omap1710h3/Makefile new file mode 100644 index 000000000..2cb6e8978 --- /dev/null +++ b/board/omap1710h3/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omap1710h3.o flash.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap1710h3/config.mk b/board/omap1710h3/config.mk new file mode 100644 index 000000000..d9e3c7638 --- /dev/null +++ b/board/omap1710h3/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2004 +# Texas Instruments, +# Kshitij Gupta +# +# TI H3 board with OMAP1710 (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Innovator has 1 bank of 256 MB SDRAM +# Physical Address: +# 1000'0000 to 2000'0000 +# +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 +# (mem base + reserved) +# +# we load ourself to 1108'0000 +# +# + +PLATFORM_LDFLAGS += -no-warn-mismatch +TEXT_BASE = 0x11080000 diff --git a/board/omap1710h3/flash.c b/board/omap1710h3/flash.c new file mode 100644 index 000000000..75dbc3477 --- /dev/null +++ b/board/omap1710h3/flash.c @@ -0,0 +1,495 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ +flash_info_t flash_info[CFG_MAX_MTD_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256L18T[] = { + {4, 32 * 1024}, /* 4 * 32kBytes sectors */ + {255, 128 * 1024}, /* 255 * 128kBytes sectors */ +}; + + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); +void flash_unlock(flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + /* to reset the lock bit */ + flash_unlock(&flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ +#ifdef CFG_NAND_BOOT +#else + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_unlock(flash_info_t * info) +{ + int j; + for (j=2;jstart[j]); + flash_unprotect_sectors (addr); + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + } +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + OrgDef *pOrgDef; + + pOrgDef = OrgIntel_28F256L18T; + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + if (i > 255) { + info->start[i] = base + (i * 0x8000); + info->protect[i] = 0; + } else { + info->start[i] = base + + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; + info->size = 0x02000000; + break; /* => 32 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ +#define PD_FINTEL_WSMS_READY_MASK 0x0080 + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + flash_unprotect_sectors (addr); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00200020;/* erase setup */ + *addr = (FPW) 0x00D000D0;/* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + /* reset to read mode */ + *addr = (FPW) 0x00FF00FF; + rcode = 1; + break; + } + } + + /* clear status register cmd. */ + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/omap1710h3/lowlevel_init.S b/board/omap1710h3/lowlevel_init.S new file mode 100644 index 000000000..a969c84c3 --- /dev/null +++ b/board/omap1710h3/lowlevel_init.S @@ -0,0 +1,441 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_OMAP1710) +#include <./configs/omap1510.h> +#endif + + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +.globl lowlevel_init +lowlevel_init: + + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT1) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT1 + ldr r1, VAL_ARM_IDLECT1 + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT2) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT2 + ldr r1, VAL_ARM_IDLECT2 + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT3) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT3 + ldr r1, VAL_ARM_IDLECT3 + str r1, [r0] + + + mov r1, #0x05 /* PER_EN bit */ + ldr r0, REG_ARM_RSTCT2 + strh r1, [r0] /* CLKM; Peripheral reset. */ + + /* Set CLKM to Sync-Scalable */ + /* I supposedly need to enable the dsp clock before switching */ + ldr r1, VAL_ARM_SYSST + ldr r0, REG_ARM_SYSST + strh r1, [r0] + mov r0, #0x400 +1: + subs r0, r0, #0x1 /* wait for any bubbles to finish */ + bne 1b + ldr r1, VAL_ARM_CKCTL + ldr r0, REG_ARM_CKCTL + strh r1, [r0] + + /* a few nops to let settle */ + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* setup DPLL 1 */ + /* Ramp up the clock to 96Mhz */ + ldr r1, VAL_DPLL1_CTL + ldr r0, REG_DPLL1_CTL + strh r1, [r0] + ands r1, r1, #0x10 /* Check if PLL is enabled. */ + beq lock_end /* Do not look for lock if BYPASS selected */ +2: + ldrh r1, [r0] + ands r1, r1, #0x01 /* Check the LOCK bit.*/ + beq 2b /* loop until bit goes hi. */ +lock_end: + + + /*------------------------------------------------------* + * Turn off the watchdog during init... * + *------------------------------------------------------*/ + ldr r0, REG_WATCHDOG + ldr r1, WATCHDOG_VAL1 + str r1, [r0] + ldr r1, WATCHDOG_VAL2 + str r1, [r0] + ldr r0, REG_WSPRDOG + ldr r1, WSPRDOG_VAL1 + str r1, [r0] + ldr r0, REG_WWPSDOG + +watch1Wait: + ldr r1, [r0] + tst r1, #0x10 + bne watch1Wait + + ldr r0, REG_WSPRDOG + ldr r1, WSPRDOG_VAL2 + str r1, [r0] + ldr r0, REG_WWPSDOG +watch2Wait: + ldr r1, [r0] + tst r1, #0x10 + bne watch2Wait + + + /* Set memory timings corresponding to the new clock speed */ + + /* Check execution location to determine current execution location + * and branch to appropriate initialization code. + */ + /* Load physical SDRAM base. */ + mov r0, #0x10000000 + /* Get current execution location. */ + mov r1, pc + /* Compare. */ + cmp r1, r0 + /* Skip over EMIF-fast initialization if running from SDRAM. */ + bge skip_sdram + + /* Enable EMIFF TC Doubler in OMAP1710 */ + ldr r0, REG_EMIFF_DOUBLER + mov r1, #0x1 + str r1, [r0] + + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 /* value should be checked */ +3: + subs r3, r3, #0x1 /* Decrement count */ + bne 3b + + + /* + * Set SDRAM control values. Disable refresh before MRS command. + */ + + /* mobile ddr operation */ + ldr r0, REG_SDRAM_OPERATION + mov r2, #07 + str r2, [r0] + + /* config register */ + ldr r0, REG_SDRAM_CONFIG + ldr r1, SDRAM_CONFIG_VAL + str r1, [r0] + + /* manual command register */ + ldr r0, REG_SDRAM_MANUAL_CMD + /* issue set cke high */ + mov r1, #CMD_SDRAM_CKE_SET_HIGH + str r1, [r0] + /* issue nop */ + mov r1, #CMD_SDRAM_NOP + str r1, [r0] + + mov r2, #0x0100 +waitMDDR1: + subs r2, r2, #1 + bne waitMDDR1 /* delay loop */ + + /* issue precharge */ + mov r1, #CMD_SDRAM_PRECHARGE + str r1, [r0] + + + /* issue autorefresh x 2 */ + mov r1, #CMD_SDRAM_AUTOREFRESH + str r1, [r0] + str r1, [r0] + + /* mrs register ddr mobile */ + ldr r0, REG_SDRAM_MRS + mov r1, #0x33 + str r1, [r0] + + /* emrs1 low-power register */ + ldr r0, REG_SDRAM_EMRS1 + /* self refresh on all banks */ + mov r1, #0 + str r1, [r0] + + ldr r0, REG_DLL_URD_CONTROL + ldr r1, DLL_URD_CONTROL_VAL + str r1, [r0] + + ldr r0, REG_DLL_LRD_CONTROL + ldr r1, DLL_LRD_CONTROL_VAL + str r1, [r0] + + ldr r0, REG_DLL_WRT_CONTROL + ldr r1, DLL_WRT_CONTROL_VAL + str r1, [r0] + + /* delay loop */ + mov r2, #0x0100 +waitMDDR2: + subs r2, r2, #1 + bne waitMDDR2 + + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 +4: + subs r3, r3, #1 /* Decrement count. */ + bne 4b + b common_tc + +skip_sdram: + + ldr r0, REG_SDRAM_CONFIG + ldr r1, SDRAM_CONFIG_VAL + str r1, [r0] + +common_tc: + /* slow interface */ + ldr r1, VAL_TC_EMIFS_CONFIG + ldr r0, REG_TC_EMIFS_CONFIG + str r1, [r0] + + ldr r1, VAL_TC_EMIFS_CS0_CONFIG + ldr r0, REG_TC_EMIFS_CS0_CONFIG + str r1, [r0] /* Chip Select 0 */ + + ldr r1, VAL_TC_EMIFS_CS1_CONFIG + ldr r0, REG_TC_EMIFS_CS1_CONFIG + str r1, [r0] /* Chip Select 1 */ + + ldr r1, VAL_TC_EMIFS_CS3_CONFIG + ldr r0, REG_TC_EMIFS_CS3_CONFIG + str r1, [r0] /* Chip Select 3 */ + + /* inserting additional 2 clock cycle hold time for testing LAN */ + ldr r0, REG_TC_EMIFS_CS1_ADVANCED + ldr r1, VAL_TC_EMIFS_CS1_ADVANCED + str r1, [r0] + + /* Start MPU Timer 1 */ + ldr r0, REG_MPU_LOAD_TIMER + ldr r1, VAL_MPU_LOAD_TIMER + str r1, [r0] + + ldr r0, REG_MPU_CNTL_TIMER + ldr r1, VAL_MPU_CNTL_TIMER + str r1, [r0] + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + + +REG_TC_EMIFS_CONFIG: /* 32 bits */ + .word 0xfffecc0c +REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ + .word 0xfffecc10 +REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ + .word 0xfffecc14 +REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ + .word 0xfffecc18 +REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ + .word 0xfffecc1c +REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ + .word 0xfffecc54 + +/* MPU clock/reset/power mode control registers */ +REG_ARM_CKCTL: /* 16 bits */ + .word 0xfffece00 + +REG_ARM_IDLECT3: /* 16 bits */ + .word 0xfffece24 +REG_ARM_IDLECT2: /* 16 bits */ + .word 0xfffece08 +REG_ARM_IDLECT1: /* 16 bits */ + .word 0xfffece04 + +REG_ARM_RSTCT2: /* 16 bits */ + .word 0xfffece14 +REG_ARM_SYSST: /* 16 bits */ + .word 0xfffece18 +/* DPLL control registers */ +REG_DPLL1_CTL: /* 16 bits */ + .word 0xfffecf00 + +/* Watch Dog register */ +/* secure watchdog stop */ +REG_WSPRDOG: + .word 0xfffeb048 +/* watchdog write pending */ +REG_WWPSDOG: + .word 0xfffeb034 + +WSPRDOG_VAL1: + .word 0x0000aaaa +WSPRDOG_VAL2: + .word 0x00005555 + +/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, + counter @8192 rows, 10 ns, 8 burst */ +REG_SDRAM_CONFIG: + .word 0xfffecc20 + +/* Operation register */ +REG_SDRAM_OPERATION: + .word 0xfffecc80 + +REG_EMIFF_DOUBLER: + .word 0xfffecc60 + +/* Manual command register */ +REG_SDRAM_MANUAL_CMD: + .word 0xfffecc84 + +/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ +REG_SDRAM_MRS: + .word 0xfffecc70 + +/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ +REG_SDRAM_EMRS1: + .word 0xfffecc78 + +/* WRT DLL register */ +REG_DLL_WRT_CONTROL: + .word 0xfffecc64 +DLL_WRT_CONTROL_VAL: + .word 0x03500002 + +/* URD DLL register */ +REG_DLL_URD_CONTROL: + .word 0xfffeccc0 +DLL_URD_CONTROL_VAL: + .word 0x00000006 + +/* LRD DLL register */ +REG_DLL_LRD_CONTROL: + .word 0xfffecccc + +REG_WATCHDOG: + .word 0xfffec808 + +REG_MPU_LOAD_TIMER: + .word 0xfffec600 +REG_MPU_CNTL_TIMER: + .word 0xfffec500 + +/* 96 MHz Samsung Mobile DDR */ +SDRAM_CONFIG_VAL: + .word 0x0c028af4 + +DLL_LRD_CONTROL_VAL: + .word 0x00000006 + +VAL_ARM_CKCTL: + .word 0x350e +VAL_ARM_SYSST: + .word 0x1001 + +VAL_DPLL1_CTL: + .word 0x2810 + +VAL_TC_EMIFS_CONFIG: +#ifdef CFG_NAND_BOOT + .word 0x00000010 +#else + .word 0x00000012 +#endif + +VAL_TC_EMIFS_CS0_CONFIG: + .word 0x0000fffb +VAL_TC_EMIFS_CS1_CONFIG: + .word 0x81808cc3 +VAL_TC_EMIFS_CS2_CONFIG: + .word 0xf800f22a +VAL_TC_EMIFS_CS3_CONFIG: +#ifdef CFG_NAND_BOOT + .word 0xff80fff3 +#else + .word 0x98011031 +#endif +VAL_TC_EMIFS_CS1_ADVANCED: + .word 0x00000022 + +VAL_TC_EMIFF_SDRAM_CONFIG: + .word 0x010290fc +VAL_TC_EMIFF_MRS: + .word 0x00000027 + +VAL_ARM_IDLECT1: + .word 0x000014c6 + +VAL_ARM_IDLECT2: + .word 0x000009ff +VAL_ARM_IDLECT3: + .word 0x0000003f + +WATCHDOG_VAL1: + .word 0x000000f5 +WATCHDOG_VAL2: + .word 0x000000a0 + +VAL_MPU_LOAD_TIMER: + .word 0xffffffff +VAL_MPU_CNTL_TIMER: + .word 0xffffffa1 + +/* command values */ +.equ CMD_SDRAM_NOP, 0x00000000 +.equ CMD_SDRAM_PRECHARGE, 0x00000001 +.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 +.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/omap1710h3/omap1710h3.c b/board/omap1710h3/omap1710h3.c new file mode 100644 index 000000000..b9fa1ff2f --- /dev/null +++ b/board/omap1710h3/omap1710h3.c @@ -0,0 +1,309 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_OMAP1710) +#include <./configs/omap1510.h> +#endif +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +#endif + + +void flash__init (void); +void ether__init (void); +void set_muxconf_regs (void); +void peripheral_power_enable (void); + +#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of OMAP1710 H3 */ + gd->bd->bi_arch_number = 509; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + /* Configure MUX settings */ + set_muxconf_regs (); + peripheral_power_enable (); + +/* this speeds up your boot a quite a bit. However to make it + * work, you need make sure your kernel startup flush bug is fixed. + * ... rkw ... + */ + icache_enable (); + + flash__init (); + ether__init (); + return 0; +} + + +int misc_init_r (void) +{ + /* currently empty */ + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +void flash__init (void) +{ +#define EMIFS_GlB_Config_REG 0xfffecc0c + unsigned int regval; + regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); + /* Turn off write protection for flash devices. */ + regval = regval | 0x0001; + *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; +} +/************************************************************* + Routine:ether__init + Description: take the Ethernet controller out of reset and wait + for the EEPROM load to complete. +*************************************************************/ +void ether__init (void) +{ + #define LAN_RESET_REGISTER 0x0400001c + #define ETH_CONTROL_REG 0x0400030b + + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; + do { + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; + udelay (3); + } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); + + do { + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; + udelay (3); + } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); + + *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; + udelay (3); +} + +/****************************** + Routine: + Description: +******************************/ +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +/****************************************************** + Routine: set_muxconf_regs + Description: Setting up the configuration Mux registers + specific to the hardware +*******************************************************/ +void set_muxconf_regs (void) +{ + volatile unsigned int *MuxConfReg; + /* set each registers to its reset value; */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); + /* setup for UART1 */ + *MuxConfReg &= ~(0x02000000); /* bit 25 */ + /* setup for UART2 */ + *MuxConfReg &= ~(0x01000000); /* bit 24 */ + /* Disable Uwire CS Hi-Z */ + *MuxConfReg |= 0x08000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); + /*setup mux for UART3 */ + *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ + *MuxConfReg &= ~0x0000003e; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); + /* Disable Uwire CS Hi-Z */ + *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); + /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ + /* hardware will actually use TX and RTS based on bit 25 in */ + /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ + *MuxConfReg |= 0x00201000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); + *MuxConfReg = 0x00006000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); + /* setup for UART2 */ + /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ + /* hardware will actually use TX and RTS based on bit 24 in */ + /* FUNC_MUX_CTRL_0. */ + *MuxConfReg |= 0x09000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); + *MuxConfReg = 0x00000000; + /* mux setup for SD/MMC driver */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); + *MuxConfReg &= 0xFFFE0FFF; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); + /* bit 13 for MMC2 XOR_CLK */ + *MuxConfReg &= ~(0x00002000); + /* bit 29 for UART 1 */ + *MuxConfReg &= ~(0x00002000); + MuxConfReg = + (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); + /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ + *MuxConfReg |= 0x000C0000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); + *MuxConfReg &= ~(0x00000070); + *MuxConfReg &= ~(0x00000008); + *MuxConfReg |= 0x00000003; + *MuxConfReg |= 0x00000180; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); + /* bit 17, software controls VBUS */ + *MuxConfReg &= ~(0x00020000); + /* Enable USB 48 and 12M clocks */ + *MuxConfReg |= 0x00000200; + *MuxConfReg &= ~(0x00000180); + /*2.75V for MMCSDIO1 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); + *MuxConfReg = 0x00001FE7; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); + *MuxConfReg = 0x00000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); + *MuxConfReg = 0x00000000; + /* Turn on UART2 48 MHZ clock */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); + *MuxConfReg |= 0x40000000; + MuxConfReg = + (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); + /* setup for USB VBus detection OMAP161x & OMAP1710 */ + *MuxConfReg |= 0x00040000; /* bit 18 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); + /* PullUps for SD/MMC driver */ + *MuxConfReg |= ~(0xFFFE0FFF); + MuxConfReg = + (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); + *MuxConfReg = COMP_MODE_ENABLE; +} + +/****************************************************** + Routine: peripheral_power_enable + Description: Enable the power for UART1 +*******************************************************/ +void peripheral_power_enable (void) +{ +#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) +#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) + + *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; +} + + + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +void nand_init(void) +{ + extern flash_info_t flash_info[]; + + nand_probe(CFG_NAND_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } + +#ifdef CFG_JFFS2_MEM_NAND + flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; + flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */ + flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ + flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x10200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */ +#endif +} +#endif + diff --git a/board/omap1710h3/u-boot.lds b/board/omap1710h3/u-boot.lds new file mode 100644 index 000000000..eee4813f3 --- /dev/null +++ b/board/omap1710h3/u-boot.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap2420h4/Makefile b/board/omap2420h4/Makefile index f39eef0ad..ed4786879 100644 --- a/board/omap2420h4/Makefile +++ b/board/omap2420h4/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := omap2420h4.o mem.o sys_info.o +OBJS := omap2420h4.o mem.o sys_info.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/omap2420h4/flash.c b/board/omap2420h4/flash.c new file mode 100644 index 000000000..d5e106a5e --- /dev/null +++ b/board/omap2420h4/flash.c @@ -0,0 +1,537 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#define PHYS_FLASH_SECT_SIZE SZ_128K +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +# define FLASH_PORT_WIDTH ushort +# define FLASH_PORT_WIDTHV vu_short +# define SWAP(x) __swab16(x) +#else +# define FLASH_PORT_WIDTH ulong +# define FLASH_PORT_WIDTHV vu_long +# define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256L18T[] = { + {4, SZ_32K}, /* 4 * 32kBytes sectors */ + {255, SZ_128K}, /* 255 * 128kBytes sectors */ +}; + + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); +void flash_unlock(flash_info_t * info, int bank); +int flash_probe(void); + +/*----------------------------------------------------------------------- + */ + +/* see if flash is ok */ +int flash_probe(void) +{ + return(flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[0])); +} + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + /* to reset the lock bit */ + flash_unlock(&flash_info[i],i); + break; + case 1: + flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); + /* to reset the lock bit */ + flash_unlock(&flash_info[i],i); + break; + + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + +#ifdef CFG_ENV_IS_IN_FLASH + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_unlock(flash_info_t * info, int bank) +{ + int j; + if (!bank) + j=2; /* leave 0,1 locked for boot bank */ + else + j=0; /* get the whole bank for #2 */ + + for (;jstart[j]); + if (addr == NULL) { + printf("Warning Flash probe failed\n"); + break; + } + flash_unprotect_sectors (addr); + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + } +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + volatile int r; /* gcc 3.4.0-1 strangeness, need to follow up.*/ + + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + if (i > 254) { /* 255,256,257,258 */ + r=i; + info->start[i] = base + (((r-(int)255) * SZ_32K) + (255*PHYS_FLASH_SECT_SIZE)); + info->protect[i] = 0; + } else { + info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + /* mb(); this one makes ARM11 err go away, but I want it :) as a guide to problems */ + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0] & 0xFF; /* just looking for 89 (8989 is hw pat)*/ + + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return(0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): /* 880D */ + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; /*0-258*/ + info->size = SZ_32M; + break; /* => 32 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return(info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ +#define PD_FINTEL_WSMS_READY_MASK 0x0080 + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int prot, sect; + ulong type, start, last; + int rcode = 0; +#ifdef CONFIG_USE_IRQ + int iflag; +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + start = get_timer (0); + last = start; + +#ifdef CONFIG_USE_IRQ + /* Disable interrupts which might cause a timeout here */ + iflag = disable_interrupts (); +#endif + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + flash_unprotect_sectors (addr); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00200020;/* erase setup */ + *addr = (FPW) 0x00D000D0;/* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + /* reset to read mode */ + *addr = (FPW) 0x00FF00FF; + rcode = 1; + break; + } + } + + /* clear status register cmd. */ + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + printf (" done\n"); + } + } +#ifdef CONFIG_USE_IRQ + if (iflag) + enable_interrupts(); +#endif + + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return(rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return(rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return(0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return(write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; +#ifdef CONFIG_USE_IRQ + int iflag; +#endif + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return(2); + } + /* Disable interrupts which might cause a timeout here */ +#ifdef CONFIG_USE_IRQ + iflag = disable_interrupts (); +#endif + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return(1); + } + } + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + +#ifdef CONFIG_USE_IRQ + if (iflag) + enable_interrupts(); +#endif + + return(0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/omap2420h4/lowlevel_init.S b/board/omap2420h4/lowlevel_init.S index 9752fc488..65bc326e3 100644 --- a/board/omap2420h4/lowlevel_init.S +++ b/board/omap2420h4/lowlevel_init.S @@ -26,13 +26,14 @@ #include #include -#include +#include #include #include _TEXT_BASE: .word TEXT_BASE /* sdram load addr from config.mk */ +#ifndef CFG_NAND_BOOT /************************************************************************** * cpy_clk_code: relocates clock code into SRAM where its safer to execute * R1 = SRAM destination address. @@ -82,17 +83,18 @@ block: /* now prepare GPMC (flash) for new dpll speed */ /* flash needs to be stable when we jump back to it */ - ldr r4, cfg3_0_addr - ldr r8, cfg3_0_val - str r8, [r4] - ldr r4, cfg4_0_addr - ldr r8, cfg4_0_val - str r8, [r4] - ldr r4, cfg1_0_addr + ldr r4, flash_cfg3_addr + ldr r8, flash_cfg3_val + str r8, [r4] + ldr r4, flash_cfg4_addr + ldr r8, flash_cfg4_val + str r8, [r4] + ldr r4, flash_cfg1_addr ldr r8, [r4] orr r8, r8, #0x3 /* up gpmc divider */ str r8, [r4] + /* setup to 2x loop though code. The first loop pre-loads the * icache, the 2nd commits the prcm config, and locks the dpll */ @@ -139,16 +141,17 @@ lloop2: _go_to_speed: .word go_to_speed /* these constants need to be close for PIC code */ -cfg3_0_addr: - .word GPMC_CONFIG3_0 -cfg3_0_val: - .word H4_24XX_GPMC_CONFIG3_0 -cfg4_0_addr: - .word GPMC_CONFIG4_0 -cfg4_0_val: - .word H4_24XX_GPMC_CONFIG4_0 -cfg1_0_addr: - .word GPMC_CONFIG1_0 +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) pll_ctl_add: .word CM_CLKEN_PLL pll_stat: @@ -158,6 +161,8 @@ pll_div_add: pll_div_val: .word DPLL_VAL /* DPLL setting (300MHz default) */ +#endif + .globl lowlevel_init lowlevel_init: ldr sp, SRAM_STACK diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c index a3295fd4e..5521037da 100644 --- a/board/omap2420h4/mem.c +++ b/board/omap2420h4/mem.c @@ -20,14 +20,54 @@ */ #include -#include +#include #include #include -#include #include #include #include #include +#include + +/****** DATA STRUCTURES ************/ + +/* Only One NAND/NOR allowed on board at a time. + * The GPMC CS Base for the same + */ +static u32 nand_cs_base = 0; +/* Board CS Organization - REV 0.1 */ +static const unsigned char chip_sel[][GPMC_MAX_CS] = { + /* GPMC CS Indices */ +/* IDX CS0, CS1, CS2 ..CS7 */ +/* 0 */ {PROC_NOR, DBG_MPDB, 0, 0, 0, 0, 0, 0}, +/* 1 */ {PROC_NAND, DBG_MPDB, 0, 0, 0, 0, 0,0}, +}; + +/* Values for each of the chips */ +static u32 gpmc_mpdb[GPMC_MAX_REG] = { + MPDB_GPMC_CONFIG1, + MPDB_GPMC_CONFIG2, + MPDB_GPMC_CONFIG3, + MPDB_GPMC_CONFIG4, + MPDB_GPMC_CONFIG5, + MPDB_GPMC_CONFIG6, 0 +}; +static u32 gpmc_stnor[GPMC_MAX_REG] = { + STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, 0 +}; +static u32 gpmc_smnand[GPMC_MAX_REG] = { + SMNAND_GPMC_CONFIG1, + SMNAND_GPMC_CONFIG2, + SMNAND_GPMC_CONFIG3, + SMNAND_GPMC_CONFIG4, + SMNAND_GPMC_CONFIG5, + SMNAND_GPMC_CONFIG6, 0 +}; /************************************************************ * sdelay() - simple spin loop. Will be constant time as @@ -48,12 +88,18 @@ void sdelay (unsigned long loops) *********************************************************************************/ void prcm_init(void) { - u32 div; + u32 val, div; void (*f_lock_pll) (u32, u32, u32, u32); extern void *_end_vect, *_start; f_lock_pll = (void *)((u32)&_end_vect - (u32)&_start + SRAM_VECT_CODE); + val = __raw_readl(PRCM_CLKSRC_CTRL) & ~(BIT1|BIT0); +#if defined(OMAP2430_SQUARE_CLOCK_INPUT) + __raw_writel(val, PRCM_CLKSRC_CTRL); +#else + __raw_writel((val | BIT0), PRCM_CLKSRC_CTRL); +#endif __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */ __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */ __raw_writel(0, CM_ICLKEN1_CORE); @@ -120,14 +166,16 @@ void make_cs1_contiguous(void) *******************************************************/ u32 mem_ok(void) { - u32 val1, val2; + u32 val1, val2, addr; u32 pattern = 0x12345678; - __raw_writel(0x0,OMAP2420_SDRC_CS0+0x400); /* clear pos A */ - __raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */ - __raw_writel(0x0,OMAP2420_SDRC_CS0+4); /* remove pattern off the bus */ - val1 = __raw_readl(OMAP2420_SDRC_CS0+0x400); /* get pos A value */ - val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */ + addr = OMAP24XX_SDRC_CS0; + + __raw_writel(0x0,addr+0x400); /* clear pos A */ + __raw_writel(pattern, addr); /* pattern to pos B */ + __raw_writel(0x0,addr+4); /* remove pattern off the bus */ + val1 = __raw_readl(addr+0x400); /* get pos A value */ + val2 = __raw_readl(addr); /* get val2 */ if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed*/ return(0); @@ -159,12 +207,14 @@ void sdrc_init(void) * we configure the first chip select. Later on we come back and * will configure the 2nd chip select if it exists. * + * For 2422 rev > ES2 only one pass is used as it only has memory on CS1. **************************************************************************/ void do_sdrc_init(u32 offset, u32 early) { - u32 cpu, dllen=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype; + u32 cpu, dllstat, dllctrl=0, rev, common=0, cs0=0, pmask=0, pass_type, mtype; sdrc_data_t *sdata; /* do not change type */ - u32 a, b, r; + u32 a, b, r, dllx = 0, mono = 0, dev; + void init_dcdl(u32 cpu); static const sdrc_data_t sdrc_2422 = { @@ -184,15 +234,25 @@ void do_sdrc_init(u32 offset, u32 early) cs0 = common = 1; /* int regs shared between both chip select */ cpu = get_cpu_type(); + dev = get_device_type(); rev = get_cpu_rev(); /* warning generated, though code generation is correct. this may bite later, * but is ok for now. there is only so much C code you can do on stack only * operation. */ - if (cpu == CPU_2422){ + if ((cpu == CPU_2422) || (cpu == CPU_2423)){ sdata = (sdrc_data_t *)&sdrc_2422; pass_type = STACKED; + if(rev > CPU_242X_ES2){ /* es2.05 and beyond changed SIP memory */ + if((!early) && (cpu == CPU_2422)) /* no work for pass 2 on 2422 rev>es2 */ + return; + if (cpu == CPU_2422) { + offset = SDRC_CS1_OSET; /* set common access offset to cs1 */ + cs0 = 0; /* specify acting on CS1 */ + mono = 1; /* flag mono die for 2422 */ + } + } } else{ sdata = (sdrc_data_t *)&sdrc_2420; pass_type = IP_DDR; @@ -209,8 +269,14 @@ void do_sdrc_init(u32 offset, u32 early) if((early) && running_in_flash()){ sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base()); /* NOR internal boot offset is 0x4000 from xloader signature */ - if(running_from_internal_boot()) - sdata = (sdrc_data_t *)((u32)sdata + 0x4000); + if(running_from_internal_boot()){ + u32 start_off; + if(dev == GP_DEVICE) + start_off = 0x8; + else + start_off = 0x4000; + sdata = (sdrc_data_t *)((u32)sdata + start_off); + } } if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) { @@ -219,7 +285,7 @@ void do_sdrc_init(u32 offset, u32 early) pass_type = COMBO_DDR; /* CS1 config */ __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, SDRC_POWER); } - if(rev != CPU_2420_2422_ES1) /* for es2 and above smooth things out */ + if(rev != CPU_242X_ES1) /* for es2 and above smooth things out */ make_cs1_contiguous(); } @@ -228,7 +294,10 @@ next_mem_type: __raw_writel(SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */ wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);/* wait till reset done set */ __raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */ - __raw_writel(sdata->sdrc_sharing, SDRC_SHARING); + if (cpu != CPU_2423) + __raw_writel(sdata->sdrc_sharing, SDRC_SHARING); + else + __raw_writel(H4_2423_SDRC_SHARING, SDRC_SHARING); #ifdef POWER_SAVE __raw_writel(__raw_readl(SMS_SYSCONFIG)|SMART_IDLE, SMS_SYSCONFIG); __raw_writel(sdata->sdrc_sharing|SMART_IDLE, SDRC_SHARING); @@ -236,9 +305,17 @@ next_mem_type: #endif } - if ((pass_type == IP_DDR) || (pass_type == STACKED)) /* (IP ddr-CS0),(2422-CS0/CS1) */ + if ((pass_type == IP_DDR) || (pass_type == STACKED)){ /* (IP ddr-CS0),(2422-CS0/CS1) */ __raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0+offset); - else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */ + if(mono) + __raw_writel(H4_2422_SDRC_MDCFG_MONO_DDR, SDRC_MCFG_0+offset); /* 2422.es2.05-CS1 */ + if (cpu == CPU_2423) { + if (offset == SDRC_CS1_OSET) + __raw_writel(H4_2423_SDRC_MDCFG_1_DDR, SDRC_MCFG_0+offset); /* 2423 32M-CS1 */ + else + __raw_writel(H4_2423_SDRC_MDCFG_0_DDR, SDRC_MCFG_0+offset); /* 2423 64M-CS0 */ + } + }else if (pass_type == COMBO_DDR){ /* (combo-CS0/CS1) */ __raw_writel(H4_2420_COMBO_MDCFG_0_DDR,SDRC_MCFG_0+offset); } else if (pass_type == IP_SDR){ /* ip sdr-CS0 */ __raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0+offset); @@ -246,14 +323,14 @@ next_mem_type: a = sdata->sdrc_actim_ctrla_0; b = sdata->sdrc_actim_ctrlb_0; - r = sdata->sdrc_dllab_ctrl; + r = sdata->sdrc_rfr_ctrl; /* work around ES1 DDR issues */ - if((pass_type != IP_SDR) && (rev == CPU_2420_2422_ES1)){ + if((pass_type != IP_SDR) && (rev == CPU_242X_ES1)){ a = H4_242x_SDRC_ACTIM_CTRLA_0_ES1; b = H4_242x_SDRC_ACTIM_CTRLB_0_ES1; r = H4_242x_SDRC_RFR_CTRL_ES1; - } + } if (cs0) { __raw_writel(a, SDRC_ACTIM_CTRLA_0); @@ -283,24 +360,49 @@ next_mem_type: __raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0+offset); /* NOTE: ES1 242x _BUG_ DLL + External Bandwidth fix*/ - if (rev == CPU_2420_2422_ES1){ - dllen = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */ + if (rev == CPU_242X_ES1){ + dllctrl = (BIT0|BIT3); /* es1 clear both bit0 and bit3 */ __raw_writel((__raw_readl(SMS_CLASS_ARB0)|BURSTCOMPLETE_GROUP7) ,SMS_CLASS_ARB0);/* enable bust complete for lcd */ - } - else - dllen = BIT0|BIT1; /* es2, clear bit0, and 1 (set phase to 72) */ + }else + + dllctrl = BIT0; /* es2, flag to clear bit0 (90deg for < 133MHz && ES2) */ + +#ifdef PRCM_CONFIG_I + /* es2.1, flag clear bit1 (set phase to 72 for > 150MHz && ES2) */ + dllctrl |= DLLPHASE; +#endif /* enable & load up DLL with good value for 75MHz, and set phase to 90 * ES1 recommends 90 phase, ES2 recommends 72 phase. */ if (common && (pass_type != IP_SDR)) { __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL); - __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen), SDRC_DLLA_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl & ~(LOADDLL|dllctrl), SDRC_DLLA_CTRL); __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL); - __raw_writel(sdata->sdrc_dllab_ctrl & ~(BIT2|dllen) , SDRC_DLLB_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl & ~(LOADDLL|dllctrl) , SDRC_DLLB_CTRL); + + init_dcdl(cpu); /* fix errata for possible bad init state */ + + sdelay(0x2000); /* give time to lock, at least 1000 L3 */ + + if(rev >= CPU_242X_ES2){ /* work around DCDL MOD16 bug */ + if ((cpu == CPU_2422) && (rev > CPU_242X_ES2)) + dllx = 8; + dllctrl = __raw_readl(SDRC_DLLA_CTRL+dllx); /* get cur ctrl value */ + dllctrl &= ~(DLL_DELAY_MASK); /* prepare for load new value */ + dllctrl |= LOADDLL; /* prepare for load + unlock mode */ + dllstat = (__raw_readl(SDRC_DLLA_STATUS+dllx) & DLL_DELAY_MASK); + dllctrl |= dllstat; /* prepare new dll load delay */ + dllctrl |= DLL_NO_FILTER_MASK; /* make sure filter is off */ + __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* go to unlock modeA */ + __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* go to unlock modeB */ + } } - sdelay(90000); + sdelay(0x1000); + + if(mono) /* 2422 ES2.05 and beyound only has 1 pass */ + make_cs1_contiguous();/* make CS1 appear at CS0 */ if(mem_ok()) return; /* STACKED, other configued type */ @@ -308,6 +410,44 @@ next_mem_type: goto next_mem_type; } +/***************************************************** + * init_dcdl(): Fix errata - unitilized flip-flop. + *****************************************************/ +void init_dcdl(u32 cpu) +{ + volatile u8 *adqs[4]; + u8 vdqs[4], idx, i; + u32 base = OMAP24XX_CTRL_BASE; + + if((cpu == CPU_2422) || (cpu == CPU_2423)){ + adqs[0] = ((volatile u8*)(base + CONTROL_PADCONF_SDRC_STK_DM1 + 0x1)); + adqs[1] = ((volatile u8*)(base + CONTROL_PADCONF_SDRC_STK_DM1 + 0x2)); + idx = 2; + } else { + adqs[0] = ((volatile u8*)(base + CONTROL_PADCONF_SDRC_STK_DM1 + 0x3)); + adqs[1] = ((volatile u8*)(base + CONTROL_PADCONF_SDRC_DQS1 + 0x0)); + adqs[2] = ((volatile u8*)(base + CONTROL_PADCONF_SDRC_DQS1 + 0x1)); + adqs[3] = ((volatile u8*)(base + CONTROL_PADCONF_SDRC_DQS1 + 0x2)); + idx = 4; + } + + for(i = 0; i < idx; ++i) /* save origional state */ + vdqs[i] = *adqs[i]; + + for(i = 0; i < idx; ++i) + *adqs[i] = ((~0x10 & vdqs[i]) | 0x8); /* enable/activate pull down */ + + sdelay(0x400); + + for(i = 0; i < idx; ++i) + *adqs[i] = (vdqs[i] | 0x10); /* enable/activate pull up */ + + sdelay(0x400); + + for(i = 0; i < idx; ++i) /* restore state */ + *adqs[i] = vdqs[i]; +} + /***************************************************** * gpmc_init(): init gpmc bus * Init GPMC for x16, MuxMode (SDRAM in x32). @@ -315,61 +455,75 @@ next_mem_type: *****************************************************/ void gpmc_init(void) { - u32 mux=0, mtype, mwidth, rev, tval; + u32 mux=0, mwidth, rev, tval; + u8 idx = 0; + u32 *gpmc_config = NULL; + u32 gpmc_base = 0; + u32 base = 0; + u32 size = 0; + unsigned char *config_sel = + (unsigned char *)(chip_sel[FLASH_CONFIGURATION_IDX]); rev = get_cpu_rev(); - if (rev == CPU_2420_2422_ES1) + if (rev == CPU_242X_ES1) tval = 1; else tval = 0; /* disable bit switched meaning */ + /* discover bus connection from sysboot */ + if (is_gpmc_muxed() == GPMC_MUXED) + mux = BIT9; + + mwidth = get_gpmc0_width(); /* global settings */ __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ __raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CFG_NAND_BOOT - __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ -#else - __raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */ -#endif + /* For Nand based boot only..OneNand?? */ + if ((config_sel[0] == PROC_NAND) + || (config_sel[0] == PISMO_ONENAND)) { + __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ + } + for (; idx < GPMC_MAX_CS; idx++) { + if (!config_sel[idx]) { + continue; + } + gpmc_base = GPMC_CONFIG_CS0 + (idx * GPMC_CONFIG_WIDTH); + __raw_writel(0, GPMC_CONFIG7 + gpmc_base); + switch (config_sel[idx]) { + case PROC_NOR: + gpmc_config = gpmc_stnor; + gpmc_config[0] |= mux | TYPE_NOR | mwidth; + base = PROC_NOR_BASE; + size = PROC_NOR_SIZE; + break; + case PROC_NAND: + base = PROC_NAND_BASE; + size = PROC_NAND_SIZE; + gpmc_config = gpmc_smnand; + gpmc_config[0] |= mux | TYPE_NAND | mwidth; + /* Either OneNand or Normal Nand at a time!! */ + nand_cs_base = gpmc_base; + break; + case DBG_MPDB: + base = DBG_MPDB_BASE; + size = DBG_MPDB_SIZE; + gpmc_config = gpmc_mpdb; + gpmc_config[0] |= mux; + break; + default: + /* Corrupt config- try and recover by putting nor here!!!! */ + continue; + } + __raw_writel(gpmc_config[0], GPMC_CONFIG1 + gpmc_base); + __raw_writel(gpmc_config[1], GPMC_CONFIG2 + gpmc_base); + __raw_writel(gpmc_config[2], GPMC_CONFIG3 + gpmc_base); + __raw_writel(gpmc_config[3], GPMC_CONFIG4 + gpmc_base); + __raw_writel(gpmc_config[4], GPMC_CONFIG5 + gpmc_base); + __raw_writel(gpmc_config[5], GPMC_CONFIG6 + gpmc_base); + /* Enable the config */ + __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), GPMC_CONFIG7 + gpmc_base); + } - /* discover bus connection from sysboot */ - if (is_gpmc_muxed() == GPMC_MUXED) - mux = BIT9; - mtype = get_gpmc0_type(); - mwidth = get_gpmc0_width(); - - /* setup cs0 */ - __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ - sdelay(1000); - -#ifdef CFG_NAND_BOOT - __raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0); -#else - __raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0); -#endif - -#ifdef PRCM_CONFIG_III - __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); -#endif - __raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0); - __raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0); -#ifdef PRCM_CONFIG_III - __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); - __raw_writel(H4_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0); -#endif - __raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */ - sdelay(2000); - - /* setup cs1 */ - __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */ - sdelay(1000); - __raw_writel(H4_24XX_GPMC_CONFIG1_1|mux, GPMC_CONFIG1_1); - __raw_writel(H4_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1); - __raw_writel(H4_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1); - __raw_writel(H4_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1); - __raw_writel(H4_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1); - __raw_writel(H4_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1); - __raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */ - sdelay(2000); } diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index 09b070dc1..fb2d7da24 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -22,7 +22,7 @@ * MA 02111-1307 USA */ #include -#include +#include #include #include #include @@ -31,7 +31,7 @@ #include #include #include -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif @@ -59,7 +59,7 @@ int board_init (void) gpmc_init(); /* in SRAM or SDRM, finish GPMC */ gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */ - gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */ + gd->bd->bi_boot_params = (OMAP24XX_SDRC_CS0+0x100); /* adress of boot parameters */ return 0; } @@ -152,14 +152,14 @@ void wait_for_command_complete(unsigned int wd_base) /******************************************************************* * Routine:ether_init * Description: take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. + * for the EEPROM load to complete. ******************************************************************/ void ether_init (void) { #ifdef CONFIG_DRIVER_LAN91C96 int cnt = 20; - __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */ + __raw_writeb(0x3,OMAP24XX_CTRL_BASE+0x10a); /*protect->gpio95 */ __raw_writew(0x0, LAN_RESET_REGISTER); do { @@ -223,7 +223,7 @@ int dram_init (void) gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = size0; - if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */ + if(rev == CPU_242X_ES1) /* ES1's 128MB remap granularity isn't worth doing */ gd->bd->bi_dram[1].start = PHYS_SDRAM_2; else /* ES2 and above can remap at 32MB granularity */ gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; @@ -738,7 +738,7 @@ void muxSetupSDRC(void) *****************************************************************************/ void update_mux(u32 btype,u32 mtype) { - u32 cpu, base = OMAP2420_CTRL_BASE; + u32 cpu, base = OMAP24XX_CTRL_BASE; cpu = get_cpu_type(); if (btype == BOARD_H4_MENELAUS) { @@ -847,7 +847,7 @@ void update_mux(u32 btype,u32 mtype) } } -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) void nand_init(void) { extern flash_info_t flash_info[]; diff --git a/board/omap2420h4/sys_info.c b/board/omap2420h4/sys_info.c index a9f72412a..da6e11fef 100644 --- a/board/omap2420h4/sys_info.c +++ b/board/omap2420h4/sys_info.c @@ -50,13 +50,13 @@ u32 get_cpu_type(void) { u32 v; - switch(get_prod_id()){ - case 1:;/* 2420 */ - case 2: return(CPU_2420); break; /* 2420 pop */ - case 4: return(CPU_2422); break; - case 8: return(CPU_2423); break; - default: break; /* early 2420/2422's unmarked */ - } + v = get_prod_id(); + if((v == 1) || (v == 2)) + return CPU_2420; + else if (v == 4) + return CPU_2422; + else if (v == 8) + return CPU_2423; v = __raw_readl(TAP_IDCODE_REG); v &= CPU_24XX_ID_MASK; @@ -168,7 +168,7 @@ u32 get_gpmc0_base(void) { u32 b; - b = __raw_readl(GPMC_CONFIG7_0); + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); b &= 0x1F; /* keep base [5:0] */ b = b << 24; /* ret 0x0b000000 */ return(b); diff --git a/board/omap2420h4/u-boot.lds b/board/omap2420h4/u-boot.lds index aae716cb2..1460adcdd 100644 --- a/board/omap2420h4/u-boot.lds +++ b/board/omap2420h4/u-boot.lds @@ -54,6 +54,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/omap2430sdp/Makefile b/board/omap2430sdp/Makefile new file mode 100644 index 000000000..768c7c7b5 --- /dev/null +++ b/board/omap2430sdp/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omap2430sdp.o mem.o sys_info.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap2430sdp/config.mk b/board/omap2430sdp/config.mk new file mode 100644 index 000000000..9d9dfa294 --- /dev/null +++ b/board/omap2430sdp/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2004 +# Texas Instruments, +# +# SDP2430 boad uses OMAP2430 (ARM1136) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP2430 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# SDP2430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) ES2 will be configurable +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap2430sdp/lowlevel_init.S b/board/omap2430sdp/lowlevel_init.S new file mode 100644 index 000000000..814b50ebe --- /dev/null +++ b/board/omap2430sdp/lowlevel_init.S @@ -0,0 +1,197 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = PRCM_CLKCFG_CTRL - addr of valid reg + * R1 = CM_CLKEN_PLL - addr dpll ctlr reg + * R2 = dpll value + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + ******************************************************************************/ +.global go_to_speed + go_to_speed: + sub sp, sp, #0x4 /* get some stack space */ + str r4, [sp] /* save r4's value */ + + /* move into fast relock bypass */ + ldr r8, pll_ctl_add + mov r4, #0x2 + str r4, [r8] + ldr r4, pll_stat +block: + ldr r8, [r4] /* wait for bypass to take effect */ + and r8, r8, #0x3 + cmp r8, #0x1 + bne block + + /* set new dpll dividers _after_ in bypass */ + ldr r4, pll_div_add + ldr r8, pll_div_val + str r8, [r4] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r4, flash_cfg3_addr + ldr r8, flash_cfg3_val + str r8, [r4] + ldr r4, flash_cfg4_addr + ldr r8, flash_cfg4_val + str r8, [r4] + ldr r4, flash_cfg5_addr + ldr r8, flash_cfg5_val + str r8, [r4] + ldr r4, flash_cfg1_addr + ldr r8, [r4] + orr r8, r8, #0x3 /* up gpmc divider */ + str r8, [r4] + + /* setup to 2x loop though code. The first loop pre-loads the + * icache, the 2nd commits the prcm config, and locks the dpll + */ + mov r4, #0x1000 /* spin spin spin */ + mov r8, #0x4 /* first pass condition & set registers */ + cmp r8, #0x4 +2: + ldrne r8, [r3] /* DPLL lock check */ + and r8, r8, #0x7 + cmp r8, #0x2 + beq 4f +3: + subeq r8, r8, #0x1 + streq r8, [r0] /* commit dividers (2nd time) */ + nop +lloop1: + sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop1 + mov r4, #0x40000 + cmp r8, #0x1 + nop + streq r2, [r1] /* lock dpll (2nd time) */ + nop +lloop2: + sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop2 + mov r4, #0x40000 + cmp r8, #0x1 + nop + ldreq r8, [r3] /* get lock condition for dpll */ + cmp r8, #0x4 /* first time though? */ + bne 2b + moveq r8, #0x2 /* set to dpll check condition. */ + beq 3b /* if condition not true branch */ +4: + ldr r4, [sp] + add sp, sp, #0x4 /* return stack space */ + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_stat: + .word CM_IDLEST_CKGEN +pll_div_add: + .word CM_CLKSEL1_PLL +pll_div_val: + .word DPLL_VAL /* DPLL setting (300MHz default) */ + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* map interrupt controller */ + ldr r0, VAL_INTH_SETUP + mcr p15, 0, r0, c15, c2, 4 + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +VAL_INTH_SETUP: + .word PERIFERAL_PORT_BASE +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + diff --git a/board/omap2430sdp/mem.c b/board/omap2430sdp/mem.c new file mode 100644 index 000000000..8b53757cb --- /dev/null +++ b/board/omap2430sdp/mem.c @@ -0,0 +1,849 @@ +/* + * (C) Copyright 2004-2005 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/****** DATA STRUCTURES ************/ + +/* Only One NAND allowed on board at a time. + * The GPMC CS Base for the same + */ +unsigned int nand_cs_base = 0; +unsigned int boot_flash_base = 0; +unsigned int boot_flash_off = 0; +unsigned int boot_flash_sec = 0; +unsigned int boot_flash_type = 0; +volatile unsigned int boot_flash_env_addr = 0; +/* help common/env_flash.c */ +#ifdef ENV_IS_VARIABLE + +/* On SDP, all the 3 NOR parts are available on all CS combinations. + * On GDP, this is a variable set. Set the default to SDP configuration + * and change it later on if the board is GDP. + */ +ulong NOR_FLASH_BANKS_LIST[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; +int NOR_MAX_FLASH_BANKS = 4 ; /* max number of flash banks */ + +uchar(*boot_env_get_char_spec) (int index); +int (*boot_env_init) (void); +int (*boot_saveenv) (void); +void (*boot_env_relocate_spec) (void); + +extern uchar flash_env_get_char_spec(int index); +extern int flash_env_init(void); +extern int flash_saveenv(void); +extern void flash_env_relocate_spec(void); +extern char *flash_env_name_spec; + +extern uchar nand_env_get_char_spec(int index); +extern int nand_env_init(void); +extern int nand_saveenv(void); +extern void nand_env_relocate_spec(void); +extern char *nand_env_name_spec; + +extern char *onenand_env; +extern uchar onenand_env_get_char_spec(int index); +extern int onenand_env_init(void); +extern int onenand_saveenv(void); +extern void onenand_env_relocate_spec(void); +extern char *onenand_env_name_spec; + +/* Global fellows */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +u8 is_nand = 0; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) +u8 is_flash = 0; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) +u8 is_onenand = 0; +#endif + +char *env_name_spec = 0; +/* update these elsewhere */ +env_t *env_ptr = 0; + +#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH)) +extern env_t *flash_addr; +#endif + +#endif /* ENV_IS_VARIABLE */ + +/* Board CS Organization - 2430SDP REV 0.1->1.1 */ +static const unsigned char chip_sel_sdp[][GPMC_MAX_CS] = { +/* GPMC CS Indices */ +/* S8- 1 2 3 IDX CS0, CS1, CS2 .. CS7 */ +/* 0 OFF OFF OFF */ {PISMO_CS2, PISMO_CS1, PROC_NOR, 0, 0, DBG_MPDB, 0, PISMO_CS0}, +/* 1 ON OFF OFF */ {PISMO_CS1, PISMO_CS0, PROC_NOR, 0, 0, DBG_MPDB, 0, PROC_NAND}, +/* 2 OFF ON OFF */ {PISMO_CS0, PROC_NOR, PISMO_CS1, 0, 0, DBG_MPDB, 0, PISMO_CS2}, +/* 3 ON ON OFF */ {PROC_NAND, PROC_NOR, PISMO_CS0, 0, 0, DBG_MPDB, 0, PISMO_CS1}, +/* 4 OFF OFF ON */ {PISMO_CS1, PISMO_CS2, PROC_NOR, 0, 0, DBG_MPDB, 0, PISMO_CS0}, +/* 5 ON OFF ON */ {PISMO_CS0, PISMO_CS1, PROC_NOR, 0, 0, DBG_MPDB, 0, PROC_NAND}, +/* 6 OFF ON ON */ {PROC_NOR, PISMO_CS0, PISMO_CS1, 0, 0, DBG_MPDB, 0, PISMO_CS2}, +/* 7 ON ON ON */ {PROC_NOR, PROC_NAND, PISMO_CS0, 0, 0, DBG_MPDB, 0, PISMO_CS1}, +}; + +/* Board CS Organization - 2430GDP REV 0.1->1.1 */ +static const unsigned char chip_sel_gdp[][GPMC_MAX_CS] = { +/* GPMC CS Indices */ +/* S8- 1 2 3 IDX CS0, CS1, CS2 .. CS7 */ +/* 0 OFF OFF OFF */ {PISMO_CS0, PISMO_CS1, PROC_NAND, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA}, +/* 1 ON OFF OFF */ {PISMO_CS2, PROC_NAND, PROC_NOR, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA}, +/* 2 OFF ON OFF */ {PROC_NAND, PISMO_CS0, PISMO_CS1, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA}, +/* 3 ON ON OFF */ {PROC_NAND, PROC_NOR, PISMO_CS2, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA}, +/* 4 OFF OFF ON */ {PISMO_CS0, PISMO_CS1, PROC_NOR, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA}, +/* 5 ON OFF ON */ {PISMO_CS2, PROC_NOR, PROC_NAND, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA}, +/* 6 OFF ON ON */ {PROC_NOR, PISMO_CS0, PISMO_CS1, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA}, +/* 7 ON ON ON */ {PROC_NOR, PROC_NAND, PISMO_CS2, 0, 0, DBG_MPDB, 0, PISMO_PCMCIA}, +}; + +/* Map the number of NORs present and NOR flash locations on GDP */ +static const ulong norfl_loc_gdp[][CFG_MAX_FLASH_BANKS + 1] = { +/* 0 OFF OFF OFF*/ {2,SIBLEY_MAP1, SIBLEY_MAP2, 0, 0 }, +/* 1 ON OFF OFF*/ {2,FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, 0, 0}, +/* 2 OFF ON OFF*/ {2,SIBLEY_MAP1, SIBLEY_MAP2, 0, 0 }, +/* 3 ON ON OFF*/ {2,FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, 0, 0}, +/* 4 OFF OFF ON */ {4,FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, SIBLEY_MAP1, SIBLEY_MAP2}, +/* 5 ON OFF ON */ {2,FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, 0, 0}, +/* 6 OFF ON ON */ {4, FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, SIBLEY_MAP1, SIBLEY_MAP2}, +/* 7 ON ON ON */ {2,FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, 0, 0}, +}; +/* Values for each of the chips */ +static u32 gpmc_mpdb[GPMC_MAX_REG] = { + MPDB_GPMC_CONFIG1, + MPDB_GPMC_CONFIG2, + MPDB_GPMC_CONFIG3, + MPDB_GPMC_CONFIG4, + MPDB_GPMC_CONFIG5, + MPDB_GPMC_CONFIG6, 0 +}; +static u32 gpmc_stnor[GPMC_MAX_REG] = { + STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, 0 +}; +static u32 gpmc_smnand[GPMC_MAX_REG] = { + SMNAND_GPMC_CONFIG1, + SMNAND_GPMC_CONFIG2, + SMNAND_GPMC_CONFIG3, + SMNAND_GPMC_CONFIG4, + SMNAND_GPMC_CONFIG5, + SMNAND_GPMC_CONFIG6, 0 +}; +static u32 gpmc_sibnor[GPMC_MAX_REG] = { + SIBNOR_GPMC_CONFIG1, + SIBNOR_GPMC_CONFIG2, + SIBNOR_GPMC_CONFIG3, + SIBNOR_GPMC_CONFIG4, + SIBNOR_GPMC_CONFIG5, + SIBNOR_GPMC_CONFIG6, 0 +}; +static u32 gpmc_onenand[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, 0 +}; +static u32 gpmc_pcmcia[GPMC_MAX_REG] = { + PCMCIA_GPMC_CONFIG1, + PCMCIA_GPMC_CONFIG2, + PCMCIA_GPMC_CONFIG3, + PCMCIA_GPMC_CONFIG4, + PCMCIA_GPMC_CONFIG5, + PCMCIA_GPMC_CONFIG6, 0 +}; + +/********** Functions ****/ + +/* ENV Functions */ + +#ifdef ENV_IS_VARIABLE +uchar env_get_char_spec(int index) +{ + if (!boot_env_get_char_spec) { + puts("ERROR!! env_get_char_spec not available\n"); + } else + return boot_env_get_char_spec(index); + return 0; +} +int env_init(void) +{ + if (!boot_env_init) { + puts("ERROR!! boot_env_init not available\n"); + } else + return boot_env_init(); + return -1; +} +int saveenv(void) +{ + if (!boot_saveenv) { + puts("ERROR!! boot_saveenv not available\n"); + } else + return boot_saveenv(); + return -1; +} +void env_relocate_spec(void) +{ + if (!boot_env_relocate_spec) { + puts("ERROR!! boot_env_relocate_spec not available\n"); + } else + boot_env_relocate_spec(); +} +#endif + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(u32 * shift) +{ +#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ +#define GPT_CTR OMAP24XX_GPT2+TCRR /* read counter address */ + u32 start, cstart, cend, cdiff, val; + + if (__raw_readl(PRCM_CLKSRC_CTRL) & BIT7) { /* if currently /2 */ + *shift = 1; + } else { + *shift = 0; + } + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* mask for sys_clk use */ + __raw_writel(val, CM_CLKSEL2_CORE); /* timer2 source to sys_clk */ + __raw_writel(BIT4, CM_ICLKEN1_CORE); /* timer2 interface clock on */ + __raw_writel(BIT4, CM_FCLKEN1_CORE); /* timer2 function clock on */ + __raw_writel(0, OMAP24XX_GPT2 + TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP24XX_GPT2 + TCLR); /* enable clock */ + /* enable 32kHz source *//* enabled out of reset */ + /* determine sys_clk via gauging */ + + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ + while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */ + cstart = __raw_readl(GPT_CTR); /* get start sys_clk count */ + while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */ + cend = __raw_readl(GPT_CTR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + + /* based on number of ticks assign speed */ + if (cdiff > (19000 >> *shift)) + return (S38_4M); + else if (cdiff > (15200 >> *shift)) + return (S26M); + else if (cdiff > (13000 >> *shift)) + return (S24M); + else if (cdiff > (9000 >> *shift)) + return (S19_2M); + else if (cdiff > (7600 >> *shift)) + return (S13M); + else + return (S12M); +} + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in 12MHz bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/********************************************************************************* + * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default). + * -- called from SRAM, or Flash (using temp SRAM stack). + *********************************************************************************/ +void prcm_init(void) +{ + u32 div, speed, val, div_by_2; + void (*f_lock_pll) (u32, u32, u32, u32); + extern void *_end_vect, *_start; + /* u32 rev = get_cpu_rev(); unused as of now */ + + f_lock_pll = + (void *)((u32) & _end_vect - (u32) & _start + SRAM_VECT_CODE); + + val = __raw_readl(PRCM_CLKSRC_CTRL) & ~(BIT1 | BIT0); +#if defined(OMAP2430_SQUARE_CLOCK_INPUT) + __raw_writel(val, PRCM_CLKSRC_CTRL); +#else + __raw_writel((val | BIT0), PRCM_CLKSRC_CTRL); +#endif + /* skip clock gauging if warm reset. For some unknown reason, + GPT2 stalls after warm reset until DPLL has been setup and + GPT2 F/I clocks are enabled. + */ + if (__raw_readl(RM_RSTST_MPU) & BIT1) { + speed = S13M; + if (((BIT23 | BIT24 | BIT25) & __raw_readl(CM_CLKSEL1_PLL)) == + (0x3 << 23)) + speed = S12M; + else if (((BIT23 | BIT24 | BIT25) & __raw_readl(CM_CLKSEL1_PLL)) + == (0x0 << 23)) + speed = S19_2M; + div_by_2 = + (((BIT6 | BIT7) & __raw_readl(PRCM_CLKSRC_CTRL)) == 0x2); + if (div_by_2) + speed <<= 1; + } else + speed = get_osc_clk_speed(&div_by_2); + + if ((speed > S19_2M) && (!div_by_2)) { /* if fast && /2 off, enable it */ + val = ~(BIT6 | BIT7) & __raw_readl(PRCM_CLKSRC_CTRL); + val |= (0x2 << 6); /* divide by 2 if (24,26,38.4) -> (12/13/19.2) */ + __raw_writel(val, PRCM_CLKSRC_CTRL); + } + __raw_writel(0, CM_FCLKEN1_CORE); /* stop all clocks to reduce ringing */ + __raw_writel(0, CM_FCLKEN2_CORE); /* may not be necessary */ + __raw_writel(0, CM_ICLKEN1_CORE); + __raw_writel(0, CM_ICLKEN2_CORE); + + __raw_writel(DPLL_OUT, CM_CLKSEL2_PLL); /* set DPLL out */ + __raw_writel(MPU_DIV, CM_CLKSEL_MPU); /* set MPU divider */ + __raw_writel(DSP_DIV, CM_CLKSEL_DSP); /* set dsp and iva dividers */ + __raw_writel(GFX_DIV, CM_CLKSEL_GFX); /* set gfx dividers */ + __raw_writel(MDM_DIV, CM_CLKSEL_MDM); /* set mdm dividers */ + + div = BUS_DIV; + __raw_writel(div, CM_CLKSEL1_CORE); /* set L3/L4/USB/Display/SSi dividers */ + sdelay(1000); + + if (running_in_flash()) { + /* if running from flash, need to jump to small relocated code area in SRAM. + * This is the only safe spot to do configurations from. + */ + (*f_lock_pll) (PRCM_CLKCFG_CTRL, CM_CLKEN_PLL, DPLL_LOCK, + CM_IDLEST_CKGEN); + } + + /* set up APLLS_CLKIN per crystal */ + if (speed > S19_2M) + speed >>= 1; /* if fast shift to /2 range */ + val = (0x2 << 23); /* default to 13Mhz for 2430c */ + if (speed == S12M) + val = (0x3 << 23); + else if (speed == S19_2M) + val = (0x0 << 23); + val |= (~(BIT23 | BIT24 | BIT25) & __raw_readl(CM_CLKSEL1_PLL)); + __raw_writel(val, CM_CLKSEL1_PLL); + + __raw_writel(DPLL_LOCK | APLL_LOCK, CM_CLKEN_PLL); /* enable apll */ + wait_on_value(BIT8, BIT8, CM_IDLEST_CKGEN, LDELAY); /* wait for apll lock */ + + sdelay(1000); +} + +/************************************************************************** + * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow + * command line mem=xyz use all memory with out discontigious support + * compiled in. Could do it at the ATAG, but there really is two banks... + * Called as part of 2nd phase DDR init. + **************************************************************************/ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(SDRC_CS0_OSET); + size /= SZ_32M; /* find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG); + +} + +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in gussing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(void) +{ + u32 val1, val2, orig1, orig2, addr; + u32 pattern = 0x12345678; + + addr = OMAP24XX_SDRC_CS0; + + orig1 = __raw_readl(addr + 0x400); /* try to save original value */ + orig2 = __raw_readl(addr); + __raw_writel(0x0, addr + 0x400); /* clear pos A */ + __raw_writel(pattern, addr); /* pattern to pos B */ + __raw_writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = __raw_readl(addr + 0x400); /* get pos A value */ + val2 = __raw_readl(addr); /* get val2 */ + if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed */ + return (0); + else { + /* restore original values and return pass */ + __raw_writel(orig1, addr + 0x400); + __raw_writel(orig2, addr); + return (1); + } +} + +/******************************************************** + * sdrc_init() - init the sdrc chip selects CS0 and CS1 + * - early init routines, called from flash or + * SRAM. + *******************************************************/ +void sdrc_init(void) +{ +#define EARLY_INIT 1 + do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */ +} + +/************************************************************************* + * do_sdrc_init(): initialize the SDRAM for use. + * -called from low level code with stack only. + * -code sets up SDRAM timing and muxing for 2422 or 2420. + * -optimal settings can be placed here, or redone after i2c + * inspection of board info + * + * This is a bit ugly, but should handle all memory modules + * used with the SDP. The first time though this code from s_init() + * we configure the first chip select. Later on we come back and + * will configure the 2nd chip select if it exists. + * + **************************************************************************/ +void do_sdrc_init(u32 offset, u32 early) +{ + u32 cpu, dev, dllstat, dllctrl = 0, rev, common = 0, cs0 = 0, pmask = + 0, pass_type, mtype; + sdrc_data_t *sdata; /* do not change type */ + u32 dllx = 0, mono = 0; + void init_dcdl(u32 cpu); + + /* the following structure has a lot data shared with 2420 H4. Only 3 2430SDP + parameters. This needs to be cleaned after wakeup */ + static const sdrc_data_t sdrc_2430 = { + H4_2420_SDRC_SHARING, SDP_2430_SDRC_MDCFG_0_DDR, + H4_2420_SDRC_MDCFG_0_SDR, + SDP_2430_SDRC_ACTIM_CTRLA_0, H4_2420_SDRC_ACTIM_CTRLB_0, + H4_2420_SDRC_RFR_CTRL, H4_2420_SDRC_MR_0_DDR, + H4_2420_SDRC_MR_0_SDR, + SDP_2430_SDRC_DLLAB_CTRL + }; + + if (offset == SDRC_CS0_OSET) + cs0 = common = 1; /* int regs shared between both chip select */ + + cpu = get_cpu_type(); + dev = get_device_type(); + rev = get_cpu_rev(); + + /* warning generated, though code generation is correct. this may bite later, + * but is ok for now. there is only so much C code you can do on stack only + * operation. + */ + sdata = (sdrc_data_t *) & sdrc_2430; + pass_type = IP_DDR; + + __asm__ __volatile__("":::"memory"); /* limit compiler scope */ + + /* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx. + * If we are running in flash prior to relocation and we use data + * here which is not pc relative we need to get the address correct. + * We need to find the current flash mapping to dress up the initial + * pointer load. As long as this is const data we should be ok. + */ + if ((early) && running_in_flash()) { + sdata = + (sdrc_data_t *) (((u32) sdata & 0x0003FFFF) | + get_gpmc0_base()); + if (running_from_internal_boot()) { + if (dev != GP_DEVICE) + /* NOR internal boot for HS device offset is + * 0x4000 from xloader signature. + */ + sdata = (sdrc_data_t *) ((u32) sdata + 0x4000); + else { + /* GP device, the image may or may not signed. + * If signed, there are 8 bytes pending so the + * u-boot is at offset 0x8. + */ + if (sdata->sdrc_sharing != H4_2420_SDRC_SHARING) + sdata = + (sdrc_data_t *) ((u32) sdata + 0x8); + } + } + } + + if (!early && (((mtype = get_mem_type()) == DDR_COMBO) + || (mtype == DDR_STACKED))) { + if (mtype == DDR_COMBO) { + pmask = BIT2; /* combo part has a shared CKE signal, can't use feature */ + pass_type = COMBO_DDR; /* CS1 config */ + __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, + SDRC_POWER); + } + if (rev != CPU_242X_ES1) /* for es2 and above smooth things out */ + make_cs1_contiguous(); + } + + next_mem_type: + if (common) { /* do a SDRC reset between types to clear regs */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG); /* reset sdrc */ + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); /* wait till reset done set */ + __raw_writel(0, SDRC_SYSCONFIG); /* clear soft reset */ + __raw_writel(sdata->sdrc_sharing, SDRC_SHARING); +#ifdef POWER_SAVE + __raw_writel(__raw_readl(SMS_SYSCONFIG) | SMART_IDLE, + SMS_SYSCONFIG); + __raw_writel(sdata->sdrc_sharing | SMART_IDLE, SDRC_SHARING); + __raw_writel((__raw_readl(SDRC_POWER) | BIT6), SDRC_POWER); +#endif + } + + if ((pass_type == IP_DDR) || (pass_type == STACKED)) { /* (IP ddr-CS0),(2422-CS0/CS1) */ + __raw_writel(sdata->sdrc_mdcfg_0_ddr, SDRC_MCFG_0 + offset); + if (mono) + __raw_writel(H4_2422_SDRC_MDCFG_MONO_DDR, SDRC_MCFG_0 + offset); /* 2422.es2.05-CS1 */ + } else if (pass_type == COMBO_DDR) { /* (combo-CS0/CS1) */ + __raw_writel(H4_2420_COMBO_MDCFG_0_DDR, SDRC_MCFG_0 + offset); + } else if (pass_type == IP_SDR) { /* ip sdr-CS0 */ + __raw_writel(sdata->sdrc_mdcfg_0_sdr, SDRC_MCFG_0 + offset); + } + + if (cs0) { + __raw_writel(sdata->sdrc_actim_ctrla_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(sdata->sdrc_actim_ctrlb_0, SDRC_ACTIM_CTRLB_0); + } else { + __raw_writel(sdata->sdrc_actim_ctrla_0, SDRC_ACTIM_CTRLA_1); + __raw_writel(sdata->sdrc_actim_ctrlb_0, SDRC_ACTIM_CTRLB_1); + } + __raw_writel(sdata->sdrc_rfr_ctrl, SDRC_RFR_CTRL + offset); + + /* init sequence for mDDR/mSDR using manual commands (DDR is a bit different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0 + offset); + sdelay(5000); /* supposed to be 100us per design spec for mddr/msdr */ + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0 + offset); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset); + + /* + * CSx SDRC Mode Register + * Burst length = (4 - DDR) (2-SDR) + * Serial mode + * CAS latency = x + */ + if (pass_type == IP_SDR) + __raw_writel(sdata->sdrc_mr_0_sdr, SDRC_MR_0 + offset); + else + __raw_writel(sdata->sdrc_mr_0_ddr, SDRC_MR_0 + offset); + + dllctrl = BIT0; /* flag to clear bit0 (90deg for < 133MHz) */ + +#ifdef PRCM_CONFIG_2 + /* flag clear bit1 (set phase to 72 for > 150MHz) */ + dllctrl |= DLLPHASE; /* phase to 72 for > 150MHz) */ +#endif + + /* If DDR enable DLL to get a value, then move to unlock mode for SDRC mod16 errata */ + if (common && (pass_type != IP_SDR)) { + __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLA_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl & ~(LOADDLL | dllctrl), + SDRC_DLLA_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl, SDRC_DLLB_CTRL); + __raw_writel(sdata->sdrc_dllab_ctrl & ~(LOADDLL | dllctrl), + SDRC_DLLB_CTRL); + + init_dcdl(cpu); /* fix errata for possible bad init state */ + + sdelay(0x2000); /* give time to lock, at least 1000 L3 */ + + /* work around DCDL MOD16 bug */ + dllctrl = __raw_readl(SDRC_DLLA_CTRL + dllx); /* get cur ctrl value */ + dllctrl &= ~(DLL_DELAY_MASK); /* prepare for load new value */ + dllctrl |= LOADDLL; /* prepare for load + unlock mode */ + dllstat = + (__raw_readl(SDRC_DLLA_STATUS + dllx) & DLL_DELAY_MASK); + dllctrl |= dllstat; /* prepare new dll load delay */ + dllctrl |= DLL_NO_FILTER_MASK; /* make sure filter is off */ + __raw_writel(dllctrl, SDRC_DLLA_CTRL); /* go to unlock modeA */ + __raw_writel(dllctrl, SDRC_DLLB_CTRL); /* go to unlock modeB */ + } + sdelay(0x1000); + + if (mono) /* Used if Stacked memory is on CS1 only */ + make_cs1_contiguous(); /* make CS1 appear at CS0 */ + + if (mem_ok()) + return; /* STACKED, other configured type */ + ++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */ + goto next_mem_type; +} + +/***************************************************** + * init_dcdl(): Fix errata - unitilized flip-flop. + *****************************************************/ +void init_dcdl(u32 cpu) +{ + volatile u8 *adqs[4]; + u8 vdqs[4], idx, i; + u32 base = OMAP24XX_CTRL_BASE; +#define CONTROL_SDRC_DQS0 0x50 + + adqs[0] = ((volatile u8 *)(base + CONTROL_SDRC_DQS0 + 0x0)); + adqs[1] = ((volatile u8 *)(base + CONTROL_SDRC_DQS0 + 0x1)); + adqs[2] = ((volatile u8 *)(base + CONTROL_SDRC_DQS0 + 0x2)); + adqs[3] = ((volatile u8 *)(base + CONTROL_SDRC_DQS0 + 0x3)); + idx = 4; + + for (i = 0; i < idx; ++i) /* save origional state */ + vdqs[i] = *adqs[i]; + + for (i = 0; i < idx; ++i) + *adqs[i] = ((~0x10 & vdqs[i]) | 0x8); /* enable/activate pull down */ + + sdelay(0x400); + + for (i = 0; i < idx; ++i) + *adqs[i] = (vdqs[i] | 0x10); /* enable/activate pull up */ + + sdelay(0x400); + + for (i = 0; i < idx; ++i) /* restore state */ + *adqs[i] = vdqs[i]; +} + +void enable_gpmc_config(u32 * gpmc_config, u32 gpmc_base, u32 base, u32 size) +{ + __raw_writel(0, GPMC_CONFIG7 + gpmc_base); + sdelay(1000); + /* Delay for settling */ + __raw_writel(gpmc_config[0], GPMC_CONFIG1 + gpmc_base); + __raw_writel(gpmc_config[1], GPMC_CONFIG2 + gpmc_base); + __raw_writel(gpmc_config[2], GPMC_CONFIG3 + gpmc_base); + __raw_writel(gpmc_config[3], GPMC_CONFIG4 + gpmc_base); + __raw_writel(gpmc_config[4], GPMC_CONFIG5 + gpmc_base); + __raw_writel(gpmc_config[5], GPMC_CONFIG6 + gpmc_base); + /* Enable the config */ + __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), GPMC_CONFIG7 + gpmc_base); + sdelay(2000); +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ + /* For readability */ + u32 mux = 0, mwidth; + u32 *gpmc_config = NULL; + u32 gpmc_base = 0; + u32 base = 0; + u8 idx = 0; + u8 cnt = 0; + u32 size = 0; + u32 f_off = CFG_MONITOR_LEN; + u32 f_sec = 0; + u32 board_type = 0; + unsigned char *config_sel = NULL; + + mux = BIT9; + mwidth = get_gpmc0_width(); + + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL); /* timeout disable */ + + /* Disable the GPMC0 config set by ROM code + * It conflicts with our MPDB (both at 0x08000000) + */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + sdelay(1000); + + /* GPMC5 is always MPDB.. need to know the chip info */ + gpmc_base = GPMC_CONFIG_CS0 + (5 * GPMC_CONFIG_WIDTH); + gpmc_mpdb[0] |= mux; + enable_gpmc_config(gpmc_mpdb, gpmc_base, DEBUG_BASE, DBG_MPDB_SIZE); + idx = get_gpmc0_type(); + /* invalid chip, assume nor boot */ + if (idx > 0x7) { + idx = 7; + } + + /* The board type information was supposed to be dynamically + * pinged from the board revision id. Due to the problem with + * fpga, this doesn't happen fast enough, hence reverting back + * to hardcoding the fact. + */ +#ifdef OMAP2430_SDP_GDP_CONFIG + board_type = BOARD_GDP_2430_T2; +#else + board_type = BOARD_SDP_2430_T2; +#endif + + if (board_type == BOARD_GDP_2430_T2) { + + config_sel = (unsigned char *)(chip_sel_gdp[idx]); + + /* GPMC7 is always PCMCIA.. need to know the chip info */ + gpmc_base = GPMC_CONFIG_CS0 + (7 * GPMC_CONFIG_WIDTH); + gpmc_pcmcia[0] |= mux; + __raw_writel(0x0, GPMC_CONFIG); /* set nWP, disable limited addr */ + enable_gpmc_config(gpmc_pcmcia, gpmc_base, PCMCIA_BASE,PISMO_PCMCIA_SIZE ); + + /* On GDP, all the 4 flashes are not present by default + * Configure only those flashes that are present. + */ + NOR_MAX_FLASH_BANKS = norfl_loc_gdp[idx][0]; + + for (cnt = 1; cnt <= NOR_MAX_FLASH_BANKS ; cnt++) { + NOR_FLASH_BANKS_LIST[cnt - 1] = norfl_loc_gdp[idx][cnt]; + } + + } else { + config_sel = (unsigned char *)(chip_sel_sdp[idx]); + } + + /* For Nand based boot only..OneNand?? */ + if (config_sel[0] == PROC_NAND) { + __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ + } + /* reuse idx */ + for (idx = 0; idx < GPMC_MAX_CS; idx++) { + if (!config_sel[idx]) { + continue; + } + gpmc_base = GPMC_CONFIG_CS0 + (idx * GPMC_CONFIG_WIDTH); + switch (config_sel[idx]) { + case PROC_NOR: + gpmc_config = gpmc_stnor; + gpmc_config[0] |= mux | TYPE_NOR | mwidth; + base = PROC_NOR_BASE; + size = PROC_NOR_SIZE; + f_sec = SZ_128K; + is_flash = 1; + break; +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + case PROC_NAND: + base = PROC_NAND_BASE; + size = PROC_NAND_SIZE; + gpmc_config = gpmc_smnand; + gpmc_config[0] |= mux | TYPE_NAND | mwidth; + /* Either OneNand or Normal Nand at a time!! */ + nand_cs_base = gpmc_base; + f_off = SMNAND_ENV_OFFSET; + is_nand = 1; + break; +#endif + case PISMO_SIBLEY0: + case PISMO_SIBLEY1: + if (config_sel[idx] == PISMO_SIBLEY0) { + base = PISMO_SIB0_BASE; + size = PISMO_SIB0_SIZE; + } else { + base = PISMO_SIB1_BASE; + size = PISMO_SIB1_SIZE; + } + f_sec = SZ_256K; + gpmc_config = gpmc_sibnor; + gpmc_config[0] |= mux | TYPE_NOR | mwidth; + is_flash = 1; + break; + case PISMO_ONENAND: + base = PISMO_ONEN_BASE; + size = PISMO_ONEN_SIZE; + gpmc_config = gpmc_onenand; + f_off = ONENAND_ENV_OFFSET; + is_onenand = 1; + break; + default: + /* MPDB/Unsupported/Corrupt config- try Next GPMC CS!!!! */ + continue; + } + if (0 == idx) { + boot_flash_base = base; + boot_flash_off = f_off; + boot_flash_sec = f_sec; + boot_flash_type = config_sel[idx]; + boot_flash_env_addr = f_off; +#ifdef ENV_IS_VARIABLE + switch (config_sel[0]) { + case PROC_NOR: + case PISMO_SIBLEY0: + case PISMO_SIBLEY1: + boot_env_get_char_spec = + flash_env_get_char_spec; + boot_env_init = flash_env_init; + boot_saveenv = flash_saveenv; + boot_env_relocate_spec = + flash_env_relocate_spec; + flash_addr = env_ptr = + (env_t *) (boot_flash_base + + boot_flash_off); + env_name_spec = flash_env_name_spec; + boot_flash_env_addr = (u32) flash_addr; + break; +#if 0 + case PROC_NAND: + boot_env_get_char_spec = nand_env_get_char_spec; + boot_env_init = nand_env_init; + boot_saveenv = nand_saveenv; + boot_env_relocate_spec = nand_env_relocate_spec; + env_ptr = 0; /* This gets filled elsewhere!! */ + env_name_spec = nand_env_name_spec; + break; +#endif + case PISMO_ONENAND: + boot_env_get_char_spec = + onenand_env_get_char_spec; + boot_env_init = onenand_env_init; + boot_saveenv = onenand_saveenv; + boot_env_relocate_spec = + onenand_env_relocate_spec; + env_ptr = + (env_t *) onenand_env; + env_name_spec = onenand_env_name_spec; + break; + default: + /* unknown variant!! */ + puts("Unknown Boot chip!!!\n"); + break; + } +#endif /* ENV_IS_VARIABLE */ + } + enable_gpmc_config(gpmc_config, gpmc_base, base, size); + } +} diff --git a/board/omap2430sdp/omap2430sdp.c b/board/omap2430sdp/omap2430sdp.c new file mode 100644 index 000000000..2e4e88678 --- /dev/null +++ b/board/omap2430sdp/omap2430sdp.c @@ -0,0 +1,622 @@ +/* + * (C) Copyright 2004-2005 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +#endif + +void wait_for_command_complete(unsigned int wd_base); + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + u32 rev ; + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRM, finish GPMC */ + rev = get_board_type(); + if ((rev == BOARD_H4_SDP)) { + gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */ + } else { + gd->bd->bi_arch_number = MACH_TYPE_OMAP_2430SDP; /* board id for linux */ + } + gd->bd->bi_boot_params = (OMAP24XX_SDRC_CS0 + 0x100); /* adress of boot parameters */ + + return 0; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); /* REQ_INFO_PERMISSION_1 L*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); /* ADDR_MATCH_1 L*/ + + + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ + + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80); /* ADDR_MATCH_2 L*/ + + /* IVA Changes */ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); /* WRITE_PERMISSION_0 L*/ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_sram(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock(); + } + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with sram stack. + **********************************************************/ +void s_init(void) +{ + int in_sdram = running_in_sdram(); + /* u32 rev = get_cpu_rev(); unused as of now.. */ + + watchdog_init(); + + try_unlock_sram(); /* Do SRAM availability first - take care of permissions too */ + + set_muxconf_regs(); + delay(100); + + if (!in_sdram){ + prcm_init(); + } + + peripheral_enable(); + icache_enable(); + if (!in_sdram) + sdrc_init(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ + ether_init(); /* better done here so timers are init'ed */ + return (0); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 4 watch dogs. 1 secure, and 3 general purpose. + * The ROM takes care of the secure one. Of the 3 GP ones, + * 1 can reset us directly, the other 2 only generate MPU interrupts. + */ + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + /* u32 rev = get_cpu_rev(); unused as of now */ + + + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01; + udelay(1000); + + h4reset_err_out: + return; +#endif +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + u8 data; +#endif +#define NOT_EARLY 0 + +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + select_bus(1, CFG_I2C_SPEED); /* select bus with T2 on it */ +#endif + btype = get_board_type(); + mtype = get_mem_type(); + display_board_info(btype); +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + if (btype == BOARD_SDP_2430_T2) { + /* Enable VMODE following voltage switching */ + data = 0x24; /* set the floor voltage to 1.05v */ + i2c_write(I2C_TRITON2, 0xBB, 1, &data, 1); + data = 0x38; /* set the roof voltage to 1.3V */ + i2c_write(I2C_TRITON2, 0xBC, 1, &data, 1); + data = 0x0; /* set jump mode for VDD voltage transition */ + i2c_write(I2C_TRITON2, 0xBD, 1, &data, 1); + data = 1; /* enable voltage scaling */ + i2c_write(I2C_TRITON2, 0xBA, 1, &data, 1); + } +#endif + + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + /* init other chip select and map CS1 right after CS0 */ + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writeb((VALUE), OMAP24XX_CTRL_BASE + (OFFSET)); + +#if (CONFIG_2430SDP) +#define MUX_DEFAULT()\ + /* SDRC */\ + MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */\ + MUX_VAL(0x0055, 0x1B) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */\ + MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */\ + MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */\ + MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */\ + /* GPMC */\ + MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */\ + MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */\ + MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */\ + MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */\ + MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */\ + MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */\ + MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */\ + MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */\ + MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */\ + MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */\ + MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */\ + MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */\ + /* GPMC mux for NAND access */\ + MUX_VAL(0x0086, 0x18) /* gpmc_a9 - EN, HI, 0*/\ + MUX_VAL(0x0087, 0x18) /* gpmc_a8 - EN, HI, 0*/\ + MUX_VAL(0x0088, 0x18) /* gpmc_a7 - EN, HI, 0*/\ + MUX_VAL(0x0089, 0x18) /* gpmc_a6 - EN, HI, 0*/\ + MUX_VAL(0x008A, 0x18) /* gpmc_a5 - EN, HI, 0*/\ + MUX_VAL(0x008B, 0x18) /* gpmc_a4 - EN, HI, 0*/\ + MUX_VAL(0x008C, 0x18) /* gpmc_a3 - EN, HI, 0*/\ + MUX_VAL(0x008D, 0x18) /* gpmc_a2 - EN, HI, 0*/\ + MUX_VAL(0x008E, 0x18) /* gpmc_a1 - EN, HI, 0*/\ + MUX_VAL(0x008F, 0x18) /* gpmc_d15 - EN,HI, 0*/\ + MUX_VAL(0x0090, 0x18) /* gpmc_d14 - EN, HI, 0*/\ + MUX_VAL(0x0091, 0x18) /* gpmc_d13 - EN, HI, 0*/\ + MUX_VAL(0x0092, 0x18) /* gpmc_d12 - EN, HI, 0*/\ + MUX_VAL(0x0093, 0x18) /* gpmc_d11 - EN, HI, 0*/\ + MUX_VAL(0x0094, 0x18) /* gpmc_d10 - EN, HI, 0*/\ + MUX_VAL(0x0095, 0x18) /* gpmc_d9 - EN, HI, 0 */\ + MUX_VAL(0x0096, 0x18) /* gpmc_d8 - EN, HI, 0*/\ + /* DSS */\ + MUX_VAL(0x009F, 0x00) /* dss_data0- Dis, 0 */\ + MUX_VAL(0x00A0, 0x00) /* dss_data1- Dis, 0 */\ + MUX_VAL(0x00A1, 0x00) /* dss_data2- Dis, 0 */\ + MUX_VAL(0x00A2, 0x00) /* dss_data3- Dis, 0 */\ + MUX_VAL(0x00A3, 0x00) /* dss_data4- Dis, 0 */\ + MUX_VAL(0x00A4, 0x00) /* dss_data5- Dis, 0 */\ + MUX_VAL(0x00A5, 0x00) /* dss_data6- Dis, 0 */\ + MUX_VAL(0x00A6, 0x00) /* dss_data7- Dis, 0 */\ + MUX_VAL(0x00A7, 0x00) /* dss_data8- Dis, 0 */\ + MUX_VAL(0x00A8, 0x00) /* dss_data9- Dis, 0 */\ + MUX_VAL(0x00A9, 0x00) /* dss_data10- Dis, 0 */\ + MUX_VAL(0x00AA, 0x00) /* dss_data11- Dis, 0 */\ + MUX_VAL(0x00AB, 0x00) /* dss_data12- Dis, 0 */\ + MUX_VAL(0x00AC, 0x00) /* dss_data13- Dis, 0 */\ + MUX_VAL(0x00AD, 0x00) /* dss_data14- Dis, 0 */\ + MUX_VAL(0x00AE, 0x00) /* dss_data15- Dis, 0 */\ + MUX_VAL(0x00AF, 0x00) /* dss_data16- Dis, 0 */\ + MUX_VAL(0x00B0, 0x00) /* dss_data17- Dis, 0 */\ + MUX_VAL(0x00B9, 0x00) /* dss_hsync- Dis, 0 */\ + MUX_VAL(0x00BA, 0x00) /* dss_acbias- Dis, 0 */\ + MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */\ + MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */\ + MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */\ + MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */\ + MUX_VAL(0x00B5, 0x1B) /* mcbsp2_dr- EN, HI, 3, ->gpio_11 */\ + MUX_VAL(0x00B6, 0x1B) /* mcbsp2_clkx- EN, HI, 3, ->gpio_12 */\ + /* CONTROL */\ + MUX_VAL(0x00BB, 0x00) /* sys_nrespwron- Dis, 0 */\ + MUX_VAL(0x00BC, 0x00) /* sys_nreswarm- Dis, 0 */\ + MUX_VAL(0x00BD, 0x18) /* sys_nirq0- EN, HI, 0 */\ + /*MUX_VAL(0x00BD, 0x1B)*/ /* sys_nirq0- EN, HI, 3, ->gpio_56 */\ + MUX_VAL(0x00BE, 0x18) /* sys_nirq1- EN, HI, 0 */\ + MUX_VAL(0x00C7, 0x00) /* gpio_132- Dis, 0, ->gpio132 */\ + MUX_VAL(0x00CB, 0x00) /* gpio_133- Dis, 0, ->gpio133 */\ + MUX_VAL(0x00C9, 0x18) /* sys_clkout- Dis, 0 */\ + /*MUX_VAL(0x00C9, 0x1B)*/ /* sys_clkout- EN, HI, 3, ->gpio_111 */\ + MUX_VAL(0x00CC, 0x18) /* jtag_emu1- EN, HI, 0 */\ + MUX_VAL(0x00CD, 0x18) /* jtag_emu0- EN, HI, 0 */\ + /* CAMERA */\ + MUX_VAL(0x00DD, 0x02) /* cam_d0- Dis, 2, sti_dout */\ + MUX_VAL(0x00DC, 0x02) /* cam_d1- Dis, 2, sti_din */\ + MUX_VAL(0x00DB, 0x1B) /* cam_d2- EN, HI, 3, ->gpio_129 */\ + MUX_VAL(0x00DA, 0x1B) /* cam_d3- EN, HI, 3, ->gpio_128 */\ + MUX_VAL(0x00D9, 0x00) /* cam_d4- Dis, 0 */\ + MUX_VAL(0x00D8, 0x00) /* cam_d5- Dis, 0 */\ + MUX_VAL(0x00D7, 0x00) /* cam_d6- Dis, 0 */\ + MUX_VAL(0x00D6, 0x00) /* cam_d7- Dis, 0 */\ + MUX_VAL(0x00D5, 0x00) /* cam_d8- Dis, 0 */\ + MUX_VAL(0x00D4, 0x00) /* cam_d9- Dis, 0 */\ + MUX_VAL(0x00E3, 0x00) /* cam_d10- Dis, 0 */\ + MUX_VAL(0x00E2, 0x00) /* cam_d11- Dis, 0 */\ + MUX_VAL(0x00DE, 0x00) /* cam_hs- Dis, 0 */\ + MUX_VAL(0x00DF, 0x00) /* cam_vs- Dis, 0 */\ + MUX_VAL(0x00E0, 0x00) /* cam_lclk- Dis, 0 */\ + MUX_VAL(0x00E1, 0x00) /* cam_xclk- Dis, 0 */\ + MUX_VAL(0x00E4, 0x01) /* gpio_134- Dis, 1, ->ccp_datn */\ + MUX_VAL(0x00E5, 0x01) /* gpio_135- Dis, 1, ->ccp_datp */\ + MUX_VAL(0x00E6, 0x01) /* gpio_136- Dis, 1, ->ccp_clkn */\ + MUX_VAL(0x00E7, 0x01) /* gpio_137- Dis, 1, ->ccp_clkp */\ + MUX_VAL(0x00E8, 0x01) /* gpio_138- Dis, 1, ->spi3_clk */\ + MUX_VAL(0x00E9, 0x01) /* gpio_139- Dis, 1, ->spi3_cs0 */\ + MUX_VAL(0x00EA, 0x01) /* gpio_140- Dis, 1, ->spi3_simo */\ + MUX_VAL(0x00EB, 0x01) /* gpio_141- Dis, 1, ->spi3_somi */\ + MUX_VAL(0x00EC, 0x18) /* gpio_142- EN, HI, 0, ->gpio_142 */\ + MUX_VAL(0x00ED, 0x18) /* gpio_154- EN, HI, 0, ->gpio_154 */\ + MUX_VAL(0x00EE, 0x18) /* gpio_148- EN, HI, 0, ->gpio_148 */\ + MUX_VAL(0x00EF, 0x18) /* gpio_149- EN, HI, 0, ->gpio_149 */\ + MUX_VAL(0x00F0, 0x18) /* gpio_150- EN, HI, 0, ->gpio_150 */\ + MUX_VAL(0x00F1, 0x18) /* gpio_152- EN, HI, 0, ->gpio_152 */\ + MUX_VAL(0x00F2, 0x18) /* gpio_153- EN, HI, 0, ->gpio_153 */\ + /* MMC1 */\ + MUX_VAL(0x00F3, 0x00) /* mmc1_clko- Dis, 0 */\ + MUX_VAL(0x00F4, 0x18) /* mmc1_cmd- EN, HI, 0 */\ + MUX_VAL(0x00F5, 0x18) /* mmc1_dat0- EN, HI, 0 */\ + MUX_VAL(0x00F6, 0x18) /* mmc1_dat1- EN, HI, 0 */\ + MUX_VAL(0x00F7, 0x18) /* mmc1_dat2- EN, HI, 0 */\ + MUX_VAL(0x00F8, 0x18) /* mmc1_dat3- EN, HI, 0 */\ + /* MMC2 */\ + MUX_VAL(0x00F9, 0x00) /* mmc2_clko- Dis, 0 */\ + MUX_VAL(0x00FA, 0x18) /* mmc2_cmd- EN, HI, 0 */\ + MUX_VAL(0x00FB, 0x18) /* mmc2_dat0- EN, HI, 0 */\ + MUX_VAL(0x00FC, 0x18) /* mmc2_dat1- EN, HI, 0 */\ + MUX_VAL(0x00FD, 0x18) /* mmc2_dat2- EN, HI, 0 */\ + MUX_VAL(0x00FE, 0x18) /* mmc2_dat3- EN, HI, 0 */\ + /* UART2 */\ + MUX_VAL(0x00FF, 0x00) /* uart2_cts- Dis, 0 */\ + MUX_VAL(0x0100, 0x00) /* uart2_rts- Dis, 0 */\ + MUX_VAL(0x0101, 0x00) /* uart2_tx- Dis, 0 */\ + MUX_VAL(0x0102, 0x00) /* uart2_rx- Dis, 0 */\ + /* MCBSP3 */\ + MUX_VAL(0x0103, 0x00) /* mcbsp3_clkx- Dis, 0 */\ + MUX_VAL(0x0104, 0x00) /* mcbsp3_fsx- Dis, 0 */\ + MUX_VAL(0x0105, 0x00) /* mcbsp3_dr- Dis, 0 */\ + MUX_VAL(0x0106, 0x00) /* mcbsp3_dx- Dis, 0 */\ + /* SSI1 */\ + MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */\ + MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */\ + MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */\ + MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */\ + MUX_VAL(0x010B, 0x01) /* gpio_63- Dis, 1, ->mcbsp4_clkx */\ + MUX_VAL(0x010C, 0x01) /* ssi1_flag_rx- Dis, 1, ->mcbsp4_dr */\ + MUX_VAL(0x010D, 0x01) /* ssi1_rdy_rx- Dis, 1, ->mcbsp4_dx */\ + MUX_VAL(0x010E, 0x01) /* ssi1_wake- Dis, 1, ->mcbsp4_fsx */\ + /* SPI1 */\ + MUX_VAL(0x010F, 0x00) /* spi1_clk- Dis, 0 */\ + MUX_VAL(0x0110, 0x00) /* spi1_simo- Dis, 0 */\ + MUX_VAL(0x0111, 0x00) /* spi1_somi- Dis, 0 */\ + MUX_VAL(0x0112, 0x00) /* spi1_cs0- Dis, 0 */\ + MUX_VAL(0x0113, 0x00) /* spi1_cs1- Dis, 0 */\ + MUX_VAL(0x0114, 0x00) /* spi1_cs2- Dis, 0 */\ + MUX_VAL(0x0115, 0x00) /* spi1_cs3- Dis, 0 */\ + /* SPI2 */\ + MUX_VAL(0x0116, 0x1B) /* spi2_clk- EN, HI, 3, ->gpio_88 */\ + MUX_VAL(0x0117, 0x1B) /* spi2_simo- EN, HI, 3, ->gpio_89 */\ + MUX_VAL(0x0118, 0x1B) /* spi2_somi- EN, HI, 3, ->gpio_90 */\ + MUX_VAL(0x0119, 0x1B) /* spi2_cs0- EN, HI, 3, ->gpio_91 */\ + /* MCBSP1 */\ + MUX_VAL(0x011A, 0x00) /* mcbsp1_clkr- Dis, 0 */\ + MUX_VAL(0x011B, 0x00) /* mcbsp1_fsr- Dis, 0 */\ + MUX_VAL(0x011C, 0x00) /* mcbsp1_dx- Dis, 0 */\ + MUX_VAL(0x011D, 0x00) /* mcbsp1_dr- Dis, 0 */\ + MUX_VAL(0x011E, 0x00) /* mcbsp1_clks- Dis, 0 */\ + MUX_VAL(0x011F, 0x00) /* mcbsp1_fsx- Dis, 0 */\ + MUX_VAL(0x0120, 0x00) /* mcbsp1_clkx- Dis, 0 */\ + /* HDQ */\ + MUX_VAL(0x0125, 0x00) /* hdq_sio- Dis, 0 */\ + /* UART3 */\ + MUX_VAL(0x0126, 0x00) /* uart3_cts_rctx- Dis, 0 */\ + MUX_VAL(0x0127, 0x00) /* uart3_rts_sd- Dis, 0 */\ + MUX_VAL(0x0128, 0x00) /* uart3_tx_irtx- Dis, 0 */\ + MUX_VAL(0x0129, 0x00) /* uart3_rx_irrx- Dis, 0 */\ + /* OTHERS */\ + MUX_VAL(0x012B, 0x1B) /* gpio_78- EN, HI, 3, ->gpio_78 */\ + MUX_VAL(0x012C, 0x01) /* gpio_79- Dis, 1, ->secure_indicator */\ + MUX_VAL(0x012D, 0x1B) /* gpio_80- EN, HI, 3, ->gpio_80 */\ + /* MCBSP2 */\ + MUX_VAL(0x012E, 0x01) /* gpio_113- Dis, 1, ->mcbsp2_clkx */\ + MUX_VAL(0x012F, 0x01) /* gpio_114- Dis, 1, ->mcbsp2_fsx */\ + MUX_VAL(0x0130, 0x01) /* gpio_115- Dis, 1, ->mcbsp2_dr */\ + MUX_VAL(0x0131, 0x01) /* gpio_116- Dis, 1, ->mcbsp2_dx */\ + /* GPIO7-AUDIOENVDD */\ + MUX_VAL(0x012A, 0x18) /* gpio_7- EN, HI, 3, ->gpio_7 */\ + +#else +/* For all other platforms */ +#define MUX_DEFAULT()\ + /* SDRC */\ + MUX_VAL(0x0054, 0x08) /* sdrc_a14 - EN, LO, 0 */\ + MUX_VAL(0x0055, 0x08) /* sdrc_a13 - EN, LO, 0 */\ + MUX_VAL(0x0056, 0x08) /* sdrc_a12 - EN, LO, 0 */\ + MUX_VAL(0x0045, 0x18) /* sdrc_ncs1 - EN, HI, 0 */\ + MUX_VAL(0x0046, 0x18) /* sdrc_ncs2 - EN, HI, 0 */\ + /* GPMC */\ + MUX_VAL(0x0030, 0x08) /* gpmc_clk - EN, LO, 0 */\ + MUX_VAL(0x0032, 0x18) /* gpmc_ncs1- EN, HI, 0 */\ + MUX_VAL(0x0033, 0x18) /* gpmc_ncs2- EN, HI, 0 */\ + MUX_VAL(0x0034, 0x18) /* gpmc_ncs3- EN, HI, 0 */\ + /* UART1 */\ + MUX_VAL(0x00B1, 0x18) /* uart1_cts- EN, HI, 0 */\ + MUX_VAL(0x00B2, 0x18) /* uart1_rts- EN, HI, 0 */\ + MUX_VAL(0x00B3, 0x18) /* uart1_tx- EN, HI, 0 */\ + MUX_VAL(0x00B4, 0x18) /* uart1_rx- EN, HI, 0 */\ + /* UART2 */\ + MUX_VAL(0x00FF, 0x18) /* uart2_cts- EN, HI, 0 */\ + MUX_VAL(0x0100, 0x18) /* uart2_rts- EN, HI, 0 */\ + MUX_VAL(0x0101, 0x18) /* uart2_tx- EN, HI, 0 */\ + MUX_VAL(0x0102, 0x18) /* uart2_rx- EN, HI, 0 */\ + /* UART3 */\ + MUX_VAL(0x0126, 0x18) /* uart3_cts_rctx- EN, HI, 0 */\ + MUX_VAL(0x0127, 0x18) /* uart3_rts_sd- EN, HI, 0 */\ + MUX_VAL(0x0127, 0x18) /* uart3_tx_irtx- EN, HI, 0 */\ + MUX_VAL(0x0127, 0x18) /* uart3_rx_irrx- EN, HI, 0 */\ + /* I2C1 */\ + MUX_VAL(0x0111, 0x00) /* i2c1_scl - DIS, NA, 0 */\ + MUX_VAL(0x0112, 0x00) /* i2c1_sda - DIS, NA, 0 */\ + +#endif /* End of Mux Mapping */ + +#if 0 +/********************************************************** + * Routine: mux_pwr_save + * Description: Set pins to optimal power savings state. + * + * NOTE ES1 Failures for Errata, Do NOT include: + * - set D0-D31 (boot failure, u-boot ok) + * - set D16-D31 (boot failue, u-boot ok) + * - set D0-D15 (boot with memory errors, u-boot ok) + * - set DQS3 (boot failures, u-boot start some failures). + * - set DQS0-2 (no apparent problems). + * + *********************************************************/ +static void mux_pwr_save(void) +{ + #define SDRAM_WIDTH 32 + #define OPTIMZE_FOR_DDR 1 + #define NUM_DQS 4 + + u32 addr, val, offset, base = OMAP24XX_CTRL_BASE; + + /* Activate DDR/SDR-SDRAM signal pull-ups on DQ signals to save power */ + for(offset = 0x65; offset < (0x65 + SDRAM_WIDTH); offset++){ + addr = base + offset; /* addr of pin config */ + val = __raw_readb(addr) | (BIT4|BIT3); /* mask for pull-up on */ + __raw_writeb(val, addr); /* update config */ + } +#if OPTIMZE_FOR_DDR + /* Activate DDR-SDRAM signal pull-ups on DQS signals to save power */ + for(offset = 0x50; (offset < 0x50 + NUM_DQS); offset++){ + addr = base + offset; /* addr of pin config */ + val = __raw_readb(addr) | (BIT4|BIT3); /* mask for pull-up on */ + __raw_writeb(val, addr); /* update config */ + } +#endif +} +#endif + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + u32 cpu; + cpu = get_cpu_type(); + /* Incase we have to handle multiple processors such as 2430 and 2430C */ + if (cpu == CPU_2430) { + MUX_DEFAULT(); + // mux_pwr_save(); /* this fails on 2430-ES1 dispite recommendation */ + } else + return; + +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void peripheral_enable(void) +{ + + unsigned int v, if_clks1 = 0, func_clks1 = 0, if_clks2 = 0, func_clks2 = 0; + /* ALERT STATUS 10000 */ + /* Enable GP2 timer. */ + if_clks1 |= BIT4; + func_clks1 |= BIT4; + v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP24XX_GPT2 */ + __raw_writel(v, CM_CLKSEL2_CORE); + __raw_writel(0x1, CM_CLKSEL_WKUP); + +#ifdef CFG_NS16550 + /* Enable UART1 clock */ + func_clks1 |= BIT21; + if_clks1 |= BIT21; +#endif +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + /* 2430 requires only the hs clock */ + func_clks2 |= BIT20|BIT19; /* i2c1 and 2 96 meg clock input */ + if_clks1 |= BIT20|BIT19; +#endif + + v = __raw_readl(CM_ICLKEN1_CORE) | if_clks1; /* Interface clocks on */ + __raw_writel(v, CM_ICLKEN1_CORE); + v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2; /* Interface clocks on */ + __raw_writel(v, CM_ICLKEN2_CORE); + v = __raw_readl(CM_FCLKEN1_CORE) | func_clks1; /* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN1_CORE); + v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2; /* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN2_CORE); + delay(1000); +} + +/***************************************************************************** + * Routine: update_mux() + * Description: Update balls which are different beween boards. All should be + * updated to match functionaly. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +void nand_init(void) +{ + extern flash_info_t flash_info[]; + + nand_probe(CFG_NAND_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +#ifdef CFG_JFFS2_MEM_NAND + flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; + flash_info[CFG_JFFS2_FIRST_BANK].size = 1024 * 1024 * 2; /* only read kernel single meg partition */ + flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ + flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */ +#endif +} +#endif diff --git a/board/omap2430sdp/sys_info.c b/board/omap2430sdp/sys_info.c new file mode 100644 index 000000000..9baf2f0b3 --- /dev/null +++ b/board/omap2430sdp/sys_info.c @@ -0,0 +1,501 @@ +/* + * (C) Copyright 2004-2005 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include + +/**************************************************************************** + * check_fpga_revision number: the rev number should be a or b + * 0xA203/5 variant did not have it, but the B101 variant has EEPROM update facility + ***************************************************************************/ +static inline u16 check_fpga_rev(void) +{ + return __raw_readw(FPGA_REV_REGISTER); +} + +/**************************************************************************** + * check_eeprom_avail: Check FPGA Availability + * OnBoard DEBUG FPGA registers need to be ready for us to proceed + * Required to retrieve the bootmode also. + ***************************************************************************/ +int check_eeprom_avail(u32 offset) +{ + u16 memst_reg; + u16 bit; + + int count = 10000; + /* old fpga revs dont seem to have this update */ + if (check_fpga_rev() < 0xB000) { + return 0; + } + /* Check if UI revision Name is already updated. + * if this is not done, we wait a bit to give a chance + * to update. This is nice to do as the Main board FPGA + * gets a chance to know off all it's components and we + * can continue to work normally + * Currently taking 269* udelay(1000) to update this on + * poweron from flash!! + */ + + if (offset == EEPROM_MAIN_BRD ) { + bit = BIT0; + } + else if (offset == EEPROM_UI_BRD ) { + bit = BIT2; + } + + memst_reg = __raw_readw(I2C2_MEMORY_STATUS_REG); + + while ( (memst_reg & bit) && count ) { + sdelay(100); + memst_reg = __raw_readw(I2C2_MEMORY_STATUS_REG); + count--; + } + /* Timed out count will be 0? */ + return count; +} + +/************************************************************************** + * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch + * settings + * 1 is on + * 0 is off + * Will return Index of type of gpmc + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ + u8 cs; + if (!check_fpga_rev()) { + /* we dont have an DEBUG FPGA??? */ + /* Depend on #defines!! default to strata boot return param */ + return 0x07; + } + cs = (u8) __raw_readw(DIP_SWITCH_INPUT_REG2); + /* The bits are inverted- S8 0-2 define the CS0 select */ + return ((~cs) & 0x07); +} + +/************************************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + * - just looking to say if this is a 2422 or 2420 or ... + * - to start with we will look at switch settings.. + * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics + * (mux for 2420, non-mux for 2422). + ***************************************************************************/ +u32 get_cpu_type(void) +{ + u32 v; + v = __raw_readl(TAP_IDCODE_REG); + v &= CPU_24XX_ID_MASK; + + if (v == CPU_2430_CHIPID) { + return (CPU_2430); + } else + return (-1); /* don't know,return invalid val */ +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 v; + v = __raw_readl(TAP_IDCODE_REG); + v = v >> 28; + return (v + 1); +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == H4_2420_SDRC_MR_0_SDR) + return (1); + return (0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + * 2422 uses stacked DDR, 2 parts CS0/CS1. + * 2420 may have 1 or 2, no good way to know...only init 1... + * when eeprom data is up we can select 1 more. + *************************************************************/ +u32 get_mem_type(void) +{ +#if 1 + /* 2340SDP only uses Infineon DDR for now. */ + return (DDR_DISCRETE); +#else + u32 cpu, sdr = is_mem_sdr(); + + cpu = get_cpu_type(); + if (cpu == CPU_2422 || cpu == CPU_2423) + return (DDR_STACKED); + + if (is_this_24xx_pop()) + return (XDR_POP); + + if (get_board_type() == BOARD_H4_MENELAUS) + if (sdr) + return (SDR_DISCRETE); + else + return (DDR_COMBO); + else if (sdr) /* SDP + SDR kit */ + return (SDR_DISCRETE); + else + return (DDR_DISCRETE); /* origional SDP */ +#endif +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/*********************************************************************** + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + ************************************************************************/ +u32 get_board_type(void) +{ + u32 cpu = get_cpu_rev(); + + /* we have sdp/we timed out.. base on 2430 rev */ + /* > ES2 can voltage scale and is bundled w/ T2 */ + if(cpu >= CPU_2430_ES2) + return BOARD_SDP_2430_T2; + else + return BOARD_SDP_2430_M1; +} + + +/*********************************************************************** +get_sdp_type() - get the sdp type : SDP or GDP based on the board id name tag. + On any failure conditions - due to lack of fpga information or + timeout, always default to SDP. +***********************************************************************/ +u32 get_sdp_type(void) +{ + if (check_eeprom_avail(EEPROM_MAIN_BRD)) { + volatile char *m_brd_name = (char *)(EEPROM_MAIN_BRD+0x08); + char t_brd_name[] = GDP_MB_EE_NAME; + int count=0; + + /* scan to check if all the characters match */ + /* Move ahead to name location */ + count = sizeof(t_brd_name) -2; + while ((m_brd_name[count] == t_brd_name[count]) && count) { + count--; + } + /* Match?? */ + if (!count) { + /* GDP!! */ + return BOARD_GDP_2430_T2; + } + else { + return BOARD_SDP_2430_T2; + } + } + else return BOARD_SDP_2430_T2; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings (dip switch on h4) + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return (0x00000FFF & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return (WIDTH_16BIT); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + * 0x00 = old H4 SDP + * 0x01 = 0.1. wakeup + * 0x10 = 1.0. Adds OneNAND, Sibley NOR, new camera + * 0x11 = 1.1. Adds T2 + * 0x20 = 2.0. ES2.0 Silicon + * TODO: Figure a way out to differentiate b/w various board versions + *************************************************************************/ +u32 get_board_rev(void) +{ + /* Currently reading EEPROM reg to get UI board version and try it out */ + volatile char *ui_brd_name = (char *)EEPROM_UI_BRD; + char enhanced_ui_brd_name[] = ENHANCED_UI_EE_NAME; + int count = 0; + if (!check_eeprom_avail(EEPROM_UI_BRD)) { + /* timed out OR fpga rev not found!! */ + /* Assume 1.0 */ + return 0x01; + } + /* Move ahead to name location */ + ui_brd_name += 0x08; + count = sizeof(enhanced_ui_brd_name) - 2; + while ((enhanced_ui_brd_name[count] == ui_brd_name[count]) && count) { + count--; + } + /* Match?? */ + if (!count) { + /* Enhanced UI board.. SDP1.1 */ + return 0x11; + } + /* Legacy UI - hope they are all 1.0 boards.. */ + return (0x10); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char *bootmode[] = { + "ONND", + "SIB1", + "SIB0", + "NAND", + "SIB1", + "SIB0", + "NOR", + "NOR", + }; + u32 brev = get_board_rev(); + char cpu_2430s[] = "2430C"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; + char t_sdp[] = "2430SDP"; + char t_gdp[] = "2430GDP"; +#ifdef CONFIG_LED_INFO + char led_string[CONFIG_LED_LEN] = { 0 }; +#endif + +#if defined(PRCM_CONFIG_2) + char prcm[] = "#2"; +#elif defined(PRCM_CONFIG_3) + char prcm[] = "#3"; +#elif defined(PRCM_CONFIG_5A) + char prcm[] = "#5A"; +#elif defined(PRCM_CONFIG_5B) + char prcm[] = "#5B" +#endif + char *cpu_s, *db_s, *mem_s, *sec_s, *sdp; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + cpu_s = cpu_2430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + if (get_sdp_type() == BOARD_GDP_2430_T2) { + sdp=t_gdp; + } else { + sdp=t_sdp; + } + printf("OMAP%s-%s revision %d, PRCM %s\n", cpu_s, sec_s, rev, prcm); + printf("TI %s %s Version + %s (Boot %s)\n",sdp, db_s, + mem_s, bootmode[get_gpmc0_type()]); +#ifdef CONFIG_LED_INFO + /* Format: 0123456789ABCDEF + * 2430C GP#5A NAND + */ + sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, prcm, + bootmode[get_gpmc0_type()]); + /* reuse sec */ + for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) { + /* invert byte loc */ + u16 val = led_string[sec] << 8; + val |= led_string[sec + 1]; + __raw_writew(val, LED_REGISTER + sec); + } +#endif + +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} + +/************************************************************* + * running_from_internal_boot() - am I boot through mask rom. + *************************************************************/ +u32 running_from_internal_boot(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT2 | BIT1 | BIT0); + /* external boot settings bit1 == bit2 */ + if (((v & BIT1) && (v & BIT2)) || (!(v & BIT1) && !(v & BIT2))) + v = 0; + else /* all other defined combos are internal */ + v = 1; + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return (mode >>= 8); +} diff --git a/board/omap2430sdp/u-boot.lds b/board/omap2430sdp/u-boot.lds new file mode 100644 index 000000000..724c1dd48 --- /dev/null +++ b/board/omap2430sdp/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3430labrador/Makefile b/board/omap3430labrador/Makefile new file mode 100644 index 000000000..1bd516429 --- /dev/null +++ b/board/omap3430labrador/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omap3430labrador.o sys_info.o + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap3430labrador/config.mk b/board/omap3430labrador/config.mk new file mode 100644 index 000000000..03f071f24 --- /dev/null +++ b/board/omap3430labrador/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2006 +# Texas Instruments, +# +# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP3430 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap3430labrador/omap3430labrador.c b/board/omap3430labrador/omap3430labrador.c new file mode 100644 index 000000000..eeb1aea82 --- /dev/null +++ b/board/omap3430labrador/omap3430labrador.c @@ -0,0 +1,857 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_3430ZOOM2 +#include "../omap3430zoom2/board_rev.h" +#endif + +int get_boot_type(void); +void v7_flush_dcache_all(int, int); +void l2cache_enable(void); +void setup_auxcr(int, int); +void eth_init(void *); + + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ +#ifdef CONFIG_3430ZOOM2 + gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2; /* Linux mach id*/ +#ifdef CONFIG_BOARD_REVISION + gd->bd->bi_board_revision = zoom2_board_revision(); +#endif +#else + gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430LABRADOR; /* Linux mach id*/ +#endif + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */ + + return 0; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_1); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_2); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_3); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + + +/********************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world + * general use. + ***********************************************************/ +void secureworld_exit(void) +{ + unsigned long i; + + /* configrue non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r" (i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); + /* allow allocation of locked TLBs and L2 lines in NS world */ + /* allow use of PLE registers in NS world also */ + __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r" (i)); + + /* Enable ASA and IBE in ACR register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x50":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r" (i)); +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + int in_sdram = running_in_sdram(); + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock_mem(); + } + /* If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ +void s_init(void) +{ + int i; + int external_boot = 0; + int in_sdram = running_in_sdram(); + +#ifdef CONFIG_3430VIRTIO + in_sdram = 0; /* allow setup from memory for Virtio */ +#endif + watchdog_init(); + + external_boot = (get_boot_type() == 0x1F) ? 1 : 0; + /* Right now flushing at low MPU speed. Need to move after clock init */ + v7_flush_dcache_all(get_device_type(), external_boot); + + try_unlock_memory(); + +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5A80, CONTROL_SCALABLE_OMAP_OCP); +#endif + + if (cpu_is_3410()) { + /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ + __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); + } + +#ifndef CONFIG_ICACHE_OFF + icache_enable(); +#endif + +#ifdef CONFIG_L2_OFF + l2cache_disable(); +#else + l2cache_enable(); +#endif + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + setup_auxcr(get_device_type(), external_boot); + + prcm_init(); + + per_clocks_enable(); + + if (!in_sdram) + sdrc_init(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ +#ifdef CONFIG_3430ZOOM2 + { + /* GPIO LEDs + 154 blue , bank 5, index 26 + 173 red , bank 6, index 13 + 61 blue2, bank 2, index 29 + + GPIO to query for debug board + 158 db board query, bank 5, index 30 + This is an input only, no additional setup is needed */ + + gpio_t *gpio2_base = (gpio_t *)OMAP34XX_GPIO2_BASE; + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + + /* Configure GPIOs to output */ + sr32((u32)&gpio2_base->oe, 29, 1, 0); + sr32((u32)&gpio5_base->oe, 26, 1, 0); + sr32((u32)&gpio6_base->oe, 13, 1, 0); + + sr32((u32)&gpio6_base->cleardataout, 13, 1, 1); /* red off */ + sr32((u32)&gpio5_base->setdataout, 26, 1, 1); /* blue on */ + sr32((u32)&gpio2_base->setdataout, 29, 1, 1); /* blue 2 on */ + } +#endif +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + unsigned char data; + extern int twl4030_init_battery_charging(void); + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* + * Board Reset + * + * For Zoom1: + * + * Enable resetting the board by pressing the red button + * on the top right on the front side of the main board and + * holding for eight seconds. + */ + twl4030_power_reset_init(); + twl4030_usb_init(); + twl4030_keypad_init(); + twl4030_init_battery_charging(); + /* see if we need to activate the power button startup */ + char *s = getenv("pbboot"); + if (s) { + /* figure out why we have booted */ + i2c_read(0x4b, 0x3a, 1, &data, 1); + + /* if status is non-zero, we didn't transition + * from WAIT_ON state + */ + if (data) { + printf("Transitioning to Wait State (%x)\n", data); + + /* clear status */ + data = 0; + i2c_write(0x4b, 0x3a, 1, &data, 1); + + /* put PM into WAIT_ON state */ + data = 0x01; + i2c_write(0x4b, 0x46, 1, &data, 1); + + /* no return - wait for power shutdown */ + while (1) {;} + } + printf("Transitioning to Active State (%x)\n", data); + + /* turn on long pwr button press reset*/ + data = 0x40; + i2c_write(0x4b, 0x46, 1, &data, 1); + printf("Power Button Active\n"); + } +#endif + ether_init(); /* better done here so timers are init'ed */ + dieid_num_r(); + return (0); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01; + udelay(1000); + + h4reset_err_out: + return; + +#elif CONFIG_3430LABRADOR + DECLARE_GLOBAL_DATA_PTR; + eth_init(gd->bd); +#endif +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + #define NOT_EARLY 0 + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; + + btype = get_board_type(); + mtype = get_mem_type(); +#ifndef CONFIG_3430ZEBU + /* fixme... dont know why this func is crashing in ZeBu */ + display_board_info(btype); +#endif + /* If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT_ES2()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IEN | PTD | DIS | M4)) /*GPIO_54 lab*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTD | DIS | M4)) /*GPIO_55 lab*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M4)) /*GPIO_56 lab*/\ + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS ), (IDIS | PTD | DIS | M7)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS ), (IDIS | PTD | DIS | M7)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 */\ + MUX_VAL(CP(CAM_D0 ), (IEN | PTD | DIS | M2)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1 ), (IEN | PTD | DIS | M2)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_101 */\ + MUX_VAL(CP(CAM_D3 ), (IEN | PTD | DIS | M4)) /*GPIO_102 */\ + MUX_VAL(CP(CAM_D4 ), (IEN | PTD | DIS | M4)) /*GPIO_103 */\ + MUX_VAL(CP(CAM_D5 ), (IEN | PTD | DIS | M4)) /*GPIO_104 */\ + MUX_VAL(CP(CAM_D6 ), (IEN | PTD | DIS | M4)) /*GPIO_105 */\ + MUX_VAL(CP(CAM_D7 ), (IEN | PTD | DIS | M4)) /*GPIO_106 */\ + MUX_VAL(CP(CAM_D8 ), (IEN | PTD | DIS | M4)) /*GPIO_107 */\ + MUX_VAL(CP(CAM_D9 ), (IEN | PTD | DIS | M4)) /*GPIO_108 */\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M7)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M4)) /*GPIO_126 - lab*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + /* sim lab */\ + MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*uP_spi lab */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M1)) /*mcspi3_ck lab*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M1)) /*mcspi3_simo lab*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M1)) /*mcspi3_somi lab*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*gpio_133 lab*/\ + MUX_VAL(CP(MMC2_DAT2), (IDIS | PTD | EN | M1)) /*mcspi3_cs1 lab*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M1)) /*mcspi3_cs0 lab*/\ + /* MMC3 lab */\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M3)) /*mmc3_dat0 lab*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M3)) /*mmc3_dat1 lab*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M3)) /*mmc3_dat2 lab*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M3)) /*mmc3_dat3 lab*/\ + /* pcm out */\ + MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\ + MUX_VAL(CP(McBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\ + MUX_VAL(CP(McBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/\ + MUX_VAL(CP(McBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\ + /* uart2 */\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + /*per irqs */\ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M4)) /*gpio_152 lab*/\ + MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M4)) /*gpio_153 lab*/\ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M4)) /*gpio_154 lab*/\ + MUX_VAL(CP(McBSP4_FSX), (IDIS | PTD | DIS | M4)) /*gpio_155 lab*/\ + /* per func*/\ + MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | EN | M2)) /*sim_cd lab*/\ + MUX_VAL(CP(McBSP1_FSR), (IEN | PTU | EN | M4)) /*gpio_157 lab*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTU | EN | M4)) /*gpio_158 lab*/\ + MUX_VAL(CP(McBSP1_DR), (IEN | PTU | EN | M4)) /*gpio_159 lab*/\ + MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | EN | M4)) /*unused lab*/\ + MUX_VAL(CP(McBSP1_FSX), (IEN | PTU | EN | M4)) /*gpio_161 lab*/\ + MUX_VAL(CP(McBSP1_CLKX), (IEN | PTU | EN | M4)) /*gpio_162 lab*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0 */\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1 */\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2 */\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3 */\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4 */\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5 */\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6 */\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7 */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\ + MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M3)) /*mmc3_cmd lab*/\ + MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M3)) /*mmc3_clk lab*/\ + MUX_VAL(CP(McSPI1_CS3), (IDIS | PTD | DIS | M3)) /*hsusb2_data2 lab*/\ + /*hsusb2 lab */\ + MUX_VAL(CP(McSPI2_CLK), (IDIS | PTD | DIS | M3)) /*hsusb2_d7 lab*/\ + MUX_VAL(CP(McSPI2_SIMO), (IDIS | PTD | DIS | M3)) /*hsusb2_d4 lab*/\ + MUX_VAL(CP(McSPI2_SOMI), (IDIS | PTD | DIS | M3)) /*hsusb2_d5 lab*/\ + MUX_VAL(CP(McSPI2_CS0), (IDIS | PTD | DIS | M3)) /*hsusb2_d6 lab*/\ + MUX_VAL(CP(McSPI2_CS1), (IDIS | PTD | DIS | M3)) /*hsusb2_d3 lab*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 - */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 - */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 - */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 - */\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8 - */\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ + /* clkout1 to t2-hfclkin, clkout2 to usb transeiver (both 26mhz) lab */\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | DIS | M0)) /*emu0/gpio11 lab*/\ + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M0)) /*emu1/gpio31 lab*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*USB1_STP lab*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*USB1_CLK lab*/\ + MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA0 lab*/\ + MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA1 lab*/\ + MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA2 lab*/\ + MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA7 lab*/\ + MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA4 lab*/\ + MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA5 lab*/\ + MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA6 lab*/\ + MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA3 lab*/\ + MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DIR lab*/\ + MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_NXT lab*/\ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M3)) /*USB2_CLK lab*/\ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M3)) /*USB2_STP lab*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB2_DIR lab*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB2_NXT lab*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA0 lab*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA1 lab*/\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (IEN | PTD | EN | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 unused*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT_ES2(); + + /* Set ZOOM2 specific mux */ +#ifdef CONFIG_3430ZOOM2 + /* IDCC modem Power On */ + MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /*gpio_110*/ + MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /*GPIO_103 */ + + /* GPMC CS7 has LAN9211 device */ + MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7 lab*/ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*gpio_158 lab: for LAN9221 on zoom2*/ + MUX_VAL(CP(McSPI1_CS2), (IEN | PTD | EN | M0)) /*mcspi1_cs2 zoom2*/ + + /* GPMC CS3 has Serial TL16CP754C device */ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3 lab*/ + /* Toggle Reset pin of TL16CP754C device */ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTU | EN | M4)) /*gpio_152 lab*/ + delay(10); + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | EN | M4)) /*gpio_152 lab*/ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTU | EN | M0)) /*sdrc_cke1 */ + + /* leds */ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | EN | M4)) /* gpio_173 red */ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | EN | M4)) /* gpio_154 blue */ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | EN | M4)) /* gpio_61 blue2 */ + /* Keep UART3 RX line pulled-up: + * Crashs have been seen on Zoom2 otherwise + */ + MUX_VAL(CP(UART3_RX_IRRX),(IEN | PTU | DIS | M0)) /*UART3_RX_IRRX*/ + + /* gpio 94 is used to detect preproduction vs production boards */ + MUX_VAL(CP(CAM_HS), (IEN | PTD | DIS | M4)) /*gpio_94 */ + +#endif +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} + diff --git a/board/omap3430labrador/sys_info.c b/board/omap3430labrador/sys_info.c new file mode 100644 index 000000000..148fa4e08 --- /dev/null +++ b/board/omap3430labrador/sys_info.c @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include +#include + +#ifdef CONFIG_3430ZOOM2 +#include "../omap3430zoom2/board_rev.h" +#endif + +/************************************************************************ + * get_gpmc0_type() - read sysboot lines to see type of memory attached + ************************************************************************/ +u32 get_gpmc0_type(void) +{ + u32 type; + type = get_sysboot_value(); +// if ((type & (BIT3|BIT2)) == (BIT3|BIT2)) + return(TYPE_NAND); +} + +/**************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + ****************************************************/ +u32 get_cpu_type(void) +{ + return (CPU_3430); +} + +/* + * cpu_is_3410(void) - returns true for 3410 + */ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3XX_ES20) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* + * Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == SDP_SDRC_MR_0_SDR) + return (1); + return (0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + ***********************************************************/ +u32 get_mem_type(void) +{ + return (DDR_DISCRETE); /* LAB has single stacked x32 POP die */ +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/*********************************************************************** + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + ************************************************************************/ +u32 get_board_type(void) +{ + return BOARD_3430_LABRADOR; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return (0x0000003F & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return (WIDTH_16BIT); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +u32 get_board_rev(void) +{ + return (BOARD_3430_LABRADOR_V1); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char *bootmode[] = { + "NOR", + "ONND", + "NAND", + }; + u32 brev = get_board_rev(); + char cpu_3430s[] = "3430"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; + +#if defined(L3_165MHZ) + char p_l3[] = "165"; +#elif defined(L3_110MHZ) + char p_l3[] = "110"; +#elif defined(L3_133MHZ) + char p_l3[] = "133"; +#elif defined(L3_100MHZ) + char p_l3[] = "100" +#endif + +#if defined(PRCM_PCLK_OPP1) + char p_cpu[] = "1"; +#elif defined(PRCM_PCLK_OPP2) + char p_cpu[] = "2"; +#elif defined(PRCM_PCLK_OPP3) + char p_cpu[] = "3"; +#elif defined(PRCM_PCLK_OPP4) + char p_cpu[] = "4" +#endif + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + cpu_s = cpu_3430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev, p_cpu, + p_l3); + +#ifdef CONFIG_3430ZOOM2 + printf("OMAP3430Zoom2 Rev %s + %s (Boot %s)\n", + ZOOM2_BOARD_REVISION_STRING(), + mem_s, bootmode[2]); + +#else + printf("OMAP3430LAB %s Version + %s (Boot %s)\n", db_s, + mem_s, bootmode[2]); +#endif +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * sdram. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 sys mem/perif + ***************************************************************/ +u32 get_boot_type(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return (mode >>= 8); +} diff --git a/board/omap3430labrador/u-boot.lds b/board/omap3430labrador/u-boot.lds new file mode 100644 index 000000000..6c811937f --- /dev/null +++ b/board/omap3430labrador/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3430sdp/Makefile b/board/omap3430sdp/Makefile new file mode 100644 index 000000000..361c9e94b --- /dev/null +++ b/board/omap3430sdp/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omap3430sdp.o mem.o clock.o syslib.o sys_info.o nand.o +SOBJS := lowlevel_init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap3430sdp/clock.c b/board/omap3430sdp/clock.c new file mode 100644 index 000000000..5012cc2b8 --- /dev/null +++ b/board/omap3430sdp/clock.c @@ -0,0 +1,352 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; + +#define MAX_SIL_INDEX 3 +typedef struct dpll_param dpll_param; + +/* Following functions are exported from lowlevel_init.S */ + +extern dpll_param * get_mpu_dpll_param(void); +extern dpll_param * get_iva_dpll_param(void); +extern dpll_param * get_core_dpll_param(void); +extern dpll_param * get_per_dpll_param(void); + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(void) +{ + u32 start, cstart, cend, cdiff, val; + + val = __raw_readl(PRM_CLKSRC_CTRL); + /* If SYS_CLK is being divided by 2, remove for now */ + val = (val & (~BIT7)) | BIT6; + __raw_writel(val, PRM_CLKSRC_CTRL); + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; + __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ + + /* Enable I and F Clocks for GPT1 */ + val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; + __raw_writel(val, CM_ICLKEN_WKUP); + val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; + __raw_writel(val, CM_FCLKEN_WKUP); + + __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ + /* enable 32kHz source *//* enabled out of reset */ + /* determine sys_clk via gauging */ + + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ + while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ + cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ + while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ + cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + + /* based on number of ticks assign speed */ + if (cdiff > 19000) + return (S38_4M); + else if (cdiff > 15200) + return (S26M); + else if (cdiff > 13000) + return (S24M); + else if (cdiff > 9000) + return (S19_2M); + else if (cdiff > 7600) + return (S13M); + else + return (S12M); +} + +/****************************************************************************** + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * -- input oscillator clock frequency. + * + *****************************************************************************/ +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) +{ + if(osc_clk == S38_4M) + *sys_clkin_sel= 4; + else if(osc_clk == S26M) + *sys_clkin_sel = 3; + else if(osc_clk == S19_2M) + *sys_clkin_sel = 2; + else if(osc_clk == S13M) + *sys_clkin_sel = 1; + else if(osc_clk == S12M) + *sys_clkin_sel = 0; +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + void (*f_lock_pll) (u32, u32, u32, u32); + int xip_safe, p0, p1, p2, p3; + u32 osc_clk=0, sys_clkin_sel; + extern void *_end_vect, *_start; + u32 clk_index, sil_index=0; + dpll_param *dpll_param_p; + + f_lock_pll = + (void *)((u32) & _end_vect - (u32) & _start + SRAM_VECT_CODE); + + xip_safe = running_in_sram(); +#ifdef CONFIG_3430VIRTIO + xip_safe = 1; +#endif + /* Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ + + sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ + clk_index = sys_clkin_sel; + + sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ + + /* + * The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ + if (cpu_is_3410()) { + sil_index = 2; + } else { + if (get_cpu_rev() == CPU_3XX_ES10) + sil_index = 0; + else if (get_cpu_rev() >= CPU_3XX_ES20) + sil_index = 1; + } + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address of Core DPLL param table*/ + dpll_param_p = (dpll_param *)get_core_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + if(xip_safe){ + /* CORE DPLL */ + /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); + /* For 3430 ES1.0 Errata 1.50, default value directly doesnt + work. write another value and then default value. */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ + sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ + sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only */ + sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ + sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ + sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ + sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ + sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); + } else if(running_in_flash()){ + /* if running from flash, jump to small relocated code area in SRAM.*/ + p0 = __raw_readl(CM_CLKEN_PLL); + sr32((u32)&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); + sr32((u32)&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + + p1 = __raw_readl(CM_CLKSEL1_PLL); + sr32((u32)&p1, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32((u32)&p1, 16, 11, dpll_param_p->m); /* Set M */ + sr32((u32)&p1, 8, 7, dpll_param_p->n); /* Set N */ + sr32((u32)&p1, 6, 1, 0); /* set source for 96M */ + p2 = __raw_readl(CM_CLKSEL_CORE); + sr32((u32)&p2, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32((u32)&p2, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only*/ + sr32((u32)&p2, 2, 2, CORE_L4_DIV); /* l4 */ + sr32((u32)&p2, 0, 2, CORE_L3_DIV); /* l3 */ + + p3 = CM_IDLEST_CKGEN; + + (*f_lock_pll) (p0, p1, p2, p3); + } + + /* PER DPLL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to PER DPLL param table*/ + /* Set N */ + dpll_param_p = (dpll_param *)get_per_dpll_param(); + /* Moving it to the right sysclk base */ + dpll_param_p = dpll_param_p + clk_index; + /* Errata 1.50 Workaround for 3430 ES1.0 only */ + /* If using default divisors, write default divisor + 1 + and then the actual divisor value */ + /* Need to change it to silicon and revisino check */ + if(1) { + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2 + 1); /* set M6 */ + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2 + 1); /* set M5 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2 + 1); /* set M4 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2 + 1); /* set M3 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2 + 1);/* set M2 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + } + else { + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + } + sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ + sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to MPU DPLL param table*/ + dpll_param_p = (dpll_param *)get_mpu_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address to IVA DPLL param table*/ + dpll_param_p = (dpll_param *)get_iva_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* IVA DPLL (set to 12*20=240MHz) */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); + sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ + /* IVA bypass clock set to CORECLK/4=(83Mhz) at OPP1 */ + sr32(CM_CLKSEL1_PLL_IVA2, 19, 3, 4); /* set CLK_SRC */ + sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ + sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ + sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); + + /* Set up GPTimers to sys_clk source only */ + sr32(CM_CLKSEL_PER, 0, 8, 0xff); + sr32(CM_CLKSEL_WKUP, 0, 1, 1); + + sdelay(5000); +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void per_clocks_enable(void) +{ + /* Enable GP2 timer. */ + sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ + sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ + sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ + +#ifdef CFG_NS16550 + /* Enable UART1 clocks */ + sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); + sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); +#endif +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + /* Turn on all 3 I2C clocks*/ + sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); + sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ +#endif + /* Enable the ICLK for 32K Sync Timer as its used in udelay */ + sr32(CM_ICLKEN_WKUP,2, 1, 0x1); +#ifdef CONFIG_MMC + #define FCK_MMC_ON 0x1 + #define ICK_MMC_ON 0x1 + sr32(CM_FCLKEN1_CORE, 24, 1, FCK_MMC_ON); + sr32(CM_ICLKEN1_CORE, 24, 1, ICK_MMC_ON); +#endif /* CONFIG_MMC */ + +//#define CLOCKS_ALL_ON 1 +#ifdef CLOCKS_ALL_ON + #define FCK_IVA2_ON 0x00000001 + #define FCK_CORE1_ON 0x03fffe29 + #define ICK_CORE1_ON 0x3ffffffb + #define ICK_CORE2_ON 0x0000001f + #define FCK_WKUP_ON 0x000000e9 + #define ICK_WKUP_ON 0x0000003f + #define FCK_DSS_ON 0x00000005 /* tv+dss1 (not dss2) */ + #define ICK_DSS_ON 0x00000001 + #define FCK_CAM_ON 0x00000001 + #define ICK_CAM_ON 0x00000001 + #define FCK_PER_ON 0x0003ffff + #define ICK_PER_ON 0x0003ffff + sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); + sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); + sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); + sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); + sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); + sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); + sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); + sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); + sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); + sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); + sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); + sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); +#endif + sdelay(1000); +} diff --git a/board/omap3430sdp/config.mk b/board/omap3430sdp/config.mk new file mode 100644 index 000000000..03f071f24 --- /dev/null +++ b/board/omap3430sdp/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2006 +# Texas Instruments, +# +# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP3430 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap3430sdp/lowlevel_init.S b/board/omap3430sdp/lowlevel_init.S new file mode 100644 index 000000000..2fda1d9db --- /dev/null +++ b/board/omap3430sdp/lowlevel_init.S @@ -0,0 +1,358 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this code + * runs from flash before SDR is init so that should be ok. + ******************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4-r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4-r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x0FE,0x07,0x05,0x01 +/* ES2 */ +.word 0x0FA,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x17D,0x0C,0x03,0x01 +/* ES2 */ +.word 0x1F4,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x179,0x12,0x04,0x01 +/* ES2 */ +.word 0x271,0x17,0x03,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x17D,0x19,0x03,0x01 +/* ES2 */ +.word 0x0FA,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x1FA,0x32,0x03,0x01 +/* ES2 */ +.word 0x271,0x2F,0x03,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x07D,0x05,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x0FA,0x0C,0x03,0x01 +/* ES2 */ +.word 0x168,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x082,0x09,0x07,0x01 +/* ES2 */ +.word 0x0E1,0x0B,0x06,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x07D,0x0C,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x13F,0x30,0x03,0x01 +/* ES2 */ +.word 0x0E1,0x17,0x06,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + +/* Core DPLL targets for L3 at 166 & L133 */ +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 +/* ES2 */ +.word M_12,N_12,FSEL_12,M2_12 +/* 3410 */ +.word M_12,N_12,FSEL_12,M2_12 + +/* 13MHz */ +/* ES1 */ +.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 +/* ES2 */ +.word M_13,N_13,FSEL_13,M2_13 +/* 3410 */ +.word M_13,N_13,FSEL_13,M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 +/* ES2 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 +/* 3410 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 + +/* 26MHz */ +/* ES1 */ +.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 +/* ES2 */ +.word M_26,N_26,FSEL_26,M2_26 +/* 3410 */ +.word M_26,N_26,FSEL_26,M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 +/* ES2 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 +/* 3410 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word 0xD8,0x05,0x07,0x09 + +/* 13MHz */ +.word 0x1B0,0x0C,0x03,0x09 + +/* 19.2MHz */ +.word 0xE1,0x09,0x07,0x09 + +/* 26MHz */ +.word 0xD8,0x0C,0x07,0x09 + +/* 38.4MHz */ +.word 0xE1,0x13,0x07,0x09 + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + diff --git a/board/omap3430sdp/mem.c b/board/omap3430sdp/mem.c new file mode 100644 index 000000000..a3dad9623 --- /dev/null +++ b/board/omap3430sdp/mem.c @@ -0,0 +1,597 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/****** DATA STRUCTURES ************/ + +/* Only One NAND allowed on board at a time. + * The GPMC CS Base for the same + */ +unsigned int nand_cs_base = 0; +unsigned int onenand_cs_base = 0; +unsigned int boot_flash_base = 0; +unsigned int boot_flash_off = 0; +unsigned int boot_flash_sec = 0; +unsigned int boot_flash_type = 0; +volatile unsigned int boot_flash_env_addr = 0; +/* help common/env_flash.c */ +#ifdef ENV_IS_VARIABLE + +ulong NOR_FLASH_BANKS_LIST[CFG_MAX_FLASH_BANKS]; + +int NOR_MAX_FLASH_BANKS = 0 ; /* max number of flash banks */ + +uchar(*boot_env_get_char_spec) (int index); +int (*boot_env_init) (void); +int (*boot_saveenv) (void); +void (*boot_env_relocate_spec) (void); + +/* StrataNor */ +extern uchar flash_env_get_char_spec(int index); +extern int flash_env_init(void); +extern int flash_saveenv(void); +extern void flash_env_relocate_spec(void); +extern char *flash_env_name_spec; + +/* 16 bit NAND */ +extern uchar nand_env_get_char_spec(int index); +extern int nand_env_init(void); +extern int nand_saveenv(void); +extern void nand_env_relocate_spec(void); +extern char *nand_env_name_spec; + +/* OneNAND */ +extern char *onenand_env; +extern uchar onenand_env_get_char_spec(int index); +extern int onenand_env_init(void); +extern int onenand_saveenv(void); +extern void onenand_env_relocate_spec(void); +extern char *onenand_env_name_spec; + +/* Global fellows */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +u8 is_nand = 0; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) +u8 is_flash = 0; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) +u8 is_onenand = 0; +#endif + +char *env_name_spec = 0; +/* update these elsewhere */ +env_t *env_ptr = 0; + +#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH)) +extern env_t *flash_addr; +#endif + +#endif /* ENV_IS_VARIABLE */ + +/* SDP3430 Board CS Organization + * Two PISMO connections are specified. PISMO1 is first and default PISMO board + * PISMO2 is a 2nd stacked PISMOv2 board and is meant for vendor extensions. + */ +static const unsigned char chip_sel[][GPMC_MAX_CS] = { +/* GPMC CS Indices (ON=0, OFF=1)*/ +/* S8- 1 2 3 IDX CS0, CS1, CS2 .. CS7 */ +/*ON ON ON */{PISMO1_NOR, PISMO1_NAND, PISMO1_ONENAND, DBG_MPDB, 0, 0, 0, 0}, +/*ON ON OFF */{PISMO1_ONENAND, PISMO1_NAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, +/*ON OFF ON */{PISMO1_NAND, PISMO1_ONENAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, +/*ON OFF OFF */{PISMO2_CS0, PISMO1_ONENAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, +/*OFF ON ON*/{PISMO1_NOR, PISMO2_CS1, PISMO1_ONENAND, DBG_MPDB, 0, 0, 0, 0}, +/*OFF ON OFF*/{PISMO1_NOR, PISMO2_CS1, PISMO2_CS0, DBG_MPDB, 0, 0, 0, 0}, +/*OFF OFF ON*/{PISMO2_CS0, PISMO1_NOR, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, +/*OFF OFF OFF*/{PISMO2_CS1, PISMO1_NOR, PISMO2_CS0, DBG_MPDB, 0, 0, 0, 0} +}; + +/* SDP3430 V2 Board CS organization + * Different from SDP3430 V1. Now 4 switches used to specify CS + */ +static const unsigned char chip_sel_sdpv2[][GPMC_MAX_CS] = { +/* GPMC CS Indices (ON=0, OFF=1)*/ +/* S8-1 2 3 4 IDX CS0, CS1, CS2 .. CS7 */ +/*ON ON ON ON*/{PISMO1_NOR, PISMO1_NAND, PISMO1_ONENAND, DBG_MPDB, 0, 0, 0, 0}, +/*ON ON ON OFF*/{PISMO1_ONENAND, PISMO1_NAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, +/*ON ON OFF ON */{PISMO1_NAND, PISMO1_ONENAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, +/*ON ON OFF OFF*/{PISMO1_NOR, PISMO2_CS0, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, +/*ON OFF ON ON*/{PISMO1_ONENAND, PISMO2_CS0, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, +/*ON OFF ON OFF*/{PISMO1_NAND, PISMO2_CS0, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, +/*ON OFF OFF ON*/{PISMO1_NOR, PISMO2_NAND_CS0, PISMO2_NAND_CS1, DBG_MPDB, 0, 0, 0, 0}, +/*ON OFF OFF OFF*/{PISMO1_ONENAND, PISMO2_NAND_CS0, PISMO2_NAND_CS1, DBG_MPDB, 0, 0, 0, 0} +}; + +/* Values for each of the chips */ +static u32 gpmc_mpdb[GPMC_MAX_REG] = { + MPDB_GPMC_CONFIG1, + MPDB_GPMC_CONFIG2, + MPDB_GPMC_CONFIG3, + MPDB_GPMC_CONFIG4, + MPDB_GPMC_CONFIG5, + MPDB_GPMC_CONFIG6, 0 +}; +static u32 gpmc_mpdb_v2[GPMC_MAX_REG] = { + SDPV2_MPDB_GPMC_CONFIG1, + SDPV2_MPDB_GPMC_CONFIG2, + SDPV2_MPDB_GPMC_CONFIG3, + SDPV2_MPDB_GPMC_CONFIG4, + SDPV2_MPDB_GPMC_CONFIG5, + SDPV2_MPDB_GPMC_CONFIG6, 0 +}; +static u32 gpmc_stnor[GPMC_MAX_REG] = { + STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, 0 +}; +static u32 gpmc_sibnor[GPMC_MAX_REG] = { + SIBNOR_GPMC_CONFIG1, + SIBNOR_GPMC_CONFIG2, + SIBNOR_GPMC_CONFIG3, + SIBNOR_GPMC_CONFIG4, + SIBNOR_GPMC_CONFIG5, + SIBNOR_GPMC_CONFIG6, 0 +}; +static u32 gpmc_smnand[GPMC_MAX_REG] = { + SMNAND_GPMC_CONFIG1, + SMNAND_GPMC_CONFIG2, + SMNAND_GPMC_CONFIG3, + SMNAND_GPMC_CONFIG4, + SMNAND_GPMC_CONFIG5, + SMNAND_GPMC_CONFIG6, 0 +}; +static u32 gpmc_pismo2[GPMC_MAX_REG] = { + P2_GPMC_CONFIG1, + P2_GPMC_CONFIG2, + P2_GPMC_CONFIG3, + P2_GPMC_CONFIG4, + P2_GPMC_CONFIG5, + P2_GPMC_CONFIG6, 0 +}; +static u32 gpmc_onenand[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, 0 +}; + +/********** Functions ****/ + +/* ENV Functions */ +#ifdef ENV_IS_VARIABLE +uchar env_get_char_spec(int index) +{ + if (!boot_env_get_char_spec) { + puts("ERROR!! env_get_char_spec not available\n"); + } else + return boot_env_get_char_spec(index); + return 0; +} +int env_init(void) +{ + if (!boot_env_init) { + puts("ERROR!! boot_env_init not available\n"); + } else + return boot_env_init(); + return -1; +} +int saveenv(void) +{ + if (!boot_saveenv) { + puts("ERROR!! boot_saveenv not available\n"); + } else + return boot_saveenv(); + return -1; +} +void env_relocate_spec(void) +{ + if (!boot_env_relocate_spec) { + puts("ERROR!! boot_env_relocate_spec not available\n"); + } else + boot_env_relocate_spec(); +} +#endif + + +/************************************************************************** + * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow + * command line mem=xyz use all memory with out discontinuous support + * compiled in. Could do it at the ATAG, but there really is two banks... + * Called as part of 2nd phase DDR init. + **************************************************************************/ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(SDRC_CS0_OSET); + size /= SZ_32M; /* find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG); + +} + +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in guessing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(void) +{ + u32 val1, val2, addr; + u32 pattern = 0x12345678; + + addr = OMAP34XX_SDRC_CS0; + + __raw_writel(0x0, addr + 0x400); /* clear pos A */ + __raw_writel(pattern, addr); /* pattern to pos B */ + __raw_writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = __raw_readl(addr + 0x400); /* get pos A value */ + val2 = __raw_readl(addr); /* get val2 */ + + if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed */ + return (0); + else + return (1); +} + +/******************************************************** + * sdrc_init() - init the sdrc chip selects CS0 and CS1 + * - early init routines, called from flash or + * SRAM. + *******************************************************/ +void sdrc_init(void) +{ +#define EARLY_INIT 1 + do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */ +} + +/************************************************************************* + * do_sdrc_init(): initialize the SDRAM for use. + * -code sets up SDRAM basic SDRC timings for CS0 + * -optimal settings can be placed here, or redone after i2c + * inspection of board info + * + * - code called ones in C-Stack only context for CS0 and a possible 2nd + * time depending on memory configuration from stack+global context + **************************************************************************/ +void do_sdrc_init(u32 offset, u32 early) +{ + u32 common = 0, cs0 = 0, pmask = 0, pass_type, mtype, mono = 0; + + if (offset == SDRC_CS0_OSET) + cs0 = common = 1; /* int regs shared between both chip select */ + + pass_type = IP_DDR; + + /* If this is a 2nd pass init of a CS1, make it contiguous with CS0 */ + if (!early && (((mtype = get_mem_type()) == DDR_COMBO) + || (mtype == DDR_STACKED))) { + if (mtype == DDR_COMBO) { + pmask = BIT2; /* if shared CKE don't use */ + pass_type = COMBO_DDR; /* CS1 config */ + __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, + SDRC_POWER); + } + make_cs1_contiguous(); + } + +next_mem_type: + if (common) { /* do a SDRC reset between types to clear regs */ + + /* check if its h/w or s/w reset for warm reset workaround */ + if (__raw_readl(PRM_RSTTST) & 0x2) { + /* Enable SDRC clock & wait SDRC idle status to access*/ + sr32(CM_ICLKEN1_CORE, 1, 1, 0x1); + wait_on_value(BIT1, 0, CM_IDLEST1_CORE, LDELAY); + } else { + /* do a SDRC reset between types to clear regs */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG);/* reset sdrc */ + /* wait on reset */ + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + __raw_writel(0, SDRC_SYSCONFIG);/* clear soft reset */ + } + /* Clear reset sources */ + __raw_writel(0xfff, PRM_RSTTST); + + __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); + /* If its a 3430 ES1.0 silicon, configure WAKEUPPROC to 1 as + per Errata 1.22 */ + /* Need to change the condition to silicon and rev check */ + if(1) + __raw_writel((__raw_readl(SDRC_POWER)) | WAKEUPPROC + , SDRC_POWER); +#ifdef POWER_SAVE + __raw_writel(__raw_readl(SMS_SYSCONFIG) | SMART_IDLE, + SMS_SYSCONFIG); + __raw_writel(SDP_SDRC_SHARING | SMART_IDLE, SDRC_SHARING); + __raw_writel((__raw_readl(SDRC_POWER) | BIT6), SDRC_POWER); +#endif + } + + /* set MDCFG_0 values */ + if ((pass_type == IP_DDR) || (pass_type == STACKED)) { + /* ES 3.1 uses DDR2 */ + if (CPU_3XX_ES31 == get_cpu_rev()) + __raw_writel(SDP_SDRC_MDCFG_0_DDR_2G, + SDRC_MCFG_0 + offset); + else + __raw_writel(SDP_SDRC_MDCFG_0_DDR, + SDRC_MCFG_0 + offset); + + if (mono) /* Stacked with memory on CS1 only */ + __raw_writel(SDP_SDRC_MDCFG_MONO_DDR, + SDRC_MCFG_0 + offset); + } else if (pass_type == COMBO_DDR) { /* (combo-CS0/CS1) */ + __raw_writel(SDP_COMBO_MDCFG_0_DDR, SDRC_MCFG_0 + offset); + } else if (pass_type == IP_SDR) { /* ip sdr-CS0 */ + __raw_writel(SDP_SDRC_MDCFG_0_SDR, SDRC_MCFG_0 + offset); + } + + /* Set ACTIM values */ + if (cs0) { + __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + } else { + __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_1); + __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); + } + __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL_0 + offset); + + /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0 + offset); + sdelay(5000); /* supposed to be 100us per design spec for mddr/msdr */ + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0 + offset); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset); + + /* Set MR0 values */ + if (pass_type == IP_SDR) + __raw_writel(SDP_SDRC_MR_0_SDR, SDRC_MR_0 + offset); + else + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0 + offset); + + /* setup 343x DLL values (DDR only) */ + if (common && (pass_type != IP_SDR)) { + __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); + sdelay(0x2000); /* give time to lock, at least 1000 L3 */ + } + sdelay(0x1000); + + if (mono) /* Used if Stacked memory is on CS1 only */ + make_cs1_contiguous(); /* make CS1 appear at CS0 */ + + if (mem_ok()) + return; /* STACKED, other configured type */ + ++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */ + goto next_mem_type; +} + +void enable_gpmc_config(u32 * gpmc_config, u32 gpmc_base, u32 base, u32 size) +{ + __raw_writel(0, GPMC_CONFIG7 + gpmc_base); + sdelay(1000); + /* Delay for settling */ + __raw_writel(gpmc_config[0], GPMC_CONFIG1 + gpmc_base); + __raw_writel(gpmc_config[1], GPMC_CONFIG2 + gpmc_base); + __raw_writel(gpmc_config[2], GPMC_CONFIG3 + gpmc_base); + __raw_writel(gpmc_config[3], GPMC_CONFIG4 + gpmc_base); + __raw_writel(gpmc_config[4], GPMC_CONFIG5 + gpmc_base); + __raw_writel(gpmc_config[5], GPMC_CONFIG6 + gpmc_base); + /* Enable the config */ + __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), GPMC_CONFIG7 + gpmc_base); + sdelay(2000); +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ +/* putting a blanket check on GPMC based on ZeBu for now */ +#ifndef CONFIG_3430ZEBU + u32 mux = 0, mwidth; + u32 *gpmc_config = NULL; + u32 gpmc_base = 0; + u32 base = 0; + u8 idx = 0; + u32 size = 0; + u32 f_off = CFG_MONITOR_LEN; + u32 f_sec = 0; + u32 config = 0; + unsigned char *config_sel = NULL; + u32 i=0; + + mux = BIT9; + mwidth = get_gpmc0_width(); + + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL); /* timeout disable */ + + /* For SDPV2, FPGA uses WAIT1 line in active low mode */ + if(get_board_type() == SDP_3430_V2) { + config = __raw_readl(GPMC_CONFIG); + config &= (~0xf00); + __raw_writel(config, GPMC_CONFIG); + } + + /* Disable the GPMC0 config set by ROM code + * It conflicts with our MPDB (both at 0x08000000) + */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + sdelay(1000); + + if(get_board_type() == SDP_3430_V2) + gpmc_config = gpmc_mpdb_v2; + else + gpmc_config = gpmc_mpdb; + + /* GPMC3 is always MPDB.. need to know the chip info */ + gpmc_base = GPMC_CONFIG_CS0 + (3 * GPMC_CONFIG_WIDTH); + gpmc_config[0] |= mux; + enable_gpmc_config(gpmc_config, gpmc_base, DEBUG_BASE, DBG_MPDB_SIZE); + + /* Look up chip select map */ + idx = get_gpmc0_type(); + if(get_board_type() == SDP_3430_V2) + config_sel = (unsigned char *)(chip_sel_sdpv2[idx]); + else + config_sel = (unsigned char *)(chip_sel[idx]); + + /* Initialize each chip selects timings (may be to 0) */ + for (idx = 0; idx < GPMC_MAX_CS; idx++) { + gpmc_base = GPMC_CONFIG_CS0 + (idx * GPMC_CONFIG_WIDTH); + switch (config_sel[idx]) { + case PISMO1_NOR: + if(get_board_type() == SDP_3430_V2) { + gpmc_config = gpmc_sibnor; + f_sec = SZ_256K; + NOR_MAX_FLASH_BANKS = 1; + size = PISMO1_NOR_SIZE_SDPV2; + for(i=0; i < NOR_MAX_FLASH_BANKS; i++) + NOR_FLASH_BANKS_LIST[i] = + FLASH_BASE_SDPV2 + PHYS_FLASH_SIZE_SDPV2*i; + } + else { + gpmc_config = gpmc_stnor; + f_sec = SZ_128K; + NOR_MAX_FLASH_BANKS = 2; + size = PISMO1_NOR_SIZE; + for(i=0; i < NOR_MAX_FLASH_BANKS; i++) + NOR_FLASH_BANKS_LIST[i] = + FLASH_BASE_SDPV1 + PHYS_FLASH_SIZE*i; + } + gpmc_config[0] |= mux | TYPE_NOR | mwidth; + base = NOR_FLASH_BANKS_LIST[0]; + is_flash = 1; + break; +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + case PISMO1_NAND: + base = PISMO1_NAND_BASE; + size = PISMO1_NAND_SIZE; + gpmc_config = gpmc_smnand; + nand_cs_base = gpmc_base; + f_off = SMNAND_ENV_OFFSET; + is_nand = 1; + break; +#endif + case PISMO2_CS0: + case PISMO2_CS1: + base = PISMO2_BASE; + size = PISMO2_SIZE; + gpmc_config = gpmc_pismo2; + gpmc_config[0] |= mux | TYPE_NOR | mwidth; + break; +/* Either OneNand or Normal Nand at a time!! */ +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) + case PISMO1_ONENAND: + base = PISMO1_ONEN_BASE; + size = PISMO1_ONEN_SIZE; + gpmc_config = gpmc_onenand; + onenand_cs_base = gpmc_base; + f_off = ONENAND_ENV_OFFSET; + is_onenand = 1; + break; +#endif + default: + /* MPDB/Unsupported/Corrupt config- try Next GPMC CS!!!! */ + continue; + } + + /* handle boot CS0 */ + if (idx == 0) { + boot_flash_base = base; + boot_flash_off = f_off; + boot_flash_sec = f_sec; + boot_flash_type = config_sel[idx]; + boot_flash_env_addr = f_off; +#ifdef ENV_IS_VARIABLE + switch (config_sel[0]) { + case PISMO1_NOR: + boot_env_get_char_spec = + flash_env_get_char_spec; + boot_env_init = flash_env_init; + boot_saveenv = flash_saveenv; + boot_env_relocate_spec = + flash_env_relocate_spec; + flash_addr = env_ptr = + (env_t *) (boot_flash_base + + boot_flash_off); + env_name_spec = flash_env_name_spec; + boot_flash_env_addr = (u32) flash_addr; + break; +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + case PISMO1_NAND: + boot_env_get_char_spec = nand_env_get_char_spec; + boot_env_init = nand_env_init; + boot_saveenv = nand_saveenv; + boot_env_relocate_spec = nand_env_relocate_spec; + env_ptr = 0; /* This gets filled elsewhere!! */ + env_name_spec = nand_env_name_spec; + break; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) + case PISMO1_ONENAND: + boot_env_get_char_spec = + onenand_env_get_char_spec; + boot_env_init = onenand_env_init; + boot_saveenv = onenand_saveenv; + boot_env_relocate_spec = + onenand_env_relocate_spec; + env_ptr = + (env_t *) onenand_env; + env_name_spec = onenand_env_name_spec; + break; +#endif + default: + /* unknown variant!! */ + puts("Unknown Boot chip!!!\n"); + break; + } +#endif /* ENV_IS_VARIABLE */ + } + enable_gpmc_config(gpmc_config, gpmc_base, base, size); + } +#endif +} diff --git a/board/omap3430sdp/nand.c b/board/omap3430sdp/nand.c new file mode 100644 index 000000000..7ac6e2575 --- /dev/null +++ b/board/omap3430sdp/nand.c @@ -0,0 +1,551 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments, + * Rohit Choraria + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include + +#define GPMC_CHUNK_SHIFT 24 /* 16 MB */ +#define GPMC_SECTION_SHIFT 28 /* 128 MB */ + +#define CS_NUM_SHIFT 24 +#define ENABLE_PREFETCH 7 +#define DMA_MPU_MODE 2 + +#define ECC_P1_128_E(val) ((val) & 0x000000FF) /* Bits 0-7 */ +#define ECC_P512_2048_E(val) (((val) & 0x00000F00)>>8) /* Bits 8-11 */ +#define ECC_P1_128_O(val) (((val) & 0x00FF0000)>>16) /* Bits 16-23 */ +#define ECC_P512_2048_O(val) (((val) & 0x0F000000)>>24) /* Bits 24-27 */ + + +#define OMAP_NAND_GPMC_PREFETCH 1 + +unsigned char cs; +volatile unsigned long gpmc_cs_base_add; + +#ifdef OMAP_NAND_GPMC_PREFETCH +volatile unsigned long nand_fifo_add; +#endif + +/* + * omap_nand_hwcontrol - Set the address pointers corretly for the + * following address/data/command operation + * @mtd: MTD device structure + * @ctrl: Says whether Address or Command or Data is following. + */ + +static void omap_nand_hwcontrol(struct mtd_info *mtd, int ctrl) +{ + register struct nand_chip *this = mtd->priv; + + +/* + * Point the IO_ADDR to DATA and ADDRESS registers instead of chip address + */ + switch (ctrl) { + case NAND_CTL_SETCLE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + case NAND_CTL_SETALE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_ADR; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + case NAND_CTL_CLRCLE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + case NAND_CTL_CLRALE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + } +} + +/* + * omap_nand_wait - called primarily after a program/erase operation + * so that we access NAND again only after the device + * is ready again. + * @mtd: MTD device structure + * @chip: nand_chip structure + * @state: State from which wait function is being called i.e write/erase. + */ +static int omap_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state) +{ + register struct nand_chip *this = mtd->priv; + int status = 0; + + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + /* Send the status command and loop until the device is free */ + while(!(status & 0x40)){ + __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W); + status = __raw_readb(this->IO_ADDR_R); + } + return status; +} + +#ifdef OMAP_NAND_GPMC_PREFETCH +/* + * gpmc_cs_get_memconf - Get memory configs of device + * @cs: Chip selected + * @base: Base address pointer for device + * @size: Size of device + */ +static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) +{ + u32 l; + u32 mask; + + l = __raw_readl(gpmc_cs_base_add + GPMC_CONFIG7); + *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; + mask = (l >> 8) & 0x0f; + *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); +} + +/* + * gpmc_prefetch_init - configures default configuration for prefetch engine + */ +static void gpmc_prefetch_init(void) +{ + /* Setting the default threshold to 64 */ + __raw_writel(0x0, GPMC_BASE + GPMC_PREFETCH_CONTROL); + __raw_writel(0x40 << 8, GPMC_BASE + GPMC_PREFETCH_CONFIG1); + __raw_writel(0x0, GPMC_BASE + GPMC_PREFETCH_CONFIG2); +} + +/* + * gpmc_prefetch_start - configures and starts prefetch transfer + * @cs - nand cs (chip select) number + * @dma_mode: dma mode enable (1) or disable (0) + * @u32_count: number of bytes to be transferred + * @is_write: prefetch read(0) or write post(1) mode + */ +void gpmc_prefetch_start(int cs, unsigned int u32_count, int is_write) +{ + uint32_t prefetch_config1; + if (is_write) { + /* Set the amount of bytes to be prefetched */ + __raw_writel(u32_count, GPMC_BASE + GPMC_PREFETCH_CONFIG2); + + /* Set mpu mode, the post write and enable the engine + * Set which cs is using the post write + */ + prefetch_config1 = __raw_readl(GPMC_BASE + GPMC_PREFETCH_CONFIG1); + prefetch_config1 |= (((cs << CS_NUM_SHIFT) | + (1 << ENABLE_PREFETCH) | 0x1) & + ~(1 << DMA_MPU_MODE)); + __raw_writel(prefetch_config1, GPMC_BASE + GPMC_PREFETCH_CONFIG1); + } else { + /* Set the amount of bytes to be prefetched */ + __raw_writel(u32_count, GPMC_BASE + GPMC_PREFETCH_CONFIG2); + + /* Set dma/mpu mode, the prefech read and enable the engine + * Set which cs is using the prefetch + */ + prefetch_config1 = __raw_readl(GPMC_BASE + GPMC_PREFETCH_CONFIG1); + prefetch_config1 |= (((cs << CS_NUM_SHIFT) | + (1 << ENABLE_PREFETCH)) & + ~((1 << DMA_MPU_MODE) | 0x1)); + __raw_writel(prefetch_config1, GPMC_BASE + GPMC_PREFETCH_CONFIG1); + } + /* Start the prefetch engine */ + __raw_writel(0x1, GPMC_BASE + GPMC_PREFETCH_CONTROL); +} + +/* + * gpmc_prefetch_stop - disables and stops the prefetch engine + */ +void gpmc_prefetch_stop(void) +{ + uint32_t prefetch_config1; + /* stop the PFPW engine */ + __raw_writel(0x0, GPMC_BASE + GPMC_PREFETCH_CONTROL); + + /* Disable the PFPW engine */ + prefetch_config1 = __raw_readl(GPMC_BASE + GPMC_PREFETCH_CONFIG1); + prefetch_config1 &= ~((0x07 << CS_NUM_SHIFT) | + (1 << ENABLE_PREFETCH) | + (1 << DMA_MPU_MODE) | 0x1); + __raw_writel(prefetch_config1, GPMC_BASE + GPMC_PREFETCH_CONFIG1); +} + +/* + * gpmc_prefetch_status - reads prefetch status of engine + */ +int gpmc_prefetch_status(void) +{ + return __raw_readl(GPMC_BASE + GPMC_PREFETCH_STATUS); +} +#endif + +/* + * omap_nand_write_buf - write buffer to NAND controller + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + */ + +static void omap_nand_write_buf(struct mtd_info *mtd, const uint8_t * buf, + int len) +{ + uint8_t *p = (uint8_t *)buf; + uint32_t prefetch_status = 0; + int i, bytes_to_write = 0; + +#ifdef OMAP_NAND_GPMC_PREFETCH + /* configure and start prefetch transfer */ + gpmc_prefetch_start(cs, len, 0x1); + + prefetch_status = gpmc_prefetch_status(); + while (prefetch_status & 0x3FFF) { + bytes_to_write = (prefetch_status >> 24) & 0x7F; + for (i = 0; ((i < bytes_to_write) && (len)); i++, len--) + *(volatile uint8_t *)(nand_fifo_add) = *p++; + prefetch_status = gpmc_prefetch_status(); + } + /* disable and stop the PFPW engine */ + gpmc_prefetch_stop(); +#else + for (i = 0; i < len; i++) { + writeb(p[i], chip->IO_ADDR_W); + for(j=0;j<10;j++); + } +#endif +} + +/* + * omap_nand_read_buf - read data from NAND controller into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + */ + +static void omap_nand_read_buf(struct mtd_info *mtd, uint8_t * buf, int len) +{ + uint32_t prefetch_status = 0; + int i, bytes_to_read = 0; + +#ifdef OMAP_NAND_GPMC_PREFETCH + /* configure and start prefetch transfer */ + gpmc_prefetch_start(cs, len, 0x0); + + prefetch_status = gpmc_prefetch_status(); + while (len) { + bytes_to_read = (prefetch_status >> 24) & 0x7F; + for (i = 0; (i < bytes_to_read) && (len); i++, len--) + *buf++ = *(volatile uint8_t *)(nand_fifo_add); + prefetch_status = gpmc_prefetch_status(); + } + /* disable and stop the PFPW engine */ + gpmc_prefetch_stop(); +#else + for (i = 0; i < len; i++) { + buf[i] = readb(chip->IO_ADDR_R); + for(j=0;j<10;j++); + } +#endif +} + +/* + * omap_hwecc_init - Initialize HW ECC engine for NAND flash in GPMC controller + * @mtd: MTD device structure + * + */ +static void omap_hwecc_init(struct nand_chip *chip) +{ + unsigned long val = 0x0; + + /* Init ECC Control Register */ + /* Clear all ECC | Enable Reg1 */ + val = ((0x00000001<<8) | 0x00000001); + __raw_writel(val, GPMC_BASE + GPMC_ECC_CONTROL); + __raw_writel(0x3fcff000, GPMC_BASE + GPMC_ECC_SIZE_CONFIG); +} + +/* + * omap_correct_data - Compares ecc read from OOB with ECC registers values + * + * @mtd: MTD device structure + * @dat: page data + * @read_ecc: ecc read from nand flash + * @calc_ecc: ecc read from ECC registers + * + * Compares ecc read from OOB with ECC registers values + * and corrects one bit error if it has occured + */ +static int omap_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + return 0; +} + +/* + * omap_calculate_ecc - Generate non-inverted ECC bytes. + * + * @mtd: MTD structure + * @dat: unused + * @ecc_code: ecc_code buffer + * + * Using noninverted ECC can be considered ugly since writing a blank + * page ie. padding will clear the ECC bytes. This is no problem as + * long nobody is trying to write data on the seemingly unused page. + * Reading an erased page will produce an ECC mismatch between + * generated and read ECC bytes that has to be dealt with separately. + */ +static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) +{ + unsigned long val = 0x0; + unsigned long reg; + + /* Start Reading from HW ECC1_Result = 0x200 */ + reg = (unsigned long)(GPMC_BASE + GPMC_ECC1_RESULT); + val = __raw_readl(reg); + + *ecc_code++ = ECC_P1_128_E(val); + *ecc_code++ = ECC_P1_128_O(val); + *ecc_code++ = ECC_P512_2048_E(val) | ECC_P512_2048_O(val) << 4; + + return 0; +} + +/* + * omap_enable_ecc - This function enables the hardware ecc functionality + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +static void omap_enable_hwecc(struct mtd_info *mtd , int mode) +{ + struct nand_chip *chip = mtd->priv; + unsigned int val = __raw_readl(GPMC_BASE + GPMC_ECC_CONFIG); + unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; + + switch (mode) { + case NAND_ECC_READ: + __raw_writel(0x101, GPMC_BASE + GPMC_ECC_CONTROL); + /* ECC col width) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1) ; + break; + case NAND_ECC_READSYN: + __raw_writel(0x100, GPMC_BASE + GPMC_ECC_CONTROL); + /* ECC col width) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1) ; + break; + case NAND_ECC_WRITE: + __raw_writel(0x101, GPMC_BASE + GPMC_ECC_CONTROL); + /* ECC col width) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1) ; + break; + default: + printf("Error: Unrecognized Mode[%d]!\n", mode); + break; + } + + __raw_writel(val, GPMC_BASE + GPMC_ECC_CONFIG); +} + +static struct nand_oobinfo hw_nand_oob_64 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 12, + .eccpos = { + 1, 2, 3, 4, + 5, 6, 7, 8, + 9, 10, 11, 12 + }, + .oobfree = { {13, 51} } /* don't care */ +}; + +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks + * + * The memory based patterns just + */ +static uint8_t scan_ff_pattern[] = { 0xff }; +static struct nand_bbt_descr bb_descriptor_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 0, + .len = 1, + .pattern = scan_ff_pattern, +}; + +static struct nand_oobinfo sw_nand_oob_64 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 24, + .eccpos = { + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63 + }, + .oobfree = { {2, 38} } +}; + +void omap_nand_switch_ecc(struct mtd_info *mtd, int hardware) +{ + struct nand_chip *nand = mtd->priv; + + if (!hardware) { + nand->eccmode = NAND_ECC_SOFT; + nand->autooob = &sw_nand_oob_64; +#if (CFG_SW_ECC_512) + nand->eccsize = 512; +#else + nand->eccsize = 256; +#endif + nand->eccbytes = 3; + nand->eccsteps = mtd->oobblock / nand->eccsize; + nand->enable_hwecc = 0; + nand->calculate_ecc = nand_calculate_ecc; + nand->correct_data = nand_correct_data; + } else { + nand->eccmode = NAND_ECC_HW3_512; + nand->autooob = &hw_nand_oob_64; + nand->badblock_pattern = &bb_descriptor_flashbased; + nand->eccsize = 512; + nand->eccbytes = 3; + nand->eccsteps = 4; + nand->enable_hwecc = omap_enable_hwecc; + nand->correct_data = omap_correct_data; + nand->calculate_ecc = omap_calculate_ecc; + + omap_hwecc_init(nand); + } + + mtd->eccsize = nand->eccsize; + nand->oobdirty = 1; + + if (nand->options & NAND_BUSWIDTH_16) { + mtd->oobavail = mtd->oobsize - (nand->autooob->eccbytes + 2); + if (nand->autooob->eccbytes & 0x01) + mtd->oobavail--; + } else + mtd->oobavail = mtd->oobsize - (nand->autooob->eccbytes + 1); +} + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand_new.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + int gpmc_config=0; + u32 size; + cs = 0; + while (cs <= GPMC_MAX_CS) { + /* Each GPMC set for a single CS is at offset 0x30 */ + /* already remapped for us */ + gpmc_cs_base_add = (GPMC_CONFIG_CS0 + (cs*0x30)); + /* xloader/Uboot would have written the NAND type for us + * -NOTE This is a temporary measure and cannot handle ONENAND. + * The proper way of doing this is to pass the setup of u-boot up to kernel + * using kernel params - something on the lines of machineID + */ + /* Check if NAND type is set */ + if ((__raw_readl(gpmc_cs_base_add + GPMC_CONFIG1) & 0xC00)==0x800) { + /* Found it!! */ + break; + } + cs++; + } + if (cs > GPMC_MAX_CS) { + printk ("NAND: Unable to find NAND settings in GPMC Configuration - quitting\n"); + } + gpmc_config = __raw_readl(GPMC_CONFIG); + /* Disable Write protect */ + gpmc_config |= 0x10; + __raw_writel(gpmc_config, GPMC_CONFIG); + + nand->IO_ADDR_R = (void *)gpmc_cs_base_add + GPMC_NAND_DAT; + nand->IO_ADDR_W = (void *)gpmc_cs_base_add + GPMC_NAND_CMD; + + nand->hwcontrol = omap_nand_hwcontrol; + nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->read_buf = omap_nand_read_buf; + nand->write_buf = omap_nand_write_buf; +#if (CFG_HW_ECC_ROMCODE) + nand->eccmode = NAND_ECC_HW3_512; + nand->autooob = &hw_nand_oob_64; + nand->badblock_pattern = &bb_descriptor_flashbased; + nand->eccsize = 512; + nand->eccbytes = 3; + nand->eccsteps = 4; + nand->enable_hwecc = omap_enable_hwecc; + nand->correct_data = omap_correct_data; + nand->calculate_ecc = omap_calculate_ecc; + + omap_hwecc_init(nand); +#else + nand->eccmode = NAND_ECC_SOFT; +#if (CFG_SW_ECC_512) + nand->eccsize = 512; +#else + nand->eccsize = 256; +#endif +#endif +/* if RDY/BSY line is connected to OMAP then use the omap ready funcrtion + * and the generic nand_wait function which reads the status register after + * monitoring the RDY/BSY line. Otherwise use a standard chip delay which + * is slightly more than tR (AC Timing) of the NAND device and read the + * status register until you get a failure or success + */ +#ifdef OMAP_NAND_GPMC_PREFETCH + gpmc_cs_get_memconf(cs, (u32 *)&nand_fifo_add, &size); + gpmc_prefetch_init(); +#endif + +#if 0 + nand->dev_ready = omap_nand_dev_ready; +#else + nand->waitfunc = omap_nand_wait; + nand->chip_delay = 50; +#endif +} + + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ + diff --git a/board/omap3430sdp/omap3430sdp.c b/board/omap3430sdp/omap3430sdp.c new file mode 100644 index 000000000..0da1be473 --- /dev/null +++ b/board/omap3430sdp/omap3430sdp.c @@ -0,0 +1,1098 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +#endif + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP; /* board id for Linux */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */ + + return 0; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_1); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_2); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_3); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + + +/********************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world + * general use. + ***********************************************************/ + +void secureworld_exit(void) +{ + unsigned long i; + + /* configrue non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r" (i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); + /* allow allocation of locked TLBs and L2 lines in NS world */ + /* allow use of PLE registers in NS world also */ + __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r" (i)); + + /* + * Enable IBE in ACR register.ASA is disabled following + * recommendation from ARM + */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x40":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r" (i)); +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +int get_boot_type(void); +void v7_flush_dcache_all(int,int); +void l2cache_enable(void); +void setup_auxcr(int,int); + +void try_unlock_memory(void) +{ + int mode; + int in_sdram = running_in_sdram(); + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock_mem(); + } + /* If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ + +void s_init(void) +{ + int i; + int external_boot = 0; + int in_sdram = running_in_sdram(); + +#ifdef CONFIG_3430VIRTIO + in_sdram = 0; /* allow setup from memory for Virtio */ +#endif + watchdog_init(); + + external_boot = (get_boot_type() == 0x1F) ? 1 : 0; + /* Right now flushing at low MPU speed. Need to move after clock init */ + v7_flush_dcache_all(get_device_type(), external_boot); + + try_unlock_memory(); + +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5A80, CONTROL_SCALABLE_OMAP_OCP); +#endif + + if (cpu_is_3410()) { + /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ + __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); + } + +#ifndef CONFIG_ICACHE_OFF + icache_enable(); +#endif + +#ifdef CONFIG_L2_OFF + l2cache_disable(); +#else + l2cache_enable(); +#endif + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + setup_auxcr(get_device_type(), external_boot); + + prcm_init(); + + per_clocks_enable(); + + if (!in_sdram) + sdrc_init(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); +#endif + ether_init(); /* better done here so timers are init'ed */ + dieid_num_r(); + return (0); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01; + udelay(1000); + + h4reset_err_out: + return; +#endif +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + #define NOT_EARLY 0 + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; + + btype = get_board_type(); + mtype = get_mem_type(); +#ifndef CONFIG_3430ZEBU + /* fixme... dont know why this func is crashing in ZeBu */ + display_board_info(btype); +#endif + /* If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT_ES2()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_nCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_55 - FLASH_DIS*/\ + MUX_VAL(CP(GPMC_nCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) /*GPIO_56 - TORCH_EN*/\ + MUX_VAL(CP(GPMC_nCS6), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_57 - aGPS SLEEP*/\ + MUX_VAL(CP(GPMC_nCS7), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPMC_58 - WLAN_IRQ*/\ + MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_61 - BT_SHUTDOWN*/\ + MUX_VAL(CP(GPMC_nWP), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS ), (OFF_IN_PD | IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS ), (OFF_IN_PD | IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) /*GPIO_98 - CAM_RESET*/\ + MUX_VAL(CP(CAM_D0 ), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1 ), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D2 */\ + MUX_VAL(CP(CAM_D3 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D3 */\ + MUX_VAL(CP(CAM_D4 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D4 */\ + MUX_VAL(CP(CAM_D5 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D5 */\ + MUX_VAL(CP(CAM_D6 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D6 */\ + MUX_VAL(CP(CAM_D7 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D7 */\ + MUX_VAL(CP(CAM_D8 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D8 */\ + MUX_VAL(CP(CAM_D9 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D9 */\ + MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(McBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(McBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(McBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(McBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT0*/\ + MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT1*/\ + MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1)) /*MMC2_DIR_CMD */\ + MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ + /*Bluetooth*/\ + MUX_VAL(CP(McBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\ + MUX_VAL(CP(McBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McBSP3_DR*/\ + MUX_VAL(CP(McBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McBSP3_CLKX */\ + MUX_VAL(CP(McBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\ + MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(McBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1)) /*SSI1_DAT_RX */\ + MUX_VAL(CP(McBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX */\ + MUX_VAL(CP(McBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1)) /*SSI1_RDY_RX */\ + MUX_VAL(CP(McBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\ + MUX_VAL(CP(McBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McBSP1_CLKR */\ + MUX_VAL(CP(McBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4)) /*GPIO_157 - BT_WAKEUP*/\ + MUX_VAL(CP(McBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*McBSP1_DX*/\ + MUX_VAL(CP(McBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McBSP1_DR*/\ + MUX_VAL(CP(McBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0)) /*McBSP_CLKS */\ + MUX_VAL(CP(McBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\ + MUX_VAL(CP(McBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McBSP1_CLKX */\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX ), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_DATA0 */\ + MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_DATA1 */\ + MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_DATA2 */\ + MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_DATA3 */\ + MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_DATA4 */\ + MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_DATA5 */\ + MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_DATA6 */\ + MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB0_DATA7 */\ + MUX_VAL(CP(I2C1_SCL), (OFF_IN_PD | IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (OFF_IN_PD | IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (OFF_IN_PD | IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (OFF_IN_PD | IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (OFF_IN_PD | IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (OFF_IN_PD | IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0)) /*HDQ_SIO*/\ + MUX_VAL(CP(McSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(McSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(McSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(McSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(McSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ + MUX_VAL(CP(McSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) /*GPIO_176 - NOR_DPD*/\ + MUX_VAL(CP(McSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0)) /*McSPI1_CS3*/\ + MUX_VAL(CP(McSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\ + MUX_VAL(CP(McSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\ + MUX_VAL(CP(McSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\ + MUX_VAL(CP(McSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0)) /*McSPI2_CS0*/\ + MUX_VAL(CP(McSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0)) /*McSPI2_CS1*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_nIRQ), (OFF_IN_PD | IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4)) /*GPIO_2 - PEN_IRQ */\ + MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP */\ + MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4)) /*GPIO_5 - LCD_ENVDD*/\ + MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4)) /*GPIO_6 - LAN_INTR0*/\ + MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4)) /*GPIO_7 - MMC2_WP*/\ + MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) /*GPIO_8 - LCD_ENBKL*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1 */\ + MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ + MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ + MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0)) /*HSUSB1_TLL_STP*/\ + MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) /*HSUSB1_TLL_CLK*/\ + MUX_VAL(CP(ETK_D0_ES2 ), (OFF_IN_PD | IEN | PTD | DIS | M1)) /*HSUSB1_TLL_DATA0*/\ + MUX_VAL(CP(ETK_D1_ES2 ), (OFF_IN_PD | IEN | PTD | DIS | M1)) /*McSPI3_CS0*/\ + MUX_VAL(CP(ETK_D2_ES2 ), (OFF_IN_PD | IEN | PTD | EN | M1)) /*HSUSB1_TLL_DATA2*/\ + MUX_VAL(CP(ETK_D3_ES2 ), (OFF_IN_PD | IEN | PTD | DIS | M1)) /*HSUSB1_TLL_DATA7*/\ + MUX_VAL(CP(ETK_D4_ES2 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB1_TLL_DATA4*/\ + MUX_VAL(CP(ETK_D5_ES2 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB1_TLL_DATA5*/\ + MUX_VAL(CP(ETK_D6_ES2 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB1_TLL_DATA6*/\ + MUX_VAL(CP(ETK_D7_ES2 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB1_TLL_DATA3*/\ + MUX_VAL(CP(ETK_D8_ES2 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB1_TLL_DIR*/\ + MUX_VAL(CP(ETK_D9_ES2 ), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB1_TLL_NXT*/\ + MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB2_TLL_CLK*/\ + MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB2_TLL_STP*/\ + MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB2_TLL_DIR*/\ + MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB2_TLL_NXT*/\ + MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB2_TLL_DATA0*/\ + MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*HSUSB2_TLL_DATA1*/\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron ), (OFF_OUT_PD | IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (OFF_IN_PD | IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq ), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (OFF_IN_PD | IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (OFF_IN_PD | IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (OFF_IN_PD | IEN | PTU | EN | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (OFF_OUT_PD | IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/ +#define MUX_DEFAULT()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\ + MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\ + MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\ + MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\ + MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS ), (IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS ), (IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98*/\ + MUX_VAL(CP(CAM_D0 ), (IEN | PTD | DIS | M0)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1 ), (IEN | PTD | DIS | M0)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2 ), (IEN | PTD | DIS | M0)) /*CAM_D2 */\ + MUX_VAL(CP(CAM_D3 ), (IEN | PTD | DIS | M0)) /*CAM_D3 */\ + MUX_VAL(CP(CAM_D4 ), (IEN | PTD | DIS | M0)) /*CAM_D4 */\ + MUX_VAL(CP(CAM_D5 ), (IEN | PTD | DIS | M0)) /*CAM_D5 */\ + MUX_VAL(CP(CAM_D6 ), (IEN | PTD | DIS | M0)) /*CAM_D6 */\ + MUX_VAL(CP(CAM_D7 ), (IEN | PTD | DIS | M0)) /*CAM_D7 */\ + MUX_VAL(CP(CAM_D8 ), (IEN | PTD | DIS | M0)) /*CAM_D8 */\ + MUX_VAL(CP(CAM_D9 ), (IEN | PTD | DIS | M0)) /*CAM_D9 */\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT0*/\ + MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT1*/\ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_CMD */\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ + /*Bluetooth*/\ + MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\ + MUX_VAL(CP(McBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\ + MUX_VAL(CP(McBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX */\ + MUX_VAL(CP(McBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX */\ + MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX */\ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX */\ + MUX_VAL(CP(McBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\ + MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR */\ + MUX_VAL(CP(McBSP1_FSR), (IDIS | PTU | EN | M2)) /*CAM_GLOBAL_RESET*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\ + MUX_VAL(CP(McBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\ + MUX_VAL(CP(McBSP_CLKS), (IDIS | PTU | EN | M2)) /*CAM_SHUTTER */\ + MUX_VAL(CP(McBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\ + MUX_VAL(CP(McBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX */\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M0)) /*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0 */\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1 */\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2 */\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3 */\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4 */\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5 */\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6 */\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7 */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\ + MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(McSPI1_CS0), (IEN | PTU | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | DIS | M0)) /*McSPI1_CS1*/\ + MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M0)) /*McSPI1_CS2*/\ + MUX_VAL(CP(McSPI1_CS3), (IDIS | PTD | DIS | M0)) /*McSPI1_CS3*/\ + MUX_VAL(CP(McSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\ + MUX_VAL(CP(McSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO */\ + MUX_VAL(CP(McSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI */\ + MUX_VAL(CP(McSPI2_CS0), (IEN | PTU | EN | M0)) /*McSPI2_CS0*/\ + MUX_VAL(CP(McSPI2_CS1), (IDIS | PTD | DIS | M0)) /*McSPI2_CS1*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1 */\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ + MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\ + MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\ + MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\ + MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\ + MUX_VAL(CP(ETK_D3 ), (IEN | PTD | DIS | M2)) /*McSPI3_CLK*/\ + MUX_VAL(CP(ETK_D4 ), (IEN | PTD | DIS | M2)) /*McSPI3_SIMO */\ + MUX_VAL(CP(ETK_D5 ), (IEN | PTD | DIS | M2)) /*McSPI3_SOMI */\ + MUX_VAL(CP(ETK_D6 ), (IEN | PTD | DIS | M2)) /*McSPI3_CS0*/\ + MUX_VAL(CP(ETK_D7 ), (IEN | PTD | DIS | M2)) /*McSPI3_CS1*/\ + MUX_VAL(CP(ETK_D8 ), (IEN | PTD | DIS | M1)) /*SYS_DRM_MSECURE*/\ + MUX_VAL(CP(ETK_D9 ), (IEN | PTD | DIS | M1)) /*SYS_SECURE_IND */\ + MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\ + MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\ + MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\ + MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\ + MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\ + MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (IEN | PTD | DIS | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (IEN | PTD | DIS | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (IEN | PTD | DIS | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (IEN | PTD | DIS | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (IEN | PTD | DIS | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (IEN | PTD | DIS | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (IEN | PTD | DIS | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (IEN | PTD | DIS | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (IEN | PTD | DIS | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (IEN | PTD | DIS | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (IEN | PTD | DIS | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (IEN | PTD | DIS | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (IEN | PTD | DIS | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (IEN | PTD | DIS | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (IEN | PTD | DIS | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (IEN | PTD | DIS | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (IEN | PTD | DIS | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (IEN | PTD | DIS | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (IEN | PTD | DIS | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (IEN | PTD | DIS | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (IEN | PTD | DIS | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (IEN | PTD | DIS | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (IEN | PTD | DIS | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (IEN | PTD | DIS | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (IEN | PTD | DIS | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (IEN | PTD | DIS | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (IEN | PTD | DIS | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (IEN | PTD | DIS | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (IEN | PTD | DIS | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (IEN | PTD | DIS | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (IEN | PTD | DIS | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (IEN | PTD | DIS | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (IEN | PTD | DIS | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (IEN | PTD | DIS | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (IEN | PTD | DIS | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (IEN | PTD | DIS | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (IEN | PTD | DIS | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | DIS | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (IEN | PTD | DIS | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (IEN | PTD | DIS | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (IEN | PTD | DIS | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (IEN | PTD | DIS | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | DIS | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (IEN | PTD | DIS | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */ +//#endif + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + */ +void set_muxconf_regs(void) +{ + if (get_cpu_rev() >= CPU_3XX_ES20) { + MUX_DEFAULT_ES2(); + } else { + MUX_DEFAULT(); + } +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) +/********************************************************** + * Routine: nand+_init + * Description: Set up nand for nand and jffs2 commands + *********************************************************/ +void nand_init(void) +{ + extern flash_info_t flash_info[]; + + nand_probe(CFG_NAND_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +#ifdef CFG_JFFS2_MEM_NAND + flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; + /* only read kernel single meg partition */ + flash_info[CFG_JFFS2_FIRST_BANK].size = 1024 * 1024 * 2; + /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ + flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; + /* ?, ram for now, open question, copy to RAM or adapt for NAND */ + flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; +#endif +} +#endif + diff --git a/board/omap3430sdp/sys_info.c b/board/omap3430sdp/sys_info.c new file mode 100644 index 000000000..9449bb3d7 --- /dev/null +++ b/board/omap3430sdp/sys_info.c @@ -0,0 +1,414 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include +#include + +/**************************************************************************** + * check_fpga_revision number: the rev number should be a or b + ***************************************************************************/ +inline u16 check_fpga_rev(void) +{ + return __raw_readw(FPGA_REV_REGISTER); +} + +/**************************************************************************** + * check_uieeprom_avail: Check FPGA Availability + * OnBoard DEBUG FPGA registers need to be ready for us to proceed + * Required to retrieve the bootmode also. + ***************************************************************************/ +int check_uieeprom_avail(void) +{ + volatile unsigned short *ui_brd_name = + (volatile unsigned short *)EEPROM_UI_BRD + 8; + int count = 1000; + + /* Check if UI revision Name is already updated. + * if this is not done, we wait a bit to give a chance + * to update. This is nice to do as the Main board FPGA + * gets a chance to know off all it's components and we can continue + * to work normally + * Currently taking 269* udelay(1000) to update this on poweron from flash! + */ + while ((*ui_brd_name == 0x00) && count) { + udelay(200); + count--; + } + /* Timed out count will be 0? */ + return count; +} + +/************************************************************************** + * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch + * settings + * 1 is on + * 0 is off + * Will return Index of type of gpmc + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ + u8 cs; + + if (!check_fpga_rev()) { + /* we dont have an DEBUG FPGA??? */ + /* Depend on #defines!! default to strata boot return param */ + return 0x0; + } + /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */ + cs = (u8) (__raw_readw(DIP_SWITCH_INPUT_REG2) & 0xF); + + if(get_board_type() == SDP_3430_V2) + /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */ + cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | + ((cs & 2) << 1) | ((cs & 1) << 3); + else + /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */ + cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2); + return (cs); +} + +/**************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + ****************************************************/ +u32 get_cpu_type(void) +{ + // fixme, need to get register defines for 3430 + return (CPU_3430); +} + +/* + * cpu_is_3410(void) - returns true for 3410 + */ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3XX_ES20) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* + * Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == SDP_SDRC_MR_0_SDR) + return (1); + return (0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + ***********************************************************/ +u32 get_mem_type(void) +{ + /* Current SDP3430 uses 2x16 MDDR Infenion parts */ + return (DDR_DISCRETE); +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/* + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + */ +u32 get_board_type(void) +{ + if (get_cpu_rev() >= CPU_3XX_ES20) + return SDP_3430_V2; + else + return SDP_3430_V1; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return (0x0000003F & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return (WIDTH_16BIT); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +u32 get_board_rev(void) +{ + /* Currently reading EEPROM reg to get UI board version and try it out + */ +#if 0 + if (!check_uieeprom_avail()) { + /* timed out OR fpga rev not found!! */ + /* Assume 1.0 */ + return 0x01; + } + /* Move ahead to name location */ + ui_brd_name += 0x08; + count = sizeof(enhanced_ui_brd_name) - 2; + while ((enhanced_ui_brd_name[count] == ui_brd_name[count]) && count) { + count--; + } + /* Match?? */ + if (!count) { + /* Enhanced UI board.. SDP1.1 */ + return 0x11; + } +#endif + /* Legacy UI - hope they are all 1.0 boards.. */ + return (0x10); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char *bootmode[] = { + "NOR", + "ONND", + "NAND", + "P2a", + "NOR", + "NOR", + "P2a", + "P2b", + }; + u32 brev = get_board_rev(); + char cpu_3430s[] = "3430"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; +#ifdef CONFIG_LED_INFO + char led_string[CONFIG_LED_LEN] = { 0 }; +#endif + +#if defined(L3_165MHZ) + char p_l3[] = "165"; +#elif defined(L3_110MHZ) + char p_l3[] = "110"; +#elif defined(L3_133MHZ) + char p_l3[] = "133"; +#elif defined(L3_100MHZ) + char p_l3[] = "100" +#endif + +#if defined(PRCM_PCLK_OPP1) + char p_cpu[] = "1"; +#elif defined(PRCM_PCLK_OPP2) + char p_cpu[] = "2"; +#elif defined(PRCM_PCLK_OPP3) + char p_cpu[] = "3"; +#elif defined(PRCM_PCLK_OPP4) + char p_cpu[] = "4" +#endif + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + cpu_s = cpu_3430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev, + p_cpu, p_l3); + printf("TI 3430SDP %s Version + %s (Boot %s)\n", db_s, + mem_s, bootmode[get_gpmc0_type()]); +#ifdef CONFIG_LED_INFO + /* Format: 0123456789ABCDEF + * 3430C GP L3-100 NAND + */ + sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, p_l3, + bootmode[get_gpmc0_type()]); + /* reuse sec */ + for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) { + /* invert byte loc */ + u16 val = led_string[sec] << 8; + val |= led_string[sec + 1]; + __raw_writew(val, LED_REGISTER + sec); + } +#endif + +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * sdram. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 sys mem/perif + ***************************************************************/ +u32 get_boot_type(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return (mode >>= 8); +} diff --git a/board/omap3430sdp/syslib.c b/board/omap3430sdp/syslib.c new file mode 100644 index 000000000..2b16cc476 --- /dev/null +++ b/board/omap3430sdp/syslib.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} + diff --git a/board/omap3430sdp/u-boot.lds b/board/omap3430sdp/u-boot.lds new file mode 100644 index 000000000..6c811937f --- /dev/null +++ b/board/omap3430sdp/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3430zoom2/Makefile b/board/omap3430zoom2/Makefile new file mode 100644 index 000000000..1eb2931c1 --- /dev/null +++ b/board/omap3430zoom2/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2008 Texas Instruments. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := \ + board_rev.o \ + omap3430zoom2.o \ + sys_info.o + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap3430zoom2/board_rev.c b/board/omap3430zoom2/board_rev.c new file mode 100644 index 000000000..1811dcb8d --- /dev/null +++ b/board/omap3430zoom2/board_rev.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#include +#include +#include "board_rev.h" + +#if (defined(CONFIG_BOARD_REVISION) && (CONFIG_BOARD_REVISION)) + +static int board_revision = ZOOM2_BOARD_REVISION_UNKNOWN; + +static void zoom2_board_revision_detect (void) +{ + unsigned int val; + /* + * GPIO 94 to query for board revision + * production vs preproduction + * 94 is bank bank 3, index 30 + */ + gpio_t *gpio3_base = (gpio_t *) OMAP34XX_GPIO3_BASE; + + val = __raw_readl (&gpio3_base->datain); + + /* Check the bit for gpio 94 */ + if (!(val & (1 << 30))) + board_revision = ZOOM2_BOARD_REVISION_PRODUCTION_1; + else + board_revision = ZOOM2_BOARD_REVISION_BETA; +} + +int zoom2_board_revision (void) +{ + if (ZOOM2_BOARD_REVISION_UNKNOWN == board_revision) { + zoom2_board_revision_detect (); + } + return board_revision; +} + +#endif /* CONFIG_BOARD_REVISION */ diff --git a/board/omap3430zoom2/board_rev.h b/board/omap3430zoom2/board_rev.h new file mode 100644 index 000000000..b145036e0 --- /dev/null +++ b/board/omap3430zoom2/board_rev.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#ifndef _ZOOM2_BOARD_REV +#define _ZOOM2_BOARD_REV + +#define ZOOM2_BOARD_REVISION_UNKNOWN 0 +#define ZOOM2_BOARD_REVISION_ALPHA 1 +#define ZOOM2_BOARD_REVISION_BETA 2 +#define ZOOM2_BOARD_REVISION_PRODUCTION_1 3 + +#if (defined(CONFIG_BOARD_REVISION) && (CONFIG_BOARD_REVISION)) + +int zoom2_board_revision (void); + +#else + +#define zoom2_board_revision() ZOOM2_BOARD_REVISION_UNKNOWN + +#endif /* CONFIG_BOARD_REVISION */ + +#define ZOOM2_BOARD_REVISION_STRING() \ + ((ZOOM2_BOARD_REVISION_ALPHA == zoom2_board_revision()) ? "Alpha" : \ + (ZOOM2_BOARD_REVISION_BETA == zoom2_board_revision()) ? "Beta" : \ + (ZOOM2_BOARD_REVISION_PRODUCTION_1 == zoom2_board_revision()) ? "Production" : \ + "Unknown") + \ +#endif /* _ZOOM2_BOARD_REV */ diff --git a/board/omap3430zoom2/config.mk b/board/omap3430zoom2/config.mk new file mode 100644 index 000000000..03f071f24 --- /dev/null +++ b/board/omap3430zoom2/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2006 +# Texas Instruments, +# +# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP3430 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap3430zoom2/omap3430zoom2.c b/board/omap3430zoom2/omap3430zoom2.c new file mode 100644 index 000000000..19f9dec1e --- /dev/null +++ b/board/omap3430zoom2/omap3430zoom2.c @@ -0,0 +1,860 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_3430ZOOM2 +#include "../omap3430zoom2/board_rev.h" +#endif + +int get_boot_type(void); +void v7_flush_dcache_all(int, int); +void l2cache_enable(void); +void setup_auxcr(int, int); +void eth_init(void *); + + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ +#ifdef CONFIG_3430ZOOM2 + gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2; /* Linux mach id*/ +#ifdef CONFIG_BOARD_REVISION + gd->bd->bi_board_revision = zoom2_board_revision(); +#endif +#else + gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430LABRADOR; /* Linux mach id*/ +#endif + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */ + + return 0; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_1); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_2); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_3); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + + +/********************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world + * general use. + ***********************************************************/ +void secureworld_exit(void) +{ + unsigned long i; + + /* configrue non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r" (i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); + /* allow allocation of locked TLBs and L2 lines in NS world */ + /* allow use of PLE registers in NS world also */ + __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r" (i)); + + /* Enable ASA and IBE in ACR register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x50":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r" (i)); +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + int in_sdram = running_in_sdram(); + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock_mem(); + } + /* If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ +void s_init(void) +{ + int i; + int external_boot = 0; + int in_sdram = running_in_sdram(); + +#ifdef CONFIG_3430VIRTIO + in_sdram = 0; /* allow setup from memory for Virtio */ +#endif + watchdog_init(); + + external_boot = (get_boot_type() == 0x1F) ? 1 : 0; + /* Right now flushing at low MPU speed. Need to move after clock init */ + v7_flush_dcache_all(get_device_type(), external_boot); + + try_unlock_memory(); + +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5A80, CONTROL_SCALABLE_OMAP_OCP); +#endif + + if (cpu_is_3410()) { + /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ + __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); + } + +#ifndef CONFIG_ICACHE_OFF + icache_enable(); +#endif + +#ifdef CONFIG_L2_OFF + l2cache_disable(); +#else + l2cache_enable(); +#endif + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + setup_auxcr(get_device_type(), external_boot); + + prcm_init(); + + per_clocks_enable(); + + if (!in_sdram) + sdrc_init(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ +#ifdef CONFIG_3430ZOOM2 + { + /* GPIO LEDs + 154 blue , bank 5, index 26 + 173 red , bank 6, index 13 + 61 blue2, bank 2, index 29 + + GPIO to query for debug board + 158 db board query, bank 5, index 30 + This is an input only, no additional setup is needed */ + + gpio_t *gpio2_base = (gpio_t *)OMAP34XX_GPIO2_BASE; + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + + /* Configure GPIOs to output */ + sr32((u32)&gpio2_base->oe, 29, 1, 0); + sr32((u32)&gpio5_base->oe, 26, 1, 0); + sr32((u32)&gpio6_base->oe, 13, 1, 0); + + sr32((u32)&gpio6_base->cleardataout, 13, 1, 1); /* red off */ + sr32((u32)&gpio5_base->setdataout, 26, 1, 1); /* blue on */ + sr32((u32)&gpio2_base->setdataout, 29, 1, 1); /* blue 2 on */ + } +#endif +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + unsigned char data; + extern int twl4030_init_battery_charging(void); + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + +#ifdef CONFIG_3430ZOOM2 + /* + * Board Reset + * Enable resetting the board by pressing the large button + * on the top right side of the main board and holding for + * eight seconds. + * + * There are reported problems of some preproduction boards + * continously resetting. For those boards, disable resetting. + */ + if (ZOOM2_BOARD_REVISION_PRODUCTION_1 <= zoom2_board_revision()) + twl4030_power_reset_init(); +#endif + twl4030_usb_init(); + twl4030_init_battery_charging(); + /* see if we need to activate the power button startup */ + char *s = getenv("pbboot"); + if (s) { + /* figure out why we have booted */ + i2c_read(0x4b, 0x3a, 1, &data, 1); + + /* if status is non-zero, we didn't transition + * from WAIT_ON state + */ + if (data) { + printf("Transitioning to Wait State (%x)\n", data); + + /* clear status */ + data = 0; + i2c_write(0x4b, 0x3a, 1, &data, 1); + + /* put PM into WAIT_ON state */ + data = 0x01; + i2c_write(0x4b, 0x46, 1, &data, 1); + + /* no return - wait for power shutdown */ + while (1) {;} + } + printf("Transitioning to Active State (%x)\n", data); + + /* turn on long pwr button press reset*/ + data = 0x40; + i2c_write(0x4b, 0x46, 1, &data, 1); + printf("Power Button Active\n"); + } +#endif + twl4030_keypad_init(); + ether_init(); /* better done here so timers are init'ed */ + dieid_num_r(); + return (0); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01; + udelay(1000); + + h4reset_err_out: + return; + +#elif CONFIG_3430LABRADOR + DECLARE_GLOBAL_DATA_PTR; + eth_init(gd->bd); +#endif +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + #define NOT_EARLY 0 + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; + + btype = get_board_type(); + mtype = get_mem_type(); +#ifndef CONFIG_3430ZEBU + /* fixme... dont know why this func is crashing in ZeBu */ + display_board_info(btype); +#endif + /* If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT_ES2()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IEN | PTD | DIS | M4)) /*GPIO_54 lab*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTD | DIS | M4)) /*GPIO_55 lab*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M4)) /*GPIO_56 lab*/\ + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS ), (IDIS | PTD | DIS | M7)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS ), (IDIS | PTD | DIS | M7)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M4)) /*gpio_96 LCD*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 */\ + MUX_VAL(CP(CAM_D0 ), (IEN | PTD | DIS | M2)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1 ), (IEN | PTD | DIS | M2)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_101 */\ + MUX_VAL(CP(CAM_D3 ), (IEN | PTD | DIS | M4)) /*GPIO_102 */\ + MUX_VAL(CP(CAM_D4 ), (IEN | PTD | DIS | M4)) /*GPIO_103 */\ + MUX_VAL(CP(CAM_D5 ), (IEN | PTD | DIS | M4)) /*GPIO_104 */\ + MUX_VAL(CP(CAM_D6 ), (IEN | PTD | DIS | M4)) /*GPIO_105 */\ + MUX_VAL(CP(CAM_D7 ), (IEN | PTD | DIS | M4)) /*GPIO_106 */\ + MUX_VAL(CP(CAM_D8 ), (IEN | PTD | DIS | M4)) /*GPIO_107 */\ + MUX_VAL(CP(CAM_D9 ), (IEN | PTD | DIS | M4)) /*GPIO_108 */\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M7)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M4)) /*GPIO_126 - lab*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + /* sim lab */\ + MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*uP_spi lab */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M1)) /*mcspi3_ck lab*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M1)) /*mcspi3_simo lab*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M1)) /*mcspi3_somi lab*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*gpio_133 lab*/\ + MUX_VAL(CP(MMC2_DAT2), (IDIS | PTD | EN | M1)) /*mcspi3_cs1 lab*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M1)) /*mcspi3_cs0 lab*/\ + /* MMC3 lab */\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M3)) /*mmc3_dat0 lab*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M3)) /*mmc3_dat1 lab*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M3)) /*mmc3_dat2 lab*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M3)) /*mmc3_dat3 lab*/\ + /* pcm out */\ + MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\ + MUX_VAL(CP(McBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\ + MUX_VAL(CP(McBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/\ + MUX_VAL(CP(McBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\ + /* uart2 */\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + /*per irqs */\ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M4)) /*gpio_152 lab*/\ + MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M4)) /*gpio_153 lab*/\ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M4)) /*gpio_154 lab*/\ + MUX_VAL(CP(McBSP4_FSX), (IDIS | PTD | DIS | M4)) /*gpio_155 lab*/\ + /* per func*/\ + MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | EN | M2)) /*sim_cd lab*/\ + MUX_VAL(CP(McBSP1_FSR), (IEN | PTU | EN | M4)) /*gpio_157 lab*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTU | EN | M4)) /*gpio_158 lab*/\ + MUX_VAL(CP(McBSP1_DR), (IEN | PTU | EN | M4)) /*gpio_159 lab*/\ + MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | EN | M4)) /*unused lab*/\ + MUX_VAL(CP(McBSP1_FSX), (IEN | PTU | EN | M4)) /*gpio_161 lab*/\ + MUX_VAL(CP(McBSP1_CLKX), (IEN | PTU | EN | M4)) /*gpio_162 lab*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0 */\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1 */\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2 */\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3 */\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4 */\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5 */\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6 */\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7 */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\ + MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M3)) /*mmc3_cmd lab*/\ + MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M3)) /*mmc3_clk lab*/\ + MUX_VAL(CP(McSPI1_CS3), (IDIS | PTD | DIS | M3)) /*hsusb2_data2 lab*/\ + /*hsusb2 lab */\ + MUX_VAL(CP(McSPI2_CLK), (IDIS | PTD | DIS | M3)) /*hsusb2_d7 lab*/\ + MUX_VAL(CP(McSPI2_SIMO), (IDIS | PTD | DIS | M3)) /*hsusb2_d4 lab*/\ + MUX_VAL(CP(McSPI2_SOMI), (IDIS | PTD | DIS | M3)) /*hsusb2_d5 lab*/\ + MUX_VAL(CP(McSPI2_CS0), (IDIS | PTD | DIS | M3)) /*hsusb2_d6 lab*/\ + MUX_VAL(CP(McSPI2_CS1), (IDIS | PTD | DIS | M3)) /*hsusb2_d3 lab*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 - */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 - */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 - */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 - */\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8 - */\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ + /* clkout1 to t2-hfclkin, clkout2 to usb transeiver (both 26mhz) lab */\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | DIS | M0)) /*emu0/gpio11 lab*/\ + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M0)) /*emu1/gpio31 lab*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*USB1_STP lab*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*USB1_CLK lab*/\ + MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA0 lab*/\ + MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA1 lab*/\ + MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA2 lab*/\ + MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA7 lab*/\ + MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA4 lab*/\ + MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA5 lab*/\ + MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA6 lab*/\ + MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA3 lab*/\ + MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DIR lab*/\ + MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_NXT lab*/\ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M3)) /*USB2_CLK lab*/\ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M3)) /*USB2_STP lab*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB2_DIR lab*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB2_NXT lab*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA0 lab*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA1 lab*/\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (IEN | PTD | EN | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 unused*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT_ES2(); + + /* Set ZOOM2 specific mux */ +#ifdef CONFIG_3430ZOOM2 + /* IDCC modem Power On */ + MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /*gpio_110*/ + MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /*GPIO_103 */ + + /* GPMC CS7 has LAN9211 device */ + MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7 lab*/ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*gpio_158 lab: for LAN9221 on zoom2*/ + MUX_VAL(CP(McSPI1_CS2), (IEN | PTD | EN | M0)) /*mcspi1_cs2 zoom2*/ + + /* GPMC CS3 has Serial TL16CP754C device */ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3 lab*/ + /* Toggle Reset pin of TL16CP754C device */ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTU | EN | M4)) /*gpio_152 lab*/ + delay(10); + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | EN | M4)) /*gpio_152 lab*/ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTU | EN | M0)) /*sdrc_cke1 */ + + /* leds */ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | EN | M4)) /* gpio_173 red */ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | EN | M4)) /* gpio_154 blue */ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | EN | M4)) /* gpio_61 blue2 */ + /* Keep UART3 RX line pulled-up: + * Crashs have been seen on Zoom2 otherwise + */ + MUX_VAL(CP(UART3_RX_IRRX),(IEN | PTU | DIS | M0)) /*UART3_RX_IRRX*/ + + /* gpio 94 is used to detect preproduction vs production boards */ + MUX_VAL(CP(CAM_HS), (IEN | PTD | DIS | M4)) /*gpio_94 */ + +#endif +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} + diff --git a/board/omap3430zoom2/sys_info.c b/board/omap3430zoom2/sys_info.c new file mode 100644 index 000000000..148fa4e08 --- /dev/null +++ b/board/omap3430zoom2/sys_info.c @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include +#include + +#ifdef CONFIG_3430ZOOM2 +#include "../omap3430zoom2/board_rev.h" +#endif + +/************************************************************************ + * get_gpmc0_type() - read sysboot lines to see type of memory attached + ************************************************************************/ +u32 get_gpmc0_type(void) +{ + u32 type; + type = get_sysboot_value(); +// if ((type & (BIT3|BIT2)) == (BIT3|BIT2)) + return(TYPE_NAND); +} + +/**************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + ****************************************************/ +u32 get_cpu_type(void) +{ + return (CPU_3430); +} + +/* + * cpu_is_3410(void) - returns true for 3410 + */ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3XX_ES20) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* + * Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == SDP_SDRC_MR_0_SDR) + return (1); + return (0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + ***********************************************************/ +u32 get_mem_type(void) +{ + return (DDR_DISCRETE); /* LAB has single stacked x32 POP die */ +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/*********************************************************************** + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + ************************************************************************/ +u32 get_board_type(void) +{ + return BOARD_3430_LABRADOR; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return (0x0000003F & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return (WIDTH_16BIT); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +u32 get_board_rev(void) +{ + return (BOARD_3430_LABRADOR_V1); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char *bootmode[] = { + "NOR", + "ONND", + "NAND", + }; + u32 brev = get_board_rev(); + char cpu_3430s[] = "3430"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; + +#if defined(L3_165MHZ) + char p_l3[] = "165"; +#elif defined(L3_110MHZ) + char p_l3[] = "110"; +#elif defined(L3_133MHZ) + char p_l3[] = "133"; +#elif defined(L3_100MHZ) + char p_l3[] = "100" +#endif + +#if defined(PRCM_PCLK_OPP1) + char p_cpu[] = "1"; +#elif defined(PRCM_PCLK_OPP2) + char p_cpu[] = "2"; +#elif defined(PRCM_PCLK_OPP3) + char p_cpu[] = "3"; +#elif defined(PRCM_PCLK_OPP4) + char p_cpu[] = "4" +#endif + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + cpu_s = cpu_3430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev, p_cpu, + p_l3); + +#ifdef CONFIG_3430ZOOM2 + printf("OMAP3430Zoom2 Rev %s + %s (Boot %s)\n", + ZOOM2_BOARD_REVISION_STRING(), + mem_s, bootmode[2]); + +#else + printf("OMAP3430LAB %s Version + %s (Boot %s)\n", db_s, + mem_s, bootmode[2]); +#endif +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * sdram. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 sys mem/perif + ***************************************************************/ +u32 get_boot_type(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return (mode >>= 8); +} diff --git a/board/omap3430zoom2/u-boot.lds b/board/omap3430zoom2/u-boot.lds new file mode 100644 index 000000000..6c811937f --- /dev/null +++ b/board/omap3430zoom2/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3530overo/Makefile b/board/omap3530overo/Makefile new file mode 100644 index 000000000..4ddd8701d --- /dev/null +++ b/board/omap3530overo/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2008 Texas Instruments. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := \ + omap3530overo.o \ + sys_info.o + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap3530overo/config.mk b/board/omap3530overo/config.mk new file mode 100644 index 000000000..03f071f24 --- /dev/null +++ b/board/omap3530overo/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2006 +# Texas Instruments, +# +# SDP3430 board uses OMAP3430 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP3430 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap3530overo/omap3530overo.c b/board/omap3530overo/omap3530overo.c new file mode 100644 index 000000000..ccab5235e --- /dev/null +++ b/board/omap3530overo/omap3530overo.c @@ -0,0 +1,1087 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int get_boot_type(void); +void v7_flush_dcache_all(int, int); +void l2cache_enable(void); +void setup_auxcr(int, int); +void eth_init(void *); + + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned char *uart_thr; + uart_thr = (unsigned char *)0x49020000; + *uart_thr = 0x41; + *uart_thr = 0x42; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_3530OVERO; /* Linux mach id */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */ + + return 0; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_1); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_2); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_3); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + + +/********************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world + * general use. + ***********************************************************/ +void secureworld_exit(void) +{ + unsigned long i; + + /* configrue non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r" (i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); + /* allow allocation of locked TLBs and L2 lines in NS world */ + /* allow use of PLE registers in NS world also */ + __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r" (i)); + + /* Enable ASA and IBE in ACR register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x50":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r" (i)); +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + int in_sdram = running_in_sdram(); + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock_mem(); + } + /* If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ +void s_init(void) +{ + int i; + int external_boot = 0; + int in_sdram = running_in_sdram(); + +#ifdef CONFIG_3430VIRTIO + in_sdram = 0; /* allow setup from memory for Virtio */ +#endif + watchdog_init(); + + external_boot = (get_boot_type() == 0x1F) ? 1 : 0; + /* Right now flushing at low MPU speed. Need to move after clock init */ + v7_flush_dcache_all(get_device_type(), external_boot); + + try_unlock_memory(); + +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5A80, CONTROL_SCALABLE_OMAP_OCP); +#endif + + if (cpu_is_3410()) { + /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ + __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); + } + +#ifndef CONFIG_ICACHE_OFF + icache_enable(); +#endif + +#ifdef CONFIG_L2_OFF + l2cache_disable(); +#else + l2cache_enable(); +#endif + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + setup_auxcr(get_device_type(), external_boot); + + prcm_init(); + + per_clocks_enable(); + + if (!in_sdram) + sdrc_init(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + unsigned char data; + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + twl4030_usb_init(); + + /* see if we need to activate the power button startup */ + char *s = getenv("pbboot"); + if (s) { + /* figure out why we have booted */ + i2c_read(0x4b, 0x3a, 1, &data, 1); + + /* if status is non-zero, we didn't transition + * from WAIT_ON state + */ + if (data) { + printf("Transitioning to Wait State (%x)\n", data); + + /* clear status */ + data = 0; + i2c_write(0x4b, 0x3a, 1, &data, 1); + + /* put PM into WAIT_ON state */ + data = 0x01; + i2c_write(0x4b, 0x46, 1, &data, 1); + + /* no return - wait for power shutdown */ + while (1) {;} + } + printf("Transitioning to Active State (%x)\n", data); + + /* turn on long pwr button press reset*/ + data = 0x40; + i2c_write(0x4b, 0x46, 1, &data, 1); + printf("Power Button Active\n"); + } +#endif + dieid_num_r(); + return (0); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + #define NOT_EARLY 0 + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; + + btype = get_board_type(); + mtype = get_mem_type(); +#ifndef CONFIG_3430ZEBU + /* fixme... dont know why this func is crashing in ZeBu */ + display_board_info(btype); +#endif + /* If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + make_cs1_contiguous(); + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ + +#define MUX_DEFAULT_ES2()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IEN | PTD | DIS | M4)) /*GPIO_54 lab*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTD | DIS | M4)) /*GPIO_55 lab*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M4)) /*GPIO_56 lab*/\ + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS ), (IDIS | PTD | DIS | M7)) /*CAM_HS */ \ + MUX_VAL(CP(CAM_VS ), (IDIS | PTD | DIS | M7)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M4)) /*gpio_96 LCD*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 */\ + MUX_VAL(CP(CAM_D0 ), (IEN | PTD | DIS | M2)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1 ), (IEN | PTD | DIS | M2)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_101 */\ + MUX_VAL(CP(CAM_D3 ), (IEN | PTD | DIS | M4)) /*GPIO_102 */\ + MUX_VAL(CP(CAM_D4 ), (IEN | PTD | DIS | M4)) /*GPIO_103 */\ + MUX_VAL(CP(CAM_D5 ), (IEN | PTD | DIS | M4)) /*GPIO_104 */\ + MUX_VAL(CP(CAM_D6 ), (IEN | PTD | DIS | M4)) /*GPIO_105 */\ + MUX_VAL(CP(CAM_D7 ), (IEN | PTD | DIS | M4)) /*GPIO_106 */\ + MUX_VAL(CP(CAM_D8 ), (IEN | PTD | DIS | M4)) /*GPIO_107 */\ + MUX_VAL(CP(CAM_D9 ), (IEN | PTD | DIS | M4)) /*GPIO_108 */\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M7)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M4)) /*GPIO_126 - lab*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/ \ + MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/ \ + MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/ \ + MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/ \ + /* Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + /* sim lab */\ + MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | EN | M0)) /*MMC1_DAT4*/ \ + MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | EN | M0)) /*MMC1_DAT5*/ \ + MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | EN | M0)) /*MMC1_DAT6*/ \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/ \ + /*uP_spi lab */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M1)) /*mcspi3_ck lab*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M1)) /*mcspi3_simo lab*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M1)) /*mcspi3_somi lab*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*gpio_133 lab*/\ + MUX_VAL(CP(MMC2_DAT2), (IDIS | PTD | EN | M1)) /*mcspi3_cs1 lab*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M1)) /*mcspi3_cs0 lab*/\ + /* MMC3 lab */\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M7)) /*mmc3_dat0 lab*/ \ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M7)) /*mmc3_dat1 lab*/ \ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M7)) /*mmc3_dat2 lab*/ \ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M7)) /*mmc3_dat3 lab*/ \ + /* pcm out */\ + MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/ \ + MUX_VAL(CP(McBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/ \ + MUX_VAL(CP(McBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/ \ + MUX_VAL(CP(McBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/ \ + /* uart2 */\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + /*per irqs */\ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M4)) /*gpio_152 lab*/\ + MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M4)) /*gpio_153 lab*/\ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M4)) /*gpio_154 lab*/\ + MUX_VAL(CP(McBSP4_FSX), (IDIS | PTD | DIS | M4)) /*gpio_155 lab*/\ + /* per func*/\ + MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | EN | M2)) /*sim_cd lab*/\ + MUX_VAL(CP(McBSP1_FSR), (IEN | PTU | EN | M4)) /*gpio_157 lab*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTU | EN | M4)) /*gpio_158 lab*/\ + MUX_VAL(CP(McBSP1_DR), (IEN | PTU | EN | M4)) /*gpio_159 lab*/\ + MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | EN | M4)) /*unused lab*/\ + MUX_VAL(CP(McBSP1_FSX), (IEN | PTU | EN | M4)) /*gpio_161 lab*/\ + MUX_VAL(CP(McBSP1_CLKX), (IEN | PTU | EN | M4)) /*gpio_162 lab*/ \ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0 */\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1 */\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2 */\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3 */\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4 */\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5 */\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6 */\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7 */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\ + MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M3)) /*mmc3_cmd lab*/\ + MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M3)) /*mmc3_clk lab*/\ + MUX_VAL(CP(McSPI1_CS3), (IDIS | PTD | DIS | M3)) /*hsusb2_data2 lab*/\ + /*hsusb2 lab */\ + MUX_VAL(CP(McSPI2_CLK), (IDIS | PTD | DIS | M3)) /*hsusb2_d7 lab*/\ + MUX_VAL(CP(McSPI2_SIMO), (IDIS | PTD | DIS | M3)) /*hsusb2_d4 lab*/\ + MUX_VAL(CP(McSPI2_SOMI), (IDIS | PTD | DIS | M3)) /*hsusb2_d5 lab*/\ + MUX_VAL(CP(McSPI2_CS0), (IDIS | PTD | DIS | M3)) /*hsusb2_d6 lab*/\ + MUX_VAL(CP(McSPI2_CS1), (IDIS | PTD | DIS | M3)) /*hsusb2_d3 lab*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 - */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 - */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 - */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 - */\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8 - */\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ + /* clkout1 to t2-hfclkin, clkout2 to usb transeiver (both 26mhz) lab */\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | DIS | M0)) /*emu0/gpio11 lab*/\ + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M0)) /*emu1/gpio31 lab*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*USB1_STP lab*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*USB1_CLK lab*/\ + MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA0 lab*/\ + MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA1 lab*/\ + MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA2 lab*/\ + MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA7 lab*/\ + MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA4 lab*/\ + MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA5 lab*/\ + MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA6 lab*/\ + MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA3 lab*/\ + MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DIR lab*/\ + MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_NXT lab*/\ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M3)) /*USB2_CLK lab*/\ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M3)) /*USB2_STP lab*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB2_DIR lab*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB2_NXT lab*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA0 lab*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA1 lab*/\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (IEN | PTD | EN | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 unused*/ + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_OVERO() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\ + /* - MMC1_WP*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + /* - SMSC911X_NRES*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ + /* - PEN_DOWN*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTU | EN | M4)) /*GPIO_115*/\ + /*Audio Interface */\ + MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ + /*Bluetooth*/\ + MUX_VAL(CP(McBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ + MUX_VAL(CP(McBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ + MUX_VAL(CP(McBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ + MUX_VAL(CP(McBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ + MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\ + MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\ + MUX_VAL(CP(McBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\ + MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\ + MUX_VAL(CP(McBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\ + MUX_VAL(CP(McBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\ + MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ + MUX_VAL(CP(McBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\ + MUX_VAL(CP(McBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\ + /* BT_NRESET*/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ + /* - USBH_CPEN*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ + /* - USBH_RESET*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\ + MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ + MUX_VAL(CP(McSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\ + /* - LAN_INTR */\ + MUX_VAL(CP(McSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\ + MUX_VAL(CP(McSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\ + MUX_VAL(CP(McSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\ + MUX_VAL(CP(McSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\ + MUX_VAL(CP(McSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\ + MUX_VAL(CP(McSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\ + /* - W2W_NRESET*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (IEN | PTD | EN | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | EN | M0)) + + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ +// MUX_DEFAULT_ES2(); + MUX_OVERO(); +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} + diff --git a/board/omap3530overo/sys_info.c b/board/omap3530overo/sys_info.c new file mode 100644 index 000000000..560185a0c --- /dev/null +++ b/board/omap3530overo/sys_info.c @@ -0,0 +1,314 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include +#include + +/************************************************************************ + * get_gpmc0_type() - read sysboot lines to see type of memory attached + ************************************************************************/ +u32 get_gpmc0_type(void) +{ + u32 type; + type = get_sysboot_value(); +// if ((type & (BIT3|BIT2)) == (BIT3|BIT2)) + return(TYPE_NAND); +} + +/**************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + ****************************************************/ +u32 get_cpu_type(void) +{ + return (CPU_3430); +} + +/* + * cpu_is_3410(void) - returns true for 3410 + */ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3XX_ES20) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* + * Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == SDP_SDRC_MR_0_SDR) + return (1); + return (0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + ***********************************************************/ +u32 get_mem_type(void) +{ + return (DDR_STACKED); /* LAB has single stacked x32 POP die */ +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/*********************************************************************** + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + ************************************************************************/ +u32 get_board_type(void) +{ + return BOARD_3430_LABRADOR; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return (0x0000003F & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return (WIDTH_16BIT); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +u32 get_board_rev(void) +{ + return (BOARD_3430_LABRADOR_V1); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char *bootmode[] = { + "NOR", + "ONND", + "NAND", + }; + u32 brev = get_board_rev(); + char cpu_3430s[] = "3430"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; + +#if defined(L3_165MHZ) + char p_l3[] = "165"; +#elif defined(L3_110MHZ) + char p_l3[] = "110"; +#elif defined(L3_133MHZ) + char p_l3[] = "133"; +#elif defined(L3_100MHZ) + char p_l3[] = "100" +#endif + +#if defined(PRCM_PCLK_OPP1) + char p_cpu[] = "1"; +#elif defined(PRCM_PCLK_OPP2) + char p_cpu[] = "2"; +#elif defined(PRCM_PCLK_OPP3) + char p_cpu[] = "3"; +#elif defined(PRCM_PCLK_OPP4) + char p_cpu[] = "4" +#endif + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + cpu_s = cpu_3430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev, p_cpu, + p_l3); + + printf("OMAP3530 OVERO %s Version + %s (Boot %s)\n", db_s, + mem_s, bootmode[2]); +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * sdram. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 sys mem/perif + ***************************************************************/ +u32 get_boot_type(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return (mode >>= 8); +} diff --git a/board/omap3530overo/u-boot.lds b/board/omap3530overo/u-boot.lds new file mode 100644 index 000000000..6c811937f --- /dev/null +++ b/board/omap3530overo/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3630sdp/Makefile b/board/omap3630sdp/Makefile new file mode 100644 index 000000000..818e34ef9 --- /dev/null +++ b/board/omap3630sdp/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2009 Texas Instruments. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := \ + omap3630sdp.o \ + sys_info.o + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap3630sdp/config.mk b/board/omap3630sdp/config.mk new file mode 100644 index 000000000..7236e92a6 --- /dev/null +++ b/board/omap3630sdp/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2009 +# Texas Instruments, +# +# Zoom3 board uses OMAP3630 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP3430 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap3630sdp/omap3630sdp.c b/board/omap3630sdp/omap3630sdp.c new file mode 100755 index 000000000..9de053ece --- /dev/null +++ b/board/omap3630sdp/omap3630sdp.c @@ -0,0 +1,793 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*int get_boot_type(void); +void v7_flush_dcache_all(int, int); +void l2cache_enable(void); +void setup_auxcr(int, int); +void eth_init(bd_t *); +*/ + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* Linux mach id*/ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_3630SDP; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_1); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_2); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_3); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + + +/********************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world + * general use. + ***********************************************************/ +void secureworld_exit(void) +{ + unsigned long i; + + /* configrue non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2" : "=r" (i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00" : "=r"(i)); + /* allow allocation of locked TLBs and L2 lines in NS world */ + /* allow use of PLE registers in NS world also */ + __asm__ __volatile__("orr %0, %0, #0x70000" : "=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2" : "=r" (i)); + + /* Enable ASA and IBE in ACR register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x50" : "=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : "=r" (i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0" : "=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x31" : "=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0" : "=r" (i)); +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + int in_sdram = running_in_sdram(); + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) + secure_unlock_mem(); + + /* If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ +void s_init(void) +{ + int i; + int external_boot = 0; + int in_sdram = running_in_sdram(); + +#ifdef CONFIG_3430VIRTIO + in_sdram = 0; /* allow setup from memory for Virtio */ +#endif + watchdog_init(); + + external_boot = (get_boot_type() == 0x1F) ? 1 : 0; + /* Right now flushing at low MPU speed. Need to move after clock init */ + v7_flush_dcache_all(get_device_type(), external_boot); + + try_unlock_memory(); + +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5A80, CONTROL_SCALABLE_OMAP_OCP); +#endif + + if (cpu_is_3410()) { + /* Lock down 6-ways in L2 cache, + so that effective size of L2 is 64K */ + __asm__ __volatile__("mov %0, #0xFC" : "=r" (i)); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0" : "=r" (i)); + } + +#ifndef CONFIG_ICACHE_OFF + icache_enable(); +#endif + +#ifdef CONFIG_L2_OFF + l2cache_disable(); +#else + l2cache_enable(); +#endif + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + setup_auxcr(get_device_type(), external_boot); + + prcm_init(); + + per_clocks_enable(); + + if (!in_sdram) + sdrc_init(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + unsigned char data; + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + twl4030_usb_init(); + twl4030_power_reset_init(); + twl4030_init_battery_charging(); + /* see if we need to activate the power button startup */ + char *s = getenv("pbboot"); + if (s) { + /* figure out why we have booted */ + i2c_read(0x4b, 0x3a, 1, &data, 1); + + /* if status is non-zero, we didn't transition + * from WAIT_ON state + */ + if (data) { + printf("Transitioning to Wait State (%x)\n", data); + + /* clear status */ + data = 0; + i2c_write(0x4b, 0x3a, 1, &data, 1); + + /* put PM into WAIT_ON state */ + data = 0x01; + i2c_write(0x4b, 0x46, 1, &data, 1); + + /* no return - wait for power shutdown */ + while (1) + ; + } + printf("Transitioning to Active State (%x)\n", data); + + /* turn on long pwr button press reset*/ + data = 0x40; + i2c_write(0x4b, 0x46, 1, &data, 1); + printf("Power Button Active\n"); + } +#endif + + twl4030_keypad_init(); + ether_init(); /* better done here so timers are init'ed */ + dieid_num_r(); + return 0; +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01; + udelay(1000); + +h4reset_err_out: + return; + +#elif CONFIG_3430LABRADOR + DECLARE_GLOBAL_DATA_PTR; + eth_init(gd->bd); +#endif +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + #define NOT_EARLY 0 + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; + + btype = get_board_type(); + mtype = get_mem_type(); +#ifndef CONFIG_3430ZEBU + /* fixme... dont know why this func is crashing in ZeBu */ + display_board_info(btype); +#endif + /* If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +#define MUX_VAL(OFFSET, VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT_ES2()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IEN | PTD | DIS | M4)) /*GPIO_54 lab*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTD | DIS | M4)) /*GPIO_55 lab*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M4)) /*GPIO_56 lab*/\ + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1))/*sys_ndmareq1 lab*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1))/*GPMC_IO_DIR lab*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_VS), (IDIS | PTD | DIS | M7)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 */\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M2)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M2)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M4)) /*GPIO_101 */\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M4)) /*GPIO_102 */\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M4)) /*GPIO_103 */\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M4)) /*GPIO_104 */\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M7)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M4)) /*GPIO_126 - lab*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + /* sim lab */\ + MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*uP_spi lab */\ + MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + /* MMC3 lab */\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M3)) /*mmc3_dat0 lab*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M3)) /*mmc3_dat1 lab*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M3)) /*mmc3_dat2 lab*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M3)) /*mmc3_dat3 lab*/\ + /* pcm out */\ + MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\ + MUX_VAL(CP(McBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\ + MUX_VAL(CP(McBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/\ + MUX_VAL(CP(McBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\ + /* uart2 */\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + /*per irqs */\ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M4)) /*gpio_152 lab*/\ + MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M4)) /*gpio_153 lab*/\ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M4)) /*gpio_154 lab*/\ + MUX_VAL(CP(McBSP4_FSX), (IDIS | PTD | DIS | M4)) /*gpio_155 lab*/\ + /* per func*/\ + MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | EN | M2)) /*sim_cd lab*/\ + MUX_VAL(CP(McBSP1_FSR), (IEN | PTU | EN | M4)) /*gpio_157 lab*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTU | EN | M4)) /*gpio_158 lab*/\ + MUX_VAL(CP(McBSP1_DR), (IEN | PTU | EN | M4)) /*gpio_159 lab*/\ + MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | EN | M4)) /*unused lab*/\ + MUX_VAL(CP(McBSP1_FSX), (IEN | PTU | EN | M4)) /*gpio_161 lab*/\ + MUX_VAL(CP(McBSP1_CLKX), (IEN | PTU | EN | M4)) /*gpio_162 lab*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0))/*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0 */\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1 */\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2 */\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3 */\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4 */\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5 */\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6 */\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7 */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\ + MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M3)) /*mmc3_cmd lab*/\ + MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M3)) /*mmc3_clk lab*/\ + MUX_VAL(CP(McSPI1_CS3), (IDIS | PTD | DIS | M3))/*hsusb2_data2 lab*/\ + /*hsusb2 lab */\ + MUX_VAL(CP(McSPI2_CLK), (IDIS | PTD | DIS | M3)) /*hsusb2_d7 lab*/\ + MUX_VAL(CP(McSPI2_SIMO), (IDIS | PTD | DIS | M3)) /*hsusb2_d4 lab*/\ + MUX_VAL(CP(McSPI2_SOMI), (IDIS | PTD | DIS | M3)) /*hsusb2_d5 lab*/\ + MUX_VAL(CP(McSPI2_CS0), (IDIS | PTD | DIS | M3)) /*hsusb2_d6 lab*/\ + MUX_VAL(CP(McSPI2_CS1), (IDIS | PTD | DIS | M3)) /*hsusb2_d3 lab*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - */\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ + /* clkout1 to t2-hfclkin, clkout2 to usb transeiver (both 26mhz) lab */\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0))/*sys_clkout2 lab*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0))/*sys_clkout2 lab*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | DIS | M0))/*emu0/gpio11 lab*/\ + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M0))/*emu1/gpio31 lab*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*USB1_STP lab*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*USB1_CLK lab*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3)) /*USB1_DATA0 lab*/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3)) /*USB1_DATA1 lab*/\ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | DIS | M3)) /*USB1_DATA2 lab*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3)) /*USB1_DATA7 lab*/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3)) /*USB1_DATA4 lab*/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3)) /*USB1_DATA5 lab*/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3)) /*USB1_DATA6 lab*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3)) /*USB1_DATA3 lab*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M3)) /*USB1_DIR lab*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M3)) /*USB1_NXT lab*/\ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M3)) /*USB2_CLK lab*/\ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M3)) /*USB2_STP lab*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB2_DIR lab*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB2_NXT lab*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA0 lab*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA1 lab*/\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (IEN | PTD | EN | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7))/*sdrc_cke1 unused*/\ + MUX_VAL(CP(gpmc_a11), (IEN | PTD | EN | M4))/*gpmc_all unused*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT_ES2(); + + /* IDCC modem Power On */ + MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /*gpio_110*/ + MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /*GPIO_103 */ + + /* GPMC CS3 has LAN9211 device */ + MUX_VAL(CP(GPMC_nCS3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M4)) /*GPMC_58*/ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*gpio_158 for LAN*/ + + /* Keep UART3 RX line pulled-up: + * Crashs have been seen on Zoom2 otherwise + */ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | DIS | M0)) /*UART3_RX_IRRX*/ + + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M4)) /*gpio_96 LCD reset*/ + MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M4)) /*gpio_95 for TVOut*/ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M4)) /*gpio_97 for HDMI*/ +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} + diff --git a/board/omap3630sdp/sys_info.c b/board/omap3630sdp/sys_info.c new file mode 100644 index 000000000..7307de3b8 --- /dev/null +++ b/board/omap3630sdp/sys_info.c @@ -0,0 +1,383 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include +#include +/************************************************************************** + * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch + * settings + * 1 is on + * 0 is off + * Will return Index of type of gpmc + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ + u8 cs = 0x00; + + /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */ + cs = (u8) (__raw_readw(DIP_SWITCH_INPUT_REG2) & 0xF); + + if (get_board_type() == SDP_3430_V2) + /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */ + cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | + ((cs & 2) << 1) | ((cs & 1) << 3); + else + /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */ + cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2); + + return cs; +} + +/**************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + ****************************************************/ +u32 get_cpu_type(void) +{ + /* fixme, need to get register defines for 3430 */ + return CPU_3430; +} + +/* + * cpu_is_3410(void) - returns true for 3410 + */ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3XX_ES20) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* + * Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == SDP_SDRC_MR_0_SDR) + return 1; + return 0; +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + ***********************************************************/ +u32 get_mem_type(void) +{ + /* Current SDP3430 uses 2x16 MDDR Infenion parts */ + return DDR_DISCRETE; +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return size; +} + +/* + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + */ +u32 get_board_type(void) +{ + if (get_cpu_rev() >= CPU_3XX_ES20) + return SDP_3430_V2; + else + return SDP_3430_V1; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + u32 opt; + opt = 0x0000003F & __raw_readl(CONTROL_STATUS); + return opt; +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return b; +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return WIDTH_16BIT; +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +u32 get_board_rev(void) +{ + /* Currently reading EEPROM reg to get UI board version and try it out + */ +#if 0 + if (!check_uieeprom_avail()) { + /* timed out OR fpga rev not found!! */ + /* Assume 1.0 */ + return 0x01; + } + /* Move ahead to name location */ + ui_brd_name += 0x08; + count = sizeof(enhanced_ui_brd_name) - 2; + while ((enhanced_ui_brd_name[count] == ui_brd_name[count]) && count) + count--; + + /* Match?? */ + if (!count) { + /* Enhanced UI board.. SDP1.1 */ + return 0x11; + } +#endif + /* Legacy UI - hope they are all 1.0 boards.. */ + return 0x10; +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char *bootmode[] = { + "NOR", + "ONND", + "NAND", + "P2a", + "NOR", + "NOR", + "P2a", + "P2b", + }; + u32 brev = get_board_rev(); + char cpu_3430s[] = "3630"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; +#ifdef CONFIG_LED_INFO + char led_string[CONFIG_LED_LEN] = { 0 }; +#endif + +#if defined(L3_200MHZ) + char p_l3[] = "200"; +#elif defined(L3_165MHZ) + char p_l3[] = "165"; +#elif defined(L3_110MHZ) + char p_l3[] = "110"; +#elif defined(L3_133MHZ) + char p_l3[] = "133"; +#elif defined(L3_100MHZ) + char p_l3[] = "100"; +#endif + +#if defined(PRCM_PCLK_OPP1) + char p_cpu[] = "1"; +#elif defined(PRCM_PCLK_OPP2) + char p_cpu[] = "2"; +#elif defined(PRCM_PCLK_OPP3) + char p_cpu[] = "3"; +#elif defined(PRCM_PCLK_OPP4) + char p_cpu[] = "4"; +#endif + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + cpu_s = cpu_3430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev, + p_cpu, p_l3); + + printf("%s %s Version + %s (Boot %s)\n", CFG_PROMPT, db_s, + mem_s, bootmode[get_gpmc0_type()]); + +#ifdef CONFIG_LED_INFO + /* Format: 0123456789ABCDEF + * 3430C GP L3-100 NAND + */ + sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, p_l3, + bootmode[get_gpmc0_type()]); + /* reuse sec */ + for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) { + /* invert byte loc */ + u16 val = led_string[sec] << 8; + val |= led_string[sec + 1]; + __raw_writew(val, LED_REGISTER + sec); + } +#endif + +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n" : "=r"(val) :: "memory"); + val &= 0xF0000000; + val >>= 28; + return val; +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return 1; /* in flash */ + return 0; /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return 1; /* in SRAM */ + return 0; /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * sdram. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return 1; /* in sdram */ + return 0; /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 sys mem/perif + ***************************************************************/ +int get_boot_type(void) +{ + u32 v; + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + + return (int)v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + mode = mode >> 8; + + return mode; +} diff --git a/board/omap3630sdp/u-boot.lds b/board/omap3630sdp/u-boot.lds new file mode 100644 index 000000000..41064339e --- /dev/null +++ b/board/omap3630sdp/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3630zoom3/Makefile b/board/omap3630zoom3/Makefile new file mode 100644 index 000000000..9819f86b5 --- /dev/null +++ b/board/omap3630zoom3/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2009 Texas Instruments. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := \ + omap3630zoom3.o \ + mmc.o \ + sys_info.o + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap3630zoom3/config.mk b/board/omap3630zoom3/config.mk new file mode 100644 index 000000000..7236e92a6 --- /dev/null +++ b/board/omap3630zoom3/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2009 +# Texas Instruments, +# +# Zoom3 board uses OMAP3630 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP3430 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap3630zoom3/mmc.c b/board/omap3630zoom3/mmc.c new file mode 100644 index 000000000..349b860bc --- /dev/null +++ b/board/omap3630zoom3/mmc.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2004-2009 Texas Instruments, + * Kishore Kadiyala + * Moiz Sonasath + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include + +#if (CONFIG_FASTBOOT) +#include +#endif + +void board_mmc_init(void) +{ +#if (CONFIG_FASTBOOT) + + /* Partitons on EMMC preasent on OMAP4SDP required for Fastboot*/ + fastboot_ptentry ptn[10] = { + { + .name = "mbr", + .start = 0x00, /*Sector Start */ + .length = 0x200, /*512B */ + .flags = 0, + }, + { + .name = "xloader", + .start = 0x100, /*Sector Start */ + .length = 0x0060000, /*384KB */ + .flags = 0, + }, + { + .name = "bootloader", + .start = 0x400, /*Sector Start */ + .length = 0x0060000, /* 384KB */ + .flags = 0, + }, + { + .name = "environment", + .start = 0x700, /* Sector Start */ + .length = 0x0020000, /*128KB */ + .flags = FASTBOOT_PTENTRY_FLAGS_WRITE_ENV, + }, + { + .name = "kernel", + .start = 0x800, /* Sector Start */ + .length = 0x00680000, /*6.5MB */ + .flags = 0, + }, + { + .name = "misc", + .start = 0x3C00, /*Sector Start */ + .length = 0x200, /*512B */ + .flags = 0, + }, + { + .name = "system", + .start = 0x3EC1, /* Sector Start */ + .length = 0xC800000, /*200MB */ + .flags = 0, + }, + { + .name = "userdata", + .start = 0x69E5B, /* Sector Start */ + .length = 0x2000000, /*32MB */ + .flags = 0, + }, + { + .name = "cache", + .start = 0x7D820, /* Sector Start */ + .length = 0x2000000, /*32MB */ + .flags = 0, + }, + { + .name = "recovery", + .start = 0x911E5, /*Sector Start */ + .length = 0x12C00000, /*300MB */ + .flags = 0, + }, + + /* Rest of the RAW Partitions can start from Sector start 0x1271E5 */ + }; + int i; + for (i = 0; i < 10; i++) + fastboot_flash_add_ptn(&ptn[i]); +#endif +} diff --git a/board/omap3630zoom3/omap3630zoom3.c b/board/omap3630zoom3/omap3630zoom3.c new file mode 100644 index 000000000..caa4ba5b6 --- /dev/null +++ b/board/omap3630zoom3/omap3630zoom3.c @@ -0,0 +1,867 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int get_boot_type(void); +void v7_flush_dcache_all(int, int); +void l2cache_enable(void); +void setup_auxcr(int, int); +void eth_init(void *); + +#ifdef CONFIG_STORAGE_EMMC +#include + +extern uchar(*boot_env_get_char_spec) (int index); +extern int (*boot_env_init) (void); +extern int (*boot_saveenv) (void); +extern void (*boot_env_relocate_spec) (void); + +/* EMMC */ +extern uchar mmc_env_get_char_spec(int index); +extern int mmc_env_init(void); +extern int mmc_saveenv(void); +extern void mmc_env_relocate_spec(void); +extern char *mmc_env_name_spec; + +char *env_name_spec; +/* update these elsewhere */ +env_t *env_ptr; +#endif + + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_STORAGE_EMMC + /* Intializing env functional pointers with eMMC */ + boot_env_get_char_spec = mmc_env_get_char_spec; + boot_env_init = mmc_env_init; + boot_saveenv = mmc_saveenv; + boot_env_relocate_spec = mmc_env_relocate_spec; + env_ptr = (env_t *) (CFG_FLASH_BASE + CFG_ENV_OFFSET); + env_name_spec = mmc_env_name_spec; +#endif + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM3; /* Linux mach id*/ + + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */ + + return 0; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_1); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_2); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_3); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + + +/********************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world + * general use. + ***********************************************************/ +void secureworld_exit(void) +{ + unsigned long i; + + /* configrue non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r" (i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); + /* allow allocation of locked TLBs and L2 lines in NS world */ + /* allow use of PLE registers in NS world also */ + __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r" (i)); + + /* Enable ASA and IBE in ACR register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x50":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r" (i)); +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + int in_sdram = running_in_sdram(); + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock_mem(); + } + /* If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ +void s_init(void) +{ + int i; + int external_boot = 0; + int in_sdram = running_in_sdram(); + +#ifdef CONFIG_3430VIRTIO + in_sdram = 0; /* allow setup from memory for Virtio */ +#endif + watchdog_init(); + + external_boot = (get_boot_type() == 0x1F) ? 1 : 0; + /* Right now flushing at low MPU speed. Need to move after clock init */ + v7_flush_dcache_all(get_device_type(), external_boot); + + try_unlock_memory(); + +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5A80, CONTROL_SCALABLE_OMAP_OCP); +#endif + + if (cpu_is_3410()) { + /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ + __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); + } + +#ifndef CONFIG_ICACHE_OFF + icache_enable(); +#endif + +#ifdef CONFIG_L2_OFF + l2cache_disable(); +#else + l2cache_enable(); +#endif + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + setup_auxcr(get_device_type(), external_boot); + + prcm_init(); + + per_clocks_enable(); + + if (!in_sdram) + sdrc_init(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ +#ifdef CONFIG_3430ZOOM2 + { + /* GPIO LEDs + 154 blue , bank 5, index 26 + 173 red , bank 6, index 13 + 61 blue2, bank 2, index 29 + 94 green, bank 3, index 30 + + GPIO to query for debug board + 158 db board query, bank 5, index 30 + This is an input only, no additional setup is needed */ + + gpio_t *gpio2_base = (gpio_t *)OMAP34XX_GPIO2_BASE; + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; + + /* Configure GPIOs to output */ + sr32((u32)&gpio2_base->oe, 29, 1, 0); + sr32((u32)&gpio5_base->oe, 26, 1, 0); + sr32((u32)&gpio6_base->oe, 13, 1, 0); + sr32((u32)&gpio3_base->oe, 30, 1, 0); + + sr32((u32)&gpio6_base->cleardataout, 13, 1, 1); /* red off */ + sr32((u32)&gpio5_base->setdataout, 26, 1, 1); /* blue on */ + sr32((u32)&gpio2_base->setdataout, 29, 1, 1); /* blue 2 on */ + sr32((u32)&gpio3_base->cleardataout, 30, 1, 1); /* green off */ + } + +#endif +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + unsigned char data; + extern int twl4030_init_battery_charging(void); + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + twl4030_usb_init(); + twl4030_power_reset_init(); + twl4030_init_battery_charging(); + /* see if we need to activate the power button startup */ + char *s = getenv("pbboot"); + if (s) { + /* figure out why we have booted */ + i2c_read(0x4b, 0x3a, 1, &data, 1); + + /* if status is non-zero, we didn't transition + * from WAIT_ON state + */ + if (data) { + printf("Transitioning to Wait State (%x)\n", data); + + /* clear status */ + data = 0; + i2c_write(0x4b, 0x3a, 1, &data, 1); + + /* put PM into WAIT_ON state */ + data = 0x01; + i2c_write(0x4b, 0x46, 1, &data, 1); + + /* no return - wait for power shutdown */ + while (1) {;} + } + printf("Transitioning to Active State (%x)\n", data); + + /* turn on long pwr button press reset*/ + data = 0x40; + i2c_write(0x4b, 0x46, 1, &data, 1); + printf("Power Button Active\n"); + } +#endif + twl4030_keypad_init(); + ether_init(); /* better done here so timers are init'ed */ + dieid_num_r(); + return (0); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01; + udelay(1000); + + h4reset_err_out: + return; + +#elif CONFIG_3430LABRADOR + DECLARE_GLOBAL_DATA_PTR; + eth_init(gd->bd); +#endif +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + #define NOT_EARLY 0 + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; + + btype = get_board_type(); + mtype = get_mem_type(); +#ifndef CONFIG_3430ZEBU + /* fixme... dont know why this func is crashing in ZeBu */ + display_board_info(btype); +#endif + /* If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT_ES2()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IEN | PTD | DIS | M4)) /*GPIO_54 lab*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTD | DIS | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M4)) /*GPIO_56 lab*/\ + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_VS ), (IDIS | PTD | DIS | M7)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 */\ + MUX_VAL(CP(CAM_D0 ), (IEN | PTD | DIS | M2)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1 ), (IEN | PTD | DIS | M2)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_101 */\ + MUX_VAL(CP(CAM_D3 ), (IEN | PTD | DIS | M4)) /*GPIO_102 */\ + MUX_VAL(CP(CAM_D4 ), (IEN | PTD | DIS | M4)) /*GPIO_103 */\ + MUX_VAL(CP(CAM_D5 ), (IEN | PTD | DIS | M4)) /*GPIO_104 */\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M7)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M4)) /*GPIO_126 - lab*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + /* sim lab */\ + MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*uP_spi lab */\ + MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + /* MMC3 lab */\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M3)) /*mmc3_dat0 lab*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M3)) /*mmc3_dat1 lab*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M3)) /*mmc3_dat2 lab*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M3)) /*mmc3_dat3 lab*/\ + /* pcm out */\ + MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\ + MUX_VAL(CP(McBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\ + MUX_VAL(CP(McBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/\ + MUX_VAL(CP(McBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\ + /* uart2 */\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + /*per irqs */\ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M4)) /*gpio_152 lab*/\ + MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M4)) /*gpio_153 lab*/\ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M4)) /*gpio_154 lab*/\ + MUX_VAL(CP(McBSP4_FSX), (IDIS | PTD | DIS | M4)) /*gpio_155 lab*/\ + /* per func*/\ + MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | EN | M2)) /*sim_cd lab*/\ + MUX_VAL(CP(McBSP1_FSR), (IEN | PTU | EN | M4)) /*gpio_157 lab*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTU | EN | M4)) /*gpio_158 lab*/\ + MUX_VAL(CP(McBSP1_DR), (IEN | PTU | EN | M4)) /*gpio_159 lab*/\ + MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | EN | M4)) /*unused lab*/\ + MUX_VAL(CP(McBSP1_FSX), (IEN | PTU | EN | M4)) /*gpio_161 lab*/\ + MUX_VAL(CP(McBSP1_CLKX), (IEN | PTU | EN | M4)) /*gpio_162 lab*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0 */\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1 */\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2 */\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3 */\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4 */\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5 */\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6 */\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7 */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\ + MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M3)) /*mmc3_cmd lab*/\ + MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M3)) /*mmc3_clk lab*/\ + MUX_VAL(CP(McSPI1_CS3), (IDIS | PTD | DIS | M3)) /*hsusb2_data2 lab*/\ + /*hsusb2 lab */\ + MUX_VAL(CP(McSPI2_CLK), (IDIS | PTD | DIS | M3)) /*hsusb2_d7 lab*/\ + MUX_VAL(CP(McSPI2_SIMO), (IDIS | PTD | DIS | M3)) /*hsusb2_d4 lab*/\ + MUX_VAL(CP(McSPI2_SOMI), (IDIS | PTD | DIS | M3)) /*hsusb2_d5 lab*/\ + MUX_VAL(CP(McSPI2_CS0), (IDIS | PTD | DIS | M3)) /*hsusb2_d6 lab*/\ + MUX_VAL(CP(McSPI2_CS1), (IDIS | PTD | DIS | M3)) /*hsusb2_d3 lab*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - */\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ + /* clkout1 to t2-hfclkin, clkout2 to usb transeiver (both 26mhz) lab */\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | DIS | M0)) /*emu0/gpio11 lab*/\ + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M0)) /*emu1/gpio31 lab*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*USB1_STP lab*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*USB1_CLK lab*/\ + MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA0 lab*/\ + MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA1 lab*/\ + MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA2 lab*/\ + MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA7 lab*/\ + MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA4 lab*/\ + MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA5 lab*/\ + MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA6 lab*/\ + MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA3 lab*/\ + MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DIR lab*/\ + MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_NXT lab*/\ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M3)) /*USB2_CLK lab*/\ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M3)) /*USB2_STP lab*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB2_DIR lab*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB2_NXT lab*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA0 lab*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA1 lab*/\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (IEN | PTD | EN | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 unused*/\ + MUX_VAL(CP(gpmc_a11), (IEN | PTD | EN | M4))/*gpmc_all unused*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT_ES2(); + + /* Set ZOOM2 specific mux */ +#ifdef CONFIG_3430ZOOM2 + /* IDCC modem Power On */ + MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /*gpio_110*/ + MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /*GPIO_103 */ + + /* GPMC CS7 has LAN9211 device */ + MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7 lab*/ + MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*gpio_158 lab: for LAN9221 on zoom2*/ + MUX_VAL(CP(McSPI1_CS2), (IEN | PTD | EN | M0)) /*mcspi1_cs2 zoom2*/ + + /* GPMC CS3 has Serial TL16CP754C device */ + MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3 lab*/ + /* Toggle Reset pin of TL16CP754C device */ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTU | EN | M4)) /*gpio_152 lab*/ + delay (100); + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | EN | M4)) /*gpio_152 lab*/ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTU | EN | M0)) /*sdrc_cke1 */ + + /* leds */ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | EN | M4)) /* gpio_173 red */ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | EN | M4)) /* gpio_154 blue */ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | EN | M4)) /* gpio_61 blue2 */ + MUX_VAL(CP(CAM_HS), (IEN | PTD | EN | M4)) /* gpio_94 green */ + /* Keep UART3 RX line pulled-up: + * Crashs have been seen on Zoom2 otherwise + */ + MUX_VAL(CP(UART3_RX_IRRX),(IEN | PTU | DIS | M0)) /*UART3_RX_IRRX*/ + + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M4)) /*gpio_96 LCD reset*/ + MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M4)) /*gpio_95 for TVOut*/ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M4)) /*gpio_97 for HDMI*/ +#endif +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} + diff --git a/board/omap3630zoom3/sys_info.c b/board/omap3630zoom3/sys_info.c new file mode 100644 index 000000000..b9c66de9d --- /dev/null +++ b/board/omap3630zoom3/sys_info.c @@ -0,0 +1,386 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include +#include + +/************************************************************************** + * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch + * settings + * 1 is on + * 0 is off + * Will return Index of type of gpmc + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ + u8 cs; + + if(get_board_type() == SDP_3430_V2) + /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */ + cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | + ((cs & 2) << 1) | ((cs & 1) << 3); + else + /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */ + cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2); + return (cs); +} + +/**************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + ****************************************************/ +u32 get_cpu_type(void) +{ + // fixme, need to get register defines for 3430 + return (CPU_3430); +} + +/* + * cpu_is_3410(void) - returns true for 3410 + */ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3XX_ES20) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* + * Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == SDP_SDRC_MR_0_SDR) + return (1); + return (0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + ***********************************************************/ +u32 get_mem_type(void) +{ + /* Current SDP3430 uses 2x16 MDDR Infenion parts */ + return (DDR_DISCRETE); +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/* + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + */ +u32 get_board_type(void) +{ + if (get_cpu_rev() >= CPU_3XX_ES20) + return SDP_3430_V2; + else + return SDP_3430_V1; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return (0x0000003F & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return (WIDTH_16BIT); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +u32 get_board_rev(void) +{ + /* Currently reading EEPROM reg to get UI board version and try it out + */ +#if 0 + if (!check_uieeprom_avail()) { + /* timed out OR fpga rev not found!! */ + /* Assume 1.0 */ + return 0x01; + } + /* Move ahead to name location */ + ui_brd_name += 0x08; + count = sizeof(enhanced_ui_brd_name) - 2; + while ((enhanced_ui_brd_name[count] == ui_brd_name[count]) && count) { + count--; + } + /* Match?? */ + if (!count) { + /* Enhanced UI board.. SDP1.1 */ + return 0x11; + } +#endif + /* Legacy UI - hope they are all 1.0 boards.. */ + return (0x10); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + u32 boot_device = 0; + char boot_dev_name[8]; + + /* Read boot device from saved scratch pad */ + boot_device = __raw_readl(0x480029c0) & 0xff; + + switch(boot_device) { + case 0x03: + strcpy(boot_dev_name, "ONENAND"); + break; + case 0x02: + default: + strcpy(boot_dev_name, "NAND"); + break; + case 0x05: + strcpy(boot_dev_name, "EMMC"); + break; + case 0x06: + strcpy(boot_dev_name, "MMC/SD1"); + break; + }; + + u32 brev = get_board_rev(); + char cpu_3430s[] = "3630"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; +#ifdef CONFIG_LED_INFO + char led_string[CONFIG_LED_LEN] = { 0 }; +#endif + +#if defined(L3_200MHZ) + char p_l3[] = "200"; +#elif defined(L3_165MHZ) + char p_l3[] = "165"; +#elif defined(L3_110MHZ) + char p_l3[] = "110"; +#elif defined(L3_133MHZ) + char p_l3[] = "133"; +#elif defined(L3_100MHZ) + char p_l3[] = "100"; +#endif + +#if defined(PRCM_PCLK_OPP1) + char p_cpu[] = "1"; +#elif defined(PRCM_PCLK_OPP2) + char p_cpu[] = "2"; +#elif defined(PRCM_PCLK_OPP3) + char p_cpu[] = "3"; +#elif defined(PRCM_PCLK_OPP4) + char p_cpu[] = "4"; +#endif + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + cpu_s = cpu_3430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev, + p_cpu, p_l3); + printf("OMAP3630Zoom3 %s Version + %s (Boot from %s)\n", db_s, + mem_s, boot_dev_name); +#ifdef CONFIG_LED_INFO + /* Format: 0123456789ABCDEF + * 3430C GP L3-100 NAND + */ + sprintf(led_string, "%5s%3s%3s %s", cpu_s, sec_s, p_l3, + boot_dev_name); + /* reuse sec */ + for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) { + /* invert byte loc */ + u16 val = led_string[sec] << 8; + val |= led_string[sec + 1]; + __raw_writew(val, LED_REGISTER + sec); + } +#endif + +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * sdram. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 sys mem/perif + ***************************************************************/ +u32 get_boot_type(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return (mode >>= 8); +} diff --git a/board/omap3630zoom3/u-boot.lds b/board/omap3630zoom3/u-boot.lds new file mode 100644 index 000000000..6c811937f --- /dev/null +++ b/board/omap3630zoom3/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap3730overo/Makefile b/board/omap3730overo/Makefile new file mode 100644 index 000000000..0548fe763 --- /dev/null +++ b/board/omap3730overo/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2009 Texas Instruments. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := \ + omap3730overo.o \ + sys_info.o + +$(LIB): $(OBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omap3730overo/config.mk b/board/omap3730overo/config.mk new file mode 100644 index 000000000..12dd62d00 --- /dev/null +++ b/board/omap3730overo/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2009 +# Texas Instruments, +# +# 3530 OVERO board uses OMAP3530 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# SDP3430 has 1 bank of 32MB or 64MB mDDR-SDRAM on CS0 +# SDP3430 has 1 bank of 32MB or 00MB mDDR-SDRAM on CS1 +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap3730overo/omap3730overo.c b/board/omap3730overo/omap3730overo.c new file mode 100644 index 000000000..163db65ff --- /dev/null +++ b/board/omap3730overo/omap3730overo.c @@ -0,0 +1,733 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int get_boot_type(void); +void v7_flush_dcache_all(int, int); +void l2cache_enable(void); +void setup_auxcr(int, int); +void eth_init(void *); + + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_3530OVERO; /* Linux mach id */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */ + + return 0; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_1); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_2); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_3); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + + +/********************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world + * general use. + ***********************************************************/ +void secureworld_exit(void) +{ + unsigned long i; + + /* configrue non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r" (i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); + /* allow allocation of locked TLBs and L2 lines in NS world */ + /* allow use of PLE registers in NS world also */ + __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r" (i)); + + /* Enable ASA and IBE in ACR register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x50":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r" (i)); +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + int in_sdram = running_in_sdram(); + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock_mem(); + } + /* If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ +void s_init(void) +{ + int i; + int external_boot = 0; + int in_sdram = running_in_sdram(); + +#ifdef CONFIG_3430VIRTIO + in_sdram = 0; /* allow setup from memory for Virtio */ +#endif + watchdog_init(); + + external_boot = (get_boot_type() == 0x1F) ? 1 : 0; + /* Right now flushing at low MPU speed. Need to move after clock init */ + v7_flush_dcache_all(get_device_type(), external_boot); + + try_unlock_memory(); + +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5A80, CONTROL_SCALABLE_OMAP_OCP); +#endif + + if (cpu_is_3410()) { + /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ + __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); + } + +#ifndef CONFIG_ICACHE_OFF + icache_enable(); +#endif + +#ifdef CONFIG_L2_OFF + l2cache_disable(); +#else + l2cache_enable(); +#endif + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + setup_auxcr(get_device_type(), external_boot); + + prcm_init(); + + per_clocks_enable(); + + if (!in_sdram) + sdrc_init(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + unsigned char data; + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + twl4030_usb_init(); + + /* see if we need to activate the power button startup */ + char *s = getenv("pbboot"); + if (s) { + /* figure out why we have booted */ + i2c_read(0x4b, 0x3a, 1, &data, 1); + + /* if status is non-zero, we didn't transition + * from WAIT_ON state + */ + if (data) { + printf("Transitioning to Wait State (%x)\n", data); + + /* clear status */ + data = 0; + i2c_write(0x4b, 0x3a, 1, &data, 1); + + /* put PM into WAIT_ON state */ + data = 0x01; + i2c_write(0x4b, 0x46, 1, &data, 1); + + /* no return - wait for power shutdown */ + while (1) {;} + } + printf("Transitioning to Active State (%x)\n", data); + + /* turn on long pwr button press reset*/ + data = 0x40; + i2c_write(0x4b, 0x46, 1, &data, 1); + printf("Power Button Active\n"); + } +#endif + dieid_num_r(); + return (0); +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is + * either taken care of by ROM (HS/EMU) or not accessible (GP). + * We need to take care of WD2-MPU or take a PRCM reset. WD3 + * should not be running and does not generate a PRCM reset. + */ + + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */ + + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + #define NOT_EARLY 0 + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; + + btype = get_board_type(); + mtype = get_mem_type(); +#ifndef CONFIG_3430ZEBU + /* fixme... dont know why this func is crashing in ZeBu */ + display_board_info(btype); +#endif + /* If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT_ES2()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_nCS3), (IEN | PTD | DIS | M4)) /*GPIO_54 lab*/\ + MUX_VAL(CP(GPMC_nCS4), (IDIS | PTD | DIS | M4)) /*GPIO_55 lab*/\ + MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M4)) /*GPIO_56 lab*/\ + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*sys_ndmareq1 lab*/\ + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_IO_DIR lab*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1 lab*/\ + MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*gpmc_nWait lab*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS ), (IDIS | PTD | DIS | M7)) /*CAM_HS */ \ + MUX_VAL(CP(CAM_VS ), (IDIS | PTD | DIS | M7)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M4)) /*gpio_96 LCD*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 */\ + MUX_VAL(CP(CAM_D0 ), (IEN | PTD | DIS | M2)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1 ), (IEN | PTD | DIS | M2)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_101 */\ + MUX_VAL(CP(CAM_D3 ), (IEN | PTD | DIS | M4)) /*GPIO_102 */\ + MUX_VAL(CP(CAM_D4 ), (IEN | PTD | DIS | M4)) /*GPIO_103 */\ + MUX_VAL(CP(CAM_D5 ), (IEN | PTD | DIS | M4)) /*GPIO_104 */\ + MUX_VAL(CP(CAM_D6 ), (IEN | PTD | DIS | M4)) /*GPIO_105 */\ + MUX_VAL(CP(CAM_D7 ), (IEN | PTD | DIS | M4)) /*GPIO_106 */\ + MUX_VAL(CP(CAM_D8 ), (IEN | PTD | DIS | M4)) /*GPIO_107 */\ + MUX_VAL(CP(CAM_D9 ), (IEN | PTD | DIS | M4)) /*GPIO_108 */\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M7)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | DIS | M4)) /*GPIO_126 - lab*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\ + /*Audio Interface */\ + MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/ \ + MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/ \ + MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/ \ + MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/ \ + /* Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTD | DIS | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + /* sim lab */\ + MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | EN | M0)) /*MMC1_DAT4*/ \ + MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | EN | M0)) /*MMC1_DAT5*/ \ + MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | EN | M0)) /*MMC1_DAT6*/ \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/ \ + /*uP_spi lab */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M1)) /*mcspi3_ck lab*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M1)) /*mcspi3_simo lab*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M1)) /*mcspi3_somi lab*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*gpio_133 lab*/\ + MUX_VAL(CP(MMC2_DAT2), (IDIS | PTD | EN | M1)) /*mcspi3_cs1 lab*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | EN | M1)) /*mcspi3_cs0 lab*/\ + /* MMC3 lab */\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M7)) /*mmc3_dat0 lab*/ \ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M7)) /*mmc3_dat1 lab*/ \ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M7)) /*mmc3_dat2 lab*/ \ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M7)) /*mmc3_dat3 lab*/ \ + /* pcm out */\ + MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/ \ + MUX_VAL(CP(McBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/ \ + MUX_VAL(CP(McBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/ \ + MUX_VAL(CP(McBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/ \ + /* uart2 */\ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + /*per irqs */\ + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M4)) /*gpio_152 lab*/\ + MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M4)) /*gpio_153 lab*/\ + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M4)) /*gpio_154 lab*/\ + MUX_VAL(CP(McBSP4_FSX), (IDIS | PTD | DIS | M4)) /*gpio_155 lab*/\ + /* per func*/\ + MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | EN | M2)) /*sim_cd lab*/\ + MUX_VAL(CP(McBSP1_FSR), (IEN | PTU | EN | M4)) /*gpio_157 lab*/\ + MUX_VAL(CP(McBSP1_DX), (IEN | PTU | EN | M4)) /*gpio_158 lab*/\ + MUX_VAL(CP(McBSP1_DR), (IEN | PTU | EN | M4)) /*gpio_159 lab*/\ + MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | EN | M4)) /*unused lab*/\ + MUX_VAL(CP(McBSP1_FSX), (IEN | PTU | EN | M4)) /*gpio_161 lab*/\ + MUX_VAL(CP(McBSP1_CLKX), (IEN | PTU | EN | M4)) /*gpio_162 lab*/ \ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\ + MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0 */\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1 */\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2 */\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3 */\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4 */\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5 */\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6 */\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7 */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) /*HDQ_SIO*/\ + MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M3)) /*mmc3_cmd lab*/\ + MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M3)) /*mmc3_clk lab*/\ + MUX_VAL(CP(McSPI1_CS3), (IDIS | PTD | DIS | M3)) /*hsusb2_data2 lab*/\ + /*hsusb2 lab */\ + MUX_VAL(CP(McSPI2_CLK), (IDIS | PTD | DIS | M3)) /*hsusb2_d7 lab*/\ + MUX_VAL(CP(McSPI2_SIMO), (IDIS | PTD | DIS | M3)) /*hsusb2_d4 lab*/\ + MUX_VAL(CP(McSPI2_SOMI), (IDIS | PTD | DIS | M3)) /*hsusb2_d5 lab*/\ + MUX_VAL(CP(McSPI2_CS0), (IDIS | PTD | DIS | M3)) /*hsusb2_d6 lab*/\ + MUX_VAL(CP(McSPI2_CS1), (IDIS | PTD | DIS | M3)) /*hsusb2_d3 lab*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 - */\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - */\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 - */\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 - */\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 - */\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8 - */\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\ + /* clkout1 to t2-hfclkin, clkout2 to usb transeiver (both 26mhz) lab */\ + MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M0)) /*sys_clkout2 lab*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ + MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | DIS | M0)) /*emu0/gpio11 lab*/\ + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M0)) /*emu1/gpio31 lab*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*USB1_STP lab*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*USB1_CLK lab*/\ + MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA0 lab*/\ + MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA1 lab*/\ + MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA2 lab*/\ + MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA7 lab*/\ + MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA4 lab*/\ + MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA5 lab*/\ + MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA6 lab*/\ + MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DATA3 lab*/\ + MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_DIR lab*/\ + MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M3)) /*USB1_NXT lab*/\ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M3)) /*USB2_CLK lab*/\ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M3)) /*USB2_STP lab*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB2_DIR lab*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB2_NXT lab*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA0 lab*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB2_DATA1 lab*/\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (IEN | PTD | EN | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 unused*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT_ES2(); +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} + diff --git a/board/omap3730overo/sys_info.c b/board/omap3730overo/sys_info.c new file mode 100644 index 000000000..6c3673f00 --- /dev/null +++ b/board/omap3730overo/sys_info.c @@ -0,0 +1,377 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include +#include + +/************************************************************************** + * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch + * settings + * 1 is on + * 0 is off + * Will return Index of type of gpmc + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ + u8 cs; + + if(get_board_type() == SDP_3430_V2) + /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */ + cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | + ((cs & 2) << 1) | ((cs & 1) << 3); + else + /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */ + cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2); + return (cs); +} + +/**************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + ****************************************************/ +u32 get_cpu_type(void) +{ + // fixme, need to get register defines for 3430 + return (CPU_3430); +} + +/* + * cpu_is_3410(void) - returns true for 3410 + */ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3XX_ES20) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* + * Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == SDP_SDRC_MR_0_SDR) + return (1); + return (0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + ***********************************************************/ +u32 get_mem_type(void) +{ + /* Current SDP3430 uses 2x16 MDDR Infenion parts */ + return (DDR_DISCRETE); +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/* + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + */ +u32 get_board_type(void) +{ + if (get_cpu_rev() >= CPU_3XX_ES20) + return SDP_3430_V2; + else + return SDP_3430_V1; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return (0x0000003F & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return (WIDTH_16BIT); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +u32 get_board_rev(void) +{ + /* Currently reading EEPROM reg to get UI board version and try it out + */ +#if 0 + if (!check_uieeprom_avail()) { + /* timed out OR fpga rev not found!! */ + /* Assume 1.0 */ + return 0x01; + } + /* Move ahead to name location */ + ui_brd_name += 0x08; + count = sizeof(enhanced_ui_brd_name) - 2; + while ((enhanced_ui_brd_name[count] == ui_brd_name[count]) && count) { + count--; + } + /* Match?? */ + if (!count) { + /* Enhanced UI board.. SDP1.1 */ + return 0x11; + } +#endif + /* Legacy UI - hope they are all 1.0 boards.. */ + return (0x10); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + enum { + BOOTMODE_NOR, + BOOTMODE_ONND, + BOOTMODE_NAND, + BOOTMODE_MMC + }; + + char *bootmode[] = { + "NOR", + "ONND", + "NAND", + "MMC" + }; + u32 brev = get_board_rev(); + char cpu_3430s[] = "3730"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; +#ifdef CONFIG_LED_INFO + char led_string[CONFIG_LED_LEN] = { 0 }; +#endif + +#if defined(L3_200MHZ) + char p_l3[] = "200"; +#elif defined(L3_165MHZ) + char p_l3[] = "165"; +#elif defined(L3_110MHZ) + char p_l3[] = "110"; +#elif defined(L3_133MHZ) + char p_l3[] = "133"; +#elif defined(L3_100MHZ) + char p_l3[] = "100"; +#endif + +#if defined(PRCM_PCLK_OPP1) + char p_cpu[] = "1"; +#elif defined(PRCM_PCLK_OPP2) + char p_cpu[] = "2"; +#elif defined(PRCM_PCLK_OPP3) + char p_cpu[] = "3"; +#elif defined(PRCM_PCLK_OPP4) + char p_cpu[] = "4"; +#endif + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + cpu_s = cpu_3430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev, + p_cpu, p_l3); + printf("OMAP3730 Overo %s Version + %s (Boot %s)\n", db_s, + mem_s, bootmode[BOOTMODE_MMC]); +#ifdef CONFIG_LED_INFO + /* Format: 0123456789ABCDEF + * 3430C GP L3-100 NAND + */ + sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, p_l3, + bootmode[2]); + /* reuse sec */ + for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) { + /* invert byte loc */ + u16 val = led_string[sec] << 8; + val |= led_string[sec + 1]; + __raw_writew(val, LED_REGISTER + sec); + } +#endif + +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * sdram. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 sys mem/perif + ***************************************************************/ +u32 get_boot_type(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return (mode >>= 8); +} diff --git a/board/omap3730overo/u-boot.lds b/board/omap3730overo/u-boot.lds new file mode 100644 index 000000000..6c811937f --- /dev/null +++ b/board/omap3730overo/u-boot.lds @@ -0,0 +1,58 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/omap5912osk/Makefile b/board/omap5912osk/Makefile index e9bb0ecd7..4b564217b 100644 --- a/board/omap5912osk/Makefile +++ b/board/omap5912osk/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := omap5912osk.o +OBJS := omap5912osk.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/omap5912osk/lowlevel_init.S b/board/omap5912osk/lowlevel_init.S index 7bfdb2632..a1fa097d9 100644 --- a/board/omap5912osk/lowlevel_init.S +++ b/board/omap5912osk/lowlevel_init.S @@ -125,7 +125,7 @@ lock_end: /*------------------------------------------------------* * Turn off the watchdog during init... * - *------------------------------------------------------*/ + *------------------------------------------------------*/ ldr r0, REG_WATCHDOG ldr r1, WATCHDOG_VAL1 str r1, [r0] @@ -191,7 +191,7 @@ skip_TMP_Patch: mov r0, #0x1800 /* value should be checked */ 3: subs r0, r0, #0x1 /* Decrement count */ - bne 3b + bne 3b /* * Set SDRAM control values. Disable refresh before MRS command. @@ -294,7 +294,7 @@ common_tc: #ifdef CONFIG_H2_OMAP1610 /* inserting additional 2 clock cycle hold time for LAN */ ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED + ldr r1, VAL_TC_EMIFS_CS1_ADVANCED str r1, [r0] #endif /* Start MPU Timer 1 */ diff --git a/board/omap5912osk/u-boot.lds b/board/omap5912osk/u-boot.lds index 9a34e46ee..142450cdd 100644 --- a/board/omap5912osk/u-boot.lds +++ b/board/omap5912osk/u-boot.lds @@ -47,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/omap730p2/Makefile b/board/omap730p2/Makefile index 0d7ae6145..29467ac39 100644 --- a/board/omap730p2/Makefile +++ b/board/omap730p2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := omap730p2.o flash.o +OBJS := omap730p2.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/omap730p2/lowlevel_init.S b/board/omap730p2/lowlevel_init.S index d4e97a5aa..9ab71cf55 100644 --- a/board/omap730p2/lowlevel_init.S +++ b/board/omap730p2/lowlevel_init.S @@ -65,7 +65,7 @@ lowlevel_init: str r1, [r0] /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * + * Set up ARM CLM registers (IDLECT2) * *------------------------------------------------------*/ ldr r0, REG_ARM_IDLECT2 ldr r1, VAL_ARM_IDLECT2 @@ -123,7 +123,7 @@ lock_end: /*------------------------------------------------------* * Turn off the watchdog during init... * - *------------------------------------------------------*/ + *------------------------------------------------------*/ ldr r0, REG_WATCHDOG ldr r1, WATCHDOG_VAL1 str r1, [r0] @@ -158,7 +158,7 @@ watch2Wait: /* Compare. */ cmp r0, #0 /* Skip over EMIF-fast initialization if running from SDRAM. */ - bne skip_sdram + bne skip_sdram /* * Delay for SDRAM initialization. @@ -166,7 +166,7 @@ watch2Wait: mov r3, #0x1800 /* value should be checked */ 3: subs r3, r3, #0x1 /* Decrement count */ - bne 3b + bne 3b ldr r0, REG_SDRAM_CONFIG ldr r1, SDRAM_CONFIG_VAL @@ -239,7 +239,7 @@ common_tc: #ifdef CONFIG_P2_OMAP1610 /* inserting additional 2 clock cycle hold time for LAN */ ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED + ldr r1, VAL_TC_EMIFS_CS1_ADVANCED str r1, [r0] #endif /* Start MPU Timer 1 */ diff --git a/board/omap730p2/u-boot.lds b/board/omap730p2/u-boot.lds index a4fcd1a9b..710b2a2d6 100644 --- a/board/omap730p2/u-boot.lds +++ b/board/omap730p2/u-boot.lds @@ -47,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/omapv1030gsample/Makefile b/board/omapv1030gsample/Makefile new file mode 100644 index 000000000..5d5d8caef --- /dev/null +++ b/board/omapv1030gsample/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := omapv1030gsample.o flash.o +SOBJS := platform.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/omapv1030gsample/config.mk b/board/omapv1030gsample/config.mk new file mode 100644 index 000000000..d9e3c7638 --- /dev/null +++ b/board/omapv1030gsample/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# David Mueller, ELSOFT AG, +# +# (C) Copyright 2004 +# Texas Instruments, +# Kshitij Gupta +# +# TI H3 board with OMAP1710 (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Innovator has 1 bank of 256 MB SDRAM +# Physical Address: +# 1000'0000 to 2000'0000 +# +# +# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 +# (mem base + reserved) +# +# we load ourself to 1108'0000 +# +# + +PLATFORM_LDFLAGS += -no-warn-mismatch +TEXT_BASE = 0x11080000 diff --git a/board/omapv1030gsample/flash.c b/board/omapv1030gsample/flash.c new file mode 100644 index 000000000..7e97ee906 --- /dev/null +++ b/board/omapv1030gsample/flash.c @@ -0,0 +1,492 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ +flash_info_t flash_info[CFG_MAX_MTD_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#undef FLASH_PORT_WIDTH32 +#define FLASH_PORT_WIDTH16 + +#ifdef FLASH_PORT_WIDTH16 +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) __swab16(x) +#else +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) __swab32(x) +#endif + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define mb() __asm__ __volatile__ ("" : : : "memory") + + +/* Flash Organization Structure */ +typedef struct OrgDef { + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgIntel_28F256L18T[] = { + {4, 32 * 1024}, /* 4 * 32kBytes sectors */ + {255, 128 * 1024}, /* 255 * 128kBytes sectors */ +}; + + +/*----------------------------------------------------------------------- + * Functions + */ +unsigned long flash_init (void); +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); +void flash_print_info (flash_info_t * info); +void flash_unprotect_sectors (FPWV * addr); +int flash_erase (flash_info_t * info, int s_first, int s_last); +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); +void flash_unlock(flash_info_t * info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + switch (i) { + case 0: + flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); + flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); + /* to reset the lock bit */ + flash_unlock(&flash_info[i]); + break; + default: + panic ("configured too many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_unlock(flash_info_t * info) +{ + int j; + for (j=2;jstart[j]); + flash_unprotect_sectors (addr); + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + } +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + OrgDef *pOrgDef; + + pOrgDef = OrgIntel_28F256L18T; + if (info->flash_id == FLASH_UNKNOWN) { + return; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + if (i > 255) { + info->start[i] = base + (i * 0x8000); + info->protect[i] = 0; + } else { + info->start[i] = base + + (i * PHYS_FLASH_SECT_SIZE); + info->protect[i] = 0; + } + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F256L18T: + printf ("FLASH 28F256L18T\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + volatile FPW value; + + /* Write auto select command: read Manufacturer ID */ + addr[0x5555] = (FPW) 0x00AA00AA; + addr[0x2AAA] = (FPW) 0x00550055; + addr[0x5555] = (FPW) 0x00900090; + + mb (); + value = addr[0]; + switch (value) { + + case (FPW) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + mb (); + value = addr[1]; /* device ID */ + switch (value) { + + case (FPW) (INTEL_ID_28F256L18T): + case (FPW) (0x880A880A): + info->flash_id += FLASH_28F256L18T; + info->sector_count = 259; + info->size = 0x02000000; + break; /* => 32 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + + return (info->size); +} + + +/* unprotects a sector for write and erase + * on some intel parts, this unprotects the entire chip, but it + * wont hurt to call this additional times per sector... + */ +void flash_unprotect_sectors (FPWV * addr) +{ +#define PD_FINTEL_WSMS_READY_MASK 0x0080 + + *addr = (FPW) 0x00500050; /* clear status register */ + + /* this sends the clear lock bit command */ + *addr = (FPW) 0x00600060; + *addr = (FPW) 0x00D000D0; +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + flash_unprotect_sectors (addr); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + *addr = (FPW) 0x00500050;/* clear status register */ + *addr = (FPW) 0x00200020;/* erase setup */ + *addr = (FPW) 0x00D000D0;/* erase confirm */ + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer_masked () > + CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + /* suspend erase */ + *addr = (FPW) 0x00B000B0; + /* reset to read mode */ + *addr = (FPW) 0x00FF00FF; + rcode = 1; + break; + } + } + + /* clear status register cmd. */ + *addr = (FPW) 0x00500050; + *addr = (FPW) 0x00FF00FF;/* resest to read mode */ + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } +/* get lower word aligned address */ +#ifdef FLASH_PORT_WIDTH16 + wp = (addr & ~1); + port_width = 2; +#else + wp = (addr & ~3); + port_width = 4; +#endif + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + } + + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_data (info, wp, SWAP (data))) != 0) { + return (rc); + } + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < port_width; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_data (info, wp, SWAP (data))); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong status; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait while polling the status register */ + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} diff --git a/board/omapv1030gsample/omapv1030gsample.c b/board/omapv1030gsample/omapv1030gsample.c new file mode 100644 index 000000000..d96f4d3eb --- /dev/null +++ b/board/omapv1030gsample/omapv1030gsample.c @@ -0,0 +1,223 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, + * + * (C) Copyright 2003 + * Texas Instruments, + * Kshitij Gupta + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_OMAPV1030) +#include <./configs/omap1510.h> +#endif +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +#endif + + +void flash__init (void); +void ether__init (void); +void set_muxconf_regs (void); +void peripheral_power_enable (void); + +#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) + +static inline void delay (unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of OMAPV10300 G-Sample */ + gd->bd->bi_arch_number = 998; /* a temp one */ + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x10000100; + + /* Configure MUX settings */ + set_muxconf_regs (); + peripheral_power_enable (); + +/* this speeds up your boot a quite a bit. However to make it + * work, you need make sure your kernel startup flush bug is fixed. + * ... rkw ... + */ + icache_enable (); + + flash__init (); + ether__init (); + return 0; +} + + +int misc_init_r (void) +{ + /* currently empty */ + return (0); +} + +/****************************** + Routine: + Description: +******************************/ +void flash__init (void) +{ +#define EMIFS_GlB_Config_REG 0xfffecc0c + unsigned int regval; + regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); + /* Turn off write protection for flash devices. */ + regval = regval | 0x0001; + *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; +} +/************************************************************* + Routine:ether__init + Description: take the Ethernet controller out of reset and wait + for the EEPROM load to complete. +*************************************************************/ +void ether__init (void) +{ + #define LAN_RESET_REGISTER 0x0840001c + #define ETH_CONTROL_REG 0x0840030b + + int timeout; + + timeout = 1000; + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; + do { + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; + udelay (3); + } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001 && --timeout); + if (!timeout) + printf("timed out when resettimg LAN.\n"); + + timeout = 1000; + do { + *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; + udelay (3); + } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000 && --timeout); + if (!timeout) + printf("timed out when resettimg LAN.\n"); + + *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; + udelay (3); +} + +/****************************** + Routine: + Description: +******************************/ +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +/****************************************************** + Routine: set_muxconf_regs + Description: Setting up the configuration Mux registers + specific to the hardware +*******************************************************/ +/* OMAPV1030 has a different way to config mux */ +void set_muxconf_regs (void) +{ + volatile unsigned int *MuxConfReg; + /* set each registers to its reset value; */ + + /* SPARE Register setting at Configuration level */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) 0xFFFE102C); + *MuxConfReg = 1; + + /* Select emifs_nfcs_1 instead of gpio19 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) 0xFFFE11E8); + *MuxConfReg = 1; + + /* Select emifs_nfcs_2 */ + MuxConfReg = + (volatile unsigned int *) ((unsigned int) 0xFFFE14B8); + *MuxConfReg = 2; + + /* Select wire_1 for TEST_NEMU1 */ + //MuxConfReg = + // (volatile unsigned int *) ((unsigned int) 0xFFFE12D8); + //*MuxConfReg = 5; + + /* TBD: add more pin mux here */ + + + MuxConfReg = + (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); + *MuxConfReg = COMP_MODE_ENABLE; +} + +/****************************************************** + Routine: peripheral_power_enable + Description: Enable the power for UART1 +*******************************************************/ +void peripheral_power_enable (void) +{ +/* OMAPV1030 has a different ULPDR */ +#define UART2_48MHZ_ENABLE ((unsigned short)0x0040) +#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFB101A) + + *SW_CLOCK_REQUEST |= UART2_48MHZ_ENABLE; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +void nand_init(void) +{ + extern flash_info_t flash_info[]; + + nand_probe(CFG_NAND_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } + +#ifdef CFG_JFFS2_MEM_NAND + flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; + flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */ + flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ + flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x10200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */ +#endif +} +#endif + diff --git a/board/omapv1030gsample/platform.S b/board/omapv1030gsample/platform.S new file mode 100644 index 000000000..e08e6f81c --- /dev/null +++ b/board/omapv1030gsample/platform.S @@ -0,0 +1,508 @@ +/* + * G-Sample Board specific setup info + * + * (C) Copyright 2004-2005 + * Texas Instruments, + * Kshitij Gupta + * Jian Zhang + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if defined(CONFIG_OMAPV1030) +#include <./configs/omap1510.h> +#endif + + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +.globl platformsetup +platformsetup: + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT1) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT1 + ldr r1, VAL_ARM_IDLECT1 + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT2) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT2 + ldr r1, VAL_ARM_IDLECT2 + str r1, [r0] + + /*------------------------------------------------------* + * Set up ARM CLM registers (IDLECT3) * + *------------------------------------------------------*/ + ldr r0, REG_ARM_IDLECT3 + ldr r1, VAL_ARM_IDLECT3 + str r1, [r0] + + mov r1, #0x05 /* PER_EN bit */ + ldr r0, REG_ARM_RSTCT2 + strh r1, [r0] /* CLKM; Peripheral reset. */ + + /* check lock bit is not good enough: + when boot from NOR flash and control goes here + lock bit is set, ADPLL1 reg1 is zero. This is x2 + mode which is not what we want. We want x16. + */ +#if 0 + /* check if ADPLL LOCK bit (BIT 4) set or not */ + ldr r0, REG_ADPLL1_3 + ldrh r1, [r0] + ands r1, r1, #0x10 /* Check the LOCK bit.*/ + bne skip_adpll /* skip if already locked*/ +#else + /* Load physical SDRAM base. */ + mov r0, #0x10000000 + /* Get current execution location. */ + mov r1, pc + /* Compare. */ + cmp r1, r0 + /* Skip over ADPLL initialization if running from SDRAM. */ + bge skip_adpll +#endif + /* Set CLKM to bypass mode so DPLL multiplier/divider can be changed */ + /* Otherwise DPLL won't lock */ + /* I supposedly need to enable the dsp clock before switching */ + ldr r1, VAL1_ARM_SYSST + ldr r0, REG_ARM_SYSST + strh r1, [r0] + mov r0, #0x400 +1: + subs r0, r0, #0x1 /* wait for any bubbles to finish */ + bne 1b + ldr r1, VAL1_ARM_CKCTL /* for now, let arm/dsp/tc be dpll/2 */ + ldr r0, REG_ARM_CKCTL + strh r1, [r0] + /* a few nops to let settle */ + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + /* setup ADPLL1 */ + /* Ramp up the clock to 13*16Mhz */ + ldr r0, REG_ADPLL1_1 /* X16 */ + mov r1, #0x140 + strh r1, [r0] + + /* clear and set enable bit (BIT 14) */ + ldr r0, REG_ADPLL1_3 + mov r1, #0 + strh r1, [r0] + mov r1, #0x4000 + strh r1, [r0] + /* set, clear, and set INITZ bit (BIT 7) */ + orr r1, r1, #0x80 + strh r1, [r0] + mov r1, #0x4000 + strh r1, [r0] + orr r1, r1, #0x80 + strh r1, [r0] + /* get all bits right */ + ldr r1, VAL_ADPLL1_3 + strh r1, [r0] + /* wait until LOCK bit (BIT 4) set */ +2: + ldrh r1, [r0] + ands r1, r1, #0x10 /* Check the LOCK bit.*/ + beq 2b /* loop until bit goes hi. */ +lock_end: + + /* Now set CLKM to Sync-Scalable */ + /* I supposedly need to enable the dsp clock before switching */ + ldr r1, VAL2_ARM_SYSST + ldr r0, REG_ARM_SYSST + strh r1, [r0] + mov r0, #0x400 +3: + subs r0, r0, #0x1 /* wait for any bubbles to finish */ + bne 3b + ldr r1, VAL2_ARM_CKCTL /* for now, let arm/dsp/tc be dpll/2 */ + ldr r0, REG_ARM_CKCTL + strh r1, [r0] + /* a few nops to let settle */ + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +skip_adpll: + /*------------------------------------------------------* + * Turn off the watchdog during init... * + *------------------------------------------------------*/ + ldr r0, REG_WATCHDOG + ldr r1, WATCHDOG_VAL1 + str r1, [r0] + ldr r1, WATCHDOG_VAL2 + str r1, [r0] + ldr r0, REG_WSPRDOG + ldr r1, WSPRDOG_VAL1 + str r1, [r0] + ldr r0, REG_WWPSDOG + +watch1Wait: + ldr r1, [r0] + tst r1, #0x10 + bne watch1Wait + + ldr r0, REG_WSPRDOG + ldr r1, WSPRDOG_VAL2 + str r1, [r0] + ldr r0, REG_WWPSDOG +watch2Wait: + ldr r1, [r0] + tst r1, #0x10 + bne watch2Wait + + + /* Set memory timings corresponding to the new clock speed */ + + /* Check execution location to determine current execution location + * and branch to appropriate initialization code. + */ + /* Load physical SDRAM base. */ + mov r0, #0x10000000 + /* Get current execution location. */ + mov r1, pc + /* Compare. */ + cmp r1, r0 + /* Skip over EMIF-fast initialization if running from SDRAM. */ + bge skip_sdram + + /* Enable EMIFF TC Doubler in OMAP1710 */ + ldr r0, REG_EMIFF_DOUBLER + mov r1, #0x1 + str r1, [r0] + + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 /* value should be checked */ +4: + subs r3, r3, #0x1 /* Decrement count */ + bne 4b + + + /* + * Set SDRAM control values. Disable refresh before MRS command. + */ + + /* mobile ddr operation */ + ldr r0, REG_SDRAM_OPERATION //cc80 + mov r2, #07 + str r2, [r0] + + /* config register */ + ldr r0, REG_SDRAM_CONFIG //cc20 + ldr r1, SDRAM_CONFIG_VAL + str r1, [r0] + + /* manual command register */ + ldr r0, REG_SDRAM_MANUAL_CMD //cc84 + /* issue set cke high */ + mov r1, #CMD_SDRAM_CKE_SET_HIGH //#7 + str r1, [r0] + /* issue nop */ + mov r1, #CMD_SDRAM_NOP //#0 + str r1, [r0] + + mov r2, #0x0100 +waitMDDR1: + subs r2, r2, #1 + bne waitMDDR1 /* delay loop */ + + /* issue precharge */ + mov r1, #CMD_SDRAM_PRECHARGE + str r1, [r0] + + /* issue autorefresh x 2 */ + mov r1, #CMD_SDRAM_AUTOREFRESH + str r1, [r0] + str r1, [r0] + + /* mrs register ddr mobile */ + ldr r0, REG_SDRAM_MRS + mov r1, #0x33 + str r1, [r0] + + /* emrs1 low-power register */ + ldr r0, REG_SDRAM_EMRS1 + /* self refresh on all banks */ + mov r1, #0 + str r1, [r0] + + ldr r0, REG_DLL_URD_CONTROL + ldr r1, DLL_URD_CONTROL_VAL + str r1, [r0] + + ldr r0, REG_DLL_LRD_CONTROL + ldr r1, DLL_LRD_CONTROL_VAL + str r1, [r0] + + ldr r0, REG_DLL_WRT_CONTROL + ldr r1, DLL_WRT_CONTROL_VAL + str r1, [r0] + + /* delay loop */ + mov r2, #0x0100 +waitMDDR2: + subs r2, r2, #1 + bne waitMDDR2 + + /* + * Delay for SDRAM initialization. + */ + mov r3, #0x1800 +5: + subs r3, r3, #1 /* Decrement count. */ + bne 5b + b common_tc + +skip_sdram: + + ldr r0, REG_SDRAM_CONFIG + ldr r1, SDRAM_CONFIG_VAL + str r1, [r0] + +common_tc: + /* slow interface */ + ldr r1, VAL_TC_EMIFS_CONFIG + ldr r0, REG_TC_EMIFS_CONFIG + str r1, [r0] + + ldr r1, VAL_TC_EMIFS_CS0_CONFIG + ldr r0, REG_TC_EMIFS_CS0_CONFIG + str r1, [r0] /* Chip Select 0 */ + + ldr r1, VAL_TC_EMIFS_CS1_CONFIG + ldr r0, REG_TC_EMIFS_CS1_CONFIG + str r1, [r0] /* Chip Select 1 */ + + ldr r1, VAL_TC_EMIFS_CS2_CONFIG + ldr r0, REG_TC_EMIFS_CS2_CONFIG + str r1, [r0] /* Chip Select 2 */ + + ldr r1, VAL_TC_EMIFS_CS3_CONFIG + ldr r0, REG_TC_EMIFS_CS3_CONFIG + str r1, [r0] /* Chip Select 3 */ + + /* inserting additional 2 clock cycle hold time for testing LAN */ + ldr r0, REG_TC_EMIFS_CS2_ADVANCED + ldr r1, VAL_TC_EMIFS_CS2_ADVANCED + str r1, [r0] + + /* Start MPU Timer 1 */ + ldr r0, REG_MPU_LOAD_TIMER + ldr r1, VAL_MPU_LOAD_TIMER + str r1, [r0] + + ldr r0, REG_MPU_CNTL_TIMER + ldr r1, VAL_MPU_CNTL_TIMER + str r1, [r0] + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + + +REG_TC_EMIFS_CONFIG: /* 32 bits */ + .word 0xfffecc0c +REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ + .word 0xfffecc10 +REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ + .word 0xfffecc14 +REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ + .word 0xfffecc18 +REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ + .word 0xfffecc1c +REG_TC_EMIFS_CS2_ADVANCED: /* 32 bits */ + .word 0xfffecc58 + +/* MPU clock/reset/power mode control registers */ +REG_ARM_CKCTL: /* 16 bits */ + .word 0xfffece00 + +REG_ARM_IDLECT3: /* 16 bits */ + .word 0xfffece24 +REG_ARM_IDLECT2: /* 16 bits */ + .word 0xfffece08 +REG_ARM_IDLECT1: /* 16 bits */ + .word 0xfffece04 + +REG_ARM_RSTCT2: /* 16 bits */ + .word 0xfffece14 +REG_ARM_SYSST: /* 16 bits */ + .word 0xfffece18 +/* ADPLL registers */ +REG_ADPLL1_1: /* 16 bits */ + .word 0xfffecf02 +REG_ADPLL1_3: /* 16 bits */ + .word 0xfffecf06 +VAL_ADPLL1_3: + .word 0x0000dc98 + +/* Watch Dog register */ +/* secure watchdog stop */ +REG_WSPRDOG: + .word 0xfffeb048 +/* watchdog write pending */ +REG_WWPSDOG: + .word 0xfffeb034 + +WSPRDOG_VAL1: + .word 0x0000aaaa +WSPRDOG_VAL2: + .word 0x00005555 + +/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, + counter @8192 rows, 10 ns, 8 burst */ +REG_SDRAM_CONFIG: + .word 0xfffecc20 + +/* Operation register */ +REG_SDRAM_OPERATION: + .word 0xfffecc80 + +REG_EMIFF_DOUBLER: + .word 0xfffecc60 + +/* Manual command register */ +REG_SDRAM_MANUAL_CMD: + .word 0xfffecc84 + +/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ +REG_SDRAM_MRS: + .word 0xfffecc70 + +/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ +REG_SDRAM_EMRS1: + .word 0xfffecc78 + +/* WRT DLL register */ +REG_DLL_WRT_CONTROL: + .word 0xfffecc64 +DLL_WRT_CONTROL_VAL: + .word 0x00000006 + +/* URD DLL register */ +REG_DLL_URD_CONTROL: + .word 0xfffeccc0 +DLL_URD_CONTROL_VAL: + .word 0x00000006 + +/* LRD DLL register */ +REG_DLL_LRD_CONTROL: + .word 0xfffecccc + +REG_WATCHDOG: + .word 0xfffec808 + +REG_MPU_LOAD_TIMER: + .word 0xfffec600 +REG_MPU_CNTL_TIMER: + .word 0xfffec500 + +/* 96 MHz Samsung Mobile DDR */ +SDRAM_CONFIG_VAL: + .word 0x0003f7f6 + +DLL_LRD_CONTROL_VAL: + .word 0x00000006 + +VAL1_ARM_CKCTL: + .word 0x1555 +VAL2_ARM_CKCTL: + .word 0x350e +VAL1_ARM_SYSST: + .word 0x2800 +VAL2_ARM_SYSST: + .word 0x1001 + +VAL_DPLL1_CTL: + .word 0x2810 + +VAL_TC_EMIFS_CONFIG: + .word 0x00000010 + +VAL_TC_EMIFS_CS0_CONFIG: + .word 0x0017000c +VAL_TC_EMIFS_CS1_CONFIG: + .word 0x0010fffb +/* EMIFS CS2 Configuration Register: A/D Multiplexed, 8 RWS, 8 WWS, + WELEN = 4, 1 BT WST, Asynchronous Read mode & Ref_Clk = TC_Clock */ +VAL_TC_EMIFS_CS2_CONFIG: + .word 0x0040488b +VAL_TC_EMIFS_CS3_CONFIG: + .word 0xffc0fff3 +/* EMIFS CS2 Advanced Configuration Register: ADV hold = 2 Ref_Clk cycles, + OE SETUP = 3 */ +VAL_TC_EMIFS_CS2_ADVANCED: + .word 0x00000103 + +VAL_TC_EMIFF_SDRAM_CONFIG: + .word 0x010290fc +VAL_TC_EMIFF_MRS: + .word 0x00000027 + +VAL_ARM_IDLECT1: + .word 0x000014c6 + +VAL_ARM_IDLECT2: + .word 0x000009ff +VAL_ARM_IDLECT3: + .word 0x0000003f + +WATCHDOG_VAL1: + .word 0x000000f5 +WATCHDOG_VAL2: + .word 0x000000a0 + +VAL_MPU_LOAD_TIMER: + .word 0xffffffff +VAL_MPU_CNTL_TIMER: + .word 0xffffffa1 + +/* command values */ +.equ CMD_SDRAM_NOP, 0x00000000 +.equ CMD_SDRAM_PRECHARGE, 0x00000001 +.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 +.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/omapv1030gsample/u-boot.lds b/board/omapv1030gsample/u-boot.lds new file mode 100644 index 000000000..eee4813f3 --- /dev/null +++ b/board/omapv1030gsample/u-boot.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/overo/Makefile b/board/overo/Makefile new file mode 100644 index 000000000..dd673ca4d --- /dev/null +++ b/board/overo/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := overo.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +######################################################################### +sinclude $(obj).depend diff --git a/board/overo/config.mk b/board/overo/config.mk new file mode 100644 index 000000000..d372fd901 --- /dev/null +++ b/board/overo/config.mk @@ -0,0 +1,29 @@ +# +# Overo uses OMAP3 (ARM-CortexA8) cpu +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 diff --git a/board/overo/overo.c b/board/overo/overo.c new file mode 100644 index 000000000..e85be7d5e --- /dev/null +++ b/board/overo/overo.c @@ -0,0 +1,138 @@ +/* + * Maintainer : Steve Sakoman + * + * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by + * Richard Woodruff + * Syed Mohammed Khasim + * Sunil Kumar + * Shashi Ranjan + * + * (C) Copyright 2004-2008 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "overo.h" + +#if defined(CONFIG_CMD_NET) +static void setup_net_chip(void); +#endif + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OVERO; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + twl4030_power_init(); + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); + +#if defined(CONFIG_CMD_NET) + setup_net_chip(); +#endif + + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_OVERO(); +} + +#if defined(CONFIG_CMD_NET) +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void setup_net_chip(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + /* Configure GPMC registers */ + writel(NET_LAN9221_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1); + writel(NET_LAN9221_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2); + writel(NET_LAN9221_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3); + writel(NET_LAN9221_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4); + writel(NET_LAN9221_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5); + writel(NET_LAN9221_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6); + writel(NET_LAN9221_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); + + /* Make GPIO 64 as output pin and send a magic pulse through it */ + if (!omap_request_gpio(64)) { + omap_set_gpio_direction(64, 0); + omap_set_gpio_dataout(64, 1); + udelay(1); + omap_set_gpio_dataout(64, 0); + udelay(1); + omap_set_gpio_dataout(64, 1); + } +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/board/overo/overo.h b/board/overo/overo.h new file mode 100644 index 000000000..18735232a --- /dev/null +++ b/board/overo/overo.h @@ -0,0 +1,391 @@ +/* + * (C) Copyright 2008 + * Steve Sakoman + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OVERO_H_ +#define _OVERO_H_ + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "Gumstix Overo board", +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "OneNAND", +#else + "NAND", +#endif +}; + +/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */ +#define NET_LAN9221_GPMC_CONFIG1 0x00001000 +#define NET_LAN9221_GPMC_CONFIG2 0x00080701 +#define NET_LAN9221_GPMC_CONFIG3 0x00020201 +#define NET_LAN9221_GPMC_CONFIG4 0x08030703 +#define NET_LAN9221_GPMC_CONFIG5 0x00060908 +#define NET_LAN9221_GPMC_CONFIG6 0x87030000 +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_OVERO() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\ + /* - MMC1_WP*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + /* - SMSC911X_NRES*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_nCS3*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ + /* - PEN_DOWN*/\ + MUX_VAL(CP(CSI2_DY1), (IEN | PTU | EN | M4)) /*GPIO_115*/\ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\ + MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ + MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\ + MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\ + MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\ + MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\ + MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\ + MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\ + MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\ + MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\ + MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\ + MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\ + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\ + /* BT_NRESET*/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\ + /* - USBH_CPEN*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\ + /* - USBH_RESET*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\ + MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\ + MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\ + /* - LAN_INTR */\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\ + MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\ + /* - W2W_NRESET*/\ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\ + /* die to die */\ + MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ + + +#endif diff --git a/board/oxc/Makefile b/board/oxc/Makefile index cf07cf40f..ae7a93208 100644 --- a/board/oxc/Makefile +++ b/board/oxc/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/oxc/flash.c b/board/oxc/flash.c index 296c01dc8..795b7ccff 100644 --- a/board/oxc/flash.c +++ b/board/oxc/flash.c @@ -163,7 +163,7 @@ static ulong flash_get_size (vu_char *addr, flash_info_t *info) } if (devid == FLASH_STM320DB) { - /* MPC8240 can address maximum 2Mb of flash, that is why the MSB + /* MPC8240 can address maximum 2Mb of flash, that is why the MSB * lead is grounded and we can access only 2 first Mb */ info->flash_id = vendor << 16 | devid; info->sector_count = 32; diff --git a/board/oxc/oxc.c b/board/oxc/oxc.c index b61d39951..6cc3cc5a3 100644 --- a/board/oxc/oxc.c +++ b/board/oxc/oxc.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { #ifndef CFG_RAMBOOT long size; diff --git a/board/oxc/u-boot.lds b/board/oxc/u-boot.lds new file mode 100644 index 000000000..2a5cd2ebd --- /dev/null +++ b/board/oxc/u-boot.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pb1x00/Makefile b/board/pb1x00/Makefile index afe02c27c..d1cdc6b92 100644 --- a/board/pb1x00/Makefile +++ b/board/pb1x00/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,23 +23,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o -SOBJS = lowlevel_init.o +OBJS = $(BOARD).o flash.o +SOBJS = memsetup.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/pb1x00/memsetup.S b/board/pb1x00/memsetup.S new file mode 100644 index 000000000..44f02b955 --- /dev/null +++ b/board/pb1x00/memsetup.S @@ -0,0 +1,392 @@ +/* Memory sub-system initialization code */ + +#include +#include +#include +#include +#include + +#define AU1500_SYS_ADDR 0xB1900000 +#define sys_endian 0x0038 +#define CP0_Config0 $16 +#define MEM_1MS ((396000000/1000000) * 1000) + + .text + .set noreorder + .set mips32 + + .globl memsetup +memsetup: + /* + * Step 1) Establish CPU endian mode. + * NOTE: A fair amount of code is necessary on the Pb1000 to + * obtain the value of Switch S8.1 which is used to determine + * endian at run-time. + */ + + /* RCE1 */ + li t0, MEM_STCFG1 + li t1, 0x00000083 + sw t1, 0(t0) + + li t0, MEM_STTIME1 + li t1, 0x33030A10 + sw t1, 0(t0) + + li t0, MEM_STADDR1 + li t1, 0x11803E40 + sw t1, 0(t0) + + /* Set DSTRB bits so switch will read correctly */ + li t1, 0xBE00000C + lw t2, 0(t1) + or t2, t2, 0x00000300 + sw t2, 0(t1) + + /* Check switch setting */ + li t1, 0xBE000014 + lw t2, 0(t1) + and t2, t2, 0x00000100 + bne t2, zero, big_endian + nop + +little_endian: + + /* Change Au1 core to little endian */ + li t0, AU1500_SYS_ADDR + li t1, 1 + sw t1, sys_endian(t0) + mfc0 t2, CP0_CONFIG + mtc0 t2, CP0_CONFIG + nop + nop + + /* Big Endian is default so nothing to do but fall through */ + +big_endian: + + /* + * Step 2) Establish Status Register + * (set BEV, clear ERL, clear EXL, clear IE) + */ + li t1, 0x00400000 + mtc0 t1, CP0_STATUS + + /* + * Step 3) Establish CP0 Config0 + * (set OD, set K0=3) + */ + li t1, 0x00080003 + mtc0 t1, CP0_CONFIG + + /* + * Step 4) Disable Watchpoint facilities + */ + li t1, 0x00000000 + mtc0 t1, CP0_WATCHLO + mtc0 t1, CP0_IWATCHLO + /* + * Step 5) Disable the performance counters + */ + mtc0 zero, CP0_PERFORMANCE + nop + + /* + * Step 6) Establish EJTAG Debug register + */ + mtc0 zero, CP0_DEBUG + nop + + /* + * Step 7) Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + + /* First setup pll:s to make serial work ok */ + /* We have a 12 MHz crystal */ + li t0, SYS_CPUPLL + li t1, 0x21 /* 396 MHz */ + sw t1, 0(t0) + sync + nop + nop + + /* wait 1mS for clocks to settle */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + /* Setup AUX PLL */ + li t0, SYS_AUXPLL + li t1, 8 /* 96 MHz */ + sw t1, 0(t0) /* aux pll */ + sync + + /* Static memory controller */ + + /* RCE0 8MB AMD29D323 Flash */ + li t0, MEM_STCFG0 + li t1, 0x00001403 + sw t1, 0(t0) + + li t0, MEM_STTIME0 + li t1, 0xFFFFFFDD + sw t1, 0(t0) + + li t0, MEM_STADDR0 + li t1, 0x11F83FE0 + sw t1, 0(t0) + + /* RCE1 CPLD Board Logic */ + li t0, MEM_STCFG1 + li t1, 0x00000083 + sw t1, 0(t0) + + li t0, MEM_STTIME1 + li t1, 0x33030A10 + sw t1, 0(t0) + + li t0, MEM_STADDR1 + li t1, 0x11803E40 + sw t1, 0(t0) + + /* RCE2 CPLD Board Logic */ + li t0, MEM_STCFG2 + li t1, 0x00000004 + sw t1, 0(t0) + + li t0, MEM_STTIME2 + li t1, 0x08061908 + sw t1, 0(t0) + + li t0, MEM_STADDR2 + li t1, 0x12A03FC0 + sw t1, 0(t0) + + /* RCE3 PCMCIA 250ns */ + li t0, MEM_STCFG3 + li t1, 0x00000002 + sw t1, 0(t0) + + li t0, MEM_STTIME3 + li t1, 0x280E3E07 + sw t1, 0(t0) + + li t0, MEM_STADDR3 + li t1, 0x10000000 + sw t1, 0(t0) + + sync + + /* Set peripherals to a known state */ + li t0, IC0_CFG0CLR + li t1, 0xFFFFFFFF + sw t1, 0(t0) + + li t0, IC0_CFG0CLR + sw t1, 0(t0) + + li t0, IC0_CFG1CLR + sw t1, 0(t0) + + li t0, IC0_CFG2CLR + sw t1, 0(t0) + + li t0, IC0_SRCSET + sw t1, 0(t0) + + li t0, IC0_ASSIGNSET + sw t1, 0(t0) + + li t0, IC0_WAKECLR + sw t1, 0(t0) + + li t0, IC0_RISINGCLR + sw t1, 0(t0) + + li t0, IC0_FALLINGCLR + sw t1, 0(t0) + + li t0, IC0_TESTBIT + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, IC1_CFG0CLR + li t1, 0xFFFFFFFF + sw t1, 0(t0) + + li t0, IC1_CFG0CLR + sw t1, 0(t0) + + li t0, IC1_CFG1CLR + sw t1, 0(t0) + + li t0, IC1_CFG2CLR + sw t1, 0(t0) + + li t0, IC1_SRCSET + sw t1, 0(t0) + + li t0, IC1_ASSIGNSET + sw t1, 0(t0) + + li t0, IC1_WAKECLR + sw t1, 0(t0) + + li t0, IC1_RISINGCLR + sw t1, 0(t0) + + li t0, IC1_FALLINGCLR + sw t1, 0(t0) + + li t0, IC1_TESTBIT + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, SYS_FREQCTRL0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_FREQCTRL1 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_CLKSRC + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_PININPUTEN + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, 0xB1100100 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, 0xB1400100 + li t1, 0x00000000 + sw t1, 0(t0) + + + li t0, SYS_WAKEMSK + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_WAKESRC + li t1, 0x00000000 + sw t1, 0(t0) + + /* wait 1mS before setup */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + + /* + * Skip memory setup if we are running from memory + */ + li t0, 0x90000000 + sub t0, ra, t0 + bltz t0, skip_memsetup + nop + + /* + * SDCS0 - Not used, for SMROM + * SDCS1 - 32MB Micron 48LCBM16A2 + * SDCS2 - 32MB Micron 48LCBM16A2 + */ + li t0, MEM_SDMODE0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_SDMODE1 + li t1, 0x00552229 + sw t1, 0(t0) + + li t0, MEM_SDMODE2 + li t1, 0x00552229 + sw t1, 0(t0) + + li t0, MEM_SDADDR0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_SDADDR1 + li t1, 0x001003F8 + sw t1, 0(t0) + + li t0, MEM_SDADDR2 + li t1, 0x001023F8 + sw t1, 0(t0) + + sync + + li t0, MEM_SDREFCFG + li t1, 0x74000c30 /* Disable */ + sw t1, 0(t0) + sync + + li t0, MEM_SDPRECMD + sw zero, 0(t0) + sync + + li t0, MEM_SDAUTOREF + sw zero, 0(t0) + sync + sw zero, 0(t0) + sync + + li t0, MEM_SDREFCFG + li t1, 0x76000c30 /* Enable */ + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD0 + li t1, 0x00000023 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD1 + li t1, 0x00000023 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD2 + li t1, 0x00000023 + sw t1, 0(t0) + sync + + /* wait 1mS after setup */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + +skip_memsetup: + + li t0, SYS_PINFUNC + li t1, 0/*0x00008080*/ + sw t1, 0(t0) + + /* + li t0, SYS_TRIOUTCLR + li t1, 0x00001FFF + sw t1, 0(t0) + + li t0, SYS_OUTPUTCLR + li t1, 0x00008000 + sw t1, 0(t0) + */ + sync + + j ra + nop diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c index 82e2613e2..40ac2a4d7 100644 --- a/board/pb1x00/pb1x00.c +++ b/board/pb1x00/pb1x00.c @@ -25,9 +25,8 @@ #include #include #include -#include -phys_size_t initdram(int board_type) +long int initdram(int board_type) { /* Sdram is setup by assembler code */ /* If memory could be changed, we should return the true value here */ @@ -42,16 +41,14 @@ void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); int checkboard (void) { -#if defined(CONFIG_IDE_PCMCIA) && 0 u16 status; -#endif /* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */ volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; u32 proc_id; *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ - proc_id = read_c0_prid(); + proc_id = read_32bit_cp0_register(CP0_PRID); switch (proc_id >> 24) { case 0: @@ -72,9 +69,6 @@ int checkboard (void) default: printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); } - - set_io_port_base(0); - #if defined(CONFIG_IDE_PCMCIA) && 0 /* Enable 3.3 V on slot 0 ( VCC ) No 5V */ diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 1e1c5590d..a2d19a84c 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -43,28 +43,26 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = .; - _gp = ALIGN(16) + 0x7ff0; + . = ALIGN(4); + .sdata : { *(.sdata) } - .got : { - __got_start = .; - *(.got) - __got_end = .; - } + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; .sdata : { *(.sdata) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; . = ALIGN(4); - .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .sbss : { *(.sbss) } + .bss : { *(.bss) } uboot_end = .; } diff --git a/board/pcippc2/Makefile b/board/pcippc2/Makefile index a6ae906de..2998f23eb 100644 --- a/board/pcippc2/Makefile +++ b/board/pcippc2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,23 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o \ fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o -SOBJS = +AOBJS = -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(COBJS) $(AOBJS) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/pcippc2/cpc710_init_ram.c b/board/pcippc2/cpc710_init_ram.c index 171f06c58..57ed8f087 100644 --- a/board/pcippc2/cpc710_init_ram.c +++ b/board/pcippc2/cpc710_init_ram.c @@ -28,205 +28,227 @@ #include "pcippc2.h" #include "i2c.h" -typedef struct cpc710_mem_org_s { - u8 rows; - u8 cols; - u8 banks2; - u8 org; +typedef struct cpc710_mem_org_s +{ + u8 rows; + u8 cols; + u8 banks2; + u8 org; } cpc710_mem_org_t; -static int cpc710_compute_mcer (u32 * mcer, - unsigned long *size, unsigned int sdram); -static int cpc710_eeprom_checksum (unsigned int sdram); -static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset); +static int cpc710_compute_mcer (u32 * mcer, + unsigned long * + size, + unsigned int sdram); +static int cpc710_eeprom_checksum (unsigned int sdram); +static u8 cpc710_eeprom_read (unsigned int sdram, + unsigned int offset); -static u32 cpc710_mcer_mem[] = { - 0x000003f3, /* 18 lines, 4 Mb */ - 0x000003e3, /* 19 lines, 8 Mb */ - 0x000003c3, /* 20 lines, 16 Mb */ - 0x00000383, /* 21 lines, 32 Mb */ - 0x00000303, /* 22 lines, 64 Mb */ - 0x00000203, /* 23 lines, 128 Mb */ - 0x00000003, /* 24 lines, 256 Mb */ - 0x00000002, /* 25 lines, 512 Mb */ - 0x00000001 /* 26 lines, 1024 Mb */ +static u32 cpc710_mcer_mem [] = +{ + 0x000003f3, /* 18 lines, 4 Mb */ + 0x000003e3, /* 19 lines, 8 Mb */ + 0x000003c3, /* 20 lines, 16 Mb */ + 0x00000383, /* 21 lines, 32 Mb */ + 0x00000303, /* 22 lines, 64 Mb */ + 0x00000203, /* 23 lines, 128 Mb */ + 0x00000003, /* 24 lines, 256 Mb */ + 0x00000002, /* 25 lines, 512 Mb */ + 0x00000001 /* 26 lines, 1024 Mb */ }; -static cpc710_mem_org_t cpc710_mem_org[] = { - {0x0c, 0x09, 0x02, 0x00}, /* 0000: 12/ 9/2 */ - {0x0d, 0x09, 0x02, 0x00}, /* 0000: 13/ 9/2 */ - {0x0d, 0x0a, 0x02, 0x00}, /* 0000: 13/10/2 */ - {0x0d, 0x0b, 0x02, 0x00}, /* 0000: 13/11/2 */ - {0x0d, 0x0c, 0x02, 0x00}, /* 0000: 13/12/2 */ - {0x0e, 0x0c, 0x02, 0x00}, /* 0000: 14/12/2 */ - {0x0b, 0x08, 0x02, 0x01}, /* 0001: 11/ 8/2 */ - {0x0b, 0x09, 0x01, 0x02}, /* 0010: 11/ 9/1 */ - {0x0b, 0x0a, 0x01, 0x03}, /* 0011: 11/10/1 */ - {0x0c, 0x08, 0x02, 0x04}, /* 0100: 12/ 8/2 */ - {0x0c, 0x0a, 0x02, 0x05}, /* 0101: 12/10/2 */ - {0x0d, 0x08, 0x01, 0x06}, /* 0110: 13/ 8/1 */ - {0x0d, 0x08, 0x02, 0x07}, /* 0111: 13/ 8/2 */ - {0x0d, 0x09, 0x01, 0x08}, /* 1000: 13/ 9/1 */ - {0x0d, 0x0a, 0x01, 0x09}, /* 1001: 13/10/1 */ - {0x0b, 0x08, 0x01, 0x0a}, /* 1010: 11/ 8/1 */ - {0x0c, 0x08, 0x01, 0x0b}, /* 1011: 12/ 8/1 */ - {0x0c, 0x09, 0x01, 0x0c}, /* 1100: 12/ 9/1 */ - {0x0e, 0x09, 0x02, 0x0d}, /* 1101: 14/ 9/2 */ - {0x0e, 0x0a, 0x02, 0x0e}, /* 1110: 14/10/2 */ - {0x0e, 0x0b, 0x02, 0x0f} /* 1111: 14/11/2 */ +static cpc710_mem_org_t cpc710_mem_org [] = +{ + { 0x0c, 0x09, 0x02, 0x00 }, /* 0000: 12/ 9/2 */ + { 0x0d, 0x09, 0x02, 0x00 }, /* 0000: 13/ 9/2 */ + { 0x0d, 0x0a, 0x02, 0x00 }, /* 0000: 13/10/2 */ + { 0x0d, 0x0b, 0x02, 0x00 }, /* 0000: 13/11/2 */ + { 0x0d, 0x0c, 0x02, 0x00 }, /* 0000: 13/12/2 */ + { 0x0e, 0x0c, 0x02, 0x00 }, /* 0000: 14/12/2 */ + { 0x0b, 0x08, 0x02, 0x01 }, /* 0001: 11/ 8/2 */ + { 0x0b, 0x09, 0x01, 0x02 }, /* 0010: 11/ 9/1 */ + { 0x0b, 0x0a, 0x01, 0x03 }, /* 0011: 11/10/1 */ + { 0x0c, 0x08, 0x02, 0x04 }, /* 0100: 12/ 8/2 */ + { 0x0c, 0x0a, 0x02, 0x05 }, /* 0101: 12/10/2 */ + { 0x0d, 0x08, 0x01, 0x06 }, /* 0110: 13/ 8/1 */ + { 0x0d, 0x08, 0x02, 0x07 }, /* 0111: 13/ 8/2 */ + { 0x0d, 0x09, 0x01, 0x08 }, /* 1000: 13/ 9/1 */ + { 0x0d, 0x0a, 0x01, 0x09 }, /* 1001: 13/10/1 */ + { 0x0b, 0x08, 0x01, 0x0a }, /* 1010: 11/ 8/1 */ + { 0x0c, 0x08, 0x01, 0x0b }, /* 1011: 12/ 8/1 */ + { 0x0c, 0x09, 0x01, 0x0c }, /* 1100: 12/ 9/1 */ + { 0x0e, 0x09, 0x02, 0x0d }, /* 1101: 14/ 9/2 */ + { 0x0e, 0x0a, 0x02, 0x0e }, /* 1110: 14/10/2 */ + { 0x0e, 0x0b, 0x02, 0x0f } /* 1111: 14/11/2 */ }; unsigned long cpc710_ram_init (void) { - unsigned long memsize = 0; - unsigned long bank_size; - u32 mcer; + unsigned long memsize = 0; + unsigned long bank_size; + u32 mcer; #ifndef CFG_RAMBOOT - /* Clear memory banks - */ - out32 (REG (SDRAM0, MCER0), 0); - out32 (REG (SDRAM0, MCER1), 0); - out32 (REG (SDRAM0, MCER2), 0); - out32 (REG (SDRAM0, MCER3), 0); - out32 (REG (SDRAM0, MCER4), 0); - out32 (REG (SDRAM0, MCER5), 0); - out32 (REG (SDRAM0, MCER6), 0); - out32 (REG (SDRAM0, MCER7), 0); - iobarrier_rw (); + /* Clear memory banks + */ + out32(REG(SDRAM0, MCER0), 0); + out32(REG(SDRAM0, MCER1), 0); + out32(REG(SDRAM0, MCER2), 0); + out32(REG(SDRAM0, MCER3), 0); + out32(REG(SDRAM0, MCER4), 0); + out32(REG(SDRAM0, MCER5), 0); + out32(REG(SDRAM0, MCER6), 0); + out32(REG(SDRAM0, MCER7), 0); + iobarrier_rw(); - /* Disable memory - */ - out32 (REG (SDRAM0, MCCR), 0x13b06000); - iobarrier_rw (); + /* Disable memory + */ + out32(REG(SDRAM0,MCCR), 0x13b06000); + iobarrier_rw(); #endif - /* Only the first memory bank is initialised now - */ - if (!cpc710_compute_mcer (&mcer, &bank_size, 0)) { - puts ("Unsupported SDRAM type !\n"); - hang (); - } - memsize += bank_size; + /* Only the first memory bank is initialised now + */ + if (! cpc710_compute_mcer(& mcer, & bank_size, 0)) + { + puts("Unsupported SDRAM type !\n"); + hang(); + } + memsize += bank_size; #ifndef CFG_RAMBOOT - /* Enable bank, zero start - */ - out32 (REG (SDRAM0, MCER0), mcer | 0x80000000); - iobarrier_rw (); + /* Enable bank, zero start + */ + out32(REG(SDRAM0, MCER0), mcer | 0x80000000); + iobarrier_rw(); #endif #ifndef CFG_RAMBOOT - /* Enable memory - */ - out32 (REG (SDRAM0, MCCR), in32 (REG (SDRAM0, MCCR)) | 0x80000000); + /* Enable memory + */ + out32(REG(SDRAM0, MCCR), in32(REG(SDRAM0, MCCR)) | 0x80000000); - /* Wait until initialisation finished - */ - while (!(in32 (REG (SDRAM0, MCCR)) & 0x20000000)) { - iobarrier_rw (); - } + /* Wait until initialisation finished + */ + while (! (in32 (REG(SDRAM0, MCCR)) & 0x20000000)) + { + iobarrier_rw(); + } - /* Clear Memory Error Status and Address registers - */ - out32 (REG (SDRAM0, MESR), 0); - out32 (REG (SDRAM0, MEAR), 0); - iobarrier_rw (); + /* Clear Memory Error Status and Address registers + */ + out32(REG(SDRAM0, MESR), 0); + out32(REG(SDRAM0, MEAR), 0); + iobarrier_rw(); - /* ECC is not configured now - */ + /* ECC is not configured now + */ #endif - /* Memory size counter - */ - out32 (REG (CPC0, RGBAN1), memsize); + /* Memory size counter + */ + out32(REG(CPC0, RGBAN1), memsize); - return memsize; + return memsize; } -static int cpc710_compute_mcer (u32 * mcer, unsigned long *size, unsigned int sdram) +static int cpc710_compute_mcer ( + u32 * mcer, + unsigned long * size, + unsigned int sdram) { - u8 rows; - u8 cols; - u8 banks2; - unsigned int lines; - u32 mc = 0; - unsigned int i; - cpc710_mem_org_t *org = 0; + u8 rows; + u8 cols; + u8 banks2; + unsigned int lines; + u32 mc = 0; + unsigned int i; + cpc710_mem_org_t * org = 0; - if (!i2c_reset ()) { - puts ("Can't reset I2C!\n"); - hang (); - } - if (!cpc710_eeprom_checksum (sdram)) { - puts ("Invalid EEPROM checksum !\n"); - hang (); - } + if (! i2c_reset()) + { + puts("Can't reset I2C!\n"); + hang(); + } - rows = cpc710_eeprom_read (sdram, 3); - cols = cpc710_eeprom_read (sdram, 4); - /* Can be 2 or 4 banks; divide by 2 - */ - banks2 = cpc710_eeprom_read (sdram, 17) / 2; + if (! cpc710_eeprom_checksum(sdram)) + { + puts("Invalid EEPROM checksum !\n"); + hang(); + } - lines = rows + cols + banks2; + rows = cpc710_eeprom_read(sdram, 3); + cols = cpc710_eeprom_read(sdram, 4); + /* Can be 2 or 4 banks; divide by 2 + */ + banks2 = cpc710_eeprom_read(sdram, 17) / 2; - if (lines < 18 || lines > 26) { - /* Unsupported configuration - */ - return 0; - } + lines = rows + cols + banks2; - mc |= cpc710_mcer_mem[lines - 18] << 6; + if (lines < 18 || lines > 26) + { + /* Unsupported configuration + */ + return 0; + } - for (i = 0; i < sizeof (cpc710_mem_org) / sizeof (cpc710_mem_org_t); - i++) { - cpc710_mem_org_t *corg = cpc710_mem_org + i; - if (corg->rows == rows && corg->cols == cols - && corg->banks2 == banks2) { - org = corg; + mc |= cpc710_mcer_mem [lines - 18] << 6; - break; - } - } + for (i = 0; i < sizeof(cpc710_mem_org) / sizeof(cpc710_mem_org_t); i++) + { + cpc710_mem_org_t * corg = cpc710_mem_org + i; - if (!org) { - /* Unsupported configuration - */ - return 0; - } + if (corg->rows == rows && corg->cols == cols && corg->banks2 == banks2) + { + org = corg; - mc |= (u32) org->org << 2; + break; + } + } - /* Supported configuration - */ - *mcer = mc; - *size = 1l << (lines + 4); + if (! org) + { + /* Unsupported configuration + */ + return 0; + } - return 1; + mc |= (u32) org->org << 2; + + /* Supported configuration + */ + *mcer = mc; + *size = 1l << (lines + 4); + + return 1; } -static int cpc710_eeprom_checksum (unsigned int sdram) +static int cpc710_eeprom_checksum ( + unsigned int sdram) { - u8 sum = 0; - unsigned int i; + u8 sum = 0; + unsigned int i; - for (i = 0; i < 63; i++) { - sum += cpc710_eeprom_read (sdram, i); - } + for (i = 0; i < 63; i++) + { + sum += cpc710_eeprom_read(sdram, i); + } - return sum == cpc710_eeprom_read (sdram, 63); + return sum == cpc710_eeprom_read(sdram, 63); } -static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset) +static u8 cpc710_eeprom_read ( + unsigned int sdram, + unsigned int offset) { - u8 dev = (sdram << 1) | 0xa0; - u8 data; + u8 dev = (sdram << 1) | 0xa0; + u8 data; - if (!i2c_read_byte (&data, dev, offset)) { - puts ("I2C error !\n"); - hang (); - } + if (! i2c_read_byte(& data, dev,offset)) + { + puts("I2C error !\n"); + hang(); + } - return data; + return data; } diff --git a/board/pcippc2/fpga_serial.h b/board/pcippc2/fpga_serial.h index 52750143c..92c9cdd33 100644 --- a/board/pcippc2/fpga_serial.h +++ b/board/pcippc2/fpga_serial.h @@ -25,10 +25,10 @@ #define _FPGA_SERIAL_H_ extern void fpga_serial_init (int); -extern void fpga_serial_putc (char); -extern void fpga_serial_puts (const char *); -extern int fpga_serial_getc (void); -extern int fpga_serial_tstc (void); -extern void fpga_serial_setbrg (void); +extern void fpga_serial_putc (char); +extern void fpga_serial_puts (const char *); +extern int fpga_serial_getc (void); +extern int fpga_serial_tstc (void); +extern void fpga_serial_setbrg (void); #endif diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index c1917c11b..a216c55bc 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -63,7 +63,7 @@ u32 pcippc2_sdram_size (void) return in32 (REG (CPC0, RGBAN1)); } -phys_size_t initdram (int board_type) +long initdram (int board_type) { return cpc710_ram_init (); } @@ -202,7 +202,7 @@ void watchdog_reset (void) enable_interrupts (); } -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { switch (argc) { @@ -241,5 +241,5 @@ U_BOOT_CMD( "wd - print current status\n" ); -#endif +#endif /* CFG_CMD_BSP */ #endif /* CONFIG_WATCHDOG */ diff --git a/board/pcippc2/pcippc2.h b/board/pcippc2/pcippc2.h index a1366ef69..3820bbec6 100644 --- a/board/pcippc2/pcippc2.h +++ b/board/pcippc2/pcippc2.h @@ -38,11 +38,11 @@ extern u32 pcippc2_fpga1_phys; extern u32 pcippc2_sdram_size (void); -extern void pcippc2_fpga_init (void); +extern void pcippc2_fpga_init (void); -extern void pcippc2_cpci3264_init (void); +extern void pcippc2_cpci3264_init (void); -extern void cpc710_pci_init (void); +extern void cpc710_pci_init (void); extern void cpc710_pci_enable_timeout (void); extern unsigned long diff --git a/board/pcippc2/sconsole.h b/board/pcippc2/sconsole.h index 5d850a589..40fd75b81 100644 --- a/board/pcippc2/sconsole.h +++ b/board/pcippc2/sconsole.h @@ -26,23 +26,24 @@ #include -typedef struct sconsole_buffer_s { - unsigned long size; - unsigned long max_size; - unsigned long pos; - unsigned long baud; - char data[1]; +typedef struct sconsole_buffer_s +{ + unsigned long size; + unsigned long max_size; + unsigned long pos; + unsigned long baud; + char data [1]; } sconsole_buffer_t; #define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR) -extern void (* sconsole_putc) (char); -extern void (* sconsole_puts) (const char *); -extern int (* sconsole_getc) (void); -extern int (* sconsole_tstc) (void); -extern void (* sconsole_setbrg) (void); +extern void (* sconsole_putc) (char); +extern void (* sconsole_puts) (const char *); +extern int (* sconsole_getc) (void); +extern int (* sconsole_tstc) (void); +extern void (* sconsole_setbrg) (void); extern void sconsole_flush (void); -extern int sconsole_get_baudrate (void); +extern int sconsole_get_baudrate (void); #endif diff --git a/board/pcippc2/u-boot.lds b/board/pcippc2/u-boot.lds index ebb1b6d46..5c8cd5a88 100644 --- a/board/pcippc2/u-boot.lds +++ b/board/pcippc2/u-boot.lds @@ -29,6 +29,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -40,11 +41,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/pcs440ep/Makefile b/board/pcs440ep/Makefile index 40446884c..4a2a3888f 100644 --- a/board/pcs440ep/Makefile +++ b/board/pcs440ep/Makefile @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk index 4d942ebc7..319c4fa21 100644 --- a/board/pcs440ep/config.mk +++ b/board/pcs440ep/config.mk @@ -25,9 +25,6 @@ # PCS440EP board # -# Check the U-Boot Image with a SHA1 checksum -ALL += $(obj)u-boot.sha1 - #TEXT_BASE = 0x00001000 ifeq ($(ramsym),1) diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c index c5a62e254..ece54781b 100644 --- a/board/pcs440ep/flash.c +++ b/board/pcs440ep/flash.c @@ -82,9 +82,7 @@ void flash_print_info(flash_info_t *info) case FLASH_MAN_AMD: printf ("AMD "); break; case FLASH_MAN_FUJ: printf ("FUJITSU "); break; case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("ST Micro"); break; case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; - case FLASH_MAN_MX: printf ("MXIC "); break; default: printf ("Unknown Vendor "); break; } @@ -119,8 +117,6 @@ void flash_print_info(flash_info_t *info) break; case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); break; - case STM_ID_M29W040B: printf ("ST Micro M29W040B (4 Mbit, uniform sector size)\n"); - break; default: printf ("Unknown Chip Type\n"); break; } @@ -196,15 +192,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; - case (CFG_FLASH_WORD_SIZE)MX_MANUFACT: - info->flash_id = FLASH_MAN_MX; - break; default: info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; @@ -232,11 +222,6 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) info->sector_count = 8; info->size = 0x0080000; /* => 0.5 MB */ break; - case (CFG_FLASH_WORD_SIZE)STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 0,5 MB */ - break; case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: info->flash_id += FLASH_AM800T; diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S index 36a40c97a..0eee4d809 100644 --- a/board/pcs440ep/init.S +++ b/board/pcs440ep/init.S @@ -87,32 +87,27 @@ .globl tlbtab tlbtab: - tlbtab_start + tlbtab_start - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) - /* - * TLB entries for SDRAM are not needed on this platform. - * They are dynamically generated in the SPD DDR detection - * routine. - */ + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) - /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) - /* USB 2.0 Device */ - tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) - - tlbtab_end + tlbtab_end diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index f66f3f233..8858f0a5e 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -23,116 +23,20 @@ #include #include -#include -#include -#include #include #include -#include -#include -#include DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -unsigned char sha1_checksum[SHA1_SUM_LEN]; - -/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */ -unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, - 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf}; - -static void set_leds (int val) +static void set_leds(int val) { - out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27)); + unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, + 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf}; + out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27)); } -#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27) - -void __led_init (led_id_t mask, int state) -{ - int val = GET_LEDS; - - if (state == STATUS_LED_ON) - val |= mask; - else - val &= ~mask; - set_leds (val); -} - -void __led_set (led_id_t mask, int state) -{ - int val = GET_LEDS; - - if (state == STATUS_LED_ON) - val |= mask; - else if (state == STATUS_LED_OFF) - val &= ~mask; - set_leds (val); -} - -void __led_toggle (led_id_t mask) -{ - int val = GET_LEDS; - - val ^= mask; - set_leds (val); -} - -static void status_led_blink (void) -{ - int i; - int val = GET_LEDS; - - /* set all LED which are on, to state BLINKING */ - for (i = 0; i < 4; i++) { - if (val & 0x01) status_led_set (3 - i, STATUS_LED_BLINKING); - else status_led_set (3 - i, STATUS_LED_OFF); - val = val >> 1; - } -} - -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -void show_boot_progress (int val) -{ - /* find all valid Codes for val in README */ - if (val == -30) return; - if (val < 0) { - /* smthing goes wrong */ - status_led_blink (); - return; - } - switch (val) { - case 1: - /* validating Image */ - status_led_set (0, STATUS_LED_OFF); - status_led_set (1, STATUS_LED_ON); - status_led_set (2, STATUS_LED_ON); - break; - case 15: - /* booting */ - status_led_set (0, STATUS_LED_ON); - status_led_set (1, STATUS_LED_ON); - status_led_set (2, STATUS_LED_ON); - break; -#if 0 - case 64: - /* starting Ethernet configuration */ - status_led_set (0, STATUS_LED_OFF); - status_led_set (1, STATUS_LED_OFF); - status_led_set (2, STATUS_LED_ON); - break; -#endif - case 80: - /* loading Image */ - status_led_set (0, STATUS_LED_ON); - status_led_set (1, STATUS_LED_OFF); - status_led_set (2, STATUS_LED_ON); - break; - } -} -#endif - int board_early_init_f(void) { register uint reg; @@ -175,272 +79,12 @@ int board_early_init_f(void) *-------------------------------------------------------------------*/ mfsdr(sdr_pci0, reg); mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */ + mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */ mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ return 0; } -#define EEPROM_LEN 256 -void load_sernum_ethaddr (void) -{ - int ret; - char buf[EEPROM_LEN]; - char mac[32]; - char *use_eeprom; - u16 checksumcrc16 = 0; - - /* read the MACs from EEprom */ - status_led_set (0, STATUS_LED_ON); - status_led_set (1, STATUS_LED_ON); - ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN); - if (ret == 0) { - checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2); - /* check, if the EEprom is programmed: - * - The Prefix(Byte 0,1,2) is equal to "ATR" - * - The checksum, stored in the last 2 Bytes, is correct - */ - if ((strncmp (buf,"ATR",3) != 0) || - ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) || - ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) { - /* EEprom is not programmed */ - printf("%s: EEPROM Checksum not OK\n", __FUNCTION__); - } else { - /* get the MACs */ - sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", - buf[3], - buf[4], - buf[5], - buf[6], - buf[7], - buf[8]); - setenv ("ethaddr", (char *) mac); - sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", - buf[9], - buf[10], - buf[11], - buf[12], - buf[13], - buf[14]); - setenv ("eth1addr", (char *) mac); - return; - } - } - - /* some error reading the EEprom */ - if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) { - /* dont use bootcmd */ - setenv("bootdelay", "-1"); - return; - } - /* == default ? use standard */ - if (strncmp (use_eeprom, "default", 7) == 0) { - return; - } - /* Env doesnt exist -> hang */ - status_led_blink (); - /* here we do this "handy" because we have no interrupts - at this time */ - puts ("### EEPROM ERROR ### Please RESET the board ###\n"); - for (;;) { - __led_toggle (12); - udelay (100000); - } - return; -} - -#ifdef CONFIG_PREBOOT - -static uchar kbd_magic_prefix[] = "key_magic"; -static uchar kbd_command_prefix[] = "key_cmd"; - -struct kbd_data_t { - char s1; - char s2; -}; - -struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) -{ - char *val; - unsigned long tmp; - - /* use the DIPs for some bootoptions */ - val = getenv (ENV_NAME_DIP); - tmp = simple_strtoul (val, NULL, 16); - - kbd_data->s2 = (tmp & 0x0f); - kbd_data->s1 = (tmp & 0xf0) >> 4; - return kbd_data; -} - -static int compare_magic (const struct kbd_data_t *kbd_data, char *str) -{ - char s1 = str[0]; - - if (s1 >= '0' && s1 <= '9') - s1 -= '0'; - else if (s1 >= 'a' && s1 <= 'f') - s1 = s1 - 'a' + 10; - else if (s1 >= 'A' && s1 <= 'F') - s1 = s1 - 'A' + 10; - else - return -1; - - if (s1 != kbd_data->s1) return -1; - - s1 = str[1]; - if (s1 >= '0' && s1 <= '9') - s1 -= '0'; - else if (s1 >= 'a' && s1 <= 'f') - s1 = s1 - 'a' + 10; - else if (s1 >= 'A' && s1 <= 'F') - s1 = s1 - 'A' + 10; - else - return -1; - - if (s1 != kbd_data->s2) return -1; - return 0; -} - -static char *key_match (const struct kbd_data_t *kbd_data) -{ - char magic[sizeof (kbd_magic_prefix) + 1]; - char *suffix; - char *kbd_magic_keys; - - /* - * The following string defines the characters that can be appended - * to "key_magic" to form the names of environment variables that - * hold "magic" key codes, i. e. such key codes that can cause - * pre-boot actions. If the string is empty (""), then only - * "key_magic" is checked (old behaviour); the string "125" causes - * checks for "key_magic1", "key_magic2" and "key_magic5", etc. - */ - if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) - kbd_magic_keys = ""; - - /* loop over all magic keys; - * use '\0' suffix in case of empty string - */ - for (suffix = kbd_magic_keys; *suffix || - suffix == kbd_magic_keys; ++suffix) { - sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); - if (compare_magic (kbd_data, getenv (magic)) == 0) { - char cmd_name[sizeof (kbd_command_prefix) + 1]; - char *cmd; - - sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); - cmd = getenv (cmd_name); - - return (cmd); - } - } - return (NULL); -} - -#endif /* CONFIG_PREBOOT */ - -static int pcs440ep_readinputs (void) -{ - int i; - char value[20]; - - /* read the inputs and set the Envvars */ - /* Revision Level Bit 26 - 29 */ - i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2); - i = swapbits[i]; - sprintf (value, "%02x", i); - setenv (ENV_NAME_REVLEV, value); - /* Solder Switch Bit 30 - 33 */ - i = (in32 (GPIO0_IR) & 0x00000003) << 2; - i += (in32 (GPIO1_IR) & 0xc0000000) >> 30; - i = swapbits[i]; - sprintf (value, "%02x", i); - setenv (ENV_NAME_SOLDER, value); - /* DIP Switch Bit 49 - 56 */ - i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7); - i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4]; - sprintf (value, "%02x", i); - setenv (ENV_NAME_DIP, value); - return 0; -} - - -#if defined(CONFIG_SHA1_CHECK_UB_IMG) -/************************************************************************* - * calculate a SHA1 sum for the U-Boot image in Flash. - * - ************************************************************************/ -static int pcs440ep_sha1 (int docheck) -{ - unsigned char *data; - unsigned char *ptroff; - unsigned char output[20]; - unsigned char org[20]; - int i, len = CONFIG_SHA1_LEN; - - memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len); - data = (unsigned char *)CFG_LOAD_ADDR; - ptroff = &data[len + SHA1_SUM_POS]; - - for (i = 0; i < SHA1_SUM_LEN; i++) { - org[i] = ptroff[i]; - ptroff[i] = 0; - } - - sha1_csum ((unsigned char *) data, len, (unsigned char *)output); - - if (docheck == 2) { - for (i = 0; i < 20 ; i++) { - printf("%02X ", output[i]); - } - printf("\n"); - } - if (docheck == 1) { - for (i = 0; i < 20 ; i++) { - if (org[i] != output[i]) return 1; - } - } - return 0; -} - -/************************************************************************* - * do some checks after the SHA1 checksum from the U-Boot Image was - * calculated. - * - ************************************************************************/ -static void pcs440ep_checksha1 (void) -{ - int ret; - char *cs_test; - - status_led_set (0, STATUS_LED_OFF); - status_led_set (1, STATUS_LED_OFF); - status_led_set (2, STATUS_LED_ON); - ret = pcs440ep_sha1 (1); - if (ret == 0) return; - - if ((cs_test = getenv ("cs_test")) == NULL) { - /* Env doesnt exist -> hang */ - status_led_blink (); - /* here we do this "handy" because we have no interrupts - at this time */ - puts ("### SHA1 ERROR ### Please RESET the board ###\n"); - for (;;) { - __led_toggle (2); - udelay (100000); - } - } - - if (strncmp (cs_test, "off", 3) == 0) { - printf ("SHA1 U-Boot sum NOT ok!\n"); - setenv ("bootdelay", "-1"); - } -} -#else -static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);} -#endif - int misc_init_r (void) { uint pbcr; @@ -495,18 +139,6 @@ int misc_init_r (void) CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, &flash_info[1]); - pcs440ep_readinputs (); - pcs440ep_checksha1 (); -#ifdef CONFIG_PREBOOT - { - struct kbd_data_t kbd_data; - /* Decode keys */ - char *str = strdup (key_match (get_keys (&kbd_data))); - /* Set or delete definition */ - setenv ("preboot", str); - free (str); - } -#endif /* CONFIG_PREBOOT */ return 0; } @@ -524,35 +156,55 @@ int checkboard(void) return (0); } -void spd_ddr_init_hang (void) -{ - status_led_set (0, STATUS_LED_OFF); - status_led_set (1, STATUS_LED_ON); - /* we cannot use hang() because we are still running from - Flash, and so the status_led driver is not initialized */ - puts ("### SDRAM ERROR ### Please RESET the board ###\n"); - for (;;) { - __led_toggle (4); - udelay (100000); - } -} - -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long dram_size = 0; - status_led_set (0, STATUS_LED_ON); - status_led_set (1, STATUS_LED_OFF); + set_leds(1); /* display boot info counter */ dram_size = spd_sdram(); - status_led_set (0, STATUS_LED_OFF); - status_led_set (1, STATUS_LED_ON); - if (dram_size == 0) { - hang(); - } + set_leds(2); /* display boot info counter */ return dram_size; } +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + /************************************************************************* * pci_pre_init * @@ -565,7 +217,7 @@ phys_size_t initdram (int board_type) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -606,7 +258,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* * pci_target_init @@ -725,155 +377,3 @@ void hw_watchdog_reset(void) } #endif - -/************************************************************************* - * "led" Commando for the U-Boot shell - * - ************************************************************************/ -int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int rcode = 0, i; - ulong pattern = 0; - - pattern = simple_strtoul (argv[1], NULL, 16); - if (pattern > 0x400) { - int val = GET_LEDS; - printf ("led: %x\n", val); - return rcode; - } - if (pattern > 0x200) { - status_led_blink (); - hang (); - return rcode; - } - if (pattern > 0x100) { - status_led_blink (); - return rcode; - } - pattern &= 0x0f; - for (i = 0; i < 4; i++) { - if (pattern & 0x01) status_led_set (i, STATUS_LED_ON); - else status_led_set (i, STATUS_LED_OFF); - pattern = pattern >> 1; - } - return rcode; -} - -U_BOOT_CMD( - led, 2, 1, do_led, - "led [bitmask] - set the DIAG-LED\n", - "[bitmask] 0x01 = DIAG 1 on\n" - " 0x02 = DIAG 2 on\n" - " 0x04 = DIAG 3 on\n" - " 0x08 = DIAG 4 on\n" - " > 0x100 set the LED, who are on, to state blinking\n" -); - -#if defined(CONFIG_SHA1_CHECK_UB_IMG) -/************************************************************************* - * "sha1" Commando for the U-Boot shell - * - ************************************************************************/ -int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int rcode = -1; - - if (argc < 2) { - usage: - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - if (argc >= 3) { - unsigned char *data; - unsigned char output[20]; - int len; - int i; - - data = (unsigned char *)simple_strtoul (argv[1], NULL, 16); - len = simple_strtoul (argv[2], NULL, 16); - sha1_csum (data, len, (unsigned char *)output); - printf ("U-Boot sum:\n"); - for (i = 0; i < 20 ; i++) { - printf ("%02X ", output[i]); - } - printf ("\n"); - if (argc == 4) { - data = (unsigned char *)simple_strtoul (argv[3], NULL, 16); - memcpy (data, output, 20); - } - return 0; - } - if (argc == 2) { - char *ptr = argv[1]; - if (*ptr != '-') goto usage; - ptr++; - if ((*ptr == 'c') || (*ptr == 'C')) { - rcode = pcs440ep_sha1 (1); - printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : ""); - } else if ((*ptr == 'p') || (*ptr == 'P')) { - rcode = pcs440ep_sha1 (2); - } else { - rcode = pcs440ep_sha1 (0); - } - return rcode; - } - return rcode; -} - -U_BOOT_CMD( - sha1, 4, 1, do_sha1, - "sha1 - calculate the SHA1 Sum\n", - "address len [addr] calculate the SHA1 sum [save at addr]\n" - " -p calculate the SHA1 sum from the U-Boot image in flash and print\n" - " -c check the U-Boot image in flash\n" -); -#endif - -#if defined (CONFIG_CMD_IDE) -/* These addresses need to be shifted one place to the left - * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) - * These values are shifted - */ -extern ulong *ide_bus_offset; -void inline ide_outb(int dev, int port, unsigned char val) -{ - debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", - dev, port, val, (ATA_CURR_BASE(dev)+port)); - - out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val); -} -unsigned char inline ide_inb(int dev, int port) -{ - uchar val; - val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1))); - debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", - dev, port, (ATA_CURR_BASE(dev)+port), val); - return (val); -} -#endif - -#ifdef CONFIG_IDE_PREINIT -int ide_preinit (void) -{ - /* Set True IDE Mode */ - out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000)); - out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000)); - out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040)); - udelay (100000); - return 0; -} -#endif - -#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - if (idereset == 0) { - out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000)); - } else { - out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000)); - } - udelay (10000); -} -#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ diff --git a/board/pcs440ep/u-boot.lds b/board/pcs440ep/u-boot.lds index ed6135987..6ab476ab1 100644 --- a/board/pcs440ep/u-boot.lds +++ b/board/pcs440ep/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -43,11 +44,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -64,7 +65,6 @@ SECTIONS { cpu/ppc4xx/start.o (.text) board/pcs440ep/init.o (.text) - lib_generic/sha1.o (.text) *(.text) *(.fixup) @@ -128,7 +128,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/pleb2/Makefile b/board/pleb2/Makefile index faa26911b..95d9170b2 100644 --- a/board/pleb2/Makefile +++ b/board/pleb2/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,29 +24,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := pleb2.o flash.o +OBJS := pleb2.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c index 5a1eba6b3..97271d921 100644 --- a/board/pleb2/flash.c +++ b/board/pleb2/flash.c @@ -196,7 +196,7 @@ void flash_print_info (flash_info_t * info) int i; uchar *boottype; uchar *bootletter; - char *fmt; + uchar *fmt; uchar botbootletter[] = "B"; uchar topbootletter[] = "T"; uchar botboottype[] = "bottom boot sector"; diff --git a/board/pleb2/u-boot.lds b/board/pleb2/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/pleb2/u-boot.lds +++ b/board/pleb2/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/pm520/Makefile b/board/pm520/Makefile index c94e24fc6..8cf0d7de7 100644 --- a/board/pm520/Makefile +++ b/board/pm520/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,28 +24,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o flash.o +OBJS := $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/pm520/flash.c b/board/pm520/flash.c index 4301b8c23..38f579bc5 100644 --- a/board/pm520/flash.c +++ b/board/pm520/flash.c @@ -35,36 +35,36 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ #undef FLASH_PORT_WIDTH16 #ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) (x) +#define FLASH_PORT_WIDTH ushort +#define FLASH_PORT_WIDTHV vu_short +#define SWAP(x) (x) #else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) (x) +#define FLASH_PORT_WIDTH ulong +#define FLASH_PORT_WIDTHV vu_long +#define SWAP(x) (x) #endif /* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x00890089 -#define INTEL_ALT 0x00B000B0 +#define INTEL_COMPAT 0x00890089 +#define INTEL_ALT 0x00B000B0 /* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_RESET 0xFFFFFFFF +#define INTEL_PROGRAM 0x00100010 +#define INTEL_ERASE 0x00200020 +#define INTEL_CLEAR 0x00500050 +#define INTEL_LOCKBIT 0x00600060 +#define INTEL_PROTECT 0x00010001 +#define INTEL_STATUS 0x00700070 +#define INTEL_READID 0x00900090 +#define INTEL_CONFIRM 0x00D000D0 +#define INTEL_RESET 0xFFFFFFFF /* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 +#define INTEL_FINISHED 0x00800080 +#define INTEL_OK 0x00800080 -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV #define mb() __asm__ __volatile__ ("" : : : "memory") diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c index 83d9bcd02..65c529192 100644 --- a/board/pm520/pm520.c +++ b/board/pm520/pm520.c @@ -84,7 +84,7 @@ static void sdram_start (int hi_addr) */ #if defined(CONFIG_MPC5200) -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; @@ -187,7 +187,7 @@ phys_size_t initdram (int board_type) #elif defined(CONFIG_MGT5100) -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong dramsize = 0; #ifndef CFG_RAMBOOT @@ -299,7 +299,7 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) void init_ide_reset (void) { @@ -312,9 +312,9 @@ void ide_set_reset (int idereset) debug ("ide_reset(%d)\n", idereset); } -#endif +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) extern void doc_probe (ulong physadr); void doc_init (void) { diff --git a/board/pm520/u-boot.lds b/board/pm520/u-boot.lds new file mode 100644 index 000000000..3cc296848 --- /dev/null +++ b/board/pm520/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pm826/Makefile b/board/pm826/Makefile index dcb190703..7a2014d46 100644 --- a/board/pm826/Makefile +++ b/board/pm826/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/pm826/config.mk b/board/pm826/config.mk index 48ac299fa..c93bad98e 100644 --- a/board/pm826/config.mk +++ b/board/pm826/config.mk @@ -26,7 +26,7 @@ # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE ## Standard: boot 64-bit flash diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c index 7ee3ab65c..7514cd77b 100644 --- a/board/pm826/pm826.c +++ b/board/pm826/pm826.c @@ -279,7 +279,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; @@ -310,7 +310,7 @@ phys_size_t initdram (int board_type) return (psize); } -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) extern void doc_probe (ulong physadr); void doc_init (void) { diff --git a/board/pm826/u-boot.lds b/board/pm826/u-boot.lds new file mode 100644 index 000000000..05f29c6ed --- /dev/null +++ b/board/pm826/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pm828/Makefile b/board/pm828/Makefile index dcb190703..b9ef0c050 100644 --- a/board/pm828/Makefile +++ b/board/pm828/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/pm828/config.mk b/board/pm828/config.mk index 6288431a5..e894af775 100644 --- a/board/pm828/config.mk +++ b/board/pm828/config.mk @@ -26,7 +26,7 @@ # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE ## Standard: boot 64-bit flash diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c index 6038e9758..31932742a 100644 --- a/board/pm828/pm828.c +++ b/board/pm828/pm828.c @@ -312,7 +312,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; @@ -343,7 +343,7 @@ phys_size_t initdram (int board_type) return (psize); } -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) extern void doc_probe (ulong physadr); void doc_init (void) { diff --git a/board/pm828/u-boot.lds b/board/pm828/u-boot.lds new file mode 100644 index 000000000..928c1cf39 --- /dev/null +++ b/board/pm828/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/pm854/Makefile b/board/pm854/Makefile index 2d71cbc51..78281660d 100644 --- a/board/pm854/Makefile +++ b/board/pm854/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/pm854/init.S b/board/pm854/init.S new file mode 100644 index 000000000..ade5d6e5b --- /dev/null +++ b/board/pm854/init.S @@ -0,0 +1,263 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH (8,16,32 or 64 MB) + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 7: 256M DDR + * 0x00000000 256M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 555f6c0ca..94c492f78 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -29,12 +29,14 @@ #include #include #include -#include +#include #if defined(CONFIG_DDR_ECC) extern void ddr_enable_ecc(unsigned int dram_size); #endif +extern long int spd_sdram(void); + void local_bus_init(void); void sdram_init(void); long int fixed_sdram(void); @@ -43,7 +45,8 @@ long int fixed_sdram(void); int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; pci->peer &= 0xffffffdf; /* disable master abort */ #endif @@ -71,16 +74,18 @@ int checkboard (void) } -phys_size_t +long int initdram(int board_type) { long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur= &immap->im_gur; int i,x; x = 10; @@ -93,7 +98,7 @@ initdram(int board_type) udelay (200); while (gur->ddrdllcr != 0x81000100) { - gur->devdisr = gur->devdisr | 0x00010000; + gur->devdisr = gur->devdisr | 0x00010000; asm("sync;isync;msync"); for (i=0; iim_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; uint lbc_hz; @@ -223,7 +229,8 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; @@ -282,6 +289,8 @@ void pci_init_board(void) { #ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/pm854/u-boot.lds b/board/pm854/u-boot.lds index f200810f0..fbfc65a1e 100644 --- a/board/pm854/u-boot.lds +++ b/board/pm854/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -34,6 +35,7 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) + board/pm854/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -43,11 +45,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,6 +65,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) + board/pm854/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) @@ -135,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/pm856/Makefile b/board/pm856/Makefile index 2d71cbc51..5d8ea3494 100644 --- a/board/pm856/Makefile +++ b/board/pm856/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/pm856/init.S b/board/pm856/init.S new file mode 100644 index 000000000..ade5d6e5b --- /dev/null +++ b/board/pm856/init.S @@ -0,0 +1,263 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH (8,16,32 or 64 MB) + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 7: 256M DDR + * 0x00000000 256M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index bf325f89e..504470837 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -30,13 +30,15 @@ #include #include #include -#include +#include #include #if defined(CONFIG_DDR_ECC) extern void ddr_enable_ecc(unsigned int dram_size); #endif +extern long int spd_sdram(void); + void local_bus_init(void); long int fixed_sdram(void); @@ -225,17 +227,18 @@ int checkboard (void) } -phys_size_t +long int initdram(int board_type) { long dram_size = 0; - + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; puts("Initializing\n"); #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur= &immap->im_gur; int i,x; x = 10; @@ -248,7 +251,7 @@ initdram(int board_type) udelay (200); while (gur->ddrdllcr != 0x81000100) { - gur->devdisr = gur->devdisr | 0x00010000; + gur->devdisr = gur->devdisr | 0x00010000; asm("sync;isync;msync"); for (i=0; iim_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; uint clkdiv; uint lbc_hz; @@ -378,7 +382,8 @@ int testdram (void) long int fixed_sdram (void) { #ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; ddr->cs0_bnds = CFG_DDR_CS0_BNDS; ddr->cs0_config = CFG_DDR_CS0_CONFIG; @@ -437,6 +442,8 @@ void pci_init_board(void) { #ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/pm856/u-boot.lds b/board/pm856/u-boot.lds index 01727d177..e946a8e51 100644 --- a/board/pm856/u-boot.lds +++ b/board/pm856/u-boot.lds @@ -23,6 +23,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -35,6 +36,7 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) + board/pm856/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -44,11 +46,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -64,6 +66,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) + board/pm856/init.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) @@ -135,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/pn62/Makefile b/board/pn62/Makefile index eb88898e7..e85d4fdc6 100644 --- a/board/pn62/Makefile +++ b/board/pn62/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o cmd_pn62.o misc.o +OBJS = $(BOARD).o cmd_pn62.o misc.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c index 3f53e4b7c..3ea068d35 100644 --- a/board/pn62/cmd_pn62.c +++ b/board/pn62/cmd_pn62.c @@ -29,7 +29,7 @@ #include #include "pn62.h" -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) extern int do_bootm (cmd_tbl_t *, int, int, char *[]); @@ -157,15 +157,8 @@ int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *s; if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { - printf ("Running autoscript at addr 0x%08lX", load_addr); - - s = getenv ("autoscript_uname"); - if (s) - printf (":%s ...\n", s); - else - puts (" ...\n"); - - rcode = autoscript (load_addr, s); + printf("Running autoscript at addr 0x%08lX ...\n", load_addr); + rcode = autoscript (bd, load_addr); } } #endif diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c index d905b2965..b2f348d4d 100644 --- a/board/pn62/pn62.c +++ b/board/pn62/pn62.c @@ -75,7 +75,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h index f356a40f0..7bda0ad9d 100644 --- a/board/pn62/pn62.h +++ b/board/pn62/pn62.h @@ -26,8 +26,8 @@ /* * Definitions for the Intel Bridge 21554 or 21555. */ -#define I2155X_VPD_ADDR 0xe6 -#define I2155X_VPD_DATA 0xe8 +#define I2155X_VPD_ADDR 0xe6 +#define I2155X_VPD_DATA 0xe8 #define I2155X_VPD_START 0x80 #define I2155X_VPD_SN_START 0x80 @@ -65,17 +65,17 @@ * Definitions for boot protocol using Scratchpad registers. */ #define BOOT_DONE 0 -#define BOOT_DONE_CLEAR 0x00dead00 -#define BOOT_DONE_ERROR 0xbad0dead -#define BOOT_DONE_U_BOOT 0x12345678 -#define BOOT_DONE_LINUX 0x87654321 -#define BOOT_CMD 1 -#define BOOT_CMD_MOVE 0x1 -#define BOOT_CMD_BOOT 0x2 +#define BOOT_DONE_CLEAR 0x00dead00 +#define BOOT_DONE_ERROR 0xbad0dead +#define BOOT_DONE_U_BOOT 0x12345678 +#define BOOT_DONE_LINUX 0x87654321 +#define BOOT_CMD 1 +#define BOOT_CMD_MOVE 0x1 +#define BOOT_CMD_BOOT 0x2 #define BOOT_DATA 2 #define BOOT_PROTO 3 -#define BOOT_PROTO_READY 0x23456789 -#define BOOT_PROTO_CLEAR 0x00000000 +#define BOOT_PROTO_READY 0x23456789 +#define BOOT_PROTO_CLEAR 0x00000000 #define BOOT_STATUS 4 /* @@ -145,15 +145,15 @@ /* * Forward declarations */ -int i2155x_init (void); +int i2155x_init (void); void i2155x_write_scrapad(int idx, u32 val); u32 i2155x_read_scrapad (int idx); void i2155x_set_bar_base (int bar, u32 addr); -int i2155x_read_vpd (int offset, int size, unsigned char *data); +int i2155x_read_vpd (int offset, int size, unsigned char *data); int am79c95x_init (void); -void set_led (unsigned int number, unsigned int function); +void set_led (unsigned int number, unsigned int function); void fatal_error (unsigned int error_code); void show_startup_phase (int phase); diff --git a/board/pn62/u-boot.lds b/board/pn62/u-boot.lds new file mode 100644 index 000000000..eaee3fdef --- /dev/null +++ b/board/pn62/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ppmc7xx/Makefile b/board/ppmc7xx/Makefile index 22332fb3d..c378677cc 100644 --- a/board/ppmc7xx/Makefile +++ b/board/ppmc7xx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,30 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a +OBJS := ppmc7xx.o pci.o flash.o SOBJS := init.o -COBJS := ppmc7xx.o pci.o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c index 061e01ec4..402ac5e20 100644 --- a/board/ppmc7xx/ppmc7xx.c +++ b/board/ppmc7xx/ppmc7xx.c @@ -29,7 +29,7 @@ extern void _start_warm(void); * the SDRAM was already initialised by board_asm_init (see init.S) so we just * return the size of RAM. */ -phys_size_t initdram( int board_type ) +long initdram( int board_type ) { return CFG_SDRAM_SIZE; } diff --git a/board/ppmc7xx/u-boot.lds b/board/ppmc7xx/u-boot.lds index 5239b35af..0dfa8c000 100644 --- a/board/ppmc7xx/u-boot.lds +++ b/board/ppmc7xx/u-boot.lds @@ -26,6 +26,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -37,11 +38,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -122,7 +123,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/ppmc8260/Makefile b/board/ppmc8260/Makefile index 1d56d1618..351f4eea2 100644 --- a/board/ppmc8260/Makefile +++ b/board/ppmc8260/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := ppmc8260.o +OBJS := ppmc8260.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c index f3c85096b..2b20c26f1 100644 --- a/board/ppmc8260/ppmc8260.c +++ b/board/ppmc8260/ppmc8260.c @@ -199,7 +199,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/ppmc8260/u-boot.lds b/board/ppmc8260/u-boot.lds new file mode 100644 index 000000000..84d4b78b9 --- /dev/null +++ b/board/ppmc8260/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c index 363631fd8..8630cc166 100644 --- a/board/prodrive/common/flash.c +++ b/board/prodrive/common/flash.c @@ -48,7 +48,6 @@ void flash_print_info(flash_info_t *info) case FLASH_MAN_AMD: printf ("AMD "); break; case FLASH_MAN_FUJ: printf ("FUJITSU "); break; case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("ST "); break; case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; default: printf ("Unknown Vendor "); break; } @@ -157,9 +156,6 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; diff --git a/board/prodrive/p3p440/Makefile b/board/prodrive/p3p440/Makefile index b93f2c389..47116d367 100644 --- a/board/prodrive/p3p440/Makefile +++ b/board/prodrive/p3p440/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o +OBJS = $(BOARD).o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 1a8aacbdf..2f28e9d87 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -176,7 +176,7 @@ int misc_init_r (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) int pci_pre_init(struct pci_controller *hose) { unsigned long strap; @@ -193,7 +193,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* * pci_target_init diff --git a/board/prodrive/p3p440/u-boot.lds b/board/prodrive/p3p440/u-boot.lds index 0e6c878a4..92bb740e4 100644 --- a/board/prodrive/p3p440/u-boot.lds +++ b/board/prodrive/p3p440/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -43,11 +44,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -67,6 +68,19 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/prodrive/p3p440/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -131,7 +145,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/prodrive/pdnb3/Makefile b/board/prodrive/pdnb3/Makefile index d07f25f98..f3cd5a3f1 100644 --- a/board/prodrive/pdnb3/Makefile +++ b/board/prodrive/pdnb3/Makefile @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := flash.o pdnb3.o nand.o +OBJS := flash.o pdnb3.o nand.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/prodrive/pdnb3/config.mk b/board/prodrive/pdnb3/config.mk index 51dee86ae..6b0f18b30 100644 --- a/board/prodrive/pdnb3/config.mk +++ b/board/prodrive/pdnb3/config.mk @@ -1,2 +1,4 @@ -# TEXT_BASE = 0x01f00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c index 518ea9c03..d0e5fe703 100644 --- a/board/prodrive/pdnb3/flash.c +++ b/board/prodrive/pdnb3/flash.c @@ -24,8 +24,6 @@ #include #include -#if !defined(CFG_FLASH_CFI_DRIVER) - /* * include common flash code (for esd boards) */ @@ -85,5 +83,3 @@ unsigned long flash_init(void) return size; } - -#endif /* CFG_FLASH_CFI_DRIVER */ diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c index b1e704104..1931d64de 100644 --- a/board/prodrive/pdnb3/nand.c +++ b/board/prodrive/pdnb3/nand.c @@ -23,7 +23,7 @@ #include -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include @@ -148,7 +148,7 @@ static int pdnb3_nand_dev_ready(struct mtd_info *mtd) return 1; } -int board_nand_init(struct nand_chip *nand) +void board_nand_init(struct nand_chip *nand) { pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE; @@ -167,6 +167,5 @@ int board_nand_init(struct nand_chip *nand) nand->read_buf = pdnb3_nand_read_buf; nand->verify_buf = pdnb3_nand_verify_buf; nand->dev_ready = pdnb3_nand_dev_ready; - return 0; } #endif diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c index 3445a3abf..e2fed5d74 100644 --- a/board/prodrive/pdnb3/pdnb3.c +++ b/board/prodrive/pdnb3/pdnb3.c @@ -48,6 +48,11 @@ static unsigned long old_val = 0; /* * Miscelaneous platform dependent initialisations */ +int board_post_init(void) +{ + return (0); +} + int board_init(void) { /* arch number of PDNB3 */ @@ -231,7 +236,7 @@ U_BOOT_CMD( "address size\n - boot FPGA with gzipped image at
\n" ); -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) +#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined(CONFIG_PCI) extern struct pci_controller hose; extern void pci_ixp_init(struct pci_controller * hose); diff --git a/board/prodrive/pdnb3/u-boot.lds b/board/prodrive/pdnb3/u-boot.lds index 638edbeee..f05f09344 100644 --- a/board/prodrive/pdnb3/u-boot.lds +++ b/board/prodrive/pdnb3/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile index 301b4a0a5..8e55c9bcd 100644 --- a/board/psyent/pci5441/Makefile +++ b/board/psyent/pci5441/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -12,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -22,34 +22,29 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a COMOBJS := ../common/AMDLV065D.o -COBJS := $(BOARD).o $(COMOBJS) +OBJS := $(BOARD).o $(COMOBJS) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SOBJS = -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/psyent/pci5441/pci5441.c b/board/psyent/pci5441/pci5441.c index 0afef6f96..ea80dd139 100644 --- a/board/psyent/pci5441/pci5441.c +++ b/board/psyent/pci5441/pci5441.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (0); } diff --git a/board/psyent/pci5441/u-boot.lds b/board/psyent/pci5441/u-boot.lds index d3b7c31ae..8f9cd8fa5 100644 --- a/board/psyent/pci5441/u-boot.lds +++ b/board/psyent/pci5441/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS * bss follows. We keep it adjacent to simplify init code. */ __bss_start = .; - .sbss (NOLOAD) : + .sbss : { *(.sbss) *(.sbss.*) @@ -96,7 +96,7 @@ SECTIONS *(.scommon) } . = ALIGN(4); - .bss (NOLOAD) : + .bss : { *(.bss) *(.bss.*) diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile index e23a17bc3..5c1db036b 100644 --- a/board/psyent/pk1c20/Makefile +++ b/board/psyent/pk1c20/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -12,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -22,34 +22,29 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a COMOBJS := ../common/AMDLV065D.o -COBJS := $(BOARD).o led.o $(COMOBJS) +OBJS := $(BOARD).o led.o $(COMOBJS) -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SOBJS = -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/psyent/pk1c20/pk1c20.c b/board/psyent/pk1c20/pk1c20.c index 95b48bc57..1924ae3d1 100644 --- a/board/psyent/pk1c20/pk1c20.c +++ b/board/psyent/pk1c20/pk1c20.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (0); } diff --git a/board/psyent/pk1c20/u-boot.lds b/board/psyent/pk1c20/u-boot.lds index d3b7c31ae..8f9cd8fa5 100644 --- a/board/psyent/pk1c20/u-boot.lds +++ b/board/psyent/pk1c20/u-boot.lds @@ -88,7 +88,7 @@ SECTIONS * bss follows. We keep it adjacent to simplify init code. */ __bss_start = .; - .sbss (NOLOAD) : + .sbss : { *(.sbss) *(.sbss.*) @@ -96,7 +96,7 @@ SECTIONS *(.scommon) } . = ALIGN(4); - .bss (NOLOAD) : + .bss : { *(.bss) *(.bss.*) diff --git a/board/purple/Makefile b/board/purple/Makefile index 29844ba96..b2f2fc0fd 100644 --- a/board/purple/Makefile +++ b/board/purple/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,23 +24,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o sconsole.o +OBJS = $(BOARD).o flash.o sconsole.o SOBJS = lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/purple/flash.c b/board/purple/flash.c index 1baae35eb..752258080 100644 --- a/board/purple/flash.c +++ b/board/purple/flash.c @@ -299,7 +299,7 @@ void flash_print_info (flash_info_t *info) int i; uchar *boottype; uchar *bootletter; - char *fmt; + uchar *fmt; uchar botbootletter[] = "B"; uchar topbootletter[] = "T"; uchar botboottype[] = "bottom boot sector"; diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S index 1bd3edb81..668124a78 100644 --- a/board/purple/lowlevel_init.S +++ b/board/purple/lowlevel_init.S @@ -23,6 +23,7 @@ */ #include +#include #include #define MC_IOGP 0xBF800800 @@ -32,5 +33,5 @@ lowlevel_init: li t0, MC_IOGP li t1, 0xf24 sw t1, 0(t0) - jr ra + j ra nop diff --git a/board/purple/purple.c b/board/purple/purple.c index 977559112..4c3e5b44b 100644 --- a/board/purple/purple.c +++ b/board/purple/purple.c @@ -26,39 +26,30 @@ #include #include #include -#include #include #include -#include #include "sconsole.h" -#define cache_unroll(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, (%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ +#define cache_unroll(base,op) \ + __asm__ __volatile__(" \ + .set noreorder; \ + .set mips3; \ + cache %1, (%0); \ + .set mips0; \ + .set reorder" \ + : \ + : "r" (base), \ "i" (op)); typedef void (*FUNCPTR)(ulong *source, ulong *destination, ulong nlongs); extern void asc_serial_init (void); -extern void asc_serial_putc (char); -extern void asc_serial_puts (const char *); -extern int asc_serial_getc (void); -extern int asc_serial_tstc (void); -extern void asc_serial_setbrg (void); - -void _machine_restart(void) -{ - void (*f)(void) = (void *) 0xbfc00000; - - f(); -} +extern void asc_serial_putc (char); +extern void asc_serial_puts (const char *); +extern int asc_serial_getc (void); +extern int asc_serial_tstc (void); +extern void asc_serial_setbrg (void); static void sdram_timing_init (ulong size) { @@ -85,16 +76,16 @@ static void sdram_timing_init (ulong size) while (p4 < 32 && done == 0) { WRITE_MC_IOGP_1; - for (addr = CKSEG1 + 0x4000; - addr < CKSEG1ADDR (size); + for (addr = KSEG1 + 0x4000; + addr < KSEG1ADDR (size); addr = addr + 4) { *(uint *) addr = 0xaa55aa55; } pass = 1; - for (addr = CKSEG1 + 0x4000; - addr < CKSEG1ADDR (size) && pass == 1; + for (addr = KSEG1 + 0x4000; + addr < KSEG1ADDR (size) && pass == 1; addr = addr + 4) { if (*(uint *) addr != 0xaa55aa55) pass = 0; @@ -124,7 +115,7 @@ static void sdram_timing_init (ulong size) } } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { /* The only supported number of SDRAM banks is 4. */ @@ -138,7 +129,7 @@ phys_size_t initdram(int board_type) ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB; void (* sdram_init) (ulong); - sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init); + sdram_init = (void (*)(ulong)) KSEG0ADDR(&sdram_timing_init); sdram_init(0x10000); @@ -154,8 +145,6 @@ int checkboard (void) printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000); - set_io_port_base(0); - return 0; } @@ -184,7 +173,8 @@ static void copydwords (ulong *source, ulong *destination, ulong nlongs) ulong temp,temp1; ulong *dstend = destination + nlongs; - while (destination < dstend) { + while (destination < dstend) + { temp = *source++; /* dummy read from sdram */ temp1 = *(ulong *)0xa0000000; @@ -260,14 +250,14 @@ void copy_code (ulong dest_addr) /* flush caches */ - start = CKSEG0; + start = KSEG0; end = start + CFG_DCACHE_SIZE; while(start < end) { cache_unroll(start,Index_Writeback_Inv_D); start += CFG_CACHELINE_SIZE; } - start = CKSEG0; + start = KSEG0; end = start + CFG_ICACHE_SIZE; while(start < end) { cache_unroll(start,Index_Invalidate_I); diff --git a/board/purple/sconsole.h b/board/purple/sconsole.h index e130ad4c1..d441f37fc 100644 --- a/board/purple/sconsole.h +++ b/board/purple/sconsole.h @@ -26,20 +26,21 @@ #include -typedef struct sconsole_buffer_s { - unsigned long size; - unsigned long max_size; - unsigned long pos; - char data[1]; +typedef struct sconsole_buffer_s +{ + unsigned long size; + unsigned long max_size; + unsigned long pos; + char data [1]; } sconsole_buffer_t; #define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR) -extern void (* sconsole_putc) (char); -extern void (* sconsole_puts) (const char *); -extern int (* sconsole_getc) (void); -extern int (* sconsole_tstc) (void); -extern void (* sconsole_setbrg) (void); +extern void (* sconsole_putc) (char); +extern void (* sconsole_puts) (const char *); +extern int (* sconsole_getc) (void); +extern int (* sconsole_tstc) (void); +extern void (* sconsole_setbrg) (void); extern void sconsole_flush (void); diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index 972e6e720..1bdac1f4a 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -53,28 +53,27 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = .; - _gp = ALIGN(16) + 0x7ff0; + . = ALIGN(4); + .sdata : { *(.sdata) } - .got : { - __got_start = .; - *(.got) - __got_end = .; - } + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; .sdata : { *(.sdata) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; . = ALIGN(4); - .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .sbss : { *(.sbss) } + .bss : { *(.bss) } uboot_end = .; } diff --git a/board/pxa255_idp/Makefile b/board/pxa255_idp/Makefile index 4892b42bc..b5f352a6f 100644 --- a/board/pxa255_idp/Makefile +++ b/board/pxa255_idp/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,29 +24,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := pxa_idp.o -SOBJS := lowlevel_init.o +OBJS := pxa_idp.o +SOBJS := memsetup.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/pxa255_idp/config.mk b/board/pxa255_idp/config.mk index 55c8b270a..d2a2040e6 100644 --- a/board/pxa255_idp/config.mk +++ b/board/pxa255_idp/config.mk @@ -1,3 +1,3 @@ #TEXT_BASE = 0xa1700000 -TEXT_BASE = 0xa3080000 +TEXT_BASE = 0xa3000000 #TEXT_BASE = 0 diff --git a/board/pxa255_idp/memsetup.S b/board/pxa255_idp/memsetup.S new file mode 100644 index 000000000..7e485a28a --- /dev/null +++ b/board/pxa255_idp/memsetup.S @@ -0,0 +1,496 @@ +/* + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/memsetup.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DRAM_SIZE: .long CFG_DRAM_SIZE + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + +/* + * Memory setup + */ +.globl memsetup +memsetup: + + mov r10, lr + +#ifdef DEBUG_BLINK_ENABLE + /* 3rd blink */ + bl blink +#endif + + /* Set up GPIO pins first ----------------------------------------- */ + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + +#ifdef DEBUG_BLINK_ENABLE + /* 4th debug blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + +#ifdef DEBUG_BLINK_ENABLE + /* 5th blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r3, =CFG_MDREFR_VAL + ldr r2, =0xFFF + and r3, r3, r2 + ldr r4, =0x03ca4000 + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + /* FIXME: we use async mode for now */ + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + /* set MDREFR according to user define with exception of a few bits */ + + ldr r4, =CFG_MDREFR_VAL + orr r4, r4, #(MDREFR_SLFRSH) + bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4b: de-assert MDREFR:SLFRSH. */ + + bic r4, r4, #(MDREFR_SLFRSH) + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ + + ldr r4, =CFG_MDREFR_VAL + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) + str r3, [r1, #MDCNFG_OFFSET] + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ +#if 0 + /* FIXME turn on serial ports */ + /* look into moving this to board_init() */ + ldr r2, =(PXA_CS5_PHYS + 0x03C0002c) + mov r3, #0x13 + str r3, [r2] +#endif + +#ifdef DEBUG_BLINK_ENABLE + /* 6th blink */ + bl blink +#endif + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + /* (hard-coding at 398.12MHz for now). */ + + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ + /* Note: See label 'ENABLECLKS' for the re-enabling */ +#if 0 + ldr r1, =CKEN + mov r2, #0 + str r2, [r1] + + /* default value in case no valid rotary switch setting is found */ + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ + + /* ... and write the core clock config register */ + ldr r1, =CCCR + str r2, [r1] + +#endif + +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#endif + + /* ---------------------------------------------------------------- */ + /* */ + /* ---------------------------------------------------------------- */ + + /* Save SDRAM size */ + ldr r1, =DRAM_SIZE + str r8, [r1] + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + + /* FIXME */ + +#define NODEBUG +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End memsetup */ + /* ---------------------------------------------------------------- */ + +#ifdef DEBUG_BLINK_ENABLE + /* 7th blink */ + bl blink +#endif + +endmemsetup: + + mov pc, r10 + + +#ifdef DEBUG_BLINK_ENABLE + +/* debug LED code */ + +/* delay about 200ms */ +delay: + + /* reset OSCR to 0 */ + ldr r8, =OSCR + mov r9, #0 + str r9, [r8] + + /* make sure new value has stuck */ +1: + ldr r8, =OSCR + ldr r9, [r8] + mov r8, #0x10000 + cmp r9, r8 + bgt 1b + + /* now, wait for delay to expire */ +1: + ldr r8, =OSCR + ldr r9, [r8] + mov r8, #0xd4000 + cmp r8, r9 + bgt 1b + + mov pc, lr + +/* blink code -- trashes r7, r8, r9 */ + +.globl blink +blink: + + mov r7, lr + + /* set GPIO10 as outout */ + ldr r8, =GPDR0 + ldr r9, [r8] + orr r9, r9, #(1<<10) + str r9, [r8] + + /* turn LED off */ + mov r9, #(1<<10) + ldr r8, =GPCR0 + str r9, [r8] + bl delay + + /* turn LED on */ + mov r9, #(1<<10) + ldr r8, =GPSR0 + str r9, [r8] + bl delay + + /* turn LED off */ + mov r9, #(1<<10) + ldr r8, =GPCR0 + str r9, [r8] + + mov pc, r7 + +#endif diff --git a/board/pxa255_idp/u-boot.lds b/board/pxa255_idp/u-boot.lds index 381b6b746..20ce10893 100644 --- a/board/pxa255_idp/u-boot.lds +++ b/board/pxa255_idp/u-boot.lds @@ -44,13 +44,12 @@ SECTIONS . = ALIGN(4); .got : { *(.got) } - . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/quantum/Makefile b/board/quantum/Makefile index c7a1d0551..e50f5ff08 100644 --- a/board/quantum/Makefile +++ b/board/quantum/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o fpga.o +OBJS = $(BOARD).o fpga.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/quantum/fpga.h b/board/quantum/fpga.h index 79b73b561..2ef45e59b 100644 --- a/board/quantum/fpga.h +++ b/board/quantum/fpga.h @@ -31,3 +31,4 @@ int fpga_boot(unsigned char *fpgadata, int size); #define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ #define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ #define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ +/* vim: set ts=4 sw=4 tw=78: */ diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c index 345f127b6..afa6e113d 100644 --- a/board/quantum/quantum.c +++ b/board/quantum/quantum.c @@ -102,7 +102,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds index 1f9a191d4..049f9901f 100644 --- a/board/quantum/u-boot.lds +++ b/board/quantum/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -129,7 +130,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug index 0cd053a8b..894b9bd25 100644 --- a/board/quantum/u-boot.lds.debug +++ b/board/quantum/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/r360mpi/Makefile b/board/r360mpi/Makefile index 9f34ad1c0..1a7e7a693 100644 --- a/board/r360mpi/Makefile +++ b/board/r360mpi/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o pcmcia.o +OBJS = $(BOARD).o flash.o pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/r360mpi/pcmcia.c b/board/r360mpi/pcmcia.c index 4fd9d1298..7d34ac80a 100644 --- a/board/r360mpi/pcmcia.c +++ b/board/r360mpi/pcmcia.c @@ -4,11 +4,11 @@ #undef CONFIG_PCMCIA -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -123,7 +123,7 @@ int pcmcia_hardware_enable(int slot) } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { volatile immap_t *immap; @@ -150,7 +150,7 @@ int pcmcia_hardware_disable(int slot) return (0); } -#endif +#endif /* CFG_CMD_PCMCIA */ int pcmcia_voltage_set(int slot, int vcc, int vpp) @@ -195,10 +195,10 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) reg = 0; switch(vcc) { - case 0: break; + case 0: break; case 33: reg |= 0x0200; break; case 50: reg |= 0x0400; break; - default: goto done; + default: goto done; } /* Checking supported voltages */ diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c index c51e412f4..ffb4c0ecf 100644 --- a/board/r360mpi/r360mpi.c +++ b/board/r360mpi/r360mpi.c @@ -103,7 +103,7 @@ static long int dram_size (long int, long int *, long int); /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds index 5fcd5c9f1..8b06af78e 100644 --- a/board/r360mpi/u-boot.lds +++ b/board/r360mpi/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -126,7 +127,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/r5200/Makefile b/board/r5200/Makefile new file mode 100644 index 000000000..d0364ed85 --- /dev/null +++ b/board/r5200/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/r5200/config.mk b/board/r5200/config.mk new file mode 100644 index 000000000..8fc531979 --- /dev/null +++ b/board/r5200/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x10000000 diff --git a/board/r5200/r5200.c b/board/r5200/r5200.c new file mode 100644 index 000000000..69f3a765b --- /dev/null +++ b/board/r5200/r5200.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + + +int checkboard (void) { + puts ("Board: R5200 Ethernet Module\n"); + return 0; +}; + +long int initdram (int board_type) { + int i; + + /* + * Set CS2 pin to be SD_CS0 + */ + mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) + | MCF_GPIO_PAR_CS_PAR_CS2); + + mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM) + | MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01)); + + /* + * Check to see if the SDRAM has already been initialized + * by a run control tool + */ + if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { + /* + * Initialize DRAM Control Register: DCR + */ + mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01) + | MCF_SDRAMC_DCR_RC(0x30)); + + /* + * Initialize DACR0 + */ + mbar_writeLong(MCF_SDRAMC_DACR0, + MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) + | MCF_SDRAMC_DACRn_CASL(0) + | MCF_SDRAMC_DACRn_CBM(3) + | MCF_SDRAMC_DACRn_PS(2)); + + /* + * Initialize DMR0 + */ + mbar_writeLong(MCF_SDRAMC_DMR0, + MCF_SDRAMC_DMRn_BAM_8M + | MCF_SDRAMC_DMRn_V); + + /* + * Set IP bit in DACR + */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_IP); + + /* + * Wait at least 20ns to allow banks to precharge + */ + for (i = 0; i < 5; i++) + asm(" nop"); + + /* + * Write to this block to initiate precharge + */ + *(u16 *)(CFG_SDRAM_BASE) = 0x9696; + + /* + * Set RE bit in DACR + */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_RE); + + + /* + * Wait for at least 8 auto refresh cycles to occur + */ + for (i = 0; i < 2000; i++) + asm(" nop"); + + /* + * Finish the configuration by issuing the MRS. + */ + mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) + | MCF_SDRAMC_DACRn_MRS); + + + /* + * Write to the SDRAM Mode Register + */ + *(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696; + } + + return CFG_SDRAM_SIZE * 1024 * 1024; +}; + +int testdram (void) { + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/r5200/u-boot.lds b/board/r5200/u-boot.lds new file mode 100644 index 000000000..f7dc07090 --- /dev/null +++ b/board/r5200/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/rattler/Makefile b/board/rattler/Makefile index dc40d9b94..52f0fd6ef 100644 --- a/board/rattler/Makefile +++ b/board/rattler/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o +OBJS := $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c index ad75c2156..be7977dec 100644 --- a/board/rattler/rattler.c +++ b/board/rattler/rattler.c @@ -185,7 +185,7 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -phys_size_t initdram(int board_type) +long int initdram(int board_type) { long int msize = CFG_SDRAM_SIZE; diff --git a/board/rattler/u-boot.lds b/board/rattler/u-boot.lds new file mode 100644 index 000000000..522e6daa5 --- /dev/null +++ b/board/rattler/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/rbc823/Makefile b/board/rbc823/Makefile index 2182bc976..0121ddc79 100644 --- a/board/rbc823/Makefile +++ b/board/rbc823/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o kbd.o +OBJS = $(BOARD).o flash.o kbd.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c index 26ebcae86..84ae5c1b5 100644 --- a/board/rbc823/flash.c +++ b/board/rbc823/flash.c @@ -131,11 +131,11 @@ void flash_print_info (flash_info_t *info) if (info->size >> 20) { printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, + info->size >> 20, info->sector_count); } else { printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, + info->size >> 10, info->sector_count); } @@ -213,7 +213,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x00080000; - break; /* => 512Kb */ + break; /* => 512Kb */ default: info->flash_id = FLASH_UNKNOWN; @@ -448,7 +448,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* re-enable interrupts if necessary */ if (flag) - enable_interrupts(); + enable_interrupts(); /* data polling for D7 */ start = get_timer (0); diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c index 5b62af614..9e60c2b64 100644 --- a/board/rbc823/rbc823.c +++ b/board/rbc823/rbc823.c @@ -142,7 +142,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index e41782554..68ca85644 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -127,7 +128,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/rmu/Makefile b/board/rmu/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/rmu/Makefile +++ b/board/rmu/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/rmu/rmu.c b/board/rmu/rmu.c index e22dc5258..8cb03c7f8 100644 --- a/board/rmu/rmu.c +++ b/board/rmu/rmu.c @@ -92,7 +92,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/rmu/u-boot.lds b/board/rmu/u-boot.lds index 1f9a191d4..049f9901f 100644 --- a/board/rmu/u-boot.lds +++ b/board/rmu/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -129,7 +130,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/rmu/u-boot.lds.debug b/board/rmu/u-boot.lds.debug index 0cd053a8b..894b9bd25 100644 --- a/board/rmu/u-boot.lds.debug +++ b/board/rmu/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/rpxsuper/Makefile b/board/rpxsuper/Makefile index a749e26cc..4535106e6 100644 --- a/board/rpxsuper/Makefile +++ b/board/rpxsuper/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := rpxsuper.o flash.o mii_phy.o +OBJS := rpxsuper.o flash.o mii_phy.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c index f633c5c47..b4331f1cd 100644 --- a/board/rpxsuper/rpxsuper.c +++ b/board/rpxsuper/rpxsuper.c @@ -225,7 +225,7 @@ int checkboard(void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/rpxsuper/u-boot.lds b/board/rpxsuper/u-boot.lds new file mode 100644 index 000000000..9e623d0b9 --- /dev/null +++ b/board/rpxsuper/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/rsdproto/Makefile b/board/rsdproto/Makefile index 5c9c33c9f..9934787e4 100644 --- a/board/rsdproto/Makefile +++ b/board/rsdproto/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := rsdproto.o flash.o +OBJS := rsdproto.o flash.o SOBJS := flash_asm.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/rsdproto/config.mk b/board/rsdproto/config.mk index 35c3d8c76..5844ec1ea 100644 --- a/board/rsdproto/config.mk +++ b/board/rsdproto/config.mk @@ -31,5 +31,3 @@ TEXT_BASE = 0xff000000 /*TEXT_BASE = 0x00200000 */ - -LDSCRIPT := $(SRCTREE)/board/rsdproto/u-boot.lds diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c index 4e43b2966..5ad321852 100644 --- a/board/rsdproto/flash.c +++ b/board/rsdproto/flash.c @@ -76,17 +76,17 @@ unsigned long flash_init (void) unsigned long long *f_addr = (unsigned long long *)PHYS_FLASH; unsigned long long f_command, vendor, device; /* Perform Autoselect */ - f_command = 0x00AA00AA00AA00AAULL; + f_command = 0x00AA00AA00AA00AAULL; ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; + f_command = 0x0055005500550055ULL; ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x0090009000900090ULL; + f_command = 0x0090009000900090ULL; ull_write(&f_addr[0x555], &f_command); ull_read(&f_addr[0], &vendor); vendor &= 0xffff; ull_read(&f_addr[1], &device); device &= 0xffff; - f_command = 0x00F000F000F000F0ULL; + f_command = 0x00F000F000F000F0ULL; ull_write(&f_addr[0x555], &f_command); if (vendor != VENDOR_AMD || device != AMD_29DL323C_B) return 0; @@ -225,16 +225,16 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00AA00AA00AA00AAULL; + f_addr = (unsigned long long *)info->start[0]; + f_command = 0x00AA00AA00AA00AAULL; ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; + f_command = 0x0055005500550055ULL; ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x0080008000800080ULL; + f_command = 0x0080008000800080ULL; ull_write(&f_addr[0x555], &f_command); - f_command = 0x00AA00AA00AA00AAULL; + f_command = 0x00AA00AA00AA00AAULL; ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; + f_command = 0x0055005500550055ULL; ull_write(&f_addr[0x2AA], &f_command); /* Disable interrupts which might cause a timeout here */ @@ -244,9 +244,9 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) for (l_sect = -1, sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - f_addr = + f_addr = (unsigned long long *)(info->start[sect]); - f_command = 0x0030003000300030ULL; + f_command = 0x0030003000300030ULL; ull_write(f_addr, &f_command); l_sect = sect; } @@ -264,7 +264,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) /* this command turns the flash back to read mode */ f_addr = (unsigned long long *)(info->start[l_sect]); - f_command = 0x00F000F000F000F0ULL; + f_command = 0x00F000F000F000F0ULL; ull_write(f_addr, &f_command); printf (" timeout\n"); return 1; @@ -357,7 +357,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * * PARAMETERS: 32 bit long pointer to address, 64 bit long pointer to data * -* RETURNS: 0 if OK, 1 if timeout, 4 if parameter error +* RETURNS: 0 if OK, 1 if timeout, 4 if parameter error *--------------------------------------------------------------------------*/ static unsigned char write_ull(flash_info_t *info, @@ -372,16 +372,16 @@ static unsigned char write_ull(flash_info_t *info, if (address & 0x7) return ERR_ALIGN; - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00AA00AA00AA00AAULL; + f_addr = (unsigned long long *)info->start[0]; + f_command = 0x00AA00AA00AA00AAULL; ull_write(&f_addr[0x555], &f_command); - f_command = 0x0055005500550055ULL; + f_command = 0x0055005500550055ULL; ull_write(&f_addr[0x2AA], &f_command); - f_command = 0x00A000A000A000A0ULL; + f_command = 0x00A000A000A000A0ULL; ull_write(&f_addr[0x555], &f_command); - f_addr = (unsigned long long *)address; - f_command = data; + f_addr = (unsigned long long *)address; + f_command = data; ull_write(f_addr, &f_command); start = get_timer (0); @@ -391,8 +391,8 @@ static unsigned char write_ull(flash_info_t *info, { /* write reset command, command address is unimportant */ /* this command turns the flash back to read mode */ - f_addr = (unsigned long long *)info->start[0]; - f_command = 0x00F000F000F000F0ULL; + f_addr = (unsigned long long *)info->start[0]; + f_command = 0x00F000F000F000F0ULL; ull_write(f_addr, &f_command); return ERR_TIMOUT; } diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c index eeec3b4dc..bf4fd5305 100644 --- a/board/rsdproto/rsdproto.c +++ b/board/rsdproto/rsdproto.c @@ -210,7 +210,7 @@ void read_RS5C372_time (struct tm *timedate) #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) - if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) { + if (i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) { timedate->tm_sec = BCD_TO_BIN (buffer[0]); timedate->tm_min = BCD_TO_BIN (buffer[1]); timedate->tm_hour = BCD_TO_BIN (buffer[2]); @@ -231,7 +231,7 @@ int read_LM84_temp (int address) unsigned char buffer[8]; /*int rc;*/ - if (! i2c_read (address, 0, 1, buffer, 1)) { + if (i2c_read (address, 0, 1, buffer, 1)) { return (int) buffer[0]; } else { /*printf("i2c error %02x\n", rc); */ @@ -282,7 +282,7 @@ int misc_init_f (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index 07a7277c8..70fc3a5d2 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -117,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile index de8a5b2a0..baefa4a74 100644 --- a/board/sacsng/Makefile +++ b/board/sacsng/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := sacsng.o flash.o clkinit.o +OBJS := sacsng.o flash.o clkinit.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c index c00f14ee6..e50b74792 100644 --- a/board/sacsng/sacsng.c +++ b/board/sacsng/sacsng.c @@ -22,8 +22,8 @@ * MA 02111-1307 USA */ -#include #include +#include #include #include #include @@ -159,7 +159,7 @@ int checkboard(void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; @@ -837,36 +837,43 @@ void show_boot_progress (int status) /* * The following are used to control the SPI chip selects for the SPI command. */ -#if defined(CONFIG_CMD_SPI) +#if (CONFIG_COMMANDS & CFG_CMD_SPI) #define SPI_ADC_CS_MASK 0x00000800 #define SPI_DAC_CS_MASK 0x00001000 -static const u32 cs_mask[] = { - SPI_ADC_CS_MASK, - SPI_DAC_CS_MASK, +void spi_adc_chipsel(int cs) +{ + volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); + + if(cs) + iopd->pdat &= ~SPI_ADC_CS_MASK; /* activate the chip select */ + else + iopd->pdat |= SPI_ADC_CS_MASK; /* deactivate the chip select */ +} + +void spi_dac_chipsel(int cs) +{ + volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); + + if(cs) + iopd->pdat &= ~SPI_DAC_CS_MASK; /* activate the chip select */ + else + iopd->pdat |= SPI_DAC_CS_MASK; /* deactivate the chip select */ +} + +/* + * The SPI command uses this table of functions for controlling the SPI + * chip selects: it calls the appropriate function to control the SPI + * chip selects. + */ +spi_chipsel_type spi_chipsel[] = { + spi_adc_chipsel, + spi_dac_chipsel }; +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]); -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); - - iopd->pdat &= ~cs_mask[slave->cs]; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); - - iopd->pdat |= cs_mask[slave->cs]; -} - -#endif +#endif /* CFG_CMD_SPI */ #endif /* CONFIG_MISC_INIT_R */ diff --git a/board/sacsng/u-boot.lds b/board/sacsng/u-boot.lds new file mode 100644 index 000000000..9e623d0b9 --- /dev/null +++ b/board/sacsng/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c index 1e3dffb1e..859dd7afe 100644 --- a/board/sandburst/common/ppc440gx_i2c.c +++ b/board/sandburst/common/ppc440gx_i2c.c @@ -27,8 +27,13 @@ */ #include #include -#include <4xx_i2c.h> +#if defined(CONFIG_440) +# include <440_i2c.h> +#else +# include <405gp_i2c.h> +#endif #include +#include <440_i2c.h> #include #include "ppc440gx_i2c.h" diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h index 10000f5ba..cd4fc8666 100644 --- a/board/sandburst/common/ppc440gx_i2c.h +++ b/board/sandburst/common/ppc440gx_i2c.h @@ -27,7 +27,11 @@ */ #include #include -#include <4xx_i2c.h> +#if defined(CONFIG_440) +# include <440_i2c.h> +#else +# include <405gp_i2c.h> +#endif #include #ifdef CONFIG_HARD_I2C diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index 51b1c7514..781647251 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -200,7 +200,7 @@ void sbcommon_fans(void) * Initialize sdram * ************************************************************************/ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long dram_size = 0; @@ -313,7 +313,7 @@ long int fixed_sdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -330,7 +330,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* * pci_target_init diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile index 49d240c4c..8b3173ca1 100644 --- a/board/sandburst/karef/Makefile +++ b/board/sandburst/karef/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2005 # Sandburst Corporation # Travis B. Sawyer @@ -26,9 +23,6 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif # TBS: add for debugging purposes BUILDUSER := $(shell whoami) @@ -38,31 +32,28 @@ CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' # TBS: end debugging -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ +OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ ../common/sb_common.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend *~ ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds index 216f9c64d..9e9e99045 100644 --- a/board/sandburst/karef/u-boot.lds +++ b/board/sandburst/karef/u-boot.lds @@ -23,6 +23,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -44,11 +45,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -71,7 +72,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -146,7 +147,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index af7d5c08a..47d80fae1 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -23,6 +23,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -34,11 +35,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -61,7 +62,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile index eb149108a..06a9a22b6 100644 --- a/board/sandburst/metrobox/Makefile +++ b/board/sandburst/metrobox/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2005 # Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com # @@ -25,9 +22,6 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif # TBS: add for debugging purposes BUILDUSER := $(shell whoami) @@ -37,30 +31,27 @@ CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' # TBS: end debugging -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ +OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ ../common/sb_common.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend *~ ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c index 66cdfb156..86d259fac 100644 --- a/board/sandburst/metrobox/metrobox.c +++ b/board/sandburst/metrobox/metrobox.c @@ -270,7 +270,7 @@ int checkboard (void) } printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev); - printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name); + printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]); /* Fix the ack in the bme 32 */ udelay(5000); diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds index 6abf3f390..a17401af9 100644 --- a/board/sandburst/metrobox/u-boot.lds +++ b/board/sandburst/metrobox/u-boot.lds @@ -23,6 +23,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -44,11 +45,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -71,7 +72,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -146,7 +147,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index 527c26432..fef4c4220 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -23,6 +23,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -34,11 +35,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -61,7 +62,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sandpoint/Makefile b/board/sandpoint/Makefile index cf07cf40f..d6bbf2f29 100644 --- a/board/sandpoint/Makefile +++ b/board/sandpoint/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c index 7429647b8..d3445bd92 100644 --- a/board/sandpoint/sandpoint.c +++ b/board/sandpoint/sandpoint.c @@ -40,7 +40,7 @@ int checkboard (void) return 0; } -#if 0 /* NOT USED */ +#if 0 /* NOT USED */ int checkflash (void) { /* TODO: XXX XXX XXX */ @@ -50,7 +50,7 @@ int checkflash (void) } #endif -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long size; long new_bank0_end; diff --git a/board/sandpoint/speed.h b/board/sandpoint/speed.h index 3f32a143c..b66393bec 100644 --- a/board/sandpoint/speed.h +++ b/board/sandpoint/speed.h @@ -28,10 +28,10 @@ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 * * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock + * GCLK CPU clock * SPEED_TMR2_PS prescaler */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ /*----------------------------------------------------------------------- * Timer value for PIT diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds new file mode 100644 index 000000000..2a5cd2ebd --- /dev/null +++ b/board/sandpoint/u-boot.lds @@ -0,0 +1,133 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/santiago/Makefile b/board/santiago/Makefile new file mode 100644 index 000000000..3f92cecba --- /dev/null +++ b/board/santiago/Makefile @@ -0,0 +1,76 @@ +# +# (C) Copyright 2009 Texas Instruments. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +COMMONDIR = ../tomtom/common +PLATDIR = ../tomtom/plat-omap3 + +LIB = lib$(BOARD).a + +# Boot shell scripts +USHOBJS := bootcmd.o altbootcmd.o preboot.o preboot_plat.o + +# U-Boot 1.1.4 build system sucks :P +ifeq (,$(shell fgrep -q 'CONFIG_DEBUG_BUILD' \ + $(TOPDIR)/include/`sed -ne 's|.*<\(.*\)>.*|\1|p' $(TOPDIR)/include/config.h` \ + 2>/dev/null || echo x)) +USHOBJS += bootcmd_debug.o altbootcmd_debug.o preboot_debug.o +endif + +OBJS := \ + santiago.o \ + sys_info.o \ + +OBJS += $(COMMONDIR)/bootcount.o $(COMMONDIR)/env_init.o +OBJS += $(PLATDIR)/boot_mode.o $(PLATDIR)/flipflop.o $(PLATDIR)/watchdog.o + +$(LIB): $(OBJS) $(USHOBJS) + $(AR) crv $@ $^ + +%.o: %.image + cd $( $@ + +-include .depend + +######################################################################### diff --git a/board/santiago/altbootcmd.ush b/board/santiago/altbootcmd.ush new file mode 100644 index 000000000..5fdcaaa32 --- /dev/null +++ b/board/santiago/altbootcmd.ush @@ -0,0 +1,2 @@ +flipflop 1 +bootm ${kernel.rescue.addr} diff --git a/board/santiago/altbootcmd_debug.ush b/board/santiago/altbootcmd_debug.ush new file mode 100644 index 000000000..986728dc0 --- /dev/null +++ b/board/santiago/altbootcmd_debug.ush @@ -0,0 +1,4 @@ +mw.l ${fdaddr} 0xdeadbeef 0x80 +ignore fatload ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${fdaddr} /altbootcmd.image +ignore autoscr ${fdaddr} +run altbootcmd.default diff --git a/board/santiago/bootcmd.ush b/board/santiago/bootcmd.ush new file mode 100644 index 000000000..4a5ed5798 --- /dev/null +++ b/board/santiago/bootcmd.ush @@ -0,0 +1,4 @@ +mw.l ${loadaddr} 0xdeadbeef 0x80 +echo Reading kernel from ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${bootfile} +ext2load ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${loadaddr} ${bootfile} ${kernel.maxsize} +bootm diff --git a/board/santiago/bootcmd_debug.ush b/board/santiago/bootcmd_debug.ush new file mode 100644 index 000000000..a957ba24c --- /dev/null +++ b/board/santiago/bootcmd_debug.ush @@ -0,0 +1,4 @@ +mw.l ${fdaddr} 0xdeadbeef 0x80 +ignore fatload ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${fdaddr} /bootcmd.image +ignore autoscr ${fdaddr} +run bootcmd.default diff --git a/board/santiago/config.mk b/board/santiago/config.mk new file mode 100644 index 000000000..a351e42c5 --- /dev/null +++ b/board/santiago/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x80200000 diff --git a/board/santiago/preboot.ush b/board/santiago/preboot.ush new file mode 100644 index 000000000..b6743f857 --- /dev/null +++ b/board/santiago/preboot.ush @@ -0,0 +1,19 @@ +run preboot_plat +setenv appletname /preboot-app.bin +setenv autoscript no +setenv bootfile /uImage +setenv conf.file /uboot.conf +setenv conf.maxsize 0x80 +setenv flash.part.bootfs /dev/mmcblk${kernel.bootdev}p${flash.part.bootfs.num} +setenv flash.part.rootfs /dev/mmcblk${kernel.bootdev}p${flash.part.rootfs.num} +setenv kernel.root.options rootwait +setenv kernel.console.options ${baudrate} +setenv kernel.extrabootargs +setenv timeout 2 +setenv verify no +setenv no_trybooty no +setenv bootargs root=${flash.part.rootfs} ${kernel.root.options} console=${kernel.console},${kernel.console.options} ${kernel.extrabootargs} androidboot.console=${kernel.console} sysboot_mode=${sysboot_mode} init=/init omapfb.vram="0:4M" omapfb.rotate=1 omapfb.vrfb=y +mmcinit ${bootdev} +mw.w ${fdaddr} 0x00000000 ${conf.maxsize} +ignore fatload ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${fdaddr} /uboot.conf ${conf.maxsize} +ignore bootconf ${fdaddr} diff --git a/board/santiago/preboot_debug.ush b/board/santiago/preboot_debug.ush new file mode 100644 index 000000000..60b38ce7b --- /dev/null +++ b/board/santiago/preboot_debug.ush @@ -0,0 +1,8 @@ +run preboot.default +setenv verify yes +setenv kernel.bricknum 0 +setenv kernel.bricknum.rescue 0 +setenv kernel.quiet +mw.l ${fdaddr} 0xdeadbeef 0x80 +fatload ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${fdaddr} /preboot.image +autoscr ${fdaddr} diff --git a/board/santiago/preboot_plat.ush b/board/santiago/preboot_plat.ush new file mode 100644 index 000000000..5f6d5c3b4 --- /dev/null +++ b/board/santiago/preboot_plat.ush @@ -0,0 +1,9 @@ +setenv bootdev 0 +setenv bootdev.class mmc +setenv flash.part.bootfs.num 4 +setenv flash.part.rootfs.num 4 +setenv kernel.bootdev ${bootdev} +setenv force_altboot no +setenv kernel.bricknum 0 +setenv kernel.bricknum.rescue 0 +setenv kernel.rescue.addr 0x08040000 diff --git a/board/santiago/santiago.c b/board/santiago/santiago.c new file mode 100644 index 000000000..9b45d65c5 --- /dev/null +++ b/board/santiago/santiago.c @@ -0,0 +1,463 @@ + +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Before including the padconfig settings, we have to set proper config */ +#define BOOTLOADER_UBOOT_PADCONFIG +#ifdef SIMSANTIAGO +#include +#else +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +extern void detect_boot_mode(void); +extern void hw_watchdog_init(void); + +int get_boot_type(void); +void v7_flush_dcache_all(int, int); +void l2cache_enable(void); +void setup_auxcr(int, int); +void eth_init(void *); + +int bootdev; + +# define BOOTDEV_SDCARD 0 +# define BOOTDEV_MOVI 1 + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + detect_boot_mode(); + + bootdev = BOOTDEV_MOVI; + + if (SYSBOOT_MODE_COLD == gd->tomtom.sysboot_mode) + /* cold boot => initialize the flipflop, we can't rely on the + state of the scratchpad register */ + flipflop_set(0); + + if ((__raw_readl(0x480029c0) & 0xff) == 0x6) { /* Booted SD slot? */ + bootdev = BOOTDEV_SDCARD; + } + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + gd->bd->bi_arch_number = MACH_TYPE_SANTIAGO; /* Linux mach id */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */ + + return 0; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_1); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_2); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_3); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + + +/********************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world + * general use. + ***********************************************************/ +void secureworld_exit(void) +{ + unsigned long i; + + /* configrue non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r" (i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); + /* allow allocation of locked TLBs and L2 lines in NS world */ + /* allow use of PLE registers in NS world also */ + __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r" (i)); + + /* Enable ASA and IBE in ACR register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x50":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r" (i)); +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + int in_sdram = running_in_sdram(); + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock_mem(); + } + /* If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ +void s_init(void) +{ + int i; + int external_boot = 0; + int in_sdram = running_in_sdram(); + +#ifdef CONFIG_3430VIRTIO + in_sdram = 0; /* allow setup from memory for Virtio */ +#endif + +#ifdef CONFIG_HW_WATCHDOG + hw_watchdog_init(); +#endif + + external_boot = (get_boot_type() == 0x1F) ? 1 : 0; + /* Right now flushing at low MPU speed. Need to move after clock init */ + v7_flush_dcache_all(get_device_type(), external_boot); + + try_unlock_memory(); + +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5A80, CONTROL_SCALABLE_OMAP_OCP); +#endif + + if (cpu_is_3410()) { + /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ + __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); + } + +#ifndef CONFIG_ICACHE_OFF + icache_enable(); +#endif + +#ifdef CONFIG_L2_OFF + l2cache_disable(); +#else + l2cache_enable(); +#endif + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + setup_auxcr(get_device_type(), external_boot); + + prcm_init(); + + per_clocks_enable(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + unsigned char data; + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + twl4030_usb_init(); + + /* see if we need to activate the power button startup */ + char *s = getenv("pbboot"); + if (s) { + /* figure out why we have booted */ + i2c_read(0x4b, 0x3a, 1, &data, 1); + + /* if status is non-zero, we didn't transition + * from WAIT_ON state + */ + if (data) { + printf("Transitioning to Wait State (%x)\n", data); + + /* clear status */ + data = 0; + i2c_write(0x4b, 0x3a, 1, &data, 1); + + /* put PM into WAIT_ON state */ + data = 0x01; + i2c_write(0x4b, 0x46, 1, &data, 1); + + /* no return - wait for power shutdown */ + while (1) {;} + } + printf("Transitioning to Active State (%x)\n", data); + + /* turn on long pwr button press reset*/ + data = 0x40; + i2c_write(0x4b, 0x46, 1, &data, 1); + printf("Power Button Active\n"); + } +#endif + dieid_num_r(); + return (0); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + #define NOT_EARLY 0 + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0; + u32 mtype, btype; + + btype = get_board_type(); + mtype = get_mem_type(); +#ifndef CONFIG_3430ZEBU + /* fixme... dont know why this func is crashing in ZeBu */ + display_board_info(btype); +#endif + /* If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + + return 0; +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT_ES2()\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (IEN | PTD | EN | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 unused*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + PADCONFIG_SETTINGS_UBOOT + PADCONFIG_SETTINGS_COMMON + MUX_DEFAULT_ES2(); +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} + +void board_env_init() +{ + char console[6]; + + sprintf(console, "ttyO%d", CONFIG_CONS_INDEX - 1); + setenv("kernel.console", console); +} diff --git a/board/santiago/sys_info.c b/board/santiago/sys_info.c new file mode 100644 index 000000000..ea63104af --- /dev/null +++ b/board/santiago/sys_info.c @@ -0,0 +1,377 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include +#include + +/************************************************************************** + * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch + * settings + * 1 is on + * 0 is off + * Will return Index of type of gpmc + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ + u8 cs; + + if(get_board_type() == SDP_3430_V2) + /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */ + cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | + ((cs & 2) << 1) | ((cs & 1) << 3); + else + /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */ + cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2); + return (cs); +} + +/**************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + ****************************************************/ +u32 get_cpu_type(void) +{ + // fixme, need to get register defines for 3430 + return (CPU_3430); +} + +/* + * cpu_is_3410(void) - returns true for 3410 + */ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3XX_ES20) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* + * Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == SDP_SDRC_MR_0_SDR) + return (1); + return (0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + ***********************************************************/ +u32 get_mem_type(void) +{ + /* Current SDP3430 uses 2x16 MDDR Infenion parts */ + return (DDR_DISCRETE); +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/* + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + */ +u32 get_board_type(void) +{ + if (get_cpu_rev() >= CPU_3XX_ES20) + return SDP_3430_V2; + else + return SDP_3430_V1; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return (0x0000003F & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return (WIDTH_16BIT); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +u32 get_board_rev(void) +{ + /* Currently reading EEPROM reg to get UI board version and try it out + */ +#if 0 + if (!check_uieeprom_avail()) { + /* timed out OR fpga rev not found!! */ + /* Assume 1.0 */ + return 0x01; + } + /* Move ahead to name location */ + ui_brd_name += 0x08; + count = sizeof(enhanced_ui_brd_name) - 2; + while ((enhanced_ui_brd_name[count] == ui_brd_name[count]) && count) { + count--; + } + /* Match?? */ + if (!count) { + /* Enhanced UI board.. SDP1.1 */ + return 0x11; + } +#endif + /* Legacy UI - hope they are all 1.0 boards.. */ + return (0x10); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + enum { + BOOTMODE_NOR, + BOOTMODE_ONND, + BOOTMODE_NAND, + BOOTMODE_MMC + }; + + char *bootmode[] = { + "NOR", + "ONND", + "NAND", + "MMC" + }; + u32 brev = get_board_rev(); + char cpu_3430s[] = "3630"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; +#ifdef CONFIG_LED_INFO + char led_string[CONFIG_LED_LEN] = { 0 }; +#endif + +#if defined(L3_200MHZ) + char p_l3[] = "200"; +#elif defined(L3_165MHZ) + char p_l3[] = "165"; +#elif defined(L3_110MHZ) + char p_l3[] = "110"; +#elif defined(L3_133MHZ) + char p_l3[] = "133"; +#elif defined(L3_100MHZ) + char p_l3[] = "100"; +#endif + +#if defined(PRCM_PCLK_OPP1) + char p_cpu[] = "1"; +#elif defined(PRCM_PCLK_OPP2) + char p_cpu[] = "2"; +#elif defined(PRCM_PCLK_OPP3) + char p_cpu[] = "3"; +#elif defined(PRCM_PCLK_OPP4) + char p_cpu[] = "4"; +#endif + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + cpu_s = cpu_3430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev, + p_cpu, p_l3); + printf("OMAP3630 Santiago %s Version + %s (Boot %s)\n", db_s, + mem_s, bootmode[BOOTMODE_MMC]); +#ifdef CONFIG_LED_INFO + /* Format: 0123456789ABCDEF + * 3430C GP L3-100 NAND + */ + sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, p_l3, + bootmode[2]); + /* reuse sec */ + for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) { + /* invert byte loc */ + u16 val = led_string[sec] << 8; + val |= led_string[sec + 1]; + __raw_writew(val, LED_REGISTER + sec); + } +#endif + +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * sdram. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 sys mem/perif + ***************************************************************/ +u32 get_boot_type(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return (mode >>= 8); +} diff --git a/board/santiago/u-boot.lds b/board/santiago/u-boot.lds new file mode 100644 index 000000000..a810db903 --- /dev/null +++ b/board/santiago/u-boot.lds @@ -0,0 +1,83 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .bootscript : { *(.bootscript) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + . = ALIGN(4); + _end = .; + + . = 0x81000000; + /* NOBITS section to contain the FDT */ + .fdt . (COPY) : + { + __fdt_start = .; + . = . + 128K; /* Max FDT len is 128K */ + __fdt_end = .; + } + + . = ALIGN(128); + /* NOBITS section to contain the kernel */ + .kern . (COPY) : + { + __kern_start = .; + . = . + 4M; + __kern_end = .; + } + + . = ALIGN(4); +} + diff --git a/board/sbc2410x/Makefile b/board/sbc2410x/Makefile index 95f2ad120..ae8665ec3 100644 --- a/board/sbc2410x/Makefile +++ b/board/sbc2410x/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := sbc2410x.o flash.o +OBJS := sbc2410x.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/sbc2410x/flash.c b/board/sbc2410x/flash.c index 0c669e4d7..f2718f256 100644 --- a/board/sbc2410x/flash.c +++ b/board/sbc2410x/flash.c @@ -288,7 +288,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) * Copy memory to flash */ -static int write_hword (flash_info_t * info, ulong dest, ushort data) +volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) { vu_short *addr = (vu_short *) dest; ushort result; diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index 6c894a386..7030985b2 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -31,11 +31,11 @@ #include #include -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include #endif -DECLARE_GLOBAL_DATA_PTR; +/* ------------------------------------------------------------------------- */ #define FCLK_SPEED 1 @@ -74,6 +74,7 @@ static inline void delay (unsigned long loops) int board_init (void) { + DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); @@ -127,13 +128,15 @@ int board_init (void) int dram_init (void) { + DECLARE_GLOBAL_DATA_PTR; + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; return 0; } -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) extern ulong nand_probe(ulong physadr); static inline void NF_Reset(void) @@ -177,4 +180,4 @@ void nand_init(void) #endif printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ diff --git a/board/sbc2410x/u-boot.lds b/board/sbc2410x/u-boot.lds index 3b7977672..76df6b2af 100644 --- a/board/sbc2410x/u-boot.lds +++ b/board/sbc2410x/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/sbc405/Makefile b/board/sbc405/Makefile index 1c60447e8..c4198c4fc 100644 --- a/board/sbc405/Makefile +++ b/board/sbc405/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o strataflash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS = $(BOARD).o strataflash.o $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c index 7818cd7e5..0ae6d0ba4 100644 --- a/board/sbc405/sbc405.c +++ b/board/sbc405/sbc405.c @@ -96,7 +96,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return spd_sdram (); } diff --git a/board/sbc405/u-boot.lds b/board/sbc405/u-boot.lds index 7b1c6b211..39fba6168 100644 --- a/board/sbc405/u-boot.lds +++ b/board/sbc405/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -63,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -137,7 +138,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/sbc8240/Makefile b/board/sbc8240/Makefile index dcb190703..7a2014d46 100644 --- a/board/sbc8240/Makefile +++ b/board/sbc8240/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/sbc8240/sbc8240.c b/board/sbc8240/sbc8240.c index 175720d90..8a52f6741 100644 --- a/board/sbc8240/sbc8240.c +++ b/board/sbc8240/sbc8240.c @@ -45,7 +45,7 @@ int checkboard (void) return 0; } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { long size; long new_bank0_end; diff --git a/board/sbc8240/u-boot.lds b/board/sbc8240/u-boot.lds new file mode 100644 index 000000000..7be85e441 --- /dev/null +++ b/board/sbc8240/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sbc8260/Makefile b/board/sbc8260/Makefile index 034a55169..14ed45711 100644 --- a/board/sbc8260/Makefile +++ b/board/sbc8260/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := sbc8260.o flash.o +OBJS := sbc8260.o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/sbc8260/sbc8260.c b/board/sbc8260/sbc8260.c index 5781f6281..48aefa010 100644 --- a/board/sbc8260/sbc8260.c +++ b/board/sbc8260/sbc8260.c @@ -208,7 +208,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/sbc8260/u-boot.lds b/board/sbc8260/u-boot.lds new file mode 100644 index 000000000..9e623d0b9 --- /dev/null +++ b/board/sbc8260/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sbc8560/Makefile b/board/sbc8560/Makefile index bb96d95a3..da295fbdf 100644 --- a/board/sbc8560/Makefile +++ b/board/sbc8560/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2004-2006 +# (C) Copyright 2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2004 Wind River Systems Inc . @@ -26,28 +26,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o law.o tlb.o +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/sbc8560/init.S b/board/sbc8560/init.S new file mode 100644 index 000000000..3d8d180d8 --- /dev/null +++ b/board/sbc8560/init.S @@ -0,0 +1,165 @@ +/* +* Copyright (C) 2002,2003, Motorola Inc. +* Xianghua Xiao +* +* (C) Copyright 2004 Wind River Systems Inc . +* Added support for Wind River SBC8560 board +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include +#include + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + +/* LAW(Local Access Window) configuration: + * 0000_0000-0800_0000: DDR(512M) -or- larger + * c000_0000-cfff_ffff: PCI(256M) + * d000_0000-dfff_ffff: RapidIO(256M) + * e000_0000-ffff_ffff: localbus(512M) + * e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6 + * e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1 + * e800_0000-efff_ffff: LBC 128M, nothing here + * f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3 + * f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4 + * f800_0000-fdff_ffff: LBC 64M, nothing here + * fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5 + * fd00_0000-fdff_ffff: LBC 16M, nothing here + * fe00_0000-feff_ffff: LBC 16M, nothing here + * ff00_0000-ff6f_ffff: LBC 7M, nothing here + * ff70_0000-ff7f_ffff: CCSRBAR 1M + * ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0 + * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access + * Window. + * Note: If flash is 8M at default position(last 8M),no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) + #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) + #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) +#else + #define LAWBAR0 0 + #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR2 ((0xe0000000>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x03 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 + entry_end + +/* TLB1 entries configuration: */ + + .section .bootpg, "ax" + .globl tlb1_entry + +tlb1_entry: + entry_start + + .long 0x08 /* the following data table uses a few of 16 TLB entries */ + +/* TLB for CCSRBAR (IMMR) */ + + .long TLB1_MAS0(1,1,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + +/* TLB for Local Bus stuff, just map the whole 512M */ +/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ + + .long TLB1_MAS0(1,2,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((0xe0000000>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((0xe0000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,3,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((0xf0000000>>12)&0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((0xf0000000>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + .long TLB1_MAS0(1,4,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,5,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) +#else + .long TLB1_MAS0(1,4,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,5,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) +#endif + + .long TLB1_MAS0(1,6,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) +#ifdef CONFIG_L2_INIT_RAM + .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) +#else + .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) +#endif + .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,7,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + .long TLB1_MAS0(1,15,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) +#else + .long TLB1_MAS0(1,15,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) +#endif + entry_end diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index d9e598c29..e8b9929e7 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -27,14 +27,14 @@ */ +extern long int spd_sdram (void); + #include #include #include #include -#include +#include #include -#include -#include long int fixed_sdram (void); @@ -195,7 +195,8 @@ const iop_conf_t iop_conf_tab[4][32] = { int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; pci->peer &= 0xfffffffdf; /* disable master abort */ #endif @@ -259,19 +260,20 @@ int checkboard (void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long dram_size = 0; - + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; #if 0 #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc= &immap->im_lbc; sys_info_t sysinfo; uint temp_lbcdll = 0; #endif #endif /* 0 */ #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur= &immap->im_gur; #endif #if defined(CONFIG_DDR_DLL) uint temp_ddrdll = 0; @@ -334,7 +336,8 @@ phys_size_t initdram (int board_type) * enable errors */ uint *p = 0; uint i = 0; - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } @@ -421,13 +424,10 @@ long int fixed_sdram (void) #define CFG_DDR_CONTROL 0xc2000000 #ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; -#if (CFG_SDRAM_SIZE == 512) - ddr->cs0_bnds = 0x0000000f; -#else ddr->cs0_bnds = 0x00000007; -#endif ddr->cs1_bnds = 0x0010001f; ddr->cs2_bnds = 0x00000000; ddr->cs3_bnds = 0x00000000; @@ -458,29 +458,3 @@ long int fixed_sdram (void) return CFG_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ - - -#if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - int node, tmp[2]; -#ifdef CONFIG_PCI - const char *path; -#endif - - ft_cpu_setup(blob, bd); - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { -#ifdef CONFIG_PCI - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = hose.last_busno - hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } -} -#endif diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds index ba5ce0bd6..48e19fe2a 100644 --- a/board/sbc8560/u-boot.lds +++ b/board/sbc8560/u-boot.lds @@ -25,6 +25,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -37,6 +38,7 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) + board/sbc8560/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -46,11 +48,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -66,6 +68,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) + board/sbc8560/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) @@ -74,6 +77,7 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/i2c.o (.text) cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) @@ -141,7 +145,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/sc520_cdp/Makefile b/board/sc520_cdp/Makefile index 0d2800d5e..ab06ebc81 100644 --- a/board/sc520_cdp/Makefile +++ b/board/sc520_cdp/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. # @@ -26,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := sc520_cdp.o flash.o +OBJS := sc520_cdp.o flash.o SOBJS := sc520_cdp_asm.o sc520_cdp_asm16.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c index 8050aa6fe..b6add59bb 100644 --- a/board/sc520_cdp/sc520_cdp.c +++ b/board/sc520_cdp/sc520_cdp.c @@ -233,9 +233,9 @@ static void bus_init(void) { /* set up the GP IO pins */ - write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */ - write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */ + write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */ write_mmcr_byte(SC520_CLKSEL, 0x70); @@ -507,7 +507,6 @@ int dram_init(void) void show_boot_progress(int val) { - if (val < -32) val = -1; /* let things compatible */ outb(val&0xff, 0x80); outb((val&0xff00)>>8, 0x680); } diff --git a/board/sc520_cdp/sc520_cdp_asm.S b/board/sc520_cdp/sc520_cdp_asm.S index 6ac5a5de9..be7b2bb48 100644 --- a/board/sc520_cdp/sc520_cdp_asm.S +++ b/board/sc520_cdp/sc520_cdp_asm.S @@ -73,11 +73,11 @@ done: movb $0x88, %al movw $0x680, %dx out %al, %dx - jmp *%ebp /* return to caller */ + jmp *%ebp /* return to caller */ -.globl show_boot_progress -show_boot_progress: +.globl __show_boot_progress +__show_boot_progress: out %al, $0x80 xchg %al, %ah movw $0x680, %dx diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds index 96093263e..72164a1c8 100644 --- a/board/sc520_cdp/u-boot.lds +++ b/board/sc520_cdp/u-boot.lds @@ -33,7 +33,7 @@ SECTIONS . = ALIGN(4); .rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) } - . = 0x400000; /* Ram data segment to use */ + . = 0x400000; /* Ram data segment to use */ _i386boot_romdata_dest = ABSOLUTE(.); .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } _i386boot_romdata_start = LOADADDR(.data); @@ -45,7 +45,7 @@ SECTIONS . = ALIGN(4); _i386boot_bss_start = ABSOLUTE(.); - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _i386boot_bss_size = SIZEOF(.bss); diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile index e04172e3b..242d53c42 100644 --- a/board/sc520_spunk/Makefile +++ b/board/sc520_spunk/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. # @@ -26,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := sc520_spunk.o flash.o +OBJS := sc520_spunk.o flash.o SOBJS := sc520_spunk_asm.o sc520_spunk_asm16.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/sc520_spunk/flash.c b/board/sc520_spunk/flash.c index 0b4bf6889..4942e598d 100644 --- a/board/sc520_spunk/flash.c +++ b/board/sc520_spunk/flash.c @@ -33,6 +33,7 @@ #define PROBE_BUFFER_SIZE 1024 static unsigned char buffer[PROBE_BUFFER_SIZE]; + #define SC520_MAX_FLASH_BANKS 1 #define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */ #define SC520_FLASH_BANKSIZE 0x8000000 @@ -61,6 +62,7 @@ flash_info_t flash_info[SC520_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- */ + static u32 _probe_flash(u32 addr, u32 bw, int il) { u32 result=0; @@ -178,6 +180,7 @@ static u32 _probe_flash(u32 addr, u32 bw, int il) break; } + return result; } @@ -212,9 +215,11 @@ static int identify_flash(unsigned address, int width) enable_interrupts(); } + vendor = res >> 16; device = res & 0xffff; + return res; } @@ -380,6 +385,7 @@ void flash_print_info(flash_info_t *info) break; } + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); @@ -393,13 +399,13 @@ void flash_print_info(flash_info_t *info) } printf ("\n"); -done: - return; + done: } /*----------------------------------------------------------------------- */ + static u32 _amd_erase_flash(u32 addr, u32 sector) { unsigned elapsed; @@ -461,6 +467,7 @@ static u32 _intel_erase_flash(u32 addr, u32 sector) *(volatile u16*)(addr + sector) = 0x0020; /* erase setup */ *(volatile u16*)(addr + sector) = 0x00D0; /* erase confirm */ + /* Wait at least 80us - let's wait 1 ms */ __udelay(1000); @@ -479,6 +486,7 @@ static u32 _intel_erase_flash(u32 addr, u32 sector) return 0; } + extern int _intel_erase_flash_end; asm ("_intel_erase_flash_end:\n" ".long 0\n"); @@ -540,6 +548,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) printf ("\n"); } + /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { @@ -557,6 +566,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) enable_interrupts(); } + if (res) { printf("Erase timed out, sector %d\n", sect); return res; @@ -566,6 +576,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) } } + return 0; } @@ -575,11 +586,11 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) * 1 - write timeout * 2 - Flash not erased */ -static int _amd_write_word(unsigned start, unsigned dest, u16 data) +static int _amd_write_word(unsigned start, unsigned dest, unsigned data) { - volatile u16 *addr2 = (volatile u16*)start; - volatile u16 *dest2 = (volatile u16*)dest; - volatile u16 *data2 = (volatile u16*)&data; + volatile u16 *addr2 = (u16*)start; + volatile u16 *dest2 = (u16*)dest; + volatile u16 *data2 = (u16*)&data; int i; unsigned elapsed; @@ -590,6 +601,7 @@ static int _amd_write_word(unsigned start, unsigned dest, u16 data) for (i = 0; i < 2; i++) { + addr2[0x5555] = 0x00AA; addr2[0x2aaa] = 0x0055; addr2[0x5555] = 0x00A0; @@ -618,6 +630,7 @@ extern int _amd_write_word_end; asm ("_amd_write_word_end:\n" ".long 0\n"); + static int _intel_write_word(unsigned start, unsigned dest, unsigned data) { int i; @@ -650,12 +663,14 @@ static int _intel_write_word(unsigned start, unsigned dest, unsigned data) return 0; + } extern int _intel_write_word_end; asm ("_intel_write_word_end:\n" ".long 0\n"); + /*----------------------------------------------------------------------- * Copy memory to flash, returns: * 0 - OK @@ -700,8 +715,10 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) return 3; } + wp = (addr & ~3); /* get lower word aligned address */ + /* * handle unaligned start bytes */ @@ -788,4 +805,5 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) } return rc; + } diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c index 038d47995..ed226fd64 100644 --- a/board/sc520_spunk/sc520_spunk.c +++ b/board/sc520_spunk/sc520_spunk.c @@ -256,11 +256,11 @@ static void bus_init(void) if (version) { /* set up the GP IO pins (for the Spunk board) */ - write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); /* set the GPIO pin function 31-16 reg */ - write_mmcr_word(SC520_PIOPFS15_0, 0x000f); /* set the GPIO pin function 15-0 reg */ - write_mmcr_word(SC520_PIODIR31_16, 0x000f); /* set the GPIO direction 31-16 reg */ - write_mmcr_word(SC520_PIODIR15_0, 0x1ff0); /* set the GPIO direction 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0xc0); /* set the CS pin function reg */ + write_mmcr_word(SC520_PIOPFS31_16, 0xfff0); /* set the GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0x000f); /* set the GPIO pin function 15-0 reg */ + write_mmcr_word(SC520_PIODIR31_16, 0x000f); /* set the GPIO direction 31-16 reg */ + write_mmcr_word(SC520_PIODIR15_0, 0x1ff0); /* set the GPIO direction 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0xc0); /* set the CS pin function reg */ write_mmcr_byte(SC520_CLKSEL, 0x70); write_mmcr_word(SC520_PIOCLR31_16, 0x0003); /* reset SSI chip-selects */ @@ -268,11 +268,11 @@ static void bus_init(void) } else { /* set up the GP IO pins (for the Hyglo board) */ - write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); /* set the GPIO pin function 31-16 reg */ - write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f); /* set the GPIO pin function 15-0 reg */ - write_mmcr_word(SC520_PIODIR31_16, 0x003f); /* set the GPIO direction 31-16 reg */ - write_mmcr_word(SC520_PIODIR15_0, 0xe180); /* set the GPIO direction 15-0 reg */ - write_mmcr_byte(SC520_CSPFS, 0x00); /* set the CS pin function reg */ + write_mmcr_word(SC520_PIOPFS31_16, 0xffc0); /* set the GPIO pin function 31-16 reg */ + write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f); /* set the GPIO pin function 15-0 reg */ + write_mmcr_word(SC520_PIODIR31_16, 0x003f); /* set the GPIO direction 31-16 reg */ + write_mmcr_word(SC520_PIODIR15_0, 0xe180); /* set the GPIO direction 15-0 reg */ + write_mmcr_byte(SC520_CSPFS, 0x00); /* set the CS pin function reg */ write_mmcr_byte(SC520_CLKSEL, 0x70); write_mmcr_word(SC520_PIOCLR15_0, 0x0180); /* reset SSI chip-selects */ @@ -507,7 +507,6 @@ void show_boot_progress(int val) { int version = read_mmcr_byte(SC520_SYSINFO); - if (val < -32) val = -1; /* let things compatible */ if (version == 0) { /* PIO31-PIO16 Data */ write_mmcr_word(SC520_PIODATA31_16, @@ -656,7 +655,7 @@ ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) offset |= addr[i]; } - return read_mmcr_byte(SC520_SYSINFO) ? + return read_mmcr_byte(SC520_SYSINFO) ? spi_eeprom_read(1, offset, buffer, len) : mw_eeprom_read(1, offset, buffer, len); } @@ -672,7 +671,7 @@ ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) offset |= addr[i]; } - return read_mmcr_byte(SC520_SYSINFO) ? + return read_mmcr_byte(SC520_SYSINFO) ? spi_eeprom_write(1, offset, buffer, len) : mw_eeprom_write(1, offset, buffer, len); } diff --git a/board/sc520_spunk/sc520_spunk_asm.S b/board/sc520_spunk/sc520_spunk_asm.S index 3430b6adb..8b3410399 100644 --- a/board/sc520_spunk/sc520_spunk_asm.S +++ b/board/sc520_spunk/sc520_spunk_asm.S @@ -70,11 +70,11 @@ next: addl $8, %esi /* advance esi */ done: movl $0xfffefc32,%edx movw $0000,(%edx) - jmp *%ebp /* return to caller */ + jmp *%ebp /* return to caller */ -.globl show_boot_progress -show_boot_progress: +.globl __show_boot_progress +__show_boot_progress: movl $0xfffefc32,%edx xorw $0xffff, %ax movw %ax,(%edx) diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds index 33480d328..127d707e6 100644 --- a/board/sc520_spunk/u-boot.lds +++ b/board/sc520_spunk/u-boot.lds @@ -34,7 +34,7 @@ SECTIONS . = ALIGN(4); .rodata : { *(.rodata) } - . = 0x400000; /* Ram data segment to use */ + . = 0x400000; /* Ram data segment to use */ _i386boot_romdata_dest = ABSOLUTE(.); .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) } _i386boot_romdata_start = LOADADDR(.data); @@ -46,7 +46,7 @@ SECTIONS . = ALIGN(4); _i386boot_bss_start = ABSOLUTE(.); - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _i386boot_bss_size = SIZEOF(.bss); diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile index 3bac4776d..5dc3fd4e4 100644 --- a/board/scb9328/Makefile +++ b/board/scb9328/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := scb9328.o flash.o +OBJS := scb9328.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c index 304190cbf..1b56f8c6a 100644 --- a/board/scb9328/flash.c +++ b/board/scb9328/flash.c @@ -44,7 +44,6 @@ #if ( SCB9328_FLASH_BUS_WIDTH == 1 ) # define FLASH_BUS vu_char -# define FLASH_BUS_RET u_char # if ( SCB9328_FLASH_INTERLEAVE == 1 ) # define FLASH_CMD( x ) x # else @@ -54,7 +53,6 @@ #elif ( SCB9328_FLASH_BUS_WIDTH == 2 ) # define FLASH_BUS vu_short -# define FLASH_BUS_RET u_short # if ( SCB9328_FLASH_INTERLEAVE == 1 ) # define FLASH_CMD( x ) x # elif ( SCB9328_FLASH_INTERLEAVE == 2 ) @@ -66,7 +64,6 @@ #elif ( SCB9328_FLASH_BUS_WIDTH == 4 ) # define FLASH_BUS vu_long -# define FLASH_BUS_RET u_long # if ( SCB9328_FLASH_INTERLEAVE == 1 ) # define FLASH_CMD( x ) x # elif ( SCB9328_FLASH_INTERLEAVE == 2 ) @@ -84,7 +81,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -static FLASH_BUS_RET flash_status_reg (void) +static FLASH_BUS flash_status_reg (void) { FLASH_BUS *addr = (FLASH_BUS *) 0; diff --git a/board/scb9328/u-boot.lds b/board/scb9328/u-boot.lds index 46ed451ee..1d1669cde 100644 --- a/board/scb9328/u-boot.lds +++ b/board/scb9328/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/shannon/Makefile b/board/shannon/Makefile index 16ed4cf41..f66b096a4 100644 --- a/board/shannon/Makefile +++ b/board/shannon/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := shannon.o flash.o +OBJS := shannon.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/shannon/u-boot.lds b/board/shannon/u-boot.lds index 6bd06270a..258bece23 100644 --- a/board/shannon/u-boot.lds +++ b/board/shannon/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/siemens/CCM/Makefile b/board/siemens/CCM/Makefile index c5695f98c..ee2fc53bb 100644 --- a/board/siemens/CCM/Makefile +++ b/board/siemens/CCM/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,34 +23,19 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../../tqc/tqm8xx) -endif +LIB = lib$(BOARD).a -LIB = $(obj)lib$(BOARD).a +OBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \ + ../../tqm8xx/load_sernum_ethaddr.o -COBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \ - ../../tqc/tqm8xx/load_sernum_ethaddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c index d65376328..5a32e45e2 100644 --- a/board/siemens/CCM/ccm.c +++ b/board/siemens/CCM/ccm.c @@ -155,7 +155,7 @@ static void init_leds (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds index 10b38ec35..cdf550f67 100644 --- a/board/siemens/CCM/u-boot.lds +++ b/board/siemens/CCM/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug index bf6399197..3b50272ea 100644 --- a/board/siemens/CCM/u-boot.lds.debug +++ b/board/siemens/CCM/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c index 9c0ff0278..e498937b6 100644 --- a/board/siemens/IAD210/IAD210.c +++ b/board/siemens/IAD210/IAD210.c @@ -100,7 +100,7 @@ const uint sdram_table[] = { /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/siemens/IAD210/Makefile b/board/siemens/IAD210/Makefile index aa1510e1c..87a689372 100644 --- a/board/siemens/IAD210/Makefile +++ b/board/siemens/IAD210/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o atm.o +OBJS = $(BOARD).o flash.o atm.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c index 1b27f336b..c77e35912 100644 --- a/board/siemens/IAD210/atm.c +++ b/board/siemens/IAD210/atm.c @@ -1,3 +1,4 @@ + #include #include #include @@ -6,7 +7,7 @@ #include #define SYNC __asm__("sync") -#define MY_ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1))) +#define ALIGN(p, a) ((char *)(((uint32)(p)+(a)-1) & ~((uint32)(a)-1))) #define FALSE 1 #define TRUE 0 @@ -159,7 +160,7 @@ int atmMemInit() g_atm.csram = &csram[0]; memset(&(g_atm.csram), 0x00, g_atm.csram_size); - g_atm.int_reload_ptr = (uint32 *)MY_ALIGN(g_atm.csram, 4); + g_atm.int_reload_ptr = (uint32 *)ALIGN(g_atm.csram, 4); g_atm.rbd_base_ptr = (struct atm_bd_t *)(g_atm.int_reload_ptr + NUM_INT_ENTRIES); g_atm.tbd_base_ptr = (struct atm_bd_t *)(g_atm.rbd_base_ptr + total_num_rbd); diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds index 291f6b368..42e1b83b9 100644 --- a/board/siemens/IAD210/u-boot.lds +++ b/board/siemens/IAD210/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -126,7 +127,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile index 6ef49c2ce..af646e4eb 100644 --- a/board/siemens/SCM/Makefile +++ b/board/siemens/SCM/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,34 +23,20 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../../tqc/tqm8xx) -endif +LIB = lib$(BOARD).a -LIB = $(obj)lib$(BOARD).a +OBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \ + ../../tqm8xx/load_sernum_ethaddr.o -COBJS = scm.o flash.o fpga_scm.o ../common/fpga.o \ - ../../tqc/tqm8xx/load_sernum_ethaddr.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c index 6a9dd2583..8783aafe9 100644 --- a/board/siemens/SCM/scm.c +++ b/board/siemens/SCM/scm.c @@ -306,7 +306,7 @@ int power_on_reset (void) return gd->reset_status & RSR_CSRS ? 0 : 1; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; diff --git a/board/siemens/SCM/scm.h b/board/siemens/SCM/scm.h index cb5e03e58..70c12e6cc 100644 --- a/board/siemens/SCM/scm.h +++ b/board/siemens/SCM/scm.h @@ -29,7 +29,7 @@ /*----------------*/ /* Message */ -struct can_msg { +typedef struct can_msg { uchar ctrl_0; uchar ctrl_1; uchar arbit_0; @@ -38,9 +38,7 @@ struct can_msg { uchar arbit_3; uchar config; uchar data[8]; -} __attribute__ ((packed)); - -typedef struct can_msg can_msg_t; +} can_msg_t; /* CAN Register */ typedef struct can_reg { @@ -52,35 +50,35 @@ typedef struct can_reg { ushort gbl_mask_std; uint gbl_mask_extd; uint msg15_mask; - can_msg_t msg1; + can_msg_t msg1 __attribute__ ((packed)); uchar clkout; - can_msg_t msg2; + can_msg_t msg2 __attribute__ ((packed)); uchar bus_config; - can_msg_t msg3; + can_msg_t msg3 __attribute__ ((packed)); uchar bit_timing_0; - can_msg_t msg4; + can_msg_t msg4 __attribute__ ((packed)); uchar bit_timing_1; - can_msg_t msg5; + can_msg_t msg5 __attribute__ ((packed)); uchar interrupt; - can_msg_t msg6; + can_msg_t msg6 __attribute__ ((packed)); uchar resv1; - can_msg_t msg7; + can_msg_t msg7 __attribute__ ((packed)); uchar resv2; - can_msg_t msg8; + can_msg_t msg8 __attribute__ ((packed)); uchar resv3; - can_msg_t msg9; + can_msg_t msg9 __attribute__ ((packed)); uchar p1conf; - can_msg_t msg10; + can_msg_t msg10 __attribute__ ((packed)); uchar p2conf; - can_msg_t msg11; + can_msg_t msg11 __attribute__ ((packed)); uchar p1in; - can_msg_t msg12; + can_msg_t msg12 __attribute__ ((packed)); uchar p2in; - can_msg_t msg13; + can_msg_t msg13 __attribute__ ((packed)); uchar p1out; - can_msg_t msg14; + can_msg_t msg14 __attribute__ ((packed)); uchar p2out; - can_msg_t msg15; + can_msg_t msg15 __attribute__ ((packed)); uchar ser_res_addr; uchar resv_cs[0x8000-0x100]; /* 0x8000 is the min size for CS */ } can_reg_t; diff --git a/board/siemens/SCM/u-boot.lds b/board/siemens/SCM/u-boot.lds new file mode 100644 index 000000000..05f29c6ed --- /dev/null +++ b/board/siemens/SCM/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c index ac0022e7b..e9941cda6 100644 --- a/board/siemens/common/fpga.c +++ b/board/siemens/common/fpga.c @@ -131,44 +131,45 @@ static int fpga_reset (fpga_t* fpga) static int fpga_load (fpga_t* fpga, ulong addr, int checkall) { volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base; - image_header_t *hdr = (image_header_t *)addr; - ulong len; - uchar *data; - char msg[32]; + image_header_t hdr; + ulong len, checksum; + uchar *data = (uchar *)&hdr; + char *s, msg[32]; int verify, i; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - /* * Check the image header and data of the net-list */ - if (!image_check_magic (hdr)) { + memcpy (&hdr, (char *)addr, sizeof(image_header_t)); + + if (hdr.ih_magic != IH_MAGIC) { strcpy (msg, "Bad Image Magic Number"); goto failure; } - if (!image_check_hcrc (hdr)) { + len = sizeof(image_header_t); + + checksum = hdr.ih_hcrc; + hdr.ih_hcrc = 0; + + if (crc32 (0, data, len) != checksum) { strcpy (msg, "Bad Image Header CRC"); goto failure; } - data = (uchar*)image_get_data (hdr); - len = image_get_data_size (hdr); + data = (uchar*)(addr + sizeof(image_header_t)); + len = hdr.ih_size; - verify = getenv_yesno ("verify"); + s = getenv ("verify"); + verify = (s && (*s == 'n')) ? 0 : 1; if (verify) { - if (!image_check_dcrc (hdr)) { + if (crc32 (0, data, len) != hdr.ih_dcrc) { strcpy (msg, "Bad Image Data CRC"); goto failure; } } - if (checkall && fpga_get_version(fpga, image_get_name (hdr)) < 0) + if (checkall && fpga_get_version(fpga, (char *)(hdr.ih_name)) < 0) return 1; /* align length */ @@ -183,7 +184,7 @@ static int fpga_load (fpga_t* fpga, ulong addr, int checkall) goto failure; } - printf ("(%s)... ", image_get_name (hdr)); + printf ("(%s)... ", hdr.ih_name); /* * Copy data to FPGA */ @@ -218,7 +219,7 @@ static int fpga_load (fpga_t* fpga, ulong addr, int checkall) return 1; } -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ @@ -298,7 +299,7 @@ U_BOOT_CMD( "fpga load [name] addr - load FPGA configuration data\n" ); -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_BSP */ /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ @@ -340,14 +341,7 @@ int fpga_init (void) } hdr = (image_header_t *)addr; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if ((new_id = fpga_get_version(fpga, image_get_name (hdr))) == -1) + if ((new_id = fpga_get_version(fpga, (char *)(hdr->ih_name))) == -1) return 1; do_load = 1; diff --git a/board/siemens/pcu_e/Makefile b/board/siemens/pcu_e/Makefile index dcb190703..7a2014d46 100644 --- a/board/siemens/pcu_e/Makefile +++ b/board/siemens/pcu_e/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c index 5647f7af0..3f05e4a6a 100644 --- a/board/siemens/pcu_e/pcu_e.c +++ b/board/siemens/pcu_e/pcu_e.c @@ -156,7 +156,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; @@ -368,7 +368,7 @@ void reset_phy (void) /*----------------------------------------------------------------------- * Board Special Commands: access functions for "PUMA" FPGA */ -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) #define PUMA_READ_MODE 0 #define PUMA_LOAD_MODE 1 @@ -408,7 +408,7 @@ U_BOOT_CMD (puma, 4, 1, do_puma, "status - print PUMA status\n" "puma load addr len - load PUMA configuration data\n"); -#endif +#endif /* CFG_CMD_BSP */ /* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds index bc1ea7372..6505d4556 100644 --- a/board/siemens/pcu_e/u-boot.lds +++ b/board/siemens/pcu_e/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -117,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug index 2ee823745..828afbbce 100644 --- a/board/siemens/pcu_e/u-boot.lds.debug +++ b/board/siemens/pcu_e/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/sixnet/Makefile b/board/sixnet/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/sixnet/Makefile +++ b/board/sixnet/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c index dcd34726b..a4cb4dcf0 100644 --- a/board/sixnet/sixnet.c +++ b/board/sixnet/sixnet.c @@ -33,7 +33,7 @@ # include #endif -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif @@ -75,9 +75,9 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #error "SXNI855T has no PCMCIA port" -#endif +#endif /* CFG_CMD_PCMCIA */ /* ------------------------------------------------------------------------- */ @@ -327,7 +327,7 @@ int misc_init_r (void) return (0); } -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) void nand_init(void) { unsigned long totlen = nand_probe(CFG_DFLASH_BASE); @@ -496,7 +496,7 @@ const uint sdram_table[] = /* ------------------------------------------------------------------------- */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds index b91c44a57..1513a8517 100644 --- a/board/sixnet/u-boot.lds +++ b/board/sixnet/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -117,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/sl8245/Makefile b/board/sl8245/Makefile index dcb190703..6d1124043 100644 --- a/board/sl8245/Makefile +++ b/board/sl8245/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 - 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/sl8245/sl8245.c b/board/sl8245/sl8245.c index 86478871b..593eb4ee8 100644 --- a/board/sl8245/sl8245.c +++ b/board/sl8245/sl8245.c @@ -34,7 +34,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { #ifndef CFG_RAMBOOT long size; diff --git a/board/sl8245/u-boot.lds b/board/sl8245/u-boot.lds new file mode 100644 index 000000000..acb9ffda3 --- /dev/null +++ b/board/sl8245/u-boot.lds @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/smdk2400/Makefile b/board/smdk2400/Makefile index 90cb2b8f6..fc3d48fae 100644 --- a/board/smdk2400/Makefile +++ b/board/smdk2400/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := smdk2400.o flash.o +OBJS := smdk2400.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/smdk2400/lowlevel_init.S b/board/smdk2400/lowlevel_init.S index a7959f391..a5de806af 100644 --- a/board/smdk2400/lowlevel_init.S +++ b/board/smdk2400/lowlevel_init.S @@ -117,7 +117,7 @@ #define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ #define Trp 0x0 /* 2 clk */ #define Trc 0x3 /* 7 clk */ -#define Tchr 0x2 /* 3 clk */ +#define Tchr 0x2 /* 3 clk */ #define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */ diff --git a/board/smdk2400/u-boot.lds b/board/smdk2400/u-boot.lds index 14cd22800..f4fbf969c 100644 --- a/board/smdk2400/u-boot.lds +++ b/board/smdk2400/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/smdk2410/Makefile b/board/smdk2410/Makefile index 5d0cd722d..4ee21f597 100644 --- a/board/smdk2410/Makefile +++ b/board/smdk2410/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := smdk2410.o flash.o +OBJS := smdk2410.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/smdk2410/flash.c b/board/smdk2410/flash.c index 376930bd3..993946be9 100644 --- a/board/smdk2410/flash.c +++ b/board/smdk2410/flash.c @@ -290,7 +290,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) * Copy memory to flash */ -static int write_hword (flash_info_t * info, ulong dest, ushort data) +volatile static int write_hword (flash_info_t * info, ulong dest, ushort data) { vu_short *addr = (vu_short *) dest; ushort result; diff --git a/board/smdk2410/lowlevel_init.S b/board/smdk2410/lowlevel_init.S index ab6afdd48..310f2a0a9 100644 --- a/board/smdk2410/lowlevel_init.S +++ b/board/smdk2410/lowlevel_init.S @@ -45,85 +45,85 @@ #define BWSCON 0x48000000 /* BWSCON */ -#define DW8 (0x0) -#define DW16 (0x1) -#define DW32 (0x2) -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) +#define DW8 (0x0) +#define DW16 (0x1) +#define DW32 (0x2) +#define WAIT (0x1<<2) +#define UBLB (0x1<<3) -#define B1_BWSCON (DW32) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) +#define B1_BWSCON (DW32) +#define B2_BWSCON (DW16) +#define B3_BWSCON (DW16 + WAIT + UBLB) +#define B4_BWSCON (DW16) +#define B5_BWSCON (DW16) +#define B6_BWSCON (DW32) +#define B7_BWSCON (DW32) /* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x0 /* 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 -#define B0_PMC 0x0 /* normal */ +#define B0_Tacs 0x0 /* 0clk */ +#define B0_Tcos 0x0 /* 0clk */ +#define B0_Tacc 0x7 /* 14clk */ +#define B0_Tcoh 0x0 /* 0clk */ +#define B0_Tah 0x0 /* 0clk */ +#define B0_Tacp 0x0 +#define B0_PMC 0x0 /* normal */ /* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x0 /* 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 -#define B1_PMC 0x0 +#define B1_Tacs 0x0 /* 0clk */ +#define B1_Tcos 0x0 /* 0clk */ +#define B1_Tacc 0x7 /* 14clk */ +#define B1_Tcoh 0x0 /* 0clk */ +#define B1_Tah 0x0 /* 0clk */ +#define B1_Tacp 0x0 +#define B1_PMC 0x0 -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 +#define B2_Tacs 0x0 +#define B2_Tcos 0x0 +#define B2_Tacc 0x7 +#define B2_Tcoh 0x0 +#define B2_Tah 0x0 +#define B2_Tacp 0x0 +#define B2_PMC 0x0 -#define B3_Tacs 0x0 /* 0clk */ -#define B3_Tcos 0x3 /* 4clk */ -#define B3_Tacc 0x7 /* 14clk */ -#define B3_Tcoh 0x1 /* 1clk */ -#define B3_Tah 0x0 /* 0clk */ -#define B3_Tacp 0x3 /* 6clk */ -#define B3_PMC 0x0 /* normal */ +#define B3_Tacs 0x0 /* 0clk */ +#define B3_Tcos 0x3 /* 4clk */ +#define B3_Tacc 0x7 /* 14clk */ +#define B3_Tcoh 0x1 /* 1clk */ +#define B3_Tah 0x0 /* 0clk */ +#define B3_Tacp 0x3 /* 6clk */ +#define B3_PMC 0x0 /* normal */ -#define B4_Tacs 0x0 /* 0clk */ -#define B4_Tcos 0x0 /* 0clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x0 /* 0clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 -#define B4_PMC 0x0 /* normal */ +#define B4_Tacs 0x0 /* 0clk */ +#define B4_Tcos 0x0 /* 0clk */ +#define B4_Tacc 0x7 /* 14clk */ +#define B4_Tcoh 0x0 /* 0clk */ +#define B4_Tah 0x0 /* 0clk */ +#define B4_Tacp 0x0 +#define B4_PMC 0x0 /* normal */ -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x0 /* 0clk */ -#define B5_Tacc 0x7 /* 14clk */ -#define B5_Tcoh 0x0 /* 0clk */ -#define B5_Tah 0x0 /* 0clk */ -#define B5_Tacp 0x0 -#define B5_PMC 0x0 /* normal */ +#define B5_Tacs 0x0 /* 0clk */ +#define B5_Tcos 0x0 /* 0clk */ +#define B5_Tacc 0x7 /* 14clk */ +#define B5_Tcoh 0x0 /* 0clk */ +#define B5_Tah 0x0 /* 0clk */ +#define B5_Tacp 0x0 +#define B5_PMC 0x0 /* normal */ -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 -#define B6_SCAN 0x1 /* 9bit */ +#define B6_MT 0x3 /* SDRAM */ +#define B6_Trcd 0x1 +#define B6_SCAN 0x1 /* 9bit */ -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ -#define B7_SCAN 0x1 /* 9bit */ +#define B7_MT 0x3 /* SDRAM */ +#define B7_Trcd 0x1 /* 3clk */ +#define B7_SCAN 0x1 /* 9bit */ /* REFRESH parameter */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +#define REFEN 0x1 /* Refresh enable */ +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ +#define Trp 0x0 /* 2clk */ +#define Trc 0x3 /* 7clk */ +#define Tchr 0x2 /* 3clk */ +#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ /**************************************/ _TEXT_BASE: diff --git a/board/smdk2410/u-boot.lds b/board/smdk2410/u-boot.lds index 14cd22800..f4fbf969c 100644 --- a/board/smdk2410/u-boot.lds +++ b/board/smdk2410/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/snmc/qs850/Makefile b/board/snmc/qs850/Makefile index cf07cf40f..e5d844631 100644 --- a/board/snmc/qs850/Makefile +++ b/board/snmc/qs850/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/snmc/qs850/qs850.c b/board/snmc/qs850/qs850.c index 2fbe8aeb5..637f1250e 100644 --- a/board/snmc/qs850/qs850.c +++ b/board/snmc/qs850/qs850.c @@ -86,13 +86,6 @@ const uint sdram_table[] = * * Always return 1 */ -#if defined(CONFIG_QS850) -#define BOARD_IDENTITY "QS850" -#elif defined(CONFIG_QS823) -#define BOARD_IDENTITY "QS823" -#else -#define BOARD_IDENTITY "QS???" -#endif int checkboard (void) { @@ -103,8 +96,14 @@ int checkboard (void) i = getenv_r("serial#", buf, sizeof(buf)); s = (i>0) ? buf : NULL; - if (!s || strncmp(s, BOARD_IDENTITY, 5)) { - puts ("### No HW ID - assuming " BOARD_IDENTITY); +#ifdef CONFIG_QS850 + if (!s || strncmp(s, "QS850", 5)) { + puts ("### No HW ID - assuming QS850"); +#endif +#ifdef CONFIG_QS823 + if (!s || strncmp(s, "QS823", 5)) { + puts ("### No HW ID - assuming QS823"); +#endif } else { for (e=s; *e; ++e) { if (*e == ' ') @@ -144,7 +143,7 @@ int checkboard (void) #define REFRESH_INIT_LOOPS (0) -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds index 2410d5f2c..cb3f456a0 100644 --- a/board/snmc/qs850/u-boot.lds +++ b/board/snmc/qs850/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -131,7 +132,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/snmc/qs860t/Makefile b/board/snmc/qs860t/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/snmc/qs860t/Makefile +++ b/board/snmc/qs860t/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c index aa2e85605..c84d08d62 100644 --- a/board/snmc/qs860t/flash.c +++ b/board/snmc/qs860t/flash.c @@ -79,7 +79,8 @@ unsigned long flash_init (void) } /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) { + if (CFG_MAX_FLASH_BANKS == 1) + { /* Setup offsets */ flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]); @@ -97,11 +98,15 @@ unsigned long flash_init (void) #endif size_b1 = 0 ; flash_info[0].size = size_b0; - } else { /* 2 banks */ + } + /* 2 banks */ + else + { size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]); /* Re-do sizing to get full correct info */ - if (size_b1) { + if (size_b1) + { mtdcr(ebccfga, pb0cr); pbcr = mfdcr(ebccfgd); mtdcr(ebccfga, pb0cr); @@ -110,7 +115,8 @@ unsigned long flash_init (void) mtdcr(ebccfgd, pbcr); } - if (size_b0) { + if (size_b0) + { mtdcr(ebccfga, pb1cr); pbcr = mfdcr(ebccfgd); mtdcr(ebccfga, pb1cr); @@ -560,17 +566,17 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) info->flash_id += FLASH_28F320J3A; info->sector_count = 32; info->size = 0x00400000; - break; /* => 32 MBit */ + break; /* => 32 MBit */ case (INTEL_ID_28F640J3A & FLASH_ID_MASK): info->flash_id += FLASH_28F640J3A; info->sector_count = 64; info->size = 0x00800000; - break; /* => 64 MBit */ + break; /* => 64 MBit */ case (INTEL_ID_28F128J3A & FLASH_ID_MASK): info->flash_id += FLASH_28F128J3A; info->sector_count = 128; info->size = 0x01000000; - break; /* => 128 MBit */ + break; /* => 128 MBit */ default: /* FIXME*/ @@ -607,11 +613,10 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) /*----------------------------------------------------------------------- */ -int flash_erase (flash_info_t * info, int s_first, int s_last) +int flash_erase (flash_info_t *info, int s_first, int s_last) { - volatile FLASH_WORD_SIZE *addr = - (volatile FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]); int flag, prot, sect, l_sect, barf; ulong start, now, last; int rcode = 0; @@ -626,21 +631,22 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) } if ((info->flash_id == FLASH_UNKNOWN) || - ((info->flash_id > FLASH_AMD_COMP) && - ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) { + ((info->flash_id > FLASH_AMD_COMP) && + ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){ printf ("Can't erase unknown flash type - aborted\n"); return 1; } prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { + for (sect=s_first; sect<=s_last; ++sect) { if (info->protect[sect]) { prot++; } } if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); } else { printf ("\n"); } @@ -648,112 +654,109 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) l_sect = -1; /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - if (info->flash_id < FLASH_AMD_COMP) { + flag = disable_interrupts(); + if(info->flash_id < FLASH_AMD_COMP) { #ifndef CFG_FLASH_16BIT - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; #else - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; + addr[0x0555] = 0x0080; + addr[0x0555] = 0x00AA; + addr[0x02AA] = 0x0055; #endif - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]); - addr[0] = (0x00300030 & FLASH_ID_MASK); - l_sect = sect; - } + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]); + addr[0] = (0x00300030 & FLASH_ID_MASK); + l_sect = sect; } + } - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; - start = get_timer (0); - last = start; - addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]); - while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) != - (0x00800080 & FLASH_ID_MASK)) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } + start = get_timer (0); + last = start; + addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]); + while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != + (0x00800080&FLASH_ID_MASK) ) + { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } - DONE: - /* reset to read mode */ - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ - } else { +DONE: + /* reset to read mode */ + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */ + } else { - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - barf = 0; + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + barf = 0; #ifndef CFG_FLASH_16BIT - addr = (vu_long *) (info->start[sect]); - addr[0] = 0x00200020; - addr[0] = 0x00D000D0; - while (!(addr[0] & 0x00800080)); /* wait for error or finish */ - if (addr[0] & 0x003A003A) { /* check for error */ - barf = addr[0] & 0x003A0000; - if (barf) { - barf >>= 16; - } else { - barf = addr[0] & 0x0000003A; - } + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00200020; + addr[0] = 0x00D000D0; + while(!(addr[0] & 0x00800080)); /* wait for error or finish */ + if( addr[0] & 0x003A003A) { /* check for error */ + barf = addr[0] & 0x003A0000; + if( barf ) { + barf >>=16; + } else { + barf = addr[0] & 0x0000003A; } -#else - addr = (vu_short *) (info->start[sect]); - addr[0] = 0x0020; - addr[0] = 0x00D0; - while (!(addr[0] & 0x0080)); /* wait for error or finish */ - if (addr[0] & 0x003A) /* check for error */ - barf = addr[0] & 0x003A; -#endif - if (barf) { - printf ("\nFlash error in sector at %lx\n", - (unsigned long) addr); - if (barf & 0x0002) - printf ("Block locked, not erased.\n"); - if ((barf & 0x0030) == 0x0030) - printf ("Command Sequence error.\n"); - if ((barf & 0x0030) == 0x0020) - printf ("Block Erase error.\n"); - if (barf & 0x0008) - printf ("Vpp Low error.\n"); - rcode = 1; - } else - printf ("."); - l_sect = sect; } - addr = (volatile FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ - +#else + addr = (vu_short*)(info->start[sect]); + addr[0] = 0x0020; + addr[0] = 0x00D0; + while(!(addr[0] & 0x0080)); /* wait for error or finish */ + if( addr[0] & 0x003A) /* check for error */ + barf = addr[0] & 0x003A; +#endif + if(barf) { + printf("\nFlash error in sector at %lx\n",(unsigned long)addr); + if(barf & 0x0002) printf("Block locked, not erased.\n"); + if((barf & 0x0030) == 0x0030) + printf("Command Sequence error.\n"); + if((barf & 0x0030) == 0x0020) + printf("Block Erase error.\n"); + if(barf & 0x0008) printf("Vpp Low error.\n"); + rcode = 1; + } else printf("."); + l_sect = sect; } + addr = (volatile FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ } + + } printf (" done\n"); return rcode; } @@ -1020,7 +1023,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) } } } else { - while(!(addr[0] & 0x00800080)) { /* wait for error or finish */ + while(!(addr[0] & 0x00800080)) { /* wait for error or finish */ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { return (1); } @@ -1088,7 +1091,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data) } else { /* intel stuff */ - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); } @@ -1102,7 +1105,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data) } *addr = 0x00B0; *addr = 0x0070; - while(!(addr[0] & 0x0080)){ /* wait for error or finish */ + while(!(addr[0] & 0x0080)){ /* wait for error or finish */ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); } *addr = 0x00FF; @@ -1110,6 +1113,8 @@ static int write_short (flash_info_t *info, ulong dest, ushort data) return (0); } + #endif -/*-----------------------------------------------------------------------*/ +/*----------------------------------------------------------------------- + */ diff --git a/board/snmc/qs860t/qs860t.c b/board/snmc/qs860t/qs860t.c index 17c935621..a11d86301 100644 --- a/board/snmc/qs860t/qs860t.c +++ b/board/snmc/qs860t/qs860t.c @@ -115,7 +115,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds index 2410d5f2c..cb3f456a0 100644 --- a/board/snmc/qs860t/u-boot.lds +++ b/board/snmc/qs860t/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -131,7 +132,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/sorcery/Makefile b/board/sorcery/Makefile index 434d34898..3d6d67379 100644 --- a/board/sorcery/Makefile +++ b/board/sorcery/Makefile @@ -1,5 +1,4 @@ -# -# (C) Copyright 2005-2006 +# (C) Copyright 2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +22,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o +OBJS := $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c index 2b789d474..35d6a0608 100644 --- a/board/sorcery/sorcery.c +++ b/board/sorcery/sorcery.c @@ -27,13 +27,13 @@ #include #include -phys_size_t initdram (int board_type) +long int initdram (int board_type) { ulong size; size = dramSetup (); - return get_ram_size(CFG_SDRAM_BASE, size); + return get_ram_size((ulong *)CFG_SDRAM_BASE, size); } int checkboard (void) diff --git a/board/sorcery/u-boot.lds b/board/sorcery/u-boot.lds new file mode 100644 index 000000000..889bc77d2 --- /dev/null +++ b/board/sorcery/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8220/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/spc1920/Makefile b/board/spc1920/Makefile index 0c48c3aee..47afef7e6 100644 --- a/board/spc1920/Makefile +++ b/board/spc1920/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o hpi.o +OBJS = $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/spc1920/pld.h b/board/spc1920/pld.h index 5beb71b5c..3254f820c 100644 --- a/board/spc1920/pld.h +++ b/board/spc1920/pld.h @@ -5,8 +5,8 @@ typedef struct spc1920_pld { uchar com1_en; uchar dsp_reset; uchar dsp_hpi_on; - uchar superv_mode; uchar codec_dsp_power_en; + uchar clk2_en; uchar clk3_select; uchar clk4_select; } spc1920_pld_t; diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c index a32aad0ee..028f4c635 100644 --- a/board/spc1920/spc1920.c +++ b/board/spc1920/spc1920.c @@ -27,9 +27,9 @@ #include #include #include "pld.h" -#include "hpi.h" #define _NOT_USED_ 0xFFFFFFFF +/* #define debug(fmt,args...) printf (fmt ,##args) */ static long int dram_size (long int, long int *, long int); @@ -82,7 +82,7 @@ const uint sdram_table[] = { _NOT_USED_, _NOT_USED_, _NOT_USED_, }; -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; @@ -172,12 +172,10 @@ phys_size_t initdram (int board_type) memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; udelay (1000); - /* initalize the DSP Host Port Interface */ - hpi_init(); - /* FRAM Setup */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; + /* PLD Setup */ + memctl->memc_or5 = CFG_OR5_PRELIM; + memctl->memc_br5 = CFG_BR5_PRELIM; udelay(1000); return (size_b0); @@ -209,31 +207,13 @@ int board_early_init_f(void) { volatile immap_t *immap = (immap_t *) CFG_IMMR; - /* Set Go/NoGo led (PA15) to color red */ - immap->im_ioport.iop_papar &= ~0x1; - immap->im_ioport.iop_paodr &= ~0x1; - immap->im_ioport.iop_padir |= 0x1; - immap->im_ioport.iop_padat |= 0x1; -#if 0 /* Turn on LED PD9 */ immap->im_ioport.iop_pdpar &= ~(0x0040); immap->im_ioport.iop_pddir |= 0x0040; immap->im_ioport.iop_pddat |= 0x0040; -#endif - /* - * Enable console on SMC1. This requires turning on - * the com2_en signal and SMC1_DISABLE - */ - - /* SMC1_DISABLE: PB17 */ - immap->im_cpm.cp_pbodr &= ~0x4000; - immap->im_cpm.cp_pbpar &= ~0x4000; - immap->im_cpm.cp_pbdir |= 0x4000; - immap->im_cpm.cp_pbdat &= ~0x4000; - - /* COM2_EN: PD10 */ + /* Enable PD10 (COM2_EN) */ immap->im_ioport.iop_pdpar &= ~0x0020; immap->im_ioport.iop_pddir &= ~0x4000; immap->im_ioport.iop_pddir |= 0x0020; @@ -248,14 +228,6 @@ int board_early_init_f(void) return 0; } -int last_stage_init(void) -{ -#ifdef CONFIG_SPC1920_HPI_TEST - printf("CMB1920 Host Port Interface Test: %s\n", - hpi_test() ? "Failed!" : "OK"); -#endif - return 0; -} int checkboard (void) { diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds index 8c46e4677..d526d1d07 100644 --- a/board/spc1920/u-boot.lds +++ b/board/spc1920/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -131,7 +132,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/spd8xx/Makefile b/board/spd8xx/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/spd8xx/Makefile +++ b/board/spd8xx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/spd8xx/spd8xx.c b/board/spd8xx/spd8xx.c index 6387f8a65..c79b9b0dd 100644 --- a/board/spd8xx/spd8xx.c +++ b/board/spd8xx/spd8xx.c @@ -143,7 +143,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index 13b29084f..f9150ab3d 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -117,7 +118,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug index fd2245f57..650572d4d 100644 --- a/board/spd8xx/u-boot.lds.debug +++ b/board/spd8xx/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/ssv/adnpesc1/Makefile b/board/ssv/adnpesc1/Makefile index 40f04b81f..9182a4ecf 100644 --- a/board/ssv/adnpesc1/Makefile +++ b/board/ssv/adnpesc1/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o flash.o misc.o -SOBJS := vectors.o +OBJS := $(BOARD).o flash.o misc.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SOBJS = vectors.o -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/ssv/adnpesc1/adnpesc1.c b/board/ssv/adnpesc1/adnpesc1.c index 71de20899..2f704a0af 100644 --- a/board/ssv/adnpesc1/adnpesc1.c +++ b/board/ssv/adnpesc1/adnpesc1.c @@ -57,7 +57,7 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { return (0); } @@ -65,30 +65,31 @@ phys_size_t initdram (int board_type) /* * The following are used to control the SPI chip selects for the SPI command. */ -#if defined(CONFIG_CMD_SPI) && CONFIG_NIOS_SPI +#if (CONFIG_COMMANDS & CFG_CMD_SPI) && CONFIG_NIOS_SPI #define SPI_RTC_CS_MASK 0x00000001 -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) +void spi_rtc_chipsel(int cs) { nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; - spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */ + if (cs) + spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */ + else + spi->slaveselect = 0; /* deactivate (0) */ } -void spi_cs_deactivate(struct spi_slave *slave) -{ - nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; +/* + * The SPI command uses this table of functions for controlling the SPI + * chip selects: it calls the appropriate function to control the SPI + * chip selects. + */ +spi_chipsel_type spi_chipsel[] = { + spi_rtc_chipsel +}; +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); - spi->slaveselect = 0; /* deactivate (0) */ -} - -#endif +#endif /* CFG_CMD_SPI */ #if defined(CONFIG_POST) /* diff --git a/board/ssv/adnpesc1/u-boot.lds b/board/ssv/adnpesc1/u-boot.lds index be7795274..8b01f45e5 100644 --- a/board/ssv/adnpesc1/u-boot.lds +++ b/board/ssv/adnpesc1/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS __bss_start = .; . = ALIGN(4); - .bss (NOLOAD) : + .bss : { *(.bss) } diff --git a/board/ssv/common/cmd_sled.c b/board/ssv/common/cmd_sled.c index 2208580fa..d61fa3ed4 100644 --- a/board/ssv/common/cmd_sled.c +++ b/board/ssv/common/cmd_sled.c @@ -32,8 +32,8 @@ * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! * !!!!! !!!!! * !!!!! Next type definition was coming from original !!!!! - * !!!!! status LED driver drivers/misc/status_led.c !!!!! - * !!!!! and should be exported for using it here. !!!!! + * !!!!! status LED driver drivers/status_led.c and !!!!! + * !!!!! should exported for using here. !!!!! * !!!!! !!!!! * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */ @@ -46,7 +46,7 @@ typedef struct { extern led_dev_t led_dev[]; -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int led_id = 0; @@ -158,5 +158,5 @@ int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD (sled, 3, 0, do_sled, "sled - check and set status led\n", "sled [name [state]]\n" __NAME_STR " - state: on|off|blink\n"); -#endif +#endif /* CFG_CMD_BSP */ #endif /* CONFIG_STATUS_LED */ diff --git a/board/ssv/common/wd_pio.c b/board/ssv/common/wd_pio.c index 9945c5987..3215ac96a 100644 --- a/board/ssv/common/wd_pio.c +++ b/board/ssv/common/wd_pio.c @@ -112,7 +112,7 @@ void hw_watchdog_reset(void) enable_interrupts (); } -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { nios_pio_t *ena_piop = (nios_pio_t*)CONFIG_HW_WDENA_BASE; @@ -156,5 +156,5 @@ U_BOOT_CMD( "wd off - switch watchdog off\n" "wd - print current status\n" ); -#endif +#endif /* CFG_CMD_BSP */ #endif /* CONFIG_HW_WATCHDOG */ diff --git a/board/stamp/Makefile b/board/stamp/Makefile new file mode 100644 index 000000000..ab97e1b48 --- /dev/null +++ b/board/stamp/Makefile @@ -0,0 +1,68 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o stamp.o +SOBJS = + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/stamp/config.mk b/board/stamp/config.mk new file mode 100644 index 000000000..0d0073032 --- /dev/null +++ b/board/stamp/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x07FC0000 +PLATFORM_CPPFLAGS += -I$(TOPDIR) diff --git a/board/stamp/stamp.c b/board/stamp/stamp.c new file mode 100644 index 000000000..7e3af20ea --- /dev/null +++ b/board/stamp/stamp.c @@ -0,0 +1,276 @@ +/* + * U-boot - stamp.c STAMP board specific routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "stamp.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define STATUS_LED_OFF 0 +#define STATUS_LED_ON 1 + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +int checkboard (void) +{ + printf ("CPU: ADSP BF533 Rev.: 0.%d\n", *pCHIPID >> 28); + printf ("Board: ADI BF533 Stamp board\n"); + printf (" Support: http://blackfin.uclinux.org/\n"); + printf (" Richard Klingler \n"); + return 0; +} + +long int initdram (int board_type) +{ +#ifdef DEBUG + printf ("SDRAM attributes:\n"); + printf (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; " + "CAS Latency:%d cycles\n", + (SDRAM_tRCD >> 15), + (SDRAM_tRP >> 11), + (SDRAM_tRAS >> 6), + (SDRAM_tWR >> 19), + (SDRAM_CL >> 2)); + printf ("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); + printf ("Bank size = %d MB\n", 128); +#endif + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; + return (gd->bd->bi_memsize); +} + +void swap_to (int device_id) +{ + + if (device_id == ETHERNET) { + *pFIO_DIR = PF0; + asm ("ssync;"); + *pFIO_FLAG_S = PF0; + asm ("ssync;"); + } else if (device_id == FLASH) { + *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0); + *pFIO_FLAG_S = (PF4 | PF3 | PF2); + *pFIO_MASKA_D = (PF8 | PF6 | PF5); + *pFIO_MASKB_D = (PF7); + *pFIO_POLAR = (PF8 | PF6 | PF5); + *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5); + *pFIO_INEN = (PF8 | PF7 | PF6 | PF5); + *pFIO_FLAG_D = (PF4 | PF3 | PF2); + asm ("ssync;"); + } else { + printf ("Unknown bank to switch\n"); + } + + return; +} + +#if defined(CONFIG_MISC_INIT_R) +/* miscellaneous platform dependent initialisations */ +int misc_init_r (void) +{ + int i; + int cf_stat = 0; + + /* Check whether CF card is inserted */ + *pFIO_EDGE = FIO_EDGE_CF_BITS; + *pFIO_POLAR = FIO_POLAR_CF_BITS; + for (i = 0; i < 0x300; i++) + asm ("nop;"); + + if ((*pFIO_FLAG_S) & CF_STAT_BITS) { + cf_stat = 0; + } else { + cf_stat = 1; + } + + *pFIO_EDGE = FIO_EDGE_BITS; + *pFIO_POLAR = FIO_POLAR_BITS; + + + if (cf_stat) { + printf ("Booting from COMPACT flash\n"); + + /* Set cycle time for CF */ + *(volatile unsigned long *) ambctl1 = CF_AMBCTL1VAL; + + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + for (i = 0; i < 0x1000; i++) + asm ("nop;"); + + serial_setbrg (); + ide_init (); + + setenv ("bootargs", ""); + setenv ("bootcmd", + "fatload ide 0:1 0x1000000 uImage-stamp;bootm 0x1000000;bootm 0x20100000"); + } else { + printf ("Booting from FLASH\n"); + } + + return 1; +} +#endif + +#ifdef CONFIG_STAMP_CF + +void cf_outb (unsigned char val, volatile unsigned char *addr) +{ + /* + * Set PF1 PF0 respectively to 0 1 to divert address + * to the expansion memory banks + */ + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + *(addr) = val; + asm ("ssync;"); + + /* Setback PF1 PF0 to 0 0 to address external + * memory banks */ + *(volatile unsigned short *) pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} + +unsigned char cf_inb (volatile unsigned char *addr) +{ + volatile unsigned char c; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + c = *(addr); + asm ("ssync;"); + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); + + return c; +} + +void cf_insw (unsigned short *sect_buf, unsigned short *addr, int words) +{ + int i; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + for (i = 0; i < words; i++) { + *(sect_buf + i) = *(addr); + asm ("ssync;"); + } + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} + +void cf_outsw (unsigned short *addr, unsigned short *sect_buf, int words) +{ + int i; + + *pFIO_FLAG_S = CF_PF0; + *pFIO_FLAG_C = CF_PF1; + asm ("ssync;"); + + for (i = 0; i < words; i++) { + *(addr) = *(sect_buf + i); + asm ("ssync;"); + } + + *pFIO_FLAG_C = CF_PF1_PF0; + asm ("ssync;"); +} +#endif + +void stamp_led_set (int LED1, int LED2, int LED3) +{ + *pFIO_INEN &= ~(PF2 | PF3 | PF4); + *pFIO_DIR |= (PF2 | PF3 | PF4); + + if (LED1 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF2; + else + *pFIO_FLAG_C = PF2; + if (LED2 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF3; + else + *pFIO_FLAG_C = PF3; + if (LED3 == STATUS_LED_OFF) + *pFIO_FLAG_S = PF4; + else + *pFIO_FLAG_C = PF4; + asm ("ssync;"); +} + +void show_boot_progress (int status) +{ + switch (status) { + case 1: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, STATUS_LED_ON); + break; + case 2: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_OFF); + break; + case 3: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_ON, STATUS_LED_ON); + break; + case 4: + stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_OFF); + break; + case 5: + case 6: + stamp_led_set (STATUS_LED_ON, STATUS_LED_OFF, STATUS_LED_ON); + break; + case 7: + case 8: + stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_OFF); + break; + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + stamp_led_set (STATUS_LED_OFF, STATUS_LED_OFF, + STATUS_LED_OFF); + break; + default: + stamp_led_set (STATUS_LED_ON, STATUS_LED_ON, STATUS_LED_ON); + break; + } +} diff --git a/board/stamp/stamp.h b/board/stamp/stamp.h new file mode 100644 index 000000000..7bc33b414 --- /dev/null +++ b/board/stamp/stamp.h @@ -0,0 +1,57 @@ +/* + * U-boot - stamp.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __STAMP_H__ +#define __STAMP_H__ + +extern void init_Flags(void); + +extern volatile unsigned long *ambctl0; +extern volatile unsigned long *ambctl1; +extern volatile unsigned long *amgctl; + +extern unsigned long pll_div_fact; +extern void serial_setbrg(void); +extern void pll_set(int vco, int crystal_frq, int pll_div); + +/* Definitions used in Compact Flash Boot support */ +#define FIO_EDGE_CF_BITS 0x0000 +#define FIO_POLAR_CF_BITS 0x0000 +#define FIO_EDGE_BITS 0x1E0 +#define FIO_POLAR_BITS 0x160 + +/* Compact flash status bits in status register */ +#define CF_STAT_BITS 0x00000060 + +/* CF Flags used to switch between expansion and external + * memory banks + */ +#define CF_PF0 0x0001 +#define CF_PF1 0x0002 +#define CF_PF1_PF0 0x0003 + +#endif diff --git a/board/stamp/u-boot.lds b/board/stamp/u-boot.lds new file mode 100644 index 000000000..9a22e5078 --- /dev/null +++ b/board/stamp/u-boot.lds @@ -0,0 +1,147 @@ +/* + * U-boot - u-boot.lds + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(bfin) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector before the environment sector. If it throws */ + /* an error during compilation remove an object here to get */ + /* it linked after the configuration sector. */ + + cpu/bf533/start.o (.text) + cpu/bf533/start1.o (.text) + cpu/bf533/traps.o (.text) + cpu/bf533/interrupt.o (.text) + cpu/bf533/serial.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/strasbourg/Makefile b/board/strasbourg/Makefile new file mode 100644 index 000000000..1b2d01619 --- /dev/null +++ b/board/strasbourg/Makefile @@ -0,0 +1,77 @@ +# +# (C) Copyright 2009 Texas Instruments. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +COMMONDIR = ../tomtom/common +PLATDIR = ../tomtom/plat-omap3 + +LIB = lib$(BOARD).a + +# Boot shell scripts +USHOBJS := bootcmd.o altbootcmd.o preboot.o preboot_plat.o + +# U-Boot 1.1.4 build system sucks :P +ifeq (,$(shell fgrep -q 'CONFIG_DEBUG_BUILD' \ + $(TOPDIR)/include/`sed -ne 's|.*<\(.*\)>.*|\1|p' $(TOPDIR)/include/config.h` \ + 2>/dev/null || echo x)) +USHOBJS += bootcmd_debug.o altbootcmd_debug.o preboot_debug.o +endif + +OBJS := \ + strasbourg.o \ + sys_info.o \ + epic_fail.o + +OBJS += $(COMMONDIR)/bootcount.o $(COMMONDIR)/env_init.o +OBJS += $(PLATDIR)/boot_mode.o $(PLATDIR)/flipflop.o $(PLATDIR)/watchdog.o + +$(LIB): $(OBJS) $(USHOBJS) + $(AR) crv $@ $^ + +%.o: %.image + cd $( $@ + +-include .depend + +######################################################################### diff --git a/board/strasbourg/altbootcmd.ush b/board/strasbourg/altbootcmd.ush new file mode 100644 index 000000000..5fdcaaa32 --- /dev/null +++ b/board/strasbourg/altbootcmd.ush @@ -0,0 +1,2 @@ +flipflop 1 +bootm ${kernel.rescue.addr} diff --git a/board/strasbourg/altbootcmd_debug.ush b/board/strasbourg/altbootcmd_debug.ush new file mode 100644 index 000000000..986728dc0 --- /dev/null +++ b/board/strasbourg/altbootcmd_debug.ush @@ -0,0 +1,4 @@ +mw.l ${fdaddr} 0xdeadbeef 0x80 +ignore fatload ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${fdaddr} /altbootcmd.image +ignore autoscr ${fdaddr} +run altbootcmd.default diff --git a/board/strasbourg/bootcmd.ush b/board/strasbourg/bootcmd.ush new file mode 100644 index 000000000..4a5ed5798 --- /dev/null +++ b/board/strasbourg/bootcmd.ush @@ -0,0 +1,4 @@ +mw.l ${loadaddr} 0xdeadbeef 0x80 +echo Reading kernel from ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${bootfile} +ext2load ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${loadaddr} ${bootfile} ${kernel.maxsize} +bootm diff --git a/board/strasbourg/bootcmd_debug.ush b/board/strasbourg/bootcmd_debug.ush new file mode 100644 index 000000000..a957ba24c --- /dev/null +++ b/board/strasbourg/bootcmd_debug.ush @@ -0,0 +1,4 @@ +mw.l ${fdaddr} 0xdeadbeef 0x80 +ignore fatload ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${fdaddr} /bootcmd.image +ignore autoscr ${fdaddr} +run bootcmd.default diff --git a/board/strasbourg/config.mk b/board/strasbourg/config.mk new file mode 100644 index 000000000..a351e42c5 --- /dev/null +++ b/board/strasbourg/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x80200000 diff --git a/board/strasbourg/epic_fail.S b/board/strasbourg/epic_fail.S new file mode 100644 index 000000000..503f8bb9c --- /dev/null +++ b/board/strasbourg/epic_fail.S @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2010 + * TomTom International B.V. + * Martin Jackson + * + * + * Check whether we have previously tried all happy booting scenarios, + * and power off if there are no more options (an 'epic fail') + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef EPICFAIL_POWEROFF + +/* Unfortunately, we need this pin mapping _really_ early */ +# ifdef __VARIANT_A1 +# define CP_PWR_HOLD CONTROL_PADCONF_GPMC_A9 /* GPIO 42 */ +/* GPIO 42 Bank related */ +# define CLKEN_PER_EN_PWR_HOLD_BIT CLKEN_PER_EN_GPIO2_BIT /* Bit to toggle bank clock */ +# define OMAP34XX_PWR_HOLD_BASE OMAP34XX_GPIO2_BASE /* Base of bank */ +# define PWR_HOLD_BANK_GPIO 10 /* Offset within bank */ +# elif defined(__VARIANT_A2) +# define CP_PWR_HOLD CONTROL_PADCONF_GPMC_nBE1 /* GPIO 61 */ +/* GPIO 61 Bank related */ +# define CLKEN_PER_EN_PWR_HOLD_BIT CLKEN_PER_EN_GPIO2_BIT /* Bit to toggle bank clock */ +# define OMAP34XX_PWR_HOLD_BASE OMAP34XX_GPIO2_BASE /* Base of bank */ +# define PWR_HOLD_BANK_GPIO 29 /* Offset within bank */ +# else +# error Unrecognized variant! +# endif + +#endif /* EPICFAIL_POWEROFF */ + + +#define TOUT_01S 0xffff7fff /* Watchdog timeout of 1s */ +#define TOUT_10S 0xfffaffff /* Watchdog timeout of 10s */ +#define TOUT_60S 0xffe1ffff /* Watchdog timeout of 60s */ +#define WD_TIMEOUT TOUT_60S + + +@ Return value in r0 +.macro readl addr + ldr r0, =\addr + ldr r0, [r0] +.endm + +@ Clobbers r0, r1 +.macro writel val, addr + ldr r1, =\addr + ldr r0, =\val + str r0, [r1] +.endm + +@ Clobbers r0, r1 +.macro writew val, addr + ldr r1, =\addr + ldr r0, =\val + strh r0, [r1] +.endm + +@ Clobbers r0, r1 +.macro __modify_bit nr, addr, op + ldr r1, =\addr + ldr r0, [r1] + \op r0, r0, #1<<\nr + str r0, [r1] +.endm + +@ Clobbers r0, r1 +.macro set_bit nr, addr + __modify_bit \nr, \addr, orr +.endm + +@ Clobbers r0, r1 +.macro clr_bit nr, addr + __modify_bit \nr, \addr, bic +.endm + +@ Sets CPSR status bits, clobbers r0 +.macro tst_bit nr, addr + readl \addr + ands r0, r0, #1<<\nr +.endm + +.macro wdsync + ldr r0, =WD2_BASE+WWPS @ Wait for watchdog reg writes to drain +1: ldr r1, [r0] + cmp r1, #0 + bne 1b +.endm + +.macro wd_wr val, reg + writel \val, WD2_BASE + \reg + wdsync +.endm + + +@ Check whether an epic fail condition occurred +.global check_epicfail + +/* + * We don't push any context in case the stack or bits of memory are buggered. + * Clobbers: + * - r0: Scratch register + * - r1: Scratch register + * - r3: Saved CPSR state + * - r12: Saved LR + */ +check_epicfail: +#ifdef EPICFAIL_POWEROFF + mov r12, lr + + mrs r3, cpsr @ Disable all interrupts + mov r0, r3 + orr r0, r0, #0xc0 + msr cpsr, r0 + + @ PWR_HOLD probably isn't asserted here anyway, but deassert it just in case. + bl deassert_pwrhold + + @ Arm the watchdog with timeout of 60s + set_bit 5, CM_FCLKEN_WKUP @ Enable watchdog FCLK + set_bit 5, CM_ICLKEN_WKUP @ Enable watchdog ICLK + + ldr r0, =CM_IDLEST_WKUP @ Wait for watchdog to become accessible +1: ldr r1, [r0] + ands r1, #0x20 + bne 1b + + bl wd_disable @ Changing the timeout fails if we don't do this + + wd_wr WD_TIMEOUT, WLDR @ Load timeout value + wd_wr 0xaa55aa55, WTGR @ Reload the watchdog timeout + + @ Write the magic sequence 0xbbbb, 0x4444 that starts the watchdog count + wd_wr 0xbbbb, WSPR + wd_wr 0x4444, WSPR + + tst_bit 4, PRM_RSTTST @ Check whether it's a watchdog reset + beq no_epicfail + + @ Check the epic fail bit: did boot and altboot both fail already? + tst_bit EPICFAIL_BIT, FLIP_FLOP_LOCATION + bne epicfail @ epic fail bit set + watchdog reboot == epic fail + +no_epicfail: + @ Set the epic fail bit: this has to be cleared later by userland + @ (after the kernel boots) to prove no epic fail occurred. + set_bit EPICFAIL_BIT, FLIP_FLOP_LOCATION + + msr cpsr, r3 @ Restore interrupts + +#endif /* EPICFAIL_POWEROFF */ + mov pc, r12 + +.ltorg + + +@ Epic fail occurred: power the system down. Does NOT return +.global epicfail +epicfail: +#ifdef EPICFAIL_POWEROFF + clr_bit EPICFAIL_BIT, FLIP_FLOP_LOCATION @ System will attempt to boot next time SYSTEM_ON is asserted + bl deassert_pwrhold + bl wd_disable + + @ Could print a helpful message saying what happened. But don't want to + @ risk crashing in the UART code :P +1: b 1b @ Hang here until power goes down +#else + mov pc, lr +#endif /* EPICFAIL_POWEROFF */ + +.ltorg + + +#ifdef EPICFAIL_POWEROFF +@ Disable the watchdog +wd_disable: + @ Disable the watchdog with the magic 0xaaaa, 0x5555 sequence + wd_wr 0xaaaa, WSPR + wd_wr 0x5555, WSPR + +.ltorg + + +@ Deassert the PWR_HOLD pin +deassert_pwrhold: + writew (IDIS | PTD | DIS | M4), \ + OMAP34XX_CTRL_BASE+(CP_PWR_HOLD) @ Configure PWR_HOLD pin mux as GPIO + set_bit CLKEN_PER_EN_PWR_HOLD_BIT, \ + CM_FCLKEN_PER @ Enable PWR_HOLD GPIO bank FCLK + set_bit CLKEN_PER_EN_PWR_HOLD_BIT, \ + CM_ICLKEN_PER @ Enable PWR_HOLD GPIO bank ICLK + clr_bit PWR_HOLD_BANK_GPIO, OMAP34XX_PWR_HOLD_BASE + \ + OMAP34XX_GPIO_OE @ Set PWR_HOLD pin to output + clr_bit PWR_HOLD_BANK_GPIO, OMAP34XX_PWR_HOLD_BASE + \ + OMAP34XX_GPIO_DATAOUT @ Set PWR_HOLD pin low + mov pc, lr +.ltorg +#endif /* EPICFAIL_POWEROFF */ + + +.end + diff --git a/board/strasbourg/preboot.ush b/board/strasbourg/preboot.ush new file mode 100644 index 000000000..d379641d2 --- /dev/null +++ b/board/strasbourg/preboot.ush @@ -0,0 +1,19 @@ +run preboot_plat +setenv appletname /preboot-app.bin +setenv autoscript no +setenv bootfile /uImage +setenv conf.file /uboot.conf +setenv conf.maxsize 0x80 +setenv flash.part.bootfs /dev/mmcblk${kernel.bootdev}p${flash.part.bootfs.num} +setenv flash.part.rootfs /dev/mmcblk${hackdevice}p${flash.part.rootfs.num} +setenv kernel.root.options rootwait +setenv kernel.console.options ${baudrate} +setenv kernel.extrabootargs +setenv timeout 2 +setenv verify no +setenv no_trybooty no +setenv bootargs root=${flash.part.rootfs} ${kernel.root.options} console=${kernel.console},${kernel.console.options} ${kernel.extrabootargs} androidboot.console=${kernel.console} sysboot_mode=${sysboot_mode} init=/init videoout=omap24xxvout omap_vout.video1_numbuffers=6 omap_vout.vid1_static_vrfb_alloc=y omapfb.vram="0:4M" +mmcinit ${bootdev} +mw.w ${fdaddr} 0x00000000 ${conf.maxsize} +ignore fatload ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${fdaddr} /uboot.conf ${conf.maxsize} +ignore bootconf ${fdaddr} diff --git a/board/strasbourg/preboot_debug.ush b/board/strasbourg/preboot_debug.ush new file mode 100644 index 000000000..60b38ce7b --- /dev/null +++ b/board/strasbourg/preboot_debug.ush @@ -0,0 +1,8 @@ +run preboot.default +setenv verify yes +setenv kernel.bricknum 0 +setenv kernel.bricknum.rescue 0 +setenv kernel.quiet +mw.l ${fdaddr} 0xdeadbeef 0x80 +fatload ${bootdev.class} ${bootdev}:${flash.part.bootfs.num} ${fdaddr} /preboot.image +autoscr ${fdaddr} diff --git a/board/strasbourg/preboot_plat.ush b/board/strasbourg/preboot_plat.ush new file mode 100644 index 000000000..ffdcfabd9 --- /dev/null +++ b/board/strasbourg/preboot_plat.ush @@ -0,0 +1,8 @@ +setenv bootdev.class mmc +setenv flash.part.bootfs.num 2 +setenv flash.part.rootfs.num 2 +setenv kernel.bootdev ${bootdev} +setenv force_altboot no +setenv kernel.bricknum 0 +setenv kernel.bricknum.rescue 0 +setenv kernel.rescue.addr 0x08040000 diff --git a/board/strasbourg/strasbourg.c b/board/strasbourg/strasbourg.c new file mode 100644 index 000000000..30de608bb --- /dev/null +++ b/board/strasbourg/strasbourg.c @@ -0,0 +1,490 @@ + +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Before including the padconfig settings, we have to set proper config */ +#define BOOTLOADER_UBOOT_PADCONFIG +#ifdef __VARIANT_A1 +# include +#elif defined(__VARIANT_A2) +# include +#else +# error Unrecognized variant! +#endif + +DECLARE_GLOBAL_DATA_PTR; + +extern void detect_boot_mode(void); +extern void hw_watchdog_init(void); + +int get_boot_type(void); +void v7_flush_dcache_all(int, int); +void l2cache_enable(void); +void setup_auxcr(int, int); +void eth_init(void *); + +#ifdef __VARIANT_A1 +# define BOOTDEV_SDCARD 0 +# define BOOTDEV_MOVI 1 + +/* Fudge kernel bootdevice if sd card is present: + * - root=/dev/mmcblk0p2 if no SD card present OR if booting from SD + * - root=/dev/mmcblk1p2 if have SD card and booting from movi + */ +int hackdevice; + +#else +# define BOOTDEV_MOVI 0 +#endif + +int bootdev; + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + detect_boot_mode(); + + if (SYSBOOT_MODE_COLD == gd->tomtom.sysboot_mode) + /* cold boot => initialize the flipflop, we can't rely on the + state of the scratchpad register */ + flipflop_set(0); + + /* In general, load the kernel from MoviNAND; on A1 the SD slot is useful for recovery */ + bootdev = BOOTDEV_MOVI; + +#ifdef BOOTDEV_SDCARD + hackdevice = !mmc_init(0); + + if ((__raw_readl(0x480029c0) & 0xff) == 0x6) { /* Booted from the A1 SD slot? */ + bootdev = BOOTDEV_SDCARD; + hackdevice = 0; + } +#endif + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ +#if defined(__VARIANT_A2) + gd->bd->bi_arch_number = MACH_TYPE_STRASBOURG_A2; /* Linux mach id */ +#else + gd->bd->bi_arch_number = MACH_TYPE_STRASBOURG; /* Linux mach id */ +#endif + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param addr */ + + return 0; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_1); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_1); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_2); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_2); + + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_3); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_3); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + + +/********************************************************** + * Routine: secureworld_exit() + * Description: If chip is EMU and boot type is external + * configure secure registers and exit secure world + * general use. + ***********************************************************/ +void secureworld_exit(void) +{ + unsigned long i; + + /* configrue non-secure access control register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r" (i)); + /* enabling co-processor CP10 and CP11 accesses in NS world */ + __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); + /* allow allocation of locked TLBs and L2 lines in NS world */ + /* allow use of PLE registers in NS world also */ + __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r" (i)); + + /* Enable ASA and IBE in ACR register */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x50":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); + + /* Exiting secure world */ + __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r" (i)); +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + int in_sdram = running_in_sdram(); + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) { + secure_unlock_mem(); + } + /* If device is EMU and boot is XIP external booting + * Unlock firewalls and disable L2 and put chip + * out of secure world + */ + /* Assuming memories are unlocked by the demon who put us in SDRAM */ + if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) + && (!in_sdram)) { + secure_unlock_mem(); + secureworld_exit(); + } + + return; +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ +void s_init(void) +{ + int i; + int external_boot = 0; + int in_sdram = running_in_sdram(); + +#ifdef CONFIG_3430VIRTIO + in_sdram = 0; /* allow setup from memory for Virtio */ +#endif + hw_watchdog_init(); + + external_boot = (get_boot_type() == 0x1F) ? 1 : 0; + /* Right now flushing at low MPU speed. Need to move after clock init */ + v7_flush_dcache_all(get_device_type(), external_boot); + + try_unlock_memory(); + +#ifdef CONFIG_3430_AS_3410 + /* setup the scalability control register for + * 3430 to work in 3410 mode + */ + __raw_writel(0x5A80, CONTROL_SCALABLE_OMAP_OCP); +#endif + + if (cpu_is_3410()) { + /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ + __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); + __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); + } + +#ifndef CONFIG_ICACHE_OFF + icache_enable(); +#endif + +#ifdef CONFIG_L2_OFF + l2cache_disable(); +#else + l2cache_enable(); +#endif + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + setup_auxcr(get_device_type(), external_boot); + + prcm_init(); + + per_clocks_enable(); +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + unsigned char data; + + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + twl4030_usb_init(); + + /* see if we need to activate the power button startup */ + char *s = getenv("pbboot"); + if (s) { + /* figure out why we have booted */ + i2c_read(0x4b, 0x3a, 1, &data, 1); + + /* if status is non-zero, we didn't transition + * from WAIT_ON state + */ + if (data) { + printf("Transitioning to Wait State (%x)\n", data); + + /* clear status */ + data = 0; + i2c_write(0x4b, 0x3a, 1, &data, 1); + + /* put PM into WAIT_ON state */ + data = 0x01; + i2c_write(0x4b, 0x46, 1, &data, 1); + + /* no return - wait for power shutdown */ + while (1) {;} + } + printf("Transitioning to Active State (%x)\n", data); + + /* turn on long pwr button press reset*/ + data = 0x40; + i2c_write(0x4b, 0x46, 1, &data, 1); + printf("Power Button Active\n"); + } +#endif + dieid_num_r(); + return (0); +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + #define NOT_EARLY 0 + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0; + u32 mtype, btype; + + btype = get_board_type(); + mtype = get_mem_type(); +#ifndef CONFIG_3430ZEBU + /* fixme... dont know why this func is crashing in ZeBu */ + display_board_info(btype); +#endif + /* If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + } + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + + return 0; +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_DEFAULT_ES2()\ + /*Die to Die */\ + MUX_VAL(CP(d2d_mcad0), (IEN | PTD | EN | M0)) /*d2d_mcad0*/\ + MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ + MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ + MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ + MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ + MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ + MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ + MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ + MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ + MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ + MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ + MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ + MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ + MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ + MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ + MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ + MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ + MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ + MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ + MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ + MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ + MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ + MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ + MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ + MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ + MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ + MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ + MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ + MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ + MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ + MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ + MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ + MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ + MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ + MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ + MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ + MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ + MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi */\ + MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ + MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\ + MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\ + MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ + MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\ + MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\ + MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0 */\ + MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1 */\ + MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2 */\ + MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3 */\ + MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst */\ + MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ + MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ + MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ + MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ + MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck */\ + MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\ + MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq */\ + MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack */\ + MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ + MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ + MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ + MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ + MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag */\ + MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag */\ + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\ + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 unused*/ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + PADCONFIG_SETTINGS_UBOOT + PADCONFIG_SETTINGS_COMMON + MUX_DEFAULT_ES2(); +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} + +void board_env_init() +{ + /* Replace with factory data when available */ + switch(gd->bd->bi_arch_number) { + case MACH_TYPE_STRASBOURG_A2: + setenv("kernel.console", "ttyO2"); + break; + case MACH_TYPE_STRASBOURG: + default: + setenv("kernel.console", "ttyO0"); + break; + } +} diff --git a/board/strasbourg/sys_info.c b/board/strasbourg/sys_info.c new file mode 100644 index 000000000..56065e96b --- /dev/null +++ b/board/strasbourg/sys_info.c @@ -0,0 +1,377 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include /* get mem tables */ +#include +#include +#include +#include + +/************************************************************************** + * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch + * settings + * 1 is on + * 0 is off + * Will return Index of type of gpmc + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ + u8 cs; + + if(get_board_type() == SDP_3430_V2) + /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */ + cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) | + ((cs & 2) << 1) | ((cs & 1) << 3); + else + /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */ + cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2); + return (cs); +} + +/**************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + ****************************************************/ +u32 get_cpu_type(void) +{ + // fixme, need to get register defines for 3430 + return (CPU_3430); +} + +/* + * cpu_is_3410(void) - returns true for 3410 + */ +u32 cpu_is_3410(void) +{ + int status; + if (get_cpu_rev() < CPU_3XX_ES20) { + return 0; + } else { + /* read scalability status and return 1 for 3410*/ + status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS); + /* + * Check whether MPU frequency is set to 266 MHz which + * is nominal for 3410. If yes return true else false + */ + if (((status >> 8) & 0x3) == 0x2) + return 1; + else + return 0; + } +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == SDP_SDRC_MR_0_SDR) + return (1); + return (0); +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + ***********************************************************/ +u32 get_mem_type(void) +{ + /* Current SDP3430 uses 2x16 MDDR Infenion parts */ + return (DDR_DISCRETE); +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return (size); +} + +/* + * get_board_type() - get board type based on current production stats. + * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info. + * when they are available we can get info from there. This should + * be correct of all known boards up until today. + * - NOTE-2- EEPROMs are populated but they are updated very slowly. To + * avoid waiting on them we will use ES version of the chip to get info. + * A later version of the FPGA migth solve their speed issue. + */ +u32 get_board_type(void) +{ + if (get_cpu_rev() >= CPU_3XX_ES20) + return SDP_3430_V2; + else + return SDP_3430_V1; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return (0x0000003F & __raw_readl(CONTROL_STATUS)); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return (b); +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + return (WIDTH_16BIT); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + *************************************************************************/ +u32 get_board_rev(void) +{ + /* Currently reading EEPROM reg to get UI board version and try it out + */ +#if 0 + if (!check_uieeprom_avail()) { + /* timed out OR fpga rev not found!! */ + /* Assume 1.0 */ + return 0x01; + } + /* Move ahead to name location */ + ui_brd_name += 0x08; + count = sizeof(enhanced_ui_brd_name) - 2; + while ((enhanced_ui_brd_name[count] == ui_brd_name[count]) && count) { + count--; + } + /* Match?? */ + if (!count) { + /* Enhanced UI board.. SDP1.1 */ + return 0x11; + } +#endif + /* Legacy UI - hope they are all 1.0 boards.. */ + return (0x10); +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + enum { + BOOTMODE_NOR, + BOOTMODE_ONND, + BOOTMODE_NAND, + BOOTMODE_MMC + }; + + char *bootmode[] = { + "NOR", + "ONND", + "NAND", + "MMC" + }; + u32 brev = get_board_rev(); + char cpu_3430s[] = "3630"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; +#ifdef CONFIG_LED_INFO + char led_string[CONFIG_LED_LEN] = { 0 }; +#endif + +#if defined(L3_200MHZ) + char p_l3[] = "200"; +#elif defined(L3_165MHZ) + char p_l3[] = "165"; +#elif defined(L3_110MHZ) + char p_l3[] = "110"; +#elif defined(L3_133MHZ) + char p_l3[] = "133"; +#elif defined(L3_100MHZ) + char p_l3[] = "100"; +#endif + +#if defined(PRCM_PCLK_OPP1) + char p_cpu[] = "1"; +#elif defined(PRCM_PCLK_OPP2) + char p_cpu[] = "2"; +#elif defined(PRCM_PCLK_OPP3) + char p_cpu[] = "3"; +#elif defined(PRCM_PCLK_OPP4) + char p_cpu[] = "4"; +#endif + char *cpu_s, *db_s, *mem_s, *sec_s; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) + mem_s = mem_sdr; + else + mem_s = mem_ddr; + + cpu_s = cpu_3430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev, + p_cpu, p_l3); + printf("OMAP3630 Strasbourg %s Version + %s (Boot %s)\n", db_s, + mem_s, bootmode[BOOTMODE_MMC]); +#ifdef CONFIG_LED_INFO + /* Format: 0123456789ABCDEF + * 3430C GP L3-100 NAND + */ + sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, p_l3, + bootmode[2]); + /* reuse sec */ + for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) { + /* invert byte loc */ + u16 val = led_string[sec] << 8; + val |= led_string[sec + 1]; + __raw_writew(val, LED_REGISTER + sec); + } +#endif + +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory"); + val &= 0xF0000000; + val >>= 28; + return (val); +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return (1); /* in flash */ + return (0); /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return (1); /* in SRAM */ + return (0); /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * sdram. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return (1); /* in sdram */ + return (0); /* running in SRAM or FLASH */ +} + +/*************************************************************** + * get_boot_type() - Is this an XIP type device or a stream one + * bits 4-0 specify type. Bit 5 sys mem/perif + ***************************************************************/ +u32 get_boot_type(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0); + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return (mode >>= 8); +} diff --git a/board/strasbourg/u-boot.lds b/board/strasbourg/u-boot.lds new file mode 100644 index 000000000..a810db903 --- /dev/null +++ b/board/strasbourg/u-boot.lds @@ -0,0 +1,83 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/omap3/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .bootscript : { *(.bootscript) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + . = ALIGN(4); + _end = .; + + . = 0x81000000; + /* NOBITS section to contain the FDT */ + .fdt . (COPY) : + { + __fdt_start = .; + . = . + 128K; /* Max FDT len is 128K */ + __fdt_end = .; + } + + . = ALIGN(128); + /* NOBITS section to contain the kernel */ + .kern . (COPY) : + { + __kern_start = .; + . = . + 4M; + __kern_end = .; + } + + . = ALIGN(4); +} + diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile index 325d6d572..d150df831 100644 --- a/board/stxgp3/Makefile +++ b/board/stxgp3/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o flash.o law.o tlb.o +OBJS := $(BOARD).o flash.o +SOBJS := init.o +#SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(OBJS) $(SOBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/stxgp3/init.S b/board/stxgp3/init.S new file mode 100644 index 000000000..d504289bb --- /dev/null +++ b/board/stxgp3/init.S @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2004 Embedded Edge, LLC + * Dan Malek + * Copied from ADS85xx. + * Updates for Silicon Tx GP3 8560. We only support 32-bit flash + * and DDR with SPD EEPROM configuration. + * + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \ + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \ + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \ + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \ + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \ + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \ + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \ + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \ + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \ + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \ + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), \ + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), \ + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 16K Non-cacheable, guarded + * 0xfc000000 16K Configuration Latch register + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_LCLDEVS_BASE), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 8, 9: 128M DDR + * 0x00000000 64M DDR System memory + * 0x04000000 64M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ +#error("Update the number of table entries in tlb1_entry") + .long TLB1_MAS0(1, 8, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1, 9, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000), + 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xfc00_0000 0xfc00_ffff Config Latch 64K + * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c index 218e8053f..2b3949cd7 100644 --- a/board/stxgp3/stxgp3.c +++ b/board/stxgp3/stxgp3.c @@ -29,13 +29,15 @@ */ +extern long int spd_sdram (void); + #include #include #include #include #include #include -#include +#include #include long int fixed_sdram (void); @@ -201,7 +203,8 @@ int board_early_init_f(void) { #if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; pci->peer &= 0xfffffffdf; /* disable master abort */ #endif @@ -275,14 +278,16 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); } -phys_size_t +long int initdram (int board_type) { long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur= &immap->im_gur; uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ @@ -370,6 +375,8 @@ void pci_init_board(void) { #ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds index 9cc499747..3bc615021 100644 --- a/board/stxgp3/u-boot.lds +++ b/board/stxgp3/u-boot.lds @@ -27,6 +27,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -39,6 +40,7 @@ SECTIONS .bootpg 0xFFFFF000 : { cpu/mpc85xx/start.o (.bootpg) + board/stxgp3/init.o (.bootpg) } = 0xffff /* Read-only sections, merged into text segment: */ @@ -48,11 +50,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -68,6 +70,7 @@ SECTIONS .text : { cpu/mpc85xx/start.o (.text) + board/stxgp3/init.o (.text) cpu/mpc85xx/commproc.o (.text) cpu/mpc85xx/traps.o (.text) cpu/mpc85xx/interrupts.o (.text) @@ -76,6 +79,7 @@ SECTIONS cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/i2c.o (.text) cpu/mpc85xx/spd_sdram.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) @@ -143,7 +147,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/stxxtc/Makefile b/board/stxxtc/Makefile index 424ab1cf9..11065cfd2 100644 --- a/board/stxxtc/Makefile +++ b/board/stxxtc/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o +OBJS = $(BOARD).o oftree.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +%.dtb: %.dts + dtc -f -V 0x10 -I dts -O dtb $< >$@ + +%.c: %.dtb + xxd -i $< \ + | sed -e "s/^unsigned char/const unsigned char/g" \ + | sed -e "s/^unsigned int/const unsigned int/g" > $@ ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/stxxtc/oftree.dts b/board/stxxtc/oftree.dts new file mode 100644 index 000000000..e3f301794 --- /dev/null +++ b/board/stxxtc/oftree.dts @@ -0,0 +1,52 @@ +/ { + model = "STXXTC V1"; + compatible = "STXXTC"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + linux,phandle = <1>; + #address-cells = <1>; + #size-cells = <0>; + PowerPC,MPC870@0 { + linux,phandle = <3>; + name = "PowerPC,MPC870"; + device_type = "cpu"; + reg = <0>; + clock-frequency = <0>; /* place-holder for runtime fillup */ + timebase-frequency = <0>; /* dido */ + linux,boot-cpu; + i-cache-size = <2000>; + d-cache-size = <2000>; + 32-bit; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <00000000 00000000 00000000 20000000>; + }; + + /* copy of the bd_t information (place-holders) */ + bd_t { + memstart = <0>; + memsize = <0>; + flashstart = <0>; + flashsize = <0>; + flashoffset = <0>; + sramstart = <0>; + sramsize = <0>; + + immr_base = <0>; + + bootflags = <0>; + ip_addr = <0>; + enetaddr = [ 00 00 00 00 00 00 ]; + ethspeed = <0>; + intfreq = <0>; + busfreq = <0>; + + baudrate = <0>; + }; + +}; diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c index a75037439..7caf06a08 100644 --- a/board/stxxtc/stxxtc.c +++ b/board/stxxtc/stxxtc.c @@ -399,7 +399,7 @@ void check_ram(unsigned int addr, unsigned int size) #define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0) -phys_size_t initdram(int board_type) +long int initdram(int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -574,7 +574,7 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include diff --git a/board/stxxtc/u-boot.lds b/board/stxxtc/u-boot.lds index f560189c0..9f2901c86 100644 --- a/board/stxxtc/u-boot.lds +++ b/board/stxxtc/u-boot.lds @@ -22,21 +22,22 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS { /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; - .interp : { *(.interp) } + .interp : { *(.interp) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } @@ -49,8 +50,8 @@ SECTIONS .rel.plt : { *(.rel.plt) } .rela.plt : { *(.rela.plt) } .init : { *(.init) } - .plt : { *(.plt) } - .text : + .plt : { *(.plt) } + .text : { cpu/mpc8xx/start.o (.text) cpu/mpc8xx/traps.o (.text) @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/stxxtc/u-boot.lds.debug b/board/stxxtc/u-boot.lds.debug index 5bf1a6628..004e7fd35 100644 --- a/board/stxxtc/u-boot.lds.debug +++ b/board/stxxtc/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/svm_sc8xx/Makefile b/board/svm_sc8xx/Makefile index cf07cf40f..13ce9fc9d 100644 --- a/board/svm_sc8xx/Makefile +++ b/board/svm_sc8xx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c index 06fb18b34..9bb9fd019 100644 --- a/board/svm_sc8xx/svm_sc8xx.c +++ b/board/svm_sc8xx/svm_sc8xx.c @@ -100,7 +100,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -153,7 +153,7 @@ phys_size_t initdram (int board_type) return (size_b0 ); } -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) extern void doc_probe (ulong physadr); void doc_init (void) { diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index 14ff17987..d7f7dc132 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -132,7 +133,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug index 0cd053a8b..894b9bd25 100644 --- a/board/svm_sc8xx/u-boot.lds.debug +++ b/board/svm_sc8xx/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/sx1/Makefile b/board/sx1/Makefile index 4c11030ed..8fbdf2a5e 100644 --- a/board/sx1/Makefile +++ b/board/sx1/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2004-2006 +# (C) Copyright 2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := sx1.o +OBJS := sx1.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/sx1/u-boot.lds b/board/sx1/u-boot.lds index b608223a7..d28155f4c 100644 --- a/board/sx1/u-boot.lds +++ b/board/sx1/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/tb0229/Makefile b/board/tb0229/Makefile index 1f6f51726..4375073af 100644 --- a/board/tb0229/Makefile +++ b/board/tb0229/Makefile @@ -1,7 +1,7 @@ # # (C) Masami Komiya 2004 # -# (C) Copyright 2003-2006 +# (C) Copyright 2003-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,23 +25,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o vr4131-pci.o +OBJS = $(BOARD).o flash.o vr4131-pci.o SOBJS = lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/tb0229/lowlevel_init.S b/board/tb0229/lowlevel_init.S index 5fce8567d..df318067b 100644 --- a/board/tb0229/lowlevel_init.S +++ b/board/tb0229/lowlevel_init.S @@ -10,6 +10,7 @@ */ #include +#include #include diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c index 921bd3adc..e7914bd15 100644 --- a/board/tb0229/tb0229.c +++ b/board/tb0229/tb0229.c @@ -12,16 +12,10 @@ #include #include #include -#include -#include +#include #include -void _machine_restart(void) -{ - void (*f)(void) = (void *) 0xbfc00000; - - f(); -} +unsigned long mips_io_port_base = 0; #if defined(CONFIG_PCI) static struct pci_controller hose; @@ -32,17 +26,17 @@ void pci_init_board (void) } #endif -phys_size_t initdram(int board_type) + +long int initdram(int board_type) { return get_ram_size (CFG_SDRAM_BASE, 0x8000000); } + int checkboard (void) { printf("Board: TANBAC TB0229 "); printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000); - set_io_port_base(0); - return 0; } diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds index b18e6a6fc..30a2bc57e 100644 --- a/board/tb0229/u-boot.lds +++ b/board/tb0229/u-boot.lds @@ -43,28 +43,27 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = .; - _gp = ALIGN(16) + 0x7ff0; + . = ALIGN(4); + .sdata : { *(.sdata) } - .got : { - __got_start = .; - *(.got) - __got_end = .; - } + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; .sdata : { *(.sdata) } - .u_boot_cmd : { - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; . = ALIGN(4); - .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .sbss : { *(.sbss) } + .bss : { *(.bss) } uboot_end = .; } diff --git a/board/tb0229/vr4131-pci.c b/board/tb0229/vr4131-pci.c index 4c9192341..0ee4bf30e 100644 --- a/board/tb0229/vr4131-pci.c +++ b/board/tb0229/vr4131-pci.c @@ -13,34 +13,34 @@ #include #include -#define VR4131_PCIMMAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c00) -#define VR4131_PCIMMAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c04) -#define VR4131_PCITAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c08) -#define VR4131_PCITAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c0c) -#define VR4131_PCIMIOAWREG (volatile unsigned int *)(CKSEG1 + 0x0f000c10) -#define VR4131_PCICONFDREG (volatile unsigned int *)(CKSEG1 + 0x0f000c14) -#define VR4131_PCICONFAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c18) -#define VR4131_PCIMAILREG (volatile unsigned int *)(CKSEG1 + 0x0f000c1c) -#define VR4131_BUSERRADREG (volatile unsigned int *)(CKSEG1 + 0x0f000c24) -#define VR4131_INTCNTSTAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c28) -#define VR4131_PCIEXACCREG (volatile unsigned int *)(CKSEG1 + 0x0f000c2c) -#define VR4131_PCIRECONTREG (volatile unsigned int *)(CKSEG1 + 0x0f000c30) -#define VR4131_PCIENREG (volatile unsigned int *)(CKSEG1 + 0x0f000c34) -#define VR4131_PCICLKSELREG (volatile unsigned int *)(CKSEG1 + 0x0f000c38) -#define VR4131_PCITRDYREG (volatile unsigned int *)(CKSEG1 + 0x0f000c3c) -#define VR4131_PCICLKRUNREG (volatile unsigned int *)(CKSEG1 + 0x0f000c60) -#define VR4131_PCIHOSTCONFIG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) -#define VR4131_VENDORIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) -#define VR4131_DEVICEIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) -#define VR4131_COMMANDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04) -#define VR4131_STATUSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04) -#define VR4131_REVREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08) -#define VR4131_CLASSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08) -#define VR4131_CACHELSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c) -#define VR4131_LATTIMERRG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c) -#define VR4131_MAILBAREG (volatile unsigned int *)(CKSEG1 + 0x0f000d10) -#define VR4131_PCIMBA1REG (volatile unsigned int *)(CKSEG1 + 0x0f000d14) -#define VR4131_PCIMBA2REG (volatile unsigned int *)(CKSEG1 + 0x0f000d18) +#define VR4131_PCIMMAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c00) +#define VR4131_PCIMMAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c04) +#define VR4131_PCITAW1REG (volatile unsigned int*)(KSEG1 + 0x0f000c08) +#define VR4131_PCITAW2REG (volatile unsigned int*)(KSEG1 + 0x0f000c0c) +#define VR4131_PCIMIOAWREG (volatile unsigned int*)(KSEG1 + 0x0f000c10) +#define VR4131_PCICONFDREG (volatile unsigned int*)(KSEG1 + 0x0f000c14) +#define VR4131_PCICONFAREG (volatile unsigned int*)(KSEG1 + 0x0f000c18) +#define VR4131_PCIMAILREG (volatile unsigned int*)(KSEG1 + 0x0f000c1c) +#define VR4131_BUSERRADREG (volatile unsigned int*)(KSEG1 + 0x0f000c24) +#define VR4131_INTCNTSTAREG (volatile unsigned int*)(KSEG1 + 0x0f000c28) +#define VR4131_PCIEXACCREG (volatile unsigned int*)(KSEG1 + 0x0f000c2c) +#define VR4131_PCIRECONTREG (volatile unsigned int*)(KSEG1 + 0x0f000c30) +#define VR4131_PCIENREG (volatile unsigned int*)(KSEG1 + 0x0f000c34) +#define VR4131_PCICLKSELREG (volatile unsigned int*)(KSEG1 + 0x0f000c38) +#define VR4131_PCITRDYREG (volatile unsigned int*)(KSEG1 + 0x0f000c3c) +#define VR4131_PCICLKRUNREG (volatile unsigned int*)(KSEG1 + 0x0f000c60) +#define VR4131_PCIHOSTCONFIG (volatile unsigned int*)(KSEG1 + 0x0f000d00) +#define VR4131_VENDORIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) +#define VR4131_DEVICEIDREG (volatile unsigned int*)(KSEG1 + 0x0f000d00) +#define VR4131_COMMANDREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) +#define VR4131_STATUSREG (volatile unsigned int*)(KSEG1 + 0x0f000d04) +#define VR4131_REVREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) +#define VR4131_CLASSREG (volatile unsigned int*)(KSEG1 + 0x0f000d08) +#define VR4131_CACHELSREG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) +#define VR4131_LATTIMERRG (volatile unsigned int*)(KSEG1 + 0x0f000d0c) +#define VR4131_MAILBAREG (volatile unsigned int*)(KSEG1 + 0x0f000d10) +#define VR4131_PCIMBA1REG (volatile unsigned int*)(KSEG1 + 0x0f000d14) +#define VR4131_PCIMBA2REG (volatile unsigned int*)(KSEG1 + 0x0f000d18) /*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */ /*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */ diff --git a/board/tomtom/common/bootcount.c b/board/tomtom/common/bootcount.c new file mode 100644 index 000000000..2c3f79c3a --- /dev/null +++ b/board/tomtom/common/bootcount.c @@ -0,0 +1,79 @@ +/* + * BCM4760 'flipflop' - Retains 1-bit across a watchdog reset. + * + * Copyright (C) 2010 TomTom International B.V. + * Author: Martin Jackson + * + ************************************************************************ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + ************************************************************************ + */ + +/* #define DEBUG */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int get_bootlimit(void) +{ + char *s; + +#ifdef CONFIG_BOOTCOUNT_LIMIT + if ((s=getenv("bootlimit")) != NULL) { + int n = simple_strtoul(s, NULL, 10); + debug("bootlimit = %d\n", n); + return n; + } +#endif + debug("bootlimit hardcoded to 1\n"); + return 1; +} + +void bootcount_store(ulong count) +{ + debug("Storing bootcount [%lu]\n", count); + gd->tomtom.bootcount = count; + if (count <= get_bootlimit()) + flipflop_set(1); + else + flipflop_set(0); +} + +ulong bootcount_load(void) +{ + ulong r = gd->tomtom.bootcount; + char *s; + +#ifdef __NON_LEGACY + if ((s=getenv("sysboot_mode")) != NULL && + strcmp(s, "watchdog") == 0) +#else + if (gd->tomtom.sysboot_mode == SYSBOOT_MODE_WATCHDOG && + gd->tomtom.bootcount == 0) +#endif + { + debug("sysboot_mode is watchdog\n"); + if (flipflop_get()) { + r += get_bootlimit(); + } + } else { + debug("sysboot_mode is cold\n"); + } + + debug("Returning bootcount %lu\n", r); + return r; +} diff --git a/board/tomtom/common/env_init.c b/board/tomtom/common/env_init.c new file mode 100644 index 000000000..9d627069f --- /dev/null +++ b/board/tomtom/common/env_init.c @@ -0,0 +1,99 @@ +/* + * Initialize TomTom specific environment variables + * + * Some of this stuff we normally would do in the board file, but the + * environment isn't initialized when board_init() is called + * + * Copyright (C) 2010 TomTom International B.V. + * Author: Matthias Kaehlcke + * Martin Jackson + * + ************************************************************************ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + ************************************************************************ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern void board_env_init (void) __attribute__((weak)); + +void tomtom_env_init(void) +{ + const char *str_bootmode; + char ulong_str[16]; /* Needs to be as long as "0x12345678" + '\0' */ + + switch (gd->tomtom.sysboot_mode) { + case SYSBOOT_MODE_COLD: + str_bootmode = SYSBOOT_MODE_STR_COLD; + break; + + case SYSBOOT_MODE_WARM: + case SYSBOOT_MODE_WATCHDOG: + /* we treat warm and watchdog resets uniformly */ + str_bootmode = SYSBOOT_MODE_STR_WATCHDOG; /* TODO: consider changing to "warm" */ + break; + + default: + printf("invalid value for sysboot_mode: %d\n", gd->tomtom.sysboot_mode); + + str_bootmode = SYSBOOT_MODE_STR_COLD; + } + + setenv("sysboot_mode", str_bootmode); + + IMPORT_BOOTSCRIPT(preboot_plat, preboot_plat); +#ifdef CONFIG_DEBUG_BUILD + IMPORT_BOOTSCRIPT(preboot_debug, preboot); + IMPORT_BOOTSCRIPT(bootcmd_debug, bootcmd); + IMPORT_BOOTSCRIPT(altbootcmd_debug, altbootcmd); + IMPORT_BOOTSCRIPT(preboot, preboot.default); + IMPORT_BOOTSCRIPT(bootcmd, bootcmd.default); + IMPORT_BOOTSCRIPT(altbootcmd, altbootcmd.default); +#else + IMPORT_BOOTSCRIPT(preboot, preboot); + IMPORT_BOOTSCRIPT(bootcmd, bootcmd); + IMPORT_BOOTSCRIPT(altbootcmd, altbootcmd); +#endif + + sprintf(ulong_str, "%p", CFG_LOAD_ADDR); + setenv("loadaddr", ulong_str); + + sprintf(ulong_str, "%p", CFG_FDT_ADDR); + setenv("fdaddr", ulong_str); + + sprintf(ulong_str, "%#x", MEMADDR_KERN_LEN); + setenv("kernel.maxsize", ulong_str); + +extern int bootdev; /* Defined in the board/.../.c */ + sprintf(ulong_str, "%u", bootdev); + setenv("bootdev", ulong_str); + +#ifdef __VARIANT_A1 + /* make this work better :S */ +extern int hackdevice; /* Defined in the board/.../.c */ + sprintf(ulong_str, "%u", hackdevice); +#else + sprintf(ulong_str, "%u", 0); +#endif + setenv("hackdevice", ulong_str); + + if (board_env_init) + board_env_init(); +} + diff --git a/board/tomtom/plat-omap3/boot_mode.c b/board/tomtom/plat-omap3/boot_mode.c new file mode 100644 index 000000000..36672f2a8 --- /dev/null +++ b/board/tomtom/plat-omap3/boot_mode.c @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2010 TomTom BV + * Author: Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Detect the boot mode evaluating the PRM_RSTTST and a register in the + * scratchpad holding a magic value on software reset + */ + +#include +#include + +#define BOOT_MODE_AUX_REG (OMAP34XX_CTRL_BASE + 0x09FC) +#define BOOT_MODE_AUX_MASK 0x3fffffff +#define BOOT_MODE_AUX_MAGIC 0x3eafc35b + +DECLARE_GLOBAL_DATA_PTR; + +void detect_boot_mode(void) +{ + u32 val = __raw_readl(PRM_RSTTST); + + if (val & GLOBAL_COLD_RST) { + /* cold boot or software reset */ + + val = __raw_readl(BOOT_MODE_AUX_REG); + + if ((val & BOOT_MODE_AUX_MASK) == BOOT_MODE_AUX_MAGIC) { + /* the register contains the magic value => software reset */ + gd->tomtom.sysboot_mode = SYSBOOT_MODE_WARM; + } else { + gd->tomtom.sysboot_mode = SYSBOOT_MODE_COLD; + + /* write the magic value to the register */ + val = ((val & ~BOOT_MODE_AUX_MASK) | BOOT_MODE_AUX_MAGIC); + __raw_writel(val, BOOT_MODE_AUX_REG); + } + } else if (val & MPU_WD_RST) { + gd->tomtom.sysboot_mode = SYSBOOT_MODE_WATCHDOG; + } else { + /* treat any other case as watchdog reset */ + gd->tomtom.sysboot_mode = SYSBOOT_MODE_WATCHDOG; + } + + /* reset all bits in PRM_RSTTST */ + __raw_writel(0xFFFFFFFF, PRM_RSTTST); +} diff --git a/board/tomtom/plat-omap3/flipflop.c b/board/tomtom/plat-omap3/flipflop.c new file mode 100644 index 000000000..d28696d50 --- /dev/null +++ b/board/tomtom/plat-omap3/flipflop.c @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2010 TomTom BV + * Author: Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Implementation of the flip-flop. This can store 1 bit of information + * across a (watchdog) reset. + */ + +#include + +#ifdef CONFIG_SW_FLIPFLOP + +#include +#include +#include + +#define FLIP_FLOP_LOCATION (OMAP34XX_CTRL_BASE + 0x09FC) +#define FLIP_FLOP_BIT 31 + +void flipflop_set(int state) +{ + unsigned long value= readl(FLIP_FLOP_LOCATION); + + if (state) + value |= (1 << FLIP_FLOP_BIT); + else + value &= ~(1 << FLIP_FLOP_BIT); + + writel(value, FLIP_FLOP_LOCATION); +} + +int flipflop_get(void) +{ + const unsigned long value = readl(FLIP_FLOP_LOCATION); + + return (value & (1 << FLIP_FLOP_BIT)); +} + +void epicfail_reset(void) +{ + writel(readl(FLIP_FLOP_LOCATION) & ~(1 << EPICFAIL_BIT), + FLIP_FLOP_LOCATION); +} + +#endif diff --git a/board/tomtom/plat-omap3/watchdog.c b/board/tomtom/plat-omap3/watchdog.c new file mode 100644 index 000000000..492f177d3 --- /dev/null +++ b/board/tomtom/plat-omap3/watchdog.c @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2010 TomTom BV + * Author: Matthias Kaehlcke + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Watchdog driver for OMAP3 */ + +#include + +#if defined(CONFIG_HW_WATCHDOG) + +#include +#include +#include +#include + +#define WDT_DISABLE1 0xAAAA +#define WDT_DISABLE2 0x5555 +#define WDT_ENABLE1 0xBBBB +#define WDT_ENABLE2 0x4444 + +#define WDT_TIMEOUT 60 /* watchdog timeout in seconds */ +#define WDT_LOAD_VAL (0xFFFFFFFFUL - (WDT_TIMEOUT * 32768)) /* default clock: 32kHz */ + +struct { +#define WD_NOT_ARMED 0 +#define WD_ARMED 1 + int armed; /* Is the watchdog armed (enabled)? */ +} +wd_state; + +#define is_armed(wd) (wd.armed == WD_ARMED) + +static inline void wd_write(unsigned int value, unsigned int reg) +{ + __raw_writel(value, WD2_BASE + reg); +} + +static inline unsigned int wd_read(unsigned int reg) +{ + return __raw_readl(WD2_BASE + reg); +} + +static inline void wd_write_sync(unsigned int value, unsigned int reg) +{ + wd_write(value, reg); + + while (wd_read(WWPS)) + ; +} + +static void __wd_start(void) +{ + wd_write_sync(WDT_ENABLE1, WSPR); + wd_write_sync(WDT_ENABLE2, WSPR); +} + +static void wd_start(void) +{ + __wd_start(); + wd_state.armed = WD_ARMED; +} + +static void __wd_stop(void) +{ + wd_write_sync(WDT_DISABLE1, WSPR); + wd_write_sync(WDT_DISABLE2, WSPR); +} + +static void wd_stop(void) +{ + __wd_stop(); + wd_state.armed = WD_NOT_ARMED; +} + +/* initialize the watchdog counter */ +static void wd_mod_count_loadval_prescaler(ulong val, ulong *reg) +{ + if (is_armed(wd_state)) + __wd_stop(); + + wd_write_sync(val, reg); + + if (is_armed(wd_state)) + __wd_start(); +} + +void hw_watchdog_activate(unsigned int activate) +{ + if (activate) { + /* reload the counter */ + hw_watchdog_reset(); + wd_start(); + } else { + wd_stop(); + } +} + +void hw_watchdog_reset(void) +{ + /* read the current trigger value */ + unsigned int trigger_val = wd_read(WTGR); + + /* reload the watchdog counter by changing the value in WTGR */ + trigger_val++; + wd_write_sync(trigger_val, WTGR); +} + +void hw_watchdog_init(void) +{ +#if 0 /* Enabled in x-loader */ + /* enable the watchdog clocks */ + sr32(CM_FCLKEN_WKUP, 5, 1, 1); + sr32(CM_ICLKEN_WKUP, 5, 1, 1); + + /* wait for the watchdog to become accesible */ + wait_on_value(BIT5, 0x00, CM_IDLEST_WKUP, 5); + + wd_state.armed = WD_NOT_ARMED; + + /* start the watchdog */ + wd_mod_count_loadval_prescaler(WDT_LOAD_VAL, WLDR); + hw_watchdog_activate(1); +#else + wd_state.armed = WD_ARMED; +#endif + + /* Linux takes care of things like smart-idle, clockactivity, ... */ +} + +#endif diff --git a/board/total5200/Makefile b/board/total5200/Makefile index a8abd7d78..232956a39 100644 --- a/board/total5200/Makefile +++ b/board/total5200/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o sdram.o +OBJS := $(BOARD).o sdram.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/total5200/config.mk b/board/total5200/config.mk index e7ac93d24..1a7a7cfc1 100644 --- a/board/total5200/config.mk +++ b/board/total5200/config.mk @@ -31,7 +31,7 @@ # 0x00100000 boot from RAM (for testing only) # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE ## Standard: boot high diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c index 1ae24c4f3..1a3518726 100644 --- a/board/total5200/total5200.c +++ b/board/total5200/total5200.c @@ -36,7 +36,7 @@ #include "mt48lc16m16a2-75.h" #endif -phys_size_t initdram (int board_type) +long int initdram (int board_type) { sdram_conf_t sdram_conf; @@ -67,14 +67,14 @@ int checkboard (void) puts ("Board: Total5100 "); #endif - /* - * Retrieve FPGA Revision. - */ - printf ("(FPGA %08lX)\n", *(vu_long *) (CFG_FPGA_BASE + 0x400)); +/* + * Retrieve FPGA Revision. + */ +printf ("(FPGA %08X)\n", *(vu_long *) (CFG_FPGA_BASE + 0x400)); - /* - * Take all peripherals in power-up mode. - */ +/* + * Take all peripherals in power-up mode. + */ #if CONFIG_TOTAL5200_REV==2 *(vu_char *) (CFG_CPLD_BASE + 0x46) = 0x70; #else @@ -109,7 +109,7 @@ void pci_init_board(void) } #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) /* IRDA_1 aka PSC6_3 (pin C13) */ #define GPIO_IRDA_1 0x20000000UL @@ -118,7 +118,7 @@ void init_ide_reset (void) { debug ("init_ide_reset\n"); - /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */ + /* Configure IRDA_1 (PSC6_3) as GPIO output for ATA reset */ *(vu_long *) MPC5XXX_GPIO_ENABLE |= GPIO_IRDA_1; *(vu_long *) MPC5XXX_GPIO_DIR |= GPIO_IRDA_1; } @@ -133,7 +133,7 @@ void ide_set_reset (int idereset) *(vu_long *) MPC5XXX_GPIO_DATA_O |= GPIO_IRDA_1; } } -#endif +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ #ifdef CONFIG_VIDEO_SED13806 #include diff --git a/board/total5200/u-boot.lds b/board/total5200/u-boot.lds new file mode 100644 index 000000000..3cc296848 --- /dev/null +++ b/board/total5200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile new file mode 100644 index 000000000..9a1ea4873 --- /dev/null +++ b/board/tqm5200/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o cmd_stk52xx.o cmd_tb5200.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/tqm5200/cmd_stk52xx.c b/board/tqm5200/cmd_stk52xx.c new file mode 100755 index 000000000..c37d4c662 --- /dev/null +++ b/board/tqm5200/cmd_stk52xx.c @@ -0,0 +1,1221 @@ +/* + * (C) Copyright 2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * STK52XX specific functions + */ +/*#define DEBUG*/ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +#if defined (CONFIG_STK52XX) + +#define DEFAULT_VOL 45 +#define DEFAULT_FREQ 500 +#define DEFAULT_DURATION 200 +#define LEFT 1 +#define RIGHT 2 +#define LEFT_RIGHT 3 +#define BL_OFF 0 +#define BL_ON 1 + +#define SM501_GPIO_CTRL_LOW 0x00000008UL +#define SM501_GPIO_CTRL_HIGH 0x0000000CUL +#define SM501_POWER_MODE0_GATE 0x00000040UL +#define SM501_POWER_MODE1_GATE 0x00000048UL +#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL +#define SM501_GPIO_DATA_LOW 0x00010000UL +#define SM501_GPIO_DATA_HIGH 0x00010004UL +#define SM501_GPIO_DATA_DIR_LOW 0x00010008UL +#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL +#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL + +static int i2s_squarewave(unsigned long duration, unsigned int freq, + unsigned int channel); +static int i2s_sawtooth(unsigned long duration, unsigned int freq, + unsigned int channel); +static void spi_init(void); +static int spi_transmit(unsigned char data); +static void pcm1772_write_reg(unsigned char addr, unsigned char data); +static void set_attenuation(unsigned char attenuation); + +static void spi_init(void) +{ + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; + + /* PSC3 as SPI and GPIOs */ + gpio->port_config &= 0xFFFFF0FF; + gpio->port_config |= 0x00000800; + /* + * Its important to use the correct order when initializing the + * registers + */ + spi->ddr = 0x0F; /* set all SPI pins as output */ + spi->pdr = 0x08; /* set SS high */ + spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */ + spi->cr2 = 0x00; /* normal operation */ + spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */ +} + +static int spi_transmit(unsigned char data) +{ + int dummy; + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; + + spi->dr = data; + /* wait for SPI transmission completed */ + while(!(spi->sr & 0x80)) + { + if (spi->sr & 0x40) /* if write collision occured */ + { + /* do dummy read to clear status register */ + dummy = spi->dr; + printf ("SPI write collision\n"); + return -1; + } + } + return (spi->dr); +} + +static void pcm1772_write_reg(unsigned char addr, unsigned char data) +{ + struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI; + + spi->pdr = 0x00; /* Set SS low */ + spi_transmit(addr); + spi_transmit(data); + /* wait some time to meet MS# hold time of PCM1772 */ + udelay (1); + spi->pdr = 0x08; /* set SS high */ +} + +static void set_attenuation(unsigned char attenuation) +{ + pcm1772_write_reg(0x01, attenuation); /* left channel */ + debug ("PCM1772 attenuation left set to %d.\n", attenuation); + pcm1772_write_reg(0x02, attenuation); /* right channel */ + debug ("PCM1772 attenuation right set to %d.\n", attenuation); +} + +void amplifier_init(void) +{ + static int init_done = 0; + int i; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; + + /* Do this only once, because of the long time delay */ + if (!init_done) { + /* configure PCM1772 audio format as I2S */ + pcm1772_write_reg(0x03, 0x01); + /* enable audio amplifier */ + gpio->sint_gpioe |= 0x02; /* PSC3_5 as GPIO */ + gpio->sint_ode &= ~0x02; /* PSC3_5 is not open Drain */ + gpio->sint_dvo &= ~0x02; /* PSC3_5 is LOW */ + gpio->sint_ddr |= 0x02; /* PSC3_5 as output */ + /* + * wait some time to allow amplifier to recover from shutdown + * mode. + */ + for(i = 0; i < 350; i++) + udelay(1000); + /* + * The used amplifier (LM4867) has a so called "pop and click" + * elmination filter. The input signal of the amplifier must + * exceed a certain level once after power up to activate the + * generation of the output signal. This is achieved by + * sending a low frequent (nearly inaudible) sawtooth with a + * sufficient signal level. + */ + set_attenuation(50); + i2s_sawtooth (200, 5, LEFT_RIGHT); + init_done = 1; + } +} + +static void i2s_init(void) +{ + unsigned long i; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; + + gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */ + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + psc->sicr = 0x22E00000; /* 16 bit data; I2S */ + + *(vu_long *)(CFG_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK + * 5.617 MHz */ + *(vu_long *)(CFG_MBAR + 0x214) |= 0x00000040; /* CDM clock enable + * register */ + psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */ + psc->ctur = 0x0F; /* 16 bit frame width */ + + for(i=0;i<128;i++) + { + psc->psc_buffer_32 = 0; /* clear tx fifo */ + } +} + +static int i2s_play_wave(unsigned long addr, unsigned long len) +{ + unsigned long i; + unsigned char *wave_file = (uchar *)addr + 44; /* quick'n dirty: skip + * wav header*/ + unsigned char swapped[4]; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; + + /* + * play wave file in memory; bytes/words are be swapped + */ + psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); + + for(i = 0;i < (len / 4); i++) { + swapped[3]=*wave_file++; + swapped[2]=*wave_file++; + swapped[1]=*wave_file++; + swapped[0]=*wave_file++; + psc->psc_buffer_32 = *((unsigned long*)swapped); + while (psc->tfnum > 400) { + if(ctrlc()) + return 0; + } + } + while (psc->tfnum > 0); /* wait for fifo empty */ + udelay (100); + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + return 0; +} + +static int i2s_sawtooth(unsigned long duration, unsigned int freq, + unsigned int channel) +{ + long i,j; + unsigned long data; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; + + psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); + + /* + * Generate sawtooth. Start with middle level up to highest level. Then + * go to lowest level and back to middle level. + */ + for(j = 0; j < ((duration * freq) / 1000); j++) { + for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4)))) { + data = (i & 0xFFFF); + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) { + data = (i & 0xFFFF); + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) { + data = (i & 0xFFFF); + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + } + while (psc->tfnum > 0); /* wait for fifo empty */ + udelay (100); + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + + return 0; +} + +static int i2s_squarewave(unsigned long duration, unsigned int freq, + unsigned int channel) +{ + long i,j; + unsigned long data; + struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2; + + psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE); + + /* + * Generate sqarewave. Start with high level, duty cycle 1:1. + */ + for(j = 0; j < ((duration * freq) / 1000); j++) { + for(i = 0; i < (44100/(freq*2)); i ++) { + data = 0x7FFF; + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + for(i = 0; i < (44100/(freq*2)); i ++) { + data = 0x8000; + /* data format: right data left data) */ + if (channel == LEFT_RIGHT) + data |= (data<<16); + if (channel == RIGHT) + data = (data<<16); + psc->psc_buffer_32 = data; + while (psc->tfnum > 400); + } + } + while (psc->tfnum > 0); /* wait for fifo empty */ + udelay (100); + psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); + + return 0; +} + +static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long reg, val, duration; + char *tmp; + unsigned int freq, channel; + unsigned char volume; + int rcode = 1; + +#ifdef CONFIG_STK52XX_REV100 + printf ("Revision 100 of STK52XX not supported!\n"); + return 1; +#endif + spi_init(); + i2s_init(); + amplifier_init(); + + if ((tmp = getenv ("volume")) != NULL) { + volume = simple_strtoul (tmp, NULL, 10); + } else { + volume = DEFAULT_VOL; + } + set_attenuation(volume); + + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strncmp(argv[1],"saw",3) == 0) { + printf ("Play sawtooth\n"); + rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + printf ("Play squarewave\n"); + rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strncmp(argv[1],"saw",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + printf ("Play sawtooth\n"); + rcode = i2s_sawtooth (duration, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + printf ("Play squarewave\n"); + rcode = i2s_squarewave (duration, DEFAULT_FREQ, + LEFT_RIGHT); + return rcode; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 4: + if (strncmp(argv[1],"saw",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + printf ("Play sawtooth\n"); + rcode = i2s_sawtooth (duration, freq, + LEFT_RIGHT); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + printf ("Play squarewave\n"); + rcode = i2s_squarewave (duration, freq, + LEFT_RIGHT); + return rcode; + } else if (strcmp(argv[1],"pcm1772") == 0) { + reg = simple_strtoul(argv[2], NULL, 10); + val = simple_strtoul(argv[3], NULL, 10); + printf("Set PCM1772 %lu. %lu\n", reg, val); + pcm1772_write_reg((uchar)reg, (uchar)val); + return 0; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 5: + if (strncmp(argv[1],"saw",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + if (strncmp(argv[4],"l",1) == 0) + channel = LEFT; + else if (strncmp(argv[4],"r",1) == 0) + channel = RIGHT; + else + channel = LEFT_RIGHT; + printf ("Play squarewave\n"); + rcode = i2s_sawtooth (duration, freq, + channel); + return rcode; + } else if (strncmp(argv[1],"squ",3) == 0) { + duration = simple_strtoul(argv[2], NULL, 10); + freq = (unsigned int)simple_strtoul(argv[3], NULL, 10); + if (strncmp(argv[4],"l",1) == 0) + channel = LEFT; + else if (strncmp(argv[4],"r",1) == 0) + channel = RIGHT; + else + channel = LEFT_RIGHT; + printf ("Play squarewave\n"); + rcode = i2s_squarewave (duration, freq, + channel); + return rcode; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + printf ("Usage:\nsound cmd [arg1] [arg2] ...\n"); + return 1; +} + +static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long length, addr; + unsigned char volume; + int rcode = 1; + char *tmp; + +#ifdef CONFIG_STK52XX_REV100 + printf ("Revision 100 of STK52XX not supported!\n"); + return 1; +#endif + spi_init(); + i2s_init(); + amplifier_init(); + + switch (argc) { + + case 3: + length = simple_strtoul(argv[2], NULL, 16); + addr = simple_strtoul(argv[1], NULL, 16); + break; + + case 2: + if ((tmp = getenv ("filesize")) != NULL) { + length = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No filesize provided\n"); + return 1; + } + addr = simple_strtoul(argv[1], NULL, 16); + + case 1: + if ((tmp = getenv ("filesize")) != NULL) { + length = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No filesize provided\n"); + return 1; + } + if ((tmp = getenv ("loadaddr")) != NULL) { + addr = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No loadaddr provided\n"); + return 1; + } + break; + + default: + printf("Usage:\nwav usage); + return 1; + } + + if ((tmp = getenv ("volume")) != NULL) { + volume = simple_strtoul (tmp, NULL, 10); + } else { + volume = DEFAULT_VOL; + } + set_attenuation(volume); + + printf("Beep on "); + if (channel == LEFT) + printf ("left "); + else if (channel == RIGHT) + printf ("right "); + else + printf ("left and right "); + printf ("channel\n"); + + rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel); + + return rcode; +} + +void led_init(void) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + /* configure PSC3 for SPI and GPIO */ + gpio->port_config &= ~(0x00000F00); + gpio->port_config |= 0x00000800; + + gpio->simple_gpioe &= ~(0x00000F00); + gpio->simple_gpioe |= 0x00000F00; + + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000F00; + + /* configure timer 4-7 for simple GPIO output */ + gpt->gpt4.emsr |= 0x00000024; + gpt->gpt5.emsr |= 0x00000024; + gpt->gpt6.emsr |= 0x00000024; + gpt->gpt7.emsr |= 0x00000024; + + + /* enable SM501 GPIO control (in both power modes) */ + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + + /* configure SM501 gpio pins 24-27 as output */ + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24); + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24); + + /* configure SM501 gpio pins 48-51 as output */ + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16); +} + +/* + * return 1 if led number unknown + * return 0 else + */ +int do_led(char *argv[]) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + switch (simple_strtoul(argv[2], NULL, 10)) { + + case 0: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 8); + } else { + gpio->simple_dvo &= ~(1 << 8); + } + break; + + case 1: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 9); + } else { + gpio->simple_dvo &= ~(1 << 9); + } + break; + + case 2: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 10); + } else { + gpio->simple_dvo &= ~(1 << 10); + } + break; + + case 3: + if (strcmp (argv[3], "on") == 0) { + gpio->simple_dvo |= (1 << 11); + } else { + gpio->simple_dvo &= ~(1 << 11); + } + break; + + case 4: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt4.emsr |= (1 << 4); + } else { + gpt->gpt4.emsr &= ~(1 << 4); + } + break; + + case 5: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt5.emsr |= (1 << 4); + } else { + gpt->gpt5.emsr &= ~(1 << 4); + } + break; + + case 6: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt6.emsr |= (1 << 4); + } else { + gpt->gpt6.emsr &= ~(1 << 4); + } + break; + + case 7: + if (strcmp (argv[3], "on") == 0) { + gpt->gpt7.emsr |= (1 << 4); + } else { + gpt->gpt7.emsr &= ~(1 << 4); + } + break; + + case 24: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 24); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 24); + } + break; + + case 25: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 25); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 25); + } + break; + + case 26: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 26); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 26); + } + break; + + case 27: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |= + (0x1 << 27); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &= + ~(0x1 << 27); + } + break; + + case 48: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 16); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 16); + } + break; + + case 49: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 17); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 17); + } + break; + + case 50: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 18); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 18); + } + break; + + case 51: + if (strcmp (argv[3], "on") == 0) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + (0x1 << 19); + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~(0x1 << 19); + } + break; + + default: + printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]); + return 1; + } + + return 0; +} + +/* + * return 1 on CAN initialization failure + * return 0 if no failure + */ +int can_init(void) +{ + static int init_done = 0; + int i; + struct mpc5xxx_mscan *can1 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); + struct mpc5xxx_mscan *can2 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); + + /* GPIO configuration of the CAN pins is done in TQM5200.h */ + + if (!init_done) { + /* init CAN 1 */ + can1->canctl1 |= 0x80; /* CAN enable */ + udelay(100); + + i = 0; + can1->canctl0 |= 0x02; /* sleep mode */ + /* wait until sleep mode reached */ + while (!(can1->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not enter sleep mode!\n", + __FUNCTION__); + return 1; + } + } + i = 0; + can1->canctl0 = 0x01; /* enter init mode */ + /* wait until init mode reached */ + while (!(can1->canctl1 & 0x01)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not enter init mode!\n", + __FUNCTION__); + return 1; + } + } + can1->canctl1 = 0x80; + can1->canctl1 |= 0x40; + can1->canbtr0 = 0x0F; + can1->canbtr1 = 0x7F; + can1->canidac &= ~(0x30); + can1->canidar1 = 0x00; + can1->canidar3 = 0x00; + can1->canidar5 = 0x00; + can1->canidar7 = 0x00; + can1->canidmr0 = 0xFF; + can1->canidmr1 = 0xFF; + can1->canidmr2 = 0xFF; + can1->canidmr3 = 0xFF; + can1->canidmr4 = 0xFF; + can1->canidmr5 = 0xFF; + can1->canidmr6 = 0xFF; + can1->canidmr7 = 0xFF; + + i = 0; + can1->canctl0 &= ~(0x01); /* leave init mode */ + can1->canctl0 &= ~(0x02); + /* wait until init and sleep mode left */ + while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN1 initialize error, " + "can not leave init/sleep mode!\n", + __FUNCTION__); + return 1; + } + } + + /* init CAN 2 */ + can2->canctl1 |= 0x80; /* CAN enable */ + udelay(100); + + i = 0; + can2->canctl0 |= 0x02; /* sleep mode */ + /* wait until sleep mode reached */ + while (!(can2->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not enter sleep mode!\n", + __FUNCTION__); + return 1; + } + } + i = 0; + can2->canctl0 = 0x01; /* enter init mode */ + /* wait until init mode reached */ + while (!(can2->canctl1 & 0x01)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not enter init mode!\n", + __FUNCTION__); + return 1; + } + } + can2->canctl1 = 0x80; + can2->canctl1 |= 0x40; + can2->canbtr0 = 0x0F; + can2->canbtr1 = 0x7F; + can2->canidac &= ~(0x30); + can2->canidar1 = 0x00; + can2->canidar3 = 0x00; + can2->canidar5 = 0x00; + can2->canidar7 = 0x00; + can2->canidmr0 = 0xFF; + can2->canidmr1 = 0xFF; + can2->canidmr2 = 0xFF; + can2->canidmr3 = 0xFF; + can2->canidmr4 = 0xFF; + can2->canidmr5 = 0xFF; + can2->canidmr6 = 0xFF; + can2->canidmr7 = 0xFF; + can2->canctl0 &= ~(0x01); /* leave init mode */ + can2->canctl0 &= ~(0x02); + + i = 0; + /* wait until init mode left */ + while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) { + udelay(10); + i++; + if (i == 10) { + printf ("%s: CAN2 initialize error, " + "can not leave init/sleep mode!\n", + __FUNCTION__); + return 1; + } + } + init_done = 1; + } + return 0; +} + +/* + * return 1 on CAN failure + * return 0 if no failure + */ +int do_can(char *argv[]) +{ + int i; + struct mpc5xxx_mscan *can1 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); + struct mpc5xxx_mscan *can2 = + (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); + + /* send a message on CAN1 */ + can1->cantbsel = 0x01; + can1->cantxfg.idr[0] = 0x55; + can1->cantxfg.idr[1] = 0x00; + can1->cantxfg.idr[1] &= ~0x8; + can1->cantxfg.idr[1] &= ~0x10; + can1->cantxfg.dsr[0] = 0xCC; + can1->cantxfg.dlr = 1; + can1->cantxfg.tbpr = 0; + can1->cantflg = 0x01; + + i = 0; + while ((can1->cantflg & 0x01) == 0) { + i++; + if (i == 10) { + printf ("%s: CAN1 send timeout, " + "can not send message!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + udelay(1000); + + i = 0; + while (!(can2->canrflg & 0x01)) { + i++; + if (i == 10) { + printf ("%s: CAN2 receive timeout, " + "no message received!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + + if (can2->canrxfg.dsr[0] != 0xCC) { + printf ("%s: CAN2 receive error, " + "data mismatch!\n", + __FUNCTION__); + return 1; + } + + /* send a message on CAN2 */ + can2->cantbsel = 0x01; + can2->cantxfg.idr[0] = 0x55; + can2->cantxfg.idr[1] = 0x00; + can2->cantxfg.idr[1] &= ~0x8; + can2->cantxfg.idr[1] &= ~0x10; + can2->cantxfg.dsr[0] = 0xCC; + can2->cantxfg.dlr = 1; + can2->cantxfg.tbpr = 0; + can2->cantflg = 0x01; + + i = 0; + while ((can2->cantflg & 0x01) == 0) { + i++; + if (i == 10) { + printf ("%s: CAN2 send error, " + "can not send message!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + udelay(1000); + + i = 0; + while (!(can1->canrflg & 0x01)) { + i++; + if (i == 10) { + printf ("%s: CAN1 receive timeout, " + "no message received!\n", + __FUNCTION__); + return 1; + } + udelay(1000); + } + + if (can1->canrxfg.dsr[0] != 0xCC) { + printf ("%s: CAN1 receive error 0x%02x\n", + __FUNCTION__, (can1->canrxfg.dsr[0])); + return 1; + } + + return 0; +} + +/* + * return 1 if rs232 port unknown + * return 2 on txd/rxd failure (only rs232 2) + * return 3 on rts/cts failure + * return 0 if no failure + */ +int do_rs232(char *argv[]) +{ + int error_status = 0; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; + + switch (simple_strtoul(argv[2], NULL, 10)) { + + case 1: + /* check RTS <-> CTS loop */ + /* set rts to 0 */ + psc1->op1 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 0) { + error_status = 3; + printf ("%s: failure at rs232_1, cts status is %d " + "(should be 0)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + + /* set rts to 1 */ + psc1->op0 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 1) { + error_status = 3; + printf ("%s: failure at rs232_1, cts status is %d " + "(should be 1)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + + break; + + case 2: + /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000500; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000200) { + error_status = 2; + printf ("%s: failure at rs232_2, rxd status is %d " + "(should be 1)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000000) { + error_status = 2; + printf ("%s: failure at rs232_2, rxd status is %d " + "(should be 0)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000800) { + error_status = 3; + printf ("%s: failure at rs232_2, cts status is %d " + "(should be 1)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000000) { + error_status = 3; + printf ("%s: failure at rs232_2, cts status is %d " + "(should be 0)\n", + __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + + /* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */ + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000F00; + break; + + default: + printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); + error_status = 1; + break; + } + + return error_status; +} + +static void sm501_backlight (unsigned int state) +{ + if (state == BL_ON) { + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= + (1 << 26) | (1 << 27); + } else if (state == BL_OFF) + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= + ~((1 << 26) | (1 << 27)); +} + +int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode; + +#ifdef CONFIG_STK52XX_REV100 + printf ("Revision 100 of STK52XX not supported!\n"); + return 1; +#endif + led_init(); + can_init(); + + switch (argc) { + + case 0: + case 1: + break; + + case 2: + if (strncmp (argv[1], "can", 3) == 0) { + rcode = do_can (argv); + if (rcode == 0) + printf ("OK\n"); + else + printf ("Error\n"); + return rcode; + } + break; + + case 3: + if (strncmp (argv[1], "rs232", 3) == 0) { + rcode = do_rs232 (argv); + if (rcode == 0) + printf ("OK\n"); + else + printf ("Error\n"); + return rcode; + } else if (strncmp (argv[1], "backlight", 4) == 0) { + if (strncmp (argv[2], "on", 2) == 0) { + sm501_backlight (BL_ON); + return 0; + } + else if (strncmp (argv[2], "off", 3) == 0) { + sm501_backlight (BL_OFF); + return 0; + } + } + break; + + case 4: + if (strcmp (argv[1], "led") == 0) { + return (do_led (argv)); + } + break; + + default: + break; + } + + printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n"); + return 1; +} + + +U_BOOT_CMD( + sound , 5, 1, cmd_sound, + "sound - Sound sub-system\n", + "saw [duration] [freq] [channel]\n" + " - generate sawtooth for 'duration' ms with frequency 'freq'\n" + " on left \"l\" or right \"r\" channel\n" + "sound square [duration] [freq] [channel]\n" + " - generate squarewave for 'duration' ms with frequency 'freq'\n" + " on left \"l\" or right \"r\" channel\n" + "pcm1772 reg val\n" +); + +U_BOOT_CMD( + wav , 3, 1, cmd_wav, + "wav - play wav file\n", + "[addr] [bytes]\n" + " - play wav file at address 'addr' with length 'bytes'\n" +); + +U_BOOT_CMD( + beep , 2, 1, cmd_beep, + "beep - play short beep\n", + "[channel]\n" + " - play short beep on \"l\"eft or \"r\"ight channel\n" +); + +U_BOOT_CMD( + fkt , 4, 1, cmd_fkt, + "fkt - Function test routines\n", + "led number on/off\n" + " - 'number's like printed on STK52XX board\n" + "fkt can\n" + " - loopback plug for X83 required\n" + "fkt rs232 number\n" + " - loopback plug(s) for X2 required\n" + "fkt backlight on/off\n" + " - switch backlight on or off\n" +); +#endif /* CONFIG_STK52XX */ +#endif /* CFG_CMD_BSP */ diff --git a/board/tqm5200/cmd_tb5200.c b/board/tqm5200/cmd_tb5200.c new file mode 100644 index 000000000..8784b1f80 --- /dev/null +++ b/board/tqm5200/cmd_tb5200.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2005 - 2006 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * TB5200 specific functions + */ +/*#define DEBUG*/ + +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) +#if defined (CONFIG_TB5200) + +#define SM501_PANEL_DISPLAY_CONTROL 0x00080000UL + +static void led_init(void) +{ + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + /* configure timer 4 for simple GPIO output */ + gpt->gpt4.emsr |= 0x00000024; +} + +int cmd_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + led_init(); + + if (strcmp (argv[1], "on") == 0) { + debug ("switch status LED on\n"); + gpt->gpt4.emsr |= (1 << 4); + } else if (strcmp (argv[1], "off") == 0) { + debug ("switch status LED off\n"); + gpt->gpt4.emsr &= ~(1 << 4); + } else { + printf ("Usage:\nled on/off\n"); + return 1; + } + + return 0; +} + +static void sm501_backlight (unsigned int state) +{ + if (state == 1) { + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |= + (1 << 26) | (1 << 27); + } else if (state == 0) + *(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &= + ~((1 << 26) | (1 << 27)); +} + +int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (strcmp (argv[1], "on") == 0) { + debug ("switch backlight on\n"); + sm501_backlight (1); + } else if (strcmp (argv[1], "off") == 0) { + debug ("switch backlight off\n"); + sm501_backlight (0); + } else { + printf ("Usage:\nbacklight on/off\n"); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + led , 2, 1, cmd_led, + "led - switch status LED on or off\n", + "on/off\n" +); + +U_BOOT_CMD( + backlight , 2, 1, cmd_backlight, + "backlight - switch backlight on or off\n", + "on/off\n" + ); + +#endif /* CONFIG_STK52XX */ +#endif /* CFG_CMD_BSP */ diff --git a/board/tqm5200/config.mk b/board/tqm5200/config.mk new file mode 100644 index 000000000..84ddee80d --- /dev/null +++ b/board/tqm5200/config.mk @@ -0,0 +1,46 @@ +# +# (C) Copyright 2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM5200 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFC000000 boot low (standard configuration with room for max 64 MByte +# Flash ROM) +# 0xFFF00000 boot high (for a backup copy of U-Boot) +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot low +TEXT_BASE = 0xFC000000 +## For a backup copy of U-Boot at the end of flash: boot high +# TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/tqm5200/flash.c b/board/tqm5200/flash.c new file mode 100644 index 000000000..af4d78a95 --- /dev/null +++ b/board/tqm5200/flash.c @@ -0,0 +1,497 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * CPU to flash interface is 32-bit, so make declaration accordingly + */ +typedef unsigned long FLASH_PORT_WIDTH; +typedef volatile unsigned long FLASH_PORT_WIDTHV; + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); +static flash_info_t *flash_get_info(ulong base); + +/*----------------------------------------------------------------------- + * flash_init() + * + * sets up flash_info and returns size of FLASH (bytes) + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + extern void flash_preinit(void); + ulong flashbase = CFG_FLASH_BASE; + + flash_preinit(); + + /* Init: no FLASHes known */ + memset(&flash_info[0], 0, sizeof(flash_info_t)); + + flash_info[0].size = + flash_get_size((FPW *)flashbase, &flash_info[0]); + + size = flash_info[0].size; + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + return size ? size : 1; +} + +/*----------------------------------------------------------------------- + */ +static void flash_reset(flash_info_t *info) +{ + FPWV *base = (FPWV *)(info->start[0]); + + /* Put FLASH back in read mode */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) + *base = (FPW)0x00F000F0; /* AMD Read Mode */ +} + +/*----------------------------------------------------------------------- + */ + +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && info->start[0] <= base && + base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} + +/*----------------------------------------------------------------------- + */ + +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMLV128U: + printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); + break; + case FLASH_AM160B: + printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, + info->sector_count); + + printf (" Sector Start Addresses:"); + + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +ulong flash_get_size (FPWV *addr, flash_info_t *info) +{ + int i; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ + + /* The manufacturer codes are only 1 byte, so just use 1 byte. + * This works for any bus width and any FLASH device width. + */ + udelay(100); + switch (addr[0] & 0xff) { + + case (uchar)AMD_MANUFACT: + debug ("Manufacturer: AMD (Spansion)\n"); + info->flash_id = FLASH_MAN_AMD; + break; + + case (uchar)INTEL_MANUFACT: + debug ("Manufacturer: Intel (not supported yet)\n"); + info->flash_id = FLASH_MAN_INTEL; + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + + /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ + if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) { + + case (FPW)AMD_ID_LV160B: + debug ("Chip: AM29LV160MB\n"); + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + /* + * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all + * the other ones are 64 kB + */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for( i = 4; i < info->sector_count; i++ ) + info->start[i] = + base + (i * 2 * (64 << 10)) - 0x00060000; + break; /* => 4 MB */ + + case AMD_ID_MIRROR: + debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", + addr[14], addr[15]); + + switch(addr[14]) { + case AMD_ID_LV128U_2: + if (addr[15] != AMD_ID_LV128U_3) { + debug ("Chip: AM29LVxxxM -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + } else { + debug ("Chip: AM29LV128M\n"); + info->flash_id += FLASH_AMLV128U; + info->sector_count = 256; + info->size = 0x02000000; + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 0x20000; + } + } + break; /* => 32 MB */ + default: + debug ("Chip: *** unknown ***\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + break; + } + break; + + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + } + + /* Put FLASH back in read mode */ + flash_reset(info); + + return (info->size); +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + debug ("flash_erase: first: %d last: %d\n", s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + /* + * Get lower word aligned address. Assumes 32 bit flash bus width. + */ + wp = (addr & ~3); + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word_amd(info, (FPW *)wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) +{ + ulong start; + int flag; + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + base = (FPWV *)(info->start[0]); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + start = get_timer (0); + + /* data polling for D7 */ + while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + return (1); + } + } + return (0); +} diff --git a/board/tqm5200/mt48lc16m16a2-75.h b/board/tqm5200/mt48lc16m16a2-75.h new file mode 100644 index 000000000..3f1e1691b --- /dev/null +++ b/board/tqm5200/mt48lc16m16a2-75.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +/* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +/* #define SDRAM_CONFIG1 0xD2222800 */ /* CAS latency 2 */ +/*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ +#define SDRAM_CONFIG2 0x8AD70000 +/*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c new file mode 100644 index 000000000..d6f7737d5 --- /dev/null +++ b/board/tqm5200/tqm5200.c @@ -0,0 +1,699 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004-2006 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CONFIG_VIDEO_SM501 +#include +#endif + +#if defined(CONFIG_MPC5200_DDR) +#include "mt46v16m16-75.h" +#else +#include "mt48lc16m16a2-75.h" +#endif + +#ifdef CONFIG_PS2MULT +void ps2mult_early_init(void); +#endif + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | + hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +#if defined(CONFIG_MPC5200) +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; + uint svr, pvr; + +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */ + + /* find RAM size using SDRAM CS1 only */ + sdram_start(0); + test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } +#endif /* CFG_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + +#if defined(CONFIG_TQM5200_B) + return dramsize + dramsize2; +#else + return dramsize; +#endif /* CONFIG_TQM5200_B */ +} + +#elif defined(CONFIG_MGT5100) + +long int initdram (int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup and enable SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; + *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + + /* address select register */ + *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; + __asm__ volatile ("sync"); + + /* find RAM size */ + sdram_start(0); + test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* set SDRAM end address according to size */ + *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); + +#else /* CFG_RAMBOOT */ + + /* Retrieve amount of SDRAM available */ + dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); + +#endif /* CFG_RAMBOOT */ + + return dramsize; +} + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif + +int checkboard (void) +{ +#if defined(CONFIG_AEVFIFO) + puts ("Board: AEVFIFO\n"); + return 0; +#endif + +#if defined(CONFIG_TQM5200S) +# define MODULE_NAME "TQM5200S" +#else +# define MODULE_NAME "TQM5200" +#endif + +#if defined(CONFIG_STK52XX) +# define CARRIER_NAME "STK52xx" +#elif defined(CONFIG_TB5200) +# define CARRIER_NAME "TB5200" +#elif defined(CONFIG_CAM5200) +# define CARRIER_NAME "Cam5200" +#else +# error "Unknown carrier board" +#endif + + puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n" + " on a " CARRIER_NAME " carrier board\n"); + + return 0; +} + +#undef MODULE_NAME +#undef CARRIER_NAME + +void flash_preinit(void) +{ + /* + * Now, when we are in RAM, enable flash write + * access for detection process. + * Note that CS_BOOT cannot be cleared when + * executing in flash. + */ +#if defined(CONFIG_MGT5100) + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ + *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ +#endif + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ +} + + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +#if defined (CONFIG_MINIFAP) +#define SM501_POWER_MODE0_GATE 0x00000040UL +#define SM501_POWER_MODE1_GATE 0x00000048UL +#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL +#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL +#define SM501_GPIO_DATA_HIGH 0x00010004UL +#define SM501_GPIO_51 0x00080000UL +#else +#define GPIO_PSC1_4 0x01000000UL +#endif + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + +#if defined (CONFIG_MINIFAP) + /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */ + + /* enable GPIO control (in both power modes) */ + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |= + POWER_MODE_GATE_GPIO_PWM_I2C; + /* configure GPIO51 as output */ + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= + SM501_GPIO_51; +#else + /* Configure PSC1_4 as GPIO output for ATA reset */ + *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; + *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; +#endif +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + +#if defined (CONFIG_MINIFAP) + if (idereset) { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &= + ~SM501_GPIO_51; + } else { + *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |= + SM501_GPIO_51; + } +#else + if (idereset) { + *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4; + } else { + *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4; + } +#endif +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#ifdef CONFIG_POST +/* + * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3 + * is left open, no keypress is detected. + */ +int post_hotkeys_pressed(void) +{ + struct mpc5xxx_gpio *gpio; + + gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; + + /* + * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in + * CODEC or UART mode. Consumer IrDA should still be possible. + */ + gpio->port_config &= ~(0x07000000); + gpio->port_config |= 0x03000000; + + /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ + gpio->simple_gpioe |= 0x20000000; + + /* Configure GPIO_IRDA_1 as input */ + gpio->simple_ddr &= ~(0x20000000); + + return ((gpio->simple_ival & 0x20000000) ? 0 : 1); +} +#endif + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + +void post_word_store (ulong a) +{ + volatile ulong *save_addr = + (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + + *save_addr = a; +} + +ulong post_word_load (void) +{ + volatile ulong *save_addr = + (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + + return *save_addr; +} +#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ + +#ifdef CONFIG_PS2MULT +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ + ps2mult_early_init(); + return (0); +} +#endif +#endif /* CONFIG_PS2MULT */ + +int last_stage_init (void) +{ + /* + * auto scan for really existing devices and re-set chip select + * configuration. + */ + u16 save, tmp; + int restore; + + /* + * Check for SRAM and SRAM size + */ + + /* save original SRAM content */ + save = *(volatile u16 *)CFG_CS2_START; + restore = 1; + + /* write test pattern to SRAM */ + *(volatile u16 *)CFG_CS2_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in SRAM detection\n"); + + if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) { + /* no SRAM at all, disable cs */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); + *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; + *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; + restore = 0; + __asm__ volatile ("sync"); + } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) { + /* make sure that we access a mirrored address */ + *(volatile u16 *)CFG_CS2_START = 0x1111; + __asm__ volatile ("sync"); + if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) { + /* SRAM size = 512 kByte */ + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, + 0x80000); + __asm__ volatile ("sync"); + puts ("SRAM: 512 kB\n"); + } + else + puts ("!! possible error in SRAM detection\n"); + } else { + puts ("SRAM: 1 MB\n"); + } + /* restore origianl SRAM content */ + if (restore) { + *(volatile u16 *)CFG_CS2_START = save; + __asm__ volatile ("sync"); + } + + /* + * Check for Grafic Controller + */ + + /* save origianl FB content */ + save = *(volatile u16 *)CFG_CS1_START; + restore = 1; + + /* write test pattern to FB memory */ + *(volatile u16 *)CFG_CS1_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in grafic controller detection\n"); + + if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + /* no grafic controller at all, disable cs */ + *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); + *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; + *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF; + restore = 0; + __asm__ volatile ("sync"); + } else { + puts ("VGA: SMI501 (Voyager) with 8 MB\n"); + } + /* restore origianl FB content */ + if (restore) { + *(volatile u16 *)CFG_CS1_START = save; + __asm__ volatile ("sync"); + } + + return 0; +} + +#ifdef CONFIG_VIDEO_SM501 + +#define DISPLAY_WIDTH 640 +#define DISPLAY_HEIGHT 480 + +#ifdef CONFIG_VIDEO_SM501_8BPP +#error CONFIG_VIDEO_SM501_8BPP not supported. +#endif /* CONFIG_VIDEO_SM501_8BPP */ + +#ifdef CONFIG_VIDEO_SM501_16BPP +#error CONFIG_VIDEO_SM501_16BPP not supported. +#endif /* CONFIG_VIDEO_SM501_16BPP */ +#ifdef CONFIG_VIDEO_SM501_32BPP +static const SMI_REGS init_regs [] = +{ +#if 0 /* CRT only */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x10090a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x10090a01}, + {0x00054, 0x0}, + {0x80200, 0x00010000}, + {0x80204, 0x0}, + {0x80208, 0x0A000A00}, + {0x8020C, 0x02fa027f}, + {0x80210, 0x004a028b}, + {0x80214, 0x020c01df}, + {0x80218, 0x000201e9}, + {0x80200, 0x00013306}, +#else /* panel + CRT */ + {0x00004, 0x0}, + {0x00048, 0x00021807}, + {0x0004C, 0x091a0a01}, + {0x00054, 0x1}, + {0x00040, 0x00021807}, + {0x00044, 0x091a0a01}, + {0x00054, 0x0}, + {0x80000, 0x0f013106}, + {0x80004, 0xc428bb17}, + {0x8000C, 0x00000000}, + {0x80010, 0x0a000a00}, + {0x80014, 0x02800000}, + {0x80018, 0x01e00000}, + {0x8001C, 0x00000000}, + {0x80020, 0x01e00280}, + {0x80024, 0x02fa027f}, + {0x80028, 0x004a028b}, + {0x8002C, 0x020c01df}, + {0x80030, 0x000201e9}, + {0x80200, 0x00010000}, +#endif + {0, 0} +}; +#endif /* CONFIG_VIDEO_SM501_32BPP */ + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +/* + * Return text to be printed besides the logo. + */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { + strcpy (info, " Board: TQM5200 (TQ-Components GmbH)"); +#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) + } else if (line_number == 2) { +#if defined (CONFIG_STK52XX) + strcpy (info, " on a STK52xx carrier board"); +#endif +#if defined (CONFIG_TB5200) + strcpy (info, " on a TB5200 carrier board"); +#endif +#endif + } + else { + info [0] = '\0'; + } +} +#endif + +/* + * Returns SM501 register base address. First thing called in the + * driver. Checks if SM501 is physically present. + */ +unsigned int board_video_init (void) +{ + u16 save, tmp; + int restore, ret; + + /* + * Check for Grafic Controller + */ + + /* save origianl FB content */ + save = *(volatile u16 *)CFG_CS1_START; + restore = 1; + + /* write test pattern to FB memory */ + *(volatile u16 *)CFG_CS1_START = 0xA5A5; + __asm__ volatile ("sync"); + /* + * Put a different pattern on the data lines: otherwise they may float + * long enough to read back what we wrote. + */ + tmp = *(volatile u16 *)CFG_FLASH_BASE; + if (tmp == 0xA5A5) + puts ("!! possible error in grafic controller detection\n"); + + if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + /* no grafic controller found */ + restore = 0; + ret = 0; + } else { + ret = SM501_MMIO_BASE; + } + + if (restore) { + *(volatile u16 *)CFG_CS1_START = save; + __asm__ volatile ("sync"); + } + return ret; +} + +/* + * Returns SM501 framebuffer address + */ +unsigned int board_video_get_fb (void) +{ + return SM501_FB_BASE; +} + +/* + * Called after initializing the SM501 and before clearing the screen. + */ +void board_validate_screen (unsigned int base) +{ +} + +/* + * Return a pointer to the initialization sequence. + */ +const SMI_REGS *board_get_regs (void) +{ + return init_regs; +} + +int board_get_width (void) +{ + return DISPLAY_WIDTH; +} + +int board_get_height (void) +{ + return DISPLAY_HEIGHT; +} + +#endif /* CONFIG_VIDEO_SM501 */ diff --git a/board/tqm5200/u-boot.lds b/board/tqm5200/u-boot.lds new file mode 100644 index 000000000..3cc296848 --- /dev/null +++ b/board/tqm5200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm8260/Makefile b/board/tqm8260/Makefile new file mode 100644 index 000000000..c10b9fee6 --- /dev/null +++ b/board/tqm8260/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/tqm8260/config.mk b/board/tqm8260/config.mk new file mode 100644 index 000000000..1fe99524c --- /dev/null +++ b/board/tqm8260/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM8260 boards +# + +# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# +TEXT_BASE = 0x40000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/tqm8260/flash.c b/board/tqm8260/flash.c new file mode 100644 index 000000000..056fe810b --- /dev/null +++ b/board/tqm8260/flash.c @@ -0,0 +1,488 @@ +/* + * (C) Copyright 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Flash Routines for AMD devices on the TQM8260 board + * + *-------------------------------------------------------------------- + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#define V_ULONG(a) (*(volatile unsigned long *)( a )) +#define V_BYTE(a) (*(volatile unsigned char *)( a )) + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + + +/*----------------------------------------------------------------------- + */ +void flash_reset (void) +{ + if (flash_info[0].flash_id != FLASH_UNKNOWN) { + V_ULONG (flash_info[0].start[0]) = 0x00F000F0; + V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0; + } +} + +/*----------------------------------------------------------------------- + */ +ulong flash_get_size (ulong baseaddr, flash_info_t * info) +{ + short i; + unsigned long flashtest_h, flashtest_l; + + /* Write auto select command sequence and test FLASH answer */ + V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA; + V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055; + V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090; + V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA; + V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055; + V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090; + + flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */ + flashtest_l = V_ULONG (baseaddr + 4); + + switch ((int) flashtest_h) { + case AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + flashtest_h = V_ULONG (baseaddr + 8); /* device ID */ + flashtest_l = V_ULONG (baseaddr + 12); + if (flashtest_h != flashtest_l) { + info->flash_id = FLASH_UNKNOWN; + } else { + switch (flashtest_h) { + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00400000; + break; /* 4 * 1 MB = 4 MB */ + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00400000; + break; /* 4 * 1 MB = 4 MB */ + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00800000; + break; /* 4 * 2 MB = 8 MB */ + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00800000; + break; /* 4 * 2 MB = 8 MB */ + case AMD_ID_DL322T: + info->flash_id += FLASH_AMDL322T; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_DL322B: + info->flash_id += FLASH_AMDL322B; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_DL323T: + info->flash_id += FLASH_AMDL323T; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_DL323B: + info->flash_id += FLASH_AMDL323B; + info->sector_count = 71; + info->size = 0x01000000; + break; /* 4 * 4 MB = 16 MB */ + case AMD_ID_LV640U: + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x02000000; + break; /* 4 * 8 MB = 32 MB */ + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* no or unknown flash */ + } + } + + if (flashtest_h == AMD_ID_LV640U) { + + /* set up sector start adress table (uniform sector type) */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = baseaddr + (i * 0x00040000); + + } else if (info->flash_id & FLASH_BTYPE) { + + /* set up sector start adress table (bottom sector type) */ + info->start[0] = baseaddr + 0x00000000; + info->start[1] = baseaddr + 0x00010000; + info->start[2] = baseaddr + 0x00018000; + info->start[3] = baseaddr + 0x00020000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; + } + + } else { + + /* set up sector start adress table (top sector type) */ + i = info->sector_count - 1; + info->start[i--] = baseaddr + info->size - 0x00010000; + info->start[i--] = baseaddr + info->size - 0x00018000; + info->start[i--] = baseaddr + info->size - 0x00020000; + for (; i >= 0; i--) { + info->start[i] = baseaddr + i * 0x00040000; + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + if ((V_ULONG (info->start[i] + 16) & 0x00010001) || + (V_ULONG (info->start[i] + 20) & 0x00010001)) { + info->protect[i] = 1; /* D0 = 1 if protected */ + } else { + info->protect[i] = 0; + } + } + + flash_reset (); + return (info->size); +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size_b0 = 0; + int i; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here (only one bank) */ + + size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]); + if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 >> 20); + } + + /* + * protect monitor and environment sectors + */ + +#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); +#endif + +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + + return (size_b0); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf ("AMD "); + break; + case FLASH_MAN_FUJ: + printf ("FUJITSU "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM800T: + printf ("29LV800T (8 M, top sector)\n"); + break; + case FLASH_AM800B: + printf ("29LV800T (8 M, bottom sector)\n"); + break; + case FLASH_AM160T: + printf ("29LV160T (16 M, top sector)\n"); + break; + case FLASH_AM160B: + printf ("29LV160B (16 M, bottom sector)\n"); + break; + case FLASH_AMDL322T: + printf ("29DL322T (32 M, top sector)\n"); + break; + case FLASH_AMDL322B: + printf ("29DL322B (32 M, bottom sector)\n"); + break; + case FLASH_AMDL323T: + printf ("29DL323T (32 M, top sector)\n"); + break; + case FLASH_AMDL323B: + printf ("29DL323B (32 M, bottom sector)\n"); + break; + case FLASH_AM640U: + printf ("29LV640D (64 M, uniform sector)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect, l_sect; + ulong start, now, last; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + prot++; + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080; + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; + udelay (1000); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + V_ULONG (info->start[sect]) = 0x00300030; + V_ULONG (info->start[sect] + 4) = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || + (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) + { + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + serial_putc ('.'); + last = now; + } + } + + DONE: + /* reset to read mode */ + flash_reset (); + + printf (" done\n"); + return 0; +} + +static int write_dword (flash_info_t *, ulong, unsigned char *); + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong dp; + static unsigned char bb[8]; + int i, l, rc, cc = cnt; + + dp = (addr & ~7); /* get lower dword aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - dp) != 0) { + for (i = 0; i < 8; i++) + bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++; + if ((rc = write_dword (info, dp, bb)) != 0) { + return (rc); + } + dp += 8; + cc -= 8 - l; + } + + /* + * handle word aligned part + */ + while (cc >= 8) { + if ((rc = write_dword (info, dp, src)) != 0) { + return (rc); + } + dp += 8; + src += 8; + cc -= 8; + } + + if (cc <= 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + for (i = 0; i < 8; i++) { + bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i); + } + return (write_dword (info, dp, bb)); +} + +/*----------------------------------------------------------------------- + * Write a dword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) +{ + ulong start, cl, ch; + int flag, i; + + for (ch = 0, i = 0; i < 4; i++) + ch = (ch << 8) + *pdata++; /* high word */ + for (cl = 0, i = 0; i < 4; i++) + cl = (cl << 8) + *pdata++; /* low word */ + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *) dest) & ch) != ch + || (*((vu_long *) (dest + 4)) & cl) != cl) { + return (2); + } + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0; + V_ULONG (dest) = ch; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; + V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; + V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0; + V_ULONG (dest + 4) = cl; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || + ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} diff --git a/board/tqm8260/tqm8260.c b/board/tqm8260/tqm8260.c new file mode 100644 index 000000000..029863b7d --- /dev/null +++ b/board/tqm8260/tqm8260.c @@ -0,0 +1,368 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ + /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ + /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ + /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ + /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ + /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */ + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + char str[64]; + int i = getenv_r ("serial#", str, sizeof (str)); + + puts ("Board: "); + + if (!i || strncmp (str, "TQM82", 5)) { + puts ("### No HW ID - assuming TQM8260\n"); + return (0); + } + + puts (str); + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; + orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + long size8, size9; +#endif + long psize, lsize; + + psize = 16 * 1024 * 1024; + lsize = 0; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#if 0 /* Just for debugging */ +#define prt_br_or(brX,orX) do { \ + ulong start = memctl->memc_ ## brX & 0xFFFF8000; \ + ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \ + printf ("\n" \ + #brX " 0x%08x " #orX " 0x%08x " \ + "==> 0x%08lx ... 0x%08lx = %ld MB\n", \ + memctl->memc_ ## brX, memctl->memc_ ## orX, \ + start, start+sizem, (sizem+1)>>20); \ + } while (0) + prt_br_or (br0, or0); + prt_br_or (br1, or1); + prt_br_or (br2, or2); + prt_br_or (br3, or3); +#endif + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, + (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, + (uchar *) CFG_SDRAM_BASE); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL - %ld MB, ", psize >> 20); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, + (uchar *) CFG_SDRAM_BASE); + printf ("(60x:8COL - %ld MB, ", psize >> 20); + } + + /* Local SDRAM setup: + */ +#ifdef CFG_INIT_LOCAL_SDRAM + memctl->memc_lsrt = CFG_LSRT; + size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + (uchar *) SDRAM_BASE2_PRELIM); + size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, + (uchar *) SDRAM_BASE2_PRELIM); + + if (size8 < size9) { + lsize = size9; + printf ("Local:9COL - %ld MB) using ", lsize >> 20); + } else { + lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + (uchar *) SDRAM_BASE2_PRELIM); + printf ("Local:8COL - %ld MB) using ", lsize >> 20); + } + +#if 0 + /* Set up BR2 so that the local SDRAM goes + * right after the 60x SDRAM + */ + memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | + (CFG_SDRAM_BASE + psize); +#endif +#endif /* CFG_INIT_LOCAL_SDRAM */ +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +/* ------------------------------------------------------------------------- */ diff --git a/board/tqm8260/u-boot.lds b/board/tqm8260/u-boot.lds new file mode 100644 index 000000000..05f29c6ed --- /dev/null +++ b/board/tqm8260/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm834x/Makefile b/board/tqm834x/Makefile new file mode 100644 index 000000000..3ecc7d090 --- /dev/null +++ b/board/tqm834x/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o pci.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/tqm834x/config.mk b/board/tqm834x/config.mk new file mode 100644 index 000000000..f172c4ede --- /dev/null +++ b/board/tqm834x/config.mk @@ -0,0 +1,23 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x80000000 diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c new file mode 100644 index 000000000..5a23e6c55 --- /dev/null +++ b/board/tqm834x/pci.c @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +#ifdef CONFIG_PCI + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_tqm834x_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } + }, + {} +}; +#endif + +static struct pci_controller pci1_hose = { +#ifndef CONFIG_PCI_PNP + config_table:pci_tqm834x_config_table, +#endif +}; + + +/************************************************************************** + * pci_init_board() + * + * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since + * per TQM834x design physical connections to external devices (PCI sockets) + * are routed only to the PCI1 we do not account for the second one - this code + * supports PCI1 module only. Should support for the PCI2 be required in the + * future it needs a separate pci_controller structure (above) and handling - + * please refer to other boards' implementation for dual PCI host controllers, + * for example board/Marvell/db64360/pci.c, pci_init_board() + * + */ +void +pci_init_board(void) +{ + volatile immap_t * immr; + volatile clk8349_t * clk; + volatile law8349_t * pci_law; + volatile pot8349_t * pci_pot; + volatile pcictrl8349_t * pci_ctrl; + volatile pciconf8349_t * pci_conf; + u16 reg16; + u32 reg32; + struct pci_controller * hose; + + immr = (immap_t *)CFG_IMMRBAR; + clk = (clk8349_t *)&immr->clk; + pci_law = immr->sysconf.pcilaw; + pci_pot = immr->ios.pot; + pci_ctrl = immr->pci_ctrl; + pci_conf = immr->pci_conf; + + hose = &pci1_hose; + + /* + * Configure PCI controller and PCI_CLK_OUTPUT + */ + + /* + * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one + * line actually used for clocking all external PCI devices in TQM83xx. + * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for + * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 + * are known to hang the board; this issue is under investigation + * (13 oct 05) + */ + reg32 = OCCR_PCICOE1; +#if 0 + /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ + reg32 = 0xff000000; +#endif + if (clk->spmr & SPMR_CKID) { + /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR + * fields accordingly */ + reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); + + reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ + | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ + | OCCR_PCICD6 | OCCR_PCICD7); + } + + clk->occr = reg32; + udelay(2000); + + /* + * Release PCI RST Output signal + */ + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + udelay(2000); + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; + + /* + * Configure PCI Outbound Translation Windows + */ + + /* PCI1 mem space */ + pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); + + /* PCI1 IO space */ + pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); + + /* + * Configure PCI Inbound Translation Windows + */ + + /* we need RAM mapped to PCI space for the devices to + * access main memory */ + pci_ctrl[0].pitar1 = 0x0; + pci_ctrl[0].pibar1 = 0x0; + pci_ctrl[0].piebar1 = 0x0; + pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M; + + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI memory space */ + pci_set_region(hose->regions + 0, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* PCI IO space */ + pci_set_region(hose->regions + 1, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + /* System memory space */ + pci_set_region(hose->regions + 2, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + CONFIG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 3; + + pci_setup_indirect(hose, + (CFG_IMMRBAR+0x8300), + (CFG_IMMRBAR+0x8304)); + + pci_register_hose(hose); + + /* + * Write to Command register + */ + reg16 = 0xff; + pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, + ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, + reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, + 0xffff); + pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, + 0x80); + +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + /* + * Hose scan. + */ + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCI */ diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c new file mode 100644 index 000000000..41b34cc6f --- /dev/null +++ b/board/tqm834x/tqm834x.c @@ -0,0 +1,435 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define IOSYNC asm("eieio") +#define ISYNC asm("isync") +#define SYNC asm("sync") +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define DDR_MAX_SIZE_PER_CS 0x20000000 + +#if defined(DDR_CASLAT_20) +#define TIMING_CASLAT TIMING_CFG1_CASLAT_20 +#define MODE_CASLAT DDR_MODE_CASLAT_20 +#else +#define TIMING_CASLAT TIMING_CFG1_CASLAT_25 +#define MODE_CASLAT DDR_MODE_CASLAT_25 +#endif + +#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \ + CSCONFIG_COL_BIT_9) + +/* Global variable used to store detected number of banks */ +int tqm834x_num_flash_banks; + +/* External definitions */ +ulong flash_get_size (ulong base, int banknum); +extern flash_info_t flash_info[]; +extern long spd_sdram (void); + +/* Local functions */ +static int detect_num_flash_banks(void); +static long int get_ddr_bank_size(short cs, volatile long *base); +static void set_cs_bounds(short cs, long base, long size); +static void set_cs_config(short cs, long config); +static void set_ddr_config(void); + +/* Local variable */ +static volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + +/************************************************************************** + * Board initialzation after relocation to RAM. Used to detect the number + * of Flash banks on TQM834x. + */ +int board_early_init_r (void) { + /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */ + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return 0; + + /* detect the number of Flash banks */ + return detect_num_flash_banks(); +} + +/************************************************************************** + * DRAM initalization and size detection + */ +long int initdram (int board_type) +{ + long bank_size; + long size; + int cs; + + /* during size detection, set up the max DDRLAW size */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE; + im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); + + /* set CS bounds to maximum size */ + for(cs = 0; cs < 4; ++cs) { + set_cs_bounds(cs, + CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), + DDR_MAX_SIZE_PER_CS); + + set_cs_config(cs, INITIAL_CS_CONFIG); + } + + /* configure ddr controller */ + set_ddr_config(); + + udelay(200); + + /* enable DDR controller */ + im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | + SDRAM_CFG_SREN | + SDRAM_CFG_SDRAM_TYPE_DDR); + SYNC; + + /* size detection */ + debug("\n"); + size = 0; + for(cs = 0; cs < 4; ++cs) { + debug("\nDetecting Bank%d\n", cs); + + bank_size = get_ddr_bank_size(cs, + (volatile long*)(CFG_DDR_BASE + size)); + size += bank_size; + + debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20); + + /* exit if less than one bank */ + if(size < DDR_MAX_SIZE_PER_CS) break; + } + + return size; +} + +/************************************************************************** + * checkboard() + */ +int checkboard (void) +{ + puts("Board: TQM834x\n"); + +#ifdef CONFIG_PCI + volatile immap_t * immr; + u32 w, f; + + immr = (immap_t *)CFG_IMMRBAR; + if (!(immr->reset.rcwh & RCWH_PCIHOST)) { + printf("PCI: NOT in host mode..?!\n"); + return 0; + } + + /* get bus width */ + w = 32; + if (immr->reset.rcwh & RCWH_PCI64) + w = 64; + + /* get clock */ + f = gd->pci_clk; + + printf("PCI1: %d bit, %d MHz\n", w, f / 1000000); +#else + printf("PCI: disabled\n"); +#endif + return 0; +} + + +/************************************************************************** + * + * Local functions + * + *************************************************************************/ + +/************************************************************************** + * Detect the number of flash banks (1 or 2). Store it in + * a global variable tqm834x_num_flash_banks. + * Bank detection code based on the Monitor code. + */ +static int detect_num_flash_banks(void) +{ + typedef unsigned long FLASH_PORT_WIDTH; + typedef volatile unsigned long FLASH_PORT_WIDTHV; + FPWV *bank1_base; + FPWV *bank2_base; + FPW bank1_read; + FPW bank2_read; + ulong bank1_size; + ulong bank2_size; + ulong total_size; + + tqm834x_num_flash_banks = 2; /* assume two banks */ + + /* Get bank 1 and 2 information */ + bank1_size = flash_get_size(CFG_FLASH_BASE, 0); + debug("Bank1 size: %lu\n", bank1_size); + bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1); + debug("Bank2 size: %lu\n", bank2_size); + total_size = bank1_size + bank2_size; + + if (bank2_size > 0) { + /* Seems like we've got bank 2, but maybe it's mirrored 1 */ + + /* Set the base addresses */ + bank1_base = (FPWV *) (CFG_FLASH_BASE); + bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size); + + /* Put bank 2 into CFI command mode and read */ + bank2_base[0x55] = 0x00980098; + IOSYNC; + ISYNC; + bank2_read = bank2_base[0x10]; + + /* Read from bank 1 (it's in read mode) */ + bank1_read = bank1_base[0x10]; + + /* Reset Flash */ + bank1_base[0] = 0x00F000F0; + bank2_base[0] = 0x00F000F0; + + if (bank2_read == bank1_read) { + /* + * Looks like just one bank, but not sure yet. Let's + * read from bank 2 in autosoelect mode. + */ + bank2_base[0x0555] = 0x00AA00AA; + bank2_base[0x02AA] = 0x00550055; + bank2_base[0x0555] = 0x00900090; + IOSYNC; + ISYNC; + bank2_read = bank2_base[0x10]; + + /* Read from bank 1 (it's in read mode) */ + bank1_read = bank1_base[0x10]; + + /* Reset Flash */ + bank1_base[0] = 0x00F000F0; + bank2_base[0] = 0x00F000F0; + + if (bank2_read == bank1_read) { + /* + * In both CFI command and autoselect modes, + * we got the some data reading from Flash. + * There is only one mirrored bank. + */ + tqm834x_num_flash_banks = 1; + total_size = bank1_size; + } + } + } + + debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks); + + /* set OR0 and BR0 */ + im->lbus.bank[0].or = CFG_OR_TIMING_FLASH | + (-(total_size) & OR_GPCM_AM); + im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) | + (BR_MS_GPCM | BR_PS_32 | BR_V); + + return (0); +} + +/************************************************************************* + * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly. + */ +static long int get_ddr_bank_size(short cs, volatile long *base) +{ + /* This array lists all valid DDR SDRAM configurations, with + * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM). + * The last entry has to to have size equal 0 and is igonred during + * autodection. Bank sizes must be in increasing order of size + */ + struct { + long row; + long col; + long size; + } conf[] = { + {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20}, + {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20}, + {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20}, + {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20}, + {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20}, + {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20}, + {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20}, + {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20}, + {0, 0, 0} + }; + + int i; + int detected; + long size; + + detected = -1; + for(i = 0; conf[i].size != 0; ++i) { + + /* set sdram bank configuration */ + set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row); + + debug("Getting RAM size...\n"); + size = get_ram_size(base, DDR_MAX_SIZE_PER_CS); + + if((size == conf[i].size) && (i == detected + 1)) + detected = i; + + debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n", + conf[i].row, + conf[i].col, + conf[i].size >> 20, + base, + size >> 20); + } + + if(detected == -1){ + /* disable empty cs */ + debug("\nNo valid configurations for CS%d, disabling...\n", cs); + set_cs_config(cs, 0); + return 0; + } + + debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n", + conf[detected].row, conf[detected].col, conf[detected].size >> 20, base); + + /* configure cs ro detected params */ + set_cs_config(cs, CSCONFIG_EN | conf[detected].row | + conf[detected].col); + + set_cs_bounds(cs, (long)base, conf[detected].size); + + return(conf[detected].size); +} + +/************************************************************************** + * Sets DDR bank CS bounds. + */ +static void set_cs_bounds(short cs, long base, long size) +{ + debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs); + if(size == 0){ + im->ddr.csbnds[cs].csbnds = 0x00000000; + } else { + im->ddr.csbnds[cs].csbnds = + ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | + (((base + size - 1) >> CSBNDS_EA_SHIFT) & + CSBNDS_EA); + } + SYNC; +} + +/************************************************************************** + * Sets DDR banks CS configuration. + * config == 0x00000000 disables the CS. + */ +static void set_cs_config(short cs, long config) +{ + debug("Setting config %08x for cs %d\n", config, cs); + im->ddr.cs_config[cs] = config; + SYNC; +} + +/************************************************************************** + * Sets DDR clocks, timings and configuration. + */ +static void set_ddr_config(void) { + /* clock control */ + im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN | + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; + SYNC; + + /* timing configuration */ + im->ddr.timing_cfg_1 = + (4 << TIMING_CFG1_PRETOACT_SHIFT) | + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | + (4 << TIMING_CFG1_ACTTORW_SHIFT) | + (5 << TIMING_CFG1_REFREC_SHIFT) | + (3 << TIMING_CFG1_WRREC_SHIFT) | + (3 << TIMING_CFG1_ACTTOACT_SHIFT) | + (1 << TIMING_CFG1_WRTORD_SHIFT) | + (TIMING_CFG1_CASLAT & TIMING_CASLAT); + + im->ddr.timing_cfg_2 = + TIMING_CFG2_CPO_DEF | + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT); + SYNC; + + /* don't enable DDR controller yet */ + im->ddr.sdram_cfg = + SDRAM_CFG_SREN | + SDRAM_CFG_SDRAM_TYPE_DDR; + SYNC; + + /* Set SDRAM mode */ + im->ddr.sdram_mode = + ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) << + SDRAM_MODE_ESD_SHIFT) | + ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) << + SDRAM_MODE_SD_SHIFT) | + ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) & + MODE_CASLAT); + SYNC; + + /* Set fast SDRAM refresh rate */ + im->ddr.sdram_interval = + (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | + (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); + SYNC; + + /* Workaround for DDR6 Erratum + * see MPC8349E Device Errata Rev.8, 2/2006 + * This workaround influences the MPC internal "input enables" + * dependent on CAS latency and MPC revision. According to errata + * sheet the internal reserved registers for this workaround are + * not available from revision 2.0 and up. + */ + + /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0 + * (0x200) + */ + if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) { + + /* There is a internal reserved register at IMMRBAR+0x2F00 + * which has to be written with a certain value defined by + * errata sheet. + */ + u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00); + +#if defined(DDR_CASLAT_20) + *reserved_p = 0x201c0000; +#else + *reserved_p = 0x202c0000; +#endif + } +} diff --git a/board/tqm834x/u-boot.lds b/board/tqm834x/u-boot.lds new file mode 100644 index 000000000..020cfa66f --- /dev/null +++ b/board/tqm834x/u-boot.lds @@ -0,0 +1,122 @@ +/* + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/tqm85xx/Makefile b/board/tqm85xx/Makefile new file mode 100644 index 000000000..3933d46f0 --- /dev/null +++ b/board/tqm85xx/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o sdram.o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/tqm85xx/config.mk b/board/tqm85xx/config.mk new file mode 100644 index 000000000..52e84ad77 --- /dev/null +++ b/board/tqm85xx/config.mk @@ -0,0 +1,29 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# tqm85xx board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 256k +# +TEXT_BASE = 0xfffc0000 diff --git a/board/tqm85xx/init.S b/board/tqm85xx/init.S new file mode 100644 index 000000000..1f610385e --- /dev/null +++ b/board/tqm85xx/init.S @@ -0,0 +1,234 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0, 1: 128M Non-cacheable, guarded + * 0xf8000000 128M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7+8: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + .long TLB1_MAS0(1, 8, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/tqm85xx/sdram.c b/board/tqm85xx/sdram.c new file mode 100644 index 000000000..9c1f08768 --- /dev/null +++ b/board/tqm85xx/sdram.c @@ -0,0 +1,226 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include +#include +#include +#include + +struct sdram_conf_s { + unsigned long size; + unsigned long reg; +}; + +typedef struct sdram_conf_s sdram_conf_t; + +sdram_conf_t ddr_cs_conf[] = { + {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ + {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ + {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ + {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ +}; + +#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0])) + +int cas_latency(void); + +/* + * Autodetect onboard DDR SDRAM on 85xx platforms + * + * NOTE: Some of the hardcoded values are hardware dependant, + * so this should be extended for other future boards + * using this routine! + */ +long int sdram_setup(int casl) +{ + int i; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr; + unsigned long cfg_ddr_timing1; + unsigned long cfg_ddr_mode; + + /* + * Disable memory controller. + */ + ddr->cs0_config = 0; + ddr->sdram_cfg = 0; + + switch (casl) { + case 20: + cfg_ddr_timing1 = 0x47405331 | (3 << 16); + cfg_ddr_mode = 0x40020002 | (2 << 4); + break; + + case 25: + cfg_ddr_timing1 = 0x47405331 | (4 << 16); + cfg_ddr_mode = 0x40020002 | (6 << 4); + break; + + case 30: + default: + cfg_ddr_timing1 = 0x47405331 | (5 << 16); + cfg_ddr_mode = 0x40020002 | (3 << 4); + break; + } + + ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; + ddr->cs0_config = ddr_cs_conf[0].reg; + ddr->timing_cfg_1 = cfg_ddr_timing1; + ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */ + ddr->sdram_mode = cfg_ddr_mode; + ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ + ddr->err_disable = 0x0000000D; + + asm ("sync;isync;msync"); + udelay(1000); + + ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ + asm ("sync; isync; msync"); + udelay(1000); + + for (i=0; ics0_config = ddr_cs_conf[i].reg; + + if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) { + /* + * OK, size detected -> all done + */ + return ddr_cs_conf[i].size; + } + } + + return 0; /* nothing found ! */ +} + +void board_add_ram_info(int use_default) +{ + int casl; + + if (use_default) + casl = CONFIG_DDR_DEFAULT_CL; + else + casl = cas_latency(); + + puts(" (CL="); + switch (casl) { + case 20: + puts("2)"); + break; + + case 25: + puts("2.5)"); + break; + + case 30: + puts("3)"); + break; + } +} + +long int initdram (int board_type) +{ + long dram_size = 0; + int casl; + +#if defined(CONFIG_DDR_DLL) + /* + * This DLL-Override only used on TQM8540 and TQM8560 + */ + { + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_gur_t *gur= &immap->im_gur; + int i,x; + + x = 10; + + /* + * Work around to stabilize DDR DLL + */ + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay (200); + while (gur->ddrdllcr != 0x81000100) { + gur->devdisr = gur->devdisr | 0x00010000; + asm("sync;isync;msync"); + for (i=0; idevdisr = gur->devdisr & 0xfff7ffff; + asm("sync;isync;msync"); + x++; + } + } +#endif + + casl = cas_latency(); + dram_size = sdram_setup(casl); + if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { + /* + * Try again with default CAS latency + */ + puts("Problem with CAS lantency"); + board_add_ram_info(1); + puts(", using default CL!\n"); + casl = CONFIG_DDR_DEFAULT_CL; + dram_size = sdram_setup(casl); + puts(" "); + } + + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf ("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf ("SDRAM test passed.\n"); + return 0; +} +#endif diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c new file mode 100644 index 000000000..b4ef5afe7 --- /dev/null +++ b/board/tqm85xx/tqm85xx.c @@ -0,0 +1,425 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +void local_bus_init (void); +long int fixed_sdram (void); +ulong flash_get_size (ulong base, int banknum); + +#ifdef CONFIG_PS2MULT +void ps2mult_early_init(void); +#endif + +#ifdef CONFIG_CPM2 +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; +#endif /* CONFIG_CPM2 */ + +#define CASL_STRING1 "casl=xx" +#define CASL_STRING2 "casl=" + +static const int casl_table[] = { 20, 25, 30 }; +#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0])) + +int cas_latency(void) +{ + char *s = getenv("serial#"); + int casl; + int val; + int i; + + casl = CONFIG_DDR_DEFAULT_CL; + + if (s != NULL) { + if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2, + strlen(CASL_STRING2)) == 0) { + val = simple_strtoul(s + strlen(s) - 2, NULL, 10); + + for (i=0; iim_lbc; + + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Check if boot FLASH isn't max size + */ + if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { + memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); + memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + } + + /* + * Check if only one FLASH bank is available + */ + if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { + memctl->or1 = 0; + memctl->br1 = 0; + + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + } + + return 0; +} + +/* + * Initialize Local Bus + */ +void local_bus_init (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info (&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->ltedr = 0xa4c80000; /* DK: !!! */ + + } else if (lbc_hz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr (); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + udelay (200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm ("sync;isync;msync"); + } +} + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxads_config_table[] = { + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER}}, + {} +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc85xxads_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void pci_init_board (void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init (struct pci_controller *hose); + + pci_mpc85xx_init (&hose); +#endif /* CONFIG_PCI */ +} + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ +#ifdef CONFIG_PS2MULT + ps2mult_early_init(); +#endif /* CONFIG_PS2MULT */ + return (0); +} +#endif /* CONFIG_BOARD_EARLY_INIT_R */ diff --git a/board/tqm85xx/u-boot.lds b/board/tqm85xx/u-boot.lds new file mode 100644 index 000000000..4cc825bcd --- /dev/null +++ b/board/tqm85xx/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2002,2003, Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/tqm85xx/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/tqm85xx/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm8xx/Makefile b/board/tqm8xx/Makefile new file mode 100644 index 000000000..2ff9b4dab --- /dev/null +++ b/board/tqm8xx/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o flash.o load_sernum_ethaddr.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/tqm8xx/config.mk b/board/tqm8xx/config.mk new file mode 100644 index 000000000..9d6080b84 --- /dev/null +++ b/board/tqm8xx/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM8xxL boards +# + +TEXT_BASE = 0x40000000 diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c new file mode 100644 index 000000000..db0a7e5eb --- /dev/null +++ b/board/tqm8xx/flash.c @@ -0,0 +1,830 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if 0 +#define DEBUG +#endif + +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ + && !defined(CONFIG_TQM885D) +# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ +# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ + OR_SCY_2_CLK | OR_EHTR | OR_BI) +# endif +#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ + +#ifndef CFG_ENV_ADDR +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#endif + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + unsigned long size_b0, size_b1; + int i; + +#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ + int scy, trlx, flash_or_timing, clk_diff; + + scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; + if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { + trlx = OR_TRLX; + scy *= 2; + } else + trlx = 0; + + /* We assume that each 10MHz of bus clock require 1-clk SCY + * adjustment. + */ + clk_diff = (gd->bus_clk / 1000000) - 50; + + /* We need proper rounding here. This is what the "+5" and "-5" + * are here for. + */ + if (clk_diff >= 0) + scy += (clk_diff + 5) / 10; + else + scy += (clk_diff - 5) / 10; + + /* For bus frequencies above 50MHz, we want to use relaxed timing + * (OR_TRLX). + */ + if (gd->bus_clk >= 50000000) + trlx = OR_TRLX; + else + trlx = 0; + + if (trlx) + scy /= 2; + + if (scy > 0xf) + scy = 0xf; + if (scy < 1) + scy = 1; + + flash_or_timing = (scy << 4) | trlx | + (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); +#endif + /* Init: no FLASHes known */ + for (i=0; i size_b0) { + printf ("## ERROR: " + "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", + size_b1, size_b1<<20, + size_b0, size_b0<<20 + ); + flash_info[0].flash_id = FLASH_UNKNOWN; + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[0].sector_count = -1; + flash_info[1].sector_count = -1; + flash_info[0].size = 0; + flash_info[1].size = 0; + return (0); + } + + debug ("## Before remap: " + "BR0: 0x%08x OR0: 0x%08x " + "BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0, + memctl->memc_br1, memctl->memc_or1); + + /* Remap FLASH according to real size */ +#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ + memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); +#else + memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK); +#endif + memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + debug ("## BR0: 0x%08x OR0: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0); + + /* Re-do sizing to get full correct info */ + size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + debug ("Protect monitor: %08lx ... %08lx\n", + (ulong)CFG_MONITOR_BASE, + (ulong)CFG_MONITOR_BASE + monitor_flash_len - 1); + + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ +# ifdef CFG_ENV_ADDR_REDUND + debug ("Protect primary environment: %08lx ... %08lx\n", + (ulong)CFG_ENV_ADDR, + (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1); +# else + debug ("Protect environment: %08lx ... %08lx\n", + (ulong)CFG_ENV_ADDR, + (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1); +# endif + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_ADDR_REDUND + debug ("Protect redundand environment: %08lx ... %08lx\n", + (ulong)CFG_ENV_ADDR_REDUND, + (ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + if (size_b1) { +#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ + memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); +#else + memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000); +#endif + memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + BR_MS_GPCM | BR_V; + + debug ("## BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + + /* Re-do sizing to get full correct info */ + size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + &flash_info[1]); + +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[1]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SIZE-1, + &flash_info[1]); +#endif + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + flash_info[1].size = 0; + + debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + } + + debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + + return (size_b0 + size_b1); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { +#ifdef CONFIG_TQM8xxM /* mirror bit flash */ + case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); + break; + case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n"); + break; + case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n"); + break; + case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n"); + break; +# else /* ! TQM8xxM */ + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); + break; +#endif /* TQM8xxM */ + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AMDL163B: printf ("AM29DL163B (16 Mbit, bottom boot sect)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ + +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value; + ulong base = (ulong)addr; + + /* Write auto select command: read Manufacturer ID */ + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00900090; + + value = addr[0]; + + debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); + + switch (value) { + case AMD_MANUFACT: + debug ("Manufacturer: AMD\n"); + info->flash_id = FLASH_MAN_AMD; + break; + case FUJ_MANUFACT: + debug ("Manufacturer: FUJITSU\n"); + info->flash_id = FLASH_MAN_FUJ; + break; + default: + debug ("Manufacturer: *** unknown ***\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr[1]; /* device ID */ + + debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); + + switch (value) { +#ifdef CONFIG_TQM8xxM /* mirror bit flash */ + case AMD_ID_MIRROR: + debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", + addr[14], addr[15]); + /* Special case for AMLV320MH/L */ + if ((addr[14] & 0x00ff00ff) == 0x001d001d && + (addr[15] & 0x00ff00ff) == 0x00000000) { + debug ("Chip: AMLV320MH/L\n"); + info->flash_id += FLASH_AMLV320U; + info->sector_count = 64; + info->size = 0x00800000; /* => 8 MB */ + break; + } + switch(addr[14]) { + case AMD_ID_LV128U_2: + if (addr[15] != AMD_ID_LV128U_3) { + debug ("Chip: AMLV128U -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + } else { + debug ("Chip: AMLV128U\n"); + info->flash_id += FLASH_AMLV128U; + info->sector_count = 256; + info->size = 0x02000000; + } + break; /* => 32 MB */ + case AMD_ID_LV640U_2: + if (addr[15] != AMD_ID_LV640U_3) { + debug ("Chip: AMLV640U -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + } else { + debug ("Chip: AMLV640U\n"); + info->flash_id += FLASH_AMLV640U; + info->sector_count = 128; + info->size = 0x01000000; + } + break; /* => 16 MB */ + case AMD_ID_LV320B_2: + if (addr[15] != AMD_ID_LV320B_3) { + debug ("Chip: AMLV320B -> unknown\n"); + info->flash_id = FLASH_UNKNOWN; + } else { + debug ("Chip: AMLV320B\n"); + info->flash_id += FLASH_AMLV320B; + info->sector_count = 71; + info->size = 0x00800000; + } + break; /* => 8 MB */ + default: + debug ("Chip: *** unknown ***\n"); + info->flash_id = FLASH_UNKNOWN; + break; + } + break; +# else /* ! TQM8xxM */ + case AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00100000; + break; /* => 1 MB */ + + case AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00200000; + break; /* => 2 MB */ + + case AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ + + case AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00800000; + break; /* => 8 MB */ +#endif /* TQM8xxM */ + + case AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00400000; + break; /* => 4 MB */ + + case AMD_ID_DL163B: + info->flash_id += FLASH_AMDL163B; + info->sector_count = 39; + info->size = 0x00400000; + break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + switch (value) { +#ifdef CONFIG_TQM8xxM /* mirror bit flash */ + case AMD_ID_MIRROR: + switch (info->flash_id & FLASH_TYPEMASK) { + /* only known types here - no default */ + case FLASH_AMLV128U: + case FLASH_AMLV640U: + case FLASH_AMLV320U: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += 0x20000; + } + break; + case FLASH_AMLV320B: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The first 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < 8) + ? 2 * ( 8 << 10) + : 2 * (64 << 10); + } + break; + } + break; +# else /* ! TQM8xxM */ + case AMD_ID_LV400B: + case AMD_ID_LV800B: + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + break; + case AMD_ID_LV400T: + case AMD_ID_LV800T: + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + break; + case AMD_ID_LV320B: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The first 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < 8) + ? 2 * ( 8 << 10) + : 2 * (64 << 10); + } + break; + case AMD_ID_LV320T: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The last 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < (info->sector_count - 8)) + ? 2 * (64 << 10) + : 2 * ( 8 << 10); + } + break; +#endif /* TQM8xxM */ + case AMD_ID_LV160B: + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00008000; + info->start[2] = base + 0x0000C000; + info->start[3] = base + 0x00010000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00020000) - 0x00060000; + } + break; + case AMD_ID_LV160T: + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000C000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00020000; + } + break; + case AMD_ID_DL163B: + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + /* + * The first 8 sectors are 8 kB, + * all the other ones are 64 kB + */ + base += (i < 8) + ? 2 * ( 8 << 10) + : 2 * (64 << 10); + } + break; + default: + return (0); + break; + } + +#if 0 + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr = (volatile unsigned long *)(info->start[i]); + info->protect[i] = addr[2] & 1; + } +#endif + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (volatile unsigned long *)info->start[0]; + + *addr = 0x00F000F0; /* reset bank */ + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + vu_long *addr = (vu_long*)(info->start[0]); + int flag, prot, sect, l_sect; + ulong start, now, last; + + debug ("flash_erase: first: %d last: %d\n", s_first, s_last); + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ((info->flash_id == FLASH_UNKNOWN) || + (info->flash_id > FLASH_AMD_COMP)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00800080; + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr = (vu_long*)(info->start[sect]); + addr[0] = 0x00300030; + l_sect = sect; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + + start = get_timer (0); + last = start; + addr = (vu_long*)(info->start[l_sect]); + while ((addr[0] & 0x00800080) != 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + +DONE: + /* reset to read mode */ + addr = (volatile unsigned long *)info->start[0]; + addr[0] = 0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long*)(info->start[0]); + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr[0x0555] = 0x00AA00AA; + addr[0x02AA] = 0x00550055; + addr[0x0555] = 0x00A000A0; + + *((vu_long *)dest) = data; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/tqm8xx/load_sernum_ethaddr.c b/board/tqm8xx/load_sernum_ethaddr.c new file mode 100644 index 000000000..143f36801 --- /dev/null +++ b/board/tqm8xx/load_sernum_ethaddr.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2000, 2001, 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/*----------------------------------------------------------------------- + * Process Hardware Information Block: + * + * If we boot on a system fresh from factory, check if the Hardware + * Information Block exists and save the information it contains. + * + * The TQM8xxL / TQM82xx Hardware Information Block is defined as + * follows: + * - located in first flash bank + * - starts at offset 0x0003FFC0 + * - size 0x00000040 + * + * Internal structure: + * - sequence of ASCII character strings + * - fields separated by a single space character (0x20) + * - last field terminated by NUL character (0x00) + * - remaining space filled with NUL characters (0x00) + * + * Fields in Hardware Information Block: + * 1) Module Type + * 2) Serial Number + * 3) First MAC Address + * 4) Number of additional MAC addresses + */ + +void load_sernum_ethaddr (void) +{ + unsigned char *hwi; + unsigned char serial [CFG_HWINFO_SIZE]; + unsigned char ethaddr[CFG_HWINFO_SIZE]; + unsigned short ih, is, ie, part; + + hwi = (unsigned char *)(CFG_FLASH_BASE + CFG_HWINFO_OFFSET); + ih = is = ie = 0; + + if (*((unsigned long *)hwi) != (unsigned long)CFG_HWINFO_MAGIC) { + return; + } + + part = 1; + + /* copy serial # / MAC address */ + while ((hwi[ih] != '\0') && (ih < CFG_HWINFO_SIZE)) { + if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */ + return; + } + switch (part) { + default: /* Copy serial # */ + if (hwi[ih] == ' ') { + ++part; + } + serial[is++] = hwi[ih]; + break; + case 3: /* Copy MAC address */ + if (hwi[ih] == ' ') { + ++part; + break; + } + ethaddr[ie++] = hwi[ih]; + if ((ie % 3) == 2) + ethaddr[ie++] = ':'; + break; + } + ++ih; + } + serial[is] = '\0'; + if (ie && ethaddr[ie-1] == ':') + --ie; + ethaddr[ie] = '\0'; + + /* set serial# and ethaddr if not yet defined */ + if (getenv("serial#") == NULL) { + setenv ((char *)"serial#", (char *)serial); + } + + if (getenv("ethaddr") == NULL) { + setenv ((char *)"ethaddr", (char *)ethaddr); + } +} diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c new file mode 100644 index 000000000..6b206f8a1 --- /dev/null +++ b/board/tqm8xx/tqm8xx.c @@ -0,0 +1,504 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if 0 +#define DEBUG +#endif + +#include +#include +#ifdef CONFIG_PS2MULT +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static long int dram_size (long int, long int *, long int); + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = +{ + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, + 0x1FF5FC47, /* last */ + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + * + * Test TQ ID string (TQM8xx...) + * If present, check for "L" type (no second DRAM bank), + * otherwise "L" type is assumed as default. + * + * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else. + */ + +int checkboard (void) +{ + char *s = getenv ("serial#"); + + puts ("Board: "); + + if (!s || strncmp (s, "TQM8", 4)) { + puts ("### No HW ID - assuming TQM8xxL\n"); + return (0); + } + + if ((*(s + 6) == 'L')) { /* a TQM8xxL type */ + gd->board_type = 'L'; + } + + if ((*(s + 6) == 'M')) { /* a TQM8xxM type */ + gd->board_type = 'M'; + } + + if ((*(s + 6) == 'D')) { /* a TQM885D type */ + gd->board_type = 'D'; + } + + for (; *s; ++s) { + if (*s == ' ') + break; + putc (*s); + } +#ifdef CONFIG_VIRTLAB2 + puts (" (Virtlab2)"); +#endif + putc ('\n'); + + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size8, size9, size10; + long int size_b0 = 0; + long int size_b1 = 0; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + + /* + * The following value is used as an address (i.e. opcode) for + * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If + * the port size is 32bit the SDRAM does NOT "see" the lower two + * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for + * MICRON SDRAMs: + * -> 0 00 010 0 010 + * | | | | +- Burst Length = 4 + * | | | +----- Burst Type = Sequential + * | | +------- CAS Latency = 2 + * | +----------- Operating Mode = Standard + * +-------------- Write Burst Mode = Programmed Burst Length + */ + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ + memctl->memc_or2 = CFG_OR2_PRELIM; + memctl->memc_br2 = CFG_BR2_PRELIM; + +#ifndef CONFIG_CAN_DRIVER + if ((board_type != 'L') && + (board_type != 'M') && + (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */ + memctl->memc_or3 = CFG_OR3_PRELIM; + memctl->memc_br3 = CFG_BR3_PRELIM; + } +#endif /* CONFIG_CAN_DRIVER */ + + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ + udelay (1); + +#ifndef CONFIG_CAN_DRIVER + if ((board_type != 'L') && + (board_type != 'M') && + (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ + memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ + udelay (1); + memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */ + udelay (1); + } +#endif /* CONFIG_CAN_DRIVER */ + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay (1000); + + /* + * Check Bank 0 Memory Size for re-configuration + * + * try 8 column mode + */ + size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20); + + udelay (1000); + + /* + * try 9 column mode + */ + size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20); + + udelay(1000); + +#if defined(CFG_MAMR_10COL) + /* + * try 10 column mode + */ + size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20); +#else + size10 = 0; +#endif /* CFG_MAMR_10COL */ + + if ((size8 < size10) && (size9 < size10)) { + size_b0 = size10; + } else if ((size8 < size9) && (size10 < size9)) { + size_b0 = size9; + memctl->memc_mamr = CFG_MAMR_9COL; + udelay (500); + } else { + size_b0 = size8; + memctl->memc_mamr = CFG_MAMR_8COL; + udelay (500); + } + debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20); + +#ifndef CONFIG_CAN_DRIVER + if ((board_type != 'L') && + (board_type != 'M') && + (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */ + /* + * Check Bank 1 Memory Size + * use current column settings + * [9 column SDRAM may also be used in 8 column mode, + * but then only half the real size will be used.] + */ + size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM, + SDRAM_MAX_SIZE); + debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20); + } else { + size_b1 = 0; + } +#endif /* CONFIG_CAN_DRIVER */ + + udelay (1000); + + /* + * Adjust refresh rate depending on SDRAM type, both banks + * For types > 128 MBit leave it at the current (fast) rate + */ + if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { + /* reduce to 15.6 us (62.4 us / quad) */ + memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + udelay (1000); + } + + /* + * Final mapping: map bigger bank first + */ + if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ + + memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + if (size_b0 > 0) { + /* + * Position Bank 0 immediately above Bank 1 + */ + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + + size_b1; + } else { + unsigned long reg; + + /* + * No bank 0 + * + * invalidate bank + */ + memctl->memc_br2 = 0; + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + + } else { /* SDRAM Bank 0 is bigger - map first */ + + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br2 = + (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + + if (size_b1 > 0) { + /* + * Position Bank 1 immediately above Bank 0 + */ + memctl->memc_or3 = + ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_br3 = + ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + + size_b0; + } else { + unsigned long reg; + +#ifndef CONFIG_CAN_DRIVER + /* + * No bank 1 + * + * invalidate bank + */ + memctl->memc_br3 = 0; +#endif /* CONFIG_CAN_DRIVER */ + + /* adjust refresh rate depending on SDRAM type, one bank */ + reg = memctl->memc_mptpr; + reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + memctl->memc_mptpr = reg; + } + } + + udelay (10000); + +#ifdef CONFIG_CAN_DRIVER + /* Initialize OR3 / BR3 */ + memctl->memc_or3 = CFG_OR3_CAN; + memctl->memc_br3 = CFG_BR3_CAN; + + /* Initialize MBMR */ + memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ + + /* Initialize UPMB for CAN: single read */ + memctl->memc_mdr = 0xFFFFC004; + memctl->memc_mcr = 0x0100 | UPMB; + + memctl->memc_mdr = 0x0FFFD004; + memctl->memc_mcr = 0x0101 | UPMB; + + memctl->memc_mdr = 0x0FFFC000; + memctl->memc_mcr = 0x0102 | UPMB; + + memctl->memc_mdr = 0x3FFFC004; + memctl->memc_mcr = 0x0103 | UPMB; + + memctl->memc_mdr = 0xFFFFDC05; + memctl->memc_mcr = 0x0104 | UPMB; + + /* Initialize UPMB for CAN: single write */ + memctl->memc_mdr = 0xFFFCC004; + memctl->memc_mcr = 0x0118 | UPMB; + + memctl->memc_mdr = 0xCFFCD004; + memctl->memc_mcr = 0x0119 | UPMB; + + memctl->memc_mdr = 0x0FFCC000; + memctl->memc_mcr = 0x011A | UPMB; + + memctl->memc_mdr = 0x7FFCC004; + memctl->memc_mcr = 0x011B | UPMB; + + memctl->memc_mdr = 0xFFFDCC05; + memctl->memc_mcr = 0x011C | UPMB; +#endif /* CONFIG_CAN_DRIVER */ + +#ifdef CONFIG_ISP1362_USB + /* Initialize OR5 / BR5 */ + memctl->memc_or5 = CFG_OR5_ISP1362; + memctl->memc_br5 = CFG_BR5_ISP1362; +#endif /* CONFIG_ISP1362_USB */ + + + return (size_b0 + size_b1); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ + +static long int dram_size (long int mamr_value, long int *base, long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + memctl->memc_mamr = mamr_value; + + return (get_ram_size(base, maxsize)); +} + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_PS2MULT + +#ifdef CONFIG_HMI10 +#define BASE_BAUD ( 1843200 / 16 ) +struct serial_state rs_table[] = { + { BASE_BAUD, 4, (void*)0xec140000 }, + { BASE_BAUD, 2, (void*)0xec150000 }, + { BASE_BAUD, 6, (void*)0xec160000 }, + { BASE_BAUD, 10, (void*)0xec170000 }, +}; + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r (void) +{ + ps2mult_early_init(); + return (0); +} +#endif +#endif /* CONFIG_HMI10 */ + +#endif /* CONFIG_PS2MULT */ + +/* ---------------------------------------------------------------------------- */ +/* HMI10 specific stuff */ +/* ---------------------------------------------------------------------------- */ +#ifdef CONFIG_HMI10 + +int misc_init_r (void) +{ +# ifdef CONFIG_IDE_LED + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* Configure PA15 as output port */ + immap->im_ioport.iop_padir |= 0x0001; + immap->im_ioport.iop_paodr |= 0x0001; + immap->im_ioport.iop_papar &= ~0x0001; + immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ +# endif + return (0); +} + +# ifdef CONFIG_IDE_LED +void ide_led (uchar led, uchar status) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* We have one led for both pcmcia slots */ + if (status) { /* led on */ + immap->im_ioport.iop_padat |= 0x0001; + } else { + immap->im_ioport.iop_padat &= ~0x0001; + } +} +# endif +#endif /* CONFIG_HMI10 */ + +/* ---------------------------------------------------------------------------- */ +/* NSCU specific stuff */ +/* ---------------------------------------------------------------------------- */ +#ifdef CONFIG_NSCU + +int misc_init_r (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + + /* wake up ethernet module */ + immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ + immr->im_ioport.iop_pcdir |= 0x0004; /* output */ + immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ + immr->im_ioport.iop_pcdat |= 0x0004; /* enable */ + + return (0); +} +#endif /* CONFIG_NSCU */ + +/* ------------------------------------------------------------------------- */ diff --git a/board/tqm8xx/u-boot.lds b/board/tqm8xx/u-boot.lds new file mode 100644 index 000000000..d526d1d07 --- /dev/null +++ b/board/tqm8xx/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm8xx/u-boot.lds.debug b/board/tqm8xx/u-boot.lds.debug new file mode 100644 index 000000000..ddd4678ee --- /dev/null +++ b/board/tqm8xx/u-boot.lds.debug @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/trab/Makefile b/board/trab/Makefile index 2402577a5..159404b26 100644 --- a/board/trab/Makefile +++ b/board/trab/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,50 +23,43 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o +OBJS := trab.o flash.o vfd.o cmd_trab.o memory.o tsc2000.o auto_update.o SOBJS := lowlevel_init.o -COBJS_FKT := trab_fkt.o rs485.o tsc2000.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS_FKT:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -OBJS_FKT := $(addprefix $(obj),$(COBJS_FKT)) - gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) LOAD_ADDR = 0xc100000 ######################################################################### -all: $(LIB) $(obj)trab_fkt.srec $(obj)trab_fkt.bin +all: $(LIB) trab_fkt.srec trab_fkt.bin -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) -$(obj)trab_fkt.srec: $(OBJS_FKT) $(LIB) - $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \ - -L$(obj)../../examples -lstubs \ +trab_fkt.srec: trab_fkt.o rs485.o tsc2000.o $(LIB) + $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ $(LIB) \ + -L../../examples -lstubs \ + -L../../lib_generic -lgeneric \ -L$(gcclibdir) -lgcc $(OBJCOPY) -O srec $(<:.o=) $@ -$(obj)trab_fkt.bin: $(obj)trab_fkt.srec +trab_fkt.bin: trab_fkt.srec $(OBJCOPY) -I srec -O binary $< $@ clean: - rm -f $(SOBJS) $(OBJS) $(OBJS_FKT) + rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c index 46110cc76..d2c8d44a7 100644 --- a/board/trab/auto_update.c +++ b/board/trab/auto_update.c @@ -34,7 +34,7 @@ #ifdef CONFIG_AUTO_UPDATE -#ifndef CONFIG_USB_OHCI_NEW +#ifndef CONFIG_USB_OHCI #error "must define CONFIG_USB_OHCI" #endif @@ -46,8 +46,8 @@ #error "must define CFG_HUSH_PARSER" #endif -#if !defined(CONFIG_CMD_FAT) -#error "must define CONFIG_CMD_FAT" +#if !(CONFIG_COMMANDS & CFG_CMD_FAT) +#error "must define CFG_CMD_FAT" #endif /* @@ -203,27 +203,28 @@ extern int flash_write (char *, ulong, ulong); /* change char* to void* to shutup the compiler */ extern int i2c_write_multiple (uchar, uint, int, void *, int); extern int i2c_read_multiple (uchar, uint, int, void *, int); +extern block_dev_desc_t *get_dev (char*, int); extern int u_boot_hush_start(void); int au_check_cksum_valid(int idx, long nbytes) { image_header_t *hdr; + unsigned long checksum; hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - if (nbytes != image_get_image_size (hdr)) { + if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) + { printf ("Image %s bad total SIZE\n", aufile[idx]); return -1; } /* check the data CRC */ - if (!image_check_dcrc (hdr)) { + checksum = ntohl(hdr->ih_dcrc); + + if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) + != checksum) + { printf ("Image %s bad data checksum\n", aufile[idx]); return -1; } @@ -238,55 +239,54 @@ au_check_header_valid(int idx, long nbytes) unsigned char buf[4]; hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - /* check the easy ones first */ #undef CHECK_VALID_DEBUG #ifdef CHECK_VALID_DEBUG - printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC); - printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM); - printf("size %#x %#lx ", image_get_data_size (hdr), nbytes); - printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL); + printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC); + printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_ARM); + printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes); + printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL); #endif - if (nbytes < image_get_header_size ()) { + if (nbytes < sizeof(*hdr)) + { printf ("Image %s bad header SIZE\n", aufile[idx]); return -1; } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_ARM)) { + if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_ARM) + { printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]); return -1; } /* check the hdr CRC */ - if (!image_check_hcrc (hdr)) { + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)hdr, sizeof(*hdr)) != checksum) { printf ("Image %s bad header checksum\n", aufile[idx]); return -1; } + hdr->ih_hcrc = htonl(checksum); /* check the type - could do this all in one gigantic if() */ - if ((idx == IDX_FIRMWARE) && - !image_check_type (hdr, IH_TYPE_FIRMWARE)) { + if ((idx == IDX_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) { printf ("Image %s wrong type\n", aufile[idx]); return -1; } - if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) { + if ((idx == IDX_KERNEL) && (hdr->ih_type != IH_TYPE_KERNEL)) { printf ("Image %s wrong type\n", aufile[idx]); return -1; } - if ((idx == IDX_DISK) && !image_check_type (hdr, IH_TYPE_FILESYSTEM)) { + if ((idx == IDX_DISK) && (hdr->ih_type != IH_TYPE_FILESYSTEM)) { printf ("Image %s wrong type\n", aufile[idx]); return -1; } - if ((idx == IDX_APP) && !image_check_type (hdr, IH_TYPE_RAMDISK) - && !image_check_type (hdr, IH_TYPE_FILESYSTEM)) { + if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK) + && (hdr->ih_type != IH_TYPE_FILESYSTEM)) { printf ("Image %s wrong type\n", aufile[idx]); return -1; } if ((idx == IDX_PREPARE || idx == IDX_PREINST || idx == IDX_POSTINST) - && !image_check_type (hdr, IH_TYPE_SCRIPT)) { + && (hdr->ih_type != IH_TYPE_SCRIPT)) + { printf ("Image %s wrong type\n", aufile[idx]); return -1; } @@ -294,10 +294,10 @@ au_check_header_valid(int idx, long nbytes) if (idx == IDX_PREPARE) return 0; /* recycle checksum */ - checksum = image_get_data_size (hdr); + checksum = ntohl(hdr->ih_size); /* for kernel and app the image header must also fit into flash */ if ((idx != IDX_DISK) && (idx != IDX_FIRMWARE)) - checksum += image_get_header_size (); + checksum += sizeof(*hdr); /* check the size does not exceed space in flash. HUSH scripts */ /* all have ausize[] set to 0 */ if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { @@ -311,10 +311,10 @@ au_check_header_valid(int idx, long nbytes) printf ("buf[0] %#x buf[1] %#x buf[2] %#x buf[3] %#x " "as int %#x time %#x\n", buf[0], buf[1], buf[2], buf[3], - *((unsigned int *)buf), image_get_time (hdr)); + *((unsigned int *)buf), ntohl(hdr->ih_time)); #endif /* check it */ - if (*((unsigned int *)buf) >= image_get_time (hdr)) { + if (*((unsigned int *)buf) >= ntohl(hdr->ih_time)) { printf ("Image %s is too old\n", aufile[idx]); return -1; } @@ -336,22 +336,16 @@ au_do_update(int idx, long sz) uint nbytes; hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif /* disable the power switch */ *CPLD_VFD_BK |= POWER_OFF; /* execute a script */ - if (image_check_type (hdr, IH_TYPE_SCRIPT)) { - addr = (char *)((char *)hdr + image_get_header_size ()); + if (hdr->ih_type == IH_TYPE_SCRIPT) { + addr = (char *)((char *)hdr + sizeof(*hdr)); /* stick a NULL at the end of the script, otherwise */ /* parse_string_outer() runs off the end. */ - addr[image_get_data_size (hdr)] = 0; + addr[ntohl(hdr->ih_size)] = 0; addr += 8; parse_string_outer(addr, FLAG_PARSE_SEMICOLON); return 0; @@ -379,20 +373,19 @@ au_do_update(int idx, long sz) flash_sect_erase(start, end); wait_ms(100); /* strip the header - except for the kernel and ramdisk */ - if (image_check_type (hdr, IH_TYPE_KERNEL) || - image_check_type (hdr, IH_TYPE_RAMDISK)) { + if (hdr->ih_type == IH_TYPE_KERNEL || hdr->ih_type == IH_TYPE_RAMDISK) { addr = (char *)hdr; - off = image_get_header_size (); - nbytes = image_get_image_size (hdr); + off = sizeof(*hdr); + nbytes = sizeof(*hdr) + ntohl(hdr->ih_size); } else { - addr = (char *)((char *)hdr + image_get_header_size ()); + addr = (char *)((char *)hdr + sizeof(*hdr)); #ifdef AU_UPDATE_TEST /* copy it to where Linux goes */ if (idx == IDX_FIRMWARE) start = aufl_layout[1].start; #endif off = 0; - nbytes = image_get_data_size (hdr); + nbytes = ntohl(hdr->ih_size); } /* copy the data from RAM to FLASH */ @@ -404,8 +397,7 @@ au_do_update(int idx, long sz) } /* check the dcrc of the copy */ - if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) != - image_get_dcrc (hdr)) { + if (crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) { printf ("Image %s Bad Data Checksum After COPY\n", aufile[idx]); return -1; } @@ -432,24 +424,17 @@ au_update_eeprom(int idx) } hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - /* write the time field into EEPROM */ off = auee_off[idx].time; - val = image_get_time (hdr); + val = ntohl(hdr->ih_time); i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); /* write the size field into EEPROM */ off = auee_off[idx].size; - val = image_get_data_size (hdr); + val = ntohl(hdr->ih_size); i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); /* write the dcrc field into EEPROM */ off = auee_off[idx].dcrc; - val = image_get_dcrc (hdr); + val = ntohl(hdr->ih_dcrc); i2c_write_multiple(0x54, off, 1, &val, sizeof(val)); /* enable the power switch */ *CPLD_VFD_BK &= ~POWER_OFF; @@ -466,7 +451,7 @@ do_auto_update(void) { block_dev_desc_t *stor_dev; long sz; - int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc; + int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc; char *env; long start, end; @@ -493,21 +478,18 @@ do_auto_update(void) au_usb_stor_curr_dev = usb_stor_scan(0); if (au_usb_stor_curr_dev == -1) { debug ("No device found. Not initialized?\n"); - res = -1; - goto xit; + return -1; } /* check whether it has a partition table */ stor_dev = get_dev("usb", 0); if (stor_dev == NULL) { debug ("uknown device type\n"); - res = -1; - goto xit; + return -1; } if (fat_register_device(stor_dev, 1) != 0) { debug ("Unable to use USB %d:%d for fatls\n", au_usb_stor_curr_dev, 1); - res = -1; - goto xit; + return -1; } if (file_fat_detectfs() != 0) { debug ("file_fat_detectfs failed\n"); @@ -593,10 +575,10 @@ do_auto_update(void) /* just loop thru all the possible files */ for (i = 0; i < AU_MAXFILES; i++) { /* just read the header */ - sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ()); + sz = file_fat_read(aufile[i], LOAD_ADDR, sizeof(image_header_t)); debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - if (sz <= 0 || sz < image_get_header_size ()) { + aufile[i], sz, sizeof(image_header_t)); + if (sz <= 0 || sz < sizeof(image_header_t)) { debug ("%s not found\n", aufile[i]); continue; } @@ -606,8 +588,8 @@ do_auto_update(void) } sz = file_fat_read(aufile[i], LOAD_ADDR, MAX_LOADSZ); debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - if (sz <= 0 || sz <= image_get_header_size ()) { + aufile[i], sz, sizeof(image_header_t)); + if (sz <= 0 || sz <= sizeof(image_header_t)) { debug ("%s not found\n", aufile[i]); continue; } @@ -667,10 +649,9 @@ do_auto_update(void) /* enable the power switch */ *CPLD_VFD_BK &= ~POWER_OFF; } + usb_stop(); /* restore the old state */ disable_ctrlc(old_ctrlc); -xit: - usb_stop(); - return res; + return 0; } #endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index daa6aeefc..b82c8edef 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -32,7 +32,7 @@ * TRAB board specific commands. Especially commands for burn-in and function * test. */ -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) /* limits for valid range of VCC5V in mV */ #define VCC5V_MIN 4500 @@ -846,7 +846,7 @@ int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int contact_temp; int delay = 0; -#if defined(CONFIG_CMD_DATE) +#if (CONFIG_COMMANDS & CFG_CMD_DATE) struct rtc_time tm; #endif @@ -862,7 +862,7 @@ int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) spi_init (); while (1) { -#if defined(CONFIG_CMD_DATE) +#if (CONFIG_COMMANDS & CFG_CMD_DATE) rtc_get (&tm); printf ("%4d-%02d-%02d %2d:%02d:%02d - ", tm.tm_year, tm.tm_mon, tm.tm_mday, @@ -893,4 +893,4 @@ U_BOOT_CMD( " For each measurment a timestamp is printeted\n" ); -#endif +#endif /* CFG_CMD_BSP */ diff --git a/board/trab/config.mk b/board/trab/config.mk index 800cc28a1..f2411d009 100644 --- a/board/trab/config.mk +++ b/board/trab/config.mk @@ -19,7 +19,7 @@ # download areas is 0C80'0000 # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE TEXT_BASE = 0x0DF40000 diff --git a/board/trab/lowlevel_init.S b/board/trab/lowlevel_init.S index bc7142abe..128ae7e4a 100644 --- a/board/trab/lowlevel_init.S +++ b/board/trab/lowlevel_init.S @@ -128,7 +128,7 @@ #define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ #define Trp 0x0 /* 2 clk */ #define Trc 0x3 /* 7 clk */ -#define Tchr 0x2 /* 3 clk */ +#define Tchr 0x2 /* 3 clk */ #ifdef CONFIG_TRAB_50MHZ #define REFCNT 1269 /* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */ diff --git a/board/trab/memory.c b/board/trab/memory.c index 052432e9d..58bd99500 100644 --- a/board/trab/memory.c +++ b/board/trab/memory.c @@ -282,7 +282,7 @@ static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) #endif if(readback == *testaddr) { printf ("Memory (address line) error at %08lx<->%08lx, " - "XOR value %08lx !\n", + "XOR value %08lx !\n", (ulong)testaddr, (ulong)target, xor); ret = -1; @@ -460,7 +460,7 @@ int memory_post_test (int flags) { int ret = 0; bd_t *bd = gd->bd; - phys_size_t memsize = (bd->bi_memsize >= 256 << 20 ? + unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? 256 << 20 : bd->bi_memsize) - (1 << 20); diff --git a/board/trab/trab.c b/board/trab/trab.c index b869023ea..26e52d29e 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -89,7 +89,7 @@ int board_init () gpio->PBCON = 0xaaaaaaaa; gpio->PBUP = 0xffff; /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */ - /* 00, 10, 10, 10, 10, 10, 10 */ + /* 00, 10, 10, 10, 10, 10, 10 */ gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10); #ifdef CONFIG_HWFLOW /* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */ @@ -130,7 +130,7 @@ int board_init () #ifdef CONFIG_DRIVER_S3C24X0_I2C /* Configure I/O ports PG5 und PG6 for I2C */ - gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00; + gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00; #endif /* CONFIG_DRIVER_S3C24X0_I2C */ return 0; @@ -175,11 +175,9 @@ int misc_init_r (void) #endif /* CONFIG_VERSION_VARIABLE */ #ifdef CONFIG_AUTO_UPDATE - { - extern int do_auto_update(void); - /* this has priority over all else */ - do_auto_update(); - } + extern int do_auto_update(void); + /* this has priority over all else */ + do_auto_update(); #endif for (i = 0; i < KEYBD_KEY_NUM; ++i) { @@ -321,9 +319,9 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - kbd, 1, 1, do_kbd, - "kbd - read keyboard status\n", - NULL + kbd, 1, 1, do_kbd, + "kbd - read keyboard status\n", + NULL ); #ifdef CONFIG_MODEM_SUPPORT @@ -356,7 +354,7 @@ static void spi_init(void) int i; /* Configure I/O ports. */ - gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; + gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000; gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000; gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000; gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000; diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index 7273ef97b..71be6e03e 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -148,14 +148,14 @@ static int rs485_receive_chars (char *data, int timeout); static unsigned short updcrc(unsigned short icrc, unsigned char *icp, unsigned int icnt); -#if defined(CONFIG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) static int trab_eeprom_read (char **argv); static int trab_eeprom_write (char **argv); int i2c_write_multiple (uchar chip, uint addr, int alen, uchar *buffer, int len); int i2c_read_multiple ( uchar chip, uint addr, int alen, uchar *buffer, int len); -#endif +#endif /* CFG_CMD_I2C */ /* * TRAB board specific commands. Especially commands for burn-in and function @@ -959,7 +959,7 @@ static int touch_check_pressed (void) static int touch_write_clibration_values (int calib_point, int x, int y) { -#if defined(CONFIG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) int x_verify = 0; int y_verify = 0; @@ -1019,10 +1019,10 @@ static int touch_write_clibration_values (int calib_point, int x, int y) } return 1; #else - printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write " + printf ("No I2C support enabled (CFG_CMD_I2C), could not write " "to EEPROM\n"); return (1); -#endif +#endif /* CFG_CMD_I2C */ } @@ -1105,7 +1105,7 @@ static int rs485_receive_chars (char *data, int timeout) int do_serial_number (char **argv) { -#if defined(CONFIG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) unsigned int serial_number; if (strcmp (argv[2], "read") == 0) { @@ -1130,16 +1130,16 @@ int do_serial_number (char **argv) printf ("%s: unknown command %s\n", __FUNCTION__, argv[2]); return (1); /* unknown command, return error */ #else - printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write " + printf ("No I2C support enabled (CFG_CMD_I2C), could not write " "to EEPROM\n"); return (1); -#endif +#endif /* CFG_CMD_I2C */ } int do_crc16 (void) { -#if defined(CONFIG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) int crc; unsigned char buf[EEPROM_MAX_CRC_BUF]; @@ -1160,10 +1160,10 @@ int do_crc16 (void) } return (0); #else - printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write " + printf ("No I2C support enabled (CFG_CMD_I2C), could not write " "to EEPROM\n"); return (1); -#endif +#endif /* CFG_CMD_I2C */ } @@ -1260,7 +1260,7 @@ int do_gain (char **argv) int do_eeprom (char **argv) { -#if defined(CONFIG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) if (strcmp (argv[2], "read") == 0) { return (trab_eeprom_read (argv)); } @@ -1272,13 +1272,13 @@ int do_eeprom (char **argv) printf ("%s: invalid parameter %s\n", __FUNCTION__, argv[2]); return (1); #else - printf ("No I2C support enabled (CONFIG_CMD_I2C), could not write " + printf ("No I2C support enabled (CFG_CMD_I2C), could not write " "to EEPROM\n"); return (1); -#endif +#endif /* CFG_CMD_I2C */ } -#if defined(CONFIG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) static int trab_eeprom_read (char **argv) { int i; @@ -1408,4 +1408,4 @@ int i2c_read_multiple ( uchar chip, uint addr, int alen, } return (0); } -#endif +#endif /* CFG_CMD_I2C */ diff --git a/board/trab/tsc2000.h b/board/trab/tsc2000.h index af1b64458..aac9c0c77 100644 --- a/board/trab/tsc2000.h +++ b/board/trab/tsc2000.h @@ -29,45 +29,45 @@ #define _TSC2000_H_ /* temperature channel multiplexer definitions */ -#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100) -#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF) -#define SET_MUX0 (gpio->PCDAT |= 0x00010) +#define CON_MUX0 (gpio->PCCON = (gpio->PCCON & 0x0FFFFFCFF) | 0x00000100) +#define CLR_MUX0 (gpio->PCDAT &= 0x0FFEF) +#define SET_MUX0 (gpio->PCDAT |= 0x00010) -#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400) -#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF) -#define SET_MUX1 (gpio->PCDAT |= 0x00020) +#define CON_MUX1 (gpio->PCCON = (gpio->PCCON & 0x0FFFFF3FF) | 0x00000400) +#define CLR_MUX1 (gpio->PCDAT &= 0x0FFDF) +#define SET_MUX1 (gpio->PCDAT |= 0x00020) -#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000) -#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040) -#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF) +#define CON_MUX1_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFFCFFF) | 0x00001000) +#define CLR_MUX1_ENABLE (gpio->PCDAT |= 0x00040) +#define SET_MUX1_ENABLE (gpio->PCDAT &= 0x0FFBF) -#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000) -#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080) -#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F) +#define CON_MUX2_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFF3FFF) | 0x00004000) +#define CLR_MUX2_ENABLE (gpio->PCDAT |= 0x00080) +#define SET_MUX2_ENABLE (gpio->PCDAT &= 0x0FF7F) -#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000) -#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100) -#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF) +#define CON_MUX3_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFFCFFFF) | 0x00010000) +#define CLR_MUX3_ENABLE (gpio->PCDAT |= 0x00100) +#define SET_MUX3_ENABLE (gpio->PCDAT &= 0x0FEFF) -#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000) -#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200) -#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF) +#define CON_MUX4_ENABLE (gpio->PCCON = (gpio->PCCON & 0x0FFF3FFFF) | 0x00040000) +#define CLR_MUX4_ENABLE (gpio->PCDAT |= 0x00200) +#define SET_MUX4_ENABLE (gpio->PCDAT &= 0x0FDFF) -#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000) -#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF) -#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400) +#define CON_SEL_TEMP_V_0 (gpio->PCCON = (gpio->PCCON & 0x0FFCFFFFF) | 0x00100000) +#define CLR_SEL_TEMP_V_0 (gpio->PCDAT &= 0x0FBFF) +#define SET_SEL_TEMP_V_0 (gpio->PCDAT |= 0x00400) -#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000) -#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF) -#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800) +#define CON_SEL_TEMP_V_1 (gpio->PCCON = (gpio->PCCON & 0x0FF3FFFFF) | 0x00400000) +#define CLR_SEL_TEMP_V_1 (gpio->PCDAT &= 0x0F7FF) +#define SET_SEL_TEMP_V_1 (gpio->PCDAT |= 0x00800) -#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000) -#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF) -#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000) +#define CON_SEL_TEMP_V_2 (gpio->PCCON = (gpio->PCCON & 0x0FCFFFFFF) | 0x01000000) +#define CLR_SEL_TEMP_V_2 (gpio->PCDAT &= 0x0EFFF) +#define SET_SEL_TEMP_V_2 (gpio->PCDAT |= 0x01000) -#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000) -#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF) -#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000) +#define CON_SEL_TEMP_V_3 (gpio->PCCON = (gpio->PCCON & 0x0F3FFFFFF) | 0x04000000) +#define CLR_SEL_TEMP_V_3 (gpio->PCDAT &= 0x0DFFF) +#define SET_SEL_TEMP_V_3 (gpio->PCDAT |= 0x02000) /* TSC2000 register definition */ #define TSC2000_REG_X ((0 << 11) | (0 << 5)) @@ -89,21 +89,21 @@ #define TSC2000_REG_CONFIG ((1 << 11) | (5 << 5)) /* bit definition of TSC2000 ADC register */ -#define TC_PSM (1 << 15) -#define TC_STS (1 << 14) -#define TC_AD3 (1 << 13) -#define TC_AD2 (1 << 12) -#define TC_AD1 (1 << 11) -#define TC_AD0 (1 << 10) -#define TC_RS1 (1 << 9) -#define TC_RS0 (1 << 8) -#define TC_AV1 (1 << 7) -#define TC_AV0 (1 << 6) -#define TC_CL1 (1 << 5) -#define TC_CL0 (1 << 4) -#define TC_PV2 (1 << 3) -#define TC_PV1 (1 << 2) -#define TC_PV0 (1 << 1) +#define TC_PSM (1 << 15) +#define TC_STS (1 << 14) +#define TC_AD3 (1 << 13) +#define TC_AD2 (1 << 12) +#define TC_AD1 (1 << 11) +#define TC_AD0 (1 << 10) +#define TC_RS1 (1 << 9) +#define TC_RS0 (1 << 8) +#define TC_AV1 (1 << 7) +#define TC_AV0 (1 << 6) +#define TC_CL1 (1 << 5) +#define TC_CL0 (1 << 4) +#define TC_PV2 (1 << 3) +#define TC_PV1 (1 << 2) +#define TC_PV0 (1 << 1) /* default value for TSC2000 ADC register for use with touch functions */ #define DEFAULT_ADC (TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0) @@ -111,7 +111,8 @@ #define TSC2000_DELAY_BASE 500 #define TSC2000_NO_SENSOR -0x10000 -#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on TRAB */ +#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on + * TRAB */ void tsc2000_write(unsigned short, unsigned short); unsigned short tsc2000_read (unsigned short); diff --git a/board/trab/u-boot.lds b/board/trab/u-boot.lds index 043e01c9b..e56cdd3ca 100644 --- a/board/trab/u-boot.lds +++ b/board/trab/u-boot.lds @@ -60,6 +60,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/trab/vfd.c b/board/trab/vfd.c index eb506f39b..b6798fdce 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -104,7 +104,7 @@ void init_grid_ctrl(void) bit = grid_cycle * 256 * 4 + (grid_cycle + 200) * 4 + frame_buf_offs + display; - /* wrap arround if offset (see manual S3C2400) */ + /* wrap arround if offset (see manual S3C2400) */ if (bit>=FRAME_BUF_SIZE*8) bit = bit - (FRAME_BUF_SIZE * 8); adr = gd->fb_base + (bit/32) * 4 + (3 - (bit%32) / 8); @@ -117,7 +117,7 @@ void init_grid_ctrl(void) if(grid_cycle<55) bit = grid_cycle*256*4+(grid_cycle+201)*4+frame_buf_offs+display; else - bit = grid_cycle*256*4+200*4+frame_buf_offs+display-4; /* grid nr. 0 */ + bit = grid_cycle*256*4+200*4+frame_buf_offs+display-4; /* grid nr. 0 */ /* wrap arround if offset (see manual S3C2400) */ if (bit>=FRAME_BUF_SIZE*8) bit = bit-(FRAME_BUF_SIZE*8); @@ -190,7 +190,7 @@ void create_vfd_table(void) /* Display 0 red pixels */ vfd_table[x][y][1][display][0] = (x==0) ? y*16+512+display - : (x%4)*4+y*16+((x-1)/2)*1024+512+display; + : (x%4)*4+y*16+((x-1)/2)*1024+512+display; } } } @@ -488,7 +488,7 @@ int drv_vfd_init(void) lcd->LCDCON1 = 0x00000000; /* frame buffer startadr */ lcd->LCDSADDR1 = gd->fb_base >> 1; - /* frame buffer endadr */ + /* frame buffer endadr */ lcd->LCDSADDR2 = (gd->fb_base + FRAME_BUF_SIZE) >> 1; lcd->LCDSADDR3 = ((256/4)); lcd->LCDCON2 = 0x000DC000; diff --git a/board/uc100/Makefile b/board/uc100/Makefile index 92ee091f6..2d2cc2320 100644 --- a/board/uc100/Makefile +++ b/board/uc100/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,23 +23,19 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -#COBJS = $(BOARD).o flash.o pcmcia.o -COBJS = $(BOARD).o pcmcia.o +#OBJS = $(BOARD).o flash.o pcmcia.o +OBJS = $(BOARD).o pcmcia.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/uc100/pcmcia.c b/board/uc100/pcmcia.c index 407bdb73c..6e4b6d6c6 100644 --- a/board/uc100/pcmcia.c +++ b/board/uc100/pcmcia.c @@ -4,11 +4,11 @@ #undef CONFIG_PCMCIA -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) #define CONFIG_PCMCIA #endif -#if (defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CONFIG_PCMCIA #endif @@ -123,7 +123,7 @@ int pcmcia_hardware_enable(int slot) } -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) int pcmcia_hardware_disable(int slot) { volatile immap_t *immap; @@ -149,7 +149,7 @@ int pcmcia_hardware_disable(int slot) return (0); } -#endif +#endif /* CFG_CMD_PCMCIA */ int pcmcia_voltage_set(int slot, int vcc, int vpp) diff --git a/board/uc100/u-boot.lds b/board/uc100/u-boot.lds index db2934249..d7c798ebb 100644 --- a/board/uc100/u-boot.lds +++ b/board/uc100/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -130,7 +131,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/uc100/u-boot.lds.debug b/board/uc100/u-boot.lds.debug index 25702a543..d9bb86836 100644 --- a/board/uc100/u-boot.lds.debug +++ b/board/uc100/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c index 896f9693e..4f2cff624 100644 --- a/board/uc100/uc100.c +++ b/board/uc100/uc100.c @@ -169,7 +169,7 @@ int checkboard (void) /* * Initialize SDRAM */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *) CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -188,7 +188,7 @@ phys_size_t initdram (int board_type) memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */ memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */ - memctl->memc_mbmr = CFG_MBMR_VAL; + memctl->memc_mbmr = CFG_MBMR_VAL; /*---------------------------------------------------------------------*/ /* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */ diff --git a/board/utx8245/Makefile b/board/utx8245/Makefile index 7ad768bc4..e698afc7f 100644 --- a/board/utx8245/Makefile +++ b/board/utx8245/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2002 @@ -28,22 +28,20 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SOBJS = -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c index 199f619a8..327182708 100644 --- a/board/utx8245/flash.c +++ b/board/utx8245/flash.c @@ -46,7 +46,7 @@ #endif #define FLASH_BANK_SIZE ((uint)(16 * 1024 * 1024)) /* max 16Mbyte */ -#define MAIN_SECT_SIZE 0x10000 +#define MAIN_SECT_SIZE 0x10000 #define SECT_SIZE_32KB 0x8000 #define SECT_SIZE_8KB 0x2000 diff --git a/board/utx8245/u-boot.lds b/board/utx8245/u-boot.lds new file mode 100644 index 000000000..45f3018bb --- /dev/null +++ b/board/utx8245/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Gregory E. Allen, gallen@arlut.utexas.edu + * Matthew E. Karger, karger@arlut.utexas.edu + * Applied Research Laboratories, The University of Texas at Austin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc824x/start.o (.text) + lib_ppc/board.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c index e2a961a3a..834fd8407 100644 --- a/board/utx8245/utx8245.c +++ b/board/utx8245/utx8245.c @@ -46,7 +46,7 @@ int checkboard(void) } -phys_size_t initdram(int board_type) +long int initdram(int board_type) { long size; long new_bank0_end; diff --git a/board/v37/Makefile b/board/v37/Makefile index 109cec264..7a1706793 100644 --- a/board/v37/Makefile +++ b/board/v37/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/v37/flash.c b/board/v37/flash.c index d845f652f..6a319721b 100644 --- a/board/v37/flash.c +++ b/board/v37/flash.c @@ -31,7 +31,7 @@ * are not tested. * * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? + * does not use AM29LV800 flash memory exist ? * I don't know... */ diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds index 7bcf06155..f9722dbb6 100644 --- a/board/v37/u-boot.lds +++ b/board/v37/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -133,7 +134,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/v37/v37.c b/board/v37/v37.c index 2067fedfc..1ef879d5f 100644 --- a/board/v37/v37.c +++ b/board/v37/v37.c @@ -38,8 +38,8 @@ static long int dram_size (void); /* ------------------------------------------------------------------------- */ -#define MBYTE (1024*1024) -#define DRAM_DELAY 0x00000379 /* DRAM delay count */ +#define MBYTE (1024*1024) +#define DRAM_DELAY 0x00000379 /* DRAM delay count */ #define _NOT_USED_ 0xFFFFCC25 const uint sdram_table[] = @@ -90,7 +90,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; diff --git a/board/versatile/Makefile b/board/versatile/Makefile index 044a42989..fbdc627e3 100644 --- a/board/versatile/Makefile +++ b/board/versatile/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := versatile.o flash.o +OBJS := versatile.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/versatile/flash.c b/board/versatile/flash.c index bbe5df724..71533719f 100644 --- a/board/versatile/flash.c +++ b/board/versatile/flash.c @@ -92,7 +92,7 @@ static void flash_vpp(int on) if (on) tmp |= VERSATILE_FLASHPROG_FLVPPEN; else - tmp &= ~VERSATILE_FLASHPROG_FLVPPEN; + tmp &= ~VERSATILE_FLASHPROG_FLVPPEN; *(unsigned int *)(VERSATILE_FLASHCTRL) = tmp; } @@ -476,7 +476,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* Check if Flash is (sufficiently) erased */ if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr); + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); return (2); } diff --git a/board/versatile/split_by_variant.sh b/board/versatile/split_by_variant.sh index ccded7e8c..576f238ad 100755 --- a/board/versatile/split_by_variant.sh +++ b/board/versatile/split_by_variant.sh @@ -5,30 +5,28 @@ # --------------------------------------------------------- # Set up the Versatile type define # --------------------------------------------------------- - -mkdir -p ${obj}include variant=PB926EJ-S -if [ "$1" = "" ] +if [ "$1" == "" ] then echo "$0:: No parameters - using versatilepb_config" - echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h + echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h variant=PB926EJ-S else case "$1" in versatilepb_config | \ versatile_config) - echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h + echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h ;; versatileab_config) - echo "#define CONFIG_ARCH_VERSATILE_AB" > ${obj}include/config.h + echo "#define CONFIG_ARCH_VERSATILE_AB" > ./include/config.h variant=AB926EJ-S ;; *) echo "$0:: Unrecognised config - using versatilepb_config" - echo "#define CONFIG_ARCH_VERSATILE_PB" > ${obj}include/config.h + echo "#define CONFIG_ARCH_VERSATILE_PB" > ./include/config.h variant=PB926EJ-S ;; @@ -38,5 +36,5 @@ fi # --------------------------------------------------------- # Complete the configuration # --------------------------------------------------------- -$MKCONFIG -a versatile arm arm926ejs versatile NULL versatile +./mkconfig -a versatile arm arm926ejs versatile NULL versatile echo "Variant:: $variant" diff --git a/board/versatile/u-boot.lds b/board/versatile/u-boot.lds index 82cb8e311..cb6ee188b 100644 --- a/board/versatile/u-boot.lds +++ b/board/versatile/u-boot.lds @@ -46,6 +46,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/versatile/versatile.c b/board/versatile/versatile.c index 3b9b0207a..9d1a25ec8 100644 --- a/board/versatile/versatile.c +++ b/board/versatile/versatile.c @@ -104,7 +104,7 @@ void flash__init (void) /************************************************************* Routine:ether__init Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. + for the EEPROM load to complete. *************************************************************/ void ether__init (void) { diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile index e7c1cbb31..6302fa854 100644 --- a/board/voiceblue/Makefile +++ b/board/voiceblue/Makefile @@ -1,4 +1,4 @@ -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de # # (C) Copyright 2005 @@ -24,51 +24,43 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := voiceblue.o +OBJS := voiceblue.o SOBJS := setup.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c eeprom_start.S -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) LOAD_ADDR = 0x10400000 LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds -lnk = $(if $(obj),$(obj),.) -all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin +all: $(LIB) eeprom.srec eeprom.bin $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) -$(obj)eeprom.srec: $(obj)eeprom.o $(obj)eeprom_start.o - cd $(lnk) && $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ - -o $(<:.o=) -e eeprom eeprom.o eeprom_start.o \ - -L$(obj)../../examples -lstubs \ - -L$(obj)../../lib_generic -lgeneric \ +eeprom.srec: eeprom.o eeprom_start.o + $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ + -o $(<:.o=) -e $(<:.o=) $^ \ + -L../../examples -lstubs \ + -L../../lib_generic -lgeneric \ -L$(gcclibdir) -lgcc $(OBJCOPY) -O srec $(<:.o=) $@ -$(obj)eeprom.bin: $(obj)eeprom.srec +eeprom.bin: eeprom.srec $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null clean: - rm -f $(SOBJS) $(OBJS) $(obj)eeprom \ - $(obj)eeprom.srec $(obj)eeprom.bin \ - $(obj)eeprom.o $(obj)eeprom_start.o - + rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core config.tmp *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/voiceblue/config.mk b/board/voiceblue/config.mk index 2cfc56ada..b77c91c65 100644 --- a/board/voiceblue/config.mk +++ b/board/voiceblue/config.mk @@ -1 +1,16 @@ +# +# Linux-Kernel is expected to be at 1000'8000, +# entry 1000'8000 (mem base + reserved) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifeq ($(VOICEBLUE_SMALL_FLASH),y) +# We load ourself to internal SRAM at 2001'2000 +# Check map file when changing TEXT_BASE. +# Everything has fit into 192kB internal SRAM! +TEXT_BASE = 0x20012000 +else +# Running in SDRAM... TEXT_BASE = 0x13FD0000 +endif diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c index d8ea6e573..0ad1b666b 100644 --- a/board/voiceblue/eeprom.c +++ b/board/voiceblue/eeprom.c @@ -26,7 +26,7 @@ #include #include -#include "../drivers/net/smc91111.h" +#include "../drivers/smc91111.h" #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE diff --git a/board/voiceblue/eeprom.lds b/board/voiceblue/eeprom.lds index 89b0a8209..317550dba 100644 --- a/board/voiceblue/eeprom.lds +++ b/board/voiceblue/eeprom.lds @@ -46,6 +46,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/voiceblue/setup.S b/board/voiceblue/setup.S index cc50e8c39..dcf37b5dc 100644 --- a/board/voiceblue/setup.S +++ b/board/voiceblue/setup.S @@ -77,7 +77,7 @@ MUX_CONFIG_VALUES: .word 0x00000000 @ FUNC_MUX_CTRL_3 .word 0x00000000 @ FUNC_MUX_CTRL_4 .word 0x12082480 @ FUNC_MUX_CTRL_5 - .word 0x0000001c @ FUNC_MUX_CTRL_6 + .word 0x00000004 @ FUNC_MUX_CTRL_6 .word 0x00000003 @ FUNC_MUX_CTRL_7 .word 0x10001200 @ FUNC_MUX_CTRL_8 .word 0x01201012 @ FUNC_MUX_CTRL_9 @@ -273,7 +273,7 @@ ulocking: mov r0, #0x4000 sdelay: subs r0, r0, #0x1 - bne sdelay + bne sdelay /* back to arch calling code */ mov pc, lr diff --git a/board/voiceblue/u-boot.lds b/board/voiceblue/u-boot.lds index bce925bbf..f35a3ab02 100644 --- a/board/voiceblue/u-boot.lds +++ b/board/voiceblue/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c index c8dde3651..04093d172 100644 --- a/board/voiceblue/voiceblue.c +++ b/board/voiceblue/voiceblue.c @@ -28,7 +28,8 @@ int board_init(void) *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa; /* arch number of VoiceBlue board */ - gd->bd->bi_arch_number = MACH_TYPE_VOICEBLUE; + /* TODO: use define from asm/mach-types.h */ + gd->bd->bi_arch_number = 218; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x10000100; @@ -40,8 +41,8 @@ int dram_init(void) { *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff; - /* Take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. */ + /* Take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. */ *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; udelay(10); /* doesn't work before interrupt_init call */ *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; diff --git a/board/w7o/Makefile b/board/w7o/Makefile index e481bb288..d008f896c 100644 --- a/board/w7o/Makefile +++ b/board/w7o/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2001 # Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. # @@ -26,30 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \ +OBJS = $(BOARD).o flash.o fpga.o fsboot.o post2.o vpd.o cmd_vpd.o \ watchdog.o SOBJS = init.o post1.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c index fdd6ceb8b..449089e4e 100644 --- a/board/w7o/cmd_vpd.c +++ b/board/w7o/cmd_vpd.c @@ -24,7 +24,7 @@ #include #include -#if defined(CONFIG_CMD_BSP) +#if (CONFIG_COMMANDS & CFG_CMD_BSP) #include "vpd.h" @@ -63,4 +63,4 @@ U_BOOT_CMD( " - Read VPD Data from default address, or device address 'dev_addr'.\n" ); -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_BSP) */ diff --git a/board/w7o/post1.S b/board/w7o/post1.S index a6f46c874..21d206e7c 100644 --- a/board/w7o/post1.S +++ b/board/w7o/post1.S @@ -62,7 +62,7 @@ * Switch to .data section. */ .section ".data" -err_str: .asciz "*** POST ERROR = " +err_str: .asciz "*** POST ERROR = " warn_str: .asciz "*** POST WARNING = " end_str: .asciz "\r\n" @@ -93,7 +93,7 @@ test_led: stw r0, +16(r1) /* Save link register */ stw r4, +8(r1) /* save R4 */ - WATCHDOG_RESET /* Reset the watchdog */ + WATCHDOG_RESET /* Reset the watchdog */ addi r3, 0, ERR_FF /* first test value is ffff */ addi r4, r3, 0 /* save copy of pattern */ @@ -155,7 +155,7 @@ l2_loop: addi r31, r3, 0 /* save original size */ /* now kick the dog and test the mem */ - WATCHDOG_RESET /* Reset the watchdog */ + WATCHDOG_RESET /* Reset the watchdog */ bl Data_Buster /* test crossed/shorted data lines */ addi r3, r30, 0 /* get log2(memsize) */ addi r4, r31, 0 /* get memsize */ @@ -257,7 +257,7 @@ clr_loop: addi r28, r28, 4 /* Increment to next word */ andi. r27, r28, 0xffff /* check for 2^16 loops */ bne clr_skip /* if not there, then skip */ - WATCHDOG_RESET /* kick the dog every now and then */ + WATCHDOG_RESET /* kick the dog every now and then */ clr_skip: bdnz clr_loop /* Round and round... */ @@ -272,7 +272,7 @@ outside: * thus the sequence 0,1,2,4,8,..,2^(n-1) * setting the bit is done with the following shift functions. */ - WATCHDOG_RESET /* Reset the watchdog */ + WATCHDOG_RESET /* Reset the watchdog */ addi r31, 0, 1 /* r31 = 1 */ slw r28, r31, r30 /* set bit coresponding to loop cnt */ @@ -301,20 +301,20 @@ inside: bne Casper /* we found a ghost! */ /* now close ghost ( inner ) loop */ - addi r29, r29, 1 /* increment inner loop counter */ - cmpw r29, r26 /* check for last inner loop */ + addi r29, r29, 1 /* increment inner loop counter */ + cmpw r29, r26 /* check for last inner loop */ blt inside /* do more inner loops */ /* now close referance ( outer ) loop */ - addi r31, 0, 0 /* r31 = zero */ + addi r31, 0, 0 /* r31 = zero */ stb r31, 0(28) /* zero out the altered address loc. */ /* * Increment and check for end, count is zero based. * With the ble, this gives us one more loops than * address bits for sequence 0,1,2,4,8,...2^(n-1) */ - addi r30, r30, 1 /* increment outer loop counter */ - cmpw r30, r26 /* check for last inner loop */ + addi r30, r30, 1 /* increment outer loop counter */ + cmpw r30, r26 /* check for last inner loop */ ble outside /* do more outer loops */ /* were done, lets go home */ @@ -391,7 +391,7 @@ fill_test: mr r28, r4 mr r29, r5 - WATCHDOG_RESET /* Reset the watchdog */ + WATCHDOG_RESET /* Reset the watchdog */ /* first fill memory with Value */ srawi r31, r29, 2 /* convert bytes to longs */ @@ -401,10 +401,10 @@ ft_0: stw r28, 0(r30) /* Store value */ addi r30, r30, 4 /* Increment to next word */ andi. r31, r30, 0xffff /* check for 2^16 loops */ bne ft_0a /* if not there, then skip */ - WATCHDOG_RESET /* kick the dog every now and then */ + WATCHDOG_RESET /* kick the dog every now and then */ ft_0a: bdnz ft_0 /* Round and round... */ - WATCHDOG_RESET /* Reset the watchdog */ + WATCHDOG_RESET /* Reset the watchdog */ /* Now confirm Value is in memory */ srawi r31, r29, 2 /* convert bytes to longs */ @@ -419,7 +419,7 @@ ft_1: lwz r31, 0(r30) /* get value from memory */ WATCHDOG_RESET /* kick the dog every now and then */ ft_1a: bdnz ft_1 /* Round and round... */ - WATCHDOG_RESET /* Reset the watchdog */ + WATCHDOG_RESET /* Reset the watchdog */ b fill_done /* restore and return */ @@ -608,9 +608,9 @@ temp_uart_init: /* output a few line feeds */ addi r3, 0, '\n' /* load line feed */ - bl post_putc /* output the char */ + bl post_putc /* output the char */ addi r3, 0, '\n' /* load line feed */ - bl post_putc /* output the char */ + bl post_putc /* output the char */ /* restore stack and return */ lwz r0, +12(r1) /* Get saved link register */ @@ -637,15 +637,15 @@ post_putc: addis r31, 0, 0xef60 /* Point to uart base */ ori r31, r31, 0x0300 - addis r30, 0, 152 /* Load about 10,000,000 ticks. */ + addis r30, 0, 152 /* Load about 10,000,000 ticks. */ pputc_lp: - lbz r29, 5(r31) /* Read Line Status Register */ + lbz r29, 5(r31) /* Read Line Status Register */ andi. r29, r29, 0x20 /* Check THRE status */ bne thre_set /* Branch if FIFO empty */ addic. r30, r30, -1 /* Decrement and check if empty. */ bne pputc_lp /* Try, try again */ addi r3, 0, -1 /* Load error code for timeout */ - b pputc_done /* Bail out with error code set */ + b pputc_done /* Bail out with error code set */ thre_set: stb r3, 0(r31) /* Store character to UART */ addi r3, 0, 0 /* clear error code */ @@ -671,7 +671,7 @@ post_puts: stw r0, +16(r1) /* Save link register */ stw r31, 8(r1) /* save r31 - char pointer */ - addi r31, r3, 0 /* move pointer to R31 */ + addi r31, r3, 0 /* move pointer to R31 */ pputs_nxt: lbz r3, 0(r31) /* Get next character */ addic. r3, r3, 0 /* Check for zero */ @@ -679,13 +679,13 @@ pputs_nxt: bl post_putc /* output the char */ addic. r3, r3, 0 /* check for error */ bne pputs_err - addi r31, r31, 1 /* point to next char */ - b pputs_nxt /* loop till term */ + addi r31, r31, 1 /* point to next char */ + b pputs_nxt /* loop till term */ pputs_err: - addi r3, 0, -1 /* set error code */ + addi r3, 0, -1 /* set error code */ b pputs_end /* were outa here */ pputs_term: - addi r3, 0, 1 /* set success code */ + addi r3, 0, 1 /* set success code */ /* restore stack and return */ pputs_end: lwz r31, 8(r1) /* restore r27 - r31 from stack */ @@ -711,20 +711,20 @@ disp_hex: stmw r30, 8(r1) /* save r30 - r31 on stack */ /* r31 output char */ /* r30 uart base address */ - addi r30, 0, 8 /* Go through 8 nibbles. */ - addi r31, r3, 0 + addi r30, 0, 8 /* Go through 8 nibbles. */ + addi r31, r3, 0 pputh_nxt: rlwinm r31, r31, 4, 0, 31 /* Rotate next nibble into position */ - andi. r3, r31, 0x0f /* Get nibble. */ - addi r3, r3, 0x30 /* Add zero's ASCII code. */ + andi. r3, r31, 0x0f /* Get nibble. */ + addi r3, r3, 0x30 /* Add zero's ASCII code. */ cmpwi r3, 0x03a blt pputh_out - addi r3, r3, 0x07 /* 0x27 for lower case. */ + addi r3, r3, 0x07 /* 0x27 for lower case. */ pputh_out: - cmpw r30, r4 + cmpw r30, r4 bgt pputh_skip bl post_putc - addic. r3, r3, 0 /* check for error */ + addic. r3, r3, 0 /* check for error */ bne pputh_err pputh_skip: addic. r30, r30, -1 @@ -732,7 +732,7 @@ pputh_skip: xor r3, r3, r3 /* Clear error code */ b pputh_done pputh_err: - addi r3, 0, -1 /* set error code */ + addi r3, 0, -1 /* set error code */ pputh_done: /* restore stack and return */ lmw r30, 8(r1) /* restore r30 - r31 from stack */ diff --git a/board/w7o/post2.c b/board/w7o/post2.c index 6ee33eba3..e59012824 100644 --- a/board/w7o/post2.c +++ b/board/w7o/post2.c @@ -29,12 +29,6 @@ #include "errors.h" #include "dtt.h" -/* for LM75 DTT POST test */ -#define DTT_READ_TEMP 0x0 -#define DTT_CONFIG 0x1 -#define DTT_TEMP_HYST 0x2 -#define DTT_TEMP_SET 0x3 - #if defined(CONFIG_RTC_M48T35A) void rtctest(void) { diff --git a/board/w7o/u-boot.lds b/board/w7o/u-boot.lds index 3373793c6..7e3e15dc2 100644 --- a/board/w7o/u-boot.lds +++ b/board/w7o/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -38,11 +39,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -122,7 +123,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug index d3ffed300..a0c72c921 100644 --- a/board/w7o/u-boot.lds.debug +++ b/board/w7o/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 0e3b84c61..c56c269da 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -31,7 +31,6 @@ #include unsigned long get_dram_size (void); -void sdram_init(void); /* * Macros to transform values @@ -152,15 +151,8 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { - /* - * ToDo: Move the asm init routine sdram_init() to this C file, - * or even better use some common ppc4xx code available - * in cpu/ppc4xx - */ - sdram_init(); - return get_dram_size (); } diff --git a/board/w7o/w7o.h b/board/w7o/w7o.h index d1fed028c..d6f50e2e6 100644 --- a/board/w7o/w7o.h +++ b/board/w7o/w7o.h @@ -31,6 +31,9 @@ #define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */ #define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */ +/* AMCC 405GP DCRs */ +#define CPC0_CR0 0xb1 /* Chip control register 0 */ + /* LMG FPGA <=> CPU GPIO signals */ #define LMG_XCV_INIT 0x10000000L #define LMG_XCV_PROG 0x04000000L diff --git a/board/wepep250/Makefile b/board/wepep250/Makefile index 0669b0ebb..11ad8fbec 100644 --- a/board/wepep250/Makefile +++ b/board/wepep250/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := wepep250.o flash.o +OBJS := wepep250.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c index e2e08f742..2a322903d 100644 --- a/board/wepep250/flash.c +++ b/board/wepep250/flash.c @@ -44,7 +44,6 @@ #if ( WEP_FLASH_BUS_WIDTH == 1 ) # define FLASH_BUS vu_char -# define FLASH_BUS_RET u_char # if ( WEP_FLASH_INTERLEAVE == 1 ) # define FLASH_CMD( x ) x # else @@ -54,7 +53,6 @@ #elif ( WEP_FLASH_BUS_WIDTH == 2 ) # define FLASH_BUS vu_short -# define FLASH_BUS_RET u_short # if ( WEP_FLASH_INTERLEAVE == 1 ) # define FLASH_CMD( x ) x # elif ( WEP_FLASH_INTERLEAVE == 2 ) @@ -66,7 +64,6 @@ #elif ( WEP_FLASH_BUS_WIDTH == 4 ) # define FLASH_BUS vu_long -# define FLASH_BUS_RET u_long # if ( WEP_FLASH_INTERLEAVE == 1 ) # define FLASH_CMD( x ) x # elif ( WEP_FLASH_INTERLEAVE == 2 ) @@ -84,7 +81,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -static FLASH_BUS_RET flash_status_reg (void) +static FLASH_BUS flash_status_reg (void) { FLASH_BUS *addr = (FLASH_BUS *) 0; diff --git a/board/wepep250/lowlevel_init.S b/board/wepep250/lowlevel_init.S index 9bb091f50..b172ceaa6 100644 --- a/board/wepep250/lowlevel_init.S +++ b/board/wepep250/lowlevel_init.S @@ -41,9 +41,9 @@ lowlevel_init: mov r10, lr /* setup memory - see 6.12 in [1] - * Step 1 - wait 200 us + * Step 1 - wait 200 us */ - mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */ + mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */ 1: subs r0, r0, #1 bne 1b /* TODO: complete step 1 for Synchronous Static memory*/ @@ -51,7 +51,7 @@ lowlevel_init: ldr r0, =0x48000000 /* MC_BASE */ -/* step 1.a - setup MSCx +/* step 1.a - setup MSCx */ ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */ str r1, [r0, #0x8] /* MSC0_OFFSET */ @@ -111,7 +111,7 @@ lowlevel_init: /* Step 5 - wait at least 200 us for SDRAM * see section B. in [2] */ - mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */ + mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */ 1: subs r2, r2, #1 bne 1b diff --git a/board/wepep250/u-boot.lds b/board/wepep250/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/wepep250/u-boot.lds +++ b/board/wepep250/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/westel/amx860/Makefile b/board/westel/amx860/Makefile index dcb190703..7a2014d46 100644 --- a/board/westel/amx860/Makefile +++ b/board/westel/amx860/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/westel/amx860/amx860.c b/board/westel/amx860/amx860.c index 4742aafc5..8826667cd 100644 --- a/board/westel/amx860/amx860.c +++ b/board/westel/amx860/amx860.c @@ -61,7 +61,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +long int initdram (int board_type) { volatile immap_t *immap = (immap_t *)CFG_IMMR; diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds index 10b38ec35..cdf550f67 100644 --- a/board/westel/amx860/u-boot.lds +++ b/board/westel/amx860/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -128,7 +129,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug index 7a7a40c23..87f228bee 100644 --- a/board/westel/amx860/u-boot.lds.debug +++ b/board/westel/amx860/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/xaeniax/Makefile b/board/xaeniax/Makefile index 7dd2ea04a..7c5f0cd1a 100644 --- a/board/xaeniax/Makefile +++ b/board/xaeniax/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := xaeniax.o flash.o +OBJS := xaeniax.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/xaeniax/u-boot.lds b/board/xaeniax/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/xaeniax/u-boot.lds +++ b/board/xaeniax/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/xilinx/common/xdma_channel.c b/board/xilinx/common/xdma_channel.c index f81613824..3d5fc75e3 100644 --- a/board/xilinx/common/xdma_channel.c +++ b/board/xilinx/common/xdma_channel.c @@ -226,7 +226,7 @@ XDmaChannel_GetVersion(XDmaChannel * InstancePtr) * XST_SUCCESS is returned if the self test is successful, or one of the * following errors. * -* XST_DMA_RESET_REGISTER_ERROR Indicates the control register value +* XST_DMA_RESET_REGISTER_ERROR Indicates the control register value * after a reset was not correct * * NOTES: @@ -475,7 +475,7 @@ XDmaChannel_GetStatus(XDmaChannel * InstancePtr) * XDC_IXR_DMA_DONE_MASK The dma operation is done * XDC_IXR_DMA_ERROR_MASK The dma operation had an error * XDC_IXR_PKT_DONE_MASK A packet is complete -* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached +* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached * XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached * XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed * XDC_IXR_BD_MASK A buffer descriptor is done @@ -533,7 +533,7 @@ XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status) * XDC_IXR_DMA_DONE_MASK The dma operation is done * XDC_IXR_DMA_ERROR_MASK The dma operation had an error * XDC_IXR_PKT_DONE_MASK A packet is complete -* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached +* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached * XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached * XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed * XDC_IXR_SG_END_MASK Current descriptor was the end of the list @@ -584,7 +584,7 @@ XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr) * XDC_IXR_DMA_DONE_MASK The dma operation is done * XDC_IXR_DMA_ERROR_MASK The dma operation had an error * XDC_IXR_PKT_DONE_MASK A packet is complete -* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached +* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached * XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached * XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed * XDC_IXR_SG_END_MASK Current descriptor was the end of the list @@ -638,7 +638,7 @@ XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable) * XDC_IXR_DMA_DONE_MASK The dma operation is done * XDC_IXR_DMA_ERROR_MASK The dma operation had an error * XDC_IXR_PKT_DONE_MASK A packet is complete -* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached +* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached * XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached * XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed * XDC_IXR_BD_MASK A buffer descriptor is done diff --git a/board/xilinx/common/xdma_channel.h b/board/xilinx/common/xdma_channel.h index 468598223..06976c3e0 100644 --- a/board/xilinx/common/xdma_channel.h +++ b/board/xilinx/common/xdma_channel.h @@ -96,7 +96,7 @@ * 1. Create a scatter gather list for the DMA channel which puts empty buffer * descriptors into the list. * 2. Create buffer descriptors which describe the buffers to be filled with -* receive data or the buffers which contain data to be sent. +* receive data or the buffers which contain data to be sent. * 3. Put buffer descriptors into the DMA channel scatter list such that scatter * gather operations are requested. * 4. Commit the buffer descriptors in the list such that they are ready to be @@ -208,7 +208,7 @@ #define XDC_IXR_DMA_DONE_MASK 0x1UL /* dma operation done */ #define XDC_IXR_DMA_ERROR_MASK 0x2UL /* dma operation error */ #define XDC_IXR_PKT_DONE_MASK 0x4UL /* packet done */ -#define XDC_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */ +#define XDC_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */ #define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL /* packet wait bound reached */ #define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL /* scatter gather disable acknowledge occurred */ diff --git a/board/xilinx/ml300/Makefile b/board/xilinx/ml300/Makefile index 9215d77bb..880c494c9 100644 --- a/board/xilinx/ml300/Makefile +++ b/board/xilinx/ml300/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -19,22 +19,14 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA -# include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../xilinx_enet) -$(shell mkdir -p $(obj)../xilinx_iic) -endif -INCS := -I../common -I../xilinx_enet -I../xilinx_iic -CFLAGS += $(INCS) -HOST_CFLAGS += $(INCS) +CFLAGS += -I../ml300 -I../common -I../xilinx_enet -I../xilinx_iic -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o \ +OBJS = $(BOARD).o \ serial.o \ ../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \ ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \ @@ -47,24 +39,20 @@ COBJS = $(BOARD).o \ SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/xilinx/ml300/init.S b/board/xilinx/ml300/init.S index a282c9ae2..f753df851 100644 --- a/board/xilinx/ml300/init.S +++ b/board/xilinx/ml300/init.S @@ -42,3 +42,7 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: blr + + .globl sdram_init +sdram_init: + blr diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c index 5d493eeb7..dad562f1c 100644 --- a/board/xilinx/ml300/ml300.c +++ b/board/xilinx/ml300/ml300.c @@ -38,9 +38,9 @@ * */ -#include #include #include +#include "xparameters.h" #ifdef CFG_ENV_IS_IN_EEPROM extern void convert_env(void); @@ -79,7 +79,7 @@ checkboard(void) return (0); } -phys_size_t +long int initdram(int board_type) { return 128 * 1024 * 1024; @@ -108,7 +108,7 @@ ulong get_PCI_freq(void) { ulong val; - PPC4xx_SYS_INFO sys_info; + PPC405_SYS_INFO sys_info; get_sys_info(&sys_info); val = sys_info.freqPCI; diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c index 993dfa30f..c204b88e4 100644 --- a/board/xilinx/ml300/serial.c +++ b/board/xilinx/ml300/serial.c @@ -36,11 +36,12 @@ * */ -#include #include #include +#include #include -#include +#include +#include "xparameters.h" DECLARE_GLOBAL_DATA_PTR; @@ -122,7 +123,7 @@ serial_puts(const char *s) } } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) void kgdb_serial_init(void) { @@ -151,4 +152,4 @@ kgdb_interruptible(int yes) { return; } -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/board/xilinx/ml300/u-boot.lds b/board/xilinx/ml300/u-boot.lds index 2d32225d4..b6d748e1d 100644 --- a/board/xilinx/ml300/u-boot.lds +++ b/board/xilinx/ml300/u-boot.lds @@ -23,6 +23,7 @@ OUTPUT_ARCH(powerpc) ENTRY(_start) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -34,11 +35,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -61,7 +62,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) @@ -136,7 +137,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/xilinx/ml300/u-boot.lds.debug b/board/xilinx/ml300/u-boot.lds.debug index 0552994f4..1608f8cda 100644 --- a/board/xilinx/ml300/u-boot.lds.debug +++ b/board/xilinx/ml300/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c index d3403038e..b30e89766 100644 --- a/board/xilinx/xilinx_enet/emac_adapter.c +++ b/board/xilinx/xilinx_enet/emac_adapter.c @@ -37,9 +37,9 @@ * ******************************************************************************/ -#include #include #include +#include "xparameters.h" #include "xemac.h" #if defined(XPAR_EMAC_0_DEVICE_ID) @@ -147,11 +147,7 @@ eth_rx(void) RecvFrameLength = PKTSIZE; Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength); if (Result == XST_SUCCESS) { -#ifndef CONFIG_EMACLITE NetReceive((uchar *)etherrxbuff, RecvFrameLength); -#else - NetReceive(etherrxbuff, RecvFrameLength); -#endif return (1); } else { return (0); diff --git a/board/xilinx/xilinx_enet/xemac.h b/board/xilinx/xilinx_enet/xemac.h index 584cb7ac5..ed704bf29 100644 --- a/board/xilinx/xilinx_enet/xemac.h +++ b/board/xilinx/xilinx_enet/xemac.h @@ -257,9 +257,9 @@ /***************************** Include Files *********************************/ -#include #include "xbasic_types.h" #include "xstatus.h" +#include "xparameters.h" #include "xpacket_fifo_v1_00_b.h" /* Uses v1.00b of Packet Fifo */ #include "xdma_channel.h" diff --git a/board/xilinx/xilinx_enet/xemac_g.c b/board/xilinx/xilinx_enet/xemac_g.c index d9851574f..9340f911f 100644 --- a/board/xilinx/xilinx_enet/xemac_g.c +++ b/board/xilinx/xilinx_enet/xemac_g.c @@ -43,7 +43,7 @@ * *******************************************************************/ -#include +#include "xparameters.h" #include "xemac.h" /* diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c index 37dce0391..163fe1511 100644 --- a/board/xilinx/xilinx_iic/iic_adapter.c +++ b/board/xilinx/xilinx_iic/iic_adapter.c @@ -37,10 +37,10 @@ * ******************************************************************************/ -#include #include #include #include +#include "xparameters.h" #ifdef CFG_ENV_IS_IN_EEPROM #include diff --git a/board/xm250/Makefile b/board/xm250/Makefile index a174f6619..1b0a3f017 100644 --- a/board/xm250/Makefile +++ b/board/xm250/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := xm250.o flash.o +OBJS := xm250.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/xm250/u-boot.lds b/board/xm250/u-boot.lds index bf42e9f3d..db8387520 100644 --- a/board/xm250/u-boot.lds +++ b/board/xm250/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c index 56b1cd4f4..528d3239c 100644 --- a/board/xm250/xm250.c +++ b/board/xm250/xm250.c @@ -50,6 +50,14 @@ sleep (int i) * Miscelaneous platform dependent initialisations */ +int +/**********************************************************/ +board_post_init (void) +/**********************************************************/ +{ + return (0); +} + int /**********************************************************/ board_init (void) diff --git a/board/xpedite1k/Makefile b/board/xpedite1k/Makefile index 6ab1a26b1..c5c09152d 100644 --- a/board/xpedite1k/Makefile +++ b/board/xpedite1k/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2002-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o +OBJS +=flash.o SOBJS = init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/board/xpedite1k/u-boot.lds b/board/xpedite1k/u-boot.lds index 70b1e38f3..0f0863710 100644 --- a/board/xpedite1k/u-boot.lds +++ b/board/xpedite1k/u-boot.lds @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -43,11 +44,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -70,7 +71,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) @@ -144,7 +145,7 @@ SECTIONS __init_end = .; __bss_start = .; - .bss (NOLOAD) : + .bss : { *(.sbss) *(.scommon) *(.dynbss) diff --git a/board/xpedite1k/u-boot.lds.debug b/board/xpedite1k/u-boot.lds.debug index e0da854a4..506632692 100644 --- a/board/xpedite1k/u-boot.lds.debug +++ b/board/xpedite1k/u-boot.lds.debug @@ -22,6 +22,7 @@ */ OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); /* Do we need any of these for elf? __DYNAMIC = 0; */ SECTIONS @@ -33,11 +34,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -60,7 +61,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) + cpu/ppc4xx/serial.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c index bc7e3bd17..a569b5347 100644 --- a/board/xpedite1k/xpedite1k.c +++ b/board/xpedite1k/xpedite1k.c @@ -104,7 +104,7 @@ int checkboard (void) } -phys_size_t initdram (int board_type) +long int initdram (int board_type) { long dram_size = 0; @@ -209,7 +209,7 @@ long int fixed_sdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -227,7 +227,7 @@ int pci_pre_init(struct pci_controller * hose ) #endif return 1; } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* * pci_target_init diff --git a/board/xsengine/Makefile b/board/xsengine/Makefile index fc239358b..ed1464af3 100644 --- a/board/xsengine/Makefile +++ b/board/xsengine/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,29 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := xsengine.o flash.o +OBJS := xsengine.o flash.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c index a188e2440..2b9afc7a7 100644 --- a/board/xsengine/flash.c +++ b/board/xsengine/flash.c @@ -46,11 +46,11 @@ unsigned long flash_init (void) for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { switch (i) { case 0: - flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]); + flash_get_size ((long *) PHYS_FLASH_1, &flash_info[i]); flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); break; case 1: - flash_get_size ((vu_long *) PHYS_FLASH_2, &flash_info[i]); + flash_get_size ((long *) PHYS_FLASH_2, &flash_info[i]); flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); break; default: diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S index b0b156124..309faabd9 100644 --- a/board/xsengine/lowlevel_init.S +++ b/board/xsengine/lowlevel_init.S @@ -109,7 +109,7 @@ lowlevel_init: ldr r3, =OSCR /* reset the OS Timer Count to zero */ mov r2, #0 str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */ + ldr r4, =0x300 /* really 0x2E1 is about 200usec, so 0x300 should be plenty */ 1: ldr r2, [r3] cmp r4, r2 @@ -144,7 +144,7 @@ mem_init: ldr r3, =OSCR /* reset the OS Timer Count to zero */ mov r2, #0 str r2, [r3] - ldr r4, =0x300 /* about 200 usec */ + ldr r4, =0x300 /* about 200 usec */ 1: ldr r2, [r3] cmp r4, r2 diff --git a/board/xsengine/u-boot.lds b/board/xsengine/u-boot.lds index bf42e9f3d..db8387520 100644 --- a/board/xsengine/u-boot.lds +++ b/board/xsengine/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c index 65923e92c..23d56c43a 100644 --- a/board/xsengine/xsengine.c +++ b/board/xsengine/xsengine.c @@ -47,7 +47,7 @@ int board_init (void) return 0; } -int board_late_init (void) +int board_post_init (void) { setenv ("stdout", "serial"); setenv ("stderr", "serial"); diff --git a/board/zpc1900/Makefile b/board/zpc1900/Makefile index dc40d9b94..8b1099319 100644 --- a/board/zpc1900/Makefile +++ b/board/zpc1900/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := $(BOARD).o +OBJS := $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/zpc1900/u-boot.lds b/board/zpc1900/u-boot.lds new file mode 100644 index 000000000..18c4b46f4 --- /dev/null +++ b/board/zpc1900/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Modified by Yuli Barcohen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c index 103ef714f..7db535e8a 100644 --- a/board/zpc1900/zpc1900.c +++ b/board/zpc1900/zpc1900.c @@ -220,7 +220,7 @@ void nvram_write(long dest, const void *src, size_t count) } #endif /* CFG_NVRAM_ACCESS_ROUTINE */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { vu_char *bcsr = (vu_char *)CFG_BCSR; volatile immap_t *immap = (immap_t *)CFG_IMMR; diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile index 89542356b..f3ad67458 100644 --- a/board/zylonite/Makefile +++ b/board/zylonite/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -20,32 +20,27 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +LIB = lib$(BOARD).a -COBJS := zylonite.o nand.o +OBJS := zylonite.o nand.o SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak $(obj).depend + rm -f $(LIB) core *.bak .depend ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +-include .depend ######################################################################### diff --git a/board/zylonite/config.mk b/board/zylonite/config.mk index 09b0f7155..b5d5955ef 100644 --- a/board/zylonite/config.mk +++ b/board/zylonite/config.mk @@ -2,3 +2,5 @@ #TEXT_BASE = 0xa1700000 #TEXT_BASE = 0xa3080000 TEXT_BASE = 0xa3008000 + +BOARDLIBS = drivers/nand/libnand.a diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c index ca1657843..5d2cd6585 100644 --- a/board/zylonite/nand.c +++ b/board/zylonite/nand.c @@ -22,7 +22,7 @@ #include -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #ifdef CONFIG_NEW_NAND_CODE #include @@ -254,7 +254,7 @@ static unsigned long dfc_wait_event(unsigned long event) break; } if(get_delta(start) > timeout) { - DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event); + DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event); return 0xff000000; } @@ -448,7 +448,7 @@ static void dfc_gpio_init(void) * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init(struct nand_chip *nand) { unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; @@ -576,7 +576,6 @@ int board_nand_init(struct nand_chip *nand) nand->cmdfunc = dfc_cmdfunc; nand->autooob = &delta_oob; nand->badblock_pattern = &delta_bbt_descr; - return 0; } #else diff --git a/board/zylonite/u-boot.lds b/board/zylonite/u-boot.lds index 14d264a68..f0102391b 100644 --- a/board/zylonite/u-boot.lds +++ b/board/zylonite/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss : { *(.bss) } _end = .; } diff --git a/common/ACEX1K.c b/common/ACEX1K.c index 76dc16643..2a421e2da 100644 --- a/common/ACEX1K.c +++ b/common/ACEX1K.c @@ -28,7 +28,7 @@ #include /* core U-Boot definitions */ #include /* ACEX device family */ -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K) +#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) /* Define FPGA_DEBUG to get debug printf's */ #ifdef FPGA_DEBUG @@ -363,4 +363,4 @@ static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset) } -#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */ +#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */ diff --git a/common/Makefile b/common/Makefile index 42871087a..cb448891d 100644 --- a/common/Makefile +++ b/common/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2004-2006 +# (C) Copyright 2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,152 +23,64 @@ include $(TOPDIR)/config.mk -LIB = $(obj)libcommon.a +LIB = libcommon.a AOBJS = -COBJS-y += main.o -COBJS-y += ACEX1K.o -COBJS-y += altera.o -COBJS-y += bedbug.o -COBJS-y += circbuf.o -COBJS-$(CONFIG_CMD_AMBAPP) += cmd_ambapp.o -COBJS-y += cmd_autoscript.o -COBJS-$(CONFIG_CMD_BDI) += cmd_bdinfo.o -COBJS-$(CONFIG_CMD_BEDBUG) += cmd_bedbug.o -COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o -COBJS-y += image.o -COBJS-y += gunzip.o -COBJS-y += cmd_boot.o -COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o -COBJS-y += cmd_bootm.o -COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o -COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o -COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o -COBJS-$(CONFIG_CMD_DATE) += cmd_date.o -ifdef CONFIG_4xx -COBJS-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o -endif -ifdef CONFIG_POST -COBJS-$(CONFIG_CMD_DIAG) += cmd_diag.o -endif -COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o -COBJS-$(CONFIG_CMD_DOC) += cmd_doc.o -COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o -COBJS-y += cmd_eeprom.o -COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o -COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o -COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o -COBJS-y += cmd_fdc.o -COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o -COBJS-$(CONFIG_CMD_FDOS) += cmd_fdos.o -COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o -ifdef CONFIG_FPGA -COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o -endif -COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o -COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o -COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o -COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o -COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o -COBJS-y += cmd_load.o -COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o -COBJS-y += cmd_mem.o -COBJS-$(CONFIG_CMD_MII) += cmd_mii.o -COBJS-$(CONFIG_CMD_MISC) += cmd_misc.o -COBJS-$(CONFIG_CMD_MMC) += cmd_mmc.o -COBJS-y += cmd_nand.o -COBJS-$(CONFIG_CMD_NET) += cmd_net.o -COBJS-y += cmd_nvedit.o -COBJS-y += cmd_onenand.o -COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o -ifdef CONFIG_PCI -COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o -endif -COBJS-y += cmd_pcmcia.o -COBJS-$(CONFIG_CMD_PORTIO) += cmd_portio.o -COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o -COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o -COBJS-$(CONFIG_CMD_SATA) += cmd_sata.o -COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o -COBJS-$(CONFIG_CMD_SETEXPR) += cmd_setexpr.o -COBJS-$(CONFIG_CMD_SPI) += cmd_spi.o -COBJS-$(CONFIG_CMD_STRINGS) += cmd_strings.o -COBJS-$(CONFIG_CMD_TERMINAL) += cmd_terminal.o -COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o -COBJS-$(CONFIG_CMD_USB) += cmd_usb.o -COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o -COBJS-y += cmd_vfd.o -COBJS-y += command.o -COBJS-y += console.o -COBJS-y += cyclon2.o -COBJS-y += stratixII.o -COBJS-y += devices.o -COBJS-y += dlmalloc.o -COBJS-y += docecc.o -COBJS-y += environment.o -COBJS-y += env_common.o -COBJS-y += env_nand.o -COBJS-y += env_dataflash.o -COBJS-y += env_flash.o -COBJS-y += env_eeprom.o -COBJS-y += env_onenand.o -COBJS-y += env_sf.o -COBJS-y += env_nvram.o -COBJS-y += env_nowhere.o -COBJS-y += exports.o -COBJS-y += flash.o -COBJS-y += fpga.o -COBJS-y += hush.o -COBJS-y += kgdb.o -COBJS-y += lcd.o -COBJS-y += lists.o -COBJS-y += lynxkdi.o -COBJS-y += memsize.o -COBJS-y += miiphybb.o -COBJS-y += miiphyutil.o -COBJS-y += s_record.o -COBJS-y += serial.o -COBJS-y += soft_i2c.o -COBJS-y += soft_spi.o -COBJS-y += spartan2.o -COBJS-y += spartan3.o -COBJS-y += usb.o -COBJS-y += usb_kbd.o -COBJS-y += usb_storage.o -COBJS-y += virtex2.o -COBJS-y += xilinx.o -COBJS-y += crc16.o -COBJS-y += xyzModem.o -COBJS-y += cmd_mac.o -COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o -COBJS-$(CONFIG_MP) += cmd_mp.o -COBJS-$(CONFIG_CMD_SF) += cmd_sf.o +COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ + cmd_ace.o cmd_autoscript.o \ + cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \ + cmd_cache.o \ + cmd_clock.o \ + cmd_console.o \ + cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \ + cmd_eeprom.o cmd_elf.o cmd_ext2.o \ + cmd_fastboot.o cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_flipflop.o cmd_fpga.o \ + cmd_i2c.o cmd_ide.o cmd_immap.o cmd_itest.o cmd_jffs2.o \ + cmd_ignore.o \ + cmd_load.o cmd_log.o \ + cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ + cmd_nand.o cmd_net.o cmd_nvedit.o \ + cmd_onenand.o \ + cmd_pci.o cmd_pcmcia.o cmd_portio.o \ + cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \ + cmd_usb.o cmd_vfd.o \ + cmd_voltage.o \ + command.o console.o devices.o dlmalloc.o docecc.o \ + environment.o env_common.o \ + env_nand.o env_dataflash.o env_flash.o env_eeprom.o \ + env_nvram.o env_nowhere.o env_onenand.o \ + env_mmc.o \ + exports.o \ + flash.o fpga.o ft_build.o \ + hush.o kgdb.o lcd.o lists.o lynxkdi.o \ + memsize.o miiphybb.o miiphyutil.o \ + s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \ + usb.o usb_kbd.o usb_storage.o \ + virtex2.o xilinx.o crc16.o xyzModem.o -COBJS := $(COBJS-y) -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) +OBJS = $(AOBJS) $(COBJS) CPPFLAGS += -I.. all: $(LIB) $(AOBJS) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) -$(obj)environment.o: $(src)environment.c $(obj)../tools/envcrc +environment.o: environment.c ../tools/envcrc $(CC) $(AFLAGS) -Wa,--no-warn \ - -DENV_CRC=$(shell $(obj)../tools/envcrc) \ - -c -o $@ $(src)environment.c + -DENV_CRC=$(shell ../tools/envcrc) \ + -c -o $@ environment.c -$(obj)../tools/envcrc: +../tools/envcrc: $(MAKE) -C ../tools ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/common/altera.c b/common/altera.c index a2b5967ec..ebd50382c 100644 --- a/common/altera.c +++ b/common/altera.c @@ -30,7 +30,6 @@ */ #include #include -#include /* Define FPGA_DEBUG to get debug printf's */ /* #define FPGA_DEBUG */ @@ -41,43 +40,31 @@ #define PRINTF(fmt,args...) #endif -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) +#if (CONFIG_FPGA & CFG_FPGA_ALTERA) /* Local Static Functions */ -static int altera_validate (Altera_desc * desc, const char *fn); +static int altera_validate (Altera_desc * desc, char *fn); /* ------------------------------------------------------------------------- */ int altera_load( Altera_desc *desc, void *buf, size_t bsize ) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate (desc, (char *)__FUNCTION__)) { + if (!altera_validate (desc, __FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else { switch (desc->family) { case Altera_ACEX1K: - case Altera_CYC2: -#if defined(CONFIG_FPGA_ACEX1K) +#if (CONFIG_FPGA & CFG_ACEX1K) PRINTF ("%s: Launching the ACEX1K Loader...\n", __FUNCTION__); ret_val = ACEX1K_load (desc, buf, bsize); -#elif defined(CONFIG_FPGA_CYCLON2) - PRINTF ("%s: Launching the CYCLON II Loader...\n", - __FUNCTION__); - ret_val = CYC2_load (desc, buf, bsize); #else printf ("%s: No support for ACEX1K devices.\n", __FUNCTION__); #endif break; -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - PRINTF ("%s: Launching the Stratix II Loader...\n", - __FUNCTION__); - ret_val = StratixII_load (desc, buf, bsize); - break; -#endif default: printf ("%s: Unsupported family type, %d\n", __FUNCTION__, desc->family); @@ -91,12 +78,12 @@ int altera_dump( Altera_desc *desc, void *buf, size_t bsize ) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate (desc, (char *)__FUNCTION__)) { + if (!altera_validate (desc, __FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else { switch (desc->family) { case Altera_ACEX1K: -#if defined(CONFIG_FPGA_ACEX) +#if (CONFIG_FPGA & CFG_ACEX) PRINTF ("%s: Launching the ACEX1K Reader...\n", __FUNCTION__); ret_val = ACEX1K_dump (desc, buf, bsize); @@ -106,13 +93,6 @@ int altera_dump( Altera_desc *desc, void *buf, size_t bsize ) #endif break; -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - PRINTF ("%s: Launching the Stratix II Reader...\n", - __FUNCTION__); - ret_val = StratixII_dump (desc, buf, bsize); - break; -#endif default: printf ("%s: Unsupported family type, %d\n", __FUNCTION__, desc->family); @@ -126,18 +106,12 @@ int altera_info( Altera_desc *desc ) { int ret_val = FPGA_FAIL; - if (altera_validate (desc, (char *)__FUNCTION__)) { + if (altera_validate (desc, __FUNCTION__)) { printf ("Family: \t"); switch (desc->family) { case Altera_ACEX1K: printf ("ACEX1K\n"); break; - case Altera_CYC2: - printf ("CYCLON II\n"); - break; - case Altera_StratixII: - printf ("Stratix II\n"); - break; /* Add new family types here */ default: printf ("Unknown family type, %d\n", desc->family); @@ -160,13 +134,6 @@ int altera_info( Altera_desc *desc ) case altera_jtag_mode: /* Not used */ printf ("JTAG Mode\n"); break; - case fast_passive_parallel: - printf ("Fast Passive Parallel (FPP)\n"); - break; - case fast_passive_parallel_security: - printf - ("Fast Passive Parallel with Security (FPPS) \n"); - break; /* Add new interface types here */ default: printf ("Unsupported interface type, %d\n", desc->iface); @@ -180,22 +147,14 @@ int altera_info( Altera_desc *desc ) printf ("Device Function Table @ 0x%p\n", desc->iface_fns); switch (desc->family) { case Altera_ACEX1K: - case Altera_CYC2: -#if defined(CONFIG_FPGA_ACEX1K) +#if (CONFIG_FPGA & CFG_ACEX1K) ACEX1K_info (desc); -#elif defined(CONFIG_FPGA_CYCLON2) - CYC2_info (desc); #else /* just in case */ printf ("%s: No support for ACEX1K devices.\n", __FUNCTION__); #endif break; -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - StratixII_info (desc); - break; -#endif /* Add new family types here */ default: /* we don't need a message here - we give one up above */ @@ -217,29 +176,16 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset) { int ret_val = FPGA_FAIL; /* assume a failure */ - if (!altera_validate (desc, (char *)__FUNCTION__)) { + if (!altera_validate (desc, __FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else { switch (desc->family) { case Altera_ACEX1K: -#if defined(CONFIG_FPGA_ACEX1K) +#if (CONFIG_FPGA & CFG_ACEX1K) ret_val = ACEX1K_reloc (desc, reloc_offset); #else printf ("%s: No support for ACEX devices.\n", __FUNCTION__); -#endif - break; -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - ret_val = StratixII_reloc (desc, reloc_offset); - break; -#endif - case Altera_CYC2: -#if defined(CONFIG_FPGA_CYCLON2) - ret_val = CYC2_reloc (desc, reloc_offset); -#else - printf ("%s: No support for CYCLON II devices.\n", - __FUNCTION__); #endif break; /* Add new family types here */ @@ -254,7 +200,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset) /* ------------------------------------------------------------------------- */ -static int altera_validate (Altera_desc * desc, const char *fn) +static int altera_validate (Altera_desc * desc, char *fn) { int ret_val = FALSE; @@ -284,4 +230,4 @@ static int altera_validate (Altera_desc * desc, const char *fn) /* ------------------------------------------------------------------------- */ -#endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */ +#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */ diff --git a/common/bedbug.c b/common/bedbug.c index 3bf1fc3cc..6966de744 100644 --- a/common/bedbug.c +++ b/common/bedbug.c @@ -2,7 +2,7 @@ #include -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) #include #include @@ -1253,4 +1253,4 @@ int find_next_address (unsigned char *nextaddr, int step_over, * purpose. */ -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_BEDBUG */ diff --git a/common/cmd_ace.c b/common/cmd_ace.c new file mode 100644 index 000000000..b6d61057f --- /dev/null +++ b/common/cmd_ace.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2004 Picture Elements, Inc. + * Stephen Williams (XXXXXXXXXXXXXXXX) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +#ident "$Id:$" + +/* + * The Xilinx SystemACE chip support is activated by defining + * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE + * to set the base address of the device. This code currently + * assumes that the chip is connected via a byte-wide bus. + * + * The CONFIG_SYSTEMACE also adds to fat support the device class + * "ace" that allows the user to execute "fatls ace 0" and the + * like. This works by making the systemace_get_dev function + * available to cmd_fat.c:get_dev and filling in a block device + * description that has all the bits needed for FAT support to + * read sectors. + * + * According to Xilinx technical support, before accessing the + * SystemACE CF you need to set the following control bits: + * FORCECFGMODE : 1 + * CFGMODE : 0 + * CFGSTART : 0 + */ + +# include +# include +# include +# include +# include + +#ifdef CONFIG_SYSTEMACE + +/* + * The ace_readw and writew functions read/write 16bit words, but the + * offset value is the BYTE offset as most used in the Xilinx + * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined + * to be the base address for the chip, usually in the local + * peripheral bus. + */ +static unsigned ace_readw(unsigned offset) +{ +#if (CFG_SYSTEMACE_WIDTH == 8) + u16 temp; + +#if !defined(__BIG_ENDIAN) + temp =((u16)readb(CFG_SYSTEMACE_BASE+offset) << 8); + temp |= (u16)readb(CFG_SYSTEMACE_BASE+offset+1); +#else + temp = (u16)readb(CFG_SYSTEMACE_BASE+offset); + temp |=((u16)readb(CFG_SYSTEMACE_BASE+offset+1) << 8); +#endif + return temp; +#else + return readw(CFG_SYSTEMACE_BASE+offset); +#endif +} + +static void ace_writew(unsigned val, unsigned offset) +{ +#if (CFG_SYSTEMACE_WIDTH == 8) +#if !defined(__BIG_ENDIAN) + writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset); + writeb((u8)val, CFG_SYSTEMACE_BASE+offset+1); +#else + writeb((u8)val, CFG_SYSTEMACE_BASE+offset); + writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset+1); +#endif +#else + writew(val, CFG_SYSTEMACE_BASE+offset); +#endif +} + +/* */ + +static unsigned long systemace_read(int dev, + unsigned long start, + unsigned long blkcnt, + unsigned long *buffer); + +static block_dev_desc_t systemace_dev = {0}; + +static int get_cf_lock(void) +{ + int retry = 10; + + /* CONTROLREG = LOCKREG */ + unsigned val=ace_readw(0x18); + val|=0x0002; + ace_writew((val&0xffff), 0x18); + + /* Wait for MPULOCK in STATUSREG[15:0] */ + while (! (ace_readw(0x04) & 0x0002)) { + + if (retry < 0) + return -1; + + udelay(100000); + retry -= 1; + } + + return 0; +} + +static void release_cf_lock(void) +{ + unsigned val=ace_readw(0x18); + val&=~(0x0002); + ace_writew((val&0xffff), 0x18); +} + +block_dev_desc_t * systemace_get_dev(int dev) +{ + /* The first time through this, the systemace_dev object is + not yet initialized. In that case, fill it in. */ + if (systemace_dev.blksz == 0) { + systemace_dev.if_type = IF_TYPE_UNKNOWN; + systemace_dev.dev = 0; + systemace_dev.part_type = PART_TYPE_UNKNOWN; + systemace_dev.type = DEV_TYPE_HARDDISK; + systemace_dev.blksz = 512; + systemace_dev.removable = 1; + systemace_dev.block_read = systemace_read; + + init_part(&systemace_dev); + + } + + return &systemace_dev; +} + +/* + * This function is called (by dereferencing the block_read pointer in + * the dev_desc) to read blocks of data. The return value is the + * number of blocks read. A zero return indicates an error. + */ +static unsigned long systemace_read(int dev, + unsigned long start, + unsigned long blkcnt, + unsigned long *buffer) +{ + int retry; + unsigned blk_countdown; + unsigned char*dp = (unsigned char*)buffer; + unsigned val; + + if (get_cf_lock() < 0) { + unsigned status = ace_readw(0x04); + + /* If CFDETECT is false, card is missing. */ + if (! (status&0x0010)) { + printf("** CompactFlash card not present. **\n"); + return 0; + } + + printf("**** ACE locked away from me (STATUSREG=%04x)\n", status); + return 0; + } + +#ifdef DEBUG_SYSTEMACE + printf("... systemace read %lu sectors at %lu\n", blkcnt, start); +#endif + + retry = 2000; + for (;;) { + val = ace_readw(0x04); + + /* If CFDETECT is false, card is missing. */ + if (! (val & 0x0010)) { + printf("**** ACE CompactFlash not found.\n"); + release_cf_lock(); + return 0; + } + + /* If RDYFORCMD, then we are ready to go. */ + if (val & 0x0100) + break; + + if (retry < 0) { + printf("**** SystemACE not ready.\n"); + release_cf_lock(); + return 0; + } + + udelay(1000); + retry -= 1; + } + + /* The SystemACE can only transfer 256 sectors at a time, so + limit the current chunk of sectors. The blk_countdown + variable is the number of sectors left to transfer. */ + + blk_countdown = blkcnt; + while (blk_countdown > 0) { + unsigned trans = blk_countdown; + + if (trans > 256) trans = 256; + +#ifdef DEBUG_SYSTEMACE + printf("... transfer %lu sector in a chunk\n", trans); +#endif + /* Write LBA block address */ + ace_writew((start>> 0) & 0xffff, 0x10); + ace_writew((start>>16) & 0x00ff, 0x12); + + /* NOTE: in the Write Sector count below, a count of 0 + causes a transfer of 256, so &0xff gives the right + value for whatever transfer count we want. */ + + /* Write sector count | ReadMemCardData. */ + ace_writew((trans&0xff) | 0x0300, 0x14); + + /* Reset the configruation controller */ + val = ace_readw(0x18); + val|=0x0080; + ace_writew(val, 0x18); + + retry = trans * 16; + while (retry > 0) { + int idx; + + /* Wait for buffer to become ready. */ + while (! (ace_readw(0x04) & 0x0020)) { + udelay(100); + } + + /* Read 16 words of 2bytes from the sector buffer. */ + for (idx = 0 ; idx < 16 ; idx += 1) { + unsigned short val = ace_readw(0x40); + *dp++ = val & 0xff; + *dp++ = (val>>8) & 0xff; + } + + retry -= 1; + } + + /* Clear the configruation controller reset */ + val = ace_readw(0x18); + val&=~0x0080; + ace_writew(val, 0x18); + + /* Count the blocks we transfer this time. */ + start += trans; + blk_countdown -= trans; + } + + release_cf_lock(); + + return blkcnt; +} +#endif /* CONFIG_SYSTEMACE */ diff --git a/common/cmd_autoscript.c b/common/cmd_autoscript.c index 13af93ec8..e3253022d 100644 --- a/common/cmd_autoscript.c +++ b/common/cmd_autoscript.c @@ -47,112 +47,60 @@ #include #endif -#if defined(CONFIG_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) +#if defined(CONFIG_AUTOSCRIPT) || \ + (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT ) +extern image_header_t header; /* from cmd_bootm.c */ int -autoscript (ulong addr, const char *fit_uname) +autoscript (ulong addr) { - ulong len; - image_header_t *hdr; - ulong *data; - char *cmd; - int rcode = 0; - int verify; -#if defined(CONFIG_FIT) - const void* fit_hdr; - int noffset; - const void *fit_data; - size_t fit_len; -#endif + ulong crc, data, len; + image_header_t *hdr = &header; + ulong *len_ptr; + char *cmd; + int rcode = 0; + int verify; - verify = getenv_yesno ("verify"); + cmd = getenv ("verify"); + verify = (cmd && (*cmd == 'n')) ? 0 : 1; - switch (genimg_get_format ((void *)addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *)addr; - if (!image_check_magic (hdr)) { - puts ("Bad magic number\n"); + memmove (hdr, (char *)addr, sizeof(image_header_t)); + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + puts ("Bad magic number\n"); + return 1; + } + + crc = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + len = sizeof (image_header_t); + data = (ulong)hdr; + if (crc32(0, (uchar *)data, len) != crc) { + puts ("Bad header crc\n"); + return 1; + } + + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + + if (verify) { + if (crc32(0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { + puts ("Bad data crc\n"); return 1; } + } - if (!image_check_hcrc (hdr)) { - puts ("Bad header crc\n"); - return 1; - } + if (hdr->ih_type != IH_TYPE_SCRIPT) { + puts ("Bad image type\n"); + return 1; + } - if (verify) { - if (!image_check_dcrc (hdr)) { - puts ("Bad data crc\n"); - return 1; - } - } + /* get length of script */ + len_ptr = (ulong *)data; - if (!image_check_type (hdr, IH_TYPE_SCRIPT)) { - puts ("Bad image type\n"); - return 1; - } - - /* get length of script */ - data = (ulong *)image_get_data (hdr); - - if ((len = uimage_to_cpu (*data)) == 0) { - puts ("Empty Script\n"); - return 1; - } - - /* - * scripts are just multi-image files with one component, seek - * past the zero-terminated sequence of image lengths to get - * to the actual image data - */ - while (*data++); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - if (fit_uname == NULL) { - puts ("No FIT subimage unit name\n"); - return 1; - } - - fit_hdr = (const void *)addr; - if (!fit_check_format (fit_hdr)) { - puts ("Bad FIT image format\n"); - return 1; - } - - /* get script component image node offset */ - noffset = fit_image_get_node (fit_hdr, fit_uname); - if (noffset < 0) { - printf ("Can't find '%s' FIT subimage\n", fit_uname); - return 1; - } - - if (!fit_image_check_type (fit_hdr, noffset, IH_TYPE_SCRIPT)) { - puts ("Not a image image\n"); - return 1; - } - - /* verify integrity */ - if (verify) { - if (!fit_image_check_hashes (fit_hdr, noffset)) { - puts ("Bad Data Hash\n"); - return 1; - } - } - - /* get script subimage data address and length */ - if (fit_image_get_data (fit_hdr, noffset, &fit_data, &fit_len)) { - puts ("Could not find script subimage data\n"); - return 1; - } - - data = (ulong *)fit_data; - len = (ulong)fit_len; - break; -#endif - default: - puts ("Wrong image format for autoscript\n"); + if ((len = ntohl(*len_ptr)) == 0) { + puts ("Empty Script\n"); return 1; } @@ -162,8 +110,10 @@ autoscript (ulong addr, const char *fit_uname) return 1; } + while (*len_ptr++); + /* make sure cmd is null terminated */ - memmove (cmd, (char *)data, len); + memmove (cmd, (char *)len_ptr, len); *(cmd + len) = 0; #ifdef CFG_HUSH_PARSER /*?? */ @@ -200,44 +150,33 @@ autoscript (ulong addr, const char *fit_uname) return rcode; } -#endif - +#endif /* CONFIG_AUTOSCRIPT || CFG_CMD_AUTOSCRIPT */ /**************************************************/ -#if defined(CONFIG_CMD_AUTOSCRIPT) +#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) int do_autoscript (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong addr; int rcode; - const char *fit_uname = NULL; - /* Find script image */ if (argc < 2) { addr = CFG_LOAD_ADDR; - debug ("* autoscr: default load address = 0x%08lx\n", addr); -#if defined(CONFIG_FIT) - } else if (fit_parse_subimage (argv[1], load_addr, &addr, &fit_uname)) { - debug ("* autoscr: subimage '%s' from FIT image at 0x%08lx\n", - fit_uname, addr); -#endif } else { - addr = simple_strtoul(argv[1], NULL, 16); - debug ("* autoscr: cmdline image address = 0x%08lx\n", addr); + addr = simple_strtoul (argv[1],0,16); } - printf ("## Executing script at %08lx\n", addr); - rcode = autoscript (addr, fit_uname); + printf ("## Executing script at %08lx\n",addr); + rcode = autoscript (addr); return rcode; } +#if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) U_BOOT_CMD( autoscr, 2, 0, do_autoscript, "autoscr - run script from memory\n", "[addr] - run script starting at addr" " - A valid autoscr header must be present\n" -#if defined(CONFIG_FIT) - "For FIT format uImage addr must include subimage\n" - "unit name in the form of addr:\n" -#endif ); -#endif +#endif /* CFG_CMD_AUTOSCRIPT */ + +#endif /* CONFIG_AUTOSCRIPT || CFG_CMD_AUTOSCRIPT */ diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 24ff9b995..13d58cce3 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -30,10 +30,10 @@ DECLARE_GLOBAL_DATA_PTR; +#if (CONFIG_COMMANDS & CFG_CMD_BDI) static void print_num(const char *, ulong); #ifndef CONFIG_ARM /* PowerPC and other */ -static void print_lnum(const char *, u64); #ifdef CONFIG_PPC static void print_str(const char *, const char *); @@ -48,7 +48,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num ("bd address", (ulong)bd ); #endif print_num ("memstart", bd->bi_memstart ); - print_lnum ("memsize", bd->bi_memsize ); + print_num ("memsize", bd->bi_memsize ); print_num ("flashstart", bd->bi_flashstart ); print_num ("flashsize", bd->bi_flashsize ); print_num ("flashoffset", bd->bi_flashoffset ); @@ -60,18 +60,16 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif print_num ("bootflags", bd->bi_bootflags ); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_XILINX_405) || \ + defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) print_str ("procfreq", strmhz(buf, bd->bi_procfreq)); print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq)); -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_405) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq)); #endif -#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */ +#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */ #if defined(CONFIG_CPM2) print_str ("vco", strmhz(buf, bd->bi_vco)); print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq)); @@ -82,7 +80,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq)); #endif print_str ("busfreq", strmhz(buf, bd->bi_busfreq)); -#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */ +#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_ML300, CONFIG_440EP CONFIG_440GR */ #if defined(CONFIG_MPC8220) print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq)); print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq)); @@ -133,7 +131,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) bd_t *bd = gd->bd; print_num ("memstart", (ulong)bd->bi_memstart); - print_lnum ("memsize", (u64)bd->bi_memsize); + print_num ("memsize", (ulong)bd->bi_memsize); print_num ("flashstart", (ulong)bd->bi_flashstart); print_num ("flashsize", (ulong)bd->bi_flashsize); print_num ("flashoffset", (ulong)bd->bi_flashoffset); @@ -153,13 +151,11 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if defined(CONFIG_CMD_NET) int i; -#endif bd_t *bd = gd->bd; print_num ("mem start", (ulong)bd->bi_memstart); - print_lnum ("mem size", (u64)bd->bi_memsize); + print_num ("mem size", (ulong)bd->bi_memsize); print_num ("flash start", (ulong)bd->bi_flashstart); print_num ("flash size", (ulong)bd->bi_flashsize); print_num ("flash offset", (ulong)bd->bi_flashoffset); @@ -169,7 +165,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num ("sram size", (ulong)bd->bi_sramsize); #endif -#if defined(CONFIG_CMD_NET) +#if defined(CFG_CMD_NET) puts ("ethaddr ="); for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); @@ -182,167 +178,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } -#elif defined(CONFIG_MICROBLAZE) /* ! PPC, which leaves Microblaze */ - -int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i; - bd_t *bd = gd->bd; - print_num ("mem start ", (ulong)bd->bi_memstart); - print_lnum ("mem size ", (u64)bd->bi_memsize); - print_num ("flash start ", (ulong)bd->bi_flashstart); - print_num ("flash size ", (ulong)bd->bi_flashsize); - print_num ("flash offset ", (ulong)bd->bi_flashoffset); -#if defined(CFG_SRAM_BASE) - print_num ("sram start ", (ulong)bd->bi_sramstart); - print_num ("sram size ", (ulong)bd->bi_sramsize); -#endif -#if defined(CONFIG_CMD_NET) - puts ("ethaddr ="); - for (i=0; i<6; ++i) { - printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); - } - puts ("\nip_addr = "); - print_IPaddr (bd->bi_ip_addr); -#endif - printf ("\nbaudrate = %ld bps\n", (ulong)bd->bi_baudrate); - return 0; -} - -#elif defined(CONFIG_SPARC) /* SPARC */ -int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - bd_t *bd = gd->bd; -#if defined(CONFIG_CMD_NET) - int i; -#endif - -#ifdef DEBUG - print_num("bd address ", (ulong) bd); -#endif - print_num("memstart ", bd->bi_memstart); - print_lnum("memsize ", bd->bi_memsize); - print_num("flashstart ", bd->bi_flashstart); - print_num("CFG_MONITOR_BASE ", CFG_MONITOR_BASE); - print_num("CFG_ENV_ADDR ", CFG_ENV_ADDR); - printf("CFG_RELOC_MONITOR_BASE = 0x%lx (%d)\n", CFG_RELOC_MONITOR_BASE, - CFG_MONITOR_LEN); - printf("CFG_MALLOC_BASE = 0x%lx (%d)\n", CFG_MALLOC_BASE, - CFG_MALLOC_LEN); - printf("CFG_INIT_SP_OFFSET = 0x%lx (%d)\n", CFG_INIT_SP_OFFSET, - CFG_STACK_SIZE); - printf("CFG_PROM_OFFSET = 0x%lx (%d)\n", CFG_PROM_OFFSET, - CFG_PROM_SIZE); - printf("CFG_GBL_DATA_OFFSET = 0x%lx (%d)\n", CFG_GBL_DATA_OFFSET, - CFG_GBL_DATA_SIZE); - -#if defined(CONFIG_CMD_NET) - puts("ethaddr ="); - for (i = 0; i < 6; ++i) { - printf("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); - } - puts("\nIP addr = "); - print_IPaddr(bd->bi_ip_addr); -#endif - printf("\nbaudrate = %6ld bps\n", bd->bi_baudrate); - return 0; -} - -#elif defined(CONFIG_M68K) /* M68K */ -static void print_str(const char *, const char *); - -int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i; - bd_t *bd = gd->bd; - char buf[32]; - - print_num ("memstart", (ulong)bd->bi_memstart); - print_lnum ("memsize", (u64)bd->bi_memsize); - print_num ("flashstart", (ulong)bd->bi_flashstart); - print_num ("flashsize", (ulong)bd->bi_flashsize); - print_num ("flashoffset", (ulong)bd->bi_flashoffset); -#if defined(CFG_INIT_RAM_ADDR) - print_num ("sramstart", (ulong)bd->bi_sramstart); - print_num ("sramsize", (ulong)bd->bi_sramsize); -#endif -#if defined(CFG_MBAR) - print_num ("mbar", bd->bi_mbar_base); -#endif - print_str ("busfreq", strmhz(buf, bd->bi_busfreq)); -#ifdef CONFIG_PCI - print_str ("pcifreq", strmhz(buf, bd->bi_pcifreq)); -#endif -#ifdef CONFIG_EXTRA_CLOCK - print_str ("flbfreq", strmhz(buf, bd->bi_flbfreq)); - print_str ("inpfreq", strmhz(buf, bd->bi_inpfreq)); - print_str ("vcofreq", strmhz(buf, bd->bi_vcofreq)); -#endif -#if defined(CONFIG_CMD_NET) - puts ("ethaddr ="); - for (i=0; i<6; ++i) { - printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); - } - -#if defined(CONFIG_HAS_ETH1) - puts ("\neth1addr ="); - for (i=0; i<6; ++i) { - printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]); - } -#endif - -#if defined(CONFIG_HAS_ETH2) - puts ("\neth2addr ="); - for (i=0; i<6; ++i) { - printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]); - } -#endif - -#if defined(CONFIG_HAS_ETH3) - puts ("\neth3addr ="); - for (i=0; i<6; ++i) { - printf ("%c%02X", i ? ':' : ' ', bd->bi_enet3addr[i]); - } -#endif - - puts ("\nip_addr = "); - print_IPaddr (bd->bi_ip_addr); -#endif - printf ("\nbaudrate = %d bps\n", bd->bi_baudrate); - - return 0; -} - -#elif defined(CONFIG_BLACKFIN) - -int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i; - bd_t *bd = gd->bd; - - printf("U-Boot = %s\n", bd->bi_r_version); - printf("CPU = %s\n", bd->bi_cpu); - printf("Board = %s\n", bd->bi_board_name); - printf("VCO = %lu MHz\n", bd->bi_vco / 1000000); - printf("CCLK = %lu MHz\n", bd->bi_cclk / 1000000); - printf("SCLK = %lu MHz\n", bd->bi_sclk / 1000000); - - print_num("boot_params", (ulong)bd->bi_boot_params); - print_num("memstart", (ulong)bd->bi_memstart); - print_lnum("memsize", (u64)bd->bi_memsize); - print_num("flashstart", (ulong)bd->bi_flashstart); - print_num("flashsize", (ulong)bd->bi_flashsize); - print_num("flashoffset", (ulong)bd->bi_flashoffset); - - puts("ethaddr ="); - for (i = 0; i < 6; ++i) - printf("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); - puts("\nip_addr = "); - print_IPaddr(bd->bi_ip_addr); - printf("\nbaudrate = %d bps\n", bd->bi_baudrate); - - return 0; -} #else /* ! PPC, which leaves MIPS */ @@ -353,7 +188,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num ("boot_params", (ulong)bd->bi_boot_params); print_num ("memstart", (ulong)bd->bi_memstart); - print_lnum ("memsize", (u64)bd->bi_memsize); + print_num ("memsize", (ulong)bd->bi_memsize); print_num ("flashstart", (ulong)bd->bi_flashstart); print_num ("flashsize", (ulong)bd->bi_flashsize); print_num ("flashoffset", (ulong)bd->bi_flashoffset); @@ -378,6 +213,9 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) bd_t *bd = gd->bd; print_num ("arch_number", bd->bi_arch_number); +#ifdef CONFIG_BOARD_REVISION + print_num ("board rev", bd->bi_board_revision); +#endif print_num ("env_t", (ulong)bd->bi_env); print_num ("boot_params", (ulong)bd->bi_boot_params); @@ -387,7 +225,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) print_num("-> size", bd->bi_dram[i].size); } -#if defined(CONFIG_CMD_NET) puts ("ethaddr ="); for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); @@ -395,7 +232,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ( "\n" "ip_addr = "); print_IPaddr (bd->bi_ip_addr); -#endif printf ("\n" "baudrate = %d bps\n", bd->bi_baudrate); @@ -409,14 +245,7 @@ static void print_num(const char *name, ulong value) printf ("%-12s= 0x%08lX\n", name, value); } -#ifndef CONFIG_ARM -static void print_lnum(const char *name, u64 value) -{ - printf ("%-12s= 0x%.8llX\n", name, value); -} -#endif - -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) +#ifdef CONFIG_PPC static void print_str(const char *name, const char *str) { printf ("%-12s= %6s MHz\n", name, str); @@ -431,3 +260,4 @@ U_BOOT_CMD( "bdinfo - print Board Info structure\n", NULL ); +#endif /* CFG_CMD_BDI */ diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c index 94f7e0847..48086a628 100644 --- a/common/cmd_bedbug.c +++ b/common/cmd_bedbug.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + #ifndef MAX #define MAX(a,b) ((a) > (b) ? (a) : (b)) #endif @@ -411,6 +413,7 @@ int do_bedbug_rdump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD (rdump, 1, 1, do_bedbug_rdump, "rdump - Show registers.\n", " - Show registers.\n"); /* ====================================================================== */ +#endif /* CFG_CMD_BEDBUG */ /* diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index 197e5e871..ad412c81e 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -31,67 +31,13 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_BMP) + static int bmp_info (ulong addr); static int bmp_display (ulong addr, int x, int y); int gunzip(void *, int, unsigned char *, unsigned long *); -/* - * Allocate and decompress a BMP image using gunzip(). - * - * Returns a pointer to the decompressed image data. Must be freed by - * the caller after use. - * - * Returns NULL if decompression failed, or if the decompressed data - * didn't contain a valid BMP signature. - */ -#ifdef CONFIG_VIDEO_BMP_GZIP -static bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) -{ - void *dst; - unsigned long len; - bmp_image_t *bmp; - - /* - * Decompress bmp image - */ - len = CFG_VIDEO_LOGO_MAX_SIZE; - dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); - if (dst == NULL) { - puts("Error: malloc in gunzip failed!\n"); - return NULL; - } - if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) { - free(dst); - return NULL; - } - if (len == CFG_VIDEO_LOGO_MAX_SIZE) - puts("Image could be truncated" - " (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); - - bmp = dst; - - /* - * Check for bmp mark 'BM' - */ - if (!((bmp->header.signature[0] == 'B') && - (bmp->header.signature[1] == 'M'))) { - free(dst); - return NULL; - } - - puts("Gzipped BMP image detected!\n"); - - return bmp; -} -#else -static bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) -{ - return NULL; -} -#endif - - /* * Subroutine: do_bmp * @@ -157,24 +103,63 @@ U_BOOT_CMD( static int bmp_info(ulong addr) { bmp_image_t *bmp=(bmp_image_t *)addr; - unsigned long len; +#ifdef CONFIG_VIDEO_BMP_GZIP + unsigned char *dst = NULL; + ulong len; +#endif /* CONFIG_VIDEO_BMP_GZIP */ if (!((bmp->header.signature[0]=='B') && - (bmp->header.signature[1]=='M'))) - bmp = gunzip_bmp(addr, &len); + (bmp->header.signature[1]=='M'))) { - if (bmp == NULL) { +#ifdef CONFIG_VIDEO_BMP_GZIP + /* + * Decompress bmp image + */ + len = CFG_VIDEO_LOGO_MAX_SIZE; + dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); + if (dst == NULL) { + printf("Error: malloc in gunzip failed!\n"); + return(1); + } + if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) { + printf("There is no valid bmp file at the given address\n"); + return(1); + } + if (len == CFG_VIDEO_LOGO_MAX_SIZE) { + printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); + } + + /* + * Set addr to decompressed image + */ + bmp = (bmp_image_t *)dst; + + /* + * Check for bmp mark 'BM' + */ + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + printf("There is no valid bmp file at the given address\n"); + free(dst); + return(1); + } + + printf("Gzipped BMP image detected!\n"); +#else /* CONFIG_VIDEO_BMP_GZIP */ printf("There is no valid bmp file at the given address\n"); - return 1; + return(1); +#endif /* CONFIG_VIDEO_BMP_GZIP */ } - printf("Image size : %d x %d\n", le32_to_cpu(bmp->header.width), le32_to_cpu(bmp->header.height)); printf("Bits per pixel: %d\n", le16_to_cpu(bmp->header.bit_count)); printf("Compression : %d\n", le32_to_cpu(bmp->header.compression)); - if ((unsigned long)bmp != addr) - free(bmp); +#ifdef CONFIG_VIDEO_BMP_GZIP + if (dst) { + free(dst); + } +#endif /* CONFIG_VIDEO_BMP_GZIP */ return(0); } @@ -191,33 +176,16 @@ static int bmp_info(ulong addr) */ static int bmp_display(ulong addr, int x, int y) { - int ret; - bmp_image_t *bmp = (bmp_image_t *)addr; - unsigned long len; - - if (!((bmp->header.signature[0]=='B') && - (bmp->header.signature[1]=='M'))) - bmp = gunzip_bmp(addr, &len); - - if (!bmp) { - printf("There is no valid bmp file at the given address\n"); - return 1; - } - #if defined(CONFIG_LCD) extern int lcd_display_bitmap (ulong, int, int); - ret = lcd_display_bitmap ((unsigned long)bmp, x, y); + return (lcd_display_bitmap (addr, x, y)); #elif defined(CONFIG_VIDEO) extern int video_display_bitmap (ulong, int, int); - - ret = video_display_bitmap ((unsigned long)bmp, x, y); + return (video_display_bitmap (addr, x, y)); #else # error bmp_display() requires CONFIG_LCD or CONFIG_VIDEO #endif - - if ((unsigned long)bmp != addr) - free(bmp); - - return ret; } + +#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) */ diff --git a/common/cmd_boot.c b/common/cmd_boot.c index d83f5af53..e68f16f9d 100644 --- a/common/cmd_boot.c +++ b/common/cmd_boot.c @@ -28,12 +28,9 @@ #include #include -/* Allow ports to override the default behavior */ -__attribute__((weak)) -unsigned long do_go_exec (ulong (*entry)(int, char *[]), int argc, char *argv[]) -{ - return entry (argc, argv); -} +#if defined(CONFIG_I386) +DECLARE_GLOBAL_DATA_PTR; +#endif int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -53,7 +50,21 @@ int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * pass address parameter as argv[0] (aka command name), * and all remaining args */ - rc = do_go_exec ((void *)addr, argc - 1, argv + 1); +#if defined(CONFIG_I386) + /* + * x86 does not use a dedicated register to pass the pointer + * to the global_data + */ + argv[0] = (char *)gd; +#endif +#if !defined(CONFIG_NIOS) + rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]); +#else + /* + * Nios function pointers are address >> 1 + */ + rc = ((ulong (*)(int, char *[]))(addr>>1)) (--argc, &argv[1]); +#endif if (rc != 0) rcode = 1; printf ("## Application terminated, rc = 0x%lX\n", rc); diff --git a/common/cmd_bootconf.c b/common/cmd_bootconf.c new file mode 100644 index 000000000..2ea77b881 --- /dev/null +++ b/common/cmd_bootconf.c @@ -0,0 +1,122 @@ +/* + * Bootloader configuration file parser + * + * Copyright (C) 2010 TomTom International B.V. + * Author: Martin Jackson + * + ************************************************************************ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + ************************************************************************ + */ + +/* #define DEBUG */ + +#include +#include +#include + +#if defined(CONFIG_CMD_BOOTCONF) + +#define FLAG(f, v, s, u) { \ + .flag = f, \ + .var = v, \ + .setval = s, \ + .unsetval = u, \ +} +#define FLAG_YESNO(f, v) FLAG(f, v, "yes", "no") + +struct { + char flag; + char *var; + char *setval; + char *unsetval; +} +bootconf_flags[] = { + FLAG_YESNO('M', "run_memorytest"), + FLAG('R', "force_altboot", "yes", NULL), + FLAG('S', "sysboot_mode", "warm", NULL), + FLAG_YESNO('W', "disable_watchdog"), + FLAG_YESNO('E', "exec_applet"), + FLAG_YESNO('Y', "no_trybooty"), + FLAG('F', "force_flasher_mode","flasher", ""), +}; +#define BC_I bootconf_flags[i] + +int do_bootconf (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char *addr = NULL; + int i; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return -1; + } + + if ((addr = (char *) simple_strtoul(argv[1], NULL, 16)) == NULL) { + eprintf("Address is NULL\n"); + goto unset_all; + return -1; + } + + /* Might also be that uboot.conf couldn't be loaded here */ + if (addr[0] != '-') { + printf("'uboot.conf' ignored\n"); + goto unset_all; + } + + for(i=0; i\n" + " - Parse configuration at 'addr'\n" +); + +#endif /* CONFIG_CMD_BOOTCONF */ + diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 529596926..8dfa337ae 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2006 + * (C) Copyright 2000-2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -21,7 +21,6 @@ * MA 02111-1307 USA */ - /* * Boot support */ @@ -33,51 +32,68 @@ #include #include #include -#include #include -#if defined(CONFIG_CMD_USB) -#include + /*cmd_boot.c*/ + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) +#include #endif #ifdef CFG_HUSH_PARSER #include #endif -DECLARE_GLOBAL_DATA_PTR; - -extern int gunzip (void *dst, int dstlen, unsigned char *src, unsigned long *lenp); -#ifndef CFG_BOOTM_LEN -#define CFG_BOOTM_LEN 0x800000 /* use 8MByte as default max gunzip size */ +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) #endif -#ifdef CONFIG_BZIP2 -extern void bz_internal_error(int); +#ifdef CFG_INIT_RAM_LOCK +#include #endif -#if defined(CONFIG_CMD_IMI) +#ifdef CONFIG_LOGBUFFER +#include +#endif + +#ifdef CONFIG_HAS_DATAFLASH +#include +#endif + +/* + * Some systems (for example LWMON) have very short watchdog periods; + * we must make sure to split long operations like memmove() or + * crc32() into reasonable chunks. + */ +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +# define CHUNKSZ (64 * 1024) +#endif + +int gunzip (void *, int, unsigned char *, unsigned long *); + +static void *zalloc(void *, unsigned, unsigned); +static void zfree(void *, void *, unsigned); + +#if (CONFIG_COMMANDS & CFG_CMD_IMI) static int image_info (unsigned long addr); #endif -#if defined(CONFIG_CMD_IMLS) +#if (CONFIG_COMMANDS & CFG_CMD_IMLS) #include -extern flash_info_t flash_info[]; /* info for FLASH chips */ +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #endif -#ifdef CONFIG_SILENT_CONSOLE -static void fixup_silent_linux (void); -#endif +static void print_type (image_header_t *hdr); -static image_header_t *image_get_kernel (ulong img_addr, int verify); -#if defined(CONFIG_FIT) -static int fit_check_kernel (const void *fit, int os_noffset, int verify); +#ifdef __I386__ +image_header_t *fake_header(image_header_t *hdr, void *ptr, int size); #endif -static void *boot_get_kernel (cmd_tbl_t *cmdtp, int flag,int argc, char *argv[], - bootm_headers_t *images, ulong *os_data, ulong *os_len); -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); - /* * Continue booting an OS image; caller already has: * - copied image header to global variable `header' @@ -86,150 +102,198 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); * - loaded (first part of) image to header load address, * - disabled interrupts. */ -typedef void boot_os_fn (cmd_tbl_t *cmdtp, int flag, - int argc, char *argv[], - bootm_headers_t *images); /* pointers to os/initrd/fdt */ +typedef void boot_os_Fcn (cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[], + ulong addr, /* of image to boot */ + ulong *len_ptr, /* multi-file image length table */ + int verify); /* getenv("verify")[0] != 'n' */ -extern boot_os_fn do_bootm_linux; -static boot_os_fn do_bootm_netbsd; -#if defined(CONFIG_LYNXKDI) -static boot_os_fn do_bootm_lynxkdi; -extern void lynxkdi_boot (image_header_t *); +#ifdef DEBUG +extern int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #endif -static boot_os_fn do_bootm_rtems; -#if defined(CONFIG_CMD_ELF) -static boot_os_fn do_bootm_vxworks; -static boot_os_fn do_bootm_qnxelf; -int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +#ifdef CONFIG_PPC +static boot_os_Fcn do_bootm_linux; +#else +extern boot_os_Fcn do_bootm_linux; #endif +#ifdef CONFIG_SILENT_CONSOLE +static void fixup_silent_linux (void); +#endif +static boot_os_Fcn do_bootm_netbsd; +static boot_os_Fcn do_bootm_rtems; +#if (CONFIG_COMMANDS & CFG_CMD_ELF) +static boot_os_Fcn do_bootm_vxworks; +static boot_os_Fcn do_bootm_qnxelf; +int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ); +int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ); +#endif /* CFG_CMD_ELF */ #if defined(CONFIG_ARTOS) && defined(CONFIG_PPC) -static boot_os_fn do_bootm_artos; +static boot_os_Fcn do_bootm_artos; +#endif +#ifdef CONFIG_LYNXKDI +static boot_os_Fcn do_bootm_lynxkdi; +extern void lynxkdi_boot( image_header_t * ); #endif ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */ -static bootm_headers_t images; /* pointers to os/initrd/fdt images */ +ulong load_size = 0; -void __board_lmb_reserve(struct lmb *lmb) -{ - /* please define platform specific board_lmb_reserve() */ -} -void board_lmb_reserve(struct lmb *lmb) __attribute__((weak, alias("__board_lmb_reserve"))); +image_header_t header; +#ifndef CFG_BOOTM_LEN +#define CFG_BOOTM_LEN 0x800000 /* use 8MByte as default max gunzip size */ +#endif -/*******************************************************************/ -/* bootm - boot application image from image in memory */ -/*******************************************************************/ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong iflag; - const char *type_name; - uint unc_len = CFG_BOOTM_LEN; - uint8_t comp, type, os; + ulong iflag; + ulong addr; + ulong data, len, checksum; + ulong *len_ptr; + uint unc_len = CFG_BOOTM_LEN; + int i, verify; + char *name, *s; + int (*appl)(int, char *[]); + image_header_t *hdr = &header; - void *os_hdr; - ulong os_data, os_len; - ulong image_start, image_end; - ulong load_start, load_end; - ulong mem_start; - phys_size_t mem_size; + s = getenv ("verify"); + verify = (s && (*s == 'n')) ? 0 : 1; - struct lmb lmb; - - memset ((void *)&images, 0, sizeof (images)); - images.verify = getenv_yesno ("verify"); - images.lmb = &lmb; - - lmb_init(&lmb); - - mem_start = getenv_bootm_low(); - mem_size = getenv_bootm_size(); - - lmb_add(&lmb, (phys_addr_t)mem_start, mem_size); - - board_lmb_reserve(&lmb); - - /* get kernel image header, start address and length */ - os_hdr = boot_get_kernel (cmdtp, flag, argc, argv, - &images, &os_data, &os_len); - if (os_len == 0) { - puts ("ERROR: can't get kernel image!\n"); - return 1; + if (argc < 2) { + addr = load_addr; + } else { + addr = simple_strtoul(argv[1], NULL, 16); } - /* get image parameters */ - switch (genimg_get_format (os_hdr)) { - case IMAGE_FORMAT_LEGACY: - type = image_get_type (os_hdr); - comp = image_get_comp (os_hdr); - os = image_get_os (os_hdr); + SHOW_BOOT_PROGRESS (1); + printf ("## Booting image at %08lx ...\n", addr); - image_end = image_get_image_end (os_hdr); - load_start = image_get_load (os_hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - if (fit_image_get_type (images.fit_hdr_os, - images.fit_noffset_os, &type)) { - puts ("Can't get image type!\n"); - show_boot_progress (-109); - return 1; - } - - if (fit_image_get_comp (images.fit_hdr_os, - images.fit_noffset_os, &comp)) { - puts ("Can't get image compression!\n"); - show_boot_progress (-110); - return 1; - } - - if (fit_image_get_os (images.fit_hdr_os, - images.fit_noffset_os, &os)) { - puts ("Can't get image OS!\n"); - show_boot_progress (-111); - return 1; - } - - image_end = fit_get_end (images.fit_hdr_os); - - if (fit_image_get_load (images.fit_hdr_os, images.fit_noffset_os, - &load_start)) { - puts ("Can't get image load address!\n"); - show_boot_progress (-112); - return 1; - } - break; + /* Copy header so we can blank CRC field for re-calculation */ +#ifdef CONFIG_HAS_DATAFLASH + if (addr_dataflash(addr)){ + read_dataflash(addr, sizeof(image_header_t), (char *)&header); + } else #endif - default: - puts ("ERROR: unknown image format type!\n"); + memmove (&header, (char *)addr, sizeof(image_header_t)); + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { +#ifdef __I386__ /* correct image format not implemented yet - fake it */ + if (fake_header(hdr, (void*)addr, -1) != NULL) { + /* to compensate for the addition below */ + addr -= sizeof(image_header_t); + /* turnof verify, + * fake_header() does not fake the data crc + */ + verify = 0; + } else +#endif /* __I386__ */ + { + puts ("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + } + SHOW_BOOT_PROGRESS (2); + + data = (ulong)&header; + len = sizeof(image_header_t); + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (unsigned char *)data, len) != checksum) { + puts ("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS (-2); return 1; } + SHOW_BOOT_PROGRESS (3); - image_start = (ulong)os_hdr; - load_end = 0; - type_name = genimg_get_type_name (type); + /* for multi-file images we need the data part, too */ + print_image_hdr ((image_header_t *)addr); + + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + +#ifdef CONFIG_HAS_DATAFLASH + if (addr_dataflash(addr)){ + read_dataflash(data, len, (char *)CFG_LOAD_ADDR); + data = CFG_LOAD_ADDR; + } +#endif + + if (verify) { + puts (" Verifying Checksum ... "); + if (crc32 (0, (unsigned char *)data, len) != ntohl(hdr->ih_dcrc)) { + printf ("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS (-3); + return 1; + } + puts ("OK\n"); + } + SHOW_BOOT_PROGRESS (4); + + len_ptr = (ulong *)data; + +#if defined(__PPC__) + if (hdr->ih_arch != IH_CPU_PPC) +#elif defined(__ARM__) + if (hdr->ih_arch != IH_CPU_ARM) +#elif defined(__I386__) + if (hdr->ih_arch != IH_CPU_I386) +#elif defined(__mips__) + if (hdr->ih_arch != IH_CPU_MIPS) +#elif defined(__nios__) + if (hdr->ih_arch != IH_CPU_NIOS) +#elif defined(__M68K__) + if (hdr->ih_arch != IH_CPU_M68K) +#elif defined(__microblaze__) + if (hdr->ih_arch != IH_CPU_MICROBLAZE) +#elif defined(__nios2__) + if (hdr->ih_arch != IH_CPU_NIOS2) +#else +# error Unknown CPU type +#endif + { + printf ("Unsupported Architecture 0x%x\n", hdr->ih_arch); + SHOW_BOOT_PROGRESS (-4); + return 1; + } + SHOW_BOOT_PROGRESS (5); + + switch (hdr->ih_type) { + case IH_TYPE_STANDALONE: + name = "Standalone Application"; + /* A second argument overwrites the load address */ + if (argc > 2) { + hdr->ih_load = simple_strtoul(argv[2], NULL, 16); + } + break; + case IH_TYPE_KERNEL: + name = "Kernel Image"; + break; + case IH_TYPE_MULTI: + name = "Multi-File Image"; + len = ntohl(len_ptr[0]); + /* OS kernel is always the first image */ + data += 8; /* kernel_len + terminator */ + for (i=1; len_ptr[i]; ++i) + data += 4; + break; + default: printf ("Wrong Image Type for %s command\n", cmdtp->name); + SHOW_BOOT_PROGRESS (-5); + return 1; + } + SHOW_BOOT_PROGRESS (6); /* * We have reached the point of no return: we are going to * overwrite all exception vector code, so we cannot easily * recover from any failures any more... */ + iflag = disable_interrupts(); -#if defined(CONFIG_CMD_USB) - /* - * turn off USB to prevent the host controller from writing to the - * SDRAM while Linux is booting. This could happen (at least for OHCI - * controller), because the HCCA (Host Controller Communication Area) - * lies within the SDRAM and the host controller writes continously to - * this area (as busmaster!). The HccaFrameNumber is for example - * updated every 1 ms within the HCCA structure in SDRAM! For more - * details see the OpenHCI specification. - */ - usb_stop(); -#endif - - #ifdef CONFIG_AMIGAONEG3SE /* * We've possible left the caches enabled during @@ -241,610 +305,164 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) dcache_disable(); #endif - switch (comp) { + switch (hdr->ih_comp) { case IH_COMP_NONE: - if (load_start == (ulong)os_hdr) { - printf (" XIP %s ... ", type_name); + if(ntohl(hdr->ih_load) == addr) { + printf (" XIP %s ... ", name); } else { - printf (" Loading %s ... ", type_name); +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + size_t l = len; + void *to = (void *)ntohl(hdr->ih_load); + void *from = (void *)data; - memmove_wd ((void *)load_start, - (void *)os_data, os_len, CHUNKSZ); + printf (" Loading %s ... ", name); + + while (l > 0) { + size_t tail = (l > CHUNKSZ) ? CHUNKSZ : l; + WATCHDOG_RESET(); + memmove (to, from, tail); + to += tail; + from += tail; + l -= tail; + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + memmove ((void *) ntohl(hdr->ih_load), (uchar *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ } - load_end = load_start + os_len; - puts("OK\n"); break; case IH_COMP_GZIP: - printf (" Uncompressing %s ... ", type_name); - if (gunzip ((void *)load_start, unc_len, - (uchar *)os_data, &os_len) != 0) { - puts ("GUNZIP: uncompress or overwrite error " - "- must RESET board to recover\n"); - show_boot_progress (-6); + printf (" Uncompressing %s ... ", name); + if (gunzip ((void *)ntohl(hdr->ih_load), unc_len, + (uchar *)data, &len) != 0) { + puts ("GUNZIP ERROR - must RESET board to recover\n"); + SHOW_BOOT_PROGRESS (-6); do_reset (cmdtp, flag, argc, argv); } - - load_end = load_start + os_len; break; #ifdef CONFIG_BZIP2 case IH_COMP_BZIP2: - printf (" Uncompressing %s ... ", type_name); + printf (" Uncompressing %s ... ", name); /* * If we've got less than 4 MB of malloc() space, * use slower decompression algorithm which requires * at most 2300 KB of memory. */ - int i = BZ2_bzBuffToBuffDecompress ((char*)load_start, - &unc_len, (char *)os_data, os_len, - CFG_MALLOC_LEN < (4096 * 1024), 0); + i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load), + &unc_len, (char *)data, len, + CFG_MALLOC_LEN < (4096 * 1024), 0); if (i != BZ_OK) { - printf ("BUNZIP2: uncompress or overwrite error %d " - "- must RESET board to recover\n", i); - show_boot_progress (-6); + printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i); + SHOW_BOOT_PROGRESS (-6); + udelay(100000); do_reset (cmdtp, flag, argc, argv); } - - load_end = load_start + unc_len; break; #endif /* CONFIG_BZIP2 */ default: if (iflag) enable_interrupts(); - printf ("Unimplemented compression type %d\n", comp); - show_boot_progress (-7); + printf ("Unimplemented compression type %d\n", hdr->ih_comp); + SHOW_BOOT_PROGRESS (-7); return 1; } puts ("OK\n"); - debug (" kernel loaded at 0x%08lx, end = 0x%08lx\n", load_start, load_end); - show_boot_progress (7); + SHOW_BOOT_PROGRESS (7); - if ((load_start < image_end) && (load_end > image_start)) { - debug ("image_start = 0x%lX, image_end = 0x%lx\n", image_start, image_end); - debug ("load_start = 0x%lx, load_end = 0x%lx\n", load_start, load_end); + switch (hdr->ih_type) { + case IH_TYPE_STANDALONE: + if (iflag) + enable_interrupts(); - if (images.legacy_hdr_valid) { - if (image_get_type (&images.legacy_hdr_os_copy) == IH_TYPE_MULTI) - puts ("WARNING: legacy format multi component " - "image overwritten\n"); - } else { - puts ("ERROR: new format image overwritten - " - "must RESET the board to recover\n"); - show_boot_progress (-113); - do_reset (cmdtp, flag, argc, argv); + /* load (and uncompress), but don't start if "autostart" + * is set to "no" + */ + if (((s = getenv("autostart")) != NULL) && (strcmp(s,"no") == 0)) { + char buf[32]; + sprintf(buf, "%lX", len); + setenv("filesize", buf); + return 0; } + appl = (int (*)(int, char *[]))ntohl(hdr->ih_ep); + (*appl)(argc-1, &argv[1]); + return 0; + case IH_TYPE_KERNEL: + case IH_TYPE_MULTI: + /* handled below */ + break; + default: + if (iflag) + enable_interrupts(); + printf ("Can't boot image type %d\n", hdr->ih_type); + SHOW_BOOT_PROGRESS (-8); + return 1; } + SHOW_BOOT_PROGRESS (8); - show_boot_progress (8); - - lmb_reserve(&lmb, load_start, (load_end - load_start)); - - switch (os) { + switch (hdr->ih_os) { default: /* handled by (original) Linux case */ case IH_OS_LINUX: #ifdef CONFIG_SILENT_CONSOLE fixup_silent_linux(); #endif - do_bootm_linux (cmdtp, flag, argc, argv, &images); + do_bootm_linux (cmdtp, flag, argc, argv, + addr, len_ptr, verify); break; - case IH_OS_NETBSD: - do_bootm_netbsd (cmdtp, flag, argc, argv, &images); + do_bootm_netbsd (cmdtp, flag, argc, argv, + addr, len_ptr, verify); break; #ifdef CONFIG_LYNXKDI case IH_OS_LYNXOS: - do_bootm_lynxkdi (cmdtp, flag, argc, argv, &images); + do_bootm_lynxkdi (cmdtp, flag, argc, argv, + addr, len_ptr, verify); break; #endif case IH_OS_RTEMS: - do_bootm_rtems (cmdtp, flag, argc, argv, &images); + do_bootm_rtems (cmdtp, flag, argc, argv, + addr, len_ptr, verify); break; -#if defined(CONFIG_CMD_ELF) +#if (CONFIG_COMMANDS & CFG_CMD_ELF) case IH_OS_VXWORKS: - do_bootm_vxworks (cmdtp, flag, argc, argv, &images); + do_bootm_vxworks (cmdtp, flag, argc, argv, + addr, len_ptr, verify); break; - case IH_OS_QNX: - do_bootm_qnxelf (cmdtp, flag, argc, argv, &images); + do_bootm_qnxelf (cmdtp, flag, argc, argv, + addr, len_ptr, verify); break; -#endif - +#endif /* CFG_CMD_ELF */ #ifdef CONFIG_ARTOS case IH_OS_ARTOS: - do_bootm_artos (cmdtp, flag, argc, argv, &images); + do_bootm_artos (cmdtp, flag, argc, argv, + addr, len_ptr, verify); break; #endif } - show_boot_progress (-9); + SHOW_BOOT_PROGRESS (-9); #ifdef DEBUG puts ("\n## Control returned to monitor - resetting...\n"); do_reset (cmdtp, flag, argc, argv); #endif - if (iflag) - enable_interrupts(); - - return 1; -} - -/** - * image_get_kernel - verify legacy format kernel image - * @img_addr: in RAM address of the legacy format image to be verified - * @verify: data CRC verification flag - * - * image_get_kernel() verifies legacy image integrity and returns pointer to - * legacy image header if image verification was completed successfully. - * - * returns: - * pointer to a legacy image header if valid image was found - * otherwise return NULL - */ -static image_header_t *image_get_kernel (ulong img_addr, int verify) -{ - image_header_t *hdr = (image_header_t *)img_addr; - - if (!image_check_magic(hdr)) { - puts ("Bad Magic Number\n"); - show_boot_progress (-1); - return NULL; - } - show_boot_progress (2); - - if (!image_check_hcrc (hdr)) { - puts ("Bad Header Checksum\n"); - show_boot_progress (-2); - return NULL; - } - - show_boot_progress (3); - image_print_contents (hdr); - - if (verify) { - puts (" Verifying Checksum ... "); - if (!image_check_dcrc (hdr)) { - printf ("Bad Data CRC\n"); - show_boot_progress (-3); - return NULL; - } - puts ("OK\n"); - } - show_boot_progress (4); - - if (!image_check_target_arch (hdr)) { - printf ("Unsupported Architecture 0x%x\n", image_get_arch (hdr)); - show_boot_progress (-4); - return NULL; - } - return hdr; -} - -/** - * fit_check_kernel - verify FIT format kernel subimage - * @fit_hdr: pointer to the FIT image header - * os_noffset: kernel subimage node offset within FIT image - * @verify: data CRC verification flag - * - * fit_check_kernel() verifies integrity of the kernel subimage and from - * specified FIT image. - * - * returns: - * 1, on success - * 0, on failure - */ -#if defined (CONFIG_FIT) -static int fit_check_kernel (const void *fit, int os_noffset, int verify) -{ - fit_image_print (fit, os_noffset, " "); - - if (verify) { - puts (" Verifying Hash Integrity ... "); - if (!fit_image_check_hashes (fit, os_noffset)) { - puts ("Bad Data Hash\n"); - show_boot_progress (-104); - return 0; - } - puts ("OK\n"); - } - show_boot_progress (105); - - if (!fit_image_check_target_arch (fit, os_noffset)) { - puts ("Unsupported Architecture\n"); - show_boot_progress (-105); - return 0; - } - - show_boot_progress (106); - if (!fit_image_check_type (fit, os_noffset, IH_TYPE_KERNEL)) { - puts ("Not a kernel image\n"); - show_boot_progress (-106); - return 0; - } - - show_boot_progress (107); - return 1; -} -#endif /* CONFIG_FIT */ - -/** - * boot_get_kernel - find kernel image - * @os_data: pointer to a ulong variable, will hold os data start address - * @os_len: pointer to a ulong variable, will hold os data length - * - * boot_get_kernel() tries to find a kernel image, verifies its integrity - * and locates kernel data. - * - * returns: - * pointer to image header if valid image was found, plus kernel start - * address and length, otherwise NULL - */ -static void *boot_get_kernel (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], - bootm_headers_t *images, ulong *os_data, ulong *os_len) -{ - image_header_t *hdr; - ulong img_addr; -#if defined(CONFIG_FIT) - void *fit_hdr; - const char *fit_uname_config = NULL; - const char *fit_uname_kernel = NULL; - const void *data; - size_t len; - int cfg_noffset; - int os_noffset; -#endif - - /* find out kernel image address */ - if (argc < 2) { - img_addr = load_addr; - debug ("* kernel: default image load address = 0x%08lx\n", - load_addr); -#if defined(CONFIG_FIT) - } else if (fit_parse_conf (argv[1], load_addr, &img_addr, - &fit_uname_config)) { - debug ("* kernel: config '%s' from image at 0x%08lx\n", - fit_uname_config, img_addr); - } else if (fit_parse_subimage (argv[1], load_addr, &img_addr, - &fit_uname_kernel)) { - debug ("* kernel: subimage '%s' from image at 0x%08lx\n", - fit_uname_kernel, img_addr); -#endif - } else { - img_addr = simple_strtoul(argv[1], NULL, 16); - debug ("* kernel: cmdline image address = 0x%08lx\n", img_addr); - } - - show_boot_progress (1); - - /* copy from dataflash if needed */ - img_addr = genimg_get_image (img_addr); - - /* check image type, for FIT images get FIT kernel node */ - *os_data = *os_len = 0; - switch (genimg_get_format ((void *)img_addr)) { - case IMAGE_FORMAT_LEGACY: - printf ("## Booting kernel from Legacy Image at %08lx ...\n", - img_addr); - hdr = image_get_kernel (img_addr, images->verify); - if (!hdr) - return NULL; - show_boot_progress (5); - - /* get os_data and os_len */ - switch (image_get_type (hdr)) { - case IH_TYPE_KERNEL: - *os_data = image_get_data (hdr); - *os_len = image_get_data_size (hdr); - break; - case IH_TYPE_MULTI: - image_multi_getimg (hdr, 0, os_data, os_len); - break; - default: - printf ("Wrong Image Type for %s command\n", cmdtp->name); - show_boot_progress (-5); - return NULL; - } - - /* - * copy image header to allow for image overwrites during kernel - * decompression. - */ - memmove (&images->legacy_hdr_os_copy, hdr, sizeof(image_header_t)); - - /* save pointer to image header */ - images->legacy_hdr_os = hdr; - - images->legacy_hdr_valid = 1; - show_boot_progress (6); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (void *)img_addr; - printf ("## Booting kernel from FIT Image at %08lx ...\n", - img_addr); - - if (!fit_check_format (fit_hdr)) { - puts ("Bad FIT kernel image format!\n"); - show_boot_progress (-100); - return NULL; - } - show_boot_progress (100); - - if (!fit_uname_kernel) { - /* - * no kernel image node unit name, try to get config - * node first. If config unit node name is NULL - * fit_conf_get_node() will try to find default config node - */ - show_boot_progress (101); - cfg_noffset = fit_conf_get_node (fit_hdr, fit_uname_config); - if (cfg_noffset < 0) { - show_boot_progress (-101); - return NULL; - } - /* save configuration uname provided in the first - * bootm argument - */ - images->fit_uname_cfg = fdt_get_name (fit_hdr, cfg_noffset, NULL); - printf (" Using '%s' configuration\n", images->fit_uname_cfg); - show_boot_progress (103); - - os_noffset = fit_conf_get_kernel_node (fit_hdr, cfg_noffset); - fit_uname_kernel = fit_get_name (fit_hdr, os_noffset, NULL); - } else { - /* get kernel component image node offset */ - show_boot_progress (102); - os_noffset = fit_image_get_node (fit_hdr, fit_uname_kernel); - } - if (os_noffset < 0) { - show_boot_progress (-103); - return NULL; - } - - printf (" Trying '%s' kernel subimage\n", fit_uname_kernel); - - show_boot_progress (104); - if (!fit_check_kernel (fit_hdr, os_noffset, images->verify)) - return NULL; - - /* get kernel image data address and length */ - if (fit_image_get_data (fit_hdr, os_noffset, &data, &len)) { - puts ("Could not find kernel subimage data!\n"); - show_boot_progress (-107); - return NULL; - } - show_boot_progress (108); - - *os_len = len; - *os_data = (ulong)data; - images->fit_hdr_os = fit_hdr; - images->fit_uname_os = fit_uname_kernel; - images->fit_noffset_os = os_noffset; - break; -#endif - default: - printf ("Wrong Image Format for %s command\n", cmdtp->name); - show_boot_progress (-108); - return NULL; - } - - debug (" kernel data at 0x%08lx, len = 0x%08lx (%ld)\n", - *os_data, *os_len, *os_len); - - return (void *)img_addr; -} - -U_BOOT_CMD( - bootm, CFG_MAXARGS, 1, do_bootm, - "bootm - boot application image from memory\n", - "[addr [arg ...]]\n - boot application image stored in memory\n" - "\tpassing arguments 'arg ...'; when booting a Linux kernel,\n" - "\t'arg' can be the address of an initrd image\n" -#if defined(CONFIG_OF_LIBFDT) - "\tWhen booting a Linux kernel which requires a flat device-tree\n" - "\ta third argument is required which is the address of the\n" - "\tdevice-tree blob. To boot that kernel without an initrd image,\n" - "\tuse a '-' for the second argument. If you do not pass a third\n" - "\ta bd_info struct will be passed instead\n" -#endif -#if defined(CONFIG_FIT) - "\t\nFor the new multi component uImage format (FIT) addresses\n" - "\tmust be extened to include component or configuration unit name:\n" - "\taddr: - direct component image specification\n" - "\taddr# - configuration specification\n" - "\tUse iminfo command to get the list of existing component\n" - "\timages and configurations.\n" -#endif -); - -/*******************************************************************/ -/* bootd - boot default image */ -/*******************************************************************/ -#if defined(CONFIG_CMD_BOOTD) -int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int rcode = 0; - -#ifndef CFG_HUSH_PARSER - if (run_command (getenv ("bootcmd"), flag) < 0) - rcode = 1; -#else - if (parse_string_outer (getenv ("bootcmd"), - FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) != 0) - rcode = 1; -#endif - return rcode; -} - -U_BOOT_CMD( - boot, 1, 1, do_bootd, - "boot - boot default, i.e., run 'bootcmd'\n", - NULL -); - -/* keep old command name "bootd" for backward compatibility */ -U_BOOT_CMD( - bootd, 1, 1, do_bootd, - "bootd - boot default, i.e., run 'bootcmd'\n", - NULL -); - -#endif - - -/*******************************************************************/ -/* iminfo - print header info for a requested image */ -/*******************************************************************/ -#if defined(CONFIG_CMD_IMI) -int do_iminfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int arg; - ulong addr; - int rcode = 0; - - if (argc < 2) { - return image_info (load_addr); - } - - for (arg = 1; arg < argc; ++arg) { - addr = simple_strtoul (argv[arg], NULL, 16); - if (image_info (addr) != 0) - rcode = 1; - } - return rcode; -} - -static int image_info (ulong addr) -{ - void *hdr = (void *)addr; - - printf ("\n## Checking Image at %08lx ...\n", addr); - - switch (genimg_get_format (hdr)) { - case IMAGE_FORMAT_LEGACY: - puts (" Legacy image found\n"); - if (!image_check_magic (hdr)) { - puts (" Bad Magic Number\n"); - return 1; - } - - if (!image_check_hcrc (hdr)) { - puts (" Bad Header Checksum\n"); - return 1; - } - - image_print_contents (hdr); - - puts (" Verifying Checksum ... "); - if (!image_check_dcrc (hdr)) { - puts (" Bad Data CRC\n"); - return 1; - } - puts ("OK\n"); - return 0; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - puts (" FIT image found\n"); - - if (!fit_check_format (hdr)) { - puts ("Bad FIT image format!\n"); - return 1; - } - - fit_print_contents (hdr); - return 0; -#endif - default: - puts ("Unknown image format!\n"); - break; - } - return 1; } U_BOOT_CMD( - iminfo, CFG_MAXARGS, 1, do_iminfo, - "iminfo - print header information for application image\n", - "addr [addr ...]\n" - " - print header information for application image starting at\n" - " address 'addr' in memory; this includes verification of the\n" - " image contents (magic number, header and payload checksums)\n" + bootm, CFG_MAXARGS, 1, do_bootm, + "bootm - boot application image from memory\n", + "[addr [arg ...]]\n - boot application image stored in memory\n" + "\tpassing arguments 'arg ...'; when booting a Linux kernel,\n" + "\t'arg' can be the address of an initrd image\n" ); -#endif - -/*******************************************************************/ -/* imls - list all images found in flash */ -/*******************************************************************/ -#if defined(CONFIG_CMD_IMLS) -int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - flash_info_t *info; - int i, j; - void *hdr; - - for (i = 0, info = &flash_info[0]; - i < CFG_MAX_FLASH_BANKS; ++i, ++info) { - - if (info->flash_id == FLASH_UNKNOWN) - goto next_bank; - for (j = 0; j < info->sector_count; ++j) { - - hdr = (void *)info->start[j]; - if (!hdr) - goto next_sector; - - switch (genimg_get_format (hdr)) { - case IMAGE_FORMAT_LEGACY: - if (!image_check_hcrc (hdr)) - goto next_sector; - - printf ("Legacy Image at %08lX:\n", (ulong)hdr); - image_print_contents (hdr); - - puts (" Verifying Checksum ... "); - if (!image_check_dcrc (hdr)) { - puts ("Bad Data CRC\n"); - } else { - puts ("OK\n"); - } - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - if (!fit_check_format (hdr)) - goto next_sector; - - printf ("FIT Image at %08lX:\n", (ulong)hdr); - fit_print_contents (hdr); - break; -#endif - default: - goto next_sector; - } - -next_sector: ; - } -next_bank: ; - } - - return (0); -} - -U_BOOT_CMD( - imls, 1, 1, do_imls, - "imls - list all images found in flash\n", - "\n" - " - Prints information about all images found at sector\n" - " boundaries in flash.\n" -); -#endif - -/*******************************************************************/ -/* helper routines */ -/*******************************************************************/ #ifdef CONFIG_SILENT_CONSOLE -static void fixup_silent_linux () +static void +fixup_silent_linux () { + DECLARE_GLOBAL_DATA_PTR; char buf[256], *start, *end; char *cmdline = getenv ("bootargs"); @@ -874,28 +492,364 @@ static void fixup_silent_linux () } #endif /* CONFIG_SILENT_CONSOLE */ - -/*******************************************************************/ -/* OS booting routines */ -/*******************************************************************/ - -static void do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, - int argc, char *argv[], - bootm_headers_t *images) +#ifdef CONFIG_PPC +static void +do_bootm_linux (cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[], + ulong addr, + ulong *len_ptr, + int verify) { - void (*loader)(bd_t *, image_header_t *, char *, char *); - image_header_t *os_hdr, *hdr; - ulong kernel_data, kernel_len; - char *consdev; - char *cmdline; + DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset ("NetBSD"); - do_reset (cmdtp, flag, argc, argv); + ulong sp; + ulong len, checksum; + ulong initrd_start, initrd_end; + ulong cmd_start, cmd_end; + ulong initrd_high; + ulong data; + int initrd_copy_to_ram = 1; + char *cmdline; + char *s; + bd_t *kbd; + void (*kernel)(bd_t *, ulong, ulong, ulong, ulong); + image_header_t *hdr = &header; + + if ((s = getenv ("initrd_high")) != NULL) { + /* a value of "no" or a similar string will act like 0, + * turning the "load high" feature off. This is intentional. + */ + initrd_high = simple_strtoul(s, NULL, 16); + if (initrd_high == ~0) + initrd_copy_to_ram = 0; + } else { /* not set, no restrictions to load high */ + initrd_high = ~0; } + +#ifdef CONFIG_LOGBUFFER + kbd=gd->bd; + /* Prevent initrd from overwriting logbuffer */ + if (initrd_high < (kbd->bi_memsize-LOGBUFF_LEN-LOGBUFF_OVERHEAD)) + initrd_high = kbd->bi_memsize-LOGBUFF_LEN-LOGBUFF_OVERHEAD; + debug ("## Logbuffer at 0x%08lX ", kbd->bi_memsize-LOGBUFF_LEN); #endif - hdr = images->legacy_hdr_os; + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CFG_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + + asm( "mr %0,1": "=r"(sp) : ); + + debug ("## Current stack ends at 0x%08lX ", sp); + + sp -= 2048; /* just to be sure */ + if (sp > CFG_BOOTMAPSZ) + sp = CFG_BOOTMAPSZ; + sp &= ~0xF; + + debug ("=> set upper limit to 0x%08lX\n", sp); + + cmdline = (char *)((sp - CFG_BARGSIZE) & ~0xF); + kbd = (bd_t *)(((ulong)cmdline - sizeof(bd_t)) & ~0xF); + + if ((s = getenv("bootargs")) == NULL) + s = ""; + + strcpy (cmdline, s); + + cmd_start = (ulong)&cmdline[0]; + cmd_end = cmd_start + strlen(cmdline); + + *kbd = *(gd->bd); + +#ifdef DEBUG + printf ("## cmdline at 0x%08lX ... 0x%08lX\n", cmd_start, cmd_end); + + do_bdinfo (NULL, 0, 0, NULL); +#endif + + if ((s = getenv ("clocks_in_mhz")) != NULL) { + /* convert all clock information to MHz */ + kbd->bi_intfreq /= 1000000L; + kbd->bi_busfreq /= 1000000L; +#if defined(CONFIG_MPC8220) + kbd->bi_inpfreq /= 1000000L; + kbd->bi_pcifreq /= 1000000L; + kbd->bi_pevfreq /= 1000000L; + kbd->bi_flbfreq /= 1000000L; + kbd->bi_vcofreq /= 1000000L; +#endif +#if defined(CONFIG_8260) || defined(CONFIG_MPC8560) + kbd->bi_cpmfreq /= 1000000L; + kbd->bi_brgfreq /= 1000000L; + kbd->bi_sccfreq /= 1000000L; + kbd->bi_vco /= 1000000L; +#endif /* CONFIG_8260 */ +#if defined(CONFIG_MPC5xxx) + kbd->bi_ipbfreq /= 1000000L; + kbd->bi_pcifreq /= 1000000L; +#endif /* CONFIG_MPC5xxx */ + } + + kernel = (void (*)(bd_t *, ulong, ulong, ulong, ulong))hdr->ih_ep; + + /* + * Check if there is an initrd image + */ + if (argc >= 3) { + SHOW_BOOT_PROGRESS (9); + + addr = simple_strtoul(argv[2], NULL, 16); + + printf ("## Loading RAMDisk Image at %08lx ...\n", addr); + + /* Copy header so we can blank CRC field for re-calculation */ + memmove (&header, (char *)addr, sizeof(image_header_t)); + + if (hdr->ih_magic != IH_MAGIC) { + puts ("Bad Magic Number\n"); + SHOW_BOOT_PROGRESS (-10); + do_reset (cmdtp, flag, argc, argv); + } + + data = (ulong)&header; + len = sizeof(image_header_t); + + checksum = hdr->ih_hcrc; + hdr->ih_hcrc = 0; + + if (crc32 (0, (char *)data, len) != checksum) { + puts ("Bad Header Checksum\n"); + SHOW_BOOT_PROGRESS (-11); + do_reset (cmdtp, flag, argc, argv); + } + + SHOW_BOOT_PROGRESS (10); + + print_image_hdr (hdr); + + data = addr + sizeof(image_header_t); + len = hdr->ih_size; + + if (verify) { + ulong csum = 0; +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + ulong cdata = data, edata = cdata + len; +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + + puts (" Verifying Checksum ... "); + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + + while (cdata < edata) { + ulong chunk = edata - cdata; + + if (chunk > CHUNKSZ) + chunk = CHUNKSZ; + csum = crc32 (csum, (char *)cdata, chunk); + cdata += chunk; + + WATCHDOG_RESET(); + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + csum = crc32 (0, (char *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + + if (csum != hdr->ih_dcrc) { + puts ("Bad Data CRC\n"); + SHOW_BOOT_PROGRESS (-12); + do_reset (cmdtp, flag, argc, argv); + } + puts ("OK\n"); + } + + SHOW_BOOT_PROGRESS (11); + + if ((hdr->ih_os != IH_OS_LINUX) || + (hdr->ih_arch != IH_CPU_PPC) || + (hdr->ih_type != IH_TYPE_RAMDISK) ) { + puts ("No Linux PPC Ramdisk Image\n"); + SHOW_BOOT_PROGRESS (-13); + do_reset (cmdtp, flag, argc, argv); + } + + /* + * Now check if we have a multifile image + */ + } else if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) { + u_long tail = ntohl(len_ptr[0]) % 4; + int i; + + SHOW_BOOT_PROGRESS (13); + + /* skip kernel length and terminator */ + data = (ulong)(&len_ptr[2]); + /* skip any additional image length fields */ + for (i=1; len_ptr[i]; ++i) + data += 4; + /* add kernel length, and align */ + data += ntohl(len_ptr[0]); + if (tail) { + data += 4 - tail; + } + + len = ntohl(len_ptr[1]); + + } else { + /* + * no initrd image + */ + SHOW_BOOT_PROGRESS (14); + + len = data = 0; + } + + if (!data) { + debug ("No initrd\n"); + } + + if (data) { + if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ + initrd_start = data; + initrd_end = initrd_start + len; + } else { + initrd_start = (ulong)kbd - len; + initrd_start &= ~(4096 - 1); /* align on page */ + + if (initrd_high) { + ulong nsp; + + /* + * the inital ramdisk does not need to be within + * CFG_BOOTMAPSZ as it is not accessed until after + * the mm system is initialised. + * + * do the stack bottom calculation again and see if + * the initrd will fit just below the monitor stack + * bottom without overwriting the area allocated + * above for command line args and board info. + */ + asm( "mr %0,1": "=r"(nsp) : ); + nsp -= 2048; /* just to be sure */ + nsp &= ~0xF; + if (nsp > initrd_high) /* limit as specified */ + nsp = initrd_high; + nsp -= len; + nsp &= ~(4096 - 1); /* align on page */ + if (nsp >= sp) + initrd_start = nsp; + } + + SHOW_BOOT_PROGRESS (12); + + debug ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", + data, data + len - 1, len, len); + + initrd_end = initrd_start + len; + printf (" Loading Ramdisk to %08lx, end %08lx ... ", + initrd_start, initrd_end); +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + { + size_t l = len; + void *to = (void *)initrd_start; + void *from = (void *)data; + + while (l > 0) { + size_t tail = (l > CHUNKSZ) ? CHUNKSZ : l; + WATCHDOG_RESET(); + memmove (to, from, tail); + to += tail; + from += tail; + l -= tail; + } + } +#else /* !(CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG) */ + memmove ((void *)initrd_start, (void *)data, len); +#endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ + puts ("OK\n"); + } + } else { + initrd_start = 0; + initrd_end = 0; + } + + + debug ("## Transferring control to Linux (at address %08lx) ...\n", + (ulong)kernel); + + SHOW_BOOT_PROGRESS (15); + +#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) + unlock_ram_in_cache(); +#endif + /* + * Linux Kernel Parameters: + * r3: ptr to board info data + * r4: initrd_start or 0 if no initrd + * r5: initrd_end - unused if r4 is 0 + * r6: Start of command line string + * r7: End of command line string + */ + (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end); +} +#endif /* CONFIG_PPC */ + +/*******************************************************************/ +/* altboot - boot alternative image */ +/*******************************************************************/ +#if defined(CONFIG_CMD_ALTBOOT) +int do_altboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; + +#ifndef __DONT_INTEGRATE_ME_TO_1_3_4__ + /* Temporary hack for temporary update system. The correct behaviour is: + 1) Try Movi + 2) Try recovery on NOR + 3) Kill power + */ +#endif + +#ifndef CFG_HUSH_PARSER + if (run_command (getenv ("altbootcmd"), flag) < 0) + rcode = 1; +#else + if (parse_string_outer (getenv ("altbootcmd"), + FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) != 0) + rcode = 1; +#endif + return rcode; +} + +U_BOOT_CMD( + altboot, 1, 1, do_altboot, + "altboot - boot alternative, i.e., run 'altbootcmd'\n", + NULL +); +#endif /* CONFIG_CMD_ALTBOOT */ + +static void +do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[], + ulong addr, + ulong *len_ptr, + int verify) +{ + DECLARE_GLOBAL_DATA_PTR; + + image_header_t *hdr = &header; + + void (*loader)(bd_t *, image_header_t *, char *, char *); + image_header_t *img_addr; + char *consdev; + char *cmdline; + /* * Booting a (NetBSD) kernel image @@ -908,12 +862,11 @@ static void do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, * line, the name of the console device, and (optionally) the * address of the original image header. */ - os_hdr = NULL; - if (image_check_type (&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) { - image_multi_getimg (hdr, 1, &kernel_data, &kernel_len); - if (kernel_len) - os_hdr = hdr; - } + + img_addr = 0; + if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) + img_addr = (image_header_t *) addr; + consdev = ""; #if defined (CONFIG_8xx_CONS_SMC1) @@ -930,26 +883,26 @@ static void do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, ulong len; int i; - for (i = 2, len = 0; i < argc; i += 1) + for (i=2, len=0 ; i 2) cmdline[len++] = ' '; strcpy (&cmdline[len], argv[i]); len += strlen (argv[i]); } - } else if ((cmdline = getenv ("bootargs")) == NULL) { + } else if ((cmdline = getenv("bootargs")) == NULL) { cmdline = ""; } - loader = (void (*)(bd_t *, image_header_t *, char *, char *))image_get_ep (hdr); + loader = (void (*)(bd_t *, image_header_t *, char *, char *)) hdr->ih_ep; printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n", (ulong)loader); - show_boot_progress (15); + SHOW_BOOT_PROGRESS (15); /* * NetBSD Stage-2 Loader Parameters: @@ -958,116 +911,29 @@ static void do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, * r5: console device * r6: boot args string */ - (*loader) (gd->bd, os_hdr, consdev, cmdline); + (*loader) (gd->bd, img_addr, consdev, cmdline); } -#ifdef CONFIG_LYNXKDI -static void do_bootm_lynxkdi (cmd_tbl_t *cmdtp, int flag, - int argc, char *argv[], - bootm_headers_t *images) -{ - image_header_t *hdr = &images->legacy_hdr_os_copy; - -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset ("Lynx"); - do_reset (cmdtp, flag, argc, argv); - } -#endif - - lynxkdi_boot ((image_header_t *)hdr); -} -#endif /* CONFIG_LYNXKDI */ - -static void do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, - int argc, char *argv[], - bootm_headers_t *images) -{ - image_header_t *hdr = &images->legacy_hdr_os_copy; - void (*entry_point)(bd_t *); - -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset ("RTEMS"); - do_reset (cmdtp, flag, argc, argv); - } -#endif - - entry_point = (void (*)(bd_t *))image_get_ep (hdr); - - printf ("## Transferring control to RTEMS (at address %08lx) ...\n", - (ulong)entry_point); - - show_boot_progress (15); - - /* - * RTEMS Parameters: - * r3: ptr to board info data - */ - (*entry_point)(gd->bd); -} - -#if defined(CONFIG_CMD_ELF) -static void do_bootm_vxworks (cmd_tbl_t *cmdtp, int flag, - int argc, char *argv[], - bootm_headers_t *images) -{ - char str[80]; - image_header_t *hdr = &images->legacy_hdr_os_copy; - -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset ("VxWorks"); - do_reset (cmdtp, flag, argc, argv); - } -#endif - - sprintf(str, "%x", image_get_ep (hdr)); /* write entry-point into string */ - setenv("loadaddr", str); - do_bootvx(cmdtp, 0, 0, NULL); -} - -static void do_bootm_qnxelf(cmd_tbl_t *cmdtp, int flag, - int argc, char *argv[], - bootm_headers_t *images) -{ - char *local_args[2]; - char str[16]; - image_header_t *hdr = &images->legacy_hdr_os_copy; - -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset ("QNX"); - do_reset (cmdtp, flag, argc, argv); - } -#endif - - sprintf(str, "%x", image_get_ep (hdr)); /* write entry-point into string */ - local_args[0] = argv[0]; - local_args[1] = str; /* and provide it via the arguments */ - do_bootelf(cmdtp, 0, 2, local_args); -} -#endif - #if defined(CONFIG_ARTOS) && defined(CONFIG_PPC) -static void do_bootm_artos (cmd_tbl_t *cmdtp, int flag, - int argc, char *argv[], - bootm_headers_t *images) + +/* Function that returns a character from the environment */ +extern uchar (*env_get_char)(int); + +static void +do_bootm_artos (cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[], + ulong addr, + ulong *len_ptr, + int verify) { + DECLARE_GLOBAL_DATA_PTR; ulong top; char *s, *cmdline; char **fwenv, **ss; int i, j, nxt, len, envno, envsz; bd_t *kbd; void (*entry)(bd_t *bd, char *cmdline, char **fwenv, ulong top); - image_header_t *hdr = &images->legacy_hdr_os_copy; - -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset ("ARTOS"); - do_reset (cmdtp, flag, argc, argv); - } -#endif + image_header_t *hdr = &header; /* * Booting an ARTOS kernel image + application @@ -1088,27 +954,27 @@ static void do_bootm_artos (cmd_tbl_t *cmdtp, int flag, debug ("=> set upper limit to 0x%08lX\n", top); /* first check the artos specific boot args, then the linux args*/ - if ((s = getenv( "abootargs")) == NULL && (s = getenv ("bootargs")) == NULL) + if ((s = getenv("abootargs")) == NULL && (s = getenv("bootargs")) == NULL) s = ""; /* get length of cmdline, and place it */ - len = strlen (s); + len = strlen(s); top = (top - (len + 1)) & ~0xF; cmdline = (char *)top; debug ("## cmdline at 0x%08lX ", top); - strcpy (cmdline, s); + strcpy(cmdline, s); /* copy bdinfo */ - top = (top - sizeof (bd_t)) & ~0xF; + top = (top - sizeof(bd_t)) & ~0xF; debug ("## bd at 0x%08lX ", top); kbd = (bd_t *)top; - memcpy (kbd, gd->bd, sizeof (bd_t)); + memcpy(kbd, gd->bd, sizeof(bd_t)); /* first find number of env entries, and their size */ envno = 0; envsz = 0; - for (i = 0; env_get_char (i) != '\0'; i = nxt + 1) { - for (nxt = i; env_get_char (nxt) != '\0'; ++nxt) + for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) { + for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) ; envno++; envsz += (nxt - i) + 1; /* plus trailing zero */ @@ -1116,7 +982,7 @@ static void do_bootm_artos (cmd_tbl_t *cmdtp, int flag, envno++; /* plus the terminating zero */ debug ("## %u envvars total size %u ", envno, envsz); - top = (top - sizeof (char **) * envno) & ~0xF; + top = (top - sizeof(char **)*envno) & ~0xF; fwenv = (char **)top; debug ("## fwenv at 0x%08lX ", top); @@ -1125,17 +991,424 @@ static void do_bootm_artos (cmd_tbl_t *cmdtp, int flag, ss = fwenv; /* now copy them */ - for (i = 0; env_get_char (i) != '\0'; i = nxt + 1) { - for (nxt = i; env_get_char (nxt) != '\0'; ++nxt) + for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) { + for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) ; *ss++ = s; for (j = i; j < nxt; ++j) - *s++ = env_get_char (j); + *s++ = env_get_char(j); *s++ = '\0'; } *ss++ = NULL; /* terminate */ - entry = (void (*)(bd_t *, char *, char **, ulong))image_get_ep (hdr); - (*entry) (kbd, cmdline, fwenv, top); + entry = (void (*)(bd_t *, char *, char **, ulong))ntohl(hdr->ih_ep); + (*entry)(kbd, cmdline, fwenv, top); } #endif + + +#if (CONFIG_COMMANDS & CFG_CMD_BOOTD) +int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; +#ifndef CFG_HUSH_PARSER + if (run_command (getenv ("bootcmd"), flag) < 0) rcode = 1; +#else + if (parse_string_outer(getenv("bootcmd"), + FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP) != 0 ) rcode = 1; +#endif + return rcode; +} + +U_BOOT_CMD( + boot, 1, 1, do_bootd, + "boot - boot default, i.e., run 'bootcmd'\n", + NULL +); + +/* keep old command name "bootd" for backward compatibility */ +U_BOOT_CMD( + bootd, 1, 1, do_bootd, + "bootd - boot default, i.e., run 'bootcmd'\n", + NULL +); + +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IMI) +int do_iminfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int arg; + ulong addr; + int rcode=0; + + if (argc < 2) { + return image_info (load_addr); + } + + for (arg=1; arg ih_magic) != IH_MAGIC) { + puts (" Bad Magic Number\n"); + return 1; + } + + data = (ulong)&header; + len = sizeof(image_header_t); + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (unsigned char *)data, len) != checksum) { + puts (" Bad Header Checksum\n"); + return 1; + } + + /* for multi-file images we need the data part, too */ + print_image_hdr ((image_header_t *)addr); + + data = addr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + + puts (" Verifying Checksum ... "); + if (crc32 (0, (unsigned char *)data, len) != ntohl(hdr->ih_dcrc)) { + puts (" Bad Data CRC\n"); + return 1; + } + puts ("OK\n"); + return 0; +} + +U_BOOT_CMD( + iminfo, CFG_MAXARGS, 1, do_iminfo, + "iminfo - print header information for application image\n", + "addr [addr ...]\n" + " - print header information for application image starting at\n" + " address 'addr' in memory; this includes verification of the\n" + " image contents (magic number, header and payload checksums)\n" +); + +#endif /* CFG_CMD_IMI */ + +#if (CONFIG_COMMANDS & CFG_CMD_IMLS) +/*----------------------------------------------------------------------- + * List all images found in flash. + */ +int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + flash_info_t *info; + int i, j; + image_header_t *hdr; + ulong data, len, checksum; + + for (i=0, info=&flash_info[0]; iflash_id == FLASH_UNKNOWN) + goto next_bank; + for (j=0; jstart[j]) || + (ntohl(hdr->ih_magic) != IH_MAGIC)) + goto next_sector; + + /* Copy header so we can blank CRC field for re-calculation */ + memmove (&header, (char *)hdr, sizeof(image_header_t)); + + checksum = ntohl(header.ih_hcrc); + header.ih_hcrc = 0; + + if (crc32 (0, (unsigned char *)&header, sizeof(image_header_t)) + != checksum) + goto next_sector; + + printf ("Image at %08lX:\n", (ulong)hdr); + print_image_hdr( hdr ); + + data = (ulong)hdr + sizeof(image_header_t); + len = ntohl(hdr->ih_size); + + puts (" Verifying Checksum ... "); + if (crc32 (0, (unsigned char *)data, len) != ntohl(hdr->ih_dcrc)) { + puts (" Bad Data CRC\n"); + } + puts ("OK\n"); +next_sector: ; + } +next_bank: ; + } + + return (0); +} + +U_BOOT_CMD( + imls, 1, 1, do_imls, + "imls - list all images found in flash\n", + "\n" + " - Prints information about all images found at sector\n" + " boundaries in flash.\n" +); +#endif /* CFG_CMD_IMLS */ + +void +print_image_hdr (image_header_t *hdr) +{ +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) + time_t timestamp = (time_t)ntohl(hdr->ih_time); + struct rtc_time tm; +#endif + + printf (" Image Name: %.*s\n", IH_NMLEN, hdr->ih_name); +#if (CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_TIMESTAMP) + to_tm (timestamp, &tm); + printf (" Created: %4d-%02d-%02d %2d:%02d:%02d UTC\n", + tm.tm_year, tm.tm_mon, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec); +#endif /* CFG_CMD_DATE, CONFIG_TIMESTAMP */ + puts (" Image Type: "); print_type(hdr); + printf ("\n Data Size: %d Bytes = ", ntohl(hdr->ih_size)); + print_size (ntohl(hdr->ih_size), "\n"); + printf (" Load Address: %08x\n" + " Entry Point: %08x\n", + ntohl(hdr->ih_load), ntohl(hdr->ih_ep)); + + if (hdr->ih_type == IH_TYPE_MULTI) { + int i; + ulong len; + ulong *len_ptr = (ulong *)((ulong)hdr + sizeof(image_header_t)); + + puts (" Contents:\n"); + for (i=0; (len = ntohl(*len_ptr)); ++i, ++len_ptr) { + printf (" Image %d: %8ld Bytes = ", i, len); + print_size (len, "\n"); + } + } +} + + +static void +print_type (image_header_t *hdr) +{ + char *os, *arch, *type, *comp; + + switch (hdr->ih_os) { + case IH_OS_INVALID: os = "Invalid OS"; break; + case IH_OS_NETBSD: os = "NetBSD"; break; + case IH_OS_LINUX: os = "Linux"; break; + case IH_OS_VXWORKS: os = "VxWorks"; break; + case IH_OS_QNX: os = "QNX"; break; + case IH_OS_U_BOOT: os = "U-Boot"; break; + case IH_OS_RTEMS: os = "RTEMS"; break; +#ifdef CONFIG_ARTOS + case IH_OS_ARTOS: os = "ARTOS"; break; +#endif +#ifdef CONFIG_LYNXKDI + case IH_OS_LYNXOS: os = "LynxOS"; break; +#endif + default: os = "Unknown OS"; break; + } + + switch (hdr->ih_arch) { + case IH_CPU_INVALID: arch = "Invalid CPU"; break; + case IH_CPU_ALPHA: arch = "Alpha"; break; + case IH_CPU_ARM: arch = "ARM"; break; + case IH_CPU_I386: arch = "Intel x86"; break; + case IH_CPU_IA64: arch = "IA64"; break; + case IH_CPU_MIPS: arch = "MIPS"; break; + case IH_CPU_MIPS64: arch = "MIPS 64 Bit"; break; + case IH_CPU_PPC: arch = "PowerPC"; break; + case IH_CPU_S390: arch = "IBM S390"; break; + case IH_CPU_SH: arch = "SuperH"; break; + case IH_CPU_SPARC: arch = "SPARC"; break; + case IH_CPU_SPARC64: arch = "SPARC 64 Bit"; break; + case IH_CPU_M68K: arch = "M68K"; break; + case IH_CPU_MICROBLAZE: arch = "Microblaze"; break; + default: arch = "Unknown Architecture"; break; + } + + switch (hdr->ih_type) { + case IH_TYPE_INVALID: type = "Invalid Image"; break; + case IH_TYPE_STANDALONE:type = "Standalone Program"; break; + case IH_TYPE_KERNEL: type = "Kernel Image"; break; + case IH_TYPE_RAMDISK: type = "RAMDisk Image"; break; + case IH_TYPE_MULTI: type = "Multi-File Image"; break; + case IH_TYPE_FIRMWARE: type = "Firmware"; break; + case IH_TYPE_SCRIPT: type = "Script"; break; + default: type = "Unknown Image"; break; + } + + switch (hdr->ih_comp) { + case IH_COMP_NONE: comp = "uncompressed"; break; + case IH_COMP_GZIP: comp = "gzip compressed"; break; + case IH_COMP_BZIP2: comp = "bzip2 compressed"; break; + default: comp = "unknown compression"; break; + } + + printf ("%s %s %s (%s)", arch, os, type, comp); +} + +#define ZALLOC_ALIGNMENT 16 + +static void *zalloc(void *x, unsigned items, unsigned size) +{ + void *p; + + size *= items; + size = (size + ZALLOC_ALIGNMENT - 1) & ~(ZALLOC_ALIGNMENT - 1); + + p = malloc (size); + + return (p); +} + +static void zfree(void *x, void *addr, unsigned nb) +{ + free (addr); +} + +#define HEAD_CRC 2 +#define EXTRA_FIELD 4 +#define ORIG_NAME 8 +#define COMMENT 0x10 +#define RESERVED 0xe0 + +#define DEFLATED 8 + +int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) +{ + z_stream s; + int r, i, flags; + + /* skip header */ + i = 10; + flags = src[3]; + if (src[2] != DEFLATED || (flags & RESERVED) != 0) { + puts ("Error: Bad gzipped data\n"); + return (-1); + } + if ((flags & EXTRA_FIELD) != 0) + i = 12 + src[10] + (src[11] << 8); + if ((flags & ORIG_NAME) != 0) + while (src[i++] != 0) + ; + if ((flags & COMMENT) != 0) + while (src[i++] != 0) + ; + if ((flags & HEAD_CRC) != 0) + i += 2; + if (i >= *lenp) { + puts ("Error: gunzip out of data in header\n"); + return (-1); + } + + s.zalloc = zalloc; + s.zfree = zfree; +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + s.outcb = (cb_func)WATCHDOG_RESET; +#else + s.outcb = Z_NULL; +#endif /* CONFIG_HW_WATCHDOG */ + + r = inflateInit2(&s, -MAX_WBITS); + if (r != Z_OK) { + printf ("Error: inflateInit2() returned %d\n", r); + return (-1); + } + s.next_in = src + i; + s.avail_in = *lenp - i; + s.next_out = dst; + s.avail_out = dstlen; + r = inflate(&s, Z_FINISH); + if (r != Z_OK && r != Z_STREAM_END) { + printf ("Error: inflate() returned %d\n", r); + return (-1); + } + *lenp = s.next_out - (unsigned char *) dst; + inflateEnd(&s); + + return (0); +} + +#ifdef CONFIG_BZIP2 +void bz_internal_error(int errcode) +{ + printf ("BZIP2 internal error %d\n", errcode); +} +#endif /* CONFIG_BZIP2 */ + +static void +do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ + DECLARE_GLOBAL_DATA_PTR; + image_header_t *hdr = &header; + void (*entry_point)(bd_t *); + + entry_point = (void (*)(bd_t *)) hdr->ih_ep; + + printf ("## Transferring control to RTEMS (at address %08lx) ...\n", + (ulong)entry_point); + + SHOW_BOOT_PROGRESS (15); + + /* + * RTEMS Parameters: + * r3: ptr to board info data + */ + + (*entry_point ) ( gd->bd ); +} + +#if (CONFIG_COMMANDS & CFG_CMD_ELF) +static void +do_bootm_vxworks (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ + image_header_t *hdr = &header; + char str[80]; + + sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */ + setenv("loadaddr", str); + do_bootvx(cmdtp, 0, 0, NULL); +} + +static void +do_bootm_qnxelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], + ulong addr, ulong *len_ptr, int verify) +{ + image_header_t *hdr = &header; + char *local_args[2]; + char str[16]; + + sprintf(str, "%x", hdr->ih_ep); /* write entry-point into string */ + local_args[0] = argv[0]; + local_args[1] = str; /* and provide it via the arguments */ + do_bootelf(cmdtp, 0, 2, local_args); +} +#endif /* CFG_CMD_ELF */ + +#ifdef CONFIG_LYNXKDI +static void +do_bootm_lynxkdi (cmd_tbl_t *cmdtp, int flag, + int argc, char *argv[], + ulong addr, + ulong *len_ptr, + int verify) +{ + lynxkdi_boot( &header ); +} + +#endif /* CONFIG_LYNXKDI */ diff --git a/common/cmd_cache.c b/common/cmd_cache.c index 675d43fa1..6c250bc1c 100644 --- a/common/cmd_cache.c +++ b/common/cmd_cache.c @@ -27,7 +27,7 @@ #include #include -#if defined(CONFIG_CMD_CACHE) +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) static int on_off (const char *); @@ -109,4 +109,4 @@ U_BOOT_CMD( " - enable or disable data (writethrough) cache\n" ); -#endif +#endif /* CFG_CMD_CACHE */ diff --git a/common/cmd_clock.c b/common/cmd_clock.c new file mode 100644 index 000000000..f8b21e530 --- /dev/null +++ b/common/cmd_clock.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + +#if defined(CONFIG_CMD_CLOCK) + +#ifdef CONFIG_CMD_CLOCK_INFO_BOARD +extern void board_clock_info(); +#else +#define board_clock_info() +#endif + +#ifdef CONFIG_CMD_CLOCK_INFO_CPU +extern void cpu_clock_info(void); +#else +#define cpu_clock_info() +#endif + +int do_clock (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int ret = 1; + + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + } else { + if (0) { + /* Noop to be a base for else-if's */ + } + +#if defined(CONFIG_CMD_CLOCK_INFO_BOARD) || defined(CONFIG_CMD_CLOCK_INFO_CPU) + else if (0 == strncmp(argv[1], "info", 4)) { + cpu_clock_info(); + board_clock_info(); + } +#endif + else { + printf("Unsupported option:\n%s\n", argv[1]); + printf("Usage:\n%s\n", cmdtp->usage); + } + } + + return ret; +} + +U_BOOT_CMD( + clock, 2, 1, do_clock, + "clock - Manage system clocks\n", + " options : \n" + " info - display clock information\n" +); + + + +#endif /* CONFIG_CMD_CLOCK */ diff --git a/common/cmd_console.c b/common/cmd_console.c index 50ddb011c..1bd3709bd 100644 --- a/common/cmd_console.c +++ b/common/cmd_console.c @@ -28,6 +28,8 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_CONSOLE) + extern void _do_coninfo (void); int do_coninfo (cmd_tbl_t * cmd, int flag, int argc, char *argv[]) { @@ -65,3 +67,5 @@ U_BOOT_CMD( "coninfo - print console devices and information\n", "" ); + +#endif /* CFG_CMD_CONSOLE */ diff --git a/common/cmd_date.c b/common/cmd_date.c index 751159847..84932f756 100644 --- a/common/cmd_date.c +++ b/common/cmd_date.c @@ -27,10 +27,11 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; +#if (CONFIG_COMMANDS & CFG_CMD_DATE) + const char *weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", }; @@ -43,11 +44,6 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { struct rtc_time tm; int rcode = 0; - int old_bus; - - /* switch to correct I2C bus */ - old_bus = I2C_GET_BUS(); - I2C_SET_BUS(CFG_RTC_BUS_NUM); switch (argc) { case 2: /* set date & time */ @@ -60,7 +56,7 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* insert new date & time */ if (mk_date (argv[1], &tm) != 0) { puts ("## Bad date format\n"); - break; + return 1; } /* and write to RTC */ rtc_set (&tm); @@ -75,15 +71,11 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) "unknown " : RELOC(weekdays[tm.tm_wday]), tm.tm_hour, tm.tm_min, tm.tm_sec); - break; + return 0; default: printf ("Usage:\n%s\n", cmdtp->usage); rcode = 1; } - - /* switch back to original I2C bus */ - I2C_SET_BUS(old_bus); - return rcode; } @@ -208,3 +200,5 @@ U_BOOT_CMD( " - with numeric argument: set the system date & time\n" " - with 'reset' argument: reset the RTC\n" ); + +#endif /* CFG_CMD_DATE */ diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c index 439d07a65..5842471df 100644 --- a/common/cmd_dcr.c +++ b/common/cmd_dcr.c @@ -29,8 +29,7 @@ #include #include -unsigned long get_dcr (unsigned short); -unsigned long set_dcr (unsigned short, unsigned long); +#if defined(CONFIG_4xx) && (CONFIG_COMMANDS & CFG_CMD_SETGETDCR) /* ======================================================================= * Interpreter command to retrieve an AMCC PPC 4xx Device Control Register @@ -65,6 +64,8 @@ int do_getdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) */ int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { + unsigned long get_dcr (unsigned short); + unsigned long set_dcr (unsigned short, unsigned long); unsigned short dcrn; /* Device Control Register Num */ unsigned long value; @@ -105,120 +106,6 @@ int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } -/* ======================================================================= - * Interpreter command to retrieve an register value through AMCC PPC 4xx - * Device Control Register inderect addressing. - * ======================================================================= - */ -int do_getidcr (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned short adr_dcrn; /* Device Control Register Num for Address */ - unsigned short dat_dcrn; /* Device Control Register Num for Data */ - unsigned short offset; /* Register's offset */ - unsigned long value; /* Register's value */ - char *ptr = NULL; - char buf[80]; - - /* Validate arguments */ - if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - /* Find out whether ther is '.' (dot) symbol in the first parameter. */ - strncpy (buf, argv[1], sizeof(buf)-1); - buf[sizeof(buf)-1] = 0; /* will guarantee zero-end string */ - ptr = strchr (buf, '.'); - - if (ptr != NULL) { - /* First parameter has format adr_dcrn.dat_dcrn */ - *ptr++ = 0; /* erase '.', create zero-end string */ - adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16); - dat_dcrn = (unsigned short) simple_strtoul (ptr, NULL, 16); - } else { - /* - * First parameter has format adr_dcrn; dat_dcrn will be - * calculated as adr_dcrn+1. - */ - adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16); - dat_dcrn = adr_dcrn+1; - } - - /* Register's offset */ - offset = (unsigned short) simple_strtoul (argv[2], NULL, 16); - - /* Disable interrupts */ - disable_interrupts (); - /* Set offset */ - set_dcr (adr_dcrn, offset); - /* get data */ - value = get_dcr (dat_dcrn); - /* Enable interrupts */ - enable_interrupts (); - - printf ("%04x.%04x-%04x Read %08lx\n", adr_dcrn, dat_dcrn, offset, value); - - return 0; -} - -/* ======================================================================= - * Interpreter command to update an register value through AMCC PPC 4xx - * Device Control Register inderect addressing. - * ======================================================================= - */ -int do_setidcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - unsigned short adr_dcrn; /* Device Control Register Num for Address */ - unsigned short dat_dcrn; /* Device Control Register Num for Data */ - unsigned short offset; /* Register's offset */ - unsigned long value; /* Register's value */ - char *ptr = NULL; - char buf[80]; - - /* Validate arguments */ - if (argc < 4) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - /* Find out whether ther is '.' (dot) symbol in the first parameter. */ - strncpy (buf, argv[1], sizeof(buf)-1); - buf[sizeof(buf)-1] = 0; /* will guarantee zero-end string */ - ptr = strchr (buf, '.'); - - if (ptr != NULL) { - /* First parameter has format adr_dcrn.dat_dcrn */ - *ptr++ = 0; /* erase '.', create zero-end string */ - adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16); - dat_dcrn = (unsigned short) simple_strtoul (ptr, NULL, 16); - } else { - /* - * First parameter has format adr_dcrn; dat_dcrn will be - * calculated as adr_dcrn+1. - */ - adr_dcrn = (unsigned short) simple_strtoul (buf, NULL, 16); - dat_dcrn = adr_dcrn+1; - } - - /* Register's offset */ - offset = (unsigned short) simple_strtoul (argv[2], NULL, 16); - /* New value */ - value = (unsigned long) simple_strtoul (argv[3], NULL, 16); - - /* Disable interrupts */ - disable_interrupts (); - /* Set offset */ - set_dcr (adr_dcrn, offset); - /* set data */ - set_dcr (dat_dcrn, value); - /* Enable interrupts */ - enable_interrupts (); - - printf ("%04x.%04x-%04x Write %08lx\n", adr_dcrn, dat_dcrn, offset, value); - - return 0; -} - /***************************************************/ U_BOOT_CMD( @@ -232,14 +119,4 @@ U_BOOT_CMD( "dcrn - set a DCR's value.\n" ); -U_BOOT_CMD( - getidcr, 3, 1, do_getidcr, - "getidcr - Get a register value via indirect DCR addressing\n", - "adr_dcrn[.dat_dcrn] offset - write offset to adr_dcrn, read value from dat_dcrn.\n" -); - -U_BOOT_CMD( - setidcr, 4, 1, do_setidcr, - "setidcr - Set a register value via indirect DCR addressing\n", - "adr_dcrn[.dat_dcrn] offset value - write offset to adr_dcrn, write value to dat_dcrn.\n" -); +#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ diff --git a/common/cmd_diag.c b/common/cmd_diag.c index 82d5ad313..45c4b31f5 100644 --- a/common/cmd_diag.c +++ b/common/cmd_diag.c @@ -28,6 +28,8 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_DIAG) && defined(CONFIG_POST) + int do_diag (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { unsigned int i; @@ -74,3 +76,5 @@ U_BOOT_CMD( "diag run [test1 [test2]]\n" " - run specified tests\n" ); + +#endif /* CFG_CMD_DIAG */ diff --git a/common/cmd_display.c b/common/cmd_display.c index a29345c6b..abee8444e 100644 --- a/common/cmd_display.c +++ b/common/cmd_display.c @@ -24,6 +24,8 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_DISPLAY) + #undef DEBUG_DISP #define DISP_SIZE 8 @@ -76,3 +78,5 @@ U_BOOT_CMD( " - with argument: display on dot matrix display\n" " - without arguments: clear dot matrix display\n" ); + +#endif /* CFG_CMD_DISPLAY */ diff --git a/common/cmd_doc.c b/common/cmd_doc.c index d7b2f535f..ab3751695 100644 --- a/common/cmd_doc.c +++ b/common/cmd_doc.c @@ -11,6 +11,16 @@ #include #include #include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) + #include #include @@ -205,11 +215,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong offset = 0; image_header_t *hdr; int rcode = 0; -#if defined(CONFIG_FIT) - const void *fit_hdr = NULL; -#endif - show_boot_progress (34); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -230,27 +236,24 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - show_boot_progress (-35); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (35); if (!boot_device) { puts ("\n** No boot device **\n"); - show_boot_progress (-36); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (36); dev = simple_strtoul(boot_device, &ep, 16); if ((dev >= CFG_MAX_DOC_DEVICE) || (doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN)) { printf ("\n** Device %d not available\n", dev); - show_boot_progress (-37); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (37); printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n", dev, doc_dev_desc[dev].name, doc_dev_desc[dev].physadr, @@ -259,55 +262,30 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (doc_rw (doc_dev_desc + dev, 1, offset, SECTORSIZE, NULL, (u_char *)addr)) { printf ("** Read error on %d\n", dev); - show_boot_progress (-38); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (38); - switch (genimg_get_format ((void *)addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *)addr; + hdr = (image_header_t *)addr; - image_print_contents (hdr); + if (hdr->ih_magic == IH_MAGIC) { - cnt = image_get_image_size (hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (const void *)addr; - puts ("Fit image detected...\n"); + print_image_hdr (hdr); - cnt = fit_get_size (fit_hdr); - break; -#endif - default: - show_boot_progress (-39); - puts ("** Unknown image type\n"); + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); + cnt -= SECTORSIZE; + } else { + puts ("\n** Bad Magic Number **\n"); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (39); - cnt -= SECTORSIZE; if (doc_rw (doc_dev_desc + dev, 1, offset + SECTORSIZE, cnt, NULL, (u_char *)(addr+SECTORSIZE))) { printf ("** Read error on %d\n", dev); - show_boot_progress (-40); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (40); - -#if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { - if (!fit_check_format (fit_hdr)) { - show_boot_progress (-130); - puts ("** Bad FIT image format\n"); - return 1; - } - show_boot_progress (131); - fit_print_contents (fit_hdr); - } -#endif /* Loading ok, update default load address */ @@ -1629,3 +1607,5 @@ void doc_probe(unsigned long physadr) puts ("No DiskOnChip found\n"); } } + +#endif /* (CONFIG_COMMANDS & CFG_CMD_DOC) */ diff --git a/common/cmd_dtt.c b/common/cmd_dtt.c index 956dc69da..9db64e9e3 100644 --- a/common/cmd_dtt.c +++ b/common/cmd_dtt.c @@ -25,28 +25,22 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_DTT) + #include -#include int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i; unsigned char sensors[] = CONFIG_DTT_SENSORS; - int old_bus; - - /* switch to correct I2C bus */ - old_bus = I2C_GET_BUS(); - I2C_SET_BUS(CFG_DTT_BUS_NUM); /* * Loop through sensors, read * temperature, and output it. */ - for (i = 0; i < sizeof (sensors); i++) + for (i = 0; i < sizeof (sensors); i++) { printf ("DTT%d: %i C\n", i + 1, dtt_get_temp (sensors[i])); - - /* switch back to original I2C bus */ - I2C_SET_BUS(old_bus); + } return 0; } /* do_dtt() */ @@ -55,6 +49,8 @@ int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( dtt, 1, 1, do_dtt, - "dtt - Digital Thermometer and Thermostat\n", + "dtt - Digital Thermometer and Themostat\n", " - Read temperature from digital thermometer and thermostat.\n" ); + +#endif /* CONFIG_COMMANDS & CFG_CMD_DTT */ diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index e5000e9ff..d15a41205 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -42,7 +42,7 @@ #include #include -#if defined(CFG_ENV_IS_IN_EEPROM) || defined(CONFIG_CMD_EEPROM) +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) || defined(CFG_ENV_IS_IN_EEPROM) extern void eeprom_init (void); extern int eeprom_read (unsigned dev_addr, unsigned offset, @@ -62,7 +62,7 @@ extern int eeprom_write_enable (unsigned dev_addr, int state); /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_CMD_EEPROM) +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { const char *const fmt = @@ -110,7 +110,7 @@ int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf ("Usage:\n%s\n", cmdtp->usage); return 1; } -#endif +#endif /* CFG_CMD_EEPROM */ /*----------------------------------------------------------------------- * @@ -121,7 +121,7 @@ int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * 0x00000nxx for EEPROM address selectors and page number at n. */ -#if defined(CFG_ENV_IS_IN_EEPROM) || defined(CONFIG_CMD_EEPROM) +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) || defined(CFG_ENV_IS_IN_EEPROM) #ifndef CONFIG_SPI #if !defined(CFG_I2C_EEPROM_ADDR_LEN) || CFG_I2C_EEPROM_ADDR_LEN < 1 || CFG_I2C_EEPROM_ADDR_LEN > 2 @@ -422,11 +422,10 @@ void eeprom_init (void) } /*----------------------------------------------------------------------- */ -#endif - +#endif /* CFG_CMD_EEPROM */ /***************************************************/ -#if defined(CONFIG_CMD_EEPROM) +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) #ifdef CFG_I2C_MULTI_EEPROMS U_BOOT_CMD( @@ -446,4 +445,4 @@ U_BOOT_CMD( ); #endif /* CFG_I2C_MULTI_EEPROMS */ -#endif +#endif /* CFG_CMD_EEPROM */ diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 62e5e76ac..1d92bb37d 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -23,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif +#if (CONFIG_COMMANDS & CFG_CMD_ELF) + #ifndef MAX #define MAX(a,b) ((a) > (b) ? (a) : (b)) #endif @@ -30,32 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; int valid_elf_image (unsigned long addr); unsigned long load_elf_image (unsigned long addr); -/* Allow ports to override the default behavior */ -__attribute__((weak)) -unsigned long do_bootelf_exec (ulong (*entry)(int, char *[]), int argc, char *argv[]) -{ - unsigned long ret; - - /* - * QNX images require the data cache is disabled. - * Data cache is already flushed, so just turn it off. - */ - int dcache = dcache_status (); - if (dcache) - dcache_disable (); - - /* - * pass address parameter as argv[0] (aka command name), - * and all remaining args - */ - ret = entry (argc, argv); - - if (dcache) - dcache_enable (); - - return ret; -} - /* ====================================================================== * Interpreter command to boot an arbitrary ELF image from memory. * ====================================================================== */ @@ -79,11 +55,18 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("## Starting application at 0x%08lx ...\n", addr); + /* + * QNX images require the data cache is disabled. + * Data cache is already flushed, so just turn it off. + */ + if (dcache_status ()) + dcache_disable (); + /* * pass address parameter as argv[0] (aka command name), * and all remaining args */ - rc = do_bootelf_exec ((void *)addr, argc - 1, argv + 1); + rc = ((ulong (*)(int, char *[])) addr) (--argc, &argv[1]); if (rc != 0) rcode = 1; @@ -96,7 +79,7 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * be either an ELF image or a raw binary. Will attempt to setup the * bootline and other parameters correctly. * ====================================================================== */ -int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { unsigned long addr; /* Address of image */ unsigned long bootaddr; /* Address to put the bootline */ @@ -113,12 +96,14 @@ int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * If we don't know where the image is then we're done. */ - if (argc < 2) - addr = load_addr; - else - addr = simple_strtoul (argv[1], NULL, 16); + if ((tmp = getenv ("loadaddr")) != NULL) { + addr = simple_strtoul (tmp, NULL, 16); + } else { + puts ("No load address provided\n"); + return 1; + } -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) /* Check to see if we need to tftp the image ourselves before starting */ if ((argc == 2) && (strcmp (argv[1], "tftp") == 0)) { @@ -340,3 +325,5 @@ U_BOOT_CMD( "bootvx - Boot vxWorks from an ELF image\n", " [address] - load address of vxWorks ELF image.\n" ); + +#endif /* CFG_CMD_ELF */ diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c index f56940643..bce74ff6f 100644 --- a/common/cmd_ext2.c +++ b/common/cmd_ext2.c @@ -33,14 +33,15 @@ * Ext2fs support */ #include -#include + +#if (CONFIG_COMMANDS & CFG_CMD_EXT2) #include #include #include #include #include #include -#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) +#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE)) #include #endif @@ -56,6 +57,41 @@ #define PRINTF(fmt,args...) #endif +static block_dev_desc_t *get_dev (char* ifname, int dev) +{ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + if (strncmp(ifname,"ide",3)==0) { + extern block_dev_desc_t * ide_get_dev(int dev); + return((dev >= CFG_IDE_MAXDEVICE) ? NULL : ide_get_dev(dev)); + } +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + if (strncmp(ifname,"scsi",4)==0) { + extern block_dev_desc_t * scsi_get_dev(int dev); + return((dev >= CFG_SCSI_MAXDEVICE) ? NULL : scsi_get_dev(dev)); + } +#endif +#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE)) + if (strncmp(ifname,"usb",3)==0) { + extern block_dev_desc_t * usb_stor_get_dev(int dev); + return((dev >= USB_MAX_STOR_DEV) ? NULL : usb_stor_get_dev(dev)); + } +#endif +#if defined(CONFIG_MMC) + if (strncmp(ifname,"mmc",3)==0) { + extern block_dev_desc_t * mmc_get_dev(int dev); + return((dev >= 2) ? NULL : mmc_get_dev(dev)); + } +#endif +#if defined(CONFIG_SYSTEMACE) + if (strcmp(ifname,"ace")==0) { + extern block_dev_desc_t * systemace_get_dev(int dev); + return((dev >= 1) ? NULL : systemace_get_dev(dev)); + } +#endif + return(NULL); +} + int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { char *filename = "/"; @@ -70,7 +106,7 @@ int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return(1); } dev = (int)simple_strtoul (argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); + dev_desc=get_dev(argv[1],dev); if (dev_desc == NULL) { printf ("\n** Block device %s %d not supported\n", argv[1], dev); @@ -173,8 +209,10 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return(1); } + setenv("filesize", 0); + dev = (int)simple_strtoul (argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); + dev_desc=get_dev(argv[1],dev); if (dev_desc==NULL) { printf ("\n** Block device %s %d not supported\n", argv[1], dev); return(1); @@ -242,12 +280,13 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* Loading ok, update default load address */ load_addr = addr; + load_size = filelen; printf ("\n%ld bytes read\n", filelen); sprintf(buf, "%lX", filelen); setenv("filesize", buf); - return(filelen); + return 0; } U_BOOT_CMD( @@ -257,3 +296,5 @@ U_BOOT_CMD( " - load binary file 'filename' from 'dev' on 'interface'\n" " to address 'addr' from ext2 filesystem\n" ); + +#endif /* CONFIG_COMMANDS & CFG_CMD_EXT2 */ diff --git a/common/cmd_fastboot.c b/common/cmd_fastboot.c new file mode 100644 index 000000000..bc7dff293 --- /dev/null +++ b/common/cmd_fastboot.c @@ -0,0 +1,1776 @@ +/* + * Copyright 2008 - 2009 (C) Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Part of the rx_handler were copied from the Android project. + * Specifically rx command parsing in the usb_rx_data_complete + * function of the file bootable/bootloader/legacy/usbloader/usbloader.c + * + * The logical naming of flash comes from the Android project + * Thse structures and functions that look like fastboot_flash_* + * They come from bootable/bootloader/legacy/libboot/flash.c + * + * This is their Copyright: + * + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include +#include +#include + +#if (CONFIG_FASTBOOT) + +#include +#include +#include + +/* Use do_reset for fastboot's 'reboot' command */ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +/* Use do_nand for fastboot's flash commands */ +#if defined(CONFIG_STORAGE_NAND) +extern int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); +#elif defined(CONFIG_STORAGE_EMMC) +extern int do_mmc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern env_t *env_ptr; +#endif +/* Use do_setenv and do_saveenv to permenantly save data */ +int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int do_setenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +/* Use do_bootm and do_go for fastboot's 'boot' command */ +int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/* Forward decl */ +static int tx_handler(void); +static int rx_handler (const unsigned char *buffer, unsigned int buffer_size); +static void reset_handler (void); + +static struct cmd_fastboot_interface interface = +{ + .rx_handler = rx_handler, + .reset_handler = reset_handler, + .product_name = NULL, + .serial_no = NULL, + .nand_block_size = 0, + .transfer_buffer = (unsigned char *)0xffffffff, + .transfer_buffer_size = 0, +}; + +static unsigned int download_size; +static unsigned int download_bytes; +static unsigned int download_bytes_unpadded; +static unsigned int download_error; +static unsigned int continue_booting; +static unsigned int upload_size; +static unsigned int upload_bytes; +static unsigned int upload_error; +static unsigned int mmc_controller_no; + +/* To support the Android-style naming of flash */ +#define MAX_PTN 16 +static fastboot_ptentry ptable[MAX_PTN]; +static unsigned int pcount; +static int static_pcount = -1; + +static void set_env(char *var, char *val) +{ + char *setenv[4] = { "setenv", NULL, NULL, NULL, }; + + setenv[1] = var; + setenv[2] = val; + + do_setenv(NULL, 0, 3, setenv); +} + +static void save_env(struct fastboot_ptentry *ptn, + char *var, char *val) +{ + char start[32], length[32]; + char ecc_type[32]; + + char *lock[5] = { "nand", "lock", NULL, NULL, NULL, }; + char *unlock[5] = { "nand", "unlock", NULL, NULL, NULL, }; + char *ecc[4] = { "nand", "ecc", NULL, NULL, }; + char *saveenv[2] = { "setenv", NULL, }; + + lock[2] = unlock[2] = start; + lock[3] = unlock[3] = length; + + set_env (var, val); + + /* Some flashing requires the nand's ecc to be set */ + ecc[2] = ecc_type; + if ((ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC) && + (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_SW_ECC)) { + /* Both can not be true */ + printf("Warning can not do hw and sw ecc for partition '%s'\n", ptn->name); + printf("Ignoring these flags\n"); + } else if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC) { + sprintf(ecc_type, "hw"); + do_nand(NULL, 0, 3, ecc); + } else if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_SW_ECC) { + sprintf(ecc_type, "sw"); + do_nand(NULL, 0, 3, ecc); + } + sprintf(start, "0x%x", ptn->start); + sprintf(length, "0x%x", ptn->length); + + /* This could be a problem is there is an outstanding lock */ + do_nand(NULL, 0, 4, unlock); + do_saveenv(NULL, 0, 1, saveenv); + do_nand(NULL, 0, 4, lock); +} + +static void save_block_values(struct fastboot_ptentry *ptn, + unsigned int offset, + unsigned int size) +{ + struct fastboot_ptentry *env_ptn; + + char var[64], val[32]; + char start[32], length[32]; + char ecc_type[32]; + + char *lock[5] = { "nand", "lock", NULL, NULL, NULL, }; + char *unlock[5] = { "nand", "unlock", NULL, NULL, NULL, }; + char *ecc[4] = { "nand", "ecc", NULL, NULL, }; + char *setenv[4] = { "setenv", NULL, NULL, NULL, }; + char *saveenv[2] = { "setenv", NULL, }; + + setenv[1] = var; + setenv[2] = val; + lock[2] = unlock[2] = start; + lock[3] = unlock[3] = length; + + printf ("saving it..\n"); + + if (size == 0) + { + /* The error case, where the variables are being unset */ + + sprintf (var, "%s_nand_offset", ptn->name); + sprintf (val, ""); + do_setenv (NULL, 0, 3, setenv); + + sprintf (var, "%s_nand_size", ptn->name); + sprintf (val, ""); + do_setenv (NULL, 0, 3, setenv); + } + else + { + /* Normal case */ + + sprintf (var, "%s_nand_offset", ptn->name); + sprintf (val, "0x%x", offset); + + printf ("%s %s %s\n", setenv[0], setenv[1], setenv[2]); + + do_setenv (NULL, 0, 3, setenv); + + sprintf (var, "%s_nand_size", ptn->name); + + sprintf (val, "0x%x", size); + + printf ("%s %s %s\n", setenv[0], setenv[1], setenv[2]); + + do_setenv (NULL, 0, 3, setenv); + } + + + /* Warning : + The environment is assumed to be in a partition named 'enviroment'. + It is very possible that your board stores the enviroment + someplace else. */ + env_ptn = fastboot_flash_find_ptn("environment"); + + if (env_ptn) + { + /* Some flashing requires the nand's ecc to be set */ + ecc[2] = ecc_type; + if ((env_ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC) && + (env_ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_SW_ECC)) + { + /* Both can not be true */ + printf ("Warning can not do hw and sw ecc for partition '%s'\n", ptn->name); + printf ("Ignoring these flags\n"); + } + else if (env_ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC) + { + sprintf (ecc_type, "hw"); + do_nand (NULL, 0, 3, ecc); + } + else if (env_ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_SW_ECC) + { + sprintf (ecc_type, "sw"); + do_nand (NULL, 0, 3, ecc); + } + + sprintf (start, "0x%x", env_ptn->start); + sprintf (length, "0x%x", env_ptn->length); + + /* This could be a problem is there is an outstanding lock */ + do_nand (NULL, 0, 4, unlock); + } + + do_saveenv (NULL, 0, 1, saveenv); + + if (env_ptn) + { + do_nand (NULL, 0, 4, lock); + } +} + +static void reset_handler () +{ + /* If there was a download going on, bail */ + download_size = 0; + download_bytes = 0; + download_bytes_unpadded = 0; + download_error = 0; + continue_booting = 0; + upload_size = 0; + upload_bytes = 0; + upload_error = 0; +} + +/* When save = 0, just parse. The input is unchanged + When save = 1, parse and do the save. The input is changed */ +static int parse_env(void *ptn, char *err_string, int save, int debug) +{ + int ret = 1; + unsigned int sets = 0; + unsigned int comment_start = 0; + char *var = NULL; + char *var_end = NULL; + char *val = NULL; + char *val_end = NULL; + unsigned int i; + + char *buff = (char *)interface.transfer_buffer; + unsigned int size = download_bytes_unpadded; + + /* The input does not have to be null terminated. + This will cause a problem in the corner case + where the last line does not have a new line. + Put a null after the end of the input. + + WARNING : Input buffer is assumed to be bigger + than the size of the input */ + if (save) + buff[size] = 0; + + for (i = 0; i < size; i++) { + + if (NULL == var) { + + /* + * Check for comments, comment ok only on + * mostly empty lines + */ + if (buff[i] == '#') + comment_start = 1; + + if (comment_start) { + if ((buff[i] == '\r') || + (buff[i] == '\n')) { + comment_start = 0; + } + } else { + if (!((buff[i] == ' ') || + (buff[i] == '\t') || + (buff[i] == '\r') || + (buff[i] == '\n'))) { + /* + * Normal whitespace before the + * variable + */ + var = &buff[i]; + } + } + + } else if (((NULL == var_end) || (NULL == val)) && + ((buff[i] == '\r') || (buff[i] == '\n'))) { + + /* This is the case when a variable + is unset. */ + + if (save) { + /* Set the var end to null so the + normal string routines will work + + WARNING : This changes the input */ + buff[i] = '\0'; + + save_env(ptn, var, val); + + if (debug) + printf("Unsetting %s\n", var); + } + + /* Clear the variable so state is parse is back + to initial. */ + var = NULL; + var_end = NULL; + sets++; + } else if (NULL == var_end) { + if ((buff[i] == ' ') || + (buff[i] == '\t')) + var_end = &buff[i]; + } else if (NULL == val) { + if (!((buff[i] == ' ') || + (buff[i] == '\t'))) + val = &buff[i]; + } else if (NULL == val_end) { + if ((buff[i] == '\r') || + (buff[i] == '\n')) { + /* look for escaped cr or ln */ + if ('\\' == buff[i - 1]) { + /* check for dos */ + if ((buff[i] == '\r') && + (buff[i+1] == '\n')) + buff[i + 1] = ' '; + buff[i - 1] = buff[i] = ' '; + } else { + val_end = &buff[i]; + } + } + } else { + sprintf(err_string, "Internal Error"); + + if (debug) + printf("Internal error at %s %d\n", + __FILE__, __LINE__); + return 1; + } + /* Check if a var / val pair is ready */ + if (NULL != val_end) { + if (save) { + /* Set the end's with nulls so + normal string routines will + work. + + WARNING : This changes the input */ + *var_end = '\0'; + *val_end = '\0'; + + save_env(ptn, var, val); + + if (debug) + printf("Setting %s %s\n", var, val); + } + + /* Clear the variable so state is parse is back + to initial. */ + var = NULL; + var_end = NULL; + val = NULL; + val_end = NULL; + + sets++; + } + } + + /* Corner case + Check for the case that no newline at end of the input */ + if ((NULL != var) && + (NULL == val_end)) { + if (save) { + /* case of val / val pair */ + if (var_end) + *var_end = '\0'; + /* else case handled by setting 0 past + the end of buffer. + Similar for val_end being null */ + save_env(ptn, var, val); + + if (debug) { + if (var_end) + printf("Trailing Setting %s %s\n", var, val); + else + printf("Trailing Unsetting %s\n", var); + } + } + sets++; + } + /* Did we set anything ? */ + if (0 == sets) + sprintf(err_string, "No variables set"); + else + ret = 0; + + return ret; +} + +static int saveenv_to_ptn(struct fastboot_ptentry *ptn, char *err_string) +{ + int ret = 1; + int save = 0; + int debug = 0; + + /* err_string is only 32 bytes + Initialize with a generic error message. */ + sprintf(err_string, "%s", "Unknown Error"); + + /* Parse the input twice. + Only save to the enviroment if the entire input if correct */ + save = 0; + if (0 == parse_env(ptn, err_string, save, debug)) { + save = 1; + ret = parse_env(ptn, err_string, save, debug); + } + return ret; +} + +static void set_ptn_ecc(struct fastboot_ptentry *ptn) +{ + char ecc_type[32]; + char *ecc[4] = {"nand", "ecc", NULL, NULL, }; + + /* Some flashing requires the nand's ecc to be set */ + ecc[2] = ecc_type; + if ((ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC) && + (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_SW_ECC)) { + /* Both can not be true */ + printf("Warning can not do hw and sw ecc for partition '%s'\n", + ptn->name); + printf("Ignoring these flags\n"); + } else if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC) { + sprintf(ecc_type, "hw"); + do_nand(NULL, 0, 3, ecc); + } else if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_SW_ECC) { + sprintf(ecc_type, "sw"); + do_nand(NULL, 0, 3, ecc); + } +} + +static int write_to_ptn(struct fastboot_ptentry *ptn) +{ + int ret = 1; + char start[32], length[32]; + char wstart[32], wlength[32], addr[32]; + char write_type[32]; + int repeat, repeat_max; + + char *lock[5] = { "nand", "lock", NULL, NULL, NULL, }; + char *unlock[5] = { "nand", "unlock", NULL, NULL, NULL, }; + char *write[6] = { "nand", "write", NULL, NULL, NULL, NULL, }; + char *erase[5] = { "nand", "erase", NULL, NULL, NULL, }; + + lock[2] = unlock[2] = erase[2] = start; + lock[3] = unlock[3] = erase[3] = length; + + write[1] = write_type; + write[2] = addr; + write[3] = wstart; + write[4] = wlength; + + printf("flashing '%s'\n", ptn->name); + + /* Which flavor of write to use */ + if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_I) + sprintf(write_type, "write.i"); +#ifdef CFG_NAND_YAFFS_WRITE + else if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_YAFFS) + sprintf(write_type, "write.yaffs"); +#endif + else + sprintf(write_type, "write"); + + set_ptn_ecc(ptn); + + /* Some flashing requires writing the same data in multiple, + consecutive flash partitions */ + repeat_max = 1; + if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_REPEAT_MASK) { + if (ptn->flags & + FASTBOOT_PTENTRY_FLAGS_WRITE_CONTIGUOUS_BLOCK) { + printf("Warning can not do both 'contiguous block' and 'repeat' writes for for partition '%s'\n", ptn->name); + printf("Ignoring repeat flag\n"); + } else { + repeat_max = ptn->flags & + FASTBOOT_PTENTRY_FLAGS_REPEAT_MASK; + } + } + + /* Unlock the whole partition instead of trying to + manage special cases */ + sprintf(length, "0x%x", ptn->length * repeat_max); + + for (repeat = 0; repeat < repeat_max; repeat++) { + sprintf(start, "0x%x", ptn->start + (repeat * ptn->length)); + + do_nand(NULL, 0, 4, unlock); + do_nand(NULL, 0, 4, erase); + + if ((ptn->flags & + FASTBOOT_PTENTRY_FLAGS_WRITE_NEXT_GOOD_BLOCK) && + (ptn->flags & + FASTBOOT_PTENTRY_FLAGS_WRITE_CONTIGUOUS_BLOCK)) { + /* Both can not be true */ + printf("Warning can not do 'next good block' and 'contiguous block' for partition '%s'\n", ptn->name); + printf("Ignoring these flags\n"); + } else if (ptn->flags & + FASTBOOT_PTENTRY_FLAGS_WRITE_NEXT_GOOD_BLOCK) { + /* Keep writing until you get a good block + transfer_buffer should already be aligned */ + if (interface.nand_block_size) { + unsigned int blocks = download_bytes / + interface.nand_block_size; + unsigned int i = 0; + unsigned int offset = 0; + + sprintf(wlength, "0x%x", + interface.nand_block_size); + while (i < blocks) { + /* Check for overflow */ + if (offset >= ptn->length) + break; + + /* download's address only advance + if last write was successful */ + sprintf(addr, "0x%x", + interface.transfer_buffer + + (i * interface.nand_block_size)); + + /* nand's address always advances */ + sprintf(wstart, "0x%x", + ptn->start + (repeat * ptn->length) + offset); + + ret = do_nand(NULL, 0, 5, write); + if (ret) + break; + else + i++; + + /* Go to next nand block */ + offset += interface.nand_block_size; + } + } else { + printf("Warning nand block size can not be 0 when using 'next good block' for partition '%s'\n", ptn->name); + printf("Ignoring write request\n"); + } + } else if (ptn->flags & + FASTBOOT_PTENTRY_FLAGS_WRITE_CONTIGUOUS_BLOCK) { + /* Keep writing until you get a good block + transfer_buffer should already be aligned */ + if (interface.nand_block_size) { + if (0 == nand_curr_device) { + nand_info_t *nand; + unsigned long off; + unsigned int ok_start; + + nand = &nand_info[nand_curr_device]; + + printf("\nDevice %d bad blocks:\n", + nand_curr_device); + + /* Initialize the ok_start to the + start of the partition + Then try to find a block large + enough for the download */ + ok_start = ptn->start; + + /* It is assumed that the start and + length are multiples of block size */ + for (off = ptn->start; + off < ptn->start + ptn->length; + off += nand->erasesize) { + if (nand_block_isbad(nand, off)) { + /* Reset the ok_start + to the next block */ + ok_start = off + + nand->erasesize; + } + + /* Check if we have enough + blocks */ + if ((ok_start - off) >= + download_bytes) + break; + } + + /* Check if there is enough space */ + if (ok_start + download_bytes <= + ptn->start + ptn->length) { + sprintf(addr, "0x%x", interface.transfer_buffer); + sprintf(wstart, "0x%x", ok_start); + sprintf(wlength, "0x%x", download_bytes); + + ret = do_nand(NULL, 0, 5, write); + + /* Save the results into an + environment variable on the + format + ptn_name + 'offset' + ptn_name + 'size' */ + if (ret) { + /* failed */ + save_block_values(ptn, 0, 0); + } else { + /* success */ + save_block_values(ptn, ok_start, download_bytes); + } + } else { + printf("Error could not find enough contiguous space in partition '%s' \n", ptn->name); + printf("Ignoring write request\n"); + } + } else { + /* TBD : Generalize flash handling */ + printf("Error only handling 1 NAND per board"); + printf("Ignoring write request\n"); + } + } else { + printf("Warning nand block size can not be 0 when using 'continuous block' for partition '%s'\n", ptn->name); + printf("Ignoring write request\n"); + } + } else { + /* Normal case */ + sprintf(addr, "0x%x", interface.transfer_buffer); + sprintf(wstart, "0x%x", ptn->start + + (repeat * ptn->length)); + sprintf(wlength, "0x%x", download_bytes); +#ifdef CFG_NAND_YAFFS_WRITE + if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_YAFFS) + sprintf(wlength, "0x%x", + download_bytes_unpadded); +#endif + + ret = do_nand(NULL, 0, 5, write); + + if (0 == repeat) { + if (ret) /* failed */ + save_block_values(ptn, 0, 0); + else /* success */ + save_block_values(ptn, ptn->start, + download_bytes); + } + } + + do_nand(NULL, 0, 4, lock); + + if (ret) + break; + } + + return ret; +} + +static int tx_handler(void) +{ + if (upload_size) { + + int bytes_written; + bytes_written = fastboot_tx(interface.transfer_buffer + + upload_bytes, upload_size - + upload_bytes); + if (bytes_written > 0) { + + upload_bytes += bytes_written; + /* Check if this is the last */ + if (upload_bytes == upload_size) { + + /* Reset upload */ + upload_size = 0; + upload_bytes = 0; + upload_error = 0; + } + } + } + return upload_error; +} + +static int rx_handler (const unsigned char *buffer, unsigned int buffer_size) +{ + int ret = 1; + + /* Use 65 instead of 64 + null gets dropped + strcpy's need the extra byte */ + char response[65]; + + if (download_size) + { + /* Something to download */ + + if (buffer_size) + { + /* Handle possible overflow */ + unsigned int transfer_size = + download_size - download_bytes; + + if (buffer_size < transfer_size) + transfer_size = buffer_size; + + /* Save the data to the transfer buffer */ + memcpy (interface.transfer_buffer + download_bytes, + buffer, transfer_size); + + download_bytes += transfer_size; + + /* Check if transfer is done */ + if (download_bytes >= download_size) { + /* Reset global transfer variable, + Keep download_bytes because it will be + used in the next possible flashing command */ + download_size = 0; + + if (download_error) { + /* There was an earlier error */ + sprintf(response, "ERROR"); + } else { + /* Everything has transferred, + send the OK response */ + sprintf(response, "OKAY"); + } + fastboot_tx_status(response, strlen(response)); + + printf ("\ndownloading of %d bytes finished\n", + download_bytes); + +#if defined(CONFIG_STORAGE_NAND) + /* Pad to block length + In most cases, padding the download to be + block aligned is correct. The exception is + when the following flash writes to the oob + area. This happens when the image is a + YAFFS image. Since we do not know what + the download is until it is flashed, + go ahead and pad it, but save the true + size in case if should have + been unpadded */ + download_bytes_unpadded = download_bytes; + if (interface.nand_block_size) + { + if (download_bytes % + interface.nand_block_size) + { + unsigned int pad = interface.nand_block_size - (download_bytes % interface.nand_block_size); + unsigned int i; + + for (i = 0; i < pad; i++) + { + if (download_bytes >= interface.transfer_buffer_size) + break; + + interface.transfer_buffer[download_bytes] = 0; + download_bytes++; + } + } + } +#endif + } + + /* Provide some feedback */ + if (download_bytes && + 0 == (download_bytes % + (16 * interface.nand_block_size))) + { + /* Some feeback that the + download is happening */ + if (download_error) + printf("X"); + else + printf("."); + if (0 == (download_bytes % + (80 * 16 * + interface.nand_block_size))) + printf("\n"); + + } + } + else + { + /* Ignore empty buffers */ + printf ("Warning empty download buffer\n"); + printf ("Ignoring\n"); + } + ret = 0; + } + else + { + /* A command */ + + /* Cast to make compiler happy with string functions */ + const char *cmdbuf = (char *) buffer; + + /* Generic failed response */ + sprintf(response, "FAIL"); + + /* reboot + Reboot the board. */ + + if(memcmp(cmdbuf, "reboot", 6) == 0) + { + sprintf(response,"OKAY"); + fastboot_tx_status(response, strlen(response)); + udelay (1000000); /* 1 sec */ + + do_reset (NULL, 0, 0, NULL); + + /* This code is unreachable, + leave it to make the compiler happy */ + return 0; + } + + /* getvar + Get common fastboot variables + Board has a chance to handle other variables */ + if(memcmp(cmdbuf, "getvar:", 7) == 0) + { + strcpy(response,"OKAY"); + + if(!strcmp(cmdbuf + strlen("version"), "version")) + { + strcpy(response + 4, FASTBOOT_VERSION); + } + else if(!strcmp(cmdbuf + strlen("product"), "product")) + { + if (interface.product_name) + strcpy(response + 4, interface.product_name); + + } else if(!strcmp(cmdbuf + strlen("serialno"), "serialno")) { + if (interface.serial_no) + strcpy(response + 4, interface.serial_no); + + } else if(!strcmp(cmdbuf + strlen("downloadsize"), "downloadsize")) { + if (interface.transfer_buffer_size) + sprintf(response + 4, "08x", interface.transfer_buffer_size); + } + else + { + fastboot_getvar(cmdbuf + 7, response + 4); + } + ret = 0; + + } + + /* erase + Erase a register flash partition + Board has to set up flash partitions */ + + if(memcmp(cmdbuf, "erase:", 6) == 0){ +#if defined(CONFIG_STORAGE_NAND) + struct fastboot_ptentry *ptn; + + ptn = fastboot_flash_find_ptn(cmdbuf + 6); + if(ptn == 0) + { + sprintf(response, "FAILpartition does not exist"); + } + else + { + char start[32], length[32]; + int status, repeat, repeat_max; + + printf("erasing '%s'\n", ptn->name); + + char *lock[5] = { "nand", "lock", NULL, NULL, NULL, }; + char *unlock[5] = { "nand", "unlock", NULL, NULL, NULL, }; + char *erase[5] = { "nand", "erase", NULL, NULL, NULL, }; + + lock[2] = unlock[2] = erase[2] = start; + lock[3] = unlock[3] = erase[3] = length; + + repeat_max = 1; + if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_REPEAT_MASK) + repeat_max = ptn->flags & FASTBOOT_PTENTRY_FLAGS_REPEAT_MASK; + + sprintf (length, "0x%x", ptn->length); + for (repeat = 0; repeat < repeat_max; repeat++) + { + sprintf (start, "0x%x", ptn->start + (repeat * ptn->length)); + + do_nand (NULL, 0, 4, unlock); + status = do_nand (NULL, 0, 4, erase); + do_nand (NULL, 0, 4, lock); + + if (status) + break; + } + + if (status) + { + sprintf(response,"FAILfailed to erase partition"); + } + else + { + printf("partition '%s' erased\n", ptn->name); + sprintf(response, "OKAY"); + } + + } +#elif defined(CONFIG_STORAGE_EMMC) + struct fastboot_ptentry *ptn; + + /* Save the MMC controller number */ + mmc_controller_no = CFG_FASTBOOT_MMC_NO; + + /* Find the partition and erase it */ + ptn = fastboot_flash_find_ptn(cmdbuf + 6); + + if (ptn == 0) { + sprintf(response, "FAIL: partition doesn't exist"); + } else { + /* Call MMC erase function here */ + char start[32], length[32]; + char slot_no[32]; + + char *erase[5] = { "mmc", NULL, "erase", NULL, NULL, }; + char *mmc_init[2] = {"mmcinit", NULL,}; + + mmc_init[1] = slot_no; + erase[1] = slot_no; + erase[3] = start; + erase[4] = length; + + sprintf(slot_no, "%d", mmc_controller_no); + sprintf(length, "0x%x", ptn->length); + sprintf(start, "0x%x", ptn->start); + + printf("Initializing '%s'\n", ptn->name); + if (do_mmc(NULL, 0, 2, mmc_init)) + sprintf(response, "FAIL: Init of MMC card"); + else + sprintf(response, "OKAY"); + + printf("Erasing '%s'\n", ptn->name); + if (do_mmc(NULL, 0, 5, erase)) { + printf("Erasing '%s' FAILED!\n", ptn->name); + sprintf(response, "FAIL: Erase partition"); + } else { + printf("Erasing '%s' DONE!\n", ptn->name); + sprintf(response, "OKAY"); + } + } +#endif + ret = 0; + } + + /* download + download something .. + What happens to it depends on the next command after data */ + + if(memcmp(cmdbuf, "download:", 9) == 0) { + + /* save the size */ + download_size = simple_strtoul (cmdbuf + 9, NULL, 16); + /* Reset the bytes count, now it is safe */ + download_bytes = 0; + /* Reset error */ + download_error = 0; + + printf ("Starting download of %d bytes\n", download_size); + + if (0 == download_size) + { + /* bad user input */ + sprintf(response, "FAILdata invalid size"); + } + else if (download_size > interface.transfer_buffer_size) + { + /* set download_size to 0 because this is an error */ + download_size = 0; + sprintf(response, "FAILdata too large"); + } + else + { + /* The default case, the transfer fits + completely in the interface buffer */ + sprintf(response, "DATA%08x", download_size); + } + ret = 0; + } + + /* boot + boot what was downloaded + + WARNING WARNING WARNING + + This is not what you expect. + The fastboot client does its own packaging of the + kernel. The layout is defined in the android header + file bootimage.h. This layeout is copiedlooks like this, + + ** + ** +-----------------+ + ** | boot header | 1 page + ** +-----------------+ + ** | kernel | n pages + ** +-----------------+ + ** | ramdisk | m pages + ** +-----------------+ + ** | second stage | o pages + ** +-----------------+ + ** + + We only care about the kernel. + So we have to jump past a page. + + What is a page size ? + The fastboot client uses 2048 + + The is the default value of + + CFG_FASTBOOT_MKBOOTIMAGE_PAGE_SIZE + + */ + + if(memcmp(cmdbuf, "boot", 4) == 0) { + + if ((download_bytes) && + (CFG_FASTBOOT_MKBOOTIMAGE_PAGE_SIZE < download_bytes)) + { + char start[32]; + char *bootm[3] = { "bootm", NULL, NULL, }; + char *go[3] = { "go", NULL, NULL, }; + + /* + * Use this later to determine if a command line was passed + * for the kernel. + */ + struct fastboot_boot_img_hdr *fb_hdr = + (struct fastboot_boot_img_hdr *) interface.transfer_buffer; + + /* Skip the mkbootimage header */ + image_header_t *hdr = + (image_header_t *) + &interface.transfer_buffer[CFG_FASTBOOT_MKBOOTIMAGE_PAGE_SIZE]; + + bootm[1] = go[1] = start; + sprintf (start, "0x%x", hdr); + + /* Execution should jump to kernel so send the response + now and wait a bit. */ + sprintf(response, "OKAY"); + fastboot_tx_status(response, strlen(response)); + udelay (1000000); /* 1 sec */ + + if (ntohl(hdr->ih_magic) == IH_MAGIC) { + /* Looks like a kernel.. */ + printf ("Booting kernel..\n"); + + /* + * Check if the user sent a bootargs down. + * If not, do not override what is already there + */ + if (strlen ((char *) &fb_hdr->cmdline[0])) + set_env ("bootargs", (char *) &fb_hdr->cmdline[0]); + + do_bootm (NULL, 0, 2, bootm); + } else { + /* Raw image, maybe another uboot */ + printf ("Booting raw image..\n"); + + do_go (NULL, 0, 2, go); + } + printf ("ERROR : bootting failed\n"); + printf ("You should reset the board\n"); + } + sprintf(response, "FAILinvalid boot image"); + ret = 0; + } + + /* flash + Flash what was downloaded */ + + if(memcmp(cmdbuf, "flash:", 6) == 0) { +#if defined(CONFIG_STORAGE_NAND) + if (download_bytes) + { + struct fastboot_ptentry *ptn; + + ptn = fastboot_flash_find_ptn(cmdbuf + 6); + if (ptn == 0) { + sprintf(response, "FAILpartition does not exist"); + } else if ((download_bytes > ptn->length) && + !(ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_ENV)) { + sprintf(response, "FAILimage too large for partition"); + /* TODO : Improve check for yaffs write */ + } else { + /* Check if this is not really a flash write + but rather a saveenv */ + if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_ENV) { + /* Since the response can only be 64 bytes, + there is no point in having a large error message. */ + char err_string[32]; + if (saveenv_to_ptn(ptn, &err_string[0])) { + printf("savenv '%s' failed : %s\n", ptn->name, err_string); + sprintf(response, "FAIL%s", err_string); + } else { + printf("partition '%s' saveenv-ed\n", ptn->name); + sprintf(response, "OKAY"); + } + } else { + /* Normal case */ + if (write_to_ptn(ptn)) { + printf("flashing '%s' failed\n", ptn->name); + sprintf(response, "FAILfailed to flash partition"); + } else { + printf("partition '%s' flashed\n", ptn->name); + sprintf(response, "OKAY"); + } + } + } + } + else + { + sprintf(response, "FAILno image downloaded"); + } +#elif defined(CONFIG_STORAGE_EMMC) + if (download_bytes) { + + struct fastboot_ptentry *ptn; + + /* Save the MMC controller number */ + mmc_controller_no = CFG_FASTBOOT_MMC_NO; + + /* Next is the partition name */ + ptn = fastboot_flash_find_ptn(cmdbuf + 6); + + if (ptn == 0) { + printf("Partition:'%s' does not exist\n", ptn->name); + sprintf(response, "FAILpartition does not exist"); + } else if ((download_bytes > ptn->length) && + !(ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_ENV)) { + printf("Image too large for the partition\n"); + sprintf(response, "FAILimage too large for partition"); + } else if (ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_ENV) { + /* Check if this is not really a flash write, + * but instead a saveenv + */ + unsigned int i = 0; + /* Env file is expected with a NULL delimeter between + * env variables So replace New line Feeds (0x0a) with + * NULL (0x00) + */ + for (i = 0; i < download_bytes; i++) { + if (interface.transfer_buffer[i] == 0x0a) + interface.transfer_buffer[i] = 0x00; + } + memset(env_ptr->data, 0, ENV_SIZE); + memcpy(env_ptr->data, interface.transfer_buffer, download_bytes); + do_saveenv(NULL, 0, 1, NULL); + printf("saveenv to '%s' DONE!\n", ptn->name); + sprintf(response, "OKAY"); + } else { + /* Normal case */ + + char source[32], dest[32], length[32]; + char slot_no[32]; + + printf("writing to partition '%s'\n", ptn->name); + char *mmc_write[6] = {"mmc", NULL, "write", NULL, NULL, NULL}; + char *mmc_init[2] = {"mmcinit", NULL,}; + + mmc_init[1] = slot_no; + mmc_write[1] = slot_no; + mmc_write[3] = source; + mmc_write[4] = dest; + mmc_write[5] = length; + + sprintf(slot_no, "%d", mmc_controller_no); + sprintf(source, "0x%x", interface.transfer_buffer); + sprintf(dest, "0x%x", ptn->start); + sprintf(length, "0x%x", download_bytes); + + printf("Initializing '%s'\n", ptn->name); + if (do_mmc(NULL, 0, 2, mmc_init)) + sprintf(response, "FAIL:Init of MMC card"); + else + sprintf(response, "OKAY"); + + + printf("Writing '%s'\n", ptn->name); + if (do_mmc(NULL, 0, 6, mmc_write)) { + printf("Writing '%s' FAILED!\n", ptn->name); + sprintf(response, "FAIL: Write partition"); + } else { + printf("Writing '%s' DONE!\n", ptn->name); + sprintf(response, "OKAY"); + } + } + + } else { + sprintf(response, "FAILno image downloaded"); + } +#endif + ret = 0; + } + + /* continue + Stop doing fastboot */ + if (memcmp(cmdbuf, "continue", 8) == 0) { + sprintf(response, "OKAY"); + continue_booting = 1; + ret = 0; + } + + /* upload + Upload just the data in a partition */ + if ((memcmp(cmdbuf, "upload:", 7) == 0) || + (memcmp(cmdbuf, "uploadraw:", 10) == 0)) { +#if defined(CONFIG_STORAGE_NAND) + unsigned int adv, delim_index, len; + struct fastboot_ptentry *ptn; + unsigned int is_raw = 0; + + /* Is this a raw read ? */ + if (memcmp(cmdbuf, "uploadraw:", 10) == 0) { + is_raw = 1; + adv = 10; + } else { + adv = 7; + } + + /* Scan to the next ':' to find when the size starts */ + len = strlen(cmdbuf); + for (delim_index = adv; + delim_index < len; delim_index++) { + if (cmdbuf[delim_index] == ':') { + /* WARNING, cmdbuf is being modified. */ + *((char *) &cmdbuf[delim_index]) = 0; + break; + } + } + + ptn = fastboot_flash_find_ptn(cmdbuf + adv); + if (ptn == 0) { + sprintf(response, + "FAILpartition does not exist"); + } else { + /* This is how much the user is expecting */ + unsigned int user_size; + /* + * This is the maximum size needed for + * this partition + */ + unsigned int size; + /* This is the length of the data */ + unsigned int length; + /* + * Used to check previous write of + * the parition + */ + char env_ptn_length_var[128]; + char *env_ptn_length_val; + + user_size = 0; + if (delim_index < len) + user_size = + simple_strtoul(cmdbuf + delim_index + + 1, NULL, 16); + + /* Make sure output is padded to block size */ + length = ptn->length; + sprintf(env_ptn_length_var, + "%s_nand_size", ptn->name); + env_ptn_length_val = getenv(env_ptn_length_var); + if (env_ptn_length_val) { + length = + simple_strtoul(env_ptn_length_val, + NULL, 16); + /* Catch possible problems */ + if (!length) + length = ptn->length; + } + + size = length / interface.nand_block_size; + size *= interface.nand_block_size; + if (length % interface.nand_block_size) + size += interface.nand_block_size; + + if (is_raw) + size += (size / + interface.nand_block_size) * + interface.nand_oob_size; + + if (size > interface.transfer_buffer_size) { + + sprintf(response, "FAILdata too large"); + + } else if (user_size == 0) { + + /* Send the data response */ + sprintf(response, "DATA%08x", size); + + } else if (user_size != size) { + /* This is the wrong size */ + sprintf(response, "FAIL"); + } else { + /* + * This is where the transfer + * buffer is populated + */ + unsigned char *buf = + interface.transfer_buffer; + char start[32], length[32], type[32], + addr[32]; + char *read[6] = { "nand", NULL, NULL, + NULL, NULL, NULL, }; + + /* + * Setting upload_size causes + * transfer to happen in main loop + */ + upload_size = size; + upload_bytes = 0; + upload_error = 0; + + /* + * Poison the transfer buffer, 0xff + * is erase value of nand + */ + memset(buf, 0xff, upload_size); + + /* Which flavor of read to use */ + if (is_raw) + sprintf(type, "read.raw"); + else + sprintf(type, "read.i"); + + sprintf(addr, "0x%x", + interface.transfer_buffer); + sprintf(start, "0x%x", ptn->start); + sprintf(length, "0x%x", upload_size); + + read[1] = type; + read[2] = addr; + read[3] = start; + read[4] = length; + + set_ptn_ecc(ptn); + + do_nand(NULL, 0, 5, read); + + /* Send the data response */ + sprintf(response, "DATA%08x", size); + } + } +#endif + ret = 0; + } + + fastboot_tx_status(response, strlen(response)); + + } /* End of command */ + + return ret; +} + +static int check_against_static_partition(struct fastboot_ptentry *ptn) +{ + int ret = 0; + struct fastboot_ptentry *c; + int i; + + for (i = 0; i < static_pcount; i++) { + c = fastboot_flash_get_ptn((unsigned int) i); + + if (0 == ptn->length) + break; + + if ((ptn->start >= c->start) && + (ptn->start < c->start + c->length)) + break; + + if ((ptn->start + ptn->length > c->start) && + (ptn->start + ptn->length <= c->start + c->length)) + break; + + if ((0 == strcmp(ptn->name, c->name)) && + (0 == strcmp(c->name, ptn->name))) + break; + } + + if (i >= static_pcount) + ret = 1; + return ret; +} + +static unsigned long long memparse(char *ptr, char **retptr) +{ + char *endptr; /* local pointer to end of parsed string */ + + unsigned long ret = simple_strtoul(ptr, &endptr, 0); + + switch (*endptr) { + case 'M': + case 'm': + ret <<= 10; + case 'K': + case 'k': + ret <<= 10; + endptr++; + default: + break; + } + + if (retptr) + *retptr = endptr; + + return ret; +} + +static int add_partition_from_environment(char *s, char **retptr) +{ + unsigned long size; + unsigned long offset = 0; + char *name; + int name_len; + int delim; + unsigned int flags; + struct fastboot_ptentry part; + + size = memparse(s, &s); + if (0 == size) { + printf("Error:FASTBOOT size of parition is 0\n"); + return 1; + } + + /* fetch partition name and flags */ + flags = 0; /* this is going to be a regular partition */ + delim = 0; + /* check for offset */ + if (*s == '@') { + s++; + offset = memparse(s, &s); + } else { + printf("Error:FASTBOOT offset of parition is not given\n"); + return 1; + } + + /* now look for name */ + if (*s == '(') + delim = ')'; + + if (delim) { + char *p; + + name = ++s; + p = strchr((const char *)name, delim); + if (!p) { + printf("Error:FASTBOOT no closing %c found in partition name\n", delim); + return 1; + } + name_len = p - name; + s = p + 1; + } else { + printf("Error:FASTBOOT no partition name for \'%s\'\n", s); + return 1; + } + + /* test for options */ + while (1) { + if (strncmp(s, "i", 1) == 0) { + flags |= FASTBOOT_PTENTRY_FLAGS_WRITE_I; + s += 1; + } else if (strncmp(s, "yaffs", 5) == 0) { + /* yaffs */ + flags |= FASTBOOT_PTENTRY_FLAGS_WRITE_YAFFS; + s += 5; + } else if (strncmp(s, "swecc", 5) == 0) { + /* swecc */ + flags |= FASTBOOT_PTENTRY_FLAGS_WRITE_SW_ECC; + s += 5; + } else if (strncmp(s, "hwecc", 5) == 0) { + /* hwecc */ + flags |= FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC; + s += 5; + } else { + break; + } + if (strncmp(s, "|", 1) == 0) + s += 1; + } + + /* enter this partition (offset will be calculated later if it is zero at this point) */ + part.length = size; + part.start = offset; + part.flags = flags; + + if (name) { + if (name_len >= sizeof(part.name)) { + printf("Error:FASTBOOT partition name is too long\n"); + return 1; + } + strncpy(&part.name[0], name, name_len); + /* name is not null terminated */ + part.name[name_len] = '\0'; + } else { + printf("Error:FASTBOOT no name\n"); + return 1; + } + + + /* Check if this overlaps a static partition */ + if (check_against_static_partition(&part)) { + printf("Adding: %s, offset 0x%8.8x, size 0x%8.8x, flags 0x%8.8x\n", + part.name, part.start, part.length, part.flags); + fastboot_flash_add_ptn(&part); + } + + /* return (updated) pointer command line string */ + *retptr = s; + + /* return partition table */ + return 0; +} + + + +int do_fastboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int ret = 1; + char fbparts[4096], *env; + int check_timeout = 0; + uint64_t timeout_endtime = 0; + uint64_t timeout_ticks = 0; + long timeout_seconds = -1; + int continue_from_disconnect = 0; + + /* + * Place the runtime partitions at the end of the + * static paritions. First save the start off so + * it can be saved from run to run. + */ + if (static_pcount >= 0) { + /* Reset */ + pcount = static_pcount; + } else { + /* Save */ + static_pcount = pcount; + } + env = getenv("fbparts"); + if (env) { + unsigned int len; + len = strlen(env); + if (len && len < 4096) { + char *s, *e; + + memcpy(&fbparts[0], env, len + 1); + printf("Fastboot: Adding partitions from environment\n"); + s = &fbparts[0]; + e = s + len; + while (s < e) { + if (add_partition_from_environment(s, &s)) { + printf("Error:Fastboot: Abort adding partitions\n"); + /* reset back to static */ + pcount = static_pcount; + break; + } + /* Skip a bunch of delimiters */ + while (s < e) { + if ((' ' == *s) || + ('\t' == *s) || + ('\n' == *s) || + ('\r' == *s) || + (',' == *s)) { + s++; + } else { + break; + } + } + } + } + } + + /* Time out */ + if (2 == argc) { + long try_seconds; + char *try_seconds_end; + /* Check for timeout */ + try_seconds = simple_strtol(argv[1], + &try_seconds_end, 10); + if ((try_seconds_end != argv[1]) && + (try_seconds >= 0)) { + check_timeout = 1; + timeout_seconds = try_seconds; + printf("Fastboot inactivity timeout %ld seconds\n", timeout_seconds); + } + } + + if (1 == check_timeout) { + timeout_ticks = (uint64_t) + (timeout_seconds * get_tbclk()); + } + + + do { + continue_from_disconnect = 0; + + /* Initialize the board specific support */ + if (0 == fastboot_init(&interface)) { + + int poll_status; + + /* If we got this far, we are a success */ + ret = 0; + printf("fastboot initialized\n"); + + timeout_endtime = get_ticks(); + timeout_endtime += timeout_ticks; + + while (1) { + uint64_t current_time = 0; + poll_status = fastboot_poll(); + + if (1 == check_timeout) + current_time = get_ticks(); + + if (FASTBOOT_ERROR == poll_status) { + /* Error */ + break; + } else if (FASTBOOT_DISCONNECT == poll_status) { + /* beak, cleanup and re-init */ + printf("Fastboot disconnect detected\n"); + continue_from_disconnect = 1; + break; + } else if ((1 == check_timeout) && + (FASTBOOT_INACTIVE == poll_status)) { + + /* No activity */ + if (current_time >= timeout_endtime) { + printf("Fastboot inactivity detected\n"); + break; + } + } else { + /* Something happened */ + if (1 == check_timeout) { + /* Update the timeout endtime */ + timeout_endtime = current_time; + timeout_endtime += timeout_ticks; + } + } + + /* Check if the user wanted to terminate with ^C */ + if ((FASTBOOT_INACTIVE == poll_status) && + (ctrlc())) { + printf("Fastboot ended by user\n"); + break; + } + + /* + * Check if the fastboot client wanted to + * continue booting + */ + if (continue_booting) { + printf("Fastboot ended by client\n"); + break; + } + + /* Check if there is something to upload */ + tx_handler(); + } + } + + /* Reset the board specific support */ + fastboot_shutdown(); + + /* restart the loop if a disconnect was detected */ + } while (continue_from_disconnect); + + return ret; +} + +U_BOOT_CMD( + fastboot, 2, 1, do_fastboot, + "fastboot- use USB Fastboot protocol\n", + "[inactive timeout]\n" + " - Run as a fastboot usb device.\n" + " - The optional inactive timeout is the decimal seconds before\n" + " - the normal console resumes\n" +); + + +/* + * Android style flash utilties */ +void fastboot_flash_add_ptn(fastboot_ptentry *ptn) +{ + if(pcount < MAX_PTN){ + memcpy(ptable + pcount, ptn, sizeof(*ptn)); + pcount++; + } +} + +void fastboot_flash_dump_ptn(void) +{ + unsigned int n; + for(n = 0; n < pcount; n++) { + fastboot_ptentry *ptn = ptable + n; + printf("ptn %d name='%s' start=%d len=%d\n", + n, ptn->name, ptn->start, ptn->length); + } +} + + +fastboot_ptentry *fastboot_flash_find_ptn(const char *name) +{ + unsigned int n; + + for(n = 0; n < pcount; n++) { + /* Make sure a substring is not accepted */ + if (strlen(name) == strlen(ptable[n].name)) + { + if(0 == strcmp(ptable[n].name, name)) + return ptable + n; + } + } + return 0; +} + +fastboot_ptentry *fastboot_flash_get_ptn(unsigned int n) +{ + if(n < pcount) { + return ptable + n; + } else { + return 0; + } +} + +unsigned int fastboot_flash_get_ptn_count(void) +{ + return pcount; +} + + + +#endif /* CONFIG_FASTBOOT */ diff --git a/common/cmd_fat.c b/common/cmd_fat.c index 9576cdf38..6844c103f 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -29,10 +29,50 @@ #include #include #include -#include + +#if (CONFIG_COMMANDS & CFG_CMD_FAT) + +#undef DEBUG + #include +block_dev_desc_t *get_dev (char* ifname, int dev) +{ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + if (strncmp(ifname,"ide",3)==0) { + extern block_dev_desc_t * ide_get_dev(int dev); + return(ide_get_dev(dev)); + } +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + if (strncmp(ifname,"scsi",4)==0) { + extern block_dev_desc_t * scsi_get_dev(int dev); + return(scsi_get_dev(dev)); + } +#endif +#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE)) + if (strncmp(ifname,"usb",3)==0) { + extern block_dev_desc_t * usb_stor_get_dev(int dev); + return(usb_stor_get_dev(dev)); + } +#endif +#if defined(CONFIG_MMC) + if (strncmp(ifname,"mmc",3)==0) { + extern block_dev_desc_t * mmc_get_dev(int dev); + return(mmc_get_dev(dev)); + } +#endif +#if defined(CONFIG_SYSTEMACE) + if (strcmp(ifname,"ace")==0) { + extern block_dev_desc_t * systemace_get_dev(int dev); + return(systemace_get_dev(dev)); + } +#endif + return NULL; +} + + int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { long size; @@ -318,3 +358,5 @@ void hexdump (int cnt, unsigned char *data) } } #endif /* NOT_IMPLEMENTED_YET */ + +#endif /* CFG_CMD_FAT */ diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c index 8493defe9..03f4ce6d3 100644 --- a/common/cmd_fdc.c +++ b/common/cmd_fdc.c @@ -46,23 +46,24 @@ #define FALSE 0 #endif -/*#if defined(CONFIG_CMD_DATE) */ + +/*#if (CONFIG_COMMANDS & CFG_CMD_DATE) */ /*#include */ /*#endif */ -#if defined(CONFIG_CMD_FDC) || defined(CONFIG_CMD_FDOS) +#if ((CONFIG_COMMANDS & CFG_CMD_FDC) || (CONFIG_COMMANDS & CFG_CMD_FDOS)) + typedef struct { - int flags; /* connected drives ect */ - unsigned long blnr; /* Logical block nr */ - uchar drive; /* drive no */ - uchar cmdlen; /* cmd length */ - uchar cmd[16]; /* cmd desc */ - uchar dma; /* if > 0 dma enabled */ - uchar result[11]; /* status information */ - uchar resultlen; /* lenght of result */ + int flags; /* connected drives ect */ + unsigned long blnr; /* Logical block nr */ + uchar drive; /* drive no */ + uchar cmdlen; /* cmd length */ + uchar cmd[16]; /* cmd desc */ + uchar dma; /* if > 0 dma enabled */ + uchar result[11];/* status information */ + uchar resultlen; /* lenght of result */ } FDC_COMMAND_STRUCT; - /* flags: only the lower 8bit used: * bit 0 if set drive 0 is present * bit 1 if set drive 1 is present @@ -74,30 +75,31 @@ typedef struct { * bit 7 if set disk in drive 4 is inserted */ + /* cmd indexes */ -#define COMMAND 0 -#define DRIVE 1 +#define COMMAND 0 +#define DRIVE 1 #define CONFIG0 1 -#define SPEC_HUTSRT 1 -#define TRACK 2 +#define SPEC_HUTSRT 1 +#define TRACK 2 #define CONFIG1 2 #define SPEC_HLT 2 -#define HEAD 3 +#define HEAD 3 #define CONFIG2 3 -#define SECTOR 4 -#define SECTOR_SIZE 5 -#define LAST_TRACK 6 -#define GAP 7 -#define DTL 8 +#define SECTOR 4 +#define SECTOR_SIZE 5 +#define LAST_TRACK 6 +#define GAP 7 +#define DTL 8 /* result indexes */ -#define STATUS_0 0 -#define STATUS_PCN 1 -#define STATUS_1 1 -#define STATUS_2 2 -#define STATUS_TRACK 3 -#define STATUS_HEAD 4 -#define STATUS_SECT 5 -#define STATUS_SECT_SIZE 6 +#define STATUS_0 0 +#define STATUS_PCN 1 +#define STATUS_1 1 +#define STATUS_2 2 +#define STATUS_TRACK 3 +#define STATUS_HEAD 4 +#define STATUS_SECT 5 +#define STATUS_SECT_SIZE 6 /* Register addresses */ @@ -112,34 +114,34 @@ typedef struct { #define FDC_DIR FDC_BASE + 6 /* Digital Input Register */ #define FDC_CCR FDC_BASE + 7 /* Configuration Control */ /* Commands */ -#define FDC_CMD_SENSE_INT 0x08 -#define FDC_CMD_CONFIGURE 0x13 -#define FDC_CMD_SPECIFY 0x03 -#define FDC_CMD_RECALIBRATE 0x07 -#define FDC_CMD_READ 0x06 -#define FDC_CMD_READ_TRACK 0x02 -#define FDC_CMD_READ_ID 0x0A -#define FDC_CMD_DUMP_REG 0x0E -#define FDC_CMD_SEEK 0x0F +#define FDC_CMD_SENSE_INT 0x08 +#define FDC_CMD_CONFIGURE 0x13 +#define FDC_CMD_SPECIFY 0x03 +#define FDC_CMD_RECALIBRATE 0x07 +#define FDC_CMD_READ 0x06 +#define FDC_CMD_READ_TRACK 0x02 +#define FDC_CMD_READ_ID 0x0A +#define FDC_CMD_DUMP_REG 0x0E +#define FDC_CMD_SEEK 0x0F -#define FDC_CMD_SENSE_INT_LEN 0x01 -#define FDC_CMD_CONFIGURE_LEN 0x04 -#define FDC_CMD_SPECIFY_LEN 0x03 -#define FDC_CMD_RECALIBRATE_LEN 0x02 -#define FDC_CMD_READ_LEN 0x09 -#define FDC_CMD_READ_TRACK_LEN 0x09 -#define FDC_CMD_READ_ID_LEN 0x02 -#define FDC_CMD_DUMP_REG_LEN 0x01 -#define FDC_CMD_SEEK_LEN 0x03 +#define FDC_CMD_SENSE_INT_LEN 0x01 +#define FDC_CMD_CONFIGURE_LEN 0x04 +#define FDC_CMD_SPECIFY_LEN 0x03 +#define FDC_CMD_RECALIBRATE_LEN 0x02 +#define FDC_CMD_READ_LEN 0x09 +#define FDC_CMD_READ_TRACK_LEN 0x09 +#define FDC_CMD_READ_ID_LEN 0x02 +#define FDC_CMD_DUMP_REG_LEN 0x01 +#define FDC_CMD_SEEK_LEN 0x03 -#define FDC_FIFO_THR 0x0C -#define FDC_FIFO_DIS 0x00 +#define FDC_FIFO_THR 0x0C +#define FDC_FIFO_DIS 0x00 #define FDC_IMPLIED_SEEK 0x01 -#define FDC_POLL_DIS 0x00 -#define FDC_PRE_TRK 0x00 -#define FDC_CONFIGURE FDC_FIFO_THR | (FDC_POLL_DIS<<4) | (FDC_FIFO_DIS<<5) | (FDC_IMPLIED_SEEK << 6) -#define FDC_MFM_MODE 0x01 /* MFM enable */ -#define FDC_SKIP_MODE 0x00 /* skip enable */ +#define FDC_POLL_DIS 0x00 +#define FDC_PRE_TRK 0x00 +#define FDC_CONFIGURE FDC_FIFO_THR | (FDC_POLL_DIS<<4) | (FDC_FIFO_DIS<<5) | (FDC_IMPLIED_SEEK << 6) +#define FDC_MFM_MODE 0x01 /* MFM enable */ +#define FDC_SKIP_MODE 0x00 /* skip enable */ #define FDC_TIME_OUT 100000 /* time out */ #define FDC_RW_RETRIES 3 /* read write retries */ @@ -148,18 +150,18 @@ typedef struct { /* Disk structure */ typedef struct { - unsigned int size; /* nr of sectors total */ - unsigned int sect; /* sectors per track */ - unsigned int head; /* nr of heads */ - unsigned int track; /* nr of tracks */ - unsigned int stretch; /* !=0 means double track steps */ - unsigned char gap; /* gap1 size */ - unsigned char rate; /* data rate. |= 0x40 for perpendicular */ - unsigned char spec1; /* stepping rate, head unload time */ - unsigned char fmt_gap;/* gap2 size */ - unsigned char hlt; /* head load time */ - unsigned char sect_code;/* Sector Size code */ - const char * name; /* used only for predefined formats */ + unsigned int size; /* nr of sectors total */ + unsigned int sect; /* sectors per track */ + unsigned int head; /* nr of heads */ + unsigned int track; /* nr of tracks */ + unsigned int stretch; /* !=0 means double track steps */ + unsigned char gap; /* gap1 size */ + unsigned char rate; /* data rate. |= 0x40 for perpendicular */ + unsigned char spec1; /* stepping rate, head unload time */ + unsigned char fmt_gap; /* gap2 size */ + unsigned char hlt; /* head load time */ + unsigned char sect_code; /* Sector Size code */ + const char * name; /* used only for predefined formats */ } FD_GEO_STRUCT; @@ -340,7 +342,7 @@ int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG) case FDC_CMD_CONFIGURE: pCMD->cmd[CONFIG0]=0; pCMD->cmd[CONFIG1]=FDC_CONFIGURE; /* FIFO Threshold, Poll, Enable FIFO */ - pCMD->cmd[CONFIG2]=FDC_PRE_TRK; /* Precompensation Track */ + pCMD->cmd[CONFIG2]=FDC_PRE_TRK; /* Precompensation Track */ pCMD->cmdlen=FDC_CMD_CONFIGURE_LEN; pCMD->resultlen=0; /* no result */ break; @@ -512,7 +514,7 @@ int fdc_read_data(unsigned char *buffer, unsigned long blocks,FDC_COMMAND_STRUCT if(readblk>blocks) /* is end within 1st track */ readblk=blocks; /* yes, correct it */ PRINTF("we read %ld blocks start %ld\n",readblk,pCMD->blnr); - bufferw = &buffer[0]; /* setup working buffer */ + bufferw=&buffer[0]; /* setup working buffer */ do { retryrw: len=sect_size * readblk; @@ -566,7 +568,7 @@ retryrw: * we need to get the results */ fdc_terminate(pCMD); offset+=(sect_size*readblk); /* set up buffer pointer */ - bufferw = &buffer[offset]; + bufferw=&buffer[offset]; pCMD->blnr+=readblk; /* update current block nr */ blocks-=readblk; /* update blocks */ if(blocks==0) @@ -705,9 +707,9 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) return TRUE; } -#endif +#endif /* ((CONFIG_COMMANDS & CFG_CMD_FDC)||(CONFIG_COMMANDS & CFG_CMD_FDOS))*/ -#if defined(CONFIG_CMD_FDOS) +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) /* Low level functions for the Floppy-DOS layer */ @@ -770,9 +772,9 @@ int fdc_fdos_read (void *buffer, int len) return (fdc_read_data (buffer, len, pCMD, pFG)); } -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_FDOS) */ -#if defined(CONFIG_CMD_FDC) +#if (CONFIG_COMMANDS & CFG_CMD_FDC) /**************************************************************************** * main routine do_fdcboot */ @@ -786,9 +788,6 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int i,nrofblk; char *ep; int rcode = 0; -#if defined(CONFIG_FIT) - const void *fit_hdr = NULL; -#endif switch (argc) { case 1: @@ -836,27 +835,14 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("result%d: 0x%02X\n",i,pCMD->result[i]); return 1; } - - switch (genimg_get_format ((void *)addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *)addr; - image_print_contents (hdr); - - imsize = image_get_image_size (hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (const void *)addr; - puts ("Fit image detected...\n"); - - imsize = fit_get_size (fit_hdr); - break; -#endif - default: - puts ("** Unknown image type\n"); + hdr = (image_header_t *)addr; + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + printf ("Bad Magic Number\n"); return 1; } + print_image_hdr(hdr); + imsize= ntohl(hdr->ih_size)+sizeof(image_header_t); nrofblk=imsize/512; if((imsize%512)>0) nrofblk++; @@ -872,45 +858,35 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("OK %ld Bytes loaded.\n",imsize); flush_cache (addr, imsize); - -#if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { - if (!fit_check_format (fit_hdr)) { - puts ("** Bad FIT image format\n"); - return 1; - } - fit_print_contents (fit_hdr); - } -#endif - /* Loading ok, update default load address */ + load_addr = addr; + if(hdr->ih_type == IH_TYPE_KERNEL) { + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { + char *local_args[2]; + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); - /* Check if we should attempt an auto-start */ - if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) { - char *local_args[2]; - extern int do_bootm (cmd_tbl_t *, int, int, char *[]); + local_args[0] = argv[0]; + local_args[1] = NULL; - local_args[0] = argv[0]; - local_args[1] = NULL; + printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); - printf ("Automatic boot of image at addr 0x%08lX ...\n", addr); - - do_bootm (cmdtp, 0, 1, local_args); - rcode ++; + do_bootm (cmdtp, 0, 1, local_args); + rcode ++; + } } return rcode; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_FDC */ /***************************************************/ -#if defined(CONFIG_CMD_FDC) +#if (CONFIG_COMMANDS & CFG_CMD_FDC) U_BOOT_CMD( fdcboot, 3, 1, do_fdcboot, diff --git a/common/cmd_fdos.c b/common/cmd_fdos.c index b3dbd19fa..dc02b3595 100644 --- a/common/cmd_fdos.c +++ b/common/cmd_fdos.c @@ -31,6 +31,8 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) + /*----------------------------------------------------------------------------- * do_fdosboot -- *----------------------------------------------------------------------------- @@ -151,3 +153,5 @@ U_BOOT_CMD( "fdosls - list files in a directory\n", "[directory]\n" ); + +#endif /* CONFIG_COMMANDS & CFG_CMD_FDOS */ diff --git a/common/cmd_flash.c b/common/cmd_flash.c index 18d2250f3..cb1c5bb43 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -31,7 +31,9 @@ #include #endif -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) #include /* parition handling routines */ @@ -41,7 +43,6 @@ int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part); #endif -#ifndef CFG_NO_FLASH extern flash_info_t flash_info[]; /* info for FLASH chips */ /* @@ -210,7 +211,7 @@ flash_fill_sect_ranges (ulong addr_first, ulong addr_last, s_last [bank] = -1; /* last sector to erase */ } - for (bank=0,info = &flash_info[0]; + for (bank=0,info=&flash_info[0]; (bank < CFG_MAX_FLASH_BANKS) && (addr_first <= addr_last); ++bank, ++info) { ulong b_end; @@ -276,19 +277,15 @@ flash_fill_sect_ranges (ulong addr_first, ulong addr_last, return rcode; } -#endif /* CFG_NO_FLASH */ int do_flinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#ifndef CFG_NO_FLASH ulong bank; -#endif #ifdef CONFIG_HAS_DATAFLASH dataflash_print_info(); #endif -#ifndef CFG_NO_FLASH if (argc == 1) { /* print info for all FLASH banks */ for (bank=0; bank - erase partition */ if ((argc == 2) && (id_parse(argv[1], NULL, &dev_type, &dev_num) == 0)) { mtdparts_init(); @@ -360,7 +355,7 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr_last = addr_first + part->size - 1; printf ("Erase Flash Parition %s, " - "bank %ld, 0x%08lx - 0x%08lx ", + "bank %d, 0x%08lx - 0x%08lx ", argv[1], bank, addr_first, addr_last); @@ -404,12 +399,8 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) rcode = flash_sect_erase(addr_first, addr_last); return rcode; -#else - return 0; -#endif /* CFG_NO_FLASH */ } -#ifndef CFG_NO_FLASH int flash_sect_erase (ulong addr_first, ulong addr_last) { flash_info_t *info; @@ -427,7 +418,7 @@ int flash_sect_erase (ulong addr_first, ulong addr_last) s_first, s_last, &planned ); if (planned && (rcode == 0)) { - for (bank=0,info = &flash_info[0]; + for (bank=0,info=&flash_info[0]; (bank < CFG_MAX_FLASH_BANKS) && (rcode == 0); ++bank, ++info) { if (s_first[bank]>=0) { @@ -450,18 +441,13 @@ int flash_sect_erase (ulong addr_first, ulong addr_last) } return rcode; } -#endif /* CFG_NO_FLASH */ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#ifndef CFG_NO_FLASH flash_info_t *info; - ulong bank; - int i, n, sect_first, sect_last; -#endif /* CFG_NO_FLASH */ - ulong addr_first, addr_last; - int p; -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) + ulong bank, addr_first, addr_last; + int i, p, n, sect_first, sect_last; +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) struct mtd_device *dev; struct part_info *part; u8 dev_type, dev_num, pnum; @@ -503,7 +489,6 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #endif -#ifndef CFG_NO_FLASH if (strcmp(argv[2], "all") == 0) { for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) { info = &flash_info[bank-1]; @@ -534,7 +519,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("Bad sector specification\n"); return 1; } - printf("%sProtect Flash Sectors %d-%d in Bank # %zu\n", + printf("%sProtect Flash Sectors %d-%d in Bank # %d\n", p ? "" : "Un-", sect_first, sect_last, (info-flash_info)+1); for (i = sect_first; i <= sect_last; i++) { @@ -554,7 +539,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return rcode; } -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) /* protect on/off */ if ((argc == 3) && (id_parse(argv[2], NULL, &dev_type, &dev_num) == 0)) { mtdparts_init(); @@ -566,7 +551,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr_last = addr_first + part->size - 1; printf ("%sProtect Flash Parition %s, " - "bank %ld, 0x%08lx - 0x%08lx\n", + "bank %d, 0x%08lx - 0x%08lx\n", p ? "" : "Un", argv[1], bank, addr_first, addr_last); @@ -628,11 +613,10 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } rcode = flash_sect_protect (p, addr_first, addr_last); -#endif /* CFG_NO_FLASH */ return rcode; } -#ifndef CFG_NO_FLASH + int flash_sect_protect (int p, ulong addr_first, ulong addr_last) { flash_info_t *info; @@ -651,7 +635,7 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last) protected = 0; if (planned && (rcode == 0)) { - for (bank=0,info = &flash_info[0]; bank < CFG_MAX_FLASH_BANKS; ++bank, ++info) { + for (bank=0,info=&flash_info[0]; bank < CFG_MAX_FLASH_BANKS; ++bank, ++info) { if (info->flash_id == FLASH_UNKNOWN) { continue; } @@ -685,11 +669,10 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last) } return rcode; } -#endif /* CFG_NO_FLASH */ /**************************************************/ -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) # define TMP_ERASE "erase \n - erase partition\n" # define TMP_PROT_ON "protect on \n - protect partition\n" # define TMP_PROT_OFF "protect off \n - make partition writable\n" @@ -707,7 +690,7 @@ U_BOOT_CMD( ); U_BOOT_CMD( - erase, 3, 0, do_flerase, + erase, 3, 1, do_flerase, "erase - erase FLASH memory\n", "start end\n" " - erase FLASH from addr 'start' to addr 'end'\n" @@ -721,7 +704,7 @@ U_BOOT_CMD( ); U_BOOT_CMD( - protect, 4, 0, do_protect, + protect, 4, 1, do_protect, "protect - enable or disable FLASH write protection\n", "on start end\n" " - protect FLASH from addr 'start' to addr 'end'\n" @@ -748,3 +731,5 @@ U_BOOT_CMD( #undef TMP_ERASE #undef TMP_PROT_ON #undef TMP_PROT_OFF + +#endif /* CFG_CMD_FLASH */ diff --git a/common/cmd_flipflop.c b/common/cmd_flipflop.c new file mode 100644 index 000000000..9424853db --- /dev/null +++ b/common/cmd_flipflop.c @@ -0,0 +1,84 @@ +/* + * Command to set/activate the flipflop fail flags. + * + * Copyright (C) 2010 TomTom International B.V. + * + ************************************************************************ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + ************************************************************************ + */ + +#include +#include +#include +#include + +#if defined(CONFIG_CMD_FLIPFLOP) + + +static int do_flipflop (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc != 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (strcmp(argv[1], "0") == 0) { + flipflop_set(0); + debug("set flipflop 0\n"); + } else { + flipflop_set(1); /* set boot fail flag */ + debug("set flipflop 1\n"); + } + + return 0; +} + +U_BOOT_CMD( + flipflop, 2, 0, do_flipflop, + "flipflop- [de]activate boot fail flag\n", + "flipflop [ 1 | 0 ]\n" + " - activate or deactivate boot fail flag\n" +); + + +#ifndef __NON_LEGACY +static int do_getbootfail (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc != 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (flipflop_get()) { + setenv (argv[1], "fail"); + } else { + setenv (argv[1], "pass"); + } + + return 0; +} + +U_BOOT_CMD( + getbootfail, 2, 0, do_getbootfail, + "getbootfail- return boot fail status\n", + "getbootfail \n" + " - return boot fail status ('fail' or 'pass') in 'name'\n" +); +#endif /* __NON_LEGACY */ + +#endif /* CONFIG_CMD_FLIPFLOP */ + diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index dcbbc993d..9a01e7df8 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -27,7 +27,7 @@ */ #include #include -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) #include #endif #include @@ -43,6 +43,8 @@ #define PRINTF(fmt,args...) #endif +#if defined (CONFIG_FPGA) && ( CONFIG_COMMANDS & CFG_CMD_FPGA ) + /* Local functions */ static void fpga_usage (cmd_tbl_t * cmdtp); static int fpga_get_op (char *opstr); @@ -53,21 +55,23 @@ static int fpga_get_op (char *opstr); #define FPGA_LOAD 1 #define FPGA_LOADB 2 #define FPGA_DUMP 3 -#define FPGA_LOADMK 4 /* Convert bitstream data and load into the fpga */ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) { -#if defined(CONFIG_FPGA_XILINX) unsigned int length; + unsigned char* swapdata; unsigned int swapsize; char buffer[80]; + unsigned char *ptr; unsigned char *dataptr; + unsigned char data; unsigned int i; int rc; dataptr = (unsigned char *)fpgadata; +#if CFG_FPGA_XILINX /* skip the first bytes of the bitsteam, their meaning is unknown */ length = (*dataptr << 8) + *(dataptr+1); dataptr+=2; @@ -85,7 +89,7 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) length = (*dataptr << 8) + *(dataptr+1); dataptr+=2; for(i=0;i= size) { + printf("%s: Could not find right length of data in bitstream\n", + __FUNCTION__); + return FPGA_FAIL; + } + + /* allocate memory */ + swapdata = (unsigned char *)malloc(swapsize); + if (swapdata == NULL) { + printf("%s: Could not allocate %d bytes memory !\n", + __FUNCTION__, swapsize); + return FPGA_FAIL; + } + + /* read data into memory and swap bits */ + ptr = swapdata; + for (i = 0; i < swapsize; i++) { + data = 0x00; + data |= (*dataptr & 0x01) << 7; + data |= (*dataptr & 0x02) << 5; + data |= (*dataptr & 0x04) << 3; + data |= (*dataptr & 0x08) << 1; + data |= (*dataptr & 0x10) >> 1; + data |= (*dataptr & 0x20) >> 3; + data |= (*dataptr & 0x40) >> 5; + data |= (*dataptr & 0x80) >> 7; + *ptr++ = data; + dataptr++; + } + + rc = fpga_load(dev, swapdata, swapsize); + free(swapdata); return rc; #else printf("Bitstream support only for Xilinx devices\n"); @@ -164,10 +200,6 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) char *devstr = getenv ("fpga"); char *datastr = getenv ("fpgadata"); int rc = FPGA_FAIL; -#if defined (CONFIG_FIT) - const char *fit_uname = NULL; - ulong fit_addr; -#endif if (devstr) dev = (int) simple_strtoul (devstr, NULL, 16); @@ -177,22 +209,9 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) switch (argc) { case 5: /* fpga */ data_size = simple_strtoul (argv[4], NULL, 16); - case 4: /* fpga */ -#if defined(CONFIG_FIT) - if (fit_parse_subimage (argv[3], (ulong)fpga_data, - &fit_addr, &fit_uname)) { - fpga_data = (void *)fit_addr; - debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n", - fit_uname, fit_addr); - } else -#endif - { - fpga_data = (void *) simple_strtoul (argv[3], NULL, 16); - debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data); - } + fpga_data = (void *) simple_strtoul (argv[3], NULL, 16); PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data); - case 3: /* fpga */ dev = (int) simple_strtoul (argv[2], NULL, 16); PRINTF ("%s: device = %d\n", __FUNCTION__, dev); @@ -200,29 +219,14 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */ PRINTF ("%s: Assuming buffer pointer in arg 3\n", __FUNCTION__); - -#if defined(CONFIG_FIT) - if (fit_parse_subimage (argv[2], (ulong)fpga_data, - &fit_addr, &fit_uname)) { - fpga_data = (void *)fit_addr; - debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n", - fit_uname, fit_addr); - } else -#endif - { - fpga_data = (void *) dev; - debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data); - } - + fpga_data = (void *) dev; PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data); dev = FPGA_INVALID_DEVICE; /* reset device num */ } - case 2: /* fpga */ op = (int) fpga_get_op (argv[1]); break; - default: PRINTF ("%s: Too many or too few args (%d)\n", __FUNCTION__, argc); @@ -247,65 +251,6 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) rc = fpga_loadbitstream(dev, fpga_data, data_size); break; - case FPGA_LOADMK: - switch (genimg_get_format (fpga_data)) { - case IMAGE_FORMAT_LEGACY: - { - image_header_t *hdr = (image_header_t *)fpga_data; - ulong data; - - data = (ulong)image_get_data (hdr); - data_size = image_get_data_size (hdr); - rc = fpga_load (dev, (void *)data, data_size); - } - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - { - const void *fit_hdr = (const void *)fpga_data; - int noffset; - void *fit_data; - - if (fit_uname == NULL) { - puts ("No FIT subimage unit name\n"); - return 1; - } - - if (!fit_check_format (fit_hdr)) { - puts ("Bad FIT image format\n"); - return 1; - } - - /* get fpga component image node offset */ - noffset = fit_image_get_node (fit_hdr, fit_uname); - if (noffset < 0) { - printf ("Can't find '%s' FIT subimage\n", fit_uname); - return 1; - } - - /* verify integrity */ - if (!fit_image_check_hashes (fit_hdr, noffset)) { - puts ("Bad Data Hash\n"); - return 1; - } - - /* get fpga subimage data address and length */ - if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) { - puts ("Could not find fpga subimage data\n"); - return 1; - } - - rc = fpga_load (dev, fit_data, data_size); - } - break; -#endif - default: - puts ("** Unknown image type\n"); - rc = FPGA_FAIL; - break; - } - break; - case FPGA_DUMP: rc = fpga_dump (dev, fpga_data, data_size); break; @@ -337,8 +282,6 @@ static int fpga_get_op (char *opstr) op = FPGA_LOADB; } else if (!strcmp ("load", opstr)) { op = FPGA_LOAD; - } else if (!strcmp ("loadmk", opstr)) { - op = FPGA_LOADMK; } else if (!strcmp ("dump", opstr)) { op = FPGA_DUMP; } @@ -356,10 +299,5 @@ U_BOOT_CMD (fpga, 6, 1, do_fpga, "\tinfo\tlist known device information\n" "\tload\tLoad device from memory buffer\n" "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n" - "\tloadmk\tLoad device generated with mkimage\n" - "\tdump\tLoad device to memory buffer\n" -#if defined(CONFIG_FIT) - "\tFor loadmk operating on FIT format uImage address must include\n" - "\tsubimage unit name in the form of addr:\n" -#endif -); + "\tdump\tLoad device to memory buffer\n"); +#endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */ diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index aac7e9a6c..ca553d171 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -86,6 +86,9 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_I2C) + + /* Display values from last command. * Memory modify remembered values are different from display memory. */ @@ -98,33 +101,12 @@ static uchar i2c_mm_last_chip; static uint i2c_mm_last_addr; static uint i2c_mm_last_alen; -/* If only one I2C bus is present, the list of devices to ignore when - * the probe command is issued is represented by a 1D array of addresses. - * When multiple buses are present, the list is an array of bus-address - * pairs. The following macros take care of this */ - #if defined(CFG_I2C_NOPROBES) -#if defined(CONFIG_I2C_MULTI_BUS) -static struct -{ - uchar bus; - uchar addr; -} i2c_no_probes[] = CFG_I2C_NOPROBES; -#define GET_BUS_NUM i2c_get_bus_num() -#define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b)) -#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a)) -#define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr -#else /* single bus */ static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; -#define GET_BUS_NUM 0 -#define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */ -#define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a)) -#define NO_PROBE_ADDR(i) i2c_no_probes[(i)] -#endif /* CONFIG_MULTI_BUS */ - -#define NUM_ELEMENTS_NOPROBE (sizeof(i2c_no_probes)/sizeof(i2c_no_probes[0])) #endif +int select_bus(int, int); + static int mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]); extern int cmd_get_data_size(char* arg, int default_size); @@ -171,7 +153,7 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = 1; - for (j = 0; j < 8; j++) { + for(j = 0; j < 8; j++) { if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; if (alen > 4) { @@ -179,8 +161,9 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } break; - } else if (argv[2][j] == '\0') + } else if (argv[2][j] == '\0') { break; + } } /* @@ -204,9 +187,9 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; - if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0) + if(i2c_read(chip, addr, alen, linebuf, linebytes) != 0) { puts ("Error reading the chip.\n"); - else { + } else { printf("%04x:", addr); cp = linebuf; for (j=0; j 4) { + if(alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') + } else if (argv[2][j] == '\0') { break; + } } /* @@ -295,14 +279,16 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Optional count */ - if (argc == 5) + if(argc == 5) { count = simple_strtoul(argv[4], NULL, 16); - else + } else { count = 1; + } while (count-- > 0) { - if (i2c_write(chip, addr++, alen, &byte, 1) != 0) + if(i2c_write(chip, addr++, alen, &byte, 1) != 0) { puts ("Error writing the chip.\n"); + } /* * Wait for the write to complete. The write can take * up to 10mSec (we allow a little more time). @@ -319,9 +305,9 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif #if 0 - for (timeout = 0; timeout < 10; timeout++) { + for(timeout = 0; timeout < 10; timeout++) { udelay(2000); - if (i2c_probe(chip) == 0) + if(i2c_probe(chip) == 0) break; } #endif @@ -353,8 +339,8 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } /* - * Chip is always specified. - */ + * Chip is always specified. + */ chip = simple_strtoul(argv[1], NULL, 16); /* @@ -362,16 +348,17 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = 1; - for (j = 0; j < 8; j++) { + for(j = 0; j < 8; j++) { if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; - if (alen > 4) { + if(alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') + } else if (argv[2][j] == '\0') { break; + } } /* @@ -386,16 +373,19 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ crc = 0; err = 0; - while (count-- > 0) { - if (i2c_read(chip, addr, alen, &byte, 1) != 0) + while(count-- > 0) { + if(i2c_read(chip, addr, alen, &byte, 1) != 0) { err++; + } crc = crc32 (crc, &byte, 1); addr++; } - if (err > 0) + if(err > 0) + { puts ("Error reading the chip,\n"); - else + } else { printf ("%08lx\n", crc); + } return 0; } @@ -444,8 +434,8 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) size = cmd_get_data_size(argv[0], 1); /* - * Chip is always specified. - */ + * Chip is always specified. + */ chip = simple_strtoul(argv[1], NULL, 16); /* @@ -453,16 +443,17 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = 1; - for (j = 0; j < 8; j++) { + for(j = 0; j < 8; j++) { if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; - if (alen > 4) { + if(alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; - } else if (argv[2][j] == '\0') + } else if (argv[2][j] == '\0') { break; + } } } @@ -472,16 +463,17 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) */ do { printf("%08lx:", addr); - if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) + if(i2c_read(chip, addr, alen, (uchar *)&data, size) != 0) { puts ("\nError reading the chip,\n"); - else { + } else { data = cpu_to_be32(data); - if (size == 1) + if(size == 1) { printf(" %02lx", (data >> 24) & 0x000000FF); - else if (size == 2) + } else if(size == 2) { printf(" %04lx", (data >> 16) & 0x0000FFFF); - else + } else { printf(" %08lx", data); + } } nbytes = readline (" ? "); @@ -498,17 +490,19 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) #endif } #ifdef CONFIG_BOOT_RETRY_TIME - else if (nbytes == -2) + else if (nbytes == -2) { break; /* timed out, exit the command */ + } #endif else { char *endp; data = simple_strtoul(console_buffer, &endp, 16); - if (size == 1) + if(size == 1) { data = data << 24; - else if (size == 2) + } else if(size == 2) { data = data << 16; + } data = be32_to_cpu(data); nbytes = endp - console_buffer; if (nbytes) { @@ -518,8 +512,9 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) */ reset_cmd_timeout(); #endif - if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) + if(i2c_write(chip, addr, alen, (uchar *)&data, size) != 0) { puts ("Error writing the chip.\n"); + } #ifdef CFG_EEPROM_PAGE_WRITE_DELAY_MS udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif @@ -545,15 +540,14 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int j; #if defined(CFG_I2C_NOPROBES) int k, skip; - uchar bus = GET_BUS_NUM; -#endif /* NOPROBES */ +#endif puts ("Valid chip addresses:"); - for (j = 0; j < 128; j++) { + for(j = 0; j < 128; j++) { #if defined(CFG_I2C_NOPROBES) skip = 0; - for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { - if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) { + for (k = 0; k < sizeof(i2c_no_probes); k++){ + if (j == i2c_no_probes[k]){ skip = 1; break; } @@ -561,17 +555,16 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (skip) continue; #endif - if (i2c_probe(j) == 0) + if(i2c_probe(j) == 0) { printf(" %02X", j); + } } putc ('\n'); #if defined(CFG_I2C_NOPROBES) puts ("Excluded chip addresses:"); - for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) { - if (COMPARE_BUS(bus,k)) - printf(" %02X", NO_PROBE_ADDR(k)); - } + for( k = 0; k < sizeof(i2c_no_probes); k++ ) + printf(" %02X", i2c_no_probes[k] ); putc ('\n'); #endif @@ -610,7 +603,7 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = 1; - for (j = 0; j < 8; j++) { + for(j = 0; j < 8; j++) { if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; if (alen > 4) { @@ -618,8 +611,9 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } break; - } else if (argv[2][j] == '\0') + } else if (argv[2][j] == '\0') { break; + } } /* @@ -627,21 +621,24 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ length = 1; length = simple_strtoul(argv[3], NULL, 16); - if (length > sizeof(bytes)) + if(length > sizeof(bytes)) { length = sizeof(bytes); + } /* * The delay time (uSec) is optional. */ delay = 1000; - if (argc > 3) + if (argc > 3) { delay = simple_strtoul(argv[4], NULL, 10); + } /* * Run the loop... */ - while (1) { - if (i2c_read(chip, addr, alen, bytes, length) != 0) + while(1) { + if(i2c_read(chip, addr, alen, bytes, length) != 0) { puts ("Error reading the chip.\n"); + } udelay(delay); } @@ -654,121 +651,29 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * The SDRAM command is separately configured because many * (most?) embedded boards don't use SDRAM DIMMs. */ -#if defined(CONFIG_CMD_SDRAM) -static void print_ddr2_tcyc (u_char const b) -{ - printf ("%d.", (b >> 4) & 0x0F); - switch (b & 0x0F) { - case 0x0: - case 0x1: - case 0x2: - case 0x3: - case 0x4: - case 0x5: - case 0x6: - case 0x7: - case 0x8: - case 0x9: - printf ("%d ns\n", b & 0x0F); - break; - case 0xA: - puts ("25 ns\n"); - break; - case 0xB: - puts ("33 ns\n"); - break; - case 0xC: - puts ("66 ns\n"); - break; - case 0xD: - puts ("75 ns\n"); - break; - default: - puts ("?? ns\n"); - break; - } -} - -static void decode_bits (u_char const b, char const *str[], int const do_once) -{ - u_char mask; - - for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) { - if (b & mask) { - puts (*str); - if (do_once) - return; - } - } -} +#if (CONFIG_COMMANDS & CFG_CMD_SDRAM) /* * Syntax: * sdram {i2c_chip} */ -int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - enum { unknown, EDO, SDRAM, DDR2 } type; - u_char chip; u_char data[128]; u_char cksum; int j; - static const char *decode_CAS_DDR2[] = { - " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD" - }; - - static const char *decode_CAS_default[] = { - " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1" - }; - - static const char *decode_CS_WE_default[] = { - " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0" - }; - - static const char *decode_byte21_default[] = { - " TBD (bit 7)\n", - " Redundant row address\n", - " Differential clock input\n", - " Registerd DQMB inputs\n", - " Buffered DQMB inputs\n", - " On-card PLL\n", - " Registered address/control lines\n", - " Buffered address/control lines\n" - }; - - static const char *decode_byte22_DDR2[] = { - " TBD (bit 7)\n", - " TBD (bit 6)\n", - " TBD (bit 5)\n", - " TBD (bit 4)\n", - " TBD (bit 3)\n", - " Supports partial array self refresh\n", - " Supports 50 ohm ODT\n", - " Supports weak driver\n" - }; - - static const char *decode_row_density_DDR2[] = { - "512 MiB", "256 MiB", "128 MiB", "16 GiB", - "8 GiB", "4 GiB", "2 GiB", "1 GiB" - }; - - static const char *decode_row_density_default[] = { - "512 MiB", "256 MiB", "128 MiB", "64 MiB", - "32 MiB", "16 MiB", "8 MiB", "4 MiB" - }; - if (argc < 2) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } /* * Chip is always specified. - */ - chip = simple_strtoul (argv[1], NULL, 16); + */ + chip = simple_strtoul(argv[1], NULL, 16); - if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) { + if(i2c_read(chip, 0, 1, data, sizeof(data)) != 0) { puts ("No SDRAM Serial Presence Detect found.\n"); return 1; } @@ -777,159 +682,84 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) for (j = 0; j < 63; j++) { cksum += data[j]; } - if (cksum != data[63]) { + if(cksum != data[63]) { printf ("WARNING: Configuration data checksum failure:\n" - " is 0x%02x, calculated 0x%02x\n", data[63], cksum); + " is 0x%02x, calculated 0x%02x\n", + data[63], cksum); } - printf ("SPD data revision %d.%d\n", + printf("SPD data revision %d.%d\n", (data[62] >> 4) & 0x0F, data[62] & 0x0F); - printf ("Bytes used 0x%02X\n", data[0]); - printf ("Serial memory size 0x%02X\n", 1 << data[1]); - + printf("Bytes used 0x%02X\n", data[0]); + printf("Serial memory size 0x%02X\n", 1 << data[1]); puts ("Memory type "); - switch (data[2]) { - case 2: - type = EDO; - puts ("EDO\n"); - break; - case 4: - type = SDRAM; - puts ("SDRAM\n"); - break; - case 8: - type = DDR2; - puts ("DDR2\n"); - break; - default: - type = unknown; - puts ("unknown\n"); - break; - } - - puts ("Row address bits "); - if ((data[3] & 0x00F0) == 0) - printf ("%d\n", data[3] & 0x0F); - else - printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F); - - puts ("Column address bits "); - if ((data[4] & 0x00F0) == 0) - printf ("%d\n", data[4] & 0x0F); - else - printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F); - - switch (type) { - case DDR2: - printf ("Number of ranks %d\n", - (data[5] & 0x07) + 1); - break; - default: - printf ("Module rows %d\n", data[5]); - break; - } - - switch (type) { - case DDR2: - printf ("Module data width %d bits\n", data[6]); - break; - default: - printf ("Module data width %d bits\n", - (data[7] << 8) | data[6]); - break; - } - - puts ("Interface signal levels "); - switch(data[8]) { - case 0: puts ("TTL 5.0 V\n"); break; - case 1: puts ("LVTTL\n"); break; - case 2: puts ("HSTL 1.5 V\n"); break; - case 3: puts ("SSTL 3.3 V\n"); break; - case 4: puts ("SSTL 2.5 V\n"); break; - case 5: puts ("SSTL 1.8 V\n"); break; + switch(data[2]) { + case 2: puts ("EDO\n"); break; + case 4: puts ("SDRAM\n"); break; default: puts ("unknown\n"); break; } - - switch (type) { - case DDR2: - printf ("SDRAM cycle time "); - print_ddr2_tcyc (data[9]); - break; - default: - printf ("SDRAM cycle time %d.%d ns\n", - (data[9] >> 4) & 0x0F, data[9] & 0x0F); - break; + puts ("Row address bits "); + if((data[3] & 0x00F0) == 0) { + printf("%d\n", data[3] & 0x0F); + } else { + printf("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F); } - - switch (type) { - case DDR2: - printf ("SDRAM access time 0.%d%d ns\n", - (data[10] >> 4) & 0x0F, data[10] & 0x0F); - break; - default: - printf ("SDRAM access time %d.%d ns\n", - (data[10] >> 4) & 0x0F, data[10] & 0x0F); - break; + puts ("Column address bits "); + if((data[4] & 0x00F0) == 0) { + printf("%d\n", data[4] & 0x0F); + } else { + printf("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F); } - + printf("Module rows %d\n", data[5]); + printf("Module data width %d bits\n", (data[7] << 8) | data[6]); + puts ("Interface signal levels "); + switch(data[8]) { + case 0: puts ("5.0v/TTL\n"); break; + case 1: puts ("LVTTL\n"); break; + case 2: puts ("HSTL 1.5\n"); break; + case 3: puts ("SSTL 3.3\n"); break; + case 4: puts ("SSTL 2.5\n"); break; + default: puts ("unknown\n"); break; + } + printf("SDRAM cycle time %d.%d nS\n", + (data[9] >> 4) & 0x0F, data[9] & 0x0F); + printf("SDRAM access time %d.%d nS\n", + (data[10] >> 4) & 0x0F, data[10] & 0x0F); puts ("EDC configuration "); - switch (data[11]) { + switch(data[11]) { case 0: puts ("None\n"); break; case 1: puts ("Parity\n"); break; case 2: puts ("ECC\n"); break; default: puts ("unknown\n"); break; } - - if ((data[12] & 0x80) == 0) + if((data[12] & 0x80) == 0) { puts ("No self refresh, rate "); - else + } else { puts ("Self refresh, rate "); - + } switch(data[12] & 0x7F) { - case 0: puts ("15.625 us\n"); break; - case 1: puts ("3.9 us\n"); break; - case 2: puts ("7.8 us\n"); break; - case 3: puts ("31.3 us\n"); break; - case 4: puts ("62.5 us\n"); break; - case 5: puts ("125 us\n"); break; + case 0: puts ("15.625uS\n"); break; + case 1: puts ("3.9uS\n"); break; + case 2: puts ("7.8uS\n"); break; + case 3: puts ("31.3uS\n"); break; + case 4: puts ("62.5uS\n"); break; + case 5: puts ("125uS\n"); break; default: puts ("unknown\n"); break; } - - switch (type) { - case DDR2: - printf ("SDRAM width (primary) %d\n", data[13]); - break; - default: - printf ("SDRAM width (primary) %d\n", data[13] & 0x7F); - if ((data[13] & 0x80) != 0) { - printf (" (second bank) %d\n", - 2 * (data[13] & 0x7F)); + printf("SDRAM width (primary) %d\n", data[13] & 0x7F); + if((data[13] & 0x80) != 0) { + printf(" (second bank) %d\n", + 2 * (data[13] & 0x7F)); + } + if(data[14] != 0) { + printf("EDC width %d\n", + data[14] & 0x7F); + if((data[14] & 0x80) != 0) { + printf(" (second bank) %d\n", + 2 * (data[14] & 0x7F)); } - break; } - - switch (type) { - case DDR2: - if (data[14] != 0) - printf ("EDC width %d\n", data[14]); - break; - default: - if (data[14] != 0) { - printf ("EDC width %d\n", - data[14] & 0x7F); - - if ((data[14] & 0x80) != 0) { - printf (" (second bank) %d\n", - 2 * (data[14] & 0x7F)); - } - } - break; - } - - if (DDR2 != type) { - printf ("Min clock delay, back-to-back random column addresses " - "%d\n", data[15]); - } - + printf("Min clock delay, back-to-back random column addresses %d\n", + data[15]); puts ("Burst length(s) "); if (data[16] & 0x80) puts (" Page"); if (data[16] & 0x08) puts (" 8"); @@ -937,342 +767,137 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (data[16] & 0x02) puts (" 2"); if (data[16] & 0x01) puts (" 1"); putc ('\n'); - printf ("Number of banks %d\n", data[17]); - - switch (type) { - case DDR2: - puts ("CAS latency(s) "); - decode_bits (data[18], decode_CAS_DDR2, 0); - putc ('\n'); - break; - default: - puts ("CAS latency(s) "); - decode_bits (data[18], decode_CAS_default, 0); - putc ('\n'); - break; - } - - if (DDR2 != type) { - puts ("CS latency(s) "); - decode_bits (data[19], decode_CS_WE_default, 0); - putc ('\n'); - } - - if (DDR2 != type) { - puts ("WE latency(s) "); - decode_bits (data[20], decode_CS_WE_default, 0); - putc ('\n'); - } - - switch (type) { - case DDR2: - puts ("Module attributes:\n"); - if (data[21] & 0x80) - puts (" TBD (bit 7)\n"); - if (data[21] & 0x40) - puts (" Analysis probe installed\n"); - if (data[21] & 0x20) - puts (" TBD (bit 5)\n"); - if (data[21] & 0x10) - puts (" FET switch external enable\n"); - printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03); - if (data[20] & 0x11) { - printf (" %d active registers on DIMM\n", - (data[21] & 0x03) + 1); - } - break; - default: - puts ("Module attributes:\n"); - if (!data[21]) - puts (" (none)\n"); - else - decode_bits (data[21], decode_byte21_default, 0); - break; - } - - switch (type) { - case DDR2: - decode_bits (data[22], decode_byte22_DDR2, 0); - break; - default: - puts ("Device attributes:\n"); - if (data[22] & 0x80) puts (" TBD (bit 7)\n"); - if (data[22] & 0x40) puts (" TBD (bit 6)\n"); - if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n"); - else puts (" Upper Vcc tolerance 10%\n"); - if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n"); - else puts (" Lower Vcc tolerance 10%\n"); - if (data[22] & 0x08) puts (" Supports write1/read burst\n"); - if (data[22] & 0x04) puts (" Supports precharge all\n"); - if (data[22] & 0x02) puts (" Supports auto precharge\n"); - if (data[22] & 0x01) puts (" Supports early RAS# precharge\n"); - break; - } - - switch (type) { - case DDR2: - printf ("SDRAM cycle time (2nd highest CAS latency) "); - print_ddr2_tcyc (data[23]); - break; - default: - printf ("SDRAM cycle time (2nd highest CAS latency) %d." - "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F); - break; - } - - switch (type) { - case DDR2: - printf ("SDRAM access from clock (2nd highest CAS latency) 0." - "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); - break; - default: - printf ("SDRAM access from clock (2nd highest CAS latency) %d." - "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); - break; - } - - switch (type) { - case DDR2: - printf ("SDRAM cycle time (3rd highest CAS latency) "); - print_ddr2_tcyc (data[25]); - break; - default: - printf ("SDRAM cycle time (3rd highest CAS latency) %d." - "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F); - break; - } - - switch (type) { - case DDR2: - printf ("SDRAM access from clock (3rd highest CAS latency) 0." - "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); - break; - default: - printf ("SDRAM access from clock (3rd highest CAS latency) %d." - "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); - break; - } - - switch (type) { - case DDR2: - printf ("Minimum row precharge %d.%02d ns\n", - (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03)); - break; - default: - printf ("Minimum row precharge %d ns\n", data[27]); - break; - } - - switch (type) { - case DDR2: - printf ("Row active to row active min %d.%02d ns\n", - (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03)); - break; - default: - printf ("Row active to row active min %d ns\n", data[28]); - break; - } - - switch (type) { - case DDR2: - printf ("RAS to CAS delay min %d.%02d ns\n", - (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03)); - break; - default: - printf ("RAS to CAS delay min %d ns\n", data[29]); - break; - } - - printf ("Minimum RAS pulse width %d ns\n", data[30]); - - switch (type) { - case DDR2: - puts ("Density of each row "); - decode_bits (data[31], decode_row_density_DDR2, 1); - putc ('\n'); - break; - default: - puts ("Density of each row "); - decode_bits (data[31], decode_row_density_default, 1); - putc ('\n'); - break; - } - - switch (type) { - case DDR2: - puts ("Command and Address setup "); - if (data[32] >= 0xA0) { - printf ("1.%d%d ns\n", - ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F); - } else { - printf ("0.%d%d ns\n", - ((data[32] >> 4) & 0x0F), data[32] & 0x0F); - } - break; - default: - printf ("Command and Address setup %c%d.%d ns\n", - (data[32] & 0x80) ? '-' : '+', - (data[32] >> 4) & 0x07, data[32] & 0x0F); - break; - } - - switch (type) { - case DDR2: - puts ("Command and Address hold "); - if (data[33] >= 0xA0) { - printf ("1.%d%d ns\n", - ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F); - } else { - printf ("0.%d%d ns\n", - ((data[33] >> 4) & 0x0F), data[33] & 0x0F); - } - break; - default: - printf ("Command and Address hold %c%d.%d ns\n", - (data[33] & 0x80) ? '-' : '+', - (data[33] >> 4) & 0x07, data[33] & 0x0F); - break; - } - - switch (type) { - case DDR2: - printf ("Data signal input setup 0.%d%d ns\n", - (data[34] >> 4) & 0x0F, data[34] & 0x0F); - break; - default: - printf ("Data signal input setup %c%d.%d ns\n", - (data[34] & 0x80) ? '-' : '+', - (data[34] >> 4) & 0x07, data[34] & 0x0F); - break; - } - - switch (type) { - case DDR2: - printf ("Data signal input hold 0.%d%d ns\n", - (data[35] >> 4) & 0x0F, data[35] & 0x0F); - break; - default: - printf ("Data signal input hold %c%d.%d ns\n", - (data[35] & 0x80) ? '-' : '+', - (data[35] >> 4) & 0x07, data[35] & 0x0F); - break; - } - + printf("Number of banks %d\n", data[17]); + puts ("CAS latency(s) "); + if (data[18] & 0x80) puts (" TBD"); + if (data[18] & 0x40) puts (" 7"); + if (data[18] & 0x20) puts (" 6"); + if (data[18] & 0x10) puts (" 5"); + if (data[18] & 0x08) puts (" 4"); + if (data[18] & 0x04) puts (" 3"); + if (data[18] & 0x02) puts (" 2"); + if (data[18] & 0x01) puts (" 1"); + putc ('\n'); + puts ("CS latency(s) "); + if (data[19] & 0x80) puts (" TBD"); + if (data[19] & 0x40) puts (" 6"); + if (data[19] & 0x20) puts (" 5"); + if (data[19] & 0x10) puts (" 4"); + if (data[19] & 0x08) puts (" 3"); + if (data[19] & 0x04) puts (" 2"); + if (data[19] & 0x02) puts (" 1"); + if (data[19] & 0x01) puts (" 0"); + putc ('\n'); + puts ("WE latency(s) "); + if (data[20] & 0x80) puts (" TBD"); + if (data[20] & 0x40) puts (" 6"); + if (data[20] & 0x20) puts (" 5"); + if (data[20] & 0x10) puts (" 4"); + if (data[20] & 0x08) puts (" 3"); + if (data[20] & 0x04) puts (" 2"); + if (data[20] & 0x02) puts (" 1"); + if (data[20] & 0x01) puts (" 0"); + putc ('\n'); + puts ("Module attributes:\n"); + if (!data[21]) puts (" (none)\n"); + if (data[21] & 0x80) puts (" TBD (bit 7)\n"); + if (data[21] & 0x40) puts (" Redundant row address\n"); + if (data[21] & 0x20) puts (" Differential clock input\n"); + if (data[21] & 0x10) puts (" Registerd DQMB inputs\n"); + if (data[21] & 0x08) puts (" Buffered DQMB inputs\n"); + if (data[21] & 0x04) puts (" On-card PLL\n"); + if (data[21] & 0x02) puts (" Registered address/control lines\n"); + if (data[21] & 0x01) puts (" Buffered address/control lines\n"); + puts ("Device attributes:\n"); + if (data[22] & 0x80) puts (" TBD (bit 7)\n"); + if (data[22] & 0x40) puts (" TBD (bit 6)\n"); + if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n"); + else puts (" Upper Vcc tolerance 10%\n"); + if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n"); + else puts (" Lower Vcc tolerance 10%\n"); + if (data[22] & 0x08) puts (" Supports write1/read burst\n"); + if (data[22] & 0x04) puts (" Supports precharge all\n"); + if (data[22] & 0x02) puts (" Supports auto precharge\n"); + if (data[22] & 0x01) puts (" Supports early RAS# precharge\n"); + printf("SDRAM cycle time (2nd highest CAS latency) %d.%d nS\n", + (data[23] >> 4) & 0x0F, data[23] & 0x0F); + printf("SDRAM access from clock (2nd highest CAS latency) %d.%d nS\n", + (data[24] >> 4) & 0x0F, data[24] & 0x0F); + printf("SDRAM cycle time (3rd highest CAS latency) %d.%d nS\n", + (data[25] >> 4) & 0x0F, data[25] & 0x0F); + printf("SDRAM access from clock (3rd highest CAS latency) %d.%d nS\n", + (data[26] >> 4) & 0x0F, data[26] & 0x0F); + printf("Minimum row precharge %d nS\n", data[27]); + printf("Row active to row active min %d nS\n", data[28]); + printf("RAS to CAS delay min %d nS\n", data[29]); + printf("Minimum RAS pulse width %d nS\n", data[30]); + puts ("Density of each row "); + if (data[31] & 0x80) puts (" 512"); + if (data[31] & 0x40) puts (" 256"); + if (data[31] & 0x20) puts (" 128"); + if (data[31] & 0x10) puts (" 64"); + if (data[31] & 0x08) puts (" 32"); + if (data[31] & 0x04) puts (" 16"); + if (data[31] & 0x02) puts (" 8"); + if (data[31] & 0x01) puts (" 4"); + puts ("MByte\n"); + printf("Command and Address setup %c%d.%d nS\n", + (data[32] & 0x80) ? '-' : '+', + (data[32] >> 4) & 0x07, data[32] & 0x0F); + printf("Command and Address hold %c%d.%d nS\n", + (data[33] & 0x80) ? '-' : '+', + (data[33] >> 4) & 0x07, data[33] & 0x0F); + printf("Data signal input setup %c%d.%d nS\n", + (data[34] & 0x80) ? '-' : '+', + (data[34] >> 4) & 0x07, data[34] & 0x0F); + printf("Data signal input hold %c%d.%d nS\n", + (data[35] & 0x80) ? '-' : '+', + (data[35] >> 4) & 0x07, data[35] & 0x0F); puts ("Manufacturer's JEDEC ID "); - for (j = 64; j <= 71; j++) - printf ("%02X ", data[j]); + for(j = 64; j <= 71; j++) + printf("%02X ", data[j]); putc ('\n'); - printf ("Manufacturing Location %02X\n", data[72]); + printf("Manufacturing Location %02X\n", data[72]); puts ("Manufacturer's Part Number "); - for (j = 73; j <= 90; j++) - printf ("%02X ", data[j]); + for(j = 73; j <= 90; j++) + printf("%02X ", data[j]); putc ('\n'); - printf ("Revision Code %02X %02X\n", data[91], data[92]); - printf ("Manufacturing Date %02X %02X\n", data[93], data[94]); + printf("Revision Code %02X %02X\n", data[91], data[92]); + printf("Manufacturing Date %02X %02X\n", data[93], data[94]); puts ("Assembly Serial Number "); - for (j = 95; j <= 98; j++) - printf ("%02X ", data[j]); + for(j = 95; j <= 98; j++) + printf("%02X ", data[j]); putc ('\n'); + printf("Speed rating PC%d\n", + data[126] == 0x66 ? 66 : data[126]); - if (DDR2 != type) { - printf ("Speed rating PC%d\n", - data[126] == 0x66 ? 66 : data[126]); - } return 0; } -#endif +#endif /* CFG_CMD_SDRAM */ -#if defined(CONFIG_I2C_CMD_TREE) -#if defined(CONFIG_I2C_MULTI_BUS) -int do_i2c_bus_num(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) + +#if defined(CFG_I2C_BUS_SELECT) +int do_i2c_bus(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - int bus_idx, ret=0; - - if (argc == 1) - /* querying current setting */ - printf("Current bus is %d\n", i2c_get_bus_num()); - else { - bus_idx = simple_strtoul(argv[1], NULL, 10); - printf("Setting bus to %d\n", bus_idx); - ret = i2c_set_bus_num(bus_idx); - if (ret) - printf("Failure changing bus number (%d)\n", ret); + int bus_idx, bus_spd, res = 0; + if (argc < 3) { + printf("Usage[%d]:\n%s\n", argc, cmdtp->usage); + return 1; } - return ret; -} -#endif /* CONFIG_I2C_MULTI_BUS */ - -int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - int speed, ret=0; - - if (argc == 1) - /* querying current speed */ - printf("Current bus speed=%d\n", i2c_get_bus_speed()); - else { - speed = simple_strtoul(argv[1], NULL, 10); - printf("Setting bus speed to %d Hz\n", speed); - ret = i2c_set_bus_speed(speed); - if (ret) - printf("Failure changing bus speed (%d)\n", ret); + bus_idx = simple_strtoul(argv[1], NULL, 16); + bus_spd = simple_strtoul(argv[2], NULL, 16); + printf("Setting bus[%d] to Speed[%d]: ", bus_idx, bus_spd); + res = select_bus(bus_idx, bus_spd); + if (res) { + printf("FAILED\n"); + } else { + printf("PASS\n"); } - return ret; + return res; } - -int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ -#if defined(CONFIG_I2C_MULTI_BUS) - if (!strncmp(argv[1], "de", 2)) - return do_i2c_bus_num(cmdtp, flag, --argc, ++argv); -#endif /* CONFIG_I2C_MULTI_BUS */ - if (!strncmp(argv[1], "sp", 2)) - return do_i2c_bus_speed(cmdtp, flag, --argc, ++argv); - if (!strncmp(argv[1], "md", 2)) - return do_i2c_md(cmdtp, flag, --argc, ++argv); - if (!strncmp(argv[1], "mm", 2)) - return do_i2c_mm(cmdtp, flag, --argc, ++argv); - if (!strncmp(argv[1], "mw", 2)) - return do_i2c_mw(cmdtp, flag, --argc, ++argv); - if (!strncmp(argv[1], "nm", 2)) - return do_i2c_nm(cmdtp, flag, --argc, ++argv); - if (!strncmp(argv[1], "cr", 2)) - return do_i2c_crc(cmdtp, flag, --argc, ++argv); - if (!strncmp(argv[1], "pr", 2)) - return do_i2c_probe(cmdtp, flag, --argc, ++argv); - if (!strncmp(argv[1], "lo", 2)) - return do_i2c_loop(cmdtp, flag, --argc, ++argv); -#if defined(CONFIG_CMD_SDRAM) - if (!strncmp(argv[1], "sd", 2)) - return do_sdram(cmdtp, flag, --argc, ++argv); -#endif - else - printf ("Usage:\n%s\n", cmdtp->usage); - return 0; -} -#endif /* CONFIG_I2C_CMD_TREE */ - +#endif /* bus select */ /***************************************************/ -#if defined(CONFIG_I2C_CMD_TREE) -U_BOOT_CMD( - i2c, 6, 1, do_i2c, - "i2c - I2C sub-system\n", -#if defined(CONFIG_I2C_MULTI_BUS) - "dev [dev] - show or set current I2C bus\n" -#endif /* CONFIG_I2C_MULTI_BUS */ - "i2c speed [speed] - show or set I2C bus speed\n" - "i2c md chip address[.0, .1, .2] [# of objects] - read from I2C device\n" - "i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n" - "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n" - "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n" - "i2c crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" - "i2c probe - show devices on the I2C bus\n" - "i2c loop chip address[.0, .1, .2] [# of objects] - looping read of device\n" -#if defined(CONFIG_CMD_SDRAM) - "i2c sdram chip - print SDRAM configuration information\n" -#endif -); -#endif /* CONFIG_I2C_CMD_TREE */ U_BOOT_CMD( imd, 4, 1, do_i2c_md, \ "imd - i2c memory display\n", \ @@ -1280,7 +905,7 @@ U_BOOT_CMD( ); U_BOOT_CMD( - imm, 3, 1, do_i2c_mm, + imm, 3, 1, do_i2c_mm, "imm - i2c memory modify (auto-incrementing)\n", "chip address[.0, .1, .2]\n" " - memory modify, auto increment address\n" @@ -1319,7 +944,7 @@ U_BOOT_CMD( " - loop, reading a set of addresses\n" ); -#if defined(CONFIG_CMD_SDRAM) +#if (CONFIG_COMMANDS & CFG_CMD_SDRAM) U_BOOT_CMD( isdram, 2, 1, do_sdram, "isdram - print SDRAM configuration information\n", @@ -1327,3 +952,12 @@ U_BOOT_CMD( " (valid chip values 50..57)\n" ); #endif + +#if defined(CFG_I2C_BUS_SELECT) +U_BOOT_CMD(ibus, 3, 1, do_i2c_bus, + "ibus - Select i2c Bus\n", + "bus_index speed\n - Selects the bus index and sets the speed (0x64(ST),0x190(FS),0xD48(HS))\n" + " (reports success/failure)\n"); +#endif + +#endif /* CFG_CMD_I2C */ diff --git a/common/cmd_ide.c b/common/cmd_ide.c index d6ba79f70..a4155029a 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -31,26 +31,34 @@ #include #include #include -#include - #if defined(CONFIG_IDE_8xx_DIRECT) || defined(CONFIG_IDE_PCMCIA) # include #endif - #ifdef CONFIG_8xx # include #endif - #ifdef CONFIG_MPC5xxx #include #endif - #include #include - #ifdef CONFIG_STATUS_LED # include #endif +#ifndef __PPC__ +#include +#ifdef __MIPS__ +/* Macros depend on this variable */ +unsigned long mips_io_port_base = 0; +#endif +#endif + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif #ifdef CONFIG_IDE_8xx_DIRECT DECLARE_GLOBAL_DATA_PTR; @@ -64,6 +72,8 @@ DECLARE_GLOBAL_DATA_PTR; # define SYNC /* nothing */ #endif +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + #ifdef CONFIG_IDE_8xx_DIRECT /* Timings for IDE Interface * @@ -119,6 +129,8 @@ ulong ide_bus_offset[CFG_IDE_MAXBUS] = { }; +#define ATA_CURR_BASE(dev) (CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) + #ifndef CONFIG_AMIGAONEG3SE static int ide_bus_ok[CFG_IDE_MAXBUS]; #else @@ -161,17 +173,16 @@ static uchar ide_wait (int dev, ulong t); #define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */ +static void __inline__ ide_outb(int dev, int port, unsigned char val); +static unsigned char __inline__ ide_inb(int dev, int port); static void input_data(int dev, ulong *sect_buf, int words); static void output_data(int dev, ulong *sect_buf, int words); static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); -#ifndef CFG_ATA_PORT_ADDR -#define CFG_ATA_PORT_ADDR(port) (port) -#endif #ifdef CONFIG_ATAPI static void atapi_inquiry(block_dev_desc_t *dev_desc); -ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer); +ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer); #endif @@ -296,7 +307,7 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong addr = simple_strtoul(argv[2], NULL, 16); ulong cnt = simple_strtoul(argv[4], NULL, 16); ulong n; -#ifdef CFG_64BIT_LBA +#ifdef CFG_64BIT_STRTOUL lbaint_t blk = simple_strtoull(argv[3], NULL, 16); printf ("\nIDE read: device %d block # %qd, count %ld ... ", @@ -325,7 +336,7 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong addr = simple_strtoul(argv[2], NULL, 16); ulong cnt = simple_strtoul(argv[4], NULL, 16); ulong n; -#ifdef CFG_64BIT_LBA +#ifdef CFG_64BIT_STRTOUL lbaint_t blk = simple_strtoull(argv[3], NULL, 16); printf ("\nIDE write: device %d block # %qd, count %ld ... ", @@ -360,15 +371,11 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *boot_device = NULL; char *ep; int dev, part = 0; - ulong addr, cnt; + ulong addr, cnt, checksum; disk_partition_t info; image_header_t *hdr; int rcode = 0; -#if defined(CONFIG_FIT) - const void *fit_hdr = NULL; -#endif - show_boot_progress (41); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -384,50 +391,44 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - show_boot_progress (-42); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (42); if (!boot_device) { puts ("\n** No boot device **\n"); - show_boot_progress (-43); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (43); dev = simple_strtoul(boot_device, &ep, 16); if (ide_dev_desc[dev].type==DEV_TYPE_UNKNOWN) { printf ("\n** Device %d not available\n", dev); - show_boot_progress (-44); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (44); if (*ep) { if (*ep != ':') { puts ("\n** Invalid boot device, use `dev[:part]' **\n"); - show_boot_progress (-45); + SHOW_BOOT_PROGRESS (-1); return 1; } part = simple_strtoul(++ep, NULL, 16); } - show_boot_progress (45); - if (get_partition_info (&ide_dev_desc[dev], part, &info)) { - show_boot_progress (-46); + if (get_partition_info (ide_dev_desc, part, &info)) { + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (46); if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) && (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) { printf ("\n** Invalid partition type \"%.32s\"" " (expect \"" BOOT_PART_TYPE "\")\n", info.type); - show_boot_progress (-47); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (47); printf ("\nLoading from IDE device %d, partition %d: " "Name: %.32s Type: %.32s\n", @@ -438,42 +439,31 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (ide_dev_desc[dev].block_read (dev, info.start, 1, (ulong *)addr) != 1) { printf ("** Read error on %d:%d\n", dev, part); - show_boot_progress (-48); - return 1; - } - show_boot_progress (48); - - switch (genimg_get_format ((void *)addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *)addr; - - show_boot_progress (49); - - if (!image_check_hcrc (hdr)) { - puts ("\n** Bad Header Checksum **\n"); - show_boot_progress (-50); - return 1; - } - show_boot_progress (50); - - image_print_contents (hdr); - - cnt = image_get_image_size (hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (const void *)addr; - puts ("Fit image detected...\n"); - - cnt = fit_get_size (fit_hdr); - break; -#endif - default: - show_boot_progress (-49); - puts ("** Unknown image type\n"); + SHOW_BOOT_PROGRESS (-1); return 1; } + hdr = (image_header_t *)addr; + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + printf("\n** Bad Magic Number **\n"); + SHOW_BOOT_PROGRESS (-1); + return 1; + } + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) { + puts ("\n** Bad Header Checksum **\n"); + SHOW_BOOT_PROGRESS (-2); + return 1; + } + hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */ + + print_image_hdr (hdr); + + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); cnt += info.blksz - 1; cnt /= info.blksz; cnt -= 1; @@ -481,23 +471,10 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (ide_dev_desc[dev].block_read (dev, info.start+1, cnt, (ulong *)(addr+info.blksz)) != cnt) { printf ("** Read error on %d:%d\n", dev, part); - show_boot_progress (-51); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (51); -#if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { - if (!fit_check_format (fit_hdr)) { - show_boot_progress (-140); - puts ("** Bad FIT image format\n"); - return 1; - } - show_boot_progress (141); - fit_print_contents (fit_hdr); - } -#endif /* Loading ok, update default load address */ @@ -521,28 +498,6 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* ------------------------------------------------------------------------- */ -void inline -__ide_outb(int dev, int port, unsigned char val) -{ - debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", - dev, port, val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); - outb(val, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); -} -void inline ide_outb (int dev, int port, unsigned char val) - __attribute__((weak, alias("__ide_outb"))); - -unsigned char inline -__ide_inb(int dev, int port) -{ - uchar val; - val = inb((ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); - debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", - dev, port, (ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)), val); - return val; -} -unsigned char inline ide_inb(int dev, int port) - __attribute__((weak, alias("__ide_inb"))); - void ide_init (void) { @@ -552,12 +507,10 @@ void ide_init (void) #endif unsigned char c; int i, bus; -#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3) - unsigned int ata_reset_time = ATA_RESET_TIME; - char *s; -#endif #ifdef CONFIG_AMIGAONEG3SE unsigned int max_bus_scan; + unsigned int ata_reset_time; + char *s; #endif #ifdef CONFIG_IDE_8xx_PCCARD extern int pcmcia_on (void); @@ -658,9 +611,10 @@ void ide_init (void) udelay (100000); /* 100 ms */ ide_outb (dev, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(dev)); udelay (100000); /* 100 ms */ -#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3) - if ((s = getenv("ide_reset_timeout")) != NULL) - ata_reset_time = simple_strtol(s, NULL, 10); +#ifdef CONFIG_AMIGAONEG3SE + ata_reset_time = ATA_RESET_TIME; + s = getenv("ide_reset_timeout"); + if (s) ata_reset_time = 2*simple_strtol(s, NULL, 10); #endif i = 0; do { @@ -668,7 +622,7 @@ void ide_init (void) c = ide_inb (dev, ATA_STATUS); i++; -#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3) +#ifdef CONFIG_AMIGAONEG3SE if (i > (ata_reset_time * 100)) { #else if (i > (ATA_RESET_TIME * 100)) { @@ -743,7 +697,7 @@ void ide_init (void) block_dev_desc_t * ide_get_dev(int dev) { - return (dev < CFG_IDE_MAXDEVICE) ? &ide_dev_desc[dev] : NULL; + return ((block_dev_desc_t *)&ide_dev_desc[dev]); } @@ -837,6 +791,46 @@ set_pcmcia_timing (int pmode) /* ------------------------------------------------------------------------- */ +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) +static void __inline__ +ide_outb(int dev, int port, unsigned char val) +{ + debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n", + dev, port, val, (ATA_CURR_BASE(dev)+port)); + + /* Ensure I/O operations complete */ + EIEIO; + *((uchar *)(ATA_CURR_BASE(dev)+port)) = val; +} +#else /* ! __PPC__ */ +static void __inline__ +ide_outb(int dev, int port, unsigned char val) +{ + outb(val, ATA_CURR_BASE(dev)+port); +} +#endif /* __PPC__ */ + + +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) +static unsigned char __inline__ +ide_inb(int dev, int port) +{ + uchar val; + /* Ensure I/O operations complete */ + EIEIO; + val = *((uchar *)(ATA_CURR_BASE(dev)+port)); + debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", + dev, port, (ATA_CURR_BASE(dev)+port), val); + return (val); +} +#else /* ! __PPC__ */ +static unsigned char __inline__ +ide_inb(int dev, int port) +{ + return inb(ATA_CURR_BASE(dev)+port); +} +#endif /* __PPC__ */ + #ifdef __PPC__ # ifdef CONFIG_AMIGAONEG3SE static void @@ -890,9 +884,6 @@ input_swap_data(int dev, ulong *sect_buf, int words) #ifdef __MIPS__ *dbuf++ = swab16p((u16*)pbuf); *dbuf++ = swab16p((u16*)pbuf); -#elif defined(CONFIG_PCS440EP) - *dbuf++ = *pbuf; - *dbuf++ = *pbuf; #else *dbuf++ = ld_le16(pbuf); *dbuf++ = ld_le16(pbuf); @@ -903,7 +894,7 @@ input_swap_data(int dev, ulong *sect_buf, int words) #endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */ -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH) +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) static void output_data(int dev, ulong *sect_buf, int words) { @@ -932,18 +923,10 @@ output_data(int dev, ulong *sect_buf, int words) pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); dbuf = (ushort *)sect_buf; while (words--) { -#if defined(CONFIG_PCS440EP) - /* not tested, because CF was write protected */ - EIEIO; - *pbuf = ld_le16(dbuf++); - EIEIO; - *pbuf = ld_le16(dbuf++); -#else EIEIO; *pbuf = *dbuf++; EIEIO; *pbuf = *dbuf++; -#endif } #endif } @@ -955,7 +938,7 @@ output_data(int dev, ulong *sect_buf, int words) } #endif /* __PPC__ */ -#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH) +#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) static void input_data(int dev, ulong *sect_buf, int words) { @@ -991,17 +974,10 @@ input_data(int dev, ulong *sect_buf, int words) debug("in input data base for read is %lx\n", (unsigned long) pbuf); while (words--) { -#if defined(CONFIG_PCS440EP) - EIEIO; - *dbuf++ = ld_le16(pbuf); - EIEIO; - *dbuf++ = ld_le16(pbuf); -#else EIEIO; *dbuf++ = *pbuf; EIEIO; *dbuf++ = *pbuf; -#endif } #endif } @@ -1147,9 +1123,9 @@ static void ide_ident (block_dev_desc_t *dev_desc) input_swap_data (device, iobuf, ATA_SECTORWORDS); - ident_cpy ((unsigned char*)dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision)); - ident_cpy ((unsigned char*)dev_desc->vendor, iop->model, sizeof(dev_desc->vendor)); - ident_cpy ((unsigned char*)dev_desc->product, iop->serial_no, sizeof(dev_desc->product)); + ident_cpy (dev_desc->revision, iop->fw_rev, sizeof(dev_desc->revision)); + ident_cpy (dev_desc->vendor, iop->model, sizeof(dev_desc->vendor)); + ident_cpy (dev_desc->product, iop->serial_no, sizeof(dev_desc->product)); #ifdef __LITTLE_ENDIAN /* * firmware revision and model number have Big Endian Byte @@ -1232,7 +1208,7 @@ static void ide_ident (block_dev_desc_t *dev_desc) dev_desc->blksz=ATA_BLOCKSIZE; dev_desc->lun=0; /* just to fill something in... */ -#if 0 /* only used to test the powersaving mode, +#if 0 /* only used to test the powersaving mode, * if enabled, the drive goes after 5 sec * in standby mode */ ide_outb (device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); @@ -1251,7 +1227,7 @@ static void ide_ident (block_dev_desc_t *dev_desc) /* ------------------------------------------------------------------------- */ -ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer) +ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer) { ulong n = 0; unsigned char c; @@ -1259,7 +1235,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer) #ifdef CONFIG_LBA48 unsigned char lba48 = 0; - if (blknr & 0x0000fffff0000000ULL) { + if (blknr & 0x0000fffff0000000) { /* more than 28 bits used, use 48bit mode */ lba48 = 1; } @@ -1313,13 +1289,8 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer) /* write high bits */ ide_outb (device, ATA_SECT_CNT, 0); ide_outb (device, ATA_LBA_LOW, (blknr >> 24) & 0xFF); -#ifdef CFG_64BIT_LBA ide_outb (device, ATA_LBA_MID, (blknr >> 32) & 0xFF); ide_outb (device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF); -#else - ide_outb (device, ATA_LBA_MID, 0); - ide_outb (device, ATA_LBA_HIGH, 0); -#endif } #endif ide_outb (device, ATA_SECT_CNT, 1); @@ -1366,7 +1337,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer) ++n; ++blknr; - buffer += ATA_BLOCKSIZE; + buffer += ATA_SECTORWORDS; } IDE_READ_E: ide_led (DEVICE_LED(device), 0); /* LED off */ @@ -1376,14 +1347,14 @@ IDE_READ_E: /* ------------------------------------------------------------------------- */ -ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer) +ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer) { ulong n = 0; unsigned char c; #ifdef CONFIG_LBA48 unsigned char lba48 = 0; - if (blknr & 0x0000fffff0000000ULL) { + if (blknr & 0x0000fffff0000000) { /* more than 28 bits used, use 48bit mode */ lba48 = 1; } @@ -1408,13 +1379,8 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer) /* write high bits */ ide_outb (device, ATA_SECT_CNT, 0); ide_outb (device, ATA_LBA_LOW, (blknr >> 24) & 0xFF); -#ifdef CFG_64BIT_LBA ide_outb (device, ATA_LBA_MID, (blknr >> 32) & 0xFF); ide_outb (device, ATA_LBA_HIGH, (blknr >> 40) & 0xFF); -#else - ide_outb (device, ATA_LBA_MID, 0); - ide_outb (device, ATA_LBA_HIGH, 0); -#endif } #endif ide_outb (device, ATA_SECT_CNT, 1); @@ -1455,7 +1421,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer) c = ide_inb (device, ATA_STATUS); /* clear IRQ */ ++n; ++blknr; - buffer += ATA_BLOCKSIZE; + buffer += ATA_SECTORWORDS; } WR_OUT: ide_led (DEVICE_LED(device), 0); /* LED off */ @@ -1534,9 +1500,6 @@ static void ide_reset (void) ide_set_reset (1); /* assert reset */ - /* the reset signal shall be asserted for et least 25 us */ - udelay(25); - WATCHDOG_RESET(); #ifdef CFG_PB_12V_ENABLE @@ -1782,7 +1745,7 @@ unsigned char atapi_issue(int device,unsigned char* ccb,int ccblen, unsigned cha } output_data_shorts (device, (unsigned short *)ccb,ccblen/2); /* write command block */ - /* ATAPI Command written wait for completition */ + /* ATAPI Command written wait for completition */ udelay (5000); /* device must set bsy */ mask = ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR; @@ -1851,7 +1814,7 @@ AI_OUT: * returns, an request_sense will be issued */ -#define ATAPI_DRIVE_NOT_READY 100 +#define ATAPI_DRIVE_NOT_READY 100 #define ATAPI_UNIT_ATTN 10 unsigned char atapi_issue_autoreq (int device, @@ -1977,9 +1940,9 @@ static void atapi_inquiry(block_dev_desc_t * dev_desc) return; /* copy device ident strings */ - ident_cpy((unsigned char*)dev_desc->vendor,&iobuf[8],8); - ident_cpy((unsigned char*)dev_desc->product,&iobuf[16],16); - ident_cpy((unsigned char*)dev_desc->revision,&iobuf[32],5); + ident_cpy(dev_desc->vendor,&iobuf[8],8); + ident_cpy(dev_desc->product,&iobuf[16],16); + ident_cpy(dev_desc->revision,&iobuf[32],5); dev_desc->lun=0; dev_desc->lba=0; @@ -2046,7 +2009,7 @@ static void atapi_inquiry(block_dev_desc_t * dev_desc) #define ATAPI_READ_BLOCK_SIZE 2048 /* assuming CD part */ #define ATAPI_READ_MAX_BLOCK ATAPI_READ_MAX_BYTES/ATAPI_READ_BLOCK_SIZE /* max blocks */ -ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer) +ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, ulong *buffer) { ulong n = 0; unsigned char ccb[12]; /* Command descriptor block */ @@ -2082,7 +2045,7 @@ ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer) n+=cnt; blkcnt-=cnt; blknr+=cnt; - buffer+=(cnt*ATAPI_READ_BLOCK_SIZE); + buffer+=cnt*(ATAPI_READ_BLOCK_SIZE/4); /* ulong blocksize in ulong */ } while (blkcnt > 0); return (n); } @@ -2109,3 +2072,5 @@ U_BOOT_CMD( "diskboot- boot from IDE device\n", "loadAddr dev:part\n" ); + +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ diff --git a/common/cmd_ignore.c b/common/cmd_ignore.c new file mode 100644 index 000000000..0fbe5c283 --- /dev/null +++ b/common/cmd_ignore.c @@ -0,0 +1,74 @@ +/* + * Prefix to ignore return code of a given command + * + * Copyright (C) 2010 TomTom International B.V. + * Author: Martin Jackson + * + ************************************************************************ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + ************************************************************************ + */ + +#include +#include + +#if defined(CONFIG_CMD_IGNORE) + +/* Note - we still return error if the command is not well-formed */ +int do_ignore (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return -1; + } + + argv = &argv[1]; + argc--; + + clear_ctrlc(); /* forget any previous Control C */ + + /* Look up command in command table */ + if ((cmdtp = find_cmd(argv[0])) == NULL) { + printf ("Unknown command '%s' - try 'help'\n", argv[0]); + return -1; + } + + /* found - check max args */ + if (argc > cmdtp->maxargs) { + printf ("Usage:\n%s\n", cmdtp->usage); + return -1; + } + + /* OK - call function to do the command */ + (cmdtp->cmd) (cmdtp, flag, argc, argv); + + /* Did the user stop this? */ + if (had_ctrlc ()) { + return -1; /* if stopped then not repeatable */ + } + + return 0; +} + +U_BOOT_CMD( + ignore, CFG_MAXARGS, 0, do_ignore, + "ignore- Ignore return code of argument\n", + " [args ...]\n" + " - Execute 'command' with 'args' and carry on\n" + " with boot regardless\n" +); + +#endif /* CONFIG_CMD_IGNORE */ + diff --git a/common/cmd_immap.c b/common/cmd_immap.c index d75826977..fa79b45a3 100644 --- a/common/cmd_immap.c +++ b/common/cmd_immap.c @@ -28,7 +28,8 @@ #include #include -#if defined(CONFIG_8xx) || defined(CONFIG_8260) +#if (CONFIG_COMMANDS & CFG_CMD_IMMAP) && \ + (defined(CONFIG_8xx) || defined(CONFIG_8260)) #if defined(CONFIG_8xx) #include @@ -40,7 +41,9 @@ #include #endif +#if defined(CONFIG_8xx) || defined(CONFIG_8260) DECLARE_GLOBAL_DATA_PTR; +#endif static void unimplemented ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -717,4 +720,4 @@ U_BOOT_CMD( ); -#endif +#endif /* CFG_CMD_IMMAP && (CONFIG_8xx || CONFIG_8260) */ diff --git a/common/cmd_itest.c b/common/cmd_itest.c index ce988723c..8ad134f4a 100644 --- a/common/cmd_itest.c +++ b/common/cmd_itest.c @@ -32,6 +32,8 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_ITEST) + #define EQ 0 #define NE 1 #define LT 2 @@ -195,3 +197,4 @@ U_BOOT_CMD( "itest\t- return true/false on integer compare\n", "[.b, .w, .l, .s] [*]value1 [*]value2\n" ); +#endif /* CONFIG_COMMANDS & CFG_CMD_ITEST */ diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index b4698bee4..201c3c155 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -93,16 +93,19 @@ #include #include #include + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + #include -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #ifdef CFG_NAND_LEGACY #include #else /* !CFG_NAND_LEGACY */ #include #include #endif /* !CFG_NAND_LEGACY */ -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ /* enable/disable debugging messages */ #define DEBUG_JFFS #undef DEBUG_JFFS @@ -167,19 +170,10 @@ struct list_head devices; static struct mtd_device *current_dev = NULL; static u8 current_partnum = 0; -#if defined(CONFIG_CMD_CRAMFS) extern int cramfs_check (struct part_info *info); extern int cramfs_load (char *loadoffset, struct part_info *info, char *filename); extern int cramfs_ls (struct part_info *info, char *filename); extern int cramfs_info (struct part_info *info); -#else -/* defining empty macros for function names is ugly but avoids ifdef clutter - * all over the code */ -#define cramfs_check(x) (0) -#define cramfs_load(x,y,z) (-1) -#define cramfs_ls(x,y) (0) -#define cramfs_info(x) (0) -#endif static struct part_info* jffs2_part_info(struct mtd_device *dev, unsigned int part_num); @@ -241,13 +235,13 @@ static void memsize_format(char *buf, u32 size) #define SIZE_KB ((u32)1024) if ((size % SIZE_GB) == 0) - sprintf(buf, "%ug", size/SIZE_GB); + sprintf(buf, "%lug", size/SIZE_GB); else if ((size % SIZE_MB) == 0) - sprintf(buf, "%um", size/SIZE_MB); + sprintf(buf, "%lum", size/SIZE_MB); else if (size % SIZE_KB == 0) - sprintf(buf, "%uk", size/SIZE_KB); + sprintf(buf, "%luk", size/SIZE_KB); else - sprintf(buf, "%u", size); + sprintf(buf, "%lu", size); } /** @@ -327,7 +321,7 @@ static void current_save(void) */ static int part_validate_nor(struct mtdids *id, struct part_info *part) { -#if defined(CONFIG_CMD_FLASH) +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) /* info for FLASH chips */ extern flash_info_t flash_info[]; flash_info_t *flash; @@ -376,7 +370,7 @@ static int part_validate_nor(struct mtdids *id, struct part_info *part) */ static int part_validate_nand(struct mtdids *id, struct part_info *part) { -#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) /* info for NAND chips */ nand_info_t *nand; @@ -416,7 +410,7 @@ static int part_validate(struct mtdids *id, struct part_info *part) part->size = id->size - part->offset; if (part->offset > id->size) { - printf("%s: offset %08x beyond flash size %08x\n", + printf("%s: offset %08lx beyond flash size %08lx\n", id->mtd_id, part->offset, id->size); return 1; } @@ -725,7 +719,7 @@ static int part_parse(const char *const partdef, const char **ret, struct part_i static int device_validate(u8 type, u8 num, u32 *size) { if (type == MTD_DEV_TYPE_NOR) { -#if defined(CONFIG_CMD_FLASH) +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) if (num < CFG_MAX_FLASH_BANKS) { extern flash_info_t flash_info[]; *size = flash_info[num].size; @@ -739,7 +733,7 @@ static int device_validate(u8 type, u8 num, u32 *size) printf("support for FLASH devices not present\n"); #endif } else if (type == MTD_DEV_TYPE_NAND) { -#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) if (num < CFG_MAX_NAND_DEVICE) { #ifndef CFG_NAND_LEGACY *size = nand_info[num].size; @@ -1274,7 +1268,7 @@ static void list_partitions(void) part_num = 0; list_for_each(pentry, &dev->parts) { part = list_entry(pentry, struct part_info, link); - printf("%2d: %-20s0x%08x\t0x%08x\t%d\n", + printf(" %d: %-22s\t0x%08x\t0x%08x\t%d\n", part_num, part->name, part->size, part->offset, part->mask_flags); @@ -1288,7 +1282,7 @@ static void list_partitions(void) if (current_dev) { part = jffs2_part_info(current_dev, current_partnum); if (part) { - printf("\nactive partition: %s%d,%d - (%s) 0x%08x @ 0x%08x\n", + printf("\nactive partition: %s%d,%d - (%s) 0x%08lx @ 0x%08lx\n", MTD_DEV_TYPE(current_dev->id->type), current_dev->id->num, current_partnum, part->name, part->size, part->offset); @@ -1306,7 +1300,7 @@ static void list_partitions(void) * Given partition identifier in form of , find * corresponding device and verify partition number. * - * @param id string describing device and partition or partition name + * @param id string describing device and partition * @param dev pointer to the requested device (output) * @param part_num verified partition number (output) * @param part pointer to requested partition (output) @@ -1315,23 +1309,11 @@ static void list_partitions(void) int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part) { - struct list_head *dentry, *pentry; u8 type, dnum, pnum; const char *p; DEBUGF("--- find_dev_and_part ---\nid = %s\n", id); - list_for_each(dentry, &devices) { - *part_num = 0; - *dev = list_entry(dentry, struct mtd_device, link); - list_for_each(pentry, &(*dev)->parts) { - *part = list_entry(pentry, struct part_info, link); - if (strcmp((*part)->name, id) == 0) - return 0; - (*part_num)++; - } - } - p = id; *dev = NULL; *part = NULL; @@ -2197,3 +2179,5 @@ U_BOOT_CMD( #endif /* #ifdef CONFIG_JFFS2_CMDLINE */ /***************************************************/ + +#endif /* CFG_CMD_JFFS2 */ diff --git a/common/cmd_load.c b/common/cmd_load.c index ab167f5ab..f63b8e805 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c @@ -33,24 +33,24 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CMD_LOADB) +#if (CONFIG_COMMANDS & CFG_CMD_LOADB) static ulong load_serial_ymodem (ulong offset); #endif -#if defined(CONFIG_CMD_LOADS) +#if (CONFIG_COMMANDS & CFG_CMD_LOADS) static ulong load_serial (ulong offset); static int read_record (char *buf, ulong len); -# if defined(CONFIG_CMD_SAVES) +# if (CONFIG_COMMANDS & CFG_CMD_SAVES) static int save_serial (ulong offset, ulong size); static int write_record (char *buf); -#endif +# endif /* CFG_CMD_SAVES */ static int do_echo = 1; -#endif +#endif /* CFG_CMD_LOADS */ /* -------------------------------------------------------------------- */ -#if defined(CONFIG_CMD_LOADS) +#if (CONFIG_COMMANDS & CFG_CMD_LOADS) int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong offset = 0; @@ -253,7 +253,7 @@ read_record (char *buf, ulong len) return (p - buf); } -#if defined(CONFIG_CMD_SAVES) +#if (CONFIG_COMMANDS & CFG_CMD_SAVES) int do_save_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -399,15 +399,13 @@ write_record (char *buf) } return (0); } -# endif +# endif /* CFG_CMD_SAVES */ -#endif +#endif /* CFG_CMD_LOADS */ -#if defined(CONFIG_CMD_LOADB) -/* - * loadb command (load binary) included - */ +#if (CONFIG_COMMANDS & CFG_CMD_LOADB) /* loadb command (load binary) included */ + #define XON_CHAR 17 #define XOFF_CHAR 19 #define START_CHAR 0x01 @@ -424,6 +422,7 @@ write_record (char *buf) #define untochar(x) ((int) (((x) - SPACE) & 0xff)) extern int os_data_count; +extern int os_data_header[8]; static void set_kerm_bin_mode(unsigned long *); static int k_recv(void); @@ -520,15 +519,8 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *s; if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { - printf ("Running autoscript at addr 0x%08lX", load_addr); - - s = getenv ("autoscript_uname"); - if (s) - printf (":%s ...\n", s); - else - puts (" ...\n"); - - rcode = autoscript (load_addr, s); + printf("Running autoscript at addr 0x%08lX ...\n", load_addr); + rcode = autoscript (load_addr); } } #endif @@ -630,6 +622,11 @@ void send_nack (int n) } +/* os_data_* takes an OS Open image and puts it into memory, and + puts the boot header in an array named os_data_header + + if image is binary, no header is stored in os_data_header. +*/ void (*os_data_init) (void); void (*os_data_char) (char new_char); static int os_data_state, os_data_state_saved; @@ -637,28 +634,25 @@ int os_data_count; static int os_data_count_saved; static char *os_data_addr, *os_data_addr_saved; static char *bin_start_address; - +int os_data_header[8]; static void bin_data_init (void) { os_data_state = 0; os_data_count = 0; os_data_addr = bin_start_address; } - static void os_data_save (void) { os_data_state_saved = os_data_state; os_data_count_saved = os_data_count; os_data_addr_saved = os_data_addr; } - static void os_data_restore (void) { os_data_state = os_data_state_saved; os_data_count = os_data_count_saved; os_data_addr = os_data_addr_saved; } - static void bin_data_char (char new_char) { switch (os_data_state) { @@ -668,7 +662,6 @@ static void bin_data_char (char new_char) break; } } - static void set_kerm_bin_mode (unsigned long *addr) { bin_start_address = (char *) addr; @@ -684,19 +677,16 @@ void k_data_init (void) k_data_escape = 0; os_data_init (); } - void k_data_save (void) { k_data_escape_saved = k_data_escape; os_data_save (); } - void k_data_restore (void) { k_data_escape = k_data_escape_saved; os_data_restore (); } - void k_data_char (char new_char) { if (k_data_escape) { @@ -1046,11 +1036,11 @@ static ulong load_serial_ymodem (ulong offset) return offset; } -#endif +#endif /* CFG_CMD_LOADB */ /* -------------------------------------------------------------------- */ -#if defined(CONFIG_CMD_LOADS) +#if (CONFIG_COMMANDS & CFG_CMD_LOADS) #ifdef CFG_LOADS_BAUD_CHANGE U_BOOT_CMD( @@ -1075,7 +1065,7 @@ U_BOOT_CMD( */ -#if defined(CONFIG_CMD_SAVES) +#if (CONFIG_COMMANDS & CFG_CMD_SAVES) #ifdef CFG_LOADS_BAUD_CHANGE U_BOOT_CMD( saves, 4, 0, do_save_serial, @@ -1092,11 +1082,11 @@ U_BOOT_CMD( " - save S-Record file over serial line with offset 'off' and size 'size'\n" ); #endif /* CFG_LOADS_BAUD_CHANGE */ -#endif -#endif +#endif /* CFG_CMD_SAVES */ +#endif /* CFG_CMD_LOADS */ -#if defined(CONFIG_CMD_LOADB) +#if (CONFIG_COMMANDS & CFG_CMD_LOADB) U_BOOT_CMD( loadb, 3, 0, do_load_serial_bin, "loadb - load binary file over serial line (kermit mode)\n", @@ -1113,11 +1103,11 @@ U_BOOT_CMD( " with offset 'off' and baudrate 'baud'\n" ); -#endif +#endif /* CFG_CMD_LOADB */ /* -------------------------------------------------------------------- */ -#if defined(CONFIG_CMD_HWFLOW) +#if (CONFIG_COMMANDS & CFG_CMD_HWFLOW) int do_hwflow (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { extern int hwflow_onoff(int); @@ -1143,4 +1133,4 @@ U_BOOT_CMD( "[on|off]\n - change RTS/CTS hardware flow control over serial line\n" ); -#endif +#endif /* CFG_CMD_HWFLOW */ diff --git a/common/cmd_log.c b/common/cmd_log.c index fdcc57571..042a40302 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002-2007 + * (C) Copyright 2002 * Detlev Zundel, DENX Software Engineering, dzu@denx.de. * * Code used from linux/kernel/printk.c @@ -48,6 +48,8 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_LOGBUFFER) + /* Local prototypes */ static void logbuff_putc (const char c); static void logbuff_puts (const char *s); @@ -58,86 +60,50 @@ static char buf[1024]; /* This combination will not print messages with the default loglevel */ static unsigned console_loglevel = 3; static unsigned default_message_loglevel = 4; -static unsigned log_version = 1; -#ifdef CONFIG_ALT_LB_ADDR -static volatile logbuff_t *log; -#else -static logbuff_t *log; -#endif -static char *lbuf; +static unsigned char *log_buf = NULL; +static unsigned long *ext_log_size; +static unsigned long *ext_log_start; +static unsigned long *ext_logged_chars; +#define log_size (*ext_log_size) +#define log_start (*ext_log_start) +#define logged_chars (*ext_logged_chars) -unsigned long __logbuffer_base(void) -{ - return CFG_SDRAM_BASE + gd->bd->bi_memsize - LOGBUFF_LEN; -} -unsigned long logbuffer_base (void) __attribute__((weak, alias("__logbuffer_base"))); +/* Forced by code, eh! */ +#define LOGBUFF_MAGIC 0xc0de4ced +/* The mapping used here has to be the same as in setup_ext_logbuff () + in linux/kernel/printk */ void logbuff_init_ptrs (void) { - unsigned long tag, post_word; + unsigned long *ext_tag; + unsigned long post_word; char *s; -#ifdef CONFIG_ALT_LB_ADDR - log = (logbuff_t *)CONFIG_ALT_LH_ADDR; - lbuf = (char *)CONFIG_ALT_LB_ADDR; -#else - log = (logbuff_t *)(logbuffer_base ()) - 1; - lbuf = (char *)log->buf; -#endif - - /* Set up log version */ - if ((s = getenv ("logversion")) != NULL) - log_version = (int)simple_strtoul (s, NULL, 10); - - if (log_version == 2) - tag = log->v2.tag; - else - tag = log->v1.tag; + log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN); + ext_tag = (unsigned long *)(log_buf)-4; + ext_log_start = (unsigned long *)(log_buf)-3; + ext_log_size = (unsigned long *)(log_buf)-2; + ext_logged_chars = (unsigned long *)(log_buf)-1; post_word = post_word_load(); #ifdef CONFIG_POST /* The post routines have setup the word so we can simply test it */ - if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) { - logbuff_reset (); - } + if (post_word_load () & POST_COLDBOOT) { + logged_chars = log_size = log_start = 0; + *ext_tag = LOGBUFF_MAGIC; + } #else /* No post routines, so we do our own checking */ - if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) { - logbuff_reset (); + if (post_word != LOGBUFF_MAGIC) { + logged_chars = log_size = log_start = 0; post_word_store (LOGBUFF_MAGIC); - } + *ext_tag = LOGBUFF_MAGIC; + } #endif - if (log_version == 2 && (long)log->v2.start > (long)log->v2.con) - log->v2.start = log->v2.con; - /* Initialize default loglevel if present */ if ((s = getenv ("loglevel")) != NULL) console_loglevel = (int)simple_strtoul (s, NULL, 10); - gd->flags |= GD_FLG_LOGINIT; -} - -void logbuff_reset (void) -{ -#ifndef CONFIG_ALT_LB_ADDR - memset (log, 0, sizeof (logbuff_t)); -#endif - if (log_version == 2) { - log->v2.tag = LOGBUFF_MAGIC; -#ifdef CONFIG_ALT_LB_ADDR - log->v2.start = 0; - log->v2.con = 0; - log->v2.end = 0; - log->v2.chars = 0; -#endif - } else { - log->v1.tag = LOGBUFF_MAGIC; -#ifdef CONFIG_ALT_LB_ADDR - log->v1.dummy = 0; - log->v1.start = 0; - log->v1.size = 0; - log->v1.chars = 0; -#endif - } + gd->post_log_word |= LOGBUFF_INITIALIZED; } int drv_logbuff_init (void) @@ -174,7 +140,7 @@ static void logbuff_puts (const char *s) void logbuff_log(char *msg) { - if ((gd->flags & GD_FLG_LOGINIT)) { + if ((gd->post_log_word & LOGBUFF_INITIALIZED)) { logbuff_printk (msg); } else { /* Can happen only for pre-relocated errors as logging */ @@ -196,7 +162,7 @@ void logbuff_log(char *msg) int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { char *s; - unsigned long i, start, size; + unsigned long i; if (strcmp(argv[1],"append") == 0) { /* Log concatenation of all arguments separated by spaces */ @@ -211,34 +177,21 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) case 2: if (strcmp(argv[1],"show") == 0) { - if (log_version == 2) { - start = log->v2.start; - size = log->v2.end - log->v2.start; - } - else { - start = log->v1.start; - size = log->v1.size; - } - for (i=0; i < (size&LOGBUFF_MASK); i++) { - s = lbuf+((start+i)&LOGBUFF_MASK); + for (i=0; i < (log_size&LOGBUFF_MASK); i++) { + s = (char *)log_buf+((log_start+i)&LOGBUFF_MASK); putc (*s); } return 0; } else if (strcmp(argv[1],"reset") == 0) { - logbuff_reset (); + log_start = 0; + log_size = 0; + logged_chars = 0; return 0; } else if (strcmp(argv[1],"info") == 0) { - printf ("Logbuffer at %08lx\n", (unsigned long)lbuf); - if (log_version == 2) { - printf ("log_start = %08lx\n", log->v2.start); - printf ("log_end = %08lx\n", log->v2.end); - printf ("logged_chars = %08lx\n", log->v2.chars); - } - else { - printf ("log_start = %08lx\n", log->v1.start); - printf ("log_size = %08lx\n", log->v1.size); - printf ("logged_chars = %08lx\n", log->v1.chars); - } + printf ("Logbuffer at %08lx\n", (unsigned long)log_buf); + printf ("log_start = %08lx\n", log_start); + printf ("log_size = %08lx\n", log_size); + printf ("logged_chars = %08lx\n", logged_chars); return 0; } printf ("Usage:\n%s\n", cmdtp->usage); @@ -249,7 +202,7 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } } - +#if defined(CONFIG_LOGBUFFER) U_BOOT_CMD( log, 255, 1, do_log, "log - manipulate logbuffer\n", @@ -258,7 +211,7 @@ U_BOOT_CMD( "log show - show contents\n" "log append - append to the logbuffer\n" ); - +#endif /* CONFIG_LOGBUFFER */ static int logbuff_printk(const char *line) { int i; @@ -288,22 +241,13 @@ static int logbuff_printk(const char *line) } line_feed = 0; for (; p < buf_end; p++) { - if (log_version == 2) { - lbuf[log->v2.end & LOGBUFF_MASK] = *p; - log->v2.end++; - if (log->v2.end - log->v2.start > LOGBUFF_LEN) - log->v2.start++; - log->v2.chars++; - } - else { - lbuf[(log->v1.start + log->v1.size) & - LOGBUFF_MASK] = *p; - if (log->v1.size < LOGBUFF_LEN) - log->v1.size++; - else - log->v1.start++; - log->v1.chars++; - } + log_buf[(log_start+log_size) & LOGBUFF_MASK] = *p; + if (log_size < LOGBUFF_LEN) + log_size++; + else + log_start++; + + logged_chars++; if (*p == '\n') { line_feed = 1; break; @@ -317,3 +261,5 @@ static int logbuff_printk(const char *line) } return i; } + +#endif /* (CONFIG_LOGBUFFER) */ diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 2606986db..1a8517389 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -29,20 +29,20 @@ #include #include -#if defined(CONFIG_CMD_MMC) +#if (CONFIG_COMMANDS & CFG_CMD_MMC) #include #endif #ifdef CONFIG_HAS_DATAFLASH #include #endif -#include -#if defined(CONFIG_CMD_MEMORY) \ - || defined(CONFIG_CMD_I2C) \ - || defined(CONFIG_CMD_ITEST) \ - || defined(CONFIG_CMD_PCI) \ - || defined(CONFIG_CMD_PORTIO) +DECLARE_GLOBAL_DATA_PTR; +#if (CONFIG_COMMANDS & (CFG_CMD_MEMORY | \ + CFG_CMD_I2C | \ + CFG_CMD_ITEST | \ + CFG_CMD_PCI | \ + CMD_CMD_PORTIO ) ) int cmd_get_data_size(char* arg, int default_size) { /* Check for a size specification .b, .w or .l. @@ -66,7 +66,7 @@ int cmd_get_data_size(char* arg, int default_size) } #endif -#if defined(CONFIG_CMD_MEMORY) +#if (CONFIG_COMMANDS & CFG_CMD_MEMORY) #ifdef CMD_MEM_DEBUG #define PRINTF(fmt,args...) printf (fmt ,##args) @@ -94,9 +94,8 @@ static ulong base_address = 0; int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong addr, length; -#if defined(CONFIG_HAS_DATAFLASH) - ulong nbytes, linebytes; -#endif + ulong i, nbytes, linebytes; + u_char *cp; int size; int rc = 0; @@ -131,7 +130,6 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) length = simple_strtoul(argv[2], NULL, 16); } -#if defined(CONFIG_HAS_DATAFLASH) /* Print the lines. * * We buffer all read data, so we can make sure data is read only @@ -140,48 +138,64 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) nbytes = length * size; do { char linebuf[DISP_LINE_LEN]; - void* p; + uint *uip = (uint *)linebuf; + ushort *usp = (ushort *)linebuf; + u_char *ucp = (u_char *)linebuf; +#ifdef CONFIG_HAS_DATAFLASH + int rc; +#endif + printf("%08lx:", addr); linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; - rc = read_dataflash(addr, (linebytes/size)*size, linebuf); - p = (rc == DATAFLASH_OK) ? linebuf : (void*)addr; - print_buffer(addr, p, size, linebytes/size, DISP_LINE_LEN/size); +#ifdef CONFIG_HAS_DATAFLASH + if ((rc = read_dataflash(addr, (linebytes/size)*size, linebuf)) == DATAFLASH_OK){ + /* if outside dataflash */ + /*if (rc != 1) { + dataflash_perror (rc); + return (1); + }*/ + for (i=0; i 0x7e)) + putc ('.'); + else + printf("%c", *cp); + cp++; + } + putc ('\n'); nbytes -= linebytes; - addr += linebytes; if (ctrlc()) { rc = 1; break; } } while (nbytes > 0); -#else - -# if defined(CONFIG_BLACKFIN) - /* See if we're trying to display L1 inst */ - if (addr_bfin_on_chip_mem(addr)) { - char linebuf[DISP_LINE_LEN]; - ulong linebytes, nbytes = length * size; - do { - linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; - memcpy(linebuf, (void *)addr, linebytes); - print_buffer(addr, linebuf, size, linebytes/size, DISP_LINE_LEN/size); - - nbytes -= linebytes; - addr += linebytes; - if (ctrlc()) { - rc = 1; - break; - } - } while (nbytes > 0); - } else -# endif - - { - /* Print the lines. */ - print_buffer(addr, (void*)addr, size, length, DISP_LINE_LEN/size); - addr += size*length; - } -#endif dp_last_addr = addr; dp_last_length = length; @@ -332,13 +346,6 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #endif -#ifdef CONFIG_BLACKFIN - if (addr_bfin_on_chip_mem(addr1) || addr_bfin_on_chip_mem(addr2)) { - puts ("Comparison with L1 instruction memory not supported.\n\r"); - return 0; - } -#endif - ngood = 0; while (count-- > 0) { @@ -418,7 +425,7 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* check if we are copying to Flash */ if ( (addr2info(dest) != NULL) #ifdef CONFIG_HAS_DATAFLASH - && (!addr_dataflash(dest)) + && (!addr_dataflash(addr)) #endif ) { int rc; @@ -435,7 +442,10 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #endif -#if defined(CONFIG_CMD_MMC) +#if 0 +/* TODO */ +/*#if (CONFIG_COMMANDS & CFG_CMD_MMC)*/ + if (mmc2info(dest)) { int rc; @@ -493,11 +503,7 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } /* Check if we are copying from DataFlash to RAM */ - if (addr_dataflash(addr) && !addr_dataflash(dest) -#ifndef CFG_NO_FLASH - && (addr2info(dest) == NULL) -#endif - ){ + if (addr_dataflash(addr) && !addr_dataflash(dest) && (addr2info(dest)==NULL) ){ int rc; rc = read_dataflash(addr, count * size, (char *) dest); if (rc != 1) { @@ -513,14 +519,6 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #endif -#ifdef CONFIG_BLACKFIN - /* See if we're copying to/from L1 inst */ - if (addr_bfin_on_chip_mem(dest) || addr_bfin_on_chip_mem(addr)) { - memcpy((void *)dest, (void *)addr, count * size); - return 0; - } -#endif - while (count-- > 0) { if (size == 4) *((ulong *)dest) = *((ulong *)addr); @@ -702,10 +700,9 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) vu_long *addr, *start, *end; ulong val; ulong readback; - int rcode = 0; #if defined(CFG_ALT_MEMTEST) - vu_long len; + vu_long addr_mask; vu_long offset; vu_long test_offset; vu_long pattern; @@ -733,6 +730,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #else ulong incr; ulong pattern; + int rcode = 0; #endif if (argc > 1) { @@ -841,19 +839,26 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * all possible. * * Returns: 0 if the test succeeds, 1 if the test fails. + * + * ## NOTE ## Be sure to specify start and end + * addresses such that addr_mask has + * lots of bits set. For example an + * address range of 01000000 02000000 is + * bad while a range of 01000000 + * 01ffffff is perfect. */ - len = ((ulong)end - (ulong)start)/sizeof(vu_long); + addr_mask = ((ulong)end - (ulong)start)/sizeof(vu_long); pattern = (vu_long) 0xaaaaaaaa; anti_pattern = (vu_long) 0x55555555; - PRINTF("%s:%d: length = 0x%.8lx\n", + PRINTF("%s:%d: addr mask = 0x%.8lx\n", __FUNCTION__, __LINE__, - len); + addr_mask); /* * Write the default pattern at each of the * power-of-two offsets. */ - for (offset = 1; offset < len; offset <<= 1) { + for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) { start[offset] = pattern; } @@ -863,7 +868,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) test_offset = 0; start[test_offset] = anti_pattern; - for (offset = 1; offset < len; offset <<= 1) { + for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) { temp = start[offset]; if (temp != pattern) { printf ("\nFAILURE: Address bit stuck high @ 0x%.8lx:" @@ -873,15 +878,14 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } start[test_offset] = pattern; - WATCHDOG_RESET(); /* * Check for addr bits stuck low or shorted. */ - for (test_offset = 1; test_offset < len; test_offset <<= 1) { + for (test_offset = 1; (test_offset & addr_mask) != 0; test_offset <<= 1) { start[test_offset] = anti_pattern; - for (offset = 1; offset < len; offset <<= 1) { + for (offset = 1; (offset & addr_mask) != 0; offset <<= 1) { temp = start[offset]; if ((temp != pattern) && (offset != test_offset)) { printf ("\nFAILURE: Address bit stuck low or shorted @" @@ -911,7 +915,6 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Fill memory with a known pattern. */ for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) { - WATCHDOG_RESET(); start[offset] = pattern; } @@ -919,7 +922,6 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Check each location and invert it for the second pass. */ for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) { - WATCHDOG_RESET(); temp = start[offset]; if (temp != pattern) { printf ("\nFAILURE (read/write) @ 0x%.8lx:" @@ -936,7 +938,6 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Check each location for the inverted pattern and zero it. */ for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) { - WATCHDOG_RESET(); anti_pattern = ~pattern; temp = start[offset]; if (temp != anti_pattern) { @@ -963,7 +964,6 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) pattern, ""); for (addr=start,val=pattern; addr #include + +#if (CONFIG_COMMANDS & CFG_CMD_MII) #include +#ifdef CONFIG_TERSE_MII +/* + * Display values from last command. + */ +uint last_op; +uint last_addr; +uint last_data; +uint last_reg; + +/* + * MII device/info/read/write + * + * Syntax: + * mii device {devname} + * mii info {addr} + * mii read {addr} {reg} + * mii write {addr} {reg} {data} + */ +int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + char op; + unsigned char addr, reg; + unsigned short data; + int rcode = 0; + char *devname; + + if (argc < 2) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + +#if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2) + mii_init (); +#endif + + /* + * We use the last specified parameters, unless new ones are + * entered. + */ + op = last_op; + addr = last_addr; + data = last_data; + reg = last_reg; + + if ((flag & CMD_FLAG_REPEAT) == 0) { + op = argv[1][0]; + if (argc >= 3) + addr = simple_strtoul (argv[2], NULL, 16); + if (argc >= 4) + reg = simple_strtoul (argv[3], NULL, 16); + if (argc >= 5) + data = simple_strtoul (argv[4], NULL, 16); + } + + /* use current device */ + devname = miiphy_get_current_dev(); + + /* + * check device/read/write/list. + */ + if (op == 'i') { + unsigned char j, start, end; + unsigned int oui; + unsigned char model; + unsigned char rev; + + /* + * Look for any and all PHYs. Valid addresses are 0..31. + */ + if (argc >= 3) { + start = addr; end = addr + 1; + } else { + start = 0; end = 31; + } + + for (j = start; j < end; j++) { + if (miiphy_info (devname, j, &oui, &model, &rev) == 0) { + printf ("PHY 0x%02X: " + "OUI = 0x%04X, " + "Model = 0x%02X, " + "Rev = 0x%02X, " + "%3dbaseT, %s\n", + j, oui, model, rev, + miiphy_speed (devname, j), + (miiphy_duplex (devname, j) == FULL) + ? "FDX" : "HDX"); + } else { + puts ("Error reading info from the PHY\n"); + } + } + } else if (op == 'r') { + if (miiphy_read (devname, addr, reg, &data) != 0) { + puts ("Error reading from the PHY\n"); + rcode = 1; + } else { + printf ("%04X\n", data & 0x0000FFFF); + } + } else if (op == 'w') { + if (miiphy_write (devname, addr, reg, data) != 0) { + puts ("Error writing to the PHY\n"); + rcode = 1; + } + } else if (op == 'd') { + if (argc == 2) + miiphy_listdev (); + else + miiphy_set_current_dev (argv[2]); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + /* + * Save the parameters for repeats. + */ + last_op = op; + last_addr = addr; + last_data = data; + last_reg = reg; + + return rcode; +} + +/***************************************************/ + +U_BOOT_CMD( + mii, 5, 1, do_mii, + "mii - MII utility commands\n", + "device - list available devices\n" + "mii device - set current device\n" + "mii info - display MII PHY info\n" + "mii read - read MII PHY register \n" + "mii write - write MII PHY register \n" +); + +#else /* ! CONFIG_TERSE_MII ================================================= */ + typedef struct _MII_reg_desc_t { ushort regno; char * name; @@ -301,12 +440,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int rcode = 0; char *devname; - if (argc < 2) { - printf("Usage:\n%s\n", cmdtp->usage); - return 1; - } - -#if defined(CONFIG_MII_INIT) +#ifdef CONFIG_8xx mii_init (); #endif @@ -364,13 +498,13 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) "OUI = 0x%04X, " "Model = 0x%02X, " "Rev = 0x%02X, " - "%3dbase%s, %s\n", + "%3dbaseT, %s\n", j, oui, model, rev, miiphy_speed (devname, j), - miiphy_is_1000base_x (devname, j) - ? "X" : "T", (miiphy_duplex (devname, j) == FULL) ? "FDX" : "HDX"); + } else { + puts ("Error reading info from the PHY\n"); } } } else if (op[0] == 'r') { @@ -462,3 +596,7 @@ U_BOOT_CMD( "mii dump - pretty-print (0-5 only)\n" "Addr and/or reg may be ranges, e.g. 2-7.\n" ); + +#endif /* CONFIG_TERSE_MII */ + +#endif /* CFG_CMD_MII */ diff --git a/common/cmd_misc.c b/common/cmd_misc.c index 126b538ce..67ee9e8a8 100644 --- a/common/cmd_misc.c +++ b/common/cmd_misc.c @@ -27,6 +27,8 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_MISC) + int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong start = get_timer(0); @@ -50,7 +52,7 @@ int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } /* Implemented in $(CPU)/interrupts.c */ -#if defined(CONFIG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); U_BOOT_CMD( @@ -58,11 +60,13 @@ U_BOOT_CMD( "irqinfo - print information about IRQs\n", NULL ); -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ U_BOOT_CMD( - sleep , 2, 1, do_sleep, + sleep , 2, 2, do_sleep, "sleep - delay execution for some time\n", "N\n" " - delay execution for N seconds (N is _decimal_ !!!)\n" ); + +#endif /* CFG_CMD_MISC */ diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 25c970257..8776dac03 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -23,19 +23,94 @@ #include #include + +#if (CONFIG_COMMANDS & CFG_CMD_MMC) + #include +int mmc_flag[2] = {0, 0} ; int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - if (mmc_init (1) != 0) { - printf ("No MMC card found\n"); - return 1; + ulong src_addr, dst_addr, size; + char *cmd; + /*Default Setting to SLOT-0*/ + int slot_no = 0, mmc_cont = 0; + + if (argc < 2) { + goto mmc_cmd_usage; + } else if (argc == 2) { + if (strncmp(argv[0], "mmcinit", 7) != 0) { + goto mmc_cmd_usage; + } else { + slot_no = simple_strtoul(argv[1], NULL, 16); + if ((slot_no != 0) && (slot_no != 1)) + goto mmc_cmd_usage; + if (mmc_init(slot_no) != 0) { + printf("No MMC card found\n"); + return 1; + } else { + mmc_flag[slot_no] = 1; + } + } + } else { + mmc_cont = simple_strtoul(argv[1], NULL, 16); + if ((mmc_cont != 0) && (mmc_cont != 1)) + goto mmc_cmd_usage; + + if (!mmc_flag[mmc_cont]) { + printf("Try to do init First b4 read/write\n"); + goto mmc_cmd_usage; + } + + cmd = argv[2]; + if (strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 + && strncmp(cmd, "erase", 5) != 0) + goto mmc_cmd_usage; + + if (strcmp(cmd, "erase") == 0) { + if (argc != 5) { + goto mmc_cmd_usage; + } else { + src_addr = simple_strtoul(argv[3], NULL, 16); + size = simple_strtoul(argv[4], NULL, 16); + mmc_erase(mmc_cont, src_addr, size); + } + } + if (strcmp(cmd, "read") == 0) { + if (argc != 6) { + goto mmc_cmd_usage; + } else { + src_addr = simple_strtoul(argv[3], NULL, 16); + dst_addr = simple_strtoul(argv[4], NULL, 16); + size = simple_strtoul(argv[5], NULL, 16); + mmc_read(mmc_cont, src_addr, + (unsigned char *)dst_addr, size); + } + } + if (strcmp(cmd, "write") == 0) { + if (argc != 6) { + goto mmc_cmd_usage; + } else { + src_addr = simple_strtoul(argv[3], NULL, 16); + dst_addr = simple_strtoul(argv[4], NULL, 16); + size = simple_strtoul(argv[5], NULL, 16); + mmc_write(mmc_cont, (unsigned char *)src_addr, + dst_addr, size); + } + } } return 0; + +mmc_cmd_usage: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; } -U_BOOT_CMD( - mmcinit, 1, 0, do_mmc, - "mmcinit - init mmc card\n", - NULL -); +U_BOOT_CMD(mmcinit, 6, 1, do_mmc, + "mmcinit - initialize mmc\n" + "mmc - Read/write/Erase mmc\n", + " \n" + "mmc read \n" + "mmc write \n" + "mmc erase \n"); +#endif /* CFG_CMD_MMC */ diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 9e38bf768..165f621f3 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -19,16 +19,24 @@ */ #include -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include #include #include #include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + #include #include -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) /* parition handling routines */ int mtdparts_init(void); @@ -37,6 +45,8 @@ int find_dev_and_part(const char *id, struct mtd_device **dev, u8 *part_num, struct part_info **part); #endif +extern nand_info_t nand_info[]; /* info for NAND chips */ + static int nand_dump_oob(nand_info_t *nand, ulong off) { return 0; @@ -55,11 +65,11 @@ static int nand_dump(nand_info_t *nand, ulong off) off &= ~(nand->oobblock - 1); i = nand_read_raw(nand, buf, off, nand->oobblock, nand->oobsize); if (i < 0) { - printf("Error (%d) reading page %08lx\n", i, off); + printf("Error (%d) reading page %08x\n", i, off); free(buf); return 1; } - printf("Page %08lx dump:\n", off); + printf("Page %08x dump:\n", off); i = nand->oobblock >> 4; p = buf; while (i--) { printf( "\t%02x %02x %02x %02x %02x %02x %02x %02x" @@ -91,10 +101,10 @@ static inline int str2long(char *p, ulong *num) } static int -arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size) +arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, ulong *size) { int idx = nand_curr_device; -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) struct mtd_device *dev; struct part_info *part; u8 pnum; @@ -108,7 +118,7 @@ arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size } *off = part->offset; if (argc >= 2) { - if (!(str2long(argv[1], (ulong *)size))) { + if (!(str2long(argv[1], size))) { printf("'%s' is not a number\n", argv[1]); return -1; } @@ -134,7 +144,7 @@ arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size } if (argc >= 2) { - if (!(str2long(argv[1], (ulong *)size))) { + if (!(str2long(argv[1], size))) { printf("'%s' is not a number\n", argv[1]); return -1; } @@ -142,29 +152,33 @@ arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size *size = nand->size - *off; } -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) out: #endif printf("device %d ", idx); if (*size == nand->size) puts("whole chip\n"); else - printf("offset 0x%lx, size 0x%x\n", *off, *size); + printf("offset 0x%x, size 0x%x\n", *off, *size); return 0; } +#if defined(CONFIG_OMAP) && \ + (defined(CONFIG_3430LABRADOR) || defined(CONFIG_OMAP3EVM)) || \ + defined(CONFIG_3430ZOOM2) || defined(CONFIG_3630SDP) +extern void omap_nand_switch_ecc(nand_info_t *nand, int hardware); +extern int nand_unlock(nand_info_t *nand, ulong off, ulong size); +#else +#define omap_nand_switch_ecc(x, y) do {} while(0) +#define nand_unlock(n, o, s) !(1) +#endif int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i, dev, ret; - ulong addr, off; - size_t size; + ulong addr, off, size; char *cmd, *s; nand_info_t *nand; -#ifdef CFG_NAND_QUIET - int quiet = CFG_NAND_QUIET; -#else int quiet = 0; -#endif const char *quiet_str = getenv("quiet"); /* at least two arguments please */ @@ -181,7 +195,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) putc('\n'); for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) { if (nand_info[i].name) - printf("Device %d: %s, sector size %u KiB\n", + printf("Device %d: %s, sector size %lu KiB\n", i, nand_info[i].name, nand_info[i].erasesize >> 10); } @@ -207,23 +221,15 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf("Device %d: %s", dev, nand_info[dev].name); puts("... is now current device\n"); nand_curr_device = dev; - -#ifdef CFG_NAND_SELECT_DEVICE - /* - * Select the chip in the board/cpu specific driver - */ - board_nand_select_device(nand_info[dev].priv, dev); -#endif - return 0; } - if (strcmp(cmd, "bad") != 0 && strcmp(cmd, "erase") != 0 && + if (strncmp(cmd, "bad", 3) != 0 && strncmp(cmd, "erase", 5) != 0 && strncmp(cmd, "dump", 4) != 0 && strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && - strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && - strcmp(cmd, "biterr") != 0 && - strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 ) + strncmp(cmd, "scrub", 5) != 0 && strncmp(cmd, "markbad", 7) != 0 && + strncmp(cmd, "biterr", 6) != 0 && strncmp(cmd, "ecc", 3) != 0 && + strncmp(cmd, "lock", 4) != 0 && strncmp(cmd, "unlock", 6) != 0 ) goto usage; /* the following commands operate on the current device */ @@ -238,7 +244,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) printf("\nDevice %d bad blocks:\n", nand_curr_device); for (off = 0; off < nand->size; off += nand->erasesize) if (nand_block_isbad(nand, off)) - printf(" %08lx\n", off); + printf(" %08x\n", off); return 0; } @@ -306,6 +312,18 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return ret == 0 ? 1 : 0; } + if (strncmp(cmd, "ecc", 3) == 0) { + if (argc < 2) + goto usage; + if (strncmp(argv[2], "hw", 2) == 0) + omap_nand_switch_ecc(nand, 1); + else if (strncmp(argv[2], "sw", 2) == 0) + omap_nand_switch_ecc(nand, 0); + else + goto usage; + + return 0; + } /* read write */ if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { @@ -346,15 +364,38 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) opts.quiet = quiet; ret = nand_write_opts(nand, &opts); } - } else if (s != NULL && !strcmp(s, ".oob")) { - /* read out-of-band data */ - if (read) - ret = nand->read_oob(nand, off, size, &size, - (u_char *) addr); - else - ret = nand->write_oob(nand, off, size, &size, - (u_char *) addr); - } else { + } else if (s != NULL && (!strcmp(s, ".raw"))) { + if (read) { + /* read */ + nand_read_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char *) addr; + opts.length = size; + opts.offset = off; + opts.quiet = quiet; + opts.readoob = 1; + ret = nand_read_opts(nand, &opts); + } + } +#ifdef CFG_NAND_YAFFS_WRITE + else if (!read && s != NULL && + (!strcmp(s, ".yaffs") || !strcmp(s, ".yaffs1"))) { + nand_write_options_t opts; + memset(&opts, 0, sizeof(opts)); + opts.buffer = (u_char *) addr; + opts.length = size; + opts.offset = off; + opts.pad = 0; + opts.blockalign = 1; + opts.quiet = quiet; + opts.writeoob = 1; + opts.autoplace = 1; + if (s[6] == '1') + opts.forceyaffs = 1; + ret = nand_write_opts(nand, &opts); + } +#endif + else { if (read) ret = nand_read(nand, off, &size, (u_char *)addr); else @@ -417,7 +458,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (off == nand->size - nand->oobblock || (s != last_status && off != 0)) { - printf("%08lx - %08lx: %8lu pages %s%s%s\n", + printf("%08x - %08x: %8d pages %s%s%s\n", block_start, off-1, (off-block_start)/nand->oobblock, @@ -443,6 +484,9 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (arg_off_size(argc - 2, argv + 2, nand, &off, &size) < 0) return 1; + if (off == 0 && size == 0) + return 1; + if (!nand_unlock(nand, off, size)) { puts("NAND flash successfully unlocked\n"); } else { @@ -462,9 +506,16 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand - NAND sub-system\n", "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" - "nand read[.jffs2] - addr off|partition size\n" - "nand write[.jffs2] - addr off|partition size - read/write `size' bytes starting\n" + "nand read[.jffs2 /.i/.e] - addr off|partition size\n" + "nand write[.jffs2/.i/.e] - addr off|partiton size - read/write `size' bytes starting\n" " at offset `off' to/from memory address `addr'\n" +#ifdef CFG_NAND_YAFFS_WRITE + "nand write[.yaffs[1]] - addr off|partition size - write `size' byte yaffs image\n" + " starting at offset `off' from memory address `addr' (.yaffs1 for 512+16 NAND)\n" +#endif + "nand read.raw - addr off|partition size\n" + " at offset `off' from memory address `addr'\n" + " buffer include normal data and oob data \n" "nand erase [clean] [off size] - erase `size' bytes from\n" " offset `off' (entire device if not specified)\n" "nand bad - show bad blocks\n" @@ -472,102 +523,47 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand scrub - really clean NAND erasing bad blocks (UNSAFE)\n" "nand markbad off - mark bad block at offset (UNSAFE)\n" "nand biterr off - make a bit error at offset (UNSAFE)\n" + "nand ecc [hw/sw] - switch the ecc calculation algorithm \n" "nand lock [tight] [status] - bring nand to lock state or display locked pages\n" - "nand unlock [offset] [size] - unlock section\n"); + "nand unlock off size - unlock `size' bytes from\n" + " offset `off' (entire device if not specified)\n"); static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, ulong offset, ulong addr, char *cmd) { int r; - char *ep, *s; - size_t cnt; + char *ep; + ulong cnt; image_header_t *hdr; - int jffs2 = 0; -#if defined(CONFIG_FIT) - const void *fit_hdr = NULL; -#endif - - s = strchr(cmd, '.'); - if (s != NULL && - (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) - jffs2 = 1; printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset); cnt = nand->oobblock; - if (jffs2) { - nand_read_options_t opts; - memset(&opts, 0, sizeof(opts)); - opts.buffer = (u_char*) addr; - opts.length = cnt; - opts.offset = offset; - opts.quiet = 1; - r = nand_read_opts(nand, &opts); - } else { - r = nand_read(nand, offset, &cnt, (u_char *) addr); - } - + r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); - show_boot_progress (-56); - return 1; - } - show_boot_progress (56); - - switch (genimg_get_format ((void *)addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *)addr; - - show_boot_progress (57); - image_print_contents (hdr); - - cnt = image_get_image_size (hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (const void *)addr; - puts ("Fit image detected...\n"); - - cnt = fit_get_size (fit_hdr); - break; -#endif - default: - show_boot_progress (-57); - puts ("** Unknown image type\n"); + SHOW_BOOT_PROGRESS(-1); return 1; } - if (jffs2) { - nand_read_options_t opts; - memset(&opts, 0, sizeof(opts)); - opts.buffer = (u_char*) addr; - opts.length = cnt; - opts.offset = offset; - opts.quiet = 1; - r = nand_read_opts(nand, &opts); - } else { - r = nand_read(nand, offset, &cnt, (u_char *) addr); + hdr = (image_header_t *) addr; + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); + SHOW_BOOT_PROGRESS(-1); + return 1; } + print_image_hdr(hdr); + + cnt = (ntohl(hdr->ih_size) + sizeof (image_header_t)); + + r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); - show_boot_progress (-58); + SHOW_BOOT_PROGRESS(-1); return 1; } - show_boot_progress (58); - -#if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { - if (!fit_check_format (fit_hdr)) { - show_boot_progress (-150); - puts ("** Bad FIT image format\n"); - return 1; - } - show_boot_progress (151); - fit_print_contents (fit_hdr); - } -#endif /* Loading ok, update default load address */ @@ -594,7 +590,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) char *boot_device = NULL; int idx; ulong addr, offset = 0; -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) struct mtd_device *dev; struct part_info *part; u8 pnum; @@ -610,7 +606,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (argc > 3) goto usage; if (argc == 3) - addr = simple_strtoul(argv[1], NULL, 16); + addr = simple_strtoul(argv[2], NULL, 16); else addr = CFG_LOAD_ADDR; return nand_load_image(cmdtp, &nand_info[dev->id->num], @@ -619,7 +615,6 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } #endif - show_boot_progress(52); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -639,39 +634,36 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) offset = simple_strtoul(argv[3], NULL, 16); break; default: -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) usage: #endif printf("Usage:\n%s\n", cmdtp->usage); - show_boot_progress(-53); + SHOW_BOOT_PROGRESS(-1); return 1; } - show_boot_progress(53); if (!boot_device) { puts("\n** No boot device **\n"); - show_boot_progress(-54); + SHOW_BOOT_PROGRESS(-1); return 1; } - show_boot_progress(54); idx = simple_strtoul(boot_device, NULL, 16); if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) { printf("\n** Device %d not available\n", idx); - show_boot_progress(-55); + SHOW_BOOT_PROGRESS(-1); return 1; } - show_boot_progress(55); return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]); } U_BOOT_CMD(nboot, 4, 1, do_nandboot, "nboot - boot from NAND device\n", - "[.jffs2] [partition] | [[[loadAddr] dev] offset]\n"); + "[partition] | [[[loadAddr] dev] offset]\n"); -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ #else /* CFG_NAND_LEGACY */ /* @@ -684,14 +676,14 @@ U_BOOT_CMD(nboot, 4, 1, do_nandboot, #include #include -#ifdef CONFIG_show_boot_progress +#ifdef CONFIG_SHOW_BOOT_PROGRESS # include -# define show_boot_progress(arg) show_boot_progress(arg) +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) #else -# define show_boot_progress(arg) +# define SHOW_BOOT_PROGRESS(arg) #endif -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #include #if 0 #include @@ -748,183 +740,178 @@ extern int nand_write_oob(struct nand_chip *nand, size_t ofs, size_t len, size_t *retlen, const u_char *buf); -int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - int rcode = 0; + int rcode = 0; - switch (argc) { - case 0: - case 1: - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - case 2: - if (strcmp (argv[1], "info") == 0) { - int i; + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strcmp(argv[1],"info") == 0) { + int i; - putc ('\n'); - - for (i = 0; i < CFG_MAX_NAND_DEVICE; ++i) { - if (nand_dev_desc[i].ChipID == - NAND_ChipID_UNKNOWN) - continue; /* list only known devices */ - printf ("Device %d: ", i); - nand_print (&nand_dev_desc[i]); - } - return 0; - - } else if (strcmp (argv[1], "device") == 0) { - if ((curr_device < 0) - || (curr_device >= CFG_MAX_NAND_DEVICE)) { - puts ("\nno devices available\n"); - return 1; - } - printf ("\nDevice %d: ", curr_device); - nand_print (&nand_dev_desc[curr_device]); - return 0; - - } else if (strcmp (argv[1], "bad") == 0) { - if ((curr_device < 0) - || (curr_device >= CFG_MAX_NAND_DEVICE)) { - puts ("\nno devices available\n"); - return 1; - } - printf ("\nDevice %d bad blocks:\n", curr_device); - nand_print_bad (&nand_dev_desc[curr_device]); - return 0; + putc ('\n'); + for (i=0; iusage); - return 1; - case 3: - if (strcmp (argv[1], "device") == 0) { - int dev = (int) simple_strtoul (argv[2], NULL, 10); + return 0; - printf ("\nDevice %d: ", dev); - if (dev >= CFG_MAX_NAND_DEVICE) { - puts ("unknown device\n"); - return 1; + } else if (strcmp(argv[1],"device") == 0) { + if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { + puts ("\nno devices available\n"); + return 1; + } + printf ("\nDevice %d: ", curr_device); + nand_print(&nand_dev_desc[curr_device]); + return 0; + + } else if (strcmp(argv[1],"bad") == 0) { + if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) { + puts ("\nno devices available\n"); + return 1; + } + printf ("\nDevice %d bad blocks:\n", curr_device); + nand_print_bad(&nand_dev_desc[curr_device]); + return 0; + + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strcmp(argv[1],"device") == 0) { + int dev = (int)simple_strtoul(argv[2], NULL, 10); + + printf ("\nDevice %d: ", dev); + if (dev >= CFG_MAX_NAND_DEVICE) { + puts ("unknown device\n"); + return 1; + } + nand_print(&nand_dev_desc[dev]); + /*nand_print (dev);*/ + + if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { + return 1; + } + + curr_device = dev; + + puts ("... is now current device\n"); + + return 0; + } + else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) { + struct nand_chip* nand = &nand_dev_desc[curr_device]; + ulong off = 0; + ulong size = nand->totlen; + int ret; + + printf ("\nNAND erase: device %d offset %ld, size %ld ... ", + curr_device, off, size); + + ret = nand_legacy_erase (nand, off, size, 1); + + printf("%s\n", ret ? "ERROR" : "OK"); + + return ret; + } + + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + default: + /* at least 4 args */ + + if (strncmp(argv[1], "read", 4) == 0 || + strncmp(argv[1], "write", 5) == 0) { + ulong addr = simple_strtoul(argv[2], NULL, 16); + ulong off = simple_strtoul(argv[3], NULL, 16); + ulong size = simple_strtoul(argv[4], NULL, 16); + int cmd = (strncmp(argv[1], "read", 4) == 0) ? + NANDRW_READ : NANDRW_WRITE; + int ret, total; + char* cmdtail = strchr(argv[1], '.'); + + if (cmdtail && !strncmp(cmdtail, ".oob", 2)) { + /* read out-of-band data */ + if (cmd & NANDRW_READ) { + ret = nand_read_oob(nand_dev_desc + curr_device, + off, size, (size_t *)&total, + (u_char*)addr); } - nand_print (&nand_dev_desc[dev]); - /*nand_print (dev); */ - - if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) { - return 1; + else { + ret = nand_write_oob(nand_dev_desc + curr_device, + off, size, (size_t *)&total, + (u_char*)addr); } - - curr_device = dev; - - puts ("... is now current device\n"); - - return 0; - } else if (strcmp (argv[1], "erase") == 0 - && strcmp (argv[2], "clean") == 0) { - struct nand_chip *nand = &nand_dev_desc[curr_device]; - ulong off = 0; - ulong size = nand->totlen; - int ret; - - printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size); - - ret = nand_legacy_erase (nand, off, size, 1); - - printf ("%s\n", ret ? "ERROR" : "OK"); - return ret; } - - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - default: - /* at least 4 args */ - - if (strncmp (argv[1], "read", 4) == 0 || - strncmp (argv[1], "write", 5) == 0) { - ulong addr = simple_strtoul (argv[2], NULL, 16); - off_t off = simple_strtoul (argv[3], NULL, 16); - size_t size = simple_strtoul (argv[4], NULL, 16); - int cmd = (strncmp (argv[1], "read", 4) == 0) ? - NANDRW_READ : NANDRW_WRITE; - size_t total; - int ret; - char *cmdtail = strchr (argv[1], '.'); - - if (cmdtail && !strncmp (cmdtail, ".oob", 2)) { - /* read out-of-band data */ - if (cmd & NANDRW_READ) { - ret = nand_read_oob (nand_dev_desc + curr_device, - off, size, &total, - (u_char *) addr); - } else { - ret = nand_write_oob (nand_dev_desc + curr_device, - off, size, &total, - (u_char *) addr); - } - return ret; - } else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2)) - cmd |= NANDRW_JFFS2; /* skip bad blocks */ - else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 2)) { - cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ - if (cmd & NANDRW_READ) - cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ - } + else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2)) + cmd |= NANDRW_JFFS2; /* skip bad blocks */ + else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) { + cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ + if (cmd & NANDRW_READ) + cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ + } #ifdef SXNI855T - /* need ".e" same as ".j" for compatibility with older units */ - else if (cmdtail && !strcmp (cmdtail, ".e")) - cmd |= NANDRW_JFFS2; /* skip bad blocks */ + /* need ".e" same as ".j" for compatibility with older units */ + else if (cmdtail && !strcmp(cmdtail, ".e")) + cmd |= NANDRW_JFFS2; /* skip bad blocks */ #endif #ifdef CFG_NAND_SKIP_BAD_DOT_I - /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ - /* ".i" for image -> read skips bad block (no 0xff) */ - else if (cmdtail && !strcmp (cmdtail, ".i")) { - cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ - if (cmd & NANDRW_READ) - cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ - } + /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ + /* ".i" for image -> read skips bad block (no 0xff) */ + else if (cmdtail && !strcmp(cmdtail, ".i")) { + cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ + if (cmd & NANDRW_READ) + cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ + } #endif /* CFG_NAND_SKIP_BAD_DOT_I */ - else if (cmdtail) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } - - printf ("\nNAND %s: device %d offset %ld, size %lu ...\n", - (cmd & NANDRW_READ) ? "read" : "write", - curr_device, off, (ulong)size); - - ret = nand_legacy_rw (nand_dev_desc + curr_device, - cmd, off, size, - &total, - (u_char *) addr); - - printf (" %d bytes %s: %s\n", total, - (cmd & NANDRW_READ) ? "read" : "written", - ret ? "ERROR" : "OK"); - - return ret; - } else if (strcmp (argv[1], "erase") == 0 && - (argc == 4 || strcmp ("clean", argv[2]) == 0)) { - int clean = argc == 5; - ulong off = - simple_strtoul (argv[2 + clean], NULL, 16); - ulong size = - simple_strtoul (argv[3 + clean], NULL, 16); - int ret; - - printf ("\nNAND erase: device %d offset %ld, size %ld ...\n", - curr_device, off, size); - - ret = nand_legacy_erase (nand_dev_desc + curr_device, - off, size, clean); - - printf ("%s\n", ret ? "ERROR" : "OK"); - - return ret; - } else { + else if (cmdtail) { printf ("Usage:\n%s\n", cmdtp->usage); - rcode = 1; + return 1; } - return rcode; + printf ("\nNAND %s: device %d offset %ld, size %ld ...\n", + (cmd & NANDRW_READ) ? "read" : "write", + curr_device, off, size); + + ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size, + (size_t *)&total, (u_char*)addr); + + printf (" %d bytes %s: %s\n", total, + (cmd & NANDRW_READ) ? "read" : "written", + ret ? "ERROR" : "OK"); + + return ret; + } else if (strcmp(argv[1],"erase") == 0 && + (argc == 4 || strcmp("clean", argv[2]) == 0)) { + int clean = argc == 5; + ulong off = simple_strtoul(argv[2 + clean], NULL, 16); + ulong size = simple_strtoul(argv[3 + clean], NULL, 16); + int ret; + + printf ("\nNAND erase: device %d offset %ld, size %ld ...\n", + curr_device, off, size); + + ret = nand_legacy_erase (nand_dev_desc + curr_device, + off, size, clean); + + printf("%s\n", ret ? "ERROR" : "OK"); + + return ret; + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + rcode = 1; } + + return rcode; + } } U_BOOT_CMD( @@ -952,11 +939,6 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong offset = 0; image_header_t *hdr; int rcode = 0; -#if defined(CONFIG_FIT) - const void *fit_hdr = NULL; -#endif - - show_boot_progress (52); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -977,27 +959,24 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - show_boot_progress (-53); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (53); if (!boot_device) { puts ("\n** No boot device **\n"); - show_boot_progress (-54); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (54); dev = simple_strtoul(boot_device, &ep, 16); if ((dev >= CFG_MAX_NAND_DEVICE) || (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) { printf ("\n** Device %d not available\n", dev); - show_boot_progress (-55); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (55); printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n", dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR, @@ -1006,55 +985,31 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset, SECTORSIZE, NULL, (u_char *)addr)) { printf ("** Read error on %d\n", dev); - show_boot_progress (-56); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (56); - switch (genimg_get_format ((void *)addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *)addr; - image_print_contents (hdr); + hdr = (image_header_t *)addr; - cnt = image_get_image_size (hdr); + if (ntohl(hdr->ih_magic) == IH_MAGIC) { + + print_image_hdr (hdr); + + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); cnt -= SECTORSIZE; - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (const void *)addr; - puts ("Fit image detected...\n"); - - cnt = fit_get_size (fit_hdr); - break; -#endif - default: - show_boot_progress (-57); - puts ("** Unknown image type\n"); + } else { + printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic)); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (57); if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt, NULL, (u_char *)(addr+SECTORSIZE))) { printf ("** Read error on %d\n", dev); - show_boot_progress (-58); + SHOW_BOOT_PROGRESS (-1); return 1; } - show_boot_progress (58); - -#if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { - if (!fit_check_format (fit_hdr)) { - show_boot_progress (-150); - puts ("** Bad FIT image format\n"); - return 1; - } - show_boot_progress (151); - fit_print_contents (fit_hdr); - } -#endif /* Loading ok, update default load address */ @@ -1082,6 +1037,6 @@ U_BOOT_CMD( "loadAddr dev\n" ); -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ #endif /* CFG_NAND_LEGACY */ diff --git a/common/cmd_net.c b/common/cmd_net.c index 79e910c76..2cb2c5d34 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -28,6 +28,9 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_NET) + + extern int do_bootm (cmd_tbl_t *, int, int, char *[]); static int netboot_common (proto_t, cmd_tbl_t *, int , char *[]); @@ -51,7 +54,7 @@ int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( tftpboot, 3, 1, do_tftpb, "tftpboot- boot image via network using TFTP protocol\n", - "[loadAddress] [[hostIPaddr:]bootfilename]\n" + "[loadAddress] [bootfilename]\n" ); int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -65,7 +68,7 @@ U_BOOT_CMD( "[loadAddress] [bootfilename]\n" ); -#if defined(CONFIG_CMD_DHCP) +#if (CONFIG_COMMANDS & CFG_CMD_DHCP) int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { return netboot_common(DHCP, cmdtp, argc, argv); @@ -76,9 +79,9 @@ U_BOOT_CMD( "dhcp\t- invoke DHCP client to obtain IP/boot params\n", "\n" ); -#endif +#endif /* CFG_CMD_DHCP */ -#if defined(CONFIG_CMD_NFS) +#if (CONFIG_COMMANDS & CFG_CMD_NFS) int do_nfs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { return netboot_common(NFS, cmdtp, argc, argv); @@ -87,9 +90,9 @@ int do_nfs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( nfs, 3, 1, do_nfs, "nfs\t- boot image via network using NFS protocol\n", - "[loadAddress] [[hostIPaddr:]bootfilename]\n" + "[loadAddress] [host ip addr:bootfilename]\n" ); -#endif +#endif /* CFG_CMD_NFS */ static void netboot_update_env (void) { @@ -125,7 +128,7 @@ static void netboot_update_env (void) ip_to_string (NetOurDNSIP, tmp); setenv ("dnsip", tmp); } -#if defined(CONFIG_BOOTP_DNS2) +#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) if (NetOurDNS2IP) { ip_to_string (NetOurDNS2IP, tmp); setenv ("dnsip2", tmp); @@ -134,15 +137,13 @@ static void netboot_update_env (void) if (NetOurNISDomain[0]) setenv ("domain", NetOurNISDomain); -#if defined(CONFIG_CMD_SNTP) \ - && defined(CONFIG_BOOTP_TIMEOFFSET) +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_TIMEOFFSET) if (NetTimeOffset) { sprintf (tmp, "%d", NetTimeOffset); setenv ("timeoffset", tmp); } #endif -#if defined(CONFIG_CMD_SNTP) \ - && defined(CONFIG_BOOTP_NTPSERVER) +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NTPSERVER) if (NetNtpServerIP) { ip_to_string (NetNtpServerIP, tmp); setenv ("ntpserverip", tmp); @@ -183,25 +184,18 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - show_boot_progress (-80); return 1; } - show_boot_progress (80); - if ((size = NetLoop(proto)) < 0) { - show_boot_progress (-81); + if ((size = NetLoop(proto)) < 0) return 1; - } - show_boot_progress (81); /* NetLoop ok, update environment */ netboot_update_env(); /* done if no file was loaded (no errors though) */ - if (size == 0) { - show_boot_progress (-82); + if (size == 0) return 0; - } /* flush cache */ flush_cache(load_addr, size); @@ -214,32 +208,19 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) printf ("Automatic boot of image at addr 0x%08lX ...\n", load_addr); - show_boot_progress (82); rcode = do_bootm (cmdtp, 0, 1, local_args); } #ifdef CONFIG_AUTOSCRIPT if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { - printf ("Running autoscript at addr 0x%08lX", load_addr); - - s = getenv ("autoscript_uname"); - if (s) - printf (":%s ...\n", s); - else - puts (" ...\n"); - - show_boot_progress (83); - rcode = autoscript (load_addr, s); + printf("Running autoscript at addr 0x%08lX ...\n", load_addr); + rcode = autoscript (load_addr); } #endif - if (rcode < 0) - show_boot_progress (-83); - else - show_boot_progress (84); return rcode; } -#if defined(CONFIG_CMD_PING) +#if (CONFIG_COMMANDS & CFG_CMD_PING) int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) @@ -266,9 +247,9 @@ U_BOOT_CMD( "ping\t- send ICMP ECHO_REQUEST to network host\n", "pingAddress\n" ); -#endif +#endif /* CFG_CMD_PING */ -#if defined(CONFIG_CMD_CDP) +#if (CONFIG_COMMANDS & CFG_CMD_CDP) static void cdp_update_env(void) { @@ -309,9 +290,9 @@ U_BOOT_CMD( cdp, 1, 1, do_cdp, "cdp\t- Perform CDP network configuration\n", ); -#endif +#endif /* CFG_CMD_CDP */ -#if defined(CONFIG_CMD_SNTP) +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) int do_sntp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { char *toff; @@ -347,4 +328,6 @@ U_BOOT_CMD( "sntp\t- synchronize RTC via network\n", "[NTP server IP]\n" ); -#endif +#endif /* CFG_CMD_SNTP */ + +#endif /* CFG_CMD_NET */ diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 70897062a..5616c4232 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -46,7 +46,7 @@ #include #include #include -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) #include #endif @@ -57,10 +57,10 @@ DECLARE_GLOBAL_DATA_PTR; !defined(CFG_ENV_IS_IN_FLASH) && \ !defined(CFG_ENV_IS_IN_DATAFLASH) && \ !defined(CFG_ENV_IS_IN_NAND) && \ - !defined(CFG_ENV_IS_IN_ONENAND) && \ - !defined(CFG_ENV_IS_IN_SPI_FLASH) && \ + !defined(CFG_ENV_IS_IN_EMMC) && \ !defined(CFG_ENV_IS_NOWHERE) -# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH|ONENAND|SPI_FLASH|NOWHERE} +# error Define one of CFG_ENV_IS_IN_{NVRAM|EEPROM|FLASH|DATAFLASH \ + |NAND|EMMC|NOWHERE} #endif #define XMK_STR(x) #x @@ -69,6 +69,21 @@ DECLARE_GLOBAL_DATA_PTR; /************************************************************************ ************************************************************************/ +/* Function that returns a character from the environment */ +extern uchar (*env_get_char)(int); + +/* Function that returns a pointer to a value from the environment */ +/* (Only memory version supported / needed). */ +extern uchar *env_get_addr(int); + +/* Function that updates CRC of the enironment */ +extern void env_crc_update (void); + +/************************************************************************ +************************************************************************/ + +static int envmatch (uchar *, int); + /* * Table with supported baudrates (defined in config_xyz.h) */ @@ -99,8 +114,7 @@ int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } - printf("\nEnvironment size: %d/%ld bytes\n", - i, (ulong)ENV_SIZE); + printf("\nEnvironment size: %d/%d bytes\n", i, ENV_SIZE); return 0; } @@ -155,11 +169,6 @@ int _do_setenv (int flag, int argc, char *argv[]) name = argv[1]; - if (strchr(name, '=')) { - printf ("## Error: illegal character '=' in variable name \"%s\"\n", name); - return 1; - } - /* * search if variable with this name already exists */ @@ -181,13 +190,7 @@ int _do_setenv (int flag, int argc, char *argv[]) * Ethernet Address and serial# can be set only once, * ver is readonly. */ - if ( -#ifdef CONFIG_HAS_UID - /* Allow serial# forced overwrite with 0xdeaf4add flag */ - ((strcmp (name, "serial#") == 0) && (flag != 0xdeaf4add)) || -#else - (strcmp (name, "serial#") == 0) || -#endif + if ( (strcmp (name, "serial#") == 0) || ((strcmp (name, "ethaddr") == 0) #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0) @@ -242,7 +245,7 @@ int _do_setenv (int flag, int argc, char *argv[]) baudrate); udelay(50000); gd->baudrate = baudrate; -#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2) +#ifdef CONFIG_PPC gd->bd->bi_baudrate = baudrate; #endif @@ -361,12 +364,12 @@ int _do_setenv (int flag, int argc, char *argv[]) load_addr = simple_strtoul(argv[2], NULL, 16); return 0; } -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) if (strcmp(argv[1],"bootfile") == 0) { copy_filename (BootFile, argv[2], sizeof(BootFile)); return 0; } -#endif +#endif /* CFG_CMD_NET */ #ifdef CONFIG_AMIGAONEG3SE if (strcmp(argv[1], "vga_fg_color") == 0 || @@ -382,24 +385,13 @@ int _do_setenv (int flag, int argc, char *argv[]) return 0; } -int setenv (char *varname, char *varvalue) +void setenv (char *varname, char *varvalue) { char *argv[4] = { "setenv", varname, varvalue, NULL }; - if (varvalue == NULL) - return _do_setenv (0, 2, argv); - else - return _do_setenv (0, 3, argv); + _do_setenv (0, 3, argv); } -#ifdef CONFIG_HAS_UID -void forceenv (char *varname, char *varvalue) -{ - char *argv[4] = { "forceenv", varname, varvalue, NULL }; - _do_setenv (0xdeaf4add, 3, argv); -} -#endif - -int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_setenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { printf ("Usage:\n%s\n", cmdtp->usage); @@ -413,7 +405,7 @@ int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Prompt for environment variable */ -#if defined(CONFIG_CMD_ASKENV) +#if (CONFIG_COMMANDS & CFG_CMD_ASKENV) int do_askenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { extern char console_buffer[CFG_CBSIZE]; @@ -485,7 +477,7 @@ int do_askenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* Continue calling setenv code */ return _do_setenv (flag, len, local_args); } -#endif +#endif /* CFG_CMD_ASKENV */ /************************************************************************ * Look up variable from environment, @@ -540,11 +532,13 @@ int getenv_r (char *name, char *buf, unsigned len) return (-1); } -#if ((defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))) \ - && !defined(CFG_ENV_IS_NOWHERE)) +#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ + (CFG_CMD_ENV|CFG_CMD_FLASH)) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_NAND)) == \ + (CFG_CMD_ENV|CFG_CMD_NAND)) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_MMC)) == \ + (CFG_CMD_ENV|CFG_CMD_MMC)) int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { extern char * env_name_spec; @@ -554,6 +548,7 @@ int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (saveenv() ? 1 : 0); } + #endif @@ -565,7 +560,8 @@ int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * If the names match, return the index for the value2, else NULL. */ -int envmatch (uchar *s1, int i2) +static int +envmatch (uchar *s1, int i2) { while (*s1 == env_get_char(i2++)) @@ -596,20 +592,22 @@ U_BOOT_CMD( " - delete environment variable 'name'\n" ); -#if ((defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))) \ - && !defined(CFG_ENV_IS_NOWHERE)) +#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \ + (CFG_CMD_ENV|CFG_CMD_FLASH)) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_NAND)) == \ + (CFG_CMD_ENV|CFG_CMD_NAND)) || \ + ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_MMC)) == \ + (CFG_CMD_ENV|CFG_CMD_MMC)) U_BOOT_CMD( saveenv, 1, 0, do_saveenv, "saveenv - save environment variables to persistent storage\n", NULL ); -#endif +#endif /* CFG_CMD_ENV */ -#if defined(CONFIG_CMD_ASKENV) +#if (CONFIG_COMMANDS & CFG_CMD_ASKENV) U_BOOT_CMD( askenv, CFG_MAXARGS, 1, do_askenv, @@ -624,9 +622,9 @@ U_BOOT_CMD( " - display 'message' string and get environment variable 'name'" "from stdin (max 'size' chars)\n" ); -#endif +#endif /* CFG_CMD_ASKENV */ -#if defined(CONFIG_CMD_RUN) +#if (CONFIG_COMMANDS & CFG_CMD_RUN) int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); U_BOOT_CMD( run, CFG_MAXARGS, 1, do_run, @@ -634,4 +632,4 @@ U_BOOT_CMD( "var [...]\n" " - run the commands in the environment variable(s) 'var'\n" ); -#endif +#endif /* CFG_CMD_RUN */ diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index d6d337628..08cb05443 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -1,7 +1,7 @@ /* * U-Boot command for OneNAND support * - * Copyright (C) 2005-2007 Samsung Electronics + * Copyright (C) 2005 Samsung Electronics * Kyungmin Park * * This program is free software; you can redistribute it and/or modify @@ -12,18 +12,14 @@ #include #include -#ifdef CONFIG_CMD_ONENAND +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) -#include -#include #include -#include - extern struct mtd_info onenand_mtd; extern struct onenand_chip onenand_chip; -int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +int do_onenand(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int ret = 0; @@ -34,48 +30,39 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; case 2: - if (strncmp(argv[1], "open", 4) == 0) { - onenand_init(); - return 0; - } onenand_print_device_info(onenand_chip.device_id, 1); return 0; default: /* At least 4 args */ if (strncmp(argv[1], "erase", 5) == 0) { - struct erase_info instr = { - .callback = NULL, - }; + struct erase_info instr; ulong start, end; - ulong block; char *endtail; + ulong block; if (strncmp(argv[2], "block", 5) == 0) { start = simple_strtoul(argv[3], NULL, 10); endtail = strchr(argv[3], '-'); - end = simple_strtoul(endtail + 1, NULL, 10); + end = simple_strtoul(endtail+1, NULL, 10); } else { start = simple_strtoul(argv[2], NULL, 10); end = simple_strtoul(argv[3], NULL, 10); - - start >>= onenand_chip.erase_shift; - end >>= onenand_chip.erase_shift; - /* Don't include the end block */ - end--; + start -= (unsigned long) onenand_chip.base; + end -= (unsigned long) onenand_chip.base; } if (!end || end < 0) end = start; - printf("Erase block from %lu to %lu\n", start, end); + printf("Erase block from %d to %d\n", start, end); for (block = start; block <= end; block++) { instr.addr = block << onenand_chip.erase_shift; instr.len = 1 << onenand_chip.erase_shift; ret = onenand_erase(&onenand_mtd, &instr); if (ret) { - printf("erase failed %lu\n", block); + printf("erase failed %d\n", block); break; } } @@ -85,31 +72,34 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (strncmp(argv[1], "read", 4) == 0) { ulong addr = simple_strtoul(argv[2], NULL, 16); - ulong ofs = simple_strtoul(argv[3], NULL, 16); + ulong ofs = simple_strtoul(argv[3], NULL, 16); size_t len = simple_strtoul(argv[4], NULL, 16); size_t retlen = 0; int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1; + if (oob) - onenand_read_oob(&onenand_mtd, ofs, len, - &retlen, (u_char *) addr); + onenand_read_oob(&onenand_mtd, ofs, len, &retlen, (u_char *) addr); else - onenand_read(&onenand_mtd, ofs, len, &retlen, - (u_char *) addr); + onenand_read(&onenand_mtd, ofs, len, &retlen, (u_char *) addr); printf("Done\n"); return 0; } if (strncmp(argv[1], "write", 5) == 0) { + int ret ; ulong addr = simple_strtoul(argv[2], NULL, 16); - ulong ofs = simple_strtoul(argv[3], NULL, 16); + ulong ofs = simple_strtoul(argv[3], NULL, 16); size_t len = simple_strtoul(argv[4], NULL, 16); size_t retlen = 0; - onenand_write(&onenand_mtd, ofs, len, &retlen, - (u_char *) addr); - printf("Done\n"); + printf("onenadwrite: addr = 0x%x, ofs = 0x%x, len = 0x%x\n", addr, ofs, len); + ret = onenand_write(&onenand_mtd, ofs, len, &retlen, (u_char *) addr); + if (ret) + printf("Error writing oneNAND: ret = %d\n", ret); + else + printf("Done. ret = %d\n", ret); return 0; } @@ -135,11 +125,48 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } if (oob) - onenand_read_oob(&onenand_mtd, ofs, len, - &retlen, (u_char *) addr); + onenand_read_oob(&onenand_mtd, ofs, len, &retlen, (u_char *) addr); else - onenand_read(&onenand_mtd, ofs, len, &retlen, - (u_char *) addr); + onenand_read(&onenand_mtd, ofs, len, &retlen, (u_char *) addr); + return 0; + } + + if (strncmp(argv[1], "unlock", 6) == 0) { + ulong start = simple_strtoul(argv[2], NULL, 10); + ulong ofs = simple_strtoul(argv[3], NULL, 10); + + if (!ofs) + ofs = (1 << onenand_chip.erase_shift); + + start = start << onenand_chip.erase_shift; + printf("start = 0x%08x, ofs = 0x%08x\n", + start, ofs); + onenand_unlock(&onenand_mtd, start, start + ofs); + + return 0; + } + + if (strncmp(argv[1], "save", 4) == 0 && + strncmp(argv[2], "bootloader", 10) == 0) { + ulong addr = simple_strtoul(argv[3], NULL, 16); + struct erase_info instr; + int ofs = 0; + int len = 0x20000; + size_t retlen; + + printf("save bootloader...\n"); + + if (!addr) + break; + + onenand_unlock(&onenand_mtd, ofs, len); + + instr.addr = 0 << onenand_chip.erase_shift; + instr.len = 1 << onenand_chip.erase_shift; + onenand_erase(&onenand_mtd, &instr); + + onenand_write(&onenand_mtd, ofs, len, &retlen, (u_char *) addr); + onenand_unlock(&onenand_mtd, CFG_ENV_ADDR, onenand_mtd.size - CFG_ENV_ADDR); return 0; } @@ -150,14 +177,18 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - onenand, 6, 1, do_onenand, + onenand, 6, 1, do_onenand, "onenand - OneNAND sub-system\n", "info - show available OneNAND devices\n" "onenand read[.oob] addr ofs len - read data at ofs with len to addr\n" "onenand write addr ofs len - write data at ofs with len from addr\n" + "onenand erase block start-end - erase block from start to end\n" "onenand erase saddr eaddr - erase block start addr to end addr\n" "onenand block[.oob] addr block [page] [len] - " - "read data with (block [, page]) to addr" + "read data with (block [, page]) to addr\n" + "onenand unlock start-end - unlock block from start to end\n" + "onenand save bootloader addr - save bootloader at addr\n" ); -#endif /* CONFIG_CMD_ONENAND */ +#endif /* (CONFIG_COMMANDS & CFG_CMD_ONENAND) */ + diff --git a/common/cmd_pci.c b/common/cmd_pci.c index 89687015b..45085462f 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -30,11 +30,16 @@ */ #include + +#ifdef CONFIG_PCI + #include #include #include #include +#if (CONFIG_COMMANDS & CFG_CMD_PCI) + extern int cmd_get_data_size(char* arg, int default_size); unsigned char ShortPCIListing = 1; @@ -173,7 +178,7 @@ static char *pci_classes_str(u8 class) * Subroutine: pci_header_show_brief * * Description: Reads and prints the header of the - * specified PCI device in short form. + * specified PCI device in short form. * * Inputs: dev Bus+Device+Function number * @@ -559,3 +564,7 @@ U_BOOT_CMD( "pci write[.b, .w, .l] b.d.f address value\n" " - write to CFG address\n" ); + +#endif /* (CONFIG_COMMANDS & CFG_CMD_PCI) */ + +#endif /* CONFIG_PCI */ diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c index dcd07c05e..2eb5b26f2 100644 --- a/common/cmd_pcmcia.c +++ b/common/cmd_pcmcia.c @@ -61,7 +61,7 @@ /* -------------------------------------------------------------------- */ -#if defined(CONFIG_CMD_PCMCIA) +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) extern int pcmcia_on (void); extern int pcmcia_off (void); @@ -87,19 +87,19 @@ int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - pinit, 2, 0, do_pinit, + pinit, 2, 1, do_pinit, "pinit - PCMCIA sub-system\n", "on - power on PCMCIA socket\n" "pinit off - power off PCMCIA socket\n" ); -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_PCMCIA */ /* -------------------------------------------------------------------- */ #undef CHECK_IDE_DEVICE -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) #define CHECK_IDE_DEVICE #endif diff --git a/common/cmd_portio.c b/common/cmd_portio.c index a06cac016..d2e4c4b50 100644 --- a/common/cmd_portio.c +++ b/common/cmd_portio.c @@ -30,6 +30,8 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_PORTIO) + extern int cmd_get_data_size (char *arg, int default_size); /* Display values from last command. @@ -163,3 +165,5 @@ U_BOOT_CMD( "[.b, .w, .l] port\n" " - read datum from IO port\n" ); + +#endif /* CFG_CMD_PORTIO */ diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 0657e4b1f..f428f7e9a 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -31,9 +31,8 @@ #include #elif defined (CONFIG_MPC5200) #include -#elif defined (CONFIG_MPC86xx) -extern void mpc86xx_reginfo(void); #endif +#if (CONFIG_COMMANDS & CFG_CMD_REGINFO) int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -109,24 +108,24 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nMemory (SDRAM) Configuration\n" "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); - mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd)); mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); puts ("\n" "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n"); - mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd)); printf ("\n\n" "DMA Channels\n" @@ -149,32 +148,32 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\n" "External Bus\n" "pbear pbesr0 pbesr1 epcr\n"); - mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n" "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n"); - mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n" "pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n"); - mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n\n"); @@ -196,12 +195,12 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nMemory (SDRAM) Configuration\n" "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n"); - mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); printf ("\n\n" "DMA Channels\n" @@ -221,31 +220,31 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\n" "External Bus\n" "pbear pbesr0 pbesr1 epcr\n"); - mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n" "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n"); - mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n" "pb4cr pb4ap\n"); - mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); + mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); puts ("\n\n"); #elif defined(CONFIG_5xx) - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile memctl5xx_t *memctl = &immap->im_memctl; volatile sysconf5xx_t *sysconf = &immap->im_siu_conf; volatile sit5xx_t *timers = &immap->im_sit; @@ -282,107 +281,70 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nMPC5200 registers\n"); printf ("MBAR=%08x\n", CFG_MBAR); puts ("Memory map registers\n"); - printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", + printf ("\tCS0: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS0_START, *(volatile ulong*)MPC5XXX_CS0_STOP, *(volatile ulong*)MPC5XXX_CS0_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0); - printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", + printf ("\tCS1: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS1_START, *(volatile ulong*)MPC5XXX_CS1_STOP, *(volatile ulong*)MPC5XXX_CS1_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0); - printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", + printf ("\tCS2: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS2_START, *(volatile ulong*)MPC5XXX_CS2_STOP, *(volatile ulong*)MPC5XXX_CS2_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0); - printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", + printf ("\tCS3: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS3_START, *(volatile ulong*)MPC5XXX_CS3_STOP, *(volatile ulong*)MPC5XXX_CS3_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0); - printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", + printf ("\tCS4: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS4_START, *(volatile ulong*)MPC5XXX_CS4_STOP, *(volatile ulong*)MPC5XXX_CS4_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0); - printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", + printf ("\tCS5: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS5_START, *(volatile ulong*)MPC5XXX_CS5_STOP, *(volatile ulong*)MPC5XXX_CS5_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0); - printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", + printf ("\tCS6: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS6_START, *(volatile ulong*)MPC5XXX_CS6_STOP, *(volatile ulong*)MPC5XXX_CS6_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0); - printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", + printf ("\tCS7: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_CS7_START, *(volatile ulong*)MPC5XXX_CS7_STOP, *(volatile ulong*)MPC5XXX_CS7_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0); - printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", + printf ("\tBOOTCS: start %08X\tstop %08X\tconfig %08X\ten %d\n", *(volatile ulong*)MPC5XXX_BOOTCS_START, *(volatile ulong*)MPC5XXX_BOOTCS_STOP, *(volatile ulong*)MPC5XXX_BOOTCS_CFG, (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0); - printf ("\tSDRAMCS0: %08lX\n", + printf ("\tSDRAMCS0: %08X\n", *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG); - printf ("\tSDRAMCS1: %08lX\n", + printf ("\tSDRAMCS1: %08X\n", *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG); -#elif defined(CONFIG_MPC86xx) - mpc86xx_reginfo(); - -#elif defined(CONFIG_BLACKFIN) - puts("\nSystem Configuration registers\n"); - - puts("\nPLL Registers\n"); - printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n", - bfin_read_PLL_DIV(), bfin_read_PLL_CTL()); - printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n", - bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT()); - printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL()); - - puts("\nEBIU AMC Registers\n"); - printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL()); - printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n", - bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1()); -# ifdef EBIU_MODE - printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n", - bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT()); - printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n", - bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL()); -# endif - -# ifdef EBIU_RSTCTL - puts("\nEBIU DDR Registers\n"); - printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n", - bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1()); - printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n", - bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3()); - printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n", - bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL()); - printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n", - bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST()); -# else - puts("\nEBIU SDC Registers\n"); - printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n", - bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL()); - printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n", - bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL()); -# endif - -#endif /* CONFIG_BLACKFIN */ - +#endif /* CONFIG_MPC5200 */ return 0; } +#endif /* CONFIG_COMMANDS & CFG_CMD_REGINFO */ + + /**************************************************/ -#if defined(CONFIG_CMD_REGINFO) +#if ( defined(CONFIG_8xx) || defined(CONFIG_405GP) || \ + defined(CONFIG_405EP) || defined(CONFIG_MPC5200) ) && \ + (CONFIG_COMMANDS & CFG_CMD_REGINFO) + U_BOOT_CMD( - reginfo, 2, 1, do_reginfo, + reginfo, 2, 1, do_reginfo, "reginfo - print register information\n", ); #endif diff --git a/common/cmd_reiser.c b/common/cmd_reiser.c index b7395d795..508ffcbda 100644 --- a/common/cmd_reiser.c +++ b/common/cmd_reiser.c @@ -27,13 +27,14 @@ * Reiserfs support */ #include + +#if (CONFIG_COMMANDS & CFG_CMD_REISER) #include #include #include #include #include #include -#include #ifndef CONFIG_DOS_PARTITION #error DOS partition support must be selected @@ -47,6 +48,41 @@ #define PRINTF(fmt,args...) #endif +static block_dev_desc_t *get_dev (char* ifname, int dev) +{ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) + if (strncmp(ifname,"ide",3)==0) { + extern block_dev_desc_t * ide_get_dev(int dev); + return((dev >= CFG_IDE_MAXDEVICE) ? NULL : ide_get_dev(dev)); + } +#endif +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + if (strncmp(ifname,"scsi",4)==0) { + extern block_dev_desc_t * scsi_get_dev(int dev); + return((dev >= CFG_SCSI_MAXDEVICE) ? NULL : scsi_get_dev(dev)); + } +#endif +#if ((CONFIG_COMMANDS & CFG_CMD_USB) && defined(CONFIG_USB_STORAGE)) + if (strncmp(ifname,"usb",3)==0) { + extern block_dev_desc_t * usb_stor_get_dev(int dev); + return((dev >= USB_MAX_STOR_DEV) ? NULL : usb_stor_get_dev(dev)); + } +#endif +#if defined(CONFIG_MMC) + if (strncmp(ifname,"mmc",3)==0) { + extern block_dev_desc_t * mmc_get_dev(int dev); + return((dev >= 1) ? NULL : mmc_get_dev(dev)); + } +#endif +#if defined(CONFIG_SYSTEMACE) + if (strcmp(ifname,"ace")==0) { + extern block_dev_desc_t * systemace_get_dev(int dev); + return((dev >= 1) ? NULL : systemace_get_dev(dev)); + } +#endif + return NULL; +} + int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { char *filename = "/"; @@ -61,7 +97,7 @@ int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } dev = (int)simple_strtoul (argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); + dev_desc=get_dev(argv[1],dev); if (dev_desc == NULL) { printf ("\n** Block device %s %d not supported\n", argv[1], dev); @@ -88,7 +124,7 @@ int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } if (!reiserfs_mount(part_length)) { - printf ("** Bad Reiserfs partition or disk - %s %d:%d **\n", argv[1], dev, part); + printf ("** Bad Reisefs partition or disk - %s %d:%d **\n", argv[1], dev, part); return 1; } @@ -160,7 +196,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } dev = (int)simple_strtoul (argv[2], &ep, 16); - dev_desc = get_dev(argv[1],dev); + dev_desc=get_dev(argv[1],dev); if (dev_desc==NULL) { printf ("\n** Block device %s %d not supported\n", argv[1], dev); return 1; @@ -181,7 +217,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) { + if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) { printf ("\n** Invalid partition type \"%.32s\"" " (expect \"" BOOT_PART_TYPE "\")\n", info.type); @@ -202,7 +238,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } if (!reiserfs_mount(part_length)) { - printf ("** Bad Reiserfs partition or disk - %s %d:%d **\n", argv[1], dev, part); + printf ("** Bad Reisefs partition or disk - %s %d:%d **\n", argv[1], dev, part); return 1; } @@ -237,3 +273,5 @@ U_BOOT_CMD( " - load binary file 'filename' from 'dev' on 'interface'\n" " to address 'addr' from dos filesystem\n" ); + +#endif /* CONFIG_COMMANDS & CFG_CMD_REISER */ diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index f3574650c..e8048611f 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -34,6 +34,8 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) + #ifdef CONFIG_SCSI_SYM53C8XX #define SCSI_VEND_ID 0x1000 #ifndef CONFIG_SCSI_DEV_ID @@ -41,13 +43,8 @@ #else #define SCSI_DEV_ID CONFIG_SCSI_DEV_ID #endif -#elif defined CONFIG_SATA_ULI5288 - -#define SCSI_VEND_ID 0x10b9 -#define SCSI_DEV_ID 0x5288 - #else -#error no scsi device defined +#error CONFIG_SCSI_SYM53C8XX must be defined #endif @@ -72,7 +69,7 @@ void scsi_setup_inquiry(ccb * pccb); void scsi_ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); -ulong scsi_read(int device, ulong blknr, ulong blkcnt, void *buffer); +ulong scsi_read(int device, ulong blknr, ulong blkcnt, ulong *buffer); /********************************************************************************* @@ -127,12 +124,9 @@ void scsi_scan(int mode) if((modi&0x80)==0x80) /* drive is removable */ scsi_dev_desc[scsi_max_devs].removable=TRUE; /* get info for this device */ - scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0], - &tempbuff[8], 8); - scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].product[0], - &tempbuff[16], 16); - scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].revision[0], - &tempbuff[32], 4); + scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].vendor[0],&tempbuff[8],8); + scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].product[0],&tempbuff[16],16); + scsi_ident_cpy(&scsi_dev_desc[scsi_max_devs].revision[0],&tempbuff[32],4); scsi_dev_desc[scsi_max_devs].target=pccb->target; scsi_dev_desc[scsi_max_devs].lun=pccb->lun; @@ -171,7 +165,7 @@ removable: if(scsi_max_devs>0) scsi_curr_dev=0; else - scsi_curr_dev = -1; + scsi_curr_dev=-1; } @@ -195,7 +189,7 @@ void scsi_init(void) block_dev_desc_t * scsi_get_dev(int dev) { - return (dev < CFG_SCSI_MAX_DEVICE) ? &scsi_dev_desc[dev] : NULL; + return((block_dev_desc_t *)&scsi_dev_desc[dev]); } @@ -207,13 +201,10 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *boot_device = NULL; char *ep; int dev, part = 0; - ulong addr, cnt; + ulong addr, cnt, checksum; disk_partition_t info; image_header_t *hdr; int rcode = 0; -#if defined(CONFIG_FIT) - const void *fit_hdr = NULL; -#endif switch (argc) { case 1: @@ -252,7 +243,7 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } part = simple_strtoul(++ep, NULL, 16); } - if (get_partition_info (&scsi_dev_desc[dev], part, &info)) { + if (get_partition_info (scsi_dev_desc, part, &info)) { printf("error reading partinfo\n"); return 1; } @@ -276,31 +267,24 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - switch (genimg_get_format ((void *)addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *)addr; + hdr = (image_header_t *)addr; - if (!image_check_hcrc (hdr)) { - puts ("\n** Bad Header Checksum **\n"); - return 1; - } - - image_print_contents (hdr); - cnt = image_get_image_size (hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (const void *)addr; - puts ("Fit image detected...\n"); - - cnt = fit_get_size (fit_hdr); - break; -#endif - default: - puts ("** Unknown image type\n"); + if (ntohl(hdr->ih_magic) == IH_MAGIC) { + printf("\n** Bad Magic Number **\n"); return 1; } + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) { + puts ("\n** Bad Header Checksum **\n"); + return 1; + } + hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */ + + print_image_hdr (hdr); + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); cnt += info.blksz - 1; cnt /= info.blksz; cnt -= 1; @@ -310,18 +294,6 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("** Read error on %d:%d\n", dev, part); return 1; } - -#if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { - if (!fit_check_format (fit_hdr)) { - puts ("** Bad FIT image format\n"); - return 1; - } - fit_print_contents (fit_hdr); - } -#endif - /* Loading ok, update default load address */ load_addr = addr; @@ -394,7 +366,7 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } printf ("Usage:\n%s\n", cmdtp->usage); return 1; - case 3: + case 3: if (strncmp(argv[1],"dev",3) == 0) { int dev = (int)simple_strtoul(argv[2], NULL, 10); printf ("\nSCSI device %d: ", dev); @@ -447,7 +419,7 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #define SCSI_MAX_READ_BLK 0xFFFF /* almost the maximum amount of the scsi_ext command.. */ -ulong scsi_read(int device, ulong blknr, ulong blkcnt, void *buffer) +ulong scsi_read(int device, ulong blknr, ulong blkcnt, ulong *buffer) { ulong start,blks, buf_addr; unsigned short smallblks; @@ -631,3 +603,5 @@ U_BOOT_CMD( "scsiboot- boot from SCSI device\n", "loadAddr dev:part\n" ); + +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_SCSI) */ diff --git a/common/cmd_spi.c b/common/cmd_spi.c index 40ee7e7dd..a6fdf7fdd 100644 --- a/common/cmd_spi.c +++ b/common/cmd_spi.c @@ -29,6 +29,8 @@ #include #include +#if (CONFIG_COMMANDS & CFG_CMD_SPI) + /*----------------------------------------------------------------------- * Definitions */ @@ -37,20 +39,20 @@ # define MAX_SPI_BYTES 32 /* Maximum number of bytes we can handle */ #endif -#ifndef CONFIG_DEFAULT_SPI_BUS -# define CONFIG_DEFAULT_SPI_BUS 0 -#endif -#ifndef CONFIG_DEFAULT_SPI_MODE -# define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 -#endif +/* + * External table of chip select functions (see the appropriate board + * support for the actual definition of the table). + */ +extern spi_chipsel_type spi_chipsel[]; +extern int spi_chipsel_cnt; /* * Values from last command. */ -static unsigned int device; -static int bitlen; -static uchar dout[MAX_SPI_BYTES]; -static uchar din[MAX_SPI_BYTES]; +static int device; +static int bitlen; +static uchar dout[MAX_SPI_BYTES]; +static uchar din[MAX_SPI_BYTES]; /* * SPI read/write @@ -65,7 +67,6 @@ static uchar din[MAX_SPI_BYTES]; int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - struct spi_slave *slave; char *cp = 0; uchar tmp; int j; @@ -102,24 +103,19 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } + if ((device < 0) || (device >= spi_chipsel_cnt)) { + printf("Invalid device %d, giving up.\n", device); + return 1; + } if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) { printf("Invalid bitlen %d, giving up.\n", bitlen); return 1; } - /* FIXME: Make these parameters run-time configurable */ - slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, device, 1000000, - CONFIG_DEFAULT_SPI_MODE); - if (!slave) { - printf("Invalid device %d, giving up.\n", device); - return 1; - } + debug ("spi_chipsel[%d] = %08X\n", + device, (uint)spi_chipsel[device]); - debug ("spi chipsel = %08X\n", device); - - spi_claim_bus(slave); - if(spi_xfer(slave, bitlen, dout, din, - SPI_XFER_BEGIN | SPI_XFER_END) != 0) { + if(spi_xfer(spi_chipsel[device], bitlen, dout, din) != 0) { printf("Error with the SPI transaction.\n"); rcode = 1; } else { @@ -129,8 +125,6 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } printf("\n"); } - spi_release_bus(slave); - spi_free_slave(slave); return rcode; } @@ -145,3 +139,5 @@ U_BOOT_CMD( " - Number of bits to send (base 10)\n" " - Hexadecimal string that gets sent\n" ); + +#endif /* CFG_CMD_SPI */ diff --git a/common/cmd_universe.c b/common/cmd_universe.c index ea977828a..8d7b6fee1 100644 --- a/common/cmd_universe.c +++ b/common/cmd_universe.c @@ -28,6 +28,8 @@ #include +#if (CONFIG_COMMANDS & CFG_CMD_UNIVERSE) + #define PCI_VENDOR PCI_VENDOR_ID_TUNDRA #define PCI_DEVICE PCI_DEVICE_ID_TUNDRA_CA91C042 @@ -384,3 +386,5 @@ U_BOOT_CMD( " 02 -> D16 Data Width\n" " 03 -> D32 Data Width\n" ); + +#endif /* (CONFIG_COMMANDS & CFG_CMD_UNIVERSE) */ diff --git a/common/cmd_usb.c b/common/cmd_usb.c index c62ca9769..28c05aa20 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -28,11 +28,13 @@ #include #include #include -#include + +#if (CONFIG_COMMANDS & CFG_CMD_USB) + #include #ifdef CONFIG_USB_STORAGE -static int usb_stor_curr_dev = -1; /* current device */ +static int usb_stor_curr_dev=-1; /* current device */ #endif /* some display routines (info command) */ @@ -311,13 +313,11 @@ int do_usbboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *boot_device = NULL; char *ep; int dev, part=1, rcode; - ulong addr, cnt; + ulong addr, cnt, checksum; disk_partition_t info; image_header_t *hdr; block_dev_desc_t *stor_dev; -#if defined(CONFIG_FIT) - const void *fit_hdr = NULL; -#endif + switch (argc) { case 1: @@ -388,32 +388,25 @@ int do_usbboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - switch (genimg_get_format ((void *)addr)) { - case IMAGE_FORMAT_LEGACY: - hdr = (image_header_t *)addr; + hdr = (image_header_t *)addr; - if (!image_check_hcrc (hdr)) { - puts ("\n** Bad Header Checksum **\n"); - return 1; - } - - image_print_contents (hdr); - - cnt = image_get_image_size (hdr); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - fit_hdr = (const void *)addr; - puts ("Fit image detected...\n"); - - cnt = fit_get_size (fit_hdr); - break; -#endif - default: - puts ("** Unknown image type\n"); + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + printf("\n** Bad Magic Number **\n"); return 1; } + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = 0; + + if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) { + puts ("\n** Bad Header Checksum **\n"); + return 1; + } + hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */ + + print_image_hdr (hdr); + + cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t)); cnt += info.blksz - 1; cnt /= info.blksz; cnt -= 1; @@ -423,18 +416,6 @@ int do_usbboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("\n** Read error on %d:%d\n", dev, part); return 1; } - -#if defined(CONFIG_FIT) - /* This cannot be done earlier, we need complete FIT image in RAM first */ - if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) { - if (!fit_check_format (fit_hdr)) { - puts ("** Bad FIT image format\n"); - return 1; - } - fit_print_contents (fit_hdr); - } -#endif - /* Loading ok, update default load address */ load_addr = addr; @@ -476,7 +457,7 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #ifdef CONFIG_USB_STORAGE /* try to recognize storage devices immediately */ if (i >= 0) - usb_stor_curr_dev = usb_stor_scan(1); + usb_stor_curr_dev = usb_stor_scan(1); #endif return 0; } @@ -550,28 +531,18 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } if (strncmp(argv[1], "stor", 4) == 0) { - return usb_stor_info(); + usb_stor_info(); + return 0; } if (strncmp(argv[1],"part",4) == 0) { - int devno, ok = 0; - if (argc==2) { - for (devno=0; devnotype!=DEV_TYPE_UNKNOWN) { - ok++; - if (devno) - printf("\n"); - printf("print_part of %x\n",devno); - print_part(stor_dev); - } - } - } - else { - devno=simple_strtoul(argv[2], NULL, 16); + int devno, ok; + for (ok=0, devno=0; devnotype!=DEV_TYPE_UNKNOWN) { ok++; + if (devno) + printf("\n"); printf("print_part of %x\n",devno); print_part(stor_dev); } @@ -636,6 +607,12 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } + +#endif /* (CONFIG_COMMANDS & CFG_CMD_USB) */ + + +#if (CONFIG_COMMANDS & CFG_CMD_USB) + #ifdef CONFIG_USB_STORAGE U_BOOT_CMD( usb, 5, 1, do_usb, @@ -667,3 +644,4 @@ U_BOOT_CMD( "usb info [dev] - show available USB devices\n" ); #endif +#endif diff --git a/common/cmd_vfd.c b/common/cmd_vfd.c index 104c31056..5e623a270 100644 --- a/common/cmd_vfd.c +++ b/common/cmd_vfd.c @@ -35,7 +35,7 @@ #include #include -#if defined(CONFIG_CMD_VFD) +#if (CONFIG_COMMANDS & CFG_CMD_VFD) #include #define VFD_TEST_LOGO_BMPNR 0 @@ -66,14 +66,14 @@ int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( - vfd, 2, 0, do_vfd, - "vfd - load a bitmap to the VFDs on TRAB\n", - "/N\n" - " - load bitmap N to the VFDs (N is _decimal_ !!!)\n" + vfd, 2, 0, do_vfd, + "vfd - load a bitmap to the VFDs on TRAB\n", + "/N\n" + " - load bitmap N to the VFDs (N is _decimal_ !!!)\n" "vfd ADDR\n" " - load bitmap at address ADDR\n" ); -#endif +#endif /* CFG_CMD_VFD */ #ifdef CONFIG_VFD int trab_vfd (ulong bitmap) diff --git a/common/cmd_voltage.c b/common/cmd_voltage.c new file mode 100644 index 000000000..53a0c7d82 --- /dev/null +++ b/common/cmd_voltage.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include + +#if defined(CONFIG_CMD_VOLTAGE) + +/* To use, the board should define its own voltag_info function */ +void inline __voltage_info (void) {} +void voltage_info (void) __attribute__((weak, alias("__voltage_info"))); + +int do_voltage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int ret = 1; + + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + } else { + if (0 == strncmp(argv[1], "info", 4)) { + voltage_info(); + } else { + printf("Unsupported option:\n%s\n", argv[1]); + printf("Usage:\n%s\n", cmdtp->usage); + } + } + + return ret; +} + +U_BOOT_CMD( + voltage, 2, 1, do_voltage, + "voltage - Manage system voltages\n", + " options : \n" + " info - display voltage information\n" +); + + + +#endif /* CONFIG_CMD_VOLTAGE */ diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c index 2753389ea..8359153b2 100644 --- a/common/cmd_ximg.c +++ b/common/cmd_ximg.c @@ -24,6 +24,7 @@ * MA 02111-1307 USA */ +#if (CONFIG_COMMANDS & CFG_CMD_XIMG) /* * Multi Image extract @@ -36,137 +37,93 @@ int do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - ulong addr = load_addr; - ulong dest = 0; - ulong data, len, count; - int verify; - int part = 0; - char pbuf[10]; - image_header_t *hdr; -#if defined(CONFIG_FIT) - const char *uname = NULL; - const void* fit_hdr; - int noffset; - const void *fit_data; - size_t fit_len; -#endif + ulong addr = load_addr, dest = 0; + ulong data, len, checksum; + ulong *len_ptr; + int i, verify, part = 0; + char pbuf[10], *s; + image_header_t header; - verify = getenv_yesno ("verify"); + s = getenv("verify"); + verify = (s && (*s == 'n')) ? 0 : 1; if (argc > 1) { addr = simple_strtoul(argv[1], NULL, 16); } if (argc > 2) { part = simple_strtoul(argv[2], NULL, 16); -#if defined(CONFIG_FIT) - uname = argv[2]; -#endif } if (argc > 3) { dest = simple_strtoul(argv[3], NULL, 16); } - switch (genimg_get_format ((void *)addr)) { - case IMAGE_FORMAT_LEGACY: + printf("## Copying from image at %08lx ...\n", addr); - printf("## Copying part %d from legacy image " - "at %08lx ...\n", part, addr); + /* Copy header so we can blank CRC field for re-calculation */ + memmove(&header, (char *) addr, sizeof (image_header_t)); - hdr = (image_header_t *)addr; - if (!image_check_magic (hdr)) { - printf("Bad Magic Number\n"); - return 1; - } - - if (!image_check_hcrc (hdr)) { - printf("Bad Header Checksum\n"); - return 1; - } -#ifdef DEBUG - image_print_contents (hdr); -#endif - - if (!image_check_type (hdr, IH_TYPE_MULTI)) { - printf("Wrong Image Type for %s command\n", - cmdtp->name); - return 1; - } - - if (image_get_comp (hdr) != IH_COMP_NONE) { - printf("Wrong Compression Type for %s command\n", - cmdtp->name); - return 1; - } - - if (verify) { - printf(" Verifying Checksum ... "); - if (!image_check_dcrc (hdr)) { - printf("Bad Data CRC\n"); - return 1; - } - printf("OK\n"); - } - - count = image_multi_count (hdr); - if (part >= count) { - printf("Bad Image Part\n"); - return 1; - } - - image_multi_getimg (hdr, part, &data, &len); - break; -#if defined(CONFIG_FIT) - case IMAGE_FORMAT_FIT: - if (uname == NULL) { - puts ("No FIT subimage unit name\n"); - return 1; - } - - printf("## Copying '%s' subimage from FIT image " - "at %08lx ...\n", uname, addr); - - fit_hdr = (const void *)addr; - if (!fit_check_format (fit_hdr)) { - puts ("Bad FIT image format\n"); - return 1; - } - - /* get subimage node offset */ - noffset = fit_image_get_node (fit_hdr, uname); - if (noffset < 0) { - printf ("Can't find '%s' FIT subimage\n", uname); - return 1; - } - - if (fit_image_check_comp (fit_hdr, noffset, IH_COMP_NONE)) { - printf("Wrong Compression Type for %s command\n", - cmdtp->name); - return 1; - } - - /* verify integrity */ - if (verify) { - if (!fit_image_check_hashes (fit_hdr, noffset)) { - puts ("Bad Data Hash\n"); - return 1; - } - } - - /* get subimage data address and length */ - if (fit_image_get_data (fit_hdr, noffset, &fit_data, &fit_len)) { - puts ("Could not find script subimage data\n"); - return 1; - } - - data = (ulong)fit_data; - len = (ulong)fit_len; - break; -#endif - default: - puts ("Invalid image type for imxtract\n"); + if (ntohl(header.ih_magic) != IH_MAGIC) { + printf("Bad Magic Number\n"); return 1; } + data = (ulong) & header; + len = sizeof (image_header_t); + + checksum = ntohl(header.ih_hcrc); + header.ih_hcrc = 0; + + if (crc32(0, (char *) data, len) != checksum) { + printf("Bad Header Checksum\n"); + return 1; + } +#ifdef DEBUG + print_image_hdr((image_header_t *) addr); +#endif + + data = addr + sizeof (image_header_t); + len = ntohl(header.ih_size); + + if (header.ih_type != IH_TYPE_MULTI) { + printf("Wrong Image Type for %s command\n", cmdtp->name); + return 1; + } + + if (header.ih_comp != IH_COMP_NONE) { + printf("Wrong Compression Type for %s command\n", cmdtp->name); + return 1; + } + + if (verify) { + printf(" Verifying Checksum ... "); + if (crc32(0, (char *) data, len) != ntohl(header.ih_dcrc)) { + printf("Bad Data CRC\n"); + return 1; + } + printf("OK\n"); + } + + len_ptr = (ulong *) data; + + data += 4; /* terminator */ + for (i = 0; len_ptr[i]; ++i) { + data += 4; + if (argc > 2 && part > i) { + u_long tail; + len = ntohl(len_ptr[i]); + tail = len % 4; + data += len; + if (tail) { + data += 4 - tail; + } + } + } + if (argc > 2 && part >= i) { + printf("Bad Image Part\n"); + return 1; + } + len = ntohl(len_ptr[part]); + if (argc > 3) { memcpy((char *) dest, (char *) data, len); } @@ -182,9 +139,6 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(imxtract, 4, 1, do_imgextract, "imxtract- extract a part of a multi-image\n", "addr part [dest]\n" - " - extract from legacy image at and copy to \n" -#if defined(CONFIG_FIT) - "addr uname [dest]\n" - " - extract subimage from FIT image at and copy to \n" -#endif -); + " - extract from image at and copy to \n"); + +#endif /* CONFIG_COMMANDS & CFG_CMD_XIMG */ diff --git a/common/command.c b/common/command.c index 861796d9a..e917975a7 100644 --- a/common/command.c +++ b/common/command.c @@ -38,11 +38,11 @@ do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( version, 1, 1, do_version, - "version - print monitor version\n", + "version - print monitor version\n", NULL ); -#if defined(CONFIG_CMD_ECHO) +#if (CONFIG_COMMANDS & CFG_CMD_ECHO) int do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -71,12 +71,12 @@ do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( echo, CFG_MAXARGS, 1, do_echo, - "echo - echo args to console\n", - "[args..]\n" + "echo - echo args to console\n", + "[args..]\n" " - echo args to console; \\c suppresses newline\n" ); -#endif +#endif /* CFG_CMD_ECHO */ #ifdef CFG_HUSH_PARSER @@ -196,15 +196,17 @@ do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) expr = !expr; - debug (": returns %d\n", expr); +#if 0 + printf(": returns %d\n", expr); +#endif return expr; } U_BOOT_CMD( test, CFG_MAXARGS, 1, do_test, - "test - minimal test like /bin/sh\n", - "[args..]\n" + "test - minimal test like /bin/sh\n", + "[args..]\n" " - test functionality\n" ); @@ -222,7 +224,7 @@ do_exit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( exit, 2, 1, do_exit, - "exit - exit script\n", + "exit - exit script\n", " - exit functionality\n" ); @@ -315,12 +317,12 @@ int do_help (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( help, CFG_MAXARGS, 1, do_help, - "help - print online help\n", - "[command ...]\n" - " - show help information (for 'command')\n" - "'help' prints online help for the monitor commands.\n\n" - "Without arguments, it prints a short usage message for all commands.\n\n" - "To get detailed help information for specific commands you can type\n" + "help - print online help\n", + "[command ...]\n" + " - show help information (for 'command')\n" + "'help' prints online help for the monitor commands.\n\n" + "Without arguments, it prints a short usage message for all commands.\n\n" + "To get detailed help information for specific commands you can type\n" "'help' with one or more command names as arguments.\n" ); @@ -328,13 +330,13 @@ U_BOOT_CMD( #ifdef CFG_LONGHELP cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = { "?", CFG_MAXARGS, 1, do_help, - "? - alias for 'help'\n", + "? - alias for 'help'\n", NULL }; #else cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = { "?", CFG_MAXARGS, 1, do_help, - "? - alias for 'help'\n" + "? - alias for 'help'\n" }; #endif /* CFG_LONGHELP */ @@ -407,7 +409,7 @@ void install_auto_complete(void) { install_auto_complete_handler("printenv", var_complete); install_auto_complete_handler("setenv", var_complete); -#if defined(CONFIG_CMD_RUN) +#if (CONFIG_COMMANDS & CFG_CMD_RUN) install_auto_complete_handler("run", var_complete); #endif } @@ -496,7 +498,7 @@ static int make_argv(char *s, int argvsz, char *argv[]) while ((*s == ' ') || (*s == '\t')) ++s; - if (*s == '\0') /* end of s, no more args */ + if (*s == '\0') /* end of s, no more args */ break; argv[argc++] = s; /* begin of argument string */ diff --git a/common/console.c b/common/console.c index 1b095b1ca..e9f23bec1 100644 --- a/common/console.c +++ b/common/console.c @@ -415,7 +415,7 @@ int console_init_r (void) stdoutname = getenv ("stdout"); stderrname = getenv ("stderr"); - if (OVERWRITE_CONSOLE == 0) { /* if not overwritten by config switch */ + if (OVERWRITE_CONSOLE == 0) { /* if not overwritten by config switch */ inputdev = search_device (DEV_FLAGS_INPUT, stdinname); outputdev = search_device (DEV_FLAGS_OUTPUT, stdoutname); errdev = search_device (DEV_FLAGS_OUTPUT, stderrname); @@ -494,7 +494,13 @@ int console_init_r (void) /* suppress all output if splash screen is enabled and we have a bmp to display */ if (getenv("splashimage") != NULL) - gd->flags |= GD_FLG_SILENT; + outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev"); +#endif + +#ifdef CONFIG_SILENT_CONSOLE + /* Suppress all output if "silent" mode requested */ + if (gd->flags & GD_FLG_SILENT) + outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev"); #endif /* Scan devices looking for input and output devices */ diff --git a/common/devices.c b/common/devices.c index 9cc963ac2..ddf8f8ee2 100644 --- a/common/devices.c +++ b/common/devices.c @@ -125,7 +125,7 @@ int device_deregister(char *devname) device_t *dev = NULL; char temp_names[3][8]; - dev_index = -1; + dev_index=-1; for (i=1; i<=ListNumItems(devlist); i++) { dev = ListGetPtrToItem (devlist, i); if(strcmp(dev->name,devname)==0) { diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 4a185620f..20c206913 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1,5 +1,3 @@ -#include - #if 0 /* Moved to malloc.h */ /* ---------- To make a malloc.h, start cutting here ------------ */ @@ -949,6 +947,7 @@ void malloc_stats(); #endif /* 0 */ #endif /* 0 */ /* Moved to malloc.h */ +#include DECLARE_GLOBAL_DATA_PTR; @@ -1457,7 +1456,7 @@ typedef struct malloc_chunk* mbinptr; indexing, maintain locality, and avoid some initialization tests. */ -#define top (av_[2]) /* The topmost chunk */ +#define top (bin_at(0)->fd) /* The topmost chunk */ #define last_remainder (bin_at(1)) /* remainder from last split */ @@ -1552,14 +1551,13 @@ void malloc_bin_reloc (void) #define BINBLOCKWIDTH 4 /* bins per block */ -#define binblocks_r ((INTERNAL_SIZE_T)av_[1]) /* bitvector of nonempty blocks */ -#define binblocks_w (av_[1]) +#define binblocks (bin_at(0)->size) /* bitvector of nonempty blocks */ /* bin<->block macros */ #define idx2binblock(ix) ((unsigned)1 << (ix / BINBLOCKWIDTH)) -#define mark_binblock(ii) (binblocks_w = (mbinptr)(binblocks_r | idx2binblock(ii))) -#define clear_binblock(ii) (binblocks_w = (mbinptr)(binblocks_r & ~(idx2binblock(ii)))) +#define mark_binblock(ii) (binblocks |= idx2binblock(ii)) +#define clear_binblock(ii) (binblocks &= ~(idx2binblock(ii))) @@ -2251,17 +2249,17 @@ Void_t* mALLOc(bytes) size_t bytes; search for best fitting chunk by scanning bins in blockwidth units. */ - if ( (block = idx2binblock(idx)) <= binblocks_r) + if ( (block = idx2binblock(idx)) <= binblocks) { /* Get to the first marked block */ - if ( (block & binblocks_r) == 0) + if ( (block & binblocks) == 0) { /* force to an even block boundary */ idx = (idx & ~(BINBLOCKWIDTH - 1)) + BINBLOCKWIDTH; block <<= 1; - while ((block & binblocks_r) == 0) + while ((block & binblocks) == 0) { idx += BINBLOCKWIDTH; block <<= 1; @@ -2316,7 +2314,7 @@ Void_t* mALLOc(bytes) size_t bytes; { if ((startidx & (BINBLOCKWIDTH - 1)) == 0) { - av_[1] = (mbinptr)(binblocks_r & ~block); + binblocks &= ~block; break; } --startidx; @@ -2325,9 +2323,9 @@ Void_t* mALLOc(bytes) size_t bytes; /* Get to the next possibly nonempty block */ - if ( (block <<= 1) <= binblocks_r && (block != 0) ) + if ( (block <<= 1) <= binblocks && (block != 0) ) { - while ((block & binblocks_r) == 0) + while ((block & binblocks) == 0) { idx += BINBLOCKWIDTH; block <<= 1; diff --git a/common/docecc.c b/common/docecc.c index 5daa6fc40..79adb4895 100644 --- a/common/docecc.c +++ b/common/docecc.c @@ -31,7 +31,7 @@ #undef ECC_DEBUG #undef PSYCHO_DEBUG -#if defined(CONFIG_CMD_DOC) +#if (CONFIG_COMMANDS & CFG_CMD_DOC) #include @@ -514,4 +514,4 @@ int doc_decode_ecc(unsigned char sector[SECTOR_SIZE], unsigned char ecc1[6]) return nb_errors; } -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_DOC) */ diff --git a/common/env_common.c b/common/env_common.c index d51c2114d..29ac5b921 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -30,6 +30,13 @@ #include #include +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_AMIGAONEG3SE @@ -50,6 +57,7 @@ extern void env_relocate_spec (void); extern uchar env_get_char_spec(int); static uchar env_get_char_init (int index); +uchar (*env_get_char)(int) = env_get_char_init; /************************************************************************ * Default settings to be used when no valid environment is found @@ -133,8 +141,7 @@ uchar default_environment[] = { "\0" }; -#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ \ - || defined(CFG_ENV_IS_IN_SPI_FLASH) +#if defined(CFG_ENV_IS_IN_NAND) /* Environment is in Nand Flash */ int default_environment_size = sizeof(default_environment); #endif @@ -182,19 +189,6 @@ uchar env_get_char_memory (int index) } #endif -uchar env_get_char (int index) -{ - uchar c; - - /* if relocated to RAM */ - if (gd->flags & GD_FLG_RELOC) - c = env_get_char_memory(index); - else - c = env_get_char_init(index); - - return (c); -} - uchar *env_get_addr (int index) { if (gd->env_valid) { @@ -204,23 +198,6 @@ uchar *env_get_addr (int index) } } -void set_default_env(void) -{ - if (sizeof(default_environment) > ENV_SIZE) { - puts ("*** Error - default environment is too large\n\n"); - return; - } - - memset(env_ptr, 0, sizeof(env_t)); - memcpy(env_ptr->data, default_environment, - sizeof(default_environment)); -#ifdef CFG_REDUNDAND_ENVIRONMENT - env_ptr->flags = 0xFF; -#endif - env_crc_update (); - gd->env_valid = 1; -} - void env_relocate (void) { DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__, @@ -245,14 +222,34 @@ void env_relocate (void) DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); #endif + /* + * After relocation to RAM, we can always use the "memory" functions + */ + env_get_char = env_get_char_memory; + if (gd->env_valid == 0) { #if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */ puts ("Using default environment\n\n"); #else puts ("*** Warning - bad CRC, using default environment\n\n"); - show_boot_progress (-60); + SHOW_BOOT_PROGRESS (-1); #endif - set_default_env(); + + if (sizeof(default_environment) > ENV_SIZE) + { + puts ("*** Error - default environment is too large\n\n"); + return; + } + + memset (env_ptr, 0, sizeof(env_t)); + memcpy (env_ptr->data, + default_environment, + sizeof(default_environment)); +#ifdef CFG_REDUNDAND_ENVIRONMENT + env_ptr->flags = 0xFF; +#endif + env_crc_update (); + gd->env_valid = 1; } else { env_relocate_spec (); @@ -281,7 +278,7 @@ int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf) ; lval = (char *)env_get_addr(i); - rval = strchr(lval, '='); + rval = (char *)strchr(lval, '='); if (rval != NULL) { vallen = rval - lval; rval++; diff --git a/common/env_dataflash.c b/common/env_dataflash.c index 294536461..93fff29b0 100644 --- a/common/env_dataflash.c +++ b/common/env_dataflash.c @@ -44,22 +44,22 @@ extern uchar default_environment[]; uchar env_get_char_spec (int index) { uchar c; - read_dataflash(CFG_ENV_ADDR + index + offsetof(env_t,data), - 1, (char *)&c); + read_dataflash (CFG_ENV_ADDR+index+offsetof(env_t,data),1,&c); return (c); } void env_relocate_spec (void) { - read_dataflash(CFG_ENV_ADDR, CFG_ENV_SIZE, (char *)env_ptr); + read_dataflash (CFG_ENV_ADDR,CFG_ENV_SIZE,(uchar *)env_ptr); } int saveenv(void) { - /* env must be copied to do not alter env structure in memory*/ - unsigned char temp[CFG_ENV_SIZE]; +/* env must be copied to do not alter env structure in memory*/ +unsigned char temp[CFG_ENV_SIZE]; +int i; memcpy(temp, env_ptr, CFG_ENV_SIZE); - return write_dataflash(CFG_ENV_ADDR, (unsigned long)temp, CFG_ENV_SIZE); + return write_dataflash (CFG_ENV_ADDR, (unsigned long)temp, CFG_ENV_SIZE); } /************************************************************************ @@ -77,14 +77,13 @@ int env_init(void) AT91F_DataflashInit(); /* prepare for DATAFLASH read/write */ /* read old CRC */ - read_dataflash(CFG_ENV_ADDR + offsetof(env_t, crc), - sizeof(ulong), (char *)&crc); + read_dataflash (CFG_ENV_ADDR+offsetof(env_t,crc),sizeof(ulong),&crc); new = 0; len = ENV_SIZE; off = offsetof(env_t,data); while (len > 0) { int n = (len > sizeof(buf)) ? sizeof(buf) : len; - read_dataflash(CFG_ENV_ADDR + off, n, (char *)buf); + read_dataflash (CFG_ENV_ADDR+off,n , buf); new = crc32 (new, buf, n); len -= n; off += n; @@ -98,7 +97,7 @@ int env_init(void) } } - return (0); + return (0); } #endif /* CFG_ENV_IS_IN_DATAFLASH */ diff --git a/common/env_eeprom.c b/common/env_eeprom.c index 9e1a20194..2adc129c6 100644 --- a/common/env_eeprom.c +++ b/common/env_eeprom.c @@ -38,6 +38,10 @@ env_t *env_ptr = NULL; char * env_name_spec = "EEPROM"; +extern uchar (*env_get_char)(int); +extern uchar env_get_char_memory (int index); + + uchar env_get_char_spec (int index) { uchar c; diff --git a/common/env_flash.c b/common/env_flash.c index a92160ddf..7dd29172a 100644 --- a/common/env_flash.c +++ b/common/env_flash.c @@ -37,10 +37,10 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH) +#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH)) #define CMD_SAVEENV #elif defined(CFG_ENV_ADDR_REDUND) -#error Cannot use CFG_ENV_ADDR_REDUND without CONFIG_CMD_ENV & CONFIG_CMD_FLASH +#error Cannot use CFG_ENV_ADDR_REDUND without CFG_CMD_ENV & CFG_CMD_FLASH #endif #if defined(CFG_ENV_SIZE_REDUND) && (CFG_ENV_SIZE_REDUND < CFG_ENV_SIZE) @@ -53,6 +53,22 @@ DECLARE_GLOBAL_DATA_PTR; # endif #endif +#if (defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE)) || defined (ENV_IS_VARIABLE) +#define SMALL_SECTOR 1 +#endif + +#ifdef ENV_IS_VARIABLE +char * flash_env_name_spec = "Flash"; +/* update these elsewhere */ +extern env_t *env_ptr; + +#ifdef CMD_SAVEENV +/* static env_t *flash_addr = (env_t *)(&environment[0]);-broken on ARM-wd-*/ +env_t *flash_addr = 0; +#endif + +#else /* !ENV_IS_VARIABLE */ + char * env_name_spec = "Flash"; #ifdef ENV_IS_EMBEDDED @@ -63,6 +79,7 @@ env_t *env_ptr = (env_t *)(&environment[0]); #ifdef CMD_SAVEENV /* static env_t *flash_addr = (env_t *)(&environment[0]);-broken on ARM-wd-*/ static env_t *flash_addr = (env_t *)CFG_ENV_ADDR; + #endif #else /* ! ENV_IS_EMBEDDED */ @@ -85,11 +102,17 @@ static ulong end_addr_new = CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1; #define OBSOLETE_FLAG 0 #endif /* CFG_ENV_ADDR_REDUND */ +#endif /* ENV_IS_VARIABLE */ + extern uchar default_environment[]; extern int default_environment_size; +#ifdef ENV_IS_VARIABLE +uchar flash_env_get_char_spec (int index) +#else uchar env_get_char_spec (int index) +#endif { return ( *((uchar *)(gd->env_addr + index)) ); } @@ -147,6 +170,10 @@ int saveenv(void) char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG; #if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE ulong up_data = 0; +#else +#if SMALL_SECTOR + ulong up_data = 0; +#endif #endif debug ("Protect off %08lX ... %08lX\n", @@ -163,7 +190,8 @@ int saveenv(void) goto Done; } -#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE +#if SMALL_SECTOR + if (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) { up_data = (end_addr_new + 1 - ((long)flash_addr_new + CFG_ENV_SIZE)); debug ("Data to save 0x%x\n", up_data); if (up_data) { @@ -191,7 +219,7 @@ int saveenv(void) debug (" %08lX ... %08lX ...", (ulong)&(flash_addr_new->data), sizeof(env_ptr->data)+(ulong)&(flash_addr_new->data)); - if ((rc = flash_write((char *)env_ptr->data, + if ((rc = flash_write(env_ptr->data, (ulong)&(flash_addr_new->data), sizeof(env_ptr->data))) || (rc = flash_write((char *)&(env_ptr->crc), @@ -209,7 +237,7 @@ int saveenv(void) } puts ("done\n"); -#if CFG_ENV_SECT_SIZE > CFG_ENV_SIZE +#if SMALL_SECTOR if (up_data) { /* restore the rest of sector */ debug ("Restoring the rest of data to 0x%x len 0x%x\n", (long)flash_addr_new + CFG_ENV_SIZE, up_data); @@ -240,15 +268,19 @@ Done: /* try to re-protect */ (void) flash_sect_protect (1, (ulong)flash_addr, end_addr); (void) flash_sect_protect (1, (ulong)flash_addr_new, end_addr_new); - return rc; } #endif /* CMD_SAVEENV */ #else /* ! CFG_ENV_ADDR_REDUND */ +#ifdef ENV_IS_VARIABLE +int flash_env_init(void) +#else int env_init(void) +#endif { + if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { gd->env_addr = (ulong)&(env_ptr->data); gd->env_valid = 1; @@ -262,20 +294,23 @@ int env_init(void) #ifdef CMD_SAVEENV +#ifdef ENV_IS_VARIABLE +int flash_saveenv(void) +#else int saveenv(void) +#endif { int len, rc; ulong end_addr; ulong flash_sect_addr; -#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) +#if SMALL_SECTOR ulong flash_offset; uchar env_buffer[CFG_ENV_SECT_SIZE]; #else uchar *env_buffer = (uchar *)env_ptr; #endif /* CFG_ENV_SECT_SIZE */ int rcode = 0; - -#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) +#if SMALL_SECTOR flash_offset = ((ulong)flash_addr) & (CFG_ENV_SECT_SIZE-1); flash_sect_addr = ((ulong)flash_addr) & ~(CFG_ENV_SECT_SIZE-1); @@ -334,9 +369,13 @@ int saveenv(void) #endif /* CFG_ENV_ADDR_REDUND */ +#ifdef ENV_IS_VARIABLE +void flash_env_relocate_spec(void) +#else void env_relocate_spec (void) +#endif { -#if !defined(ENV_IS_EMBEDDED) || defined(CFG_ENV_ADDR_REDUND) +#if defined(ENV_IS_VARIABLE) || !defined(ENV_IS_EMBEDDED) || defined(CFG_ENV_ADDR_REDUND) #ifdef CFG_ENV_ADDR_REDUND if (gd->env_addr != (ulong)&(flash_addr->data)) { env_t * etmp = flash_addr; @@ -378,9 +417,7 @@ void env_relocate_spec (void) puts ("*** Warning - some problems detected " "reading environment; recovered successfully\n\n"); #endif /* CFG_ENV_ADDR_REDUND */ -#ifdef CMD_SAVEENV memcpy (env_ptr, (void*)flash_addr, CFG_ENV_SIZE); -#endif #endif /* ! ENV_IS_EMBEDDED || CFG_ENV_ADDR_REDUND */ } diff --git a/common/env_mmc.c b/common/env_mmc.c new file mode 100644 index 000000000..26e728b69 --- /dev/null +++ b/common/env_mmc.c @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2009 Texas Instruments, + * Kishore Kadiyala + * Moiz Sonasath + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CFG_ENV_IS_IN_EMMC) /* Environment is in EMMC */ + +#include +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* References to names in env_common.c */ +extern uchar default_environment[]; + +#ifdef ENV_IS_VARIABLE +char *mmc_env_name_spec = "EMMC"; +/* update these elsewhere */ +extern env_t *env_ptr; + +#else /* !ENV_IS_VARIABLE */ + +char *env_name_spec = "EMMC"; + +#ifdef ENV_IS_EMBEDDED +extern uchar environment[]; +env_t *env_ptr = (env_t *)(&environment[0]); +#else /* ! ENV_IS_EMBEDDED */ +env_t *env_ptr = (env_t *)CFG_ENV_ADDR; +#endif /* ENV_IS_EMBEDDED */ + +#endif /* ENV_IS_VARIABLE */ + +#ifdef ENV_IS_VARIABLE +uchar mmc_env_get_char_spec(int index) +#else +uchar env_get_char_spec(int index) +#endif +{ + return *((uchar *)(gd->env_addr + index)); +} + +#ifdef ENV_IS_VARIABLE +void mmc_env_relocate_spec(void) +#else +void env_relocate_spec(void) +#endif +{ + unsigned int mmc_cont = 1; + unsigned long env_addr; + int use_default = 0; + + env_addr = CFG_ENV_ADDR; + + mmc_init(mmc_cont); + mmc_read(mmc_cont, env_addr, (u_char *) env_ptr, CFG_ENV_SIZE); + + if (crc32(0, env_ptr->data, CFG_ENV_SIZE) != env_ptr->crc) + use_default = 1; + + if (use_default) { + memcpy(env_ptr->data, default_environment, CFG_ENV_SIZE); + env_ptr->crc = crc32(0, env_ptr->data, CFG_ENV_SIZE); + } +} + +#ifdef ENV_IS_VARIABLE +int mmc_saveenv(void) +#else +int saveenv(void) +#endif +{ + unsigned long env_addr = CFG_ENV_ADDR; + int len; + int mmc_cont = 1; + + len = CFG_ENV_SIZE; + puts("Erasing MMC..."); + mmc_erase(mmc_cont, env_addr, len); + printf("done\n"); + + /* update crc */ + env_ptr->crc = crc32(0, env_ptr->data, len); + puts("Writing to MMC... "); + mmc_write(mmc_cont, (u_char *) env_ptr, env_addr, len); + printf("done\n"); + + gd->env_valid = 1; + return 0; + +} + +#ifdef ENV_IS_VARIABLE +int mmc_env_init(void) +#else +int env_init(void) +#endif +{ + /* use default */ + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 1; + return 0; +} + +#endif /* CFG_ENV_IS_IN_EMMC */ diff --git a/common/env_nand.c b/common/env_nand.c index 104f0856a..4e4afdb7d 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -1,11 +1,8 @@ /* - * (C) Copyright 2008 - * Stuart Wood, Lab X Technologies - * * (C) Copyright 2004 * Jian Zhang, Texas Instruments, jzhang@ti.com. - * (C) Copyright 2000-2006 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH @@ -42,10 +39,10 @@ #include #include -#if defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND) +#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_NAND)) == (CFG_CMD_ENV|CFG_CMD_NAND)) #define CMD_SAVEENV #elif defined(CFG_ENV_OFFSET_REDUND) -#error Cannot use CFG_ENV_OFFSET_REDUND without CONFIG_CMD_ENV & CONFIG_CMD_NAND +#error Cannot use CFG_ENV_OFFSET_REDUND without CFG_CMD_ENV & CFG_CMD_NAND #endif #if defined(CFG_ENV_SIZE_REDUND) && (CFG_ENV_SIZE_REDUND != CFG_ENV_SIZE) @@ -56,20 +53,24 @@ #error CONFIG_INFERNO not supported yet #endif -#ifndef CFG_ENV_RANGE -#define CFG_ENV_RANGE CFG_ENV_SIZE -#endif - int nand_legacy_rw (struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); +/* info for NAND chips, defined in drivers/nand/nand.c */ +extern nand_info_t nand_info[]; + /* references to names in env_common.c */ extern uchar default_environment[]; extern int default_environment_size; -char * env_name_spec = "NAND"; +#ifdef ENV_IS_VARIABLE +char * nand_env_name_spec = "NAND"; +extern env_t *env_ptr; +#else /* !ENV_IS_VARIABLE */ + +char * env_name_spec = "NAND"; #ifdef ENV_IS_EMBEDDED extern uchar environment[]; @@ -78,15 +79,18 @@ env_t *env_ptr = (env_t *)(&environment[0]); env_t *env_ptr = 0; #endif /* ENV_IS_EMBEDDED */ +#endif /* ENV_IS_VARIABLE */ /* local functions */ -#if !defined(ENV_IS_EMBEDDED) static void use_default(void); -#endif DECLARE_GLOBAL_DATA_PTR; +#ifdef ENV_IS_VARIABLE +uchar nand_env_get_char_spec (int index) +#else uchar env_get_char_spec (int index) +#endif { return ( *((uchar *)(gd->env_addr + index)) ); } @@ -95,57 +99,17 @@ uchar env_get_char_spec (int index) /* this is called before nand_init() * so we can't read Nand to validate env data. * Mark it OK for now. env_relocate() in env_common.c - * will call our relocate function which does the real - * validation. - * - * When using a NAND boot image (like sequoia_nand), the environment - * can be embedded or attached to the U-Boot image in NAND flash. This way - * the SPL loads not only the U-Boot image from NAND but also the - * environment. + * will call our relocate function which will does + * the real validation. */ +#ifdef ENV_IS_VARIABLE +int nand_env_init(void) +#else int env_init(void) +#endif { -#if defined(ENV_IS_EMBEDDED) - size_t total; - int crc1_ok = 0, crc2_ok = 0; - env_t *tmp_env1, *tmp_env2; - - total = CFG_ENV_SIZE; - - tmp_env1 = env_ptr; - tmp_env2 = (env_t *)((ulong)env_ptr + CFG_ENV_SIZE); - - crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc); - crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc); - - if (!crc1_ok && !crc2_ok) - gd->env_valid = 0; - else if(crc1_ok && !crc2_ok) - gd->env_valid = 1; - else if(!crc1_ok && crc2_ok) - gd->env_valid = 2; - else { - /* both ok - check serial */ - if(tmp_env1->flags == 255 && tmp_env2->flags == 0) - gd->env_valid = 2; - else if(tmp_env2->flags == 255 && tmp_env1->flags == 0) - gd->env_valid = 1; - else if(tmp_env1->flags > tmp_env2->flags) - gd->env_valid = 1; - else if(tmp_env2->flags > tmp_env1->flags) - gd->env_valid = 2; - else /* flags are equal - almost impossible */ - gd->env_valid = 1; - } - - if (gd->env_valid == 1) - env_ptr = tmp_env1; - else if (gd->env_valid == 2) - env_ptr = tmp_env2; -#else /* ENV_IS_EMBEDDED */ gd->env_addr = (ulong)&default_environment[0]; gd->env_valid = 1; -#endif /* ENV_IS_EMBEDDED */ return (0); } @@ -155,101 +119,118 @@ int env_init(void) * The legacy NAND code saved the environment in the first NAND device i.e., * nand_dev_desc + 0. This is also the behaviour using the new NAND code. */ -int writeenv(size_t offset, u_char *buf) -{ - size_t end = offset + CFG_ENV_RANGE; - size_t amount_saved = 0; - size_t blocksize; - - u_char *char_ptr; - - blocksize = nand_info[0].erasesize; - - while (amount_saved < CFG_ENV_SIZE && offset < end) { - if (nand_block_isbad(&nand_info[0], offset)) { - offset += blocksize; - } else { - char_ptr = &buf[amount_saved]; - if (nand_write(&nand_info[0], offset, &blocksize, - char_ptr)) - return 1; - offset += blocksize; - amount_saved += blocksize; - } - } - if (amount_saved != CFG_ENV_SIZE) - return 1; - - return 0; -} #ifdef CFG_ENV_OFFSET_REDUND +#ifdef ENV_IS_VARIABLE +int nand_saveenv(void) +#else int saveenv(void) +#endif { - size_t total; + ulong total; int ret = 0; - nand_erase_options_t nand_erase_options; + int quiet = 0; + const char *quiet_str = getenv("quiet"); + nand_write_options_t w_opts; + nand_erase_options_t e_opts; + + if (quiet_str) + quiet = simple_strtoul(quiet_str, NULL, 0) != 0; env_ptr->flags++; total = CFG_ENV_SIZE; - nand_erase_options.length = CFG_ENV_RANGE; - nand_erase_options.quiet = 0; - nand_erase_options.jffs2 = 0; - nand_erase_options.scrub = 0; - - if (CFG_ENV_RANGE < CFG_ENV_SIZE) - return 1; if(gd->env_valid == 1) { - puts ("Erasing redundant Nand...\n"); - nand_erase_options.offset = CFG_ENV_OFFSET_REDUND; - if (nand_erase_opts(&nand_info[0], &nand_erase_options)) + puts ("Erasing redundant Nand..."); + memset(&e_opts, 0, sizeof(e_opts)); + e_opts.offset = CFG_ENV_OFFSET_REDUND; + e_opts.length = CFG_ENV_SIZE; + e_opts.jffs2 = 0; + e_opts.quiet = quiet; + + if (nand_erase_opts(&nand_info[0], &e_opts)) return 1; puts ("Writing to redundant Nand... "); - ret = writeenv(CFG_ENV_OFFSET_REDUND, (u_char *) env_ptr); + /* write */ + memset(&w_opts, 0, sizeof(w_opts)); + w_opts.buffer = (u_char*) env_ptr; + w_opts.length = total; + w_opts.offset = CFG_ENV_OFFSET_REDUND; + /* opts.forcejffs2 = 1; */ + w_opts.pad = 0; + w_opts.blockalign = 1; + w_opts.quiet = quiet; + + ret = nand_write_opts(&nand_info[0], &w_opts); } else { - puts ("Erasing Nand...\n"); - nand_erase_options.offset = CFG_ENV_OFFSET; - if (nand_erase_opts(&nand_info[0], &nand_erase_options)) + puts ("Erasing Nand..."); + memset(&e_opts, 0, sizeof(e_opts)); + e_opts.offset = CFG_ENV_OFFSET; + e_opts.length = CFG_ENV_SIZE; + e_opts.jffs2 = 0; + e_opts.quiet = quiet; + + if (nand_erase_opts(&nand_info[0], &e_opts)) return 1; puts ("Writing to Nand... "); - ret = writeenv(CFG_ENV_OFFSET, (u_char *) env_ptr); + memset(&w_opts, 0, sizeof(w_opts)); + w_opts.buffer = (u_char*) env_ptr; + w_opts.length = total; + w_opts.offset = CFG_ENV_OFFSET; + /* w_opts.forcejffs2 = 1; */ + w_opts.pad = 0; + w_opts.blockalign = 1; + w_opts.quiet = quiet; + + ret = nand_write_opts(&nand_info[0], &w_opts); } - if (ret) { - puts("FAILED!\n"); + if (ret || total != CFG_ENV_SIZE) return 1; - } puts ("done\n"); gd->env_valid = (gd->env_valid == 2 ? 1 : 2); return ret; } #else /* ! CFG_ENV_OFFSET_REDUND */ +#ifdef ENV_IS_VARIABLE +int nand_saveenv(void) +#else int saveenv(void) +#endif { - size_t total; + ulong total; int ret = 0; - nand_erase_options_t nand_erase_options; + int quiet = 0; + const char *quiet_str = getenv("quiet"); + nand_write_options_t w_opts; + nand_erase_options_t e_opts; - nand_erase_options.length = CFG_ENV_RANGE; - nand_erase_options.quiet = 0; - nand_erase_options.jffs2 = 0; - nand_erase_options.scrub = 0; - nand_erase_options.offset = CFG_ENV_OFFSET; + if (quiet_str) + quiet = simple_strtoul(quiet_str, NULL, 0) != 0; - if (CFG_ENV_RANGE < CFG_ENV_SIZE) - return 1; - puts ("Erasing Nand...\n"); - if (nand_erase_opts(&nand_info[0], &nand_erase_options)) + puts ("Erasing Nand..."); + memset(&e_opts, 0, sizeof(e_opts)); + e_opts.offset = CFG_ENV_OFFSET; + e_opts.length = CFG_ENV_SIZE; + e_opts.jffs2 = 0; + e_opts.quiet = quiet; + + if (nand_erase_opts(&nand_info[0], &e_opts)) return 1; puts ("Writing to Nand... "); total = CFG_ENV_SIZE; - if (writeenv(CFG_ENV_OFFSET, (u_char *) env_ptr)) { - puts("FAILED!\n"); - return 1; - } + memset(&w_opts, 0, sizeof(w_opts)); + w_opts.buffer = (u_char*) env_ptr; + w_opts.length = total; + w_opts.offset = CFG_ENV_OFFSET; + /* w_opts.forcejffs2 = 1; */ + w_opts.pad = 0; + w_opts.blockalign = 1; + w_opts.quiet = quiet; + + ret = nand_write_opts(&nand_info[0], &w_opts); puts ("done\n"); return ret; @@ -257,50 +238,42 @@ int saveenv(void) #endif /* CFG_ENV_OFFSET_REDUND */ #endif /* CMD_SAVEENV */ -int readenv (size_t offset, u_char * buf) -{ - size_t end = offset + CFG_ENV_RANGE; - size_t amount_loaded = 0; - size_t blocksize; - - u_char *char_ptr; - - blocksize = nand_info[0].erasesize; - - while (amount_loaded < CFG_ENV_SIZE && offset < end) { - if (nand_block_isbad(&nand_info[0], offset)) { - offset += blocksize; - } else { - char_ptr = &buf[amount_loaded]; - if (nand_read(&nand_info[0], offset, &blocksize, char_ptr)) - return 1; - offset += blocksize; - amount_loaded += blocksize; - } - } - if (amount_loaded != CFG_ENV_SIZE) - return 1; - - return 0; -} - #ifdef CFG_ENV_OFFSET_REDUND +#ifdef ENV_IS_VARIABLE +void nand_env_relocate_spec (void) +#else void env_relocate_spec (void) +#endif { #if !defined(ENV_IS_EMBEDDED) - size_t total; + ulong total; int crc1_ok = 0, crc2_ok = 0; env_t *tmp_env1, *tmp_env2; + int quiet = 0; + const char *quiet_str = getenv("quiet"); + nand_read_options_t r_opts; + + if (quiet_str) + quiet = simple_strtoul(quiet_str, NULL, 0) != 0; total = CFG_ENV_SIZE; tmp_env1 = (env_t *) malloc(CFG_ENV_SIZE); tmp_env2 = (env_t *) malloc(CFG_ENV_SIZE); - if (readenv(CFG_ENV_OFFSET, (u_char *) tmp_env1)) - puts("No Valid Environment Area Found\n"); - if (readenv(CFG_ENV_OFFSET_REDUND, (u_char *) tmp_env2)) - puts("No Valid Reundant Environment Area Found\n"); + memset(&r_opts, 0, sizeof(r_opts)); + r_opts.buffer = (u_char*) tmp_env1; + r_opts.length = total; + r_opts.offset = CFG_ENV_OFFSET; + r_opts.quiet = quiet; + nand_read_opts(&nand_info[0], &r_opts); + + memset(&r_opts, 0, sizeof(r_opts)); + r_opts.buffer = (u_char*) tmp_env2; + r_opts.length = total; + r_opts.offset = CFG_ENV_OFFSET_REDUND; + r_opts.quiet = quiet; + nand_read_opts(&nand_info[0], &r_opts); crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc); crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc); @@ -342,15 +315,30 @@ void env_relocate_spec (void) * The legacy NAND code saved the environment in the first NAND device i.e., * nand_dev_desc + 0. This is also the behaviour using the new NAND code. */ +#ifdef ENV_IS_VARIABLE +void nand_env_relocate_spec (void) +#else void env_relocate_spec (void) +#endif { #if !defined(ENV_IS_EMBEDDED) - size_t total; + ulong total; int ret; + const char *quiet_str = getenv("quiet"); + int quiet = 0; + nand_read_options_t r_opts; + + if (quiet_str) + quiet = simple_strtoul(quiet_str, NULL, 0) != 0; total = CFG_ENV_SIZE; - ret = readenv(CFG_ENV_OFFSET, (u_char *) env_ptr); - if (ret || total != CFG_ENV_SIZE) + memset(&r_opts, 0, sizeof(r_opts)); + r_opts.buffer = (u_char*) env_ptr; + r_opts.length = total; + r_opts.offset = CFG_ENV_OFFSET; + r_opts.quiet = quiet; + ret = nand_read_opts(&nand_info[0], &r_opts); + if (ret || total != CFG_ENV_SIZE) return use_default(); if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc) @@ -359,12 +347,22 @@ void env_relocate_spec (void) } #endif /* CFG_ENV_OFFSET_REDUND */ -#if !defined(ENV_IS_EMBEDDED) static void use_default() { puts ("*** Warning - bad CRC or NAND, using default environment\n\n"); - set_default_env(); + + if (default_environment_size > CFG_ENV_SIZE){ + puts ("*** Error - default environment is too large\n\n"); + return; + } + + memset (env_ptr, 0, sizeof(env_t)); + memcpy (env_ptr->data, + default_environment, + default_environment_size); + env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); + gd->env_valid = 1; + } -#endif #endif /* CFG_ENV_IS_IN_NAND */ diff --git a/common/env_nvram.c b/common/env_nvram.c index fa7771912..7c18896cb 100644 --- a/common/env_nvram.c +++ b/common/env_nvram.c @@ -63,6 +63,9 @@ char * env_name_spec = "NVRAM"; extern uchar default_environment[]; extern int default_environment_size; +extern uchar (*env_get_char)(int); +extern uchar env_get_char_memory (int index); + #ifdef CONFIG_AMIGAONEG3SE uchar env_get_char_spec (int index) { diff --git a/common/env_onenand.c b/common/env_onenand.c index dbd0883fa..274e52d10 100644 --- a/common/env_onenand.c +++ b/common/env_onenand.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005-2007 Samsung Electronics + * (C) Copyright 2005 Samsung Electronics * Kyungmin Park * * See file CREDITS for list of people who contributed to this @@ -30,8 +30,6 @@ #include #include -#include -#include #include extern struct mtd_info onenand_mtd; @@ -42,25 +40,43 @@ extern uchar default_environment[]; #define ONENAND_ENV_SIZE(mtd) (mtd.oobblock - ENV_HEADER_SIZE) -char *env_name_spec = "OneNAND"; +#ifdef ENV_IS_VARIABLE +char * onenand_env_name_spec = "OneNAND"; +unsigned char onenand_env[MAX_ONENAND_PAGESIZE]; +extern env_t *env_ptr; + +#else /* !ENV_IS_VARIABLE */ + +char * env_name_spec = "OneNAND"; #ifdef ENV_IS_EMBEDDED extern uchar environment[]; env_t *env_ptr = (env_t *) (&environment[0]); -#else /* ! ENV_IS_EMBEDDED */ +#else /* ! ENV_IS_EMBEDDED */ static unsigned char onenand_env[MAX_ONENAND_PAGESIZE]; env_t *env_ptr = (env_t *) onenand_env; -#endif /* ENV_IS_EMBEDDED */ +#endif /* ENV_IS_EMBEDDED */ -DECLARE_GLOBAL_DATA_PTR; +#endif /* ENV_IS_VARIABLE */ -uchar env_get_char_spec(int index) +#ifdef ENV_IS_VARIABLE +uchar onenand_env_get_char_spec (int index) +#else +uchar env_get_char_spec (int index) +#endif { - return (*((uchar *) (gd->env_addr + index))); + DECLARE_GLOBAL_DATA_PTR; + + return (*((uchar *)(gd->env_addr + index))); } +#ifdef ENV_IS_VARIABLE +void onenand_env_relocate_spec(void) +#else void env_relocate_spec(void) +#endif { + DECLARE_GLOBAL_DATA_PTR; unsigned long env_addr; int use_default = 0; size_t retlen; @@ -68,63 +84,73 @@ void env_relocate_spec(void) env_addr = CFG_ENV_ADDR; /* Check OneNAND exist */ + if (onenand_mtd.oobblock) /* Ignore read fail */ onenand_read(&onenand_mtd, env_addr, onenand_mtd.oobblock, - &retlen, (u_char *) env_ptr); + &retlen, (u_char *) env_ptr); else onenand_mtd.oobblock = MAX_ONENAND_PAGESIZE; + - if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)) != - env_ptr->crc) + if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)) != env_ptr->crc) use_default = 1; if (use_default) { - memcpy(env_ptr->data, default_environment, - ONENAND_ENV_SIZE(onenand_mtd)); - env_ptr->crc = - crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)); + memcpy(env_ptr->data, default_environment, ONENAND_ENV_SIZE(onenand_mtd)); + env_ptr->crc = crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)); } - gd->env_addr = (ulong) & env_ptr->data; + gd->env_addr = (ulong) &env_ptr->data; gd->env_valid = 1; } +#ifdef ENV_IS_VARIABLE +int onenand_saveenv(void) +#else int saveenv(void) +#endif { unsigned long env_addr = CFG_ENV_ADDR; - struct erase_info instr = { - .callback = NULL, - }; + struct erase_info instr; size_t retlen; + instr.len = CFG_ENV_SIZE; instr.addr = env_addr; + printf("Erasing oneNand..."); if (onenand_erase(&onenand_mtd, &instr)) { - printf("OneNAND: erase failed at 0x%08lx\n", env_addr); + printf("OneNAND: erase failed at 0x%08x\n", env_addr); return 1; - } + } + printf("done\n"); /* update crc */ - env_ptr->crc = - crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)); + env_ptr->crc = crc32(0, env_ptr->data, onenand_mtd.oobblock - ENV_HEADER_SIZE); - if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen, - (u_char *) env_ptr)) { + printf("Writing to oneNand... "); + if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen, (u_char *) env_ptr)) { printf("OneNAND: write failed at 0x%08x\n", instr.addr); return 2; } + printf ("done\n"); return 0; } +#ifdef ENV_IS_VARIABLE +int onenand_env_init(void) +#else int env_init(void) +#endif { + DECLARE_GLOBAL_DATA_PTR; + /* use default */ - gd->env_addr = (ulong) & default_environment[0]; + gd->env_addr = (ulong) &default_environment[0]; gd->env_valid = 1; return 0; } -#endif /* CFG_ENV_IS_IN_ONENAND */ +#endif /* CFG_ENV_IS_IN_ONENAND */ diff --git a/common/environment.c b/common/environment.c index 3b9914f49..81471ce71 100644 --- a/common/environment.c +++ b/common/environment.c @@ -51,7 +51,16 @@ * a seperate section. Note that ENV_CRC is only defined when building * U-Boot itself. */ -#if (defined(CFG_USE_PPCENV) || defined(CONFIG_NAND_U_BOOT)) && \ +#if (defined(CONFIG_CMI) || \ + defined(CONFIG_FADS) || \ + defined(CONFIG_HYMOD) || \ + defined(CONFIG_ICU862) || \ + defined(CONFIG_R360MPI) || \ + defined(CONFIG_TQM8xxL) || \ + defined(CONFIG_RRVISION) || \ + defined(CONFIG_TRAB) || \ + defined(CONFIG_PPCHAMELEONEVB) || \ + defined(CONFIG_M5271EVB)) && \ defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */ /* XXX - This only works with GNU C */ # define __PPCENV__ __attribute__ ((section(".ppcenv"))) @@ -70,16 +79,11 @@ /* * Macros to generate global absolutes. */ -#if defined(__bfin__) -# define GEN_SET_VALUE(name, value) asm (".set " GEN_SYMNAME(name) ", " GEN_VALUE(value)) -#else -# define GEN_SET_VALUE(name, value) asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) -#endif #define GEN_SYMNAME(str) SYM_CHAR #str #define GEN_VALUE(str) #str #define GEN_ABS(name, value) \ asm (".globl " GEN_SYMNAME(name)); \ - GEN_SET_VALUE(name, value) + asm (GEN_SYMNAME(name) " = " GEN_VALUE(value)) /* * Macros to transform values diff --git a/common/exports.c b/common/exports.c index ec4656bfb..ef2533816 100644 --- a/common/exports.c +++ b/common/exports.c @@ -23,19 +23,14 @@ void jumptable_init (void) gd->jt[XF_get_version] = (void *) get_version; gd->jt[XF_malloc] = (void *) malloc; gd->jt[XF_free] = (void *) free; - gd->jt[XF_getenv] = (void *) getenv; - gd->jt[XF_setenv] = (void *) setenv; - gd->jt[XF_get_timer] = (void *) get_timer; - gd->jt[XF_simple_strtoul] = (void *) simple_strtoul; - gd->jt[XF_udelay] = (void *) udelay; - gd->jt[XF_simple_strtol] = (void *) simple_strtol; - gd->jt[XF_strcmp] = (void *) strcmp; + gd->jt[XF_get_timer] = (void *)get_timer; + gd->jt[XF_udelay] = (void *)udelay; #if defined(CONFIG_I386) || defined(CONFIG_PPC) gd->jt[XF_install_hdlr] = (void *) irq_install_handler; gd->jt[XF_free_hdlr] = (void *) irq_free_handler; #endif /* I386 || PPC */ -#if defined(CONFIG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) gd->jt[XF_i2c_write] = (void *) i2c_write; gd->jt[XF_i2c_read] = (void *) i2c_read; -#endif +#endif /* CFG_CMD_I2C */ } diff --git a/common/flash.c b/common/flash.c index fe39d55ef..ce3983a1a 100644 --- a/common/flash.c +++ b/common/flash.c @@ -47,16 +47,16 @@ flash_protect (int flag, ulong from, ulong to, flash_info_t *info) short s_end = info->sector_count - 1; /* index of last sector */ int i; - /* Do nothing if input data is bad. */ - if (info->sector_count == 0 || info->size == 0 || to < from) { - return; - } - debug ("flash_protect %s: from 0x%08lX to 0x%08lX\n", (flag & FLAG_PROTECT_SET) ? "ON" : (flag & FLAG_PROTECT_CLEAR) ? "OFF" : "???", from, to); + /* Do nothing if input data is bad. */ + if (info->sector_count == 0 || info->size == 0 || to < from) { + return; + } + /* There is nothing to do if we have no data about the flash * or the protect range and flash range don't overlap. */ @@ -103,8 +103,7 @@ addr2info (ulong addr) #ifndef CONFIG_SPD823TS flash_info_t *info; int i; - - for (i=0, info = &flash_info[0]; iflash_id != FLASH_UNKNOWN && addr >= info->start[0] && /* WARNING - The '- 1' is needed if the flash @@ -117,7 +116,6 @@ addr2info (ulong addr) } } #endif /* CONFIG_SPD823TS */ - return (NULL); } diff --git a/common/fpga.c b/common/fpga.c index d16a92d70..02d3e42b3 100644 --- a/common/fpga.c +++ b/common/fpga.c @@ -67,11 +67,14 @@ static int fpga_dev_info( int devnum ); static void fpga_no_sup( char *fn, char *msg ) { if ( fn && msg ) { - printf( "%s: No support for %s.\n", fn, msg); + printf( "%s: No support for %s. CONFIG_FPGA defined as 0x%x.\n", + fn, msg, CONFIG_FPGA ); } else if ( msg ) { - printf( "No support for %s.\n", msg); + printf( "No support for %s. CONFIG_FPGA defined as 0x%x.\n", + msg, CONFIG_FPGA ); } else { - printf( "No FPGA suport!\n"); + printf( "No FPGA suport! CONFIG_FPGA defined as 0x%x.\n", + CONFIG_FPGA ); } } @@ -109,6 +112,11 @@ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_va printf( "%s: Null buffer.\n", fn ); return (fpga_desc * const)NULL; } + if ( !bsize ) { + printf( "%s: Null buffer size.\n", fn ); + return (fpga_desc * const)NULL; + } + return desc; } @@ -127,15 +135,15 @@ static int fpga_dev_info( int devnum ) switch ( desc->devtype ) { case fpga_xilinx: -#if defined(CONFIG_FPGA_XILINX) +#if CONFIG_FPGA & CFG_FPGA_XILINX printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc ); ret_val = xilinx_info( desc->devdesc ); #else - fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + fpga_no_sup( __FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: -#if defined(CONFIG_FPGA_ALTERA) +#if CONFIG_FPGA & CFG_FPGA_ALTERA printf( "Altera Device\nDescriptor @ 0x%p\n", desc ); ret_val = altera_info( desc->devdesc ); #else @@ -167,14 +175,14 @@ int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off ) switch ( devtype ) { case fpga_xilinx: -#if defined(CONFIG_FPGA_XILINX) +#if CONFIG_FPGA & CFG_FPGA_XILINX ret_val = xilinx_reloc( desc, reloc_off ); #else - fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + fpga_no_sup( __FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: -#if defined(CONFIG_FPGA_ALTERA) +#if CONFIG_FPGA & CFG_FPGA_ALTERA ret_val = altera_reloc( desc, reloc_off ); #else fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); @@ -199,6 +207,10 @@ void fpga_init( ulong reloc_off ) memset( desc_table, 0, sizeof(desc_table)); PRINTF( "%s: CONFIG_FPGA = 0x%x\n", __FUNCTION__, CONFIG_FPGA ); +#if 0 + PRINTF( "%s: CFG_FPGA_XILINX = 0x%x\n", __FUNCTION__, CFG_FPGA_XILINX ); + PRINTF( "%s: CFG_FPGA_ALTERA = 0x%x\n", __FUNCTION__, CFG_FPGA_ALTERA ); +#endif } /* fpga_count @@ -256,14 +268,14 @@ int fpga_load( int devnum, void *buf, size_t bsize ) if ( desc ) { switch ( desc->devtype ) { case fpga_xilinx: -#if defined(CONFIG_FPGA_XILINX) +#if CONFIG_FPGA & CFG_FPGA_XILINX ret_val = xilinx_load( desc->devdesc, buf, bsize ); #else - fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + fpga_no_sup( __FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: -#if defined(CONFIG_FPGA_ALTERA) +#if CONFIG_FPGA & CFG_FPGA_ALTERA ret_val = altera_load( desc->devdesc, buf, bsize ); #else fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); @@ -289,14 +301,14 @@ int fpga_dump( int devnum, void *buf, size_t bsize ) if ( desc ) { switch ( desc->devtype ) { case fpga_xilinx: -#if defined(CONFIG_FPGA_XILINX) +#if CONFIG_FPGA & CFG_FPGA_XILINX ret_val = xilinx_dump( desc->devdesc, buf, bsize ); #else - fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + fpga_no_sup( __FUNCTION__, "Xilinx devices" ); #endif break; case fpga_altera: -#if defined(CONFIG_FPGA_ALTERA) +#if CONFIG_FPGA & CFG_FPGA_ALTERA ret_val = altera_dump( desc->devdesc, buf, bsize ); #else fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); diff --git a/common/ft_build.c b/common/ft_build.c new file mode 100644 index 000000000..9e9c906fc --- /dev/null +++ b/common/ft_build.c @@ -0,0 +1,722 @@ +/* + * OF flat tree builder + */ + +#include +#include +#include + +#ifdef CONFIG_OF_FLAT_TREE + +#include +#include + +#include + +/* align addr on a size boundary - adjust address up if needed -- Cort */ +#define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1))) + +static void ft_put_word(struct ft_cxt *cxt, u32 v) +{ + if (cxt->overflow) /* do nothing */ + return; + + /* check for overflow */ + if (cxt->p + 4 > cxt->pstr) { + cxt->overflow = 1; + return; + } + + *(u32 *) cxt->p = cpu_to_be32(v); + cxt->p += 4; +} + +static inline void ft_put_bin(struct ft_cxt *cxt, const void *data, int sz) +{ + u8 *p; + + if (cxt->overflow) /* do nothing */ + return; + + /* next pointer pos */ + p = (u8 *) _ALIGN((unsigned long)cxt->p + sz, 4); + + /* check for overflow */ + if (p > cxt->pstr) { + cxt->overflow = 1; + return; + } + + memcpy(cxt->p, data, sz); + if ((sz & 3) != 0) + memset(cxt->p + sz, 0, 4 - (sz & 3)); + cxt->p = p; +} + +void ft_begin_node(struct ft_cxt *cxt, const char *name) +{ + ft_put_word(cxt, OF_DT_BEGIN_NODE); + ft_put_bin(cxt, name, strlen(name) + 1); +} + +void ft_end_node(struct ft_cxt *cxt) +{ + ft_put_word(cxt, OF_DT_END_NODE); +} + +void ft_nop(struct ft_cxt *cxt) +{ + ft_put_word(cxt, OF_DT_NOP); +} + +static int lookup_string(struct ft_cxt *cxt, const char *name) +{ + u8 *p; + + p = cxt->pstr; + while (p < cxt->pstr_begin) { + if (strcmp(p, name) == 0) + return p - cxt->p_begin; + p += strlen(p) + 1; + } + + return -1; +} + +void ft_prop(struct ft_cxt *cxt, const char *name, const void *data, int sz) +{ + int len, off; + + if (cxt->overflow) + return; + + len = strlen(name) + 1; + + off = lookup_string(cxt, name); + if (off == -1) { + /* check if we have space */ + if (cxt->p + 12 + sz + len > cxt->pstr) { + cxt->overflow = 1; + return; + } + + cxt->pstr -= len; + memcpy(cxt->pstr, name, len); + off = cxt->pstr - cxt->p_begin; + } + + /* now put offset from beginning of *STRUCTURE* */ + /* will be fixed up at the end */ + ft_put_word(cxt, OF_DT_PROP); + ft_put_word(cxt, sz); + ft_put_word(cxt, off); + ft_put_bin(cxt, data, sz); +} + +void ft_prop_str(struct ft_cxt *cxt, const char *name, const char *str) +{ + ft_prop(cxt, name, str, strlen(str) + 1); +} + +void ft_prop_int(struct ft_cxt *cxt, const char *name, int val) +{ + u32 v = cpu_to_be32((u32) val); + + ft_prop(cxt, name, &v, 4); +} + +/* start construction of the flat OF tree */ +void ft_begin(struct ft_cxt *cxt, void *blob, int max_size) +{ + struct boot_param_header *bph = blob; + u32 off; + + /* clear the cxt */ + memset(cxt, 0, sizeof(*cxt)); + + cxt->bph = bph; + cxt->max_size = max_size; + + /* zero everything in the header area */ + memset(bph, 0, sizeof(*bph)); + + bph->magic = cpu_to_be32(OF_DT_HEADER); + bph->version = cpu_to_be32(0x10); + bph->last_comp_version = cpu_to_be32(0x10); + + /* start pointers */ + cxt->pres_begin = (u8 *) _ALIGN((unsigned long)(bph + 1), 8); + cxt->pres = cxt->pres_begin; + + off = (unsigned long)cxt->pres_begin - (unsigned long)bph; + bph->off_mem_rsvmap = cpu_to_be32(off); + + ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ + ((u64 *) cxt->pres)[1] = 0; + + cxt->p_anchor = cxt->pres + 16; /* over the terminator */ +} + +/* add a reserver physical area to the rsvmap */ +void ft_add_rsvmap(struct ft_cxt *cxt, u64 physaddr, u64 size) +{ + ((u64 *) cxt->pres)[0] = cpu_to_be64(physaddr); /* phys = 0, size = 0, terminate */ + ((u64 *) cxt->pres)[1] = cpu_to_be64(size); + + cxt->pres += 16; /* advance */ + + ((u64 *) cxt->pres)[0] = 0; /* phys = 0, size = 0, terminate */ + ((u64 *) cxt->pres)[1] = 0; + + /* keep track of size */ + cxt->res_size = cxt->pres + 16 - cxt->pres_begin; + + cxt->p_anchor = cxt->pres + 16; /* over the terminator */ +} + +void ft_begin_tree(struct ft_cxt *cxt) +{ + cxt->p_begin = cxt->p_anchor; + cxt->pstr_begin = (char *)cxt->bph + cxt->max_size; /* point at the end */ + + cxt->p = cxt->p_begin; + cxt->pstr = cxt->pstr_begin; +} + +int ft_end_tree(struct ft_cxt *cxt) +{ + struct boot_param_header *bph = cxt->bph; + int off, sz, sz1; + u32 tag, v; + u8 *p; + + ft_put_word(cxt, OF_DT_END); + + if (cxt->overflow) + return -ENOMEM; + + /* size of the areas */ + cxt->struct_size = cxt->p - cxt->p_begin; + cxt->strings_size = cxt->pstr_begin - cxt->pstr; + + /* the offset we must move */ + off = (cxt->pstr_begin - cxt->p_begin) - cxt->strings_size; + + /* the new strings start */ + cxt->pstr_begin = cxt->p_begin + cxt->struct_size; + + /* move the whole string area */ + memmove(cxt->pstr_begin, cxt->pstr, cxt->strings_size); + + /* now perform the fixup of the strings */ + p = cxt->p_begin; + while ((tag = be32_to_cpu(*(u32 *) p)) != OF_DT_END) { + p += 4; + + if (tag == OF_DT_BEGIN_NODE) { + p = (u8 *) _ALIGN((unsigned long)p + strlen(p) + 1, 4); + continue; + } + + if (tag == OF_DT_END_NODE || tag == OF_DT_NOP) + continue; + + if (tag != OF_DT_PROP) + return -EINVAL; + + sz = be32_to_cpu(*(u32 *) p); + p += 4; + + v = be32_to_cpu(*(u32 *) p); + v -= off; + *(u32 *) p = cpu_to_be32(v); /* move down */ + p += 4; + + p = (u8 *) _ALIGN((unsigned long)p + sz, 4); + } + + /* fix sizes */ + p = (char *)cxt->bph; + sz = (cxt->pstr_begin + cxt->strings_size) - p; + sz1 = _ALIGN(sz, 16); /* align at 16 bytes */ + if (sz != sz1) + memset(p + sz, 0, sz1 - sz); + bph->totalsize = cpu_to_be32(sz1); + bph->off_dt_struct = cpu_to_be32(cxt->p_begin - p); + bph->off_dt_strings = cpu_to_be32(cxt->pstr_begin - p); + + /* the new strings start */ + cxt->pstr_begin = cxt->p_begin + cxt->struct_size; + cxt->pstr = cxt->pstr_begin + cxt->strings_size; + + return 0; +} + +/**********************************************************************/ + +static inline int isprint(int c) +{ + return c >= 0x20 && c <= 0x7e; +} + +static int is_printable_string(const void *data, int len) +{ + const char *s = data; + const char *ss; + + /* zero length is not */ + if (len == 0) + return 0; + + /* must terminate with zero */ + if (s[len - 1] != '\0') + return 0; + + ss = s; + while (*s && isprint(*s)) + s++; + + /* not zero, or not done yet */ + if (*s != '\0' || (s + 1 - ss) < len) + return 0; + + return 1; +} + +static void print_data(const void *data, int len) +{ + int i; + const u8 *s; + + /* no data, don't print */ + if (len == 0) + return; + + if (is_printable_string(data, len)) { + printf(" = \"%s\"", (char *)data); + return; + } + + switch (len) { + case 1: /* byte */ + printf(" = <0x%02x>", (*(u8 *) data) & 0xff); + break; + case 2: /* half-word */ + printf(" = <0x%04x>", be16_to_cpu(*(u16 *) data) & 0xffff); + break; + case 4: /* word */ + printf(" = <0x%08x>", be32_to_cpu(*(u32 *) data) & 0xffffffffU); + break; + case 8: /* double-word */ + printf(" = <0x%16llx>", be64_to_cpu(*(uint64_t *) data)); + break; + default: /* anything else... hexdump */ + printf(" = ["); + for (i = 0, s = data; i < len; i++) + printf("%02x%s", s[i], i < len - 1 ? " " : ""); + printf("]"); + + break; + } +} + +void ft_dump_blob(const void *bphp) +{ + const struct boot_param_header *bph = bphp; + const uint64_t *p_rsvmap = (const uint64_t *) + ((const char *)bph + be32_to_cpu(bph->off_mem_rsvmap)); + const u32 *p_struct = (const u32 *) + ((const char *)bph + be32_to_cpu(bph->off_dt_struct)); + const u32 *p_strings = (const u32 *) + ((const char *)bph + be32_to_cpu(bph->off_dt_strings)); + u32 tag; + const u32 *p; + const char *s, *t; + int depth, sz, shift; + int i; + uint64_t addr, size; + + if (be32_to_cpu(bph->magic) != OF_DT_HEADER) { + /* not valid tree */ + return; + } + + depth = 0; + shift = 4; + + for (i = 0;; i++) { + addr = be64_to_cpu(p_rsvmap[i * 2]); + size = be64_to_cpu(p_rsvmap[i * 2 + 1]); + if (addr == 0 && size == 0) + break; + + printf("/memreserve/ 0x%llx 0x%llx;\n", addr, size); + } + + p = p_struct; + while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { + + /* printf("tag: 0x%08x (%d)\n", tag, p - p_struct); */ + + if (tag == OF_DT_BEGIN_NODE) { + s = (const char *)p; + p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4); + + printf("%*s%s {\n", depth * shift, "", s); + + depth++; + continue; + } + + if (tag == OF_DT_END_NODE) { + depth--; + + printf("%*s};\n", depth * shift, ""); + continue; + } + + if (tag == OF_DT_NOP) { + printf("%*s[NOP]\n", depth * shift, ""); + continue; + } + + if (tag != OF_DT_PROP) { + fprintf(stderr, "%*s ** Unknown tag 0x%08x\n", + depth * shift, "", tag); + break; + } + sz = be32_to_cpu(*p++); + s = (const char *)p_strings + be32_to_cpu(*p++); + t = (const char *)p; + p = (const u32 *)_ALIGN((unsigned long)p + sz, 4); + printf("%*s%s", depth * shift, "", s); + print_data(t, sz); + printf(";\n"); + } +} + +void ft_backtrack_node(struct ft_cxt *cxt) +{ + if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE) + return; /* XXX only for node */ + + cxt->p -= 4; +} + +/* note that the root node of the blob is "peeled" off */ +void ft_merge_blob(struct ft_cxt *cxt, void *blob) +{ + struct boot_param_header *bph = (struct boot_param_header *)blob; + u32 *p_struct = (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_struct)); + u32 *p_strings = + (u32 *) ((char *)bph + be32_to_cpu(bph->off_dt_strings)); + u32 tag, *p; + char *s, *t; + int depth, sz; + + if (be32_to_cpu(*(u32 *) (cxt->p - 4)) != OF_DT_END_NODE) + return; /* XXX only for node */ + + cxt->p -= 4; + + depth = 0; + p = p_struct; + while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { + + /* printf("tag: 0x%08x (%d) - %d\n", tag, p - p_struct, depth); */ + + if (tag == OF_DT_BEGIN_NODE) { + s = (char *)p; + p = (u32 *) _ALIGN((unsigned long)p + strlen(s) + 1, 4); + + if (depth++ > 0) + ft_begin_node(cxt, s); + + continue; + } + + if (tag == OF_DT_END_NODE) { + ft_end_node(cxt); + if (--depth == 0) + break; + continue; + } + + if (tag == OF_DT_NOP) + continue; + + if (tag != OF_DT_PROP) + break; + + sz = be32_to_cpu(*p++); + s = (char *)p_strings + be32_to_cpu(*p++); + t = (char *)p; + p = (u32 *) _ALIGN((unsigned long)p + sz, 4); + + ft_prop(cxt, s, t, sz); + } +} + +void *ft_get_prop(void *bphp, const char *propname, int *szp) +{ + struct boot_param_header *bph = bphp; + uint32_t *p_struct = + (uint32_t *) ((char *)bph + be32_to_cpu(bph->off_dt_struct)); + uint32_t *p_strings = + (uint32_t *) ((char *)bph + be32_to_cpu(bph->off_dt_strings)); + uint32_t version = be32_to_cpu(bph->version); + uint32_t tag; + uint32_t *p; + char *s, *t; + char *ss; + int sz; + static char path[256], prop[256]; + + path[0] = '\0'; + + p = p_struct; + while ((tag = be32_to_cpu(*p++)) != OF_DT_END) { + + if (tag == OF_DT_BEGIN_NODE) { + s = (char *)p; + p = (uint32_t *) _ALIGN((unsigned long)p + strlen(s) + + 1, 4); + strcat(path, s); + strcat(path, "/"); + continue; + } + + if (tag == OF_DT_END_NODE) { + path[strlen(path) - 1] = '\0'; + ss = strrchr(path, '/'); + if (ss != NULL) + ss[1] = '\0'; + continue; + } + + if (tag == OF_DT_NOP) + continue; + + if (tag != OF_DT_PROP) + break; + + sz = be32_to_cpu(*p++); + s = (char *)p_strings + be32_to_cpu(*p++); + if (version < 0x10 && sz >= 8) + p = (uint32_t *) _ALIGN((unsigned long)p, 8); + t = (char *)p; + p = (uint32_t *) _ALIGN((unsigned long)p + sz, 4); + + strcpy(prop, path); + strcat(prop, s); + + if (strcmp(prop, propname) == 0) { + *szp = sz; + return t; + } + } + + return NULL; +} + +/********************************************************************/ + +extern unsigned char oftree_dtb[]; +extern unsigned int oftree_dtb_len; + +/* Function that returns a character from the environment */ +extern uchar(*env_get_char) (int); + +#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) } + +#ifdef CONFIG_OF_HAS_BD_T +static const struct { + const char *name; + int offset; +} bd_map[] = { + BDM(memstart), + BDM(memsize), + BDM(flashstart), + BDM(flashsize), + BDM(flashoffset), + BDM(sramstart), + BDM(sramsize), +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ + || defined(CONFIG_E500) + BDM(immr_base), +#endif +#if defined(CONFIG_MPC5xxx) + BDM(mbar_base), +#endif +#if defined(CONFIG_MPC83XX) + BDM(immrbar), +#endif +#if defined(CONFIG_MPC8220) + BDM(mbar_base), + BDM(inpfreq), + BDM(pcifreq), + BDM(pevfreq), + BDM(flbfreq), + BDM(vcofreq), +#endif + BDM(bootflags), + BDM(ip_addr), + BDM(intfreq), + BDM(busfreq), +#ifdef CONFIG_CPM2 + BDM(cpmfreq), + BDM(brgfreq), + BDM(sccfreq), + BDM(vco), +#endif +#if defined(CONFIG_MPC5xxx) + BDM(ipbfreq), + BDM(pcifreq), +#endif + BDM(baudrate), +}; +#endif + +void ft_setup(void *blob, int size, bd_t * bd, ulong initrd_start, ulong initrd_end) +{ + u32 *p; + int len; + struct ft_cxt cxt; + ulong clock; +#if defined(CONFIG_OF_HAS_UBOOT_ENV) + int k, nxt; +#endif +#if defined(CONFIG_OF_HAS_BD_T) + u8 *end; +#endif +#if defined(CONFIG_OF_HAS_UBOOT_ENV) || defined(CONFIG_OF_HAS_BD_T) + int i; + static char tmpenv[256]; +#endif + + /* disable OF tree; booting old kernel */ + if (getenv("disable_of") != NULL) { + memcpy(blob, bd, sizeof(*bd)); + return; + } + + ft_begin(&cxt, blob, size); + + if (initrd_start && initrd_end) + ft_add_rsvmap(&cxt, initrd_start, initrd_end - initrd_start + 1); + + ft_begin_tree(&cxt); + + ft_begin_node(&cxt, ""); + + ft_end_node(&cxt); + + /* copy RO tree */ + ft_merge_blob(&cxt, oftree_dtb); + + /* back into root */ + ft_backtrack_node(&cxt); + +#ifdef CONFIG_OF_HAS_UBOOT_ENV + ft_begin_node(&cxt, "u-boot-env"); + + for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) { + char *s, *lval, *rval; + + for (nxt = i; env_get_char(nxt) != '\0'; ++nxt) ; + s = tmpenv; + for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k) + *s++ = env_get_char(k); + *s++ = '\0'; + lval = tmpenv; + s = strchr(tmpenv, '='); + if (s != NULL) { + *s++ = '\0'; + rval = s; + } else + continue; + ft_prop_str(&cxt, lval, rval); + } + + ft_end_node(&cxt); +#endif + + ft_begin_node(&cxt, "chosen"); + + ft_prop_str(&cxt, "name", "chosen"); + ft_prop_str(&cxt, "bootargs", getenv("bootargs")); + ft_prop_int(&cxt, "linux,platform", 0x600); /* what is this? */ + if (initrd_start && initrd_end) { + ft_prop_int(&cxt, "linux,initrd-start", initrd_start); + ft_prop_int(&cxt, "linux,initrd-end", initrd_end); + } +#ifdef OF_STDOUT_PATH + ft_prop_str(&cxt, "linux,stdout-path", OF_STDOUT_PATH); +#endif + + ft_end_node(&cxt); + + ft_end_node(&cxt); /* end root */ + + ft_end_tree(&cxt); + + /* + printf("merged OF-tree\n"); + ft_dump_blob(blob); + */ + +#ifdef CONFIG_OF_HAS_BD_T + /* paste the bd_t at the end of the flat tree */ + end = (char *)blob + + be32_to_cpu(((struct boot_param_header *)blob)->totalsize); + memcpy(end, bd, sizeof(*bd)); +#endif + +#ifdef CONFIG_PPC + +#ifdef CONFIG_OF_HAS_BD_T + for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) { + uint32_t v; + + sprintf(tmpenv, "/bd_t/%s", bd_map[i].name); + v = *(uint32_t *)((char *)bd + bd_map[i].offset); + + p = ft_get_prop(blob, tmpenv, &len); + if (p != NULL) + *p = cpu_to_be32(v); + } + + p = ft_get_prop(blob, "/bd_t/enetaddr", &len); + if (p != NULL) + memcpy(p, bd->bi_enetaddr, 6); + + p = ft_get_prop(blob, "/bd_t/ethspeed", &len); + if (p != NULL) + *p = cpu_to_be32((uint32_t) bd->bi_ethspeed); +#endif + + clock = bd->bi_intfreq; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + +#ifdef OF_TBCLK + clock = OF_TBCLK; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/timebase-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); +#endif +#endif /* __powerpc__ */ + +#ifdef CONFIG_OF_BOARD_SETUP + ft_board_setup(blob, bd); +#endif + + /* + printf("final OF-tree\n"); + ft_dump_blob(blob); + */ + +} + +#endif diff --git a/common/hush.c b/common/hush.c index 75c18ce8a..feb5627ff 100644 --- a/common/hush.c +++ b/common/hush.c @@ -1,3 +1,4 @@ +/* vi: set sw=4 ts=4: */ /* * sh.c -- a prototype Bourne shell grammar parser * Intended to follow the original Thompson and Ritchie @@ -953,7 +954,7 @@ static int b_adduint(o_string *o, unsigned int i) static int static_get(struct in_str *i) { - int ch = *i->p++; + int ch=*i->p++; if (ch=='\0') return EOF; return ch; } @@ -1104,7 +1105,7 @@ static int file_get(struct in_str *i) ch = 0; /* If there is data waiting, eat it up */ if (i->p && *i->p) { - ch = *i->p++; + ch=*i->p++; } else { /* need to double check i->file because we might be doing something * more complicated by now, like sourcing or substituting. */ @@ -1121,7 +1122,7 @@ static int file_get(struct in_str *i) i->__promptme = 0; #endif if (i->p && *i->p) { - ch = *i->p++; + ch=*i->p++; } #ifndef __U_BOOT__ } else { @@ -1681,7 +1682,7 @@ static int run_pipe_real(struct pipe *pi) return -1; /* give up after bad command */ } else { int rcode; -#if defined(CONFIG_CMD_BOOTD) +#if (CONFIG_COMMANDS & CFG_CMD_BOOTD) extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* avoid "bootd" recursion */ @@ -1693,7 +1694,7 @@ static int run_pipe_real(struct pipe *pi) else flag |= CMD_FLAG_BOOTD; } -#endif +#endif /* CFG_CMD_BOOTD */ /* found - check max args */ if ((child->argc - i) > cmdtp->maxargs) { printf ("Usage:\n%s\n", cmdtp->usage); diff --git a/common/kgdb.c b/common/kgdb.c index b14898be9..6de6ec99a 100644 --- a/common/kgdb.c +++ b/common/kgdb.c @@ -92,7 +92,7 @@ #include #include -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef KGDB_DEBUG @@ -107,7 +107,7 @@ static char remcomRegBuffer[BUFMAX]; static int initialized = 0; static int kgdb_active = 0, first_entry = 1; static struct pt_regs entry_regs; -static long error_jmp_buf[BUFMAX/2]; +static u_int error_jmp_buf[BUFMAX/2]; static int longjmp_on_fault = 0; #ifdef KGDB_DEBUG static int kdebug = 1; @@ -310,7 +310,7 @@ handle_exception (struct pt_regs *regs) /* probably should check which exception occured as well */ if (longjmp_on_fault) { longjmp_on_fault = 0; - kgdb_longjmp(error_jmp_buf, KGDBERR_MEMFAULT); + kgdb_longjmp((long*)error_jmp_buf, KGDBERR_MEMFAULT); panic("kgdb longjump failed!\n"); } @@ -324,7 +324,7 @@ handle_exception (struct pt_regs *regs) printf("kgdb: handle_exception; trap [0x%x]\n", kgdb_trap(regs)); - if (kgdb_setjmp(error_jmp_buf) != 0) + if (kgdb_setjmp((long*)error_jmp_buf) != 0) panic("kgdb: error or fault in entry init!\n"); kgdb_enter(regs, &kd); @@ -379,7 +379,7 @@ handle_exception (struct pt_regs *regs) printf("kgdb: remcomInBuffer: %s\n", remcomInBuffer); #endif - errnum = kgdb_setjmp(error_jmp_buf); + errnum = kgdb_setjmp((long*)error_jmp_buf); if (errnum == 0) switch (remcomInBuffer[0]) { @@ -532,7 +532,7 @@ void kgdb_error(int errnum) { longjmp_on_fault = 0; - kgdb_longjmp(error_jmp_buf, errnum); + kgdb_longjmp((long*)error_jmp_buf, errnum); panic("kgdb_error: longjmp failed!\n"); } @@ -591,4 +591,4 @@ U_BOOT_CMD( int kgdb_not_configured = 1; -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/common/lcd.c b/common/lcd.c index 8d770f3e7..0be1912a3 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -50,11 +50,6 @@ #include #endif -#if defined(CONFIG_ATMEL_LCD) -#include -#include -#endif - #ifdef CONFIG_LCD /************************************************************************/ @@ -479,22 +474,14 @@ ulong lcd_setmem (ulong addr) static void lcd_setfgcolor (int color) { -#ifdef CONFIG_ATMEL_LCD - lcd_color_fg = color; -#else lcd_color_fg = color & 0x0F; -#endif } /*----------------------------------------------------------------------*/ static void lcd_setbgcolor (int color) { -#ifdef CONFIG_ATMEL_LCD - lcd_color_bg = color; -#else lcd_color_bg = color & 0x0F; -#endif } /*----------------------------------------------------------------------*/ @@ -521,11 +508,7 @@ static int lcd_getbgcolor (void) #ifdef CONFIG_LCD_LOGO void bitmap_plot (int x, int y) { -#ifdef CONFIG_ATMEL_LCD - uint *cmap; -#else ushort *cmap; -#endif ushort i, j; uchar *bmap; uchar *fb; @@ -539,7 +522,7 @@ void bitmap_plot (int x, int y) debug ("Logo: width %d height %d colors %d cmap %d\n", BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS, - (int)(sizeof(bmp_logo_palette)/(sizeof(ushort)))); + sizeof(bmp_logo_palette)/(sizeof(ushort))); bmap = &bmp_logo_bitmap[0]; fb = (uchar *)(lcd_base + y * lcd_line_length + x); @@ -550,8 +533,6 @@ void bitmap_plot (int x, int y) cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]); -#elif defined(CONFIG_ATMEL_LCD) - cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0)); #endif WATCHDOG_RESET(); @@ -559,26 +540,11 @@ void bitmap_plot (int x, int y) /* Set color map */ for (i=0; i<(sizeof(bmp_logo_palette)/(sizeof(ushort))); ++i) { ushort colreg = bmp_logo_palette[i]; -#ifdef CONFIG_ATMEL_LCD - uint lut_entry; -#ifdef CONFIG_ATMEL_LCD_BGR555 - lut_entry = ((colreg & 0x000F) << 11) | - ((colreg & 0x00F0) << 2) | - ((colreg & 0x0F00) >> 7); -#else /* CONFIG_ATMEL_LCD_RGB565 */ - lut_entry = ((colreg & 0x000F) << 1) | - ((colreg & 0x00F0) << 3) | - ((colreg & 0x0F00) << 4); -#endif - *(cmap + BMP_LOGO_OFFSET) = lut_entry; - cmap++; -#else /* !CONFIG_ATMEL_LCD */ #ifdef CFG_INVERT_COLORS *cmap++ = 0xffff - colreg; #else *cmap++ = colreg; #endif -#endif /* CONFIG_ATMEL_LCD */ } WATCHDOG_RESET(); @@ -605,25 +571,20 @@ void bitmap_plot (int x, int y) #endif /* CONFIG_LCD_LOGO */ /*----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) /* * Display the BMP file located at address bmp_image. * Only uncompressed. */ int lcd_display_bitmap(ulong bmp_image, int x, int y) { -#ifdef CONFIG_ATMEL_LCD - uint *cmap; -#elif !defined(CONFIG_MCC200) ushort *cmap; -#endif ushort i, j; uchar *fb; bmp_image_t *bmp=(bmp_image_t *)bmp_image; uchar *bmap; ushort padded_line; unsigned long width, height; - unsigned long pwidth = panel_info.vl_col; unsigned colors,bpix; unsigned long compression; #if defined(CONFIG_PXA250) @@ -662,15 +623,11 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) debug ("Display-bmp: %d x %d with %d colors\n", (int)width, (int)height, (int)colors); -#if !defined(CONFIG_MCC200) - /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ if (bpix==8) { #if defined(CONFIG_PXA250) cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); -#elif defined(CONFIG_ATMEL_LCD) - cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0)); #else # error "Don't know location of color map" #endif @@ -678,7 +635,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) /* Set color map */ for (i=0; icolor_table[i]; -#if !defined(CONFIG_ATMEL_LCD) ushort colreg = ( ((cte.red) << 8) & 0xf800) | ( ((cte.green) << 3) & 0x07e0) | @@ -692,36 +648,13 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) cmap++; #elif defined(CONFIG_MPC823) cmap--; -#endif -#else /* CONFIG_ATMEL_LCD */ - lcd_setcolreg(i, cte.red, cte.green, cte.blue); #endif } } -#endif - - /* - * BMP format for Monochrome assumes that the state of a - * pixel is described on a per Bit basis, not per Byte. - * So, in case of Monochrome BMP we should align widths - * on a byte boundary and convert them from Bit to Byte - * units. - * Probably, PXA250 and MPC823 process 1bpp BMP images in - * their own ways, so make the converting to be MCC200 - * specific. - */ -#if defined(CONFIG_MCC200) - if (bpix==1) - { - width = ((width + 7) & ~7) >> 3; - x = ((x + 7) & ~7) >> 3; - pwidth= ((pwidth + 7) & ~7) >> 3; - } -#endif padded_line = (width&0x3) ? ((width&~0x3)+4) : (width); - if ((x + width)>pwidth) - width = pwidth - x; + if ((x + width)>panel_info.vl_col) + width = panel_info.vl_col - x; if ((y + height)>panel_info.vl_row) height = panel_info.vl_row - y; @@ -731,9 +664,9 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) for (i = 0; i < height; ++i) { WATCHDOG_RESET(); for (j = 0; j < width ; j++) -#if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD) - *(fb++) = *(bmap++); -#elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200) +#if defined(CONFIG_PXA250) + *(fb++)=*(bmap++); +#elif defined(CONFIG_MPC823) *(fb++)=255-*(bmap++); #endif bmap += (width - padded_line); @@ -742,21 +675,14 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) return (0); } -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ -#ifdef CONFIG_VIDEO_BMP_GZIP -extern bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp); -#endif static void *lcd_logo (void) { #ifdef CONFIG_LCD_INFO char info[80]; char temp[32]; -#ifdef CONFIG_ATMEL_LCD - int i; - ulong dram_size, nand_size; -#endif #endif /* CONFIG_LCD_INFO */ #ifdef CONFIG_SPLASH_SCREEN @@ -768,16 +694,6 @@ static void *lcd_logo (void) addr = simple_strtoul(s, NULL, 16); do_splash = 0; -#ifdef CONFIG_VIDEO_BMP_GZIP - bmp_image_t *bmp = (bmp_image_t *)addr; - unsigned long len; - - if (!((bmp->header.signature[0]=='B') && - (bmp->header.signature[1]=='M'))) { - addr = (ulong)gunzip_bmp(addr, &len); - } -#endif - if (lcd_display_bitmap (addr, 0, 0) == 0) { return ((void *)lcd_base); } @@ -793,7 +709,7 @@ static void *lcd_logo (void) sprintf (info, "%s (%s - %s) ", U_BOOT_VERSION, __DATE__, __TIME__); lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info)); - sprintf (info, "(C) 2008 DENX Software Engineering GmbH"); + sprintf (info, "(C) 2004 DENX Software Engineering"); lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT, (uchar *)info, strlen(info)); @@ -824,40 +740,6 @@ static void *lcd_logo (void) # endif /* CONFIG_LCD_INFO */ #endif /* CONFIG_MPC823 */ -#ifdef CONFIG_ATMEL_LCD -# ifdef CONFIG_LCD_INFO - sprintf (info, "%s", U_BOOT_VERSION); - lcd_drawchars (LCD_INFO_X, LCD_INFO_Y, (uchar *)info, strlen(info)); - - sprintf (info, "(C) 2008 ATMEL Corp"); - lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT, - (uchar *)info, strlen(info)); - - sprintf (info, "at91support@atmel.com"); - lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 2, - (uchar *)info, strlen(info)); - - sprintf (info, "%s CPU at %s MHz", - AT91_CPU_NAME, - strmhz(temp, AT91_MAIN_CLOCK)); - lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 3, - (uchar *)info, strlen(info)); - - dram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; - nand_size = 0; - for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; - sprintf (info, " %ld MB SDRAM, %ld MB NAND", - dram_size >> 20, - nand_size >> 20 ); - lcd_drawchars (LCD_INFO_X, LCD_INFO_Y + VIDEO_FONT_HEIGHT * 4, - (uchar *)info, strlen(info)); -# endif /* CONFIG_LCD_INFO */ -#endif /* CONFIG_ATMEL_LCD */ - - #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length)); #else diff --git a/common/lists.c b/common/lists.c index 0dc090ab8..3f117b568 100644 --- a/common/lists.c +++ b/common/lists.c @@ -2,8 +2,8 @@ #include #include -#define MAX(a,b) (((a)>(b)) ? (a) : (b)) -#define MIN(a,b) (((a)<(b)) ? (a) : (b)) +#define MAX(a,b) (((a)>(b)) ? (a) : (b)) +#define MIN(a,b) (((a)<(b)) ? (a) : (b)) #define CAT4CHARS(a,b,c,d) ((a<<24) | (b<<16) | (c<<8) | d) /* increase list size by 10% every time it is full */ diff --git a/common/lynxkdi.c b/common/lynxkdi.c index a5dc88769..76a271b96 100644 --- a/common/lynxkdi.c +++ b/common/lynxkdi.c @@ -23,45 +23,45 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_MPC8260) || defined(CONFIG_440EP) || defined(CONFIG_440GR) -void lynxkdi_boot (image_header_t *hdr) +void lynxkdi_boot ( image_header_t *hdr ) { - void (*lynxkdi)(void) = (void(*)(void))image_get_ep (hdr); + void (*lynxkdi)(void) = (void(*)(void)) ntohl(hdr->ih_ep); lynxos_bootparms_t *parms = (lynxos_bootparms_t *)0x0020; bd_t *kbd; - u32 *psz = (u32 *)(image_get_load (hdr) + 0x0204); + u32 *psz = (u32 *)(ntohl(hdr->ih_load) + 0x0204); - memset (parms, 0, sizeof(*parms)); + memset( parms, 0, sizeof(*parms)); kbd = gd->bd; parms->clock_ref = kbd->bi_busfreq; parms->dramsz = kbd->bi_memsize; - memcpy (parms->ethaddr, kbd->bi_enetaddr, 6); - mtspr (SPRN_SPRG2, 0x0020); + memcpy(parms->ethaddr, kbd->bi_enetaddr, 6); + mtspr(SPRN_SPRG2, 0x0020); /* Do a simple check for Bluecat so we can pass the * kernel command line parameters. */ - if (le32_to_cpu (*psz) == image_get_data_size (hdr)) { /* FIXME: NOT SURE HERE ! */ - char *args; - char *cmdline = (char *)(image_get_load (hdr) + 0x020c); - int len; + if( le32_to_cpu(*psz) == ntohl(hdr->ih_size) ){ /* FIXME: NOT SURE HERE ! */ + char *args; + char *cmdline = (char *)(ntohl(hdr->ih_load) + 0x020c); + int len; - printf ("Booting Bluecat KDI ...\n"); - udelay (200*1000); /* Allow serial port to flush */ - if ((args = getenv ("bootargs")) == NULL) - args = ""; - /* Prepend the cmdline */ - len = strlen (args); - if (len && (len + strlen (cmdline) + 2 < (0x0400 - 0x020c))) { - memmove (cmdline + strlen (args) + 1, cmdline, strlen (cmdline)); - strcpy (cmdline, args); - cmdline[len] = ' '; - } + printf("Booting Bluecat KDI ...\n"); + udelay(200*1000); /* Allow serial port to flush */ + if ((args = getenv("bootargs")) == NULL) + args = ""; + /* Prepend the cmdline */ + len = strlen(args); + if( len && (len + strlen(cmdline) + 2 < (0x0400 - 0x020c))) { + memmove( cmdline + strlen(args) + 1, cmdline, strlen(cmdline) ); + strcpy( cmdline, args ); + cmdline[len] = ' '; + } } else { - printf ("Booting LynxOS KDI ...\n"); + printf("Booting LynxOS KDI ...\n"); } - lynxkdi (); + lynxkdi(); } #else #error "Lynx KDI support not implemented for configured CPU" diff --git a/common/main.c b/common/main.c index 187ef8a3a..3b07a0a12 100644 --- a/common/main.c +++ b/common/main.c @@ -38,18 +38,13 @@ #include #endif +#include #include -#if defined(CONFIG_SILENT_CONSOLE) || defined(CONFIG_POST) || defined(CONFIG_CMDLINE_EDITING) +#ifdef CONFIG_SILENT_CONSOLE DECLARE_GLOBAL_DATA_PTR; #endif -/* - * Board-specific Platform code can reimplement show_boot_progress () if needed - */ -void inline __show_boot_progress (int val) {} -void inline show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); - #if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY) extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* for do_reset() prototype */ #endif @@ -59,6 +54,7 @@ extern int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #define MAX_DELAY_STOP_STR 32 +static int parse_line (char *, char *[]); #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) static int abortboot(int); #endif @@ -67,9 +63,11 @@ static int abortboot(int); char console_buffer[CFG_CBSIZE]; /* console I/O buffer */ +#ifndef CONFIG_CMDLINE_EDITING static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen); static char erase_seq[] = "\b \b"; /* erase sequence */ static char tab_seq[] = " "; /* used to expand TABs */ +#endif /* CONFIG_CMDLINE_EDITING */ #ifdef CONFIG_BOOT_RETRY_TIME static uint64_t endtime = 0; /* must be set, default is instant timeout */ @@ -98,12 +96,14 @@ static __inline__ int abortboot(int bootdelay) { int abort = 0; uint64_t etime = endtick(bootdelay); - struct { + struct + { char* str; u_int len; int retry; } - delaykey [] = { + delaykey [] = + { { str: getenv ("bootdelaykey"), retry: 1 }, { str: getenv ("bootdelaykey2"), retry: 1 }, { str: getenv ("bootstopkey"), retry: 0 }, @@ -115,8 +115,16 @@ static __inline__ int abortboot(int bootdelay) u_int presskey_max = 0; u_int i; +#ifdef CONFIG_SILENT_CONSOLE + if (gd->flags & GD_FLG_SILENT) { + /* Restore serial console */ + console_assign (stdout, "serial"); + console_assign (stderr, "serial"); + } +#endif + # ifdef CONFIG_AUTOBOOT_PROMPT - printf(CONFIG_AUTOBOOT_PROMPT); + printf (CONFIG_AUTOBOOT_PROMPT, bootdelay); # endif # ifdef CONFIG_AUTOBOOT_DELAY_STR @@ -190,12 +198,18 @@ static __inline__ int abortboot(int bootdelay) } # if DEBUG_BOOTKEYS if (!abort) - puts("key timeout\n"); + puts ("key timeout\n"); # endif #ifdef CONFIG_SILENT_CONSOLE - if (abort) - gd->flags &= ~GD_FLG_SILENT; + if (abort) { + /* permanently enable normal console output */ + gd->flags &= ~(GD_FLG_SILENT); + } else if (gd->flags & GD_FLG_SILENT) { + /* Restore silent console */ + console_assign (stdout, "nulldev"); + console_assign (stderr, "nulldev"); + } #endif return abort; @@ -211,8 +225,16 @@ static __inline__ int abortboot(int bootdelay) { int abort = 0; +#ifdef CONFIG_SILENT_CONSOLE + if (gd->flags & GD_FLG_SILENT) { + /* Restore serial console */ + console_assign (stdout, "serial"); + console_assign (stderr, "serial"); + } +#endif + #ifdef CONFIG_MENUPROMPT - printf(CONFIG_MENUPROMPT); + printf(CONFIG_MENUPROMPT, bootdelay); #else printf("Hit any key to stop autoboot: %2d ", bootdelay); #endif @@ -226,7 +248,7 @@ static __inline__ int abortboot(int bootdelay) if (tstc()) { /* we got a key press */ (void) getc(); /* consume input */ puts ("\b\b\b 0"); - abort = 1; /* don't auto boot */ + abort = 1; /* don't auto boot */ } } #endif @@ -247,17 +269,23 @@ static __inline__ int abortboot(int bootdelay) # endif break; } - udelay(10000); + udelay (10000); } - printf("\b\b\b%2d ", bootdelay); + printf ("\b\b\b%2d ", bootdelay); } - putc('\n'); + putc ('\n'); #ifdef CONFIG_SILENT_CONSOLE - if (abort) - gd->flags &= ~GD_FLG_SILENT; + if (abort) { + /* permanently enable normal console output */ + gd->flags &= ~(GD_FLG_SILENT); + } else if (gd->flags & GD_FLG_SILENT) { + /* Restore silent console */ + console_assign (stdout, "nulldev"); + console_assign (stderr, "nulldev"); + } #endif return abort; @@ -277,7 +305,7 @@ void main_loop (void) #endif #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) - char *s; + char *s, *r; int bootdelay; #endif #ifdef CONFIG_PREBOOT @@ -337,7 +365,12 @@ void main_loop (void) #ifdef CONFIG_AUTO_COMPLETE install_auto_complete(); #endif +/* Disabling the check of 'OK' key press to reduce the boot time. */ +#if 0 + if (fastboot_preboot()) + run_command("fastboot", 0); +#endif #ifdef CONFIG_PREBOOT if ((p = getenv ("preboot")) != NULL) { # ifdef CONFIG_AUTOBOOT_KEYED @@ -367,19 +400,17 @@ void main_loop (void) init_cmd_timeout (); # endif /* CONFIG_BOOT_RETRY_TIME */ -#ifdef CONFIG_POST - if (gd->flags & GD_FLG_POSTFAIL) { - s = getenv("failbootcmd"); - } - else -#endif /* CONFIG_POST */ #ifdef CONFIG_BOOTCOUNT_LIMIT - if (bootlimit && (bootcount > bootlimit)) { + if (bootlimit && (bootcount > bootlimit+1)) { + hang(); + } else if (bootlimit && (bootcount > bootlimit)) { printf ("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n", (unsigned)bootlimit); s = getenv ("altbootcmd"); - } - else + } else if ((r = getenv("force_altboot")) != NULL && r[0] == 'y') { + printf ("force_altboot set, using altbootcmd.\n"); + s = getenv ("altbootcmd"); + } else #endif /* CONFIG_BOOTCOUNT_LIMIT */ s = getenv ("bootcmd"); @@ -477,7 +508,7 @@ void main_loop (void) #ifdef CONFIG_BOOT_RETRY_TIME /*************************************************************************** - * initialize command line timeout + * initialise command line timeout */ void init_cmd_timeout(void) { @@ -508,9 +539,23 @@ void reset_cmd_timeout(void) * Author: Janghoon Lyu */ +#if 1 /* avoid redundand code -- wd */ #define putnstr(str,n) do { \ - printf ("%.*s", (int)n, str); \ + printf ("%.*s", n, str); \ } while (0) +#else +void putnstr(const char *str, size_t n) +{ + if (str == NULL) + return; + + while (n && *str != '\0') { + putc(*str); + str++; + n--; + } +} +#endif #define CTL_CH(c) ((c) - 'a' + 1) @@ -699,7 +744,7 @@ static void cread_add_str(char *str, int strsize, int insert, unsigned long *num } } -static int cread_line(const char *const prompt, char *buf, unsigned int *len) +static int cread_line(char *buf, unsigned int *len) { unsigned long num = 0; unsigned long eol_num = 0; @@ -713,13 +758,6 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len) while (1) { rlen = 1; -#ifdef CONFIG_BOOT_RETRY_TIME - while (!tstc()) { /* while no incoming data */ - if (retry_time >= 0 && get_ticks() > endtime) - return (-2); /* timed out */ - } -#endif - ichar = getcmd_getch(); if ((ichar == '\n') || (ichar == '\r')) { @@ -828,7 +866,6 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len) insert = !insert; break; case CTL_CH('x'): - case CTL_CH('u'): BEGINNING_OF_LINE(); ERASE_TO_EOL(); break; @@ -878,27 +915,6 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len) REFRESH_TO_EOL(); continue; } -#ifdef CONFIG_AUTO_COMPLETE - case '\t': { - int num2, col; - - /* do not autocomplete when in the middle */ - if (num < eol_num) { - getcmd_cbeep(); - break; - } - - buf[num] = '\0'; - col = strlen(prompt) + eol_num; - num2 = num; - if (cmd_auto_complete(prompt, buf, &num2, &col)) { - col = num2 - num; - num += col; - eol_num += col; - } - break; - } -#endif default: cread_add_char(ichar, insert, &num, &eol_num, buf, *len); break; @@ -928,38 +944,22 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len) */ int readline (const char *const prompt) { - return readline_into_buffer(prompt, console_buffer); -} - - -int readline_into_buffer (const char *const prompt, char * buffer) -{ - char *p = buffer; #ifdef CONFIG_CMDLINE_EDITING + char *p = console_buffer; unsigned int len=MAX_CMDBUF_SIZE; - int rc; static int initted = 0; - /* - * History uses a global array which is not - * writable until after relocation to RAM. - * Revert to non-history version if still - * running from flash. - */ - if (gd->flags & GD_FLG_RELOC) { - if (!initted) { - hist_init(); - initted = 1; - } + if (!initted) { + hist_init(); + initted = 1; + } - puts (prompt); + puts (prompt); - rc = cread_line(prompt, p, &len); - return rc < 0 ? rc : len; - - } else { -#endif /* CONFIG_CMDLINE_EDITING */ - char * p_buf = p; + cread_line(p, &len); + return len; +#else + char *p = console_buffer; int n = 0; /* buffer index */ int plen = 0; /* prompt length */ int col; /* output column cnt */ @@ -997,13 +997,13 @@ int readline_into_buffer (const char *const prompt, char * buffer) case '\n': *p = '\0'; puts ("\r\n"); - return (p - p_buf); + return (p - console_buffer); case '\0': /* nul */ continue; case 0x03: /* ^C - break */ - p_buf[0] = '\0'; /* discard input */ + console_buffer[0] = '\0'; /* discard input */ return (-1); case 0x15: /* ^U - erase line */ @@ -1011,20 +1011,20 @@ int readline_into_buffer (const char *const prompt, char * buffer) puts (erase_seq); --col; } - p = p_buf; + p = console_buffer; n = 0; continue; - case 0x17: /* ^W - erase word */ - p=delete_char(p_buf, p, &col, &n, plen); + case 0x17: /* ^W - erase word */ + p=delete_char(console_buffer, p, &col, &n, plen); while ((n > 0) && (*p != ' ')) { - p=delete_char(p_buf, p, &col, &n, plen); + p=delete_char(console_buffer, p, &col, &n, plen); } continue; case 0x08: /* ^H - backspace */ case 0x7F: /* DEL - backspace */ - p=delete_char(p_buf, p, &col, &n, plen); + p=delete_char(console_buffer, p, &col, &n, plen); continue; default: @@ -1037,7 +1037,7 @@ int readline_into_buffer (const char *const prompt, char * buffer) /* if auto completion triggered just continue */ *p = '\0'; if (cmd_auto_complete(prompt, console_buffer, &n, &col)) { - p = p_buf + n; /* reset */ + p = console_buffer + n; /* reset */ continue; } #endif @@ -1054,13 +1054,12 @@ int readline_into_buffer (const char *const prompt, char * buffer) } } } -#ifdef CONFIG_CMDLINE_EDITING - } -#endif +#endif /* CONFIG_CMDLINE_EDITING */ } /****************************************************************************/ +#ifndef CONFIG_CMDLINE_EDITING static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen) { char *s; @@ -1090,6 +1089,7 @@ static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen) (*np)--; return (p); } +#endif /* CONFIG_CMDLINE_EDITING */ /****************************************************************************/ @@ -1147,109 +1147,105 @@ static void process_macros (const char *input, char *output) { char c, prev; const char *varname_start = NULL; - int inputcnt = strlen (input); + int inputcnt = strlen (input); int outputcnt = CFG_CBSIZE; - int state = 0; /* 0 = waiting for '$' */ - - /* 1 = waiting for '(' or '{' */ - /* 2 = waiting for ')' or '}' */ - /* 3 = waiting for ''' */ + int state = 0; /* 0 = waiting for '$' */ + /* 1 = waiting for '(' or '{' */ + /* 2 = waiting for ')' or '}' */ + /* 3 = waiting for ''' */ #ifdef DEBUG_PARSER char *output_start = output; - printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen (input), - input); + printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen(input), input); #endif - prev = '\0'; /* previous character */ + prev = '\0'; /* previous character */ while (inputcnt && outputcnt) { + c = *input++; + inputcnt--; + + if (state!=3) { + /* remove one level of escape characters */ + if ((c == '\\') && (prev != '\\')) { + if (inputcnt-- == 0) + break; + prev = c; c = *input++; - inputcnt--; + } + } - if (state != 3) { - /* remove one level of escape characters */ - if ((c == '\\') && (prev != '\\')) { - if (inputcnt-- == 0) - break; - prev = c; - c = *input++; - } + switch (state) { + case 0: /* Waiting for (unescaped) $ */ + if ((c == '\'') && (prev != '\\')) { + state = 3; + break; } + if ((c == '$') && (prev != '\\')) { + state++; + } else { + *(output++) = c; + outputcnt--; + } + break; + case 1: /* Waiting for ( */ + if (c == '(' || c == '{') { + state++; + varname_start = input; + } else { + state = 0; + *(output++) = '$'; + outputcnt--; - switch (state) { - case 0: /* Waiting for (unescaped) $ */ - if ((c == '\'') && (prev != '\\')) { - state = 3; - break; - } - if ((c == '$') && (prev != '\\')) { - state++; - } else { + if (outputcnt) { *(output++) = c; outputcnt--; } - break; - case 1: /* Waiting for ( */ - if (c == '(' || c == '{') { - state++; - varname_start = input; - } else { - state = 0; - *(output++) = '$'; - outputcnt--; + } + break; + case 2: /* Waiting for ) */ + if (c == ')' || c == '}') { + int i; + char envname[CFG_CBSIZE], *envval; + int envcnt = input-varname_start-1; /* Varname # of chars */ - if (outputcnt) { - *(output++) = c; + /* Get the varname */ + for (i = 0; i < envcnt; i++) { + envname[i] = varname_start[i]; + } + envname[i] = 0; + + /* Get its value */ + envval = getenv (envname); + + /* Copy into the line if it exists */ + if (envval != NULL) + while ((*envval) && outputcnt) { + *(output++) = *(envval++); outputcnt--; } - } - break; - case 2: /* Waiting for ) */ - if (c == ')' || c == '}') { - int i; - char envname[CFG_CBSIZE], *envval; - int envcnt = input - varname_start - 1; /* Varname # of chars */ - - /* Get the varname */ - for (i = 0; i < envcnt; i++) { - envname[i] = varname_start[i]; - } - envname[i] = 0; - - /* Get its value */ - envval = getenv (envname); - - /* Copy into the line if it exists */ - if (envval != NULL) - while ((*envval) && outputcnt) { - *(output++) = *(envval++); - outputcnt--; - } - /* Look for another '$' */ - state = 0; - } - break; - case 3: /* Waiting for ' */ - if ((c == '\'') && (prev != '\\')) { - state = 0; - } else { - *(output++) = c; - outputcnt--; - } - break; + /* Look for another '$' */ + state = 0; } - prev = c; + break; + case 3: /* Waiting for ' */ + if ((c == '\'') && (prev != '\\')) { + state = 0; + } else { + *(output++) = c; + outputcnt--; + } + break; + } + prev = c; } if (outputcnt) *output = 0; - else - *(output - 1) = 0; #ifdef DEBUG_PARSER printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", - strlen (output_start), output_start); + strlen(output_start), output_start); #endif } @@ -1364,7 +1360,7 @@ int run_command (const char *cmd, int flag) continue; } -#if defined(CONFIG_CMD_BOOTD) +#if (CONFIG_COMMANDS & CFG_CMD_BOOTD) /* avoid "bootd" recursion */ if (cmdtp->cmd == do_bootd) { #ifdef DEBUG_PARSER @@ -1378,7 +1374,7 @@ int run_command (const char *cmd, int flag) flag |= CMD_FLAG_BOOTD; } } -#endif +#endif /* CFG_CMD_BOOTD */ /* OK - call function to do the command */ if ((cmdtp->cmd) (cmdtp, flag, argc, argv) != 0) { @@ -1389,7 +1385,7 @@ int run_command (const char *cmd, int flag) /* Did the user stop this? */ if (had_ctrlc ()) - return -1; /* if stopped then not repeatable */ + return 0; /* if stopped then not repeatable */ } return rc ? rc : repeatable; @@ -1397,7 +1393,7 @@ int run_command (const char *cmd, int flag) /****************************************************************************/ -#if defined(CONFIG_CMD_RUN) +#if (CONFIG_COMMANDS & CFG_CMD_RUN) int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i; @@ -1425,4 +1421,4 @@ int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } return 0; } -#endif +#endif /* CFG_CMD_RUN */ diff --git a/common/memsize.c b/common/memsize.c index 6c275c9b2..dbc812dfc 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -21,16 +21,6 @@ * MA 02111-1307 USA */ -#include -#ifdef __PPC__ -/* - * At least on G2 PowerPC cores, sequential accesses to non-existent - * memory must be synchronized. - */ -# include /* for sync() */ -#else -# define sync() /* nothing */ -#endif /* * Check memory range for valid RAM. A simple memory test determines @@ -48,27 +38,20 @@ long get_ram_size(volatile long *base, long maxsize) for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ - sync (); save[i++] = *addr; - sync (); *addr = ~cnt; } addr = base; - sync (); save[i] = *addr; - sync (); *addr = 0; - sync (); if ((val = *addr) != 0) { /* Restore the original data before leaving the function. */ - sync (); *addr = save[i]; for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) { addr = base + cnt; - sync (); *addr = save[--i]; } return (0); diff --git a/common/miiphybb.c b/common/miiphybb.c index 537c15d29..adb697ca6 100644 --- a/common/miiphybb.c +++ b/common/miiphybb.c @@ -41,7 +41,7 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg) { int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) +#ifndef CONFIG_EP8248 volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif @@ -126,7 +126,7 @@ int bb_miiphy_read (char *devname, unsigned char addr, { short rdreg; /* register working value */ int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) +#ifndef CONFIG_EP8248 volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif @@ -193,7 +193,7 @@ int bb_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value) { int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) +#ifndef CONFIG_EP8248 volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); #endif diff --git a/common/miiphyutil.c b/common/miiphyutil.c index eac8275a4..e411e573c 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -29,13 +29,14 @@ #include #include -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) #include #include #include #include /* local debug macro */ +#define MII_DEBUG #undef MII_DEBUG #undef debug @@ -48,10 +49,10 @@ struct mii_dev { struct list_head link; char *name; - int (*read) (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); - int (*write) (char *devname, unsigned char addr, - unsigned char reg, unsigned short value); + int (* read)(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); + int (* write)(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); }; static struct list_head mii_devs; @@ -61,21 +62,21 @@ static struct mii_dev *current_mii; * * Initialize global data. Need to be called before any other miiphy routine. */ -void miiphy_init () +void miiphy_init() { - INIT_LIST_HEAD (&mii_devs); - current_mii = NULL; + INIT_LIST_HEAD(&mii_devs); + current_mii = NULL; } /***************************************************************************** * * Register read and write MII access routines for the device . */ -void miiphy_register (char *name, - int (*read) (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value), - int (*write) (char *devname, unsigned char addr, - unsigned char reg, unsigned short value)) +void miiphy_register(char *name, + int (* read)(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value), + int (* write)(char *devname, unsigned char addr, + unsigned char reg, unsigned short value)) { struct list_head *entry; struct mii_dev *new_dev; @@ -83,64 +84,63 @@ void miiphy_register (char *name, unsigned int name_len; /* check if we have unique name */ - list_for_each (entry, &mii_devs) { - miidev = list_entry (entry, struct mii_dev, link); - if (strcmp (miidev->name, name) == 0) { - printf ("miiphy_register: non unique device name " - "'%s'\n", name); + list_for_each(entry, &mii_devs) { + miidev = list_entry(entry, struct mii_dev, link); + if (strcmp(miidev->name, name) == 0) { + printf("miiphy_register: non unique device name '%s'\n", + name); return; } } /* allocate memory */ - name_len = strlen (name); - new_dev = - (struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1); + name_len = strlen(name); + new_dev = (struct mii_dev *)malloc(sizeof(struct mii_dev) + name_len + 1); - if (new_dev == NULL) { - printf ("miiphy_register: cannot allocate memory for '%s'\n", - name); + if(new_dev == NULL) { + printf("miiphy_register: cannot allocate memory for '%s'\n", + name); return; } - memset (new_dev, 0, sizeof (struct mii_dev) + name_len); + memset(new_dev, 0, sizeof(struct mii_dev) + name_len); /* initalize mii_dev struct fields */ - INIT_LIST_HEAD (&new_dev->link); + INIT_LIST_HEAD(&new_dev->link); new_dev->read = read; new_dev->write = write; new_dev->name = (char *)(new_dev + 1); - strncpy (new_dev->name, name, name_len); + strncpy(new_dev->name, name, name_len); new_dev->name[name_len] = '\0'; - debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n", - new_dev->name, new_dev->read, new_dev->write); + debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n", + new_dev->name, new_dev->read, new_dev->write); /* add it to the list */ - list_add_tail (&new_dev->link, &mii_devs); + list_add_tail(&new_dev->link, &mii_devs); if (!current_mii) current_mii = new_dev; } -int miiphy_set_current_dev (char *devname) +int miiphy_set_current_dev(char *devname) { struct list_head *entry; struct mii_dev *dev; - list_for_each (entry, &mii_devs) { - dev = list_entry (entry, struct mii_dev, link); + list_for_each(entry, &mii_devs) { + dev = list_entry(entry, struct mii_dev, link); - if (strcmp (devname, dev->name) == 0) { + if (strcmp(devname, dev->name) == 0) { current_mii = dev; return 0; } } - printf ("No such device: %s\n", devname); + printf("No such device: %s\n", devname); return 1; } -char *miiphy_get_current_dev () +char *miiphy_get_current_dev() { if (current_mii) return current_mii->name; @@ -156,8 +156,8 @@ char *miiphy_get_current_dev () * Returns: * 0 on success */ -int miiphy_read (char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) +int miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) { struct list_head *entry; struct mii_dev *dev; @@ -165,22 +165,22 @@ int miiphy_read (char *devname, unsigned char addr, unsigned char reg, int read_ret = 0; if (!devname) { - printf ("NULL device name!\n"); + printf("NULL device name!\n"); return 1; } - list_for_each (entry, &mii_devs) { - dev = list_entry (entry, struct mii_dev, link); + list_for_each(entry, &mii_devs) { + dev = list_entry(entry, struct mii_dev, link); - if (strcmp (devname, dev->name) == 0) { + if (strcmp(devname, dev->name) == 0) { found_dev = 1; - read_ret = dev->read (devname, addr, reg, value); + read_ret = dev->read(devname, addr, reg, value); break; } } if (found_dev == 0) - printf ("No such device: %s\n", devname); + printf("No such device: %s\n", devname); return ((found_dev) ? read_ret : 1); } @@ -193,8 +193,8 @@ int miiphy_read (char *devname, unsigned char addr, unsigned char reg, * Returns: * 0 on success */ -int miiphy_write (char *devname, unsigned char addr, unsigned char reg, - unsigned short value) +int miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) { struct list_head *entry; struct mii_dev *dev; @@ -202,22 +202,22 @@ int miiphy_write (char *devname, unsigned char addr, unsigned char reg, int write_ret = 0; if (!devname) { - printf ("NULL device name!\n"); + printf("NULL device name!\n"); return 1; } - list_for_each (entry, &mii_devs) { - dev = list_entry (entry, struct mii_dev, link); + list_for_each(entry, &mii_devs) { + dev = list_entry(entry, struct mii_dev, link); - if (strcmp (devname, dev->name) == 0) { + if (strcmp(devname, dev->name) == 0) { found_dev = 1; - write_ret = dev->write (devname, addr, reg, value); + write_ret = dev->write(devname, addr, reg, value); break; } } if (found_dev == 0) - printf ("No such device: %s\n", devname); + printf("No such device: %s\n", devname); return ((found_dev) ? write_ret : 1); } @@ -226,22 +226,23 @@ int miiphy_write (char *devname, unsigned char addr, unsigned char reg, * * Print out list of registered MII capable devices. */ -void miiphy_listdev (void) +void miiphy_listdev(void) { struct list_head *entry; struct mii_dev *dev; - puts ("MII devices: "); - list_for_each (entry, &mii_devs) { - dev = list_entry (entry, struct mii_dev, link); - printf ("'%s' ", dev->name); + puts("MII devices: "); + list_for_each(entry, &mii_devs) { + dev = list_entry(entry, struct mii_dev, link); + printf("'%s' ", dev->name); } - puts ("\n"); + puts("\n"); if (current_mii) - printf ("Current device: '%s'\n", current_mii->name); + printf("Current device: '%s'\n", current_mii->name); } + /***************************************************************************** * * Read the OUI, manufacture's model number, and revision number. @@ -253,38 +254,47 @@ void miiphy_listdev (void) * Returns: * 0 on success */ -int miiphy_info (char *devname, unsigned char addr, unsigned int *oui, +int miiphy_info (char *devname, + unsigned char addr, + unsigned int *oui, unsigned char *model, unsigned char *rev) { unsigned int reg = 0; unsigned short tmp; if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) { - debug ("PHY ID register 2 read failed\n"); +#ifdef DEBUG + puts ("PHY ID register 2 read failed\n"); +#endif return (-1); } reg = tmp; - debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg); - +#ifdef DEBUG + printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg); +#endif if (reg == 0xFFFF) { /* No physical device present at this address */ return (-1); } if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) { - debug ("PHY ID register 1 read failed\n"); +#ifdef DEBUG + puts ("PHY ID register 1 read failed\n"); +#endif return (-1); } reg |= tmp << 16; - debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg); - - *oui = (reg >> 10); - *model = (unsigned char)((reg >> 4) & 0x0000003F); - *rev = (unsigned char)(reg & 0x0000000F); +#ifdef DEBUG + printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg); +#endif + *oui = ( reg >> 10); + *model = (unsigned char) ((reg >> 4) & 0x0000003F); + *rev = (unsigned char) ( reg & 0x0000000F); return (0); } + /***************************************************************************** * * Reset the PHY. @@ -297,11 +307,15 @@ int miiphy_reset (char *devname, unsigned char addr) int loop_cnt; if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { - debug ("PHY status read failed\n"); +#ifdef DEBUG + printf ("PHY status read failed\n"); +#endif return (-1); } if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) { - debug ("PHY reset failed\n"); +#ifdef DEBUG + puts ("PHY reset failed\n"); +#endif return (-1); } #ifdef CONFIG_PHY_RESET_DELAY @@ -316,7 +330,9 @@ int miiphy_reset (char *devname, unsigned char addr) reg = 0x8000; while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) { if (miiphy_read (devname, addr, PHY_BMCR, ®) != 0) { - debug ("PHY status read failed\n"); +# ifdef DEBUG + puts ("PHY status read failed\n"); +# endif return (-1); } } @@ -329,138 +345,104 @@ int miiphy_reset (char *devname, unsigned char addr) return (0); } + /***************************************************************************** * - * Determine the ethernet speed (10/100/1000). Return 10 on error. + * Determine the ethernet speed (10/100). */ int miiphy_speed (char *devname, unsigned char addr) { - u16 bmcr, anlpar; + unsigned short reg; #if defined(CONFIG_PHY_GIGE) - u16 btsr; - - /* - * Check for 1000BASE-X. If it is supported, then assume that the speed - * is 1000. - */ - if (miiphy_is_1000base_x (devname, addr)) { - return _1000BASET; - } - /* - * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. - */ - /* Check for 1000BASE-T. */ - if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) { - printf ("PHY 1000BT status"); - goto miiphy_read_failed; - } - if (btsr != 0xFFFF && - (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) { - return _1000BASET; + if (miiphy_read (devname, addr, PHY_1000BTSR, ®)) { + printf ("PHY 1000BT Status read failed\n"); + } else { + if (reg != 0xFFFF) { + if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) !=0) { + return (_1000BASET); + } + } } #endif /* CONFIG_PHY_GIGE */ /* Check Basic Management Control Register first. */ - if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) { - printf ("PHY speed"); - goto miiphy_read_failed; + if (miiphy_read (devname, addr, PHY_BMCR, ®)) { + puts ("PHY speed read failed, assuming 10bT\n"); + return (_10BASET); } /* Check if auto-negotiation is on. */ - if (bmcr & PHY_BMCR_AUTON) { + if ((reg & PHY_BMCR_AUTON) != 0) { /* Get auto-negotiation results. */ - if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { - printf ("PHY AN speed"); - goto miiphy_read_failed; + if (miiphy_read (devname, addr, PHY_ANLPAR, ®)) { + puts ("PHY AN speed read failed, assuming 10bT\n"); + return (_10BASET); + } + if ((reg & PHY_ANLPAR_100) != 0) { + return (_100BASET); + } else { + return (_10BASET); } - return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET; } /* Get speed from basic control settings. */ - return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET; + else if (reg & PHY_BMCR_100MB) { + return (_100BASET); + } else { + return (_10BASET); + } - miiphy_read_failed: - printf (" read failed, assuming 10BASE-T\n"); - return _10BASET; } + /***************************************************************************** * - * Determine full/half duplex. Return half on error. + * Determine full/half duplex. */ int miiphy_duplex (char *devname, unsigned char addr) { - u16 bmcr, anlpar; + unsigned short reg; #if defined(CONFIG_PHY_GIGE) - u16 btsr; - - /* Check for 1000BASE-X. */ - if (miiphy_is_1000base_x (devname, addr)) { - /* 1000BASE-X */ - if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { - printf ("1000BASE-X PHY AN duplex"); - goto miiphy_read_failed; - } - } - /* - * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. - */ - /* Check for 1000BASE-T. */ - if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) { - printf ("PHY 1000BT status"); - goto miiphy_read_failed; - } - if (btsr != 0xFFFF) { - if (btsr & PHY_1000BTSR_1000FD) { - return FULL; - } else if (btsr & PHY_1000BTSR_1000HD) { - return HALF; + if (miiphy_read (devname, addr, PHY_1000BTSR, ®)) { + printf ("PHY 1000BT Status read failed\n"); + } else { + if ( (reg != 0xFFFF) && + (reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) ) { + if ((reg & PHY_1000BTSR_1000FD) !=0) { + return (FULL); + } else { + return (HALF); + } } } #endif /* CONFIG_PHY_GIGE */ /* Check Basic Management Control Register first. */ - if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) { - puts ("PHY duplex"); - goto miiphy_read_failed; + if (miiphy_read (devname, addr, PHY_BMCR, ®)) { + puts ("PHY duplex read failed, assuming half duplex\n"); + return (HALF); } /* Check if auto-negotiation is on. */ - if (bmcr & PHY_BMCR_AUTON) { + if ((reg & PHY_BMCR_AUTON) != 0) { /* Get auto-negotiation results. */ - if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) { - puts ("PHY AN duplex"); - goto miiphy_read_failed; + if (miiphy_read (devname, addr, PHY_ANLPAR, ®)) { + puts ("PHY AN duplex read failed, assuming half duplex\n"); + return (HALF); + } + + if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) { + return (FULL); + } else { + return (HALF); } - return (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ? - FULL : HALF; } /* Get speed from basic control settings. */ - return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF; - - miiphy_read_failed: - printf (" read failed, assuming half duplex\n"); - return HALF; -} - -/***************************************************************************** - * - * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/ - * 1000BASE-T, or on error. - */ -int miiphy_is_1000base_x (char *devname, unsigned char addr) -{ -#if defined(CONFIG_PHY_GIGE) - u16 exsr; - - if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) { - printf ("PHY extended status read failed, assuming no " - "1000BASE-X\n"); - return 0; + else if (reg & PHY_BMCR_DPLX) { + return (FULL); + } else { + return (HALF); } - return 0 != (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)); -#else - return 0; -#endif + } #ifdef CFG_FAULT_ECHO_LINK_DOWN @@ -473,7 +455,7 @@ int miiphy_link (char *devname, unsigned char addr) unsigned short reg; /* dummy read; needed to latch some phys */ - (void)miiphy_read (devname, addr, PHY_BMSR, ®); + (void)miiphy_read(devname, addr, PHY_BMSR, ®); if (miiphy_read (devname, addr, PHY_BMSR, ®)) { puts ("PHY_BMSR read failed, assuming no link\n"); return (0); @@ -487,4 +469,5 @@ int miiphy_link (char *devname, unsigned char addr) } } #endif -#endif /* CONFIG_MII */ + +#endif /* CONFIG_MII || (CONFIG_COMMANDS & CFG_CMD_MII) */ diff --git a/common/serial.c b/common/serial.c index bfda7ca55..62dc94bb6 100644 --- a/common/serial.c +++ b/common/serial.c @@ -32,8 +32,8 @@ DECLARE_GLOBAL_DATA_PTR; static struct serial_device *serial_devices = NULL; static struct serial_device *serial_current = NULL; -#if !defined(CONFIG_LWMON) && !defined(CONFIG_PXA27X) -struct serial_device *__default_serial_console (void) +#ifndef CONFIG_LWMON +struct serial_device *default_serial_console (void) { #if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) return &serial_smc_device; @@ -41,44 +41,22 @@ struct serial_device *__default_serial_console (void) || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) return &serial_scc_device; #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ - || defined(CONFIG_MPC5xxx) -#if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL) -#if (CONFIG_CONS_INDEX==1) - return &eserial1_device; -#elif (CONFIG_CONS_INDEX==2) - return &eserial2_device; -#elif (CONFIG_CONS_INDEX==3) - return &eserial3_device; -#elif (CONFIG_CONS_INDEX==4) - return &eserial4_device; -#else -#error "Bad CONFIG_CONS_INDEX." -#endif -#elif defined(CONFIG_UART1_CONSOLE) + || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) +#if defined(CONFIG_UART1_CONSOLE) return &serial1_device; #else return &serial0_device; #endif -#elif defined(CONFIG_S3C2410) -#if defined(CONFIG_SERIAL1) - return &s3c24xx_serial0_device; -#elif defined(CONFIG_SERIAL2) - return &s3c24xx_serial1_device; -#elif defined(CONFIG_SERIAL3) - return &s3c24xx_serial2_device; -#else -#error "CONFIG_SERIAL? missing." -#endif +#elif defined(CONFIG_3430ZOOM2) + return DEFAULT_ZOOM2_SERIAL_DEVICE; #else + #error No default console #endif } - -struct serial_device *default_serial_console(void) __attribute__((weak, alias("__default_serial_console"))); #endif -int serial_register (struct serial_device *dev) +static int serial_register (struct serial_device *dev) { dev->init += gd->reloc_off; dev->setbrg += gd->reloc_off; @@ -104,40 +82,18 @@ void serial_initialize (void) #endif #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ - || defined(CONFIG_MPC5xxx) + || defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx) serial_register(&serial0_device); serial_register(&serial1_device); #endif -#if defined(CFG_NS16550_SERIAL) -#if defined(CFG_NS16550_COM1) - serial_register(&eserial1_device); -#endif -#if defined(CFG_NS16550_COM2) - serial_register(&eserial2_device); -#endif -#if defined(CFG_NS16550_COM3) - serial_register(&eserial3_device); -#endif -#if defined(CFG_NS16550_COM4) - serial_register(&eserial4_device); -#endif -#endif /* CFG_NS16550_SERIAL */ -#if defined (CONFIG_FFUART) - serial_register(&serial_ffuart_device); -#endif -#if defined (CONFIG_BTUART) - serial_register(&serial_btuart_device); -#endif -#if defined (CONFIG_STUART) - serial_register(&serial_stuart_device); -#endif -#if defined(CONFIG_S3C2410) - serial_register(&s3c24xx_serial0_device); - serial_register(&s3c24xx_serial1_device); - serial_register(&s3c24xx_serial2_device); +#if defined(CONFIG_3430ZOOM2) + serial_register(&zoom2_serial_device0); + serial_register(&zoom2_serial_device1); + serial_register(&zoom2_serial_device2); + serial_register(&zoom2_serial_device3); #endif + serial_assign (default_serial_console ()->name); } diff --git a/common/soft_i2c.c b/common/soft_i2c.c index 5ef7f303b..edad51bc4 100644 --- a/common/soft_i2c.c +++ b/common/soft_i2c.c @@ -29,16 +29,13 @@ #ifdef CONFIG_MPC8260 /* only valid for MPC8260 */ #include #endif -#ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */ +#ifdef CONFIG_AT91RM9200DK /* need this for the at91rm9200dk */ #include #include #endif #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include #endif -#ifdef CONFIG_LPC2292 -#include -#endif #include #if defined(CONFIG_SOFT_I2C) @@ -252,7 +249,6 @@ static uchar read_byte(int ack) * Read 8 bits, MSB first. */ I2C_TRISTATE; - I2C_SDA(1); data = 0; for(j = 0; j < 8; j++) { I2C_SCL(0); diff --git a/common/soft_spi.c b/common/soft_spi.c index c13165030..00a57de8a 100644 --- a/common/soft_spi.c +++ b/common/soft_spi.c @@ -29,8 +29,6 @@ #if defined(CONFIG_SOFT_SPI) -#include - /*----------------------------------------------------------------------- * Definitions */ @@ -41,15 +39,6 @@ #define PRINTD(fmt,args...) #endif -struct soft_spi_slave { - struct spi_slave slave; - unsigned int mode; -}; - -static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave) -{ - return container_of(slave, struct soft_spi_slave, slave); -} /*=====================================================================*/ /* Public Functions */ @@ -67,57 +56,6 @@ void spi_init (void) #endif } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct soft_spi_slave *ss; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - ss = malloc(sizeof(struct soft_spi_slave)); - if (!ss) - return NULL; - - ss->slave.bus = bus; - ss->slave.cs = cs; - ss->mode = mode; - - /* TODO: Use max_hz to limit the SCK rate */ - - return &ss->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct soft_spi_slave *ss = to_soft_spi(slave); - - free(ss); -} - -int spi_claim_bus(struct spi_slave *slave) -{ -#ifdef CFG_IMMR - volatile immap_t *immr = (immap_t *)CFG_IMMR; -#endif - struct soft_spi_slave *ss = to_soft_spi(slave); - - /* - * Make sure the SPI clock is in idle state as defined for - * this slave. - */ - if (ss->mode & SPI_CPOL) - SPI_SCL(1); - else - SPI_SCL(0); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - /* Nothing to do */ -} /*----------------------------------------------------------------------- * SPI transfer @@ -130,54 +68,48 @@ void spi_release_bus(struct spi_slave *slave) * and "din" can point to the same memory location, in which case the * input data overwrites the output data (since both are buffered by * temporary variables, this is OK). + * + * If the chipsel() function is not NULL, it is called with a parameter + * of '1' (chip select active) at the start of the transfer and again with + * a parameter of '0' at the end of the transfer. + * + * If the chipsel() function _is_ NULL, it the responsibility of the + * caller to make the appropriate chip select active before calling + * spi_xfer() and making it inactive after spi_xfer() returns. */ -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) { -#ifdef CFG_IMMR volatile immap_t *immr = (immap_t *)CFG_IMMR; -#endif - struct soft_spi_slave *ss = to_soft_spi(slave); - uchar tmpdin = 0; - uchar tmpdout = 0; - const u8 *txd = dout; - u8 *rxd = din; - int cpol = ss->mode & SPI_CPOL; - int cpha = ss->mode & SPI_CPHA; - unsigned int j; + uchar tmpdin = 0; + uchar tmpdout = 0; + int j; - PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", - slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen); + PRINTD("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", + (int)chipsel, *(uint *)dout, *(uint *)din, bitlen); - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); + if(chipsel != NULL) { + (*chipsel)(1); /* select the target chip */ + } for(j = 0; j < bitlen; j++) { /* * Check if it is time to work on a new byte. */ if((j % 8) == 0) { - tmpdout = *txd++; + tmpdout = *dout++; if(j != 0) { - *rxd++ = tmpdin; + *din++ = tmpdin; } tmpdin = 0; } - - if (!cpha) - SPI_SCL(!cpol); + SPI_SCL(0); SPI_SDA(tmpdout & 0x80); SPI_DELAY; - if (cpha) - SPI_SCL(!cpol); - else - SPI_SCL(cpol); - tmpdin <<= 1; - tmpdin |= SPI_READ; - tmpdout <<= 1; + SPI_SCL(1); SPI_DELAY; - if (cpha) - SPI_SCL(cpol); + tmpdin <<= 1; + tmpdin |= SPI_READ; + tmpdout <<= 1; } /* * If the number of bits isn't a multiple of 8, shift the last @@ -186,10 +118,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, */ if((bitlen % 8) != 0) tmpdin <<= 8 - (bitlen % 8); - *rxd++ = tmpdin; + *din++ = tmpdin; - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + SPI_SCL(0); /* SPI wants the clock left low for idle */ + + if(chipsel != NULL) { + (*chipsel)(0); /* deselect the target chip */ + + } return(0); } diff --git a/common/spartan2.c b/common/spartan2.c index 2f1ea2c09..0fb23b659 100644 --- a/common/spartan2.c +++ b/common/spartan2.c @@ -25,7 +25,7 @@ #include /* core U-Boot definitions */ #include /* Spartan-II device family */ -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN2) +#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2)) /* Define FPGA_DEBUG to get debug printf's */ #ifdef FPGA_DEBUG @@ -441,7 +441,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; int i; - unsigned char val; + char val; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -516,7 +516,7 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) (*fn->clk) (FALSE, TRUE, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val & 0x80), TRUE, cookie); + (*fn->wr) ((val < 0), TRUE, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); @@ -561,13 +561,6 @@ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) } putc ('\n'); /* terminate the dotted line */ - /* - * Run the post configuration function if there is one. - */ - if (*fn->post) { - (*fn->post) (cookie); - } - #ifdef CFG_FPGA_PROG_FEEDBACK if (ret_val == FPGA_SUCCESS) { puts ("Done.\n"); @@ -622,10 +615,8 @@ static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, desc); - if (fn->pre) { - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - } + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; addr = (ulong) (fn->pgm) + reloc_offset; fn_r->pgm = (Xilinx_pgm_fn) addr; @@ -642,11 +633,6 @@ static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) addr = (ulong) (fn->wr) + reloc_offset; fn_r->wr = (Xilinx_wr_fn) addr; - if (fn->post) { - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - } - fn_r->relocated = TRUE; } else { diff --git a/common/spartan3.c b/common/spartan3.c index d329e70cf..c0f2b05e4 100644 --- a/common/spartan3.c +++ b/common/spartan3.c @@ -30,7 +30,7 @@ #include /* core U-Boot definitions */ #include /* Spartan-II device family */ -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3) +#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3)) /* Define FPGA_DEBUG to get debug printf's */ #ifdef FPGA_DEBUG @@ -446,7 +446,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) int ret_val = FPGA_FAIL; /* assume the worst */ Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; int i; - unsigned char val; + char val; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -521,7 +521,7 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) (*fn->clk) (FALSE, TRUE, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val & 0x80), TRUE, cookie); + (*fn->wr) ((val < 0), TRUE, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); @@ -566,13 +566,6 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) } putc ('\n'); /* terminate the dotted line */ - /* - * Run the post configuration function if there is one. - */ - if (*fn->post) { - (*fn->post) (cookie); - } - #ifdef CFG_FPGA_PROG_FEEDBACK if (ret_val == FPGA_SUCCESS) { puts ("Done.\n"); @@ -627,10 +620,8 @@ static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, desc); - if (fn->pre) { - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - } + addr = (ulong) (fn->pre) + reloc_offset; + fn_r->pre = (Xilinx_pre_fn) addr; addr = (ulong) (fn->pgm) + reloc_offset; fn_r->pgm = (Xilinx_pgm_fn) addr; @@ -647,11 +638,6 @@ static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) addr = (ulong) (fn->wr) + reloc_offset; fn_r->wr = (Xilinx_wr_fn) addr; - if (fn->post) { - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - } - fn_r->relocated = TRUE; } else { diff --git a/common/usb.c b/common/usb.c index a45d113a7..0857494b2 100644 --- a/common/usb.c +++ b/common/usb.c @@ -48,13 +48,12 @@ #include #include #include -#include -#if defined(CONFIG_CMD_USB) +#if (CONFIG_COMMANDS & CFG_CMD_USB) #include #ifdef CONFIG_4xx -#include +#include <405gp_pci.h> #endif #undef USB_DEBUG @@ -178,10 +177,10 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, /* set setup command */ setup_packet.requesttype = requesttype; setup_packet.request = request; - setup_packet.value = cpu_to_le16(value); - setup_packet.index = cpu_to_le16(index); - setup_packet.length = cpu_to_le16(size); - USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X, value 0x%X index 0x%X length 0x%X\n", + setup_packet.value = swap_16(value); + setup_packet.index = swap_16(index); + setup_packet.length = swap_16(size); + USB_PRINTF("usb_control_msg: request: 0x%X, requesttype: 0x%X\nvalue 0x%X index 0x%X length 0x%X\n", request,requesttype,value,index,size); dev->status=USB_ST_NOT_PROC; /*not yet processed */ @@ -252,7 +251,7 @@ int usb_set_maxpacket(struct usb_device *dev) for(i=0; iconfig.bNumInterfaces;i++) { for(ii=0; iiconfig.if_desc[i].bNumEndpoints; ii++) { - ep = &dev->config.if_desc[i].ep_desc[ii]; + ep=&dev->config.if_desc[i].ep_desc[ii]; b=ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; if((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)==USB_ENDPOINT_XFER_CONTROL) { /* Control => bidirectional */ @@ -301,7 +300,7 @@ int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno) return -1; } memcpy(&dev->config, buffer, buffer[0]); - le16_to_cpus(&(dev->config.wTotalLength)); + dev->config.wTotalLength = swap_16(dev->config.wTotalLength); dev->config.no_of_if = 0; index = dev->config.bLength; @@ -330,7 +329,8 @@ int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno) dev->config.if_desc[ifno].no_of_ep++; /* found an endpoint */ memcpy(&dev->config.if_desc[ifno].ep_desc[epno], &buffer[index], buffer[index]); - le16_to_cpus(&(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize)); + dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize = + swap_16(dev->config.if_desc[ifno].ep_desc[epno].wMaxPacketSize); USB_PRINTF("if %d, ep %d\n", ifno, epno); break; default: @@ -387,7 +387,7 @@ int usb_clear_halt(struct usb_device *dev, int pipe) int usb_get_descriptor(struct usb_device *dev, unsigned char type, unsigned char index, void *buf, int size) { int res; - res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), + res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, (type << 8) + index, 0, buf, size, USB_CNTL_TIMEOUT); @@ -399,7 +399,7 @@ int usb_get_descriptor(struct usb_device *dev, unsigned char type, unsigned char */ int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cfgno) { - int result; + int result; unsigned int tmp; struct usb_config_descriptor *config; @@ -413,7 +413,7 @@ int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cf printf("config descriptor too short (expected %i, got %i)\n",8,result); return -1; } - tmp = le16_to_cpu(config->wTotalLength); + tmp=swap_16(config->wTotalLength); if (tmp > USB_BUFSIZ) { USB_PRINTF("usb_get_configuration_no: failed to get descriptor - too long: %d\n", @@ -627,7 +627,7 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size) if (size <= 0 || !buf || !index) return -1; buf[0] = 0; - tbuf = &mybuf[0]; + tbuf=&mybuf[0]; /* get langid for strings if it's not yet known */ if (!dev->have_langid) { @@ -816,10 +816,10 @@ int usb_new_device(struct usb_device *dev) return 1; } /* correct le values */ - le16_to_cpus(&dev->descriptor.bcdUSB); - le16_to_cpus(&dev->descriptor.idVendor); - le16_to_cpus(&dev->descriptor.idProduct); - le16_to_cpus(&dev->descriptor.bcdDevice); + dev->descriptor.bcdUSB=swap_16(dev->descriptor.bcdUSB); + dev->descriptor.idVendor=swap_16(dev->descriptor.idVendor); + dev->descriptor.idProduct=swap_16(dev->descriptor.idProduct); + dev->descriptor.bcdDevice=swap_16(dev->descriptor.bcdDevice); /* only support for one config for now */ usb_get_configuration_no(dev,&tmpbuf[0],0); usb_parse_config(dev,&tmpbuf[0],0); @@ -857,7 +857,7 @@ void usb_scan_devices(void) /* first make all devices unknown */ for(i=0;istatus); return -1; } - portstatus = le16_to_cpu(portsts.wPortStatus); - portchange = le16_to_cpu(portsts.wPortChange); + portstatus = swap_16(portsts.wPortStatus); + portchange = swap_16(portsts.wPortChange); USB_HUB_PRINTF("portstatus %x, change %x, %s\n", portstatus ,portchange, portstatus&(1< 256 [= sizeof(char)] */ i = descriptor->bLength; if (i > USB_BUFSIZ) { - USB_HUB_PRINTF("usb_hub_configure: failed to get hub descriptor - too long: %d\n", + USB_HUB_PRINTF("usb_hub_configure: failed to get hub descriptor - too long: %d\N", descriptor->bLength); return -1; } @@ -1099,7 +1099,7 @@ int usb_hub_configure(struct usb_device *dev) } memcpy((unsigned char *)&hub->desc,buffer,descriptor->bLength); /* adjust 16bit values */ - hub->desc.wHubCharacteristics = le16_to_cpu(descriptor->wHubCharacteristics); + hub->desc.wHubCharacteristics=swap_16(descriptor->wHubCharacteristics); /* set the bitmap */ bitmap=(unsigned char *)&hub->desc.DeviceRemovable[0]; memset(bitmap,0xff,(USB_MAXCHILDREN+1+7)/8); /* devices not removable by default */ @@ -1161,11 +1161,11 @@ int usb_hub_configure(struct usb_device *dev) } hubsts = (struct usb_hub_status *)buffer; USB_HUB_PRINTF("get_hub_status returned status %X, change %X\n", - le16_to_cpu(hubsts->wHubStatus),le16_to_cpu(hubsts->wHubChange)); + swap_16(hubsts->wHubStatus),swap_16(hubsts->wHubChange)); USB_HUB_PRINTF("local power source is %s\n", - (le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? "lost (inactive)" : "good"); + (swap_16(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? "lost (inactive)" : "good"); USB_HUB_PRINTF("%sover-current condition exists\n", - (le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? "" : "no "); + (swap_16(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? "" : "no "); usb_hub_power_on(hub); for (i = 0; i < dev->maxchild; i++) { struct usb_port_status portsts; @@ -1175,8 +1175,8 @@ int usb_hub_configure(struct usb_device *dev) USB_HUB_PRINTF("get_port_status failed\n"); continue; } - portstatus = le16_to_cpu(portsts.wPortStatus); - portchange = le16_to_cpu(portsts.wPortChange); + portstatus = swap_16(portsts.wPortStatus); + portchange = swap_16(portsts.wPortChange); USB_HUB_PRINTF("Port %d Status %X Change %X\n",i+1,portstatus,portchange); if (portchange & USB_PORT_STAT_C_CONNECTION) { USB_HUB_PRINTF("port %d connection change\n", i + 1); @@ -1247,6 +1247,6 @@ int usb_hub_probe(struct usb_device *dev, int ifnum) return ret; } -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_USB) */ /* EOF */ diff --git a/common/usb_kbd.c b/common/usb_kbd.c index c8764952e..56c21660f 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -26,7 +26,6 @@ */ #include #include -#include #ifdef CONFIG_USB_KEYBOARD @@ -85,7 +84,6 @@ int repeat_delay; static unsigned char num_lock = 0; static unsigned char caps_lock = 0; static unsigned char scroll_lock = 0; -static unsigned char ctrl = 0; static unsigned char leds __attribute__ ((aligned (0x4))); @@ -122,9 +120,6 @@ static void usb_kbd_put_queue(char data) /* test if a character is in the queue */ static int usb_kbd_testc(void) { -#ifdef CFG_USB_EVENT_POLL - usb_event_poll(); -#endif if(usb_in_pointer==usb_out_pointer) return(0); /* no data */ else @@ -134,11 +129,7 @@ static int usb_kbd_testc(void) static int usb_kbd_getc(void) { char c; - while(usb_in_pointer==usb_out_pointer) { -#ifdef CFG_USB_EVENT_POLL - usb_event_poll(); -#endif - } + while(usb_in_pointer==usb_out_pointer); if((usb_out_pointer+1)==USB_KBD_BUFFER_LEN) usb_out_pointer=0; else @@ -239,7 +230,7 @@ static void usb_kbd_setled(struct usb_device *dev) leds|=1; usb_control_msg(dev, usb_sndctrlpipe(dev, 0), USB_REQ_SET_REPORT, USB_TYPE_CLASS | USB_RECIP_INTERFACE, - 0x200, iface->bInterfaceNumber,(void *)&leds, 1, 0); + 0x200, iface->bInterfaceNumber,(void *)&leds, 1, 0); } @@ -252,7 +243,7 @@ static int usb_kbd_translate(unsigned char scancode,unsigned char modifier,int p if(pressed==0) { /* key released */ - repeat_delay=0; + repeat_delay=0; return 0; } if(pressed==2) { @@ -262,7 +253,7 @@ static int usb_kbd_translate(unsigned char scancode,unsigned char modifier,int p repeat_delay=REPEAT_DELAY; } keycode=0; - if((scancode>3) && (scancode<=0x1d)) { /* alpha numeric values */ + if((scancode>3) && (scancode<0x1d)) { /* alpha numeric values */ keycode=scancode-4 + 0x61; if(caps_lock) keycode&=~CAPITAL_MASK; /* switch to capital Letters */ @@ -279,10 +270,6 @@ static int usb_kbd_translate(unsigned char scancode,unsigned char modifier,int p else /* non shifted */ keycode=usb_kbd_numkey[scancode-0x1e]; } - - if (ctrl) - keycode = scancode - 0x3; - if(pressed==1) { if(scancode==NUM_LOCK) { num_lock=~num_lock; @@ -315,17 +302,6 @@ static int usb_kbd_irq(struct usb_device *dev) return 1; } res=0; - - switch (new[0]) { - case 0x0: /* No combo key pressed */ - ctrl = 0; - break; - case 0x01: /* Left Ctrl pressed */ - case 0x10: /* Right Ctrl pressed */ - ctrl = 1; - break; - } - for (i = 2; i < 8; i++) { if (old[i] > 3 && memscan(&new[2], old[i], 6) == &new[8]) { res|=usb_kbd_translate(old[i],new[0],0); @@ -476,14 +452,14 @@ static int fetch_item(unsigned char *start,unsigned char *end, struct hid_item * break; case 2: if ((end - start) >= 2) { - item->data.u16 = le16_to_cpu((unsigned short *)start); + item->data.u16 = swap_16((unsigned short *)start); start+=2; return item->size; } case 3: item->size++; if ((end - start) >= 4) { - item->data.u32 = le32_to_cpu((unsigned long *)start); + item->data.u32 = swap_32((unsigned long *)start); start+=4; return item->size; } @@ -706,15 +682,15 @@ static int usb_kbd_get_hid_desc(struct usb_device *dev) } index=head->bLength; config=(struct usb_config_descriptor *)&buffer[0]; - len=le16_to_cpu(config->wTotalLength); + len=swap_16(config->wTotalLength); /* Ok the first entry must be a configuration entry, now process the others */ head=(struct usb_descriptor_header *)&buffer[index]; while(index+1 < len) { if(head->bDescriptorType==USB_DT_HID) { printf("HID desc found\n"); memcpy(&usb_kbd_hid_desc,&buffer[index],buffer[index]); - le16_to_cpus(&usb_kbd_hid_desc.bcdHID); - le16_to_cpus(&usb_kbd_hid_desc.wDescriptorLength); + usb_kbd_hid_desc.bcdHID=swap_16(usb_kbd_hid_desc.bcdHID); + usb_kbd_hid_desc.wDescriptorLength=swap_16(usb_kbd_hid_desc.wDescriptorLength); usb_kbd_display_hid(&usb_kbd_hid_desc); len=0; break; @@ -730,8 +706,8 @@ static int usb_kbd_get_hid_desc(struct usb_device *dev) return -1; } printf(" report descriptor (size %u, read %d)\n", len, index); - start = &buffer[0]; - end = &buffer[len]; + start=&buffer[0]; + end=&buffer[len]; i=0; do { index=fetch_item(start,end,&item); diff --git a/common/usb_storage.c b/common/usb_storage.c index d8fbb69a3..e64470cb9 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -52,12 +52,10 @@ #include #include -#include #include -#if defined(CONFIG_CMD_USB) -#include +#if (CONFIG_COMMANDS & CFG_CMD_USB) #include #ifdef CONFIG_USB_STORAGE @@ -170,13 +168,13 @@ static struct us_data usb_stor[USB_MAX_STOR_DEV]; int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc); int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data *ss); -unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer); +unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, unsigned long *buffer); struct usb_device * usb_get_dev_index(int index); void uhci_show_temp_int_td(void); block_dev_desc_t *usb_stor_get_dev(int index) { - return (index < USB_MAX_STOR_DEV) ? &usb_dev_desc[index] : NULL; + return &usb_dev_desc[index]; } @@ -189,20 +187,17 @@ void usb_show_progress(void) * show info on storage devices; 'usb start/init' must be invoked earlier * as we only retrieve structures populated during devices initialization */ -int usb_stor_info(void) +void usb_stor_info(void) { int i; - if (usb_max_devs > 0) { + if (usb_max_devs > 0) for (i = 0; i < usb_max_devs; i++) { printf (" Device %d: ", i); dev_print(&usb_dev_desc[i]); } - return 0; - } - - printf("No storage devices, perhaps not 'usb start'ed..?\n"); - return 1; + else + printf("No storage devices, perhaps not 'usb start'ed..?\n"); } /********************************************************************************* @@ -475,9 +470,9 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) /* always OUT to the ep */ pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); - cbw.dCBWSignature = cpu_to_le32(CBWSIGNATURE); - cbw.dCBWTag = cpu_to_le32(CBWTag++); - cbw.dCBWDataTransferLength = cpu_to_le32(srb->datalen); + cbw.dCBWSignature = swap_32(CBWSIGNATURE); + cbw.dCBWTag = swap_32(CBWTag++); + cbw.dCBWDataTransferLength = swap_32(srb->datalen); cbw.bCBWFlags = (dir_in? CBWFLAGS_IN : CBWFLAGS_OUT); cbw.bCBWLUN = srb->lun; cbw.bCDBLength = srb->cmdlen; @@ -693,14 +688,14 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) printf("\n"); #endif /* misuse pipe to get the residue */ - pipe = le32_to_cpu(csw.dCSWDataResidue); + pipe = swap_32(csw.dCSWDataResidue); if (pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0) pipe = srb->datalen - data_actlen; - if (CSWSIGNATURE != le32_to_cpu(csw.dCSWSignature)) { + if (CSWSIGNATURE != swap_32(csw.dCSWSignature)) { USB_STOR_PRINTF("!CSWSIGNATURE\n"); usb_stor_BBB_reset(us); return USB_STOR_TRANSPORT_FAILED; - } else if ((CBWTag - 1) != le32_to_cpu(csw.dCSWTag)) { + } else if ((CBWTag - 1) != swap_32(csw.dCSWTag)) { USB_STOR_PRINTF("!Tag\n"); usb_stor_BBB_reset(us); return USB_STOR_TRANSPORT_FAILED; @@ -731,7 +726,7 @@ int usb_stor_CB_transport(ccb *srb, struct us_data *us) ccb reqsrb; int retry,notready; - psrb = &reqsrb; + psrb=&reqsrb; status=USB_STOR_TRANSPORT_GOOD; retry=0; notready=0; @@ -776,7 +771,7 @@ do_retry: psrb->cmd[1]=srb->lun<<5; psrb->cmd[4]=18; psrb->datalen=18; - psrb->pdata = &srb->sense_buf[0]; + psrb->pdata=&srb->sense_buf[0]; psrb->cmdlen=12; /* issue the command */ result=usb_stor_CB_comdat(psrb,us); @@ -858,7 +853,7 @@ static int usb_request_sense(ccb *srb,struct us_data *ss) srb->cmd[1]=srb->lun<<5; srb->cmd[4]=18; srb->datalen=18; - srb->pdata = &srb->sense_buf[0]; + srb->pdata=&srb->sense_buf[0]; srb->cmdlen=12; ss->transport(srb,ss); USB_STOR_PRINTF("Request Sense returned %02X %02X %02X\n",srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); @@ -921,31 +916,9 @@ static int usb_read_10(ccb *srb,struct us_data *ss, unsigned long start, unsigne } -#ifdef CONFIG_USB_BIN_FIXUP -/* - * Some USB storage devices queried for SCSI identification data respond with - * binary strings, which if output to the console freeze the terminal. The - * workaround is to modify the vendor and product strings read from such - * device with proper values (as reported by 'usb info'). - * - * Vendor and product length limits are taken from the definition of - * block_dev_desc_t in include/part.h. - */ -static void usb_bin_fixup(struct usb_device_descriptor descriptor, - unsigned char vendor[], - unsigned char product[]) { - const unsigned char max_vendor_len = 40; - const unsigned char max_product_len = 20; - if (descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a) { - strncpy ((char *)vendor, "SMSC", max_vendor_len); - strncpy ((char *)product, "Flash Media Cntrller", max_product_len); - } -} -#endif /* CONFIG_USB_BIN_FIXUP */ - #define USB_MAX_READ_BLK 20 -unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer) +unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, unsigned long *buffer) { unsigned long start,blks, buf_addr; unsigned short smallblks; @@ -1198,9 +1171,6 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t dev_desc->vendor[8] = 0; dev_desc->product[16] = 0; dev_desc->revision[4] = 0; -#ifdef CONFIG_USB_BIN_FIXUP - usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor, (uchar *)dev_desc->product); -#endif /* CONFIG_USB_BIN_FIXUP */ USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n",usb_stor_buf[2],usb_stor_buf[3]); if(usb_test_unit_ready(pccb,ss)) { printf("Device NOT ready\n Request Sense returned %02X %02X %02X\n",pccb->sense_buf[2],pccb->sense_buf[12],pccb->sense_buf[13]); @@ -1223,9 +1193,18 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t if(cap[0]>(0x200000 * 10)) /* greater than 10 GByte */ cap[0]>>=16; #endif - cap[0] = cpu_to_be32(cap[0]); - cap[1] = cpu_to_be32(cap[1]); - +#ifdef LITTLEENDIAN + cap[0] = ((unsigned long)( + (((unsigned long)(cap[0]) & (unsigned long)0x000000ffUL) << 24) | + (((unsigned long)(cap[0]) & (unsigned long)0x0000ff00UL) << 8) | + (((unsigned long)(cap[0]) & (unsigned long)0x00ff0000UL) >> 8) | + (((unsigned long)(cap[0]) & (unsigned long)0xff000000UL) >> 24) )); + cap[1] = ((unsigned long)( + (((unsigned long)(cap[1]) & (unsigned long)0x000000ffUL) << 24) | + (((unsigned long)(cap[1]) & (unsigned long)0x0000ff00UL) << 8) | + (((unsigned long)(cap[1]) & (unsigned long)0x00ff0000UL) >> 8) | + (((unsigned long)(cap[1]) & (unsigned long)0xff000000UL) >> 24) )); +#endif /* this assumes bigendian! */ cap[0] += 1; capacity = &cap[0]; @@ -1244,4 +1223,4 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t } #endif /* CONFIG_USB_STORAGE */ -#endif +#endif /* CFG_CMD_USB */ diff --git a/common/virtex2.c b/common/virtex2.c index 665a503ec..b5dc366aa 100644 --- a/common/virtex2.c +++ b/common/virtex2.c @@ -31,7 +31,7 @@ #include #include -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_VIRTEX2) +#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2)) #if 0 #define FPGA_DEBUG @@ -84,7 +84,7 @@ * an XC2V1000, if anyone can ever get ahold of one. */ #ifndef CFG_FPGA_WAIT_INIT -#define CFG_FPGA_WAIT_INIT CFG_HZ/2 /* 500 ms */ +#define CFG_FPGA_WAIT_INIT CFG_HZ/2 /* 500 ms */ #endif /* diff --git a/common/xilinx.c b/common/xilinx.c index c89823868..e03e78cb2 100644 --- a/common/xilinx.c +++ b/common/xilinx.c @@ -32,7 +32,7 @@ #include #include -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX) +#if (CONFIG_FPGA & CFG_FPGA_XILINX) #if 0 #define FPGA_DEBUG @@ -59,7 +59,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) } else switch (desc->family) { case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) +#if (CONFIG_FPGA & CFG_SPARTAN2) PRINTF ("%s: Launching the Spartan-II Loader...\n", __FUNCTION__); ret_val = Spartan2_load (desc, buf, bsize); @@ -69,7 +69,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) #endif break; case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) +#if (CONFIG_FPGA & CFG_SPARTAN3) PRINTF ("%s: Launching the Spartan-III Loader...\n", __FUNCTION__); ret_val = Spartan3_load (desc, buf, bsize); @@ -79,7 +79,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize) #endif break; case Xilinx_Virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) +#if (CONFIG_FPGA & CFG_VIRTEX2) PRINTF ("%s: Launching the Virtex-II Loader...\n", __FUNCTION__); ret_val = Virtex2_load (desc, buf, bsize); @@ -106,7 +106,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) } else switch (desc->family) { case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) +#if (CONFIG_FPGA & CFG_SPARTAN2) PRINTF ("%s: Launching the Spartan-II Reader...\n", __FUNCTION__); ret_val = Spartan2_dump (desc, buf, bsize); @@ -116,7 +116,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) #endif break; case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) +#if (CONFIG_FPGA & CFG_SPARTAN3) PRINTF ("%s: Launching the Spartan-III Reader...\n", __FUNCTION__); ret_val = Spartan3_dump (desc, buf, bsize); @@ -126,7 +126,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize) #endif break; case Xilinx_Virtex2: -#if defined( CONFIG_FPGA_VIRTEX2) +#if (CONFIG_FPGA & CFG_VIRTEX2) PRINTF ("%s: Launching the Virtex-II Reader...\n", __FUNCTION__); ret_val = Virtex2_dump (desc, buf, bsize); @@ -198,7 +198,7 @@ int xilinx_info (Xilinx_desc * desc) printf ("Device Function Table @ 0x%p\n", desc->iface_fns); switch (desc->family) { case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) +#if (CONFIG_FPGA & CFG_SPARTAN2) Spartan2_info (desc); #else /* just in case */ @@ -207,7 +207,7 @@ int xilinx_info (Xilinx_desc * desc) #endif break; case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) +#if (CONFIG_FPGA & CFG_SPARTAN3) Spartan3_info (desc); #else /* just in case */ @@ -216,7 +216,7 @@ int xilinx_info (Xilinx_desc * desc) #endif break; case Xilinx_Virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) +#if (CONFIG_FPGA & CFG_VIRTEX2) Virtex2_info (desc); #else /* just in case */ @@ -249,7 +249,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset) } else switch (desc->family) { case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) +#if (CONFIG_FPGA & CFG_SPARTAN2) ret_val = Spartan2_reloc (desc, reloc_offset); #else printf ("%s: No support for Spartan-II devices.\n", @@ -257,7 +257,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset) #endif break; case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) +#if (CONFIG_FPGA & CFG_SPARTAN3) ret_val = Spartan3_reloc (desc, reloc_offset); #else printf ("%s: No support for Spartan-III devices.\n", @@ -265,7 +265,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset) #endif break; case Xilinx_Virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) +#if (CONFIG_FPGA & CFG_VIRTEX2) ret_val = Virtex2_reloc (desc, reloc_offset); #else printf ("%s: No support for Virtex-II devices.\n", @@ -308,4 +308,4 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn) return ret_val; } -#endif /* CONFIG_FPGA && CONFIG_FPGA_XILINX */ +#endif /* CONFIG_FPGA & CFG_FPGA_XILINX */ diff --git a/common/xyzModem.c b/common/xyzModem.c index a209dfa4a..d1d66e8bb 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -69,157 +69,135 @@ #define BSP 0x08 #define NAK 0x15 #define CAN 0x18 -#define EOF 0x1A /* ^Z for DOS officionados */ +#define EOF 0x1A /* ^Z for DOS officionados */ #define USE_YMODEM_LENGTH /* Data & state local to the protocol */ -static struct -{ +static struct { #ifdef REDBOOT - hal_virtual_comm_table_t *__chan; + hal_virtual_comm_table_t* __chan; #else - int *__chan; + int *__chan; #endif - unsigned char pkt[1024], *bufp; - unsigned char blk, cblk, crc1, crc2; - unsigned char next_blk; /* Expected block */ - int len, mode, total_retries; - int total_SOH, total_STX, total_CAN; - bool crc_mode, at_eof, tx_ack; + unsigned char pkt[1024], *bufp; + unsigned char blk,cblk,crc1,crc2; + unsigned char next_blk; /* Expected block */ + int len, mode, total_retries; + int total_SOH, total_STX, total_CAN; + bool crc_mode, at_eof, tx_ack; #ifdef USE_YMODEM_LENGTH - unsigned long file_length, read_length; + unsigned long file_length, read_length; #endif } xyz; -#define xyzModem_CHAR_TIMEOUT 2000 /* 2 seconds */ +#define xyzModem_CHAR_TIMEOUT 2000 /* 2 seconds */ #define xyzModem_MAX_RETRIES 20 #define xyzModem_MAX_RETRIES_WITH_CRC 10 -#define xyzModem_CAN_COUNT 3 /* Wait for 3 CAN before quitting */ +#define xyzModem_CAN_COUNT 3 /* Wait for 3 CAN before quitting */ -#ifndef REDBOOT /*SB */ +#ifndef REDBOOT /*SB */ typedef int cyg_int32; -int -CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c) -{ +int CYGACC_COMM_IF_GETC_TIMEOUT (char chan,char *c) { #define DELAY 20 - unsigned long counter = 0; - while (!tstc () && (counter < xyzModem_CHAR_TIMEOUT * 1000 / DELAY)) - { - udelay (DELAY); - counter++; - } - if (tstc ()) - { - *c = getc (); - return 1; - } - return 0; + unsigned long counter=0; + while (!tstc() && (counter < xyzModem_CHAR_TIMEOUT*1000/DELAY)) { + udelay(DELAY); + counter++; + } + if (tstc()) { + *c=getc(); + return 1; + } + return 0; } -void -CYGACC_COMM_IF_PUTC (char x, char y) -{ - putc (y); +void CYGACC_COMM_IF_PUTC(char x,char y) { + putc(y); } /* Validate a hex character */ __inline__ static bool -_is_hex (char c) +_is_hex(char c) { - return (((c >= '0') && (c <= '9')) || - ((c >= 'A') && (c <= 'F')) || ((c >= 'a') && (c <= 'f'))); + return (((c >= '0') && (c <= '9')) || + ((c >= 'A') && (c <= 'F')) || + ((c >= 'a') && (c <= 'f'))); } /* Convert a single hex nibble */ __inline__ static int -_from_hex (char c) +_from_hex(char c) { - int ret = 0; + int ret = 0; - if ((c >= '0') && (c <= '9')) - { - ret = (c - '0'); + if ((c >= '0') && (c <= '9')) { + ret = (c - '0'); + } else if ((c >= 'a') && (c <= 'f')) { + ret = (c - 'a' + 0x0a); + } else if ((c >= 'A') && (c <= 'F')) { + ret = (c - 'A' + 0x0A); } - else if ((c >= 'a') && (c <= 'f')) - { - ret = (c - 'a' + 0x0a); - } - else if ((c >= 'A') && (c <= 'F')) - { - ret = (c - 'A' + 0x0A); - } - return ret; + return ret; } /* Convert a character to lower case */ __inline__ static char -_tolower (char c) +_tolower(char c) { - if ((c >= 'A') && (c <= 'Z')) - { - c = (c - 'A') + 'a'; + if ((c >= 'A') && (c <= 'Z')) { + c = (c - 'A') + 'a'; } - return c; + return c; } /* Parse (scan) a number */ bool -parse_num (char *s, unsigned long *val, char **es, char *delim) +parse_num(char *s, unsigned long *val, char **es, char *delim) { - bool first = true; - int radix = 10; - char c; - unsigned long result = 0; - int digit; + bool first = true; + int radix = 10; + char c; + unsigned long result = 0; + int digit; - while (*s == ' ') - s++; - while (*s) - { - if (first && (s[0] == '0') && (_tolower (s[1]) == 'x')) - { - radix = 16; - s += 2; - } - first = false; - c = *s++; - if (_is_hex (c) && ((digit = _from_hex (c)) < radix)) - { - /* Valid digit */ + while (*s == ' ') s++; + while (*s) { + if (first && (s[0] == '0') && (_tolower(s[1]) == 'x')) { + radix = 16; + s += 2; + } + first = false; + c = *s++; + if (_is_hex(c) && ((digit = _from_hex(c)) < radix)) { + /* Valid digit */ #ifdef CYGPKG_HAL_MIPS - /* FIXME: tx49 compiler generates 0x2539018 for MUL which */ - /* isn't any good. */ - if (16 == radix) - result = result << 4; - else - result = 10 * result; - result += digit; + /* FIXME: tx49 compiler generates 0x2539018 for MUL which */ + /* isn't any good. */ + if (16 == radix) + result = result << 4; + else + result = 10 * result; + result += digit; #else - result = (result * radix) + digit; + result = (result * radix) + digit; #endif - } - else - { - if (delim != (char *) 0) - { - /* See if this character is one of the delimiters */ - char *dp = delim; - while (*dp && (c != *dp)) - dp++; - if (*dp) - break; /* Found a good delimiter */ - } - return false; /* Malformatted number */ - } + } else { + if (delim != (char *)0) { + /* See if this character is one of the delimiters */ + char *dp = delim; + while (*dp && (c != *dp)) dp++; + if (*dp) break; /* Found a good delimiter */ + } + return false; /* Malformatted number */ + } } - *val = result; - if (es != (char **) 0) - { - *es = s; + *val = result; + if (es != (char **)0) { + *es = s; } - return true; + return true; } #endif @@ -233,26 +211,24 @@ parse_num (char *s, unsigned long *val, char **es, char *delim) * messages. */ static int -zm_dprintf (char *fmt, ...) +zm_dprintf(char *fmt, ...) { - int cur_console; - va_list args; + int cur_console; + va_list args; - va_start (args, fmt); + va_start(args, fmt); #ifdef REDBOOT - cur_console = - CYGACC_CALL_IF_SET_CONSOLE_COMM - (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); - CYGACC_CALL_IF_SET_CONSOLE_COMM (1); + cur_console = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + CYGACC_CALL_IF_SET_CONSOLE_COMM(1); #endif - diag_vprintf (fmt, args); + diag_vprintf(fmt, args); #ifdef REDBOOT - CYGACC_CALL_IF_SET_CONSOLE_COMM (cur_console); + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur_console); #endif } static void -zm_flush (void) +zm_flush(void) { } @@ -262,43 +238,42 @@ zm_flush (void) */ #define FINAL #ifdef FINAL -static char *zm_out = (char *) 0x00380000; -static char *zm_out_start = (char *) 0x00380000; +static char *zm_out = (char *)0x00380000; +static char *zm_out_start = (char *)0x00380000; #else static char zm_buf[8192]; -static char *zm_out = zm_buf; +static char *zm_out=zm_buf; static char *zm_out_start = zm_buf; #endif static int -zm_dprintf (char *fmt, ...) +zm_dprintf(char *fmt, ...) { - int len; - va_list args; + int len; + va_list args; - va_start (args, fmt); - len = diag_vsprintf (zm_out, fmt, args); - zm_out += len; - return len; + va_start(args, fmt); + len = diag_vsprintf(zm_out, fmt, args); + zm_out += len; + return len; } static void -zm_flush (void) +zm_flush(void) { #ifdef REDBOOT - char *p = zm_out_start; - while (*p) - mon_write_char (*p++); + char *p = zm_out_start; + while (*p) mon_write_char(*p++); #endif - zm_out = zm_out_start; + zm_out = zm_out_start; } #endif static void -zm_dump_buf (void *buf, int len) +zm_dump_buf(void *buf, int len) { #ifdef REDBOOT - diag_vdump_buf_with_offset (zm_dprintf, buf, len, 0); + diag_vdump_buf_with_offset(zm_dprintf, buf, len, 0); #else #endif @@ -308,22 +283,22 @@ static unsigned char zm_buf[2048]; static unsigned char *zm_bp; static void -zm_new (void) +zm_new(void) { - zm_bp = zm_buf; + zm_bp = zm_buf; } static void -zm_save (unsigned char c) +zm_save(unsigned char c) { - *zm_bp++ = c; + *zm_bp++ = c; } static void -zm_dump (int line) +zm_dump(int line) { - zm_dprintf ("Packet at line: %d\n", line); - zm_dump_buf (zm_buf, zm_bp - zm_buf); + zm_dprintf("Packet at line: %d\n", line); + zm_dump_buf(zm_buf, zm_bp-zm_buf); } #define ZM_DEBUG(x) x @@ -333,517 +308,439 @@ zm_dump (int line) /* Wait for the line to go idle */ static void -xyzModem_flush (void) +xyzModem_flush(void) { - int res; - char c; - while (true) - { - res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, &c); - if (!res) - return; + int res; + char c; + while (true) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c); + if (!res) return; } } static int -xyzModem_get_hdr (void) +xyzModem_get_hdr(void) { - char c; - int res; - bool hdr_found = false; - int i, can_total, hdr_chars; - unsigned short cksum; + char c; + int res; + bool hdr_found = false; + int i, can_total, hdr_chars; + unsigned short cksum; - ZM_DEBUG (zm_new ()); - /* Find the start of a header */ - can_total = 0; - hdr_chars = 0; + ZM_DEBUG(zm_new()); + /* Find the start of a header */ + can_total = 0; + hdr_chars = 0; - if (xyz.tx_ack) - { - CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK); - xyz.tx_ack = false; + if (xyz.tx_ack) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + xyz.tx_ack = false; } - while (!hdr_found) - { - res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, &c); - ZM_DEBUG (zm_save (c)); - if (res) - { - hdr_chars++; - switch (c) - { - case SOH: - xyz.total_SOH++; - case STX: - if (c == STX) - xyz.total_STX++; - hdr_found = true; - break; - case CAN: - xyz.total_CAN++; - ZM_DEBUG (zm_dump (__LINE__)); - if (++can_total == xyzModem_CAN_COUNT) - { - return xyzModem_cancel; - } - else - { - /* Wait for multiple CAN to avoid early quits */ - break; - } - case EOT: - /* EOT only supported if no noise */ - if (hdr_chars == 1) - { - CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK); - ZM_DEBUG (zm_dprintf ("ACK on EOT #%d\n", __LINE__)); - ZM_DEBUG (zm_dump (__LINE__)); - return xyzModem_eof; - } - default: - /* Ignore, waiting for start of header */ - ; - } - } - else - { - /* Data stream timed out */ - xyzModem_flush (); /* Toss any current input */ - ZM_DEBUG (zm_dump (__LINE__)); - CYGACC_CALL_IF_DELAY_US ((cyg_int32) 250000); - return xyzModem_timeout; - } + while (!hdr_found) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c); + ZM_DEBUG(zm_save(c)); + if (res) { + hdr_chars++; + switch (c) { + case SOH: + xyz.total_SOH++; + case STX: + if (c == STX) xyz.total_STX++; + hdr_found = true; + break; + case CAN: + xyz.total_CAN++; + ZM_DEBUG(zm_dump(__LINE__)); + if (++can_total == xyzModem_CAN_COUNT) { + return xyzModem_cancel; + } else { + /* Wait for multiple CAN to avoid early quits */ + break; + } + case EOT: + /* EOT only supported if no noise */ + if (hdr_chars == 1) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + ZM_DEBUG(zm_dprintf("ACK on EOT #%d\n", __LINE__)); + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_eof; + } + default: + /* Ignore, waiting for start of header */ + ; + } + } else { + /* Data stream timed out */ + xyzModem_flush(); /* Toss any current input */ + ZM_DEBUG(zm_dump(__LINE__)); + CYGACC_CALL_IF_DELAY_US((cyg_int32)250000); + return xyzModem_timeout; + } } - /* Header found, now read the data */ - res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.blk); - ZM_DEBUG (zm_save (xyz.blk)); - if (!res) - { - ZM_DEBUG (zm_dump (__LINE__)); - return xyzModem_timeout; + /* Header found, now read the data */ + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.blk); + ZM_DEBUG(zm_save(xyz.blk)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; } - res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.cblk); - ZM_DEBUG (zm_save (xyz.cblk)); - if (!res) - { - ZM_DEBUG (zm_dump (__LINE__)); - return xyzModem_timeout; + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.cblk); + ZM_DEBUG(zm_save(xyz.cblk)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; } - xyz.len = (c == SOH) ? 128 : 1024; - xyz.bufp = xyz.pkt; - for (i = 0; i < xyz.len; i++) - { - res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, &c); - ZM_DEBUG (zm_save (c)); - if (res) - { - xyz.pkt[i] = c; - } - else - { - ZM_DEBUG (zm_dump (__LINE__)); - return xyzModem_timeout; - } + xyz.len = (c == SOH) ? 128 : 1024; + xyz.bufp = xyz.pkt; + for (i = 0; i < xyz.len; i++) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c); + ZM_DEBUG(zm_save(c)); + if (res) { + xyz.pkt[i] = c; + } else { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } } - res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.crc1); - ZM_DEBUG (zm_save (xyz.crc1)); - if (!res) - { - ZM_DEBUG (zm_dump (__LINE__)); - return xyzModem_timeout; + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.crc1); + ZM_DEBUG(zm_save(xyz.crc1)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; } - if (xyz.crc_mode) - { - res = CYGACC_COMM_IF_GETC_TIMEOUT (*xyz.__chan, (char *) &xyz.crc2); - ZM_DEBUG (zm_save (xyz.crc2)); - if (!res) - { - ZM_DEBUG (zm_dump (__LINE__)); - return xyzModem_timeout; - } + if (xyz.crc_mode) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, (char *)&xyz.crc2); + ZM_DEBUG(zm_save(xyz.crc2)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } } - ZM_DEBUG (zm_dump (__LINE__)); - /* Validate the message */ - if ((xyz.blk ^ xyz.cblk) != (unsigned char) 0xFF) - { - ZM_DEBUG (zm_dprintf - ("Framing error - blk: %x/%x/%x\n", xyz.blk, xyz.cblk, - (xyz.blk ^ xyz.cblk))); - ZM_DEBUG (zm_dump_buf (xyz.pkt, xyz.len)); - xyzModem_flush (); - return xyzModem_frame; + ZM_DEBUG(zm_dump(__LINE__)); + /* Validate the message */ + if ((xyz.blk ^ xyz.cblk) != (unsigned char)0xFF) { + ZM_DEBUG(zm_dprintf("Framing error - blk: %x/%x/%x\n", xyz.blk, xyz.cblk, (xyz.blk ^ xyz.cblk))); + ZM_DEBUG(zm_dump_buf(xyz.pkt, xyz.len)); + xyzModem_flush(); + return xyzModem_frame; } - /* Verify checksum/CRC */ - if (xyz.crc_mode) - { - cksum = cyg_crc16 (xyz.pkt, xyz.len); - if (cksum != ((xyz.crc1 << 8) | xyz.crc2)) - { - ZM_DEBUG (zm_dprintf ("CRC error - recvd: %02x%02x, computed: %x\n", - xyz.crc1, xyz.crc2, cksum & 0xFFFF)); - return xyzModem_cksum; - } + /* Verify checksum/CRC */ + if (xyz.crc_mode) { + cksum = cyg_crc16(xyz.pkt, xyz.len); + if (cksum != ((xyz.crc1 << 8) | xyz.crc2)) { + ZM_DEBUG(zm_dprintf("CRC error - recvd: %02x%02x, computed: %x\n", + xyz.crc1, xyz.crc2, cksum & 0xFFFF)); + return xyzModem_cksum; + } + } else { + cksum = 0; + for (i = 0; i < xyz.len; i++) { + cksum += xyz.pkt[i]; + } + if (xyz.crc1 != (cksum & 0xFF)) { + ZM_DEBUG(zm_dprintf("Checksum error - recvd: %x, computed: %x\n", xyz.crc1, cksum & 0xFF)); + return xyzModem_cksum; + } } - else - { - cksum = 0; - for (i = 0; i < xyz.len; i++) - { - cksum += xyz.pkt[i]; - } - if (xyz.crc1 != (cksum & 0xFF)) - { - ZM_DEBUG (zm_dprintf - ("Checksum error - recvd: %x, computed: %x\n", xyz.crc1, - cksum & 0xFF)); - return xyzModem_cksum; - } - } - /* If we get here, the message passes [structural] muster */ - return 0; + /* If we get here, the message passes [structural] muster */ + return 0; } int -xyzModem_stream_open (connection_info_t * info, int *err) +xyzModem_stream_open(connection_info_t *info, int *err) { #ifdef REDBOOT - int console_chan; + int console_chan; #endif - int stat = 0; - int retries = xyzModem_MAX_RETRIES; - int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC; + int stat = 0; + int retries = xyzModem_MAX_RETRIES; + int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC; /* ZM_DEBUG(zm_out = zm_out_start); */ #ifdef xyzModem_zmodem - if (info->mode == xyzModem_zmodem) - { - *err = xyzModem_noZmodem; - return -1; + if (info->mode == xyzModem_zmodem) { + *err = xyzModem_noZmodem; + return -1; } #endif #ifdef REDBOOT - /* Set up the I/O channel. Note: this allows for using a different port in the future */ - console_chan = - CYGACC_CALL_IF_SET_CONSOLE_COMM - (CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); - if (info->chan >= 0) - { - CYGACC_CALL_IF_SET_CONSOLE_COMM (info->chan); + /* Set up the I/O channel. Note: this allows for using a different port in the future */ + console_chan = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + if (info->chan >= 0) { + CYGACC_CALL_IF_SET_CONSOLE_COMM(info->chan); + } else { + CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan); } - else - { - CYGACC_CALL_IF_SET_CONSOLE_COMM (console_chan); - } - xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS (); + xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS(); - CYGACC_CALL_IF_SET_CONSOLE_COMM (console_chan); - CYGACC_COMM_IF_CONTROL (*xyz.__chan, __COMMCTL_SET_TIMEOUT, - xyzModem_CHAR_TIMEOUT); + CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan); + CYGACC_COMM_IF_CONTROL(*xyz.__chan, __COMMCTL_SET_TIMEOUT, xyzModem_CHAR_TIMEOUT); #else /* TODO: CHECK ! */ - int dummy; - xyz.__chan = &dummy; + int dummy; + xyz.__chan=&dummy; #endif - xyz.len = 0; - xyz.crc_mode = true; - xyz.at_eof = false; - xyz.tx_ack = false; - xyz.mode = info->mode; - xyz.total_retries = 0; - xyz.total_SOH = 0; - xyz.total_STX = 0; - xyz.total_CAN = 0; + xyz.len = 0; + xyz.crc_mode = true; + xyz.at_eof = false; + xyz.tx_ack = false; + xyz.mode = info->mode; + xyz.total_retries = 0; + xyz.total_SOH = 0; + xyz.total_STX = 0; + xyz.total_CAN = 0; #ifdef USE_YMODEM_LENGTH - xyz.read_length = 0; - xyz.file_length = 0; + xyz.read_length = 0; + xyz.file_length = 0; #endif - CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); + CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); - if (xyz.mode == xyzModem_xmodem) - { - /* X-modem doesn't have an information header - exit here */ - xyz.next_blk = 1; - return 0; + if (xyz.mode == xyzModem_xmodem) { + /* X-modem doesn't have an information header - exit here */ + xyz.next_blk = 1; + return 0; } - while (retries-- > 0) - { - stat = xyzModem_get_hdr (); - if (stat == 0) - { - /* Y-modem file information header */ - if (xyz.blk == 0) - { + while (retries-- > 0) { + stat = xyzModem_get_hdr(); + if (stat == 0) { + /* Y-modem file information header */ + if (xyz.blk == 0) { #ifdef USE_YMODEM_LENGTH - /* skip filename */ - while (*xyz.bufp++); - /* get the length */ - parse_num ((char *) xyz.bufp, &xyz.file_length, NULL, " "); + /* skip filename */ + while (*xyz.bufp++); + /* get the length */ + parse_num((char *)xyz.bufp, &xyz.file_length, NULL, " "); #endif - /* The rest of the file name data block quietly discarded */ - xyz.tx_ack = true; - } - xyz.next_blk = 1; - xyz.len = 0; - return 0; - } - else if (stat == xyzModem_timeout) - { - if (--crc_retries <= 0) - xyz.crc_mode = false; - CYGACC_CALL_IF_DELAY_US (5 * 100000); /* Extra delay for startup */ - CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); - xyz.total_retries++; - ZM_DEBUG (zm_dprintf ("NAK (%d)\n", __LINE__)); - } - if (stat == xyzModem_cancel) - { - break; - } + /* The rest of the file name data block quietly discarded */ + xyz.tx_ack = true; + } + xyz.next_blk = 1; + xyz.len = 0; + return 0; + } else + if (stat == xyzModem_timeout) { + if (--crc_retries <= 0) xyz.crc_mode = false; + CYGACC_CALL_IF_DELAY_US(5*100000); /* Extra delay for startup */ + CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); + xyz.total_retries++; + ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__)); + } + if (stat == xyzModem_cancel) { + break; + } } - *err = stat; - ZM_DEBUG (zm_flush ()); - return -1; + *err = stat; + ZM_DEBUG(zm_flush()); + return -1; } int -xyzModem_stream_read (char *buf, int size, int *err) +xyzModem_stream_read(char *buf, int size, int *err) { - int stat, total, len; - int retries; + int stat, total, len; + int retries; - total = 0; - stat = xyzModem_cancel; - /* Try and get 'size' bytes into the buffer */ - while (!xyz.at_eof && (size > 0)) - { - if (xyz.len == 0) - { - retries = xyzModem_MAX_RETRIES; - while (retries-- > 0) - { - stat = xyzModem_get_hdr (); - if (stat == 0) - { - if (xyz.blk == xyz.next_blk) - { - xyz.tx_ack = true; - ZM_DEBUG (zm_dprintf - ("ACK block %d (%d)\n", xyz.blk, __LINE__)); - xyz.next_blk = (xyz.next_blk + 1) & 0xFF; + total = 0; + stat = xyzModem_cancel; + /* Try and get 'size' bytes into the buffer */ + while (!xyz.at_eof && (size > 0)) { + if (xyz.len == 0) { + retries = xyzModem_MAX_RETRIES; + while (retries-- > 0) { + stat = xyzModem_get_hdr(); + if (stat == 0) { + if (xyz.blk == xyz.next_blk) { + xyz.tx_ack = true; + ZM_DEBUG(zm_dprintf("ACK block %d (%d)\n", xyz.blk, __LINE__)); + xyz.next_blk = (xyz.next_blk + 1) & 0xFF; #if defined(xyzModem_zmodem) || defined(USE_YMODEM_LENGTH) - if (xyz.mode == xyzModem_xmodem || xyz.file_length == 0) - { + if (xyz.mode == xyzModem_xmodem || xyz.file_length == 0) { #else - if (1) - { + if (1) { #endif - /* Data blocks can be padded with ^Z (EOF) characters */ - /* This code tries to detect and remove them */ - if ((xyz.bufp[xyz.len - 1] == EOF) && - (xyz.bufp[xyz.len - 2] == EOF) && - (xyz.bufp[xyz.len - 3] == EOF)) - { - while (xyz.len - && (xyz.bufp[xyz.len - 1] == EOF)) - { - xyz.len--; - } - } - } + /* Data blocks can be padded with ^Z (EOF) characters */ + /* This code tries to detect and remove them */ + if ((xyz.bufp[xyz.len-1] == EOF) && + (xyz.bufp[xyz.len-2] == EOF) && + (xyz.bufp[xyz.len-3] == EOF)) { + while (xyz.len && (xyz.bufp[xyz.len-1] == EOF)) { + xyz.len--; + } + } + } #ifdef USE_YMODEM_LENGTH - /* - * See if accumulated length exceeds that of the file. - * If so, reduce size (i.e., cut out pad bytes) - * Only do this for Y-modem (and Z-modem should it ever - * be supported since it can fall back to Y-modem mode). - */ - if (xyz.mode != xyzModem_xmodem && 0 != xyz.file_length) - { - xyz.read_length += xyz.len; - if (xyz.read_length > xyz.file_length) - { - xyz.len -= (xyz.read_length - xyz.file_length); - } - } + /* + * See if accumulated length exceeds that of the file. + * If so, reduce size (i.e., cut out pad bytes) + * Only do this for Y-modem (and Z-modem should it ever + * be supported since it can fall back to Y-modem mode). + */ + if (xyz.mode != xyzModem_xmodem && 0 != xyz.file_length) { + xyz.read_length += xyz.len; + if (xyz.read_length > xyz.file_length) { + xyz.len -= (xyz.read_length - xyz.file_length); + } + } #endif - break; - } - else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF)) - { - /* Just re-ACK this so sender will get on with it */ - CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK); - continue; /* Need new header */ - } - else - { - stat = xyzModem_sequence; - } - } - if (stat == xyzModem_cancel) - { - break; - } - if (stat == xyzModem_eof) - { - CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK); - ZM_DEBUG (zm_dprintf ("ACK (%d)\n", __LINE__)); - if (xyz.mode == xyzModem_ymodem) - { - CYGACC_COMM_IF_PUTC (*xyz.__chan, - (xyz.crc_mode ? 'C' : NAK)); - xyz.total_retries++; - ZM_DEBUG (zm_dprintf ("Reading Final Header\n")); - stat = xyzModem_get_hdr (); - CYGACC_COMM_IF_PUTC (*xyz.__chan, ACK); - ZM_DEBUG (zm_dprintf ("FINAL ACK (%d)\n", __LINE__)); - } - xyz.at_eof = true; - break; - } - CYGACC_COMM_IF_PUTC (*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); - xyz.total_retries++; - ZM_DEBUG (zm_dprintf ("NAK (%d)\n", __LINE__)); - } - if (stat < 0) - { - *err = stat; - xyz.len = -1; - return total; - } - } - /* Don't "read" data from the EOF protocol package */ - if (!xyz.at_eof) - { - len = xyz.len; - if (size < len) - len = size; - memcpy (buf, xyz.bufp, len); - size -= len; - buf += len; - total += len; - xyz.len -= len; - xyz.bufp += len; - } + break; + } else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF)) { + /* Just re-ACK this so sender will get on with it */ + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + continue; /* Need new header */ + } else { + stat = xyzModem_sequence; + } + } + if (stat == xyzModem_cancel) { + break; + } + if (stat == xyzModem_eof) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + ZM_DEBUG(zm_dprintf("ACK (%d)\n", __LINE__)); + if (xyz.mode == xyzModem_ymodem) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); + xyz.total_retries++; + ZM_DEBUG(zm_dprintf("Reading Final Header\n")); + stat = xyzModem_get_hdr(); + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + ZM_DEBUG(zm_dprintf("FINAL ACK (%d)\n", __LINE__)); + } + xyz.at_eof = true; + break; + } + CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); + xyz.total_retries++; + ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__)); + } + if (stat < 0) { + *err = stat; + xyz.len = -1; + return total; + } + } + /* Don't "read" data from the EOF protocol package */ + if (!xyz.at_eof) { + len = xyz.len; + if (size < len) len = size; + memcpy(buf, xyz.bufp, len); + size -= len; + buf += len; + total += len; + xyz.len -= len; + xyz.bufp += len; + } } - return total; + return total; } void -xyzModem_stream_close (int *err) +xyzModem_stream_close(int *err) { - diag_printf - ("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n", - xyz.crc_mode ? "CRC" : "Cksum", xyz.total_SOH, xyz.total_STX, - xyz.total_CAN, xyz.total_retries); - ZM_DEBUG (zm_flush ()); + diag_printf("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n", + xyz.crc_mode ? "CRC" : "Cksum", + xyz.total_SOH, xyz.total_STX, xyz.total_CAN, + xyz.total_retries); + ZM_DEBUG(zm_flush()); } /* Need to be able to clean out the input buffer, so have to take the */ /* getc */ -void -xyzModem_stream_terminate (bool abort, int (*getc) (void)) +void xyzModem_stream_terminate(bool abort, int (*getc)(void)) { int c; - if (abort) - { - ZM_DEBUG (zm_dprintf ("!!!! TRANSFER ABORT !!!!\n")); - switch (xyz.mode) - { + if (abort) { + ZM_DEBUG(zm_dprintf("!!!! TRANSFER ABORT !!!!\n")); + switch (xyz.mode) { case xyzModem_xmodem: case xyzModem_ymodem: /* The X/YMODEM Spec seems to suggest that multiple CAN followed by an equal */ /* number of Backspaces is a friendly way to get the other end to abort. */ - CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN); - CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN); - CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN); - CYGACC_COMM_IF_PUTC (*xyz.__chan, CAN); - CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP); - CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP); - CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP); - CYGACC_COMM_IF_PUTC (*xyz.__chan, BSP); + CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); + CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); + CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); + CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); /* Now consume the rest of what's waiting on the line. */ - ZM_DEBUG (zm_dprintf ("Flushing serial line.\n")); - xyzModem_flush (); - xyz.at_eof = true; - break; + ZM_DEBUG(zm_dprintf("Flushing serial line.\n")); + xyzModem_flush(); + xyz.at_eof = true; + break; #ifdef xyzModem_zmodem case xyzModem_zmodem: /* Might support it some day I suppose. */ #endif - break; - } - } - else - { - ZM_DEBUG (zm_dprintf ("Engaging cleanup mode...\n")); + break; + } + } else { + ZM_DEBUG(zm_dprintf("Engaging cleanup mode...\n")); /* * Consume any trailing crap left in the inbuffer from * previous recieved blocks. Since very few files are an exact multiple * of the transfer block size, there will almost always be some gunk here. * If we don't eat it now, RedBoot will think the user typed it. */ - ZM_DEBUG (zm_dprintf ("Trailing gunk:\n")); - while ((c = (*getc) ()) > -1); - ZM_DEBUG (zm_dprintf ("\n")); + ZM_DEBUG(zm_dprintf("Trailing gunk:\n")); + while ((c = (*getc)()) > -1) ; + ZM_DEBUG(zm_dprintf("\n")); /* * Make a small delay to give terminal programs like minicom * time to get control again after their file transfer program * exits. */ - CYGACC_CALL_IF_DELAY_US ((cyg_int32) 250000); - } + CYGACC_CALL_IF_DELAY_US((cyg_int32)250000); + } } char * -xyzModem_error (int err) +xyzModem_error(int err) { - switch (err) - { + switch (err) { case xyzModem_access: - return "Can't access file"; - break; + return "Can't access file"; + break; case xyzModem_noZmodem: - return "Sorry, zModem not available yet"; - break; + return "Sorry, zModem not available yet"; + break; case xyzModem_timeout: - return "Timed out"; - break; + return "Timed out"; + break; case xyzModem_eof: - return "End of file"; - break; + return "End of file"; + break; case xyzModem_cancel: - return "Cancelled"; - break; + return "Cancelled"; + break; case xyzModem_frame: - return "Invalid framing"; - break; + return "Invalid framing"; + break; case xyzModem_cksum: - return "CRC/checksum error"; - break; + return "CRC/checksum error"; + break; case xyzModem_sequence: - return "Block sequence error"; - break; + return "Block sequence error"; + break; default: - return "Unknown error"; - break; + return "Unknown error"; + break; } } /* * RedBoot interface */ -#if 0 /* SB */ -GETC_IO_FUNCS (xyzModem_io, xyzModem_stream_open, xyzModem_stream_close, - xyzModem_stream_terminate, xyzModem_stream_read, - xyzModem_error); -RedBoot_load (xmodem, xyzModem_io, false, false, xyzModem_xmodem); -RedBoot_load (ymodem, xyzModem_io, false, false, xyzModem_ymodem); +#if 0 /* SB */ +GETC_IO_FUNCS(xyzModem_io, xyzModem_stream_open, xyzModem_stream_close, + xyzModem_stream_terminate, xyzModem_stream_read, xyzModem_error); +RedBoot_load(xmodem, xyzModem_io, false, false, xyzModem_xmodem); +RedBoot_load(ymodem, xyzModem_io, false, false, xyzModem_ymodem); #endif diff --git a/config.mk b/config.mk index 1dac29be5..b59667a83 100644 --- a/config.mk +++ b/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,22 +23,6 @@ ######################################################################### -ifneq ($(OBJTREE),$(SRCTREE)) -ifeq ($(CURDIR),$(SRCTREE)) -dir := -else -dir := $(subst $(SRCTREE)/,,$(CURDIR)) -endif - -obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/) -src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/) - -$(shell mkdir -p $(obj)) -else -obj := -src := -endif - # clean the slate ... PLATFORM_RELFLAGS = PLATFORM_CPPFLAGS = @@ -69,6 +53,28 @@ PLATFORM_CPPFLAGS+= -D__ARM__ endif endif +ifeq ($(ARCH),blackfin) +PLATFORM_CPPFLAGS+= -D__BLACKFIN__ -mno-underscore +endif + +ifdef ARCH +sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules +endif +ifdef CPU +sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules +endif +ifdef SOC +sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk # include SoC specific rules +endif +ifdef VENDOR +BOARDDIR = $(VENDOR)/$(BOARD) +else +BOARDDIR = $(BOARD) +endif +ifdef BOARD +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules +endif + ######################################################################### CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ @@ -100,70 +106,27 @@ CC = $(CROSS_COMPILE)gcc CPP = $(CC) -E AR = $(CROSS_COMPILE)ar NM = $(CROSS_COMPILE)nm -LDR = $(CROSS_COMPILE)ldr STRIP = $(CROSS_COMPILE)strip OBJCOPY = $(CROSS_COMPILE)objcopy OBJDUMP = $(CROSS_COMPILE)objdump RANLIB = $(CROSS_COMPILE)RANLIB -######################################################################### - -# Load generated board configuration -sinclude $(OBJTREE)/include/autoconf.mk - -ifdef ARCH -sinclude $(TOPDIR)/$(ARCH)_config.mk # include architecture dependend rules -endif -ifdef CPU -sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules -endif -ifdef SOC -sinclude $(TOPDIR)/cpu/$(CPU)/$(SOC)/config.mk # include SoC specific rules -endif -ifdef VENDOR -BOARDDIR = $(VENDOR)/$(BOARD) -else -BOARDDIR = $(BOARD) -endif -ifdef BOARD -sinclude $(TOPDIR)/board/$(BOARDDIR)/config.mk # include board specific rules -endif - -######################################################################### - -ifneq (,$(findstring s,$(MAKEFLAGS))) -ARFLAGS = cr -else -ARFLAGS = crv -endif RELFLAGS= $(PLATFORM_RELFLAGS) DBGFLAGS= -g # -DDEBUG OPTFLAGS= -Os #-fomit-frame-pointer ifndef LDSCRIPT #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug -ifeq ($(CONFIG_NAND_U_BOOT),y) -LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds -else LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds endif -endif OBJCFLAGS += --gap-fill=0xff gccincdir := $(shell $(CC) -print-file-name=include) CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ - -D__KERNEL__ -ifneq ($(TEXT_BASE),) -CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -endif - -ifneq ($(OBJTREE),$(SRCTREE)) -CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include -endif - -CPPFLAGS += -I$(TOPDIR)/include -CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ - -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) + -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \ + -I$(TOPDIR)/include \ + -fno-builtin -ffreestanding -nostdinc -isystem \ + $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) ifdef BUILD_TAG CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes \ @@ -172,8 +135,6 @@ else CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes endif -CFLAGS += $(call cc-option,-fno-stack-protector) - # avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9) # this option have to be placed behind -Wall -- that's why it is here ifeq ($(ARCH),nios) @@ -182,9 +143,7 @@ CFLAGS := $(CPPFLAGS) -Wall -Wno-trigraphs endif endif -# $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g -# option to the assembler. -AFLAGS_DEBUG := +AFLAGS_DEBUG := -Wa,-gstabs # turn jbsr into jsr for m68k ifeq ($(ARCH),m68k) @@ -195,10 +154,7 @@ endif AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) -LDFLAGS += -Bstatic -T $(LDSCRIPT) $(PLATFORM_LDFLAGS) -ifneq ($(TEXT_BASE),) -LDFLAGS += -Ttext $(TEXT_BASE) -endif +LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) # Location of a usable BFD library, where we define "usable" as # "built for ${HOST}, supports ${TARGET}". Sensible values are @@ -236,23 +192,11 @@ export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS ######################################################################### -ifndef REMOTE_BUILD - %.s: %.S - $(CPP) $(AFLAGS) -o $@ $< + $(CPP) $(AFLAGS) -o $@ $(CURDIR)/$< %.o: %.S - $(CC) $(AFLAGS) -c -o $@ $< + $(CC) $(AFLAGS) -c -o $@ $(CURDIR)/$< %.o: %.c $(CC) $(CFLAGS) -c -o $@ $< -else - -$(obj)%.s: %.S - $(CPP) $(AFLAGS) -o $@ $< -$(obj)%.o: %.S - $(CC) $(AFLAGS) -c -o $@ $< -$(obj)%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< -endif - ######################################################################### diff --git a/cpu/74xx_7xx/Makefile b/cpu/74xx_7xx/Makefile index fe905f31f..0e10d3a4d 100644 --- a/cpu/74xx_7xx/Makefile +++ b/cpu/74xx_7xx/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2001 # Josh Huber , Mission Critical Linux, Inc. # @@ -26,26 +23,22 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -SOBJS = cache.o kgdb.o io.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o +ASOBJS = cache.o kgdb.o io.o +OBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(ASOBJS) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(ASOBJS) $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S index 3a745cbe0..a793d799d 100644 --- a/cpu/74xx_7xx/cache.S +++ b/cpu/74xx_7xx/cache.S @@ -329,28 +329,14 @@ _GLOBAL(dcache_status) blr /* - * Invalidate L2 cache using L2I and polling L2IP or L2I + * Invalidate L2 cache using L2I and polling L2IP */ _GLOBAL(l2cache_invalidate) sync - mfspr r3, l2cr oris r3, r3, L2CR_L2I@h sync mtspr l2cr, r3 sync - mfspr r3, PVR - sync - rlwinm r3, r3, 16,16,31 - cmpli 0,r3,0x8000 /* 7451, 7441 */ - beq 0,inv_7450 - cmpli 0,r3,0x8001 /* 7455, 7445 */ - beq 0,inv_7450 - cmpli 0,r3,0x8002 /* 7457, 7447 */ - beq 0,inv_7450 - cmpli 0,r3,0x8003 /* 7447A */ - beq 0,inv_7450 - cmpli 0,r3,0x8004 /* 7448 */ - beq 0,inv_7450 invl2: mfspr r3, l2cr andi. r3, r3, L2CR_L2IP @@ -362,11 +348,6 @@ invl2: mtspr l2cr, r3 sync blr -inv_7450: - mfspr r3, l2cr - andis. r3, r3, L2CR_L2I@h - bne inv_7450 - blr /* * Enable L2 cache diff --git a/cpu/74xx_7xx/config.mk b/cpu/74xx_7xx/config.mk index 324f62b83..417d99f33 100644 --- a/cpu/74xx_7xx/config.mk +++ b/cpu/74xx_7xx/config.mk @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring +PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -ffixed-r29 -mstring diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index ea43c9a9b..ca45e17ed 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -44,11 +44,6 @@ #include <74xx_7xx.h> #include -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#endif - #ifdef CONFIG_AMIGAONEG3SE #include "../board/MAI/AmigaOneG3SE/via686.h" #include "../board/MAI/AmigaOneG3SE/memio.h" @@ -106,14 +101,6 @@ get_cpu_type(void) type = CPU_7457; break; - case 0x8003: - type = CPU_7447A; - break; - - case 0x8004: - type = CPU_7448; - break; - default: break; } @@ -165,14 +152,6 @@ int checkcpu (void) str = "MPC7410"; break; - case CPU_7447A: - str = "MPC7447A"; - break; - - case CPU_7448: - str = "MPC7448"; - break; - case CPU_7450: str = "MPC7450"; break; @@ -242,7 +221,7 @@ soft_restart(unsigned long addr) void do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong addr; + ulong addr; /* flush and disable I/D cache */ __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); @@ -277,19 +256,20 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * For the 7400 the TB clock runs at 1/4 the cpu bus speed. */ -#if defined(CONFIG_AMIGAONEG3SE) || defined(CFG_CONFIG_BUS_CLK) +#ifdef CONFIG_AMIGAONEG3SE unsigned long get_tbclk(void) { return (gd->bus_clk / 4); } -#else /* ! CONFIG_AMIGAONEG3SE and !CFG_CONFIG_BUS_CLK*/ +#else /* ! CONFIG_AMIGAONEG3SE */ unsigned long get_tbclk (void) { return CFG_BUS_HZ / 4; } -#endif /* CONFIG_AMIGAONEG3SE or CFG_CONFIG_BUS_CLK*/ +#endif /* CONFIG_AMIGAONEG3SE */ /* ------------------------------------------------------------------------- */ + #if defined(CONFIG_WATCHDOG) #if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx) void @@ -301,20 +281,3 @@ watchdog_reset(void) #endif /* CONFIG_WATCHDOG */ /* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_OF_LIBFDT -void ft_cpu_setup(void *blob, bd_t *bd) -{ - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", bd->bi_busfreq / 4, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); - - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); - - fdt_fixup_ethernet(blob, bd); -} -#endif -/* ------------------------------------------------------------------------- */ diff --git a/cpu/74xx_7xx/cpu_init.c b/cpu/74xx_7xx/cpu_init.c index 1dd1b2cd8..93f180f26 100644 --- a/cpu/74xx_7xx/cpu_init.c +++ b/cpu/74xx_7xx/cpu_init.c @@ -43,8 +43,6 @@ cpu_init_f (void) case CPU_7450: case CPU_7455: case CPU_7457: - case CPU_7447A: - case CPU_7448: /* enable the timebase bit in HID0 */ set_hid0(get_hid0() | 0x4000000); break; diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S index 4f231228c..e838513c1 100644 --- a/cpu/74xx_7xx/kgdb.S +++ b/cpu/74xx_7xx/kgdb.S @@ -31,7 +31,7 @@ #include #include -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) /* * cache flushing routines for kgdb @@ -74,4 +74,4 @@ kgdb_flush_cache_range: SYNC blr -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c index d8c40cea0..2dc510746 100644 --- a/cpu/74xx_7xx/speed.c +++ b/cpu/74xx_7xx/speed.c @@ -31,8 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern unsigned long get_board_bus_clk (void); - static const int hid1_multipliers_x_10[] = { 25, /* 0000 - 2.5x */ 75, /* 0001 - 7.5x */ @@ -52,42 +50,6 @@ static const int hid1_multipliers_x_10[] = { 0 /* 1111 - off */ }; -/* PLL_CFG[0:4] table for cpu 7448/7447A/7455/7457 */ -static const int hid1_74xx_multipliers_x_10[] = { - 115, /* 00000 - 11.5x */ - 170, /* 00001 - 17x */ - 75, /* 00010 - 7.5x */ - 150, /* 00011 - 15x */ - 70, /* 00100 - 7x */ - 180, /* 00101 - 18x */ - 10, /* 00110 - bypass */ - 200, /* 00111 - 20x */ - 20, /* 01000 - 2x */ - 210, /* 01001 - 21x */ - 65, /* 01010 - 6.5x */ - 130, /* 01011 - 13x */ - 85, /* 01100 - 8.5x */ - 240, /* 01101 - 24x */ - 95, /* 01110 - 9.5x */ - 90, /* 01111 - 9x */ - 30, /* 10000 - 3x */ - 105, /* 10001 - 10.5x */ - 55, /* 10010 - 5.5x */ - 110, /* 10011 - 11x */ - 40, /* 10100 - 4x */ - 100, /* 10101 - 10x */ - 50, /* 10110 - 5x */ - 120, /* 10111 - 12x */ - 80, /* 11000 - 8x */ - 140, /* 11001 - 14x */ - 60, /* 11010 - 6x */ - 160, /* 11011 - 16x */ - 135, /* 11100 - 13.5x */ - 280, /* 11101 - 28x */ - 0, /* 11110 - off */ - 125 /* 11111 - 12.5x */ -}; - static const int hid1_fx_multipliers_x_10[] = { 00, /* 0000 - off */ 00, /* 0001 - off */ @@ -127,30 +89,21 @@ int get_clocks (void) { ulong clock = 0; -#ifdef CFG_BUS_CLK - gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */ -#else - gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */ -#endif - /* calculate the clock frequency based upon the CPU type */ switch (get_cpu_type()) { - case CPU_7447A: - case CPU_7448: case CPU_7455: case CPU_7457: /* + * It is assumed that the PLL_EXT line is zero. * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ - clock = (gd->bus_clk / 10) * - hid1_74xx_multipliers_x_10[(get_hid1 () >> 12) & 0x1F]; + clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF]; break; case CPU_750GX: case CPU_750FX: - clock = gd->bus_clk * - hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; + clock = CFG_BUS_CLK * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10; break; case CPU_7450: @@ -167,8 +120,7 @@ int get_clocks (void) * Make sure division is done before multiplication to prevent 32-bit * arithmetic overflows which will cause a negative number */ - clock = (gd->bus_clk / 10) * - hid1_multipliers_x_10[get_hid1 () >> 28]; + clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[get_hid1 () >> 28]; break; case CPU_UNKNOWN: @@ -178,6 +130,7 @@ int get_clocks (void) } gd->cpu_clk = clock; + gd->bus_clk = CFG_BUS_CLK; return (0); } diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index 42b0f72ac..1fc0fe6bc 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -44,8 +44,7 @@ #if !defined(CONFIG_DB64360) && \ !defined(CONFIG_DB64460) && \ - !defined(CONFIG_CPCI750) && \ - !defined(CONFIG_P3Mx) + !defined(CONFIG_CPCI750) #include #endif @@ -125,7 +124,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -143,7 +142,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ @@ -271,7 +270,7 @@ in_flash: * gt-regs BAT can be reused after board_init_f calls * board_early_init_f (EVB only). */ -#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx) +#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) /* enable address translation */ bl enable_addr_trans sync @@ -316,7 +315,7 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 -#ifdef CONFIG_HIGH_BATS +#ifdef CONFIG_750FX mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 @@ -327,7 +326,7 @@ invalidate_bats: mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 -#ifdef CONFIG_HIGH_BATS +#ifdef CONFIG_750FX mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 @@ -414,7 +413,7 @@ setup_bats: mtspr DBAT3U, r3 isync -#ifdef CONFIG_HIGH_BATS +#ifdef CONFIG_750FX /* IBAT 4 */ addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l @@ -758,8 +757,7 @@ in_ram: defined(CONFIG_DB64360) || \ defined(CONFIG_DB64460) || \ defined(CONFIG_CPCI750) || \ - defined(CONFIG_PPMC7XX) || \ - defined(CONFIG_P3Mx) + defined(CONFIG_PPMC7XX) mr r4, r9 /* Use RAM copy of the global data */ #endif bl after_reloc diff --git a/cpu/74xx_7xx/traps.c b/cpu/74xx_7xx/traps.c index b06622769..50c5eeb48 100644 --- a/cpu/74xx_7xx/traps.c +++ b/cpu/74xx_7xx/traps.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -133,7 +133,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -166,7 +166,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -181,7 +181,7 @@ ProgramCheckException(struct pt_regs *regs) unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; int i, j; -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -204,7 +204,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -217,7 +217,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif diff --git a/cpu/arm1136/Makefile b/cpu/arm1136/Makefile index 7701b03bb..203278e9c 100644 --- a/cpu/arm1136/Makefile +++ b/cpu/arm1136/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = cpu.o +OBJS = interrupts.o cpu.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk index 6ab0dd35a..e39e7741c 100644 --- a/cpu/arm1136/config.mk +++ b/cpu/arm1136/config.mk @@ -31,5 +31,4 @@ PLATFORM_CPPFLAGS += -march=armv5 # # ========================================================================= PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) -PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c index c27f8cd58..8e29e0384 100644 --- a/cpu/arm1136/cpu.c +++ b/cpu/arm1136/cpu.c @@ -33,6 +33,9 @@ #include #include +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) +#include +#endif #ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; @@ -44,10 +47,10 @@ static unsigned long read_p15_c1 (void) unsigned long value; __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); return value; } diff --git a/cpu/arm1136/interrupts.c b/cpu/arm1136/interrupts.c new file mode 100644 index 000000000..25ac6906f --- /dev/null +++ b/cpu/arm1136/interrupts.c @@ -0,0 +1,301 @@ +/* + * (C) Copyright 2004 + * Texas Instruments + * Richard Woodruff + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) +# include +#endif + +#include + +#define TIMER_LOAD_VAL 0 + +/* macro to read the 32 bit timer */ +#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR)) + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return(old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) +/* Use the IntegratorCP function from board/integratorcp.c */ +#else + +static ulong timestamp; +static ulong lastinc; + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init (void) +{ + int32_t val; + + /* Start the counter ticking up */ + *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ + val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ + *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */ + + reset_timer_masked(); /* init the timestamp and lastinc value */ + + return(0); +} +/* + * timer without interrupts + */ +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastinc = READ_TIMER; /* capture current incrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (now >= lastinc) /* normal mode (non roll) */ + timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */ + else /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + lastinc = now; + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} +#endif /* !Integrator/CP */ diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 51b664d93..e29de3020 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -30,27 +30,11 @@ #include #include +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) +#include +#endif .globl _start _start: b reset -#ifdef CONFIG_ONENAND_IPL - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - ldr pc, _hang - -_hang: - .word do_hang - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 - .word 0x12345678 /* now 16*4=64 */ -#else ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -67,7 +51,6 @@ _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ -#endif /* CONFIG_ONENAND_IPL */ .global _end_vect _end_vect: @@ -128,10 +111,10 @@ reset: orr r0,r0,#0xd3 msr cpsr,r0 -#ifdef CONFIG_OMAP2420H4 +#if (CONFIG_OMAP24XX) /* Copy vectors to mask ROM indirect addr */ adr r0, _start /* r0 <- current position of code */ - add r0, r0, #4 /* skip reset vector */ + add r0, r0, #4 /* skip reset vector */ mov r2, #64 /* r2 <- size to copy */ add r2, r0, r2 /* r2 <- source end address */ mov r1, #SRAM_OFFSET0 /* build vect addr */ @@ -144,8 +127,13 @@ next: stmia r1!, {r3-r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ bne next /* loop until equal */ +#if !defined(CFG_NAND_BOOT) && !defined(CFG_ONENAND_BOOT) + /* No need to copy/exec the clock code - DPLL adjust already done + * in NAND/oneNAND Boot. + */ bl cpy_clk_code /* put dpll adjust code behind vectors */ -#endif +#endif /* NAND Boot */ +#endif /* 24xx */ /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit @@ -156,9 +144,7 @@ relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ -#ifndef CONFIG_ONENAND_IPL beq stack_setup -#endif /* CONFIG_ONENAND_IPL */ ldr r2, _armboot_start ldr r3, _bss_start @@ -175,36 +161,27 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ -#ifdef CONFIG_ONENAND_IPL - sub sp, r0, #128 /* leave 32 words for abort-stack */ -#else sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ -#endif /* CONFIG_ONENAND_IPL */ + and sp, sp, #~7 /* 8 byte alinged for (ldr/str)d */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ -#ifndef CONFIG_ONENAND_IPL clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l -#endif ldr pc, _start_armboot -#ifdef CONFIG_ONENAND_IPL -_start_armboot: .word start_oneboot -#else _start_armboot: .word start_armboot -#endif /* @@ -243,8 +220,6 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ - -#ifndef CONFIG_ONENAND_IPL /* ************************************************************************* * @@ -357,17 +332,10 @@ cpu_init_crit: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm -#endif /* CONFIG_ONENAND_IPL */ /* * exception handlers */ -#ifdef CONFIG_ONENAND_IPL - .align 5 -do_hang: - ldr sp, _TEXT_BASE /* use 32 words about stack */ - bl hang /* hang and never return */ -#else /* !CONFIG_ONENAND IPL */ .align 5 undefined_instruction: get_bad_stack @@ -431,8 +399,25 @@ fiq: #endif .align 5 -.global arm1136_cache_flush -arm1136_cache_flush: +.global arm_cache_flush +arm_cache_flush: mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache mov pc, lr @ back to caller -#endif /* CONFIG_ONENAND_IPL */ + +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) +/* Use the IntegratorCP function from board/integratorcp/platform.S */ +#else + + .align 5 +.globl reset_cpu +reset_cpu: + ldr r1, rstctl /* get addr for global reset reg */ + mov r3, #0x2 /* full reset pll+mpu */ + str r3, [r1] /* force reset */ + mov r0, r0 +_loop_forever: + b _loop_forever +rstctl: + .word PM_RSTCTRL_WKUP + +#endif diff --git a/cpu/arm720t/Makefile b/cpu/arm720t/Makefile index c97f32963..f273d9299 100644 --- a/cpu/arm720t/Makefile +++ b/cpu/arm720t/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = serial.o serial_netarm.o interrupts.o cpu.o +OBJS = serial.o serial_netarm.o interrupts.o cpu.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 60c1aa90b..a5b6de760 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -73,7 +73,7 @@ int cleanup_before_linux (void) /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; #endif -#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) +#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) @@ -252,7 +252,6 @@ int dcache_status (void) void icache_enable (void) { } -#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */ #else #error No icache/dcache enable/disable functions defined for this CPU type #endif diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 9854016d4..da62502d6 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -36,12 +36,6 @@ #define TIMER_LOAD_VAL 0xffff /* macro to read the 16 bit timer */ #define READ_TIMER (IO_TC1D & 0xffff) - -#ifdef CONFIG_LPC2292 -#undef READ_TIMER -#define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) -#endif - #else #define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE)) #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL)) @@ -60,9 +54,137 @@ static struct _irq_handler IRQ_HANDLER[N_IRQS]; #endif /* CONFIG_S3C4510B */ #ifdef CONFIG_USE_IRQ +/* enable IRQ/FIQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0x80\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else /* CONFIG_USE_IRQ */ +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = + { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26", +"UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26", + "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", + "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32", + "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + void do_irq (struct pt_regs *pt_regs) { -#if defined(CONFIG_S3C4510B) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +#elif defined(CONFIG_S3C4510B) unsigned int pending; while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */ @@ -73,18 +195,11 @@ void do_irq (struct pt_regs *pt_regs) } #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No do_irq() for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - - void (*pfnct)(void); - - pfnct = (void (*)(void))VICVectAddr; - - (*pfnct)(); #else #error do_irq() not defined for this CPU type #endif } -#endif + #ifdef CONFIG_S3C4510B static void default_isr( void *data) { @@ -178,13 +293,6 @@ int interrupt_init (void) /* Start timer */ SET_REG( REG_TMOD, TM0_RUN); -#elif defined(CONFIG_LPC2292) - PUT32(T0IR, 0); /* disable all timer0 interrupts */ - PUT32(T0TCR, 0); /* disable timer0 */ - PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ); - PUT32(T0MCR, 0); - PUT32(T0TC, 0); - PUT32(T0TCR, 1); /* enable timer0 */ #else #error No interrupt_init() defined for this CPU type @@ -201,7 +309,7 @@ int interrupt_init (void) */ -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) void reset_timer (void) { @@ -229,12 +337,7 @@ void udelay (unsigned long usec) tmo += get_timer (0); while (get_timer_masked () < tmo) -#ifdef CONFIG_LPC2292 - /* GJ - not sure whether this is really needed or a misunderstanding */ - __asm__ __volatile__(" nop"); -#else /*NOP*/; -#endif } void reset_timer_masked (void) diff --git a/cpu/arm720t/serial.c b/cpu/arm720t/serial.c index 1b0e147e1..054bab981 100644 --- a/cpu/arm720t/serial.c +++ b/cpu/arm720t/serial.c @@ -123,80 +123,4 @@ serial_puts (const char *s) } } -#elif defined(CONFIG_LPC2292) - -DECLARE_GLOBAL_DATA_PTR; - -#include - -void serial_setbrg (void) -{ - unsigned short divisor = 0; - - switch (gd->baudrate) { - case 1200: divisor = 3072; break; - case 9600: divisor = 384; break; - case 19200: divisor = 192; break; - case 38400: divisor = 96; break; - case 57600: divisor = 64; break; - case 115200: divisor = 32; break; - default: hang (); break; - } - - /* init serial UART0 */ - PUT8(U0LCR, 0); - PUT8(U0IER, 0); - PUT8(U0LCR, 0x80); /* DLAB=1 */ - PUT8(U0DLL, (unsigned char)(divisor & 0x00FF)); - PUT8(U0DLM, (unsigned char)(divisor >> 8)); - PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */ - PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */ -} - -int serial_init (void) -{ - unsigned long pinsel0; - - serial_setbrg (); - - pinsel0 = GET32(PINSEL0); - pinsel0 &= ~(0x00000003); - pinsel0 |= 5; - PUT32(PINSEL0, pinsel0); - - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') - { - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, '\r'); - } - - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, c); -} - -int serial_getc (void) -{ - while((GET8(U0LSR) & 1) == 0); - return GET8(U0RBR); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -/* Test if there is a byte to read */ -int serial_tstc (void) -{ - return (GET8(U0LSR) & 1); -} - -#endif +#endif /* defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) */ diff --git a/cpu/arm720t/serial_netarm.c b/cpu/arm720t/serial_netarm.c index a593cbc32..bc6bf30b6 100644 --- a/cpu/arm720t/serial_netarm.c +++ b/cpu/arm720t/serial_netarm.c @@ -44,7 +44,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* wait until transmitter is ready for another character */ -#define TXWAITRDY(registers) \ +#define TXWAITRDY(registers) \ { \ ulong tmo = get_timer(0) + 1 * CFG_HZ; \ while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \ diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S index 8423e4f68..e66d10944 100644 --- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S @@ -43,11 +43,7 @@ _start: b reset ldr pc, _software_interrupt ldr pc, _prefetch_abort ldr pc, _data_abort -#ifdef CONFIG_LPC2292 - .word 0xB4405F76 /* 2's complement of the checksum of the vectors */ -#else ldr pc, _not_used -#endif ldr pc, _irq ldr pc, _fiq @@ -127,10 +123,6 @@ reset: bl cpu_init_crit #endif -#ifdef CONFIG_LPC2292 - bl lowlevel_init -#endif - #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ @@ -139,7 +131,6 @@ relocate: /* relocate U-Boot to RAM */ beq stack_setup #if TEXT_BASE -#ifndef CONFIG_LPC2292 /* already done in lowlevel_init */ ldr r2, =0x0 /* Relocate the exception vectors */ cmp r1, r2 /* and associated data to address */ ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */ @@ -147,7 +138,6 @@ relocate: /* relocate U-Boot to RAM */ ldmneia r0, {r3-r9} stmneia r2, {r3-r9} adrne r0, _start /* restore r0 */ -#endif /* !CONFIG_LPC2292 */ #endif ldr r2, _armboot_start @@ -216,14 +206,6 @@ SYSCON3: .word 0x80002200 #define CLKCTL_49 0x4 /* 49.152 MHz */ #define CLKCTL_73 0x6 /* 73.728 MHz */ -#elif defined(CONFIG_LPC2292) -PLLCFG_ADR: .word PLLCFG -PLLFEED_ADR: .word PLLFEED -PLLCON_ADR: .word PLLCON -PLLSTAT_ADR: .word PLLSTAT -VPBDIV_ADR: .word VPBDIV -MEMMAP_ADR: .word MEMMAP - #endif cpu_init_crit: @@ -324,50 +306,6 @@ cpu_init_crit: #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific initialisation for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - /* Set-up PLL */ - mov r3, #0xAA - mov r4, #0x55 - /* First disconnect and disable the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x00 - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Set new M and P values */ - ldr r0, PLLCFG_ADR - mov r1, #0x23 /* M=4 and P=2 */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Then enable the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x01 /* PLL enable bit */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Wait for the lock */ - ldr r0, PLLSTAT_ADR - mov r1, #0x400 /* lock bit */ -lock_loop: - ldr r2, [r0] - and r2, r1, r2 - cmp r2, #0 - beq lock_loop - /* And finally connect the PLL */ - ldr r0, PLLCON_ADR - mov r1, #0x03 /* PLL enable bit and connect bit */ - str r1, [r0] - ldr r0, PLLFEED_ADR /* start feed sequence */ - str r3, [r0] - str r4, [r0] /* feed sequence done */ - /* Set-up VPBDIV register */ - ldr r0, VPBDIV_ADR - mov r1, #0x01 /* VPB clock is same as process clock */ - str r1, [r0] #else #error No cpu_init_crit() defined for current CPU type #endif @@ -383,7 +321,6 @@ lock_loop: str r1, [r0] #endif -#ifndef CONFIG_LPC2292 mov ip, lr /* * before relocating, we have to setup RAM timing @@ -392,7 +329,6 @@ lock_loop: */ bl lowlevel_init mov lr, ip -#endif mov pc, lr @@ -601,11 +537,6 @@ reset_cpu: * on external peripherals such as watchdog timers, etc. */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) - .align 5 -.globl reset_cpu -reset_cpu: - mov pc, r0 #else #error No reset_cpu() defined for current CPU type #endif diff --git a/cpu/arm920t/Makefile b/cpu/arm920t/Makefile index e02bc6ac8..8f256e902 100644 --- a/cpu/arm920t/Makefile +++ b/cpu/arm920t/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = cpu.o interrupts.o +OBJS = cpu.o interrupts.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile index ab4c52c8f..aec9cb640 100644 --- a/cpu/arm920t/at91rm9200/Makefile +++ b/cpu/arm920t/at91rm9200/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,22 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(SOC).a +LIB = lib$(SOC).a -COBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ - lxt972.o serial.o usb.o spi.o +OBJS = bcm5221.o dm9161.o ether.o i2c.o interrupts.o \ + lxt972.o serial.o usb_ohci.o SOBJS = lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +all: .depend $(LIB) -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm920t/at91rm9200/bcm5221.c b/cpu/arm920t/at91rm9200/bcm5221.c index b52c61586..6db143562 100644 --- a/cpu/arm920t/at91rm9200/bcm5221.c +++ b/cpu/arm920t/at91rm9200/bcm5221.c @@ -32,7 +32,7 @@ #ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) /* * Name: @@ -227,6 +227,6 @@ unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status) return FALSE; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ #endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/dm9161.c b/cpu/arm920t/at91rm9200/dm9161.c index 1beb6e8ba..4b13c237c 100644 --- a/cpu/arm920t/at91rm9200/dm9161.c +++ b/cpu/arm920t/at91rm9200/dm9161.c @@ -27,7 +27,7 @@ #ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) /* * Name: @@ -95,7 +95,7 @@ UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac) return TRUE; } - if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) { + if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) { /*set MII for 100BaseTX and Half Duplex */ p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) @@ -140,7 +140,7 @@ UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac) at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue); /* set FDX, SPD, Link, INTR masks */ IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK | - DM9161_LINK_MASK | DM9161_INTR_MASK); + DM9161_LINK_MASK | DM9161_INTR_MASK); at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue); at91rm9200_EmacDisableMDIO (p_mac); @@ -174,11 +174,10 @@ UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status) if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value)) return FALSE; - /* Set the Auto_negotiation Advertisement Register */ - /* MII advertising for Next page, 100BaseTxFD and HD, */ - /* 10BaseTFD and HD, IEEE 802.3 */ + /* Set the Auto_negotiation Advertisement Register */ + /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX | - DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; + DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar)) return FALSE; @@ -221,6 +220,6 @@ UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status) return FALSE; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ #endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/ether.c b/cpu/arm920t/at91rm9200/ether.c index f20e07034..67008d0b9 100644 --- a/cpu/arm920t/at91rm9200/ether.c +++ b/cpu/arm920t/at91rm9200/ether.c @@ -50,7 +50,7 @@ typedef struct { #ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) /* alignment as per Errata #11 (64 bytes) is insufficient! */ rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512))); @@ -105,7 +105,7 @@ void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac) * Arguments: * dev - pointer to struct net_device * RegisterAddress - unsigned char - * pInput - pointer to value read from register + * pInput - pointer to value read from register * Return value: * TRUE - if data read successfully */ @@ -134,7 +134,7 @@ UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac, * Arguments: * dev - pointer to struct net_device * RegisterAddress - unsigned char - * pOutput - pointer to value to be written in the register + * pOutput - pointer to value to be written in the register * Return value: * TRUE - if data read successfully */ @@ -265,7 +265,7 @@ void eth_halt (void) { }; -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) int at91rm9200_miiphy_read(char *devname, unsigned char addr, unsigned char reg, unsigned short * value) { @@ -284,16 +284,16 @@ int at91rm9200_miiphy_write(char *devname, unsigned char addr, return 0; } -#endif +#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */ int at91rm9200_miiphy_initialize(bd_t *bis) { -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write); #endif return 0; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ #endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S index 98363eb40..1902bd02c 100644 --- a/cpu/arm920t/at91rm9200/lowlevel_init.S +++ b/cpu/arm920t/at91rm9200/lowlevel_init.S @@ -46,7 +46,7 @@ #define MC_ASR 0xFFFFFF04 #define MC_AASR 0xFFFFFF08 #define EBI_CFGR 0xFFFFFF64 -#define SMC_CSR0 0xFFFFFF70 +#define SMC2_CSR 0xFFFFFF70 /* clocks */ #define PLLAR 0xFFFFFC28 @@ -146,8 +146,8 @@ SMRDATA: .word MC_AASR_VAL .word EBI_CFGR .word EBI_CFGR_VAL - .word SMC_CSR0 - .word SMC_CSR0_VAL + .word SMC2_CSR + .word SMC2_CSR_VAL .word PLLAR .word PLLAR_VAL .word PLLBR diff --git a/cpu/arm920t/at91rm9200/lxt972.c b/cpu/arm920t/at91rm9200/lxt972.c index 260d393cf..f12c59c15 100644 --- a/cpu/arm920t/at91rm9200/lxt972.c +++ b/cpu/arm920t/at91rm9200/lxt972.c @@ -29,12 +29,11 @@ #include #include #include -#include #include #ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) /* * Name: @@ -52,8 +51,8 @@ unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac) unsigned short Id1, Id2; at91rm9200_EmacEnableMDIO (p_mac); - at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1, &Id1); - at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR2, &Id2); + at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID1, &Id1); + at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_ID2, &Id2); at91rm9200_EmacDisableMDIO (p_mac); if ((Id1 == (0x0013)) && ((Id2 & 0xFFF0) == 0x78E0)) @@ -170,23 +169,23 @@ UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status) unsigned short value; /* Set lxt972 control register */ - if (!at91rm9200_EmacReadPhy (p_mac, PHY_BMCR, &value)) + if (!at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_CTRL, &value)) return FALSE; /* Restart Auto_negotiation */ - value |= PHY_BMCR_RST_NEG; - if (!at91rm9200_EmacWritePhy (p_mac, PHY_BMCR, &value)) + value |= PHY_COMMON_CTRL_RES_AUTO; + if (!at91rm9200_EmacWritePhy (p_mac, PHY_COMMON_CTRL, &value)) return FALSE; /*check AutoNegotiate complete */ udelay (10000); - at91rm9200_EmacReadPhy(p_mac, PHY_BMSR, &value); - if (!(value & PHY_BMSR_AUTN_COMP)) + at91rm9200_EmacReadPhy (p_mac, PHY_COMMON_STAT, &value); + if (!(value & PHY_COMMON_STAT_AN_COMP)) return FALSE; return (lxt972_GetLinkSpeed (p_mac)); } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ #endif /* CONFIG_DRIVER_ETHER */ diff --git a/cpu/arm920t/at91rm9200/usb_ohci.c b/cpu/arm920t/at91rm9200/usb_ohci.c new file mode 100644 index 000000000..5b2c56cff --- /dev/null +++ b/cpu/arm920t/at91rm9200/usb_ohci.c @@ -0,0 +1,1635 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200. + * + * (C) Copyright 2003 + * Gary Jennejohn, DENX Software Engineering + * + * Note: Much of this code has been derived from Linux 2.4 + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2002 David Brownell + * + * Modified for the MP2USB by (C) Copyright 2005 Eric Benard + * ebenard@eukrea.com - based on s3c24x0's driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +/* + * IMPORTANT NOTES + * 1 - you MUST define LITTLEENDIAN in the configuration file for the + * board or this driver will NOT work! + * 2 - this driver is intended for use with USB Mass Storage Devices + * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! + * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG + * to activate workaround for bug #41 or this driver will NOT work! + */ + +#include +/* #include no PCI on the S3C24X0 */ + +#ifdef CONFIG_USB_OHCI + +#include + +#include +#include +#include "usb_ohci.h" + +#define OHCI_USE_NPS /* force NoPowerSwitching mode */ +#undef OHCI_VERBOSE_DEBUG /* not always helpful */ + +/* For initializing controller (mask in an HCFS mode too) */ +#define OHCI_CONTROL_INIT \ + (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE + +#define readl(a) (*((vu_long *)(a))) +#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) + +#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) + +#undef DEBUG +#ifdef DEBUG +#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg) +#else +#define dbg(format, arg...) do {} while(0) +#endif /* DEBUG */ +#define err(format, arg...) printf("ERROR: " format "\n", ## arg) +#undef SHOW_INFO +#ifdef SHOW_INFO +#define info(format, arg...) printf("INFO: " format "\n", ## arg) +#else +#define info(format, arg...) do {} while(0) +#endif + +#define m16_swap(x) swap_16(x) +#define m32_swap(x) swap_32(x) + +/* global ohci_t */ +static ohci_t gohci; +/* this must be aligned to a 256 byte boundary */ +struct ohci_hcca ghcca[1]; +/* a pointer to the aligned storage */ +struct ohci_hcca *phcca; +/* this allocates EDs for all possible endpoints */ +struct ohci_device ohci_dev; +/* urb_priv */ +urb_priv_t urb_priv; +/* RHSC flag */ +int got_rhsc; +/* device which was disconnected */ +struct usb_device *devgone; + +/*-------------------------------------------------------------------------*/ + +/* AMD-756 (D2 rev) reports corrupt register contents in some cases. + * The erratum (#4) description is incorrect. AMD's workaround waits + * till some bits (mostly reserved) are clear; ok for all revs. + */ +#define OHCI_QUIRK_AMD756 0xabcd +#define read_roothub(hc, register, mask) ({ \ + u32 temp = readl (&hc->regs->roothub.register); \ + if (hc->flags & OHCI_QUIRK_AMD756) \ + while (temp & mask) \ + temp = readl (&hc->regs->roothub.register); \ + temp; }) + +static u32 roothub_a (struct ohci *hc) + { return read_roothub (hc, a, 0xfc0fe000); } +static inline u32 roothub_b (struct ohci *hc) + { return readl (&hc->regs->roothub.b); } +static inline u32 roothub_status (struct ohci *hc) + { return readl (&hc->regs->roothub.status); } +static u32 roothub_portstatus (struct ohci *hc, int i) + { return read_roothub (hc, portstatus [i], 0xffe0fce0); } + + +/* forward declaration */ +static int hc_interrupt (void); +static void +td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval); + +/*-------------------------------------------------------------------------* + * URB support functions + *-------------------------------------------------------------------------*/ + +/* free HCD-private data associated with this URB */ + +static void urb_free_priv (urb_priv_t * urb) +{ + int i; + int last; + struct td * td; + + last = urb->length - 1; + if (last >= 0) { + for (i = 0; i <= last; i++) { + td = urb->td[i]; + if (td) { + td->usb_dev = NULL; + urb->td[i] = NULL; + } + } + } +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +static int sohci_get_current_frame_number (struct usb_device * dev); + +/* debug| print the main components of an URB + * small: 0) header + data packets 1) just header */ + +static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer, + int transfer_len, struct devrequest * setup, char * str, int small) +{ + urb_priv_t * purb = &urb_priv; + + dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx", + str, + sohci_get_current_frame_number (dev), + usb_pipedevice (pipe), + usb_pipeendpoint (pipe), + usb_pipeout (pipe)? 'O': 'I', + usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"): + (usb_pipecontrol (pipe)? "CTRL": "BULK"), + purb->actual_length, + transfer_len, dev->status); +#ifdef OHCI_VERBOSE_DEBUG + if (!small) { + int i, len; + + if (usb_pipecontrol (pipe)) { + printf (__FILE__ ": cmd(8):"); + for (i = 0; i < 8 ; i++) + printf (" %02x", ((__u8 *) setup) [i]); + printf ("\n"); + } + if (transfer_len > 0 && buffer) { + printf (__FILE__ ": data(%d/%d):", + purb->actual_length, + transfer_len); + len = usb_pipeout (pipe)? + transfer_len: purb->actual_length; + for (i = 0; i < 16 && i < len; i++) + printf (" %02x", ((__u8 *) buffer) [i]); + printf ("%s\n", i < len? "...": ""); + } + } +#endif +} + +/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/ +void ep_print_int_eds (ohci_t *ohci, char * str) { + int i, j; + __u32 * ed_p; + for (i= 0; i < 32; i++) { + j = 5; + ed_p = &(ohci->hcca->int_table [i]); + if (*ed_p == 0) + continue; + printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i); + while (*ed_p != 0 && j--) { + ed_t *ed = (ed_t *)m32_swap(ed_p); + printf (" ed: %4x;", ed->hwINFO); + ed_p = &ed->hwNextED; + } + printf ("\n"); + } +} + +static void ohci_dump_intr_mask (char *label, __u32 mask) +{ + dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s", + label, + mask, + (mask & OHCI_INTR_MIE) ? " MIE" : "", + (mask & OHCI_INTR_OC) ? " OC" : "", + (mask & OHCI_INTR_RHSC) ? " RHSC" : "", + (mask & OHCI_INTR_FNO) ? " FNO" : "", + (mask & OHCI_INTR_UE) ? " UE" : "", + (mask & OHCI_INTR_RD) ? " RD" : "", + (mask & OHCI_INTR_SF) ? " SF" : "", + (mask & OHCI_INTR_WDH) ? " WDH" : "", + (mask & OHCI_INTR_SO) ? " SO" : "" + ); +} + +static void maybe_print_eds (char *label, __u32 value) +{ + ed_t *edp = (ed_t *)value; + + if (value) { + dbg ("%s %08x", label, value); + dbg ("%08x", edp->hwINFO); + dbg ("%08x", edp->hwTailP); + dbg ("%08x", edp->hwHeadP); + dbg ("%08x", edp->hwNextED); + } +} + +static char * hcfs2string (int state) +{ + switch (state) { + case OHCI_USB_RESET: return "reset"; + case OHCI_USB_RESUME: return "resume"; + case OHCI_USB_OPER: return "operational"; + case OHCI_USB_SUSPEND: return "suspend"; + } + return "?"; +} + +/* dump control and status registers */ +static void ohci_dump_status (ohci_t *controller) +{ + struct ohci_regs *regs = controller->regs; + __u32 temp; + + temp = readl (®s->revision) & 0xff; + if (temp != 0x10) + dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f)); + + temp = readl (®s->control); + dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp, + (temp & OHCI_CTRL_RWE) ? " RWE" : "", + (temp & OHCI_CTRL_RWC) ? " RWC" : "", + (temp & OHCI_CTRL_IR) ? " IR" : "", + hcfs2string (temp & OHCI_CTRL_HCFS), + (temp & OHCI_CTRL_BLE) ? " BLE" : "", + (temp & OHCI_CTRL_CLE) ? " CLE" : "", + (temp & OHCI_CTRL_IE) ? " IE" : "", + (temp & OHCI_CTRL_PLE) ? " PLE" : "", + temp & OHCI_CTRL_CBSR + ); + + temp = readl (®s->cmdstatus); + dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp, + (temp & OHCI_SOC) >> 16, + (temp & OHCI_OCR) ? " OCR" : "", + (temp & OHCI_BLF) ? " BLF" : "", + (temp & OHCI_CLF) ? " CLF" : "", + (temp & OHCI_HCR) ? " HCR" : "" + ); + + ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus)); + ohci_dump_intr_mask ("intrenable", readl (®s->intrenable)); + + maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent)); + + maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead)); + maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent)); + + maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead)); + maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent)); + + maybe_print_eds ("donehead", readl (®s->donehead)); +} + +static void ohci_dump_roothub (ohci_t *controller, int verbose) +{ + __u32 temp, ndp, i; + + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); +#ifdef CONFIG_AT91C_PQFP_UHPBUG + ndp = (ndp == 2) ? 1:0; +#endif + if (verbose) { + dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp, + ((temp & RH_A_POTPGT) >> 24) & 0xff, + (temp & RH_A_NOCP) ? " NOCP" : "", + (temp & RH_A_OCPM) ? " OCPM" : "", + (temp & RH_A_DT) ? " DT" : "", + (temp & RH_A_NPS) ? " NPS" : "", + (temp & RH_A_PSM) ? " PSM" : "", + ndp + ); + temp = roothub_b (controller); + dbg ("roothub.b: %08x PPCM=%04x DR=%04x", + temp, + (temp & RH_B_PPCM) >> 16, + (temp & RH_B_DR) + ); + temp = roothub_status (controller); + dbg ("roothub.status: %08x%s%s%s%s%s%s", + temp, + (temp & RH_HS_CRWE) ? " CRWE" : "", + (temp & RH_HS_OCIC) ? " OCIC" : "", + (temp & RH_HS_LPSC) ? " LPSC" : "", + (temp & RH_HS_DRWE) ? " DRWE" : "", + (temp & RH_HS_OCI) ? " OCI" : "", + (temp & RH_HS_LPS) ? " LPS" : "" + ); + } + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s", + i, + temp, + (temp & RH_PS_PRSC) ? " PRSC" : "", + (temp & RH_PS_OCIC) ? " OCIC" : "", + (temp & RH_PS_PSSC) ? " PSSC" : "", + (temp & RH_PS_PESC) ? " PESC" : "", + (temp & RH_PS_CSC) ? " CSC" : "", + + (temp & RH_PS_LSDA) ? " LSDA" : "", + (temp & RH_PS_PPS) ? " PPS" : "", + (temp & RH_PS_PRS) ? " PRS" : "", + (temp & RH_PS_POCI) ? " POCI" : "", + (temp & RH_PS_PSS) ? " PSS" : "", + + (temp & RH_PS_PES) ? " PES" : "", + (temp & RH_PS_CCS) ? " CCS" : "" + ); + } +} + +static void ohci_dump (ohci_t *controller, int verbose) +{ + dbg ("OHCI controller usb-%s state", controller->slot_name); + + /* dumps some of the state we know about */ + ohci_dump_status (controller); + if (verbose) + ep_print_int_eds (controller, "hcca"); + dbg ("hcca frame #%04x", controller->hcca->frame_no); + ohci_dump_roothub (controller, 1); +} + + +#endif /* DEBUG */ + +/*-------------------------------------------------------------------------* + * Interface functions (URB) + *-------------------------------------------------------------------------*/ + +/* get a transfer request */ + +int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + ohci_t *ohci; + ed_t * ed; + urb_priv_t *purb_priv; + int i, size = 0; + + ohci = &gohci; + + /* when controller's hung, permit only roothub cleanup attempts + * such as powering down ports */ + if (ohci->disabled) { + err("sohci_submit_job: EPIPE"); + return -1; + } + + /* every endpoint has a ed, locate and fill it */ + if (!(ed = ep_add_ed (dev, pipe))) { + err("sohci_submit_job: ENOMEM"); + return -1; + } + + /* for the private part of the URB we need the number of TDs (size) */ + switch (usb_pipetype (pipe)) { + case PIPE_BULK: /* one TD for every 4096 Byte */ + size = (transfer_len - 1) / 4096 + 1; + break; + case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */ + size = (transfer_len == 0)? 2: + (transfer_len - 1) / 4096 + 3; + break; + } + + if (size >= (N_URB_TD - 1)) { + err("need %d TDs, only have %d", size, N_URB_TD); + return -1; + } + purb_priv = &urb_priv; + purb_priv->pipe = pipe; + + /* fill the private part of the URB */ + purb_priv->length = size; + purb_priv->ed = ed; + purb_priv->actual_length = 0; + + /* allocate the TDs */ + /* note that td[0] was allocated in ep_add_ed */ + for (i = 0; i < size; i++) { + purb_priv->td[i] = td_alloc (dev); + if (!purb_priv->td[i]) { + purb_priv->length = i; + urb_free_priv (purb_priv); + err("sohci_submit_job: ENOMEM"); + return -1; + } + } + + if (ed->state == ED_NEW || (ed->state & ED_DEL)) { + urb_free_priv (purb_priv); + err("sohci_submit_job: EINVAL"); + return -1; + } + + /* link the ed into a chain if is not already */ + if (ed->state != ED_OPER) + ep_link (ohci, ed); + + /* fill the TDs and link it to the ed */ + td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval); + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEBUG +/* tell us the current USB frame number */ + +static int sohci_get_current_frame_number (struct usb_device *usb_dev) +{ + ohci_t *ohci = &gohci; + + return m16_swap (ohci->hcca->frame_no); +} +#endif + +/*-------------------------------------------------------------------------* + * ED handling functions + *-------------------------------------------------------------------------*/ + +/* link an ed into one of the HC chains */ + +static int ep_link (ohci_t *ohci, ed_t *edi) +{ + volatile ed_t *ed = edi; + + ed->state = ED_OPER; + + switch (ed->type) { + case PIPE_CONTROL: + ed->hwNextED = 0; + if (ohci->ed_controltail == NULL) { + writel (ed, &ohci->regs->ed_controlhead); + } else { + ohci->ed_controltail->hwNextED = m32_swap (ed); + } + ed->ed_prev = ohci->ed_controltail; + if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_controltail = edi; + break; + + case PIPE_BULK: + ed->hwNextED = 0; + if (ohci->ed_bulktail == NULL) { + writel (ed, &ohci->regs->ed_bulkhead); + } else { + ohci->ed_bulktail->hwNextED = m32_swap (ed); + } + ed->ed_prev = ohci->ed_bulktail; + if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && + !ohci->ed_rm_list[1] && !ohci->sleeping) { + ohci->hc_control |= OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + ohci->ed_bulktail = edi; + break; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* unlink an ed from one of the HC chains. + * just the link to the ed is unlinked. + * the link from the ed still points to another operational ed or 0 + * so the HC can eventually finish the processing of the unlinked ed */ + +static int ep_unlink (ohci_t *ohci, ed_t *ed) +{ + ed->hwINFO |= m32_swap (OHCI_ED_SKIP); + + switch (ed->type) { + case PIPE_CONTROL: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_CLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_controltail == ed) { + ohci->ed_controltail = ed->ed_prev; + } else { + ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + + case PIPE_BULK: + if (ed->ed_prev == NULL) { + if (!ed->hwNextED) { + ohci->hc_control &= ~OHCI_CTRL_BLE; + writel (ohci->hc_control, &ohci->regs->control); + } + writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead); + } else { + ed->ed_prev->hwNextED = ed->hwNextED; + } + if (ohci->ed_bulktail == ed) { + ohci->ed_bulktail = ed->ed_prev; + } else { + ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev; + } + break; + } + ed->state = ED_UNLINK; + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +/* add/reinit an endpoint; this should be done once at the usb_set_configuration command, + * but the USB stack is a little bit stateless so we do it at every transaction + * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK + * in all other cases the state is left unchanged + * the ed info fields are setted anyway even though most of them should not change */ + +static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) +{ + td_t *td; + ed_t *ed_ret; + volatile ed_t *ed; + + ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) | + (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))]; + + if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) { + err("ep_add_ed: pending delete"); + /* pending delete request */ + return NULL; + } + + if (ed->state == ED_NEW) { + ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ + /* dummy td; end of td list for ed */ + td = td_alloc (usb_dev); + ed->hwTailP = m32_swap (td); + ed->hwHeadP = ed->hwTailP; + ed->state = ED_UNLINK; + ed->type = usb_pipetype (pipe); + ohci_dev.ed_cnt++; + } + + ed->hwINFO = m32_swap (usb_pipedevice (pipe) + | usb_pipeendpoint (pipe) << 7 + | (usb_pipeisoc (pipe)? 0x8000: 0) + | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000)) + | usb_pipeslow (pipe) << 13 + | usb_maxpacket (usb_dev, pipe) << 16); + + return ed_ret; +} + +/*-------------------------------------------------------------------------* + * TD handling functions + *-------------------------------------------------------------------------*/ + +/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ + +static void td_fill (ohci_t *ohci, unsigned int info, + void *data, int len, + struct usb_device *dev, int index, urb_priv_t *urb_priv) +{ + volatile td_t *td, *td_pt; +#ifdef OHCI_FILL_TRACE + int i; +#endif + + if (index > urb_priv->length) { + err("index > length"); + return; + } + /* use this td as the next dummy */ + td_pt = urb_priv->td [index]; + td_pt->hwNextTD = 0; + + /* fill the old dummy TD */ + td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf); + + td->ed = urb_priv->ed; + td->next_dl_td = NULL; + td->index = index; + td->data = (__u32)data; +#ifdef OHCI_FILL_TRACE + if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) { + for (i = 0; i < len; i++) + printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]); + printf("\n"); + } +#endif + if (!len) + data = 0; + + td->hwINFO = m32_swap (info); + td->hwCBP = m32_swap (data); + if (data) + td->hwBE = m32_swap (data + len - 1); + else + td->hwBE = 0; + td->hwNextTD = m32_swap (td_pt); + td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000); + + /* append to queue */ + td->ed->hwTailP = td->hwNextTD; +} + +/*-------------------------------------------------------------------------*/ + +/* prepare all TDs of a transfer */ + +static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval) +{ + ohci_t *ohci = &gohci; + int data_len = transfer_len; + void *data; + int cnt = 0; + __u32 info = 0; + unsigned int toggle = 0; + + /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */ + if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) { + toggle = TD_T_TOGGLE; + } else { + toggle = TD_T_DATA0; + usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1); + } + urb->td_cnt = 0; + if (data_len) + data = buffer; + else + data = 0; + + switch (usb_pipetype (pipe)) { + case PIPE_BULK: + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ; + while(data_len > 4096) { + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb); + data += 4096; data_len -= 4096; cnt++; + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ; + td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb); + cnt++; + + if (!ohci->sleeping) + writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */ + break; + + case PIPE_CONTROL: + info = TD_CC | TD_DP_SETUP | TD_T_DATA0; + td_fill (ohci, info, setup, 8, dev, cnt++, urb); + if (data_len > 0) { + info = usb_pipeout (pipe)? + TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1; + /* NOTE: mishandles transfers >8K, some >4K */ + td_fill (ohci, info, data, data_len, dev, cnt++, urb); + } + info = usb_pipeout (pipe)? + TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1; + td_fill (ohci, info, data, 0, dev, cnt++, urb); + if (!ohci->sleeping) + writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */ + break; + } + if (urb->length != cnt) + dbg("TD LENGTH %d != CNT %d", urb->length, cnt); +} + +/*-------------------------------------------------------------------------* + * Done List handling functions + *-------------------------------------------------------------------------*/ + + +/* calculate the transfer length and update the urb */ + +static void dl_transfer_length(td_t * td) +{ + __u32 tdINFO, tdBE, tdCBP; + urb_priv_t *lurb_priv = &urb_priv; + + tdINFO = m32_swap (td->hwINFO); + tdBE = m32_swap (td->hwBE); + tdCBP = m32_swap (td->hwCBP); + + + if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL && + ((td->index == 0) || (td->index == lurb_priv->length - 1)))) { + if (tdBE != 0) { + if (td->hwCBP == 0) + lurb_priv->actual_length += tdBE - td->data + 1; + else + lurb_priv->actual_length += tdCBP - td->data; + } + } +} + +/*-------------------------------------------------------------------------*/ + +/* replies to the request have to be on a FIFO basis so + * we reverse the reversed done-list */ + +static td_t * dl_reverse_done_list (ohci_t *ohci) +{ + __u32 td_list_hc; + td_t *td_rev = NULL; + td_t *td_list = NULL; + urb_priv_t *lurb_priv = NULL; + + td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0; + ohci->hcca->done_head = 0; + + while (td_list_hc) { + td_list = (td_t *)td_list_hc; + + if (TD_CC_GET (m32_swap (td_list->hwINFO))) { + lurb_priv = &urb_priv; + dbg(" USB-error/status: %x : %p", + TD_CC_GET (m32_swap (td_list->hwINFO)), td_list); + if (td_list->ed->hwHeadP & m32_swap (0x1)) { + if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) { + td_list->ed->hwHeadP = + (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) | + (td_list->ed->hwHeadP & m32_swap (0x2)); + lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1; + } else + td_list->ed->hwHeadP &= m32_swap (0xfffffff2); + } + } + + td_list->next_dl_td = td_rev; + td_rev = td_list; + td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0; + } + return td_list; +} + +/*-------------------------------------------------------------------------*/ + +/* td done list */ +static int dl_done_list (ohci_t *ohci, td_t *td_list) +{ + td_t *td_list_next = NULL; + ed_t *ed; + int cc = 0; + int stat = 0; + /* urb_t *urb; */ + urb_priv_t *lurb_priv; + __u32 tdINFO, edHeadP, edTailP; + + while (td_list) { + td_list_next = td_list->next_dl_td; + + lurb_priv = &urb_priv; + tdINFO = m32_swap (td_list->hwINFO); + + ed = td_list->ed; + + dl_transfer_length(td_list); + + /* error code of transfer */ + cc = TD_CC_GET (tdINFO); + if (cc != 0) { + dbg("ConditionCode %#x", cc); + stat = cc_to_error[cc]; + } + + if (ed->state != ED_NEW) { + edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0; + edTailP = m32_swap (ed->hwTailP); + + /* unlink eds if they are not busy */ + if ((edHeadP == edTailP) && (ed->state == ED_OPER)) + ep_unlink (ohci, ed); + } + + td_list = td_list_next; + } + return stat; +} + +/*-------------------------------------------------------------------------* + * Virtual Root Hub + *-------------------------------------------------------------------------*/ + +/* Device descriptor */ +static __u8 root_hub_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x01, /* __u8 iProduct; */ + 0x00, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + + +/* Configuration descriptor */ +static __u8 root_hub_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +static unsigned char root_hub_str_index0[] = +{ + 0x04, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 0x09, /* __u8 lang ID */ + 0x04, /* __u8 lang ID */ +}; + +static unsigned char root_hub_str_index1[] = +{ + 28, /* __u8 bLength; */ + 0x03, /* __u8 bDescriptorType; String-descriptor */ + 'O', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'C', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'I', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'R', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'o', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 't', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + ' ', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'H', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'u', /* __u8 Unicode */ + 0, /* __u8 Unicode */ + 'b', /* __u8 Unicode */ + 0, /* __u8 Unicode */ +}; + +/* Hub class-specific descriptor is constructed dynamically */ + + +/*-------------------------------------------------------------------------*/ + +#define OK(x) len = (x); break +#ifdef DEBUG +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} +#else +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#endif +#define RD_RH_STAT roothub_status(&gohci) +#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) + +/* request to virtual root hub */ + +int rh_check_port_status(ohci_t *controller) +{ + __u32 temp, ndp, i; + int res; + + res = -1; + temp = roothub_a (controller); + ndp = (temp & RH_A_NDP); +#ifdef CONFIG_AT91C_PQFP_UHPBUG + ndp = (ndp == 2) ? 1:0; +#endif + + for (i = 0; i < ndp; i++) { + temp = roothub_portstatus (controller, i); + /* check for a device disconnect */ + if (((temp & (RH_PS_PESC | RH_PS_CSC)) == + (RH_PS_PESC | RH_PS_CSC)) && + ((temp & RH_PS_CCS) == 0)) { + res = i; + break; + } + } + return res; +} + +static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int transfer_len, struct devrequest *cmd) +{ + void * data = buffer; + int leni = transfer_len; + int len = 0; + int stat = 0; + __u32 datab[4]; + __u8 *data_buf = (__u8 *)datab; + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + +#ifdef DEBUG +urb_priv.actual_length = 0; +pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + info("Root-Hub submit IRQ: NOT implemented"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = m16_swap (cmd->value); + wIndex = m16_swap (cmd->index); + wLength = m16_swap (cmd->length); + + info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x", + dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength); + + switch (bmRType_bReq) { + /* Request Destination: + without flags: Device, + RH_INTERFACE: interface, + RH_ENDPOINT: endpoint, + RH_CLASS means HUB here, + RH_OTHER | RH_CLASS almost ever means HUB_PORT here + */ + + case RH_GET_STATUS: + *(__u16 *) data_buf = m16_swap (1); OK (2); + case RH_GET_STATUS | RH_INTERFACE: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_ENDPOINT: + *(__u16 *) data_buf = m16_swap (0); OK (2); + case RH_GET_STATUS | RH_CLASS: + *(__u32 *) data_buf = m32_swap ( + RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE)); + OK (4); + case RH_GET_STATUS | RH_OTHER | RH_CLASS: + *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4); + + case RH_CLEAR_FEATURE | RH_ENDPOINT: + switch (wValue) { + case (RH_ENDPOINT_STALL): OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_CLASS: + switch (wValue) { + case RH_C_HUB_LOCAL_POWER: + OK(0); + case (RH_C_HUB_OVER_CURRENT): + WR_RH_STAT(RH_HS_OCIC); OK (0); + } + break; + + case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_CCS ); OK (0); + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_POCI); OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_LSDA); OK (0); + case (RH_C_PORT_CONNECTION): + WR_RH_PORTSTAT (RH_PS_CSC ); OK (0); + case (RH_C_PORT_ENABLE): + WR_RH_PORTSTAT (RH_PS_PESC); OK (0); + case (RH_C_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSSC); OK (0); + case (RH_C_PORT_OVER_CURRENT): + WR_RH_PORTSTAT (RH_PS_OCIC); OK (0); + case (RH_C_PORT_RESET): + WR_RH_PORTSTAT (RH_PS_PRSC); OK (0); + } + break; + + case RH_SET_FEATURE | RH_OTHER | RH_CLASS: + switch (wValue) { + case (RH_PORT_SUSPEND): + WR_RH_PORTSTAT (RH_PS_PSS ); OK (0); + case (RH_PORT_RESET): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PRS); + OK (0); + case (RH_PORT_POWER): + WR_RH_PORTSTAT (RH_PS_PPS ); OK (0); + case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/ + if (RD_RH_PORTSTAT & RH_PS_CCS) + WR_RH_PORTSTAT (RH_PS_PES ); + OK (0); + } + break; + + case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case (0x01): /* device descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_dev_des), + wLength)); + data_buf = root_hub_dev_des; OK(len); + case (0x02): /* configuration descriptor */ + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_config_des), + wLength)); + data_buf = root_hub_config_des; OK(len); + case (0x03): /* string descriptors */ + if(wValue==0x0300) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index0), + wLength)); + data_buf = root_hub_str_index0; + OK(len); + } + if(wValue==0x0301) { + len = min_t(unsigned int, + leni, + min_t(unsigned int, + sizeof (root_hub_str_index1), + wLength)); + data_buf = root_hub_str_index1; + OK(len); + } + default: + stat = USB_ST_STALLED; + } + break; + + case RH_GET_DESCRIPTOR | RH_CLASS: + { + __u32 temp = roothub_a (&gohci); + + data_buf [0] = 9; /* min length; */ + data_buf [1] = 0x29; + data_buf [2] = temp & RH_A_NDP; +#ifdef CONFIG_AT91C_PQFP_UHPBUG + data_buf [2] = (data_buf [2] == 2) ? 1:0; +#endif + data_buf [3] = 0; + if (temp & RH_A_PSM) /* per-port power switching? */ + data_buf [3] |= 0x1; + if (temp & RH_A_NOCP) /* no overcurrent reporting? */ + data_buf [3] |= 0x10; + else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */ + data_buf [3] |= 0x8; + + /* corresponds to data_buf[4-7] */ + datab [1] = 0; + data_buf [5] = (temp & RH_A_POTPGT) >> 24; + temp = roothub_b (&gohci); + data_buf [7] = temp & RH_B_DR; + if (data_buf [2] < 7) { + data_buf [8] = 0xff; + } else { + data_buf [0] += 2; + data_buf [8] = (temp & RH_B_DR) >> 8; + data_buf [10] = data_buf [9] = 0xff; + } + + len = min_t(unsigned int, leni, + min_t(unsigned int, data_buf [0], wLength)); + OK (len); + } + + case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); + + case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); + + default: + dbg ("unsupported root hub command"); + stat = USB_ST_STALLED; + } + +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#else + wait_ms(1); +#endif + + len = min_t(int, len, leni); + if (data != data_buf) + memcpy (data, data_buf, len); + dev->act_len = len; + dev->status = stat; + +#ifdef DEBUG + if (transfer_len) + urb_priv.actual_length = transfer_len; + pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/); +#else + wait_ms(1); +#endif + + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/* common code for handling submit messages - used for all but root hub */ +/* accesses. */ +int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup, int interval) +{ + int stat = 0; + int maxsize = usb_maxpacket(dev, pipe); + int timeout; + + /* device pulled? Shortcut the action. */ + if (devgone == dev) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if (!maxsize) { + err("submit_common_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + + if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) { + err("sohci_submit_job failed"); + return -1; + } + + wait_ms(10); + /* ohci_dump_status(&gohci); */ + + /* allow more time for a BULK device to react - some are slow */ +#define BULK_TO 5000 /* timeout in milliseconds */ + if (usb_pipetype (pipe) == PIPE_BULK) + timeout = BULK_TO; + else + timeout = 100; + + /* wait for it to complete */ + for (;;) { + /* check whether the controller is done */ + stat = hc_interrupt(); + if (stat < 0) { + stat = USB_ST_CRC_ERR; + break; + } + if (stat >= 0 && stat != 0xff) { + /* 0xff is returned for an SF-interrupt */ + break; + } + if (--timeout) { + wait_ms(1); + } else { + err("CTL:TIMEOUT "); + stat = USB_ST_CRC_ERR; + break; + } + } + /* we got an Root Hub Status Change interrupt */ + if (got_rhsc) { +#ifdef DEBUG + ohci_dump_roothub (&gohci, 1); +#endif + got_rhsc = 0; + /* abuse timeout */ + timeout = rh_check_port_status(&gohci); + if (timeout >= 0) { +#if 0 /* this does nothing useful, but leave it here in case that changes */ + /* the called routine adds 1 to the passed value */ + usb_hub_port_connect_change(gohci.rh.dev, timeout - 1); +#endif + /* + * XXX + * This is potentially dangerous because it assumes + * that only one device is ever plugged in! + */ + devgone = dev; + } + } + + dev->status = stat; + dev->act_len = transfer_len; + +#ifdef DEBUG + pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + + /* free TDs in urb_priv */ + urb_free_priv (&urb_priv); + return 0; +} + +/* submit routines called from usb.c */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len) +{ + info("submit_bulk_msg"); + return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0); +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, struct devrequest *setup) +{ + int maxsize = usb_maxpacket(dev, pipe); + + info("submit_control_msg"); +#ifdef DEBUG + urb_priv.actual_length = 0; + pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe)); +#else + wait_ms(1); +#endif + if (!maxsize) { + err("submit_control_message: pipesize for pipe %lx is zero", + pipe); + return -1; + } + if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) { + gohci.rh.dev = dev; + /* root hub - redirect */ + return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, + setup); + } + + return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0); +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int transfer_len, int interval) +{ + info("submit_int_msg"); + return -1; +} + +/*-------------------------------------------------------------------------* + * HC functions + *-------------------------------------------------------------------------*/ + +/* reset the HC and BUS */ + +static int hc_reset (ohci_t *ohci) +{ + int timeout = 30; + int smm_timeout = 50; /* 0,5 sec */ + + dbg("%s\n", __FUNCTION__); + + if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */ + writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */ + info("USB HC TakeOver from SMM"); + while (readl (&ohci->regs->control) & OHCI_CTRL_IR) { + wait_ms (10); + if (--smm_timeout == 0) { + err("USB HC TakeOver failed!"); + return -1; + } + } + } + + /* Disable HC interrupts */ + writel (OHCI_INTR_MIE, &ohci->regs->intrdisable); + + dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n", + ohci->slot_name, + readl(&ohci->regs->control)); + + /* Reset USB (needed by some controllers) */ + writel (0, &ohci->regs->control); + + /* HC Reset requires max 10 us delay */ + writel (OHCI_HCR, &ohci->regs->cmdstatus); + while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) { + if (--timeout == 0) { + err("USB HC reset timed out!"); + return -1; + } + udelay (1); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* Start an OHCI controller, set the BUS operational + * enable interrupts + * connect the virtual root hub */ + +static int hc_start (ohci_t * ohci) +{ + __u32 mask; + unsigned int fminterval; + + ohci->disabled = 1; + + /* Tell the controller where the control and bulk lists are + * The lists are empty now. */ + + writel (0, &ohci->regs->ed_controlhead); + writel (0, &ohci->regs->ed_bulkhead); + + writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */ + + fminterval = 0x2edf; + writel ((fminterval * 9) / 10, &ohci->regs->periodicstart); + fminterval |= ((((fminterval - 210) * 6) / 7) << 16); + writel (fminterval, &ohci->regs->fminterval); + writel (0x628, &ohci->regs->lsthresh); + + /* start controller operations */ + ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER; + ohci->disabled = 0; + writel (ohci->hc_control, &ohci->regs->control); + + /* disable all interrupts */ + mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD | + OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | + OHCI_INTR_OC | OHCI_INTR_MIE); + writel (mask, &ohci->regs->intrdisable); + /* clear all interrupts */ + mask &= ~OHCI_INTR_MIE; + writel (mask, &ohci->regs->intrstatus); + /* Choose the interrupts we care about now - but w/o MIE */ + mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO; + writel (mask, &ohci->regs->intrenable); + +#ifdef OHCI_USE_NPS + /* required for AMD-756 and some Mac platforms */ + writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM, + &ohci->regs->roothub.a); + writel (RH_HS_LPSC, &ohci->regs->roothub.status); +#endif /* OHCI_USE_NPS */ + +#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) + /* POTPGT delay is bits 24-31, in 2 ms units. */ + mdelay ((roothub_a (ohci) >> 23) & 0x1fe); + + /* connect the virtual root hub */ + ohci->rh.devnum = 0; + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +/* an interrupt happens */ + +static int +hc_interrupt (void) +{ + ohci_t *ohci = &gohci; + struct ohci_regs *regs = ohci->regs; + int ints; + int stat = -1; + + if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) { + ints = OHCI_INTR_WDH; + } else { + ints = readl (®s->intrstatus); + } + + /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */ + + if (ints & OHCI_INTR_RHSC) { + got_rhsc = 1; + } + + if (ints & OHCI_INTR_UE) { + ohci->disabled++; + err ("OHCI Unrecoverable Error, controller usb-%s disabled", + ohci->slot_name); + /* e.g. due to PCI Master/Target Abort */ + +#ifdef DEBUG + ohci_dump (ohci, 1); +#else + wait_ms(1); +#endif + /* FIXME: be optimistic, hope that bug won't repeat often. */ + /* Make some non-interrupt context restart the controller. */ + /* Count and limit the retries though; either hardware or */ + /* software errors can go forever... */ + hc_reset (ohci); + return -1; + } + + if (ints & OHCI_INTR_WDH) { + wait_ms(1); + writel (OHCI_INTR_WDH, ®s->intrdisable); + stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci)); + writel (OHCI_INTR_WDH, ®s->intrenable); + } + + if (ints & OHCI_INTR_SO) { + dbg("USB Schedule overrun\n"); + writel (OHCI_INTR_SO, ®s->intrenable); + stat = -1; + } + + /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */ + if (ints & OHCI_INTR_SF) { + unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1; + wait_ms(1); + writel (OHCI_INTR_SF, ®s->intrdisable); + if (ohci->ed_rm_list[frame] != NULL) + writel (OHCI_INTR_SF, ®s->intrenable); + stat = 0xff; + } + + writel (ints, ®s->intrstatus); + return stat; +} + +/*-------------------------------------------------------------------------*/ + +/*-------------------------------------------------------------------------*/ + +/* De-allocate all resources.. */ + +static void hc_release_ohci (ohci_t *ohci) +{ + dbg ("USB HC release ohci usb-%s", ohci->slot_name); + + if (!ohci->disabled) + hc_reset (ohci); +} + +/*-------------------------------------------------------------------------*/ + +/* + * low level initalisation routine, called from usb.c + */ +static char ohci_inited = 0; + +int usb_lowlevel_init(void) +{ + /* + * Enable USB host clock. + */ + *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */ + *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */ + + memset (&gohci, 0, sizeof (ohci_t)); + memset (&urb_priv, 0, sizeof (urb_priv_t)); + + /* align the storage */ + if ((__u32)&ghcca[0] & 0xff) { + err("HCCA not aligned!!"); + return -1; + } + phcca = &ghcca[0]; + info("aligned ghcca %p", phcca); + memset(&ohci_dev, 0, sizeof(struct ohci_device)); + if ((__u32)&ohci_dev.ed[0] & 0x7) { + err("EDs not aligned!!"); + return -1; + } + memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1)); + if ((__u32)gtd & 0x7) { + err("TDs not aligned!!"); + return -1; + } + ptd = gtd; + gohci.hcca = phcca; + memset (phcca, 0, sizeof (struct ohci_hcca)); + + gohci.disabled = 1; + gohci.sleeping = 0; + gohci.irq = -1; + gohci.regs = (struct ohci_regs *)AT91_USB_HOST_BASE; + + gohci.flags = 0; + gohci.slot_name = "at91rm9200"; + + if (hc_reset (&gohci) < 0) { + hc_release_ohci (&gohci); + /* Initialization failed */ + *AT91C_PMC_PCER = AT91C_ID_UHP; + *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ + return -1; + } + + /* FIXME this is a second HC reset; why?? */ +/* writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control); + wait_ms (10);*/ + + if (hc_start (&gohci) < 0) { + err ("can't start usb-%s", gohci.slot_name); + hc_release_ohci (&gohci); + /* Initialization failed */ + *AT91C_PMC_PCER = AT91C_ID_UHP; + *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ + return -1; + } + +#ifdef DEBUG + ohci_dump (&gohci, 1); +#else + wait_ms(1); +#endif + ohci_inited = 1; + return 0; +} + +int usb_lowlevel_stop(void) +{ + /* this gets called really early - before the controller has */ + /* even been initialized! */ + if (!ohci_inited) + return 0; + /* TODO release any interrupts, etc. */ + /* call hc_release_ohci() here ? */ + hc_reset (&gohci); + /* may not want to do this */ + *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; + *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */ + return 0; +} + +#endif /* CONFIG_USB_OHCI */ diff --git a/cpu/arm920t/at91rm9200/usb_ohci.h b/cpu/arm920t/at91rm9200/usb_ohci.h new file mode 100644 index 000000000..ecb4e937b --- /dev/null +++ b/cpu/arm920t/at91rm9200/usb_ohci.h @@ -0,0 +1,419 @@ +/* + * URB OHCI HCD (Host Controller Driver) for USB. + * + * (C) Copyright 1999 Roman Weissgaerber + * (C) Copyright 2000-2001 David Brownell + * + * usb-ohci.h + */ + + +static int cc_to_error[16] = { + +/* mapping of the OHCI CC status to error codes */ + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 +}; + +/* ED States */ + +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 +#define ED_OPER 0x02 +#define ED_DEL 0x04 +#define ED_URB_DEL 0x08 + +/* usb_ohci_ed */ +struct ed { + __u32 hwINFO; + __u32 hwTailP; + __u32 hwHeadP; + __u32 hwNextED; + + struct ed *ed_prev; + __u8 int_period; + __u8 int_branch; + __u8 int_load; + __u8 int_interval; + __u8 state; + __u8 type; + __u16 last_iso; + struct ed *ed_rm_list; + + struct usb_device *usb_dev; + __u32 unused[3]; +} __attribute((aligned(16))); +typedef struct ed ed_t; + + +/* TD info field */ +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 + +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 + +/* CC Codes */ +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F + + +#define MAXPSW 1 + +struct td { + __u32 hwINFO; + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ + + __u16 hwPSW[MAXPSW]; + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; + struct usb_device *usb_dev; + int transfer_len; + __u32 data; + + __u32 unused2[2]; +} __attribute((aligned(32))); +typedef struct td td_t; + +#define OHCI_ED_SKIP (1 << 14) + +/* + * The HCCA (Host Controller Communications Area) is a 256 byte + * structure defined in the OHCI spec. that the host controller is + * told the base address of. It must be 256-byte aligned. + */ + +#define NUM_INTS 32 /* part of the OHCI standard */ +struct ohci_hcca { + __u32 int_table[NUM_INTS]; /* Interrupt ED table */ + __u16 frame_no; /* current frame number */ + __u16 pad1; /* set to 0 on each frame_no change */ + __u32 done_head; /* info returned for an interrupt */ + u8 reserved_for_hc[116]; +} __attribute((aligned(256))); + + +/* + * Maximum number of root hub ports. + */ +#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ + +/* + * This is the structure of the OHCI controller's memory mapped I/O + * region. This is Memory Mapped I/O. You must use the readl() and + * writel() macros defined in asm/io.h to access these!! + */ +struct ohci_regs { + /* control and status registers */ + __u32 revision; + __u32 control; + __u32 cmdstatus; + __u32 intrstatus; + __u32 intrenable; + __u32 intrdisable; + /* memory pointers */ + __u32 hcca; + __u32 ed_periodcurrent; + __u32 ed_controlhead; + __u32 ed_controlcurrent; + __u32 ed_bulkhead; + __u32 ed_bulkcurrent; + __u32 donehead; + /* frame counters */ + __u32 fminterval; + __u32 fmremaining; + __u32 fmnumber; + __u32 periodicstart; + __u32 lsthresh; + /* Root hub ports */ + struct ohci_roothub_regs { + __u32 a; + __u32 b; + __u32 status; + __u32 portstatus[MAX_ROOT_PORTS]; + } roothub; +} __attribute((aligned(32))); + + +/* OHCI CONTROL AND STATUS REGISTER MASKS */ + +/* + * HcControl (control) register masks + */ +#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ +#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ +#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ + +/* pre-shifted values for HCFS */ +# define OHCI_USB_RESET (0 << 6) +# define OHCI_USB_RESUME (1 << 6) +# define OHCI_USB_OPER (2 << 6) +# define OHCI_USB_SUSPEND (3 << 6) + +/* + * HcCommandStatus (cmdstatus) register masks + */ +#define OHCI_HCR (1 << 0) /* host controller reset */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ + +/* + * masks used with interrupt registers: + * HcInterruptStatus (intrstatus) + * HcInterruptEnable (intrenable) + * HcInterruptDisable (intrdisable) + */ +#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ +#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ +#define OHCI_INTR_SF (1 << 2) /* start frame */ +#define OHCI_INTR_RD (1 << 3) /* resume detect */ +#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ +#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ +#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ +#define OHCI_INTR_OC (1 << 30) /* ownership change */ +#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ + + +/* Virtual Root HUB */ +struct virt_root_hub { + int devnum; /* Address of Root Hub endpoint */ + void *dev; /* was urb */ + void *int_addr; + int send; + int interval; +}; + +/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ + +/* destination of request */ +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 + +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 +/* Our Vendor Specific Request */ +#define RH_SET_EP 0x2000 + + +/* Hub port features */ +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 + +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 + +/* Hub features */ +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 + +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 + +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 + + +/* OHCI ROOT HUB REGISTER MASKS */ + +/* roothub.portstatus [i] bits */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ + +/* roothub.status bits */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ + +/* roothub.b masks */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ + +/* roothub.a masks */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ + +/* urb */ +#define N_URB_TD 48 +typedef struct +{ + ed_t *ed; + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ + int state; + unsigned long pipe; + int actual_length; + td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */ +} urb_priv_t; +#define URB_DEL 1 + +/* + * This is the full ohci controller description + * + * Note how the "proper" USB information is just + * a subset of what the full implementation needs. (Linus) + */ + + +typedef struct ohci { + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma;*/ + + int irq; + int disabled; /* e.g. got a UE, we're hung */ + int sleeping; + unsigned long flags; /* for HC bugs */ + + struct ohci_regs *regs; /* OHCI controller's memory */ + + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ + int intrstatus; + __u32 hc_control; /* copy of the hc control reg */ + struct usb_device *dev[32]; + struct virt_root_hub rh; + + const char *slot_name; +} ohci_t; + +#define NUM_EDS 8 /* num of preallocated endpoint descriptors */ + +struct ohci_device { + ed_t ed[NUM_EDS]; + int ed_cnt; +}; + +/* hcd */ +/* endpoint */ +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); + +/*-------------------------------------------------------------------------*/ + +/* we need more TDs than EDs */ +#define NUM_TD 64 + +/* +1 so we can align the storage */ +td_t gtd[NUM_TD+1]; +/* pointers to aligned storage */ +td_t *ptd; + +/* TDs ... */ +static inline struct td * +td_alloc (struct usb_device *usb_dev) +{ + int i; + struct td *td; + + td = NULL; + for (i = 0; i < NUM_TD; i++) + { + if (ptd[i].usb_dev == NULL) + { + td = &ptd[i]; + td->usb_dev = usb_dev; + break; + } + } + + return td; +} + +static inline void +ed_free (struct ed *ed) +{ + ed->usb_dev = NULL; +} diff --git a/cpu/arm920t/imx/Makefile b/cpu/arm920t/imx/Makefile index 9207ec1bc..8865f827d 100644 --- a/cpu/arm920t/imx/Makefile +++ b/cpu/arm920t/imx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,23 +23,20 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(SOC).a +LIB = lib$(SOC).a -COBJS = generic.o interrupts.o serial.o speed.o +OBJS = generic.o interrupts.o serial.o speed.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) +all: .depend $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm920t/imx/serial.c b/cpu/arm920t/imx/serial.c index 6c56acbfd..9dbaa569a 100644 --- a/cpu/arm920t/imx/serial.c +++ b/cpu/arm920t/imx/serial.c @@ -115,7 +115,7 @@ int serial_init (void) /* Enable FIFOs */ base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN; - /* Clear status flags */ + /* Clear status flags */ base->usr2 |= USR2_ADET | USR2_DTRF | USR2_IDLE | @@ -126,7 +126,7 @@ int serial_init (void) USR2_ORE | USR2_RDR; - /* Clear status flags */ + /* Clear status flags */ base->usr1 |= USR1_PARITYERR | USR1_RTSD | USR1_ESCF | diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c index c9cd066c9..a43a3ed4f 100644 --- a/cpu/arm920t/interrupts.c +++ b/cpu/arm920t/interrupts.c @@ -31,20 +31,144 @@ #include #include +#include #ifdef CONFIG_USE_IRQ -#include +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + void do_irq (struct pt_regs *pt_regs) { -#if defined (ARM920_IRQ_CALLBACK) - ARM920_IRQ_CALLBACK(); -#elif defined (CONFIG_ARCH_INTEGRATOR) +#if defined (CONFIG_USE_IRQ) && defined (CONFIG_ARCH_INTEGRATOR) /* ASSUMED to be a timer interrupt */ /* Just clear it - count handled in */ /* integratorap.c */ *(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0; #else -#error do_irq() not defined for this cpu type + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); #endif } -#endif diff --git a/cpu/arm920t/ks8695/Makefile b/cpu/arm920t/ks8695/Makefile index 7db947352..ac4906089 100644 --- a/cpu/arm920t/ks8695/Makefile +++ b/cpu/arm920t/ks8695/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,24 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(SOC).a +LIB = lib$(SOC).a -COBJS = interrupts.o serial.o +OBJS = interrupts.o serial.o SOBJS = lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +all: .depend $(LIB) -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile index 676492025..af9e4effc 100644 --- a/cpu/arm920t/s3c24x0/Makefile +++ b/cpu/arm920t/s3c24x0/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,24 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(SOC).a +LIB = lib$(SOC).a -COBJS = i2c.o interrupts.o serial.o speed.o \ - usb.o usb_ohci.o nand.o +OBJS = i2c.o interrupts.o serial.o speed.o \ + usb_ohci.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) +all: .depend $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 7ad9fcbd5..1b364123d 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -216,13 +216,4 @@ void reset_cpu (ulong ignored) /*NOTREACHED*/ } -#ifdef CONFIG_USE_IRQ -void s3c2410_irq(void) -{ - S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); - u_int32_t intpnd = irq->INTPND; - -} -#endif /* USE_IRQ */ - #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/s3c24x0/serial.c b/cpu/arm920t/s3c24x0/serial.c index 064b99871..36851ad5c 100644 --- a/cpu/arm920t/s3c24x0/serial.c +++ b/cpu/arm920t/s3c24x0/serial.c @@ -48,73 +48,18 @@ DECLARE_GLOBAL_DATA_PTR; #error "Bad: you didn't configure serial ..." #endif -#if defined(CONFIG_SERIAL_MULTI) -#include - -/* Multi serial device functions */ -#define DECLARE_S3C_SERIAL_FUNCTIONS(port) \ - int s3serial##port##_init (void) {\ - return serial_init_dev(port);}\ - void s3serial##port##_setbrg (void) {\ - serial_setbrg_dev(port);}\ - int s3serial##port##_getc (void) {\ - return serial_getc_dev(port);}\ - int s3serial##port##_tstc (void) {\ - return serial_tstc_dev(port);}\ - void s3serial##port##_putc (const char c) {\ - serial_putc_dev(port, c);}\ - void s3serial##port##_puts (const char *s) {\ - serial_puts_dev(port, s);} - -#define INIT_S3C_SERIAL_STRUCTURE(port,name,bus) {\ - name,\ - bus,\ - s3serial##port##_init,\ - s3serial##port##_setbrg,\ - s3serial##port##_getc,\ - s3serial##port##_tstc,\ - s3serial##port##_putc,\ - s3serial##port##_puts, } - -#endif /* CONFIG_SERIAL_MULTI */ - -void _serial_setbrg(const int dev_index) +void serial_setbrg (void) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); - unsigned int reg = 0; + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); int i; + unsigned int reg = 0; /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ reg = get_PCLK() / (16 * gd->baudrate) - 1; - uart->UBRDIV = reg; - for (i = 0; i < 100; i++); -} -#if defined(CONFIG_SERIAL_MULTI) -static inline void -serial_setbrg_dev(unsigned int dev_index) -{ - _serial_setbrg(dev_index); -} -#else -void serial_setbrg(void) -{ - _serial_setbrg(UART_NR); -} -#endif - - -/* Initialise the serial port. The settings are always 8 data bits, no parity, - * 1 stop bit, no start bits. - */ -static int serial_init_dev(const int dev_index) -{ - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); - /* FIFO enable, Tx/Rx FIFO clear */ uart->UFCON = 0x07; uart->UMCON = 0x0; - /* Normal,No parity,1 stop,8 bit */ uart->ULCON = 0x3; /* @@ -122,57 +67,40 @@ static int serial_init_dev(const int dev_index) * normal,interrupt or polling */ uart->UCON = 0x245; + uart->UBRDIV = reg; #ifdef CONFIG_HWFLOW uart->UMCON = 0x1; /* RTS up */ #endif - - /* FIXME: This is sooooooooooooooooooo ugly */ -#if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2) - /* we need auto hw flow control on the gsm and gps port */ - if (dev_index == 0 || dev_index == 1) - uart->UMCON = 0x10; -#endif - _serial_setbrg(dev_index); - - return (0); + for (i = 0; i < 100; i++); } -#if !defined(CONFIG_SERIAL_MULTI) -/* Initialise the serial port. The settings are always 8 data bits, no parity, - * 1 stop bit, no start bits. +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * */ int serial_init (void) { - return serial_init_dev(UART_NR); + serial_setbrg (); + + return (0); } -#endif /* * Read a single byte from the serial port. Returns 1 on success, 0 * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -int _serial_getc (const int dev_index) +int serial_getc (void) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); /* wait for character to arrive */ while (!(uart->UTRSTAT & 0x1)); return uart->URXH & 0xff; } -#if defined(CONFIG_SERIAL_MULTI) -static inline int serial_getc_dev(unsigned int dev_index) -{ - return _serial_getc(dev_index); -} -#else -int serial_getc (void) -{ - return _serial_getc(UART_NR); -} -#endif #ifdef CONFIG_HWFLOW static int hwflow = 0; /* turned off by default */ @@ -210,9 +138,9 @@ void enable_putc(void) /* * Output a single byte to the serial port. */ -void _serial_putc (const char c, const int dev_index) +void serial_putc (const char c) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); #ifdef CONFIG_MODEM_SUPPORT if (be_quiet) return; @@ -233,72 +161,23 @@ void _serial_putc (const char c, const int dev_index) if (c == '\n') serial_putc ('\r'); } -#if defined(CONFIG_SERIAL_MULTI) -static inline void serial_putc_dev(unsigned int dev_index, const char c) -{ - _serial_putc(c, dev_index); -} -#else -void serial_putc(const char c) -{ - _serial_putc(c, UART_NR); -} -#endif - /* * Test whether a character is in the RX buffer */ -int _serial_tstc(const int dev_index) +int serial_tstc (void) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); return uart->UTRSTAT & 0x1; } -#if defined(CONFIG_SERIAL_MULTI) -static inline int -serial_tstc_dev(unsigned int dev_index) -{ - return _serial_tstc(dev_index); -} -#else -int serial_tstc(void) -{ - return _serial_tstc(UART_NR); -} -#endif -void _serial_puts(const char *s, const int dev_index) -{ - while (*s) { - _serial_putc (*s++, dev_index); - } -} -#if defined(CONFIG_SERIAL_MULTI) -static inline void -serial_puts_dev(int dev_index, const char *s) -{ - _serial_puts(s, dev_index); -} -#else void serial_puts (const char *s) { - _serial_puts(s, UART_NR); + while (*s) { + serial_putc (*s++); + } } -#endif - -#if defined(CONFIG_SERIAL_MULTI) -DECLARE_S3C_SERIAL_FUNCTIONS(0); -struct serial_device s3c24xx_serial0_device = - INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1"); -DECLARE_S3C_SERIAL_FUNCTIONS(1); -struct serial_device s3c24xx_serial1_device = - INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2"); -DECLARE_S3C_SERIAL_FUNCTIONS(2); -struct serial_device s3c24xx_serial2_device = - INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3"); - -#endif /* CONFIG_SERIAL_MULTI */ #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index b57c2d895..869ca79d0 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -58,8 +58,8 @@ #define OHCI_CONTROL_INIT \ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE -#define readl(a) (*((volatile u32 *)(a))) -#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) +#define readl(a) (*((vu_long *)(a))) +#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) @@ -498,7 +498,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi) if (ohci->ed_controltail == NULL) { writel (ed, &ohci->regs->ed_controlhead); } else { - ohci->ed_controltail->hwNextED = (__u32)m32_swap (ed); + ohci->ed_controltail->hwNextED = m32_swap (ed); } ed->ed_prev = ohci->ed_controltail; if (!ohci->ed_controltail && !ohci->ed_rm_list[0] && @@ -514,7 +514,7 @@ static int ep_link (ohci_t *ohci, ed_t *edi) if (ohci->ed_bulktail == NULL) { writel (ed, &ohci->regs->ed_bulkhead); } else { - ohci->ed_bulktail->hwNextED = (__u32)m32_swap (ed); + ohci->ed_bulktail->hwNextED = m32_swap (ed); } ed->ed_prev = ohci->ed_bulktail; if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] && @@ -606,7 +606,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe) ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */ /* dummy td; end of td list for ed */ td = td_alloc (usb_dev); - ed->hwTailP = (__u32)m32_swap (td); + ed->hwTailP = m32_swap (td); ed->hwHeadP = ed->hwTailP; ed->state = ED_UNLINK; ed->type = usb_pipetype (pipe); @@ -663,13 +663,13 @@ static void td_fill (ohci_t *ohci, unsigned int info, if (!len) data = 0; - td->hwINFO = (__u32)m32_swap (info); - td->hwCBP = (__u32)m32_swap (data); + td->hwINFO = m32_swap (info); + td->hwCBP = m32_swap (data); if (data) - td->hwBE = (__u32)m32_swap (data + len - 1); + td->hwBE = m32_swap (data + len - 1); else td->hwBE = 0; - td->hwNextTD = (__u32)m32_swap (td_pt); + td->hwNextTD = m32_swap (td_pt); /* append to queue */ td->ed->hwTailP = td->hwNextTD; @@ -971,13 +971,13 @@ static unsigned char root_hub_str_index1[] = /*-------------------------------------------------------------------------*/ -#define OK(x) len = (x); break +#define OK(x) len = (x); break #ifdef DEBUG -#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} -#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} +#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);} +#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);} #else -#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) -#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) +#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status) +#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1]) #endif #define RD_RH_STAT roothub_status(&gohci) #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1) @@ -1163,7 +1163,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); data_buf [1] = 0x29; data_buf [2] = temp & RH_A_NDP; data_buf [3] = 0; - if (temp & RH_A_PSM) /* per-port power switching? */ + if (temp & RH_A_PSM) /* per-port power switching? */ data_buf [3] |= 0x1; if (temp & RH_A_NOCP) /* no overcurrent reporting? */ data_buf [3] |= 0x10; @@ -1188,9 +1188,9 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe)); OK (len); } - case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); + case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1); - case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); + case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0); default: dbg ("unsupported root hub command"); diff --git a/cpu/arm920t/s3c24x0/usb_ohci.h b/cpu/arm920t/s3c24x0/usb_ohci.h index 3af5fca80..5e9a0fdfc 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.h +++ b/cpu/arm920t/s3c24x0/usb_ohci.h @@ -11,30 +11,30 @@ static int cc_to_error[16] = { /* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 }; /* ED States */ -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 #define ED_OPER 0x02 #define ED_DEL 0x04 -#define ED_URB_DEL 0x08 +#define ED_URB_DEL 0x08 /* usb_ohci_ed */ struct ed { @@ -60,53 +60,53 @@ typedef struct ed ed_t; /* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 /* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F #define MAXPSW 1 struct td { __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; struct usb_device *usb_dev; int transfer_len; __u32 data; @@ -129,7 +129,7 @@ struct ohci_hcca { __u16 frame_no; /* current frame number */ __u16 pad1; /* set to 0 on each frame_no change */ __u32 done_head; /* info returned for an interrupt */ - u8 reserved_for_hc[116]; + u8 reserved_for_hc[116]; } __attribute((aligned(256))); @@ -140,7 +140,7 @@ struct ohci_hcca { /* * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and + * region. This is Memory Mapped I/O. You must use the readl() and * writel() macros defined in asm/io.h to access these!! */ struct ohci_regs { @@ -200,10 +200,10 @@ struct ohci_regs { * HcCommandStatus (cmdstatus) register masks */ #define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ /* * masks used with interrupt registers: @@ -234,93 +234,93 @@ struct virt_root_hub { /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ /* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 /* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 #define RH_SET_ADDRESS 0x0500 #define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 +#define RH_SET_DESCRIPTOR 0x0700 #define RH_GET_CONFIGURATION 0x0880 #define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 /* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 +#define RH_SET_EP 0x2000 /* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 /* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 /* OHCI ROOT HUB REGISTER MASKS */ /* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ /* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ /* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ /* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* urb */ #define N_URB_TD 48 @@ -345,39 +345,39 @@ typedef struct typedef struct ohci { - struct ohci_hcca *hcca; /* hcca */ - /*dma_addr_t hcca_dma; */ + struct ohci_hcca *hcca; /* hcca */ + /*dma_addr_t hcca_dma;*/ int irq; - int disabled; /* e.g. got a UE, we're hung */ + int disabled; /* e.g. got a UE, we're hung */ int sleeping; - unsigned long flags; /* for HC bugs */ + unsigned long flags; /* for HC bugs */ struct ohci_regs *regs; /* OHCI controller's memory */ - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ int intrstatus; - __u32 hc_control; /* copy of the hc control reg */ + __u32 hc_control; /* copy of the hc control reg */ struct usb_device *dev[32]; struct virt_root_hub rh; - const char *slot_name; + const char *slot_name; } ohci_t; #define NUM_EDS 8 /* num of preallocated endpoint descriptors */ struct ohci_device { - ed_t ed[NUM_EDS]; + ed_t ed[NUM_EDS]; int ed_cnt; }; /* hcd */ /* endpoint */ -static int ep_link (ohci_t * ohci, ed_t * ed); -static int ep_unlink (ohci_t * ohci, ed_t * ed); -static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe); +static int ep_link(ohci_t * ohci, ed_t * ed); +static int ep_unlink(ohci_t * ohci, ed_t * ed); +static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe); /*-------------------------------------------------------------------------*/ @@ -385,20 +385,22 @@ static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe); #define NUM_TD 64 /* +1 so we can align the storage */ -td_t gtd[NUM_TD + 1]; - +td_t gtd[NUM_TD+1]; /* pointers to aligned storage */ td_t *ptd; /* TDs ... */ -static inline struct td *td_alloc (struct usb_device *usb_dev) +static inline struct td * +td_alloc (struct usb_device *usb_dev) { int i; - struct td *td; + struct td *td; td = NULL; - for (i = 0; i < NUM_TD; i++) { - if (ptd[i].usb_dev == NULL) { + for (i = 0; i < NUM_TD; i++) + { + if (ptd[i].usb_dev == NULL) + { td = &ptd[i]; td->usb_dev = usb_dev; break; @@ -408,7 +410,8 @@ static inline struct td *td_alloc (struct usb_device *usb_dev) return td; } -static inline void ed_free (struct ed *ed) +static inline void +ed_free (struct ed *ed) { ed->usb_dev = NULL; } diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 62231f856..346f0d09e 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -27,7 +27,7 @@ #include #include -#include + /* ************************************************************************* @@ -39,7 +39,7 @@ .globl _start -_start: b start_code +_start: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -62,7 +62,7 @@ _fiq: .word fiq /* ************************************************************************* * - * Startup Code (called from the ARM reset exception vector) + * Startup Code (reset vector) * * do important init only if we don't start from memory! * relocate armboot to ram @@ -104,10 +104,10 @@ FIQ_STACK_START: /* - * the actual start code + * the actual reset code */ -start_code: +reset: /* * set the cpu to SVC32 mode */ @@ -116,37 +116,19 @@ start_code: orr r0,r0,#0xd3 msr cpsr,r0 - bl coloured_LED_init - bl red_LED_on - -#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) - /* - * relocate exception table - */ - ldr r0, =_start - ldr r1, =0x0 - mov r2, #16 -copyex: - subs r2, r2, #1 - ldr r3, [r0], #4 - str r3, [r1], #4 - bne copyex +/* turn off the watchdog */ +#if defined(CONFIG_S3C2400) +# define pWTCON 0x15300000 +# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ +# define CLKDIVN 0x14800014 /* clock divisor register */ +#elif defined(CONFIG_S3C2410) +# define pWTCON 0x53000000 +# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ +# define INTSUBMSK 0x4A00001C +# define CLKDIVN 0x4C000014 /* clock divisor register */ #endif #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) - /* turn off the watchdog */ - -# if defined(CONFIG_S3C2400) -# define pWTCON 0x15300000 -# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ -# define CLKDIVN 0x14800014 /* clock divisor register */ -#else -# define pWTCON 0x53000000 -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ -# define INTSUBMSK 0x4A00001C -# define CLKDIVN 0x4C000014 /* clock divisor register */ -# endif - ldr r0, =pWTCON mov r1, #0x0 str r1, [r0] @@ -178,8 +160,6 @@ copyex: bl cpu_init_crit #endif -#ifndef CONFIG_AT91RM9200 - #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ @@ -198,7 +178,7 @@ copy_loop: cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop #endif /* CONFIG_SKIP_RELOCATE_UBOOT */ -#endif + /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ @@ -212,13 +192,34 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 ble clbss_l +#if 0 + /* try doing this stuff after the relocation */ + ldr r0, =pWTCON + mov r1, #0x0 + str r1, [r0] + + /* + * mask all IRQs by setting all bits in the INTMR - default + */ + mov r1, #0xffffffff + ldr r0, =INTMR + str r1, [r0] + + /* FCLK:HCLK:PCLK = 1:2:4 */ + /* default FCLK is 120 MHz ! */ + ldr r0, =CLKDIVN + mov r1, #3 + str r1, [r0] + /* END stuff after relocation */ +#endif + ldr pc, _start_armboot _start_armboot: .word start_armboot @@ -261,11 +262,7 @@ cpu_init_crit: * find a lowlevel_init.S in your board directory. */ mov ip, lr -#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF) - -#else bl lowlevel_init -#endif mov lr, ip mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ @@ -329,12 +326,12 @@ cpu_init_crit: .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 - add r7, sp, #S_PC - stmdb r7, {sp, lr}^ @ Calling SP, LR - str lr, [r7, #0] @ Save calling PC + add r8, sp, #S_PC + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC mrs r6, spsr - str r6, [r7, #4] @ Save CPSR - str r0, [r7, #8] @ Save OLD_R0 + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 mov r0, sp .endm @@ -377,31 +374,31 @@ cpu_init_crit: undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -409,7 +406,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -417,7 +414,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else @@ -426,12 +423,12 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif diff --git a/cpu/arm925t/Makefile b/cpu/arm925t/Makefile index 0d4912cd7..a1db818a8 100644 --- a/cpu/arm925t/Makefile +++ b/cpu/arm925t/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o omap925.o +OBJS = interrupts.o cpu.o omap925.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c index 208a25bd9..57bb4eab6 100644 --- a/cpu/arm925t/interrupts.c +++ b/cpu/arm925t/interrupts.c @@ -36,11 +36,146 @@ #include #include +#include + #define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8)) +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + static ulong timestamp; static ulong lastdec; diff --git a/cpu/arm925t/omap925.c b/cpu/arm925t/omap925.c index 65dab9f88..ae62656f3 100644 --- a/cpu/arm925t/omap925.c +++ b/cpu/arm925t/omap925.c @@ -25,6 +25,40 @@ #include #include +ushort gpioreserved; + +void gpioreserve(ushort mask) +{ + gpioreserved |= mask; +} + +void gpiosetdir(ushort mask, ushort in) +{ + *(ushort *)GPIO_DIR_CONTROL_REG = (*(ushort *)GPIO_DIR_CONTROL_REG & ~mask) | (in & mask); +} + + +void gpiosetout(ushort mask, ushort out) +{ + ushort *r_ptr, r_val; + + r_ptr = (ushort *)GPIO_DATA_OUTPUT_REG; /* set pointer */ + r_val = *r_ptr & ~mask; /* get previous val, clear bits we want to change */ + r_val |= (out & mask); /* set specified bits in value + plus origional ones */ + *r_ptr = r_val; /* write it out */ +/* + * gcc screwed this one up :(. + * + * *(ushort *)GPIO_DATA_OUTPUT_REG = (*(ushort *)GPIO_DATA_OUTPUT_REG & ~mask) | (out & mask); + */ + +} + +void gpioinit(void) +{ +} + + #define MIF_CONFIG_REG 0xFFFECC0C #define FLASH_GLOBAL_CTRL_NWP 1 diff --git a/cpu/arm925t/start.S b/cpu/arm925t/start.S index 5ddda54bd..acd77426d 100644 --- a/cpu/arm925t/start.S +++ b/cpu/arm925t/start.S @@ -9,7 +9,7 @@ * Copyright (c) 2002 Alex Züpke * Copyright (c) 2002 Gary Jennejohn * Copyright (c) 2003 Richard Woodruff - * Copyright (c) 2003 Kshitij + * Copyright (c) 2003 Kshitij * * See file CREDITS for list of people who contributed to this * project. @@ -200,7 +200,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -357,31 +357,31 @@ cpu_init_crit: undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -389,7 +389,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -397,7 +397,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else @@ -406,13 +406,13 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile index 0facce470..060fd20c6 100644 --- a/cpu/arm926ejs/Makefile +++ b/cpu/arm926ejs/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o cpuinfo.o +OBJS = interrupts.o cpu.o cpuinfo.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index 56c6289da..722732e58 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -134,52 +134,25 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); } -/* cache_bit must be either C1_IC or C1_DC */ -static void cache_enable(uint32_t cache_bit) +void icache_enable (void) { - uint32_t reg; + ulong reg; - reg = read_p15_c1(); /* get control reg. */ - cp_delay(); - write_p15_c1(reg | cache_bit); + reg = read_p15_c1 (); /* get control reg. */ + cp_delay (); + write_p15_c1 (reg | C1_IC); } -/* cache_bit must be either C1_IC or C1_DC */ -static void cache_disable(uint32_t cache_bit) +void icache_disable (void) { - uint32_t reg; + ulong reg; - reg = read_p15_c1(); - cp_delay(); - write_p15_c1(reg & ~cache_bit); + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); } -void icache_enable(void) +int icache_status (void) { - cache_enable(C1_IC); -} - -void icache_disable(void) -{ - cache_disable(C1_IC); -} - -int icache_status(void) -{ - return (read_p15_c1() & C1_IC) != 0; -} - -void dcache_enable(void) -{ - cache_enable(C1_DC); -} - -void dcache_disable(void) -{ - cache_disable(C1_DC); -} - -int dcache_status(void) -{ - return (read_p15_c1() & C1_DC) != 0; + return (read_p15_c1 () & C1_IC) != 0; } diff --git a/cpu/arm926ejs/cpuinfo.c b/cpu/arm926ejs/cpuinfo.c index 35ba7dba0..8c9863161 100644 --- a/cpu/arm926ejs/cpuinfo.c +++ b/cpu/arm926ejs/cpuinfo.c @@ -18,6 +18,8 @@ #define omap_readw(x) *(volatile unsigned short *)(x) #define omap_readl(x) *(volatile unsigned long *)(x) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + #define OMAP_DIE_ID_0 0xfffe1800 #define OMAP_DIE_ID_1 0xfffe1804 #define OMAP_PRODUCTION_ID_0 0xfffe2000 diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c index 7a41f0b12..9cac969f6 100644 --- a/cpu/arm926ejs/interrupts.c +++ b/cpu/arm926ejs/interrupts.c @@ -37,6 +37,140 @@ #include #include +#include + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} #ifdef CONFIG_INTEGRATOR @@ -49,7 +183,7 @@ int interrupt_init (void) { extern void timer_init(void); - timer_init(); + timer_init(); return 0; } diff --git a/cpu/arm926ejs/omap/Makefile b/cpu/arm926ejs/omap/Makefile index c335d5c86..f9d337819 100644 --- a/cpu/arm926ejs/omap/Makefile +++ b/cpu/arm926ejs/omap/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(SOC).a +LIB = lib$(SOC).a -COBJS = timer.o +OBJS = timer.o SOBJS = reset.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) +all: .depend $(LIB) -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index a61fa1847..725c6639a 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -175,16 +175,13 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 ble clbss_l - bl coloured_LED_init - bl red_LED_on - ldr pc, _start_armboot _start_armboot: @@ -201,7 +198,8 @@ _start_armboot: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT + + cpu_init_crit: /* * flush v4 I/D caches @@ -227,8 +225,6 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - /* ************************************************************************* * @@ -370,7 +366,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -378,7 +374,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else diff --git a/cpu/arm926ejs/versatile/Makefile b/cpu/arm926ejs/versatile/Makefile index c335d5c86..f9d337819 100644 --- a/cpu/arm926ejs/versatile/Makefile +++ b/cpu/arm926ejs/versatile/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2005 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(SOC).a +LIB = lib$(SOC).a -COBJS = timer.o +OBJS = timer.o SOBJS = reset.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) +all: .depend $(LIB) -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm946es/Makefile b/cpu/arm946es/Makefile index d5ac7d3fd..203278e9c 100644 --- a/cpu/arm946es/Makefile +++ b/cpu/arm946es/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = interrupts.o cpu.o +OBJS = interrupts.o cpu.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm946es/interrupts.c b/cpu/arm946es/interrupts.c index a2c3646f1..5728c3a44 100644 --- a/cpu/arm946es/interrupts.c +++ b/cpu/arm946es/interrupts.c @@ -37,10 +37,144 @@ #include #include +#include #define TIMER_LOAD_VAL 0xffffffff extern void reset_cpu(ulong addr); +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + #ifdef CONFIG_INTEGRATOR /* Timer functionality supplied by Integrator board (AP or CP) */ #else diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S index 9e97f530f..e8c908bf2 100644 --- a/cpu/arm946es/start.S +++ b/cpu/arm946es/start.S @@ -167,7 +167,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -358,7 +358,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -366,7 +366,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else diff --git a/cpu/arm_intcm/Makefile b/cpu/arm_intcm/Makefile index 7701b03bb..203278e9c 100644 --- a/cpu/arm_intcm/Makefile +++ b/cpu/arm_intcm/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = cpu.o +OBJS = interrupts.o cpu.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/arm_intcm/interrupts.c b/cpu/arm_intcm/interrupts.c new file mode 100644 index 000000000..176317691 --- /dev/null +++ b/cpu/arm_intcm/interrupts.c @@ -0,0 +1,192 @@ +/* + * (C) Copyright 2003 + * Texas Instruments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifndef CONFIG_INTEGRATOR +/* Only to be used for integrator/AP or /CP */ +/* Allows U-Boot to be used with any ARM supplied core module (CM), + * provided the ARM boot monitor, or similar software, + * runs first to set up the platform e.g. map writeable memory to 0x00000000 + * - see Integrator User Guides + * Versatile has a supported cpu - arm926ejs + * Some integrator CMs cpus are supported + * CM926EJ-S, CM946E-S + * For platforms with supported cpus U-Boot can be used as the sole boot + * monitor/loader - it will configure the platform itself + * Also U-Boot may be faster/smaller in those cases since specific + * qualities of the cpu and/or CM can be used e.g i and/or d caches etc. + */ +#endif +extern void reset_cpu(ulong addr); + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +/* The timer functionality is supplied by the Integrator board */ +/* - see board/integrator<>.c */ diff --git a/cpu/arm_intcm/start.S b/cpu/arm_intcm/start.S index d5778a046..75fe9174a 100644 --- a/cpu/arm_intcm/start.S +++ b/cpu/arm_intcm/start.S @@ -165,7 +165,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -339,7 +339,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -348,7 +348,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else diff --git a/cpu/bf533/Makefile b/cpu/bf533/Makefile new file mode 100644 index 000000000..c63a8f6d0 --- /dev/null +++ b/cpu/bf533/Makefile @@ -0,0 +1,46 @@ +# U-boot - Makefile +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o start1.o interrupt.o cache.o cplbhdlr.o cplbmgr.o flush.o +OBJS = cpu.o traps.o ints.o serial.o interrupts.o + +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h new file mode 100644 index 000000000..d430e6cab --- /dev/null +++ b/cpu/bf533/bf533_serial.h @@ -0,0 +1,78 @@ +/* + * U-boot - bf533_serial.h Serial Driver defines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver. + * Copyright (C) 2003 Bas Vermeulen + * BuyWays B.V. (www.buyways.nl) + * + * Based heavily on: + * blkfinserial.h: Definitions for the BlackFin DSP serial driver. + * + * Copyright (C) 2001 Tony Z. Kou tonyko@arcturusnetworks.com + * Copyright (C) 2001 Arcturus Networks Inc. + * + * Based on code from 68328serial.c which was: + * Copyright (C) 1995 David S. Miller + * Copyright (C) 1998 Kenneth Albanowski + * Copyright (C) 1998, 1999 D. Jeff Dionne + * Copyright (C) 1999 Vladimir Gurevich + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _Bf533_SERIAL_H +#define _Bf533_SERIAL_H + +#include +#include + +#define SYNC_ALL __asm__ __volatile__ ("ssync;\n") +#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; +#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); + +void serial_setbrg(void); +static void local_put_char(char ch); +void calc_baud(void); +void serial_setbrg(void); +int serial_init(void); +void serial_putc(const char c); +int serial_tstc(void); +int serial_getc(void); +void serial_puts(const char *s); +static void local_put_char(char ch); + +extern int get_clock(void); +int baud_table[5] = {9600, 19200, 38400, 57600, 115200}; + +struct { + unsigned char dl_high; + unsigned char dl_low; +} hw_baud_table[5]; + +#ifdef CONFIG_STAMP +extern unsigned long pll_div_fact; +#endif + +#endif diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S new file mode 100644 index 000000000..8fac40274 --- /dev/null +++ b/cpu/bf533/cache.S @@ -0,0 +1,125 @@ + + +#define ASSEMBLY +#include +#include + +.text +.align 2 +ENTRY(blackfin_icache_flush_range) + R2 = -32; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; +1: + IFLUSH[P0++]; + CC = P0 < P1(iu); + IF CC JUMP 1b(bp); + IFLUSH[P0]; + SSYNC; + RTS; + +ENTRY(blackfin_dcache_flush_range) + R2 = -32; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; +1: + FLUSH[P0++]; + CC = P0 < P1(iu); + IF CC JUMP 1b(bp); + FLUSH[P0]; + SSYNC; + RTS; + +ENTRY(_icache_invalidate) +ENTRY(invalidate_entire_icache) + [--SP] = ( R7:5); + + P0.L = (IMEM_CONTROL & 0xFFFF); + P0.H = (IMEM_CONTROL >> 16); + R7 = [P0]; + + /* Clear the IMC bit , All valid bits in the instruction + * cache are set to the invalid state + */ + BITCLR(R7,IMC_P); + CLI R6; + SSYNC; /* SSYNC required before invalidating cache. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + /* Configures the instruction cache agian */ + R6 = (IMC | ENICPLB); + R7 = R7 | R6; + + CLI R6; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + ( R7:5) = [SP++]; + RTS; + +/* Invalidate the Entire Data cache by + * clearing DMC[1:0] bits + */ +ENTRY(invalidate_entire_dcache) +ENTRY(_dcache_invalidate) + [--SP] = ( R7:6); + + P0.L = (DMEM_CONTROL & 0xFFFF); + P0.H = (DMEM_CONTROL >> 16); + R7 = [P0]; + + /* Clear the DMC[1:0] bits, All valid bits in the data + * cache are set to the invalid state + */ + BITCLR(R7,DMC0_P); + BITCLR(R7,DMC1_P); + CLI R6; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + /* Configures the data cache again */ + + R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0); + R7 = R7 | R6; + + CLI R6; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + ( R7:6) = [SP++]; + RTS; + +ENTRY(blackfin_dcache_invalidate_range) + R2 = -32; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; +1: + FLUSHINV[P0++]; + CC = P0 < P1 (iu); + IF CC JUMP 1b (bp); + + /* If the data crosses a cache line, then we'll be pointing to + ** the last cache line, but won't have flushed/invalidated it yet, so do + ** one more. + */ + FLUSHINV[P0]; + SSYNC; + RTS; diff --git a/cpu/bf533/config.mk b/cpu/bf533/config.mk new file mode 100644 index 000000000..a9d529ecd --- /dev/null +++ b/cpu/bf533/config.mk @@ -0,0 +1,27 @@ +# U-boot - config.mk +# +# Copyright (c) 2005 blackfin.uclinux.org +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-P5 diff --git a/cpu/bf533/cplbhdlr.S b/cpu/bf533/cplbhdlr.S new file mode 100644 index 000000000..61be5bb90 --- /dev/null +++ b/cpu/bf533/cplbhdlr.S @@ -0,0 +1,193 @@ +/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + */ + + +/* Include an exception handler to invoke the CPLB manager + */ + +#include +#include +#include + + +.text + +.globl _cplb_hdr; +.type _cplb_hdr, STT_FUNC; +.extern _cplb_mgr; +.type _cplb_mgr, STT_FUNC; +.extern __unknown_exception_occurred; +.type __unknown_exception_occurred, STT_FUNC; +.extern __cplb_miss_all_locked; +.type __cplb_miss_all_locked, STT_FUNC; +.extern __cplb_miss_without_replacement; +.type __cplb_miss_without_replacement, STT_FUNC; +.extern __cplb_protection_violation; +.type __cplb_protection_violation, STT_FUNC; +.extern panic_pv; + +.align 2; + +ENTRY(_cplb_hdr) + SSYNC; + [--SP] = ( R7:0, P5:0 ); + [--SP] = ASTAT; + [--SP] = SEQSTAT; + [--SP] = I0; + [--SP] = I1; + [--SP] = I2; + [--SP] = I3; + [--SP] = LT0; + [--SP] = LB0; + [--SP] = LC0; + [--SP] = LT1; + [--SP] = LB1; + [--SP] = LC1; + R2 = SEQSTAT; + + /*Mask the contents of SEQSTAT and leave only EXCAUSE in R2*/ + R2 <<= 26; + R2 >>= 26; + + R1 = 0x23; /* Data access CPLB protection violation */ + CC = R2 == R1; + IF !CC JUMP not_data_write; + R0 = 2; /* is a write to data space*/ + JUMP is_icplb_miss; + +not_data_write: + R1 = 0x2C; /* CPLB miss on an instruction fetch */ + CC = R2 == R1; + R0 = 0; /* is_data_miss == False*/ + IF CC JUMP is_icplb_miss; + + R1 = 0x26; + CC = R2 == R1; + IF !CC JUMP unknown; + + R0 = 1; /* is_data_miss == True*/ + +is_icplb_miss: + +#if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE)) +#if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE)) + R1 = CPLB_ENABLE_ICACHE; +#endif +#if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE)) + R1 = CPLB_ENABLE_DCACHE; +#endif +#if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE)) + R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; +#endif +#else + R1 = 0; +#endif + + [--SP] = RETS; + CALL _cplb_mgr; + RETS = [SP++]; + CC = R0 == 0; + IF !CC JUMP not_replaced; + LC1 = [SP++]; + LB1 = [SP++]; + LT1 = [SP++]; + LC0 = [SP++]; + LB0 = [SP++]; + LT0 = [SP++]; + I3 = [SP++]; + I2 = [SP++]; + I1 = [SP++]; + I0 = [SP++]; + SEQSTAT = [SP++]; + ASTAT = [SP++]; + ( R7:0, P5:0 ) = [SP++]; + RTS; + +unknown: + [--SP] = RETS; + CALL __unknown_exception_occurred; + RETS = [SP++]; + JUMP unknown; +not_replaced: + CC = R0 == CPLB_NO_UNLOCKED; + IF !CC JUMP next_check; + [--SP] = RETS; + CALL __cplb_miss_all_locked; + RETS = [SP++]; +next_check: + CC = R0 == CPLB_NO_ADDR_MATCH; + IF !CC JUMP next_check2; + [--SP] = RETS; + CALL __cplb_miss_without_replacement; + RETS = [SP++]; + JUMP not_replaced; +next_check2: + CC = R0 == CPLB_PROT_VIOL; + IF !CC JUMP strange_return_from_cplb_mgr; + [--SP] = RETS; + CALL __cplb_protection_violation; + RETS = [SP++]; + JUMP not_replaced; +strange_return_from_cplb_mgr: + IDLE; + CSYNC; + JUMP strange_return_from_cplb_mgr; + +/************************************ + * Diagnostic exception handlers + */ + +__cplb_miss_all_locked: + sp += -12; + R0 = CPLB_NO_UNLOCKED; + call panic_bfin; + SP += 12; + RTS; + + __cplb_miss_without_replacement: + sp += -12; + R0 = CPLB_NO_ADDR_MATCH; + call panic_bfin; + SP += 12; + RTS; + +__cplb_protection_violation: + sp += -12; + R0 = CPLB_PROT_VIOL; + call panic_bfin; + SP += 12; + RTS; + +__unknown_exception_occurred: + + /* This function is invoked by the default exception + * handler, if it does not recognise the kind of + * exception that has occurred. In other words, the + * default handler only handles some of the system's + * exception types, and it does not expect any others + * to occur. If your application is going to be using + * other kinds of exceptions, you must replace the + * default handler with your own, that handles all the + * exceptions you will use. + * + * Since there's nothing we can do, we just loop here + * at what we hope is a suitably informative label. + */ + + IDLE; +do_not_know_what_to_do: + CSYNC; + JUMP __unknown_exception_occurred; + + RTS; +.__unknown_exception_occurred.end: +.global __unknown_exception_occurred; +.type __unknown_exception_occurred, STT_FUNC; + +panic_bfin: + RTS; diff --git a/cpu/bf533/cplbmgr.S b/cpu/bf533/cplbmgr.S new file mode 100644 index 000000000..7a0b04862 --- /dev/null +++ b/cpu/bf533/cplbmgr.S @@ -0,0 +1,601 @@ +/*This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + * Modification: Dec 07 2004 + * 1. Correction in icheck_lock. Valid lock entries were + * geting victimized, for instruction cplb replacement. + * 2. Setup loop's are modified as now toolchain support's P Indexed + * addressing + * :LG Soft India + * + */ + +/* Usage: int _cplb_mgr(is_data_miss,int enable_cache) + * is_data_miss==2 => Mark as Dirty, write to the clean data page + * is_data_miss==1 => Replace a data CPLB. + * is_data_miss==0 => Replace an instruction CPLB. + * + * Returns: + * CPLB_RELOADED => Successfully updated CPLB table. + * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.This indicates + * that the CPLBs in the configuration tablei are badly + * configured, as this should never occur. + * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the exception, + * is not covered by any of the CPLBs in the configuration + * table. The application isi presumably misbehaving. + * CPLB_PROT_VIOL => The address being accessed, that triggered thei exception, + * was not a first-write to a clean Write Back Data page, + * and so presumably is a genuine violation of the page's + * protection attributes. The application is misbehaving. + */ +#define ASSEMBLY + +#include +#include +#include +#include + +.text + +.align 2; +ENTRY(_cplb_mgr) + + [--SP]=( R7:0,P5:0 ); + + CC = R0 == 2; + IF CC JUMP dcplb_write; + + CC = R0 == 0; + IF !CC JUMP dcplb_miss_compare; + + /* ICPLB Miss Exception. We need to choose one of the + * currently-installed CPLBs, and replace it with one + * from the configuration table. + */ + + P4.L = (ICPLB_FAULT_ADDR & 0xFFFF); + P4.H = (ICPLB_FAULT_ADDR >> 16); + + P1 = 16; + P5.L = page_size_table; + P5.H = page_size_table; + + P0.L = (ICPLB_DATA0 & 0xFFFF); + P0.H = (ICPLB_DATA0 >> 16); + R4 = [P4]; /* Get faulting address*/ + R6 = 64; /* Advance past the fault address, which*/ + R6 = R6 + R4; /* we'll use if we find a match*/ + R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/ + + R5 = 0; +isearch: + + R1 = [P0-0x100]; /* Address for this CPLB */ + + R0 = [P0++]; /* Info for this CPLB*/ + CC = BITTST(R0,0); /* Is the CPLB valid?*/ + IF !CC JUMP nomatch; /* Skip it, if not.*/ + CC = R4 < R1(IU); /* If fault address less than page start*/ + IF CC JUMP nomatch; /* then skip this one.*/ + R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/ + P1 = R2; + P1 = P5 + (P1<<2); /* index into page-size table*/ + R2 = [P1]; /* Get the page size*/ + R1 = R1 + R2; /* and add to page start, to get page end*/ + CC = R4 < R1(IU); /* and see whether fault addr is in page.*/ + IF !CC R4 = R6; /* If so, advance the address and finish loop.*/ + IF !CC JUMP isearch_done; +nomatch: + /* Go around again*/ + R5 += 1; + CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/ + IF !CC JUMP isearch; + +isearch_done: + I0 = R4; /* Fault address we'll search for*/ + + /* set up pointers */ + P0.L = (ICPLB_DATA0 & 0xFFFF); + P0.H = (ICPLB_DATA0 >> 16); + + /* The replacement procedure for ICPLBs */ + + P4.L = (IMEM_CONTROL & 0xFFFF); + P4.H = (IMEM_CONTROL >> 16); + + /* disable cplbs */ + R5 = [P4]; /* Control Register*/ + BITCLR(R5,ENICPLB_P); + CLI R1; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P4] = R5; + SSYNC; + STI R1; + + R1 = -1; /* end point comparison */ + R3 = 16; /* counter */ + + /* Search through CPLBs for first non-locked entry */ + /* Overwrite it by moving everyone else up by 1 */ +icheck_lock: + R0 = [P0++]; + R3 = R3 + R1; + CC = R3 == R1; + IF CC JUMP all_locked; + CC = BITTST(R0, 0); /* an invalid entry is good */ + IF !CC JUMP ifound_victim; + CC = BITTST(R0,1); /* but a locked entry isn't */ + IF CC JUMP icheck_lock; + +ifound_victim: +#ifdef CONFIG_CPLB_INFO + R7 = [P0 - 0x104]; + P2.L = ipdt_table; + P2.H = ipdt_table; + P3.L = ipdt_swapcount_table; + P3.H = ipdt_swapcount_table; + P3 += -4; +icount: + R2 = [P2]; /* address from config table */ + P2 += 8; + P3 += 8; + CC = R2==-1; + IF CC JUMP icount_done; + CC = R7==R2; + IF !CC JUMP icount; + R7 = [P3]; + R7 += 1; + [P3] = R7; + CSYNC; +icount_done: +#endif + LC0=R3; + LSETUP(is_move,ie_move) LC0; +is_move: + R0 = [P0]; + [P0 - 4] = R0; + R0 = [P0 - 0x100]; + [P0-0x104] = R0; +ie_move:P0+=4; + + /* We've made space in the ICPLB table, so that ICPLB15 + * is now free to be overwritten. Next, we have to determine + * which CPLB we need to install, from the configuration + * table. This is a matter of getting the start-of-page + * addresses and page-lengths from the config table, and + * determining whether the fault address falls within that + * range. + */ + + P2.L = ipdt_table; + P2.H = ipdt_table; +#ifdef CONFIG_CPLB_INFO + P3.L = ipdt_swapcount_table; + P3.H = ipdt_swapcount_table; + P3 += -8; +#endif + P0.L = page_size_table; + P0.H = page_size_table; + + /* Retrieve our fault address (which may have been advanced + * because the faulting instruction crossed a page boundary). + */ + + R0 = I0; + + /* An extraction pattern, to get the page-size bits from + * the CPLB data entry. Bits 16-17, so two bits at posn 16. + */ + + R1 = ((16<<8)|2); +inext: R4 = [P2++]; /* address from config table */ + R2 = [P2++]; /* data from config table */ +#ifdef CONFIG_CPLB_INFO + P3 += 8; +#endif + + CC = R4 == -1; /* End of config table*/ + IF CC JUMP no_page_in_table; + + /* See if failed address > start address */ + CC = R4 <= R0(IU); + IF !CC JUMP inext; + + /* extract page size (17:16)*/ + R3 = EXTRACT(R2, R1.L) (Z); + + /* add page size to addr to get range */ + + P5 = R3; + P5 = P0 + (P5 << 2); /* scaled, for int access*/ + R3 = [P5]; + R3 = R3 + R4; + + /* See if failed address < (start address + page size) */ + CC = R0 < R3(IU); + IF !CC JUMP inext; + + /* We've found a CPLB in the config table that covers + * the faulting address, so install this CPLB into the + * last entry of the table. + */ + + P1.L = (ICPLB_DATA15 & 0xFFFF); /*ICPLB_DATA15*/ + P1.H = (ICPLB_DATA15 >> 16); + [P1] = R2; + [P1-0x100] = R4; +#ifdef CONFIG_CPLB_INFO + R3 = [P3]; + R3 += 1; + [P3] = R3; +#endif + + /* P4 points to IMEM_CONTROL, and R5 contains its old + * value, after we disabled ICPLBS. Re-enable them. + */ + + BITSET(R5,ENICPLB_P); + CLI R2; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P4] = R5; + SSYNC; + STI R2; + + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_RELOADED; + RTS; + +/* FAILED CASES*/ +no_page_in_table: + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_NO_ADDR_MATCH; + RTS; +all_locked: + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_NO_UNLOCKED; + RTS; +prot_violation: + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_PROT_VIOL; + RTS; + +dcplb_write: + + /* if a DCPLB is marked as write-back (CPLB_WT==0), and + * it is clean (CPLB_DIRTY==0), then a write to the + * CPLB's page triggers a protection violation. We have to + * mark the CPLB as dirty, to indicate that there are + * pending writes associated with the CPLB. + */ + + P4.L = (DCPLB_STATUS & 0xFFFF); + P4.H = (DCPLB_STATUS >> 16); + P3.L = (DCPLB_DATA0 & 0xFFFF); + P3.H = (DCPLB_DATA0 >> 16); + R5 = [P4]; + + /* A protection violation can be caused by more than just writes + * to a clean WB page, so we have to ensure that: + * - It's a write + * - to a clean WB page + * - and is allowed in the mode the access occurred. + */ + + CC = BITTST(R5, 16); /* ensure it was a write*/ + IF !CC JUMP prot_violation; + + /* to check the rest, we have to retrieve the DCPLB.*/ + + /* The low half of DCPLB_STATUS is a bit mask*/ + + R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/ + R3 = 30; /* so we can use this to determine the offset*/ + R2.L = SIGNBITS R2; + R2 = R2.L (Z); /* into the DCPLB table.*/ + R3 = R3 - R2; + P4 = R3; + P3 = P3 + (P4<<2); + R3 = [P3]; /* Retrieve the CPLB*/ + + /* Now we can check whether it's a clean WB page*/ + + CC = BITTST(R3, 14); /* 0==WB, 1==WT*/ + IF CC JUMP prot_violation; + CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/ + IF CC JUMP prot_violation; + + /* Check whether the write is allowed in the mode that was active.*/ + + R2 = 1<<3; /* checking write in user mode*/ + CC = BITTST(R5, 17); /* 0==was user, 1==was super*/ + R5 = CC; + R2 <<= R5; /* if was super, check write in super mode*/ + R2 = R3 & R2; + CC = R2 == 0; + IF CC JUMP prot_violation; + + /* It's a genuine write-to-clean-page.*/ + + BITSET(R3, 7); /* mark as dirty*/ + [P3] = R3; /* and write back.*/ + CSYNC; + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_RELOADED; + RTS; + +dcplb_miss_compare: + + /* Data CPLB Miss event. We need to choose a CPLB to + * evict, and then locate a new CPLB to install from the + * config table, that covers the faulting address. + */ + + P1.L = (DCPLB_DATA15 & 0xFFFF); + P1.H = (DCPLB_DATA15 >> 16); + + P4.L = (DCPLB_FAULT_ADDR & 0xFFFF); + P4.H = (DCPLB_FAULT_ADDR >> 16); + R4 = [P4]; + I0 = R4; + + /* The replacement procedure for DCPLBs*/ + + R6 = R1; /* Save for later*/ + + /* Turn off CPLBs while we work.*/ + P4.L = (DMEM_CONTROL & 0xFFFF); + P4.H = (DMEM_CONTROL >> 16); + R5 = [P4]; + BITCLR(R5,ENDCPLB_P); + CLI R0; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P4] = R5; + SSYNC; + STI R0; + + /* Start looking for a CPLB to evict. Our order of preference + * is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs + * are no good. + */ + + I1.L = (DCPLB_DATA0 & 0xFFFF); + I1.H = (DCPLB_DATA0 >> 16); + P1 = 3; + P2 = 16; + I2.L = dcplb_preference; + I2.H = dcplb_preference; + LSETUP(sdsearch1, edsearch1) LC0 = P1; +sdsearch1: + R0 = [I2++]; /* Get the bits we're interested in*/ + P0 = I1; /* Go back to start of table*/ + LSETUP (sdsearch2, edsearch2) LC1 = P2; +sdsearch2: + R1 = [P0++]; /* Fetch each installed CPLB in turn*/ + R2 = R1 & R0; /* and test for interesting bits.*/ + CC = R2 == 0; /* If none are set, it'll do.*/ + IF !CC JUMP skip_stack_check; + + R2 = [P0 - 0x104]; /* R2 - PageStart */ + P3.L = page_size_table; /* retrive end address */ + P3.H = page_size_table; /* retrive end address */ + R3 = 0x2; /* 0th - position, 2 bits -length */ + nop; /*Anamoly 05000209*/ + R7 = EXTRACT(R1,R3.l); + R7 = R7 << 2; /* Page size index offset */ + P5 = R7; + P3 = P3 + P5; + R7 = [P3]; /* page size in 1K bytes */ + + R7 = R7 << 0xA; /* in bytes * 1024*/ + R7 = R2 + R7; /* R7 - PageEnd */ + R4 = SP; /* Test SP is in range */ + + CC = R7 < R4; /* if PageEnd < SP */ + IF CC JUMP dfound_victim; + R3 = 0x284; /* stack length from start of trap till the point */ + /* 20 stack locations for future modifications */ + R4 = R4 + R3; + CC = R4 < R2; /* if SP + stacklen < PageStart */ + IF CC JUMP dfound_victim; +skip_stack_check: + +edsearch2: NOP; +edsearch1: NOP; + + /* If we got here, we didn't find a DCPLB we considered + * replacable, which means all of them were locked. + */ + + JUMP all_locked; +dfound_victim: + +#ifdef CONFIG_CPLB_INFO + R1 = [P0 - 0x104]; + P2.L = dpdt_table; + P2.H = dpdt_table; + P3.L = dpdt_swapcount_table; + P3.H = dpdt_swapcount_table; + P3 += -4; +dicount: + R2 = [P2]; + P2 += 8; + P3 += 8; + CC = R2==-1; + IF CC JUMP dicount_done; + CC = R1==R2; + IF !CC JUMP dicount; + R1 = [P3]; + R1 += 1; + [P3] = R1; + CSYNC; +dicount_done: +#endif + + /* Clean down the hardware loops*/ + R2 = 0; + LC1 = R2; + LC0 = R2; + + /* There's a suitable victim in [P0-4] (because we've + * advanced already). If it's a valid dirty write-back + * CPLB, we need to flush the pending writes first. + */ + + CC = BITTST(R1, 0); /* Is it valid?*/ + IF !CC JUMP Ddoverwrite;/* nope.*/ + CC = BITTST(R1, 7); /* Is it dirty?*/ + IF !CC JUMP Ddoverwrite (BP); /* Nope.*/ + CC = BITTST(R1, 14); /* Is it Write-Through?*/ + IF CC JUMP Ddoverwrite; /* Yep*/ + + /* This is a dirty page, so we need to flush all writes + * that are pending on the page. + */ + + /* Retrieve the page start address*/ + R0 = [P0 - 0x104]; + [--sp] = rets; + CALL dcplb_flush; /* R0==CPLB addr, R1==CPLB data*/ + rets = [sp++]; +Ddoverwrite: + + /* [P0-4] is a suitable victim CPLB, so we want to + * overwrite it by moving all the following CPLBs + * one space closer to the start. + */ + + R1.L = ((DCPLB_DATA15+4) & 0xFFFF); /*DCPLB_DATA15+4*/ + R1.H = ((DCPLB_DATA15+4) >> 16); + R0 = P0; + + /* If the victim happens to be in DCPLB15, + * we don't need to move anything. + */ + + CC = R1 == R0; + IF CC JUMP de_moved; + R1 = R1 - R0; + R1 >>= 2; + P1 = R1; + LSETUP(ds_move, de_move) LC0=P1; +ds_move: + R0 = [P0++]; /* move data */ + [P0 - 8] = R0; + R0 = [P0-0x104] /* move address */ +de_move: [P0-0x108] = R0; + + /* We've now made space in DCPLB15 for the new CPLB to be + * installed. The next stage is to locate a CPLB in the + * config table that covers the faulting address. + */ + +de_moved:NOP; + R0 = I0; /* Our faulting address */ + + P2.L = dpdt_table; + P2.H = dpdt_table; +#ifdef CONFIG_CPLB_INFO + P3.L = dpdt_swapcount_table; + P3.H = dpdt_swapcount_table; + P3 += -8; +#endif + + P1.L = page_size_table; + P1.H = page_size_table; + + /* An extraction pattern, to retrieve bits 17:16.*/ + + R1 = (16<<8)|2; +dnext: R4 = [P2++]; /* address */ + R2 = [P2++]; /* data */ +#ifdef CONFIG_CPLB_INFO + P3 += 8; +#endif + + CC = R4 == -1; + IF CC JUMP no_page_in_table; + + /* See if failed address > start address */ + CC = R4 <= R0(IU); + IF !CC JUMP dnext; + + /* extract page size (17:16)*/ + R3 = EXTRACT(R2, R1.L) (Z); + + /* add page size to addr to get range */ + + P5 = R3; + P5 = P1 + (P5 << 2); + R3 = [P5]; + R3 = R3 + R4; + + /* See if failed address < (start address + page size) */ + CC = R0 < R3(IU); + IF !CC JUMP dnext; + + /* We've found the CPLB that should be installed, so + * write it into CPLB15, masking off any caching bits + * if necessary. + */ + + P1.L = (DCPLB_DATA15 & 0xFFFF); + P1.H = (DCPLB_DATA15 >> 16); + + /* If the DCPLB has cache bits set, but caching hasn't + * been enabled, then we want to mask off the cache-in-L1 + * bit before installing. Moreover, if caching is off, we + * also want to ensure that the DCPLB has WT mode set, rather + * than WB, since WB pages still trigger first-write exceptions + * even when not caching is off, and the page isn't marked as + * cachable. Finally, we could mark the page as clean, not dirty, + * but we choose to leave that decision to the user; if the user + * chooses to have a CPLB pre-defined as dirty, then they always + * pay the cost of flushing during eviction, but don't pay the + * cost of first-write exceptions to mark the page as dirty. + */ + +#ifdef CONFIG_BLKFIN_WT + BITSET(R6, 14); /* Set WT*/ +#endif + + [P1] = R2; + [P1-0x100] = R4; +#ifdef CONFIG_CPLB_INFO + R3 = [P3]; + R3 += 1; + [P3] = R3; +#endif + + /* We've installed the CPLB, so re-enable CPLBs. P4 + * points to DMEM_CONTROL, and R5 is the value we + * last wrote to it, when we were disabling CPLBs. + */ + + BITSET(R5,ENDCPLB_P); + CLI R2; + .align 8; + [P4] = R5; + SSYNC; + STI R2; + + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_RELOADED; + RTS; + +.data +.align 4; +page_size_table: +.byte4 0x00000400; /* 1K */ +.byte4 0x00001000; /* 4K */ +.byte4 0x00100000; /* 1M */ +.byte4 0x00400000; /* 4M */ + +.align 4; +dcplb_preference: +.byte4 0x00000001; /* valid bit */ +.byte4 0x00000082; /* dirty+lock bits */ +.byte4 0x00000002; /* lock bit */ diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c new file mode 100644 index 000000000..78e2b966b --- /dev/null +++ b/cpu/bf533/cpu.c @@ -0,0 +1,189 @@ +/* + * U-boot - cpu.c CPU specific functions + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#define SSYNC() asm("ssync;") +#define CACHE_ON 1 +#define CACHE_OFF 0 + +/* Data Attibutes*/ + +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) + +#define ANOMALY_05000158 0x200 +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) + +static unsigned int icplb_table[16][2]={ + {0xFFA00000, L1_IMEMORY}, + {0x00000000, SDRAM_IKERNEL}, /*SDRAM_Page1*/ + {0x00400000, SDRAM_IKERNEL}, /*SDRAM_Page1*/ + {0x07C00000, SDRAM_IKERNEL}, /*SDRAM_Page14*/ + {0x00800000, SDRAM_IGENERIC}, /*SDRAM_Page2*/ + {0x00C00000, SDRAM_IGENERIC}, /*SDRAM_Page2*/ + {0x01000000, SDRAM_IGENERIC}, /*SDRAM_Page4*/ + {0x01400000, SDRAM_IGENERIC}, /*SDRAM_Page5*/ + {0x01800000, SDRAM_IGENERIC}, /*SDRAM_Page6*/ + {0x01C00000, SDRAM_IGENERIC}, /*SDRAM_Page7*/ + {0x02000000, SDRAM_IGENERIC}, /*SDRAM_Page8*/ + {0x02400000, SDRAM_IGENERIC}, /*SDRAM_Page9*/ + {0x02800000, SDRAM_IGENERIC}, /*SDRAM_Page10*/ + {0x02C00000, SDRAM_IGENERIC}, /*SDRAM_Page11*/ + {0x03000000, SDRAM_IGENERIC}, /*SDRAM_Page12*/ + {0x03400000, SDRAM_IGENERIC}, /*SDRAM_Page13*/ +}; + +static unsigned int dcplb_table[16][2]={ + {0xFFA00000,L1_DMEMORY}, + {0x00000000,SDRAM_DKERNEL}, /*SDRAM_Page1*/ + {0x00400000,SDRAM_DKERNEL}, /*SDRAM_Page1*/ + {0x07C00000,SDRAM_DKERNEL}, /*SDRAM_Page15*/ + {0x00800000,SDRAM_DGENERIC}, /*SDRAM_Page2*/ + {0x00C00000,SDRAM_DGENERIC}, /*SDRAM_Page3*/ + {0x01000000,SDRAM_DGENERIC}, /*SDRAM_Page4*/ + {0x01400000,SDRAM_DGENERIC}, /*SDRAM_Page5*/ + {0x01800000,SDRAM_DGENERIC}, /*SDRAM_Page6*/ + {0x01C00000,SDRAM_DGENERIC}, /*SDRAM_Page7*/ + {0x02000000,SDRAM_DGENERIC}, /*SDRAM_Page8*/ + {0x02400000,SDRAM_DGENERIC}, /*SDRAM_Page9*/ + {0x02800000,SDRAM_DGENERIC}, /*SDRAM_Page10*/ + {0x02C00000,SDRAM_DGENERIC}, /*SDRAM_Page11*/ + {0x03000000,SDRAM_DGENERIC}, /*SDRAM_Page12*/ + {0x20000000,SDRAM_EBIU}, /*For Network */ +}; + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + __asm__ __volatile__ + ("cli r3;" + "P0 = %0;" + "JUMP (P0);" + : + : "r" (L1_ISRAM) + ); + + return 0; +} + +/* These functions are just used to satisfy the linker */ +int cpu_init(void) +{ + return 0; +} + +int cleanup_before_linux(void) +{ + return 0; +} + +void icache_enable(void) +{ + unsigned int *I0,*I1; + int i; + + I0 = (unsigned int *)ICPLB_ADDR0; + I1 = (unsigned int *)ICPLB_DATA0; + + for(i=0;i<16;i++){ + *I0++ = icplb_table[i][0]; + *I1++ = icplb_table[i][1]; + } + cli(); + SSYNC(); + *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; + SSYNC(); + sti(); +} + +void icache_disable(void) +{ + cli(); + SSYNC(); + *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); + SSYNC(); + sti(); +} + +int icache_status(void) +{ + unsigned int value; + value = *(unsigned int *)IMEM_CONTROL; + + if( value & (IMC|ENICPLB) ) + return CACHE_ON; + else + return CACHE_OFF; +} + +void dcache_enable(void) +{ + unsigned int *I0,*I1; + unsigned int temp; + int i; + I0 = (unsigned int *)DCPLB_ADDR0; + I1 = (unsigned int *)DCPLB_DATA0; + + for(i=0;i<16;i++){ + *I0++ = dcplb_table[i][0]; + *I1++ = dcplb_table[i][1]; + } + cli(); + temp = *(unsigned int *)DMEM_CONTROL; + SSYNC(); + *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp; + SSYNC(); + sti(); +} + +void dcache_disable(void) +{ + cli(); + SSYNC(); + *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE |ENDCPLB |PORT_PREF0); + SSYNC(); + sti(); +} + +int dcache_status(void) +{ + unsigned int value; + value = *(unsigned int *)DMEM_CONTROL; + if( value & (ENDCPLB)) + return CACHE_ON; + else + return CACHE_OFF; +} diff --git a/cpu/bf533/cpu.h b/cpu/bf533/cpu.h new file mode 100644 index 000000000..7ec33878e --- /dev/null +++ b/cpu/bf533/cpu.h @@ -0,0 +1,65 @@ +/* + * U-boot - cpu.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CPU_H_ +#define _CPU_H_ + +#include + +#define INTERNAL_IRQS (32) +#define NUM_IRQ_NODES 16 +#define DEF_INTERRUPT_FLAGS 1 +#define MAX_TIM_LOAD 0xFFFFFFFF + +void blackfin_irq_panic(int reason, struct pt_regs * reg); +extern void dump(struct pt_regs * regs); +void display_excp(void); +asmlinkage void evt_nmi(void); +asmlinkage void evt_exception(void); +asmlinkage void trap(void); +asmlinkage void evt_ivhw(void); +asmlinkage void evt_rst(void); +asmlinkage void evt_timer(void); +asmlinkage void evt_evt7(void); +asmlinkage void evt_evt8(void); +asmlinkage void evt_evt9(void); +asmlinkage void evt_evt10(void); +asmlinkage void evt_evt11(void); +asmlinkage void evt_evt12(void); +asmlinkage void evt_evt13(void); +asmlinkage void evt_soft_int1(void); +asmlinkage void evt_system_call(void); +void blackfin_irq_panic(int reason, struct pt_regs * regs); +void blackfin_free_irq(unsigned int irq, void *dev_id); +void call_isr(int irq, struct pt_regs * fp); +void blackfin_do_irq(int vec, struct pt_regs *fp); +void blackfin_init_IRQ(void); +void blackfin_enable_irq(unsigned int irq); +void blackfin_disable_irq(unsigned int irq); +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +int blackfin_request_irq(unsigned int irq, + void (*handler)(int, void *, struct pt_regs *), + unsigned long flags,const char *devname,void *dev_id); +void timer_init(void); +#endif diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S new file mode 100644 index 000000000..9fbdefc9d --- /dev/null +++ b/cpu/bf533/flush.S @@ -0,0 +1,402 @@ +/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. + * Copyright (C) 2004 LG SOft India. All Rights Reserved. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + */ +#define ASSEMBLY + +#include +#include +#include + +.text + +/* This is an external function being called by the user + * application through __flush_cache_all. Currently this function + * serves the purpose of flushing all the pending writes in + * in the instruction cache. + */ + +ENTRY(flush_instruction_cache) + [--SP] = ( R7:6, P5:4 ); + LINK 12; + SP += -12; + P5.H = (ICPLB_ADDR0 >> 16); + P5.L = (ICPLB_ADDR0 & 0xFFFF); + P4.H = (ICPLB_DATA0 >> 16); + P4.L = (ICPLB_DATA0 & 0xFFFF); + R7 = CPLB_VALID | CPLB_L1_CHBL; + R6 = 16; +inext: R0 = [P5++]; + R1 = [P4++]; + [--SP] = RETS; + CALL icplb_flush; /* R0 = page, R1 = data*/ + RETS = [SP++]; +iskip: R6 += -1; + CC = R6; + IF CC JUMP inext; + SSYNC; + SP += 12; + UNLINK; + ( R7:6, P5:4 ) = [SP++]; + RTS; + +/* This is an internal function to flush all pending + * writes in the cache associated with a particular ICPLB. + * + * R0 - page's start address + * R1 - CPLB's data field. + */ + +.align 2 +ENTRY(icplb_flush) + [--SP] = ( R7:0, P5:0 ); + [--SP] = LC0; + [--SP] = LT0; + [--SP] = LB0; + [--SP] = LC1; + [--SP] = LT1; + [--SP] = LB1; + + /* If it's a 1K or 4K page, then it's quickest to + * just systematically flush all the addresses in + * the page, regardless of whether they're in the + * cache, or dirty. If it's a 1M or 4M page, there + * are too many addresses, and we have to search the + * cache for lines corresponding to the page. + */ + + CC = BITTST(R1, 17); /* 1MB or 4MB */ + IF !CC JUMP iflush_whole_page; + + /* We're only interested in the page's size, so extract + * this from the CPLB (bits 17:16), and scale to give an + * offset into the page_size and page_prefix tables. + */ + + R1 <<= 14; + R1 >>= 30; + R1 <<= 2; + + /* We can also determine the sub-bank used, because this is + * taken from bits 13:12 of the address. + */ + + R3 = ((12<<8)|2); /* Extraction pattern */ + nop; /*Anamoly 05000209*/ + R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ + R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/ + + + /* So: + * R0 = Page start + * R1 = Page length (actually, offset into size/prefix tables) + * R3 = sub-bank deposit values + * + * The cache has 2 Ways, and 64 sets, so we iterate through + * the sets, accessing the tag for each Way, for our Bank and + * sub-bank, looking for dirty, valid tags that match our + * address prefix. + */ + + P5.L = (ITEST_COMMAND & 0xFFFF); + P5.H = (ITEST_COMMAND >> 16); + P4.L = (ITEST_DATA0 & 0xFFFF); + P4.H = (ITEST_DATA0 >> 16); + + P0.L = page_prefix_table; + P0.H = page_prefix_table; + P1 = R1; + R5 = 0; /* Set counter*/ + P0 = P1 + P0; + R4 = [P0]; /* This is the address prefix*/ + + /* We're reading (bit 1==0) the tag (bit 2==0), and we + * don't care about which double-word, since we're only + * fetching tags, so we only have to set Set, Bank, + * Sub-bank and Way. + */ + + P2 = 4; + LSETUP (ifs1, ife1) LC1 = P2; +ifs1: P0 = 32; /* iterate over all sets*/ + LSETUP (ifs0, ife0) LC0 = P0; +ifs0: R6 = R5 << 5; /* Combine set*/ + R6.H = R3.H << 0 ; /* and sub-bank*/ + [P5] = R6; /* Issue Command*/ + SSYNC; /* CSYNC will not work here :(*/ + R7 = [P4]; /* and read Tag.*/ + CC = BITTST(R7, 0); /* Check if valid*/ + IF !CC JUMP ifskip; /* and skip if not.*/ + + /* Compare against the page address. First, plant bits 13:12 + * into the tag, since those aren't part of the returned data. + */ + + R7 = DEPOSIT(R7, R3); /* set 13:12*/ + R1 = R7 & R4; /* Mask off lower bits*/ + CC = R1 == R0; /* Compare against page start.*/ + IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/ + + /* Tag address matches against page, so this is an entry + * we must flush. + */ + + R7 >>= 10; /* Mask off the non-address bits*/ + R7 <<= 10; + P3 = R7; + IFLUSH [P3]; /* And flush the entry*/ +ifskip: +ife0: R5 += 1; /* Advance to next Set*/ +ife1: NOP; + +ifinished: + SSYNC; /* Ensure the data gets out to mem.*/ + + /*Finished. Restore context.*/ + LB1 = [SP++]; + LT1 = [SP++]; + LC1 = [SP++]; + LB0 = [SP++]; + LT0 = [SP++]; + LC0 = [SP++]; + ( R7:0, P5:0 ) = [SP++]; + RTS; + +iflush_whole_page: + /* It's a 1K or 4K page, so quicker to just flush the + * entire page. + */ + + P1 = 32; /* For 1K pages*/ + P2 = P1 << 2; /* For 4K pages*/ + P0 = R0; /* Start of page*/ + CC = BITTST(R1, 16); /* Whether 1K or 4K*/ + IF CC P1 = P2; + P1 += -1; /* Unroll one iteration*/ + SSYNC; + IFLUSH [P0++]; /* because CSYNC can't end loops.*/ + LSETUP (isall, ieall) LC0 = P1; +isall:IFLUSH [P0++]; +ieall: NOP; + SSYNC; + JUMP ifinished; + +/* This is an external function being called by the user + * application through __flush_cache_all. Currently this function + * serves the purpose of flushing all the pending writes in + * in the data cache. + */ + +ENTRY(flush_data_cache) + [--SP] = ( R7:6, P5:4 ); + LINK 12; + SP += -12; + P5.H = (DCPLB_ADDR0 >> 16); + P5.L = (DCPLB_ADDR0 & 0xFFFF); + P4.H = (DCPLB_DATA0 >> 16); + P4.L = (DCPLB_DATA0 & 0xFFFF); + R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z); + R6 = 16; +next: R0 = [P5++]; + R1 = [P4++]; + CC = BITTST(R1, 14); /* Is it write-through?*/ + IF CC JUMP skip; /* If so, ignore it.*/ + R2 = R1 & R7; /* Is it a dirty, cached page?*/ + CC = R2; + IF !CC JUMP skip; /* If not, ignore it.*/ + [--SP] = RETS; + CALL dcplb_flush; /* R0 = page, R1 = data*/ + RETS = [SP++]; +skip: R6 += -1; + CC = R6; + IF CC JUMP next; + SSYNC; + SP += 12; + UNLINK; + ( R7:6, P5:4 ) = [SP++]; + RTS; + +/* This is an internal function to flush all pending + * writes in the cache associated with a particular DCPLB. + * + * R0 - page's start address + * R1 - CPLB's data field. + */ + +.align 2 +ENTRY(dcplb_flush) + [--SP] = ( R7:0, P5:0 ); + [--SP] = LC0; + [--SP] = LT0; + [--SP] = LB0; + [--SP] = LC1; + [--SP] = LT1; + [--SP] = LB1; + + /* If it's a 1K or 4K page, then it's quickest to + * just systematically flush all the addresses in + * the page, regardless of whether they're in the + * cache, or dirty. If it's a 1M or 4M page, there + * are too many addresses, and we have to search the + * cache for lines corresponding to the page. + */ + + CC = BITTST(R1, 17); /* 1MB or 4MB */ + IF !CC JUMP dflush_whole_page; + + /* We're only interested in the page's size, so extract + * this from the CPLB (bits 17:16), and scale to give an + * offset into the page_size and page_prefix tables. + */ + + R1 <<= 14; + R1 >>= 30; + R1 <<= 2; + + /* The page could be mapped into Bank A or Bank B, depending + * on (a) whether both banks are configured as cache, and + * (b) on whether address bit A[x] is set. x is determined + * by DCBS in DMEM_CONTROL + */ + + R2 = 0; /* Default to Bank A (Bank B would be 1)*/ + + P0.L = (DMEM_CONTROL & 0xFFFF); + P0.H = (DMEM_CONTROL >> 16); + + R3 = [P0]; /* If Bank B is not enabled as cache*/ + CC = BITTST(R3, 2); /* then Bank A is our only option.*/ + IF CC JUMP bank_chosen; + + R4 = 1<<14; /* If DCBS==0, use A[14].*/ + R5 = R4 << 7; /* If DCBS==1, use A[23];*/ + CC = BITTST(R3, 4); + IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/ + R5 = R0 & R4; /* Use it to test the Page address*/ + CC = R5; /* and if that bit is set, we use Bank B,*/ + R2 = CC; /* else we use Bank A.*/ + R2 <<= 23; /* The Bank selection's at posn 23.*/ + +bank_chosen: + + /* We can also determine the sub-bank used, because this is + * taken from bits 13:12 of the address. + */ + + R3 = ((12<<8)|2); /* Extraction pattern */ + nop; /*Anamoly 05000209*/ + R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ + R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/ + + /* So: + * R0 = Page start + * R1 = Page length (actually, offset into size/prefix tables) + * R2 = Bank select mask + * R3 = sub-bank deposit values + * + * The cache has 2 Ways, and 64 sets, so we iterate through + * the sets, accessing the tag for each Way, for our Bank and + * sub-bank, looking for dirty, valid tags that match our + * address prefix. + */ + + P5.L = (DTEST_COMMAND & 0xFFFF); + P5.H = (DTEST_COMMAND >> 16); + P4.L = (DTEST_DATA0 & 0xFFFF); + P4.H = (DTEST_DATA0 >> 16); + + P0.L = page_prefix_table; + P0.H = page_prefix_table; + P1 = R1; + R5 = 0; /* Set counter*/ + P0 = P1 + P0; + R4 = [P0]; /* This is the address prefix*/ + + + /* We're reading (bit 1==0) the tag (bit 2==0), and we + * don't care about which double-word, since we're only + * fetching tags, so we only have to set Set, Bank, + * Sub-bank and Way. + */ + + P2 = 2; + LSETUP (fs1, fe1) LC1 = P2; +fs1: P0 = 64; /* iterate over all sets*/ + LSETUP (fs0, fe0) LC0 = P0; +fs0: R6 = R5 << 5; /* Combine set*/ + R6.H = R3.H << 0 ; /* and sub-bank*/ + R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/ + BITSET(R6,14); + [P5] = R6; /* Issue Command*/ + SSYNC; + R7 = [P4]; /* and read Tag.*/ + CC = BITTST(R7, 0); /* Check if valid*/ + IF !CC JUMP fskip; /* and skip if not.*/ + CC = BITTST(R7, 1); /* Check if dirty*/ + IF !CC JUMP fskip; /* and skip if not.*/ + + /* Compare against the page address. First, plant bits 13:12 + * into the tag, since those aren't part of the returned data. + */ + + R7 = DEPOSIT(R7, R3); /* set 13:12*/ + R1 = R7 & R4; /* Mask off lower bits*/ + CC = R1 == R0; /* Compare against page start.*/ + IF !CC JUMP fskip; /* Skip it if it doesn't match.*/ + + /* Tag address matches against page, so this is an entry + * we must flush. + */ + + R7 >>= 10; /* Mask off the non-address bits*/ + R7 <<= 10; + P3 = R7; + SSYNC; + FLUSHINV [P3]; /* And flush the entry*/ +fskip: +fe0: R5 += 1; /* Advance to next Set*/ +fe1: BITSET(R2, 26); /* Go to next Way.*/ + +dfinished: + SSYNC; /* Ensure the data gets out to mem.*/ + + /*Finished. Restore context.*/ + LB1 = [SP++]; + LT1 = [SP++]; + LC1 = [SP++]; + LB0 = [SP++]; + LT0 = [SP++]; + LC0 = [SP++]; + ( R7:0, P5:0 ) = [SP++]; + RTS; + +dflush_whole_page: + + /* It's a 1K or 4K page, so quicker to just flush the + * entire page. + */ + + P1 = 32; /* For 1K pages*/ + P2 = P1 << 2; /* For 4K pages*/ + P0 = R0; /* Start of page*/ + CC = BITTST(R1, 16); /* Whether 1K or 4K*/ + IF CC P1 = P2; + P1 += -1; /* Unroll one iteration*/ + SSYNC; + FLUSHINV [P0++]; /* because CSYNC can't end loops.*/ + LSETUP (eall, eall) LC0 = P1; +eall: FLUSHINV [P0++]; + SSYNC; + JUMP dfinished; + +.align 4; +page_prefix_table: +.byte4 0xFFFFFC00; /* 1K */ +.byte4 0xFFFFF000; /* 4K */ +.byte4 0xFFF00000; /* 1M */ +.byte4 0xFFC00000; /* 4M */ +.page_prefix_table.end: diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S new file mode 100644 index 000000000..e780dc6d6 --- /dev/null +++ b/cpu/bf533/interrupt.S @@ -0,0 +1,391 @@ +/* + * U-boot - interrupt.S Processing of interrupts and exception handling + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This file is based on interrupt.S + * + * Copyright (C) 2003 Metrowerks, Inc. + * Copyright (C) 2002 Arcturus Networks Ltd. Ted Ma + * Copyright (C) 1998 D. Jeff Dionne , + * Kenneth Albanowski , + * The Silver Hammer Group, Ltd. + * + * (c) 1995, Dionne & Associates + * (c) 1995, DKG Display Tech. + * + * This file is also based on exception.asm + * (C) Copyright 2001-2005 - Analog Devices, Inc. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define ASSEMBLY + +#include +#include +#include +#include + +.global blackfin_irq_panic; + +.text +.align 2 + +#ifndef CONFIG_KGDB +.global evt_emulation +evt_emulation: + SAVE_CONTEXT + r0 = IRQ_EMU; + r1 = seqstat; + sp += -12; + call blackfin_irq_panic; + sp += 12; + rte; +#endif + +.global evt_nmi +evt_nmi: + SAVE_CONTEXT + r0 = IRQ_NMI; + r1 = RETN; + sp += -12; + call blackfin_irq_panic; + sp += 12; + +_evt_nmi_exit: + rtn; + +.global trap +trap: + [--sp] = r0; + [--sp] = r1; + [--sp] = p0; + [--sp] = p1; + [--sp] = astat; + r0 = seqstat; + R0 <<= 26; + R0 >>= 26; + p0 = r0; + p1.l = EVTABLE; + p1.h = EVTABLE; + p0 = p1 + (p0 << 1); + r1 = W[p0] (Z); + p1 = r1; + jump (pc + p1); + +.global _EVENT1 +_EVENT1: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT2 +_EVENT2: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT3 +_EVENT3: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT4 +_EVENT4: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT5 +_EVENT5: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT6 +_EVENT6: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT7 +_EVENT7: + RAISE 15; + JUMP.S _EXIT; + +.global _EVENT8 +_EVENT8: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT9 +_EVENT9: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT10 +_EVENT10: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT11 +_EVENT11: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT12 +_EVENT12: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT13 +_EVENT13: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT14 +_EVENT14: +/* RAISE 14; */ + CALL _cplb_hdr; + JUMP.S _EXIT; + +.global _EVENT19 +_EVENT19: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT20 +_EVENT20: + RAISE 14; + JUMP.S _EXIT; + +.global _EVENT21 +_EVENT21: + RAISE 14; + JUMP.S _EXIT; + +.global _EXIT +_EXIT: + ASTAT = [sp++]; + p1 = [sp++]; + p0 = [sp++]; + r1 = [sp++]; + r0 = [sp++]; + RTX; + +EVTABLE: + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x0000; + .byte2 0x003E; + .byte2 0x0042; + .byte4 0x0000; + .byte4 0x0000; + .byte4 0x0000; + .byte4 0x0000; + .byte4 0x0000; + .byte4 0x0000; + .byte4 0x0000; + .byte2 0x0000; + .byte2 0x001E; + .byte2 0x0022; + .byte2 0x0032; + .byte2 0x002e; + .byte2 0x0002; + .byte2 0x0036; + .byte2 0x002A; + .byte2 0x001A; + .byte2 0x0016; + .byte2 0x000A; + .byte2 0x000E; + .byte2 0x0012; + .byte2 0x0006; + .byte2 0x0026; + +.global evt_rst +evt_rst: + SAVE_CONTEXT + r0 = IRQ_RST; + r1 = RETN; + sp += -12; + call do_reset; + sp += 12; + +_evt_rst_exit: + rtn; + +irq_panic: + r0 = IRQ_EVX; + r1 = sp; + sp += -12; + call blackfin_irq_panic; + sp += 12; + +.global evt_ivhw +evt_ivhw: + SAVE_CONTEXT + RAISE 14; + +_evt_ivhw_exit: + rti; + +.global evt_timer +evt_timer: + SAVE_CONTEXT + r0 = IRQ_CORETMR; + sp += -12; + /* Polling method used now. */ + /* call timer_int; */ + sp += 12; + RESTORE_CONTEXT + rti; + nop; + +.global evt_evt7 +evt_evt7: + SAVE_CONTEXT + r0 = 7; + sp += -12; + call process_int; + sp += 12; + +evt_evt7_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt8 +evt_evt8: + SAVE_CONTEXT + r0 = 8; + sp += -12; + call process_int; + sp += 12; + +evt_evt8_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt9 +evt_evt9: + SAVE_CONTEXT + r0 = 9; + sp += -12; + call process_int; + sp += 12; + +evt_evt9_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt10 +evt_evt10: + SAVE_CONTEXT + r0 = 10; + sp += -12; + call process_int; + sp += 12; + +evt_evt10_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt11 +evt_evt11: + SAVE_CONTEXT + r0 = 11; + sp += -12; + call process_int; + sp += 12; + +evt_evt11_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt12 +evt_evt12: + SAVE_CONTEXT + r0 = 12; + sp += -12; + call process_int; + sp += 12; +evt_evt12_exit: + RESTORE_CONTEXT + rti; + +.global evt_evt13 +evt_evt13: + SAVE_CONTEXT + r0 = 13; + sp += -12; + call process_int; + sp += 12; + +evt_evt13_exit: + RESTORE_CONTEXT + rti; + +.global evt_system_call +evt_system_call: + [--sp] = r0; + [--SP] = RETI; + r0 = [sp++]; + r0 += 2; + [--sp] = r0; + RETI = [SP++]; + r0 = [SP++]; + SAVE_CONTEXT + sp += -12; + call display_excp; + sp += 12; + RESTORE_CONTEXT + RTI; + +evt_system_call_exit: + rti; + +.global evt_soft_int1 +evt_soft_int1: + [--sp] = r0; + [--SP] = RETI; + r0 = [sp++]; + r0 += 2; + [--sp] = r0; + RETI = [SP++]; + r0 = [SP++]; + SAVE_CONTEXT + sp += -12; + call display_excp; + sp += 12; + RESTORE_CONTEXT + RTI; + +evt_soft_int1_exit: + rti; diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c new file mode 100644 index 000000000..df1a25ec7 --- /dev/null +++ b/cpu/bf533/interrupts.c @@ -0,0 +1,165 @@ +/* + * U-boot - interrupts.c Interrupt related routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on interrupts.c + * Copyright 1996 Roman Zippel + * Copyright 1999 D. Jeff Dionne + * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne + * Copyright 2002 Arcturus Networks Inc. MaTed + * Copyright 2003 Metrowerks/Motorola + * Copyright 2003 Bas Vermeulen , + * BuyWays B.V. (www.buyways.nl) + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "cpu.h" + +static ulong timestamp; +static ulong last_time; +static int int_flag; + +int irq_flags; /* needed by asm-blackfin/system.h */ + +/* Functions just to satisfy the linker */ + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On BF533 it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On BF533 it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CFG_HZ; + return tbclk; +} + +void enable_interrupts(void) +{ + restore_flags(int_flag); +} + +int disable_interrupts(void) +{ + save_and_cli(int_flag); + return 1; +} + +int interrupt_init(void) +{ + return (0); +} + +void udelay(unsigned long usec) +{ + unsigned long delay, start, stop; + unsigned long cclk; + cclk = (CONFIG_CCLK_HZ); + + while ( usec > 1 ) { + /* + * how many clock ticks to delay? + * - request(in useconds) * clock_ticks(Hz) / useconds/second + */ + if (usec < 1000) { + delay = (usec * (cclk/244)) >> 12 ; + usec = 0; + } else { + delay = (1000 * (cclk/244)) >> 12 ; + usec -= 1000; + } + + asm volatile (" %0 = CYCLES;": "=g"(start)); + do { + asm volatile (" %0 = CYCLES; ": "=g"(stop)); + } while (stop - start < delay); + } + + return; +} + +void timer_init(void) +{ + *pTCNTL = 0x1; + *pTSCALE = 0x0; + *pTCOUNT = MAX_TIM_LOAD; + *pTPERIOD = MAX_TIM_LOAD; + *pTCNTL = 0x7; + asm("CSYNC;"); + + timestamp = 0; + last_time = 0; +} + +/* Any network command or flash + * command is started get_timer shall + * be called before TCOUNT gets reset, + * to implement the accurate timeouts. + * + * How ever milliconds doesn't return + * the number that has been elapsed from + * the last reset. + * + * As get_timer is used in the u-boot + * only for timeouts this should be + * sufficient + */ +ulong get_timer(ulong base) +{ + ulong milisec; + + /* Number of clocks elapsed */ + ulong clocks = (MAX_TIM_LOAD - (*pTCOUNT)); + + /* Find if the TCOUNT is reset + timestamp gives the number of times + TCOUNT got reset */ + if(clocks < last_time) + timestamp++; + last_time = clocks; + + /* Get the number of milliseconds */ + milisec = clocks/(CONFIG_CCLK_HZ / 1000); + + /* Find the number of millisonds + that got elapsed before this TCOUNT + cycle */ + milisec += timestamp * (MAX_TIM_LOAD/(CONFIG_CCLK_HZ / 1000)); + + return (milisec - base); +} diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c new file mode 100644 index 000000000..859f4b2f0 --- /dev/null +++ b/cpu/bf533/ints.c @@ -0,0 +1,107 @@ +/* + * U-boot - ints.c Interrupt related routines + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on ints.c + * + * Apr18 2003, Changed by HuTao to support interrupt cascading for Blackfin + * drivers + * + * Copyright 1996 Roman Zippel + * Copyright 1999 D. Jeff Dionne + * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne + * Copyright 2002 Arcturus Networks Inc. MaTed + * Copyright 2003 Metrowerks/Motorola + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpu.h" + +void blackfin_irq_panic(int reason, struct pt_regs *regs) +{ + printf("\n\nException: IRQ 0x%x entered\n", reason); + printf("code=[0x%x], ", (unsigned int) (regs->seqstat & 0x3f)); + printf("stack frame=0x%x, ", (unsigned int) regs); + printf("bad PC=0x%04x\n", (unsigned int) regs->pc); + dump(regs); + printf("Unhandled IRQ or exceptions!\n"); + printf("Please reset the board \n"); +} + +void blackfin_init_IRQ(void) +{ + *(unsigned volatile long *) (SIC_IMASK) = SIC_UNMASK_ALL; + cli(); +#ifndef CONFIG_KGDB + *(unsigned volatile long *) (EVT_EMULATION_ADDR) = 0x0; +#endif + *(unsigned volatile long *) (EVT_NMI_ADDR) = + (unsigned volatile long) evt_nmi; + *(unsigned volatile long *) (EVT_EXCEPTION_ADDR) = + (unsigned volatile long) trap; + *(unsigned volatile long *) (EVT_HARDWARE_ERROR_ADDR) = + (unsigned volatile long) evt_ivhw; + *(unsigned volatile long *) (EVT_RESET_ADDR) = + (unsigned volatile long) evt_rst; + *(unsigned volatile long *) (EVT_TIMER_ADDR) = + (unsigned volatile long) evt_timer; + *(unsigned volatile long *) (EVT_IVG7_ADDR) = + (unsigned volatile long) evt_evt7; + *(unsigned volatile long *) (EVT_IVG8_ADDR) = + (unsigned volatile long) evt_evt8; + *(unsigned volatile long *) (EVT_IVG9_ADDR) = + (unsigned volatile long) evt_evt9; + *(unsigned volatile long *) (EVT_IVG10_ADDR) = + (unsigned volatile long) evt_evt10; + *(unsigned volatile long *) (EVT_IVG11_ADDR) = + (unsigned volatile long) evt_evt11; + *(unsigned volatile long *) (EVT_IVG12_ADDR) = + (unsigned volatile long) evt_evt12; + *(unsigned volatile long *) (EVT_IVG13_ADDR) = + (unsigned volatile long) evt_evt13; + *(unsigned volatile long *) (EVT_IVG14_ADDR) = + (unsigned volatile long) evt_system_call; + *(unsigned volatile long *) (EVT_IVG15_ADDR) = + (unsigned volatile long) evt_soft_int1; + *(volatile unsigned long *) ILAT = 0; + asm("csync;"); + sti(); + *(volatile unsigned long *) IMASK = 0xffbf; + asm("csync;"); +} + +void display_excp(void) +{ + printf("Exception!\n"); +} diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c new file mode 100644 index 000000000..7b43ffd18 --- /dev/null +++ b/cpu/bf533/serial.c @@ -0,0 +1,195 @@ +/* + * U-boot - serial.c Serial driver for BF533 + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART. + * Copyright (c) 2003 Bas Vermeulen , + * BuyWays B.V. (www.buyways.nl) + * + * Based heavily on blkfinserial.c + * blkfinserial.c: Serial driver for BlackFin DSP internal USRTs. + * Copyright(c) 2003 Metrowerks + * Copyright(c) 2001 Tony Z. Kou + * Copyright(c) 2001-2002 Arcturus Networks Inc. + * + * Based on code from 68328 version serial driver imlpementation which was: + * Copyright (C) 1995 David S. Miller + * Copyright (C) 1998 Kenneth Albanowski + * Copyright (C) 1998, 1999 D. Jeff Dionne + * Copyright (C) 1999 Vladimir Gurevich + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "bf533_serial.h" + +DECLARE_GLOBAL_DATA_PTR; + +unsigned long pll_div_fact; + +void calc_baud(void) +{ + unsigned char i; + int temp; + + for(i = 0; i < sizeof(baud_table)/sizeof(int); i++) { + temp = CONFIG_SCLK_HZ/(baud_table[i]*8); + if ( temp && 0x1 == 1 ) { + temp++; + } + temp = temp/2; + hw_baud_table[i].dl_high = (temp >> 8)& 0xFF; + hw_baud_table[i].dl_low = (temp) & 0xFF; + } +} + +void serial_setbrg(void) +{ + int i; + + calc_baud(); + + for (i = 0; i < sizeof(baud_table) / sizeof(int); i++) { + if (gd->baudrate == baud_table[i]) + break; + } + + /* Enable UART */ + *pUART_GCTL |= UART_GCTL_UCEN; + asm("ssync;"); + + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH; + asm("ssync;"); + + *pUART_DLL = hw_baud_table[i].dl_low; + asm("ssync;"); + *pUART_DLH = hw_baud_table[i].dl_high; + asm("ssync;"); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER; + asm("ssync;"); + + /* Enable ERBFI and ELSI interrupts + * to poll SIC_ISR register*/ + *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; + asm("ssync;"); + + /* Set LCR to Word Lengh 8-bit word select */ + *pUART_LCR = UART_LCR_WLS8; + asm("ssync;"); + + return; +} + +int serial_init(void) +{ + serial_setbrg(); + return (0); +} + +void serial_putc(const char c) +{ + if ((*pUART_LSR) & UART_LSR_TEMT) + { + if (c == '\n') + serial_putc('\r'); + + local_put_char(c); + } + + while (!((*pUART_LSR) & UART_LSR_TEMT)) + SYNC_ALL; + + return; +} + +int serial_tstc(void) +{ + if (*pUART_LSR & UART_LSR_DR) + return 1; + else + return 0; +} + +int serial_getc(void) +{ + unsigned short uart_lsr_val, uart_rbr_val; + unsigned long isr_val; + int ret; + + /* Poll for RX Interrupt */ + while (!((isr_val = *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)); + asm("csync;"); + + uart_lsr_val = *pUART_LSR; /* Clear status bit */ + uart_rbr_val = *pUART_RBR; /* getc() */ + + if (isr_val & IRQ_UART_ERROR_BIT) { + ret = -1; + } + else + { + ret = uart_rbr_val & 0xff; + } + + return ret; +} + +void serial_puts(const char *s) +{ + while (*s) { + serial_putc(*s++); + } +} + +static void local_put_char(char ch) +{ + int flags = 0; + unsigned long isr_val; + + save_and_cli(flags); + + /* Poll for TX Interruput */ + while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)); + asm("csync;"); + + *pUART_THR = ch; /* putc() */ + + if (isr_val & IRQ_UART_ERROR_BIT) { + printf("?"); + } + + restore_flags(flags); + + return ; +} diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S new file mode 100644 index 000000000..6d585751a --- /dev/null +++ b/cpu/bf533/start.S @@ -0,0 +1,435 @@ +/* + * U-boot - start.S Startup file of u-boot for BF533 + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on head.S + * Copyright (c) 2003 Metrowerks/Motorola + * Copyright (C) 1998 D. Jeff Dionne , + * Kenneth Albanowski , + * The Silver Hammer Group, Ltd. + * (c) 1995, Dionne & Associates + * (c) 1995, DKG Display Tech. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Note: A change in this file subsequently requires a change in + * board/$(board_name)/config.mk for a valid u-boot.bin + */ + +#define ASSEMBLY + +#include +#include +#include +#include + +#if (CONFIG_CCLK_DIV == 1) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 +#endif +#if (CONFIG_CCLK_DIV == 2) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 +#endif +#if (CONFIG_CCLK_DIV == 4) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 +#endif +#if (CONFIG_CCLK_DIV == 8) +#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 +#endif +#ifndef CONFIG_CCLK_ACT_DIV +#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly +#endif + +.global _stext; +.global __bss_start; +.global start; +.global _start; +.global _rambase; +.global _ramstart; +.global _ramend; +.global _bf533_data_dest; +.global _bf533_data_size; +.global edata; +.global _initialize; +.global _exit; +.global flashdataend; + +.text +_start: +start: +_stext: + + R0 = 0x30; + SYSCFG = R0; + SSYNC; + + /* As per HW reference manual DAG registers, + * DATA and Address resgister shall be zero'd + * in initialization, after a reset state + */ + r1 = 0; /* Data registers zero'd */ + r2 = 0; + r3 = 0; + r4 = 0; + r5 = 0; + r6 = 0; + r7 = 0; + + p0 = 0; /* Address registers zero'd */ + p1 = 0; + p2 = 0; + p3 = 0; + p4 = 0; + p5 = 0; + + i0 = 0; /* DAG Registers zero'd */ + i1 = 0; + i2 = 0; + i3 = 0; + m0 = 0; + m1 = 0; + m3 = 0; + m3 = 0; + l0 = 0; + l1 = 0; + l2 = 0; + l3 = 0; + b0 = 0; + b1 = 0; + b2 = 0; + b3 = 0; + + /* Set loop counters to zero, to make sure that + * hw loops are disabled. + */ + lc0 = 0; + lc1 = 0; + + SSYNC; + + /* Check soft reset status */ + p0.h = SWRST >> 16; + p0.l = SWRST & 0xFFFF; + r0.l = w[p0]; + + cc = bittst(r0, 15); + if !cc jump no_soft_reset; + + /* Clear Soft reset */ + r0 = 0x0000; + w[p0] = r0; + ssync; + +no_soft_reset: + nop; + + /* Clear EVT registers */ + p0.h = (EVT_EMULATION_ADDR >> 16); + p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0 += 8; + p1 = 14; + r1 = 0; + LSETUP(4,4) lc0 = p1; + [ p0 ++ ] = r1; + + /* + * Set PLL_CTL + * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors + * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK + * - [7] = output delay (add 200ps of delay to mem signals) + * - [6] = input delay (add 200ps of input delay to mem signals) + * - [5] = PDWN : 1=All Clocks off + * - [3] = STOPCK : 1=Core Clock off + * - [1] = PLL_OFF : 1=Disable Power to PLL + * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL + * all other bits set to zero + */ + + r0 = CONFIG_VCO_MULT; /* Load the VCO multiplier */ + r0 = r0 << 9; /* Shift it over */ + r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */ + r0 = r1 | r0; + r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */ + r1 = r1 << 8; /* Shift it over */ + r0 = r1 | r0; /* add them all together */ + + p0.h = (PLL_CTL >> 16); + p0.l = (PLL_CTL & 0xFFFF); /* Load the address */ + cli r2; /* Disable interrupts */ + w[p0] = r0; /* Set the value */ + idle; /* Wait for the PLL to stablize */ + sti r2; /* Enable interrupts */ + ssync; + + /* + * Turn on the CYCLES COUNTER + */ + r2 = SYSCFG; + BITSET (r2,1); + SYSCFG = r2; + + /* Configure SCLK & CCLK Dividers */ + r0 = CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV; + p0.h = (PLL_DIV >> 16); + p0.l = (PLL_DIV & 0xFFFF); + w[p0] = r0; + ssync; + +wait_for_pll_stab: + p0.h = (PLL_STAT >> 16); + p0.l = (PLL_STAT & 0xFFFF); + r0.l = w[p0]; + cc = bittst(r0,5); + if !cc jump wait_for_pll_stab; + + /* Configure SDRAM if SDRAM is already not enabled */ + p0.l = (EBIU_SDSTAT & 0xFFFF); + p0.h = (EBIU_SDSTAT >> 16); + r0.l = w[p0]; + cc = bittst(r0, 3); + if !cc jump skip_sdram_enable; + + /* SDRAM initialization */ + p0.l = (EBIU_SDGCTL & 0xFFFF); + p0.h = (EBIU_SDGCTL >> 16); /* SDRAM Memory Global Control Register */ + r0.h = (mem_SDGCTL >> 16); + r0.l = (mem_SDGCTL & 0xFFFF); + [p0] = r0; + ssync; + + p0.l = (EBIU_SDBCTL & 0xFFFF); + p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ + r0 = mem_SDBCTL; + w[p0] = r0.l; + ssync; + + p0.l = (EBIU_SDRRC & 0xFFFF); + p0.h = (EBIU_SDRRC >> 16); /* SDRAM Refresh Rate Control Register */ + r0 = mem_SDRRC; + w[p0] = r0.l; + ssync; + +skip_sdram_enable: + nop; + +#ifndef CFG_NO_FLASH + /* relocate into to RAM */ + p1.l = (CFG_FLASH_BASE & 0xffff); + p1.h = (CFG_FLASH_BASE >> 16); + p2.l = (CFG_MONITOR_BASE & 0xffff); + p2.h = (CFG_MONITOR_BASE >> 16); + r0.l = (CFG_MONITOR_LEN & 0xffff); + r0.h = (CFG_MONITOR_LEN >> 16); +loop1: + r1 = [p1]; + [p2] = r1; + p3=0x4; + p1=p1+p3; + p2=p2+p3; + r2=0x4; + r0=r0-r2; + cc=r0==0x0; + if !cc jump loop1; +#endif + /* + * configure STACK + */ + r0.h = (CONFIG_STACKBASE >> 16); + r0.l = (CONFIG_STACKBASE & 0xFFFF); + sp = r0; + fp = sp; + + /* + * This next section keeps the processor in supervisor mode + * during kernel boot. Switches to user mode at end of boot. + * See page 3-9 of Hardware Reference manual for documentation. + */ + + /* To keep ourselves in the supervisor mode */ + p0.l = (EVT_IVG15_ADDR & 0xFFFF); + p0.h = (EVT_IVG15_ADDR >> 16); + + p1.l = _real_start; + p1.h = _real_start; + [p0] = p1; + + p0.l = (IMASK & 0xFFFF); + p0.h = (IMASK >> 16); + r0 = IVG15_POS; + [p0] = r0; + raise 15; + p0.l = WAIT_HERE; + p0.h = WAIT_HERE; + reti = p0; + rti; + +WAIT_HERE: + jump WAIT_HERE; + +.global _real_start; +_real_start: + [ -- sp ] = reti; + +#ifdef CONFIG_EZKIT533 + p0.l = (WDOG_CTL & 0xFFFF); + p0.h = (WDOG_CTL >> 16); + r0 = WATCHDOG_DISABLE(z); + w[p0] = r0; +#endif + + /* Code for initializing Async mem banks */ + p2.h = (EBIU_AMBCTL1 >> 16); + p2.l = (EBIU_AMBCTL1 & 0xFFFF); + r0.h = (AMBCTL1VAL >> 16); + r0.l = (AMBCTL1VAL & 0xFFFF); + [p2] = r0; + ssync; + + p2.h = (EBIU_AMBCTL0 >> 16); + p2.l = (EBIU_AMBCTL0 & 0xFFFF); + r0.h = (AMBCTL0VAL >> 16); + r0.l = (AMBCTL0VAL & 0xFFFF); + [p2] = r0; + ssync; + + p2.h = (EBIU_AMGCTL >> 16); + p2.l = (EBIU_AMGCTL & 0xffff); + r0 = AMGCTLVAL; + w[p2] = r0; + ssync; + + /* DMA reset code to Hi of L1 SRAM */ +copy: + P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */ + P1.L = lo(SYSMMR_BASE); + + R0.H = reset_start; /* Source Address (high) */ + R0.L = reset_start; /* Source Address (low) */ + R1.H = reset_end; + R1.L = reset_end; + R2 = R1 - R0; /* Count */ + R1.H = hi(L1_ISRAM); /* Destination Address (high) */ + R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ + R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ + +DMA: + R6 = 0x1 (Z); + W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ + W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ + + [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ + W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ + /* Set Source DMAConfig = DMA Enable, + Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ + W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; + + [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ + W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ + /* Set Destination DMAConfig = DMA Enable, + Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ + W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; + + IDLE; /* Wait for DMA to Complete */ + + R0 = 0x1; + W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ + + /* DMA reset code to DATA BANK A which uses this port + * to avoid following problem + * " Data from a Data Cache fill can be corrupoted after or during + * instruction DMA if certain core stalls exist" + */ + +copy_as_data: + R0.H = reset_start; /* Source Address (high) */ + R0.L = reset_start; /* Source Address (low) */ + R1.H = reset_end; + R1.L = reset_end; + R2 = R1 - R0; /* Count */ + R1.H = hi(DATA_BANKA_SRAM); /* Destination Address (high) */ + R1.L = lo(DATA_BANKA_SRAM); /* Destination Address (low) */ + R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ + R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ + +DMA_DATA: + R6 = 0x1 (Z); + W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ + W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ + + [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ + W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ + /* Set Source DMAConfig = DMA Enable, + Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ + W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; + + [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ + W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ + /* Set Destination DMAConfig = DMA Enable, + Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ + W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; + + IDLE; /* Wait for DMA to Complete */ + + R0 = 0x1; + W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ + +copy_end: nop; + + /* Initialize BSS Section with 0 s */ + p1.l = __bss_start; + p1.h = __bss_start; + p2.l = _end; + p2.h = _end; + r1 = p1; + r2 = p2; + r3 = r2 - r1; + r3 = r3 >> 2; + p3 = r3; + lsetup (_clear_bss, _clear_bss_end ) lc1 = p3; + CC = p2<=p1; + if CC jump _clear_bss_skip; + r0 = 0; +_clear_bss: +_clear_bss_end: + [p1++] = r0; +_clear_bss_skip: + + p0.l = _start1; + p0.h = _start1; + jump (p0); + +reset_start: + p0.h = WDOG_CNT >> 16; + p0.l = WDOG_CNT & 0xffff; + r0 = 0x0010; + w[p0] = r0; + p0.h = WDOG_CTL >> 16; + p0.l = WDOG_CTL & 0xffff; + r0 = 0x0000; + w[p0] = r0; +reset_wait: + jump reset_wait; + +reset_end: nop; + +_exit: + jump.s _exit; diff --git a/cpu/bf533/start1.S b/cpu/bf533/start1.S new file mode 100644 index 000000000..6f4812405 --- /dev/null +++ b/cpu/bf533/start1.S @@ -0,0 +1,38 @@ +/* + * U-boot - start1.S Code running out of RAM after relocation + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define ASSEMBLY +#include +#include +#include + +.global start1; +.global _start1; + +.text +_start1: +start1: + sp += -12; + call board_init_f; + sp += 12; diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c new file mode 100644 index 000000000..37470d583 --- /dev/null +++ b/cpu/bf533/traps.c @@ -0,0 +1,73 @@ +/* + * U-boot - traps.c Routines related to interrupts and exceptions + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * No original Copyright holder listed, + * Probabily original (C) Roman Zippel (assigned DJD, 1999) + * + * Copyright 2003 Metrowerks - for Blackfin + * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne + * Copyright 1999-2000 D. Jeff Dionne, + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpu.h" + +void init_IRQ(void) +{ + blackfin_init_IRQ(); + return; +} + +void process_int(unsigned long vec, struct pt_regs *fp) +{ + return; +} + +void dump(struct pt_regs *fp) +{ + printf("PC: %08lx\n", fp->pc); + printf("SEQSTAT: %08lx SP: %08lx\n", (long) fp->seqstat, + (long) fp); + printf("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n", + fp->r0, fp->r1, fp->r2, fp->r3); + printf("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", + fp->r4, fp->r5, fp->r6, fp->r7); + printf("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n", + fp->p0, fp->p1, fp->p2, fp->p3); + printf("P4: %08lx P5: %08lx FP: %08lx\n", fp->p4, fp->p5, + fp->fp); + printf("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n", + fp->a0w, fp->a0x, fp->a1w, fp->a1x); + printf("\n"); +} diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile index 50534b615..c44412a02 100644 --- a/cpu/i386/Makefile +++ b/cpu/i386/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2002 # Daniel Engström, Omicron Ceti AB, daniel@omicron.se. # @@ -26,26 +23,22 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o start16.o reset.o COBJS = serial.o interrupts.o cpu.o timer.o sc520.o -SOBJS = sc520_asm.o +AOBJS = sc520_asm.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) +all: .depend $(START) $(LIB) -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(COBJS) $(AOBJS) + $(AR) crv $@ $(COBJS) $(AOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(COBJS:.o=.c) $(AOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) $(AOBJS:.o=.S) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index 640b25584..c83f0bb6c 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -31,9 +31,7 @@ #include #include #include -#ifdef CONFIG_SC520_SSI #include -#endif #include #include #include @@ -145,15 +143,7 @@ unsigned long init_sc520_dram(void) u32 dram_present=0; u32 dram_ctrl; -#ifdef CFG_SDRAM_DRCTMCTL - /* these memory control registers are set up in the assember part, - * in sc520_asm.S, during 'mem_init'. If we muck with them here, - * after we are running a stack in RAM, we have troubles. Besides, - * these refresh and delay values are better ? simply specified - * outright in the include/configs/{cfg} file since the HW designer - * simply dictates it. - */ -#else + int val; int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY; @@ -172,7 +162,6 @@ unsigned long init_sc520_dram(void) } else { val = 3; /* 62.4us */ } - write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4)); val = read_mmcr_byte(SC520_DRCTMCTL); @@ -192,12 +181,13 @@ unsigned long init_sc520_dram(void) val |= 1; } write_mmcr_byte(SC520_DRCTMCTL, val); -#endif + /* We read-back the configuration of the dram * controller that the assembly code wrote */ dram_ctrl = read_mmcr_long(SC520_DRCBENDADR); + bd->bi_dram[0].start = 0; if (dram_ctrl & 0x80) { /* bank 0 enabled */ @@ -284,7 +274,7 @@ int pci_sc520_set_irq(int pci_pin, int irq) { int i; -# if 1 +# if 0 printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq); #endif if (irq < 0 || irq > 15) { @@ -406,7 +396,7 @@ void reset_timer(void) ulong get_timer(ulong base) { /* fixme: 30 or 33 */ - return read_mmcr_word(SC520_GPTMR0CNT) / 33; + return read_mmcr_word(SC520_GPTMR0CNT) / 33; } void set_timer(ulong t) diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S index 34322ea25..80464fa78 100644 --- a/cpu/i386/sc520_asm.S +++ b/cpu/i386/sc520_asm.S @@ -113,7 +113,6 @@ .equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */ .equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */ .equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */ -.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */ .equ DBCTL, 0x0fffef040 /* DRAM buffer control register */ .equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */ @@ -460,12 +459,6 @@ emptybank: incl %edi loop cleanuplp -#if defined CFG_SDRAM_DRCTMCTL - /* just have your hardware desinger _GIVE_ you what you need here! */ - movl $DRCTMCTL, %edi - movb $CFG_SDRAM_DRCTMCTL,%al - movb (%edi), %al -#else #if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T) /* set the CAS latency now since it is hard to do * when we run from the RAM */ @@ -478,7 +471,6 @@ emptybank: orb $0x10, %al #endif movb %al, (%edi) -#endif #endif movl $DRCCTL, %edi /* DRAM Control register */ movb $0x3,%al /* Load mode register cmd */ @@ -512,7 +504,7 @@ dram_done: shrl $2, %eax movl %eax, %ebx -bank2: movl (%edi), %eax +bank2: movl (%edi), %eax movl %eax, %ecx andl $0x00800000, %ecx jz bank1 @@ -520,7 +512,7 @@ bank2: movl (%edi), %eax shll $6, %eax movl %eax, %ebx -bank1: movl (%edi), %eax +bank1: movl (%edi), %eax movl %eax, %ecx andl $0x00008000, %ecx jz bank0 @@ -528,7 +520,7 @@ bank1: movl (%edi), %eax shll $14, %eax movl %eax, %ebx -bank0: movl (%edi), %eax +bank0: movl (%edi), %eax movl %eax, %ecx andl $0x00000080, %ecx jz done @@ -536,49 +528,9 @@ bank0: movl (%edi), %eax shll $22, %eax movl %eax, %ebx +done: movl %ebx, %eax -done: - movl %ebx, %eax - -#if CFG_SDRAM_ECC_ENABLE - /* A nominal memory test: just a byte at each address line */ - movl %eax, %ecx - shrl $0x1, %ecx - movl $0x1, %edi -memtest0: - movb $0xa5, (%edi) - cmpb $0xa5, (%edi) - jne out - shrl $1, %ecx - andl %ecx,%ecx - jz set_ecc - shll $1, %edi - jmp memtest0 - -set_ecc: - /* clear all ram with a memset */ - movl %eax, %ecx - xorl %esi, %esi - xorl %edi, %edi - xorl %eax, %eax - shrl $2, %ecx - cld - rep stosl - /* enable read, write buffers */ - movb $0x11, %al - movl $DBCTL, %edi - movb %al, (%edi) - /* enable NMI mapping for ECC */ - movl $ECCINT, %edi - mov $0x10, %al - movb %al, (%edi) - /* Turn on ECC */ - movl $ECCCTL, %edi - mov $0x05, %al - movb %al, (%edi) -#endif -out: - movl %ebx, %eax jmp *%ebp + #endif /* CONFIG_SC520 */ diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c index 8b5f8fa11..e7299a7eb 100644 --- a/cpu/i386/serial.c +++ b/cpu/i386/serial.c @@ -394,7 +394,7 @@ int serial_buffered_tstc(void) #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) /* AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port number 0 or number 1 @@ -413,8 +413,8 @@ void kgdb_serial_init(void) * Init onboard 16550 UART */ outb(0x80, UART1_BASE + UART_LCR); /* set DLAB bit */ - outb((bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */ - outb((bdiv >> 8 ), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */ + outb(bdiv & 0xff), UART1_BASE + UART_DLL); /* set divisor for 9600 baud */ + outb(bdiv >> 8), UART1_BASE + UART_DLM); /* set divisor for 9600 baud */ outb(0x03, UART1_BASE + UART_LCR); /* line control 8 bits no parity */ outb(0x00, UART1_BASE + UART_FCR); /* disable FIFO */ outb(0x00, UART1_BASE + UART_MCR); /* no modem control DTR RTS */ @@ -500,4 +500,4 @@ void kgdb_interruptible(int yes) return; } #endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/cpu/i386/start.S b/cpu/i386/start.S index 264ac0940..afcbb2452 100644 --- a/cpu/i386/start.S +++ b/cpu/i386/start.S @@ -34,8 +34,8 @@ .globl _i386boot_start _i386boot_start: _start: - movl $0x18,%eax /* Load our segement registes, the - * gdt have already been loaded by start16.S */ + movl $0x18,%eax /* Load our segement registes, the + * gdt have already been loaded by start16.S */ movw %ax,%fs movw %ax,%ds movw %ax,%gs @@ -55,7 +55,7 @@ early_board_init_ret: /* so we try to indicate progress */ movw $0x01, %ax movl $.progress0, %ebp - jmp show_boot_progress + jmp __show_boot_progress .progress0: /* size memory */ @@ -74,15 +74,15 @@ mem_init_ret: /* indicate (lack of) progress */ movw $0x81, %ax movl $.progress0a, %ebp - jmp show_boot_progress + jmp __show_boot_progress .progress0a: - jmp die + jmp die mem_ok: /* indicate progress */ movw $0x02, %ax movl $.progress1, %ebp - jmp show_boot_progress + jmp __show_boot_progress .progress1: /* create a stack after the bss */ @@ -104,7 +104,7 @@ no_stack: /* indicate (lack of) progress */ movw $0x82, %ax movl $.progress1a, %ebp - jmp show_boot_progress + jmp __show_boot_progress .progress1a: jmp die @@ -113,7 +113,7 @@ stack_ok: /* indicate progress */ movw $0x03, %ax movl $.progress2, %ebp - jmp show_boot_progress + jmp __show_boot_progress .progress2: /* copy data section to ram, size must be 4-byte aligned */ @@ -136,20 +136,20 @@ data_fail: /* indicate (lack of) progress */ movw $0x83, %ax movl $.progress2a, %ebp - jmp show_boot_progress + jmp __show_boot_progress .progress2a: - jmp die + jmp die data_ok: /* indicate progress */ movw $0x04, %ax movl $.progress3, %ebp - jmp show_boot_progress + jmp __show_boot_progress .progress3: /* clear bss section in ram, size must be 4-byte aligned */ - movl $_i386boot_bss_start, %edi /* MK_CHG BSS start */ + movl $_i386boot_bss_start, %eax /* BSS start */ movl $_i386boot_bss_size, %ecx /* BSS size */ movl %ecx, %eax andl $3, %eax @@ -162,15 +162,15 @@ bss: movl $0, (%edi) add $4, %edi loop bss - jmp bss_ok + jmp bss_ok bss_fail: /* indicate (lack of) progress */ movw $0x84, %ax movl $.progress3a, %ebp - jmp show_boot_progress + jmp __show_boot_progress .progress3a: - jmp die + jmp die bss_ok: @@ -180,7 +180,7 @@ bss_ok: /* indicate progress */ movw $0x05, %ax movl $.progress4, %ebp - jmp show_boot_progress + jmp __show_boot_progress .progress4: call start_i386boot /* Enter, U-boot! */ @@ -188,7 +188,7 @@ bss_ok: /* indicate (lack of) progress */ movw $0x85, %ax movl $.progress4a, %ebp - jmp show_boot_progress + jmp __show_boot_progress .progress4a: die: hlt diff --git a/cpu/i386/start16.S b/cpu/i386/start16.S index 1ebb6bc8b..239f2ff39 100644 --- a/cpu/i386/start16.S +++ b/cpu/i386/start16.S @@ -39,74 +39,74 @@ start16: board_init16_ret: /* Turn of cache (this might require a 486-class CPU) */ - movl %cr0, %eax - orl $0x60000000,%eax - movl %eax, %cr0 + movl %cr0, %eax + orl $0x60000000,%eax + movl %eax, %cr0 wbinvd /* load the descriptor tables */ o32 cs lidt idt_ptr -o32 cs lgdt gdt_ptr +o32 cs lgdt gdt_ptr /* Now, we enter protected mode */ - movl %cr0, %eax - orl $1,%eax - movl %eax, %cr0 + movl %cr0, %eax + orl $1,%eax + movl %eax, %cr0 /* Flush the prefetch queue */ - jmp ff + jmp ff ff: /* Finally jump to the 32bit initialization code */ movw $code32start, %ax - movw %ax,%bp + movw %ax,%bp o32 cs ljmp *(%bp) /* 48-bit far pointer */ code32start: - .long _start /* offset */ - .word 0x10 /* segment */ + .long _start /* offset */ + .word 0x10 /* segment */ idt_ptr: - .word 0 /* limit */ - .long 0 /* base */ + .word 0 /* limit */ + .long 0 /* base */ gdt_ptr: - .word 0x30 /* limit (48 bytes = 6 GDT entries) */ - .long BOOT_SEG + gdt /* base */ + .word 0x30 /* limit (48 bytes = 6 GDT entries) */ + .long BOOT_SEG + gdt /* base */ /* The GDT table ... * - * Selector Type - * 0x00 NULL - * 0x08 Unused + * Selector Type + * 0x00 NULL + * 0x08 Unused * 0x10 32bit code * 0x18 32bit data/stack * 0x20 16bit code - * 0x28 16bit data/stack + * 0x28 16bit data/stack */ gdt: - .word 0, 0, 0, 0 /* NULL */ - .word 0, 0, 0, 0 /* unused */ + .word 0, 0, 0, 0 /* NULL */ + .word 0, 0, 0, 0 /* unused */ - .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ - .word 0 /* base address = 0 */ - .word 0x9B00 /* code read/exec */ - .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ + .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ + .word 0 /* base address = 0 */ + .word 0x9B00 /* code read/exec */ + .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ - .word 0x0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ + .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ + .word 0x0 /* base address = 0 */ + .word 0x9300 /* data read/write */ + .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9b00 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ + .word 0xFFFF /* 64kb */ + .word 0 /* base address = 0 */ + .word 0x9b00 /* data read/write */ + .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ + .word 0xFFFF /* 64kb */ + .word 0 /* base address = 0 */ + .word 0x9300 /* data read/write */ + .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ diff --git a/cpu/ixp/Makefile b/cpu/ixp/Makefile index e1fb327bb..ba2e58927 100644 --- a/cpu/ixp/Makefile +++ b/cpu/ixp/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o timer.o pci.o +OBJS = serial.o interrupts.o cpu.o timer.o pci.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c index 2c7d5a01b..7f9f3344b 100644 --- a/cpu/ixp/cpu.c +++ b/cpu/ixp/cpu.c @@ -85,7 +85,7 @@ int cpu_init (void) FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif -#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI) +#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined (CONFIG_PCI) pci_init(); #endif return 0; diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c index 84fe9378a..2dd9561e1 100644 --- a/cpu/ixp/interrupts.c +++ b/cpu/ixp/interrupts.c @@ -33,8 +33,6 @@ #include #ifdef CONFIG_USE_IRQ -#include - /* * When interrupts are enabled, use timer 2 for time/delay generation... */ @@ -52,6 +50,34 @@ static struct _irq_handler IRQ_HANDLER[N_IRQS]; static volatile ulong timestamp; +/* enable IRQ/FIQ interrupts */ +void enable_interrupts(void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts(void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0x80\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} + static void default_isr(void *data) { printf("default_isr(): called for IRQ %d, Interrupt Status=%x PR=%x\n", @@ -85,16 +111,114 @@ void reset_timer (void) timestamp = 0; } +#else /* #ifdef CONFIG_USE_IRQ */ +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} #endif /* #ifdef CONFIG_USE_IRQ */ -#ifdef CONFIG_USE_IRQ +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + printf("IRQ=%08lx FIQ=%08lx\n", *IXP425_ICIH, *IXP425_ICFH); +} + void do_irq (struct pt_regs *pt_regs) { +#ifdef CONFIG_USE_IRQ int irq = next_irq(); IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data); -} +#else + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); #endif +} int interrupt_init (void) { diff --git a/cpu/ixp/npe/IxEthAcc.c b/cpu/ixp/npe/IxEthAcc.c index 061b24bb5..d981649da 100644 --- a/cpu/ixp/npe/IxEthAcc.c +++ b/cpu/ixp/npe/IxEthAcc.c @@ -215,7 +215,7 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId) if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() ) { - return(IX_ETH_ACC_FAIL); + return(IX_ETH_ACC_FAIL); } /* @@ -235,8 +235,8 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId) if ( IX_ETH_IS_PORT_INITIALIZED(portId) ) { - /* Already initialized */ - return(IX_ETH_ACC_FAIL); + /* Already initialized */ + return(IX_ETH_ACC_FAIL); } if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS) diff --git a/cpu/ixp/npe/IxEthAccCommon.c b/cpu/ixp/npe/IxEthAccCommon.c index 211203dff..bda2c4479 100644 --- a/cpu/ixp/npe/IxEthAccCommon.c +++ b/cpu/ixp/npe/IxEthAccCommon.c @@ -96,7 +96,7 @@ extern IxEthAccInfo ixEthAccDataInfo; IX_ETH_ACC_PRIVATE IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = { - IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ + IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ "Eth Rx Q", ixEthRxFrameQMCallback, /**< Functional callback */ (IxQMgrCallbackId) 0, /**< Callback tag */ @@ -104,7 +104,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ TRUE, /**< Enable Q notification at startup */ IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ }; @@ -116,7 +116,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = IX_ETH_ACC_PRIVATE IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate = { - IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ + IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ "Eth Rx Q", ixEthRxFrameQMCallback, /**< Functional callback */ (IxQMgrCallbackId) 0, /**< Callback tag */ @@ -124,7 +124,7 @@ IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate = IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ TRUE, /**< Enable Q notification at startup */ IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ }; @@ -146,7 +146,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ FALSE, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ }, @@ -159,7 +159,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ FALSE, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ }, #ifdef __ixp46X @@ -172,7 +172,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ FALSE, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ }, #endif @@ -185,7 +185,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ FALSE, /**< Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ }, @@ -198,7 +198,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ FALSE, /**< Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ }, #ifdef __ixp46X @@ -211,7 +211,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */ FALSE, /** Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */ + IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */ IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */ }, #endif @@ -224,7 +224,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ TRUE, /**< Enable Q notification at startup */ IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ + IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */ }, diff --git a/cpu/ixp/npe/IxEthAccDataPlane.c b/cpu/ixp/npe/IxEthAccDataPlane.c index b62f0d016..e46fc9b25 100644 --- a/cpu/ixp/npe/IxEthAccDataPlane.c +++ b/cpu/ixp/npe/IxEthAccDataPlane.c @@ -544,7 +544,7 @@ ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf) IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET); /* get the next pointer */ - PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr); + PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr); if (nextPtr != NULL) { nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne)); diff --git a/cpu/ixp/npe/IxEthAccMac.c b/cpu/ixp/npe/IxEthAccMac.c index 369ee91d9..d57e71678 100644 --- a/cpu/ixp/npe/IxEthAccMac.c +++ b/cpu/ixp/npe/IxEthAccMac.c @@ -2423,14 +2423,14 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId) REG_READ(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_RX_CNTRL1, regval); - REG_WRITE(ixEthAccMacBase[portId], + REG_WRITE(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_RX_CNTRL1, regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN); REG_READ(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_TX_CNTRL1, regval); - REG_WRITE(ixEthAccMacBase[portId], + REG_WRITE(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_TX_CNTRL1, regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN); } @@ -2493,7 +2493,7 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId) REG_READ(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_TX_CNTRL1, regval); - REG_WRITE(ixEthAccMacBase[portId], + REG_WRITE(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_TX_CNTRL1, regval | IX_ETH_ACC_TX_CNTRL1_TX_EN); } diff --git a/cpu/ixp/npe/IxEthAccMii.c b/cpu/ixp/npe/IxEthAccMii.c index d282aa672..86368a473 100644 --- a/cpu/ixp/npe/IxEthAccMii.c +++ b/cpu/ixp/npe/IxEthAccMii.c @@ -324,7 +324,7 @@ ixEthAccMiiWriteRtn (UINT8 phyAddr, /*The "GO" bit is reset to 0 when the write completes*/ if((regval & IX_ETH_ACC_MII_GO) == 0x0) - { + { break; } /* Sleep for a while */ diff --git a/cpu/ixp/npe/IxNpeDl.c b/cpu/ixp/npe/IxNpeDl.c index 373833753..ffe355c51 100644 --- a/cpu/ixp/npe/IxNpeDl.c +++ b/cpu/ixp/npe/IxNpeDl.c @@ -108,6 +108,38 @@ static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={FALSE, FALSE, FALSE} ; PRIVATE IX_STATUS ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, UINT32 imageId); +/* + * Function definition: ixNpeDlMicrocodeImageLibraryOverride + */ +PUBLIC IX_STATUS +ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary) +{ + IX_STATUS status = IX_SUCCESS; + + IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, + "Entering ixNpeDlMicrocodeImageLibraryOverride\n"); + + if (clientImageLibrary == NULL) + { + status = IX_NPEDL_PARAM_ERR; + IX_NPEDL_ERROR_REPORT ("ixNpeDlMicrocodeImageLibraryOverride - " + "invalid parameter\n"); + } + else + { + status = ixNpeDlImageMgrMicrocodeImageLibraryOverride (clientImageLibrary); + if (status != IX_SUCCESS) + { + status = IX_FAIL; + } + } /* end of if-else(clientImageLibrary) */ + + IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, + "Exiting ixNpeDlMicrocodeImageLibraryOverride : " + "status = %d\n", status); + return status; +} + /* * Function definition: ixNpeDlImageDownload */ diff --git a/cpu/ixp/npe/IxNpeDlImageMgr.c b/cpu/ixp/npe/IxNpeDlImageMgr.c index ccc0da7eb..e05c22853 100644 --- a/cpu/ixp/npe/IxNpeDlImageMgr.c +++ b/cpu/ixp/npe/IxNpeDlImageMgr.c @@ -134,20 +134,12 @@ typedef struct static IxNpeDlImageMgrStats ixNpeDlImageMgrStats; /* default image */ -#ifdef CONFIG_IXP4XX_NPE_EXT_UCODE_BASE -static UINT32 *IxNpeMicroCodeImageLibrary = (UINT32 *)CONFIG_IXP4XX_NPE_EXT_UCODE_BASE; +#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE +static UINT32 *IxNpeMicroCodeImageLibrary = NULL; /* Gets set to proper value at runtime */ #else static UINT32 *IxNpeMicroCodeImageLibrary = (UINT32 *)IxNpeMicrocode_array; #endif -static UINT32* getIxNpeMicroCodeImageLibrary(void) -{ - char *s; - if ((s = getenv("npe_ucode")) != NULL) - return (UINT32*) simple_strtoul(s, NULL, 16); - else - return IxNpeMicroCodeImageLibrary; -} /* * static function prototypes. @@ -164,9 +156,8 @@ ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA, PRIVATE BOOL ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB); + IxNpeDlImageId *imageIdB); -#if 0 PRIVATE IX_STATUS ixNpeDlImageMgrImageFind_legacy (UINT32 *imageLibrary, UINT32 imageId, @@ -204,7 +195,7 @@ ixNpeDlImageMgrMicrocodeImageLibraryOverride ( status); return status; } -#endif + /* * Function definition: ixNpeDlImageMgrImageListExtract @@ -226,9 +217,9 @@ ixNpeDlImageMgrImageListExtract ( IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, "Entering ixNpeDlImageMgrImageListExtract\n"); - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); + header = (IxNpeDlImageMgrImageLibraryHeader *) IxNpeMicroCodeImageLibrary; - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) + if (ixNpeDlImageMgrSignatureCheck (IxNpeMicroCodeImageLibrary)) { /* for each image entry in the image header ... */ while (header->entry[imageCount].eohMarker != @@ -299,9 +290,9 @@ ixNpeDlImageMgrImageLocate ( IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, "Entering ixNpeDlImageMgrImageLocate\n"); - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); + header = (IxNpeDlImageMgrImageLibraryHeader *) IxNpeMicroCodeImageLibrary; - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) + if (ixNpeDlImageMgrSignatureCheck (IxNpeMicroCodeImageLibrary)) { /* for each image entry in the image library header ... */ while (header->entry[imageCount].eohMarker != @@ -316,9 +307,8 @@ ixNpeDlImageMgrImageLocate ( * get pointer to the image in the image library using offset from * 1st word in image library */ - UINT32 *tmp=getIxNpeMicroCodeImageLibrary(); imageOffset = header->entry[imageCount].image.offset; - *imagePtr = &tmp[imageOffset]; + *imagePtr = &IxNpeMicroCodeImageLibrary[imageOffset]; /* get the image size */ *imageSize = header->entry[imageCount].image.size; status = IX_SUCCESS; @@ -363,9 +353,9 @@ ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId) IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, "Entering ixNpeDlImageMgrLatestImageExtract\n"); - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); + header = (IxNpeDlImageMgrImageLibraryHeader *) IxNpeMicroCodeImageLibrary; - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) + if (ixNpeDlImageMgrSignatureCheck (IxNpeMicroCodeImageLibrary)) { /* for each image entry in the image library header ... */ while (header->entry[imageCount].eohMarker != @@ -537,7 +527,6 @@ ixNpeDlImageMgrStatsReset (void) } -#if 0 /* * Function definition: ixNpeDlImageMgrImageFind_legacy * @@ -611,7 +600,7 @@ ixNpeDlImageMgrImageFind_legacy ( "Exiting ixNpeDlImageMgrImageFind: status = %d\n", status); return status; } -#endif + /* * Function definition: ixNpeDlImageMgrImageFind @@ -642,11 +631,10 @@ ixNpeDlImageMgrImageFind ( imageLibrary = ixNpeMicrocode_binaryArray; } #else - imageLibrary = getIxNpeMicroCodeImageLibrary(); + imageLibrary = IxNpeMicroCodeImageLibrary; #endif /* IX_NPEDL_READ_MICROCODE_FROM_FILE */ } -#if 0 /* For backward's compatibility with previous image format */ if (ixNpeDlImageMgrSignatureCheck(imageLibrary)) { @@ -655,7 +643,6 @@ ixNpeDlImageMgrImageFind ( imagePtr, imageSize); } -#endif while (*(imageLibrary+offset) == NPE_IMAGE_MARKER) { diff --git a/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c b/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c index 18cac5020..9dcf3c1e4 100644 --- a/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c +++ b/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c @@ -613,9 +613,9 @@ ixNpeDlNpeMgrLogicalRegWrite ( if (verify) { - status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr, - regSize, ctxtNum, &retRegVal); - + status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr, + regSize, ctxtNum, &retRegVal); + if (IX_SUCCESS == status) { if (regVal != retRegVal) diff --git a/cpu/ixp/npe/IxOsalIoMem.c b/cpu/ixp/npe/IxOsalIoMem.c index 34df92bf7..9e540c18e 100644 --- a/cpu/ixp/npe/IxOsalIoMem.c +++ b/cpu/ixp/npe/IxOsalIoMem.c @@ -281,7 +281,7 @@ ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType) * Return value: corresponding physical address, or NULL * if there is no physical address addressable * by the given virtual address - * OS: VxWorks, Linux, WinCE, QNX, eCos + * OS: VxWorks, Linux, WinCE, QNX, eCos * Reentrant: Yes * IRQ safe: Yes */ @@ -310,7 +310,7 @@ ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency) * Return value: corresponding physical address, or NULL * if there is no physical address addressable * by the given virtual address - * OS: VxWorks, Linux, WinCE, QNX, eCos + * OS: VxWorks, Linux, WinCE, QNX, eCos * Reentrant: Yes * IRQ safe: Yes */ diff --git a/cpu/ixp/npe/IxQMgrAqmIf.c b/cpu/ixp/npe/IxQMgrAqmIf.c index 738651322..b27b3a287 100644 --- a/cpu/ixp/npe/IxQMgrAqmIf.c +++ b/cpu/ixp/npe/IxQMgrAqmIf.c @@ -209,7 +209,7 @@ ixQMgrAqmIfInit (void) */ /* AQM Queue access reg addresses, per queue */ - ixQMgrAqmIfQueAccRegAddr[i] = + ixQMgrAqmIfQueAccRegAddr[i] = (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i)); ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr = (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i)); diff --git a/cpu/ixp/npe/IxQMgrQAccess.c b/cpu/ixp/npe/IxQMgrQAccess.c index 888573624..2c3e30269 100644 --- a/cpu/ixp/npe/IxQMgrQAccess.c +++ b/cpu/ixp/npe/IxQMgrQAccess.c @@ -360,7 +360,7 @@ ixQMgrQNumEntriesGet (IxQMgrQId qId, } else { - /* The queue is either empty, either moving, + /* The queue is either empty, either moving, * Client can retry if they wish */ *numEntriesPtr = 0; diff --git a/cpu/ixp/npe/Makefile b/cpu/ixp/npe/Makefile index 25117d787..937de9d47 100644 --- a/cpu/ixp/npe/Makefile +++ b/cpu/ixp/npe/Makefile @@ -23,13 +23,11 @@ include $(TOPDIR)/config.mk -LIB := $(obj)libnpe.a +LIB := libnpe.a -LOCAL_CFLAGS += -I$(TOPDIR)/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -CFLAGS += $(LOCAL_CFLAGS) -HOST_CFLAGS += $(LOCAL_CFLAGS) +CFLAGS += -I$(TOPDIR)/cpu/ixp/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -COBJS := npe.o \ +OBJS := npe.o \ miiphy.o \ IxOsalBufferMgt.o \ IxOsalIoMem.o \ @@ -72,6 +70,7 @@ COBJS := npe.o \ IxNpeDlImageMgr.o \ IxNpeDlNpeMgr.o \ IxNpeDlNpeMgrUtils.o \ + IxNpeMicrocode.o \ IxNpeMh.o \ IxNpeMhConfig.o \ IxNpeMhReceive.o \ @@ -79,24 +78,14 @@ COBJS := npe.o \ IxNpeMhSolicitedCbMgr.o \ IxNpeMhUnsolicitedCbMgr.o -ifndef CONFIG_IXP4XX_NPE_EXT_UCODE_BASE -COBJS += IxNpeMicrocode.o -endif - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - all: $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend - -######################################################################### +sinclude .depend diff --git a/cpu/ixp/npe/include/IxDmaAcc.h b/cpu/ixp/npe/include/IxDmaAcc.h index 45c7527de..53d262559 100644 --- a/cpu/ixp/npe/include/IxDmaAcc.h +++ b/cpu/ixp/npe/include/IxDmaAcc.h @@ -172,7 +172,7 @@ typedef UINT32 IxDmaAccRequestId; #define IX_DMA_REQUEST_FULL 16 /** - * @ingroup IxDmaAcc + * @ingroup IxDmaAcc * @brief DMA completion notification * This function is called to notify a client that the DMA has been completed * @param status @ref IxDmaReturnStatus [out] - reporting to client @@ -181,11 +181,11 @@ typedef UINT32 IxDmaAccRequestId; typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status); /** - * @ingroup IxDmaAcc + * @ingroup IxDmaAcc * * @fn ixDmaAccInit(IxNpeDlNpeId npeId) * - * @brief Initialise the DMA Access component + * @brief Initialise the DMA Access component * This function will initialise the DMA Access component internals * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer * @return @li IX_SUCCESS succesfully initialised the component @@ -196,7 +196,7 @@ PUBLIC IX_STATUS ixDmaAccInit(IxNpeDlNpeId npeId); /** - * @ingroup IxDmaAcc + * @ingroup IxDmaAcc * * @fn ixDmaAccDmaTransfer( IxDmaAccDmaCompleteCallback callback, @@ -225,8 +225,8 @@ ixDmaAccInit(IxNpeDlNpeId npeId); * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode * @param TransferWidth @ref IxDmaTransferWidth [in] - The DMA transfer width * - * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful - * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured + * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful + * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid diff --git a/cpu/ixp/npe/include/IxEthAcc.h b/cpu/ixp/npe/include/IxEthAcc.h index ff706c451..b424648e9 100644 --- a/cpu/ixp/npe/include/IxEthAcc.h +++ b/cpu/ixp/npe/include/IxEthAcc.h @@ -626,8 +626,8 @@ PUBLIC void ixEthAccUnload(void); * required features. * * Dependant on Services: (Must be initialized before using this service may be initialized) - * ixNPEmh - NPE Message handling service. - * ixQmgr - Queue Manager component. + * ixNPEmh - NPE Message handling service. + * ixQmgr - Queue Manager component. * * @param portId @ref IxEthAccPortId [in] * @@ -745,7 +745,7 @@ typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *b * * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId, IxEthAccPortTxDoneCallback txCallbackFn, - UINT32 callbackTag) + UINT32 callbackTag) * * @brief Register a callback function to allow * the transmitted buffers to return to the user. diff --git a/cpu/ixp/npe/include/IxEthAccMii_p.h b/cpu/ixp/npe/include/IxEthAccMii_p.h index 568d4a0fa..aa42f9c2a 100644 --- a/cpu/ixp/npe/include/IxEthAccMii_p.h +++ b/cpu/ixp/npe/include/IxEthAccMii_p.h @@ -81,13 +81,13 @@ #define IX_ETH_ACC_MII_STAT_REG 0x1 /* Status Register */ #define IX_ETH_ACC_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ #define IX_ETH_ACC_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ -#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ +#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ /* Advertisement Register */ -#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ +#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ /* partner ability Register */ #define IX_ETH_ACC_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ /* Expansion Register */ -#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ +#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ /* next-page transmit Register */ IxEthAccStatus ixEthAccMdioShow (void); diff --git a/cpu/ixp/npe/include/IxEthAcc_p.h b/cpu/ixp/npe/include/IxEthAcc_p.h index 0ee412355..37c55605d 100644 --- a/cpu/ixp/npe/include/IxEthAcc_p.h +++ b/cpu/ixp/npe/include/IxEthAcc_p.h @@ -262,7 +262,7 @@ typedef struct { IxEthAccPortTxDoneCallback txBufferDoneCallbackFn; UINT32 txCallbackTag; - IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */ + IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */ IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */ IxQMgrQId txQueue; /**< txQueue for this port */ IxEthAccTxDataStats stats; /**< Transmit s/w stats */ diff --git a/cpu/ixp/npe/include/IxEthMii.h b/cpu/ixp/npe/include/IxEthMii.h index 397253a94..a1bfe0672 100644 --- a/cpu/ixp/npe/include/IxEthMii.h +++ b/cpu/ixp/npe/include/IxEthMii.h @@ -106,9 +106,9 @@ PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount); * @ingroup IxEthMii * * @fn ixEthMiiPhyConfig(UINT32 phyAddr, - BOOL speed100, - BOOL fullDuplex, - BOOL autonegotiate) + BOOL speed100, + BOOL fullDuplex, + BOOL autonegotiate) * * * @brief Configure a PHY @@ -209,10 +209,10 @@ PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr); * @ingroup IxEthMii * * @fn ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg) + BOOL *linkUp, + BOOL *speed100, + BOOL *fullDuplex, + BOOL *autoneg) * * @brief Retrieve the current status of a PHY * Retrieve the link, speed, duplex and autonegotiation status of a PHY diff --git a/cpu/ixp/npe/include/IxI2cDrv.h b/cpu/ixp/npe/include/IxI2cDrv.h index 92c6b24b4..2472f31a7 100644 --- a/cpu/ixp/npe/include/IxI2cDrv.h +++ b/cpu/ixp/npe/include/IxI2cDrv.h @@ -64,8 +64,8 @@ /** * @ingroup IxI2cDrv * @brief The interval of micro/mili seconds the IXP will wait before it polls for - * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @ - * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected + * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @ + * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected * through the API ixI2cDrvDelayTypeSelect. */ #define IX_I2C_US_POLL_FOR_XFER_STATUS 20 diff --git a/cpu/ixp/npe/include/IxOsalAssert.h b/cpu/ixp/npe/include/IxOsalAssert.h index 04a4f515a..45cebcdaa 100644 --- a/cpu/ixp/npe/include/IxOsalAssert.h +++ b/cpu/ixp/npe/include/IxOsalAssert.h @@ -1,6 +1,6 @@ /* * @file IxOsalAssert.h - * @author Intel Corporation + * @author Intel Corporation * @date 25-08-2004 * * @brief description goes here diff --git a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h b/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h index 4cf80d31e..5ac3f0cac 100644 --- a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h +++ b/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h @@ -76,7 +76,7 @@ typedef IX_OSAL_MBUF_POOL IX_MBUF_POOL; #define IX_MBUF_MTYPE(m_blk_ptr) \ IX_OSAL_MBUF_MTYPE(m_blk_ptr) -#define IX_MBUF_FLAGS(m_blk_ptr) \ +#define IX_MBUF_FLAGS(m_blk_ptr) \ IX_OSAL_MBUF_FLAGS(m_blk_ptr) diff --git a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h b/cpu/ixp/npe/include/IxOsalBackwardMemMap.h index 3881a3b6d..18f8f24df 100644 --- a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h +++ b/cpu/ixp/npe/include/IxOsalBackwardMemMap.h @@ -136,6 +136,6 @@ #define IX_OSSERV_MEM_MAP(physAddr, size) IX_OSAL_MEM_MAP(physAddr, size) -#define IX_OSSERV_MEM_UNMAP(virtAddr) IX_OSAL_MEM_UNMAP(virtAddr) +#define IX_OSSERV_MEM_UNMAP(virtAddr) IX_OSAL_MEM_UNMAP(virtAddr) #endif /* IX_OSAL_BACKWARD_MEM_MAP_H */ diff --git a/cpu/ixp/npe/include/IxOsalIoMem.h b/cpu/ixp/npe/include/IxOsalIoMem.h index ea6d64d00..ac0ce6570 100644 --- a/cpu/ixp/npe/include/IxOsalIoMem.h +++ b/cpu/ixp/npe/include/IxOsalIoMem.h @@ -1,6 +1,6 @@ /* * @file IxOsalIoMem.h - * @author Intel Corporation + * @author Intel Corporation * @date 25-08-2004 * * @brief description goes here diff --git a/cpu/ixp/npe/include/IxOsalMemAccess.h b/cpu/ixp/npe/include/IxOsalMemAccess.h index 9e7fb87be..2ad0ccfbb 100644 --- a/cpu/ixp/npe/include/IxOsalMemAccess.h +++ b/cpu/ixp/npe/include/IxOsalMemAccess.h @@ -410,7 +410,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData) #define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_BE(wAddr) #define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_BE(sAddr) #define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_BE(bAddr) -#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_BE(wAddr, wData) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_BE(wAddr, wData) #define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_BE(sAddr, sData) #define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_BE(bAddr, bData) @@ -419,7 +419,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData) #define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_AC(wAddr) #define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_AC(sAddr) #define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_AC(bAddr) -#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData) #define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData) #define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData) @@ -428,7 +428,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData) #define IX_OSAL_READ_LONG(wAddr) IX_OSAL_READ_LONG_LE_DC(wAddr) #define IX_OSAL_READ_SHORT(sAddr) IX_OSAL_READ_SHORT_LE_DC(sAddr) #define IX_OSAL_READ_BYTE(bAddr) IX_OSAL_READ_BYTE_LE_DC(bAddr) -#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData) +#define IX_OSAL_WRITE_LONG(wAddr, wData) IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData) #define IX_OSAL_WRITE_SHORT(sAddr, sData) IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData) #define IX_OSAL_WRITE_BYTE(bAddr, bData) IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData) diff --git a/cpu/ixp/npe/include/IxOsalTypes.h b/cpu/ixp/npe/include/IxOsalTypes.h index a190a707e..c617ec578 100644 --- a/cpu/ixp/npe/include/IxOsalTypes.h +++ b/cpu/ixp/npe/include/IxOsalTypes.h @@ -175,7 +175,7 @@ typedef volatile INT32 VINT32; #ifndef __inline__ -#define __inline__ IX_OSAL_INLINE +#define __inline__ IX_OSAL_INLINE #endif diff --git a/cpu/ixp/npe/include/IxQMgr.h b/cpu/ixp/npe/include/IxQMgr.h index 165ed96e5..c083a2b32 100644 --- a/cpu/ixp/npe/include/IxQMgr.h +++ b/cpu/ixp/npe/include/IxQMgr.h @@ -1134,7 +1134,7 @@ ixQMgrQRead (IxQMgrQId qId, * day scenario there are many entries in the queue * and the counter does not reach zero. */ - if (infoPtr->qReadCount-- == 0) + if (infoPtr->qReadCount-- == 0) { /* There is maybe no entry in the queue * qReadCount is now negative, but will be corrected before @@ -1475,7 +1475,7 @@ ixQMgrQWrite (IxQMgrQId qId, ++entry; IX_QMGR_INLINE_WRITE_LONG(++qAccRegAddr, *entry); } - entrySize = infoPtr->qEntrySizeInWords; + entrySize = infoPtr->qEntrySizeInWords; } /* overflow is available for lower queues only */ diff --git a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h b/cpu/ixp/npe/include/IxQMgrAqmIf_p.h index 4f0f64d27..7f5733c5d 100644 --- a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h +++ b/cpu/ixp/npe/include/IxQMgrAqmIf_p.h @@ -498,7 +498,7 @@ ixQMgrAqmIfQPop (IxQMgrQId qId, volatile UINT32 *accRegAddr; accRegAddr = (UINT32*)(aqmBaseAddress + - IX_QMGR_Q_ACCESS_ADDR_GET(qId)); + IX_QMGR_Q_ACCESS_ADDR_GET(qId)); switch (numWords) { @@ -533,7 +533,7 @@ ixQMgrAqmIfQPush (IxQMgrQId qId, volatile UINT32 *accRegAddr; accRegAddr = (UINT32*)(aqmBaseAddress + - IX_QMGR_Q_ACCESS_ADDR_GET(qId)); + IX_QMGR_Q_ACCESS_ADDR_GET(qId)); switch (numWords) { @@ -683,9 +683,9 @@ ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, * multiple queues split accross registers */ registerAddress = (UINT32*)(aqmBaseAddress + - registerBaseAddrOffset + - ((qId / queuesPerRegWord) * - IX_QMGR_NUM_BYTES_PER_WORD)); + registerBaseAddrOffset + + ((qId / queuesPerRegWord) * + IX_QMGR_NUM_BYTES_PER_WORD)); /* * Get the status word diff --git a/cpu/ixp/npe/include/IxQueueAssignments.h b/cpu/ixp/npe/include/IxQueueAssignments.h index f7194e72e..0c1543fa7 100644 --- a/cpu/ixp/npe/include/IxQueueAssignments.h +++ b/cpu/ixp/npe/include/IxQueueAssignments.h @@ -409,7 +409,7 @@ * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration * */ -#define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4) +#define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4) /** * diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c index 892096b26..ab7ca8bef 100644 --- a/cpu/ixp/npe/npe.c +++ b/cpu/ixp/npe/npe.c @@ -67,7 +67,7 @@ static void *npe_alloc(int size) p = npe_alloc_free; npe_alloc_free += size; } else { - printf("npe_alloc: failed (count=%d, size=%d)!\n", count, size); + printf("%s: failed (count=%d, size=%d)!\n", count, size); } return p; } @@ -408,25 +408,25 @@ static int npe_init(struct eth_device *dev, bd_t * bis) if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback, (u32)p_npe) != IX_ETH_ACC_SUCCESS) { printf("can't register RX callback!\n"); - return -1; + return 0; } if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback, (u32)p_npe) != IX_ETH_ACC_SUCCESS) { printf("can't register TX callback!\n"); - return -1; + return 0; } npe_set_mac_address(dev); if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) { printf("can't enable port!\n"); - return -1; + return 0; } p_npe->active = 1; - return 0; + return 1; } #if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */ @@ -682,7 +682,7 @@ int npe_initialize(bd_t * bis) eth_register(dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write); #endif diff --git a/cpu/ixp/pci.c b/cpu/ixp/pci.c index 8c6b0b21b..84c4339ee 100644 --- a/cpu/ixp/pci.c +++ b/cpu/ixp/pci.c @@ -259,7 +259,7 @@ void pci_ixp_init (struct pci_controller *hose) /* ========================================================== - Init IXP PCI + Init IXP PCI ========================================================== */ REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval); diff --git a/cpu/ixp/serial.c b/cpu/ixp/serial.c index 45496318a..201595857 100644 --- a/cpu/ixp/serial.c +++ b/cpu/ixp/serial.c @@ -31,13 +31,6 @@ #include #include -/* - * 14.7456 MHz - * Baud Rate = -------------- - * 16 x Divisor - */ -#define SERIAL_CLOCK 921600 - DECLARE_GLOBAL_DATA_PTR; void serial_setbrg (void) @@ -45,8 +38,18 @@ void serial_setbrg (void) unsigned int quot = 0; int uart = CFG_IXP425_CONSOLE; - if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0)) - quot = SERIAL_CLOCK / gd->baudrate; + if (gd->baudrate == 1200) + quot = 192; + else if (gd->baudrate == 9600) + quot = 96; + else if (gd->baudrate == 19200) + quot = 48; + else if (gd->baudrate == 38400) + quot = 24; + else if (gd->baudrate == 57600) + quot = 16; + else if (gd->baudrate == 115200) + quot = 8; else hang (); @@ -58,14 +61,11 @@ void serial_setbrg (void) DLL(uart) = quot & 0xff; DLH(uart) = quot >> 8; LCR(uart) = LCR_WLS0 | LCR_WLS1; -#ifdef CONFIG_SERIAL_RTS_ACTIVE - MCR(uart) = MCR_RTS; /* set RTS active */ -#else - MCR(uart) = 0; /* set RTS inactive */ -#endif + IER(uart) = IER_UUE; } + /* * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. diff --git a/cpu/ixp/start.S b/cpu/ixp/start.S index d4c8e33bc..757cfaa2d 100644 --- a/cpu/ixp/start.S +++ b/cpu/ixp/start.S @@ -140,7 +140,7 @@ reset: CPWAIT r0 /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c8, c7, 0 CPWAIT r0 /* drain write and fill buffers */ @@ -160,22 +160,22 @@ reset: /* make sure flash is visible at 0 */ #if 0 - ldr r2, =IXP425_EXP_CFG0 + ldr r2, =IXP425_EXP_CFG0 ldr r1, [r2] orr r1, r1, #0x80000000 str r1, [r2] #endif - mov r1, #CFG_SDR_CONFIG + mov r1, #CFG_SDR_CONFIG ldr r2, =IXP425_SDR_CONFIG str r1, [r2] /* disable refresh cycles */ - mov r1, #0 + mov r1, #0 ldr r3, =IXP425_SDR_REFRESH str r1, [r3] /* send nop command */ - mov r1, #3 + mov r1, #3 ldr r4, =IXP425_SDR_IR str r1, [r4] DELAY_FOR 0x4000, r0 @@ -226,7 +226,7 @@ reset: CPWAIT r0 /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c8, c7, 0 CPWAIT r0 /* drain write and fill buffers */ @@ -234,7 +234,7 @@ reset: CPWAIT r0 /* move flash to 0x50000000 */ - ldr r2, =IXP425_EXP_CFG0 + ldr r2, =IXP425_EXP_CFG0 ldr r1, [r2] bic r1, r1, #0x80000000 str r1, [r2] @@ -247,7 +247,7 @@ reset: nop /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c8, c7, 0 CPWAIT r0 /* enable I cache */ @@ -293,7 +293,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -482,13 +482,13 @@ fiq: .globl reset_cpu reset_cpu: - ldr r1, =0x482e + ldr r1, =0x482e ldr r2, =IXP425_OSWK str r1, [r2] - ldr r1, =0x0fff + ldr r1, =0x0fff ldr r2, =IXP425_OSWT str r1, [r2] - ldr r1, =0x5 + ldr r1, =0x5 ldr r2, =IXP425_OSWE str r1, [r2] b reset_endless diff --git a/cpu/lh7a40x/Makefile b/cpu/lh7a40x/Makefile index bac2a640c..b45bd6a29 100644 --- a/cpu/lh7a40x/Makefile +++ b/cpu/lh7a40x/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = cpu.o speed.o interrupts.o serial.o +OBJS = cpu.o speed.o interrupts.o serial.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/lh7a40x/interrupts.c b/cpu/lh7a40x/interrupts.c index d01787f91..23d803993 100644 --- a/cpu/lh7a40x/interrupts.c +++ b/cpu/lh7a40x/interrupts.c @@ -33,6 +33,8 @@ #include #include +#include + static ulong timer_load_val = 0; /* macro to read the 16 bit timer */ @@ -44,6 +46,139 @@ static inline ulong READ_TIMER(void) return (timer->value & 0x0000ffff); } +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + static ulong timestamp; static ulong lastdec; diff --git a/cpu/lh7a40x/start.S b/cpu/lh7a40x/start.S index e4655d69b..fb748cffc 100644 --- a/cpu/lh7a40x/start.S +++ b/cpu/lh7a40x/start.S @@ -184,7 +184,7 @@ clear_bss: @add r0, r0, #4 /* start at first byte of bss */ /* why inc. 4 bytes past then? */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -347,31 +347,31 @@ cpu_init_crit: undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -379,7 +379,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -387,7 +387,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else @@ -396,13 +396,13 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif diff --git a/cpu/mcf52x2/Makefile b/cpu/mcf52x2/Makefile index 937cdd058..879deb714 100644 --- a/cpu/mcf52x2/Makefile +++ b/cpu/mcf52x2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,25 +25,21 @@ include $(TOPDIR)/config.mk # CFLAGS += -DET_DEBUG -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a -START = start.o -COBJS = interrupts.o cpu.o speed.o cpu_init.o +START = +OBJS = serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk index 650e340ae..650db8583 100644 --- a/cpu/mcf52x2/config.mk +++ b/cpu/mcf52x2/config.mk @@ -24,37 +24,4 @@ # PLATFORM_RELFLAGS += -ffixed-d7 -msep-data - -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg)) -is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg)) -is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg)) -is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg)) -is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg)) -is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg)) - - -ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) - -ifneq (,$(findstring CONFIG_M5249,$(is5249))) -PLATFORM_CPPFLAGS += -mcpu=5249 -endif -ifneq (,$(findstring CONFIG_M5253,$(is5253))) -PLATFORM_CPPFLAGS += -mcpu=5253 -endif -ifneq (,$(findstring CONFIG_M5271,$(is5271))) -PLATFORM_CPPFLAGS += -mcpu=5271 -endif -ifneq (,$(findstring CONFIG_M5272,$(is5272))) -PLATFORM_CPPFLAGS += -mcpu=5272 -endif -ifneq (,$(findstring CONFIG_M5275,$(is5275))) -PLATFORM_CPPFLAGS += -mcpu=5275 -endif -ifneq (,$(findstring CONFIG_M5282,$(is5282))) -PLATFORM_CPPFLAGS += -mcpu=5282 -endif - -else PLATFORM_CPPFLAGS += -m5307 -endif diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index d5d3d339c..aa6b2bd67 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -6,9 +6,6 @@ * (C) Copyright 2005 * BuS Elektronik GmbH & Co. KG * - * MCF5275 additions - * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) - * * See file CREDITS for list of people who contributed to this * project. * @@ -31,291 +28,176 @@ #include #include #include -#include #ifdef CONFIG_M5271 -/* - * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to - * determine which one we are running on, based on the Chip Identification - * Register (CIR). - */ -int checkcpu(void) +#include +#include +#endif + +#ifdef CONFIG_M5272 +#include +#include +#endif + +#ifdef CONFIG_M5282 +#include +#include +#endif + +#ifdef CONFIG_M5249 +#include +#endif + +#ifdef CONFIG_M5271 +int checkcpu (void) { char buf[32]; - unsigned short cir; /* Chip Identification Register */ - unsigned short pin; /* Part identification number */ - unsigned char prn; /* Part revision number */ - char *cpu_model; - - cir = mbar_readShort(MCF_CCM_CIR); - pin = cir >> MCF_CCM_CIR_PIN_LEN; - prn = cir & MCF_CCM_CIR_PRN_MASK; - - switch (pin) { - case MCF_CCM_CIR_PIN_MCF5270: - cpu_model = "5270"; - break; - case MCF_CCM_CIR_PIN_MCF5271: - cpu_model = "5271"; - break; - default: - cpu_model = NULL; - break; - } - - if (cpu_model) - printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", - cpu_model, prn, strmhz(buf, CFG_CLK)); - else - printf("CPU: Unknown - Freescale ColdFire MCF5271 family" - " (PIN: 0x%x) rev. %hu, at %s MHz\n", - pin, prn, strmhz(buf, CFG_CLK)); + printf ("CPU: Freescale Coldfire MCF5271 at %s MHz\n", strmhz(buf, CFG_CLK)); return 0; } -int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) -{ +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { mbar_writeByte(MCF_RCM_RCR, - MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); + MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT); return 0; }; #if defined(CONFIG_WATCHDOG) -void watchdog_reset(void) +void watchdog_reset (void) { mbar_writeShort(MCF_WTM_WSR, 0x5555); mbar_writeShort(MCF_WTM_WSR, 0xAAAA); } -int watchdog_disable(void) +int watchdog_disable (void) { mbar_writeShort(MCF_WTM_WCR, 0); return (0); } -int watchdog_init(void) +int watchdog_init (void) { mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN); return (0); } -#endif /* #ifdef CONFIG_WATCHDOG */ +#endif /* #ifdef CONFIG_WATCHDOG */ #endif #ifdef CONFIG_M5272 -int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) -{ - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { + volatile wdog_t * wdp = (wdog_t *)(CFG_MBAR + MCFSIM_WRRR); wdp->wdog_wrrr = 0; - udelay(1000); + udelay (1000); /* enable watchdog, set timeout to 0 and wait */ wdp->wdog_wrrr = 1; - while (1) ; + while (1); /* we don't return! */ return 0; }; -int checkcpu(void) -{ - volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); +int checkcpu(void) { + ulong *dirp = (ulong *)(CFG_MBAR + MCFSIM_DIR); uchar msk; - char *suf; + char *suf; - puts("CPU: "); - msk = (sysctrl->sc_dir > 28) & 0xf; + puts ("CPU: "); + msk = (*dirp > 28) & 0xf; switch (msk) { - case 0x2: - suf = "1K75N"; - break; - case 0x4: - suf = "3K75N"; - break; - default: - suf = NULL; - printf("Freescale MCF5272 (Mask:%01x)\n", msk); - break; - } + case 0x2: suf = "1K75N"; break; + case 0x4: suf = "3K75N"; break; + default: + suf = NULL; + printf ("Freescale MCF5272 (Mask:%01x)\n", msk); + break; + } if (suf) - printf("Freescale MCF5272 %s\n", suf); + printf ("Freescale MCF5272 %s\n", suf); return 0; }; #if defined(CONFIG_WATCHDOG) /* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) +void watchdog_reset (void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - wdt->wdog_wcr = 0; + volatile immap_t * regp = (volatile immap_t *)CFG_MBAR; + regp->wdog_reg.wdog_wcr = 0; } -int watchdog_disable(void) +int watchdog_disable (void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; - wdt->wdog_wcr = 0; /* reset watchdog counter */ - wdt->wdog_wirr = 0; /* disable watchdog interrupt */ - wdt->wdog_wrrr = 0; /* disable watchdog timer */ + regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ + regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ + regp->wdog_reg.wdog_wrrr = 0; /* disable watchdog timer */ - puts("WATCHDOG:disabled\n"); + puts ("WATCHDOG:disabled\n"); return (0); } -int watchdog_init(void) +int watchdog_init (void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + volatile immap_t *regp = (volatile immap_t *)CFG_MBAR; - wdt->wdog_wirr = 0; /* disable watchdog interrupt */ + regp->wdog_reg.wdog_wirr = 0; /* disable watchdog interrupt */ /* set timeout and enable watchdog */ - wdt->wdog_wrrr = - ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; - wdt->wdog_wcr = 0; /* reset watchdog counter */ + regp->wdog_reg.wdog_wrrr = ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; + regp->wdog_reg.wdog_wcr = 0; /* reset watchdog counter */ - puts("WATCHDOG:enabled\n"); + puts ("WATCHDOG:enabled\n"); return (0); } -#endif /* #ifdef CONFIG_WATCHDOG */ +#endif /* #ifdef CONFIG_WATCHDOG */ -#endif /* #ifdef CONFIG_M5272 */ +#endif /* #ifdef CONFIG_M5272 */ -#ifdef CONFIG_M5275 -int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); - - udelay(1000); - - rcm->rcr = RCM_RCR_SOFTRST; - - /* we don't return! */ - return 0; -}; - -int checkcpu(void) -{ - char buf[32]; - - printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", - strmhz(buf, CFG_CLK)); - return 0; -}; - - -#if defined(CONFIG_WATCHDOG) -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - wdt->wsr = 0x5555; - wdt->wsr = 0xAAAA; -} - -int watchdog_disable(void) -{ - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - - wdt->wsr = 0x5555; /* reset watchdog counter */ - wdt->wsr = 0xAAAA; - wdt->wcr = 0; /* disable watchdog timer */ - - puts("WATCHDOG:disabled\n"); - return (0); -} - -int watchdog_init(void) -{ - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - - wdt->wcr = 0; /* disable watchdog */ - - /* set timeout and enable watchdog */ - wdt->wmr = - ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1; - wdt->wsr = 0x5555; /* reset watchdog counter */ - wdt->wsr = 0xAAAA; - - puts("WATCHDOG:enabled\n"); - return (0); -} -#endif /* #ifdef CONFIG_WATCHDOG */ - -#endif /* #ifdef CONFIG_M5275 */ #ifdef CONFIG_M5282 -int checkcpu(void) +int checkcpu (void) { unsigned char resetsource = MCFRESET_RSR; - printf("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", - MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); - printf("Reset:%s%s%s%s%s%s%s\n", - (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", - (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", - (resetsource & MCFRESET_RSR_EXT) ? " External" : "", - (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", - (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", - (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", - (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : ""); + printf ("CPU: Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n", + MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK); + printf ("Reset:%s%s%s%s%s%s%s\n", + (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "", + (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "", + (resetsource & MCFRESET_RSR_EXT) ? " External" : "", + (resetsource & MCFRESET_RSR_POR) ? " Power On" : "", + (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "", + (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "", + (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "" + ); return 0; } -int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { MCFRESET_RCR = MCFRESET_RCR_SOFTRST; return 0; }; #endif -#ifdef CONFIG_M5249 -int checkcpu(void) +#ifdef CONFIG_M5249 /* test-only: todo... */ +int checkcpu (void) { char buf[32]; - printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", - strmhz(buf, CFG_CLK)); + printf ("CPU: Freescale Coldfire MCF5249 at %s MHz\n", strmhz(buf, CFG_CLK)); return 0; } -int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) -{ +int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { /* enable watchdog, set timeout to 0 and wait */ mbar_writeByte(MCFSIM_SYPCR, 0xc0); - while (1) ; - - /* we don't return! */ - return 0; -}; -#endif - -#ifdef CONFIG_M5253 -int checkcpu(void) -{ - char buf[32]; - - unsigned char resetsource = mbar_readLong(SIM_RSR); - printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", - strmhz(buf, CFG_CLK)); - - if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { - printf("Reset:%s%s\n", - (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" - : "", - (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : - ""); - } - return 0; -} - -int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) -{ - /* enable watchdog, set timeout to 0 and wait */ - mbar_writeByte(SIM_SYPCR, 0xc0); - while (1) ; + while (1); /* we don't return! */ return 0; diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 344bceeda..1748ea9d9 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -6,13 +6,6 @@ * (C) Copyright 2005 * BuS Elektronik GmbH & Co. KG * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * Hayden Fraser (Hayden.Fraser@freescale.com) - * - * MCF5275 additions - * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) - * * See file CREDITS for list of people who contributed to this * project. * @@ -34,78 +27,28 @@ #include #include -#include -#if defined(CONFIG_M5253) -/* - * Breath some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ - mbar_writeByte(MCFSIM_SYPCR, 0x00); - mbar_writeByte(MCFSIM_SWIVR, 0x0f); - mbar_writeByte(MCFSIM_SWSR, 0x00); - mbar_writeByte(MCFSIM_SWDICR, 0x00); - mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); - mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); - mbar_writeByte(MCFSIM_I2CICR, 0x00); - mbar_writeByte(MCFSIM_UART1ICR, 0x00); - mbar_writeByte(MCFSIM_UART2ICR, 0x00); - mbar_writeByte(MCFSIM_ICR6, 0x00); - mbar_writeByte(MCFSIM_ICR7, 0x00); - mbar_writeByte(MCFSIM_ICR8, 0x00); - mbar_writeByte(MCFSIM_ICR9, 0x00); - mbar_writeByte(MCFSIM_QSPIICR, 0x00); +#ifdef CONFIG_M5271 +#include +#include +#endif - mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); - mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ - mbar2_writeByte(MCFSIM_SPURVEC, 0x00); +#ifdef CONFIG_M5272 +#include +#include +#endif - /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ +#ifdef CONFIG_M5282 +#include +#include +#endif - /* - * Setup chip selects... - */ - - mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); - mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); - mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); - - mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); - mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); - mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); - - /* enable instruction cache now */ - icache_enable(); -} - -/*initialize higher level parts of CPU like timers */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - /* Setup Ports: */ - switch (CFG_UART_PORT) { - case 0: - break; - case 1: - break; - case 2: - break; - } -} -#endif /* #if defined(CONFIG_M5253) */ +#ifdef CONFIG_M5249 +#include +#endif #if defined(CONFIG_M5271) -void cpu_init_f(void) +void cpu_init_f (void) { #ifndef CONFIG_WATCHDOG /* Disable the watchdog if we aren't using it */ @@ -115,35 +58,25 @@ void cpu_init_f(void) /* Set clockspeed to 100MHz */ mbar_writeShort(MCF_FMPLL_SYNCR, MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); - while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; + while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK); + + /* Enable UART pins */ + mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | + MCF_GPIO_PAR_UART_U0RXD | + MCF_GPIO_PAR_UART_U1RXD_UART1 | + MCF_GPIO_PAR_UART_U1TXD_UART1); + + /* Enable Ethernet pins */ + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); } /* * initialize higher level parts of CPU like timers */ -int cpu_init_r(void) +int cpu_init_r (void) { return (0); } - -void uart_port_conf(void) -{ - /* Setup Ports: */ - switch (CFG_UART_PORT) { - case 0: - mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | - MCF_GPIO_PAR_UART_U0RXD); - break; - case 1: - mbar_writeShort(MCF_GPIO_PAR_UART, - MCF_GPIO_PAR_UART_U1RXD_UART1 | - MCF_GPIO_PAR_UART_U1TXD_UART1); - break; - case 2: - mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000); - break; - } -} #endif #if defined(CONFIG_M5272) @@ -154,68 +87,69 @@ void uart_port_conf(void) * initialize a bunch of registers, * initialize the UPM's */ -void cpu_init_f(void) +void cpu_init_f (void) { /* if we come from RAM we assume the CPU is * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM - volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR); - volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO); - volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); + volatile immap_t *regp = (immap_t *)CFG_MBAR; - sysctrl->sc_scr = CFG_SCR; - sysctrl->sc_spr = CFG_SPR; + volatile unsigned char *mbar; + mbar = (volatile unsigned char *) CFG_MBAR; + + regp->sysctrl_reg.sc_scr = CFG_SCR; + regp->sysctrl_reg.sc_spr = CFG_SPR; /* Setup Ports: */ - gpio->gpio_pacnt = CFG_PACNT; - gpio->gpio_paddr = CFG_PADDR; - gpio->gpio_padat = CFG_PADAT; - gpio->gpio_pbcnt = CFG_PBCNT; - gpio->gpio_pbddr = CFG_PBDDR; - gpio->gpio_pbdat = CFG_PBDAT; - gpio->gpio_pdcnt = CFG_PDCNT; + regp->gpio_reg.gpio_pacnt = CFG_PACNT; + regp->gpio_reg.gpio_paddr = CFG_PADDR; + regp->gpio_reg.gpio_padat = CFG_PADAT; + regp->gpio_reg.gpio_pbcnt = CFG_PBCNT; + regp->gpio_reg.gpio_pbddr = CFG_PBDDR; + regp->gpio_reg.gpio_pbdat = CFG_PBDAT; + regp->gpio_reg.gpio_pdcnt = CFG_PDCNT; /* Memory Controller: */ - csctrl->cs_br0 = CFG_BR0_PRELIM; - csctrl->cs_or0 = CFG_OR0_PRELIM; + regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM; + regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM; #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) - csctrl->cs_br1 = CFG_BR1_PRELIM; - csctrl->cs_or1 = CFG_OR1_PRELIM; + regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM; + regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM; #endif #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) - csctrl->cs_br2 = CFG_BR2_PRELIM; - csctrl->cs_or2 = CFG_OR2_PRELIM; + regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM; + regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM; #endif #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) - csctrl->cs_br3 = CFG_BR3_PRELIM; - csctrl->cs_or3 = CFG_OR3_PRELIM; + regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM; + regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM; #endif #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) - csctrl->cs_br4 = CFG_BR4_PRELIM; - csctrl->cs_or4 = CFG_OR4_PRELIM; + regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM; + regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM; #endif #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) - csctrl->cs_br5 = CFG_BR5_PRELIM; - csctrl->cs_or5 = CFG_OR5_PRELIM; + regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM; + regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM; #endif #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) - csctrl->cs_br6 = CFG_BR6_PRELIM; - csctrl->cs_or6 = CFG_OR6_PRELIM; + regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM; + regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM; #endif #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) - csctrl->cs_br7 = CFG_BR7_PRELIM; - csctrl->cs_or7 = CFG_OR7_PRELIM; + regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM; + regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM; #endif -#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ +#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ /* enable instruction cache now */ icache_enable(); @@ -225,138 +159,14 @@ void cpu_init_f(void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r(void) +int cpu_init_r (void) { return (0); } +#endif /* #if defined(CONFIG_M5272) */ -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - /* Setup Ports: */ - switch (CFG_UART_PORT) { - case 0: - gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); - gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); - break; - case 1: - gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); - gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); - break; - } -} -#endif /* #if defined(CONFIG_M5272) */ - -#if defined(CONFIG_M5275) - -/* - * Breathe some life into the CPU... - * - * Set up the memory map, - * initialize a bunch of registers, - * initialize the UPM's - */ -void cpu_init_f(void) -{ - /* if we come from RAM we assume the CPU is - * already initialized. - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM - volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG); - volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); - volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS); - - /* Kill watchdog so we can initialize the PLL */ - wdog_reg->wcr = 0; - - /* Memory Controller: */ - /* Flash */ - csctrl_reg->ar0 = CFG_AR0_PRELIM; - csctrl_reg->cr0 = CFG_CR0_PRELIM; - csctrl_reg->mr0 = CFG_MR0_PRELIM; - -#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM)) - csctrl_reg->ar1 = CFG_AR1_PRELIM; - csctrl_reg->cr1 = CFG_CR1_PRELIM; - csctrl_reg->mr1 = CFG_MR1_PRELIM; -#endif - -#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM)) - csctrl_reg->ar2 = CFG_AR2_PRELIM; - csctrl_reg->cr2 = CFG_CR2_PRELIM; - csctrl_reg->mr2 = CFG_MR2_PRELIM; -#endif - -#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM)) - csctrl_reg->ar3 = CFG_AR3_PRELIM; - csctrl_reg->cr3 = CFG_CR3_PRELIM; - csctrl_reg->mr3 = CFG_MR3_PRELIM; -#endif - -#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM)) - csctrl_reg->ar4 = CFG_AR4_PRELIM; - csctrl_reg->cr4 = CFG_CR4_PRELIM; - csctrl_reg->mr4 = CFG_MR4_PRELIM; -#endif - -#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM)) - csctrl_reg->ar5 = CFG_AR5_PRELIM; - csctrl_reg->cr5 = CFG_CR5_PRELIM; - csctrl_reg->mr5 = CFG_MR5_PRELIM; -#endif - -#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM)) - csctrl_reg->ar6 = CFG_AR6_PRELIM; - csctrl_reg->cr6 = CFG_CR6_PRELIM; - csctrl_reg->mr6 = CFG_MR6_PRELIM; -#endif - -#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM)) - csctrl_reg->ar7 = CFG_AR7_PRELIM; - csctrl_reg->cr7 = CFG_CR7_PRELIM; - csctrl_reg->mr7 = CFG_MR7_PRELIM; -#endif - -#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ - -#ifdef CONFIG_FSL_I2C - gpio_reg->par_feci2c = 0x000F; -#endif - - /* enable instruction cache now */ - icache_enable(); -} - -/* - * initialize higher level parts of CPU like timers - */ -int cpu_init_r(void) -{ - return (0); -} - -void uart_port_conf(void) -{ - volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; - - /* Setup Ports: */ - switch (CFG_UART_PORT) { - case 0: - gpio->par_uart |= UART0_ENABLE_MASK; - break; - case 1: - gpio->par_uart |= UART1_ENABLE_MASK; - break; - case 2: - gpio->par_uart |= UART2_ENABLE_MASK; - break; - } -} -#endif /* #if defined(CONFIG_M5275) */ - -#if defined(CONFIG_M5282) +#ifdef CONFIG_M5282 /* * Breath some life into the CPU... * @@ -364,7 +174,7 @@ void uart_port_conf(void) * initialize a bunch of registers, * initialize the UPM's */ -void cpu_init_f(void) +void cpu_init_f (void) { #ifndef CONFIG_WATCHDOG /* disable watchdog if we aren't using it */ @@ -373,11 +183,7 @@ void cpu_init_f(void) #ifndef CONFIG_MONITOR_IS_IN_RAM /* Set speed /PLL */ - MCFCLOCK_SYNCR = - MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD); - while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; - - MCFGPIO_PBCDPAR = 0xc0; + MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD); /* Set up the GPIO ports */ #ifdef CFG_PEPAR @@ -419,117 +225,128 @@ void cpu_init_f(void) else is doing it! */ #if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \ - defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS) + defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \ + defined(CFG_CS0_WS) - MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF; + MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF; -#if (CFG_CS0_WIDTH == 8) -#define CFG_CS0_PS MCFCSM_CSCR_PS_8 -#elif (CFG_CS0_WIDTH == 16) -#define CFG_CS0_PS MCFCSM_CSCR_PS_16 -#elif (CFG_CS0_WIDTH == 32) -#define CFG_CS0_PS MCFCSM_CSCR_PS_32 -#else -#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0" -#endif - MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS) - | CFG_CS0_PS | MCFCSM_CSCR_AA; + #if (CFG_CS0_WIDTH == 8) + #define CFG_CS0_PS MCFCSM_CSCR_PS_8 + #elif (CFG_CS0_WIDTH == 16) + #define CFG_CS0_PS MCFCSM_CSCR_PS_16 + #elif (CFG_CS0_WIDTH == 32) + #define CFG_CS0_PS MCFCSM_CSCR_PS_32 + #else + #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0" + #endif + MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS) + |CFG_CS0_PS + |MCFCSM_CSCR_AA; -#if (CFG_CS0_RO != 0) - MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) - | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; + #if (CFG_CS0_RO != 0) + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1) + |MCFCSM_CSMR_WP|MCFCSM_CSMR_V; + #else + MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V; + #endif #else - MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V; -#endif -#else -#waring "Chip Select 0 are not initialized/used" + #waring "Chip Select 0 are not initialized/used" #endif #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \ - defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS) + defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \ + defined(CFG_CS1_WS) MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF; -#if (CFG_CS1_WIDTH == 8) -#define CFG_CS1_PS MCFCSM_CSCR_PS_8 -#elif (CFG_CS1_WIDTH == 16) -#define CFG_CS1_PS MCFCSM_CSCR_PS_16 -#elif (CFG_CS1_WIDTH == 32) -#define CFG_CS1_PS MCFCSM_CSCR_PS_32 -#else -#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1" -#endif - MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS) - | CFG_CS1_PS | MCFCSM_CSCR_AA; + #if (CFG_CS1_WIDTH == 8) + #define CFG_CS1_PS MCFCSM_CSCR_PS_8 + #elif (CFG_CS1_WIDTH == 16) + #define CFG_CS1_PS MCFCSM_CSCR_PS_16 + #elif (CFG_CS1_WIDTH == 32) + #define CFG_CS1_PS MCFCSM_CSCR_PS_32 + #else + #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1" + #endif + MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS) + |CFG_CS1_PS + |MCFCSM_CSCR_AA; -#if (CFG_CS1_RO != 0) - MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1) - | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; + #if (CFG_CS1_RO != 0) + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1) + |MCFCSM_CSMR_WP + |MCFCSM_CSMR_V; + #else + MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1) + |MCFCSM_CSMR_V; + #endif #else - MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1) - | MCFCSM_CSMR_V; -#endif -#else -#warning "Chip Select 1 are not initialized/used" + #warning "Chip Select 1 are not initialized/used" #endif #if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \ - defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS) + defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \ + defined(CFG_CS2_WS) MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF; -#if (CFG_CS2_WIDTH == 8) -#define CFG_CS2_PS MCFCSM_CSCR_PS_8 -#elif (CFG_CS2_WIDTH == 16) -#define CFG_CS2_PS MCFCSM_CSCR_PS_16 -#elif (CFG_CS2_WIDTH == 32) -#define CFG_CS2_PS MCFCSM_CSCR_PS_32 -#else -#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2" -#endif - MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS) - | CFG_CS2_PS | MCFCSM_CSCR_AA; + #if (CFG_CS2_WIDTH == 8) + #define CFG_CS2_PS MCFCSM_CSCR_PS_8 + #elif (CFG_CS2_WIDTH == 16) + #define CFG_CS2_PS MCFCSM_CSCR_PS_16 + #elif (CFG_CS2_WIDTH == 32) + #define CFG_CS2_PS MCFCSM_CSCR_PS_32 + #else + #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2" + #endif + MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS) + |CFG_CS2_PS + |MCFCSM_CSCR_AA; -#if (CFG_CS2_RO != 0) - MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1) - | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; + #if (CFG_CS2_RO != 0) + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1) + |MCFCSM_CSMR_WP + |MCFCSM_CSMR_V; + #else + MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1) + |MCFCSM_CSMR_V; + #endif #else - MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1) - | MCFCSM_CSMR_V; -#endif -#else -#warning "Chip Select 2 are not initialized/used" + #warning "Chip Select 2 are not initialized/used" #endif #if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \ - defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS) + defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \ + defined(CFG_CS3_WS) MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF; -#if (CFG_CS3_WIDTH == 8) -#define CFG_CS3_PS MCFCSM_CSCR_PS_8 -#elif (CFG_CS3_WIDTH == 16) -#define CFG_CS3_PS MCFCSM_CSCR_PS_16 -#elif (CFG_CS3_WIDTH == 32) -#define CFG_CS3_PS MCFCSM_CSCR_PS_32 -#else -#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1" -#endif - MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS) - | CFG_CS3_PS | MCFCSM_CSCR_AA; + #if (CFG_CS3_WIDTH == 8) + #define CFG_CS3_PS MCFCSM_CSCR_PS_8 + #elif (CFG_CS3_WIDTH == 16) + #define CFG_CS3_PS MCFCSM_CSCR_PS_16 + #elif (CFG_CS3_WIDTH == 32) + #define CFG_CS3_PS MCFCSM_CSCR_PS_32 + #else + #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1" + #endif + MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS) + |CFG_CS3_PS + |MCFCSM_CSCR_AA; -#if (CFG_CS3_RO != 0) - MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1) - | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; + #if (CFG_CS3_RO != 0) + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1) + |MCFCSM_CSMR_WP + |MCFCSM_CSMR_V; + #else + MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1) + |MCFCSM_CSMR_V; + #endif #else - MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1) - | MCFCSM_CSMR_V; -#endif -#else -#warning "Chip Select 3 are not initialized/used" + #warning "Chip Select 3 are not initialized/used" #endif -#endif /* CONFIG_MONITOR_IS_IN_RAM */ +#endif /* CONFIG_MONITOR_IS_IN_RAM */ /* defer enabling cache until boot (see do_go) */ /* icache_enable(); */ @@ -538,29 +355,10 @@ void cpu_init_f(void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r(void) +int cpu_init_r (void) { return (0); } - -void uart_port_conf(void) -{ - /* Setup Ports: */ - switch (CFG_UART_PORT) { - case 0: - MCFGPIO_PUAPAR &= 0xFc; - MCFGPIO_PUAPAR |= 0x03; - break; - case 1: - MCFGPIO_PUAPAR &= 0xF3; - MCFGPIO_PUAPAR |= 0x0C; - break; - case 2: - MCFGPIO_PASPAR &= 0xFF0F; - MCFGPIO_PASPAR |= 0x00A0; - break; - } -} #endif #if defined(CONFIG_M5249) @@ -571,13 +369,33 @@ void uart_port_conf(void) * initialize a bunch of registers, * initialize the UPM's */ -void cpu_init_f(void) +void cpu_init_f (void) { +#ifndef CFG_PLL_BYPASS + /* + * Setup the PLL to run at the specified speed + * + */ + volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); + unsigned long pllcr; +#ifdef CFG_FAST_CLK + pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ +#else + pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ +#endif + cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ + pllcr ^= 0x00000001; /* Set pll bypass to 1 */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ + udelay(0x20); /* Wait for a lock ... */ +#endif /* #ifndef CFG_PLL_BYPASS */ + /* * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins - * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins - * which is their primary function. - * ~Jeremy + * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins + * which is their primary function. + * ~Jeremy */ mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); @@ -593,7 +411,7 @@ void cpu_init_f(void) * ~Jeremy * */ - mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ + mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ mbar_writeByte(MCFSIM_SYPCR, 0x00); mbar_writeByte(MCFSIM_SWIVR, 0x0f); mbar_writeByte(MCFSIM_SWSR, 0x00); @@ -613,7 +431,7 @@ void cpu_init_f(void) mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); - mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ + mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ /* Setup interrupt priorities for gpio7 */ /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ @@ -641,19 +459,8 @@ void cpu_init_f(void) /* * initialize higher level parts of CPU like timers */ -int cpu_init_r(void) +int cpu_init_r (void) { return (0); } - -void uart_port_conf(void) -{ - /* Setup Ports: */ - switch (CFG_UART_PORT) { - case 0: - break; - case 1: - break; - } -} -#endif /* #if defined(CONFIG_M5249) */ +#endif /* #if defined(CONFIG_M5249) */ diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c new file mode 100644 index 000000000..6db621472 --- /dev/null +++ b/cpu/mcf52x2/fec.c @@ -0,0 +1,604 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_M5271 +#include +#include +#endif + +#ifdef CONFIG_M5272 +#include +#include +#endif + +#ifdef CONFIG_M5282 +#include +#include +#endif + +#include +#include + +#ifdef CONFIG_M5272 +#define FEC_ADDR (CFG_MBAR + 0x840) +#endif +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) +#define FEC_ADDR (CFG_MBAR + 0x1000) +#endif + +#undef ET_DEBUG +#undef MII_DEBUG + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) + +#ifdef CFG_DISCOVER_PHY +#include +static void mii_discover_phy (void); +#endif + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 + +#define TX_BUF_CNT 2 + +#define TOUT_LOOP 100 + +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1520 + + +static char txbuf[DBUF_LENGTH]; + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +/* + * FEC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ + +typedef volatile struct CommonBufferDescriptor { + cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ + cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ +} RTXBD; + +static RTXBD *rtx = NULL; + +int eth_send (volatile void *packet, int length) +{ + int j, rc; + volatile fec_t *fecp = (fec_t *) (FEC_ADDR); + + /* section 16.9.23.3 + * Wait for ready + */ + j = 0; + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) + && (j < TOUT_LOOP)) { + udelay (1); + j++; + } + if (j >= TOUT_LOOP) { + printf ("TX not ready\n"); + } + + rtx->txbd[txIdx].cbd_bufaddr = (uint) packet; + rtx->txbd[txIdx].cbd_datlen = length; + rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST; + + /* Activate transmit Buffer Descriptor polling */ + fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */ + + j = 0; + while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) + && (j < TOUT_LOOP)) { + udelay (1); + j++; + } + if (j >= TOUT_LOOP) { + printf ("TX timeout\n"); + } +#ifdef ET_DEBUG + printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", + __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc, + (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2); +#endif + + /* return only status bits */ ; + rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS); + + txIdx = (txIdx + 1) % TX_BUF_CNT; + + return rc; +} + +int eth_rx (void) +{ + int length; + volatile fec_t *fecp = (fec_t *) FEC_ADDR; + + for (;;) { + /* section 16.9.23.2 */ + if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = rtx->rxbd[rxIdx].cbd_datlen; + + if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) { +#ifdef ET_DEBUG + printf ("%s[%d] err: %x\n", + __FUNCTION__, __LINE__, + rtx->rxbd[rxIdx].cbd_sc); +#endif + } else { + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[rxIdx], length - 4); + } + + /* Give the buffer back to the FEC. */ + rtx->rxbd[rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + rtx->rxbd[PKTBUFSRX - 1].cbd_sc = + (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } else { + rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; + rxIdx++; + } + + /* Try to fill Buffer Descriptors */ + fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ + } + + return length; +} + +/************************************************************** + * + * FEC Ethernet Initialization Routine + * + *************************************************************/ +#define FEC_ECNTRL_ETHER_EN 0x00000002 +#define FEC_ECNTRL_RESET 0x00000001 + +#define FEC_RCNTRL_BC_REJ 0x00000010 +#define FEC_RCNTRL_PROM 0x00000008 +#define FEC_RCNTRL_MII_MODE 0x00000004 +#define FEC_RCNTRL_DRT 0x00000002 +#define FEC_RCNTRL_LOOP 0x00000001 + +#define FEC_TCNTRL_FDEN 0x00000004 +#define FEC_TCNTRL_HBC 0x00000002 +#define FEC_TCNTRL_GTS 0x00000001 + +#define FEC_RESET_DELAY 50000 + +int eth_init (bd_t * bd) +{ +#ifndef CFG_ENET_BD_BASE + DECLARE_GLOBAL_DATA_PTR; +#endif + int i; + volatile fec_t *fecp = (fec_t *) (FEC_ADDR); + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. + */ + fecp->fec_ecntrl = FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) { + printf ("FEC_RESET_DELAY timeout\n"); + return 0; + } + + /* We use strictly polling mode only + */ + fecp->fec_imask = 0; + + /* Clear any pending interrupt */ + fecp->fec_ievent = 0xffffffff; + + /* Set station address */ +#define ea bd->bi_enetaddr + fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | + (ea[2] << 8) | (ea[3]); + fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16); +#ifdef ET_DEBUG + printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n", + ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]); +#endif +#undef ea + +#ifdef CONFIG_M5271 + /* Clear multicast address hash table + */ + fecp->fec_ghash_table_high = 0; + fecp->fec_ghash_table_low = 0; + + /* Clear individual address hash table + */ + fecp->fec_ihash_table_high = 0; + fecp->fec_ihash_table_low = 0; +#else + /* Clear multicast address hash table + */ +#ifdef CONFIG_M5282 + fecp->fec_ihash_table_high = 0; + fecp->fec_ihash_table_low = 0; +#else + fecp->fec_hash_table_high = 0; + fecp->fec_hash_table_low = 0; +#endif + + /* Set maximum receive buffer size. + */ + fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; + + /* + * Setup Buffers and Buffer Desriptors + */ + rxIdx = 0; + txIdx = 0; + + if (!rtx) { +#ifdef CFG_ENET_BD_BASE + rtx = (RTXBD *) CFG_ENET_BD_BASE; +#else + rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off - + (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t) + +0xFF) + & ~0xFF) + ); + debug("set ENET_DB_BASE to %lX\n",(long) rtx); +#endif + } + + /* + * Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: + * Empty, Wrap + */ + for (i = 0; i < PKTBUFSRX; i++) { + rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + rtx->rxbd[i].cbd_datlen = 0; /* Reset */ + rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + } + rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* + * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: + * Last, Tx CRC + */ + for (i = 0; i < TX_BUF_CNT; i++) { + rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; + rtx->txbd[i].cbd_datlen = 0; /* Reset */ + rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); + } + rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; + + /* Set receive and transmit descriptor base + */ + fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]); + fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]); + + /* Enable MII mode + */ + +#if 0 /* Full duplex mode */ + fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; + fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; +#else /* Half duplex mode */ + fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */ + fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; + fecp->fec_x_cntrl = 0; +#endif + /* Set MII speed */ + fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10; + fecp->fec_mii_speed *= 2; + + /* Configure port B for MII. + */ + /* port initialization was already made in cpu_init_f() */ + + /* Now enable the transmit and receive processing + */ + fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN; + +#ifdef CFG_DISCOVER_PHY + /* wait for the PHY to wake up after reset */ + mii_discover_phy (); +#endif + + /* And last, try to fill Rx Buffer Descriptors */ + fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */ + + return 1; +} + +void eth_halt (void) +{ + volatile fec_t *fecp = (fec_t *) FEC_ADDR; + + fecp->fec_ecntrl = 0; +} + + +#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) + +static int phyaddr = -1; /* didn't find a PHY yet */ +static uint phytype; + +/* Make MII read/write commands for the FEC. +*/ + +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18)) + +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18) | \ + (VAL & 0xffff)) + +/* Interrupt events/masks. +*/ +#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ +#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ +#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ +#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ +#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ +#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ +#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ +#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ +#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ +#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ + +/* PHY identification + */ +#define PHY_ID_LXT970 0x78100000 /* LXT970 */ +#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ +#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ +#define PHY_ID_QS6612 0x01814400 /* QS6612 */ +#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ +#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ +#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ + +/* send command to phy using mii, wait for result */ +static uint mii_send (uint mii_cmd) +{ + uint mii_reply; + volatile fec_t *ep = (fec_t *) (FEC_ADDR); + + ep->fec_mii_data = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */ + mii_reply = ep->fec_mii_data; /* result from phy */ + ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#if defined(CFG_DISCOVER_PHY) +static void mii_discover_phy (void) +{ +#define MAX_PHY_PASSES 11 + uint phyno; + int pass; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay (10000); /* wait 10ms */ + } + for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) { + phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf ("PHY type 0x%x pass %d type ", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= mii_send (mk_mii_read (phyno, + PHY_PHYIDR2)); + +#ifdef ET_DEBUG + printf ("PHY @ 0x%x pass %d type ", phyno, + pass); + switch (phytype & 0xfffffff0) { + case PHY_ID_LXT970: + printf ("LXT970\n"); + break; + case PHY_ID_LXT971: + printf ("LXT971\n"); + break; + case PHY_ID_82555: + printf ("82555\n"); + break; + case PHY_ID_QS6612: + printf ("QS6612\n"); + break; + case PHY_ID_AMD79C784: + printf ("AMD79C784\n"); + break; + case PHY_ID_LSI80225B: + printf ("LSI L80225/B\n"); + break; + default: + printf ("0x%08x\n", phytype); + break; + } +#endif + } + } + } + if (phyaddr < 0) { + printf ("No PHY device found.\n"); + } +} +#endif /* CFG_DISCOVER_PHY */ + +#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) + +static int mii_init_done = 0; + +/**************************************************************************** + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + **************************************************************************** + */ +void mii_init (void) +{ + volatile fec_t *fecp = (fec_t *) (FEC_ADDR); + + int i; + + if (mii_init_done != 0) { + return; + } + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. + */ + + fecp->fec_ecntrl = FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) { + printf ("FEC_RESET_DELAY timeout\n"); + return; + } + + /* We use strictly polling mode only + */ + fecp->fec_imask = 0; + + /* Clear any pending interrupt + */ + fecp->fec_ievent = 0xffffffff; + + /* Set MII speed */ + fecp->fec_mii_speed = 0x0e; + + /* Configure port B for MII. + */ + /* port initialization was already made in cpu_init_f() */ + + /* Now enable the transmit and receive processing */ + fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN; + + mii_init_done = 1; +} + +/***************************************************************************** + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + *****************************************************************************/ + +int mcf52x2_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send (mk_mii_read (addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf ("0x%04x\n", *value); +#endif + + return 0; +} + +int mcf52x2_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send (mk_mii_write (addr, reg, value)); + +#ifdef MII_DEBUG + printf ("0x%04x\n", value); +#endif + + return 0; +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */ +#endif /* CFG_CMD_NET, FEC_ENET */ + +int mcf52x2_miiphy_initialize(bd_t *bis) +{ +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET) +#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) + miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write); +#endif +#endif + return 0; +} diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c index b8fb7bb0e..116747ad3 100644 --- a/cpu/mcf52x2/interrupts.c +++ b/cpu/mcf52x2/interrupts.c @@ -1,10 +1,9 @@ /* + * (C) Copyright 2003 Josef Baumgartner + * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * * See file CREDITS for list of people who contributed to this * project. * @@ -27,12 +26,140 @@ #include #include #include -#include + +#ifdef CONFIG_M5271 +#include +#include +#endif #ifdef CONFIG_M5272 -int interrupt_init(void) +#include +#include +#endif + +#ifdef CONFIG_M5282 +#include +#include +#endif + +#ifdef CONFIG_M5249 +#include +#endif + + +#define NR_IRQS 31 + +/* + * Interrupt vector functions. + */ +struct interrupt_action { + interrupt_handler_t *handler; + void *arg; +}; + +static struct interrupt_action irq_vecs[NR_IRQS]; + +static __inline__ unsigned short get_sr (void) { - volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC); + unsigned short sr; + + asm volatile ("move.w %%sr,%0":"=r" (sr):); + + return sr; +} + +static __inline__ void set_sr (unsigned short sr) +{ + asm volatile ("move.w %0,%%sr"::"r" (sr)); +} + +/************************************************************************/ +/* + * Install and free an interrupt handler + */ +void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) +{ +#ifdef CONFIG_M5272 + volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); +#endif + int vec_base = 0; + +#ifdef CONFIG_M5272 + vec_base = intp->int_pivr & 0xe0; +#endif + + if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) { + printf ("irq_install_handler: wrong interrupt vector %d\n", + vec); + return; + } + + irq_vecs[vec - vec_base].handler = handler; + irq_vecs[vec - vec_base].arg = arg; +} + +void irq_free_handler (int vec) +{ +#ifdef CONFIG_M5272 + volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); +#endif + int vec_base = 0; + +#ifdef CONFIG_M5272 + vec_base = intp->int_pivr & 0xe0; +#endif + + if ((vec < vec_base) || (vec > vec_base + NR_IRQS)) { + return; + } + + irq_vecs[vec - vec_base].handler = NULL; + irq_vecs[vec - vec_base].arg = NULL; +} + +void enable_interrupts (void) +{ + unsigned short sr; + + sr = get_sr (); + set_sr (sr & ~0x0700); +} + +int disable_interrupts (void) +{ + unsigned short sr; + + sr = get_sr (); + set_sr (sr | 0x0700); + + return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */ +} + +void int_handler (struct pt_regs *fp) +{ +#ifdef CONFIG_M5272 + volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); +#endif + int vec, vec_base = 0; + + vec = (fp->vector >> 2) & 0xff; +#ifdef CONFIG_M5272 + vec_base = intp->int_pivr & 0xe0; +#endif + + if (irq_vecs[vec - vec_base].handler != NULL) { + irq_vecs[vec - + vec_base].handler (irq_vecs[vec - vec_base].arg); + } else { + printf ("\nBogus External Interrupt Vector %d\n", vec); + } +} + + +#ifdef CONFIG_M5272 +int interrupt_init (void) +{ + volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1); /* disable all external interrupts */ intp->int_icr1 = 0x88888888; @@ -43,59 +170,24 @@ int interrupt_init(void) /* initialize vector register */ intp->int_pivr = 0x40; - enable_interrupts(); + enable_interrupts (); return 0; } +#endif -#if defined(CONFIG_MCFTMR) -void dtimer_intr_setup(void) +#if defined(CONFIG_M5282) || defined(CONFIG_M5271) +int interrupt_init (void) { - volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE); - - intp->int_icr1 &= ~INT_ICR1_TMR3MASK; - intp->int_icr1 |= CFG_TMRINTR_PRI; -} -#endif /* CONFIG_MCFTMR */ -#endif /* CONFIG_M5272 */ - -#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275) -int interrupt_init(void) -{ - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); - - /* Make sure all interrupts are disabled */ - intp->imrl0 |= 0x1; - - enable_interrupts(); return 0; } +#endif -#if defined(CONFIG_MCFTMR) -void dtimer_intr_setup(void) +#ifdef CONFIG_M5249 +int interrupt_init (void) { - volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); - - intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; - intp->imrl0 &= 0xFFFFFFFE; - intp->imrl0 &= ~CFG_TMRINTR_MASK; -} -#endif /* CONFIG_MCFTMR */ -#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ - -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) -int interrupt_init(void) -{ - enable_interrupts(); + enable_interrupts (); return 0; } - -#if defined(CONFIG_MCFTMR) -void dtimer_intr_setup(void) -{ - mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); - mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI); -} -#endif /* CONFIG_MCFTMR */ -#endif /* CONFIG_M5249 || CONFIG_M5253 */ +#endif diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c new file mode 100644 index 000000000..8be09e34f --- /dev/null +++ b/cpu/mcf52x2/serial.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +#ifdef CONFIG_M5271 +#include +#endif + +#ifdef CONFIG_M5272 +#include +#endif + +#ifdef CONFIG_M5282 +#include +#endif + +#ifdef CONFIG_M5249 +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_M5249) || defined(CONFIG_M5271) +#define DoubleClock(a) ((double)(CFG_CLK/2) / 32.0 / (double)(a)) +#else +#define DoubleClock(a) ((double)(CFG_CLK) / 32.0 / (double)(a)) +#endif + +void rs_serial_setbaudrate(int port,int baudrate) +{ +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271) + volatile unsigned char *uartp; +# ifndef CONFIG_M5271 + double fraction; +# endif + double clock; + + if (port == 0) + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + else + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + + clock = DoubleClock(baudrate); /* Set baud above */ + + uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ + uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */ + +# ifndef CONFIG_M5271 + fraction = ((clock - (int)clock) * 16.0) + 0.5; + uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */ +# endif +#endif + +#if defined(CONFIG_M5282) + volatile unsigned char *uartp; + long clock; + + switch (port) { + case 1: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + break; + case 2: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); + break; + default: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + } + + clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */ + + uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */ + uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */ + +#endif +}; + +void rs_serial_init (int port, int baudrate) +{ + volatile unsigned char *uartp; + + /* + * Reset UART, get it into known state... + */ + switch (port) { + case 1: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2); + break; +#if defined(CONFIG_M5282) + case 2: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3); + break; +#endif + default: + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + } + + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */ + + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR; /* reset MR pointer */ + uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR; /* reset Error pointer */ + + /* + * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity. + */ + uartp[MCFUART_UMR] = MCFUART_MR1_PARITYNONE | MCFUART_MR1_CS8; + uartp[MCFUART_UMR] = MCFUART_MR2_STOP1; + + /* Mask UART interrupts */ + uartp[MCFUART_UIMR] = 0; + + /* Set clock Select Register: Tx/Rx clock is timer */ + uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER; + + rs_serial_setbaudrate (port, baudrate); + + /* Enable Tx/Rx */ + uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE; + + return; +} + +/****************************************************************************/ +/* + * Output a single character, using UART polled mode. + * This is used for console output. + */ + +void rs_put_char(char ch) +{ + volatile unsigned char *uartp; + int i; + + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + + for (i = 0; (i < 0x10000); i++) { + if (uartp[MCFUART_USR] & MCFUART_USR_TXREADY) + break; + } + uartp[MCFUART_UTB] = ch; + return; +} + +int rs_is_char(void) +{ + volatile unsigned char *uartp; + + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + return((uartp[MCFUART_USR] & MCFUART_USR_RXREADY) ? 1 : 0); +} + +int rs_get_char(void) +{ + volatile unsigned char *uartp; + + uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1); + return(uartp[MCFUART_URB]); +} + +void serial_setbrg(void) { + rs_serial_setbaudrate(0,gd->bd->bi_baudrate); +} + +int serial_init(void) { + rs_serial_init(0,gd->baudrate); + return 0; +} + + +void serial_putc(const char c) { + if (c == '\n') + serial_putc ('\r'); + rs_put_char(c); +} + +void serial_puts (const char *s) { + while (*s) + serial_putc(*s++); +} + +int serial_getc(void) { + while(!rs_is_char()) + WATCHDOG_RESET(); + + return rs_get_char(); +} + +int serial_tstc() { + return rs_is_char(); +} diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c index f6edd5b6f..ac860b2c6 100644 --- a/cpu/mcf52x2/speed.c +++ b/cpu/mcf52x2/speed.c @@ -2,9 +2,6 @@ * (C) Copyright 2003 * Josef Baumgartner * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * Hayden Fraser (Hayden.Fraser@freescale.com) - * * See file CREDITS for list of people who contributed to this * project. * @@ -26,7 +23,6 @@ #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -35,49 +31,8 @@ DECLARE_GLOBAL_DATA_PTR; */ int get_clocks (void) { -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) - volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); - unsigned long pllcr; - -#ifndef CFG_PLL_BYPASS - -#ifdef CONFIG_M5249 - /* Setup the PLL to run at the specified speed */ -#ifdef CFG_FAST_CLK - pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ -#else - pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ -#endif -#endif /* CONFIG_M5249 */ - -#ifdef CONFIG_M5253 - pllcr = CFG_PLLCR; -#endif /* CONFIG_M5253 */ - - cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ - pllcr ^= 0x00000001; /* Set pll bypass to 1 */ - mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ - udelay(0x20); /* Wait for a lock ... */ -#endif /* #ifndef CFG_PLL_BYPASS */ - -#endif /* CONFIG_M5249 || CONFIG_M5253 */ - -#if defined(CONFIG_M5275) - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); - - /* Setup PLL */ - pll->syncr = 0x01080000; - while (!(pll->synsr & FMPLL_SYNSR_LOCK)) - ; - pll->syncr = 0x01000000; - while (!(pll->synsr & FMPLL_SYNSR_LOCK)) - ; -#endif - gd->cpu_clk = CFG_CLK; -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275) +#ifdef CONFIG_M5249 gd->bus_clk = gd->cpu_clk / 2; #else gd->bus_clk = gd->cpu_clk; diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index a05490432..8a83ca5ef 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -56,7 +56,9 @@ _vectors: .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ -#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) +#if defined(CONFIG_R5200) +.long 0x400 +#elif defined(CONFIG_M5282) .long _start - TEXT_BASE #else .long _START @@ -119,7 +121,7 @@ _start: nop move.w #0x2700,%sr -#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) +#if defined(CONFIG_M5272) || defined(CONFIG_M5249) move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */ move.c %d0, %MBAR @@ -131,7 +133,7 @@ _start: move.l #(CFG_INIT_RAM_ADDR + 1), %d0 movec %d0, %RAMBAR0 -#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ +#endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */ #if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* Initialize IPSBAR */ @@ -142,7 +144,6 @@ _start: move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 -#if defined(CONFIG_M5282) #if (TEXT_BASE == CFG_INT_FLASH_BASE) /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */ @@ -157,41 +158,37 @@ _copy_flash: _flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 - movec %d0, %FLASHBAR + move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 + movec %d0, %RAMBAR0 jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: nop _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ - move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 - movec %d0, %RAMBAR1 + move.l #(CFG_INT_FLASH_BASE + 0x21), %d0 + movec %d0, %RAMBAR0 #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ -#endif #endif /* if we come from a pre-loader we have no exception table and * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) -#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) - move.l #CFG_INT_FLASH_BASE, %d0 -#else move.l #CFG_FLASH_BASE, %d0 -#endif movec %d0, %VBR #endif -#ifdef CONFIG_M5275 - /* Initialize IPSBAR */ - move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ - move.l %d0, 0x40000000 -/* movec %d0, %MBAR */ - - /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 - movec %d0, %RAMBAR1 +#ifdef CONFIG_R5200 + move.l #(_flash_setup-CFG_FLASH_BASE), %a0 + move.l #(_flash_setup_end-CFG_FLASH_BASE), %a1 + move.l #(CFG_INIT_RAM_ADDR), %a2 +_copy_flash: + move.l (%a0)+, (%a2)+ + cmp.l %a0, %a1 + bgt.s _copy_flash + jmp CFG_INIT_RAM_ADDR +_after_flash_copy: #endif #if 0 @@ -216,6 +213,24 @@ _after_flashbar_copy: /*------------------------------------------------------------------------------*/ +#ifdef CONFIG_R5200 +_flash_setup: + /* CSAR0 */ + move.l #((CFG_FLASH_BASE & 0xffff0000) >> 16), %d0 + move.w %d0, 0x40000080 + + /* CSCR0 */ + move.l #0x2180, %d0 /* 8 wait states, 16bit port, auto ack, */ + move.w %d0, 0x4000008A + + /* CSMR0 */ + move.l #0x001f0001, %d0 /* 2 MB, valid */ + move.l %d0, 0x40000084 + + jmp _after_flash_copy.L +_flash_setup_end: +#endif + /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -248,14 +263,14 @@ relocate_code: * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ - move.l %a0, %a1 + move.l %a0, %a1 add.l #(in_ram - CFG_MONITOR_BASE), %a1 jmp (%a1) in_ram: clear_bss: - /* + /* * Now clear BSS segment */ move.l %a0, %a1 @@ -309,10 +324,10 @@ clear_bss: /* set parameters for board_init_r */ move.l %a0,-(%sp) /* dest_addr */ move.l %d0,-(%sp) /* gd */ -#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \ - defined(CFG_HALT_BEFOR_RAM_JUMP) - halt -#endif + #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \ + defined(CFG_HALT_BEFOR_RAM_JUMP) + halt + #endif jsr (%a1) /*------------------------------------------------------------------------------*/ @@ -339,24 +354,6 @@ _int_handler: /*------------------------------------------------------------------------------*/ /* cache functions */ -#ifdef CONFIG_M5271 - .globl icache_enable -icache_enable: - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ - movec %d0, %ACR0 /* Enable cache */ - - move.l #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop - - move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts -#endif - #ifdef CONFIG_M5272 .globl icache_enable icache_enable: @@ -373,25 +370,6 @@ icache_enable: rts #endif -#if defined(CONFIG_M5275) -/* - * Instruction cache only - */ - .globl icache_enable -icache_enable: - move.l #0x01400000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0x0000c000, %d0 /* Setup SDRAM caching */ - movec %d0, %ACR0 /* Enable cache */ - move.l #0x00000000, %d0 /* No other caching */ - movec %d0, %ACR1 /* Enable cache */ - move.l #0x80400100, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - moveq #1, %d0 - move.l %d0, icache_state - rts -#endif - #ifdef CONFIG_M5282 .globl icache_enable icache_enable: @@ -409,14 +387,14 @@ icache_state_access_1: rts #endif -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) +#ifdef CONFIG_M5249 .globl icache_enable icache_enable: /* * Note: The 5249 Documentation doesn't give a bit position for CINV! * From the 5272 and the 5307 documentation, I have deduced that it is * probably CACR[24]. Should someone say something to Motorola? - * ~Jeremy + * ~Jeremy */ move.l #0x01000000, %d0 /* Invalidate whole cache */ move.c %d0,%CACR @@ -446,29 +424,13 @@ icache_state_access_2: .globl icache_status icache_status: icache_state_access_3: - move.l #(icache_state), %a0 - move.l (%a0), %d0 + move.l icache_state, %d0 rts .data icache_state: .long 0 /* cache is diabled on inirialization */ - .globl dcache_enable -dcache_enable: - /* dummy function */ - rts - - .globl dcache_disable -dcache_disable: - /* dummy function */ - rts - - .globl dcache_status -dcache_status: - /* dummy function */ - rts - /*------------------------------------------------------------------------------*/ .globl version_string @@ -476,4 +438,3 @@ version_string: .ascii U_BOOT_VERSION .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" - .align 4 diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile index 9d542013c..610043eca 100644 --- a/cpu/microblaze/Makefile +++ b/cpu/microblaze/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,26 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -SOBJS = irq.o -COBJS = cpu.o interrupts.o cache.o exception.o timer.o +OBJS = cpu.o interrupts.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c index 26e88cb51..ccf67e172 100644 --- a/cpu/microblaze/interrupts.c +++ b/cpu/microblaze/interrupts.c @@ -1,8 +1,6 @@ /* - * (C) Copyright 2007 Michal Simek * (C) Copyright 2004 Atmark Techno, Inc. * - * Michal SIMEK * Yasushi SHOJI * * See file CREDITS for list of people who contributed to this @@ -15,7 +13,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -24,197 +22,11 @@ * MA 02111-1307 USA */ -#include -#include -#include -#include - -#undef DEBUG_INT - -extern void microblaze_disable_interrupts (void); -extern void microblaze_enable_interrupts (void); - -void enable_interrupts (void) +void enable_interrupts(void) { - MSRSET(0x2); } -int disable_interrupts (void) +int disable_interrupts(void) { - MSRCLR(0x2); return 0; } - -#ifdef CFG_INTC_0 -#ifdef CFG_TIMER_0 -extern void timer_init (void); -#endif -#ifdef CFG_FSL_2 -extern void fsl_init2 (void); -#endif - - -static struct irq_action vecs[CFG_INTC_0_NUM]; - -/* mapping structure to interrupt controller */ -microblaze_intc_t *intc = (microblaze_intc_t *) (CFG_INTC_0_ADDR); - -/* default handler */ -void def_hdlr (void) -{ - puts ("def_hdlr\n"); -} - -void enable_one_interrupt (int irq) -{ - int mask; - int offset = 1; - offset <<= irq; - mask = intc->ier; - intc->ier = (mask | offset); -#ifdef DEBUG_INT - printf ("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask, - intc->ier); - printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, - intc->iar, intc->mer); -#endif -} - -void disable_one_interrupt (int irq) -{ - int mask; - int offset = 1; - offset <<= irq; - mask = intc->ier; - intc->ier = (mask & ~offset); -#ifdef DEBUG_INT - printf ("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask, - intc->ier); - printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, - intc->iar, intc->mer); -#endif -} - -/* adding new handler for interrupt */ -void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg) -{ - struct irq_action *act; - /* irq out of range */ - if ((irq < 0) || (irq > CFG_INTC_0_NUM)) { - puts ("IRQ out of range\n"); - return; - } - act = &vecs[irq]; - if (hdlr) { /* enable */ - act->handler = hdlr; - act->arg = arg; - act->count = 0; - enable_one_interrupt (irq); - } else { /* disable */ - act->handler = (interrupt_handler_t *) def_hdlr; - act->arg = (void *)irq; - disable_one_interrupt (irq); - } -} - -/* initialization interrupt controller - hardware */ -void intc_init (void) -{ - intc->mer = 0; - intc->ier = 0; - intc->iar = 0xFFFFFFFF; - /* XIntc_Start - hw_interrupt enable and all interrupt enable */ - intc->mer = 0x3; -#ifdef DEBUG_INT - printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, - intc->iar, intc->mer); -#endif -} - -int interrupts_init (void) -{ - int i; - /* initialize irq list */ - for (i = 0; i < CFG_INTC_0_NUM; i++) { - vecs[i].handler = (interrupt_handler_t *) def_hdlr; - vecs[i].arg = (void *)i; - vecs[i].count = 0; - } - /* initialize intc controller */ - intc_init (); -#ifdef CFG_TIMER_0 - timer_init (); -#endif -#ifdef CFG_FSL_2 - fsl_init2 (); -#endif - enable_interrupts (); - return 0; -} - -void interrupt_handler (void) -{ - int irqs = (intc->isr & intc->ier); /* find active interrupt */ - int i = 1; -#ifdef DEBUG_INT - int value; - printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, - intc->iar, intc->mer); - R14(value); - printf ("Interrupt handler on %x line, r14 %x\n", irqs, value); -#endif - struct irq_action *act = vecs; - while (irqs) { - if (irqs & 1) { -#ifdef DEBUG_INT - printf - ("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n", - act->handler, act->count, act->arg); -#endif - act->handler (act->arg); - act->count++; - intc->iar = i; - return; - } - irqs >>= 1; - act++; - i <<= 1; - } - -#ifdef DEBUG_INT - printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr, - intc->ier, intc->iar, intc->mer); - R14(value); - printf ("Interrupt handler on %x line, r14 %x\n", irqs, value); -#endif -} -#endif - -#if defined(CONFIG_CMD_IRQ) -#ifdef CFG_INTC_0 -int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - int i; - struct irq_action *act = vecs; - - puts ("\nInterrupt-Information:\n\n" - "Nr Routine Arg Count\n" - "-----------------------------\n"); - - for (i = 0; i < CFG_INTC_0_NUM; i++) { - if (act->handler != (interrupt_handler_t*) def_hdlr) { - printf ("%02d %08x %08x %d\n", i, - (int)act->handler, (int)act->arg, act->count); - } - act++; - } - puts ("\n"); - return (0); -} -#else -int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) -{ - puts ("Undefined interrupt controller\n"); -} -#endif -#endif diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S index 8740284ad..7efdbb097 100644 --- a/cpu/microblaze/start.S +++ b/cpu/microblaze/start.S @@ -1,8 +1,6 @@ /* - * (C) Copyright 2007 Michal Simek * (C) Copyright 2004 Atmark Techno, Inc. * - * Michal SIMEK * Yasushi SHOJI * * See file CREDITS for list of people who contributed to this @@ -15,7 +13,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -29,122 +27,10 @@ .text .global _start _start: - mts rmsr, r0 /* disable cache */ - addi r1, r0, CFG_INIT_SP_OFFSET - addi r1, r1, -4 /* Decrement SP to top of memory */ - /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/ - addi r6, r0, 0xb0000000 /* hex b000 opcode imm */ - swi r6, r0, 0x0 /* reset address */ - swi r6, r0, 0x8 /* user vector exception */ - swi r6, r0, 0x10 /* interrupt */ - swi r6, r0, 0x20 /* hardware exception */ - addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/ - swi r6, r0, 0x4 /* reset address */ - swi r6, r0, 0xC /* user vector exception */ - swi r6, r0, 0x14 /* interrupt */ - swi r6, r0, 0x24 /* hardware exception */ + addi r1, r0, CFG_SDRAM_BASE /* init stack pointer */ + addi r1, r1, CFG_SDRAM_SIZE /* set sp to high up */ -#ifdef CFG_RESET_ADDRESS - /* reset address */ - addik r6, r0, CFG_RESET_ADDRESS - sw r6, r1, r0 - lhu r7, r1, r0 - shi r7, r0, 0x2 - shi r6, r0, 0x6 -/* - * Copy U-Boot code to TEXT_BASE - * solve problem with sbrk_base - */ -#if (CFG_RESET_ADDRESS != TEXT_BASE) - addi r4, r0, __end - addi r5, r0, __text_start - rsub r4, r5, r4 /* size = __end - __text_start */ - addi r6, r0, CFG_RESET_ADDRESS /* source address */ - addi r7, r0, 0 /* counter */ -4: - lw r8, r6, r7 - sw r8, r5, r7 - addi r7, r7, 0x4 - cmp r8, r4, r7 - blti r8, 4b -#endif -#endif - -#ifdef CFG_USR_EXCEP - /* user_vector_exception */ - addik r6, r0, _exception_handler - sw r6, r1, r0 - lhu r7, r1, r0 - shi r7, r0, 0xa - shi r6, r0, 0xe -#endif - -#ifdef CFG_INTC_0 - /* interrupt_handler */ - addik r6, r0, _interrupt_handler - sw r6, r1, r0 - lhu r7, r1, r0 - shi r7, r0, 0x12 - shi r6, r0, 0x16 -#endif - - /* hardware exception */ - addik r6, r0, _hw_exception_handler - sw r6, r1, r0 - lhu r7, r1, r0 - shi r7, r0, 0x22 - shi r6, r0, 0x26 - - /* enable instruction and data cache */ - mfs r12, rmsr - ori r12, r12, 0xa0 - mts rmsr, r12 - -clear_bss: - /* clear BSS segments */ - addi r5, r0, __bss_start - addi r4, r0, __bss_end - cmp r6, r5, r4 - beqi r6, 3f -2: - swi r0, r5, 0 /* write zero to loc */ - addi r5, r5, 4 /* increment to next loc */ - cmp r6, r5, r4 /* check if we have reach the end */ - bnei r6, 2b -3: /* jumping to board_init */ brai board_init + 1: bri 1b - -/* - * Read 16bit little endian - */ - .text - .global in16 - .ent in16 - .align 2 -in16: lhu r3, r0, r5 - bslli r4, r3, 8 - bsrli r3, r3, 8 - andi r4, r4, 0xffff - or r3, r3, r4 - rtsd r15, 8 - sext16 r3, r3 - .end in16 - -/* - * Write 16bit little endian - * first parameter(r5) - address, second(r6) - short value - */ - .text - .global out16 - .ent out16 - .align 2 -out16: bslli r3, r6, 8 - bsrli r6, r6, 8 - andi r3, r3, 0xffff - or r3, r3, r6 - sh r3, r0, r5 - rtsd r15, 8 - or r0, r0, r0 - .end out16 diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile index 509178123..c8b30c758 100644 --- a/cpu/mips/Makefile +++ b/cpu/mips/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,30 +23,23 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a -SOBJS-y = cache.o -COBJS-y = cpu.o interrupts.o +START = start.o +OBJS = asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \ + cpu.o interrupts.o incaip_clock.o +SOBJS = incaip_wdt.o cache.o -SOBJS-$(CONFIG_INCA_IP) += incaip_wdt.o -COBJS-$(CONFIG_INCA_IP) += asc_serial.o incaip_clock.o -COBJS-$(CONFIG_PURPLE) += asc_serial.o -COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o +all: .depend $(START) $(LIB) -SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/mips/asc_serial.c b/cpu/mips/asc_serial.c index be686c2ae..d95ec3fd2 100644 --- a/cpu/mips/asc_serial.c +++ b/cpu/mips/asc_serial.c @@ -4,6 +4,8 @@ #include +#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP) + #ifdef CONFIG_PURPLE #define serial_init asc_serial_init #define serial_putc asc_serial_putc @@ -32,10 +34,10 @@ /* Interrupt status register bits */ #define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */ -#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */ +#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */ #define FBS_ISR_AE 0x00000010 /* ASC error interrupt */ #define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */ -#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */ +#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */ #define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */ #else @@ -366,3 +368,4 @@ int serial_tstc (void) return res; } +#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */ diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index d0cf8e0c1..078e8328b 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -23,6 +23,8 @@ */ #include +#ifdef CONFIG_AU1X00 + #if defined(CFG_DISCOVER_PHY) #error "PHY not supported yet" /* We just assume that we are running 100FD for now */ @@ -31,20 +33,20 @@ /* I assume ethernet behaves like au1000 */ -#ifdef CONFIG_SOC_AU1000 +#ifdef CONFIG_AU1000 /* Base address differ between cpu:s */ #define ETH0_BASE AU1000_ETH0_BASE #define MAC0_ENABLE AU1000_MAC0_ENABLE #else -#ifdef CONFIG_SOC_AU1100 +#ifdef CONFIG_AU1100 #define ETH0_BASE AU1100_ETH0_BASE #define MAC0_ENABLE AU1100_MAC0_ENABLE #else -#ifdef CONFIG_SOC_AU1500 +#ifdef CONFIG_AU1500 #define ETH0_BASE AU1500_ETH0_BASE #define MAC0_ENABLE AU1500_MAC0_ENABLE #else -#ifdef CONFIG_SOC_AU1550 +#ifdef CONFIG_AU1550 #define ETH0_BASE AU1550_ETH0_BASE #define MAC0_ENABLE AU1550_MAC0_ENABLE #else @@ -61,7 +63,7 @@ #include #include -#if defined(CONFIG_CMD_MII) +#if (CONFIG_COMMANDS & CFG_CMD_MII) #include #endif @@ -88,65 +90,6 @@ mac_fifo_t mac_fifo[NO_OF_FIFOS]; #define MAX_WAIT 1000 -#if defined(CONFIG_CMD_MII) -int au1x00_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short * value) -{ - volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); - volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); - u32 mii_control; - unsigned int timedout = 20; - - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_read busy timeout!!\n"); - return -1; - } - } - - mii_control = MAC_SET_MII_SELECT_REG(reg) | - MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ; - - *mii_control_reg = mii_control; - - timedout = 20; - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_read busy timeout!!\n"); - return -1; - } - } - *value = *mii_data_reg; - return 0; -} - -int au1x00_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); - volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); - u32 mii_control; - unsigned int timedout = 20; - - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_write busy timeout!!\n"); - return -1; - } - } - - mii_control = MAC_SET_MII_SELECT_REG(reg) | - MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE; - - *mii_data_reg = value; - *mii_control_reg = mii_control; - return 0; -} -#endif - static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){ volatile mac_fifo_t *fifo_tx = (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); @@ -298,10 +241,71 @@ int au1x00_enet_initialize(bd_t *bis){ eth_register(dev); -#if defined(CONFIG_CMD_MII) +#if (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register(dev->name, au1x00_miiphy_read, au1x00_miiphy_write); #endif return 1; } + +#if (CONFIG_COMMANDS & CFG_CMD_MII) +int au1x00_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short * value) +{ + volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); + volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); + u32 mii_control; + unsigned int timedout = 20; + + while (*mii_control_reg & MAC_MII_BUSY) { + udelay(1000); + if (--timedout == 0) { + printf("au1x00_eth: miiphy_read busy timeout!!\n"); + return -1; + } + } + + mii_control = MAC_SET_MII_SELECT_REG(reg) | + MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ; + + *mii_control_reg = mii_control; + + timedout = 20; + while (*mii_control_reg & MAC_MII_BUSY) { + udelay(1000); + if (--timedout == 0) { + printf("au1x00_eth: miiphy_read busy timeout!!\n"); + return -1; + } + } + *value = *mii_data_reg; + return 0; +} + +int au1x00_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); + volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); + u32 mii_control; + unsigned int timedout = 20; + + while (*mii_control_reg & MAC_MII_BUSY) { + udelay(1000); + if (--timedout == 0) { + printf("au1x00_eth: miiphy_write busy timeout!!\n"); + return; + } + } + + mii_control = MAC_SET_MII_SELECT_REG(reg) | + MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE; + + *mii_data_reg = value; + *mii_control_reg = mii_control; + return 0; +} +#endif /* CONFIG_COMMANDS & CFG_CMD_MII */ + +#endif /* CONFIG_AU1X00 */ diff --git a/cpu/mips/au1x00_serial.c b/cpu/mips/au1x00_serial.c index e8baab5b1..42c668ee3 100644 --- a/cpu/mips/au1x00_serial.c +++ b/cpu/mips/au1x00_serial.c @@ -26,6 +26,9 @@ */ #include + +#ifdef CONFIG_AU1X00 + #include #include @@ -76,7 +79,7 @@ void serial_setbrg (void) sd = (*sys_powerctrl & 0x03) + 2; /* calulate 2x baudrate and round */ - divisorx2 = ((CFG_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE))); + divisorx2 = ((CFG_HZ/(sd * 16 * CONFIG_BAUDRATE))); if (divisorx2 & 0x01) divisorx2 = divisorx2 + 1; @@ -129,3 +132,4 @@ int serial_tstc (void) } return 0; } +#endif /* CONFIG_SERIAL_AU1X00 */ diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c index 1ca8aafbb..dbf72dc6f 100644 --- a/cpu/mips/au1x00_usb_ohci.c +++ b/cpu/mips/au1x00_usb_ohci.c @@ -35,7 +35,7 @@ #include -#ifdef CONFIG_USB_OHCI +#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI) /* #include no PCI on the AU1x00 */ diff --git a/cpu/mips/au1x00_usb_ohci.h b/cpu/mips/au1x00_usb_ohci.h index 631ef0a22..4ef06ffde 100644 --- a/cpu/mips/au1x00_usb_ohci.h +++ b/cpu/mips/au1x00_usb_ohci.h @@ -11,31 +11,31 @@ static int cc_to_error[16] = { /* mapping of the OHCI CC status to error codes */ - /* No Error */ 0, - /* CRC Error */ USB_ST_CRC_ERR, - /* Bit Stuff */ USB_ST_BIT_ERR, - /* Data Togg */ USB_ST_CRC_ERR, - /* Stall */ USB_ST_STALLED, - /* DevNotResp */ -1, - /* PIDCheck */ USB_ST_BIT_ERR, - /* UnExpPID */ USB_ST_BIT_ERR, - /* DataOver */ USB_ST_BUF_ERR, - /* DataUnder */ USB_ST_BUF_ERR, - /* reservd */ -1, - /* reservd */ -1, - /* BufferOver */ USB_ST_BUF_ERR, - /* BuffUnder */ USB_ST_BUF_ERR, - /* Not Access */ -1, - /* Not Access */ -1 + /* No Error */ 0, + /* CRC Error */ USB_ST_CRC_ERR, + /* Bit Stuff */ USB_ST_BIT_ERR, + /* Data Togg */ USB_ST_CRC_ERR, + /* Stall */ USB_ST_STALLED, + /* DevNotResp */ -1, + /* PIDCheck */ USB_ST_BIT_ERR, + /* UnExpPID */ USB_ST_BIT_ERR, + /* DataOver */ USB_ST_BUF_ERR, + /* DataUnder */ USB_ST_BUF_ERR, + /* reservd */ -1, + /* reservd */ -1, + /* BufferOver */ USB_ST_BUF_ERR, + /* BuffUnder */ USB_ST_BUF_ERR, + /* Not Access */ -1, + /* Not Access */ -1 }; /* ED States */ -#define ED_NEW 0x00 -#define ED_UNLINK 0x01 +#define ED_NEW 0x00 +#define ED_UNLINK 0x01 #define ED_OPER 0x02 #define ED_DEL 0x04 -#define ED_URB_DEL 0x08 +#define ED_URB_DEL 0x08 /* usb_ohci_ed */ struct ed { @@ -61,54 +61,54 @@ typedef struct ed ed_t; /* TD info field */ -#define TD_CC 0xf0000000 -#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) -#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) -#define TD_EC 0x0C000000 -#define TD_T 0x03000000 -#define TD_T_DATA0 0x02000000 -#define TD_T_DATA1 0x03000000 -#define TD_T_TOGGLE 0x00000000 -#define TD_R 0x00040000 -#define TD_DI 0x00E00000 -#define TD_DI_SET(X) (((X) & 0x07)<< 21) -#define TD_DP 0x00180000 -#define TD_DP_SETUP 0x00000000 -#define TD_DP_IN 0x00100000 -#define TD_DP_OUT 0x00080000 +#define TD_CC 0xf0000000 +#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) +#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) +#define TD_EC 0x0C000000 +#define TD_T 0x03000000 +#define TD_T_DATA0 0x02000000 +#define TD_T_DATA1 0x03000000 +#define TD_T_TOGGLE 0x00000000 +#define TD_R 0x00040000 +#define TD_DI 0x00E00000 +#define TD_DI_SET(X) (((X) & 0x07)<< 21) +#define TD_DP 0x00180000 +#define TD_DP_SETUP 0x00000000 +#define TD_DP_IN 0x00100000 +#define TD_DP_OUT 0x00080000 -#define TD_ISO 0x00010000 -#define TD_DEL 0x00020000 +#define TD_ISO 0x00010000 +#define TD_DEL 0x00020000 /* CC Codes */ -#define TD_CC_NOERROR 0x00 -#define TD_CC_CRC 0x01 -#define TD_CC_BITSTUFFING 0x02 -#define TD_CC_DATATOGGLEM 0x03 -#define TD_CC_STALL 0x04 -#define TD_DEVNOTRESP 0x05 -#define TD_PIDCHECKFAIL 0x06 -#define TD_UNEXPECTEDPID 0x07 -#define TD_DATAOVERRUN 0x08 -#define TD_DATAUNDERRUN 0x09 -#define TD_BUFFEROVERRUN 0x0C -#define TD_BUFFERUNDERRUN 0x0D -#define TD_NOTACCESSED 0x0F +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEM 0x03 +#define TD_CC_STALL 0x04 +#define TD_DEVNOTRESP 0x05 +#define TD_PIDCHECKFAIL 0x06 +#define TD_UNEXPECTEDPID 0x07 +#define TD_DATAOVERRUN 0x08 +#define TD_DATAUNDERRUN 0x09 +#define TD_BUFFEROVERRUN 0x0C +#define TD_BUFFERUNDERRUN 0x0D +#define TD_NOTACCESSED 0x0F #define MAXPSW 1 struct td { __u32 hwINFO; - __u32 hwCBP; /* Current Buffer Pointer */ - __u32 hwNextTD; /* Next TD Pointer */ - __u32 hwBE; /* Memory Buffer End Pointer */ + __u32 hwCBP; /* Current Buffer Pointer */ + __u32 hwNextTD; /* Next TD Pointer */ + __u32 hwBE; /* Memory Buffer End Pointer */ - __u16 hwPSW[MAXPSW]; - __u8 unused; - __u8 index; - struct ed *ed; - struct td *next_dl_td; + __u16 hwPSW[MAXPSW]; + __u8 unused; + __u8 index; + struct ed *ed; + struct td *next_dl_td; struct usb_device *usb_dev; int transfer_len; __u32 data; @@ -142,7 +142,7 @@ struct ohci_hcca { /* * This is the structure of the OHCI controller's memory mapped I/O - * region. This is Memory Mapped I/O. You must use the readl() and + * region. This is Memory Mapped I/O. You must use the readl() and * writel() macros defined in asm/io.h to access these!! */ struct ohci_regs { @@ -202,10 +202,10 @@ struct ohci_regs { * HcCommandStatus (cmdstatus) register masks */ #define OHCI_HCR (1 << 0) /* host controller reset */ -#define OHCI_CLF (1 << 1) /* control list filled */ -#define OHCI_BLF (1 << 2) /* bulk list filled */ -#define OHCI_OCR (1 << 3) /* ownership change request */ -#define OHCI_SOC (3 << 16) /* scheduling overrun count */ +#define OHCI_CLF (1 << 1) /* control list filled */ +#define OHCI_BLF (1 << 2) /* bulk list filled */ +#define OHCI_OCR (1 << 3) /* ownership change request */ +#define OHCI_SOC (3 << 16) /* scheduling overrun count */ /* * masks used with interrupt registers: @@ -236,101 +236,101 @@ struct virt_root_hub { /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */ /* destination of request */ -#define RH_INTERFACE 0x01 -#define RH_ENDPOINT 0x02 -#define RH_OTHER 0x03 +#define RH_INTERFACE 0x01 +#define RH_ENDPOINT 0x02 +#define RH_OTHER 0x03 -#define RH_CLASS 0x20 -#define RH_VENDOR 0x40 +#define RH_CLASS 0x20 +#define RH_VENDOR 0x40 /* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 #define RH_SET_ADDRESS 0x0500 #define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 +#define RH_SET_DESCRIPTOR 0x0700 #define RH_GET_CONFIGURATION 0x0880 #define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 /* Our Vendor Specific Request */ -#define RH_SET_EP 0x2000 +#define RH_SET_EP 0x2000 /* Hub port features */ -#define RH_PORT_CONNECTION 0x00 -#define RH_PORT_ENABLE 0x01 -#define RH_PORT_SUSPEND 0x02 -#define RH_PORT_OVER_CURRENT 0x03 -#define RH_PORT_RESET 0x04 -#define RH_PORT_POWER 0x08 -#define RH_PORT_LOW_SPEED 0x09 +#define RH_PORT_CONNECTION 0x00 +#define RH_PORT_ENABLE 0x01 +#define RH_PORT_SUSPEND 0x02 +#define RH_PORT_OVER_CURRENT 0x03 +#define RH_PORT_RESET 0x04 +#define RH_PORT_POWER 0x08 +#define RH_PORT_LOW_SPEED 0x09 -#define RH_C_PORT_CONNECTION 0x10 -#define RH_C_PORT_ENABLE 0x11 -#define RH_C_PORT_SUSPEND 0x12 -#define RH_C_PORT_OVER_CURRENT 0x13 -#define RH_C_PORT_RESET 0x14 +#define RH_C_PORT_CONNECTION 0x10 +#define RH_C_PORT_ENABLE 0x11 +#define RH_C_PORT_SUSPEND 0x12 +#define RH_C_PORT_OVER_CURRENT 0x13 +#define RH_C_PORT_RESET 0x14 /* Hub features */ -#define RH_C_HUB_LOCAL_POWER 0x00 -#define RH_C_HUB_OVER_CURRENT 0x01 +#define RH_C_HUB_LOCAL_POWER 0x00 +#define RH_C_HUB_OVER_CURRENT 0x01 -#define RH_DEVICE_REMOTE_WAKEUP 0x00 -#define RH_ENDPOINT_STALL 0x01 +#define RH_DEVICE_REMOTE_WAKEUP 0x00 +#define RH_ENDPOINT_STALL 0x01 -#define RH_ACK 0x01 -#define RH_REQ_ERR -1 -#define RH_NACK 0x00 +#define RH_ACK 0x01 +#define RH_REQ_ERR -1 +#define RH_NACK 0x00 /* OHCI ROOT HUB REGISTER MASKS */ /* roothub.portstatus [i] bits */ -#define RH_PS_CCS 0x00000001 /* current connect status */ -#define RH_PS_PES 0x00000002 /* port enable status*/ -#define RH_PS_PSS 0x00000004 /* port suspend status */ -#define RH_PS_POCI 0x00000008 /* port over current indicator */ -#define RH_PS_PRS 0x00000010 /* port reset status */ -#define RH_PS_PPS 0x00000100 /* port power status */ -#define RH_PS_LSDA 0x00000200 /* low speed device attached */ -#define RH_PS_CSC 0x00010000 /* connect status change */ -#define RH_PS_PESC 0x00020000 /* port enable status change */ -#define RH_PS_PSSC 0x00040000 /* port suspend status change */ -#define RH_PS_OCIC 0x00080000 /* over current indicator change */ -#define RH_PS_PRSC 0x00100000 /* port reset status change */ +#define RH_PS_CCS 0x00000001 /* current connect status */ +#define RH_PS_PES 0x00000002 /* port enable status*/ +#define RH_PS_PSS 0x00000004 /* port suspend status */ +#define RH_PS_POCI 0x00000008 /* port over current indicator */ +#define RH_PS_PRS 0x00000010 /* port reset status */ +#define RH_PS_PPS 0x00000100 /* port power status */ +#define RH_PS_LSDA 0x00000200 /* low speed device attached */ +#define RH_PS_CSC 0x00010000 /* connect status change */ +#define RH_PS_PESC 0x00020000 /* port enable status change */ +#define RH_PS_PSSC 0x00040000 /* port suspend status change */ +#define RH_PS_OCIC 0x00080000 /* over current indicator change */ +#define RH_PS_PRSC 0x00100000 /* port reset status change */ /* roothub.status bits */ -#define RH_HS_LPS 0x00000001 /* local power status */ -#define RH_HS_OCI 0x00000002 /* over current indicator */ -#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ -#define RH_HS_LPSC 0x00010000 /* local power status change */ -#define RH_HS_OCIC 0x00020000 /* over current indicator change */ -#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ +#define RH_HS_LPS 0x00000001 /* local power status */ +#define RH_HS_OCI 0x00000002 /* over current indicator */ +#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ +#define RH_HS_LPSC 0x00010000 /* local power status change */ +#define RH_HS_OCIC 0x00020000 /* over current indicator change */ +#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ /* roothub.b masks */ -#define RH_B_DR 0x0000ffff /* device removable flags */ -#define RH_B_PPCM 0xffff0000 /* port power control mask */ +#define RH_B_DR 0x0000ffff /* device removable flags */ +#define RH_B_PPCM 0xffff0000 /* port power control mask */ /* roothub.a masks */ -#define RH_A_NDP (0xff << 0) /* number of downstream ports */ -#define RH_A_PSM (1 << 8) /* power switching mode */ -#define RH_A_NPS (1 << 9) /* no power switching */ -#define RH_A_DT (1 << 10) /* device type (mbz) */ -#define RH_A_OCPM (1 << 11) /* over current protection mode */ -#define RH_A_NOCP (1 << 12) /* no over current protection */ -#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ +#define RH_A_NDP (0xff << 0) /* number of downstream ports */ +#define RH_A_PSM (1 << 8) /* power switching mode */ +#define RH_A_NPS (1 << 9) /* no power switching */ +#define RH_A_DT (1 << 10) /* device type (mbz) */ +#define RH_A_OCPM (1 << 11) /* over current protection mode */ +#define RH_A_NOCP (1 << 12) /* no over current protection */ +#define RH_A_POTPGT (0xff << 24) /* power on to power good time */ /* urb */ #define N_URB_TD 48 typedef struct { ed_t *ed; - __u16 length; /* number of tds associated with this request */ - __u16 td_cnt; /* number of tds already serviced */ + __u16 length; /* number of tds associated with this request */ + __u16 td_cnt; /* number of tds already serviced */ int state; unsigned long pipe; int actual_length; @@ -355,11 +355,11 @@ typedef struct ohci { int sleeping; unsigned long flags; /* for HC bugs */ - struct ohci_regs *regs; /* OHCI controller's memory */ + struct ohci_regs *regs; /* OHCI controller's memory */ - ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ - ed_t *ed_bulktail; /* last endpoint of bulk list */ - ed_t *ed_controltail; /* last endpoint of control list */ + ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */ + ed_t *ed_bulktail; /* last endpoint of bulk list */ + ed_t *ed_controltail; /* last endpoint of control list */ int intrstatus; __u32 hc_control; /* copy of the hc control reg */ struct usb_device *dev[32]; @@ -371,7 +371,7 @@ typedef struct ohci { #define NUM_EDS 8 /* num of preallocated endpoint descriptors */ struct ohci_device { - ed_t ed[NUM_EDS]; + ed_t ed[NUM_EDS]; int ed_cnt; }; diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index ee5d411e4..aad76e0af 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -1,5 +1,5 @@ /* - * Cache-handling routined for MIPS CPUs + * Cache-handling routined for MIPS 4K CPUs * * Copyright (c) 2003 Wolfgang Denk * @@ -22,33 +22,20 @@ * MA 02111-1307 USA */ + #include -#include +#include #include #include #include #include -#define RA t8 -/* - * 16kB is the maximum size of instruction and data caches on MIPS 4K, - * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. - * - * Note that the above size is the maximum size of primary cache. U-Boot - * doesn't have L2 cache support for now. - */ -#define MIPS_MAX_CACHE_SIZE 0x10000 + /* 16KB is the maximum size of instruction and data caches on + * MIPS 4K. + */ +#define MIPS_MAX_CACHE_SIZE 0x4000 -#define INDEX_BASE CKSEG0 - - .macro cache_op op addr - .set push - .set noreorder - .set mips3 - cache \op, 0(\addr) - .set pop - .endm /* * cacheop macro to automate cache operations @@ -119,77 +106,6 @@ #define icacheop(kva, n, cacheSize, cacheLineSize, op) \ icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op)) - .macro f_fill64 dst, offset, val - LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) -#if LONGSIZE == 4 - LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) - LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) -#endif - .endm - -/* - * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) - */ -LEAF(mips_init_icache) - blez a1, 9f - mtc0 zero, CP0_TAGLO - /* clear tag to invalidate */ - PTR_LI t0, INDEX_BASE - PTR_ADDU t1, t0, a1 -1: cache_op Index_Store_Tag_I t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b - /* fill once, so data field parity is correct */ - PTR_LI t0, INDEX_BASE -2: cache_op Fill t0 - PTR_ADDU t0, a2 - bne t0, t1, 2b - /* invalidate again - prudent but not strictly neccessary */ - PTR_LI t0, INDEX_BASE -1: cache_op Index_Store_Tag_I t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b -9: jr ra - END(mips_init_icache) - -/* - * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) - */ -LEAF(mips_init_dcache) - blez a1, 9f - mtc0 zero, CP0_TAGLO - /* clear all tags */ - PTR_LI t0, INDEX_BASE - PTR_ADDU t1, t0, a1 -1: cache_op Index_Store_Tag_D t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b - /* load from each line (in cached space) */ - PTR_LI t0, INDEX_BASE -2: LONG_L zero, 0(t0) - PTR_ADDU t0, a2 - bne t0, t1, 2b - /* clear all tags */ - PTR_LI t0, INDEX_BASE -1: cache_op Index_Store_Tag_D t0 - PTR_ADDU t0, a2 - bne t0, t1, 1b -9: jr ra - END(mips_init_dcache) - /******************************************************************************* * * mips_cache_reset - low level initialisation of the primary caches @@ -206,52 +122,88 @@ LEAF(mips_init_dcache) * RETURNS: N/A * */ -NESTED(mips_cache_reset, 0, ra) - move RA, ra + .globl mips_cache_reset + .ent mips_cache_reset +mips_cache_reset: + li t2, CFG_ICACHE_SIZE li t3, CFG_DCACHE_SIZE li t4, CFG_CACHELINE_SIZE move t5, t4 + li v0, MIPS_MAX_CACHE_SIZE - /* - * Now clear that much memory starting from zero. - */ - PTR_LI a0, CKSEG1 - PTR_ADDU a1, a0, v0 -2: PTR_ADDIU a0, 64 - f_fill64 a0, -64, zero - bne a0, a1, 2b - - /* - * The caches are probably in an indeterminate state, - * so we force good parity into them by doing an - * invalidate, load/fill, invalidate for each line. + /* Now clear that much memory starting from zero. */ - /* - * Assume bottom of RAM will generate good parity for the cache. + li a0, KSEG1 + addu a1, a0, v0 + +2: sw zero, 0(a0) + sw zero, 4(a0) + sw zero, 8(a0) + sw zero, 12(a0) + sw zero, 16(a0) + sw zero, 20(a0) + sw zero, 24(a0) + sw zero, 28(a0) + addu a0, 32 + bltu a0, a1, 2b + + /* Set invalid tag. */ - /* - * Initialize the I-cache first, - */ - move a1, t2 - move a2, t4 - PTR_LA t7, mips_init_icache - jalr t7 + mtc0 zero, CP0_TAGLO - /* - * then initialize D-cache. - */ - move a1, t3 - move a2, t5 - PTR_LA t7, mips_init_dcache - jalr t7 + /* + * The caches are probably in an indeterminate state, + * so we force good parity into them by doing an + * invalidate, load/fill, invalidate for each line. + */ + + /* Assume bottom of RAM will generate good parity for the cache. + */ + + li a0, K0BASE + move a2, t2 # icacheSize + move a3, t4 # icacheLineSize + move a1, a2 + icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) + + /* To support Orion/R4600, we initialise the data cache in 3 passes. + */ + + /* 1: initialise dcache tags. + */ + + li a0, K0BASE + move a2, t3 # dcacheSize + move a3, t5 # dcacheLineSize + move a1, a2 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + + /* 2: fill dcache. + */ + + li a0, K0BASE + move a2, t3 # dcacheSize + move a3, t5 # dcacheLineSize + move a1, a2 + icacheopn(a0,a1,a2,a3,1lw,(dummy)) + + /* 3: clear dcache tags. + */ + + li a0, K0BASE + move a2, t3 # dcacheSize + move a3, t5 # dcacheLineSize + move a1, a2 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + + j ra + .end mips_cache_reset - jr RA - END(mips_cache_reset) /******************************************************************************* * @@ -260,15 +212,15 @@ NESTED(mips_cache_reset, 0, ra) * RETURNS: 0 - cache disabled; 1 - cache enabled * */ -LEAF(dcache_status) - mfc0 t0, CP0_CONFIG - li t1, CONF_CM_UNCACHED - andi t0, t0, CONF_CM_CMASK - move v0, zero - beq t0, t1, 2f - li v0, 1 -2: jr ra - END(dcache_status) + .globl dcache_status + .ent dcache_status +dcache_status: + + mfc0 v0, CP0_CONFIG + andi v0, v0, 1 + j ra + + .end dcache_status /******************************************************************************* * @@ -277,32 +229,20 @@ LEAF(dcache_status) * RETURNS: N/A * */ -LEAF(dcache_disable) + .globl dcache_disable + .ent dcache_disable +dcache_disable: + mfc0 t0, CP0_CONFIG li t1, -8 and t0, t0, t1 ori t0, t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG - jr ra - END(dcache_disable) + mtc0 t0, CP0_CONFIG + j ra + + .end dcache_disable -/******************************************************************************* -* -* dcache_enable - enable cache -* -* RETURNS: N/A -* -*/ -LEAF(dcache_enable) - mfc0 t0, CP0_CONFIG - ori t0, CONF_CM_CMASK - xori t0, CONF_CM_CMASK - ori t0, CONF_CM_CACHABLE_NONCOHERENT - mtc0 t0, CP0_CONFIG - jr ra - END(dcache_enable) -#ifdef CFG_INIT_RAM_LOCK_MIPS /******************************************************************************* * * mips_cache_lock - lock RAM area pointed to by a0 in cache. @@ -318,14 +258,12 @@ LEAF(dcache_enable) .globl mips_cache_lock .ent mips_cache_lock mips_cache_lock: - li a1, CKSEG0 - CACHE_LOCK_SIZE + li a1, K0BASE - CACHE_LOCK_SIZE addu a0, a1 li a2, CACHE_LOCK_SIZE li a3, CFG_CACHELINE_SIZE move a1, a2 icacheop(a0,a1,a2,a3,0x1d) - jr ra - + j ra .end mips_cache_lock -#endif /* CFG_INIT_RAM_LOCK_MIPS */ diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk index a173c5480..b29986e26 100644 --- a/cpu/mips/config.mk +++ b/cpu/mips/config.mk @@ -20,8 +20,9 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) -MIPSFLAGS:=$(shell \ +v=$(shell \ +$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}') +MIPSFLAGS=$(shell \ if [ "$v" -lt "14" ]; then \ echo "-mcpu=4kc"; \ else \ @@ -34,6 +35,6 @@ else ENDIANNESS = -EB endif -MIPSFLAGS += $(ENDIANNESS) +MIPSFLAGS += $(ENDIANNESS) -mabicalls PLATFORM_CPPFLAGS += $(MIPSFLAGS) diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index 0f58d25b8..f48675e99 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -23,53 +23,32 @@ #include #include +#include #include -#include -#include - -#define cache_op(op,addr) \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set pop \n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - -void __attribute__((weak)) _machine_restart(void) -{ -} int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - _machine_restart(); +#if defined(CONFIG_INCA_IP) + *INCA_IP_WDT_RST_REQ = 0x3f; +#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229) + void (*f)(void) = (void *) 0xbfc00000; + f(); +#endif fprintf(stderr, "*** reset failed ***\n"); return 0; } -void flush_cache(ulong start_addr, ulong size) +void flush_cache (ulong start_addr, ulong size) { - unsigned long lsize = CFG_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); - while (1) { - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Invalidate_I, addr); - if (addr == aend) - break; - addr += lsize; - } } -void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) -{ - write_c0_entrylo0(low0); - write_c0_pagemask(pagemask); - write_c0_entrylo1(low1); - write_c0_entryhi(hi); - write_c0_index(index); +void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){ + write_32bit_cp0_register(CP0_ENTRYLO0, low0); + write_32bit_cp0_register(CP0_PAGEMASK, pagemask); + write_32bit_cp0_register(CP0_ENTRYLO1, low1); + write_32bit_cp0_register(CP0_ENTRYHI, hi); + write_32bit_cp0_register(CP0_INDEX, index); tlb_write_indexed(); } diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S index 3ade3cd6f..71adaa19d 100644 --- a/cpu/mips/incaip_wdt.S +++ b/cpu/mips/incaip_wdt.S @@ -24,6 +24,7 @@ #include +#include #include @@ -50,7 +51,7 @@ disable_incaip_wdt: and t3, 0xFFFFFF01 or t3, t2 - or t3, 0xF0 + or t3, 0xF0 sw t3, WD_CON0(t0) /* write password */ @@ -67,5 +68,5 @@ disable_incaip_wdt: li t1, WD_WRITE_ENDINIT sw t1, WD_CON0(t0) /* end command */ - jr ra + j ra nop diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 09e4aab25..e91e2137d 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -22,33 +22,12 @@ * MA 02111-1307 USA */ + #include +#include #include #include - /* - * For the moment disable interrupts, mark the kernel mode and - * set ST0_KX so that the CPU does not spit fire when using - * 64-bit addresses. - */ - .macro setup_c0_status set clr - .set push - mfc0 t0, CP0_STATUS - or t0, ST0_CU0 | \set | 0x1f | \clr - xor t0, 0x1f | \clr - mtc0 t0, CP0_STATUS - .set noreorder - sll zero, 3 # ehb - .set pop - .endm - - .macro setup_c0_status_reset -#ifdef CONFIG_64BIT - setup_c0_status ST0_KX 0 -#else - setup_c0_status 0 0 -#endif - .endm #define RVECENT(f,n) \ b f; nop @@ -213,7 +192,7 @@ _start: .word 0x00000000 .word 0x03e00008 .word 0x00000000 - .word 0x00000000 + .word 0x00000000 /* 0xbfc00428 */ .word 0xdc870000 .word 0xfca70000 @@ -224,7 +203,7 @@ _start: .word 0x00000000 .word 0x03e00008 .word 0x00000000 - .word 0x00000000 + .word 0x00000000 #endif /* CONFIG_PURPLE */ .align 4 reset: @@ -234,10 +213,18 @@ reset: mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI - /* WP(Watch Pending), SW0/1 should be cleared. */ - mtc0 zero, CP0_CAUSE + /* STATUS register */ +#ifdef CONFIG_TB0229 + li k0, ST0_CU0 +#else + mfc0 k0, CP0_STATUS +#endif + li k1, ~ST0_IE + and k0, k1 + mtc0 k0, CP0_STATUS - setup_c0_status_reset + /* CAUSE register */ + mtc0 zero, CP0_CAUSE /* Init Timer */ mtc0 zero, CP0_COUNT @@ -247,24 +234,34 @@ reset: li t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG - /* Initialize $gp. - */ - bal 1f + /* Initialize GOT pointer. + */ + bal 1f nop - .word _gp -1: - lw gp, 0(ra) + .word _GLOBAL_OFFSET_TABLE_ + 1: + move gp, ra + lw t1, 0(ra) + move gp, t1 + +#ifdef CONFIG_INCA_IP + /* Disable INCA-IP Watchdog. + */ + la t9, disable_incaip_wdt + jalr t9 + nop +#endif /* Initialize any external memory. */ - la t9, lowlevel_init - jalr t9 + la t9, lowlevel_init + jalr t9 nop /* Initialize caches... */ - la t9, mips_cache_reset - jalr t9 + la t9, mips_cache_reset + jalr t9 nop /* ... and enable them. @@ -272,22 +269,22 @@ reset: li t0, CONF_CM_CACHABLE_NONCOHERENT mtc0 t0, CP0_CONFIG + /* Set up temporary stack. */ -#ifdef CFG_INIT_RAM_LOCK_MIPS li a0, CFG_INIT_SP_OFFSET - la t9, mips_cache_lock - jalr t9 + la t9, mips_cache_lock + jalr t9 nop -#endif li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET la sp, 0(t0) la t9, board_init_f - jr t9 + j t9 nop + /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -301,7 +298,7 @@ reset: .globl relocate_code .ent relocate_code relocate_code: - move sp, a0 /* Set new stack pointer */ + move sp, a0 /* Set new stack pointer */ li t0, CFG_MONITOR_BASE la t3, in_ram @@ -309,14 +306,14 @@ relocate_code: move t1, a2 /* - * Fix $gp: + * Fix GOT pointer: * - * New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address */ move t6, gp sub gp, CFG_MONITOR_BASE - add gp, a2 /* gp now adjusted */ - sub t6, gp, t6 /* t6 <-- relocation offset */ + add gp, a2 /* gp now adjusted */ + sub t6, gp, t6 /* t6 <-- relocation offset */ /* * t0 = source address @@ -332,7 +329,7 @@ relocate_code: sw t3, 0(t1) addu t0, 4 ble t0, t2, 1b - addu t1, 4 /* delay slot */ + addu t1, 4 /* delay slot */ #endif /* If caches were enabled, we would have to flush them here. @@ -341,28 +338,18 @@ relocate_code: /* Jump to where we've relocated ourselves. */ addi t0, a2, in_ram - _start - jr t0 + j t0 nop - .word _gp - .word _GLOBAL_OFFSET_TABLE_ .word uboot_end_data .word uboot_end .word num_got_entries in_ram: - /* - * Now we want to update GOT. - * - * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object - * generated by GNU ld. Skip these reserved entries from relocation. + /* Now we want to update GOT. */ lw t3, -4(t0) /* t3 <-- num_got_entries */ - lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */ - lw t5, -20(t0) /* t5 <-- _gp */ - sub t4, t5 /* compute offset*/ - add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */ - addi t4, t4, 8 /* Skipping first two entries. */ + addi t4, gp, 8 /* Skipping first two entries. */ li t2, 2 1: lw t1, 0(t4) @@ -382,22 +369,22 @@ in_ram: add t2, t6 sub t1, 4 -1: - addi t1, 4 +1: addi t1, 4 bltl t1, t2, 1b sw zero, 0(t1) /* delay slot */ move a0, a1 la t9, board_init_r - jr t9 + j t9 move a1, a2 /* delay slot */ .end relocate_code + /* Exception handlers. */ romReserved: - b romReserved + b romReserved romExcHandle: - b romExcHandle + b romExcHandle diff --git a/cpu/mpc5xx/Makefile b/cpu/mpc5xx/Makefile index 8aab0189d..b787b6141 100644 --- a/cpu/mpc5xx/Makefile +++ b/cpu/mpc5xx/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2003 # Martin Winistoerfer, martinwinistoerfer@gmx.ch. # @@ -35,25 +32,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a -START = start.o -COBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o +START = start.S +OBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o spi.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk index 157ddc549..5b26a76b3 100644 --- a/cpu/mpc5xx/config.mk +++ b/cpu/mpc5xx/config.mk @@ -28,9 +28,6 @@ # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc5xx/u-boot.lds +PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float diff --git a/cpu/mpc5xx/cpu_init.c b/cpu/mpc5xx/cpu_init.c index 5bbb7986b..f4cd24bf7 100644 --- a/cpu/mpc5xx/cpu_init.c +++ b/cpu/mpc5xx/cpu_init.c @@ -23,7 +23,7 @@ * File: cpu_init.c * * Discription: Contains initialisation functions to setup - * the cpu properly + * the cpu properly * */ @@ -118,6 +118,6 @@ void cpu_init_f (volatile immap_t * immr) */ int cpu_init_r (void) { - /* Nothing to do at the moment */ + /* Nothing to do at the moment */ return (0); } diff --git a/cpu/mpc5xx/interrupts.c b/cpu/mpc5xx/interrupts.c index a4f47c74b..7f6e1363e 100644 --- a/cpu/mpc5xx/interrupts.c +++ b/cpu/mpc5xx/interrupts.c @@ -178,7 +178,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) return; } -#if defined(CONFIG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) /******************************************************************************* * * irqinfo - print information about IRQs @@ -204,4 +204,4 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/mpc5xx/serial.c b/cpu/mpc5xx/serial.c index 39f57a121..ac5556f05 100644 --- a/cpu/mpc5xx/serial.c +++ b/cpu/mpc5xx/serial.c @@ -24,8 +24,8 @@ * File: serial.c * * Discription: Serial interface driver for SCI1 and SCI2. - * Since this code will be called from ROM use - * only non-static local variables. + * Since this code will be called from ROM use + * only non-static local variables. * */ diff --git a/cpu/mpc5xx/speed.c b/cpu/mpc5xx/speed.c index 7b7c5b961..6a1fa155e 100644 --- a/cpu/mpc5xx/speed.c +++ b/cpu/mpc5xx/speed.c @@ -49,8 +49,8 @@ int get_clocks (void) if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) { gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1)); } else { - gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK)); - } + gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK)); + } #else /* CONFIG_5xx_GCLK_FREQ */ gd->bus_clk = CONFIG_5xx_GCLK_FREQ; diff --git a/cpu/mpc5xx/spi.c b/cpu/mpc5xx/spi.c index 3c187bee5..81c9ddbd4 100644 --- a/cpu/mpc5xx/spi.c +++ b/cpu/mpc5xx/spi.c @@ -208,9 +208,9 @@ void spi_init_f (void) * Setup RAM */ for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; } return; } @@ -238,9 +238,9 @@ ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len) immr = (immap_t *) CFG_IMMR; qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; } qsmcm->qsmcm_tranram[0] = SPI_EEPROM_WREN; /* write enable */ spi_xfer(1); @@ -312,9 +312,9 @@ ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len) qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm; for(i=0;i<32;i++) { - qsmcm->qsmcm_recram[i]=0x0000; - qsmcm->qsmcm_tranram[i]=0x0000; - qsmcm->qsmcm_comdram[i]=0x00; + qsmcm->qsmcm_recram[i]=0x0000; + qsmcm->qsmcm_tranram[i]=0x0000; + qsmcm->qsmcm_comdram[i]=0x00; } i=0; qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */ diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 0637003ce..087435e5b 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -155,7 +155,7 @@ in_flash: /* Initialize some SPRs that are hard to access from C */ /*----------------------------------------------------------------------*/ - lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */ + lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */ lis r2, CFG_INIT_SP_ADDR@h ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */ /* Note: R0 is still 0 here */ @@ -210,7 +210,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -228,7 +228,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc5xx/traps.c b/cpu/mpc5xx/traps.c index 78c820ae7..14fd59e4f 100644 --- a/cpu/mpc5xx/traps.c +++ b/cpu/mpc5xx/traps.c @@ -36,11 +36,11 @@ #include #include -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -131,7 +131,7 @@ void MachineCheckException(struct pt_regs *regs) return; } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -165,7 +165,7 @@ void MachineCheckException(struct pt_regs *regs) */ void AlignmentException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -179,7 +179,7 @@ void AlignmentException(struct pt_regs *regs) */ void ProgramCheckException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -193,7 +193,7 @@ void ProgramCheckException(struct pt_regs *regs) */ void SoftEmuException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -208,7 +208,7 @@ void SoftEmuException(struct pt_regs *regs) */ void UnknownException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -223,8 +223,8 @@ void UnknownException(struct pt_regs *regs) void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); - show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); + show_regs(regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc5xxx/Makefile b/cpu/mpc5xxx/Makefile index 312b0bfc6..a97b62517 100644 --- a/cpu/mpc5xxx/Makefile +++ b/cpu/mpc5xxx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,27 +23,23 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -SOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o -COBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \ - loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o usb.o +ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o +OBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \ + loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(ASOBJS) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(ASOBJS) $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/mpc5xxx/config.mk b/cpu/mpc5xxx/config.mk index b0ce2ee9e..ecd94e9b3 100644 --- a/cpu/mpc5xxx/config.mk +++ b/cpu/mpc5xxx/config.mk @@ -23,8 +23,5 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \ +PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc5xxx/u-boot.lds diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index ace16535f..6b6f8282c 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -29,15 +29,8 @@ #include #include #include -#include #include -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#include -#endif - DECLARE_GLOBAL_DATA_PTR; int checkcpu (void) @@ -56,16 +49,12 @@ int checkcpu (void) #else svr = get_svr(); pvr = get_pvr(); - - switch (pvr) { - case PVR_5200: - printf("MPC5200"); - break; - case PVR_5200B: - printf("MPC5200B"); + switch (SVR_VER (svr)) { + case SVR_MPC5200: + printf ("MPC5200"); break; default: - printf("Unknown MPC5xxx"); + printf ("MPC52?? (SVR %08x)", svr); break; } @@ -113,25 +102,3 @@ unsigned long get_tbclk (void) } /* ------------------------------------------------------------------------- */ - -#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) -void ft_cpu_setup(void *blob, bd_t *bd) -{ - int div = in_8((void*)CFG_MBAR + 0x204) & 0x0020 ? 8 : 4; - char * cpu_path = "/cpus/" OF_CPU; -#ifdef CONFIG_MPC5xxx_FEC - char * eth_path = "/" OF_SOC "/ethernet@3000"; -#endif - - do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); - do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1); - do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency", - bd->bi_busfreq*div, 1); -#ifdef CONFIG_MPC5xxx_FEC - do_fixup_by_path(blob, eth_path, "mac-address", bd->bi_enetaddr, 6, 0); - do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0); -#endif -} -#endif diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c index bc6201ec0..b7e00b3e2 100644 --- a/cpu/mpc5xxx/cpu_init.c +++ b/cpu/mpc5xxx/cpu_init.c @@ -123,7 +123,7 @@ void cpu_init_f (void) #endif #if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE) - *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START); + *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START); *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE); addecr |= (1 << 27); #endif @@ -156,21 +156,21 @@ void cpu_init_f (void) *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15); *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d; -# if defined(CFG_IPBCLK_EQUALS_XLBCLK) +# if defined(CFG_IPBSPEED_133) /* Motorola reports IPB should better run at 133 MHz. */ *(vu_long *)MPC5XXX_ADDECR |= 1; /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ addecr = *(vu_long *)MPC5XXX_CDM_CFG; addecr &= ~0x103; -# if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2) +# if defined(CFG_PCISPEED_66) /* pci_clk_sel = 0x01 -> IPB_CLK/2 */ addecr |= 0x01; # else /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ addecr |= 0x02; -# endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */ +# endif /* CFG_PCISPEED_66 */ *(vu_long *)MPC5XXX_CDM_CFG = addecr; -# endif /* CFG_IPBCLK_EQUALS_XLBCLK */ +# endif /* CFG_IPBSPEED_133 */ /* Configure the XLB Arbiter */ *(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff; *(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111; @@ -198,7 +198,7 @@ int cpu_init_r (void) /* route critical ints to normal ints */ *(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001; -#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) /* load FEC microcode */ loadtask(0, 2); #endif diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 82640ab77..19737ce86 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -18,10 +18,10 @@ DECLARE_GLOBAL_DATA_PTR; /* #define DEBUG 0x28 */ -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_MPC5xxx_FEC) -#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -288,13 +288,13 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ - fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ + fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */ } /* * Set Opcode/Pause Duration Register */ - fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */ + fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */ /* * Set Rx FIFO alarm and granularity value @@ -376,7 +376,7 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis) #if (DEBUG & 0x2) if (fec->xcv_type != SEVENWIRE) - mpc5xxx_fec_phydump (dev->name); + mpc5xxx_fec_phydump (); #endif /* @@ -428,13 +428,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) */ fec->eth->imask = 0x00000000; -/* - * In original Promess-provided code PHY initialization is disabled with the - * following comment: "Phy initialization is DISABLED for now. There was a - * problem with running 100 Mbps on PRO board". Thus we temporarily disable - * PHY initialization for the Motion-PRO board, until a proper fix is found. - */ - if (fec->xcv_type != SEVENWIRE) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock @@ -474,10 +467,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis) miiphy_write(dev->name, phyAddr, 0x0, 0x8000); udelay(1000); -#if defined(CONFIG_UC101) - /* Set the LED configuration Register for the UC101 Board */ - miiphy_write(dev->name, phyAddr, 0x14, 0x4122); -#endif if (fec->xcv_type == MII10) { /* * Force 10Base-T, FDX operation @@ -586,7 +575,7 @@ static void mpc5xxx_fec_halt(struct eth_device *dev) #if (DEBUG & 0x2) if (fec->xcv_type != SEVENWIRE) - mpc5xxx_fec_phydump (dev->name); + mpc5xxx_fec_phydump (); #endif /* @@ -884,26 +873,16 @@ int mpc5xxx_fec_initialize(bd_t * bis) fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec)); dev = (struct eth_device *)malloc(sizeof(*dev)); - memset(dev, 0, sizeof *dev); + memset(dev, 0, sizeof *dev); fec->eth = (ethernet_regs *)MPC5XXX_FEC; fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); -#if defined(CONFIG_CANMB) || \ - defined(CONFIG_CM5200) || \ - defined(CONFIG_HMI1001) || \ - defined(CONFIG_ICECUBE) || \ - defined(CONFIG_INKA4X0) || \ - defined(CONFIG_JUPITER) || \ - defined(CONFIG_MCC200) || \ - defined(CONFIG_MOTIONPRO) || \ - defined(CONFIG_O2DNT) || \ - defined(CONFIG_PM520) || \ - defined(CONFIG_TOP5200) || \ - defined(CONFIG_TQM5200) || \ - defined(CONFIG_UC101) || \ - defined(CONFIG_V38B) || \ - defined(CONFIG_MUNICES) +#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \ + defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \ + defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \ + defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \ + defined(CONFIG_TQM5200) # ifndef CONFIG_FEC_10MBIT fec->xcv_type = MII100; # else @@ -925,7 +904,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) sprintf(dev->name, "FEC ETHERNET"); eth_register(dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register (dev->name, fec5xxx_miiphy_read, fec5xxx_miiphy_write); #endif diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S index a07c77699..1d83fe26d 100644 --- a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S +++ b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S @@ -23,7 +23,7 @@ scEthernetRecv_Entry: /* Task 0 */ .long 0x00000000 .long 0x00000000 .long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long CFG_MBAR +.long 0xf0000000 .globl scEthernetXmit_Entry scEthernetXmit_Entry: /* Task 1 */ .long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ @@ -33,7 +33,7 @@ scEthernetXmit_Entry: /* Task 1 */ .long 0x00000000 .long 0x00000000 .long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long CFG_MBAR +.long 0xf0000000 .globl scEthernetRecv_TDT @@ -151,7 +151,7 @@ scEthernetRecv_VarTab: /* Task 0 Variable Table */ .long 0x00000000 /* var[6] */ .long 0x00000000 /* var[7] */ .long 0x00000000 /* var[8] */ -.long (CFG_MBAR + 0x8800) /* var[9] */ +.long 0xf0008800 /* var[9] */ .long 0x00000008 /* var[10] */ .long 0x0000000c /* var[11] */ .long 0x80000000 /* var[12] */ @@ -190,7 +190,7 @@ scEthernetXmit_VarTab: /* Task 1 Variable Table */ .long 0x00000000 /* var[8] */ .long 0x00000000 /* var[9] */ .long 0x00000000 /* var[10] */ -.long (CFG_MBAR + 0x8800) /* var[11] */ +.long 0xf0008800 /* var[11] */ .long 0x00000000 /* var[12] */ .long 0x80000000 /* var[13] */ .long 0x10000000 /* var[14] */ diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c index df5b4acd0..29b99f6b1 100644 --- a/cpu/mpc5xxx/ide.c +++ b/cpu/mpc5xxx/ide.c @@ -24,7 +24,7 @@ */ #include -#if defined(CONFIG_CMD_IDE) +#ifdef CFG_CMD_IDE #include DECLARE_GLOBAL_DATA_PTR; @@ -54,19 +54,11 @@ int ide_preinit (void) /* All sample codes do that... */ *(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0; -#if defined(CONFIG_UC101) - /* Configure and reset host */ - *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = - MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; - udelay (10); - *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = 0; -#else /* Configure and reset host */ *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY | MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR; udelay (10); *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY; -#endif /* Disable prefetch on Commbus */ psdma->PtdCntrl |= 1; @@ -93,4 +85,4 @@ int ide_preinit (void) return (0); } -#endif +#endif /* CFG_CMD_IDE */ diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c index 8816dd1e2..7bacecd59 100644 --- a/cpu/mpc5xxx/interrupts.c +++ b/cpu/mpc5xxx/interrupts.c @@ -1,7 +1,4 @@ /* - * (C) Copyright 2006 - * Detlev Zundel, DENX Software Engineering, dzu@denx.de - * * (C) Copyright -2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -27,212 +24,18 @@ * MA 02111-1307 USA */ -/* this section was ripped out of arch/ppc/syslib/mpc52xx_pic.c in the - * Linux 2.6 source with the following copyright. - * - * Based on (well, mostly copied from) the code from the 2.4 kernel by - * Dale Farnsworth and Kent Borg. - * - * Copyright (C) 2004 Sylvain Munaut - * Copyright (C) 2003 Montavista Software, Inc +/* + * interrupts.c - just enough support for the decrementer/timer */ #include #include -#include #include -struct irq_action { - interrupt_handler_t *handler; - void *arg; - ulong count; -}; - -static struct irq_action irq_handlers[NR_IRQS]; - -static struct mpc5xxx_intr *intr; -static struct mpc5xxx_sdma *sdma; - -static void mpc5xxx_ic_disable(unsigned int irq) -{ - u32 val; - - if (irq == MPC5XXX_IRQ0) { - val = in_be32(&intr->ctrl); - val &= ~(1 << 11); - out_be32(&intr->ctrl, val); - } else if (irq < MPC5XXX_IRQ1) { - BUG(); - } else if (irq <= MPC5XXX_IRQ3) { - val = in_be32(&intr->ctrl); - val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1))); - out_be32(&intr->ctrl, val); - } else if (irq < MPC5XXX_SDMA_IRQ_BASE) { - val = in_be32(&intr->main_mask); - val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)); - out_be32(&intr->main_mask, val); - } else if (irq < MPC5XXX_PERP_IRQ_BASE) { - val = in_be32(&sdma->IntMask); - val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE); - out_be32(&sdma->IntMask, val); - } else { - val = in_be32(&intr->per_mask); - val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)); - out_be32(&intr->per_mask, val); - } -} - -static void mpc5xxx_ic_enable(unsigned int irq) -{ - u32 val; - - if (irq == MPC5XXX_IRQ0) { - val = in_be32(&intr->ctrl); - val |= 1 << 11; - out_be32(&intr->ctrl, val); - } else if (irq < MPC5XXX_IRQ1) { - BUG(); - } else if (irq <= MPC5XXX_IRQ3) { - val = in_be32(&intr->ctrl); - val |= 1 << (10 - (irq - MPC5XXX_IRQ1)); - out_be32(&intr->ctrl, val); - } else if (irq < MPC5XXX_SDMA_IRQ_BASE) { - val = in_be32(&intr->main_mask); - val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE))); - out_be32(&intr->main_mask, val); - } else if (irq < MPC5XXX_PERP_IRQ_BASE) { - val = in_be32(&sdma->IntMask); - val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE)); - out_be32(&sdma->IntMask, val); - } else { - val = in_be32(&intr->per_mask); - val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE))); - out_be32(&intr->per_mask, val); - } -} - -static void mpc5xxx_ic_ack(unsigned int irq) -{ - u32 val; - - /* - * Only some irqs are reset here, others in interrupting hardware. - */ - - switch (irq) { - case MPC5XXX_IRQ0: - val = in_be32(&intr->ctrl); - val |= 0x08000000; - out_be32(&intr->ctrl, val); - break; - case MPC5XXX_CCS_IRQ: - val = in_be32(&intr->enc_status); - val |= 0x00000400; - out_be32(&intr->enc_status, val); - break; - case MPC5XXX_IRQ1: - val = in_be32(&intr->ctrl); - val |= 0x04000000; - out_be32(&intr->ctrl, val); - break; - case MPC5XXX_IRQ2: - val = in_be32(&intr->ctrl); - val |= 0x02000000; - out_be32(&intr->ctrl, val); - break; - case MPC5XXX_IRQ3: - val = in_be32(&intr->ctrl); - val |= 0x01000000; - out_be32(&intr->ctrl, val); - break; - default: - if (irq >= MPC5XXX_SDMA_IRQ_BASE - && irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) { - out_be32(&sdma->IntPend, - 1 << (irq - MPC5XXX_SDMA_IRQ_BASE)); - } - break; - } -} - -static void mpc5xxx_ic_disable_and_ack(unsigned int irq) -{ - mpc5xxx_ic_disable(irq); - mpc5xxx_ic_ack(irq); -} - -static void mpc5xxx_ic_end(unsigned int irq) -{ - mpc5xxx_ic_enable(irq); -} - -void mpc5xxx_init_irq(void) -{ - u32 intr_ctrl; - - /* Remap the necessary zones */ - intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL); - sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA); - - /* Disable all interrupt sources. */ - out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ - out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ - out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */ - out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */ - intr_ctrl = in_be32(&intr->ctrl); - intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */ - 0x00ff0000 | /* IRQ 0-3 level sensitive low active */ - 0x00001000 | /* MEE master external enable */ - 0x00000000 | /* 0 means disable IRQ 0-3 */ - 0x00000001; /* CEb route critical normally */ - out_be32(&intr->ctrl, intr_ctrl); - - /* Zero a bunch of the priority settings. */ - out_be32(&intr->per_pri1, 0); - out_be32(&intr->per_pri2, 0); - out_be32(&intr->per_pri3, 0); - out_be32(&intr->main_pri1, 0); - out_be32(&intr->main_pri2, 0); -} - -int mpc5xxx_get_irq(struct pt_regs *regs) -{ - u32 status; - int irq = -1; - - status = in_be32(&intr->enc_status); - - if (status & 0x00000400) { /* critical */ - irq = (status >> 8) & 0x3; - if (irq == 2) /* high priority peripheral */ - goto peripheral; - irq += MPC5XXX_CRIT_IRQ_BASE; - } else if (status & 0x00200000) { /* main */ - irq = (status >> 16) & 0x1f; - if (irq == 4) /* low priority peripheral */ - goto peripheral; - irq += MPC5XXX_MAIN_IRQ_BASE; - } else if (status & 0x20000000) { /* peripheral */ - peripheral: - irq = (status >> 24) & 0x1f; - if (irq == 0) { /* bestcomm */ - status = in_be32(&sdma->IntPend); - irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1; - } else - irq += MPC5XXX_PERP_IRQ_BASE; - } - - return irq; -} - -/****************************************************************************/ - -int interrupt_init_cpu(ulong * decrementer_count) +int interrupt_init_cpu (ulong *decrementer_count) { *decrementer_count = get_tbclk() / CFG_HZ; - mpc5xxx_init_irq(); - return (0); } @@ -241,32 +44,14 @@ int interrupt_init_cpu(ulong * decrementer_count) /* * Handle external interrupts */ -void external_interrupt(struct pt_regs *regs) +void +external_interrupt(struct pt_regs *regs) { - int irq, unmask = 1; - - irq = mpc5xxx_get_irq(regs); - - mpc5xxx_ic_disable_and_ack(irq); - - enable_interrupts(); - - if (irq_handlers[irq].handler != NULL) - (*irq_handlers[irq].handler) (irq_handlers[irq].arg); - else { - printf("\nBogus External Interrupt IRQ %d\n", irq); - /* - * turn off the bogus interrupt, otherwise it - * might repeat forever - */ - unmask = 0; - } - - if (unmask) - mpc5xxx_ic_end(irq); + puts("external_interrupt (oops!)\n"); } -void timer_interrupt_cpu(struct pt_regs *regs) +void +timer_interrupt_cpu (struct pt_regs *regs) { /* nothing to do here */ return; @@ -278,69 +63,22 @@ void timer_interrupt_cpu(struct pt_regs *regs) * Install and free a interrupt handler. */ -void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg) +void +irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) { - if (irq < 0 || irq >= NR_IRQS) { - printf("irq_install_handler: bad irq number %d\n", irq); - return; - } - if (irq_handlers[irq].handler != NULL) - printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", - (ulong) handler, (ulong) irq_handlers[irq].handler); - - irq_handlers[irq].handler = handler; - irq_handlers[irq].arg = arg; - - mpc5xxx_ic_enable(irq); } -void irq_free_handler(int irq) +void +irq_free_handler(int vec) { - if (irq < 0 || irq >= NR_IRQS) { - printf("irq_free_handler: bad irq number %d\n", irq); - return; - } - mpc5xxx_ic_disable(irq); - - irq_handlers[irq].handler = NULL; - irq_handlers[irq].arg = NULL; } /****************************************************************************/ -#if defined(CONFIG_CMD_IRQ) -void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +void +do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - int irq, re_enable; - u32 intr_ctrl; - char *irq_config[] = { "level sensitive, active high", - "edge sensitive, rising active edge", - "edge sensitive, falling active edge", - "level sensitive, active low" - }; - - re_enable = disable_interrupts(); - - intr_ctrl = in_be32(&intr->ctrl); - printf("Interrupt configuration:\n"); - - for (irq = 0; irq <= 3; irq++) { - printf("IRQ%d: %s\n", irq, - irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]); - } - - puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n"); - - for (irq = 0; irq < NR_IRQS; irq++) - if (irq_handlers[irq].handler != NULL) - printf("%02d %08lx %08lx %ld\n", irq, - (ulong) irq_handlers[irq].handler, - (ulong) irq_handlers[irq].arg, - irq_handlers[irq].count); - - if (re_enable) - enable_interrupts(); + puts("IRQ related functions are unimplemented currently.\n"); } -#endif diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c index 430d63f74..6cb523d3c 100644 --- a/cpu/mpc5xxx/serial.c +++ b/cpu/mpc5xxx/serial.c @@ -165,25 +165,6 @@ void serial_putc(const char c) psc->psc_buffer_8 = c; } -#if defined(CONFIG_SERIAL_MULTI) -void serial_putc_raw_dev(unsigned long dev_base, const char c) -#else -void serial_putc_raw(const char c) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - /* Wait for last character to go. */ - while (!(psc->psc_status & PSC_SR_TXEMP)) - ; - - psc->psc_buffer_8 = c; -} - - #if defined(CONFIG_SERIAL_MULTI) void serial_puts_dev (unsigned long dev_base, const char *s) #else @@ -258,43 +239,6 @@ void serial_setbrg(void) psc->ctlr = div & 0xff; } -#if defined(CONFIG_SERIAL_MULTI) -void serial_setrts_dev (unsigned long dev_base, int s) -#else -void serial_setrts(int s) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - - if (s) { - /* Assert RTS (become LOW) */ - psc->op1 = 0x1; - } - else { - /* Negate RTS (become HIGH) */ - psc->op0 = 0x1; - } -} - -#if defined(CONFIG_SERIAL_MULTI) -int serial_getcts_dev (unsigned long dev_base) -#else -int serial_getcts(void) -#endif -{ -#if defined(CONFIG_SERIAL_MULTI) - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; -#else - volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#endif - - return (psc->ip & 0x1) ? 0 : 1; -} - #if defined(CONFIG_SERIAL_MULTI) int serial0_init(void) { diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 9b1bd48c7..3936b5551 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -208,7 +208,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -227,7 +227,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc5xxx/traps.c b/cpu/mpc5xxx/traps.c index daa1ec6b5..2ee782b9c 100644 --- a/cpu/mpc5xxx/traps.c +++ b/cpu/mpc5xxx/traps.c @@ -37,7 +37,7 @@ #include #include -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -123,7 +123,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -158,7 +158,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -170,7 +170,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -182,7 +182,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -195,7 +195,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -204,7 +204,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -214,7 +214,7 @@ DebugException(struct pt_regs *regs) printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc5xxx/usb_ohci.c b/cpu/mpc5xxx/usb_ohci.c index 2ad12b2a2..c774da36d 100644 --- a/cpu/mpc5xxx/usb_ohci.c +++ b/cpu/mpc5xxx/usb_ohci.c @@ -56,8 +56,8 @@ #define OHCI_CONTROL_INIT \ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE -#define readl(a) (*((volatile u32 *)(a))) -#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) +#define readl(a) (*((vu_long *)(a))) +#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) diff --git a/cpu/mpc8220/Makefile b/cpu/mpc8220/Makefile index b4fad286d..7c9b6c990 100644 --- a/cpu/mpc8220/Makefile +++ b/cpu/mpc8220/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2003-2006 +# (C) Copyright 2003 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,28 +23,24 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -SOBJS = io.o fec_dma_tasks.o -COBJS = cpu.o cpu_init.o dramSetup.o fec.o i2c.o \ +ASOBJS = io.o fec_dma_tasks.o +OBJS = cpu.o cpu_init.o dramSetup.o fec.o i2c.o \ interrupts.o loadtask.o speed.o \ traps.o uart.o pci.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(ASOBJS) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(ASOBJS) $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(ASOBJS:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/mpc8220/config.mk b/cpu/mpc8220/config.mk index 5819048d0..6fec5dfe6 100644 --- a/cpu/mpc8220/config.mk +++ b/cpu/mpc8220/config.mk @@ -23,8 +23,5 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \ +PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc8220/u-boot.lds diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c index 0daac5bbd..3cf5f66a1 100644 --- a/cpu/mpc8220/cpu_init.c +++ b/cpu/mpc8220/cpu_init.c @@ -128,7 +128,7 @@ int cpu_init_r (void) /* route critical ints to normal ints */ *(vu_long *) 0xf0000710 |= 0x00000001; -#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC8220_FEC) +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC8220_FEC) /* load FEC microcode */ loadtask (0, 2); #endif diff --git a/cpu/mpc8220/fec.c b/cpu/mpc8220/fec.c index 992e0ffbc..1201e794d 100644 --- a/cpu/mpc8220/fec.c +++ b/cpu/mpc8220/fec.c @@ -15,10 +15,10 @@ #include "fec.h" #undef DEBUG -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ defined(CONFIG_MPC8220_FEC) -#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -847,7 +847,7 @@ int mpc8220_fec_initialize (bd_t * bis) sprintf (dev->name, "FEC ETHERNET"); eth_register (dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register (dev->name, fec8220_miiphy_read, fec8220_miiphy_write); #endif diff --git a/cpu/mpc8220/pci.c b/cpu/mpc8220/pci.c index 4ef214e54..ca4a04d21 100644 --- a/cpu/mpc8220/pci.c +++ b/cpu/mpc8220/pci.c @@ -170,7 +170,7 @@ pci_mpc8220_init(struct pci_controller *hose) hose->region_count = 3; hose->cfg_addr = &(xcpci->cfg_adr); - hose->cfg_data = (volatile unsigned char *)CONFIG_PCI_CFG_BUS; + hose->cfg_data = CONFIG_PCI_CFG_BUS; pci_set_ops(hose, mpc8220_pci_read_config_byte, diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index b5145ca03..52332023e 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -169,7 +169,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -188,7 +188,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc8220/traps.c b/cpu/mpc8220/traps.c index 89cca1d22..cdee2be78 100644 --- a/cpu/mpc8220/traps.c +++ b/cpu/mpc8220/traps.c @@ -37,7 +37,7 @@ #include #include -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) int (*debugger_exception_handler) (struct pt_regs *) = 0; #endif @@ -118,7 +118,7 @@ void MachineCheckException (struct pt_regs *regs) regs->nip = fixup; return; } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -152,7 +152,7 @@ void MachineCheckException (struct pt_regs *regs) void AlignmentException (struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -164,7 +164,7 @@ void AlignmentException (struct pt_regs *regs) void ProgramCheckException (struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -176,7 +176,7 @@ void ProgramCheckException (struct pt_regs *regs) void SoftEmuException (struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -189,7 +189,7 @@ void SoftEmuException (struct pt_regs *regs) void UnknownException (struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler) (regs)) return; @@ -199,7 +199,7 @@ void UnknownException (struct pt_regs *regs) _exception (0, regs); } -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) extern void do_bedbug_breakpoint (struct pt_regs *); #endif @@ -208,7 +208,7 @@ void DebugException (struct pt_regs *regs) printf ("Debugger trap at @ %lx\n", regs->nip); show_regs (regs); -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) do_bedbug_breakpoint (regs); #endif } diff --git a/cpu/mpc824x/Makefile b/cpu/mpc824x/Makefile index f249dd7c3..df0d64e41 100644 --- a/cpu/mpc824x/Makefile +++ b/cpu/mpc824x/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,35 +22,26 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)drivers/epic) -$(shell mkdir -p $(obj)drivers/i2c) -endif -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a -START = start.o -COBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \ - drivers/epic/epic1.o drivers/i2c/i2c.o pci.o -COBJS_LN = bedbug_603e.o +START = start.S +OBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \ + drivers/epic/epic1.o drivers/i2c/i2c.o pci.o bedbug_603e.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) -$(obj)bedbug_603e.c: - ln -s $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c +bedbug_603e.c: + ln -s ../mpc8260/bedbug_603e.c bedbug_603e.c ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk index 1bb0487bd..dac61d8d3 100644 --- a/cpu/mpc824x/config.mk +++ b/cpu/mpc824x/config.mk @@ -23,7 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc824x/u-boot.lds +PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float diff --git a/cpu/mpc824x/drivers/dma/Makefile b/cpu/mpc824x/drivers/dma/Makefile new file mode 100644 index 000000000..59e2fac86 --- /dev/null +++ b/cpu/mpc824x/drivers/dma/Makefile @@ -0,0 +1,83 @@ +########################################################################## +# +# Copyright Motorola, Inc. 1997 +# ALL RIGHTS RESERVED +# +# You are hereby granted a copyright license to use, modify, and +# distribute the SOFTWARE so long as this entire notice is retained +# without alteration in any modified and/or redistributed versions, +# and that such modified versions are clearly identified as such. +# No licenses are granted by implication, estoppel or otherwise under +# any patents or trademarks of Motorola, Inc. +# +# The SOFTWARE is provided on an "AS IS" basis and without warranty. +# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS +# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED +# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR +# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH +# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS +# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. +# +# To the maximum extent permitted by applicable law, IN NO EVENT SHALL +# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF +# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR +# INABILITY TO USE THE SOFTWARE. +# +############################################################################ +TARGET = libdma.a + +DEBUG = -DDMADBG +LST = -Hanno -S +OPTIM = +CC = /risc/tools/pkgs/metaware/bin/hcppc +CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc +CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) +PREP = $(CC) $(CFLAGS) -P + +# Assembler used to build the .s files (for the board version) + +ASOPT = -big_si -c +ASDEBUG = -l -fm +AS = /risc/tools/pkgs/metaware/bin/asppc + +# Linker to bring .o files together into an executable. + +LKOPT = -Bbase=0 -q -r -Qn +LKCMD = +LINK = /risc/tools/pkgs/metaware/bin/ldppc $(LKCMD) $(LKOPT) + +# DOS Utilities + +DEL = rm +COPY = cp +LIST = ls + +OBJECTS = dma1.o dma2.o + +all: $(TARGET) + +$(TARGET): $(OBJECTS) + $(LINK) $(OBJECTS) -o $@ + +objects: dma1.o + +clean: + $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) + +.s.o: + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i +# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst + +.c.o: + $(CCobj) $< + +.c.s: + $(CCobj) $(LST) $< + +dma1.o: dma_export.h dma.h dma1.c + +dma2.o: dma.h dma2.s diff --git a/cpu/mpc824x/drivers/dma/Makefile_pc b/cpu/mpc824x/drivers/dma/Makefile_pc new file mode 100644 index 000000000..8df2a3cb7 --- /dev/null +++ b/cpu/mpc824x/drivers/dma/Makefile_pc @@ -0,0 +1,89 @@ +########################################################################## +# +# makefile_pc for use with mksnt tools drivers/dma +# +# Copyright Motorola, Inc. 1997 +# ALL RIGHTS RESERVED +# +# You are hereby granted a copyright license to use, modify, and +# distribute the SOFTWARE so long as this entire notice is retained +# without alteration in any modified and/or redistributed versions, +# and that such modified versions are clearly identified as such. +# No licenses are granted by implication, estoppel or otherwise under +# any patents or trademarks of Motorola, Inc. +# +# The SOFTWARE is provided on an "AS IS" basis and without warranty. +# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS +# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED +# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR +# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH +# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS +# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. +# +# To the maximum extent permitted by applicable law, IN NO EVENT SHALL +# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF +# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR +# INABILITY TO USE THE SOFTWARE. +# +############################################################################ +TARGET = libdma.a + +DEBUG = -DDMADBG +LST = -Hanno -S +OPTIM = +CC = m:/old_tools/tools/hcppc/bin/hcppc +CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc +CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) +PREP = $(CC) $(CFLAGS) -P + +# Assembler used to build the .s files (for the board version) + +ASOPT = -big_si -c +ASDEBUG = -l -fm +AS = m:/old_tools/tools/hcppc/bin/asppc + +# Linker to bring .o files together into an executable. + +LKOPT = -Bbase=0 -q -r -Qn +LKCMD = +LINK = m:/old_tools/tools/hcppc/bin/ldppc $(LKCMD) $(LKOPT) + +# DOS Utilities + +DEL = rm +COPY = cp +LIST = ls + +OBJECTS = dma1.o dma2.o + +all: $(TARGET) + +$(TARGET): $(OBJECTS) + $(LINK) $(OBJECTS) -o $@ + +objects: dma1.o + +clean: + $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) + +.s.o: + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i +# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst + +.c.o: + $(CCobj) $< + +.c.s: + $(CCobj) $(LST) $< + +dma1.o: dma_export.h dma.h dma1.c + $(CCobj) $< + +dma2.o: dma.h dma2.s + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i diff --git a/cpu/mpc824x/drivers/dma/README b/cpu/mpc824x/drivers/dma/README new file mode 100644 index 000000000..06f4bc08d --- /dev/null +++ b/cpu/mpc824x/drivers/dma/README @@ -0,0 +1,100 @@ +CONTENT: + + dma.h + dma1.c + dma2.s + +WHAT ARE THESE FILES: + +These files contain MPC8240 (Kahlua) DMA controller +driver routines. The driver routines are not +written for any specific operating system. +They serves the purpose of code sample, and +jump-start for using the MPC8240 DMA controller. + +For the reason of correctness of C language +syntax, these files are compiled by Metaware +C compiler and assembler. + +ENDIAN NOTATION: + +The algorithm is designed for big-endian mode, +software is responsible for byte swapping. + +USAGE: + +1. The host system that is running on MPC8240 + or using MPC8240 as I/O device shall link + the files listed here. The memory location + of driver routines shall take into account of + that driver routines need to run in supervisor + mode and they process DMA controller interrupt. + +2. The host system is responsible for configuring + the MPC8240 including Embedded Utilities Memory + Block. Since the DMA controller on MPC8240 can + be accessed by either local 603e core or the host + that MPC8240 serves as I/O processor through host + PCI configuration, it is important that the local + processor uses EUMBBAR to access its local DMA + controller while the PCI master uses I/O + processor's PCSRBAR to access the DMA controller + on I/O device. + + To qualify whether is EUMBBAR or PCSRBAR, one + additional parameter is requied from the host + system, LOCAL or REMOTE so that the base value + can be correctly interpreted. + +3. If the host system is also using the EPIC unit + on MPC8240, the system can register the + DMA_ISR with the EPIC including other + desired resources. + + If the host system does not using the EPIC unit + on MPC8240, DMA_ISR function can be called for + each desired time interval. + + In both cases, the host system is free to + provide its own interrupt service routine. + +4. To start a direct mode DMA transaction, + use DMA_Bld_Curr with the start parameter + set to 1. + + To start a chaining mode DMA transaction, + the application shall build descriptors + in memory first, next, use DMA_Bld_Desp + with the start parameter set to 1. + +5. DMA_Start function clears, then sets the CS + bit of DMA mode register. + + DMA_Halt function clears the CS bit of DMA + mode register. + + These functions can be used to start and + halt the DMA transaction. + + If the chaining descriptors has been + modified since the last time a DMA + transaction started, use DMA_Chn_Cnt + function to let DMA controller process + the modified descriptor chain without + stopping or disturbing the current DMA + transaction. + + It is the host system's responsibility of + setting up the correct DMA transfer mode + and pass the correct memory address parameters. + +6. It is the host system's responsibility of + queueing the DMA I/O request. The host + system can call the DMA_ISR with its own + desired interrupt service subroutines to + handle each individual interrupt and queued + DMA I/O requests. + +7. The DMA driver routines contains a set + of utilities, Set and Get, for host system + to query and modify the desired DMA registers. diff --git a/cpu/mpc824x/drivers/dma/dma.h b/cpu/mpc824x/drivers/dma/dma.h new file mode 100644 index 000000000..a21be74ad --- /dev/null +++ b/cpu/mpc824x/drivers/dma/dma.h @@ -0,0 +1,326 @@ +#ifndef DMA_H +#define DMA_H +/******************************************************* + * + * copyright @ Motorola 1999 + * + *******************************************************/ +#define NUM_DMA_REG 7 +#define DMA_MR_REG 0 +#define DMA_SR_REG 1 +#define DMA_CDAR_REG 2 +#define DMA_SAR_REG 3 +#define DMA_DAR_REG 4 +#define DMA_BCR_REG 5 +#define DMA_NDAR_REG 6 + +typedef enum _dmastatus +{ + DMASUCCESS = 0x1000, + DMALMERROR, + DMAPERROR, + DMACHNBUSY, + DMAEOSINT, + DMAEOCAINT, + DMAINVALID, + DMANOEVENT, +} DMAStatus; + +typedef enum _location +{ + LOCAL = 0, /* local processor accesses on board DMA, + local processor's eumbbar is required */ + REMOTE = 1, /* PCI master accesses DMA on I/O board, + I/O processor's pcsrbar is required */ +} LOCATION; + +typedef enum dma_mr_bit +{ + IRQS = 0x00080000, + PDE = 0x00040000, + DAHTS = 0x00030000, + SAHTS = 0x0000c000, + DAHE = 0x00002000, + SAHE = 0x00001000, + PRC = 0x00000c00, + EIE = 0x00000080, + EOTIE = 0x00000040, + DL = 0x00000008, + CTM = 0x00000004, + CC = 0x00000002, + CS = 0x00000001, +} DMA_MR_BIT; + +typedef enum dma_sr_bit +{ + LME = 0x00000080, + PE = 0x00000010, + CB = 0x00000004, + EOSI = 0x00000002, + EOCAI = 0x00000001, +} DMA_SR_BIT; + +/* structure for DMA Mode Register */ +typedef struct _dma_mr +{ + unsigned int reserved0 : 12; + unsigned int irqs : 1; + unsigned int pde : 1; + unsigned int dahts : 2; + unsigned int sahts : 2; + unsigned int dahe : 1; + unsigned int sahe : 1; + unsigned int prc : 2; + unsigned int reserved1 : 1; + unsigned int eie : 1; + unsigned int eotie : 1; + unsigned int reserved2 : 3; + unsigned int dl : 1; + unsigned int ctm : 1; + /* if chaining mode is enabled, any time, user can modify the + * descriptor and does not need to halt the current DMA transaction. + * Set CC bit, enable DMA to process the modified descriptors + * Hardware will clear this bit each time, DMA starts. + */ + unsigned int cc : 1; + /* cs bit has dua role, halt the current DMA transaction and + * (re)start DMA transaction. In chaining mode, if the descriptor + * needs modification, cs bit shall be used not the cc bit. + * Hardware will not set/clear this bit each time DMA transaction + * stops or starts. Software shall do it. + * + * cs bit shall not be used to halt chaining DMA transaction for + * modifying the descriptor. That is the role of CC bit. + */ + unsigned int cs : 1; +} DMA_MR; + +/* structure for DMA Status register */ +typedef struct _dma_sr +{ + unsigned int reserved0 : 24; + unsigned int lme : 1; + unsigned int reserved1 : 2; + unsigned int pe : 1; + unsigned int reserved2 : 1; + unsigned int cb : 1; + unsigned int eosi : 1; + unsigned int eocai : 1; +} DMA_SR; + +/* structure for DMA current descriptor address register */ +typedef struct _dma_cdar +{ + unsigned int cda : 27; + unsigned int snen : 1; + unsigned int eosie : 1; + unsigned int ctt : 2; + unsigned int eotd : 1; +} DMA_CDAR; + +/* structure for DMA byte count register */ +typedef struct _dma_bcr +{ + unsigned int reserved : 6; + unsigned int bcr : 26; +} DMA_BCR; + +/* structure for DMA Next Descriptor Address register */ +typedef struct _dma_ndar +{ + unsigned int nda : 27; + unsigned int ndsnen : 1; + unsigned int ndeosie: 1; + unsigned int ndctt : 2; + unsigned int eotd : 1; +} DMA_NDAR; + +/* structure for DMA current transaction info */ +typedef struct _dma_curr +{ + unsigned int src_addr; + unsigned int dest_addr; + unsigned int byte_cnt; +} DMA_CURR; + +/************************* Kernel API******************** + * Kernel APIs are used to interface with O.S. kernel. + * They are the functions required by O.S. kernel to + * provide I/O service. + ********************************************************/ + +/**************DMA Device Control Functions ********/ + +/** + * Note: + * + * In all following functions, the host (KAHLUA) processor has a + * choice of accessing on board local DMA (LOCAL), + * or DMA on a distributed KAHLUA (REMOTE). In either case, + * the caller shall pass the configured embedded utility memory + * block base address relative to the DMA. If LOCAL DMA is used, + * this parameter shall be EUMBBAR, if REMOTE is used, the + * parameter shall be the corresponding PCSRBAR. + **/ + +/************************************************************** + * function: DMA_Get_Stat + * + * description: return the content of status register of + * the given DMA channel + * if error, return DMAINVALID. Otherwise return + * DMASUCCESS. + * + **************************************************************/ +static DMAStatus DMA_Get_Stat( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_SR * ); + +/************************************************************** + * function: DMA_Get_Mode + * + * description: return the content of mode register of the + * given DMA channel + * if error, return DMAINVALID. Otherwise return DMASUCCESS. + * + **************************************************************/ +static DMAStatus DMA_Get_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR * ); + +/************************************************************** + * function: DMA_Set_Mode + * + * description: Set a new mode to a given DMA channel + * return DMASUCCESS if success, otherwise return DMACHNINVALID + * + * note: It is not a good idea of changing the DMA mode during + * the middle of a transaction. + **************************************************************/ +static DMAStatus DMA_Set_Mode( LOCATION, unsigned int eumbbar, unsigned int channel, DMA_MR mode ); + +/************************************************************* + * function: DMA_ISR + * + * description: DMA interrupt service routine + * return DMAStatus based on the status + * + *************************************************************/ +static DMAStatus DMA_ISR( unsigned int eumbbar, + unsigned int channel, + DMAStatus (*lme_func)( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*pe_func) ( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*eosi_func)( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*eocai_func)(unsigned int, unsigned int, DMAStatus )); + +static DMAStatus dma_error_func( unsigned int, unsigned int, DMAStatus ); + +/********************* DMA I/O function ********************/ + +/************************************************************ + * function: DMA_Start + * + * description: start a given DMA channel transaction + * return DMASUCCESS if success, otherwise return DMACHNINVALID + * + * note: this function will clear DMA_MR(CC) first, then + * set DMA_MR(CC). + ***********************************************************/ +static DMAStatus DMA_Start( LOCATION, unsigned int eumbbar,unsigned int channel ); + +/*********************************************************** + * function: DMA_Halt + * + * description: halt the current dma transaction on the specified + * channel. + * return DMASUCCESS if success, otherwise return DMACHNINVALID + * + * note: if the specified DMA channel is idle, nothing happens + *************************************************************/ +static DMAStatus DMA_Halt( LOCATION, unsigned int eumbbar,unsigned int channel ); + +/************************************************************* + * function: DMA_Chn_Cnt + * + * description: set the DMA_MR(CC) bit for a given channel + * that is in chaining mode. + * return DMASUCCESS if successfule, otherwise return DMACHNINVALID + * + * note: if the given channel is not in chaining mode, nothing + * happen. + * + *************************************************************/ +static DMAStatus DMA_Chn_Cnt( LOCATION, unsigned int eumbbar,unsigned int channel ); + +/*********************** App. API *************************** + * App. API are the APIs Kernel provides for the application + * level program + ************************************************************/ +/************************************************************** + * function: DMA_Bld_Curr + * + * description: set current src, dest, byte count registers + * according to the desp for a given channel + * + * if the given channel is busy, no change made, + * return DMACHNBUSY. + * + * otherwise return DMASUCCESS. + * + * note: + **************************************************************/ +static DMAStatus DMA_Bld_Curr( LOCATION, + unsigned int eumbbar, + unsigned int channel, + DMA_CURR desp ); + +/************************************************************** + * function: DMA_Poke_Curr + * + * description: poke the current src, dest, byte count registers + * for a given channel. + * + * return DMASUCCESS if no error otherwise return DMACHNERROR + * + * note: Due to the undeterministic parallelism, in chaining + * mode, the value returned by this function shall + * be taken as reference when the query is made rather + * than the absolute snapshot when the value is returned. + **************************************************************/ +static DMAStatus DMA_Poke_Curr( LOCATION, + unsigned int eumbbar, + unsigned int channel, + DMA_CURR* desp ); + +/************************************************************** + * function: DMA_Bld_Desp + * + * description: set current descriptor address register + * according to the desp for a given channel + * + * if the given channel is busy return DMACHNBUSY + * and no change made, otherwise return DMASUCCESS. + * + * note: + **************************************************************/ +static DMAStatus DMA_Bld_Desp( LOCATION host, + unsigned int eumbbar, + unsigned int channel, + DMA_CDAR desp ); + +/************************************************************** + * function: DMA_Poke_Desp + * + * description: poke the current descriptor address register + * for a given channel + * + * return DMASUCCESS if no error otherwise return + * DMAINVALID + * + * note: Due to the undeterministic parallellism of DMA operation, + * the value returned by this function shall be taken as + * the most recently used descriptor when the last time + * DMA starts a chaining mode operation. + **************************************************************/ +static DMAStatus DMA_Poke_Desp( LOCATION, + unsigned int eumbbar, + unsigned int channel, + DMA_CDAR *desp ); + +#endif diff --git a/cpu/mpc824x/drivers/dma/dma1.c b/cpu/mpc824x/drivers/dma/dma1.c new file mode 100644 index 000000000..9c852670e --- /dev/null +++ b/cpu/mpc824x/drivers/dma/dma1.c @@ -0,0 +1,801 @@ +/************************************************************ + * + * copyright @ Motorola, 1999 + * + * App. API + * + * App. API are the APIs Kernel provides for the application + * level program + * + ************************************************************/ +#include "dma_export.h" +#include "dma.h" + +/* Define a macro to use an optional application-layer print function, if + * one was passed to the library during initialization. If there was no + * function pointer passed, this protects against referencing a NULL pointer. + * Also define The global variable that holds the passed pointer. + */ +#define PRINT if ( app_print ) app_print +static int (*app_print)(char *,...); + +/* Set by call to get_eumbbar during DMA_Initialize. + * This could be globally available to the library, but there is + * an advantage to passing it as a parameter: it is already in a register + * and doesn't have to be loaded from memory. Also, that is the way the + * library was already implemented and I don't want to change it without + * a more detailed analysis. + * It is being set as a global variable during initialization to hide it from + * the DINK application layer, because it is Kahlua-specific. I think that + * get_eumbbar, load_runtime_reg, and store_runtime_reg should be defined in + * a Kahlua-specific library dealing with the embedded utilities memory block. + * Right now, get_eumbbar is defined in dink32/kahlua.s. The other two are + * defined in dink32/drivers/i2c/i2c2.s, drivers/dma/dma2.s, etc. + */ +static unsigned int Global_eumbbar = 0; +extern unsigned int get_eumbbar(); + + +extern unsigned int load_runtime_reg( unsigned int eumbbar, unsigned int reg ); +#pragma Alias( load_runtime_reg, "load_runtime_reg" ); + +extern void store_runtime_reg( unsigned int eumbbar, unsigned int reg, unsigned int val ); +#pragma Alias( store_runtime_reg, "store_runtime_reg" ); + +unsigned int dma_reg_tb[][14] = { + /* local DMA registers */ + { + /* DMA_0_MR */ 0x00001100, + /* DMA_0_SR */ 0x00001104, + /* DMA_0_CDAR */ 0x00001108, + /* DMA_0_SAR */ 0x00001110, + /* DMA_0_DAR */ 0x00001118, + /* DMA_0_BCR */ 0x00001120, + /* DMA_0_NDAR */ 0x00001124, + /* DMA_1_MR */ 0x00001200, + /* DMA_1_SR */ 0x00001204, + /* DMA_1_CDAR */ 0x00001208, + /* DMA_1_SAR */ 0x00001210, + /* DMA_1_DAR */ 0x00001218, + /* DMA_1_BCR */ 0x00001220, + /* DMA_1_NDAR */ 0x00001224, + }, + /* remote DMA registers */ + { + /* DMA_0_MR */ 0x00000100, + /* DMA_0_SR */ 0x00000104, + /* DMA_0_CDAR */ 0x00000108, + /* DMA_0_SAR */ 0x00000110, + /* DMA_0_DAR */ 0x00000118, + /* DMA_0_BCR */ 0x00000120, + /* DMA_0_NDAR */ 0x00000124, + /* DMA_1_MR */ 0x00000200, + /* DMA_1_SR */ 0x00000204, + /* DMA_1_CDAR */ 0x00000208, + /* DMA_1_SAR */ 0x00000210, + /* DMA_1_DAR */ 0x00000218, + /* DMA_1_BCR */ 0x00000220, + /* DMA_1_NDAR */ 0x00000224, + }, +}; + +/* API functions */ + +/* Initialize DMA unit with the following: + * optional pointer to application layer print function + * + * These parameters may be added: + * ??? + * Interrupt enables, modes, etc. are set for each transfer. + * + * This function must be called before DMA unit can be used. + */ +extern +DMA_Status DMA_Initialize( int (*p)(char *,...)) +{ + DMAStatus status; + /* establish the pointer, if there is one, to the application's "printf" */ + app_print = p; + + /* If this is the first call, get the embedded utilities memory block + * base address. I'm not sure what to do about error handling here: + * if a non-zero value is returned, accept it. + */ + if ( Global_eumbbar == 0) + Global_eumbbar = get_eumbbar(); + if ( Global_eumbbar == 0) + { + PRINT( "DMA_Initialize: can't find EUMBBAR\n" ); + return DMA_ERROR; + } + + return DMA_SUCCESS; +} + + +/* Perform the DMA transfer, only direct mode is currently implemented. + * At this point, I think it would be better to define a different + * function for chaining mode. + * Also, I'm not sure if it is appropriate to have the "generic" API + * accept snoop and int_steer parameters. The DINK user interface allows + * them, so for now I'll leave them. + * + * int_steer controls DMA interrupt steering to PCI or local processor + * type is the type of transfer: M2M, M2P, P2M, P2P + * source is the source address of the data + * dest is the destination address of the data + * len is the length of data to transfer + * channel is the DMA channel to use for the transfer + * snoop is the snoop enable control + */ +extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer, + DMA_TRANSFER_TYPE type, + unsigned int source, + unsigned int dest, + unsigned int len, + DMA_CHANNEL channel, + DMA_SNOOP_MODE snoop) +{ + DMA_MR md; + DMA_CDAR cdar; + /* it's inappropriate for curr to be a struct, but I'll leave it */ + DMA_CURR curr; + + DMAStatus stat; + + /* The rest of this code was moved from device.c test_dma to here. + * It needs to be cleaned up and validated, but at least it is removed + * from the application and API. Most of the mode is left hard coded. + * This should be changed after the final API is defined and the user + * application has a way to control the transfer. + * + */ + + if ( DMA_Get_Mode( LOCAL, Global_eumbbar, channel, &md ) != DMASUCCESS ) + { + return DMA_ERROR; + } + + md.irqs = int_steer; + md.pde = 0; + md.dahts = 3; /* 8 - byte */ + md.sahts = 3; /* 8 - byte */ + md.dahe = 0; + md.sahe = 0; + md.prc = 0; + /* if steering interrupts to local processor, use polling mode */ + if ( int_steer == DMA_INT_STEER_PCI ) + { + md.eie = 1; + md.eotie = 1; + } else { + md.eie = 0; + md.eotie = 0; + } + md.dl = 0; + md.ctm = 1; /* direct mode */ + md.cc = 0; + + /* validate the length range */ + if (len > 0x3ffffff ) + { + PRINT( "dev DMA: length of transfer too large: %d\n", len ); + return DMA_ERROR; + } + + /* inappropriate to use a struct, but leave as is for now */ + curr.src_addr = source; + curr.dest_addr = dest; + curr.byte_cnt = len; + + (void)DMA_Poke_Desp( LOCAL, Global_eumbbar, channel, &cdar ); + cdar.snen = snoop; + cdar.ctt = type; + + if ( ( stat = DMA_Bld_Desp( LOCAL, Global_eumbbar, channel, cdar )) + != DMASUCCESS || + ( stat = DMA_Bld_Curr( LOCAL, Global_eumbbar, channel, curr )) + != DMASUCCESS || + ( stat = DMA_Set_Mode( LOCAL, Global_eumbbar, channel, md )) + != DMASUCCESS || + ( stat = DMA_Start( LOCAL, Global_eumbbar, channel )) + != DMASUCCESS ) + { + if ( stat == DMACHNBUSY ) + { + PRINT( "dev DMA: channel %d busy.\n", channel ); + } + else + { + PRINT( "dev DMA: invalid channel request.\n", channel ); + } + + return DMA_ERROR; + } + +/* Since we are interested at the DMA performace right now, + we are going to do as less as possible to burden the + 603e core. + + if you have epic enabled or don't care the return from + DMA operation, you can just return SUCCESS. + + if you don't have epic enabled and care the DMA result, + you can use the polling method below. + + Note: I'll attempt to activate the code for handling polling. + */ + +#if 0 + /* if steering interrupt to local processor, let it handle results */ + if ( int_steer == DMA_INT_STEER_LOCAL ) + { + return DMA_SUCCESS; + } + + /* polling since interrupt goes to PCI */ + do + { + stat = DMA_ISR( Global_eumbbar, channel, dma_error_func, + dma_error_func, dma_error_func, dma_error_func ); + } + while ( stat == DMANOEVENT ); +#endif + + return DMA_SUCCESS; +} + +/* DMA library internal functions */ + +/** + * Note: + * + * In all following functions, the host (KAHLUA) processor has a + * choice of accessing on board local DMA (LOCAL), + * or DMA on a distributed KAHLUA (REMOTE). In either case, + * the caller shall pass the configured embedded utility memory + * block base address relative to the DMA. If LOCAL DMA is used, + * this parameter shall be EUMBBAR, if REMOTE is used, the + * parameter shall be the corresponding PCSRBAR. + **/ + +/************************************************************** + * function: DMA_Get_Stat + * + * description: return the content of status register of + * the given DMA channel + * + * if error, reserved0 field all 1s. + **************************************************************/ +static +DMAStatus DMA_Get_Stat( LOCATION host, unsigned int eumbbar, unsigned int channel, DMA_SR *stat ) +{ + unsigned int tmp; + + if ( channel != 0 && channel != 1 || stat == 0 ) + { + return DMAINVALID; + } + + tmp = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SR_REG] ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) stat = 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SR_REG], tmp ); +#endif + + stat->reserved0 = ( tmp & 0xffffff00 ) >> 8; + stat->lme = ( tmp & 0x00000080 ) >> 7; + stat->reserved1 = ( tmp & 0x00000060 ) >> 5; + stat->pe = ( tmp & 0x00000010 ) >> 4; + stat->reserved2 = ( tmp & 0x00000008 ) >> 3; + stat->cb = ( tmp & 0x00000004 ) >> 2; + stat->eosi = ( tmp & 0x00000002 ) >> 1; + stat->eocai = ( tmp & 0x00000001 ); + + return DMASUCCESS; +} + +/************************************************************** + * function: DMA_Get_Mode + * + * description: return the content of mode register of the + * given DMA channel + * + * if error, return DMAINVALID, otherwise return + * DMASUCCESS + **************************************************************/ +static +DMAStatus DMA_Get_Mode( LOCATION host, unsigned eumbbar, unsigned int channel, DMA_MR *mode ) +{ + unsigned int tmp; + if ( channel != 0 && channel != 1 || mode == 0 ) + { + return DMAINVALID; + } + + tmp = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_MR_REG] ); + +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) mode = 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_MR_REG], tmp ); +#endif + + mode->reserved0 = (tmp & 0xfff00000) >> 20; + mode->irqs = (tmp & 0x00080000) >> 19; + mode->pde = (tmp & 0x00040000) >> 18; + mode->dahts = (tmp & 0x00030000) >> 16; + mode->sahts = (tmp & 0x0000c000) >> 14; + mode->dahe = (tmp & 0x00002000) >> 13; + mode->sahe = (tmp & 0x00001000) >> 12; + mode->prc = (tmp & 0x00000c00) >> 10; + mode->reserved1 = (tmp & 0x00000200) >> 9; + mode->eie = (tmp & 0x00000100) >> 8; + mode->eotie = (tmp & 0x00000080) >> 7; + mode->reserved2 = (tmp & 0x00000070) >> 4; + mode->dl = (tmp & 0x00000008) >> 3; + mode->ctm = (tmp & 0x00000004) >> 2; + mode->cc = (tmp & 0x00000002) >> 1; + mode->cs = (tmp & 0x00000001); + + return DMASUCCESS; +} + +/************************************************************** + * function: DMA_Set_Mode + * + * description: Set a new mode to a given DMA channel + * + * note: It is not a good idea of changing the DMA mode during + * the middle of a transaction. + **************************************************************/ +static +DMAStatus DMA_Set_Mode( LOCATION host, unsigned eumbbar, unsigned int channel, DMA_MR mode ) +{ + unsigned int tmp; + if ( channel != 0 && channel != 1 ) + { + return DMAINVALID; + } + + tmp = ( mode.reserved0 & 0xfff ) << 20; + tmp |= ( ( mode.irqs & 0x1 ) << 19); + tmp |= ( ( mode.pde & 0x1 ) << 18 ); + tmp |= ( ( mode.dahts & 0x3 ) << 16 ); + tmp |= ( ( mode.sahts & 0x3 ) << 14 ); + tmp |= ( ( mode.dahe & 0x1 ) << 13 ); + tmp |= ( ( mode.sahe & 0x1 ) << 12 ); + tmp |= ( ( mode.prc & 0x3 ) << 10 ); + tmp |= ( ( mode.reserved1 & 0x1 ) << 9 ); + tmp |= ( ( mode.eie & 0x1 ) << 8 ); + tmp |= ( ( mode.eotie & 0x1 ) << 7 ); + tmp |= ( ( mode.reserved2 & 0x7 ) << 4 ); + tmp |= ( ( mode.dl & 0x1 ) << 3 ); + tmp |= ( ( mode.ctm & 0x1 ) << 2 ); + tmp |= ( ( mode.cc & 0x1 ) << 1 ) ; + tmp |= ( mode.cs & 0x1 ); + + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], tmp ); + return DMASUCCESS; +} + +/************************************************************ + * function: DMA_Start + * + * description: start a given DMA channel transaction + * return DMASUCCESS if success otherwise return + * DMAStatus value + * + * note: this function will clear DMA_MR(CC) first, then + * set DMA_MR(CC). + ***********************************************************/ +static +DMAStatus DMA_Start( LOCATION host, unsigned int eumbbar, unsigned int channel ) +{ + DMA_SR stat; + unsigned int mode; + + if ( channel != 0 && channel != 1 ) + { + return DMAINVALID; + } + + if ( DMA_Get_Stat( host, eumbbar, channel, &stat ) != DMASUCCESS ) + { + return DMAINVALID; + } + + if ( stat.cb == 1 ) + { + /* DMA is not free */ + return DMACHNBUSY; + } + + mode = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG] ); + /* clear DMA_MR(CS) */ + mode &= 0xfffffffe; + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode ); + + /* set DMA_MR(CS) */ + mode |= CS; + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode ); + return DMASUCCESS; +} + +/*********************************************************** + * function: DMA_Halt + * + * description: halt the current dma transaction on the specified + * channel. + * return DMASUCCESS if success otherwise return DMAINVALID + * + * note: if the specified DMA channel is idle, nothing happens + *************************************************************/ +static +DMAStatus DMA_Halt( LOCATION host, unsigned int eumbbar, unsigned int channel ) +{ + unsigned int mode; + if ( channel != 0 && channel != 1 ) + { + return DMAINVALID; + } + + mode = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG]); + + /* clear DMA_MR(CS) */ + mode &= 0xfffffffe; + store_runtime_reg(eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG + DMA_MR_REG], mode ); + return DMASUCCESS; +} + +/************************************************************* + * function: DMA_Chn_Cnt + * + * description: set the DMA_MR(CC) bit for a given channel + * that is in chaining mode. + * return DMASUCCESS if successfule, otherwise return + * DMAINVALID. + * + * note: if the given channel is not in chaining mode, nothing + * happen. + * + *************************************************************/ +static +DMAStatus DMA_Chn_Cnt( LOCATION host, unsigned int eumbbar, unsigned int channel ) +{ + DMA_MR mode; + if ( channel != 0 && channel != 1 ) + { + return DMAINVALID; + } + + if ( DMA_Get_Mode( host, eumbbar, channel, &mode ) != DMASUCCESS ) + { + return DMAINVALID; + } + + if ( mode.ctm == 0 ) + { + /* either illegal mode or not chaining mode */ + return DMAINVALID; + } + + mode.cc = 1; + return DMA_Set_Mode( host, eumbbar, channel, mode ); +} + +/************************************************************** + * function: DMA_Bld_Desp + * + * description: set current descriptor address register + * according to the desp for a given channel + * + * if the given channel is busy return DMACHNBUSY + * and no change made, otherwise return DMASUCCESS. + * + * note: + **************************************************************/ +static +DMAStatus DMA_Bld_Desp( LOCATION host, + unsigned int eumbbar, + unsigned int channel, + DMA_CDAR desp ) +{ + DMA_SR status; + unsigned int temp; + + if ( channel != 0 && channel != 1 ) + { + /* channel number out of range */ + return DMAINVALID; + } + + if ( DMA_Get_Stat( host, eumbbar, channel, &status ) != DMASUCCESS ) + { + return DMAINVALID; + } + + if ( status.cb == 1 ) + { + /* channel busy */ + return DMACHNBUSY; + } + + temp = ( desp.cda & 0x7ffffff ) << 5; + temp |= (( desp.snen & 0x1 ) << 4 ); + temp |= (( desp.eosie & 0x1 ) << 3 ); + temp |= (( desp.ctt & 0x3 ) << 1 ); + temp |= ( desp.eotd & 0x1 ); + + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], temp ); + +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) cdar := 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], temp ); +#endif + + return DMASUCCESS; +} + +/************************************************************** + * function: DMA_Poke_Desp + * + * description: poke the current descriptor address register + * for a given channel + * + * return DMASUCCESS if no error + * + * note: Due to the undeterministic parallellism of DMA operation, + * the value returned by this function shall be taken as + * the most recently used descriptor when the last time + * DMA starts a chaining mode operation. + **************************************************************/ +static +DMAStatus DMA_Poke_Desp( LOCATION host, + unsigned int eumbbar, + unsigned int channel, + DMA_CDAR *desp ) +{ + unsigned int cdar; + if ( channel != 0 && channel != 1 || desp == 0 ) + { + return DMAINVALID; + } + + cdar = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG] ); + +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) cdar : 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], cdar ); +#endif + + + desp->cda = ( cdar & 0xffffffe0 ) >> 5; + desp->snen = ( cdar & 0x00000010 ) >> 4; + desp->eosie = ( cdar & 0x00000008 ) >> 3; + desp->ctt = ( cdar & 0x00000006 ) >> 1; + desp->eotd = ( cdar & 0x00000001 ); + + return DMASUCCESS; +} + +/************************************************************** + * function: DMA_Bld_Curr + * + * description: set current src, dest, byte count registers + * according to the desp for a given channel + * return DMASUCCESS if no error. + * + * note: + **************************************************************/ +static +DMAStatus DMA_Bld_Curr( LOCATION host, + unsigned int eumbbar, + unsigned int channel, + DMA_CURR desp ) +{ + DMA_SR status; + if ( channel != 0 && channel != 1 ) + { + /* channel number out of range */ + return DMAINVALID; + } + + if ( DMA_Get_Stat( host, eumbbar, channel, &status ) != DMASUCCESS ) + { + return DMAINVALID; + } + + if ( status.cb == 1 ) + { + /* channel busy */ + return DMACHNBUSY; + } + + desp.byte_cnt &= 0x03ffffff; /* upper 6-bits are 0s */ + + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SAR_REG], desp.src_addr ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) src := 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.src_addr ); +#endif + + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_DAR_REG], desp.dest_addr ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) dest := 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.dest_addr ); +#endif + + store_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_BCR_REG], desp.byte_cnt ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) count := 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp.byte_cnt ); +#endif + + + return DMASUCCESS; + +} + +/************************************************************** + * function: DMA_Poke_Curr + * + * description: poke the current src, dest, byte count registers + * for a given channel. + * + * return DMASUCCESS if no error + * + * note: Due to the undeterministic parallelism, in chaining + * mode, the value returned by this function shall + * be taken as reference when the query is made rather + * than the absolute snapshot when the value is returned. + **************************************************************/ +static +DMAStatus DMA_Poke_Curr( LOCATION host, + unsigned int eumbbar, + unsigned int channel, + DMA_CURR* desp ) +{ + if ( channel != 0 && channel != 1 || desp == 0 ) + { + return DMAINVALID; + } + + desp->src_addr = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_SAR_REG] ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) src : 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->src_addr ); +#endif + + desp->dest_addr = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_DAR_REG] ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) dest : 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->dest_addr ); +#endif + + desp->byte_cnt = load_runtime_reg( eumbbar, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_BCR_REG] ); +#ifdef DMADBG0 + PRINT( "%s(%d): %s DMA %d (0x%08x) count : 0x%08x\n", __FILE__, __LINE__, + ( host == LOCAL ? "local" : "remote" ), channel, dma_reg_tb[host][channel*NUM_DMA_REG+DMA_CDAR_REG], desp->byte_cnt ); +#endif + + + return DMASUCCESS; +} + +/***************************************************************** + * function: dma_error_func + * + * description: display the error information + * + * note: This seems like a highly convoluted way to handle messages, + * but I'll leave it as it was in device.c when I moved it into the + * DMA library source. + ****************************************************************/ +static +DMAStatus dma_error_func( unsigned int eumbbar, unsigned int chn, DMAStatus err) +{ + unsigned char *msg[] = + { + "Local Memory Error", + "PCI Error", + "Channel Busy", + "End-of-Segment Interrupt", + "End-of-Chain/Direct Interrupt", + }; + + if ( err >= DMALMERROR && err <= DMAEOCAINT ) + { + PRINT( "DMA Status: channel %d %s\n", chn, msg[err-DMASUCCESS-1] ); + } + + return err; + +} + +/************************************************************* + * function: DMA_ISR + * + * description: DMA interrupt service routine + * return DMAStatus value based on + * the status + * + *************************************************************/ +static +DMAStatus DMA_ISR( unsigned int eumbbar, + unsigned int channel, + DMAStatus (*lme_func)( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*pe_func) ( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*eosi_func)( unsigned int, unsigned int, DMAStatus ), + DMAStatus (*eocai_func)(unsigned int, unsigned int, DMAStatus )) +{ + + DMA_SR stat; + DMAStatus rval = DMANOEVENT; + unsigned int temp; + + if ( channel != 0 && channel != 1 ) + { + return DMAINVALID; + } + + if ( DMA_Get_Stat( LOCAL, eumbbar, channel, &stat ) != DMASUCCESS ) + { + return DMAINVALID; + } + + if ( stat.lme == 1 ) + { + /* local memory error */ + rval = DMALMERROR; + if ( lme_func != 0 ) + { + rval = (*lme_func)(eumbbar, channel, DMALMERROR ); + } + + } + else if ( stat.pe == 1 ) + { + /* PCI error */ + rval = DMAPERROR; + if ( pe_func != 0 ) + { + rval = (*pe_func)(eumbbar, channel, DMAPERROR ); + } + + } + else if ( stat.eosi == 1 ) + { + /* end-of-segment interrupt */ + rval = DMAEOSINT; + if ( eosi_func != 0 ) + { + rval = (*eosi_func)(eumbbar, channel, DMAEOSINT ); + } + } + else + { + /* End-of-chain/direct interrupt */ + rval = DMAEOCAINT; + if ( eocai_func != 0 ) + { + rval = (*eocai_func)(eumbbar, channel, DMAEOCAINT ); + } + } + + temp = ( stat.reserved0 & 0xffffff ) << 8; + temp |= ( ( stat.lme & 0x1 ) << 7 ); /* write one to clear */ + temp |= ( ( stat.reserved1 & 0x3 ) << 5 ); + temp |= ( ( stat.pe & 0x1 ) << 4 ); /* write one to clear */ + temp |= ( ( stat.reserved2 & 0x1 ) << 3 ); + temp |= ( ( stat.cb & 0x1 ) << 2 ); /* write one to clear */ + temp |= ( ( stat.eosi & 0x1 ) << 1 ); /* write one to clear */ + temp |= ( stat.eocai & 0x1 ); /* write one to clear */ + + store_runtime_reg( eumbbar, dma_reg_tb[LOCAL][channel*NUM_DMA_REG + DMA_SR_REG], temp ); + +#ifdef DMADBG0 + PRINT( "%s(%d): DMA channel %d SR := 0x%08x\n", __FILE__, __LINE__, channel, temp ); +#endif + + return rval; +} diff --git a/cpu/mpc824x/drivers/dma/dma2.S b/cpu/mpc824x/drivers/dma/dma2.S new file mode 100644 index 000000000..ccbc22646 --- /dev/null +++ b/cpu/mpc824x/drivers/dma/dma2.S @@ -0,0 +1,42 @@ +/************************************** + * + * copyright @ Motorola, 1999 + * + **************************************/ + +/********************************************************** + * function: load_runtime_reg + * + * input: r3 - value of eumbbar + * r4 - register offset in embedded utility space + * + * output: r3 - register content + **********************************************************/ + .text + .align 2 + .global load_runtime_reg + +load_runtime_reg: + + lwbrx r3,r4,r3 + sync + + bclr 20, 0 + +/**************************************************************** + * function: store_runtime_reg + * + * input: r3 - value of eumbbar + * r4 - register offset in embedded utility space + * r5 - new value to be stored + * + ****************************************************************/ + .text + .align 2 + .global store_runtime_reg +store_runtime_reg: + + stwbrx r5, r4, r3 + sync + + bclr 20,0 diff --git a/cpu/mpc824x/drivers/dma/dma_export.h b/cpu/mpc824x/drivers/dma/dma_export.h new file mode 100644 index 000000000..471e488c4 --- /dev/null +++ b/cpu/mpc824x/drivers/dma/dma_export.h @@ -0,0 +1,100 @@ +#ifndef DMA_EXPORT_H +#define DMA_EXPORT_H + +/**************************************************** + * $Id: + * + * Copyright Motorola 1999 + * + * $Log: + * + ****************************************************/ + +/* These are the defined return values for the DMA_* functions. + * Any non-zero value indicates failure. Failure modes can be added for + * more detailed error reporting. + */ +typedef enum _dma_status +{ + DMA_SUCCESS = 0, + DMA_ERROR, +} DMA_Status; + +/* These are the defined channel transfer types. */ +typedef enum _dma_transfer_types +{ + DMA_M2M = 0, /* local memory to local memory */ + DMA_M2P = 1, /* local memory to PCI */ + DMA_P2M = 2, /* PCI to local memory */ + DMA_P2P = 3, /* PCI to PCI */ +} DMA_TRANSFER_TYPE; + +typedef enum _dma_interrupt_steer +{ + DMA_INT_STEER_LOCAL = 0, /* steer DMA int to local processor */ + DMA_INT_STEER_PCI = 1, /* steer DMA int to PCI bus through INTA_ */ +} DMA_INTERRUPT_STEER; + +typedef enum _dma_channel +{ + DMA_CHN_0 = 0, /* kahlua has two dma channels: 0 and 1 */ + DMA_CHN_1 = 1, +} DMA_CHANNEL; + +typedef enum _dma_snoop_mode +{ + DMA_SNOOP_DISABLE = 0, + DMA_SNOOP_ENABLE = 1, +} DMA_SNOOP_MODE; + +/******************** App. API ******************** + * The application API is for user level application + * to use the functionality provided by DMA driver. + * This is a "generic" DMA interface, it should contain + * nothing specific to the Kahlua implementation. + * Only the generic functions are exported by the library. + * + * Note: Its App.s responsibility to swap the data + * byte. In our API, we currently transfer whatever + * we are given - Big/Little Endian. This could + * become part of the DMA config, though. + **************************************************/ + + +/* Initialize DMA unit with the following: + * optional pointer to application layer print function + * + * These parameters may be added: + * ??? + * Interrupt enables, modes, etc. are set for each transfer. + * + * This function must be called before DMA unit can be used. + */ +extern DMA_Status DMA_Initialize( + int (*app_print_function)(char *,...)); /* pointer to optional "printf" + * provided by application + */ + +/* Perform the DMA transfer, only direct mode is currently implemented. + * At this point, I think it would be better to define a different + * function for chaining mode. + * Also, I'm not sure if it is appropriate to have the "generic" API + * accept snoop and int_steer parameters. The DINK user interface allows + * them, so for now I'll leave them. + * + * int_steer controls DMA interrupt steering to PCI or local processor + * type is the type of transfer: M2M, M2P, P2M, P2P + * source is the source address of the data + * dest is the destination address of the data + * len is the length of data to transfer + * channel is the DMA channel to use for the transfer + * snoop is the snoop enable control + */ +extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer, + DMA_TRANSFER_TYPE type, + unsigned int source, + unsigned int dest, + unsigned int len, + DMA_CHANNEL channel, + DMA_SNOOP_MODE snoop); +#endif diff --git a/cpu/mpc824x/drivers/dma_export.h b/cpu/mpc824x/drivers/dma_export.h new file mode 100644 index 000000000..471e488c4 --- /dev/null +++ b/cpu/mpc824x/drivers/dma_export.h @@ -0,0 +1,100 @@ +#ifndef DMA_EXPORT_H +#define DMA_EXPORT_H + +/**************************************************** + * $Id: + * + * Copyright Motorola 1999 + * + * $Log: + * + ****************************************************/ + +/* These are the defined return values for the DMA_* functions. + * Any non-zero value indicates failure. Failure modes can be added for + * more detailed error reporting. + */ +typedef enum _dma_status +{ + DMA_SUCCESS = 0, + DMA_ERROR, +} DMA_Status; + +/* These are the defined channel transfer types. */ +typedef enum _dma_transfer_types +{ + DMA_M2M = 0, /* local memory to local memory */ + DMA_M2P = 1, /* local memory to PCI */ + DMA_P2M = 2, /* PCI to local memory */ + DMA_P2P = 3, /* PCI to PCI */ +} DMA_TRANSFER_TYPE; + +typedef enum _dma_interrupt_steer +{ + DMA_INT_STEER_LOCAL = 0, /* steer DMA int to local processor */ + DMA_INT_STEER_PCI = 1, /* steer DMA int to PCI bus through INTA_ */ +} DMA_INTERRUPT_STEER; + +typedef enum _dma_channel +{ + DMA_CHN_0 = 0, /* kahlua has two dma channels: 0 and 1 */ + DMA_CHN_1 = 1, +} DMA_CHANNEL; + +typedef enum _dma_snoop_mode +{ + DMA_SNOOP_DISABLE = 0, + DMA_SNOOP_ENABLE = 1, +} DMA_SNOOP_MODE; + +/******************** App. API ******************** + * The application API is for user level application + * to use the functionality provided by DMA driver. + * This is a "generic" DMA interface, it should contain + * nothing specific to the Kahlua implementation. + * Only the generic functions are exported by the library. + * + * Note: Its App.s responsibility to swap the data + * byte. In our API, we currently transfer whatever + * we are given - Big/Little Endian. This could + * become part of the DMA config, though. + **************************************************/ + + +/* Initialize DMA unit with the following: + * optional pointer to application layer print function + * + * These parameters may be added: + * ??? + * Interrupt enables, modes, etc. are set for each transfer. + * + * This function must be called before DMA unit can be used. + */ +extern DMA_Status DMA_Initialize( + int (*app_print_function)(char *,...)); /* pointer to optional "printf" + * provided by application + */ + +/* Perform the DMA transfer, only direct mode is currently implemented. + * At this point, I think it would be better to define a different + * function for chaining mode. + * Also, I'm not sure if it is appropriate to have the "generic" API + * accept snoop and int_steer parameters. The DINK user interface allows + * them, so for now I'll leave them. + * + * int_steer controls DMA interrupt steering to PCI or local processor + * type is the type of transfer: M2M, M2P, P2M, P2P + * source is the source address of the data + * dest is the destination address of the data + * len is the length of data to transfer + * channel is the DMA channel to use for the transfer + * snoop is the snoop enable control + */ +extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer, + DMA_TRANSFER_TYPE type, + unsigned int source, + unsigned int dest, + unsigned int len, + DMA_CHANNEL channel, + DMA_SNOOP_MODE snoop); +#endif diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/cpu/mpc824x/drivers/epic/epic2.S index 52d19aae8..8cc2fc60b 100644 --- a/cpu/mpc824x/drivers/epic/epic2.S +++ b/cpu/mpc824x/drivers/epic/epic2.S @@ -169,7 +169,7 @@ epic_exception: xor r3,r3,r3 xor r4,r4,r4 or r3, r3, r6 /* eumbbar in r3 */ - andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */ + andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */ stw r4,0x04(r1) /* save the vector value */ diff --git a/cpu/mpc824x/drivers/errors.h b/cpu/mpc824x/drivers/errors.h index 20794a2e8..887f284fc 100644 --- a/cpu/mpc824x/drivers/errors.h +++ b/cpu/mpc824x/drivers/errors.h @@ -61,7 +61,7 @@ to standardize the error handling in the current project */ message back to the user. */ /*----------------------------------------------------------------------*/ -/* these are specifically for the parser routines */ +/* these are specifically for the parser routines */ #define UNKNOWN_COMMAND 0xfb00 /* "unrecognized command " */ #define UNKNOWN_REGISTER 0xfb01 /* "unknown register "*/ @@ -73,8 +73,8 @@ to standardize the error handling in the current project */ #define UNIMPLEMENTED_STAGE 0xfb05 /* invalid rd or rmm parameter format */ #define REG_NOT_WRITEABLE 0xfb06 /* "unknown operator in arguements"*/ #define INVALID_FILENAME 0xfb07 /* "invalid download filename" */ -#define INVALID_BAUD_RATE 0xfb08 /* invalid baud rate from sb command */ -#define UNSUPPORTED_REGISTER 0xfb09 /* Special register is not supported */ +#define INVALID_BAUD_RATE 0xfb08 /* invalid baud rate from sb command */ +#define UNSUPPORTED_REGISTER 0xfb09 /* Special register is not supported */ #define FOR_BOARD_ONLY 0xfb0a /* "Not available for Unix." */ @@ -140,20 +140,20 @@ to standardize the error handling in the current project */ #define INVALID_FLAG 0xfd0c /* invalid flag */ /*----------------------------------------------------------------------*/ -/* these are for the getarg toolbox */ +/* these are for the getarg toolbox */ -#define INVALID_NUMBER_ARGS 0xFE00 /* invalid number of commd arguements */ +#define INVALID_NUMBER_ARGS 0xFE00 /* invalid number of commd arguements */ #define UNKNOWN_PARAMETER 0xFE01 /* "unknown type of parameter "*/ /*----------------------------------------------------------------------*/ -/* these are for the tokenizer toolbox */ +/* these are for the tokenizer toolbox */ -#define ILLEGAL_CHARACTER 0xFF00 /* unrecognized char. in input stream*/ -#define TTL_NOT_SORTED 0xFF01 /* token translation list not sorted */ -#define TTL_NOT_DEFINED 0xFF02 /* token translation list not assigned*/ -#define INVALID_STRING 0xFF03 /* unable to extract string from input */ -#define BUFFER_EMPTY 0xFF04 /* "input buffer is empty" */ +#define ILLEGAL_CHARACTER 0xFF00 /* unrecognized char. in input stream*/ +#define TTL_NOT_SORTED 0xFF01 /* token translation list not sorted */ +#define TTL_NOT_DEFINED 0xFF02 /* token translation list not assigned*/ +#define INVALID_STRING 0xFF03 /* unable to extract string from input */ +#define BUFFER_EMPTY 0xFF04 /* "input buffer is empty" */ #define INVALID_MODE 0xFF05 /* input buf is in an unrecognized mode*/ #define TOK_INTERNAL_ERROR 0xFF06 /* "internal tokenizer error" */ #define TOO_MANY_IBS 0xFF07 /* "too many open input buffers" */ @@ -172,7 +172,7 @@ to standardize the error handling in the current project */ /* THESE are for the downloader */ -#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */ +#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */ #define UNREC_RECORD_TYPE 0xf901 /* "unrecognized record type" */ #define CONVERSION_ERROR 0xf902 /* "ascii to int conversion error" */ #define INVALID_MEMORY 0xf903 /* "bad s-record memory address " */ @@ -190,7 +190,7 @@ to standardize the error handling in the current project */ /* these are for the DUART handling things */ /* "unrecognized serial port configuration" */ -#define UNKNOWN_PORT_STATE 0xf700 +#define UNKNOWN_PORT_STATE 0xf700 /* these are for the register toolbox */ @@ -208,5 +208,5 @@ to standardize the error handling in the current project */ /*----------------------------------------------------------------------*/ -/* these are specifically for the flash routines */ -#define FLASH_ERROR 0xf100 /* general flash error */ +/* these are specifically for the flash routines */ +#define FLASH_ERROR 0xf100 /* general flash error */ diff --git a/cpu/mpc824x/drivers/i2o.h b/cpu/mpc824x/drivers/i2o.h new file mode 100644 index 000000000..c47253d0f --- /dev/null +++ b/cpu/mpc824x/drivers/i2o.h @@ -0,0 +1,344 @@ +#ifndef I2O_H +#define I2O_H +/********************************************************* + * + * copyright @ Motorola, 1999 + *********************************************************/ + +#define I2O_REG_OFFSET 0x0004 + +#define PCI_CFG_CLA 0x0B +#define PCI_CFG_SCL 0x0A +#define PCI_CFG_PIC 0x09 + +#define I2O_IMR0 0x0050 +#define I2O_IMR1 0x0054 +#define I2O_OMR0 0x0058 +#define I2O_OMR1 0x005C + +#define I2O_ODBR 0x0060 +#define I2O_IDBR 0x0068 + +#define I2O_OMISR 0x0030 +#define I2O_OMIMR 0x0034 +#define I2O_IMISR 0x0100 +#define I2O_IMIMR 0x0104 + +/* accessable to PCI master but local processor */ +#define I2O_IFQPR 0x0040 +#define I2O_OFQPR 0x0044 + +/* accessable to local processor */ +#define I2O_IFHPR 0x0120 +#define I2O_IFTPR 0x0128 +#define I2O_IPHPR 0x0130 +#define I2O_IPTPR 0x0138 +#define I2O_OFHPR 0x0140 +#define I2O_OFTPR 0x0148 +#define I2O_OPHPR 0x0150 +#define I2O_OPTPR 0x0158 +#define I2O_MUCR 0x0164 +#define I2O_QBAR 0x0170 + +#define I2O_NUM_MSG 2 + +typedef enum _i2o_status +{ + I2OSUCCESS = 0, + I2OINVALID, + I2OMSGINVALID, + I2ODBINVALID, + I2OQUEINVALID, + I2OQUEEMPTY, + I2OQUEFULL, + I2ONOEVENT, +} I2OSTATUS; + +typedef enum _queue_size +{ + QSIZE_4K = 0x02, + QSIZE_8K = 0x04, + QSIZE_16K = 0x08, + QSIZE_32K = 0x10, + QSIZe_64K = 0x20, +} QUEUE_SIZE; + +typedef enum _location +{ + LOCAL = 0, /* used by local processor to access its own on board device, + local processor's eumbbar is required */ + REMOTE, /* used by PCI master to access the devices on its PCI device, + device's pcsrbar is required */ +} LOCATION; + +/* door bell */ +typedef enum _i2o_in_db +{ + IN_DB = 1, + MC, /* machine check */ +} I2O_IN_DB; + +/* I2O PCI configuration identification */ +typedef struct _i2o_iop +{ + unsigned int base_class : 8; + unsigned int sub_class : 8; + unsigned int prg_code : 8; +} I2OIOP; + +/* I2O Outbound Message Interrupt Status Register */ +typedef struct _i2o_om_stat +{ + unsigned int rsvd0 : 26; + unsigned int opqi : 1; + unsigned int rsvd1 : 1; + unsigned int odi : 1; + unsigned int rsvd2 : 1; + unsigned int om1i : 1; + unsigned int om0i : 1; +} I2OOMSTAT; + +/* I2O inbound Message Interrupt Status Register */ +typedef struct _i2o_im_stat +{ + unsigned int rsvd0 : 23; + unsigned int ofoi : 1; + unsigned int ipoi : 1; + unsigned int rsvd1 : 1; + unsigned int ipqi : 1; + unsigned int mci : 1; + unsigned int idi : 1; + unsigned int rsvd2 : 1; + unsigned int im1i : 1; + unsigned int im0i : 1; +} I2OIMSTAT; + +/** + Enable the interrupt associated with in/out bound msg + + Inbound message interrupt generated by PCI master and serviced by local processor + local processor needs to enable its inbound interrupts it wants to handle (LOCAL) + + Outbound message interrupt generated by local processor and serviced by PCI master + PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE) + **/ +extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ); /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ + +/** + Disable the interrupt associated with in/out bound msg + + local processor needs to disable its inbound interrupts it is not interested (LOCAL) + + PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE) + **/ +extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ); /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ + +/** + Read the msg register either from local inbound msg 0/1, + or an outbound msg 0/1 of devices. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, outbound msg of the device is read. + Otherwise local inbound msg is read. + **/ +extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int *msg ); + +/** + Write to nth Msg register either on local outbound msg 0/1, + or aninbound msg 0/1 of devices + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, inbound msg on the device is written. + Otherwise local outbound msg is written. + **/ +extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int msg ); + +/** + Enable the In/Out DoorBell Interrupt + + InDoorBell interrupt is generated by PCI master and serviced by local processor + local processor needs to enable its inbound doorbell interrupts it wants to handle + + OutDoorbell interrupt is generated by local processor and serviced by PCI master + PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle + **/ +extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ + +/** + Disable the In/Out DoorBell Interrupt + + local processor needs to disable its inbound doorbell interrupts it is not interested + + PCI master needs to disable outbound doorbell interrupts of devices it is not interested + + **/ +extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ + +/** + Read a local indoorbell register, or an outdoorbell of devices. + Reading a doorbell register, the register will be cleared. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, outdoorbell register on the device is read. + Otherwise local in doorbell is read + **/ +extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */ + unsigned int base); /* pcsrbar/eumbbar */ + +/** + Write to a local outdoorbell register, or an indoorbell register of devices. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, in doorbell register on the device is written. + Otherwise local out doorbell is written + **/ +extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int msg ); /* in / out */ + +/** + Read the outbound msg unit interrupt status of devices. Reading an interrupt status register, + the register will be cleared. + + The outbound interrupt status is AND with the outbound + interrupt mask. The result is returned. + + PCI master must pass the pcsrbar to the function. + **/ +extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * ); + +/** + Read the inbound msg unit interrupt status. Reading an interrupt status register, + the register will be cleared. + + The inbound interrupt status is AND with the inbound + interrupt mask. The result is returned. + + Local process must pass its eumbbar to the function. +**/ +extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * ); + +/** + Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR, + MUCR. + **/ +extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar, + QUEUE_SIZE, + unsigned int qba);/* queue base address that must be aligned at 1M */ +/** + Enable the circular queue + **/ +extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar ); + +/** + Disable the circular queue + **/ +extern void I2OFIFODisable( unsigned int eumbbar ); + +/** + Enable the circular queue interrupt + PCI master enables outbound FIFO interrupt of device + Device enables its inbound FIFO interrupt + **/ +extern void I2OFIFOIntEnable( LOCATION, unsigned int base ); + +/** + Disable the circular queue interrupt + PCI master disables outbound FIFO interrupt of device + Device disables its inbound FIFO interrupt + **/ +extern void I2OFIFOIntDisable( LOCATION, unsigned int base ); + +/** + Enable the circular queue overflow interrupt + **/ +extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar ); + +/** + Disable the circular queue overflow interrupt + **/ +extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar ); + +/** + Allocate a free msg frame from free FIFO. + + PCI Master allocates a free msg frame through inbound queue port of device(IFQPR) + while local processor allocates a free msg frame from outbound free queue(OFTPR) + + Unless both free queues are initialized, allocating a free MF will return 0xffffffff + **/ +extern I2OSTATUS I2OFIFOAlloc( LOCATION, + unsigned int base, + void **pMsg); +/** + Free a used msg frame back to free queue + PCI Master frees a MFA through outbound queue port of device(OFQPR) + while local processor frees a MFA into its inbound free queue(IFHPR) + + Used msg frame does not need to be recycled in the order they + read + + This function has to be called by PCI master to initialize Inbound free queue + and by device to initialize Outbound free queue before I2OFIFOAlloc can be used. + **/ +extern I2OSTATUS I2OFIFOFree( LOCATION, + unsigned int base, + void *pMsg ); + +/** + Post a msg into FIFO + PCI Master posts a msg through inbound queue port of device(IFQPR) + while local processor post a msg into its outbound post queue(OPHPR) + + The total number of msg must be less than the max size of the queue + Otherwise queue overflow interrupt will assert. + **/ +extern I2OSTATUS I2OFIFOPost( LOCATION, + unsigned int base, + void *pMsg ); + +/** + Read a msg from FIFO + PCI Master reads a msg through outbound queue port of device(OFQPR) + while local processor reads a msg from its inbound post queue(IPTPR) + **/ +extern I2OSTATUS I2OFIFOGet( LOCATION, + unsigned int base, + void **pMsg ); + +/** + Get the I2O PCI configuration identification register + **/ +extern I2OSTATUS I2OPCIConfigGet( LOCATION, + unsigned int base, + I2OIOP *); + +#endif diff --git a/cpu/mpc824x/drivers/i2o/Makefile b/cpu/mpc824x/drivers/i2o/Makefile new file mode 100644 index 000000000..3f5ca2668 --- /dev/null +++ b/cpu/mpc824x/drivers/i2o/Makefile @@ -0,0 +1,84 @@ +########################################################################## +# +# Copyright Motorola, Inc. 1997 +# ALL RIGHTS RESERVED +# +# You are hereby granted a copyright license to use, modify, and +# distribute the SOFTWARE so long as this entire notice is retained +# without alteration in any modified and/or redistributed versions, +# and that such modified versions are clearly identified as such. +# No licenses are granted by implication, estoppel or otherwise under +# any patents or trademarks of Motorola, Inc. +# +# The SOFTWARE is provided on an "AS IS" basis and without warranty. +# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS +# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED +# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR +# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH +# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS +# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. +# +# To the maximum extent permitted by applicable law, IN NO EVENT SHALL +# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF +# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR +# INABILITY TO USE THE SOFTWARE. +# +############################################################################ +TARGET = libi2o.a + +#DEBUG = -g +DEBUG = +LST = -Hanno -S +OPTIM = +CC = /risc/tools/pkgs/metaware/bin/hcppc +CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc +CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) +PREP = $(CC) $(CFLAGS) -P + +# Assembler used to build the .s files (for the board version) + +ASOPT = -big_si -c +ASDEBUG = -l -fm +AS = /risc/tools/pkgs/metaware/bin/asppc + +# Linker to bring .o files together into an executable. + +LKOPT = -Bbase=0 -Qn -q -r +LKCMD = +LINK = /risc/tools/pkgs/metaware/bin/ldppc $(LKCMD) $(LKOPT) + +# DOS Utilities + +DEL = rm +COPY = cp +LIST = ls + +OBJECTS = i2o1.o i2o2.o + +all: $(TARGET) + +$(TARGET): $(OBJECTS) + $(LINK) $(OBJECTS) -o $@ + +objects: i2o1.o + +clean: + $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) + +.s.o: + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i +# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst + +.c.o: + $(CCobj) $< + +.c.s: + $(CCobj) $(LST) $< + +i2o1.o: i2o.h i2o1.c + +i2o2.o: i2o.h i2o2.s diff --git a/cpu/mpc824x/drivers/i2o/Makefile_pc b/cpu/mpc824x/drivers/i2o/Makefile_pc new file mode 100644 index 000000000..6867f5837 --- /dev/null +++ b/cpu/mpc824x/drivers/i2o/Makefile_pc @@ -0,0 +1,90 @@ +########################################################################## +# +# makefile_pc for use with PC mksnt tools dink32/drivers/i2o +# +# Copyright Motorola, Inc. 1997 +# ALL RIGHTS RESERVED +# +# You are hereby granted a copyright license to use, modify, and +# distribute the SOFTWARE so long as this entire notice is retained +# without alteration in any modified and/or redistributed versions, +# and that such modified versions are clearly identified as such. +# No licenses are granted by implication, estoppel or otherwise under +# any patents or trademarks of Motorola, Inc. +# +# The SOFTWARE is provided on an "AS IS" basis and without warranty. +# To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS +# ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED +# WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR +# PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH +# REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS +# THEREOF) AND ANY ACCOMPANYING WRITTEN MATERIALS. +# +# To the maximum extent permitted by applicable law, IN NO EVENT SHALL +# MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER +# (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF +# BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +# INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR +# INABILITY TO USE THE SOFTWARE. +# +############################################################################ +TARGET = libi2o.a + +#DEBUG = -g +DEBUG = +LST = -Hanno -S +OPTIM = +CC = m:/old_tools/tools/hcppc/bin/hcppc +CFLAGS = -Hnocopyr -c -Hsds -Hon=Char_default_unsigned -Hon=Char_is_rep -I../inc -I/risc/tools/pkgs/metaware/inc +CCobj = $(CC) $(CFLAGS) $(DEBUG) $(OPTIM) +PREP = $(CC) $(CFLAGS) -P + +# Assembler used to build the .s files (for the board version) + +ASOPT = -big_si -c +ASDEBUG = -l -fm +AS = m:/old_tools/tools/hcppc/bin/asppc + +# Linker to bring .o files together into an executable. + +LKOPT = -Bbase=0 -Qn -q -r +LKCMD = +LINK = m:/old_tools/tools/hcppc/bin/ldppc $(LKCMD) $(LKOPT) + +# DOS Utilities + +DEL = rm +COPY = cp +LIST = ls + +OBJECTS = i2o1.o i2o2.o + +all: $(TARGET) + +$(TARGET): $(OBJECTS) + $(LINK) $(OBJECTS) -o $@ + +objects: i2o1.o + +clean: + $(DEL) -f *.o *.i *.map *.lst $(TARGET) $(OBJECTS) + +.s.o: + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i +# $(AS) $(ASOPT) $(ASDEBUG) $*.i > $*.lst + +.c.o: + $(CCobj) $< + +.c.s: + $(CCobj) $(LST) $< + +i2o1.o: i2o.h i2o1.c + $(CCobj) $< + +i2o2.o: i2o.h i2o2.s + $(DEL) -f $*.i + $(PREP) -Hasmcpp $< + $(AS) $(ASOPT) $*.i diff --git a/cpu/mpc824x/drivers/i2o/i2o.h b/cpu/mpc824x/drivers/i2o/i2o.h new file mode 100644 index 000000000..71572b259 --- /dev/null +++ b/cpu/mpc824x/drivers/i2o/i2o.h @@ -0,0 +1,345 @@ +#ifndef I2O_H +#define I2O_H +/********************************************************* + * + * copyright @ Motorola, 1999 + * + *********************************************************/ + +#define I2O_REG_OFFSET 0x0004 + +#define PCI_CFG_CLA 0x0B +#define PCI_CFG_SCL 0x0A +#define PCI_CFG_PIC 0x09 + +#define I2O_IMR0 0x0050 +#define I2O_IMR1 0x0054 +#define I2O_OMR0 0x0058 +#define I2O_OMR1 0x005C + +#define I2O_ODBR 0x0060 +#define I2O_IDBR 0x0068 + +#define I2O_OMISR 0x0030 +#define I2O_OMIMR 0x0034 +#define I2O_IMISR 0x0100 +#define I2O_IMIMR 0x0104 + +/* accessable to PCI master but local processor */ +#define I2O_IFQPR 0x0040 +#define I2O_OFQPR 0x0044 + +/* accessable to local processor */ +#define I2O_IFHPR 0x0120 +#define I2O_IFTPR 0x0128 +#define I2O_IPHPR 0x0130 +#define I2O_IPTPR 0x0138 +#define I2O_OFHPR 0x0140 +#define I2O_OFTPR 0x0148 +#define I2O_OPHPR 0x0150 +#define I2O_OPTPR 0x0158 +#define I2O_MUCR 0x0164 +#define I2O_QBAR 0x0170 + +#define I2O_NUM_MSG 2 + +typedef enum _i2o_status +{ + I2OSUCCESS = 0, + I2OINVALID, + I2OMSGINVALID, + I2ODBINVALID, + I2OQUEINVALID, + I2OQUEEMPTY, + I2OQUEFULL, + I2ONOEVENT, +} I2OSTATUS; + +typedef enum _queue_size +{ + QSIZE_4K = 0x02, + QSIZE_8K = 0x04, + QSIZE_16K = 0x08, + QSIZE_32K = 0x10, + QSIZe_64K = 0x20, +} QUEUE_SIZE; + +typedef enum _location +{ + LOCAL = 0, /* used by local processor to access its own on board device, + local processor's eumbbar is required */ + REMOTE, /* used by PCI master to access the devices on its PCI device, + device's pcsrbar is required */ +} LOCATION; + +/* door bell */ +typedef enum _i2o_in_db +{ + IN_DB = 1, + MC, /* machine check */ +} I2O_IN_DB; + +/* I2O PCI configuration identification */ +typedef struct _i2o_iop +{ + unsigned int base_class : 8; + unsigned int sub_class : 8; + unsigned int prg_code : 8; +} I2OIOP; + +/* I2O Outbound Message Interrupt Status Register */ +typedef struct _i2o_om_stat +{ + unsigned int rsvd0 : 26; + unsigned int opqi : 1; + unsigned int rsvd1 : 1; + unsigned int odi : 1; + unsigned int rsvd2 : 1; + unsigned int om1i : 1; + unsigned int om0i : 1; +} I2OOMSTAT; + +/* I2O inbound Message Interrupt Status Register */ +typedef struct _i2o_im_stat +{ + unsigned int rsvd0 : 23; + unsigned int ofoi : 1; + unsigned int ipoi : 1; + unsigned int rsvd1 : 1; + unsigned int ipqi : 1; + unsigned int mci : 1; + unsigned int idi : 1; + unsigned int rsvd2 : 1; + unsigned int im1i : 1; + unsigned int im0i : 1; +} I2OIMSTAT; + +/** + Enable the interrupt associated with in/out bound msg + + Inbound message interrupt generated by PCI master and serviced by local processor + local processor needs to enable its inbound interrupts it wants to handle (LOCAL) + + Outbound message interrupt generated by local processor and serviced by PCI master + PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE) + **/ +extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ); /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ + +/** + Disable the interrupt associated with in/out bound msg + + local processor needs to disable its inbound interrupts it is not interested (LOCAL) + + PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE) + **/ +extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ); /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ + +/** + Read the msg register either from local inbound msg 0/1, + or an outbound msg 0/1 of devices. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, outbound msg of the device is read. + Otherwise local inbound msg is read. + **/ +extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int *msg ); + +/** + Write to nth Msg register either on local outbound msg 0/1, + or aninbound msg 0/1 of devices + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, inbound msg on the device is written. + Otherwise local outbound msg is written. + **/ +extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int msg ); + +/** + Enable the In/Out DoorBell Interrupt + + InDoorBell interrupt is generated by PCI master and serviced by local processor + local processor needs to enable its inbound doorbell interrupts it wants to handle + + OutDoorbell interrupt is generated by local processor and serviced by PCI master + PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle + **/ +extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ + +/** + Disable the In/Out DoorBell Interrupt + + local processor needs to disable its inbound doorbell interrupts it is not interested + + PCI master needs to disable outbound doorbell interrupts of devices it is not interested + + **/ +extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ + +/** + Read a local indoorbell register, or an outdoorbell of devices. + Reading a doorbell register, the register will be cleared. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, outdoorbell register on the device is read. + Otherwise local in doorbell is read + **/ +extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */ + unsigned int base); /* pcsrbar/eumbbar */ + +/** + Write to a local outdoorbell register, or an indoorbell register of devices. + + If it is not local, pcsrbar must be passed to the function. + Otherwise eumbbar is passed. + + If it is remote, in doorbell register on the device is written. + Otherwise local out doorbell is written + **/ +extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int msg ); /* in / out */ + +/** + Read the outbound msg unit interrupt status of devices. Reading an interrupt status register, + the register will be cleared. + + The outbound interrupt status is AND with the outbound + interrupt mask. The result is returned. + + PCI master must pass the pcsrbar to the function. + **/ +extern I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT * ); + +/** + Read the inbound msg unit interrupt status. Reading an interrupt status register, + the register will be cleared. + + The inbound interrupt status is AND with the inbound + interrupt mask. The result is returned. + + Local process must pass its eumbbar to the function. +**/ +extern I2OSTATUS I2OInMsgStatGet( unsigned int eumbbar, I2OIMSTAT * ); + +/** + Configure the I2O FIFO, including QBAR, IFHPR/IFTPR,IPHPR/IPTPR,OFHPR/OFTPR, OPHPR/OPTPR, + MUCR. + **/ +extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar, + QUEUE_SIZE, + unsigned int qba);/* queue base address that must be aligned at 1M */ +/** + Enable the circular queue + **/ +extern I2OSTATUS I2OFIFOEnable( unsigned int eumbbar ); + +/** + Disable the circular queue + **/ +extern void I2OFIFODisable( unsigned int eumbbar ); + +/** + Enable the circular queue interrupt + PCI master enables outbound FIFO interrupt of device + Device enables its inbound FIFO interrupt + **/ +extern void I2OFIFOIntEnable( LOCATION, unsigned int base ); + +/** + Disable the circular queue interrupt + PCI master disables outbound FIFO interrupt of device + Device disables its inbound FIFO interrupt + **/ +extern void I2OFIFOIntDisable( LOCATION, unsigned int base ); + +/** + Enable the circular queue overflow interrupt + **/ +extern void I2OFIFOOverflowIntEnable( unsigned int eumbbar ); + +/** + Disable the circular queue overflow interrupt + **/ +extern void I2OFIFOOverflowIntDisable( unsigned int eumbbar ); + +/** + Allocate a free msg frame from free FIFO. + + PCI Master allocates a free msg frame through inbound queue port of device(IFQPR) + while local processor allocates a free msg frame from outbound free queue(OFTPR) + + Unless both free queues are initialized, allocating a free MF will return 0xffffffff + **/ +extern I2OSTATUS I2OFIFOAlloc( LOCATION, + unsigned int base, + void **pMsg); +/** + Free a used msg frame back to free queue + PCI Master frees a MFA through outbound queue port of device(OFQPR) + while local processor frees a MFA into its inbound free queue(IFHPR) + + Used msg frame does not need to be recycled in the order they + read + + This function has to be called by PCI master to initialize Inbound free queue + and by device to initialize Outbound free queue before I2OFIFOAlloc can be used. + **/ +extern I2OSTATUS I2OFIFOFree( LOCATION, + unsigned int base, + void *pMsg ); + +/** + Post a msg into FIFO + PCI Master posts a msg through inbound queue port of device(IFQPR) + while local processor post a msg into its outbound post queue(OPHPR) + + The total number of msg must be less than the max size of the queue + Otherwise queue overflow interrupt will assert. + **/ +extern I2OSTATUS I2OFIFOPost( LOCATION, + unsigned int base, + void *pMsg ); + +/** + Read a msg from FIFO + PCI Master reads a msg through outbound queue port of device(OFQPR) + while local processor reads a msg from its inbound post queue(IPTPR) + **/ +extern I2OSTATUS I2OFIFOGet( LOCATION, + unsigned int base, + void **pMsg ); + +/** + Get the I2O PCI configuration identification register + **/ +extern I2OSTATUS I2OPCIConfigGet( LOCATION, + unsigned int base, + I2OIOP *); + +#endif diff --git a/cpu/mpc824x/drivers/i2o/i2o1.c b/cpu/mpc824x/drivers/i2o/i2o1.c new file mode 100644 index 000000000..f058151c8 --- /dev/null +++ b/cpu/mpc824x/drivers/i2o/i2o1.c @@ -0,0 +1,890 @@ +/********************************************************* + * $Id + * + * copyright @ Motorola, 1999 + *********************************************************/ +#include "i2o.h" + +extern unsigned int load_runtime_reg( unsigned int eumbbar, unsigned int reg ); +#pragma Alias( load_runtime_reg, "load_runtime_reg" ); + +extern void store_runtime_reg( unsigned int eumbbar, unsigned int reg, unsigned int val ); +#pragma Alias( store_runtime_reg, "store_runtime_reg" ); + +typedef struct _fifo_stat +{ + QUEUE_SIZE qsz; + unsigned int qba; +} FIFOSTAT; + +FIFOSTAT fifo_stat = { QSIZE_4K, 0xffffffff }; + +/********************************************************************************** + * function: I2OMsgEnable + * + * description: Enable the interrupt associated with in/out bound msg + * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID. + * + * All previously enabled interrupts are preserved. + * note: + * Inbound message interrupt generated by PCI master and serviced by local processor + * Outbound message interrupt generated by local processor and serviced by PCI master + * + * local processor needs to enable its inbound interrupts it wants to handle(LOCAL) + * PCI master needs to enable the outbound interrupts of devices it wants to handle(REMOTE) + ************************************************************************************/ +I2OSTATUS I2OMsgEnable ( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ) /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ +{ + unsigned int reg, val; + if ( ( n & 0x3 ) == 0 ) + { + /* neither msg 0, nor msg 1 */ + return I2OMSGINVALID; + } + + n = (~n) & 0x3; + /* LOCATION - REMOTE : enable outbound message of device, pcsrbar as base + * LOCAL : enable local inbound message, eumbbar as base + */ + reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); + val = load_runtime_reg( base, reg ); + + val &= 0xfffffffc; /* masked out the msg interrupt bits */ + val |= n; /* LSB are the one we want */ + store_runtime_reg( base, reg, val ); + + return I2OSUCCESS; +} + +/********************************************************************************* + * function: I2OMsgDisable + * + * description: Disable the interrupt associated with in/out bound msg + * Other previously enabled interrupts are preserved. + * return I2OSUCCESS if no error otherwise return I2OMSGINVALID + * + * note: + * local processor needs to disable its inbound interrupts it is not interested(LOCAL) + * PCI master needs to disable outbound interrupts of devices it is not interested(REMOTE) + *********************************************************************************/ +I2OSTATUS I2OMsgDisable( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned char n ) /* b'1' - msg 0 + * b'10'- msg 1 + * b'11'- both + */ +{ + unsigned int reg, val; + + if ( ( n & 0x3 ) == 0 ) + { + /* neither msg 0, nor msg 1 */ + return I2OMSGINVALID; + } + + /* LOCATION - REMOTE : disable outbound message interrupt of device, pcsrbar as base + * LOCAL : disable local inbound message interrupt, eumbbar as base + */ + reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); + val = load_runtime_reg( base, reg ); + + val &= 0xfffffffc; /* masked out the msg interrupt bits */ + val |= ( n & 0x3 ); + store_runtime_reg( base, reg, val ); + + return I2OSUCCESS; + +} + +/************************************************************************** + * function: I2OMsgGet + * + * description: Local processor reads the nth Msg register from its inbound msg, + * or a PCI Master reads nth outbound msg from device + * + * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID. + * + * note: + * If it is not local, pcsrbar must be passed to the function. Otherwise eumbbar is passed. + * If it is remote, outbound msg on the device is read; otherwise local inbound msg is read + *************************************************************************/ +I2OSTATUS I2OMsgGet ( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int *msg ) +{ + if ( n >= I2O_NUM_MSG || msg == 0 ) + { + return I2OMSGINVALID; + } + + if ( loc == REMOTE ) + { + /* read the outbound msg of the device, pcsrbar as base */ + *msg = load_runtime_reg( base, I2O_OMR0+n*I2O_REG_OFFSET ); + } + else + { + /* read the inbound msg sent by PCI master, eumbbar as base */ + *msg = load_runtime_reg( base, I2O_IMR0+n*I2O_REG_OFFSET ); + } + + return I2OSUCCESS; +} + +/*************************************************************** + * function: I2OMsgPost + * + * description: Kahlua writes to its nth outbound msg register + * PCI master writes to nth inbound msg register of device + * + * return I2OSUCCESS if no error, otherwise return I2OMSGINVALID. + * + * note: + * If it is not local, pcsrbar must be passed to the function. Otherwise eumbbar is passed. + * + * If it is remote, inbound msg on the device is written; otherwise local outbound msg is written + ***************************************************************/ +I2OSTATUS I2OMsgPost( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /*pcsrbar/eumbbar */ + unsigned int n, /* 0 or 1 */ + unsigned int msg ) +{ + if ( n >= I2O_NUM_MSG ) + { + return I2OMSGINVALID; + } + + if ( loc == REMOTE ) + { + /* write to the inbound msg register of the device, pcsrbar as base */ + store_runtime_reg( base, I2O_IMR0+n*I2O_REG_OFFSET, msg ); + } + else + { + /* write to the outbound msg register for PCI master to read, eumbbar as base */ + store_runtime_reg( base, I2O_OMR0+n*I2O_REG_OFFSET, msg ); + } + + return I2OSUCCESS; +} + +/*********************************************************************** + * function: I2ODBEnable + * + * description: Local processor enables it's inbound doorbell interrupt + * PCI master enables outbound doorbell interrupt of devices + * Other previously enabled interrupts are preserved. + * Return I2OSUCCESS if no error otherwise return I2ODBINVALID + * + * note: + * In DoorBell interrupt is generated by PCI master and serviced by local processor + * Out Doorbell interrupt is generated by local processor and serviced by PCI master + * + * Out Doorbell interrupt is generated by local processor and serviced by PCI master + * PCI master needs to enable the outbound doorbell interrupts of device it wants to handle + **********************************************************************/ +I2OSTATUS I2ODBEnable( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ +{ + + /* LOCATION - REMOTE : PCI master initializes outbound doorbell message of device + * LOCAL : Kahlua initializes its inbound doorbell message + */ + unsigned int val; + + if ( loc == LOCAL && ( in_db & 0x3 ) == 0 ) + { + return I2ODBINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is base */ + val = load_runtime_reg( base, I2O_OMIMR ); + val &= 0xfffffff7; + store_runtime_reg( base, I2O_OMIMR , val ); + } + else + { + /* eumbbar is base */ + val = load_runtime_reg( base, I2O_IMIMR); + in_db = ( (~in_db) & 0x3 ) << 3; + val = ( val & 0xffffffe7) | in_db; + store_runtime_reg( base, I2O_IMIMR, val ); + } + + return I2OSUCCESS; +} + +/********************************************************************************** + * function: I2ODBDisable + * + * description: local processor disables its inbound DoorBell Interrupt + * PCI master disables outbound DoorBell interrupt of device + * Other previously enabled interrupts are preserved. + * return I2OSUCCESS if no error.Otherwise return I2ODBINVALID + * + * note: + * local processor needs to disable its inbound doorbell interrupts it is not interested + * + * PCI master needs to disable outbound doorbell interrupts of device it is not interested + ************************************************************************************/ +I2OSTATUS I2ODBDisable( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */ +{ + /* LOCATION - REMOTE : handle device's out bound message initialization + * LOCAL : handle local in bound message initialization + */ + unsigned int val; + + if ( loc == LOCAL && ( in_db & 0x3 ) == 0 ) + { + return I2ODBINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is the base */ + val = load_runtime_reg( base, I2O_OMIMR ); + val |= 0x8; + store_runtime_reg( base, I2O_OMIMR, val ); + } + else + { + val = load_runtime_reg( base, I2O_IMIMR); + in_db = ( in_db & 0x3 ) << 3; + val |= in_db; + store_runtime_reg( base, I2O_IMIMR, val ); + } + + return I2OSUCCESS; +} + +/********************************************************************************** + * function: I2ODBGet + * + * description: Local processor reads its in doorbell register, + * PCI master reads the outdoorbell register of device. + * After a doorbell register is read, the whole register will be cleared. + * Otherwise, HW keeps generating interrupt. + * + * note: + * If it is not local, pcsrbar must be passed to the function. + * Otherwise eumbbar is passed. + * + * If it is remote, out doorbell register on the device is read. + * Otherwise local in doorbell is read + * + * If the register is not cleared by write to it, any remaining bit of b'1's + * will cause interrupt pending. + *********************************************************************************/ +unsigned int I2ODBGet( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base) /* pcsrbar/eumbbar */ +{ + unsigned int msg, val; + + if ( loc == REMOTE ) + { + /* read outbound doorbell register of device, pcsrbar is the base */ + val = load_runtime_reg( base, I2O_ODBR ); + msg = val & 0xe0000000; + store_runtime_reg( base, I2O_ODBR, val ); /* clear the register */ + } + else + { + /* read the inbound doorbell register, eumbbar is the base */ + val = load_runtime_reg( base, I2O_IDBR ); + store_runtime_reg( base, I2O_IDBR, val ); /* clear the register */ + msg = val; + } + + return msg; +} + +/********************************************************************** + * function: I2ODBPost + * + * description: local processor writes to a outbound doorbell register, + * PCI master writes to the inbound doorbell register of device + * + * note: + * If it is not local, pcsrbar must be passed to the function. + * Otherwise eumbbar is passed. + * + * If it is remote, in doorbell register on the device is written. + * Otherwise local out doorbell is written + *********************************************************************/ +void I2ODBPost( LOCATION loc, /* REMOTE/LOCAL */ + unsigned int base, /* pcsrbar/eumbbar */ + unsigned int msg ) /* in / out */ +{ + if ( loc == REMOTE ) + { + /* write to inbound doorbell register of device, pcsrbar is the base */ + store_runtime_reg( base, I2O_IDBR, msg ); + } + else + { + /* write to local outbound doorbell register, eumbbar is the base */ + store_runtime_reg( base, I2O_ODBR, msg & 0x1fffffff ); + } + +} + +/******************************************************************** + * function: I2OOutMsgStatGet + * + * description: PCI master reads device's outbound msg unit interrupt status. + * Reading an interrupt status register, + * the register will be cleared. + * + * The value of the status register is AND with the outbound + * interrupt mask and result is returned. + * + * note: + * pcsrbar must be passed to the function. + ********************************************************************/ +I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT *val ) +{ + unsigned int stat; + unsigned int mask; + + if ( val == 0 ) + { + return I2OINVALID; + } + + /* read device's outbound status */ + stat = load_runtime_reg( pcsrbar, I2O_OMISR ); + mask = load_runtime_reg( pcsrbar, I2O_OMIMR ); + store_runtime_reg( pcsrbar, I2O_OMISR, stat & 0xffffffd7); + + stat &= mask; + val->rsvd0 = ( stat & 0xffffffc0 ) >> 6; + val->opqi = ( stat & 0x00000020 ) >> 5; + val->rsvd1 = ( stat & 0x00000010 ) >> 4; + val->odi = ( stat & 0x00000008 ) >> 3; + val->rsvd2 = ( stat & 0x00000004 ) >> 2; + val->om1i = ( stat & 0x00000002 ) >> 1; + val->om0i = ( stat & 0x00000001 ); + + return I2OSUCCESS; +} + +/******************************************************************** + * function: I2OInMsgStatGet + * + * description: Local processor reads its inbound msg unit interrupt status. + * Reading an interrupt status register, + * the register will be cleared. + * + * The inbound msg interrupt status is AND with the inbound + * msg interrupt mask and result is returned. + * + * note: + * eumbbar must be passed to the function. + ********************************************************************/ +I2OSTATUS I2OInMsgStatGet(unsigned int eumbbar, I2OIMSTAT *val) +{ + unsigned int stat; + unsigned int mask; + + if ( val == 0 ) + { + return I2OINVALID; + } + + /* read device's outbound status */ + stat = load_runtime_reg( eumbbar, I2O_OMISR ); + mask = load_runtime_reg( eumbbar, I2O_OMIMR ); + store_runtime_reg( eumbbar, I2O_OMISR, stat & 0xffffffe7 ); + + stat &= mask; + val->rsvd0 = ( stat & 0xfffffe00 ) >> 9; + val->ofoi = ( stat & 0x00000100 ) >> 8; + val->ipoi = ( stat & 0x00000080 ) >> 7; + val->rsvd1 = ( stat & 0x00000040 ) >> 6; + val->ipqi = ( stat & 0x00000020 ) >> 5; + val->mci = ( stat & 0x00000010 ) >> 4; + val->idi = ( stat & 0x00000008 ) >> 3; + val->rsvd2 = ( stat & 0x00000004 ) >> 2; + val->im1i = ( stat & 0x00000002 ) >> 1; + val->im0i = ( stat & 0x00000001 ); + + return I2OSUCCESS; + +} + +/*********************************************************** + * function: I2OFIFOInit + * + * description: Configure the I2O FIFO, including QBAR, + * IFHPR/IFTPR, IPHPR/IPTPR, OFHPR/OFTPR, + * OPHPR/OPTPR, MUCR. + * + * return I2OSUCCESS if no error, + * otherwise return I2OQUEINVALID + * + * note: It is NOT this driver's responsibility of initializing + * MFA blocks, i.e., FIFO queue itself. The MFA blocks + * must be initialized before I2O unit can be used. + ***********************************************************/ +I2OSTATUS I2OFIFOInit( unsigned int eumbbar, + QUEUE_SIZE sz, /* value of CQS of MUCR */ + unsigned int qba) /* queue base address that must be aligned at 1M */ +{ + + if ( ( qba & 0xfffff ) != 0 ) + { + /* QBA must be aligned at 1Mbyte boundary */ + return I2OQUEINVALID; + } + + store_runtime_reg( eumbbar, I2O_QBAR, qba ); + store_runtime_reg( eumbbar, I2O_MUCR, (unsigned int)sz ); + store_runtime_reg( eumbbar, I2O_IFHPR, qba ); + store_runtime_reg( eumbbar, I2O_IFTPR, qba ); + store_runtime_reg( eumbbar, I2O_IPHPR, qba + 1 * ( sz << 11 )); + store_runtime_reg( eumbbar, I2O_IPTPR, qba + 1 * ( sz << 11 )); + store_runtime_reg( eumbbar, I2O_OFHPR, qba + 2 * ( sz << 11 )); + store_runtime_reg( eumbbar, I2O_OFTPR, qba + 2 * ( sz << 11 )); + store_runtime_reg( eumbbar, I2O_OPHPR, qba + 3 * ( sz << 11 )); + store_runtime_reg( eumbbar, I2O_OPTPR, qba + 3 * ( sz << 11 )); + + fifo_stat.qsz = sz; + fifo_stat.qba = qba; + + return I2OSUCCESS; +} + +/************************************************** + * function: I2OFIFOEnable + * + * description: Enable the circular queue + * return I2OSUCCESS if no error. + * Otherwise I2OQUEINVALID is returned. + * + * note: + *************************************************/ +I2OSTATUS I2OFIFOEnable( unsigned int eumbbar ) +{ + unsigned int val; + + if ( fifo_stat.qba == 0xfffffff ) + { + return I2OQUEINVALID; + } + + val = load_runtime_reg( eumbbar, I2O_MUCR ); + store_runtime_reg( eumbbar, I2O_MUCR, val | 0x1 ); + + return I2OSUCCESS; +} + +/************************************************** + * function: I2OFIFODisable + * + * description: Disable the circular queue + * + * note: + *************************************************/ +void I2OFIFODisable( unsigned int eumbbar ) +{ + if ( fifo_stat.qba == 0xffffffff ) + { + /* not enabled */ + return; + } + + unsigned int val = load_runtime_reg( eumbbar, I2O_MUCR ); + store_runtime_reg( eumbbar, I2O_MUCR, val & 0xfffffffe ); +} + +/**************************************************** + * function: I2OFIFOAlloc + * + * description: Allocate a free MFA from free FIFO. + * return I2OSUCCESS if no error. + * return I2OQUEEMPTY if no more free MFA. + * return I2OINVALID on other errors. + * + * A free MFA must be allocated before a + * message can be posted. + * + * note: + * PCI Master allocates a free MFA from inbound queue of device + * (pcsrbar is the base,) through the inbound queue port of device + * while local processor allocates a free MFA from its outbound + * queue (eumbbar is the base.) + * + ****************************************************/ +I2OSTATUS I2OFIFOAlloc( LOCATION loc, + unsigned int base, + void **pMsg ) +{ + I2OSTATUS stat = I2OSUCCESS; + void *pHdr, *pTil; + + if ( pMsg == 0 || *pMsg == 0 || fifo_stat.qba == 0xffffffff ) + { + /* not configured */ + return I2OQUEINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is the base and read the inbound free tail ptr */ + pTil = (void *)load_runtime_reg( base, I2O_IFQPR ); + if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF ) + { + stat = I2OQUEEMPTY; + } + else + { + *pMsg = pTil; + } + } + else + { + /* eumbbar is the base and read the outbound free tail ptr */ + pHdr = (void *)load_runtime_reg( base, I2O_OFHPR ); /* queue head */ + pTil = (void *)load_runtime_reg( base, I2O_OFTPR ); /* queue tail */ + + /* check underflow */ + if ( pHdr == pTil ) + { + /* hdr and til point to the same fifo item, no free MFA */ + stat = I2OQUEEMPTY; + } + else + { + /* update OFTPR */ + *pMsg = (void *)(*(unsigned char *)pTil); + pTil = (void *)((unsigned int)pTil + 4); + if ( (unsigned int)pTil == fifo_stat.qba + ( 4 * ( fifo_stat.qsz << 11 ) ) ) + { + /* reach the upper limit */ + pTil = (void *)(fifo_stat.qba + ( 3 * (fifo_stat.qsz << 11) )); + } + store_runtime_reg( base, I2O_OFTPR, (unsigned int)pTil ); + } + } + + return stat; +} + +/****************************************************** + * function: I2OFIFOFree + * + * description: Free a used MFA back to free queue after + * use. + * return I2OSUCCESS if no error. + * return I2OQUEFULL if inbound free queue + * overflow + * + * note: PCI Master frees a MFA into device's outbound queue + * (OFQPR) while local processor frees a MFA into its + * inbound queue (IFHPR). + *****************************************************/ +I2OSTATUS I2OFIFOFree( LOCATION loc, + unsigned int base, + void *pMsg ) +{ + void **pHdr, **pTil; + I2OSTATUS stat = I2OSUCCESS; + + if ( fifo_stat.qba == 0xffffffff || pMsg == 0 ) + { + return I2OQUEINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is the base */ + store_runtime_reg( base, I2O_OFQPR, (unsigned int)pMsg ); + } + else + { + /* eumbbar is the base */ + pHdr = (void **)load_runtime_reg( base, I2O_IFHPR ); + pTil = (void **)load_runtime_reg( base, I2O_IFTPR ); + + /* store MFA */ + *pHdr = pMsg; + + /* update IFHPR */ + pHdr += 4; + + if ( (unsigned int)pHdr == fifo_stat.qba + ( fifo_stat.qsz << 11 ) ) + { + /* reach the upper limit */ + pHdr = (void **)fifo_stat.qba; + } + + /* check inbound free queue overflow */ + if ( pHdr != pTil ) + { + store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr); + } + else + { + stat = I2OQUEFULL; + } + + } + + return stat; + +} + +/********************************************* + * function: I2OFIFOPost + * + * description: Post a msg into FIFO post queue + * the value of msg must be the one + * returned by I2OFIFOAlloc + * + * note: PCI Master posts a msg into device's inbound queue + * (IFQPR) while local processor post a msg into device's + * outbound queue (OPHPR) + *********************************************/ +I2OSTATUS I2OFIFOPost( LOCATION loc, + unsigned int base, + void *pMsg ) +{ + void **pHdr, **pTil; + I2OSTATUS stat = I2OSUCCESS; + + if ( fifo_stat.qba == 0xffffffff || pMsg == 0 ) + { + return I2OQUEINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is the base */ + store_runtime_reg( base, I2O_IFQPR, (unsigned int)pMsg ); + } + else + { + /* eumbbar is the base */ + pHdr = (void **)load_runtime_reg( base, I2O_OPHPR ); + pTil = (void **)load_runtime_reg( base, I2O_OPTPR ); + + /* store MFA */ + *pHdr = pMsg; + + /* update IFHPR */ + pHdr += 4; + + if ( (unsigned int)pHdr == fifo_stat.qba + 3 * ( fifo_stat.qsz << 11 ) ) + { + /* reach the upper limit */ + pHdr = (void **)(fifo_stat.qba + 2 * ( fifo_stat.qsz << 11 ) ); + } + + /* check post queue overflow */ + if ( pHdr != pTil ) + { + store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr); + } + else + { + stat = I2OQUEFULL; + } + } + + return stat; +} + +/************************************************ + * function: I2OFIFOGet + * + * description: Read a msg from FIFO + * This function should be called + * only when there is a corresponding + * msg interrupt. + * + * note: PCI Master reads a msg from device's outbound queue + * (OFQPR) while local processor reads a msg from device's + * inbound queue (IPTPR) + ************************************************/ +I2OSTATUS I2OFIFOGet( LOCATION loc, + unsigned int base, + void **pMsg ) +{ + I2OSTATUS stat = I2OSUCCESS; + void *pHdr, *pTil; + + if ( pMsg == 0 || *pMsg == 0 || fifo_stat.qba == 0xffffffff ) + { + /* not configured */ + return I2OQUEINVALID; + } + + if ( loc == REMOTE ) + { + /* pcsrbar is the base */ + pTil = (void *)load_runtime_reg( base, I2O_OFQPR ); + if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF ) + { + stat = I2OQUEEMPTY; + } + else + { + *pMsg = pTil; + } + } + else + { + /* eumbbar is the base and read the outbound free tail ptr */ + pHdr = (void *)load_runtime_reg( base, I2O_IPHPR ); /* queue head */ + pTil = (void *)load_runtime_reg( base, I2O_IPTPR ); /* queue tail */ + + /* check underflow */ + if ( pHdr == pTil ) + { + /* no free MFA */ + stat = I2OQUEEMPTY; + } + else + { + /* update OFTPR */ + *pMsg = (void *)(*(unsigned char *)pTil); + pTil = (void *)((unsigned int)pTil + 4); + if ( (unsigned int)pTil == fifo_stat.qba + 2 * ( fifo_stat.qsz << 11 ) ) + { + /* reach the upper limit */ + pTil = (void *)(fifo_stat.qba + 1 * (fifo_stat.qsz << 11) ); + } + + store_runtime_reg( base, I2O_IPTPR, (unsigned int)pTil ); + } + } + + return stat; +} + +/******************************************************** + * function: I2OIOP + * + * description: Get the I2O PCI configuration identification + * register. + * + * note: PCI master should pass pcsrbar while local processor + * should pass eumbbar. + *********************************************************/ +I2OSTATUS I2OPCIConfigGet( LOCATION loc, + unsigned int base, + I2OIOP * val) +{ + unsigned int tmp; + if ( val == 0 ) + { + return I2OINVALID; + } + tmp = load_runtime_reg( base, PCI_CFG_CLA ); + val->base_class = ( tmp & 0xFF) << 16; + tmp = load_runtime_reg( base, PCI_CFG_SCL ); + val->sub_class= ( (tmp & 0xFF) << 8 ); + tmp = load_runtime_reg( base, PCI_CFG_PIC ); + val->prg_code = (tmp & 0xFF); + return I2OSUCCESS; +} + +/********************************************************* + * function: I2OFIFOIntEnable + * + * description: Enable the circular post queue interrupt + * + * note: + * PCI master enables outbound FIFO interrupt of device + * pscrbar is the base + * Device enables its inbound FIFO interrupt + * eumbbar is the base + *******************************************************/ +void I2OFIFOIntEnable( LOCATION loc, unsigned int base ) +{ + unsigned int reg, val; + + /* LOCATION - REMOTE : enable outbound message of device, pcsrbar as base + * LOCAL : enable local inbound message, eumbbar as base + */ + reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); + val = load_runtime_reg( base, reg ); + + val &= 0xffffffdf; /* clear the msg interrupt bits */ + store_runtime_reg( base, reg, val ); + +} + +/**************************************************** + * function: I2OFIFOIntDisable + * + * description: Disable the circular post queue interrupt + * + * note: + * PCI master disables outbound FIFO interrupt of device + * (pscrbar is the base) + * Device disables its inbound FIFO interrupt + * (eumbbar is the base) + *****************************************************/ +void I2OFIFOIntDisable( LOCATION loc, unsigned int base ) +{ + + /* LOCATION - REMOTE : disable outbound message interrupt of device, pcsrbar as base + * LOCAL : disable local inbound message interrupt, eumbbar as base + */ + unsigned int reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR ); + unsigned int val = load_runtime_reg( base, reg ); + + val |= 0x00000020; /* masked out the msg interrupt bits */ + store_runtime_reg( base, reg, val ); + +} + +/********************************************************* + * function: I2OFIFOOverflowIntEnable + * + * description: Enable the circular queue overflow interrupt + * + * note: + * Device enables its inbound FIFO post overflow interrupt + * and outbound free overflow interrupt. + * eumbbar is the base + *******************************************************/ +void I2OFIFOOverflowIntEnable( unsigned int eumbbar ) +{ + unsigned int val = load_runtime_reg( eumbbar, I2O_IMIMR ); + + val &= 0xfffffe7f; /* clear the two overflow interrupt bits */ + store_runtime_reg( eumbbar, I2O_IMIMR, val ); + +} + +/**************************************************** + * function: I2OFIFOOverflowIntDisable + * + * description: Disable the circular queue overflow interrupt + * + * note: + * Device disables its inbound post FIFO overflow interrupt + * and outbound free FIFO overflow interrupt + * (eumbbar is the base) + *****************************************************/ +void I2OFIFOOverflowIntDisable( unsigned int eumbbar ) +{ + + unsigned int val = load_runtime_reg( eumbbar, I2O_IMIMR ); + + val |= 0x00000180; /* masked out the msg overflow interrupt bits */ + store_runtime_reg( eumbbar, I2O_IMIMR, val ); +} diff --git a/cpu/mpc824x/drivers/i2o/i2o2.S b/cpu/mpc824x/drivers/i2o/i2o2.S new file mode 100644 index 000000000..990f9ef9a --- /dev/null +++ b/cpu/mpc824x/drivers/i2o/i2o2.S @@ -0,0 +1,47 @@ +/************************************** + * + * copyright @ Motorola, 1999 + * + **************************************/ + +/********************************************************** + * function: load_runtime_reg + * + * input: r3 - value of eumbbar + * r4 - register offset in embedded utility space + * + * output: r3 - register content + **********************************************************/ + .text + .align 2 + .global load_runtime_reg + +load_runtime_reg: + + xor r5,r5,r5 + or r5,r5,r3 /* save eumbbar */ + + lwbrx r3,r4,r5 + sync + + bclr 20, 0 + +/**************************************************************** + * function: store_runtime_reg + * + * input: r3 - value of eumbbar + * r4 - register offset in embedded utility space + * r5 - new value to be stored + * + ****************************************************************/ + .text + .align 2 + .global store_runtime_reg +store_runtime_reg: + + xor r0,r0,r0 + + stwbrx r5, r4, r3 + sync + + bclr 20,0 diff --git a/cpu/mpc824x/interrupts.c b/cpu/mpc824x/interrupts.c index 4359ecc05..acb8947e0 100644 --- a/cpu/mpc824x/interrupts.c +++ b/cpu/mpc824x/interrupts.c @@ -86,7 +86,7 @@ void irq_free_handler (int vec) vga? */ -void timer_interrupt_cpu (struct pt_regs *regs) +void timer_interrupt_cpu (struct pt_regs *regs, ulong timestamp) { /* nothing to do here */ return; diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index 784edc36a..9ff052c3b 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -220,7 +220,7 @@ _start_of_vectors: /* Alignment exception. */ . = EXC_OFF_ALIGN Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -238,7 +238,7 @@ Alignment: /* Program check exception */ . = EXC_OFF_PROGRAM ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc824x/traps.c b/cpu/mpc824x/traps.c index 0a7243020..071d003f8 100644 --- a/cpu/mpc824x/traps.c +++ b/cpu/mpc824x/traps.c @@ -175,7 +175,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -185,7 +185,7 @@ DebugException(struct pt_regs *regs) printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc8260/Makefile b/cpu/mpc8260/Makefile index 80d785229..b4c269f9c 100644 --- a/cpu/mpc8260/Makefile +++ b/cpu/mpc8260/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,27 +23,23 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o kgdb.o -COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ +OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \ bedbug_603e.o pci.o spi.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(obj)kgdb.o + $(AR) crv $@ $(OBJS) kgdb.o ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/mpc8260/bedbug_603e.c b/cpu/mpc8260/bedbug_603e.c index f1be485e8..be09cfb5c 100644 --- a/cpu/mpc8260/bedbug_603e.c +++ b/cpu/mpc8260/bedbug_603e.c @@ -10,8 +10,7 @@ #include #include -#if defined(CONFIG_CMD_BEDBUG) \ - && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && (defined(CONFIG_MPC824X) || defined(CONFIG_MPC8260)) #define MAX_BREAK_POINTS 1 diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk index 2cb027093..dd7a71fdf 100644 --- a/cpu/mpc8260/config.mk +++ b/cpu/mpc8260/config.mk @@ -23,8 +23,5 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \ +PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc8260/u-boot.lds diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index 4d5d141ea..4f23012b7 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -47,18 +47,8 @@ #include #include -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#include -#endif - DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_GET_CPU_STR_F) -extern int get_cpu_str_f (char *buf); -#endif - int checkcpu (void) { volatile immap_t *immap = (immap_t *) CFG_IMMR; @@ -91,12 +81,7 @@ int checkcpu (void) if ((immr & IMMR_ISB_MSK) != CFG_IMMR) return -1; /* whoops! someone moved the IMMR */ -#if defined(CONFIG_GET_CPU_STR_F) - get_cpu_str_f (buf); - printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev); -#else printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev); -#endif /* * the bottom 16 bits of the immr are the Part Number and Mask Number @@ -300,18 +285,3 @@ void watchdog_reset (void) #endif /* CONFIG_WATCHDOG */ /* ------------------------------------------------------------------------- */ -#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) -void ft_cpu_setup (void *blob, bd_t *bd) -{ - char * cpu_path = "/cpus/" OF_CPU; - -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) - fdt_fixup_ethernet(blob, bd); -#endif - - do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1); - do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); -} -#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c index 36fc1eba5..640026be5 100644 --- a/cpu/mpc8260/cpu_init.c +++ b/cpu/mpc8260/cpu_init.c @@ -28,10 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -extern unsigned long board_get_cpu_clk_f (void); -#endif - static void config_8260_ioports (volatile immap_t * immr) { int portnum; @@ -94,7 +90,6 @@ static void config_8260_ioports (volatile immap_t * immr) } } -#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask)) /* * Breath some life into the CPU... * @@ -106,9 +101,6 @@ void cpu_init_f (volatile immap_t * immr) { #if !defined(CONFIG_COGENT) /* done in start.S for the cogent */ uint sccr; -#endif -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) - unsigned long cpu_clk; #endif volatile memctl8260_t *memctl = &immr->im_memctl; extern void m8260_cpm_reset (void); @@ -127,27 +119,10 @@ void cpu_init_f (volatile immap_t * immr) immr->im_clkrst.car_rmr = CFG_RMR; /* BCR - Bus Configuration Register (4-25) */ -#if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE) - if (immr->im_siu_conf.sc_bcr & BCR_EBM) { - immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_60x, 0x80000010); - } else { - immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_SINGLE, 0x80000010); - } -#else immr->im_siu_conf.sc_bcr = CFG_BCR; -#endif /* SIUMCR - contains debug pin configuration (4-31) */ -#if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH) - cpu_clk = board_get_cpu_clk_f (); - if (cpu_clk >= 100000000) { - immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_HIGH, 0x9f3cc000); - } else { - immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_LOW, 0x9f3cc000); - } -#else immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; -#endif config_8260_ioports (immr); @@ -182,8 +157,7 @@ void cpu_init_f (volatile immap_t * immr) #endif /* now restrict to preliminary range */ - /* the PS came from the HRCW, don´t change it */ - memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK); + memctl->memc_br0 = CFG_BR0_PRELIM; memctl->memc_or0 = CFG_OR0_PRELIM; #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c index 37bf4456e..584c40f17 100644 --- a/cpu/mpc8260/ether_fcc.c +++ b/cpu/mpc8260/ether_fcc.c @@ -47,13 +47,13 @@ #include #include -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) #include #endif DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \ +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \ defined(CONFIG_NET_MULTI) static struct ether_fcc_info_s @@ -393,7 +393,7 @@ int fec_initialize(bd_t *bis) eth_register(dev); -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \ && defined(CONFIG_BITBANGMII) miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); @@ -1187,4 +1187,4 @@ eth_loopback_test (void) #endif /* CONFIG_ETHER_LOOPBACK_TEST */ -#endif +#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */ diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index 633d05391..a733b45c0 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -36,7 +36,7 @@ #include #include -#if defined(CONFIG_ETHER_ON_SCC) && defined(CONFIG_CMD_NET) +#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_COMMANDS & CFG_CMD_NET) #if (CONFIG_ETHER_INDEX == 1) # define PROFF_ENET PROFF_SCC1 @@ -77,9 +77,7 @@ #define TX_BUF_CNT 2 -#if !defined(CFG_SCC_TOUT_LOOP) - #define CFG_SCC_TOUT_LOOP 1000000 -#endif +#define TOUT_LOOP 1000000 static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ]; @@ -111,7 +109,7 @@ int eth_send(volatile void *packet, int length) } for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= CFG_SCC_TOUT_LOOP) { + if (i >= TOUT_LOOP) { puts ("scc: tx buffer not ready\n"); goto out; } @@ -123,7 +121,7 @@ int eth_send(volatile void *packet, int length) BD_ENET_TX_WRAP); for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= CFG_SCC_TOUT_LOOP) { + if (i >= TOUT_LOOP) { puts ("scc: tx error\n"); goto out; } @@ -264,6 +262,7 @@ int eth_init(bd_t *bis) pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ + /* 24.21 - (19): Initialize RxBD */ for (i = 0; i < PKTBUFSRX; i++) { @@ -354,4 +353,4 @@ void restart(void) } #endif -#endif +#endif /* CONFIG_ETHER_ON_SCC && CFG_CMD_NET */ diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c index c3af7b6d8..34bd3897f 100644 --- a/cpu/mpc8260/i2c.c +++ b/cpu/mpc8260/i2c.c @@ -191,10 +191,10 @@ static int i2c_setrate(int hz, int speed) if ((diff >= 0) && (diff < bestspeed_diff)) { - bestspeed_diff = diff ; - bestspeed_modval = modval; - bestspeed_brgval = brgval; - bestspeed_filter = filter; + bestspeed_diff = diff ; + bestspeed_modval = modval; + bestspeed_brgval = brgval; + bestspeed_filter = filter; } } } @@ -242,7 +242,7 @@ void i2c_init(int speed, int slaveadd) /* * initialise data in dual port ram: * - * dpaddr -> parameter ram (64 bytes) + * dpaddr -> parameter ram (64 bytes) * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes) * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes) * tx buffer (MAX_TX_SPACE bytes) diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c index bf0d4d0d5..56e9a7213 100644 --- a/cpu/mpc8260/interrupts.c +++ b/cpu/mpc8260/interrupts.c @@ -246,7 +246,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) /****************************************************************************/ -#if defined(CONFIG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) /* ripped this out of ppc4xx/interrupts.c */ @@ -276,4 +276,4 @@ do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) enable_interrupts (); } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/mpc8260/kgdb.S b/cpu/mpc8260/kgdb.S index dae87bb97..2a250249b 100644 --- a/cpu/mpc8260/kgdb.S +++ b/cpu/mpc8260/kgdb.S @@ -34,7 +34,7 @@ #include #include -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) /* * cache flushing routines for kgdb @@ -69,4 +69,4 @@ kgdb_flush_cache_range: SYNC blr -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index 82303644b..b14fc159b 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -33,10 +33,6 @@ #include #include #include -#ifdef CONFIG_OF_LIBFDT -#include -#include -#endif #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 DECLARE_GLOBAL_DATA_PTR; @@ -278,8 +274,7 @@ void pci_mpc8250_init (struct pci_controller *hose) | SIUMCR_CS10PC00 | SIUMCR_BCTLC00 | SIUMCR_MMR11; -#elif defined(CONFIG_TQM8272) -/* nothing to do for this Board here */ + #else /* * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), @@ -453,12 +448,4 @@ void pci_mpc8250_init (struct pci_controller *hose) immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); } -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - do_fixup_by_prop_u32(blob, "device_type", "pci", 4, - "clock-frequency", gd->pci_clk, 1); -} -#endif - #endif /* CONFIG_PCI */ diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c index 8d280fbb7..360404f0c 100644 --- a/cpu/mpc8260/speed.c +++ b/cpu/mpc8260/speed.c @@ -25,10 +25,6 @@ #include #include -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) -extern unsigned long board_get_cpu_clk_f (void); -#endif - DECLARE_GLOBAL_DATA_PTR; /* ------------------------------------------------------------------------- */ @@ -115,12 +111,8 @@ int get_clocks (void) #if !defined(CONFIG_8260_CLKIN) #error clock measuring not implemented yet - define CONFIG_8260_CLKIN -#else -#if defined(CONFIG_BOARD_GET_CPU_CLK_F) - clkin = board_get_cpu_clk_f (); #else clkin = CONFIG_8260_CLKIN; -#endif #endif sccr = immap->im_clkrst.car_sccr; @@ -162,30 +154,6 @@ int get_clocks (void) gd->cpu_clk = clkin; } -#ifdef CONFIG_PCI - gd->pci_clk = clkin; - - if (sccr & SCCR_PCI_MODE) { - uint pci_div; - uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT; - - if (sccr & SCCR_PCI_MODCK) { - pci_div = 2; - if (pcidf == 9) { - pci_div *= 5; - } else if (pcidf == 0xB) { - pci_div *= 6; - } else { - pci_div *= (pcidf + 1); - } - } else { - pci_div = pcidf + 1; - } - - gd->pci_clk = (gd->cpm_clk * 2) / pci_div; - } -#endif - return (0); } @@ -244,9 +212,26 @@ int prt_8260_clks (void) printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n", gd->cpu_clk, gd->cpm_clk, gd->bus_clk); -#ifdef CONFIG_PCI - printf (" - pci_clk %10ld\n", gd->pci_clk); -#endif + + if (sccr & SCCR_PCI_MODE) { + uint pci_div; + uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT; + + if (sccr & SCCR_PCI_MODCK) { + pci_div = 2; + if (pcidf == 9) { + pci_div *= 5; + } else if (pcidf == 0xB) { + pci_div *= 6; + } else { + pci_div *= (pcidf + 1); + } + } else { + pci_div = pcidf + 1; + } + + printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div); + } putc ('\n'); return (0); diff --git a/cpu/mpc8260/speed.h b/cpu/mpc8260/speed.h index 3f32a143c..b66393bec 100644 --- a/cpu/mpc8260/speed.h +++ b/cpu/mpc8260/speed.h @@ -28,10 +28,10 @@ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 * * SPEED_FCOUNT2 timer 2 counting frequency - * GCLK CPU clock + * GCLK CPU clock * SPEED_TMR2_PS prescaler */ -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ +#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ /*----------------------------------------------------------------------- * Timer value for PIT diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index 7f5dc819c..2e93bbbb8 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -279,7 +279,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -298,7 +298,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ @@ -676,13 +676,13 @@ init_debug: bdnz 1b /* Load the Instruction Address Breakpoint Register (IABR). */ - /* */ + /* */ /* The address to load is stored in the first word of dual port */ /* ram and should be preserved while the power is on, so you */ /* can plug addresses into that location then reset the cpu and */ /* this code will load that address into the IABR after the */ /* reset. */ - /* */ + /* */ /* When the program counter matches the contents of the IABR, */ /* an exception is generated (before the instruction at that */ /* location completes). The vector for this exception is 0x1300 */ diff --git a/cpu/mpc8260/traps.c b/cpu/mpc8260/traps.c index b5d416c97..0c39e434e 100644 --- a/cpu/mpc8260/traps.c +++ b/cpu/mpc8260/traps.c @@ -37,7 +37,7 @@ #include #include -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -150,7 +150,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -186,7 +186,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -198,7 +198,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -210,7 +210,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -223,7 +223,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -232,7 +232,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -242,7 +242,7 @@ DebugException(struct pt_regs *regs) printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile index fcb6a5246..60df4cdec 100644 --- a/cpu/mpc83xx/Makefile +++ b/cpu/mpc83xx/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # Copyright 2004 Freescale Semiconductor, Inc. # # See file CREDITS for list of people who contributed to this @@ -25,37 +22,31 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a -START = start.o +START = start.o \ + resetvec.o -COBJS-y += traps.o -COBJS-y += cpu.o -COBJS-y += cpu_init.o -COBJS-y += speed.o -COBJS-y += interrupts.o -COBJS-y += spd_sdram.o -COBJS-y += ecc.o -COBJS-$(CONFIG_QE) += qe_io.o -COBJS-$(CONFIG_FSL_SERDES) += serdes.o -COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS = traps.o \ + cpu.o \ + cpu_init.o \ + speed.o \ + interrupts.o \ + i2c.o \ + spd_sdram.o -COBJS := $(COBJS-y) -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) +OBJS = $(COBJS) -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk index 2f0f1ce1e..8b4ff92b1 100644 --- a/cpu/mpc83xx/config.mk +++ b/cpu/mpc83xx/config.mk @@ -23,7 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \ - -ffixed-r2 -msoft-float - -# Use default linker script. Board port can override in board/*/config.mk -LDSCRIPT := $(SRCTREE)/cpu/mpc83xx/u-boot.lds + -ffixed-r2 -ffixed-r29 -msoft-float diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 52e4476d8..20bba6c66 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright 2004 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,6 +18,11 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Change log: + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) */ /* @@ -30,159 +35,43 @@ #include #include #include +#include #include -#include DECLARE_GLOBAL_DATA_PTR; + int checkcpu(void) { - volatile immap_t *immr; ulong clock = gd->cpu_clk; u32 pvr = get_pvr(); - u32 spridr; char buf[32]; - int i; - const struct cpu_type { - char name[15]; - u32 partid; - } cpu_type_list [] = { - CPU_TYPE_ENTRY(8311), - CPU_TYPE_ENTRY(8313), - CPU_TYPE_ENTRY(8314), - CPU_TYPE_ENTRY(8315), - CPU_TYPE_ENTRY(8321), - CPU_TYPE_ENTRY(8323), - CPU_TYPE_ENTRY(8343), - CPU_TYPE_ENTRY(8347_TBGA_), - CPU_TYPE_ENTRY(8347_PBGA_), - CPU_TYPE_ENTRY(8349), - CPU_TYPE_ENTRY(8358_TBGA_), - CPU_TYPE_ENTRY(8358_PBGA_), - CPU_TYPE_ENTRY(8360), - CPU_TYPE_ENTRY(8377), - CPU_TYPE_ENTRY(8378), - CPU_TYPE_ENTRY(8379), - }; - - immr = (immap_t *)CFG_IMMR; - - puts("CPU: "); - - switch (pvr & 0xffff0000) { - case PVR_E300C1: - printf("e300c1, "); - break; - - case PVR_E300C2: - printf("e300c2, "); - break; - - case PVR_E300C3: - printf("e300c3, "); - break; - - case PVR_E300C4: - printf("e300c4, "); - break; - - default: - printf("Unknown core, "); + if ((pvr & 0xFFFF0000) != PVR_83xx) { + puts("Not MPC83xx Family!!!\n"); + return -1; } - spridr = immr->sysconf.spridr; - - for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) - if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { - puts("MPC"); - puts(cpu_type_list[i].name); - if (IS_E_PROCESSOR(spridr)) - puts("E"); - if (REVID_MAJOR(spridr) >= 2) - puts("A"); - printf(", Rev: %d.%d", REVID_MAJOR(spridr), - REVID_MINOR(spridr)); - break; - } - - if (i == ARRAY_SIZE(cpu_type_list)) - printf("(SPRIDR %08x unknown), ", spridr); - - printf(" at %s MHz, ", strmhz(buf, clock)); - - printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk)); + puts("CPU: MPC83xx, "); + switch(pvr) { + case PVR_8349_REV10: + break; + case PVR_8349_REV11: + break; + default: + puts("Rev: Unknown\n"); + return -1; /* Not sure what this is */ + } + printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4, + (pvr & 0x0f), strmhz(buf, clock)); return 0; } -/* - * Program a UPM with the code supplied in the table. - * - * The 'dummy' variable is used to increment the MAD. 'dummy' is - * supposed to be a pointer to the memory of the device being - * programmed by the UPM. The data in the MDR is written into - * memory and the MAD is incremented every time there's a read - * from 'dummy'. Unfortunately, the current prototype for this - * function doesn't allow for passing the address of this - * device, and changing the prototype will break a number lots - * of other code, so we need to use a round-about way of finding - * the value for 'dummy'. - * - * The value can be extracted from the base address bits of the - * Base Register (BR) associated with the specific UPM. To find - * that BR, we need to scan all 8 BRs until we find the one that - * has its MSEL bits matching the UPM we want. Once we know the - * right BR, we can extract the base address bits from it. - * - * The MxMR and the BR and OR of the chosen bank should all be - * configured before calling this function. - * - * Parameters: - * upm: 0=UPMA, 1=UPMB, 2=UPMC - * table: Pointer to an array of values to program - * size: Number of elements in the array. Must be 64 or less. - */ void upmconfig (uint upm, uint *table, uint size) { -#if defined(CONFIG_MPC834X) - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile lbus83xx_t *lbus = &immap->lbus; - volatile uchar *dummy = NULL; - const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */ - volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */ - uint i; - - /* Scan all the banks to determine the base address of the device */ - for (i = 0; i < 8; i++) { - if ((lbus->bank[i].br & BR_MSEL) == msel) { - dummy = (uchar *) (lbus->bank[i].br & BR_BA); - break; - } - } - - if (!dummy) { - printf("Error: %s() could not find matching BR\n", __FUNCTION__); - hang(); - } - - /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */ - *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000; - - for (i = 0; i < size; i++) { - lbus->mdr = table[i]; - __asm__ __volatile__ ("sync"); - *dummy; /* Write the value to memory and increment MAD */ - __asm__ __volatile__ ("sync"); - } - - /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */ - *mxmr &= 0xCFFFFFC0; -#else - printf("Error: %s() not defined for this configuration.\n", __FUNCTION__); - hang(); -#endif + hang(); /* FIXME: upconfig() needed? */ } @@ -194,7 +83,7 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ulong addr; #endif - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; #ifdef MPC83xx_RESET /* Interrupts and MMU off */ @@ -261,23 +150,52 @@ unsigned long get_tbclk(void) #if defined(CONFIG_WATCHDOG) void watchdog_reset (void) { - int re_enable = disable_interrupts(); + hang(); /* FIXME: implement watchdog_reset()? */ +} +#endif /* CONFIG_WATCHDOG */ - /* Reset the 83xx watchdog */ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - immr->wdt.swsrr = 0x556c; - immr->wdt.swsrr = 0xaa39; +#if defined(CONFIG_OF_FLAT_TREE) +void +ft_cpu_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + ulong clock; - if (re_enable) - enable_interrupts (); + clock = bd->bi_busfreq; + p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + + p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len); + if (p != NULL) + *p = cpu_to_be32(clock); + +#ifdef CONFIG_MPC83XX_TSEC1 + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len); + memcpy(p, bd->bi_enetaddr, 6); +#endif + +#ifdef CONFIG_MPC83XX_TSEC2 + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len); + memcpy(p, bd->bi_enet1addr, 6); +#endif } #endif #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile dma83xx_t *dma = &immap->dma; + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile dma8349_t *dma = &immap->dma; volatile u32 status = swab32(dma->dmasr0); volatile u32 dmamr0 = swab32(dma->dmamr0); @@ -307,8 +225,8 @@ void dma_init(void) uint dma_check(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile dma83xx_t *dma = &immap->dma; + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile dma8349_t *dma = &immap->dma; volatile u32 status = swab32(dma->dmasr0); volatile u32 byte_count = swab32(dma->dmabcr0); @@ -326,8 +244,8 @@ uint dma_check(void) int dma_xfer(void *dest, u32 count, void *src) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile dma83xx_t *dma = &immap->dma; + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile dma8349_t *dma = &immap->dma; volatile u32 dmamr0; /* initialize DMASARn, DMADAR and DMAABCRn */ @@ -357,23 +275,3 @@ int dma_xfer(void *dest, u32 count, void *src) return ((int)dma_check()); } #endif /*CONFIG_DDR_ECC*/ - -#ifdef CONFIG_TSEC_ENET -/* Default initializations for TSEC controllers. To override, - * create a board-specific function called: - * int board_eth_init(bd_t *bis) - */ - -extern int tsec_initialize(bd_t * bis, int index, char *devname); - -int cpu_eth_init(bd_t *bis) -{ -#if defined(CONFIG_TSEC1) - tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); -#endif -#if defined(CONFIG_TSEC2) - tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); -#endif - return 0; -} -#endif diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 67c9e570c..6ed0992c0 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright 2004 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -18,6 +18,11 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Change log: + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) */ #include @@ -26,30 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_QE -extern qe_iop_conf_t qe_iop_conf_tab[]; -extern void qe_config_iopin(u8 port, u8 pin, int dir, - int open_drain, int assign); -extern void qe_init(uint qe_base); -extern void qe_reset(void); - -static void config_qe_ioports(void) -{ - u8 port, pin; - int dir, open_drain, assign; - int i; - - for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { - port = qe_iop_conf_tab[i].port; - pin = qe_iop_conf_tab[i].pin; - dir = qe_iop_conf_tab[i].dir; - open_drain = qe_iop_conf_tab[i].open_drain; - assign = qe_iop_conf_tab[i].assign; - qe_config_iopin(port, pin, dir, open_drain, assign); - } -} -#endif - /* * Breathe some life into the CPU... * @@ -65,104 +46,6 @@ void cpu_init_f (volatile immap_t * im) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); - /* system performance tweaking */ - -#ifdef CFG_ACR_PIPE_DEP - /* Arbiter pipeline depth */ - im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | - (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); -#endif - -#ifdef CFG_ACR_RPTCNT - /* Arbiter repeat count */ - im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | - (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT); -#endif - -#ifdef CFG_SPCR_OPT - /* Optimize transactions between CSB and other devices */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | - (CFG_SPCR_OPT << SPCR_OPT_SHIFT); -#endif - -#ifdef CFG_SPCR_TSECEP - /* all eTSEC's Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | - (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT); -#endif - -#ifdef CFG_SPCR_TSEC1EP - /* TSEC1 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | - (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT); -#endif - -#ifdef CFG_SPCR_TSEC2EP - /* TSEC2 Emergency priority */ - im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | - (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT); -#endif - -#ifdef CFG_SCCR_ENCCM - /* Encryption clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) | - (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT); -#endif - -#ifdef CFG_SCCR_PCICM - /* PCI & DMA clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) | - (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT); -#endif - -#ifdef CFG_SCCR_TSECCM - /* all TSEC's clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) | - (CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT); -#endif - -#ifdef CFG_SCCR_TSEC1CM - /* TSEC1 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | - (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT); -#endif - -#ifdef CFG_SCCR_TSEC2CM - /* TSEC2 clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | - (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT); -#endif - -#ifdef CFG_SCCR_TSEC1ON - /* TSEC1 clock switch */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) | - (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT); -#endif - -#ifdef CFG_SCCR_TSEC2ON - /* TSEC2 clock switch */ - im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) | - (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT); -#endif - -#ifdef CFG_SCCR_USBMPHCM - /* USB MPH clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) | - (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT); -#endif - -#ifdef CFG_SCCR_USBDRCM - /* USB DR clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) | - (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT); -#endif - -#ifdef CFG_SCCR_SATACM - /* SATA controller clock mode */ - im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) | - (CFG_SCCR_SATACM << SCCR_SATACM_SHIFT); -#endif - /* RSR - Reset Status Register - clear all status (4.6.1.3) */ gd->reset_status = im->reset.rsr; im->reset.rsr = ~(RSR_RES); @@ -181,29 +64,11 @@ void cpu_init_f (volatile immap_t * im) /* System General Purpose Register */ #ifdef CFG_SICRH -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313) - /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ - im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CFG_SICRH; -#else im->sysconf.sicrh = CFG_SICRH; #endif -#endif #ifdef CFG_SICRL im->sysconf.sicrl = CFG_SICRL; #endif - /* DDR control driver register */ -#ifdef CFG_DDRCDR - im->sysconf.ddrcdr = CFG_DDRCDR; -#endif - /* Output buffer impedance register */ -#ifdef CFG_OBIR - im->sysconf.obir = CFG_OBIR; -#endif - -#ifdef CONFIG_QE - /* Config QE ioports */ - config_qe_ioports(); -#endif /* * Memory Controller: @@ -223,7 +88,7 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM; im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM; #else -#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined +#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined #endif #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) @@ -283,57 +148,21 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM; #endif #ifdef CFG_GPIO1_PRELIM - im->gpio[0].dir = CFG_GPIO1_DIR; - im->gpio[0].dat = CFG_GPIO1_DAT; + im->pgio[0].dir = CFG_GPIO1_DIR; + im->pgio[0].dat = CFG_GPIO1_DAT; #endif #ifdef CFG_GPIO2_PRELIM - im->gpio[1].dir = CFG_GPIO2_DIR; - im->gpio[1].dat = CFG_GPIO2_DAT; + im->pgio[1].dir = CFG_GPIO2_DIR; + im->pgio[1].dat = CFG_GPIO2_DAT; #endif } + +/* + * Initialize higher level parts of CPU like time base and timers. + */ + int cpu_init_r (void) { -#ifdef CONFIG_QE - uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */ - qe_init(qe_base); - qe_reset(); -#endif - return 0; -} - -/* - * Figure out the cause of the reset - */ -int prt_83xx_rsr(void) -{ - static struct { - ulong mask; - char *desc; - } bits[] = { - { - RSR_SWSR, "Software Soft"}, { - RSR_SWHR, "Software Hard"}, { - RSR_JSRS, "JTAG Soft"}, { - RSR_CSHR, "Check Stop"}, { - RSR_SWRS, "Software Watchdog"}, { - RSR_BMRS, "Bus Monitor"}, { - RSR_SRS, "External/Internal Soft"}, { - RSR_HRS, "External/Internal Hard"} - }; - static int n = sizeof bits / sizeof bits[0]; - ulong rsr = gd->reset_status; - int i; - char *sep; - - puts("Reset Status:"); - - sep = " "; - for (i = 0; i < n; i++) - if (rsr & bits[i].mask) { - printf("%s%s", sep, bits[i].desc); - sep = ", "; - } - puts("\n\n"); return 0; } diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c new file mode 100644 index 000000000..70450f9e4 --- /dev/null +++ b/cpu/mpc83xx/i2c.c @@ -0,0 +1,253 @@ +/* + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao + * Adapted for Motorola 85xx chip. + * + * (C) Copyright 2003 + * Gleb Natapov + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk + * + * Hardware I2C driver for MPC107 PCI bridge. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +#include +#include +#include + +#ifdef CONFIG_HARD_I2C +#include +#include + +#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X) +i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET); +#endif + +void +i2c_init(int speed, int slaveadd) +{ + /* stop I2C controller */ + writeb(0x00 , &I2C->cr); + + /* set clock */ + writeb(0x3f, &I2C->fdr); + + /* set default filter */ + writeb(0x10,&I2C->dfsrr); + + /* write slave address */ + writeb(slaveadd, &I2C->adr); + + /* clear status register */ + writeb(0x00, &I2C->sr); + + /* start I2C controller */ + writeb(I2C_CR_MEN, &I2C->cr); +} + +static __inline__ int +i2c_wait4bus (void) +{ + ulong timeval = get_timer (0); + while (readb(&I2C->sr) & I2C_SR_MBB) { + if (get_timer (timeval) > I2C_TIMEOUT) { + return -1; + } + } + return 0; +} + +static __inline__ int +i2c_wait (int write) +{ + u32 csr; + ulong timeval = get_timer(0); + do { + csr = readb(&I2C->sr); + + if (!(csr & I2C_SR_MIF)) + continue; + + writeb(0x0, &I2C->sr); + + if (csr & I2C_SR_MAL) { + debug("i2c_wait: MAL\n"); + return -1; + } + + if (!(csr & I2C_SR_MCF)) { + debug("i2c_wait: unfinished\n"); + return -1; + } + + if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } + + return 0; + } while (get_timer (timeval) < I2C_TIMEOUT); + + debug("i2c_wait: timed out\n"); + return -1; +} + +static __inline__ int +i2c_write_addr (u8 dev, u8 dir, int rsta) +{ + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | + (rsta?I2C_CR_RSTA:0), + &I2C->cr); + + writeb((dev << 1) | dir, &I2C->dr); + + if (i2c_wait (I2C_WRITE) < 0) + return 0; + return 1; +} + +static __inline__ int +__i2c_write (u8 *data, int length) +{ + int i; + + writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, + &I2C->cr); + + for (i=0; i < length; i++) { + writeb(data[i], &I2C->dr); + + if (i2c_wait (I2C_WRITE) < 0) + break; + } + return i; +} + +static __inline__ int +__i2c_read (u8 *data, int length) +{ + int i; + + writeb(I2C_CR_MEN | I2C_CR_MSTA | + ((length == 1) ? I2C_CR_TXAK : 0), + &I2C->cr); + + /* dummy read */ + readb(&I2C->dr); + + for (i=0; i < length; i++) { + if (i2c_wait (I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(I2C_CR_MEN | I2C_CR_MSTA | + I2C_CR_TXAK, + &I2C->cr); + + /* Generate stop on last byte */ + if (i == length - 1) + writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); + + data[i] = readb(&I2C->dr); + } + return i; +} + +int +i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + if (i2c_write_addr (dev, I2C_READ, 1) == 0) + goto exit; + + i = __i2c_read (data, length); + + exit: + writeb(I2C_CR_MEN, &I2C->cr); + return !(i == length); +} + +int +i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + i = __i2c_write (data, length); + + exit: + writeb(I2C_CR_MEN, &I2C->cr); + return !(i == length); +} + +int i2c_probe (uchar chip) +{ + int tmp; + + /* + * Try to read the first location of the chip. The underlying + * driver doesn't appear to support sending just the chip address + * and looking for an back. + */ + udelay(10000); + return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); +} + +uchar i2c_reg_read (uchar i2c_addr, uchar reg) +{ + uchar buf[1]; + + i2c_read (i2c_addr, reg, 1, buf, 1); + + return (buf[0]); +} + +void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write (i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc83xx/interrupts.c b/cpu/mpc83xx/interrupts.c index 98ed21ccf..5a0babfcb 100644 --- a/cpu/mpc83xx/interrupts.c +++ b/cpu/mpc83xx/interrupts.c @@ -21,6 +21,13 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Change log: + * + * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00 + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) */ #include @@ -38,7 +45,7 @@ struct irq_action { int interrupt_init_cpu (unsigned *decrementer_count) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CFG_IMMRBAR; *decrementer_count = (gd->bus_clk / 4) / CFG_HZ; @@ -81,7 +88,7 @@ void timer_interrupt_cpu (struct pt_regs *regs) } -#if defined(CONFIG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) /* ripped this out of ppc4xx/interrupts.c */ @@ -94,4 +101,4 @@ do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/mpc83xx/resetvec.S b/cpu/mpc83xx/resetvec.S new file mode 100644 index 000000000..3dfcd0dcd --- /dev/null +++ b/cpu/mpc83xx/resetvec.S @@ -0,0 +1,6 @@ + .section .resetvec,"ax" +#ifndef FIXME +#if 0 + b _start_e500 +#endif +#endif diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 76f247449..48624feca 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -1,10 +1,8 @@ /* - * (C) Copyright 2006-2007 Freescale Semiconductor, Inc. - * * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -25,6 +23,11 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Change log: + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) */ #include @@ -34,38 +37,9 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - -void board_add_ram_info(int use_default) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - char buf[32]; - - printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) - >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); - - if (ddr->sdram_cfg & SDRAM_CFG_32_BE) - puts(", 32-bit"); - else - puts(", 64-bit"); - - if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) - puts(", ECC on"); - else - puts(", ECC off"); - - printf(", %s MHz)", strmhz(buf, gd->mem_clk)); - -#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE) - puts("\nSDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); -#endif -} - #ifdef CONFIG_SPD_EEPROM -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) +#if defined(CONFIG_DDR_ECC) extern void dma_init(void); extern uint dma_check(void); extern int dma_xfer(void *dest, uint count, void *src); @@ -78,16 +52,16 @@ extern int dma_xfer(void *dest, uint count, void *src); /* * Convert picoseconds into clock cycles (rounding up if needed). */ + int picos_to_clk(int picos) { - unsigned int mem_bus_clk; int clks; - mem_bus_clk = gd->mem_clk >> 1; - clks = picos / (1000000000 / (mem_bus_clk / 1000)); - if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0) - clks++; + clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); + if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { + clks++; + } return clks; } @@ -129,142 +103,60 @@ static void spd_debug(spd_eeprom_t *spd) long int spd_sdram() { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ddr83xx_t *ddr = &immap->ddr; - volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile ddr8349_t *ddr = &immap->ddr; + volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0]; spd_eeprom_t spd; - unsigned int n_ranks; - unsigned int odt_rd_cfg, odt_wr_cfg; - unsigned char twr_clk, twtr_clk; - unsigned int sdram_type; + unsigned tmp, tmp1; unsigned int memsize; unsigned int law_size; - unsigned char caslat, caslat_ctrl; - unsigned int trfc, trfc_clk, trfc_low, trfc_high; - unsigned int trcd_clk, trtp_clk; - unsigned char cke_min_clk; - unsigned char add_lat, wr_lat; - unsigned char wr_data_delay; - unsigned char four_act; - unsigned char cpo; - unsigned char burstlen; - unsigned char odt_cfg, mode_odt_enable; - unsigned int max_bus_clk; - unsigned int max_data_rate, effective_data_rate; - unsigned int ddrc_clk; - unsigned int refresh_clk; - unsigned int sdram_cfg; - unsigned int ddrc_ecc_enable; - unsigned int pvr = get_pvr(); + unsigned char caslat; + unsigned int trfc, trfc_clk, trfc_low; - /* Read SPD parameters with I2C */ CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); #ifdef SPD_DEBUG spd_debug(&spd); #endif - /* Check the memory type */ - if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) { - debug("DDR: Module mem type is %02X\n", spd.mem_type); + if (spd.nrows > 2) { + puts("DDR:Only two chip selects are supported on ADS.\n"); return 0; } - /* Check the number of physical bank */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - n_ranks = spd.nrows; - } else { - n_ranks = (spd.nrows & 0x7) + 1; - } - - if (n_ranks > 2) { - printf("DDR: The number of physical bank is %02X\n", n_ranks); + if (spd.nrow_addr < 12 + || spd.nrow_addr > 14 + || spd.ncol_addr < 8 + || spd.ncol_addr > 11) { + puts("DDR:Row or Col number unsupported.\n"); return 0; } - /* Check if the number of row of the module is in the range of DDRC */ - if (spd.nrow_addr < 12 || spd.nrow_addr > 15) { - printf("DDR: Row number is out of range of DDRC, row=%02X\n", - spd.nrow_addr); - return 0; - } - - /* Check if the number of col of the module is in the range of DDRC */ - if (spd.ncol_addr < 8 || spd.ncol_addr > 11) { - printf("DDR: Col number is out of range of DDRC, col=%02X\n", - spd.ncol_addr); - return 0; - } - -#ifdef CFG_DDRCDR_VALUE - /* - * Adjust DDR II IO voltage biasing. It just makes it work. - */ - if(spd.mem_type == SPD_MEMTYPE_DDR2) { - immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE; - } - udelay(50000); -#endif - - /* - * ODT configuration recommendation from DDR Controller Chapter. - */ - odt_rd_cfg = 0; /* Never assert ODT */ - odt_wr_cfg = 0; /* Never assert ODT */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - odt_wr_cfg = 1; /* Assert ODT on writes to CSn */ - } - - /* Setup DDR chip select register */ -#ifdef CFG_83XX_DDR_USES_CS0 - ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1; - ddr->cs_config[0] = ( 1 << 31 - | (odt_rd_cfg << 20) - | (odt_wr_cfg << 16) - | (spd.nrow_addr - 12) << 8 - | (spd.ncol_addr - 8) ); - debug("\n"); - debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds); - debug("cs0_config = 0x%08x\n",ddr->cs_config[0]); - - if (n_ranks == 2) { - ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8) - | ((banksize(spd.row_dens) >> 23) - 1) ); - ddr->cs_config[1] = ( 1<<31 - | (odt_rd_cfg << 20) - | (odt_wr_cfg << 16) - | (spd.nrow_addr-12) << 8 - | (spd.ncol_addr-8) ); - debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds); - debug("cs1_config = 0x%08x\n",ddr->cs_config[1]); - } - -#else ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; ddr->cs_config[2] = ( 1 << 31 - | (odt_rd_cfg << 20) - | (odt_wr_cfg << 16) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("\n"); debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); - if (n_ranks == 2) { + if (spd.nrows == 2) { ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) | ((banksize(spd.row_dens) >> 23) - 1) ); ddr->cs_config[3] = ( 1<<31 - | (odt_rd_cfg << 20) - | (odt_wr_cfg << 16) | (spd.nrow_addr-12) << 8 | (spd.ncol_addr-8) ); debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); } -#endif + + if (spd.mem_type != 0x07) { + puts("No DDR module found!\n"); + return 0; + } /* * Figure out memory size in Megabytes. */ - memsize = n_ranks * banksize(spd.row_dens) / 0x100000; + memsize = spd.nrows * banksize(spd.row_dens) / 0x100000; /* * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. @@ -280,524 +172,218 @@ long int spd_sdram() debug("DDR:ar=0x%08x\n", ecm->ar); /* - * Find the largest CAS by locating the highest 1 bit - * in the spd.cas_lat field. Translate it to a DDR - * controller field value: + * find the largest CAS + */ + if(spd.cas_lat & 0x40) { + caslat = 7; + } else if (spd.cas_lat & 0x20) { + caslat = 6; + } else if (spd.cas_lat & 0x10) { + caslat = 5; + } else if (spd.cas_lat & 0x08) { + caslat = 4; + } else if (spd.cas_lat & 0x04) { + caslat = 3; + } else if (spd.cas_lat & 0x02) { + caslat = 2; + } else if (spd.cas_lat & 0x01) { + caslat = 1; + } else { + puts("DDR:no valid CAS Latency information.\n"); + return 0; + } + + tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10 + + (spd.clk_cycle & 0x0f)); + debug("DDR:Module maximum data rate is: %dMhz\n", tmp); + + tmp1 = get_bus_freq(0) / 1000000; + if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) { + /* 90~230 range, treated as DDR 200 */ + if (spd.clk_cycle3 == 0xa0) + caslat -= 2; + else if(spd.clk_cycle2 == 0xa0) + caslat--; + } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) { + /* 230-280 range, treated as DDR 266 */ + if (spd.clk_cycle3 == 0x75) + caslat -= 2; + else if (spd.clk_cycle2 == 0x75) + caslat--; + } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) { + /* 280~350 range, treated as DDR 333 */ + if (spd.clk_cycle3 == 0x60) + caslat -= 2; + else if (spd.clk_cycle2 == 0x60) + caslat--; + } else if (tmp1 < 90 || tmp1 >= 350) { + /* DDR rate out-of-range */ + puts("DDR:platform frequency is not fit for DDR rate\n"); + return 0; + } + + /* + * note: caslat must also be programmed into ddr->sdram_mode + * register. * - * CAS Lat DDR I DDR II Ctrl - * Clocks SPD Bit SPD Bit Value - * ------- ------- ------- ----- - * 1.0 0 0001 - * 1.5 1 0010 - * 2.0 2 2 0011 - * 2.5 3 0100 - * 3.0 4 3 0101 - * 3.5 5 0110 - * 4.0 6 4 0111 - * 4.5 1000 - * 5.0 5 1001 + * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD, + * use conservative value here. */ - caslat = __ilog2(spd.cas_lat); - if ((spd.mem_type == SPD_MEMTYPE_DDR) - && (caslat > 6)) { - printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat); - return 0; - } else if (spd.mem_type == SPD_MEMTYPE_DDR2 - && (caslat < 2 || caslat > 5)) { - printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n", - spd.cas_lat); - return 0; - } - debug("DDR: caslat SPD bit is %d\n", caslat); - - max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10 - + (spd.clk_cycle & 0x0f)); - max_data_rate = max_bus_clk * 2; - - debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate); - - ddrc_clk = gd->mem_clk / 1000000; - effective_data_rate = 0; - - if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ - if (ddrc_clk <= 460 && ddrc_clk > 350) { - /* DDR controller clk at 350~460 */ - effective_data_rate = 400; /* 5ns */ - caslat = caslat; - } else if (ddrc_clk <= 350 && ddrc_clk > 280) { - /* DDR controller clk at 280~350 */ - effective_data_rate = 333; /* 6ns */ - if (spd.clk_cycle2 == 0x60) - caslat = caslat - 1; - else - caslat = caslat; - } else if (ddrc_clk <= 280 && ddrc_clk > 230) { - /* DDR controller clk at 230~280 */ - effective_data_rate = 266; /* 7.5ns */ - if (spd.clk_cycle3 == 0x75) - caslat = caslat - 2; - else if (spd.clk_cycle2 == 0x75) - caslat = caslat - 1; - else - caslat = caslat; - } else if (ddrc_clk <= 230 && ddrc_clk > 90) { - /* DDR controller clk at 90~230 */ - effective_data_rate = 200; /* 10ns */ - if (spd.clk_cycle3 == 0xa0) - caslat = caslat - 2; - else if (spd.clk_cycle2 == 0xa0) - caslat = caslat - 1; - else - caslat = caslat; - } - } else if (max_data_rate >= 323) { /* it is DDR 333 */ - if (ddrc_clk <= 350 && ddrc_clk > 280) { - /* DDR controller clk at 280~350 */ - effective_data_rate = 333; /* 6ns */ - caslat = caslat; - } else if (ddrc_clk <= 280 && ddrc_clk > 230) { - /* DDR controller clk at 230~280 */ - effective_data_rate = 266; /* 7.5ns */ - if (spd.clk_cycle2 == 0x75) - caslat = caslat - 1; - else - caslat = caslat; - } else if (ddrc_clk <= 230 && ddrc_clk > 90) { - /* DDR controller clk at 90~230 */ - effective_data_rate = 200; /* 10ns */ - if (spd.clk_cycle3 == 0xa0) - caslat = caslat - 2; - else if (spd.clk_cycle2 == 0xa0) - caslat = caslat - 1; - else - caslat = caslat; - } - } else if (max_data_rate >= 256) { /* it is DDR 266 */ - if (ddrc_clk <= 350 && ddrc_clk > 280) { - /* DDR controller clk at 280~350 */ - printf("DDR: DDR controller freq is more than " - "max data rate of the module\n"); - return 0; - } else if (ddrc_clk <= 280 && ddrc_clk > 230) { - /* DDR controller clk at 230~280 */ - effective_data_rate = 266; /* 7.5ns */ - caslat = caslat; - } else if (ddrc_clk <= 230 && ddrc_clk > 90) { - /* DDR controller clk at 90~230 */ - effective_data_rate = 200; /* 10ns */ - if (spd.clk_cycle2 == 0xa0) - caslat = caslat - 1; - } - } else if (max_data_rate >= 190) { /* it is DDR 200 */ - if (ddrc_clk <= 350 && ddrc_clk > 230) { - /* DDR controller clk at 230~350 */ - printf("DDR: DDR controller freq is more than " - "max data rate of the module\n"); - return 0; - } else if (ddrc_clk <= 230 && ddrc_clk > 90) { - /* DDR controller clk at 90~230 */ - effective_data_rate = 200; /* 10ns */ - caslat = caslat; - } - } - - debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate); - debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat); - - /* - * Errata DDR6 work around: input enable 2 cycles earlier. - * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2. - */ - if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){ - if (caslat == 2) - ddr->debug_reg = 0x201c0000; /* CL=2 */ - else if (caslat == 3) - ddr->debug_reg = 0x202c0000; /* CL=2.5 */ - else if (caslat == 4) - ddr->debug_reg = 0x202c0000; /* CL=3.0 */ - - __asm__ __volatile__ ("sync"); - - debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg); - } - - /* - * Convert caslat clocks to DDR controller value. - * Force caslat_ctrl to be DDR Controller field-sized. - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - caslat_ctrl = (caslat + 1) & 0x07; - } else { - caslat_ctrl = (2 * caslat - 1) & 0x0f; - } - - debug("DDR: effective data rate is %d MHz\n", effective_data_rate); - debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n", - caslat, caslat_ctrl); - - /* - * Timing Config 0. - * Avoid writing for DDR I. - */ - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - unsigned char taxpd_clk = 8; /* By the book. */ - unsigned char tmrd_clk = 2; /* By the book. */ - unsigned char act_pd_exit = 2; /* Empirical? */ - unsigned char pre_pd_exit = 6; /* Empirical? */ - - ddr->timing_cfg_0 = (0 - | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */ - | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */ - | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */ - | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */ - ); - debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); - } - - /* - * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD, - * use conservative value. - * For DDR II, they are bytes 36 and 37, in quarter nanos. - */ - - if (spd.mem_type == SPD_MEMTYPE_DDR) { - twr_clk = 3; /* Clocks */ - twtr_clk = 1; /* Clocks */ - } else { - twr_clk = picos_to_clk(spd.twr * 250); - twtr_clk = picos_to_clk(spd.twtr * 250); - } - - /* - * Calculate Trfc, in picos. - * DDR I: Byte 42 straight up in ns. - * DDR II: Byte 40 and 42 swizzled some, in ns. - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - trfc = spd.trfc * 1000; /* up to ps */ - } else { - unsigned int byte40_table_ps[8] = { - 0, - 250, - 330, - 500, - 660, - 750, - 0, - 0 - }; - - trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000 - + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7]; - } + trfc = spd.trfc * 1000; /* up to ps */ trfc_clk = picos_to_clk(trfc); - - /* - * Trcd, Byte 29, from quarter nanos to ps and clocks. - */ - trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7; - - /* - * Convert trfc_clk to DDR controller fields. DDR I should - * fit in the REFREC field (16-19) of TIMING_CFG_1, but the - * 83xx controller has an extended REFREC field of three bits. - * The controller automatically adds 8 clocks to this value, - * so preadjust it down 8 first before splitting it up. - */ trfc_low = (trfc_clk - 8) & 0xf; - trfc_high = ((trfc_clk - 8) >> 4) & 0x3; ddr->timing_cfg_1 = - (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */ - ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */ - (trcd_clk << 20 ) | /* ACTTORW */ - (caslat_ctrl << 16 ) | /* CASLAT */ - (trfc_low << 12 ) | /* REFEC */ - ((twr_clk & 0x07) << 8) | /* WRRREC */ - ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */ - ((twtr_clk & 0x07) << 0) /* WRTORD */ - ); + (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | + ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | + ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) | + ((caslat & 0x07) << 16 ) | + (trfc_low << 12 ) | + ( 0x300 ) | + ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1); - /* - * Additive Latency - * For DDR I, 0. - * For DDR II, with ODT enabled, use "a value" less than ACTTORW, - * which comes from Trcd, and also note that: - * add_lat + caslat must be >= 4 - */ - add_lat = 0; - if (spd.mem_type == SPD_MEMTYPE_DDR2 - && (odt_wr_cfg || odt_rd_cfg) - && (caslat < 4)) { - add_lat = trcd_clk - 1; - if ((add_lat + caslat) < 4) { - add_lat = 0; - } - } - - /* - * Write Data Delay - * Historically 0x2 == 4/8 clock delay. - * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. - */ - wr_data_delay = 2; - - /* - * Write Latency - * Read to Precharge - * Minimum CKE Pulse Width. - * Four Activate Window - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - /* - * This is a lie. It should really be 1, but if it is - * set to 1, bits overlap into the old controller's - * otherwise unused ACSM field. If we leave it 0, then - * the HW will magically treat it as 1 for DDR 1. Oh Yea. - */ - wr_lat = 0; - - trtp_clk = 2; /* By the book. */ - cke_min_clk = 1; /* By the book. */ - four_act = 1; /* By the book. */ - - } else { - wr_lat = caslat - 1; - - /* Convert SPD value from quarter nanos to picos. */ - trtp_clk = picos_to_clk(spd.trtp * 250); - - cke_min_clk = 3; /* By the book. */ - four_act = picos_to_clk(37500); /* By the book. 1k pages? */ - } - - /* - * Empirically set ~MCAS-to-preamble override for DDR 2. - * Your milage will vary. - */ - cpo = 0; - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - if (effective_data_rate == 266) { - cpo = 0x4; /* READ_LAT + 1/2 */ - } else if (effective_data_rate == 333 || effective_data_rate == 400) { - cpo = 0x7; /* READ_LAT + 5/4 */ - } else { - /* Automatic calibration */ - cpo = 0x1f; - } - } - - ddr->timing_cfg_2 = (0 - | ((add_lat & 0x7) << 28) /* ADD_LAT */ - | ((cpo & 0x1f) << 23) /* CPO */ - | ((wr_lat & 0x7) << 19) /* WR_LAT */ - | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ - | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ - | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */ - | ((four_act & 0x1f) << 0) /* FOUR_ACT */ - ); + ddr->timing_cfg_2 = 0x00000800; debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); - /* Check DIMM data bus width */ - if (spd.dataw_lsb < 64) { - if (spd.mem_type == SPD_MEMTYPE_DDR) - burstlen = 0x03; /* 32 bit data bus, burst len is 8 */ - else - burstlen = 0x02; /* 32 bit data bus, burst len is 4 */ - debug("\n DDR DIMM: data bus width is 32 bit"); - } else { - burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */ - debug("\n DDR DIMM: data bus width is 64 bit"); - } - - /* Is this an ECC DDR chip? */ - if (spd.config == 0x02) - debug(" with ECC\n"); - else - debug(" without ECC\n"); - - /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus, - Burst type is sequential + /* + * Only DDR I is supported + * DDR I and II have different mode-register-set definition */ - if (spd.mem_type == SPD_MEMTYPE_DDR) { - switch (caslat) { - case 1: - ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */ - break; - case 2: - ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */ - break; - case 3: - ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */ - break; - case 4: - ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */ - break; - default: - printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n"); - return 0; - } - } else { - mode_odt_enable = 0x0; /* Default disabled */ - if (odt_wr_cfg || odt_rd_cfg) { - /* - * Bits 6 and 2 in Extended MRS(1) - * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules. - * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module. - */ - mode_odt_enable = 0x40; /* 150 Ohm */ - } - - ddr->sdram_mode = - (0 - | (1 << (16 + 10)) /* DQS Differential disable */ - | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ - | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ - | ((twr_clk - 1) << 9) /* Write Recovery Autopre */ - | (caslat << 4) /* caslat */ - | (burstlen << 0) /* Burst length */ - ); + switch(caslat) { + case 2: + tmp = 0x50; /* 1.5 */ + break; + case 3: + tmp = 0x20; /* 2.0 */ + break; + case 4: + tmp = 0x60; /* 2.5 */ + break; + case 5: + tmp = 0x30; /* 3.0 */ + break; + default: + puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n"); + return 0; } +#if defined (CONFIG_DDR_32BIT) + /* set burst length to 8 for 32-bit data path */ + tmp |= 0x03; +#else + /* set burst length to 4 - default for 64-bit data path */ + tmp |= 0x02; +#endif + ddr->sdram_mode = tmp; debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); - /* - * Clear EMRS2 and EMRS3. - */ - ddr->sdram_mode2 = 0; - debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2); - - switch (spd.refresh) { - case 0x00: - case 0x80: - refresh_clk = picos_to_clk(15625000); - break; - case 0x01: - case 0x81: - refresh_clk = picos_to_clk(3900000); - break; - case 0x02: - case 0x82: - refresh_clk = picos_to_clk(7800000); - break; - case 0x03: - case 0x83: - refresh_clk = picos_to_clk(31300000); - break; - case 0x04: - case 0x84: - refresh_clk = picos_to_clk(62500000); - break; - case 0x05: - case 0x85: - refresh_clk = picos_to_clk(125000000); - break; - default: - refresh_clk = 0x512; - break; + switch(spd.refresh) { + case 0x00: + case 0x80: + tmp = picos_to_clk(15625000); + break; + case 0x01: + case 0x81: + tmp = picos_to_clk(3900000); + break; + case 0x02: + case 0x82: + tmp = picos_to_clk(7800000); + break; + case 0x03: + case 0x83: + tmp = picos_to_clk(31300000); + break; + case 0x04: + case 0x84: + tmp = picos_to_clk(62500000); + break; + case 0x05: + case 0x85: + tmp = picos_to_clk(125000000); + break; + default: + tmp = 0x512; + break; } /* * Set BSTOPRE to 0x100 for page mode * If auto-charge is used, set BSTOPRE = 0 */ - ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100; + ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100; debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); /* - * SDRAM Cfg 2 + * Is this an ECC DDR chip? */ - odt_cfg = 0; -#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU - if (odt_rd_cfg | odt_wr_cfg) { - odt_cfg = 0x2; /* ODT to IOs during reads */ +#if defined(CONFIG_DDR_ECC) + if (spd.config == 0x02) { + /* disable error detection */ + ddr->err_disable = ~ECC_ERROR_ENABLE; + + /* set single bit error threshold to maximum value, + * reset counter to zero */ + ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) | + (0 << ECC_ERROR_MAN_SBEC_SHIFT); } + debug("DDR:err_disable=0x%08x\n", ddr->err_disable); + debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); #endif - if (spd.mem_type == SPD_MEMTYPE_DDR2) { - ddr->sdram_cfg2 = (0 - | (0 << 26) /* True DQS */ - | (odt_cfg << 21) /* ODT only read */ - | (1 << 12) /* 1 refresh at a time */ - ); - - debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); - } - -#ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ - ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; -#endif - debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); - asm("sync;isync"); - udelay(600); + udelay(500); /* - * Figure out the settings for the sdram_cfg register. Build up - * the value in 'sdram_cfg' before writing since the write into + * SS_EN=1, + * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM + * clock cycle after address/command + */ + /*ddr->sdram_clk_cntl = 0x82000000;*/ + ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05); + + /* + * Figure out the settings for the sdram_cfg register. Build up + * the entire register in 'tmp' before writing since the write into * the register will actually enable the memory controller, and all * settings must be done before enabling. * * sdram_cfg[0] = 1 (ddr sdram logic enable) * sdram_cfg[1] = 1 (self-refresh-enable) - * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM) - * 010 DDR 1 SDRAM - * 011 DDR 2 SDRAM - * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode) - * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts) + * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM) */ - if (spd.mem_type == SPD_MEMTYPE_DDR) - sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1; - else - sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2; + tmp = 0xc2000000; - sdram_cfg = (0 - | SDRAM_CFG_MEM_EN /* DDR enable */ - | SDRAM_CFG_SREN /* Self refresh */ - | sdram_type /* SDRAM type */ - ); - - /* sdram_cfg[3] = RD_EN - registered DIMM enable */ - if (spd.mod_attr & 0x02) - sdram_cfg |= SDRAM_CFG_RD_EN; - - /* The DIMM is 32bit width */ - if (spd.dataw_lsb < 64) { - if (spd.mem_type == SPD_MEMTYPE_DDR) - sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE; - if (spd.mem_type == SPD_MEMTYPE_DDR2) - sdram_cfg |= SDRAM_CFG_32_BE; +#if defined (CONFIG_DDR_32BIT) + /* in 32-Bit mode burst len is 8 beats */ + tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); +#endif + /* + * sdram_cfg[3] = RD_EN - registered DIMM enable + * A value of 0x26 indicates micron registered DIMMS (micron.com) + */ + if (spd.mod_attr == 0x26) { + tmp |= 0x10000000; } - ddrc_ecc_enable = 0; - #if defined(CONFIG_DDR_ECC) - /* Enable ECC with sdram_cfg[2] */ + /* + * If the user wanted ECC (enabled via sdram_cfg[2]) + */ if (spd.config == 0x02) { - sdram_cfg |= 0x20000000; - ddrc_ecc_enable = 1; - /* disable error detection */ - ddr->err_disable = ~ECC_ERROR_ENABLE; - /* set single bit error threshold to maximum value, - * reset counter to zero */ - ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) | - (0 << ECC_ERROR_MAN_SBEC_SHIFT); + tmp |= SDRAM_CFG_ECC_EN; } - - debug("DDR:err_disable=0x%08x\n", ddr->err_disable); - debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); #endif - debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF"); #if defined(CONFIG_DDR_2T_TIMING) /* * Enable 2T timing by setting sdram_cfg[16]. */ - sdram_cfg |= SDRAM_CFG_2T_EN; + tmp |= SDRAM_CFG_2T_EN; #endif - /* Enable controller, and GO! */ - ddr->sdram_cfg = sdram_cfg; + + ddr->sdram_cfg = tmp; asm("sync;isync"); udelay(500); @@ -806,7 +392,8 @@ long int spd_sdram() } #endif /* CONFIG_SPD_EEPROM */ -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) + +#if defined(CONFIG_DDR_ECC) /* * Use timebase counter, get_timer() is not availabe * at this point of initialization yet. @@ -842,48 +429,74 @@ static __inline__ unsigned long get_tbms (void) /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */ void ddr_enable_ecc(unsigned int dram_size) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ddr83xx_t *ddr= &immap->ddr; + uint *p; + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile ddr8349_t *ddr = &immap->ddr; unsigned long t_start, t_end; - register u64 *p; - register uint size; - unsigned int pattern[2]; #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) uint i; #endif + + debug("Initialize a Cachline in DRAM\n"); icache_enable(); + +#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA) + /* Initialise DMA for direct Transfers */ + dma_init(); +#endif + t_start = get_tbms(); - pattern[0] = 0xdeadbeef; - pattern[1] = 0xdeadbeef; #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA) - debug("ddr init: CPU FP write method\n"); - size = dram_size; - for (p = 0; p < (u64*)(size); p++) { - ppcDWstore((u32*)p, pattern); - } - __asm__ __volatile__ ("sync"); -#else - debug("ddr init: DMA method\n"); - size = 0x2000; - for (p = 0; p < (u64*)(size); p++) { - ppcDWstore((u32*)p, pattern); - } - __asm__ __volatile__ ("sync"); + debug("DDR init: Cache flush method\n"); + for (p = 0; p < (uint *)(dram_size); p++) { + if (((unsigned int)p & 0x1f) == 0) { + ppcDcbz((unsigned long) p); + } - /* Initialise DMA for direct transfer */ - dma_init(); - /* Start DMA to transfer */ - dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */ - dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */ - dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */ - dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */ - dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */ - dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */ - dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */ - dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */ - dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */ - dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */ + /* write pattern to cache and flush */ + *p = (unsigned int)0xdeadbeef; + + if (((unsigned int)p & 0x1c) == 0x1c) { + ppcDcbf((unsigned long) p); + } + } +#else + printf("DDR init: DMA method\n"); + for (p = 0; p < (uint *)(8 * 1024); p++) { + /* zero one data cache line */ + if (((unsigned int)p & 0x1f) == 0) { + ppcDcbz((unsigned long)p); + } + + /* write pattern to it and flush */ + *p = (unsigned int)0xdeadbeef; + + if (((unsigned int)p & 0x1c) == 0x1c) { + ppcDcbf((unsigned long)p); + } + } + + /* 8K */ + dma_xfer((uint *)0x2000, 0x2000, (uint *)0); + /* 16K */ + dma_xfer((uint *)0x4000, 0x4000, (uint *)0); + /* 32K */ + dma_xfer((uint *)0x8000, 0x8000, (uint *)0); + /* 64K */ + dma_xfer((uint *)0x10000, 0x10000, (uint *)0); + /* 128k */ + dma_xfer((uint *)0x20000, 0x20000, (uint *)0); + /* 256k */ + dma_xfer((uint *)0x40000, 0x40000, (uint *)0); + /* 512k */ + dma_xfer((uint *)0x80000, 0x80000, (uint *)0); + /* 1M */ + dma_xfer((uint *)0x100000, 0x100000, (uint *)0); + /* 2M */ + dma_xfer((uint *)0x200000, 0x200000, (uint *)0); + /* 4M */ + dma_xfer((uint *)0x400000, 0x400000, (uint *)0); for (i = 1; i < dram_size / 0x800000; i++) { dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 76c569de1..ad6b3f669 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright 2004 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -21,11 +21,15 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Change log: + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) */ #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -49,38 +53,38 @@ typedef enum { typedef struct { mult_t core_csb_ratio; - mult_t vco_divider; + mult_t vco_divider; } corecnf_t; corecnf_t corecnf_tab[] = { - {_byp, _byp}, /* 0x00 */ - {_byp, _byp}, /* 0x01 */ - {_byp, _byp}, /* 0x02 */ - {_byp, _byp}, /* 0x03 */ - {_byp, _byp}, /* 0x04 */ - {_byp, _byp}, /* 0x05 */ - {_byp, _byp}, /* 0x06 */ - {_byp, _byp}, /* 0x07 */ - {_1x, _x2}, /* 0x08 */ - {_1x, _x4}, /* 0x09 */ - {_1x, _x8}, /* 0x0A */ - {_1x, _x8}, /* 0x0B */ - {_1_5x, _x2}, /* 0x0C */ - {_1_5x, _x4}, /* 0x0D */ - {_1_5x, _x8}, /* 0x0E */ - {_1_5x, _x8}, /* 0x0F */ - {_2x, _x2}, /* 0x10 */ - {_2x, _x4}, /* 0x11 */ - {_2x, _x8}, /* 0x12 */ - {_2x, _x8}, /* 0x13 */ - {_2_5x, _x2}, /* 0x14 */ - {_2_5x, _x4}, /* 0x15 */ - {_2_5x, _x8}, /* 0x16 */ - {_2_5x, _x8}, /* 0x17 */ - {_3x, _x2}, /* 0x18 */ - {_3x, _x4}, /* 0x19 */ - {_3x, _x8}, /* 0x1A */ - {_3x, _x8}, /* 0x1B */ + { _byp, _byp}, /* 0x00 */ + { _byp, _byp}, /* 0x01 */ + { _byp, _byp}, /* 0x02 */ + { _byp, _byp}, /* 0x03 */ + { _byp, _byp}, /* 0x04 */ + { _byp, _byp}, /* 0x05 */ + { _byp, _byp}, /* 0x06 */ + { _byp, _byp}, /* 0x07 */ + { _1x, _x2}, /* 0x08 */ + { _1x, _x4}, /* 0x09 */ + { _1x, _x8}, /* 0x0A */ + { _1x, _x8}, /* 0x0B */ + {_1_5x, _x2}, /* 0x0C */ + {_1_5x, _x4}, /* 0x0D */ + {_1_5x, _x8}, /* 0x0E */ + {_1_5x, _x8}, /* 0x0F */ + { _2x, _x2}, /* 0x10 */ + { _2x, _x4}, /* 0x11 */ + { _2x, _x8}, /* 0x12 */ + { _2x, _x8}, /* 0x13 */ + {_2_5x, _x2}, /* 0x14 */ + {_2_5x, _x4}, /* 0x15 */ + {_2_5x, _x8}, /* 0x16 */ + {_2_5x, _x8}, /* 0x17 */ + { _3x, _x2}, /* 0x18 */ + { _3x, _x4}, /* 0x19 */ + { _3x, _x8}, /* 0x1A */ + { _3x, _x8}, /* 0x1B */ }; /* ----------------------------------------------------------------- */ @@ -88,83 +92,91 @@ corecnf_t corecnf_tab[] = { /* * */ -int get_clocks(void) +int get_clocks (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; u32 pci_sync_in; - u8 spmf; - u8 clkin_div; + u8 spmf; + u8 clkin_div; u32 sccr; u32 corecnf_tab_index; - u8 corepll; + u8 corepll; u32 lcrr; u32 csb_clk; -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) u32 tsec1_clk; u32 tsec2_clk; - u32 usbdr_clk; -#endif -#ifdef CONFIG_MPC834X - u32 usbmph_clk; -#endif u32 core_clk; - u32 i2c1_clk; -#if !defined(CONFIG_MPC832X) - u32 i2c2_clk; -#endif -#if defined(CONFIG_MPC8315) - u32 tdm_clk; -#endif -#if defined(CONFIG_MPC837X) - u32 sdhc_clk; -#endif + u32 usbmph_clk; + u32 usbdr_clk; + u32 i2c_clk; u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; - u32 mem_clk; -#if defined(CONFIG_MPC8360) - u32 mem_sec_clk; -#endif -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) - u32 qepmf; - u32 qepdf; - u32 qe_clk; - u32 brg_clk; -#endif -#if defined(CONFIG_MPC837X) - u32 pciexp1_clk; - u32 pciexp2_clk; -#endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) - u32 sata_clk; -#endif + u32 ddr_clk; - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); +#ifndef CFG_HRCW_HIGH +# error "CFG_HRCW_HIGH must be defined in board config file" +#endif /* CFG_HCWD_HIGH */ - if (im->reset.rcwh & HRCWH_PCI_HOST) { -#if defined(CONFIG_83XX_CLKIN) - pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div); -#else - pci_sync_in = 0xDEADBEEF; -#endif - } else { -#if defined(CONFIG_83XX_PCICLK) - pci_sync_in = CONFIG_83XX_PCICLK; -#else - pci_sync_in = 0xDEADBEEF; -#endif +#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST) + +# ifndef CONFIG_83XX_CLKIN +# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file" +# endif /* CONFIG_83XX_CLKIN */ +# ifdef CONFIG_83XX_PCICLK +# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred" +# endif /* CONFIG_83XX_PCICLK */ + + /* PCI Host Mode */ + if (!(im->reset.rcwh & RCWH_PCIHOST)) { + /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH + * the im->reset.rcwhr PCI Host Mode is disabled + * FIXME: findout if there is a way to issue some warning */ + return -2; + } + if (im->clk.spmr & SPMR_CKID) { + /* PCI Clock is half CONFIG_83XX_CLKIN */ + pci_sync_in = CONFIG_83XX_CLKIN / 2; + } + else { + pci_sync_in = CONFIG_83XX_CLKIN; } - spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT); - csb_clk = pci_sync_in * (1 + clkin_div) * spmf; +#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */ + +# ifdef CONFIG_83XX_CLKIN +# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred" +# endif /* CONFIG_83XX_CLKIN */ +# ifndef CONFIG_83XX_PCICLK +# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file" +# endif /* CONFIG_83XX_PCICLK */ + + /* PCI Agent Mode */ + if (im->reset.rcwh & RCWH_PCIHOST) { + /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH + * the im->reset.rcwhr PCI Host Mode is enabled */ + return -3; + } + pci_sync_in = CONFIG_83XX_PCICLK; + +#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */ + + /* we have up to date pci_sync_in */ + spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); + clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); + + if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) { + csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2; + } + else { + csb_clk = pci_sync_in * spmf * (1 + clkin_div); + } sccr = im->clk.sccr; - -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { case 0: tsec1_clk = 0; @@ -180,7 +192,62 @@ int get_clocks(void) break; default: /* unkown SCCR_TSEC1CM value */ - return -2; + return -4; + } + + switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { + case 0: + tsec2_clk = 0; + break; + case 1: + tsec2_clk = csb_clk; + break; + case 2: + tsec2_clk = csb_clk / 2; + break; + case 3: + tsec2_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_TSEC2CM value */ + return -5; + } + i2c_clk = tsec2_clk; + + switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { + case 0: + enc_clk = 0; + break; + case 1: + enc_clk = csb_clk; + break; + case 2: + enc_clk = csb_clk / 2; + break; + case 3: + enc_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_ENCCM value */ + return -6; + } + + switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { + case 0: + usbmph_clk = 0; + break; + case 1: + usbmph_clk = csb_clk; + break; + case 2: + usbmph_clk = csb_clk / 2; + break; + case 3: + usbmph_clk = csb_clk / 3; + break; + default: + /* unkown SCCR_USBMPHCM value */ + return -7; } switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { @@ -198,196 +265,17 @@ int get_clocks(void) break; default: /* unkown SCCR_USBDRCM value */ - return -3; - } -#endif - -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) - switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { - case 0: - tsec2_clk = 0; - break; - case 1: - tsec2_clk = csb_clk; - break; - case 2: - tsec2_clk = csb_clk / 2; - break; - case 3: - tsec2_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_TSEC2CM value */ - return -4; - } -#elif defined(CONFIG_MPC8313) - tsec2_clk = tsec1_clk; - - if (!(sccr & SCCR_TSEC1ON)) - tsec1_clk = 0; - if (!(sccr & SCCR_TSEC2ON)) - tsec2_clk = 0; -#endif - -#if defined(CONFIG_MPC834X) - switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { - case 0: - usbmph_clk = 0; - break; - case 1: - usbmph_clk = csb_clk; - break; - case 2: - usbmph_clk = csb_clk / 2; - break; - case 3: - usbmph_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_USBMPHCM value */ - return -5; - } - - if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) { - /* if USB MPH clock is not disabled and - * USB DR clock is not disabled then - * USB MPH & USB DR must have the same rate - */ - return -6; - } -#endif - switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { - case 0: - enc_clk = 0; - break; - case 1: - enc_clk = csb_clk; - break; - case 2: - enc_clk = csb_clk / 2; - break; - case 3: - enc_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_ENCCM value */ - return -7; - } - -#if defined(CONFIG_MPC837X) - switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) { - case 0: - sdhc_clk = 0; - break; - case 1: - sdhc_clk = csb_clk; - break; - case 2: - sdhc_clk = csb_clk / 2; - break; - case 3: - sdhc_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_SDHCCM value */ return -8; } -#endif -#if defined(CONFIG_MPC8315) - switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) { - case 0: - tdm_clk = 0; - break; - case 1: - tdm_clk = csb_clk; - break; - case 2: - tdm_clk = csb_clk / 2; - break; - case 3: - tdm_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_TDMCM value */ - return -8; - } -#endif -#if defined(CONFIG_MPC834X) - i2c1_clk = tsec2_clk; -#elif defined(CONFIG_MPC8360) - i2c1_clk = csb_clk; -#elif defined(CONFIG_MPC832X) - i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC831X) - i2c1_clk = enc_clk; -#elif defined(CONFIG_MPC837X) - i2c1_clk = sdhc_clk; -#endif -#if !defined(CONFIG_MPC832X) - i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ -#endif - -#if defined(CONFIG_MPC837X) - switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) { - case 0: - pciexp1_clk = 0; - break; - case 1: - pciexp1_clk = csb_clk; - break; - case 2: - pciexp1_clk = csb_clk / 2; - break; - case 3: - pciexp1_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_PCIEXP1CM value */ + if (usbmph_clk != 0 + && usbdr_clk != 0 + && usbmph_clk != usbdr_clk ) { + /* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */ return -9; } - switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) { - case 0: - pciexp2_clk = 0; - break; - case 1: - pciexp2_clk = csb_clk; - break; - case 2: - pciexp2_clk = csb_clk / 2; - break; - case 3: - pciexp2_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_PCIEXP2CM value */ - return -10; - } -#endif - -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) - switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) { - case 0: - sata_clk = 0; - break; - case 1: - sata_clk = csb_clk; - break; - case 2: - sata_clk = csb_clk / 2; - break; - case 3: - sata_clk = csb_clk / 3; - break; - default: - /* unkown SCCR_SATACM value */ - return -11; - } -#endif - - lbiu_clk = csb_clk * - (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); + lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; switch (lcrr) { case 2: @@ -397,19 +285,14 @@ int get_clocks(void) break; default: /* unknown lcrr */ - return -12; + return -10; } - mem_clk = csb_clk * - (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT)); - corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT; -#if defined(CONFIG_MPC8360) - mem_sec_clk = csb_clk * (1 + - ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT)); -#endif + ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); + corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); - if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) { + if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) { /* corecnf_tab_index is too high, possibly worng value */ return -11; } @@ -426,122 +309,56 @@ int get_clocks(void) core_clk = 2 * csb_clk; break; case _2_5x: - core_clk = (5 * csb_clk) / 2; + core_clk = ( 5 * csb_clk) / 2; break; case _3x: core_clk = 3 * csb_clk; break; default: /* unkown core to csb ratio */ - return -13; + return -12; } -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) - qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT; - qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT; - qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); - brg_clk = qe_clk / 2; -#endif - - gd->csb_clk = csb_clk; -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) - gd->tsec1_clk = tsec1_clk; - gd->tsec2_clk = tsec2_clk; - gd->usbdr_clk = usbdr_clk; -#endif -#if defined(CONFIG_MPC834X) + gd->csb_clk = csb_clk ; + gd->tsec1_clk = tsec1_clk ; + gd->tsec2_clk = tsec2_clk ; + gd->core_clk = core_clk ; gd->usbmph_clk = usbmph_clk; -#endif -#if defined(CONFIG_MPC8315) - gd->tdm_clk = tdm_clk; -#endif -#if defined(CONFIG_MPC837X) - gd->sdhc_clk = sdhc_clk; -#endif - gd->core_clk = core_clk; - gd->i2c1_clk = i2c1_clk; -#if !defined(CONFIG_MPC832X) - gd->i2c2_clk = i2c2_clk; -#endif - gd->enc_clk = enc_clk; - gd->lbiu_clk = lbiu_clk; - gd->lclk_clk = lclk_clk; - gd->mem_clk = mem_clk; -#if defined(CONFIG_MPC8360) - gd->mem_sec_clk = mem_sec_clk; -#endif -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) - gd->qe_clk = qe_clk; - gd->brg_clk = brg_clk; -#endif -#if defined(CONFIG_MPC837X) - gd->pciexp1_clk = pciexp1_clk; - gd->pciexp2_clk = pciexp2_clk; -#endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) - gd->sata_clk = sata_clk; -#endif - gd->pci_clk = pci_sync_in; - gd->cpu_clk = gd->core_clk; - gd->bus_clk = gd->csb_clk; - return 0; + gd->usbdr_clk = usbdr_clk ; + gd->i2c_clk = i2c_clk ; + gd->enc_clk = enc_clk ; + gd->lbiu_clk = lbiu_clk ; + gd->lclk_clk = lclk_clk ; + gd->ddr_clk = ddr_clk ; + gd->pci_clk = pci_sync_in; + gd->cpu_clk = gd->core_clk; + gd->bus_clk = gd->lbiu_clk; + return 0; } /******************************************** * get_bus_freq * return system bus freq in Hz *********************************************/ -ulong get_bus_freq(ulong dummy) +ulong get_bus_freq (ulong dummy) { return gd->csb_clk; } -int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +int print_clock_conf (void) { printf("Clock configuration:\n"); - printf(" Core: %4d MHz\n", gd->core_clk / 1000000); - printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); -#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) - printf(" QE: %4d MHz\n", gd->qe_clk / 1000000); - printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000); -#endif - printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000); - printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000); - printf(" DDR: %4ld MHz\n", gd->mem_clk / 1000000); -#if defined(CONFIG_MPC8360) - printf(" DDR Secondary: %4d MHz\n", gd->mem_sec_clk / 1000000); -#endif - printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000); - printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000); -#if !defined(CONFIG_MPC832X) - printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000); -#endif -#if defined(CONFIG_MPC8315) - printf(" TDM: %4d MHz\n", gd->tdm_clk / 1000000); -#endif -#if defined(CONFIG_MPC837X) - printf(" SDHC: %4d MHz\n", gd->sdhc_clk / 1000000); -#endif -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) - printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000); - printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000); - printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000); -#endif -#if defined(CONFIG_MPC834X) - printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000); -#endif -#if defined(CONFIG_MPC837X) - printf(" PCIEXP1: %4d MHz\n", gd->pciexp1_clk / 1000000); - printf(" PCIEXP2: %4d MHz\n", gd->pciexp2_clk / 1000000); -#endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) - printf(" SATA: %4d MHz\n", gd->sata_clk / 1000000); -#endif + printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000); + printf(" Core: %4d MHz\n",gd->core_clk/1000000); + debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000); + printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000); + debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000); + debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000); + debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000); + debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000); + debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000); + debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000); + return 0; } - -U_BOOT_CMD(clocks, 1, 0, do_clocks, - "clocks - print clock configuration\n", - " clocks\n" -); diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index c18217479..6e02cce79 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -2,7 +2,7 @@ * Copyright (C) 1998 Dan Malek * Copyright (C) 1999 Magnus Damm * Copyright (C) 2000, 2001,2002 Wolfgang Denk - * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved. + * Copyright 2004 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -77,11 +77,19 @@ END_GOT /* - * The Hard Reset Configuration Word (HRCW) table is in the first 64 - * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8 - * times so the processor can fetch it out of flash whether the flash - * is 8, 16, 32, or 64 bits wide (hardware trickery). + * Version string - must be in data segment because MPC83xx uses the + * first 256 bytes for the Hard Reset Configuration Word table (see + * below). Similarly, can't have the U-Boot Magic Number as the first + * thing in the image - don't know how this will affect the image tools, + * but I guess I'll find out soon. */ + .data + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii " ", CONFIG_IDENT_STRING, "\0" + .text #define _HRCW_TABLE_ENTRY(w) \ .fill 8,1,(((w)>>24)&0xff); \ @@ -92,25 +100,13 @@ _HRCW_TABLE_ENTRY(CFG_HRCW_LOW) _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH) -/* - * Magic number and version string - put it after the HRCW since it - * cannot be first in flash like it is in many other processors. - */ - .long 0x27051956 /* U-Boot Magic Number */ - - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii " ", CONFIG_IDENT_STRING, "\0" - #ifndef CONFIG_DEFAULT_IMMR #error CONFIG_DEFAULT_IMMR must be defined #endif /* CFG_DEFAULT_IMMR */ -#ifndef CFG_IMMR -#define CFG_IMMR CONFIG_DEFAULT_IMMR -#endif /* CFG_IMMR */ +#ifndef CFG_IMMRBAR +#define CFG_IMMRBAR CONFIG_DEFAULT_IMMR +#endif /* CFG_IMMRBAR */ /* * After configuration, a system reset exception is executed using the @@ -156,8 +152,8 @@ boot_cold: /* time t 3 */ nop boot_warm: /* time t 5 */ mfmsr r5 /* save msr contents */ - lis r3, CFG_IMMR@h - ori r3, r3, CFG_IMMR@l + lis r3, CFG_IMMRBAR@h + ori r3, r3, CFG_IMMRBAR@l stw r3, IMMRBAR(r4) /* Initialise the E300 processor core */ @@ -230,7 +226,7 @@ in_flash: GET_GOT /* initialize GOT access */ /* r3: IMMR */ - lis r3, CFG_IMMR@h + lis r3, CFG_IMMRBAR@h /* run low-level CPU init code (in Flash)*/ bl cpu_init_f @@ -263,7 +259,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -282,7 +278,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ @@ -450,7 +446,7 @@ init_e300_core: /* time t 10 */ mtspr SRR1, r3 /* Make SRR1 match MSR */ - lis r3, CFG_IMMR@h + lis r3, CFG_IMMRBAR@h #if defined(CONFIG_WATCHDOG) /* Initialise the Wathcdog values and reset it (if req) */ /*------------------------------------------------------*/ @@ -462,7 +458,7 @@ init_e300_core: /* time t 10 */ li r4, 0x556C sth r4, SWSRR@l(r3) - li r4, -0x55C7 + li r4, 0xAA39 sth r4, SWSRR@l(r3) #else /* Disable Wathcdog */ @@ -557,7 +553,7 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 -#ifdef CONFIG_HIGH_BATS +#if (CFG_HID2 & HID2_HBE) mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 @@ -568,7 +564,7 @@ invalidate_bats: mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 -#ifdef CONFIG_HIGH_BATS +#if (CFG_HID2 & HID2_HBE) mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 @@ -655,7 +651,7 @@ setup_bats: mtspr DBAT3U, r3 isync -#ifdef CONFIG_HIGH_BATS +#if (CFG_HID2 & HID2_HBE) /* IBAT 4 */ addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l @@ -840,16 +836,38 @@ get_pvr: mfspr r3, PVR blr - .globl ppcDWstore -ppcDWstore: - lfd 1, 0(r4) - stfd 1, 0(r3) +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 blr - .globl ppcDWload -ppcDWload: - lfd 1, 0(r3) - stfd 1, 0(r4) +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 blr /*-------------------------------------------------------------------*/ @@ -1171,7 +1189,7 @@ map_flash_by_law1: /* When booting from ROM (Flash or EPROM), clear the */ /* Address Mask in OR0 so ROM appears everywhere */ /*----------------------------------------------------*/ - lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */ + lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */ lwz r4, OR0@l(r3) li r5, 0x7fff /* r5 <= 0x00007FFFF */ and r4, r4, r5 @@ -1196,15 +1214,8 @@ map_flash_by_law1: lis r4, (CFG_FLASH_BASE)@h ori r4, r4, (CFG_FLASH_BASE)@l stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */ - - /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */ - lis r4, (0x80000012)@h - ori r4, r4, (0x80000012)@l - li r5, CFG_FLASH_SIZE -1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ - addi r4, r4, 1 - bne 1b - + lis r4, (0x80000016)@h + ori r4, r4, (0x80000016)@l stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */ blr @@ -1223,23 +1234,17 @@ remap_flash_by_law0: stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ lwz r4, OR0(r3) - lis r5, ~((CFG_FLASH_SIZE << 4) - 1) + lis r5, 0xFF80 /* 8M */ or r4, r4, r5 - stw r4, OR0(r3) + stw r4, OR0(r3) /* OR0 <= OR0 | 0xFF800000 */ lis r4, (CFG_FLASH_BASE)@h ori r4, r4, (CFG_FLASH_BASE)@l stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */ - /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR0 */ - lis r4, (0x80000012)@h - ori r4, r4, (0x80000012)@l - li r5, CFG_FLASH_SIZE -1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ - addi r4, r4, 1 - bne 1b - stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */ - + lis r4, (0x80000016)@h + ori r4, r4, (0x80000016)@l + stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= 8MB Flash Size */ xor r4, r4, r4 stw r4, LBLAWBAR1(r3) diff --git a/cpu/mpc83xx/traps.c b/cpu/mpc83xx/traps.c index dfd6c0386..44345afbf 100644 --- a/cpu/mpc83xx/traps.c +++ b/cpu/mpc83xx/traps.c @@ -1,8 +1,5 @@ /* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * linux/arch/ppc/kernel/traps.c * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -18,6 +15,19 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Change log: + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@cs.anu.edu.au) + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) */ /* @@ -140,7 +150,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -176,7 +186,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -188,7 +198,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -200,7 +210,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -213,7 +223,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -222,7 +232,7 @@ UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -231,7 +241,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index adbc58582..5298dc113 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2002,2003 Motorola Inc. # Xianghua Xiao,X.Xiao@motorola.com # @@ -26,31 +23,23 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o resetvec.o -SOBJS-$(CONFIG_MP) += release.o -SOBJS = $(SOBJS-y) -COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ - pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \ - $(COBJS-y) +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ + pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o +OBJS = $(COBJS) -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c index b0ecd2550..3504d50ca 100644 --- a/cpu/mpc85xx/commproc.c +++ b/cpu/mpc85xx/commproc.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; void m8560_cpm_reset(void) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *immr = (immap_t *)CFG_IMMR; volatile ulong count; gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); @@ -50,11 +50,11 @@ m8560_cpm_reset(void) /* * Reset CPM */ - cpm->im_cpm_cp.cpcr = CPM_CR_RST; + immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST; count = 0; do { /* Spin until command processed */ __asm__ __volatile__ ("eieio"); - } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); + } while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000); } /* Allocate some memory from the dual ported ram. @@ -64,7 +64,7 @@ m8560_cpm_reset(void) uint m8560_cpm_dpalloc(uint size, uint align) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *immr = (immap_t *)CFG_IMMR; uint retloc; uint align_mask, off; uint savebase; @@ -86,7 +86,7 @@ m8560_cpm_dpalloc(uint size, uint align) retloc = gd->dp_alloc_base; gd->dp_alloc_base += size; - memset((void *)&(cpm->im_dprambase[retloc]), 0, size); + memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size); return(retloc); } @@ -120,16 +120,16 @@ m8560_cpm_hostalloc(uint size, uint align) void m8560_cpm_setbrg(uint brg, uint rate) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *immr = (immap_t *)CFG_IMMR; volatile uint *bp; /* This is good enough to get SMCs running..... */ if (brg < 4) { - bp = (uint *)&(cpm->im_cpm_brg1.brgc1); + bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); } else { - bp = (uint *)&(cpm->im_cpm_brg2.brgc5); + bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); brg -= 4; } bp += brg; @@ -142,16 +142,16 @@ m8560_cpm_setbrg(uint brg, uint rate) void m8560_cpm_fastbrg(uint brg, uint rate, int div16) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *immr = (immap_t *)CFG_IMMR; volatile uint *bp; /* This is good enough to get SMCs running..... */ if (brg < 4) { - bp = (uint *)&(cpm->im_cpm_brg1.brgc1); + bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); } else { - bp = (uint *)&(cpm->im_cpm_brg2.brgc5); + bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); brg -= 4; } bp += brg; @@ -167,14 +167,14 @@ m8560_cpm_fastbrg(uint brg, uint rate, int div16) void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *immr = (immap_t *)CFG_IMMR; volatile uint *bp; if (brg < 4) { - bp = (uint *)&(cpm->im_cpm_brg1.brgc1); + bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1); } else { - bp = (uint *)&(cpm->im_cpm_brg2.brgc5); + bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5); brg -= 4; } bp += brg; diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk index 9e574a20d..612107434 100644 --- a/cpu/mpc85xx/config.mk +++ b/cpu/mpc85xx/config.mk @@ -23,6 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 \ - -Wa,-me500 -msoft-float -mno-string -PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe) +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 -ffixed-r29 -Wa,-me500 -msoft-float -mno-string diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bde8e5670..f7fe22e3e 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004,2007,2008 Freescale Semiconductor, Inc. + * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -29,45 +29,8 @@ #include #include #include -#include -DECLARE_GLOBAL_DATA_PTR; - -struct cpu_type cpu_type_list [] = { - CPU_TYPE_ENTRY(8533, 8533), - CPU_TYPE_ENTRY(8533, 8533_E), - CPU_TYPE_ENTRY(8540, 8540), - CPU_TYPE_ENTRY(8541, 8541), - CPU_TYPE_ENTRY(8541, 8541_E), - CPU_TYPE_ENTRY(8543, 8543), - CPU_TYPE_ENTRY(8543, 8543_E), - CPU_TYPE_ENTRY(8544, 8544), - CPU_TYPE_ENTRY(8544, 8544_E), - CPU_TYPE_ENTRY(8545, 8545), - CPU_TYPE_ENTRY(8545, 8545_E), - CPU_TYPE_ENTRY(8547, 8547_E), - CPU_TYPE_ENTRY(8548, 8548), - CPU_TYPE_ENTRY(8548, 8548_E), - CPU_TYPE_ENTRY(8555, 8555), - CPU_TYPE_ENTRY(8555, 8555_E), - CPU_TYPE_ENTRY(8560, 8560), - CPU_TYPE_ENTRY(8567, 8567), - CPU_TYPE_ENTRY(8567, 8567_E), - CPU_TYPE_ENTRY(8568, 8568), - CPU_TYPE_ENTRY(8568, 8568_E), - CPU_TYPE_ENTRY(8572, 8572), - CPU_TYPE_ENTRY(8572, 8572_E), -}; - -struct cpu_type *identify_cpu(u32 ver) -{ - int i; - for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) - if (cpu_type_list[i].soc_ver == ver) - return &cpu_type_list[i]; - - return NULL; -} +/* ------------------------------------------------------------------------- */ int checkcpu (void) { @@ -78,31 +41,36 @@ int checkcpu (void) uint fam; uint ver; uint major, minor; - struct cpu_type *cpu; -#ifdef CONFIG_DDR_CLK_FREQ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; -#else - u32 ddr_ratio = 0; -#endif svr = get_svr(); - ver = SVR_SOC_VER(svr); + ver = SVR_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); puts("CPU: "); - - cpu = identify_cpu(ver); - if (cpu) { - puts(cpu->name); - - if (IS_E_PROCESSOR(svr)) - puts("E"); - } else { + switch (ver) { + case SVR_8540: + puts("8540"); + break; + case SVR_8541: + puts("8541"); + break; + case SVR_8555: + puts("8555"); + break; + case SVR_8560: + puts("8560"); + break; + case SVR_8548: + puts("8548"); + break; + case SVR_8548_E: + puts("8548_E"); + break; + default: puts("Unknown"); + break; } - printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); @@ -125,36 +93,23 @@ int checkcpu (void) get_sys_info(&sysinfo); puts("Clock Configuration:\n"); - printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); - printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); - - switch (ddr_ratio) { - case 0x0: - printf(" DDR:%4lu MHz (%lu MT/s data rate), ", - DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); - break; - case 0x7: - printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", - DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000)); - break; - default: - printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", - DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); - break; - } + printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); + printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000); + printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); #if defined(CFG_LBC_LCRR) lcrr = CFG_LBC_LCRR; #else { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc= &immap->im_lbc; lcrr = lbc->lcrr; } #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) +#ifdef CONFIG_MPC8548 /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. @@ -162,14 +117,15 @@ int checkcpu (void) clkdiv *= 2; #endif printf("LBC:%4lu MHz\n", - DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv); + sysinfo.freqSystemBus / 1000000 / clkdiv); } else { printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); } -#ifdef CONFIG_CPM2 - printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); -#endif + if (ver == SVR_8560) { + printf("CPM: %lu Mhz\n", + sysinfo.freqSystemBus / 1000000); + } puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); @@ -181,30 +137,11 @@ int checkcpu (void) int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) { - uint pvr; - uint ver; - unsigned long val, msr; - - pvr = get_pvr(); - ver = PVR_VER(pvr); - - if (ver & 1){ - /* e500 v2 core has reset control register */ - volatile unsigned int * rstcr; - rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0); - *rstcr = 0x2; /* HRESET_REQ */ - udelay(100); - } - /* - * Fallthrough if the code above failed * Initiate hard reset in debug control register DBCR0 * Make sure MSR[DE] = 1 */ - - msr = mfmsr (); - msr |= MSR_DE; - mtmsr (msr); + unsigned long val; val = mfspr(DBCR0); val |= 0x70000000; @@ -219,7 +156,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { - return (gd->bus_clk + 4UL)/8UL; + + sys_info_t sys_info; + + get_sys_info(&sys_info); + return ((sys_info.freqSystemBus + 7L) / 8L); } @@ -239,25 +180,26 @@ reset_85xx_watchdog(void) * Clear TSR(WIS) bit by writing 1 */ unsigned long val; - val = mfspr(SPRN_TSR); - val |= TSR_WIS; - mtspr(SPRN_TSR, val); + val = mfspr(tsr); + val |= 0x40000000; + mtspr(tsr, val); } #endif /* CONFIG_WATCHDOG */ #if defined(CONFIG_DDR_ECC) void dma_init(void) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; dma->satr0 = 0x02c40000; dma->datr0 = 0x02c40000; - dma->sr0 = 0xfffffff; /* clear any errors */ asm("sync; isync; msync"); return; } uint dma_check(void) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; volatile uint status = dma->sr0; /* While the channel is busy, spin */ @@ -265,10 +207,6 @@ uint dma_check(void) { status = dma->sr0; } - /* clear MR0[CS] channel start bit */ - dma->mr0 &= 0x00000001; - asm("sync;isync;msync"); - if (status != 0) { printf ("DMA Error: status = %x\n", status); } @@ -276,7 +214,8 @@ uint dma_check(void) { } int dma_xfer(void *dest, uint count, void *src) { - volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_dma_t *dma = &immap->im_dma; dma->dar0 = (uint) dest; dma->sar0 = (uint) src; @@ -288,98 +227,3 @@ int dma_xfer(void *dest, uint count, void *src) { return dma_check(); } #endif -/* - * Configures a UPM. Currently, the loop fields in MxMR (RLF, WLF and TLF) - * are hardcoded as "1"."size" is the number or entries, not a sizeof. - */ -void upmconfig (uint upm, uint * table, uint size) -{ - int i, mdr, mad, old_mad = 0; - volatile u32 *mxmr; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - int loopval = 0x00004440; - volatile u32 *brp,*orp; - volatile u8* dummy = NULL; - int upmmask; - - switch (upm) { - case UPMA: - mxmr = &lbc->mamr; - upmmask = BR_MS_UPMA; - break; - case UPMB: - mxmr = &lbc->mbmr; - upmmask = BR_MS_UPMB; - break; - case UPMC: - mxmr = &lbc->mcmr; - upmmask = BR_MS_UPMC; - break; - default: - printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); - hang(); - } - - /* Find the address for the dummy write transaction */ - for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; - i++, brp += 2, orp += 2) { - - /* Look for a valid BR with selected UPM */ - if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) { - dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT); - break; - } - } - - if (i == 8) { - printf("Error: %s() could not find matching BR\n", __FUNCTION__); - hang(); - } - - for (i = 0; i < size; i++) { - /* 1 */ - out_be32(mxmr, loopval | 0x10000000 | i); /* OP_WRITE */ - /* 2 */ - out_be32(&lbc->mdr, table[i]); - /* 3 */ - mdr = in_be32(&lbc->mdr); - /* 4 */ - *(volatile u8 *)dummy = 0; - /* 5 */ - do { - mad = in_be32(mxmr) & 0x3f; - } while (mad <= old_mad && !(!mad && i == (size-1))); - old_mad = mad; - } - out_be32(mxmr, loopval); /* OP_NORMAL */ -} - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIGMPC85XX_FEC) -/* Default initializations for TSEC controllers. To override, - * create a board-specific function called: - * int board_eth_init(bd_t *bis) - */ - -extern int tsec_initialize(bd_t * bis, int index, char *devname); - -int cpu_eth_init(bd_t *bis) -{ -#if defined(CONFIG_TSEC1) - tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); -#endif -#if defined(CONFIG_TSEC2) - tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); -#endif -#if defined(CONFIG_MPC85XX_FEC) - tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); -#else -#if defined(CONFIG_TSEC3) - tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); -#endif -#if defined(CONFIG_TSEC4) - tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); -#endif -#endif - return 0; -} -#endif diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 4feb7519a..c12b47b58 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -1,6 +1,4 @@ /* - * Copyright 2007 Freescale Semiconductor. - * * (C) Copyright 2003 Motorola Inc. * Modified by Xianghua Xiao, X.Xiao@motorola.com * @@ -31,38 +29,11 @@ #include #include #include -#include -#include -#include "mp.h" DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_QE -extern qe_iop_conf_t qe_iop_conf_tab[]; -extern void qe_config_iopin(u8 port, u8 pin, int dir, - int open_drain, int assign); -extern void qe_init(uint qe_base); -extern void qe_reset(void); - -static void config_qe_ioports(void) -{ - u8 port, pin; - int dir, open_drain, assign; - int i; - - for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { - port = qe_iop_conf_tab[i].port; - pin = qe_iop_conf_tab[i].pin; - dir = qe_iop_conf_tab[i].dir; - open_drain = qe_iop_conf_tab[i].open_drain; - assign = qe_iop_conf_tab[i].assign; - qe_config_iopin(port, pin, dir, open_drain, assign); - } -} -#endif - #ifdef CONFIG_CPM2 -void config_8560_ioports (volatile ccsr_cpm_t * cpm) +static void config_8560_ioports (volatile immap_t * immr) { int portnum; @@ -102,7 +73,7 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) } if (pmsk != 0) { - volatile ioport_t *iop = ioport_addr (cpm, portnum); + volatile ioport_t *iop = ioport_addr (immr, portnum); uint tpmsk = ~pmsk; /* @@ -125,40 +96,6 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) } #endif -/* We run cpu_init_early_f in AS = 1 */ -void cpu_init_early_f(void) -{ - set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 1, 0, BOOKE_PAGESZ_4K, 0); - - /* set up CCSR if we want it moved */ -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) - { - u32 temp; - - set_tlb(0, CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_DEFAULT, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 1, 1, BOOKE_PAGESZ_4K, 0); - - temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); - out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12); - - temp = in_be32((volatile u32 *)CFG_CCSRBAR); - } -#endif - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); - - init_laws(); - invalidate_tlb(0); - init_tlbs(); -} - /* * Breathe some life into the CPU... * @@ -168,14 +105,19 @@ void cpu_init_early_f(void) void cpu_init_f (void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *memctl = &immap->im_lbc; extern void m8560_cpm_reset (void); - disable_tlb(14); - disable_tlb(15); + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + #ifdef CONFIG_CPM2 - config_8560_ioports((ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR); + config_8560_ioports(immap); #endif /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary @@ -190,23 +132,22 @@ void cpu_init_f (void) #endif /* now restrict to preliminary range */ - /* if cs1 is already set via debugger, leave cs0/cs1 alone */ - if (! memctl->br1 & 1) { #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM) - memctl->br0 = CFG_BR0_PRELIM; - memctl->or0 = CFG_OR0_PRELIM; + memctl->br0 = CFG_BR0_PRELIM; + memctl->or0 = CFG_OR0_PRELIM; #endif #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM) - memctl->or1 = CFG_OR1_PRELIM; - memctl->br1 = CFG_BR1_PRELIM; + memctl->or1 = CFG_OR1_PRELIM; + memctl->br1 = CFG_BR1_PRELIM; #endif - } +#if !defined(CONFIG_MPC85xx) #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM) memctl->or2 = CFG_OR2_PRELIM; memctl->br2 = CFG_BR2_PRELIM; #endif +#endif #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM) memctl->or3 = CFG_OR3_PRELIM; @@ -236,11 +177,6 @@ void cpu_init_f (void) #if defined(CONFIG_CPM2) m8560_cpm_reset(); #endif -#ifdef CONFIG_QE - /* Config QE ioports */ - config_qe_ioports(); -#endif - } @@ -250,91 +186,52 @@ void cpu_init_f (void) * The newer 8548, etc, parts have twice as much cache, but * use the same bit-encoding as the older 8555, etc, parts. * + * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()? */ int cpu_init_r(void) { - puts ("L2: "); - #if defined(CONFIG_L2_CACHE) - volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache; volatile uint cache_ctl; uint svr, ver; - uint l2srbar; - u32 l2siz_field; svr = get_svr(); - ver = SVR_SOC_VER(svr); + ver = SVR_VER(svr); asm("msync;isync"); cache_ctl = l2cache->l2ctl; - l2siz_field = (cache_ctl >> 28) & 0x3; - switch (l2siz_field) { - case 0x0: - printf(" unknown size (0x%08x)\n", cache_ctl); + switch (cache_ctl & 0x30000000) { + case 0x20000000: + if (ver == SVR_8548 || ver == SVR_8548_E) { + printf ("L2 cache 512KB:"); + } else { + printf ("L2 cache 256KB:"); + } + break; + case 0x00000000: + case 0x10000000: + case 0x30000000: + default: + printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); return -1; - break; - case 0x1: - if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) { - puts("128 KB "); - /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ - cache_ctl = 0xc4000000; - } else { - puts("256 KB "); - cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ - } - break; - case 0x2: - if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) { - puts("256 KB "); - /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ - cache_ctl = 0xc8000000; - } else { - puts ("512 KB "); - /* set L2E=1, L2I=1, & L2SRAM=0 */ - cache_ctl = 0xc0000000; - } - break; - case 0x3: - puts("1024 KB "); - /* set L2E=1, L2I=1, & L2SRAM=0 */ - cache_ctl = 0xc0000000; - break; } - if (l2cache->l2ctl & 0x80000000) { - puts("already enabled"); - l2srbar = l2cache->l2srbar0; -#ifdef CFG_INIT_L2_ADDR - if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { - l2srbar = CFG_INIT_L2_ADDR; - l2cache->l2srbar0 = l2srbar; - printf("moving to 0x%08x", CFG_INIT_L2_ADDR); - } -#endif /* CFG_INIT_L2_ADDR */ - puts("\n"); - } else { - asm("msync;isync"); - l2cache->l2ctl = cache_ctl; /* invalidate & enable */ - asm("msync;isync"); - puts("enabled\n"); - } + asm("msync;isync"); + l2cache->l2ctl = 0x68000000; /* invalidate */ + cache_ctl = l2cache->l2ctl; + asm("msync;isync"); + + l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */ + cache_ctl = l2cache->l2ctl; + asm("msync;isync"); + + printf(" enabled\n"); #else - puts("disabled\n"); -#endif -#ifdef CONFIG_QE - uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */ - qe_init(qe_base); - qe_reset(); + printf("L2 cache: disabled\n"); #endif -#if defined(CONFIG_MP) - setup_mp(); -#endif return 0; } diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index bd62aab9f..d15d24249 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -48,13 +48,13 @@ #include #include -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) #include #endif #if defined(CONFIG_CPM2) -#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \ +#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \ defined(CONFIG_NET_MULTI) static struct ether_fcc_info_s @@ -230,8 +230,8 @@ static int fec_init(struct eth_device* dev, bd_t *bis) { struct ether_fcc_info_s * info = dev->priv; int i; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; - volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp); fcc_enet_t *pram_ptr; unsigned long mem_addr; @@ -242,35 +242,35 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (1-2): ioports have been set up already */ /* 28.9 - (3): connect FCC's tx and rx clocks */ - cpm->im_cpm_mux.cmxuar = 0; /* ATM */ - cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | + immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */ + immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | info->cmxfcr_value; /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; + immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; } /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 1){ - cpm->im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } else if (info->ether_index == 2){ - cpm->im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; + immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC; } /* 28.9 - (6): FDSR: Ethernet Syn */ if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fdsr = 0xD555; + immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555; } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.fdsr = 0xD555; + immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555; } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.fdsr = 0xD555; + immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555; } /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ @@ -296,7 +296,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; /* 28.9 - (7): initialize parameter ram */ - pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]); + pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]); /* clear whole structure to make sure all reserved fields are zero */ memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); @@ -385,14 +385,14 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (8)(9): clear out events in FCCE */ /* 28.9 - (9): FCCM: mask all events */ if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fcce = ~0x0; - cpm->im_cpm_fcc1.fccm = 0; + immr->im_cpm.im_cpm_fcc1.fcce = ~0x0; + immr->im_cpm.im_cpm_fcc1.fccm = 0; } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.fcce = ~0x0; - cpm->im_cpm_fcc2.fccm = 0; + immr->im_cpm.im_cpm_fcc2.fcce = ~0x0; + immr->im_cpm.im_cpm_fcc2.fccm = 0; } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.fcce = ~0x0; - cpm->im_cpm_fcc3.fccm = 0; + immr->im_cpm.im_cpm_fcc3.fcce = ~0x0; + immr->im_cpm.im_cpm_fcc3.fccm = 0; } /* 28.9 - (10-12): we don't use ethernet interrupts */ @@ -413,11 +413,11 @@ static int fec_init(struct eth_device* dev, bd_t *bis) /* 28.9 - (14): enable tx/rx in gfmr */ if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; + immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; } return 1; @@ -426,15 +426,15 @@ static int fec_init(struct eth_device* dev, bd_t *bis) static void fec_halt(struct eth_device* dev) { struct ether_fcc_info_s * info = dev->priv; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *immr = (immap_t *)CFG_IMMR; /* write GFMR: disable tx/rx */ if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); } else if(info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); } else if(info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); + immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); } } @@ -458,7 +458,7 @@ int fec_initialize(bd_t *bis) eth_register(dev); -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \ && defined(CONFIG_BITBANGMII) miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); @@ -468,6 +468,6 @@ int fec_initialize(bd_t *bis) return 1; } -#endif +#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */ #endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/i2c.c b/cpu/mpc85xx/i2c.c new file mode 100644 index 000000000..32dcf5d47 --- /dev/null +++ b/cpu/mpc85xx/i2c.c @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao + * Adapted for Motorola 85xx chip. + * + * (C) Copyright 2003 + * Gleb Natapov + * Some bits are taken from linux driver writen by adrian@humboldt.co.uk + * + * Hardware I2C driver for MPC107 PCI bridge. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_HARD_I2C +#include + +#define TIMEOUT (CFG_HZ/4) + +#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000)) + +#define I2CADR &I2C_Addr[0] +#define I2CFDR &I2C_Addr[4] +#define I2CCCR &I2C_Addr[8] +#define I2CCSR &I2C_Addr[12] +#define I2CCDR &I2C_Addr[16] +#define I2CDFSRR &I2C_Addr[20] + +#define I2C_READ 1 +#define I2C_WRITE 0 + +void +i2c_init(int speed, int slaveadd) +{ + /* stop I2C controller */ + writeb(0x0, I2CCCR); + + /* set clock */ + writeb(0x3f, I2CFDR); + + /* set default filter */ + writeb(0x10,I2CDFSRR); + + /* write slave address */ + writeb(slaveadd, I2CADR); + + /* clear status register */ + writeb(0x0, I2CCSR); + + /* start I2C controller */ + writeb(MPC85xx_I2CCR_MEN, I2CCCR); +} + +static __inline__ int +i2c_wait4bus (void) +{ + ulong timeval = get_timer (0); + + while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) { + if (get_timer (timeval) > TIMEOUT) { + return -1; + } + } + + return 0; +} + +static __inline__ int +i2c_wait (int write) +{ + u32 csr; + ulong timeval = get_timer (0); + + do { + csr = readb(I2CCSR); + + if (!(csr & MPC85xx_I2CSR_MIF)) + continue; + + writeb(0x0, I2CCSR); + + if (csr & MPC85xx_I2CSR_MAL) { + debug("i2c_wait: MAL\n"); + return -1; + } + + if (!(csr & MPC85xx_I2CSR_MCF)) { + debug("i2c_wait: unfinished\n"); + return -1; + } + + if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } + + return 0; + } while (get_timer (timeval) < TIMEOUT); + + debug("i2c_wait: timed out\n"); + return -1; +} + +static __inline__ int +i2c_write_addr (u8 dev, u8 dir, int rsta) +{ + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX | + (rsta?MPC85xx_I2CCR_RSTA:0), + I2CCCR); + + writeb((dev << 1) | dir, I2CCDR); + + if (i2c_wait (I2C_WRITE) < 0) + return 0; + + return 1; +} + +static __inline__ int +__i2c_write (u8 *data, int length) +{ + int i; + + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, + I2CCCR); + + for (i=0; i < length; i++) { + writeb(data[i], I2CCDR); + + if (i2c_wait (I2C_WRITE) < 0) + break; + } + + return i; +} + +static __inline__ int +__i2c_read (u8 *data, int length) +{ + int i; + + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | + ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), + I2CCCR); + + /* dummy read */ + readb(I2CCDR); + + for (i=0; i < length; i++) { + if (i2c_wait (I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | + MPC85xx_I2CCR_TXAK, + I2CCCR); + + /* Generate stop on last byte */ + if (i == length - 1) + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR); + + data[i] = readb(I2CCDR); + } + + return i; +} + +int +i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + if (i2c_write_addr (dev, I2C_READ, 1) == 0) + goto exit; + + i = __i2c_read (data, length); + + exit: + writeb(MPC85xx_I2CCR_MEN, I2CCCR); + + return !(i == length); +} + +int +i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) +{ + int i = 0; + u8 *a = (u8*)&addr; + + if (i2c_wait4bus () < 0) + goto exit; + + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; + + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; + + i = __i2c_write (data, length); + + exit: + writeb(MPC85xx_I2CCR_MEN, I2CCCR); + + return !(i == length); +} + +int i2c_probe (uchar chip) +{ + int tmp; + + /* + * Try to read the first location of the chip. The underlying + * driver doesn't appear to support sending just the chip address + * and looking for an back. + */ + udelay(10000); + return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); +} + +uchar i2c_reg_read (uchar i2c_addr, uchar reg) +{ + uchar buf[1]; + + i2c_read (i2c_addr, reg, 1, buf, 1); + + return (buf[0]); +} + +void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write (i2c_addr, reg, 1, &val, 1); +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index 4fe1facf4..832781bab 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -80,46 +80,15 @@ int disable_interrupts (void) int interrupt_init (void) { - volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + volatile immap_t *immr = (immap_t *)CFG_IMMR; - pic->gcr = MPC85xx_PICGCR_RST; - while (pic->gcr & MPC85xx_PICGCR_RST); - pic->gcr = MPC85xx_PICGCR_M; + immr->im_pic.gcr = MPC85xx_PICGCR_RST; + while (immr->im_pic.gcr & MPC85xx_PICGCR_RST); + immr->im_pic.gcr = MPC85xx_PICGCR_M; decrementer_count = get_tbclk() / CFG_HZ; mtspr(SPRN_TCR, TCR_PIE); set_dec (decrementer_count); set_msr (get_msr () | MSR_EE); - -#ifdef CONFIG_INTERRUPTS - pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ - debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); - - pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ - debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2); - - pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ - debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3); - -#ifdef CONFIG_PCI1 - pic->iivpr8 = 0x810008; /* enable pci1 interrupts */ - debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8); -#endif -#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) - pic->iivpr9 = 0x810009; /* enable pci1 interrupts */ - debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9); -#endif -#ifdef CONFIG_PCIE1 - pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */ - debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10); -#endif -#ifdef CONFIG_PCIE3 - pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */ - debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11); -#endif - - pic->ctpr=0; /* 40080 clear current task priority register */ -#endif - return (0); } @@ -175,7 +144,7 @@ void set_timer (ulong t) timestamp = t; } -#if defined(CONFIG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) /******************************************************************************* * @@ -190,4 +159,4 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index a5060cdec..a94493e08 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -29,81 +29,20 @@ #include #include + #if defined(CONFIG_PCI) -static struct pci_controller *pci_hose; - void -pci_mpc85xx_init(struct pci_controller *board_hose) +pci_mpc85xx_init(struct pci_controller *hose) { + volatile immap_t *immap = (immap_t *)CFG_CCSRBAR; + volatile ccsr_pcix_t *pcix = &immap->im_pcix; + u16 reg16; - u32 dev; - - volatile ccsr_pcix_t *pcix = (void *)(CFG_MPC85xx_PCIX_ADDR); -#ifdef CONFIG_MPC85XX_PCI2 - volatile ccsr_pcix_t *pcix2 = (void *)(CFG_MPC85xx_PCIX2_ADDR); -#endif - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - struct pci_controller * hose; - - pci_hose = board_hose; - - hose = &pci_hose[0]; hose->first_busno = 0; hose->last_busno = 0xff; - pci_setup_indirect(hose, - (CFG_IMMR+0x8000), - (CFG_IMMR+0x8004)); - - /* - * Hose scan. - */ - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - - if (!(gur->pordevsr & PORDEVSR_PCI)) { - /* PCI-X init */ - if (CONFIG_SYS_CLK_FREQ < 66000000) - printf("PCI-X will only work at 66 MHz\n"); - - reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ - | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; - pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16); - } - - pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcix->potear1 = 0x00000000; - pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff; - pcix->powbear1 = 0x00000000; - pcix->powar1 = (POWAR_EN | POWAR_MEM_READ | - POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1)); - - pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pcix->potear2 = 0x00000000; - pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff; - pcix->powbear2 = 0x00000000; - pcix->powar2 = (POWAR_EN | POWAR_IO_READ | - POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1)); - - pcix->pitar1 = 0x00000000; - pcix->piwbar1 = 0x00000000; - pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | - PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); - - pcix->powar3 = 0; - pcix->powar4 = 0; - pcix->piwar2 = 0; - pcix->piwar3 = 0; - pci_set_region(hose->regions + 0, CFG_PCI1_MEM_BASE, CFG_PCI1_MEM_PHYS, @@ -118,8 +57,42 @@ pci_mpc85xx_init(struct pci_controller *board_hose) hose->region_count = 2; + pci_setup_indirect(hose, + (CFG_IMMR+0x8000), + (CFG_IMMR+0x8004)); + + pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->potear1 = 0x00000000; + pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; + pcix->powbear1 = 0x00000000; + pcix->powar1 = 0x8004401c; /* 512M MEM space */ + + pcix->potar2 = 0x00000000; + pcix->potear2 = 0x00000000; + pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; + pcix->powbear2 = 0x00000000; + pcix->powar2 = 0x80088017; /* 16M IO space */ + + pcix->pitar1 = 0x00000000; + pcix->piwbar1 = 0x00000000; + pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem, + * Snoop R/W, 2G */ + + /* + * Hose scan. + */ pci_register_hose(hose); + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) /* * This is a SW workaround for an apparent HW problem @@ -137,78 +110,13 @@ pci_mpc85xx_init(struct pci_controller *board_hose) u8 header_type; pci_hose_read_config_byte(hose, - PCI_BDF(0,BRIDGE_ID,0), + PCI_BDF(0,17,0), PCI_HEADER_TYPE, &header_type); } #endif hose->last_busno = pci_hose_scan(hose); - -#ifdef CONFIG_MPC85XX_PCI2 - hose = &pci_hose[1]; - - hose->first_busno = pci_hose[0].last_busno + 1; - hose->last_busno = 0xff; - - pci_setup_indirect(hose, - (CFG_IMMR+0x9000), - (CFG_IMMR+0x9004)); - - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - - pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff; - pcix2->potear1 = 0x00000000; - pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff; - pcix2->powbear1 = 0x00000000; - pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ | - POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1)); - - pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff; - pcix2->potear2 = 0x00000000; - pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff; - pcix2->powbear2 = 0x00000000; - pcix2->powar2 = (POWAR_EN | POWAR_IO_READ | - POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1)); - - pcix2->pitar1 = 0x00000000; - pcix2->piwbar1 = 0x00000000; - pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | - PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G); - - pcix2->powar3 = 0; - pcix2->powar4 = 0; - pcix2->piwar2 = 0; - pcix2->piwar3 = 0; - - pci_set_region(hose->regions + 0, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, - PCI_REGION_MEM); - - pci_set_region(hose->regions + 1, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 2; - - /* - * Hose scan. - */ - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); -#endif } + #endif /* CONFIG_PCI */ diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c index 7ee3cc823..4e925f8be 100644 --- a/cpu/mpc85xx/serial_scc.c +++ b/cpu/mpc85xx/serial_scc.c @@ -88,17 +88,17 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *im = (immap_t *)CFG_IMMR; volatile ccsr_cpm_scc_t *sp; volatile scc_uart_t *up; volatile cbd_t *tbdf, *rbdf; - volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); + volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp); uint dpaddr; /* initialize pointers to SCC */ - sp = (ccsr_cpm_scc_t *) &(cpm->im_cpm_scc[SCC_INDEX]); - up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); + sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]); + up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); /* Disable transmitter/receiver. */ @@ -107,8 +107,8 @@ int serial_init (void) /* put the SCC channel into NMSI (non multiplexd serial interface) * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15). */ - cpm->im_cpm_mux.cmxscr = \ - (cpm->im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; + im->im_cpm.im_cpm_mux.cmxscr = \ + (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE; /* Set up the baud rate generator. */ @@ -123,7 +123,7 @@ int serial_init (void) /* Set the physical address of the host memory buffers in * the buffer descriptors. */ - rbdf = (cbd_t *)&(cpm->im_dprambase[dpaddr]); + rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]); rbdf->cbd_bufaddr = (uint) (rbdf+2); rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP; tbdf = rbdf + 1; @@ -201,13 +201,14 @@ serial_putc(const char c) { volatile scc_uart_t *up; volatile cbd_t *tbdf; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *im; if (c == '\n') serial_putc ('\r'); - up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); - tbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_tbase]); + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); + tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]); /* Wait for last character to go. */ @@ -234,11 +235,12 @@ serial_getc(void) { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *im; unsigned char c; - up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); - rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); + rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); /* Wait for character to show up. */ @@ -258,10 +260,11 @@ serial_tstc() { volatile cbd_t *rbdf; volatile scc_uart_t *up; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *im; - up = (scc_uart_t *)&(cpm->im_dprambase[PROFF_SCC]); - rbdf = (cbd_t *)&(cpm->im_dprambase[up->scc_genscc.scc_rbase]); + im = (immap_t *)CFG_IMMR; + up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]); + rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]); return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0); } diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 8e321eb07..af99282dd 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -27,7 +27,6 @@ #include #include #include -#include #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) @@ -54,8 +53,8 @@ picos_to_clk(int picos) { int clks; - clks = picos / (2000000000 / (get_ddr_freq(0) / 1000)); - if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) { + clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); + if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { clks++; } @@ -132,8 +131,8 @@ convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) 800, 900, 250, - 330, - 660, + 330, /* FIXME: Is 333 better/valid? */ + 660, /* FIXME: Is 667 better/valid? */ 750, 0, /* undefined */ 0 /* undefined */ @@ -147,48 +146,24 @@ convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) } -/* - * Determine Refresh Rate. Ignore self refresh bit on DDR I. - * Table from SPD Spec, Byte 12, converted to picoseconds and - * filled in with "default" normal values. - */ -unsigned int determine_refresh_rate(unsigned int spd_refresh) -{ - unsigned int refresh_time_ns[8] = { - 15625000, /* 0 Normal 1.00x */ - 3900000, /* 1 Reduced .25x */ - 7800000, /* 2 Extended .50x */ - 31300000, /* 3 Extended 2.00x */ - 62500000, /* 4 Extended 4.00x */ - 125000000, /* 5 Extended 8.00x */ - 15625000, /* 6 Normal 1.00x filler */ - 15625000, /* 7 Normal 1.00x filler */ - }; - - return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]); -} - - long int spd_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr = &immap->im_ddr; + volatile ccsr_gur_t *gur = &immap->im_gur; spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; - unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits; + unsigned int odt_rd_cfg, odt_wr_cfg; unsigned int odt_cfg, mode_odt_enable; - unsigned int refresh_clk; -#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL - unsigned char clk_adjust; -#endif unsigned int dqs_cfg; unsigned char twr_clk, twtr_clk, twr_auto_clk; unsigned int tCKmin_ps, tCKmax_ps; unsigned int max_data_rate, effective_data_rate; unsigned int busfreq; unsigned sdram_cfg; - unsigned int memsize = 0; + unsigned int memsize; unsigned char caslat, caslat_ctrl; unsigned int trfc, trfc_clk, trfc_low, trfc_high; unsigned int trcd_clk; @@ -203,46 +178,6 @@ spd_sdram(void) unsigned int mode_caslat; unsigned char sdram_type; unsigned char d_init; - unsigned int bnds; - - /* - * Skip configuration if already configured. - * memsize is determined from last configured chip select. - */ - if (ddr->cs0_config & 0x80000000) { - debug(" cs0 already configured, bnds=%x\n",ddr->cs0_bnds); - bnds = 0xfff & ddr->cs0_bnds; - if (bnds < 0xff) { /* do not add if at top of 4G */ - memsize = (bnds + 1) << 4; - } - } - if (ddr->cs1_config & 0x80000000) { - debug(" cs1 already configured, bnds=%x\n",ddr->cs1_bnds); - bnds = 0xfff & ddr->cs1_bnds; - if (bnds < 0xff) { /* do not add if at top of 4G */ - memsize = (bnds + 1) << 4; /* assume ordered bnds */ - } - } - if (ddr->cs2_config & 0x80000000) { - debug(" cs2 already configured, bnds=%x\n",ddr->cs2_bnds); - bnds = 0xfff & ddr->cs2_bnds; - if (bnds < 0xff) { /* do not add if at top of 4G */ - memsize = (bnds + 1) << 4; - } - } - if (ddr->cs3_config & 0x80000000) { - debug(" cs3 already configured, bnds=%x\n",ddr->cs3_bnds); - bnds = 0xfff & ddr->cs3_bnds; - if (bnds < 0xff) { /* do not add if at top of 4G */ - memsize = (bnds + 1) << 4; - } - } - - if (memsize) { - printf(" Reusing current %dMB configuration\n",memsize); - memsize = setup_laws_and_tlbs(memsize); - return memsize << 20; - } /* * Read SPD information. @@ -301,19 +236,15 @@ spd_sdram(void) return 0; } -#ifdef CONFIG_MPC8548 /* - * Adjust DDR II IO voltage biasing. - * Only 8548 rev 1 needs the fix + * Adjust DDR II IO voltage biasing. It just makes it work. */ - if ((SVR_SOC_VER(get_svr()) == SVR_8548_E) && - (SVR_MJREV(get_svr()) == 1) && - (spd.mem_type == SPD_MEMTYPE_DDR2)) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - gur->ddrioovcr = (0x80000000 /* Enable */ - | 0x10000000);/* VSEL to 1.8V */ + if (spd.mem_type == SPD_MEMTYPE_DDR2) { + gur->ddrioovcr = (0 + | 0x80000000 /* Enable */ + | 0x10000000 /* VSEL to 1.8V */ + ); } -#endif /* * Determine the size of each Rank in bytes. @@ -341,14 +272,9 @@ spd_sdram(void) #endif } - ba_bits = 0; - if (spd.nbanks == 0x8) - ba_bits = 1; - ddr->cs0_config = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) - | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("\n"); @@ -422,7 +348,7 @@ spd_sdram(void) * Adjust the CAS Latency to allow for bus speeds that * are slower than the DDR module. */ - busfreq = get_ddr_freq(0) / 1000000; /* MHz */ + busfreq = get_bus_freq(0) / 1000000; /* MHz */ effective_data_rate = max_data_rate; if (busfreq < 90) { @@ -610,8 +536,8 @@ spd_sdram(void) /* * Sneak in some Extended Refresh Recovery. */ - ddr->timing_cfg_3 = (trfc_high << 16); - debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); + ddr->ext_refrec = (trfc_high << 16); + debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec); ddr->timing_cfg_1 = (0 @@ -692,10 +618,13 @@ spd_sdram(void) */ cpo = 0; if (spd.mem_type == SPD_MEMTYPE_DDR2) { - if (effective_data_rate <= 333) { + if (effective_data_rate == 266 || effective_data_rate == 333) { cpo = 0x7; /* READ_LAT + 5/4 */ - } else { + } else if (effective_data_rate == 400) { cpo = 0x9; /* READ_LAT + 7/4 */ + } else { + /* Pure speculation */ + cpo = 0xb; } } @@ -811,37 +740,51 @@ spd_sdram(void) ddr->sdram_mode_2 = 0; debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2); - /* - * Determine Refresh Rate. - */ - refresh_clk = determine_refresh_rate(spd.refresh & 0x7); /* - * Set BSTOPRE to 0x100 for page mode - * If auto-charge is used, set BSTOPRE = 0 + * Determine Refresh Rate. Ignore self refresh bit on DDR I. + * Table from SPD Spec, Byte 12, converted to picoseconds and + * filled in with "default" normal values. */ - ddr->sdram_interval = - (0 - | (refresh_clk & 0x3fff) << 16 - | 0x100 - ); - debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); + { + unsigned int refresh_clk; + unsigned int refresh_time_ns[8] = { + 15625000, /* 0 Normal 1.00x */ + 3900000, /* 1 Reduced .25x */ + 7800000, /* 2 Extended .50x */ + 31300000, /* 3 Extended 2.00x */ + 62500000, /* 4 Extended 4.00x */ + 125000000, /* 5 Extended 8.00x */ + 15625000, /* 6 Normal 1.00x filler */ + 15625000, /* 7 Normal 1.00x filler */ + }; + + refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]); + + /* + * Set BSTOPRE to 0x100 for page mode + * If auto-charge is used, set BSTOPRE = 0 + */ + ddr->sdram_interval = + (0 + | (refresh_clk & 0x3fff) << 16 + | 0x100 + ); + debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval); + } /* * Is this an ECC DDR chip? * But don't mess with it if the DDR controller will init mem. */ -#ifdef CONFIG_DDR_ECC +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) if (spd.config == 0x02) { -#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER ddr->err_disable = 0x0000000d; -#endif ddr->err_sbe = 0x00ff0000; } - debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); -#endif /* CONFIG_DDR_ECC */ +#endif asm("sync;isync;msync"); udelay(500); @@ -892,28 +835,28 @@ spd_sdram(void) #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL - /* - * Setup the clock control. - * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 - * SDRAM_CLK_CNTL[5-7] = Clock Adjust - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - if (spd.mem_type == SPD_MEMTYPE_DDR) - clk_adjust = 0x6; - else -#ifdef CONFIG_MPC8568 - /* Empirally setting clk_adjust */ - clk_adjust = 0x6; -#else - clk_adjust = 0x7; -#endif + { + unsigned char clk_adjust; - ddr->sdram_clk_cntl = (0 + /* + * Setup the clock control. + * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1 + * SDRAM_CLK_CNTL[5-7] = Clock Adjust + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + if (spd.mem_type == SPD_MEMTYPE_DDR) { + clk_adjust = 0x6; + } else { + clk_adjust = 0x7; + } + + ddr->sdram_clk_cntl = (0 | 0x80000000 | (clk_adjust << 23) ); - debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); + debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl); + } #endif /* @@ -1023,6 +966,8 @@ spd_sdram(void) static unsigned int setup_laws_and_tlbs(unsigned int memsize) { + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm; unsigned int tlb_size; unsigned int law_size; unsigned int ram_tlb_index; @@ -1042,24 +987,17 @@ setup_laws_and_tlbs(unsigned int memsize) break; case 256: case 512: - tlb_size = BOOKE_PAGESZ_256M; - break; case 1024: case 2048: - if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) - tlb_size = BOOKE_PAGESZ_1G; - else - tlb_size = BOOKE_PAGESZ_256M; + tlb_size = BOOKE_PAGESZ_256M; break; default: puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n"); /* * The memory was not able to be mapped. - * Default to a small size. */ - tlb_size = BOOKE_PAGESZ_64M; - memsize=64; + return 0; break; } @@ -1071,9 +1009,22 @@ setup_laws_and_tlbs(unsigned int memsize) ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE; while (ram_tlb_address < (memsize * 1024 * 1024) && ram_tlb_index < 16) { - set_tlb(1, ram_tlb_address, ram_tlb_address, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, ram_tlb_index, tlb_size, 1); + mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0)); + mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size)); + mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), + 0, 0, 0, 0, 0, 0, 0, 0)); + mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), + 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); + asm volatile("isync;msync;tlbwe;isync"); + + debug("DDR: MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0)); + debug("DDR: MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size)); + debug("DDR: MAS2=0x%08x\n", + TLB1_MAS2(E500_TLB_EPN(ram_tlb_address), + 0, 0, 0, 0, 0, 0, 0, 0)); + debug("DDR: MAS3=0x%08x\n", + TLB1_MAS3(E500_TLB_RPN(ram_tlb_address), + 0, 0, 0, 0, 0, 1, 0, 1, 0, 1)); ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); ram_tlb_index++; @@ -1088,10 +1039,12 @@ setup_laws_and_tlbs(unsigned int memsize) /* * Set up LAWBAR for all of DDR. */ - -#ifdef CONFIG_FSL_LAW - set_next_law(CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR); -#endif + ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff); + ecm->lawar1 = (LAWAR_EN + | LAWAR_TRGT_IF_DDR + | (LAWAR_SIZE & law_size)); + debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1); + debug("DDR: LARAR1=0x%08x\n", ecm->lawar1); /* * Confirm that the requested amount of memory was mapped. @@ -1113,7 +1066,8 @@ ddr_enable_ecc(unsigned int dram_size) { uint *p = 0; uint i = 0; - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; dma_init(); @@ -1127,16 +1081,26 @@ ddr_enable_ecc(unsigned int dram_size) } } - dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */ - dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */ - dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */ - dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */ - dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */ - dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */ - dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */ - dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */ - dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */ - dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */ + /* 8K */ + dma_xfer((uint *)0x2000, 0x2000, (uint *)0); + /* 16K */ + dma_xfer((uint *)0x4000, 0x4000, (uint *)0); + /* 32K */ + dma_xfer((uint *)0x8000, 0x8000, (uint *)0); + /* 64K */ + dma_xfer((uint *)0x10000, 0x10000, (uint *)0); + /* 128k */ + dma_xfer((uint *)0x20000, 0x20000, (uint *)0); + /* 256k */ + dma_xfer((uint *)0x40000, 0x40000, (uint *)0); + /* 512k */ + dma_xfer((uint *)0x80000, 0x80000, (uint *)0); + /* 1M */ + dma_xfer((uint *)0x100000, 0x100000, (uint *)0); + /* 2M */ + dma_xfer((uint *)0x200000, 0x200000, (uint *)0); + /* 4M */ + dma_xfer((uint *)0x400000, 0x400000, (uint *)0); for (i = 1; i < dram_size / 0x800000; i++) { dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 699441b46..ca81ee735 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -35,81 +35,66 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - uint plat_ratio,e500_ratio,half_freqSystemBus; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint plat_ratio,e500_ratio; plat_ratio = (gur->porpllsr) & 0x0000003e; plat_ratio >>= 1; - sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; + switch(plat_ratio) { + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x08: + case 0x09: + case 0x0a: + case 0x0c: + case 0x10: + sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ; + break; + default: + sysInfo->freqSystemBus = 0; + break; + } + e500_ratio = (gur->porpllsr) & 0x003f0000; e500_ratio >>= 16; - - /* Divide before multiply to avoid integer - * overflow for processor speeds above 2GHz */ - half_freqSystemBus = sysInfo->freqSystemBus/2; - sysInfo->freqProcessor = e500_ratio*half_freqSystemBus; - - /* Note: freqDDRBus is the MCLK frequency, not the data rate. */ - sysInfo->freqDDRBus = sysInfo->freqSystemBus; - -#ifdef CONFIG_DDR_CLK_FREQ - { - u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; - if (ddr_ratio != 0x7) - sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; + switch(e500_ratio) { + case 0x04: + sysInfo->freqProcessor = 2*sysInfo->freqSystemBus; + break; + case 0x05: + sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2; + break; + case 0x06: + sysInfo->freqProcessor = 3*sysInfo->freqSystemBus; + break; + case 0x07: + sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2; + break; + default: + sysInfo->freqProcessor = 0; + break; } -#endif } - int get_clocks (void) { sys_info_t sys_info; -#ifdef CONFIG_MPC8544 - volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR; -#endif #if defined(CONFIG_CPM2) - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; uint sccr, dfbrg; /* set VCO = 4 * BRG */ - cpm->im_cpm_intctl.sccr &= 0xfffffffc; - sccr = cpm->im_cpm_intctl.sccr; + immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc; + sccr = immap->im_cpm.im_cpm_intctl.sccr; dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; #endif get_sys_info (&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; - gd->mem_clk = sys_info.freqDDRBus; - - /* - * The base clock for I2C depends on the actual SOC. Unfortunately, - * there is no pattern that can be used to determine the frequency, so - * the only choice is to look up the actual SOC number and use the value - * for that SOC. This information is taken from application note - * AN2919. - */ -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) - gd->i2c1_clk = sys_info.freqSystemBus; -#elif defined(CONFIG_MPC8544) - /* - * On the 8544, the I2C clock is the same as the SEC clock. This can be - * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See - * 4.4.3.3 of the 8544 RM. Note that this might actually work for all - * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the - * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. - */ - if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->i2c1_clk = sys_info.freqSystemBus / 3; - else - gd->i2c1_clk = sys_info.freqSystemBus / 2; -#else - /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ - gd->i2c1_clk = sys_info.freqSystemBus / 2; -#endif - gd->i2c2_clk = gd->i2c1_clk; - #if defined(CONFIG_CPM2) gd->vco_out = 2*sys_info.freqSystemBus; gd->cpm_clk = gd->vco_out / 2; @@ -128,14 +113,12 @@ int get_clocks (void) *********************************************/ ulong get_bus_freq (ulong dummy) { - return gd->bus_clk; -} + ulong val; -/******************************************** - * get_ddr_freq - * return ddr bus freq in Hz - *********************************************/ -ulong get_ddr_freq (ulong dummy) -{ - return gd->mem_clk; + sys_info_t sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqSystemBus; + + return val; } diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 10fe93629..f96a4c3f8 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,6 +1,7 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004 Freescale Semiconductor. * Copyright (C) 2003 Motorola,Inc. + * Xianghua Xiao * * See file CREDITS for list of people who contributed to this * project. @@ -45,7 +46,7 @@ #endif #undef MSR_KERNEL -#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ +#define MSR_KERNEL ( MSR_ME ) /* Machine Check */ /* * Set up GOT: Global Offset Table @@ -79,37 +80,110 @@ * */ - .section .bootpg,"ax" - .globl _start_e500 + .section .bootpg,"ax" + .globl _start_e500 _start_e500: + mfspr r0, PVR + lis r1, PVR_85xx_REV1@h + ori r1, r1, PVR_85xx_REV1@l + cmpw r0, r1 + bne 1f -/* clear registers/arrays not reset by hardware */ + /* Semi-bogus errata fixup for Rev 1 */ + li r0,0x2000 + mtspr 977,r0 - /* L1 */ - li r0,2 - mtspr L1CSR0,r0 /* invalidate d-cache */ - mtspr L1CSR1,r0 /* invalidate i-cache */ + /* + * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then + * write it back immediately to fixup a Rev 1 bug (Errata CPU4) + * for this initial TLB1 entry 0, otherwise the TLB1 entry 0 + * will be invalidated (incorrectly). + */ + lis r2,0x1000 + mtspr MAS0,r2 + tlbre + tlbwe + isync + +1: + /* + * Clear and set up some registers. + * Note: Some registers need strict synchronization by + * sync/mbar/msync/isync when being "mtspr". + * BookE: isync before PID,tlbivax,tlbwe + * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe + * E500: msync,isync before L1CSR0 + * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1, + * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2], + * SPEFCSR + */ + + /* invalidate d-cache */ + mfspr r0,L1CSR0 + ori r0,r0,0x0002 + msync + isync + mtspr L1CSR0,r0 + isync + + /* disable d-cache */ + li r0,0x0 + mtspr L1CSR0,r0 + + /* invalidate i-cache */ + mfspr r0,L1CSR1 + ori r0,r0,0x0002 + mtspr L1CSR1,r0 + isync + + /* disable i-cache */ + li r0,0x0 + mtspr L1CSR1,r0 + isync + + /* clear registers */ + li r0,0 + mtspr SRR0,r0 + mtspr SRR1,r0 + mtspr CSRR0,r0 + mtspr CSRR1,r0 + mtspr MCSRR0,r0 + mtspr MCSRR1,r0 + + mtspr ESR,r0 + mtspr MCSR,r0 + mtspr DEAR,r0 + + /* not needed and conflicts with some debuggers */ + /* mtspr DBCR0,r0 */ + mtspr DBCR1,r0 + mtspr DBCR2,r0 + /* not needed and conflicts with some debuggers */ + /* mtspr IAC1,r0 */ + /* mtspr IAC2,r0 */ + mtspr DAC1,r0 + mtspr DAC2,r0 mfspr r1,DBSR mtspr DBSR,r1 /* Clear all valid bits */ - /* - * Enable L1 Caches early - * - */ + mtspr PID0,r0 + mtspr PID1,r0 + mtspr PID2,r0 + mtspr TCR,r0 - lis r2,L1CSR0_CPE@H /* enable parity */ - ori r2,r2,L1CSR0_DCE - mtspr L1CSR0,r2 /* enable L1 Dcache */ + mtspr BUCSR,r0 /* disable branch prediction */ + mtspr MAS4,r0 + mtspr MAS6,r0 +#if defined(CONFIG_ENABLE_36BIT_PHYS) + mtspr MAS7,r0 +#endif isync - mtspr L1CSR1,r2 /* enable L1 Icache */ - isync - msync /* Setup interrupt vectors */ lis r1,TEXT_BASE@h - mtspr IVPR,r1 + mtspr IVPR, r1 li r1,0x0100 mtspr IVOR0,r1 /* 0: Critical input */ @@ -143,8 +217,135 @@ _start_e500: li r1,0x0f00 mtspr IVOR15,r1 /* 15: Debug */ + /* + * Invalidate MMU L1/L2 + * + * Note: There is a fixup earlier for Errata CPU4 on + * Rev 1 parts that must precede this MMU invalidation. + */ + li r2, 0x001e + mtspr MMUCSR0, r2 + isync + + /* + * Invalidate all TLB0 entries. + */ + li r3,4 + li r4,0 + tlbivax r4,r3 + /* + * To avoid REV1 Errata CPU6 issues, make sure + * the instruction following tlbivax is not a store. + */ + + /* + * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. + * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB + * region before we can access any CCSR registers such as L2 + * registers, Local Access Registers,etc. We will also re-allocate + * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup. + * + * Please refer to board-specif directory for TLB1 entry configuration. + * (e.g. board//init.S) + * + */ + bl tlb1_entry + mr r5,r0 + li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */ + mtctr r1 + lwzu r4,0(r5) /* how many TLB1 entries we actually use */ + +0: cmpwi r4,0 + beq 1f + lwzu r0,4(r5) + lwzu r1,4(r5) + lwzu r2,4(r5) + lwzu r3,4(r5) + mtspr MAS0,r0 + mtspr MAS1,r1 + mtspr MAS2,r2 + mtspr MAS3,r3 + isync + msync + tlbwe + isync + addi r4,r4,-1 + bdnz 0b + +1: +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* Special sequence needed to update CCSRBAR itself */ + lis r4, CFG_CCSRBAR_DEFAULT@h + ori r4, r4, CFG_CCSRBAR_DEFAULT@l + + lis r5, CFG_CCSRBAR@h + ori r5, r5, CFG_CCSRBAR@l + srwi r6,r5,12 + stw r6, 0(r4) + isync + + lis r5, 0xffff + ori r5,r5,0xf000 + lwz r5, 0(r5) + isync + + lis r3, CFG_CCSRBAR@h + lwz r5, CFG_CCSRBAR@l(r3) + isync +#endif + + + /* set up local access windows, defined at board//init.S */ + lis r7,CFG_CCSRBAR@h + ori r7,r7,CFG_CCSRBAR@l + + bl law_entry + mr r6,r0 + li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */ + mtctr r1 + lwzu r5,0(r6) /* how many windows we actually use */ + + li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */ + li r1,0x0c30 + +0: cmpwi r5,0 + beq 1f + lwzu r4,4(r6) + lwzu r3,4(r6) + stwx r4,r7,r2 + stwx r3,r7,r1 + addi r5,r5,-1 + addi r2,r2,0x0020 + addi r1,r1,0x0020 + bdnz 0b + + /* Jump out the last 4K page and continue to 'normal' start */ +1: bl 3f + b _start + +3: li r0,0 + mtspr SRR1,r0 /* Keep things disabled for now */ + mflr r1 + mtspr SRR0,r1 + rfi + +/* + * r3 - 1st arg to board_init(): IMMP pointer + * r4 - 2nd arg to board_init(): boot flag + */ + .text + .long 0x27051956 /* U-BOOT Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" + + . = EXC_OFF_SYS_RESET + .globl _start +_start: /* Clear and set up some registers. */ - li r0,0x0000 + li r0,0x0000 lis r1,0xffff mtspr DEC,r0 /* prevent dec exceptions */ mttbl r0 /* prevent fit & wdt exceptions */ @@ -154,16 +355,24 @@ _start_e500: mtspr ESR,r0 /* clear exception syndrome register */ mtspr MCSR,r0 /* machine check syndrome register */ mtxer r0 /* clear integer exception register */ + lis r1,0x0002 /* set CE bit (Critical Exceptions) */ + ori r1,r1,0x1200 /* set ME/DE bit */ + mtmsr r1 /* change MSR */ + isync /* Enable Time Base and Select Time Base Clock */ lis r0,HID0_EMCP@h /* Enable machine check */ + ori r0,r0,0x4000 /* time base is processor clock */ #if defined(CONFIG_ENABLE_36BIT_PHYS) - ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */ + ori r0,r0,0x0080 /* enable MAS7 updates */ #endif - ori r0,r0,HID0_TBEN@l /* Enable Timebase */ mtspr HID0,r0 - li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ +#if defined(CONFIG_ADDR_STREAMING) + li r0,0x3000 +#else + li r0,0x1000 +#endif mtspr HID1,r0 /* Enable Branch Prediction */ @@ -181,103 +390,38 @@ _start_e500: mtspr DBCR0,r0 #endif - /* create a temp mapping in AS=1 to the boot window */ - lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h - ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l - - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l - - /* Align the mapping to 16MB */ - lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h - ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l - - lis r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l - - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - isync - msync - tlbwe - - /* create a temp mapping in AS=1 to the stack */ - lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h - ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l - - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l - - lis r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@h - ori r8,r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@l - - lis r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h - ori r9,r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l - - mtspr MAS0,r6 - mtspr MAS1,r7 - mtspr MAS2,r8 - mtspr MAS3,r9 - isync - msync - tlbwe - - lis r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@h - ori r6,r6,MSR_CE|MSR_ME|MSR_DE|MSR_IS|MSR_DS@l - lis r7,switch_as@h - ori r7,r7,switch_as@l - - mtspr SPRN_SRR0,r7 - mtspr SPRN_SRR1,r6 - rfi - -switch_as: /* L1 DCache is used for initial RAM */ + mfspr r2, L1CSR0 + ori r2, r2, 0x0003 + oris r2, r2, 0x0001 + mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */ + isync /* Allocate Initial RAM in data cache. */ - lis r3,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l - mfspr r2, L1CFG0 - andi. r2, r2, 0x1ff - /* cache size * 1024 / (2 * L1 line size) */ - slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT) + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + li r2, 512 /* 512*32=16K */ mtctr r2 - li r0,0 + li r0, 0 1: - dcbz r0,r3 - dcbtls 0,r0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + dcbz r0, r3 + dcbtls 0,r0, r3 + addi r3, r3, 32 bdnz 1b - /* Jump out the last 4K page and continue to 'normal' start */ -#ifdef CFG_RAMBOOT - b _start_cont -#else +#ifndef CFG_RAMBOOT /* Calculate absolute address in FLASH and jump there */ /*--------------------------------------------------------------*/ - lis r3,CFG_MONITOR_BASE@h - ori r3,r3,CFG_MONITOR_BASE@l - addi r3,r3,_start_cont - _start + _START_OFFSET + lis r3, CFG_MONITOR_BASE@h + ori r3, r3, CFG_MONITOR_BASE@l + addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET mtlr r3 blr -#endif - .text - .globl _start -_start: - .long 0x27051956 /* U-BOOT Magic Number */ - .globl version_string -version_string: - .ascii U_BOOT_VERSION - .ascii " (", __DATE__, " - ", __TIME__, ")" - .ascii CONFIG_IDENT_STRING, "\0" +in_flash: +#endif /* CFG_RAMBOOT */ - .align 4 - .globl _start_cont -_start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ lis r1,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET@l @@ -288,32 +432,26 @@ _start_cont: stwu r1,-8(r1) /* Save back chain and move SP */ lis r0,RESET_VECTOR@h /* Address of reset vector */ - ori r0,r0,RESET_VECTOR@l + ori r0,r0, RESET_VECTOR@l stwu r1,-8(r1) /* Save back chain and move SP */ stw r0,+12(r1) /* Save return addr (underflow vect) */ GET_GOT - bl cpu_init_early_f - - /* switch back to AS = 0 */ - lis r3,(MSR_CE|MSR_ME|MSR_DE)@h - ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l - mtmsr r3 - isync - bl cpu_init_f + bl icache_enable bl board_init_f isync - . = EXC_OFF_SYS_RESET +/* --FIXME-- machine check with MCSRRn and rfmci */ + .globl _start_of_vectors _start_of_vectors: - +#if 0 /* Critical input. */ - CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException) - -/* Machine check */ - MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) + CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException) +#endif +/* Machine check --FIXME-- Should be MACH_EXCEPTION */ + CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException) /* Data Storage exception. */ STD_EXCEPTION(0x0300, DataStorage, UnknownException) @@ -322,12 +460,12 @@ _start_of_vectors: STD_EXCEPTION(0x0400, InstStorage, UnknownException) /* External Interrupt exception. */ - STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException) + STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException) /* Alignment exception. */ . = 0x0600 Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -339,13 +477,13 @@ Alignment: mtlr r6 blrl .L_Alignment: - .long AlignmentException - _start + _START_OFFSET - .long int_return - _start + _START_OFFSET + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET /* Program check exception */ . = 0x0700 ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ @@ -353,8 +491,8 @@ ProgramCheck: mtlr r6 blrl .L_ProgramCheck: - .long ProgramCheckException - _start + _START_OFFSET - .long int_return - _start + _START_OFFSET + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET /* No FPU on MPC85xx. This exception is not supposed to happen. */ @@ -366,23 +504,23 @@ ProgramCheck: * r3-... arguments */ SystemCall: - addis r11,r0,0 /* get functions table addr */ - ori r11,r11,0 /* Note: this code is patched in trap_init */ - addis r12,r0,0 /* get number of functions */ + addis r11,r0,0 /* get functions table addr */ + ori r11,r11,0 /* Note: this code is patched in trap_init */ + addis r12,r0,0 /* get number of functions */ ori r12,r12,0 - cmplw 0,r0,r12 + cmplw 0, r0, r12 bge 1f - rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ + rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */ add r11,r11,r0 lwz r11,0(r11) - li r20,0xd00-4 /* Get stack pointer */ + li r20,0xd00-4 /* Get stack pointer */ lwz r12,0(r20) - subi r12,r12,12 /* Adjust stack pointer */ + subi r12,r12,12 /* Adjust stack pointer */ li r0,0xc00+_end_back-SystemCall - cmplw 0,r0,r12 /* Check stack overflow */ + cmplw 0, r0, r12 /* Check stack overflow */ bgt 1f stw r12,0(r20) @@ -440,7 +578,7 @@ _end_back: _end_of_vectors: - . = . + (0x100 - ( . & 0xff )) /* align for debug */ + . = 0x2100 /* * This code finishes saving the registers to the exception frame @@ -525,58 +663,26 @@ crit_return: REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) - mtspr SPRN_CSRR0,r2 - mtspr SPRN_CSRR1,r0 + mtspr 990,r2 /* SRR2 */ + mtspr 991,r0 /* SRR3 */ lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) SYNC rfci -mck_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr SPRN_MCSRR0,r2 - mtspr SPRN_MCSRR1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfmci - /* Cache functions. */ invalidate_icache: mfspr r0,L1CSR1 - ori r0,r0,L1CSR1_ICFI - msync - isync + ori r0,r0,0x0002 mtspr L1CSR1,r0 isync - blr /* entire I cache */ + blr /* entire I cache */ invalidate_dcache: mfspr r0,L1CSR0 - ori r0,r0,L1CSR0_DCFI + ori r0,r0,0x0002 msync isync mtspr L1CSR0,r0 @@ -599,9 +705,9 @@ icache_enable: .globl icache_disable icache_disable: mfspr r0,L1CSR1 - lis r3,0 - ori r3,r3,L1CSR1_ICE - andc r0,r0,r3 + lis r1,0xfffffffe@h + ori r1,r1,0xfffffffe@l + and r0,r0,r1 mtspr L1CSR1,r0 isync blr @@ -609,7 +715,7 @@ icache_disable: .globl icache_status icache_status: mfspr r3,L1CSR1 - andi. r3,r3,L1CSR1_ICE + andi. r3,r3,1 blr .globl dcache_enable @@ -629,10 +735,12 @@ dcache_enable: .globl dcache_disable dcache_disable: - mfspr r3,L1CSR0 - lis r4,0 - ori r4,r4,L1CSR0_DCE - andc r3,r3,r4 + mfspr r0,L1CSR0 + lis r1,0xfffffffe@h + ori r1,r1,0xfffffffe@l + and r0,r0,r1 + msync + isync mtspr L1CSR0,r0 isync blr @@ -640,27 +748,27 @@ dcache_disable: .globl dcache_status dcache_status: mfspr r3,L1CSR0 - andi. r3,r3,L1CSR0_DCE + andi. r3,r3,1 blr .globl get_pir get_pir: - mfspr r3,PIR + mfspr r3, PIR blr .globl get_pvr get_pvr: - mfspr r3,PVR + mfspr r3, PVR blr .globl get_svr get_svr: - mfspr r3,SVR + mfspr r3, SVR blr .globl wr_tcr wr_tcr: - mtspr TCR,r3 + mtspr TCR, r3 blr /*------------------------------------------------------------------------------- */ @@ -679,7 +787,6 @@ in8: .globl out8 out8: stb r4,0x0000(r3) - sync blr /*------------------------------------------------------------------------------- */ @@ -689,7 +796,6 @@ out8: .globl out16 out16: sth r4,0x0000(r3) - sync blr /*------------------------------------------------------------------------------- */ @@ -699,7 +805,6 @@ out16: .globl out16r out16r: sthbrx r4,r0,r3 - sync blr /*------------------------------------------------------------------------------- */ @@ -709,7 +814,6 @@ out16r: .globl out32 out32: stw r4,0x0000(r3) - sync blr /*------------------------------------------------------------------------------- */ @@ -719,7 +823,6 @@ out32: .globl out32r out32r: stwbrx r4,r0,r3 - sync blr /*------------------------------------------------------------------------------- */ @@ -758,6 +861,51 @@ in32r: lwbrx r3,r0,r3 blr +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcSync */ +/* Description: Processor Synchronize */ +/* Input: none. */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcSync +ppcSync: + sync + blr + /*------------------------------------------------------------------------------*/ /* @@ -773,16 +921,16 @@ in32r: */ .globl relocate_code relocate_code: - mr r1,r3 /* Set new stack pointer */ - mr r9,r4 /* Save copy of Init Data pointer */ - mr r10,r5 /* Save copy of Destination Address */ + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Init Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ - mr r3,r5 /* Destination Address */ - lis r4,CFG_MONITOR_BASE@h /* Source Address */ - ori r4,r4,CFG_MONITOR_BASE@l + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l lwz r5,GOT(__init_end) sub r5,r5,r4 - li r6,CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: @@ -791,12 +939,12 @@ relocate_code: * * Offset: */ - sub r15,r10,r4 + sub r15, r10, r4 /* First our own GOT */ - add r14,r14,r15 + add r14, r14, r15 /* the the one used by the C code */ - add r30,r30,r15 + add r30, r30, r15 /* * Now relocate code @@ -857,10 +1005,10 @@ relocate_code: * initialization, now running from RAM. */ - addi r0,r10,in_ram - _start + _START_OFFSET + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET mtlr r0 blr /* NEVER RETURNS! */ - .globl in_ram + in_ram: /* @@ -904,19 +1052,19 @@ clear_bss: lwz r3,GOT(__bss_start) lwz r4,GOT(_end) - cmplw 0,r3,r4 + cmplw 0, r3, r4 beq 6f - li r0,0 + li r0, 0 5: - stw r0,0(r3) - addi r3,r3,4 - cmplw 0,r3,r4 + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 bne 5b 6: - mr r3,r9 /* Init Data pointer */ - mr r4,r10 /* Destination Address */ + mr r3, r9 /* Init Data pointer */ + mr r4, r10 /* Destination Address */ bl board_init_r /* @@ -927,54 +1075,52 @@ clear_bss: */ .globl trap_init trap_init: - lwz r7,GOT(_start_of_vectors) - lwz r8,GOT(_end_of_vectors) + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) - li r9,0x100 /* reset vector always at 0x100 */ + li r9, 0x100 /* reset vector always at 0x100 */ - cmplw 0,r7,r8 + cmplw 0, r7, r8 bgelr /* return if r7>=r8 - just in case */ mflr r4 /* save link register */ 1: - lwz r0,0(r7) - stw r0,0(r9) - addi r7,r7,4 - addi r9,r9,4 - cmplw 0,r7,r8 + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 bne 1b /* * relocate `hdlr' and `int_return' entries */ - li r7,.L_CriticalInput - _start + _START_OFFSET + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET bl trap_reloc - li r7,.L_MachineCheck - _start + _START_OFFSET + li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET bl trap_reloc - li r7,.L_DataStorage - _start + _START_OFFSET + li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET bl trap_reloc - li r7,.L_InstStorage - _start + _START_OFFSET + li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET bl trap_reloc - li r7,.L_ExtInterrupt - _start + _START_OFFSET + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET bl trap_reloc - li r7,.L_Alignment - _start + _START_OFFSET + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET bl trap_reloc - li r7,.L_ProgramCheck - _start + _START_OFFSET + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET bl trap_reloc - li r7,.L_FPUnavailable - _start + _START_OFFSET + li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET bl trap_reloc - li r7,.L_Decrementer - _start + _START_OFFSET - bl trap_reloc - li r7,.L_IntervalTimer - _start + _START_OFFSET - li r8,_end_of_vectors - _start + _START_OFFSET + li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 2: bl trap_reloc - addi r7,r7,0x100 /* next exception vector */ - cmplw 0,r7,r8 + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 blt 2b lis r7,0x0 - mtspr IVPR,r7 + mtspr IVPR, r7 mtlr r4 /* restore link register */ blr @@ -983,39 +1129,29 @@ trap_init: * Function: relocate entries for one exception vector */ trap_reloc: - lwz r0,0(r7) /* hdlr ... */ - add r0,r0,r3 /* ... += dest_addr */ - stw r0,0(r7) + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) - lwz r0,4(r7) /* int_return ... */ - add r0,r0,r3 /* ... += dest_addr */ - stw r0,4(r7) + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) blr +#ifdef CFG_INIT_RAM_LOCK .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3,(CFG_INIT_RAM_ADDR & ~31)@h - ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l - mfspr r4,L1CFG0 - andi. r4,r4,0x1ff - slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) - mtctr r4 -1: dcbi r0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + lis r3, (CFG_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l + li r2,512 + mtctr r2 +1: icbi r0, r3 + dcbi r0, r3 + addi r3, r3, 32 bdnz 1b - sync - - /* Invalidate the TLB entries for the cache */ - lis r3,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l - tlbivax 0,r3 - addi r3,r3,0x1000 - tlbivax 0,r3 - addi r3,r3,0x1000 - tlbivax 0,r3 - addi r3,r3,0x1000 - tlbivax 0,r3 + sync /* Wait for all icbi to complete on bus */ isync blr +#endif diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c index 0eab69448..904f05233 100644 --- a/cpu/mpc85xx/traps.c +++ b/cpu/mpc85xx/traps.c @@ -1,7 +1,6 @@ /* * linux/arch/ppc/kernel/traps.c * - * Copyright 2007 Freescale Semiconductor. * Copyright (C) 2003 Motorola * Modified by Xianghua Xiao(x.xiao@motorola.com) * @@ -42,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -50,12 +49,10 @@ int (*debugger_exception_handler)(struct pt_regs *) = 0; extern unsigned long search_exception_table(unsigned long); /* - * End of addressable memory. This may be less than the actual - * amount of memory on the system if we're unable to keep all - * the memory mapped in. + * End of memory as shown by board info and determined by DDR setup. */ -extern ulong get_effective_memsize(void); -#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) + static __inline__ void set_tsr(unsigned long val) { @@ -77,7 +74,7 @@ static __inline__ unsigned long get_esr(void) #define ESR_DIZ 0x00400000 #define ESR_U0F 0x00008000 -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -148,13 +145,10 @@ CritcalInputException(struct pt_regs *regs) panic("Critical Input Exception"); } -int machinecheck_count = 0; -int machinecheck_error = 0; void MachineCheckException(struct pt_regs *regs) { unsigned long fixup; - unsigned int mcsr, mcsrr0, mcsrr1, mcar; /* Probing PCI using config cycles cause this exception * when a device is not present. Catch it and return to @@ -165,68 +159,40 @@ MachineCheckException(struct pt_regs *regs) return; } - mcsrr0 = mfspr(SPRN_MCSRR0); - mcsrr1 = mfspr(SPRN_MCSRR1); - mcsr = mfspr(SPRN_MCSR); - mcar = mfspr(SPRN_MCAR); - - machinecheck_count++; - machinecheck_error=1; - -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif printf("Machine check in kernel mode.\n"); - printf("Caused by (from mcsr): "); - printf("mcsr = 0x%08x\n", mcsr); - if (mcsr & 0x80000000) - printf("Machine check input pin\n"); - if (mcsr & 0x40000000) - printf("Instruction cache parity error\n"); - if (mcsr & 0x20000000) - printf("Data cache push parity error\n"); - if (mcsr & 0x10000000) - printf("Data cache parity error\n"); - if (mcsr & 0x00000080) - printf("Bus instruction address error\n"); - if (mcsr & 0x00000040) - printf("Bus Read address error\n"); - if (mcsr & 0x00000020) - printf("Bus Write address error\n"); - if (mcsr & 0x00000010) - printf("Bus Instruction data bus error\n"); - if (mcsr & 0x00000008) - printf("Bus Read data bus error\n"); - if (mcsr & 0x00000004) - printf("Bus Write bus error\n"); - if (mcsr & 0x00000002) - printf("Bus Instruction parity error\n"); - if (mcsr & 0x00000001) - printf("Bus Read parity error\n"); - + printf("Caused by (from msr): "); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); + break; + case (0x80000000>>13): + printf("Transfer error ack signal\n"); + break; + case (0x80000000>>14): + printf("Data parity signal\n"); + break; + case (0x80000000>>15): + printf("Address parity signal\n"); + break; + default: + printf("Unknown values in msr\n"); + } show_regs(regs); - printf("MCSR=0x%08x \tMCSRR0=0x%08x \nMCSRR1=0x%08x \tMCAR=0x%08x\n", - mcsr, mcsrr0, mcsrr1, mcar); print_backtrace((unsigned long *)regs->gpr[1]); - if (machinecheck_count > 10) { - panic("machine check count too high\n"); - } - - if (machinecheck_count > 1) { - regs->nip += 4; /* skip offending instruction */ - printf("Skipping current instr, Returning to 0x%08lx\n", - regs->nip); - } else { - printf("Returning back to 0x%08lx\n",regs->nip); - } + panic("machine check"); } void AlignmentException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -241,7 +207,7 @@ ProgramCheckException(struct pt_regs *regs) { long esr_val; -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -278,7 +244,7 @@ PITException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -287,40 +253,13 @@ UnknownException(struct pt_regs *regs) regs->nip, regs->msr, regs->trap); _exception(0, regs); } -void -ExtIntException(struct pt_regs *regs) -{ - volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); - - uint vect; - -#if defined(CONFIG_CMD_KGDB) - if (debugger_exception_handler && (*debugger_exception_handler)(regs)) - return; -#endif - - printf("External Interrupt Exception at PC: %lx, SR: %lx, vector=%lx", - regs->nip, regs->msr, regs->trap); - vect = pic->iack0; - printf(" irq IACK0@%05x=%d\n",(int)&pic->iack0,vect); - show_regs(regs); - print_backtrace((unsigned long *)regs->gpr[1]); - machinecheck_count++; -#ifdef EXTINT_NOSKIP - printf("Returning back to 0x%08x\n",regs->nip); -#else - regs->nip += 4; /* skip offending instruction */ - printf("Skipping current instr, Returning to 0x%08lx\n",regs->nip); -#endif - -} void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc8xx/Makefile b/cpu/mpc8xx/Makefile index 5f7045969..de75fad3c 100644 --- a/cpu/mpc8xx/Makefile +++ b/cpu/mpc8xx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,42 +25,25 @@ include $(TOPDIR)/config.mk # CFLAGS += -DET_DEBUG -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a -START-y += start.o -START-y += kgdb.o -COBJS-y += bedbug_860.o -COBJS-y += commproc.o -COBJS-y += cpu.o -COBJS-y += cpu_init.o -COBJS-y += fec.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o -COBJS-y += i2c.o -COBJS-y += interrupts.o -COBJS-y += lcd.o -COBJS-y += scc.o -COBJS-y += serial.o -COBJS-y += speed.o -COBJS-y += spi.o -COBJS-y += traps.o -COBJS-y += upatch.o -COBJS-y += video.o -SOBJS-y += plprcr_write.o +START = start.o kgdb.o +OBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \ + fec.o i2c.o interrupts.o lcd.o scc.o \ + serial.o speed.o spi.o \ + traps.o upatch.o video.o +SOBJS = plprcr_write.o -SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) -START := $(addprefix $(obj),$(START-y)) +all: .depend $(START) $(LIB) -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(obj)kgdb.o +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) kgdb.o ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(SOBJS:.o=.S) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/mpc8xx/bedbug_860.c b/cpu/mpc8xx/bedbug_860.c index 5d5236639..e91a1006f 100644 --- a/cpu/mpc8xx/bedbug_860.c +++ b/cpu/mpc8xx/bedbug_860.c @@ -10,7 +10,7 @@ #include #include -#if defined(CONFIG_CMD_BEDBUG) && defined(CONFIG_8xx) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_8xx) #define MAX_BREAK_POINTS 2 diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk index 6031e7f76..bfa6625fa 100644 --- a/cpu/mpc8xx/config.mk +++ b/cpu/mpc8xx/config.mk @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -ffixed-r29 -mstring -mcpu=860 -msoft-float diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c index ec6a3fd5d..97112f03d 100644 --- a/cpu/mpc8xx/cpu.c +++ b/cpu/mpc8xx/cpu.c @@ -39,12 +39,6 @@ #include #include -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#include -#endif - DECLARE_GLOBAL_DATA_PTR; static char *cpu_warning = "\n " \ @@ -634,4 +628,7 @@ void reset_8xx_watchdog (volatile immap_t * immr) immr->im_siu_conf.sc_swsr = 0xaa39; /* write magic2 */ # endif /* CONFIG_LWMON */ } + #endif /* CONFIG_WATCHDOG */ + +/* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c index fb3414aae..c79e5780a 100644 --- a/cpu/mpc8xx/cpu_init.c +++ b/cpu/mpc8xx/cpu_init.c @@ -31,8 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \ - defined(CFG_SMC_UCODE_PATCH) +#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) void cpm_load_patch (volatile immap_t * immr); #endif @@ -254,8 +253,7 @@ void cpu_init_f (volatile immap_t * immr) immr->im_cpm.cp_rccr = CFG_RCCR; #endif -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \ - defined(CFG_SMC_UCODE_PATCH) +#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) cpm_load_patch (immr); /* load mpc8xx microcode patch */ #endif } diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 37eb481ff..6d2755e83 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; #undef ET_DEBUG -#if defined(CONFIG_CMD_NET) && \ +#if (CONFIG_COMMANDS & CFG_CMD_NET) && \ (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ @@ -49,7 +49,7 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(WANT_MII) #include -#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -143,9 +143,6 @@ static int fec_send(struct eth_device* dev, volatile void *packet, int length); static int fec_recv(struct eth_device* dev); static int fec_init(struct eth_device* dev, bd_t * bd); static void fec_halt(struct eth_device* dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -static void __mii_init(void); -#endif int fec_initialize(bd_t *bis) { @@ -185,7 +182,7 @@ int fec_initialize(bd_t *bis) eth_register(dev); -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register(dev->name, fec8xx_miiphy_read, fec8xx_miiphy_write); #endif @@ -271,7 +268,7 @@ static int fec_recv (struct eth_device *dev) length -= 4; -#if defined(CONFIG_CMD_CDP) +#if (CONFIG_COMMANDS & CFG_CMD_CDP) if ((rx[0] & 1) != 0 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0 && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0) @@ -542,30 +539,6 @@ static void fec_pin_init(int fecidx) } } -static int fec_reset(volatile fec_t *fecp) -{ - int i; - - /* Whack a reset. - * A delay is required between a reset of the FEC block and - * initialization of other FEC registers because the reset takes - * some time to complete. If you don't delay, subsequent writes - * to FEC registers might get killed by the reset routine which is - * still in progress. - */ - - fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; - for (i = 0; - (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); - ++i) { - udelay (1); - } - if (i == FEC_RESET_DELAY) - return -1; - - return 0; -} - static int fec_init (struct eth_device *dev, bd_t * bd) { struct ether_fcc_info_s *efis = dev->priv; @@ -600,17 +573,23 @@ static int fec_init (struct eth_device *dev, bd_t * bd) #endif /* CONFIG_FADS */ } -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - /* the MII interface is connected to FEC1 - * so for the miiphy_xxx function to work we must - * call mii_init since fec_halt messes the thing up + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. */ - if (efis->ether_index != 0) - __mii_init(); -#endif - - if (fec_reset(fecp) < 0) + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) { printf ("FEC_RESET_DELAY timeout\n"); + return 0; + } /* We use strictly polling mode only */ @@ -624,12 +603,12 @@ static int fec_init (struct eth_device *dev, bd_t * bd) /* Set station address */ -#define ea dev->enetaddr +#define ea eth_get_dev()->enetaddr fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); fecp->fec_addr_high = (ea[4] << 8) | (ea[5]); #undef ea -#if defined(CONFIG_CMD_CDP) +#if (CONFIG_COMMANDS & CFG_CMD_CDP) /* * Turn on multicast address hash table */ @@ -729,7 +708,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) if (efis->actual_phy_addr == -1) { printf ("Unable to discover phy!\n"); - return -1; + return 0; } #else efis->actual_phy_addr = -1; @@ -737,8 +716,15 @@ static int fec_init (struct eth_device *dev, bd_t * bd) } else { efis->actual_phy_addr = efis->phy_addr; } - #if defined(CONFIG_MII) && defined(CONFIG_RMII) + + /* the MII interface is connected to FEC1 + * so for the miiphy_xxx function to work we must + * call mii_init since fec_halt messes the thing up + */ + if (efis->ether_index != 0) + mii_init(); + /* * adapt the RMII speed to the speed of the phy */ @@ -765,7 +751,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) efis->initialized = 1; - return 0; + return 1; } @@ -801,7 +787,7 @@ static void fec_halt(struct eth_device* dev) efis->initialized = 0; } -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) /* Make MII read/write commands for the FEC. */ @@ -866,7 +852,7 @@ mii_send(uint mii_cmd) #endif return (mii_reply & 0xffff); /* data read from phy */ } -#endif +#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */ #if defined(CFG_DISCOVER_PHY) static int mii_discover_phy(struct eth_device *dev) @@ -888,14 +874,15 @@ static int mii_discover_phy(struct eth_device *dev) udelay(10000); /* wait 10ms */ } for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); #ifdef ET_DEBUG printf("PHY type 0x%x pass %d type ", phytype, pass); #endif if (phytype != 0xffff) { phyaddr = phyno; + phytype <<= 16; phytype |= mii_send(mk_mii_read(phyno, - PHY_PHYIDR1)) << 16; + PHY_PHYIDR2)); #ifdef ET_DEBUG printf("PHY @ 0x%x pass %d type ",phyno,pass); @@ -939,20 +926,39 @@ static int mii_discover_phy(struct eth_device *dev) } #endif /* CFG_DISCOVER_PHY */ -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII) /**************************************************************************** - * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet + * mii_init -- Initialize the MII for MII command without ethernet * This function is a subset of eth_init **************************************************************************** */ -static void __mii_init(void) +void mii_init (void) { volatile immap_t *immr = (immap_t *) CFG_IMMR; volatile fec_t *fecp = &(immr->im_cpm.cp_fec); + int i, j; - if (fec_reset(fecp) < 0) + for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) { + + /* Whack a reset. + * A delay is required between a reset of the FEC block and + * initialization of other FEC registers because the reset takes + * some time to complete. If you don't delay, subsequent writes + * to FEC registers might get killed by the reset routine which is + * still in progress. + */ + + fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET; + for (i = 0; + (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY); + ++i) { + udelay (1); + } + if (i == FEC_RESET_DELAY) { printf ("FEC_RESET_DELAY timeout\n"); + return; + } /* We use strictly polling mode only */ @@ -962,21 +968,14 @@ static void __mii_init(void) */ fecp->fec_ievent = 0xffc0; + /* Setup the pin configuration of the FEC(s) + */ + fec_pin_init(ether_fcc_info[i].ether_index); + /* Now enable the transmit and receive processing */ fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN; -} - -void mii_init (void) -{ - int i; - - __mii_init(); - - /* Setup the pin configuration of the FEC(s) - */ - for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) - fec_pin_init(ether_fcc_info[i].ether_index); + } } /***************************************************************************** @@ -1021,6 +1020,6 @@ int fec8xx_miiphy_write(char *devname, unsigned char addr, #endif return 0; } -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/ -#endif +#endif /* CFG_CMD_NET, FEC_ENET */ diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c index f05b666b8..6c59374e3 100644 --- a/cpu/mpc8xx/i2c.c +++ b/cpu/mpc8xx/i2c.c @@ -590,7 +590,7 @@ i2c_test_callback(int flags, int xnum) int i2c_probe(uchar chip) { i2c_state_t state; - int rc; + int rc; uchar buf[1]; i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); diff --git a/cpu/mpc8xx/kgdb.S b/cpu/mpc8xx/kgdb.S index 812baa3ec..11c3c6933 100644 --- a/cpu/mpc8xx/kgdb.S +++ b/cpu/mpc8xx/kgdb.S @@ -34,7 +34,7 @@ #include #include -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) /* * cache flushing routines for kgdb @@ -71,4 +71,4 @@ kgdb_flush_cache_range: SYNC blr -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index 09a3db107..6b9110f13 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -1,7 +1,7 @@ /* * File: scc.c * Description: - * Basic ET HW initialization and packet RX/TX routines + * Basic ET HW initialization and packet RX/TX routines * * NOTE <<>>: * Do not cache Rx/Tx buffers! @@ -38,7 +38,7 @@ #include #include -#if defined(CONFIG_CMD_NET) && defined(SCC_ENET) +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET) /* Ethernet Transmit and Receive Buffers */ #define DBUF_LENGTH 1520 @@ -567,4 +567,4 @@ void restart (void) (SCC_GSMRL_ENR | SCC_GSMRL_ENT); } #endif -#endif +#endif /* CFG_CMD_NET, SCC_ENET */ diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index ad0229999..8ae584f2e 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -124,12 +124,6 @@ static int smc_init (void) sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]); up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC]; -#ifdef CFG_SMC_UCODE_PATCH - up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase]; -#else - /* Disable relocation */ - up->smc_rpbase = 0; -#endif /* Disable transmitter/receiver. */ @@ -218,12 +212,6 @@ static int smc_init (void) up->smc_tbase = dpaddr+sizeof(cbd_t); up->smc_rfcr = SMC_EB; up->smc_tfcr = SMC_EB; -#if defined (CFG_SMC_UCODE_PATCH) - up->smc_rbptr = up->smc_rbase; - up->smc_tbptr = up->smc_tbase; - up->smc_rstate = 0; - up->smc_tstate = 0; -#endif #if defined(CONFIG_MBX) board_serial_init(); @@ -239,16 +227,8 @@ static int smc_init (void) sp->smc_smcm = 0; sp->smc_smce = 0xff; -#ifdef CFG_SPC1920_SMC1_CLK4 - /* clock source is PLD */ - - /* set freq to 19200 Baud */ - *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0x3; - /* configure clk4 as input */ - im->im_ioport.iop_pdpar |= 0x800; - im->im_ioport.iop_pddir &= ~0x800; - - cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000); +#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */ + *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff; #else /* Set up the baud rate generator */ smc_setbrg (); @@ -300,9 +280,6 @@ smc_putc(const char c) smc_putc ('\r'); up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CFG_SMC_UCODE_PATCH - up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; -#endif tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; @@ -341,9 +318,6 @@ smc_getc(void) unsigned char c; up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CFG_SMC_UCODE_PATCH - up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; -#endif rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; @@ -369,9 +343,6 @@ smc_tstc(void) volatile cpm8xx_t *cpmp = &(im->im_cpm); up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; -#ifdef CFG_SMC_UCODE_PATCH - up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; -#endif rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; @@ -687,7 +658,7 @@ void enable_putc(void) } #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) void kgdb_serial_init(void) @@ -744,6 +715,6 @@ kgdb_interruptible (int yes) { return; } -#endif +#endif /* CFG_CMD_KGDB */ #endif /* CONFIG_8xx_CONS_NONE */ diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 070babcc9..101d5f9cb 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -174,27 +174,6 @@ unsigned long measure_gclk(void) #endif -void get_brgclk(uint sccr) -{ - uint divider = 0; - - switch((sccr&SCCR_DFBRG11)>>11){ - case 0: - divider = 1; - break; - case 1: - divider = 4; - break; - case 2: - divider = 16; - break; - case 3: - divider = 64; - break; - } - gd->brg_clk = gd->cpu_clk/divider; -} - #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) /* @@ -244,8 +223,6 @@ int get_clocks (void) gd->bus_clk = gd->cpu_clk / 2; } - get_brgclk(sccr); - return (0); } @@ -277,15 +254,16 @@ int get_clocks_866 (void) gd->cpu_clk = measure_gclk (); #endif - get_brgclk(immr->im_clkrst.car_sccr); - /* if cpu clock <= 66 MHz then set bus division factor to 1, * otherwise set it to 2 */ sccr_reg = immr->im_clkrst.car_sccr; sccr_reg &= ~SCCR_EBDF11; - +#if defined(CONFIG_TQM885D) + if (gd->cpu_clk <= 80000000) { +#else if (gd->cpu_clk <= 66000000) { +#endif sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */ gd->bus_clk = gd->cpu_clk; } else { diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index eca4b5062..33a3f6c88 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -224,7 +224,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -242,7 +242,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) + EXCEPTION_PROLOG addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc8xx/traps.c b/cpu/mpc8xx/traps.c index e1ec88961..67b75cce2 100644 --- a/cpu/mpc8xx/traps.c +++ b/cpu/mpc8xx/traps.c @@ -36,11 +36,11 @@ #include #include -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -126,7 +126,7 @@ MachineCheckException(struct pt_regs *regs) return; } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -159,7 +159,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -171,7 +171,7 @@ AlignmentException(struct pt_regs *regs) void ProgramCheckException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -183,7 +183,7 @@ ProgramCheckException(struct pt_regs *regs) void SoftEmuException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -196,7 +196,7 @@ SoftEmuException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -210,7 +210,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } diff --git a/cpu/mpc8xx/upatch.c b/cpu/mpc8xx/upatch.c index 4d6c52246..eccff645e 100644 --- a/cpu/mpc8xx/upatch.c +++ b/cpu/mpc8xx/upatch.c @@ -1,8 +1,7 @@ #include #include -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) || \ - defined(CFG_SMC_UCODE_PATCH) +#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCH) static void UcodeCopy (volatile cpm8xx_t *cpm); @@ -33,29 +32,13 @@ void cpm_load_patch (volatile immap_t *immr) } #endif -#ifdef CFG_SMC_UCODE_PATCH - { - volatile smc_uart_t *up = (smc_uart_t *) & immr->im_cpm.cp_dparam[PROFF_SMC1]; - /* Activate the microcode per the instructions in the microcode manual */ - /* NOTE: We're only relocating the SMC parameters. */ - immr->im_cpm.cp_cpmcr1 = 0x8080; /* Write Trap register 1 value */ - immr->im_cpm.cp_cpmcr2 = 0x8088; /* Write Trap register 2 value */ - up->smc_rpbase = CFG_SMC_DPMEM_OFFSET; /* Where to relocte SMC params */ - } -#endif - /* * Enable DPRAM microcode to execute from the first 512 bytes * and a 256 byte extension of DPRAM. */ -#ifdef CFG_SMC_UCODE_PATCH - immr->im_cpm.cp_rccr |= 0x0002; -#else immr->im_cpm.cp_rccr |= 0x0001; -#endif } -#if defined(CFG_I2C_UCODE_PATCH) || defined(CFG_SPI_UCODE_PATCh) static ulong patch_2000[] = { 0x7FFFEFD9, 0x3FFD0000, 0x7FFB49F7, 0x7FF90000, 0x5FEFADF7, 0x5F88ADF7, 0x5FEFAFF7, 0x5F88AFF7, @@ -99,81 +82,6 @@ static ulong patch_2F00[] = { 0x35931497, 0x35376956, 0xBD697B9D, 0x96931313, 0x19797937, 0x69350000, }; -#else - -static ulong patch_2000[] = { - 0x3fff0000, 0x3ffd0000, 0x3ffb0000, 0x3ff90000, - 0x5fefeff8, 0x5f91eff8, 0x3ff30000, 0x3ff10000, - 0x3a11e710, 0xedf0ccb9, 0xf318ed66, 0x7f0e5fe2, - 0x7fedbb38, 0x3afe7468, 0x7fedf4d8, 0x8ffbb92d, - 0xb83b77fd, 0xb0bb5eb9, 0xdfda7fed, 0x90bde74d, - 0x6f0dcbd3, 0xe7decfed, 0xcb50cfed, 0xcfeddf6d, - 0x914d4f74, 0x5eaedfcb, 0x9ee0e7df, 0xefbb6ffb, - 0xe7ef7f0e, 0x9ee57fed, 0xebb7effa, 0xeb30affb, - 0x7fea90b3, 0x7e0cf09f, 0xbffff318, 0x5fffdfff, - 0xac35efea, 0x7fce1fc1, 0xe2ff5fbd, 0xaffbe2ff, - 0x5fbfaffb, 0xf9a87d0f, 0xaef8770f, 0x7d0fb0a2, - 0xeffbbfff, 0xcfef5fba, 0x7d0fbfff, 0x5fba4cf8, - 0x7fddd09b, 0x49f847fd, 0x7efdf097, 0x7fedfffd, - 0x7dfdf093, 0xef7e7e1e, 0x5fba7f0e, 0x3a11e710, - 0xedf0cc87, 0xfb18ad0a, 0x1f85bbb8, 0x74283b7e, - 0x7375e4bb, 0x2ab64fb8, 0x5c7de4bb, 0x32fdffbf, - 0x5f0843f8, 0x7ce3e1bb, 0xe74f7ded, 0x6f0f4fe8, - 0xc7ba32be, 0x73f2efeb, 0x600b4f78, 0xe5bb760b, - 0x5388aef8, 0x4ef80b6a, 0xcfef9ee5, 0xabf8751f, - 0xefef5b88, 0x741f4fe8, 0x751e760d, 0x7fdb70dd, - 0x741cafce, 0xefcc7fce, 0x751e7088, 0x741ce7bb, - 0x334ecfed, 0xafdbefeb, 0xe5bb760b, 0x53ceaef8, - 0xafe8e7eb, 0x4bf8771e, 0x7e007fed, 0x4fcbe2cc, - 0x7fbc3085, 0x7b0f7a0f, 0x34b177fd, 0xb0e75e93, - 0xdf313e3b, 0xaf78741f, 0x741f30cc, 0xcfef5f08, - 0x741f3e88, 0xafb8771e, 0x5f437fed, 0x0bafe2cc, - 0x741ccfec, 0xe5ca53a9, 0x6fcb4f74, 0x5e89df27, - 0x2a923d14, 0x4b8fdf0c, 0x751f741c, 0x6c1eeffa, - 0xefea7fce, 0x6ffc309a, 0xefec3fca, 0x308fdf0a, - 0xadf85e7a, 0xaf7daefd, 0x5e7adf0a, 0x5e7aafdd, - 0x761f1088, 0x1e7c7efd, 0x3089fffe, 0x4908fb18, - 0x5fffdfff, 0xafbbf0f7, 0x4ef85f43, 0xadf81489, - 0x7a0f7089, 0xcfef5089, 0x7a0fdf0c, 0x5e7cafed, - 0xbc6e780f, 0xefef780f, 0xefef790f, 0xa7f85eeb, - 0xffef790f, 0xefef790f, 0x1489df0a, 0x5e7aadfd, - 0x5f09fffb, 0xe79aded9, 0xeff96079, 0x607ae79a, - 0xded8eff9, 0x60795edb, 0x607acfef, 0xefefefdf, - 0xefbfef7f, 0xeeffedff, 0xebffe7ff, 0xafefafdf, - 0xafbfaf7f, 0xaeffadff, 0xabffa7ff, 0x6fef6fdf, - 0x6fbf6f7f, 0x6eff6dff, 0x6bff67ff, 0x2fef2fdf, - 0x2fbf2f7f, 0x2eff2dff, 0x2bff27ff, 0x4e08fd1f, - 0xe5ff6e0f, 0xaff87eef, 0x7e0ffdef, 0xf11f6079, - 0xabf8f51e, 0x7e0af11c, 0x37cfae16, 0x7fec909a, - 0xadf8efdc, 0xcfeae52f, 0x7d0fe12b, 0xf11c6079, - 0x7e0a4df8, 0xcfea5ea0, 0x7d0befec, 0xcfea5ea2, - 0xe522efdc, 0x5ea2cfda, 0x4e08fd1f, 0x6e0faff8, - 0x7c1f761f, 0xfdeff91f, 0x6079abf8, 0x761cee00, - 0xf91f2bfb, 0xefefcfec, 0xf91f6079, 0x761c27fb, - 0xefdf5e83, 0xcfdc7fdd, 0x50f84bf8, 0x47fd7c1f, - 0x761ccfcf, 0x7eef7fed, 0x7dfd70ef, 0xef7e7f1e, - 0x771efb18, 0x6079e722, 0xe6bbe5bb, 0x2e66e5bb, - 0x600b2ee1, 0xe2bbe2bb, 0xe2bbe2bb, 0x2f5ee2bb, - 0xe2bb2ff9, 0x6079e2bb, -}; - -static ulong patch_2F00[] = { - 0x30303030, 0x3e3e3030, 0xaf79b9b3, 0xbaa3b979, - 0x9693369f, 0x79f79777, 0x97333fff, 0xfb3b9e9f, - 0x79b91d11, 0x9e13f3ff, 0x3f9b6bd9, 0xe173d136, - 0x695669d1, 0x697b3daf, 0x79b93a3a, 0x3f979f91, - 0x379ff976, 0xf99777fd, 0x9779737d, 0xe9d6bbf9, - 0xbfffd9df, 0x97f7fd97, 0x6f7b9bff, 0xf9bd9683, - 0x397db973, 0xd97b3b9f, 0xd7f9f733, 0x9993bb9e, - 0xe1f9ef93, 0x73773337, 0xb936917d, 0x11f87379, - 0xb979d336, 0x8b7ded73, 0x1b7d9337, 0x31f3f22f, - 0x3f2327ee, 0xeeeeeeee, 0xeeeeeeee, 0xeeeeeeee, - 0xeeeeee4b, 0xf4fbdbd2, 0x58bb1878, 0x577fdfd2, - 0xd573b773, 0xf7374b4f, 0xbdbd25b8, 0xb177d2d1, - 0x7376856b, 0xbfdd687b, 0xdd2fff8f, 0x78ffff8f, - 0xf22f0000, -}; -#endif static void UcodeCopy (volatile cpm8xx_t *cpm) { diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c index ef9116560..918de6794 100644 --- a/cpu/mpc8xx/video.c +++ b/cpu/mpc8xx/video.c @@ -115,9 +115,9 @@ DECLARE_GLOBAL_DATA_PTR; #define VIDEO_BURST_LEN (VIDEO_COLS/8) #ifdef VIDEO_MODE_YUYV -#define VIDEO_BG_COL 0x80D880D8 /* Background color in YUYV format */ +#define VIDEO_BG_COL 0x80D880D8 /* Background color in YUYV format */ #else -#define VIDEO_BG_COL 0xF8F8F8F8 /* Background color in RGB format */ +#define VIDEO_BG_COL 0xF8F8F8F8 /* Background color in RGB format */ #endif /************************************************************************/ @@ -833,10 +833,10 @@ static void video_encoder_init (void) puts ("[VIDEO ENCODER] Configuring the encoder...\n"); - printf ("Sending %zu bytes (@ %08lX) to I2C 0x%lX:\n ", + printf ("Sending %d bytes (@ %08lX) to I2C 0x%X:\n ", sizeof(video_encoder_data), (ulong)video_encoder_data, - (ulong)VIDEO_I2C_ADDR); + VIDEO_I2C_ADDR); for (i=0; i $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/nios/asmi.c b/cpu/nios/asmi.c index c2cd8fead..ce2863e5c 100644 --- a/cpu/nios/asmi.c +++ b/cpu/nios/asmi.c @@ -183,7 +183,7 @@ static void asmi_status_wr (unsigned char status) * Device information ***********************************************************************/ typedef struct asmi_devinfo_t { - const char *name; /* Device name */ + const char *name; /* Device name */ unsigned char id; /* Device silicon id */ unsigned char size; /* Total size log2(bytes)*/ unsigned char num_sects; /* Number of sectors */ diff --git a/cpu/nios/cpu.c b/cpu/nios/cpu.c index 5519e8278..d2bb2c09d 100644 --- a/cpu/nios/cpu.c +++ b/cpu/nios/cpu.c @@ -34,7 +34,7 @@ int checkcpu (void) /* Get cpu version info */ val = rdctl (CTL_CPU_ID); - puts ("CPU: "); + printf ("CPU: "); printf ("%s", (val & 0x00008000) ? "Nios-16 " : "Nios-32 "); rev_major = (val>>12) & 0x07; rev_minor = (val>>4) & 0x0ff; diff --git a/cpu/nios/interrupts.c b/cpu/nios/interrupts.c index 75e491d84..48fc81e58 100644 --- a/cpu/nios/interrupts.c +++ b/cpu/nios/interrupts.c @@ -173,7 +173,7 @@ void irq_install_handler (int vec, interrupt_handler_t *handler, void *arg) } /*************************************************************************/ -#if defined(CONFIG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int vec; @@ -193,4 +193,4 @@ int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/nios/spi.c b/cpu/nios/spi.c index 640818014..f37146b79 100644 --- a/cpu/nios/spi.c +++ b/cpu/nios/spi.c @@ -63,10 +63,10 @@ static char quickhex (int i) return hex_digit[i]; } -static void memdump (const void *pv, int num) +static void memdump (void *pv, int num) { int i; - const unsigned char *pc = (const unsigned char *) pv; + unsigned char *pc = (unsigned char *) pv; for (i = 0; i < num; i++) printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); @@ -83,64 +83,26 @@ static void memdump (const void *pv, int num) #endif /* DEBUG */ -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct spi_slave *slave; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - slave = malloc(sizeof(struct spi_slave)); - if (!slave) - return NULL; - - slave->bus = bus; - slave->cs = cs; - - /* TODO: Add support for different modes and speeds */ - - return slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - free(slave); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - -} - /* * SPI transfer: * * See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf * for more informations. */ -int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout, - void *din, unsigned long flags) +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) { - const u8 *txd = dout; - u8 *rxd = din; int j; - DPRINT(("spi_xfer: slave %u:%u dout %08X din %08X bitlen %d\n", - slave->bus, slave->cs, *(uint *)dout, *(uint *)din, bitlen)); + DPRINT(("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", + (int)chipsel, *(uint *)dout, *(uint *)din, bitlen)); - memdump(dout, (bitlen + 7) / 8); + memdump((void*)dout, (bitlen + 7) / 8); - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); + if(chipsel != NULL) { + chipsel(1); /* select the target chip */ + } - if (!(flags & SPI_XFER_END) || bitlen > CFG_NIOS_SPIBITS) { - /* leave chip select active */ + if (bitlen > CFG_NIOS_SPIBITS) { /* leave chip select active */ spi->control |= NIOS_SPI_SSO; } @@ -152,11 +114,11 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout, while ((spi->status & NIOS_SPI_TRDY) == 0) ; - spi->txdata = (unsigned)(txd[j]); + spi->txdata = (unsigned)(dout[j]); while ((spi->status & NIOS_SPI_RRDY) == 0) ; - rxd[j] = (unsigned char)(spi->rxdata & 0xff); + din[j] = (unsigned char)(spi->rxdata & 0xff); #elif (CFG_NIOS_SPIBITS == 16) j++, j++) { @@ -164,15 +126,15 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout, while ((spi->status & NIOS_SPI_TRDY) == 0) ; if ((j+1) < ((bitlen + 7) / 8)) - spi->txdata = (unsigned)((txd[j] << 8) | txd[j+1]); + spi->txdata = (unsigned)((dout[j] << 8) | dout[j+1]); else - spi->txdata = (unsigned)(txd[j] << 8); + spi->txdata = (unsigned)(dout[j] << 8); while ((spi->status & NIOS_SPI_RRDY) == 0) ; - rxd[j] = (unsigned char)((spi->rxdata >> 8) & 0xff); + din[j] = (unsigned char)((spi->rxdata >> 8) & 0xff); if ((j+1) < ((bitlen + 7) / 8)) - rxd[j+1] = (unsigned char)(spi->rxdata & 0xff); + din[j+1] = (unsigned char)(spi->rxdata & 0xff); #else #error "*** unsupported value of CFG_NIOS_SPIBITS ***" @@ -180,14 +142,15 @@ int spi_xfer(struct spi_slave *slave, int bitlen, const void *dout, } - if (bitlen > CFG_NIOS_SPIBITS && (flags & SPI_XFER_END)) { + if (bitlen > CFG_NIOS_SPIBITS) { spi->control &= ~NIOS_SPI_SSO; } - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + if(chipsel != NULL) { + chipsel(0); /* deselect the target chip */ + } - memdump(din, (bitlen + 7) / 8); + memdump((void*)din, (bitlen + 7) / 8); return 0; } diff --git a/cpu/nios/start.S b/cpu/nios/start.S index 9e73941a5..cb1af3c8b 100644 --- a/cpu/nios/start.S +++ b/cpu/nios/start.S @@ -208,7 +208,7 @@ __start: * A control register that counts system clock cycles would be * a handy feature -- hint for Altera ;-) */ - .globl dly_clks + .globl dly_clks /* Each loop is 4 instructions as delay slot is always * executed. Each instruction is approximately 4 clocks * (according to some lame info from Altera). So ... diff --git a/cpu/nios2/Makefile b/cpu/nios2/Makefile index 75f30b43a..11fda50c0 100644 --- a/cpu/nios2/Makefile +++ b/cpu/nios2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,26 +23,22 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -SOBJS = exceptions.o -COBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o +AOBJS = exceptions.o +OBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) +all: .depend $(START) $(LIB) -all: $(obj).depend $(START) $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(AOBJS) + $(AR) crv $@ $(OBJS) $(AOBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) $(AOBJS:.o=.S) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c index ec5db31b0..4685161b8 100644 --- a/cpu/nios2/interrupts.c +++ b/cpu/nios2/interrupts.c @@ -27,7 +27,6 @@ #include #include -#include #include #include #include @@ -205,7 +204,7 @@ int interrupt_init (void) /*************************************************************************/ -#if defined(CONFIG_CMD_IRQ) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int i; @@ -229,4 +228,4 @@ int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S index 6c6f294b0..4c6e47066 100644 --- a/cpu/nios2/start.S +++ b/cpu/nios2/start.S @@ -178,20 +178,20 @@ _reloc: * Instruction performance varies based on the core. For cores * with icache and static/dynamic branch prediction (II/f, II/s): * - * Normal ALU (e.g. add, cmp, etc): 1 cycle - * Branch (correctly predicted, taken): 2 cycles + * Normal ALU (e.g. add, cmp, etc): 1 cycle + * Branch (correctly predicted, taken): 2 cycles * Negative offset is predicted (II/s). * * For cores without icache and no branch prediction (II/e): * - * Normal ALU (e.g. add, cmp, etc): 6 cycles - * Branch (no prediction): 6 cycles + * Normal ALU (e.g. add, cmp, etc): 6 cycles + * Branch (no prediction): 6 cycles * * For simplicity, if an instruction cache is implemented we * assume II/f or II/s. Otherwise, we use the II/e. * */ - .globl dly_clks + .globl dly_clks dly_clks: diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c index 697ed03a2..b5a29593e 100644 --- a/cpu/nios2/sysid.c +++ b/cpu/nios2/sysid.c @@ -40,7 +40,7 @@ void display_sysid (void) stamp = readl (&sysid->timestamp); localtime_r (&stamp, &t); asctime_r (&t, asc); - printf ("SYSID : %08lx, %s", readl (&sysid->id), asc); + printf ("SYSID : %08x, %s", readl (&sysid->id), asc); } diff --git a/cpu/omap3/Makefile b/cpu/omap3/Makefile new file mode 100644 index 000000000..129612ee9 --- /dev/null +++ b/cpu/omap3/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(CPU).a + +START = start.o + +COBJS = clock.o \ + cpu.o \ + interrupts.o \ + fastboot.o \ + mem.o \ + mmc.o \ + nand.o \ + sys_info.o \ + syslib.o + +AOBJS = lowlevel_init.o + +OBJS = $(COBJS) $(AOBJS) +all: .depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) $(START:.o=.S) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) $(START:.o=.S) > $@ + +sinclude .depend + +######################################################################### diff --git a/cpu/omap3/clock.c b/cpu/omap3/clock.c new file mode 100644 index 000000000..f5b628e3f --- /dev/null +++ b/cpu/omap3/clock.c @@ -0,0 +1,827 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; + +#ifdef CONFIG_OMAP36XX + +struct dpll_per_param { + unsigned int sys_clk; + unsigned int m; + unsigned int n; + unsigned int clkin; + unsigned int sd; + unsigned int dco; + unsigned int m2; + unsigned int m3; + unsigned int m4; + unsigned int m5; + unsigned int m6; + unsigned int m2div; +}; +typedef struct dpll_per_param dpll_per_param; +#define MAX_SIL_INDEX 1 + +#else + +typedef struct dpll_param dpll_per_param; +#define MAX_SIL_INDEX 3 + +#endif /* CONFIG_OMAP36XX */ + +typedef struct dpll_param dpll_param; + +/* Following functions are exported from lowlevel_init.S */ + +extern dpll_param * get_mpu_dpll_param(void); +extern dpll_param * get_iva_dpll_param(void); +extern dpll_param * get_core_dpll_param(void); +extern dpll_param * get_per_dpll_param(void); + +/************************************************************* + * get_sys_clk_speed - determine reference oscillator speed + * based on known 32kHz clock and gptimer. + *************************************************************/ +u32 get_osc_clk_speed(void) +{ + u32 start, cstart, cend, cdiff, val; + + val = __raw_readl(PRM_CLKSRC_CTRL); + /* If SYS_CLK is being divided by 2, remove for now */ + val = (val & (~BIT7)) | BIT6; + __raw_writel(val, PRM_CLKSRC_CTRL); + + /* enable timer2 */ + val = __raw_readl(CM_CLKSEL_WKUP) | BIT0; + __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */ + + /* Enable I and F Clocks for GPT1 */ + val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2; + __raw_writel(val, CM_ICLKEN_WKUP); + val = __raw_readl(CM_FCLKEN_WKUP) | BIT0; + __raw_writel(val, CM_FCLKEN_WKUP); + + __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */ + __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */ + /* enable 32kHz source *//* enabled out of reset */ + /* determine sys_clk via gauging */ + + start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */ + while (__raw_readl(S32K_CR) < start); /* dead loop till start time */ + cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */ + while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */ + cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */ + cdiff = cend - cstart; /* get elapsed ticks */ + + /* based on number of ticks assign speed */ + if (cdiff > 19000) + return (S38_4M); + else if (cdiff > 15200) + return (S26M); + else if (cdiff > 13000) + return (S24M); + else if (cdiff > 9000) + return (S19_2M); + else if (cdiff > 7600) + return (S13M); + else + return (S12M); +} + +/****************************************************************************** + * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on + * -- input oscillator clock frequency. + * + *****************************************************************************/ +void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel) +{ + if(osc_clk == S38_4M) + *sys_clkin_sel= 4; + else if(osc_clk == S26M) + *sys_clkin_sel = 3; + else if(osc_clk == S19_2M) + *sys_clkin_sel = 2; + else if(osc_clk == S13M) + *sys_clkin_sel = 1; + else if(osc_clk == S12M) + *sys_clkin_sel = 0; +} + +static int get_silindex(void) +{ + int sil_index = 0; + + /* + * The DPLL tables are defined according to sysclk value and + * silicon revision. The clk_index value will be used to get + * the values for that input sysclk from the DPLL param table + * and sil_index will get the values for that SysClk for the + * appropriate silicon rev. + */ +#ifdef CONFIG_OMAP36XX + sil_index = 0; +#else + if (cpu_is_3410()) { + sil_index = 2; + } else { + if (get_cpu_rev() == CPU_3XX_ES10) + sil_index = 0; + else if (get_cpu_rev() >= CPU_3XX_ES20) + sil_index = 1; + } +#endif + return sil_index; +} + +static dpll_param *_get_core_dpll(int clk_index, int sil_index) +{ + dpll_param *ret = (dpll_param *)get_core_dpll_param(); + ret += (MAX_SIL_INDEX * clk_index) + sil_index; + return ret; +} + +static dpll_param *_get_mpu_dpll(int clk_index, int sil_index) +{ + dpll_param *ret = (dpll_param *)get_mpu_dpll_param(); + ret += (MAX_SIL_INDEX * clk_index) + sil_index; + return ret; +} + +static dpll_per_param *_get_per_dpll(int clk_index) +{ + dpll_per_param *ret = (dpll_per_param *)get_per_dpll_param(); + ret += clk_index; + return ret; +} + +static dpll_param *_get_iva_dpll(int clk_index, int sil_index) +{ + dpll_param *ret = (dpll_param *)get_iva_dpll_param(); + ret += (MAX_SIL_INDEX * clk_index) + sil_index; + return ret; +} + +#ifdef CONFIG_OMAP36XX + +#define PER_M_BITS 12 +#define PER_M2_BITS 5 +#define PER_M3_BITS 6 +#define PER_M4_BITS 6 +#define PER_M5_BITS 6 +#define PER_M6_BITS 6 + +static void per_dpll_init_36XX(int clk_index) +{ + dpll_per_param *per; + + per = _get_per_dpll(clk_index); + + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + + sr32(CM_CLKSEL2_PLL, 8, PER_M_BITS, per->m); + sr32(CM_CLKSEL2_PLL, 0, 7, per->n); + sr32(PRM_CLKSRC_CTRL, 8, 1, per->clkin); + sr32(CM_CLKSEL2_PLL, 24, 7, per->sd); + sr32(CM_CLKSEL2_PLL, 21, 3, per->dco); + sr32(CM_CLKSEL3_PLL, 0, PER_M2_BITS, per->m2); + sr32(CM_CLKSEL_DSS, 8, PER_M3_BITS, per->m3); + sr32(CM_CLKSEL_DSS, 0, PER_M4_BITS, per->m4); + sr32(CM_CLKSEL_CAM, 0, PER_M5_BITS, per->m5); + sr32(CM_CLKSEL1_EMU, 24, PER_M6_BITS, per->m6); + sr32(CM_CLKSEL_CORE, 12, 2, per->m2div); + + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); +} + +static void iva_dpll_init_36XX(int clk_index, int sil_index) +{ + dpll_param *iva; + + iva = _get_iva_dpll(clk_index, sil_index); + + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); + + /* IVA bypass clock set to CORECLK/2=(100) at OPP1 */ + sr32(CM_CLKSEL1_PLL_IVA2, 19, 3, 2); /* set CLK_SRC */ + sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, iva->m); + sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, iva->n); + sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, iva->m2); + + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); +} + +static void mpu_dpll_init_36XX(int clk_index, int sil_index) +{ + dpll_param *mpu; + + mpu = _get_mpu_dpll(clk_index, sil_index); + + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, mpu->m); + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, mpu->n); + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, mpu->m2); + + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); +} + +#else /* 34xx */ + +#define PER_M_BITS 11 +#define PER_M2_BITS 5 +#define PER_M3_BITS 5 +#define PER_M4_BITS 5 +#define PER_M5_BITS 5 +#define PER_M6_BITS 5 + +static void per_dpll_init_34XX(int clk_index) +{ + dpll_per_param *dpll_param_p; + + sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP); + wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY); + + /* Getting the base address to PER DPLL param table*/ + /* Set N */ + dpll_param_p = (dpll_param *)get_per_dpll_param(); + /* Moving it to the right sysclk base */ + dpll_param_p = dpll_param_p + clk_index; + /* Errata 1.50 Workaround for 3430 ES1.0 only */ + /* If using default divisors, write default divisor + 1 + and then the actual divisor value */ + /* Need to change it to silicon and revisino check */ + if(1) { + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2 + 1); /* set M6 */ + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2 + 1); /* set M5 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2 + 1); /* set M4 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2 + 1); /* set M3 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2 + 1);/* set M2 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + } + else { + sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */ + sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */ + sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */ + sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */ + sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */ + } + sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */ + sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */ + sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */ + sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY); +} + +static void iva_dpll_init_34XX(int clk_index, int sil_index) +{ + dpll_param *dpll_param_p; + + /* Getting the base address to IVA DPLL param table*/ + dpll_param_p = (dpll_param *)get_iva_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* IVA DPLL (set to 12*20=240MHz) */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY); + sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */ + + /* IVA bypass clock set to CORECLK/4=(83Mhz) at OPP1 */ + sr32(CM_CLKSEL1_PLL_IVA2, 19, 3, 4); /* set CLK_SRC */ + sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */ + sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */ + sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY); +} + +static void mpu_dpll_init_34XX(int clk_index, int sil_index) +{ + dpll_param *dpll_param_p; + + /* Getting the base address to MPU DPLL param table*/ + dpll_param_p = (dpll_param *)get_mpu_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + /* MPU DPLL (unlocked already) */ + sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY); +} + +#endif + + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + void (*f_lock_pll) (u32, u32, u32, u32); + int xip_safe, p0, p1, p2, p3; + u32 osc_clk=0, sys_clkin_sel; + extern void *_end_vect, *_start; + u32 clk_index, sil_index=1; + dpll_param *dpll_param_p; + + f_lock_pll = + (void *)((u32) & _end_vect - (u32) & _start + SRAM_VECT_CODE); + + xip_safe = running_in_sram(); +#ifdef CONFIG_3430VIRTIO + xip_safe = 1; +#endif + /* Gauge the input clock speed and find out the sys_clkin_sel + * value corresponding to the input clock. + */ + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &sys_clkin_sel); + + sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */ + + sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ + clk_index = sys_clkin_sel; + + sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */ + + sil_index = get_silindex(); + + /* Unlock MPU DPLL (slows things down, and needed later) */ + sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY); + + /* Getting the base address of Core DPLL param table*/ + dpll_param_p = (dpll_param *)get_core_dpll_param(); + /* Moving it to the right sysclk and ES rev base */ + dpll_param_p = dpll_param_p + MAX_SIL_INDEX*clk_index + sil_index; + if(xip_safe){ + /* CORE DPLL */ + /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */ + sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY); + /* For 3430 ES1.0 Errata 1.50, default value directly doesnt + work. write another value and then default value. */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */ + sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */ + sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */ + sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */ + sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */ + sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only */ + sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */ + sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */ + sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */ + sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */ +#ifndef CONFIG_OMAP36XX + sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */ +#endif + sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */ + wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY); + } else if(running_in_flash()){ + /* if running from flash, jump to small relocated code area in SRAM.*/ + p0 = __raw_readl(CM_CLKEN_PLL); + sr32((u32)&p0, 0, 3, PLL_FAST_RELOCK_BYPASS); +#ifndef CONFIG_OMAP36XX + sr32((u32)&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */ +#endif + + p1 = __raw_readl(CM_CLKSEL1_PLL); + sr32((u32)&p1, 27, 2, dpll_param_p->m2); /* Set M2 */ + sr32((u32)&p1, 16, 11, dpll_param_p->m); /* Set M */ + sr32((u32)&p1, 8, 7, dpll_param_p->n); /* Set N */ + sr32((u32)&p1, 6, 1, 0); /* set source for 96M */ + p2 = __raw_readl(CM_CLKSEL_CORE); + sr32((u32)&p2, 8, 4, CORE_SSI_DIV); /* ssi */ + sr32((u32)&p2, 4, 2, CORE_FUSB_DIV); /* fsusb ES1 only*/ + sr32((u32)&p2, 2, 2, CORE_L4_DIV); /* l4 */ + sr32((u32)&p2, 0, 2, CORE_L3_DIV); /* l3 */ + + p3 = CM_IDLEST_CKGEN; + + (*f_lock_pll) (p0, p1, p2, p3); + } + +#ifdef CONFIG_OMAP36XX + per_dpll_init_36XX(clk_index); + iva_dpll_init_36XX(clk_index, sil_index); + mpu_dpll_init_36XX(clk_index, sil_index); +#else + per_dpll_init_34XX(clk_index); + iva_dpll_init_34XX(clk_index, sil_index); + mpu_dpll_init_34XX(clk_index, sil_index); +#endif + + /* Set up GPTimers to sys_clk source only */ + sr32(CM_CLKSEL_PER, 0, 8, 0xff); + sr32(CM_CLKSEL_WKUP, 0, 1, 1); + + sdelay(5000); +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs (GPT2, UART1,...) + ******************************************************************/ +void per_clocks_enable(void) +{ + /* Enable GP2 timer. */ + sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */ + sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */ + sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */ + +#ifdef CFG_NS16550 + /* Enable UART1 clocks */ + sr32(CM_FCLKEN1_CORE, 13, 1, 0x1); + sr32(CM_ICLKEN1_CORE, 13, 1, 0x1); + /* Enable UART3 clocks */ + sr32(CM_FCLKEN_PER, 11, 1, 0x1); + sr32(CM_ICLKEN_PER, 11, 1, 0x1); +#endif + +#ifdef CONFIG_3430ZOOM2 + /* Zoom2 uses GPIO to control LED's and to detect if + the debug board is present */ + /* GPIO2 */ + sr32(CM_FCLKEN_PER, CLKEN_PER_EN_GPIO2_BIT, 1, 1); + sr32(CM_ICLKEN_PER, CLKEN_PER_EN_GPIO2_BIT, 1, 1); + /* GPIO3 */ + sr32(CM_FCLKEN_PER, CLKEN_PER_EN_GPIO3_BIT, 1, 1); + sr32(CM_ICLKEN_PER, CLKEN_PER_EN_GPIO3_BIT, 1, 1); + /* GPIO5 */ + sr32(CM_FCLKEN_PER, CLKEN_PER_EN_GPIO5_BIT, 1, 1); + sr32(CM_ICLKEN_PER, CLKEN_PER_EN_GPIO5_BIT, 1, 1); + /* GPIO6 */ + sr32(CM_FCLKEN_PER, CLKEN_PER_EN_GPIO6_BIT, 1, 1); + sr32(CM_ICLKEN_PER, CLKEN_PER_EN_GPIO6_BIT, 1, 1); +#endif + +#ifdef CONFIG_FASTBOOT + /* USB : EN_HSOTGUSB */ + sr32(CM_ICLKEN1_CORE, 4, 1, 1); +#endif + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + /* Turn on all 3 I2C clocks*/ + sr32(CM_FCLKEN1_CORE, 15, 3, 0x7); + sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */ +#endif + +#ifdef CONFIG_MMC + sr32(CM_FCLKEN1_CORE, 24, 1, 1); + sr32(CM_ICLKEN1_CORE, 24, 1, 1); +#endif /* CONFIG_MMC */ + + /* Enable the ICLK for 32K Sync Timer as its used in udelay */ + sr32(CM_ICLKEN_WKUP,2, 1, 0x1); + +//#define CLOCKS_ALL_ON 1 +#ifdef CLOCKS_ALL_ON + #define FCK_IVA2_ON 0x00000001 + #define FCK_CORE1_ON 0x03fffe29 + #define ICK_CORE1_ON 0x3ffffffb + #define ICK_CORE2_ON 0x0000001f + #define FCK_WKUP_ON 0x000000e9 + #define ICK_WKUP_ON 0x0000003f + #define FCK_DSS_ON 0x00000005 /* tv+dss1 (not dss2) */ + #define ICK_DSS_ON 0x00000001 + #define FCK_CAM_ON 0x00000001 + #define ICK_CAM_ON 0x00000001 + #define FCK_PER_ON 0x0003ffff + #define ICK_PER_ON 0x0003ffff + sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON); + sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON); + sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON); + sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON); + sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON); + sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON); + sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON); + sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON); + sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON); + sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON); + sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON); + sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON); +#endif + sdelay(1000); +} + +/* + * Clock Info + */ +#if defined(CONFIG_CMD_CLOCK) && defined(CONFIG_CMD_CLOCK_INFO_CPU) + +static void print_dpll_param(dpll_param *r, char *s) +{ + printf("DPLL %s ", s); + printf("m %d n %d fsel %d m2 %d\n", r->m, r->n, r->fsel, r->m2); +} + +static void print_dpll_per_param(dpll_per_param *r, char *s) +{ + printf("DPLL %s ", s); +#ifdef CONFIG_OMAP36XX + printf("sys clk %d m %d n %d clkin_div %d sd_div %d dco_sel %d" + "\n\tm2 %d m3 %d m4 %d m5 %d m6 %d m2div %d\n", + r->sys_clk, r->m, r->n, r->clkin, r->sd, r->dco, + r->m2, r->m3, r->m4, r->m5, r->m6, r->m2div); +#else + printf("m %d n %d fsel %d m2 %d\n", r->m, r->n, r->fsel, r->m2); +#endif + +} + +void cpu_clock_info(void) +{ + u32 osc_clk, clk_index; + int sil_index; + dpll_param *core, *mpu, *iva; + dpll_per_param *per; + + osc_clk = get_osc_clk_speed(); + get_sys_clkin_sel(osc_clk, &clk_index); + sil_index = get_silindex(); + + printf("OSC CLK %d\n", osc_clk); + printf("Clock index %d Silicon Index %d\n", clk_index, sil_index); + + core = _get_core_dpll(clk_index, sil_index); + print_dpll_param(core, "core params"); + + per = _get_per_dpll(clk_index); + print_dpll_per_param(per, "per params "); + + mpu = _get_mpu_dpll(clk_index, sil_index); + print_dpll_param(mpu, "mpu params "); + + iva = _get_iva_dpll(clk_index, sil_index); + print_dpll_param(iva, "iva params "); + + /* Now verify */ + { + /* System clk */ + u32 sys_clk; + u32 sys_clk_div; + u32 sys_clk_calc; + + /* PER / DPLL 4 clk */ + u32 per_m, per_n; + u32 per_m2; + u32 clk_96m_calc, per_clk_calc; + u32 per_m3; + u32 per_m4; + u32 per_m5; + u32 per_m6; +#ifdef CONFIG_OMAP36XX + u32 per_clk_div; + u32 per_dco_sel; + u32 per_sd_div; + u32 per_m2_div; +#else + u32 per_fsel; +#endif + /* MPU clk */ + u32 mpu_m, mpu_n, mpu_m2; +#ifndef CONFIG_OMAP36XX + u32 mpu_fsel; +#endif + + /* IVA clk */ + u32 iva_m, iva_n, iva_m2; +#ifndef CONFIG_OMAP36XX + u32 iva_fsel; +#endif + + printf("Verifying from hardware registers..\n"); + + /* Sys clk */ + sys_clk = readl(PRM_CLKSEL); + sys_clk >>= 0; + + sys_clk &= ((1 << 3) - 1); + + sys_clk_calc = 0; + + sys_clk_div = readl(PRM_CLKSRC_CTRL); + sys_clk_div >>= 6; + sys_clk_div &= ((1 << 2) - 1); + + if (4 == sys_clk) + sys_clk_calc = 38400000; + else if (3 == sys_clk) + sys_clk_calc = 26000000; + else if (2 == sys_clk) + sys_clk_calc = 19200000; + else if (1 == sys_clk) + sys_clk_calc = 13000000; + else if (0 == sys_clk) + sys_clk_calc = 12000000; + + if (sys_clk_div) + sys_clk_calc /= sys_clk_div; + else + sys_clk_calc = 0; + + printf("sys_clk %d sys_clk_div %d\n", sys_clk, sys_clk_div); + printf("calculated system clock %d\n", sys_clk_calc); + + per_clk_calc = sys_clk_calc; + + /* Per clk */ + per_m = readl(CM_CLKSEL2_PLL); + per_m >>= 8; + per_m &= ((1 << PER_M_BITS) - 1); + + per_n = readl(CM_CLKSEL2_PLL); + per_n >>= 0; + per_n &= ((1 << 7) - 1); + + printf("per m %d n %d ", per_m, per_n); + +#ifndef CONFIG_OMAP36XX + per_fsel = readl(CM_CLKEN_PLL); + per_fsel >>= 20; + per_fsel &= ((1 << 4) - 1); + + printf("fsel %d ", per_fsel); +#endif + + per_m2 = readl(CM_CLKSEL3_PLL); + per_m2 >>= 0; + per_m2 &= ((1 << PER_M2_BITS) - 1); + + per_m3 = readl(CM_CLKSEL_DSS); + per_m3 >>= 8; + per_m3 &= ((1 << PER_M3_BITS) - 1); + + per_m4 = readl(CM_CLKSEL_DSS); + per_m4 >>= 0; + per_m4 &= ((1 << PER_M4_BITS) - 1); + + per_m5 = readl(CM_CLKSEL_CAM); + per_m5 >>= 0; + per_m5 &= ((1 << PER_M5_BITS) - 1); + + per_m6 = readl(CM_CLKSEL1_EMU); + per_m6 >>= 24; + per_m6 &= ((1 << PER_M6_BITS) - 1); + +#ifdef CONFIG_OMAP36XX + per_clk_div = readl(PRM_CLKSRC_CTRL); + per_clk_div >>= 8; + per_clk_div &= 1; + + per_dco_sel = readl(CM_CLKSEL2_PLL); + per_dco_sel >>= 21; + per_dco_sel &= ((1 << 3) - 1); + + per_sd_div = readl(CM_CLKSEL2_PLL); + per_sd_div >>= 24; + per_sd_div &= ((1 << 7) - 1); + + /* Div by 6.5 */ + if (per_clk_div) { + per_clk_calc *= 2; + per_clk_calc /= ((per_n + 1) * 13); + } else { + per_clk_calc /= (per_n + 1); + } + + /* M2 div */ + per_m2_div = readl(CM_CLKSEL_CORE); + per_m2_div >>= 12; + per_m2_div &= 3; + + per_m2 *= per_m2_div; + + printf("clkdiv %d dco_sel %d sd_div %d m2_div %d ", + per_clk_div, per_dco_sel, per_sd_div, per_m2_div); + +#else + per_clk_calc /= (per_n + 1); +#endif + + printf("m2 %d m3 %d m4 %d m5 %d m6 %d", + per_m2, per_m3, per_m4, per_m5, per_m6); + + per_clk_calc *= per_m; + + if (per_m2) + clk_96m_calc = per_clk_calc / per_m2; + else + clk_96m_calc = 0; + + printf("\n"); + if (!(per_clk_calc % 1000000)) + printf("dpll4 base clk %d MHz\n", + per_clk_calc / 1000000); + else if (!(per_clk_calc % 1000)) + printf("dpll4 base clk %d KHz\n", per_clk_calc / 1000); + else + printf("dpll4 base clk %d Hz\n", per_clk_calc); + + if (!(clk_96m_calc % 1000000)) + printf("\t96M clk %d MHz\n", clk_96m_calc / 1000000); + else if (!(clk_96m_calc % 1000)) + printf("\t96M clk %d KHz\n", clk_96m_calc / 1000); + else + printf("\t96M clk %d Hz\n", clk_96m_calc); + + /* MPU */ + mpu_m = readl(CM_CLKSEL1_PLL_MPU); + mpu_m >>= 8; + mpu_m &= ((1 << 11) - 1); + + mpu_n = readl(CM_CLKSEL1_PLL_MPU); + mpu_n >>= 0; + mpu_n &= ((1 << 5) - 1); + + printf("mpu m %d n %d ", mpu_m, mpu_n); + +#ifndef CONFIG_OMAP36XX + mpu_fsel = readl(CM_CLKEN_PLL_MPU); + mpu_fsel >>= 4; + mpu_fsel &= ((1 << 4) - 1); + + printf("fsel %d ", mpu_fsel); +#endif + + mpu_m2 = readl(CM_CLKSEL2_PLL_MPU); + mpu_m2 >>= 0; + mpu_m2 &= ((1 << 5) - 1); + + printf("m2 %d\n", mpu_m2); + + /* IVA */ + iva_m = readl(CM_CLKSEL1_PLL_IVA2); + iva_m >>= 8; + iva_m &= ((1 << 11) - 1); + + iva_n = readl(CM_CLKSEL1_PLL_IVA2); + iva_n >>= 0; + iva_n &= ((1 << 7) - 1); + + printf("iva m %d n %d ", iva_m, iva_n); + +#ifndef CONFIG_OMAP36XX + iva_fsel = readl(CM_CLKEN_PLL_IVA2); + iva_fsel >>= 4; + iva_fsel &= ((1 << 4) - 1); + + printf("fsel %d ", iva_fsel); +#endif + + iva_m2 = readl(CM_CLKSEL2_PLL_IVA2); + iva_m2 >>= 0; + iva_m2 &= ((1 << 5) - 1); + + printf("m2 %d\n", iva_m2); + } +} +#endif diff --git a/cpu/omap3/config.mk b/cpu/omap3/config.mk new file mode 100644 index 000000000..f29f86ad2 --- /dev/null +++ b/cpu/omap3/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +PLATFORM_CPPFLAGS += -march=armv7-a +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) diff --git a/cpu/omap3/cpu.c b/cpu/omap3/cpu.c new file mode 100644 index 000000000..1df5a94ec --- /dev/null +++ b/cpu/omap3/cpu.c @@ -0,0 +1,284 @@ +/* + * (C) Copyright 2004 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include +#include +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) +#include +#endif +#include +#include +#include + +#ifdef CONFIG_USE_IRQ +DECLARE_GLOBAL_DATA_PTR; +#endif + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1 (void) +{ + unsigned long value; + + __asm__ __volatile__( + "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" + : "=r" (value) + : + : "memory"); + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1 (unsigned long value) +{ + __asm__ __volatile__( + "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" + : + : "r" (value) + : "memory"); + + read_p15_c1 (); +} + +static void cp_delay (void) +{ + volatile int i; + + /* Many OMAP regs need at least 2 nops */ + for (i = 0; i < 100; i++); +} + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ +#define C1_WB (1<<3) /* merging write buffer on/off */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ + + +void l2cache_disable(void); +int get_boot_type(void); +void v7_flush_dcache_all(int, int); +int get_device_type(void); +int get_cpu_rev(void); +void arm_cache_flush(void); + +int cpu_init (void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux (void) +{ + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + disable_interrupts (); + +#ifdef CONFIG_LCD + { + extern void lcd_disable(void); + extern void lcd_panel_disable(void); + + lcd_disable(); /* proper disable of lcd & panel */ + lcd_panel_disable(); + } +#endif + +{ + unsigned int i; + + /* turn off I/D-cache */ + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + i &= ~(C1_DC | C1_IC); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + + /* invalidate I-cache */ + arm_cache_flush(); + + i = 0; + /* mem barrier to sync up things */ + asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); +} + + /* Disable the NOR flash so the kernel reinitializes */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + sdelay(1000); + + return(0); +} + +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts (); + reset_cpu (0); + /*NOTREACHED*/ + return(0); +} + +void icache_enable (void) +{ + ulong reg; + + reg = read_p15_c1 (); /* get control reg. */ + cp_delay (); + reg = reg | C1_IC; + write_p15_c1 (reg); +} + +void icache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_IC); +} + +void l2cache_enable(void) +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r" (j)); + __asm__ __volatile__("mov %0, r0":"=r" (i)); + + /* GP Device ROM code API usage here */ + /* r12 = AUXCR Write function and r0 value */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("orr r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r" (i)); + __asm__ __volatile__("mov r12, %0":"=r" (j)); + } +} + +void l2cache_disable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r" (i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r" (i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r" (j)); + __asm__ __volatile__("mov %0, r0":"=r" (i)); + + /* GP Device ROM code API usage here */ + /* r12 = AUXCR Write function and r0 value */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("bic r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r" (i)); + __asm__ __volatile__("mov r12, %0":"=r" (j)); + } +} + +int icache_status (void) +{ + return(read_p15_c1 () & C1_IC) != 0; +} + +/********************************************************** + * Routine: setup_auxcr() + * Description: Write to AuxCR desired value using SMI. + * general use. + ***********************************************************/ +void setup_auxcr(int device_type, int boot_type) +{ + unsigned long i; + volatile unsigned int j; + + if (device_type == GP_DEVICE) { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r" (j)); + __asm__ __volatile__("mov %0, r0":"=r" (i)); + + /* GP Device ROM code API usage here */ + /* r12 = AUXCR Write function and r0 value */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + /* Enabling IBE. ASA is disabled following recommendation from ARM */ + __asm__ __volatile__("orr r0, r0, #0x40"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + + __asm__ __volatile__("mov r0, %0":"=r" (i)); + __asm__ __volatile__("mov r12, %0":"=r" (j)); + } + else if (((device_type == EMU_DEVICE) || (device_type == HS_DEVICE)) && + (!boot_type)) { + __asm__ __volatile__("write_aux_control_params:\ + .word 0x1, 0x42"); + __asm__ __volatile__("stmfd r13!, {r0-r12, r14}"); + __asm__ __volatile__("mov r0, #42"); + __asm__ __volatile__("mov r12, r0"); + __asm__ __volatile__("mov r1, #0"); + __asm__ __volatile__("mov r2, #4"); + __asm__ __volatile__("mov r6, #0xff"); + __asm__ __volatile__("adr r3, write_aux_control_params"); + __asm__ __volatile__("mcr p15, 0, r0, c7, c5, 4"); + __asm__ __volatile__("mcr p15, 0, r0, c7, c10, 5"); + __asm__ __volatile__(".word 0xE1600071"); + __asm__ __volatile__("ldmfd r13!, {r0-r12, r14}"); + } +} diff --git a/cpu/omap3/fastboot.c b/cpu/omap3/fastboot.c new file mode 100644 index 000000000..aad0cc2b2 --- /dev/null +++ b/cpu/omap3/fastboot.c @@ -0,0 +1,1218 @@ +/* + * Copyright 2008 - 2009 (C) Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_FASTBOOT) + +#include "usb_debug_macros.h" + +#define CONFUSED() printf ("How did we get here %s %d ? \n", __FILE__, __LINE__) + +/* memory mapped registers */ +static volatile u8 *pwr = (volatile u8 *) OMAP34XX_USB_POWER; +static volatile u16 *csr0 = (volatile u16 *) OMAP34XX_USB_CSR0; +static volatile u8 *index = (volatile u8 *) OMAP34XX_USB_INDEX; +static volatile u8 *txfifosz = (volatile u8 *) OMAP34XX_USB_TXFIFOSZ; +static volatile u8 *rxfifosz = (volatile u8 *) OMAP34XX_USB_RXFIFOSZ; +static volatile u16 *txfifoadd = (volatile u16 *) OMAP34XX_USB_TXFIFOADD; +static volatile u16 *rxfifoadd = (volatile u16 *) OMAP34XX_USB_RXFIFOADD; + +#define BULK_ENDPOINT 1 +static volatile u16 *peri_rxcsr = (volatile u16 *) OMAP34XX_USB_RXCSR(BULK_ENDPOINT); +static volatile u16 *rxmaxp = (volatile u16 *) OMAP34XX_USB_RXMAXP(BULK_ENDPOINT); +static volatile u16 *rxcount = (volatile u16 *) OMAP34XX_USB_RXCOUNT(BULK_ENDPOINT); +static volatile u16 *peri_txcsr = (volatile u16 *) OMAP34XX_USB_TXCSR(BULK_ENDPOINT); +static volatile u16 *txmaxp = (volatile u16 *) OMAP34XX_USB_TXMAXP(BULK_ENDPOINT); +static volatile u8 *bulk_fifo = (volatile u8 *) OMAP34XX_USB_FIFO(BULK_ENDPOINT); + +#define DMA_CHANNEL 1 +static volatile u8 *peri_dma_intr = (volatile u8 *) OMAP34XX_USB_DMA_INTR; +static volatile u16 *peri_dma_cntl = (volatile u16 *) OMAP34XX_USB_DMA_CNTL_CH(DMA_CHANNEL); +static volatile u32 *peri_dma_addr = (volatile u32 *) OMAP34XX_USB_DMA_ADDR_CH(DMA_CHANNEL); +static volatile u32 *peri_dma_count = (volatile u32 *) OMAP34XX_USB_DMA_COUNT_CH(DMA_CHANNEL); + +static volatile u32 *otg_sysconfig = (volatile u32 *) OMAP34XX_OTG_SYSCONFIG; +static volatile u32 *otg_interfsel = (volatile u32 *) OMAP34XX_OTG_INTERFSEL; +static volatile u32 *otg_forcestdby = (volatile u32 *) OMAP34XX_OTG_FORCESTDBY; + +/* This is the TI USB vendor id */ +#define DEVICE_VENDOR_ID 0x0451 +/* This is just made up.. */ +#define DEVICE_PRODUCT_ID 0xCAFE +/* This is just made up.. */ +#define DEVICE_BCD 0x0311; + +/* String 0 is the language id */ +#define DEVICE_STRING_PRODUCT_INDEX 1 +#define DEVICE_STRING_SERIAL_NUMBER_INDEX 2 +#define DEVICE_STRING_CONFIG_INDEX 3 +#define DEVICE_STRING_INTERFACE_INDEX 4 +#define DEVICE_STRING_MANUFACTURER_INDEX 5 +#define DEVICE_STRING_MAX_INDEX DEVICE_STRING_MANUFACTURER_INDEX +#define DEVICE_STRING_LANGUAGE_ID 0x0409 /* English (United States) */ + +/* Define this to use 1.1 / fullspeed */ +/* #define CONFIG_USB_1_1_DEVICE */ + +/* In high speed mode packets are 512 + In full speed mode packets are 64 */ +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 (0x0200) +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 (0x0040) +#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 (0x0200) +#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 (0x0040) + +/* Same, just repackaged as + 2^(m+3), 64 = 2^6, m = 3 */ +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_BITS_2_0 (6) +#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_BITS_1_1 (3) +#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE_BITS_2_0 (6) +#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE_BITS_1_1 (3) + +#define CONFIGURATION_NORMAL 1 + +#define TX_LAST() \ + *csr0 |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_P_DATAEND); \ + while (*csr0 & MUSB_CSR0_RXPKTRDY) \ + udelay(1); + +#define NAK_REQ() *csr0 |= MUSB_CSR0_P_SENDSTALL +#define ACK_REQ() *csr0 |= MUSB_CSR0_P_DATAEND + +#define ACK_RX() *peri_rxcsr |= (MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_DATAEND) + +static u8 fastboot_fifo[MUSB_EP0_FIFOSIZE]; +static u16 fastboot_fifo_used = 0; + +static unsigned int set_address = 0; +static u8 faddr = 0xff; + +static unsigned int high_speed = 0; + +static unsigned int deferred_rx = 0; + +static struct usb_device_request req; + +/* The packet size is dependend of the speed mode + In high speed mode packets are 512 + In full speed mode packets are 64 + Set to maximum of 512 */ + +/* Note: The start address (written to the MUSB_DMA_ADDR_CH(n) register) + must be word aligned */ +static u8 fastboot_bulk_fifo[0x0200] __attribute__ ((aligned(0x4))); +static char *device_strings[DEVICE_STRING_MANUFACTURER_INDEX+1]; + +static struct cmd_fastboot_interface *fastboot_interface = NULL; + +#ifdef DEBUG_FASTBOOT +static void fastboot_db_regs(void) +{ + printf("fastboot_db_regs\n"); + u8 b; + u16 s; + + /* */ + b = inb (OMAP34XX_USB_FADDR); + printf ("\tfaddr 0x%2.2x\n", b); + + b = inb (OMAP34XX_USB_POWER); + PRINT_PWR(b); + + s = inw (OMAP34XX_USB_CSR0); + PRINT_CSR0(s); + + b = inb (OMAP34XX_USB_DEVCTL); + PRINT_DEVCTL(b); + + b = inb (OMAP34XX_USB_CONFIGDATA); + PRINT_CONFIG(b); + + s = inw (OMAP34XX_USB_FRAME); + printf ("\tframe 0x%4.4x\n", s); + b = inb (OMAP34XX_USB_INDEX); + printf ("\tindex 0x%2.2x\n", b); + + s = *rxmaxp; + PRINT_RXMAXP(s); + + s = *peri_rxcsr; + PRINT_RXCSR(s); + + s = *txmaxp; + PRINT_TXMAXP(s); + + s = *peri_txcsr; + PRINT_TXCSR(s); +} + +static void fastboot_db_otg_regs(void) +{ + u32 v; + v = __raw_readl(OMAP34XX_OTG_REVISION); + printf("OTG_REVISION 0x%x\n", v); + v = __raw_readl(OMAP34XX_OTG_SYSCONFIG); + printf("OTG_SYSCONFIG 0x%x\n", v); + v = __raw_readl(OMAP34XX_OTG_SYSSTATUS); + printf("OTG_SYSSTATUS 0x%x\n", v); + v = __raw_readl(OMAP34XX_OTG_INTERFSEL); + printf("OTG_INTERFSEL 0x%x\n", v); + v = __raw_readl(OMAP34XX_OTG_FORCESTDBY); + printf("OTG_FORCESTDBY 0x%x\n", v); +} +#endif + +static void fastboot_bulk_endpoint_reset (void) +{ + u8 old_index; + /* save old index */ + old_index = *index; + + /* set index to tx/rx endpoint */ + *index = BULK_ENDPOINT; + + /* Address starts at the end of EP0 fifo, shifted right 3 (8 bytes) */ + *txfifoadd = MUSB_EP0_FIFOSIZE >> 3; + + /* Size depends on the mode. Do not double buffer */ + if (high_speed) { + *txfifosz = TX_ENDPOINT_MAXIMUM_PACKET_SIZE_BITS_2_0; + } else { + *txfifosz = TX_ENDPOINT_MAXIMUM_PACKET_SIZE_BITS_1_1; + } + + /* + * Double buffer the rx fifo because it handles the large transfers + * The extent is now double and must be considered if another fifo is + * added to the end of this one. + */ + if (high_speed) { + *rxfifosz = + RX_ENDPOINT_MAXIMUM_PACKET_SIZE_BITS_2_0 | + MUSB_RXFIFOSZ_DPB; + *rxfifoadd = (MUSB_EP0_FIFOSIZE + TX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0) >> 3; + } else { + *rxfifosz = + RX_ENDPOINT_MAXIMUM_PACKET_SIZE_BITS_1_1 | + MUSB_RXFIFOSZ_DPB; + *rxfifoadd = (MUSB_EP0_FIFOSIZE + TX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1) >> 3; + } + + /* restore index */ + *index = old_index; + + /* Setup Rx endpoint for Bulk OUT */ + *rxmaxp = fastboot_fifo_size(); + + /* Flush anything on fifo */ + while (*peri_rxcsr & MUSB_RXCSR_RXPKTRDY) + { + *peri_rxcsr |= MUSB_RXCSR_FLUSHFIFO; + udelay(1); + } + /* No dma, enable bulkout, */ + *peri_rxcsr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_ISO); + /* reset endpoint data */ + *peri_rxcsr |= MUSB_RXCSR_CLRDATATOG; + + /* Setup Tx endpoint for Bulk IN */ + /* Set max packet size per usb 1.1 / 2.0 */ + *txmaxp = fastboot_fifo_size(); + + /* Flush anything on fifo */ + while (*peri_txcsr & MUSB_TXCSR_FIFONOTEMPTY) + { + *peri_txcsr |= MUSB_TXCSR_FLUSHFIFO; + udelay(1); + } + + /* No dma, enable bulkout, no underflow */ + *peri_txcsr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_ISO | MUSB_TXCSR_P_UNDERRUN); + /* reset endpoint data, shared fifo with rx */ + *peri_txcsr |= (MUSB_TXCSR_CLRDATATOG | MUSB_TXCSR_MODE); +} + +static void fastboot_reset (void) +{ + OMAP3_LED_ERROR_ON (); + + /* Reset OTG */ + /* Set OTG to always be on */ + *otg_sysconfig = (OMAP34XX_OTG_SYSCONFIG_NO_STANDBY_MODE | + OMAP34XX_OTG_SYSCONFIG_NO_IDLE_MODE); + + /* Set the interface */ + *otg_interfsel = OMAP34XX_OTG_INTERFSEL_OMAP; + + /* Clear force standby */ + *otg_forcestdby &= ~OMAP34XX_OTG_FORCESTDBY_STANDBY; + + /* Reset MUSB */ + *pwr &= ~MUSB_POWER_SOFTCONN; + udelay(2 * 500000); /* 1 sec */ + + OMAP3_LED_ERROR_OFF (); + + /* Reset address */ + faddr = 0xff; + + /* Reset */ +#ifdef CONFIG_USB_1_1_DEVICE + *pwr &= ~MUSB_POWER_HSENAB; + *pwr |= MUSB_POWER_SOFTCONN; +#else + *pwr |= (MUSB_POWER_SOFTCONN | MUSB_POWER_HSENAB); +#endif + /* Bulk endpoint fifo */ + fastboot_bulk_endpoint_reset (); + + OMAP3_LED_ERROR_ON (); +} + +static u8 read_fifo_8(void) +{ + u8 val; + + val = inb (OMAP34XX_USB_FIFO_0); + return val; +} + +static u8 read_bulk_fifo_8(void) +{ + u8 val; + + val = *bulk_fifo; + return val; +} + +static int read_bulk_fifo_dma(u8 *buf, u32 size) +{ + int ret = 0; + + /* Set the address */ + *peri_dma_addr = (u32) buf; + /* Set the transfer size */ + *peri_dma_count = size; + /* + * Set the control parts, + * The size is either going to be 64 or 512 which + * is ok for burst mode 3 which does increment by 16. + */ + *peri_dma_cntl = + MUSB_DMA_CNTL_BUSRT_MODE_3 | + MUSB_DMA_CNTL_END_POINT(BULK_ENDPOINT) | + MUSB_DMA_CNTL_MODE_1 | + MUSB_DMA_CNTL_WRITE | + MUSB_DMA_CNTL_ENABLE; + + while (1) { + + if (MUSB_DMA_CNTL_ERR & *peri_dma_cntl) { + ret = 1; + break; + } + + if (0 == *peri_dma_count) + break; + } + return ret; +} + +static void write_fifo_8(u8 val) +{ + outb (val, OMAP34XX_USB_FIFO_0); +} + +static void write_bulk_fifo_8(u8 val) +{ + *bulk_fifo = val; +} + +static void read_request(void) +{ + int i; + + for (i = 0; i < 8; i++) + fastboot_fifo[i] = read_fifo_8 (); + memcpy (&req, &fastboot_fifo[0], 8); + fastboot_fifo_used = 0; + + *csr0 |= MUSB_CSR0_P_SVDRXPKTRDY; + + while (*csr0 & MUSB_CSR0_RXPKTRDY) + udelay(1); + +} + +static int do_usb_req_set_interface(void) +{ + int ret = FASTBOOT_OK; + + /* Only support interface 0, alternate 0 */ + if ((0 == req.wIndex) && + (0 == req.wValue)) + { + fastboot_bulk_endpoint_reset (); + ACK_REQ(); + } + else + { + NAK_REQ(); + } + + return ret; +} + +static int do_usb_req_set_address(void) +{ + int ret = FASTBOOT_OK; + + if (0xff == faddr) + { + faddr = (u8) (req.wValue & 0x7f); + set_address = 1; + + /* Check if we are in high speed mode */ + if (*pwr & MUSB_POWER_HSMODE) + high_speed = 1; + else + high_speed = 0; + + ACK_REQ(); + } + else + { + NAK_REQ(); + } + + return ret; +} + + +static int do_usb_req_set_configuration(void) +{ + int ret = FASTBOOT_OK; + + if (0xff == faddr) { + NAK_REQ(); + } else { + if (0 == req.wValue) { + /* spec says to go to address state.. */ + faddr = 0xff; + ACK_REQ(); + } else if (CONFIGURATION_NORMAL == req.wValue) { + /* This is the one! */ + + /* Bulk endpoint fifo */ + fastboot_bulk_endpoint_reset(); + + ACK_REQ(); + } else { + /* Only support 1 configuration so nak anything else */ + NAK_REQ(); + } + } + + return ret; +} + +static int do_usb_req_set_feature(void) +{ + int ret = FASTBOOT_OK; + + NAK_REQ(); + + return ret; +} + +static int do_usb_req_get_descriptor(void) +{ + int ret = FASTBOOT_OK; + + if (0 == req.wLength) + { + ACK_REQ(); + } + else + { + unsigned int byteLoop; + + if (USB_DT_DEVICE == (req.wValue >> 8)) + { + struct usb_device_descriptor d; + d.bLength = MIN(req.wLength, sizeof (d)); + + d.bDescriptorType = USB_DT_DEVICE; +#ifdef CONFIG_USB_1_1_DEVICE + d.bcdUSB = 0x110; +#else + d.bcdUSB = 0x200; +#endif + d.bDeviceClass = 0xff; + d.bDeviceSubClass = 0xff; + d.bDeviceProtocol = 0xff; + d.bMaxPacketSize0 = 0x40; + d.idVendor = DEVICE_VENDOR_ID; + d.idProduct = DEVICE_PRODUCT_ID; + d.bcdDevice = DEVICE_BCD; + d.iManufacturer = DEVICE_STRING_MANUFACTURER_INDEX; + d.iProduct = DEVICE_STRING_PRODUCT_INDEX; + d.iSerialNumber = DEVICE_STRING_SERIAL_NUMBER_INDEX; + d.bNumConfigurations = 1; + + memcpy (&fastboot_fifo, &d, d.bLength); + for (byteLoop = 0; byteLoop < d.bLength; byteLoop++) + write_fifo_8 (fastboot_fifo[byteLoop]); + + TX_LAST(); + } + else if (USB_DT_CONFIG == (req.wValue >> 8)) + { + struct usb_configuration_descriptor c; + struct usb_interface_descriptor i; + struct usb_endpoint_descriptor e1, e2; + unsigned char bytes_remaining = req.wLength; + unsigned char bytes_total = 0; + + c.bLength = MIN(bytes_remaining, sizeof (c)); + c.bDescriptorType = USB_DT_CONFIG; + /* Set this to the total we want */ + c.wTotalLength = sizeof (c) + sizeof (i) + sizeof (e1) + sizeof (e2); + c.bNumInterfaces = 1; + c.bConfigurationValue = CONFIGURATION_NORMAL; + c.iConfiguration = DEVICE_STRING_CONFIG_INDEX; + c.bmAttributes = 0xc0; + c.bMaxPower = 0x32; + + bytes_remaining -= c.bLength; + memcpy (&fastboot_fifo[0], &c, c.bLength); + bytes_total += c.bLength; + + i.bLength = MIN (bytes_remaining, sizeof(i)); + i.bDescriptorType = USB_DT_INTERFACE; + i.bInterfaceNumber = 0x00; + i.bAlternateSetting = 0x00; + i.bNumEndpoints = 0x02; + i.bInterfaceClass = FASTBOOT_INTERFACE_CLASS; + i.bInterfaceSubClass = FASTBOOT_INTERFACE_SUB_CLASS; + i.bInterfaceProtocol = FASTBOOT_INTERFACE_PROTOCOL; + i.iInterface = DEVICE_STRING_INTERFACE_INDEX; + + bytes_remaining -= i.bLength; + memcpy (&fastboot_fifo[bytes_total], &i, i.bLength); + bytes_total += i.bLength; + + e1.bLength = MIN (bytes_remaining, sizeof (e1)); + e1.bDescriptorType = USB_DT_ENDPOINT; + e1.bEndpointAddress = 0x80 | BULK_ENDPOINT; /* IN */ + e1.bmAttributes = USB_ENDPOINT_XFER_BULK; + if (high_speed) + e1.wMaxPacketSize = TX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0; + else + e1.wMaxPacketSize = TX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1; + e1.bInterval = 0x00; + + bytes_remaining -= e1.bLength; + memcpy (&fastboot_fifo[bytes_total], &e1, e1.bLength); + bytes_total += e1.bLength; + + e2.bLength = MIN (bytes_remaining, sizeof (e2)); + e2.bDescriptorType = USB_DT_ENDPOINT; + e2.bEndpointAddress = BULK_ENDPOINT; /* OUT */ + e2.bmAttributes = USB_ENDPOINT_XFER_BULK; + if (high_speed) + e2.wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0; + else + e2.wMaxPacketSize = RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1; + e2.bInterval = 0x00; + + bytes_remaining -= e2.bLength; + memcpy (&fastboot_fifo[bytes_total], &e2, e2.bLength); + bytes_total += e2.bLength; + + for (byteLoop = 0; byteLoop < bytes_total; byteLoop++) + write_fifo_8 (fastboot_fifo[byteLoop]); + + TX_LAST(); + } + else if (USB_DT_STRING == (req.wValue >> 8)) + { + unsigned char bLength; + unsigned char string_index = req.wValue & 0xff; + + if (string_index > DEVICE_STRING_MAX_INDEX) + { + /* Windows XP asks for an invalid string index. + Fail silently instead of doing + + NAK_REQ(); + */ + } + else if (0 == string_index) + { + /* Language ID */ + bLength = MIN(4, req.wLength); + + fastboot_fifo[0] = bLength; /* length */ + fastboot_fifo[1] = USB_DT_STRING; /* descriptor = string */ + fastboot_fifo[2] = DEVICE_STRING_LANGUAGE_ID & 0xff; + fastboot_fifo[3] = DEVICE_STRING_LANGUAGE_ID >> 8; + + for (byteLoop = 0; byteLoop < bLength; byteLoop++) + write_fifo_8 (fastboot_fifo[byteLoop]); + + TX_LAST(); + } + else + { + /* Size of string in chars */ + unsigned char s; + unsigned char sl = strlen (&device_strings[string_index][0]); + /* Size of descriptor + 1 : header + 2 : type + 2*sl : string */ + unsigned char bLength = 2 + (2 * sl); + bLength = MIN(bLength, req.wLength); + + fastboot_fifo[0] = bLength; /* length */ + fastboot_fifo[1] = USB_DT_STRING; /* descriptor = string */ + + /* Copy device string to fifo, expand to simple unicode */ + for (s = 0; s < sl; s++) + { + fastboot_fifo[2+ 2*s + 0] = device_strings[string_index][s]; + fastboot_fifo[2+ 2*s + 1] = 0; + } + + for (byteLoop = 0; byteLoop < bLength; byteLoop++) + write_fifo_8 (fastboot_fifo[byteLoop]); + + TX_LAST(); + } + } else if (USB_DT_DEVICE_QUALIFIER == (req.wValue >> 8)) { + +#ifdef CONFIG_USB_1_1_DEVICE + /* This is an invalid request for usb 1.1, nak it */ + NAK_REQ(); +#else + struct usb_qualifier_descriptor d; + d.bLength = MIN(req.wLength, sizeof(d)); + d.bDescriptorType = USB_DT_DEVICE_QUALIFIER; + d.bcdUSB = 0x200; + d.bDeviceClass = 0xff; + d.bDeviceSubClass = 0xff; + d.bDeviceProtocol = 0xff; + d.bMaxPacketSize0 = 0x40; + d.bNumConfigurations = 1; + d.bRESERVED = 0; + + memcpy(&fastboot_fifo, &d, d.bLength); + for (byteLoop = 0; byteLoop < d.bLength; byteLoop++) + write_fifo_8(fastboot_fifo[byteLoop]); + + TX_LAST(); +#endif + } + else + { + NAK_REQ(); + } + } + + return ret; +} + +static int do_usb_req_get_status(void) +{ + int ret = FASTBOOT_OK; + + if (0 == req.wLength) + { + ACK_REQ(); + } + else + { + /* See 9.4.5 */ + unsigned int byteLoop; + unsigned char bLength; + + bLength = MIN (req.wValue, 2); + + fastboot_fifo[0] = USB_STATUS_SELFPOWERED; + fastboot_fifo[1] = 0; + + for (byteLoop = 0; byteLoop < bLength; byteLoop++) + write_fifo_8 (fastboot_fifo[byteLoop]); + + TX_LAST(); + } + + return ret; +} + +static int fastboot_poll_h (void) +{ + int ret = FASTBOOT_INACTIVE; + u16 count0; + + if (*csr0 & MUSB_CSR0_RXPKTRDY) + { + count0 = inw (OMAP34XX_USB_COUNT0); + ret = FASTBOOT_OK; + + if (count0 != 8) + { + OMAP3_LED_ERROR_ON (); + CONFUSED(); + ret = FASTBOOT_ERROR; + } + else + { + read_request(); + + /* Check data */ + if (USB_REQ_TYPE_STANDARD == (req.bmRequestType & USB_REQ_TYPE_MASK)) + { + /* standard */ + if (0 == (req.bmRequestType & USB_REQ_DIRECTION_MASK)) + { + /* host-to-device */ + if (USB_RECIP_DEVICE == (req.bmRequestType & USB_REQ_RECIPIENT_MASK)) + { + /* device */ + switch (req.bRequest) + { + case USB_REQ_SET_ADDRESS: + ret = do_usb_req_set_address(); + break; + + case USB_REQ_SET_FEATURE: + ret = do_usb_req_set_feature(); + break; + + case USB_REQ_SET_CONFIGURATION: + ret = do_usb_req_set_configuration(); + break; + + default: + NAK_REQ(); + ret = FASTBOOT_ERROR; + break; + } + } + else if (USB_RECIP_INTERFACE == (req.bmRequestType & USB_REQ_RECIPIENT_MASK)) + { + switch (req.bRequest) + { + case USB_REQ_SET_INTERFACE: + ret = do_usb_req_set_interface(); + break; + + default: + NAK_REQ(); + ret = FASTBOOT_ERROR; + break; + } + } + else + { + NAK_REQ(); + ret = FASTBOOT_ERROR; + } + } + else + { + /* device-to-host */ + if (USB_RECIP_DEVICE == (req.bmRequestType & USB_REQ_RECIPIENT_MASK)) + { + switch (req.bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + ret = do_usb_req_get_descriptor(); + break; + + case USB_REQ_GET_STATUS: + ret = do_usb_req_get_status(); + break; + + default: + NAK_REQ(); + ret = FASTBOOT_ERROR; + break; + } + } + else + { + NAK_REQ(); + ret = FASTBOOT_ERROR; + } + } + } + else + { + /* Non-Standard Req */ + NAK_REQ(); + ret = FASTBOOT_ERROR; + } + } + if (FASTBOOT_OK > ret) + { + printf ("Unhandled req\n"); + PRINT_REQ (req); + } + } + + return ret; +} + +static int fastboot_resume (void) +{ + /* Here because of stall was sent */ + if (*csr0 & MUSB_CSR0_P_SENTSTALL) + { + *csr0 &= ~MUSB_CSR0_P_SENTSTALL; + return FASTBOOT_OK; + } + + /* Host stopped last transaction */ + if (*csr0 & MUSB_CSR0_P_SETUPEND) + { + /* This should be enough .. */ + *csr0 |= MUSB_CSR0_P_SVDSETUPEND; + +#if 0 + if (0xff != faddr) + fastboot_reset (); + + /* Let the cmd layer to reset */ + if (fastboot_interface && + fastboot_interface->reset_handler) + { + fastboot_interface->reset_handler(); + } + + /* If we were not resetting, dropping through and handling the + poll would be fine. As it is returning now is the + right thing to do here. */ + return 0; +#endif + + } + + /* Should we change the address ? */ + if (set_address) + { + outb (faddr, OMAP34XX_USB_FADDR); + set_address = 0; + + /* If you have gotten here you are mostly ok */ + OMAP3_LED_OK_ON(); + } + + return fastboot_poll_h(); +} + +static void fastboot_rx_error(void) +{ + /* Clear the RXPKTRDY bit */ + *peri_rxcsr &= ~MUSB_RXCSR_RXPKTRDY; + + /* Send stall */ + *peri_rxcsr |= MUSB_RXCSR_P_SENDSTALL; + + /* Wait till stall is sent.. */ + while (!(*peri_rxcsr & MUSB_RXCSR_P_SENTSTALL)) + udelay(1); + + /* Clear stall */ + *peri_rxcsr &= ~MUSB_RXCSR_P_SENTSTALL; + +} + +static int fastboot_rx (void) +{ + int ret = FASTBOOT_INACTIVE; + + if (*peri_rxcsr & MUSB_RXCSR_RXPKTRDY) + { + u16 count = *rxcount; + int fifo_size = fastboot_fifo_size(); + ret = FASTBOOT_OK; + + if (0 == *rxcount) { + /* Clear the RXPKTRDY bit */ + *peri_rxcsr &= ~MUSB_RXCSR_RXPKTRDY; + } else if (fifo_size < count) { + fastboot_rx_error(); + } else { + int i = 0; + int err = 1; + + /* + * If the fifo is full, it is likely we are going to + * do a multiple packet transfere. To speed this up + * do a DMA for full packets. To keep the handling + * of the end packet simple, just do it by manually + * reading the fifo + */ + if (fifo_size == count) { + /* Mode 1 + * + * The setup is not as simple as + * *peri_rxcsr |= + * (MUSB_RXCSR_DMAENAB | MUSB_RXCSR_DMAMODE) + * + * There is a special sequence needed to + * enable mode 1. This was take from + * musb_gadget.c in the 2.6.27 kernel + */ + *peri_rxcsr &= ~MUSB_RXCSR_AUTOCLEAR; + *peri_rxcsr |= MUSB_RXCSR_DMAENAB; + *peri_rxcsr |= MUSB_RXCSR_DMAMODE; + *peri_rxcsr |= MUSB_RXCSR_DMAENAB; + + if (read_bulk_fifo_dma + (fastboot_bulk_fifo, fifo_size)) { + /* Failure */ + fastboot_rx_error(); + } + + /* Disable DMA in peri_rxcsr */ + *peri_rxcsr &= ~(MUSB_RXCSR_DMAENAB | + MUSB_RXCSR_DMAMODE); + + } else { + for (i = 0; i < count; i++) + fastboot_bulk_fifo[i] = + read_bulk_fifo_8(); + } + /* Clear the RXPKTRDY bit */ + *peri_rxcsr &= ~MUSB_RXCSR_RXPKTRDY; + + /* Pass this up to the interface's handler */ + if (fastboot_interface && + fastboot_interface->rx_handler) { + if (!fastboot_interface->rx_handler + (&fastboot_bulk_fifo[0], count)) + err = 0; + } + + /* Since the buffer is not null terminated, + * poison the buffer */ + memset(&fastboot_bulk_fifo[0], 0, fifo_size); + + /* If the interface did not handle the command */ + if (err) { + OMAP3_LED_ERROR_ON (); + CONFUSED(); + ret = FASTBOOT_ERROR; + } + } + } + return ret; +} + +static int fastboot_suspend (void) +{ + /* No suspending going on here! + We are polling for all its worth */ + + return FASTBOOT_OK; +} + +int fastboot_poll(void) +{ + /* No activity */ + int ret = FASTBOOT_INACTIVE; + + u8 intrusb; + u16 intrtx; + u16 intrrx; + + if (deferred_rx) + ret = FASTBOOT_OK; + + /* Look at the interrupt registers */ + intrusb = inb (OMAP34XX_USB_INTRUSB); + + /* A disconnect happended, this signals that the cable + has been disconnected, return immediately */ + if (intrusb & OMAP34XX_USB_INTRUSB_DISCON) + return FASTBOOT_DISCONNECT; + + if (intrusb & OMAP34XX_USB_INTRUSB_RESUME) + { + ret = fastboot_resume (); + if (FASTBOOT_OK > ret) + return ret; + } + else + { + if (intrusb & OMAP34XX_USB_INTRUSB_SOF) + { + ret = fastboot_resume (); + if (FASTBOOT_OK > ret) + return ret; + + /* The fastboot client blocks of read and + intrrx is not reliable. + Really poll */ + if (deferred_rx) + ret = fastboot_rx (); + deferred_rx = 0; + if (FASTBOOT_OK > ret) + return ret; + } + if (intrusb & OMAP34XX_USB_INTRUSB_SUSPEND) + { + ret = fastboot_suspend (); + if (FASTBOOT_OK > ret) + return ret; + } + + intrtx = inw (OMAP34XX_USB_INTRTX); + if (intrtx) + { + /* TX interrupts happen when a packet has been sent + We already poll the csr register for this when + something is sent, so do not do it twice + + */ + } + + intrrx = inw (OMAP34XX_USB_INTRRX); + if (intrrx) + { + /* Defer this to SOF */ + deferred_rx = 1; + } + } + + return ret; +} + + + +void fastboot_shutdown(void) +{ + /* Let the cmd layer know that we are shutting down */ + if (fastboot_interface && + fastboot_interface->reset_handler) { + fastboot_interface->reset_handler(); + } + + /* Clear the SOFTCONN bit to disconnect */ + *pwr &= ~MUSB_POWER_SOFTCONN; + + /* Reset some globals */ + faddr = 0xff; + fastboot_interface = NULL; + high_speed = 0; + deferred_rx = 0; + + OMAP3_LED_ERROR_ON (); +} + +int fastboot_is_highspeed(void) +{ + int ret = 0; + if (*pwr & MUSB_POWER_HSMODE) + ret = 1; + return ret; +} + +int fastboot_fifo_size(void) +{ + return high_speed ? RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0 : RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1; +} + +int fastboot_tx_status(const char *buffer, unsigned int buffer_size) +{ + int ret = 1; + unsigned int i; + /* fastboot client only reads back at most 64 */ + unsigned int transfer_size = MIN(64, buffer_size); + + while (*peri_txcsr & MUSB_TXCSR_TXPKTRDY) + udelay(1); + + for (i = 0; i < transfer_size; i++) + write_bulk_fifo_8 (buffer[i]); + + *peri_txcsr |= MUSB_TXCSR_TXPKTRDY; + + while (*peri_txcsr & MUSB_TXCSR_TXPKTRDY) + udelay(1); + + /* Send an empty packet to signal that we are done */ + TX_LAST(); + + ret = 0; + + return ret; +} + +int fastboot_tx(unsigned char *buffer, unsigned int buffer_size) +{ + int ret = 0; + + if (*peri_txcsr & MUSB_TXCSR_TXPKTRDY) { + /* Small delay if fifo is in use */ + udelay(1); + } else { + unsigned int i; + + /* fastboot client only reads back at most 64 */ + unsigned int transfer_size = + MIN(fastboot_fifo_size(), buffer_size); + + for (i = 0; i < transfer_size; i++) + write_bulk_fifo_8(buffer[i]); + + *peri_txcsr |= MUSB_TXCSR_TXPKTRDY; + + ret = transfer_size; + + /* Send an empty packet to signal that we are done */ + TX_LAST(); + } + + return ret; +} + +int fastboot_getvar(const char *rx_buffer, char *tx_buffer) +{ + /* Place board specific variables here */ + return 0; +} + +int fastboot_preboot(void) +{ +#if (defined(CONFIG_TWL4030_KEYPAD) && (CONFIG_TWL4030_KEYPAD)) + int i; + unsigned char key1, key2; + int keys; + udelay(CFG_FASTBOOT_PREBOOT_INITIAL_WAIT); + for (i = 0; i < CFG_FASTBOOT_PREBOOT_LOOP_MAXIMUM; i++) { + key1 = key2 = 0; + keys = twl4030_keypad_keys_pressed(&key1, &key2); + if ((1 == CFG_FASTBOOT_PREBOOT_KEYS) && + (1 == keys)) { + if (CFG_FASTBOOT_PREBOOT_KEY1 == key1) + return 1; + } else if ((2 == CFG_FASTBOOT_PREBOOT_KEYS) && + (2 == keys)) { + if ((CFG_FASTBOOT_PREBOOT_KEY1 == key1) && + (CFG_FASTBOOT_PREBOOT_KEY2 == key2)) + return 1; + } + udelay(CFG_FASTBOOT_PREBOOT_LOOP_WAIT); + } +#endif + return 0; +} + +static void set_serial_number(void) +{ + char *dieid = getenv("dieid#"); + if (dieid == NULL) { + device_strings[DEVICE_STRING_SERIAL_NUMBER_INDEX] = "00123"; + } else { + static char serial_number[32]; + int len; + + memset(&serial_number[0], 0, 32); + len = strlen(dieid); + if (len > 30) + len = 30; + + strncpy(&serial_number[0], dieid, len); + + device_strings[DEVICE_STRING_SERIAL_NUMBER_INDEX] = + &serial_number[0]; + } +} + +int fastboot_init(struct cmd_fastboot_interface *interface) +{ + int ret = 1; + u8 devctl; + + device_strings[DEVICE_STRING_MANUFACTURER_INDEX] = "Texas Instruments"; +#if defined(CONFIG_3630SDP) + device_strings[DEVICE_STRING_PRODUCT_INDEX] = "SDP3630"; +#elif defined(CONFIG_3430ZOOM2) + device_strings[DEVICE_STRING_PRODUCT_INDEX] = "Zoom2"; +#elif defined (CONFIG_3430LABRADOR) + device_strings[DEVICE_STRING_PRODUCT_INDEX] = "Zoom"; +#elif defined (CONFIG_3530OVERO) + device_strings[DEVICE_STRING_PRODUCT_INDEX] = "Overo"; +#else + /* Default, An error message to prompt user */ +#error "Need a product name for fastboot" + +#endif + set_serial_number(); + /* These are just made up */ + device_strings[DEVICE_STRING_CONFIG_INDEX] = "Android Fastboot"; + device_strings[DEVICE_STRING_INTERFACE_INDEX] = "Android Fastboot"; + + /* The interface structure */ + fastboot_interface = interface; + fastboot_interface->product_name = device_strings[DEVICE_STRING_PRODUCT_INDEX]; + fastboot_interface->serial_no = device_strings[DEVICE_STRING_SERIAL_NUMBER_INDEX]; + fastboot_interface->nand_block_size = 2048; + fastboot_interface->nand_oob_size = 64; + fastboot_interface->transfer_buffer = (unsigned char *) CFG_FASTBOOT_TRANSFER_BUFFER; + fastboot_interface->transfer_buffer_size = CFG_FASTBOOT_TRANSFER_BUFFER_SIZE; + + fastboot_reset(); + + /* Check if device is in b-peripheral mode */ + devctl = inb (OMAP34XX_USB_DEVCTL); + if (!(devctl & MUSB_DEVCTL_BDEVICE) || + (devctl & MUSB_DEVCTL_HM)) + { + printf ("ERROR : Unsupport USB mode\n"); + printf ("Check that mini-B USB cable is attached to the device\n"); + } + else + { + ret = 0; + } + return ret; +} + +#endif /* CONFIG_FASTBOOT */ diff --git a/cpu/omap3/interrupts.c b/cpu/omap3/interrupts.c new file mode 100644 index 000000000..25ac6906f --- /dev/null +++ b/cpu/omap3/interrupts.c @@ -0,0 +1,301 @@ +/* + * (C) Copyright 2004 + * Texas Instruments + * Richard Woodruff + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) +# include +#endif + +#include + +#define TIMER_LOAD_VAL 0 + +/* macro to read the 32 bit timer */ +#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR)) + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return(old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_CINTEGRATOR) +/* Use the IntegratorCP function from board/integratorcp.c */ +#else + +static ulong timestamp; +static ulong lastinc; + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init (void) +{ + int32_t val; + + /* Start the counter ticking up */ + *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ + val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ + *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */ + + reset_timer_masked(); /* init the timestamp and lastinc value */ + + return(0); +} +/* + * timer without interrupts + */ +void reset_timer (void) +{ + reset_timer_masked (); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastinc = READ_TIMER; /* capture current incrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (now >= lastinc) /* normal mode (non roll) */ + timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */ + else /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + lastinc = now; + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CFG_HZ; + tmo /= (1000*1000); + } + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + tbclk = CFG_HZ; + return tbclk; +} +#endif /* !Integrator/CP */ diff --git a/cpu/omap3/lowlevel_init.S b/cpu/omap3/lowlevel_init.S new file mode 100644 index 000000000..2fcaf1193 --- /dev/null +++ b/cpu/omap3/lowlevel_init.S @@ -0,0 +1,218 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/* **************************************************************************** + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = CM_CLKEN_PLL-bypass value + * R1 = CM_CLKSEL1_PLL-m, n, and divider values + * R2 = CM_CLKSEL_CORE-divider values + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + * + * Note: If core unlocks/relocks and SDRAM is running fast already it gets + * confused. A reset of the controller gets it back. Taking away its + * L3 when its not in self refresh seems bad for it. Normally, this code + * runs from flash before SDR is init so that should be ok. + ******************************************************************************/ +.global go_to_speed + go_to_speed: + stmfd sp!, {r4-r6} + + /* move into fast relock bypass */ + ldr r4, pll_ctl_add + str r0, [r4] +wait1: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + beq wait1 /* if lock, loop */ + + /* set new dpll dividers _after_ in bypass */ + ldr r5, pll_div_add1 + str r1, [r5] /* set m, n, m2 */ + ldr r5, pll_div_add2 + str r2, [r5] /* set l3/l4/.. dividers*/ + ldr r5, pll_div_add3 /* wkup */ + ldr r2, pll_div_val3 /* rsm val */ + str r2, [r5] + ldr r5, pll_div_add4 /* gfx */ + ldr r2, pll_div_val4 + str r2, [r5] + ldr r5, pll_div_add5 /* emu */ + ldr r2, pll_div_val5 + str r2, [r5] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r5, flash_cfg3_addr + ldr r2, flash_cfg3_val + str r2, [r5] + ldr r5, flash_cfg4_addr + ldr r2, flash_cfg4_val + str r2, [r5] + ldr r5, flash_cfg5_addr + ldr r2, flash_cfg5_val + str r2, [r5] + ldr r5, flash_cfg1_addr + ldr r2, [r5] + orr r2, r2, #0x3 /* up gpmc divider */ + str r2, [r5] + + /* lock DPLL3 and wait a bit */ + orr r0, r0, #0x7 /* set up for lock mode */ + str r0, [r4] /* lock */ + nop /* ARM slow at this point working at sys_clk */ + nop + nop + nop +wait2: + ldr r5, [r3] /* get status */ + and r5, r5, #0x1 /* isolate core status */ + cmp r5, #0x1 /* still locked? */ + bne wait2 /* if lock, loop */ + nop + nop + nop + nop + ldmfd sp!, {r4-r6} + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_div_add1: + .word CM_CLKSEL1_PLL +pll_div_add2: + .word CM_CLKSEL_CORE +pll_div_add3: + .word CM_CLKSEL_WKUP +pll_div_val3: + .word (WKUP_RSM << 1) +pll_div_add4: + .word CM_CLKSEL_GFX +pll_div_val4: + .word (GFX_DIV << 0) +pll_div_add5: + .word CM_CLKSEL1_EMU +pll_div_val5: + .word CLSEL1_EMU_VAL + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + +.globl get_mpu_dpll_param +get_mpu_dpll_param: + adr r0, mpu_dpll_param + mov pc, lr + +.globl get_iva_dpll_param +get_iva_dpll_param: + adr r0, iva_dpll_param + mov pc, lr + + +.globl get_core_dpll_param +get_core_dpll_param: + adr r0, core_dpll_param + mov pc, lr + +.globl get_per_dpll_param +get_per_dpll_param: + adr r0, per_dpll_param + mov pc, lr + + +#if defined(CONFIG_OMAP36XX) +#include +#elif defined(CONFIG_OMAP34XX) +#include +#else +#error "DPLL Table is undefined" +#endif diff --git a/cpu/omap3/mem.c b/cpu/omap3/mem.c new file mode 100644 index 000000000..0522d043d --- /dev/null +++ b/cpu/omap3/mem.c @@ -0,0 +1,611 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/****** DATA STRUCTURES ************/ + +/* Only One NAND allowed on board at a time. + * The GPMC CS Base for the same + */ +unsigned int nand_cs_base = 0; +unsigned int onenand_cs_base = 0; +unsigned int boot_flash_base = 0; +unsigned int boot_flash_off = 0; +unsigned int boot_flash_sec = 0; +volatile unsigned int boot_flash_env_addr = 0; + +/* help common/env_flash.c */ +#ifdef ENV_IS_VARIABLE + +ulong NOR_FLASH_BANKS_LIST[CFG_MAX_FLASH_BANKS]; +int NOR_MAX_FLASH_BANKS = 0 ; /* max number of flash banks */ + +uchar(*boot_env_get_char_spec) (int index); +int (*boot_env_init) (void); +int (*boot_saveenv) (void); +void (*boot_env_relocate_spec) (void); + +/* StrataNor */ +extern uchar flash_env_get_char_spec(int index); +extern int flash_env_init(void); +extern int flash_saveenv(void); +extern void flash_env_relocate_spec(void); +extern char *flash_env_name_spec; + +/* 16 bit NAND */ +extern uchar nand_env_get_char_spec(int index); +extern int nand_env_init(void); +extern int nand_saveenv(void); +extern void nand_env_relocate_spec(void); +extern char *nand_env_name_spec; + +/* OneNAND */ +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) +extern char *onenand_env; +extern uchar onenand_env_get_char_spec(int index); +extern int onenand_env_init(void); +extern int onenand_saveenv(void); +extern void onenand_env_relocate_spec(void); +extern char *onenand_env_name_spec; +#endif + +/* Global fellows */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +u8 is_nand = 0; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) +u8 is_flash = 0; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) +u8 is_onenand = 0; +#endif + +#ifndef CONFIG_STORAGE_EMMC +char *env_name_spec = 0; +env_t *env_ptr = 0; +#endif + +#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH)) +extern env_t *flash_addr; +#endif + +#endif /* ENV_IS_VARIABLE */ + +/* Following CS organization may Different from Board to Board */ +static const unsigned char chip_sel[][GPMC_MAX_CS] = { +#ifdef CONFIG_3630SDP +/* GPMC CS Indices (ON=0, OFF=1)*/ +/* S8-1 2 3 4 IDX CS0, CS1, CS2 .. CS7 */ +/*0 0 0 0*/{PISMO1_NOR, PISMO1_NAND, PISMO1_ONENAND, DBG_MPDB, 0, 0, 0, 0}, +/*0 0 0 1*/{PISMO1_ONENAND, PISMO1_NAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, +/*0 0 1 0*/{PISMO1_NAND, PISMO1_ONENAND, PISMO1_NOR, DBG_MPDB, 0, 0, 0, 0}, +/*0 0 1 1*/{PISMO1_NOR, PISMO2_CS0, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, +/*0 1 0 0*/{PISMO1_ONENAND, PISMO2_CS0, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, +/*0 1 0 1*/{PISMO1_NAND, PISMO2_CS0, PISMO2_CS1, DBG_MPDB, 0, 0, 0, 0}, +/*0 1 1 0*/{PISMO1_NOR, PISMO2_NAND_CS0, PISMO2_NAND_CS1, DBG_MPDB, 0, 0, 0, 0}, +/*0 1 1 1*/ + {PISMO1_ONENAND, PISMO2_NAND_CS0, PISMO2_NAND_CS1, DBG_MPDB, 0, 0, 0, 0} +#else +/*ON OFF ON OFF*/{PISMO1_NAND, 0, 0, 0, 0, 0, 0, 0} +#endif +}; + +/* Values for each of the chips */ +#ifdef CONFIG_3630SDP +static u32 gpmc_mpdb[GPMC_MAX_REG] = { + SDPV2_MPDB_GPMC_CONFIG1, + SDPV2_MPDB_GPMC_CONFIG2, + SDPV2_MPDB_GPMC_CONFIG3, + SDPV2_MPDB_GPMC_CONFIG4, + SDPV2_MPDB_GPMC_CONFIG5, + SDPV2_MPDB_GPMC_CONFIG6, 0 +}; +#else +static u32 gpmc_enet[GPMC_MAX_REG] = { + LAB_ENET_GPMC_CONFIG1, + LAB_ENET_GPMC_CONFIG2, + LAB_ENET_GPMC_CONFIG3, + LAB_ENET_GPMC_CONFIG4, + LAB_ENET_GPMC_CONFIG5, + LAB_ENET_GPMC_CONFIG6, 0 +}; +#endif + +#ifdef CONFIG_3430ZOOM2 +static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { + 0x00011000, + 0x001F1F01, + 0x00080803, + 0x1D091D09, + 0x041D1F1F, + 0x1D0904C4, 0 +}; +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) +static u32 gpmc_sibnor[GPMC_MAX_REG] = { + SIBNOR_GPMC_CONFIG1, + SIBNOR_GPMC_CONFIG2, + SIBNOR_GPMC_CONFIG3, + SIBNOR_GPMC_CONFIG4, + SIBNOR_GPMC_CONFIG5, + SIBNOR_GPMC_CONFIG6, 0 +}; +#endif + +static u32 gpmc_pismo2[GPMC_MAX_REG] = { + P2_GPMC_CONFIG1, + P2_GPMC_CONFIG2, + P2_GPMC_CONFIG3, + P2_GPMC_CONFIG4, + P2_GPMC_CONFIG5, + P2_GPMC_CONFIG6, 0 +}; + +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) +static u32 gpmc_onenand[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, 0 +}; +#endif + +static u32 gpmc_m_nand[GPMC_MAX_REG] = { + M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, 0 +}; + +/********** Functions ****/ + +/* ENV Functions */ +#ifdef ENV_IS_VARIABLE +uchar env_get_char_spec(int index) +{ + if (!boot_env_get_char_spec) { + puts("ERROR!! env_get_char_spec not available\n"); + } else + return boot_env_get_char_spec(index); + return 0; +} +int env_init(void) +{ + if (!boot_env_init) { + puts("ERROR!! boot_env_init not available\n"); + } else + return boot_env_init(); + return -1; +} +int saveenv(void) +{ + if (!boot_saveenv) { + puts("ERROR!! boot_saveenv not available\n"); + } else + return boot_saveenv(); + return -1; +} +void env_relocate_spec(void) +{ + if (!boot_env_relocate_spec) { + puts("ERROR!! boot_env_relocate_spec not available\n"); + } else + boot_env_relocate_spec(); +} +#endif + + +/************************************************************************** + * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow + * command line mem=xyz use all memory with out discontinuous support + * compiled in. Could do it at the ATAG, but there really is two banks... + * Called as part of 2nd phase DDR init. + **************************************************************************/ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(SDRC_CS0_OSET); + size /= SZ_32M; /* find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG); + +} + +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in guessing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(void) +{ + u32 val1, val2, orig1, orig2, addr; + u32 pattern = 0x12345678; + + addr = OMAP34XX_SDRC_CS0; + + orig1 = __raw_readl(addr + 0x400); /* try to save original value */ + orig2 = __raw_readl(addr); + __raw_writel(0x0, addr + 0x400); /* clear pos A */ + __raw_writel(pattern, addr); /* pattern to pos B */ + __raw_writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = __raw_readl(addr + 0x400); /* get pos A value */ + val2 = __raw_readl(addr); /* get val2 */ + + if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed */ + return (0); + else { + /* restore original values and return pass */ + __raw_writel(orig1, addr + 0x400); + __raw_writel(orig2, addr); + return (1); + } +} + +/******************************************************** + * sdrc_init() - init the sdrc chip selects CS0 and CS1 + * - early init routines, called from flash or + * SRAM. + *******************************************************/ +void sdrc_init(void) +{ +#define EARLY_INIT 1 + do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank here */ +} + +/************************************************************************* + * do_sdrc_init(): initialize the SDRAM for use. + * -code sets up SDRAM basic SDRC timings for CS0 + * -optimal settings can be placed here, or redone after i2c + * inspection of board info + * + * - code called ones in C-Stack only context for CS0 and a possible 2nd + * time depending on memory configuration from stack+global context + **************************************************************************/ +void do_sdrc_init(u32 offset, u32 early) +{ + u32 common = 0, cs0 = 0, pmask = 0, pass_type, mtype, mono = 0; + + if (offset == SDRC_CS0_OSET) + cs0 = common = 1; /* int regs shared between both chip select */ + + pass_type = IP_DDR; + + /* If this is a 2nd pass init of a CS1, make it contiguous with CS0 */ + if (!early && (((mtype = get_mem_type()) == DDR_COMBO) + || (mtype == DDR_STACKED))) { + if (mtype == DDR_COMBO) { + pmask = BIT2; /* if shared CKE don't use */ + pass_type = COMBO_DDR; /* CS1 config */ + __raw_writel((__raw_readl(SDRC_POWER)) & ~pmask, + SDRC_POWER); + } + make_cs1_contiguous(); + } + +next_mem_type: + if (common) { /* do a SDRC reset between types to clear regs */ + + /* check if its h/w or s/w reset for warm reset workaround */ + if (__raw_readl(PRM_RSTTST) & 0x2) { + /* Enable SDRC clock & wait SDRC idle status to access*/ + sr32(CM_ICLKEN1_CORE, 1, 1, 0x1); + wait_on_value(BIT1, 0, CM_IDLEST1_CORE, LDELAY); + } else { + /* do a SDRC reset between types to clear regs */ + __raw_writel(SOFTRESET, SDRC_SYSCONFIG);/* reset sdrc */ + /* wait on reset */ + wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000); + __raw_writel(0, SDRC_SYSCONFIG);/* clear soft reset */ + } + /* Clear reset sources */ + __raw_writel(0xfff, PRM_RSTTST); + + __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING); + /* If its a 3430 ES1.0 silicon, configure WAKEUPPROC to 1 as + per Errata 1.22 */ + /* Need to change the condition to silicon and rev check */ + if(1) + __raw_writel((__raw_readl(SDRC_POWER)) | WAKEUPPROC + , SDRC_POWER); +#ifdef POWER_SAVE + __raw_writel(__raw_readl(SMS_SYSCONFIG) | SMART_IDLE, + SMS_SYSCONFIG); + __raw_writel(SDP_SDRC_SHARING | SMART_IDLE, SDRC_SHARING); + __raw_writel((__raw_readl(SDRC_POWER) | BIT6), SDRC_POWER); +#endif + } + + /* set MDCFG_0 values */ + if ((pass_type == IP_DDR) || (pass_type == STACKED)) { + __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0 + offset); + if (mono) /* Stacked with memory on CS1 only */ + __raw_writel(SDP_SDRC_MDCFG_MONO_DDR, SDRC_MCFG_0 + offset); + } else if (pass_type == COMBO_DDR) { /* (combo-CS0/CS1) */ + __raw_writel(SDP_COMBO_MDCFG_0_DDR, SDRC_MCFG_0 + offset); + } else if (pass_type == IP_SDR) { /* ip sdr-CS0 */ + __raw_writel(SDP_SDRC_MDCFG_0_SDR, SDRC_MCFG_0 + offset); + } + + /* Set ACTIM values */ + if (cs0) { + __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0); + __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0); + } else { + __raw_writel(SDP_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_1); + __raw_writel(SDP_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1); + } + __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL_0 + offset); + + /* init sequence for mDDR/mSDR using manual commands (DDR is different) */ + __raw_writel(CMD_NOP, SDRC_MANUAL_0 + offset); + sdelay(5000); /* supposed to be 100us per design spec for mddr/msdr */ + __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0 + offset); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset); + __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0 + offset); + + /* Set MR0 values */ + if (pass_type == IP_SDR) + __raw_writel(SDP_SDRC_MR_0_SDR, SDRC_MR_0 + offset); + else + __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0 + offset); + + /* setup 343x DLL values (DDR only) */ + if (common && (pass_type != IP_SDR)) { + __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL); + sdelay(0x2000); /* give time to lock, at least 1000 L3 */ + } + sdelay(0x1000); + + if (mono) /* Used if Stacked memory is on CS1 only */ + make_cs1_contiguous(); /* make CS1 appear at CS0 */ + + if (mem_ok()) + return; /* STACKED, other configured type */ + ++pass_type; /* IPDDR->COMBODDR->IPSDR for CS0 */ + goto next_mem_type; +} + +void enable_gpmc_config(u32 * gpmc_config, u32 gpmc_base, u32 base, u32 size) +{ + __raw_writel(0, GPMC_CONFIG7 + gpmc_base); + sdelay(1000); + /* Delay for settling */ + __raw_writel(gpmc_config[0], GPMC_CONFIG1 + gpmc_base); + __raw_writel(gpmc_config[1], GPMC_CONFIG2 + gpmc_base); + __raw_writel(gpmc_config[2], GPMC_CONFIG3 + gpmc_base); + __raw_writel(gpmc_config[3], GPMC_CONFIG4 + gpmc_base); + __raw_writel(gpmc_config[4], GPMC_CONFIG5 + gpmc_base); + __raw_writel(gpmc_config[5], GPMC_CONFIG6 + gpmc_base); + /* Enable the config */ + __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), GPMC_CONFIG7 + gpmc_base); + sdelay(2000); +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ +/* putting a blanket check on GPMC based on ZeBu for now */ + u32 mux = 0, mwidth; + u32 *gpmc_config = NULL; + u32 gpmc_base = 0; + u32 base = 0; + u8 idx = 0; + u32 size = 0; + u32 f_off = CFG_MONITOR_LEN; + u32 f_sec = 0; + u32 config = 0; + unsigned char *config_sel = NULL; + u32 i = 0; + + mux = BIT9; + mwidth = get_gpmc0_width(); + + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL); /* timeout disable */ + +#if (!defined(CONFIG_STRASBOURG) && !defined(CONFIG_SANTIAGO)) + config = __raw_readl(GPMC_CONFIG); + config &= (~0xf00); + __raw_writel(config, GPMC_CONFIG); + + /* Disable the GPMC0 config set by ROM code + * It conflicts with our MPDB (both at 0x08000000) + */ + __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0); + sdelay(1000); + +#ifdef CONFIG_3630SDP + gpmc_config = gpmc_mpdb; + /* GPMC3 is always MPDB.. need to know the chip info */ + gpmc_base = GPMC_CONFIG_CS0 + (3 * GPMC_CONFIG_WIDTH); + gpmc_config[0] |= mux; +#elif defined(CONFIG_3430ZOOM2) + /* LAN9221 is on CS 7 on Zoom2 */ + gpmc_config = gpmc_enet; + gpmc_base = GPMC_CONFIG_CS0 + (7 * GPMC_CONFIG_WIDTH); +#else + /* LAN9x18 is on CS 1 on Zoom1 */ + gpmc_config = gpmc_enet; + gpmc_base = GPMC_CONFIG_CS0 + (1 * GPMC_CONFIG_WIDTH); +#endif + enable_gpmc_config(gpmc_config, gpmc_base, DEBUG_BASE, DBG_MPDB_SIZE); + +#ifdef CONFIG_3430ZOOM2 + /* Configure UART4 console support on zoom2 */ + gpmc_config = gpmc_serial_TL16CP754C; + gpmc_base = GPMC_CONFIG_CS0 + (3 * GPMC_CONFIG_WIDTH); + enable_gpmc_config(gpmc_config, + gpmc_base, + SERIAL_TL16CP754C_BASE, + SERIAL_TL16CP754C_SIZE); +#endif + + /* Look up chip select map */ + i = 0; + idx = get_gpmc0_type(); + config_sel = (unsigned char *)(chip_sel[idx]); + /* Initialize each chip selects timings (may be to 0) */ + for (idx = 0; idx < GPMC_MAX_CS; idx++) { + gpmc_base = GPMC_CONFIG_CS0 + (idx * GPMC_CONFIG_WIDTH); + switch (config_sel[idx]) { +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) + case PISMO1_NOR: + gpmc_config = gpmc_sibnor; + f_sec = SZ_256K; + NOR_MAX_FLASH_BANKS = 1; + size = PISMO1_NOR_SIZE_SDPV2; + for (i = 0; i < NOR_MAX_FLASH_BANKS; i++) + NOR_FLASH_BANKS_LIST[i] = + FLASH_BASE_SDPV2 + PHYS_FLASH_SIZE_SDPV2*i; + gpmc_config[0] |= mux | TYPE_NOR | mwidth; + base = NOR_FLASH_BANKS_LIST[0]; + is_flash = 1; + break; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + case PISMO1_NAND: + base = PISMO1_NAND_BASE; + size = PISMO1_NAND_SIZE; + gpmc_config = gpmc_m_nand; + nand_cs_base = gpmc_base; + f_off = SMNAND_ENV_OFFSET; + is_nand = 1; + break; +#endif + case PISMO2_CS0: + case PISMO2_CS1: + base = PISMO2_BASE; + size = PISMO2_SIZE; + gpmc_config = gpmc_pismo2; + gpmc_config[0] |= mux | TYPE_NOR | mwidth; + break; +/* Either OneNand or Normal Nand at a time!! */ +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) + case PISMO1_ONENAND: + base = PISMO1_ONEN_BASE; + size = PISMO1_ONEN_SIZE; + gpmc_config = gpmc_onenand; + onenand_cs_base = gpmc_base; + f_off = ONENAND_ENV_OFFSET; + is_onenand = 1; + break; +#endif + + default: + /* MPDB/Unsupported/Corrupt config- try Next GPMC CS!!!! */ + continue; + } + + /* handle boot CS0 */ + if (idx == 0) { + boot_flash_base = base; + boot_flash_off = f_off; + boot_flash_sec = f_sec; + /* boot_flash_type = config_sel[idx]; */ + boot_flash_env_addr = f_off; +#ifdef ENV_IS_VARIABLE + switch (config_sel[0]) { +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) + case PISMO1_NOR: + boot_env_get_char_spec = flash_env_get_char_spec; + boot_env_init = flash_env_init; + boot_saveenv = flash_saveenv; + boot_env_relocate_spec = flash_env_relocate_spec; + flash_addr = env_ptr = + (env_t *) (boot_flash_base + boot_flash_off); + env_name_spec = flash_env_name_spec; + boot_flash_env_addr = (u32) flash_addr; + break; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + case PISMO1_NAND: + boot_env_get_char_spec = nand_env_get_char_spec; + boot_env_init = nand_env_init; + boot_saveenv = nand_saveenv; + boot_env_relocate_spec = nand_env_relocate_spec; + env_ptr = 0; /* This gets filled elsewhere!! */ + env_name_spec = nand_env_name_spec; + break; +#endif +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) + case PISMO1_ONENAND: + boot_env_get_char_spec = onenand_env_get_char_spec; + boot_env_init = onenand_env_init; + boot_saveenv = onenand_saveenv; + boot_env_relocate_spec = onenand_env_relocate_spec; + env_ptr = (env_t *) onenand_env; + env_name_spec = onenand_env_name_spec; + break; +#endif + default: + /* unknown variant!! */ + puts("Unknown Boot chip!!!\n"); + break; + } +#endif /* ENV_IS_VARIABLE */ + } + enable_gpmc_config(gpmc_config, gpmc_base, base, size); + } + +#ifdef OPTIONAL_NOR + /* CS 2 (fixme -- sizes for optional s-nor)*/ + gpmc_config = gpmc_stnor; + gpmc_config[0] |= mux | TYPE_NOR | mwidth; + gpmc_base = GPMC_CONFIG_CS0 + (2 * GPMC_CONFIG_WIDTH); + enable_gpmc_config(gpmc_config, gpmc_base, DEBUG_BASE, DBG_MPDB_SIZE); + + /* handle flash probe setup */ + f_sec = SZ_128K; + NOR_MAX_FLASH_BANKS = 2; + size = PISMO1_NOR_SIZE; + for(i=0; i < NOR_MAX_FLASH_BANKS; i++) + NOR_FLASH_BANKS_LIST[i] = + FLASH_BASE_SDPV1 + PHYS_FLASH_SIZE*i; + } +#endif +#endif /* CONFIG_STRASBOURG || CONFIG_SANTIAGO */ +} diff --git a/cpu/omap3/mmc.c b/cpu/omap3/mmc.c new file mode 100644 index 000000000..dd0568e7b --- /dev/null +++ b/cpu/omap3/mmc.c @@ -0,0 +1,891 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include + +#if CONFIG_DRIVER_OMAP34XX_I2C /* don't compile for x-loader */ +#include +#endif + +#ifdef CONFIG_MMC +#include "mmc_host_def.h" +#include "mmc_protocol.h" + +#define OMAP_MMC_MASTER_CLOCK 96000000 + +mmc_card_data cur_card_data[2]; +mmc_controller_data cur_controller_data[2]; + +static block_dev_desc_t mmc_blk_dev[2]; + +block_dev_desc_t *mmc_get_dev(int dev) +{ + if ((dev == 0) || (dev == 1)) { + if (cur_card_data[dev].size) + return &mmc_blk_dev[dev]; + } + return NULL; +} + +#if CONFIG_DRIVER_OMAP34XX_I2C /* don't compile for x-loader */ +static void twl4030_mmc_config(unsigned int slot) +{ + unsigned char data; + + /* configure the LDO */ + if (slot == 0) { + data = 0x20; + i2c_write(0x4B, 0x82, 1, &data, 1); + data = 0x2; + i2c_write(0x4B, 0x85, 1, &data, 1); + } else { + data = 0x20; + i2c_write(0x4B, 0x86, 1, &data, 1); +#if (defined(CONFIG_STRASBOURG) && defined(__VARIANT_A1)) + /* Configure for 1.85 V on Strasbourg A1 - + this is what the SoC expects */ + data = 0x6; +#else + data = 0xB; +#endif + i2c_write(0x4B, 0x89, 1, &data, 1); + } +#if (defined(CONFIG_STRASBOURG) && defined(__VARIANT_A2)) + /* Wait 20 ms to let the MoviNand power up */ + udelay(20000); +#endif + + return; +} +#endif + +unsigned char mmc_board_init(mmc_controller_data *mmc_cont_cur) +{ + unsigned char ret = 1; + unsigned int value = 0; + +#if CONFIG_DRIVER_OMAP34XX_I2C /* don't compile for x-loader */ + twl4030_mmc_config(mmc_cont_cur->slot); +#endif + + if (mmc_cont_cur->slot == 0) { + value = CONTROL_PBIAS_LITE; + CONTROL_PBIAS_LITE = value | (1 << 2) | (1 << 1) | (1 << 9); + + value = CONTROL_DEV_CONF0; + CONTROL_DEV_CONF0 = value | (1 << 24); + + } else if (mmc_cont_cur->slot == 1) { + value = CONTROL_DEV_CONF1; + CONTROL_DEV_CONF1 = value | (1 << 6); + value = (*(volatile unsigned int *)CM_FCLKEN1_CORE); + (*(volatile unsigned int *)CM_FCLKEN1_CORE) = value | (1 << 25); + value = (*(volatile unsigned int *)CM_ICLKEN1_CORE); + (*(volatile unsigned int *)CM_ICLKEN1_CORE) = value | (1 << 25); + } + return ret; +} + +void mmc_init_stream(mmc_controller_data *mmc_cont_cur) +{ + OMAP_HSMMC_CON(mmc_cont_cur->base) |= INIT_INITSTREAM; + + OMAP_HSMMC_CMD(mmc_cont_cur->base) = MMC_CMD0; + while (1) { + if ((OMAP_HSMMC_STAT(mmc_cont_cur->base) & CC_MASK)) + break; + } + OMAP_HSMMC_STAT(mmc_cont_cur->base) = CC_MASK; + + OMAP_HSMMC_CMD(mmc_cont_cur->base) = MMC_CMD0; + while (1) { + if ((OMAP_HSMMC_STAT(mmc_cont_cur->base) & CC_MASK)) + break; + } + + OMAP_HSMMC_STAT(mmc_cont_cur->base) = + OMAP_HSMMC_STAT(mmc_cont_cur->base); + OMAP_HSMMC_CON(mmc_cont_cur->base) &= ~INIT_INITSTREAM; +} + +unsigned char mmc_clock_config(mmc_controller_data *mmc_cont_cur, + unsigned int iclk, unsigned short clk_div) +{ + unsigned int val; + + mmc_reg_out(OMAP_HSMMC_SYSCTL(mmc_cont_cur->base), + (ICE_MASK | DTO_MASK | CEN_MASK), + (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + + switch (iclk) { + case CLK_INITSEQ: + val = MMC_INIT_SEQ_CLK / 2; + break; + case CLK_400KHZ: + val = MMC_400kHz_CLK; + break; + case CLK_MISC: + val = clk_div; + break; + default: + return 0; + } + mmc_reg_out(OMAP_HSMMC_SYSCTL(mmc_cont_cur->base), + ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE); + + while (1) { + if ((OMAP_HSMMC_SYSCTL(mmc_cont_cur->base) & ICS_MASK) + != ICS_NOTREADY) + break; + } + + OMAP_HSMMC_SYSCTL(mmc_cont_cur->base) |= CEN_ENABLE; + return 1; +} + +unsigned char mmc_init_setup(mmc_controller_data *mmc_cont_cur) +{ + unsigned int reg_val; + + mmc_board_init(mmc_cont_cur); + + OMAP_HSMMC_SYSCONFIG(mmc_cont_cur->base) |= MMC_SOFTRESET; + while (1) { + if ((OMAP_HSMMC_SYSSTATUS(mmc_cont_cur->base) + & RESETDONE) != 0) + break; + } + + OMAP_HSMMC_SYSCTL(mmc_cont_cur->base) |= SOFTRESETALL; + while ((OMAP_HSMMC_SYSCTL(mmc_cont_cur->base) & SOFTRESETALL) != 0x0) + ; + + OMAP_HSMMC_HCTL(mmc_cont_cur->base) = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0; + OMAP_HSMMC_CAPA(mmc_cont_cur->base) |= VS30_3V0SUP | VS18_1V8SUP; + + reg_val = OMAP_HSMMC_CON(mmc_cont_cur->base) & RESERVED_MASK; + + OMAP_HSMMC_CON(mmc_cont_cur->base) = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | + CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | + STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN; + + mmc_clock_config(mmc_cont_cur, CLK_INITSEQ, 0); + OMAP_HSMMC_HCTL(mmc_cont_cur->base) |= SDBP_PWRON; + + OMAP_HSMMC_IE(mmc_cont_cur->base) = OMAP_HSMMC_STATUS_REQ; + + mmc_init_stream(mmc_cont_cur); + return 1; +} + +unsigned char mmc_send_cmd(unsigned int base, unsigned int cmd, + unsigned int arg, unsigned int *response) +{ + unsigned int mmc_stat; + unsigned int cmd_index = cmd >> 24; + + while ((OMAP_HSMMC_PSTATE(base) & DATI_MASK) == DATI_CMDDIS) + ; + + OMAP_HSMMC_STAT(base) = 0xFFFFFFFF; + OMAP_HSMMC_ARG(base) = arg; + + if (cmd_index == 0x19) { /* CMD25: Multi block write */ + OMAP_HSMMC_CMD(base) = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | + CCCE_NOCHECK | MSBS | BCE | ACEN_DISABLE | DE_DISABLE; + } else { + OMAP_HSMMC_BLK(base) = BLEN_512BYTESLEN | NBLK_STPCNT; + OMAP_HSMMC_CMD(base) = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | + CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | + BCE_DISABLE | DE_DISABLE; + } + + while (1) { + do { + mmc_stat = OMAP_HSMMC_STAT(base); + } while (mmc_stat == 0); + + if ((mmc_stat & ERRI_MASK) != 0) + return (unsigned char)mmc_stat; + + + if (mmc_stat & CC_MASK) { + OMAP_HSMMC_STAT(base) = CC_MASK; + response[0] = OMAP_HSMMC_RSP10(base); + if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) { + response[1] = OMAP_HSMMC_RSP32(base); + response[2] = OMAP_HSMMC_RSP54(base); + response[3] = OMAP_HSMMC_RSP76(base); + } + break; + } + } + return 1; +} + +unsigned char mmc_read_data(unsigned int base, unsigned int *output_buf) +{ + unsigned int mmc_stat; + unsigned int read_count = 0; + + /* + * Start Polled Read + */ + while (1) { + do { + mmc_stat = OMAP_HSMMC_STAT(base); + } while (mmc_stat == 0); + + if ((mmc_stat & ERRI_MASK) != 0) + return (unsigned char)mmc_stat; + + if (mmc_stat & BRR_MASK) { + unsigned int k; + + OMAP_HSMMC_STAT(base) |= BRR_MASK; + for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) { + *output_buf = OMAP_HSMMC_DATA(base); + output_buf++; + read_count += 4; + } + } + + if (mmc_stat & BWR_MASK) + OMAP_HSMMC_STAT(base) |= BWR_MASK; + + if (mmc_stat & TC_MASK) { + OMAP_HSMMC_STAT(base) |= TC_MASK; + break; + } + } + return 1; +} + +unsigned char mmc_write_data(unsigned int base, unsigned int *input_buf) +{ + unsigned int mmc_stat; + + return 0; + + /* + * Start Polled Write + */ + while (1) { + do { + mmc_stat = OMAP_HSMMC_STAT(base); + } while (mmc_stat == 0); + + if ((mmc_stat & ERRI_MASK) != 0) + return (unsigned char)mmc_stat; + + if (mmc_stat & BWR_MASK) { + unsigned int k; + + OMAP_HSMMC_STAT(base) |= BWR_MASK; + for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) { + OMAP_HSMMC_DATA(base) = *input_buf; + input_buf++; + } + } + + if (mmc_stat & BRR_MASK) + OMAP_HSMMC_STAT(base) |= BRR_MASK; + + if (mmc_stat & TC_MASK) { + OMAP_HSMMC_STAT(base) |= TC_MASK; + break; + } + } + return 1; +} + +unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur, + mmc_controller_data *mmc_contr_cur) +{ + unsigned char err; + unsigned int argument = 0; + unsigned int ocr_value = 0; + unsigned int ocr_recvd = 0; + unsigned int ret_cmd41 = 0; + unsigned int hcs_val = 0; + unsigned int resp[4]; + unsigned short retry_cnt = 2000; + + /* Set to Initialization Clock */ + err = mmc_clock_config(mmc_contr_cur, CLK_400KHZ, 0); + if (err != 1) + return err; + + mmc_card_cur->RCA = MMC_RELATIVE_CARD_ADDRESS; + argument = 0x00000000; + + switch (mmc_contr_cur->slot) { + case 0: + ocr_value = (0x1FF << 15); + break; + case 1: + ocr_value = 0x80; + break; + default: + printf("mmc_detect_card:Invalid Slot\n"); + } + err = mmc_send_cmd(mmc_contr_cur->base, MMC_CMD0, argument, resp); + if (err != 1) + return err; + + argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE; + err = mmc_send_cmd(mmc_contr_cur->base, MMC_SDCMD8, argument, resp); + hcs_val = (err == 1) ? + MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR : + MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE; + + argument = 0x0000 << 16; + err = mmc_send_cmd(mmc_contr_cur->base, MMC_CMD55, argument, resp); + if (err == 1) { + mmc_card_cur->card_type = SD_CARD; + ocr_value |= hcs_val; + ret_cmd41 = MMC_ACMD41; + } else { + mmc_card_cur->card_type = MMC_CARD; + ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR; + ret_cmd41 = MMC_CMD1; + OMAP_HSMMC_CON(mmc_contr_cur->base) &= ~OD; + OMAP_HSMMC_CON(mmc_contr_cur->base) |= OPENDRAIN; + } + + argument = ocr_value; + err = mmc_send_cmd(mmc_contr_cur->base, ret_cmd41, argument, resp); + if (err != 1) + return err; + + ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; + + while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) { + retry_cnt--; + if (mmc_card_cur->card_type == SD_CARD) { + argument = 0x0000 << 16; + err = mmc_send_cmd(mmc_contr_cur->base, MMC_CMD55, + argument, resp); + } + + argument = ocr_value; + err = mmc_send_cmd(mmc_contr_cur->base, ret_cmd41, + argument, resp); + if (err != 1) + return err; + ocr_recvd = ((mmc_resp_r3 *) resp)->ocr; + } + + if (!(ocr_recvd & (0x1 << 31))) + return 0; + + if (mmc_card_cur->card_type == MMC_CARD) { + if ((ocr_recvd & MMC_OCR_REG_ACCESS_MODE_MASK) == + MMC_OCR_REG_ACCESS_MODE_SECTOR) { + mmc_card_cur->mode = SECTOR_MODE; + } else { + mmc_card_cur->mode = BYTE_MODE; + } + + ocr_recvd &= ~MMC_OCR_REG_ACCESS_MODE_MASK; + } else { + if ((ocr_recvd & MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK) + == MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR) { + mmc_card_cur->mode = SECTOR_MODE; + } else { + mmc_card_cur->mode = BYTE_MODE; + } + ocr_recvd &= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK; + } + + ocr_recvd &= ~(0x1 << 31); + if (!(ocr_recvd & ocr_value)) + return 0; + + err = mmc_send_cmd(mmc_contr_cur->base, MMC_CMD2, argument, resp); + if (err != 1) + return err; + + if (mmc_card_cur->card_type == MMC_CARD) { + argument = mmc_card_cur->RCA << 16; + err = mmc_send_cmd(mmc_contr_cur->base, MMC_CMD3, + argument, resp); + if (err != 1) + return err; + } else { + argument = 0x00000000; + err = mmc_send_cmd(mmc_contr_cur->base, MMC_SDCMD3, + argument, resp); + if (err != 1) + return err; + + mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca; + } + + OMAP_HSMMC_CON(mmc_contr_cur->base) &= ~OD; + OMAP_HSMMC_CON(mmc_contr_cur->base) |= NOOPENDRAIN; + return 1; +} + +unsigned char mmc_read_cardsize(unsigned int base, mmc_card_data *mmc_dev_data, + mmc_csd_reg_t *cur_csd) +{ + mmc_extended_csd_reg_t ext_csd; + unsigned int size, count, blk_len, blk_no, card_size, argument; + unsigned char err; + unsigned int resp[4]; + + if (mmc_dev_data->mode == SECTOR_MODE) { + if (mmc_dev_data->card_type == SD_CARD) { + card_size = + (((mmc_sd2_csd_reg_t *) cur_csd)-> + c_size_lsb & MMC_SD2_CSD_C_SIZE_LSB_MASK) | + ((((mmc_sd2_csd_reg_t *) cur_csd)-> + c_size_msb & MMC_SD2_CSD_C_SIZE_MSB_MASK) + << MMC_SD2_CSD_C_SIZE_MSB_OFFSET); + mmc_dev_data->size = card_size * 1024; + if (mmc_dev_data->size == 0) + return 0; + } else { + argument = 0x00000000; + err = mmc_send_cmd(base, MMC_CMD8, argument, resp); + if (err != 1) + return err; + err = mmc_read_data(base, (unsigned int *)&ext_csd); + if (err != 1) + return err; + mmc_dev_data->size = ext_csd.sectorcount; + + if (mmc_dev_data->size == 0) + mmc_dev_data->size = 8388608; + } + } else { + if (cur_csd->c_size_mult >= 8) + return 0; + + if (cur_csd->read_bl_len >= 12) + return 0; + + /* Compute size */ + count = 1 << (cur_csd->c_size_mult + 2); + card_size = (cur_csd->c_size_lsb & MMC_CSD_C_SIZE_LSB_MASK) | + ((cur_csd->c_size_msb & MMC_CSD_C_SIZE_MSB_MASK) + << MMC_CSD_C_SIZE_MSB_OFFSET); + blk_no = (card_size + 1) * count; + blk_len = 1 << cur_csd->read_bl_len; + size = blk_no * blk_len; + mmc_dev_data->size = size / MMCSD_SECTOR_SIZE; + if (mmc_dev_data->size == 0) + return 0; + } + return 1; +} + +unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes, + mmc_controller_data *mmc_cont_cur, + mmc_card_data *mmc_c, unsigned int *output_buf) +{ + unsigned char err; + unsigned int argument; + unsigned int resp[4]; + unsigned int num_sec_val = + (num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE; + unsigned int sec_inc_val; + + if (num_sec_val == 0) { + return 1; + } + if (mmc_c->mode == SECTOR_MODE) { + argument = start_sec; + sec_inc_val = 1; + } else { + argument = start_sec * MMCSD_SECTOR_SIZE; + sec_inc_val = MMCSD_SECTOR_SIZE; + } + while (num_sec_val) { + err = mmc_send_cmd(mmc_cont_cur->base, MMC_CMD17, + argument, resp); + if (err != 1) + return err; + + + err = mmc_read_data(mmc_cont_cur->base, output_buf); + if (err != 1) + return err; + + output_buf += (MMCSD_SECTOR_SIZE / 4); + argument += sec_inc_val; + num_sec_val--; + } + return 1; +} + +unsigned char omap_mmc_write_sect(unsigned int *input_buf, + unsigned int num_bytes, + mmc_controller_data *mmc_cont_cur, + mmc_card_data *mmc_c, unsigned long start_sec) +{ + unsigned char err; + unsigned int argument; + unsigned int resp[4]; + unsigned int num_sec_val = + (num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE; + unsigned int sec_inc_val; + unsigned int blk_cnt_current_tns; + + if (num_sec_val == 0) { + printf("mmc write: Invalid size\n"); + return 1; + } + + if (mmc_c->mode == SECTOR_MODE) { + argument = start_sec; + sec_inc_val = 1; + } else { + argument = start_sec * MMCSD_SECTOR_SIZE; + sec_inc_val = MMCSD_SECTOR_SIZE; + } + while (num_sec_val) { + if (num_sec_val > 0xFFFF) + /* Max number of blocks per cmd */ + blk_cnt_current_tns = 0xFFFF; + else + blk_cnt_current_tns = num_sec_val; + + /* check for Multi Block */ + if (blk_cnt_current_tns > 1) { + err = mmc_send_cmd(mmc_cont_cur->base, MMC_CMD23, + blk_cnt_current_tns, resp); + if (err != 1) + return err; + + OMAP_HSMMC_BLK(mmc_cont_cur->base) = BLEN_512BYTESLEN | + (blk_cnt_current_tns << 16); + + err = mmc_send_cmd(mmc_cont_cur->base, + MMC_CMD25, argument, resp); + if (err != 1) + return err; + } else { + err = mmc_send_cmd(mmc_cont_cur->base, MMC_CMD24, + argument, resp); + if (err != 1) + return err; + } + + err = mmc_write_data(mmc_cont_cur->base, input_buf); + if (err != 1) + return err; + + input_buf += (MMCSD_SECTOR_SIZE / 4) * blk_cnt_current_tns; + argument += sec_inc_val * blk_cnt_current_tns; + num_sec_val -= blk_cnt_current_tns; + + } + return 1; + } + +unsigned char omap_mmc_erase_sect(unsigned int start, + mmc_controller_data *mmc_cont_cur, mmc_card_data *mmc_c, int size) +{ + unsigned char err; + unsigned int argument; + unsigned int num_sec_val; + unsigned int sec_inc_val; + unsigned int resp[4]; + unsigned int mmc_stat; + unsigned int blk_cnt_current_tns; + + if ((start / MMCSD_SECTOR_SIZE) > mmc_c->size || + ((start + size) / MMCSD_SECTOR_SIZE) > mmc_c->size) { + printf("mmc erase: erase to Sector is\n" + "out of card range\n"); + return 1; + } + num_sec_val = (size + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE; + if (mmc_c->mode == SECTOR_MODE) { + argument = start; + sec_inc_val = 1; + } else { + argument = start * MMCSD_SECTOR_SIZE; + sec_inc_val = MMCSD_SECTOR_SIZE; + } + while (num_sec_val) { + if (num_sec_val > 0xFFFF) + blk_cnt_current_tns = 0xFFFF; + else + blk_cnt_current_tns = num_sec_val; + + /* check for Multi Block */ + if (blk_cnt_current_tns > 1) { + err = mmc_send_cmd(mmc_cont_cur->base, MMC_CMD23, + blk_cnt_current_tns, resp); + if (err != 1) + return err; + + OMAP_HSMMC_BLK(mmc_cont_cur->base) = BLEN_512BYTESLEN | + (blk_cnt_current_tns << 16); + + err = mmc_send_cmd(mmc_cont_cur->base, + MMC_CMD25, argument, resp); + if (err != 1) + return err; + + } else { + err = mmc_send_cmd(mmc_cont_cur->base, MMC_CMD24, + argument, resp); + if (err != 1) + return err; + } + + while (1) { + do { + mmc_stat = OMAP_HSMMC_STAT(mmc_cont_cur->base); + } while (mmc_stat == 0); + + if ((mmc_stat & ERRI_MASK) != 0) + return (unsigned char)mmc_stat; + + if (mmc_stat & BWR_MASK) { + unsigned int k; + + OMAP_HSMMC_STAT(mmc_cont_cur->base) |= BWR_MASK; + for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) { + OMAP_HSMMC_DATA(mmc_cont_cur->base) = + 0XFFFFFFFF; + } + } + + if (mmc_stat & BRR_MASK) + OMAP_HSMMC_STAT(mmc_cont_cur->base) |= BRR_MASK; + + if (mmc_stat & TC_MASK) { + OMAP_HSMMC_STAT(mmc_cont_cur->base) |= TC_MASK; + break; + } + } + argument += sec_inc_val * blk_cnt_current_tns; + num_sec_val -= blk_cnt_current_tns; + + } + return 1; +} + + +unsigned char configure_controller(mmc_controller_data *cur_controller_data, + int slot) +{ + int ret = 0; + + cur_controller_data->slot = slot; + switch (slot) { + case 0: + cur_controller_data->base = OMAP_HSMMC1_BASE; + break; + case 1: + cur_controller_data->base = OMAP_HSMMC2_BASE; + break; + default: + printf("MMC on SLOT=%d not Supported\n", slot); + ret = 1; + } + return ret; +} + +unsigned char configure_mmc(mmc_card_data *mmc_card_cur, + mmc_controller_data *mmc_cont_cur) +{ + unsigned char ret_val; + unsigned int argument; + unsigned int resp[4]; + unsigned int trans_fact, trans_unit, retries = 2; + unsigned int max_dtr; + int dsor; + mmc_csd_reg_t Card_CSD; + unsigned char trans_speed; + + ret_val = mmc_init_setup(mmc_cont_cur); + if (ret_val != 1) + return ret_val; + + + do { + ret_val = mmc_detect_card(mmc_card_cur, mmc_cont_cur); + retries--; + } while ((retries > 0) && (ret_val != 1)); + + argument = mmc_card_cur->RCA << 16; + ret_val = mmc_send_cmd(mmc_cont_cur->base, MMC_CMD9, argument, resp); + if (ret_val != 1) + return ret_val; + + ((unsigned int *)&Card_CSD)[3] = resp[3]; + ((unsigned int *)&Card_CSD)[2] = resp[2]; + ((unsigned int *)&Card_CSD)[1] = resp[1]; + ((unsigned int *)&Card_CSD)[0] = resp[0]; + + if (mmc_card_cur->card_type == MMC_CARD) + mmc_card_cur->version = Card_CSD.spec_vers; + + trans_speed = Card_CSD.tran_speed; + ret_val = mmc_send_cmd(mmc_cont_cur->base, MMC_CMD4, + MMC_DSR_DEFAULT << 16, resp); + if (ret_val != 1) + return ret_val; + + trans_unit = trans_speed & MMC_CSD_TRAN_SPEED_UNIT_MASK; + trans_fact = trans_speed & MMC_CSD_TRAN_SPEED_FACTOR_MASK; + + if (trans_unit > MMC_CSD_TRAN_SPEED_UNIT_100MHZ) + return 0; + + if ((trans_fact < MMC_CSD_TRAN_SPEED_FACTOR_1_0) || + (trans_fact > MMC_CSD_TRAN_SPEED_FACTOR_8_0)) + return 0; + + trans_unit >>= 0; + trans_fact >>= 3; + + max_dtr = tran_exp[trans_unit] * tran_mant[trans_fact]; + dsor = OMAP_MMC_MASTER_CLOCK / max_dtr; + +/* Following lines commented to build in x-loader; otherwise its including + * division library and creating a linking error. + if (OMAP_MMC_MASTER_CLOCK / dsor > max_dtr) + dsor++; +*/ + if (dsor == 4) + dsor = 5; + else if (dsor == 3) + dsor = 4; + else + return 1; + + ret_val = mmc_clock_config(mmc_cont_cur, CLK_MISC, dsor); + if (ret_val != 1) + return ret_val; + + argument = mmc_card_cur->RCA << 16; + ret_val = mmc_send_cmd(mmc_cont_cur->base, MMC_CMD7_SELECT, + argument, resp); + if (ret_val != 1) + return ret_val; + + /* Configure the block length to 512 bytes */ + argument = MMCSD_SECTOR_SIZE; + ret_val = mmc_send_cmd(mmc_cont_cur->base, MMC_CMD16, argument, resp); + if (ret_val != 1) + return ret_val; + + /* get the card size in sectors */ + ret_val = mmc_read_cardsize(mmc_cont_cur->base, + mmc_card_cur, &Card_CSD); + if (ret_val != 1) + return ret_val; + + return 1; + } + +unsigned long mmc_bread(int dev_num, ulong blknr, ulong blkcnt, ulong *dst) +{ + unsigned long ret; + + ret = (unsigned long)omap_mmc_read_sect(blknr, + (blkcnt * MMCSD_SECTOR_SIZE), + &cur_controller_data[dev_num], &cur_card_data[dev_num], + (unsigned int *)dst); + return ret ? blkcnt : 0; + } + +int mmc_init(int slot) +{ + switch (slot) { + case 0: + configure_controller(&cur_controller_data[slot], slot); + configure_mmc(&cur_card_data[slot], &cur_controller_data[slot]); + mmc_blk_dev[slot].if_type = IF_TYPE_MMC; + mmc_blk_dev[slot].part_type = PART_TYPE_DOS; + mmc_blk_dev[slot].dev = cur_controller_data[slot].slot; + mmc_blk_dev[slot].lun = 0; + mmc_blk_dev[slot].type = 0; + + /* FIXME fill in the correct size (is set to 32MByte) */ + mmc_blk_dev[slot].blksz = MMCSD_SECTOR_SIZE; + mmc_blk_dev[slot].lba = 0x10000; + mmc_blk_dev[slot].removable = 0; + mmc_blk_dev[slot].block_read = mmc_bread; + if (fat_register_device(&mmc_blk_dev[slot], 1)) + return -1; + break; + case 1: + configure_controller(&cur_controller_data[slot], slot); + configure_mmc(&cur_card_data[slot], &cur_controller_data[slot]); + mmc_blk_dev[slot].if_type = IF_TYPE_MMC; + mmc_blk_dev[slot].part_type = PART_TYPE_DOS; + mmc_blk_dev[slot].dev = cur_controller_data[slot].slot; + mmc_blk_dev[slot].lun = 0; + mmc_blk_dev[slot].type = 0; + + /* FIXME fill in the correct size (is set to 32MByte) */ + mmc_blk_dev[slot].blksz = MMCSD_SECTOR_SIZE; + mmc_blk_dev[slot].lba = 0x10000; + mmc_blk_dev[slot].removable = 0; + mmc_blk_dev[slot].block_read = mmc_bread; + if (fat_register_device(&mmc_blk_dev[slot], 1)) + return -1; + break; + default: + printf("mmc_init:mmc slot is not supported%d\n", slot); +} + return 0; + } + +int mmc_read(int mmc_cont, unsigned int src, unsigned char *dst, int size) +{ + int ret; + + ret = omap_mmc_read_sect(src, size, &cur_controller_data[mmc_cont], + &cur_card_data[mmc_cont], (unsigned int *)dst); + return ret; + } +int mmc_write(int mmc_cont, unsigned char *src, unsigned long dst, int size) +{ + int ret; + + ret = omap_mmc_write_sect((unsigned int *)src, size, + &cur_controller_data[mmc_cont], &cur_card_data[mmc_cont], dst); + return ret; +} + +int mmc_erase(int mmc_cont, unsigned int start, int size) +{ + int ret; + + ret = omap_mmc_erase_sect(start, &cur_controller_data[mmc_cont], + &cur_card_data[mmc_cont], size); + return ret; +} +#endif diff --git a/cpu/omap3/mmc_host_def.h b/cpu/omap3/mmc_host_def.h new file mode 100644 index 000000000..06959ddcd --- /dev/null +++ b/cpu/omap3/mmc_host_def.h @@ -0,0 +1,185 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_HOST_DEFINITIONS_H +#define MMC_HOST_DEFINITIONS_H + +/* + * OMAP HSMMC register definitions + */ +#define OMAP_HSMMC1_BASE 0x4809C000 +#define OMAP_HSMMC2_BASE 0x480B4000 + +#define OMAP_HSMMC_SYSCONFIG(base) (*(volatile unsigned int *)(base+0x010)) +#define OMAP_HSMMC_SYSSTATUS(base) (*(volatile unsigned int *)(base+0x014)) +#define OMAP_HSMMC_CON(base) (*(volatile unsigned int *)(base+0x02C)) +#define OMAP_HSMMC_BLK(base) (*(volatile unsigned int *)(base+0x104)) +#define OMAP_HSMMC_ARG(base) (*(volatile unsigned int *)(base+0x108)) +#define OMAP_HSMMC_CMD(base) (*(volatile unsigned int *)(base+0x10C)) +#define OMAP_HSMMC_RSP10(base) (*(volatile unsigned int *)(base+0x110)) +#define OMAP_HSMMC_RSP32(base) (*(volatile unsigned int *)(base+0x114)) +#define OMAP_HSMMC_RSP54(base) (*(volatile unsigned int *)(base+0x118)) +#define OMAP_HSMMC_RSP76(base) (*(volatile unsigned int *)(base+0x11C)) +#define OMAP_HSMMC_DATA(base) (*(volatile unsigned int *)(base+0x120)) +#define OMAP_HSMMC_PSTATE(base) (*(volatile unsigned int *)(base+0x124)) +#define OMAP_HSMMC_HCTL(base) (*(volatile unsigned int *)(base+0x128)) +#define OMAP_HSMMC_SYSCTL(base) (*(volatile unsigned int *)(base+0x12C)) +#define OMAP_HSMMC_STAT(base) (*(volatile unsigned int *)(base+0x130)) +#define OMAP_HSMMC_IE(base) (*(volatile unsigned int *)(base+0x134)) +#define OMAP_HSMMC_CAPA(base) (*(volatile unsigned int *)(base+0x140)) + +/* T2 Register definitions */ +#define CONTROL_DEV_CONF0 (*(volatile unsigned int *) 0x48002274) +#define CONTROL_DEV_CONF1 (*(volatile unsigned int *) 0x480022D8) +#define CONTROL_PBIAS_LITE (*(volatile unsigned int *) 0x48002520) +/* Configuration Header: (TOC filename offset; e.g. "CHSETTINGS") + * 12 character long name of sub image, including the zero (.\0.) terminator + */ +#define TOC_NAME_OFFSET 0x14 + +/* + * OMAP HS MMC Bit definitions + */ +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_DISABLE (0x0 << 0) +#define BCE_DISABLE (0x0 << 1) +#define ACEN_DISABLE (0x0 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define MSBS (0x1 << 5) +#define BCE (0x1 << 1) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define DATI_CMDDIS (0x1 << 1) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_DISABLE (0x0 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS30_3V0SUP (1 << 25) +#define VS18_1V8SUP (1 << 26) + +/* Interrupt MMC/SD enable register; Set the value to the register that allows + to get the status bits, on an event-by-event basis + */ +#define OMAP_HSMMC_STATUS_REQ 0x307f0033 + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE (512) +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +typedef struct { + unsigned int card_type; + unsigned int version; + unsigned int mode; + unsigned int size; + unsigned int RCA; +} mmc_card_data; + +typedef struct { + unsigned int slot; + unsigned int base; + } mmc_controller_data; + +#define mmc_reg_out(addr, mask, val) \ + (addr) = (((addr)) & (~(mask)) ) | ( (val) & (mask)); + +#endif /* MMC_HOST_DEFINITIONS_H */ + diff --git a/cpu/omap3/mmc_protocol.h b/cpu/omap3/mmc_protocol.h new file mode 100644 index 000000000..f31d2cf4a --- /dev/null +++ b/cpu/omap3/mmc_protocol.h @@ -0,0 +1,248 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_PROTOCOL_H +#define MMC_PROTOCOL_H + +#include "mmc_host_def.h" + +/* Responses */ +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) +#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) + +/* All supported commands */ +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD7_DESELECT \ + (INDEX(7) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) +#define MMC_CMD23 (INDEX(23) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD25 (INDEX(25) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) +#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) +#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) + +#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) +#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) +#define MMC_DSR_DEFAULT (0x0404) +#define SD_CMD8_CHECK_PATTERN (0xAA) +#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) + +/* Clock Configurations and Macros */ + +#define MMC_CLOCK_REFERENCE (96) +#define MMC_RELATIVE_CARD_ADDRESS (0x1234) +#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) +#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) +#define CLKDR(r, f, u) ( ( ((r)*100) / ((f)*(u)) ) + 1 ) +#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) + +#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) +#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) +#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) + +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) + +#define MMC_SD2_CSD_C_SIZE_LSB_MASK (0xFFFF) +#define MMC_SD2_CSD_C_SIZE_MSB_MASK (0x003F) +#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET (16) +#define MMC_CSD_C_SIZE_LSB_MASK (0x0003) +#define MMC_CSD_C_SIZE_MSB_MASK (0x03FF) +#define MMC_CSD_C_SIZE_MSB_OFFSET (2) + +#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) +#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) +#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) +#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) +#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) + +static const unsigned int tran_exp[] = { + 10000, 100000, 1000000, 10000000, + 0, 0, 0, 0 +}; + +static const unsigned char tran_mant[] = { + 0, 10, 12, 13, 15, 20, 25, 30, + 35, 40, 45, 50, 55, 60, 70, 80, +}; + +typedef struct { + unsigned not_used:1; + unsigned crc:7; + unsigned ecc:2; + unsigned file_format:2; + unsigned tmp_write_protect:1; + unsigned perm_write_protect:1; + unsigned copy:1; + unsigned file_format_grp:1; + unsigned content_prot_app:1; + unsigned reserved_1:4; + unsigned write_bl_partial:1; + unsigned write_bl_len:4; + unsigned r2w_factor:3; + unsigned default_ecc:2; + unsigned wp_grp_enable:1; + unsigned wp_grp_size:5; + unsigned erase_grp_mult:5; + unsigned erase_grp_size:5; + unsigned c_size_mult:3; + unsigned vdd_w_curr_max:3; + unsigned vdd_w_curr_min:3; + unsigned vdd_r_curr_max:3; + unsigned vdd_r_curr_min:3; + unsigned c_size_lsb:2; + unsigned c_size_msb:10; + unsigned reserved_2:2; + unsigned dsr_imp:1; + unsigned read_blk_misalign:1; + unsigned write_blk_misalign:1; + unsigned read_bl_partial:1; + unsigned read_bl_len:4; + unsigned ccc:12; + unsigned tran_speed:8; + unsigned nsac:8; + unsigned taac:8; + unsigned reserved_3:2; + unsigned spec_vers:4; + unsigned csd_structure:2; +} mmc_csd_reg_t; + +/* csd for sd2.0 */ +typedef struct { + unsigned not_used:1; + unsigned crc:7; + unsigned reserved_1:2; + unsigned file_format:2; + unsigned tmp_write_protect:1; + unsigned perm_write_protect:1; + unsigned copy:1; + unsigned file_format_grp:1; + unsigned reserved_2:5; + unsigned write_bl_partial:1; + unsigned write_bl_len:4; + unsigned r2w_factor:3; + unsigned reserved_3:2; + unsigned wp_grp_enable:1; + unsigned wp_grp_size:7; + unsigned sector_size:7; + unsigned erase_blk_len:1; + unsigned reserved_4:1; + unsigned c_size_lsb:16; + unsigned c_size_msb:6; + unsigned reserved_5:6; + unsigned dsr_imp:1; + unsigned read_blk_misalign:1; + unsigned write_blk_misalign:1; + unsigned read_bl_partial:1; + unsigned read_bl_len:4; + unsigned ccc:12; + unsigned tran_speed:8; + unsigned nsac:8; + unsigned taac:8; + unsigned reserved_6:6; + unsigned csd_structure:2; +} mmc_sd2_csd_reg_t; + +/* extended csd - 512 bytes long */ +typedef struct { + unsigned char reserved_1[181]; + unsigned char erasedmemorycontent; + unsigned char reserved_2; + unsigned char buswidthmode; + unsigned char reserved_3; + unsigned char highspeedinterfacetiming; + unsigned char reserved_4; + unsigned char powerclass; + unsigned char reserved_5; + unsigned char commandsetrevision; + unsigned char reserved_6; + unsigned char commandset; + unsigned char extendedcsdrevision; + unsigned char reserved_7; + unsigned char csdstructureversion; + unsigned char reserved_8; + unsigned char cardtype; + unsigned char reserved_9[3]; + unsigned char powerclass_52mhz_1_95v; + unsigned char powerclass_26mhz_1_95v; + unsigned char powerclass_52mhz_3_6v; + unsigned char powerclass_26mhz_3_6v; + unsigned char reserved_10; + unsigned char minreadperf_4b_26mhz; + unsigned char minwriteperf_4b_26mhz; + unsigned char minreadperf_8b_26mhz_4b_52mhz; + unsigned char minwriteperf_8b_26mhz_4b_52mhz; + unsigned char minreadperf_8b_52mhz; + unsigned char minwriteperf_8b_52mhz; + unsigned char reserved_11; + unsigned int sectorcount; + unsigned char reserved_12[288]; + unsigned char supportedcommandsets; + unsigned char reserved_13[7]; +} mmc_extended_csd_reg_t; + +/* mmc sd responce */ +typedef struct { + unsigned int ocr; +} mmc_resp_r3; + +typedef struct { + unsigned short cardstatus; + unsigned short newpublishedrca; +} mmc_resp_r6; + +extern mmc_card_data mmc_dev; + +unsigned char mmc_lowlevel_init(void); +unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, + unsigned int *response); +unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); +unsigned char mmc_set_opendrain(unsigned char state); +unsigned char mmc_read_data(unsigned int base, unsigned int *output_buf); + +#endif /*MMC_PROTOCOL_H */ diff --git a/cpu/omap3/nand.c b/cpu/omap3/nand.c new file mode 100644 index 000000000..1a64a9c34 --- /dev/null +++ b/cpu/omap3/nand.c @@ -0,0 +1,550 @@ +/* + * (C) Copyright 2004-2009 Texas Instruments, + * Rohit Choraria + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include + +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include + +#if (CONFIG_FASTBOOT) +#include +#endif + +unsigned char cs; +volatile unsigned long gpmc_cs_base_add; + +#define GPMC_BUF_EMPTY 0 +#define GPMC_BUF_FULL 1 + +#define ECC_P1_128_E(val) ((val) & 0x000000FF) /* Bit 0 to 7 */ +#define ECC_P512_2048_E(val) (((val) & 0x00000F00)>>8) /* Bit 8 to 11 */ +#define ECC_P1_128_O(val) (((val) & 0x00FF0000)>>16) /* Bit 16 to Bit 23 */ +#define ECC_P512_2048_O(val) (((val) & 0x0F000000)>>24) /* Bit 24 to Bit 27 */ + +void omap_nand_switch_ecc(struct mtd_info *, int ); + +int nand_unlock(struct mtd_info *mtd, unsigned long off, unsigned long size) +{ + register struct nand_chip *this = mtd->priv; + unsigned long start_block, end_block; + + printk("\nUnlocking %x - %x. locking rest..\n", off, off + size); + + if (off + size == this->chipsize) + size -= mtd->erasesize; + start_block = (unsigned long) (off >> this->page_shift); + end_block = (unsigned long) ((off + size) >> this->page_shift); + + this->cmdfunc(mtd, 0x23, -1, start_block); + this->cmdfunc(mtd, 0x24, -1, end_block); + ndelay (100); + + return 0; +} +/* + * omap_nand_hwcontrol - Set the address pointers corretly for the + * following address/data/command operation + * @mtd: MTD device structure + * @ctrl: Says whether Address or Command or Data is following. + */ + +static void omap_nand_hwcontrol(struct mtd_info *mtd, int ctrl) +{ + register struct nand_chip *this = mtd->priv; + + +/* + * Point the IO_ADDR to DATA and ADDRESS registers instead of chip address + */ + switch (ctrl) { + case NAND_CTL_SETCLE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + case NAND_CTL_SETALE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_ADR; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + case NAND_CTL_CLRCLE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + case NAND_CTL_CLRALE: + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + break; + } +} + +/* + * omap_nand_wait - called primarily after a program/erase operation + * so that we access NAND again only after the device + * is ready again. + * @mtd: MTD device structure + * @chip: nand_chip structure + * @state: State from which wait function is being called i.e write/erase. + */ +static int omap_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state) +{ + register struct nand_chip *this = mtd->priv; + int status = 0; + void *nand_ptr_r, *nand_ptr_w; + + this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD; + this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT; + nand_ptr_w = this->IO_ADDR_W; + nand_ptr_r = this->IO_ADDR_R; + + /* Send the status command and loop until the device is free */ + while(!(status & 0x40)){ + __raw_writeb(NAND_CMD_STATUS & 0xFF, nand_ptr_w); + status = __raw_readb(nand_ptr_r); + } + return status; +} + +#ifdef CFG_NAND_WIDTH_16 +/** + * omap_nand_write_buf16 - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 16bit buswith + */ +static void omap_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + void *nand_ptr_w = this->IO_ADDR_W; + + len >>= 1; + + for (i=0; ipriv; + u16 *p = (u16 *) buf; + void *nand_ptr_r = this->IO_ADDR_R; + + len >>= 1; + + for (i=0; ipriv; + void *nand_ptr_w = this->IO_ADDR_W; + + for (i = 0; i < len; i++) { + writeb(buf[i], nand_ptr_w); + for(j=0;j<10;j++); + } + +} + +/* + * omap_nand_read_buf - read data from NAND controller into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + */ + +static void omap_nand_read_buf(struct mtd_info *mtd, uint8_t * buf, int len) +{ + int i; + int j=0; + struct nand_chip *this = mtd->priv; + void *nand_ptr_r = this->IO_ADDR_R; + + for (i = 0; i < len; i++) { + buf[i] = readb(nand_ptr_r); + while (GPMC_BUF_EMPTY == (readl(GPMC_STATUS) & GPMC_BUF_FULL)); + } +} +#endif + +/* + * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in GPMC controller + * @mtd: MTD device structure + * + */ +static void omap_hwecc_init(struct nand_chip *chip) +{ + unsigned long val = 0x0; + + /* Init ECC Control Register */ + /* Clear all ECC | Enable Reg1 */ + val = ( (0x00000001<<8) | 0x00000001 ); + __raw_writel(val, GPMC_BASE + GPMC_ECC_CONTROL); + __raw_writel(0x3fcff000, GPMC_BASE + GPMC_ECC_SIZE_CONFIG); +} + +/* + * omap_correct_data - Compares the ecc read from nand spare area with ECC registers values + * and corrects one bit error if it has occured + * @mtd: MTD device structure + * @dat: page data + * @read_ecc: ecc read from nand flash + * @calc_ecc: ecc read from ECC registers + */ +static int omap_correct_data(struct mtd_info *mtd,u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + return 0; +} + +/* + * omap_calculate_ecc - Generate non-inverted ECC bytes. + * + * Using noninverted ECC can be considered ugly since writing a blank + * page ie. padding will clear the ECC bytes. This is no problem as + * long nobody is trying to write data on the seemingly unused page. + * Reading an erased page will produce an ECC mismatch between + * generated and read ECC bytes that has to be dealt with separately. + * @mtd: MTD structure + * @dat: unused + * @ecc_code: ecc_code buffer +*/ +static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) +{ + unsigned long val = 0x0; + unsigned long reg; + + /* Start Reading from HW ECC1_Result = 0x200 */ + reg = (unsigned long)(GPMC_BASE + GPMC_ECC1_RESULT); + val = __raw_readl(reg); + + *ecc_code++ = ECC_P1_128_E(val); + *ecc_code++ = ECC_P1_128_O(val); + *ecc_code++ = ECC_P512_2048_E(val) | ECC_P512_2048_O(val) << 4; + + return 0; +} + +/* + * omap_enable_ecc - This function enables the hardware ecc functionality + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +static void omap_enable_hwecc(struct mtd_info *mtd , int mode) +{ + struct nand_chip *chip = mtd->priv; + unsigned int val = __raw_readl(GPMC_BASE + GPMC_ECC_CONFIG); + unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; + + switch (mode) { + case NAND_ECC_READ : + __raw_writel(0x101, GPMC_BASE + GPMC_ECC_CONTROL); + /* ECC col width) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1) ; + break; + case NAND_ECC_READSYN : + __raw_writel(0x100, GPMC_BASE + GPMC_ECC_CONTROL); + /* ECC col width) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1) ; + break; + case NAND_ECC_WRITE : + __raw_writel(0x101, GPMC_BASE + GPMC_ECC_CONTROL); + /* ECC col width) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (cs << 1) | (0x1) ; + break; + default: + printf("Error: Unrecognized Mode[%d]!\n", mode); + break; + } + + __raw_writel(val, GPMC_BASE + GPMC_ECC_CONFIG); +} + +static struct nand_oobinfo hw_nand_oob_64 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 12, + .eccpos = { + 2, 3, 4, 5, + 6, 7, 8, 9, + 10, 11, 12, 13 + }, + .oobfree = { {14, 50} } /* don't care */ +}; + +static struct nand_oobinfo sw_nand_oob_64 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 24, + .eccpos = { + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63 + }, + .oobfree = { {2, 38} } +}; + + +void omap_nand_switch_ecc(struct mtd_info *mtd, int hardware) +{ + struct nand_chip *nand = mtd->priv; + + if (!hardware) { + nand->eccmode = NAND_ECC_SOFT; + nand->autooob = &sw_nand_oob_64; +#if (CFG_SW_ECC_512) + nand->eccsize = 512; +#else + nand->eccsize = 256; +#endif + nand->eccbytes = 3; + nand->eccsteps = mtd->oobblock / nand->eccsize; + nand->enable_hwecc = 0; + nand->calculate_ecc = nand_calculate_ecc; + nand->correct_data = nand_correct_data; + } else { + nand->eccmode = NAND_ECC_HW3_512; + nand->autooob = &hw_nand_oob_64; + nand->eccsize = 512; + nand->eccbytes = 3; + nand->eccsteps = 4; + nand->enable_hwecc = omap_enable_hwecc; + nand->correct_data = omap_correct_data; + nand->calculate_ecc = omap_calculate_ecc; + + omap_hwecc_init(nand); + } + + mtd->eccsize = nand->eccsize; + nand->oobdirty = 1; + + if (nand->options & NAND_BUSWIDTH_16) { + mtd->oobavail = mtd->oobsize - (nand->autooob->eccbytes + 2); + if (nand->autooob->eccbytes & 0x01) + mtd->oobavail--; + } else + mtd->oobavail = mtd->oobsize - (nand->autooob->eccbytes + 1); +} + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand_new.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +void board_nand_init(struct nand_chip *nand) +{ + int gpmc_config=0; + cs = 0; + while (cs <= GPMC_MAX_CS) { + /* Each GPMC set for a single CS is at offset 0x30 */ + /* already remapped for us */ + gpmc_cs_base_add = (GPMC_CONFIG_CS0 + (cs*0x30)); + /* xloader/Uboot would have written the NAND type for us + * -NOTE This is a temporary measure and cannot handle ONENAND. + * The proper way of doing this is to pass the setup of u-boot up to kernel + * using kernel params - something on the lines of machineID + */ + /* Check if NAND type is set */ + if ((__raw_readl(gpmc_cs_base_add + GPMC_CONFIG1) & 0xC00)==0x800) { + /* Found it!! */ + break; + } + cs++; + } + if (cs > GPMC_MAX_CS) { + printk ("NAND: Unable to find NAND settings in GPMC Configuration - quitting\n"); + } + + gpmc_config = __raw_readl(GPMC_CONFIG); + /* Disable Write protect */ + gpmc_config |= 0x10; + __raw_writel(gpmc_config, GPMC_CONFIG); + + + nand->IO_ADDR_R = (void *)gpmc_cs_base_add + GPMC_NAND_DAT; + nand->IO_ADDR_W = (void *)gpmc_cs_base_add + GPMC_NAND_CMD; + + nand->hwcontrol = omap_nand_hwcontrol; + nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR | + NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR; + nand->read_buf = omap_nand_read_buf; + nand->write_buf = omap_nand_write_buf; + +#if (CFG_HW_ECC_ROMCODE) + nand->eccmode = NAND_ECC_HW3_512; + nand->autooob = &hw_nand_oob_64; + nand->eccsize = 512; + nand->eccbytes = 3; + nand->eccsteps = 4; + nand->enable_hwecc = omap_enable_hwecc; + nand->correct_data = omap_correct_data; + nand->calculate_ecc = omap_calculate_ecc; + + omap_hwecc_init(nand); +#else + nand->eccmode = NAND_ECC_SOFT; +#if (CFG_SW_ECC_512) + nand->eccsize = 512; +#else + nand->eccsize = 256; +#endif +#endif +/* if RDY/BSY line is connected to OMAP then use the omap ready funcrtion + * and the generic nand_wait function which reads the status register after + * monitoring the RDY/BSY line. Otherwise use a standard chip delay which + * is slightly more than tR (AC Timing) of the NAND device and read the + * status register until you get a failure or success + */ + +#if 0 + nand->dev_ready = omap_nand_dev_ready; +#else + nand->waitfunc = omap_nand_wait; + nand->chip_delay = 50*2; +#endif + +#if (CONFIG_FASTBOOT) + /* Initialize the name of fastboot flash name mappings */ + fastboot_ptentry ptn[7] = { + { + .name = "xloader", + .start = 0x0000000, + .length = 0x0020000, + /* Written into the first 4 0x20000 blocks + Use HW ECC */ + .flags = FASTBOOT_PTENTRY_FLAGS_WRITE_I | + FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC, + }, + + { + .name = "bootloader", + .start = 0x0080000, + .length = 0x0180000, /* 1.5 M */ + /* Skip bad blocks on write + Use HW ECC */ + .flags = FASTBOOT_PTENTRY_FLAGS_WRITE_I | + FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC, + }, + { + .name = "environment", + .start = SMNAND_ENV_OFFSET, /* set in config file */ + .length = 0x0040000, + .flags = FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC | + FASTBOOT_PTENTRY_FLAGS_WRITE_ENV, + }, + + { + .name = "kernel", + /* Test with start close to bad block + The is dependent on the individual board. + Change to what is required */ + /* .start = 0x0a00000, */ + + /* The real start */ + .start = 0x0200000, + .length = 0x1D00000, /* 30M */ + .flags = FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC | + FASTBOOT_PTENTRY_FLAGS_WRITE_I, + }, +#ifndef CFG_NAND_YAFFS_WRITE +#warn "CFG_NAND_YAFFS_WRITE must be defined" +#endif + { + .name = "system", + .start = 0x2000000, + .flags = FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC | + FASTBOOT_PTENTRY_FLAGS_WRITE_YAFFS, + }, + { + .name = "userdata", + .start = 0xD400000, + .length = 0x4000000, /* 64M */ + .flags = FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC | + FASTBOOT_PTENTRY_FLAGS_WRITE_YAFFS, + }, + { + .name = "cache", + .start = 0x11400000, + .length = 0x2000000, /* 32M */ + .flags = FASTBOOT_PTENTRY_FLAGS_WRITE_HW_ECC | + FASTBOOT_PTENTRY_FLAGS_WRITE_YAFFS, + }, + }; + int i; + for (i = 0; i < 7; i++) + fastboot_flash_add_ptn (&ptn[i]); + +#endif + +} + + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ + diff --git a/cpu/omap3/start.S b/cpu/omap3/start.S new file mode 100644 index 000000000..18d673936 --- /dev/null +++ b/cpu/omap3/start.S @@ -0,0 +1,511 @@ +/* + * armboot - Startup Code for OMAP3430/ARM Cortex CPU-core + * + * Copyright (c) 2004 Texas Instruments + * + * Copyright (c) 2001 Marius Gröger + * Copyright (c) 2002 Alex Züpke + * Copyright (c) 2002 Gary Jennejohn + * Copyright (c) 2003 Richard Woodruff + * Copyright (c) 2003 Kshitij + * Copyright (c) 2006 Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR) +#include +#endif +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +.global _end_vect +_end_vect: + + .balignl 16,0xdeadbeef +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + +#ifdef CONFIG_OMAP34XX + /* Copy vectors to mask ROM indirect addr */ + adr r0, _start /* r0 <- current position of code */ + add r0, r0, #4 /* skip reset vector */ + mov r2, #64 /* r2 <- size to copy */ + add r2, r0, r2 /* r2 <- source end address */ + mov r1, #SRAM_OFFSET0 /* build vect addr */ + mov r3, #SRAM_OFFSET1 + add r1, r1, r3 + mov r3, #SRAM_OFFSET2 + add r1, r1, r3 +next: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next /* loop until equal */ +#if !defined(CFG_NAND_BOOT) && !defined(CFG_ONENAND_BOOT) + /* No need to copy/exec the clock code - DPLL adjust already done + * in NAND/oneNAND Boot. + */ + bl cpy_clk_code /* put dpll adjust code behind vectors */ +#endif /* NAND Boot */ +#endif /* 24xx */ + /* the mask ROM code should have PLL and others stable */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: /* relocate U-Boot to RAM */ + adr r0, _start /* r0 <- current position of code */ + ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ + cmp r0, r1 /* don't reloc during debug */ + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + +copy_loop: /* copy 32 bytes at a time */ + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ + sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 /* leave 3 words for abort-stack */ + and sp, sp, #~7 /* 8 byte alinged for (ldr/str)d */ + + /* Clear BSS (if any). Is below tx (watch load addr - need space) */ +clear_bss: + ldr r0, _bss_start /* find start of bss segment */ + ldr r1, _bss_end /* stop here */ + mov r2, #0x00000000 /* clear value */ +clbss_l: + str r2, [r0] /* clear BSS location */ + cmp r0, r1 /* are we at the end yet */ + add r0, r0, #4 /* increment clear index pointer */ + bne clbss_l /* keep clearing till at end */ + + ldr pc, _start_armboot /* jump to C code */ + +_start_armboot: .word start_armboot + + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * Invalidate L1 I/D + */ + mov r0, #0 /* set up for MCR */ + mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002000 @ clear bits 13 (--V-) + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) + orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align + orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB + mcr p15, 0, r0, c1, c0, 0 + + /* + * Jump to board specific initialization... The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle wake up conditions. + */ + mov ip, lr /* persevere link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack + stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 + + ldr r2, _armboot_start + sub r2, r2, #(CFG_MALLOC_LEN) + sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack + ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack (enter in banked mode) + sub r13, r13, #(CFG_MALLOC_LEN) @ move past malloc pool + sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack + + str lr, [r13] @ save caller lr in position 0 of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of saved stack + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & switch modes. + .endm + + .macro get_bad_stack_swi + sub r13, r13, #4 @ space on current stack for scratch reg. + str r0, [r13] @ save R0's value. + ldr r0, _armboot_start @ get data regions start + sub r0, r0, #(CFG_MALLOC_LEN) @ move past malloc pool + sub r0, r0, #(CFG_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack + str lr, [r0] @ save caller lr in position 0 of saved stack + mrs r0, spsr @ get the spsr + str lr, [r0, #4] @ save spsr in position 1 of saved stack + ldr r0, [r13] @ restore r0 + add r13, r13, #4 @ pop stack entry + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack_swi + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + +#ifdef CONFIG_OMAP34XX +/* Service ID from Primary Protected Application */ +#define PPA_L2_INVALIDATE 40 + +l2_inv_api_params: + .word 0x1, 0x0 +#endif + + .align 5 +.global arm_cache_flush +arm_cache_flush: + mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache + mov pc, lr @ back to caller + +/* + * v7_flush_dcache_all() + * + * Flush the whole D-cache. + * + * Corrupted registers: r0-r5, r7, r9-r11 + * + * - mm - mm_struct describing address space + */ + .align 5 +.global v7_flush_dcache_all +v7_flush_dcache_all: + stmfd r13!, {r0-r12, r14} + +#ifdef CONFIG_OMAP34XX + cmp r0, #0x3 @ check if the device is GP + beq gp_l2_inv + cmp r1, #1 @ or if it is EMU/HS device + beq emu_ext_boot_l2_inv @ in external boot mode + +emu_internal_boot_l2_inv: + mov r0, #PPA_L2_INVALIDATE @ set service ID for PPA + mov r12, r0 @ copy secure Service ID in r12 + mov r1, #0 @ set task id for ROM code in r1 + mov r2, #7 @ set some flags in r2, r6 + mov r6, #0xff + adr r3, l2_inv_api_params @ r3 points to dummy parameters + mcr p15, 0, r0, c7, c5, 4 @ data write barrier + mcr p15, 0, r0, c7, c10, 5 @ data memory barrier + .word 0xE1600071 @ call SMI monitor (smi #1) + b finished_inval + +gp_l2_inv: + mov r12, #0x1 @ set up to invalidate L2 + .word 0x01600070 @ call SMI monitor (smieq #0) + b finished_inval @ if GP device, inval done above + +emu_ext_boot_l2_inv: +#endif + + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished_inval @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +inval_loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip_inval @ skip if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb @ isb to sych the new cssr&csidr + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +inval_loop2: + mov r9, r4 @ create working copy of max way size +inval_loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge inval_loop3 + subs r7, r7, #1 @ decrement the index + bge inval_loop2 +skip_inval: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb + + ldmfd r13!, {r0-r12, pc} + + + .align 5 +.global reset_cpu +reset_cpu: + ldr r1, rstctl /* get addr for global reset reg */ + mov r3, #0x4 /* full cool reset pll+mpu */ + str r3, [r1] /* force reset */ + mov r0, r0 +_loop_forever: + b _loop_forever +rstctl: + .word PRM_RSTCTRL diff --git a/cpu/omap3/sys_info.c b/cpu/omap3/sys_info.c new file mode 100644 index 000000000..bb14c0b47 --- /dev/null +++ b/cpu/omap3/sys_info.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * Derived from board specific omap code by + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +/* + * get_cpu_rev(void) - extract version info + */ +u32 get_cpu_rev(void) +{ + u32 cpuid = 0; + ctrl_id_t *id_base; + /* + * On ES1.0 the IDCODE register is not exposed on L4 + * so using CPU ID to differentiate between ES1.0 and > ES1.0. + */ + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid)); + if ((cpuid & 0xf) == 0x0) + return CPU_3XX_ES10; + else { + /* Decode the IDs on > ES1.0 */ + id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE; + + cpuid = (__raw_readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf; + + /* Some early ES2.0 seem to report ID 0, fix this */ + if (cpuid == 0) + cpuid = CPU_3XX_ES20; + + return cpuid; + } +} + +/* + * dieid_num_r(void) - read and set die ID + */ +void dieid_num_r(void) +{ + ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE; + char *uid_s, die_id[34]; + u32 id[4]; + + memset(die_id, 0, sizeof(die_id)); + + uid_s = getenv("dieid#"); + + if (uid_s == NULL) { + id[3] = __raw_readl(&id_base->die_id_0); + id[2] = __raw_readl(&id_base->die_id_1); + id[1] = __raw_readl(&id_base->die_id_2); + id[0] = __raw_readl(&id_base->die_id_3); + sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]); + setenv("dieid#", die_id); + uid_s = die_id; + } +} + diff --git a/cpu/omap3/syslib.c b/cpu/omap3/syslib.c new file mode 100644 index 000000000..2b16cc476 --- /dev/null +++ b/cpu/omap3/syslib.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} + diff --git a/cpu/omap3/usb_debug_macros.h b/cpu/omap3/usb_debug_macros.h new file mode 100644 index 000000000..1bdb36d89 --- /dev/null +++ b/cpu/omap3/usb_debug_macros.h @@ -0,0 +1,230 @@ +#ifndef _USB_DEBUG_MACROS +#define _USB_DEBUG_MACROS + +#define PRINT_PWR(b) \ + printf ("\tpower 0x%2.2x\n", b); \ + if (b & MUSB_POWER_ISOUPDATE) \ + printf ("\t\tISOUPDATE\n"); \ + if (b & MUSB_POWER_SOFTCONN) \ + printf ("\t\tSOFTCONN\n"); \ + if (b & MUSB_POWER_HSENAB) \ + printf ("\t\tHSENAB\n"); \ + if (b & MUSB_POWER_HSMODE) \ + printf ("\t\tHSMODE\n"); \ + if (b & MUSB_POWER_RESET) \ + printf ("\t\tRESET\n"); \ + if (b & MUSB_POWER_RESUME) \ + printf ("\t\tRESUME\n"); \ + if (b & MUSB_POWER_SUSPENDM) \ + printf ("\t\tSUSPENDM\n"); \ + if (b & MUSB_POWER_ENSUSPEND) \ + printf ("\t\tENSUSPEND\n"); + +#define PRINT_CSR0(s) \ + printf ("\tcsr0 0x%4.4x\n", s); \ + if (s & MUSB_CSR0_FLUSHFIFO) \ + printf ("\t\tFLUSHFIFO\n"); \ + if (s & MUSB_CSR0_P_SVDSETUPEND) \ + printf ("\t\tSERV_SETUPEND\n"); \ + if (s & MUSB_CSR0_P_SVDRXPKTRDY) \ + printf ("\t\tSERV_RXPKTRDY\n"); \ + if (s & MUSB_CSR0_P_SENDSTALL) \ + printf ("\t\tSENDSTALL\n"); \ + if (s & MUSB_CSR0_P_SETUPEND) \ + printf ("\t\tSETUPEND\n"); \ + if (s & MUSB_CSR0_P_DATAEND) \ + printf ("\t\tDATAEND\n"); \ + if (s & MUSB_CSR0_P_SENTSTALL) \ + printf ("\t\tSENTSTALL\n"); \ + if (s & MUSB_CSR0_TXPKTRDY) \ + printf ("\t\tTXPKTRDY\n"); \ + if (s & MUSB_CSR0_RXPKTRDY) \ + printf ("\t\tRXPKTRDY\n"); + +#define PRINT_INTRUSB(b) \ + printf ("\tintrusb 0x%2.2x\n", b); \ + if (b & OMAP34XX_USB_INTRUSB_VBUSERR) \ + printf ("\t\tOMAP34XX_USB_INTRUSB_VBUSERR\n"); \ + if (b & OMAP34XX_USB_INTRUSB_SESSREQ) \ + printf ("\t\tOMAP34XX_USB_INTRUSB_SESSREQ\n"); \ + if (b & OMAP34XX_USB_INTRUSB_DISCON) \ + printf ("\t\tOMAP34XX_USB_INTRUSB_DISCON\n"); \ + if (b & OMAP34XX_USB_INTRUSB_CONN) \ + printf ("\t\tOMAP34XX_USB_INTRUSB_CONN\n"); \ + if (b & OMAP34XX_USB_INTRUSB_SOF) \ + printf ("\t\tOMAP34XX_USB_INTRUSB_SOF\n"); \ + if (b & OMAP34XX_USB_INTRUSB_RESET_BABBLE) \ + printf ("\t\tOMAP34XX_USB_INTRUSB_RESET_BABBLE\n"); \ + if (b & OMAP34XX_USB_INTRUSB_RESUME) \ + printf ("\t\tOMAP34XX_USB_INTRUSB_RESUME\n"); \ + if (b & OMAP34XX_USB_INTRUSB_SUSPEND) \ + printf ("\t\tOMAP34XX_USB_INTRUSB_SUSPEND\n"); + +#define PRINT_INTRTX(s) \ + printf ("\tintrtx 0x%4.4x\n", s); \ + +#define PRINT_INTRRX(s) \ + printf ("\tintrx 0x%4.4x\n", s); \ + +#define PRINT_DEVCTL(b) \ + printf ("\tdevctl 0x%2.2x\n", b); \ + if (b & MUSB_DEVCTL_BDEVICE) \ + printf ("\t\tB device\n"); \ + else \ + printf ("\t\tA device\n"); \ + if (b & MUSB_DEVCTL_FSDEV) \ + printf ("\t\tFast Device - (host mode)\n"); \ + if (b & MUSB_DEVCTL_LSDEV) \ + printf ("\t\tSlow Device - (host mode)\n"); \ + if (b & MUSB_DEVCTL_HM) \ + printf ("\t\tHost mode\n"); \ + else \ + printf ("\t\tPeripherial mode\n"); \ + if (b & MUSB_DEVCTL_HR) \ + printf ("\t\tHost request started (B device)\n"); \ + else \ + printf ("\t\tHost request finished (B device)\n"); \ + if (b & MUSB_DEVCTL_BDEVICE) \ + { \ + if (b & MUSB_DEVCTL_SESSION) \ + printf ("\t\tStart of session (B device)\n"); \ + else \ + printf ("\t\tEnd of session (B device)\n"); \ + } \ + else \ + { \ + if (b & MUSB_DEVCTL_SESSION) \ + printf ("\t\tStart of session (A device)\n"); \ + else \ + printf ("\t\tEnd of session (A device)\n"); \ + } + +#define PRINT_CONFIG(b) \ + printf ("\tconfig 0x%2.2x\n", b); \ + if (b & MUSB_CONFIGDATA_MPRXE) \ + printf ("\t\tAuto combine rx bulk packets\n"); \ + if (b & MUSB_CONFIGDATA_MPTXE) \ + printf ("\t\tAuto split tx bulk packets\n"); \ + if (b & MUSB_CONFIGDATA_BIGENDIAN) \ + printf ("\t\tBig Endian ordering\n"); \ + else \ + printf ("\t\tLittle Endian ordering\n"); \ + if (b & MUSB_CONFIGDATA_HBRXE) \ + printf ("\t\tHigh speed rx iso endpoint\n"); \ + if (b & MUSB_CONFIGDATA_HBTXE) \ + printf ("\t\tHigh speed tx iso endpoint\n"); \ + if (b & MUSB_CONFIGDATA_DYNFIFO) \ + printf ("\t\tDynamic fifo sizing\n"); \ + if (b & MUSB_CONFIGDATA_SOFTCONE) \ + printf ("\t\tSoft Connect\n"); \ + if (b & MUSB_CONFIGDATA_UTMIDW) \ + printf ("\t\t16 bit data width\n"); \ + else \ + printf ("\t\t8 bit data width\n"); + +#define PRINT_REQ(r) \ + printf ("usb request \n"); \ + printf ("\tbmRequestType 0x%2.2x\n", r.bmRequestType); \ + if (0 == (r.bmRequestType & USB_REQ_DIRECTION_MASK)) \ + printf ("\t\tDirection : To device\n"); \ + else \ + printf ("\t\tDirection : To host\n"); \ + if (USB_TYPE_STANDARD == (r.bmRequestType & USB_TYPE_STANDARD)) \ + printf ("\t\tType : Standard\n"); \ + if (USB_TYPE_CLASS == (r.bmRequestType & USB_TYPE_CLASS)) \ + printf ("\t\tType : Standard\n"); \ + if (USB_TYPE_VENDOR == (r.bmRequestType & USB_TYPE_VENDOR)) \ + printf ("\t\tType : Standard\n"); \ + if (USB_TYPE_RESERVED == (r.bmRequestType & USB_TYPE_RESERVED)) \ + printf ("\t\tType : Standard\n"); \ + if (USB_REQ_RECIPIENT_DEVICE == (r.bmRequestType & USB_REQ_RECIPIENT_MASK)) \ + printf ("\t\tRecipient : Device\n"); \ + if (USB_REQ_RECIPIENT_INTERFACE == (r.bmRequestType & USB_REQ_RECIPIENT_MASK)) \ + printf ("\t\tRecipient : Interface\n"); \ + if (USB_REQ_RECIPIENT_ENDPOINT == (r.bmRequestType & USB_REQ_RECIPIENT_MASK)) \ + printf ("\t\tRecipient : Endpoint\n"); \ + if (USB_REQ_RECIPIENT_OTHER == (r.bmRequestType & USB_REQ_RECIPIENT_MASK)) \ + printf ("\t\tRecipient : Other\n"); \ + printf ("\tbRequest 0x%2.2x\n", r.bRequest); \ + if (r.bRequest == USB_REQ_GET_STATUS) \ + printf ("\t\tGET_STATUS\n"); \ + else if (r.bRequest == USB_REQ_SET_ADDRESS) \ + printf ("\t\tSET_ADDRESS\n"); \ + else if (r.bRequest == USB_REQ_SET_FEATURE) \ + printf ("\t\tSET_FEATURE\n"); \ + else if (r.bRequest == USB_REQ_GET_DESCRIPTOR) \ + printf ("\t\tGET_DESCRIPTOR\n"); \ + else if (r.bRequest == USB_REQ_SET_CONFIGURATION) \ + printf ("\t\tSET_CONFIGURATION\n"); \ + else if (r.bRequest == USB_REQ_SET_INTERFACE) \ + printf ("\t\tUSB_REQ_SET_INTERFACE\n"); \ + else \ + printf ("\tUNKNOWN\n"); \ + printf ("\twValue 0x%4.4x\n", r.wValue); \ + printf ("\twIndex 0x%4.4x\n", r.wIndex); \ + printf ("\twLength 0x%4.4x\n", r.wLength); + + +#define PRINT_RXMAXP(s) \ + printf ("\trxmaxp 0x%4.4x\n", s) + +#define PRINT_RXCSR(s) \ + printf ("\trxcsr 0x%4.4x\n", s); \ + if (s & MUSB_RXCSR_AUTOCLEAR) \ + printf ("\t\tautclear\n"); \ + if (s & MUSB_RXCSR_DMAENAB) \ + printf ("\t\tdma enable\n"); \ + if (s & MUSB_RXCSR_DISNYET) \ + printf ("\t\tdisable nyet\n"); \ + if (s & MUSB_RXCSR_PID_ERR) \ + printf ("\t\tpid error\n"); \ + if (s & MUSB_RXCSR_DMAMODE) \ + printf ("\t\tdma mode should be 0 \n"); \ + if (s & MUSB_RXCSR_CLRDATATOG) \ + printf ("\t\tclear data\n"); \ + if (s & MUSB_RXCSR_FLUSHFIFO) \ + printf ("\t\tflush fifo\n"); \ + if (s & MUSB_RXCSR_DATAERROR) \ + printf ("\t\tdata error\n"); \ + if (s & MUSB_RXCSR_FIFOFULL) \ + printf ("\t\tfifo full\n"); \ + if (s & MUSB_RXCSR_RXPKTRDY) \ + printf ("\t\trx packet ready\n"); \ + if (s & MUSB_RXCSR_P_ISO) \ + printf ("\t\tiso mode\n"); \ + else \ + printf ("\t\tbulk mode\n"); \ + if (s & MUSB_RXCSR_P_SENTSTALL) \ + printf ("\t\tsent stall\n"); \ + if (s & MUSB_RXCSR_P_SENDSTALL) \ + printf ("\t\tsend stall\n"); \ + if (s & MUSB_RXCSR_P_OVERRUN) \ + printf ("\t\toverrun\n") + +#define PRINT_TXMAXP(s) \ + printf ("\ttxmaxp 0x%4.4x\n", s) + + +#define PRINT_TXCSR(s) \ + printf ("\ttxcsr 0x%4.4x\n", s); \ + if (s & MUSB_TXCSR_TXPKTRDY) \ + printf ("\t\ttxpktrdy\n"); \ + if (s & MUSB_TXCSR_FIFONOTEMPTY) \ + printf ("\t\tfifo not empty\n"); \ + if (s & MUSB_TXCSR_FLUSHFIFO) \ + printf ("\t\tflush fifo\n"); \ + if (s & MUSB_TXCSR_CLRDATATOG) \ + printf ("\t\tclear data toggle\n"); \ + if (s & MUSB_TXCSR_MODE) \ + printf ("\t\tTX mode\n"); \ + else \ + printf ("\t\tRX mode\n"); \ + if (s & MUSB_TXCSR_P_UNDERRUN) \ + printf ("\t\tunderrun\n"); \ + if (s & MUSB_TXCSR_P_SENTSTALL) \ + printf ("\t\tsent stall\n"); \ + if (s & MUSB_TXCSR_P_SENDSTALL) \ + printf ("\t\tsend stall\n"); \ + + +#endif diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c new file mode 100644 index 000000000..cf5eccb01 --- /dev/null +++ b/cpu/ppc4xx/405gp_pci.c @@ -0,0 +1,572 @@ +/*-----------------------------------------------------------------------------+ + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + *-----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ + * + * File Name: 405gp_pci.c + * + * Function: Initialization code for the 405GP PCI Configuration regs. + * + * Author: Mark Game + * + * Change Activity- + * + * Date Description of Change BY + * --------- --------------------- --- + * 09-Sep-98 Created MCG + * 02-Nov-98 Removed External arbiter selected message JWB + * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB + * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG + * from (0 to n) to (1 to n). + * 17-May-99 Port to Walnut JWB + * 17-Jun-99 Updated for VGA support JWB + * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB + * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG + * target latency timer values are not supported). + * Should be fixed in pass 2. + * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB + * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS. + * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB + * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not + * really required after a reset since PMMxMAs are already + * disabled but is a good practice nonetheless. JWB + * 12-Jun-01 stefan.roese@esd-electronics.com + * - PCI host/adapter handling reworked + * 09-Jul-01 stefan.roese@esd-electronics.com + * - PCI host now configures from device 0 (not 1) to max_dev, + * (host configures itself) + * - On CPCI-405 pci base address and size is generated from + * SDRAM and FLASH size (CFG regs not used anymore) + * - Some minor changes for CPCI-405-A (adapter version) + * 14-Sep-01 stefan.roese@esd-electronics.com + * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup + * 28-Sep-01 stefan.roese@esd-electronics.com + * - Changed pci master configuration for linux compatibility + * (no need for bios_fixup() anymore) + * 26-Feb-02 stefan.roese@esd-electronics.com + * - Bug fixed in pci configuration (Andrew May) + * - Removed pci class code init for CPCI405 board + * 15-May-02 stefan.roese@esd-electronics.com + * - New vga device handling + * 29-May-02 stefan.roese@esd-electronics.com + * - PCI class code init added (if defined) + *----------------------------------------------------------------------------*/ + +#include +#include +#if !defined(CONFIG_440) +#include <405gp_pci.h> +#endif +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) + +#ifdef CONFIG_PCI + +#if defined(CONFIG_PMC405) +ushort pmc405_pci_subsys_deviceid(void); +#endif + +/*#define DEBUG*/ + +/*-----------------------------------------------------------------------------+ + * pci_init. Initializes the 405GP PCI Configuration regs. + *-----------------------------------------------------------------------------*/ +void pci_405gp_init(struct pci_controller *hose) +{ + int i, reg_num = 0; + bd_t *bd = gd->bd; + + unsigned short temp_short; + unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; +#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) + char *ptmla_str, *ptmms_str; +#endif + unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; + unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS}; +#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) + unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; + unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; + unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; + unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0}; +#else + unsigned long pmmla[3] = {0x80000000, 0,0}; + unsigned long pmmma[3] = {0xC0000001, 0,0}; + unsigned long pmmpcila[3] = {0x80000000, 0,0}; + unsigned long pmmpciha[3] = {0x00000000, 0,0}; +#endif +#ifdef CONFIG_PCI_PNP +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + char *s; +#endif +#endif + +#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) + ptmla_str = getenv("ptm1la"); + ptmms_str = getenv("ptm1ms"); + if(NULL != ptmla_str && NULL != ptmms_str ) { + ptmla[0] = simple_strtoul (ptmla_str, NULL, 16); + ptmms[0] = simple_strtoul (ptmms_str, NULL, 16); + } + + ptmla_str = getenv("ptm2la"); + ptmms_str = getenv("ptm2ms"); + if(NULL != ptmla_str && NULL != ptmms_str ) { + ptmla[1] = simple_strtoul (ptmla_str, NULL, 16); + ptmms[1] = simple_strtoul (ptmms_str, NULL, 16); + } +#endif + + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + MIN_PCI_PCI_IOADDR, + MIN_PLB_PCI_IOADDR, + 0x10000, + PCI_REGION_IO); + + /* PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + 0x00800000, + 0xe8800000, + 0x03800000, + PCI_REGION_IO); + + reg_num = 2; + + /* Memory spaces */ + for (i=0; i<2; i++) + if (ptmms[i] & 1) + { + if (!i) hose->pci_fb = hose->regions + reg_num; + + pci_set_region(hose->regions + reg_num++, + ptmpcila[i], ptmla[i], + ~(ptmms[i] & 0xfffff000) + 1, + PCI_REGION_MEM | + PCI_REGION_MEMORY); + } + + /* PCI memory spaces */ + for (i=0; i<3; i++) + if (pmmma[i] & 1) + { + pci_set_region(hose->regions + reg_num++, + pmmpcila[i], pmmla[i], + ~(pmmma[i] & 0xfffff000) + 1, + PCI_REGION_MEM); + } + + hose->region_count = reg_num; + + pci_setup_indirect(hose, + PCICFGADR, + PCICFGDATA); + + if (hose->pci_fb) + pciauto_region_init(hose->pci_fb); + + pci_register_hose(hose); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Master configuration. + * Map one 512 MB range of PLB/processor addresses to PCI memory space. + * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF + * Use byte reversed out routines to handle endianess. + *--------------------------------------------------------------------------*/ + out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */ + out32r(PMM0LA, pmmla[0]); + out32r(PMM0PCILA, pmmpcila[0]); + out32r(PMM0PCIHA, pmmpciha[0]); + out32r(PMM0MA, pmmma[0]); + + /*--------------------------------------------------------------------------+ + * PMM1 is not used. Initialize them to zero. + *--------------------------------------------------------------------------*/ + out32r(PMM1MA, (pmmma[1]&~0x1)); + out32r(PMM1LA, pmmla[1]); + out32r(PMM1PCILA, pmmpcila[1]); + out32r(PMM1PCIHA, pmmpciha[1]); + out32r(PMM1MA, pmmma[1]); + + /*--------------------------------------------------------------------------+ + * PMM2 is not used. Initialize them to zero. + *--------------------------------------------------------------------------*/ + out32r(PMM2MA, (pmmma[2]&~0x1)); + out32r(PMM2LA, pmmla[2]); + out32r(PMM2PCILA, pmmpcila[2]); + out32r(PMM2PCIHA, pmmpciha[2]); + out32r(PMM2MA, pmmma[2]); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Target configuration. (PTM1) + * Note: PTM1MS is hardwire enabled but we set the enable bit anyway. + *--------------------------------------------------------------------------*/ + out32r(PTM1LA, ptmla[0]); /* insert address */ + out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Target configuration. (PTM2) + *--------------------------------------------------------------------------*/ + out32r(PTM2LA, ptmla[1]); /* insert address */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]); + + if (ptmms[1] == 0) + { + out32r(PTM2MS, 0x00000001); /* set enable bit */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); + out32r(PTM2MS, 0x00000000); /* disable */ + } + else + { + out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ + } + + /* + * Insert Subsystem Vendor and Device ID + */ + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); +#ifdef CONFIG_CPCI405 + if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); + else + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2); +#else + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); +#endif + + /* + * Insert Class-code + */ +#ifdef CFG_PCI_CLASSCODE + pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE); +#endif /* CFG_PCI_CLASSCODE */ + + /*--------------------------------------------------------------------------+ + * If PCI speed = 66Mhz, set 66Mhz capable bit. + *--------------------------------------------------------------------------*/ + if (bd->bi_pci_busfreq >= 66000000) { + pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); + pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ)); + } + +#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER) +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || + (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) +#endif + { + /*--------------------------------------------------------------------------+ + * Write the 405GP PCI Configuration regs. + * Enable 405GP to be a master on the PCI bus (PMM). + * Enable 405GP to act as a PCI memory target (PTM). + *--------------------------------------------------------------------------*/ + pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); + pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + } +#endif + +#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */ + pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */ +#endif + + /* + * Set HCE bit (Host Configuration Enabled) + */ + pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); + pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); + +#ifdef CONFIG_PCI_PNP + /*--------------------------------------------------------------------------+ + * Scan the PCI bus and configure devices found. + *--------------------------------------------------------------------------*/ +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || + (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) +#endif + { +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + + hose->last_busno = pci_hose_scan(hose); + } +#endif /* CONFIG_PCI_PNP */ + +} + +/* + * drivers/pci.c skips every host bridge but the 405GP since it could + * be set as an Adapter. + * + * I (Andrew May) don't know what we should do here, but I don't want + * the auto setup of a PCI device disabling what is done pci_405gp_init + * as has happened before. + */ +void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry) +{ +#ifdef DEBUG + printf("405gp_setup_bridge\n"); +#endif +} + +/* + * + */ + +void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line = 0xff; + + /* + * Write pci interrupt line register (cpci405 specific) + */ + switch (PCI_DEV(dev) & 0x03) + { + case 0: + int_line = 27 + 2; + break; + case 1: + int_line = 27 + 3; + break; + case 2: + int_line = 27 + 0; + break; + case 3: + int_line = 27 + 1; + break; + } + + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); +} + +void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry) +{ + unsigned int cmdstat = 0; + + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + + /* always enable io space on vga boards */ + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat |= PCI_COMMAND_IO; + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); +} + +#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) + +/* + *As is these functs get called out of flash Not a horrible + *thing, but something to keep in mind. (no statics?) + */ +static struct pci_config_table pci_405gp_config_table[] = { +/*if VendID is 0 it terminates the table search (ie Walnut)*/ +#ifdef CFG_PCI_SUBSYS_VENDORID + {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge}, +#endif + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, + + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, + + { } +}; + +static struct pci_controller hose = { + fixup_irq: pci_405gp_fixup_irq, + config_table: pci_405gp_config_table, +}; + +void pci_init_board(void) +{ + /*we want the ptrs to RAM not flash (ie don't use init list)*/ + hose.fixup_irq = pci_405gp_fixup_irq; + hose.config_table = pci_405gp_config_table; + pci_405gp_init(&hose); +} + +#endif + +#endif /* CONFIG_PCI */ + +#endif /* CONFIG_405GP */ + +/*-----------------------------------------------------------------------------+ + * CONFIG_440 + *-----------------------------------------------------------------------------*/ +#if defined(CONFIG_440) && defined(CONFIG_PCI) + +static struct pci_controller ppc440_hose = {0}; + + +void pci_440_init (struct pci_controller *hose) +{ + int reg_num = 0; + +#ifndef CONFIG_DISABLE_PISE_TEST + /*--------------------------------------------------------------------------+ + * The PCI initialization sequence enable bit must be set ... if not abort + * pci setup since updating the bit requires chip reset. + *--------------------------------------------------------------------------*/ +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) + unsigned long strap; + + mfsdr(sdr_sdstp1,strap); + if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { + printf("PCI: SDR0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#elif defined(CONFIG_440GP) + unsigned long strap; + + strap = mfdcr(cpc0_strp1); + if ((strap & CPC0_STRP1_PISE_MASK) == 0) { + printf("PCI: CPC0_STRP1[PISE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#endif +#endif /* CONFIG_DISABLE_PISE_TEST */ + + /*--------------------------------------------------------------------------+ + * PCI controller init + *--------------------------------------------------------------------------*/ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + 0x00000000, + PCIX0_IOBASE, + 0x10000, + PCI_REGION_IO); + + /* PCI memory space */ + pci_set_region(hose->regions + reg_num++, + CFG_PCI_TARGBASE, + CFG_PCI_MEMBASE, + 0x10000000, + PCI_REGION_MEM ); + +#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ + defined(CONFIG_PCI_SYS_MEM_SIZE) + /* System memory space */ + pci_set_region(hose->regions + reg_num++, + CONFIG_PCI_SYS_MEM_BUS, + CONFIG_PCI_SYS_MEM_PHYS, + CONFIG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY ); +#endif + + hose->region_count = reg_num; + + pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); + +#if defined(CFG_PCI_PRE_INIT) + /* Let board change/modify hose & do initial checks */ + if (pci_pre_init (hose) == 0) { + printf("PCI: Board-specific initialization failed.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } +#endif + + pci_register_hose( hose ); + + /*--------------------------------------------------------------------------+ + * PCI target init + *--------------------------------------------------------------------------*/ +#if defined(CFG_PCI_TARGET_INIT) + pci_target_init(hose); /* Let board setup pci target */ +#else + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID ); + out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) + out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ +#elif defined(PCIX0_BRDGOPT1) + out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ + out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ +#endif + + /*--------------------------------------------------------------------------+ + * PCI master init: default is one 256MB region for PCI memory: + * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE + *--------------------------------------------------------------------------*/ +#if defined(CFG_PCI_MASTER_INIT) + pci_master_init(hose); /* Let board setup pci master */ +#else + out32r( PCIX0_POM0SA, 0 ); /* disable */ + out32r( PCIX0_POM1SA, 0 ); /* disable */ + out32r( PCIX0_POM2SA, 0 ); /* disable */ +#if defined(CONFIG_440SPE) + out32r( PCIX0_POM0LAL, 0x10000000 ); + out32r( PCIX0_POM0LAH, 0x0000000c ); +#else + out32r( PCIX0_POM0LAL, 0x00000000 ); + out32r( PCIX0_POM0LAH, 0x00000003 ); +#endif + out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE ); + out32r( PCIX0_POM0PCIAH, 0x00000000 ); + out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ + out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); +#endif + + /*--------------------------------------------------------------------------+ + * PCI host configuration -- we don't make any assumptions here ... the + * _board_must_indicate_ what to do -- there's just too many runtime + * scenarios in environments like cPCI, PPMC, etc. to make a determination + * based on hard-coded values or state of arbiter enable. + *--------------------------------------------------------------------------*/ + if (is_pci_host(hose)) { +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif +#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) + out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); +#endif + hose->last_busno = pci_hose_scan(hose); + } +} + + +void pci_init_board(void) +{ + pci_440_init (&ppc440_hose); +} + +#endif /* CONFIG_440 & CONFIG_PCI */ diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 4e863dc91..fab65aff7 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -81,25 +81,22 @@ #include #include #include -#include -#include -#include #include #include #include #include <405_mal.h> #include #include -#include +#include "vecnum.h" /* * Only compile for platform with AMCC EMAC ethernet controller and * network support enabled. * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller! */ -#if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) +#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480) -#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) #error "CONFIG_MII has to be defined!" #endif @@ -108,7 +105,7 @@ #endif #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ -#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */ +#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ /* Ethernet Transmit and Receive Buffers */ /* AS.HARNOIS @@ -133,35 +130,7 @@ #define BI_PHYMODE_NONE 0 #define BI_PHYMODE_ZMII 1 #define BI_PHYMODE_RGMII 2 -#define BI_PHYMODE_GMII 3 -#define BI_PHYMODE_RTBI 4 -#define BI_PHYMODE_TBI 5 -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) -#define BI_PHYMODE_SMII 6 -#define BI_PHYMODE_MII 7 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define BI_PHYMODE_RMII 8 -#endif -#endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) -#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) -#endif - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n)) -#endif - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */ -#else -#define MAL_RX_CHAN_MUL 1 -#endif /*-----------------------------------------------------------------------------+ * Global variables. TX and RX descriptors and buffers. @@ -176,14 +145,7 @@ struct eth_device *emac0_dev = NULL; /* * Get count of EMAC devices (doesn't have to be the max. possible number * supported by the cpu) - * - * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the - * EMAC count is possible. As it is needed for the Kilauea/Haleakala - * 405EX/405EXr eval board, using the same binary. */ -#if defined(CONFIG_BOARD_EMAC_COUNT) -#define LAST_EMAC_NUM board_emac_count() -#else /* CONFIG_BOARD_EMAC_COUNT */ #if defined(CONFIG_HAS_ETH3) #define LAST_EMAC_NUM 4 #elif defined(CONFIG_HAS_ETH2) @@ -193,22 +155,6 @@ struct eth_device *emac0_dev = NULL; #else #define LAST_EMAC_NUM 1 #endif -#endif /* CONFIG_BOARD_EMAC_COUNT */ - -/* normal boards start with EMAC0 */ -#if !defined(CONFIG_EMAC_NR_START) -#define CONFIG_EMAC_NR_START 0 -#endif - -#if defined(CONFIG_405EX) || defined(CONFIG_440EPX) -#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev))) -#else -#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2)) -#endif - -#define MAL_RX_DESC_SIZE 2048 -#define MAL_TX_DESC_SIZE 2048 -#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) /*-----------------------------------------------------------------------------+ * Prototypes and externals. @@ -227,46 +173,6 @@ extern int emac4xx_miiphy_read (char *devname, unsigned char addr, extern int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value); -int board_emac_count(void); - -static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) -{ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) - u32 val; - - mfsdr(sdr_mfr, val); - val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); - mtsdr(sdr_mfr, val); -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - u32 val; - - mfsdr(SDR0_ETH_CFG, val); - val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); - mtsdr(SDR0_ETH_CFG, val); -#endif -} - -static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) -{ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) - u32 val; - - mfsdr(sdr_mfr, val); - val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); - mtsdr(sdr_mfr, val); -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - u32 val; - - mfsdr(SDR0_ETH_CFG, val); - val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); - mtsdr(SDR0_ETH_CFG, val); -#endif -} - /*-----------------------------------------------------------------------------+ | ppc_4xx_eth_halt | Disable MAL channel, and EMACn @@ -274,9 +180,12 @@ static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; - u32 val = 10000; + uint32_t failsafe = 10000; +#if defined(CONFIG_440SPE) + unsigned long mfr; +#endif - out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ + out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ @@ -290,31 +199,33 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) /* wait for reset */ while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { udelay (1000); /* Delay 1 MS so as not to hammer the register */ - val--; - if (val == 0) + failsafe--; + if (failsafe == 0) break; } - /* provide clocks for EMAC internal loopback */ - emac_loopback_enable(hw_p); - /* EMAC RESET */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); +#if defined(CONFIG_440SPE) + /* provide clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr |= 0x08000000; + mtsdr(sdr_mfr, mfr); +#endif + out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + +#if defined(CONFIG_440SPE) /* remove clocks for EMAC internal loopback */ - emac_loopback_disable(hw_p); + mfsdr (sdr_mfr, mfr); + mfr &= ~0x08000000; + mtsdr(sdr_mfr, mfr); +#endif + #ifndef CONFIG_NETCONSOLE hw_p->print_speed = 1; /* print speed message again next time */ #endif -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) - /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ - mfsdr(SDR0_ETH_CFG, val); - val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); - mtsdr(SDR0_ETH_CFG, val); -#endif - return; } @@ -343,10 +254,10 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) bis->bi_phymode[3] = BI_PHYMODE_ZMII; break; case 2: - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); + zmiifer = ZMII_FER_SMII << ZMII_FER_V(0); + zmiifer = ZMII_FER_SMII << ZMII_FER_V(1); + zmiifer = ZMII_FER_SMII << ZMII_FER_V(2); + zmiifer = ZMII_FER_SMII << ZMII_FER_V(3); bis->bi_phymode[0] = BI_PHYMODE_ZMII; bis->bi_phymode[1] = BI_PHYMODE_ZMII; bis->bi_phymode[2] = BI_PHYMODE_ZMII; @@ -402,295 +313,17 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) /* Ensure we setup mdio for this devnum and ONLY this devnum */ zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out_be32((void *)ZMII_FER, zmiifer); - out_be32((void *)RGMII_FER, rmiifer); + out32 (ZMII_FER, zmiifer); + out32 (RGMII_FER, rmiifer); return ((int)pfc1); + } #endif /* CONFIG_440_GX */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) -{ - unsigned long zmiifer=0x0; - unsigned long pfc1; - - mfsdr(sdr_pfc1, pfc1); - pfc1 &= SDR0_PFC1_SELECT_MASK; - - switch (pfc1) { - case SDR0_PFC1_SELECT_CONFIG_2: - /* 1 x GMII port */ - out_be32((void *)ZMII_FER, 0x00); - out_be32((void *)RGMII_FER, 0x00000037); - bis->bi_phymode[0] = BI_PHYMODE_GMII; - bis->bi_phymode[1] = BI_PHYMODE_NONE; - break; - case SDR0_PFC1_SELECT_CONFIG_4: - /* 2 x RGMII ports */ - out_be32((void *)ZMII_FER, 0x00); - out_be32((void *)RGMII_FER, 0x00000055); - bis->bi_phymode[0] = BI_PHYMODE_RGMII; - bis->bi_phymode[1] = BI_PHYMODE_RGMII; - break; - case SDR0_PFC1_SELECT_CONFIG_6: - /* 2 x SMII ports */ - out_be32((void *)ZMII_FER, - ((ZMII_FER_SMII) << ZMII_FER_V(0)) | - ((ZMII_FER_SMII) << ZMII_FER_V(1))); - out_be32((void *)RGMII_FER, 0x00000000); - bis->bi_phymode[0] = BI_PHYMODE_SMII; - bis->bi_phymode[1] = BI_PHYMODE_SMII; - break; - case SDR0_PFC1_SELECT_CONFIG_1_2: - /* only 1 x MII supported */ - out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); - out_be32((void *)RGMII_FER, 0x00000000); - bis->bi_phymode[0] = BI_PHYMODE_MII; - bis->bi_phymode[1] = BI_PHYMODE_NONE; - break; - default: - break; - } - - /* Ensure we setup mdio for this devnum and ONLY this devnum */ - zmiifer = in_be32((void *)ZMII_FER); - zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out_be32((void *)ZMII_FER, zmiifer); - - return ((int)0x0); -} -#endif /* CONFIG_440EPX */ - -#if defined(CONFIG_405EX) -int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) -{ - u32 gmiifer = 0; - - /* - * Right now only 2*RGMII is supported. Please extend when needed. - * sr - 2007-09-19 - */ - switch (1) { - case 1: - /* 2 x RGMII ports */ - out_be32((void *)RGMII_FER, 0x00000055); - bis->bi_phymode[0] = BI_PHYMODE_RGMII; - bis->bi_phymode[1] = BI_PHYMODE_RGMII; - break; - case 2: - /* 2 x SMII ports */ - break; - default: - break; - } - - /* Ensure we setup mdio for this devnum and ONLY this devnum */ - gmiifer = in_be32((void *)RGMII_FER); - gmiifer |= (1 << (19-devnum)); - out_be32((void *)RGMII_FER, gmiifer); - - return ((int)0x0); -} -#endif /* CONFIG_405EX */ - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) -{ - u32 eth_cfg; - u32 zmiifer; /* ZMII0_FER reg. */ - u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ - u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ - int mode; - - zmiifer = 0; - rmiifer = 0; - rmiifer1 = 0; - -#if defined(CONFIG_460EX) - mode = 9; -#else - mode = 10; -#endif - - /* TODO: - * NOTE: 460GT has 2 RGMII bridge cores: - * emac0 ------ RGMII0_BASE - * | - * emac1 -----+ - * - * emac2 ------ RGMII1_BASE - * | - * emac3 -----+ - * - * 460EX has 1 RGMII bridge core: - * and RGMII1_BASE is disabled - * emac0 ------ RGMII0_BASE - * | - * emac1 -----+ - */ - - /* - * Right now only 2*RGMII is supported. Please extend when needed. - * sr - 2008-02-19 - */ - switch (mode) { - case 1: - /* 1 MII - 460EX */ - /* GMC0 EMAC4_0, ZMII Bridge */ - zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); - bis->bi_phymode[0] = BI_PHYMODE_MII; - bis->bi_phymode[1] = BI_PHYMODE_NONE; - bis->bi_phymode[2] = BI_PHYMODE_NONE; - bis->bi_phymode[3] = BI_PHYMODE_NONE; - break; - case 2: - /* 2 MII - 460GT */ - /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */ - zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); - zmiifer |= ZMII_FER_MII << ZMII_FER_V(2); - bis->bi_phymode[0] = BI_PHYMODE_MII; - bis->bi_phymode[1] = BI_PHYMODE_NONE; - bis->bi_phymode[2] = BI_PHYMODE_MII; - bis->bi_phymode[3] = BI_PHYMODE_NONE; - break; - case 3: - /* 2 RMII - 460EX */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); - bis->bi_phymode[0] = BI_PHYMODE_RMII; - bis->bi_phymode[1] = BI_PHYMODE_RMII; - bis->bi_phymode[2] = BI_PHYMODE_NONE; - bis->bi_phymode[3] = BI_PHYMODE_NONE; - break; - case 4: - /* 4 RMII - 460GT */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */ - /* ZMII Bridge */ - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); - zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); - bis->bi_phymode[0] = BI_PHYMODE_RMII; - bis->bi_phymode[1] = BI_PHYMODE_RMII; - bis->bi_phymode[2] = BI_PHYMODE_RMII; - bis->bi_phymode[3] = BI_PHYMODE_RMII; - break; - case 5: - /* 2 SMII - 460EX */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); - bis->bi_phymode[0] = BI_PHYMODE_SMII; - bis->bi_phymode[1] = BI_PHYMODE_SMII; - bis->bi_phymode[2] = BI_PHYMODE_NONE; - bis->bi_phymode[3] = BI_PHYMODE_NONE; - break; - case 6: - /* 4 SMII - 460GT */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */ - /* ZMII Bridge */ - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); - zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); - bis->bi_phymode[0] = BI_PHYMODE_SMII; - bis->bi_phymode[1] = BI_PHYMODE_SMII; - bis->bi_phymode[2] = BI_PHYMODE_SMII; - bis->bi_phymode[3] = BI_PHYMODE_SMII; - break; - case 7: - /* This is the default mode that we want for board bringup - Maple */ - /* 1 GMII - 460EX */ - /* GMC0 EMAC4_0, RGMII Bridge 0 */ - rmiifer |= RGMII_FER_MDIO(0); - - if (devnum == 0) { - rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ - bis->bi_phymode[0] = BI_PHYMODE_GMII; - bis->bi_phymode[1] = BI_PHYMODE_NONE; - bis->bi_phymode[2] = BI_PHYMODE_NONE; - bis->bi_phymode[3] = BI_PHYMODE_NONE; - } else { - rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */ - bis->bi_phymode[0] = BI_PHYMODE_NONE; - bis->bi_phymode[1] = BI_PHYMODE_GMII; - bis->bi_phymode[2] = BI_PHYMODE_NONE; - bis->bi_phymode[3] = BI_PHYMODE_NONE; - } - break; - case 8: - /* 2 GMII - 460GT */ - /* GMC0 EMAC4_0, RGMII Bridge 0 */ - /* GMC1 EMAC4_2, RGMII Bridge 1 */ - rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ - rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */ - rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ - rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */ - - bis->bi_phymode[0] = BI_PHYMODE_GMII; - bis->bi_phymode[1] = BI_PHYMODE_NONE; - bis->bi_phymode[2] = BI_PHYMODE_GMII; - bis->bi_phymode[3] = BI_PHYMODE_NONE; - break; - case 9: - /* 2 RGMII - 460EX */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ - rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); - rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); - rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ - - bis->bi_phymode[0] = BI_PHYMODE_RGMII; - bis->bi_phymode[1] = BI_PHYMODE_RGMII; - bis->bi_phymode[2] = BI_PHYMODE_NONE; - bis->bi_phymode[3] = BI_PHYMODE_NONE; - break; - case 10: - /* 4 RGMII - 460GT */ - /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ - /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */ - rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); - rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); - rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2); - rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3); - bis->bi_phymode[0] = BI_PHYMODE_RGMII; - bis->bi_phymode[1] = BI_PHYMODE_RGMII; - bis->bi_phymode[2] = BI_PHYMODE_RGMII; - bis->bi_phymode[3] = BI_PHYMODE_RGMII; - break; - default: - break; - } - - /* Set EMAC for MDIO */ - mfsdr(SDR0_ETH_CFG, eth_cfg); - eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; - mtsdr(SDR0_ETH_CFG, eth_cfg); - - out_be32((void *)RGMII_FER, rmiifer); -#if defined(CONFIG_460GT) - out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1); -#endif - - /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ - mfsdr(SDR0_ETH_CFG, eth_cfg); - eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); - mtsdr(SDR0_ETH_CFG, eth_cfg); - - return 0; -} -#endif /* CONFIG_460EX || CONFIG_460GT */ - -static inline void *malloc_aligned(u32 size, u32 align) -{ - return (void *)(((u32)malloc(size + align) + align - 1) & - ~(align - 1)); -} - static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) { - int i; + int i, j; unsigned long reg = 0; unsigned long msr; unsigned long speed; @@ -699,30 +332,17 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) unsigned mode_reg; unsigned short devnum; unsigned short reg_short; -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) sys_info_t sysinfo; -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) int ethgroup = -1; #endif #endif - u32 bd_cached; - u32 bd_uncached = 0; -#ifdef CONFIG_4xx_DCACHE - static u32 last_used_ea = 0; -#endif -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) - int rgmii_channel; +#if defined(CONFIG_440SPE) + unsigned long mfr; #endif + EMAC_4XX_HW_PST hw_p = dev->priv; /* before doing anything, figure out if we have a MAC address */ @@ -732,11 +352,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) return -1; } -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* Need to get the OPB frequency so we can access the PHY */ get_sys_info (&sysinfo); #endif @@ -786,47 +402,57 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* NOTE: Therefore, disable all other EMACS, since we handle */ /* NOTE: only one emac at a time */ reg = 0; - out_be32((void *)ZMII_FER, 0); + out32 (ZMII_FER, 0); udelay (100); -#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); -#elif defined(CONFIG_440GX) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) + out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); +#elif defined(CONFIG_440GX) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); +#elif defined(CONFIG_440GP) + /* set RMII mode */ + out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); +#else + if ((devnum == 0) || (devnum == 1)) { + out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); + } + else { /* ((devnum == 2) || (devnum == 3)) */ + out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); + out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | + (RGMII_FER_RGMII << RGMII_FER_V (3)))); + } #endif - out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); + out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ -#if defined(CONFIG_405EX) - ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); + + __asm__ volatile ("eieio"); + + /* reset emac so we have access to the phy */ +#if defined(CONFIG_440SPE) + /* provide clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr |= 0x08000000; + mtsdr(sdr_mfr, mfr); #endif - sync(); - - /* provide clocks for EMAC internal loopback */ - emac_loopback_enable(hw_p); - - /* EMAC RESET */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); - - /* remove clocks for EMAC internal loopback */ - emac_loopback_disable(hw_p); + out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + __asm__ volatile ("eieio"); failsafe = 1000; - while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { + while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { udelay (1000); failsafe--; } - if (failsafe <= 0) - printf("\nProblem resetting EMAC!\n"); -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) +#if defined(CONFIG_440SPE) + /* remove clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr &= ~0x08000000; + mtsdr(sdr_mfr, mfr); +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* Whack the M1 register */ mode_reg = 0x0; mode_reg &= ~0x00000038; @@ -840,7 +466,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) else mode_reg |= EMAC_M1_OBCI_GT100; - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ /* wait for PHY to complete auto negotiation */ @@ -855,12 +481,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = CONFIG_PHY1_ADDR; break; #endif -#if defined (CONFIG_PHY2_ADDR) +#if defined (CONFIG_440GX) case 2: reg = CONFIG_PHY2_ADDR; break; -#endif -#if defined (CONFIG_PHY3_ADDR) case 3: reg = CONFIG_PHY3_ADDR; break; @@ -878,26 +502,15 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) * otherwise, just check the speeds & feeds */ if (hw_p->first_init == 0) { -#if defined(CONFIG_M88E1111_PHY) - miiphy_write (dev->name, reg, 0x14, 0x0ce3); - miiphy_write (dev->name, reg, 0x18, 0x4101); - miiphy_write (dev->name, reg, 0x09, 0x0e00); - miiphy_write (dev->name, reg, 0x04, 0x01e1); -#endif miiphy_reset (dev->name, reg); -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) - +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) #if defined(CONFIG_CIS8201_PHY) /* * Cicada 8201 PHY needs to have an extended register whacked * for RGMII mode. */ - if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) { + if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) { #if defined(CONFIG_CIS8201_SHORT_ETCH) miiphy_write (dev->name, reg, 23, 0x1300); #else @@ -921,26 +534,6 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* end Vitesse/Cicada errata */ } #endif - -#if defined(CONFIG_ET1011C_PHY) - /* - * Agere ET1011c PHY needs to have an extended register whacked - * for RGMII mode. - */ - if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) { - miiphy_read (dev->name, reg, 0x16, ®_short); - reg_short &= ~(0x7); - reg_short |= 0x6; /* RGMII DLL Delay*/ - miiphy_write (dev->name, reg, 0x16, reg_short); - - miiphy_read (dev->name, reg, 0x17, ®_short); - reg_short &= ~(0x40); - miiphy_write (dev->name, reg, 0x17, reg_short); - - miiphy_write(dev->name, reg, 0x1c, 0x74f0); - } -#endif - #endif /* Start/Restart autonegotiation */ phy_setup_aneg (dev->name, reg); @@ -983,15 +576,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) if (hw_p->print_speed) { hw_p->print_speed = 0; - printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n", - (int) speed, (duplex == HALF) ? "HALF" : "FULL", - hw_p->devnum); + printf ("ENET Speed is %d Mbps - %s duplex connection\n", + (int) speed, (duplex == HALF) ? "HALF" : "FULL"); } -#if defined(CONFIG_440) && \ - !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ - !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ - !defined(CONFIG_460EX) && !defined(CONFIG_460GT) +#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) mfsdr(sdr_mfr, reg); if (speed == 100) { @@ -1003,58 +592,26 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif /* Set ZMII/RGMII speed according to the phy link speed */ - reg = in_be32((void *)ZMII_SSR); + reg = in32 (ZMII_SSR); if ( (speed == 100) || (speed == 1000) ) - out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); + out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); else - out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); + out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); if ((devnum == 2) || (devnum == 3)) { if (speed == 1000) reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); else if (speed == 100) reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); - else if (speed == 10) + else reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); - else { - printf("Error in RGMII Speed\n"); - return -1; - } - out_be32((void *)RGMII_SSR, reg); + + out32 (RGMII_SSR, reg); } #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) - if (devnum >= 2) - rgmii_channel = devnum - 2; - else - rgmii_channel = devnum; - - if (speed == 1000) - reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel)); - else if (speed == 100) - reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel)); - else if (speed == 10) - reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel)); - else { - printf("Error in RGMII Speed\n"); - return -1; - } - out_be32((void *)RGMII_SSR, reg); -#if defined(CONFIG_460GT) - if ((devnum == 2) || (devnum == 3)) - out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg); -#endif -#endif - /* set the Mal configuration reg */ -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); #else @@ -1065,67 +622,91 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #endif + /* Free "old" buffers */ + if (hw_p->alloc_tx_buf) + free (hw_p->alloc_tx_buf); + if (hw_p->alloc_rx_buf) + free (hw_p->alloc_rx_buf); + /* * Malloc MAL buffer desciptors, make sure they are * aligned on cache line boundary size * (401/403/IOP480 = 16, 405 = 32) * and doesn't cross cache block boundaries. */ - if (hw_p->first_init == 0) { - debug("*** Allocating descriptor memory ***\n"); + hw_p->alloc_tx_buf = + (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) + + ((2 * CFG_CACHELINE_SIZE) - 2)); + if (NULL == hw_p->alloc_tx_buf) + return -1; + if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) { + hw_p->tx = + (mal_desc_t *) ((int) hw_p->alloc_tx_buf + + CFG_CACHELINE_SIZE - + ((int) hw_p-> + alloc_tx_buf & CACHELINE_MASK)); + } else { + hw_p->tx = hw_p->alloc_tx_buf; + } - bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); - if (!bd_cached) { - printf("%s: Error allocating MAL descriptor buffers!\n", __func__); - return -1; - } + hw_p->alloc_rx_buf = + (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) + + ((2 * CFG_CACHELINE_SIZE) - 2)); + if (NULL == hw_p->alloc_rx_buf) { + free(hw_p->alloc_tx_buf); + hw_p->alloc_tx_buf = NULL; + return -1; + } -#ifdef CONFIG_4xx_DCACHE - flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); - if (!last_used_ea) -#if defined(CFG_MEM_TOP_HIDE) - bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE; -#else - bd_uncached = bis->bi_memsize; -#endif - else - bd_uncached = last_used_ea + MAL_ALLOC_SIZE; - - last_used_ea = bd_uncached; - program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, - TLB_WORD2_I_ENABLE); -#else - bd_uncached = bd_cached; -#endif - hw_p->tx_phys = bd_cached; - hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; - hw_p->tx = (mal_desc_t *)(bd_uncached); - hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE); - debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx); + if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) { + hw_p->rx = + (mal_desc_t *) ((int) hw_p->alloc_rx_buf + + CFG_CACHELINE_SIZE - + ((int) hw_p-> + alloc_rx_buf & CACHELINE_MASK)); + } else { + hw_p->rx = hw_p->alloc_rx_buf; } for (i = 0; i < NUM_TX_BUFF; i++) { hw_p->tx[i].ctrl = 0; hw_p->tx[i].data_len = 0; - if (hw_p->first_init == 0) - hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE, - L1_CACHE_BYTES); + if (hw_p->first_init == 0) { + hw_p->txbuf_ptr = + (char *) malloc (ENET_MAX_MTU_ALIGNED); + if (NULL == hw_p->txbuf_ptr) { + free(hw_p->alloc_rx_buf); + free(hw_p->alloc_tx_buf); + hw_p->alloc_rx_buf = NULL; + hw_p->alloc_tx_buf = NULL; + for(j = 0; j < i; j++) { + free(hw_p->tx[i].data_ptr); + hw_p->tx[i].data_ptr = NULL; + } + } + } hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; if ((NUM_TX_BUFF - 1) == i) hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; hw_p->tx_run[i] = -1; - debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr); +#if 0 + printf ("TX_BUFF %d @ 0x%08lx\n", i, + (ulong) hw_p->tx[i].data_ptr); +#endif } for (i = 0; i < NUM_RX_BUFF; i++) { hw_p->rx[i].ctrl = 0; hw_p->rx[i].data_len = 0; - hw_p->rx[i].data_ptr = (char *)NetRxPackets[i]; + /* rx[i].data_ptr = (char *) &rx_buff[i]; */ + hw_p->rx[i].data_ptr = (char *) NetRxPackets[i]; if ((NUM_RX_BUFF - 1) == i) hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; hw_p->rx_ready[i] = -1; - debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr); +#if 0 + printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr); +#endif } reg = 0x00000000; @@ -1134,7 +715,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = reg << 8; reg |= dev->enetaddr[1]; - out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg); + out32 (EMAC_IAH + hw_p->hw_addr, reg); reg = 0x00000000; reg |= dev->enetaddr[2]; /* set low address */ @@ -1145,71 +726,44 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = reg << 8; reg |= dev->enetaddr[5]; - out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg); + out32 (EMAC_IAL + hw_p->hw_addr, reg); switch (devnum) { case 1: /* setup MAL tx & rx channel pointers */ #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) - mtdcr (maltxctp2r, hw_p->tx_phys); + mtdcr (maltxctp2r, hw_p->tx); #else - mtdcr (maltxctp1r, hw_p->tx_phys); + mtdcr (maltxctp1r, hw_p->tx); #endif #if defined(CONFIG_440) mtdcr (maltxbattr, 0x0); mtdcr (malrxbattr, 0x0); #endif - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) - mtdcr (malrxctp8r, hw_p->rx_phys); - /* set RX buffer size */ - mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); -#else - mtdcr (malrxctp1r, hw_p->rx_phys); + mtdcr (malrxctp1r, hw_p->rx); /* set RX buffer size */ mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); -#endif break; #if defined (CONFIG_440GX) case 2: /* setup MAL tx & rx channel pointers */ mtdcr (maltxbattr, 0x0); mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx_phys); - mtdcr (malrxctp2r, hw_p->rx_phys); + mtdcr (maltxctp2r, hw_p->tx); + mtdcr (malrxctp2r, hw_p->rx); /* set RX buffer size */ mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); break; case 3: /* setup MAL tx & rx channel pointers */ mtdcr (maltxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx_phys); + mtdcr (maltxctp3r, hw_p->tx); mtdcr (malrxbattr, 0x0); - mtdcr (malrxctp3r, hw_p->rx_phys); + mtdcr (malrxctp3r, hw_p->rx); /* set RX buffer size */ mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); break; #endif /* CONFIG_440GX */ -#if defined (CONFIG_460GT) - case 2: - /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx_phys); - mtdcr (malrxctp16r, hw_p->rx_phys); - /* set RX buffer size */ - mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16); - break; - case 3: - /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx_phys); - mtdcr (malrxctp24r, hw_p->rx_phys); - /* set RX buffer size */ - mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16); - break; -#endif /* CONFIG_460GT */ case 0: default: /* setup MAL tx & rx channel pointers */ @@ -1217,8 +771,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtdcr (maltxbattr, 0x0); mtdcr (malrxbattr, 0x0); #endif - mtdcr (maltxctp0r, hw_p->tx_phys); - mtdcr (malrxctp0r, hw_p->rx_phys); + mtdcr (maltxctp0r, hw_p->tx); + mtdcr (malrxctp0r, hw_p->rx); /* set RX buffer size */ mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); break; @@ -1233,19 +787,16 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); /* set transmit enable & receive enable */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); + out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); - mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); - - /* set rx-/tx-fifo size */ - mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; + /* set receive fifo to 4k and tx fifo to 2k */ + mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); + mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; /* set speed */ if (speed == _1000BASET) { -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long pfc1; - mfsdr (sdr_pfc1, pfc1); pfc1 |= SDR0_PFC1_EM_1000; mtsdr (sdr_pfc1, pfc1); @@ -1258,46 +809,46 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) if (duplex == FULL) mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); /* Enable broadcast and indvidual address */ /* TBS: enabling runts as some misbehaved nics will send runts */ - out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); + out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); /* we probably need to set the tx mode1 reg? maybe at tx time */ /* set transmit request threshold register */ - out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ + out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ /* set receive low/high water mark register */ #if defined(CONFIG_440) /* 440s has a 64 byte burst length */ - out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); + out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); #else /* 405s have a 16 byte burst length */ - out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); + out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); #endif /* defined(CONFIG_440) */ - out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); + out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); /* Set fifo limit entry in tx mode 0 */ - out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003); + out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003); /* Frame gap set */ - out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); + out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); /* Set EMAC IER */ hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; if (speed == _100BASET) hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; - out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ - out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); + out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ + out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); if (hw_p->first_init == 0) { /* * Connect interrupt service routines */ - irq_install_handler(ETH_IRQ_NUM(hw_p->devnum), - (interrupt_handler_t *) enetInt, dev); + irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), + (interrupt_handler_t *) enetInt, dev); } mtmsr (msr); /* enable interrupts again */ @@ -1305,7 +856,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) hw_p->bis = bis; hw_p->first_init = 1; - return 0; + return (1); } @@ -1333,7 +884,6 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); - flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); /*-----------------------------------------------------------------------+ * set TX Buffer busy, and send it @@ -1347,10 +897,10 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, hw_p->tx[hw_p->tx_slot].data_len = (short) len; hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; - sync(); + __asm__ volatile ("eieio"); - out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, - in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); + out32 (EMAC_TXM0 + hw_p->hw_addr, + in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); #ifdef INFO_4XX_ENET hw_p->stats.pkts_tx++; #endif @@ -1360,7 +910,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, *-----------------------------------------------------------------------*/ time_start = get_timer (0); while (1) { - temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr); + temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); /* loop until either TINT turns on or 3 seconds elapse */ if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { /* transmit is done, so now check for errors @@ -1378,7 +928,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, } -#if defined (CONFIG_440) || defined(CONFIG_405EX) +#if defined (CONFIG_440) #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* @@ -1387,34 +937,9 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, */ #define UIC0MSR uic1msr #define UIC0SR uic1sr -#define UIC1MSR uic1msr -#define UIC1SR uic1sr -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) -/* - * Hack: On 460EX/GT all enet irq sources are located on UIC2 - * Needs some cleanup. --ag - */ -#define UIC0MSR uic2msr -#define UIC0SR uic2sr -#define UIC1MSR uic2msr -#define UIC1SR uic2sr #else #define UIC0MSR uic0msr #define UIC0SR uic0sr -#define UIC1MSR uic1msr -#define UIC1SR uic1sr -#endif - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) -#define UICMSR_ETHX uic0msr -#define UICSR_ETHX uic0sr -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UICMSR_ETHX uic2msr -#define UICSR_ETHX uic2sr -#else -#define UICMSR_ETHX uic1msr -#define UICSR_ETHX uic1sr #endif int enetInt (struct eth_device *dev) @@ -1425,7 +950,6 @@ int enetInt (struct eth_device *dev) unsigned long emac_isr = 0; unsigned long mal_rx_eob; unsigned long my_uic0msr, my_uic1msr; - unsigned long my_uicmsr_ethx; #if defined(CONFIG_440GX) unsigned long my_uic2msr; @@ -1449,15 +973,12 @@ int enetInt (struct eth_device *dev) serviced = 0; my_uic0msr = mfdcr (UIC0MSR); - my_uic1msr = mfdcr (UIC1MSR); + my_uic1msr = mfdcr (uic1msr); #if defined(CONFIG_440GX) my_uic2msr = mfdcr (uic2msr); #endif - my_uicmsr_ethx = mfdcr (UICMSR_ETHX); - if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) - && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) - && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) { + && !(my_uic1msr & (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE))) { /* not for us */ return (rc); } @@ -1476,7 +997,8 @@ int enetInt (struct eth_device *dev) mal_isr = mfdcr (malesr); /* look for mal error */ if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) { - mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR); + mal_err (dev, mal_isr, my_uic0msr, + MAL_UIC_DEF, MAL_UIC_ERR); serviced = 1; rc = 0; } @@ -1484,8 +1006,8 @@ int enetInt (struct eth_device *dev) /* port by port dispatch of emac interrupts */ if (hw_p->devnum == 0) { - if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); + if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */ + emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1495,16 +1017,15 @@ int enetInt (struct eth_device *dev) if ((hw_p->emac_ier & emac_isr) || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */ + mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ return (rc); /* we had errors so get out */ } } #if !defined(CONFIG_440SP) if (hw_p->devnum == 1) { - if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); + if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */ + emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1514,15 +1035,14 @@ int enetInt (struct eth_device *dev) if ((hw_p->emac_ier & emac_isr) || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ - mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */ + mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ return (rc); /* we had errors so get out */ } } #if defined (CONFIG_440GX) if (hw_p->devnum == 2) { if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); + emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1532,7 +1052,7 @@ int enetInt (struct eth_device *dev) if ((hw_p->emac_ier & emac_isr) || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ mtdcr (uic2sr, UIC_ETH2); return (rc); /* we had errors so get out */ } @@ -1540,7 +1060,7 @@ int enetInt (struct eth_device *dev) if (hw_p->devnum == 3) { if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); + emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1550,7 +1070,7 @@ int enetInt (struct eth_device *dev) if ((hw_p->emac_ier & emac_isr) || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */ - mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ mtdcr (uic2sr, UIC_ETH3); return (rc); /* we had errors so get out */ } @@ -1568,9 +1088,7 @@ int enetInt (struct eth_device *dev) /* check for EOB on valid channels */ if (my_uic0msr & UIC_MRE) { mal_rx_eob = mfdcr (malrxeobisr); - if ((mal_rx_eob & - (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) - != 0) { /* call emac routine for channel x */ + if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */ /* clear EOB mtdcr(malrxeobisr, mal_rx_eob); */ enet_rcv (dev, emac_isr); @@ -1581,13 +1099,13 @@ int enetInt (struct eth_device *dev) } mtdcr (UIC0SR, UIC_MRE); /* Clear */ - mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ + mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */ switch (hw_p->devnum) { case 0: - mtdcr (UICSR_ETHX, UIC_ETH0); + mtdcr (uic1sr, UIC_ETH0); break; case 1: - mtdcr (UICSR_ETHX, UIC_ETH1); + mtdcr (uic1sr, UIC_ETH1); break; #if defined (CONFIG_440GX) case 2: @@ -1654,7 +1172,7 @@ int enetInt (struct eth_device *dev) /* port by port dispatch of emac interrupts */ if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); + emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1687,9 +1205,6 @@ int enetInt (struct eth_device *dev) } } mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ -#if defined(CONFIG_405EZ) - mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); -#endif /* defined(CONFIG_405EZ) */ } while (serviced); @@ -1728,7 +1243,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr) EMAC_4XX_HW_PST hw_p = dev->priv; printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); - out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr); + out32 (EMAC_ISR + hw_p->hw_addr, isr); } /*-----------------------------------------------------------------------------+ @@ -1746,7 +1261,7 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr) int loop_count = 0; rx_eob_isr = mfdcr (malrxeobisr); - if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { + if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) { /* clear EOB */ mtdcr (malrxeobisr, rx_eob_isr); @@ -1757,10 +1272,12 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr) if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) || (loop_count >= NUM_RX_BUFF)) break; - loop_count++; + hw_p->rx_slot++; + if (NUM_RX_BUFF == hw_p->rx_slot) + hw_p->rx_slot = 0; handled++; - data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */ + data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */ if (data_len) { if (data_len > ENET_MAX_MTU) /* Check len */ data_len = 0; @@ -1808,10 +1325,6 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr) if (NUM_RX_BUFF == hw_p->rx_i_index) hw_p->rx_i_index = 0; - hw_p->rx_slot++; - if (NUM_RX_BUFF == hw_p->rx_slot) - hw_p->rx_slot = 0; - /* AS.HARNOIS * free receive buffer only when * buffer has been handled (eth_rx) @@ -1846,14 +1359,11 @@ static int ppc_4xx_eth_rx (struct eth_device *dev) msr = mfmsr (); mtmsr (msr & ~(MSR_EE)); - length = hw_p->rx[user_index].data_len & 0x0fff; + length = hw_p->rx[user_index].data_len; /* Pass the packet up to the protocol layers. */ /* NetReceive(NetRxPackets[rxIdx], length - 4); */ /* NetReceive(NetRxPackets[i], length); */ - invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, - (u32)hw_p->rx[user_index].data_ptr + - length - 4); NetReceive (NetRxPackets[user_index], length - 4); /* Free Recv Buffer */ hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; @@ -1881,8 +1391,6 @@ int ppc_4xx_eth_initialize (bd_t * bis) struct eth_device *dev; int eth_num = 0; EMAC_4XX_HW_PST hw = NULL; - u8 ethaddr[4 + CONFIG_EMAC_NR_START][6]; - u32 hw_addr[4]; #if defined(CONFIG_440GX) unsigned long pfc1; @@ -1892,51 +1400,6 @@ int ppc_4xx_eth_initialize (bd_t * bis) pfc1 |= 0x01200000; mtsdr (sdr_pfc1, pfc1); #endif - - /* first clear all mac-addresses */ - for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) - memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6); - - for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { - switch (eth_num) { - default: /* fall through */ - case 0: - memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], - bis->bi_enetaddr, 6); - hw_addr[eth_num] = 0x0; - break; -#ifdef CONFIG_HAS_ETH1 - case 1: - memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], - bis->bi_enet1addr, 6); - hw_addr[eth_num] = 0x100; - break; -#endif -#ifdef CONFIG_HAS_ETH2 - case 2: - memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], - bis->bi_enet2addr, 6); -#if defined(CONFIG_460GT) - hw_addr[eth_num] = 0x300; -#else - hw_addr[eth_num] = 0x400; -#endif - break; -#endif -#ifdef CONFIG_HAS_ETH3 - case 3: - memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START], - bis->bi_enet3addr, 6); -#if defined(CONFIG_460GT) - hw_addr[eth_num] = 0x400; -#else - hw_addr[eth_num] = 0x600; -#endif - break; -#endif - } - } - /* set phy num and mode */ bis->bi_phynum[0] = CONFIG_PHY_ADDR; bis->bi_phymode[0] = 0; @@ -1950,22 +1413,45 @@ int ppc_4xx_eth_initialize (bd_t * bis) bis->bi_phynum[3] = CONFIG_PHY3_ADDR; bis->bi_phymode[2] = 2; bis->bi_phymode[3] = 2; -#endif -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) ppc_4xx_eth_setup_bridge(0, bis); #endif for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { - /* - * See if we can actually bring up the interface, - * otherwise, skip it - */ - if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) { - bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; - continue; + + /* See if we can actually bring up the interface, otherwise, skip it */ + switch (eth_num) { + default: /* fall through */ + case 0: + if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; + continue; + } + break; +#ifdef CONFIG_HAS_ETH1 + case 1: + if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; + continue; + } + break; +#endif +#ifdef CONFIG_HAS_ETH2 + case 2: + if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; + continue; + } + break; +#endif +#ifdef CONFIG_HAS_ETH3 + case 3: + if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) { + bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; + continue; + } + break; +#endif } /* Allocate device structure */ @@ -1988,12 +1474,36 @@ int ppc_4xx_eth_initialize (bd_t * bis) } memset(hw, 0, sizeof(*hw)); - hw->hw_addr = hw_addr[eth_num]; - memcpy (dev->enetaddr, ethaddr[eth_num], 6); + switch (eth_num) { + default: /* fall through */ + case 0: + hw->hw_addr = 0; + memcpy (dev->enetaddr, bis->bi_enetaddr, 6); + break; +#ifdef CONFIG_HAS_ETH1 + case 1: + hw->hw_addr = 0x100; + memcpy (dev->enetaddr, bis->bi_enet1addr, 6); + break; +#endif +#ifdef CONFIG_HAS_ETH2 + case 2: + hw->hw_addr = 0x400; + memcpy (dev->enetaddr, bis->bi_enet2addr, 6); + break; +#endif +#ifdef CONFIG_HAS_ETH3 + case 3: + hw->hw_addr = 0x600; + memcpy (dev->enetaddr, bis->bi_enet3addr, 6); + break; +#endif + } + hw->devnum = eth_num; hw->print_speed = 1; - sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START); + sprintf (dev->name, "ppc_4xx_eth%d", eth_num); dev->priv = (void *) hw; dev->init = ppc_4xx_eth_init; dev->halt = ppc_4xx_eth_halt; @@ -2002,10 +1512,7 @@ int ppc_4xx_eth_initialize (bd_t * bis) if (0 == virgin) { /* set the MAL IER ??? names may change with new spec ??? */ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) +#if defined(CONFIG_440SPE) mal_ier = MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; @@ -2045,16 +1552,16 @@ int ppc_4xx_eth_initialize (bd_t * bis) #endif #if defined(CONFIG_NET_MULTI) -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register (dev->name, emac4xx_miiphy_read, emac4xx_miiphy_write); #endif #endif } /* end for each supported device */ - - return 0; + return (1); } + #if !defined(CONFIG_NET_MULTI) void eth_halt (void) { if (emac0_dev) { @@ -2087,7 +1594,7 @@ int eth_rx(void) int emac4xx_miiphy_initialize (bd_t * bis) { -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_register ("ppc_4xx_eth0", emac4xx_miiphy_read, emac4xx_miiphy_write); #endif @@ -2096,4 +1603,4 @@ int emac4xx_miiphy_initialize (bd_t * bis) } #endif /* !defined(CONFIG_NET_MULTI) */ -#endif +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_NET) */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 800bb41d0..c56345700 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,58 +23,28 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a -START := resetvec.o -START += start.o +START = start.o resetvec.o kgdb.o +AOBJS = dcr.o +COBJS = 405gp_pci.o 4xx_enet.o \ + bedbug_405.o commproc.o \ + cpu.o cpu_init.o i2c.o interrupts.o \ + miiphy.o sdram.o serial.o \ + spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o -SOBJS := cache.o -SOBJS += dcr.o -SOBJS += kgdb.o +OBJS = $(AOBJS) $(COBJS) -COBJS := 40x_spd_sdram.o -COBJS += 44x_spd_ddr.o -COBJS += 44x_spd_ddr2.o -COBJS += 4xx_enet.o -COBJS += 4xx_pci.o -COBJS += 4xx_pcie.o -COBJS += 4xx_uart.o -COBJS += bedbug_405.o -COBJS += commproc.o -COBJS += cpu.o -COBJS += cpu_init.o -COBJS += denali_data_eye.o -COBJS += denali_spd_ddr2.o -COBJS += ecc.o -COBJS += fdt.o -COBJS += gpio.o -COBJS += i2c.o -COBJS += interrupts.o -COBJS += iop480_uart.o -COBJS += miiphy.o -COBJS += ndfc.o -COBJS += sdram.o -COBJS += speed.o -COBJS += tlb.o -COBJS += traps.o -COBJS += usb.o -COBJS += usb_ohci.o -COBJS += usbdev.o - -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c index 5ef560791..a3c211976 100644 --- a/cpu/ppc4xx/bedbug_405.c +++ b/cpu/ppc4xx/bedbug_405.c @@ -10,7 +10,7 @@ #include #include -#if defined(CONFIG_CMD_BEDBUG) && defined(CONFIG_4xx) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_4xx) #define MAX_BREAK_POINTS 4 diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c index 8b2954c16..68aab5b7e 100644 --- a/cpu/ppc4xx/commproc.c +++ b/cpu/ppc4xx/commproc.c @@ -26,28 +26,20 @@ #include #include -#include + #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) -#if defined(CFG_POST_WORD_ADDR) -# define _POST_ADDR ((CFG_OCM_DATA_ADDR) + (CFG_POST_WORD_ADDR)) -#elif defined(CFG_POST_ALT_WORD_ADDR) -# define _POST_ADDR (CFG_POST_ALT_WORD_ADDR) -#endif - void post_word_store (ulong a) { - volatile void *save_addr = (volatile void *)(_POST_ADDR); - - out_be32(save_addr, a); + volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); + *(volatile ulong *) save_addr = a; } ulong post_word_load (void) { - volatile void *save_addr = (volatile void *)(_POST_ADDR); - - return in_be32(save_addr); + volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); + return *(volatile ulong *) save_addr; } #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk index baa97a412..119e061b8 100644 --- a/cpu/ppc4xx/config.mk +++ b/cpu/ppc4xx/config.mk @@ -22,13 +22,5 @@ # PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float -cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') -is440:=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg)) - -ifneq (,$(findstring CONFIG_440,$(is440))) -PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 -else -PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405 -endif +PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m405 -mcpu=405 -msoft-float diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 39f439df9..71303bcc4 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2007 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -37,25 +37,28 @@ #include #include +#if !defined(CONFIG_405) DECLARE_GLOBAL_DATA_PTR; +#endif -void board_reset(void); -#if defined(CONFIG_405GP) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440) +#define FREQ_EBC (sys_info.freqEPB) +#else +#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) +#endif + +#if defined(CONFIG_405GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) #define PCI_ASYNC -static int pci_async_enabled(void) +int pci_async_enabled(void) { #if defined(CONFIG_405GP) return (mfdcr(strap) & PSR_PCI_ASYNC_EN); #endif -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) unsigned long val; mfsdr(sdr_sdstp1, val); @@ -64,9 +67,8 @@ static int pci_async_enabled(void) } #endif -#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ - !defined(CONFIG_405) && !defined(CONFIG_405EX) -static int pci_arbiter_enabled(void) +#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405) +int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) return (mfdcr(strap) & PSR_PCI_ARBIT_EN); @@ -80,31 +82,31 @@ static int pci_arbiter_enabled(void) return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); #endif -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) unsigned long val; - mfsdr(sdr_xcr, val); - return (val & 0x80000000); -#endif -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) - unsigned long val; - - mfsdr(sdr_pci0, val); - return (val & 0x80000000); + mfsdr(sdr_sdstp1, val); + return (val & SDR0_SDSTP1_PAE_MASK); #endif } #endif -#if defined(CONFIG_405EP) +#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) + #define I2C_BOOTROM -static int i2c_bootrom_enabled(void) +int i2c_bootrom_enabled(void) { #if defined(CONFIG_405EP) return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); -#else +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) unsigned long val; mfsdr(sdr_sdcs, val); @@ -113,141 +115,9 @@ static int i2c_bootrom_enabled(void) } #endif -#if defined(CONFIG_440GX) -#define SDR0_PINSTP_SHIFT 29 -static char *bootstrap_str[] = { - "EBC (16 bits)", - "EBC (8 bits)", - "EBC (32 bits)", - "EBC (8 bits)", - "PCI", - "I2C (Addr 0x54)", - "Reserved", - "I2C (Addr 0x50)", -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' }; -#endif - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define SDR0_PINSTP_SHIFT 30 -static char *bootstrap_str[] = { - "EBC (8 bits)", - "PCI", - "I2C (Addr 0x54)", - "I2C (Addr 0x50)", -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'D'}; -#endif - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define SDR0_PINSTP_SHIFT 29 -static char *bootstrap_str[] = { - "EBC (8 bits)", - "PCI", - "NAND (8 bits)", - "EBC (16 bits)", - "EBC (16 bits)", - "I2C (Addr 0x54)", - "PCI", - "I2C (Addr 0x52)", -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; -#endif - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define SDR0_PINSTP_SHIFT 29 -static char *bootstrap_str[] = { - "EBC (8 bits)", - "EBC (16 bits)", - "EBC (16 bits)", - "NAND (8 bits)", - "PCI", - "I2C (Addr 0x54)", - "PCI", - "I2C (Addr 0x52)", -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; -#endif - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define SDR0_PINSTP_SHIFT 29 -static char *bootstrap_str[] = { - "EBC (8 bits)", - "EBC (16 bits)", - "PCI", - "PCI", - "EBC (16 bits)", - "NAND (8 bits)", - "I2C (Addr 0x54)", /* A8 */ - "I2C (Addr 0x52)", /* A4 */ -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; -#endif - -#if defined(CONFIG_405EZ) -#define SDR0_PINSTP_SHIFT 28 -static char *bootstrap_str[] = { - "EBC (8 bits)", - "SPI (fast)", - "NAND (512 page, 4 addr cycle)", - "I2C (Addr 0x50)", - "EBC (32 bits)", - "I2C (Addr 0x50)", - "NAND (2K page, 5 addr cycle)", - "I2C (Addr 0x50)", - "EBC (16 bits)", - "Reserved", - "NAND (2K page, 4 addr cycle)", - "I2C (Addr 0x50)", - "NAND (512 page, 3 addr cycle)", - "I2C (Addr 0x50)", - "SPI (slow)", - "I2C (Addr 0x50)", -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \ - 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' }; -#endif - -#if defined(CONFIG_405EX) -#define SDR0_PINSTP_SHIFT 29 -static char *bootstrap_str[] = { - "EBC (8 bits)", - "EBC (16 bits)", - "EBC (16 bits)", - "NAND (8 bits)", - "NAND (8 bits)", - "I2C (Addr 0x54)", - "EBC (8 bits)", - "I2C (Addr 0x52)", -}; -static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; -#endif - -#if defined(SDR0_PINSTP_SHIFT) -static int bootstrap_option(void) -{ - unsigned long val; - - mfsdr(SDR_PINSTP, val); - return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT); -} -#endif /* SDR0_PINSTP_SHIFT */ - #if defined(CONFIG_440) -static int do_chip_reset (unsigned long sys0, unsigned long sys1) -{ - /* Changes to cpc0_sys0 and cpc0_sys1 require chip - * reset. - */ - mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ - mtdcr (cpc0_sys0, sys0); - mtdcr (cpc0_sys1, sys1); - mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ - mtspr (dbcr0, 0x20000000); /* Reset the chip */ - - return 1; -} +static int do_chip_reset(unsigned long sys0, unsigned long sys1); #endif @@ -259,7 +129,6 @@ int checkcpu (void) char buf[32]; #if !defined(CONFIG_IOP480) - char addstr[64] = ""; sys_info_t sys_info; puts ("CPU: "); @@ -268,17 +137,11 @@ int checkcpu (void) puts("AMCC PowerPC 4"); -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) puts("05"); #endif #if defined(CONFIG_440) -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) - puts("60"); -#else puts("40"); -#endif #endif switch (pvr) { @@ -322,50 +185,6 @@ int checkcpu (void) puts("EP Rev. B"); break; - case PVR_405EZ_RA: - puts("EZ Rev. A"); - break; - - case PVR_405EX1_RA: - puts("EX Rev. A"); - strcpy(addstr, "Security support"); - break; - - case PVR_405EX2_RA: - puts("EX Rev. A"); - strcpy(addstr, "No Security support"); - break; - - case PVR_405EXR1_RA: - puts("EXr Rev. A"); - strcpy(addstr, "Security support"); - break; - - case PVR_405EXR2_RA: - puts("EXr Rev. A"); - strcpy(addstr, "No Security support"); - break; - - case PVR_405EX1_RC: - puts("EX Rev. C"); - strcpy(addstr, "Security support"); - break; - - case PVR_405EX2_RC: - puts("EX Rev. C"); - strcpy(addstr, "No Security support"); - break; - - case PVR_405EXR1_RC: - puts("EXr Rev. C"); - strcpy(addstr, "Security support"); - break; - - case PVR_405EXR2_RC: - puts("EXr Rev. C"); - strcpy(addstr, "No Security support"); - break; - #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); @@ -425,88 +244,20 @@ int checkcpu (void) #endif /* CONFIG_440GR */ #endif /* CONFIG_440 */ -#ifdef CONFIG_440EPX - case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("EPx Rev. A"); - strcpy(addstr, "Security/Kasumi support"); + case PVR_440SP_RA: + puts("SP Rev. A"); break; - case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("EPx Rev. A"); - strcpy(addstr, "No Security/Kasumi support"); - break; -#endif /* CONFIG_440EPX */ - -#ifdef CONFIG_440GRX - case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("GRx Rev. A"); - strcpy(addstr, "Security/Kasumi support"); - break; - - case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("GRx Rev. A"); - strcpy(addstr, "No Security/Kasumi support"); - break; -#endif /* CONFIG_440GRX */ - - case PVR_440SP_6_RAB: - puts("SP Rev. A/B"); - strcpy(addstr, "RAID 6 support"); - break; - - case PVR_440SP_RAB: - puts("SP Rev. A/B"); - strcpy(addstr, "No RAID 6 support"); - break; - - case PVR_440SP_6_RC: - puts("SP Rev. C"); - strcpy(addstr, "RAID 6 support"); - break; - - case PVR_440SP_RC: - puts("SP Rev. C"); - strcpy(addstr, "No RAID 6 support"); - break; - - case PVR_440SPe_6_RA: - puts("SPe Rev. A"); - strcpy(addstr, "RAID 6 support"); + case PVR_440SP_RB: + puts("SP Rev. B"); break; case PVR_440SPe_RA: puts("SPe Rev. A"); - strcpy(addstr, "No RAID 6 support"); - break; - - case PVR_440SPe_6_RB: - puts("SPe Rev. B"); - strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RB: puts("SPe Rev. B"); - strcpy(addstr, "No RAID 6 support"); - break; - - case PVR_460EX_RA: - puts("EX Rev. A"); - strcpy(addstr, "No Security/Kasumi support"); - break; - - case PVR_460EX_SE_RA: - puts("EX Rev. A"); - strcpy(addstr, "Security/Kasumi support"); - break; - - case PVR_460GT_RA: - puts("GT Rev. A"); - strcpy(addstr, "No Security/Kasumi support"); - break; - - case PVR_460GT_SE_RA: - puts("GT Rev. A"); - strcpy(addstr, "Security/Kasumi support"); break; default: @@ -515,22 +266,15 @@ int checkcpu (void) } printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), - sys_info.freqPLB / 1000000, - get_OPB_freq() / 1000000, - sys_info.freqEBC / 1000000); - - if (addstr[0] != 0) - printf(" %s\n", addstr); + sys_info.freqPLB / 1000000, + sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, + FREQ_EBC / 1000000); #if defined(I2C_BOOTROM) printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); -#endif /* I2C_BOOTROM */ -#if defined(SDR0_PINSTP_SHIFT) - printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]); - printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); -#endif /* SDR0_PINSTP_SHIFT */ +#endif -#if defined(CONFIG_PCI) && !defined(CONFIG_405EX) +#if defined(CONFIG_PCI) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); #endif @@ -543,11 +287,11 @@ int checkcpu (void) } #endif -#if defined(CONFIG_PCI) && !defined(CONFIG_405EX) +#if defined(CONFIG_PCI) putc('\n'); #endif -#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) +#if defined(CONFIG_405EP) printf (" 16 kB I-Cache 16 kB D-Cache"); #elif defined(CONFIG_440) printf (" 32 kB I-Cache 32 kB D-Cache"); @@ -571,35 +315,46 @@ int checkcpu (void) return 0; } -int ppc440spe_revB() { - unsigned int pvr; - - pvr = get_pvr(); - if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB)) - return 1; - else - return 0; -} /* ------------------------------------------------------------------------- */ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if defined(CONFIG_BOARD_RESET) - board_reset(); -#else -#if defined(CFG_4xx_RESET_TYPE) - mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); +#if defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE) + /*give reset to BCSR*/ + *(unsigned char*)(CFG_BCSR_BASE | 0x06) = 0x09; + #else + /* * Initiate system reset in debug control register DBCR */ - mtspr(dbcr0, 0x30000000); -#endif /* defined(CFG_4xx_RESET_TYPE) */ -#endif /* defined(CONFIG_BOARD_RESET) */ + __asm__ __volatile__("lis 3, 0x3000" ::: "r3"); +#if defined(CONFIG_440) + __asm__ __volatile__("mtspr 0x134, 3"); +#else + __asm__ __volatile__("mtspr 0x3f2, 3"); +#endif + +#endif/* defined(CONFIG_YOSEMITE) || defined(CONFIG_YELLOWSTONE)*/ + return 1; +} + +#if defined(CONFIG_440) +static int do_chip_reset (unsigned long sys0, unsigned long sys1) +{ + /* Changes to cpc0_sys0 and cpc0_sys1 require chip + * reset. + */ + mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ + mtdcr (cpc0_sys0, sys0); + mtdcr (cpc0_sys1, sys1); + mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ + mtspr (dbcr0, 0x20000000); /* Reset the chip */ return 1; } +#endif /* @@ -620,14 +375,16 @@ unsigned long get_tbclk (void) #if defined(CONFIG_WATCHDOG) -void watchdog_reset(void) +void +watchdog_reset(void) { int re_enable = disable_interrupts(); reset_4xx_watchdog(); if (re_enable) enable_interrupts(); } -void reset_4xx_watchdog(void) +void +reset_4xx_watchdog(void) { /* * Clear TSR(WIS) bit diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index ac6427905..b27567fa4 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2007 + * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -25,179 +25,238 @@ #include #include #include -#include #include #if defined(CONFIG_405GP) || defined(CONFIG_405EP) DECLARE_GLOBAL_DATA_PTR; #endif -#ifndef CFG_PLL_RECONFIG -#define CFG_PLL_RECONFIG 0 -#endif -void reconfigure_pll(u32 new_cpu_freq) +#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) + +#ifdef CFG_INIT_DCACHE_CS +# if (CFG_INIT_DCACHE_CS == 0) +# define PBxAP pb0ap +# define PBxCR pb0cr +# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +# define PBxAP_VAL CFG_EBC_PB0AP +# define PBxCR_VAL CFG_EBC_PB0CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 1) +# define PBxAP pb1ap +# define PBxCR pb1cr +# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) +# define PBxAP_VAL CFG_EBC_PB1AP +# define PBxCR_VAL CFG_EBC_PB1CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 2) +# define PBxAP pb2ap +# define PBxCR pb2cr +# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) +# define PBxAP_VAL CFG_EBC_PB2AP +# define PBxCR_VAL CFG_EBC_PB2CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 3) +# define PBxAP pb3ap +# define PBxCR pb3cr +# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) +# define PBxAP_VAL CFG_EBC_PB3AP +# define PBxCR_VAL CFG_EBC_PB3CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 4) +# define PBxAP pb4ap +# define PBxCR pb4cr +# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) +# define PBxAP_VAL CFG_EBC_PB4AP +# define PBxCR_VAL CFG_EBC_PB4CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 5) +# define PBxAP pb5ap +# define PBxCR pb5cr +# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) +# define PBxAP_VAL CFG_EBC_PB5AP +# define PBxCR_VAL CFG_EBC_PB5CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 6) +# define PBxAP pb6ap +# define PBxCR pb6cr +# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) +# define PBxAP_VAL CFG_EBC_PB6AP +# define PBxCR_VAL CFG_EBC_PB6CR +# endif +# endif +# if (CFG_INIT_DCACHE_CS == 7) +# define PBxAP pb7ap +# define PBxCR pb7cr +# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) +# define PBxAP_VAL CFG_EBC_PB7AP +# define PBxCR_VAL CFG_EBC_PB7CR +# endif +# endif +#endif /* CFG_INIT_DCACHE_CS */ + +#if defined(CFG_440_GPIO_TABLE) +gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE; + +void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX]) { -#if defined(CONFIG_440EPX) - int reset_needed = 0; - u32 reg, temp; - u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */ - fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */ - fbdv, target_fbdv, lfbdv, target_lfbdv, - perdv0, target_perdv0, /* CLK_PERD */ - spcid0, target_spcid0; /* CLK_SPCID */ + unsigned char i=0, j=0, reg_offset = 0, gpio_core; + unsigned long gpio_reg, gpio_core_add; - /* Reconfigure clocks if necessary. - * See PPC440EPx User's Manual, sections 8.2 and 14 */ - if (new_cpu_freq == 667) { - target_prbdv0 = 2; - target_fwdva = 2; - target_fwdvb = 4; - target_fbdv = 20; - target_lfbdv = 1; - target_perdv0 = 4; - target_spcid0 = 4; + for (gpio_core=0; gpio_core> 24; - prbdv0 = temp ? temp : 8; - if (prbdv0 != target_prbdv0) { - reg &= ~PRBDV_MASK; - reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); - mtcpr(clk_primbd, reg); - reset_needed = 1; + gpio_core_add = (*gpio_tab)[gpio_core][i].add; + + if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) || + ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) { + + switch ((*gpio_tab)[gpio_core][i].alt_nb) { + case GPIO_SEL: + break; + + case GPIO_ALT1: + gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT2: + gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT3: + gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); + break; + } + } + + if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) || + ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) { + + switch ((*gpio_tab)[gpio_core][i].alt_nb) { + case GPIO_SEL: + if (gpio_core == GPIO0) { + gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j)); + out32(GPIO0_TCR, gpio_reg); + } + + if (gpio_core == GPIO1) { + gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j)); + out32(GPIO1_TCR, gpio_reg); + } + + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT1: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT2: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT3: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) + & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + } + } } - - mfcpr(clk_plld, reg); - - temp = (reg & PLLD_FWDVA_MASK) >> 16; - fwdva = temp ? temp : 16; - - temp = (reg & PLLD_FWDVB_MASK) >> 8; - fwdvb = temp ? temp : 8; - - temp = (reg & PLLD_FBDV_MASK) >> 24; - fbdv = temp ? temp : 32; - - temp = (reg & PLLD_LFBDV_MASK); - lfbdv = temp ? temp : 64; - - if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) { - reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK | - PLLD_FBDV_MASK | PLLD_LFBDV_MASK); - reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) | - ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | - ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | - (target_lfbdv == 64 ? 0 : target_lfbdv); - mtcpr(clk_plld, reg); - reset_needed = 1; - } - - mfcpr(clk_perd, reg); - perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; - if (perdv0 != target_perdv0) { - reg &= ~CPR0_PERD_PERDV0_MASK; - reg |= (target_perdv0 << 24); - mtcpr(clk_perd, reg); - reset_needed = 1; - } - - mfcpr(clk_spcid, reg); - temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; - spcid0 = temp ? temp : 4; - if (spcid0 != target_spcid0) { - reg &= ~CPR0_SPCID_SPCIDV0_MASK; - reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); - mtcpr(clk_spcid, reg); - reset_needed = 1; - } - - /* Set reload inhibit so configuration will persist across - * processor resets */ - mfcpr(clk_icfg, reg); - reg &= ~CPR0_ICFG_RLI_MASK; - reg |= 1 << 31; - mtcpr(clk_icfg, reg); } - - /* Reset processor if configuration changed */ - if (reset_needed) { - __asm__ __volatile__ ("sync; isync"); - mtspr(dbcr0, 0x20000000); - } -#endif } +#endif /* CFG_440_GPIO_TABLE */ /* * Breath some life into the CPU... * - * Reconfigure PLL if necessary, - * set up the memory map, + * Set up the memory map, * initialize a bunch of registers */ void cpu_init_f (void) { -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_460EX) - u32 val; -#endif - reconfigure_pll(CFG_PLL_RECONFIG); - -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE) +#if defined(CONFIG_405EP) /* * GPIO0 setup (select GPIO or alternate function) */ -#if defined(CFG_GPIO0_OR) - out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */ -#endif -#if defined(CFG_GPIO0_ODR) - out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */ -#endif - out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ + out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ out32(GPIO0_OSRL, CFG_GPIO0_OSRL); - out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ + out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); - out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ out32(GPIO0_TSRL, CFG_GPIO0_TSRL); -#if defined(CFG_GPIO0_ISR2H) - out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H); - out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L); -#endif -#if defined (CFG_GPIO0_TCR) - out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ -#endif -#endif /* CONFIG_405EP ... && !CFG_4xx_GPIO_TABLE */ + out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ -#if defined (CONFIG_405EP) /* * Set EMAC noise filter bits */ mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); - - /* - * Enable the internal PCI arbiter - */ - mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ -#if defined(CFG_4xx_GPIO_TABLE) - gpio_set_chip_configuration(); -#endif /* CFG_4xx_GPIO_TABLE */ +#if defined(CFG_440_GPIO_TABLE) + set_chip_gpio_configuration(&gpio_tab); +#endif /* CFG_440_GPIO_TABLE */ /* * External Bus Controller (EBC) Setup */ #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || defined(CONFIG_405)) + defined(CONFIG_405EP) || defined(CONFIG_405)) /* * Move the next instructions into icache, since these modify the flash * we are running from! */ asm volatile(" bl 0f" ::: "lr"); asm volatile("0: mflr 3" ::: "r3"); - asm volatile(" addi 4, 0, 14" ::: "r4"); + asm volatile(" addi 4, 0, 14" ::: "r4"); asm volatile(" mtctr 4" ::: "ctr"); asm volatile("1: icbt 0, 3"); asm volatile(" addi 3, 3, 32" ::: "r3"); @@ -247,22 +306,14 @@ cpu_init_f (void) mtebc(pb7cr, CFG_EBC_PB7CR); #endif -#if defined (CFG_EBC_CFG) - mtebc(EBC0_CFG, CFG_EBC_CFG); -#endif - #if defined(CONFIG_WATCHDOG) + unsigned long val; + val = mfspr(tcr); #if defined(CONFIG_440EP) || defined(CONFIG_440GR) val |= 0xb8000000; /* generate system reset after 1.34 seconds */ -#elif defined(CONFIG_440EPX) - val |= 0xb0000000; /* generate system reset after 1.34 seconds */ #else val |= 0xf0000000; /* generate system reset after 2.684 seconds */ -#endif -#if defined(CFG_4xx_RESET_TYPE) - val &= ~0x30000000; /* clear WRC bits */ - val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */ #endif mtspr(tcr, val); @@ -272,22 +323,6 @@ cpu_init_f (void) reset_4xx_watchdog(); #endif /* CONFIG_WATCHDOG */ - -#if defined(CONFIG_460EX) - /* - * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and - * clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata - * regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA - */ - mfsdr(SDR0_AHB_CFG, val); - val |= 0x80; - val &= ~0x40; - mtsdr(SDR0_AHB_CFG, val); - mfsdr(SDR0_USB2HOST_CFG, val); - val &= ~0xf00; - val |= 0x400; - mtsdr(SDR0_USB2HOST_CFG, val); -#endif /* CONFIG_460EX */ } /* @@ -302,6 +337,24 @@ int cpu_init_r (void) uint pvr = get_pvr(); #endif +#ifdef CFG_INIT_DCACHE_CS + /* + * Flush and invalidate dcache, then disable CS for temporary stack. + * Afterwards, this CS can be used for other purposes + */ + dcache_disable(); /* flush and invalidate dcache */ + mtebc(PBxAP, 0); + mtebc(PBxCR, 0); /* disable CS for temporary stack */ + +#if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) + /* + * Write new value into CS register + */ + mtebc(PBxAP, PBxAP_VAL); + mtebc(PBxCR, PBxCR_VAL); +#endif +#endif /* CFG_INIT_DCACHE_CS */ + /* * Write Ethernetaddress into on-chip register */ @@ -331,6 +384,5 @@ int cpu_init_r (void) } #endif /* defined(CONFIG_405GP) */ #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ - return (0); } diff --git a/cpu/ppc4xx/dcr.S b/cpu/ppc4xx/dcr.S index 93465a3b5..7102364eb 100644 --- a/cpu/ppc4xx/dcr.S +++ b/cpu/ppc4xx/dcr.S @@ -22,7 +22,7 @@ */ #include -#if defined(CONFIG_4xx) && defined(CONFIG_CMD_SETGETDCR) +#if defined(CONFIG_4xx) && defined(CFG_CMD_SETGETDCR) #include @@ -195,4 +195,4 @@ set_dcr: blr /* Return to calling function */ .Lfe4: .size set_dcr,.Lfe4-set_dcr /* end set_dcr() */ -#endif +#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c index d8be2cef1..7db1cd804 100644 --- a/cpu/ppc4xx/i2c.c +++ b/cpu/ppc4xx/i2c.c @@ -1,99 +1,91 @@ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * based on work by Anne Sophie Harnois - * - * (C) Copyright 2001 - * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ +/*****************************************************************************/ +/* I2C Bus interface initialisation and I2C Commands */ +/* for PPC405GP */ +/* Author : AS HARNOIS */ +/* Date : 13.Dec.00 */ +/*****************************************************************************/ #include #include -#include <4xx_i2c.h> +#if defined(CONFIG_440) +# include <440_i2c.h> +#else +# include <405gp_i2c.h> +#endif #include -#include #ifdef CONFIG_HARD_I2C DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_I2C_MULTI_BUS) -/* Initialize the bus pointer to whatever one the SPD EEPROM is on. - * Default is bus 0. This is necessary because the DDR initialization - * runs from ROM, and we can't switch buses because we can't modify - * the global variables. - */ -#ifdef CFG_SPD_BUS_NUM -static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM; -#else -static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; -#endif -#endif /* CONFIG_I2C_MULTI_BUS */ +#define IIC_OK 0 +#define IIC_NOK 1 +#define IIC_NOK_LA 2 /* Lost arbitration */ +#define IIC_NOK_ICT 3 /* Incomplete transfer */ +#define IIC_NOK_XFRA 4 /* Transfer aborted */ +#define IIC_NOK_DATA 5 /* No data in buffer */ +#define IIC_NOK_TOUT 6 /* Transfer timeout */ -static void _i2c_bus_reset(void) +#define IIC_TIMEOUT 1 /* 1 seconde */ + + +static void _i2c_bus_reset (void) { - int i; - u8 dc; + int i, status; /* Reset status register */ /* write 1 in SCMP and IRQA to clear these fields */ - out_8((u8 *)IIC_STS, 0x0A); + out8 (IIC_STS, 0x0A); /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ - out_8((u8 *)IIC_EXTSTS, 0x8F); + out8 (IIC_EXTSTS, 0x8F); + __asm__ volatile ("eieio"); - /* Place chip in the reset state */ - out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST); + /* + * Get current state, reset bus + * only if no transfers are pending. + */ + i = 10; + do { + /* Get status */ + status = in8 (IIC_STS); + udelay (500); /* 500us */ + i--; + } while ((status & IIC_STS_PT) && (i > 0)); + /* Soft reset controller */ + status = in8 (IIC_XTCNTLSS); + out8 (IIC_XTCNTLSS, (status | IIC_XTCNTLSS_SRST)); + __asm__ volatile ("eieio"); - /* Check if bus is free */ - dc = in_8((u8 *)IIC_DIRECTCNTL); - if (!DIRCTNL_FREE(dc)){ - /* Try to set bus free state */ - out_8((u8 *)IIC_DIRECTCNTL, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC); - - /* Wait until we regain bus control */ - for (i = 0; i < 100; ++i) { - dc = in_8((u8 *)IIC_DIRECTCNTL); - if (DIRCTNL_FREE(dc)) - break; - - /* Toggle SCL line */ - dc ^= IIC_DIRCNTL_SCC; - out_8((u8 *)IIC_DIRECTCNTL, dc); - udelay(10); - dc ^= IIC_DIRCNTL_SCC; - out_8((u8 *)IIC_DIRECTCNTL, dc); + /* make sure where in initial state, data hi, clock hi */ + out8 (IIC_DIRECTCNTL, 0xC); + for (i = 0; i < 10; i++) { + if ((in8 (IIC_DIRECTCNTL) & 0x3) != 0x3) { + /* clock until we get to known state */ + out8 (IIC_DIRECTCNTL, 0x8); /* clock lo */ + udelay (100); /* 100us */ + out8 (IIC_DIRECTCNTL, 0xC); /* clock hi */ + udelay (100); /* 100us */ + } else { + break; } } - - /* Remove reset */ - out_8((u8 *)IIC_XTCNTLSS, 0); + /* send start condition */ + out8 (IIC_DIRECTCNTL, 0x4); + udelay (1000); /* 1ms */ + /* send stop condition */ + out8 (IIC_DIRECTCNTL, 0xC); + udelay (1000); /* 1ms */ + /* Unreset controller */ + out8 (IIC_XTCNTLSS, (status & ~IIC_XTCNTLSS_SRST)); + udelay (1000); /* 1ms */ } -void i2c_init(int speed, int slaveadd) +void i2c_init (int speed, int slaveadd) { + sys_info_t sysInfo; unsigned long freqOPB; int val, divisor; - int bus; #ifdef CFG_I2C_INIT_BOARD /* call board specific i2c bus reset routine before accessing the */ @@ -102,99 +94,101 @@ void i2c_init(int speed, int slaveadd) i2c_init_board(); #endif - for (bus = 0; bus < CFG_MAX_I2C_BUS; bus++) { - I2C_SET_BUS(bus); + /* Handle possible failed I2C state */ + /* FIXME: put this into i2c_init_board()? */ + _i2c_bus_reset (); - /* Handle possible failed I2C state */ - /* FIXME: put this into i2c_init_board()? */ - _i2c_bus_reset(); + /* clear lo master address */ + out8 (IIC_LMADR, 0); - /* clear lo master address */ - out_8((u8 *)IIC_LMADR, 0); + /* clear hi master address */ + out8 (IIC_HMADR, 0); - /* clear hi master address */ - out_8((u8 *)IIC_HMADR, 0); + /* clear lo slave address */ + out8 (IIC_LSADR, 0); - /* clear lo slave address */ - out_8((u8 *)IIC_LSADR, 0); + /* clear hi slave address */ + out8 (IIC_HSADR, 0); - /* clear hi slave address */ - out_8((u8 *)IIC_HSADR, 0); + /* Clock divide Register */ + /* get OPB frequency */ + get_sys_info (&sysInfo); + freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; + /* set divisor according to freqOPB */ + divisor = (freqOPB - 1) / 10000000; + if (divisor == 0) + divisor = 1; + out8 (IIC_CLKDIV, divisor); - /* Clock divide Register */ - /* get OPB frequency */ - freqOPB = get_OPB_freq(); - /* set divisor according to freqOPB */ - divisor = (freqOPB - 1) / 10000000; - if (divisor == 0) - divisor = 1; - out_8((u8 *)IIC_CLKDIV, divisor); + /* no interrupts */ + out8 (IIC_INTRMSK, 0); - /* no interrupts */ - out_8((u8 *)IIC_INTRMSK, 0); + /* clear transfer count */ + out8 (IIC_XFRCNT, 0); - /* clear transfer count */ - out_8((u8 *)IIC_XFRCNT, 0); + /* clear extended control & stat */ + /* write 1 in SRC SRS SWC SWS to clear these fields */ + out8 (IIC_XTCNTLSS, 0xF0); - /* clear extended control & stat */ - /* write 1 in SRC SRS SWC SWS to clear these fields */ - out_8((u8 *)IIC_XTCNTLSS, 0xF0); + /* Mode Control Register + Flush Slave/Master data buffer */ + out8 (IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); + __asm__ volatile ("eieio"); - /* Mode Control Register - Flush Slave/Master data buffer */ - out_8((u8 *)IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); - val = in_8((u8 *)IIC_MDCNTL); + val = in8(IIC_MDCNTL); + __asm__ volatile ("eieio"); - /* Ignore General Call, slave transfers are ignored, - * disable interrupts, exit unknown bus state, enable hold - * SCL 100kHz normaly or FastMode for 400kHz and above - */ + /* Ignore General Call, slave transfers are ignored, + disable interrupts, exit unknown bus state, enable hold + SCL + 100kHz normaly or FastMode for 400kHz and above + */ - val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL; - if (speed >= 400000) - val |= IIC_MDCNTL_FSM; - out_8((u8 *)IIC_MDCNTL, val); - - /* clear control reg */ - out_8((u8 *)IIC_CNTL, 0x00); + val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL; + if( speed >= 400000 ){ + val |= IIC_MDCNTL_FSM; } + out8 (IIC_MDCNTL, val); + + /* clear control reg */ + out8 (IIC_CNTL, 0x00); + __asm__ volatile ("eieio"); - /* set to SPD bus as default bus upon powerup */ - I2C_SET_BUS(CFG_SPD_BUS_NUM); } /* - * This code tries to use the features of the 405GP i2c - * controller. It will transfer up to 4 bytes in one pass - * on the loop. It only does out_8((u8 *)lbz) to the buffer when it - * is possible to do out16(lhz) transfers. - * - * cmd_type is 0 for write 1 for read. - * - * addr_len can take any value from 0-255, it is only limited - * by the char, we could make it larger if needed. If it is - * 0 we skip the address write cycle. - * - * Typical case is a Write of an addr followd by a Read. The - * IBM FAQ does not cover this. On the last byte of the write - * we don't set the creg CHT bit, and on the first bytes of the - * read we set the RPST bit. - * - * It does not support address only transfers, there must be - * a data part. If you want to write the address yourself, put - * it in the data pointer. - * - * It does not support transfer to/from address 0. - * - * It does not check XFRCNT. - */ -static int i2c_transfer(unsigned char cmd_type, - unsigned char chip, - unsigned char addr[], - unsigned char addr_len, - unsigned char data[], - unsigned short data_len) + This code tries to use the features of the 405GP i2c + controller. It will transfer up to 4 bytes in one pass + on the loop. It only does out8(lbz) to the buffer when it + is possible to do out16(lhz) transfers. + + cmd_type is 0 for write 1 for read. + + addr_len can take any value from 0-255, it is only limited + by the char, we could make it larger if needed. If it is + 0 we skip the address write cycle. + + Typical case is a Write of an addr followd by a Read. The + IBM FAQ does not cover this. On the last byte of the write + we don't set the creg CHT bit, and on the first bytes of the + read we set the RPST bit. + + It does not support address only transfers, there must be + a data part. If you want to write the address yourself, put + it in the data pointer. + + It does not support transfer to/from address 0. + + It does not check XFRCNT. +*/ +static +int i2c_transfer(unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], + unsigned short data_len ) { unsigned char* ptr; int reading; @@ -204,88 +198,97 @@ static int i2c_transfer(unsigned char cmd_type, int i; uchar creg; - if (data == 0 || data_len == 0) { - /* Don't support data transfer of no length or to address 0 */ + if( data == 0 || data_len == 0 ){ + /*Don't support data transfer of no length or to address 0*/ printf( "i2c_transfer: bad call\n" ); return IIC_NOK; } - if (addr && addr_len) { + if( addr && addr_len ){ ptr = addr; cnt = addr_len; reading = 0; - } else { + }else{ ptr = data; cnt = data_len; reading = cmd_type; } - /* Clear Stop Complete Bit */ - out_8((u8 *)IIC_STS, IIC_STS_SCMP); + /*Clear Stop Complete Bit*/ + out8(IIC_STS,IIC_STS_SCMP); /* Check init */ - i = 10; + i=10; do { /* Get status */ - status = in_8((u8 *)IIC_STS); + status = in8(IIC_STS); + __asm__ volatile("eieio"); i--; - } while ((status & IIC_STS_PT) && (i > 0)); + } while ((status & IIC_STS_PT) && (i>0)); if (status & IIC_STS_PT) { result = IIC_NOK_TOUT; return(result); } - /* flush the Master/Slave Databuffers */ - out_8((u8 *)IIC_MDCNTL, ((in_8((u8 *)IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); - /* need to wait 4 OPB clocks? code below should take that long */ + /*flush the Master/Slave Databuffers*/ + out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); + /*need to wait 4 OPB clocks? code below should take that long*/ /* 7-bit adressing */ - out_8((u8 *)IIC_HMADR, 0); - out_8((u8 *)IIC_LMADR, chip); + out8(IIC_HMADR,0); + out8(IIC_LMADR, chip); + __asm__ volatile("eieio"); tran = 0; result = IIC_OK; creg = 0; - while (tran != cnt && (result == IIC_OK)) { + while ( tran != cnt && (result == IIC_OK)) { int bc,j; /* Control register = - * Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start, - * Transfer is a sequence of transfers - */ + Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start, + Transfer is a sequence of transfers + */ creg |= IIC_CNTL_PT; - bc = (cnt - tran) > 4 ? 4 : cnt - tran; - creg |= (bc - 1) << 4; - /* if the real cmd type is write continue trans */ - if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt)) + bc = (cnt - tran) > 4 ? 4 : + cnt - tran; + creg |= (bc-1)<<4; + /* if the real cmd type is write continue trans*/ + if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) ) creg |= IIC_CNTL_CHT; if (reading) creg |= IIC_CNTL_READ; - else - for(j=0; j < bc; j++) + else { + for(j=0; j 0)); + } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) + && (i>0)); if (status & IIC_STS_ERR) { result = IIC_NOK; - status = in_8((u8 *)IIC_EXTSTS); + status = in8 (IIC_EXTSTS); /* Lost arbitration? */ if (status & IIC_EXTSTS_LA) result = IIC_NOK_LA; @@ -303,32 +306,34 @@ static int i2c_transfer(unsigned char cmd_type, /* Are there data in buffer */ if (status & IIC_STS_MDBS) { /* - * even if we have data we have to wait 4OPB clocks - * for it to hit the front of the FIFO, after that - * we can just read. We should check XFCNT here and - * if the FIFO is full there is no need to wait. - */ - udelay(1); - for (j=0; jed (i.e. there was a chip at that address which * drove the data line low). */ - return (i2c_transfer(1, chip << 1, 0,0, buf, 1) != 0); + return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0); } -int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) +int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) { uchar xaddr[4]; int ret; - if (alen > 4) { + if ( alen > 4 ) { printf ("I2C read: addr len %d not supported\n", alen); return 1; } - if (alen > 0) { + if ( alen > 0 ) { xaddr[0] = (addr >> 24) & 0xFF; xaddr[1] = (addr >> 16) & 0xFF; xaddr[2] = (addr >> 8) & 0xFF; @@ -373,10 +378,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) * still be one byte because the extra address bits are * hidden in the chip address. */ - if (alen > 0) + if( alen > 0 ) chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); #endif - if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) { + if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { if (gd->have_console) printf( "I2c read: failed %d\n", ret); return 1; @@ -384,17 +389,16 @@ int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) return 0; } -int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) +int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) { uchar xaddr[4]; - if (alen > 4) { + if ( alen > 4 ) { printf ("I2C write: addr len %d not supported\n", alen); return 1; } - - if (alen > 0) { + if ( alen > 0 ) { xaddr[0] = (addr >> 24) & 0xFF; xaddr[1] = (addr >> 16) & 0xFF; xaddr[2] = (addr >> 8) & 0xFF; @@ -413,11 +417,11 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) * still be one byte because the extra address bits are * hidden in the chip address. */ - if (alen > 0) + if( alen > 0 ) chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); #endif - return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); + return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); } /*----------------------------------------------------------------------- @@ -429,7 +433,7 @@ uchar i2c_reg_read(uchar i2c_addr, uchar reg) i2c_read(i2c_addr, reg, 1, &buf, 1); - return (buf); + return(buf); } /*----------------------------------------------------------------------- @@ -439,38 +443,4 @@ void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val) { i2c_write(i2c_addr, reg, 1, &val, 1); } - -#if defined(CONFIG_I2C_MULTI_BUS) -/* - * Functions for multiple I2C bus handling - */ -unsigned int i2c_get_bus_num(void) -{ - return i2c_bus_num; -} - -int i2c_set_bus_num(unsigned int bus) -{ - if (bus >= CFG_MAX_I2C_BUS) - return -1; - - i2c_bus_num = bus; - - return 0; -} -#endif /* CONFIG_I2C_MULTI_BUS */ - -/* TODO: add 100/400k switching */ -unsigned int i2c_get_bus_speed(void) -{ - return CFG_I2C_SPEED; -} - -int i2c_set_bus_speed(unsigned int speed) -{ - if (speed != CFG_I2C_SPEED) - return -1; - - return 0; -} #endif /* CONFIG_HARD_I2C */ diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index 8620e2b48..886f40515 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -34,26 +34,11 @@ #include #include #include -#include +#include "vecnum.h" DECLARE_GLOBAL_DATA_PTR; -/* - * Define the number of UIC's - */ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UIC_MAX 4 -#elif defined(CONFIG_440GX) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) -#define UIC_MAX 3 -#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define UIC_MAX 2 -#else -#define UIC_MAX 1 -#endif +/****************************************************************************/ /* * CPM interrupt vector functions. @@ -64,15 +49,27 @@ struct irq_action { int count; }; -static struct irq_action irq_vecs[UIC_MAX * 32]; +static struct irq_action irq_vecs[32]; +void uic0_interrupt( void * parms); /* UIC0 handler */ -u32 get_dcr(u16); -void set_dcr(u16, u32); +#if defined(CONFIG_440) +static struct irq_action irq_vecs1[32]; /* For UIC1 */ -#if (UIC_MAX > 1) && !defined(CONFIG_440GX) -static void uic_cascade_interrupt(void *para); -#endif +void uic1_interrupt( void * parms); /* UIC1 handler */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +static struct irq_action irq_vecs2[32]; /* For UIC2 */ +void uic2_interrupt( void * parms); /* UIC2 handler */ +#endif /* CONFIG_440GX CONFIG_440SPE */ + +#if defined(CONFIG_440SPE) +static struct irq_action irq_vecs3[32]; /* For UIC3 */ +void uic3_interrupt( void * parms); /* UIC3 handler */ +#endif /* CONFIG_440SPE */ + +#endif /* CONFIG_440 */ + +/****************************************************************************/ #if defined(CONFIG_440) /* SPRN changed in 440 */ @@ -101,6 +98,8 @@ static __inline__ void set_evpr(unsigned long val) } #endif /* defined(CONFIG_440 */ +/****************************************************************************/ + int interrupt_init_cpu (unsigned *decrementer_count) { int vec; @@ -112,10 +111,25 @@ int interrupt_init_cpu (unsigned *decrementer_count) /* * Mark all irqs as free */ - for (vec = 0; vec < (UIC_MAX * 32); vec++) { + for (vec=0; vec<32; vec++) { irq_vecs[vec].handler = NULL; irq_vecs[vec].arg = NULL; irq_vecs[vec].count = 0; +#if defined(CONFIG_440) + irq_vecs1[vec].handler = NULL; + irq_vecs1[vec].arg = NULL; + irq_vecs1[vec].count = 0; +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) + irq_vecs2[vec].handler = NULL; + irq_vecs2[vec].arg = NULL; + irq_vecs2[vec].count = 0; +#endif /* CONFIG_440GX */ +#if defined(CONFIG_440SPE) + irq_vecs3[vec].handler = NULL; + irq_vecs3[vec].arg = NULL; + irq_vecs3[vec].count = 0; +#endif /* CONFIG_440SPE */ +#endif } #ifdef CONFIG_4xx @@ -156,21 +170,15 @@ int interrupt_init_cpu (unsigned *decrementer_count) */ set_evpr(0x00000000); +#if defined(CONFIG_440) #if !defined(CONFIG_440GX) -#if (UIC_MAX > 1) /* Install the UIC1 handlers */ - irq_install_handler(VECNUM_UIC1NC, uic_cascade_interrupt, 0); - irq_install_handler(VECNUM_UIC1C, uic_cascade_interrupt, 0); + irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0); + irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0); #endif -#if (UIC_MAX > 2) - irq_install_handler(VECNUM_UIC2NC, uic_cascade_interrupt, 0); - irq_install_handler(VECNUM_UIC2C, uic_cascade_interrupt, 0); #endif -#if (UIC_MAX > 3) - irq_install_handler(VECNUM_UIC3NC, uic_cascade_interrupt, 0); - irq_install_handler(VECNUM_UIC3C, uic_cascade_interrupt, 0); -#endif -#else /* !defined(CONFIG_440GX) */ + +#if defined(CONFIG_440GX) /* Take the GX out of compatibility mode * Travis Sawyer, 9 Mar 2004 * NOTE: 440gx user manual inconsistency here @@ -186,24 +194,84 @@ int interrupt_init_cpu (unsigned *decrementer_count) mtdcr(uicb0er, 0x54000000); /* None are critical */ mtdcr(uicb0cr, 0); -#endif /* !defined(CONFIG_440GX) */ +#endif return (0); } -/* Handler for UIC interrupt */ -static void uic_interrupt(u32 uic_base, int vec_base) +/****************************************************************************/ + +/* + * Handle external interrupts + */ +#if defined(CONFIG_440GX) +void external_interrupt(struct pt_regs *regs) { - u32 uic_msr; - u32 msr_shift; + ulong uic_msr; + + /* + * Read masked interrupt status register to determine interrupt source + */ + /* 440 GX uses base uic register */ + uic_msr = mfdcr(uicb0msr); + + if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) ) + uic0_interrupt(0); + + if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) + uic1_interrupt(0); + + if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) + uic2_interrupt(0); + + mtdcr(uicb0sr, uic_msr); + + return; + +} /* external_interrupt CONFIG_440GX */ + +#elif defined(CONFIG_440SPE) +void external_interrupt(struct pt_regs *regs) +{ + ulong uic_msr; + + /* + * Read masked interrupt status register to determine interrupt source + */ + /* 440 SPe uses base uic register */ + uic_msr = mfdcr(uic0msr); + + if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) ) + uic1_interrupt(0); + + if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) ) + uic2_interrupt(0); + + if ( (UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr) ) + uic3_interrupt(0); + + if (uic_msr & ~(UICB0_ALL)) + uic0_interrupt(0); + + mtdcr(uic0sr, uic_msr); + + return; +} /* external_interrupt CONFIG_440SPE */ + +#else + +void external_interrupt(struct pt_regs *regs) +{ + ulong uic_msr; + ulong msr_shift; int vec; /* * Read masked interrupt status register to determine interrupt source */ - uic_msr = get_dcr(uic_base + UIC_MSR); + uic_msr = mfdcr(uicmsr); msr_shift = uic_msr; - vec = vec_base; + vec = 0; while (msr_shift != 0) { if (msr_shift & 0x80000000) { @@ -216,18 +284,59 @@ static void uic_interrupt(u32 uic_base, int vec_base) /* call isr */ (*irq_vecs[vec].handler)(irq_vecs[vec].arg); } else { - set_dcr(uic_base + UIC_ER, - get_dcr(uic_base + UIC_ER) & - ~(0x80000000 >> (vec & 0x1f))); - printf("Masking bogus interrupt vector %d" - " (UIC_BASE=0x%x)\n", vec, uic_base); + mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector 0x%x\n", vec); } /* - * After servicing the interrupt, we have to remove the - * status indicator + * After servicing the interrupt, we have to remove the status indicator. */ - set_dcr(uic_base + UIC_SR, (0x80000000 >> (vec & 0x1f))); + mtdcr(uicsr, (0x80000000 >> vec)); + } + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +/* Handler for UIC0 interrupt */ +void uic0_interrupt( void * parms) +{ + ulong uic_msr; + ulong msr_shift; + int vec; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = mfdcr(uicmsr); + msr_shift = uic_msr; + vec = 0; + + while (msr_shift != 0) { + if (msr_shift & 0x80000000) { + /* + * Increment irq counter (for debug purpose only) + */ + irq_vecs[vec].count++; + + if (irq_vecs[vec].handler != NULL) { + /* call isr */ + (*irq_vecs[vec].handler)(irq_vecs[vec].arg); + } else { + mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector (uic0) 0x%x\n", vec); + } + + /* + * After servicing the interrupt, we have to remove the status indicator. + */ + mtdcr(uicsr, (0x80000000 >> vec)); } /* @@ -238,149 +347,272 @@ static void uic_interrupt(u32 uic_base, int vec_base) } } -#if (UIC_MAX > 1) && !defined(CONFIG_440GX) -static void uic_cascade_interrupt(void *para) -{ - external_interrupt(para); -} -#endif +#endif /* CONFIG_440GX */ #if defined(CONFIG_440) -#if defined(CONFIG_440GX) -/* 440GX uses base uic register */ -#define UIC_BMSR uicb0msr -#define UIC_BSR uicb0sr -#else -#define UIC_BMSR uic0msr -#define UIC_BSR uic0sr -#endif -#else /* CONFIG_440 */ -#define UIC_BMSR uicmsr -#define UIC_BSR uicsr -#endif /* CONFIG_440 */ - -/* - * Handle external interrupts - */ -void external_interrupt(struct pt_regs *regs) +/* Handler for UIC1 interrupt */ +void uic1_interrupt( void * parms) { - u32 uic_msr; + ulong uic1_msr; + ulong msr_shift; + int vec; /* * Read masked interrupt status register to determine interrupt source */ - uic_msr = mfdcr(UIC_BMSR); + uic1_msr = mfdcr(uic1msr); + msr_shift = uic1_msr; + vec = 0; -#if (UIC_MAX > 1) - if ((UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr)) - uic_interrupt(UIC1_DCR_BASE, 32); -#endif + while (msr_shift != 0) { + if (msr_shift & 0x80000000) { + /* + * Increment irq counter (for debug purpose only) + */ + irq_vecs1[vec].count++; -#if (UIC_MAX > 2) - if ((UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr)) - uic_interrupt(UIC2_DCR_BASE, 64); -#endif + if (irq_vecs1[vec].handler != NULL) { + /* call isr */ + (*irq_vecs1[vec].handler)(irq_vecs1[vec].arg); + } else { + mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec); + } -#if (UIC_MAX > 3) - if ((UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr)) - uic_interrupt(UIC3_DCR_BASE, 96); -#endif + /* + * After servicing the interrupt, we have to remove the status indicator. + */ + mtdcr(uic1sr, (0x80000000 >> vec)); + } -#if defined(CONFIG_440) -#if !defined(CONFIG_440GX) - if (uic_msr & ~(UICB0_ALL)) - uic_interrupt(UIC0_DCR_BASE, 0); -#else - if ((UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr)) - uic_interrupt(UIC0_DCR_BASE, 0); -#endif -#else /* CONFIG_440 */ - uic_interrupt(UIC0_DCR_BASE, 0); -#endif /* CONFIG_440 */ - - mtdcr(UIC_BSR, uic_msr); - - return; + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } } +#endif /* defined(CONFIG_440) */ + +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +/* Handler for UIC2 interrupt */ +void uic2_interrupt( void * parms) +{ + ulong uic2_msr; + ulong msr_shift; + int vec; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic2_msr = mfdcr(uic2msr); + msr_shift = uic2_msr; + vec = 0; + + while (msr_shift != 0) { + if (msr_shift & 0x80000000) { + /* + * Increment irq counter (for debug purpose only) + */ + irq_vecs2[vec].count++; + + if (irq_vecs2[vec].handler != NULL) { + /* call isr */ + (*irq_vecs2[vec].handler)(irq_vecs2[vec].arg); + } else { + mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector (uic2) 0x%x\n", vec); + } + + /* + * After servicing the interrupt, we have to remove the status indicator. + */ + mtdcr(uic2sr, (0x80000000 >> vec)); + } + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} +#endif /* defined(CONFIG_440GX) */ + +#if defined(CONFIG_440SPE) +/* Handler for UIC3 interrupt */ +void uic3_interrupt( void * parms) +{ + ulong uic3_msr; + ulong msr_shift; + int vec; + + /* + * Read masked interrupt status register to determine interrupt source + */ + uic3_msr = mfdcr(uic3msr); + msr_shift = uic3_msr; + vec = 0; + + while (msr_shift != 0) { + if (msr_shift & 0x80000000) { + /* + * Increment irq counter (for debug purpose only) + */ + irq_vecs3[vec].count++; + + if (irq_vecs3[vec].handler != NULL) { + /* call isr */ + (*irq_vecs3[vec].handler)(irq_vecs3[vec].arg); + } else { + mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> vec)); + printf ("Masking bogus interrupt vector (uic3) 0x%x\n", vec); + } + + /* + * After servicing the interrupt, we have to remove the status indicator. + */ + mtdcr(uic3sr, (0x80000000 >> vec)); + } + + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } +} +#endif /* defined(CONFIG_440SPE) */ + +/****************************************************************************/ /* * Install and free a interrupt handler. */ -void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg) + +void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) { - int i; + struct irq_action *irqa = irq_vecs; + int i = vec; + +#if defined(CONFIG_440) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) + if ((vec > 31) && (vec < 64)) { + i = vec - 32; + irqa = irq_vecs1; + } else if (vec > 63) { + i = vec - 64; + irqa = irq_vecs2; + } +#else /* CONFIG_440GX */ + if (vec > 31) { + i = vec - 32; + irqa = irq_vecs1; + } +#endif /* CONFIG_440GX */ +#endif /* CONFIG_440 */ /* - * Print warning when replacing with a different irq vector + * print warning when replacing with a different irq vector */ - if ((irq_vecs[vec].handler != NULL) && (irq_vecs[vec].handler != handler)) { - printf("Interrupt vector %d: handler 0x%x replacing 0x%x\n", - vec, (uint) handler, (uint) irq_vecs[vec].handler); + if ((irqa[i].handler != NULL) && (irqa[i].handler != handler)) { + printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n", + vec, (uint) handler, (uint) irqa[i].handler); } - irq_vecs[vec].handler = handler; - irq_vecs[vec].arg = arg; + irqa[i].handler = handler; + irqa[i].arg = arg; - i = vec & 0x1f; - if ((vec >= 0) && (vec < 32)) - mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i)); -#if (UIC_MAX > 1) - else if ((vec >= 32) && (vec < 64)) - mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i)); +#if defined(CONFIG_440) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) + if ((vec > 31) && (vec < 64)) + mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); + else if (vec > 63) + mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i)); + else +#endif /* CONFIG_440GX */ + if (vec > 31) + mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); + else #endif -#if (UIC_MAX > 2) - else if ((vec >= 64) && (vec < 96)) - mtdcr(uic2er, mfdcr(uic2er) | (0x80000000 >> i)); + mtdcr (uicer, mfdcr (uicer) | (0x80000000 >> i)); +#if 0 + printf ("Install interrupt for vector %d ==> %p\n", vec, handler); #endif -#if (UIC_MAX > 3) - else if (vec >= 96) - mtdcr(uic3er, mfdcr(uic3er) | (0x80000000 >> i)); -#endif - - debug("Install interrupt for vector %d ==> %p\n", vec, handler); } void irq_free_handler (int vec) { - int i; + struct irq_action *irqa = irq_vecs; + int i = vec; - debug("Free interrupt for vector %d ==> %p\n", - vec, irq_vecs[vec].handler); - - i = vec & 0x1f; - if ((vec >= 0) && (vec < 32)) - mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i)); -#if (UIC_MAX > 1) - else if ((vec >= 32) && (vec < 64)) - mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i)); -#endif -#if (UIC_MAX > 2) - else if ((vec >= 64) && (vec < 96)) - mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> i)); -#endif -#if (UIC_MAX > 3) - else if (vec >= 96) - mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> i)); +#if defined(CONFIG_440) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) + if ((vec > 31) && (vec < 64)) { + irqa = irq_vecs1; + i = vec - 32; + } else if (vec > 63) { + irqa = irq_vecs2; + i = vec - 64; + } +#endif /* CONFIG_440GX */ + if (vec > 31) { + irqa = irq_vecs1; + i = vec - 32; + } #endif - irq_vecs[vec].handler = NULL; - irq_vecs[vec].arg = NULL; +#if 0 + printf ("Free interrupt for vector %d ==> %p\n", + vec, irq_vecs[vec].handler); +#endif + +#if defined(CONFIG_440) +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) + if ((vec > 31) && (vec < 64)) + mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); + else if (vec > 63) + mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i)); + else +#endif /* CONFIG_440GX */ + if (vec > 31) + mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); + else +#endif + mtdcr (uicer, mfdcr (uicer) & ~(0x80000000 >> i)); + + irqa[i].handler = NULL; + irqa[i].arg = NULL; } +/****************************************************************************/ + void timer_interrupt_cpu (struct pt_regs *regs) { /* nothing to do here */ return; } -#if defined(CONFIG_CMD_IRQ) -int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +/****************************************************************************/ + +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) + +/******************************************************************************* + * + * irqinfo - print information about PCI devices + * + */ +int +do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int vec; - printf ("Interrupt-Information:\n"); + printf ("\nInterrupt-Information:\n"); +#if defined(CONFIG_440) + printf ("\nUIC 0\n"); +#endif printf ("Nr Routine Arg Count\n"); - for (vec = 0; vec < (UIC_MAX * 32); vec++) { + for (vec=0; vec<32; vec++) { if (irq_vecs[vec].handler != NULL) { printf ("%02d %08lx %08lx %d\n", vec, @@ -390,6 +622,45 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } +#if defined(CONFIG_440) + printf ("\nUIC 1\n"); + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec<32; vec++) { + if (irq_vecs1[vec].handler != NULL) + printf ("%02d %08lx %08lx %d\n", + vec+31, (ulong)irq_vecs1[vec].handler, + (ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count); + } + printf("\n"); +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) + printf ("\nUIC 2\n"); + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec<32; vec++) { + if (irq_vecs2[vec].handler != NULL) + printf ("%02d %08lx %08lx %d\n", + vec+63, (ulong)irq_vecs2[vec].handler, + (ulong)irq_vecs2[vec].arg, irq_vecs2[vec].count); + } + printf("\n"); +#endif + +#if defined(CONFIG_440SPE) + printf ("\nUIC 3\n"); + printf ("Nr Routine Arg Count\n"); + + for (vec=0; vec<32; vec++) { + if (irq_vecs3[vec].handler != NULL) + printf ("%02d %08lx %08lx %d\n", + vec+63, (ulong)irq_vecs3[vec].handler, + (ulong)irq_vecs3[vec].arg, irq_vecs3[vec].count); + } + printf("\n"); +#endif + return 0; } -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S index 4227a4c15..be283403e 100644 --- a/cpu/ppc4xx/kgdb.S +++ b/cpu/ppc4xx/kgdb.S @@ -34,7 +34,7 @@ #include #include -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) /* * cache flushing routines for kgdb */ @@ -45,7 +45,7 @@ kgdb_flush_cache_all: iccci r0,r0 /* iccci invalidates the entire I cache */ /* dcache */ addi r6,0,0x0000 /* clear GPR 6 */ - addi r7,r0, 128 /* do loop for # of dcache lines */ + addi r7,r0, 128 /* do loop for # of dcache lines */ /* NOTE: dccci invalidates both */ mtctr r7 /* ways in the D cache */ ..dcloop: @@ -56,23 +56,23 @@ kgdb_flush_cache_all: .globl kgdb_flush_cache_range kgdb_flush_cache_range: - li r5,L1_CACHE_BYTES-1 + li r5,CFG_CACHELINE_SIZE-1 andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 - srwi. r4,r4,L1_CACHE_SHIFT + srwi. r4,r4,CFG_CACHELINE_SHIFT beqlr mtctr r4 mr r6,r3 1: dcbst 0,r3 - addi r3,r3,L1_CACHE_BYTES + addi r3,r3,CFG_CACHELINE_SIZE bdnz 1b sync /* wait for dcbst's to get to ram */ mtctr r4 2: icbi 0,r6 - addi r6,r6,L1_CACHE_BYTES + addi r6,r6,CFG_CACHELINE_SIZE bdnz 2b SYNC blr -#endif +#endif /* CFG_CMD_KGDB */ diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index c8827201e..aa580ed48 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -27,26 +27,30 @@ | | Author: Mark Wisner | + | Change Activity- + | + | Date Description of Change BY + | --------- --------------------- --- + | 05-May-99 Created MKW + | 01-Jul-99 Changed clock setting of sta_reg from 66Mhz to 50Mhz to + | better match OPB speed. Also modified delay times. JWB + | 29-Jul-99 Added Full duplex support MKW + | 24-Aug-99 Removed printf from dp83843_duplex() JWB + | 19-Jul-00 Ported to esd cpci405 sr + | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS + | + | +-----------------------------------------------------------------------------*/ -/* define DEBUG for debugging output (obviously ;-)) */ -#if 0 -#define DEBUG -#endif - #include #include -#include #include #include #include #include <405_mal.h> #include -#if !defined(CONFIG_PHY_CLK_FREQ) -#define CONFIG_PHY_CLK_FREQ 0 -#endif - +#undef ET_DEBUG /***********************************************************/ /* Dump out to the screen PHY regs */ /***********************************************************/ @@ -56,6 +60,7 @@ void miiphy_dump (char *devname, unsigned char addr) unsigned long i; unsigned short data; + for (i = 0; i < 0x1A; i++) { if (miiphy_read (devname, addr, i, &data)) { printf ("read error for reg %lx\n", i); @@ -70,264 +75,213 @@ void miiphy_dump (char *devname, unsigned char addr) } /* end for loop */ } /* end dump */ + /***********************************************************/ /* (Re)start autonegotiation */ /***********************************************************/ int phy_setup_aneg (char *devname, unsigned char addr) { - u16 bmcr; - -#if defined(CONFIG_PHY_DYNAMIC_ANEG) - /* - * Set up advertisement based on capablilities reported by the PHY. - * This should work for both copper and fiber. - */ - u16 bmsr; -#if defined(CONFIG_PHY_GIGE) - u16 exsr = 0x0000; -#endif - - miiphy_read (devname, addr, PHY_BMSR, &bmsr); - -#if defined(CONFIG_PHY_GIGE) - if (bmsr & PHY_BMSR_EXT_STAT) - miiphy_read (devname, addr, PHY_EXSR, &exsr); - - if (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH)) { - /* 1000BASE-X */ - u16 anar = 0x0000; - - if (exsr & PHY_EXSR_1000XF) - anar |= PHY_X_ANLPAR_FD; - - if (exsr & PHY_EXSR_1000XH) - anar |= PHY_X_ANLPAR_HD; - - miiphy_write (devname, addr, PHY_ANAR, anar); - } else -#endif - { - u16 anar, btcr; - - miiphy_read (devname, addr, PHY_ANAR, &anar); - anar &= ~(0x5000 | PHY_ANLPAR_T4 | PHY_ANLPAR_TXFD | - PHY_ANLPAR_TX | PHY_ANLPAR_10FD | PHY_ANLPAR_10); - - miiphy_read (devname, addr, PHY_1000BTCR, &btcr); - btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD); - - if (bmsr & PHY_BMSR_100T4) - anar |= PHY_ANLPAR_T4; - - if (bmsr & PHY_BMSR_100TXF) - anar |= PHY_ANLPAR_TXFD; - - if (bmsr & PHY_BMSR_100TXH) - anar |= PHY_ANLPAR_TX; - - if (bmsr & PHY_BMSR_10TF) - anar |= PHY_ANLPAR_10FD; - - if (bmsr & PHY_BMSR_10TH) - anar |= PHY_ANLPAR_10; - - miiphy_write (devname, addr, PHY_ANAR, anar); - -#if defined(CONFIG_PHY_GIGE) - if (exsr & PHY_EXSR_1000TF) - btcr |= PHY_1000BTCR_1000FD; - - if (exsr & PHY_EXSR_1000TH) - btcr |= PHY_1000BTCR_1000HD; - - miiphy_write (devname, addr, PHY_1000BTCR, btcr); -#endif - } - -#else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ - /* - * Set up standard advertisement - */ - u16 adv; + unsigned short ctl, adv; + /* Setup standard advertise */ miiphy_read (devname, addr, PHY_ANAR, &adv); - adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | - PHY_ANLPAR_10FD | PHY_ANLPAR_10); + adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | + PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | + PHY_ANLPAR_10); miiphy_write (devname, addr, PHY_ANAR, adv); miiphy_read (devname, addr, PHY_1000BTCR, &adv); adv |= (0x0300); miiphy_write (devname, addr, PHY_1000BTCR, adv); -#endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ - /* Start/Restart aneg */ - miiphy_read (devname, addr, PHY_BMCR, &bmcr); - bmcr |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); - miiphy_write (devname, addr, PHY_BMCR, bmcr); + miiphy_read (devname, addr, PHY_BMCR, &ctl); + ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + miiphy_write (devname, addr, PHY_BMCR, ctl); return 0; } + /***********************************************************/ /* read a phy reg and return the value with a rc */ /***********************************************************/ -/* AMCC_TODO: - * Find out of the choice for the emac for MDIO is from the bridges, - * i.e. ZMII or RGMII as approporiate. If the bridges are not used - * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL] - * used? If so, then this routine below does not apply to the 460EX/GT. - * - * sr: Currently on 460EX only EMAC0 works with MDIO, so we always - * return EMAC0 offset here - */ unsigned int miiphy_getemac_offset (void) { -#if (defined(CONFIG_440) && \ - !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ - !defined(CONFIG_460EX) && !defined(CONFIG_460GT)) && \ - defined(CONFIG_NET_MULTI) +#if (defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)) && defined(CONFIG_NET_MULTI) unsigned long zmii; unsigned long eoffset; /* Need to find out which mdi port we're using */ - zmii = in_be32((void *)ZMII_FER); + zmii = in32 (ZMII_FER); - if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) + if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) { /* using port 0 */ eoffset = 0; - - else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) + } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) { /* using port 1 */ eoffset = 0x100; - - else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) + } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) { /* using port 2 */ eoffset = 0x400; - - else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) + } else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) { /* using port 3 */ eoffset = 0x600; - - else { + } else { /* None of the mdi ports are enabled! */ /* enable port 0 */ zmii |= ZMII_FER_MDI << ZMII_FER_V (0); - out_be32((void *)ZMII_FER, zmii); + out32 (ZMII_FER, zmii); eoffset = 0; /* need to soft reset port 0 */ - zmii = in_be32((void *)EMAC_M0); + zmii = in32 (EMAC_M0); zmii |= EMAC_M0_SRST; - out_be32((void *)EMAC_M0, zmii); + out32 (EMAC_M0, zmii); } return (eoffset); #else - -#if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX) - unsigned long rgmii; - int devnum = 1; - - rgmii = in_be32((void *)RGMII_FER); - if (rgmii & (1 << (19 - devnum))) - return 0x100; -#endif - return 0; #endif } -static int emac_miiphy_wait(u32 emac_reg) + +int emac4xx_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) { - u32 sta_reg; - int i; - - /* wait for completion */ - i = 0; - do { - sta_reg = in_be32((void *)EMAC_STACR + emac_reg); - if (i++ > 5) { - debug("%s [%d]: Timeout! EMAC_STACR=0x%0x\n", __func__, - __LINE__, sta_reg); - return -1; - } - udelay(10); - } while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK); - - return 0; -} - -static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) -{ - u32 emac_reg; - u32 sta_reg; - - emac_reg = miiphy_getemac_offset(); - - /* wait for completion */ - if (emac_miiphy_wait(emac_reg) != 0) - return -1; - - sta_reg = reg; /* reg address */ - - /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) -#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ - sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd; -#else - sta_reg |= cmd; -#endif -#else - sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ; -#endif - - /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */ - sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; - sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */ - sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ - if (cmd == EMAC_STACR_WRITE) - memcpy(&sta_reg, &value, 2); /* put in data */ - - out_be32((void *)EMAC_STACR + emac_reg, sta_reg); - debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg); - - /* wait for completion */ - if (emac_miiphy_wait(emac_reg) != 0) - return -1; - - debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg); - if ((sta_reg & EMAC_STACR_PHYE) != 0) - return -1; - - return 0; -} - -int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - unsigned long sta_reg; + unsigned long sta_reg; /* STA scratch area */ + unsigned long i; unsigned long emac_reg; + emac_reg = miiphy_getemac_offset (); + /* see if it is ready for 1000 nsec */ + i = 0; - if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0) + /* see if it is ready for sec */ + while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + udelay (7); + if (i > 5) { +#ifdef ET_DEBUG + sta_reg = in32 (EMAC_STACR + emac_reg); + printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ + printf ("read err 1\n"); +#endif + return -1; + } + i++; + } + sta_reg = reg; /* reg address */ + /* set clock (50Mhz) and read flags */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; +#else + sta_reg |= EMAC_STACR_READ; +#endif +#else + sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; +#endif + +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE) + sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; +#endif + sta_reg = sta_reg | (addr << 5); /* Phy address */ + sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ + out32 (EMAC_STACR + emac_reg, sta_reg); +#ifdef ET_DEBUG + printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif + + sta_reg = in32 (EMAC_STACR + emac_reg); +#ifdef ET_DEBUG + printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif + i = 0; + while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + udelay (7); + if (i > 5) { + return -1; + } + i++; + sta_reg = in32 (EMAC_STACR + emac_reg); +#ifdef ET_DEBUG + printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif + } + if ((sta_reg & EMAC_STACR_PHYE) != 0) { return -1; + } - sta_reg = in_be32((void *)EMAC_STACR + emac_reg); - *value = *(u16 *)(&sta_reg); - + *value = *(short *) (&sta_reg); return 0; -} + + +} /* phy_read */ + /***********************************************************/ /* write a phy reg and return the value with a rc */ /***********************************************************/ -int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg, - unsigned short value) +int emac4xx_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) { - return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value); -} + unsigned long sta_reg; /* STA scratch area */ + unsigned long i; + unsigned long emac_reg; + + emac_reg = miiphy_getemac_offset (); + /* see if it is ready for 1000 nsec */ + i = 0; + + while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + if (i > 5) + return -1; + udelay (7); + i++; + } + sta_reg = 0; + sta_reg = reg; /* reg address */ + /* set clock (50Mhz) and read flags */ +#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) +#if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ + sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; +#else + sta_reg |= EMAC_STACR_WRITE; +#endif +#else + sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; +#endif + +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && !defined(CONFIG__440SP) && !defined(CONFIG__440SPE) + sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ +#endif + sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */ + sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ + memcpy (&sta_reg, &value, 2); /* put in data */ + + out32 (EMAC_STACR + emac_reg, sta_reg); + + /* wait for completion */ + i = 0; + sta_reg = in32 (EMAC_STACR + emac_reg); +#ifdef ET_DEBUG + printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif + while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + udelay (7); + if (i > 5) + return -1; + i++; + sta_reg = in32 (EMAC_STACR + emac_reg); +#ifdef ET_DEBUG + printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ +#endif + } + + if ((sta_reg & EMAC_STACR_PHYE) != 0) + return -1; + return 0; + +} /* phy_write */ diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 7d60ad667..faeea5c91 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005-2007 + * (C) Copyright 2005-2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2006 @@ -31,11 +31,10 @@ #include #include #include "sdram.h" -#include "ecc.h" + #ifdef CONFIG_SDRAM_BANK0 -#ifndef CONFIG_440 #ifndef CFG_SDRAM_TABLE sdram_conf_t mb0cf[] = { @@ -51,6 +50,9 @@ sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE; #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) + +#ifndef CONFIG_440 + #ifdef CFG_SDRAM_CASL static ulong ns2clks(ulong ns) { @@ -164,7 +166,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh) /* * Autodetect onboard SDRAM on 405 platforms */ -phys_size_t initdram(int board_type) +void sdram_init(void) { ulong speed; ulong sdtr1; @@ -188,14 +190,14 @@ phys_size_t initdram(int board_type) /* * Disable memory controller. */ - mtsdram(mem_mcopt1, 0x00000000); + mtsdram0(mem_mcopt1, 0x00000000); /* * Set MB0CF for bank 0. */ - mtsdram(mem_mb0cf, mb0cf[i].reg); - mtsdram(mem_sdtr1, sdtr1); - mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64)); + mtsdram0(mem_mb0cf, mb0cf[i].reg); + mtsdram0(mem_sdtr1, sdtr1); + mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64)); udelay(200); @@ -204,67 +206,21 @@ phys_size_t initdram(int board_type) * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst * read/prefetch. */ - mtsdram(mem_mcopt1, 0x80800000); + mtsdram0(mem_mcopt1, 0x80800000); udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { - /* - * OK, size detected. Enable second bank if - * defined (assumes same type as bank 0) - */ -#ifdef CONFIG_SDRAM_BANK1 - u32 b1cr = mb0cf[i].size | mb0cf[i].reg; - - mtsdram(mem_mcopt1, 0x00000000); - mtsdram(mem_mb1cf, b1cr); /* SDRAM0_B1CR */ - mtsdram(mem_mcopt1, 0x80800000); - udelay(10000); - - /* - * Check if 2nd bank is really available. - * If the size not equal to the size of the first - * bank, then disable the 2nd bank completely. - */ - if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) != - mb0cf[i].size) { - mtsdram(mem_mb1cf, 0); - mtsdram(mem_mcopt1, 0); - } -#endif - /* * OK, size detected -> all done */ - return mb0cf[i].size; + return; } } - - return 0; } #else /* CONFIG_440 */ -/* - * Define some default values. Those can be overwritten in the - * board config file. - */ - -#ifndef CFG_SDRAM_TABLE -sdram_conf_t mb0cf[] = { - {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */ - {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */ -}; -#else -sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE; -#endif - -#ifndef CFG_SDRAM0_TR0 -#define CFG_SDRAM0_TR0 0x41094012 -#endif - -#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) - #define NUM_TRIES 64 #define NUM_READS 10 @@ -339,6 +295,50 @@ static void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } + +#ifdef CONFIG_SDRAM_ECC +static void ecc_init(ulong start, ulong size) +{ + ulong current_addr; /* current byte address */ + ulong end_addr; /* end of memory region */ + ulong addr_inc; /* address skip between writes */ + ulong cfg0_reg; /* for restoring ECC state */ + + /* + * TODO: Enable dcache before running this test (speedup) + */ + + mfsdram(mem_cfg0, cfg0_reg); + mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN); + + /* + * look at geometry of SDRAM (data width) to determine whether we + * can skip words when writing + */ + if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32) + addr_inc = 4; + else + addr_inc = 8; + + current_addr = start; + end_addr = start + size; + + while (current_addr < end_addr) { + *((ulong *)current_addr) = 0x00000000; + current_addr += addr_inc; + } + + /* + * TODO: Flush dcache and disable it again + */ + + /* + * Enable ecc checking and parity errors + */ + mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK); +} +#endif + /* * Autodetect onboard DDR SDRAM on 440 platforms * @@ -346,20 +346,11 @@ static void sdram_tr1_set(int ram_address, int* tr1_value) * so this should be extended for other future boards * using this routine! */ -phys_size_t initdram(int board_type) +long int initdram(int board_type) { int i; int tr1_bank1; -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ - defined(CONFIG_440GR) || defined(CONFIG_440SP) - /* - * Soft-reset SDRAM controller. - */ - mtsdr(sdr_srst, SDR0_SRST_DMC); - mtsdr(sdr_srst, 0x00000000); -#endif - for (i=0; i +#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) + #define ONE_BILLION 1000000000 struct sdram_conf_s { diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c new file mode 100644 index 000000000..ad3ca6e81 --- /dev/null +++ b/cpu/ppc4xx/serial.c @@ -0,0 +1,1081 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/*------------------------------------------------------------------------------+ */ +/* + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + */ +/*------------------------------------------------------------------------------- */ +/* + * Travis Sawyer 15 September 2004 + * Added CONFIG_SERIAL_MULTI support + */ +#include +#include +#include +#include +#include "vecnum.h" + +#ifdef CONFIG_SERIAL_MULTI +#include +#endif + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/*****************************************************************************/ +#ifdef CONFIG_IOP480 + +#define SPU_BASE 0x40000000 + +#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */ +#define spu_LineStat_w 0x04 /* Line Status Register (Set) */ +#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */ +#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */ +#define spu_BRateDivh 0x10 /* Baud rate divisor high */ +#define spu_BRateDivl 0x14 /* Baud rate divisor low */ +#define spu_CtlReg 0x18 /* Control Register */ +#define spu_RxCmd 0x1c /* Rx Command Register */ +#define spu_TxCmd 0x20 /* Tx Command Register */ +#define spu_RxBuff 0x24 /* Rx data buffer */ +#define spu_TxBuff 0x24 /* Tx data buffer */ + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncLSRport1 0x40000000 +#define asyncLSRport1set 0x40000004 +#define asyncLSRDataReady 0x80 +#define asyncLSRFramingError 0x40 +#define asyncLSROverrunError 0x20 +#define asyncLSRParityError 0x10 +#define asyncLSRBreakInterrupt 0x08 +#define asyncLSRTxHoldEmpty 0x04 +#define asyncLSRTxShiftEmpty 0x02 + +/*-----------------------------------------------------------------------------+ + | Handshake Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncHSRport1 0x40000008 +#define asyncHSRport1set 0x4000000c +#define asyncHSRDsr 0x80 +#define asyncLSRCts 0x40 + +/*-----------------------------------------------------------------------------+ + | Control Register. + +-----------------------------------------------------------------------------*/ +#define asyncCRport1 0x40000018 +#define asyncCRNormal 0x00 +#define asyncCRLoopback 0x40 +#define asyncCRAutoEcho 0x80 +#define asyncCRDtr 0x20 +#define asyncCRRts 0x10 +#define asyncCRWordLength7 0x00 +#define asyncCRWordLength8 0x08 +#define asyncCRParityDisable 0x00 +#define asyncCRParityEnable 0x04 +#define asyncCREvenParity 0x00 +#define asyncCROddParity 0x02 +#define asyncCRStopBitsOne 0x00 +#define asyncCRStopBitsTwo 0x01 +#define asyncCRDisableDtrRts 0x00 + +/*-----------------------------------------------------------------------------+ + | Receiver Command Register. + +-----------------------------------------------------------------------------*/ +#define asyncRCRport1 0x4000001c +#define asyncRCRDisable 0x00 +#define asyncRCREnable 0x80 +#define asyncRCRIntDisable 0x00 +#define asyncRCRIntEnabled 0x20 +#define asyncRCRDMACh2 0x40 +#define asyncRCRDMACh3 0x60 +#define asyncRCRErrorInt 0x10 +#define asyncRCRPauseEnable 0x08 + +/*-----------------------------------------------------------------------------+ + | Transmitter Command Register. + +-----------------------------------------------------------------------------*/ +#define asyncTCRport1 0x40000020 +#define asyncTCRDisable 0x00 +#define asyncTCREnable 0x80 +#define asyncTCRIntDisable 0x00 +#define asyncTCRIntEnabled 0x20 +#define asyncTCRDMACh2 0x40 +#define asyncTCRDMACh3 0x60 +#define asyncTCRTxEmpty 0x10 +#define asyncTCRErrorInt 0x08 +#define asyncTCRStopPause 0x04 +#define asyncTCRBreakGen 0x02 + +/*-----------------------------------------------------------------------------+ + | Miscellanies defines. + +-----------------------------------------------------------------------------*/ +#define asyncTxBufferport1 0x40000024 +#define asyncRxBufferport1 0x40000024 +#define asyncDLABLsbport1 0x40000014 +#define asyncDLABMsbport1 0x40000010 +#define asyncXOFFchar 0x13 +#define asyncXONchar 0x11 + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +int serial_init (void) +{ + volatile char val; + unsigned short br_reg; + + br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); + + /* + * Init onboard UART + */ + out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */ + out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ + out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ + out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */ + out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */ + out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */ + out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ + + return (0); +} + +void serial_setbrg (void) +{ + unsigned short br_reg; + + br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); + + out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ + out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ +} + +void serial_putc (const char c) +{ + if (c == '\n') + serial_putc ('\r'); + + /* load status from handshake register */ + if (in8 (SPU_BASE + spu_Handshk_rc) != 00) + out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + + out8 (SPU_BASE + spu_TxBuff, c); /* Put char */ + + while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) { + if (in8 (SPU_BASE + spu_Handshk_rc) != 00) + out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + } +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc () +{ + unsigned char status = 0; + + while (1) { + status = in8 (asyncLSRport1); + if ((status & asyncLSRDataReady) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt )) != 0) { + (void) out8 (asyncLSRport1, + asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt ); + } + } + return (0x000000ff & (int) in8 (asyncRxBufferport1)); +} + +int serial_tstc () +{ + unsigned char status; + + status = in8 (asyncLSRport1); + if ((status & asyncLSRDataReady) != 0x0) { + return (1); + } + if ((status & ( asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt )) != 0) { + (void) out8 (asyncLSRport1, + asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt); + } + return 0; +} + +#endif /* CONFIG_IOP480 */ + +/*****************************************************************************/ +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP) + +#if defined(CONFIG_440) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 +#else +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#endif + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000600 +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#define CR0_MASK 0xdfffffff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#else +#define CR0_MASK 0x3fff0000 +#define CR0_EXTCLK_ENA 0x00600000 +#define CR0_UDIV_POS 16 +#endif /* CONFIG_440GX */ +#elif defined(CONFIG_405EP) +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define UCR0_MASK 0x0000007f +#define UCR1_MASK 0x00007f00 +#define UCR0_UDIV_POS 0 +#define UCR1_UDIV_POS 8 +#define UDIV_MAX 127 +#else /* CONFIG_405GP || CONFIG_405CR */ +#define UART0_BASE 0xef600300 +#define UART1_BASE 0xef600400 +#define CR0_MASK 0x00001fff +#define CR0_EXTCLK_ENA 0x000000c0 +#define CR0_UDIV_POS 1 +#define UDIV_MAX 32 +#endif + +/* using serial port 0 or 1 as U-Boot console ? */ +#if defined(CONFIG_UART1_CONSOLE) +#define ACTING_UART0_BASE UART1_BASE +#define ACTING_UART1_BASE UART0_BASE +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) +#define UART0_SDR sdr_uart1 +#define UART1_SDR sdr_uart0 +#endif /* CONFIG_440GX */ +#else +#define ACTING_UART0_BASE UART0_BASE +#define ACTING_UART1_BASE UART1_BASE +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 +#endif /* CONFIG_440GX */ +#endif + +#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) +#error "External serial clock not supported on AMCC PPC405EP!" +#endif + +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */ +#define asyncLSRDataReady1 0x01 +#define asyncLSROverrunError1 0x02 +#define asyncLSRParityError1 0x04 +#define asyncLSRFramingError1 0x08 +#define asyncLSRBreakInterrupt1 0x10 +#define asyncLSRTxHoldEmpty1 0x20 +#define asyncLSRTxShiftEmpty1 0x40 +#define asyncLSRRxFifoError1 0x80 + +/*-----------------------------------------------------------------------------+ + | Miscellanies defines. + +-----------------------------------------------------------------------------*/ +/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */ +/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */ + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO +/*-----------------------------------------------------------------------------+ + | Fifo + +-----------------------------------------------------------------------------*/ +typedef struct { + char *rx_buffer; + ulong rx_put; + ulong rx_get; +} serial_buffer_t; + +volatile static serial_buffer_t buf_info; +#endif + +#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK) +static void serial_divs (int baudrate, unsigned long *pudiv, + unsigned short *pbdiv ) +{ + sys_info_t sysinfo; + unsigned long div; /* total divisor udiv * bdiv */ + unsigned long umin; /* minimum udiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ + unsigned long i; + unsigned long est; /* current estimate */ + + get_sys_info( &sysinfo ); + + udiv = 32; /* Assume lowest possible serial clk */ + div = sysinfo.freqPLB/(16*baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */ + diff = 32; /* highest possible */ + + /* i is the test udiv value -- start with the largest + * possible (32) to minimize serial clock and constrain + * search to umin. + */ + for( i = 32; i > umin; i-- ){ + ibdiv = div/i; + est = i * ibdiv; + idiff = (est > div) ? (est-div) : (div-est); + if( idiff == 0 ){ + udiv = i; + break; /* can't do better */ + } + else if( idiff < diff ){ + udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ + } + } + + *pudiv = udiv; + *pbdiv = div/udiv; + +} +#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */ + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +#if defined(CONFIG_440) +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else +int serial_init(void) +#endif +{ + unsigned long reg; + unsigned long udiv; + unsigned short bdiv; + volatile char val; +#ifdef CFG_EXT_SERIAL_CLOCK + unsigned long tmp; +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) +#if defined(CONFIG_SERIAL_MULTI) + if (UART0_BASE == dev_base) { + mfsdr(UART0_SDR,reg); + reg &= ~CR0_MASK; + } else { + mfsdr(UART1_SDR,reg); + reg &= ~CR0_MASK; + } +#else + mfsdr(UART0_SDR,reg); + reg &= ~CR0_MASK; +#endif +#else + reg = mfdcr(cntrl0) & ~CR0_MASK; +#endif /* CONFIG_440GX */ +#ifdef CFG_EXT_SERIAL_CLOCK + reg |= CR0_EXTCLK_ENA; + udiv = 1; + tmp = gd->baudrate * 16; + bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; +#else + /* For 440, the cpu clock is on divider chain A, UART on divider + * chain B ... so cpu clock is irrelevant. Get the "optimized" + * values that are subject to the 1/2 opb clock constraint + */ + serial_divs (gd->baudrate, &udiv, &bdiv); +#endif + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) + reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */ +#if defined(CONFIG_SERIAL_MULTI) + if (UART0_BASE == dev_base) { + mtsdr (UART0_SDR,reg); + } else { + mtsdr (UART1_SDR,reg); + } +#else + mtsdr (UART0_SDR,reg); +#endif +#else + reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ + mtdcr (cntrl0, reg); +#endif + +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */ + out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (dev_base + UART_LSR); /* clear line status */ + val = in8 (dev_base + UART_RBR); /* read receive buffer */ + out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */ + out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */ +#else + out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ + val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ + out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +#endif + return (0); +} + +#else /* !defined(CONFIG_440) */ + +#if defined(CONFIG_SERIAL_MULTI) +int serial_init_dev (unsigned long dev_base) +#else +int serial_init (void) +#endif +{ + unsigned long reg; + unsigned long tmp; + unsigned long clk; + unsigned long udiv; + unsigned short bdiv; + volatile char val; + +#ifdef CONFIG_405EP + reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); + clk = gd->cpu_clk; + tmp = CFG_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; + reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ + reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ + mtdcr (cpc0_ucr, reg); +#else /* CONFIG_405EP */ + reg = mfdcr(cntrl0) & ~CR0_MASK; +#ifdef CFG_EXT_SERIAL_CLOCK + clk = CFG_EXT_SERIAL_CLOCK; + udiv = 1; + reg |= CR0_EXTCLK_ENA; +#else + clk = gd->cpu_clk; +#ifdef CFG_405_UART_ERRATA_59 + udiv = 31; /* Errata 59: stuck at 31 */ +#else + tmp = CFG_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; +#endif +#endif + reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ + mtdcr (cntrl0, reg); +#endif /* CONFIG_405EP */ + + tmp = gd->baudrate * udiv * 16; + bdiv = (clk + tmp / 2) / tmp; + +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */ + out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (dev_base + UART_LSR); /* clear line status */ + val = in8 (dev_base + UART_RBR); /* read receive buffer */ + out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */ + out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */ +#else + out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */ + val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */ + out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +#endif + return (0); +} + +#endif /* if defined(CONFIG_440) */ + +#if defined(CONFIG_SERIAL_MULTI) +void serial_setbrg_dev (unsigned long dev_base) +#else +void serial_setbrg (void) +#endif +{ + unsigned long tmp; + unsigned long clk; + unsigned long udiv; + unsigned short bdiv; + +#ifdef CFG_EXT_SERIAL_CLOCK + clk = CFG_EXT_SERIAL_CLOCK; +#else + clk = gd->cpu_clk; +#endif + +#ifdef CONFIG_405EP + udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS); +#else + udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1; +#endif /* CONFIG_405EP */ + +#if !defined(CFG_EXT_SERIAL_CLOCK) && \ + ( defined(CONFIG_440GX) || defined(CONFIG_440EP) || \ + defined(CONFIG_440GR) || defined(CONFIG_440SP) || \ + defined(CONFIG_440SPE) ) + serial_divs (gd->baudrate, &udiv, &bdiv); + tmp = udiv << CR0_UDIV_POS; /* set the UART divisor */ +#if defined(CONFIG_SERIAL_MULTI) + if (UART0_BASE == dev_base) { + mtsdr (UART0_SDR, tmp); + } else { + mtsdr (UART1_SDR, tmp); + } +#else + mtsdr (UART0_SDR, tmp); +#endif + +#else + + tmp = gd->baudrate * udiv * 16; + bdiv = (clk + tmp / 2) / tmp; +#endif /* !defined(CFG_EXT_SERIAL_CLOCK) && (...) */ + +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ +#else + out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */ + out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ +#endif +} + +#if defined(CONFIG_SERIAL_MULTI) +void serial_putc_dev (unsigned long dev_base, const char c) +#else +void serial_putc (const char c) +#endif +{ + int i; + + if (c == '\n') +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, '\r'); +#else + serial_putc ('\r'); +#endif + + /* check THRE bit, wait for transmiter available */ + for (i = 1; i < 3500; i++) { +#if defined(CONFIG_SERIAL_MULTI) + if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20) +#else + if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20) +#endif + break; + udelay (100); + } +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_THR, c); /* put character out */ +#else + out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */ +#endif +} + +#if defined(CONFIG_SERIAL_MULTI) +void serial_puts_dev (unsigned long dev_base, const char *s) +#else +void serial_puts (const char *s) +#endif +{ + while (*s) { +#if defined(CONFIG_SERIAL_MULTI) + serial_putc_dev (dev_base, *s++); +#else + serial_putc (*s++); +#endif + } +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_getc_dev (unsigned long dev_base) +#else +int serial_getc (void) +#endif +{ + unsigned char status = 0; + + while (1) { +#if defined(CONFIG_HW_WATCHDOG) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ +#endif /* CONFIG_HW_WATCHDOG */ +#if defined(CONFIG_SERIAL_MULTI) + status = in8 (dev_base + UART_LSR); +#else + status = in8 (ACTING_UART0_BASE + UART_LSR); +#endif + if ((status & asyncLSRDataReady1) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LSR, +#else + out8 (ACTING_UART0_BASE + UART_LSR, +#endif + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + } +#if defined(CONFIG_SERIAL_MULTI) + return (0x000000ff & (int) in8 (dev_base)); +#else + return (0x000000ff & (int) in8 (ACTING_UART0_BASE)); +#endif +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_tstc_dev (unsigned long dev_base) +#else +int serial_tstc (void) +#endif +{ + unsigned char status; + +#if defined(CONFIG_SERIAL_MULTI) + status = in8 (dev_base + UART_LSR); +#else + status = in8 (ACTING_UART0_BASE + UART_LSR); +#endif + if ((status & asyncLSRDataReady1) != 0x0) { + return (1); + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { +#if defined(CONFIG_SERIAL_MULTI) + out8 (dev_base + UART_LSR, +#else + out8 (ACTING_UART0_BASE + UART_LSR, +#endif + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + return 0; +} + +#ifdef CONFIG_SERIAL_SOFTWARE_FIFO + +void serial_isr (void *arg) +{ + int space; + int c; + const int rx_get = buf_info.rx_get; + int rx_put = buf_info.rx_put; + + if (rx_get <= rx_put) { + space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); + } else { + space = rx_get - rx_put; + } + while (serial_tstc_dev (ACTING_UART0_BASE)) { + c = serial_getc_dev (ACTING_UART0_BASE); + if (space) { + buf_info.rx_buffer[rx_put++] = c; + space--; + } + if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) + rx_put = 0; + if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { + /* Stop flow by setting RTS inactive */ + out8 (ACTING_UART0_BASE + UART_MCR, + in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); + } + } + buf_info.rx_put = rx_put; +} + +void serial_buffered_init (void) +{ + serial_puts ("Switching to interrupt driven serial input mode.\n"); + buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); + buf_info.rx_put = 0; + buf_info.rx_get = 0; + + if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) { + serial_puts ("Check CTS signal present on serial port: OK.\n"); + } else { + serial_puts ("WARNING: CTS signal not present on serial port.\n"); + } + + irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , + serial_isr /*interrupt_handler_t *handler */ , + (void *) &buf_info /*void *arg */ ); + + /* Enable "RX Data Available" Interrupt on UART */ + /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */ + out8 (ACTING_UART0_BASE + UART_IER, 0x01); + /* Set DTR active */ + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01); + /* Start flow by setting RTS active */ + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); + /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ + out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); +} + +void serial_buffered_putc (const char c) +{ + /* Wait for CTS */ +#if defined(CONFIG_HW_WATCHDOG) + while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) + WATCHDOG_RESET (); +#else + while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); +#endif + serial_putc (c); +} + +void serial_buffered_puts (const char *s) +{ + serial_puts (s); +} + +int serial_buffered_getc (void) +{ + int space; + int c; + int rx_get = buf_info.rx_get; + int rx_put; + +#if defined(CONFIG_HW_WATCHDOG) + while (rx_get == buf_info.rx_put) + WATCHDOG_RESET (); +#else + while (rx_get == buf_info.rx_put); +#endif + c = buf_info.rx_buffer[rx_get++]; + if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) + rx_get = 0; + buf_info.rx_get = rx_get; + + rx_put = buf_info.rx_put; + if (rx_get <= rx_put) { + space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); + } else { + space = rx_get - rx_put; + } + if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { + /* Start flow by setting RTS active */ + out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); + } + + return c; +} + +int serial_buffered_tstc (void) +{ + return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; +} + +#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +/* + AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port + number 0 or number 1 + - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : + configuration has been already done + - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : + configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE +*/ +#if (CONFIG_KGDB_SER_INDEX & 2) +void kgdb_serial_init (void) +{ + volatile char val; + unsigned short br_reg; + + get_clocks (); + br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) + + 5) / 10; + /* + * Init onboard 16550 UART + */ + out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ + out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ + out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ + out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ + out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */ + val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ + out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ + out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +} + +void putDebugChar (const char c) +{ + if (c == '\n') + serial_putc ('\r'); + + out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */ + + /* check THRE bit, wait for transfer done */ + while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); +} + +void putDebugStr (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int getDebugChar (void) +{ + unsigned char status = 0; + + while (1) { + status = in8 (ACTING_UART1_BASE + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { + out8 (ACTING_UART1_BASE + UART_LSR, + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } + } + return (0x000000ff & (int) in8 (ACTING_UART1_BASE)); +} + +void kgdb_interruptible (int yes) +{ + return; +} + +#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ + +void kgdb_serial_init (void) +{ + serial_printf ("[on serial] "); +} + +void putDebugChar (int c) +{ + serial_putc (c); +} + +void putDebugStr (const char *str) +{ + serial_puts (str); +} + +int getDebugChar (void) +{ + return serial_getc (); +} + +void kgdb_interruptible (int yes) +{ + return; +} +#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ +#endif /* CFG_CMD_KGDB */ + + +#if defined(CONFIG_SERIAL_MULTI) +int serial0_init(void) +{ + return (serial_init_dev(UART0_BASE)); +} + +int serial1_init(void) +{ + return (serial_init_dev(UART1_BASE)); +} +void serial0_setbrg (void) +{ + serial_setbrg_dev(UART0_BASE); +} +void serial1_setbrg (void) +{ + serial_setbrg_dev(UART1_BASE); +} + +void serial0_putc(const char c) +{ + serial_putc_dev(UART0_BASE,c); +} + +void serial1_putc(const char c) +{ + serial_putc_dev(UART1_BASE, c); +} +void serial0_puts(const char *s) +{ + serial_puts_dev(UART0_BASE, s); +} + +void serial1_puts(const char *s) +{ + serial_puts_dev(UART1_BASE, s); +} + +int serial0_getc(void) +{ + return(serial_getc_dev(UART0_BASE)); +} + +int serial1_getc(void) +{ + return(serial_getc_dev(UART1_BASE)); +} +int serial0_tstc(void) +{ + return (serial_tstc_dev(UART0_BASE)); +} + +int serial1_tstc(void) +{ + return (serial_tstc_dev(UART1_BASE)); +} + +struct serial_device serial0_device = +{ + "serial0", + "UART0", + serial0_init, + serial0_setbrg, + serial0_getc, + serial0_tstc, + serial0_putc, + serial0_puts, +}; + +struct serial_device serial1_device = +{ + "serial1", + "UART1", + serial1_init, + serial1_setbrg, + serial1_getc, + serial1_tstc, + serial1_putc, + serial1_puts, +}; +#endif /* CONFIG_SERIAL_MULTI */ + +#endif /* CONFIG_405GP || CONFIG_405CR */ diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c new file mode 100644 index 000000000..c24456bea --- /dev/null +++ b/cpu/ppc4xx/spd_sdram.c @@ -0,0 +1,1831 @@ +/* + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com + * + * Based on code by: + * + * Kenneth Johansson ,Ericsson AB. + * kenneth.johansson@etx.ericsson.se + * + * hacked up by bill hunter. fixed so we could run before + * serial_init and console_init. previous version avoided this by + * running out of cache memory during serial/console init, then running + * this code later. + * + * (C) Copyright 2002 + * Jun Gu, Artesyn Technology, jung@artesyncp.com + * Support for AMCC 440 based on OpenBIOS draminit.c from IBM. + * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#ifdef CONFIG_SPD_EEPROM + +/* + * Set default values + */ +#ifndef CFG_I2C_SPEED +#define CFG_I2C_SPEED 50000 +#endif + +#ifndef CFG_I2C_SLAVE +#define CFG_I2C_SLAVE 0xFE +#endif + +#define ONE_BILLION 1000000000 + +#ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */ + +#define SDRAM0_CFG_DCE 0x80000000 +#define SDRAM0_CFG_SRE 0x40000000 +#define SDRAM0_CFG_PME 0x20000000 +#define SDRAM0_CFG_MEMCHK 0x10000000 +#define SDRAM0_CFG_REGEN 0x08000000 +#define SDRAM0_CFG_ECCDD 0x00400000 +#define SDRAM0_CFG_EMDULR 0x00200000 +#define SDRAM0_CFG_DRW_SHIFT (31-6) +#define SDRAM0_CFG_BRPF_SHIFT (31-8) + +#define SDRAM0_TR_CASL_SHIFT (31-8) +#define SDRAM0_TR_PTA_SHIFT (31-13) +#define SDRAM0_TR_CTP_SHIFT (31-15) +#define SDRAM0_TR_LDF_SHIFT (31-17) +#define SDRAM0_TR_RFTA_SHIFT (31-29) +#define SDRAM0_TR_RCD_SHIFT (31-31) + +#define SDRAM0_RTR_SHIFT (31-15) +#define SDRAM0_ECCCFG_SHIFT (31-11) + +/* SDRAM0_CFG enable macro */ +#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT ) + +#define SDRAM0_BXCR_SZ_MASK 0x000e0000 +#define SDRAM0_BXCR_AM_MASK 0x0000e000 + +#define SDRAM0_BXCR_SZ_SHIFT (31-14) +#define SDRAM0_BXCR_AM_SHIFT (31-18) + +#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) ) +#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) ) + +#ifdef CONFIG_SPDDRAM_SILENT +# define SPD_ERR(x) do { return 0; } while (0) +#else +# define SPD_ERR(x) do { printf(x); return(0); } while (0) +#endif + +#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) + +/* function prototypes */ +int spd_read(uint addr); + + +/* + * This function is reading data from the DIMM module EEPROM over the SPD bus + * and uses that to program the sdram controller. + * + * This works on boards that has the same schematics that the AMCC walnut has. + * + * Input: null for default I2C spd functions or a pointer to a custom function + * returning spd_data. + */ + +long int spd_sdram(int(read_spd)(uint addr)) +{ + int tmp,row,col; + int total_size,bank_size,bank_code; + int ecc_on; + int mode; + int bank_cnt; + + int sdram0_pmit=0x07c00000; +#ifndef CONFIG_405EP /* not on PPC405EP */ + int sdram0_besr0=-1; + int sdram0_besr1=-1; + int sdram0_eccesr=-1; +#endif + int sdram0_ecccfg; + + int sdram0_rtr=0; + int sdram0_tr=0; + + int sdram0_b0cr; + int sdram0_b1cr; + int sdram0_b2cr; + int sdram0_b3cr; + + int sdram0_cfg=0; + + int t_rp; + int t_rcd; + int t_ras; + int t_rc; + int min_cas; + + PPC405_SYS_INFO sys_info; + unsigned long bus_period_x_10; + + /* + * get the board info + */ + get_sys_info(&sys_info); + bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); + + if (read_spd == 0){ + read_spd=spd_read; + /* + * Make sure I2C controller is initialized + * before continuing. + */ + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + } + + /* Make shure we are using SDRAM */ + if (read_spd(2) != 0x04) { + SPD_ERR("SDRAM - non SDRAM memory module found\n"); + } + + /* ------------------------------------------------------------------ + * configure memory timing register + * + * data from DIMM: + * 27 IN Row Precharge Time ( t RP) + * 29 MIN RAS to CAS Delay ( t RCD) + * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS + * -------------------------------------------------------------------*/ + + /* + * first figure out which cas latency mode to use + * use the min supported mode + */ + + tmp = read_spd(127) & 0x6; + if (tmp == 0x02) { /* only cas = 2 supported */ + min_cas = 2; +/* t_ck = read_spd(9); */ +/* t_ac = read_spd(10); */ + } else if (tmp == 0x04) { /* only cas = 3 supported */ + min_cas = 3; +/* t_ck = read_spd(9); */ +/* t_ac = read_spd(10); */ + } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */ + min_cas = 2; +/* t_ck = read_spd(23); */ +/* t_ac = read_spd(24); */ + } else { + SPD_ERR("SDRAM - unsupported CAS latency \n"); + } + + /* get some timing values, t_rp,t_rcd,t_ras,t_rc + */ + t_rp = read_spd(27); + t_rcd = read_spd(29); + t_ras = read_spd(30); + t_rc = t_ras + t_rp; + + /* The following timing calcs subtract 1 before deviding. + * this has effect of using ceiling instead of floor rounding, + * and also subtracting 1 to convert number to reg value + */ + /* set up CASL */ + sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT; + /* set up PTA */ + sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT; + /* set up CTP */ + tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3; + if (tmp < 1) + tmp = 1; + sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT; + /* set LDF = 2 cycles, reg value = 1 */ + sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT; + /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */ + tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3; + if (tmp < 0) + tmp = 0; + if (tmp > 6) + tmp = 6; + sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT; + /* set RCD = t_rcd/bus_period*/ + sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ; + + + /*------------------------------------------------------------------ + * configure RTR register + * -------------------------------------------------------------------*/ + row = read_spd(3); + col = read_spd(4); + tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */ + switch (tmp) { + case 0x00: + tmp = 15625; + break; + case 0x01: + tmp = 15625 / 4; + break; + case 0x02: + tmp = 15625 / 2; + break; + case 0x03: + tmp = 15625 * 2; + break; + case 0x04: + tmp = 15625 * 4; + break; + case 0x05: + tmp = 15625 * 8; + break; + default: + SPD_ERR("SDRAM - Bad refresh period \n"); + } + /* convert from nsec to bus cycles */ + tmp = (tmp * 10) / bus_period_x_10; + sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT; + + /*------------------------------------------------------------------ + * determine the number of banks used + * -------------------------------------------------------------------*/ + /* byte 7:6 is module data width */ + if (read_spd(7) != 0) + SPD_ERR("SDRAM - unsupported module width\n"); + tmp = read_spd(6); + if (tmp < 32) + SPD_ERR("SDRAM - unsupported module width\n"); + else if (tmp < 64) + bank_cnt = 1; /* one bank per sdram side */ + else if (tmp < 73) + bank_cnt = 2; /* need two banks per side */ + else if (tmp < 161) + bank_cnt = 4; /* need four banks per side */ + else + SPD_ERR("SDRAM - unsupported module width\n"); + + /* byte 5 is the module row count (refered to as dimm "sides") */ + tmp = read_spd(5); + if (tmp == 1) + ; + else if (tmp==2) + bank_cnt *= 2; + else if (tmp==4) + bank_cnt *= 4; + else + bank_cnt = 8; /* 8 is an error code */ + + if (bank_cnt > 4) /* we only have 4 banks to work with */ + SPD_ERR("SDRAM - unsupported module rows for this width\n"); + + /* now check for ECC ability of module. We only support ECC + * on 32 bit wide devices with 8 bit ECC. + */ + if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) { + sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT; + ecc_on = 1; + } else { + sdram0_ecccfg = 0; + ecc_on = 0; + } + + /*------------------------------------------------------------------ + * calculate total size + * -------------------------------------------------------------------*/ + /* calculate total size and do sanity check */ + tmp = read_spd(31); + total_size = 1 << 22; /* total_size = 4MB */ + /* now multiply 4M by the smallest device row density */ + /* note that we don't support asymetric rows */ + while (((tmp & 0x0001) == 0) && (tmp != 0)) { + total_size = total_size << 1; + tmp = tmp >> 1; + } + total_size *= read_spd(5); /* mult by module rows (dimm sides) */ + + /*------------------------------------------------------------------ + * map rows * cols * banks to a mode + * -------------------------------------------------------------------*/ + + switch (row) { + case 11: + switch (col) { + case 8: + mode=4; /* mode 5 */ + break; + case 9: + case 10: + mode=0; /* mode 1 */ + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + break; + case 12: + switch (col) { + case 8: + mode=3; /* mode 4 */ + break; + case 9: + case 10: + mode=1; /* mode 2 */ + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + break; + case 13: + switch (col) { + case 8: + mode=5; /* mode 6 */ + break; + case 9: + case 10: + if (read_spd(17) == 2) + mode = 6; /* mode 7 */ + else + mode = 2; /* mode 3 */ + break; + case 11: + mode = 2; /* mode 3 */ + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + break; + default: + SPD_ERR("SDRAM - unsupported mode\n"); + } + + /*------------------------------------------------------------------ + * using the calculated values, compute the bank + * config register values. + * -------------------------------------------------------------------*/ + sdram0_b1cr = 0; + sdram0_b2cr = 0; + sdram0_b3cr = 0; + + /* compute the size of each bank */ + bank_size = total_size / bank_cnt; + /* convert bank size to bank size code for ppc4xx + by takeing log2(bank_size) - 22 */ + tmp = bank_size; /* start with tmp = bank_size */ + bank_code = 0; /* and bank_code = 0 */ + while (tmp > 1) { /* this takes log2 of tmp */ + bank_code++; /* and stores result in bank_code */ + tmp = tmp >> 1; + } /* bank_code is now log2(bank_size) */ + bank_code -= 22; /* subtract 22 to get the code */ + + tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1; + sdram0_b0cr = (bank_size * 0) | tmp; +#ifndef CONFIG_405EP /* not on PPC405EP */ + if (bank_cnt > 1) + sdram0_b2cr = (bank_size * 1) | tmp; + if (bank_cnt > 2) + sdram0_b1cr = (bank_size * 2) | tmp; + if (bank_cnt > 3) + sdram0_b3cr = (bank_size * 3) | tmp; +#else + /* PPC405EP chip only supports two SDRAM banks */ + if (bank_cnt > 1) + sdram0_b1cr = (bank_size * 1) | tmp; + if (bank_cnt > 2) + total_size = 2 * bank_size; +#endif + + /* + * enable sdram controller DCE=1 + * enable burst read prefetch to 32 bytes BRPF=2 + * leave other functions off + */ + + /*------------------------------------------------------------------ + * now that we've done our calculations, we are ready to + * program all the registers. + * -------------------------------------------------------------------*/ + +#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) + /* disable memcontroller so updates work */ + mtsdram0( mem_mcopt1, 0 ); + +#ifndef CONFIG_405EP /* not on PPC405EP */ + mtsdram0( mem_besra , sdram0_besr0 ); + mtsdram0( mem_besrb , sdram0_besr1 ); + mtsdram0( mem_ecccf , sdram0_ecccfg ); + mtsdram0( mem_eccerr, sdram0_eccesr ); +#endif + mtsdram0( mem_rtr , sdram0_rtr ); + mtsdram0( mem_pmit , sdram0_pmit ); + mtsdram0( mem_mb0cf , sdram0_b0cr ); + mtsdram0( mem_mb1cf , sdram0_b1cr ); +#ifndef CONFIG_405EP /* not on PPC405EP */ + mtsdram0( mem_mb2cf , sdram0_b2cr ); + mtsdram0( mem_mb3cf , sdram0_b3cr ); +#endif + mtsdram0( mem_sdtr1 , sdram0_tr ); + + /* SDRAM have a power on delay, 500 micro should do */ + udelay(500); + sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR; + if (ecc_on) + sdram0_cfg |= SDRAM0_CFG_MEMCHK; + mtsdram0(mem_mcopt1, sdram0_cfg); + + return (total_size); +} + +int spd_read(uint addr) +{ + uchar data[2]; + + if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0) + return (int)data[0]; + else + return 0; +} + +#else /* CONFIG_440 */ + +/*----------------------------------------------------------------------------- + | Memory Controller Options 0 + +-----------------------------------------------------------------------------*/ +#define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */ +#define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */ +#define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */ +#define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */ +#define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */ +#define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */ +#define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */ +#define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */ +#define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */ +#define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */ +#define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */ +#define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */ + +/*----------------------------------------------------------------------------- + | Memory Controller Options 1 + +-----------------------------------------------------------------------------*/ +#define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */ +#define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */ + +/*-----------------------------------------------------------------------------+ + | SDRAM DEVPOT Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_DEVOPT_DLL 0x80000000 +#define SDRAM_DEVOPT_DS 0x40000000 + +/*-----------------------------------------------------------------------------+ + | SDRAM MCSTS Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_MCSTS_MRSC 0x80000000 +#define SDRAM_MCSTS_SRMS 0x40000000 +#define SDRAM_MCSTS_CIS 0x20000000 + +/*----------------------------------------------------------------------------- + | SDRAM Refresh Timer Register + +-----------------------------------------------------------------------------*/ +#define SDRAM_RTR_RINT_MASK 0xFFFF0000 +#define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK) +#define sdram_HZ_to_ns(hertz) (1000000000/(hertz)) + +/*-----------------------------------------------------------------------------+ + | SDRAM UABus Base Address Reg + +-----------------------------------------------------------------------------*/ +#define SDRAM_UABBA_UBBA_MASK 0x0000000F + +/*-----------------------------------------------------------------------------+ + | Memory Bank 0-7 configuration + +-----------------------------------------------------------------------------*/ +#define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */ +#define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */ +#define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */ +#define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */ +#define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */ +#define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */ +#define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */ +#define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */ +#define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */ +#define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */ +#define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */ +#define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */ +#define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */ +#define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */ +#define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */ + +/*-----------------------------------------------------------------------------+ + | SDRAM TR0 Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_TR0_SDWR_MASK 0x80000000 +#define SDRAM_TR0_SDWR_2_CLK 0x00000000 +#define SDRAM_TR0_SDWR_3_CLK 0x80000000 +#define SDRAM_TR0_SDWD_MASK 0x40000000 +#define SDRAM_TR0_SDWD_0_CLK 0x00000000 +#define SDRAM_TR0_SDWD_1_CLK 0x40000000 +#define SDRAM_TR0_SDCL_MASK 0x01800000 +#define SDRAM_TR0_SDCL_2_0_CLK 0x00800000 +#define SDRAM_TR0_SDCL_2_5_CLK 0x01000000 +#define SDRAM_TR0_SDCL_3_0_CLK 0x01800000 +#define SDRAM_TR0_SDPA_MASK 0x000C0000 +#define SDRAM_TR0_SDPA_2_CLK 0x00040000 +#define SDRAM_TR0_SDPA_3_CLK 0x00080000 +#define SDRAM_TR0_SDPA_4_CLK 0x000C0000 +#define SDRAM_TR0_SDCP_MASK 0x00030000 +#define SDRAM_TR0_SDCP_2_CLK 0x00000000 +#define SDRAM_TR0_SDCP_3_CLK 0x00010000 +#define SDRAM_TR0_SDCP_4_CLK 0x00020000 +#define SDRAM_TR0_SDCP_5_CLK 0x00030000 +#define SDRAM_TR0_SDLD_MASK 0x0000C000 +#define SDRAM_TR0_SDLD_1_CLK 0x00000000 +#define SDRAM_TR0_SDLD_2_CLK 0x00004000 +#define SDRAM_TR0_SDRA_MASK 0x0000001C +#define SDRAM_TR0_SDRA_6_CLK 0x00000000 +#define SDRAM_TR0_SDRA_7_CLK 0x00000004 +#define SDRAM_TR0_SDRA_8_CLK 0x00000008 +#define SDRAM_TR0_SDRA_9_CLK 0x0000000C +#define SDRAM_TR0_SDRA_10_CLK 0x00000010 +#define SDRAM_TR0_SDRA_11_CLK 0x00000014 +#define SDRAM_TR0_SDRA_12_CLK 0x00000018 +#define SDRAM_TR0_SDRA_13_CLK 0x0000001C +#define SDRAM_TR0_SDRD_MASK 0x00000003 +#define SDRAM_TR0_SDRD_2_CLK 0x00000001 +#define SDRAM_TR0_SDRD_3_CLK 0x00000002 +#define SDRAM_TR0_SDRD_4_CLK 0x00000003 + +/*-----------------------------------------------------------------------------+ + | SDRAM TR1 Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_TR1_RDSS_MASK 0xC0000000 +#define SDRAM_TR1_RDSS_TR0 0x00000000 +#define SDRAM_TR1_RDSS_TR1 0x40000000 +#define SDRAM_TR1_RDSS_TR2 0x80000000 +#define SDRAM_TR1_RDSS_TR3 0xC0000000 +#define SDRAM_TR1_RDSL_MASK 0x00C00000 +#define SDRAM_TR1_RDSL_STAGE1 0x00000000 +#define SDRAM_TR1_RDSL_STAGE2 0x00400000 +#define SDRAM_TR1_RDSL_STAGE3 0x00800000 +#define SDRAM_TR1_RDCD_MASK 0x00000800 +#define SDRAM_TR1_RDCD_RCD_0_0 0x00000000 +#define SDRAM_TR1_RDCD_RCD_1_2 0x00000800 +#define SDRAM_TR1_RDCT_MASK 0x000001FF +#define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK) +#define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0) +#define SDRAM_TR1_RDCT_MIN 0x00000000 +#define SDRAM_TR1_RDCT_MAX 0x000001FF + +/*-----------------------------------------------------------------------------+ + | SDRAM WDDCTR Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_WDDCTR_WRCP_MASK 0xC0000000 +#define SDRAM_WDDCTR_WRCP_0DEG 0x00000000 +#define SDRAM_WDDCTR_WRCP_90DEG 0x40000000 +#define SDRAM_WDDCTR_WRCP_180DEG 0x80000000 +#define SDRAM_WDDCTR_DCD_MASK 0x000001FF + +/*-----------------------------------------------------------------------------+ + | SDRAM CLKTR Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 +#define SDRAM_CLKTR_CLKP_0DEG 0x00000000 +#define SDRAM_CLKTR_CLKP_90DEG 0x40000000 +#define SDRAM_CLKTR_CLKP_180DEG 0x80000000 +#define SDRAM_CLKTR_DCDT_MASK 0x000001FF + +/*-----------------------------------------------------------------------------+ + | SDRAM DLYCAL Options + +-----------------------------------------------------------------------------*/ +#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC +#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK) +#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2) + +/*-----------------------------------------------------------------------------+ + | General Definition + +-----------------------------------------------------------------------------*/ +#define DEFAULT_SPD_ADDR1 0x53 +#define DEFAULT_SPD_ADDR2 0x52 +#define MAXBANKS 4 /* at most 4 dimm banks */ +#define MAX_SPD_BYTES 256 +#define NUMHALFCYCLES 4 +#define NUMMEMTESTS 8 +#define NUMMEMWORDS 8 +#define MAXBXCR 4 +#define TRUE 1 +#define FALSE 0 + +const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { + {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF}, + {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000}, + {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555}, + {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA}, + {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A}, + {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5}, + {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA}, + {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55} +}; + +/* bank_parms is used to sort the bank sizes by descending order */ +struct bank_param { + unsigned long cr; + unsigned long bank_size_bytes; +}; + +typedef struct bank_param BANKPARMS; + +#ifdef CFG_SIMULATE_SPD_EEPROM +extern unsigned char cfg_simulate_spd_eeprom[128]; +#endif + +unsigned char spd_read(uchar chip, uint addr); + +void get_spd_info(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void check_mem_type +(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void check_volt_type +(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void program_cfg0(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void program_cfg1(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void program_rtr (unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void program_tr0 (unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +void program_tr1 (void); + +void program_ecc (unsigned long num_bytes); + +unsigned +long program_bxcr(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks); + +/* + * This function is reading data from the DIMM module EEPROM over the SPD bus + * and uses that to program the sdram controller. + * + * This works on boards that has the same schematics that the AMCC walnut has. + * + * BUG: Don't handle ECC memory + * BUG: A few values in the TR register is currently hardcoded + */ + +long int spd_sdram(void) { + unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; + unsigned long dimm_populated[sizeof(iic0_dimm_addr)]; + unsigned long total_size; + unsigned long cfg0; + unsigned long mcsts; + unsigned long num_dimm_banks; /* on board dimm banks */ + + num_dimm_banks = sizeof(iic0_dimm_addr); + + /* + * Make sure I2C controller is initialized + * before continuing. + */ + i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* + * Read the SPD information using I2C interface. Check to see if the + * DIMM slots are populated. + */ + get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * Check the memory type for the dimms plugged. + */ + check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * Check the voltage type for the dimms plugged. + */ + check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); + +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) + /* + * Soft-reset SDRAM controller. + */ + mtsdr(sdr_srst, SDR0_SRST_DMC); + mtsdr(sdr_srst, 0x00000000); +#endif + + /* + * program 440GP SDRAM controller options (SDRAM0_CFG0) + */ + program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program 440GP SDRAM controller options (SDRAM0_CFG1) + */ + program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program SDRAM refresh register (SDRAM0_RTR) + */ + program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program SDRAM Timing Register 0 (SDRAM0_TR0) + */ + program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks); + + /* + * program the BxCR registers to find out total sdram installed + */ + total_size = program_bxcr(dimm_populated, iic0_dimm_addr, + num_dimm_banks); + + /* + * program SDRAM Clock Timing Register (SDRAM0_CLKTR) + */ + mtsdram(mem_clktr, 0x40000000); + + /* + * delay to ensure 200 usec has elapsed + */ + udelay(400); + + /* + * enable the memory controller + */ + mfsdram(mem_cfg0, cfg0); + mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN); + + /* + * wait for SDRAM_CFG0_DC_EN to complete + */ + while (1) { + mfsdram(mem_mcsts, mcsts); + if ((mcsts & SDRAM_MCSTS_MRSC) != 0) { + break; + } + } + + /* + * program SDRAM Timing Register 1, adding some delays + */ + program_tr1(); + + /* + * if ECC is enabled, initialize parity bits + */ + + return total_size; +} + +unsigned char spd_read(uchar chip, uint addr) +{ + unsigned char data[2]; + +#ifdef CFG_SIMULATE_SPD_EEPROM + if (chip == CFG_SIMULATE_SPD_EEPROM) { + /* + * Onboard spd eeprom requested -> simulate values + */ + return cfg_simulate_spd_eeprom[addr]; + } +#endif /* CFG_SIMULATE_SPD_EEPROM */ + + if (i2c_probe(chip) == 0) { + if (i2c_read(chip, addr, 1, data, 1) == 0) { + return data[0]; + } + } + + return 0; +} + +void get_spd_info(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long dimm_found; + unsigned char num_of_bytes; + unsigned char total_size; + + dimm_found = FALSE; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + num_of_bytes = 0; + total_size = 0; + + num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); + total_size = spd_read(iic0_dimm_addr[dimm_num], 1); + + if ((num_of_bytes != 0) && (total_size != 0)) { + dimm_populated[dimm_num] = TRUE; + dimm_found = TRUE; +#if 0 + printf("DIMM slot %lu: populated\n", dimm_num); +#endif + } else { + dimm_populated[dimm_num] = FALSE; +#if 0 + printf("DIMM slot %lu: Not populated\n", dimm_num); +#endif + } + } + + if (dimm_found == FALSE) { + printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); + hang(); + } +} + +void check_mem_type(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned char dimm_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); + switch (dimm_type) { + case 7: +#if 0 + printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num); +#endif + break; + default: + printf("ERROR: Unsupported DIMM detected in slot %lu.\n", + dimm_num); + printf("Only DDR SDRAM DIMMs are supported.\n"); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + hang(); + break; + } + } + } +} + + +void check_volt_type(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long voltage_type; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); + if (voltage_type != 0x04) { + printf("ERROR: DIMM %lu with unsupported voltage level.\n", + dimm_num); + hang(); + } else { +#if 0 + printf("DIMM %lu voltage level supported.\n", dimm_num); +#endif + } + break; + } + } +} + +void program_cfg0(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long cfg0; + unsigned long ecc_enabled; + unsigned char ecc; + unsigned char attributes; + unsigned long data_width; + unsigned long dimm_32bit; + unsigned long dimm_64bit; + + /* + * get Memory Controller Options 0 data + */ + mfsdram(mem_cfg0, cfg0); + + /* + * clear bits + */ + cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK | + SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD | + SDRAM_CFG0_DMWD_MASK | + SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP); + + + /* + * FIXME: assume the DDR SDRAMs in both banks are the same + */ + ecc_enabled = TRUE; + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + ecc = spd_read(iic0_dimm_addr[dimm_num], 11); + if (ecc != 0x02) { + ecc_enabled = FALSE; + } + + /* + * program Registered DIMM Enable + */ + attributes = spd_read(iic0_dimm_addr[dimm_num], 21); + if ((attributes & 0x02) != 0x00) { + cfg0 |= SDRAM_CFG0_RDEN; + } + + /* + * program DDR SDRAM Data Width + */ + data_width = + (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) + + (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8); + if (data_width == 64 || data_width == 72) { + dimm_64bit = TRUE; + cfg0 |= SDRAM_CFG0_DMWD_64; + } else if (data_width == 32 || data_width == 40) { + dimm_32bit = TRUE; + cfg0 |= SDRAM_CFG0_DMWD_32; + } else { + printf("WARNING: DIMM with datawidth of %lu bits.\n", + data_width); + printf("Only DIMMs with 32 or 64 bit datawidths supported.\n"); + hang(); + } + break; + } + } + + /* + * program Memory Data Error Checking + */ + if (ecc_enabled == TRUE) { + cfg0 |= SDRAM_CFG0_MCHK_GEN; + } else { + cfg0 |= SDRAM_CFG0_MCHK_NON; + } + + /* + * program Page Management Unit (0 == enabled) + */ + cfg0 &= ~SDRAM_CFG0_PMUD; + + /* + * program Memory Controller Options 0 + * Note: DCEN must be enabled after all DDR SDRAM controller + * configuration registers get initialized. + */ + mtsdram(mem_cfg0, cfg0); +} + +void program_cfg1(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long cfg1; + mfsdram(mem_cfg1, cfg1); + + /* + * Self-refresh exit, disable PM + */ + cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN); + + /* + * program Memory Controller Options 1 + */ + mtsdram(mem_cfg1, cfg1); +} + +void program_rtr (unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long bus_period_x_10; + unsigned long refresh_rate = 0; + unsigned char refresh_rate_type; + unsigned long refresh_interval; + unsigned long sdram_rtr; + PPC440_SYS_INFO sys_info; + + /* + * get the board info + */ + get_sys_info(&sys_info); + bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); + + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); + switch (refresh_rate_type) { + case 0x00: + refresh_rate = 15625; + break; + case 0x01: + refresh_rate = 15625/4; + break; + case 0x02: + refresh_rate = 15625/2; + break; + case 0x03: + refresh_rate = 15626*2; + break; + case 0x04: + refresh_rate = 15625*4; + break; + case 0x05: + refresh_rate = 15625*8; + break; + default: + printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n", + dimm_num); + printf("Replace the DIMM module with a supported DIMM.\n"); + break; + } + + break; + } + } + + refresh_interval = refresh_rate * 10 / bus_period_x_10; + sdram_rtr = (refresh_interval & 0x3ff8) << 16; + + /* + * program Refresh Timer Register (SDRAM0_RTR) + */ + mtsdram(mem_rtr, sdram_rtr); +} + +void program_tr0 (unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long tr0; + unsigned char wcsbc; + unsigned char t_rp_ns; + unsigned char t_rcd_ns; + unsigned char t_ras_ns; + unsigned long t_rp_clk; + unsigned long t_ras_rcd_clk; + unsigned long t_rcd_clk; + unsigned long t_rfc_clk; + unsigned long plb_check; + unsigned char cas_bit; + unsigned long cas_index; + unsigned char cas_2_0_available; + unsigned char cas_2_5_available; + unsigned char cas_3_0_available; + unsigned long cycle_time_ns_x_10[3]; + unsigned long tcyc_3_0_ns_x_10; + unsigned long tcyc_2_5_ns_x_10; + unsigned long tcyc_2_0_ns_x_10; + unsigned long tcyc_reg; + unsigned long bus_period_x_10; + PPC440_SYS_INFO sys_info; + unsigned long residue; + + /* + * get the board info + */ + get_sys_info(&sys_info); + bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); + + /* + * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits + */ + mfsdram(mem_tr0, tr0); + tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK | + SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK | + SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK | + SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK); + + /* + * initialization + */ + wcsbc = 0; + t_rp_ns = 0; + t_rcd_ns = 0; + t_ras_ns = 0; + cas_2_0_available = TRUE; + cas_2_5_available = TRUE; + cas_3_0_available = TRUE; + tcyc_2_0_ns_x_10 = 0; + tcyc_2_5_ns_x_10 = 0; + tcyc_3_0_ns_x_10 = 0; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); + t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; + t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; + t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30); + cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); + + for (cas_index = 0; cas_index < 3; cas_index++) { + switch (cas_index) { + case 0: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); + break; + case 1: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23); + break; + default: + tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25); + break; + } + + if ((tcyc_reg & 0x0F) >= 10) { + printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n", + dimm_num); + hang(); + } + + cycle_time_ns_x_10[cas_index] = + (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F); + } + + cas_index = 0; + + if ((cas_bit & 0x80) != 0) { + cas_index += 3; + } else if ((cas_bit & 0x40) != 0) { + cas_index += 2; + } else if ((cas_bit & 0x20) != 0) { + cas_index += 1; + } + + if (((cas_bit & 0x10) != 0) && (cas_index < 3)) { + tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; + cas_index++; + } else { + if (cas_index != 0) { + cas_index++; + } + cas_3_0_available = FALSE; + } + + if (((cas_bit & 0x08) != 0) || (cas_index < 3)) { + tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index]; + cas_index++; + } else { + if (cas_index != 0) { + cas_index++; + } + cas_2_5_available = FALSE; + } + + if (((cas_bit & 0x04) != 0) || (cas_index < 3)) { + tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index]; + cas_index++; + } else { + if (cas_index != 0) { + cas_index++; + } + cas_2_0_available = FALSE; + } + + break; + } + } + + /* + * Program SD_WR and SD_WCSBC fields + */ + tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */ + switch (wcsbc) { + case 0: + tr0 |= SDRAM_TR0_SDWD_0_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDWD_1_CLK; + break; + } + + /* + * Program SD_CASL field + */ + if ((cas_2_0_available == TRUE) && + (bus_period_x_10 >= tcyc_2_0_ns_x_10)) { + tr0 |= SDRAM_TR0_SDCL_2_0_CLK; + } else if ((cas_2_5_available == TRUE) && + (bus_period_x_10 >= tcyc_2_5_ns_x_10)) { + tr0 |= SDRAM_TR0_SDCL_2_5_CLK; + } else if ((cas_3_0_available == TRUE) && + (bus_period_x_10 >= tcyc_3_0_ns_x_10)) { + tr0 |= SDRAM_TR0_SDCL_3_0_CLK; + } else { + printf("ERROR: No supported CAS latency with the installed DIMMs.\n"); + printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); + printf("Make sure the PLB speed is within the supported range.\n"); + hang(); + } + + /* + * Calculate Trp in clock cycles and round up if necessary + * Program SD_PTA field + */ + t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION; + plb_check = ONE_BILLION * t_rp_clk / t_rp_ns; + if (sys_info.freqPLB != plb_check) { + t_rp_clk++; + } + switch ((unsigned long)t_rp_clk) { + case 0: + case 1: + case 2: + tr0 |= SDRAM_TR0_SDPA_2_CLK; + break; + case 3: + tr0 |= SDRAM_TR0_SDPA_3_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDPA_4_CLK; + break; + } + + /* + * Program SD_CTP field + */ + t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION; + plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns); + if (sys_info.freqPLB != plb_check) { + t_ras_rcd_clk++; + } + switch (t_ras_rcd_clk) { + case 0: + case 1: + case 2: + tr0 |= SDRAM_TR0_SDCP_2_CLK; + break; + case 3: + tr0 |= SDRAM_TR0_SDCP_3_CLK; + break; + case 4: + tr0 |= SDRAM_TR0_SDCP_4_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDCP_5_CLK; + break; + } + + /* + * Program SD_LDF field + */ + tr0 |= SDRAM_TR0_SDLD_2_CLK; + + /* + * Program SD_RFTA field + * FIXME tRFC hardcoded as 75 nanoseconds + */ + t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75); + residue = sys_info.freqPLB % (ONE_BILLION / 75); + if (residue >= (ONE_BILLION / 150)) { + t_rfc_clk++; + } + switch (t_rfc_clk) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + tr0 |= SDRAM_TR0_SDRA_6_CLK; + break; + case 7: + tr0 |= SDRAM_TR0_SDRA_7_CLK; + break; + case 8: + tr0 |= SDRAM_TR0_SDRA_8_CLK; + break; + case 9: + tr0 |= SDRAM_TR0_SDRA_9_CLK; + break; + case 10: + tr0 |= SDRAM_TR0_SDRA_10_CLK; + break; + case 11: + tr0 |= SDRAM_TR0_SDRA_11_CLK; + break; + case 12: + tr0 |= SDRAM_TR0_SDRA_12_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDRA_13_CLK; + break; + } + + /* + * Program SD_RCD field + */ + t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION; + plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns; + if (sys_info.freqPLB != plb_check) { + t_rcd_clk++; + } + switch (t_rcd_clk) { + case 0: + case 1: + case 2: + tr0 |= SDRAM_TR0_SDRD_2_CLK; + break; + case 3: + tr0 |= SDRAM_TR0_SDRD_3_CLK; + break; + default: + tr0 |= SDRAM_TR0_SDRD_4_CLK; + break; + } + +#if 0 + printf("tr0: %x\n", tr0); +#endif + mtsdram(mem_tr0, tr0); +} + +void program_tr1 (void) +{ + unsigned long tr0; + unsigned long tr1; + unsigned long cfg0; + unsigned long ecc_temp; + unsigned long dlycal; + unsigned long dly_val; + unsigned long i, j, k; + unsigned long bxcr_num; + unsigned long max_pass_length; + unsigned long current_pass_length; + unsigned long current_fail_length; + unsigned long current_start; + unsigned long rdclt; + unsigned long rdclt_offset; + long max_start; + long max_end; + long rdclt_average; + unsigned char window_found; + unsigned char fail_found; + unsigned char pass_found; + unsigned long * membase; + PPC440_SYS_INFO sys_info; + + /* + * get the board info + */ + get_sys_info(&sys_info); + + /* + * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits + */ + mfsdram(mem_tr1, tr1); + tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK | + SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK); + + mfsdram(mem_tr0, tr0); + if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) && + (sys_info.freqPLB > 100000000)) { + tr1 |= SDRAM_TR1_RDSS_TR2; + tr1 |= SDRAM_TR1_RDSL_STAGE3; + tr1 |= SDRAM_TR1_RDCD_RCD_1_2; + } else { + tr1 |= SDRAM_TR1_RDSS_TR1; + tr1 |= SDRAM_TR1_RDSL_STAGE2; + tr1 |= SDRAM_TR1_RDCD_RCD_0_0; + } + + /* + * save CFG0 ECC setting to a temporary variable and turn ECC off + */ + mfsdram(mem_cfg0, cfg0); + ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK; + mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON); + + /* + * get the delay line calibration register value + */ + mfsdram(mem_dlycal, dlycal); + dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2; + + max_pass_length = 0; + max_start = 0; + max_end = 0; + current_pass_length = 0; + current_fail_length = 0; + current_start = 0; + rdclt_offset = 0; + window_found = FALSE; + fail_found = FALSE; + pass_found = FALSE; +#ifdef DEBUG + printf("Starting memory test "); +#endif + for (k = 0; k < NUMHALFCYCLES; k++) { + for (rdclt = 0; rdclt < dly_val; rdclt++) { + /* + * Set the timing reg for the test. + */ + mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); + + for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { + mtdcr(memcfga, mem_b0cr + (bxcr_num<<2)); + if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { + /* Bank is enabled */ + membase = (unsigned long*) + (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK); + + /* + * Run the short memory test + */ + for (i = 0; i < NUMMEMTESTS; i++) { + for (j = 0; j < NUMMEMWORDS; j++) { + membase[j] = test[i][j]; + ppcDcbf((unsigned long)&(membase[j])); + } + + for (j = 0; j < NUMMEMWORDS; j++) { + if (membase[j] != test[i][j]) { + ppcDcbf((unsigned long)&(membase[j])); + break; + } + ppcDcbf((unsigned long)&(membase[j])); + } + + if (j < NUMMEMWORDS) { + break; + } + } + + /* + * see if the rdclt value passed + */ + if (i < NUMMEMTESTS) { + break; + } + } + } + + if (bxcr_num == MAXBXCR) { + if (fail_found == TRUE) { + pass_found = TRUE; + if (current_pass_length == 0) { + current_start = rdclt_offset + rdclt; + } + + current_fail_length = 0; + current_pass_length++; + + if (current_pass_length > max_pass_length) { + max_pass_length = current_pass_length; + max_start = current_start; + max_end = rdclt_offset + rdclt; + } + } + } else { + current_pass_length = 0; + current_fail_length++; + + if (current_fail_length >= (dly_val>>2)) { + if (fail_found == FALSE) { + fail_found = TRUE; + } else if (pass_found == TRUE) { + window_found = TRUE; + break; + } + } + } + } +#ifdef DEBUG + printf("."); +#endif + if (window_found == TRUE) { + break; + } + + tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; + rdclt_offset += dly_val; + } +#ifdef DEBUG + printf("\n"); +#endif + + /* + * make sure we find the window + */ + if (window_found == FALSE) { + printf("ERROR: Cannot determine a common read delay.\n"); + hang(); + } + + /* + * restore the orignal ECC setting + */ + mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp); + + /* + * set the SDRAM TR1 RDCD value + */ + tr1 &= ~SDRAM_TR1_RDCD_MASK; + if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) { + tr1 |= SDRAM_TR1_RDCD_RCD_1_2; + } else { + tr1 |= SDRAM_TR1_RDCD_RCD_0_0; + } + + /* + * set the SDRAM TR1 RDCLT value + */ + tr1 &= ~SDRAM_TR1_RDCT_MASK; + while (max_end >= (dly_val << 1)) { + max_end -= (dly_val << 1); + max_start -= (dly_val << 1); + } + + rdclt_average = ((max_start + max_end) >> 1); + if (rdclt_average >= 0x60) + while (1) + ; + + if (rdclt_average < 0) { + rdclt_average = 0; + } + + if (rdclt_average >= dly_val) { + rdclt_average -= dly_val; + tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; + } + tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average); + +#if 0 + printf("tr1: %x\n", tr1); +#endif + /* + * program SDRAM Timing Register 1 TR1 + */ + mtsdram(mem_tr1, tr1); +} + +unsigned long program_bxcr(unsigned long* dimm_populated, + unsigned char* iic0_dimm_addr, + unsigned long num_dimm_banks) +{ + unsigned long dimm_num; + unsigned long bank_base_addr; + unsigned long cr; + unsigned long i; + unsigned long j; + unsigned long temp; + unsigned char num_row_addr; + unsigned char num_col_addr; + unsigned char num_banks; + unsigned char bank_size_id; + unsigned long ctrl_bank_num[MAXBANKS]; + unsigned long bx_cr_num; + unsigned long largest_size_index; + unsigned long largest_size; + unsigned long current_size_index; + BANKPARMS bank_parms[MAXBXCR]; + unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */ + unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/ + + /* + * Set the BxCR regs. First, wipe out the bank config registers. + */ + for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { + mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2)); + mtdcr(memcfgd, 0x00000000); + bank_parms[bx_cr_num].bank_size_bytes = 0; + } + +#ifdef CONFIG_BAMBOO + /* + * This next section is hardware dependent and must be programmed + * to match the hardware. For bammboo, the following holds... + * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 + * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1 + * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1 + * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3 + * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM + */ + ctrl_bank_num[0] = 0; + ctrl_bank_num[1] = 1; + ctrl_bank_num[2] = 3; +#else + ctrl_bank_num[0] = 0; + ctrl_bank_num[1] = 1; + ctrl_bank_num[2] = 2; + ctrl_bank_num[3] = 3; +#endif + + /* + * reset the bank_base address + */ + bank_base_addr = CFG_SDRAM_BASE; + + for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { + if (dimm_populated[dimm_num] == TRUE) { + num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3); + num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); + num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); + bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); + + /* + * Set the SDRAM0_BxCR regs + */ + cr = 0; + switch (bank_size_id) { + case 0x02: + cr |= SDRAM_BXCR_SDSZ_8; + break; + case 0x04: + cr |= SDRAM_BXCR_SDSZ_16; + break; + case 0x08: + cr |= SDRAM_BXCR_SDSZ_32; + break; + case 0x10: + cr |= SDRAM_BXCR_SDSZ_64; + break; + case 0x20: + cr |= SDRAM_BXCR_SDSZ_128; + break; + case 0x40: + cr |= SDRAM_BXCR_SDSZ_256; + break; + case 0x80: + cr |= SDRAM_BXCR_SDSZ_512; + break; + default: + printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", + dimm_num); + printf("ERROR: Unsupported value for the banksize: %d.\n", + bank_size_id); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + hang(); + } + + switch (num_col_addr) { + case 0x08: + cr |= SDRAM_BXCR_SDAM_1; + break; + case 0x09: + cr |= SDRAM_BXCR_SDAM_2; + break; + case 0x0A: + cr |= SDRAM_BXCR_SDAM_3; + break; + case 0x0B: + cr |= SDRAM_BXCR_SDAM_4; + break; + default: + printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n", + dimm_num); + printf("ERROR: Unsupported value for number of " + "column addresses: %d.\n", num_col_addr); + printf("Replace the DIMM module with a supported DIMM.\n\n"); + hang(); + } + + /* + * enable the bank + */ + cr |= SDRAM_BXCR_SDBE; + + for (i = 0; i < num_banks; i++) { + bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = + (4 * 1024 * 1024) * bank_size_id; + bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; + } + } + } + + /* Initialize sort tables */ + for (i = 0; i < MAXBXCR; i++) { + sorted_bank_num[i] = i; + sorted_bank_size[i] = bank_parms[i].bank_size_bytes; + } + + for (i = 0; i < MAXBXCR-1; i++) { + largest_size = sorted_bank_size[i]; + largest_size_index = 255; + + /* Find the largest remaining value */ + for (j = i + 1; j < MAXBXCR; j++) { + if (sorted_bank_size[j] > largest_size) { + /* Save largest remaining value and its index */ + largest_size = sorted_bank_size[j]; + largest_size_index = j; + } + } + + if (largest_size_index != 255) { + /* Swap the current and largest values */ + current_size_index = sorted_bank_num[largest_size_index]; + sorted_bank_size[largest_size_index] = sorted_bank_size[i]; + sorted_bank_size[i] = largest_size; + sorted_bank_num[largest_size_index] = sorted_bank_num[i]; + sorted_bank_num[i] = current_size_index; + } + } + + /* Set the SDRAM0_BxCR regs thanks to sort tables */ + for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { + if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { + mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); + temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | + SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); + temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | + bank_parms[sorted_bank_num[bx_cr_num]].cr; + mtdcr(memcfgd, temp); + bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; + } + } + + return(bank_base_addr); +} + +void program_ecc (unsigned long num_bytes) +{ + unsigned long bank_base_addr; + unsigned long current_address; + unsigned long end_address; + unsigned long address_increment; + unsigned long cfg0; + + /* + * get Memory Controller Options 0 data + */ + mfsdram(mem_cfg0, cfg0); + + /* + * reset the bank_base address + */ + bank_base_addr = CFG_SDRAM_BASE; + + if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { + mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | + SDRAM_CFG0_MCHK_GEN); + + if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) { + address_increment = 4; + } else { + address_increment = 8; + } + + current_address = (unsigned long)(bank_base_addr); + end_address = (unsigned long)(bank_base_addr) + num_bytes; + + while (current_address < end_address) { + *((unsigned long*)current_address) = 0x00000000; + current_address += address_increment; + } + + mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | + SDRAM_CFG0_MCHK_CHK); + } +} + +#endif /* CONFIG_440 */ + +#endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 34bd7214e..e552c0347 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -35,11 +35,9 @@ DECLARE_GLOBAL_DATA_PTR; #define DEBUGF(fmt,args...) #endif -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - #if defined(CONFIG_405GP) || defined(CONFIG_405CR) -void get_sys_info (PPC4xx_SYS_INFO * sysInfo) +void get_sys_info (PPC405_SYS_INFO * sysInfo) { unsigned long pllmr; unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); @@ -164,10 +162,6 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv; } } - - sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv; - - sysInfo->freqUART = sysInfo->freqProcessor; } @@ -179,7 +173,7 @@ ulong get_OPB_freq (void) { ulong val = 0; - PPC4xx_SYS_INFO sys_info; + PPC405_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllOpbDiv; @@ -195,7 +189,7 @@ ulong get_OPB_freq (void) ulong get_PCI_freq (void) { ulong val; - PPC4xx_SYS_INFO sys_info; + PPC405_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllPciDiv; @@ -205,127 +199,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -static u8 pll_fwdv_multi_bits[] = { - /* values for: 1 - 16 */ - 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, - 0x05, 0x08, 0x07, 0x02, 0x0b, 0x06 -}; - -u32 get_cpr0_fwdv(unsigned long cpr_reg_fwdv) -{ - u32 index; - - for (index = 0; index < ARRAY_SIZE(pll_fwdv_multi_bits); index++) - if (cpr_reg_fwdv == (u32)pll_fwdv_multi_bits[index]) - return index + 1; - - return 0; -} - -static u8 pll_fbdv_multi_bits[] = { - /* values for: 1 - 100 */ - 0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4, - 0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb, - 0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96, - 0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde, - 0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb, - 0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91, - 0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b, - 0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95, - 0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4, - 0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc, - /* values for: 101 - 200 */ - 0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3, - 0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90, - 0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe, - 0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6, - 0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd, - 0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1, - 0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6, - 0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9, - 0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e, - 0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf, - /* values for: 201 - 255 */ - 0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae, - 0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2, - 0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2, - 0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98, - 0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81, - 0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */ -}; - -u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) -{ - u32 index; - - for (index = 0; index < ARRAY_SIZE(pll_fbdv_multi_bits); index++) - if (cpr_reg_fbdv == (u32)pll_fbdv_multi_bits[index]) - return index + 1; - - return 0; -} - -/* - * AMCC_TODO: verify this routine against latest EAS, cause stuff changed - * with latest EAS - */ -void get_sys_info (sys_info_t * sysInfo) -{ - unsigned long strp0; - unsigned long strp1; - unsigned long temp; - unsigned long m; - unsigned long plbedv0; - - /* Extract configured divisors */ - mfsdr(sdr_sdstp0, strp0); - mfsdr(sdr_sdstp1, strp1); - - temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4); - sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); - - temp = (strp0 & PLLSYS0_FWD_DIV_B_MASK); - sysInfo->pllFwdDivB = get_cpr0_fwdv(temp); - - temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 8; - sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); - - temp = (strp1 & PLLSYS0_OPB_DIV_MASK) >> 26; - sysInfo->pllOpbDiv = temp ? temp : 4; - - /* AMCC_TODO: verify the SDR0_SDSTP1.PERDV0 value sysInfo->pllExtBusDiv */ - temp = (strp1 & PLLSYS0_PERCLK_DIV_MASK) >> 24; - sysInfo->pllExtBusDiv = temp ? temp : 4; - - temp = (strp1 & PLLSYS0_PLBEDV0_DIV_MASK) >> 29; - plbedv0 = temp ? temp: 8; - - /* Calculate 'M' based on feedback source */ - temp = (strp0 & PLLSYS0_SEL_MASK) >> 27; - if (temp == 0) { - /* PLL internal feedback */ - m = sysInfo->pllFbkDiv; - } else { - /* PLL PerClk feedback */ - m = sysInfo->pllFwdDivA * plbedv0 * sysInfo->pllOpbDiv * - sysInfo->pllExtBusDiv; - } - - /* Now calculate the individual clocks */ - sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m >> 1); - sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; - sysInfo->freqPLB = sysInfo->freqVCOMhz / sysInfo->pllFwdDivA / plbedv0; - sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; - sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; - sysInfo->freqDDR = sysInfo->freqPLB; - sysInfo->freqUART = sysInfo->freqPLB; - - return; -} - -#elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) void get_sys_info (sys_info_t *sysInfo) { unsigned long temp; @@ -341,7 +215,7 @@ void get_sys_info (sys_info_t *sysInfo) */ /* Decode CPR0_PLLD0 for divisors */ - mfcpr(clk_plld, reg); + mfclk(clk_plld, reg); temp = (reg & PLLD_FWDVA_MASK) >> 16; sysInfo->pllFwdDivA = temp ? temp : 16; temp = (reg & PLLD_FWDVB_MASK) >> 8; @@ -350,19 +224,19 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->pllFbkDiv = temp ? temp : 32; lfdiv = reg & PLLD_LFBDV_MASK; - mfcpr(clk_opbd, reg); + mfclk(clk_opbd, reg); temp = (reg & OPBDDV_MASK) >> 24; sysInfo->pllOpbDiv = temp ? temp : 4; - mfcpr(clk_perd, reg); + mfclk(clk_perd, reg); temp = (reg & PERDV_MASK) >> 24; sysInfo->pllExtBusDiv = temp ? temp : 8; - mfcpr(clk_primbd, reg); + mfclk(clk_primbd, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; - mfcpr(clk_spcid, reg); + mfclk(clk_spcid, reg); temp = (reg & SPCID_MASK) >> 24; sysInfo->pllPciDiv = temp ? temp : 4; @@ -371,7 +245,7 @@ void get_sys_info (sys_info_t *sysInfo) temp = (reg & PLLSYS0_SEL_MASK) >> 27; if (temp == 0) { /* PLL output */ /* Figure which pll to use */ - mfcpr(clk_pllc, reg); + mfclk(clk_pllc, reg); temp = (reg & PLLC_SRC_MASK) >> 29; if (!temp) /* PLLOUTA */ m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA; @@ -388,9 +262,8 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEBC = sysInfo->freqPLB/sysInfo->pllExtBusDiv; + sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv; sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv; - sysInfo->freqUART = sysInfo->freqPLB; /* Figure which timer source to use */ if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */ @@ -403,7 +276,6 @@ void get_sys_info (sys_info_t *sysInfo) else /* Internal clock */ sysInfo->freqTmrClk = sysInfo->freqProcessor; } - /******************************************** * get_PCI_freq * return PCI bus freq in Hz @@ -444,8 +316,8 @@ void get_sys_info (sys_info_t * sysInfo) if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */ sysInfo->freqPLB >>= 1; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv; - sysInfo->freqUART = sysInfo->freqPLB; + sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; + } #else void get_sys_info (sys_info_t * sysInfo) @@ -458,7 +330,7 @@ void get_sys_info (sys_info_t * sysInfo) unsigned long m; unsigned long prbdv0; -#if defined(CONFIG_YUCCA) +#if defined(CONFIG_440SPE) unsigned long sys_freq; unsigned long sys_per=0; unsigned long msr; @@ -475,7 +347,7 @@ void get_sys_info (sys_info_t * sysInfo) /*-------------------------------------------------------------------------+ | Calculate the system clock speed from the period. +-------------------------------------------------------------------------*/ - sys_freq = (ONE_BILLION / sys_per) * 1000; + sys_freq=(ONE_BILLION/sys_per)*1000; #endif /* Extract configured divisors */ @@ -512,17 +384,17 @@ void get_sys_info (sys_info_t * sysInfo) m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB; /* Now calculate the individual clocks */ -#if defined(CONFIG_YUCCA) +#if defined(CONFIG_440SPE) sysInfo->freqVCOMhz = (m * sys_freq) ; #else - sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m >> 1); + sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1); #endif sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv; + sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; -#if defined(CONFIG_YUCCA) +#if defined(CONFIG_440SPE) /* Determine PCI Clock Period */ pci_clock_per = determine_pci_clock_per(); sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000; @@ -530,12 +402,12 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); #endif - sysInfo->freqUART = sysInfo->freqPLB; + } #endif -#if defined(CONFIG_YUCCA) +#if defined(CONFIG_440SPE) unsigned long determine_sysper(void) { unsigned int fpga_clocking_reg; @@ -710,6 +582,7 @@ unsigned long determine_sysper(void) } return(sys_per); + } /*-------------------------------------------------------------------------+ @@ -754,13 +627,12 @@ ulong get_OPB_freq (void) return sys_info.freqOPB; } -#elif defined(CONFIG_XILINX_405) +#elif defined(CONFIG_XILINX_ML300) extern void get_sys_info (sys_info_t * sysInfo); extern ulong get_PCI_freq (void); #elif defined(CONFIG_AP1000) -void get_sys_info (sys_info_t * sysInfo) -{ +void get_sys_info (sys_info_t * sysInfo) { sysInfo->freqProcessor = 240 * 1000 * 1000; sysInfo->freqPLB = 80 * 1000 * 1000; sysInfo->freqPCI = 33 * 1000 * 1000; @@ -768,16 +640,17 @@ void get_sys_info (sys_info_t * sysInfo) #elif defined(CONFIG_405) -void get_sys_info (sys_info_t * sysInfo) -{ +void get_sys_info (sys_info_t * sysInfo) { + sysInfo->freqVCOMhz=3125000; sysInfo->freqProcessor=12*1000*1000; sysInfo->freqPLB=50*1000*1000; sysInfo->freqPCI=66*1000*1000; + } #elif defined(CONFIG_405EP) -void get_sys_info (PPC4xx_SYS_INFO * sysInfo) +void get_sys_info (PPC405_SYS_INFO * sysInfo) { unsigned long pllmr0; unsigned long pllmr1; @@ -805,8 +678,9 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) * Determine FBK_DIV. */ sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20); - if (sysInfo->pllFbkDiv == 0) + if (sysInfo->pllFbkDiv == 0) { sysInfo->pllFbkDiv = 16; + } /* * Determine PLB_DIV. @@ -859,10 +733,6 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) * Determine PLB clock frequency */ sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv; - - sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv; - - sysInfo->freqUART = sysInfo->freqProcessor * pllmr0_ccdv; } @@ -874,7 +744,7 @@ ulong get_OPB_freq (void) { ulong val = 0; - PPC4xx_SYS_INFO sys_info; + PPC405_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllOpbDiv; @@ -890,296 +760,18 @@ ulong get_OPB_freq (void) ulong get_PCI_freq (void) { ulong val; - PPC4xx_SYS_INFO sys_info; + PPC405_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllPciDiv; return val; } -#elif defined(CONFIG_405EZ) -void get_sys_info (PPC4xx_SYS_INFO * sysInfo) -{ - unsigned long cpr_plld; - unsigned long cpr_pllc; - unsigned long cpr_primad; - unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000); - unsigned long primad_cpudv; - unsigned long m; - - /* - * Read PLL Mode registers - */ - mfcpr(cprplld, cpr_plld); - mfcpr(cprpllc, cpr_pllc); - - /* - * Determine forward divider A - */ - sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16); - - /* - * Determine forward divider B - */ - sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8); - if (sysInfo->pllFwdDivB == 0) - sysInfo->pllFwdDivB = 8; - - /* - * Determine FBK_DIV. - */ - sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (sysInfo->pllFbkDiv == 0) - sysInfo->pllFbkDiv = 256; - - /* - * Read CPR_PRIMAD register - */ - mfcpr(cprprimad, cpr_primad); - - /* - * Determine PLB_DIV. - */ - sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16); - if (sysInfo->pllPlbDiv == 0) - sysInfo->pllPlbDiv = 16; - - /* - * Determine EXTBUS_DIV. - */ - sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK); - if (sysInfo->pllExtBusDiv == 0) - sysInfo->pllExtBusDiv = 16; - - /* - * Determine OPB_DIV. - */ - sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8); - if (sysInfo->pllOpbDiv == 0) - sysInfo->pllOpbDiv = 16; - - /* - * Determine the M factor - */ - if (cpr_pllc & PLLC_SRC_MASK) - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB; - else - m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv; - - /* - * Determine VCO clock frequency - */ - sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / - (unsigned long long)sysClkPeriodPs; - - /* - * Determine CPU clock frequency - */ - primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); - if (primad_cpudv == 0) - primad_cpudv = 16; - - sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * m) / - sysInfo->pllFwdDiv / primad_cpudv; - - /* - * Determine PLB clock frequency - */ - sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) / - sysInfo->pllFwdDiv / sysInfo->pllPlbDiv; - - sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / - sysInfo->pllExtBusDiv; - - sysInfo->freqUART = sysInfo->freqVCOHz; -} - -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC4xx_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv; - - return val; -} - -#elif defined(CONFIG_405EX) - -/* - * TODO: We need to get the CPR registers and calculate these values correctly!!!! - * We need the specs!!!! - */ -static unsigned char get_fbdv(unsigned char index) -{ - unsigned char ret = 0; - /* This is table should be 256 bytes. - * Only take first 52 values. - */ - unsigned char fbdv_tb[] = { - 0x00, 0xff, 0x7f, 0xfd, - 0x7a, 0xf5, 0x6a, 0xd5, - 0x2a, 0xd4, 0x29, 0xd3, - 0x26, 0xcc, 0x19, 0xb3, - 0x67, 0xce, 0x1d, 0xbb, - 0x77, 0xee, 0x5d, 0xba, - 0x74, 0xe9, 0x52, 0xa5, - 0x4b, 0x96, 0x2c, 0xd8, - 0x31, 0xe3, 0x46, 0x8d, - 0x1b, 0xb7, 0x6f, 0xde, - 0x3d, 0xfb, 0x76, 0xed, - 0x5a, 0xb5, 0x6b, 0xd6, - 0x2d, 0xdb, 0x36, 0xec, - - }; - - if ((index & 0x7f) == 0) - return 1; - while (ret < sizeof (fbdv_tb)) { - if (fbdv_tb[ret] == index) - break; - ret++; - } - ret++; - - return ret; -} - -#define PLL_FBK_PLL_LOCAL 0 -#define PLL_FBK_CPU 1 -#define PLL_FBK_PERCLK 5 - -void get_sys_info (sys_info_t * sysInfo) -{ - unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); - unsigned long m = 1; - unsigned int tmp; - unsigned char fwdva[16] = { - 1, 2, 14, 9, 4, 11, 16, 13, - 12, 5, 6, 15, 10, 7, 8, 3, - }; - unsigned char sel, cpudv0, plb2xDiv; - - mfcpr(cpr0_plld, tmp); - - /* - * Determine forward divider A - */ - sysInfo->pllFwdDiv = fwdva[((tmp >> 16) & 0x0f)]; /* FWDVA */ - - /* - * Determine FBK_DIV. - */ - sysInfo->pllFbkDiv = get_fbdv(((tmp >> 24) & 0x0ff)); /* FBDV */ - - /* - * Determine PLBDV0 - */ - sysInfo->pllPlbDiv = 2; - - /* - * Determine PERDV0 - */ - mfcpr(cpr0_perd, tmp); - tmp = (tmp >> 24) & 0x03; - sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp; - - /* - * Determine OPBDV0 - */ - mfcpr(cpr0_opbd, tmp); - tmp = (tmp >> 24) & 0x03; - sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp; - - /* Determine PLB2XDV0 */ - mfcpr(cpr0_plbd, tmp); - tmp = (tmp >> 16) & 0x07; - plb2xDiv = (tmp == 0) ? 8 : tmp; - - /* Determine CPUDV0 */ - mfcpr(cpr0_cpud, tmp); - tmp = (tmp >> 24) & 0x07; - cpudv0 = (tmp == 0) ? 8 : tmp; - - /* Determine SEL(5:7) in CPR0_PLLC */ - mfcpr(cpr0_pllc, tmp); - sel = (tmp >> 24) & 0x07; - - /* - * Determine the M factor - * PLL local: M = FBDV - * CPU clock: M = FBDV * FWDVA * CPUDV0 - * PerClk : M = FBDV * FWDVA * PLB2XDV0 * PLBDV0(2) * OPBDV0 * PERDV0 - * - */ - switch (sel) { - case PLL_FBK_CPU: - m = sysInfo->pllFwdDiv * cpudv0; - break; - case PLL_FBK_PERCLK: - m = sysInfo->pllFwdDiv * plb2xDiv * 2 - * sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv; - break; - case PLL_FBK_PLL_LOCAL: - break; - default: - printf("%s unknown m\n", __FUNCTION__); - return; - - } - m *= sysInfo->pllFbkDiv; - - /* - * Determine VCO clock frequency - */ - sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / - (unsigned long long)sysClkPeriodPs; - - /* - * Determine CPU clock frequency - */ - sysInfo->freqProcessor = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * cpudv0); - - /* - * Determine PLB clock frequency, ddr1x should be the same - */ - sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * plb2xDiv * 2); - sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqDDR = sysInfo->freqPLB; - sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; - sysInfo->freqUART = sysInfo->freqPLB; -} - -/******************************************** - * get_OPB_freq - * return OPB bus freq in Hz - *********************************************/ -ulong get_OPB_freq (void) -{ - ulong val = 0; - - PPC4xx_SYS_INFO sys_info; - - get_sys_info (&sys_info); - val = sys_info.freqPLB / sys_info.pllOpbDiv; - - return val; -} - #endif int get_clocks (void) { -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || defined(CONFIG_405) || \ - defined(CONFIG_440) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP) sys_info_t sys_info; get_sys_info (&sys_info); @@ -1204,10 +796,7 @@ ulong get_bus_freq (ulong dummy) { ulong val; -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || defined(CONFIG_405) || \ - defined(CONFIG_440) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP) sys_info_t sys_info; get_sys_info (&sys_info); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 426bf3c6f..699fa7fd7 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -2,9 +2,6 @@ * Copyright (C) 1998 Dan Malek * Copyright (C) 1999 Magnus Damm * Copyright (C) 2000,2001,2002 Wolfgang Denk - * Copyright (C) 2007 Stefan Roese , DENX Software Engineering - * Copyright (c) 2008 Nuovation System Designs, LLC - * Grant Erickson * * See file CREDITS for list of people who contributed to this * project. @@ -24,27 +21,26 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -/*------------------------------------------------------------------------------+ - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *------------------------------------------------------------------------------- - */ +/*------------------------------------------------------------------------------+ */ +/* */ +/* This source code has been made available to you by IBM on an AS-IS */ +/* basis. Anyone receiving this source is licensed under IBM */ +/* copyrights to use it in any way he or she deems fit, including */ +/* copying it, modifying it, compiling it, and redistributing it either */ +/* with or without modifications. No license under IBM patents or */ +/* patent applications is to be implied by the copyright license. */ +/* */ +/* Any user of this software should understand that IBM cannot provide */ +/* technical support for this software and will not be responsible for */ +/* any consequences resulting from the use of this software. */ +/* */ +/* Any person who transfers this source code or any derivative work */ +/* must include the IBM copyright notice, this paragraph, and the */ +/* preceding two paragraphs in the transferred software. */ +/* */ +/* COPYRIGHT I B M CORPORATION 1995 */ +/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ +/*------------------------------------------------------------------------------- */ /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards * @@ -62,6 +58,7 @@ * address and (s)dram will be positioned at address 0 */ #include +#include #include #include @@ -81,135 +78,37 @@ # if (CFG_INIT_DCACHE_CS == 0) # define PBxAP pb0ap # define PBxCR pb0cr -# if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) -# define PBxAP_VAL CFG_EBC_PB0AP -# define PBxCR_VAL CFG_EBC_PB0CR -# endif # endif # if (CFG_INIT_DCACHE_CS == 1) # define PBxAP pb1ap # define PBxCR pb1cr -# if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR)) -# define PBxAP_VAL CFG_EBC_PB1AP -# define PBxCR_VAL CFG_EBC_PB1CR -# endif # endif # if (CFG_INIT_DCACHE_CS == 2) # define PBxAP pb2ap # define PBxCR pb2cr -# if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR)) -# define PBxAP_VAL CFG_EBC_PB2AP -# define PBxCR_VAL CFG_EBC_PB2CR -# endif # endif # if (CFG_INIT_DCACHE_CS == 3) # define PBxAP pb3ap # define PBxCR pb3cr -# if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR)) -# define PBxAP_VAL CFG_EBC_PB3AP -# define PBxCR_VAL CFG_EBC_PB3CR -# endif # endif # if (CFG_INIT_DCACHE_CS == 4) # define PBxAP pb4ap # define PBxCR pb4cr -# if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR)) -# define PBxAP_VAL CFG_EBC_PB4AP -# define PBxCR_VAL CFG_EBC_PB4CR -# endif # endif # if (CFG_INIT_DCACHE_CS == 5) # define PBxAP pb5ap # define PBxCR pb5cr -# if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR)) -# define PBxAP_VAL CFG_EBC_PB5AP -# define PBxCR_VAL CFG_EBC_PB5CR -# endif # endif # if (CFG_INIT_DCACHE_CS == 6) # define PBxAP pb6ap # define PBxCR pb6cr -# if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR)) -# define PBxAP_VAL CFG_EBC_PB6AP -# define PBxCR_VAL CFG_EBC_PB6CR -# endif # endif # if (CFG_INIT_DCACHE_CS == 7) # define PBxAP pb7ap # define PBxCR pb7cr -# if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR)) -# define PBxAP_VAL CFG_EBC_PB7AP -# define PBxCR_VAL CFG_EBC_PB7CR -# endif -# endif -# ifndef PBxAP_VAL -# define PBxAP_VAL 0 -# endif -# ifndef PBxCR_VAL -# define PBxCR_VAL 0 -# endif -/* - * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB - * used as temporary stack pointer for the primordial stack - */ -# ifndef CFG_INIT_DCACHE_PBxAR -# define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ - EBC_BXAP_TWT_ENCODE(7) | \ - EBC_BXAP_BCE_DISABLE | \ - EBC_BXAP_BCT_2TRANS | \ - EBC_BXAP_CSN_ENCODE(0) | \ - EBC_BXAP_OEN_ENCODE(0) | \ - EBC_BXAP_WBN_ENCODE(0) | \ - EBC_BXAP_WBF_ENCODE(0) | \ - EBC_BXAP_TH_ENCODE(2) | \ - EBC_BXAP_RE_DISABLED | \ - EBC_BXAP_SOR_NONDELAYED | \ - EBC_BXAP_BEM_WRITEONLY | \ - EBC_BXAP_PEN_DISABLED) -# endif /* CFG_INIT_DCACHE_PBxAR */ -# ifndef CFG_INIT_DCACHE_PBxCR -# define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \ - EBC_BXCR_BS_64MB | \ - EBC_BXCR_BU_RW | \ - EBC_BXCR_BW_16BIT) -# endif /* CFG_INIT_DCACHE_PBxCR */ -# ifndef CFG_INIT_RAM_PATTERN -# define CFG_INIT_RAM_PATTERN 0xDEADDEAD # endif #endif /* CFG_INIT_DCACHE_CS */ -#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10))) -#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END! -#endif - -/* - * Unless otherwise overriden, enable two 128MB cachable instruction regions - * at CFG_SDRAM_BASE and another 128MB cacheable instruction region covering - * NOR flash at CFG_FLASH_BASE. Disable all cacheable data regions. - */ -#if !defined(CFG_FLASH_BASE) -/* If not already defined, set it to the "last" 128MByte region */ -# define CFG_FLASH_BASE 0xf8000000 -#endif -#if !defined(CFG_ICACHE_SACR_VALUE) -# define CFG_ICACHE_SACR_VALUE \ - (PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + ( 0 << 20)) | \ - PPC_128MB_SACR_VALUE(CFG_SDRAM_BASE + (128 << 20)) | \ - PPC_128MB_SACR_VALUE(CFG_FLASH_BASE)) -#endif /* !defined(CFG_ICACHE_SACR_VALUE) */ - -#if !defined(CFG_DCACHE_SACR_VALUE) -# define CFG_DCACHE_SACR_VALUE \ - (0x00000000) -#endif /* !defined(CFG_DCACHE_SACR_VALUE) */ - -#define function_prolog(func_name) .text; \ - .align 2; \ - .globl func_name; \ - func_name: -#define function_epilog(func_name) .type func_name,@function; \ - .size func_name,.-func_name - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -217,16 +116,13 @@ .extern ext_bus_cntlr_init -#ifdef CONFIG_NAND_U_BOOT - .extern reconfig_tlb0 -#endif + .extern sdram_init /* * Set up GOT: Global Offset Table * * Use r14 to access the GOT */ -#if !defined(CONFIG_NAND_SPL) START_GOT GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(_FIXUP_TABLE_) @@ -240,20 +136,6 @@ GOT_ENTRY(_end) GOT_ENTRY(__bss_start) END_GOT -#endif /* CONFIG_NAND_SPL */ - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * NAND U-Boot image is started from offset 0 - */ - .text -#if defined(CONFIG_440) - bl reconfig_tlb0 -#endif - GET_GOT - bl cpu_init_f /* run low-level CPU init code (from Flash) */ - bl board_init_f -#endif /* * 440 Startup -- on reset only the top 4k of the effective @@ -268,21 +150,11 @@ */ #if defined(CONFIG_440) -#if !defined(CONFIG_NAND_SPL) .section .bootpg,"ax" -#endif .globl _start_440 /**************************************************************************/ _start_440: - /*--------------------------------------------------------------------+ - | 440EPX BUP Change - Hardware team request - +--------------------------------------------------------------------*/ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - sync - nop - nop -#endif /*----------------------------------------------------------------+ | Core bug fix. Clear the esr +-----------------------------------------------------------------*/ @@ -299,31 +171,15 @@ _start_440: mtspr srr1,r0 mtspr csrr0,r0 mtspr csrr1,r0 - /* NOTE: 440GX adds machine check status regs */ -#if defined(CONFIG_440) && !defined(CONFIG_440GP) +#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* NOTE: 440GX adds machine check status regs */ mtspr mcsrr0,r0 mtspr mcsrr1,r0 - mfspr r1,mcsr + mfspr r1, mcsr mtspr mcsr,r1 #endif - - /*----------------------------------------------------------------*/ - /* CCR0 init */ - /*----------------------------------------------------------------*/ - /* Disable store gathering & broadcast, guarantee inst/data - * cache block touch, force load/store alignment - * (see errata 1.12: 440_33) - */ - lis r1,0x0030 /* store gathering & broadcast disable */ - ori r1,r1,0x6000 /* cache touch */ - mtspr ccr0,r1 - /*----------------------------------------------------------------*/ /* Initialize debug */ /*----------------------------------------------------------------*/ - mfspr r1,dbcr0 - andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ - bne skip_debug_init /* if set, don't clear debug register */ mtspr dbcr0,r0 mtspr dbcr1,r0 mtspr dbcr2,r0 @@ -337,7 +193,17 @@ _start_440: mfspr r1,dbsr mtspr dbsr,r1 /* Clear all valid bits */ -skip_debug_init: + + /*----------------------------------------------------------------*/ + /* CCR0 init */ + /*----------------------------------------------------------------*/ + /* Disable store gathering & broadcast, guarantee inst/data + * cache block touch, force load/store alignment + * (see errata 1.12: 440_33) + */ + lis r1,0x0030 /* store gathering & broadcast disable */ + ori r1,r1,0x6000 /* cache touch */ + mtspr ccr0,r1 #if defined (CONFIG_440SPE) /*----------------------------------------------------------------+ @@ -386,13 +252,11 @@ skip_debug_init: mtspr ivor7,r1 /* Floating point unavailable */ li r1,0x0c00 mtspr ivor8,r1 /* System call */ - li r1,0x0a00 - mtspr ivor9,r1 /* Auxiliary Processor unavailable */ - li r1,0x0900 - mtspr ivor10,r1 /* Decrementer */ - li r1,0x1300 - mtspr ivor13,r1 /* Data TLB error */ + li r1,0x1000 + mtspr ivor10,r1 /* Decrementer (PIT for 440) */ li r1,0x1400 + mtspr ivor13,r1 /* Data TLB error */ + li r1,0x1300 mtspr ivor14,r1 /* Instr TLB error */ li r1,0x2000 mtspr ivor15,r1 /* Debug */ @@ -451,23 +315,7 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ /*----------------------------------------------------------------*/ /* TLB entry setup -- step thru tlbtab */ /*----------------------------------------------------------------*/ -#if defined(CONFIG_440SPE) - /*----------------------------------------------------------------*/ - /* We have different TLB tables for revA and rev B of 440SPe */ - /*----------------------------------------------------------------*/ - mfspr r1, PVR - lis r0,0x5342 - ori r0,r0,0x1891 - cmpw r7,r1,r0 - bne r7,..revA - bl tlbtabB - b ..goon -..revA: - bl tlbtabA -..goon: -#else bl tlbtab /* Get tlbtab pointer */ -#endif mr r5,r0 li r1,0x003f /* 64 TLB entries max */ mtctr r1 @@ -488,8 +336,7 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ /*----------------------------------------------------------------*/ /* Continue from 'normal' start */ /*----------------------------------------------------------------*/ -2: - bl 3f +2: bl 3f b _start 3: li r0,0 @@ -503,7 +350,6 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/ * r3 - 1st arg to board_init(): IMMP pointer * r4 - 2nd arg to board_init(): boot flag */ -#ifndef CONFIG_NAND_SPL .text .long 0x27051956 /* U-Boot Magic Number */ .globl version_string @@ -512,82 +358,11 @@ version_string: .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" +/* + * Maybe this should be moved somewhere else because the current + * location (0x100) is where the CriticalInput Execption should be. + */ . = EXC_OFF_SYS_RESET - .globl _start_of_vectors -_start_of_vectors: - -/* Critical input. */ - CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) - -#ifdef CONFIG_440 -/* Machine check */ - MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) -#else - CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) -#endif /* CONFIG_440 */ - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG(SRR0, SRR1) - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + _START_OFFSET - .long int_return - _start + _START_OFFSET - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG(SRR0, SRR1) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + _START_OFFSET - .long int_return - _start + _START_OFFSET - -#ifdef CONFIG_440 - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) - STD_EXCEPTION(0xa00, APU, UnknownException) -#endif - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - -#ifdef CONFIG_440 - STD_EXCEPTION(0x1300, DataTLBError, UnknownException) - STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) -#else - STD_EXCEPTION(0x1000, PIT, DecrementerPITException) - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) -#endif - CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) - - .globl _end_of_vectors -_end_of_vectors: - . = _START_OFFSET -#endif .globl _start _start: @@ -626,8 +401,7 @@ _start: /* Setup the internal SRAM */ /*----------------------------------------------------------------*/ li r0,0 - -#ifdef CFG_INIT_RAM_DCACHE +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) /* Clear Dcache to use as RAM */ addis r3,r0,CFG_INIT_RAM_ADDR@h ori r3,r3,CFG_INIT_RAM_ADDR@l @@ -643,51 +417,19 @@ _start: dcbz r0,r3 addi r3,r3,32 bdnz ..d_ag - - /* - * Lock the init-ram/stack in d-cache, so that other regions - * may use d-cache as well - * Note, that this current implementation locks exactly 4k - * of d-cache, so please make sure that you don't define a - * bigger init-ram area. Take a look at the lwmon5 440EPx - * implementation as a reference. - */ - msync - isync - /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ - lis r1,0x0201 - ori r1,r1,0xf808 - mtspr dvlim,r1 - lis r1,0x0808 - ori r1,r1,0x0808 - mtspr dnv0,r1 - mtspr dnv1,r1 - mtspr dnv2,r1 - mtspr dnv3,r1 - mtspr dtv0,r1 - mtspr dtv1,r1 - mtspr dtv2,r1 - mtspr dtv3,r1 - msync - isync -#endif /* CFG_INIT_RAM_DCACHE */ - - /* 440EP & 440GR are only 440er PPC's without internal SRAM */ -#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) - /* not all PPC's have internal SRAM usable as L2-cache */ -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) +#else +#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */ #endif + mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ - lis r2,0x7fff + li r2,0x7fff ori r2,r2,0xffff mfdcr r1,isram0_dpc and r1,r1,r2 /* Disable parity check */ mtdcr isram0_dpc,r1 mfdcr r1,isram0_pmeg - and r1,r1,r2 /* Disable pwr mgmt */ + andis. r1,r1,r2 /* Disable pwr mgmt */ mtdcr isram0_pmeg,r1 lis r1,0x8000 /* BAS = 8000_0000 */ @@ -716,16 +458,11 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr isram0_sb3cr,r1 -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - lis r1,0x4000 /* BAS = 8000_0000 */ - ori r1,r1,0x4580 /* 16k */ - mtdcr isram0_sb0cr,r1 -#elif defined(CONFIG_440GP) +#else ori r1,r1,0x0380 /* 8k rw */ mtdcr isram0_sb0cr,r1 - mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ #endif -#endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ +#endif /*----------------------------------------------------------------*/ /* Setup the stack in internal SRAM */ @@ -742,14 +479,10 @@ _start: stwu r1,-8(r1) /* Save back chain and move SP */ stw r0,+12(r1) /* Save return addr (underflow vect) */ -#ifdef CONFIG_NAND_SPL - bl nand_boot_common /* will not return */ -#else GET_GOT bl cpu_init_f /* run low-level CPU init code (from Flash) */ bl board_init_f -#endif #endif /* CONFIG_440 */ @@ -837,19 +570,19 @@ _start: /* make sure above stores all comlete before going on */ sync - /* Set-up icache cacheability. */ - lis r1, CFG_ICACHE_SACR_VALUE@h - ori r1, r1, CFG_ICACHE_SACR_VALUE@l - mticcr r1 - isync + /*----------------------------------------------------------------------- */ + /* Enable two 128MB cachable regions. */ + /*----------------------------------------------------------------------- */ + addis r1,r0,0x8000 + addi r1,r1,0x0001 + mticcr r1 /* instruction cache */ - /* Set-up dcache cacheability. */ - lis r1, CFG_DCACHE_SACR_VALUE@h - ori r1, r1, CFG_DCACHE_SACR_VALUE@l - mtdccr r1 + addis r1,r0,0x0000 + addi r1,r1,0x0000 + mtdccr r1 /* data cache */ addis r1,r0,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ + ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */ li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ stwu r0, -4(r1) /* stack backtraces terminate cleanly */ @@ -861,25 +594,12 @@ _start: #endif /* CONFIG_IOP480 */ /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || defined(CONFIG_405) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP) /*----------------------------------------------------------------------- */ /* Clear and set up some registers. */ /*----------------------------------------------------------------------- */ addi r4,r0,0x0000 -#if !defined(CONFIG_405EX) mtspr sgr,r4 -#else - /* - * On 405EX, completely clearing the SGR leads to PPC hangup - * upon PCIe configuration access. The PCIe memory regions - * need to be guarded! - */ - lis r3,0x0000 - ori r3,r3,0x7FFC - mtspr sgr,r3 -#endif mtspr dcwr,r4 mtesr r4 /* clear Exception Syndrome Reg */ mttcr r4 /* clear Timer Control Reg */ @@ -889,20 +609,27 @@ _start: /* dbsr is cleared by setting bits to 1) */ mtdbsr r4 /* clear/reset the dbsr */ - /* Invalidate the i- and d-caches. */ + /*----------------------------------------------------------------------- */ + /* Invalidate I and D caches. Enable I cache for defined memory regions */ + /* to speed things up. Leave the D cache disabled for now. It will be */ + /* enabled/left disabled later based on user selected menu options. */ + /* Be aware that the I cache may be disabled later based on the menu */ + /* options as well. See miscLib/main.c. */ + /*----------------------------------------------------------------------- */ bl invalidate_icache bl invalidate_dcache - /* Set-up icache cacheability. */ - lis r4, CFG_ICACHE_SACR_VALUE@h - ori r4, r4, CFG_ICACHE_SACR_VALUE@l - mticcr r4 + /*----------------------------------------------------------------------- */ + /* Enable two 128MB cachable regions. */ + /*----------------------------------------------------------------------- */ + addis r4,r0,0x8000 + addi r4,r4,0x0001 + mticcr r4 /* instruction cache */ isync - /* Set-up dcache cacheability. */ - lis r4, CFG_DCACHE_SACR_VALUE@h - ori r4, r4, CFG_DCACHE_SACR_VALUE@l - mtdccr r4 + addis r4,r0,0x0000 + addi r4,r4,0x0000 + mtdccr r4 /* data cache */ #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) /*----------------------------------------------------------------------- */ @@ -911,70 +638,18 @@ _start: bl ext_bus_cntlr_init #endif -#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) - /* - * For boards that don't have OCM and can't use the data cache - * for their primordial stack, setup stack here directly after the - * SDRAM is initialized in ext_bus_cntlr_init. - */ - lis r1, CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - /* - * Set up a dummy frame to store reset vector as return address. - * this causes stack underflow to reset board. - */ - stwu r1, -8(r1) /* Save back chain and move SP */ - lis r0, RESET_VECTOR@h /* Address of reset vector */ - ori r0, r0, RESET_VECTOR@l - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save return addr (underflow vect) */ -#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ - #if defined(CONFIG_405EP) /*----------------------------------------------------------------------- */ /* DMA Status, clear to come up clean */ /*----------------------------------------------------------------------- */ - addis r3,r0, 0xFFFF /* Clear all existing DMA status */ + addis r3,r0, 0xFFFF /* Clear all existing DMA status */ ori r3,r3, 0xFFFF mtdcr dmasr, r3 - bl ppc405ep_init /* do ppc405ep specific init */ + bl ppc405ep_init /* do ppc405ep specific init */ #endif /* CONFIG_405EP */ #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) -#if defined(CONFIG_405EZ) - /******************************************************************** - * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 - *******************************************************************/ - /* - * We can map the OCM on the PLB3, so map it at - * CFG_OCM_DATA_ADDR + 0x8000 - */ - lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ - ori r3,r3,CFG_OCM_DATA_ADDR@l - ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr ocmplb3cr1,r3 /* Set PLB Access */ - ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr ocmplb3cr2,r3 /* Set PLB Access */ - isync - - lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ - ori r3,r3,CFG_OCM_DATA_ADDR@l - ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr ocmdscr1, r3 /* Set Data Side */ - mtdcr ocmiscr1, r3 /* Set Instruction Side */ - ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr ocmdscr2, r3 /* Set Data Side */ - mtdcr ocmiscr2, r3 /* Set Instruction Side */ - addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ - mtdcr ocmdsisdpc,r3 - - isync -#else /* CONFIG_405EZ */ /******************************************************************** * Setup OCM - On Chip Memory *******************************************************************/ @@ -982,106 +657,65 @@ _start: lis r0, 0x7FFF ori r0, r0, 0xFFFF mfdcr r3, ocmiscntl /* get instr-side IRAM config */ - mfdcr r4, ocmdscntl /* get data-side IRAM config */ - and r3, r3, r0 /* disable data-side IRAM */ - and r4, r4, r0 /* disable data-side IRAM */ - mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ - mtdcr ocmdscntl, r4 /* set data-side IRAM config */ + mfdcr r4, ocmdscntl /* get data-side IRAM config */ + and r3, r3, r0 /* disable data-side IRAM */ + and r4, r4, r0 /* disable data-side IRAM */ + mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ + mtdcr ocmdscntl, r4 /* set data-side IRAM config */ isync - lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ - ori r3,r3,CFG_OCM_DATA_ADDR@l + addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */ mtdcr ocmdsarc, r3 addis r4, 0, 0xC000 /* OCM data area enabled */ mtdcr ocmdscntl, r4 isync -#endif /* CONFIG_405EZ */ #endif /*----------------------------------------------------------------------- */ /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ /*----------------------------------------------------------------------- */ #ifdef CFG_INIT_DCACHE_CS - li r4, PBxAP - mtdcr ebccfga, r4 - lis r4, CFG_INIT_DCACHE_PBxAR@h - ori r4, r4, CFG_INIT_DCACHE_PBxAR@l - mtdcr ebccfgd, r4 + /*----------------------------------------------------------------------- */ + /* Memory Bank x (nothingness) initialization 1GB+64MEG */ + /* used as temporary stack pointer for stage0 */ + /*----------------------------------------------------------------------- */ + li r4,PBxAP + mtdcr ebccfga,r4 + lis r4,0x0380 + ori r4,r4,0x0480 + mtdcr ebccfgd,r4 - addi r4, 0, PBxCR - mtdcr ebccfga, r4 - lis r4, CFG_INIT_DCACHE_PBxCR@h - ori r4, r4, CFG_INIT_DCACHE_PBxCR@l - mtdcr ebccfgd, r4 + addi r4,0,PBxCR + mtdcr ebccfga,r4 + lis r4,0x400D + ori r4,r4,0xa000 + mtdcr ebccfgd,r4 - /* - * Enable the data cache for the 128MB storage access control region - * at CFG_INIT_RAM_ADDR. - */ - mfdccr r4 - oris r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h - ori r4, r4, PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l + /* turn on data chache for this region */ + lis r4,0x0080 mtdccr r4 - /* - * Preallocate data cache lines to be used to avoid a subsequent - * cache miss and an ensuing machine check exception when exceptions - * are enabled. - */ - li r0, 0 + /* set stack pointer and clear stack to known value */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l + lis r1,CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET@l - lis r4, CFG_INIT_RAM_END@h - ori r4, r4, CFG_INIT_RAM_END@l - - /* - * Convert the size, in bytes, to the number of cache lines/blocks - * to preallocate. - */ - clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) - srwi r5, r4, L1_CACHE_SHIFT - beq ..load_counter - addi r5, r5, 0x0001 -..load_counter: - mtctr r5 - - /* Preallocate the computed number of cache blocks. */ -..alloc_dcache_block: - dcba r0, r3 - addi r3, r3, L1_CACHE_BYTES - bdnz ..alloc_dcache_block - sync - - /* - * Load the initial stack pointer and data area and convert the size, - * in bytes, to the number of words to initialize to a known value. - */ - lis r1, CFG_INIT_RAM_ADDR@h - ori r1, r1, CFG_INIT_SP_OFFSET@l - - lis r4, (CFG_INIT_RAM_END >> 2)@h - ori r4, r4, (CFG_INIT_RAM_END >> 2)@l + li r4,2048 /* we store 2048 words to stack */ mtctr r4 - lis r2, CFG_INIT_RAM_ADDR@h - ori r2, r2, CFG_INIT_RAM_END@l + lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */ + ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */ - lis r4, CFG_INIT_RAM_PATTERN@h - ori r4, r4, CFG_INIT_RAM_PATTERN@l + lis r4,0xdead /* we store 0xdeaddead in the stack */ + ori r4,r4,0xdead ..stackloop: - stwu r4, -4(r2) + stwu r4,-4(r2) bdnz ..stackloop - /* - * Make room for stack frame header and clear final stack frame so - * that stack backtraces terminate cleanly. - */ - stwu r0, -4(r1) - stwu r0, -4(r1) - + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ /* * Set up a dummy frame to store reset vector as return address. * this causes stack underflow to reset board. @@ -1118,22 +752,147 @@ _start: stw r0, +12(r1) /* Save return addr (underflow vect) */ #endif /* CFG_INIT_DCACHE_CS */ -#ifdef CONFIG_NAND_SPL - bl nand_boot_common /* will not return */ -#else + /*----------------------------------------------------------------------- */ + /* Initialize SDRAM Controller */ + /*----------------------------------------------------------------------- */ + bl sdram_init + + /* + * Setup temporary stack pointer only for boards + * that do not use SDRAM SPD I2C stuff since it + * is already initialized to use DCACHE or OCM + * stacks. + */ +#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) + lis r1, CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Set up a dummy frame to store reset vector as return address. + * this causes stack underflow to reset board. + */ + stwu r1, -8(r1) /* Save back chain and move SP */ + lis r0, RESET_VECTOR@h /* Address of reset vector */ + ori r0, r0, RESET_VECTOR@l + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save return addr (underflow vect) */ +#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ + GET_GOT /* initialize GOT access */ bl cpu_init_f /* run low-level CPU init code (from Flash) */ /* NEVER RETURNS! */ bl board_init_f /* run first part of init code (from Flash) */ -#endif /* CONFIG_NAND_SPL */ #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ /*----------------------------------------------------------------------- */ -#ifndef CONFIG_NAND_SPL +/*****************************************************************************/ + .globl _start_of_vectors +_start_of_vectors: + +#if 0 +/*TODO Fixup _start above so we can do this*/ +/* Critical input. */ + CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException) +#endif + +/* Machine check */ + CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + + /* No FPU on MPC8xx. This exception is not supposed to happen. + */ + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + + /* I guess we could implement decrementer, and may have + * to someday for timekeeping. + */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + STD_EXCEPTION(0xa00, Trap_0a, UnknownException) + STD_EXCEPTION(0xb00, Trap_0b, UnknownException) + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + STD_EXCEPTION(0xd00, SingleStep, UnknownException) + + STD_EXCEPTION(0xe00, Trap_0e, UnknownException) + STD_EXCEPTION(0xf00, Trap_0f, UnknownException) + + /* On the MPC8xx, this is a software emulation interrupt. It occurs + * for all unimplemented and illegal instructions. + */ + STD_EXCEPTION(0x1000, PIT, PITException) + + STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) + STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) + STD_EXCEPTION(0x1400, DataTLBError, UnknownException) + + STD_EXCEPTION(0x1500, Reserved5, UnknownException) + STD_EXCEPTION(0x1600, Reserved6, UnknownException) + STD_EXCEPTION(0x1700, Reserved7, UnknownException) + STD_EXCEPTION(0x1800, Reserved8, UnknownException) + STD_EXCEPTION(0x1900, Reserved9, UnknownException) + STD_EXCEPTION(0x1a00, ReservedA, UnknownException) + STD_EXCEPTION(0x1b00, ReservedB, UnknownException) + + STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) + STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) + STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) + STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) + + CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) + + .globl _end_of_vectors +_end_of_vectors: + + + . = 0x2100 + /* * This code finishes saving the registers to the exception frame * and jumps to the appropriate handler for the exception. @@ -1149,12 +908,28 @@ transfer_to_handler: SAVE_4GPRS(8, r21) SAVE_8GPRS(12, r21) SAVE_8GPRS(24, r21) +#if 0 + andi. r23,r23,MSR_PR + mfspr r23,SPRG3 /* if from user, fix up tss.regs */ + beq 2f + addi r24,r1,STACK_FRAME_OVERHEAD + stw r24,PT_REGS(r23) +2: addi r2,r23,-TSS /* set r2 to current */ + tovirt(r2,r2,r23) +#endif mflr r23 andi. r24,r23,0x3f00 /* get vector offset */ stw r24,TRAP(r21) li r22,0 stw r22,RESULT(r21) mtspr SPRG2,r22 /* r1 is now kernel sp */ +#if 0 + addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */ + cmplw 0,r1,r2 + cmplw 1,r1,r24 + crand 1,1,4 + bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */ +#endif lwz r24,0(r23) /* virtual address of handler */ lwz r23,4(r23) /* where to go when done */ mtspr SRR0,r24 @@ -1215,52 +990,147 @@ crit_return: REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) - mtspr csrr0,r2 - mtspr csrr1,r0 + mtspr 990,r2 /* SRR2 */ + mtspr 991,r0 /* SRR3 */ lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) SYNC rfci -#ifdef CONFIG_440 -mck_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr mcsrr0,r2 - mtspr mcsrr1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfmci -#endif /* CONFIG_440 */ +/* Cache functions. +*/ +invalidate_icache: + iccci r0,r0 /* for 405, iccci invalidates the */ + blr /* entire I cache */ +invalidate_dcache: + addi r6,0,0x0000 /* clear GPR 6 */ + /* Do loop for # of dcache congruence classes. */ + lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */ + ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l + /* NOTE: dccci invalidates both */ + mtctr r7 /* ways in the D cache */ +..dcloop: + dccci 0,r6 /* invalidate line */ + addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */ + bdnz ..dcloop + blr + +flush_dcache: + addis r9,r0,0x0002 /* set mask for EE and CE msr bits */ + ori r9,r9,0x8000 + mfmsr r12 /* save msr */ + andc r9,r12,r9 + mtmsr r9 /* disable EE and CE */ + addi r10,r0,0x0001 /* enable data cache for unused memory */ + mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */ + or r10,r10,r9 /* bit 31 in dccr */ + mtdccr r10 + + /* do loop for # of congruence classes. */ + lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */ + ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l + lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */ + ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */ + mtctr r10 + addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */ + add r11,r10,r11 /* add to get to other side of cache line */ +..flush_dcache_loop: + lwz r3,0(r10) /* least recently used side */ + lwz r3,0(r11) /* the other side */ + dccci r0,r11 /* invalidate both sides */ + addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */ + addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */ + bdnz ..flush_dcache_loop + sync /* allow memory access to complete */ + mtdccr r9 /* restore dccr */ + mtmsr r12 /* restore msr */ + blr + + .globl icache_enable +icache_enable: + mflr r8 + bl invalidate_icache + mtlr r8 + isync + addis r3,r0, 0x8000 /* set bit 0 */ + mticcr r3 + blr + + .globl icache_disable +icache_disable: + addis r3,r0, 0x0000 /* clear bit 0 */ + mticcr r3 + isync + blr + + .globl icache_status +icache_status: + mficcr r3 + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl dcache_enable +dcache_enable: + mflr r8 + bl invalidate_dcache + mtlr r8 + isync + addis r3,r0, 0x8000 /* set bit 0 */ + mtdccr r3 + blr + + .globl dcache_disable +dcache_disable: + mflr r8 + bl flush_dcache + mtlr r8 + addis r3,r0, 0x0000 /* clear bit 0 */ + mtdccr r3 + blr + + .globl dcache_status +dcache_status: + mfdccr r3 + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr .globl get_pvr get_pvr: mfspr r3, PVR blr +#if !defined(CONFIG_440) + .globl wr_pit +wr_pit: + mtspr pit, r3 + blr +#endif + + .globl wr_tcr +wr_tcr: + mtspr tcr, r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: in8 */ +/* Description: Input 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl in8 +in8: + lbz r3,0x0000(r3) + blr + +/*------------------------------------------------------------------------------- */ +/* Function: out8 */ +/* Description: Output 8 bits */ +/*------------------------------------------------------------------------------- */ + .globl out8 +out8: + stb r4,0x0000(r3) + blr + /*------------------------------------------------------------------------------- */ /* Function: out16 */ /* Description: Output 16 bits */ @@ -1279,6 +1149,15 @@ out16r: sthbrx r4,r0,r3 blr +/*------------------------------------------------------------------------------- */ +/* Function: out32 */ +/* Description: Output 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl out32 +out32: + stw r4,0x0000(r3) + blr + /*------------------------------------------------------------------------------- */ /* Function: out32r */ /* Description: Byte reverse and output 32 bits */ @@ -1306,6 +1185,15 @@ in16r: lhbrx r3,r0,r3 blr +/*------------------------------------------------------------------------------- */ +/* Function: in32 */ +/* Description: Input 32 bits */ +/*------------------------------------------------------------------------------- */ + .globl in32 +in32: + lwz 3,0x0000(3) + blr + /*------------------------------------------------------------------------------- */ /* Function: in32r */ /* Description: Input 32 bits and byte reverse */ @@ -1315,107 +1203,55 @@ in32r: lwbrx r3,r0,r3 blr +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcSync */ +/* Description: Processor Synchronize */ +/* Input: none. */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcSync +ppcSync: + sync + blr + +/*------------------------------------------------------------------------------*/ + /* * void relocate_code (addr_sp, gd, addr_moni) * * This "function" does not return, instead it continues in RAM * after relocating the monitor code. * - * r3 = Relocated stack pointer - * r4 = Relocated global data pointer - * r5 = Relocated text pointer + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize */ .globl relocate_code relocate_code: -#if defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) - /* - * We need to flush the initial global data (gd_t) before the dcache - * will be invalidated. - */ - - /* Save registers */ - mr r9, r3 - mr r10, r4 - mr r11, r5 - - /* Flush initial global data range */ - mr r3, r4 - addi r4, r4, CFG_GBL_DATA_SIZE@l - bl flush_dcache_range - -#if defined(CFG_INIT_DCACHE_CS) - /* - * Undo the earlier data cache set-up for the primordial stack and - * data area. First, invalidate the data cache and then disable data - * cacheability for that area. Finally, restore the EBC values, if - * any. - */ - - /* Invalidate the primordial stack and data area in cache */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l - - lis r4, CFG_INIT_RAM_END@h - ori r4, r4, CFG_INIT_RAM_END@l - add r4, r4, r3 - - bl invalidate_dcache_range - - /* Disable cacheability for the region */ - mfdccr r3 - lis r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@h - ori r4, r4, ~PPC_128MB_SACR_VALUE(CFG_INIT_RAM_ADDR)@l - and r3, r3, r4 - mtdccr r3 - - /* Restore the EBC parameters */ - li r3, PBxAP - mtdcr ebccfga, r3 - lis r3, PBxAP_VAL@h - ori r3, r3, PBxAP_VAL@l - mtdcr ebccfgd, r3 - - li r3, PBxCR - mtdcr ebccfga, r3 - lis r3, PBxCR_VAL@h - ori r3, r3, PBxCR_VAL@l - mtdcr ebccfgd, r3 -#endif /* defined(CFG_INIT_DCACHE_CS) */ - - /* Restore registers */ - mr r3, r9 - mr r4, r10 - mr r5, r11 -#endif /* defined(CONFIG_4xx_DCACHE) || defined(CFG_INIT_DCACHE_CS) */ - -#ifdef CFG_INIT_RAM_DCACHE - /* - * Unlock the previously locked d-cache - */ - msync - isync - /* set TFLOOR/NFLOOR to 0 again */ - lis r6,0x0001 - ori r6,r6,0xf800 - mtspr dvlim,r6 - lis r6,0x0000 - ori r6,r6,0x0000 - mtspr dnv0,r6 - mtspr dnv1,r6 - mtspr dnv2,r6 - mtspr dnv3,r6 - mtspr dtv0,r6 - mtspr dtv1,r6 - mtspr dtv2,r6 - mtspr dtv3,r6 - msync - isync -#endif /* CFG_INIT_RAM_DCACHE */ - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) /* * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) * to speed up the boot process. Now this cache needs to be disabled. @@ -1424,17 +1260,13 @@ relocate_code: dccci 0,0 /* Invalidate data cache, now no longer our stack */ sync isync -#ifdef CFG_TLB_FOR_BOOT_FLASH - addi r1,r0,CFG_TLB_FOR_BOOT_FLASH /* Use defined TLB */ -#else - addi r1,r0,0x0000 /* Default TLB entry is #0 */ -#endif /* CFG_TLB_FOR_BOOT_FLASH */ + addi r1,r0,0x0000 /* TLB entry #0 */ tlbre r0,r1,0x0002 /* Read contents */ ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ tlbwe r0,r1,0x0002 /* Save it out */ sync isync -#endif /* defined(CONFIG_440EP) || ... || defined(CONFIG_460GT) */ +#endif mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Init Data pointer */ mr r10, r5 /* Save copy of Destination Address */ @@ -1444,7 +1276,7 @@ relocate_code: ori r4, r4, CFG_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, L1_CACHE_BYTES /* Cache Line Size */ + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: @@ -1457,7 +1289,7 @@ relocate_code: /* First our own GOT */ add r14, r14, r15 - /* then the one used by the C code */ + /* the the one used by the C code */ add r30, r30, r15 /* @@ -1514,7 +1346,7 @@ relocate_code: * initialization, now running from RAM. */ - addi r0, r10, in_ram - _start + _START_OFFSET + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET mtlr r0 blr /* NEVER RETURNS! */ @@ -1562,25 +1394,16 @@ clear_bss: lwz r4,GOT(_end) cmplw 0, r3, r4 - beq 7f + beq 6f li r0, 0 - - andi. r5, r4, 3 - beq 6f - sub r4, r4, r5 - mtctr r5 - mr r5, r4 -5: stb r0, 0(r5) - addi r5, r5, 1 - bdnz 5b -6: +5: stw r0, 0(r3) addi r3, r3, 4 cmplw 0, r3, r4 - bne 6b + bne 5b +6: -7: mr r3, r9 /* Init Data pointer */ mr r4, r10 /* Destination Address */ bl board_init_r @@ -1593,7 +1416,7 @@ clear_bss: */ .globl trap_init trap_init: - lwz r7, GOT(_start_of_vectors) + lwz r7, GOT(_start) lwz r8, GOT(_end_of_vectors) li r9, 0x100 /* reset vector always at 0x100 */ @@ -1613,65 +1436,52 @@ trap_init: /* * relocate `hdlr' and `int_return' entries */ - li r7, .L_MachineCheck - _start + _START_OFFSET - li r8, Alignment - _start + _START_OFFSET + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET 2: bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ + addi r7, r7, 0x100 /* next exception vector */ cmplw 0, r7, r8 blt 2b - li r7, .L_Alignment - _start + _START_OFFSET + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET bl trap_reloc - li r7, .L_ProgramCheck - _start + _START_OFFSET + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET bl trap_reloc -#ifdef CONFIG_440 - li r7, .L_FPUnavailable - _start + _START_OFFSET + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b - li r7, .L_Decrementer - _start + _START_OFFSET + li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b - li r7, .L_APU - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_InstructionTLBError - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_DataTLBError - _start + _START_OFFSET - bl trap_reloc -#else /* CONFIG_440 */ - li r7, .L_PIT - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_InstructionTLBMiss - _start + _START_OFFSET - bl trap_reloc - - li r7, .L_DataTLBMiss - _start + _START_OFFSET - bl trap_reloc -#endif /* CONFIG_440 */ - - li r7, .L_DebugBreakpoint - _start + _START_OFFSET - bl trap_reloc - -#if !defined(CONFIG_440) +#if !defined(CONFIG_440GX) && !defined(CONFIG_440SPE) addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ mtmsr r7 /* change MSR */ #else - bl __440_msr_set - b __440_msr_continue + bl __440gx_msr_set + b __440gx_msr_continue -__440_msr_set: +__440gx_msr_set: addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ mtspr srr1,r7 mflr r7 mtspr srr0,r7 rfi -__440_msr_continue: +__440gx_msr_continue: #endif mtlr r4 /* restore link register */ @@ -1691,60 +1501,6 @@ trap_reloc: blr -#if defined(CONFIG_440) -/*----------------------------------------------------------------------------+ -| dcbz_area. -+----------------------------------------------------------------------------*/ - function_prolog(dcbz_area) - rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ra2 - addi r5,r5,0x0001 -..d_ra2:mtctr r5 -..d_ag2:dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag2 - sync - blr - function_epilog(dcbz_area) -#endif /* CONFIG_440 */ -#endif /* CONFIG_NAND_SPL */ - -/*------------------------------------------------------------------------------- */ -/* Function: in8 */ -/* Description: Input 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl in8 -in8: - lbz r3,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out8 */ -/* Description: Output 8 bits */ -/*------------------------------------------------------------------------------- */ - .globl out8 -out8: - stb r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: out32 */ -/* Description: Output 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl out32 -out32: - stw r4,0x0000(r3) - blr - -/*------------------------------------------------------------------------------- */ -/* Function: in32 */ -/* Description: Input 32 bits */ -/*------------------------------------------------------------------------------- */ - .globl in32 -in32: - lwz 3,0x0000(3) - blr /**************************************************************************/ /* PPC405EP specific stuff */ @@ -1831,6 +1587,24 @@ ppc405ep_init: mtdcr ebccfgd,r3 #endif + addi r3,0,CPC0_PCI_HOST_CFG_EN +#ifdef CONFIG_BUBINGA + /* + !----------------------------------------------------------------------- + ! Check FPGA for PCI internal/external arbitration + ! If board is set to internal arbitration, update cpc0_pci + !----------------------------------------------------------------------- + */ + addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */ + ori r5,r5,FPGA_REG1@l + lbz r5,0x0(r5) /* read to get PCI arb selection */ + andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/ + beq ..pci_cfg_set /* if not set, then bypass reg write*/ +#endif + ori r3,r3,CPC0_PCI_ARBIT_EN +..pci_cfg_set: + mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/ + /* !----------------------------------------------------------------------- ! Check to see if chip is in bypass mode. @@ -1841,13 +1615,13 @@ ppc405ep_init: !----------------------------------------------------------------------- */ mfdcr r5, CPC0_PLLMR1 - rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ + rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ cmpi cr0,0,r4,0x1 - beq pll_done /* if SSCS =b'1' then PLL has */ - /* already been set */ - /* and CPU has been reset */ - /* so skip to next section */ + beq pll_done /* if SSCS =b'1' then PLL has */ + /* already been set */ + /* and CPU has been reset */ + /* so skip to next section */ #ifdef CONFIG_BUBINGA /* @@ -1869,13 +1643,13 @@ ppc405ep_init: lwz r4, 0(r3) addis r5,0,NVRVFY1@h addi r5,r5,NVRVFY1@l - cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ + cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ bne ..no_pllset addi r3,r3,4 lwz r4, 0(r3) addis r5,0,NVRVFY2@h addi r5,r5,NVRVFY2@l - cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ + cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ bne ..no_pllset addi r3,r3,8 /* Skip over conf_size */ lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ @@ -1886,51 +1660,12 @@ ppc405ep_init: ..no_pllset: #endif /* CONFIG_BUBINGA */ -#ifdef CONFIG_TAIHU - mfdcr r4, CPC0_BOOT - andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_1 /* serial eeprom present */ - addis r5,0,CPLD_REG0_ADDR@h - ori r5,r5,CPLD_REG0_ADDR@l - andi. r5, r5, 0x10 - bne _pci_66mhz -#endif /* CONFIG_TAIHU */ + addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ + ori r3,r3,PLLMR0_DEFAULT@l /* */ + addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ + ori r4,r4,PLLMR1_DEFAULT@l /* */ -#if defined(CONFIG_ZEUS) - mfdcr r4, CPC0_BOOT - andi. r5, r4, CPC0_BOOT_SEP@l - bne strap_1 /* serial eeprom present */ - lis r3,0x0000 - addi r3,r3,0x3030 - lis r4,0x8042 - addi r4,r4,0x223e - b 1f -strap_1: - mfdcr r3, CPC0_PLLMR0 - mfdcr r4, CPC0_PLLMR1 - b 1f -#endif - - addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ - ori r3,r3,PLLMR0_DEFAULT@l /* */ - addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ - ori r4,r4,PLLMR1_DEFAULT@l /* */ - -#ifdef CONFIG_TAIHU - b 1f -_pci_66mhz: - addis r3,0,PLLMR0_DEFAULT_PCI66@h - ori r3,r3,PLLMR0_DEFAULT_PCI66@l - addis r4,0,PLLMR1_DEFAULT_PCI66@h - ori r4,r4,PLLMR1_DEFAULT_PCI66@l - b 1f -strap_1: - mfdcr r3, CPC0_PLLMR0 - mfdcr r4, CPC0_PLLMR1 -#endif /* CONFIG_TAIHU */ - -1: - b pll_write /* Write the CPC0_PLLMR with new value */ + b pll_write /* Write the CPC0_PLLMR with new value */ pll_done: /* @@ -1947,7 +1682,7 @@ pll_done: pci_wait: bdnz pci_wait - blr /* return to main code */ + blr /* return to main code */ /* !----------------------------------------------------------------------------- @@ -1968,20 +1703,20 @@ pci_wait: pll_write: mfdcr r5, CPC0_UCR andis. r5,r5,0xFFFF - ori r5,r5,0x0101 /* Stop the UART clocks */ - mtdcr CPC0_UCR,r5 /* Before changing PLL */ + ori r5,r5,0x0101 /* Stop the UART clocks */ + mtdcr CPC0_UCR,r5 /* Before changing PLL */ mfdcr r5, CPC0_PLLMR1 - rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ + rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ mtdcr CPC0_PLLMR1,r5 - oris r5,r5,0x4000 /* Set PLL Reset */ + oris r5,r5,0x4000 /* Set PLL Reset */ mtdcr CPC0_PLLMR1,r5 - mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ - rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ - oris r5,r5,0x4000 /* Set PLL Reset */ - mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ - rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ + mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ + rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ + oris r5,r5,0x4000 /* Set PLL Reset */ + mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ + rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ mtdcr CPC0_PLLMR1,r5 /* @@ -2002,129 +1737,7 @@ pll_wait: * Not sure if this is needed... */ addis r3,0,0x1000 - mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ - /* execution will continue from the poweron */ - /* vector of 0xfffffffc */ + mtspr dbcr0,r3 /* This will cause a CPU core reset, and */ + /* execution will continue from the poweron */ + /* vector of 0xfffffffc */ #endif /* CONFIG_405EP */ - -#if defined(CONFIG_440) -/*----------------------------------------------------------------------------+ -| mttlb3. -+----------------------------------------------------------------------------*/ - function_prolog(mttlb3) - TLBWE(4,3,2) - blr - function_epilog(mttlb3) - -/*----------------------------------------------------------------------------+ -| mftlb3. -+----------------------------------------------------------------------------*/ - function_prolog(mftlb3) - TLBRE(3,3,2) - blr - function_epilog(mftlb3) - -/*----------------------------------------------------------------------------+ -| mttlb2. -+----------------------------------------------------------------------------*/ - function_prolog(mttlb2) - TLBWE(4,3,1) - blr - function_epilog(mttlb2) - -/*----------------------------------------------------------------------------+ -| mftlb2. -+----------------------------------------------------------------------------*/ - function_prolog(mftlb2) - TLBRE(3,3,1) - blr - function_epilog(mftlb2) - -/*----------------------------------------------------------------------------+ -| mttlb1. -+----------------------------------------------------------------------------*/ - function_prolog(mttlb1) - TLBWE(4,3,0) - blr - function_epilog(mttlb1) - -/*----------------------------------------------------------------------------+ -| mftlb1. -+----------------------------------------------------------------------------*/ - function_prolog(mftlb1) - TLBRE(3,3,0) - blr - function_epilog(mftlb1) -#endif /* CONFIG_440 */ - -#if defined(CONFIG_NAND_SPL) -/* - * void nand_boot_relocate(dst, src, bytes) - * - * r3 = Destination address to copy code to (in SDRAM) - * r4 = Source address to copy code from - * r5 = size to copy in bytes - */ -nand_boot_relocate: - mr r6,r3 - mr r7,r4 - mflr r8 - - /* - * Copy SPL from icache into SDRAM - */ - subi r3,r3,4 - subi r4,r4,4 - srwi r5,r5,2 - mtctr r5 -..spl_loop: - lwzu r0,4(r4) - stwu r0,4(r3) - bdnz ..spl_loop - - /* - * Calculate "corrected" link register, so that we "continue" - * in execution in destination range - */ - sub r3,r7,r6 /* r3 = src - dst */ - sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ - mtlr r8 - blr - -nand_boot_common: - /* - * First initialize SDRAM. It has to be available *before* calling - * nand_boot(). - */ - lis r3,CFG_SDRAM_BASE@h - ori r3,r3,CFG_SDRAM_BASE@l - bl initdram - - /* - * Now copy the 4k SPL code into SDRAM and continue execution - * from there. - */ - lis r3,CFG_NAND_BOOT_SPL_DST@h - ori r3,r3,CFG_NAND_BOOT_SPL_DST@l - lis r4,CFG_NAND_BOOT_SPL_SRC@h - ori r4,r4,CFG_NAND_BOOT_SPL_SRC@l - lis r5,CFG_NAND_BOOT_SPL_SIZE@h - ori r5,r5,CFG_NAND_BOOT_SPL_SIZE@l - bl nand_boot_relocate - - /* - * We're running from SDRAM now!!! - * - * It is necessary for 4xx systems to relocate from running at - * the original location (0xfffffxxx) to somewhere else (SDRAM - * preferably). This is because CS0 needs to be reconfigured for - * NAND access. And we can't reconfigure this CS when currently - * "running" from it. - */ - - /* - * Finally call nand_boot() to load main NAND U-Boot image from - * NAND and jump to it. - */ - bl nand_boot /* will not return */ -#endif /* CONFIG_NAND_SPL */ diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 55154b6f0..6aecca2db 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -36,9 +36,7 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -47,7 +45,8 @@ extern unsigned long search_exception_table(unsigned long); /* THIS NEEDS CHANGING to use the board info structure. */ -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) +#define END_OF_MEM 0x00400000 + static __inline__ void set_tsr(unsigned long val) { @@ -78,7 +77,7 @@ static __inline__ unsigned long get_esr(void) #define ESR_DIZ 0x00400000 #define ESR_U0F 0x00008000 -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) extern void do_bedbug_breakpoint(struct pt_regs *); #endif @@ -111,7 +110,7 @@ void show_regs(struct pt_regs * regs) { int i; - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n", + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, @@ -121,12 +120,14 @@ void show_regs(struct pt_regs * regs) printf("\n"); for (i = 0; i < 32; i++) { - if ((i % 8) == 0) { + if ((i % 8) == 0) + { printf("GPR%02d: ", i); } printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) { + if ((i % 8) == 7) + { printf("\n"); } } @@ -138,171 +139,48 @@ _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception"); + panic("Exception in kernel pc %lx signal %d",regs->nip,signr); } void MachineCheckException(struct pt_regs *regs) { - unsigned long fixup, val; -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - u32 value2; - int corr_ecc = 0; - int uncorr_ecc = 0; -#endif + unsigned long fixup; + /* Probing PCI using config cycles cause this exception + * when a device is not present. Catch it and return to + * the PCI exception handler. + */ if ((fixup = search_exception_table(regs->nip)) != 0) { regs->nip = fixup; - val = mfspr(MCSR); - /* Clear MCSR */ - mtspr(SPRN_MCSR, val); return; } -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif - printf("Machine Check Exception.\n"); + printf("Machine check in kernel mode.\n"); printf("Caused by (from msr): "); - printf("regs %p ", regs); - - val = get_esr(); - -#if !defined(CONFIG_440) && !defined(CONFIG_405EX) - if (val& ESR_IMCP) { - printf("Instruction"); - mtspr(ESR, val & ~ESR_IMCP); - } else { - printf("Data"); - } - printf(" machine check.\n"); - -#elif defined(CONFIG_440) || defined(CONFIG_405EX) - if (val& ESR_IMCP){ - printf("Instruction Synchronous Machine Check exception\n"); - mtspr(SPRN_ESR, val & ~ESR_IMCP); - } else { - val = mfspr(MCSR); - if (val & MCSR_IB) - printf("Instruction Read PLB Error\n"); -#if defined(CONFIG_440) - if (val & MCSR_DRB) - printf("Data Read PLB Error\n"); - if (val & MCSR_DWB) - printf("Data Write PLB Error\n"); -#else - if (val & MCSR_DB) - printf("Data PLB Error\n"); -#endif - if (val & MCSR_TLBP) - printf("TLB Parity Error\n"); - if (val & MCSR_ICP){ - /*flush_instruction_cache(); */ - printf("I-Cache Parity Error\n"); - } - if (val & MCSR_DCSP) - printf("D-Cache Search Parity Error\n"); - if (val & MCSR_DCFP) - printf("D-Cache Flush Parity Error\n"); - if (val & MCSR_IMPE) - printf("Machine Check exception is imprecise\n"); - - /* Clear MCSR */ - mtspr(SPRN_MCSR, val); - } -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - mfsdram(DDR0_00, val) ; - printf("DDR0: DDR0_00 %lx\n", val); - val = (val >> 16) & 0xff; - if (val & 0x80) - printf("DDR0: At least one interrupt active\n"); - if (val & 0x40) - printf("DDR0: DRAM initialization complete.\n"); - if (val & 0x20) { - printf("DDR0: Multiple uncorrectable ECC events.\n"); - uncorr_ecc = 1; - } - if (val & 0x10) { - printf("DDR0: Single uncorrectable ECC event.\n"); - uncorr_ecc = 1; - } - if (val & 0x08) { - printf("DDR0: Multiple correctable ECC events.\n"); - corr_ecc = 1; - } - if (val & 0x04) { - printf("DDR0: Single correctable ECC event.\n"); - corr_ecc = 1; - } - if (val & 0x02) - printf("Multiple accesses outside the defined" - " physical memory space detected\n"); - if (val & 0x01) - printf("DDR0: Single access outside the defined" - " physical memory space detected.\n"); - - mfsdram(DDR0_01, val); - val = (val >> 8) & 0x7; - switch (val ) { - case 0: - printf("DDR0: Write Out-of-Range command\n"); + printf("regs %p ",regs); + switch( regs->msr & 0x000F0000) { + case (0x80000000>>12): + printf("Machine check signal - probably due to mm fault\n" + "with mmu off\n"); break; - case 1: - printf("DDR0: Read Out-of-Range command\n"); + case (0x80000000>>13): + printf("Transfer error ack signal\n"); break; - case 2: - printf("DDR0: Masked write Out-of-Range command\n"); + case (0x80000000>>14): + printf("Data parity signal\n"); break; - case 4: - printf("DDR0: Wrap write Out-of-Range command\n"); - break; - case 5: - printf("DDR0: Wrap read Out-of-Range command\n"); + case (0x80000000>>15): + printf("Address parity signal\n"); break; default: - mfsdram(DDR0_01, value2); - printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2); + printf("Unknown values in msr\n"); } - mfsdram(DDR0_23, val); - if (((val >> 16) & 0xff) && corr_ecc) - printf("DDR0: Syndrome for correctable ECC event 0x%lx\n", - (val >> 16) & 0xff); - mfsdram(DDR0_23, val); - if (((val >> 8) & 0xff) && uncorr_ecc) - printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n", - (val >> 8) & 0xff); - mfsdram(DDR0_33, val); - if (val) - printf("DDR0: Address of command that caused an " - "Out-of-Range interrupt %lx\n", val); - mfsdram(DDR0_34, val); - if (val && uncorr_ecc) - printf("DDR0: Address of uncorrectable ECC event %lx\n", val); - mfsdram(DDR0_35, val); - if (val && uncorr_ecc) - printf("DDR0: Address of uncorrectable ECC event %lx\n", val); - mfsdram(DDR0_36, val); - if (val && uncorr_ecc) - printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val); - mfsdram(DDR0_37, val); - if (val && uncorr_ecc) - printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val); - mfsdram(DDR0_38, val); - if (val && corr_ecc) - printf("DDR0: Address of correctable ECC event %lx\n", val); - mfsdram(DDR0_39, val); - if (val && corr_ecc) - printf("DDR0: Address of correctable ECC event %lx\n", val); - mfsdram(DDR0_40, val); - if (val && corr_ecc) - printf("DDR0: Data of correctable ECC event 0x%08lx\n", val); - mfsdram(DDR0_41, val); - if (val && corr_ecc) - printf("DDR0: Data of correctable ECC event 0x%08lx\n", val); -#endif /* CONFIG_440EPX */ -#endif /* CONFIG_440 */ show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("machine check"); @@ -311,7 +189,7 @@ MachineCheckException(struct pt_regs *regs) void AlignmentException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -326,7 +204,7 @@ ProgramCheckException(struct pt_regs *regs) { long esr_val; -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -346,7 +224,7 @@ ProgramCheckException(struct pt_regs *regs) } void -DecrementerPITException(struct pt_regs *regs) +PITException(struct pt_regs *regs) { /* * Reset PIT interrupt @@ -363,7 +241,7 @@ DecrementerPITException(struct pt_regs *regs) void UnknownException(struct pt_regs *regs) { -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) if (debugger_exception_handler && (*debugger_exception_handler)(regs)) return; #endif @@ -378,7 +256,7 @@ DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) do_bedbug_breakpoint( regs ); #endif } @@ -394,17 +272,17 @@ addr_probe(uint *addr) __asm__ __volatile__( \ "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); + " eieio\n" \ + " li %0,0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (retval) : "r"(addr)); return (retval); #endif diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c index 5dbd84227..bb5765891 100644 --- a/cpu/ppc4xx/usb_ohci.c +++ b/cpu/ppc4xx/usb_ohci.c @@ -56,8 +56,8 @@ #define OHCI_CONTROL_INIT \ (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE -#define readl(a) (*((volatile u32 *)(a))) -#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) +#define readl(a) (*((vu_long *)(a))) +#define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) @@ -76,7 +76,7 @@ #define m16_swap(x) swap_16(x) #define m32_swap(x) swap_32(x) -#if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX) +#ifdef CONFIG_440EP #define ohci_cpu_to_le16(x) (x) #define ohci_cpu_to_le32(x) (x) #else @@ -1599,11 +1599,7 @@ int usb_lowlevel_init(void) gohci.disabled = 1; gohci.sleeping = 0; gohci.irq = -1; -#if defined(CONFIG_440EP) gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); -#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST) - gohci.regs = (struct ohci_regs *)(CFG_USB_HOST); -#endif gohci.flags = 0; gohci.slot_name = "ppc440"; @@ -1625,10 +1621,8 @@ int usb_lowlevel_init(void) ohci_inited = 1; urb_finished = 1; -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) /* init the device driver */ usb_dev_init(); -#endif return 0; } diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index d71ba7710..8262c54be 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c @@ -3,11 +3,11 @@ #include #include -#if (defined(CONFIG_440EP) || defined(CONFIG_440EPX)) && defined(CONFIG_CMD_USB) +#ifdef CONFIG_440EP #include #include "usbdev.h" -#include +#include "vecnum.h" #define USB_DT_DEVICE 0x01 #define USB_DT_CONFIG 0x02 @@ -186,21 +186,6 @@ int usbInt(void) return 0; } -#if defined(CONFIG_440EPX) -void usb_dev_init() -{ - printf("USB 2.0 Device init\n"); - - /*usb dev init */ - *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */ - - /*enable interrupts */ - *(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f; - - irq_install_handler(VECNUM_HSB2D, (interrupt_handler_t *) usbInt, - NULL); -} -#else void usb_dev_init() { #ifdef USB_2_0_DEVICE @@ -225,6 +210,5 @@ void usb_dev_init() irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt, NULL); } -#endif -#endif /* CONFIG_440EP || CONFIG_440EPX */ +#endif /*CONFIG_440EP */ diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h new file mode 100644 index 000000000..93cef026a --- /dev/null +++ b/cpu/ppc4xx/vecnum.h @@ -0,0 +1,170 @@ +/* +* Copyright (C) 2002 Scott McNutt +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +/* + * Interrupt vector number definitions to ease the + * 405 -- 440 porting pain ;-) + * + * NOTE: They're not all here yet ... update as needed. + * + */ + +#ifndef _VECNUMS_H_ +#define _VECNUMS_H_ + +#if defined(CONFIG_440SPE) +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_MSI0 7 /* PCI MSI level 0 */ +#define VECNUM_MSI1 8 /* PCI MSI level 0 */ +#define VECNUM_MSI2 9 /* PCI MSI level 0 */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_MS (32 + 1 ) /* MAL SERR */ +#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ +#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ +#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ +#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ +#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ +#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ +#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ +#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ + +/* UIC 2 */ +#define VECNUM_EIR5 (62 + 24) /* External interrupt 5 */ +#define VECNUM_EIR4 (62 + 25) /* External interrupt 4 */ +#define VECNUM_EIR3 (62 + 26) /* External interrupt 3 */ +#define VECNUM_EIR2 (62 + 27) /* External interrupt 2 */ +#define VECNUM_EIR1 (62 + 28) /* External interrupt 1 */ +#define VECNUM_EIR0 (62 + 29) /* External interrupt 0 */ + +#elif defined(CONFIG_440SP) + +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */ +#define VECNUM_MS (32 + 1) /* MAL SERR */ +#define VECNUM_TXDE (32 + 2) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 3) /* MAL RXDE */ +#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */ +#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */ +#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */ +#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */ +#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */ +#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */ +#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ + +#elif defined(CONFIG_440) + +/* UIC 0 */ +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_IIC0 2 /* IIC0 */ +#define VECNUM_IIC1 3 /* IIC1 */ +#define VECNUM_PIM 4 /* PCI inbound message */ +#define VECNUM_PCRW 5 /* PCI command reg write */ +#define VECNUM_PPM 6 /* PCI power management */ +#define VECNUM_MSI0 7 /* PCI MSI level 0 */ +#define VECNUM_MSI1 8 /* PCI MSI level 0 */ +#define VECNUM_MSI2 9 /* PCI MSI level 0 */ +#define VECNUM_MTE 10 /* MAL TXEOB */ +#define VECNUM_MRE 11 /* MAL RXEOB */ +#define VECNUM_D0 12 /* DMA channel 0 */ +#define VECNUM_D1 13 /* DMA channel 1 */ +#define VECNUM_D2 14 /* DMA channel 2 */ +#define VECNUM_D3 15 /* DMA channel 3 */ +#define VECNUM_CT0 18 /* GPT compare timer 0 */ +#define VECNUM_CT1 19 /* GPT compare timer 1 */ +#define VECNUM_CT2 20 /* GPT compare timer 2 */ +#define VECNUM_CT3 21 /* GPT compare timer 3 */ +#define VECNUM_CT4 22 /* GPT compare timer 4 */ +#define VECNUM_EIR0 23 /* External interrupt 0 */ +#define VECNUM_EIR1 24 /* External interrupt 1 */ +#define VECNUM_EIR2 25 /* External interrupt 2 */ +#define VECNUM_EIR3 26 /* External interrupt 3 */ +#define VECNUM_EIR4 27 /* External interrupt 4 */ +#define VECNUM_EIR5 28 /* External interrupt 5 */ +#define VECNUM_EIR6 29 /* External interrupt 6 */ +#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ +#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ + +/* UIC 1 */ +#define VECNUM_MS (32 + 0 ) /* MAL SERR */ +#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */ +#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */ +#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */ +#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ + +#else /* !defined(CONFIG_440) */ + +#define VECNUM_U0 0 /* UART0 */ +#define VECNUM_U1 1 /* UART1 */ +#define VECNUM_D0 5 /* DMA channel 0 */ +#define VECNUM_D1 6 /* DMA channel 1 */ +#define VECNUM_D2 7 /* DMA channel 2 */ +#define VECNUM_D3 8 /* DMA channel 3 */ +#define VECNUM_EWU0 9 /* Ethernet wakeup */ +#define VECNUM_MS 10 /* MAL SERR */ +#define VECNUM_MTE 11 /* MAL TXEOB */ +#define VECNUM_MRE 12 /* MAL RXEOB */ +#define VECNUM_TXDE 13 /* MAL TXDE */ +#define VECNUM_RXDE 14 /* MAL RXDE */ +#define VECNUM_ETH0 15 /* Ethernet interrupt status */ +#define VECNUM_EIR0 25 /* External interrupt 0 */ +#define VECNUM_EIR1 26 /* External interrupt 1 */ +#define VECNUM_EIR2 27 /* External interrupt 2 */ +#define VECNUM_EIR3 28 /* External interrupt 3 */ +#define VECNUM_EIR4 29 /* External interrupt 4 */ +#define VECNUM_EIR5 30 /* External interrupt 5 */ +#define VECNUM_EIR6 31 /* External interrupt 6 */ + +#endif /* defined(CONFIG_440) */ + +#endif /* _VECNUMS_H_ */ diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile index 8b4367e20..1af53d6ad 100644 --- a/cpu/pxa/Makefile +++ b/cpu/pxa/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o usb.o +OBJS = serial.o interrupts.o cpu.o i2c.o pxafb.o mmc.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk index f0b86b7dc..fb810ca7c 100644 --- a/cpu/pxa/config.mk +++ b/cpu/pxa/config.mk @@ -25,7 +25,8 @@ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ -msoft-float -PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale +#PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100 +PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale # ========================================================================= # # Supply options according to compiler version diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c index df537c435..722d94947 100644 --- a/cpu/pxa/i2c.c +++ b/cpu/pxa/i2c.c @@ -45,7 +45,7 @@ #include #include -/*#define DEBUG_I2C 1 /###* activate local debugging output */ +/*#define DEBUG_I2C 1 /###* activate local debugging output */ #define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ #if (CFG_I2C_SPEED == 400000) @@ -191,8 +191,8 @@ int i2c_transfer(struct i2c_msg *msg) /* start receive */ ICR &= ~ICR_START; ICR &= ~ICR_STOP; - if (msg->condition == I2C_COND_START) ICR |= ICR_START; - if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; + if (msg->condition == I2C_COND_START) ICR |= ICR_START; + if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; ICR &= ~ICR_ALDIE; @@ -267,7 +267,7 @@ void i2c_init(int speed, int slaveaddr) * i2c_probe: - Test if a chip answers for a given i2c address * * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise + * @return: 0 if a chip was found, -1 otherwhise */ int i2c_probe(uchar chip) @@ -457,7 +457,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) uchar i2c_reg_read (uchar chip, uchar reg) { - uchar buf; + char buf; PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg)); i2c_read(chip, reg, 1, &buf, 1); diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c index 8b577e135..0479a1048 100644 --- a/cpu/pxa/interrupts.c +++ b/cpu/pxa/interrupts.c @@ -30,9 +30,126 @@ #include #ifdef CONFIG_USE_IRQ +/* enable IRQ/FIQ interrupts */ +void enable_interrupts (void) +{ #error: interrupts not implemented yet +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ +#error: interrupts not implemented yet +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} #endif + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + + int interrupt_init (void) { /* nothing happens here - we don't setup any IRQs */ diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c index 121dcbe13..f7020eec9 100644 --- a/cpu/pxa/mmc.c +++ b/cpu/pxa/mmc.c @@ -30,13 +30,14 @@ #ifdef CONFIG_MMC -extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no); +extern int +fat_register_device(block_dev_desc_t *dev_desc, int part_no); static block_dev_desc_t mmc_dev; -block_dev_desc_t *mmc_get_dev(int dev) +block_dev_desc_t * mmc_get_dev(int dev) { - return ((block_dev_desc_t *) & mmc_dev); + return ((block_dev_desc_t *)&mmc_dev); } /* @@ -44,59 +45,72 @@ block_dev_desc_t *mmc_get_dev(int dev) * and other parameters */ static uchar mmc_buf[MMC_BLOCK_SIZE]; -static uchar spec_ver; +static mmc_csd_t mmc_csd; static int mmc_ready = 0; -static int wide = 0; -static uint32_t * + +static uchar * /****************************************************/ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat) /****************************************************/ { - static uint32_t resp[4], a, b, c; + static uchar resp[20]; ulong status; - int i; + int words, i; - debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl, - cmdat | wide); + debug("mmc_cmd %x %x %x %x\n", cmd, argh, argl, cmdat); MMC_STRPCL = MMC_STRPCL_STOP_CLK; MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; - while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)) ; - MMC_CMD = cmd; - MMC_ARGH = argh; - MMC_ARGL = argl; - MMC_CMDAT = cmdat | wide; + while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)); + MMC_CMD = cmd; + MMC_ARGH = argh; + MMC_ARGL = argl; + MMC_CMDAT = cmdat; MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES; MMC_STRPCL = MMC_STRPCL_START_CLK; - while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)) ; + while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)); status = MMC_STAT; - debug("MMC status 0x%08x\n", status); + debug("MMC status %x\n", status); if (status & MMC_STAT_TIME_OUT_RESPONSE) { return 0; } - /* Linux says: - * Did I mention this is Sick. We always need to - * discard the upper 8 bits of the first 16-bit word. - */ - a = (MMC_RES & 0xffff); - for (i = 0; i < 4; i++) { - b = (MMC_RES & 0xffff); - c = (MMC_RES & 0xffff); - resp[i] = (a << 24) | (b << 8) | (c >> 8); - a = c; - debug("MMC resp[%d] = %#08x\n", i, resp[i]); - } + switch (cmdat & 0x3) { + case MMC_CMDAT_R1: + case MMC_CMDAT_R3: + words = 3; + break; + case MMC_CMDAT_R2: + words = 8; + break; + + default: + return 0; + } + for (i = words-1; i >= 0; i--) { + ulong res_fifo = MMC_RES; + int offset = i << 1; + + resp[offset] = ((uchar *)&res_fifo)[0]; + resp[offset+1] = ((uchar *)&res_fifo)[1]; + } +#ifdef MMC_DEBUG + for (i=0; i> 16; argl = len & 0xffff; /* set block len */ - mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); + resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); /* send read command */ argh = src >> 16; @@ -119,17 +133,17 @@ mmc_block_read(uchar * dst, ulong src, ulong len) MMC_RDTO = 0xffff; MMC_NOB = 1; MMC_BLKLEN = len; - mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl, - MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK | - MMC_CMDAT_DATA_EN); + resp = mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl, + MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); + MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ; while (len) { if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) { #ifdef CONFIG_PXA27X int i; - for (i = min(len, 32); i; i--) { - *dst++ = *((volatile uchar *)&MMC_RXFIFO); + for (i=min(len,32); i; i--) { + *dst++ = * ((volatile uchar *) &MMC_RXFIFO); len--; } #else @@ -144,7 +158,7 @@ mmc_block_read(uchar * dst, ulong src, ulong len) } } MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; - while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ; + while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)); status = MMC_STAT; if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); @@ -155,9 +169,10 @@ mmc_block_read(uchar * dst, ulong src, ulong len) int /****************************************************/ -mmc_block_write(ulong dst, uchar * src, int len) +mmc_block_write(ulong dst, uchar *src, int len) /****************************************************/ { + uchar *resp; ushort argh, argl; ulong status; @@ -165,13 +180,13 @@ mmc_block_write(ulong dst, uchar * src, int len) return 0; } - debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong) src, len); + debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong)src, len); argh = len >> 16; argl = len & 0xffff; /* set block len */ - mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); + resp = mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1); /* send write command */ argh = dst >> 16; @@ -179,16 +194,15 @@ mmc_block_write(ulong dst, uchar * src, int len) MMC_STRPCL = MMC_STRPCL_STOP_CLK; MMC_NOB = 1; MMC_BLKLEN = len; - mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl, - MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK | - MMC_CMDAT_DATA_EN); + resp = mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl, + MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN); MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ; while (len) { if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) { - int i, bytes = min(32, len); + int i, bytes = min(32,len); - for (i = 0; i < bytes; i++) { + for (i=0; i> __shft; \ - if (__size + __shft > 32) \ - __res |= resp[__off-1] << ((32 - __shft) % 32); \ - __res & __mask; \ - }) - -/* - * Given the decoded CSD structure, decode the raw CID to our CID structure. - */ -static void mmc_decode_cid(uint32_t * resp) -{ - if (IF_TYPE_SD == mmc_dev.if_type) { - /* - * SD doesn't currently have a version field so we will - * have to assume we can parse this. - */ - sprintf((char *)mmc_dev.vendor, - "Man %02x OEM %c%c \"%c%c%c%c%c\" Date %02u/%04u", - UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, 112, 8), - UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp, 96, 8), - UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp, 80, 8), - UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp, 64, 8), - UNSTUFF_BITS(resp, 8, 4), UNSTUFF_BITS(resp, 12, - 8) + 2000); - sprintf((char *)mmc_dev.revision, "%d.%d", - UNSTUFF_BITS(resp, 60, 4), UNSTUFF_BITS(resp, 56, 4)); - sprintf((char *)mmc_dev.product, "%u", - UNSTUFF_BITS(resp, 24, 32)); - } else { - /* - * The selection of the format here is based upon published - * specs from sandisk and from what people have reported. - */ - switch (spec_ver) { - case 0: /* MMC v1.0 - v1.2 */ - case 1: /* MMC v1.4 */ - sprintf((char *)mmc_dev.vendor, - "Man %02x%02x%02x \"%c%c%c%c%c%c%c\" Date %02u/%04u", - UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, - 112, - 8), - UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp, - 96, 8), - UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp, - 80, 8), - UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp, - 64, 8), - UNSTUFF_BITS(resp, 56, 8), UNSTUFF_BITS(resp, - 48, 8), - UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8, - 4) + - 1997); - sprintf((char *)mmc_dev.revision, "%d.%d", - UNSTUFF_BITS(resp, 44, 4), UNSTUFF_BITS(resp, - 40, 4)); - sprintf((char *)mmc_dev.product, "%u", - UNSTUFF_BITS(resp, 16, 24)); - break; - - case 2: /* MMC v2.0 - v2.2 */ - case 3: /* MMC v3.1 - v3.3 */ - case 4: /* MMC v4 */ - sprintf((char *)mmc_dev.vendor, - "Man %02x OEM %04x \"%c%c%c%c%c%c\" Date %02u/%04u", - UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, - 104, - 16), - UNSTUFF_BITS(resp, 96, 8), UNSTUFF_BITS(resp, - 88, 8), - UNSTUFF_BITS(resp, 80, 8), UNSTUFF_BITS(resp, - 72, 8), - UNSTUFF_BITS(resp, 64, 8), UNSTUFF_BITS(resp, - 56, 8), - UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8, - 4) + - 1997); - sprintf((char *)mmc_dev.product, "%u", - UNSTUFF_BITS(resp, 16, 32)); - sprintf((char *)mmc_dev.revision, "N/A"); - break; - - default: - printf("MMC card has unknown MMCA version %d\n", - spec_ver); - break; - } - } - printf("%s card.\nVendor: %s\nProduct: %s\nRevision: %s\n", - (IF_TYPE_SD == mmc_dev.if_type) ? "SD" : "MMC", mmc_dev.vendor, - mmc_dev.product, mmc_dev.revision); -} - -/* - * Given a 128-bit response, decode to our card CSD structure. - */ -static void mmc_decode_csd(uint32_t * resp) -{ - unsigned int mult, csd_struct; - - if (IF_TYPE_SD == mmc_dev.if_type) { - csd_struct = UNSTUFF_BITS(resp, 126, 2); - if (csd_struct != 0) { - printf("SD: unrecognised CSD structure version %d\n", - csd_struct); - return; - } - } else { - /* - * We only understand CSD structure v1.1 and v1.2. - * v1.2 has extra information in bits 15, 11 and 10. - */ - csd_struct = UNSTUFF_BITS(resp, 126, 2); - if (csd_struct != 1 && csd_struct != 2) { - printf("MMC: unrecognised CSD structure version %d\n", - csd_struct); - return; - } - - spec_ver = UNSTUFF_BITS(resp, 122, 4); - mmc_dev.if_type = IF_TYPE_MMC; - } - - mult = 1 << (UNSTUFF_BITS(resp, 47, 3) + 2); - mmc_dev.lba = (1 + UNSTUFF_BITS(resp, 62, 12)) * mult; - mmc_dev.blksz = 1 << UNSTUFF_BITS(resp, 80, 4); - - /* FIXME: The following just makes assumes that's the partition type -- should really read it */ - mmc_dev.part_type = PART_TYPE_DOS; - mmc_dev.dev = 0; - mmc_dev.lun = 0; - mmc_dev.type = DEV_TYPE_HARDDISK; - mmc_dev.removable = 0; - mmc_dev.block_read = mmc_bread; - - printf("Detected: %lu blocks of %lu bytes (%luMB) ", - mmc_dev.lba, - mmc_dev.blksz, - mmc_dev.lba * mmc_dev.blksz / (1024 * 1024)); -} - int /****************************************************/ mmc_init(int verbose) /****************************************************/ { - int retries, rc = -ENODEV; - uint32_t cid_resp[4]; - uint32_t *resp; - uint16_t rca = 0; + int retries, rc = -ENODEV; + uchar *resp; - /* Reset device interface type */ - mmc_dev.if_type = IF_TYPE_UNKNOWN; - -#if defined (CONFIG_LUBBOCK) || (defined (CONFIG_GUMSTIX) && !defined(CONFIG_PXA27X)) - set_GPIO_mode(GPIO6_MMCCLK_MD); - set_GPIO_mode(GPIO8_MMCCS0_MD); +#ifdef CONFIG_LUBBOCK + set_GPIO_mode( GPIO6_MMCCLK_MD ); + set_GPIO_mode( GPIO8_MMCCS0_MD ); +#endif + CKEN |= CKEN12_MMC; /* enable MMC unit clock */ +#if defined(CONFIG_ADSVIX) + /* turn on the power */ + GPCR(114) = GPIO_bit(114); + udelay(1000); #endif - CKEN |= CKEN12_MMC; /* enable MMC unit clock */ - MMC_CLKRT = MMC_CLKRT_0_3125MHZ; - MMC_RESTO = MMC_RES_TO_MAX; - MMC_SPI = MMC_SPI_DISABLE; + mmc_csd.c_size = 0; + + MMC_CLKRT = MMC_CLKRT_0_3125MHZ; + MMC_RESTO = MMC_RES_TO_MAX; + MMC_SPI = MMC_SPI_DISABLE; /* reset */ - mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); - udelay(200000); - retries = 3; - while (retries--) { - resp = mmc_cmd(MMC_CMD_APP_CMD, 0, 0, MMC_CMDAT_R1); - if (!(resp[0] & 0x00000020)) { /* Card does not support APP_CMD */ - debug("Card does not support APP_CMD\n"); - break; - } - - /* Select 3.2-3.3 and 3.3-3.4V */ - resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0020, 0, - MMC_CMDAT_R3 | (retries < 2 ? 0 - : MMC_CMDAT_INIT)); - if (resp[0] & 0x80000000) { - mmc_dev.if_type = IF_TYPE_SD; - debug("Detected SD card\n"); - break; - } + retries = 10; + resp = mmc_cmd(0, 0, 0, 0); + resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3); + while (retries-- && resp && !(resp[4] & 0x80)) { + debug("resp %x %x\n", resp[0], resp[1]); #ifdef CONFIG_PXA27X udelay(10000); #else - udelay(200000); + udelay(50); #endif - } - - if (retries <= 0 || !(IF_TYPE_SD == mmc_dev.if_type)) { - debug("Failed to detect SD Card, trying MMC\n"); - resp = - mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000, MMC_CMDAT_R3); - - retries = 10; - while (retries-- && resp && !(resp[0] & 0x80000000)) { -#ifdef CONFIG_PXA27X - udelay(10000); -#else - udelay(200000); -#endif - resp = - mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000, - MMC_CMDAT_R3); - } + resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3); } /* try to get card id */ - resp = - mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, 0, MMC_CMDAT_R2 | MMC_CMDAT_BUSY); + resp = mmc_cmd(2, 0, 0, MMC_CMDAT_R2); if (resp) { - memcpy(cid_resp, resp, sizeof(cid_resp)); + /* TODO configure mmc driver depending on card attributes */ + mmc_cid_t *cid = (mmc_cid_t *)resp; + if (verbose) { + printf("MMC found. Card desciption is:\n"); + printf("Manufacturer ID = %02x%02x%02x\n", + cid->id[0], cid->id[1], cid->id[2]); + printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev); + cid->hwrev = cid->fwrev = 0; /* null terminate string */ + printf("Product Name = %s\n",cid->name); + printf("Serial Number = %02x%02x%02x\n", + cid->sn[0], cid->sn[1], cid->sn[2]); + printf("Month = %d\n",cid->month); + printf("Year = %d\n",1997 + cid->year); + } + /* fill in device description */ + mmc_dev.if_type = IF_TYPE_MMC; + mmc_dev.part_type = PART_TYPE_DOS; + mmc_dev.dev = 0; + mmc_dev.lun = 0; + mmc_dev.type = 0; + /* FIXME fill in the correct size (is set to 32MByte) */ + mmc_dev.blksz = 512; + mmc_dev.lba = 0x10000; + sprintf(mmc_dev.vendor,"Man %02x%02x%02x Snr %02x%02x%02x", + cid->id[0], cid->id[1], cid->id[2], + cid->sn[0], cid->sn[1], cid->sn[2]); + sprintf(mmc_dev.product,"%s",cid->name); + sprintf(mmc_dev.revision,"%x %x",cid->hwrev, cid->fwrev); + mmc_dev.removable = 0; + mmc_dev.block_read = mmc_bread; /* MMC exists, get CSD too */ - resp = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, 0, 0, MMC_CMDAT_R1); - if (IF_TYPE_SD == mmc_dev.if_type) - rca = ((resp[0] & 0xffff0000) >> 16); - resp = mmc_cmd(MMC_CMD_SEND_CSD, rca, 0, MMC_CMDAT_R2); + resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1); + resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R2); if (resp) { - mmc_decode_csd(resp); + mmc_csd_t *csd = (mmc_csd_t *)resp; + memcpy(&mmc_csd, csd, sizeof(csd)); rc = 0; mmc_ready = 1; + /* FIXME add verbose printout for csd */ } - - mmc_decode_cid(cid_resp); } - MMC_CLKRT = 0; /* 20 MHz */ - resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1); - #ifdef CONFIG_PXA27X - if (IF_TYPE_SD == mmc_dev.if_type) { - resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1); - resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1); - wide = MMC_CMDAT_SD_4DAT; - } + MMC_CLKRT = 1; /* 10 MHz - see Intel errata */ +#else + MMC_CLKRT = 0; /* 20 MHz */ #endif + resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1); - fat_register_device(&mmc_dev, 1); /* partitions start counting with 1 */ + fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */ return rc; } -int mmc_ident(block_dev_desc_t * dev) +int +mmc_ident(block_dev_desc_t *dev) { return 0; } -int mmc2info(ulong addr) +int +mmc2info(ulong addr) { - if (addr >= CFG_MMC_BASE - && addr < CFG_MMC_BASE + (mmc_dev.lba * mmc_dev.blksz)) { + /* FIXME hard codes to 32 MB device */ + if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) { return 1; } return 0; } -#endif /* CONFIG_MMC */ +#endif /* CONFIG_MMC */ diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c index 9ba457e75..cb3a47899 100644 --- a/cpu/pxa/serial.c +++ b/cpu/pxa/serial.c @@ -30,28 +30,11 @@ #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; -#define FFUART_INDEX 0 -#define BTUART_INDEX 1 -#define STUART_INDEX 2 - -#ifndef CONFIG_SERIAL_MULTI -#if defined (CONFIG_FFUART) -#define UART_INDEX FFUART_INDEX -#elif defined (CONFIG_BTUART) -#define UART_INDEX BTUART_INDEX -#elif defined (CONFIG_STUART) -#define UART_INDEX STUART_INDEX -#else -#error "Bad: you didn't configure serial ..." -#endif -#endif - -void pxa_setbrg_dev (unsigned int uart_index) +void serial_setbrg (void) { unsigned int quot = 0; @@ -70,68 +53,63 @@ void pxa_setbrg_dev (unsigned int uart_index) else hang (); - switch (uart_index) { - case FFUART_INDEX: +#ifdef CONFIG_FFUART #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_22_FFUART; + CKENA |= CKENA_22_FFUART; #else - CKEN |= CKEN6_FFUART; + CKEN |= CKEN6_FFUART; #endif /* CONFIG_CPU_MONAHANS */ - FFIER = 0; /* Disable for now */ - FFFCR = 0; /* No fifos enabled */ + FFIER = 0; /* Disable for now */ + FFFCR = 0; /* No fifos enabled */ - /* set baud rate */ - FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - FFDLL = quot & 0xff; - FFDLH = quot >> 8; - FFLCR = LCR_WLS0 | LCR_WLS1; + /* set baud rate */ + FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; + FFDLL = quot & 0xff; + FFDLH = quot >> 8; + FFLCR = LCR_WLS0 | LCR_WLS1; - FFIER = IER_UUE; /* Enable FFUART */ - break; + FFIER = IER_UUE; /* Enable FFUART */ - case BTUART_INDEX: +#elif defined(CONFIG_BTUART) #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_21_BTUART; + CKENA |= CKENA_21_BTUART; #else - CKEN |= CKEN7_BTUART; + CKEN |= CKEN7_BTUART; #endif /* CONFIG_CPU_MONAHANS */ - BTIER = 0; - BTFCR = 0; + BTIER = 0; + BTFCR = 0; - /* set baud rate */ - BTLCR = LCR_DLAB; - BTDLL = quot & 0xff; - BTDLH = quot >> 8; - BTLCR = LCR_WLS0 | LCR_WLS1; + /* set baud rate */ + BTLCR = LCR_DLAB; + BTDLL = quot & 0xff; + BTDLH = quot >> 8; + BTLCR = LCR_WLS0 | LCR_WLS1; - BTIER = IER_UUE; /* Enable BFUART */ + BTIER = IER_UUE; /* Enable BFUART */ - break; - - case STUART_INDEX: +#elif defined(CONFIG_STUART) #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_23_STUART; + CKENA |= CKENA_23_STUART; #else - CKEN |= CKEN5_STUART; + CKEN |= CKEN5_STUART; #endif /* CONFIG_CPU_MONAHANS */ - STIER = 0; - STFCR = 0; + STIER = 0; + STFCR = 0; - /* set baud rate */ - STLCR = LCR_DLAB; - STDLL = quot & 0xff; - STDLH = quot >> 8; - STLCR = LCR_WLS0 | LCR_WLS1; + /* set baud rate */ + STLCR = LCR_DLAB; + STDLL = quot & 0xff; + STDLH = quot >> 8; + STLCR = LCR_WLS0 | LCR_WLS1; - STIER = IER_UUE; /* Enable STUART */ - break; + STIER = IER_UUE; /* Enable STUART */ - default: - hang(); - } +#else +#error "Bad: you didn't configure serial ..." +#endif } @@ -140,9 +118,9 @@ void pxa_setbrg_dev (unsigned int uart_index) * are always 8 data bits, no parity, 1 stop bit, no start bits. * */ -int pxa_init_dev (unsigned int uart_index) +int serial_init (void) { - pxa_setbrg_dev (uart_index); + serial_setbrg (); return (0); } @@ -151,32 +129,26 @@ int pxa_init_dev (unsigned int uart_index) /* * Output a single byte to the serial port. */ -void pxa_putc_dev (unsigned int uart_index,const char c) +void serial_putc (const char c) { - switch (uart_index) { - case FFUART_INDEX: - /* wait for room in the tx FIFO on FFUART */ - while ((FFLSR & LSR_TEMT) == 0) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - FFTHR = c; - break; - - case BTUART_INDEX: - while ((BTLSR & LSR_TEMT ) == 0 ) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - BTTHR = c; - break; - - case STUART_INDEX: - while ((STLSR & LSR_TEMT ) == 0 ) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - STTHR = c; - break; - } +#ifdef CONFIG_FFUART + /* wait for room in the tx FIFO on FFUART */ + while ((FFLSR & LSR_TEMT) == 0) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + FFTHR = c; +#elif defined(CONFIG_BTUART) + while ((BTLSR & LSR_TEMT ) == 0 ) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + BTTHR = c; +#elif defined(CONFIG_STUART) + while ((STLSR & LSR_TEMT ) == 0 ) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + STTHR = c; +#endif /* If \n, also do \r */ if (c == '\n') - pxa_putc_dev (uart_index,'\r'); + serial_putc ('\r'); } /* @@ -184,17 +156,15 @@ void pxa_putc_dev (unsigned int uart_index,const char c) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -int pxa_tstc_dev (unsigned int uart_index) +int serial_tstc (void) { - switch (uart_index) { - case FFUART_INDEX: - return FFLSR & LSR_DR; - case BTUART_INDEX: - return BTLSR & LSR_DR; - case STUART_INDEX: - return STLSR & LSR_DR; - } - return -1; +#ifdef CONFIG_FFUART + return FFLSR & LSR_DR; +#elif defined(CONFIG_BTUART) + return BTLSR & LSR_DR; +#elif defined(CONFIG_STUART) + return STLSR & LSR_DR; +#endif } /* @@ -202,184 +172,27 @@ int pxa_tstc_dev (unsigned int uart_index) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -int pxa_getc_dev (unsigned int uart_index) +int serial_getc (void) { - switch (uart_index) { - case FFUART_INDEX: - while (!(FFLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) FFRBR & 0xff; - - case BTUART_INDEX: - while (!(BTLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) BTRBR & 0xff; - case STUART_INDEX: - while (!(STLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) STRBR & 0xff; - } - return -1; +#ifdef CONFIG_FFUART + while (!(FFLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) FFRBR & 0xff; +#elif defined(CONFIG_BTUART) + while (!(BTLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) BTRBR & 0xff; +#elif defined(CONFIG_STUART) + while (!(STLSR & LSR_DR)) + WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ + return (char) STRBR & 0xff; +#endif } void -pxa_puts_dev (unsigned int uart_index,const char *s) +serial_puts (const char *s) { while (*s) { - pxa_putc_dev (uart_index,*s++); + serial_putc (*s++); } } - -#if defined (CONFIG_FFUART) -static int ffuart_init(void) -{ - return pxa_init_dev(FFUART_INDEX); -} - -static void ffuart_setbrg(void) -{ - return pxa_setbrg_dev(FFUART_INDEX); -} - -static void ffuart_putc(const char c) -{ - return pxa_putc_dev(FFUART_INDEX,c); -} - -static void ffuart_puts(const char *s) -{ - return pxa_puts_dev(FFUART_INDEX,s); -} - -static int ffuart_getc(void) -{ - return pxa_getc_dev(FFUART_INDEX); -} - -static int ffuart_tstc(void) -{ - return pxa_tstc_dev(FFUART_INDEX); -} - -struct serial_device serial_ffuart_device = -{ - "serial_ffuart", - "PXA", - ffuart_init, - ffuart_setbrg, - ffuart_getc, - ffuart_tstc, - ffuart_putc, - ffuart_puts, -}; -#endif - -#if defined (CONFIG_BTUART) -static int btuart_init(void) -{ - return pxa_init_dev(BTUART_INDEX); -} - -static void btuart_setbrg(void) -{ - return pxa_setbrg_dev(BTUART_INDEX); -} - -static void btuart_putc(const char c) -{ - return pxa_putc_dev(BTUART_INDEX,c); -} - -static void btuart_puts(const char *s) -{ - return pxa_puts_dev(BTUART_INDEX,s); -} - -static int btuart_getc(void) -{ - return pxa_getc_dev(BTUART_INDEX); -} - -static int btuart_tstc(void) -{ - return pxa_tstc_dev(BTUART_INDEX); -} - -struct serial_device serial_btuart_device = -{ - "serial_btuart", - "PXA", - btuart_init, - btuart_setbrg, - btuart_getc, - btuart_tstc, - btuart_putc, - btuart_puts, -}; -#endif - -#if defined (CONFIG_STUART) -static int stuart_init(void) -{ - return pxa_init_dev(STUART_INDEX); -} - -static void stuart_setbrg(void) -{ - return pxa_setbrg_dev(STUART_INDEX); -} - -static void stuart_putc(const char c) -{ - return pxa_putc_dev(STUART_INDEX,c); -} - -static void stuart_puts(const char *s) -{ - return pxa_puts_dev(STUART_INDEX,s); -} - -static int stuart_getc(void) -{ - return pxa_getc_dev(STUART_INDEX); -} - -static int stuart_tstc(void) -{ - return pxa_tstc_dev(STUART_INDEX); -} - -struct serial_device serial_stuart_device = -{ - "serial_stuart", - "PXA", - stuart_init, - stuart_setbrg, - stuart_getc, - stuart_tstc, - stuart_putc, - stuart_puts, -}; -#endif - - -#ifndef CONFIG_SERIAL_MULTI -inline int serial_init(void) { - return (pxa_init_dev(UART_INDEX)); -} -void serial_setbrg(void) { - pxa_setbrg_dev(UART_INDEX); -} -int serial_getc(void) { - return(pxa_getc_dev(UART_INDEX)); -} -int serial_tstc(void) { - return(pxa_tstc_dev(UART_INDEX)); -} -void serial_putc(const char c) { - pxa_putc_dev(UART_INDEX,c); -} -void serial_puts(const char *s) { - pxa_puts_dev(UART_INDEX,s); -} -#endif /* CONFIG_SERIAL_MULTI */ diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index 23005e20f..ffaa30fdc 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -57,7 +57,7 @@ _fiq: .word fiq * Startup Code (reset vector) * * do important init only if we don't start from RAM! - * - relocate armboot to RAM + * - relocate armboot to ram * - setup stack * - jump to second stage */ @@ -90,7 +90,7 @@ IRQ_STACK_START: .globl FIQ_STACK_START FIQ_STACK_START: .word 0x0badc0de -#endif /* CONFIG_USE_IRQ */ +#endif /****************************************************************************/ @@ -100,18 +100,18 @@ FIQ_STACK_START: /****************************************************************************/ reset: - mrs r0,cpsr /* set the CPU to SVC32 mode */ + mrs r0,cpsr /* set the cpu to SVC32 mode */ bic r0,r0,#0x1f /* (superviser mode, M=10011) */ orr r0,r0,#0x13 msr cpsr,r0 /* * we do sys-critical inits only at reboot, - * not when booting from RAM! + * not when booting from ram! */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit /* we do sys-critical inits */ -#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */ +#endif #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ @@ -128,9 +128,9 @@ relocate: /* relocate U-Boot to RAM */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ + cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop -#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */ +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ /* Set up the stack */ stack_setup: @@ -139,7 +139,7 @@ stack_setup: sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif /* CONFIG_USE_IRQ */ +#endif sub sp, r0, #12 /* leave 3 words for abort-stack */ clear_bss: @@ -166,13 +166,13 @@ _start_armboot: .word start_armboot /* */ /****************************************************************************/ /* mk@tbd: Fix this! */ -#undef RCSR +#ifdef CONFIG_CPU_MONAHANS #undef ICMR #undef OSMR3 #undef OSCR #undef OWER #undef OIER -#undef CCCR +#endif /* Interrupt-Controller base address */ IC_BASE: .word 0x40d00000 @@ -193,18 +193,18 @@ OSTIMER_BASE: .word 0x40a00000 #ifdef CONFIG_CPU_MONAHANS # ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO # error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!" -# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */ +# endif # ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO # define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1 -# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */ -#else /* !CONFIG_CPU_MONAHANS */ +# endif +#else /* ! CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED CC_BASE: .word 0x41300000 #define CCCR 0x00 cpuspeed: .word CFG_CPUSPEED -#else /* !CFG_CPUSPEED */ +#else #error "You have to define CFG_CPUSPEED!!" -#endif /* CFG_CPUSPEED */ +#endif #endif /* CONFIG_CPU_MONAHANS */ /* takes care the CP15 update has taken place */ @@ -221,7 +221,7 @@ cpu_init_crit: ldr r0, IC_BASE mov r1, #0x00 str r1, [r0, #ICMR] -#else /* CONFIG_CPU_MONAHANS */ +#else /* Step 1 - Enable CP6 permission */ mrc p15, 0, r1, c15, c1, 0 @ read CPAR orr r1, r1, #0x40 @@ -240,14 +240,14 @@ cpu_init_crit: ldr r1, =CKENB ldr r2, =(CKENB_6_IRQ) str r2, [r1] -#endif /* !CONFIG_CPU_MONAHANS */ +#endif /* set clock speed */ #ifdef CONFIG_CPU_MONAHANS ldr r0, =ACCR ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK)) str r1, [r0] -#else /* !CONFIG_CPU_MONAHANS */ +#else /* ! CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED ldr r0, CC_BASE ldr r1, cpuspeed @@ -447,7 +447,7 @@ fiq: bl do_fiq /* effiction fiq_save_user_regs */ irq_restore_user_regs -#else /* !CONFIG_USE_IRQ */ +#else .align 5 irq: @@ -461,7 +461,7 @@ fiq: bad_save_user_regs bl do_fiq -#endif /* CONFIG_USE_IRQ */ +#endif /****************************************************************************/ /* */ diff --git a/cpu/s3c44b0/Makefile b/cpu/s3c44b0/Makefile index 790faebd3..d43c73e53 100644 --- a/cpu/s3c44b0/Makefile +++ b/cpu/s3c44b0/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o +OBJS = serial.o interrupts.o cpu.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c index eae6adbc0..5d50b3cea 100644 --- a/cpu/s3c44b0/cpu.c +++ b/cpu/s3c44b0/cpu.c @@ -155,7 +155,7 @@ int dcache_status (void) #define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10) #endif -int rtc_get (struct rtc_time* tm) +void rtc_get (struct rtc_time* tm) { RTCCON |= 1; tm->tm_year = BCD2HEX(BCDYEAR); @@ -184,8 +184,6 @@ int rtc_get (struct rtc_time* tm) tm->tm_year += 1900; else tm->tm_year += 2000; - - return 0; } void rtc_set (struct rtc_time* tm) diff --git a/cpu/s3c44b0/interrupts.c b/cpu/s3c44b0/interrupts.c index ed7964844..5d2c13d97 100644 --- a/cpu/s3c44b0/interrupts.c +++ b/cpu/s3c44b0/interrupts.c @@ -27,6 +27,8 @@ #include #include +#include + /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff @@ -35,8 +37,110 @@ #ifdef CONFIG_USE_IRQ #error CONFIG_USE_IRQ NOT supported +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} #endif + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = + { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26", + "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26", + "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", + "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32", + "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + static ulong timestamp; static ulong lastdec; diff --git a/cpu/s3c44b0/start.S b/cpu/s3c44b0/start.S index 1d88c1c03..7affe87b3 100644 --- a/cpu/s3c44b0/start.S +++ b/cpu/s3c44b0/start.S @@ -188,7 +188,7 @@ _start_armboot: .word start_armboot #define WTCON (0x01c00000+0x130000) cpu_init_crit: /* disable watch dog */ - ldr r0, =WTCON + ldr r0, =WTCON ldr r1, =0x0 str r1, [r0] @@ -211,7 +211,7 @@ cpu_init_crit: ldr r1, =PLLCON #if CONFIG_S3C44B0_CLOCK_SPEED==66 - ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ + ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ #elif CONFIG_S3C44B0_CLOCK_SPEED==75 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */ #else diff --git a/cpu/sa1100/Makefile b/cpu/sa1100/Makefile index 790faebd3..8c950daee 100644 --- a/cpu/sa1100/Makefile +++ b/cpu/sa1100/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,25 +23,21 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(CPU).a +LIB = lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o +OBJS = serial.o interrupts.o cpu.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(START) $(LIB) +all: .depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/interrupts.c index 53f27456a..b393e0d43 100644 --- a/cpu/sa1100/interrupts.c +++ b/cpu/sa1100/interrupts.c @@ -29,6 +29,143 @@ #include #include +#include + +#ifdef CONFIG_USE_IRQ +/* enable IRQ/FIQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__ ("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old, temp; + __asm__ __volatile__ ("mrs %0, cpsr\n" + "orr %1, %0, #0x80\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + + return (old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32" + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + + int interrupt_init (void) { /* nothing happens here - we don't setup any IRQs */ diff --git a/cpu/sa1100/start.S b/cpu/sa1100/start.S index 910650d15..431ee656e 100644 --- a/cpu/sa1100/start.S +++ b/cpu/sa1100/start.S @@ -157,7 +157,7 @@ stack_setup: clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ - mov r2, #0x00000000 /* clear */ + mov r2, #0x00000000 /* clear */ clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 @@ -349,31 +349,31 @@ cpu_init_crit: undefined_instruction: get_bad_stack bad_save_user_regs - bl do_undefined_instruction + bl do_undefined_instruction .align 5 software_interrupt: get_bad_stack bad_save_user_regs - bl do_software_interrupt + bl do_software_interrupt .align 5 prefetch_abort: get_bad_stack bad_save_user_regs - bl do_prefetch_abort + bl do_prefetch_abort .align 5 data_abort: get_bad_stack bad_save_user_regs - bl do_data_abort + bl do_data_abort .align 5 not_used: get_bad_stack bad_save_user_regs - bl do_not_used + bl do_not_used #ifdef CONFIG_USE_IRQ @@ -381,7 +381,7 @@ not_used: irq: get_irq_stack irq_save_user_regs - bl do_irq + bl do_irq irq_restore_user_regs .align 5 @@ -389,7 +389,7 @@ fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ irq_save_user_regs - bl do_fiq + bl do_fiq irq_restore_user_regs #else @@ -398,13 +398,13 @@ fiq: irq: get_bad_stack bad_save_user_regs - bl do_irq + bl do_irq .align 5 fiq: get_bad_stack bad_save_user_regs - bl do_fiq + bl do_fiq #endif diff --git a/disk/Makefile b/disk/Makefile index f19d18d89..39677f1e2 100644 --- a/disk/Makefile +++ b/disk/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,28 +25,20 @@ include $(TOPDIR)/config.mk #CFLAGS += -DET_DEBUG -DDEBUG -LIB = $(obj)libdisk.a +LIB = libdisk.a -COBJS-y += part.o -COBJS-y += part_mac.o -COBJS-y += part_dos.o -COBJS-y += part_iso.o -COBJS-y += part_amiga.o - -COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +OBJS = part.o part_mac.o part_dos.o part_iso.o part_amiga.o all: $(LIB) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/disk/part.c b/disk/part.c index 5c4bf6b61..2531f1bc2 100644 --- a/disk/part.c +++ b/disk/part.c @@ -24,7 +24,6 @@ #include #include #include -#include #undef PART_DEBUG @@ -34,66 +33,9 @@ #define PRINTF(fmt,args...) #endif -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) ) - -struct block_drvr { - char *name; - block_dev_desc_t* (*get_dev)(int dev); -}; - -static const struct block_drvr block_drvr[] = { -#if defined(CONFIG_CMD_IDE) - { .name = "ide", .get_dev = ide_get_dev, }, -#endif -#if defined(CONFIG_CMD_SATA) - {.name = "sata", .get_dev = sata_get_dev, }, -#endif -#if defined(CONFIG_CMD_SCSI) - { .name = "scsi", .get_dev = scsi_get_dev, }, -#endif -#if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) - { .name = "usb", .get_dev = usb_stor_get_dev, }, -#endif -#if defined(CONFIG_MMC) - { .name = "mmc", .get_dev = mmc_get_dev, }, -#endif -#if defined(CONFIG_SYSTEMACE) - { .name = "ace", .get_dev = systemace_get_dev, }, -#endif - { }, -}; - -DECLARE_GLOBAL_DATA_PTR; - -block_dev_desc_t *get_dev(char* ifname, int dev) -{ - const struct block_drvr *drvr = block_drvr; - block_dev_desc_t* (*reloc_get_dev)(int dev); - - while (drvr->name) { - reloc_get_dev = drvr->get_dev + gd->reloc_off; - if (strncmp(ifname, drvr->name, strlen(drvr->name)) == 0) - return reloc_get_dev(dev); - drvr++; - } - return NULL; -} -#else -block_dev_desc_t *get_dev(char* ifname, int dev) -{ - return NULL; -} -#endif - -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) ) @@ -109,45 +51,38 @@ void dev_print (block_dev_desc_t *dev_desc) lbaint_t lba512; #endif - switch (dev_desc->if_type) { - case IF_TYPE_SCSI: - printf ("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n", - dev_desc->target,dev_desc->lun, - dev_desc->vendor, - dev_desc->product, - dev_desc->revision); - break; - case IF_TYPE_IDE: - case IF_TYPE_SATA: + if (dev_desc->type==DEV_TYPE_UNKNOWN) { + puts ("not available\n"); + return; + } + if (dev_desc->if_type==IF_TYPE_SCSI) { + printf ("(%d:%d) ", dev_desc->target,dev_desc->lun); + } + if (dev_desc->if_type==IF_TYPE_IDE) { printf ("Model: %s Firm: %s Ser#: %s\n", dev_desc->vendor, dev_desc->revision, dev_desc->product); - break; - case IF_TYPE_UNKNOWN: - default: - puts ("not available\n"); - return; + } else { + printf ("Vendor: %s Prod.: %s Rev: %s\n", + dev_desc->vendor, + dev_desc->product, + dev_desc->revision); } puts (" Type: "); if (dev_desc->removable) puts ("Removable "); switch (dev_desc->type & 0x1F) { - case DEV_TYPE_HARDDISK: - puts ("Hard Disk"); - break; - case DEV_TYPE_CDROM: - puts ("CD ROM"); - break; - case DEV_TYPE_OPDISK: - puts ("Optical Device"); - break; - case DEV_TYPE_TAPE: - puts ("Tape"); - break; - default: - printf ("# %02X #", dev_desc->type & 0x1F); - break; + case DEV_TYPE_HARDDISK: puts ("Hard Disk"); + break; + case DEV_TYPE_CDROM: puts ("CD ROM"); + break; + case DEV_TYPE_OPDISK: puts ("Optical Device"); + break; + case DEV_TYPE_TAPE: puts ("Tape"); + break; + default: printf ("# %02X #", dev_desc->type & 0x1F); + break; } puts ("\n"); if ((dev_desc->lba * dev_desc->blksz)>0L) { @@ -186,13 +121,12 @@ void dev_print (block_dev_desc_t *dev_desc) puts (" Capacity: not available\n"); } } -#endif +#endif /* CFG_CMD_IDE || CFG_CMD_SCSI || CFG_CMD_USB || CONFIG_MMC */ -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + (CONFIG_COMMANDS & CFG_CMD_MMC) || \ defined(CONFIG_SYSTEMACE) ) #if defined(CONFIG_MAC_PARTITION) || \ @@ -232,10 +166,9 @@ void init_part (block_dev_desc_t * dev_desc) } -int get_partition_info (block_dev_desc_t *dev_desc, int part - , disk_partition_t *info) +int get_partition_info (block_dev_desc_t *dev_desc, int part, disk_partition_t *info) { - switch (dev_desc->part_type) { + switch (dev_desc->part_type) { #ifdef CONFIG_MAC_PARTITION case PART_TYPE_MAC: if (get_partition_info_mac(dev_desc,part,info) == 0) { @@ -282,27 +215,18 @@ static void print_part_header (const char *type, block_dev_desc_t * dev_desc) { puts ("\nPartition Map for "); switch (dev_desc->if_type) { - case IF_TYPE_IDE: - puts ("IDE"); - break; - case IF_TYPE_SATA: - puts ("SATA"); - break; - case IF_TYPE_SCSI: - puts ("SCSI"); - break; - case IF_TYPE_ATAPI: - puts ("ATAPI"); - break; - case IF_TYPE_USB: - puts ("USB"); - break; - case IF_TYPE_DOC: - puts ("DOC"); - break; - default: - puts ("UNKNOWN"); - break; + case IF_TYPE_IDE: puts ("IDE"); + break; + case IF_TYPE_SCSI: puts ("SCSI"); + break; + case IF_TYPE_ATAPI: puts ("ATAPI"); + break; + case IF_TYPE_USB: puts ("USB"); + break; + case IF_TYPE_DOC: puts ("DOC"); + break; + default: puts ("UNKNOWN"); + break; } printf (" device %d -- Partition Type: %s\n\n", dev_desc->dev, type); @@ -348,8 +272,7 @@ void print_part (block_dev_desc_t * dev_desc) #else /* neither MAC nor DOS nor ISO partition configured */ -# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION -# error nor CONFIG_ISO_PARTITION configured! +# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION nor CONFIG_ISO_PARTITION configured! #endif -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) || CONFIG_COMMANDS & CFG_CMD_SCSI) */ diff --git a/disk/part_amiga.c b/disk/part_amiga.c index 6c3d74897..41e68fcf0 100644 --- a/disk/part_amiga.c +++ b/disk/part_amiga.c @@ -26,9 +26,9 @@ #include #include "part_amiga.h" -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_AMIGA_PARTITION) diff --git a/disk/part_dos.c b/disk/part_dos.c index 4d778ec5b..c02abef54 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -35,10 +35,10 @@ #include #include "part_dos.h" -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + (CONFIG_COMMANDS & CFG_CMD_MMC) || \ defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_DOS_PARTITION) @@ -195,7 +195,6 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part info->size = le32_to_int (pt->size4); switch(dev_desc->if_type) { case IF_TYPE_IDE: - case IF_TYPE_SATA: case IF_TYPE_ATAPI: sprintf ((char *)info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num); break; @@ -250,4 +249,4 @@ int get_partition_info_dos (block_dev_desc_t *dev_desc, int part, disk_partition } -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) && CONFIG_DOS_PARTITION */ diff --git a/disk/part_iso.c b/disk/part_iso.c index 72ff8689d..073532436 100644 --- a/disk/part_iso.c +++ b/disk/part_iso.c @@ -25,10 +25,9 @@ #include #include "part_iso.h" -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_USB) || \ +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_ISO_PARTITION) @@ -81,7 +80,7 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_ /* the first sector (sector 0x10) must be a primary volume desc */ blkaddr=PVD_OFFSET; if (dev_desc->block_read (dev_desc->dev, PVD_OFFSET, 1, (ulong *) tmpbuf) != 1) - return (-1); + return (-1); if(ppr->desctype!=0x01) { if(verb) printf ("** First descriptor is NOT a primary desc on %d:%d **\n", @@ -103,7 +102,7 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_ for(i=blkaddr;iblock_read (dev_desc->dev, i, 1, (ulong *) tmpbuf) != 1) - return (-1); + return (-1); if(ppr->desctype==0x00) break; /* boot entry found */ if(ppr->desctype==0xff) { @@ -113,7 +112,7 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_ return (-1); } } - /* boot entry found */ + /* boot entry found */ if(strncmp(pbr->ident_str,"EL TORITO SPECIFICATION",23)!=0) { if(verb) printf ("** Wrong El Torito ident: %s on %d:%d **\n", @@ -158,7 +157,6 @@ int get_partition_info_iso_verb(block_dev_desc_t * dev_desc, int part_num, disk_ sprintf ((char *)info->type, "U-Boot"); switch(dev_desc->if_type) { case IF_TYPE_IDE: - case IF_TYPE_SATA: case IF_TYPE_ATAPI: sprintf ((char *)info->name, "hd%c%d\n", 'a' + dev_desc->dev, part_num); break; @@ -259,4 +257,4 @@ int test_part_iso (block_dev_desc_t *dev_desc) return(get_partition_info_iso_verb(dev_desc,0,&info,0)); } -#endif +#endif /* ((CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI)) && defined(CONFIG_ISO_PARTITION) */ diff --git a/disk/part_iso.h b/disk/part_iso.h index c139d4b63..2663578bf 100644 --- a/disk/part_iso.h +++ b/disk/part_iso.h @@ -41,8 +41,8 @@ typedef struct iso_pri_rec { unsigned char desctype; /* type of Volume descriptor: 0 = boot record, 1 = primary, 2 = Supplement, 3 = volume part 0xff trminator */ unsigned char stand_ident[5]; /* "CD001" */ unsigned char vers; /* Version */ - unsigned char unused; - char sysid[32]; /* system Identifier */ + unsigned char unused; + char sysid[32]; /* system Identifier */ char volid[32]; /* volume Identifier */ unsigned char zeros1[8]; /* unused */ unsigned long volsiz_LE; /* volume size Little Endian */ @@ -57,69 +57,69 @@ typedef struct iso_pri_rec { unsigned long pathtablen_LE;/* Path Table size LE */ unsigned long pathtablen_BE;/* Path Table size BE */ unsigned long firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */ - unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */ - unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */ - unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */ - unsigned char rootdir[34]; /* directory record for root dir */ - char volsetid[128];/* Volume set identifier */ - char pubid[128]; /* Publisher identifier */ - char dataprepid[128]; /* data preparer identifier */ - char appid[128]; /* application identifier */ - char copyr[37]; /* copyright string */ - char abstractfileid[37]; /* abstract file identifier */ - char bibliofileid[37]; /* bibliographic file identifier */ - unsigned char creationdate[17]; /* creation date */ - unsigned char modify[17]; /* modification date */ - unsigned char expire[17]; /* expiring date */ - unsigned char effective[17];/* effective date */ - unsigned char filestruc_ver; /* file structur version */ + unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */ + unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */ + unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */ + unsigned char rootdir[34]; /* directory record for root dir */ + char volsetid[128];/* Volume set identifier */ + char pubid[128]; /* Publisher identifier */ + char dataprepid[128]; /* data preparer identifier */ + char appid[128]; /* application identifier */ + char copyr[37]; /* copyright string */ + char abstractfileid[37]; /* abstract file identifier */ + char bibliofileid[37]; /* bibliographic file identifier */ + unsigned char creationdate[17]; /* creation date */ + unsigned char modify[17]; /* modification date */ + unsigned char expire[17]; /* expiring date */ + unsigned char effective[17];/* effective date */ + unsigned char filestruc_ver; /* file structur version */ } iso_pri_rec_t; typedef struct iso_sup_rec { unsigned char desctype; /* type of Volume descriptor: 0 = boot record, 1 = primary, 2 = Supplement, 3 = volume part 0xff trminator */ unsigned char stand_ident[5]; /* "CD001" */ unsigned char vers; /* Version */ - unsigned char volumeflags; /* if bit 0 = 0 => all escape sequences are according ISO 2375 */ - char sysid[32]; /* system Identifier */ + unsigned char volumeflags; /* if bit 0 = 0 => all escape sequences are according ISO 2375 */ + char sysid[32]; /* system Identifier */ char volid[32]; /* volume Identifier */ unsigned char zeros1[8]; /* unused */ - unsigned long volsiz_LE; /* volume size Little Endian */ - unsigned long volsiz_BE; /* volume size Big Endian */ - unsigned char escapeseq[32];/* Escape sequences */ + unsigned long volsiz_LE; /* volume size Little Endian */ + unsigned long volsiz_BE; /* volume size Big Endian */ + unsigned char escapeseq[32];/* Escape sequences */ unsigned short setsize_LE; /* volume set size LE */ - unsigned short setsize_BE; /* volume set size BE */ - unsigned short seqnum_LE; /* volume sequence number LE */ - unsigned short seqnum_BE; /* volume sequence number BE */ - unsigned short secsize_LE; /* sector size LE */ - unsigned short secsize_BE; /* sector size BE */ + unsigned short setsize_BE; /* volume set size BE */ + unsigned short seqnum_LE; /* volume sequence number LE */ + unsigned short seqnum_BE; /* volume sequence number BE */ + unsigned short secsize_LE; /* sector size LE */ + unsigned short secsize_BE; /* sector size BE */ unsigned long pathtablen_LE;/* Path Table size LE */ unsigned long pathtablen_BE;/* Path Table size BE */ unsigned long firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */ - unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */ - unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */ - unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */ - unsigned char rootdir[34]; /* directory record for root dir */ - char volsetid[128];/* Volume set identifier */ - char pubid[128]; /* Publisher identifier */ - char dataprepid[128]; /* data preparer identifier */ - char appid[128]; /* application identifier */ - char copyr[37]; /* copyright string */ - char abstractfileid[37]; /* abstract file identifier */ - char bibliofileid[37]; /* bibliographic file identifier */ - unsigned char creationdate[17]; /* creation date */ - unsigned char modify[17]; /* modification date */ - unsigned char expire[17]; /* expiring date */ - unsigned char effective[17];/* effective date */ - unsigned char filestruc_ver; /* file structur version */ + unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */ + unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */ + unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */ + unsigned char rootdir[34]; /* directory record for root dir */ + char volsetid[128];/* Volume set identifier */ + char pubid[128]; /* Publisher identifier */ + char dataprepid[128]; /* data preparer identifier */ + char appid[128]; /* application identifier */ + char copyr[37]; /* copyright string */ + char abstractfileid[37]; /* abstract file identifier */ + char bibliofileid[37]; /* bibliographic file identifier */ + unsigned char creationdate[17]; /* creation date */ + unsigned char modify[17]; /* modification date */ + unsigned char expire[17]; /* expiring date */ + unsigned char effective[17];/* effective date */ + unsigned char filestruc_ver; /* file structur version */ }iso_sup_rec_t; typedef struct iso_part_rec { unsigned char desctype; /* type of Volume descriptor: 0 = boot record, 1 = primary, 2 = Supplement, 3 = volume part 0xff trminator */ unsigned char stand_ident[5]; /* "CD001" */ unsigned char vers; /* Version */ - unsigned char unused; - char sysid[32]; /* system Identifier */ - char volid[32]; /* volume partition Identifier */ + unsigned char unused; + char sysid[32]; /* system Identifier */ + char volid[32]; /* volume partition Identifier */ unsigned long partloc_LE; /* volume partition location LE */ unsigned long partloc_BE; /* volume partition location BE */ unsigned long partsiz_LE; /* volume partition size LE */ @@ -131,8 +131,8 @@ typedef struct iso_val_entry { unsigned char header_id; /* Header ID must be 0x01 */ unsigned char platform; /* Platform: 0=x86, 1=PowerPC, 2=MAC */ unsigned char res[2]; /* reserved */ - char manu_str[0x18]; /* Ident String of manufacturer/developer */ - unsigned char chk_sum[2]; /* Check sum (all words must be zero) */ + char manu_str[0x18]; /* Ident String of manufacturer/developer */ + unsigned char chk_sum[2]; /* Check sum (all words must be zero) */ unsigned char key[2]; /* key[0]=55, key[1]=0xAA */ } iso_val_entry_t; @@ -140,7 +140,7 @@ typedef struct iso_header_entry { unsigned char header_id; /* Header ID must be 0x90 or 0x91 */ unsigned char platform; /* Platform: 0=x86, 1=PowerPC, 2=MAC */ unsigned char numentry[2]; /* number of entries */ - char id_str[0x1C]; /* Ident String of sectionr */ + char id_str[0x1C]; /* Ident String of sectionr */ } iso_header_entry_t; @@ -148,7 +148,7 @@ typedef struct iso_init_def_entry { unsigned char boot_ind; /* Boot indicator 0x88=bootable 0=not bootable */ unsigned char boot_media; /* boot Media Type: 0=no Emulation, 1=1.2MB floppy, 2=1.44MB floppy, 3=2.88MB floppy 4=hd (0x80) */ unsigned char ld_seg[2]; /* Load segment (flat model=addr/10) */ - unsigned char systype; /* System Type copy of byte5 of part table */ + unsigned char systype; /* System Type copy of byte5 of part table */ unsigned char res; /* reserved */ unsigned char sec_cnt[2]; /* sector count in VIRTUAL Blocks (0x200) */ unsigned char rel_block_addr[4]; /* relative Block address */ diff --git a/disk/part_mac.c b/disk/part_mac.c index 1922fe53a..8c23e211f 100644 --- a/disk/part_mac.c +++ b/disk/part_mac.c @@ -34,10 +34,9 @@ #include #include "part_mac.h" -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_SATA) || \ - defined(CONFIG_CMD_USB) || \ +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) ) && defined(CONFIG_MAC_PARTITION) @@ -252,4 +251,4 @@ int get_partition_info_mac (block_dev_desc_t *dev_desc, int part, disk_partition return (0); } -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) && CONFIG_MAC_PARTITION */ diff --git a/doc/README-i386 b/doc/README-i386 index c560d22f4..02b753cbd 100644 --- a/doc/README-i386 +++ b/doc/README-i386 @@ -57,9 +57,9 @@ Daniel Engstr --- linux-2.4.19-orig/init/do_mounts.c Sat Aug 3 02:39:46 2002 +++ linux-2.4.19/init/do_mounts.c Mon Sep 23 16:21:33 2002 @@ -224,6 +224,14 @@ - { "ftlc", 0x2c10 }, - { "ftld", 0x2c18 }, - { "mtdblock", 0x1f00 }, + { "ftlc", 0x2c10 }, + { "ftld", 0x2c18 }, + { "mtdblock", 0x1f00 }, + { "mtdblock0", 0x1f00 }, + { "mtdblock1", 0x1f01 }, + { "mtdblock2", 0x1f02 }, @@ -68,7 +68,7 @@ Daniel Engstr + { "mtdblock5", 0x1f05 }, + { "mtdblock6", 0x1f06 }, + { "mtdblock7", 0x1f07 }, - { NULL, 0 } + { NULL, 0 } }; ------------------- diff --git a/doc/README-integrator b/doc/README-integrator index 4daf3413a..ce8a9d26a 100644 --- a/doc/README-integrator +++ b/doc/README-integrator @@ -86,12 +86,12 @@ using the generic "arm_intcm" core: ap966_config Integrator Core Module for ARM966E-S TM ap922_config Integrator Core Module for ARM922T TM with ETM ap922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur -ap7_config ** CM7TDMI +ap7_config ** CM7TDMI integratorap_config ap_config -cp966_config Integrator Core Module for ARM966E-S TM +cp966_config Integrator Core Module for ARM966E-S TM cp922_config Integrator Core Module for ARM922T TM with ETM cp922_XA10_config Integrator Core Module for ARM922T using Altera Excalibur cp1026_config Integrator Core Module ARM1026EJ-S TM diff --git a/doc/README.JFFS2 b/doc/README.JFFS2 index c5d67fd4e..270da9082 100644 --- a/doc/README.JFFS2 +++ b/doc/README.JFFS2 @@ -2,7 +2,7 @@ JFFS2 options and usage. ----------------------- JFFS2 in U-Boot is a read only implementation of the file system in -Linux with the same name. To use JFFS2 define CONFIG_CMD_JFFS2. +Linux with the same name. To use JFFS2 define CFG_CMD_JFFS2. The module adds three new commands. fsload - load binary file from a file system image diff --git a/doc/README.NetConsole b/doc/README.NetConsole index fea8e3364..cc35a0a8f 100644 --- a/doc/README.NetConsole +++ b/doc/README.NetConsole @@ -38,11 +38,6 @@ The script expects exactly one argument, which is interpreted as the target IP address (or host name, assuming DNS is working). The script can be interrupted by pressing ^T (CTRL-T). -Be aware that in some distributives (Fedora Core 5 at least) -usage of nc has been changed and -l and -p options are considered -as mutually exclusive. If nc complains about options provided, -you can just remove the -p option from the script. - It turns out that 'netcat' cannot be used to listen to broadcast packets. We developed our own tool 'ncb' (see tools directory) that listens to broadcast packets on a given port and dumps them to the diff --git a/doc/README.PIP405 b/doc/README.PIP405 index 610ff2161..c5ccf1875 100644 --- a/doc/README.PIP405 +++ b/doc/README.PIP405 @@ -32,8 +32,10 @@ Changed files: - include/cmd_bsp.h added PIP405 commands definitions - include/cmd_condefs.h added Floppy and SCSI support - include/cmd_disk.h changed to work with block device description -- include/config_LANTEC.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI -- include/config_hymod.h excluded CONFIG_CMD_FDC and CONFIG_CMD_SCSI +- include/config_LANTEC.h excluded CFG_CMD_FDC and CFG_CMD_SCSI from + CONFIG_CMD_FULL +- include/config_hymod.h excluded CFG_CMD_FDC and CFG_CMD_SCSI from + CONFIG_CMD_FULL - include/flash.h added INTEL_ID_28F320C3T 0x88C488C4 - include/i2c.h added "defined(CONFIG_PIP405)" - include/image.h added IH_OS_U_BOOT, IH_TYPE_FIRMWARE @@ -86,8 +88,8 @@ section "Changes". New Commands: ------------- -CONFIG_CMD_SCSI SCSI Support -CONFIG_CMF_FDC Floppy disk support +CFG_CMD_SCSI SCSI Support +CFG_CMF_FDC Floppy disk support IDE additions: -------------- @@ -170,8 +172,8 @@ Added Devices: Floppy support: --------------- Support of a standard floppy disk controller at address CFG_ISA_IO_BASE_ADDRESS -+ 0x3F0. Enabled with define CONFIG_CMD_FDC. Reads a unformated floppy disk -with a image header (see: mkimage). No interrupts and no DMA are used for this. ++ 0x3F0. Enabled with define CFG_CMD_FDC. Reads a unformated floppy disk with a +image header (see: mkimage). No interrupts and no DMA are used for this. Added files: - common/cmd_fdc.c - include/cmd_fdc.h diff --git a/doc/README.RPXlite b/doc/README.RPXlite index c0238ae21..c8ccc41eb 100644 --- a/doc/README.RPXlite +++ b/doc/README.RPXlite @@ -451,7 +451,7 @@ reg_config.txt: PS = 00 PARE = 0 WP = 0 - MS = 1 /* UPMA */ + MS = 1 /* UPMA */ V = 1 /* Valid */ => 0x0000 0081 @@ -486,7 +486,7 @@ reg_config.txt: PS = 00 PARE = 0 WP = 0 - MS = 0 /* GPCM */ + MS = 0 /* GPCM */ V = 1 /* Valid */ => 0xFA40 0001 @@ -513,7 +513,7 @@ reg_config.txt: PS = 01 PARE = 0 WP = 0 - MS = 0 /* GPCM */ + MS = 0 /* GPCM */ V = 1 /* Valid */ => 0xFA00 0401 diff --git a/doc/README.SNTP b/doc/README.SNTP index 9edc957c6..fd6f2098f 100644 --- a/doc/README.SNTP +++ b/doc/README.SNTP @@ -1,5 +1,5 @@ -To use SNTP support, add define CONFIG_CMD_SNTP to the -configuration file of the board. +To use SNTP support, add a define CFG_CMD_SNTP to CONFIG_COMMANDS in +the configuration file of the board. The "sntp" command gets network time from NTP time server and syncronize RTC of the board. This command needs the command line diff --git a/doc/README.adnpesc1 b/doc/README.adnpesc1 index 5257f18b4..ded53210b 100644 --- a/doc/README.adnpesc1 +++ b/doc/README.adnpesc1 @@ -184,7 +184,7 @@ you have to check-up the next environment variables: - default is '0' (zero) NOTE: You should avoid to save this variable with non zero - value to Flash. Otherwise it would be allow any + value to Flash. Otherwise it would be allow any update process at any time! 2. appl_entry_addr diff --git a/doc/README.adnpesc1_base32 b/doc/README.adnpesc1_base32 index 145e8cdad..657604458 100644 --- a/doc/README.adnpesc1_base32 +++ b/doc/README.adnpesc1_base32 @@ -192,7 +192,7 @@ IDE: (TODO) : gap : | | 0x00010020 ---32-----------16|15------------0- - | | \ + | | \ | register bank | | | size = (real_size << 1) | | | real_size = 0x10 | | @@ -308,7 +308,7 @@ IDE: (TODO) + 0x18 |- - - - - - - - - - - - - - - -| | | slaveselect (1 bit) (rw) | | + 0x14 |- - - - - - - - - - - - - - - -| | - SPI0 | (reserved) | | + SPI0 | (reserved) | | [4] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 | control (11 bit) (rw) | | + 0x0c |- - - - - - - - - - - - - - - -| | diff --git a/doc/README.autoboot b/doc/README.autoboot index 2042fe5c4..e4c418673 100644 --- a/doc/README.autoboot +++ b/doc/README.autoboot @@ -114,17 +114,10 @@ What they do CONFIG_AUTOBOOT_PROMPT is displayed before the boot delay selected by CONFIG_BOOTDELAY starts. If it is not defined there is no output indicating that autoboot is in progress. - - Note that CONFIG_AUTOBOOT_PROMPT is used as the (only) - argument to a printf() call, so it may contain '%' format - specifications, provided that it also includes, sepearated by - commas exactly like in a printf statement, the required - arguments. It is the responsibility of the user to select only - such arguments that are valid in the given context. A - reasonable prompt could be defined as - - #define CONFIG_AUTOBOOT_PROMPT \ - "autoboot in %d seconds\n",bootdelay + If "%d" is included, it is replaced by the number of seconds + remaining before autoboot will start, but it does not count + down the seconds. "autoboot in %d seconds\n" is a reasonable + prompt. If CONFIG_AUTOBOOT_DELAY_STR or "bootdelaykey" is specified and this string is received from console input before diff --git a/doc/README.bamboo b/doc/README.bamboo index e139c6d12..b50be01ab 100644 --- a/doc/README.bamboo +++ b/doc/README.bamboo @@ -1,65 +1,3 @@ -The 2 important dipswitches are configured as shown below: - -SW1 (for 33MHz SysClk) ----------------------- -S1 S2 S3 S4 S5 S6 S7 S8 -OFF OFF OFF OFF OFF OFF OFF ON - -SW7 (for Op-Code Flash and Boot Option H) ------------------------------------------ -S1 S2 S3 S4 S5 S6 S7 S8 -OFF OFF OFF ON OFF OFF OFF OFF - -The EEPROM at location 0x52 is loaded with these 16 bytes: -C47042A6 05D7A190 40082350 0d050000 - -SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors -SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB -SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output -SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz -SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor -SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A -SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B -SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B -SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor -SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor -SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0 -SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0 -SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0 -SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer -SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit -SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC -SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled -SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled -SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100 -SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled -SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1 -SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled -SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC -SDR0_SDSTP0[NE]: 0 : NDFC: disabled -SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit -SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection -SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size) -SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled -SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready -SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter -SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC -SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC -SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC -SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC -SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count - -PPC440EP Clocking Configuration - -SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz -OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz - -The above information is reported by Eugene O'Brien -. Thanks a lot. - -2007-08-06, Stefan Roese ---------------------------------------------------------------------- - The configuration for the AMCC 440EP eval board "Bamboo" was changed to only use 384 kbytes of FLASH for the U-Boot image. This way the redundant environment can be saved in the remaining 2 sectors of the diff --git a/doc/README.bedbug b/doc/README.bedbug index 2616acc65..9cfb4217f 100644 --- a/doc/README.bedbug +++ b/doc/README.bedbug @@ -31,6 +31,12 @@ can be easily implemented. if it is an illegal instruction, privileged instruction or a trap. Also added debug trap handler. +./include/cmd_confdefs.h + Added definition of CFG_CMD_BEDBUG. + +./include/config_WALNUT405.h + Added CFG_CMD_BEDBUG to the CONFIG_COMMANDS for the WALNUT. + ./include/ppc_asm.tmpl Added code to handle critical exceptions @@ -72,6 +78,10 @@ Changes: cpu/mpc8xx/traps.c Added new routine DebugException() + include/config_MBX.h + Added CFG_CMD_BEDBUG to CONFIG_COMMANDS define + + New Files: cpu/mpc8xx/bedbug_860.c diff --git a/doc/README.console b/doc/README.console index 25c4f1d7d..6d477df75 100644 --- a/doc/README.console +++ b/doc/README.console @@ -97,8 +97,8 @@ SUPPORTED DRIVERS Working drivers: - serial (architecture dependent serial stuff) - video (mpc8xx video controller) + serial (architecture dependent serial stuff) + video (mpc8xx video controller) Work in progress: @@ -114,5 +114,5 @@ TESTED CONFIGURATIONS The driver has been tested with the following configurations (see CREDITS for other contact informations): -- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it +- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it - GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it diff --git a/doc/README.fastboot b/doc/README.fastboot new file mode 100644 index 000000000..a71badbd9 --- /dev/null +++ b/doc/README.fastboot @@ -0,0 +1,205 @@ +This is the document that descibes fastboot. + +Fastboot is a USB bootloader protocol that Android uses instead of traditional +serial. + +The files of interest are + +include/fastboot.h : Defines the interface between fastboot_cmd and + board specific support. +common/cmd_fastboot.c : The board independent command that implements the + high level protocol. + +Put your low level board specific file either +board//fastboot.c +or +cpu//fastboot.c + +Examples of implementation + +include/configs/omap3430labrador.h : Sets config variable CONFIG_FASTBOOT +cpu/omap3/fastboot.c : Low level support for omap3 family of + cpu's. + +The offical specification for the protocal can be found in the Android +repository. + +bootable/bootloader/legacy/fastboot_protocol.txt + +Included below is a copy of the file used. + +-------------------------------------------------------------------------------- + + +FastBoot Version 0.4 +---------------------- + +The fastboot protocol is a mechanism for communicating with bootloaders +over USB. It is designed to be very straightforward to implement, to +allow it to be used across a wide range of devices and from hosts running +Linux, Windows, or OSX. + + +Basic Requirements +------------------ + +* Two bulk endpoints (in, out) are required +* Max packet size must be 64 bytes for full-speed and 512 bytes for + high-speed USB +* The protocol is entirely host-driven and synchronous (unlike the + multi-channel, bi-directional, asynchronous ADB protocol) + + +Transport and Framing +--------------------- + +1. Host sends a command, which is an ascii string in a single + packet no greater than 64 bytes. + +2. Client response with a single packet no greater than 64 bytes. + The first four bytes of the response are "OKAY", "FAIL", "DATA", + or "INFO". Additional bytes may contain an (ascii) informative + message. + + a. INFO -> the remaining 60 bytes are an informative message + (providing progress or diagnostic messages). They should + be displayed and then step #2 repeats + + b. FAIL -> the requested command failed. The remaining 60 bytes + of the response (if present) provide a textual failure message + to present to the user. Stop. + + c. OKAY -> the requested command completed successfully. Go to #5 + + d. DATA -> the requested command is ready for the data phase. + A DATA response packet will be 12 bytes long, in the form of + DATA00000000 where the 8 digit hexidecimal number represents + the total data size to transfer. + +3. Data phase. Depending on the command, the host or client will + send the indicated amount of data. Short packets are always + acceptable and zero-length packets are ignored. This phase continues + until the client has sent or received the number of bytes indicated + in the "DATA" response above. + +4. Client responds with a single packet no greater than 64 bytes. + The first four bytes of the response are "OKAY", "FAIL", or "INFO". + Similar to #2: + + a. INFO -> display the remaining 60 bytes and return to #4 + + b. FAIL -> display the remaining 60 bytes (if present) as a failure + reason and consider the command failed. Stop. + + c. OKAY -> success. Go to #5 + +5. Success. Stop. + + +Example Session +--------------- + +Host: "getvar:version" request version variable + +Client: "OKAY0.4" return version "0.4" + +Host: "getvar:nonexistant" request some undefined variable + +Client: "OKAY" return value "" + +Host: "download:00001234" request to send 0x1234 bytes of data + +Client: "DATA00001234" ready to accept data + +Host: < 0x1234 bytes > send data + +Client: "OKAY" success + +Host: "flash:bootloader" request to flash the data to the bootloader + +Client: "INFOerasing flash" indicate status / progress + "INFOwriting flash" + "OKAY" indicate success + +Host: "powerdown" send a command + +Client: "FAILunknown command" indicate failure + + +Command Reference +----------------- + +* Command parameters are indicated by printf-style escape sequences. + +* Commands are ascii strings and sent without the quotes (which are + for illustration only here) and without a trailing 0 byte. + +* Commands that begin with a lowercase letter are reserved for this + specification. OEM-specific commands should not begin with a + lowercase letter, to prevent incompatibilities with future specs. + + "getvar:%s" Read a config/version variable from the bootloader. + The variable contents will be returned after the + OKAY response. + + "download:%08x" Write data to memory which will be later used + by "boot", "ramdisk", "flash", etc. The client + will reply with "DATA%08x" if it has enough + space in RAM or "FAIL" if not. The size of + the download is remembered. + + "verify:%08x" Send a digital signature to verify the downloaded + data. Required if the bootloader is "secure" + otherwise "flash" and "boot" will be ignored. + + "flash:%s" Write the previously downloaded image to the + named partition (if possible). + + "erase:%s" Erase the indicated partition (clear to 0xFFs) + + "boot" The previously downloaded data is a boot.img + and should be booted according to the normal + procedure for a boot.img + + "continue" Continue booting as normal (if possible) + + "reboot" Reboot the device. + + "reboot-bootloader" Reboot back into the bootloader. + Useful for upgrade processes that require upgrading + the bootloader and then upgrading other partitions + using the new bootloader. + + "powerdown" Power off the device. + + + +Client Variables +---------------- + +The "getvar:%s" command is used to read client variables which +represent various information about the device and the software +on it. + +The various currently defined names are: + + version Version of FastBoot protocol supported. + It should be "0.3" for this document. + + version-bootloader Version string for the Bootloader. + + version-baseband Version string of the Baseband Software + + product Name of the product + + serialno Product serial number + + secure If the value is "yes", this is a secure + bootloader requiring a signature before + it will install or boot images. + +Names starting with a lowercase character are reserved by this +specification. OEM-specific names should not start with lowercase +characters. + + diff --git a/doc/README.m68k b/doc/README.m68k index 0c533f3fa..6dea2b567 100644 --- a/doc/README.m68k +++ b/doc/README.m68k @@ -4,9 +4,9 @@ U-Boot for Motorola M68K ==================================================================== History -August 08,2005; Jens Scharsig +August 08,2005; Jens Scharsig MCF5282 implementation without preloader -January 12, 2004; +January 12, 2004; ==================================================================== This file contains status information for the port of U-Boot to the @@ -82,8 +82,8 @@ Board specific code is located in: board/bus/EB+MCF-EV123 To configure the board, type: -make EB+MCF-EV123_config for external FLASH -make EB+MCF-EV123_internal_config for internal FLASH +make EB+MCF-EV123_config for external FLASH +make EB+MCF-EV123_internal_config for internal FLASH 4. CONFIGURATION OPTIONS/SETTINGS @@ -149,7 +149,7 @@ CFG_RFD -- defines the PLL Reduce Frecuency Devider CFG_CSx_BASE -- defines the base address of chip select x CFG_CSx_SIZE -- defines the memory size (address range) of chip select x CFG_CSx_WIDTH -- defines the bus with of chip select x -CFG_CSx_RO -- if set to 0 chip select x is read/wirte +CFG_CSx_RO -- if set to 0 chip select x is read/wirte else chipselct is read only CFG_CSx_WS -- defines the number of wait states of chip select x diff --git a/doc/README.modnet50 b/doc/README.modnet50 index f7bb254e1..30338ce8c 100644 --- a/doc/README.modnet50 +++ b/doc/README.modnet50 @@ -51,8 +51,8 @@ board/modnet50/lowlevel_init.S .. memory setup for ModNET50 board/modnet50/flash.c .. flash routines board/modnet50/modnet50.c .. some board init stuff -drivers/net/netarm_eth.c .. ethernet driver for the NET+50 CPU -drivers/net/netarm_eth.h .. header for ethernet driver +drivers/netarm_eth.c .. ethernet driver for the NET+50 CPU +drivers/netarm_eth.h .. header for ethernet driver include/configs/modnet50.h .. configuration file for ModNET50 diff --git a/doc/README.mpc8349emds.ddrecc b/doc/README.mpc8349emds.ddrecc new file mode 100644 index 000000000..eb249c395 --- /dev/null +++ b/doc/README.mpc8349emds.ddrecc @@ -0,0 +1,154 @@ +Overview +======== + +The overall usage pattern for ECC diagnostic commands is the following: + + * (injecting errors is initially disabled) + + * define inject mask (which tells the DDR controller what type of errors + we'll be injecting: single/multiple bit etc.) + + * enable injecting errors - from now on the controller injects errors as + indicated in the inject mask + +IMPORTANT NOTICE: enabling injecting multiple-bit errors is potentially +dangerous as such errors are NOT corrected by the controller. Therefore caution +should be taken when enabling the injection of multiple-bit errors: it is only +safe when used on a carefully selected memory area and used under control of +the 'ecc test' command (see example 'Injecting Multiple-Bit Errors' below). In +particular, when you simply set the multiple-bit errors in inject mask and +enable injection, U-Boot is very likely to hang quickly as the errors will be +injected when it accesses its code, data etc. + + +Use cases for DDR 'ecc' command: +================================ + +Before executing particular tests reset target board or clear status registers: + +=> ecc captureclear +=> ecc errdetectclr all +=> ecc sbecnt 0 + + +Injecting Single-Bit Errors +--------------------------- + +1. Set 1 bit in Data Path Error Inject Mask + +=> ecc injectdatahi 1 + +2. Run test over some memory region + +=> ecc test 200000 10 + +3. Check ECC status + +=> ecc status +... +Memory Data Path Error Injection Mask High/Low: 00000001 00000000 +... +Memory Single-Bit Error Management (0..255): + Single-Bit Error Threshold: 255 + Single Bit Error Counter: 16 +... +Memory Error Detect: + Multiple Memory Errors: 0 + Multiple-Bit Error: 0 + Single-Bit Error: 0 +... + +16 errors were generated, Single-Bit Error flag was not set as Single Bit Error +Counter did not reach Single-Bit Error Threshold. + +4. Make sure used memory region got re-initialized with 0xcafecafe pattern + +=> md 200000 +00200000: cafecafe cafecafe cafecafe cafecafe ................ +00200010: cafecafe cafecafe cafecafe cafecafe ................ +00200020: cafecafe cafecafe cafecafe cafecafe ................ +00200030: cafecafe cafecafe cafecafe cafecafe ................ +00200040: cafecafe cafecafe cafecafe cafecafe ................ +00200050: cafecafe cafecafe cafecafe cafecafe ................ +00200060: cafecafe cafecafe cafecafe cafecafe ................ +00200070: cafecafe cafecafe cafecafe cafecafe ................ +00200080: deadbeef deadbeef deadbeef deadbeef ................ +00200090: deadbeef deadbeef deadbeef deadbeef ................ + + +Injecting Multiple-Bit Errors +----------------------------- + +1. Set more than 1 bit in Data Path Error Inject Mask + +=> ecc injectdatahi 5 + +2. Run test over some memory region + +=> ecc test 200000 10 + +3. Check ECC status + +=> ecc status +... +Memory Data Path Error Injection Mask High/Low: 00000005 00000000 +... +Memory Error Detect: + Multiple Memory Errors: 1 + Multiple-Bit Error: 1 + Single-Bit Error: 0 +... + +Observe that both Multiple Memory Errors and Multiple-Bit Error flags are set. + +4. Make sure used memory region got re-initialized with 0xcafecafe pattern + +=> md 200000 +00200000: cafecafe cafecafe cafecafe cafecafe ................ +00200010: cafecafe cafecafe cafecafe cafecafe ................ +00200020: cafecafe cafecafe cafecafe cafecafe ................ +00200030: cafecafe cafecafe cafecafe cafecafe ................ +00200040: cafecafe cafecafe cafecafe cafecafe ................ +00200050: cafecafe cafecafe cafecafe cafecafe ................ +00200060: cafecafe cafecafe cafecafe cafecafe ................ +00200070: cafecafe cafecafe cafecafe cafecafe ................ +00200080: deadbeef deadbeef deadbeef deadbeef ................ +00200090: deadbeef deadbeef deadbeef deadbeef ................ + + +Test Single-Bit Error Counter and Threshold +------------------------------------------- + +1. Set 1 bit in Data Path Error Inject Mask + +=> ecc injectdatahi 1 + +2. Enable error injection + +=> ecc inject en + +3. Let u-boot run for a with Single-Bit error injection enabled + +4. Disable error injection + +=> ecc inject dis + +4. Check status + +=> ecc status + +... +Memory Single-Bit Error Management (0..255): + Single-Bit Error Threshold: 255 + Single Bit Error Counter: 60 + +Memory Error Detect: + Multiple Memory Errors: 1 + Multiple-Bit Error: 0 + Single-Bit Error: 1 +... + +Observe that Single-Bit Error is 'on' which means that Single-Bit Error Counter +reached Single-Bit Error Threshold. Multiple Memory Errors bit is also 'on', that +is Counter reached Threshold more than one time (it wraps back after reaching +Threshold). diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index ae8202bdd..f0cf782a8 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -100,9 +100,6 @@ Updated 13-July-2004 Jon Loeliger SW7[1:4] = 0101 = 5 => 5 x 66 = 330 CCB Sysclk SW7[5:6] = 01 => 5:2 x 330 = 825 Core clock - In order to use PCI-X (only in the first PCI slot. The one with - the RIO connector), you need to set SW1[4] (config) to 1 (off). - Also, configure the board to run PCI at 66 MHz. 2. MEMORY MAP TO WORK WITH LINUX KERNEL diff --git a/doc/README.nand b/doc/README.nand index 647a6b8e6..f2d6a5b1e 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -1,7 +1,9 @@ NAND FLASH commands and notes + See NOTE below!!! + # (C) Copyright 2003 # Dave Ellis, SIXNET, dge@sixnetio.com # @@ -34,19 +36,14 @@ Commands: nand device num Make device `num' the current device and print information about it. - nand erase off|partition size - nand erase clean [off|partition size] - Erase `size' bytes starting at offset `off'. Alternatively partition - name can be specified, in this case size will be eventually limited - to not exceed partition size (this behaviour applies also to read - and write commands). Only complete erase blocks can be erased. - - If `erase' is specified without an offset or size, the entire flash - is erased. If `erase' is specified with partition but without an - size, the entire partition is erased. + nand erase off size + nand erase clean [off size] + Erase `size' bytes starting at offset `off'. Only complete erase + blocks can be erased. If `clean' is specified, a JFFS2-style clean marker is written to - each block after it is erased. + each block after it is erased. If `clean' is specified without an + offset or size, the entire flash is erased. This command will not erase blocks that are marked bad. There is a debug option in cmd_nand.c to allow bad blocks to be erased. @@ -56,36 +53,36 @@ Commands: nand info Print information about all of the NAND devices found. - nand read addr ofs|partition size + nand read addr ofs size Read `size' bytes from `ofs' in NAND flash to `addr'. If a page cannot be read because it is marked bad or an uncorrectable data error is found the command stops with an error. - nand read.jffs2 addr ofs|partition size + nand read.jffs2 addr ofs size Like `read', but the data for blocks that are marked bad is read as 0xff. This gives a readable JFFS2 image that can be processed by the JFFS2 commands such as ls and fsload. - nand read.oob addr ofs|partition size + nand read.oob addr ofs size Read `size' bytes from the out-of-band data area corresponding to `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of data for one 512-byte page or 2 256-byte pages. There is no check for bad blocks or ECC errors. - nand write addr ofs|partition size + nand write addr ofs size Write `size' bytes from `addr' to `ofs' in NAND flash. If a page cannot be written because it is marked bad or the write fails the command stops with an error. - nand write.jffs2 addr ofs|partition size + nand write.jffs2 addr ofs size Like `write', but blocks that are marked bad are skipped and the - data is written to the next block instead. This allows writing + is written to the next block instead. This allows writing writing a JFFS2 image, as long as the image is short enough to fit even after skipping the bad blocks. Compact images, such as those produced by mkfs.jffs2 should work well, but loading an image copied from another flash is going to be trouble if there are any bad blocks. - nand write.oob addr ofs|partition size + nand write.oob addr ofs size Write `size' bytes from `addr' to the out-of-band data area corresponding to `ofs' in NAND flash. This is limited to the 16 bytes of data for one 512-byte page or 2 256-byte pages. There is no check @@ -93,8 +90,8 @@ Commands: Configuration Options: - CONFIG_CMD_NAND - Enables NAND support and commmands. + CFG_CMD_NAND + A good one to add to CONFIG_COMMANDS since it enables NAND support. CONFIG_MTD_NAND_ECC_JFFS2 Define this if you want the Error Correction Code information in @@ -192,7 +189,12 @@ The old NAND handling code has been re-factored and is now confined to only board-specific files and - unfortunately - to the DoC code (see below). A new configuration variable has been introduced: CFG_NAND_LEGACY, which has to be defined in the board config file if -that board uses legacy code. +that board uses legacy code. If CFG_NAND_LEGACY is defined, the board +specific config.mk file should also have "BOARDLIBS = +drivers/nand_legacy/libnand_legacy.a". For boards using the new NAND +approach (PPChameleon and netstar at the moment) no variable is +necessary, but the config.mk should have "BOARDLIBS = +drivers/nand/libnand.a". The necessary changes have been made to all affected boards, and no build breakage has been introduced, except for NETTA and NETTA_ISDN @@ -205,46 +207,3 @@ As mentioned above, the legacy code is still used by the DoC subsystem. The consequence of this is that the legacy NAND can't be removed from the tree until the DoC is ported to use the new NAND support (or boards with DoC will break). - - -Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006 - -JFFS2 related commands: - - implement "nand erase clean" and old "nand erase" - using both the new code which is able to skip bad blocks - "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob. - - "nand write.jffs2" - like "nand write" but skip found bad eraseblocks - - "nand read.jffs2" - like "nand read" but skip found bad eraseblocks - -Miscellaneous and testing commands: - "markbad [offset]" - create an artificial bad block (for testing bad block handling) - - "scrub [offset length]" - like "erase" but don't skip bad block. Instead erase them. - DANGEROUS!!! Factory set bad blocks will be lost. Use only - to remove artificial bad blocks created with the "markbad" command. - - -NAND locking command (for chips with active LOCKPRE pin) - - "nand lock" - set NAND chip to lock state (all pages locked) - - "nand lock tight" - set NAND chip to lock tight state (software can't change locking anymore) - - "nand lock status" - displays current locking status of all pages - - "nand unlock [offset] [size]" - unlock consecutive area (can be called multiple times for different areas) - - -I have tested the code with board containing 128MiB NAND large page chips -and 32MiB small page chips. diff --git a/doc/README.ppc440 b/doc/README.ppc440 index 2e04abacc..08f34f589 100644 --- a/doc/README.ppc440 +++ b/doc/README.ppc440 @@ -146,13 +146,12 @@ that maps in a single PCI I/O space and PCI memory space. The I/O space begins at PCI I/O address 0 and the PCI memory space is 256 MB starting at PCI address CFG_PCI_TARGBASE. After the pci_controller structure is initialized, the cpu-specific code will -call the routine pci_pre_init(). This routine is implemented by -board-specific code & is where the board can over-ride/extend the -default pci_controller structure settings and exspecially provide -a routine to map the PCI interrupts and do other pre-initialization -tasks. If pci_pre_init() returns a value of zero, PCI initialization -is aborted; otherwise the controller structure is registered and -initialization continues. +call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is +defined. This routine is implemented by board-specific code & is where +the board can over-ride/extend the default pci_controller structure +settings and do other pre-initialization tasks. If pci_pre_init() +returns a value of zero, PCI initialization is aborted; otherwise the +controller structure is registered and initialization continues. The default 440GP PCI target configuration is minimal -- it assumes that the strapping registers are set as necessary. Since the strapping bits diff --git a/doc/README.sbc8560 b/doc/README.sbc8560 new file mode 100644 index 000000000..52592e3f4 --- /dev/null +++ b/doc/README.sbc8560 @@ -0,0 +1,53 @@ +The port was tested on Wind River System Sbc8560 board . +U-Boot was installed on the flash memory of the CPU card (no the SODIMM). + +NOTE: Please configure uboot compile to the proper PCI frequency and +setup the appropriate DIP switch settings. + +SBC8560 board: + +Make sure boards switches are set to their appropriate conditions. +Refer to the Engineering Reference Guide ERG-00300-002. Of particular +importance are: 1)Tthe settings for JP4 (JP4 1-3 and 2-4), which +select the on-board FLASH device (Intel 28F128Jx); 2) The settings +for the Clock SW9 (33 MHz or 66 MHz). + + Note: SW9 Settings: 66 MHz + 4:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on + Note: SW9 Settings: 33 MHz + 8:1 ratio CCB clocks:SYSCLK + 3:1 ration e500 Core:CCB + pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on + + +Flashing the FLASH device with the "Wind River ICE": + +1) Properly connect and configure the Wind River ICE to the + target JTAG port. This includes running the SBC8560 register script. + Make sure target memory can be read and written. + +2) Build the u-boot image: + make distclean + make SBC8560_66_config or SBC8560_33_config + make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all + + Note: reference is made to the ELDK3.0 compiler but any 85xx cross-compiler + should suffice. + +3) Convert the uboot (.elf) file to a uboot.bin file (using visionClick converter). + The bin file should be converted from fffc0000 to ffffffff + +4) Setup the Flash Utility (tools menu) for: + + Determine the clock speed of the PCI bus and set SW9 accordingly + Note: the speed of the PCI bus defaults to the slowest PCI card + PlayBack the "default" register file for the SBC8560 + Select the uboot.bin file with zero bias + Select the initialize Target prior to programming + Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm + Select the erase base address from FFFC0000 to FFFFFFFF + Select the start address from 0 with size of 4000 + +5) Erase and Program diff --git a/doc/README.standalone b/doc/README.standalone index 81b949a0a..39988317e 100644 --- a/doc/README.standalone +++ b/doc/README.standalone @@ -19,12 +19,11 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications: thus the compiler cannot perform type checks on these assignments. 2. The pointer to the jump table is passed to the application in a - machine-dependent way. PowerPC, ARM, MIPS and Blackfin architectures - use a dedicated register to hold the pointer to the 'global_data' - structure: r2 on PowerPC, r8 on ARM, k0 on MIPS, and P5 on Blackfin. - The x86 architecture does not use such a register; instead, the - pointer to the 'global_data' structure is passed as 'argv[-1]' - pointer. + machine-dependent way. PowerPC, ARM and MIPS architectures use a + dedicated register to hold the pointer to the 'global_data' + structure: r29 on PowerPC, r8 on ARM and k0 on MIPS. The x86 + architecture does not use such a register; instead, the pointer to + the 'global_data' structure is passed as 'argv[-1]' pointer. The application can access the 'global_data' structure in the same way as U-Boot does: @@ -50,12 +49,11 @@ Design Notes on Exporting U-Boot Functions to Standalone Applications: 4. The default load and start addresses of the applications are as follows: - Load address Start address - x86 0x00040000 0x00040000 - PowerPC 0x00040000 0x00040004 - ARM 0x0c100000 0x0c100000 - MIPS 0x80200000 0x80200000 - Blackfin 0x00001000 0x00001000 + Load address Start address + x86 0x00040000 0x00040000 + PowerPC 0x00040000 0x00040004 + ARM 0x0c100000 0x0c100000 + MIPS 0x80200000 0x80200000 For example, the "hello world" application may be loaded and executed on a PowerPC board with the following commands: diff --git a/doc/README.usb b/doc/README.usb index b3bcb91f4..41f76f4b7 100644 --- a/doc/README.usb +++ b/doc/README.usb @@ -73,8 +73,8 @@ Storage USB Commands: Config Switches: ---------------- -CONFIG_CMD_USB enables basic USB support and the usb command -CONFIG_USB_UHCI defines the lowlevel part.A lowlevel part must be defined - if using CONFIG_CMD_USB +CFG_CMD_USB enables basic USB support and the usb command +CONFIG_USB_UHCI defines the lowlevel part.A lowlevel part must be defined if + using CFG_CMD_USB CONFIG_USB_KEYBOARD enables the USB Keyboard CONFIG_USB_STORAGE enables the USB storage devices diff --git a/doc/README.video b/doc/README.video index 34e199c2d..c145d9be0 100644 --- a/doc/README.video +++ b/doc/README.video @@ -26,5 +26,5 @@ U-Boot MPC8xx video controller driver The driver has been tested with the following configurations: -- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it +- MPC823FADS with AD7176 on a PAL TV (YCbYCr) - arsenio@tin.it - GENIETV with AD7177 on a PAL TV (YCbYCr) - arsenio@tin.it diff --git a/drivers/3c589.c b/drivers/3c589.c new file mode 100644 index 000000000..080b686e2 --- /dev/null +++ b/drivers/3c589.c @@ -0,0 +1,519 @@ +/*------------------------------------------------------------------------ + . 3c589.c + . This is a driver for 3Com's 3C589 (Etherlink III) PCMCIA Ethernet device. + . + . (C) Copyright 2002 + . Sysgo Real-Time Solutions, GmbH + . Rolf Offermanns + . + . This program is free software; you can redistribute it and/or modify + . it under the terms of the GNU General Public License as published by + . the Free Software Foundation; either version 2 of the License, or + . (at your option) any later version. + . + . This program is distributed in the hope that it will be useful, + . but WITHOUT ANY WARRANTY; without even the implied warranty of + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + . GNU General Public License for more details. + . + . You should have received a copy of the GNU General Public License + . along with this program; if not, write to the Free Software + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + . + ----------------------------------------------------------------------------*/ + +#include +#include +#include + +#ifdef CONFIG_DRIVER_3C589 + +#include "3c589.h" + + +/* Use power-down feature of the chip */ +#define POWER_DOWN 0 + +#define NO_AUTOPROBE + +static const char version[] = + "Your ad here! :P\n"; + + +#undef EL_DEBUG + +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long int dword; +/*------------------------------------------------------------------------ + . + . Configuration options, for the experienced user to change. + . + -------------------------------------------------------------------------*/ + +/* + . Wait time for memory to be free. This probably shouldn't be + . tuned that much, as waiting for this means nothing else happens + . in the system +*/ +#define MEMORY_WAIT_TIME 16 + + +#if (EL_DEBUG > 2 ) +#define PRINTK3(args...) printf(args) +#else +#define PRINTK3(args...) +#endif + +#if EL_DEBUG > 1 +#define PRINTK2(args...) printf(args) +#else +#define PRINTK2(args...) +#endif + +#ifdef EL_DEBUG +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + +#define outb(args...) mmio_outb(args) +#define mmio_outb(value, addr) (*((volatile byte *)(addr)) = value) + +#define inb(args...) mmio_inb(args) +#define mmio_inb(addr) (*((volatile byte *)(addr))) + +#define outw(args...) mmio_outw(args) +#define mmio_outw(value, addr) (*((volatile word *)(addr)) = value) + +#define inw(args...) mmio_inw(args) +#define mmio_inw(addr) (*((volatile word *)(addr))) + +#define outsw(args...) mmio_outsw(args) +#define mmio_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + mmio_outw( *(__b2 + __i), r); \ + } \ + }) + +#define insw(args...) mmio_insw(args) +#define mmio_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = mmio_inw(r); \ + mmio_inw(0); \ + }; \ + }) + +/*------------------------------------------------------------------------ + . + . The internal workings of the driver. If you are changing anything + . here with the 3Com stuff, you should have the datasheet and know + . what you are doing. + . + -------------------------------------------------------------------------*/ +#define EL_BASE_ADDR 0x20000000 + + +/* Offsets from base I/O address. */ +#define EL3_DATA 0x00 +#define EL3_TIMER 0x0a +#define EL3_CMD 0x0e +#define EL3_STATUS 0x0e + +#define EEPROM_READ 0x0080 + +#define EL3WINDOW(win_num) mmio_outw(SelectWindow + (win_num), EL_BASE_ADDR + EL3_CMD) + +/* The top five bits written to EL3_CMD are a command, the lower + 11 bits are the parameter, if applicable. */ +enum c509cmd { + TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11, + RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, RxDiscard = 8<<11, + TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11, + FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11, + SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11, + SetTxThreshold = 18<<11, SetTxStart = 19<<11, StatsEnable = 21<<11, + StatsDisable = 22<<11, StopCoax = 23<<11, +}; + +enum c509status { + IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004, + TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, + IntReq = 0x0040, StatsFull = 0x0080, CmdBusy = 0x1000 +}; + +/* The SetRxFilter command accepts the following classes: */ +enum RxFilter { + RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 +}; + +/* Register window 1 offsets, the window used in normal operation. */ +#define TX_FIFO 0x00 +#define RX_FIFO 0x00 +#define RX_STATUS 0x08 +#define TX_STATUS 0x0B +#define TX_FREE 0x0C /* Remaining free bytes in Tx buffer. */ + + +/* + Read a word from the EEPROM using the regular EEPROM access register. + Assume that we are in register window zero. +*/ +static word read_eeprom(dword ioaddr, int index) +{ + int i; + outw(EEPROM_READ + index, ioaddr + 0xa); + /* Reading the eeprom takes 162 us */ + for (i = 1620; i >= 0; i--) + if ((inw(ioaddr + 10) & EEPROM_BUSY) == 0) + break; + return inw(ioaddr + 0xc); +} + +static void el_get_mac_addr( unsigned char *mac_addr ) +{ + int i; + union + { + word w; + unsigned char b[2]; + } wrd; + unsigned char old_window = inw( EL_BASE_ADDR + EL3_STATUS ) >> 13; + GO_WINDOW(0); + VX_BUSY_WAIT; + for (i = 0; i < 3; i++) + { + wrd.w = read_eeprom(EL_BASE_ADDR, 0xa+i); +#ifdef __BIG_ENDIAN + mac_addr[2*i] = wrd.b[0]; + mac_addr[2*i+1] = wrd.b[1]; +#else + mac_addr[2*i] = wrd.b[1]; + mac_addr[2*i+1] = wrd.b[0]; +#endif + } + GO_WINDOW(old_window); + VX_BUSY_WAIT; +} + + +#if EL_DEBUG > 1 +static void print_packet( byte * buf, int length ) +{ + int i; + int remainder; + int lines; + + PRINTK2("Packet of length %d \n", length ); + + lines = length / 16; + remainder = length % 16; + + for ( i = 0; i < lines ; i ++ ) { + int cur; + + for ( cur = 0; cur < 8; cur ++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + PRINTK2("%02x%02x ", a, b ); + } + PRINTK2("\n"); + } + for ( i = 0; i < remainder/2 ; i++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + PRINTK2("%02x%02x ", a, b ); + } + PRINTK2("\n"); +} +#endif /* EL_DEBUG > 1 */ + + +/************************************************************************** +ETH_RESET - Reset adapter +***************************************************************************/ +static void el_reset(bd_t *bd) +{ + /*********************************************************** + Reset 3Com 595 card + *************************************************************/ + /* QUICK HACK + * - adjust timing for 3c589 + * - enable io for PCMCIA */ + outw(0x0004, 0xa0000018); + udelay(100); + outw(0x0041, 0x28010000); + udelay(100); + + /* issue global reset */ + outw(GLOBAL_RESET, BASE + VX_COMMAND); + + /* must wait for at least 1ms */ + udelay(100000000); + + /* set mac addr */ + { + unsigned char *mac_addr = bd->bi_enetaddr; + int i; + + el_get_mac_addr( mac_addr ); + + GO_WINDOW(2); + VX_BUSY_WAIT; + + printf("3C589 MAC Addr.: "); + for (i = 0; i < 6; i++) + { + printf("%02x", mac_addr[i]); + outb(mac_addr[i], BASE + VX_W2_ADDR_0 + i); + VX_BUSY_WAIT; + } + printf("\n\n"); + } + + /* set RX filter */ + outw(SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST, BASE + VX_COMMAND); + VX_BUSY_WAIT; + + + /* set irq mask and read_zero */ + outw(SET_RD_0_MASK | S_CARD_FAILURE | S_RX_COMPLETE | + S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND); + VX_BUSY_WAIT; + + outw(SET_INTR_MASK | S_CARD_FAILURE | S_RX_COMPLETE | + S_TX_COMPLETE | S_TX_AVAIL, BASE + VX_COMMAND); + VX_BUSY_WAIT; + + /* enable TP Linkbeat */ + GO_WINDOW(4); + VX_BUSY_WAIT; + + outw( ENABLE_UTP, BASE + VX_W4_MEDIA_TYPE); + VX_BUSY_WAIT; + + +/* + * Attempt to get rid of any stray interrupts that occured during + * configuration. On the i386 this isn't possible because one may + * already be queued. However, a single stray interrupt is + * unimportant. + */ + + outw(ACK_INTR | 0xff, BASE + VX_COMMAND); + VX_BUSY_WAIT; + + /* enable TX and RX */ + outw( RX_ENABLE, BASE + VX_COMMAND ); + VX_BUSY_WAIT; + + outw( TX_ENABLE, BASE + VX_COMMAND ); + VX_BUSY_WAIT; + + + /* print the diag. regs. */ + PRINTK2("Diag. Regs\n"); + PRINTK2("--> MEDIA_TYPE: %04x\n", inw(BASE + VX_W4_MEDIA_TYPE)); + PRINTK2("--> NET_DIAG: %04x\n", inw(BASE + VX_W4_NET_DIAG)); + PRINTK2("--> FIFO_DIAG: %04x\n", inw(BASE + VX_W4_FIFO_DIAG)); + PRINTK2("--> CTRLR_STATUS: %04x\n", inw(BASE + VX_W4_CTRLR_STATUS)); + PRINTK2("\n\n"); + + /* enter working mode */ + GO_WINDOW(1); + VX_BUSY_WAIT; + + /* wait for another 1ms */ + udelay(100000000); +} + + +/*----------------------------------------------------------------- + . + . The driver can be entered at any of the following entry points. + . + .------------------------------------------------------------------ */ + +extern int eth_init(bd_t *bd); +extern void eth_halt(void); +extern int eth_rx(void); +extern int eth_send(volatile void *packet, int length); + + +/* + ------------------------------------------------------------ + . + . Internal routines + . + ------------------------------------------------------------ +*/ + +int eth_init(bd_t *bd) +{ + el_reset(bd); + return 0; +} + +void eth_halt() { + return; +} + +#define EDEBUG 1 + + +/************************************************************************** +ETH_POLL - Wait for a frame +***************************************************************************/ + +int eth_rx() +{ + word status, rx_status, packet_size; + + VX_BUSY_WAIT; + + status = inw( BASE + VX_STATUS ); + + if ( (status & S_RX_COMPLETE) == 0 ) return 0; /* nothing to do */ + + /* Packet waiting -> check RX_STATUS */ + rx_status = inw( BASE + VX_W1_RX_STATUS ); + + if ( rx_status & ERR_RX ) + { + /* error in packet -> discard */ + PRINTK("[ERROR] Invalid packet -> discarding\n"); + PRINTK("-- error code 0x%02x\n", rx_status & ERR_MASK); + PRINTK("-- rx bytes 0x%04d\n", rx_status & ((1<<11) - 1)); + PRINTK("[ERROR] Invalid packet -> discarding\n"); + outw( RX_DISCARD_TOP_PACK, BASE + VX_COMMAND ); + return 0; + } + + /* correct pack. waiting in fifo */ + packet_size = rx_status & RX_BYTES_MASK; + + PRINTK("Correct packet waiting in fifo, size: %d\n", packet_size); + + { + volatile word *packet_start = (word *)(BASE + VX_W1_RX_PIO_RD_1); + word *RcvBuffer = (word *)(NetRxPackets[0]); + int wcount = 0; + + for (wcount = 0; wcount < (packet_size >> 1); wcount++) + { + *RcvBuffer++ = *(packet_start); + } + + /* handle odd packets */ + if ( packet_size & 1 ) + { + *RcvBuffer++ = *(packet_start); + } + } + + /* fifo should now be empty (besides the padding bytes) */ + if ( ((*((word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK) > 3 ) + { + PRINTK("[ERROR] Fifo not empty after packet read (remaining pkts: %d)\n", + (((*(word *)(BASE + VX_W1_RX_STATUS))) & RX_BYTES_MASK)); + } + + /* discard packet */ + *((word *)(BASE + VX_COMMAND)) = RX_DISCARD_TOP_PACK; + + /* Pass Packets to upper Layer */ + NetReceive(NetRxPackets[0], packet_size); + return packet_size; +} + + +/************************************************************************** +ETH_TRANSMIT - Transmit a frame +***************************************************************************/ +static char padmap[] = { + 0, 3, 2, 1}; + + +int eth_send(volatile void *packet, int length) { + int pad; + int status; + volatile word *buf = (word *)packet; + int dummy = 0; + + /* padding stuff */ + pad = padmap[length & 3]; + + PRINTK("eth_send(), length: %d\n", length); + /* drop acknowledgements */ + while(( status=inb(EL_BASE_ADDR + VX_W1_TX_STATUS) )& TXS_COMPLETE ) { + if(status & (TXS_UNDERRUN|TXS_MAX_COLLISION|TXS_STATUS_OVERFLOW)) { + outw(TX_RESET, EL_BASE_ADDR + VX_COMMAND); + outw(TX_ENABLE, EL_BASE_ADDR + VX_COMMAND); + PRINTK("Bad status, resetting and reenabling transmitter\n"); + } + + outb(0x0, EL_BASE_ADDR + VX_W1_TX_STATUS); + } + + + while (inw(EL_BASE_ADDR + VX_W1_FREE_TX) < length + pad + 4) { + /* no room in FIFO */ + if (dummy == 0) + { + PRINTK("No room in FIFO, waiting...\n"); + dummy++; + } + + } + + PRINTK(" ---> FIFO ready\n"); + + + outw(length, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1); + + /* Second dword meaningless */ + outw(0x0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1); + +#if EL_DEBUG > 1 + print_packet((byte *)buf, length); +#endif + + /* write packet */ + { + unsigned int i, totw; + + totw = ((length + 1) >> 1); + PRINTK("Buffer: (totw = %d)\n", totw); + for (i = 0; i < totw; i++) { + outw( *(buf+i), EL_BASE_ADDR + VX_W1_TX_PIO_WR_1); + udelay(10); + } + if(totw & 1) + { /* pad to double word length */ + outw( 0, EL_BASE_ADDR + VX_W1_TX_PIO_WR_1); + udelay(10); + } + PRINTK("\n\n"); + } + + /* wait for Tx complete */ + PRINTK("Waiting for Tx to complete...\n"); + while(((status = inw(EL_BASE_ADDR + VX_STATUS)) & S_COMMAND_IN_PROGRESS) != 0) + { + udelay(10); + } + PRINTK(" ---> Tx completed, status = 0x%04x\n", status); + + return length; +} + + +#endif /* CONFIG_DRIVER_3C589 */ diff --git a/drivers/3c589.h b/drivers/3c589.h new file mode 100644 index 000000000..6735bf9f6 --- /dev/null +++ b/drivers/3c589.h @@ -0,0 +1,435 @@ +/* + * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. 2. The name + * of the author may not be used to endorse or promote products derived from + * this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + October 2, 1994 + + Modified by: Andres Vega Garcia + + INRIA - Sophia Antipolis, France + e-mail: avega@sophia.inria.fr + finger: avega@pax.inria.fr + + */ + +/* + * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the + * 3c590 family. + */ + +/* + * Modified by Shusuke Nisiyama + * for etherboot + * Mar. 14, 2000 +*/ + +/* + * Ethernet software status per interface. + */ + +/* + * Some global constants + */ + +#define TX_INIT_RATE 16 +#define TX_INIT_MAX_RATE 64 +#define RX_INIT_LATENCY 64 +#define RX_INIT_EARLY_THRESH 64 +#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ +#define MIN_RX_EARLY_THRESHL 4 + +#define EEPROMSIZE 0x40 +#define MAX_EEPROMBUSY 1000 +#define VX_LAST_TAG 0xd7 +#define VX_MAX_BOARDS 16 +#define VX_ID_PORT 0x100 + +/* + * some macros to acces long named fields + */ +#define BASE (EL_BASE_ADDR) + +/* + * Commands to read/write EEPROM trough EEPROM command register (Window 0, + * Offset 0xa) + */ +#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ +#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ +#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ +#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ + +#define EEPROM_BUSY (1<<15) + +/* + * Some short functions, worth to let them be a macro + */ + +/************************************************************************** + * * + * These define the EEPROM data structure. They are used in the probe + * function to verify the existence of the adapter after having sent + * the ID_Sequence. + * + * There are others but only the ones we use are defined here. + * + **************************************************************************/ + +#define EEPROM_NODE_ADDR_0 0x0 /* Word */ +#define EEPROM_NODE_ADDR_1 0x1 /* Word */ +#define EEPROM_NODE_ADDR_2 0x2 /* Word */ +#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ +#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ +#define EEPROM_ADDR_CFG 0x8 /* Base addr */ +#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ +#define EEPROM_OEM_ADDR_0 0xa /* Word */ +#define EEPROM_OEM_ADDR_1 0xb /* Word */ +#define EEPROM_OEM_ADDR_2 0xc /* Word */ +#define EEPROM_SOFT_INFO_2 0xf /* Software information 2 */ + +#define NO_RX_OVN_ANOMALY (1<<5) + +/************************************************************************** + * * + * These are the registers for the 3Com 3c509 and their bit patterns when * + * applicable. They have been taken out the the "EtherLink III Parallel * + * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * + * from 3com. * + * * + **************************************************************************/ + +#define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a + * command reg. */ +#define VX_STATUS 0x0e /* Read. BASE+0x0e is always status + * reg. */ +#define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window + * reg. */ +/* + * Window 0 registers. Setup. + */ +/* Write */ +#define VX_W0_EEPROM_DATA 0x0c +#define VX_W0_EEPROM_COMMAND 0x0a +#define VX_W0_RESOURCE_CFG 0x08 +#define VX_W0_ADDRESS_CFG 0x06 +#define VX_W0_CONFIG_CTRL 0x04 + /* Read */ +#define VX_W0_PRODUCT_ID 0x02 +#define VX_W0_MFG_ID 0x00 + + +/* + * Window 1 registers. Operating Set. + */ +/* Write */ +#define VX_W1_TX_PIO_WR_2 0x02 +#define VX_W1_TX_PIO_WR_1 0x00 +/* Read */ +#define VX_W1_FREE_TX 0x0c +#define VX_W1_TX_STATUS 0x0b /* byte */ +#define VX_W1_TIMER 0x0a /* byte */ +#define VX_W1_RX_STATUS 0x08 +#define VX_W1_RX_PIO_RD_2 0x02 +#define VX_W1_RX_PIO_RD_1 0x00 + +/* + * Window 2 registers. Station Address Setup/Read + */ +/* Read/Write */ +#define VX_W2_ADDR_5 0x05 +#define VX_W2_ADDR_4 0x04 +#define VX_W2_ADDR_3 0x03 +#define VX_W2_ADDR_2 0x02 +#define VX_W2_ADDR_1 0x01 +#define VX_W2_ADDR_0 0x00 + +/* + * Window 3 registers. FIFO Management. + */ +/* Read */ +#define VX_W3_INTERNAL_CFG 0x00 +#define VX_W3_RESET_OPT 0x08 +#define VX_W3_FREE_TX 0x0c +#define VX_W3_FREE_RX 0x0a + +/* + * Window 4 registers. Diagnostics. + */ +/* Read/Write */ +#define VX_W4_MEDIA_TYPE 0x0a +#define VX_W4_CTRLR_STATUS 0x08 +#define VX_W4_NET_DIAG 0x06 +#define VX_W4_FIFO_DIAG 0x04 +#define VX_W4_HOST_DIAG 0x02 +#define VX_W4_TX_DIAG 0x00 + +/* + * Window 5 Registers. Results and Internal status. + */ +/* Read */ +#define VX_W5_READ_0_MASK 0x0c +#define VX_W5_INTR_MASK 0x0a +#define VX_W5_RX_FILTER 0x08 +#define VX_W5_RX_EARLY_THRESH 0x06 +#define VX_W5_TX_AVAIL_THRESH 0x02 +#define VX_W5_TX_START_THRESH 0x00 + +/* + * Window 6 registers. Statistics. + */ +/* Read/Write */ +#define TX_TOTAL_OK 0x0c +#define RX_TOTAL_OK 0x0a +#define TX_DEFERRALS 0x08 +#define RX_FRAMES_OK 0x07 +#define TX_FRAMES_OK 0x06 +#define RX_OVERRUNS 0x05 +#define TX_COLLISIONS 0x04 +#define TX_AFTER_1_COLLISION 0x03 +#define TX_AFTER_X_COLLISIONS 0x02 +#define TX_NO_SQE 0x01 +#define TX_CD_LOST 0x00 + +/**************************************** + * + * Register definitions. + * + ****************************************/ + +/* + * Command register. All windows. + * + * 16 bit register. + * 15-11: 5-bit code for command to be executed. + * 10-0: 11-bit arg if any. For commands with no args; + * this can be set to anything. + */ +#define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms + * after issuing */ +#define WINDOW_SELECT (unsigned short) (0x1<<11) +#define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to + * determine whether + * this is needed. If + * so; wait 800 uSec + * before using trans- + * ceiver. */ +#define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on + * power-up */ +#define RX_ENABLE (unsigned short) (0x4<<11) +#define RX_RESET (unsigned short) (0x5<<11) +#define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11) +#define TX_ENABLE (unsigned short) (0x9<<11) +#define TX_DISABLE (unsigned short) (0xa<<11) +#define TX_RESET (unsigned short) (0xb<<11) +#define REQ_INTR (unsigned short) (0xc<<11) +/* + * The following C_* acknowledge the various interrupts. Some of them don't + * do anything. See the manual. + */ +#define ACK_INTR (unsigned short) (0x6800) +# define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1) +# define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2) +# define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4) +# define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8) +# define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10) +# define C_RX_EARLY (unsigned short) (ACK_INTR|0x20) +# define C_INT_RQD (unsigned short) (ACK_INTR|0x40) +# define C_UPD_STATS (unsigned short) (ACK_INTR|0x80) +#define SET_INTR_MASK (unsigned short) (0xe<<11) +#define SET_RD_0_MASK (unsigned short) (0xf<<11) +#define SET_RX_FILTER (unsigned short) (0x10<<11) +# define FIL_INDIVIDUAL (unsigned short) (0x1) +# define FIL_MULTICAST (unsigned short) (0x02) +# define FIL_BRDCST (unsigned short) (0x04) +# define FIL_PROMISC (unsigned short) (0x08) +#define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11) +#define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11) +#define SET_TX_START_THRESH (unsigned short) (0x13<<11) +#define STATS_ENABLE (unsigned short) (0x15<<11) +#define STATS_DISABLE (unsigned short) (0x16<<11) +#define STOP_TRANSCEIVER (unsigned short) (0x17<<11) + +/* + * Status register. All windows. + * + * 15-13: Window number(0-7). + * 12: Command_in_progress. + * 11: reserved. + * 10: reserved. + * 9: reserved. + * 8: reserved. + * 7: Update Statistics. + * 6: Interrupt Requested. + * 5: RX Early. + * 4: RX Complete. + * 3: TX Available. + * 2: TX Complete. + * 1: Adapter Failure. + * 0: Interrupt Latch. + */ +#define S_INTR_LATCH (unsigned short) (0x1) +#define S_CARD_FAILURE (unsigned short) (0x2) +#define S_TX_COMPLETE (unsigned short) (0x4) +#define S_TX_AVAIL (unsigned short) (0x8) +#define S_RX_COMPLETE (unsigned short) (0x10) +#define S_RX_EARLY (unsigned short) (0x20) +#define S_INT_RQD (unsigned short) (0x40) +#define S_UPD_STATS (unsigned short) (0x80) +#define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000) + +#define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) + +/* Address Config. Register. + * Window 0/Port 06 + */ + +#define ACF_CONNECTOR_BITS 14 +#define ACF_CONNECTOR_UTP 0 +#define ACF_CONNECTOR_AUI 1 +#define ACF_CONNECTOR_BNC 3 + +#define INTERNAL_CONNECTOR_BITS 20 +#define INTERNAL_CONNECTOR_MASK 0x01700000 + +/* + * FIFO Registers. RX Status. + * + * 15: Incomplete or FIFO empty. + * 14: 1: Error in RX Packet 0: Incomplete or no error. + * 13-11: Type of error. + * 1000 = Overrun. + * 1011 = Run Packet Error. + * 1100 = Alignment Error. + * 1101 = CRC Error. + * 1001 = Oversize Packet Error (>1514 bytes) + * 0010 = Dribble Bits. + * (all other error codes, no errors.) + * + * 10-0: RX Bytes (0-1514) + */ +#define ERR_INCOMPLETE (unsigned short) (0x8000) +#define ERR_RX (unsigned short) (0x4000) +#define ERR_MASK (unsigned short) (0x7800) +#define ERR_OVERRUN (unsigned short) (0x4000) +#define ERR_RUNT (unsigned short) (0x5800) +#define ERR_ALIGNMENT (unsigned short) (0x6000) +#define ERR_CRC (unsigned short) (0x6800) +#define ERR_OVERSIZE (unsigned short) (0x4800) +#define ERR_DRIBBLE (unsigned short) (0x1000) + +/* + * TX Status. + * + * Reports the transmit status of a completed transmission. Writing this + * register pops the transmit completion stack. + * + * Window 1/Port 0x0b. + * + * 7: Complete + * 6: Interrupt on successful transmission requested. + * 5: Jabber Error (TP Only, TX Reset required. ) + * 4: Underrun (TX Reset required. ) + * 3: Maximum Collisions. + * 2: TX Status Overflow. + * 1-0: Undefined. + * + */ +#define TXS_COMPLETE 0x80 +#define TXS_INTR_REQ 0x40 +#define TXS_JABBER 0x20 +#define TXS_UNDERRUN 0x10 +#define TXS_MAX_COLLISION 0x8 +#define TXS_STATUS_OVERFLOW 0x4 + +#define RS_AUI (1<<5) +#define RS_BNC (1<<4) +#define RS_UTP (1<<3) +#define RS_T4 (1<<0) +#define RS_TX (1<<1) +#define RS_FX (1<<2) +#define RS_MII (1<<6) + + +/* + * FIFO Status (Window 4) + * + * Supports FIFO diagnostics + * + * Window 4/Port 0x04.1 + * + * 15: 1=RX receiving (RO). Set when a packet is being received + * into the RX FIFO. + * 14: Reserved + * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. + * Requires RX Reset or Global Reset command to recover. + * It is generated when you read past the end of a packet - + * reading past what has been received so far will give bad + * data. + * 12: 1=RX status overrun (RO). Set when there are already 8 + * packets in the RX FIFO. While this bit is set, no additional + * packets are received. Requires no action on the part of + * the host. The condition is cleared once a packet has been + * read out of the RX FIFO. + * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there + * may not be an overrun packet yet). While this bit is set, + * no additional packets will be received (some additional + * bytes can still be pending between the wire and the RX + * FIFO). Requires no action on the part of the host. The + * condition is cleared once a few bytes have been read out + * from the RX FIFO. + * 10: 1=TX overrun (RO). Generates adapter failure interrupt. + * Requires TX Reset or Global Reset command to recover. + * Disables Transmitter. + * 9-8: Unassigned. + * 7-0: Built in self test bits for the RX and TX FIFO's. + */ +#define FIFOS_RX_RECEIVING (unsigned short) 0x8000 +#define FIFOS_RX_UNDERRUN (unsigned short) 0x2000 +#define FIFOS_RX_STATUS_OVERRUN (unsigned short) 0x1000 +#define FIFOS_RX_OVERRUN (unsigned short) 0x0800 +#define FIFOS_TX_OVERRUN (unsigned short) 0x0400 + +/* + * Misc defines for various things. + */ +#define TAG_ADAPTER 0xd0 +#define ACTIVATE_ADAPTER_TO_CONFIG 0xff +#define ENABLE_DRQ_IRQ 0x0001 +#define MFG_ID 0x506d /* `TCM' */ +#define PROD_ID 0x5090 +#define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND) +#define JABBER_GUARD_ENABLE 0x40 +#define LINKBEAT_ENABLE 0x80 +#define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) +#define DISABLE_UTP 0x0 +#define RX_BYTES_MASK (unsigned short) (0x07ff) +#define RX_ERROR 0x4000 +#define RX_INCOMPLETE 0x8000 +#define TX_INDICATE 1<<15 +#define is_eeprom_busy(b) (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY) + +#define VX_IOSIZE 0x20 + +#define VX_CONNECTORS 8 + +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/drivers/5701rls.c b/drivers/5701rls.c new file mode 100644 index 000000000..86950d0f8 --- /dev/null +++ b/drivers/5701rls.c @@ -0,0 +1,46 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* */ +/******************************************************************************/ + +#if INCLUDE_5701_AX_FIX + +#include "bcm570x_mm.h" +#include "5701rls.h" + +LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice) +{ + T3_FWIMG_INFO FwImgInfo; + + FwImgInfo.StartAddress = t3FwStartAddr; + FwImgInfo.Text.Buffer = (PLM_UINT8)t3FwText; + FwImgInfo.Text.Offset = t3FwTextAddr; + FwImgInfo.Text.Length = t3FwTextLen; + FwImgInfo.ROnlyData.Buffer = (PLM_UINT8)t3FwRodata; + FwImgInfo.ROnlyData.Offset = t3FwRodataAddr; + FwImgInfo.ROnlyData.Length = t3FwRodataLen; + FwImgInfo.Data.Buffer = (PLM_UINT8)t3FwData; + FwImgInfo.Data.Offset = t3FwDataAddr; + FwImgInfo.Data.Length = t3FwDataLen; + + if (LM_LoadFirmware(pDevice, + &FwImgInfo, + T3_RX_CPU_ID | T3_TX_CPU_ID, + T3_RX_CPU_ID) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + return LM_STATUS_SUCCESS; +} + +#endif /* INCLUDE_5701_AX_FIX */ diff --git a/drivers/5701rls.h b/drivers/5701rls.h new file mode 100644 index 000000000..30b127a42 --- /dev/null +++ b/drivers/5701rls.h @@ -0,0 +1,198 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ + +typedef unsigned long U32; +int t3FwReleaseMajor = 0x0; +int t3FwReleaseMinor = 0x0; +int t3FwReleaseFix = 0x0; +U32 t3FwStartAddr = 0x08000000; +U32 t3FwTextAddr = 0x08000000; +int t3FwTextLen = 0x9c0; +U32 t3FwRodataAddr = 0x080009c0; +int t3FwRodataLen = 0x60; +U32 t3FwDataAddr = 0x08000a40; +int t3FwDataLen = 0x20; +U32 t3FwSbssAddr = 0x08000a60; +int t3FwSbssLen = 0xc; +U32 t3FwBssAddr = 0x08000a70; +int t3FwBssLen = 0x10; +U32 t3FwText[(0x9c0/4) + 1] = { +0x0, +0x10000003, 0x0, 0xd, 0xd, +0x3c1d0800, 0x37bd3ffc, 0x3a0f021, 0x3c100800, +0x26100000, 0xe000018, 0x0, 0xd, +0x3c1d0800, 0x37bd3ffc, 0x3a0f021, 0x3c100800, +0x26100034, 0xe00021c, 0x0, 0xd, +0x0, 0x0, 0x0, 0x27bdffe0, +0x3c1cc000, 0xafbf0018, 0xaf80680c, 0xe00004c, +0x241b2105, 0x97850000, 0x97870002, 0x9782002c, +0x9783002e, 0x3c040800, 0x248409c0, 0xafa00014, +0x21400, 0x621825, 0x52c00, 0xafa30010, +0x8f860010, 0xe52825, 0xe000060, 0x24070102, +0x3c02ac00, 0x34420100, 0x3c03ac01, 0x34630100, +0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, +0xaf82049c, 0x24020001, 0xaf825ce0, 0xe00003f, +0xaf825d00, 0xe000140, 0x0, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, +0x8f835400, 0x34630400, 0xaf835400, 0xaf825404, +0x3c020800, 0x24420034, 0xaf82541c, 0x3e00008, +0xaf805400, 0x0, 0x0, 0x3c020800, +0x34423000, 0x3c030800, 0x34633000, 0x3c040800, +0x348437ff, 0x3c010800, 0xac220a64, 0x24020040, +0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, +0xac600000, 0x24630004, 0x83102b, 0x5040fffd, +0xac600000, 0x3e00008, 0x0, 0x804821, +0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, +0x8c840a68, 0x8fab0014, 0x24430001, 0x44102b, +0x3c010800, 0xac230a60, 0x14400003, 0x4021, +0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, +0x3c030800, 0x8c630a64, 0x91240000, 0x21140, +0x431021, 0x481021, 0x25080001, 0xa0440000, +0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, +0x8c420a60, 0x3c030800, 0x8c630a64, 0x8f84680c, +0x21140, 0x431021, 0xac440008, 0xac45000c, +0xac460010, 0xac470014, 0xac4a0018, 0x3e00008, +0xac4b001c, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x2000008, +0x0, 0xa0001e3, 0x3c0a0001, 0xa0001e3, +0x3c0a0002, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x3c0a0007, 0xa0001e3, 0x3c0a0008, 0xa0001e3, +0x3c0a0009, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x3c0a000b, 0xa0001e3, +0x3c0a000c, 0xa0001e3, 0x3c0a000d, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x3c0a000e, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x0, 0xa0001e3, +0x0, 0xa0001e3, 0x3c0a0013, 0xa0001e3, +0x3c0a0014, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x27bdffe0, +0x1821, 0x1021, 0xafbf0018, 0xafb10014, +0xafb00010, 0x3c010800, 0x220821, 0xac200a70, +0x3c010800, 0x220821, 0xac200a74, 0x3c010800, +0x220821, 0xac200a78, 0x24630001, 0x1860fff5, +0x2442000c, 0x24110001, 0x8f906810, 0x32020004, +0x14400005, 0x24040001, 0x3c020800, 0x8c420a78, +0x18400003, 0x2021, 0xe000182, 0x0, +0x32020001, 0x10400003, 0x0, 0xe000169, +0x0, 0xa000153, 0xaf915028, 0x8fbf0018, +0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0020, +0x3c050800, 0x8ca50a70, 0x3c060800, 0x8cc60a80, +0x3c070800, 0x8ce70a78, 0x27bdffe0, 0x3c040800, +0x248409d0, 0xafbf0018, 0xafa00010, 0xe000060, +0xafa00014, 0xe00017b, 0x2021, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x24020001, 0x8f836810, +0x821004, 0x21027, 0x621824, 0x3e00008, +0xaf836810, 0x27bdffd8, 0xafbf0024, 0x1080002e, +0xafb00020, 0x8f825cec, 0xafa20018, 0x8f825cec, +0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, +0xaf825cec, 0x8e020000, 0x18400016, 0x0, +0x3c020800, 0x94420a74, 0x8fa3001c, 0x221c0, +0xac830004, 0x8fa2001c, 0x3c010800, 0xe000201, +0xac220a74, 0x10400005, 0x0, 0x8e020000, +0x24420001, 0xa0001df, 0xae020000, 0x3c020800, +0x8c420a70, 0x21c02, 0x321c0, 0xa0001c5, +0xafa2001c, 0xe000201, 0x0, 0x1040001f, +0x0, 0x8e020000, 0x8fa3001c, 0x24420001, +0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, +0xa0001df, 0xae020000, 0x3c100800, 0x26100a78, +0x8e020000, 0x18400028, 0x0, 0xe000201, +0x0, 0x14400024, 0x0, 0x8e020000, +0x3c030800, 0x8c630a70, 0x2442ffff, 0xafa3001c, +0x18400006, 0xae020000, 0x31402, 0x221c0, +0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, +0x2442ff00, 0x2c420300, 0x1440000b, 0x24024000, +0x3c040800, 0x248409dc, 0xafa00010, 0xafa00014, +0x8fa6001c, 0x24050008, 0xe000060, 0x3821, +0xa0001df, 0x0, 0xaf825cf8, 0x3c020800, +0x8c420a40, 0x8fa3001c, 0x24420001, 0xaf835cf8, +0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, +0x3e00008, 0x27bd0028, 0x27bdffe0, 0x3c040800, +0x248409e8, 0x2821, 0x3021, 0x3821, +0xafbf0018, 0xafa00010, 0xe000060, 0xafa00014, +0x8fbf0018, 0x3e00008, 0x27bd0020, 0x8f82680c, +0x8f85680c, 0x21827, 0x3182b, 0x31823, +0x431024, 0x441021, 0xa2282b, 0x10a00006, +0x0, 0x401821, 0x8f82680c, 0x43102b, +0x1440fffd, 0x0, 0x3e00008, 0x0, +0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, +0x64102b, 0x54400002, 0x831023, 0x641023, +0x2c420008, 0x3e00008, 0x38420001, 0x27bdffe0, +0x802821, 0x3c040800, 0x24840a00, 0x3021, +0x3821, 0xafbf0018, 0xafa00010, 0xe000060, +0xafa00014, 0xa000216, 0x0, 0x8fbf0018, +0x3e00008, 0x27bd0020, 0x0, 0x27bdffe0, +0x3c1cc000, 0xafbf0018, 0xe00004c, 0xaf80680c, +0x3c040800, 0x24840a10, 0x3802821, 0x3021, +0x3821, 0xafa00010, 0xe000060, 0xafa00014, +0x2402ffff, 0xaf825404, 0x3c0200aa, 0xe000234, +0xaf825434, 0x8fbf0018, 0x3e00008, 0x27bd0020, +0x0, 0x0, 0x0, 0x27bdffe8, +0xafb00010, 0x24100001, 0xafbf0014, 0x3c01c003, +0xac200000, 0x8f826810, 0x30422000, 0x10400003, +0x0, 0xe000246, 0x0, 0xa00023a, +0xaf905428, 0x8fbf0014, 0x8fb00010, 0x3e00008, +0x27bd0018, 0x27bdfff8, 0x8f845d0c, 0x3c0200ff, +0x3c030800, 0x8c630a50, 0x3442fff8, 0x821024, +0x1043001e, 0x3c0500ff, 0x34a5fff8, 0x3c06c003, +0x3c074000, 0x851824, 0x8c620010, 0x3c010800, +0xac230a50, 0x30420008, 0x10400005, 0x871025, +0x8cc20000, 0x24420001, 0xacc20000, 0x871025, +0xaf825d0c, 0x8fa20000, 0x24420001, 0xafa20000, +0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, +0x8fa20000, 0x8f845d0c, 0x3c030800, 0x8c630a50, +0x851024, 0x1443ffe8, 0x851824, 0x27bd0008, +0x3e00008, 0x0, 0x0, 0x0 }; +U32 t3FwRodata[(0x60/4) + 1] = { +0x35373031, 0x726c7341, 0x0, +0x0, 0x53774576, 0x656e7430, 0x0, +0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, +0x45766e74, 0x0, 0x0, 0x0, +0x0, 0x66617461, 0x6c457272, 0x0, +0x0, 0x4d61696e, 0x43707542, 0x0, +0x0, 0x0 }; +U32 t3FwData[(0x20/4) + 1] = { +0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0 }; diff --git a/drivers/8390.h b/drivers/8390.h new file mode 100644 index 000000000..f087217ed --- /dev/null +++ b/drivers/8390.h @@ -0,0 +1,124 @@ +/* + +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + +*/ + +/* Generic NS8390 register definitions. */ +/* This file is part of Donald Becker's 8390 drivers, and is distributed + under the same license. Auto-loading of 8390.o only in v2.2 - Paul G. + Some of these names and comments originated from the Crynwr + packet drivers, which are distributed under the GPL. */ + +#ifndef _8390_h +#define _8390_h + +/* Some generic ethernet register configurations. */ +#define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */ +#define E8390_RX_IRQ_MASK 0x5 +#define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */ +#define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */ +#define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */ +#define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */ + +/* Register accessed at EN_CMD, the 8390 base addr. */ +#define E8390_STOP 0x01 /* Stop and reset the chip */ +#define E8390_START 0x02 /* Start the chip, clear reset */ +#define E8390_TRANS 0x04 /* Transmit a frame */ +#define E8390_RREAD 0x08 /* Remote read */ +#define E8390_RWRITE 0x10 /* Remote write */ +#define E8390_NODMA 0x20 /* Remote DMA */ +#define E8390_PAGE0 0x00 /* Select page chip registers */ +#define E8390_PAGE1 0x40 /* using the two high-order bits */ +#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ + +/* + * Only generate indirect loads given a machine that needs them. + * - removed AMIGA_PCMCIA from this list, handled as ISA io now + */ + +#define n2k_inb(port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE))) +#define n2k_outb(val,port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)) = val) + +#define EI_SHIFT(x) (x) + +#define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */ +/* Page 0 register offsets. */ +#define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */ +#define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */ +#define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */ +#define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */ +#define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */ +#define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */ +#define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */ +#define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */ +#define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */ +#define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */ +#define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */ +#define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ +#define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */ +#define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */ +#define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */ +#define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */ +#define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */ +#define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */ +#define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */ +#define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */ +#define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */ +#define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */ +#define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */ +#define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */ +#define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */ +#define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */ + +/* Bits in EN0_ISR - Interrupt status register */ +#define ENISR_RX 0x01 /* Receiver, no error */ +#define ENISR_TX 0x02 /* Transmitter, no error */ +#define ENISR_RX_ERR 0x04 /* Receiver, with error */ +#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ +#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ +#define ENISR_COUNTERS 0x20 /* Counters need emptying */ +#define ENISR_RDC 0x40 /* remote dma complete */ +#define ENISR_RESET 0x80 /* Reset completed */ +#define ENISR_ALL 0x3f /* Interrupts we will enable */ + +/* Bits in EN0_DCFG - Data config register */ +#define ENDCFG_WTS 0x01 /* word transfer mode selection */ +#define ENDCFG_BOS 0x02 /* byte order selection */ +#define ENDCFG_AUTO_INIT 0x10 /* Auto-init to remove packets from ring */ +#define ENDCFG_FIFO 0x40 /* 8 bytes */ + +/* Page 1 register offsets. */ +#define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */ +#define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */ +#define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */ +#define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */ +#define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */ + +/* Bits in received packet status byte and EN0_RSR*/ +#define ENRSR_RXOK 0x01 /* Received a good packet */ +#define ENRSR_CRC 0x02 /* CRC error */ +#define ENRSR_FAE 0x04 /* frame alignment error */ +#define ENRSR_FO 0x08 /* FIFO overrun */ +#define ENRSR_MPA 0x10 /* missed pkt */ +#define ENRSR_PHY 0x20 /* physical/multicast address */ +#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ +#define ENRSR_DEF 0x80 /* deferring */ + +/* Transmitted packet status, EN0_TSR. */ +#define ENTSR_PTX 0x01 /* Packet transmitted without error */ +#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ +#define ENTSR_COL 0x04 /* The transmit collided at least once. */ +#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ +#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ +#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ +#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ +#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ + +#define NIC_RECEIVE_MONITOR_MODE 0x20 + +#endif /* _8390_h */ diff --git a/drivers/Makefile b/drivers/Makefile new file mode 100644 index 000000000..fd7b7ac99 --- /dev/null +++ b/drivers/Makefile @@ -0,0 +1,71 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG -DDEBUG + +LIB = libdrivers.a + +OBJS = 3c589.o 5701rls.o ali512x.o \ + bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ + cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ + e1000.o eepro100.o \ + i8042.o inca-ip_sw.o keyboard.o \ + lan91c96.o \ + natsemi.o ne2000.o netarm_eth.o netconsole.o \ + ns16550.o ns8382x.o ns87308.o ns7520_eth.o omap1510_i2c.o \ + omap24xx_i2c.o pci.o pci_auto.o pci_indirect.o \ + pcnet.o plb2800_eth.o \ + ps2ser.o ps2mult.o pc_keyb.o \ + rtl8019.o rtl8139.o rtl8169.o \ + s3c4510b_eth.o s3c4510b_uart.o \ + sed13806.o sed156x.o \ + serial.o serial_max3100.o \ + serial_pl010.o serial_pl011.o serial_xuartlite.o \ + sl811_usb.o sm501.o smc91111.o smiLynxEM.o \ + status_led.o sym53c8xx.o \ + twl4030.o ti_pci1410a.o tigon3.o tsec.o \ + usbdcore.o usbdcore_ep0.o usbdcore_omap1510.o usbtty.o \ + videomodes.o w83c553f.o \ + ks8695eth.o smsc9118.o \ + pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ + rpx_pcmcia.o \ + zoom2_debug_board.o \ + zoom2_led.o \ + zoom2_serial.o + + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/drivers/ali512x.c b/drivers/ali512x.c new file mode 100644 index 000000000..7b7edc09a --- /dev/null +++ b/drivers/ali512x.c @@ -0,0 +1,423 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Based on sc520cdp.c from rolo 1.6: + *---------------------------------------------------------------------- + * (C) Copyright 2000 + * Sysgo Real-Time Solutions GmbH + * Klein-Winternheim, Germany + *---------------------------------------------------------------------- + */ + +#include + +#ifdef CONFIG_ALI152X + +#include +#include +#include + + +/* ALI M5123 Logical device numbers: + * 0 FDC + * 1 unused? + * 2 unused? + * 3 lpt + * 4 UART1 + * 5 UART2 + * 6 RTC + * 7 mouse/kbd + * 8 CIO + */ + +/* + ************************************************************ + * Some access primitives for the ALi chip: * + ************************************************************ + */ + +static void ali_write(u8 index, u8 value) +{ + /* write an arbirary register */ + outb(index, ALI_INDEX); + outb(value, ALI_DATA); +} + +#if 0 +static int ali_read(u8 index) +{ + outb(index, ALI_INDEX); + return inb(ALI_DATA); +} +#endif + +#define ALI_OPEN() \ + outb(0x51, ALI_INDEX); \ + outb(0x23, ALI_INDEX) + + +#define ALI_CLOSE() \ + outb(0xbb, ALI_INDEX) + +/* Select a logical device */ +#define ALI_SELDEV(dev) \ + ali_write(0x07, dev) + + +void ali512x_init(void) +{ + ALI_OPEN(); + + ali_write(0x02, 0x01); /* soft reset */ + ali_write(0x03, 0x03); /* disable access to CIOs */ + ali_write(0x22, 0x00); /* disable direct powerdown */ + ali_write(0x23, 0x00); /* disable auto powerdown */ + ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */ + + ALI_CLOSE(); +} + +void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel) +{ + ALI_OPEN(); + ALI_SELDEV(0); + + ali_write(0x30, enabled?1:0); + if (enabled) { + ali_write(0x60, io >> 8); + ali_write(0x61, io & 0xff); + ali_write(0x70, irq); + ali_write(0x74, dma_channel); + + /* AT mode, no drive swap */ + ali_write(0xf0, 0x08); + ali_write(0xf1, 0x00); + ali_write(0xf2, 0xff); + ali_write(0xf4, 0x00); + } + ALI_CLOSE(); +} + + +void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel) +{ + ALI_OPEN(); + ALI_SELDEV(3); + + ali_write(0x30, enabled?1:0); + if (enabled) { + ali_write(0x60, io >> 8); + ali_write(0x61, io & 0xff); + ali_write(0x70, irq); + ali_write(0x74, dma_channel); + + /* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */ + ali_write(0xf0, 0xbc); + /* 12 MHz, Burst DMA in ECP */ + ali_write(0xf1, 0x05); + } + ALI_CLOSE(); + +} + +void ali512x_set_uart(int enabled, int index, u16 io, u8 irq) +{ + ALI_OPEN(); + ALI_SELDEV(index?5:4); + + ali_write(0x30, enabled?1:0); + if (enabled) { + ali_write(0x60, io >> 8); + ali_write(0x61, io & 0xff); + ali_write(0x70, irq); + + ali_write(0xf0, 0x00); + ali_write(0xf1, 0x00); + + /* huh? write 0xf2 twice - a typo in rolo + * or some secret ali errata? Who knows? + */ + if (index) { + ali_write(0xf2, 0x00); + } + ali_write(0xf2, 0x0c); + } + ALI_CLOSE(); + +} + +void ali512x_set_uart2_irda(int enabled) +{ + ALI_OPEN(); + ALI_SELDEV(5); + + ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */ + ALI_CLOSE(); + +} + +void ali512x_set_rtc(int enabled, u16 io, u8 irq) +{ + ALI_OPEN(); + ALI_SELDEV(6); + + ali_write(0x30, enabled?1:0); + if (enabled) { + ali_write(0x60, io >> 8); + ali_write(0x61, io & 0xff); + ali_write(0x70, irq); + + ali_write(0xf0, 0x00); + } + ALI_CLOSE(); +} + +void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) +{ + ALI_OPEN(); + ALI_SELDEV(7); + + ali_write(0x30, enabled?1:0); + if (enabled) { + ali_write(0x70, kbc_irq); + ali_write(0x72, mouse_irq); + + ali_write(0xf0, 0x00); + } + ALI_CLOSE(); +} + + +/* Common I/O + * + * (This descripotsion is base on several incompete sources + * since I have not been able to obtain any datasheet for the device + * there may be some mis-understandings burried in here. + * -- Daniel daniel@omicron.se) + * + * There are 22 CIO pins numbered + * 10-17 + * 20-25 + * 30-37 + * + * 20-24 are dedicated CIO pins, the other 17 are muliplexed with + * other functions. + * + * Secondary + * CIO Pin Function Decription + * ======================================================= + * CIO10 IRQIN1 Interrupt input 1? + * CIO11 IRQIN2 Interrupt input 2? + * CIO12 IRRX IrDa Receive + * CIO13 IRTX IrDa Transmit + * CIO14 P21 KBC P21 fucntion + * CIO15 P20 KBC P21 fucntion + * CIO16 I2C_CLK I2C Clock + * CIO17 I2C_DAT I2C Data + * + * CIO20 - + * CIO21 - + * CIO22 - + * CIO23 - + * CIO24 - + * CIO25 LOCK Keylock + * + * CIO30 KBC_CLK Keybaord Clock + * CIO31 CS0J General Chip Select decoder CS0J + * CIO32 CS1J General Chip Select decoder CS1J + * CIO33 ALT_KCLK Alternative Keyboard Clock + * CIO34 ALT_KDAT Alternative Keyboard Data + * CIO35 ALT_MCLK Alternative Mouse Clock + * CIO36 ALT_MDAT Alternative Mouse Data + * CIO37 ALT_KBC Alternative KBC select + * + * The CIO use an indirect address scheme. + * + * Reigster 3 in the SIO is used to select the index and data + * port addresses where the CIO I/O registers show up. + * The function selection registers are accessible under + * function SIO 8. + * + * SIO reigster 3 (CIO Address Selection) bit definitions: + * bit 7 CIO index and data registers enabled + * bit 1-0 CIO indirect registers port address select + * 0 index = 0xE0 data = 0xE1 + * 1 index = 0xE2 data = 0xE3 + * 2 index = 0xE4 data = 0xE5 + * 3 index = 0xEA data = 0xEB + * + * There are three CIO I/O register accessed via CIO index port and CIO data port + * 0x01 CIO 10-17 data + * 0x02 CIO 20-25 data (bits 7-6 unused) + * 0x03 CIO 30-37 data + * + * + * The pin function is accessed through normal + * SIO registers, each register have the same format: + * + * Bit Function Value + * 0 Input/output 1=input + * 1 Polarity of signal 1=inverted + * 2 Unused ?? + * 3 Function (normal or special) 1=special + * 7-4 Unused + * + * SIO REG + * 0xe0 CIO 10 Config + * 0xe1 CIO 11 Config + * 0xe2 CIO 12 Config + * 0xe3 CIO 13 Config + * 0xe4 CIO 14 Config + * 0xe5 CIO 15 Config + * 0xe6 CIO 16 Config + * 0xe7 CIO 16 Config + * + * 0xe8 CIO 20 Config + * 0xe9 CIO 21 Config + * 0xea CIO 22 Config + * 0xeb CIO 23 Config + * 0xec CIO 24 Config + * 0xed CIO 25 Config + * + * 0xf5 CIO 30 Config + * 0xf6 CIO 31 Config + * 0xf7 CIO 32 Config + * 0xf8 CIO 33 Config + * 0xf9 CIO 34 Config + * 0xfa CIO 35 Config + * 0xfb CIO 36 Config + * 0xfc CIO 37 Config + * + */ + +#define ALI_CIO_PORT_SEL 0x83 +#define ALI_CIO_INDEX 0xea +#define ALI_CIO_DATA 0xeb + +void ali512x_set_cio(int enabled) +{ + int i; + + ALI_OPEN(); + + if (enabled) { + ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */ + } else { + ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80); + } + + ALI_SELDEV(8); + + ali_write(0x30, enabled?1:0); + + /* set all pins to input to start with */ + for (i=0xe0;i<0xee;i++) { + ali_write(i, 1); + } + + for (i=0xf5;i<0xfe;i++) { + ali_write(i, 1); + } + + ALI_CLOSE(); +} + + +void ali512x_cio_function(int pin, int special, int inv, int input) +{ + u8 data; + u8 addr; + + /* valid pins are 10-17, 20-25 and 30-37 */ + if (pin >= 10 && pin <= 17) { + addr = 0xe0+(pin&7); + } else if (pin >= 20 && pin <= 25) { + addr = 0xe8+(pin&7); + } else if (pin >= 30 && pin <= 37) { + addr = 0xf5+(pin&7); + } else { + return; + } + + ALI_OPEN(); + + ALI_SELDEV(8); + + + data=0xf4; + if (special) { + data |= 0x08; + } else { + if (inv) { + data |= 0x02; + } + if (input) { + data |= 0x01; + } + } + + ali_write(addr, data); + + ALI_CLOSE(); +} + +void ali512x_cio_out(int pin, int value) +{ + u8 reg; + u8 data; + u8 bit; + + reg = pin/10; + bit = 1 << (pin%10); + + + outb(reg, ALI_CIO_INDEX); /* select I/O register */ + data = inb(ALI_CIO_DATA); + if (value) { + data |= bit; + } else { + data &= ~bit; + } + outb(data, ALI_CIO_DATA); +} + +int ali512x_cio_in(int pin) +{ + u8 reg; + u8 data; + u8 bit; + + /* valid pins are 10-17, 20-25 and 30-37 */ + reg = pin/10; + bit = 1 << (pin%10); + + + outb(reg, ALI_CIO_INDEX); /* select I/O register */ + data = inb(ALI_CIO_DATA); + + return data & bit; +} + + +#endif diff --git a/drivers/bcm570x.c b/drivers/bcm570x.c new file mode 100644 index 000000000..5f632a646 --- /dev/null +++ b/drivers/bcm570x.c @@ -0,0 +1,1691 @@ +/* + * Broadcom BCM570x Ethernet Driver for U-Boot. + * Support 5701, 5702, 5703, and 5704. Single instance driver. + * Copyright (C) 2002 James F. Dougherty (jfd@broadcom.com) + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && (!defined(CONFIG_NET_MULTI)) && \ + defined(CONFIG_BCM570x) + +#ifdef CONFIG_BMW +#include +#endif +#include +#include "bcm570x_mm.h" +#include "bcm570x_autoneg.h" +#include +#include + + +/* + * PCI Registers and definitions. + */ +#define PCI_CMD_MASK 0xffff0000 /* mask to save status bits */ +#define PCI_ANY_ID (~0) + +/* + * PCI memory base for Ethernet device as well as device Interrupt. + */ +#define BCM570X_MBAR 0x80100000 +#define BCM570X_ILINE 1 + + +#define SECOND_USEC 1000000 +#define MAX_PACKET_SIZE 1600 +#define MAX_UNITS 4 + +/* Globals to this module */ +int initialized = 0; +unsigned int ioBase = 0; +volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */ +volatile PUM_DEVICE_BLOCK pUmDevice = NULL; + +/* Used to pass the full-duplex flag, etc. */ +int line_speed[MAX_UNITS] = {0,0,0,0}; +static int full_duplex[MAX_UNITS] = {1,1,1,1}; +static int rx_flow_control[MAX_UNITS] = {0,0,0,0}; +static int tx_flow_control[MAX_UNITS] = {0,0,0,0}; +static int auto_flow_control[MAX_UNITS] = {0,0,0,0}; +static int tx_checksum[MAX_UNITS] = {1,1,1,1}; +static int rx_checksum[MAX_UNITS] = {1,1,1,1}; +static int auto_speed[MAX_UNITS] = {1,1,1,1}; + +#if JUMBO_FRAMES +/* Jumbo MTU for interfaces. */ +static int mtu[MAX_UNITS] = {0,0,0,0}; +#endif + +/* Turn on Wake-on lan for a device unit */ +static int enable_wol[MAX_UNITS] = {0,0,0,0}; + +#define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT +static unsigned int tx_pkt_desc_cnt[MAX_UNITS] = + {TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, TX_DESC_CNT}; + +#define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT +static unsigned int rx_std_desc_cnt[MAX_UNITS] = + {RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT}; + +static unsigned int rx_adaptive_coalesce[MAX_UNITS] = {1,1,1,1}; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT +#define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT +static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] = + {JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT}; +#endif +#define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS +static unsigned int rx_coalesce_ticks[MAX_UNITS] = + {RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK}; + +#define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES +static unsigned int rx_max_coalesce_frames[MAX_UNITS] = + {RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM}; + +#define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS +static unsigned int tx_coalesce_ticks[MAX_UNITS] = + {TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK}; + +#define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES +static unsigned int tx_max_coalesce_frames[MAX_UNITS] = + {TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM}; + +#define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS +static unsigned int stats_coalesce_ticks[MAX_UNITS] = + {ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK}; + + +/* + * Legitimate values for BCM570x device types + */ +typedef enum { + BCM5700VIGIL = 0, + BCM5700A6, + BCM5700T6, + BCM5700A9, + BCM5700T9, + BCM5700, + BCM5701A5, + BCM5701T1, + BCM5701T8, + BCM5701A7, + BCM5701A10, + BCM5701A12, + BCM5701, + BCM5702, + BCM5703, + BCM5703A31, + TC996T, + TC996ST, + TC996SSX, + TC996SX, + TC996BT, + TC997T, + TC997SX, + TC1000T, + TC940BR01, + TC942BR01, + NC6770, + NC7760, + NC7770, + NC7780 +} board_t; + +/* Chip-Rev names for each device-type */ +static struct { + char* name; +} chip_rev[] = { + {"BCM5700VIGIL"}, + {"BCM5700A6"}, + {"BCM5700T6"}, + {"BCM5700A9"}, + {"BCM5700T9"}, + {"BCM5700"}, + {"BCM5701A5"}, + {"BCM5701T1"}, + {"BCM5701T8"}, + {"BCM5701A7"}, + {"BCM5701A10"}, + {"BCM5701A12"}, + {"BCM5701"}, + {"BCM5702"}, + {"BCM5703"}, + {"BCM5703A31"}, + {"TC996T"}, + {"TC996ST"}, + {"TC996SSX"}, + {"TC996SX"}, + {"TC996BT"}, + {"TC997T"}, + {"TC997SX"}, + {"TC1000T"}, + {"TC940BR01"}, + {"TC942BR01"}, + {"NC6770"}, + {"NC7760"}, + {"NC7770"}, + {"NC7780"}, + {0} +}; + + +/* indexed by board_t, above */ +static struct { + char *name; +} board_info[] = { + { "Broadcom Vigil B5700 1000Base-T" }, + { "Broadcom BCM5700 1000Base-T" }, + { "Broadcom BCM5700 1000Base-SX" }, + { "Broadcom BCM5700 1000Base-SX" }, + { "Broadcom BCM5700 1000Base-T" }, + { "Broadcom BCM5700" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-SX" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701 1000Base-T" }, + { "Broadcom BCM5701" }, + { "Broadcom BCM5702 1000Base-T" }, + { "Broadcom BCM5703 1000Base-T" }, + { "Broadcom BCM5703 1000Base-SX" }, + { "3Com 3C996 10/100/1000 Server NIC" }, + { "3Com 3C996 10/100/1000 Server NIC" }, + { "3Com 3C996 Gigabit Fiber-SX Server NIC" }, + { "3Com 3C996 Gigabit Fiber-SX Server NIC" }, + { "3Com 3C996B Gigabit Server NIC" }, + { "3Com 3C997 Gigabit Server NIC" }, + { "3Com 3C997 Gigabit Fiber-SX Server NIC" }, + { "3Com 3C1000 Gigabit NIC" }, + { "3Com 3C940 Gigabit LOM (21X21)" }, + { "3Com 3C942 Gigabit LOM (31X31)" }, + { "Compaq NC6770 Gigabit Server Adapter" }, + { "Compaq NC7760 Gigabit Server Adapter" }, + { "Compaq NC7770 Gigabit Server Adapter" }, + { "Compaq NC7780 Gigabit Server Adapter" }, + { 0 }, +}; + +/* PCI Devices which use the 570x chipset */ +struct pci_device_table { + unsigned short vendor_id, device_id; /* Vendor/DeviceID */ + unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ + unsigned long board_id; /* Data private to the driver */ + int io_size, min_latency; +} bcm570xDevices[] = { + {0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL ,128,32}, + {0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6 ,128,32}, + {0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6 ,128,32}, + {0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9 ,128,32}, + {0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9 ,128,32}, + {0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700 ,128,32}, + {0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700 ,128,32}, + {0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700 ,128,32}, + {0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700 ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX ,128,32}, + {0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01 ,128,32}, + {0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10 ,128,32}, + {0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12 ,128,32}, + {0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770 ,128,32}, + {0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770 ,128,32}, + {0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780 ,128,32}, + {0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701 ,128,32}, + {0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX ,128,32}, + {0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT ,128,32}, + {0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T ,128,32}, + {0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01 ,128,32}, + {0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701 ,128,32}, + {0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32}, + {0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32}, + {0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32}, + {0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32}, + {0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32}, + {0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32}, + {0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32}, + {0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32}, + {0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780 ,128,32}, + {0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32}, + {0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32}, + {0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32}, + {0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780 ,128,32}, + {0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32} +}; + +#define n570xDevices (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0])) + + +/* + * Allocate a packet buffer from the bcm570x packet pool. + */ +void * +bcm570xPktAlloc(int u, int pksize) +{ + return malloc(pksize); +} + +/* + * Free a packet previously allocated from the bcm570x packet + * buffer pool. + */ +void +bcm570xPktFree(int u, void *p) +{ + free(p); +} + +int +bcm570xReplenishRxBuffers(PUM_DEVICE_BLOCK pUmDevice) +{ + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + void *skb; + int queue_rx = 0; + int ret = 0; + + while ((pUmPacket = (PUM_PACKET) + QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) != 0) { + + pPacket = (PLM_PACKET) pUmPacket; + + /* reuse an old skb */ + if (pUmPacket->skbuff) { + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + queue_rx = 1; + continue; + } + if ( ( skb = bcm570xPktAlloc(pUmDevice->index, + pPacket->u.Rx.RxBufferSize + 2)) == 0) { + QQ_PushHead(&pUmDevice->rx_out_of_buf_q.Container,pPacket); + printf("NOTICE: Out of RX memory.\n"); + ret = 1; + break; + } + + pUmPacket->skbuff = skb; + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + queue_rx = 1; + } + + if (queue_rx) { + LM_QueueRxPackets(pDevice); + } + + return ret; +} + +/* + * Probe, Map, and Init 570x device. + */ +int eth_init(bd_t *bis) +{ + int i, rv, devFound = FALSE; + pci_dev_t devbusfn; + unsigned short status; + + /* Find PCI device, if it exists, configure ... */ + for( i = 0; i < n570xDevices; i++){ + devbusfn = pci_find_device(bcm570xDevices[i].vendor_id, + bcm570xDevices[i].device_id, 0); + if(devbusfn == -1) { + continue; /* No device of that vendor/device ID */ + } else { + + /* Set ILINE */ + pci_write_config_byte(devbusfn, + PCI_INTERRUPT_LINE, BCM570X_ILINE); + + /* + * 0x10 - 0x14 define one 64-bit MBAR. + * 0x14 is the higher-order address bits of the BAR. + */ + pci_write_config_dword(devbusfn, + PCI_BASE_ADDRESS_1, 0); + + ioBase = BCM570X_MBAR; + + pci_write_config_dword(devbusfn, + PCI_BASE_ADDRESS_0, ioBase); + + /* + * Enable PCI memory, IO, and Master -- don't + * reset any status bits in doing so. + */ + pci_read_config_word(devbusfn, + PCI_COMMAND, &status); + + status |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER; + + pci_write_config_word(devbusfn, + PCI_COMMAND, status); + + printf("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n", + board_info[bcm570xDevices[i].board_id].name, + PCI_BUS(devbusfn), + PCI_DEV(devbusfn), + PCI_FUNC(devbusfn), + ioBase); + + /* Allocate once, but always clear on init */ + if (!pDevice) { + pDevice = malloc(sizeof(UM_DEVICE_BLOCK)); + pUmDevice = (PUM_DEVICE_BLOCK)pDevice; + memset(pDevice, 0x0, sizeof(UM_DEVICE_BLOCK)); + } + + /* Configure pci dev structure */ + pUmDevice->pdev = devbusfn; + pUmDevice->index = 0; + pUmDevice->tx_pkt = 0; + pUmDevice->rx_pkt = 0; + devFound = TRUE; + break; + } + } + + if(!devFound){ + printf("eth_init: FAILURE: no BCM570x Ethernet devices found.\n"); + return -1; + } + + /* Setup defaults for chip */ + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + + if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) { + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + } else { + + if (rx_checksum[i]) { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_RX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_RX_UDP_CHECKSUM; + } + + if (tx_checksum[i]) { + pDevice->TaskToOffload |= + LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM; + pDevice->NoTxPseudoHdrChksum = TRUE; + } + } + + /* Set Device PCI Memory base address */ + pDevice->pMappedMemBase = (PLM_UINT8) ioBase; + + /* Pull down adapter info */ + if ((rv = LM_GetAdapterInfo(pDevice)) != LM_STATUS_SUCCESS) { + printf("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv ); + return -2; + } + + /* Lock not needed */ + pUmDevice->do_global_lock = 0; + + if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) { + /* The 5700 chip works best without interleaved register */ + /* accesses on certain machines. */ + pUmDevice->do_global_lock = 1; + } + + /* Setup timer delays */ + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) { + pDevice->UseTaggedStatus = TRUE; + pUmDevice->timer_interval = CFG_HZ; + } + else { + pUmDevice->timer_interval = CFG_HZ / 50; + } + + /* Grab name .... */ + pUmDevice->name = + (char*)malloc(strlen(board_info[bcm570xDevices[i].board_id].name)+1); + strcpy(pUmDevice->name,board_info[bcm570xDevices[i].board_id].name); + + memcpy(pDevice->NodeAddress, bis->bi_enetaddr, 6); + LM_SetMacAddress(pDevice, bis->bi_enetaddr); + /* Init queues .. */ + QQ_InitQueue(&pUmDevice->rx_out_of_buf_q.Container, + MAX_RX_PACKET_DESC_COUNT); + pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0; + + /* delay for 4 seconds */ + pUmDevice->delayed_link_ind = + (4 * CFG_HZ) / pUmDevice->timer_interval; + + pUmDevice->adaptive_expiry = + CFG_HZ / pUmDevice->timer_interval; + + /* Sometimes we get spurious ints. after reset when link is down. */ + /* This field tells the isr to service the int. even if there is */ + /* no status block update. */ + pUmDevice->adapter_just_inited = + (3 * CFG_HZ) / pUmDevice->timer_interval; + + /* Initialize 570x */ + if (LM_InitializeAdapter(pDevice) != LM_STATUS_SUCCESS) { + printf("ERROR: Adapter initialization failed.\n"); + return ERROR; + } + + /* Enable chip ISR */ + LM_EnableInterrupt(pDevice); + + /* Clear MC table */ + LM_MulticastClear(pDevice); + + /* Enable Multicast */ + LM_SetReceiveMask(pDevice, + pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST); + + pUmDevice->opened = 1; + pUmDevice->tx_full = 0; + pUmDevice->tx_pkt = 0; + pUmDevice->rx_pkt = 0; + printf("eth%d: %s @0x%lx,", + pDevice->index, pUmDevice->name, (unsigned long)ioBase); + printf( "node addr "); + for (i = 0; i < 6; i++) { + printf("%2.2x", pDevice->NodeAddress[i]); + } + printf("\n"); + + printf("eth%d: ", pDevice->index); + printf("%s with ", + chip_rev[bcm570xDevices[i].board_id].name); + + if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID) + printf("Broadcom BCM5400 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + printf("Broadcom BCM5401 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID) + printf("Broadcom BCM5411 Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID) + printf("Broadcom BCM5701 Integrated Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID) + printf("Broadcom BCM5703 Integrated Copper "); + else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID) + printf("Broadcom BCM8002 SerDes "); + else if (pDevice->EnableTbi) + printf("Agilent HDMP-1636 SerDes "); + else + printf("Unknown "); + printf("transceiver found\n"); + + printf("eth%d: %s, MTU: %d,", + pDevice->index, pDevice->BusSpeedStr, 1500); + + if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && + rx_checksum[i]) + printf("Rx Checksum ON\n"); + else + printf("Rx Checksum OFF\n"); + initialized++; + + return 0; +} + +/* Ethernet Interrupt service routine */ +void +eth_isr(void) +{ + LM_UINT32 oldtag, newtag; + int i; + + pUmDevice->interrupt = 1; + + if (pDevice->UseTaggedStatus) { + if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) || + pUmDevice->adapter_just_inited) { + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); + oldtag = pDevice->pStatusBlkVirt->StatusTag; + + for (i = 0; ; i++) { + pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED; + LM_ServiceInterrupts(pDevice); + newtag = pDevice->pStatusBlkVirt->StatusTag; + if ((newtag == oldtag) || (i > 50)) { + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24); + if (pDevice->UndiFix) { + REG_WR(pDevice, Grc.LocalCtrl, + pDevice->GrcLocalCtrl | 0x2); + } + break; + } + oldtag = newtag; + } + } + } + else { + while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) { + unsigned int dummy; + + pDevice->pMemView->Mailbox.Interrupt[0].Low = 1; + pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED; + LM_ServiceInterrupts(pDevice); + pDevice->pMemView->Mailbox.Interrupt[0].Low = 0; + dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low; + } + } + + /* Allocate new RX buffers */ + if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) { + bcm570xReplenishRxBuffers(pUmDevice); + } + + /* Queue packets */ + if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) { + LM_QueueRxPackets(pDevice); + } + + if (pUmDevice->tx_queued) { + pUmDevice->tx_queued = 0; + } + + if(pUmDevice->tx_full){ + if(pDevice->LinkStatus != LM_STATUS_LINK_DOWN){ + printf("NOTICE: tx was previously blocked, restarting MUX\n"); + pUmDevice->tx_full = 0; + } + } + + pUmDevice->interrupt = 0; + +} + +int +eth_send(volatile void *packet, int length) +{ + int status = 0; +#if ET_DEBUG + unsigned char* ptr = (unsigned char*)packet; +#endif + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + + /* Link down, return */ + while(pDevice->LinkStatus == LM_STATUS_LINK_DOWN) { +#if 0 + printf("eth%d: link down - check cable or link partner.\n", + pUmDevice->index); +#endif + eth_isr(); + + /* Wait to see link for one-half a second before sending ... */ + udelay(1500000); + + } + + /* Clear sent flag */ + pUmDevice->tx_pkt = 0; + + /* Previously blocked */ + if(pUmDevice->tx_full){ + printf("eth%d: tx blocked.\n", pUmDevice->index); + return 0; + } + + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->TxPacketFreeQ.Container); + + if (pPacket == 0) { + pUmDevice->tx_full = 1; + printf("bcm570xEndSend: TX full!\n"); + return 0; + } + + if (pDevice->SendBdLeft.counter == 0) { + pUmDevice->tx_full = 1; + printf("bcm570xEndSend: no more TX descriptors!\n"); + QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); + return 0; + } + + if (length <= 0){ + printf("eth: bad packet size: %d\n", length); + goto out; + } + + /* Get packet buffers and fragment list */ + pUmPacket = (PUM_PACKET) pPacket; + /* Single DMA Descriptor transmit. + * Fragments may be provided, but one DMA descriptor max is + * used to send the packet. + */ + if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) { + if (pUmPacket->skbuff == NULL){ + /* Packet was discarded */ + printf("TX: failed (1)\n"); + status = 1; + } else{ + printf("TX: failed (2)\n"); + status = 2; + } + QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); + return status; + } + + /* Copy packet to DMA buffer */ + memset(pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE); + memcpy((void*)pUmPacket->skbuff, (void*)packet, length); + pPacket->PacketSize = length; + pPacket->Flags |= SND_BD_FLAG_END|SND_BD_FLAG_COAL_NOW; + pPacket->u.Tx.FragCount = 1; + /* We've already provided a frame ready for transmission */ + pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM; + + if ( LM_SendPacket(pDevice, pPacket) == LM_STATUS_FAILURE){ + /* + * A lower level send failure will push the packet descriptor back + * in the free queue, so just deal with the VxWorks clusters. + */ + if (pUmPacket->skbuff == NULL){ + printf("TX failed (1)!\n"); + /* Packet was discarded */ + status = 3; + } else { + /* A resource problem ... */ + printf("TX failed (2)!\n"); + status = 4; + } + + if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) == 0) { + printf("TX: emptyQ!\n"); + pUmDevice->tx_full = 1; + } + } + + while(pUmDevice->tx_pkt == 0){ + /* Service TX */ + eth_isr(); + } +#if ET_DEBUG + printf("eth_send: 0x%x, %d bytes\n" + "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n", + (int)pPacket, length, + ptr[0],ptr[1],ptr[2],ptr[3],ptr[4],ptr[5], + ptr[6],ptr[7],ptr[8],ptr[9],ptr[10],ptr[11],ptr[12], + ptr[13],ptr[14],ptr[15]); +#endif + pUmDevice->tx_pkt = 0; + QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); + + /* Done with send */ + out: + return status; +} + + +/* Ethernet receive */ +int +eth_rx(void) +{ + PLM_PACKET pPacket = NULL; + PUM_PACKET pUmPacket = NULL; + void *skb; + int size=0; + + while(TRUE) { + + bcm570x_service_isr: + /* Pull down packet if it is there */ + eth_isr(); + + /* Indicate RX packets called */ + if(pUmDevice->rx_pkt){ + /* printf("eth_rx: got a packet...\n"); */ + pUmDevice->rx_pkt = 0; + } else { + /* printf("eth_rx: waiting for packet...\n"); */ + goto bcm570x_service_isr; + } + + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->RxPacketReceivedQ.Container); + + if (pPacket == 0){ + printf("eth_rx: empty packet!\n"); + goto bcm570x_service_isr; + } + + pUmPacket = (PUM_PACKET) pPacket; +#if ET_DEBUG + printf("eth_rx: packet @0x%x\n", + (int)pPacket); +#endif + /* If the packet generated an error, reuse buffer */ + if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) || + ((size = pPacket->PacketSize) > pDevice->RxMtu)) { + + /* reuse skb */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + printf("eth_rx: error in packet dma!\n"); + goto bcm570x_service_isr; + } + + /* Set size and address */ + skb = pUmPacket->skbuff; + size = pPacket->PacketSize; + + /* Pass the packet up to the protocol + * layers. + */ + NetReceive(skb, size); + + /* Free packet buffer */ + bcm570xPktFree (pUmDevice->index, skb); + pUmPacket->skbuff = NULL; + + /* Reuse SKB */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + return 0; /* Got a packet, bail ... */ + } + return size; +} + + +/* Shut down device */ +void +eth_halt(void) +{ + int i; + if ( initialized) + if (pDevice && pUmDevice && pUmDevice->opened){ + printf("\neth%d:%s,", pUmDevice->index, pUmDevice->name); + printf("HALT,"); + /* stop device */ + LM_Halt(pDevice); + printf("POWER DOWN,"); + LM_SetPowerState(pDevice, LM_POWER_STATE_D3); + + /* Free the memory allocated by the device in tigon3 */ + for (i = 0; i < pUmDevice->mem_list_num; i++) { + if (pUmDevice->mem_list[i]) { + /* sanity check */ + if (pUmDevice->dma_list[i]) { /* cache-safe memory */ + free(pUmDevice->mem_list[i]); + } else { + free(pUmDevice->mem_list[i]); /* normal memory */ + } + } + } + pUmDevice->opened = 0; + free(pDevice); + pDevice = NULL; + pUmDevice = NULL; + initialized = 0; + printf("done - offline.\n"); + } +} + + +/* + * + * Middle Module: Interface between the HW driver (tigon3 modules) and + * the native (SENS) driver. These routines implement the system + * interface for tigon3 on VxWorks. + */ + +/* Middle module dependency - size of a packet descriptor */ +int MM_Packet_Desc_Size = sizeof(UM_PACKET); + + +LM_STATUS +MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 *pValue32) +{ + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_read_config_dword(pUmDevice->pdev, + Offset, (u32 *) pValue32); + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 Value32) +{ + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_write_config_dword(pUmDevice->pdev, + Offset, Value32); + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT16 *pValue16) +{ + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_read_config_word(pUmDevice->pdev, + Offset, (u16*) pValue16); + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT16 Value16) +{ + UM_DEVICE_BLOCK *pUmDevice; + pUmDevice = (UM_DEVICE_BLOCK *) pDevice; + pci_write_config_word(pUmDevice->pdev, + Offset, Value16); + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt, + PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, + LM_BOOL Cached) +{ + PLM_VOID pvirt; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + dma_addr_t mapping; + + pvirt = malloc(BlockSize); + mapping = (dma_addr_t)(pvirt); + if (!pvirt) + return LM_STATUS_FAILURE; + + pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; + pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping; + pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; + memset(pvirt, 0, BlockSize); + + *pMemoryBlockVirt = (PLM_VOID) pvirt; + MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping); + + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt) +{ + PLM_VOID pvirt; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + + pvirt = malloc(BlockSize); + + if (!pvirt) + return LM_STATUS_FAILURE; + + pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt; + pUmDevice->dma_list[pUmDevice->mem_list_num] = 0; + pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize; + memset(pvirt, 0, BlockSize); + *pMemoryBlockVirt = pvirt; + + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_MapMemBase(PLM_DEVICE_BLOCK pDevice) +{ + printf("BCM570x PCI Memory base address @0x%x\n", + (unsigned int)pDevice->pMappedMemBase); + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice) +{ + int i; + void* skb; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PUM_PACKET pUmPacket = NULL; + PLM_PACKET pPacket = NULL; + + for (i = 0; i < pDevice->RxPacketDescCnt; i++) { + pPacket = QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + pUmPacket = (PUM_PACKET) pPacket; + + if (pPacket == 0) { + printf("MM_InitializeUmPackets: Bad RxPacketFreeQ\n"); + } + + skb = bcm570xPktAlloc(pUmDevice->index, + pPacket->u.Rx.RxBufferSize + 2); + + if (skb == 0) { + pUmPacket->skbuff = 0; + QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket); + printf("MM_InitializeUmPackets: out of buffer.\n"); + continue; + } + + pUmPacket->skbuff = skb; + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } + + pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8; + + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_GetConfig(PLM_DEVICE_BLOCK pDevice) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + int index = pDevice->index; + + if (auto_speed[index] == 0) + pDevice->DisableAutoNeg = TRUE; + else + pDevice->DisableAutoNeg = FALSE; + + if (line_speed[index] == 0) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->DisableAutoNeg = FALSE; + } + else { + if (line_speed[index] == 1000) { + if (pDevice->EnableTbi) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX; + } + else if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX; + } + else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS; + } + if (!pDevice->EnableTbi) + pDevice->DisableAutoNeg = FALSE; + } + else if (line_speed[index] == 100) { + if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX; + } + else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS; + } + } + else if (line_speed[index] == 10) { + if (full_duplex[index]) { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX; + } + else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; + } + } + else { + pDevice->RequestedMediaType = + LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->DisableAutoNeg = FALSE; + } + + } + pDevice->FlowControlCap = 0; + if (rx_flow_control[index] != 0) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + if (tx_flow_control[index] != 0) { + pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + if ((auto_flow_control[index] != 0) && + (pDevice->DisableAutoNeg == FALSE)) { + + pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE; + if ((tx_flow_control[index] == 0) && + (rx_flow_control[index] == 0)) { + pDevice->FlowControlCap |= + LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + + /* Default MTU for now */ + pUmDevice->mtu = 1500; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if (pUmDevice->mtu > 1500) { + pDevice->RxMtu = pUmDevice->mtu; + pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; + } + else { + pDevice->RxJumboDescCnt = 0; + } + pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index]; +#else + pDevice->RxMtu = pUmDevice->mtu; +#endif + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) { + pDevice->UseTaggedStatus = TRUE; + pUmDevice->timer_interval = CFG_HZ; + } + else { + pUmDevice->timer_interval = CFG_HZ/50; + } + + pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index]; + pDevice->RxStdDescCnt = rx_std_desc_cnt[index]; + /* Note: adaptive coalescence really isn't adaptive in this driver */ + pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index]; + if (!pUmDevice->rx_adaptive_coalesce) { + pDevice->RxCoalescingTicks = rx_coalesce_ticks[index]; + if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS) + pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS; + pUmDevice->rx_curr_coalesce_ticks =pDevice->RxCoalescingTicks; + + pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index]; + if (pDevice->RxMaxCoalescedFrames>MAX_RX_MAX_COALESCED_FRAMES) + pDevice->RxMaxCoalescedFrames = + MAX_RX_MAX_COALESCED_FRAMES; + pUmDevice->rx_curr_coalesce_frames = + pDevice->RxMaxCoalescedFrames; + pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index]; + if (pDevice->StatsCoalescingTicks>MAX_STATS_COALESCING_TICKS) + pDevice->StatsCoalescingTicks= + MAX_STATS_COALESCING_TICKS; + } + else { + pUmDevice->rx_curr_coalesce_frames = + DEFAULT_RX_MAX_COALESCED_FRAMES; + pUmDevice->rx_curr_coalesce_ticks = + DEFAULT_RX_COALESCING_TICKS; + } + pDevice->TxCoalescingTicks = tx_coalesce_ticks[index]; + if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS) + pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS; + pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index]; + if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES) + pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES; + + if (enable_wol[index]) { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET; + pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET; + } + pDevice->NicSendBd = TRUE; + + /* Don't update status blocks during interrupt */ + pDevice->RxCoalescingTicksDuringInt = 0; + pDevice->TxCoalescingTicksDuringInt = 0; + + return LM_STATUS_SUCCESS; + +} + + +LM_STATUS +MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + printf("Start TX DMA: dev=%d packet @0x%x\n", + (int)pUmDevice->index, (unsigned int)pPacket); + + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + printf("Complete TX DMA: dev=%d packet @0x%x\n", + (int)pUmDevice->index, (unsigned int)pPacket); + return LM_STATUS_SUCCESS; +} + + +LM_STATUS +MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status) +{ + char buf[128]; + char lcd[4]; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + LM_FLOW_CONTROL flow_control; + + pUmDevice->delayed_link_ind = 0; + memset(lcd, 0x0, 4); + + if (Status == LM_STATUS_LINK_DOWN) { + sprintf(buf,"eth%d: %s: NIC Link is down\n", + pUmDevice->index,pUmDevice->name); + lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?'; + } else if (Status == LM_STATUS_LINK_ACTIVE) { + sprintf(buf,"eth%d:%s: ", pUmDevice->index, pUmDevice->name); + + if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS){ + strcat(buf,"1000 Mbps "); + lcd[0] = '1';lcd[1]='G';lcd[2]='B'; + } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS){ + strcat(buf,"100 Mbps "); + lcd[0] = '1';lcd[1]='0';lcd[2]='0'; + } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS){ + strcat(buf,"10 Mbps "); + lcd[0] = '1';lcd[1]='0';lcd[2]=' '; + } + if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL){ + strcat(buf, "full duplex"); + lcd[3] = 'F'; + } else { + strcat(buf, "half duplex"); + lcd[3] = 'H'; + } + strcat(buf, " link up"); + + flow_control = pDevice->FlowControl & + (LM_FLOW_CONTROL_RECEIVE_PAUSE | + LM_FLOW_CONTROL_TRANSMIT_PAUSE); + + if (flow_control) { + if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) { + strcat(buf,", receive "); + if (flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + strcat(buf," & transmit "); + } + else { + strcat(buf,", transmit "); + } + strcat(buf,"flow control ON"); + } else { + strcat(buf, ", flow control OFF"); + } + strcat(buf,"\n"); + printf("%s",buf); + } +#if 0 + sysLedDsply(lcd[0],lcd[1],lcd[2],lcd[3]); +#endif + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PUM_PACKET pUmPacket; + void *skb; + + pUmPacket = (PUM_PACKET) pPacket; + + if ((skb = pUmPacket->skbuff)) + bcm570xPktFree(pUmDevice->index, skb); + + pUmPacket->skbuff = 0; + + return LM_STATUS_SUCCESS; +} + +unsigned long +MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo) +{ + return get_timer(0); +} + +/* + * Transform an MBUF chain into a single MBUF. + * This routine will fail if the amount of data in the + * chain overflows a transmit buffer. In that case, + * the incoming MBUF chain will be freed. This routine can + * also fail by not being able to allocate a new MBUF (including + * cluster and mbuf headers). In that case the failure is + * non-fatal. The incoming cluster chain is not freed, giving + * the caller the choice of whether to try a retransmit later. + */ +LM_STATUS +MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + void *skbnew; + int len = 0; + + if (len == 0) + return (LM_STATUS_SUCCESS); + + if (len > MAX_PACKET_SIZE){ + printf ("eth%d: xmit frame discarded, too big!, size = %d\n", + pUmDevice->index, len); + return (LM_STATUS_FAILURE); + } + + skbnew = bcm570xPktAlloc(pUmDevice->index, MAX_PACKET_SIZE); + + if (skbnew == NULL) { + pUmDevice->tx_full = 1; + printf ("eth%d: out of transmit buffers", pUmDevice->index); + return (LM_STATUS_FAILURE); + } + + /* New packet values */ + pUmPacket->skbuff = skbnew; + pUmPacket->lm_packet.u.Tx.FragCount = 1; + + return (LM_STATUS_SUCCESS); +} + + +LM_STATUS +MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + pUmDevice->rx_pkt = 1; + return LM_STATUS_SUCCESS; +} + +LM_STATUS +MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice) +{ + PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice; + PLM_PACKET pPacket; + PUM_PACKET pUmPacket; + void *skb; + while ( TRUE ) { + + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->TxPacketXmittedQ.Container); + + if (pPacket == 0) + break; + + pUmPacket = (PUM_PACKET) pPacket; + skb = (void*)pUmPacket->skbuff; + + /* + * Free MBLK if we transmitted a fragmented packet or a + * non-fragmented packet straight from the VxWorks + * buffer pool. If packet was copied to a local transmit + * buffer, then there's no MBUF to free, just free + * the transmit buffer back to the cluster pool. + */ + + if (skb) + bcm570xPktFree (pUmDevice->index, skb); + + pUmPacket->skbuff = 0; + QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); + pUmDevice->tx_pkt = 1; + } + if (pUmDevice->tx_full) { + if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) >= + (QQ_GetSize(&pDevice->TxPacketFreeQ.Container) >> 1)) + pUmDevice->tx_full = 0; + } + return LM_STATUS_SUCCESS; +} + +/* + * Scan an MBUF chain until we reach fragment number "frag" + * Return its length and physical address. + */ +void MM_MapTxDma + ( + PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR *paddr, + LM_UINT32 *len, + int frag) +{ + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + *len = pPacket->PacketSize; + MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff); +} + +/* + * Convert an mbuf address, a CPU local virtual address, + * to a physical address as seen from a PCI device. Store the + * result at paddr. + */ +void MM_MapRxDma( + PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR *paddr) +{ + PUM_PACKET pUmPacket = (PUM_PACKET) pPacket; + MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff); +} + +void +MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr) +{ +#if (BITS_PER_LONG == 64) + paddr->High = ((unsigned long) addr) >> 32; + paddr->Low = ((unsigned long) addr) & 0xffffffff; +#else + paddr->High = 0; + paddr->Low = (unsigned long) addr; +#endif +} + +void +MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr) +{ + unsigned long baddr = (unsigned long) addr; +#if (BITS_PER_LONG == 64) + set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32); +#else + set_64bit_addr(paddr, baddr, 0); +#endif +} + +/* + * This combination of `inline' and `extern' has almost the effect of a + * macro. The way to use it is to put a function definition in a header + * file with these keywords, and put another copy of the definition + * (lacking `inline' and `extern') in a library file. The definition in + * the header file will cause most calls to the function to be inlined. + * If any uses of the function remain, they will refer to the single copy + * in the library. + */ +void +atomic_set(atomic_t* entry, int val) +{ + entry->counter = val; +} +int +atomic_read(atomic_t* entry) +{ + return entry->counter; +} +void +atomic_inc(atomic_t* entry) +{ + if(entry) + entry->counter++; +} + +void +atomic_dec(atomic_t* entry) +{ + if(entry) + entry->counter--; +} + +void +atomic_sub(int a, atomic_t* entry) +{ + if(entry) + entry->counter -= a; +} + +void +atomic_add(int a, atomic_t* entry) +{ + if(entry) + entry->counter += a; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +QQ_InitQueue( +PQQ_CONTAINER pQueue, +unsigned int QueueSize) { + pQueue->Head = 0; + pQueue->Tail = 0; + pQueue->Size = QueueSize+1; + atomic_set(&pQueue->EntryCnt, 0); +} /* QQ_InitQueue */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +char +QQ_Full( +PQQ_CONTAINER pQueue) { + unsigned int NewHead; + + NewHead = (pQueue->Head + 1) % pQueue->Size; + + return(NewHead == pQueue->Tail); +} /* QQ_Full */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +char +QQ_Empty( +PQQ_CONTAINER pQueue) { + return(pQueue->Head == pQueue->Tail); +} /* QQ_Empty */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +unsigned int +QQ_GetSize( +PQQ_CONTAINER pQueue) { + return pQueue->Size; +} /* QQ_GetSize */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +unsigned int +QQ_GetEntryCnt( +PQQ_CONTAINER pQueue) { + return atomic_read(&pQueue->EntryCnt); +} /* QQ_GetEntryCnt */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* TRUE entry was added successfully. */ +/* FALSE queue is full. */ +/******************************************************************************/ +char +QQ_PushHead( +PQQ_CONTAINER pQueue, +PQQ_ENTRY pEntry) { + unsigned int Head; + + Head = (pQueue->Head + 1) % pQueue->Size; + +#if !defined(QQ_NO_OVERFLOW_CHECK) + if(Head == pQueue->Tail) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ + + pQueue->Array[pQueue->Head] = pEntry; + wmb(); + pQueue->Head = Head; + atomic_inc(&pQueue->EntryCnt); + + return -1; +} /* QQ_PushHead */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* TRUE entry was added successfully. */ +/* FALSE queue is full. */ +/******************************************************************************/ +char +QQ_PushTail( +PQQ_CONTAINER pQueue, +PQQ_ENTRY pEntry) { + unsigned int Tail; + + Tail = pQueue->Tail; + if(Tail == 0) { + Tail = pQueue->Size; + } /* if */ + Tail--; + +#if !defined(QQ_NO_OVERFLOW_CHECK) + if(Tail == pQueue->Head) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ + + pQueue->Array[Tail] = pEntry; + wmb(); + pQueue->Tail = Tail; + atomic_inc(&pQueue->EntryCnt); + + return -1; +} /* QQ_PushTail */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +PQQ_ENTRY +QQ_PopHead( +PQQ_CONTAINER pQueue) { + unsigned int Head; + PQQ_ENTRY Entry; + + Head = pQueue->Head; + +#if !defined(QQ_NO_UNDERFLOW_CHECK) + if(Head == pQueue->Tail) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ + + if(Head == 0) { + Head = pQueue->Size; + } /* if */ + Head--; + + Entry = pQueue->Array[Head]; + membar(); + + pQueue->Head = Head; + atomic_dec(&pQueue->EntryCnt); + + return Entry; +} /* QQ_PopHead */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +PQQ_ENTRY +QQ_PopTail( +PQQ_CONTAINER pQueue) { + unsigned int Tail; + PQQ_ENTRY Entry; + + Tail = pQueue->Tail; + +#if !defined(QQ_NO_UNDERFLOW_CHECK) + if(Tail == pQueue->Head) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ + + Entry = pQueue->Array[Tail]; + membar(); + pQueue->Tail = (Tail + 1) % pQueue->Size; + atomic_dec(&pQueue->EntryCnt); + + return Entry; +} /* QQ_PopTail */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +PQQ_ENTRY +QQ_GetHead( + PQQ_CONTAINER pQueue, + unsigned int Idx) +{ + if(Idx >= atomic_read(&pQueue->EntryCnt)) + { + return (PQQ_ENTRY) 0; + } + + if(pQueue->Head > Idx) + { + Idx = pQueue->Head - Idx; + } + else + { + Idx = pQueue->Size - (Idx - pQueue->Head); + } + Idx--; + + return pQueue->Array[Idx]; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +PQQ_ENTRY +QQ_GetTail( + PQQ_CONTAINER pQueue, + unsigned int Idx) +{ + if(Idx >= atomic_read(&pQueue->EntryCnt)) + { + return (PQQ_ENTRY) 0; + } + + Idx += pQueue->Tail; + if(Idx >= pQueue->Size) + { + Idx = Idx - pQueue->Size; + } + + return pQueue->Array[Idx]; +} + +#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */ diff --git a/drivers/bcm570x_autoneg.c b/drivers/bcm570x_autoneg.c new file mode 100644 index 000000000..9023796aa --- /dev/null +++ b/drivers/bcm570x_autoneg.c @@ -0,0 +1,439 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2001 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ +#if !defined(CONFIG_NET_MULTI) +#if INCLUDE_TBI_SUPPORT +#include "bcm570x_autoneg.h" +#include "bcm570x_mm.h" + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +MM_AnTxConfig( + PAN_STATE_INFO pAnInfo) +{ + PLM_DEVICE_BLOCK pDevice; + + pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext; + + REG_WR(pDevice, MacCtrl.TxAutoNeg, (LM_UINT32) pAnInfo->TxConfig.AsUSHORT); + + pDevice->MacMode |= MAC_MODE_SEND_CONFIGS; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +MM_AnTxIdle( + PAN_STATE_INFO pAnInfo) +{ + PLM_DEVICE_BLOCK pDevice; + + pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext; + + pDevice->MacMode &= ~MAC_MODE_SEND_CONFIGS; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +char +MM_AnRxConfig( + PAN_STATE_INFO pAnInfo, + unsigned short *pRxConfig) +{ + PLM_DEVICE_BLOCK pDevice; + LM_UINT32 Value32; + char Retcode; + + Retcode = AN_FALSE; + + pDevice = (PLM_DEVICE_BLOCK) pAnInfo->pContext; + + Value32 = REG_RD(pDevice, MacCtrl.Status); + if(Value32 & MAC_STATUS_RECEIVING_CFG) + { + Value32 = REG_RD(pDevice, MacCtrl.RxAutoNeg); + *pRxConfig = (unsigned short) Value32; + + Retcode = AN_TRUE; + } + + return Retcode; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +void +AutonegInit( + PAN_STATE_INFO pAnInfo) +{ + unsigned long j; + + for(j = 0; j < sizeof(AN_STATE_INFO); j++) + { + ((unsigned char *) pAnInfo)[j] = 0; + } + + /* Initialize the default advertisement register. */ + pAnInfo->mr_adv_full_duplex = 1; + pAnInfo->mr_adv_sym_pause = 1; + pAnInfo->mr_adv_asym_pause = 1; + pAnInfo->mr_an_enable = 1; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +AUTONEG_STATUS +Autoneg8023z( + PAN_STATE_INFO pAnInfo) +{ + unsigned short RxConfig; + unsigned long Delta_us; + AUTONEG_STATUS AnRet; + + /* Get the current time. */ + if(pAnInfo->State == AN_STATE_UNKNOWN) + { + pAnInfo->RxConfig.AsUSHORT = 0; + pAnInfo->CurrentTime_us = 0; + pAnInfo->LinkTime_us = 0; + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->IdleMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; + } + + /* Increment the timer tick. This function is called every microsecon. */ +/* pAnInfo->CurrentTime_us++; */ + + /* Set the AbilityMatch, IdleMatch, and AckMatch flags if their */ + /* corresponding conditions are satisfied. */ + if(MM_AnRxConfig(pAnInfo, &RxConfig)) + { + if(RxConfig != pAnInfo->AbilityMatchCfg) + { + pAnInfo->AbilityMatchCfg = RxConfig; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->AbilityMatchCnt = 0; + } + else + { + pAnInfo->AbilityMatchCnt++; + if(pAnInfo->AbilityMatchCnt > 1) + { + pAnInfo->AbilityMatch = AN_TRUE; + pAnInfo->AbilityMatchCfg = RxConfig; + } + } + + if(RxConfig & AN_CONFIG_ACK) + { + pAnInfo->AckMatch = AN_TRUE; + } + else + { + pAnInfo->AckMatch = AN_FALSE; + } + + pAnInfo->IdleMatch = AN_FALSE; + } + else + { + pAnInfo->IdleMatch = AN_TRUE; + + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; + + RxConfig = 0; + } + + /* Save the last Config. */ + pAnInfo->RxConfig.AsUSHORT = RxConfig; + + /* Default return code. */ + AnRet = AUTONEG_STATUS_OK; + + /* Autoneg state machine as defined in 802.3z section 37.3.1.5. */ + switch(pAnInfo->State) + { + case AN_STATE_UNKNOWN: + if(pAnInfo->mr_an_enable || pAnInfo->mr_restart_an) + { + pAnInfo->CurrentTime_us = 0; + pAnInfo->State = AN_STATE_AN_ENABLE; + } + + /* Fall through.*/ + + case AN_STATE_AN_ENABLE: + pAnInfo->mr_an_complete = AN_FALSE; + pAnInfo->mr_page_rx = AN_FALSE; + + if(pAnInfo->mr_an_enable) + { + pAnInfo->LinkTime_us = 0; + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->IdleMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; + + pAnInfo->State = AN_STATE_AN_RESTART_INIT; + } + else + { + pAnInfo->State = AN_STATE_DISABLE_LINK_OK; + } + break; + + case AN_STATE_AN_RESTART_INIT: + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + pAnInfo->mr_np_loaded = AN_FALSE; + + pAnInfo->TxConfig.AsUSHORT = 0; + MM_AnTxConfig(pAnInfo); + + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + pAnInfo->State = AN_STATE_AN_RESTART; + + /* Fall through.*/ + + case AN_STATE_AN_RESTART: + /* Get the current time and compute the delta with the saved */ + /* link timer. */ + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { + pAnInfo->State = AN_STATE_ABILITY_DETECT_INIT; + } + else + { + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + } + break; + + case AN_STATE_DISABLE_LINK_OK: + AnRet = AUTONEG_STATUS_DONE; + break; + + case AN_STATE_ABILITY_DETECT_INIT: + /* Note: in the state diagram, this variable is set to */ + /* mr_adv_ability<12>. Is this right?. */ + pAnInfo->mr_toggle_tx = AN_FALSE; + + /* Send the config as advertised in the advertisement register. */ + pAnInfo->TxConfig.AsUSHORT = 0; + pAnInfo->TxConfig.D5_FD = pAnInfo->mr_adv_full_duplex; + pAnInfo->TxConfig.D6_HD = pAnInfo->mr_adv_half_duplex; + pAnInfo->TxConfig.D7_PS1 = pAnInfo->mr_adv_sym_pause; + pAnInfo->TxConfig.D8_PS2 = pAnInfo->mr_adv_asym_pause; + pAnInfo->TxConfig.D12_RF1 = pAnInfo->mr_adv_remote_fault1; + pAnInfo->TxConfig.D13_RF2 = pAnInfo->mr_adv_remote_fault2; + pAnInfo->TxConfig.D15_NP = pAnInfo->mr_adv_next_page; + + MM_AnTxConfig(pAnInfo); + + pAnInfo->State = AN_STATE_ABILITY_DETECT; + + break; + + case AN_STATE_ABILITY_DETECT: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT != 0) + { + pAnInfo->State = AN_STATE_ACK_DETECT_INIT; + } + + break; + + case AN_STATE_ACK_DETECT_INIT: + pAnInfo->TxConfig.D14_ACK = 1; + MM_AnTxConfig(pAnInfo); + + pAnInfo->State = AN_STATE_ACK_DETECT; + + /* Fall through. */ + + case AN_STATE_ACK_DETECT: + if(pAnInfo->AckMatch == AN_TRUE) + { + if((pAnInfo->RxConfig.AsUSHORT & ~AN_CONFIG_ACK) == + (pAnInfo->AbilityMatchCfg & ~AN_CONFIG_ACK)) + { + pAnInfo->State = AN_STATE_COMPLETE_ACK_INIT; + } + else + { + pAnInfo->State = AN_STATE_AN_ENABLE; + } + } + else if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + } + + break; + + case AN_STATE_COMPLETE_ACK_INIT: + /* Make sure invalid bits are not set. */ + if(pAnInfo->RxConfig.bits.D0 || pAnInfo->RxConfig.bits.D1 || + pAnInfo->RxConfig.bits.D2 || pAnInfo->RxConfig.bits.D3 || + pAnInfo->RxConfig.bits.D4 || pAnInfo->RxConfig.bits.D9 || + pAnInfo->RxConfig.bits.D10 || pAnInfo->RxConfig.bits.D11) + { + AnRet = AUTONEG_STATUS_FAILED; + break; + } + + /* Set up the link partner advertisement register. */ + pAnInfo->mr_lp_adv_full_duplex = pAnInfo->RxConfig.D5_FD; + pAnInfo->mr_lp_adv_half_duplex = pAnInfo->RxConfig.D6_HD; + pAnInfo->mr_lp_adv_sym_pause = pAnInfo->RxConfig.D7_PS1; + pAnInfo->mr_lp_adv_asym_pause = pAnInfo->RxConfig.D8_PS2; + pAnInfo->mr_lp_adv_remote_fault1 = pAnInfo->RxConfig.D12_RF1; + pAnInfo->mr_lp_adv_remote_fault2 = pAnInfo->RxConfig.D13_RF2; + pAnInfo->mr_lp_adv_next_page = pAnInfo->RxConfig.D15_NP; + + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + + pAnInfo->mr_toggle_tx = !pAnInfo->mr_toggle_tx; + pAnInfo->mr_toggle_rx = pAnInfo->RxConfig.bits.D11; + pAnInfo->mr_np_rx = pAnInfo->RxConfig.D15_NP; + pAnInfo->mr_page_rx = AN_TRUE; + + pAnInfo->State = AN_STATE_COMPLETE_ACK; + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + break; + + case AN_STATE_COMPLETE_ACK: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + break; + } + + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { + if(pAnInfo->mr_adv_next_page == 0 || + pAnInfo->mr_lp_adv_next_page == 0) + { + pAnInfo->State = AN_STATE_IDLE_DETECT_INIT; + } + else + { + if(pAnInfo->TxConfig.bits.D15 == 0 && + pAnInfo->mr_np_rx == 0) + { + pAnInfo->State = AN_STATE_IDLE_DETECT_INIT; + } + else + { + AnRet = AUTONEG_STATUS_FAILED; + } + } + } + + break; + + case AN_STATE_IDLE_DETECT_INIT: + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + + MM_AnTxIdle(pAnInfo); + + pAnInfo->State = AN_STATE_IDLE_DETECT; + + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + break; + + case AN_STATE_IDLE_DETECT: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + break; + } + + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { +#if 0 +/* if(pAnInfo->IdleMatch == AN_TRUE) */ +/* { */ +#endif + pAnInfo->State = AN_STATE_LINK_OK; +#if 0 +/* } */ +/* else */ +/* { */ +/* AnRet = AUTONEG_STATUS_FAILED; */ +/* break; */ +/* } */ +#endif + } + + break; + + case AN_STATE_LINK_OK: + pAnInfo->mr_an_complete = AN_TRUE; + pAnInfo->mr_link_ok = AN_TRUE; + AnRet = AUTONEG_STATUS_DONE; + + break; + + case AN_STATE_NEXT_PAGE_WAIT_INIT: + break; + + case AN_STATE_NEXT_PAGE_WAIT: + break; + + default: + AnRet = AUTONEG_STATUS_FAILED; + break; + } + + return AnRet; +} +#endif /* INCLUDE_TBI_SUPPORT */ + +#endif /* !defined(CONFIG_NET_MULTI) */ diff --git a/drivers/bcm570x_autoneg.h b/drivers/bcm570x_autoneg.h new file mode 100644 index 000000000..7830944b8 --- /dev/null +++ b/drivers/bcm570x_autoneg.h @@ -0,0 +1,408 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2001 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ + + +#ifndef AUTONEG_H +#define AUTONEG_H + + +/******************************************************************************/ +/* Constants. */ +/******************************************************************************/ + +#define AN_LINK_TIMER_INTERVAL_US 9000 /* 10ms */ + +/* TRUE, FALSE */ +#define AN_TRUE 1 +#define AN_FALSE 0 + + +/******************************************************************************/ +/* Main data structure for keeping track of 802.3z auto-negotation state */ +/* variables as shown in Figure 37-6 of the IEEE 802.3z specification. */ +/******************************************************************************/ + +typedef struct +{ + /* Current auto-negotiation state. */ + unsigned long State; + #define AN_STATE_UNKNOWN 0 + #define AN_STATE_AN_ENABLE 1 + #define AN_STATE_AN_RESTART_INIT 2 + #define AN_STATE_AN_RESTART 3 + #define AN_STATE_DISABLE_LINK_OK 4 + #define AN_STATE_ABILITY_DETECT_INIT 5 + #define AN_STATE_ABILITY_DETECT 6 + #define AN_STATE_ACK_DETECT_INIT 7 + #define AN_STATE_ACK_DETECT 8 + #define AN_STATE_COMPLETE_ACK_INIT 9 + #define AN_STATE_COMPLETE_ACK 10 + #define AN_STATE_IDLE_DETECT_INIT 11 + #define AN_STATE_IDLE_DETECT 12 + #define AN_STATE_LINK_OK 13 + #define AN_STATE_NEXT_PAGE_WAIT_INIT 14 + #define AN_STATE_NEXT_PAGE_WAIT 16 + + /* Link timer. */ + unsigned long LinkTime_us; + + /* Current time. */ + unsigned long CurrentTime_us; + + /* Need these values for consistency check. */ + unsigned short AbilityMatchCfg; + + /* Ability, idle, and ack match functions. */ + unsigned long AbilityMatchCnt; + char AbilityMatch; + char IdleMatch; + char AckMatch; + + /* Tx config data */ + union + { + /* The TxConfig register is arranged as follows: */ + /* */ + /* MSB LSB */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + struct + { +#ifdef BIG_ENDIAN_HOST + unsigned int D7:1; /* PS1 */ + unsigned int D6:1; /* HD */ + unsigned int D5:1; /* FD */ + unsigned int D4:1; + unsigned int D3:1; + unsigned int D2:1; + unsigned int D1:1; + unsigned int D0:1; + unsigned int D15:1; /* NP */ + unsigned int D14:1; /* ACK */ + unsigned int D13:1; /* RF2 */ + unsigned int D12:1; /* RF1 */ + unsigned int D11:1; + unsigned int D10:1; + unsigned int D9:1; + unsigned int D8:1; /* PS2 */ +#else /* BIG_ENDIAN_HOST */ + unsigned int D8:1; /* PS2 */ + unsigned int D9:1; + unsigned int D10:1; + unsigned int D11:1; + unsigned int D12:1; /* RF1 */ + unsigned int D13:1; /* RF2 */ + unsigned int D14:1; /* ACK */ + unsigned int D15:1; /* NP */ + unsigned int D0:1; + unsigned int D1:1; + unsigned int D2:1; + unsigned int D3:1; + unsigned int D4:1; + unsigned int D5:1; /* FD */ + unsigned int D6:1; /* HD */ + unsigned int D7:1; /* PS1 */ +#endif + } bits; + + unsigned short AsUSHORT; + + #define D8_PS2 bits.D8 + #define D12_RF1 bits.D12 + #define D13_RF2 bits.D13 + #define D14_ACK bits.D14 + #define D15_NP bits.D15 + #define D5_FD bits.D5 + #define D6_HD bits.D6 + #define D7_PS1 bits.D7 + } TxConfig; + + /* Rx config data */ + union + { + /* The RxConfig register is arranged as follows: */ + /* */ + /* MSB LSB */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + struct + { +#ifdef BIG_ENDIAN_HOST + unsigned int D7:1; /* PS1 */ + unsigned int D6:1; /* HD */ + unsigned int D5:1; /* FD */ + unsigned int D4:1; + unsigned int D3:1; + unsigned int D2:1; + unsigned int D1:1; + unsigned int D0:1; + unsigned int D15:1; /* NP */ + unsigned int D14:1; /* ACK */ + unsigned int D13:1; /* RF2 */ + unsigned int D12:1; /* RF1 */ + unsigned int D11:1; + unsigned int D10:1; + unsigned int D9:1; + unsigned int D8:1; /* PS2 */ +#else /* BIG_ENDIAN_HOST */ + unsigned int D8:1; /* PS2 */ + unsigned int D9:1; + unsigned int D10:1; + unsigned int D11:1; + unsigned int D12:1; /* RF1 */ + unsigned int D13:1; /* RF2 */ + unsigned int D14:1; /* ACK */ + unsigned int D15:1; /* NP */ + unsigned int D0:1; + unsigned int D1:1; + unsigned int D2:1; + unsigned int D3:1; + unsigned int D4:1; + unsigned int D5:1; /* FD */ + unsigned int D6:1; /* HD */ + unsigned int D7:1; /* PS1 */ +#endif + } bits; + + unsigned short AsUSHORT; + } RxConfig; + + #define AN_CONFIG_NP 0x0080 + #define AN_CONFIG_ACK 0x0040 + #define AN_CONFIG_RF2 0x0020 + #define AN_CONFIG_RF1 0x0010 + #define AN_CONFIG_PS2 0x0001 + #define AN_CONFIG_PS1 0x8000 + #define AN_CONFIG_HD 0x4000 + #define AN_CONFIG_FD 0x2000 + + + /* Management registers. */ + + /* Control register. */ + union + { + struct + { + unsigned int an_enable:1; + unsigned int loopback:1; + unsigned int reset:1; + unsigned int restart_an:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_an_enable Mr0.bits.an_enable + #define mr_loopback Mr0.bits.loopback + #define mr_main_reset Mr0.bits.reset + #define mr_restart_an Mr0.bits.restart_an + } Mr0; + + /* Status register. */ + union + { + struct + { + unsigned int an_complete:1; + unsigned int link_ok:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_an_complete Mr1.bits.an_complete + #define mr_link_ok Mr1.bits.link_ok + } Mr1; + + /* Advertisement register. */ + union + { + struct + { + unsigned int reserved_4:5; + unsigned int full_duplex:1; + unsigned int half_duplex:1; + unsigned int sym_pause:1; + unsigned int asym_pause:1; + unsigned int reserved_11:3; + unsigned int remote_fault1:1; + unsigned int remote_fault2:1; + unsigned int reserved_14:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_adv_full_duplex Mr4.bits.full_duplex + #define mr_adv_half_duplex Mr4.bits.half_duplex + #define mr_adv_sym_pause Mr4.bits.sym_pause + #define mr_adv_asym_pause Mr4.bits.asym_pause + #define mr_adv_remote_fault1 Mr4.bits.remote_fault1 + #define mr_adv_remote_fault2 Mr4.bits.remote_fault2 + #define mr_adv_next_page Mr4.bits.next_page + } Mr4; + + /* Link partner advertisement register. */ + union + { + struct + { + unsigned int reserved_4:5; + unsigned int lp_full_duplex:1; + unsigned int lp_half_duplex:1; + unsigned int lp_sym_pause:1; + unsigned int lp_asym_pause:1; + unsigned int reserved_11:3; + unsigned int lp_remote_fault1:1; + unsigned int lp_remote_fault2:1; + unsigned int lp_ack:1; + unsigned int lp_next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_lp_adv_full_duplex Mr5.bits.lp_full_duplex + #define mr_lp_adv_half_duplex Mr5.bits.lp_half_duplex + #define mr_lp_adv_sym_pause Mr5.bits.lp_sym_pause + #define mr_lp_adv_asym_pause Mr5.bits.lp_asym_pause + #define mr_lp_adv_remote_fault1 Mr5.bits.lp_remote_fault1 + #define mr_lp_adv_remote_fault2 Mr5.bits.lp_remote_fault2 + #define mr_lp_adv_next_page Mr5.bits.lp_next_page + } Mr5; + + /* Auto-negotiation expansion register. */ + union + { + struct + { + unsigned int reserved_0:1; + unsigned int page_received:1; + unsigned int next_pageable:1; + unsigned int reserved_15:13; + } bits; + + unsigned short AsUSHORT; + } Mr6; + + /* Auto-negotiation next page transmit register. */ + union + { + struct + { + unsigned int code_field:11; + unsigned int toggle:1; + unsigned int ack2:1; + unsigned int message_page:1; + unsigned int reserved_14:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_np_tx Mr7.AsUSHORT + } Mr7; + + /* Auto-negotiation link partner ability register. */ + union + { + struct + { + unsigned int code_field:11; + unsigned int toggle:1; + unsigned int ack2:1; + unsigned int message_page:1; + unsigned int ack:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_lp_np_rx Mr8.AsUSHORT + } Mr8; + + /* Extended status register. */ + union + { + struct + { + unsigned int reserved_11:12; + unsigned int base1000_t_hd:1; + unsigned int base1000_t_fd:1; + unsigned int base1000_x_hd:1; + unsigned int base1000_x_fd:1; + } bits; + + unsigned short AsUSHORT; + } Mr15; + + /* Miscellaneous state variables. */ + union + { + struct + { + unsigned int toggle_tx:1; + unsigned int toggle_rx:1; + unsigned int np_rx:1; + unsigned int page_rx:1; + unsigned int np_loaded:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_toggle_tx MrMisc.bits.toggle_tx + #define mr_toggle_rx MrMisc.bits.toggle_rx + #define mr_np_rx MrMisc.bits.np_rx + #define mr_page_rx MrMisc.bits.page_rx + #define mr_np_loaded MrMisc.bits.np_loaded + } MrMisc; + + + /* Implement specifics */ + + /* Pointer to the operating system specific data structure. */ + void *pContext; +} AN_STATE_INFO, *PAN_STATE_INFO; + + +/******************************************************************************/ +/* Return code of Autoneg8023z. */ +/******************************************************************************/ + +typedef enum +{ + AUTONEG_STATUS_OK = 0, + AUTONEG_STATUS_DONE = 1, + AUTONEG_STATUS_TIMER_ENABLED = 2, + AUTONEG_STATUS_FAILED = 0xfffffff +} AUTONEG_STATUS, *PAUTONEG_STATUS; + + +/******************************************************************************/ +/* Function prototypes. */ +/******************************************************************************/ + +AUTONEG_STATUS Autoneg8023z(PAN_STATE_INFO pAnInfo); +void AutonegInit(PAN_STATE_INFO pAnInfo); + + +/******************************************************************************/ +/* The following functions are defined in the os-dependent module. */ +/******************************************************************************/ + +void MM_AnTxConfig(PAN_STATE_INFO pAnInfo); +void MM_AnTxIdle(PAN_STATE_INFO pAnInfo); +char MM_AnRxConfig(PAN_STATE_INFO pAnInfo, unsigned short *pRxConfig); + + +#endif /* AUTONEG_H */ diff --git a/drivers/bcm570x_bits.h b/drivers/bcm570x_bits.h new file mode 100644 index 000000000..615d61e98 --- /dev/null +++ b/drivers/bcm570x_bits.h @@ -0,0 +1,57 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef BITS_H +#define BITS_H + + +/******************************************************************************/ +/* Bit Mask definitions */ +/******************************************************************************/ +#define BIT_NONE 0x00 +#define BIT_0 0x01 +#define BIT_1 0x02 +#define BIT_2 0x04 +#define BIT_3 0x08 +#define BIT_4 0x10 +#define BIT_5 0x20 +#define BIT_6 0x40 +#define BIT_7 0x80 +#define BIT_8 0x0100 +#define BIT_9 0x0200 +#define BIT_10 0x0400 +#define BIT_11 0x0800 +#define BIT_12 0x1000 +#define BIT_13 0x2000 +#define BIT_14 0x4000 +#define BIT_15 0x8000 +#define BIT_16 0x010000 +#define BIT_17 0x020000 +#define BIT_18 0x040000 +#define BIT_19 0x080000 +#define BIT_20 0x100000 +#define BIT_21 0x200000 +#define BIT_22 0x400000 +#define BIT_23 0x800000 +#define BIT_24 0x01000000 +#define BIT_25 0x02000000 +#define BIT_26 0x04000000 +#define BIT_27 0x08000000 +#define BIT_28 0x10000000 +#define BIT_29 0x20000000 +#define BIT_30 0x40000000 +#define BIT_31 0x80000000 + +#endif /* BITS_H */ diff --git a/drivers/bcm570x_debug.h b/drivers/bcm570x_debug.h new file mode 100644 index 000000000..88e209b0f --- /dev/null +++ b/drivers/bcm570x_debug.h @@ -0,0 +1,109 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef DEBUG_H +#define DEBUG_H + +#ifdef VXWORKS +#include +#endif + +/******************************************************************************/ +/* Debug macros */ +/******************************************************************************/ + +/* Code path for controlling output debug messages. */ +/* Define your code path here. */ +#define CP_INIT 0x010000 +#define CP_SEND 0x020000 +#define CP_RCV 0x040000 +#define CP_INT 0x080000 +#define CP_UINIT 0x100000 +#define CP_RESET 0x200000 + +#define CP_ALL (CP_INIT | CP_SEND | CP_RCV | CP_INT | \ + CP_RESET | CP_UINIT) + +#define CP_MASK 0xffff0000 + + +/* Debug message levels. */ +#define LV_VERBOSE 0x03 +#define LV_INFORM 0x02 +#define LV_WARN 0x01 +#define LV_FATAL 0x00 + +#define LV_MASK 0xffff + + +/* Code path and messsage level combined. These are the first argument of */ +/* the DbgMessage macro. */ +#define INIT_V (CP_INIT | LV_VERBOSE) +#define INIT_I (CP_INIT | LV_INFORM) +#define INIT_W (CP_INIT | LV_WARN) +#define SEND_V (CP_SEND | LV_VERBOSE) +#define SEND_I (CP_SEND | LV_INFORM) +#define SEND_W (CP_SEND | LV_WARN) +#define RCV_V (CP_RCV | LV_VERBOSE) +#define RCV_I (CP_RCV | LV_INFORM) +#define RCV_W (CP_RCV | LV_WARN) +#define INT_V (CP_INT | LV_VERBOSE) +#define INT_I (CP_INT | LV_INFORM) +#define INT_W (CP_INT | LV_WARN) +#define UINIT_V (CP_UINIT | LV_VERBOSE) +#define UINIT_I (CP_UINIT | LV_INFORM) +#define UINIT_W (CP_UINIT | LV_WARN) +#define RESET_V (CP_RESET | LV_VERBOSE) +#define RESET_I (CP_RESET | LV_INFORM) +#define RESET_W (CP_RESET | LV_WARN) +#define CPALL_V (CP_ALL | LV_VERBOSE) +#define CPALL_I (CP_ALL | LV_INFORM) +#define CPALL_W (CP_ALL | LV_WARN) + + +/* All code path message levels. */ +#define FATAL (CP_ALL | LV_FATAL) +#define WARN (CP_ALL | LV_WARN) +#define INFORM (CP_ALL | LV_INFORM) +#define VERBOSE (CP_ALL | LV_VERBOSE) + + +/* These constants control the message output. */ +/* Set your debug message output level and code path here. */ +#ifndef DBG_MSG_CP +#define DBG_MSG_CP CP_ALL /* Where to output messages. */ +#endif + +#ifndef DBG_MSG_LV +#define DBG_MSG_LV LV_VERBOSE /* Level of message output. */ +#endif + +/* DbgMessage macro. */ +#if DBG +#define DbgMessage(CNTRL, MESSAGE) \ + if((CNTRL & DBG_MSG_CP) && ((CNTRL & LV_MASK) <= DBG_MSG_LV)) \ + printf MESSAGE +#define DbgBreak() DbgBreakPoint() +#undef STATIC +#define STATIC +#else +#define DbgMessage(CNTRL, MESSAGE) +#define DbgBreak() +#undef STATIC +#define STATIC static +#endif /* DBG */ + + +#endif /* DEBUG_H */ diff --git a/drivers/bcm570x_lm.h b/drivers/bcm570x_lm.h new file mode 100644 index 000000000..607f3fd06 --- /dev/null +++ b/drivers/bcm570x_lm.h @@ -0,0 +1,451 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef LM_H +#define LM_H + +#include "bcm570x_queue.h" +#include "bcm570x_bits.h" + + +/******************************************************************************/ +/* Basic types. */ +/******************************************************************************/ + +typedef char LM_CHAR, *PLM_CHAR; +typedef unsigned int LM_UINT, *PLM_UINT; +typedef unsigned char LM_UINT8, *PLM_UINT8; +typedef unsigned short LM_UINT16, *PLM_UINT16; +typedef unsigned int LM_UINT32, *PLM_UINT32; +typedef unsigned int LM_COUNTER, *PLM_COUNTER; +typedef void LM_VOID, *PLM_VOID; +typedef char LM_BOOL, *PLM_BOOL; + +/* 64bit value. */ +typedef struct { +#ifdef BIG_ENDIAN_HOST + LM_UINT32 High; + LM_UINT32 Low; +#else /* BIG_ENDIAN_HOST */ + LM_UINT32 Low; + LM_UINT32 High; +#endif /* !BIG_ENDIAN_HOST */ +} LM_UINT64, *PLM_UINT64; + +typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; + +/* void LM_INC_PHYSICAL_ADDRESS(PLM_PHYSICAL_ADDRESS pAddr,LM_UINT32 IncSize) */ +#define LM_INC_PHYSICAL_ADDRESS(pAddr, IncSize) \ + { \ + LM_UINT32 OrgLow; \ + \ + OrgLow = (pAddr)->Low; \ + (pAddr)->Low += IncSize; \ + if((pAddr)->Low < OrgLow) { \ + (pAddr)->High++; /* Wrap around. */ \ + } \ + } + + +#ifndef NULL +#define NULL ((void *) 0) +#endif /* NULL */ + +#ifndef OFFSETOF +#define OFFSETOF(_s, _m) (MM_UINT_PTR(&(((_s *) 0)->_m))) +#endif /* OFFSETOF */ + + +/******************************************************************************/ +/* Simple macros. */ +/******************************************************************************/ + +#define IS_ETH_BROADCAST(_pEthAddr) \ + (((unsigned char *) (_pEthAddr))[0] == ((unsigned char) 0xff)) + +#define IS_ETH_MULTICAST(_pEthAddr) \ + (((unsigned char *) (_pEthAddr))[0] & ((unsigned char) 0x01)) + +#define IS_ETH_ADDRESS_EQUAL(_pEtherAddr1, _pEtherAddr2) \ + ((((unsigned char *) (_pEtherAddr1))[0] == \ + ((unsigned char *) (_pEtherAddr2))[0]) && \ + (((unsigned char *) (_pEtherAddr1))[1] == \ + ((unsigned char *) (_pEtherAddr2))[1]) && \ + (((unsigned char *) (_pEtherAddr1))[2] == \ + ((unsigned char *) (_pEtherAddr2))[2]) && \ + (((unsigned char *) (_pEtherAddr1))[3] == \ + ((unsigned char *) (_pEtherAddr2))[3]) && \ + (((unsigned char *) (_pEtherAddr1))[4] == \ + ((unsigned char *) (_pEtherAddr2))[4]) && \ + (((unsigned char *) (_pEtherAddr1))[5] == \ + ((unsigned char *) (_pEtherAddr2))[5])) + +#define COPY_ETH_ADDRESS(_Src, _Dst) \ + ((unsigned char *) (_Dst))[0] = ((unsigned char *) (_Src))[0]; \ + ((unsigned char *) (_Dst))[1] = ((unsigned char *) (_Src))[1]; \ + ((unsigned char *) (_Dst))[2] = ((unsigned char *) (_Src))[2]; \ + ((unsigned char *) (_Dst))[3] = ((unsigned char *) (_Src))[3]; \ + ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4]; \ + ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5]; + + +/******************************************************************************/ +/* Constants. */ +/******************************************************************************/ + +#define ETHERNET_ADDRESS_SIZE 6 +#define ETHERNET_PACKET_HEADER_SIZE 14 +#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */ +#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */ +#define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60 +#define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514 +#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */ + +#ifndef LM_MAX_MC_TABLE_SIZE +#define LM_MAX_MC_TABLE_SIZE 32 +#endif /* LM_MAX_MC_TABLE_SIZE */ +#define LM_MC_ENTRY_SIZE (ETHERNET_ADDRESS_SIZE+1) +#define LM_MC_INSTANCE_COUNT_INDEX (LM_MC_ENTRY_SIZE-1) + + +/* Receive filter masks. */ +#define LM_ACCEPT_UNICAST 0x0001 +#define LM_ACCEPT_MULTICAST 0x0002 +#define LM_ACCEPT_ALL_MULTICAST 0x0004 +#define LM_ACCEPT_BROADCAST 0x0008 +#define LM_ACCEPT_ERROR_PACKET 0x0010 + +#define LM_PROMISCUOUS_MODE 0x10000 + + +/******************************************************************************/ +/* PCI registers. */ +/******************************************************************************/ + +#define PCI_VENDOR_ID_REG 0x00 +#define PCI_DEVICE_ID_REG 0x02 + +#define PCI_COMMAND_REG 0x04 +#define PCI_IO_SPACE_ENABLE 0x0001 +#define PCI_MEM_SPACE_ENABLE 0x0002 +#define PCI_BUSMASTER_ENABLE 0x0004 +#define PCI_MEMORY_WRITE_INVALIDATE 0x0010 +#define PCI_PARITY_ERROR_ENABLE 0x0040 +#define PCI_SYSTEM_ERROR_ENABLE 0x0100 +#define PCI_FAST_BACK_TO_BACK_ENABLE 0x0200 + +#define PCI_STATUS_REG 0x06 +#define PCI_REV_ID_REG 0x08 + +#define PCI_CACHE_LINE_SIZE_REG 0x0c + +#define PCI_IO_BASE_ADDR_REG 0x10 +#define PCI_IO_BASE_ADDR_MASK 0xfffffff0 + +#define PCI_MEM_BASE_ADDR_LOW 0x10 +#define PCI_MEM_BASE_ADDR_HIGH 0x14 + +#define PCI_SUBSYSTEM_VENDOR_ID_REG 0x2c +#define PCI_SUBSYSTEM_ID_REG 0x2e +#define PCI_INT_LINE_REG 0x3c + +#define PCIX_CAP_REG 0x40 +#define PCIX_ENABLE_RELAXED_ORDERING BIT_17 + +/******************************************************************************/ +/* Fragment structure. */ +/******************************************************************************/ + +typedef struct { + LM_UINT32 FragSize; + LM_PHYSICAL_ADDRESS FragBuf; +} LM_FRAG, *PLM_FRAG; + +typedef struct { + /* FragCount is initialized for the caller to the maximum array size, on */ + /* return FragCount is the number of the actual fragments in the array. */ + LM_UINT32 FragCount; + + /* Total buffer size. */ + LM_UINT32 TotalSize; + + /* Fragment array buffer. */ + LM_FRAG Fragments[1]; +} LM_FRAG_LIST, *PLM_FRAG_LIST; + +#define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \ + typedef struct { \ + LM_FRAG_LIST FragList; \ + LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \ + } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME + + +/******************************************************************************/ +/* Status codes. */ +/******************************************************************************/ + +#define LM_STATUS_SUCCESS 0 +#define LM_STATUS_FAILURE 1 + +#define LM_STATUS_INTERRUPT_ACTIVE 2 +#define LM_STATUS_INTERRUPT_NOT_ACTIVE 3 + +#define LM_STATUS_LINK_ACTIVE 4 +#define LM_STATUS_LINK_DOWN 5 +#define LM_STATUS_LINK_SETTING_MISMATCH 6 + +#define LM_STATUS_TOO_MANY_FRAGMENTS 7 +#define LM_STATUS_TRANSMIT_ABORTED 8 +#define LM_STATUS_TRANSMIT_ERROR 9 +#define LM_STATUS_RECEIVE_ABORTED 10 +#define LM_STATUS_RECEIVE_ERROR 11 +#define LM_STATUS_INVALID_PACKET_SIZE 12 +#define LM_STATUS_OUT_OF_MAP_REGISTERS 13 +#define LM_STATUS_UNKNOWN_ADAPTER 14 + +typedef LM_UINT LM_STATUS, *PLM_STATUS; + + +/******************************************************************************/ +/* Requested media type. */ +/******************************************************************************/ + +#define LM_REQUESTED_MEDIA_TYPE_AUTO 0 +#define LM_REQUESTED_MEDIA_TYPE_BNC 1 +#define LM_REQUESTED_MEDIA_TYPE_UTP_AUTO 2 +#define LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS 3 +#define LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX 4 +#define LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS 5 +#define LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX 6 +#define LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS 7 +#define LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX 8 +#define LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS 9 +#define LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX 10 +#define LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS 11 +#define LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX 12 +#define LM_REQUESTED_MEDIA_TYPE_MAC_LOOPBACK 0xfffe +#define LM_REQUESTED_MEDIA_TYPE_PHY_LOOPBACK 0xffff + +typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE; + + +/******************************************************************************/ +/* Media type. */ +/******************************************************************************/ + +#define LM_MEDIA_TYPE_UNKNOWN -1 +#define LM_MEDIA_TYPE_AUTO 0 +#define LM_MEDIA_TYPE_UTP 1 +#define LM_MEDIA_TYPE_BNC 2 +#define LM_MEDIA_TYPE_AUI 3 +#define LM_MEDIA_TYPE_FIBER 4 + +typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE; + + +/******************************************************************************/ +/* Line speed. */ +/******************************************************************************/ + +#define LM_LINE_SPEED_UNKNOWN 0 +#define LM_LINE_SPEED_10MBPS 1 +#define LM_LINE_SPEED_100MBPS 2 +#define LM_LINE_SPEED_1000MBPS 3 + +typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED; + + +/******************************************************************************/ +/* Duplex mode. */ +/******************************************************************************/ + +#define LM_DUPLEX_MODE_UNKNOWN 0 +#define LM_DUPLEX_MODE_HALF 1 +#define LM_DUPLEX_MODE_FULL 2 + +typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE; + + +/******************************************************************************/ +/* Power state. */ +/******************************************************************************/ + +#define LM_POWER_STATE_D0 0 +#define LM_POWER_STATE_D1 1 +#define LM_POWER_STATE_D2 2 +#define LM_POWER_STATE_D3 3 + +typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE; + + +/******************************************************************************/ +/* Task offloading. */ +/******************************************************************************/ + +#define LM_TASK_OFFLOAD_NONE 0x0000 +#define LM_TASK_OFFLOAD_TX_IP_CHECKSUM 0x0001 +#define LM_TASK_OFFLOAD_RX_IP_CHECKSUM 0x0002 +#define LM_TASK_OFFLOAD_TX_TCP_CHECKSUM 0x0004 +#define LM_TASK_OFFLOAD_RX_TCP_CHECKSUM 0x0008 +#define LM_TASK_OFFLOAD_TX_UDP_CHECKSUM 0x0010 +#define LM_TASK_OFFLOAD_RX_UDP_CHECKSUM 0x0020 +#define LM_TASK_OFFLOAD_TCP_SEGMENTATION 0x0040 + +typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD; + + +/******************************************************************************/ +/* Flow control. */ +/******************************************************************************/ + +#define LM_FLOW_CONTROL_NONE 0x00 +#define LM_FLOW_CONTROL_RECEIVE_PAUSE 0x01 +#define LM_FLOW_CONTROL_TRANSMIT_PAUSE 0x02 +#define LM_FLOW_CONTROL_RX_TX_PAUSE (LM_FLOW_CONTROL_RECEIVE_PAUSE | \ + LM_FLOW_CONTROL_TRANSMIT_PAUSE) + +/* This value can be or-ed with RECEIVE_PAUSE and TRANSMIT_PAUSE. If the */ +/* auto-negotiation is disabled and the RECEIVE_PAUSE and TRANSMIT_PAUSE */ +/* bits are set, then flow control is enabled regardless of link partner's */ +/* flow control capability. */ +#define LM_FLOW_CONTROL_AUTO_PAUSE 0x80000000 + +typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL; + + +/******************************************************************************/ +/* Wake up mode. */ +/******************************************************************************/ + +#define LM_WAKE_UP_MODE_NONE 0 +#define LM_WAKE_UP_MODE_MAGIC_PACKET 1 +#define LM_WAKE_UP_MODE_NWUF 2 +#define LM_WAKE_UP_MODE_LINK_CHANGE 4 + +typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE; + + +/******************************************************************************/ +/* Counters. */ +/******************************************************************************/ + +#define LM_COUNTER_FRAMES_XMITTED_OK 0 +#define LM_COUNTER_FRAMES_RECEIVED_OK 1 +#define LM_COUNTER_ERRORED_TRANSMIT_COUNT 2 +#define LM_COUNTER_ERRORED_RECEIVE_COUNT 3 +#define LM_COUNTER_RCV_CRC_ERROR 4 +#define LM_COUNTER_ALIGNMENT_ERROR 5 +#define LM_COUNTER_SINGLE_COLLISION_FRAMES 6 +#define LM_COUNTER_MULTIPLE_COLLISION_FRAMES 7 +#define LM_COUNTER_FRAMES_DEFERRED 8 +#define LM_COUNTER_MAX_COLLISIONS 9 +#define LM_COUNTER_RCV_OVERRUN 10 +#define LM_COUNTER_XMIT_UNDERRUN 11 +#define LM_COUNTER_UNICAST_FRAMES_XMIT 12 +#define LM_COUNTER_MULTICAST_FRAMES_XMIT 13 +#define LM_COUNTER_BROADCAST_FRAMES_XMIT 14 +#define LM_COUNTER_UNICAST_FRAMES_RCV 15 +#define LM_COUNTER_MULTICAST_FRAMES_RCV 16 +#define LM_COUNTER_BROADCAST_FRAMES_RCV 17 + +typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE; + + +/******************************************************************************/ +/* Forward definition. */ +/******************************************************************************/ + +typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK; +typedef struct _LM_PACKET *PLM_PACKET; + + +/******************************************************************************/ +/* Function prototypes. */ +/******************************************************************************/ + +LM_STATUS LM_GetAdapterInfo(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_InitializeAdapter(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_ResetAdapter(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_DisableInterrupt(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_EnableInterrupt(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS LM_ServiceInterrupts(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask); +LM_STATUS LM_Halt(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_MulticastAdd(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); +LM_STATUS LM_MulticastDel(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress); +LM_STATUS LM_MulticastClear(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetMacAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress); +LM_STATUS LM_LoopbackAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress); + +LM_UINT32 LM_GetCrcCounter(PLM_DEVICE_BLOCK pDevice); + +LM_WAKE_UP_MODE LM_PMCapabilities(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_NwufAdd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, + LM_UINT8 *pByteMask, LM_UINT8 *pPattern); +LM_STATUS LM_NwufRemove(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize, + LM_UINT8 *pByteMask, LM_UINT8 *pPattern); +LM_STATUS LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel); + +LM_VOID LM_ReadPhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, + PLM_UINT32 pData32); +LM_VOID LM_WritePhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, + LM_UINT32 Data32); + +LM_STATUS LM_ControlLoopBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control); +LM_STATUS LM_SetupPhy(PLM_DEVICE_BLOCK pDevice); +int LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration); + + +/******************************************************************************/ +/* These are the OS specific functions called by LMAC. */ +/******************************************************************************/ + +LM_STATUS MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 *pValue16); +LM_STATUS MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT16 Value16); +LM_STATUS MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 *pValue32); +LM_STATUS MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, + LM_UINT32 Value32); +LM_STATUS MM_MapMemBase(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_MapIoBase(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt); +LM_STATUS MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, + PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, + LM_BOOL Cached); +LM_STATUS MM_GetConfig(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status); +LM_STATUS MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice); +LM_STATUS MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket); +LM_STATUS LM_MbufWorkAround(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_SetLinkSpeed(PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType); + +#if INCLUDE_5703_A0_FIX +LM_STATUS LM_Load5703DmaWFirmware(PLM_DEVICE_BLOCK pDevice); +#endif + + +#endif /* LM_H */ diff --git a/drivers/bcm570x_mm.h b/drivers/bcm570x_mm.h new file mode 100644 index 000000000..b7cbf8abd --- /dev/null +++ b/drivers/bcm570x_mm.h @@ -0,0 +1,160 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/******************************************************************************/ + +#ifndef MM_H +#define MM_H + +#define __raw_readl readl +#define __raw_writel writel + +#define BIG_ENDIAN_HOST 1 +#define readl(addr) (*(volatile unsigned int*)(addr)) +#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) + +/* Define memory barrier function here if needed */ +#define wmb() +#define membar() +#include +#include +#include "bcm570x_lm.h" +#include "bcm570x_queue.h" +#include "tigon3.h" +#include + +#define FALSE 0 +#define TRUE 1 +#define ERROR -1 + +#if DBG +#define STATIC +#else +#define STATIC static +#endif + +extern int MM_Packet_Desc_Size; + +#define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size + +DECLARE_QUEUE_TYPE(UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT+1); + +#define MAX_MEM 16 + +/* Synch */ +typedef int mutex_t; +typedef int spinlock_t; + +/* Embedded device control */ +typedef struct _UM_DEVICE_BLOCK { + LM_DEVICE_BLOCK lm_dev; + pci_dev_t pdev; + char *name; + void *mem_list[MAX_MEM]; + dma_addr_t dma_list[MAX_MEM]; + int mem_size_list[MAX_MEM]; + int mem_list_num; + int mtu; + int index; + int opened; + int delayed_link_ind; /* Delay link status during initial load */ + int adapter_just_inited; /* the first few seconds after init. */ + int spurious_int; /* new -- unsupported */ + int timer_interval; + int adaptive_expiry; + int crc_counter_expiry; /* new -- unsupported */ + int poll_tib_expiry; /* new -- unsupported */ + int tx_full; + int tx_queued; + int line_speed; /* in Mbps, 0 if link is down */ + UM_RX_PACKET_Q rx_out_of_buf_q; + int rx_out_of_buf; + int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */ + int rx_buf_repl_panic_thresh; + int rx_buf_align; /* new -- unsupported */ + int do_global_lock; + mutex_t global_lock; + mutex_t undi_lock; + long undi_flags; + volatile int interrupt; + int tasklet_pending; + int tasklet_busy; /* new -- unsupported */ + int rx_pkt; + int tx_pkt; +#ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */ + void (*nice_rx)(void*, void* ); + void* nice_ctx; +#endif /* NICE_SUPPORT */ + int rx_adaptive_coalesce; + unsigned int rx_last_cnt; + unsigned int tx_last_cnt; + unsigned int rx_curr_coalesce_frames; + unsigned int rx_curr_coalesce_ticks; + unsigned int tx_curr_coalesce_frames; /* new -- unsupported */ +#if TIGON3_DEBUG /* new -- unsupported */ + uint tx_zc_count; + uint tx_chksum_count; + uint tx_himem_count; + uint rx_good_chksum_count; +#endif + unsigned int rx_bad_chksum_count; /* new -- unsupported */ + unsigned int rx_misc_errors; /* new -- unsupported */ +} UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK; + + +/* Physical/PCI DMA address */ +typedef union { + dma_addr_t dma_map; +} dma_map_t; + +/* Packet */ +typedef struct +_UM_PACKET { + LM_PACKET lm_packet; + void* skbuff; /* Address of packet buffer */ +} UM_PACKET, *PUM_PACKET; + +#define MM_ACQUIRE_UNDI_LOCK(_pDevice) +#define MM_RELEASE_UNDI_LOCK(_pDevice) +#define MM_ACQUIRE_INT_LOCK(_pDevice) +#define MM_RELEASE_INT_LOCK(_pDevice) +#define MM_UINT_PTR(_ptr) ((unsigned long) (_ptr)) + +/* Macro for setting 64bit address struct */ +#define set_64bit_addr(paddr, low, high) \ + (paddr)->Low = low; \ + (paddr)->High = high; + +/* Assume that PCI controller's view of host memory is same as host */ + +#define MEM_TO_PCI_PHYS(addr) (addr) + +extern void MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr); +extern void MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr); +extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR *paddr, + LM_UINT32 *len, int frag); +extern void MM_MapRxDma ( PLM_DEVICE_BLOCK pDevice, + struct _LM_PACKET *pPacket, + T3_64BIT_HOST_ADDR *paddr); + + +/* BSP needs to provide sysUsecDelay and sysSerialPrintString */ +extern void sysSerialPrintString (char *s); +#define MM_Wait(usec) udelay(usec) + +/* Define memory barrier function here if needed */ +#define wmb() + +#if 0 +#define cpu_to_le32(val) LONGSWAP(val) +#endif +#endif /* MM_H */ diff --git a/drivers/bcm570x_queue.h b/drivers/bcm570x_queue.h new file mode 100644 index 000000000..336b3caa4 --- /dev/null +++ b/drivers/bcm570x_queue.h @@ -0,0 +1,387 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* Queue functions. */ +/* void QQ_InitQueue(PQQ_CONTAINER pQueue) */ +/* char QQ_Full(PQQ_CONTAINER pQueue) */ +/* char QQ_Empty(PQQ_CONTAINER pQueue) */ +/* unsigned int QQ_GetSize(PQQ_CONTAINER pQueue) */ +/* unsigned int QQ_GetEntryCnt(PQQ_CONTAINER pQueue) */ +/* char QQ_PushHead(PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) */ +/* char QQ_PushTail(PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry) */ +/* PQQ_ENTRY QQ_PopHead(PQQ_CONTAINER pQueue) */ +/* PQQ_ENTRY QQ_PopTail(PQQ_CONTAINER pQueue) */ +/* PQQ_ENTRY QQ_GetHead(PQQ_CONTAINER pQueue, unsigned int Idx) */ +/* PQQ_ENTRY QQ_GetTail(PQQ_CONTAINER pQueue, unsigned int Idx) */ +/* */ +/* */ +/* History: */ +/* 02/25/00 Hav Khauv Initial version. */ +/******************************************************************************/ + +#ifndef BCM_QUEUE_H +#define BCM_QUEUE_H +#ifndef EMBEDDED +#define EMBEDDED 1 +#endif + +/******************************************************************************/ +/* Queue definitions. */ +/******************************************************************************/ + +/* Entry for queueing. */ +typedef void *PQQ_ENTRY; + +/* Linux Atomic Ops support */ +typedef struct { int counter; } atomic_t; + + +/* + * This combination of `inline' and `extern' has almost the effect of a + * macro. The way to use it is to put a function definition in a header + * file with these keywords, and put another copy of the definition + * (lacking `inline' and `extern') in a library file. The definition in + * the header file will cause most calls to the function to be inlined. + * If any uses of the function remain, they will refer to the single copy + * in the library. + */ +extern __inline void +atomic_set(atomic_t* entry, int val) +{ + entry->counter = val; +} +extern __inline int +atomic_read(atomic_t* entry) +{ + return entry->counter; +} +extern __inline void +atomic_inc(atomic_t* entry) +{ + if(entry) + entry->counter++; +} + +extern __inline void +atomic_dec(atomic_t* entry) +{ + if(entry) + entry->counter--; +} + +extern __inline void +atomic_sub(int a, atomic_t* entry) +{ + if(entry) + entry->counter -= a; +} +extern __inline void +atomic_add(int a, atomic_t* entry) +{ + if(entry) + entry->counter += a; +} + + +/* Queue header -- base type. */ +typedef struct { + unsigned int Head; + unsigned int Tail; + unsigned int Size; + atomic_t EntryCnt; + PQQ_ENTRY Array[1]; +} QQ_CONTAINER, *PQQ_CONTAINER; + + +/* Declare queue type macro. */ +#define DECLARE_QUEUE_TYPE(_QUEUE_TYPE, _QUEUE_SIZE) \ + \ + typedef struct { \ + QQ_CONTAINER Container; \ + PQQ_ENTRY EntryBuffer[_QUEUE_SIZE]; \ + } _QUEUE_TYPE, *P##_QUEUE_TYPE + + +/******************************************************************************/ +/* Compilation switches. */ +/******************************************************************************/ + +#if DBG +#undef QQ_NO_OVERFLOW_CHECK +#undef QQ_NO_UNDERFLOW_CHECK +#endif /* DBG */ + +#ifdef QQ_USE_MACROS +/* notdone */ +#else + +#ifdef QQ_NO_INLINE +#define __inline +#endif /* QQ_NO_INLINE */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline void +QQ_InitQueue( +PQQ_CONTAINER pQueue, +unsigned int QueueSize) { + pQueue->Head = 0; + pQueue->Tail = 0; + pQueue->Size = QueueSize+1; + atomic_set(&pQueue->EntryCnt, 0); +} /* QQ_InitQueue */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline char +QQ_Full( +PQQ_CONTAINER pQueue) { + unsigned int NewHead; + + NewHead = (pQueue->Head + 1) % pQueue->Size; + + return(NewHead == pQueue->Tail); +} /* QQ_Full */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline char +QQ_Empty( +PQQ_CONTAINER pQueue) { + return(pQueue->Head == pQueue->Tail); +} /* QQ_Empty */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline unsigned int +QQ_GetSize( +PQQ_CONTAINER pQueue) { + return pQueue->Size; +} /* QQ_GetSize */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline unsigned int +QQ_GetEntryCnt( +PQQ_CONTAINER pQueue) { + return atomic_read(&pQueue->EntryCnt); +} /* QQ_GetEntryCnt */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* TRUE entry was added successfully. */ +/* FALSE queue is full. */ +/******************************************************************************/ +extern __inline char +QQ_PushHead( +PQQ_CONTAINER pQueue, +PQQ_ENTRY pEntry) { + unsigned int Head; + + Head = (pQueue->Head + 1) % pQueue->Size; + +#if !defined(QQ_NO_OVERFLOW_CHECK) + if(Head == pQueue->Tail) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ + + pQueue->Array[pQueue->Head] = pEntry; + wmb(); + pQueue->Head = Head; + atomic_inc(&pQueue->EntryCnt); + + return -1; +} /* QQ_PushHead */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* TRUE entry was added successfully. */ +/* FALSE queue is full. */ +/******************************************************************************/ +extern __inline char +QQ_PushTail( +PQQ_CONTAINER pQueue, +PQQ_ENTRY pEntry) { + unsigned int Tail; + + Tail = pQueue->Tail; + if(Tail == 0) { + Tail = pQueue->Size; + } /* if */ + Tail--; + +#if !defined(QQ_NO_OVERFLOW_CHECK) + if(Tail == pQueue->Head) { + return 0; + } /* if */ +#endif /* QQ_NO_OVERFLOW_CHECK */ + + pQueue->Array[Tail] = pEntry; + wmb(); + pQueue->Tail = Tail; + atomic_inc(&pQueue->EntryCnt); + + return -1; +} /* QQ_PushTail */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline PQQ_ENTRY +QQ_PopHead( +PQQ_CONTAINER pQueue) { + unsigned int Head; + PQQ_ENTRY Entry; + + Head = pQueue->Head; + +#if !defined(QQ_NO_UNDERFLOW_CHECK) + if(Head == pQueue->Tail) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ + + if(Head == 0) { + Head = pQueue->Size; + } /* if */ + Head--; + + Entry = pQueue->Array[Head]; +#ifdef EMBEDDED + membar(); +#else + mb(); +#endif + pQueue->Head = Head; + atomic_dec(&pQueue->EntryCnt); + + return Entry; +} /* QQ_PopHead */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline PQQ_ENTRY +QQ_PopTail( +PQQ_CONTAINER pQueue) { + unsigned int Tail; + PQQ_ENTRY Entry; + + Tail = pQueue->Tail; + +#if !defined(QQ_NO_UNDERFLOW_CHECK) + if(Tail == pQueue->Head) { + return (PQQ_ENTRY) 0; + } /* if */ +#endif /* QQ_NO_UNDERFLOW_CHECK */ + + Entry = pQueue->Array[Tail]; +#ifdef EMBEDDED + membar(); +#else + mb(); +#endif + pQueue->Tail = (Tail + 1) % pQueue->Size; + atomic_dec(&pQueue->EntryCnt); + + return Entry; +} /* QQ_PopTail */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline PQQ_ENTRY +QQ_GetHead( + PQQ_CONTAINER pQueue, + unsigned int Idx) +{ + if(Idx >= atomic_read(&pQueue->EntryCnt)) + { + return (PQQ_ENTRY) 0; + } + + if(pQueue->Head > Idx) + { + Idx = pQueue->Head - Idx; + } + else + { + Idx = pQueue->Size - (Idx - pQueue->Head); + } + Idx--; + + return pQueue->Array[Idx]; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +extern __inline PQQ_ENTRY +QQ_GetTail( + PQQ_CONTAINER pQueue, + unsigned int Idx) +{ + if(Idx >= atomic_read(&pQueue->EntryCnt)) + { + return (PQQ_ENTRY) 0; + } + + Idx += pQueue->Tail; + if(Idx >= pQueue->Size) + { + Idx = Idx - pQueue->Size; + } + + return pQueue->Array[Idx]; +} + +#endif /* QQ_USE_MACROS */ + + +#endif /* QUEUE_H */ diff --git a/drivers/cfb_console.c b/drivers/cfb_console.c new file mode 100644 index 000000000..9727aebbc --- /dev/null +++ b/drivers/cfb_console.c @@ -0,0 +1,1274 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * cfb_console.c + * + * Color Framebuffer Console driver for 8/15/16/24/32 bits per pixel. + * + * At the moment only the 8x16 font is tested and the font fore- and + * background color is limited to black/white/gray colors. The Linux + * logo can be placed in the upper left corner and additional board + * information strings (that normaly goes to serial port) can be drawed. + * + * The console driver can use the standard PC keyboard interface (i8042) + * for character input. Character output goes to a memory mapped video + * framebuffer with little or big-endian organisation. + * With environment setting 'console=serial' the console i/o can be + * forced to serial port. + + The driver uses graphic specific defines/parameters/functions: + + (for SMI LynxE graphic chip) + + CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810 + VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian + VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill + VIDEO_HW_BITBLT - graphic driver supports hardware bit blt + + Console Parameters are set by graphic drivers global struct: + + VIDEO_VISIBLE_COLS - x resolution + VIDEO_VISIBLE_ROWS - y resolution + VIDEO_PIXEL_SIZE - storage size in byte per pixel + VIDEO_DATA_FORMAT - graphical data format GDF + VIDEO_FB_ADRS - start of video memory + + CONFIG_I8042_KBD - AT Keyboard driver for i8042 + VIDEO_KBD_INIT_FCT - init function for keyboard + VIDEO_TSTC_FCT - keyboard_tstc function + VIDEO_GETC_FCT - keyboard_getc function + + CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with delay + loop in VIDEO_TSTC_FCT (i8042) + CFG_CONSOLE_BLINK_COUNT - value for delay loop - blink rate + CONFIG_CONSOLE_TIME - display time/date in upper right corner, + needs CFG_CMD_DATE and CONFIG_CONSOLE_CURSOR + CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner + CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo + CONFIG_CONSOLE_EXTRA_INFO - display additional board information strings + that normaly goes to serial port. This define + requires a board specific function: + video_drawstring (VIDEO_INFO_X, + VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT, + info); + that fills a info buffer at i=row. + s.a: board/eltec/bab7xx. +CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be initialised + as an output only device. The Keyboard driver + will not be set-up. This may be used, if you + have none or more than one Keyboard devices + (USB Keyboard, AT Keyboard). + +CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last character. No + blinking is provided. Uses the macros CURSOR_SET + and CURSOR_OFF. +CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the + graphic chip. Uses the macro CURSOR_SET. + ATTENTION: If booting an OS, the display driver + must disable the hardware register of the graphic + chip. Otherwise a blinking field is displayed +*/ + +#include + +#ifdef CONFIG_CFB_CONSOLE + +#include + +/*****************************************************************************/ +/* Console device defines with SMI graphic */ +/* Any other graphic must change this section */ +/*****************************************************************************/ + +#ifdef CONFIG_VIDEO_SMI_LYNXEM + +#define VIDEO_FB_LITTLE_ENDIAN +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + +/*****************************************************************************/ +/* Defines for the CT69000 driver */ +/*****************************************************************************/ +#ifdef CONFIG_VIDEO_CT69000 + +#define VIDEO_FB_LITTLE_ENDIAN +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + +/*****************************************************************************/ +/* Defines for the SED13806 driver */ +/*****************************************************************************/ +#ifdef CONFIG_VIDEO_SED13806 + +#ifndef CONFIG_TOTAL5200 +#define VIDEO_FB_LITTLE_ENDIAN +#endif +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT +#endif + +/*****************************************************************************/ +/* Defines for the SED13806 driver */ +/*****************************************************************************/ +#ifdef CONFIG_VIDEO_SM501 + +#ifdef CONFIG_HH405 +#define VIDEO_FB_LITTLE_ENDIAN +#endif +#endif + +/*****************************************************************************/ +/* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */ +/*****************************************************************************/ +#include + +/*****************************************************************************/ +/* some Macros */ +/*****************************************************************************/ +#define VIDEO_VISIBLE_COLS (pGD->winSizeX) +#define VIDEO_VISIBLE_ROWS (pGD->winSizeY) +#define VIDEO_PIXEL_SIZE (pGD->gdfBytesPP) +#define VIDEO_DATA_FORMAT (pGD->gdfIndex) +#define VIDEO_FB_ADRS (pGD->frameAdrs) + +/*****************************************************************************/ +/* Console device defines with i8042 keyboard controller */ +/* Any other keyboard controller must change this section */ +/*****************************************************************************/ + +#ifdef CONFIG_I8042_KBD +#include + +#define VIDEO_KBD_INIT_FCT i8042_kbd_init() +#define VIDEO_TSTC_FCT i8042_tstc +#define VIDEO_GETC_FCT i8042_getc +#endif + +/*****************************************************************************/ +/* Console device */ +/*****************************************************************************/ + +#include +#include +#include +#include +#ifdef CFG_CMD_DATE +#include + +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#include +#include +#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ + +/*****************************************************************************/ +/* Cursor definition: */ +/* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/i8042.c) to */ +/* let the cursor blink. Uses the macros CURSOR_OFF */ +/* and CURSOR_ON. */ +/* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No */ +/* blinking is provided. Uses the macros CURSOR_SET */ +/* and CURSOR_OFF. */ +/* CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the */ +/* graphic chip. Uses the macro CURSOR_SET. */ +/* ATTENTION: If booting an OS, the display driver */ +/* must disable the hardware register of the graphic */ +/* chip. Otherwise a blinking field is displayed */ +/*****************************************************************************/ +#if !defined(CONFIG_CONSOLE_CURSOR) && \ + !defined(CONFIG_VIDEO_SW_CURSOR) && \ + !defined(CONFIG_VIDEO_HW_CURSOR) +/* no Cursor defined */ +#define CURSOR_ON +#define CURSOR_OFF +#define CURSOR_SET +#endif + +#ifdef CONFIG_CONSOLE_CURSOR +#ifdef CURSOR_ON +#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined +#endif +void console_cursor (int state); +#define CURSOR_ON console_cursor(1); +#define CURSOR_OFF console_cursor(0); +#define CURSOR_SET +#ifndef CONFIG_I8042_KBD +#warning Cursor drawing on/off needs timer function s.a. drivers/i8042.c +#endif +#else +#ifdef CONFIG_CONSOLE_TIME +#error CONFIG_CONSOLE_CURSOR must be defined for CONFIG_CONSOLE_TIME +#endif +#endif /* CONFIG_CONSOLE_CURSOR */ + +#ifdef CONFIG_VIDEO_SW_CURSOR +#ifdef CURSOR_ON +#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined +#endif +#define CURSOR_ON +#define CURSOR_OFF video_putchar(console_col * VIDEO_FONT_WIDTH,\ + console_row * VIDEO_FONT_HEIGHT, ' '); +#define CURSOR_SET video_set_cursor(); +#endif /* CONFIG_VIDEO_SW_CURSOR */ + + +#ifdef CONFIG_VIDEO_HW_CURSOR +#ifdef CURSOR_ON +#error only one of CONFIG_CONSOLE_CURSOR,CONFIG_VIDEO_SW_CURSOR,CONFIG_VIDEO_HW_CURSOR can be defined +#endif +#define CURSOR_ON +#define CURSOR_OFF +#define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \ + (console_row * VIDEO_FONT_HEIGHT) + VIDEO_LOGO_HEIGHT); +#endif /* CONFIG_VIDEO_HW_CURSOR */ + +#ifdef CONFIG_VIDEO_LOGO +#ifdef CONFIG_VIDEO_BMP_LOGO +#include +#define VIDEO_LOGO_WIDTH BMP_LOGO_WIDTH +#define VIDEO_LOGO_HEIGHT BMP_LOGO_HEIGHT +#define VIDEO_LOGO_LUT_OFFSET BMP_LOGO_OFFSET +#define VIDEO_LOGO_COLORS BMP_LOGO_COLORS + +#else /* CONFIG_VIDEO_BMP_LOGO */ +#define LINUX_LOGO_WIDTH 80 +#define LINUX_LOGO_HEIGHT 80 +#define LINUX_LOGO_COLORS 214 +#define LINUX_LOGO_LUT_OFFSET 0x20 +#define __initdata +#include +#define VIDEO_LOGO_WIDTH LINUX_LOGO_WIDTH +#define VIDEO_LOGO_HEIGHT LINUX_LOGO_HEIGHT +#define VIDEO_LOGO_LUT_OFFSET LINUX_LOGO_LUT_OFFSET +#define VIDEO_LOGO_COLORS LINUX_LOGO_COLORS +#endif /* CONFIG_VIDEO_BMP_LOGO */ +#define VIDEO_INFO_X (VIDEO_LOGO_WIDTH) +#define VIDEO_INFO_Y (VIDEO_FONT_HEIGHT/2) +#else /* CONFIG_VIDEO_LOGO */ +#define VIDEO_LOGO_WIDTH 0 +#define VIDEO_LOGO_HEIGHT 0 +#endif /* CONFIG_VIDEO_LOGO */ + +#define VIDEO_COLS VIDEO_VISIBLE_COLS +#define VIDEO_ROWS VIDEO_VISIBLE_ROWS +#define VIDEO_SIZE (VIDEO_ROWS*VIDEO_COLS*VIDEO_PIXEL_SIZE) +#define VIDEO_PIX_BLOCKS (VIDEO_SIZE >> 2) +#define VIDEO_LINE_LEN (VIDEO_COLS*VIDEO_PIXEL_SIZE) +#define VIDEO_BURST_LEN (VIDEO_COLS/8) + +#ifdef CONFIG_VIDEO_LOGO +#define CONSOLE_ROWS ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / VIDEO_FONT_HEIGHT) +#else +#define CONSOLE_ROWS (VIDEO_ROWS / VIDEO_FONT_HEIGHT) +#endif + +#define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH) +#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN) +#define CONSOLE_ROW_FIRST (video_console_address) +#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE) +#define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE) +#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) +#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) + +/* Macros */ +#ifdef VIDEO_FB_LITTLE_ENDIAN +#define SWAP16(x) ((((x) & 0x00ff) << 8) | ( (x) >> 8)) +#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ + (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) +#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | (((x) & 0x0000ff00) >> 8)|\ + (((x) & 0x00ff0000) << 8) | (((x) & 0xff000000) >> 8) ) +#else +#define SWAP16(x) (x) +#define SWAP32(x) (x) +#define SHORTSWAP32(x) (x) +#endif + +#if defined(DEBUG) || defined(DEBUG_CFB_CONSOLE) +#define PRINTD(x) printf(x) +#else +#define PRINTD(x) +#endif + + +#ifdef CONFIG_CONSOLE_EXTRA_INFO +extern void video_get_info_str ( /* setup a board string: type, speed, etc. */ + int line_number, /* location to place info string beside logo */ + char *info /* buffer for info string */ + ); + +#endif + +/* Locals */ +static GraphicDevice *pGD; /* Pointer to Graphic array */ + +static void *video_fb_address; /* frame buffer address */ +static void *video_console_address; /* console buffer start address */ + +static int console_col = 0; /* cursor col */ +static int console_row = 0; /* cursor row */ + +static u32 eorx, fgx, bgx; /* color pats */ + +static const int video_font_draw_table8[] = { + 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, + 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, + 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, + 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff }; + +static const int video_font_draw_table15[] = { + 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff }; + +static const int video_font_draw_table16[] = { + 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff }; + +static const int video_font_draw_table24[16][3] = { + { 0x00000000, 0x00000000, 0x00000000 }, + { 0x00000000, 0x00000000, 0x00ffffff }, + { 0x00000000, 0x0000ffff, 0xff000000 }, + { 0x00000000, 0x0000ffff, 0xffffffff }, + { 0x000000ff, 0xffff0000, 0x00000000 }, + { 0x000000ff, 0xffff0000, 0x00ffffff }, + { 0x000000ff, 0xffffffff, 0xff000000 }, + { 0x000000ff, 0xffffffff, 0xffffffff }, + { 0xffffff00, 0x00000000, 0x00000000 }, + { 0xffffff00, 0x00000000, 0x00ffffff }, + { 0xffffff00, 0x0000ffff, 0xff000000 }, + { 0xffffff00, 0x0000ffff, 0xffffffff }, + { 0xffffffff, 0xffff0000, 0x00000000 }, + { 0xffffffff, 0xffff0000, 0x00ffffff }, + { 0xffffffff, 0xffffffff, 0xff000000 }, + { 0xffffffff, 0xffffffff, 0xffffffff } }; + +static const int video_font_draw_table32[16][4] = { + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + { 0x00000000, 0x00000000, 0x00000000, 0x00ffffff }, + { 0x00000000, 0x00000000, 0x00ffffff, 0x00000000 }, + { 0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff }, + { 0x00000000, 0x00ffffff, 0x00000000, 0x00000000 }, + { 0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff }, + { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000 }, + { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff }, + { 0x00ffffff, 0x00000000, 0x00000000, 0x00000000 }, + { 0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff }, + { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000 }, + { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff }, + { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000 }, + { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff }, + { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000 }, + { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } }; + + +int gunzip(void *, int, unsigned char *, unsigned long *); + +/******************************************************************************/ + +static void video_drawchars (int xx, int yy, unsigned char *s, int count) +{ + u8 *cdat, *dest, *dest0; + int rows, offset, c; + + offset = yy * VIDEO_LINE_LEN + xx * VIDEO_PIXEL_SIZE; + dest0 = video_fb_address + offset; + + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + case GDF__8BIT_332RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = (video_font_draw_table8[bits >> 4] & eorx) ^ bgx; + ((u32 *) dest)[1] = (video_font_draw_table8[bits & 15] & eorx) ^ bgx; + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_15BIT_555RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 6] & eorx) ^ bgx); + ((u32 *) dest)[1] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 4 & 3] & eorx) ^ bgx); + ((u32 *) dest)[2] = SHORTSWAP32 ((video_font_draw_table15 [bits >> 2 & 3] & eorx) ^ bgx); + ((u32 *) dest)[3] = SHORTSWAP32 ((video_font_draw_table15 [bits & 3] & eorx) ^ bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_16BIT_565RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 6] & eorx) ^ bgx); + ((u32 *) dest)[1] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 4 & 3] & eorx) ^ bgx); + ((u32 *) dest)[2] = SHORTSWAP32 ((video_font_draw_table16 [bits >> 2 & 3] & eorx) ^ bgx); + ((u32 *) dest)[3] = SHORTSWAP32 ((video_font_draw_table16 [bits & 3] & eorx) ^ bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_32BIT_X888RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = SWAP32 ((video_font_draw_table32 [bits >> 4][0] & eorx) ^ bgx); + ((u32 *) dest)[1] = SWAP32 ((video_font_draw_table32 [bits >> 4][1] & eorx) ^ bgx); + ((u32 *) dest)[2] = SWAP32 ((video_font_draw_table32 [bits >> 4][2] & eorx) ^ bgx); + ((u32 *) dest)[3] = SWAP32 ((video_font_draw_table32 [bits >> 4][3] & eorx) ^ bgx); + ((u32 *) dest)[4] = SWAP32 ((video_font_draw_table32 [bits & 15][0] & eorx) ^ bgx); + ((u32 *) dest)[5] = SWAP32 ((video_font_draw_table32 [bits & 15][1] & eorx) ^ bgx); + ((u32 *) dest)[6] = SWAP32 ((video_font_draw_table32 [bits & 15][2] & eorx) ^ bgx); + ((u32 *) dest)[7] = SWAP32 ((video_font_draw_table32 [bits & 15][3] & eorx) ^ bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + + case GDF_24BIT_888RGB: + while (count--) { + c = *s; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; + rows--; + dest += VIDEO_LINE_LEN) { + u8 bits = *cdat++; + + ((u32 *) dest)[0] = (video_font_draw_table24[bits >> 4][0] & eorx) ^ bgx; + ((u32 *) dest)[1] = (video_font_draw_table24[bits >> 4][1] & eorx) ^ bgx; + ((u32 *) dest)[2] = (video_font_draw_table24[bits >> 4][2] & eorx) ^ bgx; + ((u32 *) dest)[3] = (video_font_draw_table24[bits & 15][0] & eorx) ^ bgx; + ((u32 *) dest)[4] = (video_font_draw_table24[bits & 15][1] & eorx) ^ bgx; + ((u32 *) dest)[5] = (video_font_draw_table24[bits & 15][2] & eorx) ^ bgx; + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; + } +} + +/*****************************************************************************/ + +static inline void video_drawstring (int xx, int yy, unsigned char *s) +{ + video_drawchars (xx, yy, s, strlen ((char *)s)); +} + +/*****************************************************************************/ + +static void video_putchar (int xx, int yy, unsigned char c) +{ + video_drawchars (xx, yy + VIDEO_LOGO_HEIGHT, &c, 1); +} + +/*****************************************************************************/ +#if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR) +static void video_set_cursor (void) +{ + /* swap drawing colors */ + eorx = fgx; + fgx = bgx; + bgx = eorx; + eorx = fgx ^ bgx; + /* draw cursor */ + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, + ' '); + /* restore drawing colors */ + eorx = fgx; + fgx = bgx; + bgx = eorx; + eorx = fgx ^ bgx; +} +#endif +/*****************************************************************************/ +#ifdef CONFIG_CONSOLE_CURSOR +void console_cursor (int state) +{ + static int last_state = 0; + +#ifdef CONFIG_CONSOLE_TIME + struct rtc_time tm; + char info[16]; + + /* time update only if cursor is on (faster scroll) */ + if (state) { + rtc_get (&tm); + + sprintf (info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min, + tm.tm_sec); + video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH, + VIDEO_INFO_Y, (uchar *)info); + + sprintf (info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon, + tm.tm_year); + video_drawstring (VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH, + VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT, (uchar *)info); + } +#endif + + if (state && (last_state != state)) { + video_set_cursor (); + } + + if (!state && (last_state != state)) { + /* clear cursor */ + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, + ' '); + } + + last_state = state; +} +#endif + +/*****************************************************************************/ + +#ifndef VIDEO_HW_RECTFILL +static void memsetl (int *p, int c, int v) +{ + while (c--) + *(p++) = v; +} +#endif + +/*****************************************************************************/ + +#ifndef VIDEO_HW_BITBLT +static void memcpyl (int *d, int *s, int c) +{ + while (c--) + *(d++) = *(s++); +} +#endif + +/*****************************************************************************/ + +static void console_scrollup (void) +{ + /* copy up rows ignoring the first one */ + +#ifdef VIDEO_HW_BITBLT + video_hw_bitblt (VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* source pos x */ + VIDEO_LOGO_HEIGHT + VIDEO_FONT_HEIGHT, /* source pos y */ + 0, /* dest pos x */ + VIDEO_LOGO_HEIGHT, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_VISIBLE_ROWS - VIDEO_LOGO_HEIGHT - VIDEO_FONT_HEIGHT /* frame height */ + ); +#else + memcpyl (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, + CONSOLE_SCROLL_SIZE >> 2); +#endif + + /* clear the last one */ +#ifdef VIDEO_HW_RECTFILL + video_hw_rectfill (VIDEO_PIXEL_SIZE, /* bytes per pixel */ + 0, /* dest pos x */ + VIDEO_VISIBLE_ROWS - VIDEO_FONT_HEIGHT, /* dest pos y */ + VIDEO_VISIBLE_COLS, /* frame width */ + VIDEO_FONT_HEIGHT, /* frame height */ + CONSOLE_BG_COL /* fill color */ + ); +#else + memsetl (CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, CONSOLE_BG_COL); +#endif +} + +/*****************************************************************************/ + +static void console_back (void) +{ + CURSOR_OFF console_col--; + + if (console_col < 0) { + console_col = CONSOLE_COLS - 1; + console_row--; + if (console_row < 0) + console_row = 0; + } + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, + ' '); +} + +/*****************************************************************************/ + +static void console_newline (void) +{ + CURSOR_OFF console_row++; + console_col = 0; + + /* Check if we need to scroll the terminal */ + if (console_row >= CONSOLE_ROWS) { + /* Scroll everything up */ + console_scrollup (); + + /* Decrement row number */ + console_row--; + } +} + +/*****************************************************************************/ + +void video_putc (const char c) +{ + switch (c) { + case 13: /* ignore */ + break; + + case '\n': /* next line */ + console_newline (); + break; + + case 9: /* tab 8 */ + CURSOR_OFF console_col |= 0x0008; + console_col &= ~0x0007; + + if (console_col >= CONSOLE_COLS) + console_newline (); + break; + + case 8: /* backspace */ + console_back (); + break; + + default: /* draw the char */ + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, + c); + console_col++; + + /* check for newline */ + if (console_col >= CONSOLE_COLS) + console_newline (); + } +CURSOR_SET} + + +/*****************************************************************************/ + +void video_puts (const char *s) +{ + int count = strlen (s); + + while (count--) + video_putc (*s++); +} + +/*****************************************************************************/ + +#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) + +#define FILL_8BIT_332RGB(r,g,b) { \ + *fb = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6); \ + fb ++; \ +} + +#define FILL_15BIT_555RGB(r,g,b) { \ + *(unsigned short *)fb = SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); \ + fb += 2; \ +} + +#define FILL_16BIT_565RGB(r,g,b) { \ + *(unsigned short *)fb = SWAP16((unsigned short)((((r)>>3)<<11) | (((g)>>2)<<5) | ((b)>>3))); \ + fb += 2; \ +} + +#define FILL_32BIT_X888RGB(r,g,b) { \ + *(unsigned long *)fb = SWAP32((unsigned long)(((r<<16) | (g<<8) | b))); \ + fb += 4; \ +} + +#ifdef VIDEO_FB_LITTLE_ENDIAN +#define FILL_24BIT_888RGB(r,g,b) { \ + fb[0] = b; \ + fb[1] = g; \ + fb[2] = r; \ + fb += 3; \ +} +#else +#define FILL_24BIT_888RGB(r,g,b) { \ + fb[0] = r; \ + fb[1] = g; \ + fb[2] = b; \ + fb += 3; \ +} +#endif + + +/* + * Display the BMP file located at address bmp_image. + * Only uncompressed + */ +int video_display_bitmap (ulong bmp_image, int x, int y) +{ + ushort xcount, ycount; + uchar *fb; + bmp_image_t *bmp = (bmp_image_t *) bmp_image; + uchar *bmap; + ushort padded_line; + unsigned long width, height, bpp; + unsigned colors; + unsigned long compression; + bmp_color_table_entry_t cte; +#ifdef CONFIG_VIDEO_BMP_GZIP + unsigned char *dst = NULL; + ulong len; +#endif + + WATCHDOG_RESET (); + + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + +#ifdef CONFIG_VIDEO_BMP_GZIP + /* + * Could be a gzipped bmp image, try to decrompress... + */ + len = CFG_VIDEO_LOGO_MAX_SIZE; + dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); + if (dst == NULL) { + printf("Error: malloc in gunzip failed!\n"); + return(1); + } + if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)bmp_image, &len) != 0) { + printf ("Error: no valid bmp or bmp.gz image at %lx\n", bmp_image); + free(dst); + return 1; + } + if (len == CFG_VIDEO_LOGO_MAX_SIZE) { + printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); + } + + /* + * Set addr to decompressed image + */ + bmp = (bmp_image_t *)dst; + + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + printf ("Error: no valid bmp.gz image at %lx\n", bmp_image); + return 1; + } +#else + printf ("Error: no valid bmp image at %lx\n", bmp_image); + return 1; +#endif /* CONFIG_VIDEO_BMP_GZIP */ + } + + width = le32_to_cpu (bmp->header.width); + height = le32_to_cpu (bmp->header.height); + bpp = le16_to_cpu (bmp->header.bit_count); + colors = le32_to_cpu (bmp->header.colors_used); + compression = le32_to_cpu (bmp->header.compression); + + debug ("Display-bmp: %d x %d with %d colors\n", + width, height, colors); + + if (compression != BMP_BI_RGB) { + printf ("Error: compression type %ld not supported\n", + compression); + return 1; + } + + padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3; + + if ((x + width) > VIDEO_VISIBLE_COLS) + width = VIDEO_VISIBLE_COLS - x; + if ((y + height) > VIDEO_VISIBLE_ROWS) + height = VIDEO_VISIBLE_ROWS - y; + + bmap = (uchar *) bmp + le32_to_cpu (bmp->header.data_offset); + fb = (uchar *) (video_fb_address + + ((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) + + x * VIDEO_PIXEL_SIZE); + + /* We handle only 8bpp or 24 bpp bitmap */ + switch (le16_to_cpu (bmp->header.bit_count)) { + case 8: + padded_line -= width; + if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) { + /* Copy colormap */ + for (xcount = 0; xcount < colors; ++xcount) { + cte = bmp->color_table[xcount]; + video_set_lut (xcount, cte.red, cte.green, cte.blue); + } + } + ycount = height; + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + *fb++ = *bmap++; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF__8BIT_332RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_8BIT_332RGB (cte.red, cte.green, cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_15BIT_555RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_15BIT_555RGB (cte.red, cte.green, cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_16BIT_565RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_16BIT_565RGB (cte.red, cte.green, cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_32BIT_X888RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_32BIT_X888RGB (cte.red, cte.green, cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_24BIT_888RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + cte = bmp->color_table[*bmap++]; + FILL_24BIT_888RGB (cte.red, cte.green, cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + } + break; + case 24: + padded_line -= 3 * width; + ycount = height; + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_332RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + FILL_8BIT_332RGB (bmap[2], bmap[1], bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_15BIT_555RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + FILL_15BIT_555RGB (bmap[2], bmap[1], bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_16BIT_565RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + FILL_16BIT_565RGB (bmap[2], bmap[1], bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_32BIT_X888RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + FILL_32BIT_X888RGB (bmap[2], bmap[1], bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + case GDF_24BIT_888RGB: + while (ycount--) { + WATCHDOG_RESET (); + xcount = width; + while (xcount--) { + FILL_24BIT_888RGB (bmap[2], bmap[1], bmap[0]); + bmap += 3; + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * VIDEO_PIXEL_SIZE; + } + break; + default: + printf ("Error: 24 bits/pixel bitmap incompatible with current video mode\n"); + break; + } + break; + default: + printf ("Error: %d bit/pixel bitmaps not supported by U-Boot\n", + le16_to_cpu (bmp->header.bit_count)); + break; + } + +#ifdef CONFIG_VIDEO_BMP_GZIP + if (dst) { + free(dst); + } +#endif + + return (0); +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ + +/*****************************************************************************/ + +#ifdef CONFIG_VIDEO_LOGO +void logo_plot (void *screen, int width, int x, int y) +{ + + int xcount, i; + int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE; + int ycount = VIDEO_LOGO_HEIGHT; + unsigned char r, g, b, *logo_red, *logo_blue, *logo_green; + unsigned char *source; + unsigned char *dest = (unsigned char *)screen + ((y * width * VIDEO_PIXEL_SIZE) + x); + +#ifdef CONFIG_VIDEO_BMP_LOGO + source = bmp_logo_bitmap; + + /* Allocate temporary space for computing colormap */ + logo_red = malloc (BMP_LOGO_COLORS); + logo_green = malloc (BMP_LOGO_COLORS); + logo_blue = malloc (BMP_LOGO_COLORS); + /* Compute color map */ + for (i = 0; i < VIDEO_LOGO_COLORS; i++) { + logo_red[i] = (bmp_logo_palette[i] & 0x0f00) >> 4; + logo_green[i] = (bmp_logo_palette[i] & 0x00f0); + logo_blue[i] = (bmp_logo_palette[i] & 0x000f) << 4; + } +#else + source = linux_logo; + logo_red = linux_logo_red; + logo_green = linux_logo_green; + logo_blue = linux_logo_blue; +#endif + + if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) { + for (i = 0; i < VIDEO_LOGO_COLORS; i++) { + video_set_lut (i + VIDEO_LOGO_LUT_OFFSET, + logo_red[i], logo_green[i], logo_blue[i]); + } + } + + while (ycount--) { + xcount = VIDEO_LOGO_WIDTH; + while (xcount--) { + r = logo_red[*source - VIDEO_LOGO_LUT_OFFSET]; + g = logo_green[*source - VIDEO_LOGO_LUT_OFFSET]; + b = logo_blue[*source - VIDEO_LOGO_LUT_OFFSET]; + + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + *dest = *source; + break; + case GDF__8BIT_332RGB: + *dest = ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6); + break; + case GDF_15BIT_555RGB: + *(unsigned short *) dest = + SWAP16 ((unsigned short) (((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3))); + break; + case GDF_16BIT_565RGB: + *(unsigned short *) dest = + SWAP16 ((unsigned short) (((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3))); + break; + case GDF_32BIT_X888RGB: + *(unsigned long *) dest = + SWAP32 ((unsigned long) ((r << 16) | (g << 8) | b)); + break; + case GDF_24BIT_888RGB: +#ifdef VIDEO_FB_LITTLE_ENDIAN + dest[0] = b; + dest[1] = g; + dest[2] = r; +#else + dest[0] = r; + dest[1] = g; + dest[2] = b; +#endif + break; + } + source++; + dest += VIDEO_PIXEL_SIZE; + } + dest += skip; + } +#ifdef CONFIG_VIDEO_BMP_LOGO + free (logo_red); + free (logo_green); + free (logo_blue); +#endif +} + +/*****************************************************************************/ + +static void *video_logo (void) +{ + char info[128]; + extern char version_string; + +#ifdef CONFIG_SPLASH_SCREEN + char *s; + ulong addr; + + if ((s = getenv ("splashimage")) != NULL) { + addr = simple_strtoul (s, NULL, 16); + + if (video_display_bitmap (addr, 0, 0) == 0) { + return ((void *) (video_fb_address)); + } + } +#endif /* CONFIG_SPLASH_SCREEN */ + + logo_plot (video_fb_address, VIDEO_COLS, 0, 0); + + sprintf (info, " %s", &version_string); + video_drawstring (VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *)info); + +#ifdef CONFIG_CONSOLE_EXTRA_INFO + { + int i, n = ((VIDEO_LOGO_HEIGHT - VIDEO_FONT_HEIGHT) / VIDEO_FONT_HEIGHT); + + for (i = 1; i < n; i++) { + video_get_info_str (i, info); + if (*info) + video_drawstring (VIDEO_INFO_X, + VIDEO_INFO_Y + i * VIDEO_FONT_HEIGHT, + (uchar *)info); + } + } +#endif + + return (video_fb_address + VIDEO_LOGO_HEIGHT * VIDEO_LINE_LEN); +} +#endif + + +/*****************************************************************************/ + +static int video_init (void) +{ + unsigned char color8; + + if ((pGD = video_hw_init ()) == NULL) + return -1; + + video_fb_address = (void *) VIDEO_FB_ADRS; +#ifdef CONFIG_VIDEO_HW_CURSOR + video_init_hw_cursor (VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT); +#endif + + /* Init drawing pats */ + switch (VIDEO_DATA_FORMAT) { + case GDF__8BIT_INDEX: + video_set_lut (0x01, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL); + video_set_lut (0x00, CONSOLE_BG_COL, CONSOLE_BG_COL, CONSOLE_BG_COL); + fgx = 0x01010101; + bgx = 0x00000000; + break; + case GDF__8BIT_332RGB: + color8 = ((CONSOLE_FG_COL & 0xe0) | + ((CONSOLE_FG_COL >> 3) & 0x1c) | CONSOLE_FG_COL >> 6); + fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8; + color8 = ((CONSOLE_BG_COL & 0xe0) | + ((CONSOLE_BG_COL >> 3) & 0x1c) | CONSOLE_BG_COL >> 6); + bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8; + break; + case GDF_15BIT_555RGB: + fgx = (((CONSOLE_FG_COL >> 3) << 26) | + ((CONSOLE_FG_COL >> 3) << 21) | ((CONSOLE_FG_COL >> 3) << 16) | + ((CONSOLE_FG_COL >> 3) << 10) | ((CONSOLE_FG_COL >> 3) << 5) | + (CONSOLE_FG_COL >> 3)); + bgx = (((CONSOLE_BG_COL >> 3) << 26) | + ((CONSOLE_BG_COL >> 3) << 21) | ((CONSOLE_BG_COL >> 3) << 16) | + ((CONSOLE_BG_COL >> 3) << 10) | ((CONSOLE_BG_COL >> 3) << 5) | + (CONSOLE_BG_COL >> 3)); + break; + case GDF_16BIT_565RGB: + fgx = (((CONSOLE_FG_COL >> 3) << 27) | + ((CONSOLE_FG_COL >> 2) << 21) | ((CONSOLE_FG_COL >> 3) << 16) | + ((CONSOLE_FG_COL >> 3) << 11) | ((CONSOLE_FG_COL >> 2) << 5) | + (CONSOLE_FG_COL >> 3)); + bgx = (((CONSOLE_BG_COL >> 3) << 27) | + ((CONSOLE_BG_COL >> 2) << 21) | ((CONSOLE_BG_COL >> 3) << 16) | + ((CONSOLE_BG_COL >> 3) << 11) | ((CONSOLE_BG_COL >> 2) << 5) | + (CONSOLE_BG_COL >> 3)); + break; + case GDF_32BIT_X888RGB: + fgx = (CONSOLE_FG_COL << 16) | (CONSOLE_FG_COL << 8) | CONSOLE_FG_COL; + bgx = (CONSOLE_BG_COL << 16) | (CONSOLE_BG_COL << 8) | CONSOLE_BG_COL; + break; + case GDF_24BIT_888RGB: + fgx = (CONSOLE_FG_COL << 24) | (CONSOLE_FG_COL << 16) | + (CONSOLE_FG_COL << 8) | CONSOLE_FG_COL; + bgx = (CONSOLE_BG_COL << 24) | (CONSOLE_BG_COL << 16) | + (CONSOLE_BG_COL << 8) | CONSOLE_BG_COL; + break; + } + eorx = fgx ^ bgx; + +#ifdef CONFIG_VIDEO_LOGO + /* Plot the logo and get start point of console */ + PRINTD ("Video: Drawing the logo ...\n"); + video_console_address = video_logo (); +#else + video_console_address = video_fb_address; +#endif + + /* Initialize the console */ + console_col = 0; + console_row = 0; + + return 0; +} + + +/*****************************************************************************/ + +int drv_video_init (void) +{ + int skip_dev_init; + device_t console_dev; + + skip_dev_init = 0; + + /* Init video chip - returns with framebuffer cleared */ + if (video_init () == -1) + skip_dev_init = 1; + +#ifdef CONFIG_VGA_AS_SINGLE_DEVICE + /* Devices VGA and Keyboard will be assigned seperately */ + /* Init vga device */ + if (!skip_dev_init) { + memset (&console_dev, 0, sizeof (console_dev)); + strcpy (console_dev.name, "vga"); + console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ + console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; + console_dev.putc = video_putc; /* 'putc' function */ + console_dev.puts = video_puts; /* 'puts' function */ + console_dev.tstc = NULL; /* 'tstc' function */ + console_dev.getc = NULL; /* 'getc' function */ + + if (device_register (&console_dev) == 0) + return 1; + } +#else + PRINTD ("KBD: Keyboard init ...\n"); + if (VIDEO_KBD_INIT_FCT == -1) + skip_dev_init = 1; + + /* Init console device */ + if (!skip_dev_init) { + memset (&console_dev, 0, sizeof (console_dev)); + strcpy (console_dev.name, "vga"); + console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ + console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + console_dev.putc = video_putc; /* 'putc' function */ + console_dev.puts = video_puts; /* 'puts' function */ + console_dev.tstc = VIDEO_TSTC_FCT; /* 'tstc' function */ + console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */ + + if (device_register (&console_dev) == 0) + return 1; + } +#endif /* CONFIG_VGA_AS_SINGLE_DEVICE */ + /* No console dev available */ + return 0; +} +#endif /* CONFIG_CFB_CONSOLE */ diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c new file mode 100644 index 000000000..a935fdebb --- /dev/null +++ b/drivers/cfi_flash.c @@ -0,0 +1,1536 @@ +/* + * (C) Copyright 2002-2004 + * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com + * + * Copyright (C) 2003 Arabella Software Ltd. + * Yuli Barcohen + * Modified to work with AMD flashes + * + * Copyright (C) 2004 + * Ed Okerson + * Modified to work with little-endian systems. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * History + * 01/20/2004 - combined variants of original driver. + * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay) + * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud) + * 01/27/2004 - Little endian support Ed Okerson + * + * Tested Architectures + * Port Width Chip Width # of banks Flash Chip Board + * 32 16 1 28F128J3 seranoa/eagle + * 64 16 1 28F128J3 seranoa/falcon + * + */ + +/* The DEBUG define must be before common to enable debugging */ +/*#define DEBUG */ + +#include +#include +#include +#include +#ifdef CFG_FLASH_CFI_DRIVER + +/* + * This file implements a Common Flash Interface (CFI) driver for U-Boot. + * The width of the port and the width of the chips are determined at initialization. + * These widths are used to calculate the address for access CFI data structures. + * It has been tested on an Intel Strataflash implementation and AMD 29F016D. + * + * References + * JEDEC Standard JESD68 - Common Flash Interface (CFI) + * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes + * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets + * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet + * + * TODO + * + * Use Primary Extended Query table (PRI) and Alternate Algorithm Query + * Table (ALT) to determine if protection is available + * + * Add support for other command sets Use the PRI and ALT to determine command set + * Verify erase and program timeouts. + */ + +#ifndef CFG_FLASH_BANKS_LIST +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#endif + +#define FLASH_CMD_CFI 0x98 +#define FLASH_CMD_READ_ID 0x90 +#define FLASH_CMD_RESET 0xff +#define FLASH_CMD_BLOCK_ERASE 0x20 +#define FLASH_CMD_ERASE_CONFIRM 0xD0 +#define FLASH_CMD_WRITE 0x40 +#define FLASH_CMD_WRITE_S 0x41 +#define FLASH_CMD_PROTECT 0x60 +#define FLASH_CMD_PROTECT_SET 0x01 +#define FLASH_CMD_PROTECT_CLEAR 0xD0 +#define FLASH_CMD_CLEAR_STATUS 0x50 +#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 +#define FLASH_CMD_WRITE_TO_BUFFER_S 0xE9 +#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 + +#define FLASH_STATUS_DONE 0x80 +#define FLASH_STATUS_ESS 0x40 +#define FLASH_STATUS_ECLBS 0x20 +#define FLASH_STATUS_PSLBS 0x10 +#define FLASH_STATUS_VPENS 0x08 +#define FLASH_STATUS_PSS 0x04 +#define FLASH_STATUS_DPS 0x02 +#define FLASH_STATUS_R 0x01 +#define FLASH_STATUS_PROTECT 0x01 + +#define AMD_CMD_RESET 0xF0 +#define AMD_CMD_WRITE 0xA0 +#define AMD_CMD_ERASE_START 0x80 +#define AMD_CMD_ERASE_SECTOR 0x30 +#define AMD_CMD_UNLOCK_START 0xAA +#define AMD_CMD_UNLOCK_ACK 0x55 +#define AMD_CMD_WRITE_TO_BUFFER 0x25 +#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 + +#define AMD_STATUS_TOGGLE 0x40 +#define AMD_STATUS_ERROR 0x20 +#define AMD_ADDR_ERASE_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) +#define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) +#define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA) + +#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_CFI_RESP 0x10 +#define FLASH_OFFSET_PRIMARY_VENDOR 0x13 +#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 /* extended query table primary addr */ +#define FLASH_OFFSET_WTOUT 0x1F +#define FLASH_OFFSET_WBTOUT 0x20 +#define FLASH_OFFSET_ETOUT 0x21 +#define FLASH_OFFSET_CETOUT 0x22 +#define FLASH_OFFSET_WMAX_TOUT 0x23 +#define FLASH_OFFSET_WBMAX_TOUT 0x24 +#define FLASH_OFFSET_EMAX_TOUT 0x25 +#define FLASH_OFFSET_CEMAX_TOUT 0x26 +#define FLASH_OFFSET_SIZE 0x27 +#define FLASH_OFFSET_INTERFACE 0x28 +#define FLASH_OFFSET_BUFFER_SIZE 0x2A +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C +#define FLASH_OFFSET_ERASE_REGIONS 0x2D +#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_USER_PROTECTION 0x85 +#define FLASH_OFFSET_INTEL_PROTECTION 0x81 + + +#define FLASH_MAN_CFI 0x01000000 + +#define CFI_CMDSET_NONE 0 +#define CFI_CMDSET_INTEL_EXTENDED 1 +#define CFI_CMDSET_INTEL_SIBLEY 512 +#define CFI_CMDSET_AMD_STANDARD 2 +#define CFI_CMDSET_INTEL_STANDARD 3 +#define CFI_CMDSET_AMD_EXTENDED 4 +#define CFI_CMDSET_MITSU_STANDARD 256 +#define CFI_CMDSET_MITSU_EXTENDED 257 +#define CFI_CMDSET_SST 258 + + +#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ +# undef FLASH_CMD_RESET +# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ +#endif + + +typedef union { + unsigned char c; + unsigned short w; + unsigned long l; + unsigned long long ll; +} cfiword_t; + +typedef union { + volatile unsigned char *cp; + volatile unsigned short *wp; + volatile unsigned long *lp; + volatile unsigned long long *llp; +} cfiptr_t; + +#define NUM_ERASE_REGIONS 4 + +/* use CFG_MAX_FLASH_BANKS_DETECT if defined */ +#ifdef CFG_MAX_FLASH_BANKS_DETECT +static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST; +flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */ +#else +static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */ +#endif + +/* + * Check if chip width is defined. If not, start detecting with 8bit. + */ +#ifndef CFG_FLASH_CFI_WIDTH +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#endif +/*----------------------------------------------------------------------- + * Functions + */ + +typedef unsigned long flash_sect_t; + +static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c); +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf); +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, ulong cmd); +static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect); +static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd); +static int flash_detect_cfi (flash_info_t * info); +static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); +static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt); +ulong flash_get_size (ulong base, int banknum); +#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +static flash_info_t *flash_get_info(ulong base); +#endif +#ifdef CFG_FLASH_USE_BUFFER_WRITE +static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len); +#endif + +/*----------------------------------------------------------------------- + * create an address based on the offset and the port width + */ +inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset) +{ + return ((uchar *) (info->start[sect] + (offset * info->portwidth))); +} + +#ifdef DEBUG +/*----------------------------------------------------------------------- + * Debug support + */ +void print_longlong (char *str, unsigned long long data) +{ + int i; + char *cp; + + cp = (unsigned char *) &data; + for (i = 0; i < 8; i++) + sprintf (&str[i * 2], "%2.2x", *cp++); +} +static void flash_printqry (flash_info_t * info, flash_sect_t sect) +{ + cfiptr_t cptr; + int x, y; + + for (x = 0; x < 0x40; x += 16U / info->portwidth) { + cptr.cp = + flash_make_addr (info, sect, + x + FLASH_OFFSET_CFI_RESP); + debug ("%p : ", cptr.cp); + for (y = 0; y < 16; y++) { + debug ("%2.2x ", cptr.cp[y]); + } + debug (" "); + for (y = 0; y < 16; y++) { + if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) { + debug ("%c", cptr.cp[y]); + } else { + debug ("."); + } + } + debug ("\n"); + } +} +#endif + + +/*----------------------------------------------------------------------- + * read a character at a port width address + */ +inline uchar flash_read_uchar (flash_info_t * info, uint offset) +{ + uchar *cp; + + cp = flash_make_addr (info, 0, offset); +#if defined(__LITTLE_ENDIAN) + return (cp[0]); +#else + return (cp[info->portwidth - 1]); +#endif +} + +/*----------------------------------------------------------------------- + * read a short word by swapping for ppc format. + */ +ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) +{ + uchar *addr; + ushort retval; + +#ifdef DEBUG + int x; +#endif + addr = flash_make_addr (info, sect, offset); + +#ifdef DEBUG + debug ("ushort addr is at %p info->portwidth = %d\n", addr, + info->portwidth); + for (x = 0; x < 2 * info->portwidth; x++) { + debug ("addr[%x] = 0x%x\n", x, addr[x]); + } +#endif +#if defined(__LITTLE_ENDIAN) + retval = ((addr[(info->portwidth)] << 8) | addr[0]); +#else + retval = ((addr[(2 * info->portwidth) - 1] << 8) | + addr[info->portwidth - 1]); +#endif + + debug ("retval = 0x%x\n", retval); + return retval; +} + +/*----------------------------------------------------------------------- + * read a long word by picking the least significant byte of each maiximum + * port size word. Swap for ppc format. + */ +ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) +{ + uchar *addr; + ulong retval; + +#ifdef DEBUG + int x; +#endif + addr = flash_make_addr (info, sect, offset); + +#ifdef DEBUG + debug ("long addr is at %p info->portwidth = %d\n", addr, + info->portwidth); + for (x = 0; x < 4 * info->portwidth; x++) { + debug ("addr[%x] = 0x%x\n", x, addr[x]); + } +#endif +#if defined(__LITTLE_ENDIAN) + retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) | + (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8); +#else + retval = (addr[(2 * info->portwidth) - 1] << 24) | + (addr[(info->portwidth) - 1] << 16) | + (addr[(4 * info->portwidth) - 1] << 8) | + addr[(3 * info->portwidth) - 1]; +#endif + return retval; +} + +/*----------------------------------------------------------------------- + */ +unsigned long flash_init (void) +{ + unsigned long size = 0; + int i; + +#ifdef CFG_FLASH_PROTECTION + char *s = getenv("unlock"); +#endif + +#ifdef ENV_IS_VARIABLE + /* GDP has a different flash combination */ + extern ulong NOR_FLASH_BANKS_LIST[CFG_MAX_FLASH_BANKS]; + extern int NOR_MAX_FLASH_BANKS; + memcpy(bank_base, NOR_FLASH_BANKS_LIST, sizeof(bank_base)); +#endif + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; +#ifdef ENV_IS_VARIABLE + if(i > (NOR_MAX_FLASH_BANKS - 1)) { + break; + } +#endif + size += flash_info[i].size = flash_get_size (bank_base[i], i); + if (flash_info[i].flash_id == FLASH_UNKNOWN) { +#ifndef CFG_FLASH_QUIET_TEST + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, flash_info[i].size, flash_info[i].size << 20); +#endif /* CFG_FLASH_QUIET_TEST */ + } +#ifdef CFG_FLASH_PROTECTION + else if ((s != NULL) && (strcmp(s, "yes") == 0)) { + /* + * Only the U-Boot image and it's environment is protected, + * all other sectors are unprotected (unlocked) if flash + * hardware protection is used (CFG_FLASH_PROTECTION) and + * the environment variable "unlock" is set to "yes". + */ + if (flash_info[i].legacy_unlock) { + int k; + + /* + * Disable legacy_unlock temporarily, since + * flash_real_protect would relock all other sectors + * again otherwise. + */ + flash_info[i].legacy_unlock = 0; + + /* + * Legacy unlocking (e.g. Intel J3) -> unlock only one + * sector. This will unlock all sectors. + */ + flash_real_protect (&flash_info[i], 0, 0); + + flash_info[i].legacy_unlock = 1; + + /* + * Manually mark other sectors as unlocked (unprotected) + */ + for (k = 1; k < flash_info[i].sector_count; k++) + flash_info[i].protect[k] = 0; + } else { + /* + * No legancy unlocking -> unlock all sectors + */ + flash_protect (FLAG_PROTECT_CLEAR, + flash_info[i].start[0], + flash_info[i].start[0] + flash_info[i].size - 1, + &flash_info[i]); + } + } +#endif /* CFG_FLASH_PROTECTION */ + } + + /* Monitor protection ON by default */ +#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +#ifdef ENV_IS_VARIABLE +extern int flash_env_init(void); +extern int (*boot_env_init) (void); + if (flash_env_init == boot_env_init) +#endif + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + flash_get_info(CFG_MONITOR_BASE)); +#endif + + /* Environment protection ON by default */ +#ifdef CFG_ENV_IS_IN_FLASH +#ifdef ENV_IS_VARIABLE +extern int flash_env_init(void); +extern int (*boot_env_init) (void); + if (flash_env_init == boot_env_init) +#endif + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + flash_get_info(CFG_ENV_ADDR)); +#endif + + /* Redundant environment protection ON by default */ +#ifdef CFG_ENV_ADDR_REDUND + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + flash_get_info(CFG_ENV_ADDR_REDUND)); +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +static flash_info_t *flash_get_info(ulong base) +{ + int i; + flash_info_t * info = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + info = & flash_info[i]; + if (info->size && info->start[0] <= base && + base <= info->start[0] + info->size - 1) + break; + } + + return i == CFG_MAX_FLASH_BANKS ? 0 : info; +} +#endif + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int rcode = 0; + int prot; + flash_sect_t sect; + + if (info->flash_id != FLASH_MAN_CFI) { + puts ("Can't erase unknown flash type - aborted\n"); + return 1; + } + if ((s_first < 0) || (s_first > s_last)) { + puts ("- no sectors to erase\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + putc ('\n'); + } + + + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_SIBLEY: + flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE); + flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM); + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + flash_unlock_seq (info, sect); + flash_write_cmd (info, sect, AMD_ADDR_ERASE_START, + AMD_CMD_ERASE_START); + flash_unlock_seq (info, sect); + flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR); + break; + default: + debug ("Unkown flash vendor %d\n", + info->vendor); + break; + } + + if (flash_full_status_check + (info, sect, info->erase_blk_tout, "erase")) { + rcode = 1; + } else + putc ('.'); + } + } + puts (" done\n"); + return rcode; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id != FLASH_MAN_CFI) { + puts ("missing or unknown FLASH type\n"); + return; + } + + printf ("CFI conformant FLASH (%d x %d)", + (info->portwidth << 3), (info->chipwidth << 3)); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", + info->erase_blk_tout, + info->write_tout, + info->buffer_write_tout, + info->buffer_size); + + puts (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { +#ifdef CFG_FLASH_EMPTY_INFO + int k; + int size; + int erased; + volatile unsigned long *flash; + + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *) info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n"); + /* print empty and read-only info */ + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " "); +#else /* ! CFG_FLASH_EMPTY_INFO */ + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); +#endif + } + putc ('\n'); + return; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp; + ulong cp; + int aln; + cfiword_t cword; + int i, rc; + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + int buffered_size; +#endif + /* get lower aligned address */ + wp = (addr & ~(info->portwidth - 1)); + + /* handle unaligned start */ + if ((aln = addr - wp) != 0) { + cword.l = 0; + cp = wp; + for (i = 0; i < aln; ++i, ++cp) + flash_add_byte (info, &cword, (*(uchar *) cp)); + + for (; (i < info->portwidth) && (cnt > 0); i++) { + flash_add_byte (info, &cword, *src++); + cnt--; + cp++; + } + for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) + flash_add_byte (info, &cword, (*(uchar *) cp)); + if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + return rc; + wp = cp; + } + + /* handle the aligned part */ +#ifdef CFG_FLASH_USE_BUFFER_WRITE + buffered_size = (info->portwidth / info->chipwidth); + buffered_size *= info->buffer_size; + while (cnt >= info->portwidth) { + /* prohibit buffer write when buffer_size is 1 */ + if (info->buffer_size == 1) { + cword.l = 0; + for (i = 0; i < info->portwidth; i++) + flash_add_byte (info, &cword, *src++); + if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + continue; + } + + /* write buffer until next buffered_size aligned boundary */ + i = buffered_size - (wp % buffered_size); + if (i > cnt) + i = cnt; + if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) + return rc; + i -= i & (info->portwidth - 1); + wp += i; + src += i; + cnt -= i; + } +#else + while (cnt >= info->portwidth) { + cword.l = 0; + for (i = 0; i < info->portwidth; i++) { + flash_add_byte (info, &cword, *src++); + } + if ((rc = flash_write_cfiword (info, wp, cword)) != 0) + return rc; + wp += info->portwidth; + cnt -= info->portwidth; + } +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + cword.l = 0; + for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { + flash_add_byte (info, &cword, *src++); + --cnt; + } + for (; i < info->portwidth; ++i, ++cp) { + flash_add_byte (info, &cword, (*(uchar *) cp)); + } + return flash_write_cfiword (info, wp, cword); +} + +/*----------------------------------------------------------------------- + */ +#ifdef CFG_FLASH_PROTECTION + +int flash_real_protect (flash_info_t * info, long sector, int prot) +{ + int retcode = 0; + + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); + if (prot) + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + if ((retcode = + flash_full_status_check (info, sector, info->erase_blk_tout, + prot ? "protect" : "unprotect")) == 0) { + + info->protect[sector] = prot; + + /* + * On some of Intel's flash chips (marked via legacy_unlock) + * unprotect unprotects all locking. + */ + if ((prot == 0) && (info->legacy_unlock)) { + flash_sect_t i; + for (i = 0; i < info->sector_count; i++) { + if (info->protect[i]) + flash_real_protect (info, i, 1); + } + } + } + return retcode; +} +/*----------------------------------------------------------------------- + * flash_read_user_serial - read the OneTimeProgramming cells + */ +void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, + int len) +{ + uchar *src; + uchar *dst; + + dst = buffer; + src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION); + flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); + memcpy (dst, src + offset, len); + flash_write_cmd (info, 0, 0, info->cmd_reset); +} + +/* + * flash_read_factory_serial - read the device Id from the protection area + */ +void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, + int len) +{ + uchar *src; + + src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION); + flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); + memcpy (buffer, src + offset, len); + flash_write_cmd (info, 0, 0, info->cmd_reset); +} + +#endif /* CFG_FLASH_PROTECTION */ + +/* + * flash_is_busy - check to see if the flash is busy + * This routine checks the status of the chip and returns true if the chip is busy + */ +static int flash_is_busy (flash_info_t * info, flash_sect_t sect) +{ + int retval; + + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_SIBLEY: + retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); + break; + default: + retval = 0; + } + debug ("flash_is_busy: %d\n", retval); + return retval; +} + +/*----------------------------------------------------------------------- + * wait for XSR.7 to be set. Time out with an error if it does not. + * This routine does not set the flash to read-array mode. + */ +static int flash_status_check (flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt) +{ + ulong start; + +#if CFG_HZ != 1000 + tout *= CFG_HZ/1000; +#endif + + /* Wait for command completion */ + start = get_timer (0); + while (flash_is_busy (info, sector)) { + if (get_timer (start) > tout) { + printf ("Flash %s timeout at address %lx data %lx\n", + prompt, info->start[sector], + flash_read_long (info, sector, 0)); + flash_write_cmd (info, sector, 0, info->cmd_reset); + return ERR_TIMOUT; + } + udelay (1); /* also triggers watchdog */ + } + return ERR_OK; +} + +/*----------------------------------------------------------------------- + * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. + * This routine sets the flash to read-array mode. + */ +static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, + ulong tout, char *prompt) +{ + int retcode; + + retcode = flash_status_check (info, sector, tout, prompt); + switch (info->vendor) { + case CFI_CMDSET_INTEL_SIBLEY: + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_STANDARD: + if ((retcode != ERR_OK) + && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { + retcode = ERR_INVAL; + printf ("Flash %s error at address %lx\n", prompt, + info->start[sector]); + if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) { + puts ("Command Sequence Error.\n"); + } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) { + puts ("Block Erase Error.\n"); + retcode = ERR_NOT_ERASED; + } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) { + puts ("Locking Error\n"); + } + if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { + puts ("Block locked.\n"); + retcode = ERR_PROTECTED; + } + if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) + puts ("Vpp Low Error.\n"); + } + flash_write_cmd (info, sector, 0, info->cmd_reset); + break; + default: + break; + } + return retcode; +} + +/*----------------------------------------------------------------------- + */ +static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) +{ +#if defined(__LITTLE_ENDIAN) + unsigned short w; + unsigned int l; + unsigned long long ll; +#endif + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cword->c = c; + break; + case FLASH_CFI_16BIT: +#if defined(__LITTLE_ENDIAN) + w = c; + w <<= 8; + cword->w = (cword->w >> 8) | w; +#else + cword->w = (cword->w << 8) | c; +#endif + break; + case FLASH_CFI_32BIT: +#if defined(__LITTLE_ENDIAN) + l = c; + l <<= 24; + cword->l = (cword->l >> 8) | l; +#else + cword->l = (cword->l << 8) | c; +#endif + break; + case FLASH_CFI_64BIT: +#if defined(__LITTLE_ENDIAN) + ll = c; + ll <<= 56; + cword->ll = (cword->ll >> 8) | ll; +#else + cword->ll = (cword->ll << 8) | c; +#endif + break; + } +} + + +/*----------------------------------------------------------------------- + * make a proper sized command based on the port and chip widths + */ +static void flash_make_cmd (flash_info_t * info, ulong cmd, void *cmdbuf) +{ + int i; + +#if defined(__LITTLE_ENDIAN) + ushort stmpw; + uint stmpi; +#endif + uchar *cp = (uchar *) cmdbuf; + + /* Store cmd in proper location based on chip width and port width + * cmd might be >1 byte in which case, we locate the proper part of + * cmd to store into the cmdbuf + */ + for (i = 0; i < info->portwidth; i++) { + *cp++ = ((i + 1) % info->chipwidth) ? cmd>>(8*(i+1)): cmd; + } +#if defined(__LITTLE_ENDIAN) + switch (info->portwidth) { + case FLASH_CFI_8BIT: + break; + case FLASH_CFI_16BIT: + stmpw = *(ushort *) cmdbuf; + *(ushort *) cmdbuf = __swab16 (stmpw); + break; + case FLASH_CFI_32BIT: + stmpi = *(uint *) cmdbuf; + *(uint *) cmdbuf = __swab32 (stmpi); + break; + default: + debug ("WARNING: flash_make_cmd: unsuppported LittleEndian mode\n"); + break; + } +#endif +} + + +/* + * Write a proper sized command to the correct address + */ +static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, ulong cmd) +{ + + volatile cfiptr_t addr; + cfiword_t cword; + + addr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd, + cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + *addr.cp = cword.c; +#ifdef CONFIG_BLACKFIN + asm("ssync;"); +#endif + break; + case FLASH_CFI_16BIT: + debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp, + cmd, cword.w, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + *addr.wp = cword.w; +#ifdef CONFIG_BLACKFIN + asm("ssync;"); +#endif + break; + case FLASH_CFI_32BIT: + debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp, + cmd, cword.l, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + *addr.lp = cword.l; +#ifdef CONFIG_BLACKFIN + asm("ssync;"); +#endif + break; + case FLASH_CFI_64BIT: +#ifdef DEBUG + { + char str[20]; + + print_longlong (str, cword.ll); + + debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", + addr.llp, cmd, str, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + } +#endif + *addr.llp = cword.ll; +#ifdef CONFIG_BLACKFIN + asm("ssync;"); +#endif + break; + } +} + +static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) +{ + flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START); + flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK); +} + +/*----------------------------------------------------------------------- + */ +static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + + debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + debug ("is= %x %x\n", cptr.cp[0], cword.c); + retval = (cptr.cp[0] == cword.c); + break; + case FLASH_CFI_16BIT: + debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w); + retval = (cptr.wp[0] == cword.w); + break; + case FLASH_CFI_32BIT: + debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l); + retval = (cptr.lp[0] == cword.l); + break; + case FLASH_CFI_64BIT: +#ifdef DEBUG + { + char str1[20]; + char str2[20]; + + print_longlong (str1, cptr.llp[0]); + print_longlong (str2, cword.ll); + debug ("is= %s %s\n", str1, str2); + } +#endif + retval = (cptr.llp[0] == cword.ll); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + */ +static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) == cword.l); + break; + case FLASH_CFI_64BIT: + retval = ((cptr.llp[0] & cword.ll) == cword.ll); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + */ +static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd) +{ + cfiptr_t cptr; + cfiword_t cword; + int retval; + + cptr.cp = flash_make_addr (info, sect, offset); + flash_make_cmd (info, cmd, &cword); + switch (info->portwidth) { + case FLASH_CFI_8BIT: + retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c)); + break; + case FLASH_CFI_16BIT: + retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w)); + break; + case FLASH_CFI_32BIT: + retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l)); + break; + case FLASH_CFI_64BIT: + retval = ((cptr.llp[0] & cword.ll) != + (cptr.llp[0] & cword.ll)); + break; + default: + retval = 0; + break; + } + return retval; +} + +/*----------------------------------------------------------------------- + * detect if flash is compatible with the Common Flash Interface (CFI) + * http://www.jedec.org/download/search/jesd68.pdf + * +*/ +static int flash_detect_cfi (flash_info_t * info) +{ + debug ("flash detect cfi\n"); + + for (info->portwidth = CFG_FLASH_CFI_WIDTH; + info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { + for (info->chipwidth = FLASH_CFI_BY8; + info->chipwidth <= info->portwidth; + info->chipwidth <<= 1) { + flash_write_cmd (info, 0, 0, info->cmd_reset); + flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); + if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') + && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') + && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { + info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE); + debug ("device interface is %d\n", + info->interface); + debug ("found port %d chip %d ", + info->portwidth, info->chipwidth); + debug ("port %d bits chip %d bits\n", + info->portwidth << CFI_FLASH_SHIFT_WIDTH, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + return 1; + } + } + } + debug ("not found\n"); + return 0; +} + +/* + * The following code cannot be run from FLASH! + * + */ +ulong flash_get_size (ulong base, int banknum) +{ + flash_info_t *info = &flash_info[banknum]; + int i, j; + flash_sect_t sect_cnt; + unsigned long sector; + unsigned long tmp; + int size_ratio; + uchar num_erase_regions; + int erase_region_size; + int erase_region_count; +#ifdef CFG_FLASH_PROTECTION + int ext_addr; + info->legacy_unlock = 0; +#endif + + info->start[0] = base; + + if (flash_detect_cfi (info)) { + info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR); +#ifdef DEBUG + flash_printqry (info, 0); +#endif + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_SIBLEY: + default: + info->cmd_reset = FLASH_CMD_RESET; +#ifdef CFG_FLASH_PROTECTION + /* read legacy lock/unlock bit from intel flash */ + ext_addr = flash_read_ushort (info, 0, + FLASH_OFFSET_EXT_QUERY_T_P_ADDR); + info->legacy_unlock = + flash_read_uchar (info, ext_addr + 5) & 0x08; +#endif + break; + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + info->cmd_reset = AMD_CMD_RESET; + break; + } + + debug ("manufacturer is %d\n", info->vendor); + size_ratio = info->portwidth / info->chipwidth; + /* if the chip is x8/x16 reduce the ratio by half */ + if ((info->interface == FLASH_CFI_X8X16) + && (info->chipwidth == FLASH_CFI_BY8)) { + size_ratio >>= 1; + } + num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS); + debug ("size_ratio %d port %d bits chip %d bits\n", + size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, + info->chipwidth << CFI_FLASH_SHIFT_WIDTH); + debug ("found %d erase regions\n", num_erase_regions); + sect_cnt = 0; + sector = base; + for (i = 0; i < num_erase_regions; i++) { + if (i > NUM_ERASE_REGIONS) { + printf ("%d erase regions found, only %d used\n", + num_erase_regions, NUM_ERASE_REGIONS); + break; + } + tmp = flash_read_long (info, 0, + FLASH_OFFSET_ERASE_REGIONS + + i * 4); + erase_region_size = + (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; + tmp >>= 16; + erase_region_count = (tmp & 0xffff) + 1; + debug ("erase_region_count = %d erase_region_size = %d\n", + erase_region_count, erase_region_size); + for (j = 0; j < erase_region_count; j++) { + info->start[sect_cnt] = sector; + sector += (erase_region_size * size_ratio); + /* + * Only read protection status from supported devices (intel...) + */ + switch (info->vendor) { + case CFI_CMDSET_INTEL_SIBLEY: + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_STANDARD: + + info->protect[sect_cnt] = + flash_isset (info, sect_cnt, + FLASH_OFFSET_PROTECT, + FLASH_STATUS_PROTECT); + break; + default: + info->protect[sect_cnt] = 0; /* default: not protected */ + } + + sect_cnt++; + } + } + + info->sector_count = sect_cnt; + /* multiply the size by the number of chips */ + info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio; + info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE)); + tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); + info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); + tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT)) * + (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)); + info->buffer_write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */ + tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) * + (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT)); + info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */ + info->flash_id = FLASH_MAN_CFI; + if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { + info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */ + } + } + + flash_write_cmd (info, 0, 0, info->cmd_reset); + return (info->size); +} + +/* loop through the sectors from the highest address + * when the passed address is greater or equal to the sector address + * we have a match + */ +static flash_sect_t find_sector (flash_info_t * info, ulong addr) +{ + flash_sect_t sector; + + for (sector = info->sector_count - 1; sector >= 0; sector--) { + if (addr >= info->start[sector]) + break; + } + return sector; +} + +/*----------------------------------------------------------------------- + */ +static int flash_write_cfiword(flash_info_t * info, ulong dest, + cfiword_t cword) +{ + cfiptr_t ctladdr; + cfiptr_t cptr; + int flag; + + ctladdr.cp = flash_make_addr (info, 0, 0); + cptr.cp = (uchar *) dest; + + + /* Check if Flash is (sufficiently) erased */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + flag = ((cptr.cp[0] & cword.c) == cword.c); + break; + case FLASH_CFI_16BIT: + flag = ((cptr.wp[0] & cword.w) == cword.w); + break; + case FLASH_CFI_32BIT: + flag = ((cptr.lp[0] & cword.l) == cword.l); + break; + case FLASH_CFI_64BIT: + flag = ((cptr.llp[0] & cword.ll) == cword.ll); + break; + default: + return 2; + } + if (!flag) + return 2; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + switch (info->vendor) { + case CFI_CMDSET_INTEL_SIBLEY: + flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE_S); + break; + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_STANDARD: + flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); + break; + case CFI_CMDSET_AMD_EXTENDED: + case CFI_CMDSET_AMD_STANDARD: + flash_unlock_seq (info, 0); + flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE); + break; + } + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cptr.cp[0] = cword.c; + break; + case FLASH_CFI_16BIT: + cptr.wp[0] = cword.w; + break; + case FLASH_CFI_32BIT: + cptr.lp[0] = cword.l; + break; + case FLASH_CFI_64BIT: + cptr.llp[0] = cword.ll; + break; + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + return flash_full_status_check (info, find_sector (info, dest), + info->write_tout, "write"); +} + +#ifdef CFG_FLASH_USE_BUFFER_WRITE + +static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, + int len) +{ + flash_sect_t sector; + int cnt, buffered_size=0; + int retcode; + volatile cfiptr_t src; + volatile cfiptr_t dst; + volatile int shift_bits; + + switch (info->vendor) { + case CFI_CMDSET_INTEL_STANDARD: + case CFI_CMDSET_INTEL_EXTENDED: + case CFI_CMDSET_INTEL_SIBLEY: + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector (info, dest); + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + if(info->vendor == CFI_CMDSET_INTEL_SIBLEY){ + flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER_S); + } + else { + flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); + } +/* This seems like out of place for flash. Actually not sending status command + * Check once + */ +#if 0 + if ((retcode = flash_status_check (info, sector, info->buffer_write_tout, + "write to buffer")) == ERR_OK) { +#else + retcode = ERR_OK; + if(retcode == ERR_OK) { +#endif + /* reduce the number of loops by the width of the port */ + switch (info->portwidth) { + case FLASH_CFI_8BIT: + shift_bits = 0; + break; + case FLASH_CFI_16BIT: + shift_bits = 1; + break; + case FLASH_CFI_32BIT: + shift_bits = 2; + break; + case FLASH_CFI_64BIT: + shift_bits = 3; + break; + default: + return ERR_INVAL; + break; + } + + cnt = len >> shift_bits; + /* + * if there are trailing bytes to write(non-aligned end).. + * then do one more word write + */ + if (len & ((0x1 << shift_bits) - 1)) + cnt++; + /* + * It is found that buffered programming works only if the size of the buffer written is + * the size of write buffer on Sibley NOR.. + * REVISIT: why this is happening.Also see if it is the case with STRATA NOR + */ + if (info->vendor == CFI_CMDSET_INTEL_SIBLEY) { + buffered_size = (info->portwidth / info->chipwidth); + buffered_size *= info->buffer_size; + buffered_size >>= shift_bits; + flash_write_cmd (info, sector, 0, (uchar) buffered_size - 1); + buffered_size -=cnt; + } else + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + + while (cnt-- > 0) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = *src.lp++; + break; + case FLASH_CFI_64BIT: + *dst.llp++ = *src.llp++; + break; + default: + return ERR_INVAL; + break; + } + } + if (info->vendor == CFI_CMDSET_INTEL_SIBLEY) { + while (buffered_size-- > 0) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + *dst.cp++ = 0; + break; + case FLASH_CFI_16BIT: + *dst.wp++ = 0; + break; + case FLASH_CFI_32BIT: + *dst.lp++ = 0; + break; + case FLASH_CFI_64BIT: + *dst.llp++ = 0; + break; + default: + return ERR_INVAL; + break; + } + } + } + flash_write_cmd (info, sector, 0, + FLASH_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check (info, sector, + info->buffer_write_tout, + "buffer write"); + } + return retcode; + + case CFI_CMDSET_AMD_STANDARD: + case CFI_CMDSET_AMD_EXTENDED: + src.cp = cp; + dst.cp = (uchar *) dest; + sector = find_sector (info, dest); + + flash_unlock_seq(info,0); + flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER); + + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cnt = len; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.cp++ = *src.cp++; + break; + case FLASH_CFI_16BIT: + cnt = len >> 1; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.wp++ = *src.wp++; + break; + case FLASH_CFI_32BIT: + cnt = len >> 2; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.lp++ = *src.lp++; + break; + case FLASH_CFI_64BIT: + cnt = len >> 3; + flash_write_cmd (info, sector, 0, (uchar) cnt - 1); + while (cnt-- > 0) *dst.llp++ = *src.llp++; + break; + default: + return ERR_INVAL; + } + + flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); + retcode = flash_full_status_check (info, sector, info->buffer_write_tout, + "buffer write"); + return retcode; + + default: + debug ("Unknown Command Set\n"); + return ERR_INVAL; + } +} + +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CFG_FLASH_CFI */ + diff --git a/drivers/cs8900.c b/drivers/cs8900.c new file mode 100644 index 000000000..082434ca2 --- /dev/null +++ b/drivers/cs8900.c @@ -0,0 +1,322 @@ +/* + * Cirrus Logic CS8900A Ethernet + * + * (C) 2003 Wolfgang Denk, wd@denx.de + * Extension to synchronize ethaddr environment variable + * against value in EEPROM + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copyright (C) 1999 Ben Williamson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is loaded into SRAM in bootstrap mode, where it waits + * for commands on UART1 to read and write memory, jump to code etc. + * A design goal for this program is to be entirely independent of the + * target board. Anything with a CL-PS7111 or EP7211 should be able to run + * this code in bootstrap mode. All the board specifics can be handled on + * the host. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include "cs8900.h" +#include + +#ifdef CONFIG_DRIVER_CS8900 + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +#undef DEBUG + +/* packet page register access functions */ + +#ifdef CS8900_BUS32 +/* we don't need 16 bit initialisation on 32 bit bus */ +#define get_reg_init_bus(x) get_reg((x)) +#else +static unsigned short get_reg_init_bus (int regno) +{ + /* force 16 bit busmode */ + volatile unsigned char c; + + c = CS8900_BUS16_0; + c = CS8900_BUS16_1; + c = CS8900_BUS16_0; + c = CS8900_BUS16_1; + c = CS8900_BUS16_0; + + CS8900_PPTR = regno; + return (unsigned short) CS8900_PDATA; +} +#endif + +static unsigned short get_reg (int regno) +{ + CS8900_PPTR = regno; + return (unsigned short) CS8900_PDATA; +} + + +static void put_reg (int regno, unsigned short val) +{ + CS8900_PPTR = regno; + CS8900_PDATA = val; +} + +static void eth_reset (void) +{ + int tmo; + unsigned short us; + + /* reset NIC */ + put_reg (PP_SelfCTL, get_reg (PP_SelfCTL) | PP_SelfCTL_Reset); + + /* wait for 200ms */ + udelay (200000); + /* Wait until the chip is reset */ + + tmo = get_timer (0) + 1 * CFG_HZ; + while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0) + && tmo < get_timer (0)) + /*NOP*/; +} + +static void eth_reginit (void) +{ + /* receive only error free packets addressed to this card */ + put_reg (PP_RxCTL, PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK); + /* do not generate any interrupts on receive operations */ + put_reg (PP_RxCFG, 0); + /* do not generate any interrupts on transmit operations */ + put_reg (PP_TxCFG, 0); + /* do not generate any interrupts on buffer operations */ + put_reg (PP_BufCFG, 0); + /* enable transmitter/receiver mode */ + put_reg (PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx); +} + +void cs8900_get_enetaddr (uchar * addr) +{ + int i; + unsigned char env_enetaddr[6]; + char *tmp = getenv ("ethaddr"); + char *end; + + for (i=0; i<6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + + /* verify chip id */ + if (get_reg_init_bus (PP_ChipID) != 0x630e) + return; + eth_reset (); + if ((get_reg (PP_SelfST) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) == + (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) { + + /* Load the MAC from EEPROM */ + for (i = 0; i < 6 / 2; i++) { + unsigned int Addr; + + Addr = get_reg (PP_IA + i * 2); + addr[i * 2] = Addr & 0xFF; + addr[i * 2 + 1] = Addr >> 8; + } + + if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 && + memcmp(env_enetaddr, addr, 6) != 0) { + printf ("\nWarning: MAC addresses don't match:\n"); + printf ("\tHW MAC address: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + addr[0], addr[1], + addr[2], addr[3], + addr[4], addr[5] ); + printf ("\t\"ethaddr\" value: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + env_enetaddr[0], env_enetaddr[1], + env_enetaddr[2], env_enetaddr[3], + env_enetaddr[4], env_enetaddr[5]) ; + debug ("### Set MAC addr from environment\n"); + memcpy (addr, env_enetaddr, 6); + } + if (!tmp) { + char ethaddr[20]; + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + addr[0], addr[1], + addr[2], addr[3], + addr[4], addr[5]) ; + debug ("### Set environment from HW MAC addr = \"%s\"\n", ethaddr); + setenv ("ethaddr", ethaddr); + } + + } +} + +void eth_halt (void) +{ + /* disable transmitter/receiver mode */ + put_reg (PP_LineCTL, 0); + + /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */ + get_reg_init_bus (PP_ChipID); +} + +int eth_init (bd_t * bd) +{ + + /* verify chip id */ + if (get_reg_init_bus (PP_ChipID) != 0x630e) { + printf ("CS8900 Ethernet chip not found?!\n"); + return 0; + } + + eth_reset (); + /* set the ethernet address */ + put_reg (PP_IA + 0, bd->bi_enetaddr[0] | (bd->bi_enetaddr[1] << 8)); + put_reg (PP_IA + 2, bd->bi_enetaddr[2] | (bd->bi_enetaddr[3] << 8)); + put_reg (PP_IA + 4, bd->bi_enetaddr[4] | (bd->bi_enetaddr[5] << 8)); + + eth_reginit (); + return 0; +} + +/* Get a data block via Ethernet */ +extern int eth_rx (void) +{ + int i; + unsigned short rxlen; + unsigned short *addr; + unsigned short status; + + status = get_reg (PP_RER); + + if ((status & PP_RER_RxOK) == 0) + return 0; + + status = CS8900_RTDATA; /* stat */ + rxlen = CS8900_RTDATA; /* len */ + +#ifdef DEBUG + if (rxlen > PKTSIZE_ALIGN + PKTALIGN) + printf ("packet too big!\n"); +#endif + for (addr = (unsigned short *) NetRxPackets[0], i = rxlen >> 1; i > 0; + i--) + *addr++ = CS8900_RTDATA; + if (rxlen & 1) + *addr++ = CS8900_RTDATA; + + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], rxlen); + + return rxlen; +} + +/* Send a data block via Ethernet. */ +extern int eth_send (volatile void *packet, int length) +{ + volatile unsigned short *addr; + int tmo; + unsigned short s; + +retry: + /* initiate a transmit sequence */ + CS8900_TxCMD = PP_TxCmd_TxStart_Full; + CS8900_TxLEN = length; + + /* Test to see if the chip has allocated memory for the packet */ + if ((get_reg (PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) { + /* Oops... this should not happen! */ +#ifdef DEBUG + printf ("cs: unable to send packet; retrying...\n"); +#endif + for (tmo = get_timer (0) + 5 * CFG_HZ; get_timer (0) < tmo;) + /*NOP*/; + eth_reset (); + eth_reginit (); + goto retry; + } + + /* Write the contents of the packet */ + /* assume even number of bytes */ + for (addr = packet; length > 0; length -= 2) + CS8900_RTDATA = *addr++; + + /* wait for transfer to succeed */ + tmo = get_timer (0) + 5 * CFG_HZ; + while ((s = get_reg (PP_TER) & ~0x1F) == 0) { + if (get_timer (0) >= tmo) + break; + } + + /* nothing */ ; + if ((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) { +#ifdef DEBUG + printf ("\ntransmission error %#x\n", s); +#endif + } + + return 0; +} + +static void cs8900_e2prom_ready(void) +{ + while(get_reg(PP_SelfST) & SI_BUSY); +} + +/***********************************************************/ +/* read a 16-bit word out of the EEPROM */ +/***********************************************************/ + +int cs8900_e2prom_read(unsigned char addr, unsigned short *value) +{ + cs8900_e2prom_ready(); + put_reg(PP_EECMD, EEPROM_READ_CMD | addr); + cs8900_e2prom_ready(); + *value = get_reg(PP_EEData); + + return 0; +} + + +/***********************************************************/ +/* write a 16-bit word into the EEPROM */ +/***********************************************************/ + +int cs8900_e2prom_write(unsigned char addr, unsigned short value) +{ + cs8900_e2prom_ready(); + put_reg(PP_EECMD, EEPROM_WRITE_EN); + cs8900_e2prom_ready(); + put_reg(PP_EEData, value); + put_reg(PP_EECMD, EEPROM_WRITE_CMD | addr); + cs8900_e2prom_ready(); + put_reg(PP_EECMD, EEPROM_WRITE_DIS); + cs8900_e2prom_ready(); + + return 0; +} + +#endif /* COMMANDS & CFG_NET */ + +#endif /* CONFIG_DRIVER_CS8900 */ diff --git a/drivers/cs8900.h b/drivers/cs8900.h new file mode 100644 index 000000000..f886d103c --- /dev/null +++ b/drivers/cs8900.h @@ -0,0 +1,258 @@ +/* + * Cirrus Logic CS8900A Ethernet + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Copyright (C) 1999 Ben Williamson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is loaded into SRAM in bootstrap mode, where it waits + * for commands on UART1 to read and write memory, jump to code etc. + * A design goal for this program is to be entirely independent of the + * target board. Anything with a CL-PS7111 or EP7211 should be able to run + * this code in bootstrap mode. All the board specifics can be handled on + * the host. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +#ifdef CONFIG_DRIVER_CS8900 + +/* although the registers are 16 bit, they are 32-bit aligned on the + EDB7111. so we have to read them as 32-bit registers and ignore the + upper 16-bits. i'm not sure if this holds for the EDB7211. */ + +#ifdef CS8900_BUS16 + /* 16 bit aligned registers, 16 bit wide */ + #define CS8900_REG u16 + #define CS8900_OFF 0x02 + #define CS8900_BUS16_0 *(volatile u8 *)(CS8900_BASE+0x00) + #define CS8900_BUS16_1 *(volatile u8 *)(CS8900_BASE+0x01) +#elif defined(CS8900_BUS32) + /* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */ + #define CS8900_REG u32 + #define CS8900_OFF 0x04 +#else + #error unknown bussize ... +#endif + +#define CS8900_RTDATA *(volatile CS8900_REG *)(CS8900_BASE+0x00*CS8900_OFF) +#define CS8900_TxCMD *(volatile CS8900_REG *)(CS8900_BASE+0x02*CS8900_OFF) +#define CS8900_TxLEN *(volatile CS8900_REG *)(CS8900_BASE+0x03*CS8900_OFF) +#define CS8900_ISQ *(volatile CS8900_REG *)(CS8900_BASE+0x04*CS8900_OFF) +#define CS8900_PPTR *(volatile CS8900_REG *)(CS8900_BASE+0x05*CS8900_OFF) +#define CS8900_PDATA *(volatile CS8900_REG *)(CS8900_BASE+0x06*CS8900_OFF) + + +#define ISQ_RxEvent 0x04 +#define ISQ_TxEvent 0x08 +#define ISQ_BufEvent 0x0C +#define ISQ_RxMissEvent 0x10 +#define ISQ_TxColEvent 0x12 +#define ISQ_EventMask 0x3F + +/* packet page register offsets */ + +/* bus interface registers */ +#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */ +#define PP_ChipRev 0x0002 /* Chip revision, model codes */ + +#define PP_IntReg 0x0022 /* Interrupt configuration */ +#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */ +#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */ +#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */ +#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */ + +/* status and control registers */ + +#define PP_RxCFG 0x0102 /* Receiver configuration */ +#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */ +#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */ +#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */ +#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */ +#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */ +#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */ +#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */ +#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */ +#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */ + +#define PP_RxCTL 0x0104 /* Receiver control */ +#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */ +#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */ +#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */ +#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */ +#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */ +#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */ +#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */ +#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */ +#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */ + +#define PP_TxCFG 0x0106 /* Transmit configuration */ +#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */ +#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */ +#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */ +#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */ +#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */ +#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */ +#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */ + +#define PP_TxCmd 0x0108 /* Transmit command status */ +#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */ +#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */ +#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */ +#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */ +#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */ +#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */ +#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */ +#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */ + +#define PP_BufCFG 0x010A /* Buffer configuration */ +#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */ +#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */ +#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */ +#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */ +#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */ +#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */ +#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */ +#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */ +#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */ + +#define PP_LineCTL 0x0112 /* Line control */ +#define PP_LineCTL_Rx 0x0040 /* Enable receiver */ +#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */ +#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */ +#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */ +#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */ +#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */ +#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */ +#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */ + +#define PP_SelfCTL 0x0114 /* Chip self control */ +#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */ +#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */ +#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */ +#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */ +#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */ +#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */ +#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */ +#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */ + +#define PP_BusCTL 0x0116 /* Bus control */ +#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */ +#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */ +#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */ +#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */ +#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */ +#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */ +#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */ +#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */ + +#define PP_TestCTL 0x0118 /* Test control */ +#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */ +#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */ +#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */ +#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */ +#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */ + +#define PP_ISQ 0x0120 /* Interrupt Status Queue */ + +#define PP_RER 0x0124 /* Receive event */ +#define PP_RER_IAHash 0x0040 /* Frame hash match */ +#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */ +#define PP_RER_RxOK 0x0100 /* Frame received with no errors */ +#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */ +#define PP_RER_IA 0x0400 /* Frame address matched IA */ +#define PP_RER_Broadcast 0x0800 /* Broadcast frame */ +#define PP_RER_CRC 0x1000 /* Frame had CRC error */ +#define PP_RER_RUNT 0x2000 /* Runt frame */ +#define PP_RER_EXTRA 0x4000 /* Frame was too long */ + +#define PP_TER 0x0128 /* Transmit event */ +#define PP_TER_CRS 0x0040 /* Carrier lost */ +#define PP_TER_SQE 0x0080 /* Signal Quality Error */ +#define PP_TER_TxOK 0x0100 /* Packet sent without error */ +#define PP_TER_Late 0x0200 /* Out of window */ +#define PP_TER_Jabber 0x0400 /* Stuck transmit? */ +#define PP_TER_NumCollisions 0x7800 /* Number of collisions */ +#define PP_TER_16Collisions 0x8000 /* > 16 collisions */ + +#define PP_BER 0x012C /* Buffer event */ +#define PP_BER_SWint 0x0040 /* Software interrupt */ +#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */ +#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */ +#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */ +#define PP_BER_RxMiss 0x0400 /* Received frame missed */ +#define PP_BER_Rx128 0x0800 /* 128 bytes received */ +#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */ + +#define PP_RxMiss 0x0130 /* Receiver miss counter */ + +#define PP_TxCol 0x0132 /* Transmit collision counter */ + +#define PP_LineSTAT 0x0134 /* Line status */ +#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */ +#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */ +#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */ +#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */ +#define PP_LineSTAT_CRS 0x4000 /* Frame being received */ + +#define PP_SelfSTAT 0x0136 /* Chip self status */ +#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */ +#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */ +#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */ +#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */ +#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */ +#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */ +#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */ + +#define PP_BusSTAT 0x0138 /* Bus status */ +#define PP_BusSTAT_TxBid 0x0080 /* Tx error */ +#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */ + +#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */ + +/* initiate transmit registers */ + +#define PP_TxCommand 0x0144 /* Tx Command */ +#define PP_TxLength 0x0146 /* Tx Length */ + + +/* address filter registers */ + +#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */ +#define PP_IA 0x0158 /* Individual address (MAC) */ + +/* EEPROM Kram */ +#define SI_BUSY 0x0100 +#define PP_SelfST 0x0136 /* Self State register */ +#define PP_EECMD 0x0040 /* NVR Interface Command register */ +#define PP_EEData 0x0042 /* NVR Interface Data Register */ +#define EEPROM_WRITE_EN 0x00F0 +#define EEPROM_WRITE_DIS 0x0000 +#define EEPROM_WRITE_CMD 0x0100 +#define EEPROM_READ_CMD 0x0200 +#define EEPROM_ERASE_CMD 0x0300 + +extern int cs8900_e2prom_read(uchar, ushort *); +extern int cs8900_e2prom_write(uchar, ushort); + +#endif /* CONFIG_DRIVER_CS8900 */ diff --git a/drivers/ct69000.c b/drivers/ct69000.c new file mode 100644 index 000000000..29d82e4c4 --- /dev/null +++ b/drivers/ct69000.c @@ -0,0 +1,1286 @@ +/* ported from ctfb.c (linux kernel): + * Created in Jan - July 2000 by Thomas Höhenleitner + * + * Ported to U-Boot: + * (C) Copyright 2002 Denis Peter, MPL AG Switzerland + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_VIDEO + +#include +#include +#include "videomodes.h" + +#ifdef CONFIG_VIDEO_CT69000 + +/* debug */ +#undef VGA_DEBUG +#undef VGA_DUMP_REG +#ifdef VGA_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +/* Macros */ +#ifndef min +#define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b ) +#endif +#ifndef max +#define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b ) +#endif +#ifdef minmax +#error "term minmax already used." +#endif +#define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) ) +#define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) ) + +/* CT Register Offsets */ +#define CT_AR_O 0x3c0 /* Index and Data write port of the attribute Registers */ +#define CT_GR_O 0x3ce /* Index port of the Graphic Controller Registers */ +#define CT_SR_O 0x3c4 /* Index port of the Sequencer Controller */ +#define CT_CR_O 0x3d4 /* Index port of the CRT Controller */ +#define CT_XR_O 0x3d6 /* Extended Register index */ +#define CT_MSR_W_O 0x3c2 /* Misc. Output Register (write only) */ +#define CT_LUT_MASK_O 0x3c6 /* Color Palette Mask */ +#define CT_LUT_START_O 0x3c8 /* Color Palette Write Mode Index */ +#define CT_LUT_RGB_O 0x3c9 /* Color Palette Data Port */ +#define CT_STATUS_REG0_O 0x3c2 /* Status Register 0 (read only) */ +#define CT_STATUS_REG1_O 0x3da /* Input Status Register 1 (read only) */ + +#define CT_FP_O 0x3d0 /* Index port of the Flat panel Registers */ +#define CT_MR_O 0x3d2 /* Index Port of the Multimedia Extension */ + +/* defines for the memory mapped registers */ +#define BR00_o 0x400000 /* Source and Destination Span Register */ +#define BR01_o 0x400004 /* Pattern/Source Expansion Background Color & Transparency Key Register */ +#define BR02_o 0x400008 /* Pattern/Source Expansion Foreground Color Register */ +#define BR03_o 0x40000C /* Monochrome Source Control Register */ +#define BR04_o 0x400010 /* BitBLT Control Register */ +#define BR05_o 0x400014 /* Pattern Address Registe */ +#define BR06_o 0x400018 /* Source Address Register */ +#define BR07_o 0x40001C /* Destination Address Register */ +#define BR08_o 0x400020 /* Destination Width & Height Register */ +#define BR09_o 0x400024 /* Source Expansion Background Color & Transparency Key Register */ +#define BR0A_o 0x400028 /* Source Expansion Foreground Color Register */ + +#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ +#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ +#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ +#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ + +/* Some Mode definitions */ +#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_EXT 4 /* external sync */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ + /* vtotal = 144d/288n/576i => PAL */ + /* vtotal = 121d/242n/484i => NTSC */ +#define FB_SYNC_ON_GREEN 32 /* sync on green */ + +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +#define FB_VMODE_INTERLACED 1 /* interlaced */ +#define FB_VMODE_DOUBLE 2 /* double scan */ +#define FB_VMODE_MASK 255 + +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ +#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ + +#define text 0 +#define fntwidth 8 + +/* table for VGA Initialization */ +typedef struct { + const unsigned char reg; + const unsigned char val; +} CT_CFG_TABLE; + +/* this table provides some basic initialisations such as Memory Clock etc */ +static CT_CFG_TABLE xreg[] = { + {0x09, 0x01}, /* CRT Controller Extensions Enable */ + {0x0A, 0x02}, /* Frame Buffer Mapping */ + {0x0B, 0x01}, /* PCI Write Burst support */ + {0x20, 0x00}, /* BitBLT Configuration */ + {0x40, 0x03}, /* Memory Access Control */ + {0x60, 0x00}, /* Video Pin Control */ + {0x61, 0x00}, /* DPMS Synch control */ + {0x62, 0x00}, /* GPIO Pin Control */ + {0x63, 0xBD}, /* GPIO Pin Data */ + {0x67, 0x00}, /* Pin Tri-State */ + {0x80, 0x80}, /* Pixel Pipeline Config 0 register */ + {0xA0, 0x00}, /* Cursor 1 Control Reg */ + {0xA1, 0x00}, /* Cursor 1 Vertical Extension Reg */ + {0xA2, 0x00}, /* Cursor 1 Base Address Low */ + {0xA3, 0x00}, /* Cursor 1 Base Address High */ + {0xA4, 0x00}, /* Cursor 1 X-Position Low */ + {0xA5, 0x00}, /* Cursor 1 X-Position High */ + {0xA6, 0x00}, /* Cursor 1 Y-Position Low */ + {0xA7, 0x00}, /* Cursor 1 Y-Position High */ + {0xA8, 0x00}, /* Cursor 2 Control Reg */ + {0xA9, 0x00}, /* Cursor 2 Vertical Extension Reg */ + {0xAA, 0x00}, /* Cursor 2 Base Address Low */ + {0xAB, 0x00}, /* Cursor 2 Base Address High */ + {0xAC, 0x00}, /* Cursor 2 X-Position Low */ + {0xAD, 0x00}, /* Cursor 2 X-Position High */ + {0xAE, 0x00}, /* Cursor 2 Y-Position Low */ + {0xAF, 0x00}, /* Cursor 2 Y-Position High */ + {0xC0, 0x7D}, /* Dot Clock 0 VCO M-Divisor */ + {0xC1, 0x07}, /* Dot Clock 0 VCO N-Divisor */ + {0xC3, 0x34}, /* Dot Clock 0 Divisor select */ + {0xC4, 0x55}, /* Dot Clock 1 VCO M-Divisor */ + {0xC5, 0x09}, /* Dot Clock 1 VCO N-Divisor */ + {0xC7, 0x24}, /* Dot Clock 1 Divisor select */ + {0xC8, 0x7D}, /* Dot Clock 2 VCO M-Divisor */ + {0xC9, 0x07}, /* Dot Clock 2 VCO N-Divisor */ + {0xCB, 0x34}, /* Dot Clock 2 Divisor select */ + {0xCC, 0x38}, /* Memory Clock 0 VCO M-Divisor */ + {0xCD, 0x03}, /* Memory Clock 0 VCO N-Divisor */ + {0xCE, 0x90}, /* Memory Clock 0 Divisor select */ + {0xCF, 0x06}, /* Clock Config */ + {0xD0, 0x0F}, /* Power Down */ + {0xD1, 0x01}, /* Power Down BitBLT */ + {0xFF, 0xFF} /* end of table */ +}; +/* Clock Config: + * ============= + * + * PD Registers: + * ------------- + * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor. + * They are encoded as follows: + * + * +---+--------------+ + * | 2 | Loop Divisor | + * +---+--------------+ + * | 1 | 1 | + * +---+--------------+ + * | 0 | 4 | + * +---+--------------+ + * Note: The Memory Clock does not have a Loop Divisor. + * +---+---+---+--------------+ + * | 6 | 5 | 4 | Post Divisor | + * +---+---+---+--------------+ + * | 0 | 0 | 0 | 1 | + * +---+---+---+--------------+ + * | 0 | 0 | 1 | 2 | + * +---+---+---+--------------+ + * | 0 | 1 | 0 | 4 | + * +---+---+---+--------------+ + * | 0 | 1 | 1 | 8 | + * +---+---+---+--------------+ + * | 1 | 0 | 0 | 16 | + * +---+---+---+--------------+ + * | 1 | 0 | 1 | 32 | + * +---+---+---+--------------+ + * | 1 | 1 | X | reserved | + * +---+---+---+--------------+ + * + * All other bits are reserved in these registers. + * + * Clock VCO M Registers: + * ---------------------- + * These Registers contain the M Value -2. + * + * Clock VCO N Registers: + * ---------------------- + * These Registers contain the N Value -2. + * + * Formulas: + * --------- + * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz + * Fout = Fvco / Post Divisor + * + * Dot Clk0 (default 25MHz): + * ------------------------- + * Fvco = 14.318 * 127 / 9 = 202.045MHz + * Fout = 202.045MHz / 8 = 25.25MHz + * Post Divisor = 8 + * Loop Divisor = 1 + * XRC0 = (M - 2) = 125 = 0x7D + * XRC1 = (N - 2) = 7 = 0x07 + * XRC3 = 0x34 + * + * Dot Clk1 (default 28MHz): + * ------------------------- + * Fvco = 14.318 * 87 / 11 = 113.24MHz + * Fout = 113.24MHz / 4 = 28.31MHz + * Post Divisor = 4 + * Loop Divisor = 1 + * XRC4 = (M - 2) = 85 = 0x55 + * XRC5 = (N - 2) = 9 = 0x09 + * XRC7 = 0x24 + * + * Dot Clk2 (variable for extended modes set to 25MHz): + * ---------------------------------------------------- + * Fvco = 14.318 * 127 / 9 = 202.045MHz + * Fout = 202.045MHz / 8 = 25.25MHz + * Post Divisor = 8 + * Loop Divisor = 1 + * XRC8 = (M - 2) = 125 = 0x7D + * XRC9 = (N - 2) = 7 = 0x07 + * XRCB = 0x34 + * + * Memory Clk for most modes >50MHz: + * ---------------------------------- + * Fvco = 14.318 * 58 / 5 = 166MHz + * Fout = 166MHz / 2 = 83MHz + * Post Divisor = 2 + * XRCC = (M - 2) = 57 = 0x38 + * XRCD = (N - 2) = 3 = 0x03 + * XRCE = 0x90 + * + * Note Bit7 enables the clock source from the VCO + * + */ + +/******************************************************************* + * Chips struct + *******************************************************************/ +struct ctfb_chips_properties { + int device_id; /* PCI Device ID */ + unsigned long max_mem; /* memory for frame buffer */ + int vld_set; /* value of VLD if bit2 in clock control is set */ + int vld_not_set; /* value of VLD if bit2 in clock control is set */ + int mn_diff; /* difference between M/N Value + mn_diff = M/N Register */ + int mn_min; /* min value of M/N Value */ + int mn_max; /* max value of M/N Value */ + int vco_min; /* VCO Min in MHz */ + int vco_max; /* VCO Max in MHz */ +}; + +static const struct ctfb_chips_properties chips[] = { + {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220}, +#ifdef CONFIG_USE_CPCIDVI + {PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220}, +#endif + {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */ + {0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */ +}; + +/* + * The Graphic Device + */ +GraphicDevice ctfb; + +/******************************************************************************* +* +* Low Level Routines +*/ + +/******************************************************************************* +* +* Read CT ISA register +*/ +#ifdef VGA_DEBUG +static unsigned char +ctRead (unsigned short index) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + if (index == CT_AR_O) + /* synch the Flip Flop */ + in8 (pGD->isaBase + CT_STATUS_REG1_O); + + return (in8 (pGD->isaBase + index)); +} +#endif +/******************************************************************************* +* +* Write CT ISA register +*/ +static void +ctWrite (unsigned short index, unsigned char val) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + + out8 ((pGD->isaBase + index), val); +} + +/******************************************************************************* +* +* Read CT ISA register indexed +*/ +static unsigned char +ctRead_i (unsigned short index, char reg) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + if (index == CT_AR_O) + /* synch the Flip Flop */ + in8 (pGD->isaBase + CT_STATUS_REG1_O); + out8 ((pGD->isaBase + index), reg); + return (in8 (pGD->isaBase + index + 1)); +} + +/******************************************************************************* +* +* Write CT ISA register indexed +*/ +static void +ctWrite_i (unsigned short index, char reg, char val) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + if (index == CT_AR_O) { + /* synch the Flip Flop */ + in8 (pGD->isaBase + CT_STATUS_REG1_O); + out8 ((pGD->isaBase + index), reg); + out8 ((pGD->isaBase + index), val); + } else { + out8 ((pGD->isaBase + index), reg); + out8 ((pGD->isaBase + index + 1), val); + } +} + +/******************************************************************************* +* +* Write a table of CT ISA register +*/ +static void +ctLoadRegs (unsigned short index, CT_CFG_TABLE * regTab) +{ + while (regTab->reg != 0xFF) { + ctWrite_i (index, regTab->reg, regTab->val); + regTab++; + } +} + +/*****************************************************************************/ +static void +SetArRegs (void) +{ + int i, tmp; + + for (i = 0; i < 0x10; i++) + ctWrite_i (CT_AR_O, i, i); + if (text) + tmp = 0x04; + else + tmp = 0x41; + + ctWrite_i (CT_AR_O, 0x10, tmp); /* Mode Control Register */ + ctWrite_i (CT_AR_O, 0x11, 0x00); /* Overscan Color Register */ + ctWrite_i (CT_AR_O, 0x12, 0x0f); /* Memory Plane Enable Register */ + if (fntwidth == 9) + tmp = 0x08; + else + tmp = 0x00; + ctWrite_i (CT_AR_O, 0x13, tmp); /* Horizontal Pixel Panning */ + ctWrite_i (CT_AR_O, 0x14, 0x00); /* Color Select Register */ + ctWrite (CT_AR_O, 0x20); /* enable video */ +} + +/*****************************************************************************/ +static void +SetGrRegs (void) +{ /* Set Graphics Mode */ + int i; + + for (i = 0; i < 0x05; i++) + ctWrite_i (CT_GR_O, i, 0); + if (text) { + ctWrite_i (CT_GR_O, 0x05, 0x10); + ctWrite_i (CT_GR_O, 0x06, 0x02); + } else { + ctWrite_i (CT_GR_O, 0x05, 0x40); + ctWrite_i (CT_GR_O, 0x06, 0x05); + } + ctWrite_i (CT_GR_O, 0x07, 0x0f); + ctWrite_i (CT_GR_O, 0x08, 0xff); +} + +/*****************************************************************************/ +static void +SetSrRegs (void) +{ + int tmp = 0; + + ctWrite_i (CT_SR_O, 0x00, 0x00); /* reset */ + /*rr( sr, 0x01, tmp ); + if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01; + wr( sr, 0x01, tmp ); */ + if (fntwidth == 8) + ctWrite_i (CT_SR_O, 0x01, 0x01); /* Clocking Mode Register */ + else + ctWrite_i (CT_SR_O, 0x01, 0x00); /* Clocking Mode Register */ + ctWrite_i (CT_SR_O, 0x02, 0x0f); /* Enable CPU wr access to given memory plane */ + ctWrite_i (CT_SR_O, 0x03, 0x00); /* Character Map Select Register */ + if (text) + tmp = 0x02; + else + tmp = 0x0e; + ctWrite_i (CT_SR_O, 0x04, tmp); /* Enable CPU accesses to the rest of the 256KB + total VGA memory beyond the first 64KB and set + fb mapping mode. */ + ctWrite_i (CT_SR_O, 0x00, 0x03); /* enable */ +} + +/*****************************************************************************/ +static void +SetBitsPerPixelIntoXrRegs (int bpp) +{ + unsigned int n = (bpp >> 3), tmp; /* only for 15, 8, 16, 24 bpp */ + static char md[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */ + static char off[4] = { ~0x20, ~0x30, ~0x20, ~0x10 }; /* mask */ + static char on[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */ + if (bpp == 15) + n = 0; + tmp = ctRead_i (CT_XR_O, 0x20); + tmp &= off[n]; + tmp |= on[n]; + ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */ + ctWrite_i (CT_XR_O, 0x81, md[n]); +} + +/*****************************************************************************/ +static void +SetCrRegs (struct ctfb_res_modes *var, int bits_per_pixel) +{ /* he -le- ht|0 hd -ri- hs -h- he */ + unsigned char cr[0x7a]; + int i, tmp; + unsigned int hd, hs, he, ht, hbe; /* Horizontal. */ + unsigned int vd, vs, ve, vt; /* vertical */ + unsigned int bpp, wd, dblscan, interlaced, bcast, CrtHalfLine; + unsigned int CompSyncCharClkDelay, CompSyncPixelClkDelay; + unsigned int NTSC_PAL_HorizontalPulseWidth, BlDelayCtrl; + unsigned int HorizontalEqualizationPulses; + unsigned int HorizontalSerration1Start, HorizontalSerration2Start; + + const int LineCompare = 0x3ff; + unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */ + unsigned int RAMDAC_BlankPedestalEnable = 0; /* 1=en-, 0=disable, see XR82 */ + + hd = (var->xres) / 8; /* HDisp. */ + hs = (var->xres + var->right_margin) / 8; /* HsStrt */ + he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */ + ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */ + hbe = ht - 1; /* HBlankEnable todo docu wants ht here, but it does not work */ + /* ve -up- vt|0 vd -lo- vs -v- ve */ + vd = var->yres; /* VDisplay */ + vs = var->yres + var->lower_margin; /* VSyncStart */ + ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */ + vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */ + bpp = bits_per_pixel; + dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0; + interlaced = var->vmode & FB_VMODE_INTERLACED; + bcast = var->sync & FB_SYNC_BROADCAST; + CrtHalfLine = bcast ? (hd >> 1) : 0; + BlDelayCtrl = bcast ? 1 : 0; + CompSyncCharClkDelay = 0; /* 2 bit */ + CompSyncPixelClkDelay = 0; /* 3 bit */ + if (bcast) { + NTSC_PAL_HorizontalPulseWidth = 7; /*( var->hsync_len >> 1 ) + 1 */ + HorizontalEqualizationPulses = 0; /* inverse value */ + HorizontalSerration1Start = 31; /* ( ht >> 1 ) */ + HorizontalSerration2Start = 89; /* ( ht >> 1 ) */ + } else { + NTSC_PAL_HorizontalPulseWidth = 0; + /* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] ) + * / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */ + HorizontalEqualizationPulses = 1; /* inverse value */ + HorizontalSerration1Start = 0; /* ( ht >> 1 ) */ + HorizontalSerration2Start = 0; /* ( ht >> 1 ) */ + } + + if (bpp == 15) + bpp = 16; + wd = var->xres * bpp / 64; /* double words per line */ + if (interlaced) { /* we divide all vertical timings, exept vd */ + vs >>= 1; + ve >>= 1; + vt >>= 1; + } + memset (cr, 0, sizeof (cr)); + cr[0x00] = 0xff & (ht - 5); + cr[0x01] = hd - 1; /* soll:4f ist 59 */ + cr[0x02] = hd; + cr[0x03] = (hbe & 0x1F) | 0x80; /* hd + ht - hd */ + cr[0x04] = hs; + cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); + cr[0x06] = (vt - 2) & 0xFF; + cr[0x30] = (vt - 2) >> 8; + cr[0x07] = ((vt & 0x100) >> 8) + | ((vd & 0x100) >> 7) + | ((vs & 0x100) >> 6) + | ((vs & 0x100) >> 5) + | ((LineCompare & 0x100) >> 4) + | ((vt & 0x200) >> 4) + | ((vd & 0x200) >> 3) + | ((vs & 0x200) >> 2); + cr[0x08] = 0x00; + cr[0x09] = (dblscan << 7) + | ((LineCompare & 0x200) >> 3) + | ((vs & 0x200) >> 4) + | (TextScanLines - 1); + cr[0x10] = vs & 0xff; /* VSyncPulseStart */ + cr[0x32] = (vs & 0xf00) >> 8; /* VSyncPulseStart */ + cr[0x11] = (ve & 0x0f); /* | 0x20; */ + cr[0x12] = (vd - 1) & 0xff; /* LineCount */ + cr[0x31] = ((vd - 1) & 0xf00) >> 8; /* LineCount */ + cr[0x13] = wd & 0xff; + cr[0x41] = (wd & 0xf00) >> 8; + cr[0x15] = vs & 0xff; + cr[0x33] = (vs & 0xf00) >> 8; + cr[0x38] = (0x100 & (ht - 5)) >> 8; + cr[0x3C] = 0xc0 & hbe; + cr[0x16] = (vt - 1) & 0xff; /* vbe - docu wants vt here, */ + cr[0x17] = 0xe3; /* but it does not work */ + cr[0x18] = 0xff & LineCompare; + cr[0x22] = 0xff; /* todo? */ + cr[0x70] = interlaced ? (0x80 | CrtHalfLine) : 0x00; /* check:0xa6 */ + cr[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable << 6) + | (BlDelayCtrl << 5) + | ((0x03 & CompSyncCharClkDelay) << 3) + | (0x07 & CompSyncPixelClkDelay); /* todo: see XR82 */ + cr[0x72] = HorizontalSerration1Start; + cr[0x73] = HorizontalSerration2Start; + cr[0x74] = (HorizontalEqualizationPulses << 5) + | NTSC_PAL_HorizontalPulseWidth; + /* todo: ct69000 has also 0x75-79 */ + /* now set the registers */ + for (i = 0; i <= 0x0d; i++) { /*CR00 .. CR0D */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + for (i = 0x10; i <= 0x18; i++) { /*CR10 .. CR18 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + i = 0x22; /*CR22 */ + ctWrite_i (CT_CR_O, i, cr[i]); + for (i = 0x30; i <= 0x33; i++) { /*CR30 .. CR33 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + i = 0x38; /*CR38 */ + ctWrite_i (CT_CR_O, i, cr[i]); + i = 0x3C; /*CR3C */ + ctWrite_i (CT_CR_O, i, cr[i]); + for (i = 0x40; i <= 0x41; i++) { /*CR40 .. CR41 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + for (i = 0x70; i <= 0x74; i++) { /*CR70 .. CR74 */ + ctWrite_i (CT_CR_O, i, cr[i]); + } + tmp = ctRead_i (CT_CR_O, 0x40); + tmp &= 0x0f; + tmp |= 0x80; + ctWrite_i (CT_CR_O, 0x40, tmp); /* StartAddressEnable */ +} + +/* pixelclock control */ + +/***************************************************************************** + We have a rational number p/q and need an m/n which is very close to p/q + but has m and n within mnmin and mnmax. We have no floating point in the + kernel. We can use long long without divide. And we have time to compute... +******************************************************************************/ +static unsigned int +FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin, + unsigned int mnmax, unsigned int *pm, unsigned int *pn) +{ + /* this code is not for general purpose usable but good for our number ranges */ + unsigned int n = mnmin, m = 0; + long long int L = 0, P = p, Q = q, H = P >> 1; + long long int D = 0x7ffffffffffffffLL; + for (n = mnmin; n <= mnmax; n++) { + m = mnmin; /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */ + L = P * n - m * Q; /* n * vco - m * fref should be near 0 */ + while (L > 0 && m < mnmax) { + L -= q; /* difference is greater as 0 subtract fref */ + m++; /* and increment m */ + } + /* difference is less or equal than 0 or m > maximum */ + if (m > mnmax) + break; /* no solution: if we increase n we get the same situation */ + /* L is <= 0 now */ + if (-L > H && m > mnmin) { /* if difference > the half fref */ + L += q; /* we take the situation before */ + m--; /* because its closer to 0 */ + } + L = (L < 0) ? -L : +L; /* absolute value */ + if (D < L) /* if last difference was better take next n */ + continue; + D = L; + *pm = m; + *pn = n; /* keep improved data */ + if (D == 0) + break; /* best result we can get */ + } + return (unsigned int) (0xffffffff & D); +} + +/* that is the hardware < 69000 we have to manage + +---------+ +-------------------+ +----------------------+ +--+ + | REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__ + | 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | | + +---------+ +-------------------+ +----------------------+ +--+ | + ___________________________________________________________________| + | + | fvco fout + | +--------+ +------------+ +-----+ +-------------------+ +----+ + +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |---> + +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | | + | +--------+ +------------+ +-----+ | +-------------------+ +----+ + | | + | +--+ +---------------+ | + |____|÷M|___|VCO Loop Divide|__________| + | | |(VLD)(÷4, ÷16) | + +--+ +---------------+ +**************************************************************************** + that is the hardware >= 69000 we have to manage + +---------+ +--+ + | REFCLK |__|÷N|__ + | 14.3MHz | | | | + +---------+ +--+ | + __________________| + | + | fvco fout + | +--------+ +------------+ +-----+ +-------------------+ +----+ + +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |---> + +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | | + | +--------+ +------------+ +-----+ | +-------------------+ +----+ + | | + | +--+ +---------------+ | + |____|÷M|___|VCO Loop Divide|__________| + | | |(VLD)(÷1, ÷4) | + +--+ +---------------+ + + +*/ + +#define VIDEO_FREF 14318180; /* Hz */ +/*****************************************************************************/ +static int +ReadPixClckFromXrRegsBack (struct ctfb_chips_properties *param) +{ + unsigned int m, n, vld, pd, PD, fref, xr_cb, i, pixclock; + i = 0; + pixclock = -1; + fref = VIDEO_FREF; + m = ctRead_i (CT_XR_O, 0xc8); + n = ctRead_i (CT_XR_O, 0xc9); + m -= param->mn_diff; + n -= param->mn_diff; + xr_cb = ctRead_i (CT_XR_O, 0xcb); + PD = (0x70 & xr_cb) >> 4; + pd = 1; + for (i = 0; i < PD; i++) { + pd *= 2; + } + vld = (0x04 & xr_cb) ? param->vld_set : param->vld_not_set; + if (n * vld * m) { + unsigned long long p = 1000000000000LL * pd * n; + unsigned long long q = (long long) fref * vld * m; + while ((p > 0xffffffffLL) || (q > 0xffffffffLL)) { + p >>= 1; /* can't divide with long long so we scale down */ + q >>= 1; + } + pixclock = (unsigned) p / (unsigned) q; + } else + printf ("Invalid data in xr regs.\n"); + return pixclock; +} + +/*****************************************************************************/ +static void +FindAndSetPllParamIntoXrRegs (unsigned int pixelclock, + struct ctfb_chips_properties *param) +{ + unsigned int m, n, vld, pd, PD, fref, xr_cb; + unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk; + unsigned int pfreq, fvco, new_pixclock; + unsigned int D,nback,mback; + + fref = VIDEO_FREF; + pd = 1; + PD = 0; + fvcomin = param->vco_min; + fvcomax = param->vco_max; /* MHz */ + pclckmin = 1000000 / fvcomax + 1; /* 4546 */ + pclckmax = 32000000 / fvcomin - 1; /* 666665 */ + pclk = minmax (pclckmin, pixelclock, pclckmax); /* ps pp */ + pfreq = 250 * (4000000000U / pclk); + fvco = pfreq; /* Hz */ + new_pixclock = 0; + while (fvco < fvcomin * 1000000) { + /* double VCO starting with the pixelclock frequency + * as long as it is lower than the minimal VCO frequency */ + fvco *= 2; + pd *= 2; + PD++; + } + /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */ + /* first try */ + vld = param->vld_set; + D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */ + mback=m; + nback=n; + /* second try */ + vld = param->vld_not_set; + if(Dmn_min, param->mn_max, &m, &n)) { /* rds = 1 */ + /* first try was better */ + m=mback; + n=nback; + vld = param->vld_set; + } + m += param->mn_diff; + n += param->mn_diff; + PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco, pd, m, n, vld); + xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0); + /* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be + * written, and in order from XRC8 to XRCB, before the hardware will + * update the synthesizer s settings. + */ + ctWrite_i (CT_XR_O, 0xc8, m); + ctWrite_i (CT_XR_O, 0xc9, n); /* xrca does not exist in CT69000 and CT69030 */ + ctWrite_i (CT_XR_O, 0xca, 0); /* because of a hw bug I guess, but we write */ + ctWrite_i (CT_XR_O, 0xcb, xr_cb); /* 0 to it for savety */ + new_pixclock = ReadPixClckFromXrRegsBack (param); + PRINTF ("pixelclock.set = %d, pixelclock.real = %d \n", + pixelclock, new_pixclock); +} + +/*****************************************************************************/ +static void +SetMsrRegs (struct ctfb_res_modes *mode) +{ + unsigned char h_synch_high, v_synch_high; + + h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */ + v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */ + ctWrite (CT_MSR_W_O, (h_synch_high | v_synch_high | 0x29)); + /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01 + * Selects the upper 64KB page.Bit5=1 + * CLK2 (left reserved in standard VGA) Bit3|2=1|0 + * Disables CPU access to frame buffer. Bit1=0 + * Sets the I/O address decode for ST01, FCR, and all CR registers + * to the 3Dx I/O address range (CGA emulation). Bit0=1 + */ +} + +/************************************************************************************/ +#ifdef VGA_DUMP_REG + +static void +ctDispRegs (unsigned short index, int from, int to) +{ + unsigned char status; + int i; + + for (i = from; i < to; i++) { + status = ctRead_i (index, i); + printf ("%02X: is %02X\n", i, status); + } +} + +void +video_dump_reg (void) +{ + int i; + + printf ("Extended Regs:\n"); + ctDispRegs (CT_XR_O, 0, 0xC); + ctDispRegs (CT_XR_O, 0xe, 0xf); + ctDispRegs (CT_XR_O, 0x20, 0x21); + ctDispRegs (CT_XR_O, 0x40, 0x50); + ctDispRegs (CT_XR_O, 0x60, 0x64); + ctDispRegs (CT_XR_O, 0x67, 0x68); + ctDispRegs (CT_XR_O, 0x70, 0x72); + ctDispRegs (CT_XR_O, 0x80, 0x83); + ctDispRegs (CT_XR_O, 0xA0, 0xB0); + ctDispRegs (CT_XR_O, 0xC0, 0xD3); + printf ("Sequencer Regs:\n"); + ctDispRegs (CT_SR_O, 0, 0x8); + printf ("Graphic Regs:\n"); + ctDispRegs (CT_GR_O, 0, 0x9); + printf ("CRT Regs:\n"); + ctDispRegs (CT_CR_O, 0, 0x19); + ctDispRegs (CT_CR_O, 0x22, 0x23); + ctDispRegs (CT_CR_O, 0x30, 0x34); + ctDispRegs (CT_CR_O, 0x38, 0x39); + ctDispRegs (CT_CR_O, 0x3C, 0x3D); + ctDispRegs (CT_CR_O, 0x40, 0x42); + ctDispRegs (CT_CR_O, 0x70, 0x80); + /* don't display the attributes */ +} + +#endif + +#ifdef CONFIG_VIDEO_HW_CURSOR +/*************************************************************** + * Set Hardware Cursor in Pixel + */ +void +video_set_hw_cursor (int x, int y) +{ + int sig_x = 0, sig_y = 0; + if (x < 0) { + x *= -1; + sig_x = 1; + } + if (y < 0) { + y *= -1; + sig_y = 1; + } + ctWrite_i (CT_XR_O, 0xa4, x & 0xff); + ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7); + ctWrite_i (CT_XR_O, 0xa6, y & 0xff); + ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7); +} + +/*************************************************************** + * Init Hardware Cursor. To know the size of the Cursor, + * we have to know the Font size. + */ +void +video_init_hw_cursor (int font_width, int font_height) +{ + unsigned char xr_80; + unsigned long *curs, pattern; + int i; + int cursor_start; + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + + cursor_start = pGD->dprBase; + xr_80 = ctRead_i (CT_XR_O, 0x80); + /* set start address */ + ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0); + ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f); + /* set cursor shape */ + curs = (unsigned long *) cursor_start; + i = 0; + while (i < 0x400) { + curs[i++] = 0xffffffff; /* AND mask */ + curs[i++] = 0xffffffff; /* AND mask */ + curs[i++] = 0; /* XOR mask */ + curs[i++] = 0; /* XOR mask */ + /* Transparent */ + } + pattern = 0xffffffff >> font_width; + i = 0; + while (i < (font_height * 2)) { + curs[i++] = pattern; /* AND mask */ + curs[i++] = pattern; /* AND mask */ + curs[i++] = 0; /* XOR mask */ + curs[i++] = 0; /* XOR mask */ + /* Cursor Color 0 */ + } + /* set blink rate */ + ctWrite_i (CT_FP_O, 0x19, 0xf); + + /* set cursors colors */ + xr_80 = ctRead_i (CT_XR_O, 0x80); + xr_80 |= 0x1; /* alternate palette select */ + ctWrite_i (CT_XR_O, 0x80, xr_80); + video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL); + /* position 4 is color 0 cursor 0 */ + xr_80 &= 0xfe; /* normal palette select */ + ctWrite_i (CT_XR_O, 0x80, xr_80); + /* cursor enable */ + ctWrite_i (CT_XR_O, 0xa0, 0x91); + xr_80 |= 0x10; /* enable hwcursor */ + ctWrite_i (CT_XR_O, 0x80, xr_80); + video_set_hw_cursor (0, 0); +} +#endif /* CONFIG_VIDEO_HW_CURSOR */ + +/*************************************************************** + * Wait for BitBlt ready + */ +static int +video_wait_bitblt (unsigned long addr) +{ + unsigned long br04; + int i = 0; + br04 = in32r (addr); + while (br04 & 0x80000000) { + udelay (1); + br04 = in32r (addr); + if (i++ > 1000000) { + printf ("ERROR Timeout %lx\n", br04); + return 1; + } + } + return 0; +} + +/*************************************************************** + * Set up BitBlt Registrs + */ +static void +SetDrawingEngine (int bits_per_pixel) +{ + unsigned long br04, br00; + unsigned char tmp; + + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + + tmp = ctRead_i (CT_XR_O, 0x20); /* BitBLT Configuration */ + tmp |= 0x02; /* reset BitBLT */ + ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */ + udelay (10); + tmp &= 0xfd; /* release reset BitBLT */ + ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */ + video_wait_bitblt (pGD->pciBase + BR04_o); + + /* set pattern Address */ + out32r (pGD->pciBase + BR05_o, PATTERN_ADR & 0x003ffff8); + br04 = 0; + if (bits_per_pixel == 1) { + br04 |= 0x00040000; /* monochome Pattern */ + br04 |= 0x00001000; /* monochome source */ + } + br00 = ((pGD->winSizeX * pGD->gdfBytesPP) << 16) + (pGD->winSizeX * pGD->gdfBytesPP); /* bytes per scanline */ + out32r (pGD->pciBase + BR00_o, br00); /* */ + out32r (pGD->pciBase + BR08_o, (10 << 16) + 10); /* dummy */ + out32r (pGD->pciBase + BR04_o, br04); /* write all 0 */ + out32r (pGD->pciBase + BR07_o, 0); /* destination */ + video_wait_bitblt (pGD->pciBase + BR04_o); +} + +/**************************************************************************** +* supported Video Chips +*/ +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000}, +#ifdef CONFIG_USE_CPCIDVI + {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030}, +#endif + {} +}; + +/******************************************************************************* +* +* Init video chip +*/ +void * +video_hw_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + unsigned short device_id; + pci_dev_t devbusfn; + int videomode; + unsigned long t1, hsynch, vsynch; + unsigned int pci_mem_base, *vm; + int tmp, i, bits_per_pixel; + char *penv; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + struct ctfb_chips_properties *chips_param; + /* Search for video chip */ + + if ((devbusfn = pci_find_devices (supported, 0)) < 0) { +#ifdef CONFIG_VIDEO_ONBOARD + printf ("Video: Controller not found !\n"); +#endif + return (NULL); + } + + /* PCI setup */ + pci_write_config_dword (devbusfn, PCI_COMMAND, + (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base); + pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base); + + /* get chips params */ + for (chips_param = (struct ctfb_chips_properties *) &chips[0]; + chips_param->device_id != 0; chips_param++) { + if (chips_param->device_id == device_id) + break; + } + if (chips_param->device_id == 0) { +#ifdef CONFIG_VIDEO_ONBOARD + printf ("Video: controller 0x%X not supported\n", device_id); +#endif + return NULL; + } + /* supported Video controller found */ + printf ("Video: "); + + tmp = 0; + videomode = 0x301; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("no VESA Mode found, switching to mode 0x301 "); + i = 0; + } + res_mode = + (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i]. + resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + } else { + + res_mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params (res_mode, penv); + } + + /* calculate available color depth for controller memory */ + if (bits_per_pixel == 15) + tmp = 2; + else + tmp = bits_per_pixel >> 3; /* /8 */ + if (((chips_param->max_mem - + ACCELMEMORY) / (res_mode->xres * res_mode->yres)) < tmp) { + tmp = + ((chips_param->max_mem - + ACCELMEMORY) / (res_mode->xres * res_mode->yres)); + if (tmp == 0) { + printf + ("No matching videomode found .-> reduce resolution\n"); + return NULL; + } else { + printf ("Switching back to %d Bits per Pixel ", + tmp << 3); + bits_per_pixel = tmp << 3; + } + } + + /* calculate hsynch and vsynch freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= + (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bits_per_pixel, (hsynch / 1000), + (vsynch / 1000)); + printf ("%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->plnSizeX = res_mode->xres; + pGD->plnSizeY = res_mode->yres; + switch (bits_per_pixel) { + case 8: + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + break; + case 15: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_15BIT_555RGB; + break; + case 16: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_16BIT_565RGB; + break; + case 24: + pGD->gdfBytesPP = 3; + pGD->gdfIndex = GDF_24BIT_888RGB; + break; + } + pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS; + pGD->pciBase = pci_mem_base; + pGD->frameAdrs = pci_mem_base; + pGD->memSize = chips_param->max_mem; + /* Cursor Start Address */ + pGD->dprBase = + (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + pci_mem_base; + if ((pGD->dprBase & 0x0fff) != 0) { + /* allign it */ + pGD->dprBase &= 0xfffff000; + pGD->dprBase += 0x00001000; + } + PRINTF ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, + PATTERN_ADR); + pGD->vprBase = pci_mem_base; /* Dummy */ + pGD->cprBase = pci_mem_base; /* Dummy */ + /* set up Hardware */ + +#ifdef CONFIG_USE_CPCIDVI + if (device_id == PCI_DEVICE_ID_CT_69030) { + ctWrite (CT_MSR_W_O, 0x0b); + ctWrite (0x3cd, 0x13); + ctWrite_i (CT_FP_O, 0x02, 0x00); + ctWrite_i (CT_FP_O, 0x05, 0x00); + ctWrite_i (CT_FP_O, 0x06, 0x00); + ctWrite (0x3c2, 0x0b); + ctWrite_i (CT_FP_O, 0x02, 0x10); + ctWrite_i (CT_FP_O, 0x01, 0x09); + } else { + ctWrite (CT_MSR_W_O, 0x01); + } +#else + ctWrite (CT_MSR_W_O, 0x01); +#endif + + /* set the extended Registers */ + ctLoadRegs (CT_XR_O, xreg); + /* set atribute registers */ + SetArRegs (); + /* set Graphics register */ + SetGrRegs (); + /* set sequencer */ + SetSrRegs (); + + /* set msr */ + SetMsrRegs (res_mode); + + /* set CRT Registers */ + SetCrRegs (res_mode, bits_per_pixel); + /* set color mode */ + SetBitsPerPixelIntoXrRegs (bits_per_pixel); + + /* set PLL */ + FindAndSetPllParamIntoXrRegs (res_mode->pixclock, chips_param); + + ctWrite_i (CT_SR_O, 0, 0x03); /* clear synchronous reset */ + /* Clear video memory */ + i = pGD->memSize / 4; + vm = (unsigned int *) pGD->pciBase; + while (i--) + *vm++ = 0; + SetDrawingEngine (bits_per_pixel); +#ifdef VGA_DUMP_REG + video_dump_reg (); +#endif + + return ((void *) &ctfb); +} + + /******************************************************************************* +* +* Set a RGB color in the LUT (8 bit index) +*/ +void +video_set_lut (unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + + ctWrite (CT_LUT_MASK_O, 0xff); + + ctWrite (CT_LUT_START_O, (char) index); + + ctWrite (CT_LUT_RGB_O, r); /* red */ + ctWrite (CT_LUT_RGB_O, g); /* green */ + ctWrite (CT_LUT_RGB_O, b); /* blue */ + udelay (1); + ctWrite (CT_LUT_MASK_O, 0xff); +} + +/******************************************************************************* +* +* Drawing engine fill on screen region +*/ +void +video_hw_rectfill (unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + unsigned long *p, br04; + + video_wait_bitblt (pGD->pciBase + BR04_o); + + p = (unsigned long *) PATTERN_ADR; + dim_x *= bpp; + if (bpp == 3) + bpp++; /* 24Bit needs a 32bit pattern */ + memset (p, color, (bpp * sizeof (unsigned char) * 8 * 8)); /* 8 x 8 pattern data */ + out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */ + br04 = in32r (pGD->pciBase + BR04_o) & 0xffffff00; + br04 |= 0xF0; /* write Pattern P -> D */ + out32r (pGD->pciBase + BR04_o, br04); /* */ + out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* starts the BITBlt */ + video_wait_bitblt (pGD->pciBase + BR04_o); +} + +/******************************************************************************* +* +* Drawing engine bitblt with screen region +*/ +void +video_hw_bitblt (unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + unsigned long br04; + + br04 = in32r (pGD->pciBase + BR04_o); + + /* to prevent data corruption due to overlap, we have to + * find out if, and how the frames overlaps */ + if (src_x < dst_x) { + /* src is more left than dest + * the frame may overlap -> start from right to left */ + br04 |= 0x00000100; /* set bit 8 */ + src_x += dim_x; + dst_x += dim_x; + } else { + br04 &= 0xfffffeff; /* clear bit 8 left to right */ + } + if (src_y < dst_y) { + /* src is higher than dst + * the frame may overlap => start from bottom */ + br04 |= 0x00000200; /* set bit 9 */ + src_y += dim_y; + dst_y += dim_y; + } else { + br04 &= 0xfffffdff; /* clear bit 9 top to bottom */ + } + dim_x *= bpp; + out32r (pGD->pciBase + BR06_o, ((pGD->winSizeX * src_y) + src_x) * pGD->gdfBytesPP); /* source */ + out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */ + br04 &= 0xffffff00; + br04 |= 0x000000CC; /* S -> D */ + out32r (pGD->pciBase + BR04_o, br04); /* */ + out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* start the BITBlt */ + video_wait_bitblt (pGD->pciBase + BR04_o); +} + +#endif /* CONFIG_CT69000 */ + +#endif /* CONFIG_VIDEO */ diff --git a/drivers/dataflash.c b/drivers/dataflash.c new file mode 100644 index 000000000..17eb8597f --- /dev/null +++ b/drivers/dataflash.c @@ -0,0 +1,362 @@ +/* LowLevel function for ATMEL DataFlash support + * Author : Hamid Ikdoumi (Atmel) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#ifdef CONFIG_HAS_DATAFLASH +#include +#include + +AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; +static AT91S_DataFlash DataFlashInst; + +int cs[][CFG_MAX_DATAFLASH_BANKS] = { + {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} +}; + +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0, 0x7fff, FLAG_PROTECT_SET}, /* ROM code */ + {0x8000, 0x1ffff, FLAG_PROTECT_SET}, /* u-boot code */ + {0x20000, 0x27fff, FLAG_PROTECT_CLEAR}, /* u-boot environment */ + {0x28000, 0x1fffff, FLAG_PROTECT_CLEAR}, /* data area size to tune */ +}; + +extern void AT91F_SpiInit (void); +extern int AT91F_DataflashProbe (int i, AT91PS_DataflashDesc pDesc); +extern int AT91F_DataFlashRead (AT91PS_DataFlash pDataFlash, + unsigned long addr, + unsigned long size, char *buffer); +extern int AT91F_DataFlashWrite( AT91PS_DataFlash pDataFlash, + unsigned char *src, + int dest, + int size ); + +int AT91F_DataflashInit (void) +{ + int i, j; + int dfcode; + + AT91F_SpiInit (); + + for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + dataflash_info[i].Desc.state = IDLE; + dataflash_info[i].id = 0; + dataflash_info[i].Device.pages_number = 0; + dfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc); + + switch (dfcode) { + case AT45DB161: + dataflash_info[i].Device.pages_number = 4096; + dataflash_info[i].Device.pages_size = 528; + dataflash_info[i].Device.page_offset = 10; + dataflash_info[i].Device.byte_mask = 0x300; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + break; + + case AT45DB321: + dataflash_info[i].Device.pages_number = 8192; + dataflash_info[i].Device.pages_size = 528; + dataflash_info[i].Device.page_offset = 10; + dataflash_info[i].Device.byte_mask = 0x300; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + break; + + case AT45DB642: + dataflash_info[i].Device.pages_number = 8192; + dataflash_info[i].Device.pages_size = 1056; + dataflash_info[i].Device.page_offset = 11; + dataflash_info[i].Device.byte_mask = 0x700; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + break; + case AT45DB128: + dataflash_info[i].Device.pages_number = 16384; + dataflash_info[i].Device.pages_size = 1056; + dataflash_info[i].Device.page_offset = 11; + dataflash_info[i].Device.byte_mask = 0x700; + dataflash_info[i].Device.cs = cs[i][1]; + dataflash_info[i].Desc.DataFlash_state = IDLE; + dataflash_info[i].logical_address = cs[i][0]; + dataflash_info[i].id = dfcode; + break; + + default: + break; + } + /* set the last area end to the dataflash size*/ + area_list[NB_DATAFLASH_AREA -1].end = + (dataflash_info[i].Device.pages_number * + dataflash_info[i].Device.pages_size)-1; + + /* set the area addresses */ + for(j = 0; jpDataFlashDesc = &(dataflash_info[i].Desc); + pFlash->pDevice = &(dataflash_info[i].Device); + *addr -= dataflash_info[i].logical_address; + return (pFlash); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : addr_dataflash */ +/* Object : Test if address is valid */ +/*------------------------------------------------------------------------------*/ +int addr_dataflash (unsigned long addr) +{ + int addr_valid = 0; + int i; + + for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + if ((((int) addr) & 0xFF000000) == + dataflash_info[i].logical_address) { + addr_valid = 1; + break; + } + } + + return addr_valid; +} +/*-----------------------------------------------------------------------------*/ +/* Function Name : size_dataflash */ +/* Object : Test if address is valid regarding the size */ +/*-----------------------------------------------------------------------------*/ +int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size) +{ + /* is outside the dataflash */ + if (((int)addr & 0x0FFFFFFF) > (pdataFlash->pDevice->pages_size * + pdataFlash->pDevice->pages_number)) return 0; + /* is too large for the dataflash */ + if (size > ((pdataFlash->pDevice->pages_size * + pdataFlash->pDevice->pages_number) - ((int)addr & 0x0FFFFFFF))) return 0; + + return 1; +} +/*-----------------------------------------------------------------------------*/ +/* Function Name : prot_dataflash */ +/* Object : Test if destination area is protected */ +/*-----------------------------------------------------------------------------*/ +int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr) +{ +int area; + /* find area */ + for (area=0; area < NB_DATAFLASH_AREA; area++) { + if ((addr >= pdataFlash->pDevice->area_list[area].start) && + (addr < pdataFlash->pDevice->area_list[area].end)) + break; + } + if (area == NB_DATAFLASH_AREA) return -1; + /*test protection value*/ + if (pdataFlash->pDevice->area_list[area].protected == FLAG_PROTECT_SET) return 0; + + return 1; +} +/*-----------------------------------------------------------------------------*/ +/* Function Name : dataflash_real_protect */ +/* Object : protect/unprotect area */ +/*-----------------------------------------------------------------------------*/ +int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr) +{ +int i,j, area1, area2, addr_valid = 0; + /* find dataflash */ + for (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) { + if ((((int) start_addr) & 0xF0000000) == + dataflash_info[i].logical_address) { + addr_valid = 1; + break; + } + } + if (!addr_valid) { + return -1; + } + /* find start area */ + for (area1=0; area1 < NB_DATAFLASH_AREA; area1++) { + if (start_addr == dataflash_info[i].Device.area_list[area1].start) break; + } + if (area1 == NB_DATAFLASH_AREA) return -1; + /* find end area */ + for (area2=0; area2 < NB_DATAFLASH_AREA; area2++) { + if (end_addr == dataflash_info[i].Device.area_list[area2].end) break; + } + if (area2 == NB_DATAFLASH_AREA) return -1; + + /*set protection value*/ + for(j = area1; j < area2+1 ; j++) + if (flag == 0) dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_CLEAR; + else dataflash_info[i].Device.area_list[j].protected = FLAG_PROTECT_SET; + + return (area2-area1+1); +} + +/*------------------------------------------------------------------------------*/ +/* Function Name : read_dataflash */ +/* Object : dataflash memory read */ +/*------------------------------------------------------------------------------*/ +int read_dataflash (unsigned long addr, unsigned long size, char *result) +{ + unsigned long AddrToRead = addr; + AT91PS_DataFlash pFlash = &DataFlashInst; + + pFlash = AT91F_DataflashSelect (pFlash, &AddrToRead); + + if (pFlash == 0) + return ERR_UNKNOWN_FLASH_TYPE; + + if (size_dataflash(pFlash,addr,size) == 0) + return ERR_INVAL; + + return (AT91F_DataFlashRead (pFlash, AddrToRead, size, result)); +} + + +/*-----------------------------------------------------------------------------*/ +/* Function Name : write_dataflash */ +/* Object : write a block in dataflash */ +/*-----------------------------------------------------------------------------*/ +int write_dataflash (unsigned long addr_dest, unsigned long addr_src, + unsigned long size) +{ + unsigned long AddrToWrite = addr_dest; + AT91PS_DataFlash pFlash = &DataFlashInst; + + pFlash = AT91F_DataflashSelect (pFlash, &AddrToWrite); + + if (pFlash == 0) + return ERR_UNKNOWN_FLASH_TYPE; + + if (size_dataflash(pFlash,addr_dest,size) == 0) + return ERR_INVAL; + + if (prot_dataflash(pFlash,addr_dest) == 0) + return ERR_PROTECTED; + + if (AddrToWrite == -1) + return -1; + + return AT91F_DataFlashWrite (pFlash, (uchar *)addr_src, AddrToWrite, size); +} + + +void dataflash_perror (int err) +{ + switch (err) { + case ERR_OK: + break; + case ERR_TIMOUT: + printf ("Timeout writing to DataFlash\n"); + break; + case ERR_PROTECTED: + printf ("Can't write to protected DataFlash sectors\n"); + break; + case ERR_INVAL: + printf ("Outside available DataFlash\n"); + break; + case ERR_UNKNOWN_FLASH_TYPE: + printf ("Unknown Type of DataFlash\n"); + break; + case ERR_PROG_ERROR: + printf ("General DataFlash Programming Error\n"); + break; + default: + printf ("%s[%d] FIXME: rc=%d\n", __FILE__, __LINE__, err); + break; + } +} + +#endif diff --git a/drivers/dc2114x.c b/drivers/dc2114x.c new file mode 100644 index 000000000..c43cd5ec2 --- /dev/null +++ b/drivers/dc2114x.c @@ -0,0 +1,771 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ + && defined(CONFIG_TULIP) + +#include +#include +#include + +#undef DEBUG_SROM +#undef DEBUG_SROM2 + +#undef UPDATE_SROM + +/* PCI Registers. + */ +#define PCI_CFDA_PSM 0x43 + +#define CFRV_RN 0x000000f0 /* Revision Number */ + +#define WAKEUP 0x00 /* Power Saving Wakeup */ +#define SLEEP 0x80 /* Power Saving Sleep Mode */ + +#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */ + +/* Ethernet chip registers. + */ +#define DE4X5_BMR 0x000 /* Bus Mode Register */ +#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */ +#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */ +#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */ +#define DE4X5_STS 0x028 /* Status Register */ +#define DE4X5_OMR 0x030 /* Operation Mode Register */ +#define DE4X5_SICR 0x068 /* SIA Connectivity Register */ +#define DE4X5_APROM 0x048 /* Ethernet Address PROM */ + +/* Register bits. + */ +#define BMR_SWR 0x00000001 /* Software Reset */ +#define STS_TS 0x00700000 /* Transmit Process State */ +#define STS_RS 0x000e0000 /* Receive Process State */ +#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */ +#define OMR_SR 0x00000002 /* Start/Stop Receive */ +#define OMR_PS 0x00040000 /* Port Select */ +#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */ +#define OMR_PM 0x00000080 /* Pass All Multicast */ + +/* Descriptor bits. + */ +#define R_OWN 0x80000000 /* Own Bit */ +#define RD_RER 0x02000000 /* Receive End Of Ring */ +#define RD_LS 0x00000100 /* Last Descriptor */ +#define RD_ES 0x00008000 /* Error Summary */ +#define TD_TER 0x02000000 /* Transmit End Of Ring */ +#define T_OWN 0x80000000 /* Own Bit */ +#define TD_LS 0x40000000 /* Last Segment */ +#define TD_FS 0x20000000 /* First Segment */ +#define TD_ES 0x00008000 /* Error Summary */ +#define TD_SET 0x08000000 /* Setup Packet */ + +/* The EEPROM commands include the alway-set leading bit. */ +#define SROM_WRITE_CMD 5 +#define SROM_READ_CMD 6 +#define SROM_ERASE_CMD 7 + +#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */ +#define SROM_RD 0x00004000 /* Read from Boot ROM */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x4801 +#define EE_WRITE_1 0x4805 +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define SROM_SR 0x00000800 /* Select Serial ROM when set */ + +#define DT_IN 0x00000004 /* Serial Data In */ +#define DT_CLK 0x00000002 /* Serial ROM Clock */ +#define DT_CS 0x00000001 /* Serial ROM Chip Select */ + +#define POLL_DEMAND 1 + +#ifdef CONFIG_TULIP_FIX_DAVICOM +#define RESET_DM9102(dev) {\ + unsigned long i;\ + i=INL(dev, 0x0);\ + udelay(1000);\ + OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ + udelay(1000);\ +} +#else +#define RESET_DE4X5(dev) {\ + int i;\ + i=INL(dev, DE4X5_BMR);\ + udelay(1000);\ + OUTL(dev, i | BMR_SWR, DE4X5_BMR);\ + udelay(1000);\ + OUTL(dev, i, DE4X5_BMR);\ + udelay(1000);\ + for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\ + udelay(1000);\ +} +#endif + +#define START_DE4X5(dev) {\ + s32 omr; \ + omr = INL(dev, DE4X5_OMR);\ + omr |= OMR_ST | OMR_SR;\ + OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\ +} + +#define STOP_DE4X5(dev) {\ + s32 omr; \ + omr = INL(dev, DE4X5_OMR);\ + omr &= ~(OMR_ST|OMR_SR);\ + OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ +} + +#define NUM_RX_DESC PKTBUFSRX +#ifndef CONFIG_TULIP_FIX_DAVICOM + #define NUM_TX_DESC 1 /* Number of TX descriptors */ +#else + #define NUM_TX_DESC 4 +#endif +#define RX_BUFF_SZ PKTSIZE_ALIGN + +#define TOUT_LOOP 1000000 + +#define SETUP_FRAME_LEN 192 +#define ETH_ALEN 6 + +struct de4x5_desc { + volatile s32 status; + u32 des1; + u32 buf; + u32 next; +}; + +static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */ +static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */ +static int rx_new; /* RX descriptor ring pointer */ +static int tx_new; /* TX descriptor ring pointer */ + +static char rxRingSize; +static char txRingSize; + +#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) +static void sendto_srom(struct eth_device* dev, u_int command, u_long addr); +static int getfrom_srom(struct eth_device* dev, u_long addr); +static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len); +static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len); +#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ +#ifdef UPDATE_SROM +static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value); +static void update_srom(struct eth_device *dev, bd_t *bis); +#endif +#ifndef CONFIG_TULIP_FIX_DAVICOM +static int read_srom(struct eth_device *dev, u_long ioaddr, int index); +static void read_hw_addr(struct eth_device* dev, bd_t * bis); +#endif /* CONFIG_TULIP_FIX_DAVICOM */ +static void send_setup_frame(struct eth_device* dev, bd_t * bis); + +static int dc21x4x_init(struct eth_device* dev, bd_t* bis); +static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length); +static int dc21x4x_recv(struct eth_device* dev); +static void dc21x4x_halt(struct eth_device* dev); +#ifdef CONFIG_TULIP_SELECT_MEDIA +extern void dc21x4x_select_media(struct eth_device* dev); +#endif + +#if defined(CONFIG_E500) +#define phys_to_bus(a) (a) +#else +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) +#endif + +static int INL(struct eth_device* dev, u_long addr) +{ + return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase)); +} + +static void OUTL(struct eth_device* dev, int command, u_long addr) +{ + *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command); +} + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST }, + { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 }, +#ifdef CONFIG_TULIP_FIX_DAVICOM + { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A }, +#endif + { } +}; + +int dc21x4x_initialize(bd_t *bis) +{ + int idx=0; + int card_number = 0; + unsigned int cfrv; + unsigned char timer; + pci_dev_t devbusfn; + unsigned int iobase; + unsigned short status; + struct eth_device* dev; + + while(1) { + devbusfn = pci_find_devices(supported, idx++); + if (devbusfn == -1) { + break; + } + + /* Get the chip configuration revision register. */ + pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv); + +#ifndef CONFIG_TULIP_FIX_DAVICOM + if ((cfrv & CFRV_RN) < DC2114x_BRK ) { + printf("Error: The chip is not DC21143.\n"); + continue; + } +#endif + + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + status |= +#ifdef CONFIG_TULIP_USE_IO + PCI_COMMAND_IO | +#else + PCI_COMMAND_MEMORY | +#endif + PCI_COMMAND_MASTER; + pci_write_config_word(devbusfn, PCI_COMMAND, status); + + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_IO)) { + printf("Error: Can not enable I/O access.\n"); + continue; + } + + if (!(status & PCI_COMMAND_IO)) { + printf("Error: Can not enable I/O access.\n"); + continue; + } + + if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + /* Check the latency timer for values >= 0x60. */ + pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); + + if (timer < 0x60) { + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60); + } + +#ifdef CONFIG_TULIP_USE_IO + /* read BAR for memory space access */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); + iobase &= PCI_BASE_ADDRESS_IO_MASK; +#else + /* read BAR for memory space access */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; +#endif + debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); + + dev = (struct eth_device*) malloc(sizeof *dev); + +#ifdef CONFIG_TULIP_FIX_DAVICOM + sprintf(dev->name, "Davicom#%d", card_number); +#else + sprintf(dev->name, "dc21x4x#%d", card_number); +#endif + +#ifdef CONFIG_TULIP_USE_IO + dev->iobase = pci_io_to_phys(devbusfn, iobase); +#else + dev->iobase = pci_mem_to_phys(devbusfn, iobase); +#endif + dev->priv = (void*) devbusfn; + dev->init = dc21x4x_init; + dev->halt = dc21x4x_halt; + dev->send = dc21x4x_send; + dev->recv = dc21x4x_recv; + + /* Ensure we're not sleeping. */ + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); + + udelay(10 * 1000); + +#ifndef CONFIG_TULIP_FIX_DAVICOM + read_hw_addr(dev, bis); +#endif + eth_register(dev); + + card_number++; + } + + return card_number; +} + +static int dc21x4x_init(struct eth_device* dev, bd_t* bis) +{ + int i; + int devbusfn = (int) dev->priv; + + /* Ensure we're not sleeping. */ + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); + +#ifdef CONFIG_TULIP_FIX_DAVICOM + RESET_DM9102(dev); +#else + RESET_DE4X5(dev); +#endif + + if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) { + printf("Error: Cannot reset ethernet controller.\n"); + return 0; + } + +#ifdef CONFIG_TULIP_SELECT_MEDIA + dc21x4x_select_media(dev); +#else + OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR); +#endif + + for (i = 0; i < NUM_RX_DESC; i++) { + rx_ring[i].status = cpu_to_le32(R_OWN); + rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); + rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i])); +#ifdef CONFIG_TULIP_FIX_DAVICOM + rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC])); +#else + rx_ring[i].next = 0; +#endif + } + + for (i=0; i < NUM_TX_DESC; i++) { + tx_ring[i].status = 0; + tx_ring[i].des1 = 0; + tx_ring[i].buf = 0; + +#ifdef CONFIG_TULIP_FIX_DAVICOM + tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC])); +#else + tx_ring[i].next = 0; +#endif + } + + rxRingSize = NUM_RX_DESC; + txRingSize = NUM_TX_DESC; + + /* Write the end of list marker to the descriptor lists. */ + rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); + tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER); + + /* Tell the adapter where the TX/RX rings are located. */ + OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA); + OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA); + + START_DE4X5(dev); + + tx_new = 0; + rx_new = 0; + + send_setup_frame(dev, bis); + + return 1; +} + +static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length) +{ + int status = -1; + int i; + + if (length <= 0) { + printf("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx error buffer not ready\n", dev->name); + goto Done; + } + } + + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet)); + tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length); + tx_ring[tx_new].status = cpu_to_le32(T_OWN); + + OUTL(dev, POLL_DEMAND, DE4X5_TPD); + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf(".%s: tx buffer not ready\n", dev->name); + goto Done; + } + } + + if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) { +#if 0 /* test-only */ + printf("TX error status = 0x%08X\n", + le32_to_cpu(tx_ring[tx_new].status)); +#endif + tx_ring[tx_new].status = 0x0; + goto Done; + } + + status = length; + + Done: + tx_new = (tx_new+1) % NUM_TX_DESC; + return status; +} + +static int dc21x4x_recv(struct eth_device* dev) +{ + s32 status; + int length = 0; + + for ( ; ; ) { + status = (s32)le32_to_cpu(rx_ring[rx_new].status); + + if (status & R_OWN) { + break; + } + + if (status & RD_LS) { + /* Valid frame status. + */ + if (status & RD_ES) { + + /* There was an error. + */ + printf("RX error status = 0x%08X\n", status); + } else { + /* A valid frame received. + */ + length = (le32_to_cpu(rx_ring[rx_new].status) >> 16); + + /* Pass the packet up to the protocol + * layers. + */ + NetReceive(NetRxPackets[rx_new], length - 4); + } + + /* Change buffer ownership for this frame, back + * to the adapter. + */ + rx_ring[rx_new].status = cpu_to_le32(R_OWN); + } + + /* Update entry information. + */ + rx_new = (rx_new + 1) % rxRingSize; + } + + return length; +} + +static void dc21x4x_halt(struct eth_device* dev) +{ + int devbusfn = (int) dev->priv; + + STOP_DE4X5(dev); + OUTL(dev, 0, DE4X5_SICR); + + pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP); +} + +static void send_setup_frame(struct eth_device* dev, bd_t *bis) +{ + int i; + char setup_frame[SETUP_FRAME_LEN]; + char *pa = &setup_frame[0]; + + memset(pa, 0xff, SETUP_FRAME_LEN); + + for (i = 0; i < ETH_ALEN; i++) { + *(pa + (i & 1)) = dev->enetaddr[i]; + if (i & 0x01) { + pa += 4; + } + } + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx error buffer not ready\n", dev->name); + goto Done; + } + } + + tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0])); + tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN); + tx_ring[tx_new].status = cpu_to_le32(T_OWN); + + OUTL(dev, POLL_DEMAND, DE4X5_TPD); + + for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx buffer not ready\n", dev->name); + goto Done; + } + } + + if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) { + printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status)); + } + tx_new = (tx_new+1) % NUM_TX_DESC; + +Done: + return; +} + +#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) +/* SROM Read and write routines. + */ +static void +sendto_srom(struct eth_device* dev, u_int command, u_long addr) +{ + OUTL(dev, command, addr); + udelay(1); +} + +static int +getfrom_srom(struct eth_device* dev, u_long addr) +{ + s32 tmp; + + tmp = INL(dev, addr); + udelay(1); + + return tmp; +} + +/* Note: this routine returns extra data bits for size detection. */ +static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len) +{ + int i; + unsigned retval = 0; + int read_cmd = location | (SROM_READ_CMD << addr_len); + + sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + +#ifdef DEBUG_SROM + printf(" EEPROM read at %d ", location); +#endif + + /* Shift the read command bits out. */ + for (i = 4 + addr_len; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr); + udelay(10); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); + udelay(10); +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev, ioaddr) & 15); +#endif + retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); + } + + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + +#ifdef DEBUG_SROM2 + printf(" :%X:", getfrom_srom(dev, ioaddr) & 15); +#endif + + for (i = 16; i > 0; i--) { + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); + udelay(10); +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev, ioaddr) & 15); +#endif + retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0); + sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); + udelay(10); + } + + /* Terminate the EEPROM access. */ + sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); + +#ifdef DEBUG_SROM2 + printf(" EEPROM value at %d is %5.5x.\n", location, retval); +#endif + + return retval; +} +#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ + +/* This executes a generic EEPROM command, typically a write or write + * enable. It returns the data output from the EEPROM, and thus may + * also be used for reads. + */ +#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM) +static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len) +{ + unsigned retval = 0; + +#ifdef DEBUG_SROM + printf(" EEPROM op 0x%x: ", cmd); +#endif + + sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr); + + /* Shift the command bits out. */ + do { + short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; + sendto_srom(dev,dataval, ioaddr); + udelay(10); + +#ifdef DEBUG_SROM2 + printf("%X", getfrom_srom(dev,ioaddr) & 15); +#endif + + sendto_srom(dev,dataval | DT_CLK, ioaddr); + udelay(10); + retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0); + } while (--cmd_len >= 0); + sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr); + + /* Terminate the EEPROM access. */ + sendto_srom(dev,SROM_RD | SROM_SR, ioaddr); + +#ifdef DEBUG_SROM + printf(" EEPROM result is 0x%5.5x.\n", retval); +#endif + + return retval; +} +#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */ + +#ifndef CONFIG_TULIP_FIX_DAVICOM +static int read_srom(struct eth_device *dev, u_long ioaddr, int index) +{ + int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; + + return do_eeprom_cmd(dev, ioaddr, + (((SROM_READ_CMD << ee_addr_size) | index) << 16) + | 0xffff, 3 + ee_addr_size + 16); +} +#endif /* CONFIG_TULIP_FIX_DAVICOM */ + +#ifdef UPDATE_SROM +static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value) +{ + int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6; + int i; + unsigned short newval; + + udelay(10*1000); /* test-only */ + +#ifdef DEBUG_SROM + printf("ee_addr_size=%d.\n", ee_addr_size); + printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index); +#endif + + /* Enable programming modes. */ + do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size); + + /* Do the actual write. */ + do_eeprom_cmd(dev, ioaddr, + (((SROM_WRITE_CMD<enetaddr[0]); + int i, j = 0; + + for (i = 0; i < (ETH_ALEN >> 1); i++) { + tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i)); + *p = le16_to_cpu(tmp); + j += *p++; + } + + if ((j == 0) || (j == 0x2fffd)) { + memset (dev->enetaddr, 0, ETH_ALEN); + debug ("Warning: can't read HW address from SROM.\n"); + goto Done; + } + + return; + +Done: +#ifdef UPDATE_SROM + update_srom(dev, bis); +#endif + return; +} +#endif /* CONFIG_TULIP_FIX_DAVICOM */ + +#ifdef UPDATE_SROM +static void update_srom(struct eth_device *dev, bd_t *bis) +{ + int i; + static unsigned short eeprom[0x40] = { + 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ + 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */ + 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */ + 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */ + 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */ + 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ + }; + + /* Ethernet Addr... */ + eeprom[0x0a] = ((bis->bi_enetaddr[1] & 0xff) << 8) | (bis->bi_enetaddr[0] & 0xff); + eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff); + eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff); + + for (i=0; i<0x40; i++) + { + write_srom(dev, DE4X5_APROM, i, eeprom[i]); + } +} +#endif /* UPDATE_SROM */ + +#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_TULIP */ diff --git a/drivers/dm9000x.c b/drivers/dm9000x.c new file mode 100644 index 000000000..0e475d472 --- /dev/null +++ b/drivers/dm9000x.c @@ -0,0 +1,590 @@ +/* + dm9000.c: Version 1.2 12/15/2003 + + A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. + Copyright (C) 1997 Sten Wang + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2 + of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. + +V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match + 06/22/2001 Support DM9801 progrmming + E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 + E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 + R17 = (R17 & 0xfff0) | NF + 3 + E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 + R17 = (R17 & 0xfff0) | NF + +v1.00 modify by simon 2001.9.5 + change for kernel 2.4.x + +v1.1 11/09/2001 fix force mode bug + +v1.2 03/18/2003 Weilun Huang : + Fixed phy reset. + Added tx/rx 32 bit mode. + Cleaned up for kernel merge. + +-------------------------------------- + + 12/15/2003 Initial port to u-boot by Sascha Hauer + +TODO: Homerun NIC and longrun NIC are not functional, only internal at the + moment. +*/ + +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_DM9000 + +#include "dm9000x.h" + +/* Board/System/Debug information/definition ---------------- */ + +#define DM9801_NOISE_FLOOR 0x08 +#define DM9802_NOISE_FLOOR 0x05 + +/* #define CONFIG_DM9000_DEBUG */ + +#ifdef CONFIG_DM9000_DEBUG +#define DM9000_DBG(fmt,args...) printf(fmt ,##args) +#else /* */ +#define DM9000_DBG(fmt,args...) +#endif /* */ +enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD = + 1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO = + 8, DM9000_1M_HPNA = 0x10 +}; +enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2 +}; + +/* Structure/enum declaration ------------------------------- */ +typedef struct board_info { + u32 runt_length_counter; /* counter: RX length < 64byte */ + u32 long_length_counter; /* counter: RX length > 1514byte */ + u32 reset_counter; /* counter: RESET */ + u32 reset_tx_timeout; /* RESET caused by TX Timeout */ + u32 reset_rx_status; /* RESET caused by RX Statsus wrong */ + u16 tx_pkt_cnt; + u16 queue_start_addr; + u16 dbug_cnt; + u8 phy_addr; + u8 device_wait_reset; /* device state */ + u8 nic_type; /* NIC type */ + unsigned char srom[128]; +} board_info_t; +board_info_t dmfe_info; + +/* For module input parameter */ +static int media_mode = DM9000_AUTO; +static u8 nfloor = 0; + +/* function declaration ------------------------------------- */ +int eth_init(bd_t * bd); +int eth_send(volatile void *, int); +int eth_rx(void); +void eth_halt(void); +static int dm9000_probe(void); +static u16 phy_read(int); +static void phy_write(int, u16); +static u16 read_srom_word(int); +static u8 DM9000_ior(int); +static void DM9000_iow(int reg, u8 value); + +/* DM9000 network board routine ---------------------------- */ + +#define DM9000_outb(d,r) ( *(volatile u8 *)r = d ) +#define DM9000_outw(d,r) ( *(volatile u16 *)r = d ) +#define DM9000_outl(d,r) ( *(volatile u32 *)r = d ) +#define DM9000_inb(r) (*(volatile u8 *)r) +#define DM9000_inw(r) (*(volatile u16 *)r) +#define DM9000_inl(r) (*(volatile u32 *)r) + +#ifdef CONFIG_DM9000_DEBUG +static void +dump_regs(void) +{ + DM9000_DBG("\n"); + DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0)); + DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1)); + DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2)); + DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3)); + DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4)); + DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5)); + DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6)); + DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(ISR)); + DM9000_DBG("\n"); +} +#endif /* */ + +/* + Search DM9000 board, allocate space and register it +*/ +int +dm9000_probe(void) +{ + u32 id_val; + id_val = DM9000_ior(DM9000_VIDL); + id_val |= DM9000_ior(DM9000_VIDH) << 8; + id_val |= DM9000_ior(DM9000_PIDL) << 16; + id_val |= DM9000_ior(DM9000_PIDH) << 24; + if (id_val == DM9000_ID) { + printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE, + id_val); + return 0; + } else { + printf("dm9000 not found at 0x%08x id: 0x%08x\n", + CONFIG_DM9000_BASE, id_val); + return -1; + } +} + +/* Set PHY operationg mode +*/ +static void +set_PHY_mode(void) +{ + u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000; + if (!(media_mode & DM9000_AUTO)) { + switch (media_mode) { + case DM9000_10MHD: + phy_reg4 = 0x21; + phy_reg0 = 0x0000; + break; + case DM9000_10MFD: + phy_reg4 = 0x41; + phy_reg0 = 0x1100; + break; + case DM9000_100MHD: + phy_reg4 = 0x81; + phy_reg0 = 0x2000; + break; + case DM9000_100MFD: + phy_reg4 = 0x101; + phy_reg0 = 0x3100; + break; + } + phy_write(4, phy_reg4); /* Set PHY media mode */ + phy_write(0, phy_reg0); /* Tmp */ + } + DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */ + DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */ +} + +/* + Init HomeRun DM9801 +*/ +static void +program_dm9801(u16 HPNA_rev) +{ + __u16 reg16, reg17, reg24, reg25; + if (!nfloor) + nfloor = DM9801_NOISE_FLOOR; + reg16 = phy_read(16); + reg17 = phy_read(17); + reg24 = phy_read(24); + reg25 = phy_read(25); + switch (HPNA_rev) { + case 0xb900: /* DM9801 E3 */ + reg16 |= 0x1000; + reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000; + break; + case 0xb901: /* DM9801 E4 */ + reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200; + reg17 = (reg17 & 0xfff0) + nfloor + 3; + break; + case 0xb902: /* DM9801 E5 */ + case 0xb903: /* DM9801 E6 */ + default: + reg16 |= 0x1000; + reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200; + reg17 = (reg17 & 0xfff0) + nfloor; + } + phy_write(16, reg16); + phy_write(17, reg17); + phy_write(25, reg25); +} + +/* + Init LongRun DM9802 +*/ +static void +program_dm9802(void) +{ + __u16 reg25; + if (!nfloor) + nfloor = DM9802_NOISE_FLOOR; + reg25 = phy_read(25); + reg25 = (reg25 & 0xff00) + nfloor; + phy_write(25, reg25); +} + +/* Identify NIC type +*/ +static void +identify_nic(void) +{ + struct board_info *db = &dmfe_info; /* Point a board information structure */ + u16 phy_reg3; + DM9000_iow(DM9000_NCR, NCR_EXT_PHY); + phy_reg3 = phy_read(3); + switch (phy_reg3 & 0xfff0) { + case 0xb900: + if (phy_read(31) == 0x4404) { + db->nic_type = HOMERUN_NIC; + program_dm9801(phy_reg3); + DM9000_DBG("found homerun NIC\n"); + } else { + db->nic_type = LONGRUN_NIC; + DM9000_DBG("found longrun NIC\n"); + program_dm9802(); + } + break; + default: + db->nic_type = FASTETHER_NIC; + break; + } + DM9000_iow(DM9000_NCR, 0); +} + +/* General Purpose dm9000 reset routine */ +static void +dm9000_reset(void) +{ + DM9000_DBG("resetting\n"); + DM9000_iow(DM9000_NCR, NCR_RST); + udelay(1000); /* delay 1ms */ +} + +/* Initilize dm9000 board +*/ +int +eth_init(bd_t * bd) +{ + int i, oft, lnk; + DM9000_DBG("eth_init()\n"); + + /* RESET device */ + dm9000_reset(); + dm9000_probe(); + + /* NIC Type: FASTETHER, HOMERUN, LONGRUN */ + identify_nic(); + + /* GPIO0 on pre-activate PHY */ + DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */ + + /* Set PHY */ + set_PHY_mode(); + + /* Program operating register */ + DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */ + DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */ + DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ + DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */ + DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */ + DM9000_iow(DM9000_SMCR, 0); /* Special Mode */ + DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */ + DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */ + + /* Set Node address */ + for (i = 0; i < 6; i++) + ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i); + printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0], + bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3], + bd->bi_enetaddr[4], bd->bi_enetaddr[5]); + for (i = 0, oft = 0x10; i < 6; i++, oft++) + DM9000_iow(oft, bd->bi_enetaddr[i]); + for (i = 0, oft = 0x16; i < 8; i++, oft++) + DM9000_iow(oft, 0xff); + + /* read back mac, just to be sure */ + for (i = 0, oft = 0x10; i < 6; i++, oft++) + DM9000_DBG("%02x:", DM9000_ior(oft)); + DM9000_DBG("\n"); + + /* Activate DM9000 */ + DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */ + DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */ + i = 0; + while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */ + udelay(1000); + i++; + if (i == 10000) { + printf("could not establish link\n"); + return 0; + } + } + + /* see what we've got */ + lnk = phy_read(17) >> 12; + printf("operating at "); + switch (lnk) { + case 1: + printf("10M half duplex "); + break; + case 2: + printf("10M full duplex "); + break; + case 4: + printf("100M half duplex "); + break; + case 8: + printf("100M full duplex "); + break; + default: + printf("unknown: %d ", lnk); + break; + } + printf("mode\n"); + return 0; +} + +/* + Hardware start transmission. + Send a packet to media from the upper layer. +*/ +int +eth_send(volatile void *packet, int length) +{ + char *data_ptr; + u32 tmplen, i; + int tmo; + DM9000_DBG("eth_send: length: %d\n", length); + for (i = 0; i < length; i++) { + if (i % 8 == 0) + DM9000_DBG("\nSend: 02x: ", i); + DM9000_DBG("%02x ", ((unsigned char *) packet)[i]); + } DM9000_DBG("\n"); + + /* Move data to DM9000 TX RAM */ + data_ptr = (char *) packet; + DM9000_outb(DM9000_MWCMD, DM9000_IO); + +#ifdef CONFIG_DM9000_USE_8BIT + /* Byte mode */ + for (i = 0; i < length; i++) + DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_16BIT + tmplen = (length + 1) / 2; + for (i = 0; i < tmplen; i++) + DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_32BIT + tmplen = (length + 3) / 4; + for (i = 0; i < tmplen; i++) + DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA); + +#endif /* */ + + /* Set TX length to DM9000 */ + DM9000_iow(DM9000_TXPLL, length & 0xff); + DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff); + + /* Issue TX polling command */ + DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ + + /* wait for end of transmission */ + tmo = get_timer(0) + 5 * CFG_HZ; + while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) { + if (get_timer(0) >= tmo) { + printf("transmission timeout\n"); + break; + } + } + DM9000_DBG("transmit done\n\n"); + return 0; +} + +/* + Stop the interface. + The interface is stopped when it is brought. +*/ +void +eth_halt(void) +{ + DM9000_DBG("eth_halt\n"); + + /* RESET devie */ + phy_write(0, 0x8000); /* PHY RESET */ + DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */ + DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */ + DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */ +} + +/* + Received a packet and pass to upper layer +*/ +int +eth_rx(void) +{ + u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0]; + u16 RxStatus, RxLen = 0; + u32 tmplen, i; + + /* Check packet ready or not */ + DM9000_ior(DM9000_MRCMDX); /* Dummy read */ + rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */ + if (rxbyte == 0) + return 0; + + /* Status check: this byte must be 0 or 1 */ + if (rxbyte > 1) { + DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */ + DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */ + DM9000_DBG("rx status check: %d\n", rxbyte); + } + DM9000_DBG("receiving packet\n"); + + /* A packet ready now & Get status/length */ + DM9000_outb(DM9000_MRCMD, DM9000_IO); + +#ifdef CONFIG_DM9000_USE_8BIT + RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); + RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_16BIT + RxStatus = DM9000_inw(DM9000_DATA); + RxLen = DM9000_inw(DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_32BIT + tmpdata = DM9000_inl(DM9000_DATA); + RxStatus = tmpdata; + RxLen = tmpdata >> 16; + +#endif /* */ + DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen); + + /* Move data from DM9000 */ + /* Read received packet from RX SRAM */ +#ifdef CONFIG_DM9000_USE_8BIT + for (i = 0; i < RxLen; i++) + rdptr[i] = DM9000_inb(DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_16BIT + tmplen = (RxLen + 1) / 2; + for (i = 0; i < tmplen; i++) + ((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA); + +#endif /* */ +#ifdef CONFIG_DM9000_USE_32BIT + tmplen = (RxLen + 3) / 4; + for (i = 0; i < tmplen; i++) + ((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA); + +#endif /* */ + if ((RxStatus & 0xbf00) || (RxLen < 0x40) + || (RxLen > DM9000_PKT_MAX)) { + if (RxStatus & 0x100) { + printf("rx fifo error\n"); + } + if (RxStatus & 0x200) { + printf("rx crc error\n"); + } + if (RxStatus & 0x8000) { + printf("rx length error\n"); + } + if (RxLen > DM9000_PKT_MAX) { + printf("rx length too big\n"); + dm9000_reset(); + } + } else { + + /* Pass to upper layer */ + DM9000_DBG("passing packet to upper layer\n"); + NetReceive(NetRxPackets[0], RxLen); + return RxLen; + } + return 0; +} + +/* + Read a word data from SROM +*/ +static u16 +read_srom_word(int offset) +{ + DM9000_iow(DM9000_EPAR, offset); + DM9000_iow(DM9000_EPCR, 0x4); + udelay(200); + DM9000_iow(DM9000_EPCR, 0x0); + return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8)); +} + +/* + Read a byte from I/O port +*/ +static u8 +DM9000_ior(int reg) +{ + DM9000_outb(reg, DM9000_IO); + return DM9000_inb(DM9000_DATA); +} + +/* + Write a byte to I/O port +*/ +static void +DM9000_iow(int reg, u8 value) +{ + DM9000_outb(reg, DM9000_IO); + DM9000_outb(value, DM9000_DATA); +} + +/* + Read a word from phyxcer +*/ +static u16 +phy_read(int reg) +{ + u16 val; + + /* Fill the phyxcer register into REG_0C */ + DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); + DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ + udelay(100); /* Wait read complete */ + DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ + val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); + + /* The read data keeps on REG_0D & REG_0E */ + DM9000_DBG("phy_read(%d): %d\n", reg, val); + return val; +} + +/* + Write a word to phyxcer +*/ +static void +phy_write(int reg, u16 value) +{ + + /* Fill the phyxcer register into REG_0C */ + DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); + + /* Fill the written data into REG_0D & REG_0E */ + DM9000_iow(DM9000_EPDRL, (value & 0xff)); + DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); + DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ + udelay(500); /* Wait write complete */ + DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ + DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value); +} +#endif /* CONFIG_DRIVER_DM9000 */ diff --git a/drivers/dm9000x.h b/drivers/dm9000x.h new file mode 100644 index 000000000..f47ff8cb3 --- /dev/null +++ b/drivers/dm9000x.h @@ -0,0 +1,119 @@ +/* + * dm9000 Ethernet + */ + +#ifdef CONFIG_DRIVER_DM9000 + +#define DM9000_ID 0x90000A46 +#define DM9000_PKT_MAX 1536 /* Received packet max size */ +#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */ + +/* although the registers are 16 bit, they are 32-bit aligned. + */ + +#define DM9000_NCR 0x00 +#define DM9000_NSR 0x01 +#define DM9000_TCR 0x02 +#define DM9000_TSR1 0x03 +#define DM9000_TSR2 0x04 +#define DM9000_RCR 0x05 +#define DM9000_RSR 0x06 +#define DM9000_ROCR 0x07 +#define DM9000_BPTR 0x08 +#define DM9000_FCTR 0x09 +#define DM9000_FCR 0x0A +#define DM9000_EPCR 0x0B +#define DM9000_EPAR 0x0C +#define DM9000_EPDRL 0x0D +#define DM9000_EPDRH 0x0E +#define DM9000_WCR 0x0F + +#define DM9000_PAR 0x10 +#define DM9000_MAR 0x16 + +#define DM9000_GPCR 0x1e +#define DM9000_GPR 0x1f +#define DM9000_TRPAL 0x22 +#define DM9000_TRPAH 0x23 +#define DM9000_RWPAL 0x24 +#define DM9000_RWPAH 0x25 + +#define DM9000_VIDL 0x28 +#define DM9000_VIDH 0x29 +#define DM9000_PIDL 0x2A +#define DM9000_PIDH 0x2B + +#define DM9000_CHIPR 0x2C +#define DM9000_SMCR 0x2F + +#define DM9000_PHY 0x40 /* PHY address 0x01 */ + +#define DM9000_MRCMDX 0xF0 +#define DM9000_MRCMD 0xF2 +#define DM9000_MRRL 0xF4 +#define DM9000_MRRH 0xF5 +#define DM9000_MWCMDX 0xF6 +#define DM9000_MWCMD 0xF8 +#define DM9000_MWRL 0xFA +#define DM9000_MWRH 0xFB +#define DM9000_TXPLL 0xFC +#define DM9000_TXPLH 0xFD +#define DM9000_ISR 0xFE +#define DM9000_IMR 0xFF + +#define NCR_EXT_PHY (1<<7) +#define NCR_WAKEEN (1<<6) +#define NCR_FCOL (1<<4) +#define NCR_FDX (1<<3) +#define NCR_LBK (3<<1) +#define NCR_RST (1<<0) + +#define NSR_SPEED (1<<7) +#define NSR_LINKST (1<<6) +#define NSR_WAKEST (1<<5) +#define NSR_TX2END (1<<3) +#define NSR_TX1END (1<<2) +#define NSR_RXOV (1<<1) + +#define TCR_TJDIS (1<<6) +#define TCR_EXCECM (1<<5) +#define TCR_PAD_DIS2 (1<<4) +#define TCR_CRC_DIS2 (1<<3) +#define TCR_PAD_DIS1 (1<<2) +#define TCR_CRC_DIS1 (1<<1) +#define TCR_TXREQ (1<<0) + +#define TSR_TJTO (1<<7) +#define TSR_LC (1<<6) +#define TSR_NC (1<<5) +#define TSR_LCOL (1<<4) +#define TSR_COL (1<<3) +#define TSR_EC (1<<2) + +#define RCR_WTDIS (1<<6) +#define RCR_DIS_LONG (1<<5) +#define RCR_DIS_CRC (1<<4) +#define RCR_ALL (1<<3) +#define RCR_RUNT (1<<2) +#define RCR_PRMSC (1<<1) +#define RCR_RXEN (1<<0) + +#define RSR_RF (1<<7) +#define RSR_MF (1<<6) +#define RSR_LCS (1<<5) +#define RSR_RWTO (1<<4) +#define RSR_PLE (1<<3) +#define RSR_AE (1<<2) +#define RSR_CE (1<<1) +#define RSR_FOE (1<<0) + +#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 ) +#define FCTR_LWOT(ot) ( ot & 0xf ) + +#define IMR_PAR (1<<7) +#define IMR_ROOM (1<<3) +#define IMR_ROM (1<<2) +#define IMR_PTM (1<<1) +#define IMR_PRM (1<<0) + +#endif diff --git a/drivers/ds1722.c b/drivers/ds1722.c new file mode 100644 index 000000000..227d8169a --- /dev/null +++ b/drivers/ds1722.c @@ -0,0 +1,142 @@ + +#include + +#include + +#ifdef CONFIG_DS1722 + +static void ds1722_select(int dev) +{ + ssi_set_interface(4096, 0, 0, 0); + ssi_chip_select(0); + udelay(1); + ssi_chip_select(dev); + udelay(1); +} + + +u8 ds1722_read(int dev, int addr) +{ + u8 res; + + ds1722_select(dev); + + ssi_tx_byte(addr); + res = ssi_rx_byte(); + + ssi_chip_select(0); + + return res; +} + +void ds1722_write(int dev, int addr, u8 data) +{ + ds1722_select(dev); + + ssi_tx_byte(0x80|addr); + ssi_tx_byte(data); + + ssi_chip_select(0); +} + + +u16 ds1722_temp(int dev, int resolution) +{ + static int useconds[] = { + 75000, 150000, 300000, 600000, 1200000 + }; + char temp; + u16 res; + + + /* set up the desired resulotion ... */ + ds1722_write(dev, 0, 0xe0 | (resolution << 1)); + + /* wait while the chip measures the tremperature */ + udelay(useconds[resolution]); + + res = (temp = ds1722_read(dev, 2)) << 8; + + if (temp < 0) { + temp = (16 - (ds1722_read(dev, 1) >> 4)) & 0x0f; + } else { + temp = (ds1722_read(dev, 1) >> 4); + } + + switch (temp) { + case 0: + /* .0000 */ + break; + case 1: + /* .0625 */ + res |=1; + break; + case 2: + /* .1250 */ + res |=1; + break; + case 3: + /* .1875 */ + res |=2; + break; + case 4: + /* .2500 */ + res |=3; + break; + case 5: + /* .3125 */ + res |=3; + break; + case 6: + /* .3750 */ + res |=4; + break; + case 7: + /* .4375 */ + res |=4; + break; + case 8: + /* .5000 */ + res |=5; + break; + case 9: + /* .5625 */ + res |=6; + break; + case 10: + /* .6250 */ + res |=6; + break; + case 11: + /* .6875 */ + res |=7; + break; + case 12: + /* .7500 */ + res |=8; + break; + case 13: + /* .8125 */ + res |=8; + break; + case 14: + /* .8750 */ + res |=9; + break; + case 15: + /* .9375 */ + res |=9; + break; + } + return res; + +} + +int ds1722_probe(int dev) +{ + u16 temp = ds1722_temp(dev, DS1722_RESOLUTION_12BIT); + printf("%d.%d deg C\n\n", (char)(temp >> 8), temp & 0xff); + return 0; +} + +#endif diff --git a/drivers/e1000.c b/drivers/e1000.c new file mode 100644 index 000000000..927acbb26 --- /dev/null +++ b/drivers/e1000.c @@ -0,0 +1,3016 @@ +/************************************************************************** +Inter Pro 1000 for ppcboot/das-u-boot +Drivers are port from Intel's Linux driver e1000-4.3.15 +and from Etherboot pro 1000 driver by mrakes at vivato dot net +tested on both gig copper and gig fiber boards +***************************************************************************/ +/******************************************************************************* + + + Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program; if not, write to the Free Software Foundation, Inc., 59 + Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + The full GNU General Public License is included in this distribution in the + file called LICENSE. + + Contact Information: + Linux NICS + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +*******************************************************************************/ +/* + * Copyright (C) Archway Digital Solutions. + * + * written by Chrsitopher Li or + * 2/9/2002 + * + * Copyright (C) Linux Networx. + * Massive upgrade to work with the new intel gigabit NICs. + * + */ + +#include "e1000.h" + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_E1000) + +#define TOUT_LOOP 100000 + +#undef virt_to_bus +#define virt_to_bus(x) ((unsigned long)x) +#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) +#define mdelay(n) udelay((n)*1000) + +#define E1000_DEFAULT_PBA 0x00000030 + +/* NIC specific static variables go here */ + +static char tx_pool[128 + 16]; +static char rx_pool[128 + 16]; +static char packet[2096]; + +static struct e1000_tx_desc *tx_base; +static struct e1000_rx_desc *rx_base; + +static int tx_tail; +static int rx_tail, rx_last; + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, +}; + +/* Function forward declarations */ +static int e1000_setup_link(struct eth_device *nic); +static int e1000_setup_fiber_link(struct eth_device *nic); +static int e1000_setup_copper_link(struct eth_device *nic); +static int e1000_phy_setup_autoneg(struct e1000_hw *hw); +static void e1000_config_collision_dist(struct e1000_hw *hw); +static int e1000_config_mac_to_phy(struct e1000_hw *hw); +static int e1000_config_fc_after_link_up(struct e1000_hw *hw); +static int e1000_check_for_link(struct eth_device *nic); +static int e1000_wait_autoneg(struct e1000_hw *hw); +static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, + uint16_t * duplex); +static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, + uint16_t * phy_data); +static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, + uint16_t phy_data); +static void e1000_phy_hw_reset(struct e1000_hw *hw); +static int e1000_phy_reset(struct e1000_hw *hw); +static int e1000_detect_gig_phy(struct e1000_hw *hw); + +#define E1000_WRITE_REG(a, reg, value) (writel((value), ((a)->hw_addr + E1000_##reg))) +#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_##reg)) +#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\ + writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))) +#define E1000_READ_REG_ARRAY(a, reg, offset) ( \ + readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) +#define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} + +#ifndef CONFIG_AP1000 /* remove for warnings */ +/****************************************************************************** + * Raises the EEPROM's clock input. + * + * hw - Struct containing variables accessed by shared code + * eecd - EECD's current value + *****************************************************************************/ +static void +e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) +{ + /* Raise the clock input to the EEPROM (by setting the SK bit), and then + * wait 50 microseconds. + */ + *eecd = *eecd | E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, *eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); +} + +/****************************************************************************** + * Lowers the EEPROM's clock input. + * + * hw - Struct containing variables accessed by shared code + * eecd - EECD's current value + *****************************************************************************/ +static void +e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) +{ + /* Lower the clock input to the EEPROM (by clearing the SK bit), and then + * wait 50 microseconds. + */ + *eecd = *eecd & ~E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, *eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); +} + +/****************************************************************************** + * Shift data bits out to the EEPROM. + * + * hw - Struct containing variables accessed by shared code + * data - data to send to the EEPROM + * count - number of bits to shift out + *****************************************************************************/ +static void +e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) +{ + uint32_t eecd; + uint32_t mask; + + /* We need to shift "count" bits out to the EEPROM. So, value in the + * "data" parameter will be shifted out to the EEPROM one bit at a time. + * In order to do this, "data" must be broken down into bits. + */ + mask = 0x01 << (count - 1); + eecd = E1000_READ_REG(hw, EECD); + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); + do { + /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", + * and then raising and then lowering the clock (the SK bit controls + * the clock input to the EEPROM). A "0" is shifted out to the EEPROM + * by setting "DI" to "0" and then raising and then lowering the clock. + */ + eecd &= ~E1000_EECD_DI; + + if (data & mask) + eecd |= E1000_EECD_DI; + + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + + udelay(50); + + e1000_raise_ee_clk(hw, &eecd); + e1000_lower_ee_clk(hw, &eecd); + + mask = mask >> 1; + + } while (mask); + + /* We leave the "DI" bit set to "0" when we leave this routine. */ + eecd &= ~E1000_EECD_DI; + E1000_WRITE_REG(hw, EECD, eecd); +} + +/****************************************************************************** + * Shift data bits in from the EEPROM + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static uint16_t +e1000_shift_in_ee_bits(struct e1000_hw *hw) +{ + uint32_t eecd; + uint32_t i; + uint16_t data; + + /* In order to read a register from the EEPROM, we need to shift 16 bits + * in from the EEPROM. Bits are "shifted in" by raising the clock input to + * the EEPROM (setting the SK bit), and then reading the value of the "DO" + * bit. During this "shifting in" process the "DI" bit should always be + * clear.. + */ + + eecd = E1000_READ_REG(hw, EECD); + + eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); + data = 0; + + for (i = 0; i < 16; i++) { + data = data << 1; + e1000_raise_ee_clk(hw, &eecd); + + eecd = E1000_READ_REG(hw, EECD); + + eecd &= ~(E1000_EECD_DI); + if (eecd & E1000_EECD_DO) + data |= 1; + + e1000_lower_ee_clk(hw, &eecd); + } + + return data; +} + +/****************************************************************************** + * Prepares EEPROM for access + * + * hw - Struct containing variables accessed by shared code + * + * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This + * function should be called before issuing a command to the EEPROM. + *****************************************************************************/ +static void +e1000_setup_eeprom(struct e1000_hw *hw) +{ + uint32_t eecd; + + eecd = E1000_READ_REG(hw, EECD); + + /* Clear SK and DI */ + eecd &= ~(E1000_EECD_SK | E1000_EECD_DI); + E1000_WRITE_REG(hw, EECD, eecd); + + /* Set CS */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); +} + +/****************************************************************************** + * Returns EEPROM to a "standby" state + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static void +e1000_standby_eeprom(struct e1000_hw *hw) +{ + uint32_t eecd; + + eecd = E1000_READ_REG(hw, EECD); + + /* Deselct EEPROM */ + eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); + + /* Clock high */ + eecd |= E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); + + /* Select EEPROM */ + eecd |= E1000_EECD_CS; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); + + /* Clock low */ + eecd &= ~E1000_EECD_SK; + E1000_WRITE_REG(hw, EECD, eecd); + E1000_WRITE_FLUSH(hw); + udelay(50); +} + +/****************************************************************************** + * Reads a 16 bit word from the EEPROM. + * + * hw - Struct containing variables accessed by shared code + * offset - offset of word in the EEPROM to read + * data - word read from the EEPROM + *****************************************************************************/ +static int +e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data) +{ + uint32_t eecd; + uint32_t i = 0; + int large_eeprom = FALSE; + + /* Request EEPROM Access */ + if (hw->mac_type > e1000_82544) { + eecd = E1000_READ_REG(hw, EECD); + if (eecd & E1000_EECD_SIZE) + large_eeprom = TRUE; + eecd |= E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + eecd = E1000_READ_REG(hw, EECD); + while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { + i++; + udelay(10); + eecd = E1000_READ_REG(hw, EECD); + } + if (!(eecd & E1000_EECD_GNT)) { + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + DEBUGOUT("Could not acquire EEPROM grant\n"); + return -E1000_ERR_EEPROM; + } + } + + /* Prepare the EEPROM for reading */ + e1000_setup_eeprom(hw); + + /* Send the READ command (opcode + addr) */ + e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3); + e1000_shift_out_ee_bits(hw, offset, (large_eeprom) ? 8 : 6); + + /* Read the data */ + *data = e1000_shift_in_ee_bits(hw); + + /* End this read operation */ + e1000_standby_eeprom(hw); + + /* Stop requesting EEPROM access */ + if (hw->mac_type > e1000_82544) { + eecd = E1000_READ_REG(hw, EECD); + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + } + + return 0; +} + +#if 0 +static void +e1000_eeprom_cleanup(struct e1000_hw *hw) +{ + uint32_t eecd; + + eecd = E1000_READ_REG(hw, EECD); + eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); + E1000_WRITE_REG(hw, EECD, eecd); + e1000_raise_ee_clk(hw, &eecd); + e1000_lower_ee_clk(hw, &eecd); +} + +static uint16_t +e1000_wait_eeprom_done(struct e1000_hw *hw) +{ + uint32_t eecd; + uint32_t i; + + e1000_standby_eeprom(hw); + for (i = 0; i < 200; i++) { + eecd = E1000_READ_REG(hw, EECD); + if (eecd & E1000_EECD_DO) + return (TRUE); + udelay(5); + } + return (FALSE); +} + +static int +e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data) +{ + uint32_t eecd; + int large_eeprom = FALSE; + int i = 0; + + /* Request EEPROM Access */ + if (hw->mac_type > e1000_82544) { + eecd = E1000_READ_REG(hw, EECD); + if (eecd & E1000_EECD_SIZE) + large_eeprom = TRUE; + eecd |= E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + eecd = E1000_READ_REG(hw, EECD); + while ((!(eecd & E1000_EECD_GNT)) && (i < 100)) { + i++; + udelay(5); + eecd = E1000_READ_REG(hw, EECD); + } + if (!(eecd & E1000_EECD_GNT)) { + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + DEBUGOUT("Could not acquire EEPROM grant\n"); + return FALSE; + } + } + e1000_setup_eeprom(hw); + e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5); + e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); + e1000_standby_eeprom(hw); + e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3); + e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 8 : 6); + e1000_shift_out_ee_bits(hw, Data, 16); + if (!e1000_wait_eeprom_done(hw)) { + return FALSE; + } + e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5); + e1000_shift_out_ee_bits(hw, Reg, (large_eeprom) ? 6 : 4); + e1000_eeprom_cleanup(hw); + + /* Stop requesting EEPROM access */ + if (hw->mac_type > e1000_82544) { + eecd = E1000_READ_REG(hw, EECD); + eecd &= ~E1000_EECD_REQ; + E1000_WRITE_REG(hw, EECD, eecd); + } + i = 0; + eecd = E1000_READ_REG(hw, EECD); + while (((eecd & E1000_EECD_GNT)) && (i < 500)) { + i++; + udelay(10); + eecd = E1000_READ_REG(hw, EECD); + } + if ((eecd & E1000_EECD_GNT)) { + DEBUGOUT("Could not release EEPROM grant\n"); + } + return TRUE; +} +#endif + +/****************************************************************************** + * Verifies that the EEPROM has a valid checksum + * + * hw - Struct containing variables accessed by shared code + * + * Reads the first 64 16 bit words of the EEPROM and sums the values read. + * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is + * valid. + *****************************************************************************/ +static int +e1000_validate_eeprom_checksum(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint16_t checksum = 0; + uint16_t i, eeprom_data; + + DEBUGFUNC(); + + for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { + if (e1000_read_eeprom(hw, i, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + checksum += eeprom_data; + } + + if (checksum == (uint16_t) EEPROM_SUM) { + return 0; + } else { + DEBUGOUT("EEPROM Checksum Invalid\n"); + return -E1000_ERR_EEPROM; + } +} +#endif /* #ifndef CONFIG_AP1000 */ + +/****************************************************************************** + * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the + * second function of dual function devices + * + * nic - Struct containing variables accessed by shared code + *****************************************************************************/ +static int +e1000_read_mac_addr(struct eth_device *nic) +{ +#ifndef CONFIG_AP1000 + struct e1000_hw *hw = nic->priv; + uint16_t offset; + uint16_t eeprom_data; + int i; + + DEBUGFUNC(); + + for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { + offset = i >> 1; + if (e1000_read_eeprom(hw, offset, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } + nic->enetaddr[i] = eeprom_data & 0xff; + nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; + } + if ((hw->mac_type == e1000_82546) && + (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { + /* Invert the last bit if this is the second device */ + nic->enetaddr[5] += 1; + } +#else + /* + * The AP1000's e1000 has no eeprom; the MAC address is stored in the + * environment variables. Currently this does not support the addition + * of a PMC e1000 card, which is certainly a possibility, so this should + * be updated to properly use the env variable only for the onboard e1000 + */ + + int ii; + char *s, *e; + + DEBUGFUNC(); + + s = getenv ("ethaddr"); + if (s == NULL){ + return -E1000_ERR_EEPROM; + } + else{ + for(ii = 0; ii < 6; ii++) { + nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0; + if (s){ + s = (*e) ? e + 1 : e; + } + } + } +#endif + return 0; +} + +/****************************************************************************** + * Initializes receive address filters. + * + * hw - Struct containing variables accessed by shared code + * + * Places the MAC address in receive address register 0 and clears the rest + * of the receive addresss registers. Clears the multicast table. Assumes + * the receiver is in reset when the routine is called. + *****************************************************************************/ +static void +e1000_init_rx_addrs(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t i; + uint32_t addr_low; + uint32_t addr_high; + + DEBUGFUNC(); + + /* Setup the receive address. */ + DEBUGOUT("Programming MAC Address into RAR[0]\n"); + addr_low = (nic->enetaddr[0] | + (nic->enetaddr[1] << 8) | + (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); + + addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); + + E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); + E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); + + /* Zero out the other 15 receive addresses. */ + DEBUGOUT("Clearing RAR[1-15]\n"); + for (i = 1; i < E1000_RAR_ENTRIES; i++) { + E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); + E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); + } +} + +/****************************************************************************** + * Clears the VLAN filer table + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static void +e1000_clear_vfta(struct e1000_hw *hw) +{ + uint32_t offset; + + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) + E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); +} + +/****************************************************************************** + * Set the mac type member in the hw struct. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +static int +e1000_set_mac_type(struct e1000_hw *hw) +{ + DEBUGFUNC(); + + switch (hw->device_id) { + case E1000_DEV_ID_82542: + switch (hw->revision_id) { + case E1000_82542_2_0_REV_ID: + hw->mac_type = e1000_82542_rev2_0; + break; + case E1000_82542_2_1_REV_ID: + hw->mac_type = e1000_82542_rev2_1; + break; + default: + /* Invalid 82542 revision ID */ + return -E1000_ERR_MAC_TYPE; + } + break; + case E1000_DEV_ID_82543GC_FIBER: + case E1000_DEV_ID_82543GC_COPPER: + hw->mac_type = e1000_82543; + break; + case E1000_DEV_ID_82544EI_COPPER: + case E1000_DEV_ID_82544EI_FIBER: + case E1000_DEV_ID_82544GC_COPPER: + case E1000_DEV_ID_82544GC_LOM: + hw->mac_type = e1000_82544; + break; + case E1000_DEV_ID_82540EM: + case E1000_DEV_ID_82540EM_LOM: + hw->mac_type = e1000_82540; + break; + case E1000_DEV_ID_82545EM_COPPER: + case E1000_DEV_ID_82545EM_FIBER: + hw->mac_type = e1000_82545; + break; + case E1000_DEV_ID_82546EB_COPPER: + case E1000_DEV_ID_82546EB_FIBER: + hw->mac_type = e1000_82546; + break; + default: + /* Should never have loaded on this device */ + return -E1000_ERR_MAC_TYPE; + } + return E1000_SUCCESS; +} + +/****************************************************************************** + * Reset the transmit and receive units; mask and clear all interrupts. + * + * hw - Struct containing variables accessed by shared code + *****************************************************************************/ +void +e1000_reset_hw(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint32_t ctrl_ext; + uint32_t icr; + uint32_t manc; + + DEBUGFUNC(); + + /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ + if (hw->mac_type == e1000_82542_rev2_0) { + DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); + pci_write_config_word(hw->pdev, PCI_COMMAND, + hw-> + pci_cmd_word & ~PCI_COMMAND_INVALIDATE); + } + + /* Clear interrupt mask to stop board from generating interrupts */ + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, IMC, 0xffffffff); + + /* Disable the Transmit and Receive units. Then delay to allow + * any pending transactions to complete before we hit the MAC with + * the global reset. + */ + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); + E1000_WRITE_FLUSH(hw); + + /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ + hw->tbi_compatibility_on = FALSE; + + /* Delay to allow any outstanding PCI transactions to complete before + * resetting the device + */ + mdelay(10); + + /* Issue a global reset to the MAC. This will reset the chip's + * transmit, receive, DMA, and link units. It will not effect + * the current PCI configuration. The global reset bit is self- + * clearing, and should clear within a microsecond. + */ + DEBUGOUT("Issuing a global reset to MAC\n"); + ctrl = E1000_READ_REG(hw, CTRL); + +#if 0 + if (hw->mac_type > e1000_82543) + E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); + else +#endif + E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); + + /* Force a reload from the EEPROM if necessary */ + if (hw->mac_type < e1000_82540) { + /* Wait for reset to complete */ + udelay(10); + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_EE_RST; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + /* Wait for EEPROM reload */ + mdelay(2); + } else { + /* Wait for EEPROM reload (it happens automatically) */ + mdelay(4); + /* Dissable HW ARPs on ASF enabled adapters */ + manc = E1000_READ_REG(hw, MANC); + manc &= ~(E1000_MANC_ARP_EN); + E1000_WRITE_REG(hw, MANC, manc); + } + + /* Clear interrupt mask to stop board from generating interrupts */ + DEBUGOUT("Masking off all interrupts\n"); + E1000_WRITE_REG(hw, IMC, 0xffffffff); + + /* Clear any pending interrupt events. */ + icr = E1000_READ_REG(hw, ICR); + + /* If MWI was previously enabled, reenable it. */ + if (hw->mac_type == e1000_82542_rev2_0) { + pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); + } +} + +/****************************************************************************** + * Performs basic configuration of the adapter. + * + * hw - Struct containing variables accessed by shared code + * + * Assumes that the controller has previously been reset and is in a + * post-reset uninitialized state. Initializes the receive address registers, + * multicast table, and VLAN filter table. Calls routines to setup link + * configuration and flow control settings. Clears all on-chip counters. Leaves + * the transmit and receive units disabled and uninitialized. + *****************************************************************************/ +static int +e1000_init_hw(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t ctrl, status; + uint32_t i; + int32_t ret_val; + uint16_t pcix_cmd_word; + uint16_t pcix_stat_hi_word; + uint16_t cmd_mmrbc; + uint16_t stat_mmrbc; + e1000_bus_type bus_type = e1000_bus_type_unknown; + + DEBUGFUNC(); +#if 0 + /* Initialize Identification LED */ + ret_val = e1000_id_led_init(hw); + if (ret_val < 0) { + DEBUGOUT("Error Initializing Identification LED\n"); + return ret_val; + } +#endif + /* Set the Media Type and exit with error if it is not valid. */ + if (hw->mac_type != e1000_82543) { + /* tbi_compatibility is only valid on 82543 */ + hw->tbi_compatibility_en = FALSE; + } + + if (hw->mac_type >= e1000_82543) { + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_TBIMODE) { + hw->media_type = e1000_media_type_fiber; + /* tbi_compatibility not valid on fiber */ + hw->tbi_compatibility_en = FALSE; + } else { + hw->media_type = e1000_media_type_copper; + } + } else { + /* This is an 82542 (fiber only) */ + hw->media_type = e1000_media_type_fiber; + } + + /* Disabling VLAN filtering. */ + DEBUGOUT("Initializing the IEEE VLAN\n"); + E1000_WRITE_REG(hw, VET, 0); + + e1000_clear_vfta(hw); + + /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ + if (hw->mac_type == e1000_82542_rev2_0) { + DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); + pci_write_config_word(hw->pdev, PCI_COMMAND, + hw-> + pci_cmd_word & ~PCI_COMMAND_INVALIDATE); + E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); + E1000_WRITE_FLUSH(hw); + mdelay(5); + } + + /* Setup the receive address. This involves initializing all of the Receive + * Address Registers (RARs 0 - 15). + */ + e1000_init_rx_addrs(nic); + + /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ + if (hw->mac_type == e1000_82542_rev2_0) { + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_FLUSH(hw); + mdelay(1); + pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); + } + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < E1000_MC_TBL_SIZE; i++) + E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); + +#if 0 + /* Set the PCI priority bit correctly in the CTRL register. This + * determines if the adapter gives priority to receives, or if it + * gives equal priority to transmits and receives. + */ + if (hw->dma_fairness) { + ctrl = E1000_READ_REG(hw, CTRL); + E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); + } +#endif + if (hw->mac_type >= e1000_82543) { + status = E1000_READ_REG(hw, STATUS); + bus_type = (status & E1000_STATUS_PCIX_MODE) ? + e1000_bus_type_pcix : e1000_bus_type_pci; + } + /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ + if (bus_type == e1000_bus_type_pcix) { + pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, + &pcix_cmd_word); + pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, + &pcix_stat_hi_word); + cmd_mmrbc = + (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> + PCIX_COMMAND_MMRBC_SHIFT; + stat_mmrbc = + (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> + PCIX_STATUS_HI_MMRBC_SHIFT; + if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) + stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; + if (cmd_mmrbc > stat_mmrbc) { + pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; + pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; + pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, + pcix_cmd_word); + } + } + + /* Call a subroutine to configure the link and setup flow control. */ + ret_val = e1000_setup_link(nic); + + /* Set the transmit descriptor write-back policy */ + if (hw->mac_type > e1000_82544) { + ctrl = E1000_READ_REG(hw, TXDCTL); + ctrl = + (ctrl & ~E1000_TXDCTL_WTHRESH) | + E1000_TXDCTL_FULL_TX_DESC_WB; + E1000_WRITE_REG(hw, TXDCTL, ctrl); + } +#if 0 + /* Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs(hw); +#endif + + return ret_val; +} + +/****************************************************************************** + * Configures flow control and link settings. + * + * hw - Struct containing variables accessed by shared code + * + * Determines which flow control settings to use. Calls the apropriate media- + * specific link configuration function. Configures the flow control settings. + * Assuming the adapter has a valid link partner, a valid link should be + * established. Assumes the hardware has previously been reset and the + * transmitter and receiver are not enabled. + *****************************************************************************/ +static int +e1000_setup_link(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t ctrl_ext; + int32_t ret_val; + uint16_t eeprom_data; + + DEBUGFUNC(); + +#ifndef CONFIG_AP1000 + /* Read and store word 0x0F of the EEPROM. This word contains bits + * that determine the hardware's default PAUSE (flow control) mode, + * a bit that determines whether the HW defaults to enabling or + * disabling auto-negotiation, and the direction of the + * SW defined pins. If there is no SW over-ride of the flow + * control setting, then the variable hw->fc will + * be initialized based on a value in the EEPROM. + */ + if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) { + DEBUGOUT("EEPROM Read Error\n"); + return -E1000_ERR_EEPROM; + } +#else + /* we have to hardcode the proper value for our hardware. */ + /* this value is for the 82540EM pci card used for prototyping, and it works. */ + eeprom_data = 0xb220; +#endif + + if (hw->fc == e1000_fc_default) { + if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) + hw->fc = e1000_fc_none; + else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == + EEPROM_WORD0F_ASM_DIR) + hw->fc = e1000_fc_tx_pause; + else + hw->fc = e1000_fc_full; + } + + /* We want to save off the original Flow Control configuration just + * in case we get disconnected and then reconnected into a different + * hub or switch with different Flow Control capabilities. + */ + if (hw->mac_type == e1000_82542_rev2_0) + hw->fc &= (~e1000_fc_tx_pause); + + if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) + hw->fc &= (~e1000_fc_rx_pause); + + hw->original_fc = hw->fc; + + DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); + + /* Take the 4 bits from EEPROM word 0x0F that determine the initial + * polarity value for the SW controlled pins, and setup the + * Extended Device Control reg with that info. + * This is needed because one of the SW controlled pins is used for + * signal detection. So this should be done before e1000_setup_pcs_link() + * or e1000_phy_setup() is called. + */ + if (hw->mac_type == e1000_82543) { + ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << + SWDPIO__EXT_SHIFT); + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + } + + /* Call the necessary subroutine to configure the link. */ + ret_val = (hw->media_type == e1000_media_type_fiber) ? + e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); + if (ret_val < 0) { + return ret_val; + } + + /* Initialize the flow control address, type, and PAUSE timer + * registers to their default values. This is done even if flow + * control is disabled, because it does not hurt anything to + * initialize these registers. + */ + DEBUGOUT + ("Initializing the Flow Control address, type and timer regs\n"); + + E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); + E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); + E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); + E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); + + /* Set the flow control receive threshold registers. Normally, + * these registers will be set to a default threshold that may be + * adjusted later by the driver's runtime code. However, if the + * ability to transmit pause frames in not enabled, then these + * registers will be set to 0. + */ + if (!(hw->fc & e1000_fc_tx_pause)) { + E1000_WRITE_REG(hw, FCRTL, 0); + E1000_WRITE_REG(hw, FCRTH, 0); + } else { + /* We need to set up the Receive Threshold high and low water marks + * as well as (optionally) enabling the transmission of XON frames. + */ + if (hw->fc_send_xon) { + E1000_WRITE_REG(hw, FCRTL, + (hw->fc_low_water | E1000_FCRTL_XONE)); + E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); + } else { + E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); + E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); + } + } + return ret_val; +} + +/****************************************************************************** + * Sets up link for a fiber based adapter + * + * hw - Struct containing variables accessed by shared code + * + * Manipulates Physical Coding Sublayer functions in order to configure + * link. Assumes the hardware has been previously reset and the transmitter + * and receiver are not enabled. + *****************************************************************************/ +static int +e1000_setup_fiber_link(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t ctrl; + uint32_t status; + uint32_t txcw = 0; + uint32_t i; + uint32_t signal; + int32_t ret_val; + + DEBUGFUNC(); + /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be + * set when the optics detect a signal. On older adapters, it will be + * cleared when there is a signal + */ + ctrl = E1000_READ_REG(hw, CTRL); + if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) + signal = E1000_CTRL_SWDPIN1; + else + signal = 0; + + printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, + ctrl); + /* Take the link out of reset */ + ctrl &= ~(E1000_CTRL_LRST); + + e1000_config_collision_dist(hw); + + /* Check for a software override of the flow control settings, and setup + * the device accordingly. If auto-negotiation is enabled, then software + * will have to set the "PAUSE" bits to the correct value in the Tranmsit + * Config Word Register (TXCW) and re-start auto-negotiation. However, if + * auto-negotiation is disabled, then software will have to manually + * configure the two flow control enable bits in the CTRL register. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames, but + * not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames but we do + * not support receiving pause frames). + * 3: Both Rx and TX flow control (symmetric) are enabled. + */ + switch (hw->fc) { + case e1000_fc_none: + /* Flow control is completely disabled by a software over-ride. */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); + break; + case e1000_fc_rx_pause: + /* RX Flow control is enabled and TX Flow control is disabled by a + * software over-ride. Since there really isn't a way to advertise + * that we are capable of RX Pause ONLY, we will advertise that we + * support both symmetric and asymmetric RX PAUSE. Later, we will + * disable the adapter's ability to send PAUSE frames. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); + break; + case e1000_fc_tx_pause: + /* TX Flow control is enabled, and RX Flow control is disabled, by a + * software over-ride. + */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); + break; + case e1000_fc_full: + /* Flow control (both RX and TX) is enabled by a software over-ride. */ + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + break; + } + + /* Since auto-negotiation is enabled, take the link out of reset (the link + * will be in reset, because we previously reset the chip). This will + * restart auto-negotiation. If auto-neogtiation is successful then the + * link-up status bit will be set and the flow control enable bits (RFCE + * and TFCE) will be set according to their negotiated value. + */ + DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); + + E1000_WRITE_REG(hw, TXCW, txcw); + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + hw->txcw = txcw; + mdelay(1); + + /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" + * indication in the Device Status Register. Time-out if a link isn't + * seen in 500 milliseconds seconds (Auto-negotiation should complete in + * less than 500 milliseconds even if the other end is doing it in SW). + */ + if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { + DEBUGOUT("Looking for Link\n"); + for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { + mdelay(10); + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_LU) + break; + } + if (i == (LINK_UP_TIMEOUT / 10)) { + /* AutoNeg failed to achieve a link, so we'll call + * e1000_check_for_link. This routine will force the link up if we + * detect a signal. This will allow us to communicate with + * non-autonegotiating link partners. + */ + DEBUGOUT("Never got a valid link from auto-neg!!!\n"); + hw->autoneg_failed = 1; + ret_val = e1000_check_for_link(nic); + if (ret_val < 0) { + DEBUGOUT("Error while checking for link\n"); + return ret_val; + } + hw->autoneg_failed = 0; + } else { + hw->autoneg_failed = 0; + DEBUGOUT("Valid Link Found\n"); + } + } else { + DEBUGOUT("No Signal Detected\n"); + return -E1000_ERR_NOLINK; + } + return 0; +} + +/****************************************************************************** +* Detects which PHY is present and the speed and duplex +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int +e1000_setup_copper_link(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t ctrl; + int32_t ret_val; + uint16_t i; + uint16_t phy_data; + + DEBUGFUNC(); + + ctrl = E1000_READ_REG(hw, CTRL); + /* With 82543, we need to force speed and duplex on the MAC equal to what + * the PHY speed and duplex configuration is. In addition, we need to + * perform a hardware reset on the PHY to take it out of reset. + */ + if (hw->mac_type > e1000_82543) { + ctrl |= E1000_CTRL_SLU; + ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + E1000_WRITE_REG(hw, CTRL, ctrl); + } else { + ctrl |= + (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); + E1000_WRITE_REG(hw, CTRL, ctrl); + e1000_phy_hw_reset(hw); + } + + /* Make sure we have a valid PHY */ + ret_val = e1000_detect_gig_phy(hw); + if (ret_val < 0) { + DEBUGOUT("Error, did not detect valid phy.\n"); + return ret_val; + } + DEBUGOUT("Phy ID = %x \n", hw->phy_id); + + /* Enable CRS on TX. This must be set for half-duplex operation. */ + if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; + +#if 0 + /* Options: + * MDI/MDI-X = 0 (default) + * 0 - Auto for all speeds + * 1 - MDI mode + * 2 - MDI-X mode + * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) + */ + phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; + switch (hw->mdix) { + case 1: + phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; + break; + case 2: + phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; + break; + case 3: + phy_data |= M88E1000_PSCR_AUTO_X_1000T; + break; + case 0: + default: + phy_data |= M88E1000_PSCR_AUTO_X_MODE; + break; + } +#else + phy_data |= M88E1000_PSCR_AUTO_X_MODE; +#endif + +#if 0 + /* Options: + * disable_polarity_correction = 0 (default) + * Automatic Correction for Reversed Cable Polarity + * 0 - Disabled + * 1 - Enabled + */ + phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; + if (hw->disable_polarity_correction == 1) + phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; +#else + phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; +#endif + if (e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } + + /* Force TX_CLK in the Extended PHY Specific Control Register + * to 25MHz clock. + */ + if (e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + phy_data |= M88E1000_EPSCR_TX_CLK_25; + /* Configure Master and Slave downshift values */ + phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | + M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); + phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | + M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); + if (e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } + + /* SW Reset the PHY so all changes take effect */ + ret_val = e1000_phy_reset(hw); + if (ret_val < 0) { + DEBUGOUT("Error Resetting the PHY\n"); + return ret_val; + } + + /* Options: + * autoneg = 1 (default) + * PHY will advertise value(s) parsed from + * autoneg_advertised and fc + * autoneg = 0 + * PHY will be set to 10H, 10F, 100H, or 100F + * depending on value parsed from forced_speed_duplex. + */ + + /* Is autoneg enabled? This is enabled by default or by software override. + * If so, call e1000_phy_setup_autoneg routine to parse the + * autoneg_advertised and fc options. If autoneg is NOT enabled, then the + * user should have provided a speed/duplex override. If so, then call + * e1000_phy_force_speed_duplex to parse and set this up. + */ + /* Perform some bounds checking on the hw->autoneg_advertised + * parameter. If this variable is zero, then set it to the default. + */ + hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; + + /* If autoneg_advertised is zero, we assume it was not defaulted + * by the calling code so we set to advertise full capability. + */ + if (hw->autoneg_advertised == 0) + hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; + + DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); + ret_val = e1000_phy_setup_autoneg(hw); + if (ret_val < 0) { + DEBUGOUT("Error Setting up Auto-Negotiation\n"); + return ret_val; + } + DEBUGOUT("Restarting Auto-Neg\n"); + + /* Restart auto-negotiation by setting the Auto Neg Enable bit and + * the Auto Neg Restart bit in the PHY control register. + */ + if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); + if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } +#if 0 + /* Does the user want to wait for Auto-Neg to complete here, or + * check at a later time (for example, callback routine). + */ + if (hw->wait_autoneg_complete) { + ret_val = e1000_wait_autoneg(hw); + if (ret_val < 0) { + DEBUGOUT + ("Error while waiting for autoneg to complete\n"); + return ret_val; + } + } +#else + /* If we do not wait for autonegtation to complete I + * do not see a valid link status. + */ + ret_val = e1000_wait_autoneg(hw); + if (ret_val < 0) { + DEBUGOUT("Error while waiting for autoneg to complete\n"); + return ret_val; + } +#endif + + /* Check link status. Wait up to 100 microseconds for link to become + * valid. + */ + for (i = 0; i < 10; i++) { + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (phy_data & MII_SR_LINK_STATUS) { + /* We have link, so we need to finish the config process: + * 1) Set up the MAC to the current PHY speed/duplex + * if we are on 82543. If we + * are on newer silicon, we only need to configure + * collision distance in the Transmit Control Register. + * 2) Set up flow control on the MAC to that established with + * the link partner. + */ + if (hw->mac_type >= e1000_82544) { + e1000_config_collision_dist(hw); + } else { + ret_val = e1000_config_mac_to_phy(hw); + if (ret_val < 0) { + DEBUGOUT + ("Error configuring MAC to PHY settings\n"); + return ret_val; + } + } + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val < 0) { + DEBUGOUT("Error Configuring Flow Control\n"); + return ret_val; + } + DEBUGOUT("Valid link established!!!\n"); + return 0; + } + udelay(10); + } + + DEBUGOUT("Unable to establish link!!!\n"); + return -E1000_ERR_NOLINK; +} + +/****************************************************************************** +* Configures PHY autoneg and flow control advertisement settings +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int +e1000_phy_setup_autoneg(struct e1000_hw *hw) +{ + uint16_t mii_autoneg_adv_reg; + uint16_t mii_1000t_ctrl_reg; + + DEBUGFUNC(); + + /* Read the MII Auto-Neg Advertisement Register (Address 4). */ + if (e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + /* Read the MII 1000Base-T Control Register (Address 9). */ + if (e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + /* Need to parse both autoneg_advertised and fc and set up + * the appropriate PHY registers. First we will parse for + * autoneg_advertised software override. Since we can advertise + * a plethora of combinations, we need to check each bit + * individually. + */ + + /* First we clear all the 10/100 mb speed bits in the Auto-Neg + * Advertisement Register (Address 4) and the 1000 mb speed bits in + * the 1000Base-T Control Register (Address 9). + */ + mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; + mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; + + DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); + + /* Do we want to advertise 10 Mb Half Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_10_HALF) { + DEBUGOUT("Advertise 10mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; + } + + /* Do we want to advertise 10 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_10_FULL) { + DEBUGOUT("Advertise 10mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; + } + + /* Do we want to advertise 100 Mb Half Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_100_HALF) { + DEBUGOUT("Advertise 100mb Half duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; + } + + /* Do we want to advertise 100 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_100_FULL) { + DEBUGOUT("Advertise 100mb Full duplex\n"); + mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; + } + + /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ + if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { + DEBUGOUT + ("Advertise 1000mb Half duplex requested, request denied!\n"); + } + + /* Do we want to advertise 1000 Mb Full Duplex? */ + if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { + DEBUGOUT("Advertise 1000mb Full duplex\n"); + mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; + } + + /* Check for a software override of the flow control settings, and + * setup the PHY advertisement registers accordingly. If + * auto-negotiation is enabled, then software will have to set the + * "PAUSE" bits to the correct value in the Auto-Negotiation + * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause frames + * but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * but we do not support receiving pause frames). + * 3: Both Rx and TX flow control (symmetric) are enabled. + * other: No software override. The flow control configuration + * in the EEPROM is used. + */ + switch (hw->fc) { + case e1000_fc_none: /* 0 */ + /* Flow control (RX & TX) is completely disabled by a + * software over-ride. + */ + mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case e1000_fc_rx_pause: /* 1 */ + /* RX Flow control is enabled, and TX Flow control is + * disabled, by a software over-ride. + */ + /* Since there really isn't a way to advertise that we are + * capable of RX Pause ONLY, we will advertise that we + * support both symmetric and asymmetric RX PAUSE. Later + * (in e1000_config_fc_after_link_up) we will disable the + *hw's ability to send PAUSE frames. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + case e1000_fc_tx_pause: /* 2 */ + /* TX Flow control is enabled, and RX Flow control is + * disabled, by a software over-ride. + */ + mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; + mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; + break; + case e1000_fc_full: /* 3 */ + /* Flow control (both RX and TX) is enabled by a software + * over-ride. + */ + mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + } + + if (e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } + + DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); + + if (e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } + return 0; +} + +/****************************************************************************** +* Sets the collision distance in the Transmit Control register +* +* hw - Struct containing variables accessed by shared code +* +* Link should have been established previously. Reads the speed and duplex +* information from the Device Status register. +******************************************************************************/ +static void +e1000_config_collision_dist(struct e1000_hw *hw) +{ + uint32_t tctl; + + tctl = E1000_READ_REG(hw, TCTL); + + tctl &= ~E1000_TCTL_COLD; + tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; + + E1000_WRITE_REG(hw, TCTL, tctl); + E1000_WRITE_FLUSH(hw); +} + +/****************************************************************************** +* Sets MAC speed and duplex settings to reflect the those in the PHY +* +* hw - Struct containing variables accessed by shared code +* mii_reg - data to write to the MII control register +* +* The contents of the PHY register containing the needed information need to +* be passed in. +******************************************************************************/ +static int +e1000_config_mac_to_phy(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint16_t phy_data; + + DEBUGFUNC(); + + /* Read the Device Control Register and set the bits to Force Speed + * and Duplex. + */ + ctrl = E1000_READ_REG(hw, CTRL); + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); + ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); + + /* Set up duplex in the Device Control and Transmit Control + * registers depending on negotiated values. + */ + if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (phy_data & M88E1000_PSSR_DPLX) + ctrl |= E1000_CTRL_FD; + else + ctrl &= ~E1000_CTRL_FD; + + e1000_config_collision_dist(hw); + + /* Set up speed in the Device Control register depending on + * negotiated values. + */ + if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) + ctrl |= E1000_CTRL_SPD_1000; + else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) + ctrl |= E1000_CTRL_SPD_100; + /* Write the configured values back to the Device Control Reg. */ + E1000_WRITE_REG(hw, CTRL, ctrl); + return 0; +} + +/****************************************************************************** + * Forces the MAC's flow control settings. + * + * hw - Struct containing variables accessed by shared code + * + * Sets the TFCE and RFCE bits in the device control register to reflect + * the adapter settings. TFCE and RFCE need to be explicitly set by + * software when a Copper PHY is used because autonegotiation is managed + * by the PHY rather than the MAC. Software must also configure these + * bits when link is forced on a fiber connection. + *****************************************************************************/ +static int +e1000_force_mac_fc(struct e1000_hw *hw) +{ + uint32_t ctrl; + + DEBUGFUNC(); + + /* Get the current configuration of the Device Control Register */ + ctrl = E1000_READ_REG(hw, CTRL); + + /* Because we didn't get link via the internal auto-negotiation + * mechanism (we either forced link or we got link via PHY + * auto-neg), we have to manually enable/disable transmit an + * receive flow control. + * + * The "Case" statement below enables/disable flow control + * according to the "hw->fc" parameter. + * + * The possible values of the "fc" parameter are: + * 0: Flow control is completely disabled + * 1: Rx flow control is enabled (we can receive pause + * frames but not send pause frames). + * 2: Tx flow control is enabled (we can send pause frames + * frames but we do not receive pause frames). + * 3: Both Rx and TX flow control (symmetric) is enabled. + * other: No other values should be possible at this point. + */ + + switch (hw->fc) { + case e1000_fc_none: + ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); + break; + case e1000_fc_rx_pause: + ctrl &= (~E1000_CTRL_TFCE); + ctrl |= E1000_CTRL_RFCE; + break; + case e1000_fc_tx_pause: + ctrl &= (~E1000_CTRL_RFCE); + ctrl |= E1000_CTRL_TFCE; + break; + case e1000_fc_full: + ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); + break; + default: + DEBUGOUT("Flow control param set incorrectly\n"); + return -E1000_ERR_CONFIG; + } + + /* Disable TX Flow Control for 82542 (rev 2.0) */ + if (hw->mac_type == e1000_82542_rev2_0) + ctrl &= (~E1000_CTRL_TFCE); + + E1000_WRITE_REG(hw, CTRL, ctrl); + return 0; +} + +/****************************************************************************** + * Configures flow control settings after link is established + * + * hw - Struct containing variables accessed by shared code + * + * Should be called immediately after a valid link has been established. + * Forces MAC flow control settings if link was forced. When in MII/GMII mode + * and autonegotiation is enabled, the MAC flow control settings will be set + * based on the flow control negotiated by the PHY. In TBI mode, the TFCE + * and RFCE bits will be automaticaly set to the negotiated flow control mode. + *****************************************************************************/ +static int +e1000_config_fc_after_link_up(struct e1000_hw *hw) +{ + int32_t ret_val; + uint16_t mii_status_reg; + uint16_t mii_nway_adv_reg; + uint16_t mii_nway_lp_ability_reg; + uint16_t speed; + uint16_t duplex; + + DEBUGFUNC(); + + /* Check for the case where we have fiber media and auto-neg failed + * so we had to force link. In this case, we need to force the + * configuration of the MAC to match the "fc" parameter. + */ + if ((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) { + ret_val = e1000_force_mac_fc(hw); + if (ret_val < 0) { + DEBUGOUT("Error forcing flow control settings\n"); + return ret_val; + } + } + + /* Check for the case where we have copper media and auto-neg is + * enabled. In this case, we need to check and see if Auto-Neg + * has completed, and if so, how the PHY and link partner has + * flow control configured. + */ + if (hw->media_type == e1000_media_type_copper) { + /* Read the MII Status Register and check to see if AutoNeg + * has completed. We read this twice because this reg has + * some "sticky" (latched) bits. + */ + if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { + DEBUGOUT("PHY Read Error \n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { + DEBUGOUT("PHY Read Error \n"); + return -E1000_ERR_PHY; + } + + if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { + /* The AutoNeg process has completed, so we now need to + * read both the Auto Negotiation Advertisement Register + * (Address 4) and the Auto_Negotiation Base Page Ability + * Register (Address 5) to determine how flow control was + * negotiated. + */ + if (e1000_read_phy_reg + (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg + (hw, PHY_LP_ABILITY, + &mii_nway_lp_ability_reg) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + /* Two bits in the Auto Negotiation Advertisement Register + * (Address 4) and two bits in the Auto Negotiation Base + * Page Ability Register (Address 5) determine flow control + * for both the PHY and the link partner. The following + * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, + * 1999, describes these PAUSE resolution bits and how flow + * control is determined based upon these settings. + * NOTE: DC = Don't Care + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution + *-------|---------|-------|---------|-------------------- + * 0 | 0 | DC | DC | e1000_fc_none + * 0 | 1 | 0 | DC | e1000_fc_none + * 0 | 1 | 1 | 0 | e1000_fc_none + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * 1 | 0 | 0 | DC | e1000_fc_none + * 1 | DC | 1 | DC | e1000_fc_full + * 1 | 1 | 0 | 0 | e1000_fc_none + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + */ + /* Are both PAUSE bits set to 1? If so, this implies + * Symmetric Flow Control is enabled at both ends. The + * ASM_DIR bits are irrelevant per the spec. + * + * For Symmetric Flow Control: + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | DC | 1 | DC | e1000_fc_full + * + */ + if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { + /* Now we need to check if the user selected RX ONLY + * of pause frames. In this case, we had to advertise + * FULL flow control because we could not advertise RX + * ONLY. Hence, we must now check to see if we need to + * turn OFF the TRANSMISSION of PAUSE frames. + */ + if (hw->original_fc == e1000_fc_full) { + hw->fc = e1000_fc_full; + DEBUGOUT("Flow Control = FULL.\r\n"); + } else { + hw->fc = e1000_fc_rx_pause; + DEBUGOUT + ("Flow Control = RX PAUSE frames only.\r\n"); + } + } + /* For receiving PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 0 | 1 | 1 | 1 | e1000_fc_tx_pause + * + */ + else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && + (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) + { + hw->fc = e1000_fc_tx_pause; + DEBUGOUT + ("Flow Control = TX PAUSE frames only.\r\n"); + } + /* For transmitting PAUSE frames ONLY. + * + * LOCAL DEVICE | LINK PARTNER + * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result + *-------|---------|-------|---------|-------------------- + * 1 | 1 | 0 | 1 | e1000_fc_rx_pause + * + */ + else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && + (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && + !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && + (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) + { + hw->fc = e1000_fc_rx_pause; + DEBUGOUT + ("Flow Control = RX PAUSE frames only.\r\n"); + } + /* Per the IEEE spec, at this point flow control should be + * disabled. However, we want to consider that we could + * be connected to a legacy switch that doesn't advertise + * desired flow control, but can be forced on the link + * partner. So if we advertised no flow control, that is + * what we will resolve to. If we advertised some kind of + * receive capability (Rx Pause Only or Full Flow Control) + * and the link partner advertised none, we will configure + * ourselves to enable Rx Flow Control only. We can do + * this safely for two reasons: If the link partner really + * didn't want flow control enabled, and we enable Rx, no + * harm done since we won't be receiving any PAUSE frames + * anyway. If the intent on the link partner was to have + * flow control enabled, then by us enabling RX only, we + * can at least receive pause frames and process them. + * This is a good idea because in most cases, since we are + * predominantly a server NIC, more times than not we will + * be asked to delay transmission of packets than asking + * our link partner to pause transmission of frames. + */ + else if (hw->original_fc == e1000_fc_none || + hw->original_fc == e1000_fc_tx_pause) { + hw->fc = e1000_fc_none; + DEBUGOUT("Flow Control = NONE.\r\n"); + } else { + hw->fc = e1000_fc_rx_pause; + DEBUGOUT + ("Flow Control = RX PAUSE frames only.\r\n"); + } + + /* Now we need to do one last check... If we auto- + * negotiated to HALF DUPLEX, flow control should not be + * enabled per IEEE 802.3 spec. + */ + e1000_get_speed_and_duplex(hw, &speed, &duplex); + + if (duplex == HALF_DUPLEX) + hw->fc = e1000_fc_none; + + /* Now we call a subroutine to actually force the MAC + * controller to use the correct flow control settings. + */ + ret_val = e1000_force_mac_fc(hw); + if (ret_val < 0) { + DEBUGOUT + ("Error forcing flow control settings\n"); + return ret_val; + } + } else { + DEBUGOUT + ("Copper PHY and Auto Neg has not completed.\r\n"); + } + } + return 0; +} + +/****************************************************************************** + * Checks to see if the link status of the hardware has changed. + * + * hw - Struct containing variables accessed by shared code + * + * Called by any function that needs to check the link status of the adapter. + *****************************************************************************/ +static int +e1000_check_for_link(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + uint32_t rxcw; + uint32_t ctrl; + uint32_t status; + uint32_t rctl; + uint32_t signal; + int32_t ret_val; + uint16_t phy_data; + uint16_t lp_capability; + + DEBUGFUNC(); + + /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be + * set when the optics detect a signal. On older adapters, it will be + * cleared when there is a signal + */ + ctrl = E1000_READ_REG(hw, CTRL); + if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) + signal = E1000_CTRL_SWDPIN1; + else + signal = 0; + + status = E1000_READ_REG(hw, STATUS); + rxcw = E1000_READ_REG(hw, RXCW); + DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); + + /* If we have a copper PHY then we only want to go out to the PHY + * registers to see if Auto-Neg has completed and/or if our link + * status has changed. The get_link_status flag will be set if we + * receive a Link Status Change interrupt or we have Rx Sequence + * Errors. + */ + if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { + /* First we want to see if the MII Status Register reports + * link. If so, then we want to get the current speed/duplex + * of the PHY. + * Read the register twice since the link bit is sticky. + */ + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + + if (phy_data & MII_SR_LINK_STATUS) { + hw->get_link_status = FALSE; + } else { + /* No link detected */ + return -E1000_ERR_NOLINK; + } + + /* We have a M88E1000 PHY and Auto-Neg is enabled. If we + * have Si on board that is 82544 or newer, Auto + * Speed Detection takes care of MAC speed/duplex + * configuration. So we only need to configure Collision + * Distance in the MAC. Otherwise, we need to force + * speed/duplex on the MAC to the current PHY speed/duplex + * settings. + */ + if (hw->mac_type >= e1000_82544) + e1000_config_collision_dist(hw); + else { + ret_val = e1000_config_mac_to_phy(hw); + if (ret_val < 0) { + DEBUGOUT + ("Error configuring MAC to PHY settings\n"); + return ret_val; + } + } + + /* Configure Flow Control now that Auto-Neg has completed. First, we + * need to restore the desired flow control settings because we may + * have had to re-autoneg with a different link partner. + */ + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val < 0) { + DEBUGOUT("Error configuring flow control\n"); + return ret_val; + } + + /* At this point we know that we are on copper and we have + * auto-negotiated link. These are conditions for checking the link + * parter capability register. We use the link partner capability to + * determine if TBI Compatibility needs to be turned on or off. If + * the link partner advertises any speed in addition to Gigabit, then + * we assume that they are GMII-based, and TBI compatibility is not + * needed. If no other speeds are advertised, we assume the link + * partner is TBI-based, and we turn on TBI Compatibility. + */ + if (hw->tbi_compatibility_en) { + if (e1000_read_phy_reg + (hw, PHY_LP_ABILITY, &lp_capability) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (lp_capability & (NWAY_LPAR_10T_HD_CAPS | + NWAY_LPAR_10T_FD_CAPS | + NWAY_LPAR_100TX_HD_CAPS | + NWAY_LPAR_100TX_FD_CAPS | + NWAY_LPAR_100T4_CAPS)) { + /* If our link partner advertises anything in addition to + * gigabit, we do not need to enable TBI compatibility. + */ + if (hw->tbi_compatibility_on) { + /* If we previously were in the mode, turn it off. */ + rctl = E1000_READ_REG(hw, RCTL); + rctl &= ~E1000_RCTL_SBP; + E1000_WRITE_REG(hw, RCTL, rctl); + hw->tbi_compatibility_on = FALSE; + } + } else { + /* If TBI compatibility is was previously off, turn it on. For + * compatibility with a TBI link partner, we will store bad + * packets. Some frames have an additional byte on the end and + * will look like CRC errors to to the hardware. + */ + if (!hw->tbi_compatibility_on) { + hw->tbi_compatibility_on = TRUE; + rctl = E1000_READ_REG(hw, RCTL); + rctl |= E1000_RCTL_SBP; + E1000_WRITE_REG(hw, RCTL, rctl); + } + } + } + } + /* If we don't have link (auto-negotiation failed or link partner cannot + * auto-negotiate), the cable is plugged in (we have signal), and our + * link partner is not trying to auto-negotiate with us (we are receiving + * idles or data), we need to force link up. We also need to give + * auto-negotiation time to complete, in case the cable was just plugged + * in. The autoneg_failed flag does this. + */ + else if ((hw->media_type == e1000_media_type_fiber) && + (!(status & E1000_STATUS_LU)) && + ((ctrl & E1000_CTRL_SWDPIN1) == signal) && + (!(rxcw & E1000_RXCW_C))) { + if (hw->autoneg_failed == 0) { + hw->autoneg_failed = 1; + return 0; + } + DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n"); + + /* Disable auto-negotiation in the TXCW register */ + E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); + + /* Force link-up and also force full-duplex. */ + ctrl = E1000_READ_REG(hw, CTRL); + ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); + E1000_WRITE_REG(hw, CTRL, ctrl); + + /* Configure Flow Control after forcing link up. */ + ret_val = e1000_config_fc_after_link_up(hw); + if (ret_val < 0) { + DEBUGOUT("Error configuring flow control\n"); + return ret_val; + } + } + /* If we are forcing link and we are receiving /C/ ordered sets, re-enable + * auto-negotiation in the TXCW register and disable forced link in the + * Device Control register in an attempt to auto-negotiate with our link + * partner. + */ + else if ((hw->media_type == e1000_media_type_fiber) && + (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { + DEBUGOUT + ("RXing /C/, enable AutoNeg and stop forcing link.\r\n"); + E1000_WRITE_REG(hw, TXCW, hw->txcw); + E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); + } + return 0; +} + +/****************************************************************************** + * Detects the current speed and duplex settings of the hardware. + * + * hw - Struct containing variables accessed by shared code + * speed - Speed of the connection + * duplex - Duplex setting of the connection + *****************************************************************************/ +static void +e1000_get_speed_and_duplex(struct e1000_hw *hw, + uint16_t * speed, uint16_t * duplex) +{ + uint32_t status; + + DEBUGFUNC(); + + if (hw->mac_type >= e1000_82543) { + status = E1000_READ_REG(hw, STATUS); + if (status & E1000_STATUS_SPEED_1000) { + *speed = SPEED_1000; + DEBUGOUT("1000 Mbs, "); + } else if (status & E1000_STATUS_SPEED_100) { + *speed = SPEED_100; + DEBUGOUT("100 Mbs, "); + } else { + *speed = SPEED_10; + DEBUGOUT("10 Mbs, "); + } + + if (status & E1000_STATUS_FD) { + *duplex = FULL_DUPLEX; + DEBUGOUT("Full Duplex\r\n"); + } else { + *duplex = HALF_DUPLEX; + DEBUGOUT(" Half Duplex\r\n"); + } + } else { + DEBUGOUT("1000 Mbs, Full Duplex\r\n"); + *speed = SPEED_1000; + *duplex = FULL_DUPLEX; + } +} + +/****************************************************************************** +* Blocks until autoneg completes or times out (~4.5 seconds) +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int +e1000_wait_autoneg(struct e1000_hw *hw) +{ + uint16_t i; + uint16_t phy_data; + + DEBUGFUNC(); + DEBUGOUT("Waiting for Auto-Neg to complete.\n"); + + /* We will wait for autoneg to complete or 4.5 seconds to expire. */ + for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { + /* Read the MII Status Register and wait for Auto-Neg + * Complete bit to be set. + */ + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + if (phy_data & MII_SR_AUTONEG_COMPLETE) { + DEBUGOUT("Auto-Neg complete.\n"); + return 0; + } + mdelay(100); + } + DEBUGOUT("Auto-Neg timedout.\n"); + return -E1000_ERR_TIMEOUT; +} + +/****************************************************************************** +* Raises the Management Data Clock +* +* hw - Struct containing variables accessed by shared code +* ctrl - Device control register's current value +******************************************************************************/ +static void +e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) +{ + /* Raise the clock input to the Management Data Clock (by setting the MDC + * bit), and then delay 2 microseconds. + */ + E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); + E1000_WRITE_FLUSH(hw); + udelay(2); +} + +/****************************************************************************** +* Lowers the Management Data Clock +* +* hw - Struct containing variables accessed by shared code +* ctrl - Device control register's current value +******************************************************************************/ +static void +e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) +{ + /* Lower the clock input to the Management Data Clock (by clearing the MDC + * bit), and then delay 2 microseconds. + */ + E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); + E1000_WRITE_FLUSH(hw); + udelay(2); +} + +/****************************************************************************** +* Shifts data bits out to the PHY +* +* hw - Struct containing variables accessed by shared code +* data - Data to send out to the PHY +* count - Number of bits to shift out +* +* Bits are shifted out in MSB to LSB order. +******************************************************************************/ +static void +e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) +{ + uint32_t ctrl; + uint32_t mask; + + /* We need to shift "count" number of bits out to the PHY. So, the value + * in the "data" parameter will be shifted out to the PHY one bit at a + * time. In order to do this, "data" must be broken down into bits. + */ + mask = 0x01; + mask <<= (count - 1); + + ctrl = E1000_READ_REG(hw, CTRL); + + /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ + ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); + + while (mask) { + /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and + * then raising and lowering the Management Data Clock. A "0" is + * shifted out to the PHY by setting the MDIO bit to "0" and then + * raising and lowering the clock. + */ + if (data & mask) + ctrl |= E1000_CTRL_MDIO; + else + ctrl &= ~E1000_CTRL_MDIO; + + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + udelay(2); + + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + mask = mask >> 1; + } +} + +/****************************************************************************** +* Shifts data bits in from the PHY +* +* hw - Struct containing variables accessed by shared code +* +* Bits are shifted in in MSB to LSB order. +******************************************************************************/ +static uint16_t +e1000_shift_in_mdi_bits(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint16_t data = 0; + uint8_t i; + + /* In order to read a register from the PHY, we need to shift in a total + * of 18 bits from the PHY. The first two bit (turnaround) times are used + * to avoid contention on the MDIO pin when a read operation is performed. + * These two bits are ignored by us and thrown away. Bits are "shifted in" + * by raising the input to the Management Data Clock (setting the MDC bit), + * and then reading the value of the MDIO bit. + */ + ctrl = E1000_READ_REG(hw, CTRL); + + /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ + ctrl &= ~E1000_CTRL_MDIO_DIR; + ctrl &= ~E1000_CTRL_MDIO; + + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + + /* Raise and Lower the clock before reading in the data. This accounts for + * the turnaround bits. The first clock occurred when we clocked out the + * last bit of the Register Address. + */ + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + for (data = 0, i = 0; i < 16; i++) { + data = data << 1; + e1000_raise_mdi_clk(hw, &ctrl); + ctrl = E1000_READ_REG(hw, CTRL); + /* Check to see if we shifted in a "1". */ + if (ctrl & E1000_CTRL_MDIO) + data |= 1; + e1000_lower_mdi_clk(hw, &ctrl); + } + + e1000_raise_mdi_clk(hw, &ctrl); + e1000_lower_mdi_clk(hw, &ctrl); + + return data; +} + +/***************************************************************************** +* Reads the value from a PHY register +* +* hw - Struct containing variables accessed by shared code +* reg_addr - address of the PHY register to read +******************************************************************************/ +static int +e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) +{ + uint32_t i; + uint32_t mdic = 0; + const uint32_t phy_addr = 1; + + if (reg_addr > MAX_PHY_REG_ADDRESS) { + DEBUGOUT("PHY Address %d is out of range\n", reg_addr); + return -E1000_ERR_PARAM; + } + + if (hw->mac_type > e1000_82543) { + /* Set up Op-code, Phy Address, and register address in the MDI + * Control register. The MAC will take care of interfacing with the + * PHY to retrieve the desired data. + */ + mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | + (phy_addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_READ)); + + E1000_WRITE_REG(hw, MDIC, mdic); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < 64; i++) { + udelay(10); + mdic = E1000_READ_REG(hw, MDIC); + if (mdic & E1000_MDIC_READY) + break; + } + if (!(mdic & E1000_MDIC_READY)) { + DEBUGOUT("MDI Read did not complete\n"); + return -E1000_ERR_PHY; + } + if (mdic & E1000_MDIC_ERROR) { + DEBUGOUT("MDI Error\n"); + return -E1000_ERR_PHY; + } + *phy_data = (uint16_t) mdic; + } else { + /* We must first send a preamble through the MDIO pin to signal the + * beginning of an MII instruction. This is done by sending 32 + * consecutive "1" bits. + */ + e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); + + /* Now combine the next few fields that are required for a read + * operation. We use this method instead of calling the + * e1000_shift_out_mdi_bits routine five different times. The format of + * a MII read instruction consists of a shift out of 14 bits and is + * defined as follows: + * + * followed by a shift in of 18 bits. This first two bits shifted in + * are TurnAround bits used to avoid contention on the MDIO pin when a + * READ operation is performed. These two bits are thrown away + * followed by a shift in of 16 bits which contains the desired data. + */ + mdic = ((reg_addr) | (phy_addr << 5) | + (PHY_OP_READ << 10) | (PHY_SOF << 12)); + + e1000_shift_out_mdi_bits(hw, mdic, 14); + + /* Now that we've shifted out the read command to the MII, we need to + * "shift in" the 16-bit value (18 total bits) of the requested PHY + * register address. + */ + *phy_data = e1000_shift_in_mdi_bits(hw); + } + return 0; +} + +/****************************************************************************** +* Writes a value to a PHY register +* +* hw - Struct containing variables accessed by shared code +* reg_addr - address of the PHY register to write +* data - data to write to the PHY +******************************************************************************/ +static int +e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) +{ + uint32_t i; + uint32_t mdic = 0; + const uint32_t phy_addr = 1; + + if (reg_addr > MAX_PHY_REG_ADDRESS) { + DEBUGOUT("PHY Address %d is out of range\n", reg_addr); + return -E1000_ERR_PARAM; + } + + if (hw->mac_type > e1000_82543) { + /* Set up Op-code, Phy Address, register address, and data intended + * for the PHY register in the MDI Control register. The MAC will take + * care of interfacing with the PHY to send the desired data. + */ + mdic = (((uint32_t) phy_data) | + (reg_addr << E1000_MDIC_REG_SHIFT) | + (phy_addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_WRITE)); + + E1000_WRITE_REG(hw, MDIC, mdic); + + /* Poll the ready bit to see if the MDI read completed */ + for (i = 0; i < 64; i++) { + udelay(10); + mdic = E1000_READ_REG(hw, MDIC); + if (mdic & E1000_MDIC_READY) + break; + } + if (!(mdic & E1000_MDIC_READY)) { + DEBUGOUT("MDI Write did not complete\n"); + return -E1000_ERR_PHY; + } + } else { + /* We'll need to use the SW defined pins to shift the write command + * out to the PHY. We first send a preamble to the PHY to signal the + * beginning of the MII instruction. This is done by sending 32 + * consecutive "1" bits. + */ + e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); + + /* Now combine the remaining required fields that will indicate a + * write operation. We use this method instead of calling the + * e1000_shift_out_mdi_bits routine for each field in the command. The + * format of a MII write instruction is as follows: + * . + */ + mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | + (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); + mdic <<= 16; + mdic |= (uint32_t) phy_data; + + e1000_shift_out_mdi_bits(hw, mdic, 32); + } + return 0; +} + +/****************************************************************************** +* Returns the PHY to the power-on reset state +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static void +e1000_phy_hw_reset(struct e1000_hw *hw) +{ + uint32_t ctrl; + uint32_t ctrl_ext; + + DEBUGFUNC(); + + DEBUGOUT("Resetting Phy...\n"); + + if (hw->mac_type > e1000_82543) { + /* Read the device control register and assert the E1000_CTRL_PHY_RST + * bit. Then, take it out of reset. + */ + ctrl = E1000_READ_REG(hw, CTRL); + E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); + E1000_WRITE_FLUSH(hw); + mdelay(10); + E1000_WRITE_REG(hw, CTRL, ctrl); + E1000_WRITE_FLUSH(hw); + } else { + /* Read the Extended Device Control Register, assert the PHY_RESET_DIR + * bit to put the PHY into reset. Then, take it out of reset. + */ + ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); + ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; + ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + mdelay(10); + ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; + E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); + E1000_WRITE_FLUSH(hw); + } + udelay(150); +} + +/****************************************************************************** +* Resets the PHY +* +* hw - Struct containing variables accessed by shared code +* +* Sets bit 15 of the MII Control regiser +******************************************************************************/ +static int +e1000_phy_reset(struct e1000_hw *hw) +{ + uint16_t phy_data; + + DEBUGFUNC(); + + if (e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + phy_data |= MII_CR_RESET; + if (e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) { + DEBUGOUT("PHY Write Error\n"); + return -E1000_ERR_PHY; + } + udelay(1); + return 0; +} + +/****************************************************************************** +* Probes the expected PHY address for known PHY IDs +* +* hw - Struct containing variables accessed by shared code +******************************************************************************/ +static int +e1000_detect_gig_phy(struct e1000_hw *hw) +{ + uint16_t phy_id_high, phy_id_low; + int match = FALSE; + + DEBUGFUNC(); + + /* Read the PHY ID Registers to identify which PHY is onboard. */ + if (e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + hw->phy_id = (uint32_t) (phy_id_high << 16); + udelay(2); + if (e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) { + DEBUGOUT("PHY Read Error\n"); + return -E1000_ERR_PHY; + } + hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); + + switch (hw->mac_type) { + case e1000_82543: + if (hw->phy_id == M88E1000_E_PHY_ID) + match = TRUE; + break; + case e1000_82544: + if (hw->phy_id == M88E1000_I_PHY_ID) + match = TRUE; + break; + case e1000_82540: + case e1000_82545: + case e1000_82546: + if (hw->phy_id == M88E1011_I_PHY_ID) + match = TRUE; + break; + default: + DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); + return -E1000_ERR_CONFIG; + } + if (match) { + DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); + return 0; + } + DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); + return -E1000_ERR_PHY; +} + +/** + * e1000_sw_init - Initialize general software structures (struct e1000_adapter) + * + * e1000_sw_init initializes the Adapter private data structure. + * Fields are initialized based on PCI device information and + * OS network device settings (MTU size). + **/ + +static int +e1000_sw_init(struct eth_device *nic, int cardnum) +{ + struct e1000_hw *hw = (typeof(hw)) nic->priv; + int result; + + /* PCI config space info */ + pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); + pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); + pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, + &hw->subsystem_vendor_id); + pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); + + pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); + pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); + + /* identify the MAC */ + result = e1000_set_mac_type(hw); + if (result) { + E1000_ERR("Unknown MAC Type\n"); + return result; + } + + /* lan a vs. lan b settings */ + if (hw->mac_type == e1000_82546) + /*this also works w/ multiple 82546 cards */ + /*but not if they're intermingled /w other e1000s */ + hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a; + else + hw->lan_loc = e1000_lan_a; + + /* flow control settings */ + hw->fc_high_water = E1000_FC_HIGH_THRESH; + hw->fc_low_water = E1000_FC_LOW_THRESH; + hw->fc_pause_time = E1000_FC_PAUSE_TIME; + hw->fc_send_xon = 1; + + /* Media type - copper or fiber */ + + if (hw->mac_type >= e1000_82543) { + uint32_t status = E1000_READ_REG(hw, STATUS); + + if (status & E1000_STATUS_TBIMODE) { + DEBUGOUT("fiber interface\n"); + hw->media_type = e1000_media_type_fiber; + } else { + DEBUGOUT("copper interface\n"); + hw->media_type = e1000_media_type_copper; + } + } else { + hw->media_type = e1000_media_type_fiber; + } + + if (hw->mac_type < e1000_82543) + hw->report_tx_early = 0; + else + hw->report_tx_early = 1; + + hw->tbi_compatibility_en = TRUE; +#if 0 + hw->wait_autoneg_complete = FALSE; + hw->adaptive_ifs = TRUE; + + /* Copper options */ + if (hw->media_type == e1000_media_type_copper) { + hw->mdix = AUTO_ALL_MODES; + hw->disable_polarity_correction = FALSE; + } +#endif + return E1000_SUCCESS; +} + +void +fill_rx(struct e1000_hw *hw) +{ + struct e1000_rx_desc *rd; + + rx_last = rx_tail; + rd = rx_base + rx_tail; + rx_tail = (rx_tail + 1) % 8; + memset(rd, 0, 16); + rd->buffer_addr = cpu_to_le64((u32) & packet); + E1000_WRITE_REG(hw, RDT, rx_tail); +} + +/** + * e1000_configure_tx - Configure 8254x Transmit Unit after Reset + * @adapter: board private structure + * + * Configure the Tx unit of the MAC after a reset. + **/ + +static void +e1000_configure_tx(struct e1000_hw *hw) +{ + unsigned long ptr; + unsigned long tctl; + unsigned long tipg; + + ptr = (u32) tx_pool; + if (ptr & 0xf) + ptr = (ptr + 0x10) & (~0xf); + + tx_base = (typeof(tx_base)) ptr; + + E1000_WRITE_REG(hw, TDBAL, (u32) tx_base); + E1000_WRITE_REG(hw, TDBAH, 0); + + E1000_WRITE_REG(hw, TDLEN, 128); + + /* Setup the HW Tx Head and Tail descriptor pointers */ + E1000_WRITE_REG(hw, TDH, 0); + E1000_WRITE_REG(hw, TDT, 0); + tx_tail = 0; + + /* Set the default values for the Tx Inter Packet Gap timer */ + switch (hw->mac_type) { + case e1000_82542_rev2_0: + case e1000_82542_rev2_1: + tipg = DEFAULT_82542_TIPG_IPGT; + tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; + tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; + break; + default: + if (hw->media_type == e1000_media_type_fiber) + tipg = DEFAULT_82543_TIPG_IPGT_FIBER; + else + tipg = DEFAULT_82543_TIPG_IPGT_COPPER; + tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; + tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; + } + E1000_WRITE_REG(hw, TIPG, tipg); +#if 0 + /* Set the Tx Interrupt Delay register */ + E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay); + if (hw->mac_type >= e1000_82540) + E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay); +#endif + /* Program the Transmit Control Register */ + tctl = E1000_READ_REG(hw, TCTL); + tctl &= ~E1000_TCTL_CT; + tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | + (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); + E1000_WRITE_REG(hw, TCTL, tctl); + + e1000_config_collision_dist(hw); +#if 0 + /* Setup Transmit Descriptor Settings for this adapter */ + adapter->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_IDE; + + if (adapter->hw.report_tx_early == 1) + adapter->txd_cmd |= E1000_TXD_CMD_RS; + else + adapter->txd_cmd |= E1000_TXD_CMD_RPS; +#endif +} + +/** + * e1000_setup_rctl - configure the receive control register + * @adapter: Board private structure + **/ +static void +e1000_setup_rctl(struct e1000_hw *hw) +{ + uint32_t rctl; + + rctl = E1000_READ_REG(hw, RCTL); + + rctl &= ~(3 << E1000_RCTL_MO_SHIFT); + + rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF; /* | + (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */ + + if (hw->tbi_compatibility_on == 1) + rctl |= E1000_RCTL_SBP; + else + rctl &= ~E1000_RCTL_SBP; + + rctl &= ~(E1000_RCTL_SZ_4096); +#if 0 + switch (adapter->rx_buffer_len) { + case E1000_RXBUFFER_2048: + default: +#endif + rctl |= E1000_RCTL_SZ_2048; + rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); +#if 0 + break; + case E1000_RXBUFFER_4096: + rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX | E1000_RCTL_LPE; + break; + case E1000_RXBUFFER_8192: + rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX | E1000_RCTL_LPE; + break; + case E1000_RXBUFFER_16384: + rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX | E1000_RCTL_LPE; + break; + } +#endif + E1000_WRITE_REG(hw, RCTL, rctl); +} + +/** + * e1000_configure_rx - Configure 8254x Receive Unit after Reset + * @adapter: board private structure + * + * Configure the Rx unit of the MAC after a reset. + **/ +static void +e1000_configure_rx(struct e1000_hw *hw) +{ + unsigned long ptr; + unsigned long rctl; +#if 0 + unsigned long rxcsum; +#endif + rx_tail = 0; + /* make sure receives are disabled while setting up the descriptors */ + rctl = E1000_READ_REG(hw, RCTL); + E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); +#if 0 + /* set the Receive Delay Timer Register */ + + E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay); +#endif + if (hw->mac_type >= e1000_82540) { +#if 0 + E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay); +#endif + /* Set the interrupt throttling rate. Value is calculated + * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */ +#define MAX_INTS_PER_SEC 8000 +#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) + E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); + } + + /* Setup the Base and Length of the Rx Descriptor Ring */ + ptr = (u32) rx_pool; + if (ptr & 0xf) + ptr = (ptr + 0x10) & (~0xf); + rx_base = (typeof(rx_base)) ptr; + E1000_WRITE_REG(hw, RDBAL, (u32) rx_base); + E1000_WRITE_REG(hw, RDBAH, 0); + + E1000_WRITE_REG(hw, RDLEN, 128); + + /* Setup the HW Rx Head and Tail Descriptor Pointers */ + E1000_WRITE_REG(hw, RDH, 0); + E1000_WRITE_REG(hw, RDT, 0); +#if 0 + /* Enable 82543 Receive Checksum Offload for TCP and UDP */ + if ((adapter->hw.mac_type >= e1000_82543) && (adapter->rx_csum == TRUE)) { + rxcsum = E1000_READ_REG(hw, RXCSUM); + rxcsum |= E1000_RXCSUM_TUOFL; + E1000_WRITE_REG(hw, RXCSUM, rxcsum); + } +#endif + /* Enable Receives */ + + E1000_WRITE_REG(hw, RCTL, rctl); + fill_rx(hw); +} + +/************************************************************************** +POLL - Wait for a frame +***************************************************************************/ +static int +e1000_poll(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + struct e1000_rx_desc *rd; + /* return true if there's an ethernet packet ready to read */ + rd = rx_base + rx_last; + if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD) + return 0; + /*DEBUGOUT("recv: packet len=%d \n", rd->length); */ + NetReceive((uchar *)packet, le32_to_cpu(rd->length)); + fill_rx(hw); + return 1; +} + +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static int +e1000_transmit(struct eth_device *nic, volatile void *packet, int length) +{ + struct e1000_hw *hw = nic->priv; + struct e1000_tx_desc *txp; + int i = 0; + + txp = tx_base + tx_tail; + tx_tail = (tx_tail + 1) % 8; + + txp->buffer_addr = cpu_to_le64(virt_to_bus(packet)); + txp->lower.data = cpu_to_le32(E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | + E1000_TXD_CMD_IFCS | length); + txp->upper.data = 0; + E1000_WRITE_REG(hw, TDT, tx_tail); + + while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) { + if (i++ > TOUT_LOOP) { + DEBUGOUT("e1000: tx timeout\n"); + return 0; + } + udelay(10); /* give the nic a chance to write to the register */ + } + return 1; +} + +/*reset function*/ +static inline int +e1000_reset(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + + e1000_reset_hw(hw); + if (hw->mac_type >= e1000_82544) { + E1000_WRITE_REG(hw, WUC, 0); + } + return e1000_init_hw(nic); +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void +e1000_disable(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + + /* Turn off the ethernet interface */ + E1000_WRITE_REG(hw, RCTL, 0); + E1000_WRITE_REG(hw, TCTL, 0); + + /* Clear the transmit ring */ + E1000_WRITE_REG(hw, TDH, 0); + E1000_WRITE_REG(hw, TDT, 0); + + /* Clear the receive ring */ + E1000_WRITE_REG(hw, RDH, 0); + E1000_WRITE_REG(hw, RDT, 0); + + /* put the card in its initial state */ +#if 0 + E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); +#endif + mdelay(10); + +} + +/************************************************************************** +INIT - set up ethernet interface(s) +***************************************************************************/ +static int +e1000_init(struct eth_device *nic, bd_t * bis) +{ + struct e1000_hw *hw = nic->priv; + int ret_val = 0; + + ret_val = e1000_reset(nic); + if (ret_val < 0) { + if ((ret_val == -E1000_ERR_NOLINK) || + (ret_val == -E1000_ERR_TIMEOUT)) { + E1000_ERR("Valid Link not detected\n"); + } else { + E1000_ERR("Hardware Initialization Failed\n"); + } + return 0; + } + e1000_configure_tx(hw); + e1000_setup_rctl(hw); + e1000_configure_rx(hw); + return 1; +} + +/************************************************************************** +PROBE - Look for an adapter, this routine's visible to the outside +You should omit the last argument struct pci_device * for a non-PCI NIC +***************************************************************************/ +int +e1000_initialize(bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *nic = NULL; + struct e1000_hw *hw = NULL; + u32 iobase; + int idx = 0; + u32 PciCommandWord; + + while (1) { /* Find PCI device(s) */ + if ((devno = pci_find_devices(supported, idx++)) < 0) { + break; + } + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0xf; /* Mask the bits that say "this is an io addr" */ + DEBUGOUT("e1000#%d: iobase 0x%08x\n", card_number, iobase); + + pci_write_config_dword(devno, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + /* Check if I/O accesses and Bus Mastering are enabled. */ + pci_read_config_dword(devno, PCI_COMMAND, &PciCommandWord); + if (!(PciCommandWord & PCI_COMMAND_MEMORY)) { + printf("Error: Can not enable MEM access.\n"); + continue; + } else if (!(PciCommandWord & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + nic = (struct eth_device *) malloc(sizeof (*nic)); + hw = (struct e1000_hw *) malloc(sizeof (*hw)); + hw->pdev = devno; + nic->priv = hw; + nic->iobase = bus_to_phys(devno, iobase); + + sprintf(nic->name, "e1000#%d", card_number); + + /* Are these variables needed? */ +#if 0 + hw->fc = e1000_fc_none; + hw->original_fc = e1000_fc_none; +#else + hw->fc = e1000_fc_default; + hw->original_fc = e1000_fc_default; +#endif + hw->autoneg_failed = 0; + hw->get_link_status = TRUE; + hw->hw_addr = (typeof(hw->hw_addr)) iobase; + hw->mac_type = e1000_undefined; + + /* MAC and Phy settings */ + if (e1000_sw_init(nic, card_number) < 0) { + free(hw); + free(nic); + return 0; + } +#ifndef CONFIG_AP1000 + if (e1000_validate_eeprom_checksum(nic) < 0) { + printf("The EEPROM Checksum Is Not Valid\n"); + free(hw); + free(nic); + return 0; + } +#endif + e1000_read_mac_addr(nic); + + E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA); + + printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n", + nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], + nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); + + nic->init = e1000_init; + nic->recv = e1000_poll; + nic->send = e1000_transmit; + nic->halt = e1000_disable; + + eth_register(nic); + + card_number++; + } + return 1; +} + +#endif diff --git a/drivers/e1000.h b/drivers/e1000.h new file mode 100644 index 000000000..0fbdc90b1 --- /dev/null +++ b/drivers/e1000.h @@ -0,0 +1,1758 @@ +/******************************************************************************* + + + Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License along with + this program; if not, write to the Free Software Foundation, Inc., 59 + Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + The full GNU General Public License is included in this distribution in the + file called LICENSE. + + Contact Information: + Linux NICS + Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 + +*******************************************************************************/ + +/* e1000_hw.h + * Structures, enums, and macros for the MAC + */ + +#ifndef _E1000_HW_H_ +#define _E1000_HW_H_ + +#include +#include +#include +#include +#include + +#define E1000_ERR(args...) printf("e1000: " args) + +#ifdef E1000_DEBUG +#define E1000_DBG(args...) printf("e1000: " args) +#define DEBUGOUT(fmt,args...) printf(fmt ,##args) +#define DEBUGFUNC() printf("%s\n", __FUNCTION__); +#else +#define E1000_DBG(args...) +#define DEBUGFUNC() +#define DEBUGOUT(fmt,args...) +#endif + +/* Forward declarations of structures used by the shared code */ +struct e1000_hw; +struct e1000_hw_stats; + +typedef enum { + FALSE = 0, + TRUE = 1 +} boolean_t; + +/* Enumerated types specific to the e1000 hardware */ +/* Media Access Controlers */ +typedef enum { + e1000_undefined = 0, + e1000_82542_rev2_0, + e1000_82542_rev2_1, + e1000_82543, + e1000_82544, + e1000_82540, + e1000_82545, + e1000_82546, + e1000_num_macs +} e1000_mac_type; + +/* Media Types */ +typedef enum { + e1000_media_type_copper = 0, + e1000_media_type_fiber = 1, + e1000_num_media_types +} e1000_media_type; + +typedef enum { + e1000_10_half = 0, + e1000_10_full = 1, + e1000_100_half = 2, + e1000_100_full = 3 +} e1000_speed_duplex_type; + +typedef enum { + e1000_lan_a = 0, + e1000_lan_b = 1 +} e1000_lan_loc; + +/* Flow Control Settings */ +typedef enum { + e1000_fc_none = 0, + e1000_fc_rx_pause = 1, + e1000_fc_tx_pause = 2, + e1000_fc_full = 3, + e1000_fc_default = 0xFF +} e1000_fc_type; + +/* PCI bus types */ +typedef enum { + e1000_bus_type_unknown = 0, + e1000_bus_type_pci, + e1000_bus_type_pcix +} e1000_bus_type; + +/* PCI bus speeds */ +typedef enum { + e1000_bus_speed_unknown = 0, + e1000_bus_speed_33, + e1000_bus_speed_66, + e1000_bus_speed_100, + e1000_bus_speed_133, + e1000_bus_speed_reserved +} e1000_bus_speed; + +/* PCI bus widths */ +typedef enum { + e1000_bus_width_unknown = 0, + e1000_bus_width_32, + e1000_bus_width_64 +} e1000_bus_width; + +/* PHY status info structure and supporting enums */ +typedef enum { + e1000_cable_length_50 = 0, + e1000_cable_length_50_80, + e1000_cable_length_80_110, + e1000_cable_length_110_140, + e1000_cable_length_140, + e1000_cable_length_undefined = 0xFF +} e1000_cable_length; + +typedef enum { + e1000_10bt_ext_dist_enable_normal = 0, + e1000_10bt_ext_dist_enable_lower, + e1000_10bt_ext_dist_enable_undefined = 0xFF +} e1000_10bt_ext_dist_enable; + +typedef enum { + e1000_rev_polarity_normal = 0, + e1000_rev_polarity_reversed, + e1000_rev_polarity_undefined = 0xFF +} e1000_rev_polarity; + +typedef enum { + e1000_polarity_reversal_enabled = 0, + e1000_polarity_reversal_disabled, + e1000_polarity_reversal_undefined = 0xFF +} e1000_polarity_reversal; + +typedef enum { + e1000_auto_x_mode_manual_mdi = 0, + e1000_auto_x_mode_manual_mdix, + e1000_auto_x_mode_auto1, + e1000_auto_x_mode_auto2, + e1000_auto_x_mode_undefined = 0xFF +} e1000_auto_x_mode; + +typedef enum { + e1000_1000t_rx_status_not_ok = 0, + e1000_1000t_rx_status_ok, + e1000_1000t_rx_status_undefined = 0xFF +} e1000_1000t_rx_status; + +struct e1000_phy_info { + e1000_cable_length cable_length; + e1000_10bt_ext_dist_enable extended_10bt_distance; + e1000_rev_polarity cable_polarity; + e1000_polarity_reversal polarity_correction; + e1000_auto_x_mode mdix_mode; + e1000_1000t_rx_status local_rx; + e1000_1000t_rx_status remote_rx; +}; + +struct e1000_phy_stats { + uint32_t idle_errors; + uint32_t receive_errors; +}; + +/* Error Codes */ +#define E1000_SUCCESS 0 +#define E1000_ERR_EEPROM 1 +#define E1000_ERR_PHY 2 +#define E1000_ERR_CONFIG 3 +#define E1000_ERR_PARAM 4 +#define E1000_ERR_MAC_TYPE 5 +#define E1000_ERR_NOLINK 6 +#define E1000_ERR_TIMEOUT 7 + +/* PCI Device IDs */ +#define E1000_DEV_ID_82542 0x1000 +#define E1000_DEV_ID_82543GC_FIBER 0x1001 +#define E1000_DEV_ID_82543GC_COPPER 0x1004 +#define E1000_DEV_ID_82544EI_COPPER 0x1008 +#define E1000_DEV_ID_82544EI_FIBER 0x1009 +#define E1000_DEV_ID_82544GC_COPPER 0x100C +#define E1000_DEV_ID_82544GC_LOM 0x100D +#define E1000_DEV_ID_82540EM 0x100E +#define E1000_DEV_ID_82540EM_LOM 0x1015 +#define E1000_DEV_ID_82545EM_COPPER 0x100F +#define E1000_DEV_ID_82545EM_FIBER 0x1011 +#define E1000_DEV_ID_82546EB_COPPER 0x1010 +#define E1000_DEV_ID_82546EB_FIBER 0x1012 +#define NUM_DEV_IDS 13 + +#define NODE_ADDRESS_SIZE 6 +#define ETH_LENGTH_OF_ADDRESS 6 + +/* MAC decode size is 128K - This is the size of BAR0 */ +#define MAC_DECODE_SIZE (128 * 1024) + +#define E1000_82542_2_0_REV_ID 2 +#define E1000_82542_2_1_REV_ID 3 + +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define HALF_DUPLEX 1 +#define FULL_DUPLEX 2 + +/* The sizes (in bytes) of a ethernet packet */ +#define ENET_HEADER_SIZE 14 +#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ +#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ +#define ETHERNET_FCS_SIZE 4 +#define MAXIMUM_ETHERNET_PACKET_SIZE \ + (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) +#define MINIMUM_ETHERNET_PACKET_SIZE \ + (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) +#define CRC_LENGTH ETHERNET_FCS_SIZE +#define MAX_JUMBO_FRAME_SIZE 0x3F00 + +/* 802.1q VLAN Packet Sizes */ +#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ + +/* Ethertype field values */ +#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ +#define ETHERNET_IP_TYPE 0x0800 /* IP packets */ +#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ + +/* Packet Header defines */ +#define IP_PROTOCOL_TCP 6 +#define IP_PROTOCOL_UDP 0x11 + +/* This defines the bits that are set in the Interrupt Mask + * Set/Read Register. Each bit is documented below: + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) + * o RXSEQ = Receive Sequence Error + */ +#define POLL_IMS_ENABLE_MASK ( \ + E1000_IMS_RXDMT0 | \ + E1000_IMS_RXSEQ) + +/* This defines the bits that are set in the Interrupt Mask + * Set/Read Register. Each bit is documented below: + * o RXT0 = Receiver Timer Interrupt (ring 0) + * o TXDW = Transmit Descriptor Written Back + * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) + * o RXSEQ = Receive Sequence Error + * o LSC = Link Status Change + */ +#define IMS_ENABLE_MASK ( \ + E1000_IMS_RXT0 | \ + E1000_IMS_TXDW | \ + E1000_IMS_RXDMT0 | \ + E1000_IMS_RXSEQ | \ + E1000_IMS_LSC) + +/* The number of high/low register pairs in the RAR. The RAR (Receive Address + * Registers) holds the directed and multicast addresses that we monitor. We + * reserve one of these spots for our directed address, allowing us room for + * E1000_RAR_ENTRIES - 1 multicast addresses. + */ +#define E1000_RAR_ENTRIES 16 + +#define MIN_NUMBER_OF_DESCRIPTORS 8 +#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 + +/* Receive Descriptor */ +struct e1000_rx_desc { + uint64_t buffer_addr; /* Address of the descriptor's data buffer */ + uint16_t length; /* Length of data DMAed into data buffer */ + uint16_t csum; /* Packet checksum */ + uint8_t status; /* Descriptor status */ + uint8_t errors; /* Descriptor Errors */ + uint16_t special; +}; + +/* Receive Decriptor bit definitions */ +#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ +#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ +#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ +#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ +#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ +#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ +#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ +#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ +#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ +#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ +#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ +#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ +#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ +#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ +#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ +#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ +#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ +#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ +#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ + +/* mask to determine if packets should be dropped due to frame errors */ +#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ + E1000_RXD_ERR_CE | \ + E1000_RXD_ERR_SE | \ + E1000_RXD_ERR_SEQ | \ + E1000_RXD_ERR_CXE | \ + E1000_RXD_ERR_RXE) + +/* Transmit Descriptor */ +struct e1000_tx_desc { + uint64_t buffer_addr; /* Address of the descriptor's data buffer */ + union { + uint32_t data; + struct { + uint16_t length; /* Data buffer length */ + uint8_t cso; /* Checksum offset */ + uint8_t cmd; /* Descriptor control */ + } flags; + } lower; + union { + uint32_t data; + struct { + uint8_t status; /* Descriptor status */ + uint8_t css; /* Checksum start */ + uint16_t special; + } fields; + } upper; +}; + +/* Transmit Descriptor bit definitions */ +#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ +#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ +#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ +#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ +#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ +#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ +#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ +#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ +#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ +#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ +#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ +#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ +#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ +#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ +#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ +#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ +#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ +#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ +#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ +#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ + +/* Offload Context Descriptor */ +struct e1000_context_desc { + union { + uint32_t ip_config; + struct { + uint8_t ipcss; /* IP checksum start */ + uint8_t ipcso; /* IP checksum offset */ + uint16_t ipcse; /* IP checksum end */ + } ip_fields; + } lower_setup; + union { + uint32_t tcp_config; + struct { + uint8_t tucss; /* TCP checksum start */ + uint8_t tucso; /* TCP checksum offset */ + uint16_t tucse; /* TCP checksum end */ + } tcp_fields; + } upper_setup; + uint32_t cmd_and_length; /* */ + union { + uint32_t data; + struct { + uint8_t status; /* Descriptor status */ + uint8_t hdr_len; /* Header length */ + uint16_t mss; /* Maximum segment size */ + } fields; + } tcp_seg_setup; +}; + +/* Offload data descriptor */ +struct e1000_data_desc { + uint64_t buffer_addr; /* Address of the descriptor's buffer address */ + union { + uint32_t data; + struct { + uint16_t length; /* Data buffer length */ + uint8_t typ_len_ext; /* */ + uint8_t cmd; /* */ + } flags; + } lower; + union { + uint32_t data; + struct { + uint8_t status; /* Descriptor status */ + uint8_t popts; /* Packet Options */ + uint16_t special; /* */ + } fields; + } upper; +}; + +/* Filters */ +#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ +#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ +#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ + +/* Receive Address Register */ +struct e1000_rar { + volatile uint32_t low; /* receive address low */ + volatile uint32_t high; /* receive address high */ +}; + +/* The number of entries in the Multicast Table Array (MTA). */ +#define E1000_NUM_MTA_REGISTERS 128 + +/* IPv4 Address Table Entry */ +struct e1000_ipv4_at_entry { + volatile uint32_t ipv4_addr; /* IP Address (RW) */ + volatile uint32_t reserved; +}; + +/* Four wakeup IP addresses are supported */ +#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 +#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX +#define E1000_IP6AT_SIZE 1 + +/* IPv6 Address Table Entry */ +struct e1000_ipv6_at_entry { + volatile uint8_t ipv6_addr[16]; +}; + +/* Flexible Filter Length Table Entry */ +struct e1000_fflt_entry { + volatile uint32_t length; /* Flexible Filter Length (RW) */ + volatile uint32_t reserved; +}; + +/* Flexible Filter Mask Table Entry */ +struct e1000_ffmt_entry { + volatile uint32_t mask; /* Flexible Filter Mask (RW) */ + volatile uint32_t reserved; +}; + +/* Flexible Filter Value Table Entry */ +struct e1000_ffvt_entry { + volatile uint32_t value; /* Flexible Filter Value (RW) */ + volatile uint32_t reserved; +}; + +/* Four Flexible Filters are supported */ +#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 + +/* Each Flexible Filter is at most 128 (0x80) bytes in length */ +#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 + +#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX +#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX +#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX + +/* Register Set. (82543, 82544) + * + * Registers are defined to be 32 bits and should be accessed as 32 bit values. + * These registers are physically located on the NIC, but are mapped into the + * host memory address space. + * + * RW - register is both readable and writable + * RO - register is read only + * WO - register is write only + * R/clr - register is read only and is cleared when read + * A - register array + */ +#define E1000_CTRL 0x00000 /* Device Control - RW */ +#define E1000_STATUS 0x00008 /* Device Status - RO */ +#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ +#define E1000_EERD 0x00014 /* EEPROM Read - RW */ +#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ +#define E1000_MDIC 0x00020 /* MDI Control - RW */ +#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ +#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ +#define E1000_FCT 0x00030 /* Flow Control Type - RW */ +#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ +#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ +#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ +#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ +#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ +#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ +#define E1000_RCTL 0x00100 /* RX Control - RW */ +#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ +#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ +#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ +#define E1000_TCTL 0x00400 /* TX Control - RW */ +#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ +#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ +#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ +#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ +#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ +#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ +#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ +#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ +#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ +#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ +#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ +#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ +#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ +#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ +#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ +#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ +#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ +#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ +#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ +#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ +#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ +#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ +#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ +#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ +#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ +#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ +#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ +#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ +#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ +#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ +#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ +#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ +#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ +#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ +#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ +#define E1000_COLC 0x04028 /* Collision Count - R/clr */ +#define E1000_DC 0x04030 /* Defer Count - R/clr */ +#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ +#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ +#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ +#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ +#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ +#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ +#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ +#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ +#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ +#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ +#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ +#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ +#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ +#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ +#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ +#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ +#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ +#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ +#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ +#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ +#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ +#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ +#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ +#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ +#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ +#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ +#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ +#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ +#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ +#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ +#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ +#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ +#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ +#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ +#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ +#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ +#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ +#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ +#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ +#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ +#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ +#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ +#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ +#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ +#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ +#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ +#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ +#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ +#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ +#define E1000_RA 0x05400 /* Receive Address - RW Array */ +#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ +#define E1000_WUC 0x05800 /* Wakeup Control - RW */ +#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ +#define E1000_WUS 0x05810 /* Wakeup Status - RO */ +#define E1000_MANC 0x05820 /* Management Control - RW */ +#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ +#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ +#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ +#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ +#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ +#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ +#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ +#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ + +/* Register Set (82542) + * + * Some of the 82542 registers are located at different offsets than they are + * in more current versions of the 8254x. Despite the difference in location, + * the registers function in the same manner. + */ +#define E1000_82542_CTRL E1000_CTRL +#define E1000_82542_STATUS E1000_STATUS +#define E1000_82542_EECD E1000_EECD +#define E1000_82542_EERD E1000_EERD +#define E1000_82542_CTRL_EXT E1000_CTRL_EXT +#define E1000_82542_MDIC E1000_MDIC +#define E1000_82542_FCAL E1000_FCAL +#define E1000_82542_FCAH E1000_FCAH +#define E1000_82542_FCT E1000_FCT +#define E1000_82542_VET E1000_VET +#define E1000_82542_RA 0x00040 +#define E1000_82542_ICR E1000_ICR +#define E1000_82542_ITR E1000_ITR +#define E1000_82542_ICS E1000_ICS +#define E1000_82542_IMS E1000_IMS +#define E1000_82542_IMC E1000_IMC +#define E1000_82542_RCTL E1000_RCTL +#define E1000_82542_RDTR 0x00108 +#define E1000_82542_RDBAL 0x00110 +#define E1000_82542_RDBAH 0x00114 +#define E1000_82542_RDLEN 0x00118 +#define E1000_82542_RDH 0x00120 +#define E1000_82542_RDT 0x00128 +#define E1000_82542_FCRTH 0x00160 +#define E1000_82542_FCRTL 0x00168 +#define E1000_82542_FCTTV E1000_FCTTV +#define E1000_82542_TXCW E1000_TXCW +#define E1000_82542_RXCW E1000_RXCW +#define E1000_82542_MTA 0x00200 +#define E1000_82542_TCTL E1000_TCTL +#define E1000_82542_TIPG E1000_TIPG +#define E1000_82542_TDBAL 0x00420 +#define E1000_82542_TDBAH 0x00424 +#define E1000_82542_TDLEN 0x00428 +#define E1000_82542_TDH 0x00430 +#define E1000_82542_TDT 0x00438 +#define E1000_82542_TIDV 0x00440 +#define E1000_82542_TBT E1000_TBT +#define E1000_82542_AIT E1000_AIT +#define E1000_82542_VFTA 0x00600 +#define E1000_82542_LEDCTL E1000_LEDCTL +#define E1000_82542_PBA E1000_PBA +#define E1000_82542_RXDCTL E1000_RXDCTL +#define E1000_82542_RADV E1000_RADV +#define E1000_82542_RSRPD E1000_RSRPD +#define E1000_82542_TXDMAC E1000_TXDMAC +#define E1000_82542_TXDCTL E1000_TXDCTL +#define E1000_82542_TADV E1000_TADV +#define E1000_82542_TSPMT E1000_TSPMT +#define E1000_82542_CRCERRS E1000_CRCERRS +#define E1000_82542_ALGNERRC E1000_ALGNERRC +#define E1000_82542_SYMERRS E1000_SYMERRS +#define E1000_82542_RXERRC E1000_RXERRC +#define E1000_82542_MPC E1000_MPC +#define E1000_82542_SCC E1000_SCC +#define E1000_82542_ECOL E1000_ECOL +#define E1000_82542_MCC E1000_MCC +#define E1000_82542_LATECOL E1000_LATECOL +#define E1000_82542_COLC E1000_COLC +#define E1000_82542_DC E1000_DC +#define E1000_82542_TNCRS E1000_TNCRS +#define E1000_82542_SEC E1000_SEC +#define E1000_82542_CEXTERR E1000_CEXTERR +#define E1000_82542_RLEC E1000_RLEC +#define E1000_82542_XONRXC E1000_XONRXC +#define E1000_82542_XONTXC E1000_XONTXC +#define E1000_82542_XOFFRXC E1000_XOFFRXC +#define E1000_82542_XOFFTXC E1000_XOFFTXC +#define E1000_82542_FCRUC E1000_FCRUC +#define E1000_82542_PRC64 E1000_PRC64 +#define E1000_82542_PRC127 E1000_PRC127 +#define E1000_82542_PRC255 E1000_PRC255 +#define E1000_82542_PRC511 E1000_PRC511 +#define E1000_82542_PRC1023 E1000_PRC1023 +#define E1000_82542_PRC1522 E1000_PRC1522 +#define E1000_82542_GPRC E1000_GPRC +#define E1000_82542_BPRC E1000_BPRC +#define E1000_82542_MPRC E1000_MPRC +#define E1000_82542_GPTC E1000_GPTC +#define E1000_82542_GORCL E1000_GORCL +#define E1000_82542_GORCH E1000_GORCH +#define E1000_82542_GOTCL E1000_GOTCL +#define E1000_82542_GOTCH E1000_GOTCH +#define E1000_82542_RNBC E1000_RNBC +#define E1000_82542_RUC E1000_RUC +#define E1000_82542_RFC E1000_RFC +#define E1000_82542_ROC E1000_ROC +#define E1000_82542_RJC E1000_RJC +#define E1000_82542_MGTPRC E1000_MGTPRC +#define E1000_82542_MGTPDC E1000_MGTPDC +#define E1000_82542_MGTPTC E1000_MGTPTC +#define E1000_82542_TORL E1000_TORL +#define E1000_82542_TORH E1000_TORH +#define E1000_82542_TOTL E1000_TOTL +#define E1000_82542_TOTH E1000_TOTH +#define E1000_82542_TPR E1000_TPR +#define E1000_82542_TPT E1000_TPT +#define E1000_82542_PTC64 E1000_PTC64 +#define E1000_82542_PTC127 E1000_PTC127 +#define E1000_82542_PTC255 E1000_PTC255 +#define E1000_82542_PTC511 E1000_PTC511 +#define E1000_82542_PTC1023 E1000_PTC1023 +#define E1000_82542_PTC1522 E1000_PTC1522 +#define E1000_82542_MPTC E1000_MPTC +#define E1000_82542_BPTC E1000_BPTC +#define E1000_82542_TSCTC E1000_TSCTC +#define E1000_82542_TSCTFC E1000_TSCTFC +#define E1000_82542_RXCSUM E1000_RXCSUM +#define E1000_82542_WUC E1000_WUC +#define E1000_82542_WUFC E1000_WUFC +#define E1000_82542_WUS E1000_WUS +#define E1000_82542_MANC E1000_MANC +#define E1000_82542_IPAV E1000_IPAV +#define E1000_82542_IP4AT E1000_IP4AT +#define E1000_82542_IP6AT E1000_IP6AT +#define E1000_82542_WUPL E1000_WUPL +#define E1000_82542_WUPM E1000_WUPM +#define E1000_82542_FFLT E1000_FFLT +#define E1000_82542_FFMT E1000_FFMT +#define E1000_82542_FFVT E1000_FFVT + +/* Statistics counters collected by the MAC */ +struct e1000_hw_stats { + uint64_t crcerrs; + uint64_t algnerrc; + uint64_t symerrs; + uint64_t rxerrc; + uint64_t mpc; + uint64_t scc; + uint64_t ecol; + uint64_t mcc; + uint64_t latecol; + uint64_t colc; + uint64_t dc; + uint64_t tncrs; + uint64_t sec; + uint64_t cexterr; + uint64_t rlec; + uint64_t xonrxc; + uint64_t xontxc; + uint64_t xoffrxc; + uint64_t xofftxc; + uint64_t fcruc; + uint64_t prc64; + uint64_t prc127; + uint64_t prc255; + uint64_t prc511; + uint64_t prc1023; + uint64_t prc1522; + uint64_t gprc; + uint64_t bprc; + uint64_t mprc; + uint64_t gptc; + uint64_t gorcl; + uint64_t gorch; + uint64_t gotcl; + uint64_t gotch; + uint64_t rnbc; + uint64_t ruc; + uint64_t rfc; + uint64_t roc; + uint64_t rjc; + uint64_t mgprc; + uint64_t mgpdc; + uint64_t mgptc; + uint64_t torl; + uint64_t torh; + uint64_t totl; + uint64_t toth; + uint64_t tpr; + uint64_t tpt; + uint64_t ptc64; + uint64_t ptc127; + uint64_t ptc255; + uint64_t ptc511; + uint64_t ptc1023; + uint64_t ptc1522; + uint64_t mptc; + uint64_t bptc; + uint64_t tsctc; + uint64_t tsctfc; +}; + +/* Structure containing variables used by the shared code (e1000_hw.c) */ +struct e1000_hw { + pci_dev_t pdev; + uint8_t *hw_addr; + e1000_mac_type mac_type; + e1000_media_type media_type; + e1000_lan_loc lan_loc; + e1000_fc_type fc; +#if 0 + e1000_bus_speed bus_speed; + e1000_bus_width bus_width; + e1000_bus_type bus_type; + uint32_t io_base; +#endif + uint32_t phy_id; + uint32_t phy_addr; + uint32_t original_fc; + uint32_t txcw; + uint32_t autoneg_failed; +#if 0 + uint32_t max_frame_size; + uint32_t min_frame_size; + uint32_t mc_filter_type; + uint32_t num_mc_addrs; + uint32_t collision_delta; + uint32_t tx_packet_delta; + uint32_t ledctl_default; + uint32_t ledctl_mode1; + uint32_t ledctl_mode2; +#endif + uint16_t autoneg_advertised; + uint16_t pci_cmd_word; + uint16_t fc_high_water; + uint16_t fc_low_water; + uint16_t fc_pause_time; +#if 0 + uint16_t current_ifs_val; + uint16_t ifs_min_val; + uint16_t ifs_max_val; + uint16_t ifs_step_size; + uint16_t ifs_ratio; +#endif + uint16_t device_id; + uint16_t vendor_id; + uint16_t subsystem_id; + uint16_t subsystem_vendor_id; + uint8_t revision_id; +#if 0 + uint8_t autoneg; + uint8_t mdix; + uint8_t forced_speed_duplex; + uint8_t wait_autoneg_complete; + uint8_t dma_fairness; +#endif +#if 0 + uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; + boolean_t disable_polarity_correction; +#endif + boolean_t get_link_status; + boolean_t tbi_compatibility_en; + boolean_t tbi_compatibility_on; + boolean_t fc_send_xon; + boolean_t report_tx_early; +#if 0 + boolean_t adaptive_ifs; + boolean_t ifs_params_forced; + boolean_t in_ifs_mode; +#endif +}; + +#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ +#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ + +/* Register Bit Masks */ +/* Device Control */ +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ +#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ +#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ +#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ +#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ +#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ +#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ +#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ +#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ +#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ +#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ +#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ +#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ +#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ +#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ +#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ +#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ +#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ +#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ +#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ +#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ +#define E1000_CTRL_RST 0x04000000 /* Global reset */ +#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ +#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ +#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ +#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ + +/* Device Status */ +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ +#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ +#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ +#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ +#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ +#define E1000_STATUS_SPEED_MASK 0x000000C0 +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ +#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ +#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ +#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ +#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ +#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ +#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ +#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ + +/* Constants used to intrepret the masked PCI-X bus speed. */ +#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ +#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ +#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ + +/* EEPROM/Flash Control */ +#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ +#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ +#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ +#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ +#define E1000_EECD_FWE_MASK 0x00000030 +#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ +#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ +#define E1000_EECD_FWE_SHIFT 4 +#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ +#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ +#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ +#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ + +/* EEPROM Read */ +#define E1000_EERD_START 0x00000001 /* Start Read */ +#define E1000_EERD_DONE 0x00000010 /* Read Done */ +#define E1000_EERD_ADDR_SHIFT 8 +#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ +#define E1000_EERD_DATA_SHIFT 16 +#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ + +/* Extended Device Control */ +#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ +#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ +#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN +#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ +#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ +#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ +#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ +#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA +#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ +#define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */ +#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ +#define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */ +#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ +#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ +#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ +#define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */ +#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ +#define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */ +#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ +#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ +#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ +#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ +#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 +#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 +#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 +#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 +#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 +#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 +#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 +#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 + +/* MDI Control */ +#define E1000_MDIC_DATA_MASK 0x0000FFFF +#define E1000_MDIC_REG_MASK 0x001F0000 +#define E1000_MDIC_REG_SHIFT 16 +#define E1000_MDIC_PHY_MASK 0x03E00000 +#define E1000_MDIC_PHY_SHIFT 21 +#define E1000_MDIC_OP_WRITE 0x04000000 +#define E1000_MDIC_OP_READ 0x08000000 +#define E1000_MDIC_READY 0x10000000 +#define E1000_MDIC_INT_EN 0x20000000 +#define E1000_MDIC_ERROR 0x40000000 + +/* LED Control */ +#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F +#define E1000_LEDCTL_LED0_MODE_SHIFT 0 +#define E1000_LEDCTL_LED0_IVRT 0x00000040 +#define E1000_LEDCTL_LED0_BLINK 0x00000080 +#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 +#define E1000_LEDCTL_LED1_MODE_SHIFT 8 +#define E1000_LEDCTL_LED1_IVRT 0x00004000 +#define E1000_LEDCTL_LED1_BLINK 0x00008000 +#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 +#define E1000_LEDCTL_LED2_MODE_SHIFT 16 +#define E1000_LEDCTL_LED2_IVRT 0x00400000 +#define E1000_LEDCTL_LED2_BLINK 0x00800000 +#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 +#define E1000_LEDCTL_LED3_MODE_SHIFT 24 +#define E1000_LEDCTL_LED3_IVRT 0x40000000 +#define E1000_LEDCTL_LED3_BLINK 0x80000000 + +#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 +#define E1000_LEDCTL_MODE_LINK_100_1000 0x1 +#define E1000_LEDCTL_MODE_LINK_UP 0x2 +#define E1000_LEDCTL_MODE_ACTIVITY 0x3 +#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 +#define E1000_LEDCTL_MODE_LINK_10 0x5 +#define E1000_LEDCTL_MODE_LINK_100 0x6 +#define E1000_LEDCTL_MODE_LINK_1000 0x7 +#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 +#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 +#define E1000_LEDCTL_MODE_COLLISION 0xA +#define E1000_LEDCTL_MODE_BUS_SPEED 0xB +#define E1000_LEDCTL_MODE_BUS_SIZE 0xC +#define E1000_LEDCTL_MODE_PAUSED 0xD +#define E1000_LEDCTL_MODE_LED_ON 0xE +#define E1000_LEDCTL_MODE_LED_OFF 0xF + +/* Receive Address */ +#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ + +/* Interrupt Cause Read */ +#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ +#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ +#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ +#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ +#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ +#define E1000_ICR_RXO 0x00000040 /* rx overrun */ +#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ +#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ +#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ +#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ +#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ +#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ +#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ +#define E1000_ICR_TXD_LOW 0x00008000 +#define E1000_ICR_SRPD 0x00010000 + +/* Interrupt Cause Set */ +#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_ICS_SRPD E1000_ICR_SRPD + +/* Interrupt Mask Set */ +#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_IMS_SRPD E1000_ICR_SRPD + +/* Interrupt Mask Clear */ +#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ +#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ +#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ +#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ +#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ +#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ +#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ +#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW +#define E1000_IMC_SRPD E1000_ICR_SRPD + +/* Receive Control */ +#define E1000_RCTL_RST 0x00000001 /* Software reset */ +#define E1000_RCTL_EN 0x00000002 /* enable */ +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ +#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ +#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ +#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ +#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ +#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ +#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ +#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ +#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ +#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ +#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ +/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ +#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ +#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ +#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ +#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ +/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ +#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ +#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ +#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ +#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ +#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ +#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ + +/* Receive Descriptor */ +#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ +#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ +#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ +#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ +#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ + +/* Flow Control */ +#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ +#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ +#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ +#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ + +/* Receive Descriptor Control */ +#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ +#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ +#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ +#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ + +/* Transmit Descriptor Control */ +#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */ +#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */ +#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */ +#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ +#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ +#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ + +/* Transmit Configuration Word */ +#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ +#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ +#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ +#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ +#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ +#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ +#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ +#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ +#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ +#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ + +/* Receive Configuration Word */ +#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ +#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ +#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ +#define E1000_RXCW_CC 0x10000000 /* Receive config change */ +#define E1000_RXCW_C 0x20000000 /* Receive config */ +#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ +#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ + +/* Transmit Control */ +#define E1000_TCTL_RST 0x00000001 /* software reset */ +#define E1000_TCTL_EN 0x00000002 /* enable tx */ +#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ +#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ +#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ +#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ +#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ +#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ + +/* Receive Checksum Control */ +#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ +#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ +#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ +#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ + +/* Definitions for power management and wakeup registers */ +/* Wake Up Control */ +#define E1000_WUC_APME 0x00000001 /* APM Enable */ +#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ +#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ +#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ + +/* Wake Up Filter Control */ +#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ +#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ +#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ +#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ +#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ +#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ +#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ +#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ +#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ +#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ +#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ +#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ +#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ +#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ +#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ + +/* Wake Up Status */ +#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ +#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ +#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ +#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ +#define E1000_WUS_BC 0x00000010 /* Broadcast Received */ +#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ +#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ +#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ +#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ +#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ +#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ +#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ +#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ + +/* Management Control */ +#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ +#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ +#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ +#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ +#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ +#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ +#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ +#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ +#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ +#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery + * Filtering */ +#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ +#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ +#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ +#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ +#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ +#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ +#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ +#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ +#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ + +#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ +#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ + +/* Wake Up Packet Length */ +#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ + +#define E1000_MDALIGN 4096 + +/* EEPROM Commands */ +#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */ +#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */ +#define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */ +#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */ +#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */ + +/* EEPROM Word Offsets */ +#define EEPROM_COMPAT 0x0003 +#define EEPROM_ID_LED_SETTINGS 0x0004 +#define EEPROM_INIT_CONTROL1_REG 0x000A +#define EEPROM_INIT_CONTROL2_REG 0x000F +#define EEPROM_FLASH_VERSION 0x0032 +#define EEPROM_CHECKSUM_REG 0x003F + +/* Word definitions for ID LED Settings */ +#define ID_LED_RESERVED_0000 0x0000 +#define ID_LED_RESERVED_FFFF 0xFFFF +#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ + (ID_LED_OFF1_OFF2 << 8) | \ + (ID_LED_DEF1_DEF2 << 4) | \ + (ID_LED_DEF1_DEF2)) +#define ID_LED_DEF1_DEF2 0x1 +#define ID_LED_DEF1_ON2 0x2 +#define ID_LED_DEF1_OFF2 0x3 +#define ID_LED_ON1_DEF2 0x4 +#define ID_LED_ON1_ON2 0x5 +#define ID_LED_ON1_OFF2 0x6 +#define ID_LED_OFF1_DEF2 0x7 +#define ID_LED_OFF1_ON2 0x8 +#define ID_LED_OFF1_OFF2 0x9 + +/* Mask bits for fields in Word 0x03 of the EEPROM */ +#define EEPROM_COMPAT_SERVER 0x0400 +#define EEPROM_COMPAT_CLIENT 0x0200 + +/* Mask bits for fields in Word 0x0a of the EEPROM */ +#define EEPROM_WORD0A_ILOS 0x0010 +#define EEPROM_WORD0A_SWDPIO 0x01E0 +#define EEPROM_WORD0A_LRST 0x0200 +#define EEPROM_WORD0A_FD 0x0400 +#define EEPROM_WORD0A_66MHZ 0x0800 + +/* Mask bits for fields in Word 0x0f of the EEPROM */ +#define EEPROM_WORD0F_PAUSE_MASK 0x3000 +#define EEPROM_WORD0F_PAUSE 0x1000 +#define EEPROM_WORD0F_ASM_DIR 0x2000 +#define EEPROM_WORD0F_ANE 0x0800 +#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 + +/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ +#define EEPROM_SUM 0xBABA + +/* EEPROM Map defines (WORD OFFSETS)*/ +#define EEPROM_NODE_ADDRESS_BYTE_0 0 +#define EEPROM_PBA_BYTE_1 8 + +/* EEPROM Map Sizes (Byte Counts) */ +#define PBA_SIZE 4 + +/* Collision related configuration parameters */ +#define E1000_COLLISION_THRESHOLD 16 +#define E1000_CT_SHIFT 4 +#define E1000_COLLISION_DISTANCE 64 +#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE +#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE +#define E1000_GB_HDX_COLLISION_DISTANCE 512 +#define E1000_COLD_SHIFT 12 + +/* The number of Transmit and Receive Descriptors must be a multiple of 8 */ +#define REQ_TX_DESCRIPTOR_MULTIPLE 8 +#define REQ_RX_DESCRIPTOR_MULTIPLE 8 + +/* Default values for the transmit IPG register */ +#define DEFAULT_82542_TIPG_IPGT 10 +#define DEFAULT_82543_TIPG_IPGT_FIBER 9 +#define DEFAULT_82543_TIPG_IPGT_COPPER 8 + +#define E1000_TIPG_IPGT_MASK 0x000003FF +#define E1000_TIPG_IPGR1_MASK 0x000FFC00 +#define E1000_TIPG_IPGR2_MASK 0x3FF00000 + +#define DEFAULT_82542_TIPG_IPGR1 2 +#define DEFAULT_82543_TIPG_IPGR1 8 +#define E1000_TIPG_IPGR1_SHIFT 10 + +#define DEFAULT_82542_TIPG_IPGR2 10 +#define DEFAULT_82543_TIPG_IPGR2 6 +#define E1000_TIPG_IPGR2_SHIFT 20 + +#define E1000_TXDMAC_DPP 0x00000001 + +/* Adaptive IFS defines */ +#define TX_THRESHOLD_START 8 +#define TX_THRESHOLD_INCREMENT 10 +#define TX_THRESHOLD_DECREMENT 1 +#define TX_THRESHOLD_STOP 190 +#define TX_THRESHOLD_DISABLE 0 +#define TX_THRESHOLD_TIMER_MS 10000 +#define MIN_NUM_XMITS 1000 +#define IFS_MAX 80 +#define IFS_STEP 10 +#define IFS_MIN 40 +#define IFS_RATIO 4 + +/* PBA constants */ +#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ +#define E1000_PBA_24K 0x0018 +#define E1000_PBA_40K 0x0028 +#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ + +/* Flow Control Constants */ +#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 +#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 +#define FLOW_CONTROL_TYPE 0x8808 + +/* The historical defaults for the flow control values are given below. */ +#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ +#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ +#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ + +/* Flow Control High-Watermark: 43464 bytes */ +#define E1000_FC_HIGH_THRESH 0xA9C8 +/* Flow Control Low-Watermark: 43456 bytes */ +#define E1000_FC_LOW_THRESH 0xA9C0 +/* Flow Control Pause Time: 858 usec */ +#define E1000_FC_PAUSE_TIME 0x0680 + +/* PCIX Config space */ +#define PCIX_COMMAND_REGISTER 0xE6 +#define PCIX_STATUS_REGISTER_LO 0xE8 +#define PCIX_STATUS_REGISTER_HI 0xEA + +#define PCIX_COMMAND_MMRBC_MASK 0x000C +#define PCIX_COMMAND_MMRBC_SHIFT 0x2 +#define PCIX_STATUS_HI_MMRBC_MASK 0x0060 +#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 +#define PCIX_STATUS_HI_MMRBC_4K 0x3 +#define PCIX_STATUS_HI_MMRBC_2K 0x2 + +/* The number of bits that we need to shift right to move the "pause" + * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field + * in the TXCW register + */ +#define PAUSE_SHIFT 5 + +/* The number of bits that we need to shift left to move the "SWDPIO" + * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field + * in the CTRL register + */ +#define SWDPIO_SHIFT 17 + +/* The number of bits that we need to shift left to move the "SWDPIO_EXT" + * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The + * Extended CTRL register. + * in the CTRL register + */ +#define SWDPIO__EXT_SHIFT 4 + +/* The number of bits that we need to shift left to move the "ILOS" + * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field + * in the CTRL register + */ +#define ILOS_SHIFT 3 + +#define RECEIVE_BUFFER_ALIGN_SIZE (256) + +/* The number of milliseconds we wait for auto-negotiation to complete */ +#define LINK_UP_TIMEOUT 500 + +#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) + +/* The carrier extension symbol, as received by the NIC. */ +#define CARRIER_EXTENSION 0x0F + +/* TBI_ACCEPT macro definition: + * + * This macro requires: + * adapter = a pointer to struct e1000_hw + * status = the 8 bit status field of the RX descriptor with EOP set + * error = the 8 bit error field of the RX descriptor with EOP set + * length = the sum of all the length fields of the RX descriptors that + * make up the current frame + * last_byte = the last byte of the frame DMAed by the hardware + * max_frame_length = the maximum frame length we want to accept. + * min_frame_length = the minimum frame length we want to accept. + * + * This macro is a conditional that should be used in the interrupt + * handler's Rx processing routine when RxErrors have been detected. + * + * Typical use: + * ... + * if (TBI_ACCEPT) { + * accept_frame = TRUE; + * e1000_tbi_adjust_stats(adapter, MacAddress); + * frame_length--; + * } else { + * accept_frame = FALSE; + * } + * ... + */ + +#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \ + ((adapter)->tbi_compatibility_on && \ + (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ + ((last_byte) == CARRIER_EXTENSION) && \ + (((status) & E1000_RXD_STAT_VP) ? \ + (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ + ((length) <= ((adapter)->max_frame_size + 1))) : \ + (((length) > (adapter)->min_frame_size) && \ + ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) + +/* Structures, enums, and macros for the PHY */ + +/* Bit definitions for the Management Data IO (MDIO) and Management Data + * Clock (MDC) pins in the Device Control Register. + */ +#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 +#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 +#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 +#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 +#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 +#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 +#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR +#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA + +/* PHY 1000 MII Register/Bit Definitions */ +/* PHY Registers defined by IEEE */ +#define PHY_CTRL 0x00 /* Control Register */ +#define PHY_STATUS 0x01 /* Status Regiser */ +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ + +/* M88E1000 Specific Registers */ +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ +#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ +#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ +#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ + +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ + +/* PHY Control Register */ +#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ +#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ +#define MII_CR_POWER_DOWN 0x0800 /* Power down */ +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ +#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ + +/* PHY Status Register */ +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ + +/* Autoneg Advertisement Register */ +#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ +#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ +#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ +#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ +#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ +#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ +#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ +#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ +#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ +#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + +/* Link Partner Ability Register (Base Page) */ +#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ +#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ +#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ +#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ +#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ +#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ +#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ +#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ +#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ +#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ +#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ + +/* Autoneg Expansion Register */ +#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ +#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ +#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ +#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */ + +/* Next Page TX Register */ +#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges + * of different NP + */ +#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg + * 0 = cannot comply with msg + */ +#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow + * 0 = sending last NP + */ + +/* Link Partner Next Page Register */ +#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges + * of different NP + */ +#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg + * 0 = cannot comply with msg + */ +#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ +#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow + * 0 = sending last NP + */ + +/* 1000BASE-T Control Register */ +#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ +#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ +#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ +#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ + /* 0=DTE device */ +#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ + /* 0=Configure PHY as Slave */ +#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ + /* 0=Automatic Master/Slave config */ +#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ +#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ +#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ +#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ +#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ + +/* 1000BASE-T Status Register */ +#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ +#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ +#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ +#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ +#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ +#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ +#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ +#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 +#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 + +/* Extended Status Register */ +#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ +#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ +#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ +#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ + +#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ +#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ + +#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ + /* (0=enable, 1=disable) */ + +/* M88E1000 PHY Specific Control Register */ +#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ +#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ +#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ +#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, + * 0=CLK125 toggling + */ +#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ + /* Manual MDI configuration */ +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ +#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, + * 100BASE-TX/10BASE-T: + * MDI Mode + */ +#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled + * all speeds. + */ +#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 + /* 1=Enable Extended 10BASE-T distance + * (Lower 10BASE-T RX Threshold) + * 0=Normal 10BASE-T RX Threshold */ +#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 + /* 1=5-Bit interface in 100BASE-TX + * 0=MII interface in 100BASE-TX */ +#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ +#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ +#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ + +#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 +#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 +#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 + +/* M88E1000 PHY Specific Status Register */ +#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ +#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ +#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ +#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; + * 3=110-140M;4=>140M */ +#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ +#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ +#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ +#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ +#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ +#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ +#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ +#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ + +#define M88E1000_PSSR_REV_POLARITY_SHIFT 1 +#define M88E1000_PSSR_MDIX_SHIFT 6 +#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 + +/* M88E1000 Extended PHY Specific Control Register */ +#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ +#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. + * Will assert lost lock and bring + * link down if idle not seen + * within 1ms in 1000BASE-T + */ +/* Number of times we will attempt to autonegotiate before downshifting if we + * are the master */ +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 +#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 +/* Number of times we will attempt to autonegotiate before downshifting if we + * are the slave */ +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 +#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 +#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ + +/* Bit definitions for valid PHY IDs. */ +#define M88E1000_E_PHY_ID 0x01410C50 +#define M88E1000_I_PHY_ID 0x01410C30 +#define M88E1011_I_PHY_ID 0x01410C20 +#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID +#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID + +/* Miscellaneous PHY bit definitions. */ +#define PHY_PREAMBLE 0xFFFFFFFF +#define PHY_SOF 0x01 +#define PHY_OP_READ 0x02 +#define PHY_OP_WRITE 0x01 +#define PHY_TURNAROUND 0x02 +#define PHY_PREAMBLE_SIZE 32 +#define MII_CR_SPEED_1000 0x0040 +#define MII_CR_SPEED_100 0x2000 +#define MII_CR_SPEED_10 0x0000 +#define E1000_PHY_ADDRESS 0x01 +#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ +#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ +#define PHY_REVISION_MASK 0xFFFFFFF0 +#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ +#define REG4_SPEED_MASK 0x01E0 +#define REG9_SPEED_MASK 0x0300 +#define ADVERTISE_10_HALF 0x0001 +#define ADVERTISE_10_FULL 0x0002 +#define ADVERTISE_100_HALF 0x0004 +#define ADVERTISE_100_FULL 0x0008 +#define ADVERTISE_1000_HALF 0x0010 +#define ADVERTISE_1000_FULL 0x0020 +#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ + +#endif /* _E1000_HW_H_ */ diff --git a/drivers/eepro100.c b/drivers/eepro100.c new file mode 100644 index 000000000..04c17f69f --- /dev/null +++ b/drivers/eepro100.c @@ -0,0 +1,948 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#undef DEBUG + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_EEPRO100) + + /* Ethernet chip registers. + */ +#define SCBStatus 0 /* Rx/Command Unit Status *Word* */ +#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ +#define SCBCmd 2 /* Rx/Command Unit Command *Word* */ +#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ +#define SCBPointer 4 /* General purpose pointer. */ +#define SCBPort 8 /* Misc. commands and operands. */ +#define SCBflash 12 /* Flash memory control. */ +#define SCBeeprom 14 /* EEPROM memory control. */ +#define SCBCtrlMDI 16 /* MDI interface control. */ +#define SCBEarlyRx 20 /* Early receive byte count. */ +#define SCBGenControl 28 /* 82559 General Control Register */ +#define SCBGenStatus 29 /* 82559 General Status register */ + + /* 82559 SCB status word defnitions + */ +#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ +#define SCB_STATUS_FR 0x4000 /* frame received */ +#define SCB_STATUS_CNA 0x2000 /* CU left active state */ +#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ +#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ +#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ +#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ + +#define SCB_INTACK_MASK 0xFD00 /* all the above */ + +#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) +#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) + + /* System control block commands + */ +/* CU Commands */ +#define CU_NOP 0x0000 +#define CU_START 0x0010 +#define CU_RESUME 0x0020 +#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ +#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ +#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ +#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ + +/* RUC Commands */ +#define RUC_NOP 0x0000 +#define RUC_START 0x0001 +#define RUC_RESUME 0x0002 +#define RUC_ABORT 0x0004 +#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ +#define RUC_RESUMENR 0x0007 + +#define CU_CMD_MASK 0x00f0 +#define RU_CMD_MASK 0x0007 + +#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ +#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ + +#define CU_STATUS_MASK 0x00C0 +#define RU_STATUS_MASK 0x003C + +#define RU_STATUS_IDLE (0<<2) +#define RU_STATUS_SUS (1<<2) +#define RU_STATUS_NORES (2<<2) +#define RU_STATUS_READY (4<<2) +#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) +#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) +#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) + + /* 82559 Port interface commands. + */ +#define I82559_RESET 0x00000000 /* Software reset */ +#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ +#define I82559_SELECTIVE_RESET 0x00000002 +#define I82559_DUMP 0x00000003 +#define I82559_DUMP_WAKEUP 0x00000007 + + /* 82559 Eeprom interface. + */ +#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ +#define EE_CS 0x02 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x01 +#define EE_WRITE_1 0x05 +#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ +#define EE_ENB (0x4800 | EE_CS) +#define EE_CMD_BITS 3 +#define EE_DATA_BITS 16 + + /* The EEPROM commands include the alway-set leading bit. + */ +#define EE_EWENB_CMD (4 << addr_len) +#define EE_WRITE_CMD (5 << addr_len) +#define EE_READ_CMD (6 << addr_len) +#define EE_ERASE_CMD (7 << addr_len) + + /* Receive frame descriptors. + */ +struct RxFD { + volatile u16 status; + volatile u16 control; + volatile u32 link; /* struct RxFD * */ + volatile u32 rx_buf_addr; /* void * */ + volatile u32 count; + + volatile u8 data[PKTSIZE_ALIGN]; +}; + +#define RFD_STATUS_C 0x8000 /* completion of received frame */ +#define RFD_STATUS_OK 0x2000 /* frame received with no errors */ + +#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ +#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ +#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ +#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ + +#define RFD_COUNT_MASK 0x3fff +#define RFD_COUNT_F 0x4000 +#define RFD_COUNT_EOF 0x8000 + +#define RFD_RX_CRC 0x0800 /* crc error */ +#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ +#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ +#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ +#define RFD_RX_SHORT 0x0080 /* short frame error */ +#define RFD_RX_LENGTH 0x0020 +#define RFD_RX_ERROR 0x0010 /* receive error */ +#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ +#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ +#define RFD_RX_TCO 0x0001 /* TCO indication */ + + /* Transmit frame descriptors + */ +struct TxFD { /* Transmit frame descriptor set. */ + volatile u16 status; + volatile u16 command; + volatile u32 link; /* void * */ + volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ + volatile s32 count; + + volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ + volatile s32 tx_buf_size0; /* Length of Tx frame. */ + volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ + volatile s32 tx_buf_size1; /* Length of Tx frame. */ +}; + +#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ +#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ +#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ +#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ +#define TxCB_CMD_S 0x4000 /* suspend on completion */ +#define TxCB_CMD_EL 0x8000 /* last command block in CBL */ + +#define TxCB_COUNT_MASK 0x3fff +#define TxCB_COUNT_EOF 0x8000 + + /* The Speedo3 Rx and Tx frame/buffer descriptors. + */ +struct descriptor { /* A generic descriptor. */ + volatile u16 status; + volatile u16 command; + volatile u32 link; /* struct descriptor * */ + + unsigned char params[0]; +}; + +#define CFG_CMD_EL 0x8000 +#define CFG_CMD_SUSPEND 0x4000 +#define CFG_CMD_INT 0x2000 +#define CFG_CMD_IAS 0x0001 /* individual address setup */ +#define CFG_CMD_CONFIGURE 0x0002 /* configure */ + +#define CFG_STATUS_C 0x8000 +#define CFG_STATUS_OK 0x2000 + + /* Misc. + */ +#define NUM_RX_DESC PKTBUFSRX +#define NUM_TX_DESC 1 /* Number of TX descriptors */ + +#define TOUT_LOOP 1000000 + +#define ETH_ALEN 6 + +static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ +static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ +static int rx_next; /* RX descriptor ring pointer */ +static int tx_next; /* TX descriptor ring pointer */ +static int tx_threshold; + +/* + * The parameters for a CmdConfigure operation. + * There are so many options that it would be difficult to document + * each bit. We mostly use the default or recommended settings. + */ +static const char i82557_config_cmd[] = { + 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */ + 0, 0x2E, 0, 0x60, 0, + 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */ + 0x3f, 0x05, +}; +static const char i82558_config_cmd[] = { + 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ + 0, 0x2E, 0, 0x60, 0x08, 0x88, + 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ + 0x31, 0x05, +}; + +static void init_rx_ring (struct eth_device *dev); +static void purge_tx_ring (struct eth_device *dev); + +static void read_hw_addr (struct eth_device *dev, bd_t * bis); + +static int eepro100_init (struct eth_device *dev, bd_t * bis); +static int eepro100_send (struct eth_device *dev, volatile void *packet, + int length); +static int eepro100_recv (struct eth_device *dev); +static void eepro100_halt (struct eth_device *dev); + +#if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460) +#define bus_to_phys(a) (a) +#define phys_to_bus(a) (a) +#else +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) +#endif + +static inline int INW (struct eth_device *dev, u_long addr) +{ + return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase)); +} + +static inline void OUTW (struct eth_device *dev, int command, u_long addr) +{ + *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command); +} + +static inline void OUTL (struct eth_device *dev, int command, u_long addr) +{ + *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command); +} + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +static inline int INL (struct eth_device *dev, u_long addr) +{ + return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); +} + +static int get_phyreg (struct eth_device *dev, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + int cmd; + int timeout = 50; + + /* read requested data */ + cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); + OUTL (dev, cmd, SCBCtrlMDI); + + do { + udelay(1000); + cmd = INL (dev, SCBCtrlMDI); + } while (!(cmd & (1 << 28)) && (--timeout)); + + if (timeout == 0) + return -1; + + *value = (unsigned short) (cmd & 0xffff); + + return 0; +} + +static int set_phyreg (struct eth_device *dev, unsigned char addr, + unsigned char reg, unsigned short value) +{ + int cmd; + int timeout = 50; + + /* write requested data */ + cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); + OUTL (dev, cmd | value, SCBCtrlMDI); + + while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) + udelay(1000); + + if (timeout == 0) + return -1; + + return 0; +} + +/* Check if given phyaddr is valid, i.e. there is a PHY connected. + * Do this by checking model value field from ID2 register. + */ +static struct eth_device* verify_phyaddr (char *devname, unsigned char addr) +{ + struct eth_device *dev; + unsigned short value; + unsigned char model; + + dev = eth_get_dev_by_name(devname); + if (dev == NULL) { + printf("%s: no such device\n", devname); + return NULL; + } + + /* read id2 register */ + if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) { + printf("%s: mii read timeout!\n", devname); + return NULL; + } + + /* get model */ + model = (unsigned char)((value >> 4) & 0x003f); + + if (model == 0) { + printf("%s: no PHY at address %d\n", devname, addr); + return NULL; + } + + return dev; +} + +static int eepro100_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + struct eth_device *dev; + + dev = verify_phyaddr(devname, addr); + if (dev == NULL) + return -1; + + if (get_phyreg(dev, addr, reg, value) != 0) { + printf("%s: mii read timeout!\n", devname); + return -1; + } + + return 0; +} + +static int eepro100_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct eth_device *dev; + + dev = verify_phyaddr(devname, addr); + if (dev == NULL) + return -1; + + if (set_phyreg(dev, addr, reg, value) != 0) { + printf("%s: mii write timeout!\n", devname); + return -1; + } + + return 0; +} + +#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */ + +/* Wait for the chip get the command. +*/ +static int wait_for_eepro100 (struct eth_device *dev) +{ + int i; + + for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { + if (i >= TOUT_LOOP) { + return 0; + } + } + + return 1; +} + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER}, + {} +}; + +int eepro100_initialize (bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase, status; + int idx = 0; + + while (1) { + /* Find PCI device + */ + if ((devno = pci_find_devices (supported, idx++)) < 0) { + break; + } + + pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0xf; + +#ifdef DEBUG + printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", + iobase); +#endif + + pci_write_config_dword (devno, + PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Check if I/O accesses and Bus Mastering are enabled. + */ + pci_read_config_dword (devno, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { + printf ("Error: Can not enable MEM access.\n"); + continue; + } + + if (!(status & PCI_COMMAND_MASTER)) { + printf ("Error: Can not enable Bus Mastering.\n"); + continue; + } + + dev = (struct eth_device *) malloc (sizeof *dev); + + sprintf (dev->name, "i82559#%d", card_number); + dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ + dev->iobase = bus_to_phys (iobase); + dev->init = eepro100_init; + dev->halt = eepro100_halt; + dev->send = eepro100_send; + dev->recv = eepro100_recv; + + eth_register (dev); + +#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + /* register mii command access routines */ + miiphy_register(dev->name, + eepro100_miiphy_read, eepro100_miiphy_write); +#endif + + card_number++; + + /* Set the latency timer for value. + */ + pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); + + udelay (10 * 1000); + + read_hw_addr (dev, bis); + } + + return card_number; +} + + +static int eepro100_init (struct eth_device *dev, bd_t * bis) +{ + int i, status = 0; + int tx_cur; + struct descriptor *ias_cmd, *cfg_cmd; + + /* Reset the ethernet controller + */ + OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); + udelay (20); + + OUTL (dev, I82559_RESET, SCBPort); + udelay (20); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); + + /* Initialize Rx and Tx rings. + */ + init_rx_ring (dev); + purge_tx_ring (dev); + + /* Tell the adapter where the RX ring is located. + */ + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); + OUTW (dev, SCB_M | RUC_START, SCBCmd); + + /* Send the Configure frame */ + tx_cur = tx_next; + tx_next = ((tx_next + 1) % NUM_TX_DESC); + + cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; + cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE)); + cfg_cmd->status = 0; + cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); + + memcpy (cfg_cmd->params, i82558_config_cmd, + sizeof (i82558_config_cmd)); + + if (!wait_for_eepro100 (dev)) { + printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); + OUTW (dev, SCB_M | CU_START, SCBCmd); + + for (i = 0; + !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + printf ("%s: Tx error buffer not ready\n", dev->name); + goto Done; + } + } + + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); + goto Done; + } + + /* Send the Individual Address Setup frame + */ + tx_cur = tx_next; + tx_next = ((tx_next + 1) % NUM_TX_DESC); + + ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; + ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS)); + ias_cmd->status = 0; + ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); + + memcpy (ias_cmd->params, dev->enetaddr, 6); + + /* Tell the adapter where the TX ring is located. + */ + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); + OUTW (dev, SCB_M | CU_START, SCBCmd); + + for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + printf ("%s: Tx error buffer not ready\n", + dev->name); + goto Done; + } + } + + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); + goto Done; + } + + status = 1; + + Done: + return status; +} + +static int eepro100_send (struct eth_device *dev, volatile void *packet, int length) +{ + int i, status = -1; + int tx_cur; + + if (length <= 0) { + printf ("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + + tx_cur = tx_next; + tx_next = (tx_next + 1) % NUM_TX_DESC; + + tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | + TxCB_CMD_SF | + TxCB_CMD_S | + TxCB_CMD_EL ); + tx_ring[tx_cur].status = 0; + tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); + tx_ring[tx_cur].link = + cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); + tx_ring[tx_cur].tx_desc_addr = + cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0)); + tx_ring[tx_cur].tx_buf_addr0 = + cpu_to_le32 (phys_to_bus ((u_long) packet)); + tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); + + if (!wait_for_eepro100 (dev)) { + printf ("%s: Tx error ethernet controller not ready.\n", + dev->name); + goto Done; + } + + /* Send the packet. + */ + OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); + OUTW (dev, SCB_M | CU_START, SCBCmd); + + for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C); + i++) { + if (i >= TOUT_LOOP) { + printf ("%s: Tx error buffer not ready\n", dev->name); + goto Done; + } + } + + if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) { + printf ("TX error status = 0x%08X\n", + le16_to_cpu (tx_ring[tx_cur].status)); + goto Done; + } + + status = length; + + Done: + return status; +} + +static int eepro100_recv (struct eth_device *dev) +{ + u16 status, stat; + int rx_prev, length = 0; + + stat = INW (dev, SCBStatus); + OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); + + for (;;) { + status = le16_to_cpu (rx_ring[rx_next].status); + + if (!(status & RFD_STATUS_C)) { + break; + } + + /* Valid frame status. + */ + if ((status & RFD_STATUS_OK)) { + /* A valid frame received. + */ + length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; + + /* Pass the packet up to the protocol + * layers. + */ + NetReceive (rx_ring[rx_next].data, length); + } else { + /* There was an error. + */ + printf ("RX error status = 0x%08X\n", status); + } + + rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); + rx_ring[rx_next].status = 0; + rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); + + rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; + rx_ring[rx_prev].control = 0; + + /* Update entry information. + */ + rx_next = (rx_next + 1) % NUM_RX_DESC; + } + + if (stat & SCB_STATUS_RNR) { + + printf ("%s: Receiver is not ready, restart it !\n", dev->name); + + /* Reinitialize Rx ring. + */ + init_rx_ring (dev); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not restart ethernet controller.\n"); + goto Done; + } + + OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); + OUTW (dev, SCB_M | RUC_START, SCBCmd); + } + + Done: + return length; +} + +static void eepro100_halt (struct eth_device *dev) +{ + /* Reset the ethernet controller + */ + OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); + udelay (20); + + OUTL (dev, I82559_RESET, SCBPort); + udelay (20); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); + + if (!wait_for_eepro100 (dev)) { + printf ("Error: Can not reset ethernet controller.\n"); + goto Done; + } + OUTL (dev, 0, SCBPointer); + OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); + + Done: + return; +} + + /* SROM Read. + */ +static int read_eeprom (struct eth_device *dev, int location, int addr_len) +{ + unsigned short retval = 0; + int read_cmd = location | EE_READ_CMD; + int i; + + OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); + OUTW (dev, EE_ENB, SCBeeprom); + + /* Shift the read command bits out. */ + for (i = 12; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + + OUTW (dev, EE_ENB | dataval, SCBeeprom); + udelay (1); + OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay (1); + } + OUTW (dev, EE_ENB, SCBeeprom); + + for (i = 15; i >= 0; i--) { + OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); + udelay (1); + retval = (retval << 1) | + ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); + OUTW (dev, EE_ENB, SCBeeprom); + udelay (1); + } + + /* Terminate the EEPROM access. */ + OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); + return retval; +} + +#ifdef CONFIG_EEPRO100_SROM_WRITE +int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data) +{ + unsigned short dataval; + int enable_cmd = 0x3f | EE_EWENB_CMD; + int write_cmd = location | EE_WRITE_CMD; + int i; + unsigned long datalong, tmplong; + + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB, SCBeeprom); + + /* Shift the enable command bits out. */ + for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) + { + dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); + } + + OUTW(dev, EE_ENB, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB, SCBeeprom); + + + /* Shift the write command bits out. */ + for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) + { + dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); + } + + /* Write the data */ + datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8)); + + for (i = 0; i< EE_DATA_BITS; i++) + { + /* Extract and move data bit to bit DI */ + dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0; + + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + + datalong = datalong << 1; /* Adjust significant data bit*/ + } + + /* Finish up command (toggle CS) */ + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + udelay(1); /* delay for more than 250 ns */ + OUTW(dev, EE_ENB, SCBeeprom); + + /* Wait for programming ready (D0 = 1) */ + tmplong = 10; + do + { + dataval = INW(dev, SCBeeprom); + if (dataval & EE_DATA_READ) + break; + udelay(10000); + } + while (-- tmplong); + + if (tmplong == 0) + { + printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); + return -1; + } + + /* Terminate the EEPROM access. */ + OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); + + return 0; +} +#endif + +static void init_rx_ring (struct eth_device *dev) +{ + int i; + + for (i = 0; i < NUM_RX_DESC; i++) { + rx_ring[i].status = 0; + rx_ring[i].control = + (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0; + rx_ring[i].link = + cpu_to_le32 (phys_to_bus + ((u32) & rx_ring[(i + 1) % NUM_RX_DESC])); + rx_ring[i].rx_buf_addr = 0xffffffff; + rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); + } + + rx_next = 0; +} + +static void purge_tx_ring (struct eth_device *dev) +{ + int i; + + tx_next = 0; + tx_threshold = 0x01208000; + + for (i = 0; i < NUM_TX_DESC; i++) { + tx_ring[i].status = 0; + tx_ring[i].command = 0; + tx_ring[i].link = 0; + tx_ring[i].tx_desc_addr = 0; + tx_ring[i].count = 0; + + tx_ring[i].tx_buf_addr0 = 0; + tx_ring[i].tx_buf_size0 = 0; + tx_ring[i].tx_buf_addr1 = 0; + tx_ring[i].tx_buf_size1 = 0; + } +} + +static void read_hw_addr (struct eth_device *dev, bd_t * bis) +{ + u16 eeprom[0x40]; + u16 sum = 0; + int i, j; + int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; + + for (j = 0, i = 0; i < 0x40; i++) { + u16 value = read_eeprom (dev, i, addr_len); + + eeprom[i] = value; + sum += value; + if (i < 3) { + dev->enetaddr[j++] = value; + dev->enetaddr[j++] = value >> 8; + } + } + + if (sum != 0xBABA) { + memset (dev->enetaddr, 0, ETH_ALEN); +#ifdef DEBUG + printf ("%s: Invalid EEPROM checksum %#4.4x, " + "check settings before activating this device!\n", + dev->name, sum); +#endif + } +} + +#endif diff --git a/drivers/i8042.c b/drivers/i8042.c new file mode 100644 index 000000000..22c2a4e3a --- /dev/null +++ b/drivers/i8042.c @@ -0,0 +1,674 @@ +/* + * (C) Copyright 2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* i8042.c - Intel 8042 keyboard driver routines */ + +/* includes */ + +#include + +#ifdef CONFIG_I8042_KBD + +#ifdef CONFIG_USE_CPCIDVI +extern u8 gt_cpcidvi_in8(u32 offset); +extern void gt_cpcidvi_out8(u32 offset, u8 data); + +#define in8(a) gt_cpcidvi_in8(a) +#define out8(a, b) gt_cpcidvi_out8(a,b) +#endif + +#include + +/* defines */ + +#ifdef CONFIG_CONSOLE_CURSOR +extern void console_cursor (int state); +static int blinkCount = CFG_CONSOLE_BLINK_COUNT; +static int cursor_state = 0; +#endif + +/* locals */ + +static int kbd_input = -1; /* no input yet */ +static int kbd_mapping = KBD_US; /* default US keyboard */ +static int kbd_flags = NORMAL; /* after reset */ +static int kbd_state = 0; /* unshift code */ + +static void kbd_conv_char (unsigned char scan_code); +static void kbd_led_set (void); +static void kbd_normal (unsigned char scan_code); +static void kbd_shift (unsigned char scan_code); +static void kbd_ctrl (unsigned char scan_code); +static void kbd_num (unsigned char scan_code); +static void kbd_caps (unsigned char scan_code); +static void kbd_scroll (unsigned char scan_code); +static void kbd_alt (unsigned char scan_code); +static int kbd_input_empty (void); +static int kbd_reset (void); + +static unsigned char kbd_fct_map [144] = + { /* kbd_fct_map table for scan code */ + 0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */ + AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */ + AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */ + AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */ + AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */ + AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */ + ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */ + ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */ + 0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */ + AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */ + AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */ + }; + +static unsigned char kbd_key_map [2][5][144] = + { + { /* US keyboard */ + { /* unshift code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ + 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ + '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* shift code */ + 0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */ + '&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */ + 'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */ + '"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */ + 'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* control code */ + 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ + 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ + 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ + 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ + 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ + 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ + 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ + 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + }, + { /* non numeric code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */ + 'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */ + '\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ + 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ + 'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* right alt mode - not used in US keyboard */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + } + }, + { /* german keyboard */ + { /* unshift code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ + 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ + 0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* shift code */ + 0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */ + '/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */ + 'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */ + 'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */ + 0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */ + 'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */ + '8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */ + '2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* control code */ + 0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */ + 0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */ + 0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */ + 0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */ + 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */ + 0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */ + 0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */ + 0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + }, + { /* non numeric code */ + 0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */ + '7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */ + 'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */ + 'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */ + 0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */ + 'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */ + ' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */ + 0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */ + 'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */ + 'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */ + 0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */ + '\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */ + 0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */ + }, + { /* Right alt mode - is used in German keyboard */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */ + '{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */ + '@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */ + 0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */ + 0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */ + } + } + }; + +static unsigned char ext_key_map [] = + { + 0x1c, /* keypad enter */ + 0x1d, /* right control */ + 0x35, /* keypad slash */ + 0x37, /* print screen */ + 0x38, /* right alt */ + 0x46, /* break */ + 0x47, /* editpad home */ + 0x48, /* editpad up */ + 0x49, /* editpad pgup */ + 0x4b, /* editpad left */ + 0x4d, /* editpad right */ + 0x4f, /* editpad end */ + 0x50, /* editpad dn */ + 0x51, /* editpad pgdn */ + 0x52, /* editpad ins */ + 0x53, /* editpad del */ + 0x00 /* map end */ + }; + +/******************************************************************************* + * + * i8042_kbd_init - reset keyboard and init state flags + */ +int i8042_kbd_init (void) +{ + int keymap, try; + char *penv; + +#ifdef CONFIG_USE_CPCIDVI + if ((penv = getenv ("console")) != NULL) { + if (strncmp (penv, "serial", 7) == 0) { + return -1; + } + } +#endif + /* Init keyboard device (default US layout) */ + keymap = KBD_US; + if ((penv = getenv ("keymap")) != NULL) + { + if (strncmp (penv, "de", 3) == 0) + keymap = KBD_GER; + } + + for (try = 0; try < KBD_RESET_TRIES; try++) + { + if (kbd_reset() == 0) + { + kbd_mapping = keymap; + kbd_flags = NORMAL; + kbd_state = 0; + kbd_led_set(); + return 0; + } + } + return -1; +} + + +/******************************************************************************* + * + * i8042_tstc - test if keyboard input is available + * option: cursor blinking if called in a loop + */ +int i8042_tstc (void) +{ + unsigned char scan_code = 0; + +#ifdef CONFIG_CONSOLE_CURSOR + if (--blinkCount == 0) + { + cursor_state ^= 1; + console_cursor (cursor_state); + blinkCount = CFG_CONSOLE_BLINK_COUNT; + udelay (10); + } +#endif + + if ((in8 (I8042_STATUS_REG) & 0x01) == 0) + return 0; + else + { + scan_code = in8 (I8042_DATA_REG); + if (scan_code == 0xfa) + return 0; + + kbd_conv_char(scan_code); + + if (kbd_input != -1) + return 1; + } + return 0; +} + + +/******************************************************************************* + * + * i8042_getc - wait till keyboard input is available + * option: turn on/off cursor while waiting + */ +int i8042_getc (void) +{ + int ret_chr; + unsigned char scan_code; + + while (kbd_input == -1) + { + while ((in8 (I8042_STATUS_REG) & 0x01) == 0) + { +#ifdef CONFIG_CONSOLE_CURSOR + if (--blinkCount==0) + { + cursor_state ^= 1; + console_cursor (cursor_state); + blinkCount = CFG_CONSOLE_BLINK_COUNT; + } + udelay (10); +#endif + } + + scan_code = in8 (I8042_DATA_REG); + + if (scan_code != 0xfa) + kbd_conv_char (scan_code); + } + ret_chr = kbd_input; + kbd_input = -1; + return ret_chr; +} + + +/******************************************************************************/ + +static void kbd_conv_char (unsigned char scan_code) +{ + if (scan_code == 0xe0) + { + kbd_flags |= EXT; + return; + } + + /* if high bit of scan_code, set break flag */ + if (scan_code & 0x80) + kbd_flags |= BRK; + else + kbd_flags &= ~BRK; + + if ((scan_code == 0xe1) || (kbd_flags & E1)) + { + if (scan_code == 0xe1) + { + kbd_flags ^= BRK; /* reset the break flag */ + kbd_flags ^= E1; /* bitwise EXOR with E1 flag */ + } + return; + } + + scan_code &= 0x7f; + + if (kbd_flags & EXT) + { + int i; + + kbd_flags ^= EXT; + for (i=0; ext_key_map[i]; i++) + { + if (ext_key_map[i] == scan_code) + { + scan_code = 0x80 + i; + break; + } + } + /* not found ? */ + if (!ext_key_map[i]) + return; + } + + switch (kbd_fct_map [scan_code]) + { + case AS: kbd_normal (scan_code); + break; + case SH: kbd_shift (scan_code); + break; + case CN: kbd_ctrl (scan_code); + break; + case NM: kbd_num (scan_code); + break; + case CP: kbd_caps (scan_code); + break; + case ST: kbd_scroll (scan_code); + break; + case AK: kbd_alt (scan_code); + break; + } + return; +} + + +/******************************************************************************/ + +static void kbd_normal (unsigned char scan_code) +{ + unsigned char chr; + + if ((kbd_flags & BRK) == NORMAL) + { + chr = kbd_key_map [kbd_mapping][kbd_state][scan_code]; + if ((chr == 0xff) || (chr == 0x00)) + { + return; + } + + /* if caps lock convert upper to lower */ + if (((kbd_flags & CAPS) == CAPS) && (chr >= 'a' && chr <= 'z')) + { + chr -= 'a' - 'A'; + } + kbd_input = chr; + } +} + + +/******************************************************************************/ + +static void kbd_shift (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == BRK) + { + kbd_state = AS; + kbd_flags &= (~SHIFT); + } + else + { + kbd_state = SH; + kbd_flags |= SHIFT; + } +} + + +/******************************************************************************/ + +static void kbd_ctrl (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == BRK) + { + kbd_state = AS; + kbd_flags &= (~CTRL); + } + else + { + kbd_state = CN; + kbd_flags |= CTRL; + } +} + + +/******************************************************************************/ + +static void kbd_caps (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == NORMAL) + { + kbd_flags ^= CAPS; + kbd_led_set (); /* update keyboard LED */ + } +} + + +/******************************************************************************/ + +static void kbd_num (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == NORMAL) + { + kbd_flags ^= NUM; + kbd_state = (kbd_flags & NUM) ? AS : NM; + kbd_led_set (); /* update keyboard LED */ + } +} + + +/******************************************************************************/ + +static void kbd_scroll (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == NORMAL) + { + kbd_flags ^= STP; + kbd_led_set (); /* update keyboard LED */ + if (kbd_flags & STP) + kbd_input = 0x13; + else + kbd_input = 0x11; + } +} + +/******************************************************************************/ + +static void kbd_alt (unsigned char scan_code) +{ + if ((kbd_flags & BRK) == BRK) + { + kbd_state = AS; + kbd_flags &= (~ALT); + } + else + { + kbd_state = AK; + kbd_flags &= ALT; + } +} + + +/******************************************************************************/ + +static void kbd_led_set (void) +{ + kbd_input_empty(); + out8 (I8042_DATA_REG, 0xed); /* SET LED command */ + kbd_input_empty(); + out8 (I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */ +} + + +/******************************************************************************/ + +static int kbd_input_empty (void) +{ + int kbdTimeout = KBD_TIMEOUT; + + /* wait for input buf empty */ + while ((in8 (I8042_STATUS_REG) & 0x02) && kbdTimeout--) + udelay(1000); + + return kbdTimeout; +} + +/******************************************************************************/ + +static int kbd_reset (void) +{ + if (kbd_input_empty() == 0) + return -1; + + out8 (I8042_DATA_REG, 0xff); + + udelay(250000); + + if (kbd_input_empty() == 0) + return -1; + +#ifdef CONFIG_USE_CPCIDVI + out8 (I8042_COMMAND_REG, 0x60); +#else + out8 (I8042_DATA_REG, 0x60); +#endif + + if (kbd_input_empty() == 0) + return -1; + + out8 (I8042_DATA_REG, 0x45); + + + if (kbd_input_empty() == 0) + return -1; + + out8 (I8042_COMMAND_REG, 0xae); + + if (kbd_input_empty() == 0) + return -1; + + return 0; +} + +#endif /* CONFIG_I8042_KBD */ diff --git a/drivers/i82365.c b/drivers/i82365.c new file mode 100644 index 000000000..a40fcf41c --- /dev/null +++ b/drivers/i82365.c @@ -0,0 +1,1014 @@ +/* + * (C) Copyright 2003-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * + * Lots of code copied from: + * + * i82365.c 1.352 - Linux driver for Intel 82365 and compatible + * PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers. + * (C) 1999 David A. Hinds + */ + +#include + +#ifdef CONFIG_I82365 + +#include +#include +#include +#include + +#include +#include +#include +#ifdef CONFIG_CPC45 +#include +#else +#include +#endif + +static struct pci_device_id supported[] = { +#ifdef CONFIG_CPC45 + {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729}, +#else + {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510}, +#endif + {0, 0} +}; + +#define CYCLE_TIME 120 + +#ifdef CONFIG_CPC45 +extern int SPD67290Init (void); +#endif + +#ifdef DEBUG +static void i82365_dump_regions (pci_dev_t dev); +#endif + +typedef struct socket_info_t { + pci_dev_t dev; + u_short bcr; + u_char pci_lat, cb_lat, sub_bus, cache; + u_int cb_phys; + + socket_cap_t cap; + u_short type; + u_int flags; +#ifdef CONFIG_CPC45 + cirrus_state_t c_state; +#else + ti113x_state_t state; +#endif +} socket_info_t; + +#ifdef CONFIG_CPC45 +/* These definitions must match the pcic table! */ +typedef enum pcic_id { + IS_PD6710, IS_PD672X, IS_VT83C469 +} pcic_id; + +typedef struct pcic_t { + char *name; +} pcic_t; + +static pcic_t pcic[] = { + {" Cirrus PD6710: "}, + {" Cirrus PD672x: "}, + {" VIA VT83C469: "}, +}; +#endif + +static socket_info_t socket; +static socket_state_t state; +static struct pccard_mem_map mem; +static struct pccard_io_map io; + +/*====================================================================*/ + +/* Some PCI shortcuts */ + +static int pci_readb (socket_info_t * s, int r, u_char * v) +{ + return pci_read_config_byte (s->dev, r, v); +} +static int pci_writeb (socket_info_t * s, int r, u_char v) +{ + return pci_write_config_byte (s->dev, r, v); +} +static int pci_readw (socket_info_t * s, int r, u_short * v) +{ + return pci_read_config_word (s->dev, r, v); +} +static int pci_writew (socket_info_t * s, int r, u_short v) +{ + return pci_write_config_word (s->dev, r, v); +} +#ifndef CONFIG_CPC45 +static int pci_readl (socket_info_t * s, int r, u_int * v) +{ + return pci_read_config_dword (s->dev, r, v); +} +static int pci_writel (socket_info_t * s, int r, u_int v) +{ + return pci_write_config_dword (s->dev, r, v); +} +#endif /* !CONFIG_CPC45 */ + +/*====================================================================*/ + +#ifdef CONFIG_CPC45 + +#define cb_readb(s) readb((s)->cb_phys + 1) +#define cb_writeb(s, v) writeb(v, (s)->cb_phys) +#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1) +#define cb_readl(s, r) readl((s)->cb_phys + (r)) +#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) + + +static u_char i365_get (socket_info_t * s, u_short reg) +{ + u_char val; +#ifdef CONFIG_PCMCIA_SLOT_A + int slot = 0; +#else + int slot = 1; +#endif + + val = I365_REG (slot, reg); + + cb_writeb (s, val); + val = cb_readb (s); + + debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val); + return val; +} + +static void i365_set (socket_info_t * s, u_short reg, u_char data) +{ +#ifdef CONFIG_PCMCIA_SLOT_A + int slot = 0; +#else + int slot = 1; +#endif + u_char val; + + val = I365_REG (slot, reg); + + cb_writeb (s, val); + cb_writeb2 (s, data); + + debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data); +} + +#else /* ! CONFIG_CPC45 */ + +#define cb_readb(s, r) readb((s)->cb_phys + (r)) +#define cb_readl(s, r) readl((s)->cb_phys + (r)) +#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r)) +#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r)) + +static u_char i365_get (socket_info_t * s, u_short reg) +{ + return cb_readb (s, 0x0800 + reg); +} + +static void i365_set (socket_info_t * s, u_short reg, u_char data) +{ + cb_writeb (s, 0x0800 + reg, data); +} +#endif /* CONFIG_CPC45 */ + +static void i365_bset (socket_info_t * s, u_short reg, u_char mask) +{ + i365_set (s, reg, i365_get (s, reg) | mask); +} + +static void i365_bclr (socket_info_t * s, u_short reg, u_char mask) +{ + i365_set (s, reg, i365_get (s, reg) & ~mask); +} + +#if 0 /* not used */ +static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b) +{ + u_char d = i365_get (s, reg); + + i365_set (s, reg, (b) ? (d | mask) : (d & ~mask)); +} + +static u_short i365_get_pair (socket_info_t * s, u_short reg) +{ + return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8)); +} +#endif /* not used */ + +static void i365_set_pair (socket_info_t * s, u_short reg, u_short data) +{ + i365_set (s, reg, data & 0xff); + i365_set (s, reg + 1, data >> 8); +} + +#ifdef CONFIG_CPC45 +/*====================================================================== + + Code to save and restore global state information for Cirrus + PD67xx controllers, and to set and report global configuration + options. + +======================================================================*/ + +#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b)))) + +static void cirrus_get_state (socket_info_t * s) +{ + int i; + cirrus_state_t *p = &s->c_state; + + p->misc1 = i365_get (s, PD67_MISC_CTL_1); + p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); + p->misc2 = i365_get (s, PD67_MISC_CTL_2); + for (i = 0; i < 6; i++) + p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i); + +} + +static void cirrus_set_state (socket_info_t * s) +{ + int i; + u_char misc; + cirrus_state_t *p = &s->c_state; + + misc = i365_get (s, PD67_MISC_CTL_2); + i365_set (s, PD67_MISC_CTL_2, p->misc2); + if (misc & PD67_MC2_SUSPEND) + udelay (50000); + misc = i365_get (s, PD67_MISC_CTL_1); + misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA); + i365_set (s, PD67_MISC_CTL_1, misc | p->misc1); + for (i = 0; i < 6; i++) + i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]); +} + +static u_int cirrus_set_opts (socket_info_t * s) +{ + cirrus_state_t *p = &s->c_state; + u_int mask = 0xffff; +#if DEBUG + char buf[200]; + + memset (buf, 0, 200); +#endif + + if (has_ring == -1) + has_ring = 1; + flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring); + flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode); +#if DEBUG + if (p->misc2 & PD67_MC2_IRQ15_RI) + strcat (buf, " [ring]"); + if (p->misc2 & PD67_MC2_DYNAMIC_MODE) + strcat (buf, " [dyn mode]"); + if (p->misc1 & PD67_MC1_INPACK_ENA) + strcat (buf, " [inpack]"); +#endif + + if (p->misc2 & PD67_MC2_IRQ15_RI) + mask &= ~0x8000; + if (has_led > 0) { +#if DEBUG + strcat (buf, " [led]"); +#endif + mask &= ~0x1000; + } + if (has_dma > 0) { +#if DEBUG + strcat (buf, " [dma]"); +#endif + mask &= ~0x0600; + flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass); +#if DEBUG + if (p->misc2 & PD67_MC2_FREQ_BYPASS) + strcat (buf, " [freq bypass]"); +#endif + } + + if (setup_time >= 0) + p->timer[0] = p->timer[3] = setup_time; + if (cmd_time > 0) { + p->timer[1] = cmd_time; + p->timer[4] = cmd_time * 2 + 4; + } + if (p->timer[1] == 0) { + p->timer[1] = 6; + p->timer[4] = 16; + if (p->timer[0] == 0) + p->timer[0] = p->timer[3] = 1; + } + if (recov_time >= 0) + p->timer[2] = p->timer[5] = recov_time; + + debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n", + buf, + p->timer[0], p->timer[1], p->timer[2], + p->timer[3], p->timer[4], p->timer[5]); + + return mask; +} + +#else /* !CONFIG_CPC45 */ + +/*====================================================================== + + Code to save and restore global state information for TI 1130 and + TI 1131 controllers, and to set and report global configuration + options. + +======================================================================*/ + +static void ti113x_get_state (socket_info_t * s) +{ + ti113x_state_t *p = &s->state; + + pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl); + pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl); + pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl); + pci_readb (s, TI1250_DIAGNOSTIC, &p->diag); + pci_readl (s, TI12XX_IRQMUX, &p->irqmux); +} + +static void ti113x_set_state (socket_info_t * s) +{ + ti113x_state_t *p = &s->state; + + pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl); + pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl); + pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl); + pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0); + pci_writeb (s, TI1250_DIAGNOSTIC, p->diag); + pci_writel (s, TI12XX_IRQMUX, p->irqmux); + i365_set_pair (s, TI113X_IO_OFFSET (0), 0); + i365_set_pair (s, TI113X_IO_OFFSET (1), 0); +} + +static u_int ti113x_set_opts (socket_info_t * s) +{ + ti113x_state_t *p = &s->state; + u_int mask = 0xffff; + + p->cardctl &= ~TI113X_CCR_ZVENABLE; + p->cardctl |= TI113X_CCR_SPKROUTEN; + + return mask; +} +#endif /* CONFIG_CPC45 */ + +/*====================================================================== + + Routines to handle common CardBus options + +======================================================================*/ + +/* Default settings for PCI command configuration register */ +#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ + PCI_COMMAND_MASTER|PCI_COMMAND_WAIT) + +static void cb_get_state (socket_info_t * s) +{ + pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache); + pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat); + pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat); + pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus); + pci_readb (s, CB_SUBORD_BUS, &s->sub_bus); + pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr); +} + +static void cb_set_state (socket_info_t * s) +{ +#ifndef CONFIG_CPC45 + pci_writel (s, CB_LEGACY_MODE_BASE, 0); + pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys); +#endif + pci_writew (s, PCI_COMMAND, CMD_DFLT); + pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache); + pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat); + pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat); + pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus); + pci_writeb (s, CB_SUBORD_BUS, s->sub_bus); + pci_writew (s, CB_BRIDGE_CONTROL, s->bcr); +} + +static void cb_set_opts (socket_info_t * s) +{ +#ifndef CONFIG_CPC45 + if (s->cache == 0) + s->cache = 8; + if (s->pci_lat == 0) + s->pci_lat = 0xa8; + if (s->cb_lat == 0) + s->cb_lat = 0xb0; +#endif +} + +/*====================================================================== + + Power control for Cardbus controllers: used both for 16-bit and + Cardbus cards. + +======================================================================*/ + +static int cb_set_power (socket_info_t * s, socket_state_t * state) +{ + u_int reg = 0; + +#ifdef CONFIG_CPC45 + + reg = I365_PWR_NORESET; + if (state->flags & SS_PWR_AUTO) + reg |= I365_PWR_AUTO; + if (state->flags & SS_OUTPUT_ENA) + reg |= I365_PWR_OUT; + if (state->Vpp != 0) { + if (state->Vpp == 120) { + reg |= I365_VPP1_12V; + puts (" 12V card found: "); + } else if (state->Vpp == state->Vcc) { + reg |= I365_VPP1_5V; + } else { + puts (" power not found: "); + return -1; + } + } + if (state->Vcc != 0) { + reg |= I365_VCC_5V; + if (state->Vcc == 33) { + puts (" 3.3V card found: "); + i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } else if (state->Vcc == 50) { + puts (" 5V card found: "); + i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } else { + puts (" power not found: "); + return -1; + } + } + + if (reg != i365_get (s, I365_POWER)) { + reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V); + i365_set (s, I365_POWER, reg); + } + +#else /* ! CONFIG_CPC45 */ + + /* restart card voltage detection if it seems appropriate */ + if ((state->Vcc == 0) && (state->Vpp == 0) && + !(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE)) + cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST); + switch (state->Vcc) { + case 0: + reg = 0; + break; + case 33: + reg = CB_SC_VCC_3V; + break; + case 50: + reg = CB_SC_VCC_5V; + break; + default: + return -1; + } + switch (state->Vpp) { + case 0: + break; + case 33: + reg |= CB_SC_VPP_3V; + break; + case 50: + reg |= CB_SC_VPP_5V; + break; + case 120: + reg |= CB_SC_VPP_12V; + break; + default: + return -1; + } + if (reg != cb_readl (s, CB_SOCKET_CONTROL)) + cb_writel (s, CB_SOCKET_CONTROL, reg); +#endif /* CONFIG_CPC45 */ + return 0; +} + +/*====================================================================== + + Generic routines to get and set controller options + +======================================================================*/ + +static void get_bridge_state (socket_info_t * s) +{ +#ifdef CONFIG_CPC45 + cirrus_get_state (s); +#else + ti113x_get_state (s); +#endif + cb_get_state (s); +} + +static void set_bridge_state (socket_info_t * s) +{ + cb_set_state (s); + i365_set (s, I365_GBLCTL, 0x00); + i365_set (s, I365_GENCTL, 0x00); +#ifdef CONFIG_CPC45 + cirrus_set_state (s); +#else + ti113x_set_state (s); +#endif +} + +static void set_bridge_opts (socket_info_t * s) +{ +#ifdef CONFIG_CPC45 + cirrus_set_opts (s); +#else + ti113x_set_opts (s); +#endif + cb_set_opts (s); +} + +/*====================================================================*/ +#define PD67_EXT_INDEX 0x2e /* Extension index */ +#define PD67_EXT_DATA 0x2f /* Extension data */ +#define PD67_EXD_VS1(s) (0x01 << ((s)<<1)) + +#define pd67_ext_get(s, r) \ + (i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA)) + +static int i365_get_status (socket_info_t * s, u_int * value) +{ + u_int status; +#ifdef CONFIG_CPC45 + u_char val; + u_char power, vcc, vpp; + u_int powerstate; +#endif + + status = i365_get (s, I365_IDENT); + status = i365_get (s, I365_STATUS); + *value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0; + if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) { + *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG; + } else { + *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD; + *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN; + } + *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0; + *value |= (status & I365_CS_READY) ? SS_READY : 0; + *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0; + +#ifdef CONFIG_CPC45 + /* Check for Cirrus CL-PD67xx chips */ + i365_set (s, PD67_CHIP_INFO, 0); + val = i365_get (s, PD67_CHIP_INFO); + s->type = -1; + if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) { + val = i365_get (s, PD67_CHIP_INFO); + if ((val & PD67_INFO_CHIP_ID) == 0) { + s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710; + i365_set (s, PD67_EXT_INDEX, 0xe5); + if (i365_get (s, PD67_EXT_INDEX) != 0xe5) + s->type = IS_VT83C469; + } + } else { + printf ("no Cirrus Chip found\n"); + *value = 0; + return -1; + } + + power = i365_get (s, I365_POWER); + state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0; + state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0; + vcc = power & I365_VCC_MASK; + vpp = power & I365_VPP1_MASK; + state.Vcc = state.Vpp = 0; + if((vcc== 0) || (vpp == 0)) { + /* + * On the Cirrus we get the info which card voltage + * we have in EXTERN DATA and write it to MISC_CTL1 + */ + powerstate = pd67_ext_get(s, PD67_EXTERN_DATA); + if (powerstate & PD67_EXD_VS1(0)) { + /* 5V Card */ + i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } else { + /* 3.3V Card */ + i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V); + } + i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V)); + power = i365_get (s, I365_POWER); + } + if (power & I365_VCC_5V) { + state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50; + } + + if (power == I365_VPP1_12V) + state.Vpp = 120; + + /* IO card, RESET flags, IO interrupt */ + power = i365_get (s, I365_INTCTL); + state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET; + if (power & I365_PC_IOCARD) + state.flags |= SS_IOCARD; + state.io_irq = power & I365_IRQ_MASK; + + /* Card status change mask */ + power = i365_get (s, I365_CSCINT); + state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0; + if (state.flags & SS_IOCARD) + state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0; + else { + state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0; + state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0; + state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0; + } + debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, " + "io_irq %d, csc_mask %#2.2x\n", state.flags, + state.Vcc, state.Vpp, state.io_irq, state.csc_mask); + +#else /* !CONFIG_CPC45 */ + + status = cb_readl (s, CB_SOCKET_STATE); + *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0; + *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0; + *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0; + *value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING; + /* For now, ignore cards with unsupported voltage keys */ + if (*value & SS_XVCARD) + *value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD); +#endif /* CONFIG_CPC45 */ + return 0; +} /* i365_get_status */ + +static int i365_set_socket (socket_info_t * s, socket_state_t * state) +{ + u_char reg; + + set_bridge_state (s); + + /* IO card, RESET flag */ + reg = 0; + reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET; + reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0; + i365_set (s, I365_INTCTL, reg); + +#ifdef CONFIG_CPC45 + cb_set_power (s, state); + +#if 0 + /* Card status change interrupt mask */ + reg = s->cs_irq << 4; + if (state->csc_mask & SS_DETECT) + reg |= I365_CSC_DETECT; + if (state->flags & SS_IOCARD) { + if (state->csc_mask & SS_STSCHG) + reg |= I365_CSC_STSCHG; + } else { + if (state->csc_mask & SS_BATDEAD) + reg |= I365_CSC_BVD1; + if (state->csc_mask & SS_BATWARN) + reg |= I365_CSC_BVD2; + if (state->csc_mask & SS_READY) + reg |= I365_CSC_READY; + } + i365_set (s, I365_CSCINT, reg); + i365_get (s, I365_CSC); +#endif /* 0 */ + +#else /* !CONFIG_CPC45 */ + + reg = I365_PWR_NORESET; + if (state->flags & SS_PWR_AUTO) + reg |= I365_PWR_AUTO; + if (state->flags & SS_OUTPUT_ENA) + reg |= I365_PWR_OUT; + + cb_set_power (s, state); + reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK); + + if (reg != i365_get (s, I365_POWER)) + i365_set (s, I365_POWER, reg); +#endif /* CONFIG_CPC45 */ + + return 0; +} /* i365_set_socket */ + +/*====================================================================*/ + +static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem) +{ + u_short base, i; + u_char map; + + debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n", + mem->map, mem->flags, mem->speed, + mem->sys_start, mem->sys_stop, mem->card_start); + + map = mem->map; + if ((map > 4) || + (mem->card_start > 0x3ffffff) || + (mem->sys_start > mem->sys_stop) || + (mem->speed > 1000)) { + return -1; + } + + /* Turn off the window before changing anything */ + if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map)) + i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map)); + + /* Take care of high byte, for PCI controllers */ + i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24); + + base = I365_MEM (map); + i = (mem->sys_start >> 12) & 0x0fff; + if (mem->flags & MAP_16BIT) + i |= I365_MEM_16BIT; + if (mem->flags & MAP_0WS) + i |= I365_MEM_0WS; + i365_set_pair (s, base + I365_W_START, i); + + i = (mem->sys_stop >> 12) & 0x0fff; + switch (mem->speed / CYCLE_TIME) { + case 0: + break; + case 1: + i |= I365_MEM_WS0; + break; + case 2: + i |= I365_MEM_WS1; + break; + default: + i |= I365_MEM_WS1 | I365_MEM_WS0; + break; + } + i365_set_pair (s, base + I365_W_STOP, i); + +#ifdef CONFIG_CPC45 + i = 0; +#else + i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff; +#endif + if (mem->flags & MAP_WRPROT) + i |= I365_MEM_WRPROT; + if (mem->flags & MAP_ATTRIB) + i |= I365_MEM_REG; + i365_set_pair (s, base + I365_W_OFF, i); + +#ifdef CONFIG_CPC45 + /* set System Memory map Upper Adress */ + i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map)); + i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff)); +#endif + + /* Turn on the window if necessary */ + if (mem->flags & MAP_ACTIVE) + i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map)); + return 0; +} /* i365_set_mem_map */ + +static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io) +{ + u_char map, ioctl; + + map = io->map; + /* comment out: comparison is always false due to limited range of data type */ + if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */ + (io->stop < io->start)) + return -1; + /* Turn off the window before changing anything */ + if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map)) + i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map)); + i365_set_pair (s, I365_IO (map) + I365_W_START, io->start); + i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop); + ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map); + if (io->speed) + ioctl |= I365_IOCTL_WAIT (map); + if (io->flags & MAP_0WS) + ioctl |= I365_IOCTL_0WS (map); + if (io->flags & MAP_16BIT) + ioctl |= I365_IOCTL_16BIT (map); + if (io->flags & MAP_AUTOSZ) + ioctl |= I365_IOCTL_IOCS16 (map); + i365_set (s, I365_IOCTL, ioctl); + /* Turn on the window if necessary */ + if (io->flags & MAP_ACTIVE) + i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map)); + return 0; +} /* i365_set_io_map */ + +/*====================================================================*/ + +int i82365_init (void) +{ + u_int val; + int i; + +#ifdef CONFIG_CPC45 + if (SPD67290Init () != 0) + return 1; +#endif + if ((socket.dev = pci_find_devices (supported, 0)) < 0) { + /* Controller not found */ + return 1; + } + debug ("i82365 Device Found!\n"); + + pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys); + socket.cb_phys &= ~0xf; + +#ifdef CONFIG_CPC45 + /* + 0xfe000000 see MPC 8245 Users Manual Adress Map B */ + socket.cb_phys += 0xfe000000; +#endif + + get_bridge_state (&socket); + set_bridge_opts (&socket); + + i = i365_get_status (&socket, &val); + +#ifdef CONFIG_CPC45 + if (i > -1) { + puts (pcic[socket.type].name); + } else { + printf ("i82365: Controller not found.\n"); + return 1; + } + if((val & SS_DETECT) != SS_DETECT){ + puts ("No card\n"); + return 1; + } +#else /* !CONFIG_CPC45 */ + if (val & SS_DETECT) { + if (val & SS_3VCARD) { + state.Vcc = state.Vpp = 33; + puts (" 3.3V card found: "); + } else if (!(val & SS_XVCARD)) { + state.Vcc = state.Vpp = 50; + puts (" 5.0V card found: "); + } else { + puts ("i82365: unsupported voltage key\n"); + state.Vcc = state.Vpp = 0; + } + } else { + /* No card inserted */ + puts ("No card\n"); + return 1; + } +#endif /* CONFIG_CPC45 */ + +#ifdef CONFIG_CPC45 + state.flags |= SS_OUTPUT_ENA; +#else + state.flags = SS_IOCARD | SS_OUTPUT_ENA; + state.csc_mask = 0; + state.io_irq = 0; +#endif + + i365_set_socket (&socket, &state); + + for (i = 500; i; i--) { + if ((i365_get (&socket, I365_STATUS) & I365_CS_READY)) + break; + udelay (1000); + } + + if (i == 0) { + /* PC Card not ready for data transfer */ + puts ("i82365 PC Card not ready for data transfer\n"); + return 1; + } + debug (" PC Card ready for data transfer: "); + + mem.map = 0; + mem.flags = MAP_ATTRIB | MAP_ACTIVE; + mem.speed = 300; + mem.sys_start = CFG_PCMCIA_MEM_ADDR; + mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1; + mem.card_start = 0; + i365_set_mem_map (&socket, &mem); + +#ifdef CONFIG_CPC45 + mem.map = 1; + mem.flags = MAP_ACTIVE; + mem.speed = 300; + mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE; + mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1; + mem.card_start = 0; + i365_set_mem_map (&socket, &mem); + +#else /* !CONFIG_CPC45 */ + + io.map = 0; + io.flags = MAP_AUTOSZ | MAP_ACTIVE; + io.speed = 0; + io.start = 0x0100; + io.stop = 0x010F; + i365_set_io_map (&socket, &io); + +#endif /* CONFIG_CPC45 */ + +#ifdef DEBUG + i82365_dump_regions (socket.dev); +#endif + + return 0; +} + +void i82365_exit (void) +{ + io.map = 0; + io.flags = 0; + io.speed = 0; + io.start = 0; + io.stop = 0x1; + + i365_set_io_map (&socket, &io); + + mem.map = 0; + mem.flags = 0; + mem.speed = 0; + mem.sys_start = 0; + mem.sys_stop = 0x1000; + mem.card_start = 0; + + i365_set_mem_map (&socket, &mem); + +#ifdef CONFIG_CPC45 + mem.map = 1; + mem.flags = 0; + mem.speed = 0; + mem.sys_start = 0; + mem.sys_stop = 0x1000; + mem.card_start = 0; + + i365_set_mem_map (&socket, &mem); +#else /* !CONFIG_CPC45 */ + socket.state.sysctl &= 0xFFFF00FF; +#endif + state.Vcc = state.Vpp = 0; + + i365_set_socket (&socket, &state); +} + +/*====================================================================== + + Debug stuff + +======================================================================*/ + +#ifdef DEBUG +static void i82365_dump_regions (pci_dev_t dev) +{ + u_int tmp[2]; + u_int *mem = (void *) socket.cb_phys; + u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR; + u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET); + + pci_read_config_dword (dev, 0x00, tmp + 0); + pci_read_config_dword (dev, 0x80, tmp + 1); + + printf ("PCI CONF: %08X ... %08X\n", + tmp[0], tmp[1]); + printf ("PCI MEM: ... %08X ... %08X\n", + mem[0x8 / 4], mem[0x800 / 4]); + printf ("CIS: ...%c%c%c%c%c%c%c%c...\n", + cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e], + cis[0x40], cis[0x42], cis[0x44], cis[0x48]); + printf ("CIS CONF: %02X %02X %02X ...\n", + cis[0x200], cis[0x202], cis[0x204]); + printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n", + ide[0], ide[1], ide[2], ide[3], + ide[4], ide[5], ide[6], ide[7]); +} +#endif /* DEBUG */ + +#endif /* CONFIG_I82365 */ diff --git a/drivers/inca-ip_sw.c b/drivers/inca-ip_sw.c new file mode 100644 index 000000000..ab22b4d53 --- /dev/null +++ b/drivers/inca-ip_sw.c @@ -0,0 +1,817 @@ +/* + * INCA-IP internal switch ethernet driver. + * + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ + && defined(CONFIG_INCA_IP_SWITCH) + +#include +#include +#include +#include + + +#define NUM_RX_DESC PKTBUFSRX +#define NUM_TX_DESC 3 +#define TOUT_LOOP 1000000 + + +#define DELAY udelay(10000) + /* Sometimes the store word instruction hangs while writing to one + * of the Switch registers. Moving the instruction into a separate + * function somehow makes the problem go away. + */ +static void SWORD(volatile u32 * reg, u32 value) +{ + *reg = value; +} + +#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value; +#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) +#define SW_WRITE_REG(reg, value) \ + SWORD(reg, value);\ + DELAY;\ + SWORD(reg, value); + +#define SW_READ_REG(reg, value) \ + value = (u32)*((volatile u32*)reg);\ + DELAY;\ + value = (u32)*((volatile u32*)reg); + +#define INCA_DMA_TX_POLLING_TIME 0x07 +#define INCA_DMA_RX_POLLING_TIME 0x07 + +#define INCA_DMA_TX_HOLD 0x80000000 +#define INCA_DMA_TX_EOP 0x40000000 +#define INCA_DMA_TX_SOP 0x20000000 +#define INCA_DMA_TX_ICPT 0x10000000 +#define INCA_DMA_TX_IEOP 0x08000000 + +#define INCA_DMA_RX_C 0x80000000 +#define INCA_DMA_RX_SOP 0x40000000 +#define INCA_DMA_RX_EOP 0x20000000 + +#define INCA_SWITCH_PHY_SPEED_10H 0x1 +#define INCA_SWITCH_PHY_SPEED_10F 0x5 +#define INCA_SWITCH_PHY_SPEED_100H 0x2 +#define INCA_SWITCH_PHY_SPEED_100F 0x6 + +/************************ Auto MDIX settings ************************/ +#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR +#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL +#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT +#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16 + +#define WAIT_SIGNAL_RETRIES 100 +#define WAIT_LINK_RETRIES 100 +#define LINK_RETRY_DELAY 2000 /* ms */ +/********************************************************************/ + +typedef struct +{ + union { + struct { + volatile u32 HOLD :1; + volatile u32 ICpt :1; + volatile u32 IEop :1; + volatile u32 offset :3; + volatile u32 reserved0 :4; + volatile u32 NFB :22; + }field; + + volatile u32 word; + }params; + + volatile u32 nextRxDescPtr; + + volatile u32 RxDataPtr; + + union { + struct { + volatile u32 C :1; + volatile u32 Sop :1; + volatile u32 Eop :1; + volatile u32 reserved3 :12; + volatile u32 NBT :17; + }field; + + volatile u32 word; + }status; + +} inca_rx_descriptor_t; + + +typedef struct +{ + union { + struct { + volatile u32 HOLD :1; + volatile u32 Eop :1; + volatile u32 Sop :1; + volatile u32 ICpt :1; + volatile u32 IEop :1; + volatile u32 reserved0 :5; + volatile u32 NBA :22; + }field; + + volatile u32 word; + }params; + + volatile u32 nextTxDescPtr; + + volatile u32 TxDataPtr; + + volatile u32 C :1; + volatile u32 reserved3 :31; + +} inca_tx_descriptor_t; + + +static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16))); +static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16))); + +static int tx_new, rx_new, tx_hold, rx_hold; +static int tx_old_hold = -1; +static int initialized = 0; + + +static int inca_switch_init(struct eth_device *dev, bd_t * bis); +static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length); +static int inca_switch_recv(struct eth_device *dev); +static void inca_switch_halt(struct eth_device *dev); +static void inca_init_switch_chip(void); +static void inca_dma_init(void); +static int inca_amdix(void); + + +int inca_switch_initialize(bd_t * bis) +{ + struct eth_device *dev; + +#if 0 + printf("Entered inca_switch_initialize()\n"); +#endif + + if (!(dev = (struct eth_device *) malloc (sizeof *dev))) { + printf("Failed to allocate memory\n"); + return 0; + } + memset(dev, 0, sizeof(*dev)); + + inca_dma_init(); + + inca_init_switch_chip(); + +#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) + inca_amdix(); +#endif + + sprintf(dev->name, "INCA-IP Switch"); + dev->init = inca_switch_init; + dev->halt = inca_switch_halt; + dev->send = inca_switch_send; + dev->recv = inca_switch_recv; + + eth_register(dev); + +#if 0 + printf("Leaving inca_switch_initialize()\n"); +#endif + + return 1; +} + + +static int inca_switch_init(struct eth_device *dev, bd_t * bis) +{ + int i; + u32 v, regValue; + u16 wTmp; + +#if 0 + printf("Entering inca_switch_init()\n"); +#endif + + /* Set MAC address. + */ + wTmp = (u16)dev->enetaddr[0]; + regValue = (wTmp << 8) | dev->enetaddr[1]; + + SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue); + + wTmp = (u16)dev->enetaddr[2]; + regValue = (wTmp << 8) | dev->enetaddr[3]; + regValue = regValue << 16; + wTmp = (u16)dev->enetaddr[4]; + regValue |= (wTmp<<8) | dev->enetaddr[5]; + + SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue); + + /* Initialize the descriptor rings. + */ + for (i = 0; i < NUM_RX_DESC; i++) { + inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]); + memset(rx_desc, 0, sizeof(rx_ring[i])); + + /* Set maximum size of receive buffer. + */ + rx_desc->params.field.NFB = PKTSIZE_ALIGN; + + /* Set the offset of the receive buffer. Zero means + * that the offset mechanism is not used. + */ + rx_desc->params.field.offset = 0; + + /* Check if it is the last descriptor. + */ + if (i == (NUM_RX_DESC - 1)) { + /* Let the last descriptor point to the first + * one. + */ + rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring); + } else { + /* Set the address of the next descriptor. + */ + rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]); + } + + rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]); + } + +#if 0 + printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]); + printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]); +#endif + + for (i = 0; i < NUM_TX_DESC; i++) { + inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]); + + memset(tx_desc, 0, sizeof(tx_ring[i])); + + tx_desc->params.word = 0; + tx_desc->params.field.HOLD = 1; + tx_desc->C = 1; + + /* Check if it is the last descriptor. + */ + if (i == (NUM_TX_DESC - 1)) { + /* Let the last descriptor point to the + * first one. + */ + tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring); + } else { + /* Set the address of the next descriptor. + */ + tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]); + } + } + + /* Initialize RxDMA. + */ + DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v); +#if 0 + printf("RX status = 0x%08X\n", v); +#endif + + /* Writing to the FRDA of CHANNEL. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring); + + /* Writing to the COMMAND REG. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT); + + /* Initialize TxDMA. + */ + DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v); +#if 0 + printf("TX status = 0x%08X\n", v); +#endif + + /* Writing to the FRDA of CHANNEL. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring); + + tx_new = rx_new = 0; + + tx_hold = NUM_TX_DESC - 1; + rx_hold = NUM_RX_DESC - 1; + +#if 0 + rx_ring[rx_hold].params.field.HOLD = 1; +#endif + /* enable spanning tree forwarding, enable the CPU port */ + /* ST_PT: + * CPS (CPU port status) 0x3 (forwarding) + * LPS (LAN port status) 0x3 (forwarding) + * PPS (PC port status) 0x3 (forwarding) + */ + SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f); + +#if 0 + printf("Leaving inca_switch_init()\n"); +#endif + + return 0; +} + + +static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length) +{ + int i; + int res = -1; + u32 command; + u32 regValue; + inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]); + +#if 0 + printf("Entered inca_switch_send()\n"); +#endif + + if (length <= 0) { + printf ("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + + for(i = 0; tx_desc->C == 0; i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx error buffer not ready\n", dev->name); + goto Done; + } + } + + if (tx_old_hold >= 0) { + KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1; + } + tx_old_hold = tx_hold; + + tx_desc->params.word = + (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD); + + tx_desc->C = 0; + tx_desc->TxDataPtr = (u32)packet; + tx_desc->params.field.NBA = length; + + KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0; + + tx_hold = tx_new; + tx_new = (tx_new + 1) % NUM_TX_DESC; + + + if (! initialized) { + command = INCA_IP_DMA_DMA_TXCCR0_INIT; + initialized = 1; + } else { + command = INCA_IP_DMA_DMA_TXCCR0_HR; + } + + DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); + regValue |= command; +#if 0 + printf("regValue = 0x%x\n", regValue); +#endif + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); + +#if 1 + for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) { + if (i >= TOUT_LOOP) { + printf("%s: tx buffer not ready\n", dev->name); + goto Done; + } + } +#endif + res = length; +Done: +#if 0 + printf("Leaving inca_switch_send()\n"); +#endif + return res; +} + + +static int inca_switch_recv(struct eth_device *dev) +{ + int length = 0; + inca_rx_descriptor_t * rx_desc; + +#if 0 + printf("Entered inca_switch_recv()\n"); +#endif + + for (;;) { + rx_desc = KSEG1ADDR(&rx_ring[rx_new]); + + if (rx_desc->status.field.C == 0) { + break; + } + +#if 0 + rx_ring[rx_new].params.field.HOLD = 1; +#endif + + if (! rx_desc->status.field.Eop) { + printf("Partly received packet!!!\n"); + break; + } + + length = rx_desc->status.field.NBT; + rx_desc->status.word &= + ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C); +#if 0 +{ + int i; + for (i=0;iparams.field.HOLD = 0; + + rx_hold = rx_new; + + rx_new = (rx_new + 1) % NUM_RX_DESC; + } + +#if 0 + printf("Leaving inca_switch_recv()\n"); +#endif + + return length; +} + + +static void inca_switch_halt(struct eth_device *dev) +{ +#if 0 + printf("Entered inca_switch_halt()\n"); +#endif + +#if 1 + initialized = 0; +#endif +#if 1 + /* Disable forwarding to the CPU port. + */ + SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); + + /* Close RxDMA channel. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); + + /* Close TxDMA channel. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF); + + +#endif +#if 0 + printf("Leaving inca_switch_halt()\n"); +#endif +} + + +static void inca_init_switch_chip(void) +{ + u32 regValue; + + /* To workaround a problem with collision counter + * (see Errata sheet). + */ + SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001); + SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001); + +#if 1 + /* init MDIO configuration: + * MDS (Poll speed): 0x01 (4ms) + * PHY_LAN_ADDR: 0x06 + * PHY_PC_ADDR: 0x05 + * UEP (Use External PHY): 0x00 (Internal PHY is used) + * PS (Port Select): 0x00 (PT/UMM for LAN) + * PT (PHY Test): 0x00 (no test mode) + * UMM (Use MDIO Mode): 0x00 (state machine is disabled) + */ + SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50); + + /* init PHY: + * SL (Auto Neg. Speed for LAN) + * SP (Auto Neg. Speed for PC) + * LL (Link Status for LAN) + * LP (Link Status for PC) + * DL (Duplex Status for LAN) + * DP (Duplex Status for PC) + * PL (Auto Neg. Pause Status for LAN) + * PP (Auto Neg. Pause Status for PC) + */ + SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff); + + /* MDIO_ACC: + * RA (Request/Ack) 0x01 (Request) + * RW (Read/Write) 0x01 (Write) + * PHY_ADDR 0x05 (PC) + * REG_ADDR 0x00 (PHY_BCR: basic control register) + * PHY_DATA 0x8000 + * Reset - software reset + * LB (loop back) - normal + * SS (speed select) - 10 Mbit/s + * ANE (auto neg. enable) - enable + * PD (power down) - normal + * ISO (isolate) - normal + * RAN (restart auto neg.) - normal + * DM (duplex mode) - half duplex + * CT (collision test) - enable + */ + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000); + + /* MDIO_ACC: + * RA (Request/Ack) 0x01 (Request) + * RW (Read/Write) 0x01 (Write) + * PHY_ADDR 0x06 (LAN) + * REG_ADDR 0x00 (PHY_BCR: basic control register) + * PHY_DATA 0x8000 + * Reset - software reset + * LB (loop back) - normal + * SS (speed select) - 10 Mbit/s + * ANE (auto neg. enable) - enable + * PD (power down) - normal + * ISO (isolate) - normal + * RAN (restart auto neg.) - normal + * DM (duplex mode) - half duplex + * CT (collision test) - enable + */ + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000); + +#endif + + /* Make sure the CPU port is disabled for now. We + * don't want packets to get stacked for us until + * we enable DMA and are prepared to receive them. + */ + SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf); + + SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue); + + /* CRC GEN is enabled. + */ + regValue |= 0x00000200; + SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue); + + /* ADD TAG is disabled. + */ + SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); + regValue &= ~0x00000002; + SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue); +} + + +static void inca_dma_init(void) +{ + /* Switch off all DMA channels. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF); + + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF); + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF); + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF); + + /* Setup TX channel polling time. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME); + + /* Setup RX channel polling time. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME); + + /* ERRATA: write reset value into the DMA RX IMR register. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF); + + /* Just in case: disable all transmit interrupts also. + */ + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF); + + DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF); + DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF); +} + +#if defined(CONFIG_INCA_IP_SWITCH_AMDIX) +static int inca_amdix(void) +{ + u32 phyReg1 = 0; + u32 phyReg4 = 0; + u32 phyReg5 = 0; + u32 phyReg6 = 0; + u32 phyReg31 = 0; + u32 regEphy = 0; + int mdi_flag; + int retries; + + /* Setup GPIO pins. + */ + *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); + *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); + +#if 0 + /* Wait for signal. + */ + retries = WAIT_SIGNAL_RETRIES; + while (--retries) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (17 << 16)); /* PHY_MCSR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); + } while (phyReg1 & (1 << 31)); + + if (phyReg1 & (1 << 1)) { + /* Signal detected */ + break; + } + } + + if (!retries) + goto Fail; +#endif + + /* Set MDI mode. + */ + *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); + mdi_flag = 1; + + /* Wait for link. + */ + retries = WAIT_LINK_RETRIES; + while (--retries) { + udelay(LINK_RETRY_DELAY * 1000); + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (1 << 16)); /* PHY_BSR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); + } while (phyReg1 & (1 << 31)); + + if (phyReg1 & (1 << 2)) { + /* Link is up */ + break; + } else if (mdi_flag) { + /* Set MDIX mode */ + *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); + mdi_flag = 0; + } else { + /* Set MDI mode */ + *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX); + mdi_flag = 1; + } + } + + if (!retries) { + goto Fail; + } else { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (1 << 16)); /* PHY_BSR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1); + } while (phyReg1 & (1 << 31)); + + /* Auto-negotiation / Parallel detection complete + */ + if (phyReg1 & (1 << 5)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (31 << 16)); /* PHY_SCSR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31); + } while (phyReg31 & (1 << 31)); + + switch ((phyReg31 >> 2) & 0x7) { + case INCA_SWITCH_PHY_SPEED_10H: + /* 10Base-T Half-duplex */ + regEphy = 0; + break; + case INCA_SWITCH_PHY_SPEED_10F: + /* 10Base-T Full-duplex */ + regEphy = INCA_IP_Switch_EPHY_DL; + break; + case INCA_SWITCH_PHY_SPEED_100H: + /* 100Base-TX Half-duplex */ + regEphy = INCA_IP_Switch_EPHY_SL; + break; + case INCA_SWITCH_PHY_SPEED_100F: + /* 100Base-TX Full-duplex */ + regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL; + break; + } + + /* In case of Auto-negotiation, + * update the negotiated PAUSE support status + */ + if (phyReg1 & (1 << 3)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (6 << 16)); /* PHY_ANER */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6); + } while (phyReg6 & (1 << 31)); + + /* We are Autoneg-able. + * Is Link partner also able to autoneg? + */ + if (phyReg6 & (1 << 0)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (4 << 16)); /* PHY_ANAR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4); + } while (phyReg4 & (1 << 31)); + + /* We advertise PAUSE capab. + * Does link partner also advertise it? + */ + if (phyReg4 & (1 << 10)) { + SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, + (0x1 << 31) | /* RA */ + (0x0 << 30) | /* Read */ + (0x6 << 21) | /* LAN */ + (5 << 16)); /* PHY_ANLPAR */ + do { + SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5); + } while (phyReg5 & (1 << 31)); + + /* Link partner is PAUSE capab. + */ + if (phyReg5 & (1 << 10)) { + regEphy |= INCA_IP_Switch_EPHY_PL; + } + } + } + + } + + /* Link is up */ + regEphy |= INCA_IP_Switch_EPHY_LL; + + SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy); + } + } + + return 0; + +Fail: + printf("No Link on LAN port\n"); + return -1; +} +#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */ + +#endif diff --git a/drivers/keyboard.c b/drivers/keyboard.c new file mode 100644 index 000000000..9975202d7 --- /dev/null +++ b/drivers/keyboard.c @@ -0,0 +1,305 @@ +/*********************************************************************** + * + * (C) Copyright 2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * All rights reserved. + * + * Keyboard driver + * + ***********************************************************************/ + +#include + +#ifdef CONFIG_PS2KBD + +#include +#include + +#undef KBG_DEBUG + +#ifdef KBG_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + + +#define DEVNAME "kbd" + +#define LED_SCR 0x01 /* scroll lock led */ +#define LED_CAP 0x04 /* caps lock led */ +#define LED_NUM 0x02 /* num lock led */ + +#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */ + +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +int ps2ser_check(void); +#endif + +static volatile char kbd_buffer[KBD_BUFFER_LEN]; +static volatile int in_pointer = 0; +static volatile int out_pointer = 0; + +static unsigned char leds = 0; +static unsigned char num_lock = 0; +static unsigned char caps_lock = 0; +static unsigned char scroll_lock = 0; +static unsigned char shift = 0; +static unsigned char ctrl = 0; +static unsigned char alt = 0; +static unsigned char e0 = 0; + +/****************************************************************** + * Queue handling + ******************************************************************/ + +/* puts character in the queue and sets up the in and out pointer */ +static void kbd_put_queue(char data) +{ + if((in_pointer+1)==KBD_BUFFER_LEN) { + if(out_pointer==0) { + return; /* buffer full */ + } else{ + in_pointer=0; + } + } else { + if((in_pointer+1)==out_pointer) + return; /* buffer full */ + in_pointer++; + } + kbd_buffer[in_pointer]=data; + return; +} + +/* test if a character is in the queue */ +static int kbd_testc(void) +{ +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + /* no ISR is used, so received chars must be polled */ + ps2ser_check(); +#endif + if(in_pointer==out_pointer) + return(0); /* no data */ + else + return(1); +} + +/* gets the character from the queue */ +static int kbd_getc(void) +{ + char c; + while(in_pointer==out_pointer) { +#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + /* no ISR is used, so received chars must be polled */ + ps2ser_check(); +#endif + ;} + if((out_pointer+1)==KBD_BUFFER_LEN) + out_pointer=0; + else + out_pointer++; + c=kbd_buffer[out_pointer]; + return (int)c; + +} + +/* Simple translation table for the keys */ + +static unsigned char kbd_plain_xlate[] = { + 0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */ + 'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */ + 'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */ + 'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + +static unsigned char kbd_shift_xlate[] = { + 0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */ + 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */ + 'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */ + 'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + +static unsigned char kbd_ctrl_xlate[] = { + 0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */ + 0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */ + 0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */ + 0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */ + 0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */ + '2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */ + '\r',0xff,0xff + }; + + +void handle_scancode(unsigned char scancode) +{ + unsigned char keycode; + + /* Convert scancode to keycode */ + PRINTF("scancode %x\n",scancode); + if(scancode==0xe0) { + e0=1; /* special charakters */ + return; + } + if(e0==1) { + e0=0; /* delete flag */ + if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */ + ((scancode&0x7F)==0x1D)|| /* the right alt key */ + ((scancode&0x7F)==0x35)|| /* the right '/' key */ + ((scancode&0x7F)==0x1C) )) /* the right enter key */ + /* we swallow unknown e0 codes */ + return; + } + /* special cntrl keys */ + switch(scancode) { + case 0x2A: + case 0x36: /* shift pressed */ + shift=1; + return; /* do nothing else */ + case 0xAA: + case 0xB6: /* shift released */ + shift=0; + return; /* do nothing else */ + case 0x38: /* alt pressed */ + alt=1; + return; /* do nothing else */ + case 0xB8: /* alt released */ + alt=0; + return; /* do nothing else */ + case 0x1d: /* ctrl pressed */ + ctrl=1; + return; /* do nothing else */ + case 0x9d: /* ctrl released */ + ctrl=0; + return; /* do nothing else */ + case 0x46: /* scrollock pressed */ + scroll_lock=~scroll_lock; + if(scroll_lock==0) + leds&=~LED_SCR; /* switch LED off */ + else + leds|=LED_SCR; /* switch on LED */ + pckbd_leds(leds); + return; /* do nothing else */ + case 0x3A: /* capslock pressed */ + caps_lock=~caps_lock; + if(caps_lock==0) + leds&=~LED_CAP; /* switch caps_lock off */ + else + leds|=LED_CAP; /* switch on LED */ + pckbd_leds(leds); + return; + case 0x45: /* numlock pressed */ + num_lock=~num_lock; + if(num_lock==0) + leds&=~LED_NUM; /* switch LED off */ + else + leds|=LED_NUM; /* switch on LED */ + pckbd_leds(leds); + return; + case 0xC6: /* scroll lock released */ + case 0xC5: /* num lock released */ + case 0xBA: /* caps lock released */ + return; /* just swallow */ + } +#if 1 + if((scancode&0x80)==0x80) /* key released */ + return; +#else + if((scancode&0x80)==0x00) /* key pressed */ + return; + scancode &= ~0x80; +#endif + /* now, decide which table we need */ + if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow it */ + } + /* setup plain code first */ + keycode=kbd_plain_xlate[scancode]; + if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown caps-locked scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_shift_xlate[scancode]; + if(keycode<'A') { /* we only want the alphas capital */ + keycode=kbd_plain_xlate[scancode]; + } + } + if(shift==1) { /* shift overwrites caps_lock */ + if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown shifted scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_shift_xlate[scancode]; + } + if(ctrl==1) { /* ctrl overwrites caps_lock and shift */ + if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */ + PRINTF("unkown ctrl scancode %X\n",scancode); + return; /* swallow it */ + } + keycode=kbd_ctrl_xlate[scancode]; + } + /* check if valid keycode */ + if(keycode==0xff) { + PRINTF("unkown scancode %X\n",scancode); + return; /* swallow unknown codes */ + } + + kbd_put_queue(keycode); + PRINTF("%x\n",keycode); +} + +/****************************************************************** + * Init + ******************************************************************/ + +#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +extern int overwrite_console (void); +#define OVERWRITE_CONSOLE overwrite_console () +#else +#define OVERWRITE_CONSOLE 0 +#endif /* CFG_CONSOLE_OVERWRITE_ROUTINE */ + +int kbd_init (void) +{ + int error; + device_t kbddev ; + char *stdinname = getenv ("stdin"); + + if(kbd_init_hw()==-1) + return -1; + memset (&kbddev, 0, sizeof(kbddev)); + strcpy(kbddev.name, DEVNAME); + kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + kbddev.putc = NULL ; + kbddev.puts = NULL ; + kbddev.getc = kbd_getc ; + kbddev.tstc = kbd_testc ; + + error = device_register (&kbddev); + if(error==0) { + /* check if this is the standard input device */ + if(strcmp(stdinname,DEVNAME)==0) { + /* reassign the console */ + if(OVERWRITE_CONSOLE) { + return 1; + } + error=console_assign(stdin,DEVNAME); + if(error==0) + return 1; + else + return error; + } + return 1; + } + return error; +} + +#endif /* CONFIG_PS2KBD */ diff --git a/drivers/ks8695eth.c b/drivers/ks8695eth.c new file mode 100644 index 000000000..b598dd7f2 --- /dev/null +++ b/drivers/ks8695eth.c @@ -0,0 +1,238 @@ +/* + * ks8695eth.c -- KS8695 ethernet driver + * + * (C) Copyright 2004-2005, Greg Ungerer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/****************************************************************************/ + +#include + +#ifdef CONFIG_DRIVER_KS8695ETH +#include +#include +#include +#include + +/****************************************************************************/ + +/* + * Hardware register access to the KS8695 LAN ethernet port + * (well, it is the 4 port switch really). + */ +#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) +#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v) + +/****************************************************************************/ + +/* + * Define the descriptor in-memory data structures. + */ +struct ks8695_txdesc { + uint32_t owner; + uint32_t ctrl; + uint32_t addr; + uint32_t next; +}; + +struct ks8695_rxdesc { + uint32_t status; + uint32_t ctrl; + uint32_t addr; + uint32_t next; +}; + +/****************************************************************************/ + +/* + * Allocate local data structures to use for receiving and sending + * packets. Just to keep it all nice and simple. + */ + +#define TXDESCS 4 +#define RXDESCS 4 +#define BUFSIZE 2048 + +volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256))); +volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256))); +volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));; + +/****************************************************************************/ + +/* + * Ideally we want to use the MAC address stored in flash. + * But we do some sanity checks in case they are not present + * first. + */ +unsigned char eth_mac[] = { + 0x00, 0x13, 0xc6, 0x00, 0x00, 0x00 +}; + +void ks8695_getmac(void) +{ + unsigned char *fp; + int i; + + /* Check if flash MAC is valid */ + fp = (unsigned char *) 0x0201c000; + for (i = 0; (i < 6); i++) { + if ((fp[i] != 0) && (fp[i] != 0xff)) + break; + } + + /* If we found a valid looking MAC address then use it */ + if (i < 6) + memcpy(ð_mac[0], fp, 6); +} + +/****************************************************************************/ + +void eth_reset(bd_t *bd) +{ + int i; + + debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__); + + /* Reset the ethernet engines first */ + ks8695_write(KS8695_LAN_DMA_TX, 0x80000000); + ks8695_write(KS8695_LAN_DMA_RX, 0x80000000); + + ks8695_getmac(); + + /* Set MAC address */ + ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) | + (eth_mac[3] << 16) | (eth_mac[2] << 24))); + ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8))); + + /* Turn the 4 port switch on */ + i = ks8695_read(KS8695_SWITCH_CTRL0); + ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1)); + /* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */ + + /* Initialize descriptor rings */ + for (i = 0; (i < TXDESCS); i++) { + ks8695_tx[i].owner = 0; + ks8695_tx[i].ctrl = 0; + ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE]; + ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1]; + } + ks8695_tx[TXDESCS-1].ctrl = 0x02000000; + ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0]; + + for (i = 0; (i < RXDESCS); i++) { + ks8695_rx[i].status = 0x80000000; + ks8695_rx[i].ctrl = BUFSIZE - 4; + ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE]; + ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1]; + } + ks8695_rx[RXDESCS-1].ctrl |= 0x00080000; + ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0]; + + /* The KS8695 is pretty slow reseting the ethernets... */ + udelay(2000000); + + /* Enable the ethernet engine */ + ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]); + ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]); + ks8695_write(KS8695_LAN_DMA_TX, 0x3); + ks8695_write(KS8695_LAN_DMA_RX, 0x71); + ks8695_write(KS8695_LAN_DMA_RX_START, 0x1); + + printf("KS8695 ETHERNET: "); + for (i = 0; (i < 5); i++) { + bd->bi_enetaddr[i] = eth_mac[i]; + printf("%02x:", eth_mac[i]); + } + bd->bi_enetaddr[i] = eth_mac[i]; + printf("%02x\n", eth_mac[i]); +} + +/****************************************************************************/ + +int eth_init(bd_t *bd) +{ + debug ("%s(%d): eth_init()\n", __FILE__, __LINE__); + + eth_reset(bd); + return 0; +} + +/****************************************************************************/ + +void eth_halt(void) +{ + debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__); + + /* Reset the ethernet engines */ + ks8695_write(KS8695_LAN_DMA_TX, 0x80000000); + ks8695_write(KS8695_LAN_DMA_RX, 0x80000000); +} + +/****************************************************************************/ + +int eth_rx(void) +{ + volatile struct ks8695_rxdesc *dp; + int i, len = 0; + + debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__); + + for (i = 0; (i < RXDESCS); i++) { + dp= &ks8695_rx[i]; + if ((dp->status & 0x80000000) == 0) { + len = (dp->status & 0x7ff) - 4; + NetReceive((void *) dp->addr, len); + dp->status = 0x80000000; + ks8695_write(KS8695_LAN_DMA_RX_START, 0x1); + break; + } + } + + return len; +} + +/****************************************************************************/ + +int eth_send(volatile void *packet, int len) +{ + volatile struct ks8695_txdesc *dp; + static int next = 0; + + debug ("%s(%d): eth_send(packet=%x,len=%d)\n", __FILE__, __LINE__, + packet, len); + + dp = &ks8695_tx[next]; + memcpy((void *) dp->addr, (void *) packet, len); + + if (len < 64) { + memset((void *) (dp->addr + len), 0, 64-len); + len = 64; + } + + dp->ctrl = len | 0xe0000000; + dp->owner = 0x80000000; + + ks8695_write(KS8695_LAN_DMA_TX, 0x3); + ks8695_write(KS8695_LAN_DMA_TX_START, 0x1); + + if (++next >= TXDESCS) + next = 0; + + return len; +} + +#endif /* CONFIG_DRIVER_KS8695ETH */ diff --git a/drivers/lan91c96.c b/drivers/lan91c96.c new file mode 100644 index 000000000..a50c5f0ab --- /dev/null +++ b/drivers/lan91c96.c @@ -0,0 +1,967 @@ +/*------------------------------------------------------------------------ + * lan91c96.c + * This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based + * on the SMC91111 driver from U-boot. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Rolf Offermanns + * + * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + * Developed by Simple Network Magic Corporation (SNMC) + * Copyright (C) 1996 by Erik Stahlman (ES) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Information contained in this file was obtained from the LAN91C96 + * manual from SMC. To get a copy, if you really want one, you can find + * information under www.smsc.com. + * + * + * "Features" of the SMC chip: + * 6144 byte packet memory. ( for the 91C96 ) + * EEPROM for configuration + * AUI/TP selection ( mine has 10Base2/10BaseT select ) + * + * Arguments: + * io = for the base address + * irq = for the IRQ + * + * author: + * Erik Stahlman ( erik@vt.edu ) + * Daris A Nevil ( dnevil@snmc.com ) + * + * + * Hardware multicast code from Peter Cammaert ( pc@denkart.be ) + * + * Sources: + * o SMSC LAN91C96 databook (www.smsc.com) + * o smc91111.c (u-boot driver) + * o smc9194.c (linux kernel driver) + * o lan91c96.c (Intel Diagnostic Manager driver) + * + * History: + * 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version) + * for lan91c96 + *--------------------------------------------------------------------------- + */ + +#include +#include +#include "lan91c96.h" +#include + +#ifdef CONFIG_DRIVER_LAN91C96 + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/*------------------------------------------------------------------------ + * + * Configuration options, for the experienced user to change. + * + -------------------------------------------------------------------------*/ + +/* Use power-down feature of the chip */ +#define POWER_DOWN 0 + +/* + * Wait time for memory to be free. This probably shouldn't be + * tuned that much, as waiting for this means nothing else happens + * in the system +*/ +#define MEMORY_WAIT_TIME 16 + +#define SMC_DEBUG 0 + +#if (SMC_DEBUG > 2 ) +#define PRINTK3(args...) printf(args) +#else +#define PRINTK3(args...) +#endif + +#if SMC_DEBUG > 1 +#define PRINTK2(args...) printf(args) +#else +#define PRINTK2(args...) +#endif + +#ifdef SMC_DEBUG +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + + +/*------------------------------------------------------------------------ + * + * The internal workings of the driver. If you are changing anything + * here with the SMC stuff, you should have the datasheet and know + * what you are doing. + * + *------------------------------------------------------------------------ + */ +#define CARDNAME "LAN91C96" + +#define SMC_BASE_ADDRESS CONFIG_LAN91C96_BASE + +#define SMC_DEV_NAME "LAN91C96" +#define SMC_ALLOC_MAX_TRY 5 +#define SMC_TX_TIMEOUT 30 + +#define ETH_ZLEN 60 + +#ifdef CONFIG_LAN91C96_USE_32_BIT +#define USE_32_BIT 1 +#else +#undef USE_32_BIT +#endif + +/*----------------------------------------------------------------- + * + * The driver can be entered at any of the following entry points. + * + *----------------------------------------------------------------- + */ + +extern int eth_init (bd_t * bd); +extern void eth_halt (void); +extern int eth_rx (void); +extern int eth_send (volatile void *packet, int length); +#if 0 +static int smc_hw_init (void); +#endif + +/* + * This is called by register_netdev(). It is responsible for + * checking the portlist for the SMC9000 series chipset. If it finds + * one, then it will initialize the device, find the hardware information, + * and sets up the appropriate device parameters. + * NOTE: Interrupts are *OFF* when this procedure is called. + * + * NB:This shouldn't be static since it is referred to externally. + */ +int smc_init (void); + +/* + * This is called by unregister_netdev(). It is responsible for + * cleaning up before the driver is finally unregistered and discarded. + */ +void smc_destructor (void); + +/* + * The kernel calls this function when someone wants to use the device, + * typically 'ifconfig ethX up'. + */ +static int smc_open (bd_t *bd); + + +/* + * This is called by the kernel in response to 'ifconfig ethX down'. It + * is responsible for cleaning up everything that the open routine + * does, and maybe putting the card into a powerdown state. + */ +static int smc_close (void); + +/* + * This is a separate procedure to handle the receipt of a packet, to + * leave the interrupt code looking slightly cleaner + */ +static int smc_rcv (void); + +/* See if a MAC address is defined in the current environment. If so use it. If not + . print a warning and set the environment and other globals with the default. + . If an EEPROM is present it really should be consulted. +*/ +int smc_get_ethaddr(bd_t *bd); +int get_rom_mac(unsigned char *v_rom_mac); + +/* ------------------------------------------------------------ + * Internal routines + * ------------------------------------------------------------ + */ + +static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c }; + +/* + * This function must be called before smc_open() if you want to override + * the default mac address. + */ + +void smc_set_mac_addr (const unsigned char *addr) +{ + int i; + + for (i = 0; i < sizeof (smc_mac_addr); i++) { + smc_mac_addr[i] = addr[i]; + } +} + +/* + * smc_get_macaddr is no longer used. If you want to override the default + * mac address, call smc_get_mac_addr as a part of the board initialisation. + */ + +#if 0 +void smc_get_macaddr (byte * addr) +{ + /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ + unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); + int i; + + + for (i = 0; i < 6; i++) { + addr[0] = *(dnp1110_mac + 0); + addr[1] = *(dnp1110_mac + 1); + addr[2] = *(dnp1110_mac + 2); + addr[3] = *(dnp1110_mac + 3); + addr[4] = *(dnp1110_mac + 4); + addr[5] = *(dnp1110_mac + 5); + } +} +#endif /* 0 */ + +/*********************************************** + * Show available memory * + ***********************************************/ +void dump_memory_info (void) +{ + word mem_info; + word old_bank; + + old_bank = SMC_inw (LAN91C96_BANK_SELECT) & 0xF; + + SMC_SELECT_BANK (0); + mem_info = SMC_inw (LAN91C96_MIR); + PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048); + + SMC_SELECT_BANK (old_bank); +} + +/* + * A rather simple routine to print out a packet for debugging purposes. + */ +#if SMC_DEBUG > 2 +static void print_packet (byte *, int); +#endif + +/* #define tx_done(dev) 1 */ + + +/* this does a soft reset on the device */ +static void smc_reset (void); + +/* Enable Interrupts, Receive, and Transmit */ +static void smc_enable (void); + +/* this puts the device in an inactive state */ +static void smc_shutdown (void); + + +static int poll4int (byte mask, int timeout) +{ + int tmo = get_timer (0) + timeout * CFG_HZ; + int is_timeout = 0; + word old_bank = SMC_inw (LAN91C96_BANK_SELECT); + + PRINTK2 ("Polling...\n"); + SMC_SELECT_BANK (2); + while ((SMC_inw (LAN91C96_INT_STATS) & mask) == 0) { + if (get_timer (0) >= tmo) { + is_timeout = 1; + break; + } + } + + /* restore old bank selection */ + SMC_SELECT_BANK (old_bank); + + if (is_timeout) + return 1; + else + return 0; +} + +/* + * Function: smc_reset( void ) + * Purpose: + * This sets the SMC91111 chip to its normal state, hopefully from whatever + * mess that any other DOS driver has put it in. + * + * Maybe I should reset more registers to defaults in here? SOFTRST should + * do that for me. + * + * Method: + * 1. send a SOFT RESET + * 2. wait for it to finish + * 3. enable autorelease mode + * 4. reset the memory management unit + * 5. clear all interrupts + * +*/ +static void smc_reset (void) +{ + PRINTK2 ("%s:smc_reset\n", SMC_DEV_NAME); + + /* This resets the registers mostly to defaults, but doesn't + affect EEPROM. That seems unnecessary */ + SMC_SELECT_BANK (0); + SMC_outw (LAN91C96_RCR_SOFT_RST, LAN91C96_RCR); + + udelay (10); + + /* Disable transmit and receive functionality */ + SMC_outw (0, LAN91C96_RCR); + SMC_outw (0, LAN91C96_TCR); + + /* set the control register */ + SMC_SELECT_BANK (1); + SMC_outw (SMC_inw (LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8, + LAN91C96_CONTROL); + + /* Disable all interrupts */ + SMC_outb (0, LAN91C96_INT_MASK); +} + +/* + * Function: smc_enable + * Purpose: let the chip talk to the outside work + * Method: + * 1. Initialize the Memory Configuration Register + * 2. Enable the transmitter + * 3. Enable the receiver +*/ +static void smc_enable () +{ + PRINTK2 ("%s:smc_enable\n", SMC_DEV_NAME); + SMC_SELECT_BANK (0); + + /* Initialize the Memory Configuration Register. See page + 49 of the LAN91C96 data sheet for details. */ + SMC_outw (LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR); + + /* Initialize the Transmit Control Register */ + SMC_outw (LAN91C96_TCR_TXENA, LAN91C96_TCR); + /* Initialize the Receive Control Register + * FIXME: + * The promiscuous bit set because I could not receive ARP reply + * packets from the server when I send a ARP request. It only works + * when I set the promiscuous bit + */ + SMC_outw (LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR); +} + +/* + * Function: smc_shutdown + * Purpose: closes down the SMC91xxx chip. + * Method: + * 1. zero the interrupt mask + * 2. clear the enable receive flag + * 3. clear the enable xmit flags + * + * TODO: + * (1) maybe utilize power down mode. + * Why not yet? Because while the chip will go into power down mode, + * the manual says that it will wake up in response to any I/O requests + * in the register space. Empirical results do not show this working. + */ +static void smc_shutdown () +{ + PRINTK2 (CARDNAME ":smc_shutdown\n"); + + /* no more interrupts for me */ + SMC_SELECT_BANK (2); + SMC_outb (0, LAN91C96_INT_MASK); + + /* and tell the card to stay away from that nasty outside world */ + SMC_SELECT_BANK (0); + SMC_outb (0, LAN91C96_RCR); + SMC_outb (0, LAN91C96_TCR); +} + + +/* + * Function: smc_hardware_send_packet(struct net_device * ) + * Purpose: + * This sends the actual packet to the SMC9xxx chip. + * + * Algorithm: + * First, see if a saved_skb is available. + * ( this should NOT be called if there is no 'saved_skb' + * Now, find the packet number that the chip allocated + * Point the data pointers at it in memory + * Set the length word in the chip's memory + * Dump the packet to chip memory + * Check if a last byte is needed ( odd length packet ) + * if so, set the control flag right + * Tell the card to send it + * Enable the transmit interrupt, so I know if it failed + * Free the kernel data if I actually sent it. + */ +static int smc_send_packet (volatile void *packet, int packet_length) +{ + byte packet_no; + unsigned long ioaddr; + byte *buf; + int length; + int numPages; + int try = 0; + int time_out; + byte status; + + + PRINTK3 ("%s:smc_hardware_send_packet\n", SMC_DEV_NAME); + + length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; + + /* allocate memory + ** The MMU wants the number of pages to be the number of 256 bytes + ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) + ** + ** The 91C111 ignores the size bits, but the code is left intact + ** for backwards and future compatibility. + ** + ** Pkt size for allocating is data length +6 (for additional status + ** words, length and ctl!) + ** + ** If odd size then last byte is included in this header. + */ + numPages = ((length & 0xfffe) + 6); + numPages >>= 8; /* Divide by 256 */ + + if (numPages > 7) { + printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); + return 0; + } + + /* now, try to allocate the memory */ + + SMC_SELECT_BANK (2); + SMC_outw (LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU); + + again: + try++; + time_out = MEMORY_WAIT_TIME; + do { + status = SMC_inb (LAN91C96_INT_STATS); + if (status & LAN91C96_IST_ALLOC_INT) { + + SMC_outb (LAN91C96_IST_ALLOC_INT, LAN91C96_INT_STATS); + break; + } + } while (--time_out); + + if (!time_out) { + PRINTK2 ("%s: memory allocation, try %d failed ...\n", + SMC_DEV_NAME, try); + if (try < SMC_ALLOC_MAX_TRY) + goto again; + else + return 0; + } + + PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", + SMC_DEV_NAME, try); + + /* I can send the packet now.. */ + + ioaddr = SMC_BASE_ADDRESS; + + buf = (byte *) packet; + + /* If I get here, I _know_ there is a packet slot waiting for me */ + packet_no = SMC_inb (LAN91C96_ARR); + if (packet_no & LAN91C96_ARR_FAILED) { + /* or isn't there? BAD CHIP! */ + printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); + return 0; + } + + /* we have a packet address, so tell the card to use it */ + SMC_outb (packet_no, LAN91C96_PNR); + + /* point to the beginning of the packet */ + SMC_outw (LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); + + PRINTK3 ("%s: Trying to xmit packet of length %x\n", + SMC_DEV_NAME, length); + +#if SMC_DEBUG > 2 + printf ("Transmitting Packet\n"); + print_packet (buf, length); +#endif + + /* send the packet length ( +6 for status, length and ctl byte ) + and the status word ( set to zeros ) */ +#ifdef USE_32_BIT + SMC_outl ((length + 6) << 16, LAN91C96_DATA_HIGH); +#else + SMC_outw (0, LAN91C96_DATA_HIGH); + /* send the packet length ( +6 for status words, length, and ctl */ + SMC_outw ((length + 6), LAN91C96_DATA_HIGH); +#endif /* USE_32_BIT */ + + /* send the actual data + * I _think_ it's faster to send the longs first, and then + * mop up by sending the last word. It depends heavily + * on alignment, at least on the 486. Maybe it would be + * a good idea to check which is optimal? But that could take + * almost as much time as is saved? + */ +#ifdef USE_32_BIT + SMC_outsl (LAN91C96_DATA_HIGH, buf, length >> 2); + if (length & 0x2) + SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), + LAN91C96_DATA_HIGH); +#else + SMC_outsw (LAN91C96_DATA_HIGH, buf, (length) >> 1); +#endif /* USE_32_BIT */ + + /* Send the last byte, if there is one. */ + if ((length & 1) == 0) { + SMC_outw (0, LAN91C96_DATA_HIGH); + } else { + SMC_outw (buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH); + } + + /* and let the chipset deal with it */ + SMC_outw (LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU); + + /* poll for TX INT */ + if (poll4int (LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) { + /* sending failed */ + PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); + + /* release packet */ + SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + + /* wait for MMU getting ready (low) */ + while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) { + udelay (10); + } + + PRINTK2 ("MMU ready\n"); + + + return 0; + } else { + /* ack. int */ + SMC_outw (LAN91C96_IST_TX_INT, LAN91C96_INT_STATS); + + PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, length); + + /* release packet */ + SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + + /* wait for MMU getting ready (low) */ + while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) { + udelay (10); + } + + PRINTK2 ("MMU ready\n"); + } + + return length; +} + +/*------------------------------------------------------------------------- + * smc_destructor( struct net_device * dev ) + * Input parameters: + * dev, pointer to the device structure + * + * Output: + * None. + *-------------------------------------------------------------------------- + */ +void smc_destructor () +{ + PRINTK2 (CARDNAME ":smc_destructor\n"); +} + + +/* + * Open and Initialize the board + * + * Set up everything, reset the card, etc .. + * + */ +static int smc_open (bd_t *bd) +{ + int i, err; /* used to set hw ethernet address */ + + PRINTK2 ("%s:smc_open\n", SMC_DEV_NAME); + + /* reset the hardware */ + + smc_reset (); + smc_enable (); + + SMC_SELECT_BANK (1); + + err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */ + if (err < 0) { + memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */ + return (-1); /* upper code ignores this, but NOT bi_enetaddr */ + } +#ifdef USE_32_BIT + for (i = 0; i < 6; i += 2) { + word address; + + address = smc_mac_addr[i + 1] << 8; + address |= smc_mac_addr[i]; + SMC_outw (address, LAN91C96_IA0 + i); + } +#else + for (i = 0; i < 6; i++) + SMC_outb (smc_mac_addr[i], LAN91C96_IA0 + i); +#endif + return 0; +} + +/*------------------------------------------------------------- + * + * smc_rcv - receive a packet from the card + * + * There is ( at least ) a packet waiting to be read from + * chip-memory. + * + * o Read the status + * o If an error, record it + * o otherwise, read in the packet + *------------------------------------------------------------- + */ +static int smc_rcv () +{ + int packet_number; + word status; + word packet_length; + int is_error = 0; + +#ifdef USE_32_BIT + dword stat_len; +#endif + + + SMC_SELECT_BANK (2); + packet_number = SMC_inw (LAN91C96_FIFO); + + if (packet_number & LAN91C96_FIFO_RXEMPTY) { + return 0; + } + + PRINTK3 ("%s:smc_rcv\n", SMC_DEV_NAME); + /* start reading from the start of the packet */ + SMC_outw (LAN91C96_PTR_READ | LAN91C96_PTR_RCV | + LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); + + /* First two words are status and packet_length */ +#ifdef USE_32_BIT + stat_len = SMC_inl (LAN91C96_DATA_HIGH); + status = stat_len & 0xffff; + packet_length = stat_len >> 16; +#else + status = SMC_inw (LAN91C96_DATA_HIGH); + packet_length = SMC_inw (LAN91C96_DATA_HIGH); +#endif + + packet_length &= 0x07ff; /* mask off top bits */ + + PRINTK2 ("RCV: STATUS %4x LENGTH %4x\n", status, packet_length); + + if (!(status & FRAME_FILTER)) { + /* Adjust for having already read the first two words */ + packet_length -= 4; /*4; */ + + + /* set odd length for bug in LAN91C111, */ + /* which never sets RS_ODDFRAME */ + /* TODO ? */ + + +#ifdef USE_32_BIT + PRINTK3 (" Reading %d dwords (and %d bytes) \n", + packet_length >> 2, packet_length & 3); + /* QUESTION: Like in the TX routine, do I want + to send the DWORDs or the bytes first, or some + mixture. A mixture might improve already slow PIO + performance */ + SMC_insl (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 2); + /* read the left over bytes */ + if (packet_length & 3) { + int i; + + byte *tail = (byte *) (NetRxPackets[0] + (packet_length & ~3)); + dword leftover = SMC_inl (LAN91C96_DATA_HIGH); + + for (i = 0; i < (packet_length & 3); i++) + *tail++ = (byte) (leftover >> (8 * i)) & 0xff; + } +#else + PRINTK3 (" Reading %d words and %d byte(s) \n", + (packet_length >> 1), packet_length & 1); + SMC_insw (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 1); + +#endif /* USE_32_BIT */ + +#if SMC_DEBUG > 2 + printf ("Receiving Packet\n"); + print_packet (NetRxPackets[0], packet_length); +#endif + } else { + /* error ... */ + /* TODO ? */ + is_error = 1; + } + + while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + udelay (1); /* Wait until not busy */ + + /* error or good, tell the card to get rid of this packet */ + SMC_outw (LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU); + + while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + udelay (1); /* Wait until not busy */ + + if (!is_error) { + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], packet_length); + return packet_length; + } else { + return 0; + } + +} + +/*---------------------------------------------------- + * smc_close + * + * this makes the board clean up everything that it can + * and not talk to the outside world. Caused by + * an 'ifconfig ethX down' + * + -----------------------------------------------------*/ +static int smc_close () +{ + PRINTK2 ("%s:smc_close\n", SMC_DEV_NAME); + + /* clear everything */ + smc_shutdown (); + + return 0; +} + +#if SMC_DEBUG > 2 +static void print_packet (byte * buf, int length) +{ +#if 0 + int i; + int remainder; + int lines; + + printf ("Packet of length %d \n", length); + + lines = length / 16; + remainder = length % 16; + + for (i = 0; i < lines; i++) { + int cur; + + for (cur = 0; cur < 8; cur++) { + byte a, b; + + a = *(buf++); + b = *(buf++); + printf ("%02x%02x ", a, b); + } + printf ("\n"); + } + for (i = 0; i < remainder / 2; i++) { + byte a, b; + + a = *(buf++); + b = *(buf++); + printf ("%02x%02x ", a, b); + } + printf ("\n"); +#endif /* 0 */ +} +#endif /* SMC_DEBUG > 2 */ + +int eth_init (bd_t * bd) +{ + return (smc_open(bd)); +} + +void eth_halt () +{ + smc_close (); +} + +int eth_rx () +{ + return smc_rcv (); +} + +int eth_send (volatile void *packet, int length) +{ + return smc_send_packet (packet, length); +} + + +#if 0 +/*------------------------------------------------------------------------- + * smc_hw_init() + * + * Function: + * Reset and enable the device, check if the I/O space location + * is correct + * + * Input parameters: + * None + * + * Output: + * 0 --> success + * 1 --> error + *-------------------------------------------------------------------------- + */ +static int smc_hw_init () +{ + unsigned short status_test; + + /* The attribute register of the LAN91C96 is located at address + 0x0e000000 on the lubbock platform */ + volatile unsigned *attaddr = (unsigned *) (0x0e000000); + + /* first reset, then enable the device. Sequence is critical */ + attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_SRESET; + udelay (100); + attaddr[LAN91C96_ECOR] &= ~LAN91C96_ECOR_SRESET; + attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_ENABLE; + + /* force 16-bit mode */ + attaddr[LAN91C96_ECSR] &= ~LAN91C96_ECSR_IOIS8; + udelay (100); + + /* check if the I/O address is correct, the upper byte of the + bank select register should read 0x33 */ + + status_test = SMC_inw (LAN91C96_BANK_SELECT); + if ((status_test & 0xFF00) != 0x3300) { + printf ("Failed to initialize ethernetchip\n"); + return 1; + } + return 0; +} +#endif /* 0 */ + +#endif /* COMMANDS & CFG_NET */ + + +/* smc_get_ethaddr (bd_t * bd) + * + * This checks both the environment and the ROM for an ethernet address. If + * found, the environment takes precedence. + */ + +int smc_get_ethaddr (bd_t * bd) +{ + int env_size = 0; + int rom_valid = 0; + int env_present = 0; + int reg = 0; + char *s = NULL; + char *e = NULL; + char *v_mac, es[] = "11:22:33:44:55:66"; + char s_env_mac[64]; + uchar v_env_mac[6]; + uchar v_rom_mac[6]; + + env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac)); + if (env_size != sizeof(es)) { /* Ignore if env is bad or not set */ + printf ("\n*** Warning: ethaddr is not set properly, ignoring!!\n"); + } else { + env_present = 1; + s = s_env_mac; + + for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */ + v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + } + + rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */ + + if (!env_present) { /* if NO env */ + if (rom_valid) { /* but ROM is valid */ + v_mac = (char *)v_rom_mac; + sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", + v_mac[0], v_mac[1], v_mac[2], v_mac[3], + v_mac[4], v_mac[5]); + setenv ("ethaddr", s_env_mac); + } else { /* no env, bad ROM */ + printf ("\n*** ERROR: ethaddr is NOT set !!\n"); + return (-1); + } + } else { /* good env, don't care ROM */ + v_mac = (char *)v_env_mac; /* always use a good env over a ROM */ + } + + if (env_present && rom_valid) { /* if both env and ROM are good */ + if (memcmp (v_env_mac, v_rom_mac, 6) != 0) { + printf ("\nWarning: MAC addresses don't match:\n"); + printf ("\tHW MAC address: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + v_rom_mac[0], v_rom_mac[1], + v_rom_mac[2], v_rom_mac[3], + v_rom_mac[4], v_rom_mac[5] ); + printf ("\t\"ethaddr\" value: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + v_env_mac[0], v_env_mac[1], + v_env_mac[2], v_env_mac[3], + v_env_mac[4], v_env_mac[5]) ; + debug ("### Set MAC addr from environment\n"); + } + } + memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */ + smc_set_mac_addr ((unsigned char *)v_mac); /* use old function to update smc default */ + PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1], + v_mac[2], v_mac[3], v_mac[4], v_mac[5]); + return (0); +} + +/* + * get_rom_mac() + * Note, this has omly been tested for the OMAP730 P2. + */ + +int get_rom_mac (unsigned char *v_rom_mac) +{ +#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ + char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; + + memcpy (v_rom_mac, hw_mac_addr, 6); + return (1); +#else + int i; + SMC_SELECT_BANK (1); + for (i=0; i<6; i++) + { + v_rom_mac[i] = SMC_inb (LAN91C96_IA0 + i); + } + return (1); +#endif +} + +#endif /* CONFIG_DRIVER_LAN91C96 */ diff --git a/drivers/lan91c96.h b/drivers/lan91c96.h new file mode 100644 index 000000000..7d33a821f --- /dev/null +++ b/drivers/lan91c96.h @@ -0,0 +1,643 @@ +/*------------------------------------------------------------------------ + * lan91c96.h + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Rolf Offermanns + * Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + * Developed by Simple Network Magic Corporation (SNMC) + * Copyright (C) 1996 by Erik Stahlman (ES) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file contains register information and access macros for + * the LAN91C96 single chip ethernet controller. It is a modified + * version of the smc9111.h file. + * + * Information contained in this file was obtained from the LAN91C96 + * manual from SMC. To get a copy, if you really want one, you can find + * information under www.smsc.com. + * + * Authors + * Erik Stahlman ( erik@vt.edu ) + * Daris A Nevil ( dnevil@snmc.com ) + * + * History + * 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version) + * for lan91c96 + *------------------------------------------------------------------------- + */ +#ifndef _LAN91C96_H_ +#define _LAN91C96_H_ + +#include +#include +#include + +/* + * This function may be called by the board specific initialisation code + * in order to override the default mac address. + */ + +void smc_set_mac_addr(const unsigned char *addr); + + +/* I want some simple types */ + +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long int dword; + +/* + * DEBUGGING LEVELS + * + * 0 for normal operation + * 1 for slightly more details + * >2 for various levels of increasingly useless information + * 2 for interrupt tracking, status flags + * 3 for packet info + * 4 for complete packet dumps + */ +/*#define SMC_DEBUG 0 */ + +/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ + +#define SMC_IO_EXTENT 16 + +#ifdef CONFIG_PXA250 + +#ifdef CONFIG_LUBBOCK +#define SMC_IO_SHIFT 2 +#undef USE_32_BIT + +#else +#define SMC_IO_SHIFT 0 +#endif + +#define SMCREG(r) (SMC_BASE_ADDRESS+((r)<>= 8; \ + else __v &= 0xff; \ + __v; }) + +#define SMC_outl(d,r) (*((volatile dword *)SMCREG(r)) = d) +#define SMC_outw(d,r) (*((volatile word *)SMCREG(r)) = d) +#define SMC_outb(d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(__w,(r)&~1); \ + }) + +#define SMC_outsl(r,b,l) ({ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl( *(__b2 + __i), r ); \ + } \ + }) + +#define SMC_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw( *(__b2 + __i), r ); \ + } \ + }) + +#define SMC_insl(r,b,l) ({ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl(r); \ + SMC_inl(0); \ + }; \ + }) + +#define SMC_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw(r); \ + SMC_inw(0); \ + }; \ + }) + +#define SMC_insb(r,b,l) ({ int __i ; \ + byte *__b2; \ + __b2 = (byte *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inb(r); \ + SMC_inb(0); \ + }; \ + }) + +#else /* if not CONFIG_PXA250 */ + +/* + * We have only 16 Bit PCMCIA access on Socket 0 + */ + +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) + +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outb(d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(__w,(r)&~1); \ + }) +#if 0 +#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) +#else +#define SMC_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw( *(__b2 + __i), r); \ + } \ + }) +#endif + +#if 0 +#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) +#else +#define SMC_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw(r); \ + SMC_inw(0); \ + }; \ + }) +#endif + +#endif + +/* + **************************************************************************** + * Bank Select Field + **************************************************************************** + */ +#define LAN91C96_BANK_SELECT 14 /* Bank Select Register */ +#define LAN91C96_BANKSELECT (0x3UC << 0) +#define BANK0 0x00 +#define BANK1 0x01 +#define BANK2 0x02 +#define BANK3 0x03 +#define BANK4 0x04 + +/* + **************************************************************************** + * EEPROM Addresses. + **************************************************************************** + */ +#define EEPROM_MAC_OFFSET_1 0x6020 +#define EEPROM_MAC_OFFSET_2 0x6021 +#define EEPROM_MAC_OFFSET_3 0x6022 + +/* + **************************************************************************** + * Bank 0 Register Map in I/O Space + **************************************************************************** + */ +#define LAN91C96_TCR 0 /* Transmit Control Register */ +#define LAN91C96_EPH_STATUS 2 /* EPH Status Register */ +#define LAN91C96_RCR 4 /* Receive Control Register */ +#define LAN91C96_COUNTER 6 /* Counter Register */ +#define LAN91C96_MIR 8 /* Memory Information Register */ +#define LAN91C96_MCR 10 /* Memory Configuration Register */ + +/* + **************************************************************************** + * Transmit Control Register - Bank 0 - Offset 0 + **************************************************************************** + */ +#define LAN91C96_TCR_TXENA (0x1U << 0) +#define LAN91C96_TCR_LOOP (0x1U << 1) +#define LAN91C96_TCR_FORCOL (0x1U << 2) +#define LAN91C96_TCR_TXP_EN (0x1U << 3) +#define LAN91C96_TCR_PAD_EN (0x1U << 7) +#define LAN91C96_TCR_NOCRC (0x1U << 8) +#define LAN91C96_TCR_MON_CSN (0x1U << 10) +#define LAN91C96_TCR_FDUPLX (0x1U << 11) +#define LAN91C96_TCR_STP_SQET (0x1U << 12) +#define LAN91C96_TCR_EPH_LOOP (0x1U << 13) +#define LAN91C96_TCR_ETEN_TYPE (0x1U << 14) +#define LAN91C96_TCR_FDSE (0x1U << 15) + +/* + **************************************************************************** + * EPH Status Register - Bank 0 - Offset 2 + **************************************************************************** + */ +#define LAN91C96_EPHSR_TX_SUC (0x1U << 0) +#define LAN91C96_EPHSR_SNGL_COL (0x1U << 1) +#define LAN91C96_EPHSR_MUL_COL (0x1U << 2) +#define LAN91C96_EPHSR_LTX_MULT (0x1U << 3) +#define LAN91C96_EPHSR_16COL (0x1U << 4) +#define LAN91C96_EPHSR_SQET (0x1U << 5) +#define LAN91C96_EPHSR_LTX_BRD (0x1U << 6) +#define LAN91C96_EPHSR_TX_DEFR (0x1U << 7) +#define LAN91C96_EPHSR_WAKEUP (0x1U << 8) +#define LAN91C96_EPHSR_LATCOL (0x1U << 9) +#define LAN91C96_EPHSR_LOST_CARR (0x1U << 10) +#define LAN91C96_EPHSR_EXC_DEF (0x1U << 11) +#define LAN91C96_EPHSR_CTR_ROL (0x1U << 12) + +#define LAN91C96_EPHSR_LINK_OK (0x1U << 14) +#define LAN91C96_EPHSR_TX_UNRN (0x1U << 15) + +#define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \ + LAN91C96_EPHSR_MUL_COL | \ + LAN91C96_EPHSR_16COL | \ + LAN91C96_EPHSR_SQET | \ + LAN91C96_EPHSR_TX_DEFR | \ + LAN91C96_EPHSR_LATCOL | \ + LAN91C96_EPHSR_LOST_CARR | \ + LAN91C96_EPHSR_EXC_DEF | \ + LAN91C96_EPHSR_LINK_OK | \ + LAN91C96_EPHSR_TX_UNRN) + +/* + **************************************************************************** + * Receive Control Register - Bank 0 - Offset 4 + **************************************************************************** + */ +#define LAN91C96_RCR_RX_ABORT (0x1U << 0) +#define LAN91C96_RCR_PRMS (0x1U << 1) +#define LAN91C96_RCR_ALMUL (0x1U << 2) +#define LAN91C96_RCR_RXEN (0x1U << 8) +#define LAN91C96_RCR_STRIP_CRC (0x1U << 9) +#define LAN91C96_RCR_FILT_CAR (0x1U << 14) +#define LAN91C96_RCR_SOFT_RST (0x1U << 15) + +/* + **************************************************************************** + * Counter Register - Bank 0 - Offset 6 + **************************************************************************** + */ +#define LAN91C96_ECR_SNGL_COL (0xFU << 0) +#define LAN91C96_ECR_MULT_COL (0xFU << 5) +#define LAN91C96_ECR_DEF_TX (0xFU << 8) +#define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12) + +/* + **************************************************************************** + * Memory Information Register - Bank 0 - OFfset 8 + **************************************************************************** + */ +#define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */ + +/* + **************************************************************************** + * Memory Configuration Register - Bank 0 - Offset 10 + **************************************************************************** + */ +#define LAN91C96_MCR_MEM_RES (0xFFU << 0) +#define LAN91C96_MCR_MEM_MULT (0x3U << 9) +#define LAN91C96_MCR_HIGH_ID (0x3U << 12) + +#define LAN91C96_MCR_TRANSMIT_PAGES 0x6 + +/* + **************************************************************************** + * Bank 1 Register Map in I/O Space + **************************************************************************** + */ +#define LAN91C96_CONFIG 0 /* Configuration Register */ +#define LAN91C96_BASE 2 /* Base Address Register */ +#define LAN91C96_IA0 4 /* Individual Address Register - 0 */ +#define LAN91C96_IA1 5 /* Individual Address Register - 1 */ +#define LAN91C96_IA2 6 /* Individual Address Register - 2 */ +#define LAN91C96_IA3 7 /* Individual Address Register - 3 */ +#define LAN91C96_IA4 8 /* Individual Address Register - 4 */ +#define LAN91C96_IA5 9 /* Individual Address Register - 5 */ +#define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */ +#define LAN91C96_CONTROL 12 /* Control Register */ + +/* + **************************************************************************** + * Configuration Register - Bank 1 - Offset 0 + **************************************************************************** + */ +#define LAN91C96_CR_INT_SEL0 (0x1U << 1) +#define LAN91C96_CR_INT_SEL1 (0x1U << 2) +#define LAN91C96_CR_RES (0x3U << 3) +#define LAN91C96_CR_DIS_LINK (0x1U << 6) +#define LAN91C96_CR_16BIT (0x1U << 7) +#define LAN91C96_CR_AUI_SELECT (0x1U << 8) +#define LAN91C96_CR_SET_SQLCH (0x1U << 9) +#define LAN91C96_CR_FULL_STEP (0x1U << 10) +#define LAN91C96_CR_NO_WAIT (0x1U << 12) + +/* + **************************************************************************** + * Base Address Register - Bank 1 - Offset 2 + **************************************************************************** + */ +#define LAN91C96_BAR_RA_BITS (0x27U << 0) +#define LAN91C96_BAR_ROM_SIZE (0x1U << 6) +#define LAN91C96_BAR_A_BITS (0xFFU << 8) + +/* + **************************************************************************** + * Control Register - Bank 1 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_CTR_STORE (0x1U << 0) +#define LAN91C96_CTR_RELOAD (0x1U << 1) +#define LAN91C96_CTR_EEPROM (0x1U << 2) +#define LAN91C96_CTR_TE_ENABLE (0x1U << 5) +#define LAN91C96_CTR_CR_ENABLE (0x1U << 6) +#define LAN91C96_CTR_LE_ENABLE (0x1U << 7) +#define LAN91C96_CTR_BIT_8 (0x1U << 8) +#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11) +#define LAN91C96_CTR_WAKEUP_EN (0x1U << 12) +#define LAN91C96_CTR_PWRDN (0x1U << 13) +#define LAN91C96_CTR_RCV_BAD (0x1U << 14) + +/* + **************************************************************************** + * Bank 2 Register Map in I/O Space + **************************************************************************** + */ +#define LAN91C96_MMU 0 /* MMU Command Register */ +#define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */ +#define LAN91C96_PNR 2 /* Packet Number Register */ +#define LAN91C96_ARR 3 /* Allocation Result Register */ +#define LAN91C96_FIFO 4 /* FIFO Ports Register */ +#define LAN91C96_POINTER 6 /* Pointer Register */ +#define LAN91C96_DATA_HIGH 8 /* Data High Register */ +#define LAN91C96_DATA_LOW 10 /* Data Low Register */ +#define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */ +#define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */ +#define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */ + +/* + **************************************************************************** + * MMU Command Register - Bank 2 - Offset 0 + **************************************************************************** + */ +#define LAN91C96_MMUCR_NO_BUSY (0x1U << 0) +#define LAN91C96_MMUCR_N1 (0x1U << 1) +#define LAN91C96_MMUCR_N2 (0x1U << 2) +#define LAN91C96_MMUCR_COMMAND (0xFU << 4) +#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */ +#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */ +#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */ +#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */ +#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */ +#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */ +#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */ +#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */ + +/* + **************************************************************************** + * Auto Tx Start Register - Bank 2 - Offset 1 + **************************************************************************** + */ +#define LAN91C96_AUTOTX (0xFFU << 0) + +/* + **************************************************************************** + * Packet Number Register - Bank 2 - Offset 2 + **************************************************************************** + */ +#define LAN91C96_PNR_TX (0x1FU << 0) + +/* + **************************************************************************** + * Allocation Result Register - Bank 2 - Offset 3 + **************************************************************************** + */ +#define LAN91C96_ARR_ALLOC_PN (0x7FU << 0) +#define LAN91C96_ARR_FAILED (0x1U << 7) + +/* + **************************************************************************** + * FIFO Ports Register - Bank 2 - Offset 4 + **************************************************************************** + */ +#define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0) +#define LAN91C96_FIFO_TEMPTY (0x1U << 7) +#define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8) +#define LAN91C96_FIFO_RXEMPTY (0x1U << 15) + +/* + **************************************************************************** + * Pointer Register - Bank 2 - Offset 6 + **************************************************************************** + */ +#define LAN91C96_PTR_LOW (0xFFU << 0) +#define LAN91C96_PTR_HIGH (0x7U << 8) +#define LAN91C96_PTR_AUTO_TX (0x1U << 11) +#define LAN91C96_PTR_ETEN (0x1U << 12) +#define LAN91C96_PTR_READ (0x1U << 13) +#define LAN91C96_PTR_AUTO_INCR (0x1U << 14) +#define LAN91C96_PTR_RCV (0x1U << 15) + +#define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \ + LAN91C96_PTR_AUTO_INCR | \ + LAN91C96_PTR_READ) + +/* + **************************************************************************** + * Data Register - Bank 2 - Offset 8 + **************************************************************************** + */ +#define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */ +#define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */ + +/* + **************************************************************************** + * Interrupt Status Register - Bank 2 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_IST_RCV_INT (0x1U << 0) +#define LAN91C96_IST_TX_INT (0x1U << 1) +#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2) +#define LAN91C96_IST_ALLOC_INT (0x1U << 3) +#define LAN91C96_IST_RX_OVRN_INT (0x1U << 4) +#define LAN91C96_IST_EPH_INT (0x1U << 5) +#define LAN91C96_IST_ERCV_INT (0x1U << 6) +#define LAN91C96_IST_RX_IDLE_INT (0x1U << 7) + +/* + **************************************************************************** + * Interrupt Acknowledge Register - Bank 2 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_ACK_TX_INT (0x1U << 1) +#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2) +#define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4) +#define LAN91C96_ACK_ERCV_INT (0x1U << 6) + +/* + **************************************************************************** + * Interrupt Mask Register - Bank 2 - Offset 13 + **************************************************************************** + */ +#define LAN91C96_MSK_RCV_INT (0x1U << 0) +#define LAN91C96_MSK_TX_INT (0x1U << 1) +#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2) +#define LAN91C96_MSK_ALLOC_INT (0x1U << 3) +#define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4) +#define LAN91C96_MSK_EPH_INT (0x1U << 5) +#define LAN91C96_MSK_ERCV_INT (0x1U << 6) +#define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7) + +/* + **************************************************************************** + * Bank 3 Register Map in I/O Space + ************************************************************************** + */ +#define LAN91C96_MGMT_MDO (0x1U << 0) +#define LAN91C96_MGMT_MDI (0x1U << 1) +#define LAN91C96_MGMT_MCLK (0x1U << 2) +#define LAN91C96_MGMT_MDOE (0x1U << 3) +#define LAN91C96_MGMT_LOW_ID (0x3U << 4) +#define LAN91C96_MGMT_IOS0 (0x1U << 8) +#define LAN91C96_MGMT_IOS1 (0x1U << 9) +#define LAN91C96_MGMT_IOS2 (0x1U << 10) +#define LAN91C96_MGMT_nXNDEC (0x1U << 11) +#define LAN91C96_MGMT_HIGH_ID (0x3U << 12) + +/* + **************************************************************************** + * Revision Register - Bank 3 - Offset 10 + **************************************************************************** + */ +#define LAN91C96_REV_REVID (0xFU << 0) +#define LAN91C96_REV_CHIPID (0xFU << 4) + +/* + **************************************************************************** + * Early RCV Register - Bank 3 - Offset 12 + **************************************************************************** + */ +#define LAN91C96_ERCV_THRESHOLD (0x1FU << 0) +#define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7) + +/* + **************************************************************************** + * PCMCIA Configuration Registers + **************************************************************************** + */ +#define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */ +#define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */ + +/* + **************************************************************************** + * PCMCIA Ethernet Configuration Option Register (ECOR) + **************************************************************************** + */ +#define LAN91C96_ECOR_ENABLE (0x1U << 0) +#define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2) +#define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6) +#define LAN91C96_ECOR_SRESET (0x1U << 7) + +/* + **************************************************************************** + * PCMCIA Ethernet Configuration and Status Register (ECSR) + **************************************************************************** + */ +#define LAN91C96_ECSR_INTR (0x1U << 1) +#define LAN91C96_ECSR_PWRDWN (0x1U << 2) +#define LAN91C96_ECSR_IOIS8 (0x1U << 5) + +/* + **************************************************************************** + * Receive Frame Status Word - See page 38 of the LAN91C96 specification. + **************************************************************************** + */ +#define LAN91C96_TOO_SHORT (0x1U << 10) +#define LAN91C96_TOO_LONG (0x1U << 11) +#define LAN91C96_ODD_FRM (0x1U << 12) +#define LAN91C96_BAD_CRC (0x1U << 13) +#define LAN91C96_BROD_CAST (0x1U << 14) +#define LAN91C96_ALGN_ERR (0x1U << 15) + +#define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR) + +/* + **************************************************************************** + * Default MAC Address + **************************************************************************** + */ +#define MAC_DEF_HI 0x0800 +#define MAC_DEF_MED 0x3333 +#define MAC_DEF_LO 0x0100 + +/* + **************************************************************************** + * Default I/O Signature - 0x33 + **************************************************************************** + */ +#define LAN91C96_LOW_SIGNATURE (0x33U << 0) +#define LAN91C96_HIGH_SIGNATURE (0x33U << 8) +#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE) + +#define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */ +#define ETHERNET_MAX_LENGTH 1514 + + +/*------------------------------------------------------------------------- + * I define some macros to make it easier to do somewhat common + * or slightly complicated, repeated tasks. + *------------------------------------------------------------------------- + */ + +/* select a register bank, 0 to 3 */ + +#define SMC_SELECT_BANK(x) { SMC_outw( x, LAN91C96_BANK_SELECT ); } + +/* this enables an interrupt in the interrupt mask register */ +#define SMC_ENABLE_INT(x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(2);\ + mask = SMC_inb( LAN91C96_INT_MASK );\ + mask |= (x);\ + SMC_outb( mask, LAN91C96_INT_MASK ); \ +} + +/* this disables an interrupt from the interrupt mask register */ + +#define SMC_DISABLE_INT(x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(2);\ + mask = SMC_inb( LAN91C96_INT_MASK );\ + mask &= ~(x);\ + SMC_outb( mask, LAN91C96_INT_MASK ); \ +} + +/*---------------------------------------------------------------------- + * Define the interrupts that I want to receive from the card + * + * I want: + * LAN91C96_IST_EPH_INT, for nasty errors + * LAN91C96_IST_RCV_INT, for happy received packets + * LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver + *------------------------------------------------------------------------- + */ +#define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT) + +#endif /* _LAN91C96_H_ */ diff --git a/drivers/mpc8xx_pcmcia.c b/drivers/mpc8xx_pcmcia.c new file mode 100644 index 000000000..399a719e5 --- /dev/null +++ b/drivers/mpc8xx_pcmcia.c @@ -0,0 +1,304 @@ +#include +#if defined(CONFIG_8xx) +#include +#endif +#include + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#if defined(CONFIG_8xx) && defined(CONFIG_PCMCIA) + +#if defined(CONFIG_IDE_8xx_PCCARD) +extern int check_ide_device (int slot); +#endif + +extern int pcmcia_hardware_enable (int slot); +extern int pcmcia_voltage_set(int slot, int vcc, int vpp); + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +extern int pcmcia_hardware_disable(int slot); +#endif + +static u_int m8xx_get_graycode(u_int size); +#if 0 /* Disabled */ +static u_int m8xx_get_speed(u_int ns, u_int is_io); +#endif + +/* look up table for pgcrx registers */ +u_int *pcmcia_pgcrx[2] = { + &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcra, + &((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb, +}; + +/* + * Search this table to see if the windowsize is + * supported... + */ + +#define M8XX_SIZES_NO 32 + +static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] = +{ 0x00000001, 0x00000002, 0x00000008, 0x00000004, + 0x00000080, 0x00000040, 0x00000010, 0x00000020, + 0x00008000, 0x00004000, 0x00001000, 0x00002000, + 0x00000100, 0x00000200, 0x00000800, 0x00000400, + + 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x01000000, 0x02000000, 0xffffffff, 0x04000000, + 0x00010000, 0x00020000, 0x00080000, 0x00040000, + 0x00800000, 0x00400000, 0x00100000, 0x00200000 }; + + +/* -------------------------------------------------------------------- */ + +#ifdef CONFIG_HMI10 +#define HMI10_FRAM_TIMING ( PCMCIA_SHT(2) \ + | PCMCIA_SST(2) \ + | PCMCIA_SL(4)) +#endif + +#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU) +#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(9) \ + | PCMCIA_SST(3) \ + | PCMCIA_SL(12)) +#else +#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(2) \ + | PCMCIA_SST(4) \ + | PCMCIA_SL(9)) +#endif + +/* -------------------------------------------------------------------- */ + +int pcmcia_on (void) +{ + u_long reg, base; + pcmcia_win_t *win; + u_int slotbit; + u_int rc, slot; + int i; + + debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n"); + + /* intialize the fixed memory windows */ + win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0); + base = CFG_PCMCIA_MEM_ADDR; + + if((reg = m8xx_get_graycode(CFG_PCMCIA_MEM_SIZE)) == -1) { + printf ("Cannot set window size to 0x%08x\n", + CFG_PCMCIA_MEM_SIZE); + return (1); + } + + slotbit = PCMCIA_SLOT_x; + for (i=0; ibr = base; + +#if (PCMCIA_SOCKETS_NO == 2) + if (i == 4) /* Another slot starting from win 4 */ + slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B); +#endif + switch (i) { +#ifdef CONFIG_IDE_8xx_PCCARD + case 4: +#ifdef CONFIG_HMI10 + { /* map FRAM area */ + win->or = ( PCMCIA_BSIZE_256K + | PCMCIA_PPS_8 + | PCMCIA_PRS_ATTR + | slotbit + | PCMCIA_PV + | HMI10_FRAM_TIMING ); + break; + } +#endif + case 0: { /* map attribute memory */ + win->or = ( PCMCIA_BSIZE_64M + | PCMCIA_PPS_8 + | PCMCIA_PRS_ATTR + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } + case 5: + case 1: { /* map I/O window for data reg */ + win->or = ( PCMCIA_BSIZE_1K + | PCMCIA_PPS_16 + | PCMCIA_PRS_IO + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } + case 6: + case 2: { /* map I/O window for cmd/ctrl reg block */ + win->or = ( PCMCIA_BSIZE_1K + | PCMCIA_PPS_8 + | PCMCIA_PRS_IO + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } +#endif /* CONFIG_IDE_8xx_PCCARD */ +#ifdef CONFIG_HMI10 + case 3: { /* map I/O window for 4xUART data/ctrl */ + win->br += 0x40000; + win->or = ( PCMCIA_BSIZE_256K + | PCMCIA_PPS_8 + | PCMCIA_PRS_IO + | slotbit + | PCMCIA_PV + | CFG_PCMCIA_TIMING ); + break; + } +#endif /* CONFIG_HMI10 */ + default: /* set to not valid */ + win->or = 0; + break; + } + + debug ("MemWin %d: PBR 0x%08lX POR %08lX\n", + i, win->br, win->or); + base += CFG_PCMCIA_MEM_SIZE; + ++win; + } + + for (i=0, rc=0, slot=_slot_; iim_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_); + ((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_); + + /* turn off interrupt and disable CxOE */ + PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE; + + /* turn off memory windows */ + win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0); + + for (i=0; ior = 0; + ++win; + } + + /* turn off voltage */ + pcmcia_voltage_set(_slot_, 0, 0); + + /* disable external hardware */ + printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n"); + pcmcia_hardware_disable(_slot_); + return 0; +} +#endif /* CFG_CMD_PCMCIA */ + + +static u_int m8xx_get_graycode(u_int size) +{ + u_int k; + + for (k = 0; k < M8XX_SIZES_NO; k++) { + if(m8xx_size_to_gray[k] == size) + break; + } + + if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) + k = -1; + + return k; +} + +#if 0 + +#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) + +/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. + * SYPCR is write once only, therefore must the slowest memory be faster + * than the bus monitor or we will get a machine check due to the bus timeout. + */ +#undef PCMCIA_BMT_LIMIT +#define PCMCIA_BMT_LIMIT (6*8) +#endif + +static u_int m8xx_get_speed(u_int ns, u_int is_io) +{ + u_int reg, clocks, psst, psl, psht; + + if(!ns) { + + /* + * We get called with IO maps setup to 0ns + * if not specified by the user. + * They should be 255ns. + */ + + if(is_io) + ns = 255; + else + ns = 100; /* fast memory if 0 */ + } + + /* + * In PSST, PSL, PSHT fields we tell the controller + * timing parameters in CLKOUT clock cycles. + * CLKOUT is the same as GCLK2_50. + */ + + /* how we want to adjust the timing - in percent */ + +#define ADJ 180 /* 80 % longer accesstime - to be sure */ + + clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000; + clocks = (clocks * ADJ) / (100*1000); + + if(clocks >= PCMCIA_BMT_LIMIT) { + DEBUG(0, "Max access time limit reached\n"); + clocks = PCMCIA_BMT_LIMIT-1; + } + + psst = clocks / 7; /* setup time */ + psht = clocks / 7; /* hold time */ + psl = (clocks * 5) / 7; /* strobe length */ + + psst += clocks - (psst + psht + psl); + + reg = psst << 12; + reg |= psl << 7; + reg |= psht << 16; + + return reg; +} +#endif /* 0 */ + +#endif /* CONFIG_8xx && CONFIG_PCMCIA */ diff --git a/drivers/mw_eeprom.c b/drivers/mw_eeprom.c new file mode 100644 index 000000000..2a1f48984 --- /dev/null +++ b/drivers/mw_eeprom.c @@ -0,0 +1,241 @@ +/* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */ + +#include +#include + + +#ifdef CONFIG_MW_EEPROM + +/* + * Serial EEPROM opcodes, including start bit + */ +#define EEP_OPC_ERASE 0x7 /* 3-bit opcode */ +#define EEP_OPC_WRITE 0x5 /* 3-bit opcode */ +#define EEP_OPC_READ 0x6 /* 3-bit opcode */ + +#define EEP_OPC_ERASE_ALL 0x12 /* 5-bit opcode */ +#define EEP_OPC_ERASE_EN 0x13 /* 5-bit opcode */ +#define EEP_OPC_WRITE_ALL 0x11 /* 5-bit opcode */ +#define EEP_OPC_ERASE_DIS 0x10 /* 5-bit opcode */ + +static int addrlen; + +static void mw_eeprom_select(int dev) +{ + ssi_set_interface(2048, 0, 0, 0); + ssi_chip_select(0); + udelay(1); + ssi_chip_select(dev); + udelay(1); +} + +static int mw_eeprom_size(int dev) +{ + int x; + u16 res; + + mw_eeprom_select(dev); + ssi_tx_byte(EEP_OPC_READ); + + res = ssi_txrx_byte(0) << 8; + res |= ssi_rx_byte(); + for (x = 0; x < 16; x++) { + if (! (res & 0x8000)) { + break; + } + res <<= 1; + } + ssi_chip_select(0); + + return x; +} + +int mw_eeprom_erase_enable(int dev) +{ + mw_eeprom_select(dev); + ssi_tx_byte(EEP_OPC_ERASE_EN); + ssi_tx_byte(0); + udelay(1); + ssi_chip_select(0); + + return 0; +} + +int mw_eeprom_erase_disable(int dev) +{ + mw_eeprom_select(dev); + ssi_tx_byte(EEP_OPC_ERASE_DIS); + ssi_tx_byte(0); + udelay(1); + ssi_chip_select(0); + + return 0; +} + + +u32 mw_eeprom_read_word(int dev, int addr) +{ + u16 rcv; + u16 res; + int bits; + + mw_eeprom_select(dev); + ssi_tx_byte((EEP_OPC_READ << 5) | ((addr >> (addrlen - 5)) & 0x1f)); + rcv = ssi_txrx_byte(addr << (13 - addrlen)); + res = rcv << (16 - addrlen); + bits = 4 + addrlen; + + while (bits>0) { + rcv = ssi_rx_byte(); + if (bits > 7) { + res |= rcv << (bits - 8); + } else { + res |= rcv >> (8 - bits); + } + bits -= 8; + } + + ssi_chip_select(0); + + return res; +} + +int mw_eeprom_write_word(int dev, int addr, u16 data) +{ + u8 byte1=0; + u8 byte2=0; + + mw_eeprom_erase_enable(dev); + mw_eeprom_select(dev); + + switch (addrlen) { + case 6: + byte1 = EEP_OPC_WRITE >> 2; + byte2 = (EEP_OPC_WRITE << 6)&0xc0; + byte2 |= addr; + break; + case 7: + byte1 = EEP_OPC_WRITE >> 1; + byte2 = (EEP_OPC_WRITE << 7)&0x80; + byte2 |= addr; + break; + case 8: + byte1 = EEP_OPC_WRITE; + byte2 = addr; + break; + case 9: + byte1 = EEP_OPC_WRITE << 1; + byte1 |= addr >> 8; + byte2 = addr & 0xff; + break; + case 10: + byte1 = EEP_OPC_WRITE << 2; + byte1 |= addr >> 8; + byte2 = addr & 0xff; + break; + default: + printf("Unsupported number of address bits: %d\n", addrlen); + return -1; + + } + + ssi_tx_byte(byte1); + ssi_tx_byte(byte2); + ssi_tx_byte(data >> 8); + ssi_tx_byte(data & 0xff); + ssi_chip_select(0); + udelay(10000); /* Worst case */ + mw_eeprom_erase_disable(dev); + + return 0; +} + + +int mw_eeprom_write(int dev, int addr, u8 *buffer, int len) +{ + int done; + + done = 0; + if (addr & 1) { + u16 temp = mw_eeprom_read_word(dev, addr >> 1); + temp &= 0xff00; + temp |= buffer[0]; + + mw_eeprom_write_word(dev, addr >> 1, temp); + len--; + addr++; + buffer++; + done++; + } + + while (len <= 2) { + mw_eeprom_write_word(dev, addr >> 1, *(u16*)buffer); + len-=2; + addr+=2; + buffer+=2; + done+=2; + } + + if (len) { + u16 temp = mw_eeprom_read_word(dev, addr >> 1); + temp &= 0x00ff; + temp |= buffer[0] << 8; + + mw_eeprom_write_word(dev, addr >> 1, temp); + len--; + addr++; + buffer++; + done++; + } + + return done; +} + + +int mw_eeprom_read(int dev, int addr, u8 *buffer, int len) +{ + int done; + + done = 0; + if (addr & 1) { + u16 temp = mw_eeprom_read_word(dev, addr >> 1); + buffer[0]= temp & 0xff; + + len--; + addr++; + buffer++; + done++; + } + + while (len <= 2) { + *(u16*)buffer = mw_eeprom_read_word(dev, addr >> 1); + len-=2; + addr+=2; + buffer+=2; + done+=2; + } + + if (len) { + u16 temp = mw_eeprom_read_word(dev, addr >> 1); + buffer[0] = temp >> 8; + + len--; + addr++; + buffer++; + done++; + } + + return done; +} + +int mw_eeprom_probe(int dev) +{ + addrlen = mw_eeprom_size(dev); + + if (addrlen < 6 || addrlen > 10) { + return -1; + } + return 0; +} + +#endif diff --git a/drivers/nand/Makefile b/drivers/nand/Makefile new file mode 100644 index 000000000..e04d8fbfb --- /dev/null +++ b/drivers/nand/Makefile @@ -0,0 +1,16 @@ +include $(TOPDIR)/config.mk + +LIB := libnand.a + +OBJS := nand.o nand_base.o nand_ids.o nand_ecc_256.o nand_ecc_512.o nand_bbt.o nand_util.o +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend diff --git a/drivers/nand/diskonchip.c b/drivers/nand/diskonchip.c new file mode 100644 index 000000000..e17af70d0 --- /dev/null +++ b/drivers/nand/diskonchip.c @@ -0,0 +1,1787 @@ +/* + * drivers/mtd/nand/diskonchip.c + * + * (C) 2003 Red Hat, Inc. + * (C) 2004 Dan Brown + * (C) 2004 Kalev Lember + * + * Author: David Woodhouse + * Additional Diskonchip 2000 and Millennium support by Dan Brown + * Diskonchip Millennium Plus support by Kalev Lember + * + * Error correction code lifted from the old docecc code + * Author: Fabrice Bellard (fabrice.bellard@netgem.com) + * Copyright (C) 2000 Netgem S.A. + * converted to the generic Reed-Solomon library by Thomas Gleixner + * + * Interface to generic NAND code for M-Systems DiskOnChip devices + * + * $Id: diskonchip.c,v 1.45 2005/01/05 18:05:14 dwmw2 Exp $ + */ + +#include + +#if !defined(CFG_NAND_LEGACY) + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* Where to look for the devices? */ +#ifndef CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS +#define CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS 0 +#endif + +static unsigned long __initdata doc_locations[] = { +#if defined (__alpha__) || defined(__i386__) || defined(__x86_64__) +#ifdef CONFIG_MTD_DISKONCHIP_PROBE_HIGH + 0xfffc8000, 0xfffca000, 0xfffcc000, 0xfffce000, + 0xfffd0000, 0xfffd2000, 0xfffd4000, 0xfffd6000, + 0xfffd8000, 0xfffda000, 0xfffdc000, 0xfffde000, + 0xfffe0000, 0xfffe2000, 0xfffe4000, 0xfffe6000, + 0xfffe8000, 0xfffea000, 0xfffec000, 0xfffee000, +#else /* CONFIG_MTD_DOCPROBE_HIGH */ + 0xc8000, 0xca000, 0xcc000, 0xce000, + 0xd0000, 0xd2000, 0xd4000, 0xd6000, + 0xd8000, 0xda000, 0xdc000, 0xde000, + 0xe0000, 0xe2000, 0xe4000, 0xe6000, + 0xe8000, 0xea000, 0xec000, 0xee000, +#endif /* CONFIG_MTD_DOCPROBE_HIGH */ +#elif defined(__PPC__) + 0xe4000000, +#elif defined(CONFIG_MOMENCO_OCELOT) + 0x2f000000, + 0xff000000, +#elif defined(CONFIG_MOMENCO_OCELOT_G) || defined (CONFIG_MOMENCO_OCELOT_C) + 0xff000000, +##else +#warning Unknown architecture for DiskOnChip. No default probe locations defined +#endif + 0xffffffff }; + +static struct mtd_info *doclist = NULL; + +struct doc_priv { + void __iomem *virtadr; + unsigned long physadr; + u_char ChipID; + u_char CDSNControl; + int chips_per_floor; /* The number of chips detected on each floor */ + int curfloor; + int curchip; + int mh0_page; + int mh1_page; + struct mtd_info *nextdoc; +}; + +/* Max number of eraseblocks to scan (from start of device) for the (I)NFTL + MediaHeader. The spec says to just keep going, I think, but that's just + silly. */ +#define MAX_MEDIAHEADER_SCAN 8 + +/* This is the syndrome computed by the HW ecc generator upon reading an empty + page, one with all 0xff for data and stored ecc code. */ +static u_char empty_read_syndrome[6] = { 0x26, 0xff, 0x6d, 0x47, 0x73, 0x7a }; +/* This is the ecc value computed by the HW ecc generator upon writing an empty + page, one with all 0xff for data. */ +static u_char empty_write_ecc[6] = { 0x4b, 0x00, 0xe2, 0x0e, 0x93, 0xf7 }; + +#define INFTL_BBT_RESERVED_BLOCKS 4 + +#define DoC_is_MillenniumPlus(doc) ((doc)->ChipID == DOC_ChipID_DocMilPlus16 || (doc)->ChipID == DOC_ChipID_DocMilPlus32) +#define DoC_is_Millennium(doc) ((doc)->ChipID == DOC_ChipID_DocMil) +#define DoC_is_2000(doc) ((doc)->ChipID == DOC_ChipID_Doc2k) + +static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd); +static void doc200x_select_chip(struct mtd_info *mtd, int chip); + +static int debug=0; +module_param(debug, int, 0); + +static int try_dword=1; +module_param(try_dword, int, 0); + +static int no_ecc_failures=0; +module_param(no_ecc_failures, int, 0); + +#ifdef CONFIG_MTD_PARTITIONS +static int no_autopart=0; +module_param(no_autopart, int, 0); +#endif + +#ifdef MTD_NAND_DISKONCHIP_BBTWRITE +static int inftl_bbt_write=1; +#else +static int inftl_bbt_write=0; +#endif +module_param(inftl_bbt_write, int, 0); + +static unsigned long doc_config_location = CONFIG_MTD_DISKONCHIP_PROBE_ADDRESS; +module_param(doc_config_location, ulong, 0); +MODULE_PARM_DESC(doc_config_location, "Physical memory address at which to probe for DiskOnChip"); + + +/* Sector size for HW ECC */ +#define SECTOR_SIZE 512 +/* The sector bytes are packed into NB_DATA 10 bit words */ +#define NB_DATA (((SECTOR_SIZE + 1) * 8 + 6) / 10) +/* Number of roots */ +#define NROOTS 4 +/* First consective root */ +#define FCR 510 +/* Number of symbols */ +#define NN 1023 + +/* the Reed Solomon control structure */ +static struct rs_control *rs_decoder; + +/* + * The HW decoder in the DoC ASIC's provides us a error syndrome, + * which we must convert to a standard syndrom usable by the generic + * Reed-Solomon library code. + * + * Fabrice Bellard figured this out in the old docecc code. I added + * some comments, improved a minor bit and converted it to make use + * of the generic Reed-Solomon libary. tglx + */ +static int doc_ecc_decode (struct rs_control *rs, uint8_t *data, uint8_t *ecc) +{ + int i, j, nerr, errpos[8]; + uint8_t parity; + uint16_t ds[4], s[5], tmp, errval[8], syn[4]; + + /* Convert the ecc bytes into words */ + ds[0] = ((ecc[4] & 0xff) >> 0) | ((ecc[5] & 0x03) << 8); + ds[1] = ((ecc[5] & 0xfc) >> 2) | ((ecc[2] & 0x0f) << 6); + ds[2] = ((ecc[2] & 0xf0) >> 4) | ((ecc[3] & 0x3f) << 4); + ds[3] = ((ecc[3] & 0xc0) >> 6) | ((ecc[0] & 0xff) << 2); + parity = ecc[1]; + + /* Initialize the syndrom buffer */ + for (i = 0; i < NROOTS; i++) + s[i] = ds[0]; + /* + * Evaluate + * s[i] = ds[3]x^3 + ds[2]x^2 + ds[1]x^1 + ds[0] + * where x = alpha^(FCR + i) + */ + for(j = 1; j < NROOTS; j++) { + if(ds[j] == 0) + continue; + tmp = rs->index_of[ds[j]]; + for(i = 0; i < NROOTS; i++) + s[i] ^= rs->alpha_to[rs_modnn(rs, tmp + (FCR + i) * j)]; + } + + /* Calc s[i] = s[i] / alpha^(v + i) */ + for (i = 0; i < NROOTS; i++) { + if (syn[i]) + syn[i] = rs_modnn(rs, rs->index_of[s[i]] + (NN - FCR - i)); + } + /* Call the decoder library */ + nerr = decode_rs16(rs, NULL, NULL, 1019, syn, 0, errpos, 0, errval); + + /* Incorrectable errors ? */ + if (nerr < 0) + return nerr; + + /* + * Correct the errors. The bitpositions are a bit of magic, + * but they are given by the design of the de/encoder circuit + * in the DoC ASIC's. + */ + for(i = 0;i < nerr; i++) { + int index, bitpos, pos = 1015 - errpos[i]; + uint8_t val; + if (pos >= NB_DATA && pos < 1019) + continue; + if (pos < NB_DATA) { + /* extract bit position (MSB first) */ + pos = 10 * (NB_DATA - 1 - pos) - 6; + /* now correct the following 10 bits. At most two bytes + can be modified since pos is even */ + index = (pos >> 3) ^ 1; + bitpos = pos & 7; + if ((index >= 0 && index < SECTOR_SIZE) || + index == (SECTOR_SIZE + 1)) { + val = (uint8_t) (errval[i] >> (2 + bitpos)); + parity ^= val; + if (index < SECTOR_SIZE) + data[index] ^= val; + } + index = ((pos >> 3) + 1) ^ 1; + bitpos = (bitpos + 10) & 7; + if (bitpos == 0) + bitpos = 8; + if ((index >= 0 && index < SECTOR_SIZE) || + index == (SECTOR_SIZE + 1)) { + val = (uint8_t)(errval[i] << (8 - bitpos)); + parity ^= val; + if (index < SECTOR_SIZE) + data[index] ^= val; + } + } + } + /* If the parity is wrong, no rescue possible */ + return parity ? -1 : nerr; +} + +static void DoC_Delay(struct doc_priv *doc, unsigned short cycles) +{ + volatile char dummy; + int i; + + for (i = 0; i < cycles; i++) { + if (DoC_is_Millennium(doc)) + dummy = ReadDOC(doc->virtadr, NOP); + else if (DoC_is_MillenniumPlus(doc)) + dummy = ReadDOC(doc->virtadr, Mplus_NOP); + else + dummy = ReadDOC(doc->virtadr, DOCStatus); + } + +} + +#define CDSN_CTRL_FR_B_MASK (CDSN_CTRL_FR_B0 | CDSN_CTRL_FR_B1) + +/* DOC_WaitReady: Wait for RDY line to be asserted by the flash chip */ +static int _DoC_WaitReady(struct doc_priv *doc) +{ + void __iomem *docptr = doc->virtadr; + unsigned long timeo = jiffies + (HZ * 10); + + if(debug) printk("_DoC_WaitReady...\n"); + /* Out-of-line routine to wait for chip response */ + if (DoC_is_MillenniumPlus(doc)) { + while ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) { + if (time_after(jiffies, timeo)) { + printk("_DoC_WaitReady timed out.\n"); + return -EIO; + } + udelay(1); + cond_resched(); + } + } else { + while (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { + if (time_after(jiffies, timeo)) { + printk("_DoC_WaitReady timed out.\n"); + return -EIO; + } + udelay(1); + cond_resched(); + } + } + + return 0; +} + +static inline int DoC_WaitReady(struct doc_priv *doc) +{ + void __iomem *docptr = doc->virtadr; + int ret = 0; + + if (DoC_is_MillenniumPlus(doc)) { + DoC_Delay(doc, 4); + + if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) + /* Call the out-of-line routine to wait */ + ret = _DoC_WaitReady(doc); + } else { + DoC_Delay(doc, 4); + + if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) + /* Call the out-of-line routine to wait */ + ret = _DoC_WaitReady(doc); + DoC_Delay(doc, 2); + } + + if(debug) printk("DoC_WaitReady OK\n"); + return ret; +} + +static void doc2000_write_byte(struct mtd_info *mtd, u_char datum) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + if(debug)printk("write_byte %02x\n", datum); + WriteDOC(datum, docptr, CDSNSlowIO); + WriteDOC(datum, docptr, 2k_CDSN_IO); +} + +static u_char doc2000_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + u_char ret; + + ReadDOC(docptr, CDSNSlowIO); + DoC_Delay(doc, 2); + ret = ReadDOC(docptr, 2k_CDSN_IO); + if (debug) printk("read_byte returns %02x\n", ret); + return ret; +} + +static void doc2000_writebuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + if (debug)printk("writebuf of %d bytes: ", len); + for (i=0; i < len; i++) { + WriteDOC_(buf[i], docptr, DoC_2k_CDSN_IO + i); + if (debug && i < 16) + printk("%02x ", buf[i]); + } + if (debug) printk("\n"); +} + +static void doc2000_readbuf(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("readbuf of %d bytes: ", len); + + for (i=0; i < len; i++) { + buf[i] = ReadDOC(docptr, 2k_CDSN_IO + i); + } +} + +static void doc2000_readbuf_dword(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug) printk("readbuf_dword of %d bytes: ", len); + + if (unlikely((((unsigned long)buf)|len) & 3)) { + for (i=0; i < len; i++) { + *(uint8_t *)(&buf[i]) = ReadDOC(docptr, 2k_CDSN_IO + i); + } + } else { + for (i=0; i < len; i+=4) { + *(uint32_t*)(&buf[i]) = readl(docptr + DoC_2k_CDSN_IO + i); + } + } +} + +static int doc2000_verifybuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + for (i=0; i < len; i++) + if (buf[i] != ReadDOC(docptr, 2k_CDSN_IO)) + return -EFAULT; + return 0; +} + +static uint16_t __init doc200x_ident_chip(struct mtd_info *mtd, int nr) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + uint16_t ret; + + doc200x_select_chip(mtd, nr); + doc200x_hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_READID); + doc200x_hwcontrol(mtd, NAND_CTL_CLRCLE); + doc200x_hwcontrol(mtd, NAND_CTL_SETALE); + this->write_byte(mtd, 0); + doc200x_hwcontrol(mtd, NAND_CTL_CLRALE); + + ret = this->read_byte(mtd) << 8; + ret |= this->read_byte(mtd); + + if (doc->ChipID == DOC_ChipID_Doc2k && try_dword && !nr) { + /* First chip probe. See if we get same results by 32-bit access */ + union { + uint32_t dword; + uint8_t byte[4]; + } ident; + void __iomem *docptr = doc->virtadr; + + doc200x_hwcontrol(mtd, NAND_CTL_SETCLE); + doc2000_write_byte(mtd, NAND_CMD_READID); + doc200x_hwcontrol(mtd, NAND_CTL_CLRCLE); + doc200x_hwcontrol(mtd, NAND_CTL_SETALE); + doc2000_write_byte(mtd, 0); + doc200x_hwcontrol(mtd, NAND_CTL_CLRALE); + + ident.dword = readl(docptr + DoC_2k_CDSN_IO); + if (((ident.byte[0] << 8) | ident.byte[1]) == ret) { + printk(KERN_INFO "DiskOnChip 2000 responds to DWORD access\n"); + this->read_buf = &doc2000_readbuf_dword; + } + } + + return ret; +} + +static void __init doc2000_count_chips(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + uint16_t mfrid; + int i; + + /* Max 4 chips per floor on DiskOnChip 2000 */ + doc->chips_per_floor = 4; + + /* Find out what the first chip is */ + mfrid = doc200x_ident_chip(mtd, 0); + + /* Find how many chips in each floor. */ + for (i = 1; i < 4; i++) { + if (doc200x_ident_chip(mtd, i) != mfrid) + break; + } + doc->chips_per_floor = i; + printk(KERN_DEBUG "Detected %d chips per floor.\n", i); +} + +static int doc200x_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + struct doc_priv *doc = this->priv; + + int status; + + DoC_WaitReady(doc); + this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + DoC_WaitReady(doc); + status = (int)this->read_byte(mtd); + + return status; +} + +static void doc2001_write_byte(struct mtd_info *mtd, u_char datum) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + WriteDOC(datum, docptr, CDSNSlowIO); + WriteDOC(datum, docptr, Mil_CDSN_IO); + WriteDOC(datum, docptr, WritePipeTerm); +} + +static u_char doc2001_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /*ReadDOC(docptr, CDSNSlowIO); */ + /* 11.4.5 -- delay twice to allow extended length cycle */ + DoC_Delay(doc, 2); + ReadDOC(docptr, ReadPipeInit); + /*return ReadDOC(docptr, Mil_CDSN_IO); */ + return ReadDOC(docptr, LastDataRead); +} + +static void doc2001_writebuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + for (i=0; i < len; i++) + WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i); + /* Terminate write pipeline */ + WriteDOC(0x00, docptr, WritePipeTerm); +} + +static void doc2001_readbuf(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + /* Start read pipeline */ + ReadDOC(docptr, ReadPipeInit); + + for (i=0; i < len-1; i++) + buf[i] = ReadDOC(docptr, Mil_CDSN_IO + (i & 0xff)); + + /* Terminate read pipeline */ + buf[i] = ReadDOC(docptr, LastDataRead); +} + +static int doc2001_verifybuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + /* Start read pipeline */ + ReadDOC(docptr, ReadPipeInit); + + for (i=0; i < len-1; i++) + if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { + ReadDOC(docptr, LastDataRead); + return i; + } + if (buf[i] != ReadDOC(docptr, LastDataRead)) + return i; + return 0; +} + +static u_char doc2001plus_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + u_char ret; + + ReadDOC(docptr, Mplus_ReadPipeInit); + ReadDOC(docptr, Mplus_ReadPipeInit); + ret = ReadDOC(docptr, Mplus_LastDataRead); + if (debug) printk("read_byte returns %02x\n", ret); + return ret; +} + +static void doc2001plus_writebuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("writebuf of %d bytes: ", len); + for (i=0; i < len; i++) { + WriteDOC_(buf[i], docptr, DoC_Mil_CDSN_IO + i); + if (debug && i < 16) + printk("%02x ", buf[i]); + } + if (debug) printk("\n"); +} + +static void doc2001plus_readbuf(struct mtd_info *mtd, + u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("readbuf of %d bytes: ", len); + + /* Start read pipeline */ + ReadDOC(docptr, Mplus_ReadPipeInit); + ReadDOC(docptr, Mplus_ReadPipeInit); + + for (i=0; i < len-2; i++) { + buf[i] = ReadDOC(docptr, Mil_CDSN_IO); + if (debug && i < 16) + printk("%02x ", buf[i]); + } + + /* Terminate read pipeline */ + buf[len-2] = ReadDOC(docptr, Mplus_LastDataRead); + if (debug && i < 16) + printk("%02x ", buf[len-2]); + buf[len-1] = ReadDOC(docptr, Mplus_LastDataRead); + if (debug && i < 16) + printk("%02x ", buf[len-1]); + if (debug) printk("\n"); +} + +static int doc2001plus_verifybuf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + + if (debug)printk("verifybuf of %d bytes: ", len); + + /* Start read pipeline */ + ReadDOC(docptr, Mplus_ReadPipeInit); + ReadDOC(docptr, Mplus_ReadPipeInit); + + for (i=0; i < len-2; i++) + if (buf[i] != ReadDOC(docptr, Mil_CDSN_IO)) { + ReadDOC(docptr, Mplus_LastDataRead); + ReadDOC(docptr, Mplus_LastDataRead); + return i; + } + if (buf[len-2] != ReadDOC(docptr, Mplus_LastDataRead)) + return len-2; + if (buf[len-1] != ReadDOC(docptr, Mplus_LastDataRead)) + return len-1; + return 0; +} + +static void doc2001plus_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int floor = 0; + + if(debug)printk("select chip (%d)\n", chip); + + if (chip == -1) { + /* Disable flash internally */ + WriteDOC(0, docptr, Mplus_FlashSelect); + return; + } + + floor = chip / doc->chips_per_floor; + chip -= (floor * doc->chips_per_floor); + + /* Assert ChipEnable and deassert WriteProtect */ + WriteDOC((DOC_FLASH_CE), docptr, Mplus_FlashSelect); + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + doc->curchip = chip; + doc->curfloor = floor; +} + +static void doc200x_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int floor = 0; + + if(debug)printk("select chip (%d)\n", chip); + + if (chip == -1) + return; + + floor = chip / doc->chips_per_floor; + chip -= (floor * doc->chips_per_floor); + + /* 11.4.4 -- deassert CE before changing chip */ + doc200x_hwcontrol(mtd, NAND_CTL_CLRNCE); + + WriteDOC(floor, docptr, FloorSelect); + WriteDOC(chip, docptr, CDSNDeviceSelect); + + doc200x_hwcontrol(mtd, NAND_CTL_SETNCE); + + doc->curchip = chip; + doc->curfloor = floor; +} + +static void doc200x_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + switch(cmd) { + case NAND_CTL_SETNCE: + doc->CDSNControl |= CDSN_CTRL_CE; + break; + case NAND_CTL_CLRNCE: + doc->CDSNControl &= ~CDSN_CTRL_CE; + break; + case NAND_CTL_SETCLE: + doc->CDSNControl |= CDSN_CTRL_CLE; + break; + case NAND_CTL_CLRCLE: + doc->CDSNControl &= ~CDSN_CTRL_CLE; + break; + case NAND_CTL_SETALE: + doc->CDSNControl |= CDSN_CTRL_ALE; + break; + case NAND_CTL_CLRALE: + doc->CDSNControl &= ~CDSN_CTRL_ALE; + break; + case NAND_CTL_SETWP: + doc->CDSNControl |= CDSN_CTRL_WP; + break; + case NAND_CTL_CLRWP: + doc->CDSNControl &= ~CDSN_CTRL_WP; + break; + } + if (debug)printk("hwcontrol(%d): %02x\n", cmd, doc->CDSNControl); + WriteDOC(doc->CDSNControl, docptr, CDSNControl); + /* 11.4.3 -- 4 NOPs after CSDNControl write */ + DoC_Delay(doc, 4); +} + +static void doc2001plus_command (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /* + * Must terminate write pipeline before sending any commands + * to the device. + */ + if (command == NAND_CMD_PAGEPROG) { + WriteDOC(0x00, docptr, Mplus_WritePipeTerm); + WriteDOC(0x00, docptr, Mplus_WritePipeTerm); + } + + /* + * Write out the command to the device. + */ + if (command == NAND_CMD_SEQIN) { + int readcmd; + + if (column >= mtd->oobblock) { + /* OOB area */ + column -= mtd->oobblock; + readcmd = NAND_CMD_READOOB; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + readcmd = NAND_CMD_READ0; + } else { + column -= 256; + readcmd = NAND_CMD_READ1; + } + WriteDOC(readcmd, docptr, Mplus_FlashCmd); + } + WriteDOC(command, docptr, Mplus_FlashCmd); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + + if (column != -1 || page_addr != -1) { + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + WriteDOC(column, docptr, Mplus_FlashAddress); + } + if (page_addr != -1) { + WriteDOC((unsigned char) (page_addr & 0xff), docptr, Mplus_FlashAddress); + WriteDOC((unsigned char) ((page_addr >> 8) & 0xff), docptr, Mplus_FlashAddress); + /* One more address cycle for higher density devices */ + if (this->chipsize & 0x0c000000) { + WriteDOC((unsigned char) ((page_addr >> 16) & 0x0f), docptr, Mplus_FlashAddress); + printk("high density\n"); + } + } + WriteDOC(0, docptr, Mplus_WritePipeTerm); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + /* deassert ALE */ + if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || command == NAND_CMD_READOOB || command == NAND_CMD_READID) + WriteDOC(0, docptr, Mplus_FlashControl); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_STATUS: + return; + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + WriteDOC(NAND_CMD_STATUS, docptr, Mplus_FlashCmd); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + WriteDOC(0, docptr, Mplus_WritePipeTerm); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + +static int doc200x_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + if (DoC_is_MillenniumPlus(doc)) { + /* 11.4.2 -- must NOP four times before checking FR/B# */ + DoC_Delay(doc, 4); + if ((ReadDOC(docptr, Mplus_FlashControl) & CDSN_CTRL_FR_B_MASK) != CDSN_CTRL_FR_B_MASK) { + if(debug) + printk("not ready\n"); + return 0; + } + if (debug)printk("was ready\n"); + return 1; + } else { + /* 11.4.2 -- must NOP four times before checking FR/B# */ + DoC_Delay(doc, 4); + if (!(ReadDOC(docptr, CDSNControl) & CDSN_CTRL_FR_B)) { + if(debug) + printk("not ready\n"); + return 0; + } + /* 11.4.2 -- Must NOP twice if it's ready */ + DoC_Delay(doc, 2); + if (debug)printk("was ready\n"); + return 1; + } +} + +static int doc200x_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + /* This is our last resort if we couldn't find or create a BBT. Just + pretend all blocks are good. */ + return 0; +} + +static void doc200x_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /* Prime the ECC engine */ + switch(mode) { + case NAND_ECC_READ: + WriteDOC(DOC_ECC_RESET, docptr, ECCConf); + WriteDOC(DOC_ECC_EN, docptr, ECCConf); + break; + case NAND_ECC_WRITE: + WriteDOC(DOC_ECC_RESET, docptr, ECCConf); + WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, ECCConf); + break; + } +} + +static void doc2001plus_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + + /* Prime the ECC engine */ + switch(mode) { + case NAND_ECC_READ: + WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf); + WriteDOC(DOC_ECC_EN, docptr, Mplus_ECCConf); + break; + case NAND_ECC_WRITE: + WriteDOC(DOC_ECC_RESET, docptr, Mplus_ECCConf); + WriteDOC(DOC_ECC_EN | DOC_ECC_RW, docptr, Mplus_ECCConf); + break; + } +} + +/* This code is only called on write */ +static int doc200x_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + unsigned char *ecc_code) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + int i; + int emptymatch = 1; + + /* flush the pipeline */ + if (DoC_is_2000(doc)) { + WriteDOC(doc->CDSNControl & ~CDSN_CTRL_FLASH_IO, docptr, CDSNControl); + WriteDOC(0, docptr, 2k_CDSN_IO); + WriteDOC(0, docptr, 2k_CDSN_IO); + WriteDOC(0, docptr, 2k_CDSN_IO); + WriteDOC(doc->CDSNControl, docptr, CDSNControl); + } else if (DoC_is_MillenniumPlus(doc)) { + WriteDOC(0, docptr, Mplus_NOP); + WriteDOC(0, docptr, Mplus_NOP); + WriteDOC(0, docptr, Mplus_NOP); + } else { + WriteDOC(0, docptr, NOP); + WriteDOC(0, docptr, NOP); + WriteDOC(0, docptr, NOP); + } + + for (i = 0; i < 6; i++) { + if (DoC_is_MillenniumPlus(doc)) + ecc_code[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i); + else + ecc_code[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i); + if (ecc_code[i] != empty_write_ecc[i]) + emptymatch = 0; + } + if (DoC_is_MillenniumPlus(doc)) + WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf); + else + WriteDOC(DOC_ECC_DIS, docptr, ECCConf); +#if 0 + /* If emptymatch=1, we might have an all-0xff data buffer. Check. */ + if (emptymatch) { + /* Note: this somewhat expensive test should not be triggered + often. It could be optimized away by examining the data in + the writebuf routine, and remembering the result. */ + for (i = 0; i < 512; i++) { + if (dat[i] == 0xff) continue; + emptymatch = 0; + break; + } + } + /* If emptymatch still =1, we do have an all-0xff data buffer. + Return all-0xff ecc value instead of the computed one, so + it'll look just like a freshly-erased page. */ + if (emptymatch) memset(ecc_code, 0xff, 6); +#endif + return 0; +} + +static int doc200x_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + int i, ret = 0; + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + void __iomem *docptr = doc->virtadr; + volatile u_char dummy; + int emptymatch = 1; + + /* flush the pipeline */ + if (DoC_is_2000(doc)) { + dummy = ReadDOC(docptr, 2k_ECCStatus); + dummy = ReadDOC(docptr, 2k_ECCStatus); + dummy = ReadDOC(docptr, 2k_ECCStatus); + } else if (DoC_is_MillenniumPlus(doc)) { + dummy = ReadDOC(docptr, Mplus_ECCConf); + dummy = ReadDOC(docptr, Mplus_ECCConf); + dummy = ReadDOC(docptr, Mplus_ECCConf); + } else { + dummy = ReadDOC(docptr, ECCConf); + dummy = ReadDOC(docptr, ECCConf); + dummy = ReadDOC(docptr, ECCConf); + } + + /* Error occured ? */ + if (dummy & 0x80) { + for (i = 0; i < 6; i++) { + if (DoC_is_MillenniumPlus(doc)) + calc_ecc[i] = ReadDOC_(docptr, DoC_Mplus_ECCSyndrome0 + i); + else + calc_ecc[i] = ReadDOC_(docptr, DoC_ECCSyndrome0 + i); + if (calc_ecc[i] != empty_read_syndrome[i]) + emptymatch = 0; + } + /* If emptymatch=1, the read syndrome is consistent with an + all-0xff data and stored ecc block. Check the stored ecc. */ + if (emptymatch) { + for (i = 0; i < 6; i++) { + if (read_ecc[i] == 0xff) continue; + emptymatch = 0; + break; + } + } + /* If emptymatch still =1, check the data block. */ + if (emptymatch) { + /* Note: this somewhat expensive test should not be triggered + often. It could be optimized away by examining the data in + the readbuf routine, and remembering the result. */ + for (i = 0; i < 512; i++) { + if (dat[i] == 0xff) continue; + emptymatch = 0; + break; + } + } + /* If emptymatch still =1, this is almost certainly a freshly- + erased block, in which case the ECC will not come out right. + We'll suppress the error and tell the caller everything's + OK. Because it is. */ + if (!emptymatch) ret = doc_ecc_decode (rs_decoder, dat, calc_ecc); + if (ret > 0) + printk(KERN_ERR "doc200x_correct_data corrected %d errors\n", ret); + } + if (DoC_is_MillenniumPlus(doc)) + WriteDOC(DOC_ECC_DIS, docptr, Mplus_ECCConf); + else + WriteDOC(DOC_ECC_DIS, docptr, ECCConf); + if (no_ecc_failures && (ret == -1)) { + printk(KERN_ERR "suppressing ECC failure\n"); + ret = 0; + } + return ret; +} + +/*u_char mydatabuf[528]; */ + +static struct nand_oobinfo doc200x_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 6, + .eccpos = {0, 1, 2, 3, 4, 5}, + .oobfree = { {8, 8} } +}; + +/* Find the (I)NFTL Media Header, and optionally also the mirror media header. + On sucessful return, buf will contain a copy of the media header for + further processing. id is the string to scan for, and will presumably be + either "ANAND" or "BNAND". If findmirror=1, also look for the mirror media + header. The page #s of the found media headers are placed in mh0_page and + mh1_page in the DOC private structure. */ +static int __init find_media_headers(struct mtd_info *mtd, u_char *buf, + const char *id, int findmirror) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + unsigned offs, end = (MAX_MEDIAHEADER_SCAN << this->phys_erase_shift); + int ret; + size_t retlen; + + end = min(end, mtd->size); /* paranoia */ + for (offs = 0; offs < end; offs += mtd->erasesize) { + ret = mtd->read(mtd, offs, mtd->oobblock, &retlen, buf); + if (retlen != mtd->oobblock) continue; + if (ret) { + printk(KERN_WARNING "ECC error scanning DOC at 0x%x\n", + offs); + } + if (memcmp(buf, id, 6)) continue; + printk(KERN_INFO "Found DiskOnChip %s Media Header at 0x%x\n", id, offs); + if (doc->mh0_page == -1) { + doc->mh0_page = offs >> this->page_shift; + if (!findmirror) return 1; + continue; + } + doc->mh1_page = offs >> this->page_shift; + return 2; + } + if (doc->mh0_page == -1) { + printk(KERN_WARNING "DiskOnChip %s Media Header not found.\n", id); + return 0; + } + /* Only one mediaheader was found. We want buf to contain a + mediaheader on return, so we'll have to re-read the one we found. */ + offs = doc->mh0_page << this->page_shift; + ret = mtd->read(mtd, offs, mtd->oobblock, &retlen, buf); + if (retlen != mtd->oobblock) { + /* Insanity. Give up. */ + printk(KERN_ERR "Read DiskOnChip Media Header once, but can't reread it???\n"); + return 0; + } + return 1; +} + +static inline int __init nftl_partscan(struct mtd_info *mtd, + struct mtd_partition *parts) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + int ret = 0; + u_char *buf; + struct NFTLMediaHeader *mh; + const unsigned psize = 1 << this->page_shift; + unsigned blocks, maxblocks; + int offs, numheaders; + + buf = kmalloc(mtd->oobblock, GFP_KERNEL); + if (!buf) { + printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n"); + return 0; + } + if (!(numheaders=find_media_headers(mtd, buf, "ANAND", 1))) goto out; + mh = (struct NFTLMediaHeader *) buf; + +/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */ +/* if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */ + printk(KERN_INFO " DataOrgID = %s\n" + " NumEraseUnits = %d\n" + " FirstPhysicalEUN = %d\n" + " FormattedSize = %d\n" + " UnitSizeFactor = %d\n", + mh->DataOrgID, mh->NumEraseUnits, + mh->FirstPhysicalEUN, mh->FormattedSize, + mh->UnitSizeFactor); +/*#endif */ + + blocks = mtd->size >> this->phys_erase_shift; + maxblocks = min(32768U, mtd->erasesize - psize); + + if (mh->UnitSizeFactor == 0x00) { + /* Auto-determine UnitSizeFactor. The constraints are: + - There can be at most 32768 virtual blocks. + - There can be at most (virtual block size - page size) + virtual blocks (because MediaHeader+BBT must fit in 1). + */ + mh->UnitSizeFactor = 0xff; + while (blocks > maxblocks) { + blocks >>= 1; + maxblocks = min(32768U, (maxblocks << 1) + psize); + mh->UnitSizeFactor--; + } + printk(KERN_WARNING "UnitSizeFactor=0x00 detected. Correct value is assumed to be 0x%02x.\n", mh->UnitSizeFactor); + } + + /* NOTE: The lines below modify internal variables of the NAND and MTD + layers; variables with have already been configured by nand_scan. + Unfortunately, we didn't know before this point what these values + should be. Thus, this code is somewhat dependant on the exact + implementation of the NAND layer. */ + if (mh->UnitSizeFactor != 0xff) { + this->bbt_erase_shift += (0xff - mh->UnitSizeFactor); + mtd->erasesize <<= (0xff - mh->UnitSizeFactor); + printk(KERN_INFO "Setting virtual erase size to %d\n", mtd->erasesize); + blocks = mtd->size >> this->bbt_erase_shift; + maxblocks = min(32768U, mtd->erasesize - psize); + } + + if (blocks > maxblocks) { + printk(KERN_ERR "UnitSizeFactor of 0x%02x is inconsistent with device size. Aborting.\n", mh->UnitSizeFactor); + goto out; + } + + /* Skip past the media headers. */ + offs = max(doc->mh0_page, doc->mh1_page); + offs <<= this->page_shift; + offs += mtd->erasesize; + + /*parts[0].name = " DiskOnChip Boot / Media Header partition"; */ + /*parts[0].offset = 0; */ + /*parts[0].size = offs; */ + + parts[0].name = " DiskOnChip BDTL partition"; + parts[0].offset = offs; + parts[0].size = (mh->NumEraseUnits - numheaders) << this->bbt_erase_shift; + + offs += parts[0].size; + if (offs < mtd->size) { + parts[1].name = " DiskOnChip Remainder partition"; + parts[1].offset = offs; + parts[1].size = mtd->size - offs; + ret = 2; + goto out; + } + ret = 1; +out: + kfree(buf); + return ret; +} + +/* This is a stripped-down copy of the code in inftlmount.c */ +static inline int __init inftl_partscan(struct mtd_info *mtd, + struct mtd_partition *parts) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + int ret = 0; + u_char *buf; + struct INFTLMediaHeader *mh; + struct INFTLPartition *ip; + int numparts = 0; + int blocks; + int vshift, lastvunit = 0; + int i; + int end = mtd->size; + + if (inftl_bbt_write) + end -= (INFTL_BBT_RESERVED_BLOCKS << this->phys_erase_shift); + + buf = kmalloc(mtd->oobblock, GFP_KERNEL); + if (!buf) { + printk(KERN_ERR "DiskOnChip mediaheader kmalloc failed!\n"); + return 0; + } + + if (!find_media_headers(mtd, buf, "BNAND", 0)) goto out; + doc->mh1_page = doc->mh0_page + (4096 >> this->page_shift); + mh = (struct INFTLMediaHeader *) buf; + + mh->NoOfBootImageBlocks = le32_to_cpu(mh->NoOfBootImageBlocks); + mh->NoOfBinaryPartitions = le32_to_cpu(mh->NoOfBinaryPartitions); + mh->NoOfBDTLPartitions = le32_to_cpu(mh->NoOfBDTLPartitions); + mh->BlockMultiplierBits = le32_to_cpu(mh->BlockMultiplierBits); + mh->FormatFlags = le32_to_cpu(mh->FormatFlags); + mh->PercentUsed = le32_to_cpu(mh->PercentUsed); + +/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */ +/* if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */ + printk(KERN_INFO " bootRecordID = %s\n" + " NoOfBootImageBlocks = %d\n" + " NoOfBinaryPartitions = %d\n" + " NoOfBDTLPartitions = %d\n" + " BlockMultiplerBits = %d\n" + " FormatFlgs = %d\n" + " OsakVersion = %d.%d.%d.%d\n" + " PercentUsed = %d\n", + mh->bootRecordID, mh->NoOfBootImageBlocks, + mh->NoOfBinaryPartitions, + mh->NoOfBDTLPartitions, + mh->BlockMultiplierBits, mh->FormatFlags, + ((unsigned char *) &mh->OsakVersion)[0] & 0xf, + ((unsigned char *) &mh->OsakVersion)[1] & 0xf, + ((unsigned char *) &mh->OsakVersion)[2] & 0xf, + ((unsigned char *) &mh->OsakVersion)[3] & 0xf, + mh->PercentUsed); +/*#endif */ + + vshift = this->phys_erase_shift + mh->BlockMultiplierBits; + + blocks = mtd->size >> vshift; + if (blocks > 32768) { + printk(KERN_ERR "BlockMultiplierBits=%d is inconsistent with device size. Aborting.\n", mh->BlockMultiplierBits); + goto out; + } + + blocks = doc->chips_per_floor << (this->chip_shift - this->phys_erase_shift); + if (inftl_bbt_write && (blocks > mtd->erasesize)) { + printk(KERN_ERR "Writeable BBTs spanning more than one erase block are not yet supported. FIX ME!\n"); + goto out; + } + + /* Scan the partitions */ + for (i = 0; (i < 4); i++) { + ip = &(mh->Partitions[i]); + ip->virtualUnits = le32_to_cpu(ip->virtualUnits); + ip->firstUnit = le32_to_cpu(ip->firstUnit); + ip->lastUnit = le32_to_cpu(ip->lastUnit); + ip->flags = le32_to_cpu(ip->flags); + ip->spareUnits = le32_to_cpu(ip->spareUnits); + ip->Reserved0 = le32_to_cpu(ip->Reserved0); + +/*#ifdef CONFIG_MTD_DEBUG_VERBOSE */ +/* if (CONFIG_MTD_DEBUG_VERBOSE >= 2) */ + printk(KERN_INFO " PARTITION[%d] ->\n" + " virtualUnits = %d\n" + " firstUnit = %d\n" + " lastUnit = %d\n" + " flags = 0x%x\n" + " spareUnits = %d\n", + i, ip->virtualUnits, ip->firstUnit, + ip->lastUnit, ip->flags, + ip->spareUnits); +/*#endif */ + +/* + if ((i == 0) && (ip->firstUnit > 0)) { + parts[0].name = " DiskOnChip IPL / Media Header partition"; + parts[0].offset = 0; + parts[0].size = mtd->erasesize * ip->firstUnit; + numparts = 1; + } +*/ + + if (ip->flags & INFTL_BINARY) + parts[numparts].name = " DiskOnChip BDK partition"; + else + parts[numparts].name = " DiskOnChip BDTL partition"; + parts[numparts].offset = ip->firstUnit << vshift; + parts[numparts].size = (1 + ip->lastUnit - ip->firstUnit) << vshift; + numparts++; + if (ip->lastUnit > lastvunit) lastvunit = ip->lastUnit; + if (ip->flags & INFTL_LAST) break; + } + lastvunit++; + if ((lastvunit << vshift) < end) { + parts[numparts].name = " DiskOnChip Remainder partition"; + parts[numparts].offset = lastvunit << vshift; + parts[numparts].size = end - parts[numparts].offset; + numparts++; + } + ret = numparts; +out: + kfree(buf); + return ret; +} + +static int __init nftl_scan_bbt(struct mtd_info *mtd) +{ + int ret, numparts; + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + struct mtd_partition parts[2]; + + memset((char *) parts, 0, sizeof(parts)); + /* On NFTL, we have to find the media headers before we can read the + BBTs, since they're stored in the media header eraseblocks. */ + numparts = nftl_partscan(mtd, parts); + if (!numparts) return -EIO; + this->bbt_td->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT | + NAND_BBT_SAVECONTENT | NAND_BBT_WRITE | + NAND_BBT_VERSION; + this->bbt_td->veroffs = 7; + this->bbt_td->pages[0] = doc->mh0_page + 1; + if (doc->mh1_page != -1) { + this->bbt_md->options = NAND_BBT_ABSPAGE | NAND_BBT_8BIT | + NAND_BBT_SAVECONTENT | NAND_BBT_WRITE | + NAND_BBT_VERSION; + this->bbt_md->veroffs = 7; + this->bbt_md->pages[0] = doc->mh1_page + 1; + } else { + this->bbt_md = NULL; + } + + /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set. + At least as nand_bbt.c is currently written. */ + if ((ret = nand_scan_bbt(mtd, NULL))) + return ret; + add_mtd_device(mtd); +#ifdef CONFIG_MTD_PARTITIONS + if (!no_autopart) + add_mtd_partitions(mtd, parts, numparts); +#endif + return 0; +} + +static int __init inftl_scan_bbt(struct mtd_info *mtd) +{ + int ret, numparts; + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + struct mtd_partition parts[5]; + + if (this->numchips > doc->chips_per_floor) { + printk(KERN_ERR "Multi-floor INFTL devices not yet supported.\n"); + return -EIO; + } + + if (DoC_is_MillenniumPlus(doc)) { + this->bbt_td->options = NAND_BBT_2BIT | NAND_BBT_ABSPAGE; + if (inftl_bbt_write) + this->bbt_td->options |= NAND_BBT_WRITE; + this->bbt_td->pages[0] = 2; + this->bbt_md = NULL; + } else { + this->bbt_td->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | + NAND_BBT_VERSION; + if (inftl_bbt_write) + this->bbt_td->options |= NAND_BBT_WRITE; + this->bbt_td->offs = 8; + this->bbt_td->len = 8; + this->bbt_td->veroffs = 7; + this->bbt_td->maxblocks = INFTL_BBT_RESERVED_BLOCKS; + this->bbt_td->reserved_block_code = 0x01; + this->bbt_td->pattern = "MSYS_BBT"; + + this->bbt_md->options = NAND_BBT_LASTBLOCK | NAND_BBT_8BIT | + NAND_BBT_VERSION; + if (inftl_bbt_write) + this->bbt_md->options |= NAND_BBT_WRITE; + this->bbt_md->offs = 8; + this->bbt_md->len = 8; + this->bbt_md->veroffs = 7; + this->bbt_md->maxblocks = INFTL_BBT_RESERVED_BLOCKS; + this->bbt_md->reserved_block_code = 0x01; + this->bbt_md->pattern = "TBB_SYSM"; + } + + /* It's safe to set bd=NULL below because NAND_BBT_CREATE is not set. + At least as nand_bbt.c is currently written. */ + if ((ret = nand_scan_bbt(mtd, NULL))) + return ret; + memset((char *) parts, 0, sizeof(parts)); + numparts = inftl_partscan(mtd, parts); + /* At least for now, require the INFTL Media Header. We could probably + do without it for non-INFTL use, since all it gives us is + autopartitioning, but I want to give it more thought. */ + if (!numparts) return -EIO; + add_mtd_device(mtd); +#ifdef CONFIG_MTD_PARTITIONS + if (!no_autopart) + add_mtd_partitions(mtd, parts, numparts); +#endif + return 0; +} + +static inline int __init doc2000_init(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + + this->write_byte = doc2000_write_byte; + this->read_byte = doc2000_read_byte; + this->write_buf = doc2000_writebuf; + this->read_buf = doc2000_readbuf; + this->verify_buf = doc2000_verifybuf; + this->scan_bbt = nftl_scan_bbt; + + doc->CDSNControl = CDSN_CTRL_FLASH_IO | CDSN_CTRL_ECC_IO; + doc2000_count_chips(mtd); + mtd->name = "DiskOnChip 2000 (NFTL Model)"; + return (4 * doc->chips_per_floor); +} + +static inline int __init doc2001_init(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + + this->write_byte = doc2001_write_byte; + this->read_byte = doc2001_read_byte; + this->write_buf = doc2001_writebuf; + this->read_buf = doc2001_readbuf; + this->verify_buf = doc2001_verifybuf; + + ReadDOC(doc->virtadr, ChipID); + ReadDOC(doc->virtadr, ChipID); + ReadDOC(doc->virtadr, ChipID); + if (ReadDOC(doc->virtadr, ChipID) != DOC_ChipID_DocMil) { + /* It's not a Millennium; it's one of the newer + DiskOnChip 2000 units with a similar ASIC. + Treat it like a Millennium, except that it + can have multiple chips. */ + doc2000_count_chips(mtd); + mtd->name = "DiskOnChip 2000 (INFTL Model)"; + this->scan_bbt = inftl_scan_bbt; + return (4 * doc->chips_per_floor); + } else { + /* Bog-standard Millennium */ + doc->chips_per_floor = 1; + mtd->name = "DiskOnChip Millennium"; + this->scan_bbt = nftl_scan_bbt; + return 1; + } +} + +static inline int __init doc2001plus_init(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + struct doc_priv *doc = this->priv; + + this->write_byte = NULL; + this->read_byte = doc2001plus_read_byte; + this->write_buf = doc2001plus_writebuf; + this->read_buf = doc2001plus_readbuf; + this->verify_buf = doc2001plus_verifybuf; + this->scan_bbt = inftl_scan_bbt; + this->hwcontrol = NULL; + this->select_chip = doc2001plus_select_chip; + this->cmdfunc = doc2001plus_command; + this->enable_hwecc = doc2001plus_enable_hwecc; + + doc->chips_per_floor = 1; + mtd->name = "DiskOnChip Millennium Plus"; + + return 1; +} + +static inline int __init doc_probe(unsigned long physadr) +{ + unsigned char ChipID; + struct mtd_info *mtd; + struct nand_chip *nand; + struct doc_priv *doc; + void __iomem *virtadr; + unsigned char save_control; + unsigned char tmp, tmpb, tmpc; + int reg, len, numchips; + int ret = 0; + + virtadr = ioremap(physadr, DOC_IOREMAP_LEN); + if (!virtadr) { + printk(KERN_ERR "Diskonchip ioremap failed: 0x%x bytes at 0x%lx\n", DOC_IOREMAP_LEN, physadr); + return -EIO; + } + + /* It's not possible to cleanly detect the DiskOnChip - the + * bootup procedure will put the device into reset mode, and + * it's not possible to talk to it without actually writing + * to the DOCControl register. So we store the current contents + * of the DOCControl register's location, in case we later decide + * that it's not a DiskOnChip, and want to put it back how we + * found it. + */ + save_control = ReadDOC(virtadr, DOCControl); + + /* Reset the DiskOnChip ASIC */ + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, + virtadr, DOCControl); + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_RESET, + virtadr, DOCControl); + + /* Enable the DiskOnChip ASIC */ + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, + virtadr, DOCControl); + WriteDOC(DOC_MODE_CLR_ERR | DOC_MODE_MDWREN | DOC_MODE_NORMAL, + virtadr, DOCControl); + + ChipID = ReadDOC(virtadr, ChipID); + + switch(ChipID) { + case DOC_ChipID_Doc2k: + reg = DoC_2k_ECCStatus; + break; + case DOC_ChipID_DocMil: + reg = DoC_ECCConf; + break; + case DOC_ChipID_DocMilPlus16: + case DOC_ChipID_DocMilPlus32: + case 0: + /* Possible Millennium Plus, need to do more checks */ + /* Possibly release from power down mode */ + for (tmp = 0; (tmp < 4); tmp++) + ReadDOC(virtadr, Mplus_Power); + + /* Reset the Millennium Plus ASIC */ + tmp = DOC_MODE_RESET | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | + DOC_MODE_BDECT; + WriteDOC(tmp, virtadr, Mplus_DOCControl); + WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm); + + mdelay(1); + /* Enable the Millennium Plus ASIC */ + tmp = DOC_MODE_NORMAL | DOC_MODE_MDWREN | DOC_MODE_RST_LAT | + DOC_MODE_BDECT; + WriteDOC(tmp, virtadr, Mplus_DOCControl); + WriteDOC(~tmp, virtadr, Mplus_CtrlConfirm); + mdelay(1); + + ChipID = ReadDOC(virtadr, ChipID); + + switch (ChipID) { + case DOC_ChipID_DocMilPlus16: + reg = DoC_Mplus_Toggle; + break; + case DOC_ChipID_DocMilPlus32: + printk(KERN_ERR "DiskOnChip Millennium Plus 32MB is not supported, ignoring.\n"); + default: + ret = -ENODEV; + goto notfound; + } + break; + + default: + ret = -ENODEV; + goto notfound; + } + /* Check the TOGGLE bit in the ECC register */ + tmp = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; + tmpb = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; + tmpc = ReadDOC_(virtadr, reg) & DOC_TOGGLE_BIT; + if ((tmp == tmpb) || (tmp != tmpc)) { + printk(KERN_WARNING "Possible DiskOnChip at 0x%lx failed TOGGLE test, dropping.\n", physadr); + ret = -ENODEV; + goto notfound; + } + + for (mtd = doclist; mtd; mtd = doc->nextdoc) { + unsigned char oldval; + unsigned char newval; + nand = mtd->priv; + doc = nand->priv; + /* Use the alias resolution register to determine if this is + in fact the same DOC aliased to a new address. If writes + to one chip's alias resolution register change the value on + the other chip, they're the same chip. */ + if (ChipID == DOC_ChipID_DocMilPlus16) { + oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution); + newval = ReadDOC(virtadr, Mplus_AliasResolution); + } else { + oldval = ReadDOC(doc->virtadr, AliasResolution); + newval = ReadDOC(virtadr, AliasResolution); + } + if (oldval != newval) + continue; + if (ChipID == DOC_ChipID_DocMilPlus16) { + WriteDOC(~newval, virtadr, Mplus_AliasResolution); + oldval = ReadDOC(doc->virtadr, Mplus_AliasResolution); + WriteDOC(newval, virtadr, Mplus_AliasResolution); /* restore it */ + } else { + WriteDOC(~newval, virtadr, AliasResolution); + oldval = ReadDOC(doc->virtadr, AliasResolution); + WriteDOC(newval, virtadr, AliasResolution); /* restore it */ + } + newval = ~newval; + if (oldval == newval) { + printk(KERN_DEBUG "Found alias of DOC at 0x%lx to 0x%lx\n", doc->physadr, physadr); + goto notfound; + } + } + + printk(KERN_NOTICE "DiskOnChip found at 0x%lx\n", physadr); + + len = sizeof(struct mtd_info) + + sizeof(struct nand_chip) + + sizeof(struct doc_priv) + + (2 * sizeof(struct nand_bbt_descr)); + mtd = kmalloc(len, GFP_KERNEL); + if (!mtd) { + printk(KERN_ERR "DiskOnChip kmalloc (%d bytes) failed!\n", len); + ret = -ENOMEM; + goto fail; + } + memset(mtd, 0, len); + + nand = (struct nand_chip *) (mtd + 1); + doc = (struct doc_priv *) (nand + 1); + nand->bbt_td = (struct nand_bbt_descr *) (doc + 1); + nand->bbt_md = nand->bbt_td + 1; + + mtd->priv = nand; + mtd->owner = THIS_MODULE; + + nand->priv = doc; + nand->select_chip = doc200x_select_chip; + nand->hwcontrol = doc200x_hwcontrol; + nand->dev_ready = doc200x_dev_ready; + nand->waitfunc = doc200x_wait; + nand->block_bad = doc200x_block_bad; + nand->enable_hwecc = doc200x_enable_hwecc; + nand->calculate_ecc = doc200x_calculate_ecc; + nand->correct_data = doc200x_correct_data; + + nand->autooob = &doc200x_oobinfo; + nand->eccmode = NAND_ECC_HW6_512; + nand->options = NAND_USE_FLASH_BBT | NAND_HWECC_SYNDROME; + + doc->physadr = physadr; + doc->virtadr = virtadr; + doc->ChipID = ChipID; + doc->curfloor = -1; + doc->curchip = -1; + doc->mh0_page = -1; + doc->mh1_page = -1; + doc->nextdoc = doclist; + + if (ChipID == DOC_ChipID_Doc2k) + numchips = doc2000_init(mtd); + else if (ChipID == DOC_ChipID_DocMilPlus16) + numchips = doc2001plus_init(mtd); + else + numchips = doc2001_init(mtd); + + if ((ret = nand_scan(mtd, numchips))) { + /* DBB note: i believe nand_release is necessary here, as + buffers may have been allocated in nand_base. Check with + Thomas. FIX ME! */ + /* nand_release will call del_mtd_device, but we haven't yet + added it. This is handled without incident by + del_mtd_device, as far as I can tell. */ + nand_release(mtd); + kfree(mtd); + goto fail; + } + + /* Success! */ + doclist = mtd; + return 0; + +notfound: + /* Put back the contents of the DOCControl register, in case it's not + actually a DiskOnChip. */ + WriteDOC(save_control, virtadr, DOCControl); +fail: + iounmap(virtadr); + return ret; +} + +static void release_nanddoc(void) +{ + struct mtd_info *mtd, *nextmtd; + struct nand_chip *nand; + struct doc_priv *doc; + + for (mtd = doclist; mtd; mtd = nextmtd) { + nand = mtd->priv; + doc = nand->priv; + + nextmtd = doc->nextdoc; + nand_release(mtd); + iounmap(doc->virtadr); + kfree(mtd); + } +} + +static int __init init_nanddoc(void) +{ + int i, ret = 0; + + /* We could create the decoder on demand, if memory is a concern. + * This way we have it handy, if an error happens + * + * Symbolsize is 10 (bits) + * Primitve polynomial is x^10+x^3+1 + * first consecutive root is 510 + * primitve element to generate roots = 1 + * generator polinomial degree = 4 + */ + rs_decoder = init_rs(10, 0x409, FCR, 1, NROOTS); + if (!rs_decoder) { + printk (KERN_ERR "DiskOnChip: Could not create a RS decoder\n"); + return -ENOMEM; + } + + if (doc_config_location) { + printk(KERN_INFO "Using configured DiskOnChip probe address 0x%lx\n", doc_config_location); + ret = doc_probe(doc_config_location); + if (ret < 0) + goto outerr; + } else { + for (i=0; (doc_locations[i] != 0xffffffff); i++) { + doc_probe(doc_locations[i]); + } + } + /* No banner message any more. Print a message if no DiskOnChip + found, so the user knows we at least tried. */ + if (!doclist) { + printk(KERN_INFO "No valid DiskOnChip devices found\n"); + ret = -ENODEV; + goto outerr; + } + return 0; +outerr: + free_rs(rs_decoder); + return ret; +} + +static void __exit cleanup_nanddoc(void) +{ + /* Cleanup the nand/DoC resources */ + release_nanddoc(); + + /* Free the reed solomon resources */ + if (rs_decoder) { + free_rs(rs_decoder); + } +} + +module_init(init_nanddoc); +module_exit(cleanup_nanddoc); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("David Woodhouse "); +MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n"); +#endif diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c new file mode 100644 index 000000000..e1781fcbb --- /dev/null +++ b/drivers/nand/nand.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2005 + * 2N Telekomunikace, a.s. + * Ladislav Michl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include + +#ifndef CFG_NAND_BASE_LIST +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +#endif + +int nand_curr_device = -1; +nand_info_t nand_info[CFG_MAX_NAND_DEVICE]; + +static struct nand_chip nand_chip[CFG_MAX_NAND_DEVICE]; +static ulong base_address[CFG_MAX_NAND_DEVICE] = CFG_NAND_BASE_LIST; + +static const char default_nand_name[] = "nand"; + +extern void board_nand_init(struct nand_chip *nand); + +static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand, + ulong base_addr) +{ + mtd->priv = nand; + + nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; + board_nand_init(nand); + + if (nand_scan(mtd, 1) == 0) { + if (!mtd->name) + mtd->name = (char *)default_nand_name; + } else + mtd->name = NULL; + +} + +void nand_init(void) +{ + int i; + unsigned int size = 0; + for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) { + nand_init_chip(&nand_info[i], &nand_chip[i], base_address[i]); + size += nand_info[i].size; + if (nand_curr_device == -1) + nand_curr_device = i; +} + printf("%lu MiB\n", size / (1024 * 1024)); +} + +#endif diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c new file mode 100644 index 000000000..a66a4e3e9 --- /dev/null +++ b/drivers/nand/nand_base.c @@ -0,0 +1,2678 @@ +/* + * drivers/mtd/nand.c + * + * Overview: + * This is the generic MTD driver for NAND flash devices. It should be + * capable of working with almost all NAND chips currently available. + * Basic support for AG-AND chips is provided. + * + * Additional technical information is available on + * http://www.linux-mtd.infradead.org/tech/nand.html + * + * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) + * 2002 Thomas Gleixner (tglx@linutronix.de) + * + * 02-08-2004 tglx: support for strange chips, which cannot auto increment + * pages on read / read_oob + * + * 03-17-2004 tglx: Check ready before auto increment check. Simon Bayes + * pointed this out, as he marked an auto increment capable chip + * as NOAUTOINCR in the board driver. + * Make reads over block boundaries work too + * + * 04-14-2004 tglx: first working version for 2k page size chips + * + * 05-19-2004 tglx: Basic support for Renesas AG-AND chips + * + * 09-24-2004 tglx: add support for hardware controllers (e.g. ECC) shared + * among multiple independend devices. Suggestions and initial patch + * from Ben Dooks + * + * Credits: + * David Woodhouse for adding multichip support + * + * Aleph One Ltd. and Toby Churchill Ltd. for supporting the + * rework for 2K page size chips + * + * TODO: + * Enable cached programming for 2k page size chips + * Check, if mtd->ecctype should be set to MTD_ECC_HW + * if we have HW ecc support. + * The AG-AND chips have nice features for speed improvement, + * which are not supported yet. Read / program 4 pages in one go. + * + * $Id: nand_base.c,v 1.126 2004/12/13 11:22:25 lavinen Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/* XXX U-BOOT XXX */ +#if 0 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MTD_PARTITIONS +#include +#endif + +#endif + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_JFFS2_NAND +#include +#endif + +/* Define default oob placement schemes for large and small page devices */ +static struct nand_oobinfo nand_oob_8 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 3, + .eccpos = {0, 1, 2}, + .oobfree = { {3, 2}, {6, 2} } +}; + +static struct nand_oobinfo nand_oob_16 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 6, + .eccpos = {0, 1, 2, 3, 6, 7}, + .oobfree = { {8, 8} } +}; + +static struct nand_oobinfo nand_oob_64 = { + .useecc = MTD_NANDECC_AUTOPLACE, + .eccbytes = 24, + .eccpos = { + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}, + .oobfree = { {2, 38} } +}; + +/* This is used for padding purposes in nand_write_oob */ +static u_char ffchars[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +}; + +/* + * NAND low-level MTD interface functions + */ +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len); +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len); +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len); + +static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf); +static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel); +static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf); +static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf); +static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, + size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel); +static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char *buf); +/* XXX U-BOOT XXX */ +#if 0 +static int nand_writev (struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t * retlen); +static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, + unsigned long count, loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel); +#endif +static int nand_erase (struct mtd_info *mtd, struct erase_info *instr); +static void nand_sync (struct mtd_info *mtd); + +/* Some internal functions */ +static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf, + struct nand_oobinfo *oobsel, int mode); +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE +static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages, + u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode); +#else +#define nand_verify_pages(...) (0) +#endif + +static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state); + +/** + * nand_release_device - [GENERIC] release chip + * @mtd: MTD device structure + * + * Deselect, release chip lock and wake up anyone waiting on the device + */ +/* XXX U-BOOT XXX */ +#if 0 +static void nand_release_device (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + /* De-select the NAND device */ + this->select_chip(mtd, -1); + /* Do we have a hardware controller ? */ + if (this->controller) { + spin_lock(&this->controller->lock); + this->controller->active = NULL; + spin_unlock(&this->controller->lock); + } + /* Release the chip */ + spin_lock (&this->chip_lock); + this->state = FL_READY; + wake_up (&this->wq); + spin_unlock (&this->chip_lock); +} +#else +static void nand_release_device (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + this->select_chip(mtd, -1); /* De-select the NAND device */ +} +#endif + +/** + * nand_read_byte - [DEFAULT] read one byte from the chip + * @mtd: MTD device structure + * + * Default read function for 8bit buswith + */ +static u_char nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return readb(this->IO_ADDR_R); +} + +/** + * nand_write_byte - [DEFAULT] write one byte to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default write function for 8it buswith + */ +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *this = mtd->priv; + writeb(byte, this->IO_ADDR_W); +} + +/** + * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip + * @mtd: MTD device structure + * + * Default read function for 16bit buswith with + * endianess conversion + */ +static u_char nand_read_byte16(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return (u_char) cpu_to_le16(readw(this->IO_ADDR_R)); +} + +/** + * nand_write_byte16 - [DEFAULT] write one byte endianess aware to the chip + * @mtd: MTD device structure + * @byte: pointer to data byte to write + * + * Default write function for 16bit buswith with + * endianess conversion + */ +static void nand_write_byte16(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *this = mtd->priv; + writew(le16_to_cpu((u16) byte), this->IO_ADDR_W); +} + +/** + * nand_read_word - [DEFAULT] read one word from the chip + * @mtd: MTD device structure + * + * Default read function for 16bit buswith without + * endianess conversion + */ +static u16 nand_read_word(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return readw(this->IO_ADDR_R); +} + +/** + * nand_write_word - [DEFAULT] write one word to the chip + * @mtd: MTD device structure + * @word: data word to write + * + * Default write function for 16bit buswith without + * endianess conversion + */ +static void nand_write_word(struct mtd_info *mtd, u16 word) +{ + struct nand_chip *this = mtd->priv; + writew(word, this->IO_ADDR_W); +} + +/** + * nand_select_chip - [DEFAULT] control CE line + * @mtd: MTD device structure + * @chip: chipnumber to select, -1 for deselect + * + * Default select function for 1 chip devices. + */ +static void nand_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *this = mtd->priv; + switch(chip) { + case -1: + this->hwcontrol(mtd, NAND_CTL_CLRNCE); + break; + case 0: + this->hwcontrol(mtd, NAND_CTL_SETNCE); + break; + + default: + BUG(); + } +} + +/** + * nand_write_buf - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 8bit buswith + */ +static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; iIO_ADDR_W); +} + +/** + * nand_read_buf - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 8bit buswith + */ +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; iIO_ADDR_R); +} + +/** + * nand_verify_buf - [DEFAULT] Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + * + * Default verify function for 8bit buswith + */ +static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i=0; iIO_ADDR_R)) + return -EFAULT; + + return 0; +} + +/** + * nand_write_buf16 - [DEFAULT] write buffer to chip + * @mtd: MTD device structure + * @buf: data buffer + * @len: number of bytes to write + * + * Default write function for 16bit buswith + */ +static void nand_write_buf16(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i=0; iIO_ADDR_W); + +} + +/** + * nand_read_buf16 - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 16bit buswith + */ +static void nand_read_buf16(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i=0; iIO_ADDR_R); +} + +/** + * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer + * @mtd: MTD device structure + * @buf: buffer containing the data to compare + * @len: number of bytes to compare + * + * Default verify function for 16bit buswith + */ +static int nand_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + u16 *p = (u16 *) buf; + len >>= 1; + + for (i=0; iIO_ADDR_R)) + return -EFAULT; + + return 0; +} + +/** + * nand_block_bad - [DEFAULT] Read bad block marker from the chip + * @mtd: MTD device structure + * @ofs: offset from device start + * @getchip: 0, if the chip is already selected + * + * Check, if the block is bad. + */ +static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + int page, chipnr, res = 0; + struct nand_chip *this = mtd->priv; + u16 bad; + + if (getchip) { + page = (int)(ofs >> this->page_shift); + chipnr = (int)(ofs >> this->chip_shift); + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_READING); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + } else + page = (int) ofs; + + if (this->options & NAND_BUSWIDTH_16) { + this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos & 0xFE, page & this->pagemask); + bad = cpu_to_le16(this->read_word(mtd)); + if (this->badblockpos & 0x1) + bad >>= 1; + if ((bad & 0xFF) != 0xff) + res = 1; + } else { + this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos, page & this->pagemask); + if (this->read_byte(mtd) != 0xff) + res = 1; + } + + if (getchip) { + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + } + + return res; +} + +/** + * nand_default_block_markbad - [DEFAULT] mark a block bad + * @mtd: MTD device structure + * @ofs: offset from device start + * + * This is the default implementation, which can be overridden by + * a hardware specific driver. +*/ +static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) +{ + struct nand_chip *this = mtd->priv; + u_char buf[2] = {0, 0}; + size_t retlen; + int block; + + /* Get block number */ + block = ((int) ofs) >> this->bbt_erase_shift; + this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); + + /* Do we have a flash based bad block table ? */ + if (this->options & NAND_USE_FLASH_BBT) + return nand_update_bbt (mtd, ofs); + + /* We write two bytes, so we dont have to mess with 16 bit access */ + ofs += mtd->oobsize + (this->badblockpos & ~0x01); + return nand_write_oob (mtd, ofs , 2, &retlen, buf); +} + +/** + * nand_check_wp - [GENERIC] check if the chip is write protected + * @mtd: MTD device structure + * Check, if the device is write protected + * + * The function expects, that the device is already selected + */ +static int nand_check_wp (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + /* Check the WP bit */ + this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1); + return (this->read_byte(mtd) & 0x80) ? 0 : 1; +} + +/** + * nand_block_checkbad - [GENERIC] Check if a block is marked bad + * @mtd: MTD device structure + * @ofs: offset from device start + * @getchip: 0, if the chip is already selected + * @allowbbt: 1, if its allowed to access the bbt area + * + * Check, if the block is bad. Either by reading the bad block table or + * calling of the scan function. + */ +static int nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt) +{ + struct nand_chip *this = mtd->priv; + + if (!this->bbt) + return this->block_bad(mtd, ofs, getchip); + + /* Return info from the table */ + return nand_isbad_bbt (mtd, ofs, allowbbt); +} + +/** + * nand_command - [DEFAULT] Send command to NAND device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + * + * Send command to NAND device. This function is used for small page + * devices (256/512 Bytes per page) + */ +static void nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* + * Write out the command to the device. + */ + if (command == NAND_CMD_SEQIN) { + int readcmd; + + if (column >= mtd->oobblock) { + /* OOB area */ + column -= mtd->oobblock; + readcmd = NAND_CMD_READOOB; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + readcmd = NAND_CMD_READ0; + } else { + column -= 256; + readcmd = NAND_CMD_READ1; + } + this->write_byte(mtd, readcmd); + } + this->write_byte(mtd, command); + + /* Set ALE and clear CLE to start address cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column); + } + if (page_addr != -1) { + this->write_byte(mtd, (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 32MiB */ + if (this->chipsize > (32 << 20)) + this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0x0f)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_STATUS: + return; + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + +/** + * nand_command_lp - [DEFAULT] Send command to NAND large page device + * @mtd: MTD device structure + * @command: the command to be sent + * @column: the column address for this command, -1 if none + * @page_addr: the page address for this command, -1 if none + * + * Send command to NAND device. This is the version for the new large page devices + * We dont have the seperate regions as we have in the small page devices. + * We must emulate NAND_CMD_READOOB to keep the code compatible. + * + */ +static void nand_command_lp (struct mtd_info *mtd, unsigned command, int column, int page_addr) +{ + register struct nand_chip *this = mtd->priv; + + /* Emulate NAND_CMD_READOOB */ + if (command == NAND_CMD_READOOB) { + column += mtd->oobblock; + command = NAND_CMD_READ0; + } + + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the command to the device. */ + this->write_byte(mtd, command); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + if (column != -1 || page_addr != -1) { + this->hwcontrol(mtd, NAND_CTL_SETALE); + + /* Serially input address */ + if (column != -1) { + /* Adjust columns for 16 bit buswidth */ + if (this->options & NAND_BUSWIDTH_16) + column >>= 1; + this->write_byte(mtd, column & 0xff); + this->write_byte(mtd, column >> 8); + } + if (page_addr != -1) { + this->write_byte(mtd, (unsigned char) (page_addr & 0xff)); + this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff)); + /* One more address cycle for devices > 128MiB */ + if (this->chipsize > (128 << 20)) + this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0xff)); + } + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + } + + /* + * program and erase have their own busy handlers + * status and sequential in needs no delay + */ + switch (command) { + + case NAND_CMD_CACHEDPROG: + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_SEQIN: + case NAND_CMD_STATUS: + return; + + + case NAND_CMD_RESET: + if (this->dev_ready) + break; + udelay(this->chip_delay); + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, NAND_CMD_STATUS); + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + while ( !(this->read_byte(mtd) & 0x40)); + return; + + case NAND_CMD_READ0: + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the start read command */ + this->write_byte(mtd, NAND_CMD_READSTART); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + /* Fall through into ready check */ + + /* This applies to read commands */ + default: + /* + * If we don't have access to the busy pin, we apply the given + * command delay + */ + if (!this->dev_ready) { + udelay (this->chip_delay); + return; + } + } + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + /* wait until command is processed */ + while (!this->dev_ready(mtd)); +} + +/** + * nand_get_device - [GENERIC] Get chip for selected access + * @this: the nand chip descriptor + * @mtd: MTD device structure + * @new_state: the state which is requested + * + * Get the device and lock it for exclusive access + */ +/* XXX U-BOOT XXX */ +#if 0 +static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state) +{ + struct nand_chip *active = this; + + DECLARE_WAITQUEUE (wait, current); + + /* + * Grab the lock and see if the device is available + */ +retry: + /* Hardware controller shared among independend devices */ + if (this->controller) { + spin_lock (&this->controller->lock); + if (this->controller->active) + active = this->controller->active; + else + this->controller->active = this; + spin_unlock (&this->controller->lock); + } + + if (active == this) { + spin_lock (&this->chip_lock); + if (this->state == FL_READY) { + this->state = new_state; + spin_unlock (&this->chip_lock); + return; + } + } + set_current_state (TASK_UNINTERRUPTIBLE); + add_wait_queue (&active->wq, &wait); + spin_unlock (&active->chip_lock); + schedule (); + remove_wait_queue (&active->wq, &wait); + goto retry; +} +#else +static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state) {} +#endif + +/** + * nand_wait - [DEFAULT] wait until the command is done + * @mtd: MTD device structure + * @this: NAND chip structure + * @state: state to select the max. timeout value + * + * Wait for command done. This applies to erase and program only + * Erase can take up to 400ms and program up to 20ms according to + * general NAND and SmartMedia specs + * +*/ +/* XXX U-BOOT XXX */ +#if 0 +static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long timeo = jiffies; + int status; + + if (state == FL_ERASING) + timeo += (HZ * 400) / 1000; + else + timeo += (HZ * 20) / 1000; + + /* Apply this short delay always to ensure that we do wait tWB in + * any case on any machine. */ + ndelay (100); + + if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) + this->cmdfunc (mtd, NAND_CMD_STATUS_MULTI, -1, -1); + else + this->cmdfunc (mtd, NAND_CMD_STATUS, -1, -1); + + while (time_before(jiffies, timeo)) { + /* Check, if we were interrupted */ + if (this->state != state) + return 0; + + if (this->dev_ready) { + if (this->dev_ready(mtd)) + break; + } else { + if (this->read_byte(mtd) & NAND_STATUS_READY) + break; + } + yield (); + } + status = (int) this->read_byte(mtd); + return status; + + return 0; +} +#else +static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) +{ + unsigned long timeo; + + if (state == FL_ERASING) + timeo = CFG_HZ * 400; + else + timeo = CFG_HZ * 20; + + if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) + this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); + else + this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); + + reset_timer(); + + while (1) { + if (get_timer(0) > timeo) { + printf("Timeout!"); + return 0; + } + + if (this->dev_ready) { + if (this->dev_ready(mtd)) + break; + } else { + if (this->read_byte(mtd) & NAND_STATUS_READY) + break; + } + } +#ifdef PPCHAMELON_NAND_TIMER_HACK + reset_timer(); + while (get_timer(0) < 10); +#endif /* PPCHAMELON_NAND_TIMER_HACK */ + + return this->read_byte(mtd); +} +#endif + +/** + * nand_write_page - [GENERIC] write one page + * @mtd: MTD device structure + * @this: NAND chip structure + * @page: startpage inside the chip, must be called with (page & this->pagemask) + * @oob_buf: out of band data buffer + * @oobsel: out of band selecttion structre + * @cached: 1 = enable cached programming if supported by chip + * + * Nand_page_program function is used for write and writev ! + * This function will always program a full page of data + * If you call it with a non page aligned buffer, you're lost :) + * + * Cached programming is not supported yet. + */ +static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, + u_char *oob_buf, struct nand_oobinfo *oobsel, int cached) +{ + int i, status; + u_char ecc_code[32]; + int eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE; + uint *oob_config = oobsel->eccpos; + int datidx = 0, eccidx = 0, eccsteps = this->eccsteps; + int eccbytes = 0; + + /* FIXME: Enable cached programming */ + cached = 0; + + /* Send command to begin auto page programming */ + this->cmdfunc (mtd, NAND_CMD_SEQIN, 0x00, page); + + /* Write out complete page of data, take care of eccmode */ + switch (eccmode) { + /* No ecc, write all */ + case NAND_ECC_NONE: + printk (KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n"); + this->write_buf(mtd, this->data_poi, mtd->oobblock); + break; + + /* Software ecc 3/256, write all */ + case NAND_ECC_SOFT: + for (; eccsteps; eccsteps--) { + this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code); + for (i = 0; i < 3; i++, eccidx++) + oob_buf[oob_config[eccidx]] = ecc_code[i]; + datidx += this->eccsize; + } + this->write_buf(mtd, this->data_poi, mtd->oobblock); + break; + default: + eccbytes = this->eccbytes; + for (; eccsteps; eccsteps--) { + /* enable hardware ecc logic for write */ + this->enable_hwecc(mtd, NAND_ECC_WRITE); + this->write_buf(mtd, &this->data_poi[datidx], this->eccsize); + this->calculate_ecc(mtd, &this->data_poi[datidx], ecc_code); + for (i = 0; i < eccbytes; i++, eccidx++) + oob_buf[oob_config[eccidx]] = ecc_code[i]; + /* If the hardware ecc provides syndromes then + * the ecc code must be written immidiately after + * the data bytes (words) */ + if (this->options & NAND_HWECC_SYNDROME) + this->write_buf(mtd, ecc_code, eccbytes); + datidx += this->eccsize; + } + break; + } + + /* Write out OOB data */ + if (this->options & NAND_HWECC_SYNDROME) + this->write_buf(mtd, &oob_buf[oobsel->eccbytes], mtd->oobsize - oobsel->eccbytes); + else + this->write_buf(mtd, oob_buf, mtd->oobsize); + + /* Send command to actually program the data */ + this->cmdfunc (mtd, cached ? NAND_CMD_CACHEDPROG : NAND_CMD_PAGEPROG, -1, -1); + + if (!cached) { + /* call wait ready function */ + status = this->waitfunc (mtd, this, FL_WRITING); + /* See if device thinks it succeeded */ + if (status & 0x01) { + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page); + return -EIO; + } + } else { + /* FIXME: Implement cached programming ! */ + /* wait until cache is ready*/ + /* status = this->waitfunc (mtd, this, FL_CACHEDRPG); */ + } + return 0; +} + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE +/** + * nand_verify_pages - [GENERIC] verify the chip contents after a write + * @mtd: MTD device structure + * @this: NAND chip structure + * @page: startpage inside the chip, must be called with (page & this->pagemask) + * @numpages: number of pages to verify + * @oob_buf: out of band data buffer + * @oobsel: out of band selecttion structre + * @chipnr: number of the current chip + * @oobmode: 1 = full buffer verify, 0 = ecc only + * + * The NAND device assumes that it is always writing to a cleanly erased page. + * Hence, it performs its internal write verification only on bits that + * transitioned from 1 to 0. The device does NOT verify the whole page on a + * byte by byte basis. It is possible that the page was not completely erased + * or the page is becoming unusable due to wear. The read with ECC would catch + * the error later when the ECC page check fails, but we would rather catch + * it early in the page write stage. Better to write no data than invalid data. + */ +static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int page, int numpages, + u_char *oob_buf, struct nand_oobinfo *oobsel, int chipnr, int oobmode) +{ + int i, j, datidx = 0, oobofs = 0, res = -EIO; + int eccsteps = this->eccsteps; + int hweccbytes; + u_char oobdata[64]; + + hweccbytes = (this->options & NAND_HWECC_SYNDROME) ? (oobsel->eccbytes / eccsteps) : 0; + + /* Send command to read back the first page */ + this->cmdfunc (mtd, NAND_CMD_READ0, 0, page); + + for(;;) { + for (j = 0; j < eccsteps; j++) { + /* Loop through and verify the data */ + if (this->verify_buf(mtd, &this->data_poi[datidx], mtd->eccsize)) { + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + goto out; + } + datidx += mtd->eccsize; + /* Have we a hw generator layout ? */ + if (!hweccbytes) + continue; + if (this->verify_buf(mtd, &this->oob_buf[oobofs], hweccbytes)) { + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + goto out; + } + oobofs += hweccbytes; + } + + /* check, if we must compare all data or if we just have to + * compare the ecc bytes + */ + if (oobmode) { + if (this->verify_buf(mtd, &oob_buf[oobofs], mtd->oobsize - hweccbytes * eccsteps)) { + DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page); + goto out; + } + } else { + /* Read always, else autoincrement fails */ + this->read_buf(mtd, oobdata, mtd->oobsize - hweccbytes * eccsteps); + + if (oobsel->useecc != MTD_NANDECC_OFF && !hweccbytes) { + int ecccnt = oobsel->eccbytes; + + for (i = 0; i < ecccnt; i++) { + int idx = oobsel->eccpos[i]; + if (oobdata[idx] != oob_buf[oobofs + idx] ) { + DEBUG (MTD_DEBUG_LEVEL0, + "%s: Failed ECC write " + "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i); + goto out; + } + } + } + } + oobofs += mtd->oobsize - hweccbytes * eccsteps; + page++; + numpages--; + + /* Apply delay or wait for ready/busy pin + * Do this before the AUTOINCR check, so no problems + * arise if a chip which does auto increment + * is marked as NOAUTOINCR by the board driver. + * Do this also before returning, so the chip is + * ready for the next command. + */ + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + /* All done, return happy */ + if (!numpages) + return 0; + + + /* Check, if the chip supports auto page increment */ + if (!NAND_CANAUTOINCR(this)) + this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page); + } + /* + * Terminate the read command. We come here in case of an error + * So we must issue a reset command. + */ +out: + this->cmdfunc (mtd, NAND_CMD_RESET, -1, -1); + return res; +} +#endif + +/** + * nand_read - [MTD Interface] MTD compability function for nand_read_ecc + * @mtd: MTD device structure + * @from: offset to read from + * @len: number of bytes to read + * @retlen: pointer to variable to store the number of read bytes + * @buf: the databuffer to put data + * + * This function simply calls nand_read_ecc with oob buffer and oobsel = NULL +*/ +static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf) +{ + return nand_read_ecc (mtd, from, len, retlen, buf, NULL, NULL); +} + + +/** + * nand_read_ecc - [MTD Interface] Read data with ECC + * @mtd: MTD device structure + * @from: offset to read from + * @len: number of bytes to read + * @retlen: pointer to variable to store the number of read bytes + * @buf: the databuffer to put data + * @oob_buf: filesystem supplied oob data buffer + * @oobsel: oob selection structure + * + * NAND read with ECC + */ +static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, + size_t * retlen, u_char * buf, u_char * oob_buf, struct nand_oobinfo *oobsel) +{ + int i, j, col, realpage, page, end, ecc, chipnr, sndcmd = 1; + int read = 0, oob = 0, ecc_status = 0, ecc_failed = 0; + struct nand_chip *this = mtd->priv; + u_char *data_poi, *oob_data = oob_buf; + u_char ecc_calc[32]; + u_char ecc_code[32]; + int eccmode, eccsteps; + unsigned *oob_config; + int datidx; + int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; + int eccbytes; + int compareecc = 1; + int oobreadlen; + + + DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n"); + *retlen = 0; + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd ,FL_READING); + + /* use userspace supplied oobinfo, if zero */ + if (oobsel == NULL) + oobsel = &mtd->oobinfo; + + /* Autoplace of oob data ? Use the default placement scheme */ + if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) + oobsel = this->autooob; + + eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE; + oob_config = oobsel->eccpos; + + /* Select the NAND device */ + chipnr = (int)(from >> this->chip_shift); + this->select_chip(mtd, chipnr); + + /* First we calculate the starting page */ + realpage = (int) (from >> this->page_shift); + page = realpage & this->pagemask; + + /* Get raw starting column */ + col = from & (mtd->oobblock - 1); + + end = mtd->oobblock; + ecc = this->eccsize; + eccbytes = this->eccbytes; + + if ((eccmode == NAND_ECC_NONE) || (this->options & NAND_HWECC_SYNDROME)) + compareecc = 0; + + oobreadlen = mtd->oobsize; + if (this->options & NAND_HWECC_SYNDROME) + oobreadlen -= oobsel->eccbytes; + + /* Loop until all data read */ + while (read < len) { + + int aligned = (!col && (len - read) >= end); + /* + * If the read is not page aligned, we have to read into data buffer + * due to ecc, else we read into return buffer direct + */ + if (aligned) + data_poi = &buf[read]; + else + data_poi = this->data_buf; + + /* Check, if we have this page in the buffer + * + * FIXME: Make it work when we must provide oob data too, + * check the usage of data_buf oob field + */ + if (realpage == this->pagebuf && !oob_buf) { + /* aligned read ? */ + if (aligned) + memcpy (data_poi, this->data_buf, end); + goto readdata; + } + + /* Check, if we must send the read command */ + if (sndcmd) { + this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page); + sndcmd = 0; + } + + /* get oob area, if we have no oob buffer from fs-driver */ + if (!oob_buf || oobsel->useecc == MTD_NANDECC_AUTOPLACE || + oobsel->useecc == MTD_NANDECC_AUTOPL_USR) + oob_data = &this->data_buf[end]; + + eccsteps = this->eccsteps; + + switch (eccmode) { + case NAND_ECC_NONE: { /* No ECC, Read in a page */ +/* XXX U-BOOT XXX */ +#if 0 + static unsigned long lastwhinge = 0; + if ((lastwhinge / HZ) != (jiffies / HZ)) { + printk (KERN_WARNING "Reading data from NAND FLASH without ECC is not recommended\n"); + lastwhinge = jiffies; + } +#else + puts("Reading data from NAND FLASH without ECC is not recommended\n"); +#endif + this->read_buf(mtd, data_poi, end); + break; + } + + case NAND_ECC_SOFT: /* Software ECC 3/256: Read in a page + oob data */ + this->read_buf(mtd, data_poi, end); + for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=3, datidx += ecc) + this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]); + break; + + default: + for (i = 0, datidx = 0; eccsteps; eccsteps--, i+=eccbytes, datidx += ecc) { + this->enable_hwecc(mtd, NAND_ECC_READ); + this->read_buf(mtd, &data_poi[datidx], ecc); + + /* HW ecc with syndrome calculation must read the + * syndrome from flash immidiately after the data */ + if (!compareecc) { + /* Some hw ecc generators need to know when the + * syndrome is read from flash */ + this->enable_hwecc(mtd, NAND_ECC_READSYN); + this->read_buf(mtd, &oob_data[i], eccbytes); + /* We calc error correction directly, it checks the hw + * generator for an error, reads back the syndrome and + * does the error correction on the fly */ + if (this->correct_data(mtd, &data_poi[datidx], &oob_data[i], &ecc_code[i]) == -1) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " + "Failed ECC read, page 0x%08x on chip %d\n", page, chipnr); + ecc_failed++; + } + } else { + this->calculate_ecc(mtd, &data_poi[datidx], &ecc_calc[i]); + } + } + break; + } + + /* read oobdata */ + this->read_buf(mtd, &oob_data[mtd->oobsize - oobreadlen], oobreadlen); + + /* Skip ECC check, if not requested (ECC_NONE or HW_ECC with syndromes) */ + if (!compareecc) + goto readoob; + + /* Pick the ECC bytes out of the oob data */ + for (j = 0; j < oobsel->eccbytes; j++) + ecc_code[j] = oob_data[oob_config[j]]; + + /* correct data, if neccecary */ + for (i = 0, j = 0, datidx = 0; i < this->eccsteps; i++, datidx += ecc) { + ecc_status = this->correct_data(mtd, &data_poi[datidx], &ecc_code[j], &ecc_calc[j]); + + /* Get next chunk of ecc bytes */ + j += eccbytes; + + /* Check, if we have a fs supplied oob-buffer, + * This is the legacy mode. Used by YAFFS1 + * Should go away some day + */ + if (oob_buf && oobsel->useecc == MTD_NANDECC_PLACE) { + int *p = (int *)(&oob_data[mtd->oobsize]); + p[i] = ecc_status; + } + + if (ecc_status == -1) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: " "Failed ECC read, page 0x%08x\n", page); + ecc_failed++; + } + } + + readoob: + /* check, if we have a fs supplied oob-buffer */ + if (oob_buf) { + /* without autoplace. Legacy mode used by YAFFS1 */ + switch(oobsel->useecc) { + case MTD_NANDECC_AUTOPLACE: + case MTD_NANDECC_AUTOPL_USR: + /* Walk through the autoplace chunks */ + for (i = 0, j = 0; j < mtd->oobavail; i++) { + int from = oobsel->oobfree[i][0]; + int num = oobsel->oobfree[i][1]; + memcpy(&oob_buf[oob], &oob_data[from], num); + j+= num; + } + oob += mtd->oobavail; + break; + case MTD_NANDECC_PLACE: + /* YAFFS1 legacy mode */ + oob_data += this->eccsteps * sizeof (int); + default: + oob_data += mtd->oobsize; + } + } + readdata: + /* Partial page read, transfer data into fs buffer */ + if (!aligned) { + for (j = col; j < end && read < len; j++) + buf[read++] = data_poi[j]; + this->pagebuf = realpage; + } else + read += mtd->oobblock; + + /* Apply delay or wait for ready/busy pin + * Do this before the AUTOINCR check, so no problems + * arise if a chip which does auto increment + * is marked as NOAUTOINCR by the board driver. + */ + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + if (read == len) + break; + + /* For subsequent reads align to page boundary. */ + col = 0; + /* Increment page address */ + realpage++; + + page = realpage & this->pagemask; + /* Check, if we cross a chip boundary */ + if (!page) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + /* Check, if the chip supports auto page increment + * or if we have hit a block boundary. + */ + if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) + sndcmd = 1; + } + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + /* + * Return success, if no ECC failures, else -EBADMSG + * fs driver will take care of that, because + * retlen == desired len and result == -EBADMSG + */ + *retlen = read; + return ecc_failed ? -EBADMSG : 0; +} + +/** + * nand_read_oob - [MTD Interface] NAND read out-of-band + * @mtd: MTD device structure + * @from: offset to read from + * @len: number of bytes to read + * @retlen: pointer to variable to store the number of read bytes + * @buf: the databuffer to put data + * + * NAND read out-of-band data from the spare area + */ +static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf) +{ + int i, col, page, chipnr; + struct nand_chip *this = mtd->priv; + int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; + + DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + + /* Shift to get page */ + page = (int)(from >> this->page_shift); + chipnr = (int)(from >> this->chip_shift); + + /* Mask to get column */ + col = from & (mtd->oobsize - 1); + + /* Initialize return length value */ + *retlen = 0; + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: Attempt read beyond end of device\n"); + *retlen = 0; + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd , FL_READING); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Send the read command */ + this->cmdfunc (mtd, NAND_CMD_READOOB, col, page & this->pagemask); + /* + * Read the data, if we read more than one page + * oob data, let the device transfer the data ! + */ + i = 0; + while (i < len) { + int thislen = mtd->oobsize - col; + thislen = min_t(int, thislen, len); + this->read_buf(mtd, &buf[i], thislen); + i += thislen; + + /* Apply delay or wait for ready/busy pin + * Do this before the AUTOINCR check, so no problems + * arise if a chip which does auto increment + * is marked as NOAUTOINCR by the board driver. + */ + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + /* Read more ? */ + if (i < len) { + page++; + col = 0; + + /* Check, if we cross a chip boundary */ + if (!(page & this->pagemask)) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + + /* Check, if the chip supports auto page increment + * or if we have hit a block boundary. + */ + if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) { + /* For subsequent page reads set offset to 0 */ + this->cmdfunc (mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask); + } + } + } + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + /* Return happy */ + *retlen = len; + return 0; +} + +/** + * nand_read_raw - [GENERIC] Read raw data including oob into buffer + * @mtd: MTD device structure + * @buf: temporary buffer + * @from: offset to read from + * @len: number of bytes to read + * @ooblen: number of oob data bytes to read + * + * Read raw data including oob into buffer + */ +int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen) +{ + struct nand_chip *this = mtd->priv; + int page = (int) (from >> this->page_shift); + int chip = (int) (from >> this->chip_shift); + int sndcmd = 1; + int cnt = 0; + int pagesize = mtd->oobblock + mtd->oobsize; + int blockcheck = (1 << (this->phys_erase_shift - this->page_shift)) - 1; + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt read beyond end of device\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd , FL_READING); + + this->select_chip (mtd, chip); + + /* Add requested oob length */ + len += ooblen; + + while (len) { + if (sndcmd) + this->cmdfunc (mtd, NAND_CMD_READ0, 0, page & this->pagemask); + sndcmd = 0; + + this->read_buf (mtd, &buf[cnt], pagesize); + + len -= pagesize; + cnt += pagesize; + page++; + + if (!this->dev_ready) + udelay (this->chip_delay); + else + while (!this->dev_ready(mtd)); + + /* Check, if the chip supports auto page increment */ + if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) + sndcmd = 1; + } + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + return 0; +} + + +/** + * nand_prepare_oobbuf - [GENERIC] Prepare the out of band buffer + * @mtd: MTD device structure + * @fsbuf: buffer given by fs driver + * @oobsel: out of band selection structre + * @autoplace: 1 = place given buffer into the oob bytes + * @numpages: number of pages to prepare + * + * Return: + * 1. Filesystem buffer available and autoplacement is off, + * return filesystem buffer + * 2. No filesystem buffer or autoplace is off, return internal + * buffer + * 3. Filesystem buffer is given and autoplace selected + * put data from fs buffer into internal buffer and + * retrun internal buffer + * + * Note: The internal buffer is filled with 0xff. This must + * be done only once, when no autoplacement happens + * Autoplacement sets the buffer dirty flag, which + * forces the 0xff fill before using the buffer again. + * +*/ +static u_char * nand_prepare_oobbuf (struct mtd_info *mtd, u_char *fsbuf, struct nand_oobinfo *oobsel, + int autoplace, int numpages) +{ + struct nand_chip *this = mtd->priv; + int i, len, ofs; + + /* Zero copy fs supplied buffer */ + if (fsbuf && !autoplace) + return fsbuf; + + /* Check, if the buffer must be filled with ff again */ + if (this->oobdirty) { + memset (this->oob_buf, 0xff, + mtd->oobsize << (this->phys_erase_shift - this->page_shift)); + this->oobdirty = 0; + } + + /* If we have no autoplacement or no fs buffer use the internal one */ + if (!autoplace || !fsbuf) + return this->oob_buf; + + /* Walk through the pages and place the data */ + this->oobdirty = 1; + ofs = 0; + while (numpages--) { + for (i = 0, len = 0; len < mtd->oobavail; i++) { + int to = ofs + oobsel->oobfree[i][0]; + int num = oobsel->oobfree[i][1]; + memcpy (&this->oob_buf[to], fsbuf, num); + len += num; + fsbuf += num; + } + ofs += mtd->oobavail; + } + return this->oob_buf; +} + +#define NOTALIGNED(x) (x & (mtd->oobblock-1)) != 0 + +/** + * nand_write - [MTD Interface] compability function for nand_write_ecc + * @mtd: MTD device structure + * @to: offset to write to + * @len: number of bytes to write + * @retlen: pointer to variable to store the number of written bytes + * @buf: the data to write + * + * This function simply calls nand_write_ecc with oob buffer and oobsel = NULL + * +*/ +static int nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf) +{ + return (nand_write_ecc (mtd, to, len, retlen, buf, NULL, NULL)); +} + +/** + * nand_write_ecc - [MTD Interface] NAND write with ECC + * @mtd: MTD device structure + * @to: offset to write to + * @len: number of bytes to write + * @retlen: pointer to variable to store the number of written bytes + * @buf: the data to write + * @eccbuf: filesystem supplied oob data buffer + * @oobsel: oob selection structure + * + * NAND write with ECC + */ +static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, + size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel) +{ + int startpage, page, ret = -EIO, oob = 0, written = 0, chipnr; + int autoplace = 0, numpages, totalpages; + struct nand_chip *this = mtd->priv; + u_char *oobbuf, *bufstart; + int ppblock = (1 << (this->phys_erase_shift - this->page_shift)); + + DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + + /* Initialize retlen, in case of early exit */ + *retlen = 0; + + /* Do not allow write past end of device */ + if ((to + len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n"); + return -EINVAL; + } + + /* reject writes, which are not page aligned */ + if (NOTALIGNED (to) || NOTALIGNED(len)) { + printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_WRITING); + + /* Calculate chipnr */ + chipnr = (int)(to >> this->chip_shift); + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) + goto out; + + /* if oobsel is NULL, use chip defaults */ + if (oobsel == NULL) + oobsel = &mtd->oobinfo; + + /* Autoplace of oob data ? Use the default placement scheme */ + if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) { + oobsel = this->autooob; + autoplace = 1; + } + if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR) + autoplace = 1; + + /* Setup variables and oob buffer */ + totalpages = len >> this->page_shift; + page = (int) (to >> this->page_shift); + /* Invalidate the page cache, if we write to the cached page */ + if (page <= this->pagebuf && this->pagebuf < (page + totalpages)) + this->pagebuf = -1; + + /* Set it relative to chip */ + page &= this->pagemask; + startpage = page; + /* Calc number of pages we can write in one go */ + numpages = min (ppblock - (startpage & (ppblock - 1)), totalpages); + oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel, autoplace, numpages); + bufstart = (u_char *)buf; + + /* Loop until all data is written */ + while (written < len) { + + this->data_poi = (u_char*) &buf[written]; + /* Write one page. If this is the last page to write + * or the last page in this block, then use the + * real pageprogram command, else select cached programming + * if supported by the chip. + */ + ret = nand_write_page (mtd, this, page, &oobbuf[oob], oobsel, (--numpages > 0)); + if (ret) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: write_page failed %d\n", ret); + goto out; + } + /* Next oob page */ + oob += mtd->oobsize; + /* Update written bytes count */ + written += mtd->oobblock; + if (written == len) + goto cmp; + + /* Increment page address */ + page++; + + /* Have we hit a block boundary ? Then we have to verify and + * if verify is ok, we have to setup the oob buffer for + * the next pages. + */ + if (!(page & (ppblock - 1))){ + int ofs; + this->data_poi = bufstart; + ret = nand_verify_pages (mtd, this, startpage, + page - startpage, + oobbuf, oobsel, chipnr, (eccbuf != NULL)); + if (ret) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret); + goto out; + } + *retlen = written; + + ofs = autoplace ? mtd->oobavail : mtd->oobsize; + if (eccbuf) + eccbuf += (page - startpage) * ofs; + totalpages -= page - startpage; + numpages = min (totalpages, ppblock); + page &= this->pagemask; + startpage = page; + oob = 0; + this->oobdirty = 1; + oobbuf = nand_prepare_oobbuf (mtd, eccbuf, oobsel, + autoplace, numpages); + /* Check, if we cross a chip boundary */ + if (!page) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + } + } + /* Verify the remaining pages */ +cmp: + this->data_poi = bufstart; + ret = nand_verify_pages (mtd, this, startpage, totalpages, + oobbuf, oobsel, chipnr, (eccbuf != NULL)); + if (!ret) + *retlen = written; + else + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: verify_pages failed %d\n", ret); + +out: + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + return ret; +} + + +/** + * nand_write_oob - [MTD Interface] NAND write out-of-band + * @mtd: MTD device structure + * @to: offset to write to + * @len: number of bytes to write + * @retlen: pointer to variable to store the number of written bytes + * @buf: the data to write + * + * NAND write out-of-band + */ +static int nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf) +{ + int column, page, status, ret = -EIO, chipnr; + struct nand_chip *this = mtd->priv; + + DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + + /* Shift to get page */ + page = (int) (to >> this->page_shift); + chipnr = (int) (to >> this->chip_shift); + + /* Mask to get column */ + column = to & (mtd->oobsize - 1); + + /* Initialize return length value */ + *retlen = 0; + + /* Do not allow write past end of page */ + if ((column + len) > mtd->oobsize) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_WRITING); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Reset the chip. Some chips (like the Toshiba TC5832DC found + in one of my DiskOnChip 2000 test units) will clear the whole + data page too if we don't do this. I have no clue why, but + I seem to have 'fixed' it in the doc2000 driver in + August 1999. dwmw2. */ + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) + goto out; + + /* Invalidate the page cache, if we write to the cached page */ + if (page == this->pagebuf) + this->pagebuf = -1; + + if (NAND_MUST_PAD(this)) { + /* Write out desired data */ + this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page & this->pagemask); + /* prepad 0xff for partial programming */ + this->write_buf(mtd, ffchars, column); + /* write data */ + this->write_buf(mtd, buf, len); + /* postpad 0xff for partial programming */ + this->write_buf(mtd, ffchars, mtd->oobsize - (len+column)); + } else { + /* Write out desired data */ + this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock + column, page & this->pagemask); + /* write data */ + this->write_buf(mtd, buf, len); + } + /* Send command to program the OOB data */ + this->cmdfunc (mtd, NAND_CMD_PAGEPROG, -1, -1); + + status = this->waitfunc (mtd, this, FL_WRITING); + + /* See if device thinks it succeeded */ + if (status & 0x01) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page); + ret = -EIO; + goto out; + } + /* Return happy */ + *retlen = len; + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* Send command to read back the data */ + this->cmdfunc (mtd, NAND_CMD_READOOB, column, page & this->pagemask); + + if (this->verify_buf(mtd, buf, len)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write verify, page 0x%08x\n", page); + ret = -EIO; + goto out; + } +#endif + ret = 0; +out: + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + return ret; +} + +/* XXX U-BOOT XXX */ +#if 0 +/** + * nand_writev - [MTD Interface] compabilty function for nand_writev_ecc + * @mtd: MTD device structure + * @vecs: the iovectors to write + * @count: number of vectors + * @to: offset to write to + * @retlen: pointer to variable to store the number of written bytes + * + * NAND write with kvec. This just calls the ecc function + */ +static int nand_writev (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, + loff_t to, size_t * retlen) +{ + return (nand_writev_ecc (mtd, vecs, count, to, retlen, NULL, NULL)); +} + +/** + * nand_writev_ecc - [MTD Interface] write with iovec with ecc + * @mtd: MTD device structure + * @vecs: the iovectors to write + * @count: number of vectors + * @to: offset to write to + * @retlen: pointer to variable to store the number of written bytes + * @eccbuf: filesystem supplied oob data buffer + * @oobsel: oob selection structure + * + * NAND write with iovec with ecc + */ +static int nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, + loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel) +{ + int i, page, len, total_len, ret = -EIO, written = 0, chipnr; + int oob, numpages, autoplace = 0, startpage; + struct nand_chip *this = mtd->priv; + int ppblock = (1 << (this->phys_erase_shift - this->page_shift)); + u_char *oobbuf, *bufstart; + + /* Preset written len for early exit */ + *retlen = 0; + + /* Calculate total length of data */ + total_len = 0; + for (i = 0; i < count; i++) + total_len += (int) vecs[i].iov_len; + + DEBUG (MTD_DEBUG_LEVEL3, + "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count); + + /* Do not allow write past end of page */ + if ((to + total_len) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n"); + return -EINVAL; + } + + /* reject writes, which are not page aligned */ + if (NOTALIGNED (to) || NOTALIGNED(total_len)) { + printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_WRITING); + + /* Get the current chip-nr */ + chipnr = (int) (to >> this->chip_shift); + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) + goto out; + + /* if oobsel is NULL, use chip defaults */ + if (oobsel == NULL) + oobsel = &mtd->oobinfo; + + /* Autoplace of oob data ? Use the default placement scheme */ + if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) { + oobsel = this->autooob; + autoplace = 1; + } + if (oobsel->useecc == MTD_NANDECC_AUTOPL_USR) + autoplace = 1; + + /* Setup start page */ + page = (int) (to >> this->page_shift); + /* Invalidate the page cache, if we write to the cached page */ + if (page <= this->pagebuf && this->pagebuf < ((to + total_len) >> this->page_shift)) + this->pagebuf = -1; + + startpage = page & this->pagemask; + + /* Loop until all kvec' data has been written */ + len = 0; + while (count) { + /* If the given tuple is >= pagesize then + * write it out from the iov + */ + if ((vecs->iov_len - len) >= mtd->oobblock) { + /* Calc number of pages we can write + * out of this iov in one go */ + numpages = (vecs->iov_len - len) >> this->page_shift; + /* Do not cross block boundaries */ + numpages = min (ppblock - (startpage & (ppblock - 1)), numpages); + oobbuf = nand_prepare_oobbuf (mtd, NULL, oobsel, autoplace, numpages); + bufstart = (u_char *)vecs->iov_base; + bufstart += len; + this->data_poi = bufstart; + oob = 0; + for (i = 1; i <= numpages; i++) { + /* Write one page. If this is the last page to write + * then use the real pageprogram command, else select + * cached programming if supported by the chip. + */ + ret = nand_write_page (mtd, this, page & this->pagemask, + &oobbuf[oob], oobsel, i != numpages); + if (ret) + goto out; + this->data_poi += mtd->oobblock; + len += mtd->oobblock; + oob += mtd->oobsize; + page++; + } + /* Check, if we have to switch to the next tuple */ + if (len >= (int) vecs->iov_len) { + vecs++; + len = 0; + count--; + } + } else { + /* We must use the internal buffer, read data out of each + * tuple until we have a full page to write + */ + int cnt = 0; + while (cnt < mtd->oobblock) { + if (vecs->iov_base != NULL && vecs->iov_len) + this->data_buf[cnt++] = ((u_char *) vecs->iov_base)[len++]; + /* Check, if we have to switch to the next tuple */ + if (len >= (int) vecs->iov_len) { + vecs++; + len = 0; + count--; + } + } + this->pagebuf = page; + this->data_poi = this->data_buf; + bufstart = this->data_poi; + numpages = 1; + oobbuf = nand_prepare_oobbuf (mtd, NULL, oobsel, autoplace, numpages); + ret = nand_write_page (mtd, this, page & this->pagemask, + oobbuf, oobsel, 0); + if (ret) + goto out; + page++; + } + + this->data_poi = bufstart; + ret = nand_verify_pages (mtd, this, startpage, numpages, oobbuf, oobsel, chipnr, 0); + if (ret) + goto out; + + written += mtd->oobblock * numpages; + /* All done ? */ + if (!count) + break; + + startpage = page & this->pagemask; + /* Check, if we cross a chip boundary */ + if (!startpage) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + } + ret = 0; +out: + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + *retlen = written; + return ret; +} +#endif + +/** + * single_erease_cmd - [GENERIC] NAND standard block erase command function + * @mtd: MTD device structure + * @page: the page address of the block which will be erased + * + * Standard erase command for NAND chips + */ +static void single_erase_cmd (struct mtd_info *mtd, int page) +{ + struct nand_chip *this = mtd->priv; + /* Send commands to erase a block */ + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page); + this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1); +} + +/** + * multi_erease_cmd - [GENERIC] AND specific block erase command function + * @mtd: MTD device structure + * @page: the page address of the block which will be erased + * + * AND multi block erase command function + * Erase 4 consecutive blocks + */ +static void multi_erase_cmd (struct mtd_info *mtd, int page) +{ + struct nand_chip *this = mtd->priv; + /* Send commands to erase a block */ + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++); + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++); + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page++); + this->cmdfunc (mtd, NAND_CMD_ERASE1, -1, page); + this->cmdfunc (mtd, NAND_CMD_ERASE2, -1, -1); +} + +/** + * nand_erase - [MTD Interface] erase block(s) + * @mtd: MTD device structure + * @instr: erase instruction + * + * Erase one ore more blocks + */ +static int nand_erase (struct mtd_info *mtd, struct erase_info *instr) +{ + return nand_erase_nand (mtd, instr, 0); +} + +/** + * nand_erase_intern - [NAND Interface] erase block(s) + * @mtd: MTD device structure + * @instr: erase instruction + * @allowbbt: allow erasing the bbt area + * + * Erase one ore more blocks + */ +int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt) +{ + int page, len, status, pages_per_block, ret, chipnr; + struct nand_chip *this = mtd->priv; + + DEBUG (MTD_DEBUG_LEVEL3, + "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); + + /* Start address must align on block boundary */ + if (instr->addr & ((1 << this->phys_erase_shift) - 1)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n"); + return -EINVAL; + } + + /* Length must align on block boundary */ + if (instr->len & ((1 << this->phys_erase_shift) - 1)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n"); + return -EINVAL; + } + + /* Do not allow erase past end of device */ + if ((instr->len + instr->addr) > mtd->size) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n"); + return -EINVAL; + } + + instr->fail_addr = 0xffffffff; + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_ERASING); + + /* Shift to get first page */ + page = (int) (instr->addr >> this->page_shift); + chipnr = (int) (instr->addr >> this->chip_shift); + + /* Calculate pages in each block */ + pages_per_block = 1 << (this->phys_erase_shift - this->page_shift); + + /* Select the NAND device */ + this->select_chip(mtd, chipnr); + + /* Check the WP bit */ + /* Check, if it is write protected */ + if (nand_check_wp(mtd)) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n"); + instr->state = MTD_ERASE_FAILED; + goto erase_exit; + } + + /* Loop through the pages */ + len = instr->len; + + instr->state = MTD_ERASING; + + while (len) { +#ifndef NAND_ALLOW_ERASE_ALL + /* Check if we have a bad block, we do not erase bad blocks ! */ + if (nand_block_checkbad(mtd, ((loff_t) page) << this->page_shift, 0, allowbbt)) { + printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page); + instr->state = MTD_ERASE_FAILED; + goto erase_exit; + } +#endif + /* Invalidate the page cache, if we erase the block which contains + the current cached page */ + if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block)) + this->pagebuf = -1; + + this->erase_cmd (mtd, page & this->pagemask); + + status = this->waitfunc (mtd, this, FL_ERASING); + + /* See if block erase succeeded */ + if (status & 0x01) { + DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page); + instr->state = MTD_ERASE_FAILED; + instr->fail_addr = (page << this->page_shift); + goto erase_exit; + } + + /* Increment page address and decrement length */ + len -= (1 << this->phys_erase_shift); + page += pages_per_block; + + /* Check, if we cross a chip boundary */ + if (len && !(page & this->pagemask)) { + chipnr++; + this->select_chip(mtd, -1); + this->select_chip(mtd, chipnr); + } + } + instr->state = MTD_ERASE_DONE; + +erase_exit: + + ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; + /* Do call back function */ + if (!ret) + mtd_erase_callback(instr); + + /* Deselect and wake up anyone waiting on the device */ + nand_release_device(mtd); + + /* Return more or less happy */ + return ret; +} + +/** + * nand_sync - [MTD Interface] sync + * @mtd: MTD device structure + * + * Sync is actually a wait for chip ready function + */ +static void nand_sync (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n"); + + /* Grab the lock and see if the device is available */ + nand_get_device (this, mtd, FL_SYNCING); + /* Release it and go back */ + nand_release_device (mtd); +} + + +/** + * nand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad + * @mtd: MTD device structure + * @ofs: offset relative to mtd start + */ +static int nand_block_isbad (struct mtd_info *mtd, loff_t ofs) +{ + /* Check for invalid offset */ + if (ofs > mtd->size) + return -EINVAL; + + return nand_block_checkbad (mtd, ofs, 1, 0); +} + +/** + * nand_block_markbad - [MTD Interface] Mark the block at the given offset as bad + * @mtd: MTD device structure + * @ofs: offset relative to mtd start + */ +static int nand_block_markbad (struct mtd_info *mtd, loff_t ofs) +{ + struct nand_chip *this = mtd->priv; + int ret; + + if ((ret = nand_block_isbad(mtd, ofs))) { + /* If it was bad already, return success and do nothing. */ + if (ret > 0) + return 0; + return ret; + } + + return this->block_markbad(mtd, ofs); +} + +/** + * nand_scan - [NAND Interface] Scan for the NAND device + * @mtd: MTD device structure + * @maxchips: Number of chips to scan for + * + * This fills out all the not initialized function pointers + * with the defaults. + * The flash ID is read and the mtd/chip structures are + * filled with the appropriate values. Buffers are allocated if + * they are not provided by the board driver + * + */ +int nand_scan (struct mtd_info *mtd, int maxchips) +{ + int i, j, nand_maf_id, nand_dev_id, busw; + struct nand_chip *this = mtd->priv; + + /* Get buswidth to select the correct functions*/ + busw = this->options & NAND_BUSWIDTH_16; + + /* check for proper chip_delay setup, set 20us if not */ + if (!this->chip_delay) + this->chip_delay = 20; + + /* check, if a user supplied command function given */ + if (this->cmdfunc == NULL) + this->cmdfunc = nand_command; + + /* check, if a user supplied wait function given */ + if (this->waitfunc == NULL) + this->waitfunc = nand_wait; + + if (!this->select_chip) + this->select_chip = nand_select_chip; + if (!this->write_byte) + this->write_byte = busw ? nand_write_byte16 : nand_write_byte; + if (!this->read_byte) + this->read_byte = busw ? nand_read_byte16 : nand_read_byte; + if (!this->write_word) + this->write_word = nand_write_word; + if (!this->read_word) + this->read_word = nand_read_word; + if (!this->block_bad) + this->block_bad = nand_block_bad; + if (!this->block_markbad) + this->block_markbad = nand_default_block_markbad; + if (!this->write_buf) + this->write_buf = busw ? nand_write_buf16 : nand_write_buf; + if (!this->read_buf) + this->read_buf = busw ? nand_read_buf16 : nand_read_buf; + if (!this->verify_buf) + this->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; + if (!this->scan_bbt) + this->scan_bbt = nand_default_bbt; + + /* Select the device */ + this->select_chip(mtd, 0); + + /* + * Reset the chip, required by some chips + * (e.g. Micron MT29FxGxxxxx) after power-up + */ + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* Send the command for reading device ID */ + this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + nand_maf_id = this->read_byte(mtd); + nand_dev_id = this->read_byte(mtd); + + /* Print and store flash device information */ + for (i = 0; nand_flash_ids[i].name != NULL; i++) { + + if (nand_dev_id != nand_flash_ids[i].id) + continue; + + if (!mtd->name) mtd->name = nand_flash_ids[i].name; + this->chipsize = nand_flash_ids[i].chipsize << 20; + + /* New devices have all the information in additional id bytes */ + if (!nand_flash_ids[i].pagesize) { + int extid; + /* The 3rd id byte contains non relevant data ATM */ + extid = this->read_byte(mtd); + /* The 4th id byte is the important one */ + extid = this->read_byte(mtd); + /* Calc pagesize */ + mtd->oobblock = 1024 << (extid & 0x3); + extid >>= 2; + /* Calc oobsize */ + mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512); + extid >>= 2; + /* Calc blocksize. Blocksize is multiples of 64KiB */ + mtd->erasesize = (64 * 1024) << (extid & 0x03); + extid >>= 2; + /* Get buswidth information */ + busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + + } else { + /* Old devices have this data hardcoded in the + * device id table */ + mtd->erasesize = nand_flash_ids[i].erasesize; + mtd->oobblock = nand_flash_ids[i].pagesize; + mtd->oobsize = mtd->oobblock / 32; + busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16; + } + + /* Check, if buswidth is correct. Hardware drivers should set + * this correct ! */ + if (busw != (this->options & NAND_BUSWIDTH_16)) { + printk (KERN_INFO "NAND device: Manufacturer ID:" + " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id, + nand_manuf_ids[i].name , mtd->name); + printk (KERN_WARNING + "NAND bus width %d instead %d bit\n", + (this->options & NAND_BUSWIDTH_16) ? 16 : 8, + busw ? 16 : 8); + this->select_chip(mtd, -1); + return 1; + } + + /* Calculate the address shift from the page size */ + this->page_shift = ffs(mtd->oobblock) - 1; + this->bbt_erase_shift = this->phys_erase_shift = ffs(mtd->erasesize) - 1; + this->chip_shift = ffs(this->chipsize) - 1; + + /* Set the bad block position */ + this->badblockpos = mtd->oobblock > 512 ? + NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS; + + /* Get chip options, preserve non chip based options */ + this->options &= ~NAND_CHIPOPTIONS_MSK; + this->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK; + /* Set this as a default. Board drivers can override it, if neccecary */ + this->options |= NAND_NO_AUTOINCR; + /* Check if this is a not a samsung device. Do not clear the options + * for chips which are not having an extended id. + */ + if (nand_maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize) + this->options &= ~NAND_SAMSUNG_LP_OPTIONS; + + /* Check for AND chips with 4 page planes */ + if (this->options & NAND_4PAGE_ARRAY) + this->erase_cmd = multi_erase_cmd; + else + this->erase_cmd = single_erase_cmd; + + /* Do not replace user supplied command function ! */ + if (mtd->oobblock > 512 && this->cmdfunc == nand_command) + this->cmdfunc = nand_command_lp; + + /* Try to identify manufacturer */ + for (j = 0; nand_manuf_ids[j].id != 0x0; j++) { + if (nand_manuf_ids[j].id == nand_maf_id) + break; + } + break; + } + + if (!nand_flash_ids[i].name) { + printk (KERN_WARNING "No NAND device found!!!\n"); + this->select_chip(mtd, -1); + return 1; + } + + for (i=1; i < maxchips; i++) { + this->select_chip(mtd, i); + + /* + * Reset the chip, required by some chips + * (e.g. Micron MT29FxGxxxxx) after power-up + */ + this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* Send the command for reading device ID */ + this->cmdfunc (mtd, NAND_CMD_READID, 0x00, -1); + + /* Read manufacturer and device IDs */ + if (nand_maf_id != this->read_byte(mtd) || + nand_dev_id != this->read_byte(mtd)) + break; + } + if (i > 1) + printk(KERN_INFO "%d NAND chips detected\n", i); + + /* Allocate buffers, if neccecary */ + if (!this->oob_buf) { + size_t len; + len = mtd->oobsize << (this->phys_erase_shift - this->page_shift); + this->oob_buf = kmalloc (len, GFP_KERNEL); + if (!this->oob_buf) { + printk (KERN_ERR "nand_scan(): Cannot allocate oob_buf\n"); + return -ENOMEM; + } + this->options |= NAND_OOBBUF_ALLOC; + } + + if (!this->data_buf) { + size_t len; + len = mtd->oobblock + mtd->oobsize; + this->data_buf = kmalloc (len, GFP_KERNEL); + if (!this->data_buf) { + if (this->options & NAND_OOBBUF_ALLOC) + kfree (this->oob_buf); + printk (KERN_ERR "nand_scan(): Cannot allocate data_buf\n"); + return -ENOMEM; + } + this->options |= NAND_DATABUF_ALLOC; + } + + /* Store the number of chips and calc total size for mtd */ + this->numchips = i; + mtd->size = i * this->chipsize; + /* Convert chipsize to number of pages per chip -1. */ + this->pagemask = (this->chipsize >> this->page_shift) - 1; + /* Preset the internal oob buffer */ + memset(this->oob_buf, 0xff, mtd->oobsize << (this->phys_erase_shift - this->page_shift)); + + /* If no default placement scheme is given, select an + * appropriate one */ + if (!this->autooob) { + /* Select the appropriate default oob placement scheme for + * placement agnostic filesystems */ + switch (mtd->oobsize) { + case 8: + this->autooob = &nand_oob_8; + break; + case 16: + this->autooob = &nand_oob_16; + break; + case 64: + this->autooob = &nand_oob_64; + break; + default: + printk (KERN_WARNING "No oob scheme defined for oobsize %d\n", + mtd->oobsize); +/* BUG(); */ + } + } + + /* The number of bytes available for the filesystem to place fs dependend + * oob data */ + if (this->options & NAND_BUSWIDTH_16) { + mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2); + if (this->autooob->eccbytes & 0x01) + mtd->oobavail--; + } else + mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1); + + /* + * check ECC mode, default to software + * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize + * fallback to software ECC + */ + if (512 != this->eccsize) + this->eccsize = 256; /* set default eccsize */ + this->eccbytes = 3; + + switch (this->eccmode) { + case NAND_ECC_HW12_2048: + if (mtd->oobblock < 2048) { + printk(KERN_WARNING "2048 byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", + mtd->oobblock); + this->eccmode = NAND_ECC_SOFT; + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + } else + this->eccsize = 2048; + break; + + case NAND_ECC_HW3_512: + case NAND_ECC_HW6_512: + case NAND_ECC_HW8_512: + if (mtd->oobblock == 256) { + printk (KERN_WARNING "512 byte HW ECC not possible on 256 Byte pagesize, fallback to SW ECC \n"); + this->eccmode = NAND_ECC_SOFT; + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + } else + this->eccsize = 512; /* set eccsize to 512 */ + break; + + case NAND_ECC_HW3_256: + break; + + case NAND_ECC_NONE: + printk (KERN_WARNING "NAND_ECC_NONE selected by board driver. This is not recommended !!\n"); + this->eccmode = NAND_ECC_NONE; + break; + + case NAND_ECC_SOFT: + this->calculate_ecc = nand_calculate_ecc; + this->correct_data = nand_correct_data; + break; + + default: + printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode); +/* BUG(); */ + } + + /* Check hardware ecc function availability and adjust number of ecc bytes per + * calculation step + */ + switch (this->eccmode) { + case NAND_ECC_HW12_2048: + this->eccbytes += 4; + case NAND_ECC_HW8_512: + this->eccbytes += 2; + case NAND_ECC_HW6_512: + this->eccbytes += 3; + case NAND_ECC_HW3_512: + case NAND_ECC_HW3_256: + if (this->calculate_ecc && this->correct_data && this->enable_hwecc) + break; + printk (KERN_WARNING "No ECC functions supplied, Hardware ECC not possible\n"); +/* BUG(); */ + } + + mtd->eccsize = this->eccsize; + + /* Set the number of read / write steps for one page to ensure ECC generation */ + switch (this->eccmode) { + case NAND_ECC_HW12_2048: + this->eccsteps = mtd->oobblock / 2048; + break; + case NAND_ECC_HW3_512: + case NAND_ECC_HW6_512: + case NAND_ECC_HW8_512: + this->eccsteps = mtd->oobblock / 512; + break; + case NAND_ECC_HW3_256: + case NAND_ECC_SOFT: + this->eccsteps = mtd->oobblock / this->eccsize; + break; + + case NAND_ECC_NONE: + this->eccsteps = 1; + break; + } + +/* XXX U-BOOT XXX */ +#if 0 + /* Initialize state, waitqueue and spinlock */ + this->state = FL_READY; + init_waitqueue_head (&this->wq); + spin_lock_init (&this->chip_lock); +#endif + + /* De-select the device */ + this->select_chip(mtd, -1); + + /* Invalidate the pagebuffer reference */ + this->pagebuf = -1; + + /* Fill in remaining MTD driver data */ + mtd->type = MTD_NANDFLASH; + mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC; + mtd->ecctype = MTD_ECC_SW; + mtd->erase = nand_erase; + mtd->point = NULL; + mtd->unpoint = NULL; + mtd->read = nand_read; + mtd->write = nand_write; + mtd->read_ecc = nand_read_ecc; + mtd->write_ecc = nand_write_ecc; + mtd->read_oob = nand_read_oob; + mtd->write_oob = nand_write_oob; +/* XXX U-BOOT XXX */ +#if 0 + mtd->readv = NULL; + mtd->writev = nand_writev; + mtd->writev_ecc = nand_writev_ecc; +#endif + mtd->sync = nand_sync; +/* XXX U-BOOT XXX */ +#if 0 + mtd->lock = NULL; + mtd->unlock = NULL; + mtd->suspend = NULL; + mtd->resume = NULL; +#endif + mtd->block_isbad = nand_block_isbad; + mtd->block_markbad = nand_block_markbad; + + /* and make the autooob the default one */ + memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo)); +/* XXX U-BOOT XXX */ +#if 0 + mtd->owner = THIS_MODULE; +#endif + /* Build bad block table */ + return this->scan_bbt (mtd); +} + +/** + * nand_release - [NAND Interface] Free resources held by the NAND device + * @mtd: MTD device structure + */ +void nand_release (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + +#ifdef CONFIG_MTD_PARTITIONS + /* Deregister partitions */ + del_mtd_partitions (mtd); +#endif + /* Deregister the device */ +/* XXX U-BOOT XXX */ +#if 0 + del_mtd_device (mtd); +#endif + /* Free bad block table memory, if allocated */ + if (this->bbt) + kfree (this->bbt); + /* Buffer allocated by nand_scan ? */ + if (this->options & NAND_OOBBUF_ALLOC) + kfree (this->oob_buf); + /* Buffer allocated by nand_scan ? */ + if (this->options & NAND_DATABUF_ALLOC) + kfree (this->data_buf); +} + +#endif diff --git a/drivers/nand/nand_bbt.c b/drivers/nand/nand_bbt.c new file mode 100644 index 000000000..aaa9400e5 --- /dev/null +++ b/drivers/nand/nand_bbt.c @@ -0,0 +1,1052 @@ +/* + * drivers/mtd/nand_bbt.c + * + * Overview: + * Bad block table support for the NAND driver + * + * Copyright (C) 2004 Thomas Gleixner (tglx@linutronix.de) + * + * $Id: nand_bbt.c,v 1.28 2004/11/13 10:19:09 gleixner Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Description: + * + * When nand_scan_bbt is called, then it tries to find the bad block table + * depending on the options in the bbt descriptor(s). If a bbt is found + * then the contents are read and the memory based bbt is created. If a + * mirrored bbt is selected then the mirror is searched too and the + * versions are compared. If the mirror has a greater version number + * than the mirror bbt is used to build the memory based bbt. + * If the tables are not versioned, then we "or" the bad block information. + * If one of the bbt's is out of date or does not exist it is (re)created. + * If no bbt exists at all then the device is scanned for factory marked + * good / bad blocks and the bad block tables are created. + * + * For manufacturer created bbts like the one found on M-SYS DOC devices + * the bbt is searched and read but never created + * + * The autogenerated bad block table is located in the last good blocks + * of the device. The table is mirrored, so it can be updated eventually. + * The table is marked in the oob area with an ident pattern and a version + * number which indicates which of both tables is more up to date. + * + * The table uses 2 bits per block + * 11b: block is good + * 00b: block is factory marked bad + * 01b, 10b: block is marked bad due to wear + * + * The memory bad block table uses the following scheme: + * 00b: block is good + * 01b: block is marked bad due to wear + * 10b: block is reserved (to protect the bbt area) + * 11b: block is factory marked bad + * + * Multichip devices like DOC store the bad block info per floor. + * + * Following assumptions are made: + * - bbts start at a page boundary, if autolocated on a block boundary + * - the space neccecary for a bbt in FLASH does not exceed a block boundary + * + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +#include +#include +#include + +#include + +/** + * check_pattern - [GENERIC] check if a pattern is in the buffer + * @buf: the buffer to search + * @len: the length of buffer to search + * @paglen: the pagelength + * @td: search pattern descriptor + * + * Check for a pattern at the given place. Used to search bad block + * tables and good / bad block identifiers. + * If the SCAN_EMPTY option is set then check, if all bytes except the + * pattern area contain 0xff + * +*/ +static int check_pattern (uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td) +{ + int i, end; + uint8_t *p = buf; + + end = paglen + td->offs; + if (td->options & NAND_BBT_SCANEMPTY) { + for (i = 0; i < end; i++) { + if (p[i] != 0xff) + return -1; + } + } + p += end; + + /* Compare the pattern */ + for (i = 0; i < td->len; i++) { + if (p[i] != td->pattern[i]) + return -1; + } + + p += td->len; + end += td->len; + if (td->options & NAND_BBT_SCANEMPTY) { + for (i = end; i < len; i++) { + if (*p++ != 0xff) + return -1; + } + } + return 0; +} + +/** + * read_bbt - [GENERIC] Read the bad block table starting from page + * @mtd: MTD device structure + * @buf: temporary buffer + * @page: the starting page + * @num: the number of bbt descriptors to read + * @bits: number of bits per block + * @offs: offset in the memory table + * @reserved_block_code: Pattern to identify reserved blocks + * + * Read the bad block table starting from page. + * + */ +static int read_bbt (struct mtd_info *mtd, uint8_t *buf, int page, int num, + int bits, int offs, int reserved_block_code) +{ + int res, i, j, act = 0; + struct nand_chip *this = mtd->priv; + size_t retlen, len, totlen; + loff_t from; + uint8_t msk = (uint8_t) ((1 << bits) - 1); + + totlen = (num * bits) >> 3; + from = ((loff_t)page) << this->page_shift; + + while (totlen) { + len = min (totlen, (size_t) (1 << this->bbt_erase_shift)); + res = mtd->read_ecc (mtd, from, len, &retlen, buf, NULL, this->autooob); + if (res < 0) { + if (retlen != len) { + printk (KERN_INFO "nand_bbt: Error reading bad block table\n"); + return res; + } + printk (KERN_WARNING "nand_bbt: ECC error while reading bad block table\n"); + } + + /* Analyse data */ + for (i = 0; i < len; i++) { + uint8_t dat = buf[i]; + for (j = 0; j < 8; j += bits, act += 2) { + uint8_t tmp = (dat >> j) & msk; + if (tmp == msk) + continue; + if (reserved_block_code && + (tmp == reserved_block_code)) { + printk (KERN_DEBUG "nand_read_bbt: Reserved block at 0x%08x\n", + ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06); + continue; + } + /* Leave it for now, if its matured we can move this + * message to MTD_DEBUG_LEVEL0 */ + printk (KERN_DEBUG "nand_read_bbt: Bad block at 0x%08x\n", + ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + /* Factory marked bad or worn out ? */ + if (tmp == 0) + this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); + else + this->bbt[offs + (act >> 3)] |= 0x1 << (act & 0x06); + } + } + totlen -= len; + from += len; + } + return 0; +} + +/** + * read_abs_bbt - [GENERIC] Read the bad block table starting at a given page + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @chip: read the table for a specific chip, -1 read all chips. + * Applies only if NAND_BBT_PERCHIP option is set + * + * Read the bad block table for all chips starting at a given page + * We assume that the bbt bits are in consecutive order. +*/ +static int read_abs_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip) +{ + struct nand_chip *this = mtd->priv; + int res = 0, i; + int bits; + + bits = td->options & NAND_BBT_NRBITS_MSK; + if (td->options & NAND_BBT_PERCHIP) { + int offs = 0; + for (i = 0; i < this->numchips; i++) { + if (chip == -1 || chip == i) + res = read_bbt (mtd, buf, td->pages[i], this->chipsize >> this->bbt_erase_shift, bits, offs, td->reserved_block_code); + if (res) + return res; + offs += this->chipsize >> (this->bbt_erase_shift + 2); + } + } else { + res = read_bbt (mtd, buf, td->pages[0], mtd->size >> this->bbt_erase_shift, bits, 0, td->reserved_block_code); + if (res) + return res; + } + return 0; +} + +/** + * read_abs_bbts - [GENERIC] Read the bad block table(s) for all chips starting at a given page + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @md: descriptor for the bad block table mirror + * + * Read the bad block table(s) for all chips starting at a given page + * We assume that the bbt bits are in consecutive order. + * +*/ +static int read_abs_bbts (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, + struct nand_bbt_descr *md) +{ + struct nand_chip *this = mtd->priv; + + /* Read the primary version, if available */ + if (td->options & NAND_BBT_VERSION) { + nand_read_raw (mtd, buf, td->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize); + td->version[0] = buf[mtd->oobblock + td->veroffs]; + printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", td->pages[0], td->version[0]); + } + + /* Read the mirror version, if available */ + if (md && (md->options & NAND_BBT_VERSION)) { + nand_read_raw (mtd, buf, md->pages[0] << this->page_shift, mtd->oobblock, mtd->oobsize); + md->version[0] = buf[mtd->oobblock + md->veroffs]; + printk (KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]); + } + + return 1; +} + +/** + * create_bbt - [GENERIC] Create a bad block table by scanning the device + * @mtd: MTD device structure + * @buf: temporary buffer + * @bd: descriptor for the good/bad block search pattern + * @chip: create the table for a specific chip, -1 read all chips. + * Applies only if NAND_BBT_PERCHIP option is set + * + * Create a bad block table by scanning the device + * for the given good/bad block identify pattern + */ +static void create_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip) +{ + struct nand_chip *this = mtd->priv; + int i, j, numblocks, len, scanlen; + int startblock; + loff_t from; + size_t readlen, ooblen; + + if (bd->options & NAND_BBT_SCANALLPAGES) + len = 1 << (this->bbt_erase_shift - this->page_shift); + else { + if (bd->options & NAND_BBT_SCAN2NDPAGE) + len = 2; + else + len = 1; + } + scanlen = mtd->oobblock + mtd->oobsize; + readlen = len * mtd->oobblock; + ooblen = len * mtd->oobsize; + + if (chip == -1) { + /* Note that numblocks is 2 * (real numblocks) here, see i+=2 below as it + * makes shifting and masking less painful */ + numblocks = mtd->size >> (this->bbt_erase_shift - 1); + startblock = 0; + from = 0; + } else { + if (chip >= this->numchips) { + printk (KERN_WARNING "create_bbt(): chipnr (%d) > available chips (%d)\n", + chip + 1, this->numchips); + return; + } + numblocks = this->chipsize >> (this->bbt_erase_shift - 1); + startblock = chip * numblocks; + numblocks += startblock; + from = startblock << (this->bbt_erase_shift - 1); + } + + for (i = startblock; i < numblocks;) { + nand_read_raw (mtd, buf, from, readlen, ooblen); + for (j = 0; j < len; j++) { + if (check_pattern (&buf[j * scanlen], scanlen, mtd->oobblock, bd)) { + this->bbt[i >> 3] |= 0x03 << (i & 0x6); + break; + } + } + i += 2; + from += (1 << this->bbt_erase_shift); + } +} + +/** + * search_bbt - [GENERIC] scan the device for a specific bad block table + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * + * Read the bad block table by searching for a given ident pattern. + * Search is preformed either from the beginning up or from the end of + * the device downwards. The search starts always at the start of a + * block. + * If the option NAND_BBT_PERCHIP is given, each chip is searched + * for a bbt, which contains the bad block information of this chip. + * This is neccecary to provide support for certain DOC devices. + * + * The bbt ident pattern resides in the oob area of the first page + * in a block. + */ +static int search_bbt (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td) +{ + struct nand_chip *this = mtd->priv; + int i, chips; + int bits, startblock, block, dir; + int scanlen = mtd->oobblock + mtd->oobsize; + int bbtblocks; + + /* Search direction top -> down ? */ + if (td->options & NAND_BBT_LASTBLOCK) { + startblock = (mtd->size >> this->bbt_erase_shift) -1; + dir = -1; + } else { + startblock = 0; + dir = 1; + } + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) { + chips = this->numchips; + bbtblocks = this->chipsize >> this->bbt_erase_shift; + startblock &= bbtblocks - 1; + } else { + chips = 1; + bbtblocks = mtd->size >> this->bbt_erase_shift; + } + + /* Number of bits for each erase block in the bbt */ + bits = td->options & NAND_BBT_NRBITS_MSK; + + for (i = 0; i < chips; i++) { + /* Reset version information */ + td->version[i] = 0; + td->pages[i] = -1; + /* Scan the maximum number of blocks */ + for (block = 0; block < td->maxblocks; block++) { + int actblock = startblock + dir * block; + /* Read first page */ + nand_read_raw (mtd, buf, actblock << this->bbt_erase_shift, mtd->oobblock, mtd->oobsize); + if (!check_pattern(buf, scanlen, mtd->oobblock, td)) { + td->pages[i] = actblock << (this->bbt_erase_shift - this->page_shift); + if (td->options & NAND_BBT_VERSION) { + td->version[i] = buf[mtd->oobblock + td->veroffs]; + } + break; + } + } + startblock += this->chipsize >> this->bbt_erase_shift; + } + /* Check, if we found a bbt for each requested chip */ + for (i = 0; i < chips; i++) { + if (td->pages[i] == -1) + printk (KERN_WARNING "Bad block table not found for chip %d\n", i); + else + printk (KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i], td->version[i]); + } + return 0; +} + +/** + * search_read_bbts - [GENERIC] scan the device for bad block table(s) + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @md: descriptor for the bad block table mirror + * + * Search and read the bad block table(s) +*/ +static int search_read_bbts (struct mtd_info *mtd, uint8_t *buf, + struct nand_bbt_descr *td, struct nand_bbt_descr *md) +{ + /* Search the primary table */ + search_bbt (mtd, buf, td); + + /* Search the mirror table */ + if (md) + search_bbt (mtd, buf, md); + + /* Force result check */ + return 1; +} + + +/** + * write_bbt - [GENERIC] (Re)write the bad block table + * + * @mtd: MTD device structure + * @buf: temporary buffer + * @td: descriptor for the bad block table + * @md: descriptor for the bad block table mirror + * @chipsel: selector for a specific chip, -1 for all + * + * (Re)write the bad block table + * +*/ +static int write_bbt (struct mtd_info *mtd, uint8_t *buf, + struct nand_bbt_descr *td, struct nand_bbt_descr *md, int chipsel) +{ + struct nand_chip *this = mtd->priv; + struct nand_oobinfo oobinfo; + struct erase_info einfo; + int i, j, res, chip = 0; + int bits, startblock, dir, page, offs, numblocks, sft, sftmsk; + int nrchips, bbtoffs, pageoffs; + uint8_t msk[4]; + uint8_t rcode = td->reserved_block_code; + size_t retlen, len = 0; + loff_t to; + + if (!rcode) + rcode = 0xff; + /* Write bad block table per chip rather than per device ? */ + if (td->options & NAND_BBT_PERCHIP) { + numblocks = (int) (this->chipsize >> this->bbt_erase_shift); + /* Full device write or specific chip ? */ + if (chipsel == -1) { + nrchips = this->numchips; + } else { + nrchips = chipsel + 1; + chip = chipsel; + } + } else { + numblocks = (int) (mtd->size >> this->bbt_erase_shift); + nrchips = 1; + } + + /* Loop through the chips */ + for (; chip < nrchips; chip++) { + + /* There was already a version of the table, reuse the page + * This applies for absolute placement too, as we have the + * page nr. in td->pages. + */ + if (td->pages[chip] != -1) { + page = td->pages[chip]; + goto write; + } + + /* Automatic placement of the bad block table */ + /* Search direction top -> down ? */ + if (td->options & NAND_BBT_LASTBLOCK) { + startblock = numblocks * (chip + 1) - 1; + dir = -1; + } else { + startblock = chip * numblocks; + dir = 1; + } + + for (i = 0; i < td->maxblocks; i++) { + int block = startblock + dir * i; + /* Check, if the block is bad */ + switch ((this->bbt[block >> 2] >> (2 * (block & 0x03))) & 0x03) { + case 0x01: + case 0x03: + continue; + } + page = block << (this->bbt_erase_shift - this->page_shift); + /* Check, if the block is used by the mirror table */ + if (!md || md->pages[chip] != page) + goto write; + } + printk (KERN_ERR "No space left to write bad block table\n"); + return -ENOSPC; +write: + + /* Set up shift count and masks for the flash table */ + bits = td->options & NAND_BBT_NRBITS_MSK; + switch (bits) { + case 1: sft = 3; sftmsk = 0x07; msk[0] = 0x00; msk[1] = 0x01; msk[2] = ~rcode; msk[3] = 0x01; break; + case 2: sft = 2; sftmsk = 0x06; msk[0] = 0x00; msk[1] = 0x01; msk[2] = ~rcode; msk[3] = 0x03; break; + case 4: sft = 1; sftmsk = 0x04; msk[0] = 0x00; msk[1] = 0x0C; msk[2] = ~rcode; msk[3] = 0x0f; break; + case 8: sft = 0; sftmsk = 0x00; msk[0] = 0x00; msk[1] = 0x0F; msk[2] = ~rcode; msk[3] = 0xff; break; + default: return -EINVAL; + } + + bbtoffs = chip * (numblocks >> 2); + + to = ((loff_t) page) << this->page_shift; + + memcpy (&oobinfo, this->autooob, sizeof(oobinfo)); + oobinfo.useecc = MTD_NANDECC_PLACEONLY; + + /* Must we save the block contents ? */ + if (td->options & NAND_BBT_SAVECONTENT) { + /* Make it block aligned */ + to &= ~((loff_t) ((1 << this->bbt_erase_shift) - 1)); + len = 1 << this->bbt_erase_shift; + res = mtd->read_ecc (mtd, to, len, &retlen, buf, &buf[len], &oobinfo); + if (res < 0) { + if (retlen != len) { + printk (KERN_INFO "nand_bbt: Error reading block for writing the bad block table\n"); + return res; + } + printk (KERN_WARNING "nand_bbt: ECC error while reading block for writing bad block table\n"); + } + /* Calc the byte offset in the buffer */ + pageoffs = page - (int)(to >> this->page_shift); + offs = pageoffs << this->page_shift; + /* Preset the bbt area with 0xff */ + memset (&buf[offs], 0xff, (size_t)(numblocks >> sft)); + /* Preset the bbt's oob area with 0xff */ + memset (&buf[len + pageoffs * mtd->oobsize], 0xff, + ((len >> this->page_shift) - pageoffs) * mtd->oobsize); + if (td->options & NAND_BBT_VERSION) { + buf[len + (pageoffs * mtd->oobsize) + td->veroffs] = td->version[chip]; + } + } else { + /* Calc length */ + len = (size_t) (numblocks >> sft); + /* Make it page aligned ! */ + len = (len + (mtd->oobblock-1)) & ~(mtd->oobblock-1); + /* Preset the buffer with 0xff */ + memset (buf, 0xff, len + (len >> this->page_shift) * mtd->oobsize); + offs = 0; + /* Pattern is located in oob area of first page */ + memcpy (&buf[len + td->offs], td->pattern, td->len); + if (td->options & NAND_BBT_VERSION) { + buf[len + td->veroffs] = td->version[chip]; + } + } + + /* walk through the memory table */ + for (i = 0; i < numblocks; ) { + uint8_t dat; + dat = this->bbt[bbtoffs + (i >> 2)]; + for (j = 0; j < 4; j++ , i++) { + int sftcnt = (i << (3 - sft)) & sftmsk; + /* Do not store the reserved bbt blocks ! */ + buf[offs + (i >> sft)] &= ~(msk[dat & 0x03] << sftcnt); + dat >>= 2; + } + } + + memset (&einfo, 0, sizeof (einfo)); + einfo.mtd = mtd; + einfo.addr = (unsigned long) to; + einfo.len = 1 << this->bbt_erase_shift; + res = nand_erase_nand (mtd, &einfo, 1); + if (res < 0) { + printk (KERN_WARNING "nand_bbt: Error during block erase: %d\n", res); + return res; + } + + res = mtd->write_ecc (mtd, to, len, &retlen, buf, &buf[len], &oobinfo); + if (res < 0) { + printk (KERN_WARNING "nand_bbt: Error while writing bad block table %d\n", res); + return res; + } + printk (KERN_DEBUG "Bad block table written to 0x%08x, version 0x%02X\n", + (unsigned int) to, td->version[chip]); + + /* Mark it as used */ + td->pages[chip] = page; + } + return 0; +} + +/** + * nand_memory_bbt - [GENERIC] create a memory based bad block table + * @mtd: MTD device structure + * @bd: descriptor for the good/bad block search pattern + * + * The function creates a memory based bbt by scanning the device + * for manufacturer / software marked good / bad blocks +*/ +static int nand_memory_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd) +{ + struct nand_chip *this = mtd->priv; + + /* Ensure that we only scan for the pattern and nothing else */ + bd->options = 0; + create_bbt (mtd, this->data_buf, bd, -1); + return 0; +} + +/** + * check_create - [GENERIC] create and write bbt(s) if neccecary + * @mtd: MTD device structure + * @buf: temporary buffer + * @bd: descriptor for the good/bad block search pattern + * + * The function checks the results of the previous call to read_bbt + * and creates / updates the bbt(s) if neccecary + * Creation is neccecary if no bbt was found for the chip/device + * Update is neccecary if one of the tables is missing or the + * version nr. of one table is less than the other +*/ +static int check_create (struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd) +{ + int i, chips, writeops, chipsel, res; + struct nand_chip *this = mtd->priv; + struct nand_bbt_descr *td = this->bbt_td; + struct nand_bbt_descr *md = this->bbt_md; + struct nand_bbt_descr *rd, *rd2; + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) + chips = this->numchips; + else + chips = 1; + + for (i = 0; i < chips; i++) { + writeops = 0; + rd = NULL; + rd2 = NULL; + /* Per chip or per device ? */ + chipsel = (td->options & NAND_BBT_PERCHIP) ? i : -1; + /* Mirrored table avilable ? */ + if (md) { + if (td->pages[i] == -1 && md->pages[i] == -1) { + writeops = 0x03; + goto create; + } + + if (td->pages[i] == -1) { + rd = md; + td->version[i] = md->version[i]; + writeops = 1; + goto writecheck; + } + + if (md->pages[i] == -1) { + rd = td; + md->version[i] = td->version[i]; + writeops = 2; + goto writecheck; + } + + if (td->version[i] == md->version[i]) { + rd = td; + if (!(td->options & NAND_BBT_VERSION)) + rd2 = md; + goto writecheck; + } + + if (((int8_t) (td->version[i] - md->version[i])) > 0) { + rd = td; + md->version[i] = td->version[i]; + writeops = 2; + } else { + rd = md; + td->version[i] = md->version[i]; + writeops = 1; + } + + goto writecheck; + + } else { + if (td->pages[i] == -1) { + writeops = 0x01; + goto create; + } + rd = td; + goto writecheck; + } +create: + /* Create the bad block table by scanning the device ? */ + if (!(td->options & NAND_BBT_CREATE)) + continue; + + /* Create the table in memory by scanning the chip(s) */ + create_bbt (mtd, buf, bd, chipsel); + + td->version[i] = 1; + if (md) + md->version[i] = 1; +writecheck: + /* read back first ? */ + if (rd) + read_abs_bbt (mtd, buf, rd, chipsel); + /* If they weren't versioned, read both. */ + if (rd2) + read_abs_bbt (mtd, buf, rd2, chipsel); + + /* Write the bad block table to the device ? */ + if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, td, md, chipsel); + if (res < 0) + return res; + } + + /* Write the mirror bad block table to the device ? */ + if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, md, td, chipsel); + if (res < 0) + return res; + } + } + return 0; +} + +/** + * mark_bbt_regions - [GENERIC] mark the bad block table regions + * @mtd: MTD device structure + * @td: bad block table descriptor + * + * The bad block table regions are marked as "bad" to prevent + * accidental erasures / writes. The regions are identified by + * the mark 0x02. +*/ +static void mark_bbt_region (struct mtd_info *mtd, struct nand_bbt_descr *td) +{ + struct nand_chip *this = mtd->priv; + int i, j, chips, block, nrblocks, update; + uint8_t oldval, newval; + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) { + chips = this->numchips; + nrblocks = (int)(this->chipsize >> this->bbt_erase_shift); + } else { + chips = 1; + nrblocks = (int)(mtd->size >> this->bbt_erase_shift); + } + + for (i = 0; i < chips; i++) { + if ((td->options & NAND_BBT_ABSPAGE) || + !(td->options & NAND_BBT_WRITE)) { + if (td->pages[i] == -1) continue; + block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift); + block <<= 1; + oldval = this->bbt[(block >> 3)]; + newval = oldval | (0x2 << (block & 0x06)); + this->bbt[(block >> 3)] = newval; + if ((oldval != newval) && td->reserved_block_code) + nand_update_bbt(mtd, block << (this->bbt_erase_shift - 1)); + continue; + } + update = 0; + if (td->options & NAND_BBT_LASTBLOCK) + block = ((i + 1) * nrblocks) - td->maxblocks; + else + block = i * nrblocks; + block <<= 1; + for (j = 0; j < td->maxblocks; j++) { + oldval = this->bbt[(block >> 3)]; + newval = oldval | (0x2 << (block & 0x06)); + this->bbt[(block >> 3)] = newval; + if (oldval != newval) update = 1; + block += 2; + } + /* If we want reserved blocks to be recorded to flash, and some + new ones have been marked, then we need to update the stored + bbts. This should only happen once. */ + if (update && td->reserved_block_code) + nand_update_bbt(mtd, (block - 2) << (this->bbt_erase_shift - 1)); + } +} + +/** + * nand_scan_bbt - [NAND Interface] scan, find, read and maybe create bad block table(s) + * @mtd: MTD device structure + * @bd: descriptor for the good/bad block search pattern + * + * The function checks, if a bad block table(s) is/are already + * available. If not it scans the device for manufacturer + * marked good / bad blocks and writes the bad block table(s) to + * the selected place. + * + * The bad block table memory is allocated here. It must be freed + * by calling the nand_free_bbt function. + * +*/ +int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd) +{ + struct nand_chip *this = mtd->priv; + int len, res = 0; + uint8_t *buf; + struct nand_bbt_descr *td = this->bbt_td; + struct nand_bbt_descr *md = this->bbt_md; + + len = mtd->size >> (this->bbt_erase_shift + 2); + /* Allocate memory (2bit per block) */ + this->bbt = kmalloc (len, GFP_KERNEL); + if (!this->bbt) { + printk (KERN_ERR "nand_scan_bbt: Out of memory\n"); + return -ENOMEM; + } + /* Clear the memory bad block table */ + memset (this->bbt, 0x00, len); + + /* If no primary table decriptor is given, scan the device + * to build a memory based bad block table + */ + if (!td) + return nand_memory_bbt(mtd, bd); + + /* Allocate a temporary buffer for one eraseblock incl. oob */ + len = (1 << this->bbt_erase_shift); + len += (len >> this->page_shift) * mtd->oobsize; + buf = kmalloc (len, GFP_KERNEL); + if (!buf) { + printk (KERN_ERR "nand_bbt: Out of memory\n"); + kfree (this->bbt); + this->bbt = NULL; + return -ENOMEM; + } + + /* Is the bbt at a given page ? */ + if (td->options & NAND_BBT_ABSPAGE) { + res = read_abs_bbts (mtd, buf, td, md); + } else { + /* Search the bad block table using a pattern in oob */ + res = search_read_bbts (mtd, buf, td, md); + } + + if (res) + res = check_create (mtd, buf, bd); + + /* Prevent the bbt regions from erasing / writing */ + mark_bbt_region (mtd, td); + if (md) + mark_bbt_region (mtd, md); + + kfree (buf); + return res; +} + + +/** + * nand_update_bbt - [NAND Interface] update bad block table(s) + * @mtd: MTD device structure + * @offs: the offset of the newly marked block + * + * The function updates the bad block table(s) +*/ +int nand_update_bbt (struct mtd_info *mtd, loff_t offs) +{ + struct nand_chip *this = mtd->priv; + int len, res = 0, writeops = 0; + int chip, chipsel; + uint8_t *buf; + struct nand_bbt_descr *td = this->bbt_td; + struct nand_bbt_descr *md = this->bbt_md; + + if (!this->bbt || !td) + return -EINVAL; + + len = mtd->size >> (this->bbt_erase_shift + 2); + /* Allocate a temporary buffer for one eraseblock incl. oob */ + len = (1 << this->bbt_erase_shift); + len += (len >> this->page_shift) * mtd->oobsize; + buf = kmalloc (len, GFP_KERNEL); + if (!buf) { + printk (KERN_ERR "nand_update_bbt: Out of memory\n"); + return -ENOMEM; + } + + writeops = md != NULL ? 0x03 : 0x01; + + /* Do we have a bbt per chip ? */ + if (td->options & NAND_BBT_PERCHIP) { + chip = (int) (offs >> this->chip_shift); + chipsel = chip; + } else { + chip = 0; + chipsel = -1; + } + + td->version[chip]++; + if (md) + md->version[chip]++; + + /* Write the bad block table to the device ? */ + if ((writeops & 0x01) && (td->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, td, md, chipsel); + if (res < 0) + goto out; + } + /* Write the mirror bad block table to the device ? */ + if ((writeops & 0x02) && md && (md->options & NAND_BBT_WRITE)) { + res = write_bbt (mtd, buf, md, td, chipsel); + } + +out: + kfree (buf); + return res; +} + +/* Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks + * + * The memory based patterns just + */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr smallpage_memorybased = { + .options = 0, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr smallpage_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 5, + .len = 1, + .pattern = scan_ff_pattern +}; + +static struct nand_bbt_descr largepage_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern +}; + +static uint8_t scan_agand_pattern[] = { 0x1C, 0x71, 0xC7, 0x1C, 0x71, 0xC7 }; + +static struct nand_bbt_descr agand_flashbased = { + .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .offs = 0x20, + .len = 6, + .pattern = scan_agand_pattern +}; + +/* Generic flash bbt decriptors +*/ +static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' }; + +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 8, + .len = 4, + .veroffs = 12, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 8, + .len = 4, + .veroffs = 12, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +/** + * nand_default_bbt - [NAND Interface] Select a default bad block table for the device + * @mtd: MTD device structure + * + * This function selects the default bad block table + * support for the device and calls the nand_scan_bbt function + * +*/ +int nand_default_bbt (struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + + /* Default for AG-AND. We must use a flash based + * bad block table as the devices have factory marked + * _good_ blocks. Erasing those blocks leads to loss + * of the good / bad information, so we _must_ store + * this information in a good / bad table during + * startup + */ + if (this->options & NAND_IS_AND) { + /* Use the default pattern descriptors */ + if (!this->bbt_td) { + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + } + this->options |= NAND_USE_FLASH_BBT; + return nand_scan_bbt (mtd, &agand_flashbased); + } + + + /* Is a flash based bad block table requested ? */ + if (this->options & NAND_USE_FLASH_BBT) { + /* Use the default pattern descriptors */ + if (!this->bbt_td) { + this->bbt_td = &bbt_main_descr; + this->bbt_md = &bbt_mirror_descr; + } + if (!this->badblock_pattern) { + this->badblock_pattern = (mtd->oobblock > 512) ? + &largepage_flashbased : &smallpage_flashbased; + } + } else { + this->bbt_td = NULL; + this->bbt_md = NULL; + if (!this->badblock_pattern) { + this->badblock_pattern = (mtd->oobblock > 512) ? + &largepage_memorybased : &smallpage_memorybased; + } + } + return nand_scan_bbt (mtd, this->badblock_pattern); +} + +/** + * nand_isbad_bbt - [NAND Interface] Check if a block is bad + * @mtd: MTD device structure + * @offs: offset in the device + * @allowbbt: allow access to bad block table region + * + */ +int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt) +{ + struct nand_chip *this = mtd->priv; + int block; + uint8_t res; + + /* Get block number * 2 */ + block = (int) (offs >> (this->bbt_erase_shift - 1)); + res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03; + + DEBUG (MTD_DEBUG_LEVEL2, "nand_isbad_bbt(): bbt info for offs 0x%08x: (block %d) 0x%02x\n", + (unsigned int)offs, res, block >> 1); + + switch ((int)res) { + case 0x00: return 0; + case 0x01: return 1; + case 0x02: return allowbbt ? 0 : 1; + } + return 1; +} + +#endif diff --git a/drivers/nand/nand_ecc_256.c b/drivers/nand/nand_ecc_256.c new file mode 100644 index 000000000..15ad45bc9 --- /dev/null +++ b/drivers/nand/nand_ecc_256.c @@ -0,0 +1,201 @@ +/* + * This file contains an ECC algorithm from Toshiba that detects and + * corrects 1 bit errors in a 256 byte block of data. + * + * drivers/mtd/nand/nand_ecc.c + * + * Copyright (C) 2000-2004 Steven J. Hill (sjhill@realitydiluted.com) + * Toshiba America Electronics Components, Inc. + * + * Copyright (C) 2006 Thomas Gleixner + * + * $Id: 0001-U-boot-NAND-Add-512-byte-SW-ECC-support.patch,v 1.1 2009-03-06 03:44:40 trix Exp $ + * + * This file is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 or (at your option) any + * later version. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this file; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * As a special exception, if other files instantiate templates or use + * macros or inline functions from these files, or you compile these + * files and link them with other works to produce a work based on these + * files, these files do not by themselves cause the resulting work to be + * covered by the GNU General Public License. However the source code for + * these files must still be made available in accordance with section (3) + * of the GNU General Public License. + * + * This exception does not invalidate any other reasons why a work based on + * this file might be covered by the GNU General Public License. + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && !(CFG_SW_ECC_512) + +#include + +/* + * Pre-calculated 256-way 1 byte column parity + */ +static const u_char nand_ecc_precalc_table[] = { + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, + 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, + 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, + 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, + 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, + 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, + 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, + 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, + 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, + 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, + 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, + 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, + 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, + 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, + 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, + 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, + 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 +}; + +/** + * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256-byte block + * @mtd: MTD block structure + * @dat: raw data + * @ecc_code: buffer for ECC + */ + + +int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) +{ + uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; + int i; + + /* Initialize variables */ + reg1 = reg2 = reg3 = 0; + + /* Build up column parity */ + for (i = 0; i < 256; i++) { + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[*dat++]; + reg1 ^= (idx & 0x3f); + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (uint8_t) i; + reg2 ^= ~((uint8_t) i); + } + } + + /* Create non-inverted ECC code from line parity */ + tmp1 = (reg3 & 0x80) >> 0; /* B7 -> B7 */ + tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */ + tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */ + tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */ + tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */ + tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */ + tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */ + tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */ + + tmp2 = (reg3 & 0x08) << 4; /* B3 -> B7 */ + tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */ + tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */ + tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */ + tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */ + tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */ + tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */ + tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */ + + /* Calculate final ECC code */ + ecc_code[0] = ~tmp1; + ecc_code[1] = ~tmp2; + ecc_code[2] = ((~reg1) << 2) | 0x03; + + return 0; +} + +static inline int countbits(uint32_t byte) +{ + int res = 0; + + for (; byte; byte >>= 1) + res += byte & 0x01; + return res; +} + +/** + * nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @mtd: MTD block structure + * @dat: raw data read from the chip + * @read_ecc: ECC from the chip + * @calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256 byte block + */ +int nand_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + uint8_t s0, s1, s2; + s0 = calc_ecc[0] ^ read_ecc[0]; + s1 = calc_ecc[1] ^ read_ecc[1]; + s2 = calc_ecc[2] ^ read_ecc[2]; + + if ((s0 | s1 | s2) == 0) + return 0; + +/* Check for a single bit error */ + if (((s0 ^ (s0 >> 1)) & 0x55) == 0x55 && + ((s1 ^ (s1 >> 1)) & 0x55) == 0x55 && + ((s2 ^ (s2 >> 1)) & 0x54) == 0x54) { + + uint32_t byteoffs, bitnum; + + byteoffs = (s1 << 0) & 0x80; + byteoffs |= (s1 << 1) & 0x40; + byteoffs |= (s1 << 2) & 0x20; + byteoffs |= (s1 << 3) & 0x10; + + byteoffs |= (s0 >> 4) & 0x08; + byteoffs |= (s0 >> 3) & 0x04; + byteoffs |= (s0 >> 2) & 0x02; + byteoffs |= (s0 >> 1) & 0x01; + + bitnum = (s2 >> 5) & 0x04; + bitnum |= (s2 >> 4) & 0x02; + bitnum |= (s2 >> 3) & 0x01; + + dat[byteoffs] ^= (1 << bitnum); + + return 1; + } + + if (countbits(s0 | ((uint32_t)s1 << 8) | ((uint32_t)s2 << 16)) == 1) + return 1; + + return -1; +} +#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ diff --git a/drivers/nand/nand_ecc_512.c b/drivers/nand/nand_ecc_512.c new file mode 100644 index 000000000..cb16b61b6 --- /dev/null +++ b/drivers/nand/nand_ecc_512.c @@ -0,0 +1,453 @@ +/* + * This file contains an ECC algorithm that detects and corrects 1 bit + * errors in a 256 byte block of data. + * + * drivers/mtd/nand/nand_ecc.c + * + * Copyright © 2008 Koninklijke Philips Electronics NV. + * Author: Frans Meulenbroeks + * + * Completely replaces the previous ECC implementation which was written by: + * Steven J. Hill (sjhill@realitydiluted.com) + * Thomas Gleixner (tglx@linutronix.de) + * + * Information on how this algorithm works and how it was developed + * can be found in Documentation/mtd/nand_ecc.txt + * + * This file is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 or (at your option) any + * later version. + * + * This file is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this file; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && (CFG_SW_ECC_512) + +#include +#include +#include +#include +#include + +/* + * invparity is a 256 byte table that contains the odd parity + * for each byte. So if the number of bits in a byte is even, + * the array element is 1, and when the number of bits is odd + * the array eleemnt is 0. + */ +static const char invparity[256] = { + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1 +}; + +/* + * bitsperbyte contains the number of bits per byte + * this is only used for testing and repairing parity + * (a precalculated value slightly improves performance) + */ +static const char bitsperbyte[256] = { + 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, + 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, +}; + +/* + * addressbits is a lookup table to filter out the bits from the xor-ed + * ecc data that identify the faulty location. + * this is only used for repairing parity + * see the comments in nand_correct_data for more details + */ +static const char addressbits[256] = { + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x01, + 0x02, 0x02, 0x03, 0x03, 0x02, 0x02, 0x03, 0x03, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x04, 0x04, 0x05, 0x05, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x08, 0x08, 0x09, 0x09, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0b, 0x0a, 0x0a, 0x0b, 0x0b, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0c, 0x0c, 0x0d, 0x0d, + 0x0e, 0x0e, 0x0f, 0x0f, 0x0e, 0x0e, 0x0f, 0x0f +}; + +/** + * nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256/512-byte + * block + * @mtd: MTD block structure + * @buf: input buffer with raw data + * @code: output buffer with ECC + */ +int nand_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf, + unsigned char *code) +{ + int i; + const uint32_t *bp = (uint32_t *)buf; + /* 256 or 512 bytes/ecc */ + const uint32_t eccsize_mult = + (((struct nand_chip *)mtd->priv)->eccsize) >> 8; + uint32_t cur; /* current value in buffer */ + /* rp0..rp15..rp17 are the various accumulated parities (per byte) */ + uint32_t rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7; + uint32_t rp8, rp9, rp10, rp11, rp12, rp13, rp14, rp15, rp16; + uint32_t rp17 = 0; + uint32_t par; /* the cumulative parity for all data */ + uint32_t tmppar; /* the cumulative parity for this iteration; + for rp12, rp14 and rp16 at the end of the + loop */ + + par = 0; + rp4 = 0; + rp6 = 0; + rp8 = 0; + rp10 = 0; + rp12 = 0; + rp14 = 0; + rp16 = 0; + + /* + * The loop is unrolled a number of times; + * This avoids if statements to decide on which rp value to update + * Also we process the data by longwords. + * Note: passing unaligned data might give a performance penalty. + * It is assumed that the buffers are aligned. + * tmppar is the cumulative sum of this iteration. + * needed for calculating rp12, rp14, rp16 and par + * also used as a performance improvement for rp6, rp8 and rp10 + */ + for (i = 0; i < eccsize_mult << 2; i++) { + cur = *bp++; + tmppar = cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= tmppar; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp8 ^= tmppar; + + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp10 ^= tmppar; + + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp6 ^= cur; + rp8 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= cur; + rp8 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp8 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp8 ^= cur; + + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp6 ^= cur; + cur = *bp++; + tmppar ^= cur; + rp4 ^= cur; + cur = *bp++; + tmppar ^= cur; + + par ^= tmppar; + if ((i & 0x1) == 0) + rp12 ^= tmppar; + if ((i & 0x2) == 0) + rp14 ^= tmppar; + if (eccsize_mult == 2 && (i & 0x4) == 0) + rp16 ^= tmppar; + } + + /* + * handle the fact that we use longword operations + * we'll bring rp4..rp14..rp16 back to single byte entities by + * shifting and xoring first fold the upper and lower 16 bits, + * then the upper and lower 8 bits. + */ + rp4 ^= (rp4 >> 16); + rp4 ^= (rp4 >> 8); + rp4 &= 0xff; + rp6 ^= (rp6 >> 16); + rp6 ^= (rp6 >> 8); + rp6 &= 0xff; + rp8 ^= (rp8 >> 16); + rp8 ^= (rp8 >> 8); + rp8 &= 0xff; + rp10 ^= (rp10 >> 16); + rp10 ^= (rp10 >> 8); + rp10 &= 0xff; + rp12 ^= (rp12 >> 16); + rp12 ^= (rp12 >> 8); + rp12 &= 0xff; + rp14 ^= (rp14 >> 16); + rp14 ^= (rp14 >> 8); + rp14 &= 0xff; + if (eccsize_mult == 2) { + rp16 ^= (rp16 >> 16); + rp16 ^= (rp16 >> 8); + rp16 &= 0xff; + } + + /* + * we also need to calculate the row parity for rp0..rp3 + * This is present in par, because par is now + * rp3 rp3 rp2 rp2 in little endian and + * rp2 rp2 rp3 rp3 in big endian + * as well as + * rp1 rp0 rp1 rp0 in little endian and + * rp0 rp1 rp0 rp1 in big endian + * First calculate rp2 and rp3 + */ +#ifdef __BIG_ENDIAN + rp2 = (par >> 16); + rp2 ^= (rp2 >> 8); + rp2 &= 0xff; + rp3 = par & 0xffff; + rp3 ^= (rp3 >> 8); + rp3 &= 0xff; +#else + rp3 = (par >> 16); + rp3 ^= (rp3 >> 8); + rp3 &= 0xff; + rp2 = par & 0xffff; + rp2 ^= (rp2 >> 8); + rp2 &= 0xff; +#endif + + /* reduce par to 16 bits then calculate rp1 and rp0 */ + par ^= (par >> 16); +#ifdef __BIG_ENDIAN + rp0 = (par >> 8) & 0xff; + rp1 = (par & 0xff); +#else + rp1 = (par >> 8) & 0xff; + rp0 = (par & 0xff); +#endif + + /* finally reduce par to 8 bits */ + par ^= (par >> 8); + par &= 0xff; + + /* + * and calculate rp5..rp15..rp17 + * note that par = rp4 ^ rp5 and due to the commutative property + * of the ^ operator we can say: + * rp5 = (par ^ rp4); + * The & 0xff seems superfluous, but benchmarking learned that + * leaving it out gives slightly worse results. No idea why, probably + * it has to do with the way the pipeline in pentium is organized. + */ + rp5 = (par ^ rp4) & 0xff; + rp7 = (par ^ rp6) & 0xff; + rp9 = (par ^ rp8) & 0xff; + rp11 = (par ^ rp10) & 0xff; + rp13 = (par ^ rp12) & 0xff; + rp15 = (par ^ rp14) & 0xff; + if (eccsize_mult == 2) + rp17 = (par ^ rp16) & 0xff; + + /* + * Finally calculate the ecc bits. + * Again here it might seem that there are performance optimisations + * possible, but benchmarks showed that on the system this is developed + * the code below is the fastest + */ + code[1] = + (invparity[rp7] << 7) | + (invparity[rp6] << 6) | + (invparity[rp5] << 5) | + (invparity[rp4] << 4) | + (invparity[rp3] << 3) | + (invparity[rp2] << 2) | + (invparity[rp1] << 1) | + (invparity[rp0]); + code[0] = + (invparity[rp15] << 7) | + (invparity[rp14] << 6) | + (invparity[rp13] << 5) | + (invparity[rp12] << 4) | + (invparity[rp11] << 3) | + (invparity[rp10] << 2) | + (invparity[rp9] << 1) | + (invparity[rp8]); + if (eccsize_mult == 1) + code[2] = + (invparity[par & 0xf0] << 7) | + (invparity[par & 0x0f] << 6) | + (invparity[par & 0xcc] << 5) | + (invparity[par & 0x33] << 4) | + (invparity[par & 0xaa] << 3) | + (invparity[par & 0x55] << 2) | + 3; + else + code[2] = + (invparity[par & 0xf0] << 7) | + (invparity[par & 0x0f] << 6) | + (invparity[par & 0xcc] << 5) | + (invparity[par & 0x33] << 4) | + (invparity[par & 0xaa] << 3) | + (invparity[par & 0x55] << 2) | + (invparity[rp17] << 1) | + (invparity[rp16] << 0); + return 0; +} + +/** + * nand_correct_data - [NAND Interface] Detect and correct bit error(s) + * @mtd: MTD block structure + * @buf: raw data read from the chip + * @read_ecc: ECC from the chip + * @calc_ecc: the ECC calculated from raw data + * + * Detect and correct a 1 bit error for 256/512 byte block + */ +int nand_correct_data(struct mtd_info *mtd, unsigned char *buf, + unsigned char *read_ecc, unsigned char *calc_ecc) +{ + unsigned char b0, b1, b2; + uint32_t byte_addr; + unsigned char bit_addr; + /* 256 or 512 bytes/ecc */ + const uint32_t eccsize_mult = + (((struct nand_chip *)mtd->priv)->eccsize) >> 8; + + /* + * b0 to b2 indicate which bit is faulty (if any) + * we might need the xor result more than once, + * so keep them in a local var + */ + b0 = read_ecc[1] ^ calc_ecc[1]; + b1 = read_ecc[0] ^ calc_ecc[0]; + b2 = read_ecc[2] ^ calc_ecc[2]; + + /* check if there are any bitfaults */ + + /* repeated if statements are slightly more efficient than switch ... */ + /* ordered in order of likelihood */ + + if ((b0 | b1 | b2) == 0) + return 0; /* no error */ + + if ((((b0 ^ (b0 >> 1)) & 0x55) == 0x55) && + (((b1 ^ (b1 >> 1)) & 0x55) == 0x55) && + ((eccsize_mult == 1 && ((b2 ^ (b2 >> 1)) & 0x54) == 0x54) || + (eccsize_mult == 2 && ((b2 ^ (b2 >> 1)) & 0x55) == 0x55))) { + /* single bit error */ + /* + * rp17/rp15/13/11/9/7/5/3/1 indicate which byte is the faulty + * byte, cp 5/3/1 indicate the faulty bit. + * A lookup table (called addressbits) is used to filter + * the bits from the byte they are in. + * A marginal optimisation is possible by having three + * different lookup tables. + * One as we have now (for b0), one for b2 + * (that would avoid the >> 1), and one for b1 (with all values + * << 4). However it was felt that introducing two more tables + * hardly justify the gain. + * + * The b2 shift is there to get rid of the lowest two bits. + * We could also do addressbits[b2] >> 1 but for the + * performace it does not make any difference + */ + if (eccsize_mult == 1) + byte_addr = (addressbits[b1] << 4) + addressbits[b0]; + else + byte_addr = (addressbits[b2 & 0x3] << 8) + + (addressbits[b1] << 4) + addressbits[b0]; + bit_addr = addressbits[b2 >> 2]; + /* flip the bit */ + buf[byte_addr] ^= (1 << bit_addr); + return 1; + + } + /* count nr of bits; use table lookup, faster than calculating it */ + if ((bitsperbyte[b0] + bitsperbyte[b1] + bitsperbyte[b2]) == 1) + return 1; /* error in ecc data; no action needed */ + + printk(KERN_ERR "uncorrectable error : "); + return -1; +} +#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c new file mode 100644 index 000000000..a2422132b --- /dev/null +++ b/drivers/nand/nand_ids.c @@ -0,0 +1,129 @@ +/* + * drivers/mtd/nandids.c + * + * Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de) + * + * $Id: nand_ids.c,v 1.10 2004/05/26 13:40:12 gleixner Exp $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include + +/* +* Chip ID list +* +* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size, +* options +* +* Pagesize; 0, 256, 512 +* 0 get this information from the extended chip ID ++ 256 256 Byte page size +* 512 512 Byte page size +*/ +struct nand_flash_dev nand_flash_ids[] = { + {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0}, + {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0}, + {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0}, + {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0}, + {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0}, + {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0}, + {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0}, + {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0}, + {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0}, + {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0}, + + {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0}, + {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0}, + {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16}, + {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16}, + + {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0}, + {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0}, + {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0}, + {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0}, + {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0}, + {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0}, + {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0}, + {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0}, + {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16}, + {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16}, + + {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0}, + + {"NAND 512MiB 3,3V 8-bit", 0xDC, 512, 512, 0x4000, 0}, + + /* These are the new chips with large page size. The pagesize + * and the erasesize is determined from the extended id bytes + */ + /* 1 Gigabit */ + {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, /* sdp3430*/ + {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 2 Gigabit */ + {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, /* lab3430 */ + {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 4 Gigabit */ + {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 8 Gigabit */ + {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* 16 Gigabit */ + {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_NO_AUTOINCR}, + {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, NAND_SAMSUNG_LP_OPTIONS | NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR}, + + /* Renesas AND 1 Gigabit. Those chips do not support extended id and have a strange page/block layout ! + * The chosen minimum erasesize is 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page planes + * 1 block = 2 pages, but due to plane arrangement the blocks 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 + * Anyway JFFS2 would increase the eraseblock size so we chose a combined one which can be erased in one go + * There are more speed improvements for reads and writes possible, but not implemented now + */ + {"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000, NAND_IS_AND | NAND_NO_AUTOINCR | NAND_4PAGE_ARRAY}, + + {NULL,} +}; + +/* +* Manufacturer ID list +*/ +struct nand_manufacturers nand_manuf_ids[] = { + {NAND_MFR_TOSHIBA, "Toshiba"}, + {NAND_MFR_SAMSUNG, "Samsung"}, + {NAND_MFR_FUJITSU, "Fujitsu"}, + {NAND_MFR_NATIONAL, "National"}, + {NAND_MFR_RENESAS, "Renesas"}, + {NAND_MFR_STMICRO, "ST Micro"}, + {NAND_MFR_MICRON, "Micron"}, + {0x0, "Unknown"} +}; +#endif diff --git a/drivers/nand/nand_util.c b/drivers/nand/nand_util.c new file mode 100644 index 000000000..62f4e5409 --- /dev/null +++ b/drivers/nand/nand_util.c @@ -0,0 +1,863 @@ +/* + * drivers/nand/nand_util.c + * + * Copyright (C) 2006 by Weiss-Electronic GmbH. + * All rights reserved. + * + * @author: Guido Classen + * @descr: NAND Flash support + * @references: borrowed heavily from Linux mtd-utils code: + * flash_eraseall.c by Arcom Control System Ltd + * nandwrite.c by Steven J. Hill (sjhill@realitydiluted.com) + * and Thomas Gleixner (tglx@linutronix.de) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) + +#include +#include +#include + +#include +#include + +typedef struct erase_info erase_info_t; +typedef struct mtd_info mtd_info_t; + +/* support only for native endian JFFS2 */ +#define cpu_to_je16(x) (x) +#define cpu_to_je32(x) (x) + +/*****************************************************************************/ +static int nand_block_bad_scrub(struct mtd_info *mtd, loff_t ofs, int getchip) +{ + return 0; +} + +/** + * nand_erase_opts: - erase NAND flash with support for various options + * (jffs2 formating) + * + * @param meminfo NAND device to erase + * @param opts options, @see struct nand_erase_options + * @return 0 in case of success + * + * This code is ported from flash_eraseall.c from Linux mtd utils by + * Arcom Control System Ltd. + */ +int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts) +{ + struct jffs2_unknown_node cleanmarker; + int clmpos = 0; + int clmlen = 8; + erase_info_t erase; + ulong erase_length; + int isNAND; + int bbtest = 1; + int result; + int percent_complete = -1; + int (*nand_block_bad_old)(struct mtd_info *, loff_t, int) = NULL; + const char *mtd_device = meminfo->name; + + memset(&erase, 0, sizeof(erase)); + + erase.mtd = meminfo; + erase.len = meminfo->erasesize; + erase.addr = opts->offset; + erase_length = opts->length; + + isNAND = meminfo->type == MTD_NANDFLASH ? 1 : 0; + + if (opts->jffs2) { + cleanmarker.magic = cpu_to_je16 (JFFS2_MAGIC_BITMASK); + cleanmarker.nodetype = cpu_to_je16 (JFFS2_NODETYPE_CLEANMARKER); + if (isNAND) { + struct nand_oobinfo *oobinfo = &meminfo->oobinfo; + + /* check for autoplacement */ + if (oobinfo->useecc == MTD_NANDECC_AUTOPLACE) { + /* get the position of the free bytes */ + if (!oobinfo->oobfree[0][1]) { + printf(" Eeep. Autoplacement selected " + "and no empty space in oob\n"); + return -1; + } + clmpos = oobinfo->oobfree[0][0]; + clmlen = oobinfo->oobfree[0][1]; + if (clmlen > 8) + clmlen = 8; + } else { + /* legacy mode */ + switch (meminfo->oobsize) { + case 8: + clmpos = 6; + clmlen = 2; + break; + case 16: + clmpos = 8; + clmlen = 8; + break; + case 64: + clmpos = 16; + clmlen = 8; + break; + } + } + + cleanmarker.totlen = cpu_to_je32(8); + } else { + cleanmarker.totlen = + cpu_to_je32(sizeof(struct jffs2_unknown_node)); + } + cleanmarker.hdr_crc = cpu_to_je32( + crc32_no_comp(0, (unsigned char *) &cleanmarker, + sizeof(struct jffs2_unknown_node) - 4)); + } + + /* scrub option allows to erase badblock. To prevent internal + * check from erase() method, set block check method to dummy + * and disable bad block table while erasing. + */ + if (opts->scrub) { + struct nand_chip *priv_nand = meminfo->priv; + + nand_block_bad_old = priv_nand->block_bad; + priv_nand->block_bad = nand_block_bad_scrub; + /* we don't need the bad block table anymore... + * after scrub, there are no bad blocks left! + */ + if (priv_nand->bbt) { + kfree(priv_nand->bbt); + } + priv_nand->bbt = NULL; + } + + for (; + erase.addr < opts->offset + erase_length; + erase.addr += meminfo->erasesize) { + + WATCHDOG_RESET (); + + if (!opts->scrub && bbtest) { + int ret = meminfo->block_isbad(meminfo, erase.addr); + if (ret > 0) { + if (!opts->quiet) + printf("\rSkipping bad block at " + "0x%08x " + " \n", + erase.addr); + continue; + + } else if (ret < 0) { + printf("\n%s: MTD get bad block failed: %d\n", + mtd_device, + ret); + return -1; + } + } + + result = meminfo->erase(meminfo, &erase); + if (result != 0) { + printf("\n%s: MTD Erase failure: %d\n", + mtd_device, result); + continue; + } + + /* format for JFFS2 ? */ + if (opts->jffs2) { + + /* write cleanmarker */ + if (isNAND) { + size_t written; + result = meminfo->write_oob(meminfo, + erase.addr + clmpos, + clmlen, + &written, + (unsigned char *) + &cleanmarker); + if (result != 0) { + printf("\n%s: MTD writeoob failure: %d\n", + mtd_device, result); + continue; + } + } else { + printf("\n%s: this erase routine only supports" + " NAND devices!\n", + mtd_device); + } + } + + if (!opts->quiet) { + unsigned long percent = ((unsigned long) + (erase.addr+meminfo->erasesize-opts->offset) + * 100 / erase_length); + + /* output progress message only at whole percent + * steps to reduce the number of messages printed + * on (slow) serial consoles + */ + if ((int)percent != percent_complete) { + percent_complete = (int)percent; + + printf("\rErasing at 0x%x -- %3d%% complete.", + erase.addr, (int)percent); + + if (opts->jffs2 && result == 0) + printf(" Cleanmarker written at 0x%x.", + erase.addr); + } + } + } + if (!opts->quiet) + printf("\n"); + + if (nand_block_bad_old) { + struct nand_chip *priv_nand = meminfo->priv; + + priv_nand->block_bad = nand_block_bad_old; + priv_nand->scan_bbt(meminfo); + } + + return 0; +} + +#define MAX_PAGE_SIZE 2048 +#define MAX_OOB_SIZE 64 + +/* + * buffer array used for writing data + */ +static unsigned char data_buf[MAX_PAGE_SIZE]; +static unsigned char oob_buf[MAX_OOB_SIZE]; + +/* OOB layouts to pass into the kernel as default */ +static struct nand_oobinfo none_oobinfo = { + .useecc = MTD_NANDECC_OFF, +}; + +static struct nand_oobinfo jffs2_oobinfo = { + .useecc = MTD_NANDECC_PLACE, + .eccbytes = 6, + .eccpos = { 0, 1, 2, 3, 6, 7 } +}; + +static struct nand_oobinfo yaffs_oobinfo = { + .useecc = MTD_NANDECC_PLACE, + .eccbytes = 6, + .eccpos = { 8, 9, 10, 13, 14, 15} +}; + +static struct nand_oobinfo autoplace_oobinfo = { + .useecc = MTD_NANDECC_AUTOPLACE +}; + +/** + * nand_write_opts: - write image to NAND flash with support for various options + * + * @param meminfo NAND device to erase + * @param opts write options (@see nand_write_options) + * @return 0 in case of success + * + * This code is ported from nandwrite.c from Linux mtd utils by + * Steven J. Hill and Thomas Gleixner. + */ +int nand_write_opts(nand_info_t *meminfo, const nand_write_options_t *opts) +{ + int imglen = 0; + int pagelen; + int baderaseblock; + int blockstart = -1; + loff_t offs; + int readlen; + int oobinfochanged = 0; + int percent_complete = -1; + struct nand_oobinfo old_oobinfo; + ulong mtdoffset = opts->offset; + ulong erasesize_blockalign; + u_char *buffer = opts->buffer; + size_t written; + int result; + + if (opts->pad && opts->writeoob) { + printf("Can't pad when oob data is present.\n"); + return -1; + } + + /* set erasesize to specified number of blocks - to match + * jffs2 (virtual) block size */ + if (opts->blockalign == 0) { + erasesize_blockalign = meminfo->erasesize; + } else { + erasesize_blockalign = meminfo->erasesize * opts->blockalign; + } + + /* make sure device page sizes are valid */ + if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512) + && !(meminfo->oobsize == 8 && meminfo->oobblock == 256) + && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) { + printf("Unknown flash (not normal NAND)\n"); + return -1; + } + + /* read the current oob info */ + memcpy(&old_oobinfo, &meminfo->oobinfo, sizeof(old_oobinfo)); + + /* write without ecc? */ + if (opts->noecc) { + memcpy(&meminfo->oobinfo, &none_oobinfo, + sizeof(meminfo->oobinfo)); + oobinfochanged = 1; + } + + /* autoplace ECC? */ + if (opts->autoplace && (old_oobinfo.useecc != MTD_NANDECC_AUTOPLACE)) { + + memcpy(&meminfo->oobinfo, &autoplace_oobinfo, + sizeof(meminfo->oobinfo)); + oobinfochanged = 1; + } + + /* force OOB layout for jffs2 or yaffs? */ + if (opts->forcejffs2 || opts->forceyaffs) { + struct nand_oobinfo *oobsel = + opts->forcejffs2 ? &jffs2_oobinfo : &yaffs_oobinfo; + + if (meminfo->oobsize == 8) { + if (opts->forceyaffs) { + printf("YAFSS cannot operate on " + "256 Byte page size\n"); + goto restoreoob; + } + /* Adjust number of ecc bytes */ + jffs2_oobinfo.eccbytes = 3; + } + + memcpy(&meminfo->oobinfo, oobsel, sizeof(meminfo->oobinfo)); + } + + /* get image length */ + imglen = opts->length; + pagelen = meminfo->oobblock + + ((opts->writeoob != 0) ? meminfo->oobsize : 0); + + /* check, if file is pagealigned */ + if ((!opts->pad) && ((imglen % pagelen) != 0)) { + printf("Input block length is not page aligned\n"); + goto restoreoob; + } + + /* check, if length fits into device */ + if (((imglen / pagelen) * meminfo->oobblock) + > (meminfo->size - opts->offset)) { + printf("Image %d bytes, NAND page %d bytes, " + "OOB area %u bytes, device size %u bytes\n", + imglen, pagelen, meminfo->oobblock, meminfo->size); + printf("Input block does not fit into device\n"); + goto restoreoob; + } + + if (!opts->quiet) + printf("\n"); + + /* get data from input and write to the device */ + while (imglen && (mtdoffset < meminfo->size)) { + + WATCHDOG_RESET (); + + /* + * new eraseblock, check for bad block(s). Stay in the + * loop to be sure if the offset changes because of + * a bad block, that the next block that will be + * written to is also checked. Thus avoiding errors if + * the block(s) after the skipped block(s) is also bad + * (number of blocks depending on the blockalign + */ + while (blockstart != (mtdoffset & (~erasesize_blockalign+1))) { + blockstart = mtdoffset & (~erasesize_blockalign+1); + offs = blockstart; + baderaseblock = 0; + + /* check all the blocks in an erase block for + * bad blocks */ + do { + int ret = meminfo->block_isbad(meminfo, offs); + + if (ret < 0) { + printf("Bad block check failed\n"); + goto restoreoob; + } + if (ret == 1) { + baderaseblock = 1; + if (!opts->quiet) + printf("\rBad block at 0x%lx " + "in erase block from " + "0x%x will be skipped\n", + (long) offs, + blockstart); + } + + if (baderaseblock) { + mtdoffset = blockstart + + erasesize_blockalign; + } + offs += erasesize_blockalign + / opts->blockalign; + } while (offs < blockstart + erasesize_blockalign); + } + + readlen = meminfo->oobblock; + if (opts->pad && (imglen < readlen)) { + readlen = imglen; + memset(data_buf + readlen, 0xff, + meminfo->oobblock - readlen); + } + + /* read page data from input memory buffer */ + memcpy(data_buf, buffer, readlen); + buffer += readlen; + + if (opts->writeoob) { + struct nand_oobinfo *oobinfo_yaffs2 = &meminfo->oobinfo; + memset(oob_buf, 0xff, meminfo->oobsize); + /* Read OOB data from input memory block. + Only copy yaffs portion. The offset and + sizes are set in the oobfree array at index + 0 and 1 respectively. + Exit on failure */ + memcpy(oob_buf+oobinfo_yaffs2->oobfree[0][0], + buffer, oobinfo_yaffs2->oobfree[0][1]); + buffer += meminfo->oobsize; + + /* write OOB data first, as ecc will be placed + * in there*/ + result = meminfo->write_oob(meminfo, + mtdoffset, + meminfo->oobsize, + &written, + (unsigned char *) + &oob_buf); + + if (result != 0) { + printf("\nMTD writeoob failure: %d\n", + result); + goto restoreoob; + } + imglen -= meminfo->oobsize; + } + + /* write out the page data */ + result = meminfo->write(meminfo, + mtdoffset, + meminfo->oobblock, + &written, + (unsigned char *) &data_buf); + + if (result != 0) { + printf("writing NAND page at offset 0x%lx failed\n", + mtdoffset); + goto restoreoob; + } + imglen -= readlen; + + if (!opts->quiet) { + unsigned long percent = ((opts->length-imglen) * 100 + / opts->length); + /* output progress message only at whole percent + * steps to reduce the number of messages printed + * on (slow) serial consoles + */ + if ((int)percent != percent_complete) { + printf("\rWriting data at 0x%x " + "-- %3d%% complete.", + mtdoffset, (int)percent); + percent_complete = (int)percent; + } + } + + mtdoffset += meminfo->oobblock; + } + + if (!opts->quiet) + printf("\n"); + +restoreoob: + if (oobinfochanged) { + memcpy(&meminfo->oobinfo, &old_oobinfo, + sizeof(meminfo->oobinfo)); + } + + if (imglen > 0) { + printf("Data did not fit into device, due to bad blocks\n"); + return -1; + } + + /* return happy */ + return 0; +} + +/** + * nand_read_opts: - read image from NAND flash with support for various options + * + * @param meminfo NAND device to erase + * @param opts read options (@see struct nand_read_options) + * @return 0 in case of success + * + */ +int nand_read_opts(nand_info_t *meminfo, const nand_read_options_t *opts) +{ + int imglen = opts->length; + int pagelen; + int baderaseblock; + int blockstart = -1; + int percent_complete = -1; + loff_t offs; + size_t readlen; + ulong mtdoffset = opts->offset; + u_char *buffer = opts->buffer; + int result; + + /* make sure device page sizes are valid */ + if (!(meminfo->oobsize == 16 && meminfo->oobblock == 512) + && !(meminfo->oobsize == 8 && meminfo->oobblock == 256) + && !(meminfo->oobsize == 64 && meminfo->oobblock == 2048)) { + printf("Unknown flash (not normal NAND)\n"); + return -1; + } + + pagelen = meminfo->oobblock + + ((opts->readoob != 0) ? meminfo->oobsize : 0); + + /* check, if length is not larger than device */ + if (((imglen / pagelen) * meminfo->oobblock) + > (meminfo->size - opts->offset)) { + printf("Image %d bytes, NAND page %d bytes, " + "OOB area %u bytes, device size %u bytes\n", + imglen, pagelen, meminfo->oobblock, meminfo->size); + printf("Input block is larger than device\n"); + return -1; + } + + if (!opts->quiet) + printf("\n"); + + /* get data from input and write to the device */ + while (imglen && (mtdoffset < meminfo->size)) { + + WATCHDOG_RESET (); + + /* + * new eraseblock, check for bad block(s). Stay in the + * loop to be sure if the offset changes because of + * a bad block, that the next block that will be + * written to is also checked. Thus avoiding errors if + * the block(s) after the skipped block(s) is also bad + * (number of blocks depending on the blockalign + */ + while (blockstart != (mtdoffset & (~meminfo->erasesize+1))) { + blockstart = mtdoffset & (~meminfo->erasesize+1); + offs = blockstart; + baderaseblock = 0; + + /* check all the blocks in an erase block for + * bad blocks */ + do { + int ret = meminfo->block_isbad(meminfo, offs); + + if (ret < 0) { + printf("Bad block check failed\n"); + return -1; + } + if (ret == 1) { + baderaseblock = 1; + if (!opts->quiet) + printf("\rBad block at 0x%lx " + "in erase block from " + "0x%x will be skipped\n", + (long) offs, + blockstart); + } + + if (baderaseblock) { + mtdoffset = blockstart + + meminfo->erasesize; + } + offs += meminfo->erasesize; + + } while (offs < blockstart + meminfo->erasesize); + } + + + /* read page data to memory buffer */ + result = meminfo->read(meminfo, + mtdoffset, + meminfo->oobblock, + &readlen, + (unsigned char *) &data_buf); + + if (result != 0) { + printf("reading NAND page at offset 0x%lx failed\n", + mtdoffset); + return -1; + } + + if (imglen < readlen) { + readlen = imglen; + } + + memcpy(buffer, data_buf, readlen); + buffer += readlen; + imglen -= readlen; + + if (opts->readoob) { + result = meminfo->read_oob(meminfo, + mtdoffset, + meminfo->oobsize, + &readlen, + (unsigned char *) + &oob_buf); + + if (result != 0) { + printf("\nMTD readoob failure: %d\n", + result); + return -1; + } + + + if (imglen < readlen) { + readlen = imglen; + } + + memcpy(buffer, oob_buf, readlen); + + buffer += readlen; + imglen -= readlen; + } + + if (!opts->quiet) { + unsigned long percent = ((opts->length-imglen) * 100 + / opts->length); + /* output progress message only at whole percent + * steps to reduce the number of messages printed + * on (slow) serial consoles + */ + if ((int)percent != percent_complete) { + if (!opts->quiet) + /*printf("\rReading data from 0x%x " + "-- %3d%% complete.", + mtdoffset, (int)percent);*/ + percent_complete = (int)percent; + } + } + + mtdoffset += meminfo->oobblock; + } + + if (!opts->quiet) + printf("\n"); + + if (imglen > 0) { + printf("Could not read entire image due to bad blocks\n"); + return -1; + } + + /* return happy */ + return 0; +} + +/****************************************************************************** + * Support for locking / unlocking operations of some NAND devices + *****************************************************************************/ + +#define NAND_CMD_LOCK 0x2a +#define NAND_CMD_LOCK_TIGHT 0x2c +#define NAND_CMD_UNLOCK1 0x23 +#define NAND_CMD_UNLOCK2 0x24 +#define NAND_CMD_LOCK_STATUS 0x7a + +/** + * nand_lock: Set all pages of NAND flash chip to the LOCK or LOCK-TIGHT + * state + * + * @param meminfo nand mtd instance + * @param tight bring device in lock tight mode + * + * @return 0 on success, -1 in case of error + * + * The lock / lock-tight command only applies to the whole chip. To get some + * parts of the chip lock and others unlocked use the following sequence: + * + * - Lock all pages of the chip using nand_lock(mtd, 0) (or the lockpre pin) + * - Call nand_unlock() once for each consecutive area to be unlocked + * - If desired: Bring the chip to the lock-tight state using nand_lock(mtd, 1) + * + * If the device is in lock-tight state software can't change the + * current active lock/unlock state of all pages. nand_lock() / nand_unlock() + * calls will fail. It is only posible to leave lock-tight state by + * an hardware signal (low pulse on _WP pin) or by power down. + */ +int nand_lock(nand_info_t *meminfo, int tight) +{ + int ret = 0; + int status; + struct nand_chip *this = meminfo->priv; + + /* select the NAND device */ + this->select_chip(meminfo, 0); + + this->cmdfunc(meminfo, + (tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK), + -1, -1); + + /* call wait ready function */ + status = this->waitfunc(meminfo, this, FL_WRITING); + + /* see if device thinks it succeeded */ + if (status & 0x01) { + ret = -1; + } + + /* de-select the NAND device */ + this->select_chip(meminfo, -1); + return ret; +} + +/** + * nand_get_lock_status: - query current lock state from one page of NAND + * flash + * + * @param meminfo nand mtd instance + * @param offset page address to query (muss be page aligned!) + * + * @return -1 in case of error + * >0 lock status: + * bitfield with the following combinations: + * NAND_LOCK_STATUS_TIGHT: page in tight state + * NAND_LOCK_STATUS_LOCK: page locked + * NAND_LOCK_STATUS_UNLOCK: page unlocked + * + */ +int nand_get_lock_status(nand_info_t *meminfo, ulong offset) +{ + int ret = 0; + int chipnr; + int page; + struct nand_chip *this = meminfo->priv; + + /* select the NAND device */ + chipnr = (int)(offset >> this->chip_shift); + this->select_chip(meminfo, chipnr); + + + if ((offset & (meminfo->oobblock - 1)) != 0) { + printf ("nand_get_lock_status: " + "Start address must be beginning of " + "nand page!\n"); + ret = -1; + goto out; + } + + /* check the Lock Status */ + page = (int)(offset >> this->page_shift); + this->cmdfunc(meminfo, NAND_CMD_LOCK_STATUS, -1, page & this->pagemask); + + ret = this->read_byte(meminfo) & (NAND_LOCK_STATUS_TIGHT + | NAND_LOCK_STATUS_LOCK + | NAND_LOCK_STATUS_UNLOCK); + + out: + /* de-select the NAND device */ + this->select_chip(meminfo, -1); + return ret; +} + #if 0 +/** + * nand_unlock: - Unlock area of NAND pages + * only one consecutive area can be unlocked at one time! + * + * @param meminfo nand mtd instance + * @param start start byte address + * @param length number of bytes to unlock (must be a multiple of + * page size nand->oobblock) + * + * @return 0 on success, -1 in case of error + */ +int nand_unlock(nand_info_t *meminfo, ulong start, ulong length) +{ + int ret = 0; + int chipnr; + int status; + int page; + struct nand_chip *this = meminfo->priv; + printf ("nand_unlock: start: %08x, length: %d!\n", + (int)start, (int)length); + + /* select the NAND device */ + chipnr = (int)(start >> this->chip_shift); + this->select_chip(meminfo, chipnr); + + /* check the WP bit */ + this->cmdfunc(meminfo, NAND_CMD_STATUS, -1, -1); + if ((this->read_byte(meminfo) & 0x80) == 0) { + printf ("nand_unlock: Device is write protected!\n"); + ret = -1; + goto out; + } + + if ((start & (meminfo->oobblock - 1)) != 0) { + printf ("nand_unlock: Start address must be beginning of " + "nand page!\n"); + ret = -1; + goto out; + } + + if (length == 0 || (length & (meminfo->oobblock - 1)) != 0) { + printf ("nand_unlock: Length must be a multiple of nand page " + "size!\n"); + ret = -1; + goto out; + } + + /* submit address of first page to unlock */ + page = (int)(start >> this->page_shift); + this->cmdfunc(meminfo, NAND_CMD_UNLOCK1, -1, page & this->pagemask); + + /* submit ADDRESS of LAST page to unlock */ + page += (int)(length >> this->page_shift) - 1; + this->cmdfunc(meminfo, NAND_CMD_UNLOCK2, -1, page & this->pagemask); + + /* call wait ready function */ + status = this->waitfunc(meminfo, this, FL_WRITING); + /* see if device thinks it succeeded */ + if (status & 0x01) { + /* there was an error */ + ret = -1; + goto out; + } + + out: + /* de-select the NAND device */ + this->select_chip(meminfo, -1); + return ret; +} + #endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) */ diff --git a/drivers/nand_legacy/Makefile b/drivers/nand_legacy/Makefile new file mode 100644 index 000000000..7e2cf6673 --- /dev/null +++ b/drivers/nand_legacy/Makefile @@ -0,0 +1,16 @@ +include $(TOPDIR)/config.mk + +LIB := libnand_legacy.a + +OBJS := nand_legacy.o +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend diff --git a/drivers/nand_legacy/nand_legacy.c b/drivers/nand_legacy/nand_legacy.c new file mode 100644 index 000000000..458046d41 --- /dev/null +++ b/drivers/nand_legacy/nand_legacy.c @@ -0,0 +1,1619 @@ +/* + * (C) 2006 Denx + * Driver for NAND support, Rick Bronson + * borrowed heavily from: + * (c) 1999 Machine Vision Holdings, Inc. + * (c) 1999, 2000 David Woodhouse + * + * Added 16-bit nand support + * (C) 2004 Texas Instruments + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) + +#include +#include +#include + +#ifdef CONFIG_OMAP1510 +void archflashwp(void *archdata, int wp); +#endif + +#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) + +#undef PSYCHO_DEBUG +#undef NAND_DEBUG + +/* ****************** WARNING ********************* + * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will + * erase (or at least attempt to erase) blocks that are marked + * bad. This can be very handy if you are _sure_ that the block + * is OK, say because you marked a good block bad to test bad + * block handling and you are done testing, or if you have + * accidentally marked blocks bad. + * + * Erasing factory marked bad blocks is a _bad_ idea. If the + * erase succeeds there is no reliable way to find them again, + * and attempting to program or erase bad blocks can affect + * the data in _other_ (good) blocks. + */ +#define ALLOW_ERASE_BAD_DEBUG 0 + +#define CONFIG_MTD_NAND_ECC /* enable ECC */ +#define CONFIG_MTD_NAND_ECC_JFFS2 + +/* bits for nand_legacy_rw() `cmd'; or together as needed */ +#define NANDRW_READ 0x01 +#define NANDRW_WRITE 0x00 +#define NANDRW_JFFS2 0x02 +#define NANDRW_JFFS2_SKIP 0x04 + + +/* + * Exported variables etc. + */ + +/* Definition of the out of band configuration structure */ +struct nand_oob_config { + /* position of ECC bytes inside oob */ + int ecc_pos[6]; + /* position of bad blk flag inside oob -1 = inactive */ + int badblock_pos; + /* position of ECC valid flag inside oob -1 = inactive */ + int eccvalid_pos; +} oob_config = { {0}, 0, 0}; + +struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}}; + +int curr_device = -1; /* Current NAND Device */ + + +/* + * Exported functionss + */ +int nand_legacy_erase(struct nand_chip* nand, size_t ofs, + size_t len, int clean); +int nand_legacy_rw(struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf); +void nand_print(struct nand_chip *nand); +void nand_print_bad(struct nand_chip *nand); +int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, u_char * buf); +int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, const u_char * buf); + +/* + * Internals + */ +static int NanD_WaitReady(struct nand_chip *nand, int ale_wait); +static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, + size_t * retlen, u_char *buf, u_char *ecc_code); +static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, + size_t * retlen, const u_char * buf, + u_char * ecc_code); +#ifdef CONFIG_MTD_NAND_ECC +static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc); +static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code); +#endif + + +/* + * + * Function definitions + * + */ + +/* returns 0 if block containing pos is OK: + * valid erase block and + * not marked bad, or no bad mark position is specified + * returns 1 if marked bad or otherwise invalid + */ +static int check_block (struct nand_chip *nand, unsigned long pos) +{ + size_t retlen; + uint8_t oob_data; + uint16_t oob_data16[6]; + int page0 = pos & (-nand->erasesize); + int page1 = page0 + nand->oobblock; + int badpos = oob_config.badblock_pos; + + if (pos >= nand->totlen) + return 1; + + if (badpos < 0) + return 0; /* no way to check, assume OK */ + + if (nand->bus16) { + if (nand_read_oob(nand, (page0 + 0), 12, &retlen, (uint8_t *)oob_data16) + || (oob_data16[2] & 0xff00) != 0xff00) + return 1; + if (nand_read_oob(nand, (page1 + 0), 12, &retlen, (uint8_t *)oob_data16) + || (oob_data16[2] & 0xff00) != 0xff00) + return 1; + } else { + /* Note - bad block marker can be on first or second page */ + if (nand_read_oob(nand, page0 + badpos, 1, &retlen, (unsigned char *)&oob_data) + || oob_data != 0xff + || nand_read_oob (nand, page1 + badpos, 1, &retlen, (unsigned char *)&oob_data) + || oob_data != 0xff) + return 1; + } + + return 0; +} + +/* print bad blocks in NAND flash */ +void nand_print_bad(struct nand_chip* nand) +{ + unsigned long pos; + + for (pos = 0; pos < nand->totlen; pos += nand->erasesize) { + if (check_block(nand, pos)) + printf(" 0x%8.8lx\n", pos); + } + puts("\n"); +} + +/* cmd: 0: NANDRW_WRITE write, fail on bad block + * 1: NANDRW_READ read, fail on bad block + * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks + * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks + * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks + */ +int nand_legacy_rw (struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf) +{ + int ret = 0, n, total = 0; + char eccbuf[6]; + /* eblk (once set) is the start of the erase block containing the + * data being processed. + */ + unsigned long eblk = ~0; /* force mismatch on first pass */ + unsigned long erasesize = nand->erasesize; + + while (len) { + if ((start & (-erasesize)) != eblk) { + /* have crossed into new erase block, deal with + * it if it is sure marked bad. + */ + eblk = start & (-erasesize); /* start of block */ + if (check_block(nand, eblk)) { + if (cmd == (NANDRW_READ | NANDRW_JFFS2)) { + while (len > 0 && + start - eblk < erasesize) { + *(buf++) = 0xff; + ++start; + ++total; + --len; + } + continue; + } else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) { + start += erasesize; + continue; + } else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) { + /* skip bad block */ + start += erasesize; + continue; + } else { + ret = 1; + break; + } + } + } + /* The ECC will not be calculated correctly if + less than 512 is written or read */ + /* Is request at least 512 bytes AND it starts on a proper boundry */ + if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200)) + printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n"); + + if (cmd & NANDRW_READ) { + ret = nand_read_ecc(nand, start, + min(len, eblk + erasesize - start), + (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); + } else { + ret = nand_write_ecc(nand, start, + min(len, eblk + erasesize - start), + (size_t *)&n, (u_char*)buf, (u_char *)eccbuf); + } + + if (ret) + break; + + start += n; + buf += n; + total += n; + len -= n; + } + if (retlen) + *retlen = total; + + return ret; +} + +void nand_print(struct nand_chip *nand) +{ + if (nand->numchips > 1) { + printf("%s at 0x%lx,\n" + "\t %d chips %s, size %d MB, \n" + "\t total size %ld MB, sector size %ld kB\n", + nand->name, nand->IO_ADDR, nand->numchips, + nand->chips_name, 1 << (nand->chipshift - 20), + nand->totlen >> 20, nand->erasesize >> 10); + } + else { + printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR); + print_size(nand->totlen, ", "); + print_size(nand->erasesize, " sector)\n"); + } +} + +/* ------------------------------------------------------------------------- */ + +static int NanD_WaitReady(struct nand_chip *nand, int ale_wait) +{ + /* This is inline, to optimise the common case, where it's ready instantly */ + int ret = 0; + +#ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */ + if(ale_wait) + NAND_WAIT_READY(nand); /* do the worst case 25us wait */ + else + udelay(10); +#else /* has functional r/b signal */ + NAND_WAIT_READY(nand); +#endif + return ret; +} + +/* NanD_Command: Send a flash command to the flash chip */ + +static inline int NanD_Command(struct nand_chip *nand, unsigned char command) +{ + unsigned long nandptr = nand->IO_ADDR; + + /* Assert the CLE (Command Latch Enable) line to the flash chip */ + NAND_CTL_SETCLE(nandptr); + + /* Send the command */ + WRITE_NAND_COMMAND(command, nandptr); + + /* Lower the CLE line */ + NAND_CTL_CLRCLE(nandptr); + +#ifdef NAND_NO_RB + if(command == NAND_CMD_RESET){ + u_char ret_val; + NanD_Command(nand, NAND_CMD_STATUS); + do { + ret_val = READ_NAND(nandptr);/* wait till ready */ + } while((ret_val & 0x40) != 0x40); + } +#endif + return NanD_WaitReady(nand, 0); +} + +/* NanD_Address: Set the current address for the flash chip */ + +static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs) +{ + unsigned long nandptr; + int i; + + nandptr = nand->IO_ADDR; + + /* Assert the ALE (Address Latch Enable) line to the flash chip */ + NAND_CTL_SETALE(nandptr); + + /* Send the address */ + /* Devices with 256-byte page are addressed as: + * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31) + * there is no device on the market with page256 + * and more than 24 bits. + * Devices with 512-byte page are addressed as: + * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31) + * 25-31 is sent only if the chip support it. + * bit 8 changes the read command to be sent + * (NAND_CMD_READ0 or NAND_CMD_READ1). + */ + + if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE) + WRITE_NAND_ADDRESS(ofs, nandptr); + + ofs = ofs >> nand->page_shift; + + if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE) { + for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8) { + WRITE_NAND_ADDRESS(ofs, nandptr); + } + } + + /* Lower the ALE line */ + NAND_CTL_CLRALE(nandptr); + + /* Wait for the chip to respond */ + return NanD_WaitReady(nand, 1); +} + +/* NanD_SelectChip: Select a given flash chip within the current floor */ + +static inline int NanD_SelectChip(struct nand_chip *nand, int chip) +{ + /* Wait for it to be ready */ + return NanD_WaitReady(nand, 0); +} + +/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */ + +static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip) +{ + int mfr, id, i; + + NAND_ENABLE_CE(nand); /* set pin low */ + /* Reset the chip */ + if (NanD_Command(nand, NAND_CMD_RESET)) { +#ifdef NAND_DEBUG + printf("NanD_Command (reset) for %d,%d returned true\n", + floor, chip); +#endif + NAND_DISABLE_CE(nand); /* set pin high */ + return 0; + } + + /* Read the NAND chip ID: 1. Send ReadID command */ + if (NanD_Command(nand, NAND_CMD_READID)) { +#ifdef NAND_DEBUG + printf("NanD_Command (ReadID) for %d,%d returned true\n", + floor, chip); +#endif + NAND_DISABLE_CE(nand); /* set pin high */ + return 0; + } + + /* Read the NAND chip ID: 2. Send address byte zero */ + NanD_Address(nand, ADDR_COLUMN, 0); + + /* Read the manufacturer and device id codes from the device */ + + mfr = READ_NAND(nand->IO_ADDR); + + id = READ_NAND(nand->IO_ADDR); + + NAND_DISABLE_CE(nand); /* set pin high */ + +#ifdef NAND_DEBUG + printf("NanD_Command (ReadID) got %x %x\n", mfr, id); +#endif + if (mfr == 0xff || mfr == 0) { + /* No response - return failure */ + return 0; + } + + /* Check it's the same as the first chip we identified. + * M-Systems say that any given nand_chip device should only + * contain _one_ type of flash part, although that's not a + * hardware restriction. */ + if (nand->mfr) { + if (nand->mfr == mfr && nand->id == id) { + return 1; /* This is another the same the first */ + } else { + printf("Flash chip at floor %d, chip %d is different:\n", + floor, chip); + } + } + + /* Print and store the manufacturer and ID codes. */ + for (i = 0; nand_flash_ids[i].name != NULL; i++) { + if (mfr == nand_flash_ids[i].manufacture_id && + id == nand_flash_ids[i].model_id) { +#ifdef NAND_DEBUG + printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, " + "Chip ID: 0x%2.2X (%s)\n", mfr, id, + nand_flash_ids[i].name); +#endif + if (!nand->mfr) { + nand->mfr = mfr; + nand->id = id; + nand->chipshift = + nand_flash_ids[i].chipshift; + nand->page256 = nand_flash_ids[i].page256; + nand->eccsize = 256; + if (nand->page256) { + nand->oobblock = 256; + nand->oobsize = 8; + nand->page_shift = 8; + } else { + nand->oobblock = 512; + nand->oobsize = 16; + nand->page_shift = 9; + } + nand->pageadrlen = nand_flash_ids[i].pageadrlen; + nand->erasesize = nand_flash_ids[i].erasesize; + nand->chips_name = nand_flash_ids[i].name; + nand->bus16 = nand_flash_ids[i].bus16; + return 1; + } + return 0; + } + } + + +#ifdef NAND_DEBUG + /* We haven't fully identified the chip. Print as much as we know. */ + printf("Unknown flash chip found: %2.2X %2.2X\n", + id, mfr); +#endif + + return 0; +} + +/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */ + +static void NanD_ScanChips(struct nand_chip *nand) +{ + int floor, chip; + int numchips[NAND_MAX_FLOORS]; + int maxchips = NAND_MAX_CHIPS; + int ret = 1; + + nand->numchips = 0; + nand->mfr = 0; + nand->id = 0; + + + /* For each floor, find the number of valid chips it contains */ + for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { + ret = 1; + numchips[floor] = 0; + for (chip = 0; chip < maxchips && ret != 0; chip++) { + + ret = NanD_IdentChip(nand, floor, chip); + if (ret) { + numchips[floor]++; + nand->numchips++; + } + } + } + + /* If there are none at all that we recognise, bail */ + if (!nand->numchips) { +#ifdef NAND_DEBUG + puts ("No NAND flash chips recognised.\n"); +#endif + return; + } + + /* Allocate an array to hold the information for each chip */ + nand->chips = malloc(sizeof(struct Nand) * nand->numchips); + if (!nand->chips) { + puts ("No memory for allocating chip info structures\n"); + return; + } + + ret = 0; + + /* Fill out the chip array with {floor, chipno} for each + * detected chip in the device. */ + for (floor = 0; floor < NAND_MAX_FLOORS; floor++) { + for (chip = 0; chip < numchips[floor]; chip++) { + nand->chips[ret].floor = floor; + nand->chips[ret].chip = chip; + nand->chips[ret].curadr = 0; + nand->chips[ret].curmode = 0x50; + ret++; + } + } + + /* Calculate and print the total size of the device */ + nand->totlen = nand->numchips * (1 << nand->chipshift); + +#ifdef NAND_DEBUG + printf("%d flash chips found. Total nand_chip size: %ld MB\n", + nand->numchips, nand->totlen >> 20); +#endif +} + +/* we need to be fast here, 1 us per read translates to 1 second per meg */ +static void NanD_ReadBuf (struct nand_chip *nand, u_char * data_buf, int cntr) +{ + unsigned long nandptr = nand->IO_ADDR; + + NanD_Command (nand, NAND_CMD_READ0); + + if (nand->bus16) { + u16 val; + + while (cntr >= 16) { + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + cntr -= 16; + } + + while (cntr > 0) { + val = READ_NAND (nandptr); + *data_buf++ = val & 0xff; + *data_buf++ = val >> 8; + cntr -= 2; + } + } else { + while (cntr >= 16) { + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + *data_buf++ = READ_NAND (nandptr); + cntr -= 16; + } + + while (cntr > 0) { + *data_buf++ = READ_NAND (nandptr); + cntr--; + } + } +} + +/* + * NAND read with ECC + */ +static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len, + size_t * retlen, u_char *buf, u_char *ecc_code) +{ + int col, page; + int ecc_status = 0; +#ifdef CONFIG_MTD_NAND_ECC + int j; + int ecc_failed = 0; + u_char *data_poi; + u_char ecc_calc[6]; +#endif + + /* Do not allow reads past end of device */ + if ((start + len) > nand->totlen) { + printf ("%s: Attempt read beyond end of device %x %x %x\n", + __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen); + *retlen = 0; + return -1; + } + + /* First we calculate the starting page */ + /*page = shr(start, nand->page_shift);*/ + page = start >> nand->page_shift; + + /* Get raw starting column */ + col = start & (nand->oobblock - 1); + + /* Initialize return value */ + *retlen = 0; + + /* Select the NAND device */ + NAND_ENABLE_CE(nand); /* set pin low */ + + /* Loop until all data read */ + while (*retlen < len) { + +#ifdef CONFIG_MTD_NAND_ECC + /* Do we have this page in cache ? */ + if (nand->cache_page == page) + goto readdata; + /* Send the read command */ + NanD_Command(nand, NAND_CMD_READ0); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Read in a page + oob data */ + NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize); + + /* copy data into cache, for read out of cache and if ecc fails */ + if (nand->data_cache) { + memcpy (nand->data_cache, nand->data_buf, + nand->oobblock + nand->oobsize); + } + + /* Pick the ECC bytes out of the oob data */ + for (j = 0; j < 6; j++) { + ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])]; + } + + /* Calculate the ECC and verify it */ + /* If block was not written with ECC, skip ECC */ + if (oob_config.eccvalid_pos != -1 && + (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) { + + nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]); + switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) { + case -1: + printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); + ecc_failed++; + break; + case 1: + case 2: /* transfer ECC corrected data to cache */ + if (nand->data_cache) + memcpy (nand->data_cache, nand->data_buf, 256); + break; + } + } + + if (oob_config.eccvalid_pos != -1 && + nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) { + + nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]); + switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) { + case -1: + printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page); + ecc_failed++; + break; + case 1: + case 2: /* transfer ECC corrected data to cache */ + if (nand->data_cache) + memcpy (&nand->data_cache[256], &nand->data_buf[256], 256); + break; + } + } +readdata: + /* Read the data from ECC data buffer into return buffer */ + data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf; + data_poi += col; + if ((*retlen + (nand->oobblock - col)) >= len) { + memcpy (buf + *retlen, data_poi, len - *retlen); + *retlen = len; + } else { + memcpy (buf + *retlen, data_poi, nand->oobblock - col); + *retlen += nand->oobblock - col; + } + /* Set cache page address, invalidate, if ecc_failed */ + nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1; + + ecc_status += ecc_failed; + ecc_failed = 0; + +#else + /* Send the read command */ + NanD_Command(nand, NAND_CMD_READ0); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Read the data directly into the return buffer */ + if ((*retlen + (nand->oobblock - col)) >= len) { + NanD_ReadBuf(nand, buf + *retlen, len - *retlen); + *retlen = len; + /* We're done */ + continue; + } else { + NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col); + *retlen += nand->oobblock - col; + } +#endif + /* For subsequent reads align to page boundary. */ + col = 0; + /* Increment page address */ + page++; + } + + /* De-select the NAND device */ + NAND_DISABLE_CE(nand); /* set pin high */ + + /* + * Return success, if no ECC failures, else -EIO + * fs driver will take care of that, because + * retlen == desired len and result == -EIO + */ + return ecc_status ? -1 : 0; +} + +/* + * Nand_page_program function is used for write and writev ! + */ +static int nand_write_page (struct nand_chip *nand, + int page, int col, int last, u_char * ecc_code) +{ + + int i; + unsigned long nandptr = nand->IO_ADDR; + +#ifdef CONFIG_MTD_NAND_ECC +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + int ecc_bytes = (nand->oobblock == 512) ? 6 : 3; +#endif +#endif + /* pad oob area */ + for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++) + nand->data_buf[i] = 0xff; + +#ifdef CONFIG_MTD_NAND_ECC + /* Zero out the ECC array */ + for (i = 0; i < 6; i++) + ecc_code[i] = 0x00; + + /* Read back previous written data, if col > 0 */ + if (col) { + NanD_Command (nand, NAND_CMD_READ0); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + if (nand->bus16) { + u16 val; + + for (i = 0; i < col; i += 2) { + val = READ_NAND (nandptr); + nand->data_buf[i] = val & 0xff; + nand->data_buf[i + 1] = val >> 8; + } + } else { + for (i = 0; i < col; i++) + nand->data_buf[i] = READ_NAND (nandptr); + } + } + + /* Calculate and write the ECC if we have enough data */ + if ((col < nand->eccsize) && (last >= nand->eccsize)) { + nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0])); + for (i = 0; i < 3; i++) { + nand->data_buf[(nand->oobblock + + oob_config.ecc_pos[i])] = ecc_code[i]; + } + if (oob_config.eccvalid_pos != -1) { + nand->data_buf[nand->oobblock + + oob_config.eccvalid_pos] = 0xf0; + } + } + + /* Calculate and write the second ECC if we have enough data */ + if ((nand->oobblock == 512) && (last == nand->oobblock)) { + nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3])); + for (i = 3; i < 6; i++) { + nand->data_buf[(nand->oobblock + + oob_config.ecc_pos[i])] = ecc_code[i]; + } + if (oob_config.eccvalid_pos != -1) { + nand->data_buf[nand->oobblock + + oob_config.eccvalid_pos] &= 0x0f; + } + } +#endif + /* Prepad for partial page programming !!! */ + for (i = 0; i < col; i++) + nand->data_buf[i] = 0xff; + + /* Postpad for partial page programming !!! oob is already padded */ + for (i = last; i < nand->oobblock; i++) + nand->data_buf[i] = 0xff; + + /* Send command to begin auto page programming */ + NanD_Command (nand, NAND_CMD_READ0); + NanD_Command (nand, NAND_CMD_SEQIN); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Write out complete page of data */ + if (nand->bus16) { + for (i = 0; i < (nand->oobblock + nand->oobsize); i += 2) { + WRITE_NAND (nand->data_buf[i] + + (nand->data_buf[i + 1] << 8), + nand->IO_ADDR); + } + } else { + for (i = 0; i < (nand->oobblock + nand->oobsize); i++) + WRITE_NAND (nand->data_buf[i], nand->IO_ADDR); + } + + /* Send command to actually program the data */ + NanD_Command (nand, NAND_CMD_PAGEPROG); + NanD_Command (nand, NAND_CMD_STATUS); +#ifdef NAND_NO_RB + { + u_char ret_val; + + do { + ret_val = READ_NAND (nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + /* See if device thinks it succeeded */ + if (READ_NAND (nand->IO_ADDR) & 0x01) { + printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, + page); + return -1; + } +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* + * The NAND device assumes that it is always writing to + * a cleanly erased page. Hence, it performs its internal + * write verification only on bits that transitioned from + * 1 to 0. The device does NOT verify the whole page on a + * byte by byte basis. It is possible that the page was + * not completely erased or the page is becoming unusable + * due to wear. The read with ECC would catch the error + * later when the ECC page check fails, but we would rather + * catch it early in the page write stage. Better to write + * no data than invalid data. + */ + + /* Send command to read back the page */ + if (col < nand->eccsize) + NanD_Command (nand, NAND_CMD_READ0); + else + NanD_Command (nand, NAND_CMD_READ1); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + + /* Loop through and verify the data */ + if (nand->bus16) { + for (i = col; i < last; i = +2) { + if ((nand->data_buf[i] + + (nand->data_buf[i + 1] << 8)) != READ_NAND (nand->IO_ADDR)) { + printf ("%s: Failed write verify, page 0x%08x ", + __FUNCTION__, page); + return -1; + } + } + } else { + for (i = col; i < last; i++) { + if (nand->data_buf[i] != READ_NAND (nand->IO_ADDR)) { + printf ("%s: Failed write verify, page 0x%08x ", + __FUNCTION__, page); + return -1; + } + } + } + +#ifdef CONFIG_MTD_NAND_ECC + /* + * We also want to check that the ECC bytes wrote + * correctly for the same reasons stated above. + */ + NanD_Command (nand, NAND_CMD_READOOB); + if (nand->bus16) { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + (col >> 1)); + } else { + NanD_Address (nand, ADDR_COLUMN_PAGE, + (page << nand->page_shift) + col); + } + if (nand->bus16) { + for (i = 0; i < nand->oobsize; i += 2) { + u16 val; + + val = READ_NAND (nand->IO_ADDR); + nand->data_buf[i] = val & 0xff; + nand->data_buf[i + 1] = val >> 8; + } + } else { + for (i = 0; i < nand->oobsize; i++) { + nand->data_buf[i] = READ_NAND (nand->IO_ADDR); + } + } + for (i = 0; i < ecc_bytes; i++) { + if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) { + printf ("%s: Failed ECC write " + "verify, page 0x%08x, " + "%6i bytes were succesful\n", + __FUNCTION__, page, i); + return -1; + } + } +#endif /* CONFIG_MTD_NAND_ECC */ +#endif /* CONFIG_MTD_NAND_VERIFY_WRITE */ + return 0; +} + +static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len, + size_t * retlen, const u_char * buf, u_char * ecc_code) +{ + int i, page, col, cnt, ret = 0; + + /* Do not allow write past end of device */ + if ((to + len) > nand->totlen) { + printf ("%s: Attempt to write past end of page\n", __FUNCTION__); + return -1; + } + + /* Shift to get page */ + page = ((int) to) >> nand->page_shift; + + /* Get the starting column */ + col = to & (nand->oobblock - 1); + + /* Initialize return length value */ + *retlen = 0; + + /* Select the NAND device */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,0); +#endif +#ifdef CFG_NAND_WP + NAND_WP_OFF(); +#endif + + NAND_ENABLE_CE(nand); /* set pin low */ + + /* Check the WP bit */ + NanD_Command(nand, NAND_CMD_STATUS); + if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { + printf ("%s: Device is write protected!!!\n", __FUNCTION__); + ret = -1; + goto out; + } + + /* Loop until all data is written */ + while (*retlen < len) { + /* Invalidate cache, if we write to this page */ + if (nand->cache_page == page) + nand->cache_page = -1; + + /* Write data into buffer */ + if ((col + len) >= nand->oobblock) { + for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++) { + nand->data_buf[i] = buf[(*retlen + cnt)]; + } + } else { + for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++) { + nand->data_buf[i] = buf[(*retlen + cnt)]; + } + } + /* We use the same function for write and writev !) */ + ret = nand_write_page (nand, page, col, i, ecc_code); + if (ret) + goto out; + + /* Next data start at page boundary */ + col = 0; + + /* Update written bytes count */ + *retlen += cnt; + + /* Increment page address */ + page++; + } + + /* Return happy */ + *retlen = len; + +out: + /* De-select the NAND device */ + NAND_DISABLE_CE(nand); /* set pin high */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,1); +#endif +#ifdef CFG_NAND_WP + NAND_WP_ON(); +#endif + + return ret; +} + +/* read from the 16 bytes of oob data that correspond to a 512 byte + * page or 2 256-byte pages. + */ +int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, u_char * buf) +{ + int len256 = 0; + struct Nand *mychip; + int ret = 0; + + mychip = &nand->chips[ofs >> nand->chipshift]; + + /* update address for 2M x 8bit devices. OOB starts on the second */ + /* page to maintain compatibility with nand_read_ecc. */ + if (nand->page256) { + if (!(ofs & 0x8)) + ofs += 0x100; + else + ofs -= 0x8; + } + + NAND_ENABLE_CE(nand); /* set pin low */ + NanD_Command(nand, NAND_CMD_READOOB); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + ((ofs >> nand->page_shift) << nand->page_shift) + + ((ofs & (nand->oobblock - 1)) >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); + } + + /* treat crossing 8-byte OOB data for 2M x 8bit devices */ + /* Note: datasheet says it should automaticaly wrap to the */ + /* next OOB block, but it didn't work here. mf. */ + if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { + len256 = (ofs | 0x7) + 1 - ofs; + NanD_ReadBuf(nand, buf, len256); + + NanD_Command(nand, NAND_CMD_READOOB); + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); + } + + NanD_ReadBuf(nand, &buf[len256], len - len256); + + *retlen = len; + /* Reading the full OOB data drops us off of the end of the page, + * causing the flash device to go into busy mode, so we need + * to wait until ready 11.4.1 and Toshiba TC58256FT nands */ + + ret = NanD_WaitReady(nand, 1); + NAND_DISABLE_CE(nand); /* set pin high */ + + return ret; + +} + +/* write to the 16 bytes of oob data that correspond to a 512 byte + * page or 2 256-byte pages. + */ +int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len, + size_t * retlen, const u_char * buf) +{ + int len256 = 0; + int i; + unsigned long nandptr = nand->IO_ADDR; + +#ifdef PSYCHO_DEBUG + printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n", + (long)ofs, len, buf[0], buf[1], buf[2], buf[3], + buf[8], buf[9], buf[14],buf[15]); +#endif + + NAND_ENABLE_CE(nand); /* set pin low to enable chip */ + + /* Reset the chip */ + NanD_Command(nand, NAND_CMD_RESET); + + /* issue the Read2 command to set the pointer to the Spare Data Area. */ + NanD_Command(nand, NAND_CMD_READOOB); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + ((ofs >> nand->page_shift) << nand->page_shift) + + ((ofs & (nand->oobblock - 1)) >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); + } + + /* update address for 2M x 8bit devices. OOB starts on the second */ + /* page to maintain compatibility with nand_read_ecc. */ + if (nand->page256) { + if (!(ofs & 0x8)) + ofs += 0x100; + else + ofs -= 0x8; + } + + /* issue the Serial Data In command to initial the Page Program process */ + NanD_Command(nand, NAND_CMD_SEQIN); + if (nand->bus16) { + NanD_Address(nand, ADDR_COLUMN_PAGE, + ((ofs >> nand->page_shift) << nand->page_shift) + + ((ofs & (nand->oobblock - 1)) >> 1)); + } else { + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs); + } + + /* treat crossing 8-byte OOB data for 2M x 8bit devices */ + /* Note: datasheet says it should automaticaly wrap to the */ + /* next OOB block, but it didn't work here. mf. */ + if (nand->page256 && ofs + len > (ofs | 0x7) + 1) { + len256 = (ofs | 0x7) + 1 - ofs; + for (i = 0; i < len256; i++) + WRITE_NAND(buf[i], nandptr); + + NanD_Command(nand, NAND_CMD_PAGEPROG); + NanD_Command(nand, NAND_CMD_STATUS); +#ifdef NAND_NO_RB + { u_char ret_val; + do { + ret_val = READ_NAND(nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + if (READ_NAND(nandptr) & 1) { + puts ("Error programming oob data\n"); + /* There was an error */ + NAND_DISABLE_CE(nand); /* set pin high */ + *retlen = 0; + return -1; + } + NanD_Command(nand, NAND_CMD_SEQIN); + NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff)); + } + + if (nand->bus16) { + for (i = len256; i < len; i += 2) { + WRITE_NAND(buf[i] + (buf[i+1] << 8), nandptr); + } + } else { + for (i = len256; i < len; i++) + WRITE_NAND(buf[i], nandptr); + } + + NanD_Command(nand, NAND_CMD_PAGEPROG); + NanD_Command(nand, NAND_CMD_STATUS); +#ifdef NAND_NO_RB + { u_char ret_val; + do { + ret_val = READ_NAND(nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + if (READ_NAND(nandptr) & 1) { + puts ("Error programming oob data\n"); + /* There was an error */ + NAND_DISABLE_CE(nand); /* set pin high */ + *retlen = 0; + return -1; + } + + NAND_DISABLE_CE(nand); /* set pin high */ + *retlen = len; + return 0; + +} + +int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean) +{ + /* This is defined as a structure so it will work on any system + * using native endian jffs2 (the default). + */ + static struct jffs2_unknown_node clean_marker = { + JFFS2_MAGIC_BITMASK, + JFFS2_NODETYPE_CLEANMARKER, + 8 /* 8 bytes in this node */ + }; + unsigned long nandptr; + struct Nand *mychip; + int ret = 0; + + if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) { + printf ("Offset and size must be sector aligned, erasesize = %d\n", + (int) nand->erasesize); + return -1; + } + + nandptr = nand->IO_ADDR; + + /* Select the NAND device */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,0); +#endif +#ifdef CFG_NAND_WP + NAND_WP_OFF(); +#endif + NAND_ENABLE_CE(nand); /* set pin low */ + + /* Check the WP bit */ + NanD_Command(nand, NAND_CMD_STATUS); + if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { + printf ("nand_write_ecc: Device is write protected!!!\n"); + ret = -1; + goto out; + } + + /* Check the WP bit */ + NanD_Command(nand, NAND_CMD_STATUS); + if (!(READ_NAND(nand->IO_ADDR) & 0x80)) { + printf ("%s: Device is write protected!!!\n", __FUNCTION__); + ret = -1; + goto out; + } + + /* FIXME: Do nand in the background. Use timers or schedule_task() */ + while(len) { + /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/ + mychip = &nand->chips[ofs >> nand->chipshift]; + + /* always check for bad block first, genuine bad blocks + * should _never_ be erased. + */ + if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) { + /* Select the NAND device */ + NAND_ENABLE_CE(nand); /* set pin low */ + + NanD_Command(nand, NAND_CMD_ERASE1); + NanD_Address(nand, ADDR_PAGE, ofs); + NanD_Command(nand, NAND_CMD_ERASE2); + + NanD_Command(nand, NAND_CMD_STATUS); + +#ifdef NAND_NO_RB + { u_char ret_val; + do { + ret_val = READ_NAND(nandptr); /* wait till ready */ + } while ((ret_val & 0x40) != 0x40); + } +#endif + if (READ_NAND(nandptr) & 1) { + printf ("%s: Error erasing at 0x%lx\n", + __FUNCTION__, (long)ofs); + /* There was an error */ + ret = -1; + goto out; + } + if (clean) { + int n; /* return value not used */ + int p, l; + + /* clean marker position and size depend + * on the page size, since 256 byte pages + * only have 8 bytes of oob data + */ + if (nand->page256) { + p = NAND_JFFS2_OOB8_FSDAPOS; + l = NAND_JFFS2_OOB8_FSDALEN; + } else { + p = NAND_JFFS2_OOB16_FSDAPOS; + l = NAND_JFFS2_OOB16_FSDALEN; + } + + ret = nand_write_oob(nand, ofs + p, l, (size_t *)&n, + (u_char *)&clean_marker); + /* quit here if write failed */ + if (ret) + goto out; + } + } + ofs += nand->erasesize; + len -= nand->erasesize; + } + +out: + /* De-select the NAND device */ + NAND_DISABLE_CE(nand); /* set pin high */ +#ifdef CONFIG_OMAP1510 + archflashwp(0,1); +#endif +#ifdef CFG_NAND_WP + NAND_WP_ON(); +#endif + + return ret; +} + + +static inline int nandcheck(unsigned long potential, unsigned long physadr) +{ + return 0; +} + +unsigned long nand_probe(unsigned long physadr) +{ + struct nand_chip *nand = NULL; + int i = 0, ChipID = 1; + +#ifdef CONFIG_MTD_NAND_ECC_JFFS2 + oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0; + oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1; + oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2; + oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3; + oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4; + oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5; + oob_config.eccvalid_pos = 4; +#else + oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0; + oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1; + oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2; + oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3; + oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4; + oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5; + oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS; +#endif + oob_config.badblock_pos = 5; + + for (i=0; iIO_ADDR = physadr; + nand->cache_page = -1; /* init the cache page */ + NanD_ScanChips(nand); + + if (nand->totlen == 0) { + /* no chips found, clean up and quit */ + memset((char *)nand, 0, sizeof(struct nand_chip)); + nand->ChipID = NAND_ChipID_UNKNOWN; + return (0); + } + + nand->ChipID = ChipID; + if (curr_device == -1) + curr_device = i; + + nand->data_buf = malloc (nand->oobblock + nand->oobsize); + if (!nand->data_buf) { + puts ("Cannot allocate memory for data structures.\n"); + return (0); + } + + return (nand->totlen); +} + +#ifdef CONFIG_MTD_NAND_ECC +/* + * Pre-calculated 256-way 1 byte column parity + */ +static const u_char nand_ecc_precalc_table[] = { + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, + 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, + 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, + 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, + 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, + 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, + 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, + 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, + 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, + 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a, + 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, + 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f, + 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, + 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c, + 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, + 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69, + 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, + 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03, + 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, + 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66, + 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, + 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65, + 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, + 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00 +}; + + +/* + * Creates non-inverted ECC code from line parity + */ +static void nand_trans_result(u_char reg2, u_char reg3, + u_char *ecc_code) +{ + u_char a, b, i, tmp1, tmp2; + + /* Initialize variables */ + a = b = 0x80; + tmp1 = tmp2 = 0; + + /* Calculate first ECC byte */ + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */ + tmp1 |= b; + b >>= 1; + a >>= 1; + } + + /* Calculate second ECC byte */ + b = 0x80; + for (i = 0; i < 4; i++) { + if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */ + tmp2 |= b; + b >>= 1; + a >>= 1; + } + + /* Store two of the ECC bytes */ + ecc_code[0] = tmp1; + ecc_code[1] = tmp2; +} + +/* + * Calculate 3 byte ECC code for 256 byte block + */ +static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code) +{ + u_char idx, reg1, reg3; + int j; + + /* Initialize variables */ + reg1 = reg3 = 0; + ecc_code[0] = ecc_code[1] = ecc_code[2] = 0; + + /* Build up column parity */ + for(j = 0; j < 256; j++) { + + /* Get CP0 - CP5 from table */ + idx = nand_ecc_precalc_table[dat[j]]; + reg1 ^= idx; + + /* All bit XOR = 1 ? */ + if (idx & 0x40) { + reg3 ^= (u_char) j; + } + } + + /* Create non-inverted ECC code from line parity */ + nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code); + + /* Calculate final ECC code */ + ecc_code[0] = ~ecc_code[0]; + ecc_code[1] = ~ecc_code[1]; + ecc_code[2] = ((~reg1) << 2) | 0x03; +} + +/* + * Detect and correct a 1 bit error for 256 byte block + */ +static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) +{ + u_char a, b, c, d1, d2, d3, add, bit, i; + + /* Do error detection */ + d1 = calc_ecc[0] ^ read_ecc[0]; + d2 = calc_ecc[1] ^ read_ecc[1]; + d3 = calc_ecc[2] ^ read_ecc[2]; + + if ((d1 | d2 | d3) == 0) { + /* No errors */ + return 0; + } else { + a = (d1 ^ (d1 >> 1)) & 0x55; + b = (d2 ^ (d2 >> 1)) & 0x55; + c = (d3 ^ (d3 >> 1)) & 0x54; + + /* Found and will correct single bit error in the data */ + if ((a == 0x55) && (b == 0x55) && (c == 0x54)) { + c = 0x80; + add = 0; + a = 0x80; + for (i=0; i<4; i++) { + if (d1 & c) + add |= a; + c >>= 2; + a >>= 1; + } + c = 0x80; + for (i=0; i<4; i++) { + if (d2 & c) + add |= a; + c >>= 2; + a >>= 1; + } + bit = 0; + b = 0x04; + c = 0x80; + for (i=0; i<3; i++) { + if (d3 & c) + bit |= b; + c >>= 2; + b >>= 1; + } + b = 0x01; + a = dat[add]; + a ^= (b << bit); + dat[add] = a; + return 1; + } + else { + i = 0; + while (d1) { + if (d1 & 0x01) + ++i; + d1 >>= 1; + } + while (d2) { + if (d2 & 0x01) + ++i; + d2 >>= 1; + } + while (d3) { + if (d3 & 0x01) + ++i; + d3 >>= 1; + } + if (i == 1) { + /* ECC Code Error Correction */ + read_ecc[0] = calc_ecc[0]; + read_ecc[1] = calc_ecc[1]; + read_ecc[2] = calc_ecc[2]; + return 2; + } + else { + /* Uncorrectable Error */ + return -1; + } + } + } + + /* Should never happen */ + return -1; +} + +#endif + +#ifdef CONFIG_JFFS2_NAND +int read_jffs2_nand(size_t start, size_t len, + size_t * retlen, u_char * buf, int nanddev) +{ + return nand_legacy_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2, + start, len, retlen, buf); +} +#endif /* CONFIG_JFFS2_NAND */ + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) */ diff --git a/drivers/natsemi.c b/drivers/natsemi.c new file mode 100644 index 000000000..b009db63e --- /dev/null +++ b/drivers/natsemi.c @@ -0,0 +1,882 @@ +/* + natsemi.c: A U-Boot driver for the NatSemi DP8381x series. + Author: Mark A. Rakes (mark_rakes@vivato.net) + + Adapted from an Etherboot driver written by: + + Copyright (C) 2001 Entity Cyber, Inc. + + This development of this Etherboot driver was funded by + + Sicom Systems: http://www.sicompos.com/ + + Author: Marty Connor (mdc@thinguin.org) + Adapted from a Linux driver which was written by Donald Becker + + This software may be used and distributed according to the terms + of the GNU Public License (GPL), incorporated herein by reference. + + Original Copyright Notice: + + Written/copyright 1999-2001 by Donald Becker. + + This software may be used and distributed according to the terms of + the GNU General Public License (GPL), incorporated herein by reference. + Drivers based on or derived from this code fall under the GPL and must + retain the authorship, copyright and license notice. This file is not + a complete program and may only be used when the entire operating + system is licensed under the GPL. License for under other terms may be + available. Contact the original author for details. + + The original author may be reached as becker@scyld.com, or at + Scyld Computing Corporation + 410 Severn Ave., Suite 210 + Annapolis MD 21403 + + Support information and updates available at + http://www.scyld.com/network/netsemi.html + + References: + http://www.scyld.com/expert/100mbps.html + http://www.scyld.com/expert/NWay.html + Datasheet is available from: + http://www.national.com/pf/DP/DP83815.html +*/ + +/* Revision History + * October 2002 mar 1.0 + * Initial U-Boot Release. Tested with Netgear FA311 board + * and dp83815 chipset on custom board +*/ + +/* Includes */ +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_NATSEMI) + +/* defines */ +#define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/ + +#define DSIZE 0x00000FFF +#define ETH_ALEN 6 +#define CRC_SIZE 4 +#define TOUT_LOOP 500000 +#define TX_BUF_SIZE 1536 +#define RX_BUF_SIZE 1536 +#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ + +/* Offsets to the device registers. + Unlike software-only systems, device drivers interact with complex hardware. + It's not useful to define symbolic names for every register bit in the + device. */ +enum register_offsets { + ChipCmd = 0x00, + ChipConfig = 0x04, + EECtrl = 0x08, + IntrMask = 0x14, + IntrEnable = 0x18, + TxRingPtr = 0x20, + TxConfig = 0x24, + RxRingPtr = 0x30, + RxConfig = 0x34, + ClkRun = 0x3C, + RxFilterAddr = 0x48, + RxFilterData = 0x4C, + SiliconRev = 0x58, + PCIPM = 0x44, + BasicControl = 0x80, + BasicStatus = 0x84, + /* These are from the spec, around page 78... on a separate table. */ + PGSEL = 0xCC, + PMDCSR = 0xE4, + TSTDAT = 0xFC, + DSPCFG = 0xF4, + SDCFG = 0x8C +}; + +/* Bit in ChipCmd. */ +enum ChipCmdBits { + ChipReset = 0x100, + RxReset = 0x20, + TxReset = 0x10, + RxOff = 0x08, + RxOn = 0x04, + TxOff = 0x02, + TxOn = 0x01 +}; + +enum ChipConfigBits { + LinkSts = 0x80000000, + HundSpeed = 0x40000000, + FullDuplex = 0x20000000, + TenPolarity = 0x10000000, + AnegDone = 0x08000000, + AnegEnBothBoth = 0x0000E000, + AnegDis100Full = 0x0000C000, + AnegEn100Both = 0x0000A000, + AnegDis100Half = 0x00008000, + AnegEnBothHalf = 0x00006000, + AnegDis10Full = 0x00004000, + AnegEn10Both = 0x00002000, + DuplexMask = 0x00008000, + SpeedMask = 0x00004000, + AnegMask = 0x00002000, + AnegDis10Half = 0x00000000, + ExtPhy = 0x00001000, + PhyRst = 0x00000400, + PhyDis = 0x00000200, + BootRomDisable = 0x00000004, + BEMode = 0x00000001, +}; + +enum TxConfig_bits { + TxDrthMask = 0x3f, + TxFlthMask = 0x3f00, + TxMxdmaMask = 0x700000, + TxMxdma_512 = 0x0, + TxMxdma_4 = 0x100000, + TxMxdma_8 = 0x200000, + TxMxdma_16 = 0x300000, + TxMxdma_32 = 0x400000, + TxMxdma_64 = 0x500000, + TxMxdma_128 = 0x600000, + TxMxdma_256 = 0x700000, + TxCollRetry = 0x800000, + TxAutoPad = 0x10000000, + TxMacLoop = 0x20000000, + TxHeartIgn = 0x40000000, + TxCarrierIgn = 0x80000000 +}; + +enum RxConfig_bits { + RxDrthMask = 0x3e, + RxMxdmaMask = 0x700000, + RxMxdma_512 = 0x0, + RxMxdma_4 = 0x100000, + RxMxdma_8 = 0x200000, + RxMxdma_16 = 0x300000, + RxMxdma_32 = 0x400000, + RxMxdma_64 = 0x500000, + RxMxdma_128 = 0x600000, + RxMxdma_256 = 0x700000, + RxAcceptLong = 0x8000000, + RxAcceptTx = 0x10000000, + RxAcceptRunt = 0x40000000, + RxAcceptErr = 0x80000000 +}; + +/* Bits in the RxMode register. */ +enum rx_mode_bits { + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0xC0000000, + AcceptMulticast = 0x00200000, + AcceptAllMulticast = 0x20000000, + AcceptAllPhys = 0x10000000, + AcceptMyPhys = 0x08000000 +}; + +typedef struct _BufferDesc { + u32 link; + vu_long cmdsts; + u32 bufptr; + u32 software_use; +} BufferDesc; + +/* Bits in network_desc.status */ +enum desc_status_bits { + DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000, + DescNoCRC = 0x10000000, DescPktOK = 0x08000000, + DescSizeMask = 0xfff, + + DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000, + DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000, + DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000, + DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000, + + DescRxAbort = 0x04000000, DescRxOver = 0x02000000, + DescRxDest = 0x01800000, DescRxLong = 0x00400000, + DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000, + DescRxCRC = 0x00080000, DescRxAlign = 0x00040000, + DescRxLoop = 0x00020000, DesRxColl = 0x00010000, +}; + +/* Globals */ +#ifdef NATSEMI_DEBUG +static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */ +#endif +static u32 SavedClkRun; +static unsigned int cur_rx; +static unsigned int advertising; +static unsigned int rx_config; +static unsigned int tx_config; + +/* Note: transmit and receive buffers and descriptors must be + longword aligned */ +static BufferDesc txd __attribute__ ((aligned(4))); +static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4))); + +static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4))); +static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE] + __attribute__ ((aligned(4))); + +/* Function Prototypes */ +#if 0 +static void write_eeprom(struct eth_device *dev, long addr, int location, + short value); +#endif +static int read_eeprom(struct eth_device *dev, long addr, int location); +static int mdio_read(struct eth_device *dev, int phy_id, int location); +static int natsemi_init(struct eth_device *dev, bd_t * bis); +static void natsemi_reset(struct eth_device *dev); +static void natsemi_init_rxfilter(struct eth_device *dev); +static void natsemi_init_txd(struct eth_device *dev); +static void natsemi_init_rxd(struct eth_device *dev); +static void natsemi_set_rx_mode(struct eth_device *dev); +static void natsemi_check_duplex(struct eth_device *dev); +static int natsemi_send(struct eth_device *dev, volatile void *packet, + int length); +static int natsemi_poll(struct eth_device *dev); +static void natsemi_disable(struct eth_device *dev); + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815}, + {} +}; + +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +static inline int +INW(struct eth_device *dev, u_long addr) +{ + return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); +} + +static int +INL(struct eth_device *dev, u_long addr) +{ + return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); +} + +static inline void +OUTW(struct eth_device *dev, int command, u_long addr) +{ + *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); +} + +static inline void +OUTL(struct eth_device *dev, int command, u_long addr) +{ + *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); +} + +/* + * Function: natsemi_initialize + * + * Description: Retrieves the MAC address of the card, and sets up some + * globals required by other routines, and initializes the NIC, making it + * ready to send and receive packets. + * + * Side effects: + * leaves the natsemi initialized, and ready to recieve packets. + * + * Returns: struct eth_device *: pointer to NIC data structure + */ + +int +natsemi_initialize(bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase, status, chip_config; + int i, idx = 0; + int prev_eedata; + u32 tmp; + + while (1) { + /* Find PCI device(s) */ + if ((devno = pci_find_devices(supported, idx++)) < 0) { + break; + } + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); + iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */ + + pci_write_config_dword(devno, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Check if I/O accesses and Bus Mastering are enabled. */ + pci_read_config_dword(devno, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { + printf("Error: Can not enable MEM access.\n"); + continue; + } else if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + dev = (struct eth_device *) malloc(sizeof *dev); + + sprintf(dev->name, "dp83815#%d", card_number); + dev->iobase = bus_to_phys(iobase); +#ifdef NATSEMI_DEBUG + printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase); +#endif + dev->priv = (void *) devno; + dev->init = natsemi_init; + dev->halt = natsemi_disable; + dev->send = natsemi_send; + dev->recv = natsemi_poll; + + eth_register(dev); + + card_number++; + + /* Set the latency timer for value. */ + pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); + + udelay(10 * 1000); + + /* natsemi has a non-standard PM control register + * in PCI config space. Some boards apparently need + * to be brought to D0 in this manner. */ + pci_read_config_dword(devno, PCIPM, &tmp); + if (tmp & (0x03 | 0x100)) { + /* D0 state, disable PME assertion */ + u32 newtmp = tmp & ~(0x03 | 0x100); + pci_write_config_dword(devno, PCIPM, newtmp); + } + + printf("natsemi: EEPROM contents:\n"); + for (i = 0; i <= EEPROM_SIZE; i++) { + short eedata = read_eeprom(dev, EECtrl, i); + printf(" %04hx", eedata); + } + printf("\n"); + + /* get MAC address */ + prev_eedata = read_eeprom(dev, EECtrl, 6); + for (i = 0; i < 3; i++) { + int eedata = read_eeprom(dev, EECtrl, i + 7); + dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15); + dev->enetaddr[i*2+1] = eedata >> 7; + prev_eedata = eedata; + } + + /* Reset the chip to erase any previous misconfiguration. */ + OUTL(dev, ChipReset, ChipCmd); + + advertising = mdio_read(dev, 1, 4); + chip_config = INL(dev, ChipConfig); +#ifdef NATSEMI_DEBUG + printf("%s: Transceiver status %#08X advertising %#08X\n", + dev->name, (int) INL(dev, BasicStatus), advertising); + printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n", + dev->name, chip_config & AnegMask ? "enabled, advertise" : + "disabled, force", chip_config & SpeedMask ? "0" : "", + chip_config & DuplexMask ? "full" : "half"); +#endif + chip_config |= AnegEnBothBoth; +#ifdef NATSEMI_DEBUG + printf("%s: changed to autoneg. %s 10%s %s duplex.\n", + dev->name, chip_config & AnegMask ? "enabled, advertise" : + "disabled, force", chip_config & SpeedMask ? "0" : "", + chip_config & DuplexMask ? "full" : "half"); +#endif + /*write new autoneg bits, reset phy*/ + OUTL(dev, (chip_config | PhyRst), ChipConfig); + /*un-reset phy*/ + OUTL(dev, chip_config, ChipConfig); + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + SavedClkRun = INL(dev, ClkRun); + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + } + return card_number; +} + +/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. + The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */ + +/* Delay between EEPROM clock transitions. + No extra delay is needed with 33Mhz PCI, but future 66Mhz + access may need a delay. */ +#define eeprom_delay(ee_addr) INL(dev, ee_addr) + +enum EEPROM_Ctrl_Bits { + EE_ShiftClk = 0x04, + EE_DataIn = 0x01, + EE_ChipSelect = 0x08, + EE_DataOut = 0x02 +}; + +#define EE_Write0 (EE_ChipSelect) +#define EE_Write1 (EE_ChipSelect | EE_DataIn) +/* The EEPROM commands include the alway-set leading bit. */ +enum EEPROM_Cmds { + EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6), + EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6), +}; + +#if 0 +static void +write_eeprom(struct eth_device *dev, long addr, int location, short value) +{ + int i; + int ee_addr = (typeof(ee_addr))addr; + short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/ + short write_cmd = location | EE_WriteCmd; + +#ifdef NATSEMI_DEBUG + printf("write_eeprom: %08x, %04hx, %04hx\n", + dev->iobase + ee_addr, write_cmd, value); +#endif + /* Shift the write enable command bits out. */ + for (i = 9; i >= 0; i--) { + short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, cmdval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, cmdval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + + OUTL(dev, 0, ee_addr); /*bring chip select low*/ + OUTL(dev, EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + + /* Shift the write command bits out. */ + for (i = 9; i >= 0; i--) { + short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, cmdval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, cmdval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + + for (i = 0; i < 16; i++) { + short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, cmdval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, cmdval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + + OUTL(dev, 0, ee_addr); /*bring chip select low*/ + OUTL(dev, EE_ShiftClk, ee_addr); + for (i = 0; i < 200000; i++) { + OUTL(dev, EE_Write0, ee_addr); /*poll for done*/ + if (INL(dev, ee_addr) & EE_DataOut) { + break; /*finished*/ + } + } + eeprom_delay(ee_addr); + + /* Terminate the EEPROM access. */ + OUTL(dev, EE_Write0, ee_addr); + OUTL(dev, 0, ee_addr); + return; +} +#endif + +static int +read_eeprom(struct eth_device *dev, long addr, int location) +{ + int i; + int retval = 0; + int ee_addr = (typeof(ee_addr))addr; + int read_cmd = location | EE_ReadCmd; + + OUTL(dev, EE_Write0, ee_addr); + + /* Shift the read command bits out. */ + for (i = 10; i >= 0; i--) { + short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0; + OUTL(dev, dataval, ee_addr); + eeprom_delay(ee_addr); + OUTL(dev, dataval | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + } + OUTL(dev, EE_ChipSelect, ee_addr); + eeprom_delay(ee_addr); + + for (i = 0; i < 16; i++) { + OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr); + eeprom_delay(ee_addr); + retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0; + OUTL(dev, EE_ChipSelect, ee_addr); + eeprom_delay(ee_addr); + } + + /* Terminate the EEPROM access. */ + OUTL(dev, EE_Write0, ee_addr); + OUTL(dev, 0, ee_addr); +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("read_eeprom: %08x, %08x, retval %08x\n", + dev->iobase + ee_addr, read_cmd, retval); +#endif + return retval; +} + +/* MII transceiver control section. + The 83815 series has an internal transceiver, and we present the + management registers as if they were MII connected. */ + +static int +mdio_read(struct eth_device *dev, int phy_id, int location) +{ + if (phy_id == 1 && location < 32) + return INL(dev, BasicControl+(location<<2))&0xffff; + else + return 0xffff; +} + +/* Function: natsemi_init + * + * Description: resets the ethernet controller chip and configures + * registers and data structures required for sending and receiving packets. + * + * Arguments: struct eth_device *dev: NIC data structure + * + * returns: int. + */ + +static int +natsemi_init(struct eth_device *dev, bd_t * bis) +{ + + natsemi_reset(dev); + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + + natsemi_init_rxfilter(dev); + natsemi_init_txd(dev); + natsemi_init_rxd(dev); + + /* Configure the PCI bus bursts and FIFO thresholds. */ + tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002); + rx_config = RxMxdma_256 | 0x20; + +#ifdef NATSEMI_DEBUG + printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config); + printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config); +#endif + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); + + natsemi_check_duplex(dev); + natsemi_set_rx_mode(dev); + + OUTL(dev, (RxOn | TxOn), ChipCmd); + return 1; +} + +/* + * Function: natsemi_reset + * + * Description: soft resets the controller chip + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ +static void +natsemi_reset(struct eth_device *dev) +{ + OUTL(dev, ChipReset, ChipCmd); + + /* On page 78 of the spec, they recommend some settings for "optimum + performance" to be done in sequence. These settings optimize some + of the 100Mbit autodetection circuitry. Also, we only want to do + this for rev C of the chip. */ + if (INL(dev, SiliconRev) == 0x302) { + OUTW(dev, 0x0001, PGSEL); + OUTW(dev, 0x189C, PMDCSR); + OUTW(dev, 0x0000, TSTDAT); + OUTW(dev, 0x5040, DSPCFG); + OUTW(dev, 0x008C, SDCFG); + } + /* Disable interrupts using the mask. */ + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); +} + +/* Function: natsemi_init_rxfilter + * + * Description: sets receive filter address to our MAC address + * + * Arguments: struct eth_device *dev: NIC data structure + * + * returns: void. + */ + +static void +natsemi_init_rxfilter(struct eth_device *dev) +{ + int i; + + for (i = 0; i < ETH_ALEN; i += 2) { + OUTL(dev, i, RxFilterAddr); + OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8), + RxFilterData); + } +} + +/* + * Function: natsemi_init_txd + * + * Description: initializes the Tx descriptor + * + * Arguments: struct eth_device *dev: NIC data structure + * + * returns: void. + */ + +static void +natsemi_init_txd(struct eth_device *dev) +{ + txd.link = (u32) 0; + txd.cmdsts = (u32) 0; + txd.bufptr = (u32) & txb[0]; + + /* load Transmit Descriptor Register */ + OUTL(dev, (u32) & txd, TxRingPtr); +#ifdef NATSEMI_DEBUG + printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n", + INL(dev, TxRingPtr)); +#endif +} + +/* Function: natsemi_init_rxd + * + * Description: initializes the Rx descriptor ring + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ + +static void +natsemi_init_rxd(struct eth_device *dev) +{ + int i; + + cur_rx = 0; + + /* init RX descriptor */ + for (i = 0; i < NUM_RX_DESC; i++) { + rxd[i].link = + cpu_to_le32((i + 1 < + NUM_RX_DESC) ? (u32) & rxd[i + + 1] : (u32) & + rxd[0]); + rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE); + rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]); +#ifdef NATSEMI_DEBUG + printf + ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n", + i, &rxd[i], le32_to_cpu(rxd[i].link), + rxd[i].cmdsts, rxd[i].bufptr); +#endif + } + + /* load Receive Descriptor Register */ + OUTL(dev, (u32) & rxd[0], RxRingPtr); + +#ifdef NATSEMI_DEBUG + printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n", + INL(dev, RxRingPtr)); +#endif +} + +/* Function: natsemi_set_rx_mode + * + * Description: + * sets the receive mode to accept all broadcast packets and packets + * with our MAC address, and reject all multicast packets. + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ + +static void +natsemi_set_rx_mode(struct eth_device *dev) +{ + u32 rx_mode = AcceptBroadcast | AcceptMyPhys; + + OUTL(dev, rx_mode, RxFilterAddr); +} + +static void +natsemi_check_duplex(struct eth_device *dev) +{ + int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0; + +#ifdef NATSEMI_DEBUG + printf("%s: Setting %s-duplex based on negotiated link" + " capability.\n", dev->name, duplex ? "full" : "half"); +#endif + if (duplex) { + rx_config |= RxAcceptTx; + tx_config |= (TxCarrierIgn | TxHeartIgn); + } else { + rx_config &= ~RxAcceptTx; + tx_config &= ~(TxCarrierIgn | TxHeartIgn); + } + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); +} + +/* Function: natsemi_send + * + * Description: transmits a packet and waits for completion or timeout. + * + * Returns: void. */ +static int +natsemi_send(struct eth_device *dev, volatile void *packet, int length) +{ + u32 i, status = 0; + u32 tx_status = 0; + vu_long *res = (vu_long *)&tx_status; + + /* Stop the transmitter */ + OUTL(dev, TxOff, ChipCmd); + +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("natsemi_send: sending %d bytes\n", (int) length); +#endif + + /* set the transmit buffer descriptor and enable Transmit State Machine */ + txd.link = cpu_to_le32(0); + txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet)); + txd.cmdsts = cpu_to_le32(DescOwn | length); + + /* load Transmit Descriptor Register */ + OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr); +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("natsemi_send: TX descriptor register loaded with: %#08X\n", + INL(dev, TxRingPtr)); +#endif + /* restart the transmitter */ + OUTL(dev, TxOn, ChipCmd); + + for (i = 0; + (*res = le32_to_cpu(txd.cmdsts)) & DescOwn; + i++) { + if (i >= TOUT_LOOP) { + printf + ("%s: tx error buffer not ready: txd.cmdsts == %#X\n", + dev->name, tx_status); + goto Done; + } + } + + if (!(tx_status & DescPktOK)) { + printf("natsemi_send: Transmit error, Tx status %X.\n", + tx_status); + goto Done; + } + + status = 1; + Done: + return status; +} + +/* Function: natsemi_poll + * + * Description: checks for a received packet and returns it if found. + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: 1 if packet was received. + * 0 if no packet was received. + * + * Side effects: + * Returns (copies) the packet to the array dev->packet. + * Returns the length of the packet. + */ + +static int +natsemi_poll(struct eth_device *dev) +{ + int retstat = 0; + int length = 0; + u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts); + + if (!(rx_status & (u32) DescOwn)) + return retstat; +#ifdef NATSEMI_DEBUG + if (natsemi_debug) + printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n", + cur_rx, rx_status); +#endif + length = (rx_status & DSIZE) - CRC_SIZE; + + if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) { + printf + ("natsemi_poll: Corrupted packet received, buffer status = %X\n", + rx_status); + retstat = 0; + } else { /* give packet to higher level routine */ + NetReceive((rxb + cur_rx * RX_BUF_SIZE), length); + retstat = 1; + } + + /* return the descriptor and buffer to receive ring */ + rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE); + rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]); + + if (++cur_rx == NUM_RX_DESC) + cur_rx = 0; + + /* re-enable the potentially idle receive state machine */ + OUTL(dev, RxOn, ChipCmd); + + return retstat; +} + +/* Function: natsemi_disable + * + * Description: Turns off interrupts and stops Tx and Rx engines + * + * Arguments: struct eth_device *dev: NIC data structure + * + * Returns: void. + */ + +static void +natsemi_disable(struct eth_device *dev) +{ + /* Disable interrupts using the mask. */ + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); + + /* Stop the chip's Tx and Rx processes. */ + OUTL(dev, RxOff | TxOff, ChipCmd); + + /* Restore PME enable bit */ + OUTL(dev, SavedClkRun, ClkRun); +} + +#endif diff --git a/drivers/ne2000.c b/drivers/ne2000.c new file mode 100644 index 000000000..b7ed87616 --- /dev/null +++ b/drivers/ne2000.c @@ -0,0 +1,963 @@ +/* +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + + +========================================================================== + +dev/if_dp83902a.c + +Ethernet device driver for NS DP83902a ethernet controller + +========================================================================== +####ECOSGPLCOPYRIGHTBEGIN#### +------------------------------------------- +This file is part of eCos, the Embedded Configurable Operating System. +Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + +eCos is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2 or (at your option) any later version. + +eCos is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License along +with eCos; if not, write to the Free Software Foundation, Inc., +59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + +As a special exception, if other files instantiate templates or use macros +or inline functions from this file, or you compile this file and link it +with other works to produce a work based on this file, this file does not +by itself cause the resulting work to be covered by the GNU General Public +License. However the source code for this file must still be made available +in accordance with section (3) of the GNU General Public License. + +This exception does not invalidate any other reasons why a work based on +this file might be covered by the GNU General Public License. + +Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +at http://sources.redhat.com/ecos/ecos-license/ +------------------------------------------- +####ECOSGPLCOPYRIGHTEND#### +####BSDCOPYRIGHTBEGIN#### + +------------------------------------------- + +Portions of this software may have been derived from OpenBSD or other sources, +and are covered by the appropriate copyright disclaimers included herein. + +------------------------------------------- + +####BSDCOPYRIGHTEND#### +========================================================================== +#####DESCRIPTIONBEGIN#### + +Author(s): gthomas +Contributors: gthomas, jskov, rsandifo +Date: 2001-06-13 +Purpose: +Description: + +FIXME: Will fail if pinged with large packets (1520 bytes) +Add promisc config +Add SNMP + +####DESCRIPTIONEND#### + + +========================================================================== + +*/ + +#include +#include +#include +#include + +#ifdef CONFIG_DRIVER_NE2000 + +/* wor around udelay resetting OCR */ +static void my_udelay(long us) { + long tmo; + + tmo = get_timer (0) + us * CFG_HZ / 1000000; /* will this be much greater than 0 ? */ + while (get_timer (0) < tmo); +} + +#define mdelay(n) my_udelay((n)*1000) + +/* forward definition of function used for the uboot interface */ +void uboot_push_packet_len(int len); +void uboot_push_tx_done(int key, int val); + +/* timeout for tx/rx in s */ +#define TOUT 5 + +#define ETHER_ADDR_LEN 6 + +/* + ------------------------------------------------------------------------ + Debugging details + + Set to perms of: + 0 disables all debug output + 1 for process debug output + 2 for added data IO output: get_reg, put_reg + 4 for packet allocation/free output + 8 for only startup status, so we can tell we're installed OK +*/ +/*#define DEBUG 0xf*/ +#define DEBUG 0 + +#if DEBUG & 1 +#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0) +#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0) +#else +#define DEBUG_FUNCTION() do {} while(0) +#define DEBUG_LINE() do {} while(0) +#endif + +#include "ne2000.h" + +#if DEBUG & 1 +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + +static dp83902a_priv_data_t nic; /* just one instance of the card supported */ + +static bool +dp83902a_init(void) +{ + dp83902a_priv_data_t *dp = &nic; + cyg_uint8* base; + int i; + + DEBUG_FUNCTION(); + + base = dp->base; + if (!base) return false; /* No device found */ + + DEBUG_LINE(); + + /* Prepare ESA */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ + /* Use the address from the serial EEPROM */ + for (i = 0; i < 6; i++) + DP_IN(base, DP_P1_PAR0+i, dp->esa[i]); + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ + + printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n", + "eeprom", + dp->esa[0], + dp->esa[1], + dp->esa[2], + dp->esa[3], + dp->esa[4], + dp->esa[5] ); + + return true; +} + +static void +dp83902a_stop(void) +{ + dp83902a_priv_data_t *dp = &nic; + cyg_uint8 *base = dp->base; + + DEBUG_FUNCTION(); + + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ + DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */ + + dp->running = false; +} + +/* + This function is called to "start up" the interface. It may be called + multiple times, even when the hardware is already running. It will be + called whenever something "hardware oriented" changes and should leave + the hardware ready to send/receive packets. +*/ +static void +dp83902a_start(unsigned char * enaddr) +{ + dp83902a_priv_data_t *dp = &nic; + cyg_uint8 *base = dp->base; + int i; + + DEBUG_FUNCTION(); + + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + DP_OUT(base, DP_DCR, DP_DCR_INIT); + DP_OUT(base, DP_RBCH, 0); /* Remote byte count */ + DP_OUT(base, DP_RBCL, 0); + DP_OUT(base, DP_RCR, DP_RCR_MON); /* Accept no packets */ + DP_OUT(base, DP_TCR, DP_TCR_LOCAL); /* Transmitter [virtually] off */ + DP_OUT(base, DP_TPSR, dp->tx_buf1); /* Transmitter start page */ + dp->tx1 = dp->tx2 = 0; + dp->tx_next = dp->tx_buf1; + dp->tx_started = false; + DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */ + DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */ + DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */ + dp->rx_next = dp->rx_buf_start-1; + DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ + DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ + DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ + for (i = 0; i < ETHER_ADDR_LEN; i++) { + DP_OUT(base, DP_P1_PAR0+i, enaddr[i]); + } + /* Enable and start device */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */ + DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ + dp->running = true; +} + +/* + This routine is called to start the transmitter. It is split out from the + data handling routine so it may be called either when data becomes first + available or when an Tx interrupt occurs +*/ + +static void +dp83902a_start_xmit(int start_page, int len) +{ + dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic; + cyg_uint8 *base = dp->base; + + DEBUG_FUNCTION(); + +#if DEBUG & 1 + printf("Tx pkt %d len %d\n", start_page, len); + if (dp->tx_started) + printf("TX already started?!?\n"); +#endif + + DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE)); + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_TBCL, len & 0xFF); + DP_OUT(base, DP_TBCH, len >> 8); + DP_OUT(base, DP_TPSR, start_page); + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); + + dp->tx_started = true; +} + +/* + This routine is called to send data to the hardware. It is known a-priori + that there is free buffer space (dp->tx_next). +*/ +static void +dp83902a_send(unsigned char *data, int total_len, unsigned long key) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + int len, start_page, pkt_len, i, isr; +#if DEBUG & 4 + int dx; +#endif + + DEBUG_FUNCTION(); + + len = pkt_len = total_len; + if (pkt_len < IEEE_8023_MIN_FRAME) pkt_len = IEEE_8023_MIN_FRAME; + + start_page = dp->tx_next; + if (dp->tx_next == dp->tx_buf1) { + dp->tx1 = start_page; + dp->tx1_len = pkt_len; + dp->tx1_key = key; + dp->tx_next = dp->tx_buf2; + } else { + dp->tx2 = start_page; + dp->tx2_len = pkt_len; + dp->tx2_key = key; + dp->tx_next = dp->tx_buf1; + } + +#if DEBUG & 5 + printf("TX prep page %d len %d\n", start_page, pkt_len); +#endif + + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + { + /* Dummy read. The manual sez something slightly different, */ + /* but the code is extended a bit to do what Hitachi's monitor */ + /* does (i.e., also read data). */ + + cyg_uint16 tmp; + int len = 1; + + DP_OUT(base, DP_RSAL, 0x100-len); + DP_OUT(base, DP_RSAH, (start_page-1) & 0xff); + DP_OUT(base, DP_RBCL, len); + DP_OUT(base, DP_RBCH, 0); + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START); + DP_IN_DATA(dp->data, tmp); + } + +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA + /* Stall for a bit before continuing to work around random data */ + /* corruption problems on some platforms. */ + CYGACC_CALL_IF_DELAY_US(1); +#endif + + /* Send data to device buffer(s) */ + DP_OUT(base, DP_RSAL, 0); + DP_OUT(base, DP_RSAH, start_page); + DP_OUT(base, DP_RBCL, pkt_len & 0xFF); + DP_OUT(base, DP_RBCH, pkt_len >> 8); + DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START); + + /* Put data into buffer */ +#if DEBUG & 4 + printf(" sg buf %08lx len %08x\n ", (unsigned long) data, len); + dx = 0; +#endif + while (len > 0) { +#if DEBUG & 4 + printf(" %02x", *data); + if (0 == (++dx % 16)) printf("\n "); +#endif + DP_OUT_DATA(dp->data, *data++); + len--; + } +#if DEBUG & 4 + printf("\n"); +#endif + if (total_len < pkt_len) { +#if DEBUG & 4 + printf(" + %d bytes of padding\n", pkt_len - total_len); +#endif + /* Padding to 802.3 length was required */ + for (i = total_len; i < pkt_len;) { + i++; + DP_OUT_DATA(dp->data, 0); + } + } + +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA + /* After last data write, delay for a bit before accessing the */ + /* device again, or we may get random data corruption in the last */ + /* datum (on some platforms). */ + CYGACC_CALL_IF_DELAY_US(1); +#endif + + /* Wait for DMA to complete */ + do { + DP_IN(base, DP_ISR, isr); + } while ((isr & DP_ISR_RDC) == 0); + /* Then disable DMA */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + + /* Start transmit if not already going */ + if (!dp->tx_started) { + if (start_page == dp->tx1) { + dp->tx_int = 1; /* Expecting interrupt from BUF1 */ + } else { + dp->tx_int = 2; /* Expecting interrupt from BUF2 */ + } + dp83902a_start_xmit(start_page, pkt_len); + } +} + +/* + This function is called when a packet has been received. It's job is + to prepare to unload the packet from the hardware. Once the length of + the packet is known, the upper layer of the driver can be told. When + the upper layer is ready to unload the packet, the internal function + 'dp83902a_recv' will be called to actually fetch it from the hardware. +*/ +static void +dp83902a_RxEvent(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + unsigned char rsr; + unsigned char rcv_hdr[4]; + int i, len, pkt, cur; + + DEBUG_FUNCTION(); + + DP_IN(base, DP_RSR, rsr); + while (true) { + /* Read incoming packet header */ + DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START); + DP_IN(base, DP_P1_CURP, cur); + DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_IN(base, DP_BNDRY, pkt); + + pkt += 1; + if (pkt == dp->rx_buf_end) + pkt = dp->rx_buf_start; + + if (pkt == cur) { + break; + } + DP_OUT(base, DP_RBCL, sizeof(rcv_hdr)); + DP_OUT(base, DP_RBCH, 0); + DP_OUT(base, DP_RSAL, 0); + DP_OUT(base, DP_RSAH, pkt); + if (dp->rx_next == pkt) { + if (cur == dp->rx_buf_start) + DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); + else + DP_OUT(base, DP_BNDRY, cur-1); /* Update pointer */ + return; + } + dp->rx_next = pkt; + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA + CYGACC_CALL_IF_DELAY_US(10); +#endif + + for (i = 0; i < sizeof(rcv_hdr);) { + DP_IN_DATA(dp->data, rcv_hdr[i++]); + } + +#if DEBUG & 5 + printf("rx hdr %02x %02x %02x %02x\n", + rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]); +#endif + len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr); + uboot_push_packet_len(len); + if (rcv_hdr[1] == dp->rx_buf_start) + DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); + else + DP_OUT(base, DP_BNDRY, rcv_hdr[1]-1); /* Update pointer */ + } +} + +/* + This function is called as a result of the "eth_drv_recv()" call above. + It's job is to actually fetch data for a packet from the hardware once + memory buffers have been allocated for the packet. Note that the buffers + may come in pieces, using a scatter-gather list. This allows for more + efficient processing in the upper layers of the stack. +*/ +static void +dp83902a_recv(unsigned char *data, int len) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + int i, mlen; + cyg_uint8 saved_char = 0; + bool saved; +#if DEBUG & 4 + int dx; +#endif + + DEBUG_FUNCTION(); + +#if DEBUG & 5 + printf("Rx packet %d length %d\n", dp->rx_next, len); +#endif + + /* Read incoming packet data */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + DP_OUT(base, DP_RBCL, len & 0xFF); + DP_OUT(base, DP_RBCH, len >> 8); + DP_OUT(base, DP_RSAL, 4); /* Past header */ + DP_OUT(base, DP_RSAH, dp->rx_next); + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); +#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA + CYGACC_CALL_IF_DELAY_US(10); +#endif + + saved = false; + for (i = 0; i < 1; i++) { + if (data) { + mlen = len; +#if DEBUG & 4 + printf(" sg buf %08lx len %08x \n", (unsigned long) data, mlen); + dx = 0; +#endif + while (0 < mlen) { + /* Saved byte from previous loop? */ + if (saved) { + *data++ = saved_char; + mlen--; + saved = false; + continue; + } + + { + cyg_uint8 tmp; + DP_IN_DATA(dp->data, tmp); +#if DEBUG & 4 + printf(" %02x", tmp); + if (0 == (++dx % 16)) printf("\n "); +#endif + *data++ = tmp;; + mlen--; + } + } +#if DEBUG & 4 + printf("\n"); +#endif + } + } +} + +static void +dp83902a_TxEvent(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + unsigned char tsr; + unsigned long key; + + DEBUG_FUNCTION(); + + DP_IN(base, DP_TSR, tsr); + if (dp->tx_int == 1) { + key = dp->tx1_key; + dp->tx1 = 0; + } else { + key = dp->tx2_key; + dp->tx2 = 0; + } + /* Start next packet if one is ready */ + dp->tx_started = false; + if (dp->tx1) { + dp83902a_start_xmit(dp->tx1, dp->tx1_len); + dp->tx_int = 1; + } else if (dp->tx2) { + dp83902a_start_xmit(dp->tx2, dp->tx2_len); + dp->tx_int = 2; + } else { + dp->tx_int = 0; + } + /* Tell higher level we sent this packet */ + uboot_push_tx_done(key, 0); +} + +/* Read the tally counters to clear them. Called in response to a CNT */ +/* interrupt. */ +static void +dp83902a_ClearCounters(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + cyg_uint8 cnt1, cnt2, cnt3; + + DP_IN(base, DP_FER, cnt1); + DP_IN(base, DP_CER, cnt2); + DP_IN(base, DP_MISSED, cnt3); + DP_OUT(base, DP_ISR, DP_ISR_CNT); +} + +/* Deal with an overflow condition. This code follows the procedure set */ +/* out in section 7.0 of the datasheet. */ +static void +dp83902a_Overflow(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic; + cyg_uint8 *base = dp->base; + cyg_uint8 isr; + + /* Issue a stop command and wait 1.6ms for it to complete. */ + DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA); + CYGACC_CALL_IF_DELAY_US(1600); + + /* Clear the remote byte counter registers. */ + DP_OUT(base, DP_RBCL, 0); + DP_OUT(base, DP_RBCH, 0); + + /* Enter loopback mode while we clear the buffer. */ + DP_OUT(base, DP_TCR, DP_TCR_LOCAL); + DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA); + + /* Read in as many packets as we can and acknowledge any and receive */ + /* interrupts. Since the buffer has overflowed, a receive event of */ + /* some kind will have occured. */ + dp83902a_RxEvent(); + DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE); + + /* Clear the overflow condition and leave loopback mode. */ + DP_OUT(base, DP_ISR, DP_ISR_OFLW); + DP_OUT(base, DP_TCR, DP_TCR_NORMAL); + + /* If a transmit command was issued, but no transmit event has occured, */ + /* restart it here. */ + DP_IN(base, DP_ISR, isr); + if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) { + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); + } +} + +static void +dp83902a_poll(void) +{ + struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + cyg_uint8 *base = dp->base; + unsigned char isr; + + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START); + DP_IN(base, DP_ISR, isr); + while (0 != isr) { + /* The CNT interrupt triggers when the MSB of one of the error */ + /* counters is set. We don't much care about these counters, but */ + /* we should read their values to reset them. */ + if (isr & DP_ISR_CNT) { + dp83902a_ClearCounters(); + } + /* Check for overflow. It's a special case, since there's a */ + /* particular procedure that must be followed to get back into */ + /* a running state.a */ + if (isr & DP_ISR_OFLW) { + dp83902a_Overflow(); + } else { + /* Other kinds of interrupts can be acknowledged simply by */ + /* clearing the relevant bits of the ISR. Do that now, then */ + /* handle the interrupts we care about. */ + DP_OUT(base, DP_ISR, isr); /* Clear set bits */ + if (!dp->running) break; /* Is this necessary? */ + /* Check for tx_started on TX event since these may happen */ + /* spuriously it seems. */ + if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) { + dp83902a_TxEvent(); + } + if (isr & (DP_ISR_RxP|DP_ISR_RxE)) { + dp83902a_RxEvent(); + } + } + DP_IN(base, DP_ISR, isr); + } +} + +/* find prom (taken from pc_net_cs.c from Linux) */ + +#include "8390.h" + +typedef struct hw_info_t { + u_int offset; + u_char a0, a1, a2; + u_int flags; +} hw_info_t; + +#define DELAY_OUTPUT 0x01 +#define HAS_MISC_REG 0x02 +#define USE_BIG_BUF 0x04 +#define HAS_IBM_MISC 0x08 +#define IS_DL10019 0x10 +#define IS_DL10022 0x20 +#define HAS_MII 0x40 +#define USE_SHMEM 0x80 /* autodetected */ + +#define AM79C9XX_HOME_PHY 0x00006B90 /* HomePNA PHY */ +#define AM79C9XX_ETH_PHY 0x00006B70 /* 10baseT PHY */ +#define MII_PHYID_REV_MASK 0xfffffff0 +#define MII_PHYID_REG1 0x02 +#define MII_PHYID_REG2 0x03 + +static hw_info_t hw_info[] = { + { /* Accton EN2212 */ 0x0ff0, 0x00, 0x00, 0xe8, DELAY_OUTPUT }, + { /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 }, + { /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 }, + { /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94, + DELAY_OUTPUT | HAS_IBM_MISC }, + { /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 }, + { /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 }, + { /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 }, + { /* D-Link DE-650 */ 0x0040, 0x00, 0x80, 0xc8, 0 }, + { /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 }, + { /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 }, + { /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 }, + { /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 }, + { /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* IBM FME */ 0x0374, 0x00, 0x04, 0xac, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 }, + { /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 }, + { /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 }, + { /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 }, + { /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 }, + { /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 }, + { /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45, + HAS_MISC_REG | HAS_IBM_MISC }, + { /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 }, + { /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 }, + { /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 }, + { /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b, + DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF }, + { /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 }, + { /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 }, + { /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 }, + { /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 }, + { /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 } +}; + +#define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t)) + +static hw_info_t default_info = { 0, 0, 0, 0, 0 }; + +unsigned char dev_addr[6]; + +#define PCNET_CMD 0x00 +#define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */ +#define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */ +#define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */ + +unsigned long nic_base; + +static void pcnet_reset_8390(void) +{ + int i, r; + + PRINTK("nic base is %lx\n", nic_base); + +#if 1 + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); + n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD)); +#endif + n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD); + + n2k_outb(n2k_inb(nic_base + PCNET_RESET), PCNET_RESET); + + for (i = 0; i < 100; i++) { + if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0) + break; + PRINTK("got %x in reset\n", r); + my_udelay(100); + } + n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */ + + if (i == 100) + printf("pcnet_reset_8390() did not complete.\n"); +} /* pcnet_reset_8390 */ + +static hw_info_t * get_prom(void ) { + unsigned char prom[32]; + int i, j; + struct { + u_char value, offset; + } program_seq[] = { + {E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/ + {0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */ + {0x00, EN0_RCNTLO}, /* Clear the count regs. */ + {0x00, EN0_RCNTHI}, + {0x00, EN0_IMR}, /* Mask completion irq. */ + {0xFF, EN0_ISR}, + {E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */ + {E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */ + {32, EN0_RCNTLO}, + {0x00, EN0_RCNTHI}, + {0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */ + {0x00, EN0_RSARHI}, + {E8390_RREAD+E8390_START, E8390_CMD}, + }; + + PRINTK("trying to get MAC via prom reading\n"); + + pcnet_reset_8390(); + + mdelay(10); + + for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++) + n2k_outb(program_seq[i].value, program_seq[i].offset); + + PRINTK("PROM:"); + for (i = 0; i < 32; i++) { + prom[i] = n2k_inb(PCNET_DATAPORT); + PRINTK(" %02x", prom[i]); + } + PRINTK("\n"); + for (i = 0; i < NR_INFO; i++) { + if ((prom[0] == hw_info[i].a0) && + (prom[2] == hw_info[i].a1) && + (prom[4] == hw_info[i].a2)) { + PRINTK("matched board %d\n", i); + break; + } + } + if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) { + for (j = 0; j < 6; j++) + dev_addr[j] = prom[j<<1]; + PRINTK("on exit i is %d/%ld\n", i, NR_INFO); + PRINTK("MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + dev_addr[0],dev_addr[1],dev_addr[2],dev_addr[3],dev_addr[4],dev_addr[5]); + return (i < NR_INFO) ? hw_info+i : &default_info; + } + return NULL; +} + +/* U-boot specific routines */ + +#define NB 5 + +static unsigned char *pbuf = NULL; +static int plen[NB]; +static int nrx = 0; + +static int pkey = -1; + +void uboot_push_packet_len(int len) { + PRINTK("pushed len = %d, nrx = %d\n", len, nrx); + if (len>=2000) { + printf("NE2000: packet too big\n"); + return; + } + if (nrx >= NB) { + printf("losing packets in rx\n"); + return; + } + plen[nrx] = len; + dp83902a_recv(&pbuf[nrx*2000], len); + nrx++; +} + +void uboot_push_tx_done(int key, int val) { + PRINTK("pushed key = %d\n", key); + pkey = key; +} + +int eth_init(bd_t *bd) { + static hw_info_t * r; + char ethaddr[20]; + + PRINTK("### eth_init\n"); + + if (!pbuf) { + pbuf = malloc(NB*2000); + if (!pbuf) { + printf("Cannot allocate rx buffers\n"); + return -1; + } + } + +#ifdef CONFIG_DRIVER_NE2000_CCR + { + volatile unsigned char *p = (volatile unsigned char *) CONFIG_DRIVER_NE2000_CCR; + + PRINTK("CCR before is %x\n", *p); + *p = CONFIG_DRIVER_NE2000_VAL; + PRINTK("CCR after is %x\n", *p); + } +#endif + + nic_base = CONFIG_DRIVER_NE2000_BASE; + nic.base = (cyg_uint8 *) CONFIG_DRIVER_NE2000_BASE; + + r = get_prom(); + if (!r) + return -1; + + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + dev_addr[0], dev_addr[1], + dev_addr[2], dev_addr[3], + dev_addr[4], dev_addr[5]) ; + PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr); + setenv ("ethaddr", ethaddr); + + +#define DP_DATA 0x10 + nic.data = nic.base + DP_DATA; + nic.tx_buf1 = 0x40; + nic.tx_buf2 = 0x48; + nic.rx_buf_start = 0x50; + nic.rx_buf_end = 0x80; + + if (dp83902a_init() == false) + return -1; + dp83902a_start(dev_addr); + return 0; +} + +void eth_halt() { + + PRINTK("### eth_halt\n"); + + dp83902a_stop(); +} + +int eth_rx() { + int j, tmo; + + PRINTK("### eth_rx\n"); + + tmo = get_timer (0) + TOUT * CFG_HZ; + while(1) { + dp83902a_poll(); + if (nrx > 0) { + for(j=0; j= tmo) { + printf("timeout during rx\n"); + return 0; + } + } + return 0; +} + +int eth_send(volatile void *packet, int length) { + int tmo; + + PRINTK("### eth_send\n"); + + pkey = -1; + + dp83902a_send((unsigned char *) packet, length, 666); + tmo = get_timer (0) + TOUT * CFG_HZ; + while(1) { + dp83902a_poll(); + if (pkey != -1) { + PRINTK("Packet sucesfully sent\n"); + return 0; + } + if (get_timer (0) >= tmo) { + printf("transmission error (timoeut)\n"); + return 0; + } + + } + return 0; +} + +#endif diff --git a/drivers/ne2000.h b/drivers/ne2000.h new file mode 100644 index 000000000..2955533d7 --- /dev/null +++ b/drivers/ne2000.h @@ -0,0 +1,279 @@ +/* +Ported to U-Boot by Christian Pellegrin + +Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and +eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world +are GPL, so this is, of course, GPL. + + +========================================================================== + + dev/dp83902a.h + + National Semiconductor DP83902a ethernet chip + +========================================================================== +####ECOSGPLCOPYRIGHTBEGIN#### + ------------------------------------------- + This file is part of eCos, the Embedded Configurable Operating System. + Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + + eCos is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 or (at your option) any later version. + + eCos is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License along + with eCos; if not, write to the Free Software Foundation, Inc., + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + + As a special exception, if other files instantiate templates or use macros + or inline functions from this file, or you compile this file and link it + with other works to produce a work based on this file, this file does not + by itself cause the resulting work to be covered by the GNU General Public + License. However the source code for this file must still be made available + in accordance with section (3) of the GNU General Public License. + + This exception does not invalidate any other reasons why a work based on + this file might be covered by the GNU General Public License. + + Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. + at http://sources.redhat.com/ecos/ecos-license/ */ + ------------------------------------------- +####ECOSGPLCOPYRIGHTEND#### +####BSDCOPYRIGHTBEGIN#### + + ------------------------------------------- + + Portions of this software may have been derived from OpenBSD or other sources, + and are covered by the appropriate copyright disclaimers included herein. + + ------------------------------------------- + +####BSDCOPYRIGHTEND#### +========================================================================== +#####DESCRIPTIONBEGIN#### + + Author(s): gthomas + Contributors: gthomas, jskov + Date: 2001-06-13 + Purpose: + Description: + +####DESCRIPTIONEND#### + +========================================================================== + +*/ + +/* + ------------------------------------------------------------------------ + Macros for accessing DP registers + These can be overridden by the platform header +*/ + +#define DP_IN(_b_, _o_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_)+(_o_))) +#define DP_OUT(_b_, _o_, _d_) *( (volatile unsigned char *) ((_b_)+(_o_))) = (_d_) + +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_))) +#define DP_OUT_DATA(_b_, _d_) *( (volatile unsigned char *) ((_b_))) = (_d_) + + +/* here is all the data */ + +#define cyg_uint8 unsigned char +#define cyg_uint16 unsigned short +#define bool int + +#define false 0 +#define true 1 + +#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1 +#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X) + +typedef struct dp83902a_priv_data { + cyg_uint8* base; + cyg_uint8* data; + cyg_uint8* reset; + int tx_next; /* First free Tx page */ + int tx_int; /* Expecting interrupt from this buffer */ + int rx_next; /* First free Rx page */ + int tx1, tx2; /* Page numbers for Tx buffers */ + unsigned long tx1_key, tx2_key; /* Used to ack when packet sent */ + int tx1_len, tx2_len; + bool tx_started, running, hardwired_esa; + cyg_uint8 esa[6]; + void* plf_priv; + + /* Buffer allocation */ + int tx_buf1, tx_buf2; + int rx_buf_start, rx_buf_end; +} dp83902a_priv_data_t; + +/* + ------------------------------------------------------------------------ + Some forward declarations +*/ +static void dp83902a_poll(void); + +/* ------------------------------------------------------------------------ */ +/* Register offsets */ + +#define DP_CR 0x00 +#define DP_CLDA0 0x01 +#define DP_PSTART 0x01 /* write */ +#define DP_CLDA1 0x02 +#define DP_PSTOP 0x02 /* write */ +#define DP_BNDRY 0x03 +#define DP_TSR 0x04 +#define DP_TPSR 0x04 /* write */ +#define DP_NCR 0x05 +#define DP_TBCL 0x05 /* write */ +#define DP_FIFO 0x06 +#define DP_TBCH 0x06 /* write */ +#define DP_ISR 0x07 +#define DP_CRDA0 0x08 +#define DP_RSAL 0x08 /* write */ +#define DP_CRDA1 0x09 +#define DP_RSAH 0x09 /* write */ +#define DP_RBCL 0x0a /* write */ +#define DP_RBCH 0x0b /* write */ +#define DP_RSR 0x0c +#define DP_RCR 0x0c /* write */ +#define DP_FER 0x0d +#define DP_TCR 0x0d /* write */ +#define DP_CER 0x0e +#define DP_DCR 0x0e /* write */ +#define DP_MISSED 0x0f +#define DP_IMR 0x0f /* write */ +#define DP_DATAPORT 0x10 /* "eprom" data port */ + +#define DP_P1_CR 0x00 +#define DP_P1_PAR0 0x01 +#define DP_P1_PAR1 0x02 +#define DP_P1_PAR2 0x03 +#define DP_P1_PAR3 0x04 +#define DP_P1_PAR4 0x05 +#define DP_P1_PAR5 0x06 +#define DP_P1_CURP 0x07 +#define DP_P1_MAR0 0x08 +#define DP_P1_MAR1 0x09 +#define DP_P1_MAR2 0x0a +#define DP_P1_MAR3 0x0b +#define DP_P1_MAR4 0x0c +#define DP_P1_MAR5 0x0d +#define DP_P1_MAR6 0x0e +#define DP_P1_MAR7 0x0f + +#define DP_P2_CR 0x00 +#define DP_P2_PSTART 0x01 +#define DP_P2_CLDA0 0x01 /* write */ +#define DP_P2_PSTOP 0x02 +#define DP_P2_CLDA1 0x02 /* write */ +#define DP_P2_RNPP 0x03 +#define DP_P2_TPSR 0x04 +#define DP_P2_LNPP 0x05 +#define DP_P2_ACH 0x06 +#define DP_P2_ACL 0x07 +#define DP_P2_RCR 0x0c +#define DP_P2_TCR 0x0d +#define DP_P2_DCR 0x0e +#define DP_P2_IMR 0x0f + +/* Command register - common to all pages */ + +#define DP_CR_STOP 0x01 /* Stop: software reset */ +#define DP_CR_START 0x02 /* Start: initialize device */ +#define DP_CR_TXPKT 0x04 /* Transmit packet */ +#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */ +#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */ +#define DP_CR_SEND 0x18 /* Send packet */ +#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */ +#define DP_CR_PAGE0 0x00 /* Page select */ +#define DP_CR_PAGE1 0x40 +#define DP_CR_PAGE2 0x80 +#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */ + +/* Data configuration register */ + +#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */ +#define DP_DCR_BOS 0x02 /* 1=Little Endian */ +#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */ +#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */ +#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */ +#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */ +#define DP_DCR_FIFO_2 0x20 +#define DP_DCR_FIFO_4 0x40 +#define DP_DCR_FIFO_6 0x60 + +#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4) + +/* Interrupt status register */ + +#define DP_ISR_RxP 0x01 /* Packet received */ +#define DP_ISR_TxP 0x02 /* Packet transmitted */ +#define DP_ISR_RxE 0x04 /* Receive error */ +#define DP_ISR_TxE 0x08 /* Transmit error */ +#define DP_ISR_OFLW 0x10 /* Receive overflow */ +#define DP_ISR_CNT 0x20 /* Tally counters need emptying */ +#define DP_ISR_RDC 0x40 /* Remote DMA complete */ +#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */ + +/* Interrupt mask register */ + +#define DP_IMR_RxP 0x01 /* Packet received */ +#define DP_IMR_TxP 0x02 /* Packet transmitted */ +#define DP_IMR_RxE 0x04 /* Receive error */ +#define DP_IMR_TxE 0x08 /* Transmit error */ +#define DP_IMR_OFLW 0x10 /* Receive overflow */ +#define DP_IMR_CNT 0x20 /* Tall counters need emptying */ +#define DP_IMR_RDC 0x40 /* Remote DMA complete */ + +#define DP_IMR_All 0x3F /* Everything but remote DMA */ + +/* Receiver control register */ + +#define DP_RCR_SEP 0x01 /* Save bad(error) packets */ +#define DP_RCR_AR 0x02 /* Accept runt packets */ +#define DP_RCR_AB 0x04 /* Accept broadcast packets */ +#define DP_RCR_AM 0x08 /* Accept multicast packets */ +#define DP_RCR_PROM 0x10 /* Promiscuous mode */ +#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */ + +/* Receiver status register */ + +#define DP_RSR_RxP 0x01 /* Packet received */ +#define DP_RSR_CRC 0x02 /* CRC error */ +#define DP_RSR_FRAME 0x04 /* Framing error */ +#define DP_RSR_FO 0x08 /* FIFO overrun */ +#define DP_RSR_MISS 0x10 /* Missed packet */ +#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */ +#define DP_RSR_DIS 0x40 /* Receiver disabled */ +#define DP_RSR_DFR 0x80 /* Receiver processing deferred */ + +/* Transmitter control register */ + +#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */ +#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */ +#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */ +#define DP_TCR_INLOOP 0x04 /* Full internal loopback */ +#define DP_TCR_OUTLOOP 0x08 /* External loopback */ +#define DP_TCR_ATD 0x10 /* Auto transmit disable */ +#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */ + +/* Transmit status register */ + +#define DP_TSR_TxP 0x01 /* Packet transmitted */ +#define DP_TSR_COL 0x04 /* Collision (at least one) */ +#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */ +#define DP_TSR_CRS 0x10 /* Lost carrier */ +#define DP_TSR_FU 0x20 /* FIFO underrun */ +#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */ +#define DP_TSR_OWC 0x80 /* Collision outside normal window */ + +#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ +#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ diff --git a/drivers/netarm_eth.c b/drivers/netarm_eth.c new file mode 100644 index 000000000..89b3a8394 --- /dev/null +++ b/drivers/netarm_eth.c @@ -0,0 +1,360 @@ +/* + * Copyright (C) 2004 IMMS gGmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * author(s): Thomas Elste, + * (some parts derived from uCLinux Netarm Ethernet Driver) + */ + + +#include + +#ifdef CONFIG_DRIVER_NETARMETH +#include +#include +#include "netarm_eth.h" +#include + + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +static int na_mii_poll_busy (void); + +static void na_get_mac_addr (void) +{ + unsigned short p[3]; + char *m_addr; + char ethaddr[20]; + + m_addr = (char *) p; + + p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1); + p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2); + p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3); + + sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", + m_addr[0], m_addr[1], + m_addr[2], m_addr[3], m_addr[4], m_addr[5]); + + printf ("HW-MAC Address: %s\n", ethaddr); + + /* set env, todo: check if already an adress is set */ + setenv ("ethaddr", ethaddr); +} + + +static void na_mii_write (int reg, int value) +{ + int mii_addr; + + /* Select register */ + mii_addr = CFG_ETH_PHY_ADDR + reg; + SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); + /* Write value */ + SET_EADDR (NETARM_ETH_MII_WRITE, value); + na_mii_poll_busy (); +} + +static unsigned int na_mii_read (int reg) +{ + int mii_addr, val; + + /* Select register */ + mii_addr = CFG_ETH_PHY_ADDR + reg; + SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr); + /* do one management cycle */ + SET_EADDR (NETARM_ETH_MII_CMD, + GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT); + na_mii_poll_busy (); + /* Return read value */ + val = GET_EADDR (NETARM_ETH_MII_READ); + return val; +} + +static int na_mii_poll_busy (void) +{ + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + while (get_timer_masked () < NA_MII_POLL_BUSY_DELAY) { + if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) { + return 1; + } + } + printf ("na_mii_busy timeout\n"); + return (0); +} + +static int na_mii_identify_phy (void) +{ + int id_reg_a = 0; + + /* get phy id register */ + id_reg_a = na_mii_read (MII_PHY_ID); + + if (id_reg_a == 0x0043) { + /* This must be an Enable or a Lucent LU3X31 PHY chip */ + return 1; + } else if (id_reg_a == 0x0013) { + /* it is an Intel LXT971A */ + return 1; + } + return (0); +} + +static int na_mii_negotiate (void) +{ + int i = 0; + + /* Enable auto-negotiation */ + na_mii_write (MII_PHY_AUTONEGADV, 0x01e1); + /* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */ + /* Restart auto-negotiation */ + na_mii_write (MII_PHY_CONTROL, 0x1200); + + /* status register is 0xffff after setting the autoneg restart bit */ + while (na_mii_read (MII_PHY_STATUS) == 0xffff) { + i++; + } + + /* na_mii_read uses the timer already, so we can't use it again for + timeout checking. + Instead we just try some times. + */ + for (i = 0; i < 40000; i++) { + if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) { + return 0; + } + } + /* + printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS)); + */ + return (1); +} + +static unsigned int na_mii_check_speed (void) +{ + unsigned int status; + + /* Read Status register */ + status = na_mii_read (MII_PHY_STATUS); + /* Check link status. If 0, default to 100 Mbps. */ + if ((status & 0x0004) == 0) { + printf ("*Warning* no link detected, set default speed to 100Mbs\n"); + return 1; + } else { + if ((na_mii_read (17) & 0x4000) != 0) { + printf ("100Mbs link detected\n"); + return 1; + } else { + printf ("10Mbs link detected\n"); + return 0; + } + } + return 0; +} + +static int reset_eth (void) +{ + int pt; + + na_get_mac_addr (); + pt = na_mii_identify_phy (); + + /* reset the phy */ + na_mii_write (MII_PHY_CONTROL, 0x8000); + reset_timer_masked (); + while (get_timer_masked () < NA_MII_NEGOTIATE_DELAY) { + if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) { + break; + } + } + if (get_timer_masked () >= NA_MII_NEGOTIATE_DELAY) + printf ("phy reset timeout\n"); + + /* set the PCS reg */ + SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M | + NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR); + + na_mii_negotiate (); + na_mii_check_speed (); + + /* Delay 10 millisecond. (Maybe this should be 1 second.) */ + udelay (10000); + + /* Turn receive on. + Enable statistics register autozero on read. + Do not insert MAC address on transmit. + Do not enable special test modes. */ + SET_EADDR (NETARM_ETH_STL_CFG, + (NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN)); + + /* Set the inter-packet gap delay to 0.96us for MII. + The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG + Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG + Gap Timer Register should be set to 0x00000C12 for the MII PHY. */ + SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15); + SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12); + + /* Add CRC to end of packets. + Pad packets to minimum length of 64 bytes. + Allow unlimited length transmit packets. + Receive all broadcast packets. + NOTE: Multicast addressing is NOT enabled here currently. */ + SET_EADDR (NETARM_ETH_MAC_CFG, + (NETARM_ETH_MACC_CRCEN | + NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN)); + SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD); + + /* enable fifos */ + SET_EADDR (NETARM_ETH_GEN_CTRL, + (NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX)); + + return (0); +} + + +extern int eth_init (bd_t * bd) +{ + reset_eth (); + return 0; +} + +extern void eth_halt (void) +{ + SET_EADDR (NETARM_ETH_GEN_CTRL, 0); +} + +/* Get a data block via Ethernet */ +extern int eth_rx (void) +{ + int i; + unsigned short rxlen; + unsigned int *addr; + unsigned int rxstatus, lastrxlen; + char *pa; + + /* RXBR is 1, data block was received */ + if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0) + return 0; + + /* get status register and the length of received block */ + rxstatus = GET_EADDR (NETARM_ETH_RX_STAT); + rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16; + + if (rxlen == 0) + return 0; + + /* clear RXBR to make fifo available */ + SET_EADDR (NETARM_ETH_GEN_STAT, + GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR); + + /* clear TXBC to make fifo available */ + /* According to NETARM50 data manual you just have to clear + RXBR but that has no effect. Only after clearing TXBC the + Fifo becomes readable. */ + SET_EADDR (NETARM_ETH_GEN_STAT, + GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC); + + addr = (unsigned int *) NetRxPackets[0]; + pa = (char *) NetRxPackets[0]; + + /* read the fifo */ + for (i = 0; i < rxlen / 4; i++) { + *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); + addr++; + } + + if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) { + /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */ + lastrxlen = + (GET_EADDR (NETARM_ETH_GEN_STAT) & + NETARM_ETH_GST_RXFDB) >> 28; + *addr = GET_EADDR (NETARM_ETH_FIFO_DAT1); + switch (lastrxlen) { + case 1: + *addr &= 0xff000000; + break; + case 2: + *addr &= 0xffff0000; + break; + case 3: + *addr &= 0xffffff00; + break; + } + } + + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], rxlen); + + return rxlen; +} + +/* Send a data block via Ethernet. */ +extern int eth_send (volatile void *packet, int length) +{ + int i, length32; + char *pa; + unsigned int *pa32, lastp = 0, rest; + + pa = (char *) packet; + pa32 = (unsigned int *) packet; + length32 = length / 4; + rest = length % 4; + + /* make sure there's no garbage in the last word */ + switch (rest) { + case 0: + lastp = pa32[length32]; + length32--; + break; + case 1: + lastp = pa32[length32] & 0x000000ff; + break; + case 2: + lastp = pa32[length32] & 0x0000ffff; + break; + case 3: + lastp = pa32[length32] & 0x00ffffff; + break; + } + + /* write to the fifo */ + for (i = 0; i < length32; i++) + SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]); + + /* the last word is written to an extra register, this + starts the transmission */ + SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp); + + /* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission + went fine. But we can't use the timer for a timeout loop because + of it is used already in upper layers. So we just try some times. */ + i = 0; + while (i < 50000) { + if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK) + == NETARM_ETH_TXSTAT_TXOK) + return 0; + i++; + } + + printf ("eth_send timeout\n"); + return 1; +} + +#endif /* COMMANDS & CFG_NET */ + +#endif /* CONFIG_DRIVER_NETARMETH */ diff --git a/drivers/netarm_eth.h b/drivers/netarm_eth.h new file mode 100644 index 000000000..8edab82da --- /dev/null +++ b/drivers/netarm_eth.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2003 IMMS gGmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * author(s): Thomas Elste, + */ + +#include +#include + +#ifdef CONFIG_DRIVER_NETARMETH + +#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val +#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE)) + +#define NA_MII_POLL_BUSY_DELAY 900 + +/* MII negotiation timeout value + 500 jiffies = 5 seconds */ +#define NA_MII_NEGOTIATE_DELAY 30 + +/* Registers in the physical layer chip */ +#define MII_PHY_CONTROL 0 +#define MII_PHY_STATUS 1 +#define MII_PHY_ID 2 +#define MII_PHY_AUTONEGADV 4 + +#endif /* CONFIG_DRIVER_NETARMETH */ diff --git a/drivers/netconsole.c b/drivers/netconsole.c new file mode 100644 index 000000000..69089f92c --- /dev/null +++ b/drivers/netconsole.c @@ -0,0 +1,267 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_NETCONSOLE + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static char input_buffer[512]; +static int input_size = 0; /* char count in input buffer */ +static int input_offset = 0; /* offset to valid chars in input buffer */ +static int input_recursion = 0; +static int output_recursion = 0; +static int net_timeout; +static uchar nc_ether[6]; /* server enet address */ +static IPaddr_t nc_ip; /* server ip */ +static short nc_port; /* source/target port */ +static const char *output_packet; /* used by first send udp */ +static int output_packet_len = 0; + +static void nc_wait_arp_handler (uchar * pkt, unsigned dest, unsigned src, + unsigned len) +{ + NetState = NETLOOP_SUCCESS; /* got arp reply - quit net loop */ +} + +static void nc_handler (uchar * pkt, unsigned dest, unsigned src, + unsigned len) +{ + if (input_size) + NetState = NETLOOP_SUCCESS; /* got input - quit net loop */ +} + +static void nc_timeout (void) +{ + NetState = NETLOOP_SUCCESS; +} + +void NcStart (void) +{ + if (!output_packet_len || memcmp (nc_ether, NetEtherNullAddr, 6)) { + /* going to check for input packet */ + NetSetHandler (nc_handler); + NetSetTimeout (net_timeout, nc_timeout); + } else { + /* send arp request */ + uchar *pkt; + NetSetHandler (nc_wait_arp_handler); + pkt = (uchar *) NetTxPacket + NetEthHdrSize () + IP_HDR_SIZE; + memcpy (pkt, output_packet, output_packet_len); + NetSendUDPPacket (nc_ether, nc_ip, nc_port, nc_port, output_packet_len); + } +} + +int nc_input_packet (uchar * pkt, unsigned dest, unsigned src, unsigned len) +{ + int end, chunk; + + if (dest != nc_port || !len) + return 0; /* not for us */ + + if (input_size == sizeof input_buffer) + return 1; /* no space */ + if (len > sizeof input_buffer - input_size) + len = sizeof input_buffer - input_size; + + end = input_offset + input_size; + if (end > sizeof input_buffer) + end -= sizeof input_buffer; + + chunk = len; + if (end + len > sizeof input_buffer) { + chunk = sizeof input_buffer - end; + memcpy(input_buffer, pkt + chunk, len - chunk); + } + memcpy (input_buffer + end, pkt, chunk); + + input_size += len; + + return 1; +} + +static void nc_send_packet (const char *buf, int len) +{ + struct eth_device *eth; + int inited = 0; + uchar *pkt; + uchar *ether; + IPaddr_t ip; + + if ((eth = eth_get_dev ()) == NULL) { + return; + } + + if (!memcmp (nc_ether, NetEtherNullAddr, 6)) { + if (eth->state == ETH_STATE_ACTIVE) + return; /* inside net loop */ + output_packet = buf; + output_packet_len = len; + NetLoop (NETCONS); /* wait for arp reply and send packet */ + output_packet_len = 0; + return; + } + + if (eth->state != ETH_STATE_ACTIVE) { + if (eth_init (gd->bd) < 0) + return; + inited = 1; + } + pkt = (uchar *) NetTxPacket + NetEthHdrSize () + IP_HDR_SIZE; + memcpy (pkt, buf, len); + ether = nc_ether; + ip = nc_ip; + NetSendUDPPacket (ether, ip, nc_port, nc_port, len); + + if (inited) + eth_halt (); +} + +int nc_start (void) +{ + int netmask, our_ip; + + nc_port = 6666; /* default port */ + + if (getenv ("ncip")) { + char *p; + + nc_ip = getenv_IPaddr ("ncip"); + if (!nc_ip) + return -1; /* ncip is 0.0.0.0 */ + if ((p = strchr (getenv ("ncip"), ':')) != NULL) + nc_port = simple_strtoul (p + 1, NULL, 10); + } else + nc_ip = ~0; /* ncip is not set */ + + our_ip = getenv_IPaddr ("ipaddr"); + netmask = getenv_IPaddr ("netmask"); + + if (nc_ip == ~0 || /* 255.255.255.255 */ + ((netmask & our_ip) == (netmask & nc_ip) && /* on the same net */ + (netmask | nc_ip) == ~0)) /* broadcast to our net */ + memset (nc_ether, 0xff, sizeof nc_ether); + else + memset (nc_ether, 0, sizeof nc_ether); /* force arp request */ + + return 0; +} + +void nc_putc (char c) +{ + if (output_recursion) + return; + output_recursion = 1; + + nc_send_packet (&c, 1); + + output_recursion = 0; +} + +void nc_puts (const char *s) +{ + int len; + + if (output_recursion) + return; + output_recursion = 1; + + if ((len = strlen (s)) > 512) + len = 512; + + nc_send_packet (s, len); + + output_recursion = 0; +} + +int nc_getc (void) +{ + uchar c; + + input_recursion = 1; + + net_timeout = 0; /* no timeout */ + while (!input_size) + NetLoop (NETCONS); + + input_recursion = 0; + + c = input_buffer[input_offset++]; + + if (input_offset >= sizeof input_buffer) + input_offset -= sizeof input_buffer; + input_size--; + + return c; +} + +int nc_tstc (void) +{ + struct eth_device *eth; + + if (input_recursion) + return 0; + + if (input_size) + return 1; + + eth = eth_get_dev (); + if (eth && eth->state == ETH_STATE_ACTIVE) + return 0; /* inside net loop */ + + input_recursion = 1; + + net_timeout = 1; + NetLoop (NETCONS); /* kind of poll */ + + input_recursion = 0; + + return input_size != 0; +} + +int drv_nc_init (void) +{ + device_t dev; + int rc; + + memset (&dev, 0, sizeof (dev)); + + strcpy (dev.name, "nc"); + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.start = nc_start; + dev.putc = nc_putc; + dev.puts = nc_puts; + dev.getc = nc_getc; + dev.tstc = nc_tstc; + + rc = device_register (&dev); + + return (rc == 0) ? 1 : rc; +} + +#endif /* CONFIG_NETCONSOLE */ diff --git a/drivers/nicext.h b/drivers/nicext.h new file mode 100644 index 000000000..4074972c0 --- /dev/null +++ b/drivers/nicext.h @@ -0,0 +1,109 @@ +/**************************************************************************** + * Copyright(c) 2000-2001 Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + * + * Name: nicext.h + * + * Description: Broadcom Network Interface Card Extension (NICE) is an + * extension to Linux NET device kernel mode drivers. + * NICE is designed to provide additional functionalities, + * such as receive packet intercept. To support Broadcom NICE, + * the network device driver can be modified by adding an + * device ioctl handler and by indicating receiving packets + * to the NICE receive handler. Broadcom NICE will only be + * enabled by a NICE-aware intermediate driver, such as + * Broadcom Advanced Server Program Driver (BASP). When NICE + * is not enabled, the modified network device drivers + * functions exactly as other non-NICE aware drivers. + * + * Author: Frankie Fan + * + * Created: September 17, 2000 + * + ****************************************************************************/ +#ifndef _nicext_h_ +#define _nicext_h_ + +/* + * ioctl for NICE + */ +#define SIOCNICE SIOCDEVPRIVATE+7 + +/* + * SIOCNICE: + * + * The following structure needs to be less than IFNAMSIZ (16 bytes) because + * we're overloading ifreq.ifr_ifru. + * + * If 16 bytes is not enough, we should consider relaxing this because + * this is no field after ifr_ifru in the ifreq structure. But we may + * run into future compatiability problem in case of changing struct ifreq. + */ +struct nice_req +{ + __u32 cmd; + + union + { +#ifdef __KERNEL__ + /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */ + struct + { + void (*nrqus1_rx)( struct sk_buff*, void* ); + void* nrqus1_ctx; + } nrqu_nrqus1; + + /* cmd = NICE_CMD_QUERY_SUPPORT */ + struct + { + __u32 nrqus2_magic; + __u32 nrqus2_support_rx:1; + __u32 nrqus2_support_vlan:1; + __u32 nrqus2_support_get_speed:1; + } nrqu_nrqus2; +#endif + + /* cmd = NICE_CMD_GET_SPEED */ + struct + { + unsigned int nrqus3_speed; /* 0 if link is down, */ + /* otherwise speed in Mbps */ + } nrqu_nrqus3; + + /* cmd = NICE_CMD_BLINK_LED */ + struct + { + unsigned int nrqus4_blink_time; /* blink duration in seconds */ + } nrqu_nrqus4; + + } nrq_nrqu; +}; + +#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx +#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx +#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx +#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic +#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan +#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed +#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed +#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time + +/* + * magic constants + */ +#define NICE_REQUESTOR_MAGIC 0x4543494E /* NICE in ascii */ +#define NICE_DEVICE_MAGIC 0x4E494345 /* ECIN in ascii */ + +/* + * command field + */ +#define NICE_CMD_QUERY_SUPPORT 0x00000001 +#define NICE_CMD_SET_RX 0x00000002 +#define NICE_CMD_GET_RX 0x00000003 +#define NICE_CMD_GET_SPEED 0x00000004 +#define NICE_CMD_BLINK_LED 0x00000005 + +#endif /* _nicext_h_ */ diff --git a/drivers/ns16550.c b/drivers/ns16550.c new file mode 100644 index 000000000..5646fc6a3 --- /dev/null +++ b/drivers/ns16550.c @@ -0,0 +1,87 @@ +/* + * This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * COM1 NS16550 support + * originally from linux source (arch/ppc/boot/ns16550.c) + * modified to use CFG_ISA_MEM and new defines + */ + +#include + +#ifdef CFG_NS16550 + +#include + +#define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ +#define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ +#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ + +void NS16550_init (NS16550_t com_port, int baud_divisor) +{ + com_port->ier = 0x00; +#if defined(CONFIG_OMAP) && !defined(CONFIG_3430ZOOM2) + com_port->mdr1 = 0x7; /* mode select reset TL16C750*/ +#endif + +#if defined(CONFIG_3430ZOOM2) + /* On Zoom2 board Set pre-scalar to 1 + * CLKSEL is GND => MCR[7] is 1 => preslr is 4 + * So change the prescl to 1 + */ + com_port->lcr = 0xBF; + com_port->fcr |= 0x10; + com_port->mcr &= 0x7F; +#endif + com_port->lcr = LCR_BKSE | LCRVAL; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; + +#if defined(CONFIG_OMAP) && !defined(CONFIG_3430ZOOM2) +#if defined(CONFIG_APTIX) + com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */ +#else + com_port->mdr1 = 0; /* /16 is proper to hit 115200 with 48MHz */ +#endif +#endif +} + +void NS16550_reinit (NS16550_t com_port, int baud_divisor) +{ + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; +} + +void NS16550_putc (NS16550_t com_port, char c) +{ + while ((com_port->lsr & LSR_THRE) == 0); + com_port->thr = c; +} + +char NS16550_getc (NS16550_t com_port) +{ + while ((com_port->lsr & LSR_DR) == 0) { +#ifdef CONFIG_USB_TTY + extern void usbtty_poll(void); + usbtty_poll(); +#endif + } + return (com_port->rbr); +} + +int NS16550_tstc (NS16550_t com_port) +{ + return ((com_port->lsr & LSR_DR) != 0); +} + +#endif diff --git a/drivers/ns7520_eth.c b/drivers/ns7520_eth.c new file mode 100644 index 000000000..a5a20dfd7 --- /dev/null +++ b/drivers/ns7520_eth.c @@ -0,0 +1,859 @@ +/*********************************************************************** + * + * Copyright (C) 2005 by Videon Central, Inc. + * + * $Id$ + * @Author: Arthur Shipkowski + * @Descr: Ethernet driver for the NS7520. Uses polled Ethernet, like + * the older netarmeth driver. Note that attempting to filter + * broadcast and multicast out in the SAFR register will cause + * bad things due to released errata. + * @References: [1] NS7520 Hardware Reference, December 2003 + * [2] Intel LXT971 Datasheet #249414 Rev. 02 + * + ***********************************************************************/ + +#include + +#if defined(CONFIG_DRIVER_NS7520_ETHERNET) + +#include /* NetSendPacket */ +#include +#include + +#include "ns7520_eth.h" /* for Ethernet and PHY */ + +/** + * Send an error message to the terminal. + */ +#define ERROR(x) \ +do { \ + char *__foo = strrchr(__FILE__, '/'); \ + \ + printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \ + __LINE__, __FUNCTION__); \ + printf x; printf("\n"); \ +} while (0); + +/* some definition to make transistion to linux easier */ + +#define NS7520_DRIVER_NAME "eth" +#define KERN_WARNING "Warning:" +#define KERN_ERR "Error:" +#define KERN_INFO "Info:" + +#if 1 +# define DEBUG +#endif + +#ifdef DEBUG +# define printk printf + +# define DEBUG_INIT 0x0001 +# define DEBUG_MINOR 0x0002 +# define DEBUG_RX 0x0004 +# define DEBUG_TX 0x0008 +# define DEBUG_INT 0x0010 +# define DEBUG_POLL 0x0020 +# define DEBUG_LINK 0x0040 +# define DEBUG_MII 0x0100 +# define DEBUG_MII_LOW 0x0200 +# define DEBUG_MEM 0x0400 +# define DEBUG_ERROR 0x4000 +# define DEBUG_ERROR_CRIT 0x8000 + +static int nDebugLvl = DEBUG_ERROR_CRIT; + +# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \ + printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 ) +# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \ + printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 ) +# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\ + printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 ) +# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\ + printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0) +# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \ + printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0); +# define ASSERT( expr, func ) if( !( expr ) ) { \ + printf( "Assertion failed! %s:line %d %s\n", \ + (int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \ + func } +#else /* DEBUG */ +# define printk(...) +# define DEBUG_ARGS0( FLG, a0 ) +# define DEBUG_ARGS1( FLG, a0, a1 ) +# define DEBUG_ARGS2( FLG, a0, a1, a2 ) +# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) +# define DEBUG_FN( n ) +# define ASSERT(expr, func) +#endif /* DEBUG */ + +#define NS7520_MII_NEG_DELAY (5*CFG_HZ) /* in s */ +#define TX_TIMEOUT (5*CFG_HZ) /* in s */ +#define RX_STALL_WORKAROUND_CNT 100 + +static int ns7520_eth_reset(void); + +static void ns7520_link_auto_negotiate(void); +static void ns7520_link_update_egcr(void); +static void ns7520_link_print_changed(void); + +/* the PHY stuff */ + +static char ns7520_mii_identify_phy(void); +static unsigned short ns7520_mii_read(unsigned short uiRegister); +static void ns7520_mii_write(unsigned short uiRegister, + unsigned short uiData); +static unsigned int ns7520_mii_get_clock_divisor(unsigned int + unMaxMDIOClk); +static unsigned int ns7520_mii_poll_busy(void); + +static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK; +static unsigned int uiLastLinkStatus; +static PhyType phyDetected = PHY_NONE; + +/*********************************************************************** + * @Function: eth_init + * @Return: -1 on failure otherwise 0 + * @Descr: Initializes the ethernet engine and uses either FS Forth's default + * MAC addr or the one in environment + ***********************************************************************/ + +int eth_init(bd_t * pbis) +{ + unsigned char aucMACAddr[6]; + char *pcTmp = getenv("ethaddr"); + char *pcEnd; + int i; + + DEBUG_FN(DEBUG_INIT); + + /* no need to check for hardware */ + + if (!ns7520_eth_reset()) + return -1; + + if (NULL == pcTmp) + return -1; + + for (i = 0; i < 6; i++) { + aucMACAddr[i] = + pcTmp ? simple_strtoul(pcTmp, &pcEnd, 16) : 0; + pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd; + } + + /* configure ethernet address */ + + *get_eth_reg_addr(NS7520_ETH_SA1) = + aucMACAddr[5] << 8 | aucMACAddr[4]; + *get_eth_reg_addr(NS7520_ETH_SA2) = + aucMACAddr[3] << 8 | aucMACAddr[2]; + *get_eth_reg_addr(NS7520_ETH_SA3) = + aucMACAddr[1] << 8 | aucMACAddr[0]; + + /* enable hardware */ + + *get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN; + *get_eth_reg_addr(NS7520_ETH_SUPP) = NS7520_ETH_SUPP_JABBER; + *get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN; + + /* the linux kernel may give packets < 60 bytes, for example arp */ + *get_eth_reg_addr(NS7520_ETH_MAC2) = NS7520_ETH_MAC2_CRCEN | + NS7520_ETH_MAC2_PADEN | NS7520_ETH_MAC2_HUGE; + + /* Broadcast/multicast allowed; if you don't set this even unicast chokes */ + /* Based on NS7520 errata documentation */ + *get_eth_reg_addr(NS7520_ETH_SAFR) = + NS7520_ETH_SAFR_BROAD | NS7520_ETH_SAFR_PRM; + + /* enable receive and transmit FIFO, use 10/100 Mbps MII */ + *get_eth_reg_addr(NS7520_ETH_EGCR) |= + NS7520_ETH_EGCR_ETXWM_75 | + NS7520_ETH_EGCR_ERX | + NS7520_ETH_EGCR_ERXREG | + NS7520_ETH_EGCR_ERXBR | NS7520_ETH_EGCR_ETX; + + return 0; +} + +/*********************************************************************** + * @Function: eth_send + * @Return: -1 on timeout otherwise 1 + * @Descr: sends one frame by DMA + ***********************************************************************/ + +int eth_send(volatile void *pPacket, int nLen) +{ + int i, length32, retval = 1; + char *pa; + unsigned int *pa32, lastp = 0, rest; + unsigned int status; + + pa = (char *) pPacket; + pa32 = (unsigned int *) pPacket; + length32 = nLen / 4; + rest = nLen % 4; + + /* make sure there's no garbage in the last word */ + switch (rest) { + case 0: + lastp = pa32[length32 - 1]; + length32--; + break; + case 1: + lastp = pa32[length32] & 0x000000ff; + break; + case 2: + lastp = pa32[length32] & 0x0000ffff; + break; + case 3: + lastp = pa32[length32] & 0x00ffffff; + break; + } + + while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_TXREGE) + == 0) { + } + + /* write to the fifo */ + for (i = 0; i < length32; i++) + *get_eth_reg_addr(NS7520_ETH_FIFO) = pa32[i]; + + /* the last word is written to an extra register, this + starts the transmission */ + *get_eth_reg_addr(NS7520_ETH_FIFOL) = lastp; + + /* Wait for it to be done */ + while ((*get_eth_reg_addr(NS7520_ETH_EGSR) & NS7520_ETH_EGSR_TXBC) + == 0) { + } + status = (*get_eth_reg_addr(NS7520_ETH_ETSR)); + *get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_TXBC; /* Clear it now */ + + if (status & NS7520_ETH_ETSR_TXOK) { + retval = 0; /* We're OK! */ + } else if (status & NS7520_ETH_ETSR_TXDEF) { + printf("Deferred, we'll see.\n"); + retval = 0; + } else if (status & NS7520_ETH_ETSR_TXAL) { + printf("Late collision error, %d collisions.\n", + (*get_eth_reg_addr(NS7520_ETH_ETSR)) & + NS7520_ETH_ETSR_TXCOLC); + } else if (status & NS7520_ETH_ETSR_TXAEC) { + printf("Excessive collisions: %d\n", + (*get_eth_reg_addr(NS7520_ETH_ETSR)) & + NS7520_ETH_ETSR_TXCOLC); + } else if (status & NS7520_ETH_ETSR_TXAED) { + printf("Excessive deferral on xmit.\n"); + } else if (status & NS7520_ETH_ETSR_TXAUR) { + printf("Packet underrun.\n"); + } else if (status & NS7520_ETH_ETSR_TXAJ) { + printf("Jumbo packet error.\n"); + } else { + printf("Error: Should never get here.\n"); + } + + return (retval); +} + +/*********************************************************************** + * @Function: eth_rx + * @Return: size of last frame in bytes or 0 if no frame available + * @Descr: gives one frame to U-Boot which has been copied by DMA engine already + * to NetRxPackets[ 0 ]. + ***********************************************************************/ + +int eth_rx(void) +{ + int i; + unsigned short rxlen; + unsigned short totrxlen = 0; + unsigned int *addr; + unsigned int rxstatus, lastrxlen; + char *pa; + + /* If RXBR is 1, data block was received */ + while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_RXBR) == NS7520_ETH_EGSR_RXBR) { + + /* get status register and the length of received block */ + rxstatus = *get_eth_reg_addr(NS7520_ETH_ERSR); + rxlen = (rxstatus & NS7520_ETH_ERSR_RXSIZE) >> 16; + + /* clear RXBR to make fifo available */ + *get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_RXBR; + + if (rxstatus & NS7520_ETH_ERSR_ROVER) { + printf("Receive overrun, resetting FIFO.\n"); + *get_eth_reg_addr(NS7520_ETH_EGCR) &= + ~NS7520_ETH_EGCR_ERX; + udelay(20); + *get_eth_reg_addr(NS7520_ETH_EGCR) |= + NS7520_ETH_EGCR_ERX; + } + if (rxlen == 0) { + printf("Nothing.\n"); + return 0; + } + + addr = (unsigned int *) NetRxPackets[0]; + pa = (char *) NetRxPackets[0]; + + /* read the fifo */ + for (i = 0; i < rxlen / 4; i++) { + *addr = *get_eth_reg_addr(NS7520_ETH_FIFO); + addr++; + } + + if ((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_RXREGR) { + /* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */ + lastrxlen = + ((*get_eth_reg_addr(NS7520_ETH_EGSR)) & + NS7520_ETH_EGSR_RXFDB_MA) >> 28; + *addr = *get_eth_reg_addr(NS7520_ETH_FIFO); + switch (lastrxlen) { + case 1: + *addr &= 0xff000000; + break; + case 2: + *addr &= 0xffff0000; + break; + case 3: + *addr &= 0xffffff00; + break; + } + } + + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[0], rxlen - 4); + totrxlen += rxlen - 4; + } + + return totrxlen; +} + +/*********************************************************************** + * @Function: eth_halt + * @Return: n/a + * @Descr: stops the ethernet engine + ***********************************************************************/ + +void eth_halt(void) +{ + DEBUG_FN(DEBUG_INIT); + + *get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_RXEN; + *get_eth_reg_addr(NS7520_ETH_EGCR) &= ~(NS7520_ETH_EGCR_ERX | + NS7520_ETH_EGCR_ERXDMA | + NS7520_ETH_EGCR_ERXREG | + NS7520_ETH_EGCR_ERXBR | + NS7520_ETH_EGCR_ETX | + NS7520_ETH_EGCR_ETXDMA); +} + +/*********************************************************************** + * @Function: ns7520_eth_reset + * @Return: 0 on failure otherwise 1 + * @Descr: resets the ethernet interface and the PHY, + * performs auto negotiation or fixed modes + ***********************************************************************/ + +static int ns7520_eth_reset(void) +{ + DEBUG_FN(DEBUG_MINOR); + + /* Reset important registers */ + *get_eth_reg_addr(NS7520_ETH_EGCR) = 0; /* Null it out! */ + *get_eth_reg_addr(NS7520_ETH_MAC1) &= NS7520_ETH_MAC1_SRST; + *get_eth_reg_addr(NS7520_ETH_MAC2) = 0; + /* Reset MAC */ + *get_eth_reg_addr(NS7520_ETH_EGCR) |= NS7520_ETH_EGCR_MAC_RES; + udelay(5); + *get_eth_reg_addr(NS7520_ETH_EGCR) &= ~NS7520_ETH_EGCR_MAC_RES; + + /* reset and initialize PHY */ + + *get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_SRST; + + /* we don't support hot plugging of PHY, therefore we don't reset + phyDetected and nPhyMaxMdioClock here. The risk is if the setting is + incorrect the first open + may detect the PHY correctly but succeding will fail + For reseting the PHY and identifying we have to use the standard + MDIO CLOCK value 2.5 MHz only after hardware reset + After having identified the PHY we will do faster */ + + *get_eth_reg_addr(NS7520_ETH_MCFG) = + ns7520_mii_get_clock_divisor(nPhyMaxMdioClock); + + /* reset PHY */ + ns7520_mii_write(PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET); + ns7520_mii_write(PHY_COMMON_CTRL, 0); + + udelay(3000); /* [2] p.70 says at least 300us reset recovery time. */ + + /* MII clock has been setup to default, ns7520_mii_identify_phy should + work for all */ + + if (!ns7520_mii_identify_phy()) { + printk(KERN_ERR NS7520_DRIVER_NAME + ": Unsupported PHY, aborting\n"); + return 0; + } + + /* now take the highest MDIO clock possible after detection */ + *get_eth_reg_addr(NS7520_ETH_MCFG) = + ns7520_mii_get_clock_divisor(nPhyMaxMdioClock); + + /* PHY has been detected, so there can be no abort reason and we can + finish initializing ethernet */ + + uiLastLinkStatus = 0xff; /* undefined */ + + ns7520_link_auto_negotiate(); + + if (phyDetected == PHY_LXT971A) + /* set LED2 to link mode */ + ns7520_mii_write(PHY_LXT971_LED_CFG, + (PHY_LXT971_LED_CFG_LINK_ACT << + PHY_LXT971_LED_CFG_SHIFT_LED2) | + (PHY_LXT971_LED_CFG_TRANSMIT << + PHY_LXT971_LED_CFG_SHIFT_LED1)); + + return 1; +} + +/*********************************************************************** + * @Function: ns7520_link_auto_negotiate + * @Return: void + * @Descr: performs auto-negotation of link. + ***********************************************************************/ + +static void ns7520_link_auto_negotiate(void) +{ + unsigned long ulStartJiffies; + unsigned short uiStatus; + + DEBUG_FN(DEBUG_LINK); + + /* run auto-negotation */ + /* define what we are capable of */ + ns7520_mii_write(PHY_COMMON_AUTO_ADV, + PHY_COMMON_AUTO_ADV_100BTXFD | + PHY_COMMON_AUTO_ADV_100BTX | + PHY_COMMON_AUTO_ADV_10BTFD | + PHY_COMMON_AUTO_ADV_10BT | + PHY_COMMON_AUTO_ADV_802_3); + /* start auto-negotiation */ + ns7520_mii_write(PHY_COMMON_CTRL, + PHY_COMMON_CTRL_AUTO_NEG | + PHY_COMMON_CTRL_RES_AUTO); + + /* wait for completion */ + + ulStartJiffies = get_timer(0); + while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) { + uiStatus = ns7520_mii_read(PHY_COMMON_STAT); + if ((uiStatus & + (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) + == + (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) { + /* lucky we are, auto-negotiation succeeded */ + ns7520_link_print_changed(); + ns7520_link_update_egcr(); + return; + } + } + + DEBUG_ARGS0(DEBUG_LINK, "auto-negotiation timed out\n"); + /* ignore invalid link settings */ +} + +/*********************************************************************** + * @Function: ns7520_link_update_egcr + * @Return: void + * @Descr: updates the EGCR and MAC2 link status after mode change or + * auto-negotation + ***********************************************************************/ + +static void ns7520_link_update_egcr(void) +{ + unsigned int unEGCR; + unsigned int unMAC2; + unsigned int unIPGT; + + DEBUG_FN(DEBUG_LINK); + + unEGCR = *get_eth_reg_addr(NS7520_ETH_EGCR); + unMAC2 = *get_eth_reg_addr(NS7520_ETH_MAC2); + unIPGT = + *get_eth_reg_addr(NS7520_ETH_IPGT) & ~NS7520_ETH_IPGT_IPGT; + + unEGCR &= ~NS7520_ETH_EGCR_EFULLD; + unMAC2 &= ~NS7520_ETH_MAC2_FULLD; + if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE) + == PHY_LXT971_STAT2_DUPLEX_MODE) { + unEGCR |= NS7520_ETH_EGCR_EFULLD; + unMAC2 |= NS7520_ETH_MAC2_FULLD; + unIPGT |= 0x15; /* see [1] p. 167 */ + } else + unIPGT |= 0x12; /* see [1] p. 167 */ + + *get_eth_reg_addr(NS7520_ETH_MAC2) = unMAC2; + *get_eth_reg_addr(NS7520_ETH_EGCR) = unEGCR; + *get_eth_reg_addr(NS7520_ETH_IPGT) = unIPGT; +} + +/*********************************************************************** + * @Function: ns7520_link_print_changed + * @Return: void + * @Descr: checks whether the link status has changed and if so prints + * the new mode + ***********************************************************************/ + +static void ns7520_link_print_changed(void) +{ + unsigned short uiStatus; + unsigned short uiControl; + + DEBUG_FN(DEBUG_LINK); + + uiControl = ns7520_mii_read(PHY_COMMON_CTRL); + + if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) == + PHY_COMMON_CTRL_AUTO_NEG) { + /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */ + uiStatus = ns7520_mii_read(PHY_COMMON_STAT); + + if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) { + printk(KERN_WARNING NS7520_DRIVER_NAME + ": link down\n"); + /* @TODO Linux: carrier_off */ + } else { + /* @TODO Linux: carrier_on */ + if (phyDetected == PHY_LXT971A) { + uiStatus = + ns7520_mii_read(PHY_LXT971_STAT2); + uiStatus &= + (PHY_LXT971_STAT2_100BTX | + PHY_LXT971_STAT2_DUPLEX_MODE | + PHY_LXT971_STAT2_AUTO_NEG); + + /* mask out all uninteresting parts */ + } + /* other PHYs must store there link information in + uiStatus as PHY_LXT971 */ + } + } else { + /* mode has been forced, so uiStatus should be the same as the + last link status, enforce printing */ + uiStatus = uiLastLinkStatus; + uiLastLinkStatus = 0xff; + } + + if (uiStatus != uiLastLinkStatus) { + /* save current link status */ + uiLastLinkStatus = uiStatus; + + /* print new link status */ + + printk(KERN_INFO NS7520_DRIVER_NAME + ": link mode %i Mbps %s duplex %s\n", + (uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10, + (uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" : + "half", + (uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" : + ""); + } +} + +/*********************************************************************** + * the MII low level stuff + ***********************************************************************/ + +/*********************************************************************** + * @Function: ns7520_mii_identify_phy + * @Return: 1 if supported PHY has been detected otherwise 0 + * @Descr: checks for supported PHY and prints the IDs. + ***********************************************************************/ + +static char ns7520_mii_identify_phy(void) +{ + unsigned short uiID1; + unsigned short uiID2; + unsigned char *szName; + char cRes = 0; + + DEBUG_FN(DEBUG_MII); + + phyDetected = (PhyType) uiID1 = ns7520_mii_read(PHY_COMMON_ID1); + + switch (phyDetected) { + case PHY_LXT971A: + szName = "LXT971A"; + uiID2 = ns7520_mii_read(PHY_COMMON_ID2); + nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; + cRes = 1; + break; + case PHY_NONE: + default: + /* in case uiID1 == 0 && uiID2 == 0 we may have the wrong + address or reset sets the wrong NS7520_ETH_MCFG_CLKS */ + + uiID2 = 0; + szName = "unknown"; + nPhyMaxMdioClock = PHY_MDIO_MAX_CLK; + phyDetected = PHY_NONE; + } + + printk(KERN_INFO NS7520_DRIVER_NAME + ": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName); + + return cRes; +} + +/*********************************************************************** + * @Function: ns7520_mii_read + * @Return: the data read from PHY register uiRegister + * @Descr: the data read may be invalid if timed out. If so, a message + * is printed but the invalid data is returned. + * The fixed device address is being used. + ***********************************************************************/ + +static unsigned short ns7520_mii_read(unsigned short uiRegister) +{ + DEBUG_FN(DEBUG_MII_LOW); + + /* write MII register to be read */ + *get_eth_reg_addr(NS7520_ETH_MADR) = + CONFIG_PHY_ADDR << 8 | uiRegister; + + *get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ; + + if (!ns7520_mii_poll_busy()) + printk(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in read\n"); + /* continue to read */ + + *get_eth_reg_addr(NS7520_ETH_MCMD) = 0; + + return (unsigned short) (*get_eth_reg_addr(NS7520_ETH_MRDD)); +} + +/*********************************************************************** + * @Function: ns7520_mii_write + * @Return: nothing + * @Descr: writes the data to the PHY register. In case of a timeout, + * no special handling is performed but a message printed + * The fixed device address is being used. + ***********************************************************************/ + +static void ns7520_mii_write(unsigned short uiRegister, + unsigned short uiData) +{ + DEBUG_FN(DEBUG_MII_LOW); + + /* write MII register to be written */ + *get_eth_reg_addr(NS7520_ETH_MADR) = + CONFIG_PHY_ADDR << 8 | uiRegister; + + *get_eth_reg_addr(NS7520_ETH_MWTD) = uiData; + + if (!ns7520_mii_poll_busy()) { + printf(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in write\n"); + } +} + +/*********************************************************************** + * @Function: ns7520_mii_get_clock_divisor + * @Return: the clock divisor that should be used in NS7520_ETH_MCFG_CLKS + * @Descr: if no clock divisor can be calculated for the + * current SYSCLK and the maximum MDIO Clock, a warning is printed + * and the greatest divisor is taken + ***********************************************************************/ + +static unsigned int ns7520_mii_get_clock_divisor(unsigned int unMaxMDIOClk) +{ + struct { + unsigned int unSysClkDivisor; + unsigned int unClks; /* field for NS7520_ETH_MCFG_CLKS */ + } PHYClockDivisors[] = { + { + 4, NS7520_ETH_MCFG_CLKS_4}, { + 6, NS7520_ETH_MCFG_CLKS_6}, { + 8, NS7520_ETH_MCFG_CLKS_8}, { + 10, NS7520_ETH_MCFG_CLKS_10}, { + 14, NS7520_ETH_MCFG_CLKS_14}, { + 20, NS7520_ETH_MCFG_CLKS_20}, { + 28, NS7520_ETH_MCFG_CLKS_28} + }; + + int nIndexSysClkDiv; + int nArraySize = + sizeof(PHYClockDivisors) / sizeof(PHYClockDivisors[0]); + unsigned int unClks = NS7520_ETH_MCFG_CLKS_28; /* defaults to + greatest div */ + + DEBUG_FN(DEBUG_INIT); + + for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize; + nIndexSysClkDiv++) { + /* find first sysclock divisor that isn't higher than 2.5 MHz + clock */ + if (NETARM_XTAL_FREQ / + PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <= + unMaxMDIOClk) { + unClks = PHYClockDivisors[nIndexSysClkDiv].unClks; + break; + } + } + + DEBUG_ARGS2(DEBUG_INIT, + "Taking MDIO Clock bit mask 0x%0x for max clock %i\n", + unClks, unMaxMDIOClk); + + /* return greatest divisor */ + return unClks; +} + +/*********************************************************************** + * @Function: ns7520_mii_poll_busy + * @Return: 0 if timed out otherwise the remaing timeout + * @Descr: waits until the MII has completed a command or it times out + * code may be interrupted by hard interrupts. + * It is not checked what happens on multiple actions when + * the first is still being busy and we timeout. + ***********************************************************************/ + +static unsigned int ns7520_mii_poll_busy(void) +{ + unsigned int unTimeout = 1000; + + DEBUG_FN(DEBUG_MII_LOW); + + while (((*get_eth_reg_addr(NS7520_ETH_MIND) & NS7520_ETH_MIND_BUSY) + == NS7520_ETH_MIND_BUSY) && unTimeout) + unTimeout--; + + return unTimeout; +} + +/* ---------------------------------------------------------------------------- + * Net+ARM ethernet MII functionality. + */ +#if defined(CONFIG_MII) + +/** + * Maximum MII address we support + */ +#define MII_ADDRESS_MAX (31) + +/** + * Maximum MII register address we support + */ +#define MII_REGISTER_MAX (31) + +/** + * Ethernet MII interface return values for public functions. + */ +enum mii_status { + MII_STATUS_SUCCESS = 0, + MII_STATUS_FAILURE = 1, +}; + +/** + * Read a 16-bit value from an MII register. + */ +extern int ns7520_miiphy_read(char *devname, unsigned char const addr, + unsigned char const reg, unsigned short *const value) +{ + int ret = MII_STATUS_FAILURE; + + /* Parameter checks */ + if (addr > MII_ADDRESS_MAX) { + ERROR(("invalid addr, 0x%02X", addr)); + goto miiphy_read_failed_0; + } + + if (reg > MII_REGISTER_MAX) { + ERROR(("invalid reg, 0x%02X", reg)); + goto miiphy_read_failed_0; + } + + if (value == NULL) { + ERROR(("NULL value")); + goto miiphy_read_failed_0; + } + + DEBUG_FN(DEBUG_MII_LOW); + + /* write MII register to be read */ + *get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg; + + *get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ; + + if (!ns7520_mii_poll_busy()) + printk(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in read\n"); + /* continue to read */ + + *get_eth_reg_addr(NS7520_ETH_MCMD) = 0; + + *value = (*get_eth_reg_addr(NS7520_ETH_MRDD)); + ret = MII_STATUS_SUCCESS; + /* Fall through */ + + miiphy_read_failed_0: + return (ret); +} + +/** + * Write a 16-bit value to an MII register. + */ +extern int ns7520_miiphy_write(char *devname, unsigned char const addr, + unsigned char const reg, unsigned short const value) +{ + int ret = MII_STATUS_FAILURE; + + /* Parameter checks */ + if (addr > MII_ADDRESS_MAX) { + ERROR(("invalid addr, 0x%02X", addr)); + goto miiphy_write_failed_0; + } + + if (reg > MII_REGISTER_MAX) { + ERROR(("invalid reg, 0x%02X", reg)); + goto miiphy_write_failed_0; + } + + /* write MII register to be written */ + *get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg; + + *get_eth_reg_addr(NS7520_ETH_MWTD) = value; + + if (!ns7520_mii_poll_busy()) { + printf(KERN_WARNING NS7520_DRIVER_NAME + ": MII still busy in write\n"); + } + + ret = MII_STATUS_SUCCESS; + /* Fall through */ + + miiphy_write_failed_0: + return (ret); +} +#endif /* defined(CONFIG_MII) */ +#endif /* CONFIG_DRIVER_NS7520_ETHERNET */ + +int ns7520_miiphy_initialize(bd_t *bis) +{ +#if defined(CONFIG_DRIVER_NS7520_ETHERNET) +#if defined(CONFIG_MII) + miiphy_register("ns7520phy", ns7520_miiphy_read, ns7520_miiphy_write); +#endif +#endif + return 0; +} diff --git a/drivers/ns8382x.c b/drivers/ns8382x.c new file mode 100644 index 000000000..976f86aaf --- /dev/null +++ b/drivers/ns8382x.c @@ -0,0 +1,863 @@ +/* + ns8382x.c: A U-Boot driver for the NatSemi DP8382[01]. + ported by: Mark A. Rakes (mark_rakes@vivato.net) + + Adapted from: + 1. an Etherboot driver for DP8381[56] written by: + Copyright (C) 2001 Entity Cyber, Inc. + + This development of this Etherboot driver was funded by + Sicom Systems: http://www.sicompos.com/ + + Author: Marty Connor (mdc@thinguin.org) + Adapted from a Linux driver which was written by Donald Becker + + This software may be used and distributed according to the terms + of the GNU Public License (GPL), incorporated herein by reference. + + 2. A Linux driver by Donald Becker, ns820.c: + Written/copyright 1999-2002 by Donald Becker. + + This software may be used and distributed according to the terms of + the GNU General Public License (GPL), incorporated herein by reference. + Drivers based on or derived from this code fall under the GPL and must + retain the authorship, copyright and license notice. This file is not + a complete program and may only be used when the entire operating + system is licensed under the GPL. License for under other terms may be + available. Contact the original author for details. + + The original author may be reached as becker@scyld.com, or at + Scyld Computing Corporation + 410 Severn Ave., Suite 210 + Annapolis MD 21403 + + Support information and updates available at + http://www.scyld.com/network/netsemi.html + + Datasheets available from: + http://www.national.com/pf/DP/DP83820.html + http://www.national.com/pf/DP/DP83821.html +*/ + +/* Revision History + * October 2002 mar 1.0 + * Initial U-Boot Release. + * Tested with Netgear GA622T (83820) + * and SMC9452TX (83821) + * NOTE: custom boards with these chips may (likely) require + * a programmed EEPROM device (if present) in order to work + * correctly. +*/ + +/* Includes */ +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_NS8382X) + +/* defines */ +#define DSIZE 0x00000FFF +#define ETH_ALEN 6 +#define CRC_SIZE 4 +#define TOUT_LOOP 500000 +#define TX_BUF_SIZE 1536 +#define RX_BUF_SIZE 1536 +#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ + +enum register_offsets { + ChipCmd = 0x00, + ChipConfig = 0x04, + EECtrl = 0x08, + IntrMask = 0x14, + IntrEnable = 0x18, + TxRingPtr = 0x20, + TxRingPtrHi = 0x24, + TxConfig = 0x28, + RxRingPtr = 0x30, + RxRingPtrHi = 0x34, + RxConfig = 0x38, + PriQueue = 0x3C, + RxFilterAddr = 0x48, + RxFilterData = 0x4C, + ClkRun = 0xCC, + PCIPM = 0x44, +}; + +enum ChipCmdBits { + ChipReset = 0x100, + RxReset = 0x20, + TxReset = 0x10, + RxOff = 0x08, + RxOn = 0x04, + TxOff = 0x02, + TxOn = 0x01 +}; + +enum ChipConfigBits { + LinkSts = 0x80000000, + GigSpeed = 0x40000000, + HundSpeed = 0x20000000, + FullDuplex = 0x10000000, + TBIEn = 0x01000000, + Mode1000 = 0x00400000, + T64En = 0x00004000, + D64En = 0x00001000, + M64En = 0x00000800, + PhyRst = 0x00000400, + PhyDis = 0x00000200, + ExtStEn = 0x00000100, + BEMode = 0x00000001, +}; +#define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex) + +enum TxConfig_bits { + TxDrthMask = 0x000000ff, + TxFlthMask = 0x0000ff00, + TxMxdmaMask = 0x00700000, + TxMxdma_8 = 0x00100000, + TxMxdma_16 = 0x00200000, + TxMxdma_32 = 0x00300000, + TxMxdma_64 = 0x00400000, + TxMxdma_128 = 0x00500000, + TxMxdma_256 = 0x00600000, + TxMxdma_512 = 0x00700000, + TxMxdma_1024 = 0x00000000, + TxCollRetry = 0x00800000, + TxAutoPad = 0x10000000, + TxMacLoop = 0x20000000, + TxHeartIgn = 0x40000000, + TxCarrierIgn = 0x80000000 +}; + +enum RxConfig_bits { + RxDrthMask = 0x0000003e, + RxMxdmaMask = 0x00700000, + RxMxdma_8 = 0x00100000, + RxMxdma_16 = 0x00200000, + RxMxdma_32 = 0x00300000, + RxMxdma_64 = 0x00400000, + RxMxdma_128 = 0x00500000, + RxMxdma_256 = 0x00600000, + RxMxdma_512 = 0x00700000, + RxMxdma_1024 = 0x00000000, + RxAcceptLenErr = 0x04000000, + RxAcceptLong = 0x08000000, + RxAcceptTx = 0x10000000, + RxStripCRC = 0x20000000, + RxAcceptRunt = 0x40000000, + RxAcceptErr = 0x80000000, +}; + +/* Bits in the RxMode register. */ +enum rx_mode_bits { + RxFilterEnable = 0x80000000, + AcceptAllBroadcast = 0x40000000, + AcceptAllMulticast = 0x20000000, + AcceptAllUnicast = 0x10000000, + AcceptPerfectMatch = 0x08000000, +}; + +typedef struct _BufferDesc { + u32 link; + u32 bufptr; + vu_long cmdsts; + u32 extsts; /*not used here */ +} BufferDesc; + +/* Bits in network_desc.status */ +enum desc_status_bits { + DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000, + DescNoCRC = 0x10000000, DescPktOK = 0x08000000, + DescSizeMask = 0xfff, + + DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000, + DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000, + DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000, + DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000, + + DescRxAbort = 0x04000000, DescRxOver = 0x02000000, + DescRxDest = 0x01800000, DescRxLong = 0x00400000, + DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000, + DescRxCRC = 0x00080000, DescRxAlign = 0x00040000, + DescRxLoop = 0x00020000, DesRxColl = 0x00010000, +}; + +/* Bits in MEAR */ +enum mii_reg_bits { + MDIO_ShiftClk = 0x0040, + MDIO_EnbOutput = 0x0020, + MDIO_Data = 0x0010, +}; + +/* PHY Register offsets. */ +enum phy_reg_offsets { + BMCR = 0x00, + BMSR = 0x01, + PHYIDR1 = 0x02, + PHYIDR2 = 0x03, + ANAR = 0x04, + KTCR = 0x09, +}; + +/* basic mode control register bits */ +enum bmcr_bits { + Bmcr_Reset = 0x8000, + Bmcr_Loop = 0x4000, + Bmcr_Speed0 = 0x2000, + Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */ + Bmcr_RstAutoNeg = 0x0200, + Bmcr_Duplex = 0x0100, + Bmcr_Speed1 = 0x0040, + Bmcr_Force10H = 0x0000, + Bmcr_Force10F = 0x0100, + Bmcr_Force100H = 0x2000, + Bmcr_Force100F = 0x2100, + Bmcr_Force1000H = 0x0040, + Bmcr_Force1000F = 0x0140, +}; + +/* auto negotiation advertisement register */ +enum anar_bits { + anar_adv_100F = 0x0100, + anar_adv_100H = 0x0080, + anar_adv_10F = 0x0040, + anar_adv_10H = 0x0020, + anar_ieee_8023 = 0x0001, +}; + +/* 1K-base T control register */ +enum ktcr_bits { + ktcr_adv_1000H = 0x0100, + ktcr_adv_1000F = 0x0200, +}; + +/* Globals */ +static u32 SavedClkRun; +static unsigned int cur_rx; +static unsigned int rx_config; +static unsigned int tx_config; + +/* Note: transmit and receive buffers and descriptors must be + long long word aligned */ +static BufferDesc txd __attribute__ ((aligned(8))); +static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8))); +static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8))); +static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE] + __attribute__ ((aligned(8))); + +/* Function Prototypes */ +static int mdio_read(struct eth_device *dev, int phy_id, int addr); +static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value); +static void mdio_sync(struct eth_device *dev, u32 offset); +static int ns8382x_init(struct eth_device *dev, bd_t * bis); +static void ns8382x_reset(struct eth_device *dev); +static void ns8382x_init_rxfilter(struct eth_device *dev); +static void ns8382x_init_txd(struct eth_device *dev); +static void ns8382x_init_rxd(struct eth_device *dev); +static void ns8382x_set_rx_mode(struct eth_device *dev); +static void ns8382x_check_duplex(struct eth_device *dev); +static int ns8382x_send(struct eth_device *dev, volatile void *packet, + int length); +static int ns8382x_poll(struct eth_device *dev); +static void ns8382x_disable(struct eth_device *dev); + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820}, + {} +}; + +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +static inline int +INW(struct eth_device *dev, u_long addr) +{ + return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); +} + +static int +INL(struct eth_device *dev, u_long addr) +{ + return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); +} + +static inline void +OUTW(struct eth_device *dev, int command, u_long addr) +{ + *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); +} + +static inline void +OUTL(struct eth_device *dev, int command, u_long addr) +{ + *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); +} + +/* Function: ns8382x_initialize + * Description: Retrieves the MAC address of the card, and sets up some + * globals required by other routines, and initializes the NIC, making it + * ready to send and receive packets. + * Side effects: initializes ns8382xs, ready to recieve packets. + * Returns: int: number of cards found + */ + +int +ns8382x_initialize(bd_t * bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase, status; + int i, idx = 0; + u32 phyAddress; + u32 tmp; + u32 chip_config; + + while (1) { /* Find PCI device(s) */ + if ((devno = pci_find_devices(supported, idx++)) < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */ + +#ifdef NS8382X_DEBUG + printf("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase); +#endif + + pci_write_config_dword(devno, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Check if I/O accesses and Bus Mastering are enabled. */ + pci_read_config_dword(devno, PCI_COMMAND, &status); + if (!(status & PCI_COMMAND_MEMORY)) { + printf("Error: Can not enable MEM access.\n"); + continue; + } else if (!(status & PCI_COMMAND_MASTER)) { + printf("Error: Can not enable Bus Mastering.\n"); + continue; + } + + dev = (struct eth_device *) malloc(sizeof *dev); + + sprintf(dev->name, "dp8382x#%d", card_number); + dev->iobase = bus_to_phys(iobase); + dev->priv = (void *) devno; + dev->init = ns8382x_init; + dev->halt = ns8382x_disable; + dev->send = ns8382x_send; + dev->recv = ns8382x_poll; + + /* ns8382x has a non-standard PM control register + * in PCI config space. Some boards apparently need + * to be brought to D0 in this manner. */ + pci_read_config_dword(devno, PCIPM, &tmp); + if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */ + u32 newtmp = tmp & ~(0x03 | 0x100); + pci_write_config_dword(devno, PCIPM, newtmp); + } + + /* get MAC address */ + for (i = 0; i < 3; i++) { + u32 data; + char *mac = (char *)&dev->enetaddr[i * 2]; + + OUTL(dev, i * 2, RxFilterAddr); + data = INL(dev, RxFilterData); + *mac++ = data; + *mac++ = data >> 8; + } + /* get PHY address, can't be zero */ + for (phyAddress = 1; phyAddress < 32; phyAddress++) { + u32 rev, phy1; + + phy1 = mdio_read(dev, phyAddress, PHYIDR1); + if (phy1 == 0x2000) { /*check for 83861/91 */ + rev = mdio_read(dev, phyAddress, PHYIDR2); + if ((rev & ~(0x000f)) == 0x00005c50 || + (rev & ~(0x000f)) == 0x00005c60) { +#ifdef NS8382X_DEBUG + printf("phy rev is %x\n", rev); + printf("phy address is %x\n", + phyAddress); +#endif + break; + } + } + } + + /* set phy to autonegotiate && advertise everything */ + mdio_write(dev, phyAddress, KTCR, + (ktcr_adv_1000H | ktcr_adv_1000F)); + mdio_write(dev, phyAddress, ANAR, + (anar_adv_100F | anar_adv_100H | anar_adv_10H | + anar_adv_10F | anar_ieee_8023)); + mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */ + mdio_write(dev, phyAddress, BMCR, + (Bmcr_AutoNegEn | Bmcr_RstAutoNeg)); + /* Reset the chip to erase any previous misconfiguration. */ + OUTL(dev, (ChipReset), ChipCmd); + + chip_config = INL(dev, ChipConfig); + /* reset the phy */ + OUTL(dev, (chip_config | PhyRst), ChipConfig); + /* power up and initialize transceiver */ + OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig); + + mdio_sync(dev, EECtrl); +#ifdef NS8382X_DEBUG + { + u32 chpcfg = + INL(dev, ChipConfig) ^ SpeedStatus_Polarity; + + printf("%s: Transceiver 10%s %s duplex.\n", dev->name, + (chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed) + ? "0" : "", + chpcfg & FullDuplex ? "full" : "half"); + printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, + dev->enetaddr[0], dev->enetaddr[1], + dev->enetaddr[2], dev->enetaddr[3], + dev->enetaddr[4], dev->enetaddr[5]); + } +#endif + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + SavedClkRun = INL(dev, ClkRun); + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + + eth_register(dev); + + card_number++; + + pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60); + + udelay(10 * 1000); + } + return card_number; +} + +/* MII transceiver control section. + Read and write MII registers using software-generated serial MDIO + protocol. See the MII specifications or DP83840A data sheet for details. + + The maximum data clock rate is 2.5 Mhz. To meet minimum timing we + must flush writes to the PCI bus with a PCI read. */ +#define mdio_delay(mdio_addr) INL(dev, mdio_addr) + +#define MDIO_EnbIn (0) +#define MDIO_WRITE0 (MDIO_EnbOutput) +#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput) + +/* Generate the preamble required for initial synchronization and + a few older transceivers. */ +static void +mdio_sync(struct eth_device *dev, u32 offset) +{ + int bits = 32; + + /* Establish sync by sending at least 32 logic ones. */ + while (--bits >= 0) { + OUTL(dev, MDIO_WRITE1, offset); + mdio_delay(offset); + OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset); + mdio_delay(offset); + } +} + +static int +mdio_read(struct eth_device *dev, int phy_id, int addr) +{ + int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr; + int i, retval = 0; + + /* Shift the read command bits out. */ + for (i = 15; i >= 0; i--) { + int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; + + OUTL(dev, dataval, EECtrl); + mdio_delay(EECtrl); + OUTL(dev, dataval | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + /* Read the two transition, 16 data, and wire-idle bits. */ + for (i = 19; i > 0; i--) { + OUTL(dev, MDIO_EnbIn, EECtrl); + mdio_delay(EECtrl); + retval = + (retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0); + OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + return (retval >> 1) & 0xffff; +} + +static void +mdio_write(struct eth_device *dev, int phy_id, int addr, int value) +{ + int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value; + int i; + + /* Shift the command bits out. */ + for (i = 31; i >= 0; i--) { + int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; + + OUTL(dev, dataval, EECtrl); + mdio_delay(EECtrl); + OUTL(dev, dataval | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + /* Clear out extra bits. */ + for (i = 2; i > 0; i--) { + OUTL(dev, MDIO_EnbIn, EECtrl); + mdio_delay(EECtrl); + OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl); + mdio_delay(EECtrl); + } + return; +} + +/* Function: ns8382x_init + * Description: resets the ethernet controller chip and configures + * registers and data structures required for sending and receiving packets. + * Arguments: struct eth_device *dev: NIC data structure + * returns: int. + */ + +static int +ns8382x_init(struct eth_device *dev, bd_t * bis) +{ + u32 config; + + ns8382x_reset(dev); + + /* Disable PME: + * The PME bit is initialized from the EEPROM contents. + * PCI cards probably have PME disabled, but motherboard + * implementations may have PME set to enable WakeOnLan. + * With PME set the chip will scan incoming packets but + * nothing will be written to memory. */ + OUTL(dev, SavedClkRun & ~0x100, ClkRun); + + ns8382x_init_rxfilter(dev); + ns8382x_init_txd(dev); + ns8382x_init_rxd(dev); + + /*set up ChipConfig */ + config = INL(dev, ChipConfig); + /*turn off 64 bit ops && Ten-bit interface + * && big-endian mode && extended status */ + config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn); + OUTL(dev, config, ChipConfig); + + /* Configure the PCI bus bursts and FIFO thresholds. */ + tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad + | TxCollRetry | TxMxdma_1024 | (0x1002); + rx_config = RxMxdma_1024 | 0x20; +#ifdef NS8382X_DEBUG + printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config); + printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config); +#endif + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); + + /*turn off priority queueing */ + OUTL(dev, 0x0, PriQueue); + + ns8382x_check_duplex(dev); + ns8382x_set_rx_mode(dev); + + OUTL(dev, (RxOn | TxOn), ChipCmd); + return 1; +} + +/* Function: ns8382x_reset + * Description: soft resets the controller chip + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ +static void +ns8382x_reset(struct eth_device *dev) +{ + OUTL(dev, ChipReset, ChipCmd); + while (INL(dev, ChipCmd)) + /*wait until done */ ; + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); +} + +/* Function: ns8382x_init_rxfilter + * Description: sets receive filter address to our MAC address + * Arguments: struct eth_device *dev: NIC data structure + * returns: void. + */ + +static void +ns8382x_init_rxfilter(struct eth_device *dev) +{ + int i; + + for (i = 0; i < ETH_ALEN; i += 2) { + OUTL(dev, i, RxFilterAddr); + OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8), + RxFilterData); + } +} + +/* Function: ns8382x_init_txd + * Description: initializes the Tx descriptor + * Arguments: struct eth_device *dev: NIC data structure + * returns: void. + */ + +static void +ns8382x_init_txd(struct eth_device *dev) +{ + txd.link = (u32) 0; + txd.bufptr = cpu_to_le32((u32) & txb[0]); + txd.cmdsts = (u32) 0; + txd.extsts = (u32) 0; + + OUTL(dev, 0x0, TxRingPtrHi); + OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr); +#ifdef NS8382X_DEBUG + printf("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n", + INL(dev, TxRingPtr), &txd); +#endif +} + +/* Function: ns8382x_init_rxd + * Description: initializes the Rx descriptor ring + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ + +static void +ns8382x_init_rxd(struct eth_device *dev) +{ + int i; + + OUTL(dev, 0x0, RxRingPtrHi); + + cur_rx = 0; + for (i = 0; i < NUM_RX_DESC; i++) { + rxd[i].link = + cpu_to_le32((i + 1 < + NUM_RX_DESC) ? (u32) & rxd[i + + 1] : (u32) & + rxd[0]); + rxd[i].extsts = cpu_to_le32((u32) 0x0); + rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE); + rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]); +#ifdef NS8382X_DEBUG + printf + ("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n", + i, &rxd[i], le32_to_cpu(rxd[i].link), + le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr)); +#endif + } + OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr); + +#ifdef NS8382X_DEBUG + printf("ns8382x_init_rxd: RX descriptor register loaded with: %X\n", + INL(dev, RxRingPtr)); +#endif +} + +/* Function: ns8382x_set_rx_mode + * Description: + * sets the receive mode to accept all broadcast packets and packets + * with our MAC address, and reject all multicast packets. + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ + +static void +ns8382x_set_rx_mode(struct eth_device *dev) +{ + u32 rx_mode = 0x0; + /*spec says RxFilterEnable has to be 0 for rest of + * this stuff to be properly configured. Linux driver + * seems to support this*/ +/* OUTL(dev, rx_mode, RxFilterAddr);*/ + rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch); + OUTL(dev, rx_mode, RxFilterAddr); + printf("ns8382x_set_rx_mode: set to %X\n", rx_mode); + /*now we turn RxFilterEnable back on */ + /*rx_mode |= RxFilterEnable; + OUTL(dev, rx_mode, RxFilterAddr);*/ +} + +static void +ns8382x_check_duplex(struct eth_device *dev) +{ + int gig = 0; + int hun = 0; + int duplex = 0; + int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity); + + duplex = (config & FullDuplex) ? 1 : 0; + gig = (config & GigSpeed) ? 1 : 0; + hun = (config & HundSpeed) ? 1 : 0; +#ifdef NS8382X_DEBUG + printf("%s: Setting 10%s %s-duplex based on negotiated link" + " capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "", + duplex ? "full" : "half"); +#endif + if (duplex) { + rx_config |= RxAcceptTx; + tx_config |= (TxCarrierIgn | TxHeartIgn); + } else { + rx_config &= ~RxAcceptTx; + tx_config &= ~(TxCarrierIgn | TxHeartIgn); + } +#ifdef NS8382X_DEBUG + printf("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config); + printf("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config); +#endif + OUTL(dev, tx_config, TxConfig); + OUTL(dev, rx_config, RxConfig); + + /*if speed is 10 or 100, remove MODE1000, + * if it's 1000, then set it */ + config = INL(dev, ChipConfig); + if (gig) + config |= Mode1000; + else + config &= ~Mode1000; + +#ifdef NS8382X_DEBUG + printf("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns"); +#endif + OUTL(dev, config, ChipConfig); +} + +/* Function: ns8382x_send + * Description: transmits a packet and waits for completion or timeout. + * Returns: void. */ +static int +ns8382x_send(struct eth_device *dev, volatile void *packet, int length) +{ + u32 i, status = 0; + vu_long tx_stat = 0; + + /* Stop the transmitter */ + OUTL(dev, TxOff, ChipCmd); +#ifdef NS8382X_DEBUG + printf("ns8382x_send: sending %d bytes\n", (int)length); +#endif + + /* set the transmit buffer descriptor and enable Transmit State Machine */ + txd.link = cpu_to_le32(0x0); + txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet)); + txd.extsts = cpu_to_le32(0x0); + txd.cmdsts = cpu_to_le32(DescOwn | length); + + /* load Transmit Descriptor Register */ + OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr); +#ifdef NS8382X_DEBUG + printf("ns8382x_send: TX descriptor register loaded with: %#08X\n", + INL(dev, TxRingPtr)); + printf("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n", + le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr), + le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts)); +#endif + /* restart the transmitter */ + OUTL(dev, TxOn, ChipCmd); + + for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) { + if (i >= TOUT_LOOP) { + printf ("%s: tx error buffer not ready: txd.cmdsts %#X\n", + dev->name, tx_stat); + goto Done; + } + } + + if (!(tx_stat & DescPktOK)) { + printf("ns8382x_send: Transmit error, Tx status %X.\n", tx_stat); + goto Done; + } +#ifdef NS8382X_DEBUG + printf("ns8382x_send: tx_stat: %#08X\n", tx_stat); +#endif + + status = 1; + Done: + return status; +} + +/* Function: ns8382x_poll + * Description: checks for a received packet and returns it if found. + * Arguments: struct eth_device *dev: NIC data structure + * Returns: 1 if packet was received. + * 0 if no packet was received. + * Side effects: + * Returns (copies) the packet to the array dev->packet. + * Returns the length of the packet. + */ + +static int +ns8382x_poll(struct eth_device *dev) +{ + int retstat = 0; + int length = 0; + vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts); + + if (!(rx_status & (u32) DescOwn)) + return retstat; +#ifdef NS8382X_DEBUG + printf("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n", + cur_rx, rx_status); +#endif + length = (rx_status & DSIZE) - CRC_SIZE; + + if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) { + /* corrupted packet received */ + printf("ns8382x_poll: Corrupted packet, status:%lx\n", rx_status); + retstat = 0; + } else { + /* give packet to higher level routine */ + NetReceive((rxb + cur_rx * RX_BUF_SIZE), length); + retstat = 1; + } + + /* return the descriptor and buffer to receive ring */ + rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE); + rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]); + + if (++cur_rx == NUM_RX_DESC) + cur_rx = 0; + + /* re-enable the potentially idle receive state machine */ + OUTL(dev, RxOn, ChipCmd); + + return retstat; +} + +/* Function: ns8382x_disable + * Description: Turns off interrupts and stops Tx and Rx engines + * Arguments: struct eth_device *dev: NIC data structure + * Returns: void. + */ + +static void +ns8382x_disable(struct eth_device *dev) +{ + /* Disable interrupts using the mask. */ + OUTL(dev, 0, IntrMask); + OUTL(dev, 0, IntrEnable); + + /* Stop the chip's Tx and Rx processes. */ + OUTL(dev, (RxOff | TxOff), ChipCmd); + + /* Restore PME enable bit */ + OUTL(dev, SavedClkRun, ClkRun); +} + +#endif diff --git a/drivers/ns87308.c b/drivers/ns87308.c new file mode 100644 index 000000000..cf4d3595e --- /dev/null +++ b/drivers/ns87308.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_NS87308 + +#include + +void initialise_ns87308 (void) +{ +#ifdef CFG_NS87308_PS2MOD + unsigned char data; + + /* + * Switch floppy drive to PS/2 mode. + */ + read_pnp_config(SUPOERIO_CONF1, &data); + data &= 0xFB; + write_pnp_config(SUPOERIO_CONF1, data); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_KBC1) + PNP_SET_DEVICE_BASE(LDEV_KBC1, CFG_NS87308_KBC1_BASE); + write_pnp_config(LUN_CONFIG_REG, 0); + write_pnp_config(CBASE_HIGH, 0x00); + write_pnp_config(CBASE_LOW, 0x64); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_MOUSE) + PNP_ACTIVATE_DEVICE(LDEV_MOUSE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_RTC_APC) + PNP_SET_DEVICE_BASE(LDEV_RTC_APC, CFG_NS87308_RTC_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_FDC) + PNP_SET_DEVICE_BASE(LDEV_FDC, CFG_NS87308_FDC_BASE); + write_pnp_config(LUN_CONFIG_REG, 0x40); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_RARP) + PNP_SET_DEVICE_BASE(LDEV_PARP, CFG_NS87308_LPT_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_UART1) + PNP_SET_DEVICE_BASE(LDEV_UART1, CFG_NS87308_UART1_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_UART2) + PNP_SET_DEVICE_BASE(LDEV_UART2, CFG_NS87308_UART2_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_GPIO) + PNP_SET_DEVICE_BASE(LDEV_GPIO, CFG_NS87308_GPIO_BASE); +#endif + +#if (CFG_NS87308_DEVS & CFG_NS87308_POWRMAN) +#ifndef CFG_NS87308_PWMAN_BASE + PNP_ACTIVATE_DEVICE(LDEV_POWRMAN); +#else + PNP_SET_DEVICE_BASE(LDEV_POWRMAN, CFG_NS87308_PWMAN_BASE); + + /* + * Enable all units + */ + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_FER1, 0x7d); + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_FER2, 0x87); + +#ifdef CFG_NS87308_PMC1 + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC1, CFG_NS87308_PMC1); +#endif + +#ifdef CFG_NS87308_PMC2 + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC2, CFG_NS87308_PMC2); +#endif + +#ifdef CFG_NS87308_PMC3 + write_pm_reg(CFG_NS87308_PWMAN_BASE, PWM_PMC3, CFG_NS87308_PMC3); +#endif +#endif +#endif + +#ifdef CFG_NS87308_CS0_BASE + PNP_PGCS_CSLINE_BASE(0, CFG_NS87308_CS0_BASE); + PNP_PGCS_CSLINE_CONF(0, CFG_NS87308_CS0_CONF); +#endif + +#ifdef CFG_NS87308_CS1_BASE + PNP_PGCS_CSLINE_BASE(1, CFG_NS87308_CS1_BASE); + PNP_PGCS_CSLINE_CONF(1, CFG_NS87308_CS1_CONF); +#endif + +#ifdef CFG_NS87308_CS2_BASE + PNP_PGCS_CSLINE_BASE(2, CFG_NS87308_CS2_BASE); + PNP_PGCS_CSLINE_CONF(2, CFG_NS87308_CS2_CONF); +#endif +} + +#endif diff --git a/drivers/ns9750_eth.c b/drivers/ns9750_eth.c new file mode 100644 index 000000000..067ff8efa --- /dev/null +++ b/drivers/ns9750_eth.c @@ -0,0 +1,797 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_eth.c,v 1.2 2004/02/24 14:09:39 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Ethernet driver for the NS9750. Uses DMA Engine with polling + * interrupt status. But interrupts are not enabled. + * Only one tx buffer descriptor and the RXA buffer descriptor are used + * Currently no transmit lockup handling is included. eth_send has a 5s + * timeout for sending frames. No retransmits are performed when an + * error occurs. + * @References: [1] NS9750 Hardware Reference, December 2003 + * [2] Intel LXT971 Datasheet #249414 Rev. 02 + * [3] NS7520 Linux Ethernet Driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#include +#include /* NetSendPacket */ + +#include "ns9750_eth.h" /* for Ethernet and PHY */ + +#ifdef CONFIG_DRIVER_NS9750_ETHERNET + +/* some definition to make transistion to linux easier */ + +#define NS9750_DRIVER_NAME "eth" +#define KERN_WARNING "Warning:" +#define KERN_ERR "Error:" +#define KERN_INFO "Info:" + +#if 0 +# define DEBUG +#endif + +#ifdef DEBUG +# define printk printf + +# define DEBUG_INIT 0x0001 +# define DEBUG_MINOR 0x0002 +# define DEBUG_RX 0x0004 +# define DEBUG_TX 0x0008 +# define DEBUG_INT 0x0010 +# define DEBUG_POLL 0x0020 +# define DEBUG_LINK 0x0040 +# define DEBUG_MII 0x0100 +# define DEBUG_MII_LOW 0x0200 +# define DEBUG_MEM 0x0400 +# define DEBUG_ERROR 0x4000 +# define DEBUG_ERROR_CRIT 0x8000 + +static int nDebugLvl = DEBUG_ERROR_CRIT; + +# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \ + printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 ) +# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \ + printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 ) +# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\ + printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 ) +# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\ + printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0) +# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \ + printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0); +# define ASSERT( expr, func ) if( !( expr ) ) { \ + printf( "Assertion failed! %s:line %d %s\n", \ + (int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \ + func } +#else /* DEBUG */ +# define printk(...) +# define DEBUG_ARGS0( FLG, a0 ) +# define DEBUG_ARGS1( FLG, a0, a1 ) +# define DEBUG_ARGS2( FLG, a0, a1, a2 ) +# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) +# define DEBUG_FN( n ) +# define ASSERT(expr, func) +#endif /* DEBUG */ + +#define NS9750_MII_NEG_DELAY (5*CFG_HZ) /* in s */ +#define TX_TIMEOUT (5*CFG_HZ) /* in s */ + +/* @TODO move it to eeprom.h */ +#define FS_EEPROM_AUTONEG_MASK 0x7 +#define FS_EEPROM_AUTONEG_SPEED_MASK 0x1 +#define FS_EEPROM_AUTONEG_SPEED_10 0x0 +#define FS_EEPROM_AUTONEG_SPEED_100 0x1 +#define FS_EEPROM_AUTONEG_DUPLEX_MASK 0x2 +#define FS_EEPROM_AUTONEG_DUPLEX_HALF 0x0 +#define FS_EEPROM_AUTONEG_DUPLEX_FULL 0x2 +#define FS_EEPROM_AUTONEG_ENABLE_MASK 0x4 +#define FS_EEPROM_AUTONEG_DISABLE 0x0 +#define FS_EEPROM_AUTONEG_ENABLE 0x4 + +/* buffer descriptors taken from [1] p.306 */ +typedef struct +{ + unsigned int* punSrc; + unsigned int unLen; /* 11 bits */ + unsigned int* punDest; /* unused */ + union { + unsigned int unReg; + struct { + unsigned uStatus : 16; + unsigned uRes : 12; + unsigned uFull : 1; + unsigned uEnable : 1; + unsigned uInt : 1; + unsigned uWrap : 1; + } bits; + } s; +} rx_buffer_desc_t; + +typedef struct +{ + unsigned int* punSrc; + unsigned int unLen; /* 10 bits */ + unsigned int* punDest; /* unused */ + union { + unsigned int unReg; /* only 32bit accesses may done to NS9750 + * eth engine */ + struct { + unsigned uStatus : 16; + unsigned uRes : 12; + unsigned uFull : 1; + unsigned uLast : 1; + unsigned uInt : 1; + unsigned uWrap : 1; + } bits; + } s; +} tx_buffer_desc_t; + +static int ns9750_eth_reset( void ); + +static void ns9750_link_force( void ); +static void ns9750_link_auto_negotiate( void ); +static void ns9750_link_update_egcr( void ); +static void ns9750_link_print_changed( void ); + +/* the PHY stuff */ + +static char ns9750_mii_identify_phy( void ); +static unsigned short ns9750_mii_read( unsigned short uiRegister ); +static void ns9750_mii_write( unsigned short uiRegister, unsigned short uiData ); +static unsigned int ns9750_mii_get_clock_divisor( unsigned int unMaxMDIOClk ); +static unsigned int ns9750_mii_poll_busy( void ); + +static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK; +static unsigned char ucLinkMode = FS_EEPROM_AUTONEG_ENABLE; +static unsigned int uiLastLinkStatus; +static PhyType phyDetected = PHY_NONE; + +/* we use only one tx buffer descriptor */ +static tx_buffer_desc_t* pTxBufferDesc = + (tx_buffer_desc_t*) get_eth_reg_addr( NS9750_ETH_TXBD ); + +/* we use only one rx buffer descriptor of the 4 */ +static rx_buffer_desc_t aRxBufferDesc[ 4 ]; + +/*********************************************************************** + * @Function: eth_init + * @Return: -1 on failure otherwise 0 + * @Descr: Initializes the ethernet engine and uses either FS Forth's default + * MAC addr or the one in environment + ***********************************************************************/ + +int eth_init (bd_t * pbis) +{ + /* This default MAC Addr is reserved by FS Forth-Systeme for the case of + EEPROM failures */ + unsigned char aucMACAddr[6] = { 0x00, 0x04, 0xf3, 0x00, 0x06, 0x35 }; + char *pcTmp = getenv ("ethaddr"); + char *pcEnd; + int i; + + DEBUG_FN (DEBUG_INIT); + + /* no need to check for hardware */ + + if (!ns9750_eth_reset ()) + return -1; + + if (pcTmp != NULL) + for (i = 0; i < 6; i++) { + aucMACAddr[i] = + pcTmp ? simple_strtoul (pcTmp, &pcEnd, + 16) : 0; + pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd; + } + + /* configure ethernet address */ + + *get_eth_reg_addr (NS9750_ETH_SA1) = + aucMACAddr[5] << 8 | aucMACAddr[4]; + *get_eth_reg_addr (NS9750_ETH_SA2) = + aucMACAddr[3] << 8 | aucMACAddr[2]; + *get_eth_reg_addr (NS9750_ETH_SA3) = + aucMACAddr[1] << 8 | aucMACAddr[0]; + + /* enable hardware */ + + *get_eth_reg_addr (NS9750_ETH_MAC1) = NS9750_ETH_MAC1_RXEN; + + /* the linux kernel may give packets < 60 bytes, for example arp */ + *get_eth_reg_addr (NS9750_ETH_MAC2) = NS9750_ETH_MAC2_CRCEN | + NS9750_ETH_MAC2_PADEN | NS9750_ETH_MAC2_HUGE; + + /* enable receive and transmit FIFO, use 10/100 Mbps MII */ + *get_eth_reg_addr (NS9750_ETH_EGCR1) = + NS9750_ETH_EGCR1_ETXWM | + NS9750_ETH_EGCR1_ERX | + NS9750_ETH_EGCR1_ERXDMA | + NS9750_ETH_EGCR1_ETX | + NS9750_ETH_EGCR1_ETXDMA | NS9750_ETH_EGCR1_ITXA; + + /* prepare DMA descriptors */ + for (i = 0; i < 4; i++) { + aRxBufferDesc[i].punSrc = 0; + aRxBufferDesc[i].unLen = 0; + aRxBufferDesc[i].s.bits.uWrap = 1; + aRxBufferDesc[i].s.bits.uInt = 1; + aRxBufferDesc[i].s.bits.uEnable = 0; + aRxBufferDesc[i].s.bits.uFull = 0; + } + + /* NetRxPackets[ 0 ] is initialized before eth_init is called and never + changes. NetRxPackets is 32bit aligned */ + aRxBufferDesc[0].punSrc = (unsigned int *) NetRxPackets[0]; + aRxBufferDesc[0].s.bits.uEnable = 1; + aRxBufferDesc[0].unLen = 1522; /* as stated in [1] p.307 */ + + *get_eth_reg_addr (NS9750_ETH_RXAPTR) = + (unsigned int) &aRxBufferDesc[0]; + + /* [1] Tab. 221 states less than 5us */ + *get_eth_reg_addr (NS9750_ETH_EGCR1) |= NS9750_ETH_EGCR1_ERXINIT; + while (! + (*get_eth_reg_addr (NS9750_ETH_EGSR) & NS9750_ETH_EGSR_RXINIT)) + /* wait for finish */ + udelay (1); + + /* @TODO do we need to clear RXINIT? */ + *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~NS9750_ETH_EGCR1_ERXINIT; + + *get_eth_reg_addr (NS9750_ETH_RXFREE) = 0x1; + + return 0; +} + +/*********************************************************************** + * @Function: eth_send + * @Return: -1 on timeout otherwise 1 + * @Descr: sends one frame by DMA + ***********************************************************************/ + +int eth_send (volatile void *pPacket, int nLen) +{ + ulong ulTimeout; + + DEBUG_FN (DEBUG_TX); + + /* clear old status values */ + *get_eth_reg_addr (NS9750_ETH_EINTR) &= + *get_eth_reg_addr (NS9750_ETH_EINTR) & NS9750_ETH_EINTR_TX_MA; + + /* prepare Tx Descriptors */ + + pTxBufferDesc->punSrc = (unsigned int *) pPacket; /* pPacket is 32bit + * aligned */ + pTxBufferDesc->unLen = nLen; + /* only 32bit accesses allowed. wrap, full, interrupt and enabled to 1 */ + pTxBufferDesc->s.unReg = 0xf0000000; + /* pTxBufferDesc is the first possible buffer descriptor */ + *get_eth_reg_addr (NS9750_ETH_TXPTR) = 0x0; + + /* enable processor for next frame */ + + *get_eth_reg_addr (NS9750_ETH_EGCR2) &= ~NS9750_ETH_EGCR2_TCLER; + *get_eth_reg_addr (NS9750_ETH_EGCR2) |= NS9750_ETH_EGCR2_TCLER; + + ulTimeout = get_timer (0); + + DEBUG_ARGS0 (DEBUG_TX | DEBUG_MINOR, + "Waiting for transmission to finish\n"); + while (! + (*get_eth_reg_addr (NS9750_ETH_EINTR) & + (NS9750_ETH_EINTR_TXDONE | NS9750_ETH_EINTR_TXERR))) { + /* do nothing, wait for completion */ + if (get_timer (0) - ulTimeout > TX_TIMEOUT) { + DEBUG_ARGS0 (DEBUG_TX, "Transmit Timed out\n"); + return -1; + } + } + DEBUG_ARGS0 (DEBUG_TX | DEBUG_MINOR, "transmitted...\n"); + + return 0; +} + +/*********************************************************************** + * @Function: eth_rx + * @Return: size of last frame in bytes or 0 if no frame available + * @Descr: gives one frame to U-Boot which has been copied by DMA engine already + * to NetRxPackets[ 0 ]. + ***********************************************************************/ + +int eth_rx (void) +{ + int nLen = 0; + unsigned int unStatus; + + unStatus = + *get_eth_reg_addr (NS9750_ETH_EINTR) & NS9750_ETH_EINTR_RX_MA; + + if (!unStatus) + /* no packet available, return immediately */ + return 0; + + DEBUG_FN (DEBUG_RX); + + /* unLen always < max(nLen) and discard checksum */ + nLen = (int) aRxBufferDesc[0].unLen - 4; + + /* acknowledge status register */ + *get_eth_reg_addr (NS9750_ETH_EINTR) = unStatus; + + aRxBufferDesc[0].unLen = 1522; + aRxBufferDesc[0].s.bits.uFull = 0; + + /* Buffer A descriptor available again */ + *get_eth_reg_addr (NS9750_ETH_RXFREE) |= 0x1; + + /* NetReceive may call eth_send. Due to a possible bug of the NS9750 we + * have to acknowledge the received frame before sending a new one */ + if (unStatus & NS9750_ETH_EINTR_RXDONEA) + NetReceive (NetRxPackets[0], nLen); + + return nLen; +} + +/*********************************************************************** + * @Function: eth_halt + * @Return: n/a + * @Descr: stops the ethernet engine + ***********************************************************************/ + +void eth_halt (void) +{ + DEBUG_FN (DEBUG_INIT); + + *get_eth_reg_addr (NS9750_ETH_MAC1) &= ~NS9750_ETH_MAC1_RXEN; + *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~(NS9750_ETH_EGCR1_ERX | + NS9750_ETH_EGCR1_ERXDMA | + NS9750_ETH_EGCR1_ETX | + NS9750_ETH_EGCR1_ETXDMA); +} + +/*********************************************************************** + * @Function: ns9750_eth_reset + * @Return: 0 on failure otherwise 1 + * @Descr: resets the ethernet interface and the PHY, + * performs auto negotiation or fixed modes + ***********************************************************************/ + +static int ns9750_eth_reset (void) +{ + DEBUG_FN (DEBUG_MINOR); + + /* Reset MAC */ + *get_eth_reg_addr (NS9750_ETH_EGCR1) |= NS9750_ETH_EGCR1_MAC_HRST; + udelay (5); /* according to [1], p.322 */ + *get_eth_reg_addr (NS9750_ETH_EGCR1) &= ~NS9750_ETH_EGCR1_MAC_HRST; + + /* reset and initialize PHY */ + + *get_eth_reg_addr (NS9750_ETH_MAC1) &= ~NS9750_ETH_MAC1_SRST; + + /* we don't support hot plugging of PHY, therefore we don't reset + phyDetected and nPhyMaxMdioClock here. The risk is if the setting is + incorrect the first open + may detect the PHY correctly but succeding will fail + For reseting the PHY and identifying we have to use the standard + MDIO CLOCK value 2.5 MHz only after hardware reset + After having identified the PHY we will do faster */ + + *get_eth_reg_addr (NS9750_ETH_MCFG) = + ns9750_mii_get_clock_divisor (nPhyMaxMdioClock); + + /* reset PHY */ + ns9750_mii_write (PHY_COMMON_CTRL, PHY_COMMON_CTRL_RESET); + ns9750_mii_write (PHY_COMMON_CTRL, 0); + + /* @TODO check time */ + udelay (3000); /* [2] p.70 says at least 300us reset recovery time. But + go sure, it didn't worked stable at higher timer + frequencies under LxNETES-2.x */ + + /* MII clock has been setup to default, ns9750_mii_identify_phy should + work for all */ + + if (!ns9750_mii_identify_phy ()) { + printk (KERN_ERR NS9750_DRIVER_NAME + ": Unsupported PHY, aborting\n"); + return 0; + } + + /* now take the highest MDIO clock possible after detection */ + *get_eth_reg_addr (NS9750_ETH_MCFG) = + ns9750_mii_get_clock_divisor (nPhyMaxMdioClock); + + + /* PHY has been detected, so there can be no abort reason and we can + finish initializing ethernet */ + + uiLastLinkStatus = 0xff; /* undefined */ + + if ((ucLinkMode & FS_EEPROM_AUTONEG_ENABLE_MASK) == + FS_EEPROM_AUTONEG_DISABLE) + /* use parameters defined */ + ns9750_link_force (); + else + ns9750_link_auto_negotiate (); + + if (phyDetected == PHY_LXT971A) + /* set LED2 to link mode */ + ns9750_mii_write (PHY_LXT971_LED_CFG, + PHY_LXT971_LED_CFG_LINK_ACT << + PHY_LXT971_LED_CFG_SHIFT_LED2); + + return 1; +} + +/*********************************************************************** + * @Function: ns9750_link_force + * @Return: void + * @Descr: configures eth and MII to use the link mode defined in + * ucLinkMode + ***********************************************************************/ + +static void ns9750_link_force (void) +{ + unsigned short uiControl; + + DEBUG_FN (DEBUG_LINK); + + uiControl = ns9750_mii_read (PHY_COMMON_CTRL); + uiControl &= ~(PHY_COMMON_CTRL_SPD_MA | + PHY_COMMON_CTRL_AUTO_NEG | PHY_COMMON_CTRL_DUPLEX); + + uiLastLinkStatus = 0; + + if ((ucLinkMode & FS_EEPROM_AUTONEG_SPEED_MASK) == + FS_EEPROM_AUTONEG_SPEED_100) { + uiControl |= PHY_COMMON_CTRL_SPD_100; + uiLastLinkStatus |= PHY_LXT971_STAT2_100BTX; + } else + uiControl |= PHY_COMMON_CTRL_SPD_10; + + if ((ucLinkMode & FS_EEPROM_AUTONEG_DUPLEX_MASK) == + FS_EEPROM_AUTONEG_DUPLEX_FULL) { + uiControl |= PHY_COMMON_CTRL_DUPLEX; + uiLastLinkStatus |= PHY_LXT971_STAT2_DUPLEX_MODE; + } + + ns9750_mii_write (PHY_COMMON_CTRL, uiControl); + + ns9750_link_print_changed (); + ns9750_link_update_egcr (); +} + +/*********************************************************************** + * @Function: ns9750_link_auto_negotiate + * @Return: void + * @Descr: performs auto-negotation of link. + ***********************************************************************/ + +static void ns9750_link_auto_negotiate (void) +{ + unsigned long ulStartJiffies; + unsigned short uiStatus; + + DEBUG_FN (DEBUG_LINK); + + /* run auto-negotation */ + /* define what we are capable of */ + ns9750_mii_write (PHY_COMMON_AUTO_ADV, + PHY_COMMON_AUTO_ADV_100BTXFD | + PHY_COMMON_AUTO_ADV_100BTX | + PHY_COMMON_AUTO_ADV_10BTFD | + PHY_COMMON_AUTO_ADV_10BT | + PHY_COMMON_AUTO_ADV_802_3); + /* start auto-negotiation */ + ns9750_mii_write (PHY_COMMON_CTRL, + PHY_COMMON_CTRL_AUTO_NEG | + PHY_COMMON_CTRL_RES_AUTO); + + /* wait for completion */ + + ulStartJiffies = get_ticks (); + while (get_ticks () < ulStartJiffies + NS9750_MII_NEG_DELAY) { + uiStatus = ns9750_mii_read (PHY_COMMON_STAT); + if ((uiStatus & + (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) == + (PHY_COMMON_STAT_AN_COMP | PHY_COMMON_STAT_LNK_STAT)) { + /* lucky we are, auto-negotiation succeeded */ + ns9750_link_print_changed (); + ns9750_link_update_egcr (); + return; + } + } + + DEBUG_ARGS0 (DEBUG_LINK, "auto-negotiation timed out\n"); + /* ignore invalid link settings */ +} + +/*********************************************************************** + * @Function: ns9750_link_update_egcr + * @Return: void + * @Descr: updates the EGCR and MAC2 link status after mode change or + * auto-negotation + ***********************************************************************/ + +static void ns9750_link_update_egcr (void) +{ + unsigned int unEGCR; + unsigned int unMAC2; + unsigned int unIPGT; + + DEBUG_FN (DEBUG_LINK); + + unEGCR = *get_eth_reg_addr (NS9750_ETH_EGCR1); + unMAC2 = *get_eth_reg_addr (NS9750_ETH_MAC2); + unIPGT = *get_eth_reg_addr (NS9750_ETH_IPGT) & ~NS9750_ETH_IPGT_MA; + + unMAC2 &= ~NS9750_ETH_MAC2_FULLD; + if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE) + == PHY_LXT971_STAT2_DUPLEX_MODE) { + unMAC2 |= NS9750_ETH_MAC2_FULLD; + unIPGT |= 0x15; /* see [1] p. 339 */ + } else + unIPGT |= 0x12; /* see [1] p. 339 */ + + *get_eth_reg_addr (NS9750_ETH_MAC2) = unMAC2; + *get_eth_reg_addr (NS9750_ETH_EGCR1) = unEGCR; + *get_eth_reg_addr (NS9750_ETH_IPGT) = unIPGT; +} + +/*********************************************************************** + * @Function: ns9750_link_print_changed + * @Return: void + * @Descr: checks whether the link status has changed and if so prints + * the new mode + ***********************************************************************/ + +static void ns9750_link_print_changed (void) +{ + unsigned short uiStatus; + unsigned short uiControl; + + DEBUG_FN (DEBUG_LINK); + + uiControl = ns9750_mii_read (PHY_COMMON_CTRL); + + if ((uiControl & PHY_COMMON_CTRL_AUTO_NEG) == + PHY_COMMON_CTRL_AUTO_NEG) { + /* PHY_COMMON_STAT_LNK_STAT is only set on autonegotiation */ + uiStatus = ns9750_mii_read (PHY_COMMON_STAT); + + if (!(uiStatus & PHY_COMMON_STAT_LNK_STAT)) { + printk (KERN_WARNING NS9750_DRIVER_NAME + ": link down\n"); + /* @TODO Linux: carrier_off */ + } else { + /* @TODO Linux: carrier_on */ + if (phyDetected == PHY_LXT971A) { + uiStatus = ns9750_mii_read (PHY_LXT971_STAT2); + uiStatus &= (PHY_LXT971_STAT2_100BTX | + PHY_LXT971_STAT2_DUPLEX_MODE | + PHY_LXT971_STAT2_AUTO_NEG); + + /* mask out all uninteresting parts */ + } + /* other PHYs must store there link information in + uiStatus as PHY_LXT971 */ + } + } else { + /* mode has been forced, so uiStatus should be the same as the + last link status, enforce printing */ + uiStatus = uiLastLinkStatus; + uiLastLinkStatus = 0xff; + } + + if (uiStatus != uiLastLinkStatus) { + /* save current link status */ + uiLastLinkStatus = uiStatus; + + /* print new link status */ + + printk (KERN_INFO NS9750_DRIVER_NAME + ": link mode %i Mbps %s duplex %s\n", + (uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10, + (uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" : + "half", + (uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" : + ""); + } +} + +/*********************************************************************** + * the MII low level stuff + ***********************************************************************/ + +/*********************************************************************** + * @Function: ns9750_mii_identify_phy + * @Return: 1 if supported PHY has been detected otherwise 0 + * @Descr: checks for supported PHY and prints the IDs. + ***********************************************************************/ + +static char ns9750_mii_identify_phy (void) +{ + unsigned short uiID1; + unsigned short uiID2; + unsigned char *szName; + char cRes = 0; + + DEBUG_FN (DEBUG_MII); + + phyDetected = (PhyType) uiID1 = ns9750_mii_read (PHY_COMMON_ID1); + + switch (phyDetected) { + case PHY_LXT971A: + szName = "LXT971A"; + uiID2 = ns9750_mii_read (PHY_COMMON_ID2); + nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK; + cRes = 1; + break; + case PHY_NONE: + default: + /* in case uiID1 == 0 && uiID2 == 0 we may have the wrong + address or reset sets the wrong NS9750_ETH_MCFG_CLKS */ + + uiID2 = 0; + szName = "unknown"; + nPhyMaxMdioClock = PHY_MDIO_MAX_CLK; + phyDetected = PHY_NONE; + } + + printk (KERN_INFO NS9750_DRIVER_NAME + ": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName); + + return cRes; +} + +/*********************************************************************** + * @Function: ns9750_mii_read + * @Return: the data read from PHY register uiRegister + * @Descr: the data read may be invalid if timed out. If so, a message + * is printed but the invalid data is returned. + * The fixed device address is being used. + ***********************************************************************/ + +static unsigned short ns9750_mii_read (unsigned short uiRegister) +{ + DEBUG_FN (DEBUG_MII_LOW); + + /* write MII register to be read */ + *get_eth_reg_addr (NS9750_ETH_MADR) = + NS9750_ETH_PHY_ADDRESS << 8 | uiRegister; + + *get_eth_reg_addr (NS9750_ETH_MCMD) = NS9750_ETH_MCMD_READ; + + if (!ns9750_mii_poll_busy ()) + printk (KERN_WARNING NS9750_DRIVER_NAME + ": MII still busy in read\n"); + /* continue to read */ + + *get_eth_reg_addr (NS9750_ETH_MCMD) = 0; + + return (unsigned short) (*get_eth_reg_addr (NS9750_ETH_MRDD)); +} + + +/*********************************************************************** + * @Function: ns9750_mii_write + * @Return: nothing + * @Descr: writes the data to the PHY register. In case of a timeout, + * no special handling is performed but a message printed + * The fixed device address is being used. + ***********************************************************************/ + +static void ns9750_mii_write (unsigned short uiRegister, + unsigned short uiData) +{ + DEBUG_FN (DEBUG_MII_LOW); + + /* write MII register to be written */ + *get_eth_reg_addr (NS9750_ETH_MADR) = + NS9750_ETH_PHY_ADDRESS << 8 | uiRegister; + + *get_eth_reg_addr (NS9750_ETH_MWTD) = uiData; + + if (!ns9750_mii_poll_busy ()) { + printf (KERN_WARNING NS9750_DRIVER_NAME + ": MII still busy in write\n"); + } +} + + +/*********************************************************************** + * @Function: ns9750_mii_get_clock_divisor + * @Return: the clock divisor that should be used in NS9750_ETH_MCFG_CLKS + * @Descr: if no clock divisor can be calculated for the + * current SYSCLK and the maximum MDIO Clock, a warning is printed + * and the greatest divisor is taken + ***********************************************************************/ + +static unsigned int ns9750_mii_get_clock_divisor (unsigned int unMaxMDIOClk) +{ + struct { + unsigned int unSysClkDivisor; + unsigned int unClks; /* field for NS9750_ETH_MCFG_CLKS */ + } PHYClockDivisors[] = { + { + 4, NS9750_ETH_MCFG_CLKS_4}, { + 6, NS9750_ETH_MCFG_CLKS_6}, { + 8, NS9750_ETH_MCFG_CLKS_8}, { + 10, NS9750_ETH_MCFG_CLKS_10}, { + 20, NS9750_ETH_MCFG_CLKS_20}, { + 30, NS9750_ETH_MCFG_CLKS_30}, { + 40, NS9750_ETH_MCFG_CLKS_40} + }; + + int nIndexSysClkDiv; + int nArraySize = + sizeof (PHYClockDivisors) / sizeof (PHYClockDivisors[0]); + unsigned int unClks = NS9750_ETH_MCFG_CLKS_40; /* defaults to + greatest div */ + + DEBUG_FN (DEBUG_INIT); + + for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize; + nIndexSysClkDiv++) { + /* find first sysclock divisor that isn't higher than 2.5 MHz + clock */ + if (AHB_CLK_FREQ / + PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <= + unMaxMDIOClk) { + unClks = PHYClockDivisors[nIndexSysClkDiv].unClks; + break; + } + } + + DEBUG_ARGS2 (DEBUG_INIT, + "Taking MDIO Clock bit mask 0x%0x for max clock %i\n", + unClks, unMaxMDIOClk); + + /* return greatest divisor */ + return unClks; +} + +/*********************************************************************** + * @Function: ns9750_mii_poll_busy + * @Return: 0 if timed out otherwise the remaing timeout + * @Descr: waits until the MII has completed a command or it times out + * code may be interrupted by hard interrupts. + * It is not checked what happens on multiple actions when + * the first is still being busy and we timeout. + ***********************************************************************/ + +static unsigned int ns9750_mii_poll_busy (void) +{ + unsigned int unTimeout = 10000; + + DEBUG_FN (DEBUG_MII_LOW); + + while (((*get_eth_reg_addr (NS9750_ETH_MIND) & NS9750_ETH_MIND_BUSY) + == NS9750_ETH_MIND_BUSY) && unTimeout) + unTimeout--; + + return unTimeout; +} + +#endif /* CONFIG_DRIVER_NS9750_ETHERNET */ diff --git a/drivers/ns9750_serial.c b/drivers/ns9750_serial.c new file mode 100644 index 000000000..8dff36774 --- /dev/null +++ b/drivers/ns9750_serial.c @@ -0,0 +1,210 @@ +/*********************************************************************** + * + * Copyright (C) 2004 by FS Forth-Systeme GmbH. + * All rights reserved. + * + * $Id: ns9750_serial.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $ + * @Author: Markus Pietrek + * @Descr: Serial driver for the NS9750. Only one UART is supported yet. + * @References: [1] NS9750 Hardware Reference/December 2003 + * @TODO: Implement Character GAP Timer when chip is fixed for PLL bypass + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ***********************************************************************/ + +#include + +#ifdef CFG_NS9750_UART + +#include "ns9750_bbus.h" /* for GPIOs */ +#include "ns9750_ser.h" /* for serial configuration */ + +DECLARE_GLOBAL_DATA_PTR; + +#define CONSOLE CONFIG_CONS_INDEX + +static unsigned int calcBitrateRegister( void ); +static unsigned int calcRxCharGapRegister( void ); + +static char cCharsAvailable; /* Numbers of chars in unCharCache */ +static unsigned int unCharCache; /* unCharCache is only valid if + * cCharsAvailable > 0 */ + +/*********************************************************************** + * @Function: serial_init + * @Return: 0 + * @Descr: configures GPIOs and UART. Requires BBUS Master Reset turned off + ***********************************************************************/ + +int serial_init( void ) +{ + unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 }; + unsigned int aunGPIORxD[] = { 1, 9, 41, 45 }; + + cCharsAvailable = 0; + + /* configure TxD and RxD pins for their special function */ + set_gpio_cfg_reg_val( aunGPIOTxD[ CONSOLE ], + NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_OUTPUT ); + set_gpio_cfg_reg_val( aunGPIORxD[ CONSOLE ], + NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_INPUT ); + + /* configure serial engine */ + *get_ser_reg_addr_channel( NS9750_SER_CTRL_A, CONSOLE ) = + NS9750_SER_CTRL_A_CE | + NS9750_SER_CTRL_A_STOP | + NS9750_SER_CTRL_A_WLS_8; + + serial_setbrg(); + + *get_ser_reg_addr_channel( NS9750_SER_CTRL_B, CONSOLE ) = + NS9750_SER_CTRL_B_RCGT; + + return 0; +} + +/*********************************************************************** + * @Function: serial_putc + * @Return: n/a + * @Descr: writes one character to the FIFO. Blocks until FIFO is not full + ***********************************************************************/ + +void serial_putc( const char c ) +{ + if (c == '\n') + serial_putc( '\r' ); + + while (!(*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE) & + NS9750_SER_STAT_A_TRDY ) ) { + /* do nothing, wait for characters in FIFO sent */ + } + + *(volatile char*) get_ser_reg_addr_channel( NS9750_SER_FIFO, + CONSOLE) = c; +} + +/*********************************************************************** + * @Function: serial_puts + * @Return: n/a + * @Descr: writes non-zero string to the FIFO. + ***********************************************************************/ + +void serial_puts( const char *s ) +{ + while (*s) { + serial_putc( *s++ ); + } +} + +/*********************************************************************** + * @Function: serial_getc + * @Return: the character read + * @Descr: performs only 8bit accesses to the FIFO. No error handling + ***********************************************************************/ + +int serial_getc( void ) +{ + int i; + + while (!serial_tstc() ) { + /* do nothing, wait for incoming characters */ + } + + /* at least one character in unCharCache */ + i = (int) (unCharCache & 0xff); + + unCharCache >>= 8; + cCharsAvailable--; + + return i; +} + +/*********************************************************************** + * @Function: serial_tstc + * @Return: 0 if no input available, otherwise != 0 + * @Descr: checks for incoming FIFO not empty. Stores the incoming chars in + * unCharCache and the numbers of characters in cCharsAvailable + ***********************************************************************/ + +int serial_tstc( void ) +{ + unsigned int unRegCache; + + if ( cCharsAvailable ) + return 1; + + unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,CONSOLE ); + if( unRegCache & NS9750_SER_STAT_A_RBC ) { + *get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE ) = + NS9750_SER_STAT_A_RBC; + unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A, + CONSOLE ); + } + + if ( unRegCache & NS9750_SER_STAT_A_RRDY ) { + cCharsAvailable = (unRegCache & NS9750_SER_STAT_A_RXFDB_MA)>>20; + if ( !cCharsAvailable ) + cCharsAvailable = 4; + + unCharCache = *get_ser_reg_addr_channel( NS9750_SER_FIFO, + CONSOLE ); + return 1; + } + + /* no chars available */ + return 0; +} + +void serial_setbrg( void ) +{ + *get_ser_reg_addr_channel( NS9750_SER_BITRATE, CONSOLE ) = + calcBitrateRegister(); + *get_ser_reg_addr_channel( NS9750_SER_RX_CHAR_TIMER, CONSOLE ) = + calcRxCharGapRegister(); +} + +/*********************************************************************** + * @Function: calcBitrateRegister + * @Return: value for the serial bitrate register + * @Descr: register value depends on clock frequency and baudrate + ***********************************************************************/ + +static unsigned int calcBitrateRegister( void ) +{ + return ( NS9750_SER_BITRATE_EBIT | + NS9750_SER_BITRATE_CLKMUX_BCLK | + NS9750_SER_BITRATE_TMODE | + NS9750_SER_BITRATE_TCDR_16 | + NS9750_SER_BITRATE_RCDR_16 | + ( ( ( ( CONFIG_SYS_CLK_FREQ / 8 ) / /* BBUS clock,[1] Fig. 38 */ + ( gd->baudrate * 16 ) ) - 1 ) & + NS9750_SER_BITRATE_N_MA ) ); +} + +/*********************************************************************** + * @Function: calcRxCharGapRegister + * @Return: value for the character gap timer register + * @Descr: register value depends on clock frequency and baudrate. Currently 0 + * is used as there is a bug with the gap timer in PLL bypass mode. + ***********************************************************************/ + +static unsigned int calcRxCharGapRegister( void ) +{ + return NS9750_SER_RX_CHAR_TIMER_TRUN; +} + +#endif /* CFG_NS9750_UART */ diff --git a/drivers/omap1510_i2c.c b/drivers/omap1510_i2c.c new file mode 100644 index 000000000..04400fbcd --- /dev/null +++ b/drivers/omap1510_i2c.c @@ -0,0 +1,281 @@ +/* + * Basic I2C functions + * + * Copyright (c) 2003 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Author: Jian Zhang jzhang@ti.com, Texas Instruments + * + * Copyright (c) 2003 Wolfgang Denk, wd@denx.de + * Rewritten to fit into the current U-Boot framework + * + */ + +#include + +#ifdef CONFIG_DRIVER_OMAP1510_I2C + +static void wait_for_bb (void); +static u16 wait_for_pin (void); + +void i2c_init (int speed, int slaveadd) +{ + u16 scl; + + if (inw (I2C_CON) & I2C_CON_EN) { + outw (0, I2C_CON); + udelay (5000); + } + + /* 12Mhz I2C module clock */ + outw (0, I2C_PSC); + outw (I2C_CON_EN, I2C_CON); + outw (0, I2C_SYSTEST); + /* have to enable intrrupts or OMAP i2c module doesn't work */ + outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | + I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + scl = (12000000 / 2) / speed - 6; + outw (scl, I2C_SCLL); + outw (scl, I2C_SCLH); + /* own address */ + outw (slaveadd, I2C_OA); + outw (0, I2C_CNT); + udelay (1000); +} + +static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) +{ + int i2c_error = 0; + u16 status; + + /* wait until bus not busy */ + wait_for_bb (); + + /* one byte only */ + outw (1, I2C_CNT); + /* set slave address */ + outw (devaddr, I2C_SA); + /* no stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { + /* Important: have to use byte access */ + *(volatile u8 *) (I2C_DATA) = regoffset; + udelay (20000); + if (inw (I2C_STAT) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + /* free bus, otherwise we can't use a combined transction */ + outw (0, I2C_CON); + while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (10000); + /* Have to clear pending interrupt to clear I2C_STAT */ + inw (I2C_IV); + } + + wait_for_bb (); + /* set slave address */ + outw (devaddr, I2C_SA); + /* read one byte from slave */ + outw (1, I2C_CNT); + /* need stop bit here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, + I2C_CON); + + status = wait_for_pin (); + if (status & I2C_STAT_RRDY) { + *value = inw (I2C_DATA); + udelay (20000); + } else { + i2c_error = 1; + } + + if (!i2c_error) { + outw (I2C_CON_EN, I2C_CON); + while (inw (I2C_STAT) + || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (10000); + inw (I2C_IV); + } + } + } + + return i2c_error; +} + +static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) +{ + int i2c_error = 0; + u16 status; + + /* wait until bus not busy */ + wait_for_bb (); + + /* two bytes */ + outw (2, I2C_CNT); + /* set slave address */ + outw (devaddr, I2C_SA); + /* stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, I2C_CON); + + /* wait until state change */ + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { + /* send out two bytes */ + outw ((value << 8) + regoffset, I2C_DATA); + /* must have enough delay to allow BB bit to go low */ + udelay (30000); + if (inw (I2C_STAT) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + outw (I2C_CON_EN, I2C_CON); + while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { + udelay (1000); + /* have to read to clear intrrupt */ + inw (I2C_IV); + } + } + + return i2c_error; +} + +int i2c_probe (uchar chip) +{ + int res = 1; + + if (chip == inw (I2C_OA)) { + return res; + } + + /* wait until bus not busy */ + wait_for_bb (); + + /* try to read one byte */ + outw (1, I2C_CNT); + /* set slave address */ + outw (chip, I2C_SA); + /* stop bit needed here */ + outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + /* enough delay for the NACK bit set */ + udelay (2000); + if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { + res = 0; + } else { + outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); + udelay (20); + wait_for_bb (); + } + + return res; +} + +int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf ("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_read_byte (chip, addr + i, &buffer[i])) { + printf ("I2C read: I/O error\n"); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + return 1; + } + } + + return 0; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf ("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_write_byte (chip, addr + i, buffer[i])) { + printf ("I2C read: I/O error\n"); + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + return 1; + } + } + + return 0; +} + +static void wait_for_bb (void) +{ + int timeout = 10; + + while ((inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { + inw (I2C_IV); + udelay (1000); + } + + if (timeout <= 0) { + printf ("timed out in wait_for_bb: I2C_STAT=%x\n", + inw (I2C_STAT)); + } +} + +static u16 wait_for_pin (void) +{ + u16 status, iv; + int timeout = 10; + + do { + udelay (1000); + status = inw (I2C_STAT); + iv = inw (I2C_IV); + } while (!iv && + !(status & + (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | + I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL)) && timeout--); + + if (timeout <= 0) { + printf ("timed out in wait_for_pin: I2C_STAT=%x\n", + inw (I2C_STAT)); + } + + return status; +} + +#endif /* CONFIG_DRIVER_OMAP1510_I2C */ diff --git a/drivers/omap24xx_i2c.c b/drivers/omap24xx_i2c.c new file mode 100644 index 000000000..113b64900 --- /dev/null +++ b/drivers/omap24xx_i2c.c @@ -0,0 +1,544 @@ +/* + * Basic I2C functions + * + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Author: Jian Zhang jzhang@ti.com, Texas Instruments + * + * Copyright (c) 2003 Wolfgang Denk, wd@denx.de + * Rewritten to fit into the current U-Boot framework + * + * Adapted for OMAP2420 I2C, r-woodruff2@ti.com + * + */ + +#include + +#if defined(CONFIG_DRIVER_OMAP24XX_I2C) || defined(CONFIG_DRIVER_OMAP34XX_I2C) + +#include +#include +#include + +static u32 i2c_base = I2C_DEFAULT_BASE; +static u32 i2c_speed = CFG_I2C_SPEED; + +//#define DEBUG + +#ifdef DEBUG + +#define DBG(ARGS...) {printf ("[%d]",__LINE__);printf(ARGS);} +#define inb(a) ({u8 v=__raw_readb(i2c_base + (a));printf("%d:Rb[%x<=%x]\n",__LINE__,a,v);v;}) +#define outb(v,a) {printf("%d:Wb[%x<=%x]\n",__LINE__,a,v);__raw_writeb((v), (i2c_base + (a)));} +#define inw(a) ({u16 v=__raw_readb(i2c_base + (a));printf("%d:Rw[%x<=%x]\n",__LINE__,a,v);v;}) +#define outw(v,a) {printf("%d:Ww[%x<=%x]\n",__LINE__,a,v);__raw_writew((v), (i2c_base + (a)));} + +#else +#define DBG(ARGS...) +#define inb(a) __raw_readb(i2c_base + (a)) +#define outb(v,a) __raw_writeb((v), (i2c_base + (a))) +#define inw(a) __raw_readw(i2c_base +(a)) +#define outw(v,a) __raw_writew((v), (i2c_base + (a))) +#endif + +static void wait_for_bb(void); +static u16 wait_for_pin(void); +static void flush_fifo(void); + +#ifdef CONFIG_OMAP34XX +#define I2C_NUM_IF 3 +#else +#define I2C_NUM_IF 2 +#endif + +int select_bus(int bus, int speed) +{ + if ((bus < 0) || (bus >= I2C_NUM_IF)) { + printf("Bad bus ID-%d\n", bus); + return -1; + } + +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + /* Check speed */ + if ((speed != OMAP_I2C_STANDARD) && (speed != OMAP_I2C_FAST_MODE) + && (speed != OMAP_I2C_HIGH_SPEED)) { + printf("Invalid Speed for i2c init-%d\n", speed); + return -1; + } +#else + if ((speed != OMAP_I2C_STANDARD) && (speed != OMAP_I2C_FAST_MODE)) { + printf("Invalid Speed for i2c init-%d\n", speed); + return -1; + } +#endif + +#if defined(CONFIG_OMAP34XX) + if (bus == 2) + i2c_base = I2C_BASE3; + else +#endif + if (bus == 1) + i2c_base = I2C_BASE2; + else + i2c_base = I2C_BASE1; + + i2c_init(speed, CFG_I2C_SLAVE); + return 0; +} + +void i2c_init(int speed, int slaveadd) +{ + int psc, fsscll, fssclh; + int hsscll = 0, hssclh = 0; + u32 scll, sclh, scl; + int reset_timeout = 10; + unsigned long internal_clk; + + /* Only handle standard, fast and high speeds */ + if ((speed != OMAP_I2C_STANDARD) && + (speed != OMAP_I2C_FAST_MODE) && + (speed != OMAP_I2C_HIGH_SPEED)) { + printf("Error : I2C unsupported speed %d\n", speed); + return; + } + + /* + * Set the internal sampling clock to what the + * board requires if it is defined. Else use + * the values in the v2.6.31 kernel. + */ +#if defined(I2C_INTERNAL_SAMPLING_CLK) + internal_clk = I2C_INTERNAL_SAMPLING_CLK; +#else + /* standard */ + internal_clk = 4000; + if (speed == OMAP_I2C_HIGH_SPEED) + internal_clk = 19200; + else if (speed == OMAP_I2C_FAST_MODE) + internal_clk = 9600; + else /* standard */ + internal_clk = 4000; +#endif + + psc = I2C_IP_CLK / internal_clk; + psc -= 1; + if (psc < I2C_PSC_MIN) { + printf("Error : I2C unsupported prescalar %d\n", psc); + return; + } + + if (speed == OMAP_I2C_HIGH_SPEED) { + /* High speed */ + + /* For first phase of HS mode */ + scl = internal_clk / 400; + fsscll = scl - (scl / 3) - I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; + fssclh = (scl / 3) - I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; + + if (((fsscll < 0) || (fssclh < 0)) || + ((fsscll > 255) || (fssclh > 255))) { + printf("Error : I2C initializing clock\n"); + return; + } + + /* For second phase of HS mode */ + scl = I2C_IP_CLK / speed; + hsscll = scl - (scl / 3) - I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; + hssclh = (scl / 3) - I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; + + if (((hsscll < 0) || (hssclh < 0)) || + ((hsscll > 255) || (hssclh > 255))) { + printf("Error : I2C initializing second phase clock\n"); + return; + } + + scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; + sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; + + } else if (speed == OMAP_I2C_FAST_MODE) { + /* Standard speed */ + scl = internal_clk / speed; + fsscll = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM; + fssclh = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM; + + if (((fsscll < 0) || (fssclh < 0)) || + ((fsscll > 255) || (fssclh > 255))) { + printf("Error : I2C initializing clock\n"); + return; + } + + scll = (unsigned int)fsscll; + sclh = (unsigned int)fssclh; + + } else { + /* Standard speed */ + fsscll = fssclh = internal_clk / (2 * speed); + + fsscll -= I2C_FASTSPEED_SCLL_TRIM; + fssclh -= I2C_FASTSPEED_SCLH_TRIM; + + if (((fsscll < 0) || (fssclh < 0)) || + ((fsscll > 255) || (fssclh > 255))) { + printf("Error : I2C initializing clock\n"); + return; + } + + scll = (unsigned int)fsscll; + sclh = (unsigned int)fssclh; + } + + /* Execute Soft-reset sequence for I2C controller */ + reset_timeout = 100; + while ((inw(I2C_CON) & I2C_CON_EN) && reset_timeout--) { + /* Ensure that the module is disabled */ + outw(0, I2C_CON); + } + if (reset_timeout <= 0) + printf("ERROR: Timeout to Disable the Module\n"); + + outw(I2C_SYSC_SRST, I2C_SYSC); /* Set the I2Ci.I2C_SYSC[1] SRST bit to 1 */ + udelay(1000); + outw(I2C_CON_EN, I2C_CON); /* Enable the module */ + + reset_timeout = 100; + while (!(inw(I2C_SYSS) & I2C_SYSS_RDONE) && reset_timeout--) { + if (reset_timeout <= 0) + printf("ERROR: Timeout while waiting for soft-reset to complete\n"); + } + + outw(0, I2C_CON); /* Disable I2C controller before writing + to PSC and SCL registers */ + outw(psc, I2C_PSC); + outw(scll, I2C_SCLL); + outw(sclh, I2C_SCLH); + + /* own address */ + outw(slaveadd, I2C_OA); + outw(I2C_CON_EN, I2C_CON); + + /* have to enable intrrupts or OMAP i2c module doesn't work */ + outw(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | + I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + udelay(1000); + flush_fifo(); + outw(0xFFFF, I2C_STAT); + outw(0, I2C_CNT); +} + +static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 * value) +{ + int err; + int i2c_error = 0; + u16 status; + + /* wait until bus not busy */ + wait_for_bb(); + + /* one byte only */ + outw(1, I2C_CNT); + /* set slave address */ + outw(devaddr, I2C_SA); + /* no stop bit needed here */ + outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | + I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + + status = wait_for_pin(); + + if (status & I2C_STAT_XRDY) { + /* Important: have to use byte access */ + outb(regoffset, I2C_DATA); + + /* Important: wait for ARDY bit to set */ + err = 2000; + while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && err--) + ; + if (err <= 0) + i2c_error = 1; + + if (inw(I2C_STAT) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + err = 2000; + outw(I2C_CON_EN, I2C_CON); + while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { + /* Have to clear pending interrupt to clear I2C_STAT */ + outw(0xFFFF, I2C_STAT); + if (!err--) { + break; + } + } + + /* set slave address */ + outw(devaddr, I2C_SA); + /* read one byte from slave */ + outw(1, I2C_CNT); + /* need stop bit here */ + outw(I2C_CON_EN | + ((i2c_speed == + OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | I2C_CON_MST | + I2C_CON_STT | I2C_CON_STP, I2C_CON); + + status = wait_for_pin(); + if (status & I2C_STAT_RRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + *value = inb(I2C_DATA); +#else + *value = inw(I2C_DATA); +#endif + /* Important: wait for ARDY bit to set */ + err = 20000; + while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && err--) + ; + if (err <= 0){ +printf("i2c_read_byte -- I2C_STAT_ARDY error\n"); + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + int err = 1000; + outw(I2C_CON_EN, I2C_CON); + while (inw(I2C_STAT) + || (inw(I2C_CON) & I2C_CON_MST)) { + outw(0xFFFF, I2C_STAT); + if (!err--) { + break; + } + } + } + } + flush_fifo(); + outw(0xFFFF, I2C_STAT); + outw(0, I2C_CNT); + return i2c_error; +} + +static int i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) +{ + int eout; + int i2c_error = 0; + u16 status, stat; + + /* wait until bus not busy */ + wait_for_bb(); + + /* two bytes */ + outw(2, I2C_CNT); + /* set slave address */ + outw(devaddr, I2C_SA); + /* stop bit needed here */ + outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | + I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, I2C_CON); + + /* wait until state change */ + status = wait_for_pin(); + + if (status & I2C_STAT_XRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + /* send out 1 byte */ + outb(regoffset, I2C_DATA); + outw(I2C_STAT_XRDY, I2C_STAT); + status = wait_for_pin(); + if ((status & I2C_STAT_XRDY)) { + /* send out next 1 byte */ + outb(value, I2C_DATA); + outw(I2C_STAT_XRDY, I2C_STAT); + } else { + i2c_error = 1; + } +#else + /* send out 2 bytes */ + outw((value << 8) | regoffset, I2C_DATA); +#endif + /* must have enough delay to allow BB bit to go low */ + eout= 20000; + while (!(inw(I2C_STAT) & I2C_STAT_ARDY) && eout--) + ; + if (eout <= 0) + printf("timed out in i2c_write_byte: I2C_STAT=%x\n", + inw(I2C_STAT)); + + if (inw(I2C_STAT) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + if (!i2c_error) { + eout = 2000; + + outw(I2C_CON_EN, I2C_CON); + while ((stat = inw(I2C_STAT)) || (inw(I2C_CON) & I2C_CON_MST)) { + /* have to read to clear intrrupt */ + outw(0xFFFF, I2C_STAT); + if (--eout == 0) /* better leave with error than hang */ + break; + } + } + flush_fifo(); + outw(0xFFFF, I2C_STAT); + outw(0, I2C_CNT); + return i2c_error; +} + +static void flush_fifo(void) +{ + u16 stat; + + /* note: if you try and read data when its not there or ready + * you get a bus error + */ + while (1) { + stat = inw(I2C_STAT); + if (stat == I2C_STAT_RRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + inb(I2C_DATA); +#else + inw(I2C_DATA); +#endif + outw(I2C_STAT_RRDY, I2C_STAT); + } else + break; + } +} + +int i2c_probe(uchar chip) +{ + int res = 1; /* default = fail */ + + if (chip == inw(I2C_OA)) { + return res; + } + + /* wait until bus not busy */ + wait_for_bb(); + + /* try to read one byte */ + outw(1, I2C_CNT); + /* set slave address */ + outw(chip, I2C_SA); + /* stop bit needed here */ + outw(I2C_CON_EN | ((i2c_speed == OMAP_I2C_HIGH_SPEED) ? 0x1 << 12 : 0) | + I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + /* enough delay for the NACK bit set */ + udelay(50000); + + if (!(inw(I2C_STAT) & I2C_STAT_NACK)) { + res = 0; /* success case */ + flush_fifo(); + outw(0xFFFF, I2C_STAT); + } else { + outw(0xFFFF, I2C_STAT); /* failue, clear sources */ + outw(inw(I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + udelay(20000); + wait_for_bb(); + } + flush_fifo(); + outw(0, I2C_CNT); /* don't allow any more data in...we don't want it. */ + outw(0xFFFF, I2C_STAT); + return res; +} + +int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_read_byte(chip, addr + i, &buffer[i])) { + printf("I2C read: I/O error\n"); + i2c_init(i2c_speed, CFG_I2C_SLAVE); + return 1; + } + } + + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + int i; + + if (alen > 1) { + printf("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (addr + len > 256) { + printf("I2C read: address out of range\n"); + return 1; + } + + for (i = 0; i < len; i++) { + if (i2c_write_byte(chip, addr + i, buffer[i])) { + printf("I2C read: I/O error\n"); + i2c_init(i2c_speed, CFG_I2C_SLAVE); + return 1; + } + } + + return 0; +} + +static void wait_for_bb(void) +{ + int timeout = 5000; + u16 stat; + + outw(0xFFFF, I2C_STAT); /* clear current interruts... */ + while ((stat = inw(I2C_STAT) & I2C_STAT_BB) && timeout--) { + outw(stat, I2C_STAT); + } + + if (timeout <= 0) { + printf("timed out in wait_for_bb: I2C_STAT=%x\n", + inw(I2C_STAT)); + } + outw(0xFFFF, I2C_STAT); /* clear delayed stuff */ +} + +static u16 wait_for_pin(void) +{ + u16 status; + int timeout = 9000; + + do { + status = inw(I2C_STAT); + } while (!(status & + (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | + I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL)) && timeout--); + + if (timeout <= 0) { + printf("timed out in wait_for_pin: I2C_STAT=%x\n", + inw(I2C_STAT)); + outw(0xFFFF, I2C_STAT); + } + return status; +} + +#endif /* CONFIG_DRIVER_OMAP24XX_I2C */ diff --git a/drivers/onenand/Makefile b/drivers/onenand/Makefile new file mode 100644 index 000000000..e7446324d --- /dev/null +++ b/drivers/onenand/Makefile @@ -0,0 +1,42 @@ +# +# (C) Copyright 2005 +# Kyungmin Park, Samsung Electronics. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = libonenand.a + +OBJS = onenand_base.o onenand_bbt.o + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/drivers/onenand/onenand_base.c b/drivers/onenand/onenand_base.c new file mode 100644 index 000000000..dde7b8be1 --- /dev/null +++ b/drivers/onenand/onenand_base.c @@ -0,0 +1,1307 @@ +/* + * linux/drivers/mtd/onenand/onenand_base.c + * + * Copyright (C) 2005 Samsung Electronics + * Kyungmin Park + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) + +#include + +#include + +static void *onenand_memcpy(void *dest, const void *src, size_t count) +{ + unsigned short *_s = (unsigned short *) (src); + unsigned short *_d = (unsigned short *) (dest); + count >>= 1; + while (count--) + *_d++ = *_s++; + + return _d; +} + +static const unsigned char ffchars[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */ +}; + +/** + * onenand_readw - [OneNAND Interface] Read OneNAND register + * @param addr address to read + * + * Read OneNAND register + */ +static unsigned short onenand_readw(void __iomem *addr) +{ + return readw(addr); +} + +/** + * onenand_writew - [OneNAND Interface] Write OneNAND register with value + * @param value value to write + * @param addr address to write + * + * Write OneNAND register with value + */ +static void onenand_writew(unsigned short value, void __iomem *addr) +{ + writew(value, addr); +} + +/** + * onenand_block_address - [DEFAULT] Get block address + * @param device the device id + * @param block the block + * @return translated block address if DDP, otherwise same + * + * Setup Start Address 1 Register (F100h) + */ +static int onenand_block_address(int device, int block) +{ + if (device & ONENAND_DEVICE_IS_DDP) { + /* Device Flash Core select, NAND Flash Block Address */ + int dfs = 0, density, mask; + + density = device >> ONENAND_DEVICE_DENSITY_SHIFT; + mask = (1 << (density + 6)); + + if (block & mask) + dfs = 1; + + return (dfs << ONENAND_DDP_SHIFT) | (block & (mask - 1)); + } + + return block; +} + +/** + * onenand_bufferram_address - [DEFAULT] Get bufferram address + * @param device the device id + * @param block the block + * @return set DBS value if DDP, otherwise 0 + * + * Setup Start Address 2 Register (F101h) for DDP + */ +static int onenand_bufferram_address(int device, int block) +{ + if (device & ONENAND_DEVICE_IS_DDP) { + /* Device BufferRAM Select */ + int dbs = 0, density, mask; + + density = device >> ONENAND_DEVICE_DENSITY_SHIFT; + mask = (1 << (density + 6)); + + if (block & mask) + dbs = 1; + + return (dbs << ONENAND_DDP_SHIFT); + } + + return 0; +} + +/** + * onenand_page_address - [DEFAULT] Get page address + * @param page the page address + * @param sector the sector address + * @return combined page and sector address + * + * Setup Start Address 8 Register (F107h) + */ +static int onenand_page_address(int page, int sector) +{ + /* Flash Page Address, Flash Sector Address */ + int fpa, fsa; + + fpa = page & ONENAND_FPA_MASK; + fsa = sector & ONENAND_FSA_MASK; + + return ((fpa << ONENAND_FPA_SHIFT) | fsa); +} + +/** + * onenand_buffer_address - [DEFAULT] Get buffer address + * @param dataram1 DataRAM index + * @param sectors the sector address + * @param count the number of sectors + * @return the start buffer value + * + * Setup Start Buffer Register (F200h) + */ +static int onenand_buffer_address(int dataram1, int sectors, int count) +{ + int bsa, bsc; + + /* BufferRAM Sector Address */ + bsa = sectors & ONENAND_BSA_MASK; + + if (dataram1) + bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */ + else + bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */ + + /* BufferRAM Sector Count */ + bsc = count & ONENAND_BSC_MASK; + + return ((bsa << ONENAND_BSA_SHIFT) | bsc); +} + +/** + * onenand_command - [DEFAULT] Send command to OneNAND device + * @param mtd MTD device structure + * @param cmd the command to be sent + * @param addr offset to read from or write to + * @param len number of bytes to read or write + * + * Send command to OneNAND device. This function is used for middle/large page + * devices (1KB/2KB Bytes per page) + */ +static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len) +{ + struct onenand_chip *this = mtd->priv; + int value, readcmd = 0; + int block, page; + /* Now we use page size operation */ + int sectors = 4, count = 4; + + /* Address translation */ + switch (cmd) { + case ONENAND_CMD_UNLOCK: + case ONENAND_CMD_LOCK: + case ONENAND_CMD_LOCK_TIGHT: + block = -1; + page = -1; + break; + + case ONENAND_CMD_ERASE: + case ONENAND_CMD_BUFFERRAM: + block = (int) (addr >> this->erase_shift); + page = -1; + break; + + default: + block = (int) (addr >> this->erase_shift); + page = (int) (addr >> this->page_shift); + page &= this->page_mask; + break; + } + + + /* NOTE: The setting order of the registers is very important! */ + if (cmd == ONENAND_CMD_BUFFERRAM) { + /* Select DataRAM for DDP */ + value = onenand_bufferram_address(this->device_id, block); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); + + /* Switch to the next data buffer */ + ONENAND_SET_NEXT_BUFFERRAM(this); + + return 0; + } + + if (block != -1) { + /* Write 'DFS, FBA' of Flash */ + value = onenand_block_address(this->device_id, block); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); + } + + if (page != -1) { + int dataram; + + switch (cmd) { + case ONENAND_CMD_READ: + case ONENAND_CMD_READOOB: + dataram = ONENAND_SET_NEXT_BUFFERRAM(this); + readcmd = 1; + break; + + default: + dataram = ONENAND_CURRENT_BUFFERRAM(this); + break; + } + + /* Write 'FPA, FSA' of Flash */ + value = onenand_page_address(page, sectors); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8); + + /* Write 'BSA, BSC' of DataRAM */ + value = onenand_buffer_address(dataram, sectors, count); + this->write_word(value, this->base + ONENAND_REG_START_BUFFER); + + if (readcmd) { + /* Select DataRAM for DDP */ + value = onenand_bufferram_address(this->device_id, block); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); + } + } + + /* Interrupt clear */ + this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT); + + /* Write command */ + this->write_word(cmd, this->base + ONENAND_REG_COMMAND); + + return 0; +} + +/** + * onenand_wait - [DEFAULT] wait until the command is done + * @param mtd MTD device structure + * @param state state to select the max. timeout value + * + * Wait for command done. This applies to all OneNAND command + * Read can take up to 30us, erase up to 2ms and program up to 350us + * according to general OneNAND specs + */ +static int onenand_wait(struct mtd_info *mtd, int state) +{ + struct onenand_chip * this = mtd->priv; + unsigned int flags = ONENAND_INT_MASTER; + unsigned int interrupt = 0; + unsigned int ctrl, ecc; + + if (state == FL_UNLOCKING) + printk(""); + + while (1) { + interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); + + if (interrupt & flags) + break; + } + + + ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); + + if (state == FL_UNLOCKING) { + printk(""); + if (ctrl & (1 << 6)) + printk("Block remains locked\n"); + } + + + if (ctrl & ONENAND_CTRL_ERROR) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: controller error = 0x%04x\n", ctrl); + return -EAGAIN; + } + + if (ctrl & ONENAND_CTRL_LOCK) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: it's locked error = 0x%04x\n", ctrl); + return -EIO; + } + + if (interrupt & ONENAND_INT_READ) { + ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); + if (ecc & ONENAND_ECC_2BIT_ALL) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: ECC error = 0x%04x\n", ecc); + return -EBADMSG; + } + } + return 0; +} + +/** + * onenand_bufferram_offset - [DEFAULT] BufferRAM offset + * @param mtd MTD data structure + * @param area BufferRAM area + * @return offset given area + * + * Return BufferRAM offset given area + */ +static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) +{ + struct onenand_chip *this = mtd->priv; + + if (ONENAND_CURRENT_BUFFERRAM(this)) { + if (area == ONENAND_DATARAM) + return mtd->oobblock; + if (area == ONENAND_SPARERAM) + return mtd->oobsize; + } + + return 0; +} + +/** + * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area + * @param mtd MTD data structure + * @param area BufferRAM area + * @param buffer the databuffer to put/get data + * @param offset offset to read from or write to + * @param count number of bytes to read/write + * + * Read the BufferRAM area + */ +static int onenand_read_bufferram(struct mtd_info *mtd, int area, + unsigned char *buffer, int offset, size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + + bufferram += onenand_bufferram_offset(mtd, area); + + onenand_memcpy(buffer, bufferram + offset, count); + + return 0; +} + +/** + * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode + * @param mtd MTD data structure + * @param area BufferRAM area + * @param buffer the databuffer to put/get data + * @param offset offset to read from or write to + * @param count number of bytes to read/write + * + * Read the BufferRAM area with Sync. Burst Mode + */ +static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area, + unsigned char *buffer, int offset, size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + + bufferram += onenand_bufferram_offset(mtd, area); + + this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ); + + onenand_memcpy(buffer, bufferram + offset, count); + + this->mmcontrol(mtd, 0); + + return 0; +} + +/** + * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area + * @param mtd MTD data structure + * @param area BufferRAM area + * @param buffer the databuffer to put/get data + * @param offset offset to read from or write to + * @param count number of bytes to read/write + * + * Write the BufferRAM area + */ +static int onenand_write_bufferram(struct mtd_info *mtd, int area, + const unsigned char *buffer, int offset, size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + + bufferram += onenand_bufferram_offset(mtd, area); + + onenand_memcpy(bufferram + offset, buffer, count); + + return 0; +} + +/** + * onenand_check_bufferram - [GENERIC] Check BufferRAM information + * @param mtd MTD data structure + * @param addr address to check + * @return 1 if there are valid data, otherwise 0 + * + * Check bufferram if there is data we required + */ +static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) +{ + struct onenand_chip *this = mtd->priv; + int block, page; + int i; + + block = (int) (addr >> this->erase_shift); + page = (int) (addr >> this->page_shift); + page &= this->page_mask; + + i = ONENAND_CURRENT_BUFFERRAM(this); + + /* Is there valid data? */ + if (this->bufferram[i].block == block && + this->bufferram[i].page == page && + this->bufferram[i].valid) + return 1; + + return 0; +} + +/** + * onenand_update_bufferram - [GENERIC] Update BufferRAM information + * @param mtd MTD data structure + * @param addr address to update + * @param valid valid flag + * + * Update BufferRAM information + */ +static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr, + int valid) +{ + struct onenand_chip *this = mtd->priv; + int block, page; + int i; + + block = (int) (addr >> this->erase_shift); + page = (int) (addr >> this->page_shift); + page &= this->page_mask; + + /* Invalidate BufferRAM */ + for (i = 0; i < MAX_BUFFERRAM; i++) { + if (this->bufferram[i].block == block && + this->bufferram[i].page == page) + this->bufferram[i].valid = 0; + } + + /* Update BufferRAM */ + i = ONENAND_CURRENT_BUFFERRAM(this); + this->bufferram[i].block = block; + this->bufferram[i].page = page; + this->bufferram[i].valid = valid; + + return 0; +} + +/** + * onenand_get_device - [GENERIC] Get chip for selected access + * @param mtd MTD device structure + * @param new_state the state which is requested + * + * Get the device and lock it for exclusive access + */ +static void onenand_get_device(struct mtd_info *mtd, int new_state) +{ + /* Do nothing */ +} + +/** + * onenand_release_device - [GENERIC] release chip + * @param mtd MTD device structure + * + * Deselect, release chip lock and wake up anyone waiting on the device + */ +static void onenand_release_device(struct mtd_info *mtd) +{ + /* Do nothing */ +} + +/** + * onenand_read_ecc - [MTD Interface] Read data with ECC + * @param mtd MTD device structure + * @param from offset to read from + * @param len number of bytes to read + * @param retlen pointer to variable to store the number of read bytes + * @param buf the databuffer to put data + * @param oob_buf filesystem supplied oob data buffer + * @param oobsel oob selection structure + * + * OneNAND read with ECC + */ +static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, u_char *buf, + u_char *oob_buf, struct nand_oobinfo *oobsel) +{ + struct onenand_chip *this = mtd->priv; + int read = 0, column; + int thislen; + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + + /* Do not allow reads past end of device */ + if ((from + len) > mtd->size) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_ecc: Attempt read beyond end of device\n"); + *retlen = 0; + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_READING); + + /* TODO handling oob */ + + while (read < len) { + thislen = min_t(int, mtd->oobblock, len - read); + + column = from & (mtd->oobblock - 1); + if (column + thislen > mtd->oobblock) + thislen = mtd->oobblock - column; + + if (!onenand_check_bufferram(mtd, from)) { + this->command(mtd, ONENAND_CMD_READ, from, mtd->oobblock); + + ret = this->wait(mtd, FL_READING); + /* First copy data and check return value for ECC handling */ + onenand_update_bufferram(mtd, from, 1); + } + + this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen); + + read += thislen; + + if (read == len) + break; + + if (ret) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_ecc: read failed = %d\n", ret); + goto out; + } + + from += thislen; + buf += thislen; + } + +out: + /* Deselect and wake up anyone waiting on the device */ + onenand_release_device(mtd); + + /* + * Return success, if no ECC failures, else -EBADMSG + * fs driver will take care of that, because + * retlen == desired len and result == -EBADMSG + */ + *retlen = read; + return ret; +} + +/** + * onenand_read - [MTD Interface] MTD compability function for onenand_read_ecc + * @param mtd MTD device structure + * @param from offset to read from + * @param len number of bytes to read + * @param retlen pointer to variable to store the number of read bytes + * @param buf the databuffer to put data + * + * This function simply calls onenand_read_ecc with oob buffer and oobsel = NULL +*/ +int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, u_char *buf) +{ + return onenand_read_ecc(mtd, from, len, retlen, buf, NULL, NULL); +} + +/** + * onenand_read_oob - [MTD Interface] OneNAND read out-of-band + * @param mtd MTD device structure + * @param from offset to read from + * @param len number of bytes to read + * @param retlen pointer to variable to store the number of read bytes + * @param buf the databuffer to put data + * + * OneNAND read out-of-band data from the spare area + */ +int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, + size_t *retlen, u_char *buf) +{ + struct onenand_chip *this = mtd->priv; + int read = 0, thislen, column; + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + + /* Initialize return length value */ + *retlen = 0; + + /* Do not allow reads past end of device */ + if (unlikely((from + len) > mtd->size)) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: Attempt read beyond end of device\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_READING); + + column = from & (mtd->oobsize - 1); + + while (read < len) { + thislen = mtd->oobsize - column; + thislen = min_t(int, thislen, len); + + this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); + + onenand_update_bufferram(mtd, from, 0); + + ret = this->wait(mtd, FL_READING); + /* First copy data and check return value for ECC handling */ + + this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); + + read += thislen; + + if (read == len) + break; + + if (ret) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: read failed = %d\n", ret); + goto out; + } + + buf += thislen; + + /* Read more? */ + if (read < len) { + /* Page size */ + from += mtd->oobblock; + column = 0; + } + } + +out: + /* Deselect and wake up anyone waiting on the device */ + onenand_release_device(mtd); + + *retlen = read; + return ret; +} + +#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE +/** + * onenand_verify_page - [GENERIC] verify the chip contents after a write + * @param mtd MTD device structure + * @param buf the databuffer to verify + * @param block block address + * @param page page address + * + * Check DataRAM area directly + */ +static int onenand_verify_page(struct mtd_info *mtd, u_char *buf, + loff_t addr, int block, int page) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *dataram0, *dataram1; + int ret = 0; + + this->command(mtd, ONENAND_CMD_READ, addr, mtd->oobblock); + + ret = this->wait(mtd, FL_READING); + if (ret) + return ret; + + onenand_update_bufferram(mtd, addr, 1); + + /* Check, if the two dataram areas are same */ + dataram0 = this->base + ONENAND_DATARAM; + dataram1 = dataram0 + mtd->oobblock; + + if (memcmp(dataram0, dataram1, mtd->oobblock)) + return -EBADMSG; + + return 0; +} +#else +#define onenand_verify_page(...) (0) +#endif + +#define NOTALIGNED(x) ((x & (mtd->oobblock - 1)) != 0) + +/** + * onenand_write_ecc - [MTD Interface] OneNAND write with ECC + * @param mtd MTD device structure + * @param to offset to write to + * @param len number of bytes to write + * @param retlen pointer to variable to store the number of written bytes + * @param buf the data to write + * @param eccbuf filesystem supplied oob data buffer + * @param oobsel oob selection structure + * + * OneNAND write with ECC + */ +static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf, + u_char *eccbuf, struct nand_oobinfo *oobsel) +{ + struct onenand_chip *this = mtd->priv; + int written = 0; + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ecc: to = 0x%x, len = %d\n", (unsigned int) to, (int) len); + + /* Initialize retlen, in case of early exit */ + *retlen = 0; + + /* Do not allow writes past end of device */ + if (unlikely((to + len) > mtd->size)) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt write to past end of device\n"); + return -EINVAL; + } + + /* Reject writes, which are not page aligned */ + if (unlikely(NOTALIGNED(to))) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt to write nonpage alignd address\n"); + return -EINVAL; + } + + if (unlikely(NOTALIGNED(len))) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt to write not page aligned size\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_WRITING); + + + /* Loop until all data write */ + while (written < len) { + int thislen = min_t(int, mtd->oobblock, len - written); + + this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock); + + this->write_bufferram(mtd, ONENAND_DATARAM, buf, 0, thislen); + this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize); + + this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock); + + onenand_update_bufferram(mtd, to, 1); + + ret = this->wait(mtd, FL_WRITING); + if (ret) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: write filaed %d\n", ret); + goto out; + } + + written += thislen; + + /* Only check verify write turn on */ + ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page); + if (ret) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: verify failed %d\n", ret); + goto out; + } + + if (written == len) + break; + + to += thislen; + buf += thislen; + } + +out: + /* Deselect and wake up anyone waiting on the device */ + onenand_release_device(mtd); + + *retlen = written; + + return ret; +} + +/** + * onenand_write - [MTD Interface] compability function for onenand_write_ecc + * @param mtd MTD device structure + * @param to offset to write to + * @param len number of bytes to write + * @param retlen pointer to variable to store the number of written bytes + * @param buf the data to write + * + * This function simply calls onenand_write_ecc + * with oob buffer and oobsel = NULL + */ +int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) +{ + return onenand_write_ecc(mtd, to, len, retlen, buf, NULL, NULL); +} + +/** + * onenand_write_oob - [MTD Interface] OneNAND write out-of-band + * @param mtd MTD device structure + * @param to offset to write to + * @param len number of bytes to write + * @param retlen pointer to variable to store the number of written bytes + * @param buf the data to write + * + * OneNAND write out-of-band + */ +int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len, + size_t *retlen, const u_char *buf) +{ + struct onenand_chip *this = mtd->priv; + int column, status; + int written = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); + + /* Initialize retlen, in case of early exit */ + *retlen = 0; + + /* Do not allow writes past end of device */ + if (unlikely((to + len) > mtd->size)) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: Attempt write to past end of device\n"); + return -EINVAL; + } + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_WRITING); + + /* Loop until all data write */ + while (written < len) { + int thislen = min_t(int, mtd->oobsize, len - written); + + column = to & (mtd->oobsize - 1); + + this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize); + + this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize); + this->write_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); + + this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); + + onenand_update_bufferram(mtd, to, 0); + + status = this->wait(mtd, FL_WRITING); + if (status) + goto out; + + written += thislen; + + if (written == len) + break; + + to += thislen; + buf += thislen; + } + +out: + /* Deselect and wake up anyone waiting on the device */ + onenand_release_device(mtd); + + *retlen = written; + + return 0; +} + +/** + * onenand_erase - [MTD Interface] erase block(s) + * @param mtd MTD device structure + * @param instr erase instruction + * + * Erase one ore more blocks + */ +int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) +{ + struct onenand_chip *this = mtd->priv; + unsigned int block_size; + loff_t addr; + int len; + int ret = 0; + + DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); + + block_size = (1 << this->erase_shift); + + /* Start address must align on block boundary */ + if (unlikely(instr->addr & (block_size - 1))) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n"); + return -EINVAL; + } + + /* Length must align on block boundary */ + if (unlikely(instr->len & (block_size - 1))) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Length not block aligned\n"); + return -EINVAL; + } + + /* Do not allow erase past end of device */ + if (unlikely((instr->len + instr->addr) > mtd->size)) { + DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Erase past end of device\n"); + return -EINVAL; + } + + instr->fail_addr = 0xffffffff; + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_ERASING); + + /* Loop throught the pages */ + len = instr->len; + addr = instr->addr; + + instr->state = MTD_ERASING; + + while (len) { + + /* TODO Check badblock */ + + this->command(mtd, ONENAND_CMD_ERASE, addr, block_size); + + ret = this->wait(mtd, FL_ERASING); + /* Check, if it is write protected */ + if (ret) { + if (ret == -EPERM) + DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Device is write protected!!!\n"); + else { + printk("onenand_erase: Failed erase, block %d\n", (unsigned) (addr >> this->erase_shift)); + DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Failed erase, block %d\n", (unsigned) (addr >> this->erase_shift)); + } + instr->state = MTD_ERASE_FAILED; + instr->fail_addr = addr; + goto erase_exit; + } + + len -= block_size; + addr += block_size; + } + + instr->state = MTD_ERASE_DONE; + +erase_exit: + + ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; + /* Do call back function */ + if (!ret) + mtd_erase_callback(instr); + + /* Deselect and wake up anyone waiting on the device */ + onenand_release_device(mtd); + + return ret; +} + +/** + * onenand_sync - [MTD Interface] sync + * @param mtd MTD device structure + * + * Sync is actually a wait for chip ready function + */ +void onenand_sync(struct mtd_info *mtd) +{ + DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); + + /* Grab the lock and see if the device is available */ + onenand_get_device(mtd, FL_SYNCING); + + /* Release it and go back */ + onenand_release_device(mtd); +} + +/** + * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad + * @param mtd MTD device structure + * @param ofs offset relative to mtd start + */ +int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs) +{ + /* + * TODO + * 1. Bad block table (BBT) + * -> using NAND BBT to support JFFS2 + * 2. Bad block management (BBM) + * -> bad block replace scheme + * + * Currently we do nothing + */ + return 0; +} + +/** + * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad + * @param mtd MTD device structure + * @param ofs offset relative to mtd start + */ +int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs) +{ + /* see above */ + return 0; +} + +/** + * onenand_unlock - [MTD Interface] Unlock block(s) + * @param mtd MTD device structure + * @param ofs offset relative to mtd start + * @param len number of bytes to unlock + * + * Unlock one or more blocks + */ +int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) +{ + struct onenand_chip *this = mtd->priv; + int start, end, block, value, status; +#if 1 + start = ofs >> this->erase_shift; + end = len >> this->erase_shift; +#else + start = ofs ; + end = len ; +#endif + + /* Continuous lock scheme */ + if (this->options & ONENAND_CONT_LOCK) { + /* Set start block address */ + this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS); + /* Set end block address */ + this->write_word(end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS); + /* Write unlock command */ + this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0); + + /* There's no return value */ + this->wait(mtd, FL_UNLOCKING); + + /* Sanity check */ + while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) + & ONENAND_CTRL_ONGO) + continue; + + /* Check lock status */ + status = this->read_word(this->base + ONENAND_REG_WP_STATUS); + if (!(status & ONENAND_WP_US)) + printk(KERN_ERR "wp status = 0x%x\n", status); + + return 0; + } + + /* Block lock scheme */ + for (block = start; block < end; block++) { + /* Set start block address */ + this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); + /* Write unlock command */ + this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0); + + /* There's no return value */ + this->wait(mtd, FL_UNLOCKING); + + /* Sanity check */ + while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) + & ONENAND_CTRL_ONGO) + continue; + + /* Set block address for read block status */ + value = onenand_block_address(this->device_id, block); + this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); + + /* Check lock status */ + status = this->read_word(this->base + ONENAND_REG_WP_STATUS); + if (!(status & ONENAND_WP_US)) + printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); + } + + return 0; +} + +/** + * onenand_print_device_info - Print device ID + * @param device device ID + * + * Print device ID + */ +void onenand_print_device_info(int device, int verbose) +{ + int vcc, demuxed, ddp, density; + + if (!verbose) + return; + + vcc = device & ONENAND_DEVICE_VCC_MASK; + demuxed = device & ONENAND_DEVICE_IS_DEMUX; + ddp = device & ONENAND_DEVICE_IS_DDP; + density = device >> ONENAND_DEVICE_DENSITY_SHIFT; + printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n", + demuxed ? "" : "Muxed ", + ddp ? "(DDP)" : "", + (16 << density), + vcc ? "2.65/3.3" : "1.8", + device); +} + +static const struct onenand_manufacturers onenand_manuf_ids[] = { + {ONENAND_MFR_SAMSUNG, "Samsung"}, + {ONENAND_MFR_UNKNOWN, "Unknown"} +}; + +/** + * onenand_check_maf - Check manufacturer ID + * @param manuf manufacturer ID + * + * Check manufacturer ID + */ +static int onenand_check_maf(int manuf) +{ + int i; + + for (i = 0; onenand_manuf_ids[i].id; i++) { + if (manuf == onenand_manuf_ids[i].id) + break; + } + +#ifdef ONENAND_DEBUG + printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", + onenand_manuf_ids[i].name, manuf); +#endif + + return (i != ONENAND_MFR_UNKNOWN); +} + +/** + * onenand_probe - [OneNAND Interface] Probe the OneNAND device + * @param mtd MTD device structure + * + * OneNAND detection method: + * Compare the the values from command with ones from register + */ +static int onenand_probe(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + int bram_maf_id, bram_dev_id, maf_id, dev_id; + int version_id; + int density; + + /* Send the command for reading device ID from BootRAM */ + this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM); + + udelay(1); /* no interrupt for readid */ + + /* Read manufacturer and device IDs from BootRAM */ + bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0); + bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2); + + /* Check manufacturer ID */ + if (onenand_check_maf(bram_maf_id)) { + printk(KERN_DEBUG "OneNAND: onenand_check_maf failed : %x\n", bram_maf_id); + return -ENXIO; + } + + /* Reset OneNAND to read default register values */ + this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); + + this->wait(mtd, FL_RESETING); /* 10, 20, 500us */ + + /* Read manufacturer and device IDs from Register */ + maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); + dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); + + /* Check OneNAND device */ + if (maf_id != bram_maf_id || dev_id != bram_dev_id) { + printk(KERN_DEBUG "OneNAND mafid and dev id recog fail\n"); + return -ENXIO; + } + + /* Flash device information */ + onenand_print_device_info(dev_id, 1); + this->device_id = dev_id; + + density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; + this->chipsize = (16 << density) << 20; + + /* OneNAND page size & block size */ + /* The data buffer size is equal to page size */ + mtd->oobblock = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE); + mtd->oobsize = mtd->oobblock >> 5; + /* Pagers per block is always 64 in OneNAND */ + mtd->erasesize = mtd->oobblock << 6; + + this->erase_shift = ffs(mtd->erasesize) - 1; + this->page_shift = ffs(mtd->oobblock) - 1; + this->ppb_shift = (this->erase_shift - this->page_shift); + this->page_mask = (mtd->erasesize / mtd->oobblock) - 1; + + /* REVIST: Multichip handling */ + + mtd->size = this->chipsize; + + /* Version ID */ + version_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); +#ifdef ONENAND_DEBUG + printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version_id); +#endif + + /* Lock scheme */ + if (density <= ONENAND_DEVICE_DENSITY_512Mb && + !(version_id >> ONENAND_VERSION_PROCESS_SHIFT)) { + printk(KERN_INFO "Lock scheme is Continues Lock\n"); + this->options |= ONENAND_CONT_LOCK; + } + + return 0; +} + + +/** + * onenand_scan - [OneNAND Interface] Scan for the OneNAND device + * @param mtd MTD device structure + * @param maxchips Number of chips to scan for + * + * This fills out all the not initialized function pointers + * with the defaults. + * The flash ID is read and the mtd/chip structures are + * filled with the appropriate values. + */ +int onenand_scan(struct mtd_info *mtd, int maxchips) +{ + struct onenand_chip *this = mtd->priv; + + if (!this->read_word) + this->read_word = onenand_readw; + if (!this->write_word) + this->write_word = onenand_writew; + + if (!this->command) + this->command = onenand_command; + if (!this->wait) + this->wait = onenand_wait; + + if (!this->read_bufferram) + this->read_bufferram = onenand_read_bufferram; + if (!this->write_bufferram) + this->write_bufferram = onenand_write_bufferram; + + if (onenand_probe(mtd)) + return -ENXIO; + + /* Set Sync. Burst Read after probing */ + if (this->mmcontrol) { + printk(KERN_INFO "OneNAND Sync. Burst Read support\n"); + this->read_bufferram = onenand_sync_read_bufferram; + } + +#ifdef ENV_IS_VARIABLE +extern int onenand_env_init(void); +extern int (*boot_env_init) (void); + if (onenand_env_init == boot_env_init) +#endif + onenand_unlock(mtd, CFG_ENV_ADDR, mtd->size); + + return onenand_default_bbt(mtd); +} + +/** + * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device + * @param mtd MTD device structure + */ +void onenand_release(struct mtd_info *mtd) +{ +} + +/* + * OneNAND initialization at U-Boot + */ +struct mtd_info onenand_mtd; +struct onenand_chip onenand_chip; + +void onenand_init(void) +{ + memset(&onenand_mtd, 0, sizeof(struct mtd_info)); + memset(&onenand_chip, 0, sizeof(struct onenand_chip)); + + onenand_chip.base = (void *) CFG_ONENAND_BASE; + onenand_mtd.priv = &onenand_chip; + + onenand_scan(&onenand_mtd, 1); + +} + +#endif /* CFG_CMD_ONENAND */ diff --git a/drivers/onenand/onenand_bbt.c b/drivers/onenand/onenand_bbt.c new file mode 100644 index 000000000..183fb85aa --- /dev/null +++ b/drivers/onenand/onenand_bbt.c @@ -0,0 +1,252 @@ +/* + * linux/drivers/mtd/onenand/onenand_bbt.c + * + * Bad Block Table support for the OneNAND driver + * + * Copyright(c) 2005 Samsung Electronics + * Kyungmin Park + * + * Derived from nand_bbt.c + * + * TODO: + * Split BBT core and chip specific BBT. + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_ONENAND) + +#include +#include + +/** + * check_short_pattern - [GENERIC] check if a pattern is in the buffer + * @param buf the buffer to search + * @param len the length of buffer to search + * @param paglen the pagelength + * @param td search pattern descriptor + * + * Check for a pattern at the given place. Used to search bad block + * tables and good / bad block identifiers. Same as check_pattern, but + * no optional empty check and the pattern is expected to start + * at offset 0. + * + */ +static int check_short_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td) +{ + int i; + uint8_t *p = buf; + + /* Compare the pattern */ + for (i = 0; i < td->len; i++) { + if (p[i] != td->pattern[i]) + return -1; + } + return 0; +} + +/** + * create_bbt - [GENERIC] Create a bad block table by scanning the device + * @param mtd MTD device structure + * @param buf temporary buffer + * @param bd descriptor for the good/bad block search pattern + * @param chip create the table for a specific chip, -1 read all chips. + * Applies only if NAND_BBT_PERCHIP option is set + * + * Create a bad block table by scanning the device + * for the given good/bad block identify pattern + */ +static int create_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip) +{ + struct onenand_chip *this = mtd->priv; + struct bbm_info *bbm = this->bbm; + int i, j, numblocks, len, scanlen; + int startblock; + loff_t from; + size_t readlen, ooblen; + + printk(KERN_INFO "Scanning device for bad blocks\n"); + + len = 1; + + /* We need only read few bytes from the OOB area */ + scanlen = ooblen = 0; + readlen = bd->len; + + /* chip == -1 case only */ + /* Note that numblocks is 2 * (real numblocks) here; + * see i += 2 below as it makses shifting and masking less painful + */ + numblocks = mtd->size >> (bbm->bbt_erase_shift - 1); + printk(KERN_INFO "num of blocks = %d\n", numblocks); + startblock = 0; + from = 0; + +// ***onenand_read_oob(&onenand_mtd, ofs, len, &retlen, (u_char *) addr); + + for (i = startblock; i < numblocks; ) { + int ret; + + for (j = 0; j < len; j++) { + size_t retlen; + + /* No need to read pages fully, + * just read required OOB bytes */ + + + ret = onenand_read_oob(mtd, from + j * mtd->oobblock + bd->offs, + readlen, &retlen, &buf[0]); + + if (ret) + return ret; + + if (check_short_pattern(&buf[j * scanlen], scanlen, mtd->oobblock, bd)) { + bbm->bbt[i >> 3] |= 0x03 << (i & 0x6); + printk(KERN_WARNING "Bad eraseblock %d at 0x%08x\n", + i >> 1, (unsigned int) from); + break; + } + } + i += 2; + from += (1 << bbm->bbt_erase_shift); + } + + return 0; +} + + +/** + * onenand_memory_bbt - [GENERIC] create a memory based bad block table + * @param mtd MTD device structure + * @param bd descriptor for the good/bad block search pattern + * + * The function creates a memory based bbt by scanning the device + * for manufacturer / software marked good / bad blocks + */ +static inline int onenand_memory_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd) +{ + unsigned char data_buf[MAX_ONENAND_PAGESIZE]; + + bd->options &= ~NAND_BBT_SCANEMPTY; + return create_bbt(mtd, data_buf, bd, -1); +} + +/** + * onenand_isbad_bbt - [OneNAND Interface] Check if a block is bad + * @param mtd MTD device structure + * @param offs offset in the device + * @param allowbbt allow access to bad block table region + */ +static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) +{ + struct onenand_chip *this = mtd->priv; + struct bbm_info *bbm = this->bbm; + int block; + uint8_t res; + + /* Get block number * 2 */ + block = (int) (offs >> (bbm->bbt_erase_shift - 1)); + res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03; + + DEBUG(MTD_DEBUG_LEVEL2, "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n", + (unsigned int) offs, block >> 1, res); + + switch ((int) res) { + case 0x00: return 0; + case 0x01: return 1; + case 0x02: return allowbbt ? 0 : 1; + } + + return 1; +} + +/** + * onenand_scan_bbt - [OneNAND Interface] scan, find, read and maybe create bad block table(s) + * @param mtd MTD device structure + * @param bd descriptor for the good/bad block search pattern + * + * The function checks, if a bad block table(s) is/are already + * available. If not it scans the device for manufacturer + * marked good / bad blocks and writes the bad block table(s) to + * the selected place. + * + * The bad block table memory is allocated here. It must be freed + * by calling the onenand_free_bbt function. + * + */ +int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) +{ + struct onenand_chip *this = mtd->priv; + struct bbm_info *bbm = this->bbm; + int len, ret = 0; + + len = mtd->size >> (this->erase_shift + 2); + /* Allocate memory (2bit per block) */ + bbm->bbt = malloc(len); + if (!bbm->bbt) { + printk(KERN_ERR "onenand_scan_bbt: Out of memory\n"); + return -ENOMEM; + } + /* Clear the memory bad block table */ + memset(bbm->bbt, 0x00, len); + + /* Set the bad block position */ + bbm->badblockpos = ONENAND_BADBLOCK_POS; + + /* Set erase shift */ + bbm->bbt_erase_shift = this->erase_shift; + + if (!bbm->isbad_bbt) + bbm->isbad_bbt = onenand_isbad_bbt; + + /* Scan the device to build a memory based bad block table */ + if ((ret = onenand_memory_bbt(mtd, bd))) { + printk(KERN_ERR "onenand_scan_bbt: Can't scan flash and build the RAM-based BBT\n"); + free(bbm->bbt); + bbm->bbt = NULL; + } + + return ret; +} + +/* + * Define some generic bad / good block scan pattern which are used + * while scanning a device for factory marked good / bad blocks. + */ +static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; + +static struct nand_bbt_descr largepage_memorybased = { + .options = 0, + .offs = 0, + .len = 2, + .pattern = scan_ff_pattern, +}; + +/** + * onenand_default_bbt - [OneNAND Interface] Select a default bad block table for the device + * @param mtd MTD device structure + * + * This function selects the default bad block table + * support for the device and calls the onenand_scan_bbt function + */ +int onenand_default_bbt(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + struct bbm_info *bbm; + + this->bbm = malloc(sizeof(struct bbm_info)); + if (!this->bbm) + return -ENOMEM; + + bbm = this->bbm; + + memset(bbm, 0, sizeof(struct bbm_info)); + + /* 1KB page has same configuration as 2KB page */ + if (!bbm->badblock_pattern) + bbm->badblock_pattern = &largepage_memorybased; + + return onenand_scan_bbt(mtd, bbm->badblock_pattern); +} + +#endif /* CFG_CMD_ONENAND */ diff --git a/drivers/pc_keyb.c b/drivers/pc_keyb.c new file mode 100644 index 000000000..81d3e9893 --- /dev/null +++ b/drivers/pc_keyb.c @@ -0,0 +1,256 @@ +/*********************************************************************** + * + * (C) Copyright 2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * All rights reserved. + * + * PS/2 keyboard driver + * + * Originally from linux source (drivers/char/pc_keyb.c) + * + ***********************************************************************/ + +#include + +#ifdef CONFIG_PS2KBD + +#include +#include + +#undef KBG_DEBUG + +#ifdef KBG_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + + +/* + * This reads the keyboard status port, and does the + * appropriate action. + * + */ +static unsigned char handle_kbd_event(void) +{ + unsigned char status = kbd_read_status(); + unsigned int work = 10000; + + while ((--work > 0) && (status & KBD_STAT_OBF)) { + unsigned char scancode; + + scancode = kbd_read_input(); + + /* Error bytes must be ignored to make the + Synaptics touchpads compaq use work */ + /* Ignore error bytes */ + if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) { + if (status & KBD_STAT_MOUSE_OBF) + ; /* not supported: handle_mouse_event(scancode); */ + else + handle_scancode(scancode); + } + status = kbd_read_status(); + } + if (!work) + PRINTF("pc_keyb: controller jammed (0x%02X).\n", status); + return status; +} + + +static int kbd_read_data(void) +{ + int val; + unsigned char status; + + val=-1; + status = kbd_read_status(); + if (status & KBD_STAT_OBF) { + val = kbd_read_input(); + if (status & (KBD_STAT_GTO | KBD_STAT_PERR)) + val = -2; + } + return val; +} + +static int kbd_wait_for_input(void) +{ + unsigned long timeout; + int val; + + timeout = KBD_TIMEOUT; + val=kbd_read_data(); + while(val < 0) { + if(timeout--==0) + return -1; + udelay(1000); + val=kbd_read_data(); + } + return val; +} + + +static int kb_wait(void) +{ + unsigned long timeout = KBC_TIMEOUT * 10; + + do { + unsigned char status = handle_kbd_event(); + if (!(status & KBD_STAT_IBF)) + return 0; /* ok */ + udelay(1000); + timeout--; + } while (timeout); + return 1; +} + +static void kbd_write_command_w(int data) +{ + if(kb_wait()) + PRINTF("timeout in kbd_write_command_w\n"); + kbd_write_command(data); +} + +static void kbd_write_output_w(int data) +{ + if(kb_wait()) + PRINTF("timeout in kbd_write_output_w\n"); + kbd_write_output(data); +} + +static void kbd_send_data(unsigned char data) +{ + kbd_write_output_w(data); + kbd_wait_for_input(); +} + + +static char * kbd_initialize(void) +{ + int status; + + /* + * Test the keyboard interface. + * This seems to be the only way to get it going. + * If the test is successful a x55 is placed in the input buffer. + */ + kbd_write_command_w(KBD_CCMD_SELF_TEST); + if (kbd_wait_for_input() != 0x55) + return "Kbd: failed self test"; + /* + * Perform a keyboard interface test. This causes the controller + * to test the keyboard clock and data lines. The results of the + * test are placed in the input buffer. + */ + kbd_write_command_w(KBD_CCMD_KBD_TEST); + if (kbd_wait_for_input() != 0x00) + return "Kbd: interface failed self test"; + /* + * Enable the keyboard by allowing the keyboard clock to run. + */ + kbd_write_command_w(KBD_CCMD_KBD_ENABLE); + + /* + * Reset keyboard. If the read times out + * then the assumption is that no keyboard is + * plugged into the machine. + * This defaults the keyboard to scan-code set 2. + * + * Set up to try again if the keyboard asks for RESEND. + */ + do { + kbd_write_output_w(KBD_CMD_RESET); + status = kbd_wait_for_input(); + if (status == KBD_REPLY_ACK) + break; + if (status != KBD_REPLY_RESEND) { + PRINTF("status: %X\n",status); + return "Kbd: reset failed, no ACK"; + } + } while (1); + if (kbd_wait_for_input() != KBD_REPLY_POR) + return "Kbd: reset failed, no POR"; + + /* + * Set keyboard controller mode. During this, the keyboard should be + * in the disabled state. + * + * Set up to try again if the keyboard asks for RESEND. + */ + do { + kbd_write_output_w(KBD_CMD_DISABLE); + status = kbd_wait_for_input(); + if (status == KBD_REPLY_ACK) + break; + if (status != KBD_REPLY_RESEND) + return "Kbd: disable keyboard: no ACK"; + } while (1); + + kbd_write_command_w(KBD_CCMD_WRITE_MODE); + kbd_write_output_w(KBD_MODE_KBD_INT + | KBD_MODE_SYS + | KBD_MODE_DISABLE_MOUSE + | KBD_MODE_KCC); + + /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */ + kbd_write_command_w(KBD_CCMD_READ_MODE); + if (!(kbd_wait_for_input() & KBD_MODE_KCC)) { + /* + * If the controller does not support conversion, + * Set the keyboard to scan-code set 1. + */ + kbd_write_output_w(0xF0); + kbd_wait_for_input(); + kbd_write_output_w(0x01); + kbd_wait_for_input(); + } + kbd_write_output_w(KBD_CMD_ENABLE); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: enable keyboard: no ACK"; + + /* + * Finally, set the typematic rate to maximum. + */ + kbd_write_output_w(KBD_CMD_SET_RATE); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: Set rate: no ACK"; + kbd_write_output_w(0x00); + if (kbd_wait_for_input() != KBD_REPLY_ACK) + return "Kbd: Set rate: no ACK"; + return NULL; +} + +static void kbd_interrupt(void *dev_id) +{ + handle_kbd_event(); +} + +/****************************************************************** + * Init + ******************************************************************/ + +int kbd_init_hw(void) +{ + char* result; + + kbd_request_region(); + + result=kbd_initialize(); + if (result==NULL) { + PRINTF("AT Keyboard initialized\n"); + kbd_request_irq(kbd_interrupt); + return (1); + } else { + printf("%s\n",result); + return (-1); + } +} + +void pckbd_leds(unsigned char leds) +{ + kbd_send_data(KBD_CMD_SET_LEDS); + kbd_send_data(leds); +} + +#endif /* CONFIG_PS2KBD */ diff --git a/drivers/pci.c b/drivers/pci.c new file mode 100644 index 000000000..050582f78 --- /dev/null +++ b/drivers/pci.c @@ -0,0 +1,518 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * (C) Copyright 2002, 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI routines + */ + +#include + +#ifdef CONFIG_PCI + +#include +#include +#include +#include + +#define PCI_HOSE_OP(rw, size, type) \ +int pci_hose_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, \ + int offset, type value) \ +{ \ + return hose->rw##_##size(hose, dev, offset, value); \ +} + +PCI_HOSE_OP(read, byte, u8 *) +PCI_HOSE_OP(read, word, u16 *) +PCI_HOSE_OP(read, dword, u32 *) +PCI_HOSE_OP(write, byte, u8) +PCI_HOSE_OP(write, word, u16) +PCI_HOSE_OP(write, dword, u32) + +#ifndef CONFIG_IXP425 +#define PCI_OP(rw, size, type, error_code) \ +int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \ +{ \ + struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \ + \ + if (!hose) \ + { \ + error_code; \ + return -1; \ + } \ + \ + return pci_hose_##rw##_config_##size(hose, dev, offset, value); \ +} + +PCI_OP(read, byte, u8 *, *value = 0xff) +PCI_OP(read, word, u16 *, *value = 0xffff) +PCI_OP(read, dword, u32 *, *value = 0xffffffff) +PCI_OP(write, byte, u8, ) +PCI_OP(write, word, u16, ) +PCI_OP(write, dword, u32, ) +#endif /* CONFIG_IXP425 */ + +#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \ +int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\ + pci_dev_t dev, \ + int offset, type val) \ +{ \ + u32 val32; \ + \ + if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ + return -1; \ + \ + *val = (val32 >> ((offset & (int)off_mask) * 8)); \ + \ + return 0; \ +} + +#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \ +int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\ + pci_dev_t dev, \ + int offset, type val) \ +{ \ + u32 val32, mask, ldata, shift; \ + \ + if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\ + return -1; \ + \ + shift = ((offset & (int)off_mask) * 8); \ + ldata = (((unsigned long)val) & val_mask) << shift; \ + mask = val_mask << shift; \ + val32 = (val32 & ~mask) | ldata; \ + \ + if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\ + return -1; \ + \ + return 0; \ +} + +PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03) +PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02) +PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff) +PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff) + +/* + * + */ + +static struct pci_controller* hose_head = NULL; + +void pci_register_hose(struct pci_controller* hose) +{ + struct pci_controller **phose = &hose_head; + + while(*phose) + phose = &(*phose)->next; + + hose->next = NULL; + + *phose = hose; +} + +struct pci_controller *pci_bus_to_hose (int bus) +{ + struct pci_controller *hose; + + for (hose = hose_head; hose; hose = hose->next) + if (bus >= hose->first_busno && bus <= hose->last_busno) + return hose; + + printf("pci_bus_to_hose() failed\n"); + return NULL; +} + +#ifndef CONFIG_IXP425 +pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) +{ + struct pci_controller * hose; + u16 vendor, device; + u8 header_type; + pci_dev_t bdf; + int i, bus, found_multi = 0; + + for (hose = hose_head; hose; hose = hose->next) + { +#ifdef CFG_SCSI_SCAN_BUS_REVERSE + for (bus = hose->last_busno; bus >= hose->first_busno; bus--) +#else + for (bus = hose->first_busno; bus <= hose->last_busno; bus++) +#endif + for (bdf = PCI_BDF(bus,0,0); +#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX) + bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); +#else + bdf < PCI_BDF(bus+1,0,0); +#endif + bdf += PCI_BDF(0,0,1)) + { + if (!PCI_FUNC(bdf)) { + pci_read_config_byte(bdf, + PCI_HEADER_TYPE, + &header_type); + + found_multi = header_type & 0x80; + } else { + if (!found_multi) + continue; + } + + pci_read_config_word(bdf, + PCI_VENDOR_ID, + &vendor); + pci_read_config_word(bdf, + PCI_DEVICE_ID, + &device); + + for (i=0; ids[i].vendor != 0; i++) + if (vendor == ids[i].vendor && + device == ids[i].device) + { + if (index <= 0) + return bdf; + + index--; + } + } + } + + return (-1); +} +#endif /* CONFIG_IXP425 */ + +pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index) +{ + static struct pci_device_id ids[2] = {{}, {0, 0}}; + + ids[0].vendor = vendor; + ids[0].device = device; + + return pci_find_devices(ids, index); +} + +/* + * + */ + +unsigned long pci_hose_phys_to_bus (struct pci_controller *hose, + unsigned long phys_addr, + unsigned long flags) +{ + struct pci_region *res; + unsigned long bus_addr; + int i; + + if (!hose) { + printf ("pci_hose_phys_to_bus: %s\n", "invalid hose"); + goto Done; + } + + for (i = 0; i < hose->region_count; i++) { + res = &hose->regions[i]; + + if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) + continue; + + bus_addr = phys_addr - res->phys_start + res->bus_start; + + if (bus_addr >= res->bus_start && + bus_addr < res->bus_start + res->size) { + return bus_addr; + } + } + + printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address"); + +Done: + return 0; +} + +unsigned long pci_hose_bus_to_phys(struct pci_controller* hose, + unsigned long bus_addr, + unsigned long flags) +{ + struct pci_region *res; + int i; + + if (!hose) { + printf ("pci_hose_bus_to_phys: %s\n", "invalid hose"); + goto Done; + } + + for (i = 0; i < hose->region_count; i++) { + res = &hose->regions[i]; + + if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0) + continue; + + if (bus_addr >= res->bus_start && + bus_addr < res->bus_start + res->size) { + return bus_addr - res->bus_start + res->phys_start; + } + } + + printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address"); + +Done: + return 0; +} + +/* + * + */ + +int pci_hose_config_device(struct pci_controller *hose, + pci_dev_t dev, + unsigned long io, + unsigned long mem, + unsigned long command) +{ + unsigned int bar_response, bar_size, bar_value, old_command; + unsigned char pin; + int bar, found_mem64; + + debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n", + io, mem, command); + + pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0); + + for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) { + pci_hose_write_config_dword (hose, dev, bar, 0xffffffff); + pci_hose_read_config_dword (hose, dev, bar, &bar_response); + + if (!bar_response) + continue; + + found_mem64 = 0; + + /* Check the BAR type and set our address mask */ + if (bar_response & PCI_BASE_ADDRESS_SPACE) { + bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; + /* round up region base address to a multiple of size */ + io = ((io - 1) | (bar_size - 1)) + 1; + bar_value = io; + /* compute new region base address */ + io = io + bar_size; + } else { + if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == + PCI_BASE_ADDRESS_MEM_TYPE_64) + found_mem64 = 1; + + bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1; + + /* round up region base address to multiple of size */ + mem = ((mem - 1) | (bar_size - 1)) + 1; + bar_value = mem; + /* compute new region base address */ + mem = mem + bar_size; + } + + /* Write it out and update our limit */ + pci_hose_write_config_dword (hose, dev, bar, bar_value); + + if (found_mem64) { + bar += 4; + pci_hose_write_config_dword (hose, dev, bar, 0x00000000); + } + } + + /* Configure Cache Line Size Register */ + pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + + /* Configure Latency Timer */ + pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80); + + /* Disable interrupt line, if device says it wants to use interrupts */ + pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin); + if (pin != 0) { + pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff); + } + + pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command); + pci_hose_write_config_dword (hose, dev, PCI_COMMAND, + (old_command & 0xffff0000) | command); + + return 0; +} + +/* + * + */ + +struct pci_config_table *pci_find_config(struct pci_controller *hose, + unsigned short class, + unsigned int vendor, + unsigned int device, + unsigned int bus, + unsigned int dev, + unsigned int func) +{ + struct pci_config_table *table; + + for (table = hose->config_table; table && table->vendor; table++) { + if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) && + (table->device == PCI_ANY_ID || table->device == device) && + (table->class == PCI_ANY_ID || table->class == class) && + (table->bus == PCI_ANY_ID || table->bus == bus) && + (table->dev == PCI_ANY_ID || table->dev == dev) && + (table->func == PCI_ANY_ID || table->func == func)) { + return table; + } + } + + return NULL; +} + +void pci_cfgfunc_config_device(struct pci_controller *hose, + pci_dev_t dev, + struct pci_config_table *entry) +{ + pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]); +} + +void pci_cfgfunc_do_nothing(struct pci_controller *hose, + pci_dev_t dev, struct pci_config_table *entry) +{ +} + +/* + * + */ + +/* HJF: Changed this to return int. I think this is required + * to get the correct result when scanning bridges + */ +extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); +extern void pciauto_config_init(struct pci_controller *hose); + +int pci_hose_scan_bus(struct pci_controller *hose, int bus) +{ + unsigned int sub_bus, found_multi=0; + unsigned short vendor, device, class; + unsigned char header_type; + struct pci_config_table *cfg; + pci_dev_t dev; + + sub_bus = bus; + + for (dev = PCI_BDF(bus,0,0); + dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1); + dev += PCI_BDF(0,0,1)) + { + /* Skip our host bridge */ + if ( dev == PCI_BDF(hose->first_busno,0,0) ) { +#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */ + /* + * Only skip hostbridge configuration if "pciconfighost" is not set + */ + if (getenv("pciconfighost") == NULL) { + continue; /* Skip our host bridge */ + } +#else + continue; /* Skip our host bridge */ +#endif + } + + if (PCI_FUNC(dev) && !found_multi) + continue; + + pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); + + pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor); + + if (vendor != 0xffff && vendor != 0x0000) { + + if (!PCI_FUNC(dev)) + found_multi = header_type & 0x80; + + debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n", + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) ); + + pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); + pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); + + cfg = pci_find_config(hose, class, vendor, device, + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); + if (cfg) { + cfg->config_device(hose, dev, cfg); + sub_bus = max(sub_bus, hose->current_busno); +#ifdef CONFIG_PCI_PNP + } else { + int n = pciauto_config_device(hose, dev); + + sub_bus = max(sub_bus, n); +#endif + } + if (hose->fixup_irq) + hose->fixup_irq(hose, dev); + +#ifdef CONFIG_PCI_SCAN_SHOW + /* Skip our host bridge */ + if ( dev != PCI_BDF(hose->first_busno,0,0) ) { + unsigned char int_line; + + pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE, + &int_line); + printf(" %02x %02x %04x %04x %04x %02x\n", + PCI_BUS(dev), PCI_DEV(dev), vendor, device, class, + int_line); + } +#endif + } + } + + return sub_bus; +} + +int pci_hose_scan(struct pci_controller *hose) +{ +#ifdef CONFIG_PCI_PNP + pciauto_config_init(hose); +#endif + return pci_hose_scan_bus(hose, hose->first_busno); +} + +void pci_init(void) +{ +#if defined(CONFIG_PCI_BOOTDELAY) + char *s; + int i; + + /* wait "pcidelay" ms (if defined)... */ + s = getenv ("pcidelay"); + if (s) { + int val = simple_strtoul (s, NULL, 10); + for (i=0; i + * + * Copyright 2000 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#ifdef CONFIG_PCI + +#include + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +#define PCIAUTO_IDE_MODE_MASK 0x05 + +/* + * + */ + +void pciauto_region_init(struct pci_region* res) +{ + res->bus_lower = res->bus_start; +} + +void pciauto_region_align(struct pci_region *res, unsigned long size) +{ + res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1; +} + +int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar) +{ + unsigned long addr; + + if (!res) { + DEBUGF("No resource"); + goto error; + } + + addr = ((res->bus_lower - 1) | (size - 1)) + 1; + + if (addr - res->bus_start + size > res->size) { + DEBUGF("No room in resource"); + goto error; + } + + res->bus_lower = addr + size; + + DEBUGF("address=0x%lx", addr); + + *bar = addr; + return 0; + + error: + *bar = 0xffffffff; + return -1; +} + +/* + * + */ + +void pciauto_setup_device(struct pci_controller *hose, + pci_dev_t dev, int bars_num, + struct pci_region *mem, + struct pci_region *prefetch, + struct pci_region *io) +{ + unsigned int bar_value, bar_response, bar_size; + unsigned int cmdstat = 0; + struct pci_region *bar_res; + int bar, bar_nr = 0; + int found_mem64 = 0; + + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; + + for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) { + /* Tickle the BAR and get the response */ + pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); + pci_hose_read_config_dword(hose, dev, bar, &bar_response); + + /* If BAR is not implemented go to the next BAR */ + if (!bar_response) + continue; + + found_mem64 = 0; + + /* Check the BAR type and set our address mask */ + if (bar_response & PCI_BASE_ADDRESS_SPACE) { + bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; + bar_res = io; + + DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size); + } else { + if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == + PCI_BASE_ADDRESS_MEM_TYPE_64) + found_mem64 = 1; + + bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1; + if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH)) + bar_res = prefetch; + else + bar_res = mem; + + DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size); + } + + if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) { + /* Write it out and update our limit */ + pci_hose_write_config_dword(hose, dev, bar, bar_value); + + /* + * If we are a 64-bit decoder then increment to the + * upper 32 bits of the bar and force it to locate + * in the lower 4GB of memory. + */ + if (found_mem64) { + bar += 4; + pci_hose_write_config_dword(hose, dev, bar, 0x00000000); + } + + cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ? + PCI_COMMAND_IO : PCI_COMMAND_MEMORY; + } + + DEBUGF("\n"); + + bar_nr++; + } + + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); + pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); +} + +static void pciauto_prescan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus) +{ + struct pci_region *pci_mem = hose->pci_mem; + struct pci_region *pci_prefetch = hose->pci_prefetch; + struct pci_region *pci_io = hose->pci_io; + unsigned int cmdstat; + + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + + /* Configure bus number registers */ + pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev)); + pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus); + pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff); + + if (pci_mem) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_mem, 0x100000); + + /* Set up memory and I/O filter limits, assume 32-bit I/O space */ + pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE, + (pci_mem->bus_lower & 0xfff00000) >> 16); + + cmdstat |= PCI_COMMAND_MEMORY; + } + + if (pci_prefetch) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_prefetch, 0x100000); + + /* Set up memory and I/O filter limits, assume 32-bit I/O space */ + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, + (pci_prefetch->bus_lower & 0xfff00000) >> 16); + + cmdstat |= PCI_COMMAND_MEMORY; + } else { + /* We don't support prefetchable memory for now, so disable */ + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000); + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000); + } + + if (pci_io) { + /* Round I/O allocator to 4KB boundary */ + pciauto_region_align(pci_io, 0x1000); + + pci_hose_write_config_byte(hose, dev, PCI_IO_BASE, + (pci_io->bus_lower & 0x0000f000) >> 8); + pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16, + (pci_io->bus_lower & 0xffff0000) >> 16); + + cmdstat |= PCI_COMMAND_IO; + } + + /* Enable memory and I/O accesses, enable bus master */ + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER); +} + +static void pciauto_postscan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus) +{ + struct pci_region *pci_mem = hose->pci_mem; + struct pci_region *pci_prefetch = hose->pci_prefetch; + struct pci_region *pci_io = hose->pci_io; + + /* Configure bus number registers */ + pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus); + + if (pci_mem) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_mem, 0x100000); + + pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT, + (pci_mem->bus_lower-1) >> 16); + } + + if (pci_prefetch) { + /* Round memory allocator to 1MB boundary */ + pciauto_region_align(pci_prefetch, 0x100000); + + pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, + (pci_prefetch->bus_lower-1) >> 16); + } + + if (pci_io) { + /* Round I/O allocator to 4KB boundary */ + pciauto_region_align(pci_io, 0x1000); + + pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT, + ((pci_io->bus_lower-1) & 0x0000f000) >> 8); + pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16, + ((pci_io->bus_lower-1) & 0xffff0000) >> 16); + } +} + +/* + * + */ + +void pciauto_config_init(struct pci_controller *hose) +{ + int i; + + hose->pci_io = hose->pci_mem = NULL; + + for (i=0; iregion_count; i++) { + switch(hose->regions[i].flags) { + case PCI_REGION_IO: + if (!hose->pci_io || + hose->pci_io->size < hose->regions[i].size) + hose->pci_io = hose->regions + i; + break; + case PCI_REGION_MEM: + if (!hose->pci_mem || + hose->pci_mem->size < hose->regions[i].size) + hose->pci_mem = hose->regions + i; + break; + case (PCI_REGION_MEM | PCI_REGION_PREFETCH): + if (!hose->pci_prefetch || + hose->pci_prefetch->size < hose->regions[i].size) + hose->pci_prefetch = hose->regions + i; + break; + } + } + + + if (hose->pci_mem) { + pciauto_region_init(hose->pci_mem); + + DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n", + hose->pci_mem->bus_start, + hose->pci_mem->bus_start + hose->pci_mem->size - 1); + } + + if (hose->pci_prefetch) { + pciauto_region_init(hose->pci_prefetch); + + DEBUGF("PCI Autoconfig: Prefetchable Memory region: [%lx-%lx]\n", + hose->pci_prefetch->bus_start, + hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1); + } + + if (hose->pci_io) { + pciauto_region_init(hose->pci_io); + + DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n", + hose->pci_io->bus_start, + hose->pci_io->bus_start + hose->pci_io->size - 1); + } +} + +/* HJF: Changed this to return int. I think this is required + * to get the correct result when scanning bridges + */ +int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned int sub_bus = PCI_BUS(dev); + unsigned short class; + unsigned char prg_iface; + int n; + + pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); + + switch(class) { + case PCI_CLASS_BRIDGE_PCI: + hose->current_busno++; + pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + + DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev)); + + /* Passing in current_busno allows for sibling P2P bridges */ + pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); + /* + * need to figure out if this is a subordinate bridge on the bus + * to be able to properly set the pri/sec/sub bridge registers. + */ + n = pci_hose_scan_bus(hose, hose->current_busno); + + /* figure out the deepest we've gone for this leg */ + sub_bus = max(n, sub_bus); + pciauto_postscan_setup_bridge(hose, dev, sub_bus); + + sub_bus = hose->current_busno; + break; + + case PCI_CLASS_STORAGE_IDE: + pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface); + if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) { + DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n"); + return sub_bus; + } + + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + break; + + case PCI_CLASS_BRIDGE_CARDBUS: + /* just do a minimal setup of the bridge, let the OS take care of the rest */ + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + + DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev)); + + hose->current_busno++; + break; + +#ifdef CONFIG_MPC5200 + case PCI_CLASS_BRIDGE_OTHER: + DEBUGF("PCI Autoconfig: Skipping bridge device %d\n", + PCI_DEV(dev)); + break; +#endif +#ifdef CONFIG_MPC834X + case PCI_CLASS_BRIDGE_OTHER: + /* + * The host/PCI bridge 1 seems broken in 8349 - it presents + * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_ + * device claiming resources io/mem/irq.. we only allow for + * the PIMMR window to be allocated (BAR0 - 1MB size) + */ + DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n"); + pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + break; +#endif + default: + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); + break; + } + + return sub_bus; +} + +#endif /* CONFIG_PCI */ diff --git a/drivers/pci_indirect.c b/drivers/pci_indirect.c new file mode 100644 index 000000000..d7be0810f --- /dev/null +++ b/drivers/pci_indirect.c @@ -0,0 +1,138 @@ +/* + * Support for indirect PCI bridges. + * + * Copyright (C) 1998 Gabriel Paubert. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include + +#ifdef CONFIG_PCI +#if (!defined(__I386__) && !defined(CONFIG_IXDP425)) + +#include +#include +#include + +#define cfg_read(val, addr, type, op) *val = op((type)(addr)) +#define cfg_write(val, addr, type, op) op((type *)(addr), (val)) + +#ifdef CONFIG_IXP425 +extern unsigned char in_8 (volatile unsigned *addr); +extern unsigned short in_le16 (volatile unsigned *addr); +extern unsigned in_le32 (volatile unsigned *addr); +extern void out_8 (volatile unsigned *addr, char val); +extern void out_le16 (volatile unsigned *addr, unsigned short val); +extern void out_le32 (volatile unsigned *addr, unsigned int val); +#endif /* CONFIG_IXP425 */ + +#if defined(CONFIG_MPC8260) +#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + u32 b, d,f; \ + b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ + b = b - hose->first_busno; \ + dev = PCI_BDF(b, d, f); \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + sync(); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + return 0; \ +} +#elif defined(CONFIG_E500) +#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + u32 b, d,f; \ + b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ + b = b - hose->first_busno; \ + dev = PCI_BDF(b, d, f); \ + *(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \ + sync(); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + return 0; \ +} +#elif defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SPE) +#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + u32 b, d,f; \ + b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ + b = b - hose->first_busno; \ + dev = PCI_BDF(b, d, f); \ + if (PCI_BUS(dev) > 0) \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \ + else \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + return 0; \ +} +#else +#define INDIRECT_PCI_OP(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + u32 b, d,f; \ + b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ + b = b - hose->first_busno; \ + dev = PCI_BDF(b, d, f); \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + return 0; \ +} +#endif + +#define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask) \ +static int \ +indirect_##rw##_config_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + unsigned int msr = mfmsr(); \ + mtmsr(msr & ~(MSR_EE | MSR_CE)); \ + out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + out_le32(hose->cfg_addr, 0x00000000); \ + mtmsr(msr); \ + return 0; \ +} + +INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3) +INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2) +INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0) +#ifdef CONFIG_405GP +INDIRECT_PCI_OP_ERRATA6(write, byte, u8, out_8, 3) +INDIRECT_PCI_OP_ERRATA6(write, word, u16, out_le16, 2) +INDIRECT_PCI_OP_ERRATA6(write, dword, u32, out_le32, 0) +#else +INDIRECT_PCI_OP(write, byte, u8, out_8, 3) +INDIRECT_PCI_OP(write, word, u16, out_le16, 2) +INDIRECT_PCI_OP(write, dword, u32, out_le32, 0) +#endif + +void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) +{ + pci_set_ops(hose, + indirect_read_config_byte, + indirect_read_config_word, + indirect_read_config_dword, + indirect_write_config_byte, + indirect_write_config_word, + indirect_write_config_dword); + + hose->cfg_addr = (unsigned int *) cfg_addr; + hose->cfg_data = (unsigned char *) cfg_data; +} + +#endif /* !__I386__ && !CONFIG_IXDP425 */ +#endif /* CONFIG_PCI */ diff --git a/drivers/pcnet.c b/drivers/pcnet.c new file mode 100644 index 000000000..da9ac7f99 --- /dev/null +++ b/drivers/pcnet.c @@ -0,0 +1,526 @@ +/* + * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. + * + * This driver for AMD PCnet network controllers is derived from the + * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#if 0 +#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ +#endif + +#if PCNET_DEBUG_LEVEL > 0 +#define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args) +#if PCNET_DEBUG_LEVEL > 1 +#define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args) +#else +#define PCNET_DEBUG2(fmt,args...) +#endif +#else +#define PCNET_DEBUG1(fmt,args...) +#define PCNET_DEBUG2(fmt,args...) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ + && defined(CONFIG_PCNET) + +#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) +#error "Macro for PCnet chip version is not defined!" +#endif + +/* + * Set the number of Tx and Rx buffers, using Log_2(# buffers). + * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. + * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). + */ +#define PCNET_LOG_TX_BUFFERS 0 +#define PCNET_LOG_RX_BUFFERS 2 + +#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) +#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) + +#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) +#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) + +#define PKT_BUF_SZ 1544 + +/* The PCNET Rx and Tx ring descriptors. */ +struct pcnet_rx_head { + u32 base; + s16 buf_length; + s16 status; + u32 msg_length; + u32 reserved; +}; + +struct pcnet_tx_head { + u32 base; + s16 length; + s16 status; + u32 misc; + u32 reserved; +}; + +/* The PCNET 32-Bit initialization block, described in databook. */ +struct pcnet_init_block { + u16 mode; + u16 tlen_rlen; + u8 phys_addr[6]; + u16 reserved; + u32 filter[2]; + /* Receive and transmit ring base, along with extra bits. */ + u32 rx_ring; + u32 tx_ring; + u32 reserved2; +}; + +typedef struct pcnet_priv { + struct pcnet_rx_head rx_ring[RX_RING_SIZE]; + struct pcnet_tx_head tx_ring[TX_RING_SIZE]; + struct pcnet_init_block init_block; + /* Receive Buffer space */ + unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; + int cur_rx; + int cur_tx; +} pcnet_priv_t; + +static pcnet_priv_t *lp; + +/* Offsets from base I/O address for WIO mode */ +#define PCNET_RDP 0x10 +#define PCNET_RAP 0x12 +#define PCNET_RESET 0x14 +#define PCNET_BDP 0x16 + +static u16 pcnet_read_csr (struct eth_device *dev, int index) +{ + outw (index, dev->iobase+PCNET_RAP); + return inw (dev->iobase+PCNET_RDP); +} + +static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) +{ + outw (index, dev->iobase+PCNET_RAP); + outw (val, dev->iobase+PCNET_RDP); +} + +static u16 pcnet_read_bcr (struct eth_device *dev, int index) +{ + outw (index, dev->iobase+PCNET_RAP); + return inw (dev->iobase+PCNET_BDP); +} + +static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) +{ + outw (index, dev->iobase+PCNET_RAP); + outw (val, dev->iobase+PCNET_BDP); +} + +static void pcnet_reset (struct eth_device *dev) +{ + inw (dev->iobase+PCNET_RESET); +} + +static int pcnet_check (struct eth_device *dev) +{ + outw (88, dev->iobase+PCNET_RAP); + return (inw (dev->iobase+PCNET_RAP) == 88); +} + +static int pcnet_init( struct eth_device* dev, bd_t *bis); +static int pcnet_send (struct eth_device* dev, volatile void *packet, + int length); +static int pcnet_recv (struct eth_device* dev); +static void pcnet_halt (struct eth_device* dev); +static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_num); + +#define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) +#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE }, + { } +}; + + +int pcnet_initialize(bd_t *bis) +{ + pci_dev_t devbusfn; + struct eth_device* dev; + u16 command, status; + int dev_nr = 0; + + PCNET_DEBUG1("\npcnet_initialize...\n"); + + for (dev_nr = 0; ; dev_nr++) { + + /* + * Find the PCnet PCI device(s). + */ + if ((devbusfn = pci_find_devices(supported, dev_nr)) < 0) { + break; + } + + /* + * Allocate and pre-fill the device structure. + */ + dev = (struct eth_device*) malloc(sizeof *dev); + dev->priv = (void *)devbusfn; + sprintf(dev->name, "pcnet#%d", dev_nr); + + /* + * Setup the PCI device. + */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase); + dev->iobase &= ~0xf; + + PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", + dev->name, devbusfn, dev->iobase); + + command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; + pci_write_config_word(devbusfn, PCI_COMMAND, command); + pci_read_config_word(devbusfn, PCI_COMMAND, &status); + if ((status & command) != command) { + printf("%s: Couldn't enable IO access or Bus Mastering\n", + dev->name); + free(dev); + continue; + } + + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); + + /* + * Probe the PCnet chip. + */ + if (pcnet_probe(dev, bis, dev_nr) < 0) { + free(dev); + continue; + } + + /* + * Setup device structure and register the driver. + */ + dev->init = pcnet_init; + dev->halt = pcnet_halt; + dev->send = pcnet_send; + dev->recv = pcnet_recv; + + eth_register(dev); + } + + udelay(10 * 1000); + + return dev_nr; +} + +static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_nr) +{ + int chip_version; + char *chipname; +#ifdef PCNET_HAS_PROM + int i; +#endif + + /* Reset the PCnet controller */ + pcnet_reset(dev); + + /* Check if register access is working */ + if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { + printf("%s: CSR register access check failed\n", dev->name); + return -1; + } + + /* Identify the chip */ + chip_version = pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev,89) << 16); + if ((chip_version & 0xfff) != 0x003) + return -1; + chip_version = (chip_version >> 12) & 0xffff; + switch (chip_version) { +#ifdef CONFIG_PCNET_79C973 + case 0x2625: + chipname = "PCnet/FAST III 79C973"; /* PCI */ + break; +#endif +#ifdef CONFIG_PCNET_79C975 + case 0x2627: + chipname = "PCnet/FAST III 79C975"; /* PCI */ + break; +#endif + default: + printf("%s: PCnet version %#x not supported\n", + dev->name, chip_version); + return -1; + } + + PCNET_DEBUG1("AMD %s\n", chipname); + +#ifdef PCNET_HAS_PROM + /* + * In most chips, after a chip reset, the ethernet address is read from + * the station address PROM at the base address and programmed into the + * "Physical Address Registers" CSR12-14. + */ + for (i = 0; i < 3; i++) { + unsigned int val; + val = pcnet_read_csr(dev, i+12) & 0x0ffff; + /* There may be endianness issues here. */ + dev->enetaddr[2*i ] = val & 0x0ff; + dev->enetaddr[2*i+1] = (val >> 8) & 0x0ff; + } +#endif /* PCNET_HAS_PROM */ + + return 0; +} + +static int pcnet_init(struct eth_device* dev, bd_t *bis) +{ + int i, val; + u32 addr; + + PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); + + /* Switch pcnet to 32bit mode */ + pcnet_write_bcr (dev, 20, 2); + +#ifdef CONFIG_PN62 + /* Setup LED registers */ + val = pcnet_read_bcr (dev, 2) | 0x1000; + pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ + pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ + pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ + pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ + pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ +#endif + + /* Set/reset autoselect bit */ + val = pcnet_read_bcr (dev, 2) & ~2; + val |= 2; + pcnet_write_bcr (dev, 2, val); + + /* Enable auto negotiate, setup, disable fd */ + val = pcnet_read_bcr(dev, 32) & ~0x98; + val |= 0x20; + pcnet_write_bcr(dev, 32, val); + + /* + * We only maintain one structure because the drivers will never + * be used concurrently. In 32bit mode the RX and TX ring entries + * must be aligned on 16-byte boundaries. + */ + if (lp == NULL) { + addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); + addr = (addr + 0xf) & ~0xf; + lp = (pcnet_priv_t *)addr; + } + + lp->init_block.mode = cpu_to_le16(0x0000); + lp->init_block.filter[0] = 0x00000000; + lp->init_block.filter[1] = 0x00000000; + + /* + * Initialize the Rx ring. + */ + lp->cur_rx = 0; + for (i = 0; i < RX_RING_SIZE; i++) { + lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); + lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); + lp->rx_ring[i].status = cpu_to_le16(0x8000); + PCNET_DEBUG1("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", + i, lp->rx_ring[i].base, lp->rx_ring[i].buf_length, + lp->rx_ring[i].status); + } + + /* + * Initialize the Tx ring. The Tx buffer address is filled in as + * needed, but we do need to clear the upper ownership bit. + */ + lp->cur_tx = 0; + for (i = 0; i < TX_RING_SIZE; i++) { + lp->tx_ring[i].base = 0; + lp->tx_ring[i].status = 0; + } + + /* + * Setup Init Block. + */ + PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block); + + for (i = 0; i < 6; i++) { + lp->init_block.phys_addr[i] = dev->enetaddr[i]; + PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]); + } + + lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | + RX_RING_LEN_BITS); + lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring); + lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring); + + PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", + lp->init_block.tlen_rlen, + lp->init_block.rx_ring, lp->init_block.tx_ring); + + /* + * Tell the controller where the Init Block is located. + */ + addr = PCI_TO_MEM(dev, &lp->init_block); + pcnet_write_csr(dev, 1, addr & 0xffff); + pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); + + pcnet_write_csr (dev, 4, 0x0915); + pcnet_write_csr (dev, 0, 0x0001); /* start */ + + /* Wait for Init Done bit */ + for (i = 10000; i > 0; i--) { + if (pcnet_read_csr (dev, 0) & 0x0100) + break; + udelay(10); + } + if (i <= 0) { + printf("%s: TIMEOUT: controller init failed\n", dev->name); + pcnet_reset (dev); + return 0; + } + + /* + * Finally start network controller operation. + */ + pcnet_write_csr (dev, 0, 0x0002); + + return 1; +} + +static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len) +{ + int i, status; + struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; + + PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet); + + /* Wait for completion by testing the OWN bit */ + for (i = 1000; i > 0; i--) { + status = le16_to_cpu(entry->status); + if ((status & 0x8000) == 0) + break; + udelay(100); + PCNET_DEBUG2("."); + } + if (i <= 0) { + printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", + dev->name, lp->cur_tx, status); + pkt_len = 0; + goto failure; + } + + /* + * Setup Tx ring. Caution: the write order is important here, + * set the status with the "ownership" bits last. + */ + status = 0x8300; + entry->length = le16_to_cpu(-pkt_len); + entry->misc = 0x00000000; + entry->base = PCI_TO_MEM_LE(dev, packet); + entry->status = le16_to_cpu(status); + + /* Trigger an immediate send poll. */ + pcnet_write_csr (dev, 0, 0x0008); + + failure: + if (++lp->cur_tx >= TX_RING_SIZE) + lp->cur_tx = 0; + + PCNET_DEBUG2("done\n"); + return pkt_len; +} + +static int pcnet_recv(struct eth_device* dev) +{ + struct pcnet_rx_head *entry; + int pkt_len = 0; + u16 status; + + while (1) { + entry = &lp->rx_ring[lp->cur_rx]; + /* + * If we own the next entry, it's a new packet. Send it up. + */ + if (((status = le16_to_cpu(entry->status)) & 0x8000) != 0) { + break; + } + status >>= 8; + + if (status != 0x03) { /* There was an error. */ + + printf("%s: Rx%d", dev->name, lp->cur_rx); + PCNET_DEBUG1(" (status=0x%x)", status); + if (status & 0x20) printf(" Frame"); + if (status & 0x10) printf(" Overflow"); + if (status & 0x08) printf(" CRC"); + if (status & 0x04) printf(" Fifo"); + printf(" Error\n"); + entry->status &= le16_to_cpu(0x03ff); + + } else { + + pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4; + if (pkt_len < 60) { + printf("%s: Rx%d: invalid packet length %d\n", + dev->name, lp->cur_rx, pkt_len); + } else { + NetReceive(lp->rx_buf[lp->cur_rx], pkt_len); + PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", + lp->cur_rx, pkt_len, lp->rx_buf[lp->cur_rx]); + } + } + entry->status |= cpu_to_le16(0x8000); + + if (++lp->cur_rx >= RX_RING_SIZE) + lp->cur_rx = 0; + } + return pkt_len; +} + +static void pcnet_halt(struct eth_device* dev) +{ + int i; + + PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); + + /* Reset the PCnet controller */ + pcnet_reset (dev); + + /* Wait for Stop bit */ + for (i = 1000; i > 0; i--) { + if (pcnet_read_csr (dev, 0) & 0x4) + break; + udelay(10); + } + if (i <= 0) { + printf("%s: TIMEOUT: controller reset failed\n", dev->name); + } +} + +#endif diff --git a/drivers/plb2800_eth.c b/drivers/plb2800_eth.c new file mode 100644 index 000000000..4c683d7a5 --- /dev/null +++ b/drivers/plb2800_eth.c @@ -0,0 +1,396 @@ +/* + * PLB2800 internal switch ethernet driver. + * + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ + && defined(CONFIG_PLB2800_ETHER) + +#include +#include +#include + + +#define NUM_RX_DESC PKTBUFSRX +#define TOUT_LOOP 1000000 + +#define LONG_REF(addr) (*((volatile unsigned long*)addr)) + +#define CMAC_CRX_CTRL LONG_REF(0xb800c870) +#define CMAC_CTX_CTRL LONG_REF(0xb800c874) +#define SYS_MAC_ADDR_0 LONG_REF(0xb800c878) +#define SYS_MAC_ADDR_1 LONG_REF(0xb800c87c) +#define MIPS_H_MASK LONG_REF(0xB800C810) + +#define MA_LEARN LONG_REF(0xb8008004) +#define DA_LOOKUP LONG_REF(0xb8008008) + +#define CMAC_CRX_CTRL_PD 0x00000001 +#define CMAC_CRX_CTRL_CG 0x00000002 +#define CMAC_CRX_CTRL_PL_SHIFT 2 +#define CMAC_CRIT 0x0 +#define CMAC_NON_CRIT 0x1 +#define MBOX_STAT_ID_SHF 28 +#define MBOX_STAT_CP 0x80000000 +#define MBOX_STAT_MB 0x00000001 +#define EN_MA_LEARN 0x02000000 +#define EN_DA_LKUP 0x01000000 +#define MA_DEST_SHF 11 +#define DA_DEST_SHF 11 +#define DA_STATE_SHF 19 +#define TSTAMP_MS 0x00000000 +#define SW_H_MBOX4_MASK 0x08000000 +#define SW_H_MBOX3_MASK 0x04000000 +#define SW_H_MBOX2_MASK 0x02000000 +#define SW_H_MBOX1_MASK 0x01000000 + +typedef volatile struct { + unsigned int stat; + unsigned int cmd; + unsigned int cnt; + unsigned int adr; +} mailbox_t; + +#define MBOX_REG(mb) ((mailbox_t*)(0xb800c830+(mb<<4))) + +typedef volatile struct { + unsigned int word0; + unsigned int word1; + unsigned int word2; +} mbhdr_t; + +#define MBOX_MEM(mb) ((void*)(0xb800a000+((3-mb)<<11))) + + +static int plb2800_eth_init(struct eth_device *dev, bd_t * bis); +static int plb2800_eth_send(struct eth_device *dev, volatile void *packet, + int length); +static int plb2800_eth_recv(struct eth_device *dev); +static void plb2800_eth_halt(struct eth_device *dev); + +static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr); +static unsigned char * plb2800_get_mac_addr(void); + +static int rx_new; +static int mac_addr_set = 0; + + +int plb2800_eth_initialize(bd_t * bis) +{ + struct eth_device *dev; + ulong temp; + +#ifdef DEBUG + printf("Entered plb2800_eth_initialize()\n"); +#endif + + if (!(dev = (struct eth_device *) malloc (sizeof *dev))) + { + printf("Failed to allocate memory\n"); + return 0; + } + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "PLB2800 Switch"); + dev->init = plb2800_eth_init; + dev->halt = plb2800_eth_halt; + dev->send = plb2800_eth_send; + dev->recv = plb2800_eth_recv; + + eth_register(dev); + + /* bug fix */ + *(ulong *)0xb800e800 = 0x838; + + /* Set MBOX ownership */ + temp = CMAC_CRIT << MBOX_STAT_ID_SHF; + MBOX_REG(0)->stat = temp; + MBOX_REG(1)->stat = temp; + + temp = CMAC_NON_CRIT << MBOX_STAT_ID_SHF; + MBOX_REG(2)->stat = temp; + MBOX_REG(3)->stat = temp; + + plb2800_set_mac_addr(dev, plb2800_get_mac_addr()); + + /* Disable all Mbox interrupt */ + temp = MIPS_H_MASK; + temp &= ~ (SW_H_MBOX1_MASK | SW_H_MBOX2_MASK | SW_H_MBOX3_MASK | SW_H_MBOX4_MASK) ; + MIPS_H_MASK = temp; + +#ifdef DEBUG + printf("Leaving plb2800_eth_initialize()\n"); +#endif + + return 1; +} + +static int plb2800_eth_init(struct eth_device *dev, bd_t * bis) +{ +#ifdef DEBUG + printf("Entering plb2800_eth_init()\n"); +#endif + + plb2800_set_mac_addr(dev, dev->enetaddr); + + rx_new = 0; + +#ifdef DEBUG + printf("Leaving plb2800_eth_init()\n"); +#endif + + return 0; +} + + +static int plb2800_eth_send(struct eth_device *dev, volatile void *packet, + int length) +{ + int i; + int res = -1; + u32 temp; + mailbox_t * mb = MBOX_REG(0); + char * mem = MBOX_MEM(0); + +#ifdef DEBUG + printf("Entered plb2800_eth_send()\n"); +#endif + + if (length <= 0) + { + printf ("%s: bad packet size: %d\n", dev->name, length); + goto Done; + } + + if (length < 64) + { + length = 64; + } + + temp = CMAC_CRX_CTRL_CG | ((length + 4) << CMAC_CRX_CTRL_PL_SHIFT); + +#ifdef DEBUG + printf("0 mb->stat = 0x%x\n", mb->stat); +#endif + + for(i = 0; mb->stat & (MBOX_STAT_CP | MBOX_STAT_MB); i++) + { + if (i >= TOUT_LOOP) + { + printf("%s: tx buffer not ready\n", dev->name); + printf("1 mb->stat = 0x%x\n", mb->stat); + goto Done; + } + } + + /* For some strange reason, memcpy doesn't work, here! + */ + do + { + int words = (length >> 2) + 1; + unsigned int* dst = (unsigned int*)(mem); + unsigned int* src = (unsigned int*)(packet); + for (i = 0; i < words; i++) + { + *dst = *src; + dst++; + src++; + }; + } while(0); + + CMAC_CRX_CTRL = temp; + mb->cmd = MBOX_STAT_CP; + +#ifdef DEBUG + printf("2 mb->stat = 0x%x\n", mb->stat); +#endif + + res = length; +Done: + +#ifdef DEBUG + printf("Leaving plb2800_eth_send()\n"); +#endif + + return res; +} + + +static int plb2800_eth_recv(struct eth_device *dev) +{ + int length = 0; + mailbox_t * mbox = MBOX_REG(3); + unsigned char * hdr = MBOX_MEM(3); + unsigned int stat; + +#ifdef DEBUG + printf("Entered plb2800_eth_recv()\n"); +#endif + + for (;;) + { + stat = mbox->stat; + + if (!(stat & MBOX_STAT_CP)) + { + break; + } + + length = ((*(hdr + 6) & 0x3f) << 8) + *(hdr + 7); + memcpy((void *)NetRxPackets[rx_new], hdr + 12, length); + + stat &= ~MBOX_STAT_CP; + mbox->stat = stat; +#ifdef DEBUG + { + int i; + for (i=0;i + +#ifdef CONFIG_PS2MULT + +#include +#include +#include + +/* #define DEBUG_MULT */ +/* #define DEBUG_KEYB */ + +#define KBD_STAT_DEFAULT (KBD_STAT_SELFTEST | KBD_STAT_UNLOCKED) + +#define PRINTF(format, args...) printf("ps2mult.c: " format, ## args) + +#ifdef DEBUG_MULT +#define PRINTF_MULT(format, args...) printf("PS2MULT: " format, ## args) +#else +#define PRINTF_MULT(format, args...) +#endif + +#ifdef DEBUG_KEYB +#define PRINTF_KEYB(format, args...) printf("KEYB: " format, ## args) +#else +#define PRINTF_KEYB(format, args...) +#endif + + +static ulong start_time; +static int init_done = 0; + +static int received_escape = 0; +static int received_bsync = 0; +static int received_selector = 0; + +static int kbd_command_active = 0; +static int mouse_command_active = 0; +static int ctl_command_active = 0; + +static u_char command_byte = 0; + +static void (*keyb_handler)(void *dev_id); + +static u_char ps2mult_buf [PS2BUF_SIZE]; +static atomic_t ps2mult_buf_cnt; +static int ps2mult_buf_in_idx; +static int ps2mult_buf_out_idx; + +static u_char ps2mult_buf_status [PS2BUF_SIZE]; + +#ifndef CONFIG_BOARD_EARLY_INIT_R +#error #define CONFIG_BOARD_EARLY_INIT_R and call ps2mult_early_init() in board_early_init_r() +#endif +void ps2mult_early_init (void) +{ + start_time = get_timer(0); +} + +static void ps2mult_send_byte(u_char byte, u_char sel) +{ + ps2ser_putc(sel); + + if (sel == PS2MULT_KB_SELECTOR) { + PRINTF_MULT("0x%02x send KEYBOARD\n", byte); + kbd_command_active = 1; + } else { + PRINTF_MULT("0x%02x send MOUSE\n", byte); + mouse_command_active = 1; + } + + switch (byte) { + case PS2MULT_ESCAPE: + case PS2MULT_BSYNC: + case PS2MULT_KB_SELECTOR: + case PS2MULT_MS_SELECTOR: + case PS2MULT_SESSION_START: + case PS2MULT_SESSION_END: + ps2ser_putc(PS2MULT_ESCAPE); + break; + default: + break; + } + + ps2ser_putc(byte); +} + +static void ps2mult_receive_byte(u_char byte, u_char sel) +{ + u_char status = KBD_STAT_DEFAULT; + +#if 1 /* Ignore mouse in U-Boot */ + if (sel == PS2MULT_MS_SELECTOR) return; +#endif + + if (sel == PS2MULT_KB_SELECTOR) { + if (kbd_command_active) { + if (!received_bsync) { + PRINTF_MULT("0x%02x lost KEYBOARD !!!\n", byte); + return; + } else { + kbd_command_active = 0; + received_bsync = 0; + } + } + PRINTF_MULT("0x%02x receive KEYBOARD\n", byte); + status |= KBD_STAT_IBF | KBD_STAT_OBF; + } else { + if (mouse_command_active) { + if (!received_bsync) { + PRINTF_MULT("0x%02x lost MOUSE !!!\n", byte); + return; + } else { + mouse_command_active = 0; + received_bsync = 0; + } + } + PRINTF_MULT("0x%02x receive MOUSE\n", byte); + status |= KBD_STAT_IBF | KBD_STAT_OBF | KBD_STAT_MOUSE_OBF; + } + + if (atomic_read(&ps2mult_buf_cnt) < PS2BUF_SIZE) { + ps2mult_buf_status[ps2mult_buf_in_idx] = status; + ps2mult_buf[ps2mult_buf_in_idx++] = byte; + ps2mult_buf_in_idx &= (PS2BUF_SIZE - 1); + atomic_inc(&ps2mult_buf_cnt); + } else { + PRINTF("buffer overflow\n"); + } + + if (received_bsync) { + PRINTF("unexpected BSYNC\n"); + received_bsync = 0; + } +} + +void ps2mult_callback (int in_cnt) +{ + int i; + u_char byte; + static int keyb_handler_active = 0; + + if (!init_done) { + return; + } + + for (i = 0; i < in_cnt; i ++) { + byte = ps2ser_getc(); + + if (received_escape) { + ps2mult_receive_byte(byte, received_selector); + received_escape = 0; + } else switch (byte) { + case PS2MULT_ESCAPE: + PRINTF_MULT("ESCAPE receive\n"); + received_escape = 1; + break; + + case PS2MULT_BSYNC: + PRINTF_MULT("BSYNC receive\n"); + received_bsync = 1; + break; + + case PS2MULT_KB_SELECTOR: + case PS2MULT_MS_SELECTOR: + PRINTF_MULT("%s receive\n", + byte == PS2MULT_KB_SELECTOR ? "KB_SEL" : "MS_SEL"); + received_selector = byte; + break; + + case PS2MULT_SESSION_START: + case PS2MULT_SESSION_END: + PRINTF_MULT("%s receive\n", + byte == PS2MULT_SESSION_START ? + "SESSION_START" : "SESSION_END"); + break; + + default: + ps2mult_receive_byte(byte, received_selector); + } + } + + if (keyb_handler && !keyb_handler_active && + atomic_read(&ps2mult_buf_cnt)) { + keyb_handler_active = 1; + keyb_handler(NULL); + keyb_handler_active = 0; + } +} + +u_char ps2mult_read_status(void) +{ + u_char byte; + + if (atomic_read(&ps2mult_buf_cnt) == 0) { + ps2ser_check(); + } + + if (atomic_read(&ps2mult_buf_cnt)) { + byte = ps2mult_buf_status[ps2mult_buf_out_idx]; + } else { + byte = KBD_STAT_DEFAULT; + } + PRINTF_KEYB("read_status()=0x%02x\n", byte); + return byte; +} + +u_char ps2mult_read_input(void) +{ + u_char byte = 0; + + if (atomic_read(&ps2mult_buf_cnt) == 0) { + ps2ser_check(); + } + + if (atomic_read(&ps2mult_buf_cnt)) { + byte = ps2mult_buf[ps2mult_buf_out_idx++]; + ps2mult_buf_out_idx &= (PS2BUF_SIZE - 1); + atomic_dec(&ps2mult_buf_cnt); + } + PRINTF_KEYB("read_input()=0x%02x\n", byte); + return byte; +} + +void ps2mult_write_output(u_char val) +{ + int i; + + PRINTF_KEYB("write_output(0x%02x)\n", val); + + for (i = 0; i < KBD_TIMEOUT; i++) { + if (!kbd_command_active && !mouse_command_active) { + break; + } + udelay(1000); + ps2ser_check(); + } + + if (kbd_command_active) { + PRINTF("keyboard command not acknoledged\n"); + kbd_command_active = 0; + } + + if (mouse_command_active) { + PRINTF("mouse command not acknoledged\n"); + mouse_command_active = 0; + } + + if (ctl_command_active) { + switch (ctl_command_active) { + case KBD_CCMD_WRITE_MODE: + /* Scan code conversion not supported */ + command_byte = val & ~KBD_MODE_KCC; + break; + + case KBD_CCMD_WRITE_AUX_OBUF: + ps2mult_receive_byte(val, PS2MULT_MS_SELECTOR); + break; + + case KBD_CCMD_WRITE_MOUSE: + ps2mult_send_byte(val, PS2MULT_MS_SELECTOR); + break; + + default: + PRINTF("invalid controller command\n"); + break; + } + + ctl_command_active = 0; + return; + } + + ps2mult_send_byte(val, PS2MULT_KB_SELECTOR); +} + +void ps2mult_write_command(u_char val) +{ + ctl_command_active = 0; + + PRINTF_KEYB("write_command(0x%02x)\n", val); + + switch (val) { + case KBD_CCMD_READ_MODE: + ps2mult_receive_byte(command_byte, PS2MULT_KB_SELECTOR); + break; + + case KBD_CCMD_WRITE_MODE: + ctl_command_active = val; + break; + + case KBD_CCMD_MOUSE_DISABLE: + break; + + case KBD_CCMD_MOUSE_ENABLE: + break; + + case KBD_CCMD_SELF_TEST: + ps2mult_receive_byte(0x55, PS2MULT_KB_SELECTOR); + break; + + case KBD_CCMD_KBD_TEST: + ps2mult_receive_byte(0x00, PS2MULT_KB_SELECTOR); + break; + + case KBD_CCMD_KBD_DISABLE: + break; + + case KBD_CCMD_KBD_ENABLE: + break; + + case KBD_CCMD_WRITE_AUX_OBUF: + ctl_command_active = val; + break; + + case KBD_CCMD_WRITE_MOUSE: + ctl_command_active = val; + break; + + default: + PRINTF("invalid controller command\n"); + break; + } +} + +static int ps2mult_getc_w (void) +{ + int res = -1; + int i; + + for (i = 0; i < KBD_TIMEOUT; i++) { + if (ps2ser_check()) { + res = ps2ser_getc(); + break; + } + udelay(1000); + } + + switch (res) { + case PS2MULT_KB_SELECTOR: + case PS2MULT_MS_SELECTOR: + received_selector = res; + break; + default: + break; + } + + return res; +} + +int ps2mult_init (void) +{ + int byte; + int kbd_found = 0; + int mouse_found = 0; + + while (get_timer(start_time) < CONFIG_PS2MULT_DELAY); + + ps2ser_init(); + + ps2ser_putc(PS2MULT_SESSION_START); + + ps2ser_putc(PS2MULT_KB_SELECTOR); + ps2ser_putc(KBD_CMD_RESET); + + do { + byte = ps2mult_getc_w(); + } while (byte >= 0 && byte != KBD_REPLY_ACK); + + if (byte == KBD_REPLY_ACK) { + byte = ps2mult_getc_w(); + if (byte == 0xaa) { + kbd_found = 1; + puts("keyboard"); + } + } + + if (!kbd_found) { + while (byte >= 0) { + byte = ps2mult_getc_w(); + } + } + +#if 1 /* detect mouse */ + ps2ser_putc(PS2MULT_MS_SELECTOR); + ps2ser_putc(AUX_RESET); + + do { + byte = ps2mult_getc_w(); + } while (byte >= 0 && byte != AUX_ACK); + + if (byte == AUX_ACK) { + byte = ps2mult_getc_w(); + if (byte == 0xaa) { + byte = ps2mult_getc_w(); + if (byte == 0x00) { + mouse_found = 1; + puts(", mouse"); + } + } + } + + if (!mouse_found) { + while (byte >= 0) { + byte = ps2mult_getc_w(); + } + } +#endif + + if (mouse_found || kbd_found) { + if (!received_selector) { + if (mouse_found) { + received_selector = PS2MULT_MS_SELECTOR; + } else { + received_selector = PS2MULT_KB_SELECTOR; + } + } + + init_done = 1; + } else { + puts("No device found"); + } + + puts("\n"); + +#if 0 /* for testing */ + { + int i; + u_char key[] = { + 0x1f, 0x12, 0x14, 0x12, 0x31, 0x2f, 0x39, /* setenv */ + 0x1f, 0x14, 0x20, 0x17, 0x31, 0x39, /* stdin */ + 0x1f, 0x12, 0x13, 0x17, 0x1e, 0x26, 0x1c, /* serial */ + }; + + for (i = 0; i < sizeof (key); i++) { + ps2mult_receive_byte (key[i], PS2MULT_KB_SELECTOR); + ps2mult_receive_byte (key[i] | 0x80, PS2MULT_KB_SELECTOR); + } + } +#endif + + return init_done ? 0 : -1; +} + +int ps2mult_request_irq(void (*handler)(void *)) +{ + keyb_handler = handler; + + return 0; +} + +#endif /* CONFIG_PS2MULT */ diff --git a/drivers/ps2ser.c b/drivers/ps2ser.c new file mode 100644 index 000000000..4e304f740 --- /dev/null +++ b/drivers/ps2ser.c @@ -0,0 +1,319 @@ +/*********************************************************************** + * + * (C) Copyright 2004 + * DENX Software Engineering + * Wolfgang Denk, wd@denx.de + * All rights reserved. + * + * Simple 16550A serial driver + * + * Originally from linux source (drivers/char/ps2ser.c) + * + * Used by the PS/2 multiplexer driver (ps2mult.c) + * + ***********************************************************************/ + +#include + +#ifdef CONFIG_PS2SERIAL + +#include +#include +#include +#if defined(CFG_NS16550) || defined(CONFIG_MPC85xx) +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* #define DEBUG */ + +#define PS2SER_BAUD 57600 + +#ifdef CONFIG_MPC5xxx +#if CONFIG_PS2SERIAL == 1 +#define PSC_BASE MPC5XXX_PSC1 +#elif CONFIG_PS2SERIAL == 2 +#define PSC_BASE MPC5XXX_PSC2 +#elif CONFIG_PS2SERIAL == 3 +#define PSC_BASE MPC5XXX_PSC3 +#elif defined(CONFIG_MGT5100) +#error CONFIG_PS2SERIAL must be in 1, 2 or 3 +#elif CONFIG_PS2SERIAL == 4 +#define PSC_BASE MPC5XXX_PSC4 +#elif CONFIG_PS2SERIAL == 5 +#define PSC_BASE MPC5XXX_PSC5 +#elif CONFIG_PS2SERIAL == 6 +#define PSC_BASE MPC5XXX_PSC6 +#else +#error CONFIG_PS2SERIAL must be in 1 ... 6 +#endif + +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + +#if CONFIG_PS2SERIAL == 1 +#define COM_BASE (CFG_CCSRBAR+0x4500) +#elif CONFIG_PS2SERIAL == 2 +#define COM_BASE (CFG_CCSRBAR+0x4600) +#else +#error CONFIG_PS2SERIAL must be in 1 ... 2 +#endif + +#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */ + +static int ps2ser_getc_hw(void); +static void ps2ser_interrupt(void *dev_id); + +extern struct serial_state rs_table[]; /* in serial.c */ +#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555) +static struct serial_state *state; +#endif + +static u_char ps2buf[PS2BUF_SIZE]; +static atomic_t ps2buf_cnt; +static int ps2buf_in_idx; +static int ps2buf_out_idx; + +#ifdef CONFIG_MPC5xxx +int ps2ser_init(void) +{ + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; + unsigned long baseclk; + int div; + + /* reset PSC */ + psc->command = PSC_SEL_MODE_REG_1; + + /* select clock sources */ +#if defined(CONFIG_MGT5100) + psc->psc_clock_select = 0xdd00; + baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32; +#elif defined(CONFIG_MPC5200) + psc->psc_clock_select = 0; + baseclk = (gd->ipb_clk + 16) / 32; +#endif + + /* switch to UART mode */ + psc->sicr = 0; + + /* configure parity, bit length and so on */ +#if defined(CONFIG_MGT5100) + psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE; +#elif defined(CONFIG_MPC5200) + psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; +#endif + psc->mode = PSC_MODE_ONE_STOP; + + /* set up UART divisor */ + div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD; + psc->ctur = (div >> 8) & 0xff; + psc->ctlr = div & 0xff; + + /* disable all interrupts */ + psc->psc_imr = 0; + + /* reset and enable Rx/Tx */ + psc->command = PSC_RST_RX; + psc->command = PSC_RST_TX; + psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; + + return (0); +} + +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +int ps2ser_init(void) +{ + NS16550_t com_port = (NS16550_t)COM_BASE; + + com_port->ier = 0x00; + com_port->lcr = LCR_BKSE | LCR_8N1; + com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff; + com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff; + com_port->lcr = LCR_8N1; + com_port->mcr = (MCR_DTR | MCR_RTS); + com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR); + + return (0); +} + +#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */ + +static inline unsigned int ps2ser_in(int offset) +{ + return readb((unsigned long) state->iomem_base + offset); +} + +static inline void ps2ser_out(int offset, int value) +{ + writeb(value, (unsigned long) state->iomem_base + offset); +} + +int ps2ser_init(void) +{ + int quot; + unsigned cval; + + state = rs_table + CONFIG_PS2SERIAL; + + quot = state->baud_base / PS2SER_BAUD; + cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */ + + /* Set speed, enable interrupts, enable FIFO + */ + ps2ser_out(UART_LCR, cval | UART_LCR_DLAB); + ps2ser_out(UART_DLL, quot & 0xff); + ps2ser_out(UART_DLM, quot >> 8); + ps2ser_out(UART_LCR, cval); + ps2ser_out(UART_IER, UART_IER_RDI); + ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS); + ps2ser_out(UART_FCR, + UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); + + /* If we read 0xff from the LSR, there is no UART here + */ + if (ps2ser_in(UART_LSR) == 0xff) { + printf ("ps2ser.c: no UART found\n"); + return -1; + } + + irq_install_handler(state->irq, ps2ser_interrupt, NULL); + + return 0; +} +#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */ + +void ps2ser_putc(int chr) +{ +#ifdef CONFIG_MPC5xxx + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + NS16550_t com_port = (NS16550_t)COM_BASE; +#endif +#ifdef DEBUG + printf(">>>> 0x%02x\n", chr); +#endif + +#ifdef CONFIG_MPC5xxx + while (!(psc->psc_status & PSC_SR_TXRDY)); + + psc->psc_buffer_8 = chr; +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + while ((com_port->lsr & LSR_THRE) == 0); + com_port->thr = chr; +#else + while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE)); + + ps2ser_out(UART_TX, chr); +#endif +} + +static int ps2ser_getc_hw(void) +{ +#ifdef CONFIG_MPC5xxx + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + NS16550_t com_port = (NS16550_t)COM_BASE; +#endif + int res = -1; + +#ifdef CONFIG_MPC5xxx + if (psc->psc_status & PSC_SR_RXRDY) { + res = (psc->psc_buffer_8); + } +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + if (com_port->lsr & LSR_DR) { + res = com_port->rbr; + } +#else + if (ps2ser_in(UART_LSR) & UART_LSR_DR) { + res = (ps2ser_in(UART_RX)); + } +#endif + + return res; +} + +int ps2ser_getc(void) +{ + volatile int chr; + int flags; + +#ifdef DEBUG + printf("<< "); +#endif + + flags = disable_interrupts(); + + do { + if (atomic_read(&ps2buf_cnt) != 0) { + chr = ps2buf[ps2buf_out_idx++]; + ps2buf_out_idx &= (PS2BUF_SIZE - 1); + atomic_dec(&ps2buf_cnt); + } else { + chr = ps2ser_getc_hw(); + } + } + while (chr < 0); + + if (flags) enable_interrupts(); + +#ifdef DEBUG + printf("0x%02x\n", chr); +#endif + + return chr; +} + +int ps2ser_check(void) +{ + int flags; + + flags = disable_interrupts(); + ps2ser_interrupt(NULL); + if (flags) enable_interrupts(); + + return atomic_read(&ps2buf_cnt); +} + +static void ps2ser_interrupt(void *dev_id) +{ +#ifdef CONFIG_MPC5xxx + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + NS16550_t com_port = (NS16550_t)COM_BASE; +#endif + int chr; + int status; + + do { + chr = ps2ser_getc_hw(); +#ifdef CONFIG_MPC5xxx + status = psc->psc_status; +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + status = com_port->lsr; +#else + status = ps2ser_in(UART_IIR); +#endif + if (chr < 0) continue; + + if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) { + ps2buf[ps2buf_in_idx++] = chr; + ps2buf_in_idx &= (PS2BUF_SIZE - 1); + atomic_inc(&ps2buf_cnt); + } else { + printf ("ps2ser.c: buffer overflow\n"); + } +#ifdef CONFIG_MPC5xxx + } while (status & PSC_SR_RXRDY); +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) + } while (status & LSR_DR); +#else + } while (status & UART_IIR_RDI); +#endif + + if (atomic_read(&ps2buf_cnt)) { + ps2mult_callback(atomic_read(&ps2buf_cnt)); + } +} + +#endif /* CONFIG_PS2SERIAL */ diff --git a/drivers/pxa_pcmcia.c b/drivers/pxa_pcmcia.c new file mode 100644 index 000000000..d9d38bbfc --- /dev/null +++ b/drivers/pxa_pcmcia.c @@ -0,0 +1,95 @@ +#include +#include + +#ifdef CONFIG_PXA_PCMCIA + +#include +#include +#include + +static inline void msWait(unsigned msVal) +{ + udelay(msVal*1000); +} + +int pcmcia_on (void) +{ + unsigned int reg_arr[] = { + 0x48000028, CFG_MCMEM0_VAL, + 0x4800002c, CFG_MCMEM1_VAL, + 0x48000030, CFG_MCATT0_VAL, + 0x48000034, CFG_MCATT1_VAL, + 0x48000038, CFG_MCIO0_VAL, + 0x4800003c, CFG_MCIO1_VAL, + + 0, 0 + }; + int i, rc; + +#ifdef CONFIG_EXADRON1 + int cardDetect; + volatile unsigned int *v_pBCRReg = + (volatile unsigned int *) 0x08000000; +#endif + + debug ("%s\n", __FUNCTION__); + + i = 0; + while (reg_arr[i]) + *((volatile unsigned int *) reg_arr[i++]) |= reg_arr[i++]; + udelay (1000); + + debug ("%s: programmed mem controller \n", __FUNCTION__); + +#ifdef CONFIG_EXADRON1 + +/*define useful BCR masks */ +#define BCR_CF_INIT_VAL 0x00007230 +#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231 +#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233 +#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213 +#define BCR_CF_PWRON_BUSON_RESETOFF_VAL 0x00007211 + + /* we see from the GPIO bit if the card is present */ + cardDetect = !(GPLR0 & GPIO_bit (14)); + + if (cardDetect) { + printf ("No PCMCIA card found!\n"); + } + + /* reset the card via the BCR line */ + *v_pBCRReg = (unsigned) BCR_CF_INIT_VAL; + msWait (500); + + *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL; + msWait (500); + + *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL; + msWait (500); + + *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL; + msWait (500); + + *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL; + msWait (1500); + + /* enable address bus */ + GPCR1 = 0x01; + /* and the first CF slot */ + MECR = 0x00000002; + +#endif /* EXADRON 1 */ + + rc = check_ide_device (0); /* use just slot 0 */ + + return rc; +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_off (void) +{ + return 0; +} +#endif + +#endif /* CONFIG_PXA_PCMCIA */ diff --git a/drivers/rpx_pcmcia.c b/drivers/rpx_pcmcia.c new file mode 100644 index 000000000..2a0a9e05a --- /dev/null +++ b/drivers/rpx_pcmcia.c @@ -0,0 +1,73 @@ +/* -------------------------------------------------------------------- */ +/* RPX Boards from Embedded Planet */ +/* -------------------------------------------------------------------- */ +#include +#ifdef CONFIG_8xx +#include +#endif +#include + +#undef CONFIG_PCMCIA + +#if CONFIG_COMMANDS & CFG_CMD_PCMCIA +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#if defined(CONFIG_PCMCIA) \ + && (defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)) + +#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ + u_long reg = 0; + + switch(vcc) { + case 0: break; + case 33: reg |= BCSR1_PCVCTL4; break; + case 50: reg |= BCSR1_PCVCTL5; break; + default: return 1; + } + + switch(vpp) { + case 0: break; + case 33: + case 50: + if(vcc == vpp) + reg |= BCSR1_PCVCTL6; + else + return 1; + break; + case 120: + reg |= BCSR1_PCVCTL7; + default: return 1; + } + + /* first, turn off all power */ + *((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 + | BCSR1_PCVCTL6 | BCSR1_PCVCTL7); + + /* enable new powersettings */ + *((uint *)RPX_CSR_ADDR) |= reg; + + return 0; +} + +int pcmcia_hardware_enable (int slot) +{ + return 0; /* No hardware to enable */ +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +static int pcmcia_hardware_disable(int slot) +{ + return 0; /* No hardware to disable */ +} +#endif /* CONFIG_COMMANDS & CFG_CMD_PCMCIA */ + + +#endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */ diff --git a/drivers/rtl8019.c b/drivers/rtl8019.c new file mode 100644 index 000000000..62b924551 --- /dev/null +++ b/drivers/rtl8019.c @@ -0,0 +1,282 @@ +/* + * Realtek 8019AS Ethernet + * (C) Copyright 2002-2003 + * Xue Ligong(lgxue@hotmail.com),Wang Kehao, ESLAB, whut.edu.cn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This code works in 8bit mode. + * If you need to work in 16bit mode, PLS change it! + */ + +#include +#include +#include "rtl8019.h" +#include + +#ifdef CONFIG_DRIVER_RTL8019 + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + + +/* packet page register access functions */ + + +static unsigned char get_reg (unsigned int regno) +{ + return (*(unsigned char *) regno); +} + + +static void put_reg (unsigned int regno, unsigned char val) +{ + *(volatile unsigned char *) regno = val; +} + +static void eth_reset (void) +{ + unsigned char ucTemp; + + /* reset NIC */ + ucTemp = get_reg (RTL8019_RESET); + put_reg (RTL8019_RESET, ucTemp); + put_reg (RTL8019_INTERRUPTSTATUS, 0xff); + udelay (2000); /* wait for 2ms */ +} + +void rtl8019_get_enetaddr (uchar * addr) +{ + unsigned char i; + unsigned char temp; + + eth_reset (); + + put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD); + put_reg (RTL8019_DATACONFIGURATION, 0x48); + put_reg (RTL8019_REMOTESTARTADDRESS0, 0x00); + put_reg (RTL8019_REMOTESTARTADDRESS1, 0x00); + put_reg (RTL8019_REMOTEBYTECOUNT0, 12); + put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD); + printf ("MAC: "); + for (i = 0; i < 6; i++) { + temp = get_reg (RTL8019_DMA_DATA); + *addr++ = temp; + temp = get_reg (RTL8019_DMA_DATA); + printf ("%x:", temp); + } + + while ((!get_reg (RTL8019_INTERRUPTSTATUS) & 0x40)); + printf ("\b \n"); + put_reg (RTL8019_REMOTEBYTECOUNT0, 0x00); + put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8019_COMMAND, RTL8019_PAGE0); +} + + +void eth_halt (void) +{ + put_reg (RTL8019_COMMAND, 0x01); +} + +int eth_init (bd_t * bd) +{ + eth_reset (); + put_reg (RTL8019_COMMAND, RTL8019_PAGE0STOP); + put_reg (RTL8019_DATACONFIGURATION, 0x48); + put_reg (RTL8019_REMOTEBYTECOUNT0, 0x00); + put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8019_RECEIVECONFIGURATION, 0x00); /*00; */ + put_reg (RTL8019_TRANSMITPAGE, RTL8019_TPSTART); + put_reg (RTL8019_TRANSMITCONFIGURATION, 0x02); + put_reg (RTL8019_PAGESTART, RTL8019_PSTART); + put_reg (RTL8019_BOUNDARY, RTL8019_PSTART); + put_reg (RTL8019_PAGESTOP, RTL8019_PSTOP); + put_reg (RTL8019_INTERRUPTSTATUS, 0xff); + put_reg (RTL8019_INTERRUPTMASK, 0x11); /*b; */ + put_reg (RTL8019_COMMAND, RTL8019_PAGE1STOP); + put_reg (RTL8019_PHYSICALADDRESS0, bd->bi_enetaddr[0]); + put_reg (RTL8019_PHYSICALADDRESS1, bd->bi_enetaddr[1]); + put_reg (RTL8019_PHYSICALADDRESS2, bd->bi_enetaddr[2]); + put_reg (RTL8019_PHYSICALADDRESS3, bd->bi_enetaddr[3]); + put_reg (RTL8019_PHYSICALADDRESS4, bd->bi_enetaddr[4]); + put_reg (RTL8019_PHYSICALADDRESS5, bd->bi_enetaddr[5]); + put_reg (RTL8019_MULTIADDRESS0, 0x00); + put_reg (RTL8019_MULTIADDRESS1, 0x00); + put_reg (RTL8019_MULTIADDRESS2, 0x00); + put_reg (RTL8019_MULTIADDRESS3, 0x00); + put_reg (RTL8019_MULTIADDRESS4, 0x00); + put_reg (RTL8019_MULTIADDRESS5, 0x00); + put_reg (RTL8019_MULTIADDRESS6, 0x00); + put_reg (RTL8019_MULTIADDRESS7, 0x00); + put_reg (RTL8019_CURRENT, RTL8019_PSTART); + put_reg (RTL8019_COMMAND, RTL8019_PAGE0); + put_reg (RTL8019_TRANSMITCONFIGURATION, 0xe0); /*58; */ + + return 0; +} + + +static unsigned char nic_to_pc (void) +{ + unsigned char rec_head_status; + unsigned char next_packet_pointer; + unsigned char packet_length0; + unsigned char packet_length1; + unsigned short rxlen = 0; + unsigned int i = 4; + unsigned char current_point; + unsigned char *addr; + + /* + * The RTL8019's first 4B is packet status,page of next packet + * and packet length(2B).So we receive the fist 4B. + */ + put_reg (RTL8019_REMOTESTARTADDRESS1, get_reg (RTL8019_BOUNDARY)); + put_reg (RTL8019_REMOTESTARTADDRESS0, 0x00); + put_reg (RTL8019_REMOTEBYTECOUNT1, 0x00); + put_reg (RTL8019_REMOTEBYTECOUNT0, 0x04); + + put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD); + + rec_head_status = get_reg (RTL8019_DMA_DATA); + next_packet_pointer = get_reg (RTL8019_DMA_DATA); + packet_length0 = get_reg (RTL8019_DMA_DATA); + packet_length1 = get_reg (RTL8019_DMA_DATA); + + put_reg (RTL8019_COMMAND, RTL8019_PAGE0); + /*Packet length is in two 8bit registers */ + rxlen = packet_length1; + rxlen = (((rxlen << 8) & 0xff00) + packet_length0); + rxlen -= 4; + + if (rxlen > PKTSIZE_ALIGN + PKTALIGN) + printf ("packet too big!\n"); + + /*Receive the packet */ + put_reg (RTL8019_REMOTESTARTADDRESS0, 0x04); + put_reg (RTL8019_REMOTESTARTADDRESS1, get_reg (RTL8019_BOUNDARY)); + + put_reg (RTL8019_REMOTEBYTECOUNT0, (rxlen & 0xff)); + put_reg (RTL8019_REMOTEBYTECOUNT1, ((rxlen >> 8) & 0xff)); + + + put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMARD); + + for (addr = (unsigned char *) NetRxPackets[0], i = rxlen; i > 0; i--) + *addr++ = get_reg (RTL8019_DMA_DATA); + /* Pass the packet up to the protocol layers. */ + NetReceive (NetRxPackets[0], rxlen); + + while (!(get_reg (RTL8019_INTERRUPTSTATUS)) & 0x40); /* wait for the op. */ + + /* + * To test whether the packets are all received,get the + * location of current point + */ + put_reg (RTL8019_COMMAND, RTL8019_PAGE1); + current_point = get_reg (RTL8019_CURRENT); + put_reg (RTL8019_COMMAND, RTL8019_PAGE0); + put_reg (RTL8019_BOUNDARY, next_packet_pointer); + return current_point; +} + +/* Get a data block via Ethernet */ +extern int eth_rx (void) +{ + unsigned char temp, current_point; + + put_reg (RTL8019_COMMAND, RTL8019_PAGE0); + + while (1) { + temp = get_reg (RTL8019_INTERRUPTSTATUS); + + if (temp & 0x90) { + /*overflow */ + put_reg (RTL8019_COMMAND, RTL8019_PAGE0STOP); + udelay (2000); + put_reg (RTL8019_REMOTEBYTECOUNT0, 0); + put_reg (RTL8019_REMOTEBYTECOUNT1, 0); + put_reg (RTL8019_TRANSMITCONFIGURATION, 2); + do { + current_point = nic_to_pc (); + } while (get_reg (RTL8019_BOUNDARY) != current_point); + + put_reg (RTL8019_TRANSMITCONFIGURATION, 0xe0); + } + + if (temp & 0x1) { + /*packet received */ + do { + put_reg (RTL8019_INTERRUPTSTATUS, 0x01); + current_point = nic_to_pc (); + } while (get_reg (RTL8019_BOUNDARY) != current_point); + } + + if (!(temp & 0x1)) + return 0; + /* done and exit. */ + } +} + +/* Send a data block via Ethernet. */ +extern int eth_send (volatile void *packet, int length) +{ + volatile unsigned char *p; + unsigned int pn; + + pn = length; + p = (volatile unsigned char *) packet; + + while (get_reg (RTL8019_COMMAND) == RTL8019_TRANSMIT); + + put_reg (RTL8019_REMOTESTARTADDRESS0, 0); + put_reg (RTL8019_REMOTESTARTADDRESS1, RTL8019_TPSTART); + put_reg (RTL8019_REMOTEBYTECOUNT0, (pn & 0xff)); + put_reg (RTL8019_REMOTEBYTECOUNT1, ((pn >> 8) & 0xff)); + + put_reg (RTL8019_COMMAND, RTL8019_REMOTEDMAWR); + while (pn > 0) { + put_reg (RTL8019_DMA_DATA, *p++); + pn--; + } + + pn = length; + + while (pn < 60) { /*Padding */ + put_reg (RTL8019_DMA_DATA, 0); + pn++; + } + + while (!(get_reg (RTL8019_INTERRUPTSTATUS)) & 0x40); + + put_reg (RTL8019_INTERRUPTSTATUS, 0x40); + put_reg (RTL8019_TRANSMITPAGE, RTL8019_TPSTART); + put_reg (RTL8019_TRANSMITBYTECOUNT0, (pn & 0xff)); + put_reg (RTL8019_TRANSMITBYTECOUNT1, ((pn >> 8 & 0xff))); + put_reg (RTL8019_COMMAND, RTL8019_TRANSMIT); + + return 0; +} + +#endif /* COMMANDS & CFG_NET */ + +#endif /* CONFIG_DRIVER_RTL8019 */ diff --git a/drivers/rtl8019.h b/drivers/rtl8019.h new file mode 100644 index 000000000..38116ad84 --- /dev/null +++ b/drivers/rtl8019.h @@ -0,0 +1,117 @@ +/* + * Realtek 8019AS Ethernet + * (C) Copyright 2002-2003 + * Xue Ligong(lgxue@hotmail.com),Wang Kehao, ESLAB, whut.edu.cn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This code works in 8bit mode. + * If you need to work in 16bit mode, PLS change it! + */ + +#include +#include + + +#ifdef CONFIG_DRIVER_RTL8019 + +#define RTL8019_REG_00 (RTL8019_BASE + 0x00) +#define RTL8019_REG_01 (RTL8019_BASE + 0x01) +#define RTL8019_REG_02 (RTL8019_BASE + 0x02) +#define RTL8019_REG_03 (RTL8019_BASE + 0x03) +#define RTL8019_REG_04 (RTL8019_BASE + 0x04) +#define RTL8019_REG_05 (RTL8019_BASE + 0x05) +#define RTL8019_REG_06 (RTL8019_BASE + 0x06) +#define RTL8019_REG_07 (RTL8019_BASE + 0x07) +#define RTL8019_REG_08 (RTL8019_BASE + 0x08) +#define RTL8019_REG_09 (RTL8019_BASE + 0x09) +#define RTL8019_REG_0a (RTL8019_BASE + 0x0a) +#define RTL8019_REG_0b (RTL8019_BASE + 0x0b) +#define RTL8019_REG_0c (RTL8019_BASE + 0x0c) +#define RTL8019_REG_0d (RTL8019_BASE + 0x0d) +#define RTL8019_REG_0e (RTL8019_BASE + 0x0e) +#define RTL8019_REG_0f (RTL8019_BASE + 0x0f) +#define RTL8019_REG_10 (RTL8019_BASE + 0x10) +#define RTL8019_REG_1f (RTL8019_BASE + 0x1f) + +#define RTL8019_COMMAND RTL8019_REG_00 +#define RTL8019_PAGESTART RTL8019_REG_01 +#define RTL8019_PAGESTOP RTL8019_REG_02 +#define RTL8019_BOUNDARY RTL8019_REG_03 +#define RTL8019_TRANSMITSTATUS RTL8019_REG_04 +#define RTL8019_TRANSMITPAGE RTL8019_REG_04 +#define RTL8019_TRANSMITBYTECOUNT0 RTL8019_REG_05 +#define RTL8019_NCR RTL8019_REG_05 +#define RTL8019_TRANSMITBYTECOUNT1 RTL8019_REG_06 +#define RTL8019_INTERRUPTSTATUS RTL8019_REG_07 +#define RTL8019_CURRENT RTL8019_REG_07 +#define RTL8019_REMOTESTARTADDRESS0 RTL8019_REG_08 +#define RTL8019_CRDMA0 RTL8019_REG_08 +#define RTL8019_REMOTESTARTADDRESS1 RTL8019_REG_09 +#define RTL8019_CRDMA1 RTL8019_REG_09 +#define RTL8019_REMOTEBYTECOUNT0 RTL8019_REG_0a +#define RTL8019_REMOTEBYTECOUNT1 RTL8019_REG_0b +#define RTL8019_RECEIVESTATUS RTL8019_REG_0c +#define RTL8019_RECEIVECONFIGURATION RTL8019_REG_0c +#define RTL8019_TRANSMITCONFIGURATION RTL8019_REG_0d +#define RTL8019_FAE_TALLY RTL8019_REG_0d +#define RTL8019_DATACONFIGURATION RTL8019_REG_0e +#define RTL8019_CRC_TALLY RTL8019_REG_0e +#define RTL8019_INTERRUPTMASK RTL8019_REG_0f +#define RTL8019_MISS_PKT_TALLY RTL8019_REG_0f +#define RTL8019_PHYSICALADDRESS0 RTL8019_REG_01 +#define RTL8019_PHYSICALADDRESS1 RTL8019_REG_02 +#define RTL8019_PHYSICALADDRESS2 RTL8019_REG_03 +#define RTL8019_PHYSICALADDRESS3 RTL8019_REG_04 +#define RTL8019_PHYSICALADDRESS4 RTL8019_REG_05 +#define RTL8019_PHYSICALADDRESS5 RTL8019_REG_06 +#define RTL8019_MULTIADDRESS0 RTL8019_REG_08 +#define RTL8019_MULTIADDRESS1 RTL8019_REG_09 +#define RTL8019_MULTIADDRESS2 RTL8019_REG_0a +#define RTL8019_MULTIADDRESS3 RTL8019_REG_0b +#define RTL8019_MULTIADDRESS4 RTL8019_REG_0c +#define RTL8019_MULTIADDRESS5 RTL8019_REG_0d +#define RTL8019_MULTIADDRESS6 RTL8019_REG_0e +#define RTL8019_MULTIADDRESS7 RTL8019_REG_0f +#define RTL8019_DMA_DATA RTL8019_REG_10 +#define RTL8019_RESET RTL8019_REG_1f + + +#define RTL8019_PAGE0 0x22 +#define RTL8019_PAGE1 0x62 +#define RTL8019_PAGE0DMAWRITE 0x12 +#define RTL8019_PAGE2DMAWRITE 0x92 +#define RTL8019_REMOTEDMAWR 0x12 +#define RTL8019_REMOTEDMARD 0x0A +#define RTL8019_ABORTDMAWR 0x32 +#define RTL8019_ABORTDMARD 0x2A +#define RTL8019_PAGE0STOP 0x21 +#define RTL8019_PAGE1STOP 0x61 +#define RTL8019_TRANSMIT 0x26 +#define RTL8019_TXINPROGRESS 0x04 +#define RTL8019_SEND 0x1A + +#define RTL8019_PSTART 0x4c +#define RTL8019_PSTOP 0x80 +#define RTL8019_TPSTART 0x40 + + +#endif /*end of CONFIG_DRIVER_RTL8019*/ diff --git a/drivers/rtl8139.c b/drivers/rtl8139.c new file mode 100644 index 000000000..a95f84e62 --- /dev/null +++ b/drivers/rtl8139.c @@ -0,0 +1,537 @@ +/* + * rtl8139.c : U-Boot driver for the RealTek RTL8139 + * + * Masami Komiya (mkomiya@sonare.it) + * + * Most part is taken from rtl8139.c of etherboot + * + */ + +/* rtl8139.c - etherboot driver for the Realtek 8139 chipset + + ported from the linux driver written by Donald Becker + by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 + + This software may be used and distributed according to the terms + of the GNU Public License, incorporated herein by reference. + + changes to the original driver: + - removed support for interrupts, switching to polling mode (yuck!) + - removed support for the 8129 chip (external MII) + +*/ + +/*********************************************************************/ +/* Revision History */ +/*********************************************************************/ + +/* + 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap) + Put in virt_to_bus calls to allow Etherboot relocation. + + 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) + Following email from Hyun-Joon Cha, added a disable routine, otherwise + NIC remains live and can crash the kernel later. + + 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) + Shuffled things around, removed the leftovers from the 8129 support + that was in the Linux driver and added a bit more 8139 definitions. + Moved the 8K receive buffer to a fixed, available address outside the + 0x98000-0x9ffff range. This is a bit of a hack, but currently the only + way to make room for the Etherboot features that need substantial amounts + of code like the ANSI console support. Currently the buffer is just below + 0x10000, so this even conforms to the tagged boot image specification, + which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My + interpretation of this "reserved" is that Etherboot may do whatever it + likes, as long as its environment is kept intact (like the BIOS + variables). Hopefully fixed rtl_poll() once and for all. The symptoms + were that if Etherboot was left at the boot menu for several minutes, the + first eth_poll failed. Seems like I am the only person who does this. + First of all I fixed the debugging code and then set out for a long bug + hunting session. It took me about a week full time work - poking around + various places in the driver, reading Don Becker's and Jeff Garzik's Linux + driver and even the FreeBSD driver (what a piece of crap!) - and + eventually spotted the nasty thing: the transmit routine was acknowledging + each and every interrupt pending, including the RxOverrun and RxFIFIOver + interrupts. This confused the RTL8139 thoroughly. It destroyed the + Rx ring contents by dumping the 2K FIFO contents right where we wanted to + get the next packet. Oh well, what fun. + + 18 Jan 2000 mdc@thinguin.org (Marty Connor) + Drastically simplified error handling. Basically, if any error + in transmission or reception occurs, the card is reset. + Also, pointed all transmit descriptors to the same buffer to + save buffer space. This should decrease driver size and avoid + corruption because of exceeding 32K during runtime. + + 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) + rtl_poll was quite broken: it used the RxOK interrupt flag instead + of the RxBufferEmpty flag which often resulted in very bad + transmission performace - below 1kBytes/s. + +*/ + +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_RTL8139) + +#define TICKS_PER_SEC CFG_HZ +#define TICKS_PER_MS (TICKS_PER_SEC/1000) + +#define RTL_TIMEOUT (1*TICKS_PER_SEC) + +#define ETH_FRAME_LEN 1514 +#define ETH_ALEN 6 +#define ETH_ZLEN 60 + +/* PCI Tuning Parameters + Threshold is bytes transferred to chip before transmission starts. */ +#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ +#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ +#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ +#define TX_DMA_BURST 4 /* Calculate as 16<priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +/* Symbolic offsets to registers. */ +enum RTL8139_registers { + MAC0=0, /* Ethernet hardware address. */ + MAR0=8, /* Multicast filter. */ + TxStatus0=0x10, /* Transmit status (four 32bit registers). */ + TxAddr0=0x20, /* Tx descriptors (also four 32bit). */ + RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36, + ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A, + IntrMask=0x3C, IntrStatus=0x3E, + TxConfig=0x40, RxConfig=0x44, + Timer=0x48, /* general-purpose counter. */ + RxMissed=0x4C, /* 24 bits valid, write clears. */ + Cfg9346=0x50, Config0=0x51, Config1=0x52, + TimerIntrReg=0x54, /* intr if gp counter reaches this value */ + MediaStatus=0x58, + Config3=0x59, + MultiIntr=0x5C, + RevisionID=0x5E, /* revision of the RTL8139 chip */ + TxSummary=0x60, + MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, + NWayExpansion=0x6A, + DisconnectCnt=0x6C, FalseCarrierCnt=0x6E, + NWayTestReg=0x70, + RxCnt=0x72, /* packet received counter */ + CSCR=0x74, /* chip status and configuration register */ + PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */ + /* from 0x84 onwards are a number of power management/wakeup frame + * definitions we will probably never need to know about. */ +}; + +enum ChipCmdBits { + CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, }; + +/* Interrupt register bits, using my own meaningful names. */ +enum IntrStatusBits { + PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000, + RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10, + TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01, +}; +enum TxStatusBits { + TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000, + TxOutOfWindow=0x20000000, TxAborted=0x40000000, + TxCarrierLost=0x80000000, +}; +enum RxStatusBits { + RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000, + RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004, + RxBadAlign=0x0002, RxStatusOK=0x0001, +}; + +enum MediaStatusBits { + MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08, + MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01, +}; + +enum MIIBMCRBits { + BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000, + BMCRRestartNWay=0x0200, BMCRDuplex=0x0100, +}; + +enum CSCRBits { + CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800, + CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0, + CSCR_LinkDownCmd=0x0f3c0, +}; + +/* Bits in RxConfig. */ +enum rx_mode_bits { + RxCfgWrap=0x80, + AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08, + AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01, +}; + +static int ioaddr; +static unsigned int cur_rx,cur_tx; + +/* The RTL8139 can only transmit from a contiguous, aligned memory block. */ +static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4))); +static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); + +static int rtl8139_probe(struct eth_device *dev, bd_t *bis); +static int read_eeprom(int location, int addr_len); +static void rtl_reset(struct eth_device *dev); +static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length); +static int rtl_poll(struct eth_device *dev); +static void rtl_disable(struct eth_device *dev); + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, + {} +}; + +int rtl8139_initialize(bd_t *bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase; + int idx=0; + + while(1){ + /* Find RTL8139 */ + if ((devno = pci_find_devices(supported, idx++)) < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= ~0xf; + + debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); + + dev = (struct eth_device *)malloc(sizeof *dev); + + sprintf (dev->name, "RTL8139#%d", card_number); + + dev->priv = (void *) devno; + dev->iobase = (int)bus_to_phys(iobase); + dev->init = rtl8139_probe; + dev->halt = rtl_disable; + dev->send = rtl_transmit; + dev->recv = rtl_poll; + + eth_register (dev); + + card_number++; + + pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); + + udelay (10 * 1000); + } + + return card_number; +} + +static int rtl8139_probe(struct eth_device *dev, bd_t *bis) +{ + int i; + int speed10, fullduplex; + int addr_len; + unsigned short *ap = (unsigned short *)dev->enetaddr; + + ioaddr = dev->iobase; + + /* Bring the chip out of low-power mode. */ + outb(0x00, ioaddr + Config1); + + addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6; + for (i = 0; i < 3; i++) + *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len)); + + speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10; + fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex; + + rtl_reset(dev); + + if (inb(ioaddr + MediaStatus) & MSRLinkFail) { + printf("Cable not connected or other link failure\n"); + return(0); + } + + return 1; +} + +/* Serial EEPROM section. */ + +/* EEPROM_Ctrl bits. */ +#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ +#define EE_CS 0x08 /* EEPROM chip select. */ +#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ +#define EE_WRITE_0 0x00 +#define EE_WRITE_1 0x02 +#define EE_DATA_READ 0x01 /* EEPROM chip data out. */ +#define EE_ENB (0x80 | EE_CS) + +/* + Delay between EEPROM clock transitions. + No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. +*/ + +#define eeprom_delay() inl(ee_addr) + +/* The EEPROM commands include the alway-set leading bit. */ +#define EE_WRITE_CMD (5) +#define EE_READ_CMD (6) +#define EE_ERASE_CMD (7) + +static int read_eeprom(int location, int addr_len) +{ + int i; + unsigned int retval = 0; + long ee_addr = ioaddr + Cfg9346; + int read_cmd = location | (EE_READ_CMD << addr_len); + + outb(EE_ENB & ~EE_CS, ee_addr); + outb(EE_ENB, ee_addr); + eeprom_delay(); + + /* Shift the read command bits out. */ + for (i = 4 + addr_len; i >= 0; i--) { + int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + outb(EE_ENB | dataval, ee_addr); + eeprom_delay(); + outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); + eeprom_delay(); + } + outb(EE_ENB, ee_addr); + eeprom_delay(); + + for (i = 16; i > 0; i--) { + outb(EE_ENB | EE_SHIFT_CLK, ee_addr); + eeprom_delay(); + retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0); + outb(EE_ENB, ee_addr); + eeprom_delay(); + } + + /* Terminate the EEPROM access. */ + outb(~EE_CS, ee_addr); + eeprom_delay(); + return retval; +} + +static const unsigned int rtl8139_rx_config = + (RX_BUF_LEN_IDX << 11) | + (RX_FIFO_THRESH << 13) | + (RX_DMA_BURST << 8); + +static void set_rx_mode(struct eth_device *dev) { + unsigned int mc_filter[2]; + int rx_mode; + /* !IFF_PROMISC */ + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + mc_filter[1] = mc_filter[0] = 0xffffffff; + + outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig); + + outl(mc_filter[0], ioaddr + MAR0 + 0); + outl(mc_filter[1], ioaddr + MAR0 + 4); +} + +static void rtl_reset(struct eth_device *dev) +{ + int i; + + outb(CmdReset, ioaddr + ChipCmd); + + cur_rx = 0; + cur_tx = 0; + + /* Give the chip 10ms to finish the reset. */ + for (i=0; i<100; ++i){ + if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; + udelay (100); /* wait 100us */ + } + + + for (i = 0; i < ETH_ALEN; i++) + outb(dev->enetaddr[i], ioaddr + MAC0 + i); + + /* Must enable Tx/Rx before setting transfer thresholds! */ + outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); + outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), + ioaddr + RxConfig); /* accept no frames yet! */ + outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig); + + /* The Linux driver changes Config1 here to use a different LED pattern + * for half duplex or full/autodetect duplex (for full/autodetect, the + * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses + * TX/RX, Link100, Link10). This is messy, because it doesn't match + * the inscription on the mounting bracket. It should not be changed + * from the configuration EEPROM default, because the card manufacturer + * should have set that to match the card. */ + +#ifdef DEBUG_RX + printf("rx ring address is %X\n",(unsigned long)rx_ring); +#endif + outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf); + + /* If we add multicast support, the MAR0 register would have to be + * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot + * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ + + outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); + + outl(rtl8139_rx_config, ioaddr + RxConfig); + + /* Start the chip's Tx and Rx process. */ + outl(0, ioaddr + RxMissed); + + /* set_rx_mode */ + set_rx_mode(dev); + + /* Disable all known interrupts by setting the interrupt mask. */ + outw(0, ioaddr + IntrMask); +} + +static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length) +{ + unsigned int status, to; + unsigned long txstatus; + unsigned int len = length; + + ioaddr = dev->iobase; + + memcpy((char *)tx_buffer, (char *)packet, (int)length); + +#ifdef DEBUG_TX + printf("sending %d bytes\n", len); +#endif + + /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 + * bytes are sent automatically for the FCS, totalling to 64 bytes). */ + while (len < ETH_ZLEN) { + tx_buffer[len++] = '\0'; + } + + outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4); + outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, + ioaddr + TxStatus0 + cur_tx*4); + + to = currticks() + RTL_TIMEOUT; + + do { + status = inw(ioaddr + IntrStatus); + /* Only acknlowledge interrupt sources we can properly handle + * here - the RxOverflow/RxFIFOOver MUST be handled in the + * rtl_poll() function. */ + outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus); + if ((status & (TxOK | TxErr | PCIErr)) != 0) break; + } while (currticks() < to); + + txstatus = inl(ioaddr + TxStatus0 + cur_tx*4); + + if (status & TxOK) { + cur_tx = (cur_tx + 1) % NUM_TX_DESC; +#ifdef DEBUG_TX + printf("tx done (%d ticks), status %hX txstatus %X\n", + to-currticks(), status, txstatus); +#endif + return length; + } else { +#ifdef DEBUG_TX + printf("tx timeout/error (%d ticks), status %hX txstatus %X\n", + currticks()-to, status, txstatus); +#endif + rtl_reset(dev); + + return 0; + } +} + +static int rtl_poll(struct eth_device *dev) +{ + unsigned int status; + unsigned int ring_offs; + unsigned int rx_size, rx_status; + int length=0; + + ioaddr = dev->iobase; + + if (inb(ioaddr + ChipCmd) & RxBufEmpty) { + return 0; + } + + status = inw(ioaddr + IntrStatus); + /* See below for the rest of the interrupt acknowledges. */ + outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); + +#ifdef DEBUG_RX + printf("rtl_poll: int %hX ", status); +#endif + + ring_offs = cur_rx % RX_BUF_LEN; + rx_status = *(unsigned int*)KSEG1ADDR((rx_ring + ring_offs)); + rx_size = rx_status >> 16; + rx_status &= 0xffff; + + if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) || + (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { + printf("rx error %hX\n", rx_status); + rtl_reset(dev); /* this clears all interrupts still pending */ + return 0; + } + + /* Received a good packet */ + length = rx_size - 4; /* no one cares about the FCS */ + if (ring_offs+4+rx_size-4 > RX_BUF_LEN) { + int semi_count = RX_BUF_LEN - ring_offs - 4; + unsigned char rxdata[RX_BUF_LEN]; + + memcpy(rxdata, rx_ring + ring_offs + 4, semi_count); + memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count); + + NetReceive(rxdata, length); +#ifdef DEBUG_RX + printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count); +#endif + } else { + NetReceive(rx_ring + ring_offs + 4, length); +#ifdef DEBUG_RX + printf("rx packet %d bytes", rx_size-4); +#endif + } + + cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; + outw(cur_rx - 16, ioaddr + RxBufPtr); + /* See RTL8139 Programming Guide V0.1 for the official handling of + * Rx overflow situations. The document itself contains basically no + * usable information, except for a few exception handling rules. */ + outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); + return length; +} + +static void rtl_disable(struct eth_device *dev) +{ + int i; + + ioaddr = dev->iobase; + + /* reset the chip */ + outb(CmdReset, ioaddr + ChipCmd); + + /* Give the chip 10ms to finish the reset. */ + for (i=0; i<100; ++i){ + if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; + udelay (100); /* wait 100us */ + } +} +#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_RTL8139 */ diff --git a/drivers/rtl8169.c b/drivers/rtl8169.c new file mode 100644 index 000000000..3393ba890 --- /dev/null +++ b/drivers/rtl8169.c @@ -0,0 +1,888 @@ +/* + * rtl8169.c : U-Boot driver for the RealTek RTL8169 + * + * Masami Komiya (mkomiya@sonare.it) + * + * Most part is taken from r8169.c of etherboot + * + */ + +/************************************************************************** +* r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit +* Written 2003 by Timothy Legge +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +* +* Portions of this code based on: +* r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver +* for Linux kernel 2.4.x. +* +* Written 2002 ShuChen +* See Linux Driver for full information +* +* Linux Driver Version 1.27a, 10.02.2002 +* +* Thanks to: +* Jean Chen of RealTek Semiconductor Corp. for +* providing the evaluation NIC used to develop +* this driver. RealTek's support for Etherboot +* is appreciated. +* +* REVISION HISTORY: +* ================ +* +* v1.0 11-26-2003 timlegge Initial port of Linux driver +* v1.5 01-17-2004 timlegge Initial driver output cleanup +* +* Indent Options: indent -kr -i8 +***************************************************************************/ + +#include +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_RTL8169) + +#undef DEBUG_RTL8169 +#undef DEBUG_RTL8169_TX +#undef DEBUG_RTL8169_RX + +#define drv_version "v1.5" +#define drv_date "01-17-2004" + +static u32 ioaddr; + +/* Condensed operations for readability. */ +#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) +#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) + +#define currticks() get_timer(0) +#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) +#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) + +/* media options */ +#define MAX_UNITS 8 +static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; + +/* MAC address length*/ +#define MAC_ADDR_LEN 6 + +/* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ +#define MAX_ETH_FRAME_SIZE 1536 + +#define TX_FIFO_THRESH 256 /* In bytes */ + +#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ +#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ +#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ +#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ +#define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ +#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ + +#define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ +#define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ +#define RX_BUF_SIZE 1536 /* Rx Buffer size */ +#define RX_BUF_LEN 8192 + +#define RTL_MIN_IO_SIZE 0x80 +#define TX_TIMEOUT (6*HZ) + +/* write/read MMIO register */ +#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) +#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) +#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) +#define RTL_R8(reg) readb (ioaddr + (reg)) +#define RTL_R16(reg) readw (ioaddr + (reg)) +#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) + +#define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE +#define ETH_ALEN MAC_ADDR_LEN +#define ETH_ZLEN 60 + +enum RTL8169_registers { + MAC0 = 0, /* Ethernet hardware address. */ + MAR0 = 8, /* Multicast filter. */ + TxDescStartAddr = 0x20, + TxHDescStartAddr = 0x28, + FLASH = 0x30, + ERSR = 0x36, + ChipCmd = 0x37, + TxPoll = 0x38, + IntrMask = 0x3C, + IntrStatus = 0x3E, + TxConfig = 0x40, + RxConfig = 0x44, + RxMissed = 0x4C, + Cfg9346 = 0x50, + Config0 = 0x51, + Config1 = 0x52, + Config2 = 0x53, + Config3 = 0x54, + Config4 = 0x55, + Config5 = 0x56, + MultiIntr = 0x5C, + PHYAR = 0x60, + TBICSR = 0x64, + TBI_ANAR = 0x68, + TBI_LPAR = 0x6A, + PHYstatus = 0x6C, + RxMaxSize = 0xDA, + CPlusCmd = 0xE0, + RxDescStartAddr = 0xE4, + EarlyTxThres = 0xEC, + FuncEvent = 0xF0, + FuncEventMask = 0xF4, + FuncPresetState = 0xF8, + FuncForceEvent = 0xFC, +}; + +enum RTL8169_register_content { + /*InterruptStatusBits */ + SYSErr = 0x8000, + PCSTimeout = 0x4000, + SWInt = 0x0100, + TxDescUnavail = 0x80, + RxFIFOOver = 0x40, + RxUnderrun = 0x20, + RxOverflow = 0x10, + TxErr = 0x08, + TxOK = 0x04, + RxErr = 0x02, + RxOK = 0x01, + + /*RxStatusDesc */ + RxRES = 0x00200000, + RxCRC = 0x00080000, + RxRUNT = 0x00100000, + RxRWT = 0x00400000, + + /*ChipCmdBits */ + CmdReset = 0x10, + CmdRxEnb = 0x08, + CmdTxEnb = 0x04, + RxBufEmpty = 0x01, + + /*Cfg9346Bits */ + Cfg9346_Lock = 0x00, + Cfg9346_Unlock = 0xC0, + + /*rx_mode_bits */ + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0x08, + AcceptMulticast = 0x04, + AcceptMyPhys = 0x02, + AcceptAllPhys = 0x01, + + /*RxConfigBits */ + RxCfgFIFOShift = 13, + RxCfgDMAShift = 8, + + /*TxConfigBits */ + TxInterFrameGapShift = 24, + TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ + + /*rtl8169_PHYstatus */ + TBI_Enable = 0x80, + TxFlowCtrl = 0x40, + RxFlowCtrl = 0x20, + _1000bpsF = 0x10, + _100bps = 0x08, + _10bps = 0x04, + LinkStatus = 0x02, + FullDup = 0x01, + + /*GIGABIT_PHY_registers */ + PHY_CTRL_REG = 0, + PHY_STAT_REG = 1, + PHY_AUTO_NEGO_REG = 4, + PHY_1000_CTRL_REG = 9, + + /*GIGABIT_PHY_REG_BIT */ + PHY_Restart_Auto_Nego = 0x0200, + PHY_Enable_Auto_Nego = 0x1000, + + /* PHY_STAT_REG = 1; */ + PHY_Auto_Neco_Comp = 0x0020, + + /* PHY_AUTO_NEGO_REG = 4; */ + PHY_Cap_10_Half = 0x0020, + PHY_Cap_10_Full = 0x0040, + PHY_Cap_100_Half = 0x0080, + PHY_Cap_100_Full = 0x0100, + + /* PHY_1000_CTRL_REG = 9; */ + PHY_Cap_1000_Full = 0x0200, + + PHY_Cap_Null = 0x0, + + /*_MediaType*/ + _10_Half = 0x01, + _10_Full = 0x02, + _100_Half = 0x04, + _100_Full = 0x08, + _1000_Full = 0x10, + + /*_TBICSRBit*/ + TBILinkOK = 0x02000000, +}; + +static struct { + const char *name; + u8 version; /* depend on RTL8169 docs */ + u32 RxConfigMask; /* should clear the bits supported by this chip */ +} rtl_chip_info[] = { + {"RTL-8169", 0x00, 0xff7e1880,}, + {"RTL-8169", 0x04, 0xff7e1880,}, +}; + +enum _DescStatusBit { + OWNbit = 0x80000000, + EORbit = 0x40000000, + FSbit = 0x20000000, + LSbit = 0x10000000, +}; + +struct TxDesc { + u32 status; + u32 vlan_tag; + u32 buf_addr; + u32 buf_Haddr; +}; + +struct RxDesc { + u32 status; + u32 vlan_tag; + u32 buf_addr; + u32 buf_Haddr; +}; + +/* Define the TX Descriptor */ +static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; +/* __attribute__ ((aligned(256))); */ + +/* Create a static buffer of size RX_BUF_SZ for each +TX Descriptor. All descriptors point to a +part of this buffer */ +static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; + +/* Define the RX Descriptor */ +static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; + /* __attribute__ ((aligned(256))); */ + +/* Create a static buffer of size RX_BUF_SZ for each +RX Descriptor All descriptors point to a +part of this buffer */ +static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; + +struct rtl8169_private { + void *mmio_addr; /* memory map physical address */ + int chipset; + unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ + unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ + unsigned long dirty_tx; + unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ + unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ + struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ + struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ + unsigned char *RxBufferRings; /* Index of Rx Buffer */ + unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ + unsigned char *Tx_skbuff[NUM_TX_DESC]; +} tpx; + +static struct rtl8169_private *tpc; + +static const u16 rtl8169_intr_mask = + SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | + TxOK | RxErr | RxOK; +static const unsigned int rtl8169_rx_config = + (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_REALTEK, 0x8169}, + {} +}; + +void mdio_write(int RegAddr, int value) +{ + int i; + + RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); + udelay(1000); + + for (i = 2000; i > 0; i--) { + /* Check if the RTL8169 has completed writing to the specified MII register */ + if (!(RTL_R32(PHYAR) & 0x80000000)) { + break; + } else { + udelay(100); + } + } +} + +int mdio_read(int RegAddr) +{ + int i, value = -1; + + RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); + udelay(1000); + + for (i = 2000; i > 0; i--) { + /* Check if the RTL8169 has completed retrieving data from the specified MII register */ + if (RTL_R32(PHYAR) & 0x80000000) { + value = (int) (RTL_R32(PHYAR) & 0xFFFF); + break; + } else { + udelay(100); + } + } + return value; +} + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +static int rtl8169_init_board(struct eth_device *dev) +{ + int i; + u32 tmp; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + ioaddr = dev->iobase; + + /* Soft reset the chip. */ + RTL_W8(ChipCmd, CmdReset); + + /* Check that the chip has finished the reset. */ + for (i = 1000; i > 0; i--) + if ((RTL_R8(ChipCmd) & CmdReset) == 0) + break; + else + udelay(10); + + /* identify chip attached to board */ + tmp = RTL_R32(TxConfig); + tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; + + for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ + if (tmp == rtl_chip_info[i].version) { + tpc->chipset = i; + goto match; + } + } + + /* if unknown chip, assume array element #0, original RTL-8169 in this case */ + printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); + printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig)); + tpc->chipset = 0; + +match: + return 0; +} + +/************************************************************************** +RECV - Receive a frame +***************************************************************************/ +static int rtl_recv(struct eth_device *dev) +{ + /* return true if there's an ethernet packet ready to read */ + /* nic->packet should contain data on return */ + /* nic->packetlen should contain length of data */ + int cur_rx; + int length = 0; + +#ifdef DEBUG_RTL8169_RX + printf ("%s\n", __FUNCTION__); +#endif + ioaddr = dev->iobase; + + cur_rx = tpc->cur_rx; + if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) { + if (!(tpc->RxDescArray[cur_rx].status & RxRES)) { + unsigned char rxdata[RX_BUF_LEN]; + length = (int) (tpc->RxDescArray[cur_rx]. + status & 0x00001FFF) - 4; + + memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); + NetReceive(rxdata, length); + + if (cur_rx == NUM_RX_DESC - 1) + tpc->RxDescArray[cur_rx].status = + (OWNbit | EORbit) + RX_BUF_SIZE; + else + tpc->RxDescArray[cur_rx].status = + OWNbit + RX_BUF_SIZE; + tpc->RxDescArray[cur_rx].buf_addr = + virt_to_bus(tpc->RxBufferRing[cur_rx]); + } else { + puts("Error Rx"); + } + cur_rx = (cur_rx + 1) % NUM_RX_DESC; + tpc->cur_rx = cur_rx; + return 1; + + } + tpc->cur_rx = cur_rx; + return (0); /* initially as this is called to flush the input */ +} + +#define HZ 1000 +/************************************************************************** +SEND - Transmit a frame +***************************************************************************/ +static int rtl_send(struct eth_device *dev, volatile void *packet, int length) +{ + /* send the packet to destination */ + + u32 to; + u8 *ptxb; + int entry = tpc->cur_tx % NUM_TX_DESC; + u32 len = length; + +#ifdef DEBUG_RTL8169_TX + int stime = currticks(); + printf ("%s\n", __FUNCTION__); + printf("sending %d bytes\n", len); +#endif + + ioaddr = dev->iobase; + + /* point to the current txb incase multiple tx_rings are used */ + ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; + memcpy(ptxb, (char *)packet, (int)length); + + while (len < ETH_ZLEN) + ptxb[len++] = '\0'; + + tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb); + if (entry != (NUM_TX_DESC - 1)) { + tpc->TxDescArray[entry].status = + (OWNbit | FSbit | LSbit) | ((len > ETH_ZLEN) ? + len : ETH_ZLEN); + } else { + tpc->TxDescArray[entry].status = + (OWNbit | EORbit | FSbit | LSbit) | + ((len > ETH_ZLEN) ? length : ETH_ZLEN); + } + RTL_W8(TxPoll, 0x40); /* set polling bit */ + + tpc->cur_tx++; + to = currticks() + TX_TIMEOUT; + while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */ + + if (currticks() >= to) { +#ifdef DEBUG_RTL8169_TX + puts ("tx timeout/error\n"); + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); +#endif + return 0; + } else { +#ifdef DEBUG_RTL8169_TX + puts("tx done\n"); +#endif + return length; + } +} + +static void rtl8169_set_rx_mode(struct eth_device *dev) +{ + u32 mc_filter[2]; /* Multicast hash filter */ + int rx_mode; + u32 tmp = 0; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + + /* IFF_ALLMULTI */ + /* Too many to filter perfectly -- accept all multicasts. */ + rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; + mc_filter[1] = mc_filter[0] = 0xffffffff; + + tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & + rtl_chip_info[tpc->chipset].RxConfigMask); + + RTL_W32(RxConfig, tmp); + RTL_W32(MAR0 + 0, mc_filter[0]); + RTL_W32(MAR0 + 4, mc_filter[1]); +} + +static void rtl8169_hw_start(struct eth_device *dev) +{ + u32 i; + +#ifdef DEBUG_RTL8169 + int stime = currticks(); + printf ("%s\n", __FUNCTION__); +#endif + +#if 0 + /* Soft reset the chip. */ + RTL_W8(ChipCmd, CmdReset); + + /* Check that the chip has finished the reset. */ + for (i = 1000; i > 0; i--) { + if ((RTL_R8(ChipCmd) & CmdReset) == 0) + break; + else + udelay(10); + } +#endif + + RTL_W8(Cfg9346, Cfg9346_Unlock); + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + RTL_W8(EarlyTxThres, EarlyTxThld); + + /* For gigabit rtl8169 */ + RTL_W16(RxMaxSize, RxPacketMaxSize); + + /* Set Rx Config register */ + i = rtl8169_rx_config | (RTL_R32(RxConfig) & + rtl_chip_info[tpc->chipset].RxConfigMask); + RTL_W32(RxConfig, i); + + /* Set DMA burst size and Interframe Gap Time */ + RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | + (InterFrameGap << TxInterFrameGapShift)); + + + tpc->cur_rx = 0; + + RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray)); + RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray)); + RTL_W8(Cfg9346, Cfg9346_Lock); + udelay(10); + + RTL_W32(RxMissed, 0); + + rtl8169_set_rx_mode(dev); + + /* no early-rx interrupts */ + RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); + +#ifdef DEBUG_RTL8169 + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); +#endif +} + +static void rtl8169_init_ring(struct eth_device *dev) +{ + int i; + +#ifdef DEBUG_RTL8169 + int stime = currticks(); + printf ("%s\n", __FUNCTION__); +#endif + + tpc->cur_rx = 0; + tpc->cur_tx = 0; + tpc->dirty_tx = 0; + memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); + memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); + + for (i = 0; i < NUM_TX_DESC; i++) { + tpc->Tx_skbuff[i] = &txb[i]; + } + + for (i = 0; i < NUM_RX_DESC; i++) { + if (i == (NUM_RX_DESC - 1)) + tpc->RxDescArray[i].status = + (OWNbit | EORbit) + RX_BUF_SIZE; + else + tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE; + + tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; + tpc->RxDescArray[i].buf_addr = + virt_to_bus(tpc->RxBufferRing[i]); + } + +#ifdef DEBUG_RTL8169 + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); +#endif +} + +/************************************************************************** +RESET - Finish setting up the ethernet interface +***************************************************************************/ +static void rtl_reset(struct eth_device *dev, bd_t *bis) +{ + int i; + u8 diff; + u32 TxPhyAddr, RxPhyAddr; + +#ifdef DEBUG_RTL8169 + int stime = currticks(); + printf ("%s\n", __FUNCTION__); +#endif + + tpc->TxDescArrays = tx_ring; + if (tpc->TxDescArrays == 0) + puts("Allot Error"); + /* Tx Desscriptor needs 256 bytes alignment; */ + TxPhyAddr = virt_to_bus(tpc->TxDescArrays); + diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8)); + TxPhyAddr += diff; + tpc->TxDescArray = (struct TxDesc *) (tpc->TxDescArrays + diff); + + tpc->RxDescArrays = rx_ring; + /* Rx Desscriptor needs 256 bytes alignment; */ + RxPhyAddr = virt_to_bus(tpc->RxDescArrays); + diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8)); + RxPhyAddr += diff; + tpc->RxDescArray = (struct RxDesc *) (tpc->RxDescArrays + diff); + + if (tpc->TxDescArrays == NULL || tpc->RxDescArrays == NULL) { + puts("Allocate RxDescArray or TxDescArray failed\n"); + return; + } + + rtl8169_init_ring(dev); + rtl8169_hw_start(dev); + /* Construct a perfect filter frame with the mac address as first match + * and broadcast for all others */ + for (i = 0; i < 192; i++) + txb[i] = 0xFF; + + txb[0] = dev->enetaddr[0]; + txb[1] = dev->enetaddr[1]; + txb[2] = dev->enetaddr[2]; + txb[3] = dev->enetaddr[3]; + txb[4] = dev->enetaddr[4]; + txb[5] = dev->enetaddr[5]; + +#ifdef DEBUG_RTL8169 + printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); +#endif +} + +/************************************************************************** +HALT - Turn off ethernet interface +***************************************************************************/ +static void rtl_halt(struct eth_device *dev) +{ + int i; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + + ioaddr = dev->iobase; + + /* Stop the chip's Tx and Rx DMA processes. */ + RTL_W8(ChipCmd, 0x00); + + /* Disable interrupts by clearing the interrupt mask. */ + RTL_W16(IntrMask, 0x0000); + + RTL_W32(RxMissed, 0); + + tpc->TxDescArrays = NULL; + tpc->RxDescArrays = NULL; + tpc->TxDescArray = NULL; + tpc->RxDescArray = NULL; + for (i = 0; i < NUM_RX_DESC; i++) { + tpc->RxBufferRing[i] = NULL; + } +} + +/************************************************************************** +INIT - Look for an adapter, this routine's visible to the outside +***************************************************************************/ + +#define board_found 1 +#define valid_link 0 +static int rtl_init(struct eth_device *dev, bd_t *bis) +{ + static int board_idx = -1; + static int printed_version = 0; + int i, rc; + int option = -1, Cap10_100 = 0, Cap1000 = 0; + +#ifdef DEBUG_RTL8169 + printf ("%s\n", __FUNCTION__); +#endif + + ioaddr = dev->iobase; + + board_idx++; + + printed_version = 1; + + /* point to private storage */ + tpc = &tpx; + + rc = rtl8169_init_board(dev); + if (rc) + return rc; + + /* Get MAC address. FIXME: read EEPROM */ + for (i = 0; i < MAC_ADDR_LEN; i++) + dev->enetaddr[i] = RTL_R8(MAC0 + i); + +#ifdef DEBUG_RTL8169 + printf("MAC Address"); + for (i = 0; i < MAC_ADDR_LEN; i++) + printf(":%02x", dev->enetaddr[i]); + putc('\n'); +#endif + +#ifdef DEBUG_RTL8169 + /* Print out some hardware info */ + printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); +#endif + + /* if TBI is not endbled */ + if (!(RTL_R8(PHYstatus) & TBI_Enable)) { + int val = mdio_read(PHY_AUTO_NEGO_REG); + + option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; + /* Force RTL8169 in 10/100/1000 Full/Half mode. */ + if (option > 0) { +#ifdef DEBUG_RTL8169 + printf("%s: Force-mode Enabled.\n", dev->name); +#endif + Cap10_100 = 0, Cap1000 = 0; + switch (option) { + case _10_Half: + Cap10_100 = PHY_Cap_10_Half; + Cap1000 = PHY_Cap_Null; + break; + case _10_Full: + Cap10_100 = PHY_Cap_10_Full; + Cap1000 = PHY_Cap_Null; + break; + case _100_Half: + Cap10_100 = PHY_Cap_100_Half; + Cap1000 = PHY_Cap_Null; + break; + case _100_Full: + Cap10_100 = PHY_Cap_100_Full; + Cap1000 = PHY_Cap_Null; + break; + case _1000_Full: + Cap10_100 = PHY_Cap_Null; + Cap1000 = PHY_Cap_1000_Full; + break; + default: + break; + } + mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ + mdio_write(PHY_1000_CTRL_REG, Cap1000); + } else { +#ifdef DEBUG_RTL8169 + printf("%s: Auto-negotiation Enabled.\n", + dev->name); +#endif + /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ + mdio_write(PHY_AUTO_NEGO_REG, + PHY_Cap_10_Half | PHY_Cap_10_Full | + PHY_Cap_100_Half | PHY_Cap_100_Full | + (val & 0x1F)); + + /* enable 1000 Full Mode */ + mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); + + } + + /* Enable auto-negotiation and restart auto-nigotiation */ + mdio_write(PHY_CTRL_REG, + PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); + udelay(100); + + /* wait for auto-negotiation process */ + for (i = 10000; i > 0; i--) { + /* check if auto-negotiation complete */ + if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) { + udelay(100); + option = RTL_R8(PHYstatus); + if (option & _1000bpsF) { +#ifdef DEBUG_RTL8169 + printf("%s: 1000Mbps Full-duplex operation.\n", + dev->name); +#endif + } else { +#ifdef DEBUG_RTL8169 + printf + ("%s: %sMbps %s-duplex operation.\n", + dev->name, + (option & _100bps) ? "100" : + "10", + (option & FullDup) ? "Full" : + "Half"); +#endif + } + break; + } else { + udelay(100); + } + } /* end for-loop to wait for auto-negotiation process */ + + } else { + udelay(100); +#ifdef DEBUG_RTL8169 + printf + ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", + dev->name, + (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); +#endif + } + + return 1; +} + +int rtl8169_initialize(bd_t *bis) +{ + pci_dev_t devno; + int card_number = 0; + struct eth_device *dev; + u32 iobase; + int idx=0; + + while(1){ + /* Find RTL8169 */ + if ((devno = pci_find_devices(supported, idx++)) < 0) + break; + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + iobase &= ~0xf; + + debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); + + dev = (struct eth_device *)malloc(sizeof *dev); + + sprintf (dev->name, "RTL8169#%d", card_number); + + dev->priv = (void *) devno; + dev->iobase = (int)bus_to_phys(iobase); + + dev->init = rtl_reset; + dev->halt = rtl_halt; + dev->send = rtl_send; + dev->recv = rtl_recv; + + eth_register (dev); + + rtl_init(dev, bis); + + card_number++; + } + return card_number; +} + +#endif diff --git a/drivers/s3c4510b_eth.c b/drivers/s3c4510b_eth.c new file mode 100644 index 000000000..48901aa12 --- /dev/null +++ b/drivers/s3c4510b_eth.c @@ -0,0 +1,246 @@ +/*********************************************************************** + * + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: Ethernet interface for Samsung S3C4510B SoC + */ + +#include + +#ifdef CONFIG_DRIVER_S3C4510_ETH + +#include +#include +#include +#include "s3c4510b_eth.h" + +static TX_FrameDescriptor txFDbase[ETH_MaxTxFrames]; +static MACFrame txFrameBase[ETH_MaxTxFrames]; +static RX_FrameDescriptor rxFDbase[PKTBUFSRX]; +static ETH m_eth; + +static s32 TxFDinit( ETH *eth) { + + s32 i; + MACFrame *txFrmBase; + + /* disable cache for access to the TX buffers */ + txFrmBase = (MACFrame *)( (u32)txFrameBase | CACHE_DISABLE_MASK); + + /* store start of Tx descriptors and set current */ + eth->m_curTX_FD = (TX_FrameDescriptor *) ((u32)txFDbase | CACHE_DISABLE_MASK); + eth->m_baseTX_FD = eth->m_curTX_FD; + + for ( i = 0; i < ETH_MaxTxFrames; i++) { + eth->m_baseTX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)&txFrmBase[i]; + eth->m_baseTX_FD[i].m_frameDataPtr.bf.owner = 0x0; /* CPU owner */ + eth->m_baseTX_FD[i].m_opt.ui = 0x0; + eth->m_baseTX_FD[i].m_status.ui = 0x0; + eth->m_baseTX_FD[i].m_nextFD = ð->m_baseTX_FD[i+1]; + } + + /* make the list circular */ + eth->m_baseTX_FD[i-1].m_nextFD = ð->m_baseTX_FD[0]; + + PUT_REG( REG_BDMATXPTR, (u32)eth->m_curTX_FD); + + return 0; +} + +static s32 RxFDinit( ETH *eth) { + + s32 i; + /* MACFrame *rxFrmBase; */ + + /* disable cache for access to the RX buffers */ + /* rxFrmBase = (MACFrame *)( (u32)rxFrameBase | CACHE_DISABLE_MASK); */ + + /* store start of Rx descriptors and set current */ + eth->m_curRX_FD = (RX_FrameDescriptor *)((u32)rxFDbase | CACHE_DISABLE_MASK); + eth->m_baseRX_FD = eth->m_curRX_FD; + for ( i = 0; i < PKTBUFSRX; i++) { + eth->m_baseRX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)NetRxPackets[i] | CACHE_DISABLE_MASK; + eth->m_baseRX_FD[i].m_frameDataPtr.bf.owner = 0x1; /* BDMA owner */ + eth->m_baseRX_FD[i].m_reserved = 0x0; + eth->m_baseRX_FD[i].m_status.ui = 0x0; + eth->m_baseRX_FD[i].m_nextFD = ð->m_baseRX_FD[i+1]; + } + + /* make the list circular */ + eth->m_baseRX_FD[i-1].m_nextFD = ð->m_baseRX_FD[0]; + + PUT_REG( REG_BDMARXPTR, (u32)eth->m_curRX_FD); + + return 0; +} + +/* + * Public u-boot interface functions below + */ + +int eth_init(bd_t *bis) +{ + + ETH *eth = &m_eth; + + /* store our MAC address */ + eth->m_mac = bis->bi_enetaddr; + + /* setup DBMA and MAC */ + PUT_REG( REG_BDMARXCON, ETH_BRxRS); /* reset BDMA RX machine */ + PUT_REG( REG_BDMATXCON, ETH_BTxRS); /* reset BDMA TX machine */ + PUT_REG( REG_MACCON , ETH_SwReset); /* reset MAC machine */ + PUT_REG( REG_BDMARXLSZ, sizeof(MACFrame)); + PUT_REG( REG_MACCON , 0); /* reset MAC machine */ + + /* init frame descriptors */ + TxFDinit( eth); + RxFDinit( eth); + + /* init the CAM with our MAC address */ + PUT_REG( REG_CAM_BASE, (eth->m_mac[0] << 24) | + (eth->m_mac[1] << 16) | + (eth->m_mac[2] << 8) | + (eth->m_mac[3])); + PUT_REG( REG_CAM_BASE + 0x4, (eth->m_mac[4] << 24) | + (eth->m_mac[5] << 16)); + + /* enable CAM address 1 -- the MAC we just loaded */ + PUT_REG( REG_CAMEN, 0x1); + + PUT_REG( REG_CAMCON, + ETH_BroadAcc | /* accept broadcast packetes */ + ETH_CompEn); /* enable compare mode (check against the CAM) */ + + /* configure the BDMA Transmitter control */ + PUT_REG( REG_BDMATXCON, + ETH_BTxBRST | /* BDMA Tx burst size 16 words */ + ETH_BTxMSL110 | /* BDMA Tx wait to fill 6/8 of the BDMA */ + ETH_BTxSTSKO | /* BDMA Tx interrupt(Stop) on non-owner TX FD */ + ETH_BTxEn); /* BDMA Tx Enable */ + + /* configure the MAC Transmitter control */ + PUT_REG( REG_MACTXCON, + ETH_EnComp | /* interrupt when the MAC transmits or discards packet */ + ETH_TxEn); /* MAC transmit enable */ + + /* configure the BDMA Receiver control */ + PUT_REG( REG_BDMARXCON, + ETH_BRxBRST | /* BDMA Rx Burst Size 16 words */ + ETH_BRxSTSKO | /* BDMA Rx interrupt(Stop) on non-owner RX FD */ + ETH_BRxMAINC | /* BDMA Rx Memory Address increment */ + ETH_BRxDIE | /* BDMA Rx Every Received Frame Interrupt Enable */ + ETH_BRxNLIE | /* BDMA Rx NULL List Interrupt Enable */ + ETH_BRxNOIE | /* BDMA Rx Not Owner Interrupt Enable */ + ETH_BRxLittle | /* BDMA Rx Little endian */ + ETH_BRxEn); /* BDMA Rx Enable */ + + /* configure the MAC Receiver control */ + PUT_REG( REG_MACRXCON, + ETH_RxEn); /* MAC ETH_RxEn */ + + return 0; + +} + +/* Send a packet */ +s32 eth_send(volatile void *packet, s32 length) +{ + + u32 i; + ETH *eth = &m_eth; + + if ( eth->m_curTX_FD->m_frameDataPtr.bf.owner) { + printf("eth_send(): TX Frame. CPU not owner.\n"); + return -1; + } + + /* copy user data into frame data pointer */ + memcpy((void *)(eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr), + (void *)packet, + length); + + /* Set TX Frame flags */ + eth->m_curTX_FD->m_opt.bf.widgetAlign = 0; + eth->m_curTX_FD->m_opt.bf.frameDataDir = 1; + eth->m_curTX_FD->m_opt.bf.littleEndian = 1; + eth->m_curTX_FD->m_opt.bf.macTxIrqEnbl = 1; + eth->m_curTX_FD->m_opt.bf.no_crc = 0; + eth->m_curTX_FD->m_opt.bf.no_padding = 0; + + /* Set TX Frame length */ + eth->m_curTX_FD->m_status.bf.len = length; + + /* Change ownership to BDMA */ + eth->m_curTX_FD->m_frameDataPtr.bf.owner = 1; + + /* Enable MAC and BDMA Tx control register */ + SET_REG( REG_BDMATXCON, ETH_BTxEn); + SET_REG( REG_MACTXCON, ETH_TxEn); + + /* poll on TX completion status */ + while ( !eth->m_curTX_FD->m_status.bf.complete) { + /* sleep */ + for ( i = 0; i < 0x10000; i ++); + } + + /* Change the Tx frame descriptor for next use */ + eth->m_curTX_FD = eth->m_curTX_FD->m_nextFD; + + return 0; +} + +/* Check for received packets */ +s32 eth_rx (void) +{ + s32 nLen = 0; + ETH *eth = &m_eth; + + /* check if packet ready */ + if ( (GET_REG( REG_BDMASTAT)) & ETH_S_BRxRDF) { + /* process all waiting packets */ + while ( !eth->m_curRX_FD->m_frameDataPtr.bf.owner) { + nLen = eth->m_curRX_FD->m_status.bf.len; + /* call back u-boot -- may call eth_send() */ + NetReceive ((u8 *)eth->m_curRX_FD->m_frameDataPtr.ui, nLen); + /* set owner back to CPU */ + eth->m_curRX_FD->m_frameDataPtr.bf.owner = 1; + /* clear status */ + eth->m_curRX_FD->m_status.ui = 0x0; + /* advance to next descriptor */ + eth->m_curRX_FD = eth->m_curRX_FD->m_nextFD; + /* clear received frame bit */ + PUT_REG( REG_BDMASTAT, ETH_S_BRxRDF); + } + } + + return nLen; +} + +/* Halt ethernet engine */ +void eth_halt(void) +{ + /* disable MAC */ + PUT_REG( REG_MACCON, ETH_HaltReg); +} + +#endif diff --git a/drivers/s3c4510b_eth.h b/drivers/s3c4510b_eth.h new file mode 100644 index 000000000..cbddba71a --- /dev/null +++ b/drivers/s3c4510b_eth.h @@ -0,0 +1,302 @@ +#ifndef __S3C4510B_ETH_H +#define __S3C4510B_ETH_H +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * MODULE: $Id:$ + * Description: Ethernet interface + * Runtime Env: ARM7TDMI + * Change History: + * 03-02-04 Create (Curt Brune) curt@cucy.com + * + */ + +#define __packed __attribute__ ((packed)) + +#define ETH_MAC_ADDR_SIZE (6) /* dst,src addr is 6bytes each */ +#define ETH_MaxTxFrames (16) /* Max number of Tx Frames */ + +/* Buffered DMA Receiver Control Register */ +#define ETH_BRxBRST 0x0000F /* BDMA Rx Burst Size * BRxBRST */ + /* = Burst Data Size 16 */ +#define ETH_BRxSTSKO 0x00020 /* BDMA Rx Stop/Skip Frame or Interrupt(=1) */ + /* case of not OWNER the current Frame */ +#define ETH_BRxMAINC 0x00040 /* BDMA Rx Memory Address Inc/Dec */ +#define ETH_BRxDIE 0x00080 /* BDMA Rx Every Received Frame Interrupt Enable */ +#define ETH_BRxNLIE 0x00100 /* BDMA Rx NULL List Interrupt Enable */ +#define ETH_BRxNOIE 0x00200 /* BDMA Rx Not Owner Interrupt Enable */ +#define ETH_BRxMSOIE 0x00400 /* BDMA Rx Maximum Size over Interrupr Enable */ +#define ETH_BRxLittle 0x00800 /* BDMA Rx Big/Little Endian */ +#define ETH_BRxBig 0x00000 /* BDMA Rx Big/Little Endian */ +#define ETH_BRxWA01 0x01000 /* BDMA Rx Word Alignment- one invalid byte */ +#define ETH_BRxWA10 0x02000 /* BDMA Rx Word Alignment- two invalid byte */ +#define ETH_BRxWA11 0x03000 /* BDMA Rx Word Alignment- three invalid byte */ +#define ETH_BRxEn 0x04000 /* BDMA Rx Enable */ +#define ETH_BRxRS 0x08000 /* BDMA Rx Reset */ +#define ETH_RxEmpty 0x10000 /* BDMA Rx Buffer empty interrupt */ +#define ETH_BRxEarly 0x20000 /* BDMA Rx Early notify Interrupt */ + +/* Buffered DMA Trasmit Control Register(BDMATXCON) */ +#define ETH_BTxBRST 0x0000F /* BDMA Tx Burst Size = 16 */ +#define ETH_BTxSTSKO 0x00020 /* BDMA Tx Stop/Skip Frame or Interrupt in case */ + /* of not Owner the current frame */ +#define ETH_BTxCPIE 0x00080 /* BDMA Tx Complete to send control */ + /* packet Enable */ +#define ETH_BTxNOIE 0x00200 /* BDMA Tx Buffer Not Owner */ +#define ETH_BTxEmpty 0x00400 /* BDMA Tx Buffer Empty Interrupt */ + +/* BDMA Tx buffer can be moved to the MAC Tx IO when the new frame comes in. */ +#define ETH_BTxMSL000 0x00000 /* No wait to fill the BDMA */ +#define ETH_BTxMSL001 0x00800 /* wait to fill 1/8 of the BDMA */ +#define ETH_BTxMSL010 0x01000 /* wait to fill 2/8 of the BDMA */ +#define ETH_BTxMSL011 0x01800 /* wait to fill 3/8 of the BDMA */ +#define ETH_BTxMSL100 0x02000 /* wait to fill 4/8 of the BDMA */ +#define ETH_BTxMSL101 0x02800 /* wait to fill 5/8 of the BDMA */ +#define ETH_BTxMSL110 0x03000 /* wait to fill 6/8 of the BDMA */ +#define ETH_BTxMSL111 0x03800 /* wait to fill 7/8 of the BDMA */ +#define ETH_BTxEn 0x04000 /* BDMA Tx Enable */ +#define ETH_BTxRS 0x08000 /* BDMA Tx Reset */ + +/* BDMA Status Register */ +#define ETH_S_BRxRDF 0x00001 /* BDMA Rx Done Every Received Frame */ +#define ETH_S_BRxNL 0x00002 /* BDMA Rx NULL List */ +#define ETH_S_BRxNO 0x00004 /* BDMA Rx Not Owner */ +#define ETH_S_BRxMSO 0x00008 /* BDMA Rx Maximum Size Over */ +#define ETH_S_BRxEmpty 0x00010 /* BDMA Rx Buffer Empty */ +#define ETH_S_BRxSEarly 0x00020 /* Early Notify */ +#define ETH_S_BRxFRF 0x00080 /* One more frame data in BDMA receive buffer */ +#define ETH_S_BTxCCP 0x10000 /* BDMA Tx Complete to send Control Packet */ +#define ETH_S_BTxNL 0x20000 /* BDMA Tx Null List */ +#define ETH_S_BTxNO 0x40000 /* BDMA Tx Not Owner */ +#define ETH_S_BTxEmpty 0x100000 /* BDMA Tx Buffer Empty */ + +/* MAC Control Register */ +#define ETH_HaltReg 0x0001 /* stop transmission and reception */ + /* after completion of any current packets */ +#define ETH_HaltImm 0x0002 /* Stop transmission and reception immediately */ +#define ETH_SwReset 0x0004 /* reset all Ethernet controller state machines */ + /* and FIFOs */ +#define ETH_FullDup 0x0008 /* allow transmission to begin while reception */ + /* is occurring */ +#define ETH_MACLoop 0x0010 /* MAC loopback */ +#define ETH_ConnM00 0x0000 /* Automatic-default */ +#define ETH_ConnM01 0x0020 /* Force 10Mbits endec */ +#define ETH_ConnM10 0x0040 /* Force MII (rate determined by MII clock */ +#define ETH_MIIOFF 0x0040 /* Force MII (rate determined by MII clock */ +#define ETH_Loop10 0x0080 /* Loop 10Mbps */ +#define ETH_MissRoll 0x0400 /* Missed error counter rolled over */ +#define ETH_MDCOFF 0x1000 /* MII Station Management Clock Off */ +#define ETH_EnMissRoll 0x2000 /* Interrupt when missed error counter rolls */ + /* over */ +#define ETH_Link10 0x8000 /* Link status 10Mbps */ + +/* CAM control register(CAMCON) */ +#define ETH_StationAcc 0x0001 /* Accept any packet with a unicast station */ + /* address */ +#define ETH_GroupAcc 0x0002 /* Accept any packet with multicast-group */ + /* station address */ +#define ETH_BroadAcc 0x0004 /* Accept any packet with a broadcast station */ + /* address */ +#define ETH_NegCAM 0x0008 /* 0: Accept packets CAM recognizes, */ + /* reject others */ + /* 1: reject packets CAM recognizes, */ + /* accept others */ +#define ETH_CompEn 0x0010 /* Compare Enable mode */ + +/* Transmit Control Register(MACTXCON) */ +#define ETH_TxEn 0x0001 /* transmit Enable */ +#define ETH_TxHalt 0x0002 /* Transmit Halt Request */ +#define ETH_NoPad 0x0004 /* suppress Padding */ +#define ETH_NoCRC 0x0008 /* Suppress CRC */ +#define ETH_FBack 0x0010 /* Fast Back-off */ +#define ETH_NoDef 0x0020 /* Disable the defer counter */ +#define ETH_SdPause 0x0040 /* Send Pause */ +#define ETH_MII10En 0x0080 /* MII 10Mbps mode enable */ +#define ETH_EnUnder 0x0100 /* Enable Underrun */ +#define ETH_EnDefer 0x0200 /* Enable Deferral */ +#define ETH_EnNCarr 0x0400 /* Enable No Carrier */ +#define ETH_EnExColl 0x0800 /* interrupt if 16 collision occur */ + /* in the same packet */ +#define ETH_EnLateColl 0x1000 /* interrupt if collision occurs after */ + /* 512 bit times(64 bytes times) */ +#define ETH_EnTxPar 0x2000 /* interrupt if the MAC transmit FIFO */ + /* has a parity error */ +#define ETH_EnComp 0x4000 /* interrupt when the MAC transmits or */ + /* discards one packet */ + +/* Transmit Status Register(MACTXSTAT) */ +#define ETH_ExColl 0x0010 /* Excessive collision */ +#define ETH_TxDeffered 0x0020 /* set if 16 collisions occur for same packet */ +#define ETH_Paused 0x0040 /* packet waited because of pause during */ + /* transmission */ +#define ETH_IntTx 0x0080 /* set if transmission of packet causes an */ + /* interrupt condiftion */ +#define ETH_Under 0x0100 /* MAC transmit FIFO becomes empty during */ + /* transmission */ +#define ETH_Defer 0x0200 /* MAC defers for MAC deferral */ +#define ETH_NCarr 0x0400 /* No carrier sense detected during the */ + /* transmission of a packet */ +#define ETH_SQE 0x0800 /* Signal Quality Error */ +#define ETH_LateColl 0x1000 /* a collision occures after 512 bit times */ +#define ETH_TxPar 0x2000 /* MAC transmit FIFO has detected a parity error */ +#define ETH_Comp 0x4000 /* MAC transmit or discards one packet */ +#define ETH_TxHalted 0x8000 /* Transmission was halted by clearing */ + /* TxEn or Halt immedite */ + +/* Receive Control Register (MACRXCON) */ +#define ETH_RxEn 0x0001 +#define ETH_RxHalt 0x0002 +#define ETH_LongEn 0x0004 +#define ETH_ShortEn 0x0008 +#define ETH_StripCRC 0x0010 +#define ETH_PassCtl 0x0020 +#define ETH_IgnoreCRC 0x0040 +#define ETH_EnAlign 0x0100 +#define ETH_EnCRCErr 0x0200 +#define ETH_EnOver 0x0400 +#define ETH_EnLongErr 0x0800 +#define ETH_EnRxPar 0x2000 +#define ETH_EnGood 0x4000 + +/* Receive Status Register(MACRXSTAT) */ +#define ETH_MCtlRecd 0x0020 +#define ETH_MIntRx 0x0040 +#define ETH_MRx10Stat 0x0080 +#define ETH_MAllignErr 0x0100 +#define ETH_MCRCErr 0x0200 +#define ETH_MOverflow 0x0400 +#define ETH_MLongErr 0x0800 +#define ETH_MRxPar 0x2000 +#define ETH_MRxGood 0x4000 +#define ETH_MRxHalted 0x8000 + +/* type of ethernet packets */ +#define ETH_TYPE_ARP (0x0806) +#define ETH_TYPE_IP (0x0800) + +#define ETH_HDR_SIZE (14) + +/* bit field for frame data pointer word */ +typedef struct __BF_FrameDataPtr { + u32 dataPtr:31; + u32 owner: 1; +} BF_FrameDataPtr; + +typedef union _FrameDataPtr { + u32 ui; + BF_FrameDataPtr bf; +} FrameDataPtr; + +typedef struct __BF_TX_Options { + u32 no_padding: 1; + u32 no_crc: 1; + u32 macTxIrqEnbl: 1; + u32 littleEndian: 1; + u32 frameDataDir: 1; + u32 widgetAlign: 2; + u32 reserved:25; +} BF_TX_Options; + +typedef union _TX_Options { + u32 ui; + BF_TX_Options bf; +} TX_Options; + +typedef struct __BF_RX_Status { + u32 len:16; /* frame length */ + u32 reserved1: 3; + u32 overMax: 1; + u32 reserved2: 1; + u32 ctrlRcv: 1; + u32 intRx: 1; + u32 rx10stat: 1; + u32 alignErr: 1; + u32 crcErr: 1; + u32 overFlow: 1; + u32 longErr: 1; + u32 reserved3: 1; + u32 parityErr: 1; + u32 good: 1; + u32 halted: 1; +} BF_RX_Status; + +typedef union _RX_Status { + u32 ui; + BF_RX_Status bf; +} RX_Status; + +typedef struct __BF_TX_Status { + u32 len:16; /* frame length */ + u32 txCollCnt: 4; + u32 exColl: 1; + u32 txDefer: 1; + u32 paused: 1; + u32 intTx: 1; + u32 underRun: 1; + u32 defer: 1; + u32 noCarrier: 1; + u32 SQErr: 1; + u32 lateColl: 1; + u32 parityErr: 1; + u32 complete: 1; + u32 halted: 1; +} BF_TX_Status; + +typedef union _TX_Status { + u32 ui; + BF_TX_Status bf; +} TX_Status; + +/* TX descriptor structure */ +typedef struct __TX_FrameDescriptor { + volatile FrameDataPtr m_frameDataPtr; + TX_Options m_opt; + volatile TX_Status m_status; + struct __TX_FrameDescriptor *m_nextFD; +} TX_FrameDescriptor; + +/* RX descriptor structure */ +typedef struct __RX_FrameDescriptor { + volatile FrameDataPtr m_frameDataPtr; + u32 m_reserved; + volatile RX_Status m_status; + struct __RX_FrameDescriptor *m_nextFD; +} RX_FrameDescriptor; + +/* MAC Frame Structure */ +typedef struct __MACFrame { + u8 m_dstAddr[6] __packed; + u8 m_srcAddr[6] __packed; + u16 m_lengthOrType __packed; + u8 m_payload[1506] __packed; +} MACFrame; + +/* Ethernet Control block */ +typedef struct __ETH { + TX_FrameDescriptor *m_curTX_FD; /* pointer to current TX frame descriptor */ + TX_FrameDescriptor *m_baseTX_FD; /* pointer to base TX frame descriptor */ + RX_FrameDescriptor *m_curRX_FD; /* pointer to current RX frame descriptor */ + RX_FrameDescriptor *m_baseRX_FD; /* pointer to base RX frame descriptor */ + u8 *m_mac; /* pointer to our MAC address */ +} ETH; + +#endif diff --git a/drivers/s3c4510b_uart.c b/drivers/s3c4510b_uart.c new file mode 100644 index 000000000..ddcd591f8 --- /dev/null +++ b/drivers/s3c4510b_uart.c @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * MODULE: $Id:$ + * Description: UART/Serial interface for Samsung S3C4510B SoC + * Runtime Env: ARM7TDMI + * Change History: + * 03-02-04 Create (Curt Brune) curt@cucy.com + * + */ + +#include + +#ifdef CONFIG_DRIVER_S3C4510_UART + +#include +#include "s3c4510b_uart.h" + +DECLARE_GLOBAL_DATA_PTR; + +static UART *uart; + +/* flush serial input queue. returns 0 on success or negative error + * number otherwise + */ +static int serial_flush_input(void) +{ + volatile u32 tmp; + + /* keep on reading as long as the receiver is not empty */ + while( uart->m_stat.bf.rxReady) { + tmp = uart->m_rx; + } + + return 0; +} + + +/* flush output queue. returns 0 on success or negative error number + * otherwise + */ +static int serial_flush_output(void) +{ + /* wait until the transmitter is no longer busy */ + while( !uart->m_stat.bf.txBufEmpty); + + return 0; +} + + +void serial_setbrg (void) +{ + UART_LINE_CTRL ulctrl; + UART_CTRL uctrl; + UART_BAUD_DIV ubd; + + serial_flush_output(); + serial_flush_input(); + + /* control register */ + uctrl.ui = 0x0; + uctrl.bf.rxMode = 0x1; + uctrl.bf.rxIrq = 0x0; + uctrl.bf.txMode = 0x1; + uctrl.bf.DSR = 0x0; + uctrl.bf.sendBreak = 0x0; + uctrl.bf.loopBack = 0x0; + uart->m_ctrl.ui = uctrl.ui; + + /* line control register */ + ulctrl.ui = 0x0; + ulctrl.bf.wordLen = 0x3; /* 8 bit data */ + ulctrl.bf.nStop = 0x0; /* 1 stop bit */ + ulctrl.bf.parity = 0x0; /* no parity */ + ulctrl.bf.clk = 0x0; /* internal clock */ + ulctrl.bf.infra_red = 0x0; /* no infra_red */ + uart->m_lineCtrl.ui = ulctrl.ui; + + ubd.ui = 0x0; + + /* see table on page 10-15 in SAMSUNG S3C4510B manual */ + /* get correct divisor */ + switch(gd->baudrate) { + case 1200: ubd.bf.cnt0 = 1301; break; + case 2400: ubd.bf.cnt0 = 650; break; + case 4800: ubd.bf.cnt0 = 324; break; + case 9600: ubd.bf.cnt0 = 162; break; + case 19200: ubd.bf.cnt0 = 80; break; + case 38400: ubd.bf.cnt0 = 40; break; + case 57600: ubd.bf.cnt0 = 26; break; + case 115200: ubd.bf.cnt0 = 13; break; + } + + uart->m_baudDiv.ui = ubd.ui; + uart->m_baudCnt = 0x0; + uart->m_baudClk = 0x0; + +} + + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + +#if CONFIG_SERIAL1 == 1 + uart = (UART *)UART0_BASE; +#elif CONFIG_SERIAL1 == 2 + uart = (UART *)UART1_BASE; +#else +#error CONFIG_SERIAL1 not equal to 1 or 2 +#endif + + serial_setbrg (); + + return (0); +} + + +/* + * Output a single byte to the serial port. + */ +void serial_putc (const char c) +{ + /* wait for room in the transmit FIFO */ + while( !uart->m_stat.bf.txBufEmpty); + + uart->m_tx = c; + + /* + to be polite with serial console add a line feed + to the carriage return character + */ + if (c=='\n') + serial_putc('\r'); +} + +/* + * Test if an input byte is ready from the serial port. Returns non-zero on + * success, 0 otherwise. + */ +int serial_tstc (void) +{ + return uart->m_stat.bf.rxReady; +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc (void) +{ + int rv; + + for(;;) { + rv = serial_tstc(); + + if (rv) { + return uart->m_rx & 0xFF; + } + } +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } + + /* busy wait for tx complete */ + while ( !uart->m_stat.bf.txComplete); + + /* clear break */ + uart->m_ctrl.bf.sendBreak = 0; + +} + +#endif diff --git a/drivers/s3c4510b_uart.h b/drivers/s3c4510b_uart.h new file mode 100644 index 000000000..b06c76d84 --- /dev/null +++ b/drivers/s3c4510b_uart.h @@ -0,0 +1,109 @@ +#ifndef __UART_H +#define __UART_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: S3C4510B UART register layout + */ + +/* UART LINE CONTROL register */ +typedef struct __BF_UART_LINE_CTRL { + u32 wordLen: 2; + u32 nStop: 1; + u32 parity: 3; + u32 clk: 1; + u32 infra_red: 1; + u32 unused:24; +} BF_UART_LINE_CTRL; + +typedef union _UART_LINE_CTRL { + u32 ui; + BF_UART_LINE_CTRL bf; +} UART_LINE_CTRL; + +/* UART CONTROL register */ +typedef struct __BF_UART_CTRL { + u32 rxMode: 2; + u32 rxIrq: 1; + u32 txMode: 2; + u32 DSR: 1; + u32 sendBreak: 1; + u32 loopBack: 1; + u32 unused:24; +} BF_UART_CTRL; + +typedef union _UART_CTRL { + u32 ui; + BF_UART_CTRL bf; +} UART_CTRL; + +/* UART STATUS register */ +typedef struct __BF_UART_STAT { + u32 overrun: 1; + u32 parity: 1; + u32 frame: 1; + u32 breakIrq: 1; + u32 DTR: 1; + u32 rxReady: 1; + u32 txBufEmpty: 1; + u32 txComplete: 1; + u32 unused:24; +} BF_UART_STAT; + +typedef union _UART_STAT { + u32 ui; + BF_UART_STAT bf; +} UART_STAT; + +/* UART BAUD_DIV register */ +typedef struct __BF_UART_BAUD_DIV { + u32 cnt1: 4; + u32 cnt0:12; + u32 unused:16; +} BF_UART_BAUD_DIV; + +typedef union _UART_BAUD_DIV { + u32 ui; + BF_UART_BAUD_DIV bf; +} UART_BAUD_DIV; + +/* UART register block */ +typedef struct __UART { + volatile UART_LINE_CTRL m_lineCtrl; + volatile UART_CTRL m_ctrl; + volatile UART_STAT m_stat; + volatile u32 m_tx; + volatile u32 m_rx; + volatile UART_BAUD_DIV m_baudDiv; + volatile u32 m_baudCnt; + volatile u32 m_baudClk; +} UART; + +#define NL 0x0A +#define CR 0x0D +#define BSP 0x08 +#define ESC 0x1B +#define CTRLZ 0x1A +#define RUBOUT 0x7F + +#endif diff --git a/drivers/sed13806.c b/drivers/sed13806.c new file mode 100644 index 000000000..6996ca805 --- /dev/null +++ b/drivers/sed13806.c @@ -0,0 +1,310 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* Video support for Epson SED13806 chipset */ + +#include + +#ifdef CONFIG_VIDEO_SED13806 + +#include +#include + +#define readByte(ptrReg) \ + *(volatile unsigned char *)(sed13806.isaBase + ptrReg) + +#define writeByte(ptrReg,value) \ + *(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value + +#ifdef CONFIG_TOTAL5200 +#define writeWord(ptrReg,value) \ + (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = value) +#else +#define writeWord(ptrReg,value) \ + (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00)) +#endif + +GraphicDevice sed13806; + +/*----------------------------------------------------------------------------- + * EpsonSetRegs -- + *----------------------------------------------------------------------------- + */ +static void EpsonSetRegs (void) +{ + /* the content of the chipset register depends on the board (clocks, ...)*/ + const S1D_REGS *preg = board_get_regs (); + while (preg -> Index) { + writeByte (preg -> Index, preg -> Value); + preg ++; + } +} + +/*----------------------------------------------------------------------------- + * video_hw_init -- + *----------------------------------------------------------------------------- + */ +void *video_hw_init (void) +{ + unsigned int *vm, i; + + memset (&sed13806, 0, sizeof (GraphicDevice)); + + /* Initialization of the access to the graphic chipset + Retreive base address of the chipset + (see board/RPXClassic/eccx.c) */ + if ((sed13806.isaBase = board_video_init ()) == 0) { + return (NULL); + } + + sed13806.frameAdrs = sed13806.isaBase + FRAME_BUFFER_OFFSET; + sed13806.winSizeX = board_get_width (); + sed13806.winSizeY = board_get_height (); + +#if defined(CONFIG_VIDEO_SED13806_8BPP) + sed13806.gdfIndex = GDF__8BIT_INDEX; + sed13806.gdfBytesPP = 1; + +#elif defined(CONFIG_VIDEO_SED13806_16BPP) + sed13806.gdfIndex = GDF_16BIT_565RGB; + sed13806.gdfBytesPP = 2; + +#else +#error Unsupported SED13806 BPP +#endif + + sed13806.memSize = sed13806.winSizeX * sed13806.winSizeY * sed13806.gdfBytesPP; + + /* Load SED registers */ + EpsonSetRegs (); + + /* (see board/RPXClassic/RPXClassic.c) */ + board_validate_screen (sed13806.isaBase); + + /* Clear video memory */ + i = sed13806.memSize/4; + vm = (unsigned int *)sed13806.frameAdrs; + while(i--) + *vm++ = 0; + + + return (&sed13806); +} +/*----------------------------------------------------------------------------- + * Epson_wait_idle -- Wait for hardware to become idle + *----------------------------------------------------------------------------- + */ +static void Epson_wait_idle (void) +{ + while (readByte (BLT_CTRL0) & 0x80); + + /* Read a word in the BitBLT memory area to shutdown the BitBLT engine */ + *(volatile unsigned short *)(sed13806.isaBase + BLT_REG); +} + +/*----------------------------------------------------------------------------- + * video_hw_bitblt -- + *----------------------------------------------------------------------------- + */ +void video_hw_bitblt ( + unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&sed13806; + unsigned long srcAddr, dstAddr; + unsigned int stride = bpp * pGD -> winSizeX; + + srcAddr = (src_y * stride) + (src_x * bpp); + dstAddr = (dst_y * stride) + (dst_x * bpp); + + Epson_wait_idle (); + + writeByte(BLT_ROP,0x0C); /* source */ + writeByte(BLT_OP,0x02);/* move blit in positive direction with ROP */ + writeWord(BLT_MEM_OFF0, stride / 2); + if (pGD -> gdfIndex == GDF__8BIT_INDEX) { + writeByte(BLT_CTRL1,0x00); + } + else { + writeByte(BLT_CTRL1,0x01); + } + + writeWord(BLT_WIDTH0,(dim_x - 1)); + writeWord(BLT_HEIGHT0,(dim_y - 1)); + + /* set up blit registers */ + writeByte(BLT_SRC_ADDR0,srcAddr); + writeByte(BLT_SRC_ADDR1,srcAddr>>8); + writeByte(BLT_SRC_ADDR2,srcAddr>>16); + + writeByte(BLT_DST_ADDR0,dstAddr); + writeByte(BLT_DST_ADDR1,dstAddr>>8); + writeByte(BLT_DST_ADDR2,dstAddr>>16); + + /* Engage the blt engine */ + /* rectangular region for src and dst */ + writeByte(BLT_CTRL0,0x80); + + /* wait untill current blits finished */ + Epson_wait_idle (); +} +/*----------------------------------------------------------------------------- + * video_hw_rectfill -- + *----------------------------------------------------------------------------- + */ +void video_hw_rectfill ( + unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&sed13806; + unsigned long dstAddr; + unsigned int stride = bpp * pGD -> winSizeX; + + dstAddr = (dst_y * stride) + (dst_x * bpp); + + Epson_wait_idle (); + + /* set up blit registers */ + writeByte(BLT_DST_ADDR0,dstAddr); + writeByte(BLT_DST_ADDR1,dstAddr>>8); + writeByte(BLT_DST_ADDR2,dstAddr>>16); + + writeWord(BLT_WIDTH0,(dim_x - 1)); + writeWord(BLT_HEIGHT0,(dim_y - 1)); + writeWord(BLT_FGCOLOR0,color); + + writeByte(BLT_OP,0x0C); /* solid fill */ + writeWord(BLT_MEM_OFF0,stride / 2); + + if (pGD -> gdfIndex == GDF__8BIT_INDEX) { + writeByte(BLT_CTRL1,0x00); + } + else { + writeByte(BLT_CTRL1,0x01); + } + + /* Engage the blt engine */ + /* rectangular region for src and dst */ + writeByte(BLT_CTRL0,0x80); + + /* wait untill current blits finished */ + Epson_wait_idle (); +} + +/*----------------------------------------------------------------------------- + * video_set_lut -- + *----------------------------------------------------------------------------- + */ +void video_set_lut ( + unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + writeByte(REG_LUT_ADDR, index ); + writeByte(REG_LUT_DATA, r); + writeByte(REG_LUT_DATA, g); + writeByte(REG_LUT_DATA, b); +} +#ifdef CONFIG_VIDEO_HW_CURSOR +/*----------------------------------------------------------------------------- + * video_set_hw_cursor -- + *----------------------------------------------------------------------------- + */ +void video_set_hw_cursor (int x, int y) +{ + writeByte (LCD_CURSOR_XL, (x & 0xff)); + writeByte (LCD_CURSOR_XM, (x >> 8)); + writeByte (LCD_CURSOR_YL, (y & 0xff)); + writeByte (LCD_CURSOR_YM, (y >> 8)); +} + +/*----------------------------------------------------------------------------- + * video_init_hw_cursor -- + *----------------------------------------------------------------------------- + */ +void video_init_hw_cursor (int font_width, int font_height) +{ + volatile unsigned char *ptr; + unsigned char pattern; + int i; + + + /* Init cursor content + Cursor size is 64x64 pixels + Start of the cursor memory depends on panel type (dual panel ...) */ + if ((i = readByte (LCD_CURSOR_START)) == 0) { + ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE); + } + else { + ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192)); + } + + /* Fill the first line and the first empty line after cursor */ + for (i = 0, pattern = 0; i < 64; i++) { + if (i < font_width) { + /* Invert background */ + pattern |= 0x3; + + } + else { + /* Background */ + pattern |= 0x2; + } + if ((i & 3) == 3) { + *ptr = pattern; + *(ptr + font_height * 16) = 0xaa; + ptr ++; + pattern = 0; + } + pattern <<= 2; + } + + /* Duplicate this line */ + for (i = 1; i < font_height; i++) { + memcpy ((void *)ptr, (void *)(ptr - 16), 16); + ptr += 16; + } + + for (; i < 64; i++) { + memcpy ((void *)(ptr + 16), (void *)ptr, 16); + ptr += 16; + } + + /* Select cursor mode */ + writeByte (LCD_CURSOR_CNTL, 1); +} +#endif +#endif diff --git a/drivers/sed156x.c b/drivers/sed156x.c new file mode 100644 index 000000000..e9d5ed4cc --- /dev/null +++ b/drivers/sed156x.c @@ -0,0 +1,566 @@ +/* + * (C) Copyright 2003 + * + * Pantelis Antoniou + * Intracom S.A. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +#ifdef CONFIG_SED156X + +/* configure according to the selected display */ +#if defined(CONFIG_SED156X_PG12864Q) +#define LCD_WIDTH 128 +#define LCD_HEIGHT 64 +#define LCD_LINES 64 +#define LCD_PAGES 9 +#define LCD_COLUMNS 132 +#else +#error Unsupported SED156x configuration +#endif + +/* include the font data */ +#include + +#if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16 +#error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16 +#endif + +#define LCD_BYTE_WIDTH (LCD_WIDTH / 8) +#define VIDEO_FONT_BYTE_WIDTH (VIDEO_FONT_WIDTH / 8) + +#define LCD_TEXT_WIDTH (LCD_WIDTH / VIDEO_FONT_WIDTH) +#define LCD_TEXT_HEIGHT (LCD_HEIGHT / VIDEO_FONT_HEIGHT) + +#define LCD_BYTE_LINESZ (LCD_BYTE_WIDTH * VIDEO_FONT_HEIGHT) + +const int sed156x_text_width = LCD_TEXT_WIDTH; +const int sed156x_text_height = LCD_TEXT_HEIGHT; + +/**************************************************************************************/ + +#define SED156X_SPI_RXD() (SED156X_SPI_RXD_PORT & SED156X_SPI_RXD_MASK) + +#define SED156X_SPI_TXD(x) \ + do { \ + if (x) \ + SED156X_SPI_TXD_PORT |= SED156X_SPI_TXD_MASK; \ + else \ + SED156X_SPI_TXD_PORT &= ~SED156X_SPI_TXD_MASK; \ + } while(0) + +#define SED156X_SPI_CLK(x) \ + do { \ + if (x) \ + SED156X_SPI_CLK_PORT |= SED156X_SPI_CLK_MASK; \ + else \ + SED156X_SPI_CLK_PORT &= ~SED156X_SPI_CLK_MASK; \ + } while(0) + +#define SED156X_SPI_CLK_TOGGLE() (SED156X_SPI_CLK_PORT ^= SED156X_SPI_CLK_MASK) + +#define SED156X_SPI_BIT_DELAY() /* no delay */ + +#define SED156X_CS(x) \ + do { \ + if (x) \ + SED156X_CS_PORT |= SED156X_CS_MASK; \ + else \ + SED156X_CS_PORT &= ~SED156X_CS_MASK; \ + } while(0) + +#define SED156X_A0(x) \ + do { \ + if (x) \ + SED156X_A0_PORT |= SED156X_A0_MASK; \ + else \ + SED156X_A0_PORT &= ~SED156X_A0_MASK; \ + } while(0) + +/**************************************************************************************/ + +/*** LCD Commands ***/ + +#define LCD_ON 0xAF /* Display ON */ +#define LCD_OFF 0xAE /* Display OFF */ +#define LCD_LADDR 0x40 /* Display start line set + (6-bit) address */ +#define LCD_PADDR 0xB0 /* Page address set + (4-bit) page */ +#define LCD_CADRH 0x10 /* Column address set upper + (4-bit) column hi */ +#define LCD_CADRL 0x00 /* Column address set lower + (4-bit) column lo */ +#define LCD_ADC_NRM 0xA0 /* ADC select Normal */ +#define LCD_ADC_REV 0xA1 /* ADC select Reverse */ +#define LCD_DSP_NRM 0xA6 /* LCD display Normal */ +#define LCD_DSP_REV 0xA7 /* LCD display Reverse */ +#define LCD_DPT_NRM 0xA4 /* Display all points Normal */ +#define LCD_DPT_ALL 0xA5 /* Display all points ON */ +#define LCD_BIAS9 0xA2 /* LCD bias set 1/9 */ +#define LCD_BIAS7 0xA3 /* LCD bias set 1/7 */ +#define LCD_CAINC 0xE0 /* Read/modify/write */ +#define LCD_CAEND 0xEE /* End */ +#define LCD_RESET 0xE2 /* Reset */ +#define LCD_C_NRM 0xC0 /* Common output mode select Normal direction */ +#define LCD_C_RVS 0xC8 /* Common output mode select Reverse direction */ +#define LCD_PWRMD 0x28 /* Power control set + (3-bit) mode */ +#define LCD_RESRT 0x20 /* V5 v. reg. int. resistor ratio set + (3-bit) ratio */ +#define LCD_EVSET 0x81 /* Electronic volume mode set + byte = (6-bit) volume */ +#define LCD_SIOFF 0xAC /* Static indicator OFF */ +#define LCD_SION 0xAD /* Static indicator ON + byte = (2-bit) mode */ +#define LCD_NOP 0xE3 /* NOP */ +#define LCD_TEST 0xF0 /* Test/Test mode reset (Note: *DO NOT USE*) */ + +/*------------------------------------------------------------------------------- + Compound commands + ------------------------------------------------------------------------------- + Command Description Commands + ---------- ------------------------ ------------------------------------- + POWS_ON POWER SAVER ON command LCD_OFF, LCD_D_ALL + POWS_OFF POWER SAVER OFF command LCD_D_NRM + SLEEPON SLEEP mode LCD_SIOFF, POWS_ON + SLEEPOFF SLEEP mode cancel LCD_D_NRM, LCD_SION, LCD_SIS_??? + STDBYON STAND BY mode LCD_SION, POWS_ON + STDBYOFF STAND BY mode cancel LCD_D_NRM + -------------------------------------------------------------------------------*/ + +/*** LCD various parameters ***/ +#define LCD_PPB 8 /* Pixels per byte (display is B/W, 1 bit per pixel) */ + +/*** LCD Status byte masks ***/ +#define LCD_S_BUSY 0x80 /* Status Read - BUSY mask */ +#define LCD_S_ADC 0x40 /* Status Read - ADC mask */ +#define LCD_S_ONOFF 0x20 /* Status Read - ON/OFF mask */ +#define LCD_S_RESET 0x10 /* Status Read - RESET mask */ + +/*** LCD commands parameter masks ***/ +#define LCD_M_LADDR 0x3F /* Display start line (6-bit) address mask */ +#define LCD_M_PADDR 0x0F /* Page address (4-bit) page mask */ +#define LCD_M_CADRH 0x0F /* Column address upper (4-bit) column hi mask */ +#define LCD_M_CADRL 0x0F /* Column address lower (4-bit) column lo mask */ +#define LCD_M_PWRMD 0x07 /* Power control (3-bit) mode mask */ +#define LCD_M_RESRT 0x07 /* V5 v. reg. int. resistor ratio (3-bit) ratio mask */ +#define LCD_M_EVSET 0x3F /* Electronic volume mode byte (6-bit) volume mask */ +#define LCD_M_SION 0x03 /* Static indicator ON (2-bit) mode mask */ + +/*** LCD Power control cirquits control masks ***/ +#define LCD_PWRBSTR 0x04 /* Power control mode - Booster cirquit ON */ +#define LCD_PWRVREG 0x02 /* Power control mode - Voltage regulator cirquit ON */ +#define LCD_PWRVFOL 0x01 /* Power control mode - Voltage follower cirquit ON */ + +/*** LCD Static indicator states ***/ +#define LCD_SIS_OFF 0x00 /* Static indicator register set - OFF state */ +#define LCD_SIS_BL 0x01 /* Static indicator register set - 1s blink state */ +#define LCD_SIS_RBL 0x02 /* Static indicator register set - .5s rapid blink state */ +#define LCD_SIS_ON 0x03 /* Static indicator register set - constantly on state */ + +/*** LCD functions special parameters (commands) ***/ +#define LCD_PREVP 0x80 /* Page number for moving to previous */ +#define LCD_NEXTP 0x81 /* or next page */ +#define LCD_ERR_P 0xFF /* Error in page number */ + +/*** LCD initialization settings ***/ +#define LCD_BIAS LCD_BIAS9 /* Bias: 1/9 */ +#define LCD_ADCMODE LCD_ADC_NRM /* ADC mode: normal */ +#define LCD_COMDIR LCD_C_NRM /* Common output mode: normal */ +#define LCD_RRATIO 0 /* Resistor ratio: 0 */ +#define LCD_CNTRST 0x1C /* electronic volume: 1Ch */ +#define LCD_POWERM (LCD_PWRBSTR | LCD_PWRVREG | LCD_PWRVFOL) /* Power mode: All on */ + +/**************************************************************************************/ + +static inline unsigned int sed156x_transfer(unsigned int val) +{ + unsigned int rx; + int b; + + rx = 0; b = 8; + while (--b >= 0) { + SED156X_SPI_TXD(val & 0x80); + val <<= 1; + SED156X_SPI_CLK_TOGGLE(); + SED156X_SPI_BIT_DELAY(); + rx <<= 1; + if (SED156X_SPI_RXD()) + rx |= 1; + SED156X_SPI_CLK_TOGGLE(); + SED156X_SPI_BIT_DELAY(); + } + + return rx; +} + +unsigned int sed156x_data_transfer(unsigned int val) +{ + unsigned int rx; + + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(1); + + rx = sed156x_transfer(val); + + SED156X_CS(1); + + return rx; +} + +void sed156x_data_block_transfer(const u8 *p, int size) +{ + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(1); + + while (--size >= 0) + sed156x_transfer(*p++); + + SED156X_CS(1); +} + +unsigned int sed156x_cmd_transfer(unsigned int val) +{ + unsigned int rx; + + SED156X_SPI_CLK(1); + SED156X_CS(0); + SED156X_A0(0); + + rx = sed156x_transfer(val); + + SED156X_CS(1); + SED156X_A0(1); + + return rx; +} + +/******************************************************************************/ + +static u8 hw_screen[LCD_PAGES][LCD_COLUMNS]; +static u8 last_hw_screen[LCD_PAGES][LCD_COLUMNS]; +static u8 sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT]; + +void sed156x_sync(void) +{ + int i, j, last_page; + u8 *d; + const u8 *s, *e, *b, *r; + u8 v0, v1, v2, v3, v4, v5, v6, v7; + + /* copy and rotate sw_screen to hw_screen */ + for (i = 0; i < LCD_HEIGHT / 8; i++) { + + d = &hw_screen[i][0]; + s = &sw_screen[LCD_BYTE_WIDTH * 8 * i + LCD_BYTE_WIDTH - 1]; + + for (j = 0; j < LCD_WIDTH / 8; j++) { + + v0 = s[0 * LCD_BYTE_WIDTH]; + v1 = s[1 * LCD_BYTE_WIDTH]; + v2 = s[2 * LCD_BYTE_WIDTH]; + v3 = s[3 * LCD_BYTE_WIDTH]; + v4 = s[4 * LCD_BYTE_WIDTH]; + v5 = s[5 * LCD_BYTE_WIDTH]; + v6 = s[6 * LCD_BYTE_WIDTH]; + v7 = s[7 * LCD_BYTE_WIDTH]; + + d[0] = ((v7 & 0x01) << 7) | + ((v6 & 0x01) << 6) | + ((v5 & 0x01) << 5) | + ((v4 & 0x01) << 4) | + ((v3 & 0x01) << 3) | + ((v2 & 0x01) << 2) | + ((v1 & 0x01) << 1) | + (v0 & 0x01) ; + + d[1] = ((v7 & 0x02) << 6) | + ((v6 & 0x02) << 5) | + ((v5 & 0x02) << 4) | + ((v4 & 0x02) << 3) | + ((v3 & 0x02) << 2) | + ((v2 & 0x02) << 1) | + ((v1 & 0x02) << 0) | + ((v0 & 0x02) >> 1) ; + + d[2] = ((v7 & 0x04) << 5) | + ((v6 & 0x04) << 4) | + ((v5 & 0x04) << 3) | + ((v4 & 0x04) << 2) | + ((v3 & 0x04) << 1) | + (v2 & 0x04) | + ((v1 & 0x04) >> 1) | + ((v0 & 0x04) >> 2) ; + + d[3] = ((v7 & 0x08) << 4) | + ((v6 & 0x08) << 3) | + ((v5 & 0x08) << 2) | + ((v4 & 0x08) << 1) | + (v3 & 0x08) | + ((v2 & 0x08) >> 1) | + ((v1 & 0x08) >> 2) | + ((v0 & 0x08) >> 3) ; + + d[4] = ((v7 & 0x10) << 3) | + ((v6 & 0x10) << 2) | + ((v5 & 0x10) << 1) | + (v4 & 0x10) | + ((v3 & 0x10) >> 1) | + ((v2 & 0x10) >> 2) | + ((v1 & 0x10) >> 3) | + ((v0 & 0x10) >> 4) ; + + d[5] = ((v7 & 0x20) << 2) | + ((v6 & 0x20) << 1) | + (v5 & 0x20) | + ((v4 & 0x20) >> 1) | + ((v3 & 0x20) >> 2) | + ((v2 & 0x20) >> 3) | + ((v1 & 0x20) >> 4) | + ((v0 & 0x20) >> 5) ; + + d[6] = ((v7 & 0x40) << 1) | + (v6 & 0x40) | + ((v5 & 0x40) >> 1) | + ((v4 & 0x40) >> 2) | + ((v3 & 0x40) >> 3) | + ((v2 & 0x40) >> 4) | + ((v1 & 0x40) >> 5) | + ((v0 & 0x40) >> 6) ; + + d[7] = (v7 & 0x80) | + ((v6 & 0x80) >> 1) | + ((v5 & 0x80) >> 2) | + ((v4 & 0x80) >> 3) | + ((v3 & 0x80) >> 4) | + ((v2 & 0x80) >> 5) | + ((v1 & 0x80) >> 6) | + ((v0 & 0x80) >> 7) ; + + d += 8; + s--; + } + } + + /* and now output only the differences */ + for (i = 0; i < LCD_PAGES; i++) { + + b = &hw_screen[i][0]; + e = &hw_screen[i][LCD_COLUMNS]; + + d = &last_hw_screen[i][0]; + s = b; + + last_page = -1; + + /* update only the differences */ + do { + while (s < e && *s == *d) { + s++; + d++; + } + if (s == e) + break; + r = s; + while (s < e && *s != *d) + *d++ = *s++; + + j = r - b; + + if (i != last_page) { + sed156x_cmd_transfer(LCD_PADDR | i); + last_page = i; + } + + sed156x_cmd_transfer(LCD_CADRH | ((j >> 4) & 0x0F)); + sed156x_cmd_transfer(LCD_CADRL | (j & 0x0F)); + sed156x_data_block_transfer(r, s - r); + + } while (s < e); + } + +/******** + for (i = 0; i < LCD_PAGES; i++) { + sed156x_cmd_transfer(LCD_PADDR | i); + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS); + } + memcpy(last_hw_screen, hw_screen, sizeof(last_hw_screen)); +********/ +} + +void sed156x_clear(void) +{ + memset(sw_screen, 0, sizeof(sw_screen)); +} + +void sed156x_output_at(int x, int y, const char *str, int size) +{ + int i, j; + u8 *p; + const u8 *s; + + if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH) + return; + + p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH]; + + while (--size >= 0) { + + s = &video_fontdata[((int)*str++ & 0xff) * VIDEO_FONT_BYTE_WIDTH * VIDEO_FONT_HEIGHT]; + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++) + *p++ = *s++; + p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH; + } + p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH); + + if (x >= LCD_TEXT_WIDTH) + break; + x++; + } +} + +void sed156x_reverse_at(int x, int y, int size) +{ + int i, j; + u8 *p; + + if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH) + return; + + p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH]; + + while (--size >= 0) { + + for (i = 0; i < VIDEO_FONT_HEIGHT; i++) { + for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++, p++) + *p = ~*p; + p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH; + } + p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH); + + if (x >= LCD_TEXT_WIDTH) + break; + x++; + } +} + +void sed156x_scroll_line(void) +{ + memmove(&sw_screen[0], + &sw_screen[LCD_BYTE_LINESZ], + LCD_BYTE_WIDTH * (LCD_HEIGHT - VIDEO_FONT_HEIGHT)); +} + +void sed156x_scroll(int dx, int dy) +{ + u8 *p1 = NULL, *p2 = NULL, *p3 = NULL; /* pacify gcc */ + int adx, ady, i, sz; + + adx = dx > 0 ? dx : -dx; + ady = dy > 0 ? dy : -dy; + + /* overscroll? erase everything */ + if (adx >= LCD_TEXT_WIDTH || ady >= LCD_TEXT_HEIGHT) { + memset(sw_screen, 0, sizeof(sw_screen)); + return; + } + + sz = LCD_BYTE_LINESZ * ady; + if (dy > 0) { + p1 = &sw_screen[0]; + p2 = &sw_screen[sz]; + p3 = &sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT - sz]; + } else if (dy < 0) { + p1 = &sw_screen[sz]; + p2 = &sw_screen[0]; + p3 = &sw_screen[0]; + } + + if (ady > 0) { + memmove(p1, p2, LCD_BYTE_WIDTH * LCD_HEIGHT - sz); + memset(p3, 0, sz); + } + + sz = VIDEO_FONT_BYTE_WIDTH * adx; + if (dx > 0) { + p1 = &sw_screen[0]; + p2 = &sw_screen[0] + sz; + p3 = &sw_screen[0] + LCD_BYTE_WIDTH - sz; + } else if (dx < 0) { + p1 = &sw_screen[0] + sz; + p2 = &sw_screen[0]; + p3 = &sw_screen[0]; + } + + /* xscroll */ + if (adx > 0) { + for (i = 0; i < LCD_HEIGHT; i++) { + memmove(p1, p2, LCD_BYTE_WIDTH - sz); + memset(p3, 0, sz); + p1 += LCD_BYTE_WIDTH; + p2 += LCD_BYTE_WIDTH; + p3 += LCD_BYTE_WIDTH; + } + } +} + +void sed156x_init(void) +{ + int i; + + SED156X_CS(1); + SED156X_A0(1); + + /* Send initialization commands to the LCD */ + sed156x_cmd_transfer(LCD_OFF); /* Turn display OFF */ + sed156x_cmd_transfer(LCD_BIAS); /* set the LCD Bias, */ + sed156x_cmd_transfer(LCD_ADCMODE); /* ADC mode, */ + sed156x_cmd_transfer(LCD_COMDIR); /* common output mode, */ + sed156x_cmd_transfer(LCD_RESRT | LCD_RRATIO); /* resistor ratio, */ + sed156x_cmd_transfer(LCD_EVSET); /* electronic volume, */ + sed156x_cmd_transfer(LCD_CNTRST); + sed156x_cmd_transfer(LCD_PWRMD | LCD_POWERM); /* and power mode */ + sed156x_cmd_transfer(LCD_PADDR | 0); /* cursor home */ + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_cmd_transfer(LCD_LADDR | 0); /* and display start line */ + sed156x_cmd_transfer(LCD_DSP_NRM); /* LCD display Normal */ + + /* clear everything */ + memset(sw_screen, 0, sizeof(sw_screen)); + memset(hw_screen, 0, sizeof(hw_screen)); + memset(last_hw_screen, 0, sizeof(last_hw_screen)); + + for (i = 0; i < LCD_PAGES; i++) { + sed156x_cmd_transfer(LCD_PADDR | i); + sed156x_cmd_transfer(LCD_CADRH | 0); + sed156x_cmd_transfer(LCD_CADRL | 0); + sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS); + } + + sed156x_clear(); + sed156x_sync(); + sed156x_cmd_transfer(LCD_ON); /* Turn display ON */ +} + +#endif /* CONFIG_SED156X */ diff --git a/drivers/serial.c b/drivers/serial.c new file mode 100644 index 000000000..228781b46 --- /dev/null +++ b/drivers/serial.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_NS16550_SERIAL + +#include +#ifdef CFG_NS87308 +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_CONS_INDEX) +#error "No console index specified." +#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4) +#error "Invalid console index value." +#endif + +#if CONFIG_CONS_INDEX == 1 && !defined(CFG_NS16550_COM1) +#error "Console port 1 defined but not configured." +#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_NS16550_COM2) +#error "Console port 2 defined but not configured." +#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_NS16550_COM3) +#error "Console port 3 defined but not configured." +#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_NS16550_COM4) +#error "Console port 4 defined but not configured." +#endif + +/* Note: The port number specified in the functions is 1 based. + * the array is 0 based. + */ +static NS16550_t serial_ports[4] = { +#ifdef CFG_NS16550_COM1 + (NS16550_t)CFG_NS16550_COM1, +#else + NULL, +#endif +#ifdef CFG_NS16550_COM2 + (NS16550_t)CFG_NS16550_COM2, +#else + NULL, +#endif +#ifdef CFG_NS16550_COM3 + (NS16550_t)CFG_NS16550_COM3, +#else + NULL, +#endif +#ifdef CFG_NS16550_COM4 + (NS16550_t)CFG_NS16550_COM4 +#else + NULL +#endif +}; + +#define PORT serial_ports[port-1] +#define CONSOLE (serial_ports[CONFIG_CONS_INDEX-1]) + +static int calc_divisor (NS16550_t port) +{ +#ifdef CONFIG_OMAP1510 + /* If can't cleanly clock 115200 set div to 1 */ + if ((CFG_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) { + port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */ + return (1); /* return 1 for base divisor */ + } + port->osc_12m_sel = 0; /* clear if previsouly set */ +#endif +#ifdef CONFIG_OMAP1610 + /* If can't cleanly clock 115200 set div to 1 */ + if ((CFG_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) { + return (26); /* return 26 for base divisor */ + } +#endif + +#ifdef CONFIG_APTIX +#define MODE_X_DIV 13 +#else +#define MODE_X_DIV 16 +#endif + return (CFG_NS16550_CLK / MODE_X_DIV / gd->baudrate); + +} + +int serial_init (void) +{ + int clock_divisor; + +#ifdef CFG_NS87308 + initialise_ns87308(); +#endif + +#ifdef CFG_NS16550_COM1 + clock_divisor = calc_divisor(serial_ports[0]); + NS16550_init(serial_ports[0], clock_divisor); +#endif +#ifdef CFG_NS16550_COM2 + clock_divisor = calc_divisor(serial_ports[1]); + NS16550_init(serial_ports[1], clock_divisor); +#endif +#ifdef CFG_NS16550_COM3 + clock_divisor = calc_divisor(serial_ports[2]); + NS16550_init(serial_ports[2], clock_divisor); +#endif +#ifdef CFG_NS16550_COM4 + clock_divisor = calc_divisor(serial_ports[3]); + NS16550_init(serial_ports[3], clock_divisor); +#endif + + return (0); +} + +void +_serial_putc(const char c,const int port) +{ + if (c == '\n') + NS16550_putc(PORT, '\r'); + + NS16550_putc(PORT, c); +} + +void +_serial_putc_raw(const char c,const int port) +{ + NS16550_putc(PORT, c); +} + +void +_serial_puts (const char *s,const int port) +{ + while (*s) { + _serial_putc (*s++,port); + } +} + + +int +_serial_getc(const int port) +{ + return NS16550_getc(PORT); +} + +int +_serial_tstc(const int port) +{ + return NS16550_tstc(PORT); +} + +void +_serial_setbrg (const int port) +{ + int clock_divisor; + + clock_divisor = calc_divisor(PORT); + NS16550_reinit(PORT, clock_divisor); +} + +void +serial_putc(const char c) +{ + _serial_putc(c,CONFIG_CONS_INDEX); +} + +void +serial_putc_raw(const char c) +{ + _serial_putc_raw(c,CONFIG_CONS_INDEX); +} + +void +serial_puts(const char *s) +{ + _serial_puts(s,CONFIG_CONS_INDEX); +} + +int +serial_getc(void) +{ + return _serial_getc(CONFIG_CONS_INDEX); +} + +int +serial_tstc(void) +{ + return _serial_tstc(CONFIG_CONS_INDEX); +} + +void +serial_setbrg(void) +{ + _serial_setbrg(CONFIG_CONS_INDEX); +} + +#endif diff --git a/drivers/serial_max3100.c b/drivers/serial_max3100.c new file mode 100644 index 000000000..35c559698 --- /dev/null +++ b/drivers/serial_max3100.c @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2003 + * + * Pantelis Antoniou + * Intracom S.A. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_MAX3100_SERIAL + +DECLARE_GLOBAL_DATA_PTR; + +/**************************************************************/ + +/* convienient macros */ +#define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT) + +#define MAX3100_SPI_TXD(x) \ + do { \ + if (x) \ + MAX3100_SPI_TXD_PORT |= MAX3100_SPI_TXD_BIT; \ + else \ + MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \ + } while(0) + +#define MAX3100_SPI_CLK(x) \ + do { \ + if (x) \ + MAX3100_SPI_CLK_PORT |= MAX3100_SPI_CLK_BIT; \ + else \ + MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \ + } while(0) + +#define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT) + +#define MAX3100_CS(x) \ + do { \ + if (x) \ + MAX3100_CS_PORT |= MAX3100_CS_BIT; \ + else \ + MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \ + } while(0) + +/**************************************************************/ + +/* MAX3100 definitions */ + +#define MAX3100_WC (3 << 14) /* write configuration */ +#define MAX3100_RC (1 << 14) /* read configuration */ +#define MAX3100_WD (2 << 14) /* write data */ +#define MAX3100_RD (0 << 14) /* read data */ + +/* configuration register bits */ +#define MAX3100_FEN (1 << 13) /* FIFO enable */ +#define MAX3100_SHDN (1 << 12) /* shutdown bit */ +#define MAX3100_TM (1 << 11) /* T bit irq mask */ +#define MAX3100_RM (1 << 10) /* R bit irq mask */ +#define MAX3100_PM (1 << 9) /* P bit irq mask */ +#define MAX3100_RAM (1 << 8) /* mask for RA/FE bit */ +#define MAX3100_IR (1 << 7) /* IRDA timing mode */ +#define MAX3100_ST (1 << 6) /* transmit stop bit */ +#define MAX3100_PE (1 << 5) /* parity enable bit */ +#define MAX3100_L (1 << 4) /* Length bit */ +#define MAX3100_B_MASK (0x000F) /* baud rate bits mask */ +#define MAX3100_B(x) ((x) & 0x000F) /* baud rate select bits */ + +/* data register bits (write) */ +#define MAX3100_TE (1 << 10) /* transmit enable bit (active low) */ +#define MAX3100_RTS (1 << 9) /* request-to-send bit (inverted ~RTS pin) */ + +/* data register bits (read) */ +#define MAX3100_RA (1 << 10) /* receiver activity when in shutdown mode */ +#define MAX3100_FE (1 << 10) /* framing error when in normal mode */ +#define MAX3100_CTS (1 << 9) /* clear-to-send bit (inverted ~CTS pin) */ + +/* data register bits (both directions) */ +#define MAX3100_R (1 << 15) /* receive bit */ +#define MAX3100_T (1 << 14) /* transmit bit */ +#define MAX3100_P (1 << 8) /* parity bit */ +#define MAX3100_D_MASK 0x00FF /* data bits mask */ +#define MAX3100_D(x) ((x) & 0x00FF) /* data bits */ + +/* these definitions are valid only for fOSC = 3.6864MHz */ +#define MAX3100_B_230400 MAX3100_B(0) +#define MAX3100_B_115200 MAX3100_B(1) +#define MAX3100_B_57600 MAX3100_B(2) +#define MAX3100_B_38400 MAX3100_B(9) +#define MAX3100_B_19200 MAX3100_B(10) +#define MAX3100_B_9600 MAX3100_B(11) +#define MAX3100_B_4800 MAX3100_B(12) +#define MAX3100_B_2400 MAX3100_B(13) +#define MAX3100_B_1200 MAX3100_B(14) +#define MAX3100_B_600 MAX3100_B(15) + +/**************************************************************/ + +static inline unsigned int max3100_transfer(unsigned int val) +{ + unsigned int rx; + int b; + + MAX3100_SPI_CLK(0); + MAX3100_CS(0); + + rx = 0; b = 16; + while (--b >= 0) { + MAX3100_SPI_TXD(val & 0x8000); + val <<= 1; + MAX3100_SPI_CLK_TOGGLE(); + udelay(1); + rx <<= 1; + if (MAX3100_SPI_RXD()) + rx |= 1; + MAX3100_SPI_CLK_TOGGLE(); + udelay(1); + } + + MAX3100_SPI_CLK(1); + MAX3100_CS(1); + + return rx; +} + +/**************************************************************/ + +/* must be power of 2 */ +#define RXFIFO_SZ 16 + +static int rxfifo_cnt; +static int rxfifo_in; +static int rxfifo_out; +static unsigned char rxfifo_buf[16]; + +static void max3100_putc(int c) +{ + unsigned int rx; + + while (((rx = max3100_transfer(MAX3100_RC)) & MAX3100_T) == 0) + WATCHDOG_RESET(); + + rx = max3100_transfer(MAX3100_WD | (c & 0xff)); + if ((rx & MAX3100_RD) != 0 && rxfifo_cnt < RXFIFO_SZ) { + rxfifo_cnt++; + rxfifo_buf[rxfifo_in++] = rx & 0xff; + rxfifo_in &= RXFIFO_SZ - 1; + } +} + +static int max3100_getc(void) +{ + int c; + unsigned int rx; + + while (rxfifo_cnt == 0) { + rx = max3100_transfer(MAX3100_RD); + if ((rx & MAX3100_R) != 0) { + do { + rxfifo_cnt++; + rxfifo_buf[rxfifo_in++] = rx & 0xff; + rxfifo_in &= RXFIFO_SZ - 1; + + if (rxfifo_cnt >= RXFIFO_SZ) + break; + } while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0); + } + WATCHDOG_RESET(); + } + + rxfifo_cnt--; + c = rxfifo_buf[rxfifo_out++]; + rxfifo_out &= RXFIFO_SZ - 1; + return c; +} + +static int max3100_tstc(void) +{ + unsigned int rx; + + if (rxfifo_cnt > 0) + return 1; + + rx = max3100_transfer(MAX3100_RD); + if ((rx & MAX3100_R) == 0) + return 0; + + do { + rxfifo_cnt++; + rxfifo_buf[rxfifo_in++] = rx & 0xff; + rxfifo_in &= RXFIFO_SZ - 1; + + if (rxfifo_cnt >= RXFIFO_SZ) + break; + } while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0); + + return 1; +} + +int serial_init(void) +{ + unsigned int wconf, rconf; + int i; + + wconf = 0; + + /* Set baud rate */ + switch (gd->baudrate) { + case 1200: + wconf = MAX3100_B_1200; + break; + case 2400: + wconf = MAX3100_B_2400; + break; + case 4800: + wconf = MAX3100_B_4800; + break; + case 9600: + wconf = MAX3100_B_9600; + break; + case 19200: + wconf = MAX3100_B_19200; + break; + case 38400: + wconf = MAX3100_B_38400; + break; + case 57600: + wconf = MAX3100_B_57600; + break; + default: + case 115200: + wconf = MAX3100_B_115200; + break; + case 230400: + wconf = MAX3100_B_230400; + break; + } + + /* try for 10ms, with a 100us gap */ + for (i = 0; i < 10000; i += 100) { + + max3100_transfer(MAX3100_WC | wconf); + rconf = max3100_transfer(MAX3100_RC) & 0x3fff; + + if (rconf == wconf) + break; + udelay(100); + } + + rxfifo_in = rxfifo_out = rxfifo_cnt = 0; + + return (0); +} + +void serial_putc(const char c) +{ + if (c == '\n') + max3100_putc('\r'); + + max3100_putc(c); +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc (*s++); +} + +int serial_getc(void) +{ + return max3100_getc(); +} + +int serial_tstc(void) +{ + return max3100_tstc(); +} + +/* XXX WTF? */ +void serial_setbrg(void) +{ +} + +#endif diff --git a/drivers/serial_pl010.c b/drivers/serial_pl010.c new file mode 100644 index 000000000..417b6aeda --- /dev/null +++ b/drivers/serial_pl010.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ +/* Should be fairly simple to make it work with the PL010 as well */ + +#include + +#ifdef CFG_PL010_SERIAL + +#include "serial_pl011.h" + +#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(volatile unsigned int *)(addr)) + +/* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 */ +#define CONSOLE_PORT CONFIG_CONS_INDEX +#define baudRate CONFIG_BAUDRATE +static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +#define NUM_PORTS (sizeof(port)/sizeof(port[0])) + + +static void pl010_putc (int portnum, char c); +static int pl010_getc (int portnum); +static int pl010_tstc (int portnum); + + +int serial_init (void) +{ + unsigned int divisor; + + /* + ** First, disable everything. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, 0x0); + + /* + ** Set baud rate + ** + */ + switch (baudRate) { + case 9600: + divisor = UART_PL010_BAUD_9600; + break; + + case 19200: + divisor = UART_PL010_BAUD_9600; + break; + + case 38400: + divisor = UART_PL010_BAUD_38400; + break; + + case 57600: + divisor = UART_PL010_BAUD_57600; + break; + + case 115200: + divisor = UART_PL010_BAUD_115200; + break; + + default: + divisor = UART_PL010_BAUD_38400; + } + + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRM, + ((divisor & 0xf00) >> 8)); + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRL, (divisor & 0xff)); + + /* + ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_LCRH, + (UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN)); + + /* + ** Finally, enable the UART + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL010_CR, (UART_PL010_CR_UARTEN)); + + return (0); +} + +void serial_putc (const char c) +{ + if (c == '\n') + pl010_putc (CONSOLE_PORT, '\r'); + + pl010_putc (CONSOLE_PORT, c); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + return pl010_getc (CONSOLE_PORT); +} + +int serial_tstc (void) +{ + return pl010_tstc (CONSOLE_PORT); +} + +void serial_setbrg (void) +{ +} + +static void pl010_putc (int portnum, char c) +{ + /* Wait until there is space in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); + + /* Send the character */ + IO_WRITE (port[portnum] + UART_PL01x_DR, c); +} + +static int pl010_getc (int portnum) +{ + unsigned int data; + + /* Wait until there is data in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); + + data = IO_READ (port[portnum] + UART_PL01x_DR); + + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + return -1; + } + + return (int) data; +} + +static int pl010_tstc (int portnum) +{ + return !(IO_READ (port[portnum] + UART_PL01x_FR) & + UART_PL01x_FR_RXFE); +} + +#endif diff --git a/drivers/serial_pl011.c b/drivers/serial_pl011.c new file mode 100644 index 000000000..4d35fe5e9 --- /dev/null +++ b/drivers/serial_pl011.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ +/* Should be fairly simple to make it work with the PL010 as well */ + +#include + +#ifdef CFG_PL011_SERIAL + +#include "serial_pl011.h" + +#define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) +#define IO_READ(addr) (*(volatile unsigned int *)(addr)) + +/* + * IntegratorCP has two UARTs, use the first one, at 38400-8-N-1 + * Versatile PB has four UARTs. + */ + +#define CONSOLE_PORT CONFIG_CONS_INDEX +#define baudRate CONFIG_BAUDRATE +static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +#define NUM_PORTS (sizeof(port)/sizeof(port[0])) + +static void pl011_putc (int portnum, char c); +static int pl011_getc (int portnum); +static int pl011_tstc (int portnum); + + +int serial_init (void) +{ + unsigned int temp; + unsigned int divider; + unsigned int remainder; + unsigned int fraction; + + /* + ** First, disable everything. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, 0x0); + + /* + ** Set baud rate + ** + ** IBRD = UART_CLK / (16 * BAUD_RATE) + ** FBRD = ROUND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) + */ + temp = 16 * baudRate; + divider = CONFIG_PL011_CLOCK / temp; + remainder = CONFIG_PL011_CLOCK % temp; + temp = (8 * remainder) / baudRate; + fraction = (temp >> 1) + (temp & 1); + + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_IBRD, divider); + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_FBRD, fraction); + + /* + ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled. + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_LCRH, + (UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN)); + + /* + ** Finally, enable the UART + */ + IO_WRITE (port[CONSOLE_PORT] + UART_PL011_CR, + (UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | + UART_PL011_CR_RXE)); + + return 0; +} + +void serial_putc (const char c) +{ + if (c == '\n') + pl011_putc (CONSOLE_PORT, '\r'); + + pl011_putc (CONSOLE_PORT, c); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + return pl011_getc (CONSOLE_PORT); +} + +int serial_tstc (void) +{ + return pl011_tstc (CONSOLE_PORT); +} + +void serial_setbrg (void) +{ +} + +static void pl011_putc (int portnum, char c) +{ + /* Wait until there is space in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF); + + /* Send the character */ + IO_WRITE (port[portnum] + UART_PL01x_DR, c); +} + +static int pl011_getc (int portnum) +{ + unsigned int data; + + /* Wait until there is data in the FIFO */ + while (IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); + + data = IO_READ (port[portnum] + UART_PL01x_DR); + + /* Check for an error flag */ + if (data & 0xFFFFFF00) { + /* Clear the error */ + IO_WRITE (port[portnum] + UART_PL01x_ECR, 0xFFFFFFFF); + return -1; + } + + return (int) data; +} + +static int pl011_tstc (int portnum) +{ + return !(IO_READ (port[portnum] + UART_PL01x_FR) & + UART_PL01x_FR_RXFE); +} + +#endif diff --git a/drivers/serial_pl011.h b/drivers/serial_pl011.h new file mode 100644 index 000000000..5f20fdd10 --- /dev/null +++ b/drivers/serial_pl011.h @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2003, 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * ARM PrimeCell UART's (PL010 & PL011) + * ------------------------------------ + * + * Definitions common to both PL010 & PL011 + * + */ +#define UART_PL01x_DR 0x00 /* Data read or written from the interface. */ +#define UART_PL01x_RSR 0x04 /* Receive status register (Read). */ +#define UART_PL01x_ECR 0x04 /* Error clear register (Write). */ +#define UART_PL01x_FR 0x18 /* Flag register (Read only). */ + +#define UART_PL01x_RSR_OE 0x08 +#define UART_PL01x_RSR_BE 0x04 +#define UART_PL01x_RSR_PE 0x02 +#define UART_PL01x_RSR_FE 0x01 + +#define UART_PL01x_FR_TXFE 0x80 +#define UART_PL01x_FR_RXFF 0x40 +#define UART_PL01x_FR_TXFF 0x20 +#define UART_PL01x_FR_RXFE 0x10 +#define UART_PL01x_FR_BUSY 0x08 +#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY) + +/* + * PL010 definitions + * + */ +#define UART_PL010_LCRH 0x08 /* Line control register, high byte. */ +#define UART_PL010_LCRM 0x0C /* Line control register, middle byte. */ +#define UART_PL010_LCRL 0x10 /* Line control register, low byte. */ +#define UART_PL010_CR 0x14 /* Control register. */ +#define UART_PL010_IIR 0x1C /* Interrupt indentification register (Read). */ +#define UART_PL010_ICR 0x1C /* Interrupt clear register (Write). */ +#define UART_PL010_ILPR 0x20 /* IrDA low power counter register. */ + +#define UART_PL010_CR_LPE (1 << 7) +#define UART_PL010_CR_RTIE (1 << 6) +#define UART_PL010_CR_TIE (1 << 5) +#define UART_PL010_CR_RIE (1 << 4) +#define UART_PL010_CR_MSIE (1 << 3) +#define UART_PL010_CR_IIRLP (1 << 2) +#define UART_PL010_CR_SIREN (1 << 1) +#define UART_PL010_CR_UARTEN (1 << 0) + +#define UART_PL010_LCRH_WLEN_8 (3 << 5) +#define UART_PL010_LCRH_WLEN_7 (2 << 5) +#define UART_PL010_LCRH_WLEN_6 (1 << 5) +#define UART_PL010_LCRH_WLEN_5 (0 << 5) +#define UART_PL010_LCRH_FEN (1 << 4) +#define UART_PL010_LCRH_STP2 (1 << 3) +#define UART_PL010_LCRH_EPS (1 << 2) +#define UART_PL010_LCRH_PEN (1 << 1) +#define UART_PL010_LCRH_BRK (1 << 0) + + +#define UART_PL010_BAUD_460800 1 +#define UART_PL010_BAUD_230400 3 +#define UART_PL010_BAUD_115200 7 +#define UART_PL010_BAUD_57600 15 +#define UART_PL010_BAUD_38400 23 +#define UART_PL010_BAUD_19200 47 +#define UART_PL010_BAUD_14400 63 +#define UART_PL010_BAUD_9600 95 +#define UART_PL010_BAUD_4800 191 +#define UART_PL010_BAUD_2400 383 +#define UART_PL010_BAUD_1200 767 +/* + * PL011 definitions + * + */ +#define UART_PL011_IBRD 0x24 +#define UART_PL011_FBRD 0x28 +#define UART_PL011_LCRH 0x2C +#define UART_PL011_CR 0x30 +#define UART_PL011_IMSC 0x38 +#define UART_PL011_PERIPH_ID0 0xFE0 + +#define UART_PL011_LCRH_SPS (1 << 7) +#define UART_PL011_LCRH_WLEN_8 (3 << 5) +#define UART_PL011_LCRH_WLEN_7 (2 << 5) +#define UART_PL011_LCRH_WLEN_6 (1 << 5) +#define UART_PL011_LCRH_WLEN_5 (0 << 5) +#define UART_PL011_LCRH_FEN (1 << 4) +#define UART_PL011_LCRH_STP2 (1 << 3) +#define UART_PL011_LCRH_EPS (1 << 2) +#define UART_PL011_LCRH_PEN (1 << 1) +#define UART_PL011_LCRH_BRK (1 << 0) + +#define UART_PL011_CR_CTSEN (1 << 15) +#define UART_PL011_CR_RTSEN (1 << 14) +#define UART_PL011_CR_OUT2 (1 << 13) +#define UART_PL011_CR_OUT1 (1 << 12) +#define UART_PL011_CR_RTS (1 << 11) +#define UART_PL011_CR_DTR (1 << 10) +#define UART_PL011_CR_RXE (1 << 9) +#define UART_PL011_CR_TXE (1 << 8) +#define UART_PL011_CR_LPE (1 << 7) +#define UART_PL011_CR_IIRLP (1 << 2) +#define UART_PL011_CR_SIREN (1 << 1) +#define UART_PL011_CR_UARTEN (1 << 0) + +#define UART_PL011_IMSC_OEIM (1 << 10) +#define UART_PL011_IMSC_BEIM (1 << 9) +#define UART_PL011_IMSC_PEIM (1 << 8) +#define UART_PL011_IMSC_FEIM (1 << 7) +#define UART_PL011_IMSC_RTIM (1 << 6) +#define UART_PL011_IMSC_TXIM (1 << 5) +#define UART_PL011_IMSC_RXIM (1 << 4) +#define UART_PL011_IMSC_DSRMIM (1 << 3) +#define UART_PL011_IMSC_DCDMIM (1 << 2) +#define UART_PL011_IMSC_CTSMIM (1 << 1) +#define UART_PL011_IMSC_RIMIM (1 << 0) diff --git a/drivers/serial_xuartlite.c b/drivers/serial_xuartlite.c new file mode 100644 index 000000000..ed59abea8 --- /dev/null +++ b/drivers/serial_xuartlite.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_MICROBLAZE + +#include + +/* FIXME: we should convert these to in32 and out32 */ +#define IO_WORD(offset) (*(volatile unsigned long *)(offset)) +#define IO_SERIAL(offset) IO_WORD(CONFIG_SERIAL_BASE + (offset)) + +#define IO_SERIAL_RX_FIFO IO_SERIAL(XUL_RX_FIFO_OFFSET) +#define IO_SERIAL_TX_FIFO IO_SERIAL(XUL_TX_FIFO_OFFSET) +#define IO_SERIAL_STATUS IO_SERIAL(XUL_STATUS_REG_OFFSET) +#define IO_SERIAL_CONTROL IO_SERIAL(XUL_CONTROL_REG_OFFSET) + +int serial_init(void) +{ + /* FIXME: Nothing for now. We should initialize fifo, etc */ + return 0; +} + +void serial_setbrg(void) +{ + /* FIXME: what's this for? */ +} + +void serial_putc(const char c) +{ + if (c == '\n') serial_putc('\r'); + while (IO_SERIAL_STATUS & XUL_SR_TX_FIFO_FULL); + IO_SERIAL_TX_FIFO = (unsigned char) (c & 0xff); +} + +void serial_puts(const char * s) +{ + while (*s) { + serial_putc(*s++); + } +} + +int serial_getc(void) +{ + while (!(IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA)); + return IO_SERIAL_RX_FIFO & 0xff; +} + +int serial_tstc(void) +{ + return (IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA); +} + +#endif /* CONFIG_MICROBLZE */ diff --git a/drivers/sk98lin/Makefile b/drivers/sk98lin/Makefile new file mode 100644 index 000000000..8ee0e216c --- /dev/null +++ b/drivers/sk98lin/Makefile @@ -0,0 +1,101 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# File: drivers/sk98lin/Makefile +# +# Makefile for the SysKonnect SK-98xx device driver. +# +include $(TOPDIR)/config.mk + +LIB := libsk98lin.a + +OBJS := skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o skgesirq.o \ + ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \ + skxmac2.o skcsum.o #skproc.o + +OBJS += uboot_skb.o uboot_drv.o + +# DBGDEF = \ +# -DDEBUG + +ifdef DEBUG +DBGDEF += \ +-DSK_DEBUG_CHKMOD=0x00000000L \ +-DSK_DEBUG_CHKCAT=0x00000000L +endif + + +# **** possible debug modules for SK_DEBUG_CHKMOD ***************** +# SK_DBGMOD_MERR 0x00000001L /* general module error indication */ +# SK_DBGMOD_HWM 0x00000002L /* Hardware init module */ +# SK_DBGMOD_RLMT 0x00000004L /* RLMT module */ +# SK_DBGMOD_VPD 0x00000008L /* VPD module */ +# SK_DBGMOD_I2C 0x00000010L /* I2C module */ +# SK_DBGMOD_PNMI 0x00000020L /* PNMI module */ +# SK_DBGMOD_CSUM 0x00000040L /* CSUM module */ +# SK_DBGMOD_ADDR 0x00000080L /* ADDR module */ +# SK_DBGMOD_DRV 0x00010000L /* DRV module */ + +# **** possible debug categories for SK_DEBUG_CHKCAT ************** +# *** common modules *** +# SK_DBGCAT_INIT 0x00000001L module/driver initialization +# SK_DBGCAT_CTRL 0x00000002L controlling: add/rmv MCA/MAC and other controls (IOCTL) +# SK_DBGCAT_ERR 0x00000004L error handling paths +# SK_DBGCAT_TX 0x00000008L transmit path +# SK_DBGCAT_RX 0x00000010L receive path +# SK_DBGCAT_IRQ 0x00000020L general IRQ handling +# SK_DBGCAT_QUEUE 0x00000040L any queue management +# SK_DBGCAT_DUMP 0x00000080L large data output e.g. hex dump +# SK_DBGCAT_FATAL 0x00000100L large data output e.g. hex dump + +# *** driver (file skge.c) *** +# SK_DBGCAT_DRV_ENTRY 0x00010000 entry points +# SK_DBGCAT_DRV_??? 0x00020000 not used +# SK_DBGCAT_DRV_MCA 0x00040000 multicast +# SK_DBGCAT_DRV_TX_PROGRESS 0x00080000 tx path +# SK_DBGCAT_DRV_RX_PROGRESS 0x00100000 rx path +# SK_DBGCAT_DRV_PROGRESS 0x00200000 general runtime +# SK_DBGCAT_DRV_??? 0x00400000 not used +# SK_DBGCAT_DRV_PROM 0x00800000 promiscuous mode +# SK_DBGCAT_DRV_TX_FRAME 0x01000000 display tx frames +# SK_DBGCAT_DRV_ERROR 0x02000000 error conditions +# SK_DBGCAT_DRV_INT_SRC 0x04000000 interrupts sources +# SK_DBGCAT_DRV_EVENT 0x08000000 driver events + +EXTRA_CFLAGS += -I. -DSK_USE_CSUM $(DBGDEF) + +CFLAGS += $(EXTRA_CFLAGS) + + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/drivers/sk98lin/h/lm80.h b/drivers/sk98lin/h/lm80.h new file mode 100644 index 000000000..981a4cab0 --- /dev/null +++ b/drivers/sk98lin/h/lm80.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * + * Name: lm80.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.4 $ + * Date: $Date: 2002/04/25 11:04:10 $ + * Purpose: Contains all defines for the LM80 Chip + * (National Semiconductor). + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: lm80.h,v $ + * Revision 1.4 2002/04/25 11:04:10 rschmidt + * Editorial changes + * + * Revision 1.3 1999/11/22 13:41:19 cgoos + * Changed license header to GPL. + * + * Revision 1.2 1999/03/12 13:26:51 malthoff + * remove __STDC__. + * + * Revision 1.1 1998/06/19 09:28:31 malthoff + * created. + * + * + ******************************************************************************/ + +#ifndef __INC_LM80_H +#define __INC_LM80_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines ********************************************************************/ + +/* + * LM80 register definition + * + * All registers are 8 bit wide + */ +#define LM80_CFG 0x00 /* Configuration Register */ +#define LM80_ISRC_1 0x01 /* Interrupt Status Register 1 */ +#define LM80_ISRC_2 0x02 /* Interrupt Status Register 2 */ +#define LM80_IMSK_1 0x03 /* Interrupt Mask Register 1 */ +#define LM80_IMSK_2 0x04 /* Interrupt Mask Register 2 */ +#define LM80_FAN_CTRL 0x05 /* Fan Devisor/RST#/OS# Register */ +#define LM80_TEMP_CTRL 0x06 /* OS# Config, Temp Res. Reg */ + /* 0x07 - 0x1f reserved */ + /* current values */ +#define LM80_VT0_IN 0x20 /* current Voltage 0 value */ +#define LM80_VT1_IN 0x21 /* current Voltage 1 value */ +#define LM80_VT2_IN 0x22 /* current Voltage 2 value */ +#define LM80_VT3_IN 0x23 /* current Voltage 3 value */ +#define LM80_VT4_IN 0x24 /* current Voltage 4 value */ +#define LM80_VT5_IN 0x25 /* current Voltage 5 value */ +#define LM80_VT6_IN 0x26 /* current Voltage 6 value */ +#define LM80_TEMP_IN 0x27 /* current Temperature value */ +#define LM80_FAN1_IN 0x28 /* current Fan 1 count */ +#define LM80_FAN2_IN 0x29 /* current Fan 2 count */ + /* limit values */ +#define LM80_VT0_HIGH_LIM 0x2a /* high limit val for Voltage 0 */ +#define LM80_VT0_LOW_LIM 0x2b /* low limit val for Voltage 0 */ +#define LM80_VT1_HIGH_LIM 0x2c /* high limit val for Voltage 1 */ +#define LM80_VT1_LOW_LIM 0x2d /* low limit val for Voltage 1 */ +#define LM80_VT2_HIGH_LIM 0x2e /* high limit val for Voltage 2 */ +#define LM80_VT2_LOW_LIM 0x2f /* low limit val for Voltage 2 */ +#define LM80_VT3_HIGH_LIM 0x30 /* high limit val for Voltage 3 */ +#define LM80_VT3_LOW_LIM 0x31 /* low limit val for Voltage 3 */ +#define LM80_VT4_HIGH_LIM 0x32 /* high limit val for Voltage 4 */ +#define LM80_VT4_LOW_LIM 0x33 /* low limit val for Voltage 4 */ +#define LM80_VT5_HIGH_LIM 0x34 /* high limit val for Voltage 5 */ +#define LM80_VT5_LOW_LIM 0x35 /* low limit val for Voltage 5 */ +#define LM80_VT6_HIGH_LIM 0x36 /* high limit val for Voltage 6 */ +#define LM80_VT6_LOW_LIM 0x37 /* low limit val for Voltage 6 */ +#define LM80_THOT_LIM_UP 0x38 /* hot temperature limit (high) */ +#define LM80_THOT_LIM_LO 0x39 /* hot temperature limit (low) */ +#define LM80_TOS_LIM_UP 0x3a /* OS temperature limit (high) */ +#define LM80_TOS_LIM_LO 0x3b /* OS temperature limit (low) */ +#define LM80_FAN1_COUNT_LIM 0x3c /* Fan 1 count limit (high) */ +#define LM80_FAN2_COUNT_LIM 0x3d /* Fan 2 count limit (low) */ + /* 0x3e - 0x3f reserved */ + +/* + * LM80 bit definitions + */ + +/* LM80_CFG Configuration Register */ +#define LM80_CFG_START (1<<0) /* start monitoring operation */ +#define LM80_CFG_INT_ENA (1<<1) /* enables the INT# Interrupt output */ +#define LM80_CFG_INT_POL (1<<2) /* INT# pol: 0 act low, 1 act high */ +#define LM80_CFG_INT_CLR (1<<3) /* disables INT#/RST_OUT#/OS# outputs */ +#define LM80_CFG_RESET (1<<4) /* signals a reset */ +#define LM80_CFG_CHASS_CLR (1<<5) /* clears Chassis Intrusion (CI) pin */ +#define LM80_CFG_GPO (1<<6) /* drives the GPO# pin */ +#define LM80_CFG_INIT (1<<7) /* restore power on defaults */ + +/* LM80_ISRC_1 Interrupt Status Register 1 */ +/* LM80_IMSK_1 Interrupt Mask Register 1 */ +#define LM80_IS_VT0 (1<<0) /* limit exceeded for Voltage 0 */ +#define LM80_IS_VT1 (1<<1) /* limit exceeded for Voltage 1 */ +#define LM80_IS_VT2 (1<<2) /* limit exceeded for Voltage 2 */ +#define LM80_IS_VT3 (1<<3) /* limit exceeded for Voltage 3 */ +#define LM80_IS_VT4 (1<<4) /* limit exceeded for Voltage 4 */ +#define LM80_IS_VT5 (1<<5) /* limit exceeded for Voltage 5 */ +#define LM80_IS_VT6 (1<<6) /* limit exceeded for Voltage 6 */ +#define LM80_IS_INT_IN (1<<7) /* state of INT_IN# */ + +/* LM80_ISRC_2 Interrupt Status Register 2 */ +/* LM80_IMSK_2 Interrupt Mask Register 2 */ +#define LM80_IS_TEMP (1<<0) /* HOT temperature limit exceeded */ +#define LM80_IS_BTI (1<<1) /* state of BTI# pin */ +#define LM80_IS_FAN1 (1<<2) /* count limit exceeded for Fan 1 */ +#define LM80_IS_FAN2 (1<<3) /* count limit exceeded for Fan 2 */ +#define LM80_IS_CI (1<<4) /* Chassis Intrusion occured */ +#define LM80_IS_OS (1<<5) /* OS temperature limit exceeded */ + /* bit 6 and 7 are reserved in LM80_ISRC_2 */ +#define LM80_IS_HT_IRQ_MD (1<<6) /* Hot temperature interrupt mode */ +#define LM80_IS_OT_IRQ_MD (1<<7) /* OS temperature interrupt mode */ + +/* LM80_FAN_CTRL Fan Devisor/RST#/OS# Register */ +#define LM80_FAN1_MD_SEL (1<<0) /* Fan 1 mode select */ +#define LM80_FAN2_MD_SEL (1<<1) /* Fan 2 mode select */ +#define LM80_FAN1_PRM_CTL (3<<2) /* Fan 1 speed control */ +#define LM80_FAN2_PRM_CTL (3<<4) /* Fan 2 speed control */ +#define LM80_FAN_OS_ENA (1<<6) /* enable OS mode on RST_OUT#/OS# pins*/ +#define LM80_FAN_RST_ENA (1<<7) /* sets RST_OUT#/OS# pins in RST mode */ + +/* LM80_TEMP_CTRL OS# Config, Temp Res. Reg */ +#define LM80_TEMP_OS_STAT (1<<0) /* mirrors the state of RST_OUT#/OS# */ +#define LM80_TEMP_OS_POL (1<<1) /* select OS# polarity */ +#define LM80_TEMP_OS_MODE (1<<2) /* selects Interrupt mode */ +#define LM80_TEMP_RES (1<<3) /* selects 9 or 11 bit temp resulution*/ +#define LM80_TEMP_LSB (0xf<<4)/* 4 LSBs of 11 bit temp data */ +#define LM80_TEMP_LSB_9 (1<<7) /* LSB of 9 bit temperature data */ + + /* 0x07 - 0x1f reserved */ +/* LM80_VT0_IN current Voltage 0 value */ +/* LM80_VT1_IN current Voltage 1 value */ +/* LM80_VT2_IN current Voltage 2 value */ +/* LM80_VT3_IN current Voltage 3 value */ +/* LM80_VT4_IN current Voltage 4 value */ +/* LM80_VT5_IN current Voltage 5 value */ +/* LM80_VT6_IN current Voltage 6 value */ +/* LM80_TEMP_IN current temperature value */ +/* LM80_FAN1_IN current Fan 1 count */ +/* LM80_FAN2_IN current Fan 2 count */ +/* LM80_VT0_HIGH_LIM high limit val for Voltage 0 */ +/* LM80_VT0_LOW_LIM low limit val for Voltage 0 */ +/* LM80_VT1_HIGH_LIM high limit val for Voltage 1 */ +/* LM80_VT1_LOW_LIM low limit val for Voltage 1 */ +/* LM80_VT2_HIGH_LIM high limit val for Voltage 2 */ +/* LM80_VT2_LOW_LIM low limit val for Voltage 2 */ +/* LM80_VT3_HIGH_LIM high limit val for Voltage 3 */ +/* LM80_VT3_LOW_LIM low limit val for Voltage 3 */ +/* LM80_VT4_HIGH_LIM high limit val for Voltage 4 */ +/* LM80_VT4_LOW_LIM low limit val for Voltage 4 */ +/* LM80_VT5_HIGH_LIM high limit val for Voltage 5 */ +/* LM80_VT5_LOW_LIM low limit val for Voltage 5 */ +/* LM80_VT6_HIGH_LIM high limit val for Voltage 6 */ +/* LM80_VT6_LOW_LIM low limit val for Voltage 6 */ +/* LM80_THOT_LIM_UP hot temperature limit (high) */ +/* LM80_THOT_LIM_LO hot temperature limit (low) */ +/* LM80_TOS_LIM_UP OS temperature limit (high) */ +/* LM80_TOS_LIM_LO OS temperature limit (low) */ +/* LM80_FAN1_COUNT_LIM Fan 1 count limit (high) */ +/* LM80_FAN2_COUNT_LIM Fan 2 count limit (low) */ + /* 0x3e - 0x3f reserved */ + +#define LM80_ADDR 0x28 /* LM80 default addr */ + +/* typedefs *******************************************************************/ + + +/* function prototypes ********************************************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_LM80_H */ diff --git a/drivers/sk98lin/h/skaddr.h b/drivers/sk98lin/h/skaddr.h new file mode 100644 index 000000000..711f873e7 --- /dev/null +++ b/drivers/sk98lin/h/skaddr.h @@ -0,0 +1,425 @@ +/****************************************************************************** + * + * Name: skaddr.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.26 $ + * Date: $Date: 2002/11/15 07:24:42 $ + * Purpose: Header file for Address Management (MC, UC, Prom). + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skaddr.h,v $ + * Revision 1.26 2002/11/15 07:24:42 tschilli + * SK_ADDR_EQUAL macro fixed. + * + * Revision 1.25 2002/06/10 13:55:18 tschilli + * Changes for handling YUKON. + * All changes are internally and not visible to the programmer + * using this module. + * + * Revision 1.24 2001/01/22 13:41:34 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.23 2000/08/10 11:27:50 rassmann + * Editorial changes. + * Preserving 32-bit alignment in structs for the adapter context. + * + * Revision 1.22 2000/08/07 11:10:40 rassmann + * Editorial changes. + * + * Revision 1.21 2000/05/04 09:39:59 rassmann + * Editorial changes. + * Corrected multicast address hashing. + * + * Revision 1.20 1999/11/22 13:46:14 cgoos + * Changed license header to GPL. + * Allowing overwrite for SK_ADDR_EQUAL. + * + * Revision 1.19 1999/05/28 10:56:07 rassmann + * Editorial changes. + * + * Revision 1.18 1999/04/06 17:22:04 rassmann + * Added private "ActivePort". + * + * Revision 1.17 1999/01/14 16:18:19 rassmann + * Corrected multicast initialization. + * + * Revision 1.16 1999/01/04 10:30:36 rassmann + * SkAddrOverride only possible after SK_INIT_IO phase. + * + * Revision 1.15 1998/12/29 13:13:11 rassmann + * An address override is now preserved in the SK_INIT_IO phase. + * All functions return an int now. + * Extended parameter checking. + * + * Revision 1.14 1998/11/24 12:39:45 rassmann + * Reserved multicast entry for BPDU address. + * 13 multicast entries left for protocol. + * + * Revision 1.13 1998/11/13 17:24:32 rassmann + * Changed return value of SkAddrOverride to int. + * + * Revision 1.12 1998/11/13 16:56:19 rassmann + * Added macro SK_ADDR_COMPARE. + * Changed return type of SkAddrOverride to SK_BOOL. + * + * Revision 1.11 1998/10/28 18:16:35 rassmann + * Avoiding I/Os before SK_INIT_RUN level. + * Aligning InexactFilter. + * + * Revision 1.10 1998/10/22 11:39:10 rassmann + * Corrected signed/unsigned mismatches. + * + * Revision 1.9 1998/10/15 15:15:49 rassmann + * Changed Flags Parameters from SK_U8 to int. + * Checked with lint. + * + * Revision 1.8 1998/09/24 19:15:12 rassmann + * Code cleanup. + * + * Revision 1.7 1998/09/18 20:22:13 rassmann + * Added HW access. + * + * Revision 1.6 1998/09/04 19:40:20 rassmann + * Interface enhancements. + * + * Revision 1.5 1998/09/04 12:40:57 rassmann + * Interface cleanup. + * + * Revision 1.4 1998/09/04 12:14:13 rassmann + * Interface cleanup. + * + * Revision 1.3 1998/09/02 16:56:40 rassmann + * Updated interface. + * + * Revision 1.2 1998/08/27 14:26:09 rassmann + * Updated interface. + * + * Revision 1.1 1998/08/21 08:31:08 rassmann + * First public version. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This module is intended to manage multicast addresses and promiscuous mode + * on GEnesis adapters. + * + * Include File Hierarchy: + * + * "skdrv1st.h" + * ... + * "sktypes.h" + * "skqueue.h" + * "skaddr.h" + * ... + * "skdrv2nd.h" + * + ******************************************************************************/ + +#ifndef __INC_SKADDR_H +#define __INC_SKADDR_H + +#ifdef __cplusplus +#error C++ is not yet supported. +extern "C" { +#endif /* cplusplus */ + +/* defines ********************************************************************/ + +#define SK_MAC_ADDR_LEN 6 /* Length of MAC address. */ +#define SK_MAX_ADDRS 14 /* #Addrs for exact match. */ + +/* ----- Common return values ----- */ + +#define SK_ADDR_SUCCESS 0 /* Function returned successfully. */ +#define SK_ADDR_ILLEGAL_PORT 100 /* Port number too high. */ +#define SK_ADDR_TOO_EARLY 101 /* Function called too early. */ + +/* ----- Clear/Add flag bits ----- */ + +#define SK_ADDR_PERMANENT 1 /* RLMT Address */ + +/* ----- Additional Clear flag bits ----- */ + +#define SK_MC_SW_ONLY 2 /* Do not update HW when clearing. */ + +/* ----- Override flag bits ----- */ + +#define SK_ADDR_LOGICAL_ADDRESS 0 +#define SK_ADDR_VIRTUAL_ADDRESS (SK_ADDR_LOGICAL_ADDRESS) /* old */ +#define SK_ADDR_PHYSICAL_ADDRESS 1 +#define SK_ADDR_CLEAR_LOGICAL 2 +#define SK_ADDR_SET_LOGICAL 4 + +/* ----- Override return values ----- */ + +#define SK_ADDR_OVERRIDE_SUCCESS (SK_ADDR_SUCCESS) +#define SK_ADDR_DUPLICATE_ADDRESS 1 +#define SK_ADDR_MULTICAST_ADDRESS 2 + +/* ----- Partitioning of excact match table ----- */ + +#define SK_ADDR_EXACT_MATCHES 16 /* #Exact match entries. */ + +#define SK_ADDR_FIRST_MATCH_RLMT 1 +#define SK_ADDR_LAST_MATCH_RLMT 2 +#define SK_ADDR_FIRST_MATCH_DRV 3 +#define SK_ADDR_LAST_MATCH_DRV (SK_ADDR_EXACT_MATCHES - 1) + +/* ----- SkAddrMcAdd/SkAddrMcUpdate return values ----- */ + +#define SK_MC_FILTERING_EXACT 0 /* Exact filtering. */ +#define SK_MC_FILTERING_INEXACT 1 /* Inexact filtering. */ + +/* ----- Additional SkAddrMcAdd return values ----- */ + +#define SK_MC_ILLEGAL_ADDRESS 2 /* Illegal address. */ +#define SK_MC_ILLEGAL_PORT 3 /* Illegal port (not the active one). */ +#define SK_MC_RLMT_OVERFLOW 4 /* Too many RLMT mc addresses. */ + +/* Promiscuous mode bits ----- */ + +#define SK_PROM_MODE_NONE 0 /* Normal receive. */ +#define SK_PROM_MODE_LLC 1 /* Receive all LLC frames. */ +#define SK_PROM_MODE_ALL_MC 2 /* Receive all multicast frames. */ +/* #define SK_PROM_MODE_NON_LLC 4 */ /* Receive all non-LLC frames. */ + +/* Macros */ + +#if 0 +#ifndef SK_ADDR_EQUAL +/* + * "&" instead of "&&" allows better optimization on IA-64. + * The replacement is safe here, as all bytes exist. + */ +#ifndef SK_ADDR_DWORD_COMPARE +#define SK_ADDR_EQUAL(A1,A2) ( \ + (((SK_U8 *)(A1))[5] == ((SK_U8 *)(A2))[5]) & \ + (((SK_U8 *)(A1))[4] == ((SK_U8 *)(A2))[4]) & \ + (((SK_U8 *)(A1))[3] == ((SK_U8 *)(A2))[3]) & \ + (((SK_U8 *)(A1))[2] == ((SK_U8 *)(A2))[2]) & \ + (((SK_U8 *)(A1))[1] == ((SK_U8 *)(A2))[1]) & \ + (((SK_U8 *)(A1))[0] == ((SK_U8 *)(A2))[0])) +#else /* SK_ADDR_DWORD_COMPARE */ +#define SK_ADDR_EQUAL(A1,A2) ( \ + (*(SK_U32 *)&(((SK_U8 *)(A1))[2]) == *(SK_U32 *)&(((SK_U8 *)(A2))[2])) & \ + (*(SK_U32 *)&(((SK_U8 *)(A1))[0]) == *(SK_U32 *)&(((SK_U8 *)(A2))[0]))) +#endif /* SK_ADDR_DWORD_COMPARE */ +#endif /* SK_ADDR_EQUAL */ +#endif /* 0 */ + +#ifndef SK_ADDR_EQUAL +#ifndef SK_ADDR_DWORD_COMPARE +#define SK_ADDR_EQUAL(A1,A2) ( \ + (((SK_U8 *)(A1))[5] == ((SK_U8 *)(A2))[5]) & \ + (((SK_U8 *)(A1))[4] == ((SK_U8 *)(A2))[4]) & \ + (((SK_U8 *)(A1))[3] == ((SK_U8 *)(A2))[3]) & \ + (((SK_U8 *)(A1))[2] == ((SK_U8 *)(A2))[2]) & \ + (((SK_U8 *)(A1))[1] == ((SK_U8 *)(A2))[1]) & \ + (((SK_U8 *)(A1))[0] == ((SK_U8 *)(A2))[0])) +#else /* SK_ADDR_DWORD_COMPARE */ +#define SK_ADDR_EQUAL(A1,A2) ( \ + (*(SK_U16 *)&(((SK_U8 *)(A1))[4]) == *(SK_U16 *)&(((SK_U8 *)(A2))[4])) && \ + (*(SK_U32 *)&(((SK_U8 *)(A1))[0]) == *(SK_U32 *)&(((SK_U8 *)(A2))[0]))) +#endif /* SK_ADDR_DWORD_COMPARE */ +#endif /* SK_ADDR_EQUAL */ + +/* typedefs *******************************************************************/ + +typedef struct s_MacAddr { + SK_U8 a[SK_MAC_ADDR_LEN]; +} SK_MAC_ADDR; + + +/* SK_FILTER is used to ensure alignment of the filter. */ +typedef union s_InexactFilter { + SK_U8 Bytes[8]; + SK_U64 Val; /* Dummy entry for alignment only. */ +} SK_FILTER64; + + +typedef struct s_AddrNet SK_ADDR_NET; + + +typedef struct s_AddrPort { + +/* ----- Public part (read-only) ----- */ + + SK_MAC_ADDR CurrentMacAddress; /* Current physical MAC Address. */ + SK_MAC_ADDR PermanentMacAddress; /* Permanent physical MAC Address. */ + int PromMode; /* Promiscuous Mode. */ + +/* ----- Private part ----- */ + + SK_MAC_ADDR PreviousMacAddress; /* Prev. phys. MAC Address. */ + SK_BOOL CurrentMacAddressSet; /* CurrentMacAddress is set. */ + SK_U8 Align01; + + SK_U32 FirstExactMatchRlmt; + SK_U32 NextExactMatchRlmt; + SK_U32 FirstExactMatchDrv; + SK_U32 NextExactMatchDrv; + SK_MAC_ADDR Exact[SK_ADDR_EXACT_MATCHES]; + SK_FILTER64 InexactFilter; /* For 64-bit hash register. */ + SK_FILTER64 InexactRlmtFilter; /* For 64-bit hash register. */ + SK_FILTER64 InexactDrvFilter; /* For 64-bit hash register. */ +} SK_ADDR_PORT; + + +struct s_AddrNet { +/* ----- Public part (read-only) ----- */ + + SK_MAC_ADDR CurrentMacAddress; /* Logical MAC Address. */ + SK_MAC_ADDR PermanentMacAddress; /* Logical MAC Address. */ + +/* ----- Private part ----- */ + + SK_U32 ActivePort; /* View of module ADDR. */ + SK_BOOL CurrentMacAddressSet; /* CurrentMacAddress is set. */ + SK_U8 Align01; + SK_U16 Align02; +}; + + +typedef struct s_Addr { + +/* ----- Public part (read-only) ----- */ + + SK_ADDR_NET Net[SK_MAX_NETS]; + SK_ADDR_PORT Port[SK_MAX_MACS]; + +/* ----- Private part ----- */ +} SK_ADDR; + +/* function prototypes ********************************************************/ + +#ifndef SK_KR_PROTO + +/* Functions provided by SkAddr */ + +/* ANSI/C++ compliant function prototypes */ + +extern int SkAddrInit( + SK_AC *pAC, + SK_IOC IoC, + int Level); + +extern int SkAddrMcClear( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int Flags); + +extern int SkAddrXmacMcClear( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int Flags); + +extern int SkAddrGmacMcClear( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int Flags); + +extern int SkAddrMcAdd( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + SK_MAC_ADDR *pMc, + int Flags); + +extern int SkAddrXmacMcAdd( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + SK_MAC_ADDR *pMc, + int Flags); + +extern int SkAddrGmacMcAdd( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + SK_MAC_ADDR *pMc, + int Flags); + +extern int SkAddrMcUpdate( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber); + +extern int SkAddrXmacMcUpdate( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber); + +extern int SkAddrGmacMcUpdate( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber); + +extern int SkAddrOverride( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + SK_MAC_ADDR *pNewAddr, + int Flags); + +extern int SkAddrPromiscuousChange( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int NewPromMode); + +extern int SkAddrXmacPromiscuousChange( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int NewPromMode); + +extern int SkAddrGmacPromiscuousChange( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 PortNumber, + int NewPromMode); + +extern int SkAddrSwap( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 FromPortNumber, + SK_U32 ToPortNumber); + +#else /* defined(SK_KR_PROTO)) */ + +/* Non-ANSI/C++ compliant function prototypes */ + +#error KR-style prototypes are not yet provided. + +#endif /* defined(SK_KR_PROTO)) */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_SKADDR_H */ diff --git a/drivers/sk98lin/h/skcsum.h b/drivers/sk98lin/h/skcsum.h new file mode 100644 index 000000000..2acae329e --- /dev/null +++ b/drivers/sk98lin/h/skcsum.h @@ -0,0 +1,261 @@ +/****************************************************************************** + * + * Name: skcsum.h + * Project: GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx) + * Version: $Revision: 1.9 $ + * Date: $Date: 2001/02/06 11:21:39 $ + * Purpose: Store/verify Internet checksum in send/receive packets. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skcsum.h,v $ + * Revision 1.9 2001/02/06 11:21:39 rassmann + * Editorial changes. + * + * Revision 1.8 2001/02/06 11:15:36 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.7 2000/06/29 13:17:05 rassmann + * Corrected reception of a packet with UDP checksum == 0 (which means there + * is no UDP checksum). + * + * Revision 1.6 2000/02/28 12:33:44 cgoos + * Changed C++ style comments to C style. + * + * Revision 1.5 2000/02/21 12:10:05 cgoos + * Fixed license comment. + * + * Revision 1.4 2000/02/21 11:08:37 cgoos + * Merged changes back into common source. + * + * Revision 1.1 1999/07/26 14:47:49 mkarl + * changed from common source to windows specific source + * added return SKCS_STATUS_IP_CSUM_ERROR_UDP and + * SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester + * changes for Tx csum offload + * + * Revision 1.2 1998/09/04 12:16:34 mhaveman + * Checked in for Stephan to allow compilation. + * -Added definition SK_CSUM_EVENT_CLEAR_PROTO_STATS to clear statistic + * -Added prototype for SkCsEvent() + * + * Revision 1.1 1998/09/01 15:36:53 swolf + * initial revision + * + * 01-Sep-1998 sw Created. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * Public header file for the "GEnesis" common module "CSUM". + * + * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon" + * and is the code name of this SysKonnect project. + * + * Compilation Options: + * + * SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an + * empty module. + * + * SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id + * definitions. In this case, all SKCS_PROTO_xxx definitions must be made + * external. + * + * SKCS_OVERWRITE_STATUS - Define to overwrite the default return status + * definitions. In this case, all SKCS_STATUS_xxx definitions must be made + * external. + * + * Include File Hierarchy: + * + * "h/skcsum.h" + * "h/sktypes.h" + * "h/skqueue.h" + * + ******************************************************************************/ + +#ifndef __INC_SKCSUM_H +#define __INC_SKCSUM_H + +#include "h/sktypes.h" +#include "h/skqueue.h" + +/* defines ********************************************************************/ + +/* + * Define the default bit flags for 'SKCS_PACKET_INFO.ProtocolFlags' if no user + * overwrite. + */ +#ifndef SKCS_OVERWRITE_PROTO /* User overwrite? */ +#define SKCS_PROTO_IP 0x1 /* IP (Internet Protocol version 4) */ +#define SKCS_PROTO_TCP 0x2 /* TCP (Transmission Control Protocol) */ +#define SKCS_PROTO_UDP 0x4 /* UDP (User Datagram Protocol) */ + +/* Indices for protocol statistics. */ +#define SKCS_PROTO_STATS_IP 0 +#define SKCS_PROTO_STATS_UDP 1 +#define SKCS_PROTO_STATS_TCP 2 +#define SKCS_NUM_PROTOCOLS 3 /* Number of supported protocols. */ +#endif /* !SKCS_OVERWRITE_PROTO */ + +/* + * Define the default SKCS_STATUS type and values if no user overwrite. + * + * SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame. + * SKCS_STATUS_IP_CSUM_ERROR - IP checksum error. + * SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame. + * SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame + * SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok). + * SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame). + * SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok). + * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok). + * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok. + * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok. + * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum. + */ +#ifndef SKCS_OVERWRITE_STATUS /* User overwrite? */ +#define SKCS_STATUS int /* Define status type. */ + +#define SKCS_STATUS_UNKNOWN_IP_VERSION 1 +#define SKCS_STATUS_IP_CSUM_ERROR 2 +#define SKCS_STATUS_IP_FRAGMENT 3 +#define SKCS_STATUS_IP_CSUM_OK 4 +#define SKCS_STATUS_TCP_CSUM_ERROR 5 +#define SKCS_STATUS_UDP_CSUM_ERROR 6 +#define SKCS_STATUS_TCP_CSUM_OK 7 +#define SKCS_STATUS_UDP_CSUM_OK 8 +/* needed for Microsoft */ +#define SKCS_STATUS_IP_CSUM_ERROR_UDP 9 +#define SKCS_STATUS_IP_CSUM_ERROR_TCP 10 +/* UDP checksum may be omitted */ +#define SKCS_STATUS_IP_CSUM_OK_NO_UDP 11 +#endif /* !SKCS_OVERWRITE_STATUS */ + +/* Clear protocol statistics event. */ +#define SK_CSUM_EVENT_CLEAR_PROTO_STATS 1 + +/* + * Add two values in one's complement. + * + * Note: One of the two input values may be "longer" than 16-bit, but then the + * resulting sum may be 17 bits long. In this case, add zero to the result using + * SKCS_OC_ADD() again. + * + * Result = Value1 + Value2 + */ +#define SKCS_OC_ADD(Result, Value1, Value2) { \ + unsigned long Sum; \ + \ + Sum = (unsigned long) (Value1) + (unsigned long) (Value2); \ + /* Add-in any carry. */ \ + (Result) = (Sum & 0xffff) + (Sum >> 16); \ +} + +/* + * Subtract two values in one's complement. + * + * Result = Value1 - Value2 + */ +#define SKCS_OC_SUB(Result, Value1, Value2) \ + SKCS_OC_ADD((Result), (Value1), ~(Value2) & 0xffff) + +/* typedefs *******************************************************************/ + +/* + * SKCS_PROTO_STATS - The CSUM protocol statistics structure. + * + * There is one instance of this structure for each protocol supported. + */ +typedef struct s_CsProtocolStatistics { + SK_U64 RxOkCts; /* Receive checksum ok. */ + SK_U64 RxUnableCts; /* Unable to verify receive checksum. */ + SK_U64 RxErrCts; /* Receive checksum error. */ + SK_U64 TxOkCts; /* Transmit checksum ok. */ + SK_U64 TxUnableCts; /* Unable to calculate checksum in hw. */ +} SKCS_PROTO_STATS; + +/* + * s_Csum - The CSUM module context structure. + */ +typedef struct s_Csum { + /* Enabled receive SK_PROTO_XXX bit flags. */ + unsigned ReceiveFlags[SK_MAX_NETS]; +#ifdef TX_CSUM + unsigned TransmitFlags[SK_MAX_NETS]; +#endif /* TX_CSUM */ + + /* The protocol statistics structure; one per supported protocol. */ + SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS]; +} SK_CSUM; + +/* + * SKCS_PACKET_INFO - The packet information structure. + */ +typedef struct s_CsPacketInfo { + /* Bit field specifiying the desired/found protocols. */ + unsigned ProtocolFlags; + + /* Length of complete IP header, including any option fields. */ + unsigned IpHeaderLength; + + /* IP header checksum. */ + unsigned IpHeaderChecksum; + + /* TCP/UDP pseudo header checksum. */ + unsigned PseudoHeaderChecksum; +} SKCS_PACKET_INFO; + +/* function prototypes ********************************************************/ + +#ifndef SkCsCalculateChecksum +extern unsigned SkCsCalculateChecksum( + void *pData, + unsigned Length); +#endif + +extern int SkCsEvent( + SK_AC *pAc, + SK_IOC Ioc, + SK_U32 Event, + SK_EVPARA Param); + +extern SKCS_STATUS SkCsGetReceiveInfo( + SK_AC *pAc, + void *pIpHeader, + unsigned Checksum1, + unsigned Checksum2, + int NetNumber); + +extern void SkCsGetSendInfo( + SK_AC *pAc, + void *pIpHeader, + SKCS_PACKET_INFO *pPacketInfo, + int NetNumber); + +extern void SkCsSetReceiveFlags( + SK_AC *pAc, + unsigned ReceiveFlags, + unsigned *pChecksum1Offset, + unsigned *pChecksum2Offset, + int NetNumber); + +#endif /* __INC_SKCSUM_H */ diff --git a/drivers/sk98lin/h/skdebug.h b/drivers/sk98lin/h/skdebug.h new file mode 100644 index 000000000..cf5b5ad33 --- /dev/null +++ b/drivers/sk98lin/h/skdebug.h @@ -0,0 +1,119 @@ +/****************************************************************************** + * + * Name: skdebug.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.12 $ + * Date: $Date: 2002/07/15 15:37:13 $ + * Purpose: SK specific DEBUG support + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: skdebug.h,v $ + * Revision 1.12 2002/07/15 15:37:13 rschmidt + * Power Management support + * Editorial changes + * + * Revision 1.11 2002/04/25 11:04:39 rschmidt + * Editorial changes + * + * Revision 1.10 1999/11/22 13:47:40 cgoos + * Changed license header to GPL. + * + * Revision 1.9 1999/09/14 14:02:43 rwahl + * Added SK_DBGMOD_PECP. + * + * Revision 1.8 1998/11/25 08:31:54 gklug + * fix: no C++ comments allowed in common sources + * + * Revision 1.7 1998/11/24 16:47:24 swolf + * Driver may now define its own SK_DBG_MSG() (eg. in "h/skdrv1st.h"). + * + * Revision 1.6 1998/10/28 10:23:55 rassmann + * ADDED SK_DBGMOD_ADDR. + * + * Revision 1.5 1998/10/22 09:43:55 gklug + * add: CSUM module + * + * Revision 1.4 1998/10/01 07:54:44 gklug + * add: PNMI debug module + * + * Revision 1.3 1998/09/18 08:32:34 afischer + * Macros changed according ssr-spec.: + * SK_DBG_MODCHK -> SK_DBG_CHKMOD + * SK_DBG_CATCHK -> SK_DBG_CHKCAT + * + * Revision 1.2 1998/07/03 14:38:25 malthoff + * Add category SK_DBGCAT_FATAL. + * + * Revision 1.1 1998/06/19 13:39:01 malthoff + * created. + * + * + ******************************************************************************/ + +#ifndef __INC_SKDEBUG_H +#define __INC_SKDEBUG_H + +#ifdef DEBUG +#ifndef SK_DBG_MSG +#define SK_DBG_MSG(pAC,comp,cat,arg) \ + if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \ + ((cat) & SK_DBG_CHKCAT(pAC)) ) { \ + SK_DBG_PRINTF arg ; \ + } +#endif +#else +#define SK_DBG_MSG(pAC,comp,lev,arg) +#endif + +/* PLS NOTE: + * ========= + * Due to any restrictions of kernel printf routines do not use other + * format identifiers as: %x %d %c %s . + * Never use any combined format identifiers such as: %lx %ld in your + * printf - argument (arg) because some OS specific kernel printfs may + * only support some basic identifiers. + */ + +/* Debug modules */ + +#define SK_DBGMOD_MERR 0x00000001L /* general module error indication */ +#define SK_DBGMOD_HWM 0x00000002L /* Hardware init module */ +#define SK_DBGMOD_RLMT 0x00000004L /* RLMT module */ +#define SK_DBGMOD_VPD 0x00000008L /* VPD module */ +#define SK_DBGMOD_I2C 0x00000010L /* I2C module */ +#define SK_DBGMOD_PNMI 0x00000020L /* PNMI module */ +#define SK_DBGMOD_CSUM 0x00000040L /* CSUM module */ +#define SK_DBGMOD_ADDR 0x00000080L /* ADDR module */ +#define SK_DBGMOD_PECP 0x00000100L /* PECP module */ +#define SK_DBGMOD_POWM 0x00000200L /* Power Management module */ + +/* Debug events */ + +#define SK_DBGCAT_INIT 0x00000001L /* module/driver initialization */ +#define SK_DBGCAT_CTRL 0x00000002L /* controlling devices */ +#define SK_DBGCAT_ERR 0x00000004L /* error handling paths */ +#define SK_DBGCAT_TX 0x00000008L /* transmit path */ +#define SK_DBGCAT_RX 0x00000010L /* receive path */ +#define SK_DBGCAT_IRQ 0x00000020L /* general IRQ handling */ +#define SK_DBGCAT_QUEUE 0x00000040L /* any queue management */ +#define SK_DBGCAT_DUMP 0x00000080L /* large data output e.g. hex dump */ +#define SK_DBGCAT_FATAL 0x00000100L /* fatal error */ + +#endif /* __INC_SKDEBUG_H */ diff --git a/drivers/sk98lin/h/skdrv1st.h b/drivers/sk98lin/h/skdrv1st.h new file mode 100644 index 000000000..af34d7b96 --- /dev/null +++ b/drivers/sk98lin/h/skdrv1st.h @@ -0,0 +1,264 @@ +/****************************************************************************** + * + * Name: skdrv1st.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.11 $ + * Date: $Date: 2003/02/25 14:16:40 $ + * Purpose: First header file for driver and all other modules + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skdrv1st.h,v $ + * Revision 1.11 2003/02/25 14:16:40 mlindner + * Fix: Copyright statement + * + * Revision 1.10 2002/10/02 12:46:02 mlindner + * Add: Support for Yukon + * + * Revision 1.9.2.2 2001/12/07 12:06:42 mlindner + * Fix: malloc -> slab changes + * + * Revision 1.9.2.1 2001/03/12 16:50:59 mlindner + * chg: kernel 2.4 adaption + * + * Revision 1.9 2001/01/22 14:16:04 mlindner + * added ProcFs functionality + * Dual Net functionality integrated + * Rlmt networks added + * + * Revision 1.8 2000/02/21 12:19:18 cgoos + * Added default for SK_DEBUG_CHKMOD/_CHKCAT + * + * Revision 1.7 1999/11/22 13:50:00 cgoos + * Changed license header to GPL. + * Added overwrite for several functions. + * Removed linux 2.0.x definitions. + * Removed PCI vendor ID definition (now in kernel). + * + * Revision 1.6 1999/07/27 08:03:33 cgoos + * Changed SK_IN/OUT macros to readX/writeX instead of memory + * accesses (necessary for ALPHA). + * + * Revision 1.5 1999/07/23 12:10:21 cgoos + * Removed SK_RLMT_SLOW_LOOKAHEAD define. + * + * Revision 1.4 1999/07/14 12:31:13 cgoos + * Added SK_RLMT_SLOW_LOOKAHEAD define. + * + * Revision 1.3 1999/04/07 10:12:54 cgoos + * Added check for KERNEL and OPTIMIZATION defines. + * + * Revision 1.2 1999/03/01 08:51:47 cgoos + * Fixed pcibios_read/write definitions. + * + * Revision 1.1 1999/02/16 07:40:49 cgoos + * First version. + * + * + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This is the first include file of the driver, which includes all + * neccessary system header files and some of the GEnesis header files. + * It also defines some basic items. + * + * Include File Hierarchy: + * + * see skge.c + * + ******************************************************************************/ + +#ifndef __INC_SKDRV1ST_H +#define __INC_SKDRV1ST_H + +#if 0 +/* Check kernel version */ +#include +#if (LINUX_VERSION_CODE > 0x020300) +#endif +#endif + +typedef struct s_AC SK_AC; + +/* override some default functions with optimized linux functions */ + +#define SK_PNMI_STORE_U16(p,v) memcpy((char*)(p),(char*)&(v),2) +#define SK_PNMI_STORE_U32(p,v) memcpy((char*)(p),(char*)&(v),4) +#define SK_PNMI_STORE_U64(p,v) memcpy((char*)(p),(char*)&(v),8) +#define SK_PNMI_READ_U16(p,v) memcpy((char*)&(v),(char*)(p),2) +#define SK_PNMI_READ_U32(p,v) memcpy((char*)&(v),(char*)(p),2) +#define SK_PNMI_READ_U64(p,v) memcpy((char*)&(v),(char*)(p),2) + +#define SkCsCalculateChecksum(p,l) ((~ip_compute_csum(p, l)) & 0xffff) + +#define SK_ADDR_EQUAL(a1,a2) (!memcmp(a1,a2,6)) + + +#if !defined(__OPTIMIZE__) || !defined(__KERNEL__) +#warning You must compile this file with the correct options! +#warning See the last lines of the source file. +#error You must compile this driver with "-O". +#endif + +#if 0 +#include +#endif +#include +#if 0 +#include +#endif +#include +#if 0 +#include +#include +#include +#include +#include +#endif +#include +#include +#include +#if 0 +#include +#include +#include + +#include +#include +#include +#endif + +#include "h/sktypes.h" +#include "h/skerror.h" +#include "h/skdebug.h" +#include "h/lm80.h" +#include "h/xmac_ii.h" + +#include "u-boot_compat.h" + +#ifdef __LITTLE_ENDIAN +#define SK_LITTLE_ENDIAN +#else +#define SK_BIG_ENDIAN +#endif + +#if 0 +#define SK_NET_DEVICE net_device +#else +#define SK_NET_DEVICE eth_device +#endif + + +/* we use gethrtime(), return unit: nanoseconds */ +#if 0 +#define SK_TICKS_PER_SEC HZ +#else +#define SK_TICKS_PER_SEC CFG_HZ +#endif + +#define SK_MEM_MAPPED_IO + +/* #define SK_RLMT_SLOW_LOOKAHEAD */ + +#define SK_MAX_MACS 2 +#define SK_MAX_NETS 2 + +#define SK_IOC char* + +typedef struct s_DrvRlmtMbuf SK_MBUF; + +#define SK_CONST64 INT64_C +#define SK_CONSTU64 UINT64_C + +#define SK_MEMCPY(dest,src,size) memcpy(dest,src,size) +#define SK_MEMCMP(s1,s2,size) memcmp(s1,s2,size) +#define SK_MEMSET(dest,val,size) memset(dest,val,size) +#define SK_STRLEN(pStr) strlen((char*)(pStr)) +#define SK_STRNCPY(pDest,pSrc,size) strncpy((char*)(pDest),(char*)(pSrc),size) +#define SK_STRCMP(pStr1,pStr2) strcmp((char*)(pStr1),(char*)(pStr2)) + +/* macros to access the adapter */ +#define SK_OUT8(b,a,v) writeb((v), ((b)+(a))) +#define SK_OUT16(b,a,v) writew((v), ((b)+(a))) +#define SK_OUT32(b,a,v) writel((v), ((b)+(a))) +#define SK_IN8(b,a,pv) (*(pv) = readb((b)+(a))) +#define SK_IN16(b,a,pv) (*(pv) = readw((b)+(a))) +#define SK_IN32(b,a,pv) (*(pv) = readl((b)+(a))) + +#define int8_t char +#define int16_t short +#define int32_t long +#define int64_t long long +#define uint8_t u_char +#define uint16_t u_short +#define uint32_t u_long +#define uint64_t unsigned long long +#define t_scalar_t int +#define t_uscalar_t unsigned int +#define uintptr_t unsigned long + +#define __CONCAT__(A,B) A##B + +#define INT32_C(a) __CONCAT__(a,L) +#define INT64_C(a) __CONCAT__(a,LL) +#define UINT32_C(a) __CONCAT__(a,UL) +#define UINT64_C(a) __CONCAT__(a,ULL) + +#ifdef DEBUG +#define SK_DBG_PRINTF printk +#ifndef SK_DEBUG_CHKMOD +#define SK_DEBUG_CHKMOD 0 +#endif +#ifndef SK_DEBUG_CHKCAT +#define SK_DEBUG_CHKCAT 0 +#endif +/* those come from the makefile */ +#define SK_DBG_CHKMOD(pAC) (SK_DEBUG_CHKMOD) +#define SK_DBG_CHKCAT(pAC) (SK_DEBUG_CHKCAT) + +extern void SkDbgPrintf(const char *format,...); + +#define SK_DBGMOD_DRV 0x00010000 + +/**** possible driver debug categories ********************************/ +#define SK_DBGCAT_DRV_ENTRY 0x00010000 +#define SK_DBGCAT_DRV_SAP 0x00020000 +#define SK_DBGCAT_DRV_MCA 0x00040000 +#define SK_DBGCAT_DRV_TX_PROGRESS 0x00080000 +#define SK_DBGCAT_DRV_RX_PROGRESS 0x00100000 +#define SK_DBGCAT_DRV_PROGRESS 0x00200000 +#define SK_DBGCAT_DRV_MSG 0x00400000 +#define SK_DBGCAT_DRV_PROM 0x00800000 +#define SK_DBGCAT_DRV_TX_FRAME 0x01000000 +#define SK_DBGCAT_DRV_ERROR 0x02000000 +#define SK_DBGCAT_DRV_INT_SRC 0x04000000 +#define SK_DBGCAT_DRV_EVENT 0x08000000 + +#endif + +#define SK_ERR_LOG SkErrorLog + +extern void SkErrorLog(SK_AC*, int, int, char*); + +#endif diff --git a/drivers/sk98lin/h/skdrv2nd.h b/drivers/sk98lin/h/skdrv2nd.h new file mode 100644 index 000000000..a311827aa --- /dev/null +++ b/drivers/sk98lin/h/skdrv2nd.h @@ -0,0 +1,561 @@ +/****************************************************************************** + * + * Name: skdrv2nd.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.15 $ + * Date: $Date: 2003/02/25 14:16:40 $ + * Purpose: Second header file for driver and all other modules + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skdrv2nd.h,v $ + * Revision 1.15 2003/02/25 14:16:40 mlindner + * Fix: Copyright statement + * + * Revision 1.14 2003/02/25 13:26:26 mlindner + * Add: Support for various vendors + * + * Revision 1.13 2002/10/02 12:46:02 mlindner + * Add: Support for Yukon + * + * Revision 1.12.2.2 2001/09/05 12:14:50 mlindner + * add: New hardware revision int + * + * Revision 1.12.2.1 2001/03/12 16:50:59 mlindner + * chg: kernel 2.4 adaption + * + * Revision 1.12 2001/03/01 12:52:15 mlindner + * Fixed ring size + * + * Revision 1.11 2001/02/19 13:28:02 mlindner + * Changed PNMI parameter values + * + * Revision 1.10 2001/01/22 14:16:04 mlindner + * added ProcFs functionality + * Dual Net functionality integrated + * Rlmt networks added + * + * Revision 1.1 2000/10/05 19:46:50 phargrov + * Add directory src/vipk_devs_nonlbl/vipk_sk98lin/ + * This is the SysKonnect SK-98xx Gigabit Ethernet driver, + * contributed by SysKonnect. + * + * Revision 1.9 2000/02/21 10:39:55 cgoos + * Added flag for jumbo support usage. + * + * Revision 1.8 1999/11/22 13:50:44 cgoos + * Changed license header to GPL. + * Fixed two comments. + * + * Revision 1.7 1999/09/28 12:38:21 cgoos + * Added CheckQueue to SK_AC. + * + * Revision 1.6 1999/07/27 08:04:05 cgoos + * Added checksumming variables to SK_AC. + * + * Revision 1.5 1999/03/29 12:33:26 cgoos + * Rreversed to fine lock granularity. + * + * Revision 1.4 1999/03/15 12:14:02 cgoos + * Added DriverLock to SK_AC. + * Removed other locks. + * + * Revision 1.3 1999/03/01 08:52:27 cgoos + * Changed pAC->PciDev declaration. + * + * Revision 1.2 1999/02/18 10:57:14 cgoos + * Removed SkDrvTimeStamp prototype. + * Fixed SkGeOsGetTime prototype. + * + * Revision 1.1 1999/02/16 07:41:01 cgoos + * First version. + * + * + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This is the second include file of the driver, which includes all other + * neccessary files and defines all structures and constants used by the + * driver and the common modules. + * + * Include File Hierarchy: + * + * see skge.c + * + ******************************************************************************/ + +#ifndef __INC_SKDRV2ND_H +#define __INC_SKDRV2ND_H + +#include "h/skqueue.h" +#include "h/skgehwt.h" +#include "h/sktimer.h" +#include "h/ski2c.h" +#include "h/skgepnmi.h" +#include "h/skvpd.h" +#include "h/skgehw.h" +#include "h/skgeinit.h" +#include "h/skaddr.h" +#include "h/skgesirq.h" +#include "h/skcsum.h" +#include "h/skrlmt.h" +#include "h/skgedrv.h" + +#define SK_PCI_ISCOMPLIANT(result, pdev) { \ + result = SK_FALSE; /* default */ \ + /* 3Com (0x10b7) */ \ + if (pdev->vendor == 0x10b7) { \ + /* Gigabit Ethernet Adapter (0x1700) */ \ + if ((pdev->device == 0x1700)) { \ + result = SK_TRUE; \ + } \ + /* SysKonnect (0x1148) */ \ + } else if (pdev->vendor == 0x1148) { \ + /* SK-98xx Gigabit Ethernet Server Adapter (0x4300) */ \ + /* SK-98xx V2 Gigabit Ethernet Adapter (0x4320) */ \ + if ((pdev->device == 0x4300) || \ + (pdev->device == 0x4320)) { \ + result = SK_TRUE; \ + } \ + /* D-Link (0x1186) */ \ + } else if (pdev->vendor == 0x1186) { \ + /* Gigabit Ethernet Adapter (0x4c00) */ \ + if ((pdev->device == 0x4c00)) { \ + result = SK_TRUE; \ + } \ + /* CNet (0x1371) */ \ + } else if (pdev->vendor == 0x1371) { \ + /* GigaCard Network Adapter (0x434e) */ \ + if ((pdev->device == 0x434e)) { \ + result = SK_TRUE; \ + } \ + /* Linksys (0x1737) */ \ + } else if (pdev->vendor == 0x1737) { \ + /* Gigabit Network Adapter (0x1032) */ \ + /* Gigabit Network Adapter (0x1064) */ \ + if ((pdev->device == 0x1032) || \ + (pdev->device == 0x1064)) { \ + result = SK_TRUE; \ + } \ + } else { \ + result = SK_FALSE; \ + } \ +} + + +extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned); +extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*); +extern SK_U64 SkOsGetTime(SK_AC*); +extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*); +extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*); +extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*); +extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32); +extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16); +extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8); +extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA); + +struct s_DrvRlmtMbuf { + SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */ + SK_U8 *pData; /* Data buffer (virtually contig.). */ + unsigned Size; /* Data buffer size. */ + unsigned Length; /* Length of packet (<= Size). */ + SK_U32 PortIdx; /* Receiving/transmitting port. */ +#ifdef SK_RLMT_MBUF_PRIVATE + SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */ +#endif /* SK_RLMT_MBUF_PRIVATE */ + struct sk_buff *pOs; /* Pointer to message block */ +}; + + +/* + * ioctl definitions + */ +#define SK_IOCTL_BASE (SIOCDEVPRIVATE) +#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0) +#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1) +#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2) + +typedef struct s_IOCTL SK_GE_IOCTL; + +struct s_IOCTL { + char* pData; + unsigned int Len; +}; + + +/* + * define sizes of descriptor rings in bytes + */ + +#if 0 +#define TX_RING_SIZE (8*1024) +#define RX_RING_SIZE (24*1024) +#else +#define TX_RING_SIZE (10 * 40) +#define RX_RING_SIZE (10 * 40) +#endif + +/* + * Buffer size for ethernet packets + */ +#define ETH_BUF_SIZE 1540 +#define ETH_MAX_MTU 1514 +#define ETH_MIN_MTU 60 +#define ETH_MULTICAST_BIT 0x01 +#define SK_JUMBO_MTU 9000 + +/* + * transmit priority selects the queue: LOW=asynchron, HIGH=synchron + */ +#define TX_PRIO_LOW 0 +#define TX_PRIO_HIGH 1 + +/* + * alignment of rx/tx descriptors + */ +#define DESCR_ALIGN 8 + +/* + * definitions for pnmi. TODO + */ +#define SK_DRIVER_RESET(pAC, IoC) 0 +#define SK_DRIVER_SENDEVENT(pAC, IoC) 0 +#define SK_DRIVER_SELFTEST(pAC, IoC) 0 +/* For get mtu you must add an own function */ +#define SK_DRIVER_GET_MTU(pAc,IoC,i) 0 +#define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0 +#define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0 + + +/* TX and RX descriptors *****************************************************/ + +typedef struct s_RxD RXD; /* the receive descriptor */ + +struct s_RxD { + volatile SK_U32 RBControl; /* Receive Buffer Control */ + SK_U32 VNextRxd; /* Next receive descriptor,low dword */ + SK_U32 VDataLow; /* Receive buffer Addr, low dword */ + SK_U32 VDataHigh; /* Receive buffer Addr, high dword */ + SK_U32 FrameStat; /* Receive Frame Status word */ + SK_U32 TimeStamp; /* Time stamp from XMAC */ + SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */ + SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */ + RXD *pNextRxd; /* Pointer to next Rxd */ + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ +}; + +typedef struct s_TxD TXD; /* the transmit descriptor */ + +struct s_TxD { + volatile SK_U32 TBControl; /* Transmit Buffer Control */ + SK_U32 VNextTxd; /* Next transmit descriptor,low dword */ + SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */ + SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */ + SK_U32 FrameStat; /* Transmit Frame Status Word */ + SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */ + SK_U16 TcpSumSt; /* TCP Sum Start */ + SK_U16 TcpSumWr; /* TCP Sum Write */ + SK_U32 TcpReserved; /* not used */ + TXD *pNextTxd; /* Pointer to next Txd */ + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */ +}; + + +/* definition of flags in descriptor control field */ +#define RX_CTRL_OWN_BMU UINT32_C(0x80000000) +#define RX_CTRL_STF UINT32_C(0x40000000) +#define RX_CTRL_EOF UINT32_C(0x20000000) +#define RX_CTRL_EOB_IRQ UINT32_C(0x10000000) +#define RX_CTRL_EOF_IRQ UINT32_C(0x08000000) +#define RX_CTRL_DEV_NULL UINT32_C(0x04000000) +#define RX_CTRL_STAT_VALID UINT32_C(0x02000000) +#define RX_CTRL_TIME_VALID UINT32_C(0x01000000) +#define RX_CTRL_CHECK_DEFAULT UINT32_C(0x00550000) +#define RX_CTRL_CHECK_CSUM UINT32_C(0x00560000) +#define RX_CTRL_LEN_MASK UINT32_C(0x0000FFFF) + +#define TX_CTRL_OWN_BMU UINT32_C(0x80000000) +#define TX_CTRL_STF UINT32_C(0x40000000) +#define TX_CTRL_EOF UINT32_C(0x20000000) +#define TX_CTRL_EOB_IRQ UINT32_C(0x10000000) +#define TX_CTRL_EOF_IRQ UINT32_C(0x08000000) +#define TX_CTRL_ST_FWD UINT32_C(0x04000000) +#define TX_CTRL_DISAB_CRC UINT32_C(0x02000000) +#define TX_CTRL_SOFTWARE UINT32_C(0x01000000) +#define TX_CTRL_CHECK_DEFAULT UINT32_C(0x00550000) +#define TX_CTRL_CHECK_CSUM UINT32_C(0x00560000) +#define TX_CTRL_LEN_MASK UINT32_C(0x0000FFFF) + + +/* The offsets of registers in the TX and RX queue control io area ***********/ + +#define RX_Q_BUF_CTRL_CNT 0x00 +#define RX_Q_NEXT_DESCR_LOW 0x04 +#define RX_Q_BUF_ADDR_LOW 0x08 +#define RX_Q_BUF_ADDR_HIGH 0x0c +#define RX_Q_FRAME_STAT 0x10 +#define RX_Q_TIME_STAMP 0x14 +#define RX_Q_CSUM_1_2 0x18 +#define RX_Q_CSUM_START_1_2 0x1c +#define RX_Q_CUR_DESCR_LOW 0x20 +#define RX_Q_DESCR_HIGH 0x24 +#define RX_Q_CUR_ADDR_LOW 0x28 +#define RX_Q_CUR_ADDR_HIGH 0x2c +#define RX_Q_CUR_BYTE_CNT 0x30 +#define RX_Q_CTRL 0x34 +#define RX_Q_FLAG 0x38 +#define RX_Q_TEST1 0x3c +#define RX_Q_TEST2 0x40 +#define RX_Q_TEST3 0x44 + +#define TX_Q_BUF_CTRL_CNT 0x00 +#define TX_Q_NEXT_DESCR_LOW 0x04 +#define TX_Q_BUF_ADDR_LOW 0x08 +#define TX_Q_BUF_ADDR_HIGH 0x0c +#define TX_Q_FRAME_STAT 0x10 +#define TX_Q_CSUM_START 0x14 +#define TX_Q_CSUM_START_POS 0x18 +#define TX_Q_RESERVED 0x1c +#define TX_Q_CUR_DESCR_LOW 0x20 +#define TX_Q_DESCR_HIGH 0x24 +#define TX_Q_CUR_ADDR_LOW 0x28 +#define TX_Q_CUR_ADDR_HIGH 0x2c +#define TX_Q_CUR_BYTE_CNT 0x30 +#define TX_Q_CTRL 0x34 +#define TX_Q_FLAG 0x38 +#define TX_Q_TEST1 0x3c +#define TX_Q_TEST2 0x40 +#define TX_Q_TEST3 0x44 + +/* definition of flags in the queue control field */ +#define RX_Q_CTRL_POLL_ON 0x00000080 +#define RX_Q_CTRL_POLL_OFF 0x00000040 +#define RX_Q_CTRL_STOP 0x00000020 +#define RX_Q_CTRL_START 0x00000010 +#define RX_Q_CTRL_CLR_I_PAR 0x00000008 +#define RX_Q_CTRL_CLR_I_EOB 0x00000004 +#define RX_Q_CTRL_CLR_I_EOF 0x00000002 +#define RX_Q_CTRL_CLR_I_ERR 0x00000001 + +#define TX_Q_CTRL_POLL_ON 0x00000080 +#define TX_Q_CTRL_POLL_OFF 0x00000040 +#define TX_Q_CTRL_STOP 0x00000020 +#define TX_Q_CTRL_START 0x00000010 +#define TX_Q_CTRL_CLR_I_EOB 0x00000004 +#define TX_Q_CTRL_CLR_I_EOF 0x00000002 +#define TX_Q_CTRL_CLR_I_ERR 0x00000001 + + +/* Interrupt bits in the interrupts source register **************************/ +#define IRQ_HW_ERROR 0x80000000 +#define IRQ_RESERVED 0x40000000 +#define IRQ_PKT_TOUT_RX1 0x20000000 +#define IRQ_PKT_TOUT_RX2 0x10000000 +#define IRQ_PKT_TOUT_TX1 0x08000000 +#define IRQ_PKT_TOUT_TX2 0x04000000 +#define IRQ_I2C_READY 0x02000000 +#define IRQ_SW 0x01000000 +#define IRQ_EXTERNAL_REG 0x00800000 +#define IRQ_TIMER 0x00400000 +#define IRQ_MAC1 0x00200000 +#define IRQ_LINK_SYNC_C_M1 0x00100000 +#define IRQ_MAC2 0x00080000 +#define IRQ_LINK_SYNC_C_M2 0x00040000 +#define IRQ_EOB_RX1 0x00020000 +#define IRQ_EOF_RX1 0x00010000 +#define IRQ_CHK_RX1 0x00008000 +#define IRQ_EOB_RX2 0x00004000 +#define IRQ_EOF_RX2 0x00002000 +#define IRQ_CHK_RX2 0x00001000 +#define IRQ_EOB_SY_TX1 0x00000800 +#define IRQ_EOF_SY_TX1 0x00000400 +#define IRQ_CHK_SY_TX1 0x00000200 +#define IRQ_EOB_AS_TX1 0x00000100 +#define IRQ_EOF_AS_TX1 0x00000080 +#define IRQ_CHK_AS_TX1 0x00000040 +#define IRQ_EOB_SY_TX2 0x00000020 +#define IRQ_EOF_SY_TX2 0x00000010 +#define IRQ_CHK_SY_TX2 0x00000008 +#define IRQ_EOB_AS_TX2 0x00000004 +#define IRQ_EOF_AS_TX2 0x00000002 +#define IRQ_CHK_AS_TX2 0x00000001 + +#define DRIVER_IRQS (IRQ_SW | IRQ_EOF_RX1 | IRQ_EOF_RX2 | \ + IRQ_EOF_SY_TX1 | IRQ_EOF_AS_TX1 | \ + IRQ_EOF_SY_TX2 | IRQ_EOF_AS_TX2) + +#define SPECIAL_IRQS (IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \ + IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \ + IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \ + IRQ_MAC1 | IRQ_LINK_SYNC_C_M1 | \ + IRQ_MAC2 | IRQ_LINK_SYNC_C_M2 | \ + IRQ_CHK_RX1 | IRQ_CHK_RX2 | \ + IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \ + IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2) + +#define IRQ_MASK (IRQ_SW | IRQ_EOB_RX1 | IRQ_EOF_RX1 | \ + IRQ_EOB_RX2 | IRQ_EOF_RX2 | \ + IRQ_EOB_SY_TX1 | IRQ_EOF_SY_TX1 | \ + IRQ_EOB_AS_TX1 | IRQ_EOF_AS_TX1 | \ + IRQ_EOB_SY_TX2 | IRQ_EOF_SY_TX2 | \ + IRQ_EOB_AS_TX2 | IRQ_EOF_AS_TX2 | \ + IRQ_HW_ERROR | IRQ_PKT_TOUT_RX1 | IRQ_PKT_TOUT_RX2 | \ + IRQ_PKT_TOUT_TX1 | IRQ_PKT_TOUT_TX2 | \ + IRQ_I2C_READY | IRQ_EXTERNAL_REG | IRQ_TIMER | \ + IRQ_MAC1 | \ + IRQ_MAC2 | \ + IRQ_CHK_RX1 | IRQ_CHK_RX2 | \ + IRQ_CHK_SY_TX1 | IRQ_CHK_AS_TX1 | \ + IRQ_CHK_SY_TX2 | IRQ_CHK_AS_TX2) + +#define IRQ_HWE_MASK 0x00000FFF /* enable all HW irqs */ + +typedef struct s_DevNet DEV_NET; + +struct s_DevNet { + int PortNr; + int NetNr; + int Mtu; + int Up; + SK_AC *pAC; +}; + +typedef struct s_TxPort TX_PORT; + +struct s_TxPort { + /* the transmit descriptor rings */ + caddr_t pTxDescrRing; /* descriptor area memory */ + SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */ + TXD *pTxdRingHead; /* Head of Tx rings */ + TXD *pTxdRingTail; /* Tail of Tx rings */ + TXD *pTxdRingPrev; /* descriptor sent previously */ + int TxdRingFree; /* # of free entrys */ +#if 0 + spinlock_t TxDesRingLock; /* serialize descriptor accesses */ +#endif + caddr_t HwAddr; /* bmu registers address */ + int PortIndex; /* index number of port (0 or 1) */ +}; + +typedef struct s_RxPort RX_PORT; + +struct s_RxPort { + /* the receive descriptor rings */ + caddr_t pRxDescrRing; /* descriptor area memory */ + SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */ + RXD *pRxdRingHead; /* Head of Rx rings */ + RXD *pRxdRingTail; /* Tail of Rx rings */ + RXD *pRxdRingPrev; /* descriptor given to BMU previously */ + int RxdRingFree; /* # of free entrys */ +#if 0 + spinlock_t RxDesRingLock; /* serialize descriptor accesses */ +#endif + int RxFillLimit; /* limit for buffers in ring */ + caddr_t HwAddr; /* bmu registers address */ + int PortIndex; /* index number of port (0 or 1) */ +}; + +typedef struct s_PerStrm PER_STRM; + +#define SK_ALLOC_IRQ 0x00000001 + +/**************************************************************************** + * Per board structure / Adapter Context structure: + * Allocated within attach(9e) and freed within detach(9e). + * Contains all 'per device' necessary handles, flags, locks etc.: + */ +struct s_AC { + SK_GEINIT GIni; /* GE init struct */ + SK_PNMI Pnmi; /* PNMI data struct */ + SK_VPD vpd; /* vpd data struct */ + SK_QUEUE Event; /* Event queue */ + SK_HWT Hwt; /* Hardware Timer control struct */ + SK_TIMCTRL Tim; /* Software Timer control struct */ + SK_I2C I2c; /* I2C relevant data structure */ + SK_ADDR Addr; /* for Address module */ + SK_CSUM Csum; /* for checksum module */ + SK_RLMT Rlmt; /* for rlmt module */ +#if 0 + spinlock_t SlowPathLock; /* Normal IRQ lock */ +#endif + SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */ + int RlmtMode; /* link check mode to set */ + int RlmtNets; /* Number of nets */ + + SK_IOC IoBase; /* register set of adapter */ + int BoardLevel; /* level of active hw init (0-2) */ + char DeviceStr[80]; /* adapter string from vpd */ + SK_U32 AllocFlag; /* flag allocation of resources */ +#if 0 + struct pci_dev *PciDev; /* for access to pci config space */ + SK_U32 PciDevId; /* pci device id */ +#else + int PciDev; +#endif + struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */ + char Name[30]; /* driver name */ + struct SK_NET_DEVICE *Next; /* link all devices (for clearing) */ + int RxBufSize; /* length of receive buffers */ +#if 0 + struct net_device_stats stats; /* linux 'netstat -i' statistics */ +#endif + int Index; /* internal board index number */ + + /* adapter RAM sizes for queues of active port */ + int RxQueueSize; /* memory used for receive queue */ + int TxSQueueSize; /* memory used for sync. tx queue */ + int TxAQueueSize; /* memory used for async. tx queue */ + + int PromiscCount; /* promiscuous mode counter */ + int AllMultiCount; /* allmulticast mode counter */ + int MulticCount; /* number of different MC */ + /* addresses for this board */ + /* (may be more than HW can)*/ + + int HWRevision; /* Hardware revision */ + int ActivePort; /* the active XMAC port */ + int MaxPorts; /* number of activated ports */ + int TxDescrPerRing; /* # of descriptors per tx ring */ + int RxDescrPerRing; /* # of descriptors per rx ring */ + + caddr_t pDescrMem; /* Pointer to the descriptor area */ + dma_addr_t pDescrMemDMA; /* PCI DMA address of area */ + + /* the port structures with descriptor rings */ + TX_PORT TxPort[SK_MAX_MACS][2]; + RX_PORT RxPort[SK_MAX_MACS]; + + unsigned int CsOfs1; /* for checksum calculation */ + unsigned int CsOfs2; /* for checksum calculation */ + SK_U32 CsOfs; /* for checksum calculation */ + + SK_BOOL CheckQueue; /* check event queue soon */ + + /* Only for tests */ + int PortUp; + int PortDown; + +}; + +#endif /* __INC_SKDRV2ND_H */ diff --git a/drivers/sk98lin/h/skerror.h b/drivers/sk98lin/h/skerror.h new file mode 100644 index 000000000..a454d9daa --- /dev/null +++ b/drivers/sk98lin/h/skerror.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * + * Name: skerror.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.5 $ + * Date: $Date: 2002/04/25 11:05:10 $ + * Purpose: SK specific Error log support + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: skerror.h,v $ + * Revision 1.5 2002/04/25 11:05:10 rschmidt + * Editorial changes + * + * Revision 1.4 1999/11/22 13:51:59 cgoos + * Changed license header to GPL. + * + * Revision 1.3 1999/09/14 14:04:42 rwahl + * Added error base SK_ERRBASE_PECP. + * Changed error base for driver. + * + * Revision 1.2 1998/08/11 11:15:41 gklug + * chg: comments + * + * Revision 1.1 1998/08/11 11:09:38 gklug + * add: error bases + * add: error Classes + * first version + * + * + * + ******************************************************************************/ + +#ifndef _INC_SKERROR_H_ +#define _INC_SKERROR_H_ + +/* + * Define Error Classes + */ +#define SK_ERRCL_OTHER (0) /* Other error */ +#define SK_ERRCL_CONFIG (1L<<0) /* Configuration error */ +#define SK_ERRCL_INIT (1L<<1) /* Initialization error */ +#define SK_ERRCL_NORES (1L<<2) /* Out of Resources error */ +#define SK_ERRCL_SW (1L<<3) /* Internal Software error */ +#define SK_ERRCL_HW (1L<<4) /* Hardware Failure */ +#define SK_ERRCL_COMM (1L<<5) /* Communication error */ + + +/* + * Define Error Code Bases + */ +#define SK_ERRBASE_RLMT 100 /* Base Error number for RLMT */ +#define SK_ERRBASE_HWINIT 200 /* Base Error number for HWInit */ +#define SK_ERRBASE_VPD 300 /* Base Error number for VPD */ +#define SK_ERRBASE_PNMI 400 /* Base Error number for PNMI */ +#define SK_ERRBASE_CSUM 500 /* Base Error number for Checksum */ +#define SK_ERRBASE_SIRQ 600 /* Base Error number for Special IRQ */ +#define SK_ERRBASE_I2C 700 /* Base Error number for I2C module */ +#define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */ +#define SK_ERRBASE_ADDR 900 /* Base Error number for Address module */ +#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */ +#define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */ + +#endif /* _INC_SKERROR_H_ */ diff --git a/drivers/sk98lin/h/skgedrv.h b/drivers/sk98lin/h/skgedrv.h new file mode 100644 index 000000000..72ba9ce19 --- /dev/null +++ b/drivers/sk98lin/h/skgedrv.h @@ -0,0 +1,72 @@ +/****************************************************************************** + * + * Name: skgedrv.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.6 $ + * Date: $Date: 2002/07/15 15:38:01 $ + * Purpose: Interface with the driver + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgedrv.h,v $ + * Revision 1.6 2002/07/15 15:38:01 rschmidt + * Power Management support + * Editorial changes + * + * Revision 1.5 2002/04/25 11:05:47 rschmidt + * Editorial changes + * + * Revision 1.4 1999/11/22 13:52:46 cgoos + * Changed license header to GPL. + * + * Revision 1.3 1998/12/01 13:31:39 cgoos + * SWITCH INTERN Event added. + * + * Revision 1.2 1998/11/25 08:28:38 gklug + * rmv: PORT SWITCH Event + * + * Revision 1.1 1998/09/29 06:14:07 gklug + * add: driver events (initial version) + * + * + ******************************************************************************/ + +#ifndef __INC_SKGEDRV_H_ +#define __INC_SKGEDRV_H_ + +/* defines ********************************************************************/ + +/* + * Define the driver events. + * Usually the events are defined by the destination module. + * In case of the driver we put the definition of the events here. + */ +#define SK_DRV_PORT_RESET 1 /* The port needs to be reset */ +#define SK_DRV_NET_UP 2 /* The net is operational */ +#define SK_DRV_NET_DOWN 3 /* The net is down */ +#define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links connected */ +#define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */ +#define SK_DRV_RLMT_SEND 6 /* Send a RLMT packet */ +#define SK_DRV_ADAP_FAIL 7 /* The whole adapter fails */ +#define SK_DRV_PORT_FAIL 8 /* One port fails */ +#define SK_DRV_SWITCH_INTERN 9 /* Port switch by the driver itself */ +#define SK_DRV_POWER_DOWN 10 /* Power down mode */ + +#endif /* __INC_SKGEDRV_H_ */ diff --git a/drivers/sk98lin/h/skgehw.h b/drivers/sk98lin/h/skgehw.h new file mode 100644 index 000000000..2c9842767 --- /dev/null +++ b/drivers/sk98lin/h/skgehw.h @@ -0,0 +1,2336 @@ +/****************************************************************************** + * + * Name: skgehw.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.49 $ + * Date: $Date: 2003/01/28 09:43:49 $ + * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: skgehw.h,v $ + * Revision 1.49 2003/01/28 09:43:49 rschmidt + * Added defines for PCI-Spec. 2.3 IRQ + * Added defines for CLK_RUN (YUKON-Lite) + * Editorial changes + * + * Revision 1.48 2002/12/05 10:25:11 rschmidt + * Added defines for Half Duplex Burst Mode On/Off + * Added defines for Rx GMAC FIFO Flush feature + * Editorial changes + * + * Revision 1.47 2002/11/12 17:01:31 rschmidt + * Added defines for WOL_CTL_DEFAULT + * Editorial changes + * + * Revision 1.46 2002/10/14 14:47:57 rschmidt + * Corrected bit mask for HW self test results + * Added defines for WOL Registers + * Editorial changes + * + * Revision 1.45 2002/10/11 09:25:22 mkarl + * Added bit mask for HW self test results. + * + * Revision 1.44 2002/08/16 14:44:36 rschmidt + * Added define GPC_HWCFG_GMII_FIB for YUKON Fiber + * + * Revision 1.43 2002/08/12 13:31:50 rschmidt + * Corrected macros for GMAC Address Registers: GM_INADDR(), + * GM_OUTADDR(), GM_INHASH, GM_OUTHASH. + * Editorial changes + * + * Revision 1.42 2002/08/08 15:37:56 rschmidt + * Added defines for Power Management Capabilities + * Editorial changes + * + * Revision 1.41 2002/07/23 16:02:25 rschmidt + * Added macro WOL_REG() to access WOL reg. (HW-Bug in YUKON 1st rev.) + * + * Revision 1.40 2002/07/15 15:41:37 rschmidt + * Added new defines for Power Management Cap. & Control + * Editorial changes + * + * Revision 1.39 2002/06/10 09:37:07 rschmidt + * Added macros for the ADDR-Modul + * + * Revision 1.38 2002/06/05 08:15:19 rschmidt + * Added defines for WOL Registers + * Editorial changes + * + * Revision 1.37 2002/04/25 11:39:23 rschmidt + * Added new defines for PCI Our Register 1 + * Added new registers and defines for YUKON (Rx FIFO, Tx FIFO, + * Time Stamp Timer, GMAC Control, GPHY Control,Link Control, + * GMAC IRQ Source and Mask, Wake-up Frame Pattern Match); + * Added new defines for Control/Status (VAUX available) + * Added Chip ID for YUKON + * Added define for descriptors with UDP ext. for YUKON + * Added macros to access the GMAC + * Added new Phy Type for Marvell 88E1011S (GPHY) + * Editorial changes + * + * Revision 1.36 2000/11/09 12:32:49 rassmann + * Renamed variables. + * + * Revision 1.35 2000/05/19 10:17:13 cgoos + * Added inactivity check in PHY_READ (in DEBUG mode only). + * + * Revision 1.34 1999/11/22 13:53:40 cgoos + * Changed license header to GPL. + * + * Revision 1.33 1999/08/27 11:17:10 malthoff + * It's more savely to put brackets around macro parameters. + * Brackets added for PHY_READ and PHY_WRITE. + * + * Revision 1.32 1999/05/19 07:31:01 cgoos + * Changes for 1000Base-T. + * Added HWAC_LINK_LED macro. + * + * Revision 1.31 1999/03/12 13:27:40 malthoff + * Remove __STDC__. + * + * Revision 1.30 1999/02/09 09:28:20 malthoff + * Add PCI_ERRBITS. + * + * Revision 1.29 1999/01/26 08:55:48 malthoff + * Bugfix: The 16 bit field relations inside the descriptor are + * endianess dependend if the descriptor reversal feature + * (PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled. + * Drivers which use this feature has to set the define + * SK_USE_REV_DESC. + * + * Revision 1.28 1998/12/10 11:10:22 malthoff + * bug fix: IS_IRQ_STAT and IS_IRQ_MST_ERR has been twisted. + * + * Revision 1.27 1998/11/13 14:19:21 malthoff + * Bug Fix: The bit definition of B3_PA_CTRL has completely + * changed from HW Spec v1.3 to v1.5. + * + * Revision 1.26 1998/11/04 08:31:48 cgoos + * Fixed byte ordering in XM_OUTADDR/XM_OUTHASH macros. + * + * Revision 1.25 1998/11/04 07:16:25 cgoos + * Changed byte ordering in XM_INADDR/XM_INHASH again. + * + * Revision 1.24 1998/11/02 11:08:43 malthoff + * RxCtrl and TxCtrl must be volatile. + * + * Revision 1.23 1998/10/28 13:50:45 malthoff + * Fix: Endian support missing in XM_IN/OUT-ADDR/HASH macros. + * + * Revision 1.22 1998/10/26 08:01:36 malthoff + * RX_MFF_CTRL1 is split up into RX_MFF_CTRL1, + * RX_MFF_STAT_TO, and RX_MFF_TIST_TO. + * TX_MFF_CTRL1 is split up TX_MFF_CTRL1 and TX_MFF_WAF. + * + * Revision 1.21 1998/10/20 07:43:10 malthoff + * Fix: XM_IN/OUT/ADDR/HASH macros: + * The pointer must be casted. + * + * Revision 1.20 1998/10/19 15:53:59 malthoff + * Remove ML proto definitions. + * + * Revision 1.19 1998/10/16 14:40:17 gklug + * fix: typo B0_XM_IMSK regs + * + * Revision 1.18 1998/10/16 09:46:54 malthoff + * Remove temp defines for ML diag prototype. + * Fix register definition for B0_XM1_PHY_DATA, B0_XM1_PHY_DATA + * B0_XM2_PHY_DATA, B0_XM2_PHY_ADDR, B0_XA1_CSR, B0_XS1_CSR, + * B0_XS2_CSR, and B0_XA2_CSR. + * + * Revision 1.17 1998/10/14 06:03:14 cgoos + * Changed shifted constant to ULONG. + * + * Revision 1.16 1998/10/09 07:05:41 malthoff + * Rename ALL_PA_ENA_TO to PA_ENA_TO_ALL. + * + * Revision 1.15 1998/10/05 07:54:23 malthoff + * Split up RB_CTRL and it's bit definition into + * RB_CTRL, RB_TST1, and RB_TST2. + * Rename RB_RX_HTPP to RB_RX_LTPP. + * Add ALL_PA_ENA_TO. Modify F_WATER_MARK + * according to HW Spec. v1.5. + * Add MFF_TX_CTRL_DEF. + * + * Revision 1.14 1998/09/28 13:31:16 malthoff + * bug fix: B2_MAC_3 is 0x110 not 0x114 + * + * Revision 1.13 1998/09/24 14:42:56 malthoff + * Split the RX_MFF_TST into RX_MFF_CTRL2, + * RX_MFF_TST1, and RX_MFF_TST2. + * Rename RX_MFF_CTRL to RX_MFF_CTRL1. + * Add BMU bit CSR_SV_IDLE. + * Add macros PHY_READ() and PHY_WRITE(). + * Rename macro SK_ADDR() to SK_HW_ADDR() + * because of conflicts with the Address Module. + * + * Revision 1.12 1998/09/16 07:25:33 malthoff + * Change the parameter order in the XM_INxx and XM_OUTxx macros, + * to have the IoC as first parameter. + * + * Revision 1.11 1998/09/03 09:58:41 malthoff + * Rework the XM_xxx macros. Use {} instead of () to + * be compatible with SK_xxx macros which are defined + * with {}. + * + * Revision 1.10 1998/09/02 11:16:39 malthoff + * Temporary modify B2_I2C_SW to make tests with + * the GE/ML prototype. + * + * Revision 1.9 1998/08/19 09:11:49 gklug + * fix: struct are removed from c-source (see CCC) + * add: typedefs for all structs + * + * Revision 1.8 1998/08/18 08:27:27 malthoff + * Add some temporary workarounds to test GE + * sources with the ML. + * + * Revision 1.7 1998/07/03 14:42:26 malthoff + * bug fix: Correct macro XMA(). + * Add temporary workaround to access the PCI config space over I/O + * + * Revision 1.6 1998/06/23 11:30:36 malthoff + * Remove ';' with ',' in macors. + * + * Revision 1.5 1998/06/22 14:20:57 malthoff + * Add macro SK_ADDR(Base,Addr). + * + * Revision 1.4 1998/06/19 13:35:43 malthoff + * change 'pGec' with 'pAC' + * + * Revision 1.3 1998/06/17 14:58:16 cvs + * Lost keywords reinserted. + * + * Revision 1.1 1998/06/17 14:16:36 cvs + * created + * + * + ******************************************************************************/ + +#ifndef __INC_SKGEHW_H +#define __INC_SKGEHW_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines ********************************************************************/ + +#define BIT_31 (1UL << 31) +#define BIT_30 (1L << 30) +#define BIT_29 (1L << 29) +#define BIT_28 (1L << 28) +#define BIT_27 (1L << 27) +#define BIT_26 (1L << 26) +#define BIT_25 (1L << 25) +#define BIT_24 (1L << 24) +#define BIT_23 (1L << 23) +#define BIT_22 (1L << 22) +#define BIT_21 (1L << 21) +#define BIT_20 (1L << 20) +#define BIT_19 (1L << 19) +#define BIT_18 (1L << 18) +#define BIT_17 (1L << 17) +#define BIT_16 (1L << 16) +#define BIT_15 (1L << 15) +#define BIT_14 (1L << 14) +#define BIT_13 (1L << 13) +#define BIT_12 (1L << 12) +#define BIT_11 (1L << 11) +#define BIT_10 (1L << 10) +#define BIT_9 (1L << 9) +#define BIT_8 (1L << 8) +#define BIT_7 (1L << 7) +#define BIT_6 (1L << 6) +#define BIT_5 (1L << 5) +#define BIT_4 (1L << 4) +#define BIT_3 (1L << 3) +#define BIT_2 (1L << 2) +#define BIT_1 (1L << 1) +#define BIT_0 1L + +#define BIT_15S (1U << 15) +#define BIT_14S (1 << 14) +#define BIT_13S (1 << 13) +#define BIT_12S (1 << 12) +#define BIT_11S (1 << 11) +#define BIT_10S (1 << 10) +#define BIT_9S (1 << 9) +#define BIT_8S (1 << 8) +#define BIT_7S (1 << 7) +#define BIT_6S (1 << 6) +#define BIT_5S (1 << 5) +#define BIT_4S (1 << 4) +#define BIT_3S (1 << 3) +#define BIT_2S (1 << 2) +#define BIT_1S (1 << 1) +#define BIT_0S 1 + +#define SHIFT31(x) ((x) << 31) +#define SHIFT30(x) ((x) << 30) +#define SHIFT29(x) ((x) << 29) +#define SHIFT28(x) ((x) << 28) +#define SHIFT27(x) ((x) << 27) +#define SHIFT26(x) ((x) << 26) +#define SHIFT25(x) ((x) << 25) +#define SHIFT24(x) ((x) << 24) +#define SHIFT23(x) ((x) << 23) +#define SHIFT22(x) ((x) << 22) +#define SHIFT21(x) ((x) << 21) +#define SHIFT20(x) ((x) << 20) +#define SHIFT19(x) ((x) << 19) +#define SHIFT18(x) ((x) << 18) +#define SHIFT17(x) ((x) << 17) +#define SHIFT16(x) ((x) << 16) +#define SHIFT15(x) ((x) << 15) +#define SHIFT14(x) ((x) << 14) +#define SHIFT13(x) ((x) << 13) +#define SHIFT12(x) ((x) << 12) +#define SHIFT11(x) ((x) << 11) +#define SHIFT10(x) ((x) << 10) +#define SHIFT9(x) ((x) << 9) +#define SHIFT8(x) ((x) << 8) +#define SHIFT7(x) ((x) << 7) +#define SHIFT6(x) ((x) << 6) +#define SHIFT5(x) ((x) << 5) +#define SHIFT4(x) ((x) << 4) +#define SHIFT3(x) ((x) << 3) +#define SHIFT2(x) ((x) << 2) +#define SHIFT1(x) ((x) << 1) +#define SHIFT0(x) ((x) << 0) + +/* + * Configuration Space header + * Since this module is used for different OS', those may be + * duplicate on some of them (e.g. Linux). But to keep the + * common source, we have to live with this... + */ +#define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */ +#define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */ +#define PCI_COMMAND 0x04 /* 16 bit Command */ +#define PCI_STATUS 0x06 /* 16 bit Status */ +#define PCI_REV_ID 0x08 /* 8 bit Revision ID */ +#if 0 +#define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */ +#endif +#define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */ +#define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */ +#define PCI_HEADER_T 0x0e /* 8 bit Header Type */ +#define PCI_BIST 0x0f /* 8 bit Built-in selftest */ +#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ +#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ + /* Byte 0x18..0x2b: reserved */ +#define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */ +#define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */ +#define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */ +#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */ + /* Byte 35..3b: reserved */ +#define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */ +#define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */ +#define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */ +#define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */ + /* Device Dependent Region */ +#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ +#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ + /* Power Management Region */ +#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */ +#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */ +#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */ +#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */ + /* Byte 0x4e: reserved */ +#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */ + /* VPD Region */ +#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */ +#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */ +#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */ +#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */ + /* Byte 0x58..0xff: reserved */ + +/* + * I2C Address (PCI Config) + * + * Note: The temperature and voltage sensors are relocated on a different + * I2C bus. + */ +#define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */ + +/* + * Define Bits and Values of the registers + */ +/* PCI_COMMAND 16 bit Command */ + /* Bit 15..11: reserved */ +#define PCI_INT_DIS BIT_10S /* Interrupt INTx# disable (PCI 2.3) */ +#define PCI_FBTEN BIT_9S /* Fast Back-To-Back enable */ +#define PCI_SERREN BIT_8S /* SERR enable */ +#define PCI_ADSTEP BIT_7S /* Address Stepping */ +#define PCI_PERREN BIT_6S /* Parity Report Response enable */ +#define PCI_VGA_SNOOP BIT_5S /* VGA palette snoop */ +#define PCI_MWIEN BIT_4S /* Memory write an inv cycl ena */ +#define PCI_SCYCEN BIT_3S /* Special Cycle enable */ +#define PCI_BMEN BIT_2S /* Bus Master enable */ +#define PCI_MEMEN BIT_1S /* Memory Space Access enable */ +#define PCI_IOEN BIT_0S /* I/O Space Access enable */ + +#define PCI_COMMAND_VAL (PCI_FBTEN | PCI_SERREN | PCI_PERREN | PCI_MWIEN |\ + PCI_BMEN | PCI_MEMEN | PCI_IOEN) + +/* PCI_STATUS 16 bit Status */ +#define PCI_PERR BIT_15S /* Parity Error */ +#define PCI_SERR BIT_14S /* Signaled SERR */ +#define PCI_RMABORT BIT_13S /* Received Master Abort */ +#define PCI_RTABORT BIT_12S /* Received Target Abort */ + /* Bit 11: reserved */ +#define PCI_DEVSEL (3<<9) /* Bit 10.. 9: DEVSEL Timing */ +#define PCI_DEV_FAST (0<<9) /* fast */ +#define PCI_DEV_MEDIUM (1<<9) /* medium */ +#define PCI_DEV_SLOW (2<<9) /* slow */ +#define PCI_DATAPERR BIT_8S /* DATA Parity error detected */ +#define PCI_FB2BCAP BIT_7S /* Fast Back-to-Back Capability */ +#define PCI_UDF BIT_6S /* User Defined Features */ +#define PCI_66MHZCAP BIT_5S /* 66 MHz PCI bus clock capable */ +#define PCI_NEWCAP BIT_4S /* New cap. list implemented */ +#define PCI_INT_STAT BIT_3S /* Interrupt INTx# Status (PCI 2.3) */ + /* Bit 2.. 0: reserved */ + +#define PCI_ERRBITS (PCI_PERR | PCI_SERR | PCI_RMABORT | PCI_RTABORT |\ + PCI_DATAPERR) + +/* PCI_CLASS_CODE 24 bit Class Code */ +/* Byte 2: Base Class (02) */ +/* Byte 1: SubClass (00) */ +/* Byte 0: Programming Interface (00) */ + +/* PCI_CACHE_LSZ 8 bit Cache Line Size */ +/* Possible values: 0,2,4,8,16,32,64,128 */ + +/* PCI_HEADER_T 8 bit Header Type */ +#define PCI_HD_MF_DEV BIT_7S /* 0= single, 1= multi-func dev */ +#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */ + +/* PCI_BIST 8 bit Built-in selftest */ +/* Built-in Self test not supported (optional) */ + +/* PCI_BASE_1ST 32 bit 1st Base address */ +#define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */ +#define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */ +#define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */ +#define PCI_PREFEN BIT_3 /* Prefetchable */ +#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */ +#define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */ +#define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */ +#define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */ +#define PCI_MEMSPACE BIT_0 /* Memory Space Indic. */ + +/* PCI_BASE_2ND 32 bit 2nd Base address */ +#define PCI_IOBASE 0xffffff00L /* Bit 31.. 8: I/O Base address */ +#define PCI_IOSIZE 0x000000fcL /* Bit 7.. 2: I/O Size Requirements */ + /* Bit 1: reserved */ +#define PCI_IOSPACE BIT_0 /* I/O Space Indicator */ + +/* PCI_BASE_ROM 32 bit Expansion ROM Base Address */ +#define PCI_ROMBASE 0xfffe0000L /* Bit 31..17: ROM BASE address (1st)*/ +#define PCI_ROMBASZ (0x1cL<<14) /* Bit 16..14: Treat as BASE or SIZE */ +#define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */ + /* Bit 10.. 1: reserved */ +#define PCI_ROMEN BIT_0 /* Address Decode enable */ + +/* Device Dependent Region */ +/* PCI_OUR_REG_1 32 bit Our Register 1 */ + /* Bit 31..29: reserved */ +#define PCI_PHY_COMA BIT_28 /* Set PHY to Coma Mode */ +#define PCI_EN_CAL BIT_27 /* Enable PCI buffer strength calibr. */ +#define PCI_DIS_CAL BIT_26 /* Disable PCI buffer strength calibr. */ +#define PCI_VIO BIT_25 /* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */ +#define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ +#define PCI_EN_IO BIT_23 /* Mapping to I/O space */ +#define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ + /* 1 = Map Flash to memory */ + /* 0 = Disable addr. dec */ +#define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */ +#define PCI_PAGE_16 (0L<<20) /* 16 k pages */ +#define PCI_PAGE_32K (1L<<20) /* 32 k pages */ +#define PCI_PAGE_64K (2L<<20) /* 64 k pages */ +#define PCI_PAGE_128K (3L<<20) /* 128 k pages */ + /* Bit 19: reserved */ +#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */ +#define PCI_NOTAR BIT_15 /* No turnaround cycle */ +#define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ +#define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ +#define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ +#define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ +#define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ +#define PCI_BURST_DIS BIT_9 /* Burst Disable */ +#define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ +#define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */ +#define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ + + +/* PCI_OUR_REG_2 32 bit Our Register 2 */ +#define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */ +#define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */ +#define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */ + /* Bit 13..12: reserved */ +#define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ +#define PCI_PATCH_DIR_3 BIT_11 +#define PCI_PATCH_DIR_2 BIT_10 +#define PCI_PATCH_DIR_1 BIT_9 +#define PCI_PATCH_DIR_0 BIT_8 +#define PCI_EXT_PATCHS (0xfL<<4) /* Bit 7.. 4: Extended Patches 3..0 */ +#define PCI_EXT_PATCH_3 BIT_7 +#define PCI_EXT_PATCH_2 BIT_6 +#define PCI_EXT_PATCH_1 BIT_5 +#define PCI_EXT_PATCH_0 BIT_4 +#define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ +#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ + /* Bit 1: reserved */ +#define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ + + +/* Power Management Region */ +/* PCI_PM_CAP_REG 16 bit Power Management Capabilities */ +#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event Support Mask */ +#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if Vaux) */ +#define PCI_PME_D3H_SUP BIT_14S /* PME from D3hot Support */ +#define PCI_PME_D2_SUP BIT_13S /* PME from D2 Support */ +#define PCI_PME_D1_SUP BIT_12S /* PME from D1 Support */ +#define PCI_PME_D0_SUP BIT_11S /* PME from D0 Support */ +#define PCI_PM_D2_SUP BIT_10S /* D2 Support in 33 MHz mode */ +#define PCI_PM_D1_SUP BIT_9S /* D1 Support */ + /* Bit 8.. 6: reserved */ +#define PCI_PM_DSI BIT_5S /* Device Specific Initialization */ +#define PCI_PM_APS BIT_4S /* Auxialiary Power Source */ +#define PCI_PME_CLOCK BIT_3S /* PM Event Clock */ +#define PCI_PM_VER_MSK 7 /* Bit 2.. 0: PM PCI Spec. version */ + +/* PCI_PM_CTL_STS 16 bit Power Management Control/Status */ +#define PCI_PME_STATUS BIT_15S /* PME Status (YUKON only) */ +#define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: Data Reg. scaling factor */ +#define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field */ +#define PCI_PME_EN BIT_8S /* Enable PME# generation (YUKON only) */ + /* Bit 7.. 2: reserved */ +#define PCI_PM_STATE_MSK 3 /* Bit 1.. 0: Power Management State */ + +#define PCI_PM_STATE_D0 0 /* D0: Operational (default) */ +#define PCI_PM_STATE_D1 1 /* D1: (YUKON only) */ +#define PCI_PM_STATE_D2 2 /* D2: (YUKON only) */ +#define PCI_PM_STATE_D3 3 /* D3: HOT, Power Down and Reset */ + +/* VPD Region */ +/* PCI_VPD_ADR_REG 16 bit VPD Address Register */ +#define PCI_VPD_FLAG BIT_15S /* starts VPD rd/wr cycle */ +#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD address mask */ + +/* Control Register File (Address Map) */ + +/* + * Bank 0 + */ +#define B0_RAP 0x0000 /* 8 bit Register Address Port */ + /* 0x0001 - 0x0003: reserved */ +#define B0_CTST 0x0004 /* 16 bit Control/Status register */ +#define B0_LED 0x0006 /* 8 Bit LED register */ +#define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ +#define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ +#define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ +#define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ +#define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ +#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */ + /* 0x001c: reserved */ + +/* B0 XMAC 1 registers (GENESIS only) */ +#define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/ + /* 0x0022 - 0x0027: reserved */ +#define B0_XM1_ISRC 0x0028 /* 16 bit ro XMAC 1 Interrupt Status Reg */ + /* 0x002a - 0x002f: reserved */ +#define B0_XM1_PHY_ADDR 0x0030 /* 16 bit r/w XMAC 1 PHY Address Register */ + /* 0x0032 - 0x0033: reserved */ +#define B0_XM1_PHY_DATA 0x0034 /* 16 bit r/w XMAC 1 PHY Data Register */ + /* 0x0036 - 0x003f: reserved */ + +/* B0 XMAC 2 registers (GENESIS only) */ +#define B0_XM2_IMSK 0x0040 /* 16 bit r/w XMAC 2 Interrupt Mask Register*/ + /* 0x0042 - 0x0047: reserved */ +#define B0_XM2_ISRC 0x0048 /* 16 bit ro XMAC 2 Interrupt Status Reg */ + /* 0x004a - 0x004f: reserved */ +#define B0_XM2_PHY_ADDR 0x0050 /* 16 bit r/w XMAC 2 PHY Address Register */ + /* 0x0052 - 0x0053: reserved */ +#define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w XMAC 2 PHY Data Register */ + /* 0x0056 - 0x005f: reserved */ + +/* BMU Control Status Registers */ +#define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */ +#define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */ +#define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ +#define B0_XA1_CSR 0x006c /* 32 bit BMU Ctrl/Stat Async Tx Queue 1*/ +#define B0_XS2_CSR 0x0070 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ +#define B0_XA2_CSR 0x0074 /* 32 bit BMU Ctrl/Stat Async Tx Queue 2*/ + /* 0x0078 - 0x007f: reserved */ + +/* + * Bank 1 + * - completely empty (this is the RAP Block window) + * Note: if RAP = 1 this page is reserved + */ + +/* + * Bank 2 + */ +/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */ +#define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ + /* 0x0106 - 0x0107: reserved */ +#define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ + /* 0x010e - 0x010f: reserved */ +#define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ + /* 0x0116 - 0x0117: reserved */ +#define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ +#define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ +#define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ +#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ + /* Eprom registers are currently of no use */ +#define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ +#define B2_E_1 0x011d /* 8 bit EPROM Byte 1 (PHY type) */ +#define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */ +#define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ +#define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */ +#define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */ + /* 0x0125 - 0x0127: reserved */ +#define B2_LD_CRTL 0x0128 /* 8 bit EPROM loader control register */ +#define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */ + /* 0x012a - 0x012f: reserved */ +#define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ +#define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ +#define B2_TI_CRTL 0x0138 /* 8 bit Timer Control */ +#define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ + /* 0x013a - 0x013f: reserved */ +#define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ +#define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ +#define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ +#define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ +#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ +#define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ + /* 0x0154 - 0x0157: reserved */ +#define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ +#define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ + /* 0x015a - 0x015b: reserved */ +#define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ +#define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ +#define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ +#define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ +#define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ + +/* Blink Source Counter (GENESIS only) */ +#define B2_BSC_INI 0x0170 /* 32 bit Blink Source Counter Init Val */ +#define B2_BSC_VAL 0x0174 /* 32 bit Blink Source Counter Value */ +#define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */ +#define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */ +#define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */ + /* 0x017c - 0x017f: reserved */ + +/* + * Bank 3 + */ +/* RAM Random Registers */ +#define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ +#define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ +#define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ + /* 0x018c - 0x018f: reserved */ + +/* RAM Interface Registers */ +/* + * The HW-Spec. calls this registers Timeout Value 0..11. But this names are + * not usable in SW. Please notice these are NOT real timeouts, these are + * the number of qWords transferred continuously. + */ +#define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ +#define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ +#define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ +#define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ +#define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ +#define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ +#define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ +#define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ +#define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ +#define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ +#define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ +#define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ +#define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ + /* 0x019d - 0x019f: reserved */ +#define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ +#define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ + /* 0x01a3 - 0x01af: reserved */ + +/* MAC Arbiter Registers (GENESIS only) */ +/* these are the no. of qWord transferred continuously and NOT real timeouts */ +#define B3_MA_TOINI_RX1 0x01b0 /* 8 bit Timeout Init Val Rx Path MAC 1 */ +#define B3_MA_TOINI_RX2 0x01b1 /* 8 bit Timeout Init Val Rx Path MAC 2 */ +#define B3_MA_TOINI_TX1 0x01b2 /* 8 bit Timeout Init Val Tx Path MAC 1 */ +#define B3_MA_TOINI_TX2 0x01b3 /* 8 bit Timeout Init Val Tx Path MAC 2 */ +#define B3_MA_TOVAL_RX1 0x01b4 /* 8 bit Timeout Value Rx Path MAC 1 */ +#define B3_MA_TOVAL_RX2 0x01b5 /* 8 bit Timeout Value Rx Path MAC 1 */ +#define B3_MA_TOVAL_TX1 0x01b6 /* 8 bit Timeout Value Tx Path MAC 2 */ +#define B3_MA_TOVAL_TX2 0x01b7 /* 8 bit Timeout Value Tx Path MAC 2 */ +#define B3_MA_TO_CTRL 0x01b8 /* 16 bit MAC Arbiter Timeout Ctrl Reg */ +#define B3_MA_TO_TEST 0x01ba /* 16 bit MAC Arbiter Timeout Test Reg */ + /* 0x01bc - 0x01bf: reserved */ +#define B3_MA_RCINI_RX1 0x01c0 /* 8 bit Recovery Init Val Rx Path MAC 1 */ +#define B3_MA_RCINI_RX2 0x01c1 /* 8 bit Recovery Init Val Rx Path MAC 2 */ +#define B3_MA_RCINI_TX1 0x01c2 /* 8 bit Recovery Init Val Tx Path MAC 1 */ +#define B3_MA_RCINI_TX2 0x01c3 /* 8 bit Recovery Init Val Tx Path MAC 2 */ +#define B3_MA_RCVAL_RX1 0x01c4 /* 8 bit Recovery Value Rx Path MAC 1 */ +#define B3_MA_RCVAL_RX2 0x01c5 /* 8 bit Recovery Value Rx Path MAC 1 */ +#define B3_MA_RCVAL_TX1 0x01c6 /* 8 bit Recovery Value Tx Path MAC 2 */ +#define B3_MA_RCVAL_TX2 0x01c7 /* 8 bit Recovery Value Tx Path MAC 2 */ +#define B3_MA_RC_CTRL 0x01c8 /* 16 bit MAC Arbiter Recovery Ctrl Reg */ +#define B3_MA_RC_TEST 0x01ca /* 16 bit MAC Arbiter Recovery Test Reg */ + /* 0x01cc - 0x01cf: reserved */ + +/* Packet Arbiter Registers (GENESIS only) */ +/* these are real timeouts */ +#define B3_PA_TOINI_RX1 0x01d0 /* 16 bit Timeout Init Val Rx Path MAC 1 */ + /* 0x01d2 - 0x01d3: reserved */ +#define B3_PA_TOINI_RX2 0x01d4 /* 16 bit Timeout Init Val Rx Path MAC 2 */ + /* 0x01d6 - 0x01d7: reserved */ +#define B3_PA_TOINI_TX1 0x01d8 /* 16 bit Timeout Init Val Tx Path MAC 1 */ + /* 0x01da - 0x01db: reserved */ +#define B3_PA_TOINI_TX2 0x01dc /* 16 bit Timeout Init Val Tx Path MAC 2 */ + /* 0x01de - 0x01df: reserved */ +#define B3_PA_TOVAL_RX1 0x01e0 /* 16 bit Timeout Val Rx Path MAC 1 */ + /* 0x01e2 - 0x01e3: reserved */ +#define B3_PA_TOVAL_RX2 0x01e4 /* 16 bit Timeout Val Rx Path MAC 2 */ + /* 0x01e6 - 0x01e7: reserved */ +#define B3_PA_TOVAL_TX1 0x01e8 /* 16 bit Timeout Val Tx Path MAC 1 */ + /* 0x01ea - 0x01eb: reserved */ +#define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */ + /* 0x01ee - 0x01ef: reserved */ +#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */ +#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */ + /* 0x01f4 - 0x01ff: reserved */ + +/* + * Bank 4 - 5 + */ +/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ +#define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ +#define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ +#define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ +#define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ +#define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ +#define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ +#define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ + /* 0x0213 - 0x027f: reserved */ + /* 0x0280 - 0x0292: MAC 2 */ + /* 0x0213 - 0x027f: reserved */ + +/* + * Bank 6 + */ +/* External registers (GENESIS only) */ +#define B6_EXT_REG 0x0300 + +/* + * Bank 7 + */ +/* This is a copy of the Configuration register file (lower half) */ +#define B7_CFG_SPC 0x0380 + +/* + * Bank 8 - 15 + */ +/* Receive and Transmit Queue Registers, use Q_ADDR() to access */ +#define B8_Q_REGS 0x0400 + +/* Queue Register Offsets, use Q_ADDR() to access */ +#define Q_D 0x00 /* 8*32 bit Current Descriptor */ +#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ +#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */ +#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ +#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ +#define Q_BC 0x30 /* 32 bit Current Byte Counter */ +#define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ +#define Q_F 0x38 /* 32 bit Flag Register */ +#define Q_T1 0x3c /* 32 bit Test Register 1 */ +#define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ +#define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ +#define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ +#define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ +#define Q_T2 0x40 /* 32 bit Test Register 2 */ +#define Q_T3 0x44 /* 32 bit Test Register 3 */ + /* 0x48 - 0x7f: reserved */ + +/* + * Bank 16 - 23 + */ +/* RAM Buffer Registers */ +#define B16_RAM_REGS 0x0800 + +/* RAM Buffer Register Offsets, use RB_ADDR() to access */ +#define RB_START 0x00 /* 32 bit RAM Buffer Start Address */ +#define RB_END 0x04 /* 32 bit RAM Buffer End Address */ +#define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ +#define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ +#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack */ +#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack */ +#define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ +#define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ + /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ +#define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ +#define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ +#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ +#define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ +#define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */ + /* 0x2c - 0x7f: reserved */ + +/* + * Bank 24 + */ +/* + * Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) + * use MR_ADDR() to access + */ +#define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */ +#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */ + /* 0x0c08 - 0x0c0b: reserved */ +#define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */ +#define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */ +#define RX_MFF_LEV 0x0c14 /* 32 bit Receive MAC FIFO Level */ +#define RX_MFF_CTRL1 0x0c18 /* 16 bit Receive MAC FIFO Control Reg 1*/ +#define RX_MFF_STAT_TO 0x0c1a /* 8 bit Receive MAC Status Timeout */ +#define RX_MFF_TIST_TO 0x0c1b /* 8 bit Receive MAC Time Stamp Timeout */ +#define RX_MFF_CTRL2 0x0c1c /* 8 bit Receive MAC FIFO Control Reg 2*/ +#define RX_MFF_TST1 0x0c1d /* 8 bit Receive MAC FIFO Test Reg 1 */ +#define RX_MFF_TST2 0x0c1e /* 8 bit Receive MAC FIFO Test Reg 2 */ + /* 0x0c1f: reserved */ +#define RX_LED_INI 0x0c20 /* 32 bit Receive LED Cnt Init Value */ +#define RX_LED_VAL 0x0c24 /* 32 bit Receive LED Cnt Current Value */ +#define RX_LED_CTRL 0x0c28 /* 8 bit Receive LED Cnt Control Reg */ +#define RX_LED_TST 0x0c29 /* 8 bit Receive LED Cnt Test Register */ + /* 0x0c2a - 0x0c2f: reserved */ +#define LNK_SYNC_INI 0x0c30 /* 32 bit Link Sync Cnt Init Value */ +#define LNK_SYNC_VAL 0x0c34 /* 32 bit Link Sync Cnt Current Value */ +#define LNK_SYNC_CTRL 0x0c38 /* 8 bit Link Sync Cnt Control Register */ +#define LNK_SYNC_TST 0x0c39 /* 8 bit Link Sync Cnt Test Register */ + /* 0x0c3a - 0x0c3b: reserved */ +#define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */ + /* 0x0c3d - 0x0c3f: reserved */ + +/* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */ +#define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ +#define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ +#define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ +#define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ +#define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ + /* 0x0c54 - 0x0c5f: reserved */ +#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ + /* 0x0c64 - 0x0c67: reserved */ +#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ + /* 0x0c6c - 0x0c6f: reserved */ +#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ + /* 0x0c74 - 0x0c77: reserved */ +#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ + /* 0x0c7c - 0x0c7f: reserved */ + +/* + * Bank 25 + */ + /* 0x0c80 - 0x0cbf: MAC 2 */ + /* 0x0cc0 - 0x0cff: reserved */ + +/* + * Bank 26 + */ +/* + * Transmit MAC FIFO and Transmit LED Registers (GENESIS only), + * use MR_ADDR() to access + */ +#define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */ +#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */ +#define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Ptr */ +#define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */ +#define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */ +#define TX_MFF_LEV 0x0d14 /* 32 bit Transmit MAC FIFO Level */ +#define TX_MFF_CTRL1 0x0d18 /* 16 bit Transmit MAC FIFO Ctrl Reg 1 */ +#define TX_MFF_WAF 0x0d1a /* 8 bit Transmit MAC Wait after flush */ + /* 0x0c1b: reserved */ +#define TX_MFF_CTRL2 0x0d1c /* 8 bit Transmit MAC FIFO Ctrl Reg 2 */ +#define TX_MFF_TST1 0x0d1d /* 8 bit Transmit MAC FIFO Test Reg 1 */ +#define TX_MFF_TST2 0x0d1e /* 8 bit Transmit MAC FIFO Test Reg 2 */ + /* 0x0d1f: reserved */ +#define TX_LED_INI 0x0d20 /* 32 bit Transmit LED Cnt Init Value */ +#define TX_LED_VAL 0x0d24 /* 32 bit Transmit LED Cnt Current Val */ +#define TX_LED_CTRL 0x0d28 /* 8 bit Transmit LED Cnt Control Reg */ +#define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Reg */ + /* 0x0d2a - 0x0d3f: reserved */ + +/* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */ +#define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ +#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ +#define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ + /* 0x0d4c - 0x0d5f: reserved */ +#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ +#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ +#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ + /* 0x0d6c - 0x0d6f: reserved */ +#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ +#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ +#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ + /* 0x0d7c - 0x0d7f: reserved */ + +/* + * Bank 27 + */ + /* 0x0d80 - 0x0dbf: MAC 2 */ + /* 0x0daa - 0x0dff: reserved */ + +/* + * Bank 28 + */ +/* Descriptor Poll Timer Registers */ +#define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ +#define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ +#define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ + /* 0x0e09: reserved */ +#define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ + /* 0x0e0b: reserved */ + +/* Time Stamp Timer Registers (YUKON only) */ + /* 0x0e10: reserved */ +#define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ +#define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ + /* 0x0e19: reserved */ +#define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ + /* 0x0e1b - 0x0e7f: reserved */ + +/* + * Bank 29 + */ + /* 0x0e80 - 0x0efc: reserved */ + +/* + * Bank 30 + */ +/* GMAC and GPHY Control Registers (YUKON only) */ +#define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ +#define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ +#define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ + /* 0x0f09 - 0x0f0b: reserved */ +#define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ + /* 0x0f0d - 0x0f0f: reserved */ +#define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ + /* 0x0f14 - 0x0f1f: reserved */ + +/* Wake-up Frame Pattern Match Control Registers (YUKON only) */ + +#define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ + +#define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ +#define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ +#define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ +#define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ +#define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ +#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Ptr */ + +/* use this macro to access above registers */ +#define WOL_REG(Reg) ((Reg) + (pAC->GIni.GIWolOffs)) + + +/* WOL Pattern Length Registers (YUKON only) */ + +#define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ +#define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ + +/* WOL Pattern Counter Registers (YUKON only) */ + +#define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ +#define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ + /* 0x0f40 - 0x0f7f: reserved */ + +/* + * Bank 31 + */ +/* 0x0f80 - 0x0fff: reserved */ + +/* + * Bank 32 - 33 + */ +#define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ + +/* + * Bank 0x22 - 0x3f + */ +/* 0x1100 - 0x1fff: reserved */ + +/* + * Bank 0x40 - 0x4f + */ +#define BASE_XMAC_1 0x2000 /* XMAC 1 registers */ + +/* + * Bank 0x50 - 0x5f + */ + +#define BASE_GMAC_1 0x2800 /* GMAC 1 registers */ + +/* + * Bank 0x60 - 0x6f + */ +#define BASE_XMAC_2 0x3000 /* XMAC 2 registers */ + +/* + * Bank 0x70 - 0x7f + */ +#define BASE_GMAC_2 0x3800 /* GMAC 2 registers */ + +/* + * Control Register Bit Definitions: + */ +/* B0_RAP 8 bit Register Address Port */ + /* Bit 7: reserved */ +#define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0,..,6f = block 6f */ + +/* B0_CTST 16 bit Control/Status register */ + /* Bit 15..14: reserved */ +#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN hot m. (YUKON-Lite only) */ +#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN reset (YUKON-Lite only) */ +#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN enable (YUKON-Lite only) */ +#define CS_VAUX_AVAIL BIT_10S /* VAUX available (YUKON only) */ +#define CS_BUS_CLOCK BIT_9S /* Bus Clock 0/1 = 33/66 MHz */ +#define CS_BUS_SLOT_SZ BIT_8S /* Slot Size 0/1 = 32/64 bit slot */ +#define CS_ST_SW_IRQ BIT_7S /* Set IRQ SW Request */ +#define CS_CL_SW_IRQ BIT_6S /* Clear IRQ SW Request */ +#define CS_STOP_DONE BIT_5S /* Stop Master is finished */ +#define CS_STOP_MAST BIT_4S /* Command Bit to stop the master */ +#define CS_MRST_CLR BIT_3S /* Clear Master reset */ +#define CS_MRST_SET BIT_2S /* Set Master reset */ +#define CS_RST_CLR BIT_1S /* Clear Software reset */ +#define CS_RST_SET BIT_0S /* Set Software reset */ + +/* B0_LED 8 Bit LED register */ + /* Bit 7.. 2: reserved */ +#define LED_STAT_ON BIT_1S /* Status LED on */ +#define LED_STAT_OFF BIT_0S /* Status LED off */ + +/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ +#define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ +#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ +#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ +#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ +#define PC_VAUX_ON BIT_3 /* Switch VAUX On */ +#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ +#define PC_VCC_ON BIT_1 /* Switch VCC On */ +#define PC_VCC_OFF BIT_0 /* Switch VCC Off */ + +/* B0_ISRC 32 bit Interrupt Source Register */ +/* B0_IMSK 32 bit Interrupt Mask Register */ +/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ +#define IS_ALL_MSK 0xbfffffffL /* All Interrupt bits */ +#define IS_HW_ERR BIT_31 /* Interrupt HW Error */ + /* Bit 30: reserved */ +#define IS_PA_TO_RX1 BIT_29 /* Packet Arb Timeout Rx1 */ +#define IS_PA_TO_RX2 BIT_28 /* Packet Arb Timeout Rx2 */ +#define IS_PA_TO_TX1 BIT_27 /* Packet Arb Timeout Tx1 */ +#define IS_PA_TO_TX2 BIT_26 /* Packet Arb Timeout Tx2 */ +#define IS_I2C_READY BIT_25 /* IRQ on end of I2C Tx */ +#define IS_IRQ_SW BIT_24 /* SW forced IRQ */ +#define IS_EXT_REG BIT_23 /* IRQ from LM80 or PHY (GENESIS only) */ + /* IRQ from PHY (YUKON only) */ +#define IS_TIMINT BIT_22 /* IRQ from Timer */ +#define IS_MAC1 BIT_21 /* IRQ from MAC 1 */ +#define IS_LNK_SYNC_M1 BIT_20 /* Link Sync Cnt wrap MAC 1 */ +#define IS_MAC2 BIT_19 /* IRQ from MAC 2 */ +#define IS_LNK_SYNC_M2 BIT_18 /* Link Sync Cnt wrap MAC 2 */ +/* Receive Queue 1 */ +#define IS_R1_B BIT_17 /* Q_R1 End of Buffer */ +#define IS_R1_F BIT_16 /* Q_R1 End of Frame */ +#define IS_R1_C BIT_15 /* Q_R1 Encoding Error */ +/* Receive Queue 2 */ +#define IS_R2_B BIT_14 /* Q_R2 End of Buffer */ +#define IS_R2_F BIT_13 /* Q_R2 End of Frame */ +#define IS_R2_C BIT_12 /* Q_R2 Encoding Error */ +/* Synchronous Transmit Queue 1 */ +#define IS_XS1_B BIT_11 /* Q_XS1 End of Buffer */ +#define IS_XS1_F BIT_10 /* Q_XS1 End of Frame */ +#define IS_XS1_C BIT_9 /* Q_XS1 Encoding Error */ +/* Asynchronous Transmit Queue 1 */ +#define IS_XA1_B BIT_8 /* Q_XA1 End of Buffer */ +#define IS_XA1_F BIT_7 /* Q_XA1 End of Frame */ +#define IS_XA1_C BIT_6 /* Q_XA1 Encoding Error */ +/* Synchronous Transmit Queue 2 */ +#define IS_XS2_B BIT_5 /* Q_XS2 End of Buffer */ +#define IS_XS2_F BIT_4 /* Q_XS2 End of Frame */ +#define IS_XS2_C BIT_3 /* Q_XS2 Encoding Error */ +/* Asynchronous Transmit Queue 2 */ +#define IS_XA2_B BIT_2 /* Q_XA2 End of Buffer */ +#define IS_XA2_F BIT_1 /* Q_XA2 End of Frame */ +#define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */ + + +/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ +/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ +#define IS_ERR_MSK 0x00000fffL /* All Error bits */ + /* Bit 31..14: reserved */ +#define IS_IRQ_TIST_OV BIT_13 /* Time Stamp Timer Overflow (YUKON only) */ +#define IS_IRQ_SENSOR BIT_12 /* IRQ from Sensor (YUKON only) */ +#define IS_IRQ_MST_ERR BIT_11 /* IRQ master error detected */ +#define IS_IRQ_STAT BIT_10 /* IRQ status exception */ +#define IS_NO_STAT_M1 BIT_9 /* No Rx Status from MAC 1 */ +#define IS_NO_STAT_M2 BIT_8 /* No Rx Status from MAC 2 */ +#define IS_NO_TIST_M1 BIT_7 /* No Time Stamp from MAC 1 */ +#define IS_NO_TIST_M2 BIT_6 /* No Time Stamp from MAC 2 */ +#define IS_RAM_RD_PAR BIT_5 /* RAM Read Parity Error */ +#define IS_RAM_WR_PAR BIT_4 /* RAM Write Parity Error */ +#define IS_M1_PAR_ERR BIT_3 /* MAC 1 Parity Error */ +#define IS_M2_PAR_ERR BIT_2 /* MAC 2 Parity Error */ +#define IS_R1_PAR_ERR BIT_1 /* Queue R1 Parity Error */ +#define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */ + +/* B2_CONN_TYP 8 bit Connector type */ +/* B2_PMD_TYP 8 bit PMD type */ +/* Values of connector and PMD type comply to SysKonnect internal std */ + +/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ +#define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */ + /* Bit 3.. 2: reserved */ +#define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */ +#define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/ + +/* B2_CHIP_ID 8 bit Chip Identification Number */ +#define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ +#define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ + +/* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */ +#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address mask */ + +/* B2_LD_CRTL 8 bit EPROM loader control register */ +/* Bits are currently reserved */ + +/* B2_LD_TEST 8 bit EPROM loader test register */ + /* Bit 7.. 4: reserved */ +#define LD_T_ON BIT_3S /* Loader Test mode on */ +#define LD_T_OFF BIT_2S /* Loader Test mode off */ +#define LD_T_STEP BIT_1S /* Decrement FPROM addr. Counter */ +#define LD_START BIT_0S /* Start loading FPROM */ + +/* + * Timer Section + */ +/* B2_TI_CRTL 8 bit Timer control */ +/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ + /* Bit 7.. 3: reserved */ +#define TIM_START BIT_2S /* Start Timer */ +#define TIM_STOP BIT_1S /* Stop Timer */ +#define TIM_CLR_IRQ BIT_0S /* Clear Timer IRQ (!IRQM) */ + +/* B2_TI_TEST 8 Bit Timer Test */ +/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ +/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ + /* Bit 7.. 3: reserved */ +#define TIM_T_ON BIT_2S /* Test mode on */ +#define TIM_T_OFF BIT_1S /* Test mode off */ +#define TIM_T_STEP BIT_0S /* Test step */ + +/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */ +/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */ + /* Bit 31..24: reserved */ +#define DPT_MSK 0x00ffffffL /* Bit 23.. 0: Desc Poll Timer Bits */ + +/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ + /* Bit 7.. 2: reserved */ +#define DPT_START BIT_1S /* Start Descriptor Poll Timer */ +#define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */ + +/* B2_E_3 8 bit lower 4 bits used for HW self test result */ +#define B2_E3_RES_MASK 0x0f + +/* B2_TST_CTRL1 8 bit Test Control Register 1 */ +#define TST_FRC_DPERR_MR BIT_7S /* force DATAPERR on MST RD */ +#define TST_FRC_DPERR_MW BIT_6S /* force DATAPERR on MST WR */ +#define TST_FRC_DPERR_TR BIT_5S /* force DATAPERR on TRG RD */ +#define TST_FRC_DPERR_TW BIT_4S /* force DATAPERR on TRG WR */ +#define TST_FRC_APERR_M BIT_3S /* force ADDRPERR on MST */ +#define TST_FRC_APERR_T BIT_2S /* force ADDRPERR on TRG */ +#define TST_CFG_WRITE_ON BIT_1S /* Enable Config Reg WR */ +#define TST_CFG_WRITE_OFF BIT_0S /* Disable Config Reg WR */ + +/* B2_TST_CTRL2 8 bit Test Control Register 2 */ + /* Bit 7.. 4: reserved */ + /* force the following error on the next master read/write */ +#define TST_FRC_DPERR_MR64 BIT_3S /* DataPERR RD 64 */ +#define TST_FRC_DPERR_MW64 BIT_2S /* DataPERR WR 64 */ +#define TST_FRC_APERR_1M64 BIT_1S /* AddrPERR on 1. phase */ +#define TST_FRC_APERR_2M64 BIT_0S /* AddrPERR on 2. phase */ + +/* B2_GP_IO 32 bit General Purpose I/O Register */ + /* Bit 31..26: reserved */ +#define GP_DIR_9 BIT_25 /* IO_9 direct, 0=I/1=O */ +#define GP_DIR_8 BIT_24 /* IO_8 direct, 0=I/1=O */ +#define GP_DIR_7 BIT_23 /* IO_7 direct, 0=I/1=O */ +#define GP_DIR_6 BIT_22 /* IO_6 direct, 0=I/1=O */ +#define GP_DIR_5 BIT_21 /* IO_5 direct, 0=I/1=O */ +#define GP_DIR_4 BIT_20 /* IO_4 direct, 0=I/1=O */ +#define GP_DIR_3 BIT_19 /* IO_3 direct, 0=I/1=O */ +#define GP_DIR_2 BIT_18 /* IO_2 direct, 0=I/1=O */ +#define GP_DIR_1 BIT_17 /* IO_1 direct, 0=I/1=O */ +#define GP_DIR_0 BIT_16 /* IO_0 direct, 0=I/1=O */ + /* Bit 15..10: reserved */ +#define GP_IO_9 BIT_9 /* IO_9 pin */ +#define GP_IO_8 BIT_8 /* IO_8 pin */ +#define GP_IO_7 BIT_7 /* IO_7 pin */ +#define GP_IO_6 BIT_6 /* IO_6 pin */ +#define GP_IO_5 BIT_5 /* IO_5 pin */ +#define GP_IO_4 BIT_4 /* IO_4 pin */ +#define GP_IO_3 BIT_3 /* IO_3 pin */ +#define GP_IO_2 BIT_2 /* IO_2 pin */ +#define GP_IO_1 BIT_1 /* IO_1 pin */ +#define GP_IO_0 BIT_0 /* IO_0 pin */ + +/* B2_I2C_CTRL 32 bit I2C HW Control Register */ +#define I2C_FLAG BIT_31 /* Start read/write if WR */ +#define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */ +#define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */ + /* Bit 8.. 5: reserved */ +#define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ +#define I2C_DEV_SIZE (7L<<1) /* Bit 3.. 1: I2C Device Size */ +#define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smal. */ +#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */ +#define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */ +#define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */ +#define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */ +#define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */ +#define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */ +#define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */ +#define I2C_STOP BIT_0 /* Interrupt I2C transfer */ + +/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ + /* Bit 31.. 1 reserved */ +#define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ + +/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */ + /* Bit 7.. 3: reserved */ +#define I2C_DATA_DIR BIT_2S /* direction of I2C_DATA */ +#define I2C_DATA BIT_1S /* I2C Data Port */ +#define I2C_CLK BIT_0S /* I2C Clock Port */ + +/* + * I2C Address + */ +#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/ + + +/* B2_BSC_CTRL 8 bit Blink Source Counter Control */ + /* Bit 7.. 2: reserved */ +#define BSC_START BIT_1S /* Start Blink Source Counter */ +#define BSC_STOP BIT_0S /* Stop Blink Source Counter */ + +/* B2_BSC_STAT 8 bit Blink Source Counter Status */ + /* Bit 7.. 1: reserved */ +#define BSC_SRC BIT_0S /* Blink Source, 0=Off / 1=On */ + +/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ +#define BSC_T_ON BIT_2S /* Test mode on */ +#define BSC_T_OFF BIT_1S /* Test mode off */ +#define BSC_T_STEP BIT_0S /* Test step */ + + +/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ + /* Bit 31..19: reserved */ +#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ + +/* RAM Interface Registers */ +/* B3_RI_CTRL 16 bit RAM Iface Control Register */ + /* Bit 15..10: reserved */ +#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */ +#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err*/ + /* Bit 7.. 2: reserved */ +#define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */ +#define RI_RST_SET BIT_0S /* Set RAM Interface Reset */ + +/* B3_RI_TEST 8 bit RAM Iface Test Register */ + /* Bit 15.. 4: reserved */ +#define RI_T_EV BIT_3S /* Timeout Event occured */ +#define RI_T_ON BIT_2S /* Timeout Timer Test On */ +#define RI_T_OFF BIT_1S /* Timeout Timer Test Off */ +#define RI_T_STEP BIT_0S /* Timeout Timer Step */ + +/* MAC Arbiter Registers */ +/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */ + /* Bit 15.. 4: reserved */ +#define MA_FOE_ON BIT_3S /* XMAC Fast Output Enable ON */ +#define MA_FOE_OFF BIT_2S /* XMAC Fast Output Enable OFF */ +#define MA_RST_CLR BIT_1S /* Clear MAC Arbiter Reset */ +#define MA_RST_SET BIT_0S /* Set MAC Arbiter Reset */ + +/* B3_MA_RC_CTRL 16 bit MAC Arbiter Recovery Ctrl Reg */ + /* Bit 15.. 8: reserved */ +#define MA_ENA_REC_TX2 BIT_7S /* Enable Recovery Timer TX2 */ +#define MA_DIS_REC_TX2 BIT_6S /* Disable Recovery Timer TX2 */ +#define MA_ENA_REC_TX1 BIT_5S /* Enable Recovery Timer TX1 */ +#define MA_DIS_REC_TX1 BIT_4S /* Disable Recovery Timer TX1 */ +#define MA_ENA_REC_RX2 BIT_3S /* Enable Recovery Timer RX2 */ +#define MA_DIS_REC_RX2 BIT_2S /* Disable Recovery Timer RX2 */ +#define MA_ENA_REC_RX1 BIT_1S /* Enable Recovery Timer RX1 */ +#define MA_DIS_REC_RX1 BIT_0S /* Disable Recovery Timer RX1 */ + +/* Packet Arbiter Registers */ +/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */ + /* Bit 15..14: reserved */ +#define PA_CLR_TO_TX2 BIT_13S /* Clear IRQ Packet Timeout TX2 */ +#define PA_CLR_TO_TX1 BIT_12S /* Clear IRQ Packet Timeout TX1 */ +#define PA_CLR_TO_RX2 BIT_11S /* Clear IRQ Packet Timeout RX2 */ +#define PA_CLR_TO_RX1 BIT_10S /* Clear IRQ Packet Timeout RX1 */ +#define PA_ENA_TO_TX2 BIT_9S /* Enable Timeout Timer TX2 */ +#define PA_DIS_TO_TX2 BIT_8S /* Disable Timeout Timer TX2 */ +#define PA_ENA_TO_TX1 BIT_7S /* Enable Timeout Timer TX1 */ +#define PA_DIS_TO_TX1 BIT_6S /* Disable Timeout Timer TX1 */ +#define PA_ENA_TO_RX2 BIT_5S /* Enable Timeout Timer RX2 */ +#define PA_DIS_TO_RX2 BIT_4S /* Disable Timeout Timer RX2 */ +#define PA_ENA_TO_RX1 BIT_3S /* Enable Timeout Timer RX1 */ +#define PA_DIS_TO_RX1 BIT_2S /* Disable Timeout Timer RX1 */ +#define PA_RST_CLR BIT_1S /* Clear MAC Arbiter Reset */ +#define PA_RST_SET BIT_0S /* Set MAC Arbiter Reset */ + +#define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\ + PA_ENA_TO_TX1 | PA_ENA_TO_TX2) + +/* Rx/Tx Path related Arbiter Test Registers */ +/* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */ +/* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */ +/* B3_PA_TEST 16 bit Packet Arbiter Test Register */ +/* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */ +#define TX2_T_EV BIT_15S /* TX2 Timeout/Recv Event occured */ +#define TX2_T_ON BIT_14S /* TX2 Timeout/Recv Timer Test On */ +#define TX2_T_OFF BIT_13S /* TX2 Timeout/Recv Timer Tst Off */ +#define TX2_T_STEP BIT_12S /* TX2 Timeout/Recv Timer Step */ +#define TX1_T_EV BIT_11S /* TX1 Timeout/Recv Event occured */ +#define TX1_T_ON BIT_10S /* TX1 Timeout/Recv Timer Test On */ +#define TX1_T_OFF BIT_9S /* TX1 Timeout/Recv Timer Tst Off */ +#define TX1_T_STEP BIT_8S /* TX1 Timeout/Recv Timer Step */ +#define RX2_T_EV BIT_7S /* RX2 Timeout/Recv Event occured */ +#define RX2_T_ON BIT_6S /* RX2 Timeout/Recv Timer Test On */ +#define RX2_T_OFF BIT_5S /* RX2 Timeout/Recv Timer Tst Off */ +#define RX2_T_STEP BIT_4S /* RX2 Timeout/Recv Timer Step */ +#define RX1_T_EV BIT_3S /* RX1 Timeout/Recv Event occured */ +#define RX1_T_ON BIT_2S /* RX1 Timeout/Recv Timer Test On */ +#define RX1_T_OFF BIT_1S /* RX1 Timeout/Recv Timer Tst Off */ +#define RX1_T_STEP BIT_0S /* RX1 Timeout/Recv Timer Step */ + + +/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ +/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ +/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ +/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ +/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ + /* Bit 31..24: reserved */ +#define TXA_MAX_VAL 0x00ffffffL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ + +/* TXA_CTRL 8 bit Tx Arbiter Control Register */ +#define TXA_ENA_FSYNC BIT_7S /* Enable force of sync Tx queue */ +#define TXA_DIS_FSYNC BIT_6S /* Disable force of sync Tx queue */ +#define TXA_ENA_ALLOC BIT_5S /* Enable alloc of free bandwidth */ +#define TXA_DIS_ALLOC BIT_4S /* Disable alloc of free bandwidth */ +#define TXA_START_RC BIT_3S /* Start sync Rate Control */ +#define TXA_STOP_RC BIT_2S /* Stop sync Rate Control */ +#define TXA_ENA_ARB BIT_1S /* Enable Tx Arbiter */ +#define TXA_DIS_ARB BIT_0S /* Disable Tx Arbiter */ + +/* TXA_TEST 8 bit Tx Arbiter Test Register */ + /* Bit 7.. 6: reserved */ +#define TXA_INT_T_ON BIT_5S /* Tx Arb Interval Timer Test On */ +#define TXA_INT_T_OFF BIT_4S /* Tx Arb Interval Timer Test Off */ +#define TXA_INT_T_STEP BIT_3S /* Tx Arb Interval Timer Step */ +#define TXA_LIM_T_ON BIT_2S /* Tx Arb Limit Timer Test On */ +#define TXA_LIM_T_OFF BIT_1S /* Tx Arb Limit Timer Test Off */ +#define TXA_LIM_T_STEP BIT_0S /* Tx Arb Limit Timer Step */ + +/* TXA_STAT 8 bit Tx Arbiter Status Register */ + /* Bit 7.. 1: reserved */ +#define TXA_PRIO_XS BIT_0S /* sync queue has prio to send */ + +/* Q_BC 32 bit Current Byte Counter */ + /* Bit 31..16: reserved */ +#define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ + +/* BMU Control Status Registers */ +/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ +/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ +/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ +/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ +/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ +/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ +/* Q_CSR 32 bit BMU Control/Status Register */ + /* Bit 31..25: reserved */ +#define CSR_SV_IDLE BIT_24 /* BMU SM Idle */ + /* Bit 23..22: reserved */ +#define CSR_DESC_CLR BIT_21 /* Clear Reset for Descr */ +#define CSR_DESC_SET BIT_20 /* Set Reset for Descr */ +#define CSR_FIFO_CLR BIT_19 /* Clear Reset for FIFO */ +#define CSR_FIFO_SET BIT_18 /* Set Reset for FIFO */ +#define CSR_HPI_RUN BIT_17 /* Release HPI SM */ +#define CSR_HPI_RST BIT_16 /* Reset HPI SM to Idle */ +#define CSR_SV_RUN BIT_15 /* Release Supervisor SM */ +#define CSR_SV_RST BIT_14 /* Reset Supervisor SM */ +#define CSR_DREAD_RUN BIT_13 /* Release Descr Read SM */ +#define CSR_DREAD_RST BIT_12 /* Reset Descr Read SM */ +#define CSR_DWRITE_RUN BIT_11 /* Release Descr Write SM */ +#define CSR_DWRITE_RST BIT_10 /* Reset Descr Write SM */ +#define CSR_TRANS_RUN BIT_9 /* Release Transfer SM */ +#define CSR_TRANS_RST BIT_8 /* Reset Transfer SM */ +#define CSR_ENA_POL BIT_7 /* Enable Descr Polling */ +#define CSR_DIS_POL BIT_6 /* Disable Descr Polling */ +#define CSR_STOP BIT_5 /* Stop Rx/Tx Queue */ +#define CSR_START BIT_4 /* Start Rx/Tx Queue */ +#define CSR_IRQ_CL_P BIT_3 /* (Rx) Clear Parity IRQ */ +#define CSR_IRQ_CL_B BIT_2 /* Clear EOB IRQ */ +#define CSR_IRQ_CL_F BIT_1 /* Clear EOF IRQ */ +#define CSR_IRQ_CL_C BIT_0 /* Clear ERR IRQ */ + +#define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\ + CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\ + CSR_TRANS_RST) +#define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\ + CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\ + CSR_TRANS_RUN) + +/* Q_F 32 bit Flag Register */ + /* Bit 31..28: reserved */ +#define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */ +#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ +#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ +#define F_WM_REACHED BIT_25 /* Watermark reached */ + /* reserved */ +#define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */ + /* Bit 15..11: reserved */ +#define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */ + +/* Q_T1 32 bit Test Register 1 */ +/* Holds four State Machine control Bytes */ +#define SM_CRTL_SV_MSK (0xffL<<24) /* Bit 31..24: Control Supervisor SM */ +#define SM_CRTL_RD_MSK (0xffL<<16) /* Bit 23..16: Control Read Desc SM */ +#define SM_CRTL_WR_MSK (0xffL<<8) /* Bit 15.. 8: Control Write Desc SM */ +#define SM_CRTL_TR_MSK 0xffL /* Bit 7.. 0: Control Transfer SM */ + +/* Q_T1_TR 8 bit Test Register 1 Transfer SM */ +/* Q_T1_WR 8 bit Test Register 1 Write Descriptor SM */ +/* Q_T1_RD 8 bit Test Register 1 Read Descriptor SM */ +/* Q_T1_SV 8 bit Test Register 1 Supervisor SM */ + +/* The control status byte of each machine looks like ... */ +#define SM_STATE 0xf0 /* Bit 7.. 4: State which shall be loaded */ +#define SM_LOAD BIT_3S /* Load the SM with SM_STATE */ +#define SM_TEST_ON BIT_2S /* Switch on SM Test Mode */ +#define SM_TEST_OFF BIT_1S /* Go off the Test Mode */ +#define SM_STEP BIT_0S /* Step the State Machine */ +/* The encoding of the states is not supported by the Diagnostics Tool */ + +/* Q_T2 32 bit Test Register 2 */ + /* Bit 31.. 8: reserved */ +#define T2_AC_T_ON BIT_7 /* Address Counter Test Mode on */ +#define T2_AC_T_OFF BIT_6 /* Address Counter Test Mode off */ +#define T2_BC_T_ON BIT_5 /* Byte Counter Test Mode on */ +#define T2_BC_T_OFF BIT_4 /* Byte Counter Test Mode off */ +#define T2_STEP04 BIT_3 /* Inc AC/Dec BC by 4 */ +#define T2_STEP03 BIT_2 /* Inc AC/Dec BC by 3 */ +#define T2_STEP02 BIT_1 /* Inc AC/Dec BC by 2 */ +#define T2_STEP01 BIT_0 /* Inc AC/Dec BC by 1 */ + +/* Q_T3 32 bit Test Register 3 */ + /* Bit 31.. 7: reserved */ +#define T3_MUX_MSK (7<<4) /* Bit 6.. 4: Mux Position */ + /* Bit 3: reserved */ +#define T3_VRAM_MSK 7 /* Bit 2.. 0: Virtual RAM Buffer Address */ + +/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ +/* RB_START 32 bit RAM Buffer Start Address */ +/* RB_END 32 bit RAM Buffer End Address */ +/* RB_WP 32 bit RAM Buffer Write Pointer */ +/* RB_RP 32 bit RAM Buffer Read Pointer */ +/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ +/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ +/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ +/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ +/* RB_PC 32 bit RAM Buffer Packet Counter */ +/* RB_LEV 32 bit RAM Buffer Level Register */ + /* Bit 31..19: reserved */ +#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ + +/* RB_TST2 8 bit RAM Buffer Test Register 2 */ + /* Bit 7.. 4: reserved */ +#define RB_PC_DEC BIT_3S /* Packet Counter Decrem */ +#define RB_PC_T_ON BIT_2S /* Packet Counter Test On */ +#define RB_PC_T_OFF BIT_1S /* Packet Counter Tst Off */ +#define RB_PC_INC BIT_0S /* Packet Counter Increm */ + +/* RB_TST1 8 bit RAM Buffer Test Register 1 */ + /* Bit 7: reserved */ +#define RB_WP_T_ON BIT_6S /* Write Pointer Test On */ +#define RB_WP_T_OFF BIT_5S /* Write Pointer Test Off */ +#define RB_WP_INC BIT_4S /* Write Pointer Increm */ + /* Bit 3: reserved */ +#define RB_RP_T_ON BIT_2S /* Read Pointer Test On */ +#define RB_RP_T_OFF BIT_1S /* Read Pointer Test Off */ +#define RB_RP_DEC BIT_0S /* Read Pointer Decrement */ + +/* RB_CTRL 8 bit RAM Buffer Control Register */ + /* Bit 7.. 6: reserved */ +#define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */ +#define RB_DIS_STFWD BIT_4S /* Disable Store & Forward */ +#define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */ +#define RB_DIS_OP_MD BIT_2S /* Disable Operation Mode */ +#define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */ +#define RB_RST_SET BIT_0S /* Set RAM Buf STM Reset */ + + +/* Receive and Transmit MAC FIFO Registers (GENESIS only) */ + +/* RX_MFF_EA 32 bit Receive MAC FIFO End Address */ +/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */ +/* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */ +/* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter */ +/* RX_MFF_LEV 32 bit Receive MAC FIFO Level */ +/* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */ +/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */ +/* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */ +/* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */ +/* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */ +/* TX_MFF_LEV 32 bit Transmit MAC FIFO Level */ + /* Bit 31.. 6: reserved */ +#define MFF_MSK 0x007fL /* Bit 5.. 0: MAC FIFO Address/Ptr Bits */ + +/* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */ + /* Bit 15..14: reserved */ +#define MFF_ENA_RDY_PAT BIT_13S /* Enable Ready Patch */ +#define MFF_DIS_RDY_PAT BIT_12S /* Disable Ready Patch */ +#define MFF_ENA_TIM_PAT BIT_11S /* Enable Timing Patch */ +#define MFF_DIS_TIM_PAT BIT_10S /* Disable Timing Patch */ +#define MFF_ENA_ALM_FUL BIT_9S /* Enable AlmostFull Sign */ +#define MFF_DIS_ALM_FUL BIT_8S /* Disable AlmostFull Sign */ +#define MFF_ENA_PAUSE BIT_7S /* Enable Pause Signaling */ +#define MFF_DIS_PAUSE BIT_6S /* Disable Pause Signaling */ +#define MFF_ENA_FLUSH BIT_5S /* Enable Frame Flushing */ +#define MFF_DIS_FLUSH BIT_4S /* Disable Frame Flushing */ +#define MFF_ENA_TIST BIT_3S /* Enable Time Stamp Gener */ +#define MFF_DIS_TIST BIT_2S /* Disable Time Stamp Gener */ +#define MFF_CLR_INTIST BIT_1S /* Clear IRQ No Time Stamp */ +#define MFF_CLR_INSTAT BIT_0S /* Clear IRQ No Status */ + +#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT + +/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */ +#define MFF_CLR_PERR BIT_15S /* Clear Parity Error IRQ */ + /* Bit 14: reserved */ +#define MFF_ENA_PKT_REC BIT_13S /* Enable Packet Recovery */ +#define MFF_DIS_PKT_REC BIT_12S /* Disable Packet Recovery */ +/* MFF_ENA_TIM_PAT (see RX_MFF_CTRL1) Bit 11: Enable Timing Patch */ +/* MFF_DIS_TIM_PAT (see RX_MFF_CTRL1) Bit 10: Disable Timing Patch */ +/* MFF_ENA_ALM_FUL (see RX_MFF_CTRL1) Bit 9: Enable Almost Full Sign */ +/* MFF_DIS_ALM_FUL (see RX_MFF_CTRL1) Bit 8: Disable Almost Full Sign */ +#define MFF_ENA_W4E BIT_7S /* Enable Wait for Empty */ +#define MFF_DIS_W4E BIT_6S /* Disable Wait for Empty */ +/* MFF_ENA_FLUSH (see RX_MFF_CTRL1) Bit 5: Enable Frame Flushing */ +/* MFF_DIS_FLUSH (see RX_MFF_CTRL1) Bit 4: Disable Frame Flushing */ +#define MFF_ENA_LOOPB BIT_3S /* Enable Loopback */ +#define MFF_DIS_LOOPB BIT_2S /* Disable Loopback */ +#define MFF_CLR_MAC_RST BIT_1S /* Clear XMAC Reset */ +#define MFF_SET_MAC_RST BIT_0S /* Set XMAC Reset */ + +#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH) + +/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ +/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ + /* Bit 7: reserved */ +#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Ptr TestOn */ +#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Ptr TstOff */ +#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Ptr Increment */ +#define MFF_PC_DEC BIT_3S /* Packet Counter Decrement */ +#define MFF_PC_T_ON BIT_2S /* Packet Counter Test On */ +#define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */ +#define MFF_PC_INC BIT_0S /* Packet Counter Increment */ + +/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */ +/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */ + /* Bit 7: reserved */ +#define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */ +#define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */ +#define MFF_WP_INC BIT_4S /* Write Pointer Increm */ + /* Bit 3: reserved */ +#define MFF_RP_T_ON BIT_2S /* Read Pointer Test On */ +#define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */ +#define MFF_RP_DEC BIT_0S /* Read Pointer Decrement */ + +/* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */ +/* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */ + /* Bit 7..4: reserved */ +#define MFF_ENA_OP_MD BIT_3S /* Enable Operation Mode */ +#define MFF_DIS_OP_MD BIT_2S /* Disable Operation Mode */ +#define MFF_RST_CLR BIT_1S /* Clear MAC FIFO Reset */ +#define MFF_RST_SET BIT_0S /* Set MAC FIFO Reset */ + + +/* Link LED Counter Registers (GENESIS only) */ + +/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */ +/* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */ +/* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */ + /* Bit 7.. 3: reserved */ +#define LED_START BIT_2S /* Start Timer */ +#define LED_STOP BIT_1S /* Stop Timer */ +#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED on */ +#define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */ + +/* RX_LED_TST 8 bit Receive LED Cnt Test Register */ +/* TX_LED_TST 8 bit Transmit LED Cnt Test Register */ +/* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */ + /* Bit 7.. 3: reserved */ +#define LED_T_ON BIT_2S /* LED Counter Test mode On */ +#define LED_T_OFF BIT_1S /* LED Counter Test mode Off */ +#define LED_T_STEP BIT_0S /* LED Counter Step */ + +/* LNK_LED_REG 8 bit Link LED Register */ + /* Bit 7.. 6: reserved */ +#define LED_BLK_ON BIT_5S /* Link LED Blinking On */ +#define LED_BLK_OFF BIT_4S /* Link LED Blinking Off */ +#define LED_SYNC_ON BIT_3S /* Use Sync Wire to switch LED */ +#define LED_SYNC_OFF BIT_2S /* Disable Sync Wire Input */ +#define LED_ON BIT_1S /* switch LED on */ +#define LED_OFF BIT_0S /* switch LED off */ + +/* Receive and Transmit GMAC FIFO Registers (YUKON only) */ + +/* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ +/* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ +/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ +/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ +/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ +/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ +/* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ +/* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ +/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ +/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Ptr. */ +/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ +/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ +/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ +/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ + +/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ + /* Bits 31..15: reserved */ +#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ +#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ +#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ + /* Bit 11: reserved */ +#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ +#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ +#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ +#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ +#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ +#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ +#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ +#define GMF_OPER_ON BIT_3 /* Operational Mode On */ +#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ +#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ +#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ + +/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ + /* Bits 31..19: reserved */ +#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ +#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ +#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ + /* Bits 15..7: same as for RX_GMF_CTRL_T */ +#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ +#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ +#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ + /* Bits 3..0: same as for RX_GMF_CTRL_T */ + +#define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) +#define GMF_TX_CTRL_DEF GMF_OPER_ON + +#define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ + +/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ + /* Bit 7.. 3: reserved */ +#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */ +#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */ +#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */ + +/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ + /* Bits 31.. 8: reserved */ +#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ +#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ +#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ +#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ +#define GMC_PAUSE_ON BIT_3 /* Pause On */ +#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ +#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ +#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ + +/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ + /* Bits 31..29: reserved */ +#define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ +#define GPC_INT_POL_HI BIT_27 /* IRQ Polarity is Active HIGH */ +#define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ +#define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ +#define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ +#define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ +#define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ +#define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ +#define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ +#define GPC_ANEG_0 BIT_19 /* ANEG[0] */ +#define GPC_ENA_XC BIT_18 /* Enable MDI crossover */ +#define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ +#define GPC_ANEG_3 BIT_16 /* ANEG[3] */ +#define GPC_ANEG_2 BIT_15 /* ANEG[2] */ +#define GPC_ANEG_1 BIT_14 /* ANEG[1] */ +#define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ +#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ +#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ +#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ +#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ +#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ + /* Bits 7..2: reserved */ +#define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ +#define GPC_RST_SET BIT_0 /* Set GPHY Reset */ + +#define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \ + GPC_HWCFG_M_1 | GPC_HWCFG_M_0) + +#define GPC_HWCFG_GMII_FIB ( GPC_HWCFG_M_2 | \ + GPC_HWCFG_M_1 | GPC_HWCFG_M_0) + +#define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | \ + GPC_ANEG_1 | GPC_ANEG_0) + +/* forced speed and duplex mode (don't mix with other ANEG bits) */ +#define GPC_FRC10MBIT_HALF 0 +#define GPC_FRC10MBIT_FULL GPC_ANEG_0 +#define GPC_FRC100MBIT_HALF GPC_ANEG_1 +#define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1) + +/* auto-negotiation with limited advertised speeds */ +/* mix only with master/slave settings (for copper) */ +#define GPC_ADV_1000_HALF GPC_ANEG_2 +#define GPC_ADV_1000_FULL GPC_ANEG_3 +#define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3) + +/* master/slave settings */ +/* only for copper with 1000 Mbps */ +#define GPC_FORCE_MASTER 0 +#define GPC_FORCE_SLAVE GPC_ANEG_0 +#define GPC_PREF_MASTER GPC_ANEG_1 +#define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0) + +/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ +/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ +#define GM_IS_TX_CO_OV BIT_5 /* Transmit Counter Overflow IRQ */ +#define GM_IS_RX_CO_OV BIT_4 /* Receive Counter Overflow IRQ */ +#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ +#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ +#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ +#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ + +#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | \ + GM_IS_TX_FF_UR) + +/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ + /* Bits 15.. 2: reserved */ +#define GMLC_RST_CLR BIT_1S /* Clear GMAC Link Reset */ +#define GMLC_RST_SET BIT_0S /* Set GMAC Link Reset */ + + +/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ +#define WOL_CTL_LINK_CHG_OCC BIT_15S +#define WOL_CTL_MAGIC_PKT_OCC BIT_14S +#define WOL_CTL_PATTERN_OCC BIT_13S + +#define WOL_CTL_CLEAR_RESULT BIT_12S + +#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11S +#define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10S +#define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9S +#define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8S +#define WOL_CTL_ENA_PME_ON_PATTERN BIT_7S +#define WOL_CTL_DIS_PME_ON_PATTERN BIT_6S + +#define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5S +#define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4S +#define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3S +#define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2S +#define WOL_CTL_ENA_PATTERN_UNIT BIT_1S +#define WOL_CTL_DIS_PATTERN_UNIT BIT_0S + +#define WOL_CTL_DEFAULT \ + (WOL_CTL_DIS_PME_ON_LINK_CHG | \ + WOL_CTL_DIS_PME_ON_PATTERN | \ + WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ + WOL_CTL_DIS_LINK_CHG_UNIT | \ + WOL_CTL_DIS_PATTERN_UNIT | \ + WOL_CTL_DIS_MAGIC_PKT_UNIT) + +/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ +#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) + +#define SK_NUM_WOL_PATTERN 7 +#define SK_PATTERN_PER_WORD 4 +#define SK_BITMASK_PATTERN 7 +#define SK_POW_PATTERN_LENGTH 128 + +#define WOL_LENGTH_MSK 0x7f +#define WOL_LENGTH_SHIFT 8 + + +/* Receive and Transmit Descriptors ******************************************/ + +/* Transmit Descriptor struct */ +typedef struct s_HwTxd { + SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */ + SK_U32 TxNext; /* Physical Address Pointer to the next TxD */ + SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */ + SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */ + SK_U32 TxStat; /* Transmit Frame Status Word */ +#ifndef SK_USE_REV_DESC + SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */ + SK_U16 TxRes1; /* 16 bit reserved field */ + SK_U16 TxTcpWp; /* TCP Checksum Write Position */ + SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ +#else /* SK_USE_REV_DESC */ + SK_U16 TxRes1; /* 16 bit reserved field */ + SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */ + SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */ + SK_U16 TxTcpWp; /* TCP Checksum Write Position */ +#endif /* SK_USE_REV_DESC */ + SK_U32 TxRes2; /* 32 bit reserved field */ +} SK_HWTXD; + +/* Receive Descriptor struct */ +typedef struct s_HwRxd { + SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */ + SK_U32 RxNext; /* Physical Address Pointer to the next RxD */ + SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower dword */ + SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper dword */ + SK_U32 RxStat; /* Receive Frame Status Word */ + SK_U32 RxTiSt; /* Receive Time Stamp (from XMAC on GENESIS) */ +#ifndef SK_USE_REV_DESC + SK_U16 RxTcpSum1; /* TCP Checksum 1 */ + SK_U16 RxTcpSum2; /* TCP Checksum 2 */ + SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ + SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ +#else /* SK_USE_REV_DESC */ + SK_U16 RxTcpSum2; /* TCP Checksum 2 */ + SK_U16 RxTcpSum1; /* TCP Checksum 1 */ + SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */ + SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */ +#endif /* SK_USE_REV_DESC */ +} SK_HWRXD; + +/* + * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2) + * should set the define SK_USE_REV_DESC. + * Structures are 'normaly' not endianess dependent. But in + * this case the SK_U16 fields are bound to bit positions inside the + * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord. + * The bit positions inside a DWord are of course endianess dependent and + * swaps if the DWord is swapped by the hardware. + */ + + +/* Descriptor Bit Definition */ +/* TxCtrl Transmit Buffer Control Field */ +/* RxCtrl Receive Buffer Control Field */ +#define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ +#define BMU_STF BIT_30 /* Start of Frame */ +#define BMU_EOF BIT_29 /* End of Frame */ +#define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ +#define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ +/* TxCtrl specific bits */ +#define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ +#define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ +#define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ +/* RxCtrl specific bits */ +#define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ +#define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ +#define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ + /* Bit 23..16: BMU Check Opcodes */ +#define BMU_CHECK (0x55L<<16) /* Default BMU check */ +#define BMU_TCP_CHECK (0x56L<<16) /* Descr with TCP ext */ +#define BMU_UDP_CHECK (0x57L<<16) /* Descr with UDP ext (YUKON only) */ +#define BMU_BBC 0xFFFFL /* Bit 15.. 0: Buffer Byte Counter */ + +/* TxStat Transmit Frame Status Word */ +/* RxStat Receive Frame Status Word */ +/* + *Note: TxStat is reserved for ASIC loopback mode only + * + * The Bits of the Status words are defined in xmac_ii.h + * (see XMR_FS bits) + */ + +/* other defines *************************************************************/ + +/* + * FlashProm specification + */ +#define MAX_PAGES 0x20000L /* Every byte has a single page */ +#define MAX_FADDR 1 /* 1 byte per page */ +#define SKFDDI_PSZ 8 /* address PROM size */ + +/* macros ********************************************************************/ + +/* + * Receive and Transmit Queues + */ +#define Q_R1 0x0000 /* Receive Queue 1 */ +#define Q_R2 0x0080 /* Receive Queue 2 */ +#define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ +#define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ +#define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ +#define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ + +/* + * Macro Q_ADDR() + * + * Use this macro to access the Receive and Transmit Queue Registers. + * + * para: + * Queue Queue to access. + * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2 + * Offs Queue register offset. + * Values: Q_D, Q_DA_L ... Q_T2, Q_T3 + * + * usage SK_IN32(pAC, Q_ADDR(Q_R2, Q_BC), pVal) + */ +#define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) + +/* + * Macro RB_ADDR() + * + * Use this macro to access the RAM Buffer Registers. + * + * para: + * Queue Queue to access. + * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2 + * Offs Queue register offset. + * Values: RB_START, RB_END ... RB_LEV, RB_CTRL + * + * usage SK_IN32(pAC, RB_ADDR(Q_R2, RB_RP), pVal) + */ +#define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) + + +/* + * MAC Related Registers + */ +#define MAC_1 0 /* belongs to the port near the slot */ +#define MAC_2 1 /* belongs to the port far away from the slot */ + +/* + * Macro MR_ADDR() + * + * Use this macro to access a MAC Related Registers inside the ASIC. + * + * para: + * Mac MAC to access. + * Values: MAC_1, MAC_2 + * Offs MAC register offset. + * Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG, + * TX_MFF_EA, TX_MFF_WP ... TX_LED_TST + * + * usage SK_IN32(pAC, MR_ADDR(MAC_1, TX_MFF_EA), pVal) + */ +#define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) + +#ifdef SK_LITTLE_ENDIAN +#define XM_WORD_LO 0 +#define XM_WORD_HI 1 +#else /* !SK_LITTLE_ENDIAN */ +#define XM_WORD_LO 1 +#define XM_WORD_HI 0 +#endif /* !SK_LITTLE_ENDIAN */ + + +/* + * macros to access the XMAC (GENESIS only) + * + * XM_IN16(), to read a 16 bit register (e.g. XM_MMU_CMD) + * XM_OUT16(), to write a 16 bit register (e.g. XM_MMU_CMD) + * XM_IN32(), to read a 32 bit register (e.g. XM_TX_EV_CNT) + * XM_OUT32(), to write a 32 bit register (e.g. XM_TX_EV_CNT) + * XM_INADDR(), to read a network address register (e.g. XM_SRC_CHK) + * XM_OUTADDR(), to write a network address register (e.g. XM_SRC_CHK) + * XM_INHASH(), to read the XM_HSM_CHK register + * XM_OUTHASH() to write the XM_HSM_CHK register + * + * para: + * Mac XMAC to access values: MAC_1 or MAC_2 + * IoC I/O context needed for SK I/O macros + * Reg XMAC Register to read or write + * (p)Val Value or pointer to the value which should be read or written + * + * usage: XM_OUT16(IoC, MAC_1, XM_MMU_CMD, Value); + */ + +#define XMA(Mac, Reg) \ + ((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1)) + +#define XM_IN16(IoC, Mac, Reg, pVal) \ + SK_IN16((IoC), XMA((Mac), (Reg)), (pVal)) + +#define XM_OUT16(IoC, Mac, Reg, Val) \ + SK_OUT16((IoC), XMA((Mac), (Reg)), (Val)) + +#define XM_IN32(IoC, Mac, Reg, pVal) { \ + SK_IN16((IoC), XMA((Mac), (Reg)), \ + (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_LO]); \ + SK_IN16((IoC), XMA((Mac), (Reg+2)), \ + (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_HI]); \ +} + +#define XM_OUT32(IoC, Mac, Reg, Val) { \ + SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \ + SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)(((Val) >> 16) & 0xffffL));\ +} + +/* Remember: we are always writing to / reading from LITTLE ENDIAN memory */ + +#define XM_INADDR(IoC, Mac, Reg, pVal) { \ + SK_U16 Word; \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ + pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ + pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ +} + +#define XM_OUTADDR(IoC, Mac, Reg, pVal) { \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \ + (((SK_U16)(pByte[0]) & 0x00ff) | \ + (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ + SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \ + (((SK_U16)(pByte[2]) & 0x00ff) | \ + (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ + SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \ + (((SK_U16)(pByte[4]) & 0x00ff) | \ + (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ +} + +#define XM_INHASH(IoC, Mac, Reg, pVal) { \ + SK_U16 Word; \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ + pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ + pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \ + pByte[6] = (SK_U8)(Word & 0x00ff); \ + pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \ +} + +#define XM_OUTHASH(IoC, Mac, Reg, pVal) { \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \ + (((SK_U16)(pByte[0]) & 0x00ff)| \ + (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ + SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \ + (((SK_U16)(pByte[2]) & 0x00ff)| \ + (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ + SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \ + (((SK_U16)(pByte[4]) & 0x00ff)| \ + (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ + SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \ + (((SK_U16)(pByte[6]) & 0x00ff)| \ + (((SK_U16)(pByte[7]) << 8) & 0xff00))); \ +} + +/* + * macros to access the GMAC (YUKON only) + * + * GM_IN16(), to read a 16 bit register (e.g. GM_GP_STAT) + * GM_OUT16(), to write a 16 bit register (e.g. GM_GP_CTRL) + * GM_IN32(), to read a 32 bit register (e.g. GM_) + * GM_OUT32(), to write a 32 bit register (e.g. GM_) + * GM_INADDR(), to read a network address register (e.g. GM_SRC_ADDR_1L) + * GM_OUTADDR(), to write a network address register (e.g. GM_SRC_ADDR_2L) + * GM_INHASH(), to read the GM_MC_ADDR_H1 register + * GM_OUTHASH() to write the GM_MC_ADDR_H1 register + * + * para: + * Mac GMAC to access values: MAC_1 or MAC_2 + * IoC I/O context needed for SK I/O macros + * Reg GMAC Register to read or write + * (p)Val Value or pointer to the value which should be read or written + * + * usage: GM_OUT16(IoC, MAC_1, GM_GP_CTRL, Value); + */ + +#define GMA(Mac, Reg) \ + ((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg)) + +#define GM_IN16(IoC, Mac, Reg, pVal) \ + SK_IN16((IoC), GMA((Mac), (Reg)), (pVal)) + +#define GM_OUT16(IoC, Mac, Reg, Val) \ + SK_OUT16((IoC), GMA((Mac), (Reg)), (Val)) + +#define GM_IN32(IoC, Mac, Reg, pVal) { \ + SK_IN16((IoC), GMA((Mac), (Reg)), \ + (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_LO]); \ + SK_IN16((IoC), GMA((Mac), (Reg+4)), \ + (SK_U16 *)&((SK_U16 *)(pVal))[XM_WORD_HI]); \ +} + +#define GM_OUT32(IoC, Mac, Reg, Val) { \ + SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \ + SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)(((Val) >> 16) & 0xffffL));\ +} + +#define GM_INADDR(IoC, Mac, Reg, pVal) { \ + SK_U16 Word; \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ + pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ + pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ +} + +#define GM_OUTADDR(IoC, Mac, Reg, pVal) { \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \ + (((SK_U16)(pByte[0]) & 0x00ff) | \ + (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ + SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \ + (((SK_U16)(pByte[2]) & 0x00ff) | \ + (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ + SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \ + (((SK_U16)(pByte[4]) & 0x00ff) | \ + (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ +} + +#define GM_INHASH(IoC, Mac, Reg, pVal) { \ + SK_U16 Word; \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \ + pByte[0] = (SK_U8)(Word & 0x00ff); \ + pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \ + pByte[2] = (SK_U8)(Word & 0x00ff); \ + pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \ + pByte[4] = (SK_U8)(Word & 0x00ff); \ + pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \ + SK_IN16((IoC), GMA((Mac), (Reg+12)), &Word); \ + pByte[6] = (SK_U8)(Word & 0x00ff); \ + pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \ +} + +#define GM_OUTHASH(IoC, Mac, Reg, pVal) { \ + SK_U8 *pByte; \ + pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \ + SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \ + (((SK_U16)(pByte[0]) & 0x00ff)| \ + (((SK_U16)(pByte[1]) << 8) & 0xff00))); \ + SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \ + (((SK_U16)(pByte[2]) & 0x00ff)| \ + (((SK_U16)(pByte[3]) << 8) & 0xff00))); \ + SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \ + (((SK_U16)(pByte[4]) & 0x00ff)| \ + (((SK_U16)(pByte[5]) << 8) & 0xff00))); \ + SK_OUT16((IoC), GMA((Mac), (Reg+12)), (SK_U16) \ + (((SK_U16)(pByte[6]) & 0x00ff)| \ + (((SK_U16)(pByte[7]) << 8) & 0xff00))); \ +} + +/* + * Different MAC Types + */ +#define SK_MAC_XMAC 0 /* Xaqti XMAC II */ +#define SK_MAC_GMAC 1 /* Marvell GMAC */ + +/* + * Different PHY Types + */ +#define SK_PHY_XMAC 0 /* integrated in XMAC II */ +#define SK_PHY_BCOM 1 /* Broadcom BCM5400 */ +#define SK_PHY_LONE 2 /* Level One LXT1000 */ +#define SK_PHY_NAT 3 /* National DP83891 */ +#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1011S */ +#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1011S working on fiber */ + +/* + * PHY addresses (bits 12..8 of PHY address reg) + */ +#define PHY_ADDR_XMAC (0<<8) +#define PHY_ADDR_BCOM (1<<8) +#define PHY_ADDR_LONE (3<<8) +#define PHY_ADDR_NAT (0<<8) + +/* GPHY address (bits 15..11 of SMI control reg) */ +#define PHY_ADDR_MARV 0 + +/* + * macros to access the PHY + * + * PHY_READ() read a 16 bit value from the PHY + * PHY_WRITE() write a 16 bit value to the PHY + * + * para: + * IoC I/O context needed for SK I/O macros + * pPort Pointer to port struct for PhyAddr + * Mac XMAC to access values: MAC_1 or MAC_2 + * PhyReg PHY Register to read or write + * (p)Val Value or pointer to the value which should be read or + * written. + * + * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value); + * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never + * comes back. This is checked in DEBUG mode. + */ +#ifndef DEBUG +#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \ + SK_U16 Mmu; \ + \ + XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ + XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ + if ((pPort)->PhyType != SK_PHY_XMAC) { \ + do { \ + XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ + } while ((Mmu & XM_MMU_PHY_RDY) == 0); \ + XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ + } \ +} +#else +#define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \ + SK_U16 Mmu; \ + int __i = 0; \ + \ + XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ + XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ + if ((pPort)->PhyType != SK_PHY_XMAC) { \ + do { \ + XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ + __i++; \ + if (__i > 100000) { \ + SK_DBG_PRINTF("*****************************\n"); \ + SK_DBG_PRINTF("PHY_READ on uninitialized PHY\n"); \ + SK_DBG_PRINTF("*****************************\n"); \ + break; \ + } \ + } while ((Mmu & XM_MMU_PHY_RDY) == 0); \ + XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ + } \ +} +#endif /* DEBUG */ + +#define PHY_WRITE(IoC, pPort, Mac, PhyReg, Val) { \ + SK_U16 Mmu; \ + \ + if ((pPort)->PhyType != SK_PHY_XMAC) { \ + do { \ + XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ + } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \ + } \ + XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ + XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \ + if ((pPort)->PhyType != SK_PHY_XMAC) { \ + do { \ + XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ + } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \ + } \ +} + +/* + * Macro PCI_C() + * + * Use this macro to access PCI config register from the I/O space. + * + * para: + * Addr PCI configuration register to access. + * Values: PCI_VENDOR_ID ... PCI_VPD_ADR_REG, + * + * usage SK_IN16(pAC, PCI_C(PCI_VENDOR_ID), pVal); + */ +#define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */ + +/* + * Macro SK_HW_ADDR(Base, Addr) + * + * Calculates the effective HW address + * + * para: + * Base I/O or memory base address + * Addr Address offset + * + * usage: May be used in SK_INxx and SK_OUTxx macros + * #define SK_IN8(pAC, Addr, pVal) ...\ + * *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr))) + */ +#ifdef SK_MEM_MAPPED_IO +#define SK_HW_ADDR(Base, Addr) ((Base) + (Addr)) +#else /* SK_MEM_MAPPED_IO */ +#define SK_HW_ADDR(Base, Addr) \ + ((Base) + (((Addr) & 0x7f) | (((Addr) >> 7 > 0) ? 0x80 : 0))) +#endif /* SK_MEM_MAPPED_IO */ + +#define SZ_LONG (sizeof(SK_U32)) + +/* + * Macro SK_HWAC_LINK_LED() + * + * Use this macro to set the link LED mode. + * para: + * pAC Pointer to adapter context struct + * IoC I/O context needed for SK I/O macros + * Port Port number + * Mode Mode to set for this LED + */ +#define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \ + SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode); + + +/* typedefs *******************************************************************/ + + +/* function prototypes ********************************************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_SKGEHW_H */ diff --git a/drivers/sk98lin/h/skgehwt.h b/drivers/sk98lin/h/skgehwt.h new file mode 100644 index 000000000..8aa9edd71 --- /dev/null +++ b/drivers/sk98lin/h/skgehwt.h @@ -0,0 +1,74 @@ +/****************************************************************************** + * + * Name: skhwt.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.5 $ + * Date: $Date: 1999/11/22 13:54:24 $ + * Purpose: Defines for the hardware timer functions + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgehwt.h,v $ + * Revision 1.5 1999/11/22 13:54:24 cgoos + * Changed license header to GPL. + * + * Revision 1.4 1998/08/19 09:50:58 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.3 1998/08/14 07:09:29 gklug + * fix: chg pAc -> pAC + * + * Revision 1.2 1998/08/07 12:54:21 gklug + * fix: first compiled version + * + * Revision 1.1 1998/08/07 09:32:58 gklug + * first version + * + * + * + * + * + ******************************************************************************/ + +/* + * SKGEHWT.H contains all defines and types for the timer functions + */ + +#ifndef _SKGEHWT_H_ +#define _SKGEHWT_H_ + +/* + * SK Hardware Timer + * - needed wherever the HWT module is used + * - use in Adapters context name pAC->Hwt + */ +typedef struct s_Hwt { + SK_U32 TStart ; /* HWT start */ + SK_U32 TStop ; /* HWT stop */ + int TActive ; /* HWT: flag : active/inactive */ +} SK_HWT; + +extern void SkHwtInit(SK_AC *pAC, SK_IOC Ioc); +extern void SkHwtStart(SK_AC *pAC, SK_IOC Ioc, SK_U32 Time); +extern void SkHwtStop(SK_AC *pAC, SK_IOC Ioc); +extern SK_U32 SkHwtRead(SK_AC *pAC,SK_IOC Ioc); +extern void SkHwtIsr(SK_AC *pAC, SK_IOC Ioc); +#endif /* _SKGEHWT_H_ */ diff --git a/drivers/sk98lin/h/skgei2c.h b/drivers/sk98lin/h/skgei2c.h new file mode 100644 index 000000000..e639f733c --- /dev/null +++ b/drivers/sk98lin/h/skgei2c.h @@ -0,0 +1,299 @@ +/****************************************************************************** + * + * Name: skgei2c.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.23 $ + * Date: $Date: 2002/12/19 14:34:27 $ + * Purpose: Special GEnesis defines for TWSI + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgei2c.h,v $ + * Revision 1.23 2002/12/19 14:34:27 rschmidt + * Added cast in macros SK_I2C_SET_BIT() and SK_I2C_CLR_BIT() + * Editorial changes (TWSI) + * + * Revision 1.22 2002/10/14 16:45:56 rschmidt + * Editorial changes (TWSI) + * + * Revision 1.21 2002/08/13 08:42:24 rschmidt + * Changed define for SK_MIN_SENSORS back to 5 + * Merged defines for PHY PLL 3V3 voltage (A and B) + * Editorial changes + * + * Revision 1.20 2002/08/06 09:43:56 jschmalz + * Extensions and changes for Yukon + * + * Revision 1.19 2002/08/02 12:00:08 rschmidt + * Added defines for YUKON sensors + * Editorial changes + * + * Revision 1.18 2001/08/16 12:44:33 afischer + * LM80 sensor init values corrected + * + * Revision 1.17 1999/11/22 13:55:25 cgoos + * Changed license header to GPL. + * + * Revision 1.16 1999/11/12 08:24:10 malthoff + * Change voltage warning and error limits + * (warning +-5%, error +-10%). + * + * Revision 1.15 1999/09/14 14:14:43 malthoff + * The 1000BT Dual Link adapter has got only one Fan. + * The second Fan has been removed. + * + * Revision 1.14 1999/05/27 13:40:50 malthoff + * Fan Divisor = 1. Assuming fan with 6500 rpm. + * + * Revision 1.13 1999/05/20 14:56:55 malthoff + * Bug Fix: Missing brace in SK_LM80_FAN_FAKTOR. + * + * Revision 1.12 1999/05/20 09:22:00 cgoos + * Changes for 1000Base-T (Fan sensors). + * + * Revision 1.11 1998/10/14 05:57:22 cgoos + * Fixed compilation warnings. + * + * Revision 1.10 1998/09/04 08:37:00 malthoff + * bugfix: correct the SK_I2C_GET_CTL() macro. + * + * Revision 1.9 1998/08/25 06:10:03 gklug + * add: thresholds for all sensors + * + * Revision 1.8 1998/08/20 11:37:42 gklug + * chg: change Ioc to IoC + * + * Revision 1.7 1998/08/20 08:53:11 gklug + * fix: compiler errors + * add: Threshold values + * + * Revision 1.6 1998/08/17 11:37:09 malthoff + * Bugfix in SK_I2C_CTL macro. The parameter 'dev' + * has to be shifted 9 bits. + * + * Revision 1.5 1998/08/17 06:52:21 malthoff + * Remove unrequired macros. + * Add macros for accessing TWSI SW register. + * + * Revision 1.4 1998/08/13 08:30:18 gklug + * add: conversion factors for read values + * add: new state SEN_VALEXT to read extension value of temperature sensor + * + * Revision 1.3 1998/08/12 13:37:56 gklug + * rmv: error numbers and messages + * + * Revision 1.2 1998/08/11 07:54:38 gklug + * add: sensor states for GE sensors + * add: Macro to access TWSI hardware register + * chg: Error messages for TWSI errors + * + * Revision 1.1 1998/07/17 11:27:56 gklug + * Created. + * + * + * + ******************************************************************************/ + +/* + * SKGEI2C.H contains all SK-98xx specific defines for the TWSI handling + */ + +#ifndef _INC_SKGEI2C_H_ +#define _INC_SKGEI2C_H_ + +/* + * Macros to access the B2_I2C_CTRL + */ +#define SK_I2C_CTL(IoC, flag, dev, reg, burst) \ + SK_OUT32(IoC, B2_I2C_CTRL,\ + (flag ? 0x80000000UL : 0x0L) | \ + (((SK_U32) reg << 16) & I2C_ADDR) | \ + (((SK_U32) dev << 9) & I2C_DEV_SEL) | \ + (( burst << 4) & I2C_BURST_LEN)) + +#define SK_I2C_STOP(IoC) { \ + SK_U32 I2cCtrl; \ + SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \ + SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \ +} + +#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl) + +/* + * Macros to access the TWSI SW Registers + */ +#define SK_I2C_SET_BIT(IoC, SetBits) { \ + SK_U8 OrgBits; \ + SK_IN8(IoC, B2_I2C_SW, &OrgBits); \ + SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \ +} + +#define SK_I2C_CLR_BIT(IoC, ClrBits) { \ + SK_U8 OrgBits; \ + SK_IN8(IoC, B2_I2C_SW, &OrgBits); \ + SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \ +} + +#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw) + +/* + * define the possible sensor states + */ +#define SK_SEN_IDLE 0 /* Idle: sensor not read */ +#define SK_SEN_VALUE 1 /* Value Read cycle */ +#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */ + +/* + * Conversion factor to convert read Voltage sensor to milli Volt + * Conversion factor to convert read Temperature sensor to 10th degree Celsius + */ +#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */ +#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */ +#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for the + * extension value + */ +#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2)) +/* formula: counter = (22500*60)/(rpm * divisor * pulses/2) + * assuming: 6500rpm, 4 pulses, divisor 1 + */ + +/* + * Define sensor management data + * Maximum is reached on copperfield with dual Broadcom. + * Board specific maximum is in pAC->I2c.MaxSens + */ +#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */ +#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */ + +/* + * To watch the statemachine (JS) use the timer in two ways instead of one as hitherto + */ +#define SK_TIMER_WATCH_STATEMACHINE 0 /* Watch the statemachine to finish in a specific time */ +#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */ + + +/* + * Defines for the individual Thresholds + */ + +/* Temperature sensor */ +#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */ +#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */ +#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */ +#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */ + +/* VCC which should be 5 V */ +#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */ +#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */ +#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */ +#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */ + +/* + * VIO may be 5 V or 3.3 V. Initialization takes two parts: + * 1. Initialize lowest lower limit and highest higher limit. + * 2. After the first value is read correct the upper or the lower limit to + * the appropriate C constant. + * + * Warning limits are +-5% of the exepected voltage. + * Error limits are +-10% of the expected voltage. + */ + +/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */ + +#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */ +#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */ + /* 5000 mVolt */ +#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */ +#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */ + +#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */ + +/* correction values for the second pass */ +#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */ +#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */ + /* 3300 mVolt */ +#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */ +#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */ + + +/* + * VDD voltage + */ +#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */ +#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */ +#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */ +#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */ + +/* + * PHY PLL 3V3 voltage + */ +#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */ +#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */ +#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */ +#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */ + +/* + * VAUX (YUKON only) + */ +#define SK_SEN_VAUX_3V3_HIGH_ERR 3630 /* Voltage VAUX High Err Threshold */ +#define SK_SEN_VAUX_3V3_HIGH_WARN 3476 /* Voltage VAUX High Warn Threshold */ +#define SK_SEN_VAUX_3V3_LOW_WARN 3146 /* Voltage VAUX Low Warn Threshold */ +#define SK_SEN_VAUX_3V3_LOW_ERR 2970 /* Voltage VAUX Low Err Threshold */ +#define SK_SEN_VAUX_0V_WARN_ERR 0 /* if VAUX not present */ +#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */ + +/* + * PHY 2V5 voltage + */ +#define SK_SEN_PHY_2V5_HIGH_ERR 2750 /* Voltage PHY High Err Threshold */ +#define SK_SEN_PHY_2V5_HIGH_WARN 2640 /* Voltage PHY High Warn Threshold */ +#define SK_SEN_PHY_2V5_LOW_WARN 2376 /* Voltage PHY Low Warn Threshold */ +#define SK_SEN_PHY_2V5_LOW_ERR 2222 /* Voltage PHY Low Err Threshold */ + +/* + * ASIC Core 1V5 voltage (YUKON only) + */ +#define SK_SEN_CORE_1V5_HIGH_ERR 1650 /* Voltage ASIC Core High Err Threshold */ +#define SK_SEN_CORE_1V5_HIGH_WARN 1575 /* Voltage ASIC Core High Warn Threshold */ +#define SK_SEN_CORE_1V5_LOW_WARN 1425 /* Voltage ASIC Core Low Warn Threshold */ +#define SK_SEN_CORE_1V5_LOW_ERR 1350 /* Voltage ASIC Core Low Err Threshold */ + +/* + * FAN 1 speed + */ +/* assuming: 6500rpm +-15%, 4 pulses, + * warning at: 80 % + * error at: 70 % + * no upper limit + */ +#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */ +#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */ +#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */ +#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */ + +/* + * Some Voltages need dynamic thresholds + */ +#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */ +#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */ +#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */ + +extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); +#endif /* n_INC_SKGEI2C_H */ diff --git a/drivers/sk98lin/h/skgeinit.h b/drivers/sk98lin/h/skgeinit.h new file mode 100644 index 000000000..cdddef92b --- /dev/null +++ b/drivers/sk98lin/h/skgeinit.h @@ -0,0 +1,1113 @@ +/****************************************************************************** + * + * Name: skgeinit.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.75 $ + * Date: $Date: 2003/02/05 13:36:39 $ + * Purpose: Structures and prototypes for the GE Init Module + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgeinit.h,v $ + * Revision 1.75 2003/02/05 13:36:39 rschmidt + * Added define SK_FACT_78 for YUKON's Host Clock of 78.12 MHz + * Editorial changes + * + * Revision 1.74 2003/01/28 09:39:16 rschmidt + * Added entry GIYukonLite in s_GeInit structure + * Editorial changes + * + * Revision 1.73 2002/11/15 12:47:25 rschmidt + * Replaced error message SKERR_HWI_E024 for Cable Diagnostic with + * Rx queue error in SkGeStopPort(). + * + * Revision 1.72 2002/11/12 17:08:35 rschmidt + * Added entries for Cable Diagnostic to Port structure + * Added entries GIPciSlot64 and GIPciClock66 in s_GeInit structure + * Added error message for Cable Diagnostic + * Added prototypes for SkGmCableDiagStatus() + * Editorial changes + * + * Revision 1.71 2002/10/21 11:26:10 mkarl + * Changed interface of SkGeInitAssignRamToQueues(). + * + * Revision 1.70 2002/10/14 08:21:32 rschmidt + * Changed type of GICopperType, GIVauxAvail to SK_BOOL + * Added entry PRxOverCnt to Port structure + * Added entry GIYukon32Bit in s_GeInit structure + * Editorial changes + * + * Revision 1.69 2002/10/09 16:57:15 mkarl + * Added some constants and macros for SkGeInitAssignRamToQueues(). + * + * Revision 1.68 2002/09/12 08:58:51 rwahl + * Retrieve counters needed for XMAC errata workarounds directly because + * PNMI returns corrected counter values (e.g. #10620). + * + * Revision 1.67 2002/08/16 14:40:30 rschmidt + * Added entries GIGenesis and GICopperType in s_GeInit structure + * Added prototypes for SkMacHashing() + * Editorial changes + * + * Revision 1.66 2002/08/12 13:27:21 rschmidt + * Added defines for Link speed capabilities + * Added entry PLinkSpeedCap to Port structure + * Added entry GIVauxAvail in s_GeInit structure + * Added prototypes for SkMacPromiscMode() + * Editorial changes + * + * Revision 1.65 2002/08/08 15:46:18 rschmidt + * Added define SK_PHY_ACC_TO for PHY access timeout + * Added define SK_XM_RX_HI_WM for XMAC Rx High Watermark + * Added define SK_MIN_TXQ_SIZE for Min RAM Buffer Tx Queue Size + * Added entry PhyId1 to Port structure + * + * Revision 1.64 2002/07/23 16:02:56 rschmidt + * Added entry GIWolOffs in s_GeInit struct (HW-Bug in YUKON 1st rev.) + * Added prototypes for: SkGePhyRead(), SkGePhyWrite() + * + * Revision 1.63 2002/07/18 08:17:38 rwahl + * Corrected definitions for SK_LSPEED_xxx & SK_LSPEED_STAT_xxx. + * + * Revision 1.62 2002/07/17 18:21:55 rwahl + * Added SK_LSPEED_INDETERMINATED define. + * + * Revision 1.61 2002/07/17 17:16:03 rwahl + * - MacType now member of GIni struct. + * - Struct alignment to 32bit. + * - Editorial change. + * + * Revision 1.60 2002/07/15 18:23:39 rwahl + * Added GeMacFunc to GE Init structure. + * Added prototypes for SkXmUpdateStats(), SkGmUpdateStats(), + * SkXmMacStatistic(), SkGmMacStatistic(), SkXmResetCounter(), + * SkGmResetCounter(), SkXmOverflowStatus(), SkGmOverflowStatus(). + * Added defines for current link speed state. + * Added ERRMSG defintions for MacUpdateStat() & MacStatistics(). + * + * Revision 1.59 2002/07/15 15:40:22 rschmidt + * Added entry PLinkSpeedUsed to Port structure + * Editorial changes + * + * Revision 1.58 2002/06/10 09:36:30 rschmidt + * Editorial changes. + * + * Revision 1.57 2002/06/05 08:18:00 rschmidt + * Corrected alignment in Port Structure + * Added new prototypes for GMAC + * Editorial changes + * + * Revision 1.56 2002/04/25 11:38:12 rschmidt + * Added defines for Link speed values + * Added defines for Loopback parameters for MAC and PHY + * Removed entry PRxCmd from Port structure + * Added entry PLinkSpeed to Port structure + * Added entries GIChipId and GIChipRev to GE Init structure + * Removed entry GIAnyPortAct from GE Init structure + * Added prototypes for: SkMacInit(), SkMacInitPhy(), + * SkMacRxTxDisable(), SkMacSoftRst(), SkMacHardRst(), SkMacIrq(), + * SkMacIrqDisable(), SkMacFlushTxFifo(), SkMacFlushRxFifo(), + * SkMacAutoNegDone(), SkMacAutoNegLipaPhy(), SkMacSetRxTxEn(), + * SkXmPhyRead(), SkXmPhyRead(), SkGmPhyWrite(), SkGmPhyWrite(); + * Removed prototypes for static functions in SkXmac2.c + * Editorial changes + * + * Revision 1.55 2002/02/26 15:24:53 rwahl + * Fix: no link with manual configuration (#10673). The previous fix for + * #10639 was removed. So for RLMT mode = CLS the RLMT may switch to + * misconfigured port. It should not occur for the other RLMT modes. + * + * Revision 1.54 2002/01/18 16:52:52 rwahl + * Editorial corrections. + * + * Revision 1.53 2001/11/20 09:19:58 rwahl + * Reworked bugfix #10639 (no dependency to RLMT mode). + * + * Revision 1.52 2001/10/26 07:52:23 afischer + * Port switching bug in `check local link` mode + * + * Revision 1.51 2001/02/09 12:26:38 cgoos + * Inserted #ifdef DIAG for half duplex workaround timer. + * + * Revision 1.50 2001/02/07 07:56:40 rassmann + * Corrected copyright. + * + * Revision 1.49 2001/01/31 15:32:18 gklug + * fix: problem with autosensing an SR8800 switch + * add: counter for autoneg timeouts + * + * Revision 1.48 2000/11/09 11:30:10 rassmann + * WA: Waiting after releasing reset until BCom chip is accessible. + * + * Revision 1.47 2000/10/18 12:22:40 cgoos + * Added workaround for half duplex hangup. + * + * Revision 1.46 2000/08/10 11:28:00 rassmann + * Editorial changes. + * Preserving 32-bit alignment in structs for the adapter context. + * + * Revision 1.45 1999/11/22 13:56:19 cgoos + * Changed license header to GPL. + * + * Revision 1.44 1999/10/26 07:34:15 malthoff + * The define SK_LNK_ON has been lost in v1.41. + * + * Revision 1.43 1999/10/06 09:30:16 cgoos + * Changed SK_XM_THR_JUMBO. + * + * Revision 1.42 1999/09/16 12:58:26 cgoos + * Changed SK_LED_STANDY macro to be independent of HW link sync. + * + * Revision 1.41 1999/07/30 06:56:14 malthoff + * Correct comment for SK_MS_STAT_UNSET. + * + * Revision 1.40 1999/05/27 13:38:46 cgoos + * Added SK_BMU_TX_WM. + * Made SK_BMU_TX_WM and SK_BMU_RX_WM user-definable. + * Changed XMAC Tx treshold to max. values. + * + * Revision 1.39 1999/05/20 14:35:26 malthoff + * Remove prototypes for SkGeLinkLED(). + * + * Revision 1.38 1999/05/19 11:59:12 cgoos + * Added SK_MS_CAP_INDETERMINATED define. + * + * Revision 1.37 1999/05/19 07:32:33 cgoos + * Changes for 1000Base-T. + * LED-defines for HWAC_LINK_LED macro. + * + * Revision 1.36 1999/04/08 14:00:24 gklug + * add:Port struct field PLinkResCt + * + * Revision 1.35 1999/03/25 07:43:07 malthoff + * Add error string for SKERR_HWI_E018MSG. + * + * Revision 1.34 1999/03/12 16:25:57 malthoff + * Remove PPollRxD and PPollTxD. + * Add SKERR_HWI_E017MSG. and SK_DPOLL_MAX. + * + * Revision 1.33 1999/03/12 13:34:41 malthoff + * Add Autonegotiation error codes. + * Change defines for parameter Mode in SkXmSetRxCmd(). + * Replace __STDC__ by SK_KR_PROTO. + * + * Revision 1.32 1999/01/25 14:40:20 mhaveman + * Added new return states for the virtual management port if multiple + * ports are active but differently configured. + * + * Revision 1.31 1998/12/11 15:17:02 gklug + * add: Link partnet autoneg states : Unknown Manual and Auto-negotiation + * + * Revision 1.30 1998/12/07 12:17:04 gklug + * add: Link Partner auto-negotiation flag + * + * Revision 1.29 1998/12/01 10:54:42 gklug + * add: variables for XMAC Errata + * + * Revision 1.28 1998/12/01 10:14:15 gklug + * add: PIsave saves the Interrupt status word + * + * Revision 1.27 1998/11/26 15:24:52 mhaveman + * Added link status states SK_LMODE_STAT_AUTOHALF and + * SK_LMODE_STAT_AUTOFULL which are used by PNMI. + * + * Revision 1.26 1998/11/26 14:53:01 gklug + * add:autoNeg Timeout variable + * + * Revision 1.25 1998/11/26 08:58:50 gklug + * add: Link Mode configuration (AUTO Sense mode) + * + * Revision 1.24 1998/11/24 13:30:27 gklug + * add: PCheckPar to port struct + * + * Revision 1.23 1998/11/18 13:23:26 malthoff + * Add SK_PKT_TO_MAX. + * + * Revision 1.22 1998/11/18 13:19:54 gklug + * add: PPrevShorts and PLinkBroken to port struct for WA XMAC Errata #C1 + * + * Revision 1.21 1998/10/26 08:02:57 malthoff + * Add GIRamOffs. + * + * Revision 1.20 1998/10/19 07:28:37 malthoff + * Add prototype for SkGeInitRamIface(). + * + * Revision 1.19 1998/10/14 14:47:48 malthoff + * SK_TIMER should not be defined for Diagnostics. + * Add SKERR_HWI_E015MSG and SKERR_HWI_E016MSG. + * + * Revision 1.18 1998/10/14 14:00:03 gklug + * add: timer to port struct for workaround of Errata #2 + * + * Revision 1.17 1998/10/14 11:23:09 malthoff + * Add prototype for SkXmAutoNegDone(). + * Fix SkXmSetRxCmd() prototype statement. + * + * Revision 1.16 1998/10/14 05:42:29 gklug + * add: HWLinkUp flag to Port struct + * + * Revision 1.15 1998/10/09 08:26:33 malthoff + * Rename SK_RB_ULPP_B to SK_RB_LLPP_B. + * + * Revision 1.14 1998/10/09 07:11:13 malthoff + * bug fix: SK_FACT_53 is 85 not 117. + * Rework time out init values. + * Add GIPortUsage and corresponding defines. + * Add some error log messages. + * + * Revision 1.13 1998/10/06 14:13:14 malthoff + * Add prototype for SkGeLoadLnkSyncCnt(). + * + * Revision 1.12 1998/10/05 11:29:53 malthoff + * bug fix: A comment was not closed. + * + * Revision 1.11 1998/10/05 08:01:59 malthoff + * Add default Timeout- Threshold- and + * Watermark constants. Add QRam start and end + * variables. Also add vars to store the polling + * mode and receive command. Add new Error Log + * Messages and function prototypes. + * + * Revision 1.10 1998/09/28 13:34:48 malthoff + * Add mode bits for LED functions. + * Move Autoneg and Flow Ctrl bits from shgesirq.h + * Add the required Error Log Entries + * and Function Prototypes. + * + * Revision 1.9 1998/09/16 14:38:41 malthoff + * Rework the SK_LNK_xxx defines. + * Add error log message defines. + * Add prototypes for skxmac2.c + * + * Revision 1.8 1998/09/11 05:29:18 gklug + * add: init state of a port + * + * Revision 1.7 1998/09/08 08:35:52 gklug + * add: defines of the Init Levels + * + * Revision 1.6 1998/09/03 13:48:42 gklug + * add: Link strati, capabilities to Port struct + * + * Revision 1.5 1998/09/03 13:30:59 malthoff + * Add SK_LNK_BLINK and SK_LNK_PERM. + * + * Revision 1.4 1998/09/03 09:55:31 malthoff + * Add constants for parameters Dir and RstMode + * when calling SkGeStopPort(). + * Rework the prototype section. + * Add Queue Address offsets PRxQOff, PXsQOff, and PXaQOff. + * Remove Ioc with IoC. + * + * Revision 1.3 1998/08/19 09:11:54 gklug + * fix: struct are removed from c-source (see CCC) + * add: typedefs for all structs + * + * Revision 1.2 1998/07/28 12:38:26 malthoff + * The prototypes got the parameter 'IoC'. + * + * Revision 1.1 1998/07/23 09:50:24 malthoff + * Created. + * + ******************************************************************************/ + +#ifndef __INC_SKGEINIT_H_ +#define __INC_SKGEINIT_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines ********************************************************************/ + +/* modifying Link LED behaviour (used with SkGeLinkLED()) */ +#define SK_LNK_OFF LED_OFF +#define SK_LNK_ON (LED_ON | LED_BLK_OFF | LED_SYNC_OFF) +#define SK_LNK_BLINK (LED_ON | LED_BLK_ON | LED_SYNC_ON) +#define SK_LNK_PERM (LED_ON | LED_BLK_OFF | LED_SYNC_ON) +#define SK_LNK_TST (LED_ON | LED_BLK_ON | LED_SYNC_OFF) + +/* parameter 'Mode' when calling SK_HWAC_LINK_LED() */ +#define SK_LED_OFF LED_OFF +#define SK_LED_ACTIVE (LED_ON | LED_BLK_OFF | LED_SYNC_OFF) +#define SK_LED_STANDBY (LED_ON | LED_BLK_ON | LED_SYNC_OFF) + +/* addressing LED Registers in SkGeXmitLED() */ +#define XMIT_LED_INI 0 +#define XMIT_LED_CNT (RX_LED_VAL - RX_LED_INI) +#define XMIT_LED_CTRL (RX_LED_CTRL- RX_LED_INI) +#define XMIT_LED_TST (RX_LED_TST - RX_LED_INI) + +/* parameter 'Mode' when calling SkGeXmitLED() */ +#define SK_LED_DIS 0 +#define SK_LED_ENA 1 +#define SK_LED_TST 2 + +/* Counter and Timer constants, for a host clock of 62.5 MHz */ +#define SK_XMIT_DUR 0x002faf08L /* 50 ms */ +#define SK_BLK_DUR 0x01dcd650L /* 500 ms */ + +#define SK_DPOLL_DEF 0x00ee6b28L /* 250 ms at 62.5 MHz */ + +#define SK_DPOLL_MAX 0x00ffffffL /* 268 ms at 62.5 MHz */ + /* 215 ms at 78.12 MHz */ + +#define SK_FACT_62 100 /* is given in percent */ +#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */ +#define SK_FACT_78 125 /* on YUKON: 78.12 MHz */ + +/* Timeout values */ +#define SK_MAC_TO_53 72 /* MAC arbiter timeout */ +#define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */ +#define SK_PKT_TO_MAX 0xffff /* Maximum value */ +#define SK_RI_TO_53 36 /* RAM interface timeout */ + +#define SK_PHY_ACC_TO 600000 /* PHY access timeout */ + +/* RAM Buffer High Pause Threshold values */ +#define SK_RB_ULPP ( 8 * 1024) /* Upper Level in kB/8 */ +#define SK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ +#define SK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ + +#ifndef SK_BMU_RX_WM +#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ +#endif +#ifndef SK_BMU_TX_WM +#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ +#endif + +/* XMAC II Rx High Watermark */ +#define SK_XM_RX_HI_WM 0x05aa /* 1450 */ + +/* XMAC II Tx Threshold */ +#define SK_XM_THR_REDL 0x01fb /* .. for redundant link usage */ +#define SK_XM_THR_SL 0x01fb /* .. for single link adapters */ +#define SK_XM_THR_MULL 0x01fb /* .. for multiple link usage */ +#define SK_XM_THR_JUMBO 0x03fc /* .. for jumbo frame usage */ + +/* values for GIPortUsage */ +#define SK_RED_LINK 1 /* redundant link usage */ +#define SK_MUL_LINK 2 /* multiple link usage */ +#define SK_JUMBO_LINK 3 /* driver uses jumbo frames */ + +/* Minimum RAM Buffer Rx Queue Size */ +#define SK_MIN_RXQ_SIZE 16 /* 16 kB */ + +/* Minimum RAM Buffer Tx Queue Size */ +#define SK_MIN_TXQ_SIZE 16 /* 16 kB */ + +/* Queue Size units */ +#define QZ_UNITS 0x7 +#define QZ_STEP 8 + +/* Percentage of queue size from whole memory */ +/* 80 % for receive */ +#define RAM_QUOTA_RX 80L +/* 0% for sync transfer */ +#define RAM_QUOTA_SYNC 0L +/* the rest (20%) is taken for async transfer */ + +/* Get the rounded queue size in Bytes in 8k steps */ +#define ROUND_QUEUE_SIZE(SizeInBytes) \ + ((((unsigned long) (SizeInBytes) + (QZ_STEP*1024L)-1) / 1024) & \ + ~(QZ_STEP-1)) + +/* Get the rounded queue size in KBytes in 8k steps */ +#define ROUND_QUEUE_SIZE_KB(Kilobytes) \ + ROUND_QUEUE_SIZE((Kilobytes) * 1024L) + +/* Types of RAM Buffer Queues */ +#define SK_RX_SRAM_Q 1 /* small receive queue */ +#define SK_RX_BRAM_Q 2 /* big receive queue */ +#define SK_TX_RAM_Q 3 /* small or big transmit queue */ + +/* parameter 'Dir' when calling SkGeStopPort() */ +#define SK_STOP_TX 1 /* Stops the transmit path, resets the XMAC */ +#define SK_STOP_RX 2 /* Stops the receive path */ +#define SK_STOP_ALL 3 /* Stops Rx and Tx path, resets the XMAC */ + +/* parameter 'RstMode' when calling SkGeStopPort() */ +#define SK_SOFT_RST 1 /* perform a software reset */ +#define SK_HARD_RST 2 /* perform a hardware reset */ + +/* Init Levels */ +#define SK_INIT_DATA 0 /* Init level 0: init data structures */ +#define SK_INIT_IO 1 /* Init level 1: init with IOs */ +#define SK_INIT_RUN 2 /* Init level 2: init for run time */ + +/* Link Mode Parameter */ +#define SK_LMODE_HALF 1 /* Half Duplex Mode */ +#define SK_LMODE_FULL 2 /* Full Duplex Mode */ +#define SK_LMODE_AUTOHALF 3 /* AutoHalf Duplex Mode */ +#define SK_LMODE_AUTOFULL 4 /* AutoFull Duplex Mode */ +#define SK_LMODE_AUTOBOTH 5 /* AutoBoth Duplex Mode */ +#define SK_LMODE_AUTOSENSE 6 /* configured mode auto sensing */ +#define SK_LMODE_INDETERMINATED 7 /* indeterminated */ + +/* Auto-negotiation timeout in 100ms granularity */ +#define SK_AND_MAX_TO 6 /* Wait 600 msec before link comes up */ + +/* Auto-negotiation error codes */ +#define SK_AND_OK 0 /* no error */ +#define SK_AND_OTHER 1 /* other error than below */ +#define SK_AND_DUP_CAP 2 /* Duplex capabilities error */ + + +/* Link Speed Capabilities */ +#define SK_LSPEED_CAP_AUTO (1<<0) /* Automatic resolution */ +#define SK_LSPEED_CAP_10MBPS (1<<1) /* 10 Mbps */ +#define SK_LSPEED_CAP_100MBPS (1<<2) /* 100 Mbps */ +#define SK_LSPEED_CAP_1000MBPS (1<<3) /* 1000 Mbps */ +#define SK_LSPEED_CAP_INDETERMINATED (1<<4) /* indeterminated */ + +/* Link Speed Parameter */ +#define SK_LSPEED_AUTO 1 /* Automatic resolution */ +#define SK_LSPEED_10MBPS 2 /* 10 Mbps */ +#define SK_LSPEED_100MBPS 3 /* 100 Mbps */ +#define SK_LSPEED_1000MBPS 4 /* 1000 Mbps */ +#define SK_LSPEED_INDETERMINATED 5 /* indeterminated */ + +/* Link Speed Current State */ +#define SK_LSPEED_STAT_UNKNOWN 1 +#define SK_LSPEED_STAT_10MBPS 2 +#define SK_LSPEED_STAT_100MBPS 3 +#define SK_LSPEED_STAT_1000MBPS 4 +#define SK_LSPEED_STAT_INDETERMINATED 5 + + +/* Link Capability Parameter */ +#define SK_LMODE_CAP_HALF (1<<0) /* Half Duplex Mode */ +#define SK_LMODE_CAP_FULL (1<<1) /* Full Duplex Mode */ +#define SK_LMODE_CAP_AUTOHALF (1<<2) /* AutoHalf Duplex Mode */ +#define SK_LMODE_CAP_AUTOFULL (1<<3) /* AutoFull Duplex Mode */ +#define SK_LMODE_CAP_INDETERMINATED (1<<4) /* indeterminated */ + +/* Link Mode Current State */ +#define SK_LMODE_STAT_UNKNOWN 1 /* Unknown Duplex Mode */ +#define SK_LMODE_STAT_HALF 2 /* Half Duplex Mode */ +#define SK_LMODE_STAT_FULL 3 /* Full Duplex Mode */ +#define SK_LMODE_STAT_AUTOHALF 4 /* Half Duplex Mode obtained by Auto-Neg */ +#define SK_LMODE_STAT_AUTOFULL 5 /* Full Duplex Mode obtained by Auto-Neg */ +#define SK_LMODE_STAT_INDETERMINATED 6 /* indeterminated */ + +/* Flow Control Mode Parameter (and capabilities) */ +#define SK_FLOW_MODE_NONE 1 /* No Flow-Control */ +#define SK_FLOW_MODE_LOC_SEND 2 /* Local station sends PAUSE */ +#define SK_FLOW_MODE_SYMMETRIC 3 /* Both stations may send PAUSE */ +#define SK_FLOW_MODE_SYM_OR_REM 4 /* Both stations may send PAUSE or + * just the remote station may send PAUSE + */ +#define SK_FLOW_MODE_INDETERMINATED 5 /* indeterminated */ + +/* Flow Control Status Parameter */ +#define SK_FLOW_STAT_NONE 1 /* No Flow Control */ +#define SK_FLOW_STAT_REM_SEND 2 /* Remote Station sends PAUSE */ +#define SK_FLOW_STAT_LOC_SEND 3 /* Local station sends PAUSE */ +#define SK_FLOW_STAT_SYMMETRIC 4 /* Both station may send PAUSE */ +#define SK_FLOW_STAT_INDETERMINATED 5 /* indeterminated */ + +/* Master/Slave Mode Capabilities */ +#define SK_MS_CAP_AUTO (1<<0) /* Automatic resolution */ +#define SK_MS_CAP_MASTER (1<<1) /* This station is master */ +#define SK_MS_CAP_SLAVE (1<<2) /* This station is slave */ +#define SK_MS_CAP_INDETERMINATED (1<<3) /* indeterminated */ + +/* Set Master/Slave Mode Parameter (and capabilities) */ +#define SK_MS_MODE_AUTO 1 /* Automatic resolution */ +#define SK_MS_MODE_MASTER 2 /* This station is master */ +#define SK_MS_MODE_SLAVE 3 /* This station is slave */ +#define SK_MS_MODE_INDETERMINATED 4 /* indeterminated */ + +/* Master/Slave Status Parameter */ +#define SK_MS_STAT_UNSET 1 /* The M/S status is not set */ +#define SK_MS_STAT_MASTER 2 /* This station is Master */ +#define SK_MS_STAT_SLAVE 3 /* This station is Dlave */ +#define SK_MS_STAT_FAULT 4 /* M/S resolution failed */ +#define SK_MS_STAT_INDETERMINATED 5 /* indeterminated */ + +/* parameter 'Mode' when calling SkXmSetRxCmd() */ +#define SK_STRIP_FCS_ON (1<<0) /* Enable FCS stripping of Rx frames */ +#define SK_STRIP_FCS_OFF (1<<1) /* Disable FCS stripping of Rx frames */ +#define SK_STRIP_PAD_ON (1<<2) /* Enable pad byte stripping of Rx fr */ +#define SK_STRIP_PAD_OFF (1<<3) /* Disable pad byte stripping of Rx fr */ +#define SK_LENERR_OK_ON (1<<4) /* Don't chk fr for in range len error */ +#define SK_LENERR_OK_OFF (1<<5) /* Check frames for in range len error */ +#define SK_BIG_PK_OK_ON (1<<6) /* Don't set Rx Error bit for big frames */ +#define SK_BIG_PK_OK_OFF (1<<7) /* Set Rx Error bit for big frames */ +#define SK_SELF_RX_ON (1<<8) /* Enable Rx of own packets */ +#define SK_SELF_RX_OFF (1<<9) /* Disable Rx of own packets */ + +/* parameter 'Para' when calling SkMacSetRxTxEn() */ +#define SK_MAC_LOOPB_ON (1<<0) /* Enable MAC Loopback Mode */ +#define SK_MAC_LOOPB_OFF (1<<1) /* Disable MAC Loopback Mode */ +#define SK_PHY_LOOPB_ON (1<<2) /* Enable PHY Loopback Mode */ +#define SK_PHY_LOOPB_OFF (1<<3) /* Disable PHY Loopback Mode */ +#define SK_PHY_FULLD_ON (1<<4) /* Enable GMII Full Duplex */ +#define SK_PHY_FULLD_OFF (1<<5) /* Disable GMII Full Duplex */ + +/* States of PState */ +#define SK_PRT_RESET 0 /* the port is reset */ +#define SK_PRT_STOP 1 /* the port is stopped (similar to SW reset) */ +#define SK_PRT_INIT 2 /* the port is initialized */ +#define SK_PRT_RUN 3 /* the port has an active link */ + +/* Default receive frame limit for Workaround of XMAC Errata */ +#define SK_DEF_RX_WA_LIM SK_CONSTU64(100) + +/* Link Partner Status */ +#define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */ +#define SK_LIPA_MANUAL 1 /* Link partner is in detected manual state */ +#define SK_LIPA_AUTO 2 /* Link partner is in auto-negotiation state */ + +/* Maximum Restarts before restart is ignored (3Com WA) */ +#define SK_MAX_LRESTART 3 /* Max. 3 times the link is restarted */ + +/* Max. Auto-neg. timeouts before link detection in sense mode is reset */ +#define SK_MAX_ANEG_TO 10 /* Max. 10 times the sense mode is reset */ + +/* structures *****************************************************************/ + +/* + * MAC specific functions + */ +typedef struct s_GeMacFunc { + int (*pFnMacUpdateStats)(SK_AC *pAC, SK_IOC IoC, unsigned int Port); + int (*pFnMacStatistic)(SK_AC *pAC, SK_IOC IoC, unsigned int Port, + SK_U16 StatAddr, SK_U32 *pVal); + int (*pFnMacResetCounter)(SK_AC *pAC, SK_IOC IoC, unsigned int Port); + int (*pFnMacOverflow)(SK_AC *pAC, SK_IOC IoC, unsigned int Port, + SK_U16 IStatus, SK_U64 *pVal); +} SK_GEMACFUNC; + +/* + * Port Structure + */ +typedef struct s_GePort { +#ifndef SK_DIAG + SK_TIMER PWaTimer; /* Workaround Timer */ + SK_TIMER HalfDupChkTimer; +#endif /* SK_DIAG */ + SK_U32 PPrevShorts; /* Previous short Counter checking */ + SK_U32 PPrevFcs; /* Previous FCS Error Counter checking */ + SK_U64 PPrevRx; /* Previous RxOk Counter checking */ + SK_U64 PRxLim; /* Previous RxOk Counter checking */ + SK_U64 LastOctets; /* For half duplex hang check */ + int PLinkResCt; /* Link Restart Counter */ + int PAutoNegTimeOut;/* Auto-negotiation timeout current value */ + int PAutoNegTOCt; /* Auto-negotiation Timeout Counter */ + int PRxQSize; /* Port Rx Queue Size in kB */ + int PXSQSize; /* Port Synchronous Transmit Queue Size in kB */ + int PXAQSize; /* Port Asynchronous Transmit Queue Size in kB */ + SK_U32 PRxQRamStart; /* Receive Queue RAM Buffer Start Address */ + SK_U32 PRxQRamEnd; /* Receive Queue RAM Buffer End Address */ + SK_U32 PXsQRamStart; /* Sync Tx Queue RAM Buffer Start Address */ + SK_U32 PXsQRamEnd; /* Sync Tx Queue RAM Buffer End Address */ + SK_U32 PXaQRamStart; /* Async Tx Queue RAM Buffer Start Address */ + SK_U32 PXaQRamEnd; /* Async Tx Queue RAM Buffer End Address */ + SK_U32 PRxOverCnt; /* Receive Overflow Counter */ + int PRxQOff; /* Rx Queue Address Offset */ + int PXsQOff; /* Synchronous Tx Queue Address Offset */ + int PXaQOff; /* Asynchronous Tx Queue Address Offset */ + int PhyType; /* PHY used on this port */ + SK_U16 PhyId1; /* PHY Id1 on this port */ + SK_U16 PhyAddr; /* MDIO/MDC PHY address */ + SK_U16 PIsave; /* Saved Interrupt status word */ + SK_U16 PSsave; /* Saved PHY status word */ + SK_BOOL PHWLinkUp; /* The hardware Link is up (wiring) */ + SK_BOOL PState; /* Is port initialized ? */ + SK_BOOL PLinkBroken; /* Is Link broken ? */ + SK_BOOL PCheckPar; /* Do we check for parity errors ? */ + SK_BOOL HalfDupTimerActive; + SK_U8 PLinkCap; /* Link Capabilities */ + SK_U8 PLinkModeConf; /* Link Mode configured */ + SK_U8 PLinkMode; /* Link Mode currently used */ + SK_U8 PLinkModeStatus;/* Link Mode Status */ + SK_U8 PLinkSpeedCap; /* Link Speed Capabilities(10/100/1000 Mbps) */ + SK_U8 PLinkSpeed; /* configured Link Speed (10/100/1000 Mbps) */ + SK_U8 PLinkSpeedUsed; /* current Link Speed (10/100/1000 Mbps) */ + SK_U8 PFlowCtrlCap; /* Flow Control Capabilities */ + SK_U8 PFlowCtrlMode; /* Flow Control Mode */ + SK_U8 PFlowCtrlStatus;/* Flow Control Status */ + SK_U8 PMSCap; /* Master/Slave Capabilities */ + SK_U8 PMSMode; /* Master/Slave Mode */ + SK_U8 PMSStatus; /* Master/Slave Status */ + SK_U8 PAutoNegFail; /* Auto-negotiation fail flag */ + SK_U8 PLipaAutoNeg; /* Auto-negotiation possible with Link Partner */ + SK_U8 PCableLen; /* Cable Length */ + SK_U8 PMdiPairLen[4]; /* MDI[0..3] Pair Length */ + SK_U8 PMdiPairSts[4]; /* MDI[0..3] Pair Diagnostic Status */ +} SK_GEPORT; + +/* + * Gigabit Ethernet Initialization Struct + * (has to be included in the adapter context) + */ +typedef struct s_GeInit { + SK_U8 GIPciHwRev; /* PCI HW Revision Number */ + SK_U8 GIChipId; /* Chip Identification Number */ + SK_U8 GIChipRev; /* Chip Revision Number */ + SK_BOOL GIGenesis; /* Genesis adapter ? */ + SK_BOOL GICopperType; /* Copper Type adapter ? */ + SK_BOOL GIPciSlot64; /* 64-bit PCI Slot */ + SK_BOOL GIPciClock66; /* 66 MHz PCI Clock */ + SK_BOOL GIVauxAvail; /* VAUX available (YUKON) */ + SK_BOOL GIYukon32Bit; /* 32-Bit YUKON adapter */ + SK_BOOL GIYukonLite; /* YUKON-Lite chip */ + int GIMacsFound; /* Number of MACs found on this adapter */ + int GIMacType; /* MAC Type used on this adapter */ + int GIHstClkFact; /* Host Clock Factor (62.5 / HstClk * 100) */ + int GIPortUsage; /* Driver Port Usage */ + int GILevel; /* Initialization Level completed */ + int GIRamSize; /* The RAM size of the adapter in kB */ + int GIWolOffs; /* WOL Register Offset (HW-Bug in Rev. A) */ + SK_U32 GIRamOffs; /* RAM Address Offset for addr calculation */ + SK_U32 GIPollTimerVal; /* Descr. Poll Timer Init Val (HstClk ticks) */ + SK_GEPORT GP[SK_MAX_MACS];/* Port Dependent Information */ + SK_GEMACFUNC GIFunc; /* MAC depedent functions */ +} SK_GEINIT; + +/* + * Error numbers and messages for skxmac2.c and skgeinit.c + */ +#define SKERR_HWI_E001 (SK_ERRBASE_HWINIT) +#define SKERR_HWI_E001MSG "SkXmClrExactAddr() has got illegal parameters" +#define SKERR_HWI_E002 (SKERR_HWI_E001+1) +#define SKERR_HWI_E002MSG "SkGeInit(): Level 1 call missing" +#define SKERR_HWI_E003 (SKERR_HWI_E002+1) +#define SKERR_HWI_E003MSG "SkGeInit() called with illegal init Level" +#define SKERR_HWI_E004 (SKERR_HWI_E003+1) +#define SKERR_HWI_E004MSG "SkGeInitPort(): Queue Size illegal configured" +#define SKERR_HWI_E005 (SKERR_HWI_E004+1) +#define SKERR_HWI_E005MSG "SkGeInitPort(): cannot init running ports" +#define SKERR_HWI_E006 (SKERR_HWI_E005+1) +#define SKERR_HWI_E006MSG "SkGeMacInit(): PState does not match HW state" +#define SKERR_HWI_E007 (SKERR_HWI_E006+1) +#define SKERR_HWI_E007MSG "SkXmInitDupMd() called with invalid Dup Mode" +#define SKERR_HWI_E008 (SKERR_HWI_E007+1) +#define SKERR_HWI_E008MSG "SkXmSetRxCmd() called with invalid Mode" +#define SKERR_HWI_E009 (SKERR_HWI_E008+1) +#define SKERR_HWI_E009MSG "SkGeCfgSync() called although PXSQSize zero" +#define SKERR_HWI_E010 (SKERR_HWI_E009+1) +#define SKERR_HWI_E010MSG "SkGeCfgSync() called with invalid parameters" +#define SKERR_HWI_E011 (SKERR_HWI_E010+1) +#define SKERR_HWI_E011MSG "SkGeInitPort(): Receive Queue Size too small" +#define SKERR_HWI_E012 (SKERR_HWI_E011+1) +#define SKERR_HWI_E012MSG "SkGeInitPort(): invalid Queue Size specified" +#define SKERR_HWI_E013 (SKERR_HWI_E012+1) +#define SKERR_HWI_E013MSG "SkGeInitPort(): cfg changed for running queue" +#define SKERR_HWI_E014 (SKERR_HWI_E013+1) +#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown GIPortUsage specified" +#define SKERR_HWI_E015 (SKERR_HWI_E014+1) +#define SKERR_HWI_E015MSG "Illegal Link mode parameter" +#define SKERR_HWI_E016 (SKERR_HWI_E015+1) +#define SKERR_HWI_E016MSG "Illegal Flow control mode parameter" +#define SKERR_HWI_E017 (SKERR_HWI_E016+1) +#define SKERR_HWI_E017MSG "Illegal value specified for GIPollTimerVal" +#define SKERR_HWI_E018 (SKERR_HWI_E017+1) +#define SKERR_HWI_E018MSG "FATAL: SkGeStopPort() does not terminate (Tx)" +#define SKERR_HWI_E019 (SKERR_HWI_E018+1) +#define SKERR_HWI_E019MSG "Illegal Speed parameter" +#define SKERR_HWI_E020 (SKERR_HWI_E019+1) +#define SKERR_HWI_E020MSG "Illegal Master/Slave parameter" +#define SKERR_HWI_E021 (SKERR_HWI_E020+1) +#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter" +#define SKERR_HWI_E022 (SKERR_HWI_E021+1) +#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address" +#define SKERR_HWI_E023 (SKERR_HWI_E022+1) +#define SKERR_HWI_E023MSG "SkGeInitPort(): Transmit Queue Size too small" +#define SKERR_HWI_E024 (SKERR_HWI_E023+1) +#define SKERR_HWI_E024MSG "FATAL: SkGeStopPort() does not terminate (Rx)" +#define SKERR_HWI_E025 (SKERR_HWI_E024+1) +#define SKERR_HWI_E025MSG "" + +/* function prototypes ********************************************************/ + +#ifndef SK_KR_PROTO + +/* + * public functions in skgeinit.c + */ +extern void SkGePollRxD( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL PollRxD); + +extern void SkGePollTxD( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL PollTxD); + +extern void SkGeYellowLED( + SK_AC *pAC, + SK_IOC IoC, + int State); + +extern int SkGeCfgSync( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_U32 IntTime, + SK_U32 LimCount, + int SyncMode); + +extern void SkGeLoadLnkSyncCnt( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_U32 CntVal); + +extern void SkGeStopPort( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Dir, + int RstMode); + +extern int SkGeInit( + SK_AC *pAC, + SK_IOC IoC, + int Level); + +extern void SkGeDeInit( + SK_AC *pAC, + SK_IOC IoC); + +extern int SkGeInitPort( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkGeXmitLED( + SK_AC *pAC, + SK_IOC IoC, + int Led, + int Mode); + +extern void SkGeInitRamIface( + SK_AC *pAC, + SK_IOC IoC); + +extern int SkGeInitAssignRamToQueues( + SK_AC *pAC, + int ActivePort, + SK_BOOL DualNet); + +/* + * public functions in skxmac2.c + */ +extern void SkMacRxTxDisable( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacSoftRst( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacHardRst( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkXmInitMac( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkGmInitMac( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacInitPhy( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL DoLoop); + +extern void SkMacIrqDisable( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacFlushTxFifo( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacFlushRxFifo( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacIrq( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern int SkMacAutoNegDone( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacAutoNegLipaPhy( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_U16 IStatus); + +extern void SkMacSetRxTxEn( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Para); + +extern int SkMacRxTxEnable( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkMacPromiscMode( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); + +extern void SkMacHashing( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); + +extern void SkXmPhyRead( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 *pVal); + +extern void SkXmPhyWrite( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 Val); + +extern void SkGmPhyRead( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 *pVal); + +extern void SkGmPhyWrite( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 Val); + +extern void SkGePhyRead( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 *pVal); + +extern void SkGePhyWrite( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Addr, + SK_U16 Val); + +extern void SkXmClrExactAddr( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int StartNum, + int StopNum); + +extern void SkXmInitDupMd( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkXmInitPauseMd( + SK_AC *pAC, + SK_IOC IoC, + int Port); + +extern void SkXmAutoNegLipaXmac( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_U16 IStatus); + +extern int SkXmUpdateStats( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port); + +extern int SkGmUpdateStats( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port); + +extern int SkXmMacStatistic( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port, + SK_U16 StatAddr, + SK_U32 *pVal); + +extern int SkGmMacStatistic( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port, + SK_U16 StatAddr, + SK_U32 *pVal); + +extern int SkXmResetCounter( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port); + +extern int SkGmResetCounter( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port); + +extern int SkXmOverflowStatus( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port, + SK_U16 IStatus, + SK_U64 *pStatus); + +extern int SkGmOverflowStatus( + SK_AC *pAC, + SK_IOC IoC, + unsigned int Port, + SK_U16 MacStatus, + SK_U64 *pStatus); + +extern int SkGmCableDiagStatus( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL StartTest); + +#ifdef SK_DIAG +extern void SkMacSetRxCmd( + SK_AC *pAC, + SK_IOC IoC, + int Port, + int Mode); +extern void SkMacCrcGener( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); +extern void SkMacTimeStamp( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); +extern void SkXmSendCont( + SK_AC *pAC, + SK_IOC IoC, + int Port, + SK_BOOL Enable); +#endif /* SK_DIAG */ + +#else /* SK_KR_PROTO */ + +/* + * public functions in skgeinit.c + */ +extern void SkGePollRxD(); +extern void SkGePollTxD(); +extern void SkGeYellowLED(); +extern int SkGeCfgSync(); +extern void SkGeLoadLnkSyncCnt(); +extern void SkGeStopPort(); +extern int SkGeInit(); +extern void SkGeDeInit(); +extern int SkGeInitPort(); +extern void SkGeXmitLED(); +extern void SkGeInitRamIface(); +extern int SkGeInitAssignRamToQueues(); + +/* + * public functions in skxmac2.c + */ +extern void SkMacRxTxDisable(); +extern void SkMacSoftRst(); +extern void SkMacHardRst(); +extern void SkMacInitPhy(); +extern int SkMacRxTxEnable(); +extern void SkMacPromiscMode(); +extern void SkMacHashing(); +extern void SkMacIrqDisable(); +extern void SkMacFlushTxFifo(); +extern void SkMacFlushRxFifo(); +extern void SkMacIrq(); +extern int SkMacAutoNegDone(); +extern void SkMacAutoNegLipaPhy(); +extern void SkMacSetRxTxEn(); +extern void SkGePhyRead(); +extern void SkGePhyWrite(); +extern void SkXmInitMac(); +extern void SkXmPhyRead(); +extern void SkXmPhyWrite(); +extern void SkGmInitMac(); +extern void SkGmPhyRead(); +extern void SkGmPhyWrite(); +extern void SkXmClrExactAddr(); +extern void SkXmInitDupMd(); +extern void SkXmInitPauseMd(); +extern void SkXmAutoNegLipaXmac(); +extern int SkXmUpdateStats(); +extern int SkGmUpdateStats(); +extern int SkXmMacStatistic(); +extern int SkGmMacStatistic(); +extern int SkXmResetCounter(); +extern int SkGmResetCounter(); +extern int SkXmOverflowStatus(); +extern int SkGmOverflowStatus(); +extern int SkGmCableDiagStatus(); + +#ifdef SK_DIAG +extern void SkMacSetRxCmd(); +extern void SkMacCrcGener(); +extern void SkMacTimeStamp(); +extern void SkXmSendCont(); +#endif /* SK_DIAG */ + +#endif /* SK_KR_PROTO */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_SKGEINIT_H_ */ diff --git a/drivers/sk98lin/h/skgepnm2.h b/drivers/sk98lin/h/skgepnm2.h new file mode 100644 index 000000000..5c44f4771 --- /dev/null +++ b/drivers/sk98lin/h/skgepnm2.h @@ -0,0 +1,462 @@ +/***************************************************************************** + * + * Name: skgepnm2.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.34 $ + * Date: $Date: 2002/12/16 09:05:18 $ + * Purpose: Defines for Private Network Management Interface + * + ****************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/***************************************************************************** + * + * History: + * + * $Log: skgepnm2.h,v $ + * Revision 1.34 2002/12/16 09:05:18 tschilli + * Code for VCT handling added. + * + * Revision 1.33 2002/09/10 09:00:03 rwahl + * Adapted boolean definitions according sktypes. + * + * Revision 1.32 2002/08/09 09:47:01 rwahl + * Added write-only flag to oid access defines. + * Editorial changes. + * + * Revision 1.31 2002/07/17 19:23:18 rwahl + * - Replaced MAC counter definitions by enumeration. + * - Added definition SK_PNMI_MAC_TYPES. + * - Added chipset defnition for Yukon. + * + * Revision 1.30 2001/02/06 10:03:41 mkunz + * - Pnmi V4 dual net support added. Interface functions and macros extended + * - Vpd bug fixed + * - OID_SKGE_MTU added + * + * Revision 1.29 2001/01/22 13:41:37 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.28 2000/08/03 15:12:48 rwahl + * - Additional comment for MAC statistic data structure. + * + * Revision 1.27 2000/08/01 16:10:18 rwahl + * - Added mac statistic data structure for StatRxLongFrame counter. + * + * Revision 1.26 2000/03/31 13:51:34 rwahl + * Added SK_UPTR cast to offset calculation for PNMI struct fields; + * missing cast caused compiler warnings by Win64 compiler. + * + * Revision 1.25 1999/11/22 13:57:41 cgoos + * Changed license header to GPL. + * Allowing overwrite for SK_PNMI_STORE/_READ defines. + * + * Revision 1.24 1999/04/13 15:11:11 mhaveman + * Changed copyright. + * + * Revision 1.23 1999/01/28 15:07:12 mhaveman + * Changed default threshold for port switches per hour from 10 + * to 240 which means 4 switches per minute. This fits better + * the granularity of 32 for the port switch estimate + * counter. + * + * Revision 1.22 1999/01/05 12:52:30 mhaveman + * Removed macro SK_PNMI_MICRO_SEC. + * + * Revision 1.21 1999/01/05 12:50:34 mhaveman + * Enlarged macro definition SK_PNMI_HUNDREDS_SEC() so that no 64-bit + * arithmetic is necessary if SK_TICKS_PER_SEC is 100. + * + * Revision 1.20 1998/12/09 14:02:53 mhaveman + * Defined macro SK_PNMI_DEF_RLMT_CHG_THRES for default port switch + * threshold. + * + * Revision 1.19 1998/12/03 11:28:41 mhaveman + * Removed SK_PNMI_CHECKPTR macro. + * + * Revision 1.18 1998/12/03 11:21:00 mhaveman + * -Added pointer check macro SK_PNMI_CHECKPTR + * -Added macros SK_PNMI_VPD_ARR_SIZE and SK_PNMI_VPD_STR_SIZE for + * VPD key evaluation. + * + * Revision 1.17 1998/11/20 13:20:33 mhaveman + * Fixed bug in SK_PNMI_SET_STAT macro. ErrorStatus was not correctly set. + * + * Revision 1.16 1998/11/20 08:08:49 mhaveman + * Macro SK_PNMI_CHECKFLAGS has got a if clause. + * + * Revision 1.15 1998/11/03 13:53:40 mhaveman + * Fixed alignment problem in macor SK_PNMI_SET_STAT macro. + * + * Revision 1.14 1998/10/30 15:50:13 mhaveman + * Added macro SK_PNMI_MICRO_SEC() + * + * Revision 1.13 1998/10/30 12:32:20 mhaveman + * Added forgotten cast in SK_PNMI_READ_U32 macro. + * + * Revision 1.12 1998/10/29 15:40:26 mhaveman + * -Changed SK_PNMI_TRAP_SENSOR_LEN because SensorDescr has now + * variable string length. + * -Defined SK_PNMI_CHECKFLAGS macro + * + * Revision 1.11 1998/10/29 08:53:34 mhaveman + * Removed SK_PNMI_RLM_XXX table indexed because these counters need + * not been saved over XMAC resets. + * + * Revision 1.10 1998/10/28 08:48:20 mhaveman + * -Added macros for storage according to alignment + * -Changed type of Instance to SK_U32 because of VPD + * -Removed trap structures. Not needed because of alignment problem + * -Changed type of Action form SK_U8 to int + * + * Revision 1.9 1998/10/21 13:34:45 mhaveman + * Shit, mismatched calculation of SK_PNMI_HUNDREDS_SEC. Corrected. + * + * Revision 1.8 1998/10/21 13:24:58 mhaveman + * Changed calculation of hundreds of seconds. + * + * Revision 1.7 1998/10/20 07:31:41 mhaveman + * Made type changes to unsigned int where possible. + * + * Revision 1.6 1998/09/04 17:04:05 mhaveman + * Added Sync counters to offset storage to provided settled values on + * port switch. + * + * Revision 1.5 1998/09/04 12:45:35 mhaveman + * Removed dummies for SK_DRIVER_ macros. They should be added by driver + * writer in skdrv2nd.h. + * + * Revision 1.4 1998/09/04 11:59:50 mhaveman + * Everything compiles now. Driver Macros for counting still missing. + * + * Revision 1.3 1998/08/24 12:01:35 mhaveman + * Intermediate state. + * + * Revision 1.2 1998/08/17 07:51:40 mhaveman + * Intermediate state. + * + * Revision 1.1 1998/08/11 09:08:40 mhaveman + * Intermediate state. + * + ****************************************************************************/ + +#ifndef _SKGEPNM2_H_ +#define _SKGEPNM2_H_ + +/* + * General definitions + */ +#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */ +#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */ + +#define SK_PNMI_BUS_PCI 1 /* PCI bus*/ + +/* + * Actions + */ +#define SK_PNMI_ACT_IDLE 1 +#define SK_PNMI_ACT_RESET 2 +#define SK_PNMI_ACT_SELFTEST 3 +#define SK_PNMI_ACT_RESETCNT 4 + +/* + * VPD releated defines + */ + +#define SK_PNMI_VPD_RW 1 +#define SK_PNMI_VPD_RO 2 + +#define SK_PNMI_VPD_OK 0 +#define SK_PNMI_VPD_NOTFOUND 1 +#define SK_PNMI_VPD_CUT 2 +#define SK_PNMI_VPD_TIMEOUT 3 +#define SK_PNMI_VPD_FULL 4 +#define SK_PNMI_VPD_NOWRITE 5 +#define SK_PNMI_VPD_FATAL 6 + +#define SK_PNMI_VPD_IGNORE 0 +#define SK_PNMI_VPD_CREATE 1 +#define SK_PNMI_VPD_DELETE 2 + + +/* + * RLMT related defines + */ +#define SK_PNMI_DEF_RLMT_CHG_THRES 240 /* 4 changes per minute */ + + +/* + * VCT internal status values + */ +#define SK_PNMI_VCT_PENDING 32 +#define SK_PNMI_VCT_TEST_DONE 64 +#define SK_PNMI_VCT_LINK 128 + +/* + * Internal table definitions + */ +#define SK_PNMI_GET 0 +#define SK_PNMI_PRESET 1 +#define SK_PNMI_SET 2 + +#define SK_PNMI_RO 0 +#define SK_PNMI_RW 1 +#define SK_PNMI_WO 2 + +typedef struct s_OidTabEntry { + SK_U32 Id; + SK_U32 InstanceNo; + unsigned int StructSize; + unsigned int Offset; + int Access; + int (* Func)(SK_AC *pAc, SK_IOC pIo, int action, + SK_U32 Id, char* pBuf, unsigned int* pLen, + SK_U32 Instance, unsigned int TableIndex, + SK_U32 NetNumber); + SK_U16 Param; +} SK_PNMI_TAB_ENTRY; + + +/* + * Trap lengths + */ +#define SK_PNMI_TRAP_SIMPLE_LEN 17 +#define SK_PNMI_TRAP_SENSOR_LEN_BASE 46 +#define SK_PNMI_TRAP_RLMT_CHANGE_LEN 23 +#define SK_PNMI_TRAP_RLMT_PORT_LEN 23 + +/* + * Number of MAC types supported + */ +#define SK_PNMI_MAC_TYPES (SK_MAC_GMAC + 1) + +/* + * MAC statistic data list (overall set for MAC types used) + */ +enum SK_MACSTATS { + SK_PNMI_HTX = 0, + SK_PNMI_HTX_OCTET, + SK_PNMI_HTX_OCTETHIGH = SK_PNMI_HTX_OCTET, + SK_PNMI_HTX_OCTETLOW, + SK_PNMI_HTX_BROADCAST, + SK_PNMI_HTX_MULTICAST, + SK_PNMI_HTX_UNICAST, + SK_PNMI_HTX_BURST, + SK_PNMI_HTX_PMACC, + SK_PNMI_HTX_MACC, + SK_PNMI_HTX_COL, + SK_PNMI_HTX_SINGLE_COL, + SK_PNMI_HTX_MULTI_COL, + SK_PNMI_HTX_EXCESS_COL, + SK_PNMI_HTX_LATE_COL, + SK_PNMI_HTX_DEFFERAL, + SK_PNMI_HTX_EXCESS_DEF, + SK_PNMI_HTX_UNDERRUN, + SK_PNMI_HTX_CARRIER, + SK_PNMI_HTX_UTILUNDER, + SK_PNMI_HTX_UTILOVER, + SK_PNMI_HTX_64, + SK_PNMI_HTX_127, + SK_PNMI_HTX_255, + SK_PNMI_HTX_511, + SK_PNMI_HTX_1023, + SK_PNMI_HTX_MAX, + SK_PNMI_HTX_LONGFRAMES, + SK_PNMI_HTX_SYNC, + SK_PNMI_HTX_SYNC_OCTET, + SK_PNMI_HTX_RESERVED, + + SK_PNMI_HRX, + SK_PNMI_HRX_OCTET, + SK_PNMI_HRX_OCTETHIGH = SK_PNMI_HRX_OCTET, + SK_PNMI_HRX_OCTETLOW, + SK_PNMI_HRX_BADOCTET, + SK_PNMI_HRX_BADOCTETHIGH = SK_PNMI_HRX_BADOCTET, + SK_PNMI_HRX_BADOCTETLOW, + SK_PNMI_HRX_BROADCAST, + SK_PNMI_HRX_MULTICAST, + SK_PNMI_HRX_UNICAST, + SK_PNMI_HRX_PMACC, + SK_PNMI_HRX_MACC, + SK_PNMI_HRX_PMACC_ERR, + SK_PNMI_HRX_MACC_UNKWN, + SK_PNMI_HRX_BURST, + SK_PNMI_HRX_MISSED, + SK_PNMI_HRX_FRAMING, + SK_PNMI_HRX_UNDERSIZE, + SK_PNMI_HRX_OVERFLOW, + SK_PNMI_HRX_JABBER, + SK_PNMI_HRX_CARRIER, + SK_PNMI_HRX_IRLENGTH, + SK_PNMI_HRX_SYMBOL, + SK_PNMI_HRX_SHORTS, + SK_PNMI_HRX_RUNT, + SK_PNMI_HRX_TOO_LONG, + SK_PNMI_HRX_FCS, + SK_PNMI_HRX_CEXT, + SK_PNMI_HRX_UTILUNDER, + SK_PNMI_HRX_UTILOVER, + SK_PNMI_HRX_64, + SK_PNMI_HRX_127, + SK_PNMI_HRX_255, + SK_PNMI_HRX_511, + SK_PNMI_HRX_1023, + SK_PNMI_HRX_MAX, + SK_PNMI_HRX_LONGFRAMES, + + SK_PNMI_HRX_RESERVED, + + SK_PNMI_MAX_IDX /* NOTE: Ensure SK_PNMI_CNT_NO is set to this value */ +}; + +/* + * MAC specific data + */ +typedef struct s_PnmiStatAddr { + SK_U16 Reg; /* MAC register containing the value */ + SK_BOOL GetOffset; /* TRUE: Offset managed by PNMI (call GetStatVal())*/ +} SK_PNMI_STATADDR; + + +/* + * SK_PNMI_STRUCT_DATA copy offset evaluation macros + */ +#define SK_PNMI_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e)) +#define SK_PNMI_MAI_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e)) +#define SK_PNMI_VPD_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_VPD *)0)->e)) +#define SK_PNMI_SEN_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_SENSOR *)0)->e)) +#define SK_PNMI_CHK_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_CHECKSUM *)0)->e)) +#define SK_PNMI_STA_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STAT *)0)->e)) +#define SK_PNMI_CNF_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_CONF *)0)->e)) +#define SK_PNMI_RLM_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT *)0)->e)) +#define SK_PNMI_MON_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT_MONITOR *)0)->e)) +#define SK_PNMI_TRP_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_TRAP *)0)->e)) + +#define SK_PNMI_SET_STAT(b,s,o) {SK_U32 Val32; char *pVal; \ + Val32 = (s); \ + pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \ + &(((SK_PNMI_STRUCT_DATA *)0)-> \ + ReturnStatus.ErrorStatus)); \ + SK_PNMI_STORE_U32(pVal, Val32); \ + Val32 = (o); \ + pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \ + &(((SK_PNMI_STRUCT_DATA *)0)-> \ + ReturnStatus.ErrorOffset)); \ + SK_PNMI_STORE_U32(pVal, Val32);} + +/* + * Time macros + */ +#if SK_TICKS_PER_SEC == 100 +#define SK_PNMI_HUNDREDS_SEC(t) (t) +#else +#define SK_PNMI_HUNDREDS_SEC(t) (((t) * 100) / (SK_TICKS_PER_SEC)) +#endif + +/* + * Macros to work around alignment problems + */ +#ifndef SK_PNMI_STORE_U16 +#define SK_PNMI_STORE_U16(p,v) {*(char *)(p) = *((char *)&(v)); \ + *((char *)(p) + 1) = \ + *(((char *)&(v)) + 1);} +#endif + +#ifndef SK_PNMI_STORE_U32 +#define SK_PNMI_STORE_U32(p,v) {*(char *)(p) = *((char *)&(v)); \ + *((char *)(p) + 1) = \ + *(((char *)&(v)) + 1); \ + *((char *)(p) + 2) = \ + *(((char *)&(v)) + 2); \ + *((char *)(p) + 3) = \ + *(((char *)&(v)) + 3);} +#endif + +#ifndef SK_PNMI_STORE_U64 +#define SK_PNMI_STORE_U64(p,v) {*(char *)(p) = *((char *)&(v)); \ + *((char *)(p) + 1) = \ + *(((char *)&(v)) + 1); \ + *((char *)(p) + 2) = \ + *(((char *)&(v)) + 2); \ + *((char *)(p) + 3) = \ + *(((char *)&(v)) + 3); \ + *((char *)(p) + 4) = \ + *(((char *)&(v)) + 4); \ + *((char *)(p) + 5) = \ + *(((char *)&(v)) + 5); \ + *((char *)(p) + 6) = \ + *(((char *)&(v)) + 6); \ + *((char *)(p) + 7) = \ + *(((char *)&(v)) + 7);} +#endif + +#ifndef SK_PNMI_READ_U16 +#define SK_PNMI_READ_U16(p,v) {*((char *)&(v)) = *(char *)(p); \ + *(((char *)&(v)) + 1) = \ + *((char *)(p) + 1);} +#endif + +#ifndef SK_PNMI_READ_U32 +#define SK_PNMI_READ_U32(p,v) {*((char *)&(v)) = *(char *)(p); \ + *(((char *)&(v)) + 1) = \ + *((char *)(p) + 1); \ + *(((char *)&(v)) + 2) = \ + *((char *)(p) + 2); \ + *(((char *)&(v)) + 3) = \ + *((char *)(p) + 3);} +#endif + +#ifndef SK_PNMI_READ_U64 +#define SK_PNMI_READ_U64(p,v) {*((char *)&(v)) = *(char *)(p); \ + *(((char *)&(v)) + 1) = \ + *((char *)(p) + 1); \ + *(((char *)&(v)) + 2) = \ + *((char *)(p) + 2); \ + *(((char *)&(v)) + 3) = \ + *((char *)(p) + 3); \ + *(((char *)&(v)) + 4) = \ + *((char *)(p) + 4); \ + *(((char *)&(v)) + 5) = \ + *((char *)(p) + 5); \ + *(((char *)&(v)) + 6) = \ + *((char *)(p) + 6); \ + *(((char *)&(v)) + 7) = \ + *((char *)(p) + 7);} +#endif + +/* + * Macros for Debug + */ +#ifdef DEBUG + +#define SK_PNMI_CHECKFLAGS(vSt) {if (pAC->Pnmi.MacUpdatedFlag > 0 || \ + pAC->Pnmi.RlmtUpdatedFlag > 0 || \ + pAC->Pnmi.SirqUpdatedFlag > 0) { \ + SK_DBG_MSG(pAC, \ + SK_DBGMOD_PNMI, \ + SK_DBGCAT_CTRL, \ + ("PNMI: ERR: %s MacUFlag=%d, RlmtUFlag=%d, SirqUFlag=%d\n", \ + vSt, \ + pAC->Pnmi.MacUpdatedFlag, \ + pAC->Pnmi.RlmtUpdatedFlag, \ + pAC->Pnmi.SirqUpdatedFlag))}} + +#else /* !DEBUG */ + +#define SK_PNMI_CHECKFLAGS(vSt) /* Nothing */ + +#endif /* !DEBUG */ + +#endif /* _SKGEPNM2_H_ */ diff --git a/drivers/sk98lin/h/skgepnmi.h b/drivers/sk98lin/h/skgepnmi.h new file mode 100644 index 000000000..7532313ba --- /dev/null +++ b/drivers/sk98lin/h/skgepnmi.h @@ -0,0 +1,1114 @@ +/***************************************************************************** + * + * Name: skgepnmi.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.59 $ + * Date: $Date: 2002/12/16 14:03:50 $ + * Purpose: Defines for Private Network Management Interface + * + ****************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/***************************************************************************** + * + * History: + * + * $Log: skgepnmi.h,v $ + * Revision 1.59 2002/12/16 14:03:50 tschilli + * New defines for VCT added. + * + * Revision 1.58 2002/12/16 09:04:59 tschilli + * Code for VCT handling added. + * + * Revision 1.57 2002/09/26 12:41:05 tschilli + * SK_PNMI_PORT BufPort entry in struct SK_PNMI added. + * + * Revision 1.56 2002/08/16 11:10:41 rwahl + * - Replaced c++ comment. + * + * Revision 1.55 2002/08/09 15:40:21 rwahl + * Editorial change (renamed ConfSpeedCap). + * + * Revision 1.54 2002/08/09 11:06:07 rwahl + * Added OID_SKGE_SPEED_CAP. + * + * Revision 1.53 2002/08/09 09:45:28 rwahl + * Added support for NDIS OID_PNP_xxx. + * Editorial changes. + * + * Revision 1.52 2002/08/06 17:54:07 rwahl + * - Added speed cap to PNMI config struct. + * + * Revision 1.51 2002/07/17 19:19:26 rwahl + * - Added OID_SKGE_SPEED_MODE and OID_SKGE_SPEED_STATUS. + * - Added SK_PNMI_CNT_RX_PMACC_ERR() & SK_PNMI_CNT_RX_LONGFRAMES(). + * - Added speed mode & status to PNMI config struct. + * - Editorial changes. + * + * Revision 1.50 2002/05/22 08:59:37 rwahl + * Added string definitions for error msgs. + * + * Revision 1.49 2001/11/20 09:23:50 rwahl + * - pnmi struct: reordered and aligned to 32bit. + * + * Revision 1.48 2001/02/23 14:34:24 mkunz + * Changed macro PHYS2INST. Added pAC to Interface + * + * Revision 1.47 2001/02/07 08:28:23 mkunz + * - Added Oids: OID_SKGE_DIAG_ACTION + * OID_SKGE_DIAG_RESULT + * OID_SKGE_MULTICAST_LIST + * OID_SKGE_CURRENT_PACKET_FILTER + * OID_SKGE_INTERMEDIATE_SUPPORT + * - Changed value of OID_SKGE_MTU + * + * Revision 1.46 2001/02/06 10:01:41 mkunz + * - Pnmi V4 dual net support added. Interface functions and macros extended + * - Vpd bug fixed + * - OID_SKGE_MTU added + * + * Revision 1.45 2001/01/22 13:41:37 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.44 2000/09/07 07:35:27 rwahl + * - removed NDIS counter specific data type. + * - fixed spelling for OID_SKGE_RLMT_PORT_PREFERRED. + * + * Revision 1.43 2000/08/04 11:41:08 rwahl + * - Fixed compiler warning (port is always >= 0) for macros + * SK_PNMI_CNT_RX_LONGFRAMES & SK_PNMI_CNT_SYNC_OCTETS + * + * Revision 1.42 2000/08/03 15:14:07 rwahl + * - Corrected error in driver macros addressing a physical port. + * + * Revision 1.41 2000/08/01 16:22:29 rwahl + * - Changed MDB version to 3.1. + * - Added definitions for StatRxLongFrames counter. + * - Added macro to be used by driver to count long frames received. + * - Added directive to control width (default = 32bit) of NDIS statistic + * counters (SK_NDIS_64BIT_CTR). + * + * Revision 1.40 2000/03/31 13:51:34 rwahl + * Added SK_UPTR cast to offset calculation for PNMI struct fields; + * missing cast caused compiler warnings by Win64 compiler. + * + * Revision 1.39 1999/12/06 10:09:47 rwahl + * Added new error log message. + * + * Revision 1.38 1999/11/22 13:57:55 cgoos + * Changed license header to GPL. + * + * Revision 1.37 1999/09/14 14:25:32 rwahl + * Set MDB version for 1000Base-T (sensors, Master/Slave) changes. + * + * Revision 1.36 1999/05/20 09:24:56 cgoos + * Changes for 1000Base-T (sensors, Master/Slave). + * + * Revision 1.35 1999/04/13 15:10:51 mhaveman + * Replaced RLMT macros SK_RLMT_CHECK_xxx again by those of PNMI to + * grant unified interface. But PNMI macros will store the same + * value as RLMT macros. + * + * Revision 1.34 1999/04/13 15:03:49 mhaveman + * -Changed copyright + * -Removed SK_PNMI_RLMT_MODE_CHK_xxx macros. Those of RLMT should be + * used. + * + * Revision 1.33 1999/03/23 10:41:02 mhaveman + * Changed comments. + * + * Revision 1.32 1999/01/25 15:01:33 mhaveman + * Added support for multiple simultaniously active ports. + * + * Revision 1.31 1999/01/19 10:06:26 mhaveman + * Added new error log message. + * + * Revision 1.30 1999/01/05 10:34:49 mhaveman + * Fixed little error in RlmtChangeEstimate calculation. + * + * Revision 1.29 1999/01/05 09:59:41 mhaveman + * Redesigned port switch average calculation to avoid 64bit + * arithmetic. + * + * Revision 1.28 1998/12/08 10:05:48 mhaveman + * Defined macro SK_PNMI_MIN_STRUCT_SIZE. + * + * Revision 1.27 1998/12/03 14:39:35 mhaveman + * Fixed problem that LSTAT was enumerated wrong. + * + * Revision 1.26 1998/12/03 11:19:51 mhaveman + * Changed contents of errlog message SK_PNMI_ERR016MSG + * + * Revision 1.25 1998/12/01 10:40:04 mhaveman + * Changed size of SensorNumber, ChecksumNumber and RlmtPortNumber in + * SK_PNMI_STRUCT_DATA to be conform with OID definition. + * + * Revision 1.24 1998/11/20 08:09:27 mhaveman + * Added macros to convert between logical, physical port indexes and + * instances. + * + * Revision 1.23 1998/11/10 13:41:13 mhaveman + * Needed to change interface, because NT driver needs a return value + * of needed buffer space on TOO_SHORT errors. Therefore all + * SkPnmiGet/Preset/Set functions now have a pointer to the length + * parameter, where the needed space on error is returned. + * + * Revision 1.22 1998/11/03 12:05:51 mhaveman + * Added pAC parameter to counter macors. + * + * Revision 1.21 1998/11/02 10:47:36 mhaveman + * Added syslog messages for internal errors. + * + * Revision 1.20 1998/10/30 15:49:36 mhaveman + * -Removed unused SK_PNMI_UTILIZATION_BASE and EstOldCnt. + * -Redefined SK_PNMI_CHG_EST_BASE to hundreds of seconds. + * + * Revision 1.19 1998/10/29 15:38:44 mhaveman + * Changed string lengths of PNMI_STRUCT_DATA structure because + * string OIDs are now encoded with leading length ocetet. + * + * Revision 1.18 1998/10/29 08:52:27 mhaveman + * -Added byte to strings in PNMI_STRUCT_DATA structure. + * -Shortened SK_PNMI_RLMT structure to SK_MAX_MACS elements. + * + * Revision 1.17 1998/10/28 08:49:50 mhaveman + * -Changed type of Instance back to SK_U32 because of VPD + * -Changed type from SK_U8 to char of PciBusSpeed, PciBusWidth, PMD, + * and Connector. + * + * Revision 1.16 1998/10/22 10:42:31 mhaveman + * -Removed (SK_U32) casts for OIDs + * -excluded NDIS OIDs when they are already defined with ifndef _NDIS_ + * + * Revision 1.15 1998/10/20 13:56:28 mhaveman + * Headerfile includes now directly other header files to comile correctly. + * + * Revision 1.14 1998/10/20 07:31:09 mhaveman + * Made type changes to unsigned int where possible. + * + * Revision 1.13 1998/10/19 10:53:13 mhaveman + * -Casted OID definitions to SK_U32 + * -Renamed RlmtMAC... to RlmtPort... + * -Changed wrong type of VpdEntriesList from SK_U32 to char * + * + * Revision 1.12 1998/10/13 07:42:27 mhaveman + * -Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA + * -Removed old cvs history entries + * -Renamed MacNumber to PortNumber + * + * Revision 1.11 1998/10/07 10:55:24 mhaveman + * -Added OID_MDB_VERSION. Therefore was a renumbering of the VPD OIDs + * necessary. + * -Added OID_GEN_ Ids to support the windows driver. + * + * Revision 1.10 1998/09/30 13:41:10 mhaveman + * Renamed some OIDs to reduce usage of 'MAC' which is replaced by 'PORT'. + * + * Revision 1.9 1998/09/04 17:06:17 mhaveman + * -Added SyncCounter as macro. + * -Renamed OID_SKGE_.._NO_DESCR_CTS to OID_SKGE_.._NO_BUF_CTS. + * -Added macros for driver description and version strings. + * + * Revision 1.8 1998/09/04 14:36:52 mhaveman + * Added OIDs and Structure to access value of macro counters which are + * counted by the driver. + * + * Revision 1.7 1998/09/04 11:59:36 mhaveman + * Everything compiles now. Driver Macros for counting still missing. + * + ****************************************************************************/ + +#ifndef _SKGEPNMI_H_ +#define _SKGEPNMI_H_ + +/* + * Include dependencies + */ +#include "h/sktypes.h" +#include "h/skerror.h" +#include "h/sktimer.h" +#include "h/ski2c.h" +#include "h/skaddr.h" +#include "h/skrlmt.h" +#include "h/skvpd.h" + +/* + * Management Database Version + */ +#define SK_PNMI_MDB_VERSION 0x00030001 /* 3.1 */ + + +/* + * Event definitions + */ +#define SK_PNMI_EVT_SIRQ_OVERFLOW 1 /* Counter overflow */ +#define SK_PNMI_EVT_SEN_WAR_LOW 2 /* Lower war thres exceeded */ +#define SK_PNMI_EVT_SEN_WAR_UPP 3 /* Upper war thres exceeded */ +#define SK_PNMI_EVT_SEN_ERR_LOW 4 /* Lower err thres exceeded */ +#define SK_PNMI_EVT_SEN_ERR_UPP 5 /* Upper err thres exceeded */ +#define SK_PNMI_EVT_CHG_EST_TIMER 6 /* Timer event for RLMT Chg */ +#define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */ +#define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */ +#define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */ + +#define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */ +#define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */ +#define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */ +#define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */ +#define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */ +#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets + 1 = single net; 2 = dual net */ +#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */ + + +/* + * Return values + */ +#define SK_PNMI_ERR_OK 0 +#define SK_PNMI_ERR_GENERAL 1 +#define SK_PNMI_ERR_TOO_SHORT 2 +#define SK_PNMI_ERR_BAD_VALUE 3 +#define SK_PNMI_ERR_READ_ONLY 4 +#define SK_PNMI_ERR_UNKNOWN_OID 5 +#define SK_PNMI_ERR_UNKNOWN_INST 6 +#define SK_PNMI_ERR_UNKNOWN_NET 7 + + +/* + * Return values of driver reset function SK_DRIVER_RESET() and + * driver event function SK_DRIVER_EVENT() + */ +#define SK_PNMI_ERR_OK 0 +#define SK_PNMI_ERR_FAIL 1 + + +/* + * Return values of driver test function SK_DRIVER_SELFTEST() + */ +#define SK_PNMI_TST_UNKNOWN (1 << 0) +#define SK_PNMI_TST_TRANCEIVER (1 << 1) +#define SK_PNMI_TST_ASIC (1 << 2) +#define SK_PNMI_TST_SENSOR (1 << 3) +#define SK_PNMI_TST_POWERMGMT (1 << 4) +#define SK_PNMI_TST_PCI (1 << 5) +#define SK_PNMI_TST_MAC (1 << 6) + + +/* + * RLMT specific definitions + */ +#define SK_PNMI_RLMT_STATUS_STANDBY 1 +#define SK_PNMI_RLMT_STATUS_ACTIVE 2 +#define SK_PNMI_RLMT_STATUS_ERROR 3 + +#define SK_PNMI_RLMT_LSTAT_PHY_DOWN 1 +#define SK_PNMI_RLMT_LSTAT_AUTONEG 2 +#define SK_PNMI_RLMT_LSTAT_LOG_DOWN 3 +#define SK_PNMI_RLMT_LSTAT_LOG_UP 4 +#define SK_PNMI_RLMT_LSTAT_INDETERMINATED 5 + +#define SK_PNMI_RLMT_MODE_CHK_LINK (SK_RLMT_CHECK_LINK) +#define SK_PNMI_RLMT_MODE_CHK_RX (SK_RLMT_CHECK_LOC_LINK) +#define SK_PNMI_RLMT_MODE_CHK_SPT (SK_RLMT_CHECK_SEG) +/* #define SK_PNMI_RLMT_MODE_CHK_EX */ + +/* + * OID definition + */ +#ifndef _NDIS_ /* Check, whether NDIS already included OIDs */ + +#define OID_GEN_XMIT_OK 0x00020101 +#define OID_GEN_RCV_OK 0x00020102 +#define OID_GEN_XMIT_ERROR 0x00020103 +#define OID_GEN_RCV_ERROR 0x00020104 +#define OID_GEN_RCV_NO_BUFFER 0x00020105 + +/* #define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 */ +#define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202 +/* #define OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 */ +#define OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204 +/* #define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 */ +#define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206 +/* #define OID_GEN_DIRECTED_BYTES_RCV 0x00020207 */ +#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208 +/* #define OID_GEN_MULTICAST_BYTES_RCV 0x00020209 */ +#define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A +/* #define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B */ +#define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C +#define OID_GEN_RCV_CRC_ERROR 0x0002020D +#define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E + +#define OID_802_3_PERMANENT_ADDRESS 0x01010101 +#define OID_802_3_CURRENT_ADDRESS 0x01010102 +/* #define OID_802_3_MULTICAST_LIST 0x01010103 */ +/* #define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 */ +/* #define OID_802_3_MAC_OPTIONS 0x01010105 */ + +#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101 +#define OID_802_3_XMIT_ONE_COLLISION 0x01020102 +#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103 +#define OID_802_3_XMIT_DEFERRED 0x01020201 +#define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202 +#define OID_802_3_RCV_OVERRUN 0x01020203 +#define OID_802_3_XMIT_UNDERRUN 0x01020204 +#define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206 +#define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207 + +/* + * PnP and PM OIDs + */ +#ifdef SK_POWER_MGMT +#define OID_PNP_CAPABILITIES 0xFD010100 +#define OID_PNP_SET_POWER 0xFD010101 +#define OID_PNP_QUERY_POWER 0xFD010102 +#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103 +#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104 +#define OID_PNP_ENABLE_WAKE_UP 0xFD010106 +#endif /* SK_POWER_MGMT */ + +#endif /* _NDIS_ */ + +#define OID_SKGE_MDB_VERSION 0xFF010100 +#define OID_SKGE_SUPPORTED_LIST 0xFF010101 +#define OID_SKGE_VPD_FREE_BYTES 0xFF010102 +#define OID_SKGE_VPD_ENTRIES_LIST 0xFF010103 +#define OID_SKGE_VPD_ENTRIES_NUMBER 0xFF010104 +#define OID_SKGE_VPD_KEY 0xFF010105 +#define OID_SKGE_VPD_VALUE 0xFF010106 +#define OID_SKGE_VPD_ACCESS 0xFF010107 +#define OID_SKGE_VPD_ACTION 0xFF010108 + +#define OID_SKGE_PORT_NUMBER 0xFF010110 +#define OID_SKGE_DEVICE_TYPE 0xFF010111 +#define OID_SKGE_DRIVER_DESCR 0xFF010112 +#define OID_SKGE_DRIVER_VERSION 0xFF010113 +#define OID_SKGE_HW_DESCR 0xFF010114 +#define OID_SKGE_HW_VERSION 0xFF010115 +#define OID_SKGE_CHIPSET 0xFF010116 +#define OID_SKGE_ACTION 0xFF010117 +#define OID_SKGE_RESULT 0xFF010118 +#define OID_SKGE_BUS_TYPE 0xFF010119 +#define OID_SKGE_BUS_SPEED 0xFF01011A +#define OID_SKGE_BUS_WIDTH 0xFF01011B +/* 0xFF01011C unused */ +#define OID_SKGE_DIAG_ACTION 0xFF01011D +#define OID_SKGE_DIAG_RESULT 0xFF01011E +#define OID_SKGE_MTU 0xFF01011F +#define OID_SKGE_PHYS_CUR_ADDR 0xFF010120 +#define OID_SKGE_PHYS_FAC_ADDR 0xFF010121 +#define OID_SKGE_PMD 0xFF010122 +#define OID_SKGE_CONNECTOR 0xFF010123 +#define OID_SKGE_LINK_CAP 0xFF010124 +#define OID_SKGE_LINK_MODE 0xFF010125 +#define OID_SKGE_LINK_MODE_STATUS 0xFF010126 +#define OID_SKGE_LINK_STATUS 0xFF010127 +#define OID_SKGE_FLOWCTRL_CAP 0xFF010128 +#define OID_SKGE_FLOWCTRL_MODE 0xFF010129 +#define OID_SKGE_FLOWCTRL_STATUS 0xFF01012A +#define OID_SKGE_PHY_OPERATION_CAP 0xFF01012B +#define OID_SKGE_PHY_OPERATION_MODE 0xFF01012C +#define OID_SKGE_PHY_OPERATION_STATUS 0xFF01012D +#define OID_SKGE_MULTICAST_LIST 0xFF01012E +#define OID_SKGE_CURRENT_PACKET_FILTER 0xFF01012F + +#define OID_SKGE_TRAP 0xFF010130 +#define OID_SKGE_TRAP_NUMBER 0xFF010131 + +#define OID_SKGE_RLMT_MODE 0xFF010140 +#define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141 +#define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142 +#define OID_SKGE_RLMT_PORT_PREFERRED 0xFF010143 +#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160 + +#define OID_SKGE_SPEED_CAP 0xFF010170 +#define OID_SKGE_SPEED_MODE 0xFF010171 +#define OID_SKGE_SPEED_STATUS 0xFF010172 + +#define OID_SKGE_SENSOR_NUMBER 0xFF020100 +#define OID_SKGE_SENSOR_INDEX 0xFF020101 +#define OID_SKGE_SENSOR_DESCR 0xFF020102 +#define OID_SKGE_SENSOR_TYPE 0xFF020103 +#define OID_SKGE_SENSOR_VALUE 0xFF020104 +#define OID_SKGE_SENSOR_WAR_THRES_LOW 0xFF020105 +#define OID_SKGE_SENSOR_WAR_THRES_UPP 0xFF020106 +#define OID_SKGE_SENSOR_ERR_THRES_LOW 0xFF020107 +#define OID_SKGE_SENSOR_ERR_THRES_UPP 0xFF020108 +#define OID_SKGE_SENSOR_STATUS 0xFF020109 +#define OID_SKGE_SENSOR_WAR_CTS 0xFF02010A +#define OID_SKGE_SENSOR_ERR_CTS 0xFF02010B +#define OID_SKGE_SENSOR_WAR_TIME 0xFF02010C +#define OID_SKGE_SENSOR_ERR_TIME 0xFF02010D + +#define OID_SKGE_CHKSM_NUMBER 0xFF020110 +#define OID_SKGE_CHKSM_RX_OK_CTS 0xFF020111 +#define OID_SKGE_CHKSM_RX_UNABLE_CTS 0xFF020112 +#define OID_SKGE_CHKSM_RX_ERR_CTS 0xFF020113 +#define OID_SKGE_CHKSM_TX_OK_CTS 0xFF020114 +#define OID_SKGE_CHKSM_TX_UNABLE_CTS 0xFF020115 + +#define OID_SKGE_STAT_TX 0xFF020120 +#define OID_SKGE_STAT_TX_OCTETS 0xFF020121 +#define OID_SKGE_STAT_TX_BROADCAST 0xFF020122 +#define OID_SKGE_STAT_TX_MULTICAST 0xFF020123 +#define OID_SKGE_STAT_TX_UNICAST 0xFF020124 +#define OID_SKGE_STAT_TX_LONGFRAMES 0xFF020125 +#define OID_SKGE_STAT_TX_BURST 0xFF020126 +#define OID_SKGE_STAT_TX_PFLOWC 0xFF020127 +#define OID_SKGE_STAT_TX_FLOWC 0xFF020128 +#define OID_SKGE_STAT_TX_SINGLE_COL 0xFF020129 +#define OID_SKGE_STAT_TX_MULTI_COL 0xFF02012A +#define OID_SKGE_STAT_TX_EXCESS_COL 0xFF02012B +#define OID_SKGE_STAT_TX_LATE_COL 0xFF02012C +#define OID_SKGE_STAT_TX_DEFFERAL 0xFF02012D +#define OID_SKGE_STAT_TX_EXCESS_DEF 0xFF02012E +#define OID_SKGE_STAT_TX_UNDERRUN 0xFF02012F +#define OID_SKGE_STAT_TX_CARRIER 0xFF020130 +/* #define OID_SKGE_STAT_TX_UTIL 0xFF020131 */ +#define OID_SKGE_STAT_TX_64 0xFF020132 +#define OID_SKGE_STAT_TX_127 0xFF020133 +#define OID_SKGE_STAT_TX_255 0xFF020134 +#define OID_SKGE_STAT_TX_511 0xFF020135 +#define OID_SKGE_STAT_TX_1023 0xFF020136 +#define OID_SKGE_STAT_TX_MAX 0xFF020137 +#define OID_SKGE_STAT_TX_SYNC 0xFF020138 +#define OID_SKGE_STAT_TX_SYNC_OCTETS 0xFF020139 +#define OID_SKGE_STAT_RX 0xFF02013A +#define OID_SKGE_STAT_RX_OCTETS 0xFF02013B +#define OID_SKGE_STAT_RX_BROADCAST 0xFF02013C +#define OID_SKGE_STAT_RX_MULTICAST 0xFF02013D +#define OID_SKGE_STAT_RX_UNICAST 0xFF02013E +#define OID_SKGE_STAT_RX_PFLOWC 0xFF02013F +#define OID_SKGE_STAT_RX_FLOWC 0xFF020140 +#define OID_SKGE_STAT_RX_PFLOWC_ERR 0xFF020141 +#define OID_SKGE_STAT_RX_FLOWC_UNKWN 0xFF020142 +#define OID_SKGE_STAT_RX_BURST 0xFF020143 +#define OID_SKGE_STAT_RX_MISSED 0xFF020144 +#define OID_SKGE_STAT_RX_FRAMING 0xFF020145 +#define OID_SKGE_STAT_RX_OVERFLOW 0xFF020146 +#define OID_SKGE_STAT_RX_JABBER 0xFF020147 +#define OID_SKGE_STAT_RX_CARRIER 0xFF020148 +#define OID_SKGE_STAT_RX_IR_LENGTH 0xFF020149 +#define OID_SKGE_STAT_RX_SYMBOL 0xFF02014A +#define OID_SKGE_STAT_RX_SHORTS 0xFF02014B +#define OID_SKGE_STAT_RX_RUNT 0xFF02014C +#define OID_SKGE_STAT_RX_CEXT 0xFF02014D +#define OID_SKGE_STAT_RX_TOO_LONG 0xFF02014E +#define OID_SKGE_STAT_RX_FCS 0xFF02014F +/* #define OID_SKGE_STAT_RX_UTIL 0xFF020150 */ +#define OID_SKGE_STAT_RX_64 0xFF020151 +#define OID_SKGE_STAT_RX_127 0xFF020152 +#define OID_SKGE_STAT_RX_255 0xFF020153 +#define OID_SKGE_STAT_RX_511 0xFF020154 +#define OID_SKGE_STAT_RX_1023 0xFF020155 +#define OID_SKGE_STAT_RX_MAX 0xFF020156 +#define OID_SKGE_STAT_RX_LONGFRAMES 0xFF020157 + +#define OID_SKGE_RLMT_CHANGE_CTS 0xFF020160 +#define OID_SKGE_RLMT_CHANGE_TIME 0xFF020161 +#define OID_SKGE_RLMT_CHANGE_ESTIM 0xFF020162 +#define OID_SKGE_RLMT_CHANGE_THRES 0xFF020163 + +#define OID_SKGE_RLMT_PORT_INDEX 0xFF020164 +#define OID_SKGE_RLMT_STATUS 0xFF020165 +#define OID_SKGE_RLMT_TX_HELLO_CTS 0xFF020166 +#define OID_SKGE_RLMT_RX_HELLO_CTS 0xFF020167 +#define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168 +#define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169 + +#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150 +#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151 +#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152 +#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153 +#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154 +#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155 + +#define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170 +#define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171 +#define OID_SKGE_TX_RETRY 0xFF020172 +#define OID_SKGE_RX_INTR_CTS 0xFF020173 +#define OID_SKGE_TX_INTR_CTS 0xFF020174 +#define OID_SKGE_RX_NO_BUF_CTS 0xFF020175 +#define OID_SKGE_TX_NO_BUF_CTS 0xFF020176 +#define OID_SKGE_TX_USED_DESCR_NO 0xFF020177 +#define OID_SKGE_RX_DELIVERED_CTS 0xFF020178 +#define OID_SKGE_RX_OCTETS_DELIV_CTS 0xFF020179 +#define OID_SKGE_RX_HW_ERROR_CTS 0xFF02017A +#define OID_SKGE_TX_HW_ERROR_CTS 0xFF02017B +#define OID_SKGE_IN_ERRORS_CTS 0xFF02017C +#define OID_SKGE_OUT_ERROR_CTS 0xFF02017D +#define OID_SKGE_ERR_RECOVERY_CTS 0xFF02017E +#define OID_SKGE_SYSUPTIME 0xFF02017F + +#define OID_SKGE_ALL_DATA 0xFF020190 + +/* Defines for VCT. */ +#define OID_SKGE_VCT_GET 0xFF020200 +#define OID_SKGE_VCT_SET 0xFF020201 +#define OID_SKGE_VCT_STATUS 0xFF020202 + + +/* VCT struct to store a backup copy of VCT data after a port reset. */ +typedef struct s_PnmiVct { + SK_U8 VctStatus; + SK_U8 PCableLen; + SK_U32 PMdiPairLen[4]; + SK_U8 PMdiPairSts[4]; +} SK_PNMI_VCT; + + +/* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */ +#define SK_PNMI_VCT_NONE 0 +#define SK_PNMI_VCT_OLD_VCT_DATA 1 +#define SK_PNMI_VCT_NEW_VCT_DATA 2 +#define SK_PNMI_VCT_OLD_DSP_DATA 4 +#define SK_PNMI_VCT_NEW_DSP_DATA 8 +#define SK_PNMI_VCT_RUNNING 16 + + +/* VCT cable test status. */ +#define SK_PNMI_VCT_NORMAL_CABLE 0 +#define SK_PNMI_VCT_SHORT_CABLE 1 +#define SK_PNMI_VCT_OPEN_CABLE 2 +#define SK_PNMI_VCT_TEST_FAIL 3 +#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4 + +#define OID_SKGE_TRAP_SEN_WAR_LOW 500 +#define OID_SKGE_TRAP_SEN_WAR_UPP 501 +#define OID_SKGE_TRAP_SEN_ERR_LOW 502 +#define OID_SKGE_TRAP_SEN_ERR_UPP 503 +#define OID_SKGE_TRAP_RLMT_CHANGE_THRES 520 +#define OID_SKGE_TRAP_RLMT_CHANGE_PORT 521 +#define OID_SKGE_TRAP_RLMT_PORT_DOWN 522 +#define OID_SKGE_TRAP_RLMT_PORT_UP 523 +#define OID_SKGE_TRAP_RLMT_SEGMENTATION 524 + + +/* + * Define error numbers and messages for syslog + */ +#define SK_PNMI_ERR001 (SK_ERRBASE_PNMI + 1) +#define SK_PNMI_ERR001MSG "SkPnmiGetStruct: Unknown OID" +#define SK_PNMI_ERR002 (SK_ERRBASE_PNMI + 2) +#define SK_PNMI_ERR002MSG "SkPnmiGetStruct: Cannot read VPD keys" +#define SK_PNMI_ERR003 (SK_ERRBASE_PNMI + 3) +#define SK_PNMI_ERR003MSG "OidStruct: Called with wrong OID" +#define SK_PNMI_ERR004 (SK_ERRBASE_PNMI + 4) +#define SK_PNMI_ERR004MSG "OidStruct: Called with wrong action" +#define SK_PNMI_ERR005 (SK_ERRBASE_PNMI + 5) +#define SK_PNMI_ERR005MSG "Perform: Cannot reset driver" +#define SK_PNMI_ERR006 (SK_ERRBASE_PNMI + 6) +#define SK_PNMI_ERR006MSG "Perform: Unknown OID action command" +#define SK_PNMI_ERR007 (SK_ERRBASE_PNMI + 7) +#define SK_PNMI_ERR007MSG "General: Driver description not initialized" +#define SK_PNMI_ERR008 (SK_ERRBASE_PNMI + 8) +#define SK_PNMI_ERR008MSG "Addr: Tried to get unknown OID" +#define SK_PNMI_ERR009 (SK_ERRBASE_PNMI + 9) +#define SK_PNMI_ERR009MSG "Addr: Unknown OID" +#define SK_PNMI_ERR010 (SK_ERRBASE_PNMI + 10) +#define SK_PNMI_ERR010MSG "CsumStat: Unknown OID" +#define SK_PNMI_ERR011 (SK_ERRBASE_PNMI + 11) +#define SK_PNMI_ERR011MSG "SensorStat: Sensor descr string too long" +#define SK_PNMI_ERR012 (SK_ERRBASE_PNMI + 12) +#define SK_PNMI_ERR012MSG "SensorStat: Unknown OID" +#define SK_PNMI_ERR013 (SK_ERRBASE_PNMI + 13) +#define SK_PNMI_ERR013MSG "" +#define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14) +#define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys" +#define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15) +#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys to small" +#define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16) +#define SK_PNMI_ERR016MSG "Vpd: Key string too long" +#define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17) +#define SK_PNMI_ERR017MSG "Vpd: Invalid VPD status pointer" +#define SK_PNMI_ERR018 (SK_ERRBASE_PNMI + 18) +#define SK_PNMI_ERR018MSG "Vpd: VPD data not valid" +#define SK_PNMI_ERR019 (SK_ERRBASE_PNMI + 19) +#define SK_PNMI_ERR019MSG "Vpd: VPD entries list string too long" +#define SK_PNMI_ERR021 (SK_ERRBASE_PNMI + 21) +#define SK_PNMI_ERR021MSG "Vpd: VPD data string too long" +#define SK_PNMI_ERR022 (SK_ERRBASE_PNMI + 22) +#define SK_PNMI_ERR022MSG "Vpd: VPD data string too long should be errored before" +#define SK_PNMI_ERR023 (SK_ERRBASE_PNMI + 23) +#define SK_PNMI_ERR023MSG "Vpd: Unknown OID in get action" +#define SK_PNMI_ERR024 (SK_ERRBASE_PNMI + 24) +#define SK_PNMI_ERR024MSG "Vpd: Unknown OID in preset/set action" +#define SK_PNMI_ERR025 (SK_ERRBASE_PNMI + 25) +#define SK_PNMI_ERR025MSG "Vpd: Cannot write VPD after modify entry" +#define SK_PNMI_ERR026 (SK_ERRBASE_PNMI + 26) +#define SK_PNMI_ERR026MSG "Vpd: Cannot update VPD" +#define SK_PNMI_ERR027 (SK_ERRBASE_PNMI + 27) +#define SK_PNMI_ERR027MSG "Vpd: Cannot delete VPD entry" +#define SK_PNMI_ERR028 (SK_ERRBASE_PNMI + 28) +#define SK_PNMI_ERR028MSG "Vpd: Cannot update VPD after delete entry" +#define SK_PNMI_ERR029 (SK_ERRBASE_PNMI + 29) +#define SK_PNMI_ERR029MSG "General: Driver description string too long" +#define SK_PNMI_ERR030 (SK_ERRBASE_PNMI + 30) +#define SK_PNMI_ERR030MSG "General: Driver version not initialized" +#define SK_PNMI_ERR031 (SK_ERRBASE_PNMI + 31) +#define SK_PNMI_ERR031MSG "General: Driver version string too long" +#define SK_PNMI_ERR032 (SK_ERRBASE_PNMI + 32) +#define SK_PNMI_ERR032MSG "General: Cannot read VPD Name for HW descr" +#define SK_PNMI_ERR033 (SK_ERRBASE_PNMI + 33) +#define SK_PNMI_ERR033MSG "General: HW description string too long" +#define SK_PNMI_ERR034 (SK_ERRBASE_PNMI + 34) +#define SK_PNMI_ERR034MSG "General: Unknown OID" +#define SK_PNMI_ERR035 (SK_ERRBASE_PNMI + 35) +#define SK_PNMI_ERR035MSG "Rlmt: Unknown OID" +#define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36) +#define SK_PNMI_ERR036MSG "" +#define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37) +#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event return not 0" +#define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38) +#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0" +#define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39) +#define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID" +#define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40) +#define SK_PNMI_ERR040MSG "PowerManagement: Unknown OID" +#define SK_PNMI_ERR041 (SK_ERRBASE_PNMI + 41) +#define SK_PNMI_ERR041MSG "MacPrivateConf: Unknown OID" +#define SK_PNMI_ERR042 (SK_ERRBASE_PNMI + 42) +#define SK_PNMI_ERR042MSG "MacPrivateConf: SK_HWEV_SET_ROLE returned not 0" +#define SK_PNMI_ERR043 (SK_ERRBASE_PNMI + 43) +#define SK_PNMI_ERR043MSG "MacPrivateConf: SK_HWEV_SET_LMODE returned not 0" +#define SK_PNMI_ERR044 (SK_ERRBASE_PNMI + 44) +#define SK_PNMI_ERR044MSG "MacPrivateConf: SK_HWEV_SET_FLOWMODE returned not 0" +#define SK_PNMI_ERR045 (SK_ERRBASE_PNMI + 45) +#define SK_PNMI_ERR045MSG "MacPrivateConf: SK_HWEV_SET_SPEED returned not 0" +#define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46) +#define SK_PNMI_ERR046MSG "Monitor: Unknown OID" +#define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47) +#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returns not 0" +#define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48) +#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returns not 0" +#define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49) +#define SK_PNMI_ERR049MSG "SkPnmiInit: Invalid size of 'CounterOffset' struct!!" +#define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50) +#define SK_PNMI_ERR050MSG "SkPnmiInit: Invalid size of 'StatAddr' table!!" +#define SK_PNMI_ERR051 (SK_ERRBASE_PNMI + 51) +#define SK_PNMI_ERR051MSG "SkPnmiEvent: Port switch suspicious" +#define SK_PNMI_ERR052 (SK_ERRBASE_PNMI + 52) +#define SK_PNMI_ERR052MSG "" + +/* + * Management counter macros called by the driver + */ +#define SK_PNMI_SET_DRIVER_DESCR(pAC,v) ((pAC)->Pnmi.pDriverDescription = \ + (char *)(v)) + +#define SK_PNMI_SET_DRIVER_VER(pAC,v) ((pAC)->Pnmi.pDriverVersion = \ + (char *)(v)) + + +#define SK_PNMI_CNT_TX_QUEUE_LEN(pAC,v,p) \ + { \ + (pAC)->Pnmi.Port[p].TxSwQueueLen = (SK_U64)(v); \ + if ((pAC)->Pnmi.Port[p].TxSwQueueLen > (pAC)->Pnmi.Port[p].TxSwQueueMax) { \ + (pAC)->Pnmi.Port[p].TxSwQueueMax = (pAC)->Pnmi.Port[p].TxSwQueueLen; \ + } \ + } +#define SK_PNMI_CNT_TX_RETRY(pAC,p) (((pAC)->Pnmi.Port[p].TxRetryCts)++) +#define SK_PNMI_CNT_RX_INTR(pAC,p) (((pAC)->Pnmi.Port[p].RxIntrCts)++) +#define SK_PNMI_CNT_TX_INTR(pAC,p) (((pAC)->Pnmi.Port[p].TxIntrCts)++) +#define SK_PNMI_CNT_NO_RX_BUF(pAC,p) (((pAC)->Pnmi.Port[p].RxNoBufCts)++) +#define SK_PNMI_CNT_NO_TX_BUF(pAC,p) (((pAC)->Pnmi.Port[p].TxNoBufCts)++) +#define SK_PNMI_CNT_USED_TX_DESCR(pAC,v,p) \ + ((pAC)->Pnmi.Port[p].TxUsedDescrNo=(SK_U64)(v)); +#define SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,v,p) \ + { \ + ((pAC)->Pnmi.Port[p].RxDeliveredCts)++; \ + (pAC)->Pnmi.Port[p].RxOctetsDeliveredCts += (SK_U64)(v); \ + } +#define SK_PNMI_CNT_ERR_RECOVERY(pAC,p) (((pAC)->Pnmi.Port[p].ErrRecoveryCts)++); + +#define SK_PNMI_CNT_SYNC_OCTETS(pAC,p,v) \ + { \ + if ((p) < SK_MAX_MACS) { \ + ((pAC)->Pnmi.Port[p].StatSyncCts)++; \ + (pAC)->Pnmi.Port[p].StatSyncOctetsCts += (SK_U64)(v); \ + } \ + } + +#define SK_PNMI_CNT_RX_LONGFRAMES(pAC,p) \ + { \ + if ((p) < SK_MAX_MACS) { \ + ((pAC)->Pnmi.Port[p].StatRxLongFrameCts++); \ + } \ + } + +#define SK_PNMI_CNT_RX_FRAMETOOLONG(pAC,p) \ + { \ + if ((p) < SK_MAX_MACS) { \ + ((pAC)->Pnmi.Port[p].StatRxFrameTooLongCts++); \ + } \ + } + +#define SK_PNMI_CNT_RX_PMACC_ERR(pAC,p) \ + { \ + if ((p) < SK_MAX_MACS) { \ + ((pAC)->Pnmi.Port[p].StatRxPMaccErr++); \ + } \ + } + +/* + * Conversion Macros + */ +#define SK_PNMI_PORT_INST2LOG(i) ((unsigned int)(i) - 1) +#define SK_PNMI_PORT_LOG2INST(l) ((unsigned int)(l) + 1) +#define SK_PNMI_PORT_PHYS2LOG(p) ((unsigned int)(p) + 1) +#define SK_PNMI_PORT_LOG2PHYS(pAC,l) ((unsigned int)(l) - 1) +#define SK_PNMI_PORT_PHYS2INST(pAC,p) \ + (pAC->Pnmi.DualNetActiveFlag ? 2 : ((unsigned int)(p) + 2)) +#define SK_PNMI_PORT_INST2PHYS(pAC,i) ((unsigned int)(i) - 2) + +/* + * Structure definition for SkPnmiGetStruct and SkPnmiSetStruct + */ +#define SK_PNMI_VPD_KEY_SIZE 5 +#define SK_PNMI_VPD_BUFSIZE (VPD_SIZE) +#define SK_PNMI_VPD_ENTRIES (VPD_SIZE / 4) +#define SK_PNMI_VPD_DATALEN 128 /* Number of data bytes */ + +#define SK_PNMI_MULTICAST_LISTLEN 64 +#define SK_PNMI_SENSOR_ENTRIES (SK_MAX_SENSORS) +#define SK_PNMI_CHECKSUM_ENTRIES 3 +#define SK_PNMI_MAC_ENTRIES (SK_MAX_MACS + 1) +#define SK_PNMI_MONITOR_ENTRIES 20 +#define SK_PNMI_TRAP_ENTRIES 10 +#define SK_PNMI_TRAPLEN 128 +#define SK_PNMI_STRINGLEN1 80 +#define SK_PNMI_STRINGLEN2 25 +#define SK_PNMI_TRAP_QUEUE_LEN 512 + +typedef struct s_PnmiVpd { + char VpdKey[SK_PNMI_VPD_KEY_SIZE]; + char VpdValue[SK_PNMI_VPD_DATALEN]; + SK_U8 VpdAccess; + SK_U8 VpdAction; +} SK_PNMI_VPD; + +typedef struct s_PnmiSensor { + SK_U8 SensorIndex; + char SensorDescr[SK_PNMI_STRINGLEN2]; + SK_U8 SensorType; + SK_U32 SensorValue; + SK_U32 SensorWarningThresholdLow; + SK_U32 SensorWarningThresholdHigh; + SK_U32 SensorErrorThresholdLow; + SK_U32 SensorErrorThresholdHigh; + SK_U8 SensorStatus; + SK_U64 SensorWarningCts; + SK_U64 SensorErrorCts; + SK_U64 SensorWarningTimestamp; + SK_U64 SensorErrorTimestamp; +} SK_PNMI_SENSOR; + +typedef struct s_PnmiChecksum { + SK_U64 ChecksumRxOkCts; + SK_U64 ChecksumRxUnableCts; + SK_U64 ChecksumRxErrCts; + SK_U64 ChecksumTxOkCts; + SK_U64 ChecksumTxUnableCts; +} SK_PNMI_CHECKSUM; + +typedef struct s_PnmiStat { + SK_U64 StatTxOkCts; + SK_U64 StatTxOctetsOkCts; + SK_U64 StatTxBroadcastOkCts; + SK_U64 StatTxMulticastOkCts; + SK_U64 StatTxUnicastOkCts; + SK_U64 StatTxLongFramesCts; + SK_U64 StatTxBurstCts; + SK_U64 StatTxPauseMacCtrlCts; + SK_U64 StatTxMacCtrlCts; + SK_U64 StatTxSingleCollisionCts; + SK_U64 StatTxMultipleCollisionCts; + SK_U64 StatTxExcessiveCollisionCts; + SK_U64 StatTxLateCollisionCts; + SK_U64 StatTxDeferralCts; + SK_U64 StatTxExcessiveDeferralCts; + SK_U64 StatTxFifoUnderrunCts; + SK_U64 StatTxCarrierCts; + SK_U64 Dummy1; /* StatTxUtilization */ + SK_U64 StatTx64Cts; + SK_U64 StatTx127Cts; + SK_U64 StatTx255Cts; + SK_U64 StatTx511Cts; + SK_U64 StatTx1023Cts; + SK_U64 StatTxMaxCts; + SK_U64 StatTxSyncCts; + SK_U64 StatTxSyncOctetsCts; + SK_U64 StatRxOkCts; + SK_U64 StatRxOctetsOkCts; + SK_U64 StatRxBroadcastOkCts; + SK_U64 StatRxMulticastOkCts; + SK_U64 StatRxUnicastOkCts; + SK_U64 StatRxLongFramesCts; + SK_U64 StatRxPauseMacCtrlCts; + SK_U64 StatRxMacCtrlCts; + SK_U64 StatRxPauseMacCtrlErrorCts; + SK_U64 StatRxMacCtrlUnknownCts; + SK_U64 StatRxBurstCts; + SK_U64 StatRxMissedCts; + SK_U64 StatRxFramingCts; + SK_U64 StatRxFifoOverflowCts; + SK_U64 StatRxJabberCts; + SK_U64 StatRxCarrierCts; + SK_U64 StatRxIRLengthCts; + SK_U64 StatRxSymbolCts; + SK_U64 StatRxShortsCts; + SK_U64 StatRxRuntCts; + SK_U64 StatRxCextCts; + SK_U64 StatRxTooLongCts; + SK_U64 StatRxFcsCts; + SK_U64 Dummy2; /* StatRxUtilization */ + SK_U64 StatRx64Cts; + SK_U64 StatRx127Cts; + SK_U64 StatRx255Cts; + SK_U64 StatRx511Cts; + SK_U64 StatRx1023Cts; + SK_U64 StatRxMaxCts; +} SK_PNMI_STAT; + +typedef struct s_PnmiConf { + char ConfMacCurrentAddr[6]; + char ConfMacFactoryAddr[6]; + SK_U8 ConfPMD; + SK_U8 ConfConnector; + SK_U8 ConfLinkCapability; + SK_U8 ConfLinkMode; + SK_U8 ConfLinkModeStatus; + SK_U8 ConfLinkStatus; + SK_U8 ConfFlowCtrlCapability; + SK_U8 ConfFlowCtrlMode; + SK_U8 ConfFlowCtrlStatus; + SK_U8 ConfPhyOperationCapability; + SK_U8 ConfPhyOperationMode; + SK_U8 ConfPhyOperationStatus; + SK_U8 ConfSpeedCapability; + SK_U8 ConfSpeedMode; + SK_U8 ConfSpeedStatus; +} SK_PNMI_CONF; + +typedef struct s_PnmiRlmt { + SK_U32 RlmtIndex; + SK_U32 RlmtStatus; + SK_U64 RlmtTxHelloCts; + SK_U64 RlmtRxHelloCts; + SK_U64 RlmtTxSpHelloReqCts; + SK_U64 RlmtRxSpHelloCts; +} SK_PNMI_RLMT; + +typedef struct s_PnmiRlmtMonitor { + SK_U32 RlmtMonitorIndex; + char RlmtMonitorAddr[6]; + SK_U64 RlmtMonitorErrorCts; + SK_U64 RlmtMonitorTimestamp; + SK_U8 RlmtMonitorAdmin; +} SK_PNMI_RLMT_MONITOR; + +typedef struct s_PnmiRequestStatus { + SK_U32 ErrorStatus; + SK_U32 ErrorOffset; +} SK_PNMI_REQUEST_STATUS; + +typedef struct s_PnmiStrucData { + SK_U32 MgmtDBVersion; + SK_PNMI_REQUEST_STATUS ReturnStatus; + SK_U32 VpdFreeBytes; + char VpdEntriesList[SK_PNMI_VPD_ENTRIES * SK_PNMI_VPD_KEY_SIZE]; + SK_U32 VpdEntriesNumber; + SK_PNMI_VPD Vpd[SK_PNMI_VPD_ENTRIES]; + SK_U32 PortNumber; + SK_U32 DeviceType; + char DriverDescr[SK_PNMI_STRINGLEN1]; + char DriverVersion[SK_PNMI_STRINGLEN2]; + char HwDescr[SK_PNMI_STRINGLEN1]; + char HwVersion[SK_PNMI_STRINGLEN2]; + SK_U16 Chipset; + SK_U32 MtuSize; + SK_U32 Action; + SK_U32 TestResult; + SK_U8 BusType; + SK_U8 BusSpeed; + SK_U8 BusWidth; + SK_U8 SensorNumber; + SK_PNMI_SENSOR Sensor[SK_PNMI_SENSOR_ENTRIES]; + SK_U8 ChecksumNumber; + SK_PNMI_CHECKSUM Checksum[SK_PNMI_CHECKSUM_ENTRIES]; + SK_PNMI_STAT Stat[SK_PNMI_MAC_ENTRIES]; + SK_PNMI_CONF Conf[SK_PNMI_MAC_ENTRIES]; + SK_U8 RlmtMode; + SK_U32 RlmtPortNumber; + SK_U8 RlmtPortActive; + SK_U8 RlmtPortPreferred; + SK_U64 RlmtChangeCts; + SK_U64 RlmtChangeTime; + SK_U64 RlmtChangeEstimate; + SK_U64 RlmtChangeThreshold; + SK_PNMI_RLMT Rlmt[SK_MAX_MACS]; + SK_U32 RlmtMonitorNumber; + SK_PNMI_RLMT_MONITOR RlmtMonitor[SK_PNMI_MONITOR_ENTRIES]; + SK_U32 TrapNumber; + SK_U8 Trap[SK_PNMI_TRAP_QUEUE_LEN]; + SK_U64 TxSwQueueLen; + SK_U64 TxSwQueueMax; + SK_U64 TxRetryCts; + SK_U64 RxIntrCts; + SK_U64 TxIntrCts; + SK_U64 RxNoBufCts; + SK_U64 TxNoBufCts; + SK_U64 TxUsedDescrNo; + SK_U64 RxDeliveredCts; + SK_U64 RxOctetsDeliveredCts; + SK_U64 RxHwErrorsCts; + SK_U64 TxHwErrorsCts; + SK_U64 InErrorsCts; + SK_U64 OutErrorsCts; + SK_U64 ErrRecoveryCts; + SK_U64 SysUpTime; +} SK_PNMI_STRUCT_DATA; + +#define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA)) +#define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)(SK_UPTR)\ + &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes)) + /* + * ReturnStatus field + * must be located + * before VpdFreeBytes + */ + +/* + * Various definitions + */ +#define SK_PNMI_MAX_PROTOS 3 + +#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum + * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK + * for check while init phase 1 + */ + +/* + * Estimate data structure + */ +typedef struct s_PnmiEstimate { + unsigned int EstValueIndex; + SK_U64 EstValue[7]; + SK_U64 Estimate; + SK_TIMER EstTimer; +} SK_PNMI_ESTIMATE; + + +/* + * VCT timer data structure + */ +typedef struct s_VctTimer { + SK_TIMER VctTimer; +} SK_PNMI_VCT_TIMER; + + +/* + * PNMI specific adapter context structure + */ +typedef struct s_PnmiPort { + SK_U64 StatSyncCts; + SK_U64 StatSyncOctetsCts; + SK_U64 StatRxLongFrameCts; + SK_U64 StatRxFrameTooLongCts; + SK_U64 StatRxPMaccErr; + SK_U64 TxSwQueueLen; + SK_U64 TxSwQueueMax; + SK_U64 TxRetryCts; + SK_U64 RxIntrCts; + SK_U64 TxIntrCts; + SK_U64 RxNoBufCts; + SK_U64 TxNoBufCts; + SK_U64 TxUsedDescrNo; + SK_U64 RxDeliveredCts; + SK_U64 RxOctetsDeliveredCts; + SK_U64 RxHwErrorsCts; + SK_U64 TxHwErrorsCts; + SK_U64 InErrorsCts; + SK_U64 OutErrorsCts; + SK_U64 ErrRecoveryCts; + SK_U64 RxShortZeroMark; + SK_U64 CounterOffset[SK_PNMI_CNT_NO]; + SK_U32 CounterHigh[SK_PNMI_CNT_NO]; + SK_BOOL ActiveFlag; + SK_U8 Align[3]; +} SK_PNMI_PORT; + + +typedef struct s_PnmiData { + SK_PNMI_PORT Port [SK_MAX_MACS]; + SK_PNMI_PORT BufPort [SK_MAX_MACS]; /* 2002-09-13 pweber */ + SK_U64 VirtualCounterOffset[SK_PNMI_CNT_NO]; + SK_U32 TestResult; + char HwVersion[10]; + SK_U16 Align01; + + char *pDriverDescription; + char *pDriverVersion; + + int MacUpdatedFlag; + int RlmtUpdatedFlag; + int SirqUpdatedFlag; + + SK_U64 RlmtChangeCts; + SK_U64 RlmtChangeTime; + SK_PNMI_ESTIMATE RlmtChangeEstimate; + SK_U64 RlmtChangeThreshold; + + SK_U64 StartUpTime; + SK_U32 DeviceType; + char PciBusSpeed; + char PciBusWidth; + char Chipset; + char PMD; + char Connector; + SK_BOOL DualNetActiveFlag; + SK_U16 Align02; + + char TrapBuf[SK_PNMI_TRAP_QUEUE_LEN]; + unsigned int TrapBufFree; + unsigned int TrapQueueBeg; + unsigned int TrapQueueEnd; + unsigned int TrapBufPad; + unsigned int TrapUnique; + SK_U8 VctStatus[SK_MAX_MACS]; + SK_PNMI_VCT VctBackup[SK_MAX_MACS]; + SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS]; +} SK_PNMI; + + +/* + * Function prototypes + */ +extern int SkPnmiInit(SK_AC *pAc, SK_IOC IoC, int level); +extern int SkPnmiGetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, void* pBuf, + unsigned int* pLen, SK_U32 Instance, SK_U32 NetIndex); +extern int SkPnmiPreSetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, + void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +extern int SkPnmiSetVar(SK_AC *pAc, SK_IOC IoC, SK_U32 Id, void* pBuf, + unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +extern int SkPnmiGetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf, + unsigned int *pLen, SK_U32 NetIndex); +extern int SkPnmiPreSetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf, + unsigned int *pLen, SK_U32 NetIndex); +extern int SkPnmiSetStruct(SK_AC *pAc, SK_IOC IoC, void* pBuf, + unsigned int *pLen, SK_U32 NetIndex); +extern int SkPnmiEvent(SK_AC *pAc, SK_IOC IoC, SK_U32 Event, + SK_EVPARA Param); + +#endif diff --git a/drivers/sk98lin/h/skgesirq.h b/drivers/sk98lin/h/skgesirq.h new file mode 100644 index 000000000..fc001b237 --- /dev/null +++ b/drivers/sk98lin/h/skgesirq.h @@ -0,0 +1,194 @@ +/****************************************************************************** + * + * Name: skgesirq.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.26 $ + * Date: $Date: 2002/10/14 09:52:36 $ + * Purpose: SK specific Gigabit Ethernet special IRQ functions + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: skgesirq.h,v $ + * Revision 1.26 2002/10/14 09:52:36 rschmidt + * Added SKERR_SIRQ_E023 and SKERR_SIRQ_E023 for GPHY (Yukon) + * Editorial changes + * + * Revision 1.25 2002/07/15 18:15:52 rwahl + * Editorial changes. + * + * Revision 1.24 2002/07/15 15:39:21 rschmidt + * Corrected define for SKERR_SIRQ_E022 + * Editorial changes + * + * Revision 1.23 2002/04/25 11:09:45 rschmidt + * Removed declarations for SkXmInitPhy(), SkXmRxTxEnable() + * Editorial changes + * + * Revision 1.22 2000/11/09 11:30:10 rassmann + * WA: Waiting after releasing reset until BCom chip is accessible. + * + * Revision 1.21 2000/10/18 12:22:40 cgoos + * Added workaround for half duplex hangup. + * + * Revision 1.20 1999/12/06 10:00:44 cgoos + * Added SET event for role. + * + * Revision 1.19 1999/11/22 13:58:26 cgoos + * Changed license header to GPL. + * + * Revision 1.18 1999/05/19 07:32:59 cgoos + * Changes for 1000Base-T. + * + * Revision 1.17 1999/03/12 13:29:31 malthoff + * Move Autonegotiation Error Codes to skgeinit.h. + * + * Revision 1.16 1999/03/08 10:11:28 gklug + * add: AutoNegDone return codes + * + * Revision 1.15 1998/11/18 13:20:53 gklug + * add: different timeouts for active and non-active links + * + * Revision 1.14 1998/11/04 07:18:14 cgoos + * Added prototype for SkXmRxTxEnable. + * + * Revision 1.13 1998/10/21 05:52:23 gklug + * add: parameter DoLoop to InitPhy function + * + * Revision 1.12 1998/10/19 06:45:03 cgoos + * Added prototype for SkXmInitPhy. + * + * Revision 1.11 1998/10/15 14:34:10 gklug + * add: WA_TIME is 500 msec + * + * Revision 1.10 1998/10/14 14:49:41 malthoff + * Remove err log defines E021 and E022. They are + * defined in skgeinit.h now. + * + * Revision 1.9 1998/10/14 14:00:39 gklug + * add: error logs for init phys + * + * Revision 1.8 1998/10/14 05:44:05 gklug + * add: E020 + * + * Revision 1.7 1998/10/02 06:24:58 gklug + * add: error messages + * + * Revision 1.6 1998/10/01 07:54:45 gklug + * add: PNMI debug module + * + * Revision 1.5 1998/09/28 13:36:31 malthoff + * Move the bit definitions for Autonegotiation + * and Flow Control to skgeinit.h. + * + * Revision 1.4 1998/09/15 12:29:34 gklug + * add: error logs + * + * Revision 1.3 1998/09/03 13:54:02 gklug + * add: function prototypes + * + * Revision 1.2 1998/09/03 10:24:36 gklug + * add: Events send by PNMI + * add: parameter definition for Flow Control etc. + * + * Revision 1.1 1998/08/27 11:50:27 gklug + * initial revision + * + * + ******************************************************************************/ + +#ifndef _INC_SKGESIRQ_H_ +#define _INC_SKGESIRQ_H_ + +/* + * Define the Event the special IRQ/INI module can handle + */ +#define SK_HWEV_WATIM 1 /* Timeout for WA errata #2 XMAC */ +#define SK_HWEV_PORT_START 2 /* Port Start Event by RLMT */ +#define SK_HWEV_PORT_STOP 3 /* Port Stop Event by RLMT */ +#define SK_HWEV_CLEAR_STAT 4 /* Clear Statistics by PNMI */ +#define SK_HWEV_UPDATE_STAT 5 /* Update Statistics by PNMI */ +#define SK_HWEV_SET_LMODE 6 /* Set Link Mode by PNMI */ +#define SK_HWEV_SET_FLOWMODE 7 /* Set Flow Control Mode by PNMI */ +#define SK_HWEV_SET_ROLE 8 /* Set Master/Slave (Role) by PNMI */ +#define SK_HWEV_SET_SPEED 9 /* Set Link Speed by PNMI */ +#define SK_HWEV_HALFDUP_CHK 10 /* Half Duplex Hangup Workaround */ + +#define SK_WA_ACT_TIME (5000000L) /* 5 sec */ +#define SK_WA_INA_TIME (100000L) /* 100 msec */ + +#define SK_HALFDUP_CHK_TIME (10000L) /* 10 msec */ + +/* + * Define the error numbers and messages + */ +#define SKERR_SIRQ_E001 (SK_ERRBASE_SIRQ+0) +#define SKERR_SIRQ_E001MSG "Unknown event" +#define SKERR_SIRQ_E002 (SKERR_SIRQ_E001+1) +#define SKERR_SIRQ_E002MSG "Packet timeout RX1" +#define SKERR_SIRQ_E003 (SKERR_SIRQ_E002+1) +#define SKERR_SIRQ_E003MSG "Packet timeout RX2" +#define SKERR_SIRQ_E004 (SKERR_SIRQ_E003+1) +#define SKERR_SIRQ_E004MSG "MAC 1 not correctly initialized" +#define SKERR_SIRQ_E005 (SKERR_SIRQ_E004+1) +#define SKERR_SIRQ_E005MSG "MAC 2 not correctly initialized" +#define SKERR_SIRQ_E006 (SKERR_SIRQ_E005+1) +#define SKERR_SIRQ_E006MSG "CHECK failure R1" +#define SKERR_SIRQ_E007 (SKERR_SIRQ_E006+1) +#define SKERR_SIRQ_E007MSG "CHECK failure R2" +#define SKERR_SIRQ_E008 (SKERR_SIRQ_E007+1) +#define SKERR_SIRQ_E008MSG "CHECK failure XS1" +#define SKERR_SIRQ_E009 (SKERR_SIRQ_E008+1) +#define SKERR_SIRQ_E009MSG "CHECK failure XA1" +#define SKERR_SIRQ_E010 (SKERR_SIRQ_E009+1) +#define SKERR_SIRQ_E010MSG "CHECK failure XS2" +#define SKERR_SIRQ_E011 (SKERR_SIRQ_E010+1) +#define SKERR_SIRQ_E011MSG "CHECK failure XA2" +#define SKERR_SIRQ_E012 (SKERR_SIRQ_E011+1) +#define SKERR_SIRQ_E012MSG "unexpected IRQ Master error" +#define SKERR_SIRQ_E013 (SKERR_SIRQ_E012+1) +#define SKERR_SIRQ_E013MSG "unexpected IRQ Status error" +#define SKERR_SIRQ_E014 (SKERR_SIRQ_E013+1) +#define SKERR_SIRQ_E014MSG "Parity error on RAM (read)" +#define SKERR_SIRQ_E015 (SKERR_SIRQ_E014+1) +#define SKERR_SIRQ_E015MSG "Parity error on RAM (write)" +#define SKERR_SIRQ_E016 (SKERR_SIRQ_E015+1) +#define SKERR_SIRQ_E016MSG "Parity error MAC 1" +#define SKERR_SIRQ_E017 (SKERR_SIRQ_E016+1) +#define SKERR_SIRQ_E017MSG "Parity error MAC 2" +#define SKERR_SIRQ_E018 (SKERR_SIRQ_E017+1) +#define SKERR_SIRQ_E018MSG "Parity error RX 1" +#define SKERR_SIRQ_E019 (SKERR_SIRQ_E018+1) +#define SKERR_SIRQ_E019MSG "Parity error RX 2" +#define SKERR_SIRQ_E020 (SKERR_SIRQ_E019+1) +#define SKERR_SIRQ_E020MSG "MAC transmit FIFO underrun" +#define SKERR_SIRQ_E021 (SKERR_SIRQ_E020+1) +#define SKERR_SIRQ_E021MSG "Spurious TWSI interrupt" +#define SKERR_SIRQ_E022 (SKERR_SIRQ_E021+1) +#define SKERR_SIRQ_E022MSG "Cable pair swap error" +#define SKERR_SIRQ_E023 (SKERR_SIRQ_E022+1) +#define SKERR_SIRQ_E023MSG "Auto-negotiation error" +#define SKERR_SIRQ_E024 (SKERR_SIRQ_E023+1) +#define SKERR_SIRQ_E024MSG "FIFO overflow error" + +extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus); +extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para); +extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port); +extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port); + +#endif /* _INC_SKGESIRQ_H_ */ diff --git a/drivers/sk98lin/h/ski2c.h b/drivers/sk98lin/h/ski2c.h new file mode 100644 index 000000000..5ffaf6ede --- /dev/null +++ b/drivers/sk98lin/h/ski2c.h @@ -0,0 +1,292 @@ +/****************************************************************************** + * + * Name: ski2c.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.34 $ + * Date: $Date: 2003/01/28 09:11:21 $ + * Purpose: Defines to access Voltage and Temperature Sensor + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: ski2c.h,v $ + * Revision 1.34 2003/01/28 09:11:21 rschmidt + * Editorial changes + * + * Revision 1.33 2002/10/14 16:40:50 rschmidt + * Editorial changes (TWSI) + * + * Revision 1.32 2002/08/13 08:55:07 rschmidt + * Editorial changes + * + * Revision 1.31 2002/08/06 09:44:22 jschmalz + * Extensions and changes for Yukon + * + * Revision 1.30 2001/04/05 11:38:09 rassmann + * Set SenState to idle in SkI2cWaitIrq(). + * Changed error message in SkI2cWaitIrq(). + * + * Revision 1.29 2000/08/03 14:28:17 rassmann + * - Added function to wait for I2C being ready before resetting the board. + * - Replaced one duplicate "out of range" message with correct one. + * + * Revision 1.28 1999/11/22 13:55:46 cgoos + * Changed license header to GPL. + * + * Revision 1.27 1999/05/20 09:23:10 cgoos + * Changes for 1000Base-T (Fan sensors). + * + * Revision 1.26 1998/12/01 13:45:47 gklug + * add: InitLevel to I2c struct + * + * Revision 1.25 1998/11/03 06:55:16 gklug + * add: Dummy Reads to I2c struct + * + * Revision 1.24 1998/10/02 14:28:59 cgoos + * Added prototype for SkI2cIsr. + * + * Revision 1.23 1998/09/08 12:20:11 gklug + * add: prototypes for init and read functions + * + * Revision 1.22 1998/09/08 07:37:56 gklug + * add: log error if PCI_IO voltage sensor could not be initialized + * + * Revision 1.21 1998/09/04 08:38:05 malthoff + * Change the values for I2C_READ and I2C_WRITE + * + * Revision 1.20 1998/08/25 07:52:22 gklug + * chg: Timestamps (last) added for logging + * + * Revision 1.19 1998/08/25 06:09:00 gklug + * rmv: warning and error levels of the individual sensors. + * add: timing definitions for sending traps and logging errors + * + * Revision 1.18 1998/08/20 11:41:15 gklug + * chg: omit STRCPY macro by using char * as Sensor Description + * + * Revision 1.17 1998/08/20 11:37:43 gklug + * chg: change Ioc to IoC + * + * Revision 1.16 1998/08/20 11:30:38 gklug + * fix: SenRead declaration + * + * Revision 1.15 1998/08/20 11:27:53 gklug + * fix: Compile bugs with new awrning constants + * + * Revision 1.14 1998/08/20 08:53:12 gklug + * fix: compiler errors + * add: Threshold values + * + * Revision 1.13 1998/08/19 12:21:16 gklug + * fix: remove struct from C files (see CCC) + * add: typedefs for all structs + * + * Revision 1.12 1998/08/19 10:57:41 gklug + * add: Warning levels + * + * Revision 1.11 1998/08/18 08:37:02 malthoff + * Prototypes not required for SK_DIAG. + * + * Revision 1.10 1998/08/17 13:54:00 gklug + * fix: declaration of event function + * + * Revision 1.9 1998/08/17 06:48:39 malthoff + * Remove some unrequired macros. + * Fix the compiler errors. + * + * Revision 1.8 1998/08/14 06:47:19 gklug + * fix: Values are intergers + * + * Revision 1.7 1998/08/14 06:26:05 gklug + * add: Init error message + * + * Revision 1.6 1998/08/13 08:31:08 gklug + * add: Error message + * + * Revision 1.5 1998/08/12 14:32:04 gklug + * add: new error code/message + * + * Revision 1.4 1998/08/12 13:39:08 gklug + * chg: names of error messages + * add: defines for Sensor type and thresholds + * + * Revision 1.3 1998/08/11 07:57:16 gklug + * add: sensor struct + * add: Timeout defines + * add: I2C control struct for pAC + * + * Revision 1.2 1998/07/17 11:29:02 gklug + * rmv: Microwire and SMTPANIC + * + * Revision 1.1 1998/06/19 14:30:10 malthoff + * Created. Sources taken from ML Project. + * + * + ******************************************************************************/ + +/* + * SKI2C.H contains all I2C specific defines + */ + +#ifndef _SKI2C_H_ +#define _SKI2C_H_ + +typedef struct s_Sensor SK_SENSOR; + +#include "h/skgei2c.h" + +/* + * Define the I2C events. + */ +#define SK_I2CEV_IRQ 1 /* IRQ happened Event */ +#define SK_I2CEV_TIM 2 /* Timeout event */ +#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */ + +/* + * Define READ and WRITE Constants. + */ +#undef I2C_READ /* just in case */ +#undef I2C_WRITE /* just in case */ +#define I2C_READ 0 +#define I2C_WRITE 1 +#define I2C_BURST 1 +#define I2C_SINGLE 0 + +#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0) +#define SKERR_I2C_E001MSG "Sensor index unknown" +#define SKERR_I2C_E002 (SKERR_I2C_E001+1) +#define SKERR_I2C_E002MSG "TWSI: transfer does not complete" +#define SKERR_I2C_E003 (SKERR_I2C_E002+1) +#define SKERR_I2C_E003MSG "LM80: NAK on device send" +#define SKERR_I2C_E004 (SKERR_I2C_E003+1) +#define SKERR_I2C_E004MSG "LM80: NAK on register send" +#define SKERR_I2C_E005 (SKERR_I2C_E004+1) +#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send" +#define SKERR_I2C_E006 (SKERR_I2C_E005+1) +#define SKERR_I2C_E006MSG "Unknown event" +#define SKERR_I2C_E007 (SKERR_I2C_E006+1) +#define SKERR_I2C_E007MSG "LM80 read out of state" +#define SKERR_I2C_E008 (SKERR_I2C_E007+1) +#define SKERR_I2C_E008MSG "Unexpected sensor read completed" +#define SKERR_I2C_E009 (SKERR_I2C_E008+1) +#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range" +#define SKERR_I2C_E010 (SKERR_I2C_E009+1) +#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range" +#define SKERR_I2C_E011 (SKERR_I2C_E010+1) +#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range" +#define SKERR_I2C_E012 (SKERR_I2C_E011+1) +#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range" +#define SKERR_I2C_E013 (SKERR_I2C_E012+1) +#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor" +#define SKERR_I2C_E014 (SKERR_I2C_E013+1) +#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range" +#define SKERR_I2C_E015 (SKERR_I2C_E014+1) +#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range" +#define SKERR_I2C_E016 (SKERR_I2C_E015+1) +#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete" + +/* + * Define Timeout values + */ +#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */ +#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */ +#define SK_I2C_TIM_WATCH 1000000L /* 1 second */ + +/* + * Define trap and error log hold times + */ +#ifndef SK_SEN_ERR_TR_HOLD +#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_ERR_LOG_HOLD +#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_WARN_TR_HOLD +#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC) +#endif +#ifndef SK_SEN_WARN_LOG_HOLD +#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC) +#endif + +/* + * Defines for SenType + */ +#define SK_SEN_UNKNOWN 0 +#define SK_SEN_TEMP 1 +#define SK_SEN_VOLT 2 +#define SK_SEN_FAN 3 + +/* + * Define for the SenErrorFlag + */ +#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */ +#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */ +#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */ +#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */ +#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */ + +/* + * Define the Sensor struct + */ +struct s_Sensor { + char *SenDesc; /* Description */ + int SenType; /* Voltage or Temperature */ + SK_I32 SenValue; /* Current value of the sensor */ + SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */ + SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */ + SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */ + SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */ + int SenErrFlag; /* Sensor indicated an error */ + SK_BOOL SenInit; /* Is sensor initialized ? */ + SK_U64 SenErrCts; /* Error trap counter */ + SK_U64 SenWarnCts; /* Warning trap counter */ + SK_U64 SenBegErrTS; /* Begin error timestamp */ + SK_U64 SenBegWarnTS; /* Begin warning timestamp */ + SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */ + SK_U64 SenLastErrLogTS; /* Last error log timestamp */ + SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */ + SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */ + int SenState; /* Sensor State (see HW specific include) */ + int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen); + /* Sensors read function */ + SK_U16 SenReg; /* Register Address for this sensor */ + SK_U8 SenDev; /* Device Selection for this sensor */ +}; + +typedef struct s_I2c { + SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */ + int CurrSens; /* Which sensor is currently queried */ + int MaxSens; /* Max. number of sensors */ + int TimerMode; /* Use the timer also to watch the state machine */ + int InitLevel; /* Initialized Level */ +#ifndef SK_DIAG + int DummyReads; /* Number of non-checked dummy reads */ + SK_TIMER SenTimer; /* Sensors timer */ +#endif /* !SK_DIAG */ +} SK_I2C; + +extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen); +#ifndef SK_DIAG +extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para); +extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level); +extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC); +extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC); + +#endif +#endif /* n_SKI2C_H */ diff --git a/drivers/sk98lin/h/skqueue.h b/drivers/sk98lin/h/skqueue.h new file mode 100644 index 000000000..bce20a75b --- /dev/null +++ b/drivers/sk98lin/h/skqueue.h @@ -0,0 +1,147 @@ +/****************************************************************************** + * + * Name: skqueue.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.14 $ + * Date: $Date: 2002/03/15 10:52:13 $ + * Purpose: Defines for the Event queue + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skqueue.h,v $ + * Revision 1.14 2002/03/15 10:52:13 mkunz + * Added event classes for link aggregation + * + * Revision 1.13 1999/11/22 13:59:05 cgoos + * Changed license header to GPL. + * + * Revision 1.12 1998/09/08 08:48:01 gklug + * add: init level handling + * + * Revision 1.11 1998/09/03 14:15:11 gklug + * add: CSUM and HWAC Eventclass and function. + * fix: pParaPtr according to CCC + * + * Revision 1.10 1998/08/20 12:43:03 gklug + * add: typedef SK_QUEUE + * + * Revision 1.9 1998/08/19 09:50:59 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.8 1998/08/18 07:00:01 gklug + * fix: SK_PTR not defined use void * instead. + * + * Revision 1.7 1998/08/17 13:43:19 gklug + * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR + * + * Revision 1.6 1998/08/14 07:09:30 gklug + * fix: chg pAc -> pAC + * + * Revision 1.5 1998/08/11 14:26:44 gklug + * chg: Event Dispatcher returns now int. + * + * Revision 1.4 1998/08/11 12:15:21 gklug + * add: Error numbers of skqueue module + * + * Revision 1.3 1998/08/07 12:54:23 gklug + * fix: first compiled version + * + * Revision 1.2 1998/08/07 09:34:00 gklug + * adapt structure defs to CCC + * add: prototypes for functions + * + * Revision 1.1 1998/07/30 14:52:12 gklug + * Initial version. + * Defines Event Classes, Event structs and queue management variables. + * + * + * + ******************************************************************************/ + +/* + * SKQUEUE.H contains all defines and types for the event queue + */ + +#ifndef _SKQUEUE_H_ +#define _SKQUEUE_H_ + + +/* + * define the event classes to be served + */ +#define SKGE_DRV 1 /* Driver Event Class */ +#define SKGE_RLMT 2 /* RLMT Event Class */ +#define SKGE_I2C 3 /* i2C Event Class */ +#define SKGE_PNMI 4 /* PNMI Event Class */ +#define SKGE_CSUM 5 /* Checksum Event Class */ +#define SKGE_HWAC 6 /* Hardware Access Event Class */ + +#define SKGE_SWT 9 /* Software Timer Event Class */ +#define SKGE_LACP 10 /* LACP Aggregation Event Class */ +#define SKGE_RSF 11 /* RSF Aggregation Event Class */ +#define SKGE_MARKER 12 /* MARKER Aggregation Event Class */ +#define SKGE_FD 13 /* FD Distributor Event Class */ + +/* + * define event queue as circular buffer + */ +#define SK_MAX_EVENT 64 + +/* + * Parameter union for the Para stuff + */ +typedef union u_EvPara { + void *pParaPtr; /* Parameter Pointer */ + SK_U64 Para64; /* Parameter 64bit version */ + SK_U32 Para32[2]; /* Parameter Array of 32bit parameters */ +} SK_EVPARA; + +/* + * Event Queue + * skqueue.c + * events are class/value pairs + * class is addressee, e.g. RMT, PCM etc. + * value is command, e.g. line state change, ring op change etc. + */ +typedef struct s_EventElem { + SK_U32 Class ; /* Event class */ + SK_U32 Event ; /* Event value */ + SK_EVPARA Para ; /* Event parameter */ +} SK_EVENTELEM; + +typedef struct s_Queue { + SK_EVENTELEM EvQueue[SK_MAX_EVENT]; + SK_EVENTELEM *EvPut ; + SK_EVENTELEM *EvGet ; +} SK_QUEUE; + +extern void SkEventInit(SK_AC *pAC, SK_IOC Ioc, int Level); +extern void SkEventQueue(SK_AC *pAC, SK_U32 Class, SK_U32 Event, + SK_EVPARA Para); +extern int SkEventDispatcher(SK_AC *pAC,SK_IOC Ioc); + + +/* Define Error Numbers and messages */ +#define SKERR_Q_E001 (SK_ERRBASE_QUEUE+0) +#define SKERR_Q_E001MSG "Event queue overflow" +#define SKERR_Q_E002 (SKERR_Q_E001+1) +#define SKERR_Q_E002MSG "Undefined event class" +#endif /* _SKQUEUE_H_ */ diff --git a/drivers/sk98lin/h/skrlmt.h b/drivers/sk98lin/h/skrlmt.h new file mode 100644 index 000000000..04d025b00 --- /dev/null +++ b/drivers/sk98lin/h/skrlmt.h @@ -0,0 +1,563 @@ +/****************************************************************************** + * + * Name: skrlmt.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.35 $ + * Date: $Date: 2003/01/31 14:12:41 $ + * Purpose: Header file for Redundant Link ManagemenT. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skrlmt.h,v $ + * Revision 1.35 2003/01/31 14:12:41 mkunz + * single port adapter runs now with two identical MAC addresses + * + * Revision 1.34 2002/09/23 15:13:41 rwahl + * Editorial changes. + * + * Revision 1.33 2001/07/03 12:16:48 mkunz + * New Flag ChgBcPrio (Change priority of last broadcast received) + * + * Revision 1.32 2001/02/14 14:06:31 rassmann + * Editorial changes. + * + * Revision 1.31 2001/02/05 14:25:26 rassmann + * Prepared RLMT for transparent operation. + * + * Revision 1.30 2001/01/22 13:41:39 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.29 2000/11/17 08:58:00 rassmann + * Moved CheckSwitch from SK_RLMT_PACKET_RECEIVED to SK_RLMT_TIM event. + * + * Revision 1.28 2000/11/09 12:24:34 rassmann + * Editorial changes. + * + * Revision 1.27 1999/11/22 13:59:56 cgoos + * Changed license header to GPL. + * + * Revision 1.26 1999/10/04 14:01:19 rassmann + * Corrected reaction to reception of BPDU frames (#10441). + * + * Revision 1.25 1999/07/20 12:53:39 rassmann + * Fixed documentation errors for lookahead macros. + * + * Revision 1.24 1999/05/28 11:15:56 rassmann + * Changed behaviour to reflect Design Spec v1.2. + * Controlling Link LED(s). + * Introduced RLMT Packet Version field in RLMT Packet. + * Newstyle lookahead macros (checking meta-information before looking at + * the packet). + * + * Revision 1.23 1999/01/28 12:50:42 rassmann + * Not using broadcast time stamps in CheckLinkState mode. + * + * Revision 1.22 1999/01/27 14:13:04 rassmann + * Monitoring broadcast traffic. + * Switching more reliably and not too early if switch is + * configured for spanning tree. + * + * Revision 1.21 1998/12/08 13:11:25 rassmann + * Stopping SegTimer at RlmtStop. + * + * Revision 1.20 1998/11/24 12:37:33 rassmann + * Implemented segmentation check. + * + * Revision 1.19 1998/11/17 13:43:06 rassmann + * Handling (logical) tx failure. + * Sending packet on logical address after PORT_SWITCH. + * + * Revision 1.18 1998/11/13 16:56:56 rassmann + * Added macro version of SkRlmtLookaheadPacket. + * + * Revision 1.17 1998/11/06 18:06:05 rassmann + * Corrected timing when RLMT checks fail. + * Clearing tx counter earlier in periodical checks. + * + * Revision 1.16 1998/11/03 13:53:50 rassmann + * RLMT should switch now (at least in mode 3). + * + * Revision 1.15 1998/10/22 11:39:52 rassmann + * Corrected signed/unsigned mismatches. + * Corrected receive list handling and address recognition. + * + * Revision 1.14 1998/10/15 15:16:36 rassmann + * Finished Spanning Tree checking. + * Checked with lint. + * + * Revision 1.13 1998/09/24 19:16:08 rassmann + * Code cleanup. + * Introduced Timer for PORT_DOWN due to no RX. + * + * Revision 1.12 1998/09/16 11:09:52 rassmann + * Syntax corrections. + * + * Revision 1.11 1998/09/15 11:28:50 rassmann + * Syntax corrections. + * + * Revision 1.10 1998/09/14 17:07:38 rassmann + * Added code for port checking via LAN. + * Changed Mbuf definition. + * + * Revision 1.9 1998/09/07 11:14:15 rassmann + * Syntax corrections. + * + * Revision 1.8 1998/09/07 09:06:08 rassmann + * Syntax corrections. + * + * Revision 1.7 1998/09/04 19:41:34 rassmann + * Syntax corrections. + * Started entering code for checking local links. + * + * Revision 1.6 1998/09/04 12:14:28 rassmann + * Interface cleanup. + * + * Revision 1.5 1998/09/02 16:55:29 rassmann + * Updated to reflect new DRV/HWAC/RLMT interface. + * + * Revision 1.4 1998/09/02 07:26:02 afischer + * typedef for SK_RLMT_PORT + * + * Revision 1.3 1998/08/27 14:29:03 rassmann + * Code cleanup. + * + * Revision 1.2 1998/08/27 14:26:25 rassmann + * Updated interface. + * + * Revision 1.1 1998/08/21 08:29:10 rassmann + * First public version. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This is the header file for Redundant Link ManagemenT. + * + * Include File Hierarchy: + * + * "skdrv1st.h" + * ... + * "sktypes.h" + * "skqueue.h" + * "skaddr.h" + * "skrlmt.h" + * ... + * "skdrv2nd.h" + * + ******************************************************************************/ + +#ifndef __INC_SKRLMT_H +#define __INC_SKRLMT_H + +#ifdef __cplusplus +#error C++ is not yet supported. +extern "C" { +#endif /* cplusplus */ + +/* defines ********************************************************************/ + +#define SK_RLMT_NET_DOWN_TEMP 1 /* NET_DOWN due to last port down. */ +#define SK_RLMT_NET_DOWN_FINAL 2 /* NET_DOWN due to RLMT_STOP. */ + +/* ----- Default queue sizes - must be multiples of 8 KB ----- */ + +/* Less than 8 KB free in RX queue => pause frames. */ +#define SK_RLMT_STANDBY_QRXSIZE 128 /* Size of rx standby queue in KB. */ +#define SK_RLMT_STANDBY_QXASIZE 32 /* Size of async standby queue in KB. */ +#define SK_RLMT_STANDBY_QXSSIZE 0 /* Size of sync standby queue in KB. */ + +#define SK_RLMT_MAX_TX_BUF_SIZE 60 /* Maximum RLMT transmit size. */ + +/* ----- PORT states ----- */ + +#define SK_RLMT_PS_INIT 0 /* Port state: Init. */ +#define SK_RLMT_PS_LINK_DOWN 1 /* Port state: Link down. */ +#define SK_RLMT_PS_DOWN 2 /* Port state: Port down. */ +#define SK_RLMT_PS_GOING_UP 3 /* Port state: Going up. */ +#define SK_RLMT_PS_UP 4 /* Port state: Up. */ + +/* ----- RLMT states ----- */ + +#define SK_RLMT_RS_INIT 0 /* RLMT state: Init. */ +#define SK_RLMT_RS_NET_DOWN 1 /* RLMT state: Net down. */ +#define SK_RLMT_RS_NET_UP 2 /* RLMT state: Net up. */ + +/* ----- PORT events ----- */ + +#define SK_RLMT_LINK_UP 1001 /* Link came up. */ +#define SK_RLMT_LINK_DOWN 1002 /* Link went down. */ +#define SK_RLMT_PORT_ADDR 1003 /* Port address changed. */ + +/* ----- RLMT events ----- */ + +#define SK_RLMT_START 2001 /* Start RLMT. */ +#define SK_RLMT_STOP 2002 /* Stop RLMT. */ +#define SK_RLMT_PACKET_RECEIVED 2003 /* Packet was received for RLMT. */ +#define SK_RLMT_STATS_CLEAR 2004 /* Clear statistics. */ +#define SK_RLMT_STATS_UPDATE 2005 /* Update statistics. */ +#define SK_RLMT_PREFPORT_CHANGE 2006 /* Change preferred port. */ +#define SK_RLMT_MODE_CHANGE 2007 /* New RlmtMode. */ +#define SK_RLMT_SET_NETS 2008 /* Number of Nets (1 or 2). */ + +/* ----- RLMT mode bits ----- */ + +/* + * CAUTION: These defines are private to RLMT. + * Please use the RLMT mode defines below. + */ + +#define SK_RLMT_CHECK_LINK 1 /* Check Link. */ +#define SK_RLMT_CHECK_LOC_LINK 2 /* Check other link on same adapter. */ +#define SK_RLMT_CHECK_SEG 4 /* Check segmentation. */ + +#ifndef RLMT_CHECK_REMOTE +#define SK_RLMT_CHECK_OTHERS SK_RLMT_CHECK_LOC_LINK +#else /* RLMT_CHECK_REMOTE */ +#define SK_RLMT_CHECK_REM_LINK 8 /* Check link(s) on other adapter(s). */ +#define SK_RLMT_MAX_REMOTE_PORTS_CHECKED 3 +#define SK_RLMT_CHECK_OTHERS \ + (SK_RLMT_CHECK_LOC_LINK | SK_RLMT_CHECK_REM_LINK) +#endif /* RLMT_CHECK_REMOTE */ + +#ifndef SK_RLMT_ENABLE_TRANSPARENT +#define SK_RLMT_TRANSPARENT 0 /* RLMT transparent - inactive. */ +#else /* SK_RLMT_ENABLE_TRANSPARENT */ +#define SK_RLMT_TRANSPARENT 128 /* RLMT transparent. */ +#endif /* SK_RLMT_ENABLE_TRANSPARENT */ + +/* ----- RLMT modes ----- */ + +/* Check Link State. */ +#define SK_RLMT_MODE_CLS (SK_RLMT_CHECK_LINK) + +/* Check Local Ports: check other links on the same adapter. */ +#define SK_RLMT_MODE_CLP (SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK) + +/* Check Local Ports and Segmentation Status. */ +#define SK_RLMT_MODE_CLPSS \ + (SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK | SK_RLMT_CHECK_SEG) + +#ifdef RLMT_CHECK_REMOTE +/* Check Local and Remote Ports: check links (local or remote). */ + Name of define TBD! +#define SK_RLMT_MODE_CRP \ + (SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK | SK_RLMT_CHECK_REM_LINK) + +/* Check Local and Remote Ports and Segmentation Status. */ + Name of define TBD! +#define SK_RLMT_MODE_CRPSS \ + (SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK | \ + SK_RLMT_CHECK_REM_LINK | SK_RLMT_CHECK_SEG) +#endif /* RLMT_CHECK_REMOTE */ + +/* ----- RLMT lookahead result bits ----- */ + +#define SK_RLMT_RX_RLMT 1 /* Give packet to RLMT. */ +#define SK_RLMT_RX_PROTOCOL 2 /* Give packet to protocol. */ + +/* Macros */ + +#if 0 +SK_AC *pAC /* adapter context */ +SK_U32 PortNum /* receiving port */ +unsigned PktLen /* received packet's length */ +SK_BOOL IsBc /* Flag: packet is broadcast */ +unsigned *pOffset /* offs. of bytes to present to SK_RLMT_LOOKAHEAD */ +unsigned *pNumBytes /* #Bytes to present to SK_RLMT_LOOKAHEAD */ +#endif /* 0 */ + +#define SK_RLMT_PRE_LOOKAHEAD(pAC,PortNum,PktLen,IsBc,pOffset,pNumBytes) { \ + SK_AC *_pAC; \ + SK_U32 _PortNum; \ + _pAC = (pAC); \ + _PortNum = (SK_U32)(PortNum); \ + /* _pAC->Rlmt.Port[_PortNum].PacketsRx++; */ \ + _pAC->Rlmt.Port[_PortNum].PacketsPerTimeSlot++; \ + if (_pAC->Rlmt.RlmtOff) { \ + *(pNumBytes) = 0; \ + } \ + else {\ + if ((_pAC->Rlmt.Port[_PortNum].Net->RlmtMode & SK_RLMT_TRANSPARENT) != 0) { \ + *(pNumBytes) = 0; \ + } \ + else if (IsBc) { \ + if (_pAC->Rlmt.Port[_PortNum].Net->RlmtMode != SK_RLMT_MODE_CLS) { \ + *(pNumBytes) = 6; \ + *(pOffset) = 6; \ + } \ + else { \ + *(pNumBytes) = 0; \ + } \ + } \ + else { \ + if ((PktLen) > SK_RLMT_MAX_TX_BUF_SIZE) { \ + /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \ + *(pNumBytes) = 0; \ + } \ + else { \ + *(pNumBytes) = 6; \ + *(pOffset) = 0; \ + } \ + } \ + } \ +} + +#if 0 +SK_AC *pAC /* adapter context */ +SK_U32 PortNum /* receiving port */ +SK_U8 *pLaPacket, /* received packet's data (points to pOffset) */ +SK_BOOL IsBc /* Flag: packet is broadcast */ +SK_BOOL IsMc /* Flag: packet is multicast */ +unsigned *pForRlmt /* Result: bits SK_RLMT_RX_RLMT, SK_RLMT_RX_PROTOCOL */ +SK_RLMT_LOOKAHEAD() expects *pNumBytes from +packet offset *pOffset (s.a.) at *pLaPacket. + +If you use SK_RLMT_LOOKAHEAD in a path where you already know if the packet is +BC, MC, or UC, you should use constants for IsBc and IsMc, so that your compiler +can trash unneeded parts of the if construction. +#endif /* 0 */ + +#define SK_RLMT_LOOKAHEAD(pAC,PortNum,pLaPacket,IsBc,IsMc,pForRlmt) { \ + SK_AC *_pAC; \ + SK_U32 _PortNum; \ + SK_U8 *_pLaPacket; \ + _pAC = (pAC); \ + _PortNum = (SK_U32)(PortNum); \ + _pLaPacket = (SK_U8 *)(pLaPacket); \ + if (IsBc) {\ + if (!SK_ADDR_EQUAL(_pLaPacket, _pAC->Addr.Net[_pAC->Rlmt.Port[ \ + _PortNum].Net->NetNumber].CurrentMacAddress.a)) { \ + _pAC->Rlmt.Port[_PortNum].BcTimeStamp = SkOsGetTime(_pAC); \ + _pAC->Rlmt.CheckSwitch = SK_TRUE; \ + } \ + /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \ + *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \ + } \ + else if (IsMc) { \ + if (SK_ADDR_EQUAL(_pLaPacket, BridgeMcAddr.a)) { \ + _pAC->Rlmt.Port[_PortNum].BpduPacketsPerTimeSlot++; \ + if (_pAC->Rlmt.Port[_PortNum].Net->RlmtMode & SK_RLMT_CHECK_SEG) { \ + *(pForRlmt) = SK_RLMT_RX_RLMT | SK_RLMT_RX_PROTOCOL; \ + } \ + else { \ + *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \ + } \ + } \ + else if (SK_ADDR_EQUAL(_pLaPacket, SkRlmtMcAddr.a)) { \ + *(pForRlmt) = SK_RLMT_RX_RLMT; \ + } \ + else { \ + /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \ + *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \ + } \ + } \ + else { \ + if (SK_ADDR_EQUAL( \ + _pLaPacket, \ + _pAC->Addr.Port[_PortNum].CurrentMacAddress.a)) { \ + *(pForRlmt) = SK_RLMT_RX_RLMT; \ + } \ + else { \ + /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \ + *(pForRlmt) = SK_RLMT_RX_PROTOCOL; \ + } \ + } \ +} + +#ifdef SK_RLMT_FAST_LOOKAHEAD +Error: SK_RLMT_FAST_LOOKAHEAD no longer used. Use new macros for lookahead. +#endif /* SK_RLMT_FAST_LOOKAHEAD */ +#ifdef SK_RLMT_SLOW_LOOKAHEAD +Error: SK_RLMT_SLOW_LOOKAHEAD no longer used. Use new macros for lookahead. +#endif /* SK_RLMT_SLOW_LOOKAHEAD */ + +/* typedefs *******************************************************************/ + +#ifdef SK_RLMT_MBUF_PRIVATE +typedef struct s_RlmtMbuf { + some content +} SK_RLMT_MBUF; +#endif /* SK_RLMT_MBUF_PRIVATE */ + + +#ifdef SK_LA_INFO +typedef struct s_Rlmt_PacketInfo { + unsigned PacketLength; /* Length of packet. */ + unsigned PacketType; /* Directed/Multicast/Broadcast. */ +} SK_RLMT_PINFO; +#endif /* SK_LA_INFO */ + + +typedef struct s_RootId { + SK_U8 Id[8]; /* Root Bridge Id. */ +} SK_RLMT_ROOT_ID; + + +typedef struct s_port { + SK_MAC_ADDR CheckAddr; + SK_BOOL SuspectTx; +} SK_PORT_CHECK; + + +typedef struct s_RlmtNet SK_RLMT_NET; + + +typedef struct s_RlmtPort { + +/* ----- Public part (read-only) ----- */ + + SK_U8 PortState; /* Current state of this port. */ + + /* For PNMI */ + SK_BOOL LinkDown; + SK_BOOL PortDown; + SK_U8 Align01; + + SK_U32 PortNumber; /* Number of port on adapter. */ + SK_RLMT_NET * Net; /* Net port belongs to. */ + + SK_U64 TxHelloCts; + SK_U64 RxHelloCts; + SK_U64 TxSpHelloReqCts; + SK_U64 RxSpHelloCts; + +/* ----- Private part ----- */ + +/* SK_U64 PacketsRx; */ /* Total packets received. */ + SK_U32 PacketsPerTimeSlot; /* Packets rxed between TOs. */ +/* SK_U32 DataPacketsPerTimeSlot; */ /* Data packets ... */ + SK_U32 BpduPacketsPerTimeSlot; /* BPDU packets rxed in TS. */ + SK_U64 BcTimeStamp; /* Time of last BC receive. */ + SK_U64 GuTimeStamp; /* Time of entering GOING_UP. */ + + SK_TIMER UpTimer; /* Timer struct Link/Port up. */ + SK_TIMER DownRxTimer; /* Timer struct down rx. */ + SK_TIMER DownTxTimer; /* Timer struct down tx. */ + + SK_U32 CheckingState; /* Checking State. */ + + SK_ADDR_PORT * AddrPort; + + SK_U8 Random[4]; /* Random value. */ + unsigned PortsChecked; /* #ports checked. */ + unsigned PortsSuspect; /* #ports checked that are s. */ + SK_PORT_CHECK PortCheck[1]; +/* SK_PORT_CHECK PortCheck[SK_MAX_MACS - 1]; */ + + SK_BOOL PortStarted; /* Port is started. */ + SK_BOOL PortNoRx; /* NoRx for >= 1 time slot. */ + SK_BOOL RootIdSet; + SK_RLMT_ROOT_ID Root; /* Root Bridge Id. */ +} SK_RLMT_PORT; + + +struct s_RlmtNet { + +/* ----- Public part (read-only) ----- */ + + SK_U32 NetNumber; /* Number of net. */ + + SK_RLMT_PORT * Port[SK_MAX_MACS]; /* Ports that belong to this net. */ + SK_U32 NumPorts; /* Number of ports. */ + SK_U32 PrefPort; /* Preferred port. */ + + /* For PNMI */ + + SK_U32 ChgBcPrio; /* Change Priority of last broadcast received */ + SK_U32 RlmtMode; /* Check ... */ + SK_U32 ActivePort; /* Active port. */ + SK_U32 Preference; /* 0xFFFFFFFF: Automatic. */ + + SK_U8 RlmtState; /* Current RLMT state. */ + +/* ----- Private part ----- */ + SK_BOOL RootIdSet; + SK_U16 Align01; + + int LinksUp; /* #Links up. */ + int PortsUp; /* #Ports up. */ + SK_U32 TimeoutValue; /* RLMT timeout value. */ + + SK_U32 CheckingState; /* Checking State. */ + SK_RLMT_ROOT_ID Root; /* Root Bridge Id. */ + + SK_TIMER LocTimer; /* Timer struct. */ + SK_TIMER SegTimer; /* Timer struct. */ +}; + + +typedef struct s_Rlmt { + +/* ----- Public part (read-only) ----- */ + + SK_U32 NumNets; /* Number of nets. */ + SK_U32 NetsStarted; /* Number of nets started. */ + SK_RLMT_NET Net[SK_MAX_NETS]; /* Array of available nets. */ + SK_RLMT_PORT Port[SK_MAX_MACS]; /* Array of available ports. */ + +/* ----- Private part ----- */ + SK_BOOL CheckSwitch; + SK_BOOL RlmtOff; /* set to zero if the Mac addresses + are equal or the second one + is zero */ + SK_U16 Align01; + +} SK_RLMT; + + +extern SK_MAC_ADDR BridgeMcAddr; +extern SK_MAC_ADDR SkRlmtMcAddr; + +/* function prototypes ********************************************************/ + + +#ifndef SK_KR_PROTO + +/* Functions provided by SkRlmt */ + +/* ANSI/C++ compliant function prototypes */ + +extern void SkRlmtInit( + SK_AC *pAC, + SK_IOC IoC, + int Level); + +extern int SkRlmtEvent( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 Event, + SK_EVPARA Para); + +#else /* defined(SK_KR_PROTO) */ + +/* Non-ANSI/C++ compliant function prototypes */ + +#error KR-style function prototypes are not yet provided. + +#endif /* defined(SK_KR_PROTO)) */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_SKRLMT_H */ diff --git a/drivers/sk98lin/h/sktimer.h b/drivers/sk98lin/h/sktimer.h new file mode 100644 index 000000000..36f8ccb6a --- /dev/null +++ b/drivers/sk98lin/h/sktimer.h @@ -0,0 +1,99 @@ +/****************************************************************************** + * + * Name: sktimer.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.9 $ + * Date: $Date: 1999/11/22 14:00:29 $ + * Purpose: Defines for the timer functions + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: sktimer.h,v $ + * Revision 1.9 1999/11/22 14:00:29 cgoos + * Changed license header to GPL. + * + * Revision 1.8 1998/09/08 08:48:02 gklug + * add: init level handling + * + * Revision 1.7 1998/08/20 12:31:29 gklug + * fix: SK_TIMCTRL needs to be defined + * + * Revision 1.6 1998/08/19 09:51:00 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.5 1998/08/17 13:43:21 gklug + * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR + * + * Revision 1.4 1998/08/14 07:09:31 gklug + * fix: chg pAc -> pAC + * + * Revision 1.3 1998/08/07 12:54:24 gklug + * fix: first compiled version + * + * Revision 1.2 1998/08/07 09:35:29 gklug + * add: Timer control struct for Adapters context + * add: function prototypes + * + * Revision 1.1 1998/08/05 11:27:01 gklug + * First version: adapted from SMT + * + * + ******************************************************************************/ + +/* + * SKTIMER.H contains all defines and types for the timer functions + */ + +#ifndef _SKTIMER_H_ +#define _SKTIMER_H_ + +#include "h/skqueue.h" + +/* + * SK timer + * - needed wherever a timer is used. Put this in your data structure + * wherever you want. + */ +typedef struct s_Timer SK_TIMER; + +struct s_Timer { + SK_TIMER *TmNext ; /* linked list */ + SK_U32 TmClass ; /* Timer Event class */ + SK_U32 TmEvent ; /* Timer Event value */ + SK_EVPARA TmPara ; /* Timer Event parameter */ + SK_U32 TmDelta ; /* delta time */ + int TmActive ; /* flag : active/inactive */ +} ; + +/* + * Timer control struct. + * - use in Adapters context name pAC->Tim + */ +typedef struct s_TimCtrl { + SK_TIMER *StQueue ; /* Head of Timer queue */ +} SK_TIMCTRL ; + +extern void SkTimerInit(SK_AC *pAC,SK_IOC Ioc, int Level); +extern void SkTimerStop(SK_AC *pAC,SK_IOC Ioc,SK_TIMER *pTimer); +extern void SkTimerStart(SK_AC *pAC,SK_IOC Ioc,SK_TIMER *pTimer, + SK_U32 Time,SK_U32 Class,SK_U32 Event,SK_EVPARA Para); +extern void SkTimerDone(SK_AC *pAC,SK_IOC Ioc); +#endif /* _SKTIMER_H_ */ diff --git a/drivers/sk98lin/h/sktypes.h b/drivers/sk98lin/h/sktypes.h new file mode 100644 index 000000000..e657016e5 --- /dev/null +++ b/drivers/sk98lin/h/sktypes.h @@ -0,0 +1,87 @@ +/****************************************************************************** + * + * Name: sktypes.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.3 $ + * Date: $Date: 2003/02/25 14:16:40 $ + * Purpose: Define data types for Linux + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + + /***************************************************************************** + * + * History: + * + * $Log: sktypes.h,v $ + * Revision 1.3 2003/02/25 14:16:40 mlindner + * Fix: Copyright statement + * + * Revision 1.2 1999/11/22 14:01:58 cgoos + * Changed license header to GPL. + * Now using Linux' fixed size types instead of standard types. + * + * Revision 1.1 1999/02/16 07:41:40 cgoos + * First version. + * + * + * + *****************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * In this file, all data types that are needed by the common modules + * are mapped to Linux data types. + * + * + * Include File Hierarchy: + * + * + ******************************************************************************/ + +#ifndef __INC_SKTYPES_H +#define __INC_SKTYPES_H + + +/* defines *******************************************************************/ + +/* + * Data types with a specific size. 'I' = signed, 'U' = unsigned. + */ +#define SK_I8 s8 +#define SK_U8 u8 +#define SK_I16 s16 +#define SK_U16 u16 +#define SK_I32 s32 +#define SK_U32 u32 +#define SK_I64 s64 +#define SK_U64 u64 + +#define SK_UPTR ulong /* casting pointer <-> integral */ + +/* +* Boolean type. +*/ +#define SK_BOOL SK_U8 +#define SK_FALSE 0 +#define SK_TRUE (!SK_FALSE) + +/* typedefs *******************************************************************/ + +/* function prototypes ********************************************************/ + +#endif /* __INC_SKTYPES_H */ diff --git a/drivers/sk98lin/h/skversion.h b/drivers/sk98lin/h/skversion.h new file mode 100644 index 000000000..ef466857d --- /dev/null +++ b/drivers/sk98lin/h/skversion.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Name: version.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.4 $ + * Date: $Date: 2003/02/25 14:16:40 $ + * Purpose: SK specific Error log support + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * $Log: skversion.h,v $ + * Revision 1.4 2003/02/25 14:16:40 mlindner + * Fix: Copyright statement + * + * Revision 1.3 2003/02/25 13:30:18 mlindner + * Add: Support for various vendors + * + * Revision 1.1.2.1 2001/09/05 13:38:30 mlindner + * Removed FILE description + * + * Revision 1.1 2001/03/06 09:25:00 mlindner + * first version + * + * + * + ******************************************************************************/ + + +static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH."; +static const char SysKonnectBuildNumber[] = + "@(#)SK-BUILD: 6.05 PL: 01"; + +#define BOOT_STRING "sk98lin: Network Device Driver v6.05\n" \ + "(C)Copyright 1999-2003 Marvell(R)." + +#define VER_STRING "6.05" diff --git a/drivers/sk98lin/h/skvpd.h b/drivers/sk98lin/h/skvpd.h new file mode 100644 index 000000000..1be34c5a9 --- /dev/null +++ b/drivers/sk98lin/h/skvpd.h @@ -0,0 +1,335 @@ +/****************************************************************************** + * + * Name: skvpd.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.15 $ + * Date: $Date: 2003/01/13 10:39:38 $ + * Purpose: Defines and Macros for VPD handling + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skvpd.h,v $ + * Revision 1.15 2003/01/13 10:39:38 rschmidt + * Replaced define for PCI device Id for YUKON with GENESIS + * Editorial changes + * + * Revision 1.14 2002/11/14 15:18:10 gheinig + * Added const specifier to key and buf parameters for VpdPara,VpdRead + * and VpdWrite. This is necessary for the Diag 7 GUI API + * + * Revision 1.13 2002/10/14 15:58:18 rschmidt + * Added entry in rom_size struct s_vpd + * Editorial changes + * + * Revision 1.12 2002/09/09 14:43:51 mkarl + * added PCI Id of Yukon for reading VPD in diag before the adapter has + * been initialized + * editorial changes + * + * Revision 1.11 2002/07/26 13:19:16 mkarl + * added support for Yukon + * added vpd_size to VPD struct + * + * Revision 1.10 2000/08/10 11:29:07 rassmann + * Editorial changes. + * Preserving 32-bit alignment in structs for the adapter context. + * Removed unused function VpdWriteDword() (#if 0). + * Made VpdReadKeyword() available for SKDIAG only. + * + * Revision 1.9 1999/11/22 14:02:27 cgoos + * Changed license header to GPL. + * + * Revision 1.8 1999/03/11 14:26:40 malthoff + * Replace __STDC__ with SK_KR_PROTO. + * + * Revision 1.7 1998/10/28 07:27:17 gklug + * rmv: SWAP macros + * add: VPD_IN/OUT8 macros + * chg: interface definition + * + * Revision 1.6 1998/10/22 10:03:44 gklug + * fix: use SK_OUT16 instead of SK_OUTW + * + * Revision 1.5 1998/10/14 07:05:31 cgoos + * Changed constants in SK_SWAP_32 to UL. + * + * Revision 1.4 1998/08/19 08:14:09 gklug + * fix: remove struct keyword as much as possible from the C-code (see CCC) + * + * Revision 1.3 1998/08/18 08:18:56 malthoff + * Modify VPD in and out macros for SK_DIAG + * + * Revision 1.2 1998/07/03 14:49:08 malthoff + * Add VPD_INxx() and VPD_OUTxx() macros for the Diagnostics tool. + * + * Revision 1.1 1998/06/19 14:08:03 malthoff + * Created. + * + * + ******************************************************************************/ + +/* + * skvpd.h contains Diagnostic specific defines for VPD handling + */ + +#ifndef __INC_SKVPD_H_ +#define __INC_SKVPD_H_ + +/* + * Define Resource Type Identifiers and VPD keywords + */ +#define RES_ID 0x82 /* Resource Type ID String (Product Name) */ +#define RES_VPD_R 0x90 /* start of VPD read only area */ +#define RES_VPD_W 0x91 /* start of VPD read/write area */ +#define RES_END 0x78 /* Resource Type End Tag */ + +#ifndef VPD_NAME +#define VPD_NAME "Name" /* Product Name, VPD name of RES_ID */ +#endif /* VPD_NAME */ +#define VPD_PN "PN" /* Adapter Part Number */ +#define VPD_EC "EC" /* Adapter Engineering Level */ +#define VPD_MN "MN" /* Manufacture ID */ +#define VPD_SN "SN" /* Serial Number */ +#define VPD_CP "CP" /* Extended Capability */ +#define VPD_RV "RV" /* Checksum and Reserved */ +#define VPD_YA "YA" /* Asset Tag Identifier */ +#define VPD_VL "VL" /* First Error Log Message (SK specific) */ +#define VPD_VF "VF" /* Second Error Log Message (SK specific) */ +#define VPD_RW "RW" /* Remaining Read / Write Area */ + +/* 'type' values for vpd_setup_para() */ +#define VPD_RO_KEY 1 /* RO keys are "PN", "EC", "MN", "SN", "RV" */ +#define VPD_RW_KEY 2 /* RW keys are "Yx", "Vx", and "RW" */ + +/* 'op' values for vpd_setup_para() */ +#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */ +#define OWR_KEY 2 /* overwrite key if already exists */ + +/* + * Define READ and WRITE Constants. + */ + +#define VPD_DEV_ID_GENESIS 0x4300 + +#define VPD_SIZE_YUKON 256 +#define VPD_SIZE_GENESIS 512 +#define VPD_SIZE 512 +#define VPD_READ 0x0000 +#define VPD_WRITE 0x8000 + +#define VPD_STOP(pAC,IoC) VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE) + +#define VPD_GET_RES_LEN(p) ((unsigned int) \ + (* (SK_U8 *)&(p)[1]) |\ + ((* (SK_U8 *)&(p)[2]) << 8)) +#define VPD_GET_VPD_LEN(p) ((unsigned int)(* (SK_U8 *)&(p)[2])) +#define VPD_GET_VAL(p) ((char *)&(p)[3]) + +#define VPD_MAX_LEN 50 + +/* VPD status */ + /* bit 7..1 reserved */ +#define VPD_VALID (1<<0) /* VPD data buffer, vpd_free_ro, */ + /* and vpd_free_rw valid */ + +/* + * VPD structs + */ +typedef struct s_vpd_status { + unsigned short Align01; /* Alignment */ + unsigned short vpd_status; /* VPD status, description see above */ + int vpd_free_ro; /* unused bytes in read only area */ + int vpd_free_rw; /* bytes available in read/write area */ +} SK_VPD_STATUS; + +typedef struct s_vpd { + SK_VPD_STATUS v; /* VPD status structure */ + char vpd_buf[VPD_SIZE]; /* VPD buffer */ + int rom_size; /* VPD ROM Size from PCI_OUR_REG_2 */ + int vpd_size; /* saved VPD-size */ +} SK_VPD; + +typedef struct s_vpd_para { + unsigned int p_len; /* parameter length */ + char *p_val; /* points to the value */ +} SK_VPD_PARA; + +/* + * structure of Large Resource Type Identifiers + */ + +/* was removed because of alignment problems */ + +/* + * structure of VPD keywords + */ +typedef struct s_vpd_key { + char p_key[2]; /* 2 bytes ID string */ + unsigned char p_len; /* 1 byte length */ + char p_val; /* start of the value string */ +} SK_VPD_KEY; + + +/* + * System specific VPD macros + */ +#ifndef SKDIAG +#ifndef VPD_DO_IO +#define VPD_OUT8(pAC,IoC,Addr,Val) (void)SkPciWriteCfgByte(pAC,Addr,Val) +#define VPD_OUT16(pAC,IoC,Addr,Val) (void)SkPciWriteCfgWord(pAC,Addr,Val) +#define VPD_OUT32(pAC,IoC,Addr,Val) (void)SkPciWriteCfgDWord(pAC,Addr,Val) +#define VPD_IN8(pAC,IoC,Addr,pVal) (void)SkPciReadCfgByte(pAC,Addr,pVal) +#define VPD_IN16(pAC,IoC,Addr,pVal) (void)SkPciReadCfgWord(pAC,Addr,pVal) +#define VPD_IN32(pAC,IoC,Addr,pVal) (void)SkPciReadCfgDWord(pAC,Addr,pVal) +#else /* VPD_DO_IO */ +#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(Addr),Val) +#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(Addr),Val) +#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(Addr),Val) +#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(Addr),pVal) +#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(Addr),pVal) +#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(Addr),pVal) +#endif /* VPD_DO_IO */ +#else /* SKDIAG */ +#define VPD_OUT8(pAC,Ioc,Addr,Val) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciWriteCfgByte(pAC,Addr,Val); \ + else \ + SK_OUT8(pAC,PCI_C(Addr),Val); \ + } +#define VPD_OUT16(pAC,Ioc,Addr,Val) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciWriteCfgWord(pAC,Addr,Val); \ + else \ + SK_OUT16(pAC,PCI_C(Addr),Val); \ + } +#define VPD_OUT32(pAC,Ioc,Addr,Val) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciWriteCfgDWord(pAC,Addr,Val); \ + else \ + SK_OUT32(pAC,PCI_C(Addr),Val); \ + } +#define VPD_IN8(pAC,Ioc,Addr,pVal) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciReadCfgByte(pAC,Addr,pVal); \ + else \ + SK_IN8(pAC,PCI_C(Addr),pVal); \ + } +#define VPD_IN16(pAC,Ioc,Addr,pVal) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciReadCfgWord(pAC,Addr,pVal); \ + else \ + SK_IN16(pAC,PCI_C(Addr),pVal); \ + } +#define VPD_IN32(pAC,Ioc,Addr,pVal) { \ + if ((pAC)->DgT.DgUseCfgCycle) \ + SkPciReadCfgDWord(pAC,Addr,pVal); \ + else \ + SK_IN32(pAC,PCI_C(Addr),pVal); \ + } +#endif /* nSKDIAG */ + +/* function prototypes ********************************************************/ + +#ifndef SK_KR_PROTO +#ifdef SKDIAG +extern SK_U32 VpdReadDWord( + SK_AC *pAC, + SK_IOC IoC, + int addr); +#endif /* SKDIAG */ + +extern int VpdSetupPara( + SK_AC *pAC, + const char *key, + const char *buf, + int len, + int type, + int op); + +extern SK_VPD_STATUS *VpdStat( + SK_AC *pAC, + SK_IOC IoC); + +extern int VpdKeys( + SK_AC *pAC, + SK_IOC IoC, + char *buf, + int *len, + int *elements); + +extern int VpdRead( + SK_AC *pAC, + SK_IOC IoC, + const char *key, + char *buf, + int *len); + +extern SK_BOOL VpdMayWrite( + char *key); + +extern int VpdWrite( + SK_AC *pAC, + SK_IOC IoC, + const char *key, + const char *buf); + +extern int VpdDelete( + SK_AC *pAC, + SK_IOC IoC, + char *key); + +extern int VpdUpdate( + SK_AC *pAC, + SK_IOC IoC); + +extern void VpdErrLog( + SK_AC *pAC, + SK_IOC IoC, + char *msg); + +#ifdef SKDIAG +extern int VpdReadBlock( + SK_AC *pAC, + SK_IOC IoC, + char *buf, + int addr, + int len); + +extern int VpdWriteBlock( + SK_AC *pAC, + SK_IOC IoC, + char *buf, + int addr, + int len); +#endif /* SKDIAG */ +#else /* SK_KR_PROTO */ +extern SK_U32 VpdReadDWord(); +extern int VpdSetupPara(); +extern SK_VPD_STATUS *VpdStat(); +extern int VpdKeys(); +extern int VpdRead(); +extern SK_BOOL VpdMayWrite(); +extern int VpdWrite(); +extern int VpdDelete(); +extern int VpdUpdate(); +extern void VpdErrLog(); +#endif /* SK_KR_PROTO */ + +#endif /* __INC_SKVPD_H_ */ diff --git a/drivers/sk98lin/h/xmac_ii.h b/drivers/sk98lin/h/xmac_ii.h new file mode 100644 index 000000000..2ef903a87 --- /dev/null +++ b/drivers/sk98lin/h/xmac_ii.h @@ -0,0 +1,1738 @@ +/****************************************************************************** + * + * Name: xmac_ii.h + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.46 $ + * Date: $Date: 2003/01/28 09:47:45 $ + * Purpose: Defines and Macros for Gigabit Ethernet Controller + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: xmac_ii.h,v $ + * Revision 1.46 2003/01/28 09:47:45 rschmidt + * Added defines for copper MDI/MDIX configuration + * Added defines for LED Control Register + * Editorial changes + * + * Revision 1.45 2002/12/10 14:35:13 rschmidt + * Corrected defines for Extended PHY Specific Control + * Added defines for Ext. PHY Specific Ctrl 2 Reg. (Fiber specific) + * + * Revision 1.44 2002/12/09 14:58:41 rschmidt + * Added defines for Ext. PHY Specific Ctrl Reg. (downshift feature) + * Added 'GMR_FS_UN_SIZE'-Bit to Rx GMAC FIFO Flush Mask + * + * Revision 1.43 2002/12/05 10:14:45 rschmidt + * Added define for GMAC's Half Duplex Burst Mode + * Added define for Rx GMAC FIFO Flush Mask (default) + * + * Revision 1.42 2002/11/12 16:48:19 rschmidt + * Added defines for Cable Diagnostic Register (GPHY) + * Editorial changes + * + * Revision 1.41 2002/10/21 11:20:22 rschmidt + * Added bit GMR_FS_GOOD_FC to GMR_FS_ANY_ERR + * Editorial changes + * + * Revision 1.40 2002/10/14 14:54:14 rschmidt + * Added defines for GPHY Specific Status and GPHY Interrupt Status + * Added bits PHY_M_IS_AN_ERROR and PHY_M_IS_FIFO_ERROR to PHY_M_DEF_MSK + * Editorial changes + * + * Revision 1.39 2002/10/10 15:53:44 mkarl + * added some bit definitions for link speed status and LED's + * + * Revision 1.38 2002/08/21 16:23:46 rschmidt + * Added defines for PHY Specific Ctrl Reg + * Editorial changes + * + * Revision 1.37 2002/08/16 14:50:33 rschmidt + * Added defines for Auto-Neg. Advertisement YUKON Fiber (88E1011S only) + * Changed define PHY_M_DEF_MSK for GPHY IRQ Mask + * Editorial changes + * + * Revision 1.36 2002/08/12 13:21:10 rschmidt + * Added defines for different Broadcom PHY Ids + * + * Revision 1.35 2002/08/08 15:58:01 rschmidt + * Added defines for Manual LED Override register (YUKON) + * Editorial changes + * + * Revision 1.34 2002/07/31 17:23:36 rwahl + * Added define GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR). + * + * Revision 1.33 2002/07/23 16:03:37 rschmidt + * Added defines for GPHY registers + * Editorial changes + * + * Revision 1.32 2002/07/15 18:14:37 rwahl + * Added GMAC MIB counters definitions. + * Editorial changes. + * + * Revision 1.31 2002/07/15 15:42:50 rschmidt + * Removed defines from PHY specific reg. which are + * common to all PHYs + * Added defines for GMAC MIB Counters + * Editorial changes + * + * Revision 1.30 2002/06/05 08:22:12 rschmidt + * Changed defines for GMAC Rx Control Register and Rx Status + * Editorial changes + * + * Revision 1.29 2002/04/25 11:43:56 rschmidt + * Added define PHY_B_AS_PAUSE_MSK for BCom Pause Res. + * Added new registers and defines for YUKON (GMAC, GPHY) + * Added Receive Frame Status Encoding for YUKON + * Editorial changes + * + * Revision 1.28 2000/11/09 12:32:49 rassmann + * Renamed variables. + * + * Revision 1.27 2000/05/17 11:00:46 malthoff + * Add bit for enable/disable power management in BCOM chip. + * + * Revision 1.26 1999/11/22 14:03:00 cgoos + * Changed license header to GPL. + * + * Revision 1.25 1999/08/12 19:19:38 malthoff + * Add PHY_B_AC_TX_TST bit according to BCOM A1 errata sheet. + * + * Revision 1.24 1999/07/30 11:27:21 cgoos + * Fixed a missing end-of-comment. + * + * Revision 1.23 1999/07/30 07:03:31 malthoff + * Cut some long comments. + * Correct the XMAC PHY ID definitions. + * + * Revision 1.22 1999/05/19 07:33:18 cgoos + * Changes for 1000Base-T. + * + * Revision 1.21 1999/03/25 07:46:11 malthoff + * Add XM_HW_CFG, XM_TS_READ, and XM_TS_LOAD registers. + * + * Revision 1.20 1999/03/12 13:36:09 malthoff + * Remove __STDC__. + * + * Revision 1.19 1998/12/10 12:22:54 gklug + * fix: RX_PAGE must be in interrupt mask + * + * Revision 1.18 1998/12/10 10:36:36 gklug + * fix: swap of pause bits + * + * Revision 1.17 1998/11/18 13:21:45 gklug + * fix: Default interrupt mask + * + * Revision 1.16 1998/10/29 15:53:21 gklug + * fix: Default mask uses ASS (GP0) signal + * + * Revision 1.15 1998/10/28 13:52:52 malthoff + * Add new bits in RX_CMD register. + * + * Revision 1.14 1998/10/19 15:34:53 gklug + * fix: typos + * + * Revision 1.13 1998/10/14 07:19:03 malthoff + * bug fix: Every define which describes bit 31 + * must be declared as unsigned long 'UL'. + * fix bit definitions of PHY_AN_RFB and PHY_AN_PAUSE. + * Remove ANP defines. Rework the RFB defines. + * + * Revision 1.12 1998/10/14 06:22:44 cgoos + * Changed shifted constant to ULONG. + * + * Revision 1.11 1998/10/14 05:43:26 gklug + * add: shift pause coding + * fix: PAUSE bits definition + * + * Revision 1.10 1998/10/13 09:19:21 malthoff + * Again change XMR_FS_ANY_ERR because of new info from XaQti. + * + * Revision 1.9 1998/10/09 07:58:30 malthoff + * Add XMR_FS_FCS_ERR to XMR_FS_ANY_ERR. + * + * Revision 1.8 1998/10/09 07:18:17 malthoff + * bug fix of a bug fix: XM_PAUSE_MODE and XM_DEF_MODE + * are not inverted! Bug XM_DEF_MSK is inverted. + * + * Revision 1.7 1998/10/05 08:04:32 malthoff + * bug fix: XM_PAUSE_MODE and XM_DEF_MODE + * must be inverted declarations. + * + * Revision 1.6 1998/09/28 13:38:18 malthoff + * Add default modes and masks XM_DEF_MSK, + * XM_PAUSE_MODE and XM_DEF_MODE + * + * Revision 1.5 1998/09/16 14:42:04 malthoff + * Bug Fix: XM_GP_PORT is a 32 bit (not a 16 bit) register. + * + * Revision 1.4 1998/08/20 14:59:47 malthoff + * Rework this file after reading the XaQti data sheet + * "Differences between Rev. B2 & Rev. C XMAC II". + * This file is now 100% XMAC II Rev. C complained. + * + * Revision 1.3 1998/06/29 12:18:23 malthoff + * Correct XMR_FS_ANY_ERR definition. + * + * Revision 1.2 1998/06/29 12:10:56 malthoff + * Add define XMR_FS_ANY_ERR. + * + * Revision 1.1 1998/06/19 13:37:17 malthoff + * created. + * + * + ******************************************************************************/ + +#ifndef __INC_XMAC_H +#define __INC_XMAC_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* defines ********************************************************************/ + +/* + * XMAC II registers + * + * The XMAC registers are 16 or 32 bits wide. + * The XMACs host processor interface is set to 16 bit mode, + * therefore ALL registers will be addressed with 16 bit accesses. + * + * The following macros are provided to access the XMAC registers + * XM_IN16(), XM_OUT16, XM_IN32(), XM_OUT32(), XM_INADR(), XM_OUTADR(), + * XM_INHASH(), and XM_OUTHASH(). + * The macros are defined in SkGeHw.h. + * + * Note: NA reg = Network Address e.g DA, SA etc. + * + */ +#define XM_MMU_CMD 0x0000 /* 16 bit r/w MMU Command Register */ + /* 0x0004: reserved */ +#define XM_POFF 0x0008 /* 32 bit r/w Packet Offset Register */ +#define XM_BURST 0x000c /* 32 bit r/w Burst Register for half duplex*/ +#define XM_1L_VLAN_TAG 0x0010 /* 16 bit r/w One Level VLAN Tag ID */ +#define XM_2L_VLAN_TAG 0x0014 /* 16 bit r/w Two Level VLAN Tag ID */ + /* 0x0018 - 0x001e: reserved */ +#define XM_TX_CMD 0x0020 /* 16 bit r/w Transmit Command Register */ +#define XM_TX_RT_LIM 0x0024 /* 16 bit r/w Transmit Retry Limit Register */ +#define XM_TX_STIME 0x0028 /* 16 bit r/w Transmit Slottime Register */ +#define XM_TX_IPG 0x002c /* 16 bit r/w Transmit Inter Packet Gap */ +#define XM_RX_CMD 0x0030 /* 16 bit r/w Receive Command Register */ +#define XM_PHY_ADDR 0x0034 /* 16 bit r/w PHY Address Register */ +#define XM_PHY_DATA 0x0038 /* 16 bit r/w PHY Data Register */ + /* 0x003c: reserved */ +#define XM_GP_PORT 0x0040 /* 32 bit r/w General Purpose Port Register */ +#define XM_IMSK 0x0044 /* 16 bit r/w Interrupt Mask Register */ +#define XM_ISRC 0x0048 /* 16 bit r/o Interrupt Status Register */ +#define XM_HW_CFG 0x004c /* 16 bit r/w Hardware Config Register */ + /* 0x0050 - 0x005e: reserved */ +#define XM_TX_LO_WM 0x0060 /* 16 bit r/w Tx FIFO Low Water Mark */ +#define XM_TX_HI_WM 0x0062 /* 16 bit r/w Tx FIFO High Water Mark */ +#define XM_TX_THR 0x0064 /* 16 bit r/w Tx Request Threshold */ +#define XM_HT_THR 0x0066 /* 16 bit r/w Host Request Threshold */ +#define XM_PAUSE_DA 0x0068 /* NA reg r/w Pause Destination Address */ + /* 0x006e: reserved */ +#define XM_CTL_PARA 0x0070 /* 32 bit r/w Control Parameter Register */ +#define XM_MAC_OPCODE 0x0074 /* 16 bit r/w Opcode for MAC control frames */ +#define XM_MAC_PTIME 0x0076 /* 16 bit r/w Pause time for MAC ctrl frames*/ +#define XM_TX_STAT 0x0078 /* 32 bit r/o Tx Status LIFO Register */ + + /* 0x0080 - 0x00fc: 16 NA reg r/w Exact Match Address Registers */ + /* use the XM_EXM() macro to address */ +#define XM_EXM_START 0x0080 /* r/w Start Address of the EXM Regs */ + + /* + * XM_EXM(Reg) + * + * returns the XMAC address offset of specified Exact Match Addr Reg + * + * para: Reg EXM register to addr (0 .. 15) + * + * usage: XM_INADDR(IoC, MAC_1, XM_EXM(i), &val[i]); + */ +#define XM_EXM(Reg) (XM_EXM_START + ((Reg) << 3)) + +#define XM_SRC_CHK 0x0100 /* NA reg r/w Source Check Address Register */ +#define XM_SA 0x0108 /* NA reg r/w Station Address Register */ +#define XM_HSM 0x0110 /* 64 bit r/w Hash Match Address Registers */ +#define XM_RX_LO_WM 0x0118 /* 16 bit r/w Receive Low Water Mark */ +#define XM_RX_HI_WM 0x011a /* 16 bit r/w Receive High Water Mark */ +#define XM_RX_THR 0x011c /* 32 bit r/w Receive Request Threshold */ +#define XM_DEV_ID 0x0120 /* 32 bit r/o Device ID Register */ +#define XM_MODE 0x0124 /* 32 bit r/w Mode Register */ +#define XM_LSA 0x0128 /* NA reg r/o Last Source Register */ + /* 0x012e: reserved */ +#define XM_TS_READ 0x0130 /* 32 bit r/o Time Stamp Read Register */ +#define XM_TS_LOAD 0x0134 /* 32 bit r/o Time Stamp Load Value */ + /* 0x0138 - 0x01fe: reserved */ +#define XM_STAT_CMD 0x0200 /* 16 bit r/w Statistics Command Register */ +#define XM_RX_CNT_EV 0x0204 /* 32 bit r/o Rx Counter Event Register */ +#define XM_TX_CNT_EV 0x0208 /* 32 bit r/o Tx Counter Event Register */ +#define XM_RX_EV_MSK 0x020c /* 32 bit r/w Rx Counter Event Mask */ +#define XM_TX_EV_MSK 0x0210 /* 32 bit r/w Tx Counter Event Mask */ + /* 0x0204 - 0x027e: reserved */ +#define XM_TXF_OK 0x0280 /* 32 bit r/o Frames Transmitted OK Conuter */ +#define XM_TXO_OK_HI 0x0284 /* 32 bit r/o Octets Transmitted OK High Cnt*/ +#define XM_TXO_OK_LO 0x0288 /* 32 bit r/o Octets Transmitted OK Low Cnt */ +#define XM_TXF_BC_OK 0x028c /* 32 bit r/o Broadcast Frames Xmitted OK */ +#define XM_TXF_MC_OK 0x0290 /* 32 bit r/o Multicast Frames Xmitted OK */ +#define XM_TXF_UC_OK 0x0294 /* 32 bit r/o Unicast Frames Xmitted OK */ +#define XM_TXF_LONG 0x0298 /* 32 bit r/o Tx Long Frame Counter */ +#define XM_TXE_BURST 0x029c /* 32 bit r/o Tx Burst Event Counter */ +#define XM_TXF_MPAUSE 0x02a0 /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */ +#define XM_TXF_MCTRL 0x02a4 /* 32 bit r/o Tx MAC Ctrl Frame Counter */ +#define XM_TXF_SNG_COL 0x02a8 /* 32 bit r/o Tx Single Collision Counter */ +#define XM_TXF_MUL_COL 0x02ac /* 32 bit r/o Tx Multiple Collision Counter */ +#define XM_TXF_ABO_COL 0x02b0 /* 32 bit r/o Tx aborted due to Exces. Col. */ +#define XM_TXF_LAT_COL 0x02b4 /* 32 bit r/o Tx Late Collision Counter */ +#define XM_TXF_DEF 0x02b8 /* 32 bit r/o Tx Deferred Frame Counter */ +#define XM_TXF_EX_DEF 0x02bc /* 32 bit r/o Tx Excessive Deferall Counter */ +#define XM_TXE_FIFO_UR 0x02c0 /* 32 bit r/o Tx FIFO Underrun Event Cnt */ +#define XM_TXE_CS_ERR 0x02c4 /* 32 bit r/o Tx Carrier Sense Error Cnt */ +#define XM_TXP_UTIL 0x02c8 /* 32 bit r/o Tx Utilization in % */ + /* 0x02cc - 0x02ce: reserved */ +#define XM_TXF_64B 0x02d0 /* 32 bit r/o 64 Byte Tx Frame Counter */ +#define XM_TXF_127B 0x02d4 /* 32 bit r/o 65-127 Byte Tx Frame Counter */ +#define XM_TXF_255B 0x02d8 /* 32 bit r/o 128-255 Byte Tx Frame Counter */ +#define XM_TXF_511B 0x02dc /* 32 bit r/o 256-511 Byte Tx Frame Counter */ +#define XM_TXF_1023B 0x02e0 /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/ +#define XM_TXF_MAX_SZ 0x02e4 /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/ + /* 0x02e8 - 0x02fe: reserved */ +#define XM_RXF_OK 0x0300 /* 32 bit r/o Frames Received OK */ +#define XM_RXO_OK_HI 0x0304 /* 32 bit r/o Octets Received OK High Cnt */ +#define XM_RXO_OK_LO 0x0308 /* 32 bit r/o Octets Received OK Low Counter*/ +#define XM_RXF_BC_OK 0x030c /* 32 bit r/o Broadcast Frames Received OK */ +#define XM_RXF_MC_OK 0x0310 /* 32 bit r/o Multicast Frames Received OK */ +#define XM_RXF_UC_OK 0x0314 /* 32 bit r/o Unicast Frames Received OK */ +#define XM_RXF_MPAUSE 0x0318 /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */ +#define XM_RXF_MCTRL 0x031c /* 32 bit r/o Rx MAC Ctrl Frame Counter */ +#define XM_RXF_INV_MP 0x0320 /* 32 bit r/o Rx invalid Pause Frame Cnt */ +#define XM_RXF_INV_MOC 0x0324 /* 32 bit r/o Rx Frames with inv. MAC Opcode*/ +#define XM_RXE_BURST 0x0328 /* 32 bit r/o Rx Burst Event Counter */ +#define XM_RXE_FMISS 0x032c /* 32 bit r/o Rx Missed Frames Event Cnt */ +#define XM_RXF_FRA_ERR 0x0330 /* 32 bit r/o Rx Framing Error Counter */ +#define XM_RXE_FIFO_OV 0x0334 /* 32 bit r/o Rx FIFO overflow Event Cnt */ +#define XM_RXF_JAB_PKT 0x0338 /* 32 bit r/o Rx Jabber Packet Frame Cnt */ +#define XM_RXE_CAR_ERR 0x033c /* 32 bit r/o Rx Carrier Event Error Cnt */ +#define XM_RXF_LEN_ERR 0x0340 /* 32 bit r/o Rx in Range Length Error */ +#define XM_RXE_SYM_ERR 0x0344 /* 32 bit r/o Rx Symbol Error Counter */ +#define XM_RXE_SHT_ERR 0x0348 /* 32 bit r/o Rx Short Event Error Cnt */ +#define XM_RXE_RUNT 0x034c /* 32 bit r/o Rx Runt Event Counter */ +#define XM_RXF_LNG_ERR 0x0350 /* 32 bit r/o Rx Frame too Long Error Cnt */ +#define XM_RXF_FCS_ERR 0x0354 /* 32 bit r/o Rx Frame Check Seq. Error Cnt */ + /* 0x0358 - 0x035a: reserved */ +#define XM_RXF_CEX_ERR 0x035c /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/ +#define XM_RXP_UTIL 0x0360 /* 32 bit r/o Rx Utilization in % */ + /* 0x0364 - 0x0366: reserved */ +#define XM_RXF_64B 0x0368 /* 32 bit r/o 64 Byte Rx Frame Counter */ +#define XM_RXF_127B 0x036c /* 32 bit r/o 65-127 Byte Rx Frame Counter */ +#define XM_RXF_255B 0x0370 /* 32 bit r/o 128-255 Byte Rx Frame Counter */ +#define XM_RXF_511B 0x0374 /* 32 bit r/o 256-511 Byte Rx Frame Counter */ +#define XM_RXF_1023B 0x0378 /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/ +#define XM_RXF_MAX_SZ 0x037c /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/ + /* 0x02e8 - 0x02fe: reserved */ + + +/*----------------------------------------------------------------------------*/ +/* + * XMAC Bit Definitions + * + * If the bit access behaviour differs from the register access behaviour + * (r/w, r/o) this is documented after the bit number. + * The following bit access behaviours are used: + * (sc) self clearing + * (ro) read only + */ + +/* XM_MMU_CMD 16 bit r/w MMU Command Register */ + /* Bit 15..13: reserved */ +#define XM_MMU_PHY_RDY (1<<12) /* Bit 12: PHY Read Ready */ +#define XM_MMU_PHY_BUSY (1<<11) /* Bit 11: PHY Busy */ +#define XM_MMU_IGN_PF (1<<10) /* Bit 10: Ignore Pause Frame */ +#define XM_MMU_MAC_LB (1<<9) /* Bit 9: Enable MAC Loopback */ + /* Bit 8: reserved */ +#define XM_MMU_FRC_COL (1<<7) /* Bit 7: Force Collision */ +#define XM_MMU_SIM_COL (1<<6) /* Bit 6: Simulate Collision */ +#define XM_MMU_NO_PRE (1<<5) /* Bit 5: No MDIO Preamble */ +#define XM_MMU_GMII_FD (1<<4) /* Bit 4: GMII uses Full Duplex */ +#define XM_MMU_RAT_CTRL (1<<3) /* Bit 3: Enable Rate Control */ +#define XM_MMU_GMII_LOOP (1<<2) /* Bit 2: PHY is in Loopback Mode */ +#define XM_MMU_ENA_RX (1<<1) /* Bit 1: Enable Receiver */ +#define XM_MMU_ENA_TX (1<<0) /* Bit 0: Enable Transmitter */ + + +/* XM_TX_CMD 16 bit r/w Transmit Command Register */ + /* Bit 15..7: reserved */ +#define XM_TX_BK2BK (1<<6) /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/ +#define XM_TX_ENC_BYP (1<<5) /* Bit 5: Set Encoder in Bypass Mode */ +#define XM_TX_SAM_LINE (1<<4) /* Bit 4: (sc) Start utilization calculation */ +#define XM_TX_NO_GIG_MD (1<<3) /* Bit 3: Disable Carrier Extension */ +#define XM_TX_NO_PRE (1<<2) /* Bit 2: Disable Preamble Generation */ +#define XM_TX_NO_CRC (1<<1) /* Bit 1: Disable CRC Generation */ +#define XM_TX_AUTO_PAD (1<<0) /* Bit 0: Enable Automatic Padding */ + + +/* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */ + /* Bit 15..5: reserved */ +#define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */ + + +/* XM_TX_STIME 16 bit r/w Transmit Slottime Register */ + /* Bit 15..7: reserved */ +#define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */ + + +/* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */ + /* Bit 15..8: reserved */ +#define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */ + + +/* XM_RX_CMD 16 bit r/w Receive Command Register */ + /* Bit 15..9: reserved */ +#define XM_RX_LENERR_OK (1<<8) /* Bit 8 don't set Rx Err bit for */ + /* inrange error packets */ +#define XM_RX_BIG_PK_OK (1<<7) /* Bit 7 don't set Rx Err bit for */ + /* jumbo packets */ +#define XM_RX_IPG_CAP (1<<6) /* Bit 6 repl. type field with IPG */ +#define XM_RX_TP_MD (1<<5) /* Bit 5: Enable transparent Mode */ +#define XM_RX_STRIP_FCS (1<<4) /* Bit 4: Enable FCS Stripping */ +#define XM_RX_SELF_RX (1<<3) /* Bit 3: Enable Rx of own packets */ +#define XM_RX_SAM_LINE (1<<2) /* Bit 2: (sc) Start utilization calculation */ +#define XM_RX_STRIP_PAD (1<<1) /* Bit 1: Strip pad bytes of Rx frames */ +#define XM_RX_DIS_CEXT (1<<0) /* Bit 0: Disable carrier ext. check */ + + +/* XM_PHY_ADDR 16 bit r/w PHY Address Register */ + /* Bit 15..5: reserved */ +#define XM_PHY_ADDR_SZ 0x1f /* Bit 4..0: PHY Address bits */ + + +/* XM_GP_PORT 32 bit r/w General Purpose Port Register */ + /* Bit 31..7: reserved */ +#define XM_GP_ANIP (1L<<6) /* Bit 6: (ro) Auto-Neg. in progress */ +#define XM_GP_FRC_INT (1L<<5) /* Bit 5: (sc) Force Interrupt */ + /* Bit 4: reserved */ +#define XM_GP_RES_MAC (1L<<3) /* Bit 3: (sc) Reset MAC and FIFOs */ +#define XM_GP_RES_STAT (1L<<2) /* Bit 2: (sc) Reset the statistics module */ + /* Bit 1: reserved */ +#define XM_GP_INP_ASS (1L<<0) /* Bit 0: (ro) GP Input Pin asserted */ + + +/* XM_IMSK 16 bit r/w Interrupt Mask Register */ +/* XM_ISRC 16 bit r/o Interrupt Status Register */ + /* Bit 15: reserved */ +#define XM_IS_LNK_AE (1<<14) /* Bit 14: Link Asynchronous Event */ +#define XM_IS_TX_ABORT (1<<13) /* Bit 13: Transmit Abort, late Col. etc */ +#define XM_IS_FRC_INT (1<<12) /* Bit 12: Force INT bit set in GP */ +#define XM_IS_INP_ASS (1<<11) /* Bit 11: Input Asserted, GP bit 0 set */ +#define XM_IS_LIPA_RC (1<<10) /* Bit 10: Link Partner requests config */ +#define XM_IS_RX_PAGE (1<<9) /* Bit 9: Page Received */ +#define XM_IS_TX_PAGE (1<<8) /* Bit 8: Next Page Loaded for Transmit */ +#define XM_IS_AND (1<<7) /* Bit 7: Auto-Negotiation Done */ +#define XM_IS_TSC_OV (1<<6) /* Bit 6: Time Stamp Counter Overflow */ +#define XM_IS_RXC_OV (1<<5) /* Bit 5: Rx Counter Event Overflow */ +#define XM_IS_TXC_OV (1<<4) /* Bit 4: Tx Counter Event Overflow */ +#define XM_IS_RXF_OV (1<<3) /* Bit 3: Receive FIFO Overflow */ +#define XM_IS_TXF_UR (1<<2) /* Bit 2: Transmit FIFO Underrun */ +#define XM_IS_TX_COMP (1<<1) /* Bit 1: Frame Tx Complete */ +#define XM_IS_RX_COMP (1<<0) /* Bit 0: Frame Rx Complete */ + +#define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE |\ + XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | XM_IS_TXF_UR)) + + +/* XM_HW_CFG 16 bit r/w Hardware Config Register */ + /* Bit 15.. 4: reserved */ +#define XM_HW_GEN_EOP (1<<3) /* Bit 3: generate End of Packet pulse */ +#define XM_HW_COM4SIG (1<<2) /* Bit 2: use Comma Detect for Sig. Det.*/ + /* Bit 1: reserved */ +#define XM_HW_GMII_MD (1<<0) /* Bit 0: GMII Interface selected */ + + +/* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */ +/* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */ + /* Bit 15..10 reserved */ +#define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */ + +/* XM_TX_THR 16 bit r/w Tx Request Threshold */ +/* XM_HT_THR 16 bit r/w Host Request Threshold */ +/* XM_RX_THR 16 bit r/w Rx Request Threshold */ + /* Bit 15..11 reserved */ +#define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */ + + +/* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */ +#define XM_ST_VALID (1UL<<31) /* Bit 31: Status Valid */ +#define XM_ST_BYTE_CNT (0x3fffL<<17) /* Bit 30..17: Tx frame Length */ +#define XM_ST_RETRY_CNT (0x1fL<<12) /* Bit 16..12: Retry Count */ +#define XM_ST_EX_COL (1L<<11) /* Bit 11: Excessive Collisions */ +#define XM_ST_EX_DEF (1L<<10) /* Bit 10: Excessive Deferral */ +#define XM_ST_BURST (1L<<9) /* Bit 9: p. xmitted in burst md*/ +#define XM_ST_DEFER (1L<<8) /* Bit 8: packet was defered */ +#define XM_ST_BC (1L<<7) /* Bit 7: Broadcast packet */ +#define XM_ST_MC (1L<<6) /* Bit 6: Multicast packet */ +#define XM_ST_UC (1L<<5) /* Bit 5: Unicast packet */ +#define XM_ST_TX_UR (1L<<4) /* Bit 4: FIFO Underrun occured */ +#define XM_ST_CS_ERR (1L<<3) /* Bit 3: Carrier Sense Error */ +#define XM_ST_LAT_COL (1L<<2) /* Bit 2: Late Collision Error */ +#define XM_ST_MUL_COL (1L<<1) /* Bit 1: Multiple Collisions */ +#define XM_ST_SGN_COL (1L<<0) /* Bit 0: Single Collision */ + +/* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */ +/* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */ + /* Bit 15..11: reserved */ +#define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */ + + +/* XM_DEV_ID 32 bit r/o Device ID Register */ +#define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */ +#define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */ + + +/* XM_MODE 32 bit r/w Mode Register */ + /* Bit 31..27: reserved */ +#define XM_MD_ENA_REJ (1L<<26) /* Bit 26: Enable Frame Reject */ +#define XM_MD_SPOE_E (1L<<25) /* Bit 25: Send Pause on Edge */ + /* extern generated */ +#define XM_MD_TX_REP (1L<<24) /* Bit 24: Transmit Repeater Mode */ +#define XM_MD_SPOFF_I (1L<<23) /* Bit 23: Send Pause on FIFO full */ + /* intern generated */ +#define XM_MD_LE_STW (1L<<22) /* Bit 22: Rx Stat Word in Little Endian */ +#define XM_MD_TX_CONT (1L<<21) /* Bit 21: Send Continuous */ +#define XM_MD_TX_PAUSE (1L<<20) /* Bit 20: (sc) Send Pause Frame */ +#define XM_MD_ATS (1L<<19) /* Bit 19: Append Time Stamp */ +#define XM_MD_SPOL_I (1L<<18) /* Bit 18: Send Pause on Low */ + /* intern generated */ +#define XM_MD_SPOH_I (1L<<17) /* Bit 17: Send Pause on High */ + /* intern generated */ +#define XM_MD_CAP (1L<<16) /* Bit 16: Check Address Pair */ +#define XM_MD_ENA_HASH (1L<<15) /* Bit 15: Enable Hashing */ +#define XM_MD_CSA (1L<<14) /* Bit 14: Check Station Address */ +#define XM_MD_CAA (1L<<13) /* Bit 13: Check Address Array */ +#define XM_MD_RX_MCTRL (1L<<12) /* Bit 12: Rx MAC Control Frame */ +#define XM_MD_RX_RUNT (1L<<11) /* Bit 11: Rx Runt Frames */ +#define XM_MD_RX_IRLE (1L<<10) /* Bit 10: Rx in Range Len Err Frame */ +#define XM_MD_RX_LONG (1L<<9) /* Bit 9: Rx Long Frame */ +#define XM_MD_RX_CRCE (1L<<8) /* Bit 8: Rx CRC Error Frame */ +#define XM_MD_RX_ERR (1L<<7) /* Bit 7: Rx Error Frame */ +#define XM_MD_DIS_UC (1L<<6) /* Bit 6: Disable Rx Unicast */ +#define XM_MD_DIS_MC (1L<<5) /* Bit 5: Disable Rx Multicast */ +#define XM_MD_DIS_BC (1L<<4) /* Bit 4: Disable Rx Broadcast */ +#define XM_MD_ENA_PROM (1L<<3) /* Bit 3: Enable Promiscuous */ +#define XM_MD_ENA_BE (1L<<2) /* Bit 2: Enable Big Endian */ +#define XM_MD_FTF (1L<<1) /* Bit 1: (sc) Flush Tx FIFO */ +#define XM_MD_FRF (1L<<0) /* Bit 0: (sc) Flush Rx FIFO */ + +#define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I) +#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\ + XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA) + +/* XM_STAT_CMD 16 bit r/w Statistics Command Register */ + /* Bit 16..6: reserved */ +#define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */ +#define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */ +#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */ +#define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */ +#define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */ +#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */ + + +/* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */ +/* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */ +#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/ +#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/ +#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/ +#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/ +#define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */ +#define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */ +#define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */ +#define XMR_UTIL_UR (1L<<24) /* Bit 24: Rx Util Cnt Underrun */ +#define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */ + /* Bit 22: reserved */ +#define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */ +#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/ +#define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */ +#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/ +#define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */ + /* Bit 16: reserved */ +#define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */ +#define XMR_JAB_PKT_OV (1L<<14) /* Bit 14: Rx Jabb Packet Cnt Ov */ +#define XMR_FIFO_OV (1L<<13) /* Bit 13: Rx FIFO Ov Ev Cnt Ov */ +#define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */ +#define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */ +#define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */ +#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/ +#define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */ +#define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */ +#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/ +#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/ +#define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */ +#define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */ +#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/ +#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/ +#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */ + +#define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV) + +/* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */ +/* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */ + /* Bit 31..26: reserved */ +#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/ +#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/ +#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/ +#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/ +#define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */ +#define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */ +#define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */ +#define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */ +#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/ +#define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */ +#define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */ +#define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */ +#define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */ +#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/ +#define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */ +#define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */ +#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/ +#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/ +#define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */ +#define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */ +#define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */ +#define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */ +#define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */ +#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/ +#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/ +#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */ + +#define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV) + +/* + * Receive Frame Status Encoding + */ +#define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */ +#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/ +#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/ +#define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */ +#define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */ +#define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */ + /* Bit 12: reserved */ +#define XMR_FS_BURST (1L<<11) /* Bit 11: Burst Mode */ +#define XMR_FS_CEX_ERR (1L<<10) /* Bit 10: Carrier Ext. Error */ +#define XMR_FS_802_3 (1L<<9) /* Bit 9: 802.3 Frame */ +#define XMR_FS_COL_ERR (1L<<8) /* Bit 8: Collision Error */ +#define XMR_FS_CAR_ERR (1L<<7) /* Bit 7: Carrier Event Error */ +#define XMR_FS_LEN_ERR (1L<<6) /* Bit 6: In-Range Length Error */ +#define XMR_FS_FRA_ERR (1L<<5) /* Bit 5: Framing Error */ +#define XMR_FS_RUNT (1L<<4) /* Bit 4: Runt Frame */ +#define XMR_FS_LNG_ERR (1L<<3) /* Bit 3: Giant (Jumbo) Frame */ +#define XMR_FS_FCS_ERR (1L<<2) /* Bit 2: Frame Check Sequ Err */ +#define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */ +#define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */ + +/* + * XMR_FS_ERR will be set if + * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT, + * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR + * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue + * XMR_FS_ERR unless the corresponding bit in the Receive Command + * Register is set. + */ +#define XMR_FS_ANY_ERR XMR_FS_ERR + +/*----------------------------------------------------------------------------*/ +/* + * XMAC-PHY Registers, indirect addressed over the XMAC + */ +#define PHY_XMAC_CTRL 0x00 /* 16 bit r/w PHY Control Register */ +#define PHY_XMAC_STAT 0x01 /* 16 bit r/w PHY Status Register */ +#define PHY_XMAC_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ +#define PHY_XMAC_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ +#define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ +#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Abi Reg */ +#define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ +#define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */ +#define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */ + /* 0x09 - 0x0e: reserved */ +#define PHY_XMAC_EXT_STAT 0x0f /* 16 bit r/o Ext Status Register */ +#define PHY_XMAC_RES_ABI 0x10 /* 16 bit r/o PHY Resolved Ability */ + +/*----------------------------------------------------------------------------*/ +/* + * Broadcom-PHY Registers, indirect addressed over XMAC + */ +#define PHY_BCOM_CTRL 0x00 /* 16 bit r/w PHY Control Register */ +#define PHY_BCOM_STAT 0x01 /* 16 bit r/o PHY Status Register */ +#define PHY_BCOM_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ +#define PHY_BCOM_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ +#define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ +#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ +#define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ +#define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */ +#define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */ + /* Broadcom-specific registers */ +#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ +#define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ + /* 0x0b - 0x0e: reserved */ +#define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ +#define PHY_BCOM_P_EXT_CTRL 0x10 /* 16 bit r/w PHY Extended Ctrl Reg */ +#define PHY_BCOM_P_EXT_STAT 0x11 /* 16 bit r/o PHY Extended Stat Reg */ +#define PHY_BCOM_RE_CTR 0x12 /* 16 bit r/w Receive Error Counter */ +#define PHY_BCOM_FC_CTR 0x13 /* 16 bit r/w False Carr Sense Cnt */ +#define PHY_BCOM_RNO_CTR 0x14 /* 16 bit r/w Receiver NOT_OK Cnt */ + /* 0x15 - 0x17: reserved */ +#define PHY_BCOM_AUX_CTRL 0x18 /* 16 bit r/w Auxiliary Control Reg */ +#define PHY_BCOM_AUX_STAT 0x19 /* 16 bit r/o Auxiliary Stat Summary */ +#define PHY_BCOM_INT_STAT 0x1a /* 16 bit r/o Interrupt Status Reg */ +#define PHY_BCOM_INT_MASK 0x1b /* 16 bit r/w Interrupt Mask Reg */ + /* 0x1c: reserved */ + /* 0x1d - 0x1f: test registers */ + +/*----------------------------------------------------------------------------*/ +/* + * Marvel-PHY Registers, indirect addressed over GMAC + */ +#define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ +#define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ +#define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ +#define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ +#define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ +#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ +#define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ +#define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ +#define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link P Reg */ + /* Marvel-specific registers */ +#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */ +#define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ + /* 0x0b - 0x0e: reserved */ +#define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ +#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Ctrl Reg */ +#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Stat Reg */ +#define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ +#define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ +#define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ +#define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ +#define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ + /* 0x17: reserved */ +#define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ +#define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ +#define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ +#define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ +#define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ + /* 0x1d - 0x1f: reserved */ + +/*----------------------------------------------------------------------------*/ +/* + * Level One-PHY Registers, indirect addressed over XMAC + */ +#define PHY_LONE_CTRL 0x00 /* 16 bit r/w PHY Control Register */ +#define PHY_LONE_STAT 0x01 /* 16 bit r/o PHY Status Register */ +#define PHY_LONE_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ +#define PHY_LONE_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ +#define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ +#define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ +#define PHY_LONE_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ +#define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */ +#define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner*/ + /* Level One-specific registers */ +#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/ +#define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ + /* 0x0b -0x0e: reserved */ +#define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ +#define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/ +#define PHY_LONE_Q_STAT 0x11 /* 16 bit r/o Quick Status Reg */ +#define PHY_LONE_INT_ENAB 0x12 /* 16 bit r/w Interrupt Enable Reg */ +#define PHY_LONE_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ +#define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */ +#define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */ +#define PHY_LONE_CIM 0x16 /* 16 bit r/o CIM Reg */ + /* 0x17 -0x1c: reserved */ + +/*----------------------------------------------------------------------------*/ +/* + * National-PHY Registers, indirect addressed over XMAC + */ +#define PHY_NAT_CTRL 0x00 /* 16 bit r/w PHY Control Register */ +#define PHY_NAT_STAT 0x01 /* 16 bit r/w PHY Status Register */ +#define PHY_NAT_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ +#define PHY_NAT_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ +#define PHY_NAT_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ +#define PHY_NAT_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */ +#define PHY_NAT_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ +#define PHY_NAT_NEPG 0x07 /* 16 bit r/w Next Page Register */ +#define PHY_NAT_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner Reg */ + /* National-specific registers */ +#define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ +#define PHY_NAT_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ + /* 0x0b -0x0e: reserved */ +#define PHY_NAT_EXT_STAT 0x0f /* 16 bit r/o Extended Status Register */ +#define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit r/o Extended Control Reg1 */ +#define PHY_NAT_Q_STAT1 0x11 /* 16 bit r/o Quick Status Reg1 */ +#define PHY_NAT_10B_OP 0x12 /* 16 bit r/o 10Base-T Operations Reg */ +#define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit r/o Extended Control Reg1 */ +#define PHY_NAT_Q_STAT2 0x14 /* 16 bit r/o Quick Status Reg2 */ + /* 0x15 -0x18: reserved */ +#define PHY_NAT_PHY_ADDR 0x19 /* 16 bit r/o PHY Address Register */ + + +/*----------------------------------------------------------------------------*/ + +/* + * PHY bit definitions + * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are + * Xmac/Broadcom/LevelOne/National-specific. + * All other are general. + */ + +/***** PHY_XMAC_CTRL 16 bit r/w PHY Control Register *****/ +/***** PHY_BCOM_CTRL 16 bit r/w PHY Control Register *****/ +/***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/ +#define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ +#define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ +#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */ +#define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ +#define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */ +#define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */ +#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ +#define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ +#define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */ +#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */ + /* Bit 5..0: reserved */ + +#define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ +#define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ +#define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ + + +/***** PHY_XMAC_STAT 16 bit r/w PHY Status Register *****/ +/***** PHY_BCOM_STAT 16 bit r/w PHY Status Register *****/ +/***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/ +/***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/ + /* Bit 15..9: reserved */ + /* (BC/L1) 100/10 Mbps cap bits ignored*/ +#define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ + /* Bit 7: reserved */ +#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */ +#define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ +#define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */ +#define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ +#define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ +#define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */ +#define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ + + +/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */ +/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */ +/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */ +/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */ +#define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ +#define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ +#define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */ + +/* different Broadcom PHY Ids */ +#define PHY_BCOM_ID1_A1 0x6041 +#define PHY_BCOM_ID1_B2 0x6043 +#define PHY_BCOM_ID1_C0 0x6044 +#define PHY_BCOM_ID1_C5 0x6047 + + +/***** PHY_XMAC_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ +/***** PHY_XMAC_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ +#define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */ +#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */ +#define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remote Fault Bits */ + /* Bit 11.. 9: reserved */ +#define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */ +#define PHY_X_AN_HD (1<<6) /* Bit 6: Half Duplex */ +#define PHY_X_AN_FD (1<<5) /* Bit 5: Full Duplex */ + /* Bit 4.. 0: reserved */ + +/***** PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ +/***** PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ +/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ + /* Bit 14: reserved */ +#define PHY_B_AN_RF (1<<13) /* Bit 13: Remote Fault */ + /* Bit 12: reserved */ +#define PHY_B_AN_ASP (1<<11) /* Bit 11: Asymmetric Pause */ +#define PHY_B_AN_PC (1<<10) /* Bit 10: Pause Capable */ + /* Bit 9..5: 100/10 BT cap bits ingnored */ +#define PHY_B_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/ + +/***** PHY_LONE_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ +/***** PHY_LONE_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ +/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ + /* Bit 14: reserved */ +#define PHY_L_AN_RF (1<<13) /* Bit 13: Remote Fault */ + /* Bit 12: reserved */ +#define PHY_L_AN_ASP (1<<11) /* Bit 11: Asymmetric Pause */ +#define PHY_L_AN_PC (1<<10) /* Bit 10: Pause Capable */ + /* Bit 9..5: 100/10 BT cap bits ingnored */ +#define PHY_L_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/ + +/***** PHY_NAT_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ +/***** PHY_NAT_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ +/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */ + /* Bit 14: reserved */ +#define PHY_N_AN_RF (1<<13) /* Bit 13: Remote Fault */ + /* Bit 12: reserved */ +#define PHY_N_AN_100F (1<<11) /* Bit 11: 100Base-T2 FD Support */ +#define PHY_N_AN_100H (1<<10) /* Bit 10: 100Base-T2 HD Support */ + /* Bit 9..5: 100/10 BT cap bits ingnored */ +#define PHY_N_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/ + +/* field type definition for PHY_x_AN_SEL */ +#define PHY_SEL_TYPE 0x01 /* 00001 = Ethernet */ + +/***** PHY_XMAC_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ + /* Bit 15..4: reserved */ +#define PHY_AN_LP_NP (1<<3) /* Bit 3: Link Partner can Next Page */ +#define PHY_AN_LOC_NP (1<<2) /* Bit 2: Local PHY can Next Page */ +#define PHY_AN_RX_PG (1<<1) /* Bit 1: Page Received */ + /* Bit 0: reserved */ + +/***** PHY_BCOM_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ + /* Bit 15..5: reserved */ +#define PHY_B_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */ +/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */ +/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */ +/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */ +#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */ + +/***** PHY_LONE_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/ +#define PHY_L_AN_BP (1<<5) /* Bit 5: Base Page Indication */ +#define PHY_L_AN_PDF (1<<4) /* Bit 4: Parallel Detection Fault */ +/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */ +/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */ +/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */ +#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */ + + +/***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/ +/***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/ +/***** PHY_LONE_NEPG 16 bit r/w Next Page Register *****/ +/***** PHY_XMAC_NEPG_LP 16 bit r/o Next Page Link Partner *****/ +/***** PHY_BCOM_NEPG_LP 16 bit r/o Next Page Link Partner *****/ +/***** PHY_LONE_NEPG_LP 16 bit r/o Next Page Link Partner *****/ +#define PHY_NP_MORE (1<<15) /* Bit 15: More, Next Pages to follow */ +#define PHY_NP_ACK1 (1<<14) /* Bit 14: (ro) Ack 1, for receiving a message*/ +#define PHY_NP_MSG_VAL (1<<13) /* Bit 13: Message Page valid */ +#define PHY_NP_ACK2 (1<<12) /* Bit 12: Ack 2, comply with msg content*/ +#define PHY_NP_TOG (1<<11) /* Bit 11: Toggle Bit, ensure sync */ +#define PHY_NP_MSG 0x07ff /* Bit 10..0: Message from/to Link Partner */ + +/* + * XMAC-Specific + */ +/***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/ +#define PHY_X_EX_FD (1<<15) /* Bit 15: Device Supports Full Duplex */ +#define PHY_X_EX_HD (1<<14) /* Bit 14: Device Supports Half Duplex */ + /* Bit 13..0: reserved */ + +/***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/ + /* Bit 15..9: reserved */ +#define PHY_X_RS_PAUSE (3<<7) /* Bit 8..7: selected Pause Mode */ +#define PHY_X_RS_HD (1<<6) /* Bit 6: Half Duplex Mode selected */ +#define PHY_X_RS_FD (1<<5) /* Bit 5: Full Duplex Mode selected */ +#define PHY_X_RS_ABLMIS (1<<4) /* Bit 4: duplex or pause cap mismatch */ +#define PHY_X_RS_PAUMIS (1<<3) /* Bit 3: pause capability missmatch */ + /* Bit 2..0: reserved */ +/* + * Remote Fault Bits (PHY_X_AN_RFB) encoding + */ +#define X_RFB_OK (0<<12) /* Bit 13..12 No errors, Link OK */ +#define X_RFB_LF (1<<12) /* Bit 13..12 Link Failure */ +#define X_RFB_OFF (2<<12) /* Bit 13..12 Offline */ +#define X_RFB_AN_ERR (3<<12) /* Bit 13..12 Auto-Negotiation Error */ + +/* + * Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding + */ +#define PHY_X_P_NO_PAUSE (0<<7) /* Bit 8..7: no Pause Mode */ +#define PHY_X_P_SYM_MD (1<<7) /* Bit 8..7: symmetric Pause Mode */ +#define PHY_X_P_ASYM_MD (2<<7) /* Bit 8..7: asymmetric Pause Mode */ +#define PHY_X_P_BOTH_MD (3<<7) /* Bit 8..7: both Pause Mode */ + + +/* + * Broadcom-Specific + */ +/***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ +#define PHY_B_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ +#define PHY_B_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ +#define PHY_B_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ +#define PHY_B_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ +#define PHY_B_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ +#define PHY_B_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ + /* Bit 7..0: reserved */ + +/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ +#define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ +#define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ +#define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ +#define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ +#define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ +#define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ + /* Bit 9..8: reserved */ +#define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ + +/***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/ +#define PHY_B_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ +#define PHY_B_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ +#define PHY_B_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ +#define PHY_B_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ + /* Bit 11..0: reserved */ + +/***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/ +#define PHY_B_PEC_MAC_PHY (1<<15) /* Bit 15: 10BIT/GMI-Interface */ +#define PHY_B_PEC_DIS_CROSS (1<<14) /* Bit 14: Disable MDI Crossover */ +#define PHY_B_PEC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */ +#define PHY_B_PEC_INT_DIS (1<<12) /* Bit 12: Interrupts Disabled */ +#define PHY_B_PEC_F_INT (1<<11) /* Bit 11: Force Interrupt */ +#define PHY_B_PEC_BY_45 (1<<10) /* Bit 10: Bypass 4B5B-Decoder */ +#define PHY_B_PEC_BY_SCR (1<<9) /* Bit 9: Bypass Scrambler */ +#define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */ +#define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */ +#define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */ +#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */ +#define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */ +#define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */ +#define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */ +#define PHY_B_PEC_3_LED (1<<1) /* Bit 1: Three Link LED mode */ +#define PHY_B_PEC_HIGH_LA (1<<0) /* Bit 0: GMII FIFO Elasticy */ + +/***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/ + /* Bit 15..14: reserved */ +#define PHY_B_PES_CROSS_STAT (1<<13) /* Bit 13: MDI Crossover Status */ +#define PHY_B_PES_INT_STAT (1<<12) /* Bit 12: Interrupt Status */ +#define PHY_B_PES_RRS (1<<11) /* Bit 11: Remote Receiver Stat. */ +#define PHY_B_PES_LRS (1<<10) /* Bit 10: Local Receiver Stat. */ +#define PHY_B_PES_LOCKED (1<<9) /* Bit 9: Locked */ +#define PHY_B_PES_LS (1<<8) /* Bit 8: Link Status */ +#define PHY_B_PES_RF (1<<7) /* Bit 7: Remote Fault */ +#define PHY_B_PES_CE_ER (1<<6) /* Bit 6: Carrier Ext Error */ +#define PHY_B_PES_BAD_SSD (1<<5) /* Bit 5: Bad SSD */ +#define PHY_B_PES_BAD_ESD (1<<4) /* Bit 4: Bad ESD */ +#define PHY_B_PES_RX_ER (1<<3) /* Bit 3: Receive Error */ +#define PHY_B_PES_TX_ER (1<<2) /* Bit 2: Transmit Error */ +#define PHY_B_PES_LOCK_ER (1<<1) /* Bit 1: Lock Error */ +#define PHY_B_PES_MLT3_ER (1<<0) /* Bit 0: MLT3 code Error */ + +/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/ + /* Bit 15..8: reserved */ +#define PHY_B_FC_CTR 0xff /* Bit 7..0: False Carrier Counter */ + +/***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/ +#define PHY_B_RC_LOC_MSK 0xff00 /* Bit 15..8: Local Rx NOT_OK cnt */ +#define PHY_B_RC_REM_MSK 0x00ff /* Bit 7..0: Remote Rx NOT_OK cnt */ + +/***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/ +#define PHY_B_AC_L_SQE (1<<15) /* Bit 15: Low Squelch */ +#define PHY_B_AC_LONG_PACK (1<<14) /* Bit 14: Rx Long Packets */ +#define PHY_B_AC_ER_CTRL (3<<12) /* Bit 13..12: Edgerate Control */ + /* Bit 11: reserved */ +#define PHY_B_AC_TX_TST (1<<10) /* Bit 10: Tx test bit, always 1 */ + /* Bit 9.. 8: reserved */ +#define PHY_B_AC_DIS_PRF (1<<7) /* Bit 7: dis part resp filter */ + /* Bit 6: reserved */ +#define PHY_B_AC_DIS_PM (1<<5) /* Bit 5: dis power management */ + /* Bit 4: reserved */ +#define PHY_B_AC_DIAG (1<<3) /* Bit 3: Diagnostic Mode */ + /* Bit 2.. 0: reserved */ + +/***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/ +#define PHY_B_AS_AN_C (1<<15) /* Bit 15: AutoNeg complete */ +#define PHY_B_AS_AN_CA (1<<14) /* Bit 14: AN Complete Ack */ +#define PHY_B_AS_ANACK_D (1<<13) /* Bit 13: AN Ack Detect */ +#define PHY_B_AS_ANAB_D (1<<12) /* Bit 12: AN Ability Detect */ +#define PHY_B_AS_NPW (1<<11) /* Bit 11: AN Next Page Wait */ +#define PHY_B_AS_AN_RES_MSK (7<<8) /* Bit 10..8: AN HDC */ +#define PHY_B_AS_PDF (1<<7) /* Bit 7: Parallel Detect. Fault */ +#define PHY_B_AS_RF (1<<6) /* Bit 6: Remote Fault */ +#define PHY_B_AS_ANP_R (1<<5) /* Bit 5: AN Page Received */ +#define PHY_B_AS_LP_ANAB (1<<4) /* Bit 4: LP AN Ability */ +#define PHY_B_AS_LP_NPAB (1<<3) /* Bit 3: LP Next Page Ability */ +#define PHY_B_AS_LS (1<<2) /* Bit 2: Link Status */ +#define PHY_B_AS_PRR (1<<1) /* Bit 1: Pause Resolution-Rx */ +#define PHY_B_AS_PRT (1<<0) /* Bit 0: Pause Resolution-Tx */ + +#define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT) + +/***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/ +/***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ + /* Bit 15: reserved */ +#define PHY_B_IS_PSE (1<<14) /* Bit 14: Pair Swap Error */ +#define PHY_B_IS_MDXI_SC (1<<13) /* Bit 13: MDIX Status Change */ +#define PHY_B_IS_HCT (1<<12) /* Bit 12: counter above 32k */ +#define PHY_B_IS_LCT (1<<11) /* Bit 11: counter above 128 */ +#define PHY_B_IS_AN_PR (1<<10) /* Bit 10: Page Received */ +#define PHY_B_IS_NO_HDCL (1<<9) /* Bit 9: No HCD Link */ +#define PHY_B_IS_NO_HDC (1<<8) /* Bit 8: No HCD */ +#define PHY_B_IS_NEG_USHDC (1<<7) /* Bit 7: Negotiated Unsup. HCD */ +#define PHY_B_IS_SCR_S_ER (1<<6) /* Bit 6: Scrambler Sync Error */ +#define PHY_B_IS_RRS_CHANGE (1<<5) /* Bit 5: Remote Rx Stat Change */ +#define PHY_B_IS_LRS_CHANGE (1<<4) /* Bit 4: Local Rx Stat Change */ +#define PHY_B_IS_DUP_CHANGE (1<<3) /* Bit 3: Duplex Mode Change */ +#define PHY_B_IS_LSP_CHANGE (1<<2) /* Bit 2: Link Speed Change */ +#define PHY_B_IS_LST_CHANGE (1<<1) /* Bit 1: Link Status Changed */ +#define PHY_B_IS_CRC_ER (1<<0) /* Bit 0: CRC Error */ + +#define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) + +/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */ +#define PHY_B_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */ +#define PHY_B_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */ +#define PHY_B_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */ +#define PHY_B_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */ + +/* + * Resolved Duplex mode and Capabilities (Aux Status Summary Reg) + */ +#define PHY_B_RES_1000FD (7<<8) /* Bit 10..8: 1000Base-T Full Dup. */ +#define PHY_B_RES_1000HD (6<<8) /* Bit 10..8: 1000Base-T Half Dup. */ +/* others: 100/10: invalid for us */ + +/* + * Level One-Specific + */ +/***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ +#define PHY_L_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ +#define PHY_L_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ +#define PHY_L_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ +#define PHY_L_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ +#define PHY_L_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ +#define PHY_L_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ + /* Bit 7..0: reserved */ + +/***** PHY_LONE_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ +#define PHY_L_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ +#define PHY_L_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ +#define PHY_L_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ +#define PHY_L_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/ +#define PHY_L_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ +#define PHY_L_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ + /* Bit 9..8: reserved */ +#define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ + +/***** PHY_LONE_EXT_STAT 16 bit r/o Extended Status Register *****/ +#define PHY_L_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ +#define PHY_L_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ +#define PHY_L_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ +#define PHY_L_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ + /* Bit 11..0: reserved */ + +/***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/ +#define PHY_L_PC_REP_MODE (1<<15) /* Bit 15: Repeater Mode */ + /* Bit 14: reserved */ +#define PHY_L_PC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */ +#define PHY_L_PC_BY_SCR (1<<12) /* Bit 12: Bypass Scrambler */ +#define PHY_L_PC_BY_45 (1<<11) /* Bit 11: Bypass 4B5B-Decoder */ +#define PHY_L_PC_JAB_DIS (1<<10) /* Bit 10: Jabber Disabled */ +#define PHY_L_PC_SQE (1<<9) /* Bit 9: Enable Heartbeat */ +#define PHY_L_PC_TP_LOOP (1<<8) /* Bit 8: TP Loopback */ +#define PHY_L_PC_SSS (1<<7) /* Bit 7: Smart Speed Selection */ +#define PHY_L_PC_FIFO_SIZE (1<<6) /* Bit 6: FIFO Size */ +#define PHY_L_PC_PRE_EN (1<<5) /* Bit 5: Preamble Enable */ +#define PHY_L_PC_CIM (1<<4) /* Bit 4: Carrier Integrity Mon */ +#define PHY_L_PC_10_SER (1<<3) /* Bit 3: Use Serial Output */ +#define PHY_L_PC_ANISOL (1<<2) /* Bit 2: Unisolate Port */ +#define PHY_L_PC_TEN_BIT (1<<1) /* Bit 1: 10bit iface mode on */ +#define PHY_L_PC_ALTCLOCK (1<<0) /* Bit 0: (ro) ALTCLOCK Mode on */ + +/***** PHY_LONE_Q_STAT 16 bit r/o Quick Status Reg *****/ +#define PHY_L_QS_D_RATE (3<<14) /* Bit 15..14: Data Rate */ +#define PHY_L_QS_TX_STAT (1<<13) /* Bit 13: Transmitting */ +#define PHY_L_QS_RX_STAT (1<<12) /* Bit 12: Receiving */ +#define PHY_L_QS_COL_STAT (1<<11) /* Bit 11: Collision */ +#define PHY_L_QS_L_STAT (1<<10) /* Bit 10: Link is up */ +#define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */ +#define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */ +#define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */ +#define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */ +#define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */ +#define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */ +#define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */ +#define PHY_L_QS_EVENT (1<<0) /* Bit 0: Event has occurred */ + +/***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/ +/***** PHY_LONE_INT_STAT 16 bit r/o Interrupt Status Reg *****/ + /* Bit 15..14: reserved */ +#define PHY_L_IS_AN_F (1<<13) /* Bit 13: Auto-Negotiation fault */ + /* Bit 12: not described */ +#define PHY_L_IS_CROSS (1<<11) /* Bit 11: Crossover used */ +#define PHY_L_IS_POL (1<<10) /* Bit 10: Polarity correct. used*/ +#define PHY_L_IS_SS (1<<9) /* Bit 9: Smart Speed Downgrade*/ +#define PHY_L_IS_CFULL (1<<8) /* Bit 8: Counter Full */ +#define PHY_L_IS_AN_C (1<<7) /* Bit 7: AutoNeg Complete */ +#define PHY_L_IS_SPEED (1<<6) /* Bit 6: Speed Changed */ +#define PHY_L_IS_DUP (1<<5) /* Bit 5: Duplex Changed */ +#define PHY_L_IS_LS (1<<4) /* Bit 4: Link Status Changed */ +#define PHY_L_IS_ISOL (1<<3) /* Bit 3: Isolate Occured */ +#define PHY_L_IS_MDINT (1<<2) /* Bit 2: (ro) STAT: MII Int Pending */ +#define PHY_L_IS_INTEN (1<<1) /* Bit 1: ENAB: Enable IRQs */ +#define PHY_L_IS_FORCE (1<<0) /* Bit 0: ENAB: Force Interrupt */ + +/* int. mask */ +#define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN) + +/***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/ +#define PHY_L_LC_LEDC (3<<14) /* Bit 15..14: Col/Blink/On/Off */ +#define PHY_L_LC_LEDR (3<<12) /* Bit 13..12: Rx/Blink/On/Off */ +#define PHY_L_LC_LEDT (3<<10) /* Bit 11..10: Tx/Blink/On/Off */ +#define PHY_L_LC_LEDG (3<<8) /* Bit 9..8: Giga/Blink/On/Off */ +#define PHY_L_LC_LEDS (3<<6) /* Bit 7..6: 10-100/Blink/On/Off */ +#define PHY_L_LC_LEDL (3<<4) /* Bit 5..4: Link/Blink/On/Off */ +#define PHY_L_LC_LEDF (3<<2) /* Bit 3..2: Duplex/Blink/On/Off */ +#define PHY_L_LC_PSTRECH (1<<1) /* Bit 1: Strech LED Pulses */ +#define PHY_L_LC_FREQ (1<<0) /* Bit 0: 30/100 ms */ + +/***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/ +#define PHY_L_PC_TX_TCLK (1<<15) /* Bit 15: Enable TX_TCLK */ + /* Bit 14: reserved */ +#define PHY_L_PC_ALT_NP (1<<13) /* Bit 14: Alternate Next Page */ +#define PHY_L_PC_GMII_ALT (1<<12) /* Bit 13: Alternate GMII driver */ + /* Bit 11: reserved */ +#define PHY_L_PC_TEN_CRS (1<<10) /* Bit 10: Extend CRS*/ + /* Bit 9..0: not described */ + +/***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/ +#define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */ +#define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */ + + +/* + * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding + */ +#define PHY_L_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */ +#define PHY_L_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */ +#define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */ +#define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */ + + +/* + * National-Specific + */ +/***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ +#define PHY_N_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ +#define PHY_N_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */ +#define PHY_N_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */ +#define PHY_N_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */ +#define PHY_N_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ +#define PHY_N_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ +#define PHY_N_1000C_APC (1<<7) /* Bit 7: Asymmetric Pause Cap. */ + /* Bit 6..0: reserved */ + +/***** PHY_NAT_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ +#define PHY_N_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ +#define PHY_N_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ +#define PHY_N_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ +#define PHY_N_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/ +#define PHY_N_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ +#define PHY_N_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ +#define PHY_N_1000C_LP_APC (1<<9) /* Bit 9: LP Asym. Pause Cap. */ + /* Bit 8: reserved */ +#define PHY_N_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ + +/***** PHY_NAT_EXT_STAT 16 bit r/o Extended Status Register *****/ +#define PHY_N_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */ +#define PHY_N_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */ +#define PHY_N_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */ +#define PHY_N_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */ + /* Bit 11..0: reserved */ + +/* todo: those are still missing */ +/***** PHY_NAT_EXT_CTRL1 16 bit r/o Extended Control Reg1 *****/ +/***** PHY_NAT_Q_STAT1 16 bit r/o Quick Status Reg1 *****/ +/***** PHY_NAT_10B_OP 16 bit r/o 10Base-T Operations Reg *****/ +/***** PHY_NAT_EXT_CTRL2 16 bit r/o Extended Control Reg1 *****/ +/***** PHY_NAT_Q_STAT2 16 bit r/o Quick Status Reg2 *****/ +/***** PHY_NAT_PHY_ADDR 16 bit r/o PHY Address Register *****/ + +/* + * Marvell-Specific + */ +/***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ +/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ +#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ +#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ +#define PHY_M_AN_RF BIT_13 /* Remote Fault */ + /* Bit 12: reserved */ +#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ +#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ +#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ +#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ +#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ +#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ + +/* special defines for FIBER (88E1011S only) */ +#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ +#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ +#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ +#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ + +/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ +#define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ +#define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ +#define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ +#define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ + +/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ +#define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ +#define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */ +#define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */ +#define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */ +#define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */ +#define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */ + /* Bit 7..0: reserved */ + +/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ + +#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ +#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ +#define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */ +#define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */ +#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ +#define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */ +#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ +#define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */ +#define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */ +#define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */ +#define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */ +#define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */ + +#define PHY_M_PC_MDI_XMODE(x) SHIFT5(x) +#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ +#define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ +#define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ + +/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ +#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ +#define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */ +#define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */ +#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ +#define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */ +#define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */ +#define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */ +#define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */ +#define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */ +#define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */ +#define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */ +#define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */ +#define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */ +#define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */ +#define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */ +#define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */ + +#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) + +/***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ +/***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ +#define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */ +#define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */ +#define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */ +#define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */ +#define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */ +#define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */ +#define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */ +#define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */ +#define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */ +#define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */ +#define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */ +#define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */ + /* Bit 3..2: reserved */ +#define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */ +#define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */ + +#define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ + PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) + +/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ +#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */ +#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */ +#define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ + +#define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */ +#define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */ +#define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */ + +#define MAC_TX_CLK_0_MHZ 2 +#define MAC_TX_CLK_2_5_MHZ 6 +#define MAC_TX_CLK_25_MHZ 7 + +/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ +#define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */ +#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ +#define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */ +#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ + /* Bit 7.. 5: reserved */ +#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ +#define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */ +#define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */ +#define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */ + +#define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */ + +#define PULS_NO_STR 0 /* no pulse stretching */ +#define PULS_21MS 1 /* 21 ms to 42 ms */ +#define PULS_42MS 2 /* 42 ms to 84 ms */ +#define PULS_84MS 3 /* 84 ms to 170 ms */ +#define PULS_170MS 4 /* 170 ms to 340 ms */ +#define PULS_340MS 5 /* 340 ms to 670 ms */ +#define PULS_670MS 6 /* 670 ms to 1.3 s */ +#define PULS_1300MS 7 /* 1.3 s to 2.7 s */ + +#define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */ + +#define BLINK_42MS 0 /* 42 ms */ +#define BLINK_84MS 1 /* 84 ms */ +#define BLINK_170MS 2 /* 170 ms */ +#define BLINK_340MS 3 /* 340 ms */ +#define BLINK_670MS 4 /* 670 ms */ + /* values 5 - 7: reserved */ + +/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ +#define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ +#define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ +#define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ +#define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ +#define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ +#define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ + +#define MO_LED_NORM 0 +#define MO_LED_BLINK 1 +#define MO_LED_OFF 2 +#define MO_LED_ON 3 + +/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ + /* Bit 15.. 7: reserved */ +#define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */ +#define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */ +#define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */ +#define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */ +#define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ + +/***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ +#define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */ +#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */ + /* Bit 12.. 8: reserved */ +#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */ + +/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ +#define CABD_STAT_NORMAL 0 +#define CABD_STAT_SHORT 1 +#define CABD_STAT_OPEN 2 +#define CABD_STAT_FAIL 3 + + +/* + * GMAC registers + * + * The GMAC registers are 16 or 32 bits wide. + * The GMACs host processor interface is 16 bits wide, + * therefore ALL registers will be addressed with 16 bit accesses. + * + * The following macros are provided to access the GMAC registers + * GM_IN16(), GM_OUT16, GM_IN32(), GM_OUT32(), GM_INADR(), GM_OUTADR(), + * GM_INHASH(), and GM_OUTHASH(). + * The macros are defined in SkGeHw.h. + * + * Note: NA reg = Network Address e.g DA, SA etc. + * + */ + +/* Port Registers */ +#define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ +#define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ +#define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ +#define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ +#define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow Control */ +#define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ +#define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ + +/* Source Address Registers */ +#define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ +#define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ +#define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ +#define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ +#define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ +#define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ + +/* Multicast Address Hash Registers */ +#define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ +#define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ +#define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ +#define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ + +/* Interrupt Source Registers */ +#define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ +#define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ +#define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ + +/* Interrupt Mask Registers */ +#define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ +#define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ +#define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ + +/* Serial Management Interface (SMI) Registers */ +#define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ +#define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ +#define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ + +/* MIB Counters */ +#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ +#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ + +/* + * MIB Counters base address definitions (low word) - + * use offset 4 for access to high word (32 bit r/o) + */ +#define GM_RXF_UC_OK \ + (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ +#define GM_RXF_BC_OK \ + (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ +#define GM_RXF_MPAUSE \ + (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ +#define GM_RXF_MC_OK \ + (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ +#define GM_RXF_FCS_ERR \ + (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ + /* GM_MIB_CNT_BASE + 40: reserved */ +#define GM_RXO_OK_LO \ + (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ +#define GM_RXO_OK_HI \ + (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ +#define GM_RXO_ERR_LO \ + (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ +#define GM_RXO_ERR_HI \ + (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ +#define GM_RXF_SHT \ + (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ +#define GM_RXE_FRAG \ + (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Receeived with FCS Err */ +#define GM_RXF_64B \ + (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ +#define GM_RXF_127B \ + (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ +#define GM_RXF_255B \ + (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ +#define GM_RXF_511B \ + (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ +#define GM_RXF_1023B \ + (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ +#define GM_RXF_1518B \ + (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ +#define GM_RXF_MAX_SZ \ + (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ +#define GM_RXF_LNG_ERR \ + (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ +#define GM_RXF_JAB_PKT \ + (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ + /* GM_MIB_CNT_BASE + 168: reserved */ +#define GM_RXE_FIFO_OV \ + (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ + /* GM_MIB_CNT_BASE + 184: reserved */ +#define GM_TXF_UC_OK \ + (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ +#define GM_TXF_BC_OK \ + (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ +#define GM_TXF_MPAUSE \ + (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ +#define GM_TXF_MC_OK \ + (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ +#define GM_TXO_OK_LO \ + (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ +#define GM_TXO_OK_HI \ + (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ +#define GM_TXF_64B \ + (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ +#define GM_TXF_127B \ + (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ +#define GM_TXF_255B \ + (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ +#define GM_TXF_511B \ + (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ +#define GM_TXF_1023B \ + (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ +#define GM_TXF_1518B \ + (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ +#define GM_TXF_MAX_SZ \ + (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ + /* GM_MIB_CNT_BASE + 296: reserved */ +#define GM_TXF_COL \ + (GM_MIB_CNT_BASE + 304) /* Tx Collision */ +#define GM_TXF_LAT_COL \ + (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ +#define GM_TXF_ABO_COL \ + (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ +#define GM_TXF_MUL_COL \ + (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ +#define GM_TXF_SNG_COL \ + (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ +#define GM_TXE_FIFO_UR \ + (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ + +/*----------------------------------------------------------------------------*/ +/* + * GMAC Bit Definitions + * + * If the bit access behaviour differs from the register access behaviour + * (r/w, r/o) this is documented after the bit number. + * The following bit access behaviours are used: + * (sc) self clearing + * (r/o) read only + */ + +/* GM_GP_STAT 16 bit r/o General Purpose Status Register */ + +#define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */ +#define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */ +#define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow Control Mode Disabled */ +#define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */ +#define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */ +#define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */ +#define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */ +#define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */ + /* Bit 7..6: reserved */ +#define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */ +#define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ +#define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */ +#define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow Control Mode Disabled */ +#define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */ + /* Bit 0: reserved */ + +/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ + /* Bit 15: reserved */ +#define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */ +#define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow Control Mode */ +#define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */ +#define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */ +#define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */ +#define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */ +#define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */ +#define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */ +#define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */ +#define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */ +#define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow Control Mode */ +#define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */ +#define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update for Duplex */ +#define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update for Flow-c. */ +#define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update for Speed */ + +#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) +#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ + GM_GPCR_AU_SPD_DIS) + +/* GM_TX_CTRL 16 bit r/w Transmit Control Register */ + +#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */ +#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */ +#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */ +#define GM_TXCR_COL_THR (4<<10) /* Bit 12..10: Collision Threshold */ + +/* GM_RX_CTRL 16 bit r/w Receive Control Register */ +#define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */ +#define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */ +#define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */ +#define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */ + +/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ +#define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */ +#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */ +#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */ + /* Bit 3..0: reserved */ +#define JAM_LEN_VAL(x) SHIFT14(x) +#define JAM_IPG_VAL(x) SHIFT9(x) +#define IPG_JAM_DATA(x) SHIFT4(x) + +/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ +#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ +#define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive transmit trials */ +#define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Length) */ +#define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Length) */ + /* Bit 7..5: reserved */ +#define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ + +#define DATA_BLIND_VAL(x) SHIFT11(x) +#define DATA_BLIND_FAST_ETH 0x1c +#define DATA_BLIND_GIGABIT 4 + +#define IPG_VAL_FAST_ETH 0x1e +#define IPG_VAL_GIGABIT 6 + +/* GM_SMI_CTRL 16 bit r/w SMI Control Register */ + +#define GM_SMI_CT_PHY_AD(x) SHIFT11(x) +#define GM_SMI_CT_REG_AD(x) SHIFT6(x) +#define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/ +#define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */ +#define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */ + /* Bit 2..0: reserved */ + +/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ + /* Bit 15..6: reserved */ +#define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */ +#define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */ + /* Bit 3..0: reserved */ + +/* Receive Frame Status Encoding */ +#define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */ + /* Bit 15..14: reserved */ +#define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */ +#define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */ +#define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */ +#define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */ +#define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */ +#define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */ +#define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */ +#define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */ +#define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */ +#define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */ +#define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */ + /* Bit 2: reserved */ +#define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */ +#define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */ + +/* + * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR) + */ +#define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \ + GMR_FS_LONG_ERR | \ + GMR_FS_MII_ERR | \ + GMR_FS_BAD_FC | \ + GMR_FS_GOOD_FC | \ + GMR_FS_JABBER) + +/* Rx GMAC FIFO Flush Mask (default) */ +#define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \ + GMR_FS_RX_FF_OV | \ + GMR_FS_MII_ERR | \ + GMR_FS_BAD_FC | \ + GMR_FS_GOOD_FC | \ + GMR_FS_UN_SIZE | \ + GMR_FS_JABBER) + +/* typedefs *******************************************************************/ + + +/* function prototypes ********************************************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INC_XMAC_H */ diff --git a/drivers/sk98lin/skaddr.c b/drivers/sk98lin/skaddr.c new file mode 100644 index 000000000..ed79c049b --- /dev/null +++ b/drivers/sk98lin/skaddr.c @@ -0,0 +1,1879 @@ +/****************************************************************************** + * + * Name: skaddr.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.48 $ + * Date: $Date: 2003/02/12 17:09:37 $ + * Purpose: Manage Addresses (Multicast and Unicast) and Promiscuous Mode. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skaddr.c,v $ + * Revision 1.48 2003/02/12 17:09:37 tschilli + * Fix in SkAddrOverride() to set both (physical and logical) MAC addresses + * in case that both addresses are identical. + * + * Revision 1.47 2002/09/17 06:31:10 tschilli + * Handling of SK_PROM_MODE_ALL_MC flag in SkAddrGmacMcUpdate() + * and SkAddrGmacPromiscuousChange() fixed. + * Editorial changes. + * + * Revision 1.46 2002/08/22 07:55:41 tschilli + * New function SkGmacMcHash() for GMAC multicast hashing algorithm added. + * Editorial changes. + * + * Revision 1.45 2002/08/15 12:29:35 tschilli + * SkAddrGmacMcUpdate() and SkAddrGmacPromiscuousChange() changed. + * + * Revision 1.44 2002/08/14 12:18:03 rschmidt + * Replaced direct handling of MAC Hashing (XMAC and GMAC) + * with routine SkMacHashing(). + * Replaced wrong 3rd para 'i' with 'PortNumber' in SkMacPromiscMode(). + * + * Revision 1.43 2002/08/13 09:37:43 rschmidt + * Corrected some SK_DBG_MSG outputs. + * Replaced wrong 2nd para pAC with IoC in SkMacPromiscMode(). + * Editorial changes. + * + * Revision 1.42 2002/08/12 11:24:36 rschmidt + * Remove setting of logical MAC address GM_SRC_ADDR_2 in SkAddrInit(). + * Replaced direct handling of MAC Promiscuous Mode (XMAC and GMAC) + * with routine SkMacPromiscMode(). + * Editorial changes. + * + * Revision 1.41 2002/06/10 13:52:18 tschilli + * Changes for handling YUKON. + * All changes are internally and not visible to the programmer + * using this module. + * + * Revision 1.40 2001/02/14 14:04:59 rassmann + * Editorial changes. + * + * Revision 1.39 2001/01/30 10:30:04 rassmann + * Editorial changes. + * + * Revision 1.38 2001/01/25 16:26:52 rassmann + * Ensured that logical address overrides are done on net's active port. + * + * Revision 1.37 2001/01/22 13:41:34 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.36 2000/08/07 11:10:39 rassmann + * Editorial changes. + * + * Revision 1.35 2000/05/04 09:38:41 rassmann + * Editorial changes. + * Corrected multicast address hashing. + * + * Revision 1.34 1999/11/22 13:23:44 cgoos + * Changed license header to GPL. + * + * Revision 1.33 1999/05/28 10:56:06 rassmann + * Editorial changes. + * + * Revision 1.32 1999/03/31 10:59:20 rassmann + * Returning Success instead of DupAddr if address shall be overridden + * with same value. + * + * Revision 1.31 1999/01/14 16:18:17 rassmann + * Corrected multicast initialization. + * + * Revision 1.30 1999/01/04 10:30:35 rassmann + * SkAddrOverride only possible after SK_INIT_IO phase. + * + * Revision 1.29 1998/12/29 13:13:10 rassmann + * An address override is now preserved in the SK_INIT_IO phase. + * All functions return an int now. + * Extended parameter checking. + * + * Revision 1.28 1998/12/01 11:45:53 rassmann + * Code cleanup. + * + * Revision 1.27 1998/12/01 09:22:49 rassmann + * SkAddrMcAdd and SkAddrMcUpdate returned SK_MC_FILTERING_INEXACT + * too often. + * + * Revision 1.26 1998/11/24 12:39:44 rassmann + * Reserved multicast entry for BPDU address. + * 13 multicast entries left for protocol. + * + * Revision 1.25 1998/11/17 16:54:23 rassmann + * Using exact match for up to 14 multicast addresses. + * Still receiving all multicasts if more addresses are added. + * + * Revision 1.24 1998/11/13 17:24:31 rassmann + * Changed return value of SkAddrOverride to int. + * + * Revision 1.23 1998/11/13 16:56:18 rassmann + * Added macro SK_ADDR_COMPARE. + * Changed return type of SkAddrOverride to SK_BOOL. + * + * Revision 1.22 1998/11/04 17:06:17 rassmann + * Corrected McUpdate and PromiscuousChange functions. + * + * Revision 1.21 1998/10/29 14:34:04 rassmann + * Clearing SK_ADDR struct at startup. + * + * Revision 1.20 1998/10/28 18:16:34 rassmann + * Avoiding I/Os before SK_INIT_RUN level. + * Aligning InexactFilter. + * + * Revision 1.19 1998/10/28 11:29:28 rassmann + * Programming physical address in SkAddrMcUpdate. + * Corrected programming of exact match entries. + * + * Revision 1.18 1998/10/28 10:34:48 rassmann + * Corrected reading of physical addresses. + * + * Revision 1.17 1998/10/28 10:26:13 rassmann + * Getting ports' current MAC addresses from EPROM now. + * Added debug output. + * + * Revision 1.16 1998/10/27 16:20:12 rassmann + * Reading MAC address byte by byte. + * + * Revision 1.15 1998/10/22 11:39:09 rassmann + * Corrected signed/unsigned mismatches. + * + * Revision 1.14 1998/10/19 17:12:35 rassmann + * Syntax corrections. + * + * Revision 1.13 1998/10/19 17:02:19 rassmann + * Now reading permanent MAC addresses from CRF. + * + * Revision 1.12 1998/10/15 15:15:48 rassmann + * Changed Flags Parameters from SK_U8 to int. + * Checked with lint. + * + * Revision 1.11 1998/09/24 19:15:12 rassmann + * Code cleanup. + * + * Revision 1.10 1998/09/18 20:18:54 rassmann + * Added HW access. + * Implemented swapping. + * + * Revision 1.9 1998/09/16 11:32:00 rassmann + * Including skdrv1st.h again. :( + * + * Revision 1.8 1998/09/16 11:09:34 rassmann + * Syntax corrections. + * + * Revision 1.7 1998/09/14 17:06:34 rassmann + * Minor changes. + * + * Revision 1.6 1998/09/07 08:45:41 rassmann + * Syntax corrections. + * + * Revision 1.5 1998/09/04 19:40:19 rassmann + * Interface enhancements. + * + * Revision 1.4 1998/09/04 12:14:12 rassmann + * Interface cleanup. + * + * Revision 1.3 1998/09/02 16:56:40 rassmann + * Updated interface. + * + * Revision 1.2 1998/08/27 14:26:09 rassmann + * Updated interface. + * + * Revision 1.1 1998/08/21 08:30:22 rassmann + * First public version. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This module is intended to manage multicast addresses, address override, + * and promiscuous mode on GEnesis and Yukon adapters. + * + * Address Layout: + * port address: physical MAC address + * 1st exact match: logical MAC address (GEnesis only) + * 2nd exact match: RLMT multicast (GEnesis only) + * exact match 3-13: OS-specific multicasts (GEnesis only) + * + * Include File Hierarchy: + * + * "skdrv1st.h" + * "skdrv2nd.h" + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#ifndef lint +static const char SysKonnectFileId[] = + "@(#) $Id: skaddr.c,v 1.48 2003/02/12 17:09:37 tschilli Exp $ (C) SysKonnect."; +#endif /* !defined(lint) */ + +#define __SKADDR_C + +#ifdef __cplusplus +#error C++ is not yet supported. +extern "C" { +#endif /* cplusplus */ + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + +/* defines ********************************************************************/ + + +#define XMAC_POLY 0xEDB88320UL /* CRC32-Poly - XMAC: Little Endian */ +#define GMAC_POLY 0x04C11DB7L /* CRC16-Poly - GMAC: Little Endian */ +#define HASH_BITS 6 /* #bits in hash */ +#define SK_MC_BIT 0x01 + +/* Error numbers and messages. */ + +#define SKERR_ADDR_E001 (SK_ERRBASE_ADDR + 0) +#define SKERR_ADDR_E001MSG "Bad Flags." +#define SKERR_ADDR_E002 (SKERR_ADDR_E001 + 1) +#define SKERR_ADDR_E002MSG "New Error." + +/* typedefs *******************************************************************/ + +/* None. */ + +/* global variables ***********************************************************/ + +/* 64-bit hash values with all bits set. */ + +SK_U16 OnesHash[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF}; + +/* local variables ************************************************************/ + +#ifdef DEBUG +static int Next0[SK_MAX_MACS] = {0, 0}; +#endif /* DEBUG */ + +/* functions ******************************************************************/ + +/****************************************************************************** + * + * SkAddrInit - initialize data, set state to init + * + * Description: + * + * SK_INIT_DATA + * ============ + * + * This routine clears the multicast tables and resets promiscuous mode. + * Some entries are reserved for the "logical MAC address", the + * SK-RLMT multicast address, and the BPDU multicast address. + * + * + * SK_INIT_IO + * ========== + * + * All permanent MAC addresses are read from EPROM. + * If the current MAC addresses are not already set in software, + * they are set to the values of the permanent addresses. + * The current addresses are written to the corresponding MAC. + * + * + * SK_INIT_RUN + * =========== + * + * Nothing. + * + * Context: + * init, pageable + * + * Returns: + * SK_ADDR_SUCCESS + */ +int SkAddrInit( +SK_AC *pAC, /* the adapter context */ +SK_IOC IoC, /* I/O context */ +int Level) /* initialization level */ +{ + int j; + SK_U32 i; + SK_U8 *InAddr; + SK_U16 *OutAddr; + SK_ADDR_PORT *pAPort; + + switch (Level) { + case SK_INIT_DATA: + SK_MEMSET((char *) &pAC->Addr, 0, sizeof(SK_ADDR)); + + for (i = 0; i < SK_MAX_MACS; i++) { + pAPort = &pAC->Addr.Port[i]; + pAPort->PromMode = SK_PROM_MODE_NONE; + + pAPort->FirstExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT; + pAPort->FirstExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV; + pAPort->NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT; + pAPort->NextExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV; + } +#ifdef xDEBUG + for (i = 0; i < SK_MAX_MACS; i++) { + if (pAC->Addr.Port[i].NextExactMatchRlmt < + SK_ADDR_FIRST_MATCH_RLMT) { + Next0[i] |= 4; + } + } +#endif /* DEBUG */ + /* pAC->Addr.InitDone = SK_INIT_DATA; */ + break; + + case SK_INIT_IO: + for (i = 0; i < SK_MAX_NETS; i++) { + pAC->Addr.Net[i].ActivePort = pAC->Rlmt.Net[i].ActivePort; + } +#ifdef xDEBUG + for (i = 0; i < SK_MAX_MACS; i++) { + if (pAC->Addr.Port[i].NextExactMatchRlmt < + SK_ADDR_FIRST_MATCH_RLMT) { + Next0[i] |= 8; + } + } +#endif /* DEBUG */ + + /* Read permanent logical MAC address from Control Register File. */ + for (j = 0; j < SK_MAC_ADDR_LEN; j++) { + InAddr = (SK_U8 *) &pAC->Addr.Net[0].PermanentMacAddress.a[j]; + SK_IN8(IoC, B2_MAC_1 + j, InAddr); + } + + if (!pAC->Addr.Net[0].CurrentMacAddressSet) { + /* Set the current logical MAC address to the permanent one. */ + pAC->Addr.Net[0].CurrentMacAddress = + pAC->Addr.Net[0].PermanentMacAddress; + pAC->Addr.Net[0].CurrentMacAddressSet = SK_TRUE; + } + + /* Set the current logical MAC address. */ + pAC->Addr.Port[pAC->Addr.Net[0].ActivePort].Exact[0] = + pAC->Addr.Net[0].CurrentMacAddress; +#if SK_MAX_NETS > 1 + /* Set logical MAC address for net 2 to (log | 3). */ + if (!pAC->Addr.Net[1].CurrentMacAddressSet) { + pAC->Addr.Net[1].PermanentMacAddress = + pAC->Addr.Net[0].PermanentMacAddress; + pAC->Addr.Net[1].PermanentMacAddress.a[5] |= 3; + /* Set the current logical MAC address to the permanent one. */ + pAC->Addr.Net[1].CurrentMacAddress = + pAC->Addr.Net[1].PermanentMacAddress; + pAC->Addr.Net[1].CurrentMacAddressSet = SK_TRUE; + } +#endif /* SK_MAX_NETS > 1 */ + +#ifdef DEBUG + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, + ("Permanent MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n", + i, + pAC->Addr.Net[i].PermanentMacAddress.a[0], + pAC->Addr.Net[i].PermanentMacAddress.a[1], + pAC->Addr.Net[i].PermanentMacAddress.a[2], + pAC->Addr.Net[i].PermanentMacAddress.a[3], + pAC->Addr.Net[i].PermanentMacAddress.a[4], + pAC->Addr.Net[i].PermanentMacAddress.a[5])) + + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, + ("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n", + i, + pAC->Addr.Net[i].CurrentMacAddress.a[0], + pAC->Addr.Net[i].CurrentMacAddress.a[1], + pAC->Addr.Net[i].CurrentMacAddress.a[2], + pAC->Addr.Net[i].CurrentMacAddress.a[3], + pAC->Addr.Net[i].CurrentMacAddress.a[4], + pAC->Addr.Net[i].CurrentMacAddress.a[5])) + } +#endif /* DEBUG */ + + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + pAPort = &pAC->Addr.Port[i]; + + /* Read permanent port addresses from Control Register File. */ + for (j = 0; j < SK_MAC_ADDR_LEN; j++) { + InAddr = (SK_U8 *) &pAPort->PermanentMacAddress.a[j]; + SK_IN8(IoC, B2_MAC_2 + 8 * i + j, InAddr); + } + + if (!pAPort->CurrentMacAddressSet) { + /* + * Set the current and previous physical MAC address + * of this port to its permanent MAC address. + */ + pAPort->CurrentMacAddress = pAPort->PermanentMacAddress; + pAPort->PreviousMacAddress = pAPort->PermanentMacAddress; + pAPort->CurrentMacAddressSet = SK_TRUE; + } + + /* Set port's current physical MAC address. */ + OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0]; + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + XM_OUTADDR(IoC, i, XM_SA, OutAddr); + } + else { + GM_OUTADDR(IoC, i, GM_SRC_ADDR_1L, OutAddr); + } +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, + ("SkAddrInit: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAPort->PermanentMacAddress.a[0], + pAPort->PermanentMacAddress.a[1], + pAPort->PermanentMacAddress.a[2], + pAPort->PermanentMacAddress.a[3], + pAPort->PermanentMacAddress.a[4], + pAPort->PermanentMacAddress.a[5])) + + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT, + ("SkAddrInit: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAPort->CurrentMacAddress.a[0], + pAPort->CurrentMacAddress.a[1], + pAPort->CurrentMacAddress.a[2], + pAPort->CurrentMacAddress.a[3], + pAPort->CurrentMacAddress.a[4], + pAPort->CurrentMacAddress.a[5])) +#endif /* DEBUG */ + } + /* pAC->Addr.InitDone = SK_INIT_IO; */ + break; + + case SK_INIT_RUN: +#ifdef xDEBUG + for (i = 0; i < SK_MAX_MACS; i++) { + if (pAC->Addr.Port[i].NextExactMatchRlmt < + SK_ADDR_FIRST_MATCH_RLMT) { + Next0[i] |= 16; + } + } +#endif /* DEBUG */ + + /* pAC->Addr.InitDone = SK_INIT_RUN; */ + break; + + default: /* error */ + break; + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrInit */ + + +/****************************************************************************** + * + * SkAddrMcClear - clear the multicast table + * + * Description: + * This routine clears the multicast table. + * + * If not suppressed by Flag SK_MC_SW_ONLY, the hardware is updated + * immediately. + * + * It calls either SkAddrXmacMcClear or SkAddrGmacMcClear, according + * to the adapter in use. The real work is done there. + * + * Context: + * runtime, pageable + * may be called starting with SK_INIT_DATA with flag SK_MC_SW_ONLY + * may be called after SK_INIT_IO without limitation + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrMcClear( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Index of affected port */ +int Flags) /* permanent/non-perm, sw-only */ +{ + int ReturnCode; + + if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + ReturnCode = SkAddrXmacMcClear(pAC, IoC, PortNumber, Flags); + } + else { + ReturnCode = SkAddrGmacMcClear(pAC, IoC, PortNumber, Flags); + } + + return (ReturnCode); + +} /* SkAddrMcClear */ + + +/****************************************************************************** + * + * SkAddrXmacMcClear - clear the multicast table + * + * Description: + * This routine clears the multicast table + * (either entry 2 or entries 3-16 and InexactFilter) of the given port. + * If not suppressed by Flag SK_MC_SW_ONLY, the hardware is updated + * immediately. + * + * Context: + * runtime, pageable + * may be called starting with SK_INIT_DATA with flag SK_MC_SW_ONLY + * may be called after SK_INIT_IO without limitation + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrXmacMcClear( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Index of affected port */ +int Flags) /* permanent/non-perm, sw-only */ +{ + int i; + + if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */ + + /* Clear RLMT multicast addresses. */ + pAC->Addr.Port[PortNumber].NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT; + } + else { /* not permanent => DRV */ + + /* Clear InexactFilter */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0; + } + + /* Clear DRV multicast addresses. */ + + pAC->Addr.Port[PortNumber].NextExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV; + } + + if (!(Flags & SK_MC_SW_ONLY)) { + (void) SkAddrXmacMcUpdate(pAC, IoC, PortNumber); + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrXmacMcClear */ + + +/****************************************************************************** + * + * SkAddrGmacMcClear - clear the multicast table + * + * Description: + * This routine clears the multicast hashing table (InexactFilter) + * (either the RLMT or the driver bits) of the given port. + * + * If not suppressed by Flag SK_MC_SW_ONLY, the hardware is updated + * immediately. + * + * Context: + * runtime, pageable + * may be called starting with SK_INIT_DATA with flag SK_MC_SW_ONLY + * may be called after SK_INIT_IO without limitation + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrGmacMcClear( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Index of affected port */ +int Flags) /* permanent/non-perm, sw-only */ +{ + int i; + +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("GMAC InexactFilter (not cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[1], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[2], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[3], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])) +#endif /* DEBUG */ + + /* Clear InexactFilter */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0; + } + + if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */ + + /* Copy DRV bits to InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |= + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i]; + + /* Clear InexactRlmtFilter. */ + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i] = 0; + + } + } + else { /* not permanent => DRV */ + + /* Copy RLMT bits to InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |= + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i]; + + /* Clear InexactDrvFilter. */ + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i] = 0; + } + } + +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("GMAC InexactFilter (cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[1], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[2], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[3], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6], + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7])) +#endif /* DEBUG */ + + if (!(Flags & SK_MC_SW_ONLY)) { + (void) SkAddrGmacMcUpdate(pAC, IoC, PortNumber); + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrGmacMcClear */ + +#ifndef SK_ADDR_CHEAT + +/****************************************************************************** + * + * SkXmacMcHash - hash multicast address + * + * Description: + * This routine computes the hash value for a multicast address. + * A CRC32 algorithm is used. + * + * Notes: + * The code was adapted from the XaQti data sheet. + * + * Context: + * runtime, pageable + * + * Returns: + * Hash value of multicast address. + */ +SK_U32 SkXmacMcHash( +unsigned char *pMc) /* Multicast address */ +{ + SK_U32 Idx; + SK_U32 Bit; + SK_U32 Data; + SK_U32 Crc; + + Crc = 0xFFFFFFFFUL; + for (Idx = 0; Idx < SK_MAC_ADDR_LEN; Idx++) { + Data = *pMc++; + for (Bit = 0; Bit < 8; Bit++, Data >>= 1) { + Crc = (Crc >> 1) ^ (((Crc ^ Data) & 1) ? XMAC_POLY : 0); + } + } + + return (Crc & ((1 << HASH_BITS) - 1)); + +} /* SkXmacMcHash */ + + +/****************************************************************************** + * + * SkGmacMcHash - hash multicast address + * + * Description: + * This routine computes the hash value for a multicast address. + * A CRC16 algorithm is used. + * + * Notes: + * + * + * Context: + * runtime, pageable + * + * Returns: + * Hash value of multicast address. + */ +SK_U32 SkGmacMcHash( +unsigned char *pMc) /* Multicast address */ +{ + SK_U32 Data; + SK_U32 TmpData; + SK_U32 Crc; + int Byte; + int Bit; + + Crc = 0xFFFFFFFFUL; + for (Byte = 0; Byte < 6; Byte++) { + /* Get next byte. */ + Data = (SK_U32) pMc[Byte]; + + /* Change bit order in byte. */ + TmpData = Data; + for (Bit = 0; Bit < 8; Bit++) { + if (TmpData & 1L) { + Data |= 1L << (7 - Bit); + } + else { + Data &= ~(1L << (7 - Bit)); + } + TmpData >>= 1; + } + + Crc ^= (Data << 24); + for (Bit = 0; Bit < 8; Bit++) { + if (Crc & 0x80000000) { + Crc = (Crc << 1) ^ GMAC_POLY; + } + else { + Crc <<= 1; + } + } + } + + return (Crc & ((1 << HASH_BITS) - 1)); + +} /* SkGmacMcHash */ + +#endif /* not SK_ADDR_CHEAT */ + +/****************************************************************************** + * + * SkAddrMcAdd - add a multicast address to a port + * + * Description: + * This routine enables reception for a given address on the given port. + * + * It calls either SkAddrXmacMcAdd or SkAddrGmacMcAdd, according to the + * adapter in use. The real work is done there. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_DATA + * + * Returns: + * SK_MC_FILTERING_EXACT + * SK_MC_FILTERING_INEXACT + * SK_MC_ILLEGAL_ADDRESS + * SK_MC_ILLEGAL_PORT + * SK_MC_RLMT_OVERFLOW + */ +int SkAddrMcAdd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Port Number */ +SK_MAC_ADDR *pMc, /* multicast address to be added */ +int Flags) /* permanent/non-permanent */ +{ + int ReturnCode; + + if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + ReturnCode = SkAddrXmacMcAdd(pAC, IoC, PortNumber, pMc, Flags); + } + else { + ReturnCode = SkAddrGmacMcAdd(pAC, IoC, PortNumber, pMc, Flags); + } + + return (ReturnCode); + +} /* SkAddrMcAdd */ + + +/****************************************************************************** + * + * SkAddrXmacMcAdd - add a multicast address to a port + * + * Description: + * This routine enables reception for a given address on the given port. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * The multicast bit is only checked if there are no free exact match + * entries. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_DATA + * + * Returns: + * SK_MC_FILTERING_EXACT + * SK_MC_FILTERING_INEXACT + * SK_MC_ILLEGAL_ADDRESS + * SK_MC_RLMT_OVERFLOW + */ +int SkAddrXmacMcAdd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Port Number */ +SK_MAC_ADDR *pMc, /* multicast address to be added */ +int Flags) /* permanent/non-permanent */ +{ + int i; + SK_U8 Inexact; +#ifndef SK_ADDR_CHEAT + SK_U32 HashBit; +#endif /* !defined(SK_ADDR_CHEAT) */ + + if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */ +#ifdef xDEBUG + if (pAC->Addr.Port[PortNumber].NextExactMatchRlmt < + SK_ADDR_FIRST_MATCH_RLMT) { + Next0[PortNumber] |= 1; + return (SK_MC_RLMT_OVERFLOW); + } +#endif /* DEBUG */ + + if (pAC->Addr.Port[PortNumber].NextExactMatchRlmt > + SK_ADDR_LAST_MATCH_RLMT) { + return (SK_MC_RLMT_OVERFLOW); + } + + /* Set a RLMT multicast address. */ + + pAC->Addr.Port[PortNumber].Exact[ + pAC->Addr.Port[PortNumber].NextExactMatchRlmt++] = *pMc; + + return (SK_MC_FILTERING_EXACT); + } + +#ifdef xDEBUG + if (pAC->Addr.Port[PortNumber].NextExactMatchDrv < + SK_ADDR_FIRST_MATCH_DRV) { + Next0[PortNumber] |= 2; + return (SK_MC_RLMT_OVERFLOW); + } +#endif /* DEBUG */ + + if (pAC->Addr.Port[PortNumber].NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) { + + /* Set exact match entry. */ + pAC->Addr.Port[PortNumber].Exact[ + pAC->Addr.Port[PortNumber].NextExactMatchDrv++] = *pMc; + + /* Clear InexactFilter */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0; + } + } + else { + if (!(pMc->a[0] & SK_MC_BIT)) { + /* Hashing only possible with multicast addresses. */ + return (SK_MC_ILLEGAL_ADDRESS); + } +#ifndef SK_ADDR_CHEAT + /* Compute hash value of address. */ + HashBit = 63 - SkXmacMcHash(&pMc->a[0]); + + /* Add bit to InexactFilter. */ + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[HashBit / 8] |= + 1 << (HashBit % 8); +#else /* SK_ADDR_CHEAT */ + /* Set all bits in InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF; + } +#endif /* SK_ADDR_CHEAT */ + } + + for (Inexact = 0, i = 0; i < 8; i++) { + Inexact |= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i]; + } + + if (Inexact == 0 && pAC->Addr.Port[PortNumber].PromMode == 0) { + return (SK_MC_FILTERING_EXACT); + } + else { + return (SK_MC_FILTERING_INEXACT); + } + +} /* SkAddrXmacMcAdd */ + + +/****************************************************************************** + * + * SkAddrGmacMcAdd - add a multicast address to a port + * + * Description: + * This routine enables reception for a given address on the given port. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_DATA + * + * Returns: + * SK_MC_FILTERING_INEXACT + * SK_MC_ILLEGAL_ADDRESS + */ +int SkAddrGmacMcAdd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Port Number */ +SK_MAC_ADDR *pMc, /* multicast address to be added */ +int Flags) /* permanent/non-permanent */ +{ + int i; +#ifndef SK_ADDR_CHEAT + SK_U32 HashBit; +#endif /* !defined(SK_ADDR_CHEAT) */ + + if (!(pMc->a[0] & SK_MC_BIT)) { + /* Hashing only possible with multicast addresses. */ + return (SK_MC_ILLEGAL_ADDRESS); + } + +#ifndef SK_ADDR_CHEAT + + /* Compute hash value of address. */ + HashBit = SkGmacMcHash(&pMc->a[0]); + + if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */ + + /* Add bit to InexactRlmtFilter. */ + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[HashBit / 8] |= + 1 << (HashBit % 8); + + /* Copy bit to InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |= + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i]; + } +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("GMAC InexactRlmtFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[0], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[1], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[2], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[3], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[4], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[5], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[6], + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7])) +#endif /* DEBUG */ + } + else { /* not permanent => DRV */ + + /* Add bit to InexactDrvFilter. */ + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[HashBit / 8] |= + 1 << (HashBit % 8); + + /* Copy bit to InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |= + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i]; + } +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("GMAC InexactDrvFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[0], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[1], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[2], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[3], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[4], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[5], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[6], + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7])) +#endif /* DEBUG */ + } + +#else /* SK_ADDR_CHEAT */ + + /* Set all bits in InexactFilter. */ + for (i = 0; i < 8; i++) { + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF; + } +#endif /* SK_ADDR_CHEAT */ + + return (SK_MC_FILTERING_INEXACT); + +} /* SkAddrGmacMcAdd */ + + +/****************************************************************************** + * + * SkAddrMcUpdate - update the HW MC address table and set the MAC address + * + * Description: + * This routine enables reception of the addresses contained in a local + * table for a given port. + * It also programs the port's current physical MAC address. + * + * It calls either SkAddrXmacMcUpdate or SkAddrGmacMcUpdate, according + * to the adapter in use. The real work is done there. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_MC_FILTERING_EXACT + * SK_MC_FILTERING_INEXACT + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrMcUpdate( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber) /* Port Number */ +{ + int ReturnCode; + + if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + ReturnCode = SkAddrXmacMcUpdate(pAC, IoC, PortNumber); + } + else { + ReturnCode = SkAddrGmacMcUpdate(pAC, IoC, PortNumber); + } + + return (ReturnCode); + +} /* SkAddrMcUpdate */ + + +/****************************************************************************** + * + * SkAddrXmacMcUpdate - update the HW MC address table and set the MAC address + * + * Description: + * This routine enables reception of the addresses contained in a local + * table for a given port. + * It also programs the port's current physical MAC address. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_MC_FILTERING_EXACT + * SK_MC_FILTERING_INEXACT + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrXmacMcUpdate( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber) /* Port Number */ +{ + SK_U32 i; + SK_U8 Inexact; + SK_U16 *OutAddr; + SK_ADDR_PORT *pAPort; + + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber)) + + pAPort = &pAC->Addr.Port[PortNumber]; + +#ifdef DEBUG + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])) +#endif /* DEBUG */ + + /* Start with 0 to also program the logical MAC address. */ + for (i = 0; i < pAPort->NextExactMatchRlmt; i++) { + /* Set exact match address i on XMAC */ + OutAddr = (SK_U16 *) &pAPort->Exact[i].a[0]; + XM_OUTADDR(IoC, PortNumber, XM_EXM(i), OutAddr); + } + + /* Clear other permanent exact match addresses on XMAC */ + if (pAPort->NextExactMatchRlmt <= SK_ADDR_LAST_MATCH_RLMT) { + + SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchRlmt, + SK_ADDR_LAST_MATCH_RLMT); + } + + for (i = pAPort->FirstExactMatchDrv; i < pAPort->NextExactMatchDrv; i++) { + OutAddr = (SK_U16 *) &pAPort->Exact[i].a[0]; + XM_OUTADDR(IoC, PortNumber, XM_EXM(i), OutAddr); + } + + /* Clear other non-permanent exact match addresses on XMAC */ + if (pAPort->NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) { + + SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchDrv, + SK_ADDR_LAST_MATCH_DRV); + } + + for (Inexact = 0, i = 0; i < 8; i++) { + Inexact |= pAPort->InexactFilter.Bytes[i]; + } + + if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) { + + /* Set all bits in 64-bit hash register. */ + XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + else if (Inexact != 0) { + + /* Set 64-bit hash register to InexactFilter. */ + XM_OUTHASH(IoC, PortNumber, XM_HSM, &pAPort->InexactFilter.Bytes[0]); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + else { + /* Disable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_FALSE); + } + + if (pAPort->PromMode != SK_PROM_MODE_NONE) { + (void) SkAddrXmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode); + } + + /* Set port's current physical MAC address. */ + OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0]; + + XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr); + +#ifdef xDEBUG + for (i = 0; i < pAPort->NextExactMatchRlmt; i++) { + SK_U8 InAddr8[6]; + SK_U16 *InAddr; + + /* Get exact match address i from port PortNumber. */ + InAddr = (SK_U16 *) &InAddr8[0]; + + XM_INADDR(IoC, PortNumber, XM_EXM(i), InAddr); + + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrXmacMcUpdate: MC address %d on Port %u: ", + "%02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x\n", + i, + PortNumber, + InAddr8[0], + InAddr8[1], + InAddr8[2], + InAddr8[3], + InAddr8[4], + InAddr8[5], + pAPort->Exact[i].a[0], + pAPort->Exact[i].a[1], + pAPort->Exact[i].a[2], + pAPort->Exact[i].a[3], + pAPort->Exact[i].a[4], + pAPort->Exact[i].a[5])) + } +#endif /* DEBUG */ + + /* Determine return value. */ + if (Inexact == 0 && pAPort->PromMode == 0) { + return (SK_MC_FILTERING_EXACT); + } + else { + return (SK_MC_FILTERING_INEXACT); + } + +} /* SkAddrXmacMcUpdate */ + + +/****************************************************************************** + * + * SkAddrGmacMcUpdate - update the HW MC address table and set the MAC address + * + * Description: + * This routine enables reception of the addresses contained in a local + * table for a given port. + * It also programs the port's current physical MAC address. + * + * Notes: + * The return code is only valid for SK_PROM_MODE_NONE. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_MC_FILTERING_EXACT + * SK_MC_FILTERING_INEXACT + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrGmacMcUpdate( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber) /* Port Number */ +{ + SK_U32 i; + SK_U8 Inexact; + SK_U16 *OutAddr; + SK_ADDR_PORT *pAPort; + + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber)) + + pAPort = &pAC->Addr.Port[PortNumber]; + +#ifdef DEBUG + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber])) +#endif /* DEBUG */ + + for (Inexact = 0, i = 0; i < 8; i++) { + Inexact |= pAPort->InexactFilter.Bytes[i]; + } + + /* Set 64-bit hash register to InexactFilter. */ + GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, + &pAPort->InexactFilter.Bytes[0]); + + if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) { + + /* Set all bits in 64-bit hash register. */ + GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + else { + /* Enable Hashing. */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + + if (pAPort->PromMode != SK_PROM_MODE_NONE) { + (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode); + } + + /* Set port's current physical MAC address. */ + OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0]; + GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr); + + /* Set port's current logical MAC address. */ + OutAddr = (SK_U16 *) &pAPort->Exact[0].a[0]; + GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_2L, OutAddr); + +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrGmacMcUpdate: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAPort->Exact[0].a[0], + pAPort->Exact[0].a[1], + pAPort->Exact[0].a[2], + pAPort->Exact[0].a[3], + pAPort->Exact[0].a[4], + pAPort->Exact[0].a[5])) + + SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrGmacMcUpdate: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAPort->CurrentMacAddress.a[0], + pAPort->CurrentMacAddress.a[1], + pAPort->CurrentMacAddress.a[2], + pAPort->CurrentMacAddress.a[3], + pAPort->CurrentMacAddress.a[4], + pAPort->CurrentMacAddress.a[5])) +#endif /* DEBUG */ + + /* Determine return value. */ + if (Inexact == 0 && pAPort->PromMode == 0) { + return (SK_MC_FILTERING_EXACT); + } + else { + return (SK_MC_FILTERING_INEXACT); + } + +} /* SkAddrGmacMcUpdate */ + + +/****************************************************************************** + * + * SkAddrOverride - override a port's MAC address + * + * Description: + * This routine overrides the MAC address of one port. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_ADDR_SUCCESS if successful. + * SK_ADDR_DUPLICATE_ADDRESS if duplicate MAC address. + * SK_ADDR_MULTICAST_ADDRESS if multicast or broadcast address. + * SK_ADDR_TOO_EARLY if SK_INIT_IO was not executed before. + */ +int SkAddrOverride( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* Port Number */ +SK_MAC_ADDR *pNewAddr, /* new MAC address */ +int Flags) /* logical/physical MAC address */ +{ + SK_EVPARA Para; + SK_U32 NetNumber; + SK_U32 i; + SK_U16 *OutAddr; + + NetNumber = pAC->Rlmt.Port[PortNumber].Net->NetNumber; + + if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pNewAddr != NULL && (pNewAddr->a[0] & SK_MC_BIT) != 0) { + return (SK_ADDR_MULTICAST_ADDRESS); + } + + if (!pAC->Addr.Net[NetNumber].CurrentMacAddressSet) { + return (SK_ADDR_TOO_EARLY); + } + + if (Flags & SK_ADDR_SET_LOGICAL) { /* Activate logical MAC address. */ + /* Parameter *pNewAddr is ignored. */ + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + if (!pAC->Addr.Port[i].CurrentMacAddressSet) { + return (SK_ADDR_TOO_EARLY); + } + } + + /* Set PortNumber to number of net's active port. */ + PortNumber = pAC->Rlmt.Net[NetNumber]. + Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber; + + pAC->Addr.Port[PortNumber].Exact[0] = + pAC->Addr.Net[NetNumber].CurrentMacAddress; + + /* Write address to first exact match entry of active port. */ + (void) SkAddrMcUpdate(pAC, IoC, PortNumber); + } + else if (Flags & SK_ADDR_CLEAR_LOGICAL) { + /* Deactivate logical MAC address. */ + /* Parameter *pNewAddr is ignored. */ + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + if (!pAC->Addr.Port[i].CurrentMacAddressSet) { + return (SK_ADDR_TOO_EARLY); + } + } + + /* Set PortNumber to number of net's active port. */ + PortNumber = pAC->Rlmt.Net[NetNumber]. + Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber; + + for (i = 0; i < SK_MAC_ADDR_LEN; i++ ) { + pAC->Addr.Port[PortNumber].Exact[0].a[i] = 0; + } + + /* Write address to first exact match entry of active port. */ + (void) SkAddrMcUpdate(pAC, IoC, PortNumber); + } + else if (Flags & SK_ADDR_PHYSICAL_ADDRESS) { /* Physical MAC address. */ + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) { + return (SK_ADDR_DUPLICATE_ADDRESS); + } + + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + if (!pAC->Addr.Port[i].CurrentMacAddressSet) { + return (SK_ADDR_TOO_EARLY); + } + + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Port[i].CurrentMacAddress.a)) { + if (i == PortNumber) { + return (SK_ADDR_SUCCESS); + } + else { + return (SK_ADDR_DUPLICATE_ADDRESS); + } + } + } + + pAC->Addr.Port[PortNumber].PreviousMacAddress = + pAC->Addr.Port[PortNumber].CurrentMacAddress; + pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr; + + /* Change port's physical MAC address. */ + OutAddr = (SK_U16 *) pNewAddr; + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr); + } + else { + GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr); + } + + /* Report address change to RLMT. */ + Para.Para32[0] = PortNumber; + Para.Para32[0] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para); + } + else { /* Logical MAC address. */ + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) { + return (SK_ADDR_SUCCESS); + } + + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) { + if (!pAC->Addr.Port[i].CurrentMacAddressSet) { + return (SK_ADDR_TOO_EARLY); + } + + if (SK_ADDR_EQUAL(pNewAddr->a, + pAC->Addr.Port[i].CurrentMacAddress.a)) { + return (SK_ADDR_DUPLICATE_ADDRESS); + } + } + + /* + * In case that the physical and the logical MAC addresses are equal + * we must also change the physical MAC address here. + * In this case we have an adapter which initially was programmed with + * two identical MAC addresses. + */ + if (SK_ADDR_EQUAL(pAC->Addr.Port[PortNumber].CurrentMacAddress.a, + pAC->Addr.Port[PortNumber].Exact[0].a)) { + + pAC->Addr.Port[PortNumber].PreviousMacAddress = + pAC->Addr.Port[PortNumber].CurrentMacAddress; + pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr; + + /* Report address change to RLMT. */ + Para.Para32[0] = PortNumber; + Para.Para32[0] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para); + } + + /* Set PortNumber to number of net's active port. */ + PortNumber = pAC->Rlmt.Net[NetNumber]. + Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber; + + pAC->Addr.Net[NetNumber].CurrentMacAddress = *pNewAddr; + pAC->Addr.Port[PortNumber].Exact[0] = *pNewAddr; +#ifdef DEBUG + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrOverride: Permanent MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[0], + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[1], + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[2], + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3], + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4], + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5])) + + SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL, + ("SkAddrOverride: New logical MAC Address: %02X %02X %02X %02X %02X %02X\n", + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[0], + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[1], + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[2], + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[3], + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[4], + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5])) +#endif /* DEBUG */ + + /* Write address to first exact match entry of active port. */ + (void) SkAddrMcUpdate(pAC, IoC, PortNumber); + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrOverride */ + + +/****************************************************************************** + * + * SkAddrPromiscuousChange - set promiscuous mode for given port + * + * Description: + * This routine manages promiscuous mode: + * - none + * - all LLC frames + * - all MC frames + * + * It calls either SkAddrXmacPromiscuousChange or + * SkAddrGmacPromiscuousChange, according to the adapter in use. + * The real work is done there. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrPromiscuousChange( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* port whose promiscuous mode changes */ +int NewPromMode) /* new promiscuous mode */ +{ + int ReturnCode; + + if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + ReturnCode = SkAddrXmacPromiscuousChange(pAC, IoC, PortNumber, NewPromMode); + } + else { + ReturnCode = SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, NewPromMode); + } + + return (ReturnCode); + +} /* SkAddrPromiscuousChange */ + + +/****************************************************************************** + * + * SkAddrXmacPromiscuousChange - set promiscuous mode for given port + * + * Description: + * This routine manages promiscuous mode: + * - none + * - all LLC frames + * - all MC frames + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrXmacPromiscuousChange( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* port whose promiscuous mode changes */ +int NewPromMode) /* new promiscuous mode */ +{ + int i; + SK_BOOL InexactModeBit; + SK_U8 Inexact; + SK_U8 HwInexact; + SK_FILTER64 HwInexactFilter; + SK_U16 LoMode; /* Lower 16 bits of XMAC Mode Register. */ + int CurPromMode = SK_PROM_MODE_NONE; + + /* Read CurPromMode from Hardware. */ + XM_IN16(IoC, PortNumber, XM_MODE, &LoMode); + + if ((LoMode & XM_MD_ENA_PROM) != 0) { + /* Promiscuous mode! */ + CurPromMode |= SK_PROM_MODE_LLC; + } + + for (Inexact = 0xFF, i = 0; i < 8; i++) { + Inexact &= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i]; + } + if (Inexact == 0xFF) { + CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC); + } + else { + /* Get InexactModeBit (bit XM_MD_ENA_HASH in mode register) */ + XM_IN16(IoC, PortNumber, XM_MODE, &LoMode); + + InexactModeBit = (LoMode & XM_MD_ENA_HASH) != 0; + + /* Read 64-bit hash register from XMAC */ + XM_INHASH(IoC, PortNumber, XM_HSM, &HwInexactFilter.Bytes[0]); + + for (HwInexact = 0xFF, i = 0; i < 8; i++) { + HwInexact &= HwInexactFilter.Bytes[i]; + } + + if (InexactModeBit && (HwInexact == 0xFF)) { + CurPromMode |= SK_PROM_MODE_ALL_MC; + } + } + + pAC->Addr.Port[PortNumber].PromMode = NewPromMode; + + if (NewPromMode == CurPromMode) { + return (SK_ADDR_SUCCESS); + } + + if ((NewPromMode & SK_PROM_MODE_ALL_MC) && + !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC. */ + + /* Set all bits in 64-bit hash register. */ + XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + else if ((CurPromMode & SK_PROM_MODE_ALL_MC) && + !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm MC. */ + for (Inexact = 0, i = 0; i < 8; i++) { + Inexact |= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i]; + } + if (Inexact == 0) { + /* Disable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_FALSE); + } + else { + /* Set 64-bit hash register to InexactFilter. */ + XM_OUTHASH(IoC, PortNumber, XM_HSM, + &pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0]); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + } + + if ((NewPromMode & SK_PROM_MODE_LLC) && + !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */ + /* Set the MAC in Promiscuous Mode */ + SkMacPromiscMode(pAC, IoC, PortNumber, SK_TRUE); + } + else if ((CurPromMode & SK_PROM_MODE_LLC) && + !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC. */ + /* Clear Promiscuous Mode */ + SkMacPromiscMode(pAC, IoC, PortNumber, SK_FALSE); + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrXmacPromiscuousChange */ + + +/****************************************************************************** + * + * SkAddrGmacPromiscuousChange - set promiscuous mode for given port + * + * Description: + * This routine manages promiscuous mode: + * - none + * - all LLC frames + * - all MC frames + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrGmacPromiscuousChange( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 PortNumber, /* port whose promiscuous mode changes */ +int NewPromMode) /* new promiscuous mode */ +{ + SK_U16 ReceiveControl; /* GMAC Receive Control Register */ + int CurPromMode = SK_PROM_MODE_NONE; + + /* Read CurPromMode from Hardware. */ + GM_IN16(IoC, PortNumber, GM_RX_CTRL, &ReceiveControl); + + if ((ReceiveControl & (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA)) == 0) { + /* Promiscuous mode! */ + CurPromMode |= SK_PROM_MODE_LLC; + } + + if ((ReceiveControl & GM_RXCR_MCF_ENA) == 0) { + /* All Multicast mode! */ + CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC); + } + + pAC->Addr.Port[PortNumber].PromMode = NewPromMode; + + if (NewPromMode == CurPromMode) { + return (SK_ADDR_SUCCESS); + } + + if ((NewPromMode & SK_PROM_MODE_ALL_MC) && + !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC */ + + /* Set all bits in 64-bit hash register. */ + GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash); + + /* Enable Hashing */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + + if ((CurPromMode & SK_PROM_MODE_ALL_MC) && + !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm. MC */ + + /* Set 64-bit hash register to InexactFilter. */ + GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, + &pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0]); + + /* Enable Hashing. */ + SkMacHashing(pAC, IoC, PortNumber, SK_TRUE); + } + + if ((NewPromMode & SK_PROM_MODE_LLC) && + !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */ + + /* Set the MAC to Promiscuous Mode. */ + SkMacPromiscMode(pAC, IoC, PortNumber, SK_TRUE); + } + else if ((CurPromMode & SK_PROM_MODE_LLC) && + !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC */ + + /* Clear Promiscuous Mode. */ + SkMacPromiscMode(pAC, IoC, PortNumber, SK_FALSE); + } + + return (SK_ADDR_SUCCESS); + +} /* SkAddrGmacPromiscuousChange */ + + +/****************************************************************************** + * + * SkAddrSwap - swap address info + * + * Description: + * This routine swaps address info of two ports. + * + * Context: + * runtime, pageable + * may be called after SK_INIT_IO + * + * Returns: + * SK_ADDR_SUCCESS + * SK_ADDR_ILLEGAL_PORT + */ +int SkAddrSwap( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +SK_U32 FromPortNumber, /* Port1 Index */ +SK_U32 ToPortNumber) /* Port2 Index */ +{ + int i; + SK_U8 Byte; + SK_MAC_ADDR MacAddr; + SK_U32 DWord; + + if (FromPortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (ToPortNumber >= (SK_U32) pAC->GIni.GIMacsFound) { + return (SK_ADDR_ILLEGAL_PORT); + } + + if (pAC->Rlmt.Port[FromPortNumber].Net != pAC->Rlmt.Port[ToPortNumber].Net) { + return (SK_ADDR_ILLEGAL_PORT); + } + + /* + * Swap: + * - Exact Match Entries (GEnesis and Yukon) + * Yukon uses first entry for the logical MAC + * address (stored in the second GMAC register). + * - FirstExactMatchRlmt (GEnesis only) + * - NextExactMatchRlmt (GEnesis only) + * - FirstExactMatchDrv (GEnesis only) + * - NextExactMatchDrv (GEnesis only) + * - 64-bit filter (InexactFilter) + * - Promiscuous Mode + * of ports. + */ + + for (i = 0; i < SK_ADDR_EXACT_MATCHES; i++) { + MacAddr = pAC->Addr.Port[FromPortNumber].Exact[i]; + pAC->Addr.Port[FromPortNumber].Exact[i] = + pAC->Addr.Port[ToPortNumber].Exact[i]; + pAC->Addr.Port[ToPortNumber].Exact[i] = MacAddr; + } + + for (i = 0; i < 8; i++) { + Byte = pAC->Addr.Port[FromPortNumber].InexactFilter.Bytes[i]; + pAC->Addr.Port[FromPortNumber].InexactFilter.Bytes[i] = + pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i]; + pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i] = Byte; + } + + i = pAC->Addr.Port[FromPortNumber].PromMode; + pAC->Addr.Port[FromPortNumber].PromMode = pAC->Addr.Port[ToPortNumber].PromMode; + pAC->Addr.Port[ToPortNumber].PromMode = i; + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt; + pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt = + pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt; + pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt = DWord; + + DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt; + pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt = + pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt; + pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt = DWord; + + DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv; + pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv = + pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv; + pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv = DWord; + + DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchDrv; + pAC->Addr.Port[FromPortNumber].NextExactMatchDrv = + pAC->Addr.Port[ToPortNumber].NextExactMatchDrv; + pAC->Addr.Port[ToPortNumber].NextExactMatchDrv = DWord; + } + + /* CAUTION: Solution works if only ports of one adapter are in use. */ + for (i = 0; (SK_U32) i < pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber]. + Net->NetNumber].NumPorts; i++) { + if (pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber].Net->NetNumber]. + Port[i]->PortNumber == ToPortNumber) { + pAC->Addr.Net[pAC->Rlmt.Port[ToPortNumber].Net->NetNumber]. + ActivePort = i; + /* 20001207 RA: Was "ToPortNumber;". */ + } + } + + (void) SkAddrMcUpdate(pAC, IoC, FromPortNumber); + (void) SkAddrMcUpdate(pAC, IoC, ToPortNumber); + + return (SK_ADDR_SUCCESS); + +} /* SkAddrSwap */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skcsum.c b/drivers/sk98lin/skcsum.c new file mode 100644 index 000000000..a5dc57258 --- /dev/null +++ b/drivers/sk98lin/skcsum.c @@ -0,0 +1,929 @@ +/****************************************************************************** + * + * Name: skcsum.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.10 $ + * Date: $Date: 2002/04/11 10:02:04 $ + * Purpose: Store/verify Internet checksum in send/receive packets. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skcsum.c,v $ + * Revision 1.10 2002/04/11 10:02:04 rwahl + * Fix in SkCsGetSendInfo(): + * - function did not return ProtocolFlags in every case. + * - pseudo header csum calculated wrong for big endian. + * + * Revision 1.9 2001/06/13 07:42:08 gklug + * fix: NetNumber was wrong in CLEAR_STAT event + * add: check for good NetNumber in Clear STAT + * + * Revision 1.8 2001/02/06 11:15:36 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.7 2000/06/29 13:17:05 rassmann + * Corrected reception of a packet with UDP checksum == 0 (which means there + * is no UDP checksum). + * + * Revision 1.6 2000/02/21 12:35:10 cgoos + * Fixed license header comment. + * + * Revision 1.5 2000/02/21 11:05:19 cgoos + * Merged changes back to common source. + * Fixed rx path for BIG ENDIAN architecture. + * + * Revision 1.1 1999/07/26 15:28:12 mkarl + * added return SKCS_STATUS_IP_CSUM_ERROR_UDP and + * SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester + * changed from common source to windows specific source + * therefore restarting with v1.0 + * + * Revision 1.3 1999/05/10 08:39:33 mkarl + * prevent overflows in SKCS_HTON16 + * fixed a bug in pseudo header checksum calculation + * added some comments + * + * Revision 1.2 1998/10/22 11:53:28 swolf + * Now using SK_DBG_MSG. + * + * Revision 1.1 1998/09/01 15:35:41 swolf + * initial revision + * + * 13-May-1998 sw Created. + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#ifdef SK_USE_CSUM /* Check if CSUM is to be used. */ + +#ifndef lint +static const char SysKonnectFileId[] = "@(#)" + "$Id: skcsum.c,v 1.10 2002/04/11 10:02:04 rwahl Exp $" + " (C) SysKonnect."; +#endif /* !lint */ + +/****************************************************************************** + * + * Description: + * + * This is the "GEnesis" common module "CSUM". + * + * This module contains the code necessary to calculate, store, and verify the + * Internet Checksum of IP, TCP, and UDP frames. + * + * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon" + * and is the code name of this SysKonnect project. + * + * Compilation Options: + * + * SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an + * empty module. + * + * SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id + * definitions. In this case, all SKCS_PROTO_xxx definitions must be made + * external. + * + * SKCS_OVERWRITE_STATUS - Define to overwrite the default return status + * definitions. In this case, all SKCS_STATUS_xxx definitions must be made + * external. + * + * Include File Hierarchy: + * + * "h/skdrv1st.h" + * "h/skcsum.h" + * "h/sktypes.h" + * "h/skqueue.h" + * "h/skdrv2nd.h" + * + ******************************************************************************/ + +#include "h/skdrv1st.h" +#include "h/skcsum.h" +#include "h/skdrv2nd.h" + +/* defines ********************************************************************/ + +/* The size of an Ethernet MAC header. */ +#define SKCS_ETHERNET_MAC_HEADER_SIZE (6+6+2) + +/* The size of the used topology's MAC header. */ +#define SKCS_MAC_HEADER_SIZE SKCS_ETHERNET_MAC_HEADER_SIZE + +/* The size of the IP header without any option fields. */ +#define SKCS_IP_HEADER_SIZE 20 + +/* + * Field offsets within the IP header. + */ + +/* "Internet Header Version" and "Length". */ +#define SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH 0 + +/* "Total Length". */ +#define SKCS_OFS_IP_TOTAL_LENGTH 2 + +/* "Flags" "Fragment Offset". */ +#define SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET 6 + +/* "Next Level Protocol" identifier. */ +#define SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL 9 + +/* Source IP address. */ +#define SKCS_OFS_IP_SOURCE_ADDRESS 12 + +/* Destination IP address. */ +#define SKCS_OFS_IP_DESTINATION_ADDRESS 16 + + +/* + * Field offsets within the UDP header. + */ + +/* UDP checksum. */ +#define SKCS_OFS_UDP_CHECKSUM 6 + +/* IP "Next Level Protocol" identifiers (see RFC 790). */ +#define SKCS_PROTO_ID_TCP 6 /* Transport Control Protocol */ +#define SKCS_PROTO_ID_UDP 17 /* User Datagram Protocol */ + +/* IP "Don't Fragment" bit. */ +#define SKCS_IP_DONT_FRAGMENT SKCS_HTON16(0x4000) + +/* Add a byte offset to a pointer. */ +#define SKCS_IDX(pPtr, Ofs) ((void *) ((char *) (pPtr) + (Ofs))) + +/* + * Macros that convert host to network representation and vice versa, i.e. + * little/big endian conversion on little endian machines only. + */ +#ifdef SK_LITTLE_ENDIAN +#define SKCS_HTON16(Val16) (((unsigned) (Val16) >> 8) | (((Val16) & 0xFF) << 8)) +#endif /* SK_LITTLE_ENDIAN */ +#ifdef SK_BIG_ENDIAN +#define SKCS_HTON16(Val16) (Val16) +#endif /* SK_BIG_ENDIAN */ +#define SKCS_NTOH16(Val16) SKCS_HTON16(Val16) + +/* typedefs *******************************************************************/ + +/* function prototypes ********************************************************/ + +/****************************************************************************** + * + * SkCsGetSendInfo - get checksum information for a send packet + * + * Description: + * Get all checksum information necessary to send a TCP or UDP packet. The + * function checks the IP header passed to it. If the high-level protocol + * is either TCP or UDP the pseudo header checksum is calculated and + * returned. + * + * The function returns the total length of the IP header (including any + * IP option fields), which is the same as the start offset of the IP data + * which in turn is the start offset of the TCP or UDP header. + * + * The function also returns the TCP or UDP pseudo header checksum, which + * should be used as the start value for the hardware checksum calculation. + * (Note that any actual pseudo header checksum can never calculate to + * zero.) + * + * Note: + * There is a bug in the ASIC which may lead to wrong checksums. + * + * Arguments: + * pAc - A pointer to the adapter context struct. + * + * pIpHeader - Pointer to IP header. Must be at least the IP header *not* + * including any option fields, i.e. at least 20 bytes. + * + * Note: This pointer will be used to address 8-, 16-, and 32-bit + * variables with the respective alignment offsets relative to the pointer. + * Thus, the pointer should point to a 32-bit aligned address. If the + * target system cannot address 32-bit variables on non 32-bit aligned + * addresses, then the pointer *must* point to a 32-bit aligned address. + * + * pPacketInfo - A pointer to the packet information structure for this + * packet. Before calling this SkCsGetSendInfo(), the following field must + * be initialized: + * + * ProtocolFlags - Initialize with any combination of + * SKCS_PROTO_XXX bit flags. SkCsGetSendInfo() will only work on + * the protocols specified here. Any protocol(s) not specified + * here will be ignored. + * + * Note: Only one checksum can be calculated in hardware. Thus, if + * SKCS_PROTO_IP is specified in the 'ProtocolFlags', + * SkCsGetSendInfo() must calculate the IP header checksum in + * software. It might be a better idea to have the calling + * protocol stack calculate the IP header checksum. + * + * Returns: N/A + * On return, the following fields in 'pPacketInfo' may or may not have + * been filled with information, depending on the protocol(s) found in the + * packet: + * + * ProtocolFlags - Returns the SKCS_PROTO_XXX bit flags of the protocol(s) + * that were both requested by the caller and actually found in the packet. + * Protocol(s) not specified by the caller and/or not found in the packet + * will have their respective SKCS_PROTO_XXX bit flags reset. + * + * Note: For IP fragments, TCP and UDP packet information is ignored. + * + * IpHeaderLength - The total length in bytes of the complete IP header + * including any option fields is returned here. This is the start offset + * of the IP data, i.e. the TCP or UDP header if present. + * + * IpHeaderChecksum - If IP has been specified in the 'ProtocolFlags', the + * 16-bit Internet Checksum of the IP header is returned here. This value + * is to be stored into the packet's 'IP Header Checksum' field. + * + * PseudoHeaderChecksum - If this is a TCP or UDP packet and if TCP or UDP + * has been specified in the 'ProtocolFlags', the 16-bit Internet Checksum + * of the TCP or UDP pseudo header is returned here. + */ +#if 0 +void SkCsGetSendInfo( +SK_AC *pAc, /* Adapter context struct. */ +void *pIpHeader, /* IP header. */ +SKCS_PACKET_INFO *pPacketInfo, /* Packet information struct. */ +int NetNumber) /* Net number */ +{ + /* Internet Header Version found in IP header. */ + unsigned InternetHeaderVersion; + + /* Length of the IP header as found in IP header. */ + unsigned IpHeaderLength; + + /* Bit field specifiying the desired/found protocols. */ + unsigned ProtocolFlags; + + /* Next level protocol identifier found in IP header. */ + unsigned NextLevelProtocol; + + /* Length of IP data portion. */ + unsigned IpDataLength; + + /* TCP/UDP pseudo header checksum. */ + unsigned long PseudoHeaderChecksum; + + /* Pointer to next level protocol statistics structure. */ + SKCS_PROTO_STATS *NextLevelProtoStats; + + /* Temporary variable. */ + unsigned Tmp; + + Tmp = *(SK_U8 *) + SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH); + + /* Get the Internet Header Version (IHV). */ + /* Note: The IHV is stored in the upper four bits. */ + + InternetHeaderVersion = Tmp >> 4; + + /* Check the Internet Header Version. */ + /* Note: We currently only support IP version 4. */ + + if (InternetHeaderVersion != 4) { /* IPv4? */ + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX, + ("Tx: Unknown Internet Header Version %u.\n", + InternetHeaderVersion)); + pPacketInfo->ProtocolFlags = 0; + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++; + return; + } + + /* Get the IP header length (IHL). */ + /* + * Note: The IHL is stored in the lower four bits as the number of + * 4-byte words. + */ + + IpHeaderLength = (Tmp & 0xf) * 4; + pPacketInfo->IpHeaderLength = IpHeaderLength; + + /* Check the IP header length. */ + + /* 04-Aug-1998 sw - Really check the IHL? Necessary? */ + + if (IpHeaderLength < 5*4) { + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX, + ("Tx: Invalid IP Header Length %u.\n", IpHeaderLength)); + pPacketInfo->ProtocolFlags = 0; + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++; + return; + } + + /* This is an IPv4 frame with a header of valid length. */ + + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxOkCts++; + + /* Check if we should calculate the IP header checksum. */ + + ProtocolFlags = pPacketInfo->ProtocolFlags; + + if (ProtocolFlags & SKCS_PROTO_IP) { + pPacketInfo->IpHeaderChecksum = + SkCsCalculateChecksum(pIpHeader, IpHeaderLength); + } + + /* Get the next level protocol identifier. */ + + NextLevelProtocol = + *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL); + + /* + * Check if this is a TCP or UDP frame and if we should calculate the + * TCP/UDP pseudo header checksum. + * + * Also clear all protocol bit flags of protocols not present in the + * frame. + */ + + if ((ProtocolFlags & SKCS_PROTO_TCP) != 0 && + NextLevelProtocol == SKCS_PROTO_ID_TCP) { + /* TCP/IP frame. */ + ProtocolFlags &= SKCS_PROTO_TCP | SKCS_PROTO_IP; + NextLevelProtoStats = + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP]; + } + else if ((ProtocolFlags & SKCS_PROTO_UDP) != 0 && + NextLevelProtocol == SKCS_PROTO_ID_UDP) { + /* UDP/IP frame. */ + ProtocolFlags &= SKCS_PROTO_UDP | SKCS_PROTO_IP; + NextLevelProtoStats = + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP]; + } + else { + /* + * Either not a TCP or UDP frame and/or TCP/UDP processing not + * specified. + */ + pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP; + return; + } + + /* Check if this is an IP fragment. */ + + /* + * Note: An IP fragment has a non-zero "Fragment Offset" field and/or + * the "More Fragments" bit set. Thus, if both the "Fragment Offset" + * and the "More Fragments" are zero, it is *not* a fragment. We can + * easily check both at the same time since they are in the same 16-bit + * word. + */ + + if ((*(SK_U16 *) + SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) & + ~SKCS_IP_DONT_FRAGMENT) != 0) { + /* IP fragment; ignore all other protocols. */ + pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP; + NextLevelProtoStats->TxUnableCts++; + return; + } + + /* + * Calculate the TCP/UDP pseudo header checksum. + */ + + /* Get total length of IP header and data. */ + + IpDataLength = + *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH); + + /* Get length of IP data portion. */ + + IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength; + + /* Calculate the sum of all pseudo header fields (16-bit). */ + + PseudoHeaderChecksum = + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_SOURCE_ADDRESS + 0) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_SOURCE_ADDRESS + 2) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_DESTINATION_ADDRESS + 0) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_DESTINATION_ADDRESS + 2) + + (unsigned long) SKCS_HTON16(NextLevelProtocol) + + (unsigned long) SKCS_HTON16(IpDataLength); + + /* Add-in any carries. */ + + SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0); + + /* Add-in any new carry. */ + + SKCS_OC_ADD(pPacketInfo->PseudoHeaderChecksum, PseudoHeaderChecksum, 0); + + pPacketInfo->ProtocolFlags = ProtocolFlags; + NextLevelProtoStats->TxOkCts++; /* Success. */ +} /* SkCsGetSendInfo */ + + +/****************************************************************************** + * + * SkCsGetReceiveInfo - verify checksum information for a received packet + * + * Description: + * Verify a received frame's checksum. The function returns a status code + * reflecting the result of the verification. + * + * Note: + * Before calling this function you have to verify that the frame is + * not padded and Checksum1 and Checksum2 are bigger than 1. + * + * Arguments: + * pAc - Pointer to adapter context struct. + * + * pIpHeader - Pointer to IP header. Must be at least the length in bytes + * of the received IP header including any option fields. For UDP packets, + * 8 additional bytes are needed to access the UDP checksum. + * + * Note: The actual length of the IP header is stored in the lower four + * bits of the first octet of the IP header as the number of 4-byte words, + * so it must be multiplied by four to get the length in bytes. Thus, the + * maximum IP header length is 15 * 4 = 60 bytes. + * + * Checksum1 - The first 16-bit Internet Checksum calculated by the + * hardware starting at the offset returned by SkCsSetReceiveFlags(). + * + * Checksum2 - The second 16-bit Internet Checksum calculated by the + * hardware starting at the offset returned by SkCsSetReceiveFlags(). + * + * Returns: + * SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame. + * SKCS_STATUS_IP_CSUM_ERROR - IP checksum error. + * SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame. + * SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame + * SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok). + * SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame). + * SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok). + * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok). + * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok. + * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok. + * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum. + * + * Note: If SKCS_OVERWRITE_STATUS is defined, the SKCS_STATUS_XXX values + * returned here can be defined in some header file by the module using CSUM. + * In this way, the calling module can assign return values for its own needs, + * e.g. by assigning bit flags to the individual protocols. + */ +SKCS_STATUS SkCsGetReceiveInfo( +SK_AC *pAc, /* Adapter context struct. */ +void *pIpHeader, /* IP header. */ +unsigned Checksum1, /* Hardware checksum 1. */ +unsigned Checksum2, /* Hardware checksum 2. */ +int NetNumber) /* Net number */ +{ + /* Internet Header Version found in IP header. */ + unsigned InternetHeaderVersion; + + /* Length of the IP header as found in IP header. */ + unsigned IpHeaderLength; + + /* Length of IP data portion. */ + unsigned IpDataLength; + + /* IP header checksum. */ + unsigned IpHeaderChecksum; + + /* IP header options checksum, if any. */ + unsigned IpOptionsChecksum; + + /* IP data checksum, i.e. TCP/UDP checksum. */ + unsigned IpDataChecksum; + + /* Next level protocol identifier found in IP header. */ + unsigned NextLevelProtocol; + + /* The checksum of the "next level protocol", i.e. TCP or UDP. */ + unsigned long NextLevelProtocolChecksum; + + /* Pointer to next level protocol statistics structure. */ + SKCS_PROTO_STATS *NextLevelProtoStats; + + /* Temporary variable. */ + unsigned Tmp; + + Tmp = *(SK_U8 *) + SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH); + + /* Get the Internet Header Version (IHV). */ + /* Note: The IHV is stored in the upper four bits. */ + + InternetHeaderVersion = Tmp >> 4; + + /* Check the Internet Header Version. */ + /* Note: We currently only support IP version 4. */ + + if (InternetHeaderVersion != 4) { /* IPv4? */ + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX, + ("Rx: Unknown Internet Header Version %u.\n", + InternetHeaderVersion)); + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++; + return (SKCS_STATUS_UNKNOWN_IP_VERSION); + } + + /* Get the IP header length (IHL). */ + /* + * Note: The IHL is stored in the lower four bits as the number of + * 4-byte words. + */ + + IpHeaderLength = (Tmp & 0xf) * 4; + + /* Check the IP header length. */ + + /* 04-Aug-1998 sw - Really check the IHL? Necessary? */ + + if (IpHeaderLength < 5*4) { + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX, + ("Rx: Invalid IP Header Length %u.\n", IpHeaderLength)); + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++; + return (SKCS_STATUS_IP_CSUM_ERROR); + } + + /* This is an IPv4 frame with a header of valid length. */ + + /* Get the IP header and data checksum. */ + + IpDataChecksum = Checksum2; + + /* + * The IP header checksum is calculated as follows: + * + * IpHeaderChecksum = Checksum1 - Checksum2 + */ + + SKCS_OC_SUB(IpHeaderChecksum, Checksum1, Checksum2); + + /* Check if any IP header options. */ + + if (IpHeaderLength > SKCS_IP_HEADER_SIZE) { + + /* Get the IP options checksum. */ + + IpOptionsChecksum = SkCsCalculateChecksum( + SKCS_IDX(pIpHeader, SKCS_IP_HEADER_SIZE), + IpHeaderLength - SKCS_IP_HEADER_SIZE); + + /* Adjust the IP header and IP data checksums. */ + + SKCS_OC_ADD(IpHeaderChecksum, IpHeaderChecksum, IpOptionsChecksum); + + SKCS_OC_SUB(IpDataChecksum, IpDataChecksum, IpOptionsChecksum); + } + + /* + * Check if the IP header checksum is ok. + * + * NOTE: We must check the IP header checksum even if the caller just wants + * us to check upper-layer checksums, because we cannot do any further + * processing of the packet without a valid IP checksum. + */ + + /* Get the next level protocol identifier. */ + + NextLevelProtocol = *(SK_U8 *) + SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL); + + if (IpHeaderChecksum != 0xFFFF) { + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++; + /* the NDIS tester wants to know the upper level protocol too */ + if (NextLevelProtocol == SKCS_PROTO_ID_TCP) { + return(SKCS_STATUS_IP_CSUM_ERROR_TCP); + } + else if (NextLevelProtocol == SKCS_PROTO_ID_UDP) { + return(SKCS_STATUS_IP_CSUM_ERROR_UDP); + } + return (SKCS_STATUS_IP_CSUM_ERROR); + } + + /* + * Check if this is a TCP or UDP frame and if we should calculate the + * TCP/UDP pseudo header checksum. + * + * Also clear all protocol bit flags of protocols not present in the + * frame. + */ + + if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_TCP) != 0 && + NextLevelProtocol == SKCS_PROTO_ID_TCP) { + /* TCP/IP frame. */ + NextLevelProtoStats = + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP]; + } + else if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_UDP) != 0 && + NextLevelProtocol == SKCS_PROTO_ID_UDP) { + /* UDP/IP frame. */ + NextLevelProtoStats = + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP]; + } + else { + /* + * Either not a TCP or UDP frame and/or TCP/UDP processing not + * specified. + */ + return (SKCS_STATUS_IP_CSUM_OK); + } + + /* Check if this is an IP fragment. */ + + /* + * Note: An IP fragment has a non-zero "Fragment Offset" field and/or + * the "More Fragments" bit set. Thus, if both the "Fragment Offset" + * and the "More Fragments" are zero, it is *not* a fragment. We can + * easily check both at the same time since they are in the same 16-bit + * word. + */ + + if ((*(SK_U16 *) + SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) & + ~SKCS_IP_DONT_FRAGMENT) != 0) { + /* IP fragment; ignore all other protocols. */ + NextLevelProtoStats->RxUnableCts++; + return (SKCS_STATUS_IP_FRAGMENT); + } + + /* + * 08-May-2000 ra + * + * From RFC 768 (UDP) + * If the computed checksum is zero, it is transmitted as all ones (the + * equivalent in one's complement arithmetic). An all zero transmitted + * checksum value means that the transmitter generated no checksum (for + * debugging or for higher level protocols that don't care). + */ + + if (NextLevelProtocol == SKCS_PROTO_ID_UDP && + *(SK_U16*)SKCS_IDX(pIpHeader, IpHeaderLength + 6) == 0x0000) { + + NextLevelProtoStats->RxOkCts++; + + return (SKCS_STATUS_IP_CSUM_OK_NO_UDP); + } + + /* + * Calculate the TCP/UDP checksum. + */ + + /* Get total length of IP header and data. */ + + IpDataLength = + *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH); + + /* Get length of IP data portion. */ + + IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength; + + NextLevelProtocolChecksum = + + /* Calculate the pseudo header checksum. */ + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_SOURCE_ADDRESS + 0) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_SOURCE_ADDRESS + 2) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_DESTINATION_ADDRESS + 0) + + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader, + SKCS_OFS_IP_DESTINATION_ADDRESS + 2) + + (unsigned long) SKCS_HTON16(NextLevelProtocol) + + (unsigned long) SKCS_HTON16(IpDataLength) + + + /* Add the TCP/UDP header checksum. */ + + (unsigned long) IpDataChecksum; + + /* Add-in any carries. */ + + SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0); + + /* Add-in any new carry. */ + + SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0); + + /* Check if the TCP/UDP checksum is ok. */ + + if ((unsigned) NextLevelProtocolChecksum == 0xFFFF) { + + /* TCP/UDP checksum ok. */ + + NextLevelProtoStats->RxOkCts++; + + return (NextLevelProtocol == SKCS_PROTO_ID_TCP ? + SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK); + } + + /* TCP/UDP checksum error. */ + + NextLevelProtoStats->RxErrCts++; + + return (NextLevelProtocol == SKCS_PROTO_ID_TCP ? + SKCS_STATUS_TCP_CSUM_ERROR : SKCS_STATUS_UDP_CSUM_ERROR); +} /* SkCsGetReceiveInfo */ +#endif + + +/****************************************************************************** + * + * SkCsSetReceiveFlags - set checksum receive flags + * + * Description: + * Use this function to set the various receive flags. According to the + * protocol flags set by the caller, the start offsets within received + * packets of the two hardware checksums are returned. These offsets must + * be stored in all receive descriptors. + * + * Arguments: + * pAc - Pointer to adapter context struct. + * + * ReceiveFlags - Any combination of SK_PROTO_XXX flags of the protocols + * for which the caller wants checksum information on received frames. + * + * pChecksum1Offset - The start offset of the first receive descriptor + * hardware checksum to be calculated for received frames is returned + * here. + * + * pChecksum2Offset - The start offset of the second receive descriptor + * hardware checksum to be calculated for received frames is returned + * here. + * + * Returns: N/A + * Returns the two hardware checksum start offsets. + */ +void SkCsSetReceiveFlags( +SK_AC *pAc, /* Adapter context struct. */ +unsigned ReceiveFlags, /* New receive flags. */ +unsigned *pChecksum1Offset, /* Offset for hardware checksum 1. */ +unsigned *pChecksum2Offset, /* Offset for hardware checksum 2. */ +int NetNumber) +{ + /* Save the receive flags. */ + + pAc->Csum.ReceiveFlags[NetNumber] = ReceiveFlags; + + /* First checksum start offset is the IP header. */ + *pChecksum1Offset = SKCS_MAC_HEADER_SIZE; + + /* + * Second checksum start offset is the IP data. Note that this may vary + * if there are any IP header options in the actual packet. + */ + *pChecksum2Offset = SKCS_MAC_HEADER_SIZE + SKCS_IP_HEADER_SIZE; +} /* SkCsSetReceiveFlags */ + +#ifndef SkCsCalculateChecksum + +/****************************************************************************** + * + * SkCsCalculateChecksum - calculate checksum for specified data + * + * Description: + * Calculate and return the 16-bit Internet Checksum for the specified + * data. + * + * Arguments: + * pData - Pointer to data for which the checksum shall be calculated. + * Note: The pointer should be aligned on a 16-bit boundary. + * + * Length - Length in bytes of data to checksum. + * + * Returns: + * The 16-bit Internet Checksum for the specified data. + * + * Note: The checksum is calculated in the machine's natural byte order, + * i.e. little vs. big endian. Thus, the resulting checksum is different + * for the same input data on little and big endian machines. + * + * However, when written back to the network packet, the byte order is + * always in correct network order. + */ +unsigned SkCsCalculateChecksum( +void *pData, /* Data to checksum. */ +unsigned Length) /* Length of data. */ +{ + SK_U16 *pU16; /* Pointer to the data as 16-bit words. */ + unsigned long Checksum; /* Checksum; must be at least 32 bits. */ + + /* Sum up all 16-bit words. */ + + pU16 = (SK_U16 *) pData; + for (Checksum = 0; Length > 1; Length -= 2) { + Checksum += *pU16++; + } + + /* If this is an odd number of bytes, add-in the last byte. */ + + if (Length > 0) { +#ifdef SK_BIG_ENDIAN + /* Add the last byte as the high byte. */ + Checksum += ((unsigned) *(SK_U8 *) pU16) << 8; +#else /* !SK_BIG_ENDIAN */ + /* Add the last byte as the low byte. */ + Checksum += *(SK_U8 *) pU16; +#endif /* !SK_BIG_ENDIAN */ + } + + /* Add-in any carries. */ + + SKCS_OC_ADD(Checksum, Checksum, 0); + + /* Add-in any new carry. */ + + SKCS_OC_ADD(Checksum, Checksum, 0); + + /* Note: All bits beyond the 16-bit limit are now zero. */ + + return ((unsigned) Checksum); +} /* SkCsCalculateChecksum */ + +#endif /* SkCsCalculateChecksum */ + +/****************************************************************************** + * + * SkCsEvent - the CSUM event dispatcher + * + * Description: + * This is the event handler for the CSUM module. + * + * Arguments: + * pAc - Pointer to adapter context. + * + * Ioc - I/O context. + * + * Event - Event id. + * + * Param - Event dependent parameter. + * + * Returns: + * The 16-bit Internet Checksum for the specified data. + * + * Note: The checksum is calculated in the machine's natural byte order, + * i.e. little vs. big endian. Thus, the resulting checksum is different + * for the same input data on little and big endian machines. + * + * However, when written back to the network packet, the byte order is + * always in correct network order. + */ +int SkCsEvent( +SK_AC *pAc, /* Pointer to adapter context. */ +SK_IOC Ioc, /* I/O context. */ +SK_U32 Event, /* Event id. */ +SK_EVPARA Param) /* Event dependent parameter. */ +{ + int ProtoIndex; + int NetNumber; + + switch (Event) { + /* + * Clear protocol statistics. + * + * Param - Protocol index, or -1 for all protocols. + * - Net number. + */ + case SK_CSUM_EVENT_CLEAR_PROTO_STATS: + + ProtoIndex = (int)Param.Para32[1]; + NetNumber = (int)Param.Para32[0]; + if (ProtoIndex < 0) { /* Clear for all protocols. */ + if (NetNumber >= 0) { + memset(&pAc->Csum.ProtoStats[NetNumber][0], 0, + sizeof(pAc->Csum.ProtoStats[NetNumber])); + } + } + else { /* Clear for individual protocol. */ + memset(&pAc->Csum.ProtoStats[NetNumber][ProtoIndex], 0, + sizeof(pAc->Csum.ProtoStats[NetNumber][ProtoIndex])); + } + break; + default: + break; + } + return (0); /* Success. */ +} /* SkCsEvent */ + +#endif /* SK_USE_CSUM */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skge.c b/drivers/sk98lin/skge.c new file mode 100644 index 000000000..61a609423 --- /dev/null +++ b/drivers/sk98lin/skge.c @@ -0,0 +1,4864 @@ +/****************************************************************************** + * + * Name: skge.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.46 $ + * Date: $Date: 2003/02/25 14:16:36 $ + * Purpose: The main driver source module + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * Driver for SysKonnect Gigabit Ethernet Server Adapters: + * + * SK-9871 (single link 1000Base-ZX) + * SK-9872 (dual link 1000Base-ZX) + * SK-9861 (single link 1000Base-SX, VF45 Volition Plug) + * SK-9862 (dual link 1000Base-SX, VF45 Volition Plug) + * SK-9841 (single link 1000Base-LX) + * SK-9842 (dual link 1000Base-LX) + * SK-9843 (single link 1000Base-SX) + * SK-9844 (dual link 1000Base-SX) + * SK-9821 (single link 1000Base-T) + * SK-9822 (dual link 1000Base-T) + * SK-9881 (single link 1000Base-SX V2 LC) + * SK-9871 (single link 1000Base-ZX V2) + * SK-9861 (single link 1000Base-SX V2, VF45 Volition Plug) + * SK-9841 (single link 1000Base-LX V2) + * SK-9843 (single link 1000Base-SX V2) + * SK-9821 (single link 1000Base-T V2) + * + * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and + * SysKonnects GEnesis Solaris driver + * Author: Christoph Goos (cgoos@syskonnect.de) + * Mirko Lindner (mlindner@syskonnect.de) + * + * Address all question to: linux@syskonnect.de + * + * The technical manual for the adapters is available from SysKonnect's + * web pages: www.syskonnect.com + * Goto "Support" and search Knowledge Base for "manual". + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skge.c,v $ + * Revision 1.46 2003/02/25 14:16:36 mlindner + * Fix: Copyright statement + * + * Revision 1.45 2003/02/25 13:25:55 mlindner + * Add: Performance improvements + * Add: Support for various vendors + * Fix: Init function + * + * Revision 1.44 2003/01/09 09:25:26 mlindner + * Fix: Remove useless init_module/cleanup_module forward declarations + * + * Revision 1.43 2002/11/29 08:42:41 mlindner + * Fix: Boot message + * + * Revision 1.42 2002/11/28 13:30:23 mlindner + * Add: New frame check + * + * Revision 1.41 2002/11/27 13:55:18 mlindner + * Fix: Drop wrong csum packets + * Fix: Initialize proc_entry after hw check + * + * Revision 1.40 2002/10/31 07:50:37 tschilli + * Function SkGeInitAssignRamToQueues() from common module inserted. + * Autonegotiation is set to ON for all adapters. + * LinkSpeedUsed is used in link up status report. + * Role parameter will show up for 1000 Mbps links only. + * GetConfiguration() inserted after init level 1 in SkGeChangeMtu(). + * All return values of SkGeInit() and SkGeInitPort() are checked. + * + * Revision 1.39 2002/10/02 12:56:05 mlindner + * Add: Support for Yukon + * Add: Support for ZEROCOPY, scatter-gather and hw checksum + * Add: New transmit ring function (use SG and TCP/UDP hardware checksumming) + * Add: New init function + * Add: Speed check and setup + * Add: Merge source for kernel 2.2.x and 2.4.x + * Add: Opcode check for tcp + * Add: Frame length check + * Fix: Transmit complete interrupt + * Fix: Interrupt moderation + * + * Revision 1.29.2.13 2002/01/14 12:44:52 mlindner + * Fix: Rlmt modes + * + * Revision 1.29.2.12 2001/12/07 12:06:18 mlindner + * Fix: malloc -> slab changes + * + * Revision 1.29.2.11 2001/12/06 15:19:20 mlindner + * Add: DMA attributes + * Fix: Module initialisation + * Fix: pci_map_single and pci_unmap_single replaced + * + * Revision 1.29.2.10 2001/12/06 09:56:50 mlindner + * Corrected some printk's + * + * Revision 1.29.2.9 2001/09/05 12:15:34 mlindner + * Add: LBFO Changes + * Fix: Counter Errors (Jumbo == to long errors) + * Fix: Changed pAC->PciDev declaration + * Fix: too short counters + * + * Revision 1.29.2.8 2001/06/25 12:10:44 mlindner + * fix: ReceiveIrq() changed. + * + * Revision 1.29.2.7 2001/06/25 08:07:05 mlindner + * fix: RLMT locking in ReceiveIrq() changed. + * + * Revision 1.29.2.6 2001/05/21 07:59:29 mlindner + * fix: MTU init problems + * + * Revision 1.29.2.5 2001/05/08 11:25:08 mlindner + * fix: removed VLAN error message + * + * Revision 1.29.2.4 2001/05/04 13:31:43 gklug + * fix: do not handle eth_copy on bad fragments received. + * + * Revision 1.29.2.3 2001/04/23 08:06:43 mlindner + * Fix: error handling + * + * Revision 1.29.2.2 2001/03/15 12:04:54 mlindner + * Fixed memory problem + * + * Revision 1.29.2.1 2001/03/12 16:41:44 mlindner + * add: procfs function + * add: dual-net function + * add: RLMT networks + * add: extended PNMI features + * + * Kernel 2.4.x specific: + * Revision 1.xx 2000/09/12 13:31:56 cgoos + * Fixed missign "dev=NULL in skge_probe. + * Added counting for jumbo frames (corrects error statistic). + * Removed VLAN tag check (enables VLAN support). + * + * Kernel 2.2.x specific: + * Revision 1.29 2000/02/21 13:31:56 cgoos + * Fixed "unused" warning for UltraSPARC change. + * + * Partially kernel 2.2.x specific: + * Revision 1.28 2000/02/21 10:32:36 cgoos + * Added fixes for UltraSPARC. + * Now printing RlmtMode and PrefPort setting at startup. + * Changed XmitFrame return value. + * Fixed rx checksum calculation for BIG ENDIAN systems. + * Fixed rx jumbo frames counted as ierrors. + * + * + * Revision 1.27 1999/11/25 09:06:28 cgoos + * Changed base_addr to unsigned long. + * + * Revision 1.26 1999/11/22 13:29:16 cgoos + * Changed license header to GPL. + * Changes for inclusion in linux kernel (2.2.13). + * Removed 2.0.x defines. + * Changed SkGeProbe to skge_probe. + * Added checks in SkGeIoctl. + * + * Revision 1.25 1999/10/07 14:47:52 cgoos + * Changed 984x to 98xx. + * + * Revision 1.24 1999/09/30 07:21:01 cgoos + * Removed SK_RLMT_SLOW_LOOKAHEAD option. + * Giving spanning tree packets also to OS now. + * + * Revision 1.23 1999/09/29 07:36:50 cgoos + * Changed assignment for IsBc/IsMc. + * + * Revision 1.22 1999/09/28 12:57:09 cgoos + * Added CheckQueue also to Single-Port-ISR. + * + * Revision 1.21 1999/09/28 12:42:41 cgoos + * Changed parameter strings for RlmtMode. + * + * Revision 1.20 1999/09/28 12:37:57 cgoos + * Added CheckQueue for fast delivery of RLMT frames. + * + * Revision 1.19 1999/09/16 07:57:25 cgoos + * Copperfield changes. + * + * Revision 1.18 1999/09/03 13:06:30 cgoos + * Fixed RlmtMode=CheckSeg bug: wrong DEV_KFREE_SKB in RLMT_SEND caused + * double allocated skb's. + * FrameStat in ReceiveIrq was accessed via wrong Rxd. + * Queue size for async. standby Tx queue was zero. + * FillRxLimit of 0 could cause problems with ReQueue, changed to 1. + * Removed debug output of checksum statistic. + * + * Revision 1.17 1999/08/11 13:55:27 cgoos + * Transmit descriptor polling was not reenabled after SkGePortInit. + * + * Revision 1.16 1999/07/27 15:17:29 cgoos + * Added some "\n" in output strings (removed while debuging...). + * + * Revision 1.15 1999/07/23 12:09:30 cgoos + * Performance optimization, rx checksumming, large frame support. + * + * Revision 1.14 1999/07/14 11:26:27 cgoos + * Removed Link LED settings (now in RLMT). + * Added status output at NET UP. + * Fixed SMP problems with Tx and SWITCH running in parallel. + * Fixed return code problem at RLMT_SEND event. + * + * Revision 1.13 1999/04/07 10:11:42 cgoos + * Fixed Single Port problems. + * Fixed Multi-Adapter problems. + * Always display startup string. + * + * Revision 1.12 1999/03/29 12:26:37 cgoos + * Reversed locking to fine granularity. + * Fixed skb double alloc problem (caused by incorrect xmit return code). + * Enhanced function descriptions. + * + * Revision 1.11 1999/03/15 13:10:51 cgoos + * Changed device identifier in output string to ethX. + * + * Revision 1.10 1999/03/15 12:12:34 cgoos + * Changed copyright notice. + * + * Revision 1.9 1999/03/15 12:10:17 cgoos + * Changed locking to one driver lock. + * Added check of SK_AC-size (for consistency with library). + * + * Revision 1.8 1999/03/08 11:44:02 cgoos + * Fixed missing dev->tbusy in SkGeXmit. + * Changed large frame (jumbo) buffer number. + * Added copying of short frames. + * + * Revision 1.7 1999/03/04 13:26:57 cgoos + * Fixed spinlock calls for SMP. + * + * Revision 1.6 1999/03/02 09:53:51 cgoos + * Added descriptor revertion for big endian machines. + * + * Revision 1.5 1999/03/01 08:50:59 cgoos + * Fixed SkGeChangeMtu. + * Fixed pci config space accesses. + * + * Revision 1.4 1999/02/18 15:48:44 cgoos + * Corrected some printk's. + * + * Revision 1.3 1999/02/18 12:45:55 cgoos + * Changed SK_MAX_CARD_PARAM to default 16 + * + * Revision 1.2 1999/02/18 10:55:32 cgoos + * Removed SkGeDrvTimeStamp function. + * Printing "ethX:" before adapter type at adapter init. + * + * + * 10-Feb-1999 cg Created, based on Linux' acenic.c, 3c59x.c and + * SysKonnects GEnesis Solaris driver + * + ******************************************************************************/ + +/****************************************************************************** + * + * Possible compiler options (#define xxx / -Dxxx): + * + * debugging can be enable by changing SK_DEBUG_CHKMOD and + * SK_DEBUG_CHKCAT in makefile (described there). + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This is the main module of the Linux GE driver. + * + * All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h + * are part of SysKonnect's COMMON MODULES for the SK-98xx adapters. + * Those are used for drivers on multiple OS', so some thing may seem + * unnecessary complicated on Linux. Please do not try to 'clean up' + * them without VERY good reasons, because this will make it more + * difficult to keep the Linux driver in synchronisation with the + * other versions. + * + * Include file hierarchy: + * + * + * + * "h/skdrv1st.h" + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * those three depending on kernel version used: + * + * + * + * + * + * "h/skerror.h" + * "h/skdebug.h" + * "h/sktypes.h" + * "h/lm80.h" + * "h/xmac_ii.h" + * + * "h/skdrv2nd.h" + * "h/skqueue.h" + * "h/skgehwt.h" + * "h/sktimer.h" + * "h/ski2c.h" + * "h/skgepnmi.h" + * "h/skvpd.h" + * "h/skgehw.h" + * "h/skgeinit.h" + * "h/skaddr.h" + * "h/skgesirq.h" + * "h/skcsum.h" + * "h/skrlmt.h" + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include "h/skversion.h" +#if 0 +#include +#include +#include +#endif +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + + +/* defines ******************************************************************/ +/* for debuging on x86 only */ +/* #define BREAKPOINT() asm(" int $3"); */ + +/* use the scatter-gather functionality with sendfile() */ +#if 0 +#define SK_ZEROCOPY +#endif + +/* use of a transmit complete interrupt */ +#define USE_TX_COMPLETE + +/* use interrupt moderation (for tx complete only) */ +#define USE_INT_MOD +#define INTS_PER_SEC 1000 + +/* + * threshold for copying small receive frames + * set to 0 to avoid copying, set to 9001 to copy all frames + */ +#define SK_COPY_THRESHOLD 50 + +/* number of adapters that can be configured via command line params */ +#define SK_MAX_CARD_PARAM 16 + + +/* + * use those defines for a compile-in version of the driver instead + * of command line parameters + */ +/* #define LINK_SPEED_A {"Auto", } */ +/* #define LINK_SPEED_B {"Auto", } */ +/* #define AUTO_NEG_A {"Sense", } */ +/* #define AUTO_NEG_B {"Sense", } */ +/* #define DUP_CAP_A {"Both", } */ +/* #define DUP_CAP_B {"Both", } */ +/* #define FLOW_CTRL_A {"SymOrRem", } */ +/* #define FLOW_CTRL_B {"SymOrRem", } */ +/* #define ROLE_A {"Auto", } */ +/* #define ROLE_B {"Auto", } */ +/* #define PREF_PORT {"A", } */ +/* #define RLMT_MODE {"CheckLinkState", } */ + +#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb) +#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb) +#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb) + +/* function prototypes ******************************************************/ +static void FreeResources(struct SK_NET_DEVICE *dev); +static int SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC); +static SK_BOOL BoardAllocMem(SK_AC *pAC); +static void BoardFreeMem(SK_AC *pAC); +static void BoardInitMem(SK_AC *pAC); +static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, + int*, SK_BOOL); + +#if 0 +static void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); +static void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); +static int SkGeOpen(struct SK_NET_DEVICE *dev); +static int SkGeClose(struct SK_NET_DEVICE *dev); +static int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev); +static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p); +static void SkGeSetRxMode(struct SK_NET_DEVICE *dev); +static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev); +static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd); +#else +void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); +void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); +int SkGeOpen(struct SK_NET_DEVICE *dev); +int SkGeClose(struct SK_NET_DEVICE *dev); +int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev); +#endif +static void GetConfiguration(SK_AC*); +static void ProductStr(SK_AC*); +static int XmitFrame(SK_AC*, TX_PORT*, struct sk_buff*); +static void FreeTxDescriptors(SK_AC*pAC, TX_PORT*); +static void FillRxRing(SK_AC*, RX_PORT*); +static SK_BOOL FillRxDescriptor(SK_AC*, RX_PORT*); +#if 0 +static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL); +#else +void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL); +#endif +static void ClearAndStartRx(SK_AC*, int); +static void ClearTxIrq(SK_AC*, int, int); +static void ClearRxRing(SK_AC*, RX_PORT*); +static void ClearTxRing(SK_AC*, TX_PORT*); +#if 0 +static void SetQueueSizes(SK_AC *pAC); + +static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int new_mtu); +#endif +static void PortReInitBmu(SK_AC*, int); +#if 0 +static int SkGeIocMib(DEV_NET*, unsigned int, int); +static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*); +#endif + +/*Extern */ + +/* external Proc function */ +extern int proc_read( + char *buffer, + char **buffer_location, + off_t offset, + int buffer_length, + int *eof, + void *data); + +#ifdef DEBUG +static void DumpMsg(struct sk_buff*, char*); +static void DumpData(char*, int); +static void DumpLong(char*, int); +#endif +void dump_frag( SK_U8 *data, int length); + +/* global variables *********************************************************/ +#if 0 +static const char *BootString = BOOT_STRING; +#endif +struct SK_NET_DEVICE *SkGeRootDev = NULL; +static int probed __initdata = 0; + +/* local variables **********************************************************/ +static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}}; +static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480}; + + +/* local variables **********************************************************/ +const char SK_Root_Dir_entry[8]; + +#if 0 +static struct proc_dir_entry *pSkRootDir; +#endif + + +static struct pci_device_id supported[] = { + {PCI_VENDOR_ID_3COM, 0x1700}, + {PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE}, + {PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU}, + {} +}; + + +/***************************************************************************** + * + * skge_probe - find all SK-98xx adapters + * + * Description: + * This function scans the PCI bus for SK-98xx adapters. Resources for + * each adapter are allocated and the adapter is brought into Init 1 + * state. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +#if 0 +static int __init skge_probe (void) +#else +int skge_probe (struct eth_device ** ret_dev) +#endif +{ +#if 0 + int proc_root_initialized = 0; +#endif + int boards_found = 0; +#if 0 + int vendor_flag = SK_FALSE; +#endif + SK_AC *pAC; + DEV_NET *pNet = NULL; +#if 0 + struct proc_dir_entry *pProcFile; + struct pci_dev *pdev = NULL; + unsigned long base_address; +#else + u32 base_address; +#endif + struct SK_NET_DEVICE *dev = NULL; +#if 0 + SK_BOOL DeviceFound = SK_FALSE; +#endif + SK_BOOL BootStringCount = SK_FALSE; +#if 1 + pci_dev_t devno; +#endif + + if (probed) + return -ENODEV; + probed++; + + if (!pci_present()) /* is PCI support present? */ + return -ENODEV; + +#if 0 + while((pdev = pci_find_class(PCI_CLASS_NETWORK_ETHERNET << 8, pdev))) +#else + while((devno = pci_find_devices (supported, boards_found)) >= 0) +#endif + { + + dev = NULL; + pNet = NULL; + + +#if 0 + SK_PCI_ISCOMPLIANT(vendor_flag, pdev); + if (!vendor_flag) + continue; +#endif + +/* if ((pdev->vendor != PCI_VENDOR_ID_SYSKONNECT) && + ((pdev->device != PCI_DEVICE_ID_SYSKONNECT_GE) || + (pdev->device != PCI_DEVICE_ID_SYSKONNECT_YU))){ + continue; + } +*/ +#if 0 + /* Configure DMA attributes. */ + if (pci_set_dma_mask(pdev, (u64) 0xffffffffffffffff) && + pci_set_dma_mask(pdev, (u64) 0xffffffff)) + continue; +#endif + + +#if 0 + if ((dev = init_etherdev(dev, sizeof(DEV_NET))) == NULL) { + printk(KERN_ERR "Unable to allocate etherdev " + "structure!\n"); + break; + } +#else + dev = malloc (sizeof *dev); + memset(dev, 0, sizeof(*dev)); + dev->priv = malloc(sizeof(DEV_NET)); +#endif + + if (dev->priv == NULL) { + printk(KERN_ERR "Unable to allocate adapter " + "structure!\n"); + break; + } + + pNet = dev->priv; + pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL); + if (pNet->pAC == NULL){ + kfree(dev->priv); + printk(KERN_ERR "Unable to allocate adapter " + "structure!\n"); + break; + } + + /* Print message */ + if (!BootStringCount) { + /* set display flag to TRUE so that */ + /* we only display this string ONCE */ + BootStringCount = SK_TRUE; +#ifdef SK98_INFO + printk("%s\n", BootString); +#endif + } + + memset(pNet->pAC, 0, sizeof(SK_AC)); + pAC = pNet->pAC; +#if 0 + pAC->PciDev = pdev; + pAC->PciDevId = pdev->device; + pAC->dev[0] = dev; + pAC->dev[1] = dev; +#else + pAC->PciDev = devno; + ret_dev[0] = pAC->dev[0] = dev; + ret_dev[1] = pAC->dev[1] = dev; +#endif + sprintf(pAC->Name, "SysKonnect SK-98xx"); + pAC->CheckQueue = SK_FALSE; + + pNet->Mtu = 1500; + pNet->Up = 0; +#if 0 + dev->irq = pdev->irq; + + dev->open = &SkGeOpen; + dev->stop = &SkGeClose; + dev->hard_start_xmit = &SkGeXmit; + dev->get_stats = &SkGeStats; + dev->set_multicast_list = &SkGeSetRxMode; + dev->set_mac_address = &SkGeSetMacAddr; + dev->do_ioctl = &SkGeIoctl; + dev->change_mtu = &SkGeChangeMtu; + dev->flags &= ~IFF_RUNNING; +#endif + +#ifdef SK_ZEROCOPY + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + /* Use only if yukon hardware */ + /* SK and ZEROCOPY - fly baby... */ + dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; + } +#endif + +#if 0 + /* + * Dummy value. + */ + dev->base_addr = 42; + pci_set_master(pdev); + + pci_set_master(pdev); + base_address = pci_resource_start (pdev, 0); +#else + pci_write_config_dword(devno, + PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, + &base_address); +#endif + +#ifdef SK_BIG_ENDIAN + /* + * On big endian machines, we use the adapter's aibility of + * reading the descriptors as big endian. + */ + { + SK_U32 our2; + SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2); + our2 |= PCI_REV_DESC; + SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2); + } +#endif + + /* + * Remap the regs into kernel space. + */ +#if 0 + pAC->IoBase = (char*)ioremap(base_address, 0x4000); +#else + pAC->IoBase = (char*)pci_mem_to_phys(devno, base_address); +#endif + + if (!pAC->IoBase){ + printk(KERN_ERR "%s: Unable to map I/O register, " + "SK 98xx No. %i will be disabled.\n", + dev->name, boards_found); + kfree(dev); + break; + } + + pAC->Index = boards_found; + if (SkGeBoardInit(dev, pAC)) { + FreeResources(dev); + kfree(dev); + continue; + } + +#if 0 + memcpy((caddr_t) &dev->dev_addr, + (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); +#else + memcpy((caddr_t) &dev->enetaddr, + (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6); +#endif + +#if 0 + /* First adapter... Create proc and print message */ + if (!DeviceFound) { + DeviceFound = SK_TRUE; + SK_MEMCPY(&SK_Root_Dir_entry, BootString, + sizeof(SK_Root_Dir_entry) - 1); + + /*Create proc (directory)*/ + if(!proc_root_initialized) { + pSkRootDir = create_proc_entry(SK_Root_Dir_entry, + S_IFDIR | S_IWUSR | S_IRUGO | S_IXUGO, proc_net); + proc_root_initialized = 1; + } + + pSkRootDir->owner = THIS_MODULE; + } + + + /* Create proc file */ + pProcFile = create_proc_entry(dev->name, + S_IFREG | S_IXUSR | S_IWGRP | S_IROTH, + pSkRootDir); + + + pProcFile->read_proc = proc_read; + pProcFile->write_proc = NULL; + pProcFile->nlink = 1; + pProcFile->size = sizeof(dev->name + 1); + pProcFile->data = (void *)pProcFile; +#endif + + pNet->PortNr = 0; + pNet->NetNr = 0; + +#ifdef SK_ZEROCOPY + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + /* SG and ZEROCOPY - fly baby... */ + dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; + } +#endif + + boards_found++; + + /* More then one port found */ + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) { +#if 0 + if ((dev = init_etherdev(NULL, sizeof(DEV_NET))) == 0) { + printk(KERN_ERR "Unable to allocate etherdev " + "structure!\n"); + break; + } +#else + dev = malloc (sizeof *dev); + memset(dev, 0, sizeof(*dev)); + dev->priv = malloc(sizeof(DEV_NET)); +#endif + + pAC->dev[1] = dev; + pNet = dev->priv; + pNet->PortNr = 1; + pNet->NetNr = 1; + pNet->pAC = pAC; + pNet->Mtu = 1500; + pNet->Up = 0; + +#if 0 + dev->open = &SkGeOpen; + dev->stop = &SkGeClose; + dev->hard_start_xmit = &SkGeXmit; + dev->get_stats = &SkGeStats; + dev->set_multicast_list = &SkGeSetRxMode; + dev->set_mac_address = &SkGeSetMacAddr; + dev->do_ioctl = &SkGeIoctl; + dev->change_mtu = &SkGeChangeMtu; + dev->flags &= ~IFF_RUNNING; +#endif + +#ifdef SK_ZEROCOPY + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + /* SG and ZEROCOPY - fly baby... */ + dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; + } +#endif + +#if 0 + pProcFile = create_proc_entry(dev->name, + S_IFREG | S_IXUSR | S_IWGRP | S_IROTH, + pSkRootDir); + + + pProcFile->read_proc = proc_read; + pProcFile->write_proc = NULL; + pProcFile->nlink = 1; + pProcFile->size = sizeof(dev->name + 1); + pProcFile->data = (void *)pProcFile; +#endif + +#if 0 + memcpy((caddr_t) &dev->dev_addr, + (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6); +#else + memcpy((caddr_t) &dev->enetaddr, + (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6); +#endif + + printk("%s: %s\n", dev->name, pAC->DeviceStr); + printk(" PrefPort:B RlmtMode:Dual Check Link State\n"); + + } + + + /* Save the hardware revision */ + pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) + + (pAC->GIni.GIPciHwRev & 0x0F); + + /* + * This is bollocks, but we need to tell the net-init + * code that it shall go for the next device. + */ +#if 0 +#ifndef MODULE + dev->base_addr = 0; +#endif +#endif + } + + /* + * If we're at this point we're going through skge_probe() for + * the first time. Return success (0) if we've initialized 1 + * or more boards. Otherwise, return failure (-ENODEV). + */ + + return boards_found; +} /* skge_probe */ + + +/***************************************************************************** + * + * FreeResources - release resources allocated for adapter + * + * Description: + * This function releases the IRQ, unmaps the IO and + * frees the desriptor ring. + * + * Returns: N/A + * + */ +static void FreeResources(struct SK_NET_DEVICE *dev) +{ +SK_U32 AllocFlag; +DEV_NET *pNet; +SK_AC *pAC; + + if (dev->priv) { + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + AllocFlag = pAC->AllocFlag; +#if 0 + if (AllocFlag & SK_ALLOC_IRQ) { + free_irq(dev->irq, dev); + } + if (pAC->IoBase) { + iounmap(pAC->IoBase); + } +#endif + if (pAC->pDescrMem) { + BoardFreeMem(pAC); + } + } + +} /* FreeResources */ + +#if 0 +MODULE_AUTHOR("Mirko Lindner "); +MODULE_DESCRIPTION("SysKonnect SK-NET Gigabit Ethernet SK-98xx driver"); +MODULE_LICENSE("GPL"); +MODULE_PARM(Speed_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(Speed_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(AutoNeg_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(AutoNeg_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(DupCap_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(DupCap_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(FlowCtrl_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(FlowCtrl_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(Role_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(Role_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(PrefPort, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +MODULE_PARM(RlmtMode, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s"); +/* not used, just there because every driver should have them: */ +MODULE_PARM(options, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i"); +MODULE_PARM(debug, "i"); +#endif + + +#ifdef LINK_SPEED_A +static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED_A; +#else +static char *Speed_A[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef LINK_SPEED_B +static char *Speed_B[SK_MAX_CARD_PARAM] = LINK_SPEED_B; +#else +static char *Speed_B[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef AUTO_NEG_A +static char *AutoNeg_A[SK_MAX_CARD_PARAM] = AUTO_NEG_A; +#else +static char *AutoNeg_A[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef DUP_CAP_A +static char *DupCap_A[SK_MAX_CARD_PARAM] = DUP_CAP_A; +#else +static char *DupCap_A[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef FLOW_CTRL_A +static char *FlowCtrl_A[SK_MAX_CARD_PARAM] = FLOW_CTRL_A; +#else +static char *FlowCtrl_A[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef ROLE_A +static char *Role_A[SK_MAX_CARD_PARAM] = ROLE_A; +#else +static char *Role_A[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef AUTO_NEG_B +static char *AutoNeg_B[SK_MAX_CARD_PARAM] = AUTO_NEG_B; +#else +static char *AutoNeg_B[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef DUP_CAP_B +static char *DupCap_B[SK_MAX_CARD_PARAM] = DUP_CAP_B; +#else +static char *DupCap_B[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef FLOW_CTRL_B +static char *FlowCtrl_B[SK_MAX_CARD_PARAM] = FLOW_CTRL_B; +#else +static char *FlowCtrl_B[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef ROLE_B +static char *Role_B[SK_MAX_CARD_PARAM] = ROLE_B; +#else +static char *Role_B[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef PREF_PORT +static char *PrefPort[SK_MAX_CARD_PARAM] = PREF_PORT; +#else +static char *PrefPort[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#ifdef RLMT_MODE +static char *RlmtMode[SK_MAX_CARD_PARAM] = RLMT_MODE; +#else +static char *RlmtMode[SK_MAX_CARD_PARAM] = {"", }; +#endif + +#if 0 +static int debug = 0; /* not used */ +static int options[SK_MAX_CARD_PARAM] = {0, }; /* not used */ + + +/***************************************************************************** + * + * skge_init_module - module initialization function + * + * Description: + * Very simple, only call skge_probe and return approriate result. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int __init skge_init_module(void) +{ + int cards; + SkGeRootDev = NULL; + + /* just to avoid warnings ... */ + debug = 0; + options[0] = 0; + + cards = skge_probe(); + if (cards == 0) { + printk("sk98lin: No adapter found.\n"); + } + return cards ? 0 : -ENODEV; +} /* skge_init_module */ + + +/***************************************************************************** + * + * skge_cleanup_module - module unload function + * + * Description: + * Disable adapter if it is still running, free resources, + * free device struct. + * + * Returns: N/A + */ +static void __exit skge_cleanup_module(void) +{ +DEV_NET *pNet; +SK_AC *pAC; +struct SK_NET_DEVICE *next; +unsigned long Flags; +SK_EVPARA EvPara; + + while (SkGeRootDev) { + pNet = (DEV_NET*) SkGeRootDev->priv; + pAC = pNet->pAC; + next = pAC->Next; + + netif_stop_queue(SkGeRootDev); + SkGeYellowLED(pAC, pAC->IoBase, 0); + + if(pAC->BoardLevel == 2) { + /* board is still alive */ + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + EvPara.Para32[0] = 0; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + EvPara.Para32[0] = 1; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + SkGeDeInit(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + pAC->BoardLevel = 0; + /* We do NOT check here, if IRQ was pending, of course*/ + } + + if(pAC->BoardLevel == 1) { + /* board is still alive */ + SkGeDeInit(pAC, pAC->IoBase); + pAC->BoardLevel = 0; + } + + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){ + unregister_netdev(pAC->dev[1]); + kfree(pAC->dev[1]); + } + + FreeResources(SkGeRootDev); + + SkGeRootDev->get_stats = NULL; + /* + * otherwise unregister_netdev calls get_stats with + * invalid IO ... :-( + */ + unregister_netdev(SkGeRootDev); + kfree(SkGeRootDev); + kfree(pAC); + SkGeRootDev = next; + } + + /* clear proc-dir */ + remove_proc_entry(pSkRootDir->name, proc_net); + +} /* skge_cleanup_module */ + +module_init(skge_init_module); +module_exit(skge_cleanup_module); +#endif + + +/***************************************************************************** + * + * SkGeBoardInit - do level 0 and 1 initialization + * + * Description: + * This function prepares the board hardware for running. The desriptor + * ring is set up, the IRQ is allocated and the configuration settings + * are examined. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int __init SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC) +{ +short i; +unsigned long Flags; +char *DescrString = "sk98lin: Driver for Linux"; /* this is given to PNMI */ +char *VerStr = VER_STRING; +#if 0 +int Ret; /* return code of request_irq */ +#endif +SK_BOOL DualNet; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("IoBase: %08lX\n", (unsigned long)pAC->IoBase)); + for (i=0; iTxPort[i][0].HwAddr = pAC->IoBase + TxQueueAddr[i][0]; + pAC->TxPort[i][0].PortIndex = i; + pAC->RxPort[i].HwAddr = pAC->IoBase + RxQueueAddr[i]; + pAC->RxPort[i].PortIndex = i; + } + + /* Initialize the mutexes */ + for (i=0; iTxPort[i][0].TxDesRingLock); + spin_lock_init(&pAC->RxPort[i].RxDesRingLock); + } + spin_lock_init(&pAC->SlowPathLock); + + /* level 0 init common modules here */ + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + /* Does a RESET on board ...*/ + if (SkGeInit(pAC, pAC->IoBase, 0) != 0) { + printk("HWInit (0) failed.\n"); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + return(-EAGAIN); + } + SkI2cInit( pAC, pAC->IoBase, 0); + SkEventInit(pAC, pAC->IoBase, 0); + SkPnmiInit( pAC, pAC->IoBase, 0); + SkAddrInit( pAC, pAC->IoBase, 0); + SkRlmtInit( pAC, pAC->IoBase, 0); + SkTimerInit(pAC, pAC->IoBase, 0); + + pAC->BoardLevel = 0; + pAC->RxBufSize = ETH_BUF_SIZE; + + SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString); + SK_PNMI_SET_DRIVER_VER(pAC, VerStr); + + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + /* level 1 init common modules here (HW init) */ + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + if (SkGeInit(pAC, pAC->IoBase, 1) != 0) { + printk("HWInit (1) failed.\n"); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + return(-EAGAIN); + } + SkI2cInit( pAC, pAC->IoBase, 1); + SkEventInit(pAC, pAC->IoBase, 1); + SkPnmiInit( pAC, pAC->IoBase, 1); + SkAddrInit( pAC, pAC->IoBase, 1); + SkRlmtInit( pAC, pAC->IoBase, 1); + SkTimerInit(pAC, pAC->IoBase, 1); + + GetConfiguration(pAC); + if (pAC->RlmtNets == 2) { + pAC->GIni.GIPortUsage = SK_MUL_LINK; + } + + pAC->BoardLevel = 1; + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + +#if 0 + if (pAC->GIni.GIMacsFound == 2) { + Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, pAC->Name, dev); + } else if (pAC->GIni.GIMacsFound == 1) { + Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, + pAC->Name, dev); + } else { + printk(KERN_WARNING "%s: Illegal number of ports: %d\n", + dev->name, pAC->GIni.GIMacsFound); + return -EAGAIN; + } + + if (Ret) { + printk(KERN_WARNING "%s: Requested IRQ %d is busy.\n", + dev->name, dev->irq); + return -EAGAIN; + } +#endif + pAC->AllocFlag |= SK_ALLOC_IRQ; + + /* Alloc memory for this board (Mem for RxD/TxD) : */ + if(!BoardAllocMem(pAC)) { + printk("No memory for descriptor rings.\n"); + return(-EAGAIN); + } + + SkCsSetReceiveFlags(pAC, + SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP, + &pAC->CsOfs1, &pAC->CsOfs2, 0); + pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1; + + BoardInitMem(pAC); +#if 0 + SetQueueSizes(pAC); +#else + /* tschilling: New common function with minimum size check. */ + DualNet = SK_FALSE; + if (pAC->RlmtNets == 2) { + DualNet = SK_TRUE; + } + + if (SkGeInitAssignRamToQueues( + pAC, + pAC->ActivePort, + DualNet)) { + BoardFreeMem(pAC); + printk("SkGeInitAssignRamToQueues failed.\n"); + return(-EAGAIN); + } +#endif + + /* Print adapter specific string from vpd */ + ProductStr(pAC); +#ifdef SK98_INFO + printk("%s: %s\n", dev->name, pAC->DeviceStr); + + /* Print configuration settings */ + printk(" PrefPort:%c RlmtMode:%s\n", + 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber, + (pAC->RlmtMode==0) ? "Check Link State" : + ((pAC->RlmtMode==1) ? "Check Link State" : + ((pAC->RlmtMode==3) ? "Check Local Port" : + ((pAC->RlmtMode==7) ? "Check Segmentation" : + ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error"))))); +#endif + + SkGeYellowLED(pAC, pAC->IoBase, 1); + + /* + * Register the device here + */ + pAC->Next = SkGeRootDev; + SkGeRootDev = dev; + + return (0); +} /* SkGeBoardInit */ + + +/***************************************************************************** + * + * BoardAllocMem - allocate the memory for the descriptor rings + * + * Description: + * This function allocates the memory for all descriptor rings. + * Each ring is aligned for the desriptor alignment and no ring + * has a 4 GByte boundary in it (because the upper 32 bit must + * be constant for all descriptiors in one rings). + * + * Returns: + * SK_TRUE, if all memory could be allocated + * SK_FALSE, if not + */ +static SK_BOOL BoardAllocMem( +SK_AC *pAC) +{ +caddr_t pDescrMem; /* pointer to descriptor memory area */ +size_t AllocLength; /* length of complete descriptor area */ +int i; /* loop counter */ +unsigned long BusAddr; + + + /* rings plus one for alignment (do not cross 4 GB boundary) */ + /* RX_RING_SIZE is assumed bigger than TX_RING_SIZE */ +#if (BITS_PER_LONG == 32) + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8; +#else + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + + RX_RING_SIZE + 8; +#endif + + pDescrMem = pci_alloc_consistent(pAC->PciDev, AllocLength, + &pAC->pDescrMemDMA); + + if (pDescrMem == NULL) { + return (SK_FALSE); + } + pAC->pDescrMem = pDescrMem; + BusAddr = (unsigned long) pAC->pDescrMemDMA; + + /* Descriptors need 8 byte alignment, and this is ensured + * by pci_alloc_consistent. + */ + for (i=0; iGIni.GIMacsFound; i++) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("TX%d/A: pDescrMem: %lX, PhysDescrMem: %lX\n", + i, (unsigned long) pDescrMem, + BusAddr)); + pAC->TxPort[i][0].pTxDescrRing = pDescrMem; + pAC->TxPort[i][0].VTxDescrRing = BusAddr; + pDescrMem += TX_RING_SIZE; + BusAddr += TX_RING_SIZE; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("RX%d: pDescrMem: %lX, PhysDescrMem: %lX\n", + i, (unsigned long) pDescrMem, + (unsigned long)BusAddr)); + pAC->RxPort[i].pRxDescrRing = pDescrMem; + pAC->RxPort[i].VRxDescrRing = BusAddr; + pDescrMem += RX_RING_SIZE; + BusAddr += RX_RING_SIZE; + } /* for */ + + return (SK_TRUE); +} /* BoardAllocMem */ + + +/**************************************************************************** + * + * BoardFreeMem - reverse of BoardAllocMem + * + * Description: + * Free all memory allocated in BoardAllocMem: adapter context, + * descriptor rings, locks. + * + * Returns: N/A + */ +static void BoardFreeMem( +SK_AC *pAC) +{ +size_t AllocLength; /* length of complete descriptor area */ + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("BoardFreeMem\n")); +#if (BITS_PER_LONG == 32) + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8; +#else + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + + RX_RING_SIZE + 8; +#endif + + pci_free_consistent(pAC->PciDev, AllocLength, + pAC->pDescrMem, pAC->pDescrMemDMA); + pAC->pDescrMem = NULL; +} /* BoardFreeMem */ + + +/***************************************************************************** + * + * BoardInitMem - initiate the descriptor rings + * + * Description: + * This function sets the descriptor rings up in memory. + * The adapter is initialized with the descriptor start addresses. + * + * Returns: N/A + */ +static void BoardInitMem( +SK_AC *pAC) /* pointer to adapter context */ +{ +int i; /* loop counter */ +int RxDescrSize; /* the size of a rx descriptor rounded up to alignment*/ +int TxDescrSize; /* the size of a tx descriptor rounded up to alignment*/ + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("BoardInitMem\n")); + + RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; + pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize; + TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN; + pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize; + + for (i=0; iGIni.GIMacsFound; i++) { + SetupRing( + pAC, + pAC->TxPort[i][0].pTxDescrRing, + pAC->TxPort[i][0].VTxDescrRing, + (RXD**)&pAC->TxPort[i][0].pTxdRingHead, + (RXD**)&pAC->TxPort[i][0].pTxdRingTail, + (RXD**)&pAC->TxPort[i][0].pTxdRingPrev, + &pAC->TxPort[i][0].TxdRingFree, + SK_TRUE); + SetupRing( + pAC, + pAC->RxPort[i].pRxDescrRing, + pAC->RxPort[i].VRxDescrRing, + &pAC->RxPort[i].pRxdRingHead, + &pAC->RxPort[i].pRxdRingTail, + &pAC->RxPort[i].pRxdRingPrev, + &pAC->RxPort[i].RxdRingFree, + SK_FALSE); + } +} /* BoardInitMem */ + + +/***************************************************************************** + * + * SetupRing - create one descriptor ring + * + * Description: + * This function creates one descriptor ring in the given memory area. + * The head, tail and number of free descriptors in the ring are set. + * + * Returns: + * none + */ +static void SetupRing( +SK_AC *pAC, +void *pMemArea, /* a pointer to the memory area for the ring */ +uintptr_t VMemArea, /* the virtual bus address of the memory area */ +RXD **ppRingHead, /* address where the head should be written */ +RXD **ppRingTail, /* address where the tail should be written */ +RXD **ppRingPrev, /* address where the tail should be written */ +int *pRingFree, /* address where the # of free descr. goes */ +SK_BOOL IsTx) /* flag: is this a tx ring */ +{ +int i; /* loop counter */ +int DescrSize; /* the size of a descriptor rounded up to alignment*/ +int DescrNum; /* number of descriptors per ring */ +RXD *pDescr; /* pointer to a descriptor (receive or transmit) */ +RXD *pNextDescr; /* pointer to the next descriptor */ +RXD *pPrevDescr; /* pointer to the previous descriptor */ +uintptr_t VNextDescr; /* the virtual bus address of the next descriptor */ + + if (IsTx == SK_TRUE) { + DescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * + DESCR_ALIGN; + DescrNum = TX_RING_SIZE / DescrSize; + } else { + DescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * + DESCR_ALIGN; + DescrNum = RX_RING_SIZE / DescrSize; + } + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("Descriptor size: %d Descriptor Number: %d\n", + DescrSize,DescrNum)); + + pDescr = (RXD*) pMemArea; + pPrevDescr = NULL; + pNextDescr = (RXD*) (((char*)pDescr) + DescrSize); + VNextDescr = VMemArea + DescrSize; + for(i=0; iVNextRxd = VNextDescr & 0xffffffffULL; + pDescr->pNextRxd = pNextDescr; + pDescr->TcpSumStarts = pAC->CsOfs; + + /* advance one step */ + pPrevDescr = pDescr; + pDescr = pNextDescr; + pNextDescr = (RXD*) (((char*)pDescr) + DescrSize); + VNextDescr += DescrSize; + } + pPrevDescr->pNextRxd = (RXD*) pMemArea; + pPrevDescr->VNextRxd = VMemArea; + pDescr = (RXD*) pMemArea; + *ppRingHead = (RXD*) pMemArea; + *ppRingTail = *ppRingHead; + *ppRingPrev = pPrevDescr; + *pRingFree = DescrNum; +} /* SetupRing */ + + +/***************************************************************************** + * + * PortReInitBmu - re-initiate the descriptor rings for one port + * + * Description: + * This function reinitializes the descriptor rings of one port + * in memory. The port must be stopped before. + * The HW is initialized with the descriptor start addresses. + * + * Returns: + * none + */ +static void PortReInitBmu( +SK_AC *pAC, /* pointer to adapter context */ +int PortIndex) /* index of the port for which to re-init */ +{ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("PortReInitBmu ")); + + /* set address of first descriptor of ring in BMU */ + SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+ + TX_Q_CUR_DESCR_LOW, + (uint32_t)(((caddr_t) + (pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxdRingHead) - + pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxDescrRing + + pAC->TxPort[PortIndex][TX_PRIO_LOW].VTxDescrRing) & + 0xFFFFFFFF)); + SK_OUT32(pAC->IoBase, TxQueueAddr[PortIndex][TX_PRIO_LOW]+ + TX_Q_DESCR_HIGH, + (uint32_t)(((caddr_t) + (pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxdRingHead) - + pAC->TxPort[PortIndex][TX_PRIO_LOW].pTxDescrRing + + pAC->TxPort[PortIndex][TX_PRIO_LOW].VTxDescrRing) >> 32)); + SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_CUR_DESCR_LOW, + (uint32_t)(((caddr_t)(pAC->RxPort[PortIndex].pRxdRingHead) - + pAC->RxPort[PortIndex].pRxDescrRing + + pAC->RxPort[PortIndex].VRxDescrRing) & 0xFFFFFFFF)); + SK_OUT32(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_DESCR_HIGH, + (uint32_t)(((caddr_t)(pAC->RxPort[PortIndex].pRxdRingHead) - + pAC->RxPort[PortIndex].pRxDescrRing + + pAC->RxPort[PortIndex].VRxDescrRing) >> 32)); +} /* PortReInitBmu */ + + +/**************************************************************************** + * + * SkGeIsr - handle adapter interrupts + * + * Description: + * The interrupt routine is called when the network adapter + * generates an interrupt. It may also be called if another device + * shares this interrupt vector with the driver. + * + * Returns: N/A + * + */ +#if 0 +static void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs) +#else +void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs) +#endif +{ +struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id; +DEV_NET *pNet; +SK_AC *pAC; +SK_U32 IntSrc; /* interrupts source register contents */ + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + /* + * Check and process if its our interrupt + */ + SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc); + if (IntSrc == 0) { + return; + } + + while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) { +#if 0 /* software irq currently not used */ + if (IntSrc & IRQ_SW) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("Software IRQ\n")); + } +#endif + if (IntSrc & IRQ_EOF_RX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF RX1 IRQ\n")); + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + SK_PNMI_CNT_RX_INTR(pAC, 0); + } + if (IntSrc & IRQ_EOF_RX2) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF RX2 IRQ\n")); + ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE); + SK_PNMI_CNT_RX_INTR(pAC, 1); + } +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IRQ_EOF_AS_TX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF AS TX1 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 0); + spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]); + spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + } + if (IntSrc & IRQ_EOF_AS_TX2) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF AS TX2 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 1); + spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); + FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]); + spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock); + } +#if 0 /* only if sync. queues used */ + if (IntSrc & IRQ_EOF_SY_TX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF SY TX1 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 1); + spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); + FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH); + spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); + ClearTxIrq(pAC, 0, TX_PRIO_HIGH); + } + if (IntSrc & IRQ_EOF_SY_TX2) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF SY TX2 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 1); + spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock); + FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH); + spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock); + ClearTxIrq(pAC, 1, TX_PRIO_HIGH); + } +#endif +#endif + + /* do all IO at once */ + if (IntSrc & IRQ_EOF_RX1) + ClearAndStartRx(pAC, 0); + if (IntSrc & IRQ_EOF_RX2) + ClearAndStartRx(pAC, 1); +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IRQ_EOF_AS_TX1) + ClearTxIrq(pAC, 0, TX_PRIO_LOW); + if (IntSrc & IRQ_EOF_AS_TX2) + ClearTxIrq(pAC, 1, TX_PRIO_LOW); +#endif + SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc); + } /* while (IntSrc & IRQ_MASK != 0) */ + + if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("SPECIAL IRQ DP-Cards => %x\n", IntSrc)); + pAC->CheckQueue = SK_FALSE; + spin_lock(&pAC->SlowPathLock); + if (IntSrc & SPECIAL_IRQS) + SkGeSirqIsr(pAC, pAC->IoBase, IntSrc); + + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock(&pAC->SlowPathLock); + } + /* + * do it all again is case we cleared an interrupt that + * came in after handling the ring (OUTs may be delayed + * in hardware buffers, but are through after IN) + */ + + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE); + + if (pAC->CheckQueue) { + pAC->CheckQueue = SK_FALSE; + spin_lock(&pAC->SlowPathLock); + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock(&pAC->SlowPathLock); + } + + + /* IRQ is processed - Enable IRQs again*/ + SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + + return; +} /* SkGeIsr */ + + +/**************************************************************************** + * + * SkGeIsrOnePort - handle adapter interrupts for single port adapter + * + * Description: + * The interrupt routine is called when the network adapter + * generates an interrupt. It may also be called if another device + * shares this interrupt vector with the driver. + * This is the same as above, but handles only one port. + * + * Returns: N/A + * + */ +#if 0 +static void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs) +#else +void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs) +#endif +{ +struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id; +DEV_NET *pNet; +SK_AC *pAC; +SK_U32 IntSrc; /* interrupts source register contents */ + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + /* + * Check and process if its our interrupt + */ + SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc); + if (IntSrc == 0) { + return; + } + + while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) { +#if 0 /* software irq currently not used */ + if (IntSrc & IRQ_SW) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("Software IRQ\n")); + } +#endif + if (IntSrc & IRQ_EOF_RX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF RX1 IRQ\n")); + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + SK_PNMI_CNT_RX_INTR(pAC, 0); + } +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IRQ_EOF_AS_TX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF AS TX1 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 0); + spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]); + spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock); + } +#if 0 /* only if sync. queues used */ + if (IntSrc & IRQ_EOF_SY_TX1) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_INT_SRC, + ("EOF SY TX1 IRQ\n")); + SK_PNMI_CNT_TX_INTR(pAC, 0); + spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); + FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH); + spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock); + ClearTxIrq(pAC, 0, TX_PRIO_HIGH); + } +#endif +#endif + + /* do all IO at once */ + if (IntSrc & IRQ_EOF_RX1) + ClearAndStartRx(pAC, 0); +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */ + if (IntSrc & IRQ_EOF_AS_TX1) + ClearTxIrq(pAC, 0, TX_PRIO_LOW); +#endif + SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc); + } /* while (IntSrc & IRQ_MASK != 0) */ + + if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC, + ("SPECIAL IRQ SP-Cards => %x\n", IntSrc)); + pAC->CheckQueue = SK_FALSE; + spin_lock(&pAC->SlowPathLock); + if (IntSrc & SPECIAL_IRQS) + SkGeSirqIsr(pAC, pAC->IoBase, IntSrc); + + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock(&pAC->SlowPathLock); + } + /* + * do it all again is case we cleared an interrupt that + * came in after handling the ring (OUTs may be delayed + * in hardware buffers, but are through after IN) + */ + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE); + + /* IRQ is processed - Enable IRQs again*/ + SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + + return; +} /* SkGeIsrOnePort */ + + +/**************************************************************************** + * + * SkGeOpen - handle start of initialized adapter + * + * Description: + * This function starts the initialized adapter. + * The board level variable is set and the adapter is + * brought to full functionality. + * The device flags are set for operation. + * Do all necessary level 2 initialization, enable interrupts and + * give start command to RLMT. + * + * Returns: + * 0 on success + * != 0 on error + */ +#if 0 +static int SkGeOpen( +#else +int SkGeOpen( +#endif +struct SK_NET_DEVICE *dev) +{ + DEV_NET *pNet; + SK_AC *pAC; + unsigned long Flags; /* for spin lock */ + int i; + SK_EVPARA EvPara; /* an event parameter union */ + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC)); + + if (pAC->BoardLevel == 0) { + /* level 1 init common modules here */ + if (SkGeInit(pAC, pAC->IoBase, 1) != 0) { + printk("%s: HWInit (1) failed.\n", pAC->dev[pNet->PortNr]->name); + return (-1); + } + SkI2cInit (pAC, pAC->IoBase, 1); + SkEventInit (pAC, pAC->IoBase, 1); + SkPnmiInit (pAC, pAC->IoBase, 1); + SkAddrInit (pAC, pAC->IoBase, 1); + SkRlmtInit (pAC, pAC->IoBase, 1); + SkTimerInit (pAC, pAC->IoBase, 1); + pAC->BoardLevel = 1; + } + + if (pAC->BoardLevel != 2) { + /* tschilling: Level 2 init modules here, check return value. */ + if (SkGeInit(pAC, pAC->IoBase, 2) != 0) { + printk("%s: HWInit (2) failed.\n", pAC->dev[pNet->PortNr]->name); + return (-1); + } + SkI2cInit (pAC, pAC->IoBase, 2); + SkEventInit (pAC, pAC->IoBase, 2); + SkPnmiInit (pAC, pAC->IoBase, 2); + SkAddrInit (pAC, pAC->IoBase, 2); + SkRlmtInit (pAC, pAC->IoBase, 2); + SkTimerInit (pAC, pAC->IoBase, 2); + pAC->BoardLevel = 2; + } + + for (i=0; iGIni.GIMacsFound; i++) { + /* Enable transmit descriptor polling. */ + SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE); + FillRxRing(pAC, &pAC->RxPort[i]); + } + SkGeYellowLED(pAC, pAC->IoBase, 1); + +#ifdef USE_INT_MOD +/* moderate only TX complete interrupts (these are not time critical) */ +#define IRQ_MOD_MASK (IRQ_EOF_AS_TX1 | IRQ_EOF_AS_TX2) + { + unsigned long ModBase; + ModBase = 53125000 / INTS_PER_SEC; + SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase); + SK_OUT32(pAC->IoBase, B2_IRQM_MSK, IRQ_MOD_MASK); + SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START); + } +#endif + + /* enable Interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK); + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + + if ((pAC->RlmtMode != 0) && (pAC->MaxPorts == 0)) { + EvPara.Para32[0] = pAC->RlmtNets; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, + EvPara); + EvPara.Para32[0] = pAC->RlmtMode; + EvPara.Para32[1] = 0; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE, + EvPara); + } + + EvPara.Para32[0] = pNet->NetNr; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + pAC->MaxPorts++; + pNet->Up = 1; + + MOD_INC_USE_COUNT; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeOpen suceeded\n")); + + return (0); +} /* SkGeOpen */ + + +/**************************************************************************** + * + * SkGeClose - Stop initialized adapter + * + * Description: + * Close initialized adapter. + * + * Returns: + * 0 - on success + * error code - on error + */ +#if 0 +static int SkGeClose( +#else +int SkGeClose( +#endif +struct SK_NET_DEVICE *dev) +{ + DEV_NET *pNet; + SK_AC *pAC; + + unsigned long Flags; /* for spin lock */ + int i; + int PortIdx; + SK_EVPARA EvPara; + + netif_stop_queue(dev); + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + if (pAC->RlmtNets == 1) + PortIdx = pAC->ActivePort; + else + PortIdx = pNet->NetNr; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC)); + + /* + * Clear multicast table, promiscuous mode .... + */ + SkAddrMcClear(pAC, pAC->IoBase, PortIdx, 0); + SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx, + SK_PROM_MODE_NONE); + + if (pAC->MaxPorts == 1) { + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + EvPara.Para32[0] = pNet->NetNr; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + /* stop the hardware */ + SkGeDeInit(pAC, pAC->IoBase); + pAC->BoardLevel = 0; + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + } else { + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + EvPara.Para32[0] = pNet->NetNr; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + /* Stop port */ + spin_lock_irqsave(&pAC->TxPort[pNet->PortNr] + [TX_PRIO_LOW].TxDesRingLock, Flags); + SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, + SK_STOP_ALL, SK_HARD_RST); + spin_unlock_irqrestore(&pAC->TxPort[pNet->PortNr] + [TX_PRIO_LOW].TxDesRingLock, Flags); + } + + if (pAC->RlmtNets == 1) { + /* clear all descriptor rings */ + for (i=0; iGIni.GIMacsFound; i++) { + ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE); + ClearRxRing(pAC, &pAC->RxPort[i]); + ClearTxRing(pAC, &pAC->TxPort[i][TX_PRIO_LOW]); + } + } else { + /* clear port descriptor rings */ + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE); + ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]); + ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]); + } + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeClose: done ")); + + pAC->MaxPorts--; + pNet->Up = 0; + MOD_DEC_USE_COUNT; + + return (0); +} /* SkGeClose */ + + +/***************************************************************************** + * + * SkGeXmit - Linux frame transmit function + * + * Description: + * The system calls this function to send frames onto the wire. + * It puts the frame in the tx descriptor ring. If the ring is + * full then, the 'tbusy' flag is set. + * + * Returns: + * 0, if everything is ok + * !=0, on error + * WARNING: returning 1 in 'tbusy' case caused system crashes (double + * allocated skb's) !!! + */ +#if 0 +static int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev) +#else +int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev) +#endif +{ +DEV_NET *pNet; +SK_AC *pAC; +int Rc; /* return code of XmitFrame */ + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + +#if 0 + if ((!skb_shinfo(skb)->nr_frags) || +#else + if (1 || +#endif + (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) { + /* Don't activate scatter-gather and hardware checksum */ + + if (pAC->RlmtNets == 2) + Rc = XmitFrame( + pAC, + &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW], + skb); + else + Rc = XmitFrame( + pAC, + &pAC->TxPort[pAC->ActivePort][TX_PRIO_LOW], + skb); + } else { +#if 0 + /* scatter-gather and hardware TCP checksumming anabled*/ + if (pAC->RlmtNets == 2) + Rc = XmitFrameSG( + pAC, + &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW], + skb); + else + Rc = XmitFrameSG( + pAC, + &pAC->TxPort[pAC->ActivePort][TX_PRIO_LOW], + skb); +#endif + } + + /* Transmitter out of resources? */ + if (Rc <= 0) { + netif_stop_queue(dev); + } + + /* If not taken, give buffer ownership back to the + * queueing layer. + */ + if (Rc < 0) + return (1); + +#if 0 + dev->trans_start = jiffies; +#endif + return (0); +} /* SkGeXmit */ + + +/***************************************************************************** + * + * XmitFrame - fill one socket buffer into the transmit ring + * + * Description: + * This function puts a message into the transmit descriptor ring + * if there is a descriptors left. + * Linux skb's consist of only one continuous buffer. + * The first step locks the ring. It is held locked + * all time to avoid problems with SWITCH_../PORT_RESET. + * Then the descriptoris allocated. + * The second part is linking the buffer to the descriptor. + * At the very last, the Control field of the descriptor + * is made valid for the BMU and a start TX command is given + * if necessary. + * + * Returns: + * > 0 - on succes: the number of bytes in the message + * = 0 - on resource shortage: this frame sent or dropped, now + * the ring is full ( -> set tbusy) + * < 0 - on failure: other problems ( -> return failure to upper layers) + */ +static int XmitFrame( +SK_AC *pAC, /* pointer to adapter context */ +TX_PORT *pTxPort, /* pointer to struct of port to send to */ +struct sk_buff *pMessage) /* pointer to send-message */ +{ +TXD *pTxd; /* the rxd to fill */ +unsigned long Flags; +SK_U64 PhysAddr; +int BytesSend; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("X")); + + spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags); +#ifndef USE_TX_COMPLETE + FreeTxDescriptors(pAC, pTxPort); +#endif + if (pTxPort->TxdRingFree == 0) { + /* no enough free descriptors in ring at the moment */ + FreeTxDescriptors(pAC, pTxPort); + if (pTxPort->TxdRingFree == 0) { + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); + SK_PNMI_CNT_NO_TX_BUF(pAC, pTxPort->PortIndex); + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_TX_PROGRESS, + ("XmitFrame failed\n")); + /* this message can not be sent now */ + /* Because tbusy seems to be set, the message should not be freed here */ + /* It will be used by the scheduler of the ethernet handler */ + return (-1); + } + } + /* advance head counter behind descriptor needed for this frame */ + pTxd = pTxPort->pTxdRingHead; + pTxPort->pTxdRingHead = pTxd->pNextTxd; + pTxPort->TxdRingFree--; + /* the needed descriptor is reserved now */ + + /* + * everything allocated ok, so add buffer to descriptor + */ + +#ifdef SK_DUMP_TX + DumpMsg(pMessage, "XmitFrame"); +#endif + + /* set up descriptor and CONTROL dword */ +#if 0 + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + virt_to_page(pMessage->data), + ((unsigned long) pMessage->data & + ~PAGE_MASK), + pMessage->len, + PCI_DMA_TODEVICE); +#else + PhysAddr = (SK_U64) pci_phys_to_mem(pAC->PciDev, (u32) pMessage->data); +#endif + pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32); + pTxd->pMBuf = pMessage; + pTxd->TBControl = TX_CTRL_OWN_BMU | TX_CTRL_STF | + TX_CTRL_CHECK_DEFAULT | TX_CTRL_SOFTWARE | +#ifdef USE_TX_COMPLETE + TX_CTRL_EOF | TX_CTRL_EOF_IRQ | pMessage->len; +#else + TX_CTRL_EOF | pMessage->len; +#endif + + if ((pTxPort->pTxdRingPrev->TBControl & TX_CTRL_OWN_BMU) == 0) { + /* previous descriptor already done, so give tx start cmd */ + /* StartTx(pAC, pTxPort->HwAddr); */ + SK_OUT8(pTxPort->HwAddr, TX_Q_CTRL, TX_Q_CTRL_START); + } + pTxPort->pTxdRingPrev = pTxd; + + + BytesSend = pMessage->len; + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); + /* after releasing the lock, the skb may be immidiately freed */ + if (pTxPort->TxdRingFree != 0) + return (BytesSend); + else + return (0); + +} /* XmitFrame */ + +/***************************************************************************** + * + * XmitFrameSG - fill one socket buffer into the transmit ring + * (use SG and TCP/UDP hardware checksumming) + * + * Description: + * This function puts a message into the transmit descriptor ring + * if there is a descriptors left. + * + * Returns: + * > 0 - on succes: the number of bytes in the message + * = 0 - on resource shortage: this frame sent or dropped, now + * the ring is full ( -> set tbusy) + * < 0 - on failure: other problems ( -> return failure to upper layers) + */ +#if 0 +static int XmitFrameSG( +SK_AC *pAC, /* pointer to adapter context */ +TX_PORT *pTxPort, /* pointer to struct of port to send to */ +struct sk_buff *pMessage) /* pointer to send-message */ +{ + + int i; + int BytesSend; + int hlength; + int protocol; + skb_frag_t *sk_frag; + TXD *pTxd; + TXD *pTxdFst; + TXD *pTxdLst; + SK_U64 PhysAddr; + unsigned long Flags; + + spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags); +#ifndef USE_TX_COMPLETE + FreeTxDescriptors(pAC, pTxPort); +#endif + if ((skb_shinfo(pMessage)->nr_frags +1) > pTxPort->TxdRingFree) { + FreeTxDescriptors(pAC, pTxPort); + if ((skb_shinfo(pMessage)->nr_frags + 1) > pTxPort->TxdRingFree) { + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); + SK_PNMI_CNT_NO_TX_BUF(pAC, pTxPort->PortIndex); + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_TX_PROGRESS, + ("XmitFrameSG failed - Ring full\n")); + /* this message can not be sent now */ + return(-1); + } + } + + + pTxd = pTxPort->pTxdRingHead; + pTxdFst = pTxd; + pTxdLst = pTxd; + BytesSend = 0; + protocol = 0; + + /* map first fragment (header) */ + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + virt_to_page(pMessage->data), + ((unsigned long) pMessage->data & ~PAGE_MASK), + skb_headlen(pMessage), + PCI_DMA_TODEVICE); + + pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32); + + /* HW checksum? */ + if (pMessage->ip_summed == CHECKSUM_HW) { + pTxd->TBControl = TX_CTRL_STF | + TX_CTRL_ST_FWD | + skb_headlen(pMessage); + + /* We have to use the opcode for tcp here because the opcode for + udp is not working in the hardware yet (revision 2.0)*/ + protocol = ((SK_U8)pMessage->data[23] & 0xf); + if ((protocol == 17) && (pAC->GIni.GIChipRev != 0)) + pTxd->TBControl |= BMU_UDP_CHECK; + else + pTxd->TBControl |= BMU_TCP_CHECK ; + + hlength = ((SK_U8)pMessage->data[14] & 0xf) * 4; + pTxd->TcpSumOfs = 0; /* PH-Checksum already claculated */ + pTxd->TcpSumSt = 14+hlength+16; + pTxd->TcpSumWr = 14+hlength; + + } else { + pTxd->TBControl = TX_CTRL_CHECK_DEFAULT | + TX_CTRL_SOFTWARE | + TX_CTRL_STF | + skb_headlen(pMessage); + } + + pTxd = pTxd->pNextTxd; + pTxPort->TxdRingFree--; + BytesSend += skb_headlen(pMessage); + + + /* Map SG fragments */ + for (i = 0; i < skb_shinfo(pMessage)->nr_frags; i++) { + sk_frag = &skb_shinfo(pMessage)->frags[i]; + + /* we already have the proper value in entry */ + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + sk_frag->page, + sk_frag->page_offset, + sk_frag->size, + PCI_DMA_TODEVICE); + + pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32); + pTxd->pMBuf = pMessage; + + /* HW checksum */ + if (pMessage->ip_summed == CHECKSUM_HW) { + pTxd->TBControl = TX_CTRL_OWN_BMU | + TX_CTRL_SOFTWARE | + TX_CTRL_ST_FWD; + + /* We have to use the opcode for tcp here because the opcode for + udp is not working in the hardware yet (revision 2.0)*/ + if ((protocol == 17) && (pAC->GIni.GIChipRev != 0)) + pTxd->TBControl |= BMU_UDP_CHECK ; + else + pTxd->TBControl |= BMU_TCP_CHECK ; + + } else { + pTxd->TBControl = TX_CTRL_CHECK_DEFAULT | + TX_CTRL_SOFTWARE | + TX_CTRL_OWN_BMU; + } + + /* Last fragment */ + if( (i+1) == skb_shinfo(pMessage)->nr_frags ) { +#ifdef USE_TX_COMPLETE + pTxd->TBControl |= TX_CTRL_EOF | + TX_CTRL_EOF_IRQ | + sk_frag->size; +#else + pTxd->TBControl |= TX_CTRL_EOF | + sk_frag->size; +#endif + pTxdFst->TBControl |= TX_CTRL_OWN_BMU | + TX_CTRL_SOFTWARE; + + } else { + pTxd->TBControl |= sk_frag->size; + } + pTxdLst = pTxd; + pTxd = pTxd->pNextTxd; + pTxPort->TxdRingFree--; + BytesSend += sk_frag->size; + } + + if ((pTxPort->pTxdRingPrev->TBControl & TX_CTRL_OWN_BMU) == 0) { + /* previous descriptor already done, so give tx start cmd */ + /* StartTx(pAC, pTxPort->HwAddr); */ + SK_OUT8(pTxPort->HwAddr, TX_Q_CTRL, TX_Q_CTRL_START); + } + + pTxPort->pTxdRingPrev = pTxdLst; + pTxPort->pTxdRingHead = pTxd; + + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); + + if (pTxPort->TxdRingFree > 0) + return (BytesSend); + else + return (0); +} +#endif + + +void dump_frag( SK_U8 *data, int length) +{ + int i; + + printk("Length: %d\n", length); + for( i=0; i < length; i++ ) { + printk(" %02x", (SK_U8)*(data + i) ); + if( !((i+1) % 20) ) + printk("\n"); + } + printk("\n\n"); + +} + + +/***************************************************************************** + * + * FreeTxDescriptors - release descriptors from the descriptor ring + * + * Description: + * This function releases descriptors from a transmit ring if they + * have been sent by the BMU. + * If a descriptors is sent, it can be freed and the message can + * be freed, too. + * The SOFTWARE controllable bit is used to prevent running around a + * completely free ring for ever. If this bit is no set in the + * frame (by XmitFrame), this frame has never been sent or is + * already freed. + * The Tx descriptor ring lock must be held while calling this function !!! + * + * Returns: + * none + */ +static void FreeTxDescriptors( +SK_AC *pAC, /* pointer to the adapter context */ +TX_PORT *pTxPort) /* pointer to destination port structure */ +{ +TXD *pTxd; /* pointer to the checked descriptor */ +TXD *pNewTail; /* pointer to 'end' of the ring */ +SK_U32 Control; /* TBControl field of descriptor */ +SK_U64 PhysAddr; /* address of DMA mapping */ + + pNewTail = pTxPort->pTxdRingTail; + pTxd = pNewTail; + /* + * loop forever; exits if TX_CTRL_SOFTWARE bit not set in start frame + * or TX_CTRL_OWN_BMU bit set in any frame + */ + while (1) { + Control = pTxd->TBControl; + if ((Control & TX_CTRL_SOFTWARE) == 0) { + /* + * software controllable bit is set in first + * fragment when given to BMU. Not set means that + * this fragment was never sent or is already + * freed ( -> ring completely free now). + */ + pTxPort->pTxdRingTail = pTxd; + netif_wake_queue(pAC->dev[pTxPort->PortIndex]); + return; + } + if (Control & TX_CTRL_OWN_BMU) { + pTxPort->pTxdRingTail = pTxd; + if (pTxPort->TxdRingFree > 0) { + netif_wake_queue(pAC->dev[pTxPort->PortIndex]); + } + return; + } + + /* release the DMA mapping */ + PhysAddr = ((SK_U64) pTxd->VDataHigh) << (SK_U64) 32; + PhysAddr |= (SK_U64) pTxd->VDataLow; + pci_unmap_page(pAC->PciDev, PhysAddr, + pTxd->pMBuf->len, + PCI_DMA_TODEVICE); + + if (Control & TX_CTRL_EOF) + DEV_KFREE_SKB_ANY(pTxd->pMBuf); /* free message */ + + pTxPort->TxdRingFree++; + pTxd->TBControl &= ~TX_CTRL_SOFTWARE; + pTxd = pTxd->pNextTxd; /* point behind fragment with EOF */ + } /* while(forever) */ +} /* FreeTxDescriptors */ + +/***************************************************************************** + * + * FillRxRing - fill the receive ring with valid descriptors + * + * Description: + * This function fills the receive ring descriptors with data + * segments and makes them valid for the BMU. + * The active ring is filled completely, if possible. + * The non-active ring is filled only partial to save memory. + * + * Description of rx ring structure: + * head - points to the descriptor which will be used next by the BMU + * tail - points to the next descriptor to give to the BMU + * + * Returns: N/A + */ +static void FillRxRing( +SK_AC *pAC, /* pointer to the adapter context */ +RX_PORT *pRxPort) /* ptr to port struct for which the ring + should be filled */ +{ +unsigned long Flags; + + spin_lock_irqsave(&pRxPort->RxDesRingLock, Flags); + while (pRxPort->RxdRingFree > pRxPort->RxFillLimit) { + if(!FillRxDescriptor(pAC, pRxPort)) + break; + } + spin_unlock_irqrestore(&pRxPort->RxDesRingLock, Flags); +} /* FillRxRing */ + + +/***************************************************************************** + * + * FillRxDescriptor - fill one buffer into the receive ring + * + * Description: + * The function allocates a new receive buffer and + * puts it into the next descriptor. + * + * Returns: + * SK_TRUE - a buffer was added to the ring + * SK_FALSE - a buffer could not be added + */ +static SK_BOOL FillRxDescriptor( +SK_AC *pAC, /* pointer to the adapter context struct */ +RX_PORT *pRxPort) /* ptr to port struct of ring to fill */ +{ +struct sk_buff *pMsgBlock; /* pointer to a new message block */ +RXD *pRxd; /* the rxd to fill */ +SK_U16 Length; /* data fragment length */ +SK_U64 PhysAddr; /* physical address of a rx buffer */ + + pMsgBlock = alloc_skb(pAC->RxBufSize, GFP_ATOMIC); + if (pMsgBlock == NULL) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_ENTRY, + ("%s: Allocation of rx buffer failed !\n", + pAC->dev[pRxPort->PortIndex]->name)); + SK_PNMI_CNT_NO_RX_BUF(pAC, pRxPort->PortIndex); + return(SK_FALSE); + } + skb_reserve(pMsgBlock, 2); /* to align IP frames */ + /* skb allocated ok, so add buffer */ + pRxd = pRxPort->pRxdRingTail; + pRxPort->pRxdRingTail = pRxd->pNextRxd; + pRxPort->RxdRingFree--; + Length = pAC->RxBufSize; +#if 0 + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev, + virt_to_page(pMsgBlock->data), + ((unsigned long) pMsgBlock->data & + ~PAGE_MASK), + pAC->RxBufSize - 2, + PCI_DMA_FROMDEVICE); +#else + PhysAddr = (SK_U64) pci_phys_to_mem(pAC->PciDev, (u32)pMsgBlock->data); +#endif + pRxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff); + pRxd->VDataHigh = (SK_U32) (PhysAddr >> 32); + pRxd->pMBuf = pMsgBlock; + pRxd->RBControl = RX_CTRL_OWN_BMU | RX_CTRL_STF | + RX_CTRL_EOF_IRQ | RX_CTRL_CHECK_CSUM | Length; + return (SK_TRUE); + +} /* FillRxDescriptor */ + + +/***************************************************************************** + * + * ReQueueRxBuffer - fill one buffer back into the receive ring + * + * Description: + * Fill a given buffer back into the rx ring. The buffer + * has been previously allocated and aligned, and its phys. + * address calculated, so this is no more necessary. + * + * Returns: N/A + */ +static void ReQueueRxBuffer( +SK_AC *pAC, /* pointer to the adapter context struct */ +RX_PORT *pRxPort, /* ptr to port struct of ring to fill */ +struct sk_buff *pMsg, /* pointer to the buffer */ +SK_U32 PhysHigh, /* phys address high dword */ +SK_U32 PhysLow) /* phys address low dword */ +{ +RXD *pRxd; /* the rxd to fill */ +SK_U16 Length; /* data fragment length */ + + pRxd = pRxPort->pRxdRingTail; + pRxPort->pRxdRingTail = pRxd->pNextRxd; + pRxPort->RxdRingFree--; + Length = pAC->RxBufSize; + pRxd->VDataLow = PhysLow; + pRxd->VDataHigh = PhysHigh; + pRxd->pMBuf = pMsg; + pRxd->RBControl = RX_CTRL_OWN_BMU | RX_CTRL_STF | + RX_CTRL_EOF_IRQ | RX_CTRL_CHECK_CSUM | Length; + return; +} /* ReQueueRxBuffer */ + + +/***************************************************************************** + * + * ReceiveIrq - handle a receive IRQ + * + * Description: + * This function is called when a receive IRQ is set. + * It walks the receive descriptor ring and sends up all + * frames that are complete. + * + * Returns: N/A + */ +#if 0 +static void ReceiveIrq( +#else +void ReceiveIrq( +#endif + SK_AC *pAC, /* pointer to adapter context */ + RX_PORT *pRxPort, /* pointer to receive port struct */ + SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */ +{ +RXD *pRxd; /* pointer to receive descriptors */ +SK_U32 Control; /* control field of descriptor */ +struct sk_buff *pMsg; /* pointer to message holding frame */ +struct sk_buff *pNewMsg; /* pointer to a new message for copying frame */ +int FrameLength; /* total length of received frame */ +SK_MBUF *pRlmtMbuf; /* ptr to a buffer for giving a frame to rlmt */ +SK_EVPARA EvPara; /* an event parameter union */ +unsigned long Flags; /* for spin lock */ +int PortIndex = pRxPort->PortIndex; +unsigned int Offset; +unsigned int NumBytes; +unsigned int ForRlmt; +SK_BOOL IsBc; +SK_BOOL IsMc; +SK_BOOL IsBadFrame; /* Bad frame */ + +SK_U32 FrameStat; +unsigned short Csum1; +unsigned short Csum2; +unsigned short Type; +#if 0 +int Result; +#endif +SK_U64 PhysAddr; + +rx_start: + /* do forever; exit if RX_CTRL_OWN_BMU found */ + for ( pRxd = pRxPort->pRxdRingHead ; + pRxPort->RxdRingFree < pAC->RxDescrPerRing ; + pRxd = pRxd->pNextRxd, + pRxPort->pRxdRingHead = pRxd, + pRxPort->RxdRingFree ++) { + + /* + * For a better understanding of this loop + * Go through every descriptor beginning at the head + * Please note: the ring might be completely received so the OWN bit + * set is not a good crirteria to leave that loop. + * Therefore the RingFree counter is used. + * On entry of this loop pRxd is a pointer to the Rxd that needs + * to be checked next. + */ + + Control = pRxd->RBControl; + + /* check if this descriptor is ready */ + if ((Control & RX_CTRL_OWN_BMU) != 0) { + /* this descriptor is not yet ready */ + /* This is the usual end of the loop */ + /* We don't need to start the ring again */ + FillRxRing(pAC, pRxPort); + return; + } + + /* get length of frame and check it */ + FrameLength = Control & RX_CTRL_LEN_MASK; + if (FrameLength > pAC->RxBufSize) { + goto rx_failed; + } + + /* check for STF and EOF */ + if ((Control & (RX_CTRL_STF | RX_CTRL_EOF)) != + (RX_CTRL_STF | RX_CTRL_EOF)) { + goto rx_failed; + } + + /* here we have a complete frame in the ring */ + pMsg = pRxd->pMBuf; + + FrameStat = pRxd->FrameStat; + + /* check for frame length mismatch */ +#define XMR_FS_LEN_SHIFT 18 +#define GMR_FS_LEN_SHIFT 16 + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + if (FrameLength != (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("skge: Frame length mismatch (%u/%u).\n", + FrameLength, + (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT))); + goto rx_failed; + } + } + else { + if (FrameLength != (SK_U32) (FrameStat >> GMR_FS_LEN_SHIFT)) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("skge: Frame length mismatch (%u/%u).\n", + FrameLength, + (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT))); + goto rx_failed; + } + } + + /* Set Rx Status */ + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + IsBc = (FrameStat & XMR_FS_BC) != 0; + IsMc = (FrameStat & XMR_FS_MC) != 0; + IsBadFrame = (FrameStat & + (XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0; + } else { + IsBc = (FrameStat & GMR_FS_BC) != 0; + IsMc = (FrameStat & GMR_FS_MC) != 0; + IsBadFrame = (((FrameStat & GMR_FS_ANY_ERR) != 0) || + ((FrameStat & GMR_FS_RX_OK) == 0)); + } + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 0, + ("Received frame of length %d on port %d\n", + FrameLength, PortIndex)); + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 0, + ("Number of free rx descriptors: %d\n", + pRxPort->RxdRingFree)); +/* DumpMsg(pMsg, "Rx"); */ + + if ((Control & RX_CTRL_STAT_VALID) != RX_CTRL_STAT_VALID || + (IsBadFrame)) { +#if 0 + (FrameStat & (XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0) { +#endif + /* there is a receive error in this frame */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("skge: Error in received frame, dropped!\n" + "Control: %x\nRxStat: %x\n", + Control, FrameStat)); + + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + pci_dma_sync_single(pAC->PciDev, + (dma_addr_t) PhysAddr, + FrameLength, + PCI_DMA_FROMDEVICE); + ReQueueRxBuffer(pAC, pRxPort, pMsg, + pRxd->VDataHigh, pRxd->VDataLow); + + continue; + } + + /* + * if short frame then copy data to reduce memory waste + */ + if ((FrameLength < SK_COPY_THRESHOLD) && + ((pNewMsg = alloc_skb(FrameLength+2, GFP_ATOMIC)) != NULL)) { + /* + * Short frame detected and allocation successfull + */ + /* use new skb and copy data */ + skb_reserve(pNewMsg, 2); + skb_put(pNewMsg, FrameLength); + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + + pci_dma_sync_single(pAC->PciDev, + (dma_addr_t) PhysAddr, + FrameLength, + PCI_DMA_FROMDEVICE); + eth_copy_and_sum(pNewMsg, pMsg->data, + FrameLength, 0); + ReQueueRxBuffer(pAC, pRxPort, pMsg, + pRxd->VDataHigh, pRxd->VDataLow); + pMsg = pNewMsg; + + } + else { + /* + * if large frame, or SKB allocation failed, pass + * the SKB directly to the networking + */ + + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + + /* release the DMA mapping */ + pci_unmap_single(pAC->PciDev, + PhysAddr, + pAC->RxBufSize - 2, + PCI_DMA_FROMDEVICE); + + /* set length in message */ + skb_put(pMsg, FrameLength); + /* hardware checksum */ + Type = ntohs(*((short*)&pMsg->data[12])); + if (Type == 0x800) { + Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff); + Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff); +#if 0 + if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) && + (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) || + (pAC->GIni.GIChipId == CHIP_ID_YUKON)) { + Result = SkCsGetReceiveInfo(pAC, + &pMsg->data[14], + Csum1, Csum2, pRxPort->PortIndex); + if (Result == + SKCS_STATUS_IP_FRAGMENT || + Result == + SKCS_STATUS_IP_CSUM_OK || + Result == + SKCS_STATUS_TCP_CSUM_OK || + Result == + SKCS_STATUS_UDP_CSUM_OK) { + pMsg->ip_summed = + CHECKSUM_UNNECESSARY; + } else { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("skge: CRC error. Frame dropped!\n")); + goto rx_failed; + } + }/* checksumControl calculation valid */ +#endif + } /* IP frame */ + } /* frame > SK_COPY_TRESHOLD */ + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("V")); + ForRlmt = SK_RLMT_RX_PROTOCOL; +#if 0 + IsBc = (FrameStat & XMR_FS_BC)==XMR_FS_BC; +#endif + SK_RLMT_PRE_LOOKAHEAD(pAC, PortIndex, FrameLength, + IsBc, &Offset, &NumBytes); + if (NumBytes != 0) { +#if 0 + IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC; +#endif + SK_RLMT_LOOKAHEAD(pAC, PortIndex, + &pMsg->data[Offset], + IsBc, IsMc, &ForRlmt); + } + if (ForRlmt == SK_RLMT_RX_PROTOCOL) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W")); + /* send up only frames from active port */ + if ((PortIndex == pAC->ActivePort) || + (pAC->RlmtNets == 2)) { + /* frame for upper layer */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("U")); +#ifdef xDEBUG + DumpMsg(pMsg, "Rx"); +#endif + SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC, + FrameLength, pRxPort->PortIndex); + +#if 0 + pMsg->dev = pAC->dev[pRxPort->PortIndex]; + pMsg->protocol = eth_type_trans(pMsg, + pAC->dev[pRxPort->PortIndex]); + netif_rx(pMsg); + pAC->dev[pRxPort->PortIndex]->last_rx = jiffies; +#else + NetReceive(pMsg->data, pMsg->len); + dev_kfree_skb_any(pMsg); +#endif + } + else { + /* drop frame */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("D")); + DEV_KFREE_SKB(pMsg); + } + + } /* if not for rlmt */ + else { + /* packet for rlmt */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, ("R")); + pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC, + pAC->IoBase, FrameLength); + if (pRlmtMbuf != NULL) { + pRlmtMbuf->pNext = NULL; + pRlmtMbuf->Length = FrameLength; + pRlmtMbuf->PortIdx = PortIndex; + EvPara.pParaPtr = pRlmtMbuf; + memcpy((char*)(pRlmtMbuf->pData), + (char*)(pMsg->data), + FrameLength); + + /* SlowPathLock needed? */ + if (SlowPathLock == SK_TRUE) { + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + SkEventQueue(pAC, SKGE_RLMT, + SK_RLMT_PACKET_RECEIVED, + EvPara); + pAC->CheckQueue = SK_TRUE; + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + } else { + SkEventQueue(pAC, SKGE_RLMT, + SK_RLMT_PACKET_RECEIVED, + EvPara); + pAC->CheckQueue = SK_TRUE; + } + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, + SK_DBGCAT_DRV_RX_PROGRESS, + ("Q")); + } +#if 0 + if ((pAC->dev[pRxPort->PortIndex]->flags & + (IFF_PROMISC | IFF_ALLMULTI)) != 0 || + (ForRlmt & SK_RLMT_RX_PROTOCOL) == + SK_RLMT_RX_PROTOCOL) { + pMsg->dev = pAC->dev[pRxPort->PortIndex]; + pMsg->protocol = eth_type_trans(pMsg, + pAC->dev[pRxPort->PortIndex]); + netif_rx(pMsg); + pAC->dev[pRxPort->PortIndex]->last_rx = jiffies; + } +#else + if (0) { + } +#endif + else { + DEV_KFREE_SKB(pMsg); + } + + } /* if packet for rlmt */ + } /* for ... scanning the RXD ring */ + + /* RXD ring is empty -> fill and restart */ + FillRxRing(pAC, pRxPort); + /* do not start if called from Close */ + if (pAC->BoardLevel > 0) { + ClearAndStartRx(pAC, PortIndex); + } + return; + +rx_failed: + /* remove error frame */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR, + ("Schrottdescriptor, length: 0x%x\n", FrameLength)); + + /* release the DMA mapping */ + + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + pci_unmap_page(pAC->PciDev, + PhysAddr, + pAC->RxBufSize - 2, + PCI_DMA_FROMDEVICE); + DEV_KFREE_SKB_IRQ(pRxd->pMBuf); + pRxd->pMBuf = NULL; + pRxPort->RxdRingFree++; + pRxPort->pRxdRingHead = pRxd->pNextRxd; + goto rx_start; + +} /* ReceiveIrq */ + + +/***************************************************************************** + * + * ClearAndStartRx - give a start receive command to BMU, clear IRQ + * + * Description: + * This function sends a start command and a clear interrupt + * command for one receive queue to the BMU. + * + * Returns: N/A + * none + */ +static void ClearAndStartRx( +SK_AC *pAC, /* pointer to the adapter context */ +int PortIndex) /* index of the receive port (XMAC) */ +{ + SK_OUT8(pAC->IoBase, RxQueueAddr[PortIndex]+RX_Q_CTRL, + RX_Q_CTRL_START | RX_Q_CTRL_CLR_I_EOF); +} /* ClearAndStartRx */ + + +/***************************************************************************** + * + * ClearTxIrq - give a clear transmit IRQ command to BMU + * + * Description: + * This function sends a clear tx IRQ command for one + * transmit queue to the BMU. + * + * Returns: N/A + */ +static void ClearTxIrq( +SK_AC *pAC, /* pointer to the adapter context */ +int PortIndex, /* index of the transmit port (XMAC) */ +int Prio) /* priority or normal queue */ +{ + SK_OUT8(pAC->IoBase, TxQueueAddr[PortIndex][Prio]+TX_Q_CTRL, + TX_Q_CTRL_CLR_I_EOF); +} /* ClearTxIrq */ + + +/***************************************************************************** + * + * ClearRxRing - remove all buffers from the receive ring + * + * Description: + * This function removes all receive buffers from the ring. + * The receive BMU must be stopped before calling this function. + * + * Returns: N/A + */ +static void ClearRxRing( +SK_AC *pAC, /* pointer to adapter context */ +RX_PORT *pRxPort) /* pointer to rx port struct */ +{ +RXD *pRxd; /* pointer to the current descriptor */ +unsigned long Flags; +SK_U64 PhysAddr; + + if (pRxPort->RxdRingFree == pAC->RxDescrPerRing) { + return; + } + spin_lock_irqsave(&pRxPort->RxDesRingLock, Flags); + pRxd = pRxPort->pRxdRingHead; + do { + if (pRxd->pMBuf != NULL) { + + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32; + PhysAddr |= (SK_U64) pRxd->VDataLow; + pci_unmap_page(pAC->PciDev, + PhysAddr, + pAC->RxBufSize - 2, + PCI_DMA_FROMDEVICE); + DEV_KFREE_SKB(pRxd->pMBuf); + pRxd->pMBuf = NULL; + } + pRxd->RBControl &= RX_CTRL_OWN_BMU; + pRxd = pRxd->pNextRxd; + pRxPort->RxdRingFree++; + } while (pRxd != pRxPort->pRxdRingTail); + pRxPort->pRxdRingTail = pRxPort->pRxdRingHead; + spin_unlock_irqrestore(&pRxPort->RxDesRingLock, Flags); +} /* ClearRxRing */ + + +/***************************************************************************** + * + * ClearTxRing - remove all buffers from the transmit ring + * + * Description: + * This function removes all transmit buffers from the ring. + * The transmit BMU must be stopped before calling this function + * and transmitting at the upper level must be disabled. + * The BMU own bit of all descriptors is cleared, the rest is + * done by calling FreeTxDescriptors. + * + * Returns: N/A + */ +static void ClearTxRing( +SK_AC *pAC, /* pointer to adapter context */ +TX_PORT *pTxPort) /* pointer to tx prt struct */ +{ +TXD *pTxd; /* pointer to the current descriptor */ +int i; +unsigned long Flags; + + spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags); + pTxd = pTxPort->pTxdRingHead; + for (i=0; iTxDescrPerRing; i++) { + pTxd->TBControl &= ~TX_CTRL_OWN_BMU; + pTxd = pTxd->pNextTxd; + } + FreeTxDescriptors(pAC, pTxPort); + spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags); +} /* ClearTxRing */ + + +#if 0 +/***************************************************************************** + * + * SetQueueSizes - configure the sizes of rx and tx queues + * + * Description: + * This function assigns the sizes for active and passive port + * to the appropriate HWinit structure variables. + * The passive port(s) get standard values, all remaining RAM + * is given to the active port. + * The queue sizes are in kbyte and must be multiple of 8. + * The limits for the number of buffers filled into the rx rings + * is also set in this routine. + * + * Returns: + * none + */ +static void SetQueueSizes( +SK_AC *pAC) /* pointer to the adapter context */ +{ +int StandbyRam; /* adapter RAM used for a standby port */ +int RemainingRam; /* adapter RAM available for the active port */ +int RxRam; /* RAM used for the active port receive queue */ +int i; /* loop counter */ + +if (pAC->RlmtNets == 1) { + StandbyRam = SK_RLMT_STANDBY_QRXSIZE + SK_RLMT_STANDBY_QXASIZE + + SK_RLMT_STANDBY_QXSSIZE; + RemainingRam = pAC->GIni.GIRamSize - + (pAC->GIni.GIMacsFound-1) * StandbyRam; + for (i=0; iGIni.GIMacsFound; i++) { + pAC->GIni.GP[i].PRxQSize = SK_RLMT_STANDBY_QRXSIZE; + pAC->GIni.GP[i].PXSQSize = SK_RLMT_STANDBY_QXSSIZE; + pAC->GIni.GP[i].PXAQSize = SK_RLMT_STANDBY_QXASIZE; + } + RxRam = (RemainingRam * 8 / 10) & ~7; + pAC->GIni.GP[pAC->ActivePort].PRxQSize = RxRam; + pAC->GIni.GP[pAC->ActivePort].PXSQSize = 0; + pAC->GIni.GP[pAC->ActivePort].PXAQSize = + (RemainingRam - RxRam) & ~7; + pAC->RxQueueSize = RxRam; + pAC->TxSQueueSize = 0; + pAC->TxAQueueSize = (RemainingRam - RxRam) & ~7; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("queue sizes settings - rx:%d txA:%d txS:%d\n", + pAC->RxQueueSize,pAC->TxAQueueSize, pAC->TxSQueueSize)); +} else { + RemainingRam = pAC->GIni.GIRamSize/pAC->GIni.GIMacsFound; + RxRam = (RemainingRam * 8 / 10) & ~7; + for (i=0; iGIni.GIMacsFound; i++) { + pAC->GIni.GP[i].PRxQSize = RxRam; + pAC->GIni.GP[i].PXSQSize = 0; + pAC->GIni.GP[i].PXAQSize = (RemainingRam - RxRam) & ~7; + } + + pAC->RxQueueSize = RxRam; + pAC->TxSQueueSize = 0; + pAC->TxAQueueSize = (RemainingRam - RxRam) & ~7; +} + for (i=0; iRxPort[i].RxFillLimit = pAC->RxDescrPerRing; + } + + if (pAC->RlmtNets == 2) { + for (i=0; iGIni.GIMacsFound; i++) { + pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing - 100; + } + } else { + for (i=0; iGIni.GIMacsFound; i++) { + pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing - 100; + } + /* + * Do not set the Limit to 0, because this could cause + * wrap around with ReQueue'ed buffers (a buffer could + * be requeued in the same position, made accessable to + * the hardware, and the hardware could change its + * contents! + */ + pAC->RxPort[pAC->ActivePort].RxFillLimit = 1; + } + +#ifdef DEBUG + for (i=0; iGIni.GIMacsFound; i++) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, + ("i: %d, RxQSize: %d, PXSQsize: %d, PXAQSize: %d\n", + i, + pAC->GIni.GP[i].PRxQSize, + pAC->GIni.GP[i].PXSQSize, + pAC->GIni.GP[i].PXAQSize)); + } +#endif +} /* SetQueueSizes */ + + +/***************************************************************************** + * + * SkGeSetMacAddr - Set the hardware MAC address + * + * Description: + * This function sets the MAC address used by the adapter. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p) +{ + +DEV_NET *pNet = (DEV_NET*) dev->priv; +SK_AC *pAC = pNet->pAC; + +struct sockaddr *addr = p; +unsigned long Flags; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeSetMacAddr starts now...\n")); + if(netif_running(dev)) + return -EBUSY; + + memcpy(dev->dev_addr, addr->sa_data,dev->addr_len); + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + + if (pAC->RlmtNets == 2) + SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr, + (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS); + else + SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort, + (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS); + + + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + return 0; +} /* SkGeSetMacAddr */ +#endif + + +/***************************************************************************** + * + * SkGeSetRxMode - set receive mode + * + * Description: + * This function sets the receive mode of an adapter. The adapter + * supports promiscuous mode, allmulticast mode and a number of + * multicast addresses. If more multicast addresses the available + * are selected, a hash function in the hardware is used. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +#if 0 +static void SkGeSetRxMode(struct SK_NET_DEVICE *dev) +{ + +DEV_NET *pNet; +SK_AC *pAC; + +struct dev_mc_list *pMcList; +int i; +int PortIdx; +unsigned long Flags; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeSetRxMode starts now... ")); + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + if (pAC->RlmtNets == 1) + PortIdx = pAC->ActivePort; + else + PortIdx = pNet->NetNr; + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + if (dev->flags & IFF_PROMISC) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("PROMISCUOUS mode\n")); + SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx, + SK_PROM_MODE_LLC); + } else if (dev->flags & IFF_ALLMULTI) { + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("ALLMULTI mode\n")); + SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx, + SK_PROM_MODE_ALL_MC); + } else { + SkAddrPromiscuousChange(pAC, pAC->IoBase, PortIdx, + SK_PROM_MODE_NONE); + SkAddrMcClear(pAC, pAC->IoBase, PortIdx, 0); + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("Number of MC entries: %d ", dev->mc_count)); + + pMcList = dev->mc_list; + for (i=0; imc_count; i++, pMcList = pMcList->next) { + SkAddrMcAdd(pAC, pAC->IoBase, PortIdx, + (SK_MAC_ADDR*)pMcList->dmi_addr, 0); + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MCA, + ("%02x:%02x:%02x:%02x:%02x:%02x\n", + pMcList->dmi_addr[0], + pMcList->dmi_addr[1], + pMcList->dmi_addr[2], + pMcList->dmi_addr[3], + pMcList->dmi_addr[4], + pMcList->dmi_addr[5])); + } + SkAddrMcUpdate(pAC, pAC->IoBase, PortIdx); + } + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + return; +} /* SkGeSetRxMode */ + + +/***************************************************************************** + * + * SkGeChangeMtu - set the MTU to another value + * + * Description: + * This function sets is called whenever the MTU size is changed + * (ifconfig mtu xxx dev ethX). If the MTU is bigger than standard + * ethernet MTU size, long frame support is activated. + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int NewMtu) +{ +DEV_NET *pNet; +DEV_NET *pOtherNet; +SK_AC *pAC; +unsigned long Flags; +int i; +SK_EVPARA EvPara; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeChangeMtu starts now...\n")); + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + if ((NewMtu < 68) || (NewMtu > SK_JUMBO_MTU)) { + return -EINVAL; + } + + if(pAC->BoardLevel != 2) { + return -EINVAL; + } + + pNet->Mtu = NewMtu; + pOtherNet = (DEV_NET*)pAC->dev[1 - pNet->NetNr]->priv; + if ((pOtherNet->Mtu > 1500) && (NewMtu <= 1500) && (pOtherNet->Up==1)) { + return(0); + } + + EvPara.Para32[0] = pNet->NetNr; + EvPara.Para32[1] = -1; + + pAC->RxBufSize = NewMtu + 32; + dev->mtu = NewMtu; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("New MTU: %d\n", NewMtu)); + + /* prevent reconfiguration while changing the MTU */ + + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + + /* Found more than one port */ + if ((pAC->GIni.GIMacsFound == 2 ) && + (pAC->RlmtNets == 2)) { + /* Stop both ports */ + EvPara.Para32[0] = 0; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + EvPara.Para32[0] = 1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + } else { + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara); + } + + SkEventDispatcher(pAC, pAC->IoBase); + + for (i=0; iGIni.GIMacsFound; i++) { + spin_lock_irqsave( + &pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock, Flags); + netif_stop_queue(pAC->dev[i]); + + } + + /* + * adjust number of rx buffers allocated + */ + if (NewMtu > 1500) { + /* use less rx buffers */ + for (i=0; iGIni.GIMacsFound; i++) { + /* Found more than one port */ + if ((pAC->GIni.GIMacsFound == 2 ) && + (pAC->RlmtNets == 2)) { + pAC->RxPort[i].RxFillLimit = + pAC->RxDescrPerRing - 100; + } else { + if (i == pAC->ActivePort) + pAC->RxPort[i].RxFillLimit = + pAC->RxDescrPerRing - 100; + else + pAC->RxPort[i].RxFillLimit = + pAC->RxDescrPerRing - 10; + } + } + } + else { + /* use normal amount of rx buffers */ + for (i=0; iGIni.GIMacsFound; i++) { + /* Found more than one port */ + if ((pAC->GIni.GIMacsFound == 2 ) && + (pAC->RlmtNets == 2)) { + pAC->RxPort[i].RxFillLimit = 1; + } else { + if (i == pAC->ActivePort) + pAC->RxPort[i].RxFillLimit = 1; + else + pAC->RxPort[i].RxFillLimit = + pAC->RxDescrPerRing - 100; + } + } + } + + SkGeDeInit(pAC, pAC->IoBase); + + /* + * enable/disable hardware support for long frames + */ + if (NewMtu > 1500) { +/* pAC->JumboActivated = SK_TRUE; /#* is never set back !!! */ + pAC->GIni.GIPortUsage = SK_JUMBO_LINK; + } + else { + if ((pAC->GIni.GIMacsFound == 2 ) && + (pAC->RlmtNets == 2)) { + pAC->GIni.GIPortUsage = SK_MUL_LINK; + } else { + pAC->GIni.GIPortUsage = SK_RED_LINK; + } + } + + SkGeInit( pAC, pAC->IoBase, 1); + SkI2cInit( pAC, pAC->IoBase, 1); + SkEventInit(pAC, pAC->IoBase, 1); + SkPnmiInit( pAC, pAC->IoBase, 1); + SkAddrInit( pAC, pAC->IoBase, 1); + SkRlmtInit( pAC, pAC->IoBase, 1); + SkTimerInit(pAC, pAC->IoBase, 1); + + /* + * tschilling: + * Speed and others are set back to default in level 1 init! + */ + GetConfiguration(pAC); + + SkGeInit( pAC, pAC->IoBase, 2); + SkI2cInit( pAC, pAC->IoBase, 2); + SkEventInit(pAC, pAC->IoBase, 2); + SkPnmiInit( pAC, pAC->IoBase, 2); + SkAddrInit( pAC, pAC->IoBase, 2); + SkRlmtInit( pAC, pAC->IoBase, 2); + SkTimerInit(pAC, pAC->IoBase, 2); + + /* + * clear and reinit the rx rings here + */ + for (i=0; iGIni.GIMacsFound; i++) { + ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE); + ClearRxRing(pAC, &pAC->RxPort[i]); + FillRxRing(pAC, &pAC->RxPort[i]); + + /* Enable transmit descriptor polling. */ + SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE); + FillRxRing(pAC, &pAC->RxPort[i]); + }; + + SkGeYellowLED(pAC, pAC->IoBase, 1); + +#ifdef USE_INT_MOD + { + unsigned long ModBase; + ModBase = 53125000 / INTS_PER_SEC; + SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase); + SK_OUT32(pAC->IoBase, B2_IRQM_MSK, IRQ_MOD_MASK); + SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START); + } +#endif + + netif_start_queue(pAC->dev[pNet->PortNr]); + for (i=pAC->GIni.GIMacsFound-1; i>=0; i--) { + spin_unlock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock); + } + + /* enable Interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, IRQ_MASK); + SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK); + + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); + SkEventDispatcher(pAC, pAC->IoBase); + + /* Found more than one port */ + if ((pAC->GIni.GIMacsFound == 2 ) && + (pAC->RlmtNets == 2)) { + /* Start both ports */ + EvPara.Para32[0] = pAC->RlmtNets; + EvPara.Para32[1] = -1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, + EvPara); + + + EvPara.Para32[1] = -1; + EvPara.Para32[0] = pNet->PortNr; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); + + if (pOtherNet->Up) { + EvPara.Para32[0] = pOtherNet->PortNr; + SkEventQueue(pAC, SKGE_RLMT, + SK_RLMT_START, EvPara); + } + } else { + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara); + } + + SkEventDispatcher(pAC, pAC->IoBase); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + return 0; +} /* SkGeChangeMtu */ + + +/***************************************************************************** + * + * SkGeStats - return ethernet device statistics + * + * Description: + * This function return statistic data about the ethernet device + * to the operating system. + * + * Returns: + * pointer to the statistic structure. + */ +static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev) +{ +DEV_NET *pNet = (DEV_NET*) dev->priv; +SK_AC *pAC = pNet->pAC; +SK_PNMI_STRUCT_DATA *pPnmiStruct; /* structure for all Pnmi-Data */ +SK_PNMI_STAT *pPnmiStat; /* pointer to virtual XMAC stat. data */ +SK_PNMI_CONF *pPnmiConf; /* pointer to virtual link config. */ +unsigned int Size; /* size of pnmi struct */ +unsigned long Flags; /* for spin lock */ + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeStats starts now...\n")); + pPnmiStruct = &pAC->PnmiStruct; + memset(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA)); + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + Size = SK_PNMI_STRUCT_SIZE; + SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + pPnmiStat = &pPnmiStruct->Stat[0]; + pPnmiConf = &pPnmiStruct->Conf[0]; + + pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF; + pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF; + pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts; + pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts; + + if (pNet->Mtu <= 1500) { + pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF; + } else { + pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts - + pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF); + } + + + if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && pAC->HWRevision < 12) + pAC->stats.rx_errors = pAC->stats.rx_errors - pPnmiStat->StatRxShortsCts; + + pAC->stats.tx_errors = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF; + pAC->stats.rx_dropped = (SK_U32) pPnmiStruct->RxNoBufCts & 0xFFFFFFFF; + pAC->stats.tx_dropped = (SK_U32) pPnmiStruct->TxNoBufCts & 0xFFFFFFFF; + pAC->stats.multicast = (SK_U32) pPnmiStat->StatRxMulticastOkCts & 0xFFFFFFFF; + pAC->stats.collisions = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF; + + /* detailed rx_errors: */ + pAC->stats.rx_length_errors = (SK_U32) pPnmiStat->StatRxRuntCts & 0xFFFFFFFF; + pAC->stats.rx_over_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF; + pAC->stats.rx_crc_errors = (SK_U32) pPnmiStat->StatRxFcsCts & 0xFFFFFFFF; + pAC->stats.rx_frame_errors = (SK_U32) pPnmiStat->StatRxFramingCts & 0xFFFFFFFF; + pAC->stats.rx_fifo_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF; + pAC->stats.rx_missed_errors = (SK_U32) pPnmiStat->StatRxMissedCts & 0xFFFFFFFF; + + /* detailed tx_errors */ + pAC->stats.tx_aborted_errors = (SK_U32) 0; + pAC->stats.tx_carrier_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF; + pAC->stats.tx_fifo_errors = (SK_U32) pPnmiStat->StatTxFifoUnderrunCts & 0xFFFFFFFF; + pAC->stats.tx_heartbeat_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF; + pAC->stats.tx_window_errors = (SK_U32) 0; + + return(&pAC->stats); +} /* SkGeStats */ + + +/***************************************************************************** + * + * SkGeIoctl - IO-control function + * + * Description: + * This function is called if an ioctl is issued on the device. + * There are three subfunction for reading, writing and test-writing + * the private MIB data structure (usefull for SysKonnect-internal tools). + * + * Returns: + * 0, if everything is ok + * !=0, on error + */ +static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd) +{ +DEV_NET *pNet; +SK_AC *pAC; + +SK_GE_IOCTL Ioctl; +unsigned int Err = 0; +int Size; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeIoctl starts now...\n")); + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) { + return -EFAULT; + } + + switch(cmd) { + case SK_IOCTL_SETMIB: + case SK_IOCTL_PRESETMIB: + if (!capable(CAP_NET_ADMIN)) return -EPERM; + case SK_IOCTL_GETMIB: + if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData, + Ioctl.LenPnmiStruct)? + Ioctl.Len : sizeof(pAC->PnmiStruct))) { + return -EFAULT; + } + Size = SkGeIocMib(pNet, Ioctl.Len, cmd); + if(copy_to_user(Ioctl.pData, &pAC->PnmiStruct, + Ioctl.Lenifr_data, &Ioctl, sizeof(SK_GE_IOCTL))) { + return -EFAULT; + } + break; + default: + Err = -EOPNOTSUPP; + } + return(Err); +} /* SkGeIoctl */ + + +/***************************************************************************** + * + * SkGeIocMib - handle a GetMib, SetMib- or PresetMib-ioctl message + * + * Description: + * This function reads/writes the MIB data using PNMI (Private Network + * Management Interface). + * The destination for the data must be provided with the + * ioctl call and is given to the driver in the form of + * a user space address. + * Copying from the user-provided data area into kernel messages + * and back is done by copy_from_user and copy_to_user calls in + * SkGeIoctl. + * + * Returns: + * returned size from PNMI call + */ +static int SkGeIocMib( +DEV_NET *pNet, /* pointer to the adapter context */ +unsigned int Size, /* length of ioctl data */ +int mode) /* flag for set/preset */ +{ +unsigned long Flags; /* for spin lock */ +SK_AC *pAC; + + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("SkGeIocMib starts now...\n")); + pAC = pNet->pAC; + /* access MIB */ + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + switch(mode) { + case SK_IOCTL_GETMIB: + SkPnmiGetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size, + pNet->NetNr); + break; + case SK_IOCTL_PRESETMIB: + SkPnmiPreSetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size, + pNet->NetNr); + break; + case SK_IOCTL_SETMIB: + SkPnmiSetStruct(pAC, pAC->IoBase, &pAC->PnmiStruct, &Size, + pNet->NetNr); + break; + default: + break; + } + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, + ("MIB data access succeeded\n")); + return (Size); +} /* SkGeIocMib */ +#endif + + +/***************************************************************************** + * + * GetConfiguration - read configuration information + * + * Description: + * This function reads per-adapter configuration information from + * the options provided on the command line. + * + * Returns: + * none + */ +static void GetConfiguration( +SK_AC *pAC) /* pointer to the adapter context structure */ +{ +SK_I32 Port; /* preferred port */ +int LinkSpeed; /* Link speed */ +int AutoNeg; /* auto negotiation off (0) or on (1) */ +int DuplexCap; /* duplex capabilities (0=both, 1=full, 2=half */ +int MSMode; /* master / slave mode selection */ +SK_BOOL AutoSet; +SK_BOOL DupSet; +/* + * The two parameters AutoNeg. and DuplexCap. map to one configuration + * parameter. The mapping is described by this table: + * DuplexCap -> | both | full | half | + * AutoNeg | | | | + * ----------------------------------------------------------------- + * Off | illegal | Full | Half | + * ----------------------------------------------------------------- + * On | AutoBoth | AutoFull | AutoHalf | + * ----------------------------------------------------------------- + * Sense | AutoSense | AutoSense | AutoSense | + */ +int Capabilities[3][3] = + { { -1, SK_LMODE_FULL, SK_LMODE_HALF}, + {SK_LMODE_AUTOBOTH, SK_LMODE_AUTOFULL, SK_LMODE_AUTOHALF}, + {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} }; +#define DC_BOTH 0 +#define DC_FULL 1 +#define DC_HALF 2 +#define AN_OFF 0 +#define AN_ON 1 +#define AN_SENS 2 + + /* settings for port A */ + /* settings link speed */ + LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */ + if (Speed_A != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(Speed_A[pAC->Index],"")==0) { + LinkSpeed = SK_LSPEED_AUTO; + } + else if (strcmp(Speed_A[pAC->Index],"Auto")==0) { + LinkSpeed = SK_LSPEED_AUTO; + } + else if (strcmp(Speed_A[pAC->Index],"10")==0) { + LinkSpeed = SK_LSPEED_10MBPS; + } + else if (strcmp(Speed_A[pAC->Index],"100")==0) { + LinkSpeed = SK_LSPEED_100MBPS; + } + else if (strcmp(Speed_A[pAC->Index],"1000")==0) { + LinkSpeed = SK_LSPEED_1000MBPS; + } + else printk("%s: Illegal value for Speed_A\n", + pAC->dev[0]->name); + } + + /* Check speed parameter */ + /* Only copper type adapter and GE V2 cards */ + if (((pAC->GIni.GIChipId != CHIP_ID_YUKON) || + (pAC->GIni.GICopperType != SK_TRUE)) && + ((LinkSpeed != SK_LSPEED_AUTO) && + (LinkSpeed != SK_LSPEED_1000MBPS))) { + printk("%s: Illegal value for Speed_A. " + "Not a copper card or GE V2 card\n Using " + "speed 1000\n", pAC->dev[0]->name); + LinkSpeed = SK_LSPEED_1000MBPS; + } + pAC->GIni.GP[0].PLinkSpeed = LinkSpeed; + + /* Autonegotiation */ + AutoNeg = AN_ON; /* tschilling: Default: Autonegotiation on! */ + AutoSet = SK_FALSE; + if (AutoNeg_A != NULL && pAC->IndexIndex] != NULL) { + AutoSet = SK_TRUE; + if (strcmp(AutoNeg_A[pAC->Index],"")==0) { + AutoSet = SK_FALSE; + } + else if (strcmp(AutoNeg_A[pAC->Index],"On")==0) { + AutoNeg = AN_ON; + } + else if (strcmp(AutoNeg_A[pAC->Index],"Off")==0) { + AutoNeg = AN_OFF; + } + else if (strcmp(AutoNeg_A[pAC->Index],"Sense")==0) { + AutoNeg = AN_SENS; + } + else printk("%s: Illegal value for AutoNeg_A\n", + pAC->dev[0]->name); + } + + DuplexCap = DC_BOTH; + DupSet = SK_FALSE; + if (DupCap_A != NULL && pAC->IndexIndex] != NULL) { + DupSet = SK_TRUE; + if (strcmp(DupCap_A[pAC->Index],"")==0) { + DupSet = SK_FALSE; + } + else if (strcmp(DupCap_A[pAC->Index],"Both")==0) { + DuplexCap = DC_BOTH; + } + else if (strcmp(DupCap_A[pAC->Index],"Full")==0) { + DuplexCap = DC_FULL; + } + else if (strcmp(DupCap_A[pAC->Index],"Half")==0) { + DuplexCap = DC_HALF; + } + else printk("%s: Illegal value for DupCap_A\n", + pAC->dev[0]->name); + } + + /* check for illegal combinations */ + if (AutoSet && AutoNeg==AN_SENS && DupSet) { + printk("%s, Port A: DuplexCapabilities" + " ignored using Sense mode\n", pAC->dev[0]->name); + } + if (AutoSet && AutoNeg==AN_OFF && DupSet && DuplexCap==DC_BOTH){ + printk("%s, Port A: Illegal combination" + " of values AutoNeg. and DuplexCap.\n Using " + "Full Duplex\n", pAC->dev[0]->name); + + DuplexCap = DC_FULL; + } + if (AutoSet && AutoNeg==AN_OFF && !DupSet) { + DuplexCap = DC_FULL; + } + + if (!AutoSet && DupSet) { + printk("%s, Port A: Duplex setting not" + " possible in\n default AutoNegotiation mode" + " (Sense).\n Using AutoNegotiation On\n", + pAC->dev[0]->name); + AutoNeg = AN_ON; + } + + /* set the desired mode */ + pAC->GIni.GP[0].PLinkModeConf = + Capabilities[AutoNeg][DuplexCap]; + + pAC->GIni.GP[0].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + if (FlowCtrl_A != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(FlowCtrl_A[pAC->Index],"") == 0) { + } + else if (strcmp(FlowCtrl_A[pAC->Index],"SymOrRem") == 0) { + pAC->GIni.GP[0].PFlowCtrlMode = + SK_FLOW_MODE_SYM_OR_REM; + } + else if (strcmp(FlowCtrl_A[pAC->Index],"Sym")==0) { + pAC->GIni.GP[0].PFlowCtrlMode = + SK_FLOW_MODE_SYMMETRIC; + } + else if (strcmp(FlowCtrl_A[pAC->Index],"LocSend")==0) { + pAC->GIni.GP[0].PFlowCtrlMode = + SK_FLOW_MODE_LOC_SEND; + } + else if (strcmp(FlowCtrl_A[pAC->Index],"None")==0) { + pAC->GIni.GP[0].PFlowCtrlMode = + SK_FLOW_MODE_NONE; + } + else printk("Illegal value for FlowCtrl_A\n"); + } + if (AutoNeg==AN_OFF && pAC->GIni.GP[0].PFlowCtrlMode!= + SK_FLOW_MODE_NONE) { + printk("%s, Port A: FlowControl" + " impossible without AutoNegotiation," + " disabled\n", pAC->dev[0]->name); + pAC->GIni.GP[0].PFlowCtrlMode = SK_FLOW_MODE_NONE; + } + + MSMode = SK_MS_MODE_AUTO; /* default: do auto select */ + if (Role_A != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(Role_A[pAC->Index],"")==0) { + } + else if (strcmp(Role_A[pAC->Index],"Auto")==0) { + MSMode = SK_MS_MODE_AUTO; + } + else if (strcmp(Role_A[pAC->Index],"Master")==0) { + MSMode = SK_MS_MODE_MASTER; + } + else if (strcmp(Role_A[pAC->Index],"Slave")==0) { + MSMode = SK_MS_MODE_SLAVE; + } + else printk("%s: Illegal value for Role_A\n", + pAC->dev[0]->name); + } + pAC->GIni.GP[0].PMSMode = MSMode; + + + /* settings for port B */ + /* settings link speed */ + LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */ + if (Speed_B != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(Speed_B[pAC->Index],"")==0) { + LinkSpeed = SK_LSPEED_AUTO; + } + else if (strcmp(Speed_B[pAC->Index],"Auto")==0) { + LinkSpeed = SK_LSPEED_AUTO; + } + else if (strcmp(Speed_B[pAC->Index],"10")==0) { + LinkSpeed = SK_LSPEED_10MBPS; + } + else if (strcmp(Speed_B[pAC->Index],"100")==0) { + LinkSpeed = SK_LSPEED_100MBPS; + } + else if (strcmp(Speed_B[pAC->Index],"1000")==0) { + LinkSpeed = SK_LSPEED_1000MBPS; + } + else printk("%s: Illegal value for Speed_B\n", + pAC->dev[1]->name); + } + + /* Check speed parameter */ + /* Only copper type adapter and GE V2 cards */ + if (((pAC->GIni.GIChipId != CHIP_ID_YUKON) || + (pAC->GIni.GICopperType != SK_TRUE)) && + ((LinkSpeed != SK_LSPEED_AUTO) && + (LinkSpeed != SK_LSPEED_1000MBPS))) { + printk("%s: Illegal value for Speed_B. " + "Not a copper card or GE V2 card\n Using " + "speed 1000\n", pAC->dev[1]->name); + LinkSpeed = SK_LSPEED_1000MBPS; + } + pAC->GIni.GP[1].PLinkSpeed = LinkSpeed; + + /* Auto negotiation */ + AutoNeg = AN_SENS; /* default: do auto Sense */ + AutoSet = SK_FALSE; + if (AutoNeg_B != NULL && pAC->IndexIndex] != NULL) { + AutoSet = SK_TRUE; + if (strcmp(AutoNeg_B[pAC->Index],"")==0) { + AutoSet = SK_FALSE; + } + else if (strcmp(AutoNeg_B[pAC->Index],"On")==0) { + AutoNeg = AN_ON; + } + else if (strcmp(AutoNeg_B[pAC->Index],"Off")==0) { + AutoNeg = AN_OFF; + } + else if (strcmp(AutoNeg_B[pAC->Index],"Sense")==0) { + AutoNeg = AN_SENS; + } + else printk("Illegal value for AutoNeg_B\n"); + } + + DuplexCap = DC_BOTH; + DupSet = SK_FALSE; + if (DupCap_B != NULL && pAC->IndexIndex] != NULL) { + DupSet = SK_TRUE; + if (strcmp(DupCap_B[pAC->Index],"")==0) { + DupSet = SK_FALSE; + } + else if (strcmp(DupCap_B[pAC->Index],"Both")==0) { + DuplexCap = DC_BOTH; + } + else if (strcmp(DupCap_B[pAC->Index],"Full")==0) { + DuplexCap = DC_FULL; + } + else if (strcmp(DupCap_B[pAC->Index],"Half")==0) { + DuplexCap = DC_HALF; + } + else printk("Illegal value for DupCap_B\n"); + } + + /* check for illegal combinations */ + if (AutoSet && AutoNeg==AN_SENS && DupSet) { + printk("%s, Port B: DuplexCapabilities" + " ignored using Sense mode\n", pAC->dev[1]->name); + } + if (AutoSet && AutoNeg==AN_OFF && DupSet && DuplexCap==DC_BOTH){ + printk("%s, Port B: Illegal combination" + " of values AutoNeg. and DuplexCap.\n Using " + "Full Duplex\n", pAC->dev[1]->name); + + DuplexCap = DC_FULL; + } + if (AutoSet && AutoNeg==AN_OFF && !DupSet) { + DuplexCap = DC_FULL; + } + + if (!AutoSet && DupSet) { + printk("%s, Port B: Duplex setting not" + " possible in\n default AutoNegotiation mode" + " (Sense).\n Using AutoNegotiation On\n", + pAC->dev[1]->name); + AutoNeg = AN_ON; + } + + /* set the desired mode */ + pAC->GIni.GP[1].PLinkModeConf = + Capabilities[AutoNeg][DuplexCap]; + + pAC->GIni.GP[1].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + if (FlowCtrl_B != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(FlowCtrl_B[pAC->Index],"") == 0) { + } + else if (strcmp(FlowCtrl_B[pAC->Index],"SymOrRem") == 0) { + pAC->GIni.GP[1].PFlowCtrlMode = + SK_FLOW_MODE_SYM_OR_REM; + } + else if (strcmp(FlowCtrl_B[pAC->Index],"Sym")==0) { + pAC->GIni.GP[1].PFlowCtrlMode = + SK_FLOW_MODE_SYMMETRIC; + } + else if (strcmp(FlowCtrl_B[pAC->Index],"LocSend")==0) { + pAC->GIni.GP[1].PFlowCtrlMode = + SK_FLOW_MODE_LOC_SEND; + } + else if (strcmp(FlowCtrl_B[pAC->Index],"None")==0) { + pAC->GIni.GP[1].PFlowCtrlMode = + SK_FLOW_MODE_NONE; + } + else printk("Illegal value for FlowCtrl_B\n"); + } + if (AutoNeg==AN_OFF && pAC->GIni.GP[1].PFlowCtrlMode!= + SK_FLOW_MODE_NONE) { + printk("%s, Port B: FlowControl" + " impossible without AutoNegotiation," + " disabled\n", pAC->dev[1]->name); + pAC->GIni.GP[1].PFlowCtrlMode = SK_FLOW_MODE_NONE; + } + + MSMode = SK_MS_MODE_AUTO; /* default: do auto select */ + if (Role_B != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(Role_B[pAC->Index],"")==0) { + } + else if (strcmp(Role_B[pAC->Index],"Auto")==0) { + MSMode = SK_MS_MODE_AUTO; + } + else if (strcmp(Role_B[pAC->Index],"Master")==0) { + MSMode = SK_MS_MODE_MASTER; + } + else if (strcmp(Role_B[pAC->Index],"Slave")==0) { + MSMode = SK_MS_MODE_SLAVE; + } + else printk("%s: Illegal value for Role_B\n", + pAC->dev[1]->name); + } + pAC->GIni.GP[1].PMSMode = MSMode; + + + /* settings for both ports */ + pAC->ActivePort = 0; + if (PrefPort != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(PrefPort[pAC->Index],"") == 0) { /* Auto */ + pAC->ActivePort = 0; + pAC->Rlmt.Net[0].Preference = -1; /* auto */ + pAC->Rlmt.Net[0].PrefPort = 0; + } + else if (strcmp(PrefPort[pAC->Index],"A") == 0) { + /* + * do not set ActivePort here, thus a port + * switch is issued after net up. + */ + Port = 0; + pAC->Rlmt.Net[0].Preference = Port; + pAC->Rlmt.Net[0].PrefPort = Port; + } + else if (strcmp(PrefPort[pAC->Index],"B") == 0) { + /* + * do not set ActivePort here, thus a port + * switch is issued after net up. + */ + Port = 1; + pAC->Rlmt.Net[0].Preference = Port; + pAC->Rlmt.Net[0].PrefPort = Port; + } + else printk("%s: Illegal value for PrefPort\n", + pAC->dev[0]->name); + } + + pAC->RlmtNets = 1; + + if (RlmtMode != NULL && pAC->IndexIndex] != NULL) { + if (strcmp(RlmtMode[pAC->Index], "") == 0) { + pAC->RlmtMode = 0; + } + else if (strcmp(RlmtMode[pAC->Index], "CheckLinkState") == 0) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK; + } + else if (strcmp(RlmtMode[pAC->Index], "CheckLocalPort") == 0) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK | + SK_RLMT_CHECK_LOC_LINK; + } + else if (strcmp(RlmtMode[pAC->Index], "CheckSeg") == 0) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK | + SK_RLMT_CHECK_LOC_LINK | + SK_RLMT_CHECK_SEG; + } + else if ((strcmp(RlmtMode[pAC->Index], "DualNet") == 0) && + (pAC->GIni.GIMacsFound == 2)) { + pAC->RlmtMode = SK_RLMT_CHECK_LINK; + pAC->RlmtNets = 2; + } + else { + printk("%s: Illegal value for" + " RlmtMode, using default\n", pAC->dev[0]->name); + pAC->RlmtMode = 0; + } + } + else { + pAC->RlmtMode = 0; + } +} /* GetConfiguration */ + + +/***************************************************************************** + * + * ProductStr - return a adapter identification string from vpd + * + * Description: + * This function reads the product name string from the vpd area + * and puts it the field pAC->DeviceString. + * + * Returns: N/A + */ +static void ProductStr( +SK_AC *pAC /* pointer to adapter context */ +) +{ +int StrLen = 80; /* length of the string, defined in SK_AC */ +char Keyword[] = VPD_NAME; /* vpd productname identifier */ +int ReturnCode; /* return code from vpd_read */ +unsigned long Flags; + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + ReturnCode = VpdRead(pAC, pAC->IoBase, Keyword, pAC->DeviceStr, + &StrLen); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + if (ReturnCode != 0) { + /* there was an error reading the vpd data */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR, + ("Error reading VPD data: %d\n", ReturnCode)); + pAC->DeviceStr[0] = '\0'; + } +} /* ProductStr */ + + +/****************************************************************************/ +/* functions for common modules *********************************************/ +/****************************************************************************/ + + +/***************************************************************************** + * + * SkDrvAllocRlmtMbuf - allocate an RLMT mbuf + * + * Description: + * This routine returns an RLMT mbuf or NULL. The RLMT Mbuf structure + * is embedded into a socket buff data area. + * + * Context: + * runtime + * + * Returns: + * NULL or pointer to Mbuf. + */ +SK_MBUF *SkDrvAllocRlmtMbuf( +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* the IO-context */ +unsigned BufferSize) /* size of the requested buffer */ +{ +SK_MBUF *pRlmtMbuf; /* pointer to a new rlmt-mbuf structure */ +struct sk_buff *pMsgBlock; /* pointer to a new message block */ + + pMsgBlock = alloc_skb(BufferSize + sizeof(SK_MBUF), GFP_ATOMIC); + if (pMsgBlock == NULL) { + return (NULL); + } + pRlmtMbuf = (SK_MBUF*) pMsgBlock->data; + skb_reserve(pMsgBlock, sizeof(SK_MBUF)); + pRlmtMbuf->pNext = NULL; + pRlmtMbuf->pOs = pMsgBlock; + pRlmtMbuf->pData = pMsgBlock->data; /* Data buffer. */ + pRlmtMbuf->Size = BufferSize; /* Data buffer size. */ + pRlmtMbuf->Length = 0; /* Length of packet (<= Size). */ + return (pRlmtMbuf); + +} /* SkDrvAllocRlmtMbuf */ + + +/***************************************************************************** + * + * SkDrvFreeRlmtMbuf - free an RLMT mbuf + * + * Description: + * This routine frees one or more RLMT mbuf(s). + * + * Context: + * runtime + * + * Returns: + * Nothing + */ +void SkDrvFreeRlmtMbuf( +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* the IO-context */ +SK_MBUF *pMbuf) /* size of the requested buffer */ +{ +SK_MBUF *pFreeMbuf; +SK_MBUF *pNextMbuf; + + pFreeMbuf = pMbuf; + do { + pNextMbuf = pFreeMbuf->pNext; + DEV_KFREE_SKB_ANY(pFreeMbuf->pOs); + pFreeMbuf = pNextMbuf; + } while ( pFreeMbuf != NULL ); +} /* SkDrvFreeRlmtMbuf */ + + +/***************************************************************************** + * + * SkOsGetTime - provide a time value + * + * Description: + * This routine provides a time value. The unit is 1/HZ (defined by Linux). + * It is not used for absolute time, but only for time differences. + * + * + * Returns: + * Time value + */ +SK_U64 SkOsGetTime(SK_AC *pAC) +{ +#if 0 + return jiffies; +#else + return get_timer(0); +#endif +} /* SkOsGetTime */ + + +/***************************************************************************** + * + * SkPciReadCfgDWord - read a 32 bit value from pci config space + * + * Description: + * This routine reads a 32 bit value from the pci configuration + * space. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciReadCfgDWord( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U32 *pVal) /* pointer to store the read value */ +{ + pci_read_config_dword(pAC->PciDev, PciAddr, pVal); + return(0); +} /* SkPciReadCfgDWord */ + + +/***************************************************************************** + * + * SkPciReadCfgWord - read a 16 bit value from pci config space + * + * Description: + * This routine reads a 16 bit value from the pci configuration + * space. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciReadCfgWord( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U16 *pVal) /* pointer to store the read value */ +{ + pci_read_config_word(pAC->PciDev, PciAddr, pVal); + return(0); +} /* SkPciReadCfgWord */ + + +/***************************************************************************** + * + * SkPciReadCfgByte - read a 8 bit value from pci config space + * + * Description: + * This routine reads a 8 bit value from the pci configuration + * space. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciReadCfgByte( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U8 *pVal) /* pointer to store the read value */ +{ + pci_read_config_byte(pAC->PciDev, PciAddr, pVal); + return(0); +} /* SkPciReadCfgByte */ + + +/***************************************************************************** + * + * SkPciWriteCfgDWord - write a 32 bit value to pci config space + * + * Description: + * This routine writes a 32 bit value to the pci configuration + * space. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciWriteCfgDWord( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U32 Val) /* pointer to store the read value */ +{ + pci_write_config_dword(pAC->PciDev, PciAddr, Val); + return(0); +} /* SkPciWriteCfgDWord */ + + +/***************************************************************************** + * + * SkPciWriteCfgWord - write a 16 bit value to pci config space + * + * Description: + * This routine writes a 16 bit value to the pci configuration + * space. The flag PciConfigUp indicates whether the config space + * is accesible or must be set up first. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciWriteCfgWord( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U16 Val) /* pointer to store the read value */ +{ + pci_write_config_word(pAC->PciDev, PciAddr, Val); + return(0); +} /* SkPciWriteCfgWord */ + + +/***************************************************************************** + * + * SkPciWriteCfgWord - write a 8 bit value to pci config space + * + * Description: + * This routine writes a 8 bit value to the pci configuration + * space. The flag PciConfigUp indicates whether the config space + * is accesible or must be set up first. + * + * Returns: + * 0 - indicate everything worked ok. + * != 0 - error indication + */ +int SkPciWriteCfgByte( +SK_AC *pAC, /* Adapter Control structure pointer */ +int PciAddr, /* PCI register address */ +SK_U8 Val) /* pointer to store the read value */ +{ + pci_write_config_byte(pAC->PciDev, PciAddr, Val); + return(0); +} /* SkPciWriteCfgByte */ + + +/***************************************************************************** + * + * SkDrvEvent - handle driver events + * + * Description: + * This function handles events from all modules directed to the driver + * + * Context: + * Is called under protection of slow path lock. + * + * Returns: + * 0 if everything ok + * < 0 on error + * + */ +int SkDrvEvent( +SK_AC *pAC, /* pointer to adapter context */ +SK_IOC IoC, /* io-context */ +SK_U32 Event, /* event-id */ +SK_EVPARA Param) /* event-parameter */ +{ +SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */ +struct sk_buff *pMsg; /* pointer to a message block */ +int FromPort; /* the port from which we switch away */ +int ToPort; /* the port we switch to */ +SK_EVPARA NewPara; /* parameter for further events */ +#if 0 +int Stat; +#endif +unsigned long Flags; +SK_BOOL DualNet; + + switch (Event) { + case SK_DRV_ADAP_FAIL: + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("ADAPTER FAIL EVENT\n")); + printk("%s: Adapter failed.\n", pAC->dev[0]->name); + /* disable interrupts */ + SK_OUT32(pAC->IoBase, B0_IMSK, 0); + /* cgoos */ + break; + case SK_DRV_PORT_FAIL: + FromPort = Param.Para32[0]; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("PORT FAIL EVENT, Port: %d\n", FromPort)); + if (FromPort == 0) { + printk("%s: Port A failed.\n", pAC->dev[0]->name); + } else { + printk("%s: Port B failed.\n", pAC->dev[1]->name); + } + /* cgoos */ + break; + case SK_DRV_PORT_RESET: /* SK_U32 PortIdx */ + /* action list 4 */ + FromPort = Param.Para32[0]; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("PORT RESET EVENT, Port: %d ", FromPort)); + NewPara.Para64 = FromPort; + SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara); + spin_lock_irqsave( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST); +#if 0 + pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING; +#endif + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + + /* clear rx ring from received frames */ + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); + + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + spin_lock_irqsave( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + + /* tschilling: Handling of return value inserted. */ + if (SkGeInitPort(pAC, IoC, FromPort)) { + if (FromPort == 0) { + printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name); + } else { + printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name); + } + } + SkAddrMcUpdate(pAC,IoC, FromPort); + PortReInitBmu(pAC, FromPort); + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); + ClearAndStartRx(pAC, FromPort); + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + break; + case SK_DRV_NET_UP: /* SK_U32 PortIdx */ + /* action list 5 */ + FromPort = Param.Para32[0]; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("NET UP EVENT, Port: %d ", Param.Para32[0])); +#ifdef SK98_INFO + printk("%s: network connection up using" + " port %c\n", pAC->dev[Param.Para32[0]]->name, 'A'+Param.Para32[0]); + + /* tschilling: Values changed according to LinkSpeedUsed. */ + Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed; + if (Stat == SK_LSPEED_STAT_10MBPS) { + printk(" speed: 10\n"); + } else if (Stat == SK_LSPEED_STAT_100MBPS) { + printk(" speed: 100\n"); + } else if (Stat == SK_LSPEED_STAT_1000MBPS) { + printk(" speed: 1000\n"); + } else { + printk(" speed: unknown\n"); + } + + Stat = pAC->GIni.GP[FromPort].PLinkModeStatus; + if (Stat == SK_LMODE_STAT_AUTOHALF || + Stat == SK_LMODE_STAT_AUTOFULL) { + printk(" autonegotiation: yes\n"); + } + else { + printk(" autonegotiation: no\n"); + } + if (Stat == SK_LMODE_STAT_AUTOHALF || + Stat == SK_LMODE_STAT_HALF) { + printk(" duplex mode: half\n"); + } + else { + printk(" duplex mode: full\n"); + } + Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus; + if (Stat == SK_FLOW_STAT_REM_SEND ) { + printk(" flowctrl: remote send\n"); + } + else if (Stat == SK_FLOW_STAT_LOC_SEND ){ + printk(" flowctrl: local send\n"); + } + else if (Stat == SK_FLOW_STAT_SYMMETRIC ){ + printk(" flowctrl: symmetric\n"); + } + else { + printk(" flowctrl: none\n"); + } + + /* tschilling: Check against CopperType now. */ + if ((pAC->GIni.GICopperType == SK_TRUE) && + (pAC->GIni.GP[FromPort].PLinkSpeedUsed == + SK_LSPEED_STAT_1000MBPS)) { + Stat = pAC->GIni.GP[FromPort].PMSStatus; + if (Stat == SK_MS_STAT_MASTER ) { + printk(" role: master\n"); + } + else if (Stat == SK_MS_STAT_SLAVE ) { + printk(" role: slave\n"); + } + else { + printk(" role: ???\n"); + } + } + +#ifdef SK_ZEROCOPY + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) + printk(" scatter-gather: enabled\n"); + else + printk(" scatter-gather: disabled\n"); + +#else + printk(" scatter-gather: disabled\n"); +#endif +#endif /* SK98_INFO */ + + if ((Param.Para32[0] != pAC->ActivePort) && + (pAC->RlmtNets == 1)) { + NewPara.Para32[0] = pAC->ActivePort; + NewPara.Para32[1] = Param.Para32[0]; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN, + NewPara); + } + + /* Inform the world that link protocol is up. */ +#if 0 + pAC->dev[Param.Para32[0]]->flags |= IFF_RUNNING; +#endif + + break; + case SK_DRV_NET_DOWN: /* SK_U32 Reason */ + /* action list 7 */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("NET DOWN EVENT ")); +#ifdef SK98_INFO + printk("%s: network connection down\n", pAC->dev[Param.Para32[1]]->name); +#endif +#if 0 + pAC->dev[Param.Para32[1]]->flags &= ~IFF_RUNNING; +#endif + break; + case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("PORT SWITCH HARD ")); + case SK_DRV_SWITCH_SOFT: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ + /* action list 6 */ + printk("%s: switching to port %c\n", pAC->dev[0]->name, + 'A'+Param.Para32[1]); + case SK_DRV_SWITCH_INTERN: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ + FromPort = Param.Para32[0]; + ToPort = Param.Para32[1]; + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("PORT SWITCH EVENT, From: %d To: %d (Pref %d) ", + FromPort, ToPort, pAC->Rlmt.Net[0].PrefPort)); + NewPara.Para64 = FromPort; + SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara); + NewPara.Para64 = ToPort; + SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara); + spin_lock_irqsave( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + spin_lock_irqsave( + &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST); + SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST); + spin_unlock_irqrestore( + &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */ + ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */ + + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]); + ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]); + spin_lock_irqsave( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + spin_lock_irqsave( + &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + pAC->ActivePort = ToPort; +#if 0 + SetQueueSizes(pAC); +#else + /* tschilling: New common function with minimum size check. */ + DualNet = SK_FALSE; + if (pAC->RlmtNets == 2) { + DualNet = SK_TRUE; + } + + if (SkGeInitAssignRamToQueues( + pAC, + pAC->ActivePort, + DualNet)) { + spin_unlock_irqrestore( + &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + printk("SkGeInitAssignRamToQueues failed.\n"); + break; + } +#endif + /* tschilling: Handling of return values inserted. */ + if (SkGeInitPort(pAC, IoC, FromPort) || + SkGeInitPort(pAC, IoC, ToPort)) { + printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name); + } + if (Event == SK_DRV_SWITCH_SOFT) { + SkMacRxTxEnable(pAC, IoC, FromPort); + } + SkMacRxTxEnable(pAC, IoC, ToPort); + SkAddrSwap(pAC, IoC, FromPort, ToPort); + SkAddrMcUpdate(pAC, IoC, FromPort); + SkAddrMcUpdate(pAC, IoC, ToPort); + PortReInitBmu(pAC, FromPort); + PortReInitBmu(pAC, ToPort); + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE); + SkGePollTxD(pAC, IoC, ToPort, SK_TRUE); + ClearAndStartRx(pAC, FromPort); + ClearAndStartRx(pAC, ToPort); + spin_unlock_irqrestore( + &pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags); + spin_unlock_irqrestore( + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, + Flags); + break; + case SK_DRV_RLMT_SEND: /* SK_MBUF *pMb */ + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("RLS ")); + pRlmtMbuf = (SK_MBUF*) Param.pParaPtr; + pMsg = (struct sk_buff*) pRlmtMbuf->pOs; + skb_put(pMsg, pRlmtMbuf->Length); + if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW], + pMsg) < 0) + + DEV_KFREE_SKB_ANY(pMsg); + break; + default: + break; + } + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, + ("END EVENT ")); + + return (0); +} /* SkDrvEvent */ + + +/***************************************************************************** + * + * SkErrorLog - log errors + * + * Description: + * This function logs errors to the system buffer and to the console + * + * Returns: + * 0 if everything ok + * < 0 on error + * + */ +void SkErrorLog( +SK_AC *pAC, +int ErrClass, +int ErrNum, +char *pErrorMsg) +{ +char ClassStr[80]; + + switch (ErrClass) { + case SK_ERRCL_OTHER: + strcpy(ClassStr, "Other error"); + break; + case SK_ERRCL_CONFIG: + strcpy(ClassStr, "Configuration error"); + break; + case SK_ERRCL_INIT: + strcpy(ClassStr, "Initialization error"); + break; + case SK_ERRCL_NORES: + strcpy(ClassStr, "Out of resources error"); + break; + case SK_ERRCL_SW: + strcpy(ClassStr, "internal Software error"); + break; + case SK_ERRCL_HW: + strcpy(ClassStr, "Hardware failure"); + break; + case SK_ERRCL_COMM: + strcpy(ClassStr, "Communication error"); + break; + } + printk(KERN_INFO "%s: -- ERROR --\n Class: %s\n" + " Nr: 0x%x\n Msg: %s\n", pAC->dev[0]->name, + ClassStr, ErrNum, pErrorMsg); + +} /* SkErrorLog */ + +#ifdef DEBUG +/****************************************************************************/ +/* "debug only" section *****************************************************/ +/****************************************************************************/ + + +/***************************************************************************** + * + * DumpMsg - print a frame + * + * Description: + * This function prints frames to the system logfile/to the console. + * + * Returns: N/A + * + */ +static void DumpMsg(struct sk_buff *skb, char *str) +{ + int msglen; + + if (skb == NULL) { + printk("DumpMsg(): NULL-Message\n"); + return; + } + + if (skb->data == NULL) { + printk("DumpMsg(): Message empty\n"); + return; + } + + msglen = skb->len; + if (msglen > 64) + msglen = 64; + + printk("--- Begin of message from %s , len %d (from %d) ----\n", str, msglen, skb->len); + + DumpData((char *)skb->data, msglen); + + printk("------- End of message ---------\n"); +} /* DumpMsg */ + + +/***************************************************************************** + * + * DumpData - print a data area + * + * Description: + * This function prints a area of data to the system logfile/to the + * console. + * + * Returns: N/A + * + */ +static void DumpData(char *p, int size) +{ +register int i; +int haddr, addr; +char hex_buffer[180]; +char asc_buffer[180]; +char HEXCHAR[] = "0123456789ABCDEF"; + + addr = 0; + haddr = 0; + hex_buffer[0] = 0; + asc_buffer[0] = 0; + for (i=0; i < size; ) { + if (*p >= '0' && *p <='z') + asc_buffer[addr] = *p; + else + asc_buffer[addr] = '.'; + addr++; + asc_buffer[addr] = 0; + hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4]; + haddr++; + hex_buffer[haddr] = HEXCHAR[*p & 0x0f]; + haddr++; + hex_buffer[haddr] = ' '; + haddr++; + hex_buffer[haddr] = 0; + p++; + i++; + if (i%16 == 0) { + printk("%s %s\n", hex_buffer, asc_buffer); + addr = 0; + haddr = 0; + } + } +} /* DumpData */ + + +/***************************************************************************** + * + * DumpLong - print a data area as long values + * + * Description: + * This function prints a area of data to the system logfile/to the + * console. + * + * Returns: N/A + * + */ +static void DumpLong(char *pc, int size) +{ +register int i; +int haddr, addr; +char hex_buffer[180]; +char asc_buffer[180]; +char HEXCHAR[] = "0123456789ABCDEF"; +long *p; +int l; + + addr = 0; + haddr = 0; + hex_buffer[0] = 0; + asc_buffer[0] = 0; + p = (long*) pc; + for (i=0; i < size; ) { + l = (long) *p; + hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 24) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 20) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 16) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 12) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 8) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[(l >> 4) & 0xf]; + haddr++; + hex_buffer[haddr] = HEXCHAR[l & 0x0f]; + haddr++; + hex_buffer[haddr] = ' '; + haddr++; + hex_buffer[haddr] = 0; + p++; + i++; + if (i%8 == 0) { + printk("%4x %s\n", (i-8)*4, hex_buffer); + haddr = 0; + } + } + printk("------------------------\n"); +} /* DumpLong */ + +#endif + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skgehwt.c b/drivers/sk98lin/skgehwt.c new file mode 100644 index 000000000..f8681a8b0 --- /dev/null +++ b/drivers/sk98lin/skgehwt.c @@ -0,0 +1,220 @@ +/****************************************************************************** + * + * Name: skgehwt.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.13 $ + * Date: $Date: 1999/11/22 13:31:12 $ + * Purpose: Hardware Timer. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgehwt.c,v $ + * Revision 1.13 1999/11/22 13:31:12 cgoos + * Changed license header to GPL. + * + * Revision 1.12 1998/10/15 15:11:34 gklug + * fix: ID_sccs to SysKonnectFileId + * + * Revision 1.11 1998/10/08 15:27:51 gklug + * chg: correction factor is host clock dependent + * + * Revision 1.10 1998/09/15 14:18:31 cgoos + * Changed more BOOLEANs to SK_xxx + * + * Revision 1.9 1998/09/15 14:16:06 cgoos + * Changed line 107: FALSE to SK_FALSE + * + * Revision 1.8 1998/08/24 13:04:44 gklug + * fix: typo + * + * Revision 1.7 1998/08/19 09:50:49 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.6 1998/08/17 09:59:02 gklug + * fix: typos + * + * Revision 1.5 1998/08/14 07:09:10 gklug + * fix: chg pAc -> pAC + * + * Revision 1.4 1998/08/10 14:14:52 gklug + * rmv: unneccessary SK_ADDR macro + * + * Revision 1.3 1998/08/07 12:53:44 gklug + * fix: first compiled version + * + * Revision 1.2 1998/08/07 09:19:29 gklug + * adapt functions to the C coding conventions + * rmv unneccessary functions. + * + * Revision 1.1 1998/08/05 11:28:36 gklug + * first version: adapted from SMT/FDDI + * + * + * + * + ******************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +/* + Event queue and dispatcher +*/ +static const char SysKonnectFileId[] = + "$Header: /usr56/projects/ge/schedule/skgehwt.c,v 1.13 1999/11/22 13:31:12 cgoos Exp $" ; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef __C2MAN__ +/* + Hardware Timer function queue management. + + General Description: + + */ +intro() +{} +#endif + +/* + * Prototypes of local functions. + */ +#define SK_HWT_MAX (65000) + +/* correction factor */ +#define SK_HWT_FAC (1000 * (SK_U32)pAC->GIni.GIHstClkFact / 100) + +/* + * Initialize hardware timer. + * + * Must be called during init level 1. + */ +void SkHwtInit( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc) /* IoContext */ +{ + pAC->Hwt.TStart = 0 ; + pAC->Hwt.TStop = 0 ; + pAC->Hwt.TActive = SK_FALSE ; + + SkHwtStop(pAC,Ioc) ; +} + +/* + * + * Start hardware timer (clock ticks are 16us). + * + */ +void SkHwtStart( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc, /* IoContext */ +SK_U32 Time) /* Time in units of 16us to load the timer with. */ +{ + SK_U32 Cnt ; + + if (Time > SK_HWT_MAX) + Time = SK_HWT_MAX ; + + pAC->Hwt.TStart = Time ; + pAC->Hwt.TStop = 0L ; + + Cnt = Time ; + + /* + * if time < 16 us + * time = 16 us + */ + if (!Cnt) { + Cnt++ ; + } + + SK_OUT32(Ioc, B2_TI_INI, Cnt * SK_HWT_FAC) ; + SK_OUT16(Ioc, B2_TI_CRTL, TIM_START) ; /* Start timer. */ + + pAC->Hwt.TActive = SK_TRUE ; +} + +/* + * Stop hardware timer. + * and clear the timer IRQ + */ +void SkHwtStop( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc) /* IoContext */ +{ + SK_OUT16(Ioc, B2_TI_CRTL, TIM_STOP) ; + SK_OUT16(Ioc, B2_TI_CRTL, TIM_CLR_IRQ) ; + + pAC->Hwt.TActive = SK_FALSE ; +} + + +/* + * Stop hardware timer and read time elapsed since last start. + * + * returns + * The elapsed time since last start in units of 16us. + * + */ +SK_U32 SkHwtRead( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc) /* IoContext */ +{ + SK_U32 TRead ; + SK_U32 IStatus ; + + if (pAC->Hwt.TActive) { + SkHwtStop(pAC,Ioc) ; + + SK_IN32(Ioc, B2_TI_VAL, &TRead); + TRead /= SK_HWT_FAC; + + SK_IN32(Ioc, B0_ISRC, &IStatus); + + /* Check if timer expired (or wraparound). */ + if ((TRead > pAC->Hwt.TStart) || (IStatus & IS_TIMINT)) { + SkHwtStop(pAC,Ioc) ; + pAC->Hwt.TStop = pAC->Hwt.TStart ; + } else { + pAC->Hwt.TStop = pAC->Hwt.TStart - TRead ; + } + } + return (pAC->Hwt.TStop) ; +} + +/* + * interrupt source= timer + */ +void SkHwtIsr( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc) /* IoContext */ +{ + SkHwtStop(pAC,Ioc); + pAC->Hwt.TStop = pAC->Hwt.TStart; + SkTimerDone(pAC,Ioc) ; +} + +#endif /* CONFIG_SK98 */ + +/* End of file */ diff --git a/drivers/sk98lin/skgeinit.c b/drivers/sk98lin/skgeinit.c new file mode 100644 index 000000000..a18dc0a48 --- /dev/null +++ b/drivers/sk98lin/skgeinit.c @@ -0,0 +1,2372 @@ +/****************************************************************************** + * + * Name: skgeinit.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.85 $ + * Date: $Date: 2003/02/05 15:30:33 $ + * Purpose: Contains functions to initialize the GE HW + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgeinit.c,v $ + * Revision 1.85 2003/02/05 15:30:33 rschmidt + * Corrected setting of GIHstClkFact (Host Clock Factor) and + * GIPollTimerVal (Descr. Poll Timer Init Value) for YUKON. + * Editorial changes. + * + * Revision 1.84 2003/01/28 09:57:25 rschmidt + * Added detection of YUKON-Lite Rev. A0 (stored in GIYukonLite). + * Disabled Rx GMAC FIFO Flush for YUKON-Lite Rev. A0. + * Added support for CLK_RUN (YUKON-Lite). + * Added additional check of PME from D3cold for setting GIVauxAvail. + * Editorial changes. + * + * Revision 1.83 2002/12/17 16:15:41 rschmidt + * Added default setting of PhyType (Copper) for YUKON. + * Added define around check for HW self test results. + * Editorial changes. + * + * Revision 1.82 2002/12/05 13:40:21 rschmidt + * Added setting of Rx GMAC FIFO Flush Mask register. + * Corrected PhyType with new define SK_PHY_MARV_FIBER when + * YUKON Fiber board was found. + * Editorial changes. + * + * Revision 1.81 2002/11/15 12:48:35 rschmidt + * Replaced message SKERR_HWI_E018 with SKERR_HWI_E024 for Rx queue error + * in SkGeStopPort(). + * Added init for pAC->GIni.GIGenesis with SK_FALSE in YUKON-branch. + * Editorial changes. + * + * Revision 1.80 2002/11/12 17:28:30 rschmidt + * Initialized GIPciSlot64 and GIPciClock66 in SkGeInit1(). + * Reduced PCI FIFO watermarks for 32bit/33MHz bus in SkGeInitBmu(). + * Editorial changes. + * + * Revision 1.79 2002/10/21 09:31:02 mkarl + * Changed SkGeInitAssignRamToQueues(), removed call to + * SkGeInitAssignRamToQueues in SkGeInit1 and fixed compiler warning in + * SkGeInit1. + * + * Revision 1.78 2002/10/16 15:55:07 mkarl + * Fixed a bug in SkGeInitAssignRamToQueues. + * + * Revision 1.77 2002/10/14 15:07:22 rschmidt + * Corrected timeout handling for Rx queue in SkGeStopPort() (#10748) + * Editorial changes. + * + * Revision 1.76 2002/10/11 09:24:38 mkarl + * Added check for HW self test results. + * + * Revision 1.75 2002/10/09 16:56:44 mkarl + * Now call SkGeInitAssignRamToQueues() in Init Level 1 in order to assign + * the adapter memory to the queues. This default assignment is not suitable + * for dual net mode. + * + * Revision 1.74 2002/09/12 08:45:06 rwahl + * Set defaults for PMSCap, PLinkSpeed & PLinkSpeedCap dependent on PHY. + * + * Revision 1.73 2002/08/16 15:19:45 rschmidt + * Corrected check for Tx queues in SkGeCheckQSize(). + * Added init for new entry GIGenesis and GICopperType + * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis. + * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros. + * + * Revision 1.72 2002/08/12 13:38:55 rschmidt + * Added check if VAUX is available (stored in GIVauxAvail) + * Initialized PLinkSpeedCap in Port struct with SK_LSPEED_CAP_1000MBPS + * Editorial changes. + * + * Revision 1.71 2002/08/08 16:32:58 rschmidt + * Added check for Tx queues in SkGeCheckQSize(). + * Added start of Time Stamp Timer (YUKON) in SkGeInit2(). + * Editorial changes. + * + * Revision 1.70 2002/07/23 16:04:26 rschmidt + * Added init for GIWolOffs (HW-Bug in YUKON 1st rev.) + * Minor changes + * + * Revision 1.69 2002/07/17 17:07:08 rwahl + * - SkGeInit1(): fixed PHY type debug output; corrected init of GIFunc + * table & GIMacType. + * - Editorial changes. + * + * Revision 1.68 2002/07/15 18:38:31 rwahl + * Added initialization for MAC type dependent function table. + * + * Revision 1.67 2002/07/15 15:45:39 rschmidt + * Added Tx Store & Forward for YUKON (GMAC Tx FIFO is only 1 kB) + * Replaced SK_PHY_MARV by SK_PHY_MARV_COPPER + * Editorial changes + * + * Revision 1.66 2002/06/10 09:35:08 rschmidt + * Replaced C++ comments (//) + * Editorial changes + * + * Revision 1.65 2002/06/05 08:33:37 rschmidt + * Changed GIRamSize and Reset sequence for YUKON. + * SkMacInit() replaced by SkXmInitMac() resp. SkGmInitMac() + * + * Revision 1.64 2002/04/25 13:03:20 rschmidt + * Changes for handling YUKON. + * Removed reference to xmac_ii.h (not necessary). + * Moved all defines into header file. + * Replaced all SkXm...() functions with SkMac...() to handle also + * YUKON's GMAC. + * Added handling for GMAC FIFO in SkGeInitMacFifo(), SkGeStopPort(). + * Removed 'goto'-directive from SkGeCfgSync(), SkGeCheckQSize(). + * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(), + * SkMacFlushTxFifo(). + * Optimized timeout handling in SkGeStopPort(). + * Initialized PLinkSpeed in Port struct with SK_LSPEED_AUTO. + * Release of GMAC Link Control reset in SkGeInit1(). + * Initialized GIChipId and GIChipRev in GE Init structure. + * Added GIRamSize and PhyType values for YUKON. + * Removed use of PRxCmd to setup XMAC. + * Moved setting of XM_RX_DIS_CEXT to SkXmInitMac(). + * Use of SkGeXmitLED() only for GENESIS. + * Changes for V-CPU support. + * Editorial changes. + * + * Revision 1.63 2001/04/05 11:02:09 rassmann + * Stop Port check of the STOP bit did not take 2/18 sec as wanted. + * + * Revision 1.62 2001/02/07 07:54:21 rassmann + * Corrected copyright. + * + * Revision 1.61 2001/01/31 15:31:40 gklug + * fix: problem with autosensing an SR8800 switch + * + * Revision 1.60 2000/10/18 12:22:21 cgoos + * Added workaround for half duplex hangup. + * + * Revision 1.59 2000/10/10 11:22:06 gklug + * add: in manual half duplex mode ignore carrier extension errors + * + * Revision 1.58 2000/10/02 14:10:27 rassmann + * Reading BCOM PHY after releasing reset until it returns a valid value. + * + * Revision 1.57 2000/08/03 14:55:28 rassmann + * Waiting for I2C to be ready before de-initializing adapter + * (prevents sensors from hanging up). + * + * Revision 1.56 2000/07/27 12:16:48 gklug + * fix: Stop Port check of the STOP bit does now take 2/18 sec as wanted + * + * Revision 1.55 1999/11/22 13:32:26 cgoos + * Changed license header to GPL. + * + * Revision 1.54 1999/10/26 07:32:54 malthoff + * Initialize PHWLinkUp with SK_FALSE. Required for Diagnostics. + * + * Revision 1.53 1999/08/12 19:13:50 malthoff + * Fix for 1000BT. Do not owerwrite XM_MMU_CMD when + * disabling receiver and transmitter. Other bits + * may be lost. + * + * Revision 1.52 1999/07/01 09:29:54 gklug + * fix: DoInitRamQueue needs pAC + * + * Revision 1.51 1999/07/01 08:42:21 gklug + * chg: use Store & forward for RAM buffer when Jumbos are used + * + * Revision 1.50 1999/05/27 13:19:38 cgoos + * Added Tx PCI watermark initialization. + * Removed Tx RAM queue Store & Forward setting. + * + * Revision 1.49 1999/05/20 14:32:45 malthoff + * SkGeLinkLED() is completly removed now. + * + * Revision 1.48 1999/05/19 07:28:24 cgoos + * SkGeLinkLED no more available for drivers. + * Changes for 1000Base-T. + * + * Revision 1.47 1999/04/08 13:57:45 gklug + * add: Init of new port struct fiels PLinkResCt + * chg: StopPort Timer check + * + * Revision 1.46 1999/03/25 07:42:15 malthoff + * SkGeStopPort(): Add workaround for cache incoherency. + * Create error log entry, disable port, and + * exit loop if it does not terminate. + * Add XM_RX_LENERR_OK to the default value for the + * XMAC receive command register. + * + * Revision 1.45 1999/03/12 16:24:47 malthoff + * Remove PPollRxD and PPollTxD. + * Add check for GIPollTimerVal. + * + * Revision 1.44 1999/03/12 13:40:23 malthoff + * Fix: SkGeXmitLED(), SK_LED_TST mode does not work. + * Add: Jumbo frame support. + * Chg: Resolution of parameter IntTime in SkGeCfgSync(). + * + * Revision 1.43 1999/02/09 10:29:46 malthoff + * Bugfix: The previous modification again also for the second location. + * + * Revision 1.42 1999/02/09 09:35:16 malthoff + * Bugfix: The bits '66 MHz Capable' and 'NEWCAP are reset while + * clearing the error bits in the PCI status register. + * + * Revision 1.41 1999/01/18 13:07:02 malthoff + * Bugfix: Do not use CFG cycles after during Init- or Runtime, because + * they may not be available after Boottime. + * + * Revision 1.40 1999/01/11 12:40:49 malthoff + * Bug fix: PCI_STATUS: clearing error bits sets the UDF bit. + * + * Revision 1.39 1998/12/11 15:17:33 gklug + * chg: Init LipaAutoNeg with Unknown + * + * Revision 1.38 1998/12/10 11:02:57 malthoff + * Disable Error Log Message when calling SkGeInit(level 2) + * more than once. + * + * Revision 1.37 1998/12/07 12:18:25 gklug + * add: refinement of autosense mode: take into account the autoneg cap of LiPa + * + * Revision 1.36 1998/12/07 07:10:39 gklug + * fix: init values of LinkBroken/ Capabilities for management + * + * Revision 1.35 1998/12/02 10:56:20 gklug + * fix: do NOT init LoinkSync Counter. + * + * Revision 1.34 1998/12/01 10:53:21 gklug + * add: init of additional Counters for workaround + * + * Revision 1.33 1998/12/01 10:00:49 gklug + * add: init PIsave var in Port struct + * + * Revision 1.32 1998/11/26 14:50:40 gklug + * chg: Default is autosensing with AUTOFULL mode + * + * Revision 1.31 1998/11/25 15:36:16 gklug + * fix: do NOT stop LED Timer when port should be stopped + * + * Revision 1.30 1998/11/24 13:15:28 gklug + * add: Init PCkeckPar struct member + * + * Revision 1.29 1998/11/18 13:19:27 malthoff + * Disable packet arbiter timeouts on receive side. + * Use maximum timeout value for packet arbiter + * transmit timeouts. + * Add TestStopBit() function to handle stop RX/TX + * problem with active descriptor poll timers. + * Bug Fix: Descriptor Poll Timer not started, because + * GIPollTimerVal was initialized with 0. + * + * Revision 1.28 1998/11/13 14:24:26 malthoff + * Bug Fix: SkGeStopPort() may hang if a Packet Arbiter Timout + * is pending or occurs while waiting for TX_STOP and RX_STOP. + * The PA timeout is cleared now while waiting for TX- or RX_STOP. + * + * Revision 1.27 1998/11/02 11:04:36 malthoff + * fix the last fix + * + * Revision 1.26 1998/11/02 10:37:03 malthoff + * Fix: SkGePollTxD() enables always the synchronounous poll timer. + * + * Revision 1.25 1998/10/28 07:12:43 cgoos + * Fixed "LED_STOP" in SkGeLnkSyncCnt, "== SK_INIT_IO" in SkGeInit. + * Removed: Reset of RAM Interface in SkGeStopPort. + * + * Revision 1.24 1998/10/27 08:13:12 malthoff + * Remove temporary code. + * + * Revision 1.23 1998/10/26 07:45:03 malthoff + * Add Address Calculation Workaround: If the EPROM byte + * Id is 3, the address offset is 512 kB. + * Initialize default values for PLinkMode and PFlowCtrlMode. + * + * Revision 1.22 1998/10/22 09:46:47 gklug + * fix SysKonnectFileId typo + * + * Revision 1.21 1998/10/20 12:11:56 malthoff + * Don't dendy the Queue config if the size of the unused + * Rx qeueu is zero. + * + * Revision 1.20 1998/10/19 07:27:58 malthoff + * SkGeInitRamIface() is public to be called by diagnostics. + * + * Revision 1.19 1998/10/16 13:33:45 malthoff + * Fix: enabling descriptor polling is not allowed until + * the descriptor addresses are set. Descriptor polling + * must be handled by the driver. + * + * Revision 1.18 1998/10/16 10:58:27 malthoff + * Remove temp. code for Diag prototype. + * Remove lint warning for dummy reads. + * Call SkGeLoadLnkSyncCnt() during SkGeInitPort(). + * + * Revision 1.17 1998/10/14 09:16:06 malthoff + * Change parameter LimCount and programming of + * the limit counter in SkGeCfgSync(). + * + * Revision 1.16 1998/10/13 09:21:16 malthoff + * Don't set XM_RX_SELF_RX in RxCmd Reg, because it's + * like a Loopback Mode in half duplex. + * + * Revision 1.15 1998/10/09 06:47:40 malthoff + * SkGeInitMacArb(): set recovery counters init value + * to zero although this counters are not uesd. + * Bug fix in Rx Upper/Lower Pause Threshold calculation. + * Add XM_RX_SELF_RX to RxCmd. + * + * Revision 1.14 1998/10/06 15:15:53 malthoff + * Make sure no pending IRQ is cleared in SkGeLoadLnkSyncCnt(). + * + * Revision 1.13 1998/10/06 14:09:36 malthoff + * Add SkGeLoadLnkSyncCnt(). Modify + * the 'port stopped' condition according + * to the current problem report. + * + * Revision 1.12 1998/10/05 08:17:21 malthoff + * Add functions: SkGePollRxD(), SkGePollTxD(), + * DoCalcAddr(), SkGeCheckQSize(), + * DoInitRamQueue(), and SkGeCfgSync(). + * Add coding for SkGeInitMacArb(), SkGeInitPktArb(), + * SkGeInitMacFifo(), SkGeInitRamBufs(), + * SkGeInitRamIface(), and SkGeInitBmu(). + * + * Revision 1.11 1998/09/29 08:26:29 malthoff + * bug fix: SkGeInit0() 'i' should be increment. + * + * Revision 1.10 1998/09/28 13:19:01 malthoff + * Coding time: Save the done work. + * Modify SkGeLinkLED(), add SkGeXmitLED(), + * define SkGeCheckQSize(), SkGeInitMacArb(), + * SkGeInitPktArb(), SkGeInitMacFifo(), + * SkGeInitRamBufs(), SkGeInitRamIface(), + * and SkGeInitBmu(). Do coding for SkGeStopPort(), + * SkGeInit1(), SkGeInit2(), and SkGeInit3(). + * Do coding for SkGeDinit() and SkGeInitPort(). + * + * Revision 1.9 1998/09/16 14:29:05 malthoff + * Some minor changes. + * + * Revision 1.8 1998/09/11 05:29:14 gklug + * add: init state of a port + * + * Revision 1.7 1998/09/04 09:26:25 malthoff + * Short temporary modification. + * + * Revision 1.6 1998/09/04 08:27:59 malthoff + * Remark the do-while in StopPort() because it never ends + * without a GE adapter. + * + * Revision 1.5 1998/09/03 14:05:45 malthoff + * Change comment for SkGeInitPort(). Do not + * repair the queue sizes if invalid. + * + * Revision 1.4 1998/09/03 10:03:19 malthoff + * Implement the new interface according to the + * reviewed interface specification. + * + * Revision 1.3 1998/08/19 09:11:25 gklug + * fix: struct are removed from c-source (see CCC) + * + * Revision 1.2 1998/07/28 12:33:58 malthoff + * Add 'IoC' parameter in function declaration and SK IO macros. + * + * Revision 1.1 1998/07/23 09:48:57 malthoff + * Creation. First dummy 'C' file. + * SkGeInit(Level 0) is card_start for GE. + * SkGeDeInit() is card_stop for GE. + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + +/* global variables ***********************************************************/ + +/* local variables ************************************************************/ + +static const char SysKonnectFileId[] = + "@(#)$Id: skgeinit.c,v 1.85 2003/02/05 15:30:33 rschmidt Exp $ (C) SK "; + +struct s_QOffTab { + int RxQOff; /* Receive Queue Address Offset */ + int XsQOff; /* Sync Tx Queue Address Offset */ + int XaQOff; /* Async Tx Queue Address Offset */ +}; +static struct s_QOffTab QOffTab[] = { + {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2} +}; + + +/****************************************************************************** + * + * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring + * + * Description: + * Enable or disable the descriptor polling of the receive descriptor + * ring (RxD) for port 'Port'. + * The new configuration is *not* saved over any SkGeStopPort() and + * SkGeInitPort() calls. + * + * Returns: + * nothing + */ +void SkGePollRxD( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (PollRxD) ? + CSR_ENA_POL : CSR_DIS_POL); +} /* SkGePollRxD */ + + +/****************************************************************************** + * + * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings + * + * Description: + * Enable or disable the descriptor polling of the transmit descriptor + * ring(s) (TxD) for port 'Port'. + * The new configuration is *not* saved over any SkGeStopPort() and + * SkGeInitPort() calls. + * + * Returns: + * nothing + */ +void SkGePollTxD( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ +{ + SK_GEPORT *pPrt; + SK_U32 DWord; + + pPrt = &pAC->GIni.GP[Port]; + + DWord = (PollTxD) ? CSR_ENA_POL : CSR_DIS_POL; + + if (pPrt->PXSQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord); + } + + if (pPrt->PXAQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord); + } +} /* SkGePollTxD */ + + +/****************************************************************************** + * + * SkGeYellowLED() - Switch the yellow LED on or off. + * + * Description: + * Switch the yellow LED on or off. + * + * Note: + * This function may be called any time after SkGeInit(Level 1). + * + * Returns: + * nothing + */ +void SkGeYellowLED( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int State) /* yellow LED state, 0 = OFF, 0 != ON */ +{ + if (State == 0) { + /* Switch yellow LED OFF */ + SK_OUT8(IoC, B0_LED, LED_STAT_OFF); + } + else { + /* Switch yellow LED ON */ + SK_OUT8(IoC, B0_LED, LED_STAT_ON); + } +} /* SkGeYellowLED */ + + +/****************************************************************************** + * + * SkGeXmitLED() - Modify the Operational Mode of a transmission LED. + * + * Description: + * The Rx or Tx LED which is specified by 'Led' will be + * enabled, disabled or switched on in test mode. + * + * Note: + * 'Led' must contain the address offset of the LEDs INI register. + * + * Usage: + * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA); + * + * Returns: + * nothing + */ +void SkGeXmitLED( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Led, /* offset to the LED Init Value register */ +int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */ +{ + SK_U32 LedIni; + + switch (Mode) { + case SK_LED_ENA: + LedIni = SK_XMIT_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100; + SK_OUT32(IoC, Led + XMIT_LED_INI, LedIni); + SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START); + break; + case SK_LED_TST: + SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_ON); + SK_OUT32(IoC, Led + XMIT_LED_CNT, 100); + SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START); + break; + case SK_LED_DIS: + default: + /* + * Do NOT stop the LED Timer here. The LED might be + * in on state. But it needs to go off. + */ + SK_OUT32(IoC, Led + XMIT_LED_CNT, 0); + SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF); + break; + } + + /* + * 1000BT: The Transmit LED is driven by the PHY. + * But the default LED configuration is used for + * Level One and Broadcom PHYs. + * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.) + * (In this case it has to be added here. But we will see. XXX) + */ +} /* SkGeXmitLED */ + + +/****************************************************************************** + * + * DoCalcAddr() - Calculates the start and the end address of a queue. + * + * Description: + * This function calculates the start and the end address of a queue. + * Afterwards the 'StartVal' is incremented to the next start position. + * If the port is already initialized the calculated values + * will be checked against the configured values and an + * error will be returned, if they are not equal. + * If the port is not initialized the values will be written to + * *StartAdr and *EndAddr. + * + * Returns: + * 0: success + * 1: configuration error + */ +static int DoCalcAddr( +SK_AC *pAC, /* adapter context */ +SK_GEPORT *pPrt, /* port index */ +int QuSize, /* size of the queue to configure in kB */ +SK_U32 *StartVal, /* start value for address calculation */ +SK_U32 *QuStartAddr, /* start addr to calculate */ +SK_U32 *QuEndAddr) /* end address to calculate */ +{ + SK_U32 EndVal; + SK_U32 NextStart; + int Rtv; + + Rtv = 0; + if (QuSize == 0) { + EndVal = *StartVal; + NextStart = EndVal; + } + else { + EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1; + NextStart = EndVal + 1; + } + + if (pPrt->PState >= SK_PRT_INIT) { + if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) { + Rtv = 1; + } + } + else { + *QuStartAddr = *StartVal; + *QuEndAddr = EndVal; + } + + *StartVal = NextStart; + return(Rtv); +} /* DoCalcAddr */ + +/****************************************************************************** + * + * SkGeInitAssignRamToQueues() - allocate default queue sizes + * + * Description: + * This function assigns the memory to the different queues and ports. + * When DualNet is set to SK_TRUE all ports get the same amount of memory. + * Otherwise the first port gets most of the memory and all the + * other ports just the required minimum. + * This function can only be called when pAC->GIni.GIRamSize and + * pAC->GIni.GIMacsFound have been initialized, usually this happens + * at init level 1 + * + * Returns: + * 0 - ok + * 1 - invalid input values + * 2 - not enough memory + */ + +int SkGeInitAssignRamToQueues( +SK_AC *pAC, /* Adapter context */ +int ActivePort, /* Active Port in RLMT mode */ +SK_BOOL DualNet) /* adapter context */ +{ + int i; + int UsedKilobytes; /* memory already assigned */ + int ActivePortKilobytes; /* memory available for active port */ + SK_GEPORT *pGePort; + + UsedKilobytes = 0; + + if (ActivePort >= pAC->GIni.GIMacsFound) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n", + ActivePort)); + return(1); + } + if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) + + ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n", + pAC->GIni.GIRamSize)); + return(2); + } + + + if (DualNet) { + /* every port gets the same amount of memory */ + ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound; + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + pGePort = &pAC->GIni.GP[i]; + + /* take away the minimum memory for active queues */ + ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE); + + /* receive queue gets the minimum + 80% of the rest */ + pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB(( + ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100)) + + SK_MIN_RXQ_SIZE; + + ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE); + + /* synchronous transmit queue */ + pGePort->PXSQSize = 0; + + /* asynchronous transmit queue */ + pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes + + SK_MIN_TXQ_SIZE); + } + } + else { + /* Rlmt Mode or single link adapter */ + + /* Set standby queue size defaults for all standby ports */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + if (i != ActivePort) { + pGePort = &pAC->GIni.GP[i]; + + pGePort->PRxQSize = SK_MIN_RXQ_SIZE; + pGePort->PXAQSize = SK_MIN_TXQ_SIZE; + pGePort->PXSQSize = 0; + + /* Count used RAM */ + UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize; + } + } + /* what's left? */ + ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes; + + /* assign it to the active port */ + /* first take away the minimum memory */ + ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE); + pGePort = &pAC->GIni.GP[ActivePort]; + + /* receive queue get's the minimum + 80% of the rest */ + pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes * + (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE; + + ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE); + + /* synchronous transmit queue */ + pGePort->PXSQSize = 0; + + /* asynchronous transmit queue */ + pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) + + SK_MIN_TXQ_SIZE; + } +#ifdef VCPU + VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n", + pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize); +#endif /* VCPU */ + + return(0); +} /* SkGeInitAssignRamToQueues */ + +/****************************************************************************** + * + * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration + * + * Description: + * This function verifies the Queue Size Configuration specified + * in the variables PRxQSize, PXSQSize, and PXAQSize of all + * used ports. + * This requirements must be fullfilled to have a valid configuration: + * - The size of all queues must not exceed GIRamSize. + * - The queue sizes must be specified in units of 8 kB. + * - The size of Rx queues of available ports must not be + * smaller than 16 kB. + * - The size of at least one Tx queue (synch. or asynch.) + * of available ports must not be smaller than 16 kB + * when Jumbo Frames are used. + * - The RAM start and end addresses must not be changed + * for ports which are already initialized. + * Furthermore SkGeCheckQSize() defines the Start and End Addresses + * of all ports and stores them into the HWAC port structure. + * + * Returns: + * 0: Queue Size Configuration valid + * 1: Queue Size Configuration invalid + */ +static int SkGeCheckQSize( +SK_AC *pAC, /* adapter context */ +int Port) /* port index */ +{ + SK_GEPORT *pPrt; + int UsedMem; /* total memory used (max. found ports) */ + int i; + int Rtv; + int Rtv2; + SK_U32 StartAddr; + + UsedMem = 0; + Rtv = 0; + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + pPrt = &pAC->GIni.GP[i]; + + if ((pPrt->PRxQSize & QZ_UNITS) != 0 || + (pPrt->PXSQSize & QZ_UNITS) != 0 || + (pPrt->PXAQSize & QZ_UNITS) != 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); + return(1); + } + + if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG); + return(1); + } + + /* + * the size of at least one Tx queue (synch. or asynch.) has to be > 0. + * if Jumbo Frames are used, this size has to be >= 16 kB. + */ + if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) || + (pAC->GIni.GIPortUsage == SK_JUMBO_LINK && + ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) || + (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG); + return(1); + } + + UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize; + } + + if (UsedMem > pAC->GIni.GIRamSize) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); + return(1); + } + + /* Now start address calculation */ + StartAddr = pAC->GIni.GIRamOffs; + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + pPrt = &pAC->GIni.GP[i]; + + /* Calculate/Check values for the receive queue */ + Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr, + &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd); + Rtv |= Rtv2; + + /* Calculate/Check values for the synchronous Tx queue */ + Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr, + &pPrt->PXsQRamStart, &pPrt->PXsQRamEnd); + Rtv |= Rtv2; + + /* Calculate/Check values for the asynchronous Tx queue */ + Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr, + &pPrt->PXaQRamStart, &pPrt->PXaQRamEnd); + Rtv |= Rtv2; + + if (Rtv) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E013, SKERR_HWI_E013MSG); + return(1); + } + } + + return(0); +} /* SkGeCheckQSize */ + + +/****************************************************************************** + * + * SkGeInitMacArb() - Initialize the MAC Arbiter + * + * Description: + * This function initializes the MAC Arbiter. + * It must not be called if there is still an + * initialized or active port. + * + * Returns: + * nothing + */ +static void SkGeInitMacArb( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + /* release local reset */ + SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR); + + /* configure timeout values */ + SK_OUT8(IoC, B3_MA_TOINI_RX1, SK_MAC_TO_53); + SK_OUT8(IoC, B3_MA_TOINI_RX2, SK_MAC_TO_53); + SK_OUT8(IoC, B3_MA_TOINI_TX1, SK_MAC_TO_53); + SK_OUT8(IoC, B3_MA_TOINI_TX2, SK_MAC_TO_53); + + SK_OUT8(IoC, B3_MA_RCINI_RX1, 0); + SK_OUT8(IoC, B3_MA_RCINI_RX2, 0); + SK_OUT8(IoC, B3_MA_RCINI_TX1, 0); + SK_OUT8(IoC, B3_MA_RCINI_TX2, 0); + + /* recovery values are needed for XMAC II Rev. B2 only */ + /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */ + + /* + * There is no start or enable button to push, therefore + * the MAC arbiter is configured and enabled now. + */ +} /* SkGeInitMacArb */ + + +/****************************************************************************** + * + * SkGeInitPktArb() - Initialize the Packet Arbiter + * + * Description: + * This function initializes the Packet Arbiter. + * It must not be called if there is still an + * initialized or active port. + * + * Returns: + * nothing + */ +static void SkGeInitPktArb( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + /* release local reset */ + SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR); + + /* configure timeout values */ + SK_OUT16(IoC, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); + SK_OUT16(IoC, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); + SK_OUT16(IoC, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); + SK_OUT16(IoC, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); + + /* + * enable timeout timers if jumbo frames not used + * NOTE: the packet arbiter timeout interrupt is needed for + * half duplex hangup workaround + */ + if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) { + if (pAC->GIni.GIMacsFound == 1) { + SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1); + } + else { + SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1 | PA_ENA_TO_TX2); + } + } +} /* SkGeInitPktArb */ + + +/****************************************************************************** + * + * SkGeInitMacFifo() - Initialize the MAC FIFOs + * + * Description: + * Initialize all MAC FIFOs of the specified port + * + * Returns: + * nothing + */ +static void SkGeInitMacFifo( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 Word; +#ifdef VCPU + SK_U32 DWord; +#endif /* VCPU */ + /* + * For each FIFO: + * - release local reset + * - use default value for MAC FIFO size + * - setup defaults for the control register + * - enable the FIFO + */ + + Word = GMF_RX_CTRL_DEF; + + if (pAC->GIni.GIGenesis) { + /* Configure Rx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR); + SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF); + SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD); + + /* Configure Tx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR); + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); + SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD); + + /* Enable frame flushing if jumbo frames used */ + if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH); + } + } + else { + /* set Rx GMAC FIFO Flush Mask */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK); + + if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) { + + Word &= ~GMF_RX_F_FL_ON; + } + + /* Configure Rx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR); + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word); + + /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */ + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); + + /* Configure Tx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR); + SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF); + +#ifdef VCPU + SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord); + SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord); +#endif /* VCPU */ + + /* set Tx GMAC FIFO Almost Empty Threshold */ +/* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */ + } +} /* SkGeInitMacFifo */ + + +/****************************************************************************** + * + * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting + * + * Description: + * This function starts the Link Sync Counter of the specified + * port and enables the generation of an Link Sync IRQ. + * The Link Sync Counter may be used to detect an active link, + * if autonegotiation is not used. + * + * Note: + * o To ensure receiving the Link Sync Event the LinkSyncCounter + * should be initialized BEFORE clearing the XMAC's reset! + * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this + * function. + * + * Returns: + * nothing + */ +void SkGeLoadLnkSyncCnt( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U32 CntVal) /* Counter value */ +{ + SK_U32 OrgIMsk; + SK_U32 NewIMsk; + SK_U32 ISrc; + SK_BOOL IrqPend; + + /* stop counter */ + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP); + + /* + * ASIC problem: + * Each time starting the Link Sync Counter an IRQ is generated + * by the adapter. See problem report entry from 21.07.98 + * + * Workaround: Disable Link Sync IRQ and clear the unexpeced IRQ + * if no IRQ is already pending. + */ + IrqPend = SK_FALSE; + SK_IN32(IoC, B0_ISRC, &ISrc); + SK_IN32(IoC, B0_IMSK, &OrgIMsk); + if (Port == MAC_1) { + NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1; + if ((ISrc & IS_LNK_SYNC_M1) != 0) { + IrqPend = SK_TRUE; + } + } + else { + NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M2; + if ((ISrc & IS_LNK_SYNC_M2) != 0) { + IrqPend = SK_TRUE; + } + } + if (!IrqPend) { + SK_OUT32(IoC, B0_IMSK, NewIMsk); + } + + /* load counter */ + SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal); + + /* start counter */ + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START); + + if (!IrqPend) { + /* clear the unexpected IRQ, and restore the interrupt mask */ + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ); + SK_OUT32(IoC, B0_IMSK, OrgIMsk); + } +} /* SkGeLoadLnkSyncCnt*/ + + +/****************************************************************************** + * + * SkGeCfgSync() - Configure synchronous bandwidth for this port. + * + * Description: + * This function may be used to configure synchronous bandwidth + * to the specified port. This may be done any time after + * initializing the port. The configuration values are NOT saved + * in the HWAC port structure and will be overwritten any + * time when stopping and starting the port. + * Any values for the synchronous configuration will be ignored + * if the size of the synchronous queue is zero! + * + * The default configuration for the synchronous service is + * TXA_ENA_FSYNC. This means if the size of + * the synchronous queue is unequal zero but no specific + * synchronous bandwidth is configured, the synchronous queue + * will always have the 'unlimited' transmit priority! + * + * This mode will be restored if the synchronous bandwidth is + * deallocated ('IntTime' = 0 and 'LimCount' = 0). + * + * Returns: + * 0: success + * 1: parameter configuration error + * 2: try to configure quality of service although no + * synchronous queue is configured + */ +int SkGeCfgSync( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U32 IntTime, /* Interval Timer Value in units of 8ns */ +SK_U32 LimCount, /* Number of bytes to transfer during IntTime */ +int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */ +{ + int Rtv; + + Rtv = 0; + + /* check the parameters */ + if (LimCount > IntTime || + (LimCount == 0 && IntTime != 0) || + (LimCount != 0 && IntTime == 0)) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG); + return(1); + } + + if (pAC->GIni.GP[Port].PXSQSize == 0) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG); + return(2); + } + + /* calculate register values */ + IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100; + LimCount = LimCount / 8; + + if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG); + return(1); + } + + /* + * - Enable 'Force Sync' to ensure the synchronous queue + * has the priority while configuring the new values. + * - Also 'disable alloc' to ensure the settings complies + * to the SyncMode parameter. + * - Disable 'Rate Control' to configure the new values. + * - write IntTime and LimCount + * - start 'Rate Control' and disable 'Force Sync' + * if Interval Timer or Limit Counter not zero. + */ + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), + TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); + + SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime); + SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount); + + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), + (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC))); + + if (IntTime != 0 || LimCount != 0) { + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC); + } + + return(0); +} /* SkGeCfgSync */ + + +/****************************************************************************** + * + * DoInitRamQueue() - Initialize the RAM Buffer Address of a single Queue + * + * Desccription: + * If the queue is used, enable and initialize it. + * Make sure the queue is still reset, if it is not used. + * + * Returns: + * nothing + */ +static void DoInitRamQueue( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int QuIoOffs, /* Queue IO Address Offset */ +SK_U32 QuStartAddr, /* Queue Start Address */ +SK_U32 QuEndAddr, /* Queue End Address */ +int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */ +{ + SK_U32 RxUpThresVal; + SK_U32 RxLoThresVal; + + if (QuStartAddr != QuEndAddr) { + /* calculate thresholds, assume we have a big Rx queue */ + RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8; + RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8; + + /* build HW address format */ + QuStartAddr = QuStartAddr / 8; + QuEndAddr = QuEndAddr / 8; + + /* release local reset */ + SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_CLR); + + /* configure addresses */ + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_START), QuStartAddr); + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_END), QuEndAddr); + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_WP), QuStartAddr); + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RP), QuStartAddr); + + switch (QuType) { + case SK_RX_SRAM_Q: + /* configure threshold for small Rx Queue */ + RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8; + + /* continue with SK_RX_BRAM_Q */ + case SK_RX_BRAM_Q: + /* write threshold for Rx Queue */ + + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal); + SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal); + + /* the high priority threshold not used */ + break; + case SK_TX_RAM_Q: + /* + * Do NOT use Store & Forward under normal operation due to + * performance optimization (GENESIS only). + * But if Jumbo Frames are configured (XMAC Tx FIFO is only 4 kB) + * or YUKON is used ((GMAC Tx FIFO is only 1 kB) + * we NEED Store & Forward of the RAM buffer. + */ + if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK || + !pAC->GIni.GIGenesis) { + /* enable Store & Forward Mode for the Tx Side */ + SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD); + } + break; + } + + /* set queue operational */ + SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_OP_MD); + } + else { + /* ensure the queue is still disabled */ + SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_SET); + } +} /* DoInitRamQueue */ + + +/****************************************************************************** + * + * SkGeInitRamBufs() - Initialize the RAM Buffer Queues + * + * Description: + * Initialize all RAM Buffer Queues of the specified port + * + * Returns: + * nothing + */ +static void SkGeInitRamBufs( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + int RxQType; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) { + RxQType = SK_RX_SRAM_Q; /* small Rx Queue */ + } + else { + RxQType = SK_RX_BRAM_Q; /* big Rx Queue */ + } + + DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart, + pPrt->PRxQRamEnd, RxQType); + + DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart, + pPrt->PXsQRamEnd, SK_TX_RAM_Q); + + DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart, + pPrt->PXaQRamEnd, SK_TX_RAM_Q); + +} /* SkGeInitRamBufs */ + + +/****************************************************************************** + * + * SkGeInitRamIface() - Initialize the RAM Interface + * + * Description: + * This function initializes the Adapters RAM Interface. + * + * Note: + * This function is used in the diagnostics. + * + * Returns: + * nothing + */ +void SkGeInitRamIface( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + /* release local reset */ + SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR); + + /* configure timeout values */ + SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53); + SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53); + +} /* SkGeInitRamIface */ + + +/****************************************************************************** + * + * SkGeInitBmu() - Initialize the BMU state machines + * + * Description: + * Initialize all BMU state machines of the specified port + * + * Returns: + * nothing + */ +static void SkGeInitBmu( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U32 RxWm; + SK_U32 TxWm; + + pPrt = &pAC->GIni.GP[Port]; + + RxWm = SK_BMU_RX_WM; + TxWm = SK_BMU_TX_WM; + + if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) { + /* for better performance */ + RxWm /= 2; + TxWm /= 2; + } + + /* Rx Queue: Release all local resets and set the watermark */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm); + + /* + * Tx Queue: Release all local resets if the queue is used ! + * set watermark + */ + if (pPrt->PXSQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm); + } + + if (pPrt->PXAQSize != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm); + } + /* + * Do NOT enable the descriptor poll timers here, because + * the descriptor addresses are not specified yet. + */ +} /* SkGeInitBmu */ + + +/****************************************************************************** + * + * TestStopBit() - Test the stop bit of the queue + * + * Description: + * Stopping a queue is not as simple as it seems to be. + * If descriptor polling is enabled, it may happen + * that RX/TX stop is done and SV idle is NOT set. + * In this case we have to issue another stop command. + * + * Returns: + * The queues control status register + */ +static SK_U32 TestStopBit( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int QuIoOffs) /* Queue IO Address Offset */ +{ + SK_U32 QuCsr; /* CSR contents */ + + SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); + + if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) { + /* Stop Descriptor overridden by start command */ + SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP); + + SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); + } + + return(QuCsr); +} /* TestStopBit */ + + +/****************************************************************************** + * + * SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'. + * + * Description: + * After calling this function the descriptor rings and Rx and Tx + * queues of this port may be reconfigured. + * + * It is possible to stop the receive and transmit path separate or + * both together. + * + * Dir = SK_STOP_TX Stops the transmit path only and resets the MAC. + * The receive queue is still active and + * the pending Rx frames may be still transferred + * into the RxD. + * SK_STOP_RX Stop the receive path. The tansmit path + * has to be stopped once before. + * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX + * + * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive. + * SK_HARD_RST Resets the MAC and the PHY. + * + * Example: + * 1) A Link Down event was signaled for a port. Therefore the activity + * of this port should be stopped and a hardware reset should be issued + * to enable the workaround of XMAC errata #2. But the received frames + * should not be discarded. + * ... + * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST); + * (transfer all pending Rx frames) + * SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST); + * ... + * + * 2) An event was issued which request the driver to switch + * the 'virtual active' link to an other already active port + * as soon as possible. The frames in the receive queue of this + * port may be lost. But the PHY must not be reset during this + * event. + * ... + * SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST); + * ... + * + * Extended Description: + * If SK_STOP_TX is set, + * o disable the MAC's receive and transmitter to prevent + * from sending incomplete frames + * o stop the port's transmit queues before terminating the + * BMUs to prevent from performing incomplete PCI cycles + * on the PCI bus + * - The network Rx and Tx activity and PCI Tx transfer is + * disabled now. + * o reset the MAC depending on the RstMode + * o Stop Interval Timer and Limit Counter of Tx Arbiter, + * also disable Force Sync bit and Enable Alloc bit. + * o perform a local reset of the port's Tx path + * - reset the PCI FIFO of the async Tx queue + * - reset the PCI FIFO of the sync Tx queue + * - reset the RAM Buffer async Tx queue + * - reset the RAM Buffer sync Tx queue + * - reset the MAC Tx FIFO + * o switch Link and Tx LED off, stop the LED counters + * + * If SK_STOP_RX is set, + * o stop the port's receive queue + * - The path data transfer activity is fully stopped now. + * o perform a local reset of the port's Rx path + * - reset the PCI FIFO of the Rx queue + * - reset the RAM Buffer receive queue + * - reset the MAC Rx FIFO + * o switch Rx LED off, stop the LED counter + * + * If all ports are stopped, + * o reset the RAM Interface. + * + * Notes: + * o This function may be called during the driver states RESET_PORT and + * SWITCH_PORT. + */ +void SkGeStopPort( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* I/O context */ +int Port, /* port to stop (MAC_1 + n) */ +int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */ +int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ +{ +#ifndef SK_DIAG + SK_EVPARA Para; +#endif /* !SK_DIAG */ + SK_GEPORT *pPrt; + SK_U32 DWord; + SK_U32 XsCsr; + SK_U32 XaCsr; + SK_U64 ToutStart; + int i; + int ToutCnt; + + pPrt = &pAC->GIni.GP[Port]; + + if ((Dir & SK_STOP_TX) != 0) { + /* disable receiver and transmitter */ + SkMacRxTxDisable(pAC, IoC, Port); + + /* stop both transmit queues */ + /* + * If the BMU is in the reset state CSR_STOP will terminate + * immediately. + */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP); + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP); + + ToutStart = SkOsGetTime(pAC); + ToutCnt = 0; + do { + /* + * Clear packet arbiter timeout to make sure + * this loop will terminate. + */ + SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_TX1 : + PA_CLR_TO_TX2); + + /* + * If the transfer stucks at the MAC the STOP command will not + * terminate if we don't flush the XMAC's transmit FIFO ! + */ + SkMacFlushTxFifo(pAC, IoC, Port); + + XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff); + XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff); + + if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) { + /* + * Timeout of 1/18 second reached. + * This needs to be checked at 1/18 sec only. + */ + ToutCnt++; + if (ToutCnt > 1) { + /* Might be a problem when the driver event handler + * calls StopPort again. XXX. + */ + + /* Fatal Error, Loop aborted */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018, + SKERR_HWI_E018MSG); +#ifndef SK_DIAG + Para.Para64 = Port; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); +#endif /* !SK_DIAG */ + return; + } + /* + * Cache incoherency workaround: Assume a start command + * has been lost while sending the frame. + */ + ToutStart = SkOsGetTime(pAC); + + if ((XsCsr & CSR_STOP) != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START); + } + if ((XaCsr & CSR_STOP) != 0) { + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START); + } + } + + /* + * Because of the ASIC problem report entry from 21.08.1998 it is + * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set. + */ + } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE || + (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE); + + /* Reset the MAC depending on the RstMode */ + if (RstMode == SK_SOFT_RST) { + SkMacSoftRst(pAC, IoC, Port); + } + else { + SkMacHardRst(pAC, IoC, Port); + } + + /* Disable Force Sync bit and Enable Alloc bit */ + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), + TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); + + /* Stop Interval Timer and Limit Counter of Tx Arbiter */ + SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L); + SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L); + + /* Perform a local reset of the port's Tx path */ + + /* Reset the PCI FIFO of the async Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET); + /* Reset the PCI FIFO of the sync Tx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET); + /* Reset the RAM Buffer async Tx queue */ + SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET); + /* Reset the RAM Buffer sync Tx queue */ + SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET); + + /* Reset Tx MAC FIFO */ + if (pAC->GIni.GIGenesis) { + /* Note: MFF_RST_SET does NOT reset the XMAC ! */ + SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET); + + /* switch Link and Tx LED off, stop the LED counters */ + /* Link LED is switched off by the RLMT and the Diag itself */ + SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS); + } + else { + /* Reset TX MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET); + } + } + + if ((Dir & SK_STOP_RX) != 0) { + /* + * The RX Stop Command will not terminate if no buffers + * are queued in the RxD ring. But it will always reach + * the Idle state. Therefore we can use this feature to + * stop the transfer of received packets. + */ + /* stop the port's receive queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP); + + i = 100; + do { + /* + * Clear packet arbiter timeout to make sure + * this loop will terminate + */ + SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_RX1 : + PA_CLR_TO_RX2); + + DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff); + + /* timeout if i==0 (bug fix for #10748) */ + if (--i == 0) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024, + SKERR_HWI_E024MSG); + break; + } + /* + * because of the ASIC problem report entry from 21.08.98 + * it is required to wait until CSR_STOP is reset and + * CSR_SV_IDLE is set. + */ + } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE); + + /* The path data transfer activity is fully stopped now */ + + /* Perform a local reset of the port's Rx path */ + + /* Reset the PCI FIFO of the Rx queue */ + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET); + /* Reset the RAM Buffer receive queue */ + SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET); + + /* Reset Rx MAC FIFO */ + if (pAC->GIni.GIGenesis) { + + SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET); + + /* switch Rx LED off, stop the LED counter */ + SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS); + } + else { + /* Reset Rx MAC FIFO */ + SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET); + } + } +} /* SkGeStopPort */ + + +/****************************************************************************** + * + * SkGeInit0() - Level 0 Initialization + * + * Description: + * - Initialize the BMU address offsets + * + * Returns: + * nothing + */ +static void SkGeInit0( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + int i; + SK_GEPORT *pPrt; + + for (i = 0; i < SK_MAX_MACS; i++) { + pPrt = &pAC->GIni.GP[i]; + + pPrt->PState = SK_PRT_RESET; + pPrt->PRxQOff = QOffTab[i].RxQOff; + pPrt->PXsQOff = QOffTab[i].XsQOff; + pPrt->PXaQOff = QOffTab[i].XaQOff; + pPrt->PCheckPar = SK_FALSE; + pPrt->PIsave = 0; + pPrt->PPrevShorts = 0; + pPrt->PLinkResCt = 0; + pPrt->PAutoNegTOCt = 0; + pPrt->PPrevRx = 0; + pPrt->PPrevFcs = 0; + pPrt->PRxLim = SK_DEF_RX_WA_LIM; + pPrt->PLinkMode = SK_LMODE_AUTOFULL; + pPrt->PLinkSpeedCap = SK_LSPEED_CAP_1000MBPS; + pPrt->PLinkSpeed = SK_LSPEED_1000MBPS; + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_UNKNOWN; + pPrt->PLinkModeConf = SK_LMODE_AUTOSENSE; + pPrt->PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; + pPrt->PLinkBroken = SK_TRUE; /* See WA code */ + pPrt->PLinkCap = (SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL | + SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL); + pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; + pPrt->PFlowCtrlCap = SK_FLOW_MODE_SYM_OR_REM; + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + pPrt->PMSCap = 0; + pPrt->PMSMode = SK_MS_MODE_AUTO; + pPrt->PMSStatus = SK_MS_STAT_UNSET; + pPrt->PAutoNegFail = SK_FALSE; + pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN; + pPrt->PHWLinkUp = SK_FALSE; + } + + pAC->GIni.GIPortUsage = SK_RED_LINK; + +} /* SkGeInit0*/ + +#ifdef SK_PCI_RESET + +/****************************************************************************** + * + * SkGePciReset() - Reset PCI interface + * + * Description: + * o Read PCI configuration. + * o Change power state to 3. + * o Change power state to 0. + * o Restore PCI configuration. + * + * Returns: + * 0: Success. + * 1: Power state could not be changed to 3. + */ +static int SkGePciReset( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + int i; + SK_U16 PmCtlSts; + SK_U32 Bp1; + SK_U32 Bp2; + SK_U16 PciCmd; + SK_U8 Cls; + SK_U8 Lat; + SK_U8 ConfigSpace[PCI_CFG_SIZE]; + + /* + * Note: Switching to D3 state is like a software reset. + * Switching from D3 to D0 is a hardware reset. + * We have to save and restore the configuration space. + */ + for (i = 0; i < PCI_CFG_SIZE; i++) { + SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]); + } + + /* We know the RAM Interface Arbiter is enabled. */ + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3); + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts); + + if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) { + return(1); + } + + /* Return to D0 state. */ + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0); + + /* Check for D0 state. */ + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts); + + if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) { + return(1); + } + + /* Check PCI Config Registers. */ + SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd); + SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls); + SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1); + SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2); + SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat); + + if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 || + Lat != 0) { + return(1); + } + + /* Restore PCI Config Space. */ + for (i = 0; i < PCI_CFG_SIZE; i++) { + SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]); + } + + return(0); +} /* SkGePciReset */ + +#endif /* SK_PCI_RESET */ + +/****************************************************************************** + * + * SkGeInit1() - Level 1 Initialization + * + * Description: + * o Do a software reset. + * o Clear all reset bits. + * o Verify that the detected hardware is present. + * Return an error if not. + * o Get the hardware configuration + * + Read the number of MACs/Ports. + * + Read the RAM size. + * + Read the PCI Revision Id. + * + Find out the adapters host clock speed + * + Read and check the PHY type + * + * Returns: + * 0: success + * 5: Unexpected PHY type detected + * 6: HW self test failed + */ +static int SkGeInit1( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + SK_U8 Byte; + SK_U16 Word; + SK_U16 CtrlStat; + SK_U32 FlashAddr; + int RetVal; + int i; + + RetVal = 0; + + /* save CLK_RUN bits (YUKON-Lite) */ + SK_IN16(IoC, B0_CTST, &CtrlStat); + +#ifdef SK_PCI_RESET + (void)SkGePciReset(pAC, IoC); +#endif /* SK_PCI_RESET */ + + /* do the SW-reset */ + SK_OUT8(IoC, B0_CTST, CS_RST_SET); + + /* release the SW-reset */ + SK_OUT8(IoC, B0_CTST, CS_RST_CLR); + + /* reset all error bits in the PCI STATUS register */ + /* + * Note: PCI Cfg cycles cannot be used, because they are not + * available on some platforms after 'boot time'. + */ + SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + + /* release Master Reset */ + SK_OUT8(IoC, B0_CTST, CS_MRST_CLR); + +#ifdef CLK_RUN + CtrlStat |= CS_CLK_RUN_ENA; +#endif /* CLK_RUN */ + + /* restore CLK_RUN bits */ + SK_OUT16(IoC, B0_CTST, CtrlStat & + (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)); + + /* read Chip Identification Number */ + SK_IN8(IoC, B2_CHIP_ID, &Byte); + pAC->GIni.GIChipId = Byte; + + /* read number of MACs */ + SK_IN8(IoC, B2_MAC_CFG, &Byte); + pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2; + + /* get Chip Revision Number */ + pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4); + + /* get diff. PCI parameters */ + SK_IN16(IoC, B0_CTST, &CtrlStat); + + /* read the adapters RAM size */ + SK_IN8(IoC, B2_E_0, &Byte); + + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { + + pAC->GIni.GIGenesis = SK_TRUE; + + if (Byte == 3) { + /* special case: 4 x 64k x 36, offset = 0x80000 */ + pAC->GIni.GIRamSize = 1024; + pAC->GIni.GIRamOffs = (SK_U32)512 * 1024; + } + else { + pAC->GIni.GIRamSize = (int)Byte * 512; + pAC->GIni.GIRamOffs = 0; + } + /* all GE adapters work with 53.125 MHz host clock */ + pAC->GIni.GIHstClkFact = SK_FACT_53; + + /* set Descr. Poll Timer Init Value to 250 ms */ + pAC->GIni.GIPollTimerVal = + SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100; + } + else { + pAC->GIni.GIGenesis = SK_FALSE; + +#ifndef VCPU + pAC->GIni.GIRamSize = (Byte == 0) ? 128 : (int)Byte * 4; +#else + pAC->GIni.GIRamSize = 128; +#endif + pAC->GIni.GIRamOffs = 0; + + /* WA for chip Rev. A */ + pAC->GIni.GIWolOffs = (pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0; + + /* get PM Capabilities of PCI config space */ + SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word); + + /* check if VAUX is available */ + if (((CtrlStat & CS_VAUX_AVAIL) != 0) && + /* check also if PME from D3cold is set */ + ((Word & PCI_PME_D3C_SUP) != 0)) { + /* set entry in GE init struct */ + pAC->GIni.GIVauxAvail = SK_TRUE; + } + + /* save Flash-Address Register */ + SK_IN32(IoC, B2_FAR, &FlashAddr); + + /* test Flash-Address Register */ + SK_OUT8(IoC, B2_FAR + 3, 0xff); + SK_IN8(IoC, B2_FAR + 3, &Byte); + + pAC->GIni.GIYukonLite = (SK_BOOL)(Byte != 0); + + /* restore Flash-Address Register */ + SK_OUT32(IoC, B2_FAR, FlashAddr); + + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + /* set GMAC Link Control reset */ + SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET); + + /* clear GMAC Link Control reset */ + SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR); + } + /* all YU chips work with 78.125 MHz host clock */ + pAC->GIni.GIHstClkFact = SK_FACT_78; + + pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */ + } + + /* check if 64-bit PCI Slot is present */ + pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0); + + /* check if 66 MHz PCI Clock is active */ + pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0); + + /* read PCI HW Revision Id. */ + SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte); + pAC->GIni.GIPciHwRev = Byte; + + /* read the PMD type */ + SK_IN8(IoC, B2_PMD_TYP, &Byte); + pAC->GIni.GICopperType = (SK_U8)(Byte == 'T'); + + /* read the PHY type */ + SK_IN8(IoC, B2_E_1, &Byte); + + Byte &= 0x0f; /* the PHY type is stored in the lower nibble */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + if (pAC->GIni.GIGenesis) { + switch (Byte) { + case SK_PHY_XMAC: + pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC; + break; + case SK_PHY_BCOM: + pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM; + pAC->GIni.GP[i].PMSCap = + SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE; + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE; + break; + case SK_PHY_NAT: + pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT; + break; +#endif /* OTHER_PHY */ + default: + /* ERROR: unexpected PHY type detected */ + RetVal = 5; + break; + } + } + else { + if (Byte == 0) { + /* if this field is not initialized */ + Byte = SK_PHY_MARV_COPPER; + pAC->GIni.GICopperType = SK_TRUE; + } + pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV; + + if (pAC->GIni.GICopperType) { + pAC->GIni.GP[i].PLinkSpeedCap = SK_LSPEED_CAP_AUTO | + SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS | + SK_LSPEED_CAP_1000MBPS; + pAC->GIni.GP[i].PLinkSpeed = SK_LSPEED_AUTO; + pAC->GIni.GP[i].PMSCap = + SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE; + } + else { + Byte = SK_PHY_MARV_FIBER; + } + } + + pAC->GIni.GP[i].PhyType = Byte; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("PHY type: %d PHY addr: %04x\n", Byte, + pAC->GIni.GP[i].PhyAddr)); + } + + /* get Mac Type & set function pointers dependent on */ + if (pAC->GIni.GIGenesis) { + pAC->GIni.GIMacType = SK_MAC_XMAC; + + pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats; + pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic; + pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter; + pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus; + } + else { + pAC->GIni.GIMacType = SK_MAC_GMAC; + + pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats; + pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic; + pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter; + pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus; + +#ifdef SPECIAL_HANDLING + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { + /* check HW self test result */ + SK_IN8(IoC, B2_E_3, &Byte); + if ((Byte & B2_E3_RES_MASK) != 0) { + RetVal = 6; + } + } +#endif + } + return(RetVal); +} /* SkGeInit1 */ + + +/****************************************************************************** + * + * SkGeInit2() - Level 2 Initialization + * + * Description: + * - start the Blink Source Counter + * - start the Descriptor Poll Timer + * - configure the MAC-Arbiter + * - configure the Packet-Arbiter + * - enable the Tx Arbiters + * - enable the RAM Interface Arbiter + * + * Returns: + * nothing + */ +static void SkGeInit2( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + SK_U32 DWord; + int i; + + /* start the Descriptor Poll Timer */ + if (pAC->GIni.GIPollTimerVal != 0) { + if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) { + pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG); + } + SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal); + SK_OUT8(IoC, B28_DPT_CTRL, DPT_START); + } + + if (pAC->GIni.GIGenesis) { + /* start the Blink Source Counter */ + DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100; + + SK_OUT32(IoC, B2_BSC_INI, DWord); + SK_OUT8(IoC, B2_BSC_CTRL, BSC_START); + + /* + * Configure the MAC Arbiter and the Packet Arbiter. + * They will be started once and never be stopped. + */ + SkGeInitMacArb(pAC, IoC); + + SkGeInitPktArb(pAC, IoC); + } + else { + /* start Time Stamp Timer */ + SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START); + } + + /* enable the Tx Arbiters */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + SK_OUT8(IoC, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB); + } + + /* enable the RAM Interface Arbiter */ + SkGeInitRamIface(pAC, IoC); + +} /* SkGeInit2 */ + +/****************************************************************************** + * + * SkGeInit() - Initialize the GE Adapter with the specified level. + * + * Description: + * Level 0: Initialize the Module structures. + * Level 1: Generic Hardware Initialization. The IOP/MemBase pointer has + * to be set before calling this level. + * + * o Do a software reset. + * o Clear all reset bits. + * o Verify that the detected hardware is present. + * Return an error if not. + * o Get the hardware configuration + * + Set GIMacsFound with the number of MACs. + * + Store the RAM size in GIRamSize. + * + Save the PCI Revision ID in GIPciHwRev. + * o return an error + * if Number of MACs > SK_MAX_MACS + * + * After returning from Level 0 the adapter + * may be accessed with IO operations. + * + * Level 2: start the Blink Source Counter + * + * Returns: + * 0: success + * 1: Number of MACs exceeds SK_MAX_MACS (after level 1) + * 2: Adapter not present or not accessible + * 3: Illegal initialization level + * 4: Initialization Level 1 Call missing + * 5: Unexpected PHY type detected + * 6: HW self test failed + */ +int SkGeInit( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Level) /* initialization level */ +{ + int RetVal; /* return value */ + SK_U32 DWord; + + RetVal = 0; + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, + ("SkGeInit(Level %d)\n", Level)); + + switch (Level) { + case SK_INIT_DATA: + /* Initialization Level 0 */ + SkGeInit0(pAC, IoC); + pAC->GIni.GILevel = SK_INIT_DATA; + break; + + case SK_INIT_IO: + /* Initialization Level 1 */ + RetVal = SkGeInit1(pAC, IoC); + if (RetVal != 0) { + break; + } + + /* check if the adapter seems to be accessible */ + SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L); + SK_IN32(IoC, B2_IRQM_INI, &DWord); + SK_OUT32(IoC, B2_IRQM_INI, 0L); + + if (DWord != 0x11335577L) { + RetVal = 2; + break; + } + + /* check if the number of GIMacsFound matches SK_MAX_MACS */ + if (pAC->GIni.GIMacsFound > SK_MAX_MACS) { + RetVal = 1; + break; + } + + /* Level 1 successfully passed */ + pAC->GIni.GILevel = SK_INIT_IO; + break; + + case SK_INIT_RUN: + /* Initialization Level 2 */ + if (pAC->GIni.GILevel != SK_INIT_IO) { +#ifndef SK_DIAG + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG); +#endif /* !SK_DIAG */ + RetVal = 4; + break; + } + SkGeInit2(pAC, IoC); + + /* Level 2 successfully passed */ + pAC->GIni.GILevel = SK_INIT_RUN; + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG); + RetVal = 3; + break; + } + + return(RetVal); +} /* SkGeInit */ + + +/****************************************************************************** + * + * SkGeDeInit() - Deinitialize the adapter + * + * Description: + * All ports of the adapter will be stopped if not already done. + * Do a software reset and switch off all LEDs. + * + * Returns: + * nothing + */ +void SkGeDeInit( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC) /* IO context */ +{ + int i; + SK_U16 Word; + +#ifndef VCPU + /* ensure I2C is ready */ + SkI2cWaitIrq(pAC, IoC); +#endif + + /* stop all current transfer activity */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + if (pAC->GIni.GP[i].PState != SK_PRT_STOP && + pAC->GIni.GP[i].PState != SK_PRT_RESET) { + + SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST); + } + } + + /* Reset all bits in the PCI STATUS register */ + /* + * Note: PCI Cfg cycles cannot be used, because they are not + * available on some platforms after 'boot time'. + */ + SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + + /* do the reset, all LEDs are switched off now */ + SK_OUT8(IoC, B0_CTST, CS_RST_SET); +} /* SkGeDeInit */ + + +/****************************************************************************** + * + * SkGeInitPort() Initialize the specified port. + * + * Description: + * PRxQSize, PXSQSize, and PXAQSize has to be + * configured for the specified port before calling this function. + * The descriptor rings has to be initialized too. + * + * o (Re)configure queues of the specified port. + * o configure the MAC of the specified port. + * o put ASIC and MAC(s) in operational mode. + * o initialize Rx/Tx and Sync LED + * o initialize RAM Buffers and MAC FIFOs + * + * The port is ready to connect when returning. + * + * Note: + * The MAC's Rx and Tx state machine is still disabled when returning. + * + * Returns: + * 0: success + * 1: Queue size initialization error. The configured values + * for PRxQSize, PXSQSize, or PXAQSize are invalid for one + * or more queues. The specified port was NOT initialized. + * An error log entry was generated. + * 2: The port has to be stopped before it can be initialized again. + */ +int SkGeInitPort( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port to configure */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (SkGeCheckQSize(pAC, Port) != 0) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG); + return(1); + } + + if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG); + return(2); + } + + /* configuration ok, initialize the Port now */ + + if (pAC->GIni.GIGenesis) { + /* initialize Rx, Tx and Link LED */ + /* + * If 1000BT Phy needs LED initialization than swap + * LED and XMAC initialization order + */ + SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA); + SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA); + /* The Link LED is initialized by RLMT or Diagnostics itself */ + + SkXmInitMac(pAC, IoC, Port); + } + else { + + SkGmInitMac(pAC, IoC, Port); + } + + /* do NOT initialize the Link Sync Counter */ + + SkGeInitMacFifo(pAC, IoC, Port); + + SkGeInitRamBufs(pAC, IoC, Port); + + if (pPrt->PXSQSize != 0) { + /* enable Force Sync bit if synchronous queue available */ + SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC); + } + + SkGeInitBmu(pAC, IoC, Port); + + /* mark port as initialized */ + pPrt->PState = SK_PRT_INIT; + + return(0); +} /* SkGeInitPort */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skgemib.c b/drivers/sk98lin/skgemib.c new file mode 100644 index 000000000..4a9e9e6af --- /dev/null +++ b/drivers/sk98lin/skgemib.c @@ -0,0 +1,1060 @@ +/***************************************************************************** + * + * Name: skgemib.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.7 $ + * Date: $Date: 2002/12/16 09:04:34 $ + * Purpose: Private Network Management Interface Management Database + * + ****************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/***************************************************************************** + * + * History: + * + * $Log: skgemib.c,v $ + * Revision 1.7 2002/12/16 09:04:34 tschilli + * Code for VCT handling added. + * + * Revision 1.6 2002/08/09 15:40:21 rwahl + * Editorial change (renamed ConfSpeedCap). + * + * Revision 1.5 2002/08/09 11:05:34 rwahl + * Added oid handling for link speed cap. + * + * Revision 1.4 2002/08/09 09:40:27 rwahl + * Added support for NDIS OID_PNP_xxx. + * + * Revision 1.3 2002/07/17 19:39:54 rwahl + * Added handler for OID_SKGE_SPEED_MODE & OID_SKGE_SPEED_STATUS. + * + * Revision 1.2 2002/05/22 08:59:00 rwahl + * - static functions only for release build. + * - Source file must be included. + * + * Revision 1.1 2002/05/22 08:12:42 rwahl + * Initial version. + * + ****************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +/* + * PRIVATE OID handler function prototypes + */ +PNMI_STATIC int Addr(SK_AC *pAC, SK_IOC IoC, int action, + SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int CsumStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int General(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Mac8023Stat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int MacPrivateConf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int MacPrivateStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Monitor(SK_AC *pAC, SK_IOC IoC, int action, + SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int OidStruct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Perform(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int* pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Rlmt(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int RlmtStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int SensorStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Vpd(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); + +#ifdef SK_POWER_MGMT +PNMI_STATIC int PowerManagement(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, + unsigned int TableIndex, SK_U32 NetIndex); +#endif + + +/* defines *******************************************************************/ +#define ID_TABLE_SIZE (sizeof(IdTable)/sizeof(IdTable[0])) + + +/* global variables **********************************************************/ + +/* + * Table to correlate OID with handler function and index to + * hardware register stored in StatAddress if applicable. + */ +PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = { + {OID_GEN_XMIT_OK, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX}, + {OID_GEN_RCV_OK, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX}, + {OID_GEN_XMIT_ERROR, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, + {OID_GEN_RCV_ERROR, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, + {OID_GEN_RCV_NO_BUFFER, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, + {OID_GEN_DIRECTED_FRAMES_XMIT, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNICAST}, + {OID_GEN_MULTICAST_FRAMES_XMIT, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTICAST}, + {OID_GEN_BROADCAST_FRAMES_XMIT, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_BROADCAST}, + {OID_GEN_DIRECTED_FRAMES_RCV, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_UNICAST}, + {OID_GEN_MULTICAST_FRAMES_RCV, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_MULTICAST}, + {OID_GEN_BROADCAST_FRAMES_RCV, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_BROADCAST}, + {OID_GEN_RCV_CRC_ERROR, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FCS}, + {OID_GEN_TRANSMIT_QUEUE_LENGTH, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, + {OID_802_3_PERMANENT_ADDRESS, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, 0}, + {OID_802_3_CURRENT_ADDRESS, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, 0}, + {OID_802_3_RCV_ERROR_ALIGNMENT, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FRAMING}, + {OID_802_3_XMIT_ONE_COLLISION, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_SINGLE_COL}, + {OID_802_3_XMIT_MORE_COLLISIONS, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTI_COL}, + {OID_802_3_XMIT_DEFERRED, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_DEFFERAL}, + {OID_802_3_XMIT_MAX_COLLISIONS, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_EXCESS_COL}, + {OID_802_3_RCV_OVERRUN, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_OVERFLOW}, + {OID_802_3_XMIT_UNDERRUN, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNDERRUN}, + {OID_802_3_XMIT_TIMES_CRS_LOST, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_CARRIER}, + {OID_802_3_XMIT_LATE_COLLISIONS, + 0, + 0, + 0, + SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_LATE_COL}, +#ifdef SK_POWER_MGMT + {OID_PNP_CAPABILITIES, + 0, + 0, + 0, + SK_PNMI_RO, PowerManagement, 0}, + {OID_PNP_SET_POWER, + 0, + 0, + 0, + SK_PNMI_WO, PowerManagement, 0}, + {OID_PNP_QUERY_POWER, + 0, + 0, + 0, + SK_PNMI_RO, PowerManagement, 0}, + {OID_PNP_ADD_WAKE_UP_PATTERN, + 0, + 0, + 0, + SK_PNMI_WO, PowerManagement, 0}, + {OID_PNP_REMOVE_WAKE_UP_PATTERN, + 0, + 0, + 0, + SK_PNMI_WO, PowerManagement, 0}, + {OID_PNP_ENABLE_WAKE_UP, + 0, + 0, + 0, + SK_PNMI_RW, PowerManagement, 0}, +#endif /* SK_POWER_MGMT */ + {OID_SKGE_MDB_VERSION, + 1, + 0, + SK_PNMI_MAI_OFF(MgmtDBVersion), + SK_PNMI_RO, General, 0}, + {OID_SKGE_SUPPORTED_LIST, + 0, + 0, + 0, + SK_PNMI_RO, General, 0}, + {OID_SKGE_ALL_DATA, + 0, + 0, + 0, + SK_PNMI_RW, OidStruct, 0}, + {OID_SKGE_VPD_FREE_BYTES, + 1, + 0, + SK_PNMI_MAI_OFF(VpdFreeBytes), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_ENTRIES_LIST, + 1, + 0, + SK_PNMI_MAI_OFF(VpdEntriesList), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_ENTRIES_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(VpdEntriesNumber), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_KEY, + SK_PNMI_VPD_ENTRIES, + sizeof(SK_PNMI_VPD), + SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdKey), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_VALUE, + SK_PNMI_VPD_ENTRIES, + sizeof(SK_PNMI_VPD), + SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdValue), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_ACCESS, + SK_PNMI_VPD_ENTRIES, + sizeof(SK_PNMI_VPD), + SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAccess), + SK_PNMI_RO, Vpd, 0}, + {OID_SKGE_VPD_ACTION, + SK_PNMI_VPD_ENTRIES, + sizeof(SK_PNMI_VPD), + SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAction), + SK_PNMI_RW, Vpd, 0}, + {OID_SKGE_PORT_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(PortNumber), + SK_PNMI_RO, General, 0}, + {OID_SKGE_DEVICE_TYPE, + 1, + 0, + SK_PNMI_MAI_OFF(DeviceType), + SK_PNMI_RO, General, 0}, + {OID_SKGE_DRIVER_DESCR, + 1, + 0, + SK_PNMI_MAI_OFF(DriverDescr), + SK_PNMI_RO, General, 0}, + {OID_SKGE_DRIVER_VERSION, + 1, + 0, + SK_PNMI_MAI_OFF(DriverVersion), + SK_PNMI_RO, General, 0}, + {OID_SKGE_HW_DESCR, + 1, + 0, + SK_PNMI_MAI_OFF(HwDescr), + SK_PNMI_RO, General, 0}, + {OID_SKGE_HW_VERSION, + 1, + 0, + SK_PNMI_MAI_OFF(HwVersion), + SK_PNMI_RO, General, 0}, + {OID_SKGE_CHIPSET, + 1, + 0, + SK_PNMI_MAI_OFF(Chipset), + SK_PNMI_RO, General, 0}, + {OID_SKGE_ACTION, + 1, + 0, + SK_PNMI_MAI_OFF(Action), + SK_PNMI_RW, Perform, 0}, + {OID_SKGE_RESULT, + 1, + 0, + SK_PNMI_MAI_OFF(TestResult), + SK_PNMI_RO, General, 0}, + {OID_SKGE_BUS_TYPE, + 1, + 0, + SK_PNMI_MAI_OFF(BusType), + SK_PNMI_RO, General, 0}, + {OID_SKGE_BUS_SPEED, + 1, + 0, + SK_PNMI_MAI_OFF(BusSpeed), + SK_PNMI_RO, General, 0}, + {OID_SKGE_BUS_WIDTH, + 1, + 0, + SK_PNMI_MAI_OFF(BusWidth), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_SW_QUEUE_LEN, + 1, + 0, + SK_PNMI_MAI_OFF(TxSwQueueLen), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_SW_QUEUE_MAX, + 1, + 0, + SK_PNMI_MAI_OFF(TxSwQueueMax), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_RETRY, + 1, + 0, + SK_PNMI_MAI_OFF(TxRetryCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RX_INTR_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RxIntrCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_INTR_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(TxIntrCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RX_NO_BUF_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RxNoBufCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_NO_BUF_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(TxNoBufCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_USED_DESCR_NO, + 1, + 0, + SK_PNMI_MAI_OFF(TxUsedDescrNo), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RX_DELIVERED_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RxDeliveredCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RX_OCTETS_DELIV_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RxOctetsDeliveredCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RX_HW_ERROR_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RxHwErrorsCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TX_HW_ERROR_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(TxHwErrorsCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_IN_ERRORS_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(InErrorsCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_OUT_ERROR_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(OutErrorsCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_ERR_RECOVERY_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(ErrRecoveryCts), + SK_PNMI_RO, General, 0}, + {OID_SKGE_SYSUPTIME, + 1, + 0, + SK_PNMI_MAI_OFF(SysUpTime), + SK_PNMI_RO, General, 0}, + {OID_SKGE_SENSOR_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(SensorNumber), + SK_PNMI_RO, General, 0}, + {OID_SKGE_SENSOR_INDEX, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorIndex), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_DESCR, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorDescr), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_TYPE, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorType), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_VALUE, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorValue), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_WAR_THRES_LOW, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdLow), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_WAR_THRES_UPP, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdHigh), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_ERR_THRES_LOW, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdLow), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_ERR_THRES_UPP, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdHigh), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_STATUS, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorStatus), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_WAR_CTS, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningCts), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_ERR_CTS, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorCts), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_WAR_TIME, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningTimestamp), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_SENSOR_ERR_TIME, + SK_PNMI_SENSOR_ENTRIES, + sizeof(SK_PNMI_SENSOR), + SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorTimestamp), + SK_PNMI_RO, SensorStat, 0}, + {OID_SKGE_CHKSM_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(ChecksumNumber), + SK_PNMI_RO, General, 0}, + {OID_SKGE_CHKSM_RX_OK_CTS, + SKCS_NUM_PROTOCOLS, + sizeof(SK_PNMI_CHECKSUM), + SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxOkCts), + SK_PNMI_RO, CsumStat, 0}, + {OID_SKGE_CHKSM_RX_UNABLE_CTS, + SKCS_NUM_PROTOCOLS, + sizeof(SK_PNMI_CHECKSUM), + SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxUnableCts), + SK_PNMI_RO, CsumStat, 0}, + {OID_SKGE_CHKSM_RX_ERR_CTS, + SKCS_NUM_PROTOCOLS, + sizeof(SK_PNMI_CHECKSUM), + SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxErrCts), + SK_PNMI_RO, CsumStat, 0}, + {OID_SKGE_CHKSM_TX_OK_CTS, + SKCS_NUM_PROTOCOLS, + sizeof(SK_PNMI_CHECKSUM), + SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxOkCts), + SK_PNMI_RO, CsumStat, 0}, + {OID_SKGE_CHKSM_TX_UNABLE_CTS, + SKCS_NUM_PROTOCOLS, + sizeof(SK_PNMI_CHECKSUM), + SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxUnableCts), + SK_PNMI_RO, CsumStat, 0}, + {OID_SKGE_STAT_TX, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX}, + {OID_SKGE_STAT_TX_OCTETS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOctetsOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_OCTET}, + {OID_SKGE_STAT_TX_BROADCAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBroadcastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BROADCAST}, + {OID_SKGE_STAT_TX_MULTICAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMulticastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTICAST}, + {OID_SKGE_STAT_TX_UNICAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUnicastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNICAST}, + {OID_SKGE_STAT_TX_LONGFRAMES, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLongFramesCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LONGFRAMES}, + {OID_SKGE_STAT_TX_BURST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBurstCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BURST}, + {OID_SKGE_STAT_TX_PFLOWC, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxPauseMacCtrlCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_PMACC}, + {OID_SKGE_STAT_TX_FLOWC, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMacCtrlCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MACC}, + {OID_SKGE_STAT_TX_SINGLE_COL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSingleCollisionCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SINGLE_COL}, + {OID_SKGE_STAT_TX_MULTI_COL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMultipleCollisionCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTI_COL}, + {OID_SKGE_STAT_TX_EXCESS_COL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveCollisionCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_COL}, + {OID_SKGE_STAT_TX_LATE_COL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLateCollisionCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LATE_COL}, + {OID_SKGE_STAT_TX_DEFFERAL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxDeferralCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_DEFFERAL}, + {OID_SKGE_STAT_TX_EXCESS_DEF, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveDeferralCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_DEF}, + {OID_SKGE_STAT_TX_UNDERRUN, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxFifoUnderrunCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNDERRUN}, + {OID_SKGE_STAT_TX_CARRIER, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxCarrierCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_CARRIER}, +/* {OID_SKGE_STAT_TX_UTIL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUtilization), + SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */ + {OID_SKGE_STAT_TX_64, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx64Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_64}, + {OID_SKGE_STAT_TX_127, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx127Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_127}, + {OID_SKGE_STAT_TX_255, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx255Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_255}, + {OID_SKGE_STAT_TX_511, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx511Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_511}, + {OID_SKGE_STAT_TX_1023, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx1023Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_1023}, + {OID_SKGE_STAT_TX_MAX, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMaxCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MAX}, + {OID_SKGE_STAT_TX_SYNC, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC}, + {OID_SKGE_STAT_TX_SYNC_OCTETS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncOctetsCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC_OCTET}, + {OID_SKGE_STAT_RX, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX}, + {OID_SKGE_STAT_RX_OCTETS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOctetsOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OCTET}, + {OID_SKGE_STAT_RX_BROADCAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBroadcastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BROADCAST}, + {OID_SKGE_STAT_RX_MULTICAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMulticastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MULTICAST}, + {OID_SKGE_STAT_RX_UNICAST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUnicastOkCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_UNICAST}, + {OID_SKGE_STAT_RX_LONGFRAMES, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxLongFramesCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_LONGFRAMES}, + {OID_SKGE_STAT_RX_PFLOWC, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC}, + {OID_SKGE_STAT_RX_FLOWC, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC}, + {OID_SKGE_STAT_RX_PFLOWC_ERR, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlErrorCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC_ERR}, + {OID_SKGE_STAT_RX_FLOWC_UNKWN, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlUnknownCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC_UNKWN}, + {OID_SKGE_STAT_RX_BURST, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBurstCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BURST}, + {OID_SKGE_STAT_RX_MISSED, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMissedCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MISSED}, + {OID_SKGE_STAT_RX_FRAMING, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFramingCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FRAMING}, + {OID_SKGE_STAT_RX_OVERFLOW, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFifoOverflowCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OVERFLOW}, + {OID_SKGE_STAT_RX_JABBER, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxJabberCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_JABBER}, + {OID_SKGE_STAT_RX_CARRIER, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCarrierCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CARRIER}, + {OID_SKGE_STAT_RX_IR_LENGTH, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxIRLengthCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_IRLENGTH}, + {OID_SKGE_STAT_RX_SYMBOL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxSymbolCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SYMBOL}, + {OID_SKGE_STAT_RX_SHORTS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxShortsCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SHORTS}, + {OID_SKGE_STAT_RX_RUNT, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxRuntCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_RUNT}, + {OID_SKGE_STAT_RX_CEXT, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCextCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CEXT}, + {OID_SKGE_STAT_RX_TOO_LONG, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxTooLongCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_TOO_LONG}, + {OID_SKGE_STAT_RX_FCS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFcsCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FCS}, +/* {OID_SKGE_STAT_RX_UTIL, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUtilization), + SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */ + {OID_SKGE_STAT_RX_64, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx64Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_64}, + {OID_SKGE_STAT_RX_127, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx127Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_127}, + {OID_SKGE_STAT_RX_255, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx255Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_255}, + {OID_SKGE_STAT_RX_511, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx511Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_511}, + {OID_SKGE_STAT_RX_1023, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx1023Cts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_1023}, + {OID_SKGE_STAT_RX_MAX, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_STAT), + SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMaxCts), + SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MAX}, + {OID_SKGE_PHYS_CUR_ADDR, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacCurrentAddr), + SK_PNMI_RW, Addr, 0}, + {OID_SKGE_PHYS_FAC_ADDR, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacFactoryAddr), + SK_PNMI_RO, Addr, 0}, + {OID_SKGE_PMD, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPMD), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_CONNECTOR, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfConnector), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_LINK_CAP, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkCapability), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_LINK_MODE, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkMode), + SK_PNMI_RW, MacPrivateConf, 0}, + {OID_SKGE_LINK_MODE_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkModeStatus), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_LINK_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkStatus), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_FLOWCTRL_CAP, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlCapability), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_FLOWCTRL_MODE, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlMode), + SK_PNMI_RW, MacPrivateConf, 0}, + {OID_SKGE_FLOWCTRL_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlStatus), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_PHY_OPERATION_CAP, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationCapability), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_PHY_OPERATION_MODE, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationMode), + SK_PNMI_RW, MacPrivateConf, 0}, + {OID_SKGE_PHY_OPERATION_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationStatus), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_SPEED_CAP, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedCapability), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_SPEED_MODE, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedMode), + SK_PNMI_RW, MacPrivateConf, 0}, + {OID_SKGE_SPEED_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_CONF), + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedStatus), + SK_PNMI_RO, MacPrivateConf, 0}, + {OID_SKGE_TRAP, + 1, + 0, + SK_PNMI_MAI_OFF(Trap), + SK_PNMI_RO, General, 0}, + {OID_SKGE_TRAP_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(TrapNumber), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RLMT_MODE, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtMode), + SK_PNMI_RW, Rlmt, 0}, + {OID_SKGE_RLMT_PORT_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtPortNumber), + SK_PNMI_RO, Rlmt, 0}, + {OID_SKGE_RLMT_PORT_ACTIVE, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtPortActive), + SK_PNMI_RO, Rlmt, 0}, + {OID_SKGE_RLMT_PORT_PREFERRED, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtPortPreferred), + SK_PNMI_RW, Rlmt, 0}, + {OID_SKGE_RLMT_CHANGE_CTS, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtChangeCts), + SK_PNMI_RO, Rlmt, 0}, + {OID_SKGE_RLMT_CHANGE_TIME, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtChangeTime), + SK_PNMI_RO, Rlmt, 0}, + {OID_SKGE_RLMT_CHANGE_ESTIM, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtChangeEstimate), + SK_PNMI_RO, Rlmt, 0}, + {OID_SKGE_RLMT_CHANGE_THRES, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtChangeThreshold), + SK_PNMI_RW, Rlmt, 0}, + {OID_SKGE_RLMT_PORT_INDEX, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtIndex), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_STATUS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtStatus), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_TX_HELLO_CTS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxHelloCts), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_RX_HELLO_CTS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxHelloCts), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_TX_SP_REQ_CTS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxSpHelloReqCts), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_RX_SP_CTS, + SK_PNMI_MAC_ENTRIES, + sizeof(SK_PNMI_RLMT), + SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxSpHelloCts), + SK_PNMI_RO, RlmtStat, 0}, + {OID_SKGE_RLMT_MONITOR_NUMBER, + 1, + 0, + SK_PNMI_MAI_OFF(RlmtMonitorNumber), + SK_PNMI_RO, General, 0}, + {OID_SKGE_RLMT_MONITOR_INDEX, + SK_PNMI_MONITOR_ENTRIES, + sizeof(SK_PNMI_RLMT_MONITOR), + SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorIndex), + SK_PNMI_RO, Monitor, 0}, + {OID_SKGE_RLMT_MONITOR_ADDR, + SK_PNMI_MONITOR_ENTRIES, + sizeof(SK_PNMI_RLMT_MONITOR), + SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAddr), + SK_PNMI_RO, Monitor, 0}, + {OID_SKGE_RLMT_MONITOR_ERRS, + SK_PNMI_MONITOR_ENTRIES, + sizeof(SK_PNMI_RLMT_MONITOR), + SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorErrorCts), + SK_PNMI_RO, Monitor, 0}, + {OID_SKGE_RLMT_MONITOR_TIMESTAMP, + SK_PNMI_MONITOR_ENTRIES, + sizeof(SK_PNMI_RLMT_MONITOR), + SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorTimestamp), + SK_PNMI_RO, Monitor, 0}, + {OID_SKGE_RLMT_MONITOR_ADMIN, + SK_PNMI_MONITOR_ENTRIES, + sizeof(SK_PNMI_RLMT_MONITOR), + SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAdmin), + SK_PNMI_RW, Monitor, 0}, + {OID_SKGE_MTU, + 1, + 0, + SK_PNMI_MAI_OFF(MtuSize), + SK_PNMI_RW, MacPrivateConf, 0}, + {OID_SKGE_VCT_GET, + 0, + 0, + 0, + SK_PNMI_RO, Vct, 0}, + {OID_SKGE_VCT_SET, + 0, + 0, + 0, + SK_PNMI_WO, Vct, 0}, + {OID_SKGE_VCT_STATUS, + 0, + 0, + 0, + SK_PNMI_RO, Vct, 0}, +}; + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skgepnmi.c b/drivers/sk98lin/skgepnmi.c new file mode 100644 index 000000000..b5d32b04c --- /dev/null +++ b/drivers/sk98lin/skgepnmi.c @@ -0,0 +1,8310 @@ +/***************************************************************************** + * + * Name: skgepnmi.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.102 $ + * Date: $Date: 2002/12/16 14:03:24 $ + * Purpose: Private Network Management Interface + * + ****************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/***************************************************************************** + * + * History: + * + * $Log: skgepnmi.c,v $ + * Revision 1.102 2002/12/16 14:03:24 tschilli + * VCT code in Vct() changed. + * + * Revision 1.101 2002/12/16 09:04:10 tschilli + * Code for VCT handling added. + * + * Revision 1.100 2002/09/26 14:28:13 tschilli + * For XMAC the values in the SK_PNMI_PORT Port struct are copied to + * the new SK_PNMI_PORT BufPort struct during a MacUpdate() call. + * These values are used when GetPhysStatVal() is called. With this + * mechanism you get the best results when software corrections for + * counters are needed. Example: RX_LONGFRAMES. + * + * Revision 1.99 2002/09/17 12:31:19 tschilli + * OID_SKGE_TX_HW_ERROR_CTS, OID_SKGE_OUT_ERROR_CTS, OID_GEN_XMIT_ERROR: + * Double count of SK_PNMI_HTX_EXCESS_COL in function General() removed. + * OID_PNP_CAPABILITIES: sizeof(SK_PM_WAKE_UP_CAPABILITIES) changed to + * sizeof(SK_PNP_CAPABILITIES) in function PowerManagement(). + * + * Revision 1.98 2002/09/10 09:00:03 rwahl + * Adapted boolean definitions according sktypes. + * + * Revision 1.97 2002/09/05 15:07:03 rwahl + * Editorial changes. + * + * Revision 1.96 2002/09/05 11:04:14 rwahl + * - Rx/Tx packets statistics of virtual port were zero on link down (#10750) + * - For GMAC the overflow IRQ for Rx longframe counter was not counted. + * - Incorrect calculation for oids OID_SKGE_RX_HW_ERROR_CTS, + * OID_SKGE_IN_ERRORS_CTS, OID_GEN_RCV_ERROR. + * - Moved correction for OID_SKGE_STAT_RX_TOO_LONG to GetPhysStatVal(). + * - Editorial changes. + * + * Revision 1.95 2002/09/04 08:53:37 rwahl + * - Incorrect statistics for Rx_too_long counter with jumbo frame (#10751) + * - StatRxFrameTooLong & StatRxPMaccErr counters were not reset. + * - Fixed compiler warning for debug msg arg types. + * + * Revision 1.94 2002/08/09 15:42:14 rwahl + * - Fixed StatAddr table for GMAC. + * - VirtualConf(): returned indeterminated status for speed oids if no + * active port. + * + * Revision 1.93 2002/08/09 11:04:59 rwahl + * Added handler for link speed caps. + * + * Revision 1.92 2002/08/09 09:43:03 rwahl + * - Added handler for NDIS OID_PNP_xxx ids. + * + * Revision 1.91 2002/07/17 19:53:03 rwahl + * - Added StatOvrflwBit table for XMAC & GMAC. + * - Extended StatAddr table for GMAC. Added check of number of counters + * in enumeration and size of StatAddr table on init level. + * - Added use of GIFunc table. + * - ChipSet is not static anymore, + * - Extended SIRQ event handler for both mac types. + * - Fixed rx short counter bug (#10620) + * - Added handler for oids SKGE_SPEED_MODE & SKGE_SPEED_STATUS. + * - Extendet GetPhysStatVal() for GMAC. + * - Editorial changes. + * + * Revision 1.90 2002/05/22 08:56:25 rwahl + * - Moved OID table to separate source file. + * - Fix: TX_DEFFERAL counter incremented in full-duplex mode. + * - Use string definitions for error msgs. + * + * Revision 1.89 2001/09/18 10:01:30 mkunz + * some OID's fixed for dualnetmode + * + * Revision 1.88 2001/08/02 07:58:08 rwahl + * - Fixed NetIndex to csum module at ResetCounter(). + * + * Revision 1.87 2001/04/06 13:35:09 mkunz + * -Bugs fixed in handling of OID_SKGE_MTU and the VPD OID's + * + * Revision 1.86 2001/03/09 09:18:03 mkunz + * Changes in SK_DBG_MSG + * + * Revision 1.85 2001/03/08 09:37:31 mkunz + * Bugfix in ResetCounter for Pnmi.Port structure + * + * Revision 1.84 2001/03/06 09:04:55 mkunz + * Made some changes in instance calculation + * + * Revision 1.83 2001/02/15 09:15:32 mkunz + * Necessary changes for dual net mode added + * + * Revision 1.82 2001/02/07 08:24:19 mkunz + * -Made changes in handling of OID_SKGE_MTU + * + * Revision 1.81 2001/02/06 09:58:00 mkunz + * -Vpd bug fixed + * -OID_SKGE_MTU added + * -pnmi support for dual net mode. Interface function and macros extended + * + * Revision 1.80 2001/01/22 13:41:35 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.79 2000/12/05 14:57:40 cgoos + * SetStruct failed before first Link Up (link mode of virtual + * port "INDETERMINATED"). + * + * Revision 1.78 2000/09/12 10:44:58 cgoos + * Fixed SK_PNMI_STORE_U32 calls with typecasted argument. + * + * Revision 1.77 2000/09/07 08:10:19 rwahl + * - Modified algorithm for 64bit NDIS statistic counters; + * returns 64bit or 32bit value depending on passed buffer + * size. Indicate capability for 64bit NDIS counter, if passed + * buffer size is zero. OID_GEN_XMIT_ERROR, OID_GEN_RCV_ERROR, + * and OID_GEN_RCV_NO_BUFFER handled as 64bit counter, too. + * - corrected OID_SKGE_RLMT_PORT_PREFERRED. + * + * Revision 1.76 2000/08/03 15:23:39 rwahl + * - Correction for FrameTooLong counter has to be moved to OID handling + * routines (instead of statistic counter routine). + * - Fix in XMAC Reset Event handling: Only offset counter for hardware + * statistic registers are updated. + * + * Revision 1.75 2000/08/01 16:46:05 rwahl + * - Added StatRxLongFrames counter and correction of FrameTooLong counter. + * - Added directive to control width (default = 32bit) of NDIS statistic + * counters (SK_NDIS_64BIT_CTR). + * + * Revision 1.74 2000/07/04 11:41:53 rwahl + * - Added volition connector type. + * + * Revision 1.73 2000/03/15 16:33:10 rwahl + * Fixed bug 10510; wrong reset of virtual port statistic counters. + * + * Revision 1.72 1999/12/06 16:15:53 rwahl + * Fixed problem of instance range for current and factory MAC address. + * + * Revision 1.71 1999/12/06 10:14:20 rwahl + * Fixed bug 10476; set operation for PHY_OPERATION_MODE. + * + * Revision 1.70 1999/11/22 13:33:34 cgoos + * Changed license header to GPL. + * + * Revision 1.69 1999/10/18 11:42:15 rwahl + * Added typecasts for checking event dependent param (debug only). + * + * Revision 1.68 1999/10/06 09:35:59 cgoos + * Added state check to PHY_READ call (hanged if called during startup). + * + * Revision 1.67 1999/09/22 09:53:20 rwahl + * - Read Broadcom register for updating fcs error counter (1000Base-T). + * + * Revision 1.66 1999/08/26 13:47:56 rwahl + * Added SK_DRIVER_SENDEVENT when queueing RLMT_CHANGE_THRES trap. + * + * Revision 1.65 1999/07/26 07:49:35 cgoos + * Added two typecasts to avoid compiler warnings. + * + * Revision 1.64 1999/05/20 09:24:12 cgoos + * Changes for 1000Base-T (sensors, Master/Slave). + * + * Revision 1.63 1999/04/13 15:11:58 mhaveman + * Moved include of rlmt.h to header skgepnmi.h because some macros + * are needed there. + * + * Revision 1.62 1999/04/13 15:08:07 mhaveman + * Replaced again SK_RLMT_CHECK_LINK with SK_PNMI_RLMT_MODE_CHK_LINK + * to grant unified interface by only using the PNMI header file. + * SK_PNMI_RLMT_MODE_CHK_LINK is defined the same as SK_RLMT_CHECK_LINK. + * + * Revision 1.61 1999/04/13 15:02:48 mhaveman + * Changes caused by review: + * -Changed some comments + * -Removed redundant check for OID_SKGE_PHYS_FAC_ADDR + * -Optimized PRESET check. + * -Meaning of error SK_ADDR_DUPLICATE_ADDRESS changed. Set of same + * address will now not cause this error. Removed corresponding check. + * + * Revision 1.60 1999/03/23 10:41:23 mhaveman + * Added comments. + * + * Revision 1.59 1999/02/19 08:01:28 mhaveman + * Fixed bug 10372 that after counter reset all ports were displayed + * as inactive. + * + * Revision 1.58 1999/02/16 18:04:47 mhaveman + * Fixed problem of twisted OIDs SENSOR_WAR_TIME and SENSOR_ERR_TIME. + * + * Revision 1.56 1999/01/27 12:29:11 mhaveman + * SkTimerStart was called with time value in milli seconds but needs + * micro seconds. + * + * Revision 1.55 1999/01/25 15:00:38 mhaveman + * Added support to allow multiple ports to be active. If this feature in + * future will be used, the Management Data Base variables PORT_ACTIVE + * and PORT_PREFERED should be moved to the port specific part of RLMT. + * Currently they return the values of the first active physical port + * found. A set to the virtual port will actually change all active + * physical ports. A get returns the melted values of all active physical + * ports. If the port values differ a return value INDETERMINATED will + * be returned. This effects especially the CONF group. + * + * Revision 1.54 1999/01/19 10:10:22 mhaveman + * -Fixed bug 10354: Counter values of virtual port were wrong after port + * switches + * -Added check if a switch to the same port is notified. + * + * Revision 1.53 1999/01/07 09:25:21 mhaveman + * Forgot to initialize a variable. + * + * Revision 1.52 1999/01/05 10:34:33 mhaveman + * Fixed little error in RlmtChangeEstimate calculation. + * + * Revision 1.51 1999/01/05 09:59:07 mhaveman + * -Moved timer start to init level 2 + * -Redesigned port switch average calculation to avoid 64bit + * arithmetic. + * + * Revision 1.50 1998/12/10 15:13:59 mhaveman + * -Fixed: PHYS_CUR_ADDR returned wrong addresses + * -Fixed: RLMT_PORT_PREFERED and RLMT_CHANGE_THRES preset returned + * always BAD_VALUE. + * -Fixed: TRAP buffer seemed to sometimes suddenly empty + * + * Revision 1.49 1998/12/09 16:17:07 mhaveman + * Fixed: Couldnot delete VPD keys on UNIX. + * + * Revision 1.48 1998/12/09 14:11:10 mhaveman + * -Add: Debugmessage for XMAC_RESET supressed to minimize output. + * -Fixed: RlmtChangeThreshold will now be initialized. + * -Fixed: VPD_ENTRIES_LIST extended value with unnecessary space char. + * -Fixed: On VPD key creation an invalid key name could be created + * (e.g. A5) + * -Some minor changes in comments and code. + * + * Revision 1.47 1998/12/08 16:00:31 mhaveman + * -Fixed: For RLMT_PORT_ACTIVE will now be returned a 0 if no port + * is active. + * -Fixed: For the RLMT statistics group only the last value was + * returned and the rest of the buffer was filled with 0xff + * -Fixed: Mysteriously the preset on RLMT_MODE still returned + * BAD_VALUE. + * Revision 1.46 1998/12/08 10:04:56 mhaveman + * -Fixed: Preset on RLMT_MODE returned always BAD_VALUE error. + * -Fixed: Alignment error in GetStruct + * -Fixed: If for Get/Preset/SetStruct the buffer size is equal or + * larger than SK_PNMI_MIN_STRUCT_SIZE the return value is stored + * to the buffer. In this case the caller should always return + * ok to its upper routines. Only if the buffer size is less + * than SK_PNMI_MIN_STRUCT_SIZE and the return value is unequal + * to 0, an error should be returned by the caller. + * -Fixed: Wrong number of instances with RLMT statistic. + * -Fixed: Return now SK_LMODE_STAT_UNKNOWN if the LinkModeStatus is 0. + * + * Revision 1.45 1998/12/03 17:17:24 mhaveman + * -Removed for VPD create action the buffer size limitation to 4 bytes. + * -Pass now physical/active physical port to ADDR for CUR_ADDR set + * + * Revision 1.44 1998/12/03 15:14:35 mhaveman + * Another change to Vpd instance evaluation. + * + * Revision 1.43 1998/12/03 14:18:10 mhaveman + * -Fixed problem in PnmiSetStruct. It was impossible to set any value. + * -Removed VPD key evaluation for VPD_FREE_BYTES and VPD_ACTION. + * + * Revision 1.42 1998/12/03 11:31:47 mhaveman + * Inserted cast to satisfy lint. + * + * Revision 1.41 1998/12/03 11:28:16 mhaveman + * Removed SK_PNMI_CHECKPTR + * + * Revision 1.40 1998/12/03 11:19:07 mhaveman + * Fixed problems + * -A set to virtual port will now be ignored. A set with broadcast + * address to any port will be ignored. + * -GetStruct function made VPD instance calculation wrong. + * -Prefered port returned -1 instead of 0. + * + * Revision 1.39 1998/11/26 15:30:29 mhaveman + * Added sense mode to link mode. + * + * Revision 1.38 1998/11/23 15:34:00 mhaveman + * -Fixed bug for RX counters. On an RX overflow interrupt the high + * words of all RX counters were incremented. + * -SET operations on FLOWCTRL_MODE and LINK_MODE accept now the + * value 0, which has no effect. It is usefull for multiple instance + * SETs. + * + * Revision 1.37 1998/11/20 08:02:04 mhaveman + * -Fixed: Ports were compared with MAX_SENSORS + * -Fixed: Crash in GetTrapEntry with MEMSET macro + * -Fixed: Conversions between physical, logical port index and instance + * + * Revision 1.36 1998/11/16 07:48:53 mhaveman + * Casted SK_DRIVER_SENDEVENT with (void) to eleminate compiler warnings + * on Solaris. + * + * Revision 1.35 1998/11/16 07:45:34 mhaveman + * SkAddrOverride now returns value and will be checked. + * + * Revision 1.34 1998/11/10 13:40:37 mhaveman + * Needed to change interface, because NT driver needs a return value + * of needed buffer space on TOO_SHORT errors. Therefore all + * SkPnmiGet/Preset/Set functions now have a pointer to the length + * parameter, where the needed space on error is returned. + * + * Revision 1.33 1998/11/03 13:52:46 mhaveman + * Made file lint conform. + * + * Revision 1.32 1998/11/03 13:19:07 mhaveman + * The events SK_HWEV_SET_LMODE and SK_HWEV_SET_FLOWMODE pass now in + * Para32[0] the physical MAC index and in Para32[1] the new mode. + * + * Revision 1.31 1998/11/03 12:30:40 gklug + * fix: compiler warning memset + * + * Revision 1.30 1998/11/03 12:04:46 mhaveman + * Fixed problem in SENSOR_VALUE, which wrote beyond the buffer end + * Fixed alignment problem with CHIPSET. + * + * Revision 1.29 1998/11/02 11:23:54 mhaveman + * Corrected SK_ERROR_LOG to SK_ERR_LOG. Sorry. + * + * Revision 1.28 1998/11/02 10:47:16 mhaveman + * Added syslog messages for internal errors. + * + * Revision 1.27 1998/10/30 15:48:06 mhaveman + * Fixed problems after simulation of SK_PNMI_EVT_CHG_EST_TIMER and + * RlmtChangeThreshold calculation. + * + * Revision 1.26 1998/10/29 15:36:55 mhaveman + * -Fixed bug in trap buffer handling. + * -OID_SKGE_DRIVER_DESCR, OID_SKGE_DRIVER_VERSION, OID_SKGE_HW_DESCR, + * OID_SKGE_HW_VERSION, OID_SKGE_VPD_ENTRIES_LIST, OID_SKGE_VPD_KEY, + * OID_SKGE_VPD_VALUE, and OID_SKGE_SENSOR_DESCR return values with + * a leading octet before each string storing the string length. + * -Perform a RlmtUpdate during SK_PNMI_EVT_XMAC_RESET to minimize + * RlmtUpdate calls in GetStatVal. + * -Inserted SK_PNMI_CHECKFLAGS macro increase readability. + * + * Revision 1.25 1998/10/29 08:50:36 mhaveman + * Fixed problems after second event simulation. + * + * Revision 1.24 1998/10/28 08:44:37 mhaveman + * -Fixed alignment problem + * -Fixed problems during event simulation + * -Fixed sequence of error return code (INSTANCE -> ACCESS -> SHORT) + * -Changed type of parameter Instance back to SK_U32 because of VPD + * -Updated new VPD function calls + * + * Revision 1.23 1998/10/23 10:16:37 mhaveman + * Fixed bugs after buffer test simulation. + * + * Revision 1.22 1998/10/21 13:23:52 mhaveman + * -Call syntax of SkOsGetTime() changed to SkOsGetTime(pAc). + * -Changed calculation of hundrets of seconds. + * + * Revision 1.20 1998/10/20 07:30:45 mhaveman + * Made type changes to unsigned integer where possible. + * + * Revision 1.19 1998/10/19 10:51:30 mhaveman + * -Made Bug fixes after simulation run + * -Renamed RlmtMAC... to RlmtPort... + * -Marked workarounds with Errata comments + * + * Revision 1.18 1998/10/14 07:50:08 mhaveman + * -For OID_SKGE_LINK_STATUS the link down detection has moved from RLMT + * to HWACCESS. + * -Provided all MEMCPY/MEMSET macros with (char *) pointers, because + * Solaris throwed warnings when mapping to bcopy/bset. + * + * Revision 1.17 1998/10/13 07:42:01 mhaveman + * -Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA + * -Removed old cvs history entries + * -Renamed MacNumber to PortNumber + * + * Revision 1.16 1998/10/07 10:52:49 mhaveman + * -Inserted handling of some OID_GEN_ Ids for windows + * -Fixed problem with 803.2 statistic. + * + * Revision 1.15 1998/10/01 09:16:29 mhaveman + * Added Debug messages for function call and UpdateFlag tracing. + * + * Revision 1.14 1998/09/30 13:39:09 mhaveman + * -Reduced namings of 'MAC' by replacing them with 'PORT'. + * -Completed counting of OID_SKGE_RX_HW_ERROR_CTS, + * OID_SKGE_TX_HW_ERROR_CTS, + * OID_SKGE_IN_ERRORS_CTS, and OID_SKGE_OUT_ERROR_CTS. + * -SET check for RlmtMode + * + * Revision 1.13 1998/09/28 13:13:08 mhaveman + * Hide strcmp, strlen, and strncpy behind macros SK_STRCMP, SK_STRLEN, + * and SK_STRNCPY. (Same reasons as for mem.. and MEM..) + * + * Revision 1.12 1998/09/16 08:18:36 cgoos + * Fix: XM_INxx and XM_OUTxx called with different parameter order: + * sometimes IoC,Mac,... sometimes Mac,IoC,... Now always first variant. + * Fix: inserted "Pnmi." into some pAC->pDriverDescription / Version. + * Change: memset, memcpy to makros SK_MEMSET, SK_MEMCPY + * + * Revision 1.11 1998/09/04 17:01:45 mhaveman + * Added SyncCounter as macro and OID_SKGE_.._NO_DESCR_CTS to + * OID_SKGE_RX_NO_BUF_CTS. + * + * Revision 1.10 1998/09/04 14:35:35 mhaveman + * Added macro counters, that are counted by driver. + * + ****************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +static const char SysKonnectFileId[] = + "@(#) $Id: skgepnmi.c,v 1.102 2002/12/16 14:03:24 tschilli Exp $" + " (C) SysKonnect."; + +#include "h/skdrv1st.h" +#include "h/sktypes.h" +#include "h/xmac_ii.h" +#include "h/skdebug.h" +#include "h/skqueue.h" +#include "h/skgepnmi.h" +#include "h/skgesirq.h" +#include "h/skcsum.h" +#include "h/skvpd.h" +#include "h/skgehw.h" +#include "h/skgeinit.h" +#include "h/skdrv2nd.h" +#include "h/skgepnm2.h" +#ifdef SK_POWER_MGMT +#include "h/skgepmgt.h" +#endif +/* defines *******************************************************************/ + +#ifndef DEBUG +#define PNMI_STATIC static +#else /* DEBUG */ +#define PNMI_STATIC +#endif /* DEBUG */ + +/* + * Public Function prototypes + */ +int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int level); +int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf, + unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf, + unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf, + unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, + unsigned int *pLen, SK_U32 NetIndex); +int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, + unsigned int *pLen, SK_U32 NetIndex); +int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf, + unsigned int *pLen, SK_U32 NetIndex); +int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param); + + +/* + * Private Function prototypes + */ + +PNMI_STATIC SK_U8 CalculateLinkModeStatus(SK_AC *pAC, SK_IOC IoC, unsigned int + PhysPortIndex); +PNMI_STATIC SK_U8 CalculateLinkStatus(SK_AC *pAC, SK_IOC IoC, unsigned int + PhysPortIndex); +PNMI_STATIC void CopyMac(char *pDst, SK_MAC_ADDR *pMac); +PNMI_STATIC void CopyTrapQueue(SK_AC *pAC, char *pDstBuf); +PNMI_STATIC SK_U64 GetPhysStatVal(SK_AC *pAC, SK_IOC IoC, + unsigned int PhysPortIndex, unsigned int StatIndex); +PNMI_STATIC SK_U64 GetStatVal(SK_AC *pAC, SK_IOC IoC, unsigned int LogPortIndex, + unsigned int StatIndex, SK_U32 NetIndex); +PNMI_STATIC char* GetTrapEntry(SK_AC *pAC, SK_U32 TrapId, unsigned int Size); +PNMI_STATIC void GetTrapQueueLen(SK_AC *pAC, unsigned int *pLen, + unsigned int *pEntries); +PNMI_STATIC int GetVpdKeyArr(SK_AC *pAC, SK_IOC IoC, char *pKeyArr, + unsigned int KeyArrLen, unsigned int *pKeyNo); +PNMI_STATIC int LookupId(SK_U32 Id); +PNMI_STATIC int MacUpdate(SK_AC *pAC, SK_IOC IoC, unsigned int FirstMac, + unsigned int LastMac); +PNMI_STATIC int PnmiStruct(SK_AC *pAC, SK_IOC IoC, int Action, char *pBuf, + unsigned int *pLen, SK_U32 NetIndex); +PNMI_STATIC int PnmiVar(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id, + char *pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex); +PNMI_STATIC void QueueRlmtNewMacTrap(SK_AC *pAC, unsigned int ActiveMac); +PNMI_STATIC void QueueRlmtPortTrap(SK_AC *pAC, SK_U32 TrapId, + unsigned int PortIndex); +PNMI_STATIC void QueueSensorTrap(SK_AC *pAC, SK_U32 TrapId, + unsigned int SensorIndex); +PNMI_STATIC void QueueSimpleTrap(SK_AC *pAC, SK_U32 TrapId); +PNMI_STATIC void ResetCounter(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex); +PNMI_STATIC int RlmtUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex); +PNMI_STATIC int SirqUpdate(SK_AC *pAC, SK_IOC IoC); +PNMI_STATIC void VirtualConf(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, char *pBuf); +PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id, char *pBuf, + unsigned int *pLen, SK_U32 Instance, unsigned int TableIndex, SK_U32 NetIndex); +PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32); + +/* + * Table to correlate OID with handler function and index to + * hardware register stored in StatAddress if applicable. + */ +#include "skgemib.c" + +/* global variables **********************************************************/ + +/* + * Overflow status register bit table and corresponding counter + * dependent on MAC type - the number relates to the size of overflow + * mask returned by the pFnMacOverflow function + */ +PNMI_STATIC const SK_U16 StatOvrflwBit[][SK_PNMI_MAC_TYPES] = { +/* Bit0 */ { SK_PNMI_HTX, SK_PNMI_HTX_UNICAST}, +/* Bit1 */ { SK_PNMI_HTX_OCTETHIGH, SK_PNMI_HTX_BROADCAST}, +/* Bit2 */ { SK_PNMI_HTX_OCTETLOW, SK_PNMI_HTX_PMACC}, +/* Bit3 */ { SK_PNMI_HTX_BROADCAST, SK_PNMI_HTX_MULTICAST}, +/* Bit4 */ { SK_PNMI_HTX_MULTICAST, SK_PNMI_HTX_OCTETLOW}, +/* Bit5 */ { SK_PNMI_HTX_UNICAST, SK_PNMI_HTX_OCTETHIGH}, +/* Bit6 */ { SK_PNMI_HTX_LONGFRAMES, SK_PNMI_HTX_64}, +/* Bit7 */ { SK_PNMI_HTX_BURST, SK_PNMI_HTX_127}, +/* Bit8 */ { SK_PNMI_HTX_PMACC, SK_PNMI_HTX_255}, +/* Bit9 */ { SK_PNMI_HTX_MACC, SK_PNMI_HTX_511}, +/* Bit10 */ { SK_PNMI_HTX_SINGLE_COL, SK_PNMI_HTX_1023}, +/* Bit11 */ { SK_PNMI_HTX_MULTI_COL, SK_PNMI_HTX_MAX}, +/* Bit12 */ { SK_PNMI_HTX_EXCESS_COL, SK_PNMI_HTX_LONGFRAMES}, +/* Bit13 */ { SK_PNMI_HTX_LATE_COL, SK_PNMI_HTX_RESERVED}, +/* Bit14 */ { SK_PNMI_HTX_DEFFERAL, SK_PNMI_HTX_COL}, +/* Bit15 */ { SK_PNMI_HTX_EXCESS_DEF, SK_PNMI_HTX_LATE_COL}, +/* Bit16 */ { SK_PNMI_HTX_UNDERRUN, SK_PNMI_HTX_EXCESS_COL}, +/* Bit17 */ { SK_PNMI_HTX_CARRIER, SK_PNMI_HTX_MULTI_COL}, +/* Bit18 */ { SK_PNMI_HTX_UTILUNDER, SK_PNMI_HTX_SINGLE_COL}, +/* Bit19 */ { SK_PNMI_HTX_UTILOVER, SK_PNMI_HTX_UNDERRUN}, +/* Bit20 */ { SK_PNMI_HTX_64, SK_PNMI_HTX_RESERVED}, +/* Bit21 */ { SK_PNMI_HTX_127, SK_PNMI_HTX_RESERVED}, +/* Bit22 */ { SK_PNMI_HTX_255, SK_PNMI_HTX_RESERVED}, +/* Bit23 */ { SK_PNMI_HTX_511, SK_PNMI_HTX_RESERVED}, +/* Bit24 */ { SK_PNMI_HTX_1023, SK_PNMI_HTX_RESERVED}, +/* Bit25 */ { SK_PNMI_HTX_MAX, SK_PNMI_HTX_RESERVED}, +/* Bit26 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit27 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit28 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit29 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit30 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit31 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit32 */ { SK_PNMI_HRX, SK_PNMI_HRX_UNICAST}, +/* Bit33 */ { SK_PNMI_HRX_OCTETHIGH, SK_PNMI_HRX_BROADCAST}, +/* Bit34 */ { SK_PNMI_HRX_OCTETLOW, SK_PNMI_HRX_PMACC}, +/* Bit35 */ { SK_PNMI_HRX_BROADCAST, SK_PNMI_HRX_MULTICAST}, +/* Bit36 */ { SK_PNMI_HRX_MULTICAST, SK_PNMI_HRX_FCS}, +/* Bit37 */ { SK_PNMI_HRX_UNICAST, SK_PNMI_HRX_RESERVED}, +/* Bit38 */ { SK_PNMI_HRX_PMACC, SK_PNMI_HRX_OCTETLOW}, +/* Bit39 */ { SK_PNMI_HRX_MACC, SK_PNMI_HRX_OCTETHIGH}, +/* Bit40 */ { SK_PNMI_HRX_PMACC_ERR, SK_PNMI_HRX_BADOCTETLOW}, +/* Bit41 */ { SK_PNMI_HRX_MACC_UNKWN, SK_PNMI_HRX_BADOCTETHIGH}, +/* Bit42 */ { SK_PNMI_HRX_BURST, SK_PNMI_HRX_UNDERSIZE}, +/* Bit43 */ { SK_PNMI_HRX_MISSED, SK_PNMI_HRX_RUNT}, +/* Bit44 */ { SK_PNMI_HRX_FRAMING, SK_PNMI_HRX_64}, +/* Bit45 */ { SK_PNMI_HRX_OVERFLOW, SK_PNMI_HRX_127}, +/* Bit46 */ { SK_PNMI_HRX_JABBER, SK_PNMI_HRX_255}, +/* Bit47 */ { SK_PNMI_HRX_CARRIER, SK_PNMI_HRX_511}, +/* Bit48 */ { SK_PNMI_HRX_IRLENGTH, SK_PNMI_HRX_1023}, +/* Bit49 */ { SK_PNMI_HRX_SYMBOL, SK_PNMI_HRX_MAX}, +/* Bit50 */ { SK_PNMI_HRX_SHORTS, SK_PNMI_HRX_LONGFRAMES}, +/* Bit51 */ { SK_PNMI_HRX_RUNT, SK_PNMI_HRX_TOO_LONG}, +/* Bit52 */ { SK_PNMI_HRX_TOO_LONG, SK_PNMI_HRX_JABBER}, +/* Bit53 */ { SK_PNMI_HRX_FCS, SK_PNMI_HRX_RESERVED}, +/* Bit54 */ { SK_PNMI_HRX_RESERVED, SK_PNMI_HRX_OVERFLOW}, +/* Bit55 */ { SK_PNMI_HRX_CEXT, SK_PNMI_HRX_RESERVED}, +/* Bit56 */ { SK_PNMI_HRX_UTILUNDER, SK_PNMI_HRX_RESERVED}, +/* Bit57 */ { SK_PNMI_HRX_UTILOVER, SK_PNMI_HRX_RESERVED}, +/* Bit58 */ { SK_PNMI_HRX_64, SK_PNMI_HRX_RESERVED}, +/* Bit59 */ { SK_PNMI_HRX_127, SK_PNMI_HRX_RESERVED}, +/* Bit60 */ { SK_PNMI_HRX_255, SK_PNMI_HRX_RESERVED}, +/* Bit61 */ { SK_PNMI_HRX_511, SK_PNMI_HRX_RESERVED}, +/* Bit62 */ { SK_PNMI_HRX_1023, SK_PNMI_HRX_RESERVED}, +/* Bit63 */ { SK_PNMI_HRX_MAX, SK_PNMI_HRX_RESERVED} +}; + +/* + * Table for hardware register saving on resets and port switches + */ +PNMI_STATIC const SK_PNMI_STATADDR StatAddr[SK_PNMI_MAX_IDX][SK_PNMI_MAC_TYPES] = { + /* SK_PNMI_HTX */ + {{XM_TXF_OK, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_OCTETHIGH */ + {{XM_TXO_OK_HI, SK_TRUE}, {GM_TXO_OK_HI, SK_TRUE}}, + /* SK_PNMI_HTX_OCTETLOW */ + {{XM_TXO_OK_LO, SK_FALSE}, {GM_TXO_OK_LO, SK_FALSE}}, + /* SK_PNMI_HTX_BROADCAST */ + {{XM_TXF_BC_OK, SK_TRUE}, {GM_TXF_BC_OK, SK_TRUE}}, + /* SK_PNMI_HTX_MULTICAST */ + {{XM_TXF_MC_OK, SK_TRUE}, {GM_TXF_MC_OK, SK_TRUE}}, + /* SK_PNMI_HTX_UNICAST */ + {{XM_TXF_UC_OK, SK_TRUE}, {GM_TXF_UC_OK, SK_TRUE}}, + /* SK_PNMI_HTX_BURST */ + {{XM_TXE_BURST, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_PMACC */ + {{XM_TXF_MPAUSE, SK_TRUE}, {GM_TXF_MPAUSE, SK_TRUE}}, + /* SK_PNMI_HTX_MACC */ + {{XM_TXF_MCTRL, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_COL */ + {{0, SK_FALSE}, {GM_TXF_COL, SK_TRUE}}, + /* SK_PNMI_HTX_SINGLE_COL */ + {{XM_TXF_SNG_COL, SK_TRUE}, {GM_TXF_SNG_COL, SK_TRUE}}, + /* SK_PNMI_HTX_MULTI_COL */ + {{XM_TXF_MUL_COL, SK_TRUE}, {GM_TXF_MUL_COL, SK_TRUE}}, + /* SK_PNMI_HTX_EXCESS_COL */ + {{XM_TXF_ABO_COL, SK_TRUE}, {GM_TXF_ABO_COL, SK_TRUE}}, + /* SK_PNMI_HTX_LATE_COL */ + {{XM_TXF_LAT_COL, SK_TRUE}, {GM_TXF_LAT_COL, SK_TRUE}}, + /* SK_PNMI_HTX_DEFFERAL */ + {{XM_TXF_DEF, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_EXCESS_DEF */ + {{XM_TXF_EX_DEF, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_UNDERRUN */ + {{XM_TXE_FIFO_UR, SK_TRUE}, {GM_TXE_FIFO_UR, SK_TRUE}}, + /* SK_PNMI_HTX_CARRIER */ + {{XM_TXE_CS_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_UTILUNDER */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_UTILOVER */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_64 */ + {{XM_TXF_64B, SK_TRUE}, {GM_TXF_64B, SK_TRUE}}, + /* SK_PNMI_HTX_127 */ + {{XM_TXF_127B, SK_TRUE}, {GM_TXF_127B, SK_TRUE}}, + /* SK_PNMI_HTX_255 */ + {{XM_TXF_255B, SK_TRUE}, {GM_TXF_255B, SK_TRUE}}, + /* SK_PNMI_HTX_511 */ + {{XM_TXF_511B, SK_TRUE}, {GM_TXF_511B, SK_TRUE}}, + /* SK_PNMI_HTX_1023 */ + {{XM_TXF_1023B, SK_TRUE}, {GM_TXF_1023B, SK_TRUE}}, + /* SK_PNMI_HTX_MAX */ + {{XM_TXF_MAX_SZ, SK_TRUE}, {GM_TXF_1518B, SK_TRUE}}, + /* SK_PNMI_HTX_LONGFRAMES */ + {{XM_TXF_LONG, SK_TRUE}, {GM_TXF_MAX_SZ, SK_TRUE}}, + /* SK_PNMI_HTX_SYNC */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_SYNC_OCTET */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HTX_RESERVED */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX */ + {{XM_RXF_OK, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_OCTETHIGH */ + {{XM_RXO_OK_HI, SK_TRUE}, {GM_RXO_OK_HI, SK_TRUE}}, + /* SK_PNMI_HRX_OCTETLOW */ + {{XM_RXO_OK_LO, SK_FALSE}, {GM_RXO_OK_LO, SK_FALSE}}, + /* SK_PNMI_HRX_BADOCTETHIGH */ + {{0, SK_FALSE}, {GM_RXO_ERR_HI, SK_TRUE}}, + /* SK_PNMI_HRX_BADOCTETLOW */ + {{0, SK_FALSE}, {GM_RXO_ERR_LO, SK_TRUE}}, + /* SK_PNMI_HRX_BROADCAST */ + {{XM_RXF_BC_OK, SK_TRUE}, {GM_RXF_BC_OK, SK_TRUE}}, + /* SK_PNMI_HRX_MULTICAST */ + {{XM_RXF_MC_OK, SK_TRUE}, {GM_RXF_MC_OK, SK_TRUE}}, + /* SK_PNMI_HRX_UNICAST */ + {{XM_RXF_UC_OK, SK_TRUE}, {GM_RXF_UC_OK, SK_TRUE}}, + /* SK_PNMI_HRX_PMACC */ + {{XM_RXF_MPAUSE, SK_TRUE}, {GM_RXF_MPAUSE, SK_TRUE}}, + /* SK_PNMI_HRX_MACC */ + {{XM_RXF_MCTRL, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_PMACC_ERR */ + {{XM_RXF_INV_MP, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_MACC_UNKWN */ + {{XM_RXF_INV_MOC, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_BURST */ + {{XM_RXE_BURST, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_MISSED */ + {{XM_RXE_FMISS, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_FRAMING */ + {{XM_RXF_FRA_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_UNDERSIZE */ + {{0, SK_FALSE},{GM_RXF_SHT, SK_TRUE}}, + /* SK_PNMI_HRX_OVERFLOW */ + {{XM_RXE_FIFO_OV, SK_TRUE}, {GM_RXE_FIFO_OV, SK_TRUE}}, + /* SK_PNMI_HRX_JABBER */ + {{XM_RXF_JAB_PKT, SK_TRUE}, {GM_RXF_JAB_PKT, SK_TRUE}}, + /* SK_PNMI_HRX_CARRIER */ + {{XM_RXE_CAR_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_IRLENGTH */ + {{XM_RXF_LEN_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_SYMBOL */ + {{XM_RXE_SYM_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_SHORTS */ + {{XM_RXE_SHT_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_RUNT */ + {{XM_RXE_RUNT, SK_TRUE}, {GM_RXE_FRAG, SK_TRUE}}, + /* SK_PNMI_HRX_TOO_LONG */ + {{XM_RXF_LNG_ERR, SK_TRUE}, {GM_RXF_LNG_ERR, SK_TRUE}}, + /* SK_PNMI_HRX_FCS */ + {{XM_RXF_FCS_ERR, SK_TRUE}, {GM_RXF_FCS_ERR, SK_TRUE}}, + /* SK_PNMI_HRX_CEXT */ + {{XM_RXF_CEX_ERR, SK_TRUE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_UTILUNDER */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_UTILOVER */ + {{0, SK_FALSE}, {0, SK_FALSE}}, + /* SK_PNMI_HRX_64 */ + {{XM_RXF_64B, SK_TRUE}, {GM_RXF_64B, SK_TRUE}}, + /* SK_PNMI_HRX_127 */ + {{XM_RXF_127B, SK_TRUE}, {GM_RXF_127B, SK_TRUE}}, + /* SK_PNMI_HRX_255 */ + {{XM_RXF_255B, SK_TRUE}, {GM_RXF_255B, SK_TRUE}}, + /* SK_PNMI_HRX_511 */ + {{XM_RXF_511B, SK_TRUE}, {GM_RXF_511B, SK_TRUE}}, + /* SK_PNMI_HRX_1023 */ + {{XM_RXF_1023B, SK_TRUE}, {GM_RXF_1023B, SK_TRUE}}, + /* SK_PNMI_HRX_MAX */ + {{XM_RXF_MAX_SZ, SK_TRUE}, {GM_RXF_1518B, SK_TRUE}}, + /* SK_PNMI_HRX_LONGFRAMES */ + {{0, SK_FALSE}, {GM_RXF_MAX_SZ, SK_TRUE}}, + /* SK_PNMI_HRX_RESERVED */ + {{0, SK_FALSE}, {0, SK_FALSE}} +}; + + +/***************************************************************************** + * + * Public functions + * + */ + +/***************************************************************************** + * + * SkPnmiInit - Init function of PNMI + * + * Description: + * SK_INIT_DATA: Initialises the data structures + * SK_INIT_IO: Resets the XMAC statistics, determines the device and + * connector type. + * SK_INIT_RUN: Starts a timer event for port switch per hour + * calculation. + * + * Returns: + * Always 0 + */ +int SkPnmiInit( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Level) /* Initialization level */ +{ + unsigned int PortMax; /* Number of ports */ + unsigned int PortIndex; /* Current port index in loop */ + SK_U16 Val16; /* Multiple purpose 16 bit variable */ + SK_U8 Val8; /* Mulitple purpose 8 bit variable */ + SK_EVPARA EventParam; /* Event struct for timer event */ + SK_GEPORT *pPrt; + SK_PNMI_VCT *pVctBackupData; + + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiInit: Called, level=%d\n", Level)); + + switch (Level) { + + case SK_INIT_DATA: + SK_MEMSET((char *)&pAC->Pnmi, 0, sizeof(pAC->Pnmi)); + pAC->Pnmi.TrapBufFree = SK_PNMI_TRAP_QUEUE_LEN; + pAC->Pnmi.StartUpTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC)); + pAC->Pnmi.RlmtChangeThreshold = SK_PNMI_DEF_RLMT_CHG_THRES; + for (PortIndex = 0; PortIndex < SK_MAX_MACS; PortIndex ++) { + + pAC->Pnmi.Port[PortIndex].ActiveFlag = SK_FALSE; + pAC->Pnmi.DualNetActiveFlag = SK_FALSE; + } + +#ifdef SK_PNMI_CHECK + if (SK_PNMI_MAX_IDX != SK_PNMI_CNT_NO) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR049, SK_PNMI_ERR049MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL, + ("CounterOffset struct size (%d) differs from" + "SK_PNMI_MAX_IDX (%d)\n", + SK_PNMI_CNT_NO, SK_PNMI_MAX_IDX)); + BRK; + } + + if (SK_PNMI_MAX_IDX != + (sizeof(StatAddr) / (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES))) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR050, SK_PNMI_ERR050MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL, + ("StatAddr table size (%d) differs from " + "SK_PNMI_MAX_IDX (%d)\n", + (sizeof(StatAddr) / + (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES)), + SK_PNMI_MAX_IDX)); + BRK; + } +#endif /* SK_PNMI_CHECK */ + break; + + case SK_INIT_IO: + /* + * Reset MAC counters + */ + PortMax = pAC->GIni.GIMacsFound; + + for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) { + + pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PortIndex); + } + + /* Initialize DSP variables for Vct() to 0xff => Never written! */ + for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) { + pPrt = &pAC->GIni.GP[PortIndex]; + pPrt->PCableLen =0xff; + pVctBackupData = &pAC->Pnmi.VctBackup[PortIndex]; + pVctBackupData->PCableLen = 0xff; + } + + /* + * Get pci bus speed + */ + SK_IN16(IoC, B0_CTST, &Val16); + if ((Val16 & CS_BUS_CLOCK) == 0) { + + pAC->Pnmi.PciBusSpeed = 33; + } + else { + pAC->Pnmi.PciBusSpeed = 66; + } + + /* + * Get pci bus width + */ + SK_IN16(IoC, B0_CTST, &Val16); + if ((Val16 & CS_BUS_SLOT_SZ) == 0) { + + pAC->Pnmi.PciBusWidth = 32; + } + else { + pAC->Pnmi.PciBusWidth = 64; + } + + /* + * Get chipset + */ + switch (pAC->GIni.GIChipId) { + case CHIP_ID_GENESIS: + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_XMAC; + break; + + case CHIP_ID_YUKON: + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON; + break; + + default: + break; + } + + /* + * Get PMD and DeviceType + */ + SK_IN8(IoC, B2_PMD_TYP, &Val8); + switch (Val8) { + case 'S': + pAC->Pnmi.PMD = 3; + if (pAC->GIni.GIMacsFound > 1) { + + pAC->Pnmi.DeviceType = 0x00020002; + } + else { + pAC->Pnmi.DeviceType = 0x00020001; + } + break; + + case 'L': + pAC->Pnmi.PMD = 2; + if (pAC->GIni.GIMacsFound > 1) { + + pAC->Pnmi.DeviceType = 0x00020004; + } + else { + pAC->Pnmi.DeviceType = 0x00020003; + } + break; + + case 'C': + pAC->Pnmi.PMD = 4; + if (pAC->GIni.GIMacsFound > 1) { + + pAC->Pnmi.DeviceType = 0x00020006; + } + else { + pAC->Pnmi.DeviceType = 0x00020005; + } + break; + + case 'T': + pAC->Pnmi.PMD = 5; + if (pAC->GIni.GIMacsFound > 1) { + + pAC->Pnmi.DeviceType = 0x00020008; + } + else { + pAC->Pnmi.DeviceType = 0x00020007; + } + break; + + default : + pAC->Pnmi.PMD = 1; + pAC->Pnmi.DeviceType = 0; + break; + } + + /* + * Get connector + */ + SK_IN8(IoC, B2_CONN_TYP, &Val8); + switch (Val8) { + case 'C': + pAC->Pnmi.Connector = 2; + break; + + case 'D': + pAC->Pnmi.Connector = 3; + break; + + case 'F': + pAC->Pnmi.Connector = 4; + break; + + case 'J': + pAC->Pnmi.Connector = 5; + break; + + case 'V': + pAC->Pnmi.Connector = 6; + break; + + default: + pAC->Pnmi.Connector = 1; + break; + } + break; + + case SK_INIT_RUN: + /* + * Start timer for RLMT change counter + */ + SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam)); + SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer, + 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER, + EventParam); + break; + + default: + break; /* Nothing todo */ + } + + return (0); +} + +/***************************************************************************** + * + * SkPnmiGetVar - Retrieves the value of a single OID + * + * Description: + * Calls a general sub-function for all this stuff. If the instance + * -1 is passed, the values of all instances are returned in an + * array of values. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed + * SK_PNMI_ERR_GENERAL A general severe internal error occured + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take + * the data. + * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +int SkPnmiGetVar( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 Id, /* Object ID that is to be processed */ +void *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiGetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n", + Id, *pLen, Instance, NetIndex)); + + return (PnmiVar(pAC, IoC, SK_PNMI_GET, Id, (char *)pBuf, pLen, + Instance, NetIndex)); +} + +/***************************************************************************** + * + * SkPnmiPreSetVar - Presets the value of a single OID + * + * Description: + * Calls a general sub-function for all this stuff. The preset does + * the same as a set, but returns just before finally setting the + * new value. This is usefull to check if a set might be successfull. + * If as instance a -1 is passed, an array of values is supposed and + * all instance of the OID will be set. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +int SkPnmiPreSetVar( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 Id, /* Object ID that is to be processed */ +void *pBuf, /* Buffer which stores the mgmt data to be set */ +unsigned int *pLen, /* Total length of mgmt data */ +SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiPreSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n", + Id, *pLen, Instance, NetIndex)); + + + return (PnmiVar(pAC, IoC, SK_PNMI_PRESET, Id, (char *)pBuf, pLen, + Instance, NetIndex)); +} + +/***************************************************************************** + * + * SkPnmiSetVar - Sets the value of a single OID + * + * Description: + * Calls a general sub-function for all this stuff. The preset does + * the same as a set, but returns just before finally setting the + * new value. This is usefull to check if a set might be successfull. + * If as instance a -1 is passed, an array of values is supposed and + * all instance of the OID will be set. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +int SkPnmiSetVar( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 Id, /* Object ID that is to be processed */ +void *pBuf, /* Buffer which stores the mgmt data to be set */ +unsigned int *pLen, /* Total length of mgmt data */ +SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n", + Id, *pLen, Instance, NetIndex)); + + return (PnmiVar(pAC, IoC, SK_PNMI_SET, Id, (char *)pBuf, pLen, + Instance, NetIndex)); +} + +/***************************************************************************** + * + * SkPnmiGetStruct - Retrieves the management database in SK_PNMI_STRUCT_DATA + * + * Description: + * Runs through the IdTable, queries the single OIDs and stores the + * returned data into the management database structure + * SK_PNMI_STRUCT_DATA. The offset of the OID in the structure + * is stored in the IdTable. The return value of the function will also + * be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the + * minimum size of SK_PNMI_MIN_STRUCT_SIZE. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed + * SK_PNMI_ERR_GENERAL A general severe internal error occured + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take + * the data. + * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist + */ +int SkPnmiGetStruct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +void *pBuf, /* Buffer which will store the retrieved data */ +unsigned int *pLen, /* Length of buffer */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + unsigned int TableIndex; + unsigned int DstOffset; + unsigned int InstanceNo; + unsigned int InstanceCnt; + SK_U32 Instance; + unsigned int TmpLen; + char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE]; + + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiGetStruct: Called, BufLen=%d, NetIndex=%d\n", + *pLen, NetIndex)); + + if (*pLen < SK_PNMI_STRUCT_SIZE) { + + if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) { + + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, + (SK_U32)(-1)); + } + + *pLen = SK_PNMI_STRUCT_SIZE; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Check NetIndex + */ + if (NetIndex >= pAC->Rlmt.NumNets) { + return (SK_PNMI_ERR_UNKNOWN_NET); + } + + /* Update statistic */ + SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On call"); + + if ((Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1)) != + SK_PNMI_ERR_OK) { + + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + + if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) { + + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + + if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) { + + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + + /* + * Increment semaphores to indicate that an update was + * already done + */ + pAC->Pnmi.MacUpdatedFlag ++; + pAC->Pnmi.RlmtUpdatedFlag ++; + pAC->Pnmi.SirqUpdatedFlag ++; + + /* Get vpd keys for instance calculation */ + Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen); + if (Ret != SK_PNMI_ERR_OK) { + + pAC->Pnmi.MacUpdatedFlag --; + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return"); + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (SK_PNMI_ERR_GENERAL); + } + + /* Retrieve values */ + SK_MEMSET((char *)pBuf, 0, SK_PNMI_STRUCT_SIZE); + for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) { + + InstanceNo = IdTable[TableIndex].InstanceNo; + for (InstanceCnt = 1; InstanceCnt <= InstanceNo; + InstanceCnt ++) { + + DstOffset = IdTable[TableIndex].Offset + + (InstanceCnt - 1) * + IdTable[TableIndex].StructSize; + + /* + * For the VPD the instance is not an index number + * but the key itself. Determin with the instance + * counter the VPD key to be used. + */ + if (IdTable[TableIndex].Id == OID_SKGE_VPD_KEY || + IdTable[TableIndex].Id == OID_SKGE_VPD_VALUE || + IdTable[TableIndex].Id == OID_SKGE_VPD_ACCESS || + IdTable[TableIndex].Id == OID_SKGE_VPD_ACTION) { + + SK_STRNCPY((char *)&Instance, KeyArr[InstanceCnt - 1], 4); + } + else { + Instance = (SK_U32)InstanceCnt; + } + + TmpLen = *pLen - DstOffset; + Ret = IdTable[TableIndex].Func(pAC, IoC, SK_PNMI_GET, + IdTable[TableIndex].Id, (char *)pBuf + + DstOffset, &TmpLen, Instance, TableIndex, NetIndex); + + /* + * An unknown instance error means that we reached + * the last instance of that variable. Proceed with + * the next OID in the table and ignore the return + * code. + */ + if (Ret == SK_PNMI_ERR_UNKNOWN_INST) { + + break; + } + + if (Ret != SK_PNMI_ERR_OK) { + + pAC->Pnmi.MacUpdatedFlag --; + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return"); + SK_PNMI_SET_STAT(pBuf, Ret, DstOffset); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + } + } + + pAC->Pnmi.MacUpdatedFlag --; + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + *pLen = SK_PNMI_STRUCT_SIZE; + SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return"); + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1)); + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * SkPnmiPreSetStruct - Presets the management database in SK_PNMI_STRUCT_DATA + * + * Description: + * Calls a general sub-function for all this set stuff. The preset does + * the same as a set, but returns just before finally setting the + * new value. This is usefull to check if a set might be successfull. + * The sub-function runs through the IdTable, checks which OIDs are able + * to set, and calls the handler function of the OID to perform the + * preset. The return value of the function will also be stored in + * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of + * SK_PNMI_MIN_STRUCT_SIZE. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + */ +int SkPnmiPreSetStruct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +void *pBuf, /* Buffer which contains the data to be set */ +unsigned int *pLen, /* Length of buffer */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiPreSetStruct: Called, BufLen=%d, NetIndex=%d\n", + *pLen, NetIndex)); + + return (PnmiStruct(pAC, IoC, SK_PNMI_PRESET, (char *)pBuf, + pLen, NetIndex)); +} + +/***************************************************************************** + * + * SkPnmiSetStruct - Sets the management database in SK_PNMI_STRUCT_DATA + * + * Description: + * Calls a general sub-function for all this set stuff. The return value + * of the function will also be stored in SK_PNMI_STRUCT_DATA if the + * passed buffer has the minimum size of SK_PNMI_MIN_STRUCT_SIZE. + * The sub-function runs through the IdTable, checks which OIDs are able + * to set, and calls the handler function of the OID to perform the + * set. The return value of the function will also be stored in + * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of + * SK_PNMI_MIN_STRUCT_SIZE. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + */ +int SkPnmiSetStruct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +void *pBuf, /* Buffer which contains the data to be set */ +unsigned int *pLen, /* Length of buffer */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiSetStruct: Called, BufLen=%d, NetIndex=%d\n", + *pLen, NetIndex)); + + return (PnmiStruct(pAC, IoC, SK_PNMI_SET, (char *)pBuf, + pLen, NetIndex)); +} + +/***************************************************************************** + * + * SkPnmiEvent - Event handler + * + * Description: + * Handles the following events: + * SK_PNMI_EVT_SIRQ_OVERFLOW When a hardware counter overflows an + * interrupt will be generated which is + * first handled by SIRQ which generates a + * this event. The event increments the + * upper 32 bit of the 64 bit counter. + * SK_PNMI_EVT_SEN_XXX The event is generated by the I2C module + * when a sensor reports a warning or + * error. The event will store a trap + * message in the trap buffer. + * SK_PNMI_EVT_CHG_EST_TIMER The timer event was initiated by this + * module and is used to calculate the + * port switches per hour. + * SK_PNMI_EVT_CLEAR_COUNTER The event clears all counters and + * timestamps. + * SK_PNMI_EVT_XMAC_RESET The event is generated by the driver + * before a hard reset of the XMAC is + * performed. All counters will be saved + * and added to the hardware counter + * values after reset to grant continuous + * counter values. + * SK_PNMI_EVT_RLMT_PORT_UP Generated by RLMT to notify that a port + * went logically up. A trap message will + * be stored to the trap buffer. + * SK_PNMI_EVT_RLMT_PORT_DOWN Generated by RLMT to notify that a port + * went logically down. A trap message will + * be stored to the trap buffer. + * SK_PNMI_EVT_RLMT_SEGMENTATION Generated by RLMT to notify that two + * spanning tree root bridges were + * detected. A trap message will be stored + * to the trap buffer. + * SK_PNMI_EVT_RLMT_ACTIVE_DOWN Notifies PNMI that an active port went + * down. PNMI will not further add the + * statistic values to the virtual port. + * SK_PNMI_EVT_RLMT_ACTIVE_UP Notifies PNMI that a port went up and + * is now an active port. PNMI will now + * add the statistic data of this port to + * the virtual port. + * SK_PNMI_EVT_RLMT_SET_NETS Notifies PNMI about the net mode. The first Parameter + * contains the number of nets. 1 means single net, 2 means + * dual net. The second Parameter is -1 + * + * Returns: + * Always 0 + */ +int SkPnmiEvent( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 Event, /* Event-Id */ +SK_EVPARA Param) /* Event dependent parameter */ +{ + unsigned int PhysPortIndex; + unsigned int MaxNetNumber; + int CounterIndex; + int Ret; + SK_U16 MacStatus; + SK_U64 OverflowStatus; + SK_U64 Mask; + int MacType; + SK_U64 Value; + SK_U32 Val32; + SK_U16 Register; + SK_EVPARA EventParam; + SK_U64 NewestValue; + SK_U64 OldestValue; + SK_U64 Delta; + SK_PNMI_ESTIMATE *pEst; + SK_U32 NetIndex; + SK_GEPORT *pPrt; + SK_PNMI_VCT *pVctBackupData; + SK_U32 RetCode; + int i; + SK_U32 CableLength; + + +#ifdef DEBUG + if (Event != SK_PNMI_EVT_XMAC_RESET) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: SkPnmiEvent: Called, Event=0x%x, Param=0x%x\n", + (unsigned int)Event, (unsigned int)Param.Para64)); + } +#endif + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On call"); + + MacType = pAC->GIni.GIMacType; + + switch (Event) { + + case SK_PNMI_EVT_SIRQ_OVERFLOW: + PhysPortIndex = (int)Param.Para32[0]; + MacStatus = (SK_U16)Param.Para32[1]; +#ifdef DEBUG + if (PhysPortIndex >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SIRQ_OVERFLOW parameter" + " wrong, PhysPortIndex=0x%x\n", + PhysPortIndex)); + return (0); + } +#endif + OverflowStatus = 0; + + /* + * Check which source caused an overflow interrupt. + */ + if ((pAC->GIni.GIFunc.pFnMacOverflow( + pAC, IoC, PhysPortIndex, MacStatus, &OverflowStatus) != 0) || + (OverflowStatus == 0)) { + + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); + return (0); + } + + /* + * Check the overflow status register and increment + * the upper dword of corresponding counter. + */ + for (CounterIndex = 0; CounterIndex < sizeof(Mask) * 8; + CounterIndex ++) { + + Mask = (SK_U64)1 << CounterIndex; + if ((OverflowStatus & Mask) == 0) { + + continue; + } + + switch (StatOvrflwBit[CounterIndex][MacType]) { + + case SK_PNMI_HTX_UTILUNDER: + case SK_PNMI_HTX_UTILOVER: + XM_IN16(IoC, PhysPortIndex, XM_TX_CMD, + &Register); + Register |= XM_TX_SAM_LINE; + XM_OUT16(IoC, PhysPortIndex, XM_TX_CMD, + Register); + break; + + case SK_PNMI_HRX_UTILUNDER: + case SK_PNMI_HRX_UTILOVER: + XM_IN16(IoC, PhysPortIndex, XM_RX_CMD, + &Register); + Register |= XM_RX_SAM_LINE; + XM_OUT16(IoC, PhysPortIndex, XM_RX_CMD, + Register); + break; + + case SK_PNMI_HTX_OCTETHIGH: + case SK_PNMI_HTX_OCTETLOW: + case SK_PNMI_HTX_RESERVED: + case SK_PNMI_HRX_OCTETHIGH: + case SK_PNMI_HRX_OCTETLOW: + case SK_PNMI_HRX_IRLENGTH: + case SK_PNMI_HRX_RESERVED: + + /* + * the following counters aren't be handled (id > 63) + */ + case SK_PNMI_HTX_SYNC: + case SK_PNMI_HTX_SYNC_OCTET: + break; + + case SK_PNMI_HRX_LONGFRAMES: + if (MacType == SK_MAC_GMAC) { + pAC->Pnmi.Port[PhysPortIndex]. + CounterHigh[CounterIndex] ++; + } + break; + + default: + pAC->Pnmi.Port[PhysPortIndex]. + CounterHigh[CounterIndex] ++; + } + } + break; + + case SK_PNMI_EVT_SEN_WAR_LOW: +#ifdef DEBUG + if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_LOW parameter wrong, SensorIndex=%d\n", + (unsigned int)Param.Para64)); + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate + * an event for user space applications with the + * SK_DRIVER_SENDEVENT macro. + */ + QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_LOW, + (unsigned int)Param.Para64); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + break; + + case SK_PNMI_EVT_SEN_WAR_UPP: +#ifdef DEBUG + if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR:SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_UPP parameter wrong, SensorIndex=%d\n", + (unsigned int)Param.Para64)); + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate + * an event for user space applications with the + * SK_DRIVER_SENDEVENT macro. + */ + QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_UPP, + (unsigned int)Param.Para64); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + break; + + case SK_PNMI_EVT_SEN_ERR_LOW: +#ifdef DEBUG + if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_LOW parameter wrong, SensorIndex=%d\n", + (unsigned int)Param.Para64)); + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate + * an event for user space applications with the + * SK_DRIVER_SENDEVENT macro. + */ + QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_LOW, + (unsigned int)Param.Para64); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + break; + + case SK_PNMI_EVT_SEN_ERR_UPP: +#ifdef DEBUG + if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n", + (unsigned int)Param.Para64)); + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate + * an event for user space applications with the + * SK_DRIVER_SENDEVENT macro. + */ + QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_UPP, + (unsigned int)Param.Para64); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + break; + + case SK_PNMI_EVT_CHG_EST_TIMER: + /* + * Calculate port switch average on a per hour basis + * Time interval for check : 28125 ms + * Number of values for average : 8 + * + * Be careful in changing these values, on change check + * - typedef of SK_PNMI_ESTIMATE (Size of EstValue + * array one less than value number) + * - Timer initilization SkTimerStart() in SkPnmiInit + * - Delta value below must be multiplicated with + * power of 2 + * + */ + pEst = &pAC->Pnmi.RlmtChangeEstimate; + CounterIndex = pEst->EstValueIndex + 1; + if (CounterIndex == 7) { + + CounterIndex = 0; + } + pEst->EstValueIndex = CounterIndex; + + NewestValue = pAC->Pnmi.RlmtChangeCts; + OldestValue = pEst->EstValue[CounterIndex]; + pEst->EstValue[CounterIndex] = NewestValue; + + /* + * Calculate average. Delta stores the number of + * port switches per 28125 * 8 = 225000 ms + */ + if (NewestValue >= OldestValue) { + + Delta = NewestValue - OldestValue; + } + else { + /* Overflow situation */ + Delta = (SK_U64)(0 - OldestValue) + NewestValue; + } + + /* + * Extrapolate delta to port switches per hour. + * Estimate = Delta * (3600000 / 225000) + * = Delta * 16 + * = Delta << 4 + */ + pAC->Pnmi.RlmtChangeEstimate.Estimate = Delta << 4; + + /* + * Check if threshold is exceeded. If the threshold is + * permanently exceeded every 28125 ms an event will be + * generated to remind the user of this condition. + */ + if ((pAC->Pnmi.RlmtChangeThreshold != 0) && + (pAC->Pnmi.RlmtChangeEstimate.Estimate >= + pAC->Pnmi.RlmtChangeThreshold)) { + + QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_CHANGE_THRES); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + } + + SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam)); + SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer, + 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER, + EventParam); + break; + + case SK_PNMI_EVT_CLEAR_COUNTER: + /* + * Param.Para32[0] contains the NetIndex (0 ..1). + * Param.Para32[1] is reserved, contains -1. + */ + NetIndex = (SK_U32)Param.Para32[0]; + +#ifdef DEBUG + if (NetIndex >= pAC->Rlmt.NumNets) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_CLEAR_COUNTER parameter wrong, NetIndex=%d\n", + NetIndex)); + + return (0); + } +#endif + + /* + * Set all counters and timestamps to zero + */ + ResetCounter(pAC, IoC, NetIndex); /* the according NetIndex is required + as a Parameter of the Event */ + break; + + case SK_PNMI_EVT_XMAC_RESET: + /* + * To grant continuous counter values store the current + * XMAC statistic values to the entries 1..n of the + * CounterOffset array. XMAC Errata #2 + */ +#ifdef DEBUG + if ((unsigned int)Param.Para64 >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_XMAC_RESET parameter wrong, PhysPortIndex=%d\n", + (unsigned int)Param.Para64)); + return (0); + } +#endif + PhysPortIndex = (unsigned int)Param.Para64; + + /* + * Update XMAC statistic to get fresh values + */ + Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); + if (Ret != SK_PNMI_ERR_OK) { + + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); + return (0); + } + /* + * Increment semaphore to indicate that an update was + * already done + */ + pAC->Pnmi.MacUpdatedFlag ++; + + for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX; + CounterIndex ++) { + + if (!StatAddr[CounterIndex][MacType].GetOffset) { + + continue; + } + + pAC->Pnmi.Port[PhysPortIndex]. + CounterOffset[CounterIndex] = GetPhysStatVal( + pAC, IoC, PhysPortIndex, CounterIndex); + pAC->Pnmi.Port[PhysPortIndex]. + CounterHigh[CounterIndex] = 0; + } + + pAC->Pnmi.MacUpdatedFlag --; + break; + + case SK_PNMI_EVT_RLMT_PORT_UP: + PhysPortIndex = (unsigned int)Param.Para32[0]; +#ifdef DEBUG + if (PhysPortIndex >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_UP parameter" + " wrong, PhysPortIndex=%d\n", PhysPortIndex)); + + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate an event for + * user space applications with the SK_DRIVER_SENDEVENT macro. + */ + QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_UP, PhysPortIndex); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + + /* Bugfix for XMAC errata (#10620)*/ + if (pAC->GIni.GIMacType == SK_MAC_XMAC){ + + /* Add incremental difference to offset (#10620)*/ + (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex, + XM_RXE_SHT_ERR, &Val32); + + Value = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex]. + CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32); + pAC->Pnmi.Port[PhysPortIndex].CounterOffset[SK_PNMI_HRX_SHORTS] += + Value - pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark; + } + + /* Tell VctStatus() that a link was up meanwhile. */ + pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_LINK; + break; + + case SK_PNMI_EVT_RLMT_PORT_DOWN: + PhysPortIndex = (unsigned int)Param.Para32[0]; + +#ifdef DEBUG + if (PhysPortIndex >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_DOWN parameter" + " wrong, PhysPortIndex=%d\n", PhysPortIndex)); + + return (0); + } +#endif + /* + * Store a trap message in the trap buffer and generate an event for + * user space applications with the SK_DRIVER_SENDEVENT macro. + */ + QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN, PhysPortIndex); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + + /* Bugfix #10620 - get zero level for incremental difference */ + if ((pAC->GIni.GIMacType == SK_MAC_XMAC)) { + + (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex, + XM_RXE_SHT_ERR, &Val32); + pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark = + (((SK_U64)pAC->Pnmi.Port[PhysPortIndex]. + CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32); + } + break; + + case SK_PNMI_EVT_RLMT_ACTIVE_DOWN: + PhysPortIndex = (unsigned int)Param.Para32[0]; + NetIndex = (SK_U32)Param.Para32[1]; + +#ifdef DEBUG + if (PhysPortIndex >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, PhysPort=%d\n", + PhysPortIndex)); + } + + if (NetIndex >= pAC->Rlmt.NumNets) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, NetIndex=%d\n", + NetIndex)); + } +#endif + /* + * For now, ignore event if NetIndex != 0. + */ + if (Param.Para32[1] != 0) { + + return (0); + } + + /* + * Nothing to do if port is already inactive + */ + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + return (0); + } + + /* + * Update statistic counters to calculate new offset for the virtual + * port and increment semaphore to indicate that an update was already + * done. + */ + if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) != + SK_PNMI_ERR_OK) { + + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); + return (0); + } + pAC->Pnmi.MacUpdatedFlag ++; + + /* + * Calculate new counter offset for virtual port to grant continous + * counting on port switches. The virtual port consists of all currently + * active ports. The port down event indicates that a port is removed + * from the virtual port. Therefore add the counter value of the removed + * port to the CounterOffset for the virtual port to grant the same + * counter value. + */ + for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX; + CounterIndex ++) { + + if (!StatAddr[CounterIndex][MacType].GetOffset) { + + continue; + } + + Value = GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex); + + pAC->Pnmi.VirtualCounterOffset[CounterIndex] += Value; + } + + /* + * Set port to inactive + */ + pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_FALSE; + + pAC->Pnmi.MacUpdatedFlag --; + break; + + case SK_PNMI_EVT_RLMT_ACTIVE_UP: + PhysPortIndex = (unsigned int)Param.Para32[0]; + NetIndex = (SK_U32)Param.Para32[1]; + +#ifdef DEBUG + if (PhysPortIndex >= SK_MAX_MACS) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, PhysPort=%d\n", + PhysPortIndex)); + } + + if (NetIndex >= pAC->Rlmt.NumNets) { + + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL, + ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, NetIndex=%d\n", + NetIndex)); + } +#endif + /* + * For now, ignore event if NetIndex != 0. + */ + if (Param.Para32[1] != 0) { + + return (0); + } + + /* + * Nothing to do if port is already active + */ + if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + return (0); + } + + /* + * Statistic maintenance + */ + pAC->Pnmi.RlmtChangeCts ++; + pAC->Pnmi.RlmtChangeTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC)); + + /* + * Store a trap message in the trap buffer and generate an event for + * user space applications with the SK_DRIVER_SENDEVENT macro. + */ + QueueRlmtNewMacTrap(pAC, PhysPortIndex); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + + /* + * Update statistic counters to calculate new offset for the virtual + * port and increment semaphore to indicate that an update was + * already done. + */ + if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) != + SK_PNMI_ERR_OK) { + + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); + return (0); + } + pAC->Pnmi.MacUpdatedFlag ++; + + /* + * Calculate new counter offset for virtual port to grant continous + * counting on port switches. A new port is added to the virtual port. + * Therefore substract the counter value of the new port from the + * CounterOffset for the virtual port to grant the same value. + */ + for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX; + CounterIndex ++) { + + if (!StatAddr[CounterIndex][MacType].GetOffset) { + + continue; + } + + Value = GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex); + + pAC->Pnmi.VirtualCounterOffset[CounterIndex] -= Value; + } + + /* + * Set port to active + */ + pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_TRUE; + + pAC->Pnmi.MacUpdatedFlag --; + break; + + case SK_PNMI_EVT_RLMT_SEGMENTATION: + /* + * Para.Para32[0] contains the NetIndex. + */ + + /* + * Store a trap message in the trap buffer and generate an event for + * user space applications with the SK_DRIVER_SENDEVENT macro. + */ + QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_SEGMENTATION); + (void)SK_DRIVER_SENDEVENT(pAC, IoC); + break; + + case SK_PNMI_EVT_RLMT_SET_NETS: + /* + * Param.Para32[0] contains the number of Nets. + * Param.Para32[1] is reserved, contains -1. + */ + /* + * Check number of nets + */ + MaxNetNumber = pAC->GIni.GIMacsFound; + if (((unsigned int)Param.Para32[0] < 1) + || ((unsigned int)Param.Para32[0] > MaxNetNumber)) { + return (SK_PNMI_ERR_UNKNOWN_NET); + } + + if ((unsigned int)Param.Para32[0] == 1) { /* single net mode */ + pAC->Pnmi.DualNetActiveFlag = SK_FALSE; + } + else { /* dual net mode */ + pAC->Pnmi.DualNetActiveFlag = SK_TRUE; + } + break; + + case SK_PNMI_EVT_VCT_RESET: + PhysPortIndex = Param.Para32[0]; + pPrt = &pAC->GIni.GP[PhysPortIndex]; + pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex]; + + if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) { + RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE); + if (RetCode == 2) { + /* + * VCT test is still running. + * Start VCT timer counter again. + */ + SK_MEMSET((char *) &Param, 0, sizeof(Param)); + Param.Para32[0] = PhysPortIndex; + Param.Para32[1] = -1; + SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer, + 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param); + break; + } + pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING; + pAC->Pnmi.VctStatus[PhysPortIndex] |= + (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE); + + /* Copy results for later use to PNMI struct. */ + for (i = 0; i < 4; i++) { + if (pPrt->PMdiPairLen[i] > 35) { + CableLength = 1000 * (((175 * pPrt->PMdiPairLen[i]) / 210) - 28); + } + else { + CableLength = 0; + } + pVctBackupData->PMdiPairLen[i] = CableLength; + pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i]; + } + + Param.Para32[0] = PhysPortIndex; + Param.Para32[1] = -1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Param); + SkEventDispatcher(pAC, IoC); + } + + break; + + default: + break; + } + + SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return"); + return (0); +} + + +/****************************************************************************** + * + * Private functions + * + */ + +/***************************************************************************** + * + * PnmiVar - Gets, presets, and sets single OIDs + * + * Description: + * Looks up the requested OID, calls the corresponding handler + * function, and passes the parameters with the get, preset, or + * set command. The function is called by SkGePnmiGetVar, + * SkGePnmiPreSetVar, or SkGePnmiSetVar. + * + * Returns: + * SK_PNMI_ERR_XXX. For details have a look to the description of the + * calling functions. + * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist + */ +PNMI_STATIC int PnmiVar( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer which stores the mgmt data to be set */ +unsigned int *pLen, /* Total length of mgmt data */ +SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int TableIndex; + int Ret; + + + if ((TableIndex = LookupId(Id)) == (unsigned int)(-1)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_OID); + } + + /* + * Check NetIndex + */ + if (NetIndex >= pAC->Rlmt.NumNets) { + return (SK_PNMI_ERR_UNKNOWN_NET); + } + + SK_PNMI_CHECKFLAGS("PnmiVar: On call"); + + Ret = IdTable[TableIndex].Func(pAC, IoC, Action, Id, pBuf, pLen, + Instance, TableIndex, NetIndex); + + SK_PNMI_CHECKFLAGS("PnmiVar: On return"); + + return (Ret); +} + +/***************************************************************************** + * + * PnmiStruct - Presets and Sets data in structure SK_PNMI_STRUCT_DATA + * + * Description: + * The return value of the function will also be stored in + * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of + * SK_PNMI_MIN_STRUCT_SIZE. The sub-function runs through the IdTable, + * checks which OIDs are able to set, and calls the handler function of + * the OID to perform the set. The return value of the function will + * also be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the + * minimum size of SK_PNMI_MIN_STRUCT_SIZE. The function is called + * by SkGePnmiPreSetStruct and SkGePnmiSetStruct. + * + * Returns: + * SK_PNMI_ERR_XXX. The codes are described in the calling functions. + * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist + */ +PNMI_STATIC int PnmiStruct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Set action to be performed */ +char *pBuf, /* Buffer which contains the data to be set */ +unsigned int *pLen, /* Length of buffer */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + unsigned int TableIndex; + unsigned int DstOffset; + unsigned int Len; + unsigned int InstanceNo; + unsigned int InstanceCnt; + SK_U32 Instance; + SK_U32 Id; + + + /* Check if the passed buffer has the right size */ + if (*pLen < SK_PNMI_STRUCT_SIZE) { + + /* Check if we can return the error within the buffer */ + if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) { + + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, + (SK_U32)(-1)); + } + + *pLen = SK_PNMI_STRUCT_SIZE; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Check NetIndex + */ + if (NetIndex >= pAC->Rlmt.NumNets) { + return (SK_PNMI_ERR_UNKNOWN_NET); + } + + SK_PNMI_CHECKFLAGS("PnmiStruct: On call"); + + /* + * Update the values of RLMT and SIRQ and increment semaphores to + * indicate that an update was already done. + */ + if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) { + + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + + if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) { + + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1)); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (Ret); + } + + pAC->Pnmi.RlmtUpdatedFlag ++; + pAC->Pnmi.SirqUpdatedFlag ++; + + /* Preset/Set values */ + for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) { + + if ((IdTable[TableIndex].Access != SK_PNMI_RW) && + (IdTable[TableIndex].Access != SK_PNMI_WO)) { + + continue; + } + + InstanceNo = IdTable[TableIndex].InstanceNo; + Id = IdTable[TableIndex].Id; + + for (InstanceCnt = 1; InstanceCnt <= InstanceNo; + InstanceCnt ++) { + + DstOffset = IdTable[TableIndex].Offset + + (InstanceCnt - 1) * + IdTable[TableIndex].StructSize; + + /* + * Because VPD multiple instance variables are + * not setable we do not need to evaluate VPD + * instances. Have a look to VPD instance + * calculation in SkPnmiGetStruct(). + */ + Instance = (SK_U32)InstanceCnt; + + /* + * Evaluate needed buffer length + */ + Len = 0; + Ret = IdTable[TableIndex].Func(pAC, IoC, + SK_PNMI_GET, IdTable[TableIndex].Id, + NULL, &Len, Instance, TableIndex, NetIndex); + + if (Ret == SK_PNMI_ERR_UNKNOWN_INST) { + + break; + } + if (Ret != SK_PNMI_ERR_TOO_SHORT) { + + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + SK_PNMI_CHECKFLAGS("PnmiStruct: On return"); + SK_PNMI_SET_STAT(pBuf, + SK_PNMI_ERR_GENERAL, DstOffset); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (SK_PNMI_ERR_GENERAL); + } + if (Id == OID_SKGE_VPD_ACTION) { + + switch (*(pBuf + DstOffset)) { + + case SK_PNMI_VPD_CREATE: + Len = 3 + *(pBuf + DstOffset + 3); + break; + + case SK_PNMI_VPD_DELETE: + Len = 3; + break; + + default: + Len = 1; + break; + } + } + + /* Call the OID handler function */ + Ret = IdTable[TableIndex].Func(pAC, IoC, Action, + IdTable[TableIndex].Id, pBuf + DstOffset, + &Len, Instance, TableIndex, NetIndex); + + if (Ret != SK_PNMI_ERR_OK) { + + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + SK_PNMI_CHECKFLAGS("PnmiStruct: On return"); + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE, + DstOffset); + *pLen = SK_PNMI_MIN_STRUCT_SIZE; + return (SK_PNMI_ERR_BAD_VALUE); + } + } + } + + pAC->Pnmi.RlmtUpdatedFlag --; + pAC->Pnmi.SirqUpdatedFlag --; + + SK_PNMI_CHECKFLAGS("PnmiStruct: On return"); + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1)); + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * LookupId - Lookup an OID in the IdTable + * + * Description: + * Scans the IdTable to find the table entry of an OID. + * + * Returns: + * The table index or -1 if not found. + */ +PNMI_STATIC int LookupId( +SK_U32 Id) /* Object identifier to be searched */ +{ + int i; + + for (i = 0; i < ID_TABLE_SIZE; i++) { + + if (IdTable[i].Id == Id) { + + return i; + } + } + + return (-1); +} + +/***************************************************************************** + * + * OidStruct - Handler of OID_SKGE_ALL_DATA + * + * Description: + * This OID performs a Get/Preset/SetStruct call and returns all data + * in a SK_PNMI_STRUCT_DATA structure. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int OidStruct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + if (Id != OID_SKGE_ALL_DATA) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003, + SK_PNMI_ERR003MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Check instance. We only handle single instance variables + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + switch (Action) { + + case SK_PNMI_GET: + return (SkPnmiGetStruct(pAC, IoC, pBuf, pLen, NetIndex)); + + case SK_PNMI_PRESET: + return (SkPnmiPreSetStruct(pAC, IoC, pBuf, pLen, NetIndex)); + + case SK_PNMI_SET: + return (SkPnmiSetStruct(pAC, IoC, pBuf, pLen, NetIndex)); + } + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR004, SK_PNMI_ERR004MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); +} + +/***************************************************************************** + * + * Perform - OID handler of OID_SKGE_ACTION + * + * Description: + * None. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Perform( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + SK_U32 ActionOp; + + + /* + * Check instance. We only handle single instance variables + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* Check if a get should be performed */ + if (Action == SK_PNMI_GET) { + + /* A get is easy. We always return the same value */ + ActionOp = (SK_U32)SK_PNMI_ACT_IDLE; + SK_PNMI_STORE_U32(pBuf, ActionOp); + *pLen = sizeof(SK_U32); + + return (SK_PNMI_ERR_OK); + } + + /* Continue with PRESET/SET action */ + if (*pLen > sizeof(SK_U32)) { + + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* Check if the command is a known one */ + SK_PNMI_READ_U32(pBuf, ActionOp); + if (*pLen > sizeof(SK_U32) || + (ActionOp != SK_PNMI_ACT_IDLE && + ActionOp != SK_PNMI_ACT_RESET && + ActionOp != SK_PNMI_ACT_SELFTEST && + ActionOp != SK_PNMI_ACT_RESETCNT)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* A preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + switch (ActionOp) { + + case SK_PNMI_ACT_IDLE: + /* Nothing to do */ + break; + + case SK_PNMI_ACT_RESET: + /* + * Perform a driver reset or something that comes near + * to this. + */ + Ret = SK_DRIVER_RESET(pAC, IoC); + if (Ret != 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005, + SK_PNMI_ERR005MSG); + + return (SK_PNMI_ERR_GENERAL); + } + break; + + case SK_PNMI_ACT_SELFTEST: + /* + * Perform a driver selftest or something similar to this. + * Currently this feature is not used and will probably + * implemented in another way. + */ + Ret = SK_DRIVER_SELFTEST(pAC, IoC); + pAC->Pnmi.TestResult = Ret; + break; + + case SK_PNMI_ACT_RESETCNT: + /* Set all counters and timestamps to zero */ + ResetCounter(pAC, IoC, NetIndex); + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006, + SK_PNMI_ERR006MSG); + + return (SK_PNMI_ERR_GENERAL); + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * Mac8023Stat - OID handler of OID_GEN_XXX and OID_802_3_XXX + * + * Description: + * Retrieves the statistic values of the virtual port (logical + * index 0). Only special OIDs of NDIS are handled which consist + * of a 32 bit instead of a 64 bit value. The OIDs are public + * because perhaps some other platform can use them too. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Mac8023Stat( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + SK_U64 StatVal; + SK_U32 StatVal32; + SK_BOOL Is64BitReq = SK_FALSE; + + /* + * Only the active Mac is returned + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* + * Check action type + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Check length + */ + switch (Id) { + + case OID_802_3_PERMANENT_ADDRESS: + case OID_802_3_CURRENT_ADDRESS: + if (*pLen < sizeof(SK_MAC_ADDR)) { + + *pLen = sizeof(SK_MAC_ADDR); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: +#ifndef SK_NDIS_64BIT_CTR + if (*pLen < sizeof(SK_U32)) { + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + +#else /* SK_NDIS_64BIT_CTR */ + + /* + * for compatibility, at least 32bit are required for oid + */ + if (*pLen < sizeof(SK_U32)) { + /* + * but indicate handling for 64bit values, + * if insufficient space is provided + */ + *pLen = sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + + Is64BitReq = (*pLen < sizeof(SK_U64)) ? SK_FALSE : SK_TRUE; +#endif /* SK_NDIS_64BIT_CTR */ + break; + } + + /* + * Update all statistics, because we retrieve virtual MAC, which + * consists of multiple physical statistics and increment semaphore + * to indicate that an update was already done. + */ + Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); + if ( Ret != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.MacUpdatedFlag ++; + + /* + * Get value (MAC Index 0 identifies the virtual MAC) + */ + switch (Id) { + + case OID_802_3_PERMANENT_ADDRESS: + CopyMac(pBuf, &pAC->Addr.Net[NetIndex].PermanentMacAddress); + *pLen = sizeof(SK_MAC_ADDR); + break; + + case OID_802_3_CURRENT_ADDRESS: + CopyMac(pBuf, &pAC->Addr.Net[NetIndex].CurrentMacAddress); + *pLen = sizeof(SK_MAC_ADDR); + break; + + default: + StatVal = GetStatVal(pAC, IoC, 0, IdTable[TableIndex].Param, NetIndex); + + /* + * by default 32bit values are evaluated + */ + if (!Is64BitReq) { + StatVal32 = (SK_U32)StatVal; + SK_PNMI_STORE_U32(pBuf, StatVal32); + *pLen = sizeof(SK_U32); + } + else { + SK_PNMI_STORE_U64(pBuf, StatVal); + *pLen = sizeof(SK_U64); + } + break; + } + + pAC->Pnmi.MacUpdatedFlag --; + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * MacPrivateStat - OID handler function of OID_SKGE_STAT_XXX + * + * Description: + * Retrieves the XMAC statistic data. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int MacPrivateStat( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int LogPortMax; + unsigned int LogPortIndex; + unsigned int PhysPortMax; + unsigned int Limit; + unsigned int Offset; + int Ret; + SK_U64 StatVal; + + + /* + * Calculate instance if wished. MAC index 0 is the virtual + * MAC. + */ + PhysPortMax = pAC->GIni.GIMacsFound; + LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); + + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + LogPortMax--; + } + + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */ + /* Check instance range */ + if ((Instance < 1) || (Instance > LogPortMax)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance); + Limit = LogPortIndex + 1; + } + + else { /* Instance == (SK_U32)(-1), get all Instances of that OID */ + + LogPortIndex = 0; + Limit = LogPortMax; + } + + + /* + * Check action + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Check length + */ + if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U64)) { + + *pLen = (Limit - LogPortIndex) * sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Update XMAC statistic and increment semaphore to indicate that + * an update was already done. + */ + Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); + if (Ret != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.MacUpdatedFlag ++; + + /* + * Get value + */ + Offset = 0; + for (; LogPortIndex < Limit; LogPortIndex ++) { + + switch (Id) { + +/* XXX not yet implemented due to XMAC problems + case OID_SKGE_STAT_TX_UTIL: + return (SK_PNMI_ERR_GENERAL); +*/ +/* XXX not yet implemented due to XMAC problems + case OID_SKGE_STAT_RX_UTIL: + return (SK_PNMI_ERR_GENERAL); +*/ + case OID_SKGE_STAT_RX: + case OID_SKGE_STAT_TX: + switch (pAC->GIni.GIMacType) { + case SK_MAC_XMAC: + StatVal = GetStatVal(pAC, IoC, LogPortIndex, + IdTable[TableIndex].Param, NetIndex); + break; + + case SK_MAC_GMAC: + if (Id == OID_SKGE_STAT_TX) { + + StatVal = + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HTX_BROADCAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HTX_MULTICAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HTX_UNICAST, NetIndex); + } + else { + StatVal = + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_BROADCAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_MULTICAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_UNICAST, NetIndex) + + GetStatVal(pAC, IoC, LogPortIndex, + SK_PNMI_HRX_UNDERSIZE, NetIndex); + } + break; + + default: + StatVal = 0; + break; + } + + SK_PNMI_STORE_U64(pBuf + Offset, StatVal); + break; + + default: + StatVal = GetStatVal(pAC, IoC, LogPortIndex, + IdTable[TableIndex].Param, NetIndex); + SK_PNMI_STORE_U64(pBuf + Offset, StatVal); + break; + } + + Offset += sizeof(SK_U64); + } + *pLen = Offset; + + pAC->Pnmi.MacUpdatedFlag --; + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * Addr - OID handler function of OID_SKGE_PHYS_CUR_ADDR and _FAC_ADDR + * + * Description: + * Get/Presets/Sets the current and factory MAC address. The MAC + * address of the virtual port, which is reported to the OS, may + * not be changed, but the physical ones. A set to the virtual port + * will be ignored. No error should be reported because otherwise + * a multiple instance set (-1) would always fail. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Addr( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + unsigned int LogPortMax; + unsigned int PhysPortMax; + unsigned int LogPortIndex; + unsigned int PhysPortIndex; + unsigned int Limit; + unsigned int Offset = 0; + + /* + * Calculate instance if wished. MAC index 0 is the virtual + * MAC. + */ + PhysPortMax = pAC->GIni.GIMacsFound; + LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); + + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + LogPortMax--; + } + + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */ + /* Check instance range */ + if ((Instance < 1) || (Instance > LogPortMax)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance); + Limit = LogPortIndex + 1; + } + + else { /* Instance == (SK_U32)(-1), get all Instances of that OID */ + + LogPortIndex = 0; + Limit = LogPortMax; + } + + /* + * Perform Action + */ + if (Action == SK_PNMI_GET) { + + /* + * Check length + */ + if (*pLen < (Limit - LogPortIndex) * 6) { + + *pLen = (Limit - LogPortIndex) * 6; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Get value + */ + for (; LogPortIndex < Limit; LogPortIndex ++) { + + switch (Id) { + + case OID_SKGE_PHYS_CUR_ADDR: + if (LogPortIndex == 0) { + CopyMac(pBuf + Offset, &pAC->Addr.Net[NetIndex].CurrentMacAddress); + } + else { + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex); + + CopyMac(pBuf + Offset, + &pAC->Addr.Port[PhysPortIndex].CurrentMacAddress); + } + Offset += 6; + break; + + case OID_SKGE_PHYS_FAC_ADDR: + if (LogPortIndex == 0) { + CopyMac(pBuf + Offset, + &pAC->Addr.Net[NetIndex].PermanentMacAddress); + } + else { + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + CopyMac(pBuf + Offset, + &pAC->Addr.Port[PhysPortIndex].PermanentMacAddress); + } + Offset += 6; + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008, + SK_PNMI_ERR008MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + + *pLen = Offset; + } + else { + /* + * The logical MAC address may not be changed only + * the physical ones + */ + if (Id == OID_SKGE_PHYS_FAC_ADDR) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Only the current address may be changed + */ + if (Id != OID_SKGE_PHYS_CUR_ADDR) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009, + SK_PNMI_ERR009MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Check length + */ + if (*pLen < (Limit - LogPortIndex) * 6) { + + *pLen = (Limit - LogPortIndex) * 6; + return (SK_PNMI_ERR_TOO_SHORT); + } + if (*pLen > (Limit - LogPortIndex) * 6) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* + * Check Action + */ + if (Action == SK_PNMI_PRESET) { + + *pLen = 0; + return (SK_PNMI_ERR_OK); + } + + /* + * Set OID_SKGE_MAC_CUR_ADDR + */ + for (; LogPortIndex < Limit; LogPortIndex ++, Offset += 6) { + + /* + * A set to virtual port and set of broadcast + * address will be ignored + */ + if (LogPortIndex == 0 || SK_MEMCMP(pBuf + Offset, + "\xff\xff\xff\xff\xff\xff", 6) == 0) { + + continue; + } + + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, + LogPortIndex); + + Ret = SkAddrOverride(pAC, IoC, PhysPortIndex, + (SK_MAC_ADDR *)(pBuf + Offset), + (LogPortIndex == 0 ? SK_ADDR_VIRTUAL_ADDRESS : + SK_ADDR_PHYSICAL_ADDRESS)); + if (Ret != SK_ADDR_OVERRIDE_SUCCESS) { + + return (SK_PNMI_ERR_GENERAL); + } + } + *pLen = Offset; + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * CsumStat - OID handler function of OID_SKGE_CHKSM_XXX + * + * Description: + * Retrieves the statistic values of the CSUM module. The CSUM data + * structure must be available in the SK_AC even if the CSUM module + * is not included, because PNMI reads the statistic data from the + * CSUM part of SK_AC directly. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int CsumStat( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int Index; + unsigned int Limit; + unsigned int Offset = 0; + SK_U64 StatVal; + + + /* + * Calculate instance if wished + */ + if (Instance != (SK_U32)(-1)) { + + if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + Index = (unsigned int)Instance - 1; + Limit = Index + 1; + } + else { + Index = 0; + Limit = SKCS_NUM_PROTOCOLS; + } + + /* + * Check action + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Check length + */ + if (*pLen < (Limit - Index) * sizeof(SK_U64)) { + + *pLen = (Limit - Index) * sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Get value + */ + for (; Index < Limit; Index ++) { + + switch (Id) { + + case OID_SKGE_CHKSM_RX_OK_CTS: + StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxOkCts; + break; + + case OID_SKGE_CHKSM_RX_UNABLE_CTS: + StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxUnableCts; + break; + + case OID_SKGE_CHKSM_RX_ERR_CTS: + StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxErrCts; + break; + + case OID_SKGE_CHKSM_TX_OK_CTS: + StatVal = pAC->Csum.ProtoStats[NetIndex][Index].TxOkCts; + break; + + case OID_SKGE_CHKSM_TX_UNABLE_CTS: + StatVal = pAC->Csum.ProtoStats[NetIndex][Index].TxUnableCts; + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010, + SK_PNMI_ERR010MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + SK_PNMI_STORE_U64(pBuf + Offset, StatVal); + Offset += sizeof(SK_U64); + } + + /* + * Store used buffer space + */ + *pLen = Offset; + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * SensorStat - OID handler function of OID_SKGE_SENSOR_XXX + * + * Description: + * Retrieves the statistic values of the I2C module, which handles + * the temperature and voltage sensors. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int SensorStat( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int i; + unsigned int Index; + unsigned int Limit; + unsigned int Offset; + unsigned int Len; + SK_U32 Val32; + SK_U64 Val64; + + + /* + * Calculate instance if wished + */ + if ((Instance != (SK_U32)(-1))) { + + if ((Instance < 1) || (Instance > (SK_U32)pAC->I2c.MaxSens)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + Index = (unsigned int)Instance -1; + Limit = (unsigned int)Instance; + } + else { + Index = 0; + Limit = (unsigned int) pAC->I2c.MaxSens; + } + + /* + * Check action + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Check length + */ + switch (Id) { + + case OID_SKGE_SENSOR_VALUE: + case OID_SKGE_SENSOR_WAR_THRES_LOW: + case OID_SKGE_SENSOR_WAR_THRES_UPP: + case OID_SKGE_SENSOR_ERR_THRES_LOW: + case OID_SKGE_SENSOR_ERR_THRES_UPP: + if (*pLen < (Limit - Index) * sizeof(SK_U32)) { + + *pLen = (Limit - Index) * sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_SENSOR_DESCR: + for (Offset = 0, i = Index; i < Limit; i ++) { + + Len = (unsigned int) + SK_STRLEN(pAC->I2c.SenTable[i].SenDesc) + 1; + if (Len >= SK_PNMI_STRINGLEN2) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR011, + SK_PNMI_ERR011MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + Offset += Len; + } + if (*pLen < Offset) { + + *pLen = Offset; + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_SENSOR_INDEX: + case OID_SKGE_SENSOR_TYPE: + case OID_SKGE_SENSOR_STATUS: + if (*pLen < Limit - Index) { + + *pLen = Limit - Index; + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_SENSOR_WAR_CTS: + case OID_SKGE_SENSOR_WAR_TIME: + case OID_SKGE_SENSOR_ERR_CTS: + case OID_SKGE_SENSOR_ERR_TIME: + if (*pLen < (Limit - Index) * sizeof(SK_U64)) { + + *pLen = (Limit - Index) * sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012, + SK_PNMI_ERR012MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + + } + + /* + * Get value + */ + for (Offset = 0; Index < Limit; Index ++) { + + switch (Id) { + + case OID_SKGE_SENSOR_INDEX: + *(pBuf + Offset) = (char)Index; + Offset += sizeof(char); + break; + + case OID_SKGE_SENSOR_DESCR: + Len = SK_STRLEN(pAC->I2c.SenTable[Index].SenDesc); + SK_MEMCPY(pBuf + Offset + 1, + pAC->I2c.SenTable[Index].SenDesc, Len); + *(pBuf + Offset) = (char)Len; + Offset += Len + 1; + break; + + case OID_SKGE_SENSOR_TYPE: + *(pBuf + Offset) = + (char)pAC->I2c.SenTable[Index].SenType; + Offset += sizeof(char); + break; + + case OID_SKGE_SENSOR_VALUE: + Val32 = (SK_U32)pAC->I2c.SenTable[Index].SenValue; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_WAR_THRES_LOW: + Val32 = (SK_U32)pAC->I2c.SenTable[Index]. + SenThreWarnLow; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_WAR_THRES_UPP: + Val32 = (SK_U32)pAC->I2c.SenTable[Index]. + SenThreWarnHigh; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_ERR_THRES_LOW: + Val32 = (SK_U32)pAC->I2c.SenTable[Index]. + SenThreErrLow; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_ERR_THRES_UPP: + Val32 = pAC->I2c.SenTable[Index].SenThreErrHigh; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_STATUS: + *(pBuf + Offset) = + (char)pAC->I2c.SenTable[Index].SenErrFlag; + Offset += sizeof(char); + break; + + case OID_SKGE_SENSOR_WAR_CTS: + Val64 = pAC->I2c.SenTable[Index].SenWarnCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_SENSOR_ERR_CTS: + Val64 = pAC->I2c.SenTable[Index].SenErrCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_SENSOR_WAR_TIME: + Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index]. + SenBegWarnTS); + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_SENSOR_ERR_TIME: + Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index]. + SenBegErrTS); + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("SensorStat: Unknown OID should be handled before")); + + return (SK_PNMI_ERR_GENERAL); + } + } + + /* + * Store used buffer space + */ + *pLen = Offset; + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * Vpd - OID handler function of OID_SKGE_VPD_XXX + * + * Description: + * Get/preset/set of VPD data. As instance the name of a VPD key + * can be passed. The Instance parameter is a SK_U32 and can be + * used as a string buffer for the VPD key, because their maximum + * length is 4 byte. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Vpd( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_VPD_STATUS *pVpdStatus; + unsigned int BufLen; + char Buf[256]; + char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE]; + char KeyStr[SK_PNMI_VPD_KEY_SIZE]; + unsigned int KeyNo; + unsigned int Offset; + unsigned int Index; + unsigned int FirstIndex; + unsigned int LastIndex; + unsigned int Len; + int Ret; + SK_U32 Val32; + + /* + * Get array of all currently stored VPD keys + */ + Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), + &KeyNo); + if (Ret != SK_PNMI_ERR_OK) { + *pLen = 0; + return (Ret); + } + + /* + * If instance is not -1, try to find the requested VPD key for + * the multiple instance variables. The other OIDs as for example + * OID VPD_ACTION are single instance variables and must be + * handled separatly. + */ + FirstIndex = 0; + LastIndex = KeyNo; + + if ((Instance != (SK_U32)(-1))) { + + if (Id == OID_SKGE_VPD_KEY || Id == OID_SKGE_VPD_VALUE || + Id == OID_SKGE_VPD_ACCESS) { + + SK_STRNCPY(KeyStr, (char *)&Instance, 4); + KeyStr[4] = 0; + + for (Index = 0; Index < KeyNo; Index ++) { + + if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) { + FirstIndex = Index; + LastIndex = Index+1; + break; + } + } + if (Index == KeyNo) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + } + else if (Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + } + + /* + * Get value, if a query should be performed + */ + if (Action == SK_PNMI_GET) { + + switch (Id) { + + case OID_SKGE_VPD_FREE_BYTES: + /* Check length of buffer */ + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + /* Get number of free bytes */ + pVpdStatus = VpdStat(pAC, IoC); + if (pVpdStatus == NULL) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR017, + SK_PNMI_ERR017MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + if ((pVpdStatus->vpd_status & VPD_VALID) == 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR018, + SK_PNMI_ERR018MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + Val32 = (SK_U32)pVpdStatus->vpd_free_rw; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_VPD_ENTRIES_LIST: + /* Check length */ + for (Len = 0, Index = 0; Index < KeyNo; Index ++) { + + Len += SK_STRLEN(KeyArr[Index]) + 1; + } + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* Get value */ + *(pBuf) = (char)Len - 1; + for (Offset = 1, Index = 0; Index < KeyNo; Index ++) { + + Len = SK_STRLEN(KeyArr[Index]); + SK_MEMCPY(pBuf + Offset, KeyArr[Index], Len); + + Offset += Len; + + if (Index < KeyNo - 1) { + + *(pBuf + Offset) = ' '; + Offset ++; + } + } + *pLen = Offset; + break; + + case OID_SKGE_VPD_ENTRIES_NUMBER: + /* Check length */ + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + + Val32 = (SK_U32)KeyNo; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_VPD_KEY: + /* Check buffer length, if it is large enough */ + for (Len = 0, Index = FirstIndex; + Index < LastIndex; Index ++) { + + Len += SK_STRLEN(KeyArr[Index]) + 1; + } + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Get the key to an intermediate buffer, because + * we have to prepend a length byte. + */ + for (Offset = 0, Index = FirstIndex; + Index < LastIndex; Index ++) { + + Len = SK_STRLEN(KeyArr[Index]); + + *(pBuf + Offset) = (char)Len; + SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index], + Len); + Offset += Len + 1; + } + *pLen = Offset; + break; + + case OID_SKGE_VPD_VALUE: + /* Check the buffer length if it is large enough */ + for (Offset = 0, Index = FirstIndex; + Index < LastIndex; Index ++) { + + BufLen = 256; + if (VpdRead(pAC, IoC, KeyArr[Index], Buf, + (int *)&BufLen) > 0 || + BufLen >= SK_PNMI_VPD_DATALEN) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR021, + SK_PNMI_ERR021MSG); + + return (SK_PNMI_ERR_GENERAL); + } + Offset += BufLen + 1; + } + if (*pLen < Offset) { + + *pLen = Offset; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * Get the value to an intermediate buffer, because + * we have to prepend a length byte. + */ + for (Offset = 0, Index = FirstIndex; + Index < LastIndex; Index ++) { + + BufLen = 256; + if (VpdRead(pAC, IoC, KeyArr[Index], Buf, + (int *)&BufLen) > 0 || + BufLen >= SK_PNMI_VPD_DATALEN) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR022, + SK_PNMI_ERR022MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + *(pBuf + Offset) = (char)BufLen; + SK_MEMCPY(pBuf + Offset + 1, Buf, BufLen); + Offset += BufLen + 1; + } + *pLen = Offset; + break; + + case OID_SKGE_VPD_ACCESS: + if (*pLen < LastIndex - FirstIndex) { + + *pLen = LastIndex - FirstIndex; + return (SK_PNMI_ERR_TOO_SHORT); + } + + for (Offset = 0, Index = FirstIndex; + Index < LastIndex; Index ++) { + + if (VpdMayWrite(KeyArr[Index])) { + + *(pBuf + Offset) = SK_PNMI_VPD_RW; + } + else { + *(pBuf + Offset) = SK_PNMI_VPD_RO; + } + Offset ++; + } + *pLen = Offset; + break; + + case OID_SKGE_VPD_ACTION: + Offset = LastIndex - FirstIndex; + if (*pLen < Offset) { + + *pLen = Offset; + return (SK_PNMI_ERR_TOO_SHORT); + } + SK_MEMSET(pBuf, 0, Offset); + *pLen = Offset; + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR023, + SK_PNMI_ERR023MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + else { + /* The only OID which can be set is VPD_ACTION */ + if (Id != OID_SKGE_VPD_ACTION) { + + if (Id == OID_SKGE_VPD_FREE_BYTES || + Id == OID_SKGE_VPD_ENTRIES_LIST || + Id == OID_SKGE_VPD_ENTRIES_NUMBER || + Id == OID_SKGE_VPD_KEY || + Id == OID_SKGE_VPD_VALUE || + Id == OID_SKGE_VPD_ACCESS) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR024, + SK_PNMI_ERR024MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * From this point we handle VPD_ACTION. Check the buffer + * length. It should at least have the size of one byte. + */ + if (*pLen < 1) { + + *pLen = 1; + return (SK_PNMI_ERR_TOO_SHORT); + } + + /* + * The first byte contains the VPD action type we should + * perform. + */ + switch (*pBuf) { + + case SK_PNMI_VPD_IGNORE: + /* Nothing to do */ + break; + + case SK_PNMI_VPD_CREATE: + /* + * We have to create a new VPD entry or we modify + * an existing one. Check first the buffer length. + */ + if (*pLen < 4) { + + *pLen = 4; + return (SK_PNMI_ERR_TOO_SHORT); + } + KeyStr[0] = pBuf[1]; + KeyStr[1] = pBuf[2]; + KeyStr[2] = 0; + + /* + * Is the entry writable or does it belong to the + * read-only area? + */ + if (!VpdMayWrite(KeyStr)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + Offset = (int)pBuf[3] & 0xFF; + + SK_MEMCPY(Buf, pBuf + 4, Offset); + Buf[Offset] = 0; + + /* A preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + /* Write the new entry or modify an existing one */ + Ret = VpdWrite(pAC, IoC, KeyStr, Buf); + if (Ret == SK_PNMI_VPD_NOWRITE ) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + else if (Ret != SK_PNMI_VPD_OK) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR025, + SK_PNMI_ERR025MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Perform an update of the VPD data. This is + * not mandantory, but just to be sure. + */ + Ret = VpdUpdate(pAC, IoC); + if (Ret != SK_PNMI_VPD_OK) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR026, + SK_PNMI_ERR026MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + break; + + case SK_PNMI_VPD_DELETE: + /* Check if the buffer size is plausible */ + if (*pLen < 3) { + + *pLen = 3; + return (SK_PNMI_ERR_TOO_SHORT); + } + if (*pLen > 3) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + KeyStr[0] = pBuf[1]; + KeyStr[1] = pBuf[2]; + KeyStr[2] = 0; + + /* Find the passed key in the array */ + for (Index = 0; Index < KeyNo; Index ++) { + + if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) { + + break; + } + } + /* + * If we cannot find the key it is wrong, so we + * return an appropriate error value. + */ + if (Index == KeyNo) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + /* Ok, you wanted it and you will get it */ + Ret = VpdDelete(pAC, IoC, KeyStr); + if (Ret != SK_PNMI_VPD_OK) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR027, + SK_PNMI_ERR027MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Perform an update of the VPD data. This is + * not mandantory, but just to be sure. + */ + Ret = VpdUpdate(pAC, IoC); + if (Ret != SK_PNMI_VPD_OK) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR028, + SK_PNMI_ERR028MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * General - OID handler function of various single instance OIDs + * + * Description: + * The code is simple. No description necessary. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int General( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + unsigned int Index; + unsigned int Len; + unsigned int Offset; + unsigned int Val; + SK_U8 Val8; + SK_U16 Val16; + SK_U32 Val32; + SK_U64 Val64; + SK_U64 Val64RxHwErrs = 0; + SK_U64 Val64TxHwErrs = 0; + SK_BOOL Is64BitReq = SK_FALSE; + char Buf[256]; + int MacType; + + /* + * Check instance. We only handle single instance variables + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* + * Check action. We only allow get requests. + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + MacType = pAC->GIni.GIMacType; + + /* + * Check length for the various supported OIDs + */ + switch (Id) { + + case OID_GEN_XMIT_ERROR: + case OID_GEN_RCV_ERROR: + case OID_GEN_RCV_NO_BUFFER: +#ifndef SK_NDIS_64BIT_CTR + if (*pLen < sizeof(SK_U32)) { + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + +#else /* SK_NDIS_64BIT_CTR */ + + /* + * for compatibility, at least 32bit are required for oid + */ + if (*pLen < sizeof(SK_U32)) { + /* + * but indicate handling for 64bit values, + * if insufficient space is provided + */ + *pLen = sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + + Is64BitReq = (*pLen < sizeof(SK_U64)) ? SK_FALSE : SK_TRUE; +#endif /* SK_NDIS_64BIT_CTR */ + break; + + case OID_SKGE_PORT_NUMBER: + case OID_SKGE_DEVICE_TYPE: + case OID_SKGE_RESULT: + case OID_SKGE_RLMT_MONITOR_NUMBER: + case OID_GEN_TRANSMIT_QUEUE_LENGTH: + case OID_SKGE_TRAP_NUMBER: + case OID_SKGE_MDB_VERSION: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_CHIPSET: + if (*pLen < sizeof(SK_U16)) { + + *pLen = sizeof(SK_U16); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_BUS_TYPE: + case OID_SKGE_BUS_SPEED: + case OID_SKGE_BUS_WIDTH: + case OID_SKGE_SENSOR_NUMBER: + case OID_SKGE_CHKSM_NUMBER: + if (*pLen < sizeof(SK_U8)) { + + *pLen = sizeof(SK_U8); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_TX_SW_QUEUE_LEN: + case OID_SKGE_TX_SW_QUEUE_MAX: + case OID_SKGE_TX_RETRY: + case OID_SKGE_RX_INTR_CTS: + case OID_SKGE_TX_INTR_CTS: + case OID_SKGE_RX_NO_BUF_CTS: + case OID_SKGE_TX_NO_BUF_CTS: + case OID_SKGE_TX_USED_DESCR_NO: + case OID_SKGE_RX_DELIVERED_CTS: + case OID_SKGE_RX_OCTETS_DELIV_CTS: + case OID_SKGE_RX_HW_ERROR_CTS: + case OID_SKGE_TX_HW_ERROR_CTS: + case OID_SKGE_IN_ERRORS_CTS: + case OID_SKGE_OUT_ERROR_CTS: + case OID_SKGE_ERR_RECOVERY_CTS: + case OID_SKGE_SYSUPTIME: + if (*pLen < sizeof(SK_U64)) { + + *pLen = sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + /* Checked later */ + break; + } + + /* Update statistic */ + if (Id == OID_SKGE_RX_HW_ERROR_CTS || + Id == OID_SKGE_TX_HW_ERROR_CTS || + Id == OID_SKGE_IN_ERRORS_CTS || + Id == OID_SKGE_OUT_ERROR_CTS || + Id == OID_GEN_XMIT_ERROR || + Id == OID_GEN_RCV_ERROR) { + + /* Force the XMAC to update its statistic counters and + * Increment semaphore to indicate that an update was + * already done. + */ + Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1); + if (Ret != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.MacUpdatedFlag ++; + + /* + * Some OIDs consist of multiple hardware counters. Those + * values which are contained in all of them will be added + * now. + */ + switch (Id) { + + case OID_SKGE_RX_HW_ERROR_CTS: + case OID_SKGE_IN_ERRORS_CTS: + case OID_GEN_RCV_ERROR: + Val64RxHwErrs = + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_MISSED, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FRAMING, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_JABBER, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CARRIER, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SYMBOL, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SHORTS, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT, NetIndex); + break; + + case OID_SKGE_TX_HW_ERROR_CTS: + case OID_SKGE_OUT_ERROR_CTS: + case OID_GEN_XMIT_ERROR: + Val64TxHwErrs = + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_EXCESS_COL, NetIndex) + + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_LATE_COL, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_UNDERRUN, NetIndex)+ + GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_CARRIER, NetIndex); + break; + } + } + + /* + * Retrieve value + */ + switch (Id) { + + case OID_SKGE_SUPPORTED_LIST: + Len = ID_TABLE_SIZE * sizeof(SK_U32); + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + for (Offset = 0, Index = 0; Offset < Len; + Offset += sizeof(SK_U32), Index ++) { + + Val32 = (SK_U32)IdTable[Index].Id; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + } + *pLen = Len; + break; + + case OID_SKGE_PORT_NUMBER: + Val32 = (SK_U32)pAC->GIni.GIMacsFound; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_DEVICE_TYPE: + Val32 = (SK_U32)pAC->Pnmi.DeviceType; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_DRIVER_DESCR: + if (pAC->Pnmi.pDriverDescription == NULL) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007, + SK_PNMI_ERR007MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + Len = SK_STRLEN(pAC->Pnmi.pDriverDescription) + 1; + if (Len > SK_PNMI_STRINGLEN1) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029, + SK_PNMI_ERR029MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + *pBuf = (char)(Len - 1); + SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverDescription, Len - 1); + *pLen = Len; + break; + + case OID_SKGE_DRIVER_VERSION: + if (pAC->Pnmi.pDriverVersion == NULL) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030, + SK_PNMI_ERR030MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + Len = SK_STRLEN(pAC->Pnmi.pDriverVersion) + 1; + if (Len > SK_PNMI_STRINGLEN1) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031, + SK_PNMI_ERR031MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + *pBuf = (char)(Len - 1); + SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverVersion, Len - 1); + *pLen = Len; + break; + + case OID_SKGE_HW_DESCR: + /* + * The hardware description is located in the VPD. This + * query may move to the initialisation routine. But + * the VPD data is cached and therefore a call here + * will not make much difference. + */ + Len = 256; + if (VpdRead(pAC, IoC, VPD_NAME, Buf, (int *)&Len) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032, + SK_PNMI_ERR032MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + Len ++; + if (Len > SK_PNMI_STRINGLEN1) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033, + SK_PNMI_ERR033MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + *pBuf = (char)(Len - 1); + SK_MEMCPY(pBuf + 1, Buf, Len - 1); + *pLen = Len; + break; + + case OID_SKGE_HW_VERSION: + /* Oh, I love to do some string manipulation */ + if (*pLen < 5) { + + *pLen = 5; + return (SK_PNMI_ERR_TOO_SHORT); + } + Val8 = (SK_U8)pAC->GIni.GIPciHwRev; + pBuf[0] = 4; + pBuf[1] = 'v'; + pBuf[2] = (char)(0x30 | ((Val8 >> 4) & 0x0F)); + pBuf[3] = '.'; + pBuf[4] = (char)(0x30 | (Val8 & 0x0F)); + *pLen = 5; + break; + + case OID_SKGE_CHIPSET: + Val16 = pAC->Pnmi.Chipset; + SK_PNMI_STORE_U16(pBuf, Val16); + *pLen = sizeof(SK_U16); + break; + + case OID_SKGE_BUS_TYPE: + *pBuf = (char)SK_PNMI_BUS_PCI; + *pLen = sizeof(char); + break; + + case OID_SKGE_BUS_SPEED: + *pBuf = pAC->Pnmi.PciBusSpeed; + *pLen = sizeof(char); + break; + + case OID_SKGE_BUS_WIDTH: + *pBuf = pAC->Pnmi.PciBusWidth; + *pLen = sizeof(char); + break; + + case OID_SKGE_RESULT: + Val32 = pAC->Pnmi.TestResult; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_SENSOR_NUMBER: + *pBuf = (char)pAC->I2c.MaxSens; + *pLen = sizeof(char); + break; + + case OID_SKGE_CHKSM_NUMBER: + *pBuf = SKCS_NUM_PROTOCOLS; + *pLen = sizeof(char); + break; + + case OID_SKGE_TRAP_NUMBER: + GetTrapQueueLen(pAC, &Len, &Val); + Val32 = (SK_U32)Val; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_TRAP: + GetTrapQueueLen(pAC, &Len, &Val); + if (*pLen < Len) { + + *pLen = Len; + return (SK_PNMI_ERR_TOO_SHORT); + } + CopyTrapQueue(pAC, pBuf); + *pLen = Len; + break; + + case OID_SKGE_RLMT_MONITOR_NUMBER: +/* XXX Not yet implemented by RLMT therefore we return zero elements */ + Val32 = 0; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_TX_SW_QUEUE_LEN: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueLen; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxSwQueueLen + + pAC->Pnmi.BufPort[1].TxSwQueueLen; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueLen; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxSwQueueLen + + pAC->Pnmi.Port[1].TxSwQueueLen; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + + case OID_SKGE_TX_SW_QUEUE_MAX: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueMax; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxSwQueueMax + + pAC->Pnmi.BufPort[1].TxSwQueueMax; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueMax; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxSwQueueMax + + pAC->Pnmi.Port[1].TxSwQueueMax; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_TX_RETRY: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxRetryCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxRetryCts + + pAC->Pnmi.BufPort[1].TxRetryCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxRetryCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxRetryCts + + pAC->Pnmi.Port[1].TxRetryCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RX_INTR_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].RxIntrCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].RxIntrCts + + pAC->Pnmi.BufPort[1].RxIntrCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].RxIntrCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].RxIntrCts + + pAC->Pnmi.Port[1].RxIntrCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_TX_INTR_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxIntrCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxIntrCts + + pAC->Pnmi.BufPort[1].TxIntrCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxIntrCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxIntrCts + + pAC->Pnmi.Port[1].TxIntrCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RX_NO_BUF_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].RxNoBufCts + + pAC->Pnmi.BufPort[1].RxNoBufCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].RxNoBufCts + + pAC->Pnmi.Port[1].RxNoBufCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_TX_NO_BUF_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxNoBufCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxNoBufCts + + pAC->Pnmi.BufPort[1].TxNoBufCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxNoBufCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxNoBufCts + + pAC->Pnmi.Port[1].TxNoBufCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_TX_USED_DESCR_NO: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].TxUsedDescrNo; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].TxUsedDescrNo + + pAC->Pnmi.BufPort[1].TxUsedDescrNo; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].TxUsedDescrNo; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].TxUsedDescrNo + + pAC->Pnmi.Port[1].TxUsedDescrNo; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RX_DELIVERED_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].RxDeliveredCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].RxDeliveredCts + + pAC->Pnmi.BufPort[1].RxDeliveredCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].RxDeliveredCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].RxDeliveredCts + + pAC->Pnmi.Port[1].RxDeliveredCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RX_OCTETS_DELIV_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].RxOctetsDeliveredCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].RxOctetsDeliveredCts + + pAC->Pnmi.BufPort[1].RxOctetsDeliveredCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].RxOctetsDeliveredCts + + pAC->Pnmi.Port[1].RxOctetsDeliveredCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RX_HW_ERROR_CTS: + SK_PNMI_STORE_U64(pBuf, Val64RxHwErrs); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_TX_HW_ERROR_CTS: + SK_PNMI_STORE_U64(pBuf, Val64TxHwErrs); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_IN_ERRORS_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; + } + /* Single net mode */ + else { + Val64 = Val64RxHwErrs + + pAC->Pnmi.BufPort[0].RxNoBufCts + + pAC->Pnmi.BufPort[1].RxNoBufCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts; + } + /* Single net mode */ + else { + Val64 = Val64RxHwErrs + + pAC->Pnmi.Port[0].RxNoBufCts + + pAC->Pnmi.Port[1].RxNoBufCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_OUT_ERROR_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts; + } + /* Single net mode */ + else { + Val64 = Val64TxHwErrs + + pAC->Pnmi.BufPort[0].TxNoBufCts + + pAC->Pnmi.BufPort[1].TxNoBufCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts; + } + /* Single net mode */ + else { + Val64 = Val64TxHwErrs + + pAC->Pnmi.Port[0].TxNoBufCts + + pAC->Pnmi.Port[1].TxNoBufCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_ERR_RECOVERY_CTS: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.BufPort[NetIndex].ErrRecoveryCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.BufPort[0].ErrRecoveryCts + + pAC->Pnmi.BufPort[1].ErrRecoveryCts; + } + } + else { + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + Val64 = pAC->Pnmi.Port[NetIndex].ErrRecoveryCts; + } + /* Single net mode */ + else { + Val64 = pAC->Pnmi.Port[0].ErrRecoveryCts + + pAC->Pnmi.Port[1].ErrRecoveryCts; + } + } + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_SYSUPTIME: + Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC)); + Val64 -= pAC->Pnmi.StartUpTime; + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_MDB_VERSION: + Val32 = SK_PNMI_MDB_VERSION; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_GEN_RCV_ERROR: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; + } + else { + Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts; + } + + /* + * by default 32bit values are evaluated + */ + if (!Is64BitReq) { + Val32 = (SK_U32)Val64; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + } + else { + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + } + break; + + case OID_GEN_XMIT_ERROR: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts; + } + else { + Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts; + } + + /* + * by default 32bit values are evaluated + */ + if (!Is64BitReq) { + Val32 = (SK_U32)Val64; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + } + else { + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + } + break; + + case OID_GEN_RCV_NO_BUFFER: + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (MacType == SK_MAC_XMAC) { + Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts; + } + else { + Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts; + } + + /* + * by default 32bit values are evaluated + */ + if (!Is64BitReq) { + Val32 = (SK_U32)Val64; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + } + else { + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + } + break; + + case OID_GEN_TRANSMIT_QUEUE_LENGTH: + Val32 = (SK_U32)pAC->Pnmi.Port[NetIndex].TxSwQueueLen; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034, + SK_PNMI_ERR034MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + if (Id == OID_SKGE_RX_HW_ERROR_CTS || + Id == OID_SKGE_TX_HW_ERROR_CTS || + Id == OID_SKGE_IN_ERRORS_CTS || + Id == OID_SKGE_OUT_ERROR_CTS || + Id == OID_GEN_XMIT_ERROR || + Id == OID_GEN_RCV_ERROR) { + + pAC->Pnmi.MacUpdatedFlag --; + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * Rlmt - OID handler function of OID_SKGE_RLMT_XXX single instance. + * + * Description: + * Get/Presets/Sets the RLMT OIDs. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Rlmt( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + int Ret; + unsigned int PhysPortIndex; + unsigned int PhysPortMax; + SK_EVPARA EventParam; + SK_U32 Val32; + SK_U64 Val64; + + + /* + * Check instance. Only single instance OIDs are allowed here. + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* + * Perform the requested action + */ + if (Action == SK_PNMI_GET) { + + /* + * Check if the buffer length is large enough. + */ + + switch (Id) { + + case OID_SKGE_RLMT_MODE: + case OID_SKGE_RLMT_PORT_ACTIVE: + case OID_SKGE_RLMT_PORT_PREFERRED: + if (*pLen < sizeof(SK_U8)) { + + *pLen = sizeof(SK_U8); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_RLMT_PORT_NUMBER: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_RLMT_CHANGE_CTS: + case OID_SKGE_RLMT_CHANGE_TIME: + case OID_SKGE_RLMT_CHANGE_ESTIM: + case OID_SKGE_RLMT_CHANGE_THRES: + if (*pLen < sizeof(SK_U64)) { + + *pLen = sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035, + SK_PNMI_ERR035MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Update RLMT statistic and increment semaphores to indicate + * that an update was already done. Maybe RLMT will hold its + * statistic always up to date some time. Then we can + * remove this type of call. + */ + if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.RlmtUpdatedFlag ++; + + /* + * Retrieve Value + */ + switch (Id) { + + case OID_SKGE_RLMT_MODE: + *pBuf = (char)pAC->Rlmt.Net[0].RlmtMode; + *pLen = sizeof(char); + break; + + case OID_SKGE_RLMT_PORT_NUMBER: + Val32 = (SK_U32)pAC->GIni.GIMacsFound; + SK_PNMI_STORE_U32(pBuf, Val32); + *pLen = sizeof(SK_U32); + break; + + case OID_SKGE_RLMT_PORT_ACTIVE: + *pBuf = 0; + /* + * If multiple ports may become active this OID + * doesn't make sense any more. A new variable in + * the port structure should be created. However, + * for this variable the first active port is + * returned. + */ + PhysPortMax = pAC->GIni.GIMacsFound; + + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + *pBuf = (char)SK_PNMI_PORT_PHYS2LOG(PhysPortIndex); + break; + } + } + *pLen = sizeof(char); + break; + + case OID_SKGE_RLMT_PORT_PREFERRED: + *pBuf = (char)SK_PNMI_PORT_PHYS2LOG(pAC->Rlmt.Net[NetIndex].Preference); + *pLen = sizeof(char); + break; + + case OID_SKGE_RLMT_CHANGE_CTS: + Val64 = pAC->Pnmi.RlmtChangeCts; + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_CHANGE_TIME: + Val64 = pAC->Pnmi.RlmtChangeTime; + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_CHANGE_ESTIM: + Val64 = pAC->Pnmi.RlmtChangeEstimate.Estimate; + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_CHANGE_THRES: + Val64 = pAC->Pnmi.RlmtChangeThreshold; + SK_PNMI_STORE_U64(pBuf, Val64); + *pLen = sizeof(SK_U64); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("Rlmt: Unknown OID should be handled before")); + + pAC->Pnmi.RlmtUpdatedFlag --; + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + pAC->Pnmi.RlmtUpdatedFlag --; + } + else { + /* Perform a preset or set */ + switch (Id) { + + case OID_SKGE_RLMT_MODE: + /* Check if the buffer length is plausible */ + if (*pLen < sizeof(char)) { + + *pLen = sizeof(char); + return (SK_PNMI_ERR_TOO_SHORT); + } + /* Check if the value range is correct */ + if (*pLen != sizeof(char) || + (*pBuf & SK_PNMI_RLMT_MODE_CHK_LINK) == 0 || + *(SK_U8 *)pBuf > 15) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + *pLen = 0; + return (SK_PNMI_ERR_OK); + } + /* Send an event to RLMT to change the mode */ + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + EventParam.Para32[0] |= (SK_U32)(*pBuf); + EventParam.Para32[1] = 0; + if (SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037, + SK_PNMI_ERR037MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + break; + + case OID_SKGE_RLMT_PORT_PREFERRED: + /* Check if the buffer length is plausible */ + if (*pLen < sizeof(char)) { + + *pLen = sizeof(char); + return (SK_PNMI_ERR_TOO_SHORT); + } + /* Check if the value range is correct */ + if (*pLen != sizeof(char) || *(SK_U8 *)pBuf > + (SK_U8)pAC->GIni.GIMacsFound) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + *pLen = 0; + return (SK_PNMI_ERR_OK); + } + + /* + * Send an event to RLMT change the preferred port. + * A param of -1 means automatic mode. RLMT will + * make the decision which is the preferred port. + */ + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + EventParam.Para32[0] = (SK_U32)(*pBuf) - 1; + EventParam.Para32[1] = NetIndex; + if (SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038, + SK_PNMI_ERR038MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + break; + + case OID_SKGE_RLMT_CHANGE_THRES: + /* Check if the buffer length is plausible */ + if (*pLen < sizeof(SK_U64)) { + + *pLen = sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + /* + * There are not many restrictions to the + * value range. + */ + if (*pLen != sizeof(SK_U64)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + /* A preset ends here */ + if (Action == SK_PNMI_PRESET) { + + *pLen = 0; + return (SK_PNMI_ERR_OK); + } + /* + * Store the new threshold, which will be taken + * on the next timer event. + */ + SK_PNMI_READ_U64(pBuf, Val64); + pAC->Pnmi.RlmtChangeThreshold = Val64; + break; + + default: + /* The other OIDs are not be able for set */ + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * RlmtStat - OID handler function of OID_SKGE_RLMT_XXX multiple instance. + * + * Description: + * Performs get requests on multiple instance variables. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int RlmtStat( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int PhysPortMax; + unsigned int PhysPortIndex; + unsigned int Limit; + unsigned int Offset; + int Ret; + SK_U32 Val32; + SK_U64 Val64; + + /* + * Calculate the port indexes from the instance + */ + PhysPortMax = pAC->GIni.GIMacsFound; + + if ((Instance != (SK_U32)(-1))) { + /* Check instance range */ + if ((Instance < 1) || (Instance > PhysPortMax)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* Single net mode */ + PhysPortIndex = Instance - 1; + + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + PhysPortIndex = NetIndex; + } + + /* Both net modes */ + Limit = PhysPortIndex + 1; + } + else { + /* Single net mode */ + PhysPortIndex = 0; + Limit = PhysPortMax; + + /* Dual net mode */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + PhysPortIndex = NetIndex; + Limit = PhysPortIndex + 1; + } + } + + /* + * Currently only get requests are allowed. + */ + if (Action != SK_PNMI_GET) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Check if the buffer length is large enough. + */ + switch (Id) { + + case OID_SKGE_RLMT_PORT_INDEX: + case OID_SKGE_RLMT_STATUS: + if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) { + + *pLen = (Limit - PhysPortIndex) * sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_RLMT_TX_HELLO_CTS: + case OID_SKGE_RLMT_RX_HELLO_CTS: + case OID_SKGE_RLMT_TX_SP_REQ_CTS: + case OID_SKGE_RLMT_RX_SP_CTS: + if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U64)) { + + *pLen = (Limit - PhysPortIndex) * sizeof(SK_U64); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039, + SK_PNMI_ERR039MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + + } + + /* + * Update statistic and increment semaphores to indicate that + * an update was already done. + */ + if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.RlmtUpdatedFlag ++; + + /* + * Get value + */ + Offset = 0; + for (; PhysPortIndex < Limit; PhysPortIndex ++) { + + switch (Id) { + + case OID_SKGE_RLMT_PORT_INDEX: + Val32 = PhysPortIndex; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_RLMT_STATUS: + if (pAC->Rlmt.Port[PhysPortIndex].PortState == + SK_RLMT_PS_INIT || + pAC->Rlmt.Port[PhysPortIndex].PortState == + SK_RLMT_PS_DOWN) { + + Val32 = SK_PNMI_RLMT_STATUS_ERROR; + } + else if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + Val32 = SK_PNMI_RLMT_STATUS_ACTIVE; + } + else { + Val32 = SK_PNMI_RLMT_STATUS_STANDBY; + } + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + case OID_SKGE_RLMT_TX_HELLO_CTS: + Val64 = pAC->Rlmt.Port[PhysPortIndex].TxHelloCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_RX_HELLO_CTS: + Val64 = pAC->Rlmt.Port[PhysPortIndex].RxHelloCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_TX_SP_REQ_CTS: + Val64 = pAC->Rlmt.Port[PhysPortIndex].TxSpHelloReqCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + case OID_SKGE_RLMT_RX_SP_CTS: + Val64 = pAC->Rlmt.Port[PhysPortIndex].RxSpHelloCts; + SK_PNMI_STORE_U64(pBuf + Offset, Val64); + Offset += sizeof(SK_U64); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("RlmtStat: Unknown OID should be errored before")); + + pAC->Pnmi.RlmtUpdatedFlag --; + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + *pLen = Offset; + + pAC->Pnmi.RlmtUpdatedFlag --; + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * MacPrivateConf - OID handler function of OIDs concerning the configuration + * + * Description: + * Get/Presets/Sets the OIDs concerning the configuration. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int MacPrivateConf( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int PhysPortMax; + unsigned int PhysPortIndex; + unsigned int LogPortMax; + unsigned int LogPortIndex; + unsigned int Limit; + unsigned int Offset; + char Val8; + int Ret; + SK_EVPARA EventParam; + SK_U32 Val32; + + + /* + * Calculate instance if wished. MAC index 0 is the virtual + * MAC. + */ + PhysPortMax = pAC->GIni.GIMacsFound; + LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); + + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + LogPortMax--; + } + + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */ + /* Check instance range */ + if ((Instance < 1) || (Instance > LogPortMax)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance); + Limit = LogPortIndex + 1; + } + + else { /* Instance == (SK_U32)(-1), get all Instances of that OID */ + + LogPortIndex = 0; + Limit = LogPortMax; + } + + /* + * Perform action + */ + if (Action == SK_PNMI_GET) { + + /* + * Check length + */ + switch (Id) { + + case OID_SKGE_PMD: + case OID_SKGE_CONNECTOR: + case OID_SKGE_LINK_CAP: + case OID_SKGE_LINK_MODE: + case OID_SKGE_LINK_MODE_STATUS: + case OID_SKGE_LINK_STATUS: + case OID_SKGE_FLOWCTRL_CAP: + case OID_SKGE_FLOWCTRL_MODE: + case OID_SKGE_FLOWCTRL_STATUS: + case OID_SKGE_PHY_OPERATION_CAP: + case OID_SKGE_PHY_OPERATION_MODE: + case OID_SKGE_PHY_OPERATION_STATUS: + case OID_SKGE_SPEED_CAP: + case OID_SKGE_SPEED_MODE: + case OID_SKGE_SPEED_STATUS: + if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U8)) { + + *pLen = (Limit - LogPortIndex) * + sizeof(SK_U8); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_MTU: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041, + SK_PNMI_ERR041MSG); + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Update statistic and increment semaphore to indicate + * that an update was already done. + */ + if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) { + + *pLen = 0; + return (Ret); + } + pAC->Pnmi.SirqUpdatedFlag ++; + + /* + * Get value + */ + Offset = 0; + for (; LogPortIndex < Limit; LogPortIndex ++) { + + switch (Id) { + + case OID_SKGE_PMD: + *(pBuf + Offset) = pAC->Pnmi.PMD; + Offset += sizeof(char); + break; + + case OID_SKGE_CONNECTOR: + *(pBuf + Offset) = pAC->Pnmi.Connector; + Offset += sizeof(char); + break; + + case OID_SKGE_LINK_CAP: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PLinkCap; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkCap; + Offset += sizeof(char); + } + break; + + case OID_SKGE_LINK_MODE: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PLinkModeConf; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkModeConf; + Offset += sizeof(char); + } + break; + + case OID_SKGE_LINK_MODE_STATUS: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = + CalculateLinkModeStatus(pAC, + IoC, PhysPortIndex); + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + *(pBuf + Offset) = CalculateLinkModeStatus(pAC, IoC, NetIndex); + Offset += sizeof(char); + } + break; + + case OID_SKGE_LINK_STATUS: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = + CalculateLinkStatus(pAC, + IoC, PhysPortIndex); + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = CalculateLinkStatus(pAC, IoC, NetIndex); + Offset += sizeof(char); + } + break; + + case OID_SKGE_FLOWCTRL_CAP: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PFlowCtrlCap; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PFlowCtrlCap; + Offset += sizeof(char); + } + break; + + case OID_SKGE_FLOWCTRL_MODE: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PFlowCtrlMode; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PFlowCtrlMode; + Offset += sizeof(char); + } + break; + + case OID_SKGE_FLOWCTRL_STATUS: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PFlowCtrlStatus; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PFlowCtrlStatus; + Offset += sizeof(char); + } + break; + + case OID_SKGE_PHY_OPERATION_CAP: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PMSCap; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSCap; + Offset += sizeof(char); + } + break; + + case OID_SKGE_PHY_OPERATION_MODE: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PMSMode; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSMode; + Offset += sizeof(char); + } + break; + + case OID_SKGE_PHY_OPERATION_STATUS: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PMSStatus; + } + Offset += sizeof(char); + } + else { + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSStatus; + Offset += sizeof(char); + } + break; + + case OID_SKGE_SPEED_CAP: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + + Offset); + } + else { + /* Get value for physical ports */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PLinkSpeedCap; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkSpeedCap; + Offset += sizeof(char); + } + break; + + case OID_SKGE_SPEED_MODE: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PLinkSpeed; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkSpeed; + Offset += sizeof(char); + } + break; + + case OID_SKGE_SPEED_STATUS: + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */ + if (LogPortIndex == 0) { + + /* Get value for virtual port */ + VirtualConf(pAC, IoC, Id, pBuf + Offset); + } + else { + /* Get value for physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + + *(pBuf + Offset) = pAC->GIni.GP[ + PhysPortIndex].PLinkSpeedUsed; + } + Offset += sizeof(char); + } + else { /* DualNetMode */ + + *(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkSpeedUsed; + Offset += sizeof(char); + } + break; + + case OID_SKGE_MTU: + Val32 = SK_DRIVER_GET_MTU(pAC, IoC, NetIndex); + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + Offset += sizeof(SK_U32); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("MacPrivateConf: Unknown OID should be handled before")); + + pAC->Pnmi.SirqUpdatedFlag --; + return (SK_PNMI_ERR_GENERAL); + } + } + *pLen = Offset; + pAC->Pnmi.SirqUpdatedFlag --; + + return (SK_PNMI_ERR_OK); + } + + /* + * From here SET or PRESET action. Check if the passed + * buffer length is plausible. + */ + switch (Id) { + + case OID_SKGE_LINK_MODE: + case OID_SKGE_FLOWCTRL_MODE: + case OID_SKGE_PHY_OPERATION_MODE: + case OID_SKGE_SPEED_MODE: + if (*pLen < Limit - LogPortIndex) { + + *pLen = Limit - LogPortIndex; + return (SK_PNMI_ERR_TOO_SHORT); + } + if (*pLen != Limit - LogPortIndex) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + break; + + case OID_SKGE_MTU: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + if (*pLen != sizeof(SK_U32)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Perform preset or set + */ + Offset = 0; + for (; LogPortIndex < Limit; LogPortIndex ++) { + + switch (Id) { + + case OID_SKGE_LINK_MODE: + /* Check the value range */ + Val8 = *(pBuf + Offset); + if (Val8 == 0) { + + Offset += sizeof(char); + break; + } + if (Val8 < SK_LMODE_HALF || + (LogPortIndex != 0 && Val8 > SK_LMODE_AUTOSENSE) || + (LogPortIndex == 0 && Val8 > SK_LMODE_INDETERMINATED)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + if (LogPortIndex == 0) { + + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with the new link mode to SIRQ. + */ + for (PhysPortIndex = 0; + PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (!pAC->Pnmi.Port[PhysPortIndex]. + ActiveFlag) { + + continue; + } + + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_LMODE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR043, + SK_PNMI_ERR043MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + } + else { + /* + * Send an event with the new link mode to + * the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR043, + SK_PNMI_ERR043MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + Offset += sizeof(char); + break; + + case OID_SKGE_FLOWCTRL_MODE: + /* Check the value range */ + Val8 = *(pBuf + Offset); + if (Val8 == 0) { + + Offset += sizeof(char); + break; + } + if (Val8 < SK_FLOW_MODE_NONE || + (LogPortIndex != 0 && Val8 > SK_FLOW_MODE_SYM_OR_REM) || + (LogPortIndex == 0 && Val8 > SK_FLOW_MODE_INDETERMINATED)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + if (LogPortIndex == 0) { + + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with the new flow control mode to SIRQ. + */ + for (PhysPortIndex = 0; + PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (!pAC->Pnmi.Port[PhysPortIndex]. + ActiveFlag) { + + continue; + } + + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_FLOWMODE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR044, + SK_PNMI_ERR044MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + } + else { + /* + * Send an event with the new flow control + * mode to the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_FLOWMODE, EventParam) + > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR044, + SK_PNMI_ERR044MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + Offset += sizeof(char); + break; + + case OID_SKGE_PHY_OPERATION_MODE : + /* Check the value range */ + Val8 = *(pBuf + Offset); + if (Val8 == 0) { + /* mode of this port remains unchanged */ + Offset += sizeof(char); + break; + } + if (Val8 < SK_MS_MODE_AUTO || + (LogPortIndex != 0 && Val8 > SK_MS_MODE_SLAVE) || + (LogPortIndex == 0 && Val8 > SK_MS_MODE_INDETERMINATED)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + if (LogPortIndex == 0) { + + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with new master/slave (role) mode to SIRQ. + */ + for (PhysPortIndex = 0; + PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (!pAC->Pnmi.Port[PhysPortIndex]. + ActiveFlag) { + + continue; + } + + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_ROLE, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR042, + SK_PNMI_ERR042MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + } + else { + /* + * Send an event with the new master/slave + * (role) mode to the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_ROLE, EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR042, + SK_PNMI_ERR042MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + + Offset += sizeof(char); + break; + + case OID_SKGE_SPEED_MODE: + /* Check the value range */ + Val8 = *(pBuf + Offset); + if (Val8 == 0) { + + Offset += sizeof(char); + break; + } + if (Val8 < (SK_LSPEED_AUTO) || + (LogPortIndex != 0 && Val8 > (SK_LSPEED_1000MBPS)) || + (LogPortIndex == 0 && Val8 > (SK_LSPEED_INDETERMINATED))) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + + return (SK_PNMI_ERR_OK); + } + + if (LogPortIndex == 0) { + + /* + * The virtual port consists of all currently + * active ports. Find them and send an event + * with the new flow control mode to SIRQ. + */ + for (PhysPortIndex = 0; + PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + continue; + } + + EventParam.Para32[0] = PhysPortIndex; + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_SPEED, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR045, + SK_PNMI_ERR045MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + } + else { + /* + * Send an event with the new flow control + * mode to the SIRQ module. + */ + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS( + pAC, LogPortIndex); + EventParam.Para32[1] = (SK_U32)Val8; + if (SkGeSirqEvent(pAC, IoC, + SK_HWEV_SET_SPEED, + EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, + SK_PNMI_ERR045, + SK_PNMI_ERR045MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + Offset += sizeof(char); + break; + + case OID_SKGE_MTU : + /* Check the value range */ + Val32 = *(SK_U32*)(pBuf + Offset); + if (Val32 == 0) { + /* mtu of this port remains unchanged */ + Offset += sizeof(SK_U32); + break; + } + if (SK_DRIVER_PRESET_MTU(pAC, IoC, NetIndex, Val32) != 0) { + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + /* The preset ends here */ + if (Action == SK_PNMI_PRESET) { + return (SK_PNMI_ERR_OK); + } + + if (SK_DRIVER_SET_MTU(pAC, IoC, NetIndex, Val32) != 0) { + return (SK_PNMI_ERR_GENERAL); + } + + Offset += sizeof(SK_U32); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR, + ("MacPrivateConf: Unknown OID should be handled before set")); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * Monitor - OID handler function for RLMT_MONITOR_XXX + * + * Description: + * Because RLMT currently does not support the monitoring of + * remote adapter cards, we return always an empty table. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid + * value range. + * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set. + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ +PNMI_STATIC int Monitor( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int Index; + unsigned int Limit; + unsigned int Offset; + unsigned int Entries; + + + /* + * Calculate instance if wished. + */ +/* XXX Not yet implemented. Return always an empty table. */ + Entries = 0; + + if ((Instance != (SK_U32)(-1))) { + + if ((Instance < 1) || (Instance > Entries)) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + Index = (unsigned int)Instance - 1; + Limit = (unsigned int)Instance; + } + else { + Index = 0; + Limit = Entries; + } + + /* + * Get/Set value + */ + if (Action == SK_PNMI_GET) { + + for (Offset=0; Index < Limit; Index ++) { + + switch (Id) { + + case OID_SKGE_RLMT_MONITOR_INDEX: + case OID_SKGE_RLMT_MONITOR_ADDR: + case OID_SKGE_RLMT_MONITOR_ERRS: + case OID_SKGE_RLMT_MONITOR_TIMESTAMP: + case OID_SKGE_RLMT_MONITOR_ADMIN: + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR046, + SK_PNMI_ERR046MSG); + + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } + *pLen = Offset; + } + else { + /* Only MONITOR_ADMIN can be set */ + if (Id != OID_SKGE_RLMT_MONITOR_ADMIN) { + + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* Check if the length is plausible */ + if (*pLen < (Limit - Index)) { + + return (SK_PNMI_ERR_TOO_SHORT); + } + /* Okay, we have a wide value range */ + if (*pLen != (Limit - Index)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } +/* + for (Offset=0; Index < Limit; Index ++) { + } +*/ +/* + * XXX Not yet implemented. Return always BAD_VALUE, because the table + * is empty. + */ + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * VirtualConf - Calculates the values of configuration OIDs for virtual port + * + * Description: + * We handle here the get of the configuration group OIDs, which are + * a little bit complicated. The virtual port consists of all currently + * active physical ports. If multiple ports are active and configured + * differently we get in some trouble to return a single value. So we + * get the value of the first active port and compare it with that of + * the other active ports. If they are not the same, we return a value + * that indicates that the state is indeterminated. + * + * Returns: + * Nothing + */ +PNMI_STATIC void VirtualConf( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf) /* Buffer to which to mgmt data will be retrieved */ +{ + unsigned int PhysPortMax; + unsigned int PhysPortIndex; + SK_U8 Val8; + SK_BOOL PortActiveFlag; + + + *pBuf = 0; + PortActiveFlag = SK_FALSE; + PhysPortMax = pAC->GIni.GIMacsFound; + + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + /* Check if the physical port is active */ + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + continue; + } + + PortActiveFlag = SK_TRUE; + + switch (Id) { + + case OID_SKGE_LINK_CAP: + + /* + * Different capabilities should not happen, but + * in the case of the cases OR them all together. + * From a curious point of view the virtual port + * is capable of all found capabilities. + */ + *pBuf |= pAC->GIni.GP[PhysPortIndex].PLinkCap; + break; + + case OID_SKGE_LINK_MODE: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PLinkModeConf; + continue; + } + + /* + * If we find an active port with a different link + * mode than the first one we return a value that + * indicates that the link mode is indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PLinkModeConf + ) { + + *pBuf = SK_LMODE_INDETERMINATED; + } + break; + + case OID_SKGE_LINK_MODE_STATUS: + /* Get the link mode of the physical port */ + Val8 = CalculateLinkModeStatus(pAC, IoC, PhysPortIndex); + + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = Val8; + continue; + } + + /* + * If we find an active port with a different link + * mode status than the first one we return a value + * that indicates that the link mode status is + * indeterminated. + */ + if (*pBuf != Val8) { + + *pBuf = SK_LMODE_STAT_INDETERMINATED; + } + break; + + case OID_SKGE_LINK_STATUS: + /* Get the link status of the physical port */ + Val8 = CalculateLinkStatus(pAC, IoC, PhysPortIndex); + + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = Val8; + continue; + } + + /* + * If we find an active port with a different link + * status than the first one, we return a value + * that indicates that the link status is + * indeterminated. + */ + if (*pBuf != Val8) { + + *pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED; + } + break; + + case OID_SKGE_FLOWCTRL_CAP: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap; + continue; + } + + /* + * From a curious point of view the virtual port + * is capable of all found capabilities. + */ + *pBuf |= pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap; + break; + + case OID_SKGE_FLOWCTRL_MODE: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode; + continue; + } + + /* + * If we find an active port with a different flow + * control mode than the first one, we return a value + * that indicates that the mode is indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode) { + + *pBuf = SK_FLOW_MODE_INDETERMINATED; + } + break; + + case OID_SKGE_FLOWCTRL_STATUS: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus; + continue; + } + + /* + * If we find an active port with a different flow + * control status than the first one, we return a + * value that indicates that the status is + * indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus) { + + *pBuf = SK_FLOW_STAT_INDETERMINATED; + } + break; + + case OID_SKGE_PHY_OPERATION_CAP: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PMSCap; + continue; + } + + /* + * From a curious point of view the virtual port + * is capable of all found capabilities. + */ + *pBuf |= pAC->GIni.GP[PhysPortIndex].PMSCap; + break; + + case OID_SKGE_PHY_OPERATION_MODE: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PMSMode; + continue; + } + + /* + * If we find an active port with a different master/ + * slave mode than the first one, we return a value + * that indicates that the mode is indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PMSMode) { + + *pBuf = SK_MS_MODE_INDETERMINATED; + } + break; + + case OID_SKGE_PHY_OPERATION_STATUS: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PMSStatus; + continue; + } + + /* + * If we find an active port with a different master/ + * slave status than the first one, we return a + * value that indicates that the status is + * indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PMSStatus) { + + *pBuf = SK_MS_STAT_INDETERMINATED; + } + break; + + case OID_SKGE_SPEED_MODE: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PLinkSpeed; + continue; + } + + /* + * If we find an active port with a different flow + * control mode than the first one, we return a value + * that indicates that the mode is indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PLinkSpeed) { + + *pBuf = SK_LSPEED_INDETERMINATED; + } + break; + + case OID_SKGE_SPEED_STATUS: + /* Check if it is the first active port */ + if (*pBuf == 0) { + + *pBuf = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed; + continue; + } + + /* + * If we find an active port with a different flow + * control status than the first one, we return a + * value that indicates that the status is + * indeterminated. + */ + if (*pBuf != pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed) { + + *pBuf = SK_LSPEED_STAT_INDETERMINATED; + } + break; + } + } + + /* + * If no port is active return an indeterminated answer + */ + if (!PortActiveFlag) { + + switch (Id) { + + case OID_SKGE_LINK_CAP: + *pBuf = SK_LMODE_CAP_INDETERMINATED; + break; + + case OID_SKGE_LINK_MODE: + *pBuf = SK_LMODE_INDETERMINATED; + break; + + case OID_SKGE_LINK_MODE_STATUS: + *pBuf = SK_LMODE_STAT_INDETERMINATED; + break; + + case OID_SKGE_LINK_STATUS: + *pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED; + break; + + case OID_SKGE_FLOWCTRL_CAP: + case OID_SKGE_FLOWCTRL_MODE: + *pBuf = SK_FLOW_MODE_INDETERMINATED; + break; + + case OID_SKGE_FLOWCTRL_STATUS: + *pBuf = SK_FLOW_STAT_INDETERMINATED; + break; + + case OID_SKGE_PHY_OPERATION_CAP: + *pBuf = SK_MS_CAP_INDETERMINATED; + break; + + case OID_SKGE_PHY_OPERATION_MODE: + *pBuf = SK_MS_MODE_INDETERMINATED; + break; + + case OID_SKGE_PHY_OPERATION_STATUS: + *pBuf = SK_MS_STAT_INDETERMINATED; + break; + case OID_SKGE_SPEED_CAP: + *pBuf = SK_LSPEED_CAP_INDETERMINATED; + break; + + case OID_SKGE_SPEED_MODE: + *pBuf = SK_LSPEED_INDETERMINATED; + break; + + case OID_SKGE_SPEED_STATUS: + *pBuf = SK_LSPEED_STAT_INDETERMINATED; + break; + } + } +} + +/***************************************************************************** + * + * CalculateLinkStatus - Determins the link status of a physical port + * + * Description: + * Determins the link status the following way: + * LSTAT_PHY_DOWN: Link is down + * LSTAT_AUTONEG: Auto-negotiation failed + * LSTAT_LOG_DOWN: Link is up but RLMT did not yet put the port + * logically up. + * LSTAT_LOG_UP: RLMT marked the port as up + * + * Returns: + * Link status of physical port + */ +PNMI_STATIC SK_U8 CalculateLinkStatus( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +unsigned int PhysPortIndex) /* Physical port index */ +{ + SK_U8 Result; + + + if (!pAC->GIni.GP[PhysPortIndex].PHWLinkUp) { + + Result = SK_PNMI_RLMT_LSTAT_PHY_DOWN; + } + else if (pAC->GIni.GP[PhysPortIndex].PAutoNegFail > 0) { + + Result = SK_PNMI_RLMT_LSTAT_AUTONEG; + } + else if (!pAC->Rlmt.Port[PhysPortIndex].PortDown) { + + Result = SK_PNMI_RLMT_LSTAT_LOG_UP; + } + else { + Result = SK_PNMI_RLMT_LSTAT_LOG_DOWN; + } + + return (Result); +} + +/***************************************************************************** + * + * CalculateLinkModeStatus - Determins the link mode status of a phys. port + * + * Description: + * The COMMON module only tells us if the mode is half or full duplex. + * But in the decade of auto sensing it is usefull for the user to + * know if the mode was negotiated or forced. Therefore we have a + * look to the mode, which was last used by the negotiation process. + * + * Returns: + * The link mode status + */ +PNMI_STATIC SK_U8 CalculateLinkModeStatus( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +unsigned int PhysPortIndex) /* Physical port index */ +{ + SK_U8 Result; + + + /* Get the current mode, which can be full or half duplex */ + Result = pAC->GIni.GP[PhysPortIndex].PLinkModeStatus; + + /* Check if no valid mode could be found (link is down) */ + if (Result < SK_LMODE_STAT_HALF) { + + Result = SK_LMODE_STAT_UNKNOWN; + } + else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) { + + /* + * Auto-negotiation was used to bring up the link. Change + * the already found duplex status that it indicates + * auto-negotiation was involved. + */ + if (Result == SK_LMODE_STAT_HALF) { + + Result = SK_LMODE_STAT_AUTOHALF; + } + else if (Result == SK_LMODE_STAT_FULL) { + + Result = SK_LMODE_STAT_AUTOFULL; + } + } + + return (Result); +} + +/***************************************************************************** + * + * GetVpdKeyArr - Obtain an array of VPD keys + * + * Description: + * Read the VPD keys and build an array of VPD keys, which are + * easy to access. + * + * Returns: + * SK_PNMI_ERR_OK Task successfully performed. + * SK_PNMI_ERR_GENERAL Something went wrong. + */ +PNMI_STATIC int GetVpdKeyArr( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +char *pKeyArr, /* Ptr KeyArray */ +unsigned int KeyArrLen, /* Length of array in bytes */ +unsigned int *pKeyNo) /* Number of keys */ +{ + unsigned int BufKeysLen = SK_PNMI_VPD_BUFSIZE; + char BufKeys[SK_PNMI_VPD_BUFSIZE]; + unsigned int StartOffset; + unsigned int Offset; + int Index; + int Ret; + + + SK_MEMSET(pKeyArr, 0, KeyArrLen); + + /* + * Get VPD key list + */ + Ret = VpdKeys(pAC, IoC, (char *)&BufKeys, (int *)&BufKeysLen, + (int *)pKeyNo); + if (Ret > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR014, + SK_PNMI_ERR014MSG); + + return (SK_PNMI_ERR_GENERAL); + } + /* If no keys are available return now */ + if (*pKeyNo == 0 || BufKeysLen == 0) { + + return (SK_PNMI_ERR_OK); + } + /* + * If the key list is too long for us trunc it and give a + * errorlog notification. This case should not happen because + * the maximum number of keys is limited due to RAM limitations + */ + if (*pKeyNo > SK_PNMI_VPD_ENTRIES) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR015, + SK_PNMI_ERR015MSG); + + *pKeyNo = SK_PNMI_VPD_ENTRIES; + } + + /* + * Now build an array of fixed string length size and copy + * the keys together. + */ + for (Index = 0, StartOffset = 0, Offset = 0; Offset < BufKeysLen; + Offset ++) { + + if (BufKeys[Offset] != 0) { + + continue; + } + + if (Offset - StartOffset > SK_PNMI_VPD_KEY_SIZE) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR016, + SK_PNMI_ERR016MSG); + return (SK_PNMI_ERR_GENERAL); + } + + SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE, + &BufKeys[StartOffset], SK_PNMI_VPD_KEY_SIZE); + + Index ++; + StartOffset = Offset + 1; + } + + /* Last key not zero terminated? Get it anyway */ + if (StartOffset < Offset) { + + SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE, + &BufKeys[StartOffset], SK_PNMI_VPD_KEY_SIZE); + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * SirqUpdate - Let the SIRQ update its internal values + * + * Description: + * Just to be sure that the SIRQ module holds its internal data + * structures up to date, we send an update event before we make + * any access. + * + * Returns: + * SK_PNMI_ERR_OK Task successfully performed. + * SK_PNMI_ERR_GENERAL Something went wrong. + */ +PNMI_STATIC int SirqUpdate( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC) /* IO context handle */ +{ + SK_EVPARA EventParam; + + + /* Was the module already updated during the current PNMI call? */ + if (pAC->Pnmi.SirqUpdatedFlag > 0) { + + return (SK_PNMI_ERR_OK); + } + + /* Send an synchronuous update event to the module */ + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047, + SK_PNMI_ERR047MSG); + + return (SK_PNMI_ERR_GENERAL); + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * RlmtUpdate - Let the RLMT update its internal values + * + * Description: + * Just to be sure that the RLMT module holds its internal data + * structures up to date, we send an update event before we make + * any access. + * + * Returns: + * SK_PNMI_ERR_OK Task successfully performed. + * SK_PNMI_ERR_GENERAL Something went wrong. + */ +PNMI_STATIC int RlmtUpdate( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + SK_EVPARA EventParam; + + + /* Was the module already updated during the current PNMI call? */ + if (pAC->Pnmi.RlmtUpdatedFlag > 0) { + + return (SK_PNMI_ERR_OK); + } + + /* Send an synchronuous update event to the module */ + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + EventParam.Para32[0] = NetIndex; + EventParam.Para32[1] = (SK_U32)-1; + if (SkRlmtEvent(pAC, IoC, SK_RLMT_STATS_UPDATE, EventParam) > 0) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048, + SK_PNMI_ERR048MSG); + + return (SK_PNMI_ERR_GENERAL); + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * MacUpdate - Force the XMAC to output the current statistic + * + * Description: + * The XMAC holds its statistic internally. To obtain the current + * values we send a command so that the statistic data will + * be written to apredefined memory area on the adapter. + * + * Returns: + * SK_PNMI_ERR_OK Task successfully performed. + * SK_PNMI_ERR_GENERAL Something went wrong. + */ +PNMI_STATIC int MacUpdate( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +unsigned int FirstMac, /* Index of the first Mac to be updated */ +unsigned int LastMac) /* Index of the last Mac to be updated */ +{ + unsigned int MacIndex; + + /* + * Were the statistics already updated during the + * current PNMI call? + */ + if (pAC->Pnmi.MacUpdatedFlag > 0) { + + return (SK_PNMI_ERR_OK); + } + + /* Send an update command to all MACs specified */ + for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) { + + /* + * 2002-09-13 pweber: Freeze the current sw counters. + * (That should be done as close as + * possible to the update of the + * hw counters) + */ + if (pAC->GIni.GIMacType == SK_MAC_XMAC) { + pAC->Pnmi.BufPort[MacIndex] = pAC->Pnmi.Port[MacIndex]; + } + + /* 2002-09-13 pweber: Update the hw counter */ + if (pAC->GIni.GIFunc.pFnMacUpdateStats(pAC, IoC, MacIndex) != 0) { + + return (SK_PNMI_ERR_GENERAL); + } + } + + return (SK_PNMI_ERR_OK); +} + +/***************************************************************************** + * + * GetStatVal - Retrieve an XMAC statistic counter + * + * Description: + * Retrieves the statistic counter of a virtual or physical port. The + * virtual port is identified by the index 0. It consists of all + * currently active ports. To obtain the counter value for this port + * we must add the statistic counter of all active ports. To grant + * continuous counter values for the virtual port even when port + * switches occur we must additionally add a delta value, which was + * calculated during a SK_PNMI_EVT_RLMT_ACTIVE_UP event. + * + * Returns: + * Requested statistic value + */ +PNMI_STATIC SK_U64 GetStatVal( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +unsigned int LogPortIndex, /* Index of the logical Port to be processed */ +unsigned int StatIndex, /* Index to statistic value */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + unsigned int PhysPortIndex; + unsigned int PhysPortMax; + SK_U64 Val = 0; + + + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */ + + PhysPortIndex = NetIndex; + Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex); + } + else { /* Single Net mode */ + + if (LogPortIndex == 0) { + + PhysPortMax = pAC->GIni.GIMacsFound; + + /* Add counter of all active ports */ + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; + PhysPortIndex ++) { + + if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) { + + Val += GetPhysStatVal(pAC, IoC, PhysPortIndex, + StatIndex); + } + } + + /* Correct value because of port switches */ + Val += pAC->Pnmi.VirtualCounterOffset[StatIndex]; + } + else { + /* Get counter value of physical port */ + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex); + Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex); + } + } + return (Val); +} + +/***************************************************************************** + * + * GetPhysStatVal - Get counter value for physical port + * + * Description: + * Builds a 64bit counter value. Except for the octet counters + * the lower 32bit are counted in hardware and the upper 32bit + * in software by monitoring counter overflow interrupts in the + * event handler. To grant continous counter values during XMAC + * resets (caused by a workaround) we must add a delta value. + * The delta was calculated in the event handler when a + * SK_PNMI_EVT_XMAC_RESET was received. + * + * Returns: + * Counter value + */ +PNMI_STATIC SK_U64 GetPhysStatVal( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +unsigned int PhysPortIndex, /* Index of the logical Port to be processed */ +unsigned int StatIndex) /* Index to statistic value */ +{ + SK_U64 Val = 0; + SK_U32 LowVal = 0; + SK_U32 HighVal = 0; + SK_U16 Word; + int MacType; + + SK_PNMI_PORT *pPnmiPrt; + SK_GEMACFUNC *pFnMac; + + MacType = pAC->GIni.GIMacType; + + /* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */ + if (pAC->GIni.GIMacType == SK_MAC_XMAC) { + pPnmiPrt = &pAC->Pnmi.BufPort[PhysPortIndex]; + } + else { + pPnmiPrt = &pAC->Pnmi.Port[PhysPortIndex]; + } + + pFnMac = &pAC->GIni.GIFunc; + + switch (StatIndex) { + case SK_PNMI_HTX: + case SK_PNMI_HRX: + /* Not supported by GMAC */ + if (MacType == SK_MAC_GMAC) { + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HTX_OCTET: + case SK_PNMI_HRX_OCTET: + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &HighVal); + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex + 1][MacType].Reg, + &LowVal); + break; + + case SK_PNMI_HTX_BURST: + case SK_PNMI_HTX_EXCESS_DEF: + case SK_PNMI_HTX_CARRIER: + /* Not supported by GMAC */ + if (MacType == SK_MAC_GMAC) { + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HTX_MACC: + /* GMAC only supports PAUSE MAC control frames */ + if (MacType == SK_MAC_GMAC) { + Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, SK_PNMI_HTX_PMACC); + + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HTX_COL: + case SK_PNMI_HRX_UNDERSIZE: + /* Not supported by XMAC */ + if (MacType == SK_MAC_XMAC) { + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + + case SK_PNMI_HTX_DEFFERAL: + /* Not supported by GMAC */ + if (MacType == SK_MAC_GMAC) { + return (Val); + } + + /* + * XMAC counts frames with deferred transmission + * even in full-duplex mode. + * + * In full-duplex mode the counter remains constant! + */ + if ((pAC->GIni.GP[PhysPortIndex].PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) || + (pAC->GIni.GP[PhysPortIndex].PLinkModeStatus == SK_LMODE_STAT_FULL)) { + + LowVal = 0; + HighVal = 0; + } + else { + /* Otherwise get contents of hardware register. */ + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[SK_PNMI_HTX_DEFFERAL][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + } + break; + + case SK_PNMI_HRX_BADOCTET: + /* Not supported by XMAC */ + if (MacType == SK_MAC_XMAC) { + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &HighVal); + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex + 1][MacType].Reg, + &LowVal); + break; + + case SK_PNMI_HTX_OCTETLOW: + case SK_PNMI_HRX_OCTETLOW: + case SK_PNMI_HRX_BADOCTETLOW: + return (Val); + + case SK_PNMI_HRX_LONGFRAMES: + /* For XMAC the SW counter is managed by PNMI */ + if (MacType == SK_MAC_XMAC) { + return (pPnmiPrt->StatRxLongFrameCts); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HRX_TOO_LONG: + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + + Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal); + + switch (MacType) { + case SK_MAC_GMAC: + /* For GMAC the SW counter is additionally managed by PNMI */ + Val += pPnmiPrt->StatRxFrameTooLongCts; + break; + + case SK_MAC_XMAC: + /* + * Frames longer than IEEE 802.3 frame max size are counted + * by XMAC in frame_too_long counter even reception of long + * frames was enabled and the frame was correct. + * So correct the value by subtracting RxLongFrame counter. + */ + Val -= pPnmiPrt->StatRxLongFrameCts; + break; + + default: + break; + } + + LowVal = (SK_U32)Val; + HighVal = (SK_U32)(Val >> 32); + break; + + case SK_PNMI_HRX_SHORTS: + /* Not supported by GMAC */ + if (MacType == SK_MAC_GMAC) { + /* GM_RXE_FRAG?? */ + return (Val); + } + + /* + * XMAC counts short frame errors even if link down (#10620) + * + * If link-down the counter remains constant + */ + if (pAC->GIni.GP[PhysPortIndex].PLinkModeStatus != SK_LMODE_STAT_UNKNOWN) { + + /* Otherwise get incremental difference */ + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + + Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal); + Val -= pPnmiPrt->RxShortZeroMark; + + LowVal = (SK_U32)Val; + HighVal = (SK_U32)(Val >> 32); + } + break; + + case SK_PNMI_HRX_MACC: + case SK_PNMI_HRX_MACC_UNKWN: + case SK_PNMI_HRX_BURST: + case SK_PNMI_HRX_MISSED: + case SK_PNMI_HRX_FRAMING: + case SK_PNMI_HRX_CARRIER: + case SK_PNMI_HRX_IRLENGTH: + case SK_PNMI_HRX_SYMBOL: + case SK_PNMI_HRX_CEXT: + /* Not supported by GMAC */ + if (MacType == SK_MAC_GMAC) { + /* GM_RXE_FRAG?? */ + return (Val); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + case SK_PNMI_HRX_PMACC_ERR: + /* For GMAC the SW counter is managed by PNMI */ + if (MacType == SK_MAC_GMAC) { + return (pPnmiPrt->StatRxPMaccErr); + } + + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + + /* SW counter managed by PNMI */ + case SK_PNMI_HTX_SYNC: + LowVal = (SK_U32)pPnmiPrt->StatSyncCts; + HighVal = (SK_U32)(pPnmiPrt->StatSyncCts >> 32); + break; + + /* SW counter managed by PNMI */ + case SK_PNMI_HTX_SYNC_OCTET: + LowVal = (SK_U32)pPnmiPrt->StatSyncOctetsCts; + HighVal = (SK_U32)(pPnmiPrt->StatSyncOctetsCts >> 32); + break; + + case SK_PNMI_HRX_FCS: + /* + * Broadcom filters fcs errors and counts it in + * Receive Error Counter register + */ + if (pAC->GIni.GP[PhysPortIndex].PhyType == SK_PHY_BCOM) { + /* do not read while not initialized (PHY_READ hangs!)*/ + if (pAC->GIni.GP[PhysPortIndex].PState) { + PHY_READ(IoC, &pAC->GIni.GP[PhysPortIndex], + PhysPortIndex, PHY_BCOM_RE_CTR, + &Word); + + LowVal = Word; + } + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + } + else { + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + } + break; + + default: + (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex, + StatAddr[StatIndex][MacType].Reg, + &LowVal); + HighVal = pPnmiPrt->CounterHigh[StatIndex]; + break; + } + + Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal); + + /* Correct value because of possible XMAC reset. XMAC Errata #2 */ + Val += pPnmiPrt->CounterOffset[StatIndex]; + + return (Val); +} + +/***************************************************************************** + * + * ResetCounter - Set all counters and timestamps to zero + * + * Description: + * Notifies other common modules which store statistic data to + * reset their counters and finally reset our own counters. + * + * Returns: + * Nothing + */ +PNMI_STATIC void ResetCounter( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +SK_U32 NetIndex) +{ + unsigned int PhysPortIndex; + SK_EVPARA EventParam; + + + SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam)); + + /* Notify sensor module */ + SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_CLEAR, EventParam); + + /* Notify RLMT module */ + EventParam.Para32[0] = NetIndex; + EventParam.Para32[1] = (SK_U32)-1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STATS_CLEAR, EventParam); + EventParam.Para32[1] = 0; + + /* Notify SIRQ module */ + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_CLEAR_STAT, EventParam); + + /* Notify CSUM module */ +#ifdef SK_USE_CSUM + EventParam.Para32[0] = NetIndex; + EventParam.Para32[1] = (SK_U32)-1; + SkEventQueue(pAC, SKGE_CSUM, SK_CSUM_EVENT_CLEAR_PROTO_STATS, + EventParam); +#endif + + /* Clear XMAC statistic */ + for (PhysPortIndex = 0; PhysPortIndex < + (unsigned int)pAC->GIni.GIMacsFound; PhysPortIndex ++) { + + (void)pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PhysPortIndex); + + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].CounterHigh, + 0, sizeof(pAC->Pnmi.Port[PhysPortIndex].CounterHigh)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex]. + CounterOffset, 0, sizeof(pAC->Pnmi.Port[ + PhysPortIndex].CounterOffset)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].StatSyncCts, + 0, sizeof(pAC->Pnmi.Port[PhysPortIndex].StatSyncCts)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex]. + StatSyncOctetsCts, 0, sizeof(pAC->Pnmi.Port[ + PhysPortIndex].StatSyncOctetsCts)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex]. + StatRxLongFrameCts, 0, sizeof(pAC->Pnmi.Port[ + PhysPortIndex].StatRxLongFrameCts)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex]. + StatRxFrameTooLongCts, 0, sizeof(pAC->Pnmi.Port[ + PhysPortIndex].StatRxFrameTooLongCts)); + SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex]. + StatRxPMaccErr, 0, sizeof(pAC->Pnmi.Port[ + PhysPortIndex].StatRxPMaccErr)); + } + + /* + * Clear local statistics + */ + SK_MEMSET((char *)&pAC->Pnmi.VirtualCounterOffset, 0, + sizeof(pAC->Pnmi.VirtualCounterOffset)); + pAC->Pnmi.RlmtChangeCts = 0; + pAC->Pnmi.RlmtChangeTime = 0; + SK_MEMSET((char *)&pAC->Pnmi.RlmtChangeEstimate.EstValue[0], 0, + sizeof(pAC->Pnmi.RlmtChangeEstimate.EstValue)); + pAC->Pnmi.RlmtChangeEstimate.EstValueIndex = 0; + pAC->Pnmi.RlmtChangeEstimate.Estimate = 0; + pAC->Pnmi.Port[NetIndex].TxSwQueueMax = 0; + pAC->Pnmi.Port[NetIndex].TxRetryCts = 0; + pAC->Pnmi.Port[NetIndex].RxIntrCts = 0; + pAC->Pnmi.Port[NetIndex].TxIntrCts = 0; + pAC->Pnmi.Port[NetIndex].RxNoBufCts = 0; + pAC->Pnmi.Port[NetIndex].TxNoBufCts = 0; + pAC->Pnmi.Port[NetIndex].TxUsedDescrNo = 0; + pAC->Pnmi.Port[NetIndex].RxDeliveredCts = 0; + pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts = 0; + pAC->Pnmi.Port[NetIndex].ErrRecoveryCts = 0; +} + +/***************************************************************************** + * + * GetTrapEntry - Get an entry in the trap buffer + * + * Description: + * The trap buffer stores various events. A user application somehow + * gets notified that an event occured and retrieves the trap buffer + * contens (or simply polls the buffer). The buffer is organized as + * a ring which stores the newest traps at the beginning. The oldest + * traps are overwritten by the newest ones. Each trap entry has a + * unique number, so that applications may detect new trap entries. + * + * Returns: + * A pointer to the trap entry + */ +PNMI_STATIC char* GetTrapEntry( +SK_AC *pAC, /* Pointer to adapter context */ +SK_U32 TrapId, /* SNMP ID of the trap */ +unsigned int Size) /* Space needed for trap entry */ +{ + unsigned int BufPad = pAC->Pnmi.TrapBufPad; + unsigned int BufFree = pAC->Pnmi.TrapBufFree; + unsigned int Beg = pAC->Pnmi.TrapQueueBeg; + unsigned int End = pAC->Pnmi.TrapQueueEnd; + char *pBuf = &pAC->Pnmi.TrapBuf[0]; + int Wrap; + unsigned int NeededSpace; + unsigned int EntrySize; + SK_U32 Val32; + SK_U64 Val64; + + + /* Last byte of entry will get a copy of the entry length */ + Size ++; + + /* + * Calculate needed buffer space */ + if (Beg >= Size) { + + NeededSpace = Size; + Wrap = SK_FALSE; + } + else { + NeededSpace = Beg + Size; + Wrap = SK_TRUE; + } + + /* + * Check if enough buffer space is provided. Otherwise + * free some entries. Leave one byte space between begin + * and end of buffer to make it possible to detect whether + * the buffer is full or empty + */ + while (BufFree < NeededSpace + 1) { + + if (End == 0) { + + End = SK_PNMI_TRAP_QUEUE_LEN; + } + + EntrySize = (unsigned int)*((unsigned char *)pBuf + End - 1); + BufFree += EntrySize; + End -= EntrySize; +#ifdef DEBUG + SK_MEMSET(pBuf + End, (char)(-1), EntrySize); +#endif + if (End == BufPad) { +#ifdef DEBUG + SK_MEMSET(pBuf, (char)(-1), End); +#endif + BufFree += End; + End = 0; + BufPad = 0; + } + } + + /* + * Insert new entry as first entry. Newest entries are + * stored at the beginning of the queue. + */ + if (Wrap) { + + BufPad = Beg; + Beg = SK_PNMI_TRAP_QUEUE_LEN - Size; + } + else { + Beg = Beg - Size; + } + BufFree -= NeededSpace; + + /* Save the current offsets */ + pAC->Pnmi.TrapQueueBeg = Beg; + pAC->Pnmi.TrapQueueEnd = End; + pAC->Pnmi.TrapBufPad = BufPad; + pAC->Pnmi.TrapBufFree = BufFree; + + /* Initialize the trap entry */ + *(pBuf + Beg + Size - 1) = (char)Size; + *(pBuf + Beg) = (char)Size; + Val32 = (pAC->Pnmi.TrapUnique) ++; + SK_PNMI_STORE_U32(pBuf + Beg + 1, Val32); + SK_PNMI_STORE_U32(pBuf + Beg + 1 + sizeof(SK_U32), TrapId); + Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC)); + SK_PNMI_STORE_U64(pBuf + Beg + 1 + 2 * sizeof(SK_U32), Val64); + + return (pBuf + Beg); +} + +/***************************************************************************** + * + * CopyTrapQueue - Copies the trap buffer for the TRAP OID + * + * Description: + * On a query of the TRAP OID the trap buffer contents will be + * copied continuously to the request buffer, which must be large + * enough. No length check is performed. + * + * Returns: + * Nothing + */ +PNMI_STATIC void CopyTrapQueue( +SK_AC *pAC, /* Pointer to adapter context */ +char *pDstBuf) /* Buffer to which the queued traps will be copied */ +{ + unsigned int BufPad = pAC->Pnmi.TrapBufPad; + unsigned int Trap = pAC->Pnmi.TrapQueueBeg; + unsigned int End = pAC->Pnmi.TrapQueueEnd; + char *pBuf = &pAC->Pnmi.TrapBuf[0]; + unsigned int Len; + unsigned int DstOff = 0; + + + while (Trap != End) { + + Len = (unsigned int)*(pBuf + Trap); + + /* + * Last byte containing a copy of the length will + * not be copied. + */ + *(pDstBuf + DstOff) = (char)(Len - 1); + SK_MEMCPY(pDstBuf + DstOff + 1, pBuf + Trap + 1, Len - 2); + DstOff += Len - 1; + + Trap += Len; + if (Trap == SK_PNMI_TRAP_QUEUE_LEN) { + + Trap = BufPad; + } + } +} + +/***************************************************************************** + * + * GetTrapQueueLen - Get the length of the trap buffer + * + * Description: + * Evaluates the number of currently stored traps and the needed + * buffer size to retrieve them. + * + * Returns: + * Nothing + */ +PNMI_STATIC void GetTrapQueueLen( +SK_AC *pAC, /* Pointer to adapter context */ +unsigned int *pLen, /* Length in Bytes of all queued traps */ +unsigned int *pEntries) /* Returns number of trapes stored in queue */ +{ + unsigned int BufPad = pAC->Pnmi.TrapBufPad; + unsigned int Trap = pAC->Pnmi.TrapQueueBeg; + unsigned int End = pAC->Pnmi.TrapQueueEnd; + char *pBuf = &pAC->Pnmi.TrapBuf[0]; + unsigned int Len; + unsigned int Entries = 0; + unsigned int TotalLen = 0; + + + while (Trap != End) { + + Len = (unsigned int)*(pBuf + Trap); + TotalLen += Len - 1; + Entries ++; + + Trap += Len; + if (Trap == SK_PNMI_TRAP_QUEUE_LEN) { + + Trap = BufPad; + } + } + + *pEntries = Entries; + *pLen = TotalLen; +} + +/***************************************************************************** + * + * QueueSimpleTrap - Store a simple trap to the trap buffer + * + * Description: + * A simple trap is a trap with now additional data. It consists + * simply of a trap code. + * + * Returns: + * Nothing + */ +PNMI_STATIC void QueueSimpleTrap( +SK_AC *pAC, /* Pointer to adapter context */ +SK_U32 TrapId) /* Type of sensor trap */ +{ + GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_SIMPLE_LEN); +} + +/***************************************************************************** + * + * QueueSensorTrap - Stores a sensor trap in the trap buffer + * + * Description: + * Gets an entry in the trap buffer and fills it with sensor related + * data. + * + * Returns: + * Nothing + */ +PNMI_STATIC void QueueSensorTrap( +SK_AC *pAC, /* Pointer to adapter context */ +SK_U32 TrapId, /* Type of sensor trap */ +unsigned int SensorIndex) /* Index of sensor which caused the trap */ +{ + char *pBuf; + unsigned int Offset; + unsigned int DescrLen; + SK_U32 Val32; + + + /* Get trap buffer entry */ + DescrLen = SK_STRLEN(pAC->I2c.SenTable[SensorIndex].SenDesc); + pBuf = GetTrapEntry(pAC, TrapId, + SK_PNMI_TRAP_SENSOR_LEN_BASE + DescrLen); + Offset = SK_PNMI_TRAP_SIMPLE_LEN; + + /* Store additionally sensor trap related data */ + Val32 = OID_SKGE_SENSOR_INDEX; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + *(pBuf + Offset + 4) = 4; + Val32 = (SK_U32)SensorIndex; + SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32); + Offset += 9; + + Val32 = (SK_U32)OID_SKGE_SENSOR_DESCR; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + *(pBuf + Offset + 4) = (char)DescrLen; + SK_MEMCPY(pBuf + Offset + 5, pAC->I2c.SenTable[SensorIndex].SenDesc, + DescrLen); + Offset += DescrLen + 5; + + Val32 = OID_SKGE_SENSOR_TYPE; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + *(pBuf + Offset + 4) = 1; + *(pBuf + Offset + 5) = (char)pAC->I2c.SenTable[SensorIndex].SenType; + Offset += 6; + + Val32 = OID_SKGE_SENSOR_VALUE; + SK_PNMI_STORE_U32(pBuf + Offset, Val32); + *(pBuf + Offset + 4) = 4; + Val32 = (SK_U32)pAC->I2c.SenTable[SensorIndex].SenValue; + SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32); +} + +/***************************************************************************** + * + * QueueRlmtNewMacTrap - Store a port switch trap in the trap buffer + * + * Description: + * Nothing further to explain. + * + * Returns: + * Nothing + */ +PNMI_STATIC void QueueRlmtNewMacTrap( +SK_AC *pAC, /* Pointer to adapter context */ +unsigned int ActiveMac) /* Index (0..n) of the currently active port */ +{ + char *pBuf; + SK_U32 Val32; + + + pBuf = GetTrapEntry(pAC, OID_SKGE_TRAP_RLMT_CHANGE_PORT, + SK_PNMI_TRAP_RLMT_CHANGE_LEN); + + Val32 = OID_SKGE_RLMT_PORT_ACTIVE; + SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32); + *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1; + *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)ActiveMac; +} + +/***************************************************************************** + * + * QueueRlmtPortTrap - Store port related RLMT trap to trap buffer + * + * Description: + * Nothing further to explain. + * + * Returns: + * Nothing + */ +PNMI_STATIC void QueueRlmtPortTrap( +SK_AC *pAC, /* Pointer to adapter context */ +SK_U32 TrapId, /* Type of RLMT port trap */ +unsigned int PortIndex) /* Index of the port, which changed its state */ +{ + char *pBuf; + SK_U32 Val32; + + + pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_RLMT_PORT_LEN); + + Val32 = OID_SKGE_RLMT_PORT_INDEX; + SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32); + *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1; + *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)PortIndex; +} + +/***************************************************************************** + * + * CopyMac - Copies a MAC address + * + * Description: + * Nothing further to explain. + * + * Returns: + * Nothing + */ +PNMI_STATIC void CopyMac( +char *pDst, /* Pointer to destination buffer */ +SK_MAC_ADDR *pMac) /* Pointer of Source */ +{ + int i; + + + for (i = 0; i < sizeof(SK_MAC_ADDR); i ++) { + + *(pDst + i) = pMac->a[i]; + } +} + + +#ifdef SK_POWER_MGMT +/***************************************************************************** + * + * PowerManagement - OID handler function of PowerManagement OIDs + * + * Description: + * The code is simple. No description necessary. + * + * Returns: + * SK_PNMI_ERR_OK The request was successfully performed. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter. + */ + +PNMI_STATIC int PowerManagement( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which to mgmt data will be retrieved */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */ +{ + + SK_U32 RetCode = SK_PNMI_ERR_GENERAL; + + /* + * Check instance. We only handle single instance variables + */ + if (Instance != (SK_U32)(-1) && Instance != 1) { + + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + /* + * Perform action + */ + if (Action == SK_PNMI_GET) { + + /* + * Check length + */ + switch (Id) { + + case OID_PNP_CAPABILITIES: + if (*pLen < sizeof(SK_PNP_CAPABILITIES)) { + + *pLen = sizeof(SK_PNP_CAPABILITIES); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_PNP_QUERY_POWER: + case OID_PNP_ENABLE_WAKE_UP: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_PNP_SET_POWER: + case OID_PNP_ADD_WAKE_UP_PATTERN: + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR040, + SK_PNMI_ERR040MSG); + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Get value + */ + switch (Id) { + + case OID_PNP_CAPABILITIES: + RetCode = SkPowerQueryPnPCapabilities(pAC, IoC, pBuf, pLen); + break; + + case OID_PNP_QUERY_POWER: + /* The Windows DDK describes: An OID_PNP_QUERY_POWER requests + the miniport to indicate whether it can transition its NIC + to the low-power state. + A miniport driver must always return NDIS_STATUS_SUCCESS + to a query of OID_PNP_QUERY_POWER. */ + RetCode = SK_PNMI_ERR_OK; + break; + + /* NDIS handles these OIDs as write-only. + * So in case of get action the buffer with written length = 0 + * is returned + */ + case OID_PNP_SET_POWER: + case OID_PNP_ADD_WAKE_UP_PATTERN: + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + *pLen = 0; + RetCode = SK_PNMI_ERR_OK; + break; + + case OID_PNP_ENABLE_WAKE_UP: + RetCode = SkPowerGetEnableWakeUp(pAC, IoC, pBuf, pLen); + break; + + default: + RetCode = SK_PNMI_ERR_GENERAL; + break; + } + + return (RetCode); + } + + /* + * From here SET or PRESET action. Check if the passed + * buffer length is plausible. + */ + switch (Id) { + case OID_PNP_SET_POWER: + case OID_PNP_ENABLE_WAKE_UP: + if (*pLen < sizeof(SK_U32)) { + + *pLen = sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + if (*pLen != sizeof(SK_U32)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + break; + + case OID_PNP_ADD_WAKE_UP_PATTERN: + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + if (*pLen < sizeof(SK_PM_PACKET_PATTERN)) { + + *pLen = 0; + return (SK_PNMI_ERR_BAD_VALUE); + } + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_READ_ONLY); + } + + /* + * Perform preset or set + */ + + /* POWER module does not support PRESET action */ + if (Action == SK_PNMI_PRESET) { + return (SK_PNMI_ERR_OK); + } + + switch (Id) { + case OID_PNP_SET_POWER: + RetCode = SkPowerSetPower(pAC, IoC, pBuf, pLen); + break; + + case OID_PNP_ADD_WAKE_UP_PATTERN: + RetCode = SkPowerAddWakeUpPattern(pAC, IoC, pBuf, pLen); + break; + + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, pBuf, pLen); + break; + + case OID_PNP_ENABLE_WAKE_UP: + RetCode = SkPowerSetEnableWakeUp(pAC, IoC, pBuf, pLen); + break; + + default: + RetCode = SK_PNMI_ERR_GENERAL; + } + + return (RetCode); +} +#endif /* SK_POWER_MGMT */ + + +/***************************************************************************** + * + * Vct - OID handler function of OIDs + * + * Description: + * The code is simple. No description necessary. + * + * Returns: + * SK_PNMI_ERR_OK The request was performed successfully. + * SK_PNMI_ERR_GENERAL A general severe internal error occured. + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain + * the correct data (e.g. a 32bit value is + * needed, but a 16 bit value was passed). + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't + * exist (e.g. port instance 3 on a two port + * adapter). + * SK_PNMI_ERR_READ_ONLY Only the Get action is allowed. + * + */ + +PNMI_STATIC int Vct( +SK_AC *pAC, /* Pointer to adapter context */ +SK_IOC IoC, /* IO context handle */ +int Action, /* Get/PreSet/Set action */ +SK_U32 Id, /* Object ID that is to be processed */ +char *pBuf, /* Buffer to which the mgmt data will be copied */ +unsigned int *pLen, /* On call: buffer length. On return: used buffer */ +SK_U32 Instance, /* Instance (-1,2..n) that is to be queried */ +unsigned int TableIndex, /* Index to the Id table */ +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */ +{ + SK_GEPORT *pPrt; + SK_PNMI_VCT *pVctBackupData; + SK_U32 LogPortMax; + SK_U32 PhysPortMax; + SK_U32 PhysPortIndex; + SK_U32 Limit; + SK_U32 Offset; + SK_BOOL Link; + SK_U32 RetCode = SK_PNMI_ERR_GENERAL; + int i; + SK_EVPARA Para; + SK_U32 CableLength; + + /* + * Calculate the port indexes from the instance. + */ + PhysPortMax = pAC->GIni.GIMacsFound; + LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax); + + /* Dual net mode? */ + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + LogPortMax--; + } + + if ((Instance != (SK_U32) (-1))) { + /* Check instance range. */ + if ((Instance < 2) || (Instance > LogPortMax)) { + *pLen = 0; + return (SK_PNMI_ERR_UNKNOWN_INST); + } + + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { + PhysPortIndex = NetIndex; + } + else { + PhysPortIndex = Instance - 2; + } + Limit = PhysPortIndex + 1; + } + else { /* + * Instance == (SK_U32) (-1), get all Instances of that OID. + * + * Not implemented yet. May be used in future releases. + */ + PhysPortIndex = 0; + Limit = PhysPortMax; + } + + pPrt = &pAC->GIni.GP[PhysPortIndex]; + if (pPrt->PHWLinkUp) { + Link = SK_TRUE; + } + else { + Link = SK_FALSE; + } + + /* + * Check MAC type. + */ + if (pPrt->PhyType != SK_PHY_MARV_COPPER) { + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* Initialize backup data pointer. */ + pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex]; + + /* + * Check action type. + */ + if (Action == SK_PNMI_GET) { + /* + * Check length. + */ + switch (Id) { + + case OID_SKGE_VCT_GET: + if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT)) { + *pLen = (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + case OID_SKGE_VCT_STATUS: + if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U8)) { + *pLen = (Limit - PhysPortIndex) * sizeof(SK_U8); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Get value. + */ + Offset = 0; + for (; PhysPortIndex < Limit; PhysPortIndex++) { + switch (Id) { + + case OID_SKGE_VCT_GET: + if ((Link == SK_FALSE) && + (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING)) { + RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE); + if (RetCode == 0) { + pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING; + pAC->Pnmi.VctStatus[PhysPortIndex] |= + (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE); + + /* Copy results for later use to PNMI struct. */ + for (i = 0; i < 4; i++) { + if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) { + if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] < 0xff)) { + pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH; + } + } + if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] != 0xff)) { + CableLength = 1000 * (((175 * pPrt->PMdiPairLen[i]) / 210) - 28); + } + else { + CableLength = 0; + } + pVctBackupData->PMdiPairLen[i] = CableLength; + pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i]; + } + + Para.Para32[0] = PhysPortIndex; + Para.Para32[1] = -1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para); + SkEventDispatcher(pAC, IoC); + } + else { + ; /* VCT test is running. */ + } + } + + /* Get all results. */ + CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex); + Offset += sizeof(SK_U8); + *(pBuf + Offset) = pPrt->PCableLen; + Offset += sizeof(SK_U8); + for (i = 0; i < 4; i++) { + SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->PMdiPairLen[i]); + Offset += sizeof(SK_U32); + } + for (i = 0; i < 4; i++) { + *(pBuf + Offset) = pVctBackupData->PMdiPairSts[i]; + Offset += sizeof(SK_U8); + } + + RetCode = SK_PNMI_ERR_OK; + break; + + case OID_SKGE_VCT_STATUS: + CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex); + Offset += sizeof(SK_U8); + RetCode = SK_PNMI_ERR_OK; + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } /* for */ + *pLen = Offset; + return (RetCode); + + } /* if SK_PNMI_GET */ + + /* + * From here SET or PRESET action. Check if the passed + * buffer length is plausible. + */ + + /* + * Check length. + */ + switch (Id) { + case OID_SKGE_VCT_SET: + if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) { + *pLen = (Limit - PhysPortIndex) * sizeof(SK_U32); + return (SK_PNMI_ERR_TOO_SHORT); + } + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + + /* + * Perform preset or set. + */ + + /* VCT does not support PRESET action. */ + if (Action == SK_PNMI_PRESET) { + return (SK_PNMI_ERR_OK); + } + + Offset = 0; + for (; PhysPortIndex < Limit; PhysPortIndex++) { + switch (Id) { + case OID_SKGE_VCT_SET: /* Start VCT test. */ + if (Link == SK_FALSE) { + SkGeStopPort(pAC, IoC, PhysPortIndex, SK_STOP_ALL, SK_SOFT_RST); + + RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_TRUE); + if (RetCode == 0) { /* RetCode: 0 => Start! */ + pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_PENDING; + pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_NEW_VCT_DATA; + pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_LINK; + + /* + * Start VCT timer counter. + */ + SK_MEMSET((char *) &Para, 0, sizeof(Para)); + Para.Para32[0] = PhysPortIndex; + Para.Para32[1] = -1; + SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer, + 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para); + SK_PNMI_STORE_U32((pBuf + Offset), RetCode); + RetCode = SK_PNMI_ERR_OK; + } + else { /* RetCode: 2 => Running! */ + SK_PNMI_STORE_U32((pBuf + Offset), RetCode); + RetCode = SK_PNMI_ERR_OK; + } + } + else { /* RetCode: 4 => Link! */ + RetCode = 4; + SK_PNMI_STORE_U32((pBuf + Offset), RetCode); + RetCode = SK_PNMI_ERR_OK; + } + Offset += sizeof(SK_U32); + break; + + default: + *pLen = 0; + return (SK_PNMI_ERR_GENERAL); + } + } /* for */ + *pLen = Offset; + return (RetCode); + +} /* Vct */ + + +PNMI_STATIC void CheckVctStatus( +SK_AC *pAC, +SK_IOC IoC, +char *pBuf, +SK_U32 Offset, +SK_U32 PhysPortIndex) +{ + SK_GEPORT *pPrt; + SK_PNMI_VCT *pVctData; + SK_U32 RetCode; + SK_U8 LinkSpeedUsed; + + pPrt = &pAC->GIni.GP[PhysPortIndex]; + + pVctData = (SK_PNMI_VCT *) (pBuf + Offset); + pVctData->VctStatus = SK_PNMI_VCT_NONE; + + if (!pPrt->PHWLinkUp) { + + /* Was a VCT test ever made before? */ + if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) { + if ((pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_LINK)) { + pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA; + } + else { + pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA; + } + } + + /* Check VCT test status. */ + RetCode = SkGmCableDiagStatus(pAC,IoC, PhysPortIndex, SK_FALSE); + if (RetCode == 2) { /* VCT test is running. */ + pVctData->VctStatus |= SK_PNMI_VCT_RUNNING; + } + else { /* VCT data was copied to pAC here. Check PENDING state. */ + if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) { + pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA; + } + } + + if (pPrt->PCableLen != 0xff) { /* Old DSP value. */ + pVctData->VctStatus |= SK_PNMI_VCT_OLD_DSP_DATA; + } + } + else { + + /* Was a VCT test ever made before? */ + if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) { + pVctData->VctStatus &= ~SK_PNMI_VCT_NEW_VCT_DATA; + pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA; + } + + /* DSP only valid in 100/1000 modes. */ + LinkSpeedUsed = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed; + if (LinkSpeedUsed != SK_LSPEED_STAT_10MBPS) { + pVctData->VctStatus |= SK_PNMI_VCT_NEW_DSP_DATA; + } + } + +} /* CheckVctStatus */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skgesirq.c b/drivers/sk98lin/skgesirq.c new file mode 100644 index 000000000..e5a4f7ec1 --- /dev/null +++ b/drivers/sk98lin/skgesirq.c @@ -0,0 +1,2417 @@ +/****************************************************************************** + * + * Name: skgesirq.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.83 $ + * Date: $Date: 2003/02/05 15:10:59 $ + * Purpose: Special IRQ module + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skgesirq.c,v $ + * Revision 1.83 2003/02/05 15:10:59 rschmidt + * Fixed setting of PLinkSpeedUsed in SkHWLinkUp() when + * auto-negotiation is disabled. + * Editorial changes. + * + * Revision 1.82 2003/01/29 13:34:33 rschmidt + * Added some typecasts to avoid compiler warnings. + * + * Revision 1.81 2002/12/05 10:49:51 rschmidt + * Fixed missing Link Down Event for fiber (Bug Id #10768) + * Added reading of cable length when link is up + * Removed testing of unused error bits in PHY ISR + * Editorial changes. + * + * Revision 1.80 2002/11/12 17:15:21 rschmidt + * Replaced SkPnmiGetVar() by ...MacStatistic() in SkMacParity(). + * Editorial changes. + * + * Revision 1.79 2002/10/14 15:14:51 rschmidt + * Changed clearing of IS_M1_PAR_ERR (MAC 1 Parity Error) in + * SkMacParity() depending on GIChipRev (HW-Bug #8). + * Added error messages for GPHY Auto-Negotiation Error and + * FIFO Overflow/Underrun in SkPhyIsrGmac(). + * Editorial changes. + * + * Revision 1.78 2002/10/10 15:54:29 mkarl + * changes for PLinkSpeedUsed + * + * Revision 1.77 2002/09/12 08:58:51 rwahl + * Retrieve counters needed for XMAC errata workarounds directly because + * PNMI returns corrected counter values (e.g. #10620). + * + * Revision 1.76 2002/08/16 15:21:54 rschmidt + * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis. + * Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros. + * Editorial changes. + * + * Revision 1.75 2002/08/12 13:50:47 rschmidt + * Changed clearing of IS_M1_PAR_ERR (MAC 1 Parity Error) in + * SkMacParity() by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE (HW-Bug #8). + * Added clearing of IS_IRQ_TIST_OV and IS_IRQ_SENSOR in SkGeHwErr(). + * Corrected handling of Link Up and Auto-Negotiation Over for GPHY. + * in SkGePortCheckUpGmac(). + * Editorial changes. + * + * Revision 1.74 2002/08/08 16:17:04 rschmidt + * Added PhyType check for SK_HWEV_SET_ROLE event (copper only) + * Changed Link Up check reading PHY Specific Status (YUKON) + * Editorial changes + * + * Revision 1.73 2002/07/15 18:36:53 rwahl + * Editorial changes. + * + * Revision 1.72 2002/07/15 15:46:26 rschmidt + * Added new event: SK_HWEV_SET_SPEED + * Editorial changes + * + * Revision 1.71 2002/06/10 09:34:19 rschmidt + * Editorial changes + * + * Revision 1.70 2002/06/05 08:29:18 rschmidt + * SkXmRxTxEnable() replaced by SkMacRxTxEnable(). + * Editorial changes. + * + * Revision 1.69 2002/04/25 13:03:49 rschmidt + * Changes for handling YUKON. + * Use of #ifdef OTHER_PHY to eliminate code for unused Phy types. + * Replaced all XMAC-access macros by functions: SkMacRxTxDisable(), + * SkMacIrqDisable(). + * Added handling for GMAC FIFO in SkMacParity(). + * Replaced all SkXm...() functions with SkMac...() to handle also + * YUKON's GMAC. + * Macros for XMAC PHY access PHY_READ(), PHY_WRITE() replaced + * by functions SkXmPhyRead(), SkXmPhyWrite(). + * Disabling all PHY interrupts moved to SkMacIrqDisable(). + * Added handling for GPHY IRQ in SkGeSirqIsr(). + * Removed status parameter from MAC IRQ handler SkMacIrq(). + * Added SkGePortCheckUpGmac(), SkPhyIsrGmac() for GMAC. + * Editorial changes + * + * Revision 1.68 2002/02/26 15:24:53 rwahl + * Fix: no link with manual configuration (#10673). The previous fix for + * #10639 was removed. So for RLMT mode = CLS the RLMT may switch to + * misconfigured port. It should not occur for the other RLMT modes. + * + * Revision 1.67 2001/11/20 09:19:58 rwahl + * Reworked bugfix #10639 (no dependency to RLMT mode). + * + * Revision 1.66 2001/10/26 07:52:53 afischer + * Port switching bug in `check local link` mode + * + * Revision 1.65 2001/02/23 13:41:51 gklug + * fix: PHYS2INST should be used correctly for Dual Net operation + * chg: do no longer work with older PNMI + * + * Revision 1.64 2001/02/15 11:27:04 rassmann + * Working with RLMT v1 if SK_MAX_NETS undefined. + * + * Revision 1.63 2001/02/06 10:44:23 mkunz + * - NetIndex added to interface functions of pnmi V4 with dual net support + * + * Revision 1.62 2001/01/31 15:31:41 gklug + * fix: problem with autosensing an SR8800 switch + * + * Revision 1.61 2000/11/09 11:30:09 rassmann + * WA: Waiting after releasing reset until BCom chip is accessible. + * + * Revision 1.60 2000/10/18 12:37:48 cgoos + * Reinserted the comment for version 1.56. + * + * Revision 1.59 2000/10/18 12:22:20 cgoos + * Added workaround for half duplex hangup. + * + * Revision 1.58 2000/09/28 13:06:04 gklug + * fix: BCom may NOT be touched if XMAC is in RESET state + * + * Revision 1.57 2000/09/08 12:38:39 cgoos + * Added forgotten variable declaration. + * + * Revision 1.56 2000/09/08 08:12:13 cgoos + * Changed handling of parity errors in SkGeHwErr (correct reset of error). + * + * Revision 1.55 2000/06/19 08:36:25 cgoos + * Changed comment. + * + * Revision 1.54 2000/05/22 08:45:57 malthoff + * Fix: #10523 is valid for all BCom PHYs. + * + * Revision 1.53 2000/05/19 10:20:30 cgoos + * Removed Solaris debug output code. + * + * Revision 1.52 2000/05/19 10:19:37 cgoos + * Added PHY state check in HWLinkDown. + * Move PHY interrupt code to IS_EXT_REG case in SkGeSirqIsr. + * + * Revision 1.51 2000/05/18 05:56:20 cgoos + * Fixed typo. + * + * Revision 1.50 2000/05/17 12:49:49 malthoff + * Fixes BCom link bugs (#10523). + * + * Revision 1.49 1999/12/17 11:02:50 gklug + * fix: read PHY_STAT of Broadcom chip more often to assure good status + * + * Revision 1.48 1999/12/06 10:01:17 cgoos + * Added SET function for Role. + * + * Revision 1.47 1999/11/22 13:34:24 cgoos + * Changed license header to GPL. + * + * Revision 1.46 1999/09/16 10:30:07 cgoos + * Removed debugging output statement from Linux. + * + * Revision 1.45 1999/09/16 07:32:55 cgoos + * Fixed dual-port copperfield bug (PHY_READ from resetted port). + * Removed some unused variables. + * + * Revision 1.44 1999/08/03 15:25:04 cgoos + * Removed workaround for disabled interrupts in half duplex mode. + * + * Revision 1.43 1999/08/03 14:27:58 cgoos + * Removed SENSE mode code from SkGePortCheckUpBcom. + * + * Revision 1.42 1999/07/26 09:16:54 cgoos + * Added some typecasts to avoid compiler warnings. + * + * Revision 1.41 1999/05/19 07:28:59 cgoos + * Changes for 1000Base-T. + * + * Revision 1.40 1999/04/08 13:59:39 gklug + * fix: problem with 3Com switches endless RESTARTs + * + * Revision 1.39 1999/03/08 10:10:52 gklug + * fix: AutoSensing did switch to next mode even if LiPa indicated offline + * + * Revision 1.38 1999/03/08 09:49:03 gklug + * fix: Bug using pAC instead of IoC, causing AIX problems + * fix: change compare for Linux compiler bug workaround + * + * Revision 1.37 1999/01/28 14:51:33 gklug + * fix: monitor for autosensing and extra RESETS the RX on wire counters + * + * Revision 1.36 1999/01/22 09:19:55 gklug + * fix: Init DupMode and InitPauseMd are now called in RxTxEnable + * + * Revision 1.35 1998/12/11 15:22:59 gklug + * chg: autosensing: check for receive if manual mode was guessed + * chg: simplified workaround for XMAC errata + * chg: wait additional 100 ms before link goes up. + * chg: autoneg timeout to 600 ms + * chg: restart autoneg even if configured to autonegotiation + * + * Revision 1.34 1998/12/10 10:33:14 gklug + * add: more debug messages + * fix: do a new InitPhy if link went down (AutoSensing problem) + * chg: Check for zero shorts if link is NOT up + * chg: reset Port if link goes down + * chg: wait additional 100 ms when link comes up to check shorts + * fix: dummy read extended autoneg status to prevent link going down immediately + * + * Revision 1.33 1998/12/07 12:18:29 gklug + * add: refinement of autosense mode: take into account the autoneg cap of LiPa + * + * Revision 1.32 1998/12/07 07:11:21 gklug + * fix: compiler warning + * + * Revision 1.31 1998/12/02 09:29:05 gklug + * fix: WA XMAC Errata: FCSCt check was not correct. + * fix: WA XMAC Errata: Prec Counter were NOT updated in case of short checks. + * fix: Clear Stat : now clears the Prev counters of all known Ports + * + * Revision 1.30 1998/12/01 10:54:15 gklug + * dd: workaround for XMAC errata changed. Check RX count and CRC err Count, too. + * + * Revision 1.29 1998/12/01 10:01:53 gklug + * fix: if MAC IRQ occurs during port down, this will be handled correctly + * + * Revision 1.28 1998/11/26 16:22:11 gklug + * fix: bug in autosense if manual modes are used + * + * Revision 1.27 1998/11/26 15:50:06 gklug + * fix: PNMI needs to set PLinkModeConf + * + * Revision 1.26 1998/11/26 14:51:58 gklug + * add: AutoSensing functionalty + * + * Revision 1.25 1998/11/26 07:34:37 gklug + * fix: Init PrevShorts when restarting port due to Link connection + * + * Revision 1.24 1998/11/25 10:57:32 gklug + * fix: remove unreferenced local vars + * + * Revision 1.23 1998/11/25 08:26:40 gklug + * fix: don't do a RESET on a starting or stopping port + * + * Revision 1.22 1998/11/24 13:29:44 gklug + * add: Workaround for MAC parity errata + * + * Revision 1.21 1998/11/18 15:31:06 gklug + * fix: lint bugs + * + * Revision 1.20 1998/11/18 12:58:54 gklug + * fix: use PNMI query instead of hardware access + * + * Revision 1.19 1998/11/18 12:54:55 gklug + * chg: add new workaround for XMAC Errata + * add: short event counter monitoring on active link too + * + * Revision 1.18 1998/11/13 14:27:41 malthoff + * Bug Fix: Packet Arbiter Timeout was not cleared correctly + * for timeout on TX1 and TX2. + * + * Revision 1.17 1998/11/04 07:01:59 cgoos + * Moved HW link poll sequence. + * Added call to SkXmRxTxEnable. + * + * Revision 1.16 1998/11/03 13:46:03 gklug + * add: functionality of SET_LMODE and SET_FLOW_MODE + * fix: send RLMT LinkDown event when Port stop is given with LinkUp + * + * Revision 1.15 1998/11/03 12:56:47 gklug + * fix: Needs more events + * + * Revision 1.14 1998/10/30 07:36:35 gklug + * rmv: unnecessary code + * + * Revision 1.13 1998/10/29 15:21:57 gklug + * add: Poll link feature for activating HW link + * fix: Deactivate HWLink when Port STOP is given + * + * Revision 1.12 1998/10/28 07:38:57 cgoos + * Checking link status at begin of SkHWLinkUp. + * + * Revision 1.11 1998/10/22 09:46:50 gklug + * fix SysKonnectFileId typo + * + * Revision 1.10 1998/10/14 13:57:47 gklug + * add: Port start/stop event + * + * Revision 1.9 1998/10/14 05:48:29 cgoos + * Added definition for Para. + * + * Revision 1.8 1998/10/14 05:40:09 gklug + * add: Hardware Linkup signal used + * + * Revision 1.7 1998/10/09 06:50:20 malthoff + * Remove ID_sccs by SysKonnectFileId. + * + * Revision 1.6 1998/10/08 09:11:49 gklug + * add: clear IRQ commands + * + * Revision 1.5 1998/10/02 14:27:35 cgoos + * Fixed some typos and wrong event names. + * + * Revision 1.4 1998/10/02 06:24:17 gklug + * add: HW error function + * fix: OUT macros + * + * Revision 1.3 1998/10/01 07:03:00 gklug + * add: ISR for the usual interrupt source register + * + * Revision 1.2 1998/09/03 13:50:33 gklug + * add: function prototypes + * + * Revision 1.1 1998/08/27 11:50:21 gklug + * initial revision + * + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +/* + * Special Interrupt handler + * + * The following abstract should show how this module is included + * in the driver path: + * + * In the ISR of the driver the bits for frame transmission complete and + * for receive complete are checked and handled by the driver itself. + * The bits of the slow path mask are checked after that and then the + * entry into the so-called "slow path" is prepared. It is an implementors + * decision whether this is executed directly or just scheduled by + * disabling the mask. In the interrupt service routine some events may be + * generated, so it would be a good idea to call the EventDispatcher + * right after this ISR. + * + * The Interrupt source register of the adapter is NOT read by this module. + * SO if the drivers implementor needs a while loop around the + * slow data paths interrupt bits, he needs to call the SkGeSirqIsr() for + * each loop entered. + * + * However, the MAC Interrupt status registers are read in a while loop. + * + */ + +static const char SysKonnectFileId[] = + "$Id: skgesirq.c,v 1.83 2003/02/05 15:10:59 rschmidt Exp $" ; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/skgepnmi.h" /* PNMI Definitions */ +#include "h/skrlmt.h" /* RLMT Definitions */ +#include "h/skdrv2nd.h" /* Adapter Control and Driver specific Def. */ + +/* local function prototypes */ +static int SkGePortCheckUpXmac(SK_AC*, SK_IOC, int); +static int SkGePortCheckUpBcom(SK_AC*, SK_IOC, int); +static int SkGePortCheckUpGmac(SK_AC*, SK_IOC, int); +static void SkPhyIsrBcom(SK_AC*, SK_IOC, int, SK_U16); +static void SkPhyIsrGmac(SK_AC*, SK_IOC, int, SK_U16); +#ifdef OTHER_PHY +static int SkGePortCheckUpLone(SK_AC*, SK_IOC, int); +static int SkGePortCheckUpNat(SK_AC*, SK_IOC, int); +static void SkPhyIsrLone(SK_AC*, SK_IOC, int, SK_U16); +#endif /* OTHER_PHY */ + +/* + * array of Rx counter from XMAC which are checked + * in AutoSense mode to check whether a link is not able to auto-negotiate. + */ +static const SK_U16 SkGeRxRegs[]= { + XM_RXF_64B, + XM_RXF_127B, + XM_RXF_255B, + XM_RXF_511B, + XM_RXF_1023B, + XM_RXF_MAX_SZ +} ; + +#ifdef __C2MAN__ +/* + * Special IRQ function + * + * General Description: + * + */ +intro() +{} +#endif + +/* Define return codes of SkGePortCheckUp and CheckShort */ +#define SK_HW_PS_NONE 0 /* No action needed */ +#define SK_HW_PS_RESTART 1 /* Restart needed */ +#define SK_HW_PS_LINK 2 /* Link Up actions needed */ + +/****************************************************************************** + * + * SkHWInitDefSense() - Default Autosensing mode initialization + * + * Description: sets the PLinkMode for HWInit + * + * Returns: N/A + */ +static void SkHWInitDefSense( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + pPrt = &pAC->GIni.GP[Port]; + + pPrt->PAutoNegTimeOut = 0; + + if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) { + pPrt->PLinkMode = pPrt->PLinkModeConf; + return; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("AutoSensing: First mode %d on Port %d\n", + (int)SK_LMODE_AUTOFULL, Port)); + + pPrt->PLinkMode = SK_LMODE_AUTOFULL; + + return; +} /* SkHWInitDefSense */ + + +/****************************************************************************** + * + * SkHWSenseGetNext() - Get Next Autosensing Mode + * + * Description: gets the appropriate next mode + * + * Note: + * + */ +SK_U8 SkHWSenseGetNext( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + pPrt = &pAC->GIni.GP[Port]; + + pPrt->PAutoNegTimeOut = 0; + + if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) { + /* Leave all as configured */ + return(pPrt->PLinkModeConf); + } + + if (pPrt->PLinkMode == SK_LMODE_AUTOFULL) { + /* Return next mode AUTOBOTH */ + return(SK_LMODE_AUTOBOTH); + } + + /* Return default autofull */ + return(SK_LMODE_AUTOFULL); +} /* SkHWSenseGetNext */ + + +/****************************************************************************** + * + * SkHWSenseSetNext() - Autosensing Set next mode + * + * Description: sets the appropriate next mode + * + * Returns: N/A + */ +void SkHWSenseSetNext( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U8 NewMode) /* New Mode to be written in sense mode */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + pPrt = &pAC->GIni.GP[Port]; + + pPrt->PAutoNegTimeOut = 0; + + if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) { + return; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("AutoSensing: next mode %d on Port %d\n", + (int)NewMode, Port)); + + pPrt->PLinkMode = NewMode; + + return; +} /* SkHWSenseSetNext */ + + +/****************************************************************************** + * + * SkHWLinkDown() - Link Down handling + * + * Description: handles the hardware link down signal + * + * Returns: N/A + */ +void SkHWLinkDown( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + pPrt = &pAC->GIni.GP[Port]; + + /* Disable all MAC interrupts */ + SkMacIrqDisable(pAC, IoC, Port); + + /* Disable Receiver and Transmitter */ + SkMacRxTxDisable(pAC, IoC, Port); + + /* Init default sense mode */ + SkHWInitDefSense(pAC, IoC, Port); + + if (!pPrt->PHWLinkUp) { + return; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link down Port %d\n", Port)); + + /* Set Link to DOWN */ + pPrt->PHWLinkUp = SK_FALSE; + + /* Reset Port stati */ + pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_INDETERMINATED; + + /* Re-init Phy especially when the AutoSense default is set now */ + SkMacInitPhy(pAC, IoC, Port, SK_FALSE); + + /* GP0: used for workaround of Rev. C Errata 2 */ + + /* Do NOT signal to RLMT */ + + /* Do NOT start the timer here */ +} /* SkHWLinkDown */ + + +/****************************************************************************** + * + * SkHWLinkUp() - Link Up handling + * + * Description: handles the hardware link up signal + * + * Returns: N/A + */ +void SkHWLinkUp( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PHWLinkUp) { + /* We do NOT need to proceed on active link */ + return; + } + + pPrt->PHWLinkUp = SK_TRUE; + pPrt->PAutoNegFail = SK_FALSE; + pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; + + if (pPrt->PLinkMode != SK_LMODE_AUTOHALF && + pPrt->PLinkMode != SK_LMODE_AUTOFULL && + pPrt->PLinkMode != SK_LMODE_AUTOBOTH) { + /* Link is up and no Auto-negotiation should be done */ + + /* Link speed should be the configured one */ + switch (pPrt->PLinkSpeed) { + case SK_LSPEED_AUTO: + /* default is 1000 Mbps */ + case SK_LSPEED_1000MBPS: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + break; + case SK_LSPEED_100MBPS: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_100MBPS; + break; + case SK_LSPEED_10MBPS: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_10MBPS; + break; + } + + /* Set Link Mode Status */ + if (pPrt->PLinkMode == SK_LMODE_FULL) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_FULL; + } + else { + pPrt->PLinkModeStatus = SK_LMODE_STAT_HALF; + } + + /* No flow control without auto-negotiation */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + + /* enable Rx/Tx */ + SkMacRxTxEnable(pAC, IoC, Port); + } +} /* SkHWLinkUp */ + + +/****************************************************************************** + * + * SkMacParity() - MAC parity workaround + * + * Description: handles MAC parity errors correctly + * + * Returns: N/A + */ +static void SkMacParity( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index of the port failed */ +{ + SK_EVPARA Para; + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_U32 TxMax; /* TxMax Counter */ + + pPrt = &pAC->GIni.GP[Port]; + + /* Clear IRQ Tx Parity Error */ + if (pAC->GIni.GIGenesis) { + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_PERR); + } + else { + /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), + (SK_U8)((pAC->GIni.GIChipRev == 0) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE)); + } + + if (pPrt->PCheckPar) { + if (Port == MAC_1) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG); + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E017, SKERR_SIRQ_E017MSG); + } + Para.Para64 = Port; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = Port; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + + return; + } + + /* Check whether frames with a size of 1k were sent */ + if (pAC->GIni.GIGenesis) { + /* Snap statistic counters */ + (void)SkXmUpdateStats(pAC, IoC, Port); + + (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXF_MAX_SZ, &TxMax); + } + else { + (void)SkGmMacStatistic(pAC, IoC, Port, GM_TXF_1518B, &TxMax); + } + + if (TxMax > 0) { + /* From now on check the parity */ + pPrt->PCheckPar = SK_TRUE; + } +} /* SkMacParity */ + + +/****************************************************************************** + * + * SkGeHwErr() - Hardware Error service routine + * + * Description: handles all HW Error interrupts + * + * Returns: N/A + */ +static void SkGeHwErr( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +SK_U32 HwStatus) /* Interrupt status word */ +{ + SK_EVPARA Para; + SK_U16 Word; + + if ((HwStatus & (IS_IRQ_MST_ERR | IS_IRQ_STAT)) != 0) { + /* PCI Errors occured */ + if ((HwStatus & IS_IRQ_STAT) != 0) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E013, SKERR_SIRQ_E013MSG); + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E012, SKERR_SIRQ_E012MSG); + } + + /* Reset all bits in the PCI STATUS register */ + SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); + + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); + SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); + + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); + } + + if (pAC->GIni.GIGenesis) { + if ((HwStatus & IS_NO_STAT_M1) != 0) { + /* Ignore it */ + /* This situation is also indicated in the descriptor */ + SK_OUT16(IoC, MR_ADDR(MAC_1, RX_MFF_CTRL1), MFF_CLR_INSTAT); + } + + if ((HwStatus & IS_NO_STAT_M2) != 0) { + /* Ignore it */ + /* This situation is also indicated in the descriptor */ + SK_OUT16(IoC, MR_ADDR(MAC_2, RX_MFF_CTRL1), MFF_CLR_INSTAT); + } + + if ((HwStatus & IS_NO_TIST_M1) != 0) { + /* Ignore it */ + /* This situation is also indicated in the descriptor */ + SK_OUT16(IoC, MR_ADDR(MAC_1, RX_MFF_CTRL1), MFF_CLR_INTIST); + } + + if ((HwStatus & IS_NO_TIST_M2) != 0) { + /* Ignore it */ + /* This situation is also indicated in the descriptor */ + SK_OUT16(IoC, MR_ADDR(MAC_2, RX_MFF_CTRL1), MFF_CLR_INTIST); + } + } + else { /* YUKON */ + /* This is necessary only for Rx timing measurements */ + if ((HwStatus & IS_IRQ_TIST_OV) != 0) { + /* Clear Time Stamp Timer IRQ */ + SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ); + } + + if ((HwStatus & IS_IRQ_SENSOR) != 0) { + /* Clear I2C IRQ */ + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); + } + } + + if ((HwStatus & IS_RAM_RD_PAR) != 0) { + SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_RD_PERR); + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E014, SKERR_SIRQ_E014MSG); + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); + } + + if ((HwStatus & IS_RAM_WR_PAR) != 0) { + SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_WR_PERR); + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E015, SKERR_SIRQ_E015MSG); + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para); + } + + if ((HwStatus & IS_M1_PAR_ERR) != 0) { + SkMacParity(pAC, IoC, MAC_1); + } + + if ((HwStatus & IS_M2_PAR_ERR) != 0) { + SkMacParity(pAC, IoC, MAC_2); + } + + if ((HwStatus & IS_R1_PAR_ERR) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_P); + + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG); + Para.Para64 = MAC_1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((HwStatus & IS_R2_PAR_ERR) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_P); + + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG); + Para.Para64 = MAC_2; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_2; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } +} /* SkGeHwErr */ + + +/****************************************************************************** + * + * SkGeSirqIsr() - Special Interrupt Service Routine + * + * Description: handles all non data transfer specific interrupts (slow path) + * + * Returns: N/A + */ +void SkGeSirqIsr( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +SK_U32 Istatus) /* Interrupt status word */ +{ + SK_EVPARA Para; + SK_U32 RegVal32; /* Read register value */ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + unsigned Len; + SK_U64 Octets; + SK_U16 PhyInt; + SK_U16 PhyIMsk; + int i; + + if ((Istatus & IS_HW_ERR) != 0) { + /* read the HW Error Interrupt source */ + SK_IN32(IoC, B0_HWE_ISRC, &RegVal32); + + SkGeHwErr(pAC, IoC, RegVal32); + } + + /* + * Packet Timeout interrupts + */ + /* Check whether MACs are correctly initialized */ + if (((Istatus & (IS_PA_TO_RX1 | IS_PA_TO_TX1)) != 0) && + pAC->GIni.GP[MAC_1].PState == SK_PRT_RESET) { + /* MAC 1 was not initialized but Packet timeout occured */ + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E004, + SKERR_SIRQ_E004MSG); + } + + if (((Istatus & (IS_PA_TO_RX2 | IS_PA_TO_TX2)) != 0) && + pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) { + /* MAC 2 was not initialized but Packet timeout occured */ + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E005, + SKERR_SIRQ_E005MSG); + } + + if ((Istatus & IS_PA_TO_RX1) != 0) { + /* Means network is filling us up */ + SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E002, + SKERR_SIRQ_E002MSG); + SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_RX1); + } + + if ((Istatus & IS_PA_TO_RX2) != 0) { + /* Means network is filling us up */ + SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E003, + SKERR_SIRQ_E003MSG); + SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_RX2); + } + + if ((Istatus & IS_PA_TO_TX1) != 0) { + + pPrt = &pAC->GIni.GP[0]; + + /* May be a normal situation in a server with a slow network */ + SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX1); + + /* + * workaround: if in half duplex mode, check for Tx hangup. + * Read number of TX'ed bytes, wait for 10 ms, then compare + * the number with current value. If nothing changed, we assume + * that Tx is hanging and do a FIFO flush (see event routine). + */ + if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) && + !pPrt->HalfDupTimerActive) { + /* + * many more pack. arb. timeouts may come in between, + * we ignore those + */ + pPrt->HalfDupTimerActive = SK_TRUE; + + Len = sizeof(SK_U64); + SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets, + &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(pAC, 0), + pAC->Rlmt.Port[0].Net->NetNumber); + + pPrt->LastOctets = Octets; + + Para.Para32[0] = 0; + SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME, + SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para); + } + } + + if ((Istatus & IS_PA_TO_TX2) != 0) { + + pPrt = &pAC->GIni.GP[1]; + + /* May be a normal situation in a server with a slow network */ + SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX2); + + /* workaround: see above */ + if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) && + !pPrt->HalfDupTimerActive) { + pPrt->HalfDupTimerActive = SK_TRUE; + + Len = sizeof(SK_U64); + SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets, + &Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(pAC, 1), + pAC->Rlmt.Port[1].Net->NetNumber); + + pPrt->LastOctets = Octets; + + Para.Para32[0] = 1; + SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME, + SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para); + } + } + + /* Check interrupts of the particular queues */ + if ((Istatus & IS_R1_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E006, + SKERR_SIRQ_E006MSG); + Para.Para64 = MAC_1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((Istatus & IS_R2_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E007, + SKERR_SIRQ_E007MSG); + Para.Para64 = MAC_2; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_2; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((Istatus & IS_XS1_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_XS1_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E008, + SKERR_SIRQ_E008MSG); + Para.Para64 = MAC_1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((Istatus & IS_XA1_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_XA1_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E009, + SKERR_SIRQ_E009MSG); + Para.Para64 = MAC_1; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_1; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((Istatus & IS_XS2_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_XS2_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E010, + SKERR_SIRQ_E010MSG); + Para.Para64 = MAC_2; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_2; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((Istatus & IS_XA2_C) != 0) { + /* Clear IRQ */ + SK_OUT32(IoC, B0_XA2_CSR, CSR_IRQ_CL_C); + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E011, + SKERR_SIRQ_E011MSG); + Para.Para64 = MAC_2; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); + Para.Para32[0] = MAC_2; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + /* External reg interrupt */ + if ((Istatus & IS_EXT_REG) != 0) { + /* Test IRQs from PHY */ + for (i = 0; i < pAC->GIni.GIMacsFound; i++) { + + pPrt = &pAC->GIni.GP[i]; + + if (pPrt->PState == SK_PRT_RESET) { + continue; + } + + switch (pPrt->PhyType) { + + case SK_PHY_XMAC: + break; + + case SK_PHY_BCOM: + SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_STAT, &PhyInt); + SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_MASK, &PhyIMsk); + + if ((PhyInt & ~PhyIMsk) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Port %d Bcom Int: 0x%04X Mask: 0x%04X\n", + i, PhyInt, PhyIMsk)); + SkPhyIsrBcom(pAC, IoC, i, PhyInt); + } + break; + + case SK_PHY_MARV_COPPER: + case SK_PHY_MARV_FIBER: + SkGmPhyRead(pAC, IoC, i, PHY_MARV_INT_STAT, &PhyInt); + SkGmPhyRead(pAC, IoC, i, PHY_MARV_INT_MASK, &PhyIMsk); + + if ((PhyInt & PhyIMsk) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Port %d Marv Int: 0x%04X Mask: 0x%04X\n", + i, PhyInt, PhyIMsk)); + SkPhyIsrGmac(pAC, IoC, i, PhyInt); + } + break; + +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_STAT, &PhyInt); + SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_ENAB, &PhyIMsk); + + if ((PhyInt & PhyIMsk) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Port %d Lone Int: %x Mask: %x\n", + i, PhyInt, PhyIMsk)); + SkPhyIsrLone(pAC, IoC, i, PhyInt); + } + break; + case SK_PHY_NAT: + /* todo: National */ + break; +#endif /* OTHER_PHY */ + } + } + } + + /* I2C Ready interrupt */ + if ((Istatus & IS_I2C_READY) != 0) { + SkI2cIsr(pAC, IoC); + } + + if ((Istatus & IS_LNK_SYNC_M1) != 0) { + /* + * We do NOT need the Link Sync interrupt, because it shows + * us only a link going down. + */ + /* clear interrupt */ + SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LED_CLR_IRQ); + } + + /* Check MAC after link sync counter */ + if ((Istatus & IS_MAC1) != 0) { + /* IRQ from MAC 1 */ + SkMacIrq(pAC, IoC, MAC_1); + } + + if ((Istatus & IS_LNK_SYNC_M2) != 0) { + /* + * We do NOT need the Link Sync interrupt, because it shows + * us only a link going down. + */ + /* clear interrupt */ + SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LED_CLR_IRQ); + } + + /* Check MAC after link sync counter */ + if ((Istatus & IS_MAC2) != 0) { + /* IRQ from MAC 2 */ + SkMacIrq(pAC, IoC, MAC_2); + } + + /* Timer interrupt (served last) */ + if ((Istatus & IS_TIMINT) != 0) { + SkHwtIsr(pAC, IoC); + } +} /* SkGeSirqIsr */ + + +/****************************************************************************** + * + * SkGePortCheckShorts() - Implementing XMAC Workaround Errata # 2 + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + */ +static int SkGePortCheckShorts( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + SK_U32 Shorts; /* Short Event Counter */ + SK_U32 CheckShorts; /* Check value for Short Event Counter */ + SK_U64 RxCts; /* Rx Counter (packets on network) */ + SK_U32 RxTmp; /* Rx temp. Counter */ + SK_U32 FcsErrCts; /* FCS Error Counter */ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Rtv; /* Return value */ + int i; + + pPrt = &pAC->GIni.GP[Port]; + + /* Default: no action */ + Rtv = SK_HW_PS_NONE; + + (void)SkXmUpdateStats(pAC, IoC, Port); + + /* Extra precaution: check for short Event counter */ + (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXE_SHT_ERR, &Shorts); + + /* + * Read Rx counter (packets seen on the network and not necessarily + * really received. + */ + RxCts = 0; + + for (i = 0; i < sizeof(SkGeRxRegs)/sizeof(SkGeRxRegs[0]); i++) { + (void)SkXmMacStatistic(pAC, IoC, Port, SkGeRxRegs[i], &RxTmp); + RxCts += (SK_U64)RxTmp; + } + + /* On default: check shorts against zero */ + CheckShorts = 0; + + /* Extra precaution on active links */ + if (pPrt->PHWLinkUp) { + /* Reset Link Restart counter */ + pPrt->PLinkResCt = 0; + pPrt->PAutoNegTOCt = 0; + + /* If link is up check for 2 */ + CheckShorts = 2; + + (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXF_FCS_ERR, &FcsErrCts); + + if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg == SK_LIPA_UNKNOWN && + (pPrt->PLinkMode == SK_LMODE_HALF || + pPrt->PLinkMode == SK_LMODE_FULL)) { + /* + * This is autosensing and we are in the fallback + * manual full/half duplex mode. + */ + if (RxCts == pPrt->PPrevRx) { + /* Nothing received, restart link */ + pPrt->PPrevFcs = FcsErrCts; + pPrt->PPrevShorts = Shorts; + + return(SK_HW_PS_RESTART); + } + else { + pPrt->PLipaAutoNeg = SK_LIPA_MANUAL; + } + } + + if (((RxCts - pPrt->PPrevRx) > pPrt->PRxLim) || + (!(FcsErrCts - pPrt->PPrevFcs))) { + /* + * Note: The compare with zero above has to be done the way shown, + * otherwise the Linux driver will have a problem. + */ + /* + * We received a bunch of frames or no CRC error occured on the + * network -> ok. + */ + pPrt->PPrevRx = RxCts; + pPrt->PPrevFcs = FcsErrCts; + pPrt->PPrevShorts = Shorts; + + return(SK_HW_PS_NONE); + } + + pPrt->PPrevFcs = FcsErrCts; + } + + + if ((Shorts - pPrt->PPrevShorts) > CheckShorts) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Short Event Count Restart Port %d \n", Port)); + Rtv = SK_HW_PS_RESTART; + } + + pPrt->PPrevShorts = Shorts; + pPrt->PPrevRx = RxCts; + + return(Rtv); +} /* SkGePortCheckShorts */ + + +/****************************************************************************** + * + * SkGePortCheckUp() - Check if the link is up + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUp( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + switch (pAC->GIni.GP[Port].PhyType) { + case SK_PHY_XMAC: + return(SkGePortCheckUpXmac(pAC, IoC, Port)); + case SK_PHY_BCOM: + return(SkGePortCheckUpBcom(pAC, IoC, Port)); + case SK_PHY_MARV_COPPER: + case SK_PHY_MARV_FIBER: + return(SkGePortCheckUpGmac(pAC, IoC, Port)); +#ifdef OTHER_PHY + case SK_PHY_LONE: + return(SkGePortCheckUpLone(pAC, IoC, Port)); + case SK_PHY_NAT: + return(SkGePortCheckUpNat(pAC, IoC, Port)); +#endif /* OTHER_PHY */ + } + return(SK_HW_PS_NONE); +} /* SkGePortCheckUp */ + + +/****************************************************************************** + * + * SkGePortCheckUpXmac() - Implementing of the Workaround Errata # 2 + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpXmac( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + SK_U32 Shorts; /* Short Event Counter */ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Done; + SK_U32 GpReg; /* General Purpose register value */ + SK_U16 Isrc; /* Interrupt source register */ + SK_U16 IsrcSum; /* Interrupt source register sum */ + SK_U16 LpAb; /* Link Partner Ability */ + SK_U16 ResAb; /* Resolved Ability */ + SK_U16 ExtStat; /* Extended Status Register */ + SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ + SK_U8 NextMode; /* Next AutoSensing Mode */ + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PHWLinkUp) { + if (pPrt->PhyType != SK_PHY_XMAC) { + return(SK_HW_PS_NONE); + } + else { + return(SkGePortCheckShorts(pAC, IoC, Port)); + } + } + + IsrcSum = pPrt->PIsave; + pPrt->PIsave = 0; + + /* Now wait for each port's link */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + AutoNeg = SK_FALSE; + } + else { + AutoNeg = SK_TRUE; + } + + if (pPrt->PLinkBroken) { + /* Link was broken */ + XM_IN32(IoC, Port, XM_GP_PORT, &GpReg); + + if ((GpReg & XM_GP_INP_ASS) == 0) { + /* The Link is in sync */ + XM_IN16(IoC, Port, XM_ISRC, &Isrc); + IsrcSum |= Isrc; + SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum); + + if ((Isrc & XM_IS_INP_ASS) == 0) { + /* It has been in sync since last time */ + /* Restart the PORT */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link in sync Restart Port %d\n", Port)); + + (void)SkXmUpdateStats(pAC, IoC, Port); + + /* We now need to reinitialize the PrevShorts counter */ + (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXE_SHT_ERR, &Shorts); + pPrt->PPrevShorts = Shorts; + + pPrt->PLinkBroken = SK_FALSE; + + /* + * Link Restart Workaround: + * it may be possible that the other Link side + * restarts its link as well an we detect + * another LinkBroken. To prevent this + * happening we check for a maximum number + * of consecutive restart. If those happens, + * we do NOT restart the active link and + * check whether the link is now o.k. + */ + pPrt->PLinkResCt++; + + pPrt->PAutoNegTimeOut = 0; + + if (pPrt->PLinkResCt < SK_MAX_LRESTART) { + return(SK_HW_PS_RESTART); + } + + pPrt->PLinkResCt = 0; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Do NOT restart on Port %d %x %x\n", Port, Isrc, IsrcSum)); + } + else { + pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Save Sync/nosync Port %d %x %x\n", Port, Isrc, IsrcSum)); + + /* Do nothing more if link is broken */ + return(SK_HW_PS_NONE); + } + } + else { + /* Do nothing more if link is broken */ + return(SK_HW_PS_NONE); + } + + } + else { + /* Link was not broken, check if it is */ + XM_IN16(IoC, Port, XM_ISRC, &Isrc); + IsrcSum |= Isrc; + if ((Isrc & XM_IS_INP_ASS) != 0) { + XM_IN16(IoC, Port, XM_ISRC, &Isrc); + IsrcSum |= Isrc; + if ((Isrc & XM_IS_INP_ASS) != 0) { + XM_IN16(IoC, Port, XM_ISRC, &Isrc); + IsrcSum |= Isrc; + if ((Isrc & XM_IS_INP_ASS) != 0) { + pPrt->PLinkBroken = SK_TRUE; + /* Re-Init Link partner Autoneg flag */ + pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN; + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link broken Port %d\n", Port)); + + /* Cable removed-> reinit sense mode */ + SkHWInitDefSense(pAC, IoC, Port); + + return(SK_HW_PS_RESTART); + } + } + } + else { + SkXmAutoNegLipaXmac(pAC, IoC, Port, Isrc); + if (SkGePortCheckShorts(pAC, IoC, Port) == SK_HW_PS_RESTART) { + return(SK_HW_PS_RESTART); + } + } + } + + /* + * here we usually can check whether the link is in sync and + * auto-negotiation is done. + */ + XM_IN32(IoC, Port, XM_GP_PORT, &GpReg); + XM_IN16(IoC, Port, XM_ISRC, &Isrc); + IsrcSum |= Isrc; + + SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum); + + if ((GpReg & XM_GP_INP_ASS) != 0 || (IsrcSum & XM_IS_INP_ASS) != 0) { + if ((GpReg & XM_GP_INP_ASS) == 0) { + /* Save Auto-negotiation Done interrupt only if link is in sync */ + pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND); + } +#ifdef DEBUG + if ((pPrt->PIsave & XM_IS_AND) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done rescheduled Port %d\n", Port)); + } +#endif /* DEBUG */ + return(SK_HW_PS_NONE); + } + + if (AutoNeg) { + if ((IsrcSum & XM_IS_AND) != 0) { + SkHWLinkUp(pAC, IoC, Port); + Done = SkMacAutoNegDone(pAC, IoC, Port); + if (Done != SK_AND_OK) { + /* Get PHY parameters, for debugging only */ + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LpAb); + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg FAIL Port %d (LpAb %x, ResAb %x)\n", + Port, LpAb, ResAb)); + + /* Try next possible mode */ + NextMode = SkHWSenseGetNext(pAC, IoC, Port); + SkHWLinkDown(pAC, IoC, Port); + if (Done == SK_AND_DUP_CAP) { + /* GoTo next mode */ + SkHWSenseSetNext(pAC, IoC, Port, NextMode); + } + + return(SK_HW_PS_RESTART); + } + /* + * Dummy Read extended status to prevent extra link down/ups + * (clear Page Received bit if set) + */ + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_EXP, &ExtStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done Port %d\n", Port)); + return(SK_HW_PS_LINK); + } + + /* AutoNeg not done, but HW link is up. Check for timeouts */ + pPrt->PAutoNegTimeOut++; + if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) { + /* Increase the Timeout counter */ + pPrt->PAutoNegTOCt++; + + /* Timeout occured */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("AutoNeg timeout Port %d\n", Port)); + if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg != SK_LIPA_AUTO) { + /* Set Link manually up */ + SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Set manual full duplex Port %d\n", Port)); + } + + if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg == SK_LIPA_AUTO && + pPrt->PAutoNegTOCt >= SK_MAX_ANEG_TO) { + /* + * This is rather complicated. + * we need to check here whether the LIPA_AUTO + * we saw before is false alert. We saw at one + * switch ( SR8800) that on boot time it sends + * just one auto-neg packet and does no further + * auto-negotiation. + * Solution: we restart the autosensing after + * a few timeouts. + */ + pPrt->PAutoNegTOCt = 0; + pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN; + SkHWInitDefSense(pAC, IoC, Port); + } + + /* Do the restart */ + return(SK_HW_PS_RESTART); + } + } + else { + /* Link is up and we don't need more */ +#ifdef DEBUG + if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("ERROR: Lipa auto detected on port %d\n", Port)); + } +#endif /* DEBUG */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link sync(GP), Port %d\n", Port)); + SkHWLinkUp(pAC, IoC, Port); + + /* + * Link sync (GP) and so assume a good connection. But if not received + * a bunch of frames received in a time slot (maybe broken tx cable) + * the port is restart. + */ + return(SK_HW_PS_LINK); + } + + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpXmac */ + + +/****************************************************************************** + * + * SkGePortCheckUpBcom() - Check if the link is up on Bcom PHY + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpBcom( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Done; + SK_U16 Isrc; /* Interrupt source register */ + SK_U16 PhyStat; /* Phy Status Register */ + SK_U16 ResAb; /* Master/Slave resolution */ + SK_U16 Ctrl; /* Broadcom control flags */ +#ifdef DEBUG + SK_U16 LpAb; + SK_U16 ExtStat; +#endif /* DEBUG */ + SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ + + pPrt = &pAC->GIni.GP[Port]; + + /* Check for No HCD Link events (#10523) */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &Isrc); + +#ifdef xDEBUG + if ((Isrc & ~(PHY_B_IS_HCT | PHY_B_IS_LCT) == + (PHY_B_IS_SCR_S_ER | PHY_B_IS_RRS_CHANGE | PHY_B_IS_LRS_CHANGE)) { + + SK_U32 Stat1, Stat2, Stat3; + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1); + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "CheckUp1 - Stat: %x, Mask: %x", + (void *)Isrc, + (void *)Stat1); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &Stat2); + Stat1 = Stat1 << 16 | Stat2; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3); + Stat2 = Stat2 << 16 | Stat3; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "Ctrl/Stat: %x, AN Adv/LP: %x", + (void *)Stat1, + (void *)Stat2); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2); + Stat1 = Stat1 << 16 | Stat2; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &Stat3); + Stat2 = Stat2 << 16 | Stat3; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x", + (void *)Stat1, + (void *)Stat2); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2); + Stat1 = Stat1 << 16 | Stat2; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3); + Stat2 = Stat2 << 16 | Stat3; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x", + (void *)Stat1, + (void *)Stat2); + } +#endif /* DEBUG */ + + if ((Isrc & (PHY_B_IS_NO_HDCL /* | PHY_B_IS_NO_HDC */)) != 0) { + /* + * Workaround BCom Errata: + * enable and disable loopback mode if "NO HCD" occurs. + */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Ctrl); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, + (SK_U16)(Ctrl | PHY_CT_LOOP)); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, + (SK_U16)(Ctrl & ~PHY_CT_LOOP)); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("No HCD Link event, Port %d\n", Port)); +#ifdef xDEBUG + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "No HCD link event, port %d.", + (void *)Port, + (void *)NULL); +#endif /* DEBUG */ + } + + /* Not obsolete: link status bit is latched to 0 and autoclearing! */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat); + + if (pPrt->PHWLinkUp) { + return(SK_HW_PS_NONE); + } + +#ifdef xDEBUG + { + SK_U32 Stat1, Stat2, Stat3; + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1); + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "CheckUp1a - Stat: %x, Mask: %x", + (void *)Isrc, + (void *)Stat1); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat); + Stat1 = Stat1 << 16 | PhyStat; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3); + Stat2 = Stat2 << 16 | Stat3; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "Ctrl/Stat: %x, AN Adv/LP: %x", + (void *)Stat1, + (void *)Stat2); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2); + Stat1 = Stat1 << 16 | Stat2; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb); + Stat2 = Stat2 << 16 | ResAb; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x", + (void *)Stat1, + (void *)Stat2); + + Stat1 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1); + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2); + Stat1 = Stat1 << 16 | Stat2; + Stat2 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2); + Stat3 = 0; + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3); + Stat2 = Stat2 << 16 | Stat3; + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x", + (void *)Stat1, + (void *)Stat2); + } +#endif /* DEBUG */ + + /* Now wait for each port's link */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + AutoNeg = SK_FALSE; + } + else { + AutoNeg = SK_TRUE; + } + + /* + * Here we usually can check whether the link is in sync and + * auto-negotiation is done. + */ + + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat); + + SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat)); + + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb); + + if ((ResAb & PHY_B_1000S_MSF) != 0) { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Master/Slave Fault port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + + return(SK_HW_PS_RESTART); + } + + if ((PhyStat & PHY_ST_LSYNC) == 0) { + return(SK_HW_PS_NONE); + } + + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? + SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE; + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat)); + + if (AutoNeg) { + if ((PhyStat & PHY_ST_AN_OVER) != 0) { + SkHWLinkUp(pAC, IoC, Port); + Done = SkMacAutoNegDone(pAC, IoC, Port); + if (Done != SK_AND_OK) { +#ifdef DEBUG + /* Get PHY parameters, for debugging only */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LpAb); + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ExtStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n", + Port, LpAb, ExtStat)); +#endif /* DEBUG */ + return(SK_HW_PS_RESTART); + } + else { +#ifdef xDEBUG + /* Dummy read ISR to prevent extra link downs/ups */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat); + + if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) { + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "CheckUp2 - Stat: %x", + (void *)ExtStat, + (void *)NULL); + } +#endif /* DEBUG */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done Port %d\n", Port)); + return(SK_HW_PS_LINK); + } + } + } + else { /* !AutoNeg */ + /* Link is up and we don't need more. */ +#ifdef DEBUG + if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("ERROR: Lipa auto detected on port %d\n", Port)); + } +#endif /* DEBUG */ + +#ifdef xDEBUG + /* Dummy read ISR to prevent extra link downs/ups */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat); + + if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) { + CMSMPrintString( + pAC->pConfigTable, + MSG_TYPE_RUNTIME_INFO, + "CheckUp3 - Stat: %x", + (void *)ExtStat, + (void *)NULL); + } +#endif /* DEBUG */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link sync(GP), Port %d\n", Port)); + SkHWLinkUp(pAC, IoC, Port); + return(SK_HW_PS_LINK); + } + + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpBcom */ + + +/****************************************************************************** + * + * SkGePortCheckUpGmac() - Check if the link is up on Marvell PHY + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpGmac( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Done; + SK_U16 Isrc; /* Interrupt source */ + SK_U16 PhyStat; /* Phy Status */ + SK_U16 PhySpecStat;/* Phy Specific Status */ + SK_U16 ResAb; /* Master/Slave resolution */ + SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ + + pPrt = &pAC->GIni.GP[Port]; + + /* Read PHY Interrupt Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &Isrc); + + if ((Isrc & PHY_M_IS_AN_COMPL) != 0) { + /* TBD */ + } + + if ((Isrc & PHY_M_IS_DOWNSH_DET) != 0) { + /* TBD */ + } + + if (pPrt->PHWLinkUp) { + return(SK_HW_PS_NONE); + } + + /* Now wait for each port's link */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + AutoNeg = SK_FALSE; + } + else { + AutoNeg = SK_TRUE; + } + + /* Read PHY Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat)); + + SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat); + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb); + + if ((ResAb & PHY_B_1000S_MSF) != 0) { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Master/Slave Fault port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + + return(SK_HW_PS_RESTART); + } + + /* Read PHY Specific Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg: %d, PhySpecStat: 0x%04x\n", AutoNeg, PhySpecStat)); + + if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) { + return(SK_HW_PS_NONE); + } + + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? + SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE; + + pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7); + + if (AutoNeg) { + /* Auto-Negotiation Over ? */ + if ((PhyStat & PHY_ST_AN_OVER) != 0) { + + SkHWLinkUp(pAC, IoC, Port); + + Done = SkMacAutoNegDone(pAC, IoC, Port); + + if (Done != SK_AND_OK) { + return(SK_HW_PS_RESTART); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done Port %d\n", Port)); + return(SK_HW_PS_LINK); + } + } + else { /* !AutoNeg */ + /* Link is up and we don't need more */ +#ifdef DEBUG + if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("ERROR: Lipa auto detected on port %d\n", Port)); + } +#endif /* DEBUG */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link sync, Port %d\n", Port)); + SkHWLinkUp(pAC, IoC, Port); + + return(SK_HW_PS_LINK); + } + + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpGmac */ + + +#ifdef OTHER_PHY +/****************************************************************************** + * + * SkGePortCheckUpLone() - Check if the link is up on Level One PHY + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpLone( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + int Done; + SK_U16 Isrc; /* Interrupt source register */ + SK_U16 LpAb; /* Link Partner Ability */ + SK_U16 ExtStat; /* Extended Status Register */ + SK_U16 PhyStat; /* Phy Status Register */ + SK_U16 StatSum; + SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */ + SK_U8 NextMode; /* Next AutoSensing Mode */ + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PHWLinkUp) { + return(SK_HW_PS_NONE); + } + + StatSum = pPrt->PIsave; + pPrt->PIsave = 0; + + /* Now wait for each ports link */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + AutoNeg = SK_FALSE; + } + else { + AutoNeg = SK_TRUE; + } + + /* + * here we usually can check whether the link is in sync and + * auto-negotiation is done. + */ + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_STAT, &PhyStat); + StatSum |= PhyStat; + + SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat); + + if ((PhyStat & PHY_ST_LSYNC) == 0) { + /* Save Auto-negotiation Done bit */ + pPrt->PIsave = (SK_U16)(StatSum & PHY_ST_AN_OVER); +#ifdef DEBUG + if ((pPrt->PIsave & PHY_ST_AN_OVER) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done rescheduled Port %d\n", Port)); + } +#endif /* DEBUG */ + return(SK_HW_PS_NONE); + } + + if (AutoNeg) { + if ((StatSum & PHY_ST_AN_OVER) != 0) { + SkHWLinkUp(pAC, IoC, Port); + Done = SkMacAutoNegDone(pAC, IoC, Port); + if (Done != SK_AND_OK) { + /* Get PHY parameters, for debugging only */ + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LpAb); + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ExtStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n", + Port, LpAb, ExtStat)); + + /* Try next possible mode */ + NextMode = SkHWSenseGetNext(pAC, IoC, Port); + SkHWLinkDown(pAC, IoC, Port); + if (Done == SK_AND_DUP_CAP) { + /* GoTo next mode */ + SkHWSenseSetNext(pAC, IoC, Port, NextMode); + } + + return(SK_HW_PS_RESTART); + + } + else { + /* + * Dummy Read interrupt status to prevent + * extra link down/ups + */ + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNeg done Port %d\n", Port)); + return(SK_HW_PS_LINK); + } + } + + /* AutoNeg not done, but HW link is up. Check for timeouts */ + pPrt->PAutoNegTimeOut++; + if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) { + /* Timeout occured */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("AutoNeg timeout Port %d\n", Port)); + if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE && + pPrt->PLipaAutoNeg != SK_LIPA_AUTO) { + /* Set Link manually up */ + SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Set manual full duplex Port %d\n", Port)); + } + + /* Do the restart */ + return(SK_HW_PS_RESTART); + } + } + else { + /* Link is up and we don't need more */ +#ifdef DEBUG + if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("ERROR: Lipa auto detected on port %d\n", Port)); + } +#endif /* DEBUG */ + + /* + * Dummy Read interrupt status to prevent + * extra link down/ups + */ + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("Link sync(GP), Port %d\n", Port)); + SkHWLinkUp(pAC, IoC, Port); + return(SK_HW_PS_LINK); + } + + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpLone */ + + +/****************************************************************************** + * + * SkGePortCheckUpNat() - Check if the link is up on National PHY + * + * return: + * 0 o.k. nothing needed + * 1 Restart needed on this port + * 2 Link came up + */ +static int SkGePortCheckUpNat( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO Context */ +int Port) /* Which port should be checked */ +{ + /* todo: National */ + return(SK_HW_PS_NONE); +} /* SkGePortCheckUpNat */ +#endif /* OTHER_PHY */ + + +/****************************************************************************** + * + * SkGeSirqEvent() - Event Service Routine + * + * Description: + * + * Notes: + */ +int SkGeSirqEvent( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* Io Context */ +SK_U32 Event, /* Module specific Event */ +SK_EVPARA Para) /* Event specific Parameter */ +{ + SK_U64 Octets; + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_U32 Port; + SK_U32 Time; + unsigned Len; + int PortStat; + SK_U8 Val8; + + Port = Para.Para32[0]; + pPrt = &pAC->GIni.GP[Port]; + + switch (Event) { + case SK_HWEV_WATIM: + /* Check whether port came up */ + PortStat = SkGePortCheckUp(pAC, IoC, Port); + + switch (PortStat) { + case SK_HW_PS_RESTART: + if (pPrt->PHWLinkUp) { + /* + * Set Link to down. + */ + SkHWLinkDown(pAC, IoC, Port); + + /* + * Signal directly to RLMT to ensure correct + * sequence of SWITCH and RESET event. + */ + SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para); + } + + /* Restart needed */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para); + break; + + case SK_HW_PS_LINK: + /* Signal to RLMT */ + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_UP, Para); + break; + + } + + /* Start again the check Timer */ + if (pPrt->PHWLinkUp) { + Time = SK_WA_ACT_TIME; + } + else { + Time = SK_WA_INA_TIME; + } + + /* Todo: still needed for non-XMAC PHYs??? */ + /* Start workaround Errata #2 timer */ + SkTimerStart(pAC, IoC, &pPrt->PWaTimer, Time, + SKGE_HWAC, SK_HWEV_WATIM, Para); + break; + + case SK_HWEV_PORT_START: + if (pPrt->PHWLinkUp) { + /* + * Signal directly to RLMT to ensure correct + * sequence of SWITCH and RESET event. + */ + SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para); + } + + SkHWLinkDown(pAC, IoC, Port); + + /* Schedule Port RESET */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para); + + /* Start workaround Errata #2 timer */ + SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME, + SKGE_HWAC, SK_HWEV_WATIM, Para); + break; + + case SK_HWEV_PORT_STOP: + if (pPrt->PHWLinkUp) { + /* + * Signal directly to RLMT to ensure correct + * sequence of SWITCH and RESET event. + */ + SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para); + } + + /* Stop Workaround Timer */ + SkTimerStop(pAC, IoC, &pPrt->PWaTimer); + + SkHWLinkDown(pAC, IoC, Port); + break; + + case SK_HWEV_UPDATE_STAT: + /* We do NOT need to update any statistics */ + break; + + case SK_HWEV_CLEAR_STAT: + /* We do NOT need to clear any statistics */ + for (Port = 0; Port < (SK_U32)pAC->GIni.GIMacsFound; Port++) { + pPrt->PPrevRx = 0; + pPrt->PPrevFcs = 0; + pPrt->PPrevShorts = 0; + } + break; + + case SK_HWEV_SET_LMODE: + Val8 = (SK_U8)Para.Para32[1]; + if (pPrt->PLinkModeConf != Val8) { + /* Set New link mode */ + pPrt->PLinkModeConf = Val8; + + /* Restart Port */ + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para); + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); + } + break; + + case SK_HWEV_SET_FLOWMODE: + Val8 = (SK_U8)Para.Para32[1]; + if (pPrt->PFlowCtrlMode != Val8) { + /* Set New Flow Control mode */ + pPrt->PFlowCtrlMode = Val8; + + /* Restart Port */ + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para); + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); + } + break; + + case SK_HWEV_SET_ROLE: + /* not possible for fiber */ + if (!pAC->GIni.GICopperType) { + break; + } + Val8 = (SK_U8)Para.Para32[1]; + if (pPrt->PMSMode != Val8) { + /* Set New link mode */ + pPrt->PMSMode = Val8; + + /* Restart Port */ + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para); + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); + } + break; + + case SK_HWEV_SET_SPEED: + if (pPrt->PhyType != SK_PHY_MARV_COPPER) { + break; + } + Val8 = (SK_U8)Para.Para32[1]; + if (pPrt->PLinkSpeed != Val8) { + /* Set New Speed parameter */ + pPrt->PLinkSpeed = Val8; + + /* Restart Port */ + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para); + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); + } + break; + + case SK_HWEV_HALFDUP_CHK: + /* + * half duplex hangup workaround. + * See packet arbiter timeout interrupt for description + */ + pPrt->HalfDupTimerActive = SK_FALSE; + if (pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) { + + Len = sizeof(SK_U64); + SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets, + &Len, (SK_U32)SK_PNMI_PORT_PHYS2INST(pAC, Port), + pAC->Rlmt.Port[Port].Net->NetNumber); + + if (pPrt->LastOctets == Octets) { + /* Tx hanging, a FIFO flush restarts it */ + SkMacFlushTxFifo(pAC, IoC, Port); + } + } + break; + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001, SKERR_SIRQ_E001MSG); + break; + } + + return(0); +} /* SkGeSirqEvent */ + + +/****************************************************************************** + * + * SkPhyIsrBcom() - PHY interrupt service routine + * + * Description: handles all interrupts from BCom PHY + * + * Returns: N/A + */ +static void SkPhyIsrBcom( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* Io Context */ +int Port, /* Port Num = PHY Num */ +SK_U16 IStatus) /* Interrupt Status */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_EVPARA Para; + + pPrt = &pAC->GIni.GP[Port]; + + if ((IStatus & PHY_B_IS_PSE) != 0) { + /* Incorrectable pair swap error */ + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E022, + SKERR_SIRQ_E022MSG); + } + + if ((IStatus & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) != 0) { + Para.Para32[0] = (SK_U32)Port; + + SkHWLinkDown(pAC, IoC, Port); + + /* Signal to RLMT */ + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + + /* Start workaround Errata #2 timer */ + SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME, + SKGE_HWAC, SK_HWEV_WATIM, Para); + } + +} /* SkPhyIsrBcom */ + + +/****************************************************************************** + * + * SkPhyIsrGmac() - PHY interrupt service routine + * + * Description: handles all interrupts from Marvell PHY + * + * Returns: N/A + */ +static void SkPhyIsrGmac( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* Io Context */ +int Port, /* Port Num = PHY Num */ +SK_U16 IStatus) /* Interrupt Status */ +{ + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + SK_EVPARA Para; + + pPrt = &pAC->GIni.GP[Port]; + + if ((IStatus & (PHY_M_IS_AN_PR | PHY_M_IS_LST_CHANGE)) != 0) { + Para.Para32[0] = (SK_U32)Port; + + SkHWLinkDown(pAC, IoC, Port); + + /* Signal to RLMT */ + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + + if ((IStatus & PHY_M_IS_AN_ERROR) != 0) { + /* Auto-Negotiation Error */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG); + } + + if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) { + /* TBD */ + } + + if ((IStatus & PHY_M_IS_FIFO_ERROR) != 0) { + /* FIFO Overflow/Underrun Error */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E024, SKERR_SIRQ_E024MSG); + } +} /* SkPhyIsrGmac */ + + +#ifdef OTHER_PHY +/****************************************************************************** + * + * SkPhyIsrLone() - PHY interrupt service routine + * + * Description: handles all interrupts from LONE PHY + * + * Returns: N/A + */ +static void SkPhyIsrLone( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* Io Context */ +int Port, /* Port Num = PHY Num */ +SK_U16 IStatus) /* Interrupt Status */ +{ + SK_EVPARA Para; + + if (IStatus & (PHY_L_IS_DUP | PHY_L_IS_ISOL)) { + SkHWLinkDown(pAC, IoC, Port); + + /* Signal to RLMT */ + Para.Para32[0] = (SK_U32)Port; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + } + +} /* SkPhyIsrLone */ +#endif /* OTHER_PHY */ + +#endif /* CONFIG_SK98 */ + +/* End of File */ diff --git a/drivers/sk98lin/ski2c.c b/drivers/sk98lin/ski2c.c new file mode 100644 index 000000000..2ab635a22 --- /dev/null +++ b/drivers/sk98lin/ski2c.c @@ -0,0 +1,1505 @@ +/****************************************************************************** + * + * Name: ski2c.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.57 $ + * Date: $Date: 2003/01/28 09:17:38 $ + * Purpose: Functions to access Voltage and Temperature Sensor + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: ski2c.c,v $ + * Revision 1.57 2003/01/28 09:17:38 rschmidt + * Fixed handling for sensors on YUKON Fiber. + * Editorial changes. + * + * Revision 1.56 2002/12/19 14:20:41 rschmidt + * Added debugging code in SkI2cWait(). + * Replaced all I2C-write operations with function SkI2cWrite(). + * Fixed compiler warning because of uninitialized 'Time' in SkI2cEvent(). + * Editorial changes. + * + * Revision 1.55 2002/10/15 07:23:55 rschmidt + * Added setting of the GIYukon32Bit bool variable to distinguish + * 32-bit adapters. + * Editorial changes (TWSI). + * + * Revision 1.54 2002/08/13 09:05:06 rschmidt + * Added new thresholds if VAUX is not available (GIVauxAvail). + * Merged defines for PHY PLL 3V3 voltage (A and B). + * Editorial changes. + * + * Revision 1.53 2002/08/08 11:04:53 rwahl + * Added missing comment for revision 1.51 + * + * Revision 1.52 2002/08/08 10:09:02 jschmalz + * Sensor init state caused wrong error log entry + * + * Revision 1.51 2002/08/06 09:43:03 jschmalz + * Extensions and changes for Yukon + * + * Revision 1.50 2002/08/02 12:09:22 rschmidt + * Added support for YUKON sensors. + * Editorial changes. + * + * Revision 1.49 2002/07/30 11:07:52 rschmidt + * Replaced MaxSens init by update for Copper in SkI2cInit1(), + * because it was already initialized in SkI2cInit0(). + * Editorial changes. + * + * Revision 1.48 2001/08/16 12:44:33 afischer + * LM80 sensor init values corrected + * + * Revision 1.47 2001/04/05 11:38:09 rassmann + * Set SenState to idle in SkI2cWaitIrq(). + * Changed error message in SkI2cWaitIrq(). + * + * Revision 1.46 2001/04/02 14:03:35 rassmann + * Changed pAC to IoC in SK_IN32(). + * + * Revision 1.45 2001/03/21 12:12:49 rassmann + * Resetting I2C_READY interrupt in SkI2cInit1(). + * + * Revision 1.44 2000/08/07 15:49:03 gklug + * Fix: SK_INFAST only in NetWare driver. + * + * Revision 1.43 2000/08/03 14:28:17 rassmann + * Added function to wait for I2C being ready before resetting the board. + * Replaced one duplicate "out of range" message with correct one. + * + * Revision 1.42 1999/11/22 13:35:12 cgoos + * Changed license header to GPL. + * + * Revision 1.41 1999/09/14 14:11:30 malthoff + * The 1000BT Dual Link adapter has got only one Fan. + * The second Fan has been removed. + * + * Revision 1.40 1999/05/27 13:37:27 malthoff + * Set divisor of 1 for fan count calculation. + * + * Revision 1.39 1999/05/20 14:54:43 malthoff + * I2c.DummyReads is not used in Diagnostics. + * + * Revision 1.38 1999/05/20 09:20:56 cgoos + * Changes for 1000Base-T (up to 9 sensors and fans). + * + * Revision 1.37 1999/03/25 15:11:36 gklug + * fix: reset error flag if sensor reads correct value + * + * Revision 1.36 1999/01/07 14:11:16 gklug + * fix: break added + * + * Revision 1.35 1999/01/05 15:31:49 gklug + * fix: CLEAR STAT command is now added correctly + * + * Revision 1.34 1998/12/01 13:45:16 gklug + * fix: introduced Init level, because we don't need reinits + * + * Revision 1.33 1998/11/09 14:54:25 malthoff + * Modify I2C Transfer Timeout handling for Diagnostics. + * + * Revision 1.32 1998/11/03 06:54:35 gklug + * fix: Need dummy reads at the beginning to init sensors + * + * Revision 1.31 1998/11/03 06:42:42 gklug + * fix: select correctVIO range only if between warning levels + * + * Revision 1.30 1998/11/02 07:36:53 gklug + * fix: Error should not include WARNING message + * + * Revision 1.29 1998/10/30 15:07:43 malthoff + * Disable 'I2C does not compelete' error log for diagnostics. + * + * Revision 1.28 1998/10/22 09:48:11 gklug + * fix: SysKonnectFileId typo + * + * Revision 1.27 1998/10/20 09:59:46 gklug + * add: parameter to SkOsGetTime + * + * Revision 1.26 1998/10/09 06:10:59 malthoff + * Remove ID_sccs by SysKonnectFileId. + * + * Revision 1.25 1998/09/08 12:40:26 gklug + * fix: syntax error in if clause + * + * Revision 1.24 1998/09/08 12:19:42 gklug + * chg: INIT Level checking + * + * Revision 1.23 1998/09/08 07:37:20 gklug + * fix: log error if PCI_IO voltage sensor could not be initialized + * + * Revision 1.22 1998/09/04 08:30:03 malthoff + * Bugfixes during SK_DIAG testing: + * - correct NS2BCLK() macro + * - correct SkI2cSndDev() + * - correct SkI2cWait() loop waiting for an event + * + * Revision 1.21 1998/08/27 14:46:01 gklug + * chg: if-then-else replaced by switch + * + * Revision 1.20 1998/08/27 14:40:07 gklug + * test: integral types + * + * Revision 1.19 1998/08/25 07:51:54 gklug + * fix: typos for compiling + * + * Revision 1.18 1998/08/25 06:12:24 gklug + * add: count errors and warnings + * fix: check not the sensor state but the ErrFlag! + * + * Revision 1.17 1998/08/25 05:56:48 gklug + * add: CheckSensor function + * + * Revision 1.16 1998/08/20 11:41:10 gklug + * chg: omit STRCPY macro by using char * as Sensor Description + * + * Revision 1.15 1998/08/20 11:37:35 gklug + * chg: change Ioc to IoC + * + * Revision 1.14 1998/08/20 11:32:52 gklug + * fix: Para compile error + * + * Revision 1.13 1998/08/20 11:27:41 gklug + * fix: Compile bugs with new awrning constants + * + * Revision 1.12 1998/08/20 08:53:05 gklug + * fix: compiler errors + * add: Threshold values + * + * Revision 1.11 1998/08/19 12:39:22 malthoff + * Compiler Fix: Some names have changed. + * + * Revision 1.10 1998/08/19 12:20:56 gklug + * fix: remove struct from C files (see CCC) + * + * Revision 1.9 1998/08/19 06:28:46 malthoff + * SkOsGetTime returns SK_U64 now. + * + * Revision 1.8 1998/08/17 13:53:33 gklug + * fix: Parameter of event function and its result + * + * Revision 1.7 1998/08/17 07:02:15 malthoff + * Modify the functions for accessing the I2C SW Registers. + * Modify SkI2cWait(). + * Put Lm80RcvReg into sklm80.c + * Remove Compiler Errors. + * + * Revision 1.6 1998/08/14 07:13:20 malthoff + * remove pAc with pAC + * remove smc with pAC + * change names to new convention + * + * Revision 1.5 1998/08/14 06:24:49 gklug + * add: init level 1 and 2 + * + * Revision 1.4 1998/08/12 14:31:12 gklug + * add: error log for unknown event + * + * Revision 1.3 1998/08/12 13:37:04 gklug + * add: Init 0 function + * + * Revision 1.2 1998/08/11 07:27:15 gklug + * add: functions of the interface + * adapt rest of source to C coding Conventions + * rmv: unnecessary code taken from Mona Lisa + * + * Revision 1.1 1998/06/19 14:28:43 malthoff + * Created. Sources taken from ML Projekt. + * Sources have to be reworked for GE. + * + * + ******************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +/* + * I2C Protocol + */ +static const char SysKonnectFileId[] = + "$Id: ski2c.c,v 1.57 2003/01/28 09:17:38 rschmidt Exp $"; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/lm80.h" +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef __C2MAN__ +/* + I2C protocol implementation. + + General Description: + + The I2C protocol is used for the temperature sensors and for + the serial EEPROM which hold the configuration. + + This file covers functions that allow to read write and do + some bulk requests a specified I2C address. + + The Genesis has 2 I2C buses. One for the EEPROM which holds + the VPD Data and one for temperature and voltage sensor. + The following picture shows the I2C buses, I2C devices and + their control registers. + + Note: The VPD functions are in skvpd.c +. +. PCI Config I2C Bus for VPD Data: +. +. +------------+ +. | VPD EEPROM | +. +------------+ +. | +. | <-- I2C +. | +. +-----------+-----------+ +. | | +. +-----------------+ +-----------------+ +. | PCI_VPD_ADR_REG | | PCI_VPD_DAT_REG | +. +-----------------+ +-----------------+ +. +. +. I2C Bus for LM80 sensor: +. +. +-----------------+ +. | Temperature and | +. | Voltage Sensor | +. | LM80 | +. +-----------------+ +. | +. | +. I2C --> | +. | +. +----+ +. +-------------->| OR |<--+ +. | +----+ | +. +------+------+ | +. | | | +. +--------+ +--------+ +----------+ +. | B2_I2C | | B2_I2C | | B2_I2C | +. | _CTRL | | _DATA | | _SW | +. +--------+ +--------+ +----------+ +. + The I2C bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL + and B2_I2C_DATA registers. + For driver software it is recommended to use the I2C control and + data register, because I2C bus timing is done by the ASIC and + an interrupt may be received when the I2C request is completed. + + Clock Rate Timing: MIN MAX generated by + VPD EEPROM: 50 kHz 100 kHz HW + LM80 over I2C Ctrl/Data reg. 50 kHz 100 kHz HW + LM80 over B2_I2C_SW register 0 400 kHz SW + + Note: The clock generated by the hardware is dependend on the + PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD + clock is 50 kHz. + */ +intro() +{} +#endif + +#ifdef SK_DIAG +/* + * I2C Fast Mode timing values used by the LM80. + * If new devices are added to the I2C bus the timing values have to be checked. + */ +#ifndef I2C_SLOW_TIMING +#define T_CLK_LOW 1300L /* clock low time in ns */ +#define T_CLK_HIGH 600L /* clock high time in ns */ +#define T_DATA_IN_SETUP 100L /* data in Set-up Time */ +#define T_START_HOLD 600L /* start condition hold time */ +#define T_START_SETUP 600L /* start condition Set-up time */ +#define T_STOP_SETUP 600L /* stop condition Set-up time */ +#define T_BUS_IDLE 1300L /* time the bus must free after Tx */ +#define T_CLK_2_DATA_OUT 900L /* max. clock low to data output valid */ +#else /* I2C_SLOW_TIMING */ +/* I2C Standard Mode Timing */ +#define T_CLK_LOW 4700L /* clock low time in ns */ +#define T_CLK_HIGH 4000L /* clock high time in ns */ +#define T_DATA_IN_SETUP 250L /* data in Set-up Time */ +#define T_START_HOLD 4000L /* start condition hold time */ +#define T_START_SETUP 4700L /* start condition Set-up time */ +#define T_STOP_SETUP 4000L /* stop condition Set-up time */ +#define T_BUS_IDLE 4700L /* time the bus must free after Tx */ +#endif /* !I2C_SLOW_TIMING */ + +#define NS2BCLK(x) (((x)*125)/10000) + +/* + * I2C Wire Operations + * + * About I2C_CLK_LOW(): + * + * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting + * clock to low, to prevent the ASIC and the I2C data client from driving the + * serial data line simultaneously (ASIC: last bit of a byte = '1', I2C client + * send an 'ACK'). See also Concentrator Bugreport No. 10192. + */ +#define I2C_DATA_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA) +#define I2C_DATA_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA) +#define I2C_DATA_OUT(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA_DIR) +#define I2C_DATA_IN(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA) +#define I2C_CLK_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_CLK) +#define I2C_CLK_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR) +#define I2C_START_COND(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK) + +#define NS2CLKT(x) ((x*125L)/10000) + +/*--------------- I2C Interface Register Functions --------------- */ + +/* + * sending one bit + */ +void SkI2cSndBit( +SK_IOC IoC, /* I/O Context */ +SK_U8 Bit) /* Bit to send */ +{ + I2C_DATA_OUT(IoC); + if (Bit) { + I2C_DATA_HIGH(IoC); + } + else { + I2C_DATA_LOW(IoC); + } + SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP)); + I2C_CLK_HIGH(IoC); + SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH)); + I2C_CLK_LOW(IoC); +} /* SkI2cSndBit*/ + + +/* + * Signal a start to the I2C Bus. + * + * A start is signaled when data goes to low in a high clock cycle. + * + * Ends with Clock Low. + * + * Status: not tested + */ +void SkI2cStart( +SK_IOC IoC) /* I/O Context */ +{ + /* Init data and Clock to output lines */ + /* Set Data high */ + I2C_DATA_OUT(IoC); + I2C_DATA_HIGH(IoC); + /* Set Clock high */ + I2C_CLK_HIGH(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP)); + + /* Set Data Low */ + I2C_DATA_LOW(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD)); + + /* Clock low without Data to Input */ + I2C_START_COND(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW)); +} /* SkI2cStart */ + + +void SkI2cStop( +SK_IOC IoC) /* I/O Context */ +{ + /* Init data and Clock to output lines */ + /* Set Data low */ + I2C_DATA_OUT(IoC); + I2C_DATA_LOW(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT)); + + /* Set Clock high */ + I2C_CLK_HIGH(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP)); + + /* + * Set Data High: Do it by setting the Data Line to Input. + * Because of a pull up resistor the Data Line + * floods to high. + */ + I2C_DATA_IN(IoC); + + /* + * When I2C activity is stopped + * o DATA should be set to input and + * o CLOCK should be set to high! + */ + SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE)); +} /* SkI2cStop */ + + +/* + * Receive just one bit via the I2C bus. + * + * Note: Clock must be set to LOW before calling this function. + * + * Returns The received bit. + */ +int SkI2cRcvBit( +SK_IOC IoC) /* I/O Context */ +{ + int Bit; + SK_U8 I2cSwCtrl; + + /* Init data as input line */ + I2C_DATA_IN(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT)); + + I2C_CLK_HIGH(IoC); + + SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH)); + + SK_I2C_GET_SW(IoC, &I2cSwCtrl); + + Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0; + + I2C_CLK_LOW(IoC); + SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT)); + + return(Bit); +} /* SkI2cRcvBit */ + + +/* + * Receive an ACK. + * + * returns 0 If acknowledged + * 1 in case of an error + */ +int SkI2cRcvAck( +SK_IOC IoC) /* I/O Context */ +{ + /* + * Received bit must be zero. + */ + return(SkI2cRcvBit(IoC) != 0); +} /* SkI2cRcvAck */ + + +/* + * Send an NACK. + */ +void SkI2cSndNAck( +SK_IOC IoC) /* I/O Context */ +{ + /* + * Received bit must be zero. + */ + SkI2cSndBit(IoC, 1); +} /* SkI2cSndNAck */ + + +/* + * Send an ACK. + */ +void SkI2cSndAck( +SK_IOC IoC) /* I/O Context */ +{ + /* + * Received bit must be zero. + * + */ + SkI2cSndBit(IoC, 0); +} /* SkI2cSndAck */ + + +/* + * Send one byte to the I2C device and wait for ACK. + * + * Return acknowleged status. + */ +int SkI2cSndByte( +SK_IOC IoC, /* I/O Context */ +int Byte) /* byte to send */ +{ + int i; + + for (i = 0; i < 8; i++) { + if (Byte & (1<<(7-i))) { + SkI2cSndBit(IoC, 1); + } + else { + SkI2cSndBit(IoC, 0); + } + } + + return(SkI2cRcvAck(IoC)); +} /* SkI2cSndByte */ + + +/* + * Receive one byte and ack it. + * + * Return byte. + */ +int SkI2cRcvByte( +SK_IOC IoC, /* I/O Context */ +int Last) /* Last Byte Flag */ +{ + int i; + int Byte = 0; + + for (i = 0; i < 8; i++) { + Byte <<= 1; + Byte |= SkI2cRcvBit(IoC); + } + + if (Last) { + SkI2cSndNAck(IoC); + } + else { + SkI2cSndAck(IoC); + } + + return(Byte); +} /* SkI2cRcvByte */ + + +/* + * Start dialog and send device address + * + * Return 0 if acknowleged, 1 in case of an error + */ +int SkI2cSndDev( +SK_IOC IoC, /* I/O Context */ +int Addr, /* Device Address */ +int Rw) /* Read / Write Flag */ +{ + SkI2cStart(IoC); + Rw = ~Rw; + Rw &= I2C_WRITE; + return(SkI2cSndByte(IoC, (Addr<<1) | Rw)); +} /* SkI2cSndDev */ + +#endif /* SK_DIAG */ + +/*----------------- I2C CTRL Register Functions ----------*/ + +/* + * waits for a completion of an I2C transfer + * + * returns 0: success, transfer completes + * 1: error, transfer does not complete, I2C transfer + * killed, wait loop terminated. + */ +int SkI2cWait( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Event) /* complete event to wait for (I2C_READ or I2C_WRITE) */ +{ + SK_U64 StartTime; + SK_U64 CurrentTime; + SK_U32 I2cCtrl; + + StartTime = SkOsGetTime(pAC); + + do { + CurrentTime = SkOsGetTime(pAC); + + if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) { + + SK_I2C_STOP(IoC); +#ifndef SK_DIAG + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG); +#endif /* !SK_DIAG */ + return(1); + } + + SK_I2C_GET_CTL(IoC, &I2cCtrl); + +#ifdef xYUKON_DBG + printf("StartTime=%lu, CurrentTime=%lu\n", + StartTime, CurrentTime); + if (kbhit()) { + return(1); + } +#endif /* YUKON_DBG */ + + } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31); + + return(0); +} /* SkI2cWait */ + + +/* + * waits for a completion of an I2C transfer + * + * Returns + * Nothing + */ +void SkI2cWaitIrq( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + SK_SENSOR *pSen; + SK_U64 StartTime; + SK_U32 IrqSrc; + + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + + if (pSen->SenState == SK_SEN_IDLE) { + return; + } + + StartTime = SkOsGetTime(pAC); + do { + if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) { + SK_I2C_STOP(IoC); +#ifndef SK_DIAG + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG); +#endif /* !SK_DIAG */ + return; + } + SK_IN32(IoC, B0_ISRC, &IrqSrc); + } while ((IrqSrc & IS_I2C_READY) == 0); + + pSen->SenState = SK_SEN_IDLE; + return; +} /* SkI2cWaitIrq */ + +/* + * writes a single byte or 4 bytes into the I2C device + * + * returns 0: success + * 1: error + */ +int SkI2cWrite( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 I2cData, /* I2C Data to write */ +int I2cDev, /* I2C Device Address */ +int I2cReg, /* I2C Device Register Address */ +int I2cBurst) /* I2C Burst Flag */ +{ + SK_OUT32(IoC, B2_I2C_DATA, I2cData); + SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cReg, I2cBurst); + + return(SkI2cWait(pAC, IoC, I2C_WRITE)); +} /* SkI2cWrite*/ + + +#ifdef SK_DIAG + +/* + * reads a single byte or 4 bytes from the I2C device + * + * returns the word read + */ +SK_U32 SkI2cRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int I2cDev, /* I2C Device Address */ +int I2cReg, /* I2C Device Register Address */ +int I2cBurst) /* I2C Burst Flag */ +{ + SK_U32 Data; + + SK_OUT32(IoC, B2_I2C_DATA, 0); + SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cReg, I2cBurst); + + if (SkI2cWait(pAC, IoC, I2C_READ) != 0) { + w_print("%s\n", SKERR_I2C_E002MSG); + } + + SK_IN32(IoC, B2_I2C_DATA, &Data); + return(Data); +} /* SkI2cRead */ + +#endif /* SK_DIAG */ + + +/* + * read a sensor's value + * + * This function reads a sensor's value from the I2C sensor chip. The sensor + * is defined by its index into the sensors database in the struct pAC points + * to. + * Returns + * 1 if the read is completed + * 0 if the read must be continued (I2C Bus still allocated) + */ +int SkI2cReadSensor( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_SENSOR *pSen) /* Sensor to be read */ +{ + if (pSen->SenRead != NULL) { + return((*pSen->SenRead)(pAC, IoC, pSen)); + } + else + return(0); /* no success */ +} /* SkI2cReadSensor*/ + +/* + * Do the Init state 0 initialization + */ +static int SkI2cInit0( +SK_AC *pAC) /* Adapter Context */ +{ + int i; + + /* Begin with first sensor */ + pAC->I2c.CurrSens = 0; + + /* Begin with timeout control for state machine */ + pAC->I2c.TimerMode = SK_TIMER_WATCH_STATEMACHINE; + + /* Set sensor number to zero */ + pAC->I2c.MaxSens = 0; + +#ifndef SK_DIAG + /* Initialize Number of Dummy Reads */ + pAC->I2c.DummyReads = SK_MAX_SENSORS; +#endif + + for (i = 0; i < SK_MAX_SENSORS; i++) { + pAC->I2c.SenTable[i].SenDesc = "unknown"; + pAC->I2c.SenTable[i].SenType = SK_SEN_UNKNOWN; + pAC->I2c.SenTable[i].SenThreErrHigh = 0; + pAC->I2c.SenTable[i].SenThreErrLow = 0; + pAC->I2c.SenTable[i].SenThreWarnHigh = 0; + pAC->I2c.SenTable[i].SenThreWarnLow = 0; + pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN; + pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_NONE; + pAC->I2c.SenTable[i].SenValue = 0; + pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_NOT_PRESENT; + pAC->I2c.SenTable[i].SenErrCts = 0; + pAC->I2c.SenTable[i].SenBegErrTS = 0; + pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE; + pAC->I2c.SenTable[i].SenRead = NULL; + pAC->I2c.SenTable[i].SenDev = 0; + } + + /* Now we are "INIT data"ed */ + pAC->I2c.InitLevel = SK_INIT_DATA; + return(0); +} /* SkI2cInit0*/ + + +/* + * Do the init state 1 initialization + * + * initialize the following register of the LM80: + * Configuration register: + * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT + * + * Interrupt Mask Register 1: + * - all interrupts are Disabled (0xff) + * + * Interrupt Mask Register 2: + * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter. + * + * Fan Divisor/RST_OUT register: + * - Divisors set to 1 (bits 00), all others 0s. + * + * OS# Configuration/Temperature resolution Register: + * - all 0s + * + */ +static int SkI2cInit1( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + int i; + SK_U8 I2cSwCtrl; + SK_GEPORT *pPrt; /* GIni Port struct pointer */ + + if (pAC->I2c.InitLevel != SK_INIT_DATA) { + /* ReInit not needed in I2C module */ + return(0); + } + + /* Set the Direction of I2C-Data Pin to IN */ + SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA); + /* Check for 32-Bit Yukon with Low at I2C-Data Pin */ + SK_I2C_GET_SW(IoC, &I2cSwCtrl); + + if ((I2cSwCtrl & I2C_DATA) == 0) { + /* this is a 32-Bit board */ + pAC->GIni.GIYukon32Bit = SK_TRUE; + return(0); + } + + /* Check for 64 Bit Yukon without sensors */ + if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, LM80_CFG, 0) != 0) { + return(0); + } + + (void)SkI2cWrite(pAC, IoC, 0xff, LM80_ADDR, LM80_IMSK_1, 0); + + (void)SkI2cWrite(pAC, IoC, 0xff, LM80_ADDR, LM80_IMSK_2, 0); + + (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, LM80_FAN_CTRL, 0); + + (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, LM80_TEMP_CTRL, 0); + + (void)SkI2cWrite(pAC, IoC, LM80_CFG_START, LM80_ADDR, LM80_CFG, 0); + + /* + * MaxSens has to be updated here, because PhyType is not + * set when performing Init Level 0 + */ + pAC->I2c.MaxSens = 5; + + pPrt = &pAC->GIni.GP[0]; + + if (pAC->GIni.GIGenesis) { + if (pPrt->PhyType == SK_PHY_BCOM) { + if (pAC->GIni.GIMacsFound == 1) { + pAC->I2c.MaxSens += 1; + } + else { + pAC->I2c.MaxSens += 3; + } + } + } + else { + pAC->I2c.MaxSens += 3; + } + + for (i = 0; i < pAC->I2c.MaxSens; i++) { + switch (i) { + case 0: + pAC->I2c.SenTable[i].SenDesc = "Temperature"; + pAC->I2c.SenTable[i].SenType = SK_SEN_TEMP; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_TEMP_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_TEMP_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_TEMP_IN; + break; + case 1: + pAC->I2c.SenTable[i].SenDesc = "Voltage PCI"; + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_VT0_IN; + break; + case 2: + pAC->I2c.SenTable[i].SenDesc = "Voltage PCI-IO"; + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_VT1_IN; + pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_PCI_IO; + break; + case 3: + pAC->I2c.SenTable[i].SenDesc = "Voltage ASIC"; + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VDD_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VDD_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VDD_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_VT2_IN; + break; + case 4: + if (pAC->GIni.GIGenesis) { + if (pPrt->PhyType == SK_PHY_BCOM) { + pAC->I2c.SenTable[i].SenDesc = "Voltage PHY A PLL"; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR; + } + else { + pAC->I2c.SenTable[i].SenDesc = "Voltage PMA"; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR; + } + } + else { + pAC->I2c.SenTable[i].SenDesc = "Voltage VAUX"; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN; + if (pAC->GIni.GIVauxAvail) { + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR; + } + else { + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_0V_WARN_ERR; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_0V_WARN_ERR; + } + } + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenReg = LM80_VT3_IN; + break; + case 5: + if (pAC->GIni.GIGenesis) { + pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5"; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR; + } + else { + pAC->I2c.SenTable[i].SenDesc = "Voltage ASIC-Co 1V5"; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR; + } + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenReg = LM80_VT4_IN; + break; + case 6: + if (pAC->GIni.GIGenesis) { + pAC->I2c.SenTable[i].SenDesc = "Voltage PHY B PLL"; + } + else { + pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 3V3"; + } + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_VT5_IN; + break; + case 7: + if (pAC->GIni.GIGenesis) { + pAC->I2c.SenTable[i].SenDesc = "Speed Fan"; + pAC->I2c.SenTable[i].SenType = SK_SEN_FAN; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_FAN_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_FAN_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_FAN_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN; + } + else { + pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5"; + pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT; + pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR; + pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN; + pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN; + pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR; + pAC->I2c.SenTable[i].SenReg = LM80_VT6_IN; + } + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW, + SKERR_I2C_E001, SKERR_I2C_E001MSG); + break; + } + + pAC->I2c.SenTable[i].SenValue = 0; + pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK; + pAC->I2c.SenTable[i].SenErrCts = 0; + pAC->I2c.SenTable[i].SenBegErrTS = 0; + pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE; + pAC->I2c.SenTable[i].SenRead = SkLm80ReadSensor; + pAC->I2c.SenTable[i].SenDev = LM80_ADDR; + } + +#ifndef SK_DIAG + pAC->I2c.DummyReads = pAC->I2c.MaxSens; +#endif /* !SK_DIAG */ + + /* Clear I2C IRQ */ + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); + + /* Now we are I/O initialized */ + pAC->I2c.InitLevel = SK_INIT_IO; + return(0); +} /* SkI2cInit1 */ + + +/* + * Init level 2: Start first sensor read. + */ +static int SkI2cInit2( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + int ReadComplete; + SK_SENSOR *pSen; + + if (pAC->I2c.InitLevel != SK_INIT_IO) { + /* ReInit not needed in I2C module */ + /* Init0 and Init2 not permitted */ + return(0); + } + + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen); + + if (ReadComplete) { + SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG); + } + + /* Now we are correctly initialized */ + pAC->I2c.InitLevel = SK_INIT_RUN; + + return(0); +} /* SkI2cInit2*/ + + +/* + * Initialize I2C devices + * + * Get the first voltage value and discard it. + * Go into temperature read mode. A default pointer is not set. + * + * The things to be done depend on the init level in the parameter list: + * Level 0: + * Initialize only the data structures. Do NOT access hardware. + * Level 1: + * Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts. + * Level 2: + * Everything is possible. Interrupts may be used from now on. + * + * return: + * 0 = success + * other = error. + */ +int SkI2cInit( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context needed in levels 1 and 2 */ +int Level) /* Init Level */ +{ + + switch (Level) { + case SK_INIT_DATA: + return(SkI2cInit0(pAC)); + case SK_INIT_IO: + return(SkI2cInit1(pAC, IoC)); + case SK_INIT_RUN: + return(SkI2cInit2(pAC, IoC)); + default: + break; + } + + return(0); +} /* SkI2cInit */ + + +#ifndef SK_DIAG + +/* + * Interrupt service function for the I2C Interface + * + * Clears the Interrupt source + * + * Reads the register and check it for sending a trap. + * + * Starts the timer if necessary. + */ +void SkI2cIsr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC) /* I/O Context */ +{ + SK_EVPARA Para; + + /* Clear I2C IRQ */ + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ); + + Para.Para64 = 0; + SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para); +} /* SkI2cIsr */ + + +/* + * Check this sensors Value against the threshold and send events. + */ +static void SkI2cCheckSensor( +SK_AC *pAC, /* Adapter Context */ +SK_SENSOR *pSen) +{ + SK_EVPARA ParaLocal; + SK_BOOL TooHigh; /* Is sensor too high? */ + SK_BOOL TooLow; /* Is sensor too low? */ + SK_U64 CurrTime; /* Current Time */ + SK_BOOL DoTrapSend; /* We need to send a trap */ + SK_BOOL DoErrLog; /* We need to log the error */ + SK_BOOL IsError; /* We need to log the error */ + + /* Check Dummy Reads first */ + if (pAC->I2c.DummyReads > 0) { + pAC->I2c.DummyReads--; + return; + } + + /* Get the current time */ + CurrTime = SkOsGetTime(pAC); + + /* Set para to the most useful setting: The current sensor. */ + ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens; + + /* Check the Value against the thresholds. First: Error Thresholds */ + TooHigh = (pSen->SenValue > pSen->SenThreErrHigh); + TooLow = (pSen->SenValue < pSen->SenThreErrLow); + + IsError = SK_FALSE; + if (TooHigh || TooLow) { + /* Error condition is satisfied */ + DoTrapSend = SK_TRUE; + DoErrLog = SK_TRUE; + + /* Now error condition is satisfied */ + IsError = SK_TRUE; + + if (pSen->SenErrFlag == SK_SEN_ERR_ERR) { + /* This state is the former one */ + + /* So check first whether we have to send a trap */ + if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD > + CurrTime) { + /* + * Do NOT send the Trap. The hold back time + * has to run out first. + */ + DoTrapSend = SK_FALSE; + } + + /* Check now whether we have to log an Error */ + if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD > + CurrTime) { + /* + * Do NOT log the error. The hold back time + * has to run out first. + */ + DoErrLog = SK_FALSE; + } + } + else { + /* We came from a different state -> Set Begin Time Stamp */ + pSen->SenBegErrTS = CurrTime; + pSen->SenErrFlag = SK_SEN_ERR_ERR; + } + + if (DoTrapSend) { + /* Set current Time */ + pSen->SenLastErrTrapTS = CurrTime; + pSen->SenErrCts++; + + /* Queue PNMI Event */ + SkEventQueue(pAC, SKGE_PNMI, (TooHigh ? + SK_PNMI_EVT_SEN_ERR_UPP : + SK_PNMI_EVT_SEN_ERR_LOW), + ParaLocal); + } + + if (DoErrLog) { + /* Set current Time */ + pSen->SenLastErrLogTS = CurrTime; + + if (pSen->SenType == SK_SEN_TEMP) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, + SKERR_I2C_E011MSG); + } else if (pSen->SenType == SK_SEN_VOLT) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, + SKERR_I2C_E012MSG); + } else + { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, + SKERR_I2C_E015MSG); + } + } + } + + /* Check the Value against the thresholds */ + /* 2nd: Warning thresholds */ + TooHigh = (pSen->SenValue > pSen->SenThreWarnHigh); + TooLow = (pSen->SenValue < pSen->SenThreWarnLow); + + if (!IsError && (TooHigh || TooLow)) { + /* Error condition is satisfied */ + DoTrapSend = SK_TRUE; + DoErrLog = SK_TRUE; + + if (pSen->SenErrFlag == SK_SEN_ERR_WARN) { + /* This state is the former one */ + + /* So check first whether we have to send a trap */ + if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > + CurrTime) { + /* + * Do NOT send the Trap. The hold back time + * has to run out first. + */ + DoTrapSend = SK_FALSE; + } + + /* Check now whether we have to log an Error */ + if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > + CurrTime) { + /* + * Do NOT log the error. The hold back time + * has to run out first. + */ + DoErrLog = SK_FALSE; + } + } + else { + /* We came from a different state -> Set Begin Time Stamp */ + pSen->SenBegWarnTS = CurrTime; + pSen->SenErrFlag = SK_SEN_ERR_WARN; + } + + if (DoTrapSend) { + /* Set current Time */ + pSen->SenLastWarnTrapTS = CurrTime; + pSen->SenWarnCts++; + + /* Queue PNMI Event */ + SkEventQueue(pAC, SKGE_PNMI, (TooHigh ? + SK_PNMI_EVT_SEN_WAR_UPP : + SK_PNMI_EVT_SEN_WAR_LOW), + ParaLocal); + } + + if (DoErrLog) { + /* Set current Time */ + pSen->SenLastWarnLogTS = CurrTime; + + if (pSen->SenType == SK_SEN_TEMP) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, + SKERR_I2C_E009MSG); + } else if (pSen->SenType == SK_SEN_VOLT) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, + SKERR_I2C_E010MSG); + } else + { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, + SKERR_I2C_E014MSG); + } + } + } + + /* Check for NO error at all */ + if (!IsError && !TooHigh && !TooLow) { + /* Set o.k. Status if no error and no warning condition */ + pSen->SenErrFlag = SK_SEN_ERR_OK; + } + + /* End of check against the thresholds */ + + /* Bug fix AF: 16.Aug.2001: Correct the init base + * of LM80 sensor. + */ + if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) { + + pSen->SenInit = SK_SEN_DYN_INIT_NONE; + + if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) { + /* 5V PCI-IO Voltage */ + pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR; + } + else { + /* 3.3V PCI-IO Voltage */ + pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN; + pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR; + } + } + +#if 0 + /* Dynamic thresholds also for VAUX of LM80 sensor */ + if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) { + + pSen->SenInit = SK_SEN_DYN_INIT_NONE; + + /* 3.3V VAUX Voltage */ + if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) { + pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN; + pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR; + } + /* 0V VAUX Voltage */ + else { + pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR; + pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR; + } + } + + /* + * Check initialization state: + * The VIO Thresholds need adaption + */ + if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN && + pSen->SenValue > SK_SEN_WARNLOW2C && + pSen->SenValue < SK_SEN_WARNHIGH2) { + pSen->SenThreErrLow = SK_SEN_ERRLOW2C; + pSen->SenThreWarnLow = SK_SEN_WARNLOW2C; + pSen->SenInit = SK_TRUE; + } + + if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN && + pSen->SenValue > SK_SEN_WARNLOW2 && + pSen->SenValue < SK_SEN_WARNHIGH2C) { + pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C; + pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C; + pSen->SenInit = SK_TRUE; + } +#endif + + if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) { + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG); + } +} /* SkI2cCheckSensor*/ + + +/* + * The only Event to be served is the timeout event + * + */ +int SkI2cEvent( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Event, /* Module specific Event */ +SK_EVPARA Para) /* Event specific Parameter */ +{ + int ReadComplete; + SK_SENSOR *pSen; + SK_U32 Time; + SK_EVPARA ParaLocal; + int i; + + /* New case: no sensors */ + if (pAC->I2c.MaxSens == 0) { + return(0); + } + + switch (Event) { + case SK_I2CEV_IRQ: + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen); + + if (ReadComplete) { + /* Check sensor against defined thresholds */ + SkI2cCheckSensor (pAC, pSen); + + /* Increment Current sensor and set appropriate Timeout */ + pAC->I2c.CurrSens++; + if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) { + pAC->I2c.CurrSens = 0; + Time = SK_I2C_TIM_LONG; + } + else { + Time = SK_I2C_TIM_SHORT; + } + + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + else { + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_WATCH_STATEMACHINE; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + break; + case SK_I2CEV_TIM: + if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) { + + ParaLocal.Para64 = (SK_U64)0; + SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer); + + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen); + + if (ReadComplete) { + /* Check sensor against defined thresholds */ + SkI2cCheckSensor (pAC, pSen); + + /* Increment Current sensor and set appropriate Timeout */ + pAC->I2c.CurrSens++; + if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) { + pAC->I2c.CurrSens = 0; + Time = SK_I2C_TIM_LONG; + } + else { + Time = SK_I2C_TIM_SHORT; + } + + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + } + else { + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens]; + pSen->SenErrFlag = SK_SEN_ERR_FAULTY; + SK_I2C_STOP(IoC); + + /* Increment Current sensor and set appropriate Timeout */ + pAC->I2c.CurrSens++; + if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) { + pAC->I2c.CurrSens = 0; + Time = SK_I2C_TIM_LONG; + } + else { + Time = SK_I2C_TIM_SHORT; + } + + /* Start Timer */ + ParaLocal.Para64 = (SK_U64)0; + + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING; + + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time, + SKGE_I2C, SK_I2CEV_TIM, ParaLocal); + } + break; + case SK_I2CEV_CLEAR: + for (i = 0; i < SK_MAX_SENSORS; i++) { + pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK; + pAC->I2c.SenTable[i].SenErrCts = 0; + pAC->I2c.SenTable[i].SenWarnCts = 0; + pAC->I2c.SenTable[i].SenBegErrTS = 0; + pAC->I2c.SenTable[i].SenBegWarnTS = 0; + pAC->I2c.SenTable[i].SenLastErrTrapTS = (SK_U64)0; + pAC->I2c.SenTable[i].SenLastErrLogTS = (SK_U64)0; + pAC->I2c.SenTable[i].SenLastWarnTrapTS = (SK_U64)0; + pAC->I2c.SenTable[i].SenLastWarnLogTS = (SK_U64)0; + } + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG); + } + + return(0); +} /* SkI2cEvent*/ + +#endif /* !SK_DIAG */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/sklm80.c b/drivers/sk98lin/sklm80.c new file mode 100644 index 000000000..687572b1d --- /dev/null +++ b/drivers/sk98lin/sklm80.c @@ -0,0 +1,292 @@ +/****************************************************************************** + * + * Name: sklm80.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.20 $ + * Date: $Date: 2002/08/13 09:16:27 $ + * Purpose: Funktions to access Voltage and Temperature Sensor (LM80) + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2002 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: sklm80.c,v $ + * Revision 1.20 2002/08/13 09:16:27 rschmidt + * Changed return value for SkLm80ReadSensor() back to 'int' + * Editorial changes + * + * Revision 1.19 2002/08/06 09:43:31 jschmalz + * Extensions and changes for Yukon + * + * Revision 1.18 2002/08/02 12:26:57 rschmidt + * Editorial changes + * + * Revision 1.17 1999/11/22 13:35:51 cgoos + * Changed license header to GPL. + * + * Revision 1.16 1999/05/27 14:05:47 malthoff + * Fans: Set SenVal to 0 if the fan value is 0 or 0xff. Both values + * are outside the limits (0: div zero error, 0xff: value not in + * range, assume 0). + * + * Revision 1.15 1999/05/27 13:38:51 malthoff + * Pervent from Division by zero errors. + * + * Revision 1.14 1999/05/20 09:20:01 cgoos + * Changes for 1000Base-T (Fan sensors). + * + * Revision 1.13 1998/10/22 09:48:14 gklug + * fix: SysKonnectFileId typo + * + * Revision 1.12 1998/10/09 06:12:06 malthoff + * Remove ID_sccs by SysKonnectFileId. + * + * Revision 1.11 1998/09/04 08:33:48 malthoff + * bug fix: SenState = SK_SEN_IDLE when + * leaving SK_SEN_VALEXT state + * + * Revision 1.10 1998/08/20 12:02:10 gklug + * fix: compiler warnings type mismatch + * + * Revision 1.9 1998/08/20 11:37:38 gklug + * chg: change Ioc to IoC + * + * Revision 1.8 1998/08/19 12:20:58 gklug + * fix: remove struct from C files (see CCC) + * + * Revision 1.7 1998/08/17 07:04:57 malthoff + * Take SkLm80RcvReg() function from ski2c.c. + * Add IoC parameter to BREAK_OR_WAIT() macro. + * + * Revision 1.6 1998/08/14 07:11:28 malthoff + * remove pAc with pAC. + * + * Revision 1.5 1998/08/14 06:46:55 gklug + * fix: temperature can get negative + * + * Revision 1.4 1998/08/13 08:27:04 gklug + * add: temperature reading now o.k. + * fix: pSen declaration, SK_ERR_LOG call, ADDR macro + * + * Revision 1.3 1998/08/13 07:28:21 gklug + * fix: pSen was wrong initialized + * add: correct conversion for voltage readings + * + * Revision 1.2 1998/08/11 07:52:14 gklug + * add: Lm80 read sensor function + * + * Revision 1.1 1998/07/17 09:57:12 gklug + * initial version + * + * + * + ******************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +/* + LM80 functions +*/ +static const char SysKonnectFileId[] = + "$Id: sklm80.c,v 1.20 2002/08/13 09:16:27 rschmidt Exp $" ; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/lm80.h" +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef SK_DIAG +#define BREAK_OR_WAIT(pAC,IoC,Event) SkI2cWait(pAC,IoC,Event) +#else /* nSK_DIAG */ +#define BREAK_OR_WAIT(pAC,IoC,Event) break +#endif /* nSK_DIAG */ + +#ifdef SK_DIAG +/* + * read the register 'Reg' from the device 'Dev' + * + * return read error -1 + * success the read value + */ +int SkLm80RcvReg( +SK_IOC IoC, /* Adapter Context */ +int Dev, /* I2C device address */ +int Reg) /* register to read */ +{ + int Val = 0; + int TempExt; + + /* Signal device number */ + if (SkI2cSndDev(IoC, Dev, I2C_WRITE)) { + return(-1); + } + + if (SkI2cSndByte(IoC, Reg)) { + return(-1); + } + + /* repeat start */ + if (SkI2cSndDev(IoC, Dev, I2C_READ)) { + return(-1); + } + + switch (Reg) { + case LM80_TEMP_IN: + Val = (int)SkI2cRcvByte(IoC, 1); + + /* First: correct the value: it might be negative */ + if ((Val & 0x80) != 0) { + /* Value is negative */ + Val = Val - 256; + } + Val = Val * SK_LM80_TEMP_LSB; + SkI2cStop(IoC); + + TempExt = (int)SkLm80RcvReg(IoC, LM80_ADDR, LM80_TEMP_CTRL); + + if (Val > 0) { + Val += ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB); + } + else { + Val -= ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB); + } + return(Val); + break; + case LM80_VT0_IN: + case LM80_VT1_IN: + case LM80_VT2_IN: + case LM80_VT3_IN: + Val = (int)SkI2cRcvByte(IoC, 1) * SK_LM80_VT_LSB; + break; + + default: + Val = (int)SkI2cRcvByte(IoC, 1); + break; + } + + SkI2cStop(IoC); + return(Val); +} +#endif /* SK_DIAG */ + +/* + * read a sensors value (LM80 specific) + * + * This function reads a sensors value from the I2C sensor chip LM80. + * The sensor is defined by its index into the sensors database in the struct + * pAC points to. + * + * Returns 1 if the read is completed + * 0 if the read must be continued (I2C Bus still allocated) + */ +int SkLm80ReadSensor( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context needed in level 1 and 2 */ +SK_SENSOR *pSen) /* Sensor to be read */ +{ + SK_I32 Value; + + switch (pSen->SenState) { + case SK_SEN_IDLE: + /* Send address to ADDR register */ + SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, pSen->SenReg, 0); + + pSen->SenState = SK_SEN_VALUE ; + BREAK_OR_WAIT(pAC, IoC, I2C_READ); + + case SK_SEN_VALUE: + /* Read value from data register */ + SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value)); + + Value &= 0xff; /* only least significant byte is valid */ + + /* Do NOT check the Value against the thresholds */ + /* Checking is done in the calling instance */ + + if (pSen->SenType == SK_SEN_VOLT) { + /* Voltage sensor */ + pSen->SenValue = Value * SK_LM80_VT_LSB; + pSen->SenState = SK_SEN_IDLE ; + return(1); + } + + if (pSen->SenType == SK_SEN_FAN) { + if (Value != 0 && Value != 0xff) { + /* Fan speed counter */ + pSen->SenValue = SK_LM80_FAN_FAKTOR/Value; + } + else { + /* Indicate Fan error */ + pSen->SenValue = 0; + } + pSen->SenState = SK_SEN_IDLE ; + return(1); + } + + /* First: correct the value: it might be negative */ + if ((Value & 0x80) != 0) { + /* Value is negative */ + Value = Value - 256; + } + + /* We have a temperature sensor and need to get the signed extension. + * For now we get the extension from the last reading, so in the normal + * case we won't see flickering temperatures. + */ + pSen->SenValue = (Value * SK_LM80_TEMP_LSB) + + (pSen->SenValue % SK_LM80_TEMP_LSB); + + /* Send address to ADDR register */ + SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, LM80_TEMP_CTRL, 0); + + pSen->SenState = SK_SEN_VALEXT ; + BREAK_OR_WAIT(pAC, IoC, I2C_READ); + + case SK_SEN_VALEXT: + /* Read value from data register */ + SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value)); + Value &= LM80_TEMP_LSB_9; /* only bit 7 is valid */ + + /* cut the LSB bit */ + pSen->SenValue = ((pSen->SenValue / SK_LM80_TEMP_LSB) * + SK_LM80_TEMP_LSB); + + if (pSen->SenValue < 0) { + /* Value negative: The bit value must be subtracted */ + pSen->SenValue -= ((Value >> 7) * SK_LM80_TEMPEXT_LSB); + } + else { + /* Value positive: The bit value must be added */ + pSen->SenValue += ((Value >> 7) * SK_LM80_TEMPEXT_LSB); + } + + pSen->SenState = SK_SEN_IDLE ; + return(1); + + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E007, SKERR_I2C_E007MSG); + return(1); + } + + /* Not completed */ + return(0); +} + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skproc.c b/drivers/sk98lin/skproc.c new file mode 100644 index 000000000..4e340730e --- /dev/null +++ b/drivers/sk98lin/skproc.c @@ -0,0 +1,515 @@ +/****************************************************************************** + * + * Name: skproc.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.4 $ + * Date: $Date: 2003/02/25 14:16:37 $ + * Purpose: Funktions to display statictic data + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Created 22-Nov-2000 + * Author: Mirko Lindner (mlindner@syskonnect.de) + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ +/****************************************************************************** + * + * History: + * + * $Log: skproc.c,v $ + * Revision 1.4 2003/02/25 14:16:37 mlindner + * Fix: Copyright statement + * + * Revision 1.3 2002/10/02 12:59:51 mlindner + * Add: Support for Yukon + * Add: Speed check and setup + * Add: Merge source for kernel 2.2.x and 2.4.x + * Add: Read sensor names directly from VPD + * Fix: Volt values + * + * Revision 1.2.2.7 2002/01/14 12:45:15 mlindner + * Fix: Editorial changes + * + * Revision 1.2.2.6 2001/12/06 15:26:07 mlindner + * Fix: Return value of proc_read + * + * Revision 1.2.2.5 2001/12/06 09:57:39 mlindner + * New ProcFs entries + * + * Revision 1.2.2.4 2001/09/05 12:16:02 mlindner + * Add: New ProcFs entries + * Fix: Counter Errors (Jumbo == to long errors) + * Fix: Kernel error compilation + * Fix: too short counters + * + * Revision 1.2.2.3 2001/06/25 07:26:26 mlindner + * Add: More error messages + * + * Revision 1.2.2.2 2001/03/15 12:50:13 mlindner + * fix: ProcFS owner protection + * + * Revision 1.2.2.1 2001/03/12 16:43:48 mlindner + * chg: 2.4 requirements for procfs + * + * Revision 1.1 2001/01/22 14:15:31 mlindner + * added ProcFs functionality + * Dual Net functionality integrated + * Rlmt networks added + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" +#define ZEROPAD 1 /* pad with zero */ +#define SIGN 2 /* unsigned/signed long */ +#define PLUS 4 /* show plus */ +#define SPACE 8 /* space if plus */ +#define LEFT 16 /* left justified */ +#define SPECIALX 32 /* 0x */ +#define LARGE 64 + +extern SK_AC *pACList; +extern struct net_device *SkGeRootDev; + +extern char * SkNumber( + char * str, + long long num, + int base, + int size, + int precision, + int type); + + +/***************************************************************************** + * + * proc_read - print "summaries" entry + * + * Description: + * This function fills the proc entry with statistic data about + * the ethernet device. + * + * + * Returns: buffer with statistic data + * + */ +int proc_read(char *buffer, +char **buffer_location, +off_t offset, +int buffer_length, +int *eof, +void *data) +{ + int len = 0; + int t; + int i; + DEV_NET *pNet; + SK_AC *pAC; + char test_buf[100]; + char sens_msg[50]; + unsigned long Flags; + unsigned int Size; + struct SK_NET_DEVICE *next; + struct SK_NET_DEVICE *SkgeProcDev = SkGeRootDev; + + SK_PNMI_STRUCT_DATA *pPnmiStruct; + SK_PNMI_STAT *pPnmiStat; + struct proc_dir_entry *file = (struct proc_dir_entry*) data; + + while (SkgeProcDev) { + pNet = (DEV_NET*) SkgeProcDev->priv; + pAC = pNet->pAC; + next = pAC->Next; + pPnmiStruct = &pAC->PnmiStruct; + /* NetIndex in GetStruct is now required, zero is only dummy */ + + for (t=pAC->GIni.GIMacsFound; t > 0; t--) { + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 1) + t--; + + spin_lock_irqsave(&pAC->SlowPathLock, Flags); + Size = SK_PNMI_STRUCT_SIZE; + SkPnmiGetStruct(pAC, pAC->IoBase, + pPnmiStruct, &Size, t-1); + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags); + + if (strcmp(pAC->dev[t-1]->name, file->name) == 0) { + pPnmiStat = &pPnmiStruct->Stat[0]; + len = sprintf(buffer, + "\nDetailed statistic for device %s\n", + pAC->dev[t-1]->name); + len += sprintf(buffer + len, + "=======================================\n"); + + /* Board statistics */ + len += sprintf(buffer + len, + "\nBoard statistics\n\n"); + len += sprintf(buffer + len, + "Active Port %c\n", + 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt. + Net[t-1].PrefPort]->PortNumber); + len += sprintf(buffer + len, + "Preferred Port %c\n", + 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt. + Net[t-1].PrefPort]->PortNumber); + + len += sprintf(buffer + len, + "Bus speed (MHz) %d\n", + pPnmiStruct->BusSpeed); + + len += sprintf(buffer + len, + "Bus width (Bit) %d\n", + pPnmiStruct->BusWidth); + len += sprintf(buffer + len, + "Hardware revision v%d.%d\n", + (pAC->GIni.GIPciHwRev >> 4) & 0x0F, + pAC->GIni.GIPciHwRev & 0x0F); + + /* Print sensor informations */ + for (i=0; i < pAC->I2c.MaxSens; i ++) { + /* Check type */ + switch (pAC->I2c.SenTable[i].SenType) { + case 1: + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (C)"); + len += sprintf(buffer + len, + "%-25s %d.%02d\n", + sens_msg, + pAC->I2c.SenTable[i].SenValue / 10, + pAC->I2c.SenTable[i].SenValue % 10); + + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (F)"); + len += sprintf(buffer + len, + "%-25s %d.%02d\n", + sens_msg, + ((((pAC->I2c.SenTable[i].SenValue) + *10)*9)/5 + 3200)/100, + ((((pAC->I2c.SenTable[i].SenValue) + *10)*9)/5 + 3200) % 10); + break; + case 2: + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (V)"); + len += sprintf(buffer + len, + "%-25s %d.%03d\n", + sens_msg, + pAC->I2c.SenTable[i].SenValue / 1000, + pAC->I2c.SenTable[i].SenValue % 1000); + break; + case 3: + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc); + strcat(sens_msg, " (rpm)"); + len += sprintf(buffer + len, + "%-25s %d\n", + sens_msg, + pAC->I2c.SenTable[i].SenValue); + break; + default: + break; + } + } + + /*Receive statistics */ + len += sprintf(buffer + len, + "\nReceive statistics\n\n"); + + len += sprintf(buffer + len, + "Received bytes %s\n", + SkNumber(test_buf, pPnmiStat->StatRxOctetsOkCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Received packets %s\n", + SkNumber(test_buf, pPnmiStat->StatRxOkCts, + 10,0,-1,0)); +#if 0 + if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && + pAC->HWRevision < 12) { + pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts - + pPnmiStat->StatRxShortsCts; + pPnmiStat->StatRxShortsCts = 0; + } +#endif + if (pNet->Mtu > 1500) + pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts - + pPnmiStat->StatRxTooLongCts; + + len += sprintf(buffer + len, + "Receive errors %s\n", + SkNumber(test_buf, pPnmiStruct->InErrorsCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Receive drops %s\n", + SkNumber(test_buf, pPnmiStruct->RxNoBufCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Received multicast %s\n", + SkNumber(test_buf, pPnmiStat->StatRxMulticastOkCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Receive error types\n"); + len += sprintf(buffer + len, + " length %s\n", + SkNumber(test_buf, pPnmiStat->StatRxRuntCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " buffer overflow %s\n", + SkNumber(test_buf, pPnmiStat->StatRxFifoOverflowCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " bad crc %s\n", + SkNumber(test_buf, pPnmiStat->StatRxFcsCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " framing %s\n", + SkNumber(test_buf, pPnmiStat->StatRxFramingCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " missed frames %s\n", + SkNumber(test_buf, pPnmiStat->StatRxMissedCts, + 10, 0, -1, 0)); + + if (pNet->Mtu > 1500) + pPnmiStat->StatRxTooLongCts = 0; + + len += sprintf(buffer + len, + " too long %s\n", + SkNumber(test_buf, pPnmiStat->StatRxTooLongCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " carrier extension %s\n", + SkNumber(test_buf, pPnmiStat->StatRxCextCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " too short %s\n", + SkNumber(test_buf, pPnmiStat->StatRxShortsCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " symbol %s\n", + SkNumber(test_buf, pPnmiStat->StatRxSymbolCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " LLC MAC size %s\n", + SkNumber(test_buf, pPnmiStat->StatRxIRLengthCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " carrier event %s\n", + SkNumber(test_buf, pPnmiStat->StatRxCarrierCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " jabber %s\n", + SkNumber(test_buf, pPnmiStat->StatRxJabberCts, + 10, 0, -1, 0)); + + + /*Transmit statistics */ + len += sprintf(buffer + len, + "\nTransmit statistics\n\n"); + + len += sprintf(buffer + len, + "Transmited bytes %s\n", + SkNumber(test_buf, pPnmiStat->StatTxOctetsOkCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Transmited packets %s\n", + SkNumber(test_buf, pPnmiStat->StatTxOkCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Transmit errors %s\n", + SkNumber(test_buf, pPnmiStat->StatTxSingleCollisionCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Transmit dropped %s\n", + SkNumber(test_buf, pPnmiStruct->TxNoBufCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Transmit collisions %s\n", + SkNumber(test_buf, pPnmiStat->StatTxSingleCollisionCts, + 10,0,-1,0)); + len += sprintf(buffer + len, + "Transmit errors types\n"); + len += sprintf(buffer + len, + " excessive collision %ld\n", + pAC->stats.tx_aborted_errors); + len += sprintf(buffer + len, + " carrier %s\n", + SkNumber(test_buf, pPnmiStat->StatTxCarrierCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " fifo underrun %s\n", + SkNumber(test_buf, pPnmiStat->StatTxFifoUnderrunCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " heartbeat %s\n", + SkNumber(test_buf, pPnmiStat->StatTxCarrierCts, + 10, 0, -1, 0)); + len += sprintf(buffer + len, + " window %ld\n", + pAC->stats.tx_window_errors); + + } + } + SkgeProcDev = next; + } + if (offset >= len) { + *eof = 1; + return 0; + } + + *buffer_location = buffer + offset; + if (buffer_length >= len - offset) { + *eof = 1; + } + return (min_t(int, buffer_length, len - offset)); +} + + +/***************************************************************************** + * + * SkDoDiv - convert 64bit number + * + * Description: + * This function "converts" a long long number. + * + * Returns: + * remainder of division + */ +static long SkDoDiv (long long Dividend, int Divisor, long long *pErg) +{ + long Rest; + long long Ergebnis; + long Akku; + + + Akku = Dividend >> 32; + + Ergebnis = ((long long) (Akku / Divisor)) << 32; + Rest = Akku % Divisor ; + + Akku = Rest << 16; + Akku |= ((Dividend & 0xFFFF0000) >> 16); + + + Ergebnis += ((long long) (Akku / Divisor)) << 16; + Rest = Akku % Divisor ; + + Akku = Rest << 16; + Akku |= (Dividend & 0xFFFF); + + Ergebnis += (Akku / Divisor); + Rest = Akku % Divisor ; + + *pErg = Ergebnis; + return (Rest); +} + + +#if 0 +#define do_div(n,base) ({ \ +long long __res; \ +__res = ((unsigned long long) n) % (unsigned) base; \ +n = ((unsigned long long) n) / (unsigned) base; \ +__res; }) + +#endif + + +/***************************************************************************** + * + * SkNumber - Print results + * + * Description: + * This function converts a long long number into a string. + * + * Returns: + * number as string + */ +char * SkNumber(char * str, long long num, int base, int size, int precision + ,int type) +{ + char c,sign,tmp[66], *strorg = str; + const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; + int i; + + if (type & LARGE) + digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + if (type & LEFT) + type &= ~ZEROPAD; + if (base < 2 || base > 36) + return 0; + c = (type & ZEROPAD) ? '0' : ' '; + sign = 0; + if (type & SIGN) { + if (num < 0) { + sign = '-'; + num = -num; + size--; + } else if (type & PLUS) { + sign = '+'; + size--; + } else if (type & SPACE) { + sign = ' '; + size--; + } + } + if (type & SPECIALX) { + if (base == 16) + size -= 2; + else if (base == 8) + size--; + } + i = 0; + if (num == 0) + tmp[i++]='0'; + else while (num != 0) + tmp[i++] = digits[SkDoDiv(num,base, &num)]; + + if (i > precision) + precision = i; + size -= precision; + if (!(type&(ZEROPAD+LEFT))) + while(size-->0) + *str++ = ' '; + if (sign) + *str++ = sign; + if (type & SPECIALX) { + if (base==8) + *str++ = '0'; + else if (base==16) { + *str++ = '0'; + *str++ = digits[33]; + } + } + if (!(type & LEFT)) + while (size-- > 0) + *str++ = c; + while (i < precision--) + *str++ = '0'; + while (i-- > 0) + *str++ = tmp[i]; + while (size-- > 0) + *str++ = ' '; + + str[0] = '\0'; + + return strorg; +} + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skqueue.c b/drivers/sk98lin/skqueue.c new file mode 100644 index 000000000..c49baed4f --- /dev/null +++ b/drivers/sk98lin/skqueue.c @@ -0,0 +1,242 @@ +/****************************************************************************** + * + * Name: skqueue.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.18 $ + * Date: $Date: 2002/05/07 14:11:11 $ + * Purpose: Management of an event queue. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skqueue.c,v $ + * Revision 1.18 2002/05/07 14:11:11 rwahl + * Fixed Watcom Precompiler error. + * + * Revision 1.17 2002/03/25 10:06:41 mkunz + * SkIgnoreEvent deleted + * + * Revision 1.16 2002/03/15 10:51:59 mkunz + * Added event classes for link aggregation + * + * Revision 1.15 1999/11/22 13:36:29 cgoos + * Changed license header to GPL. + * + * Revision 1.14 1998/10/15 15:11:35 gklug + * fix: ID_sccs to SysKonnectFileId + * + * Revision 1.13 1998/09/08 08:47:52 gklug + * add: init level handling + * + * Revision 1.12 1998/09/08 07:43:20 gklug + * fix: Sirq Event function name + * + * Revision 1.11 1998/09/08 05:54:34 gklug + * chg: define SK_CSUM is replaced by SK_USE_CSUM + * + * Revision 1.10 1998/09/03 14:14:49 gklug + * add: CSUM and HWAC Eventclass and function. + * + * Revision 1.9 1998/08/19 09:50:50 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.8 1998/08/17 13:43:11 gklug + * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR + * + * Revision 1.7 1998/08/14 07:09:11 gklug + * fix: chg pAc -> pAC + * + * Revision 1.6 1998/08/11 12:13:14 gklug + * add: return code feature of Event service routines + * add: correct Error log calls + * + * Revision 1.5 1998/08/07 12:53:45 gklug + * fix: first compiled version + * + * Revision 1.4 1998/08/07 09:20:48 gklug + * adapt functions to C coding conventions. + * + * Revision 1.3 1998/08/05 11:29:32 gklug + * rmv: Timer event entry. Timer will queue event directly + * + * Revision 1.2 1998/07/31 11:22:40 gklug + * Initial version + * + * Revision 1.1 1998/07/30 15:14:01 gklug + * Initial version. Adapted from SMT + * + * + * + ******************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +/* + Event queue and dispatcher +*/ +static const char SysKonnectFileId[] = + "$Header: /usr56/projects/ge/schedule/skqueue.c,v 1.18 2002/05/07 14:11:11 rwahl Exp $" ; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/skqueue.h" /* Queue Definitions */ +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef __C2MAN__ +/* + Event queue management. + + General Description: + + */ +intro() +{} +#endif + +#define PRINTF(a,b,c) + +/* + * init event queue management + * + * Must be called during init level 0. + */ +void SkEventInit( +SK_AC *pAC, /* Adapter context */ +SK_IOC Ioc, /* IO context */ +int Level) /* Init level */ +{ + switch (Level) { + case SK_INIT_DATA: + pAC->Event.EvPut = pAC->Event.EvGet = pAC->Event.EvQueue ; + break; + default: + break; + } +} + +/* + * add event to queue + */ +void SkEventQueue( +SK_AC *pAC, /* Adapters context */ +SK_U32 Class, /* Event Class */ +SK_U32 Event, /* Event to be queued */ +SK_EVPARA Para) /* Event parameter */ +{ + pAC->Event.EvPut->Class = Class ; + pAC->Event.EvPut->Event = Event ; + pAC->Event.EvPut->Para = Para ; + if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT]) + pAC->Event.EvPut = pAC->Event.EvQueue ; + + if (pAC->Event.EvPut == pAC->Event.EvGet) { + SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG) ; + } +} + +/* + * event dispatcher + * while event queue is not empty + * get event from queue + * send command to state machine + * end + * return error reported by individual Event function + * 0 if no error occured. + */ +int SkEventDispatcher( +SK_AC *pAC, /* Adapters Context */ +SK_IOC Ioc) /* Io context */ +{ + SK_EVENTELEM *pEv ; /* pointer into queue */ + SK_U32 Class ; + int Rtv ; + + pEv = pAC->Event.EvGet ; + PRINTF("dispatch get %x put %x\n",pEv,pAC->Event.ev_put) ; + while (pEv != pAC->Event.EvPut) { + PRINTF("dispatch Class %d Event %d\n",pEv->Class,pEv->Event) ; + switch(Class = pEv->Class) { +#ifndef SK_USE_LAC_EV + case SKGE_RLMT : /* RLMT Event */ + Rtv = SkRlmtEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; + case SKGE_I2C : /* I2C Event */ + Rtv = SkI2cEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; + case SKGE_PNMI : + Rtv = SkPnmiEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#endif /* SK_USE_LAC_EV */ + case SKGE_DRV : /* Driver Event */ + Rtv = SkDrvEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#ifndef SK_USE_SW_TIMER + case SKGE_HWAC : + Rtv = SkGeSirqEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#else /* !SK_USE_SW_TIMER */ + case SKGE_SWT : + Rtv = SkSwtEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#endif /* !SK_USE_SW_TIMER */ +#ifdef SK_USE_LAC_EV + case SKGE_LACP : + Rtv = SkLacpEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; + case SKGE_RSF : + Rtv = SkRsfEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; + case SKGE_MARKER : + Rtv = SkMarkerEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; + case SKGE_FD : + Rtv = SkFdEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#endif /* SK_USE_LAC_EV */ +#ifdef SK_USE_CSUM + case SKGE_CSUM : + Rtv = SkCsEvent(pAC,Ioc,pEv->Event,pEv->Para); + break ; +#endif /* SK_USE_CSUM */ + default : + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E002, + SKERR_Q_E002MSG) ; + Rtv = 0; + } + + if (Rtv != 0) { + return(Rtv) ; + } + + if (++pEv == &pAC->Event.EvQueue[SK_MAX_EVENT]) + pEv = pAC->Event.EvQueue ; + + /* Renew get: it is used in queue_events to detect overruns */ + pAC->Event.EvGet = pEv; + } + + return(0) ; +} + +#endif /* CONFIG_SK98 */ + +/* End of file */ diff --git a/drivers/sk98lin/skrlmt.c b/drivers/sk98lin/skrlmt.c new file mode 100644 index 000000000..f8a3b41f0 --- /dev/null +++ b/drivers/sk98lin/skrlmt.c @@ -0,0 +1,3508 @@ +/****************************************************************************** + * + * Name: skrlmt.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.68 $ + * Date: $Date: 2003/01/31 15:26:56 $ + * Purpose: Manage links on SK-NET Adapters, esp. redundant ones. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2001 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skrlmt.c,v $ + * Revision 1.68 2003/01/31 15:26:56 rschmidt + * Added init for local variables in RlmtInit(). + * + * Revision 1.67 2003/01/31 14:12:41 mkunz + * single port adapter runs now with two identical MAC addresses + * + * Revision 1.66 2002/09/23 15:14:19 rwahl + * - Reset broadcast timestamp on link down. + * - Editorial corrections. + * + * Revision 1.65 2002/07/22 14:29:48 rwahl + * - Removed BRK statement from debug check. + * + * Revision 1.64 2001/11/28 19:36:14 rwahl + * - RLMT Packets sent to an invalid MAC address in CLP/CLPSS mode + * (#10650). + * - Reworked fix for port switching in CLS mode (#10639) + * (no dependency to RLMT module). + * - Enabled dbg output for entry/exit of event functions. + * - Editorial changes. + * + * Revision 1.63 2001/10/26 07:53:18 afischer + * Port switching bug in `check local link` mode + * + * Revision 1.62 2001/07/03 12:16:30 mkunz + * New Flag ChgBcPrio (Change priority of last broadcast received) + * + * Revision 1.61 2001/03/14 12:52:08 rassmann + * Fixed reporting of active port up/down to PNMI. + * + * Revision 1.60 2001/02/21 16:02:25 gklug + * fix: when RLMT starts set Active Port for PNMI + * + * Revision 1.59 2001/02/16 14:38:19 rassmann + * Initializing some pointers earlier in the init phase. + * Rx Mbufs are freed if the net which they belong to is stopped. + * + * Revision 1.58 2001/02/14 14:06:31 rassmann + * Editorial changes. + * + * Revision 1.57 2001/02/05 14:25:26 rassmann + * Prepared RLMT for transparent operation. + * + * Revision 1.56 2001/01/30 10:29:09 rassmann + * Not checking switching befor RlmtStart. + * Editorial changes. + * + * Revision 1.55 2001/01/22 13:41:38 rassmann + * Supporting two nets on dual-port adapters. + * + * Revision 1.54 2000/11/30 13:25:07 rassmann + * Setting SK_TICK_INCR to 1 by default. + * + * Revision 1.53 2000/11/30 10:48:07 cgoos + * Changed definition of SK_RLMT_BC_DELTA. + * + * Revision 1.52 2000/11/27 12:50:03 rassmann + * Checking ports after receiving broadcasts. + * + * Revision 1.51 2000/11/17 08:58:00 rassmann + * Moved CheckSwitch from SK_RLMT_PACKET_RECEIVED to SK_RLMT_TIM event. + * + * Revision 1.50 2000/11/09 12:24:34 rassmann + * Indicating that segmentation check is not running anymore after + * SkRlmtCheckSeg(). + * Restarting segmentation timer after segmentation log. + * Editorial changes. + * + * Revision 1.49 1999/11/22 13:38:02 cgoos + * Changed license header to GPL. + * Added initialization to some variables to avoid compiler warnings. + * + * Revision 1.48 1999/10/04 14:01:17 rassmann + * Corrected reaction to reception of BPDU frames (#10441). + * + * Revision 1.47 1999/07/20 12:53:36 rassmann + * Fixed documentation errors for lookahead macros. + * + * Revision 1.46 1999/05/28 13:29:16 rassmann + * Replaced C++-style comment. + * + * Revision 1.45 1999/05/28 13:28:08 rassmann + * Corrected syntax error (xxx). + * + * Revision 1.44 1999/05/28 11:15:54 rassmann + * Changed behaviour to reflect Design Spec v1.2. + * Controlling Link LED(s). + * Introduced RLMT Packet Version field in RLMT Packet. + * Newstyle lookahead macros (checking meta-information before looking at + * the packet). + * + * Revision 1.43 1999/01/28 13:12:43 rassmann + * Corrected Lookahead (bug introduced in previous Rev.). + * + * Revision 1.42 1999/01/28 12:50:41 rassmann + * Not using broadcast time stamps in CheckLinkState mode. + * + * Revision 1.41 1999/01/27 14:13:02 rassmann + * Monitoring broadcast traffic. + * Switching more reliably and not too early if switch is + * configured for spanning tree. + * + * Revision 1.40 1999/01/22 13:17:30 rassmann + * Informing PNMI of NET_UP. + * Clearing RLMT multicast addresses before setting them for the first time. + * Reporting segmentation earlier, setting a "quiet time" + * after a report. + * + * Revision 1.39 1998/12/10 15:29:53 rassmann + * Corrected SuspectStatus in SkRlmtBuildCheckChain(). + * Corrected CHECK_SEG mode. + * + * Revision 1.38 1998/12/08 13:11:23 rassmann + * Stopping SegTimer at RlmtStop. + * + * Revision 1.37 1998/12/07 16:51:42 rassmann + * Corrected comments. + * + * Revision 1.36 1998/12/04 10:58:56 rassmann + * Setting next pointer to NULL when receiving. + * + * Revision 1.35 1998/12/03 16:12:42 rassmann + * Ignoring/correcting illegal PrefPort values. + * + * Revision 1.34 1998/12/01 11:45:35 rassmann + * Code cleanup. + * + * Revision 1.33 1998/12/01 10:29:32 rassmann + * Starting standby ports before getting the net up. + * Checking if a port is started when the link comes up. + * + * Revision 1.32 1998/11/30 16:19:50 rassmann + * New default for PortNoRx. + * + * Revision 1.31 1998/11/27 19:17:13 rassmann + * Corrected handling of LINK_DOWN coming shortly after LINK_UP. + * + * Revision 1.30 1998/11/24 12:37:31 rassmann + * Implemented segmentation check. + * + * Revision 1.29 1998/11/18 13:04:32 rassmann + * Secured PortUpTimer event. + * Waiting longer before starting standby port(s). + * + * Revision 1.28 1998/11/17 13:43:04 rassmann + * Handling (logical) tx failure. + * Sending packet on logical address after PORT_SWITCH. + * + * Revision 1.27 1998/11/13 17:09:50 rassmann + * Secured some events against being called in wrong state. + * + * Revision 1.26 1998/11/13 16:56:54 rassmann + * Added macro version of SkRlmtLookaheadPacket. + * + * Revision 1.25 1998/11/06 18:06:04 rassmann + * Corrected timing when RLMT checks fail. + * Clearing tx counter earlier in periodical checks. + * + * Revision 1.24 1998/11/05 10:37:27 rassmann + * Checking destination address in Lookahead. + * + * Revision 1.23 1998/11/03 13:53:49 rassmann + * RLMT should switch now (at least in mode 3). + * + * Revision 1.22 1998/10/29 14:34:49 rassmann + * Clearing SK_RLMT struct at startup. + * Initializing PortsUp during SK_RLMT_START. + * + * Revision 1.21 1998/10/28 11:30:17 rassmann + * Default mode is now SK_RLMT_CHECK_LOC_LINK. + * + * Revision 1.20 1998/10/26 16:02:03 rassmann + * Ignoring LINK_DOWN for links that are down. + * + * Revision 1.19 1998/10/22 15:54:01 rassmann + * Corrected EtherLen. + * Starting Link Check when second port comes up. + * + * Revision 1.18 1998/10/22 11:39:50 rassmann + * Corrected signed/unsigned mismatches. + * Corrected receive list handling and address recognition. + * + * Revision 1.17 1998/10/19 17:01:20 rassmann + * More detailed checking of received packets. + * + * Revision 1.16 1998/10/15 15:16:34 rassmann + * Finished Spanning Tree checking. + * Checked with lint. + * + * Revision 1.15 1998/09/24 19:16:07 rassmann + * Code cleanup. + * Introduced Timer for PORT_DOWN due to no RX. + * + * Revision 1.14 1998/09/18 20:27:14 rassmann + * Added address override. + * + * Revision 1.13 1998/09/16 11:31:48 rassmann + * Including skdrv1st.h again. :( + * + * Revision 1.12 1998/09/16 11:09:50 rassmann + * Syntax corrections. + * + * Revision 1.11 1998/09/15 12:32:03 rassmann + * Syntax correction. + * + * Revision 1.10 1998/09/15 11:28:49 rassmann + * Syntax corrections. + * + * Revision 1.9 1998/09/14 17:07:37 rassmann + * Added code for port checking via LAN. + * Changed Mbuf definition. + * + * Revision 1.8 1998/09/07 11:14:14 rassmann + * Syntax corrections. + * + * Revision 1.7 1998/09/07 09:06:07 rassmann + * Syntax corrections. + * + * Revision 1.6 1998/09/04 19:41:33 rassmann + * Syntax corrections. + * Started entering code for checking local links. + * + * Revision 1.5 1998/09/04 12:14:27 rassmann + * Interface cleanup. + * + * Revision 1.4 1998/09/02 16:55:28 rassmann + * Updated to reflect new DRV/HWAC/RLMT interface. + * + * Revision 1.3 1998/08/27 14:29:03 rassmann + * Code cleanup. + * + * Revision 1.2 1998/08/27 14:26:24 rassmann + * Updated interface. + * + * Revision 1.1 1998/08/21 08:26:49 rassmann + * First public version. + * + ******************************************************************************/ + +/****************************************************************************** + * + * Description: + * + * This module contains code for Link ManagemenT (LMT) of SK-NET Adapters. + * It is mainly intended for adapters with more than one link. + * For such adapters, this module realizes Redundant Link ManagemenT (RLMT). + * + * Include File Hierarchy: + * + * "skdrv1st.h" + * "skdrv2nd.h" + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#ifndef lint +static const char SysKonnectFileId[] = + "@(#) $Id: skrlmt.c,v 1.68 2003/01/31 15:26:56 rschmidt Exp $ (C) SysKonnect."; +#endif /* !defined(lint) */ + +#define __SKRLMT_C + +#ifdef __cplusplus +#error C++ is not yet supported. +extern "C" { +#endif /* cplusplus */ + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + +/* defines ********************************************************************/ + +#ifndef SK_HWAC_LINK_LED +#define SK_HWAC_LINK_LED(a,b,c,d) +#endif /* !defined(SK_HWAC_LINK_LED) */ + +#ifndef DEBUG +#define RLMT_STATIC static +#else /* DEBUG */ +#define RLMT_STATIC + +#ifndef SK_LITTLE_ENDIAN +/* First 32 bits */ +#define OFFS_LO32 1 + +/* Second 32 bits */ +#define OFFS_HI32 0 +#else /* SK_LITTLE_ENDIAN */ +/* First 32 bits */ +#define OFFS_LO32 0 + +/* Second 32 bits */ +#define OFFS_HI32 1 +#endif /* SK_LITTLE_ENDIAN */ + +#endif /* DEBUG */ + +/* ----- Private timeout values ----- */ + +#define SK_RLMT_MIN_TO_VAL 125000 /* 1/8 sec. */ +#define SK_RLMT_DEF_TO_VAL 1000000 /* 1 sec. */ +#define SK_RLMT_PORTDOWN_TIM_VAL 900000 /* another 0.9 sec. */ +#define SK_RLMT_PORTSTART_TIM_VAL 100000 /* 0.1 sec. */ +#define SK_RLMT_PORTUP_TIM_VAL 2500000 /* 2.5 sec. */ +#define SK_RLMT_SEG_TO_VAL 900000000 /* 15 min. */ + +/* Assume tick counter increment is 1 - may be set OS-dependent. */ +#ifndef SK_TICK_INCR +#define SK_TICK_INCR SK_CONSTU64(1) +#endif /* !defined(SK_TICK_INCR) */ + +/* + * Amount that a time stamp must be later to be recognized as "substantially + * later". This is about 1/128 sec, but above 1 tick counter increment. + */ +#define SK_RLMT_BC_DELTA (1 + ((SK_TICKS_PER_SEC >> 7) > SK_TICK_INCR ? \ + (SK_TICKS_PER_SEC >> 7) : SK_TICK_INCR)) + +/* ----- Private RLMT defaults ----- */ + +#define SK_RLMT_DEF_PREF_PORT 0 /* "Lower" port. */ +#define SK_RLMT_DEF_MODE SK_RLMT_CHECK_LINK /* Default RLMT Mode. */ + +/* ----- Private RLMT checking states ----- */ + +#define SK_RLMT_RCS_SEG 1 /* RLMT Check State: check seg. */ +#define SK_RLMT_RCS_START_SEG 2 /* RLMT Check State: start check seg. */ +#define SK_RLMT_RCS_SEND_SEG 4 /* RLMT Check State: send BPDU packet */ +#define SK_RLMT_RCS_REPORT_SEG 8 /* RLMT Check State: report seg. */ + +/* ----- Private PORT checking states ----- */ + +#define SK_RLMT_PCS_TX 1 /* Port Check State: check tx. */ +#define SK_RLMT_PCS_RX 2 /* Port Check State: check rx. */ + +/* ----- Private PORT events ----- */ + +/* Note: Update simulation when changing these. */ +#define SK_RLMT_PORTSTART_TIM 1100 /* Port start timeout. */ +#define SK_RLMT_PORTUP_TIM 1101 /* Port can now go up. */ +#define SK_RLMT_PORTDOWN_RX_TIM 1102 /* Port did not receive once ... */ +#define SK_RLMT_PORTDOWN 1103 /* Port went down. */ +#define SK_RLMT_PORTDOWN_TX_TIM 1104 /* Partner did not receive ... */ + +/* ----- Private RLMT events ----- */ + +/* Note: Update simulation when changing these. */ +#define SK_RLMT_TIM 2100 /* RLMT timeout. */ +#define SK_RLMT_SEG_TIM 2101 /* RLMT segmentation check timeout. */ + +#define TO_SHORTEN(tim) ((tim) / 2) + +/* Error numbers and messages. */ +#define SKERR_RLMT_E001 (SK_ERRBASE_RLMT + 0) +#define SKERR_RLMT_E001_MSG "No Packet." +#define SKERR_RLMT_E002 (SKERR_RLMT_E001 + 1) +#define SKERR_RLMT_E002_MSG "Short Packet." +#define SKERR_RLMT_E003 (SKERR_RLMT_E002 + 1) +#define SKERR_RLMT_E003_MSG "Unknown RLMT event." +#define SKERR_RLMT_E004 (SKERR_RLMT_E003 + 1) +#define SKERR_RLMT_E004_MSG "PortsUp incorrect." +#define SKERR_RLMT_E005 (SKERR_RLMT_E004 + 1) +#define SKERR_RLMT_E005_MSG \ + "Net seems to be segmented (different root bridges are reported on the ports)." +#define SKERR_RLMT_E006 (SKERR_RLMT_E005 + 1) +#define SKERR_RLMT_E006_MSG "Duplicate MAC Address detected." +#define SKERR_RLMT_E007 (SKERR_RLMT_E006 + 1) +#define SKERR_RLMT_E007_MSG "LinksUp incorrect." +#define SKERR_RLMT_E008 (SKERR_RLMT_E007 + 1) +#define SKERR_RLMT_E008_MSG "Port not started but link came up." +#define SKERR_RLMT_E009 (SKERR_RLMT_E008 + 1) +#define SKERR_RLMT_E009_MSG "Corrected illegal setting of Preferred Port." +#define SKERR_RLMT_E010 (SKERR_RLMT_E009 + 1) +#define SKERR_RLMT_E010_MSG "Ignored illegal Preferred Port." + +/* LLC field values. */ +#define LLC_COMMAND_RESPONSE_BIT 1 +#define LLC_TEST_COMMAND 0xE3 +#define LLC_UI 0x03 + +/* RLMT Packet fields. */ +#define SK_RLMT_DSAP 0 +#define SK_RLMT_SSAP 0 +#define SK_RLMT_CTRL (LLC_TEST_COMMAND) +#define SK_RLMT_INDICATOR0 0x53 /* S */ +#define SK_RLMT_INDICATOR1 0x4B /* K */ +#define SK_RLMT_INDICATOR2 0x2D /* - */ +#define SK_RLMT_INDICATOR3 0x52 /* R */ +#define SK_RLMT_INDICATOR4 0x4C /* L */ +#define SK_RLMT_INDICATOR5 0x4D /* M */ +#define SK_RLMT_INDICATOR6 0x54 /* T */ +#define SK_RLMT_PACKET_VERSION 0 + +/* RLMT SPT Flag values. */ +#define SK_RLMT_SPT_FLAG_CHANGE 0x01 +#define SK_RLMT_SPT_FLAG_CHANGE_ACK 0x80 + +/* RLMT SPT Packet fields. */ +#define SK_RLMT_SPT_DSAP 0x42 +#define SK_RLMT_SPT_SSAP 0x42 +#define SK_RLMT_SPT_CTRL (LLC_UI) +#define SK_RLMT_SPT_PROTOCOL_ID0 0x00 +#define SK_RLMT_SPT_PROTOCOL_ID1 0x00 +#define SK_RLMT_SPT_PROTOCOL_VERSION_ID 0x00 +#define SK_RLMT_SPT_BPDU_TYPE 0x00 +#define SK_RLMT_SPT_FLAGS 0x00 /* ?? */ +#define SK_RLMT_SPT_ROOT_ID0 0xFF /* Lowest possible priority. */ +#define SK_RLMT_SPT_ROOT_ID1 0xFF /* Lowest possible priority. */ + +/* Remaining 6 bytes will be the current port address. */ +#define SK_RLMT_SPT_ROOT_PATH_COST0 0x00 +#define SK_RLMT_SPT_ROOT_PATH_COST1 0x00 +#define SK_RLMT_SPT_ROOT_PATH_COST2 0x00 +#define SK_RLMT_SPT_ROOT_PATH_COST3 0x00 +#define SK_RLMT_SPT_BRIDGE_ID0 0xFF /* Lowest possible priority. */ +#define SK_RLMT_SPT_BRIDGE_ID1 0xFF /* Lowest possible priority. */ + +/* Remaining 6 bytes will be the current port address. */ +#define SK_RLMT_SPT_PORT_ID0 0xFF /* Lowest possible priority. */ +#define SK_RLMT_SPT_PORT_ID1 0xFF /* Lowest possible priority. */ +#define SK_RLMT_SPT_MSG_AGE0 0x00 +#define SK_RLMT_SPT_MSG_AGE1 0x00 +#define SK_RLMT_SPT_MAX_AGE0 0x00 +#define SK_RLMT_SPT_MAX_AGE1 0xFF +#define SK_RLMT_SPT_HELLO_TIME0 0x00 +#define SK_RLMT_SPT_HELLO_TIME1 0xFF +#define SK_RLMT_SPT_FWD_DELAY0 0x00 +#define SK_RLMT_SPT_FWD_DELAY1 0x40 + +/* Size defines. */ +#define SK_RLMT_MIN_PACKET_SIZE 34 +#define SK_RLMT_MAX_PACKET_SIZE (SK_RLMT_MAX_TX_BUF_SIZE) +#define SK_PACKET_DATA_LEN (SK_RLMT_MAX_PACKET_SIZE - \ + SK_RLMT_MIN_PACKET_SIZE) + +/* ----- RLMT packet types ----- */ +#define SK_PACKET_ANNOUNCE 1 /* Port announcement. */ +#define SK_PACKET_ALIVE 2 /* Alive packet to port. */ +#define SK_PACKET_ADDR_CHANGED 3 /* Port address changed. */ +#define SK_PACKET_CHECK_TX 4 /* Check your tx line. */ + +#ifdef SK_LITTLE_ENDIAN +#define SK_U16_TO_NETWORK_ORDER(Val,Addr) { \ + SK_U8 *_Addr = (SK_U8*)(Addr); \ + SK_U16 _Val = (SK_U16)(Val); \ + *_Addr++ = (SK_U8)(_Val >> 8); \ + *_Addr = (SK_U8)(_Val & 0xFF); \ +} +#endif /* SK_LITTLE_ENDIAN */ + +#ifdef SK_BIG_ENDIAN +#define SK_U16_TO_NETWORK_ORDER(Val,Addr) (*(SK_U16*)(Addr) = (SK_U16)(Val)) +#endif /* SK_BIG_ENDIAN */ + +#define AUTONEG_FAILED SK_FALSE +#define AUTONEG_SUCCESS SK_TRUE + + +/* typedefs *******************************************************************/ + +/* RLMT packet. Length: SK_RLMT_MAX_PACKET_SIZE (60) bytes. */ +typedef struct s_RlmtPacket { + SK_U8 DstAddr[SK_MAC_ADDR_LEN]; + SK_U8 SrcAddr[SK_MAC_ADDR_LEN]; + SK_U8 TypeLen[2]; + SK_U8 DSap; + SK_U8 SSap; + SK_U8 Ctrl; + SK_U8 Indicator[7]; + SK_U8 RlmtPacketType[2]; + SK_U8 Align1[2]; + SK_U8 Random[4]; /* Random value of requesting(!) station. */ + SK_U8 RlmtPacketVersion[2]; /* RLMT Packet version. */ + SK_U8 Data[SK_PACKET_DATA_LEN]; +} SK_RLMT_PACKET; + +typedef struct s_SpTreeRlmtPacket { + SK_U8 DstAddr[SK_MAC_ADDR_LEN]; + SK_U8 SrcAddr[SK_MAC_ADDR_LEN]; + SK_U8 TypeLen[2]; + SK_U8 DSap; + SK_U8 SSap; + SK_U8 Ctrl; + SK_U8 ProtocolId[2]; + SK_U8 ProtocolVersionId; + SK_U8 BpduType; + SK_U8 Flags; + SK_U8 RootId[8]; + SK_U8 RootPathCost[4]; + SK_U8 BridgeId[8]; + SK_U8 PortId[2]; + SK_U8 MessageAge[2]; + SK_U8 MaxAge[2]; + SK_U8 HelloTime[2]; + SK_U8 ForwardDelay[2]; +} SK_SPTREE_PACKET; + +/* global variables ***********************************************************/ + +SK_MAC_ADDR SkRlmtMcAddr = {{0x01, 0x00, 0x5A, 0x52, 0x4C, 0x4D}}; +SK_MAC_ADDR BridgeMcAddr = {{0x01, 0x80, 0xC2, 0x00, 0x00, 0x00}}; +SK_MAC_ADDR BcAddr = {{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}}; + +/* local variables ************************************************************/ + +/* None. */ + +/* functions ******************************************************************/ + +RLMT_STATIC void SkRlmtCheckSwitch( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 NetIdx); +RLMT_STATIC void SkRlmtCheckSeg( + SK_AC *pAC, + SK_IOC IoC, + SK_U32 NetIdx); +RLMT_STATIC void SkRlmtEvtSetNets( + SK_AC *pAC, + SK_IOC IoC, + SK_EVPARA Para); + +/****************************************************************************** + * + * SkRlmtInit - initialize data, set state to init + * + * Description: + * + * SK_INIT_DATA + * ============ + * + * This routine initializes all RLMT-related variables to a known state. + * The initial state is SK_RLMT_RS_INIT. + * All ports are initialized to SK_RLMT_PS_INIT. + * + * + * SK_INIT_IO + * ========== + * + * Nothing. + * + * + * SK_INIT_RUN + * =========== + * + * Determine the adapter's random value. + * Set the hw registers, the "logical MAC address", the + * RLMT multicast address, and eventually the BPDU multicast address. + * + * Context: + * init, pageable + * + * Returns: + * Nothing. + */ +void SkRlmtInit( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Level) /* Initialization Level */ +{ + SK_U32 i, j; + SK_U64 Random; + SK_EVPARA Para; + SK_MAC_ADDR VirtualMacAddress; + SK_MAC_ADDR PhysicalAMacAddress; + SK_BOOL VirtualMacAddressSet; + SK_BOOL PhysicalAMacAddressSet; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT, + ("RLMT Init level %d.\n", Level)) + + switch (Level) { + case SK_INIT_DATA: /* Initialize data structures. */ + SK_MEMSET((char *)&pAC->Rlmt, 0, sizeof(SK_RLMT)); + + for (i = 0; i < SK_MAX_MACS; i++) { + pAC->Rlmt.Port[i].PortState = SK_RLMT_PS_INIT; + pAC->Rlmt.Port[i].LinkDown = SK_TRUE; + pAC->Rlmt.Port[i].PortDown = SK_TRUE; + pAC->Rlmt.Port[i].PortStarted = SK_FALSE; + pAC->Rlmt.Port[i].PortNoRx = SK_FALSE; + pAC->Rlmt.Port[i].RootIdSet = SK_FALSE; + pAC->Rlmt.Port[i].PortNumber = i; + pAC->Rlmt.Port[i].Net = &pAC->Rlmt.Net[0]; + pAC->Rlmt.Port[i].AddrPort = &pAC->Addr.Port[i]; + } + + pAC->Rlmt.NumNets = 1; + for (i = 0; i < SK_MAX_NETS; i++) { + pAC->Rlmt.Net[i].RlmtState = SK_RLMT_RS_INIT; + pAC->Rlmt.Net[i].RootIdSet = SK_FALSE; + pAC->Rlmt.Net[i].PrefPort = SK_RLMT_DEF_PREF_PORT; + pAC->Rlmt.Net[i].Preference = 0xFFFFFFFF; /* Automatic. */ + /* Just assuming. */ + pAC->Rlmt.Net[i].ActivePort = pAC->Rlmt.Net[i].PrefPort; + pAC->Rlmt.Net[i].RlmtMode = SK_RLMT_DEF_MODE; + pAC->Rlmt.Net[i].TimeoutValue = SK_RLMT_DEF_TO_VAL; + pAC->Rlmt.Net[i].NetNumber = i; + } + + pAC->Rlmt.Net[0].Port[0] = &pAC->Rlmt.Port[0]; + pAC->Rlmt.Net[0].Port[1] = &pAC->Rlmt.Port[1]; +#if SK_MAX_NETS > 1 + pAC->Rlmt.Net[1].Port[0] = &pAC->Rlmt.Port[1]; +#endif /* SK_MAX_NETS > 1 */ + break; + + case SK_INIT_IO: /* GIMacsFound first available here. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT, + ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound)) + + pAC->Rlmt.Net[0].NumPorts = pAC->GIni.GIMacsFound; + + /* Initialize HW registers? */ + if (pAC->GIni.GIMacsFound == 1) { + Para.Para32[0] = SK_RLMT_MODE_CLS; + Para.Para32[1] = 0; + (void)SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE, Para); + } + break; + + case SK_INIT_RUN: + /* Ensure RLMT is set to one net. */ + if (pAC->Rlmt.NumNets > 1) { + Para.Para32[0] = 1; + Para.Para32[1] = -1; + SkRlmtEvtSetNets(pAC, IoC, Para); + } + + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + Random = SkOsGetTime(pAC); + *(SK_U32*)&pAC->Rlmt.Port[i].Random = *(SK_U32*)&Random; + + for (j = 0; j < 4; j++) { + pAC->Rlmt.Port[i].Random[j] ^= pAC->Rlmt.Port[i].AddrPort-> + CurrentMacAddress.a[SK_MAC_ADDR_LEN - 1 - j]; + } + + (void)SkAddrMcClear(pAC, IoC, i, SK_ADDR_PERMANENT | SK_MC_SW_ONLY); + + /* Add RLMT MC address. */ + (void)SkAddrMcAdd(pAC, IoC, i, &SkRlmtMcAddr, SK_ADDR_PERMANENT); + + if (pAC->Rlmt.Net[0].RlmtMode & SK_RLMT_CHECK_SEG) { + /* Add BPDU MC address. */ + (void)SkAddrMcAdd(pAC, IoC, i, &BridgeMcAddr, SK_ADDR_PERMANENT); + } + + (void)SkAddrMcUpdate(pAC, IoC, i); + } + + VirtualMacAddressSet = SK_FALSE; + /* Read virtual MAC address from Control Register File. */ + for (j = 0; j < SK_MAC_ADDR_LEN; j++) { + + SK_IN8(IoC, B2_MAC_1 + j, &VirtualMacAddress.a[j]); + VirtualMacAddressSet |= VirtualMacAddress.a[j]; + } + + PhysicalAMacAddressSet = SK_FALSE; + /* Read physical MAC address for MAC A from Control Register File. */ + for (j = 0; j < SK_MAC_ADDR_LEN; j++) { + + SK_IN8(IoC, B2_MAC_2 + j, &PhysicalAMacAddress.a[j]); + PhysicalAMacAddressSet |= PhysicalAMacAddress.a[j]; + } + + /* check if the two mac addresses contain reasonable values */ + if (!VirtualMacAddressSet || !PhysicalAMacAddressSet) { + + pAC->Rlmt.RlmtOff = SK_TRUE; + } + + /* if the two mac addresses are equal switch off the RLMT_PRE_LOOKAHEAD + and the RLMT_LOOKAHEAD macros */ + else if (SK_ADDR_EQUAL(PhysicalAMacAddress.a, VirtualMacAddress.a)) { + + pAC->Rlmt.RlmtOff = SK_TRUE; + } + else { + pAC->Rlmt.RlmtOff = SK_FALSE; + } + break; + + default: /* error */ + break; + } + return; +} /* SkRlmtInit */ + + +/****************************************************************************** + * + * SkRlmtBuildCheckChain - build the check chain + * + * Description: + * This routine builds the local check chain: + * - Each port that is up checks the next port. + * - The last port that is up checks the first port that is up. + * + * Notes: + * - Currently only local ports are considered when building the chain. + * - Currently the SuspectState is just reset; + * it would be better to save it ... + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtBuildCheckChain( +SK_AC *pAC, /* Adapter Context */ +SK_U32 NetIdx) /* Net Number */ +{ + SK_U32 i; + SK_U32 NumMacsUp; + SK_RLMT_PORT * FirstMacUp; + SK_RLMT_PORT * PrevMacUp; + + FirstMacUp = NULL; + PrevMacUp = NULL; + + if (!(pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_CHECK_LOC_LINK)) { + for (i = 0; i < pAC->Rlmt.Net[i].NumPorts; i++) { + pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked = 0; + } + return; /* Done. */ + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SkRlmtBuildCheckChain.\n")) + + NumMacsUp = 0; + + for (i = 0; i < pAC->Rlmt.Net[NetIdx].NumPorts; i++) { + pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked = 0; + pAC->Rlmt.Net[NetIdx].Port[i]->PortsSuspect = 0; + pAC->Rlmt.Net[NetIdx].Port[i]->CheckingState &= + ~(SK_RLMT_PCS_RX | SK_RLMT_PCS_TX); + + /* + * If more than two links are detected we should consider + * checking at least two other ports: + * 1. the next port that is not LinkDown and + * 2. the next port that is not PortDown. + */ + if (!pAC->Rlmt.Net[NetIdx].Port[i]->LinkDown) { + if (NumMacsUp == 0) { + FirstMacUp = pAC->Rlmt.Net[NetIdx].Port[i]; + } + else { + PrevMacUp->PortCheck[ + pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked].CheckAddr = + pAC->Rlmt.Net[NetIdx].Port[i]->AddrPort->CurrentMacAddress; + PrevMacUp->PortCheck[ + PrevMacUp->PortsChecked].SuspectTx = SK_FALSE; + PrevMacUp->PortsChecked++; + } + PrevMacUp = pAC->Rlmt.Net[NetIdx].Port[i]; + NumMacsUp++; + } + } + + if (NumMacsUp > 1) { + PrevMacUp->PortCheck[PrevMacUp->PortsChecked].CheckAddr = + FirstMacUp->AddrPort->CurrentMacAddress; + PrevMacUp->PortCheck[PrevMacUp->PortsChecked].SuspectTx = + SK_FALSE; + PrevMacUp->PortsChecked++; + } + +#ifdef DEBUG + for (i = 0; i < pAC->Rlmt.Net[NetIdx].NumPorts; i++) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Port %d checks %d other ports: %2X.\n", i, + pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked, + pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5])) + } +#endif /* DEBUG */ + + return; +} /* SkRlmtBuildCheckChain */ + + +/****************************************************************************** + * + * SkRlmtBuildPacket - build an RLMT packet + * + * Description: + * This routine sets up an RLMT packet. + * + * Context: + * runtime, pageable? + * + * Returns: + * NULL or pointer to RLMT mbuf + */ +RLMT_STATIC SK_MBUF *SkRlmtBuildPacket( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber, /* Sending port */ +SK_U16 PacketType, /* RLMT packet type */ +SK_MAC_ADDR *SrcAddr, /* Source address */ +SK_MAC_ADDR *DestAddr) /* Destination address */ +{ + int i; + SK_U16 Length; + SK_MBUF *pMb; + SK_RLMT_PACKET *pPacket; + +#ifdef DEBUG + SK_U8 CheckSrc = 0; + SK_U8 CheckDest = 0; + + for (i = 0; i < SK_MAC_ADDR_LEN; ++i) { + CheckSrc |= SrcAddr->a[i]; + CheckDest |= DestAddr->a[i]; + } + + if ((CheckSrc == 0) || (CheckDest == 0)) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_ERR, + ("SkRlmtBuildPacket: Invalid %s%saddr.\n", + (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : ""))) + } +#endif + + if ((pMb = SkDrvAllocRlmtMbuf(pAC, IoC, SK_RLMT_MAX_PACKET_SIZE)) != NULL) { + pPacket = (SK_RLMT_PACKET*)pMb->pData; + for (i = 0; i < SK_MAC_ADDR_LEN; i++) { + pPacket->DstAddr[i] = DestAddr->a[i]; + pPacket->SrcAddr[i] = SrcAddr->a[i]; + } + pPacket->DSap = SK_RLMT_DSAP; + pPacket->SSap = SK_RLMT_SSAP; + pPacket->Ctrl = SK_RLMT_CTRL; + pPacket->Indicator[0] = SK_RLMT_INDICATOR0; + pPacket->Indicator[1] = SK_RLMT_INDICATOR1; + pPacket->Indicator[2] = SK_RLMT_INDICATOR2; + pPacket->Indicator[3] = SK_RLMT_INDICATOR3; + pPacket->Indicator[4] = SK_RLMT_INDICATOR4; + pPacket->Indicator[5] = SK_RLMT_INDICATOR5; + pPacket->Indicator[6] = SK_RLMT_INDICATOR6; + + SK_U16_TO_NETWORK_ORDER(PacketType, &pPacket->RlmtPacketType[0]); + + for (i = 0; i < 4; i++) { + pPacket->Random[i] = pAC->Rlmt.Port[PortNumber].Random[i]; + } + + SK_U16_TO_NETWORK_ORDER( + SK_RLMT_PACKET_VERSION, &pPacket->RlmtPacketVersion[0]); + + for (i = 0; i < SK_PACKET_DATA_LEN; i++) { + pPacket->Data[i] = 0x00; + } + + Length = SK_RLMT_MAX_PACKET_SIZE; /* Or smaller. */ + pMb->Length = Length; + pMb->PortIdx = PortNumber; + Length -= 14; + SK_U16_TO_NETWORK_ORDER(Length, &pPacket->TypeLen[0]); + + if (PacketType == SK_PACKET_ALIVE) { + pAC->Rlmt.Port[PortNumber].TxHelloCts++; + } + } + + return (pMb); +} /* SkRlmtBuildPacket */ + + +/****************************************************************************** + * + * SkRlmtBuildSpanningTreePacket - build spanning tree check packet + * + * Description: + * This routine sets up a BPDU packet for spanning tree check. + * + * Context: + * runtime, pageable? + * + * Returns: + * NULL or pointer to RLMT mbuf + */ +RLMT_STATIC SK_MBUF *SkRlmtBuildSpanningTreePacket( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber) /* Sending port */ +{ + unsigned i; + SK_U16 Length; + SK_MBUF *pMb; + SK_SPTREE_PACKET *pSPacket; + + if ((pMb = SkDrvAllocRlmtMbuf(pAC, IoC, SK_RLMT_MAX_PACKET_SIZE)) != + NULL) { + pSPacket = (SK_SPTREE_PACKET*)pMb->pData; + for (i = 0; i < SK_MAC_ADDR_LEN; i++) { + pSPacket->DstAddr[i] = BridgeMcAddr.a[i]; + pSPacket->SrcAddr[i] = + pAC->Addr.Port[PortNumber].CurrentMacAddress.a[i]; + } + pSPacket->DSap = SK_RLMT_SPT_DSAP; + pSPacket->SSap = SK_RLMT_SPT_SSAP; + pSPacket->Ctrl = SK_RLMT_SPT_CTRL; + + pSPacket->ProtocolId[0] = SK_RLMT_SPT_PROTOCOL_ID0; + pSPacket->ProtocolId[1] = SK_RLMT_SPT_PROTOCOL_ID1; + pSPacket->ProtocolVersionId = SK_RLMT_SPT_PROTOCOL_VERSION_ID; + pSPacket->BpduType = SK_RLMT_SPT_BPDU_TYPE; + pSPacket->Flags = SK_RLMT_SPT_FLAGS; + pSPacket->RootId[0] = SK_RLMT_SPT_ROOT_ID0; + pSPacket->RootId[1] = SK_RLMT_SPT_ROOT_ID1; + pSPacket->RootPathCost[0] = SK_RLMT_SPT_ROOT_PATH_COST0; + pSPacket->RootPathCost[1] = SK_RLMT_SPT_ROOT_PATH_COST1; + pSPacket->RootPathCost[2] = SK_RLMT_SPT_ROOT_PATH_COST2; + pSPacket->RootPathCost[3] = SK_RLMT_SPT_ROOT_PATH_COST3; + pSPacket->BridgeId[0] = SK_RLMT_SPT_BRIDGE_ID0; + pSPacket->BridgeId[1] = SK_RLMT_SPT_BRIDGE_ID1; + + /* + * Use logical MAC address as bridge ID and filter these packets + * on receive. + */ + for (i = 0; i < SK_MAC_ADDR_LEN; i++) { + pSPacket->BridgeId[i + 2] = pSPacket->RootId[i + 2] = + pAC->Addr.Net[pAC->Rlmt.Port[PortNumber].Net->NetNumber]. + CurrentMacAddress.a[i]; + } + pSPacket->PortId[0] = SK_RLMT_SPT_PORT_ID0; + pSPacket->PortId[1] = SK_RLMT_SPT_PORT_ID1; + pSPacket->MessageAge[0] = SK_RLMT_SPT_MSG_AGE0; + pSPacket->MessageAge[1] = SK_RLMT_SPT_MSG_AGE1; + pSPacket->MaxAge[0] = SK_RLMT_SPT_MAX_AGE0; + pSPacket->MaxAge[1] = SK_RLMT_SPT_MAX_AGE1; + pSPacket->HelloTime[0] = SK_RLMT_SPT_HELLO_TIME0; + pSPacket->HelloTime[1] = SK_RLMT_SPT_HELLO_TIME1; + pSPacket->ForwardDelay[0] = SK_RLMT_SPT_FWD_DELAY0; + pSPacket->ForwardDelay[1] = SK_RLMT_SPT_FWD_DELAY1; + + Length = SK_RLMT_MAX_PACKET_SIZE; /* Or smaller. */ + pMb->Length = Length; + pMb->PortIdx = PortNumber; + Length -= 14; + SK_U16_TO_NETWORK_ORDER(Length, &pSPacket->TypeLen[0]); + + pAC->Rlmt.Port[PortNumber].TxSpHelloReqCts++; + } + + return (pMb); +} /* SkRlmtBuildSpanningTreePacket */ + + +/****************************************************************************** + * + * SkRlmtSend - build and send check packets + * + * Description: + * Depending on the RLMT state and the checking state, several packets + * are sent through the indicated port. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing. + */ +RLMT_STATIC void SkRlmtSend( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber) /* Sending port */ +{ + unsigned j; + SK_EVPARA Para; + SK_RLMT_PORT *pRPort; + + pRPort = &pAC->Rlmt.Port[PortNumber]; + if (pAC->Rlmt.Port[PortNumber].Net->RlmtMode & SK_RLMT_CHECK_LOC_LINK) { + if (pRPort->CheckingState & (SK_RLMT_PCS_TX | SK_RLMT_PCS_RX)) { + /* Port is suspicious. Send the RLMT packet to the RLMT mc addr. */ + if ((Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, PortNumber, + SK_PACKET_ALIVE, &pAC->Addr.Port[PortNumber].CurrentMacAddress, + &SkRlmtMcAddr)) != NULL) { + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + } + else { + /* + * Send a directed RLMT packet to all ports that are + * checked by the indicated port. + */ + for (j = 0; j < pRPort->PortsChecked; j++) { + if ((Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, PortNumber, + SK_PACKET_ALIVE, &pAC->Addr.Port[PortNumber].CurrentMacAddress, + &pRPort->PortCheck[j].CheckAddr)) != NULL) { + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + } + } + } + + if ((pAC->Rlmt.Port[PortNumber].Net->RlmtMode & SK_RLMT_CHECK_SEG) && + (pAC->Rlmt.Port[PortNumber].Net->CheckingState & SK_RLMT_RCS_SEND_SEG)) { + /* + * Send a BPDU packet to make a connected switch tell us + * the correct root bridge. + */ + if ((Para.pParaPtr = + SkRlmtBuildSpanningTreePacket(pAC, IoC, PortNumber)) != NULL) { + pAC->Rlmt.Port[PortNumber].Net->CheckingState &= ~SK_RLMT_RCS_SEND_SEG; + pRPort->RootIdSet = SK_FALSE; + + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_TX, + ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber)) + } + } + return; +} /* SkRlmtSend */ + + +/****************************************************************************** + * + * SkRlmtPortReceives - check if port is (going) down and bring it up + * + * Description: + * This routine checks if a port who received a non-BPDU packet + * needs to go up or needs to be stopped going down. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing. + */ +RLMT_STATIC void SkRlmtPortReceives( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber) /* Port to check */ +{ + SK_RLMT_PORT *pRPort; + SK_EVPARA Para; + + pRPort = &pAC->Rlmt.Port[PortNumber]; + pRPort->PortNoRx = SK_FALSE; + + if ((pRPort->PortState == SK_RLMT_PS_DOWN) && + !(pRPort->CheckingState & SK_RLMT_PCS_TX)) { + /* + * Port is marked down (rx), but received a non-BPDU packet. + * Bring it up. + */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Received on PortDown.\n")) + + pRPort->PortState = SK_RLMT_PS_GOING_UP; + pRPort->GuTimeStamp = SkOsGetTime(pAC); + Para.Para32[0] = PortNumber; + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->UpTimer, SK_RLMT_PORTUP_TIM_VAL, + SKGE_RLMT, SK_RLMT_PORTUP_TIM, Para); + pRPort->CheckingState &= ~SK_RLMT_PCS_RX; + /* pAC->Rlmt.CheckSwitch = SK_TRUE; */ + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + } /* PortDown && !SuspectTx */ + else if (pRPort->CheckingState & SK_RLMT_PCS_RX) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Stop bringing port down.\n")) + SkTimerStop(pAC, IoC, &pRPort->DownRxTimer); + pRPort->CheckingState &= ~SK_RLMT_PCS_RX; + /* pAC->Rlmt.CheckSwitch = SK_TRUE; */ + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + } /* PortGoingDown */ + + return; +} /* SkRlmtPortReceives */ + + +/****************************************************************************** + * + * SkRlmtPacketReceive - receive a packet for closer examination + * + * Description: + * This routine examines a packet more closely than SK_RLMT_LOOKAHEAD. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing. + */ +RLMT_STATIC void SkRlmtPacketReceive( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_MBUF *pMb) /* Received packet */ +{ +#ifdef xDEBUG + extern void DumpData(char *p, int size); +#endif /* DEBUG */ + int i; + unsigned j; + SK_U16 PacketType; + SK_U32 PortNumber; + SK_ADDR_PORT *pAPort; + SK_RLMT_PORT *pRPort; + SK_RLMT_PACKET *pRPacket; + SK_SPTREE_PACKET *pSPacket; + SK_EVPARA Para; + + PortNumber = pMb->PortIdx; + pAPort = &pAC->Addr.Port[PortNumber]; + pRPort = &pAC->Rlmt.Port[PortNumber]; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber)) + + pRPacket = (SK_RLMT_PACKET*)pMb->pData; + pSPacket = (SK_SPTREE_PACKET*)pRPacket; + +#ifdef xDEBUG + DumpData((char *)pRPacket, 32); +#endif /* DEBUG */ + + if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) != 0) { + SkRlmtPortReceives(pAC, IoC, PortNumber); + } + + /* Check destination address. */ + + if (!SK_ADDR_EQUAL(pAPort->CurrentMacAddress.a, pRPacket->DstAddr) && + !SK_ADDR_EQUAL(SkRlmtMcAddr.a, pRPacket->DstAddr) && + !SK_ADDR_EQUAL(BridgeMcAddr.a, pRPacket->DstAddr)) { + + /* Not sent to current MAC or registered MC address => Trash it. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Not for me.\n")) + + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + return; + } + else if (SK_ADDR_EQUAL(pAPort->CurrentMacAddress.a, pRPacket->SrcAddr)) { + + /* + * Was sent by same port (may happen during port switching + * or in case of duplicate MAC addresses). + */ + + /* + * Check for duplicate address here: + * If Packet.Random != My.Random => DupAddr. + */ + for (i = 3; i >= 0; i--) { + if (pRPort->Random[i] != pRPacket->Random[i]) { + break; + } + } + + /* + * CAUTION: Do not check for duplicate MAC address in RLMT Alive Reply + * packets (they have the LLC_COMMAND_RESPONSE_BIT set in + * pRPacket->SSap). + */ + if (i >= 0 && pRPacket->DSap == SK_RLMT_DSAP && + pRPacket->Ctrl == SK_RLMT_CTRL && + pRPacket->SSap == SK_RLMT_SSAP && + pRPacket->Indicator[0] == SK_RLMT_INDICATOR0 && + pRPacket->Indicator[1] == SK_RLMT_INDICATOR1 && + pRPacket->Indicator[2] == SK_RLMT_INDICATOR2 && + pRPacket->Indicator[3] == SK_RLMT_INDICATOR3 && + pRPacket->Indicator[4] == SK_RLMT_INDICATOR4 && + pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 && + pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Duplicate MAC Address.\n")) + + /* Error Log entry. */ + SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E006, SKERR_RLMT_E006_MSG); + } + else { + /* Simply trash it. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Sent by me.\n")) + } + + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + return; + } + + /* Check SuspectTx entries. */ + if (pRPort->PortsSuspect > 0) { + for (j = 0; j < pRPort->PortsChecked; j++) { + if (pRPort->PortCheck[j].SuspectTx && + SK_ADDR_EQUAL( + pRPacket->SrcAddr, pRPort->PortCheck[j].CheckAddr.a)) { + pRPort->PortCheck[j].SuspectTx = SK_FALSE; + pRPort->PortsSuspect--; + break; + } + } + } + + /* Determine type of packet. */ + if (pRPacket->DSap == SK_RLMT_DSAP && + pRPacket->Ctrl == SK_RLMT_CTRL && + (pRPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) == SK_RLMT_SSAP && + pRPacket->Indicator[0] == SK_RLMT_INDICATOR0 && + pRPacket->Indicator[1] == SK_RLMT_INDICATOR1 && + pRPacket->Indicator[2] == SK_RLMT_INDICATOR2 && + pRPacket->Indicator[3] == SK_RLMT_INDICATOR3 && + pRPacket->Indicator[4] == SK_RLMT_INDICATOR4 && + pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 && + pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) { + + /* It's an RLMT packet. */ + PacketType = (SK_U16)((pRPacket->RlmtPacketType[0] << 8) | + pRPacket->RlmtPacketType[1]); + + switch (PacketType) { + case SK_PACKET_ANNOUNCE: /* Not yet used. */ +#if 0 + /* Build the check chain. */ + SkRlmtBuildCheckChain(pAC); +#endif /* 0 */ + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Announce.\n")) + + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + break; + + case SK_PACKET_ALIVE: + if (pRPacket->SSap & LLC_COMMAND_RESPONSE_BIT) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Alive Reply.\n")) + + if (!(pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_LLC) || + SK_ADDR_EQUAL( + pRPacket->DstAddr, pAPort->CurrentMacAddress.a)) { + /* Obviously we could send something. */ + if (pRPort->CheckingState & SK_RLMT_PCS_TX) { + pRPort->CheckingState &= ~SK_RLMT_PCS_TX; + SkTimerStop(pAC, IoC, &pRPort->DownTxTimer); + } + + if ((pRPort->PortState == SK_RLMT_PS_DOWN) && + !(pRPort->CheckingState & SK_RLMT_PCS_RX)) { + pRPort->PortState = SK_RLMT_PS_GOING_UP; + pRPort->GuTimeStamp = SkOsGetTime(pAC); + + SkTimerStop(pAC, IoC, &pRPort->DownTxTimer); + + Para.Para32[0] = PortNumber; + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->UpTimer, + SK_RLMT_PORTUP_TIM_VAL, SKGE_RLMT, + SK_RLMT_PORTUP_TIM, Para); + } + } + + /* Mark sending port as alive? */ + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + } + else { /* Alive Request Packet. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Alive Request.\n")) + + pRPort->RxHelloCts++; + + /* Answer. */ + for (i = 0; i < SK_MAC_ADDR_LEN; i++) { + pRPacket->DstAddr[i] = pRPacket->SrcAddr[i]; + pRPacket->SrcAddr[i] = + pAC->Addr.Port[PortNumber].CurrentMacAddress.a[i]; + } + pRPacket->SSap |= LLC_COMMAND_RESPONSE_BIT; + + Para.pParaPtr = pMb; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + break; + + case SK_PACKET_CHECK_TX: + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Check your tx line.\n")) + + /* A port checking us requests us to check our tx line. */ + pRPort->CheckingState |= SK_RLMT_PCS_TX; + + /* Start PortDownTx timer. */ + Para.Para32[0] = PortNumber; + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->DownTxTimer, + SK_RLMT_PORTDOWN_TIM_VAL, SKGE_RLMT, + SK_RLMT_PORTDOWN_TX_TIM, Para); + + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + + if ((Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, PortNumber, + SK_PACKET_ALIVE, &pAC->Addr.Port[PortNumber].CurrentMacAddress, + &SkRlmtMcAddr)) != NULL) { + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + break; + + case SK_PACKET_ADDR_CHANGED: + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Address Change.\n")) + + /* Build the check chain. */ + SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber); + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + break; + + default: + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Unknown RLMT packet.\n")) + + /* RA;:;: ??? */ + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + } + } + else if (pSPacket->DSap == SK_RLMT_SPT_DSAP && + pSPacket->Ctrl == SK_RLMT_SPT_CTRL && + (pSPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) == SK_RLMT_SPT_SSAP) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: BPDU Packet.\n")) + + /* Spanning Tree packet. */ + pRPort->RxSpHelloCts++; + + if (!SK_ADDR_EQUAL(&pSPacket->RootId[2], &pAC->Addr.Net[pAC->Rlmt. + Port[PortNumber].Net->NetNumber].CurrentMacAddress.a[0])) { + /* + * Check segmentation if a new root bridge is set and + * the segmentation check is not currently running. + */ + if (!SK_ADDR_EQUAL(&pSPacket->RootId[2], &pRPort->Root.Id[2]) && + (pAC->Rlmt.Port[PortNumber].Net->LinksUp > 1) && + (pAC->Rlmt.Port[PortNumber].Net->RlmtMode & SK_RLMT_CHECK_SEG) + != 0 && (pAC->Rlmt.Port[PortNumber].Net->CheckingState & + SK_RLMT_RCS_SEG) == 0) { + pAC->Rlmt.Port[PortNumber].Net->CheckingState |= + SK_RLMT_RCS_START_SEG | SK_RLMT_RCS_SEND_SEG; + } + + /* Store tree view of this port. */ + for (i = 0; i < 8; i++) { + pRPort->Root.Id[i] = pSPacket->RootId[i]; + } + pRPort->RootIdSet = SK_TRUE; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_DUMP, + ("Root ID %d: %02x %02x %02x %02x %02x %02x %02x %02x.\n", + PortNumber, + pRPort->Root.Id[0], pRPort->Root.Id[1], + pRPort->Root.Id[2], pRPort->Root.Id[3], + pRPort->Root.Id[4], pRPort->Root.Id[5], + pRPort->Root.Id[6], pRPort->Root.Id[7])) + } + + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + if ((pAC->Rlmt.Port[PortNumber].Net->CheckingState & + SK_RLMT_RCS_REPORT_SEG) != 0) { + SkRlmtCheckSeg(pAC, IoC, pAC->Rlmt.Port[PortNumber].Net->NetNumber); + } + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX, + ("SkRlmtPacketReceive: Unknown Packet Type.\n")) + + /* Unknown packet. */ + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + } + return; +} /* SkRlmtPacketReceive */ + + +/****************************************************************************** + * + * SkRlmtCheckPort - check if a port works + * + * Description: + * This routine checks if a port whose link is up received something + * and if it seems to transmit successfully. + * + * # PortState: PsInit, PsLinkDown, PsDown, PsGoingUp, PsUp + * # PortCheckingState (Bitfield): ChkTx, ChkRx, ChkSeg + * # RlmtCheckingState (Bitfield): ChkSeg, StartChkSeg, ReportSeg + * + * if (Rx - RxBpdu == 0) { # No rx. + * if (state == PsUp) { + * PortCheckingState |= ChkRx + * } + * if (ModeCheckSeg && (Timeout == + * TO_SHORTEN(RLMT_DEFAULT_TIMEOUT))) { + * RlmtCheckingState |= ChkSeg) + * PortCheckingState |= ChkSeg + * } + * NewTimeout = TO_SHORTEN(Timeout) + * if (NewTimeout < RLMT_MIN_TIMEOUT) { + * NewTimeout = RLMT_MIN_TIMEOUT + * PortState = PsDown + * ... + * } + * } + * else { # something was received + * # Set counter to 0 at LinkDown? + * # No - rx may be reported after LinkDown ??? + * PortCheckingState &= ~ChkRx + * NewTimeout = RLMT_DEFAULT_TIMEOUT + * if (RxAck == 0) { + * possible reasons: + * is my tx line bad? -- + * send RLMT multicast and report + * back internally? (only possible + * between ports on same adapter) + * } + * if (RxChk == 0) { + * possible reasons: + * - tx line of port set to check me + * maybe bad + * - no other port/adapter available or set + * to check me + * - adapter checking me has a longer + * timeout + * ??? anything that can be done here? + * } + * } + * + * Context: + * runtime, pageable? + * + * Returns: + * New timeout value. + */ +RLMT_STATIC SK_U32 SkRlmtCheckPort( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber) /* Port to check */ +{ + unsigned i; + SK_U32 NewTimeout; + SK_RLMT_PORT *pRPort; + SK_EVPARA Para; + + pRPort = &pAC->Rlmt.Port[PortNumber]; + + if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) == 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SkRlmtCheckPort %d: No (%d) receives in last time slot.\n", + PortNumber, pRPort->PacketsPerTimeSlot)) + + /* + * Check segmentation if there was no receive at least twice + * in a row (PortNoRx is already set) and the segmentation + * check is not currently running. + */ + + if (pRPort->PortNoRx && (pAC->Rlmt.Port[PortNumber].Net->LinksUp > 1) && + (pAC->Rlmt.Port[PortNumber].Net->RlmtMode & SK_RLMT_CHECK_SEG) && + !(pAC->Rlmt.Port[PortNumber].Net->CheckingState & SK_RLMT_RCS_SEG)) { + pAC->Rlmt.Port[PortNumber].Net->CheckingState |= + SK_RLMT_RCS_START_SEG | SK_RLMT_RCS_SEND_SEG; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SkRlmtCheckPort: PortsSuspect %d, PcsRx %d.\n", + pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX)) + + if (pRPort->PortState != SK_RLMT_PS_DOWN) { + NewTimeout = TO_SHORTEN(pAC->Rlmt.Port[PortNumber].Net->TimeoutValue); + if (NewTimeout < SK_RLMT_MIN_TO_VAL) { + NewTimeout = SK_RLMT_MIN_TO_VAL; + } + + if (!(pRPort->CheckingState & SK_RLMT_PCS_RX)) { + Para.Para32[0] = PortNumber; + pRPort->CheckingState |= SK_RLMT_PCS_RX; + + /* + * What shall we do if the port checked by this one receives + * our request frames? What's bad - our rx line or his tx line? + */ + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->DownRxTimer, + SK_RLMT_PORTDOWN_TIM_VAL, SKGE_RLMT, + SK_RLMT_PORTDOWN_RX_TIM, Para); + + for (i = 0; i < pRPort->PortsChecked; i++) { + if (pRPort->PortCheck[i].SuspectTx) { + continue; + } + pRPort->PortCheck[i].SuspectTx = SK_TRUE; + pRPort->PortsSuspect++; + if ((Para.pParaPtr = + SkRlmtBuildPacket(pAC, IoC, PortNumber, SK_PACKET_CHECK_TX, + &pAC->Addr.Port[PortNumber].CurrentMacAddress, + &pRPort->PortCheck[i].CheckAddr)) != NULL) { + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + } + } + } + else { /* PortDown -- or all partners suspect. */ + NewTimeout = SK_RLMT_DEF_TO_VAL; + } + pRPort->PortNoRx = SK_TRUE; + } + else { /* A non-BPDU packet was received. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SkRlmtCheckPort %d: %d (%d) receives in last time slot.\n", + PortNumber, + pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot, + pRPort->PacketsPerTimeSlot)) + + SkRlmtPortReceives(pAC, IoC, PortNumber); + if (pAC->Rlmt.CheckSwitch) { + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + } + + NewTimeout = SK_RLMT_DEF_TO_VAL; + } + + return (NewTimeout); +} /* SkRlmtCheckPort */ + + +/****************************************************************************** + * + * SkRlmtSelectBcRx - select new active port, criteria 1 (CLP) + * + * Description: + * This routine selects the port that received a broadcast frame + * substantially later than all other ports. + * + * Context: + * runtime, pageable? + * + * Returns: + * SK_BOOL + */ +RLMT_STATIC SK_BOOL SkRlmtSelectBcRx( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Active, /* Active port */ +SK_U32 PrefPort, /* Preferred port */ +SK_U32 *pSelect) /* New active port */ +{ + SK_U64 BcTimeStamp; + SK_U32 i; + SK_BOOL PortFound; + + BcTimeStamp = 0; /* Not totally necessary, but feeling better. */ + PortFound = SK_FALSE; + + /* Select port with the latest TimeStamp. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("TimeStamp Port %d (Down: %d, NoRx: %d): %08x %08x.\n", + i, + pAC->Rlmt.Port[i].PortDown, pAC->Rlmt.Port[i].PortNoRx, + *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_HI32), + *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32))) + + if (!pAC->Rlmt.Port[i].PortDown && !pAC->Rlmt.Port[i].PortNoRx) { + if (!PortFound || pAC->Rlmt.Port[i].BcTimeStamp > BcTimeStamp) { + BcTimeStamp = pAC->Rlmt.Port[i].BcTimeStamp; + *pSelect = i; + PortFound = SK_TRUE; + } + } + } + + if (PortFound) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Port %d received the last broadcast.\n", *pSelect)) + + /* Look if another port's time stamp is similar. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (i == *pSelect) { + continue; + } + if (!pAC->Rlmt.Port[i].PortDown && !pAC->Rlmt.Port[i].PortNoRx && + (pAC->Rlmt.Port[i].BcTimeStamp > + BcTimeStamp - SK_RLMT_BC_DELTA || + pAC->Rlmt.Port[i].BcTimeStamp + + SK_RLMT_BC_DELTA > BcTimeStamp)) { + PortFound = SK_FALSE; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Port %d received a broadcast at a similar time.\n", i)) + break; + } + } + } + +#ifdef DEBUG + if (PortFound) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SELECT_BCRX found Port %d receiving the substantially " + "latest broadcast (%u).\n", + *pSelect, + BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp)) + } +#endif /* DEBUG */ + + return (PortFound); +} /* SkRlmtSelectBcRx */ + + +/****************************************************************************** + * + * SkRlmtSelectNotSuspect - select new active port, criteria 2 (CLP) + * + * Description: + * This routine selects a good port (it is PortUp && !SuspectRx). + * + * Context: + * runtime, pageable? + * + * Returns: + * SK_BOOL + */ +RLMT_STATIC SK_BOOL SkRlmtSelectNotSuspect( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Active, /* Active port */ +SK_U32 PrefPort, /* Preferred port */ +SK_U32 *pSelect) /* New active port */ +{ + SK_U32 i; + SK_BOOL PortFound; + + PortFound = SK_FALSE; + + /* Select first port that is PortUp && !SuspectRx. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (!pAC->Rlmt.Port[i].PortDown && + !(pAC->Rlmt.Port[i].CheckingState & SK_RLMT_PCS_RX)) { + *pSelect = i; + if (!pAC->Rlmt.Port[Active].PortDown && + !(pAC->Rlmt.Port[Active].CheckingState & SK_RLMT_PCS_RX)) { + *pSelect = Active; + } + if (!pAC->Rlmt.Port[PrefPort].PortDown && + !(pAC->Rlmt.Port[PrefPort].CheckingState & SK_RLMT_PCS_RX)) { + *pSelect = PrefPort; + } + PortFound = SK_TRUE; + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SELECT_NOTSUSPECT found Port %d up and not check RX.\n", + *pSelect)) + break; + } + } + return (PortFound); +} /* SkRlmtSelectNotSuspect */ + + +/****************************************************************************** + * + * SkRlmtSelectUp - select new active port, criteria 3, 4 (CLP) + * + * Description: + * This routine selects a port that is up. + * + * Context: + * runtime, pageable? + * + * Returns: + * SK_BOOL + */ +RLMT_STATIC SK_BOOL SkRlmtSelectUp( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Active, /* Active port */ +SK_U32 PrefPort, /* Preferred port */ +SK_U32 *pSelect, /* New active port */ +SK_BOOL AutoNegDone) /* Successfully auto-negotiated? */ +{ + SK_U32 i; + SK_BOOL PortFound; + + PortFound = SK_FALSE; + + /* Select first port that is PortUp. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_UP && + pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) { + *pSelect = i; + if (pAC->Rlmt.Port[Active].PortState == SK_RLMT_PS_UP && + pAC->GIni.GP[Active].PAutoNegFail != AutoNegDone) { + *pSelect = Active; + } + if (pAC->Rlmt.Port[PrefPort].PortState == SK_RLMT_PS_UP && + pAC->GIni.GP[PrefPort].PAutoNegFail != AutoNegDone) { + *pSelect = PrefPort; + } + PortFound = SK_TRUE; + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect)) + break; + } + } + return (PortFound); +} /* SkRlmtSelectUp */ + + +/****************************************************************************** + * + * SkRlmtSelectGoingUp - select new active port, criteria 5, 6 (CLP) + * + * Description: + * This routine selects the port that is going up for the longest time. + * + * Context: + * runtime, pageable? + * + * Returns: + * SK_BOOL + */ +RLMT_STATIC SK_BOOL SkRlmtSelectGoingUp( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Active, /* Active port */ +SK_U32 PrefPort, /* Preferred port */ +SK_U32 *pSelect, /* New active port */ +SK_BOOL AutoNegDone) /* Successfully auto-negotiated? */ +{ + SK_U64 GuTimeStamp; + SK_U32 i; + SK_BOOL PortFound; + + GuTimeStamp = 0; + PortFound = SK_FALSE; + + /* Select port that is PortGoingUp for the longest time. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_GOING_UP && + pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) { + GuTimeStamp = pAC->Rlmt.Port[i].GuTimeStamp; + *pSelect = i; + PortFound = SK_TRUE; + break; + } + } + + if (!PortFound) { + return (SK_FALSE); + } + + for (i = *pSelect + 1; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_GOING_UP && + pAC->Rlmt.Port[i].GuTimeStamp < GuTimeStamp && + pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) { + GuTimeStamp = pAC->Rlmt.Port[i].GuTimeStamp; + *pSelect = i; + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect)) + return (SK_TRUE); +} /* SkRlmtSelectGoingUp */ + + +/****************************************************************************** + * + * SkRlmtSelectDown - select new active port, criteria 7, 8 (CLP) + * + * Description: + * This routine selects a port that is down. + * + * Context: + * runtime, pageable? + * + * Returns: + * SK_BOOL + */ +RLMT_STATIC SK_BOOL SkRlmtSelectDown( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Active, /* Active port */ +SK_U32 PrefPort, /* Preferred port */ +SK_U32 *pSelect, /* New active port */ +SK_BOOL AutoNegDone) /* Successfully auto-negotiated? */ +{ + SK_U32 i; + SK_BOOL PortFound; + + PortFound = SK_FALSE; + + /* Select first port that is PortDown. */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + if (pAC->Rlmt.Port[i].PortState == SK_RLMT_PS_DOWN && + pAC->GIni.GP[i].PAutoNegFail != AutoNegDone) { + *pSelect = i; + if (pAC->Rlmt.Port[Active].PortState == SK_RLMT_PS_DOWN && + pAC->GIni.GP[Active].PAutoNegFail != AutoNegDone) { + *pSelect = Active; + } + if (pAC->Rlmt.Port[PrefPort].PortState == SK_RLMT_PS_DOWN && + pAC->GIni.GP[PrefPort].PAutoNegFail != AutoNegDone) { + *pSelect = PrefPort; + } + PortFound = SK_TRUE; + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect)) + break; + } + } + return (PortFound); +} /* SkRlmtSelectDown */ + + +/****************************************************************************** + * + * SkRlmtCheckSwitch - select new active port and switch to it + * + * Description: + * This routine decides which port should be the active one and queues + * port switching if necessary. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing. + */ +RLMT_STATIC void SkRlmtCheckSwitch( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 NetIdx) /* Net index */ +{ + SK_EVPARA Para; + SK_U32 Active; + SK_U32 PrefPort; + SK_U32 i; + SK_BOOL PortFound; + + Active = pAC->Rlmt.Net[NetIdx].ActivePort; /* Index of active port. */ + PrefPort = pAC->Rlmt.Net[NetIdx].PrefPort; /* Index of preferred port. */ + PortFound = SK_FALSE; + pAC->Rlmt.CheckSwitch = SK_FALSE; + +#if 0 /* RW 2001/10/18 - active port becomes always prefered one */ + if (pAC->Rlmt.Net[NetIdx].Preference == 0xFFFFFFFF) { /* Automatic */ + /* disable auto-fail back */ + PrefPort = Active; + } +#endif + + if (pAC->Rlmt.Net[NetIdx].LinksUp == 0) { + /* Last link went down - shut down the net. */ + pAC->Rlmt.Net[NetIdx].RlmtState = SK_RLMT_RS_NET_DOWN; + Para.Para32[0] = SK_RLMT_NET_DOWN_TEMP; + Para.Para32[1] = NetIdx; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_DOWN, Para); + + Para.Para32[0] = pAC->Rlmt.Net[NetIdx]. + Port[pAC->Rlmt.Net[NetIdx].ActivePort]->PortNumber; + Para.Para32[1] = NetIdx; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_ACTIVE_DOWN, Para); + return; + } /* pAC->Rlmt.LinksUp == 0 */ + else if (pAC->Rlmt.Net[NetIdx].LinksUp == 1 && + pAC->Rlmt.Net[NetIdx].RlmtState == SK_RLMT_RS_NET_DOWN) { + /* First link came up - get the net up. */ + pAC->Rlmt.Net[NetIdx].RlmtState = SK_RLMT_RS_NET_UP; + + /* + * If pAC->Rlmt.ActivePort != Para.Para32[0], + * the DRV switches to the port that came up. + */ + for (i = 0; i < pAC->Rlmt.Net[NetIdx].NumPorts; i++) { + if (!pAC->Rlmt.Net[NetIdx].Port[i]->LinkDown) { + if (!pAC->Rlmt.Net[NetIdx].Port[Active]->LinkDown) { + i = Active; + } + if (!pAC->Rlmt.Net[NetIdx].Port[PrefPort]->LinkDown) { + i = PrefPort; + } + PortFound = SK_TRUE; + break; + } + } + + if (PortFound) { + Para.Para32[0] = pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber; + Para.Para32[1] = NetIdx; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_ACTIVE_UP, Para); + + pAC->Rlmt.Net[NetIdx].ActivePort = i; + Para.Para32[0] = pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber; + Para.Para32[1] = NetIdx; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_UP, Para); + + if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 && + (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, + pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber, + SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx]. + CurrentMacAddress, &SkRlmtMcAddr)) != NULL) { + /* + * Send announce packet to RLMT multicast address to force + * switches to learn the new location of the logical MAC address. + */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } + } + else { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E007, SKERR_RLMT_E007_MSG); + } + + return; + } /* LinksUp == 1 && RlmtState == SK_RLMT_RS_NET_DOWN */ + else { /* Cannot be reached in dual-net mode. */ + Para.Para32[0] = Active; + + /* + * Preselection: + * If RLMT Mode != CheckLinkState + * select port that received a broadcast frame substantially later + * than all other ports + * else select first port that is not SuspectRx + * else select first port that is PortUp + * else select port that is PortGoingUp for the longest time + * else select first port that is PortDown + * else stop. + * + * For the preselected port: + * If ActivePort is equal in quality, select ActivePort. + * + * If PrefPort is equal in quality, select PrefPort. + * + * If ActivePort != SelectedPort, + * If old ActivePort is LinkDown, + * SwitchHard + * else + * SwitchSoft + */ + /* check of ChgBcPrio flag added */ + if ((pAC->Rlmt.Net[0].RlmtMode != SK_RLMT_MODE_CLS) && + (!pAC->Rlmt.Net[0].ChgBcPrio)) { + + if (!PortFound) { + PortFound = SkRlmtSelectBcRx( + pAC, IoC, Active, PrefPort, &Para.Para32[1]); + } + + if (!PortFound) { + PortFound = SkRlmtSelectNotSuspect( + pAC, IoC, Active, PrefPort, &Para.Para32[1]); + } + } /* pAC->Rlmt.RlmtMode != SK_RLMT_MODE_CLS */ + + /* with changed priority for last broadcast received */ + if ((pAC->Rlmt.Net[0].RlmtMode != SK_RLMT_MODE_CLS) && + (pAC->Rlmt.Net[0].ChgBcPrio)) { + if (!PortFound) { + PortFound = SkRlmtSelectNotSuspect( + pAC, IoC, Active, PrefPort, &Para.Para32[1]); + } + + if (!PortFound) { + PortFound = SkRlmtSelectBcRx( + pAC, IoC, Active, PrefPort, &Para.Para32[1]); + } + } /* pAC->Rlmt.RlmtMode != SK_RLMT_MODE_CLS */ + + if (!PortFound) { + PortFound = SkRlmtSelectUp( + pAC, IoC, Active, PrefPort, &Para.Para32[1], AUTONEG_SUCCESS); + } + + if (!PortFound) { + PortFound = SkRlmtSelectUp( + pAC, IoC, Active, PrefPort, &Para.Para32[1], AUTONEG_FAILED); + } + + if (!PortFound) { + PortFound = SkRlmtSelectGoingUp( + pAC, IoC, Active, PrefPort, &Para.Para32[1], AUTONEG_SUCCESS); + } + + if (!PortFound) { + PortFound = SkRlmtSelectGoingUp( + pAC, IoC, Active, PrefPort, &Para.Para32[1], AUTONEG_FAILED); + } + + if (pAC->Rlmt.Net[0].RlmtMode != SK_RLMT_MODE_CLS) { + if (!PortFound) { + PortFound = SkRlmtSelectDown(pAC, IoC, + Active, PrefPort, &Para.Para32[1], AUTONEG_SUCCESS); + } + + if (!PortFound) { + PortFound = SkRlmtSelectDown(pAC, IoC, + Active, PrefPort, &Para.Para32[1], AUTONEG_FAILED); + } + } /* pAC->Rlmt.RlmtMode != SK_RLMT_MODE_CLS */ + + if (PortFound) { + + if (Para.Para32[1] != Active) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Active: %d, Para1: %d.\n", Active, Para.Para32[1])) + pAC->Rlmt.Net[NetIdx].ActivePort = Para.Para32[1]; + Para.Para32[0] = pAC->Rlmt.Net[NetIdx]. + Port[Para.Para32[0]]->PortNumber; + Para.Para32[1] = pAC->Rlmt.Net[NetIdx]. + Port[Para.Para32[1]]->PortNumber; + SK_HWAC_LINK_LED(pAC, IoC, Para.Para32[1], SK_LED_ACTIVE); + if (pAC->Rlmt.Port[Active].LinkDown) { + SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_HARD, Para); + } + else { + SK_HWAC_LINK_LED(pAC, IoC, Para.Para32[0], SK_LED_STANDBY); + SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_SOFT, Para); + } + Para.Para32[1] = NetIdx; + Para.Para32[0] = + pAC->Rlmt.Net[NetIdx].Port[Para.Para32[0]]->PortNumber; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_ACTIVE_DOWN, Para); + Para.Para32[0] = pAC->Rlmt.Net[NetIdx]. + Port[pAC->Rlmt.Net[NetIdx].ActivePort]->PortNumber; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_ACTIVE_UP, Para); + if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 && + (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], + SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx].CurrentMacAddress, + &SkRlmtMcAddr)) != NULL) { + /* + * Send announce packet to RLMT multicast address to force + * switches to learn the new location of the logical + * MAC address. + */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para); + } /* (Para.pParaPtr = SkRlmtBuildPacket(...)) != NULL */ + } /* Para.Para32[1] != Active */ + } /* PortFound */ + else { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E004, SKERR_RLMT_E004_MSG); + } + } /* LinksUp > 1 || LinksUp == 1 && RlmtState != SK_RLMT_RS_NET_DOWN */ + return; +} /* SkRlmtCheckSwitch */ + + +/****************************************************************************** + * + * SkRlmtCheckSeg - Report if segmentation is detected + * + * Description: + * This routine checks if the ports see different root bridges and reports + * segmentation in such a case. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing. + */ +RLMT_STATIC void SkRlmtCheckSeg( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 NetIdx) /* Net number */ +{ + SK_EVPARA Para; + SK_RLMT_NET *pNet; + SK_U32 i, j; + SK_BOOL Equal; + + pNet = &pAC->Rlmt.Net[NetIdx]; + pNet->RootIdSet = SK_FALSE; + Equal = SK_TRUE; + + for (i = 0; i < pNet->NumPorts; i++) { + if (pNet->Port[i]->LinkDown || !pNet->Port[i]->RootIdSet) { + continue; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_DUMP, + ("Root ID %d: %02x %02x %02x %02x %02x %02x %02x %02x.\n", i, + pNet->Port[i]->Root.Id[0], pNet->Port[i]->Root.Id[1], + pNet->Port[i]->Root.Id[2], pNet->Port[i]->Root.Id[3], + pNet->Port[i]->Root.Id[4], pNet->Port[i]->Root.Id[5], + pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7])) + + if (!pNet->RootIdSet) { + pNet->Root = pNet->Port[i]->Root; + pNet->RootIdSet = SK_TRUE; + continue; + } + + for (j = 0; j < 8; j ++) { + Equal &= pNet->Port[i]->Root.Id[j] == pNet->Root.Id[j]; + if (!Equal) { + break; + } + } + + if (!Equal) { + SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E005, SKERR_RLMT_E005_MSG); + Para.Para32[0] = NetIdx; + Para.Para32[1] = (SK_U32)-1; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SEGMENTATION, Para); + + pNet->CheckingState &= ~SK_RLMT_RCS_REPORT_SEG; + + /* 2000-03-06 RA: New. */ + Para.Para32[0] = NetIdx; + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pNet->SegTimer, SK_RLMT_SEG_TO_VAL, + SKGE_RLMT, SK_RLMT_SEG_TIM, Para); + break; + } + } /* for (i = 0; i < pNet->NumPorts; i++) */ + + /* 2000-03-06 RA: Moved here. */ + /* Segmentation check not running anymore. */ + pNet->CheckingState &= ~SK_RLMT_RCS_SEG; + +} /* SkRlmtCheckSeg */ + + +/****************************************************************************** + * + * SkRlmtPortStart - initialize port variables and start port + * + * Description: + * This routine initializes a port's variables and issues a PORT_START + * to the HWAC module. This handles retries if the start fails or the + * link eventually goes down. + * + * Context: + * runtime, pageable? + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtPortStart( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 PortNumber) /* Port number */ +{ + SK_EVPARA Para; + + pAC->Rlmt.Port[PortNumber].PortState = SK_RLMT_PS_LINK_DOWN; + pAC->Rlmt.Port[PortNumber].PortStarted = SK_TRUE; + pAC->Rlmt.Port[PortNumber].LinkDown = SK_TRUE; + pAC->Rlmt.Port[PortNumber].PortDown = SK_TRUE; + pAC->Rlmt.Port[PortNumber].CheckingState = 0; + pAC->Rlmt.Port[PortNumber].RootIdSet = SK_FALSE; + Para.Para32[0] = PortNumber; + Para.Para32[1] = (SK_U32)-1; + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para); +} /* SkRlmtPortStart */ + + +/****************************************************************************** + * + * SkRlmtEvtPortStartTim - PORT_START_TIM + * + * Description: + * This routine handles PORT_START_TIM events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPortStartTim( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ +{ + SK_U32 i; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n")) + return; + } + + /* + * Used to start non-preferred ports if the preferred one + * does not come up. + * This timeout needs only be set when starting the first + * (preferred) port. + */ + if (pAC->Rlmt.Port[Para.Para32[0]].LinkDown) { + /* PORT_START failed. */ + for (i = 0; i < pAC->Rlmt.Port[Para.Para32[0]].Net->NumPorts; i++) { + if (!pAC->Rlmt.Port[Para.Para32[0]].Net->Port[i]->PortStarted) { + SkRlmtPortStart(pAC, IoC, + pAC->Rlmt.Port[Para.Para32[0]].Net->Port[i]->PortNumber); + } + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n")) +} /* SkRlmtEvtPortStartTim */ + + +/****************************************************************************** + * + * SkRlmtEvtLinkUp - LINK_UP + * + * Description: + * This routine handles LLINK_UP events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtLinkUp( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 Undefined */ +{ + SK_U32 i; + SK_RLMT_PORT *pRPort; + SK_EVPARA Para2; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0])) + + pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; + if (!pRPort->PortStarted) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E008, SKERR_RLMT_E008_MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_UP Event EMPTY.\n")) + return; + } + + if (!pRPort->LinkDown) { + /* RA;:;: Any better solution? */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_UP Event EMPTY.\n")) + return; + } + + SkTimerStop(pAC, IoC, &pRPort->UpTimer); + SkTimerStop(pAC, IoC, &pRPort->DownRxTimer); + SkTimerStop(pAC, IoC, &pRPort->DownTxTimer); + + /* Do something if timer already fired? */ + + pRPort->LinkDown = SK_FALSE; + pRPort->PortState = SK_RLMT_PS_GOING_UP; + pRPort->GuTimeStamp = SkOsGetTime(pAC); + pRPort->BcTimeStamp = 0; + pRPort->Net->LinksUp++; + if (pRPort->Net->LinksUp == 1) { + SK_HWAC_LINK_LED(pAC, IoC, Para.Para32[0], SK_LED_ACTIVE); + } + else { + SK_HWAC_LINK_LED(pAC, IoC, Para.Para32[0], SK_LED_STANDBY); + } + + for (i = 0; i < pRPort->Net->NumPorts; i++) { + if (!pRPort->Net->Port[i]->PortStarted) { + SkRlmtPortStart(pAC, IoC, pRPort->Net->Port[i]->PortNumber); + } + } + + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + + if (pRPort->Net->LinksUp >= 2) { + if (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LOC_LINK) { + /* Build the check chain. */ + SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber); + } + } + + /* If the first link comes up, start the periodical RLMT timeout. */ + if (pRPort->Net->NumPorts > 1 && pRPort->Net->LinksUp == 1 && + (pRPort->Net->RlmtMode & SK_RLMT_CHECK_OTHERS) != 0) { + Para2.Para32[0] = pRPort->Net->NetNumber; + Para2.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->Net->LocTimer, + pRPort->Net->TimeoutValue, SKGE_RLMT, SK_RLMT_TIM, Para2); + } + + Para2 = Para; + Para2.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->UpTimer, SK_RLMT_PORTUP_TIM_VAL, + SKGE_RLMT, SK_RLMT_PORTUP_TIM, Para2); + + /* Later: if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) && */ + if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 && + (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 && + (Para2.pParaPtr = + SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE, + &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr) + ) != NULL) { + /* Send "new" packet to RLMT multicast address. */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2); + } + + if (pRPort->Net->RlmtMode & SK_RLMT_CHECK_SEG) { + if ((Para2.pParaPtr = + SkRlmtBuildSpanningTreePacket(pAC, IoC, Para.Para32[0])) != NULL) { + pAC->Rlmt.Port[Para.Para32[0]].RootIdSet = SK_FALSE; + pRPort->Net->CheckingState |= + SK_RLMT_RCS_SEG | SK_RLMT_RCS_REPORT_SEG; + + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2); + + Para.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pRPort->Net->SegTimer, + SK_RLMT_SEG_TO_VAL, SKGE_RLMT, SK_RLMT_SEG_TIM, Para); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_UP Event END.\n")) +} /* SkRlmtEvtLinkUp */ + + +/****************************************************************************** + * + * SkRlmtEvtPortUpTim - PORT_UP_TIM + * + * Description: + * This routine handles PORT_UP_TIM events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPortUpTim( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ +{ + SK_RLMT_PORT *pRPort; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTUP_TIM Event EMPTY.\n")) + return; + } + + pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; + if (pRPort->LinkDown || (pRPort->PortState == SK_RLMT_PS_UP)) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0])) + return; + } + + pRPort->PortDown = SK_FALSE; + pRPort->PortState = SK_RLMT_PS_UP; + pRPort->Net->PortsUp++; + if (pRPort->Net->RlmtState != SK_RLMT_RS_INIT) { + if (pAC->Rlmt.NumNets <= 1) { + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + } + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_PORT_UP, Para); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTUP_TIM Event END.\n")) +} /* SkRlmtEvtPortUpTim */ + + +/****************************************************************************** + * + * SkRlmtEvtPortDownTim - PORT_DOWN_* + * + * Description: + * This routine handles PORT_DOWN_* events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPortDownX( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Event, /* Event code */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ +{ + SK_RLMT_PORT *pRPort; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTDOWN* Port %d Event (%d) BEGIN.\n", + Para.Para32[0], Event)) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTDOWN* Event EMPTY.\n")) + return; + } + + pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; + if (!pRPort->PortStarted || (Event == SK_RLMT_PORTDOWN_TX_TIM && + !(pRPort->CheckingState & SK_RLMT_PCS_TX))) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event)) + return; + } + + /* Stop port's timers. */ + SkTimerStop(pAC, IoC, &pRPort->UpTimer); + SkTimerStop(pAC, IoC, &pRPort->DownRxTimer); + SkTimerStop(pAC, IoC, &pRPort->DownTxTimer); + + if (pRPort->PortState != SK_RLMT_PS_LINK_DOWN) { + pRPort->PortState = SK_RLMT_PS_DOWN; + } + + if (!pRPort->PortDown) { + pRPort->Net->PortsUp--; + pRPort->PortDown = SK_TRUE; + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_PORT_DOWN, Para); + } + + pRPort->PacketsPerTimeSlot = 0; + /* pRPort->DataPacketsPerTimeSlot = 0; */ + pRPort->BpduPacketsPerTimeSlot = 0; + pRPort->BcTimeStamp = 0; + + /* + * RA;:;: To be checked: + * - actions at RLMT_STOP: We should not switch anymore. + */ + if (pRPort->Net->RlmtState != SK_RLMT_RS_INIT) { + if (Para.Para32[0] == + pRPort->Net->Port[pRPort->Net->ActivePort]->PortNumber) { + /* Active Port went down. */ + SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event)) +} /* SkRlmtEvtPortDownX */ + + +/****************************************************************************** + * + * SkRlmtEvtLinkDown - LINK_DOWN + * + * Description: + * This routine handles LINK_DOWN events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtLinkDown( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 Undefined */ +{ + SK_RLMT_PORT *pRPort; + + pRPort = &pAC->Rlmt.Port[Para.Para32[0]]; + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0])) + + if (!pAC->Rlmt.Port[Para.Para32[0]].LinkDown) { + pRPort->Net->LinksUp--; + pRPort->LinkDown = SK_TRUE; + pRPort->PortState = SK_RLMT_PS_LINK_DOWN; + SK_HWAC_LINK_LED(pAC, IoC, Para.Para32[0], SK_LED_OFF); + + if ((pRPort->Net->RlmtMode & SK_RLMT_CHECK_LOC_LINK) != 0) { + /* Build the check chain. */ + SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber); + } + + /* Ensure that port is marked down. */ + Para.Para32[1] = -1; + (void)SkRlmtEvent(pAC, IoC, SK_RLMT_PORTDOWN, Para); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_LINK_DOWN Event END.\n")) +} /* SkRlmtEvtLinkDown */ + + +/****************************************************************************** + * + * SkRlmtEvtPortAddr - PORT_ADDR + * + * Description: + * This routine handles PORT_ADDR events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPortAddr( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortNumber; SK_U32 -1 */ +{ + SK_U32 i, j; + SK_RLMT_PORT *pRPort; + SK_MAC_ADDR *pOldMacAddr; + SK_MAC_ADDR *pNewMacAddr; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORT_ADDR Event EMPTY.\n")) + return; + } + + /* Port's physical MAC address changed. */ + pOldMacAddr = &pAC->Addr.Port[Para.Para32[0]].PreviousMacAddress; + pNewMacAddr = &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress; + + /* + * NOTE: This is not scalable for solutions where ports are + * checked remotely. There, we need to send an RLMT + * address change packet - and how do we ensure delivery? + */ + for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) { + pRPort = &pAC->Rlmt.Port[i]; + for (j = 0; j < pRPort->PortsChecked; j++) { + if (SK_ADDR_EQUAL( + pRPort->PortCheck[j].CheckAddr.a, pOldMacAddr->a)) { + pRPort->PortCheck[j].CheckAddr = *pNewMacAddr; + } + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PORT_ADDR Event END.\n")) +} /* SkRlmtEvtPortAddr */ + + +/****************************************************************************** + * + * SkRlmtEvtStart - START + * + * Description: + * This routine handles START events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtStart( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ + SK_EVPARA Para2; + SK_U32 PortIdx; + SK_U32 PortNumber; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[0])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Event EMPTY.\n")) + return; + } + + if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState != SK_RLMT_RS_INIT) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Event EMPTY.\n")) + return; + } + + if (pAC->Rlmt.NetsStarted >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("All nets should have been started.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Event EMPTY.\n")) + return; + } + + if (pAC->Rlmt.Net[Para.Para32[0]].PrefPort >= + pAC->Rlmt.Net[Para.Para32[0]].NumPorts) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E009, SKERR_RLMT_E009_MSG); + + /* Change PrefPort to internal default. */ + Para2.Para32[0] = 0xFFFFFFFF; + Para2.Para32[1] = Para.Para32[0]; + (void)SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE, Para2); + } + + PortIdx = pAC->Rlmt.Net[Para.Para32[0]].PrefPort; + PortNumber = pAC->Rlmt.Net[Para.Para32[0]].Port[PortIdx]->PortNumber; + + pAC->Rlmt.Net[Para.Para32[0]].LinksUp = 0; + pAC->Rlmt.Net[Para.Para32[0]].PortsUp = 0; + pAC->Rlmt.Net[Para.Para32[0]].CheckingState = 0; + pAC->Rlmt.Net[Para.Para32[0]].RlmtState = SK_RLMT_RS_NET_DOWN; + + /* Start preferred port. */ + SkRlmtPortStart(pAC, IoC, PortNumber); + + /* Start Timer (for first port only). */ + Para2.Para32[0] = PortNumber; + Para2.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pAC->Rlmt.Port[PortNumber].UpTimer, + SK_RLMT_PORTSTART_TIM_VAL, SKGE_RLMT, SK_RLMT_PORTSTART_TIM, Para2); + + pAC->Rlmt.NetsStarted++; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_START Event END.\n")) +} /* SkRlmtEvtStart */ + + +/****************************************************************************** + * + * SkRlmtEvtStop - STOP + * + * Description: + * This routine handles STOP events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtStop( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ + SK_EVPARA Para2; + SK_U32 PortNumber; + SK_U32 i; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[0])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Event EMPTY.\n")) + return; + } + + if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState == SK_RLMT_RS_INIT) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Event EMPTY.\n")) + return; + } + + if (pAC->Rlmt.NetsStarted == 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("All nets are stopped.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Event EMPTY.\n")) + return; + } + + /* Stop RLMT timers. */ + SkTimerStop(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[0]].LocTimer); + SkTimerStop(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[0]].SegTimer); + + /* Stop net. */ + pAC->Rlmt.Net[Para.Para32[0]].RlmtState = SK_RLMT_RS_INIT; + pAC->Rlmt.Net[Para.Para32[0]].RootIdSet = SK_FALSE; + Para2.Para32[0] = SK_RLMT_NET_DOWN_FINAL; + Para2.Para32[1] = Para.Para32[0]; /* Net# */ + SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_DOWN, Para2); + + /* Stop ports. */ + for (i = 0; i < pAC->Rlmt.Net[Para.Para32[0]].NumPorts; i++) { + PortNumber = pAC->Rlmt.Net[Para.Para32[0]].Port[i]->PortNumber; + if (pAC->Rlmt.Port[PortNumber].PortState != SK_RLMT_PS_INIT) { + SkTimerStop(pAC, IoC, &pAC->Rlmt.Port[PortNumber].UpTimer); + SkTimerStop(pAC, IoC, &pAC->Rlmt.Port[PortNumber].DownRxTimer); + SkTimerStop(pAC, IoC, &pAC->Rlmt.Port[PortNumber].DownTxTimer); + + pAC->Rlmt.Port[PortNumber].PortState = SK_RLMT_PS_INIT; + pAC->Rlmt.Port[PortNumber].RootIdSet = SK_FALSE; + pAC->Rlmt.Port[PortNumber].PortStarted = SK_FALSE; + Para2.Para32[0] = PortNumber; + Para2.Para32[1] = (SK_U32)-1; + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_STOP, Para2); + } + } + + pAC->Rlmt.NetsStarted--; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STOP Event END.\n")) +} /* SkRlmtEvtStop */ + + +/****************************************************************************** + * + * SkRlmtEvtTim - TIM + * + * Description: + * This routine handles TIM events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtTim( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ + SK_RLMT_PORT *pRPort; + SK_U32 Timeout; + SK_U32 NewTimeout; + SK_U32 PortNumber; + SK_U32 i; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_TIM Event BEGIN.\n")) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_TIM Event EMPTY.\n")) + return; + } + + if ((pAC->Rlmt.Net[Para.Para32[0]].RlmtMode & SK_RLMT_CHECK_OTHERS) == 0 || + pAC->Rlmt.Net[Para.Para32[0]].LinksUp == 0) { + /* Mode changed or all links down: No more link checking. */ + return; + } + +#if 0 + pAC->Rlmt.SwitchCheckCounter--; + if (pAC->Rlmt.SwitchCheckCounter == 0) { + pAC->Rlmt.SwitchCheckCounter; + } +#endif /* 0 */ + + NewTimeout = SK_RLMT_DEF_TO_VAL; + for (i = 0; i < pAC->Rlmt.Net[Para.Para32[0]].NumPorts; i++) { + PortNumber = pAC->Rlmt.Net[Para.Para32[0]].Port[i]->PortNumber; + pRPort = &pAC->Rlmt.Port[PortNumber]; + if (!pRPort->LinkDown) { + Timeout = SkRlmtCheckPort(pAC, IoC, PortNumber); + if (Timeout < NewTimeout) { + NewTimeout = Timeout; + } + + /* + * These counters should be set to 0 for all ports before the + * first frame is sent in the next loop. + */ + pRPort->PacketsPerTimeSlot = 0; + /* pRPort->DataPacketsPerTimeSlot = 0; */ + pRPort->BpduPacketsPerTimeSlot = 0; + } + } + pAC->Rlmt.Net[Para.Para32[0]].TimeoutValue = NewTimeout; + + if (pAC->Rlmt.Net[Para.Para32[0]].LinksUp > 1) { + /* + * If checking remote ports, also send packets if + * (LinksUp == 1) && + * this port checks at least one (remote) port. + */ + + /* + * Must be new loop, as SkRlmtCheckPort can request to + * check segmentation when e.g. checking the last port. + */ + for (i = 0; i < pAC->Rlmt.Net[Para.Para32[0]].NumPorts; i++) { + if (!pAC->Rlmt.Net[Para.Para32[0]].Port[i]->LinkDown) { + SkRlmtSend(pAC, IoC, + pAC->Rlmt.Net[Para.Para32[0]].Port[i]->PortNumber); + } + } + } + + SkTimerStart(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[0]].LocTimer, + pAC->Rlmt.Net[Para.Para32[0]].TimeoutValue, SKGE_RLMT, SK_RLMT_TIM, + Para); + + if (pAC->Rlmt.Net[Para.Para32[0]].LinksUp > 1 && + (pAC->Rlmt.Net[Para.Para32[0]].RlmtMode & SK_RLMT_CHECK_SEG) && + (pAC->Rlmt.Net[Para.Para32[0]].CheckingState & SK_RLMT_RCS_START_SEG)) { + SkTimerStart(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[0]].SegTimer, + SK_RLMT_SEG_TO_VAL, SKGE_RLMT, SK_RLMT_SEG_TIM, Para); + pAC->Rlmt.Net[Para.Para32[0]].CheckingState &= ~SK_RLMT_RCS_START_SEG; + pAC->Rlmt.Net[Para.Para32[0]].CheckingState |= + SK_RLMT_RCS_SEG | SK_RLMT_RCS_REPORT_SEG; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_TIM Event END.\n")) +} /* SkRlmtEvtTim */ + + +/****************************************************************************** + * + * SkRlmtEvtSegTim - SEG_TIM + * + * Description: + * This routine handles SEG_TIM events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtSegTim( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ +#ifdef xDEBUG + int j; +#endif /* DEBUG */ + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SEG_TIM Event BEGIN.\n")) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SEG_TIM Event EMPTY.\n")) + return; + } + +#ifdef xDEBUG + for (j = 0; j < pAC->Rlmt.Net[Para.Para32[0]].NumPorts; j++) { + SK_ADDR_PORT *pAPort; + SK_U32 k; + SK_U16 *InAddr; + SK_U8 InAddr8[6]; + + InAddr = (SK_U16 *)&InAddr8[0]; + pAPort = pAC->Rlmt.Net[Para.Para32[0]].Port[j]->AddrPort; + for (k = 0; k < pAPort->NextExactMatchRlmt; k++) { + /* Get exact match address k from port j. */ + XM_INADDR(IoC, pAC->Rlmt.Net[Para.Para32[0]].Port[j]->PortNumber, + XM_EXM(k), InAddr); + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("MC address %d on Port %u: %02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x.\n", + k, pAC->Rlmt.Net[Para.Para32[0]].Port[j]->PortNumber, + InAddr8[0], InAddr8[1], InAddr8[2], + InAddr8[3], InAddr8[4], InAddr8[5], + pAPort->Exact[k].a[0], pAPort->Exact[k].a[1], + pAPort->Exact[k].a[2], pAPort->Exact[k].a[3], + pAPort->Exact[k].a[4], pAPort->Exact[k].a[5])) + } + } +#endif /* xDEBUG */ + + SkRlmtCheckSeg(pAC, IoC, Para.Para32[0]); + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SEG_TIM Event END.\n")) +} /* SkRlmtEvtSegTim */ + + +/****************************************************************************** + * + * SkRlmtEvtPacketRx - PACKET_RECEIVED + * + * Description: + * This routine handles PACKET_RECEIVED events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPacketRx( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_MBUF *pMb */ +{ + SK_MBUF *pMb; + SK_MBUF *pNextMb; + SK_U32 NetNumber; + + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n")) + + /* Should we ignore frames during port switching? */ + +#ifdef DEBUG + pMb = Para.pParaPtr; + if (pMb == NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n")) + } + else if (pMb->pNext != NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("More than one mbuf or pMb->pNext not set.\n")) + } +#endif /* DEBUG */ + + for (pMb = Para.pParaPtr; pMb != NULL; pMb = pNextMb) { + pNextMb = pMb->pNext; + pMb->pNext = NULL; + + NetNumber = pAC->Rlmt.Port[pMb->PortIdx].Net->NetNumber; + if (pAC->Rlmt.Net[NetNumber].RlmtState == SK_RLMT_RS_INIT) { + SkDrvFreeRlmtMbuf(pAC, IoC, pMb); + } + else { + SkRlmtPacketReceive(pAC, IoC, pMb); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PACKET_RECEIVED Event END.\n")) +} /* SkRlmtEvtPacketRx */ + + +/****************************************************************************** + * + * SkRlmtEvtStatsClear - STATS_CLEAR + * + * Description: + * This routine handles STATS_CLEAR events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtStatsClear( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ + SK_U32 i; + SK_RLMT_PORT *pRPort; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_CLEAR Event BEGIN.\n")) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_CLEAR Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[0])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_CLEAR Event EMPTY.\n")) + return; + } + + /* Clear statistics for logical and physical ports. */ + for (i = 0; i < pAC->Rlmt.Net[Para.Para32[0]].NumPorts; i++) { + pRPort = + &pAC->Rlmt.Port[pAC->Rlmt.Net[Para.Para32[0]].Port[i]->PortNumber]; + pRPort->TxHelloCts = 0; + pRPort->RxHelloCts = 0; + pRPort->TxSpHelloReqCts = 0; + pRPort->RxSpHelloCts = 0; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_CLEAR Event END.\n")) +} /* SkRlmtEvtStatsClear */ + + +/****************************************************************************** + * + * SkRlmtEvtStatsUpdate - STATS_UPDATE + * + * Description: + * This routine handles STATS_UPDATE events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtStatsUpdate( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_UPDATE Event BEGIN.\n")) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_UPDATE Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[0])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_UPDATE Event EMPTY.\n")) + return; + } + + /* Update statistics - currently always up-to-date. */ + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_STATS_UPDATE Event END.\n")) +} /* SkRlmtEvtStatsUpdate */ + + +/****************************************************************************** + * + * SkRlmtEvtPrefportChange - PREFPORT_CHANGE + * + * Description: + * This routine handles PREFPORT_CHANGE events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtPrefportChange( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 PortIndex; SK_U32 NetNumber */ +{ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0])) + + if (Para.Para32[1] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[1])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n")) + return; + } + + /* 0xFFFFFFFF == auto-mode. */ + if (Para.Para32[0] == 0xFFFFFFFF) { + pAC->Rlmt.Net[Para.Para32[1]].PrefPort = SK_RLMT_DEF_PREF_PORT; + } + else { + if (Para.Para32[0] >= pAC->Rlmt.Net[Para.Para32[1]].NumPorts) { + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E010, SKERR_RLMT_E010_MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n")) + return; + } + + pAC->Rlmt.Net[Para.Para32[1]].PrefPort = Para.Para32[0]; + } + + pAC->Rlmt.Net[Para.Para32[1]].Preference = Para.Para32[0]; + + if (pAC->Rlmt.Net[Para.Para32[1]].RlmtState != SK_RLMT_RS_INIT) { + SkRlmtCheckSwitch(pAC, IoC, Para.Para32[1]); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_PREFPORT_CHANGE Event END.\n")) +} /* SkRlmtEvtPrefportChange */ + + +/****************************************************************************** + * + * SkRlmtEvtSetNets - SET_NETS + * + * Description: + * This routine handles SET_NETS events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtSetNets( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NumNets; SK_U32 -1 */ +{ + int i; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event BEGIN.\n")) + + if (Para.Para32[1] != (SK_U32)-1) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad Parameter.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] == 0 || Para.Para32[0] > SK_MAX_NETS || + Para.Para32[0] > (SK_U32)pAC->GIni.GIMacsFound) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad number of nets: %d.\n", Para.Para32[0])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] == pAC->Rlmt.NumNets) { /* No change. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event EMPTY.\n")) + return; + } + + /* Entering and leaving dual mode only allowed while nets are stopped. */ + if (pAC->Rlmt.NetsStarted > 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Changing dual mode only allowed while all nets are stopped.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event EMPTY.\n")) + return; + } + + if (Para.Para32[0] == 1) { + if (pAC->Rlmt.NumNets > 1) { + /* Clear logical MAC addr from second net's active port. */ + (void)SkAddrOverride(pAC, IoC, pAC->Rlmt.Net[1].Port[pAC->Addr. + Net[1].ActivePort]->PortNumber, NULL, SK_ADDR_CLEAR_LOGICAL); + pAC->Rlmt.Net[1].NumPorts = 0; + } + + pAC->Rlmt.NumNets = Para.Para32[0]; + for (i = 0; (SK_U32)i < pAC->Rlmt.NumNets; i++) { + pAC->Rlmt.Net[i].RlmtState = SK_RLMT_RS_INIT; + pAC->Rlmt.Net[i].RootIdSet = SK_FALSE; + pAC->Rlmt.Net[i].Preference = 0xFFFFFFFF; /* "Automatic" */ + pAC->Rlmt.Net[i].PrefPort = SK_RLMT_DEF_PREF_PORT; + /* Just assuming. */ + pAC->Rlmt.Net[i].ActivePort = pAC->Rlmt.Net[i].PrefPort; + pAC->Rlmt.Net[i].RlmtMode = SK_RLMT_DEF_MODE; + pAC->Rlmt.Net[i].TimeoutValue = SK_RLMT_DEF_TO_VAL; + pAC->Rlmt.Net[i].NetNumber = i; + } + + pAC->Rlmt.Port[1].Net= &pAC->Rlmt.Net[0]; + pAC->Rlmt.Net[0].NumPorts = pAC->GIni.GIMacsFound; + + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para); + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("RLMT: Changed to one net with two ports.\n")) + } + else if (Para.Para32[0] == 2) { + pAC->Rlmt.Port[1].Net= &pAC->Rlmt.Net[1]; + pAC->Rlmt.Net[1].NumPorts = pAC->GIni.GIMacsFound - 1; + pAC->Rlmt.Net[0].NumPorts = + pAC->GIni.GIMacsFound - pAC->Rlmt.Net[1].NumPorts; + + pAC->Rlmt.NumNets = Para.Para32[0]; + for (i = 0; (SK_U32)i < pAC->Rlmt.NumNets; i++) { + pAC->Rlmt.Net[i].RlmtState = SK_RLMT_RS_INIT; + pAC->Rlmt.Net[i].RootIdSet = SK_FALSE; + pAC->Rlmt.Net[i].Preference = 0xFFFFFFFF; /* "Automatic" */ + pAC->Rlmt.Net[i].PrefPort = SK_RLMT_DEF_PREF_PORT; + /* Just assuming. */ + pAC->Rlmt.Net[i].ActivePort = pAC->Rlmt.Net[i].PrefPort; + pAC->Rlmt.Net[i].RlmtMode = SK_RLMT_DEF_MODE; + pAC->Rlmt.Net[i].TimeoutValue = SK_RLMT_DEF_TO_VAL; + + pAC->Rlmt.Net[i].NetNumber = i; + } + + /* Set logical MAC addr on second net's active port. */ + (void)SkAddrOverride(pAC, IoC, pAC->Rlmt.Net[1].Port[pAC->Addr. + Net[1].ActivePort]->PortNumber, NULL, SK_ADDR_SET_LOGICAL); + + SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para); + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("RLMT: Changed to two nets with one port each.\n")) + } + else { + /* Not implemented for more than two nets. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SetNets not implemented for more than two nets.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event EMPTY.\n")) + return; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_SET_NETS Event END.\n")) +} /* SkRlmtSetNets */ + + +/****************************************************************************** + * + * SkRlmtEvtModeChange - MODE_CHANGE + * + * Description: + * This routine handles MODE_CHANGE events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * Nothing + */ +RLMT_STATIC void SkRlmtEvtModeChange( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_EVPARA Para) /* SK_U32 NewMode; SK_U32 NetNumber */ +{ + SK_EVPARA Para2; + SK_U32 i; + SK_U32 PrevRlmtMode; + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_MODE_CHANGE Event BEGIN.\n")) + + if (Para.Para32[1] >= pAC->Rlmt.NumNets) { + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Bad NetNumber %d.\n", Para.Para32[1])) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_MODE_CHANGE Event EMPTY.\n")) + return; + } + + Para.Para32[0] |= SK_RLMT_CHECK_LINK; + + if ((pAC->Rlmt.Net[Para.Para32[1]].NumPorts == 1) && + Para.Para32[0] != SK_RLMT_MODE_CLS) { + pAC->Rlmt.Net[Para.Para32[1]].RlmtMode = SK_RLMT_MODE_CLS; + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Forced RLMT mode to CLS on single port net.\n")) + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_MODE_CHANGE Event EMPTY.\n")) + return; + } + + /* Update RLMT mode. */ + PrevRlmtMode = pAC->Rlmt.Net[Para.Para32[1]].RlmtMode; + pAC->Rlmt.Net[Para.Para32[1]].RlmtMode = Para.Para32[0]; + + if ((PrevRlmtMode & SK_RLMT_CHECK_LOC_LINK) != + (pAC->Rlmt.Net[Para.Para32[1]].RlmtMode & SK_RLMT_CHECK_LOC_LINK)) { + /* SK_RLMT_CHECK_LOC_LINK bit changed. */ + if ((PrevRlmtMode & SK_RLMT_CHECK_OTHERS) == 0 && + pAC->Rlmt.Net[Para.Para32[1]].NumPorts > 1 && + pAC->Rlmt.Net[Para.Para32[1]].PortsUp >= 1) { + /* 20001207 RA: Was "PortsUp == 1". */ + Para2.Para32[0] = Para.Para32[1]; + Para2.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[1]].LocTimer, + pAC->Rlmt.Net[Para.Para32[1]].TimeoutValue, + SKGE_RLMT, SK_RLMT_TIM, Para2); + } + } + + if ((PrevRlmtMode & SK_RLMT_CHECK_SEG) != + (pAC->Rlmt.Net[Para.Para32[1]].RlmtMode & SK_RLMT_CHECK_SEG)) { + /* SK_RLMT_CHECK_SEG bit changed. */ + for (i = 0; i < pAC->Rlmt.Net[Para.Para32[1]].NumPorts; i++) { + (void)SkAddrMcClear(pAC, IoC, + pAC->Rlmt.Net[Para.Para32[1]].Port[i]->PortNumber, + SK_ADDR_PERMANENT | SK_MC_SW_ONLY); + + /* Add RLMT MC address. */ + (void)SkAddrMcAdd(pAC, IoC, + pAC->Rlmt.Net[Para.Para32[1]].Port[i]->PortNumber, + &SkRlmtMcAddr, SK_ADDR_PERMANENT); + + if ((pAC->Rlmt.Net[Para.Para32[1]].RlmtMode & + SK_RLMT_CHECK_SEG) != 0) { + /* Add BPDU MC address. */ + (void)SkAddrMcAdd(pAC, IoC, + pAC->Rlmt.Net[Para.Para32[1]].Port[i]->PortNumber, + &BridgeMcAddr, SK_ADDR_PERMANENT); + + if (pAC->Rlmt.Net[Para.Para32[1]].RlmtState != SK_RLMT_RS_INIT) { + if (!pAC->Rlmt.Net[Para.Para32[1]].Port[i]->LinkDown && + (Para2.pParaPtr = SkRlmtBuildSpanningTreePacket( + pAC, IoC, i)) != NULL) { + pAC->Rlmt.Net[Para.Para32[1]].Port[i]->RootIdSet = + SK_FALSE; + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2); + } + } + } + (void)SkAddrMcUpdate(pAC, IoC, + pAC->Rlmt.Net[Para.Para32[1]].Port[i]->PortNumber); + } /* for ... */ + + if ((pAC->Rlmt.Net[Para.Para32[1]].RlmtMode & SK_RLMT_CHECK_SEG) != 0) { + Para2.Para32[0] = Para.Para32[1]; + Para2.Para32[1] = (SK_U32)-1; + SkTimerStart(pAC, IoC, &pAC->Rlmt.Net[Para.Para32[1]].SegTimer, + SK_RLMT_SEG_TO_VAL, SKGE_RLMT, SK_RLMT_SEG_TIM, Para2); + } + } /* SK_RLMT_CHECK_SEG bit changed. */ + + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("SK_RLMT_MODE_CHANGE Event END.\n")) +} /* SkRlmtEvtModeChange */ + + +/****************************************************************************** + * + * SkRlmtEvent - a PORT- or an RLMT-specific event happened + * + * Description: + * This routine calls subroutines to handle PORT- and RLMT-specific events. + * + * Context: + * runtime, pageable? + * may be called after SK_INIT_IO + * + * Returns: + * 0 + */ +int SkRlmtEvent( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +SK_U32 Event, /* Event code */ +SK_EVPARA Para) /* Event-specific parameter */ +{ + switch (Event) { + + /* ----- PORT events ----- */ + + case SK_RLMT_PORTSTART_TIM: /* From RLMT via TIME. */ + SkRlmtEvtPortStartTim(pAC, IoC, Para); + break; + case SK_RLMT_LINK_UP: /* From SIRQ. */ + SkRlmtEvtLinkUp(pAC, IoC, Para); + break; + case SK_RLMT_PORTUP_TIM: /* From RLMT via TIME. */ + SkRlmtEvtPortUpTim(pAC, IoC, Para); + break; + case SK_RLMT_PORTDOWN: /* From RLMT. */ + case SK_RLMT_PORTDOWN_RX_TIM: /* From RLMT via TIME. */ + case SK_RLMT_PORTDOWN_TX_TIM: /* From RLMT via TIME. */ + SkRlmtEvtPortDownX(pAC, IoC, Event, Para); + break; + case SK_RLMT_LINK_DOWN: /* From SIRQ. */ + SkRlmtEvtLinkDown(pAC, IoC, Para); + break; + case SK_RLMT_PORT_ADDR: /* From ADDR. */ + SkRlmtEvtPortAddr(pAC, IoC, Para); + break; + + /* ----- RLMT events ----- */ + + case SK_RLMT_START: /* From DRV. */ + SkRlmtEvtStart(pAC, IoC, Para); + break; + case SK_RLMT_STOP: /* From DRV. */ + SkRlmtEvtStop(pAC, IoC, Para); + break; + case SK_RLMT_TIM: /* From RLMT via TIME. */ + SkRlmtEvtTim(pAC, IoC, Para); + break; + case SK_RLMT_SEG_TIM: + SkRlmtEvtSegTim(pAC, IoC, Para); + break; + case SK_RLMT_PACKET_RECEIVED: /* From DRV. */ + SkRlmtEvtPacketRx(pAC, IoC, Para); + break; + case SK_RLMT_STATS_CLEAR: /* From PNMI. */ + SkRlmtEvtStatsClear(pAC, IoC, Para); + break; + case SK_RLMT_STATS_UPDATE: /* From PNMI. */ + SkRlmtEvtStatsUpdate(pAC, IoC, Para); + break; + case SK_RLMT_PREFPORT_CHANGE: /* From PNMI. */ + SkRlmtEvtPrefportChange(pAC, IoC, Para); + break; + case SK_RLMT_MODE_CHANGE: /* From PNMI. */ + SkRlmtEvtModeChange(pAC, IoC, Para); + break; + case SK_RLMT_SET_NETS: /* From DRV. */ + SkRlmtEvtSetNets(pAC, IoC, Para); + break; + + /* ----- Unknown events ----- */ + + default: /* Create error log entry. */ + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, + ("Unknown RLMT Event %d.\n", Event)) + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E003, SKERR_RLMT_E003_MSG); + break; + } /* switch() */ + + return (0); +} /* SkRlmtEvent */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/sktimer.c b/drivers/sk98lin/sktimer.c new file mode 100644 index 000000000..37cd4c9fe --- /dev/null +++ b/drivers/sk98lin/sktimer.c @@ -0,0 +1,297 @@ +/****************************************************************************** + * + * Name: sktimer.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.12 $ + * Date: $Date: 1999/11/22 13:38:51 $ + * Purpose: High level timer functions. + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998,1999 SysKonnect, + * a business unit of Schneider & Koch & Co. Datensysteme GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: sktimer.c,v $ + * Revision 1.12 1999/11/22 13:38:51 cgoos + * Changed license header to GPL. + * + * Revision 1.11 1998/12/17 13:24:13 gklug + * fix: restart problem: do NOT destroy timer queue if init 1 is done + * + * Revision 1.10 1998/10/15 15:11:36 gklug + * fix: ID_sccs to SysKonnectFileId + * + * Revision 1.9 1998/09/15 15:15:04 cgoos + * Changed TRUE/FALSE to SK_TRUE/SK_FALSE + * + * Revision 1.8 1998/09/08 08:47:55 gklug + * add: init level handling + * + * Revision 1.7 1998/08/19 09:50:53 gklug + * fix: remove struct keyword from c-code (see CCC) add typedefs + * + * Revision 1.6 1998/08/17 13:43:13 gklug + * chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR + * + * Revision 1.5 1998/08/14 07:09:14 gklug + * fix: chg pAc -> pAC + * + * Revision 1.4 1998/08/07 12:53:46 gklug + * fix: first compiled version + * + * Revision 1.3 1998/08/07 09:31:53 gklug + * fix: delta spelling + * + * Revision 1.2 1998/08/07 09:31:02 gklug + * adapt functions to new c coding conventions + * rmv: "fast" handling + * chg: inserting of new timer in queue. + * chg: event queue generation when timer runs out + * + * Revision 1.1 1998/08/05 11:27:55 gklug + * first version: adapted from SMT + * + * + * + * + ******************************************************************************/ + + +#include + +#ifdef CONFIG_SK98 + +/* + Event queue and dispatcher +*/ +static const char SysKonnectFileId[] = + "$Header: /usr56/projects/ge/schedule/sktimer.c,v 1.12 1999/11/22 13:38:51 cgoos Exp $" ; + +#include "h/skdrv1st.h" /* Driver Specific Definitions */ +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */ + +#ifdef __C2MAN__ +/* + Event queue management. + + General Description: + + */ +intro() +{} +#endif + + +/* Forward declaration */ +static void timer_done(SK_AC *pAC,SK_IOC Ioc,int Restart); + + +/* + * Inits the software timer + * + * needs to be called during Init level 1. + */ +void SkTimerInit( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc, /* IoContext */ +int Level) /* Init Level */ +{ + switch (Level) { + case SK_INIT_DATA: + pAC->Tim.StQueue = 0 ; + break; + case SK_INIT_IO: + SkHwtInit(pAC,Ioc) ; + SkTimerDone(pAC, Ioc); + break; + default: + break; + } +} + +/* + * Stops a high level timer + * - If a timer is not in the queue the function returns normally, too. + */ +void SkTimerStop( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc, /* IoContext */ +SK_TIMER *pTimer) /* Timer Pointer to be started */ +{ + SK_TIMER **ppTimPrev ; + SK_TIMER *pTm ; + + /* + * remove timer from queue + */ + pTimer->TmActive = SK_FALSE ; + if (pAC->Tim.StQueue == pTimer && !pTimer->TmNext) { + SkHwtStop(pAC,Ioc) ; + } + for (ppTimPrev = &pAC->Tim.StQueue ; (pTm = *ppTimPrev) ; + ppTimPrev = &pTm->TmNext ) { + if (pTm == pTimer) { + /* + * Timer found in queue + * - dequeue it and + * - correct delta of the next timer + */ + *ppTimPrev = pTm->TmNext ; + + if (pTm->TmNext) { + /* correct delta of next timer in queue */ + pTm->TmNext->TmDelta += pTm->TmDelta ; + } + return ; + } + } +} + +/* + * Start a high level software timer + */ +void SkTimerStart( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc, /* IoContext */ +SK_TIMER *pTimer, /* Timer Pointer to be started */ +SK_U32 Time, /* Time value */ +SK_U32 Class, /* Event Class for this timer */ +SK_U32 Event, /* Event Value for this timer */ +SK_EVPARA Para) /* Event Parameter for this timer */ +{ + SK_TIMER **ppTimPrev ; + SK_TIMER *pTm ; + SK_U32 Delta ; + + Time /= 16 ; /* input is uS, clock ticks are 16uS */ + if (!Time) + Time = 1 ; + + SkTimerStop(pAC,Ioc,pTimer) ; + + pTimer->TmClass = Class ; + pTimer->TmEvent = Event ; + pTimer->TmPara = Para ; + pTimer->TmActive = SK_TRUE ; + + if (!pAC->Tim.StQueue) { + /* First Timer to be started */ + pAC->Tim.StQueue = pTimer ; + pTimer->TmNext = 0 ; + pTimer->TmDelta = Time ; + SkHwtStart(pAC,Ioc,Time) ; + return ; + } + + /* + * timer correction + */ + timer_done(pAC,Ioc,0) ; + + /* + * find position in queue + */ + Delta = 0 ; + for (ppTimPrev = &pAC->Tim.StQueue ; (pTm = *ppTimPrev) ; + ppTimPrev = &pTm->TmNext ) { + if (Delta + pTm->TmDelta > Time) { + /* Position found */ + /* Here the timer needs to be inserted. */ + break ; + } + Delta += pTm->TmDelta ; + } + + /* insert in queue */ + *ppTimPrev = pTimer ; + pTimer->TmNext = pTm ; + pTimer->TmDelta = Time - Delta ; + + if (pTm) { + /* There is a next timer + * -> correct its Delta value. + */ + pTm->TmDelta -= pTimer->TmDelta ; + } + + /* + * start new with first + */ + SkHwtStart(pAC,Ioc,pAC->Tim.StQueue->TmDelta) ; +} + + +void SkTimerDone( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc) /* IoContext */ +{ + timer_done(pAC,Ioc,1) ; +} + + +static void timer_done( +SK_AC *pAC, /* Adapters context */ +SK_IOC Ioc, /* IoContext */ +int Restart) /* Do we need to restart the Hardware timer ? */ +{ + SK_U32 Delta ; + SK_TIMER *pTm ; + SK_TIMER *pTComp ; /* Timer completed now now */ + SK_TIMER **ppLast ; /* Next field of Last timer to be deq */ + int Done = 0 ; + + Delta = SkHwtRead(pAC,Ioc) ; + ppLast = &pAC->Tim.StQueue ; + pTm = pAC->Tim.StQueue ; + while (pTm && !Done) { + if (Delta >= pTm->TmDelta) { + /* Timer ran out */ + pTm->TmActive = SK_FALSE ; + Delta -= pTm->TmDelta ; + ppLast = &pTm->TmNext ; + pTm = pTm->TmNext ; + } else { + /* We found the first timer that did not run out */ + pTm->TmDelta -= Delta ; + Delta = 0 ; + Done = 1 ; + } + } + *ppLast = 0 ; + /* + * pTm points to the first Timer that did not run out. + * StQueue points to the first Timer that run out. + */ + + for ( pTComp = pAC->Tim.StQueue ; pTComp ; pTComp = pTComp->TmNext) { + SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent, + pTComp->TmPara) ; + } + + /* Set head of timer queue to the first timer that did not run out */ + pAC->Tim.StQueue = pTm ; + + if (Restart && pAC->Tim.StQueue) { + /* Restart HW timer */ + SkHwtStart(pAC,Ioc,pAC->Tim.StQueue->TmDelta) ; + } +} + +#endif /* CONFIG_SK98 */ + +/* End of file */ diff --git a/drivers/sk98lin/skvpd.c b/drivers/sk98lin/skvpd.c new file mode 100644 index 000000000..3b81e67df --- /dev/null +++ b/drivers/sk98lin/skvpd.c @@ -0,0 +1,1329 @@ +/****************************************************************************** + * + * Name: skvpd.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.37 $ + * Date: $Date: 2003/01/13 10:42:45 $ + * Purpose: Shared software to read and write VPD data + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skvpd.c,v $ + * Revision 1.37 2003/01/13 10:42:45 rschmidt + * Replaced check for PCI device Id from YUKON with GENESIS + * to set the VPD size in VpdInit() + * Editorial changes + * + * Revision 1.36 2002/11/14 15:16:56 gheinig + * Added const specifier to key and buf parameters for VpdPara, VpdRead + * and VpdWrite for Diag 7 GUI + * + * Revision 1.35 2002/10/21 14:31:59 gheinig + * Took out CVS web garbage at head of file + * + * Revision 1.34 2002/10/21 11:47:24 gheinig + * Reverted to version 1.32 due to unwanted commit + * + * Revision 1.32 2002/10/14 16:04:29 rschmidt + * Added saving of VPD ROM Size from PCI_OUR_REG_2 + * Avoid reading of PCI_OUR_REG_2 in VpdTransferBlock() + * Editorial changes + * + * Revision 1.31 2002/09/10 09:21:32 mkarl + * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis + * + * Revision 1.30 2002/09/09 14:43:03 mkarl + * changes for diagnostics in order to read VPD data before the adapter + * has been initialized + * editorial changes + * + * Revision 1.29 2002/07/26 13:20:43 mkarl + * added Yukon support + * save size of VPD in pAC->vpd.vpd_size + * + * Revision 1.28 2002/04/02 15:31:47 afischer + * Bug fix in VpdWait() + * + * Revision 1.27 2000/08/10 11:29:06 rassmann + * Editorial changes. + * Preserving 32-bit alignment in structs for the adapter context. + * Removed unused function VpdWriteDword() (#if 0). + * Made VpdReadKeyword() available for SKDIAG only. + * + * Revision 1.26 2000/06/13 08:00:01 mkarl + * additional cast to avoid compile problems in 64 bit environment + * + * Revision 1.25 1999/11/22 13:39:32 cgoos + * Changed license header to GPL. + * + * Revision 1.24 1999/03/11 14:25:49 malthoff + * Replace __STDC__ with SK_KR_PROTO. + * + * Revision 1.23 1999/01/11 15:13:11 gklug + * fix: syntax error + * + * Revision 1.22 1998/10/30 06:41:15 gklug + * rmv: WARNING + * + * Revision 1.21 1998/10/29 07:15:14 gklug + * fix: Write Stream function needs verify. + * + * Revision 1.20 1998/10/28 18:05:08 gklug + * chg: no DEBUG in VpdMayWrite + * + * Revision 1.19 1998/10/28 15:56:11 gklug + * fix: Return len at end of ReadStream + * fix: Write even less than 4 bytes correctly + * + * Revision 1.18 1998/10/28 09:00:47 gklug + * fix: unreferenced local vars + * + * Revision 1.17 1998/10/28 08:25:45 gklug + * fix: WARNING + * + * Revision 1.16 1998/10/28 08:17:30 gklug + * fix: typo + * + * Revision 1.15 1998/10/28 07:50:32 gklug + * fix: typo + * + * Revision 1.14 1998/10/28 07:20:38 gklug + * chg: Interface functions to use IoC as parameter as well + * fix: VpdRead/WriteDWord now returns SK_U32 + * chg: VPD_IN/OUT names conform to SK_IN/OUT + * add: usage of VPD_IN/OUT8 macros + * add: VpdRead/Write Stream functions to r/w a stream of data + * fix: VpdTransferBlock swapped illegal + * add: VpdMayWrite + * + * Revision 1.13 1998/10/22 10:02:37 gklug + * fix: SysKonnectFileId typo + * + * Revision 1.12 1998/10/20 10:01:01 gklug + * fix: parameter to SkOsGetTime + * + * Revision 1.11 1998/10/15 12:51:48 malthoff + * Remove unrequired parameter p in vpd_setup_para(). + * + * Revision 1.10 1998/10/08 14:52:43 malthoff + * Remove CvsId by SysKonnectFileId. + * + * Revision 1.9 1998/09/16 07:33:52 malthoff + * replace memcmp() by SK_MEMCMP and + * memcpy() by SK_MEMCPY() to be + * independent from the 'C' Standard Library. + * + * Revision 1.8 1998/08/19 12:52:35 malthoff + * compiler fix: use SK_VPD_KEY instead of S_VPD. + * + * Revision 1.7 1998/08/19 08:14:01 gklug + * fix: remove struct keyword as much as possible from the C-code (see CCC) + * + * Revision 1.6 1998/08/18 13:03:58 gklug + * SkOsGetTime now returns SK_U64 + * + * Revision 1.5 1998/08/18 08:17:29 malthoff + * Ensure we issue a VPD read in vpd_read_dword(). + * Discard all VPD keywords other than Vx or Yx, where + * x is '0..9' or 'A..Z'. + * + * Revision 1.4 1998/07/03 14:52:19 malthoff + * Add category SK_DBGCAT_FATAL to some debug macros. + * bug fix: correct the keyword name check in vpd_write(). + * + * Revision 1.3 1998/06/26 11:16:53 malthoff + * Correct the modified File Identifier. + * + * Revision 1.2 1998/06/26 11:13:43 malthoff + * Modify the File Identifier. + * + * Revision 1.1 1998/06/19 14:11:08 malthoff + * Created, Tests with AIX were performed successfully + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +/* + Please refer skvpd.txt for infomation how to include this module + */ +static const char SysKonnectFileId[] = + "@(#)$Id: skvpd.c,v 1.37 2003/01/13 10:42:45 rschmidt Exp $ (C) SK"; + +#include "h/skdrv1st.h" +#include "h/sktypes.h" +#include "h/skdebug.h" +#include "h/skdrv2nd.h" + +/* + * Static functions + */ +#ifndef SK_KR_PROTO +static SK_VPD_PARA *vpd_find_para( + SK_AC *pAC, + const char *key, + SK_VPD_PARA *p); +#else /* SK_KR_PROTO */ +static SK_VPD_PARA *vpd_find_para(); +#endif /* SK_KR_PROTO */ + +/* + * waits for a completion of a VPD transfer + * The VPD transfer must complete within SK_TICKS_PER_SEC/16 + * + * returns 0: success, transfer completes + * error exit(9) with a error message + */ +static int VpdWait( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC, /* IO Context */ +int event) /* event to wait for (VPD_READ / VPD_write) completion*/ +{ + SK_U64 start_time; + SK_U16 state; + + SK_DBG_MSG(pAC,SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD wait for %s\n", event?"Write":"Read")); + start_time = SkOsGetTime(pAC); + do { + if (SkOsGetTime(pAC) - start_time > SK_TICKS_PER_SEC) { + + /* Bug fix AF: Thu Mar 28 2002 + * Do not call: VPD_STOP(pAC, IoC); + * A pending VPD read cycle can not be aborted by writing + * VPD_WRITE to the PCI_VPD_ADR_REG (VPD address register). + * Although the write threshold in the OUR-register protects + * VPD read only space from being overwritten this does not + * protect a VPD read from being `converted` into a VPD write + * operation (on the fly). As a consequence the VPD_STOP would + * delete VPD read only data. In case of any problems with the + * I2C bus we exit the loop here. The I2C read operation can + * not be aborted except by a reset (->LR). + */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_FATAL | SK_DBGCAT_ERR, + ("ERROR:VPD wait timeout\n")); + return(1); + } + + VPD_IN16(pAC, IoC, PCI_VPD_ADR_REG, &state); + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("state = %x, event %x\n",state,event)); + } while((int)(state & PCI_VPD_FLAG) == event); + + return(0); +} + +#ifdef SKDIAG + +/* + * Read the dword at address 'addr' from the VPD EEPROM. + * + * Needed Time: MIN 1,3 ms MAX 2,6 ms + * + * Note: The DWord is returned in the endianess of the machine the routine + * is running on. + * + * Returns the data read. + */ +SK_U32 VpdReadDWord( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC, /* IO Context */ +int addr) /* VPD address */ +{ + SK_U32 Rtv; + + /* start VPD read */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD read dword at 0x%x\n",addr)); + addr &= ~VPD_WRITE; /* ensure the R/W bit is set to read */ + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)addr); + + /* ignore return code here */ + (void)VpdWait(pAC, IoC, VPD_READ); + + /* Don't swap here, it's a data stream of bytes */ + Rtv = 0; + + VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &Rtv); + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD read dword data = 0x%x\n",Rtv)); + return(Rtv); +} + +#endif /* SKDIAG */ + +#if 0 + +/* + Write the dword 'data' at address 'addr' into the VPD EEPROM, and + verify that the data is written. + + Needed Time: + +. MIN MAX +. ------------------------------------------------------------------- +. write 1.8 ms 3.6 ms +. internal write cyles 0.7 ms 7.0 ms +. ------------------------------------------------------------------- +. over all program time 2.5 ms 10.6 ms +. read 1.3 ms 2.6 ms +. ------------------------------------------------------------------- +. over all 3.8 ms 13.2 ms +. + + + Returns 0: success + 1: error, I2C transfer does not terminate + 2: error, data verify error + + */ +static int VpdWriteDWord( +SK_AC *pAC, /* pAC pointer */ +SK_IOC IoC, /* IO Context */ +int addr, /* VPD address */ +SK_U32 data) /* VPD data to write */ +{ + /* start VPD write */ + /* Don't swap here, it's a data stream of bytes */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD write dword at addr 0x%x, data = 0x%x\n",addr,data)); + VPD_OUT32(pAC, IoC, PCI_VPD_DAT_REG, (SK_U32)data); + /* But do it here */ + addr |= VPD_WRITE; + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)(addr | VPD_WRITE)); + + /* this may take up to 10,6 ms */ + if (VpdWait(pAC, IoC, VPD_WRITE)) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("Write Timed Out\n")); + return(1); + }; + + /* verify data */ + if (VpdReadDWord(pAC, IoC, addr) != data) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Data Verify Error\n")); + return(2); + } + return(0); +} /* VpdWriteDWord */ + +#endif /* 0 */ + +/* + * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from + * or to the I2C EEPROM. + * + * Returns number of bytes read / written. + */ +static int VpdWriteStream( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC, /* IO Context */ +char *buf, /* data buffer */ +int Addr, /* VPD start address */ +int Len) /* number of bytes to read / to write */ +{ + int i; + int j; + SK_U16 AdrReg; + int Rtv; + SK_U8 * pComp; /* Compare pointer */ + SK_U8 Data; /* Input Data for Compare */ + + /* Init Compare Pointer */ + pComp = (SK_U8 *) buf; + + for (i = 0; i < Len; i++, buf++) { + if ((i%sizeof(SK_U32)) == 0) { + /* + * At the begin of each cycle read the Data Reg + * So it is initialized even if only a few bytes + * are written. + */ + AdrReg = (SK_U16) Addr; + AdrReg &= ~VPD_WRITE; /* READ operation */ + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg); + + /* Wait for termination */ + Rtv = VpdWait(pAC, IoC, VPD_READ); + if (Rtv != 0) { + return(i); + } + } + + /* Write current Byte */ + VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)), + *(SK_U8*)buf); + + if (((i%sizeof(SK_U32)) == 3) || (i == (Len - 1))) { + /* New Address needs to be written to VPD_ADDR reg */ + AdrReg = (SK_U16) Addr; + Addr += sizeof(SK_U32); + AdrReg |= VPD_WRITE; /* WRITE operation */ + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg); + + /* Wait for termination */ + Rtv = VpdWait(pAC, IoC, VPD_WRITE); + if (Rtv != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("Write Timed Out\n")); + return(i - (i%sizeof(SK_U32))); + } + + /* + * Now re-read to verify + */ + AdrReg &= ~VPD_WRITE; /* READ operation */ + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg); + + /* Wait for termination */ + Rtv = VpdWait(pAC, IoC, VPD_READ); + if (Rtv != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("Verify Timed Out\n")); + return(i - (i%sizeof(SK_U32))); + } + + for (j = 0; j <= (int)(i%sizeof(SK_U32)); j++, pComp++) { + + VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + j, &Data); + + if (Data != *pComp) { + /* Verify Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("WriteStream Verify Error\n")); + return(i - (i%sizeof(SK_U32)) + j); + } + } + } + } + + return(Len); +} + + +/* + * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from + * or to the I2C EEPROM. + * + * Returns number of bytes read / written. + */ +static int VpdReadStream( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC, /* IO Context */ +char *buf, /* data buffer */ +int Addr, /* VPD start address */ +int Len) /* number of bytes to read / to write */ +{ + int i; + SK_U16 AdrReg; + int Rtv; + + for (i = 0; i < Len; i++, buf++) { + if ((i%sizeof(SK_U32)) == 0) { + /* New Address needs to be written to VPD_ADDR reg */ + AdrReg = (SK_U16) Addr; + Addr += sizeof(SK_U32); + AdrReg &= ~VPD_WRITE; /* READ operation */ + + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg); + + /* Wait for termination */ + Rtv = VpdWait(pAC, IoC, VPD_READ); + if (Rtv != 0) { + return(i); + } + } + VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)), + (SK_U8 *)buf); + } + + return(Len); +} + +/* + * Read ore writes 'len' bytes of VPD data, starting at 'addr' from + * or to the I2C EEPROM. + * + * Returns number of bytes read / written. + */ +static int VpdTransferBlock( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC, /* IO Context */ +char *buf, /* data buffer */ +int addr, /* VPD start address */ +int len, /* number of bytes to read / to write */ +int dir) /* transfer direction may be VPD_READ or VPD_WRITE */ +{ + int Rtv; /* Return value */ + int vpd_rom_size; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD %s block, addr = 0x%x, len = %d\n", + dir ? "write" : "read", addr, len)); + + if (len == 0) + return(0); + + vpd_rom_size = pAC->vpd.rom_size; + + if (addr > vpd_rom_size - 4) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Address error: 0x%x, exp. < 0x%x\n", + addr, vpd_rom_size - 4)); + return(0); + } + + if (addr + len > vpd_rom_size) { + len = vpd_rom_size - addr; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("Warning: len was cut to %d\n", len)); + } + + if (dir == VPD_READ) { + Rtv = VpdReadStream(pAC, IoC, buf, addr, len); + } + else { + Rtv = VpdWriteStream(pAC, IoC, buf, addr, len); + } + + return(Rtv); +} + +#ifdef SKDIAG + +/* + * Read 'len' bytes of VPD data, starting at 'addr'. + * + * Returns number of bytes read. + */ +int VpdReadBlock( +SK_AC *pAC, /* pAC pointer */ +SK_IOC IoC, /* IO Context */ +char *buf, /* buffer were the data should be stored */ +int addr, /* start reading at the VPD address */ +int len) /* number of bytes to read */ +{ + return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_READ)); +} + +/* + * Write 'len' bytes of *but to the VPD EEPROM, starting at 'addr'. + * + * Returns number of bytes writes. + */ +int VpdWriteBlock( +SK_AC *pAC, /* pAC pointer */ +SK_IOC IoC, /* IO Context */ +char *buf, /* buffer, holds the data to write */ +int addr, /* start writing at the VPD address */ +int len) /* number of bytes to write */ +{ + return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_WRITE)); +} +#endif /* SKDIAG */ + +/* + * (re)initialize the VPD buffer + * + * Reads the VPD data from the EEPROM into the VPD buffer. + * Get the remaining read only and read / write space. + * + * return 0: success + * 1: fatal VPD error + */ +static int VpdInit( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC) /* IO Context */ +{ + SK_VPD_PARA *r, rp; /* RW or RV */ + int i; + unsigned char x; + int vpd_size; + SK_U16 dev_id; + SK_U32 our_reg2; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit .. ")); + + VPD_IN16(pAC, IoC, PCI_DEVICE_ID, &dev_id); + + VPD_IN32(pAC, IoC, PCI_OUR_REG_2, &our_reg2); + + pAC->vpd.rom_size = 256 << ((our_reg2 & PCI_VPD_ROM_SZ) >> 14); + + /* + * this function might get used before the hardware is initialized + * therefore we cannot always trust in GIChipId + */ + if (((pAC->vpd.v.vpd_status & VPD_VALID) == 0 && + dev_id != VPD_DEV_ID_GENESIS) || + ((pAC->vpd.v.vpd_status & VPD_VALID) != 0 && + !pAC->GIni.GIGenesis)) { + + /* for Yukon the VPD size is always 256 */ + vpd_size = VPD_SIZE_YUKON; + } + else { + /* Genesis uses the maximum ROM size up to 512 for VPD */ + if (pAC->vpd.rom_size > VPD_SIZE_GENESIS) { + vpd_size = VPD_SIZE_GENESIS; + } + else { + vpd_size = pAC->vpd.rom_size; + } + } + + /* read the VPD data into the VPD buffer */ + if (VpdTransferBlock(pAC, IoC, pAC->vpd.vpd_buf, 0, vpd_size, VPD_READ) + != vpd_size) { + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("Block Read Error\n")); + return(1); + } + + pAC->vpd.vpd_size = vpd_size; + + /* find the end tag of the RO area */ + if (!(r = vpd_find_para(pAC, VPD_RV, &rp))) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Encoding Error: RV Tag not found\n")); + return(1); + } + + if (r->p_val + r->p_len > pAC->vpd.vpd_buf + vpd_size/2) { + SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Encoding Error: Invalid VPD struct size\n")); + return(1); + } + pAC->vpd.v.vpd_free_ro = r->p_len - 1; + + /* test the checksum */ + for (i = 0, x = 0; (unsigned)i <= (unsigned)vpd_size/2 - r->p_len; i++) { + x += pAC->vpd.vpd_buf[i]; + } + + if (x != 0) { + /* checksum error */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("VPD Checksum Error\n")); + return(1); + } + + /* find and check the end tag of the RW area */ + if (!(r = vpd_find_para(pAC, VPD_RW, &rp))) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Encoding Error: RV Tag not found\n")); + return(1); + } + + if (r->p_val < pAC->vpd.vpd_buf + vpd_size/2) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Encoding Error: Invalid VPD struct size\n")); + return(1); + } + pAC->vpd.v.vpd_free_rw = r->p_len; + + /* everything seems to be ok */ + if (pAC->GIni.GIChipId != 0) { + pAC->vpd.v.vpd_status |= VPD_VALID; + } + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, + ("done. Free RO = %d, Free RW = %d\n", + pAC->vpd.v.vpd_free_ro, pAC->vpd.v.vpd_free_rw)); + + return(0); +} + +/* + * find the Keyword 'key' in the VPD buffer and fills the + * parameter struct 'p' with it's values + * + * returns *p success + * 0: parameter was not found or VPD encoding error + */ +static SK_VPD_PARA *vpd_find_para( +SK_AC *pAC, /* common data base */ +const char *key, /* keyword to find (e.g. "MN") */ +SK_VPD_PARA *p) /* parameter description struct */ +{ + char *v ; /* points to VPD buffer */ + int max; /* Maximum Number of Iterations */ + + v = pAC->vpd.vpd_buf; + max = 128; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD find para %s .. ",key)); + + /* check mandatory resource type ID string (Product Name) */ + if (*v != (char)RES_ID) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Error: 0x%x missing\n", RES_ID)); + return(0); + } + + if (strcmp(key, VPD_NAME) == 0) { + p->p_len = VPD_GET_RES_LEN(v); + p->p_val = VPD_GET_VAL(v); + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("found, len = %d\n", p->p_len)); + return(p); + } + + v += 3 + VPD_GET_RES_LEN(v) + 3; + for (;; ) { + if (SK_MEMCMP(key,v,2) == 0) { + p->p_len = VPD_GET_VPD_LEN(v); + p->p_val = VPD_GET_VAL(v); + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("found, len = %d\n",p->p_len)); + return(p); + } + + /* exit when reaching the "RW" Tag or the maximum of itera. */ + max--; + if (SK_MEMCMP(VPD_RW,v,2) == 0 || max == 0) { + break; + } + + if (SK_MEMCMP(VPD_RV,v,2) == 0) { + v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */ + } + else { + v += 3 + VPD_GET_VPD_LEN(v); + } + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("scanning '%c%c' len = %d\n",v[0],v[1],v[2])); + } + +#ifdef DEBUG + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, ("not found\n")); + if (max == 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Key/Len Encoding error\n")); + } +#endif /* DEBUG */ + return(0); +} + +/* + * Move 'n' bytes. Begin with the last byte if 'n' is > 0, + * Start with the last byte if n is < 0. + * + * returns nothing + */ +static void vpd_move_para( +char *start, /* start of memory block */ +char *end, /* end of memory block to move */ +int n) /* number of bytes the memory block has to be moved */ +{ + char *p; + int i; /* number of byte copied */ + + if (n == 0) + return; + + i = (int) (end - start + 1); + if (n < 0) { + p = start + n; + while (i != 0) { + *p++ = *start++; + i--; + } + } + else { + p = end + n; + while (i != 0) { + *p-- = *end--; + i--; + } + } +} + +/* + * setup the VPD keyword 'key' at 'ip'. + * + * returns nothing + */ +static void vpd_insert_key( +const char *key, /* keyword to insert */ +const char *buf, /* buffer with the keyword value */ +int len, /* length of the value string */ +char *ip) /* inseration point */ +{ + SK_VPD_KEY *p; + + p = (SK_VPD_KEY *) ip; + p->p_key[0] = key[0]; + p->p_key[1] = key[1]; + p->p_len = (unsigned char) len; + SK_MEMCPY(&p->p_val,buf,len); +} + +/* + * Setup the VPD end tag "RV" / "RW". + * Also correct the remaining space variables vpd_free_ro / vpd_free_rw. + * + * returns 0: success + * 1: encoding error + */ +static int vpd_mod_endtag( +SK_AC *pAC, /* common data base */ +char *etp) /* end pointer input position */ +{ + SK_VPD_KEY *p; + unsigned char x; + int i; + int vpd_size; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD modify endtag at 0x%x = '%c%c'\n",etp,etp[0],etp[1])); + + vpd_size = pAC->vpd.vpd_size; + + p = (SK_VPD_KEY *) etp; + + if (p->p_key[0] != 'R' || (p->p_key[1] != 'V' && p->p_key[1] != 'W')) { + /* something wrong here, encoding error */ + SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL, + ("Encoding Error: invalid end tag\n")); + return(1); + } + if (etp > pAC->vpd.vpd_buf + vpd_size/2) { + /* create "RW" tag */ + p->p_len = (unsigned char)(pAC->vpd.vpd_buf+vpd_size-etp-3-1); + pAC->vpd.v.vpd_free_rw = (int) p->p_len; + i = pAC->vpd.v.vpd_free_rw; + etp += 3; + } + else { + /* create "RV" tag */ + p->p_len = (unsigned char)(pAC->vpd.vpd_buf+vpd_size/2-etp-3); + pAC->vpd.v.vpd_free_ro = (int) p->p_len - 1; + + /* setup checksum */ + for (i = 0, x = 0; i < vpd_size/2 - p->p_len; i++) { + x += pAC->vpd.vpd_buf[i]; + } + p->p_val = (char) 0 - x; + i = pAC->vpd.v.vpd_free_ro; + etp += 4; + } + while (i) { + *etp++ = 0x00; + i--; + } + + return(0); +} + +/* + * Insert a VPD keyword into the VPD buffer. + * + * The keyword 'key' is inserted at the position 'ip' in the + * VPD buffer. + * The keywords behind the input position will + * be moved. The VPD end tag "RV" or "RW" is generated again. + * + * returns 0: success + * 2: value string was cut + * 4: VPD full, keyword was not written + * 6: fatal VPD error + * + */ +int VpdSetupPara( +SK_AC *pAC, /* common data base */ +const char *key, /* keyword to insert */ +const char *buf, /* buffer with the keyword value */ +int len, /* length of the keyword value */ +int type, /* VPD_RO_KEY or VPD_RW_KEY */ +int op) /* operation to do: ADD_KEY or OWR_KEY */ +{ + SK_VPD_PARA vp; + char *etp; /* end tag position */ + int free; /* remaining space in selected area */ + char *ip; /* input position inside the VPD buffer */ + int rtv; /* return code */ + int head; /* additional haeder bytes to move */ + int found; /* additinoal bytes if the keyword was found */ + int vpd_size; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("VPD setup para key = %s, val = %s\n",key,buf)); + + vpd_size = pAC->vpd.vpd_size; + + rtv = 0; + ip = 0; + if (type == VPD_RW_KEY) { + /* end tag is "RW" */ + free = pAC->vpd.v.vpd_free_rw; + etp = pAC->vpd.vpd_buf + (vpd_size - free - 1 - 3); + } + else { + /* end tag is "RV" */ + free = pAC->vpd.v.vpd_free_ro; + etp = pAC->vpd.vpd_buf + (vpd_size/2 - free - 4); + } + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("Free RO = %d, Free RW = %d\n", + pAC->vpd.v.vpd_free_ro, pAC->vpd.v.vpd_free_rw)); + + head = 0; + found = 0; + if (op == OWR_KEY) { + if (vpd_find_para(pAC, key, &vp)) { + found = 3; + ip = vp.p_val - 3; + free += vp.p_len + 3; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("Overwrite Key\n")); + } + else { + op = ADD_KEY; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL, + ("Add Key\n")); + } + } + if (op == ADD_KEY) { + ip = etp; + vp.p_len = 0; + head = 3; + } + + if (len + 3 > free) { + if (free < 7) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD Buffer Overflow, keyword not written\n")); + return(4); + } + /* cut it again */ + len = free - 3; + rtv = 2; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD Buffer Full, Keyword was cut\n")); + } + + vpd_move_para(ip + vp.p_len + found, etp+2, len-vp.p_len+head); + vpd_insert_key(key, buf, len, ip); + if (vpd_mod_endtag(pAC, etp + len - vp.p_len + head)) { + pAC->vpd.v.vpd_status &= ~VPD_VALID; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD Encoding Error\n")); + return(6); + } + + return(rtv); +} + + +/* + * Read the contents of the VPD EEPROM and copy it to the + * VPD buffer if not already done. + * + * return: A pointer to the vpd_status structure. The structure contains + * this fields. + */ +SK_VPD_STATUS *VpdStat( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC) /* IO Context */ +{ + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + (void)VpdInit(pAC, IoC); + } + return(&pAC->vpd.v); +} + + +/* + * Read the contents of the VPD EEPROM and copy it to the VPD + * buffer if not already done. + * Scan the VPD buffer for VPD keywords and create the VPD + * keyword list by copying the keywords to 'buf', all after + * each other and terminated with a '\0'. + * + * Exceptions: o The Resource Type ID String (product name) is called "Name" + * o The VPD end tags 'RV' and 'RW' are not listed + * + * The number of copied keywords is counted in 'elements'. + * + * returns 0: success + * 2: buffer overfull, one or more keywords are missing + * 6: fatal VPD error + * + * example values after returning: + * + * buf = "Name\0PN\0EC\0MN\0SN\0CP\0VF\0VL\0YA\0" + * *len = 30 + * *elements = 9 + */ +int VpdKeys( +SK_AC *pAC, /* common data base */ +SK_IOC IoC, /* IO Context */ +char *buf, /* buffer where to copy the keywords */ +int *len, /* buffer length */ +int *elements) /* number of keywords returned */ +{ + char *v; + int n; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("list VPD keys .. ")); + *elements = 0; + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + if (VpdInit(pAC, IoC) != 0) { + *len = 0; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD Init Error, terminated\n")); + return(6); + } + } + + if ((signed)strlen(VPD_NAME) + 1 <= *len) { + v = pAC->vpd.vpd_buf; + strcpy(buf,VPD_NAME); + n = strlen(VPD_NAME) + 1; + buf += n; + *elements = 1; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, + ("'%c%c' ",v[0],v[1])); + } + else { + *len = 0; + SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR, + ("buffer overflow\n")); + return(2); + } + + v += 3 + VPD_GET_RES_LEN(v) + 3; + for (;; ) { + /* exit when reaching the "RW" Tag */ + if (SK_MEMCMP(VPD_RW,v,2) == 0) { + break; + } + + if (SK_MEMCMP(VPD_RV,v,2) == 0) { + v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */ + continue; + } + + if (n+3 <= *len) { + SK_MEMCPY(buf,v,2); + buf += 2; + *buf++ = '\0'; + n += 3; + v += 3 + VPD_GET_VPD_LEN(v); + *elements += 1; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, + ("'%c%c' ",v[0],v[1])); + } + else { + *len = n; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("buffer overflow\n")); + return(2); + } + } + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("\n")); + *len = n; + return(0); +} + + +/* + * Read the contents of the VPD EEPROM and copy it to the + * VPD buffer if not already done. Search for the VPD keyword + * 'key' and copy its value to 'buf'. Add a terminating '\0'. + * If the value does not fit into the buffer cut it after + * 'len' - 1 bytes. + * + * returns 0: success + * 1: keyword not found + * 2: value string was cut + * 3: VPD transfer timeout + * 6: fatal VPD error + */ +int VpdRead( +SK_AC *pAC, /* common data base */ +SK_IOC IoC, /* IO Context */ +const char *key, /* keyword to read (e.g. "MN") */ +char *buf, /* buffer where to copy the keyword value */ +int *len) /* buffer length */ +{ + SK_VPD_PARA *p, vp; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("VPD read %s .. ", key)); + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + if (VpdInit(pAC, IoC) != 0) { + *len = 0; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD init error\n")); + return(6); + } + } + + if ((p = vpd_find_para(pAC, key, &vp)) != NULL) { + if (p->p_len > (*(unsigned *)len)-1) { + p->p_len = *len - 1; + } + SK_MEMCPY(buf, p->p_val, p->p_len); + buf[p->p_len] = '\0'; + *len = p->p_len; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, + ("%c%c%c%c.., len = %d\n", + buf[0],buf[1],buf[2],buf[3],*len)); + } + else { + *len = 0; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, ("not found\n")); + return(1); + } + return(0); +} + + +/* + * Check whether a given key may be written + * + * returns + * SK_TRUE Yes it may be written + * SK_FALSE No it may be written + */ +SK_BOOL VpdMayWrite( +char *key) /* keyword to write (allowed values "Yx", "Vx") */ +{ + if ((*key != 'Y' && *key != 'V') || + key[1] < '0' || key[1] > 'Z' || + (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) { + + return(SK_FALSE); + } + return(SK_TRUE); +} + +/* + * Read the contents of the VPD EEPROM and copy it to the VPD + * buffer if not already done. Insert/overwrite the keyword 'key' + * in the VPD buffer. Cut the keyword value if it does not fit + * into the VPD read / write area. + * + * returns 0: success + * 2: value string was cut + * 3: VPD transfer timeout + * 4: VPD full, keyword was not written + * 5: keyword cannot be written + * 6: fatal VPD error + */ +int VpdWrite( +SK_AC *pAC, /* common data base */ +SK_IOC IoC, /* IO Context */ +const char *key, /* keyword to write (allowed values "Yx", "Vx") */ +const char *buf) /* buffer where the keyword value can be read from */ +{ + int len; /* length of the keyword to write */ + int rtv; /* return code */ + int rtv2; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, + ("VPD write %s = %s\n",key,buf)); + + if ((*key != 'Y' && *key != 'V') || + key[1] < '0' || key[1] > 'Z' || + (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) { + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("illegal key tag, keyword not written\n")); + return(5); + } + + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + if (VpdInit(pAC, IoC) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD init error\n")); + return(6); + } + } + + rtv = 0; + len = strlen(buf); + if (len > VPD_MAX_LEN) { + /* cut it */ + len = VPD_MAX_LEN; + rtv = 2; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("keyword too long, cut after %d bytes\n",VPD_MAX_LEN)); + } + if ((rtv2 = VpdSetupPara(pAC, key, buf, len, VPD_RW_KEY, OWR_KEY)) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD write error\n")); + return(rtv2); + } + + return(rtv); +} + +/* + * Read the contents of the VPD EEPROM and copy it to the + * VPD buffer if not already done. Remove the VPD keyword + * 'key' from the VPD buffer. + * Only the keywords in the read/write area can be deleted. + * Keywords in the read only area cannot be deleted. + * + * returns 0: success, keyword was removed + * 1: keyword not found + * 5: keyword cannot be deleted + * 6: fatal VPD error + */ +int VpdDelete( +SK_AC *pAC, /* common data base */ +SK_IOC IoC, /* IO Context */ +char *key) /* keyword to read (e.g. "MN") */ +{ + SK_VPD_PARA *p, vp; + char *etp; + int vpd_size; + + vpd_size = pAC->vpd.vpd_size; + + SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("VPD delete key %s\n",key)); + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + if (VpdInit(pAC, IoC) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD init error\n")); + return(6); + } + } + + if ((p = vpd_find_para(pAC, key, &vp)) != NULL) { + if (p->p_val < pAC->vpd.vpd_buf + vpd_size/2) { + /* try to delete read only keyword */ + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("cannot delete RO keyword\n")); + return(5); + } + + etp = pAC->vpd.vpd_buf + (vpd_size-pAC->vpd.v.vpd_free_rw-1-3); + + vpd_move_para(vp.p_val+vp.p_len, etp+2, + - ((int)(vp.p_len + 3))); + if (vpd_mod_endtag(pAC, etp - vp.p_len - 3)) { + pAC->vpd.v.vpd_status &= ~VPD_VALID; + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD encoding error\n")); + return(6); + } + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("keyword not found\n")); + return(1); + } + + return(0); +} + +/* + * If the VPD buffer contains valid data write the VPD + * read/write area back to the VPD EEPROM. + * + * returns 0: success + * 3: VPD transfer timeout + */ +int VpdUpdate( +SK_AC *pAC, /* Adapters context */ +SK_IOC IoC) /* IO Context */ +{ + int vpd_size; + + vpd_size = pAC->vpd.vpd_size; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("VPD update .. ")); + if ((pAC->vpd.v.vpd_status & VPD_VALID) != 0) { + if (VpdTransferBlock(pAC, IoC, pAC->vpd.vpd_buf + vpd_size/2, + vpd_size/2, vpd_size/2, VPD_WRITE) != vpd_size/2) { + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("transfer timed out\n")); + return(3); + } + } + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("done\n")); + return(0); +} + + +/* + * Read the contents of the VPD EEPROM and copy it to the VPD buffer + * if not already done. If the keyword "VF" is not present it will be + * created and the error log message will be stored to this keyword. + * If "VF" is not present the error log message will be stored to the + * keyword "VL". "VL" will created or overwritten if "VF" is present. + * The VPD read/write area is saved to the VPD EEPROM. + * + * returns nothing, errors will be ignored. + */ +void VpdErrLog( +SK_AC *pAC, /* common data base */ +SK_IOC IoC, /* IO Context */ +char *msg) /* error log message */ +{ + SK_VPD_PARA *v, vf; /* VF */ + int len; + + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, + ("VPD error log msg %s\n", msg)); + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) { + if (VpdInit(pAC, IoC) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR, + ("VPD init error\n")); + return; + } + } + + len = strlen(msg); + if (len > VPD_MAX_LEN) { + /* cut it */ + len = VPD_MAX_LEN; + } + if ((v = vpd_find_para(pAC, VPD_VF, &vf)) != NULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("overwrite VL\n")); + (void)VpdSetupPara(pAC, VPD_VL, msg, len, VPD_RW_KEY, OWR_KEY); + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("write VF\n")); + (void)VpdSetupPara(pAC, VPD_VF, msg, len, VPD_RW_KEY, ADD_KEY); + } + + (void)VpdUpdate(pAC, IoC); +} + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/skxmac2.c b/drivers/sk98lin/skxmac2.c new file mode 100644 index 000000000..e6b5a95d4 --- /dev/null +++ b/drivers/sk98lin/skxmac2.c @@ -0,0 +1,4396 @@ +/****************************************************************************** + * + * Name: skxmac2.c + * Project: GEnesis, PCI Gigabit Ethernet Adapter + * Version: $Revision: 1.91 $ + * Date: $Date: 2003/02/05 15:09:34 $ + * Purpose: Contains functions to initialize the MACs and PHYs + * + ******************************************************************************/ + +/****************************************************************************** + * + * (C)Copyright 1998-2003 SysKonnect GmbH. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * The information in this file is provided "AS IS" without warranty. + * + ******************************************************************************/ + +/****************************************************************************** + * + * History: + * + * $Log: skxmac2.c,v $ + * Revision 1.91 2003/02/05 15:09:34 rschmidt + * Removed setting of 'Collision Test'-bit in SkGmInitPhyMarv(). + * Disabled auto-update for speed, duplex and flow-control when + * auto-negotiation is not enabled (Bug Id #10766). + * Editorial changes. + * + * Revision 1.90 2003/01/29 13:35:19 rschmidt + * Increment Rx FIFO Overflow counter only in DEBUG-mode. + * Corrected define for blinking active LED. + * + * Revision 1.89 2003/01/28 16:37:45 rschmidt + * Changed init for blinking active LED + * + * Revision 1.88 2003/01/28 10:09:38 rschmidt + * Added debug outputs in SkGmInitMac(). + * Added customized init of LED registers in SkGmInitPhyMarv(), + * for blinking active LED (#ifdef ACT_LED_BLINK) and + * for normal duplex LED (#ifdef DUP_LED_NORMAL). + * Editorial changes. + * + * Revision 1.87 2002/12/10 14:39:05 rschmidt + * Improved initialization of GPHY in SkGmInitPhyMarv(). + * Editorial changes. + * + * Revision 1.86 2002/12/09 15:01:12 rschmidt + * Added setup of Ext. PHY Specific Ctrl Reg (downshift feature). + * + * Revision 1.85 2002/12/05 14:09:16 rschmidt + * Improved avoiding endless loop in SkGmPhyWrite(), SkGmPhyWrite(). + * Added additional advertising for 10Base-T when 100Base-T is selected. + * Added case SK_PHY_MARV_FIBER for YUKON Fiber adapter. + * Editorial changes. + * + * Revision 1.84 2002/11/15 12:50:09 rschmidt + * Changed SkGmCableDiagStatus() when getting results. + * + * Revision 1.83 2002/11/13 10:28:29 rschmidt + * Added some typecasts to avoid compiler warnings. + * + * Revision 1.82 2002/11/13 09:20:46 rschmidt + * Replaced for(..) with do {} while (...) in SkXmUpdateStats(). + * Replaced 2 macros GM_IN16() with 1 GM_IN32() in SkGmMacStatistic(). + * Added SkGmCableDiagStatus() for Virtual Cable Test (VCT). + * Editorial changes. + * + * Revision 1.81 2002/10/28 14:28:08 rschmidt + * Changed MAC address setup for GMAC in SkGmInitMac(). + * Optimized handling of counter overflow IRQ in SkGmOverflowStatus(). + * Editorial changes. + * + * Revision 1.80 2002/10/14 15:29:44 rschmidt + * Corrected disabling of all PHY IRQs. + * Added WA for deviation #16 (address used for pause packets). + * Set Pause Mode in SkMacRxTxEnable() only for Genesis. + * Added IRQ and counter for Receive FIFO Overflow in DEBUG-mode. + * SkXmTimeStamp() replaced by SkMacTimeStamp(). + * Added clearing of GMAC Tx FIFO Underrun IRQ in SkGmIrq(). + * Editorial changes. + * + * Revision 1.79 2002/10/10 15:55:36 mkarl + * changes for PLinkSpeedUsed + * + * Revision 1.78 2002/09/12 09:39:51 rwahl + * Removed deactivate code for SIRQ overflow event separate for TX/RX. + * + * Revision 1.77 2002/09/09 12:26:37 mkarl + * added handling for Yukon to SkXmTimeStamp + * + * Revision 1.76 2002/08/21 16:41:16 rschmidt + * Added bit GPC_ENA_XC (Enable MDI crossover) in HWCFG_MODE. + * Added forced speed settings in SkGmInitPhyMarv(). + * Added settings of full/half duplex capabilities for YUKON Fiber. + * Editorial changes. + * + * Revision 1.75 2002/08/16 15:12:01 rschmidt + * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis. + * Added function SkMacHashing() for ADDR-Module. + * Removed functions SkXmClrSrcCheck(), SkXmClrHashAddr() (calls replaced + * with macros). + * Removed functions SkGmGetMuxConfig(). + * Added HWCFG_MODE init for YUKON Fiber. + * Changed initialization of GPHY in SkGmInitPhyMarv(). + * Changed check of parameter in SkXmMacStatistic(). + * Editorial changes. + * + * Revision 1.74 2002/08/12 14:00:17 rschmidt + * Replaced usage of Broadcom PHY Ids with defines. + * Corrected error messages in SkGmMacStatistic(). + * Made SkMacPromiscMode() public for ADDR-Modul. + * Editorial changes. + * + * Revision 1.73 2002/08/08 16:26:24 rschmidt + * Improved reset sequence for YUKON in SkGmHardRst() and SkGmInitMac(). + * Replaced XMAC Rx High Watermark init value with SK_XM_RX_HI_WM. + * Editorial changes. + * + * Revision 1.72 2002/07/24 15:11:19 rschmidt + * Fixed wrong placement of parenthesis. + * Editorial changes. + * + * Revision 1.71 2002/07/23 16:05:18 rschmidt + * Added global functions for PHY: SkGePhyRead(), SkGePhyWrite(). + * Fixed Tx Counter Overflow IRQ (Bug ID #10730). + * Editorial changes. + * + * Revision 1.70 2002/07/18 14:27:27 rwahl + * Fixed syntax error. + * + * Revision 1.69 2002/07/17 17:08:47 rwahl + * Fixed check in SkXmMacStatistic(). + * + * Revision 1.68 2002/07/16 07:35:24 rwahl + * Removed check for cleared mib counter in SkGmResetCounter(). + * + * Revision 1.67 2002/07/15 18:35:56 rwahl + * Added SkXmUpdateStats(), SkGmUpdateStats(), SkXmMacStatistic(), + * SkGmMacStatistic(), SkXmResetCounter(), SkGmResetCounter(), + * SkXmOverflowStatus(), SkGmOverflowStatus(). + * Changes to SkXmIrq() & SkGmIrq(): Combined SIRQ Overflow for both + * RX & TX. + * Changes to SkGmInitMac(): call to SkGmResetCounter(). + * Editorial changes. + * + * Revision 1.66 2002/07/15 15:59:30 rschmidt + * Added PHY Address in SkXmPhyRead(), SkXmPhyWrite(). + * Added MIB Clear Counter in SkGmInitMac(). + * Added Duplex and Flow-Control settings. + * Reset all Multicast filtering Hash reg. in SkGmInitMac(). + * Added new function: SkGmGetMuxConfig(). + * Editorial changes. + * + * Revision 1.65 2002/06/10 09:35:39 rschmidt + * Replaced C++ comments (//). + * Added #define VCPU around VCPUwaitTime. + * Editorial changes. + * + * Revision 1.64 2002/06/05 08:41:10 rschmidt + * Added function for XMAC2: SkXmTimeStamp(). + * Added function for YUKON: SkGmSetRxCmd(). + * Changed SkGmInitMac() resp. SkGmHardRst(). + * Fixed wrong variable in SkXmAutoNegLipaXmac() (debug mode). + * SkXmRxTxEnable() replaced by SkMacRxTxEnable(). + * Editorial changes. + * + * Revision 1.63 2002/04/25 13:04:44 rschmidt + * Changes for handling YUKON. + * Use of #ifdef OTHER_PHY to eliminate code for unused Phy types. + * Macros for XMAC PHY access PHY_READ(), PHY_WRITE() replaced + * by functions SkXmPhyRead(), SkXmPhyWrite(); + * Removed use of PRxCmd to setup XMAC. + * Added define PHY_B_AS_PAUSE_MSK for BCom Pause Res. + * Added setting of XM_RX_DIS_CEXT in SkXmInitMac(). + * Removed status parameter from MAC IRQ handler SkMacIrq(), + * SkXmIrq() and SkGmIrq(). + * SkXmAutoNegLipa...() for ext. Phy replaced by SkMacAutoNegLipaPhy(). + * Added SkMac...() functions to handle both XMAC and GMAC. + * Added functions for YUKON: SkGmHardRst(), SkGmSoftRst(), + * SkGmSetRxTxEn(), SkGmIrq(), SkGmInitMac(), SkGmInitPhyMarv(), + * SkGmAutoNegDoneMarv(), SkGmPhyRead(), SkGmPhyWrite(). + * Changes for V-CPU support. + * Editorial changes. + * + * Revision 1.62 2001/08/06 09:50:14 rschmidt + * Workaround BCOM Errata #1 for the C5 type. + * Editorial changes. + * + * Revision 1.61 2001/02/09 15:40:59 rassmann + * Editorial changes. + * + * Revision 1.60 2001/02/07 15:02:01 cgoos + * Added workaround for Fujitsu switch link down. + * + * Revision 1.59 2001/01/10 09:38:06 cgoos + * Fixed Broadcom C0/A1 Id check for workaround. + * + * Revision 1.58 2000/11/29 11:30:38 cgoos + * Changed DEBUG sections with NW output to xDEBUG + * + * Revision 1.57 2000/11/27 12:40:40 rassmann + * Suppressing preamble after first access to BCom, not before (#10556). + * + * Revision 1.56 2000/11/09 12:32:48 rassmann + * Renamed variables. + * + * Revision 1.55 2000/11/09 11:30:10 rassmann + * WA: Waiting after releasing reset until BCom chip is accessible. + * + * Revision 1.54 2000/10/02 14:10:27 rassmann + * Reading BCOM PHY after releasing reset until it returns a valid value. + * + * Revision 1.53 2000/07/27 12:22:11 gklug + * fix: possible endless loop in XmHardRst. + * + * Revision 1.52 2000/05/22 08:48:31 malthoff + * Fix: #10523 errata valid for all BCOM PHYs. + * + * Revision 1.51 2000/05/17 12:52:18 malthoff + * Fixes BCom link errata (#10523). + * + * Revision 1.50 1999/11/22 13:40:14 cgoos + * Changed license header to GPL. + * + * Revision 1.49 1999/11/22 08:12:13 malthoff + * Add workaround for power consumption feature of BCom C0 chip. + * + * Revision 1.48 1999/11/16 08:39:01 malthoff + * Fix: MDIO preamble suppression is port dependent. + * + * Revision 1.47 1999/08/27 08:55:35 malthoff + * 1000BT: Optimizing MDIO transfer by oppressing MDIO preamble. + * + * Revision 1.46 1999/08/13 11:01:12 malthoff + * Fix for 1000BT: pFlowCtrlMode was not set correctly. + * + * Revision 1.45 1999/08/12 19:18:28 malthoff + * 1000BT Fixes: Do not owerwrite XM_MMU_CMD. + * Do not execute BCOM A1 workaround for B1 chips. + * Fix pause frame setting. + * Always set PHY_B_AC_TX_TST in PHY_BCOM_AUX_CTRL. + * + * Revision 1.44 1999/08/03 15:23:48 cgoos + * Fixed setting of PHY interrupt mask in half duplex mode. + * + * Revision 1.43 1999/08/03 15:22:17 cgoos + * Added some debug output. + * Disabled XMac GP0 interrupt for external PHYs. + * + * Revision 1.42 1999/08/02 08:39:23 malthoff + * BCOM PHY: TX LED: To get the mono flop behaviour it is required + * to set the LED Traffic Mode bit in PHY_BCOM_P_EXT_CTRL. + * + * Revision 1.41 1999/07/30 06:54:31 malthoff + * Add temp. workarounds for the BCOM Phy revision A1. + * + * Revision 1.40 1999/06/01 07:43:26 cgoos + * Changed Link Mode Status in SkXmAutoNegDone... from FULL/HALF to + * AUTOFULL/AUTOHALF. + * + * Revision 1.39 1999/05/19 07:29:51 cgoos + * Changes for 1000Base-T. + * + * Revision 1.38 1999/04/08 14:35:10 malthoff + * Add code for enabling signal detect. Enabling signal detect is disabled. + * + * Revision 1.37 1999/03/12 13:42:54 malthoff + * Add: Jumbo Frame Support. + * Add: Receive modes SK_LENERR_OK_ON/OFF and + * SK_BIG_PK_OK_ON/OFF in SkXmSetRxCmd(). + * + * Revision 1.36 1999/03/08 10:10:55 gklug + * fix: AutoSensing did switch to next mode even if LiPa indicated offline + * + * Revision 1.35 1999/02/22 15:16:41 malthoff + * Remove some compiler warnings. + * + * Revision 1.34 1999/01/22 09:19:59 gklug + * fix: Init DupMode and InitPauseMd are now called in RxTxEnable + * + * Revision 1.33 1998/12/11 15:19:11 gklug + * chg: lipa autoneg stati + * chg: debug messages + * chg: do NOT use spurious XmIrq + * + * Revision 1.32 1998/12/10 11:08:44 malthoff + * bug fix: pAC has been used for IOs in SkXmHardRst(). + * SkXmInitPhy() is also called for the Diag in SkXmInitMac(). + * + * Revision 1.31 1998/12/10 10:39:11 gklug + * fix: do 4 RESETS of the XMAC at the beginning + * fix: dummy read interrupt source register BEFORE initializing the Phy + * add: debug messages + * fix: Linkpartners autoneg capability cannot be shown by TX_PAGE interrupt + * + * Revision 1.30 1998/12/07 12:18:32 gklug + * add: refinement of autosense mode: take into account the autoneg cap of LiPa + * + * Revision 1.29 1998/12/07 07:12:29 gklug + * fix: if page is received the link is down. + * + * Revision 1.28 1998/12/01 10:12:47 gklug + * chg: if spurious IRQ from XMAC encountered, save it + * + * Revision 1.27 1998/11/26 07:33:38 gklug + * add: InitPhy call is now in XmInit function + * + * Revision 1.26 1998/11/18 13:38:24 malthoff + * 'Imsk' is also unused in SkXmAutoNegDone. + * + * Revision 1.25 1998/11/18 13:28:01 malthoff + * Remove unused variable 'Reg' in SkXmAutoNegDone(). + * + * Revision 1.24 1998/11/18 13:18:45 gklug + * add: workaround for xmac errata #1 + * add: detect Link Down also when Link partner requested config + * chg: XMIrq is only used when link is up + * + * Revision 1.23 1998/11/04 07:07:04 cgoos + * Added function SkXmRxTxEnable. + * + * Revision 1.22 1998/10/30 07:35:54 gklug + * fix: serve LinkDown interrupt when link is already down + * + * Revision 1.21 1998/10/29 15:32:03 gklug + * fix: Link Down signaling + * + * Revision 1.20 1998/10/29 11:17:27 gklug + * fix: AutoNegDone bug + * + * Revision 1.19 1998/10/29 10:14:43 malthoff + * Add endainesss comment for reading/writing MAC addresses. + * + * Revision 1.18 1998/10/28 07:48:55 cgoos + * Fix: ASS somtimes signaled although link is up. + * + * Revision 1.17 1998/10/26 07:55:39 malthoff + * Fix in SkXmInitPauseMd(): Pause Mode + * was disabled and not enabled. + * Fix in SkXmAutoNegDone(): Checking Mode bits + * always failed, becaues of some missing braces. + * + * Revision 1.16 1998/10/22 09:46:52 gklug + * fix SysKonnectFileId typo + * + * Revision 1.15 1998/10/21 05:51:37 gklug + * add: para DoLoop to InitPhy function for loopback set-up + * + * Revision 1.14 1998/10/16 10:59:23 malthoff + * Remove Lint warning for dummy reads. + * + * Revision 1.13 1998/10/15 14:01:20 malthoff + * Fix: SkXmAutoNegDone() is (int) but does not return a value. + * + * Revision 1.12 1998/10/14 14:45:04 malthoff + * Remove SKERR_SIRQ_E0xx and SKERR_SIRQ_E0xxMSG by + * SKERR_HWI_Exx and SKERR_HWI_E0xxMSG to be independent + * from the Sirq module. + * + * Revision 1.11 1998/10/14 13:59:01 gklug + * add: InitPhy function + * + * Revision 1.10 1998/10/14 11:20:57 malthoff + * Make SkXmAutoNegDone() public, because it's + * used in diagnostics, too. + * The Link Up event to the RLMT is issued in SkXmIrq(). + * SkXmIrq() is not available in diagnostics. + * Use PHY_READ when reading PHY registers. + * + * Revision 1.9 1998/10/14 05:50:10 cgoos + * Added definition for Para. + * + * Revision 1.8 1998/10/14 05:41:28 gklug + * add: Xmac IRQ + * add: auto-negotiation done function + * + * Revision 1.7 1998/10/09 06:55:20 malthoff + * The configuration of the XMACs Tx Request Threshold + * depends from the drivers port usage now. The port + * usage is configured in GIPortUsage. + * + * Revision 1.6 1998/10/05 07:48:00 malthoff + * minor changes + * + * Revision 1.5 1998/10/01 07:03:54 gklug + * add: dummy function for XMAC ISR + * + * Revision 1.4 1998/09/30 12:37:44 malthoff + * Add SkXmSetRxCmd() and related code. + * + * Revision 1.3 1998/09/28 13:26:40 malthoff + * Add SkXmInitMac(), SkXmInitDupMd(), and SkXmInitPauseMd() + * + * Revision 1.2 1998/09/16 14:34:21 malthoff + * Add SkXmClrExactAddr(), SkXmClrSrcCheck(), + * SkXmClrHashAddr(), SkXmFlushTxFifo(), + * SkXmFlushRxFifo(), and SkXmHardRst(). + * Finish Coding of SkXmSoftRst(). + * The sources may be compiled now. + * + * Revision 1.1 1998/09/04 10:05:56 malthoff + * Created. + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_SK98 + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" + +/* typedefs *******************************************************************/ + +/* BCOM PHY magic pattern list */ +typedef struct s_PhyHack { + int PhyReg; /* Phy register */ + SK_U16 PhyVal; /* Value to write */ +} BCOM_HACK; + +/* local variables ************************************************************/ +static const char SysKonnectFileId[] = + "@(#)$Id: skxmac2.c,v 1.91 2003/02/05 15:09:34 rschmidt Exp $ (C) SK "; + +BCOM_HACK BcomRegA1Hack[] = { + { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 }, + { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 }, + { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, + { 0, 0 } +}; +BCOM_HACK BcomRegC0Hack[] = { + { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, { 0x17, 0x0013 }, + { 0x15, 0x0A04 }, { 0x18, 0x0420 }, + { 0, 0 } +}; + +/* function prototypes ********************************************************/ +static void SkXmInitPhyXmac(SK_AC*, SK_IOC, int, SK_BOOL); +static void SkXmInitPhyBcom(SK_AC*, SK_IOC, int, SK_BOOL); +static void SkGmInitPhyMarv(SK_AC*, SK_IOC, int, SK_BOOL); +static int SkXmAutoNegDoneXmac(SK_AC*, SK_IOC, int); +static int SkXmAutoNegDoneBcom(SK_AC*, SK_IOC, int); +static int SkGmAutoNegDoneMarv(SK_AC*, SK_IOC, int); +#ifdef OTHER_PHY +static void SkXmInitPhyLone(SK_AC*, SK_IOC, int, SK_BOOL); +static void SkXmInitPhyNat (SK_AC*, SK_IOC, int, SK_BOOL); +static int SkXmAutoNegDoneLone(SK_AC*, SK_IOC, int); +static int SkXmAutoNegDoneNat (SK_AC*, SK_IOC, int); +#endif /* OTHER_PHY */ + + +/****************************************************************************** + * + * SkXmPhyRead() - Read from XMAC PHY register + * + * Description: reads a 16-bit word from XMAC PHY or ext. PHY + * + * Returns: + * nothing + */ +void SkXmPhyRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 *pVal) /* Pointer to Value */ +{ + SK_U16 Mmu; + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + /* write the PHY register's address */ + XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr); + + /* get the PHY register's value */ + XM_IN16(IoC, Port, XM_PHY_DATA, pVal); + + if (pPrt->PhyType != SK_PHY_XMAC) { + do { + XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu); + /* wait until 'Ready' is set */ + } while ((Mmu & XM_MMU_PHY_RDY) == 0); + + /* get the PHY register's value */ + XM_IN16(IoC, Port, XM_PHY_DATA, pVal); + } +} /* SkXmPhyRead */ + + +/****************************************************************************** + * + * SkXmPhyWrite() - Write to XMAC PHY register + * + * Description: writes a 16-bit word to XMAC PHY or ext. PHY + * + * Returns: + * nothing + */ +void SkXmPhyWrite( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 Val) /* Value */ +{ + SK_U16 Mmu; + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PhyType != SK_PHY_XMAC) { + do { + XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu); + /* wait until 'Busy' is cleared */ + } while ((Mmu & XM_MMU_PHY_BUSY) != 0); + } + + /* write the PHY register's address */ + XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr); + + /* write the PHY register's value */ + XM_OUT16(IoC, Port, XM_PHY_DATA, Val); + + if (pPrt->PhyType != SK_PHY_XMAC) { + do { + XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu); + /* wait until 'Busy' is cleared */ + } while ((Mmu & XM_MMU_PHY_BUSY) != 0); + } +} /* SkXmPhyWrite */ + + +/****************************************************************************** + * + * SkGmPhyRead() - Read from GPHY register + * + * Description: reads a 16-bit word from GPHY through MDIO + * + * Returns: + * nothing + */ +void SkGmPhyRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 *pVal) /* Pointer to Value */ +{ + SK_U16 Ctrl; + SK_GEPORT *pPrt; +#ifdef VCPU + u_long SimCyle; + u_long SimLowTime; + + VCPUgetTime(&SimCyle, &SimLowTime); + VCPUprintf(0, "SkGmPhyRead(%u), SimCyle=%u, SimLowTime=%u\n", + PhyReg, SimCyle, SimLowTime); +#endif /* VCPU */ + + pPrt = &pAC->GIni.GP[Port]; + + /* set PHY-Register offset and 'Read' OpCode (= 1) */ + *pVal = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | + GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD); + + GM_OUT16(IoC, Port, GM_SMI_CTRL, *pVal); + + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); + + /* additional check for MDC/MDIO activity */ + if ((Ctrl & GM_SMI_CT_BUSY) == 0) { + *pVal = 0; + return; + } + + *pVal |= GM_SMI_CT_BUSY; + + do { +#ifdef VCPU + VCPUwaitTime(1000); +#endif /* VCPU */ + + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); + + /* wait until 'ReadValid' is set */ + } while (Ctrl == *pVal); + + /* get the PHY register's value */ + GM_IN16(IoC, Port, GM_SMI_DATA, pVal); + +#ifdef VCPU + VCPUgetTime(&SimCyle, &SimLowTime); + VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n", + SimCyle, SimLowTime); +#endif /* VCPU */ +} /* SkGmPhyRead */ + + +/****************************************************************************** + * + * SkGmPhyWrite() - Write to GPHY register + * + * Description: writes a 16-bit word to GPHY through MDIO + * + * Returns: + * nothing + */ +void SkGmPhyWrite( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 Val) /* Value */ +{ + SK_U16 Ctrl; + SK_GEPORT *pPrt; +#ifdef VCPU + SK_U32 DWord; + u_long SimCyle; + u_long SimLowTime; + + VCPUgetTime(&SimCyle, &SimLowTime); + VCPUprintf(0, "SkGmPhyWrite(Reg=%u, Val=0x%04x), SimCyle=%u, SimLowTime=%u\n", + PhyReg, Val, SimCyle, SimLowTime); +#endif /* VCPU */ + + pPrt = &pAC->GIni.GP[Port]; + + /* write the PHY register's value */ + GM_OUT16(IoC, Port, GM_SMI_DATA, Val); + + /* set PHY-Register offset and 'Write' OpCode (= 0) */ + Val = GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg); + + GM_OUT16(IoC, Port, GM_SMI_CTRL, Val); + + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); + + /* additional check for MDC/MDIO activity */ + if ((Ctrl & GM_SMI_CT_BUSY) == 0) { + return; + } + + Val |= GM_SMI_CT_BUSY; + + do { +#ifdef VCPU + /* read Timer value */ + SK_IN32(IoC, B2_TI_VAL, &DWord); + + VCPUwaitTime(1000); +#endif /* VCPU */ + + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl); + + /* wait until 'Busy' is cleared */ + } while (Ctrl == Val); + +#ifdef VCPU + VCPUgetTime(&SimCyle, &SimLowTime); + VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n", + SimCyle, SimLowTime); +#endif /* VCPU */ +} /* SkGmPhyWrite */ + + +/****************************************************************************** + * + * SkGePhyRead() - Read from PHY register + * + * Description: calls a read PHY routine dep. on board type + * + * Returns: + * nothing + */ +void SkGePhyRead( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 *pVal) /* Pointer to Value */ +{ + void (*r_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 *pVal); + + if (pAC->GIni.GIGenesis) { + r_func = SkXmPhyRead; + } + else { + r_func = SkGmPhyRead; + } + + r_func(pAC, IoC, Port, PhyReg, pVal); +} /* SkGePhyRead */ + + +/****************************************************************************** + * + * SkGePhyWrite() - Write to PHY register + * + * Description: calls a write PHY routine dep. on board type + * + * Returns: + * nothing + */ +void SkGePhyWrite( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* I/O Context */ +int Port, /* Port Index (MAC_1 + n) */ +int PhyReg, /* Register Address (Offset) */ +SK_U16 Val) /* Value */ +{ + void (*w_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 Val); + + if (pAC->GIni.GIGenesis) { + w_func = SkXmPhyWrite; + } + else { + w_func = SkGmPhyWrite; + } + + w_func(pAC, IoC, Port, PhyReg, Val); +} /* SkGePhyWrite */ + + +/****************************************************************************** + * + * SkMacPromiscMode() - Enable / Disable Promiscuous Mode + * + * Description: + * enables / disables promiscuous mode by setting Mode Register (XMAC) or + * Receive Control Register (GMAC) dep. on board type + * + * Returns: + * nothing + */ +void SkMacPromiscMode( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL Enable) /* Enable / Disable */ +{ + SK_U16 RcReg; + SK_U32 MdReg; + + if (pAC->GIni.GIGenesis) { + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + /* enable or disable promiscuous mode */ + if (Enable) { + MdReg |= XM_MD_ENA_PROM; + } + else { + MdReg &= ~XM_MD_ENA_PROM; + } + /* setup Mode Register */ + XM_OUT32(IoC, Port, XM_MODE, MdReg); + } + else { + + GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg); + + /* enable or disable unicast and multicast filtering */ + if (Enable) { + RcReg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); + } + else { + RcReg |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); + } + /* setup Receive Control Register */ + GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg); + } +} /* SkMacPromiscMode*/ + + +/****************************************************************************** + * + * SkMacHashing() - Enable / Disable Hashing + * + * Description: + * enables / disables hashing by setting Mode Register (XMAC) or + * Receive Control Register (GMAC) dep. on board type + * + * Returns: + * nothing + */ +void SkMacHashing( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL Enable) /* Enable / Disable */ +{ + SK_U16 RcReg; + SK_U32 MdReg; + + if (pAC->GIni.GIGenesis) { + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + /* enable or disable hashing */ + if (Enable) { + MdReg |= XM_MD_ENA_HASH; + } + else { + MdReg &= ~XM_MD_ENA_HASH; + } + /* setup Mode Register */ + XM_OUT32(IoC, Port, XM_MODE, MdReg); + } + else { + + GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg); + + /* enable or disable multicast filtering */ + if (Enable) { + RcReg |= GM_RXCR_MCF_ENA; + } + else { + RcReg &= ~GM_RXCR_MCF_ENA; + } + /* setup Receive Control Register */ + GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg); + } +} /* SkMacHashing*/ + + +#ifdef SK_DIAG +/****************************************************************************** + * + * SkXmSetRxCmd() - Modify the value of the XMAC's Rx Command Register + * + * Description: + * The features + * - FCS stripping, SK_STRIP_FCS_ON/OFF + * - pad byte stripping, SK_STRIP_PAD_ON/OFF + * - don't set XMR_FS_ERR in status SK_LENERR_OK_ON/OFF + * for inrange length error frames + * - don't set XMR_FS_ERR in status SK_BIG_PK_OK_ON/OFF + * for frames > 1514 bytes + * - enable Rx of own packets SK_SELF_RX_ON/OFF + * + * for incoming packets may be enabled/disabled by this function. + * Additional modes may be added later. + * Multiple modes can be enabled/disabled at the same time. + * The new configuration is written to the Rx Command register immediately. + * + * Returns: + * nothing + */ +static void SkXmSetRxCmd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, + SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */ +{ + SK_U16 OldRxCmd; + SK_U16 RxCmd; + + XM_IN16(IoC, Port, XM_RX_CMD, &OldRxCmd); + + RxCmd = OldRxCmd; + + switch (Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) { + case SK_STRIP_FCS_ON: + RxCmd |= XM_RX_STRIP_FCS; + break; + case SK_STRIP_FCS_OFF: + RxCmd &= ~XM_RX_STRIP_FCS; + break; + } + + switch (Mode & (SK_STRIP_PAD_ON | SK_STRIP_PAD_OFF)) { + case SK_STRIP_PAD_ON: + RxCmd |= XM_RX_STRIP_PAD; + break; + case SK_STRIP_PAD_OFF: + RxCmd &= ~XM_RX_STRIP_PAD; + break; + } + + switch (Mode & (SK_LENERR_OK_ON | SK_LENERR_OK_OFF)) { + case SK_LENERR_OK_ON: + RxCmd |= XM_RX_LENERR_OK; + break; + case SK_LENERR_OK_OFF: + RxCmd &= ~XM_RX_LENERR_OK; + break; + } + + switch (Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) { + case SK_BIG_PK_OK_ON: + RxCmd |= XM_RX_BIG_PK_OK; + break; + case SK_BIG_PK_OK_OFF: + RxCmd &= ~XM_RX_BIG_PK_OK; + break; + } + + switch (Mode & (SK_SELF_RX_ON | SK_SELF_RX_OFF)) { + case SK_SELF_RX_ON: + RxCmd |= XM_RX_SELF_RX; + break; + case SK_SELF_RX_OFF: + RxCmd &= ~XM_RX_SELF_RX; + break; + } + + /* Write the new mode to the Rx command register if required */ + if (OldRxCmd != RxCmd) { + XM_OUT16(IoC, Port, XM_RX_CMD, RxCmd); + } +} /* SkXmSetRxCmd */ + + +/****************************************************************************** + * + * SkGmSetRxCmd() - Modify the value of the GMAC's Rx Control Register + * + * Description: + * The features + * - FCS (CRC) stripping, SK_STRIP_FCS_ON/OFF + * - don't set GMR_FS_LONG_ERR SK_BIG_PK_OK_ON/OFF + * for frames > 1514 bytes + * - enable Rx of own packets SK_SELF_RX_ON/OFF + * + * for incoming packets may be enabled/disabled by this function. + * Additional modes may be added later. + * Multiple modes can be enabled/disabled at the same time. + * The new configuration is written to the Rx Command register immediately. + * + * Returns: + * nothing + */ +static void SkGmSetRxCmd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF, + SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */ +{ + SK_U16 OldRxCmd; + SK_U16 RxCmd; + + if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) { + + GM_IN16(IoC, Port, GM_RX_CTRL, &OldRxCmd); + + RxCmd = OldRxCmd; + + if ((Mode & SK_STRIP_FCS_ON) != 0) { + RxCmd |= GM_RXCR_CRC_DIS; + } + else { + RxCmd &= ~GM_RXCR_CRC_DIS; + } + /* Write the new mode to the Rx control register if required */ + if (OldRxCmd != RxCmd) { + GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd); + } + } + + if ((Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) != 0) { + + GM_IN16(IoC, Port, GM_SERIAL_MODE, &OldRxCmd); + + RxCmd = OldRxCmd; + + if ((Mode & SK_BIG_PK_OK_ON) != 0) { + RxCmd |= GM_SMOD_JUMBO_ENA; + } + else { + RxCmd &= ~GM_SMOD_JUMBO_ENA; + } + /* Write the new mode to the Rx control register if required */ + if (OldRxCmd != RxCmd) { + GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd); + } + } +} /* SkGmSetRxCmd */ + + +/****************************************************************************** + * + * SkMacSetRxCmd() - Modify the value of the MAC's Rx Control Register + * + * Description: modifies the MAC's Rx Control reg. dep. on board type + * + * Returns: + * nothing + */ +void SkMacSetRxCmd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Mode) /* Rx Mode */ +{ + if (pAC->GIni.GIGenesis) { + + SkXmSetRxCmd(pAC, IoC, Port, Mode); + } + else { + + SkGmSetRxCmd(pAC, IoC, Port, Mode); + } +} /* SkMacSetRxCmd */ + + +/****************************************************************************** + * + * SkMacCrcGener() - Enable / Disable CRC Generation + * + * Description: enables / disables CRC generation dep. on board type + * + * Returns: + * nothing + */ +void SkMacCrcGener( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL Enable) /* Enable / Disable */ +{ + SK_U16 Word; + + if (pAC->GIni.GIGenesis) { + + XM_IN16(IoC, Port, XM_TX_CMD, &Word); + + if (Enable) { + Word &= ~XM_TX_NO_CRC; + } + else { + Word |= XM_TX_NO_CRC; + } + /* setup Tx Command Register */ + XM_OUT16(pAC, Port, XM_TX_CMD, Word); + } + else { + + GM_IN16(IoC, Port, GM_TX_CTRL, &Word); + + if (Enable) { + Word &= ~GM_TXCR_CRC_DIS; + } + else { + Word |= GM_TXCR_CRC_DIS; + } + /* setup Tx Control Register */ + GM_OUT16(IoC, Port, GM_TX_CTRL, Word); + } +} /* SkMacCrcGener*/ + +#endif /* SK_DIAG */ + + +/****************************************************************************** + * + * SkXmClrExactAddr() - Clear Exact Match Address Registers + * + * Description: + * All Exact Match Address registers of the XMAC 'Port' will be + * cleared starting with 'StartNum' up to (and including) the + * Exact Match address number of 'StopNum'. + * + * Returns: + * nothing + */ +void SkXmClrExactAddr( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int StartNum, /* Begin with this Address Register Index (0..15) */ +int StopNum) /* Stop after finished with this Register Idx (0..15) */ +{ + int i; + SK_U16 ZeroAddr[3] = {0x0000, 0x0000, 0x0000}; + + if ((unsigned)StartNum > 15 || (unsigned)StopNum > 15 || + StartNum > StopNum) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E001, SKERR_HWI_E001MSG); + return; + } + + for (i = StartNum; i <= StopNum; i++) { + XM_OUTADDR(IoC, Port, XM_EXM(i), &ZeroAddr[0]); + } +} /* SkXmClrExactAddr */ + + +/****************************************************************************** + * + * SkMacFlushTxFifo() - Flush the MAC's transmit FIFO + * + * Description: + * Flush the transmit FIFO of the MAC specified by the index 'Port' + * + * Returns: + * nothing + */ +void SkMacFlushTxFifo( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U32 MdReg; + + if (pAC->GIni.GIGenesis) { + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + + XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FTF); + } + else { + /* no way to flush the FIFO we have to issue a reset */ + /* TBD */ + } +} /* SkMacFlushTxFifo */ + + +/****************************************************************************** + * + * SkMacFlushRxFifo() - Flush the MAC's receive FIFO + * + * Description: + * Flush the receive FIFO of the MAC specified by the index 'Port' + * + * Returns: + * nothing + */ +void SkMacFlushRxFifo( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U32 MdReg; + + if (pAC->GIni.GIGenesis) { + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + + XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FRF); + } + else { + /* no way to flush the FIFO we have to issue a reset */ + /* TBD */ + } +} /* SkMacFlushRxFifo */ + + +/****************************************************************************** + * + * SkXmSoftRst() - Do a XMAC software reset + * + * Description: + * The PHY registers should not be destroyed during this + * kind of software reset. Therefore the XMAC Software Reset + * (XM_GP_RES_MAC bit in XM_GP_PORT) must not be used! + * + * The software reset is done by + * - disabling the Rx and Tx state machine, + * - resetting the statistics module, + * - clear all other significant XMAC Mode, + * Command, and Control Registers + * - clearing the Hash Register and the + * Exact Match Address registers, and + * - flushing the XMAC's Rx and Tx FIFOs. + * + * Note: + * Another requirement when stopping the XMAC is to + * avoid sending corrupted frames on the network. + * Disabling the Tx state machine will NOT interrupt + * the currently transmitted frame. But we must take care + * that the Tx FIFO is cleared AFTER the current frame + * is complete sent to the network. + * + * It takes about 12ns to send a frame with 1538 bytes. + * One PCI clock goes at least 15ns (66MHz). Therefore + * after reading XM_GP_PORT back, we are sure that the + * transmitter is disabled AND idle. And this means + * we may flush the transmit FIFO now. + * + * Returns: + * nothing + */ +static void SkXmSoftRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 ZeroAddr[4] = {0x0000, 0x0000, 0x0000, 0x0000}; + + /* reset the statistics module */ + XM_OUT32(IoC, Port, XM_GP_PORT, XM_GP_RES_STAT); + + /* disable all XMAC IRQs */ + XM_OUT16(IoC, Port, XM_IMSK, 0xffff); + + XM_OUT32(IoC, Port, XM_MODE, 0); /* clear Mode Reg */ + + XM_OUT16(IoC, Port, XM_TX_CMD, 0); /* reset TX CMD Reg */ + XM_OUT16(IoC, Port, XM_RX_CMD, 0); /* reset RX CMD Reg */ + + /* disable all PHY IRQs */ + switch (pAC->GIni.GP[Port].PhyType) { + case SK_PHY_BCOM: + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, 0xffff); + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_INT_ENAB, 0); + break; + case SK_PHY_NAT: + /* todo: National + SkXmPhyWrite(pAC, IoC, Port, PHY_NAT_INT_MASK, 0xffff); */ + break; +#endif /* OTHER_PHY */ + } + + /* clear the Hash Register */ + XM_OUTHASH(IoC, Port, XM_HSM, &ZeroAddr); + + /* clear the Exact Match Address registers */ + SkXmClrExactAddr(pAC, IoC, Port, 0, 15); + + /* clear the Source Check Address registers */ + XM_OUTHASH(IoC, Port, XM_SRC_CHK, &ZeroAddr); + +} /* SkXmSoftRst */ + + +/****************************************************************************** + * + * SkXmHardRst() - Do a XMAC hardware reset + * + * Description: + * The XMAC of the specified 'Port' and all connected devices + * (PHY and SERDES) will receive a reset signal on its *Reset pins. + * External PHYs must be reset be clearing a bit in the GPIO register + * (Timing requirements: Broadcom: 400ns, Level One: none, National: 80ns). + * + * ATTENTION: + * It is absolutely necessary to reset the SW_RST Bit first + * before calling this function. + * + * Returns: + * nothing + */ +static void SkXmHardRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U32 Reg; + int i; + int TOut; + SK_U16 Word; + + for (i = 0; i < 4; i++) { + /* TX_MFF_CTRL1 has 32 bits, but only the lowest 16 bits are used */ + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); + + TOut = 0; + do { + if (TOut++ > 10000) { + /* + * Adapter seems to be in RESET state. + * Registers cannot be written. + */ + return; + } + + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_SET_MAC_RST); + + SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &Word); + + } while ((Word & MFF_SET_MAC_RST) == 0); + } + + /* For external PHYs there must be special handling */ + if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) { + /* reset external PHY */ + SK_IN32(IoC, B2_GP_IO, &Reg); + if (Port == 0) { + Reg |= GP_DIR_0; /* set to output */ + Reg &= ~GP_IO_0; + } + else { + Reg |= GP_DIR_2; /* set to output */ + Reg &= ~GP_IO_2; + } + SK_OUT32(IoC, B2_GP_IO, Reg); + + /* short delay */ + SK_IN32(IoC, B2_GP_IO, &Reg); + } + +} /* SkXmHardRst */ + + +/****************************************************************************** + * + * SkGmSoftRst() - Do a GMAC software reset + * + * Description: + * The GPHY registers should not be destroyed during this + * kind of software reset. + * + * Returns: + * nothing + */ +static void SkGmSoftRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 EmptyHash[4] = {0x0000, 0x0000, 0x0000, 0x0000}; + SK_U16 RxCtrl; + + /* reset the statistics module */ + + /* disable all GMAC IRQs */ + SK_OUT8(IoC, GMAC_IRQ_MSK, 0); + + /* disable all PHY IRQs */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0); + + /* clear the Hash Register */ + GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash); + + /* Enable Unicast and Multicast filtering */ + GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl); + + GM_OUT16(IoC, Port, GM_RX_CTRL, + RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); + +} /* SkGmSoftRst */ + + +/****************************************************************************** + * + * SkGmHardRst() - Do a GMAC hardware reset + * + * Description: + * + * ATTENTION: + * It is absolutely necessary to reset the SW_RST Bit first + * before calling this function. + * + * Returns: + * nothing + */ +static void SkGmHardRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + /* set GPHY Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET); + + /* set GMAC Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET); + +} /* SkGmHardRst */ + + +/****************************************************************************** + * + * SkMacSoftRst() - Do a MAC software reset + * + * Description: calls a MAC software reset routine dep. on board type + * + * Returns: + * nothing + */ +void SkMacSoftRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + /* disable receiver and transmitter */ + SkMacRxTxDisable(pAC, IoC, Port); + + if (pAC->GIni.GIGenesis) { + + SkXmSoftRst(pAC, IoC, Port); + } + else { + + SkGmSoftRst(pAC, IoC, Port); + } + + /* flush the MAC's Rx and Tx FIFOs */ + SkMacFlushTxFifo(pAC, IoC, Port); + + SkMacFlushRxFifo(pAC, IoC, Port); + + pPrt->PState = SK_PRT_STOP; + +} /* SkMacSoftRst */ + + +/****************************************************************************** + * + * SkMacHardRst() - Do a MAC hardware reset + * + * Description: calls a MAC hardware reset routine dep. on board type + * + * Returns: + * nothing + */ +void SkMacHardRst( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + + if (pAC->GIni.GIGenesis) { + + SkXmHardRst(pAC, IoC, Port); + } + else { + + SkGmHardRst(pAC, IoC, Port); + } + + pAC->GIni.GP[Port].PState = SK_PRT_RESET; + +} /* SkMacHardRst */ + + +/****************************************************************************** + * + * SkXmInitMac() - Initialize the XMAC II + * + * Description: + * Initialize the XMAC of the specified port. + * The XMAC must be reset or stopped before calling this function. + * + * Note: + * The XMAC's Rx and Tx state machine is still disabled when returning. + * + * Returns: + * nothing + */ +void SkXmInitMac( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U32 Reg; + int i; + SK_U16 SWord; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PState == SK_PRT_STOP) { + /* Port State: SK_PRT_STOP */ + /* Verify that the reset bit is cleared */ + SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord); + + if ((SWord & MFF_SET_MAC_RST) != 0) { + /* PState does not match HW state */ + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG); + /* Correct it */ + pPrt->PState = SK_PRT_RESET; + } + } + + if (pPrt->PState == SK_PRT_RESET) { + /* + * clear HW reset + * Note: The SW reset is self clearing, therefore there is + * nothing to do here. + */ + SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); + + /* Ensure that XMAC reset release is done (errata from LReinbold?) */ + SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord); + + /* Clear PHY reset */ + if (pPrt->PhyType != SK_PHY_XMAC) { + + SK_IN32(IoC, B2_GP_IO, &Reg); + + if (Port == 0) { + Reg |= (GP_DIR_0 | GP_IO_0); /* set to output */ + } + else { + Reg |= (GP_DIR_2 | GP_IO_2); /* set to output */ + } + SK_OUT32(IoC, B2_GP_IO, Reg); + + /* Enable GMII interface */ + XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_GMII_MD); + + /* read Id from external PHY (all have the same address) */ + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_ID1, &pPrt->PhyId1); + + /* + * Optimize MDIO transfer by suppressing preamble. + * Must be done AFTER first access to BCOM chip. + */ + XM_IN16(IoC, Port, XM_MMU_CMD, &SWord); + + XM_OUT16(IoC, Port, XM_MMU_CMD, SWord | XM_MMU_NO_PRE); + + if (pPrt->PhyId1 == PHY_BCOM_ID1_C0) { + /* + * Workaround BCOM Errata for the C0 type. + * Write magic patterns to reserved registers. + */ + i = 0; + while (BcomRegC0Hack[i].PhyReg != 0) { + SkXmPhyWrite(pAC, IoC, Port, BcomRegC0Hack[i].PhyReg, + BcomRegC0Hack[i].PhyVal); + i++; + } + } + else if (pPrt->PhyId1 == PHY_BCOM_ID1_A1) { + /* + * Workaround BCOM Errata for the A1 type. + * Write magic patterns to reserved registers. + */ + i = 0; + while (BcomRegA1Hack[i].PhyReg != 0) { + SkXmPhyWrite(pAC, IoC, Port, BcomRegA1Hack[i].PhyReg, + BcomRegA1Hack[i].PhyVal); + i++; + } + } + + /* + * Workaround BCOM Errata (#10523) for all BCom PHYs. + * Disable Power Management after reset. + */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord); + + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, + (SK_U16)(SWord | PHY_B_AC_DIS_PM)); + + /* PHY LED initialization is done in SkGeXmitLED() */ + } + + /* Dummy read the Interrupt source register */ + XM_IN16(IoC, Port, XM_ISRC, &SWord); + + /* + * The auto-negotiation process starts immediately after + * clearing the reset. The auto-negotiation process should be + * started by the SIRQ, therefore stop it here immediately. + */ + SkMacInitPhy(pAC, IoC, Port, SK_FALSE); + +#if 0 + /* temp. code: enable signal detect */ + /* WARNING: do not override GMII setting above */ + XM_OUT16(pAC, Port, XM_HW_CFG, XM_HW_COM4SIG); +#endif + } + + /* + * configure the XMACs Station Address + * B2_MAC_2 = xx xx xx xx xx x1 is programmed to XMAC A + * B2_MAC_3 = xx xx xx xx xx x2 is programmed to XMAC B + */ + for (i = 0; i < 3; i++) { + /* + * The following 2 statements are together endianess + * independent. Remember this when changing. + */ + SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord); + + XM_OUT16(IoC, Port, (XM_SA + i * 2), SWord); + } + + /* Tx Inter Packet Gap (XM_TX_IPG): use default */ + /* Tx High Water Mark (XM_TX_HI_WM): use default */ + /* Tx Low Water Mark (XM_TX_LO_WM): use default */ + /* Host Request Threshold (XM_HT_THR): use default */ + /* Rx Request Threshold (XM_RX_THR): use default */ + /* Rx Low Water Mark (XM_RX_LO_WM): use default */ + + /* configure Rx High Water Mark (XM_RX_HI_WM) */ + XM_OUT16(IoC, Port, XM_RX_HI_WM, SK_XM_RX_HI_WM); + + /* Configure Tx Request Threshold */ + SWord = SK_XM_THR_SL; /* for single port */ + + if (pAC->GIni.GIMacsFound > 1) { + switch (pAC->GIni.GIPortUsage) { + case SK_RED_LINK: + SWord = SK_XM_THR_REDL; /* redundant link */ + break; + case SK_MUL_LINK: + SWord = SK_XM_THR_MULL; /* load balancing */ + break; + case SK_JUMBO_LINK: + SWord = SK_XM_THR_JUMBO; /* jumbo frames */ + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E014, SKERR_HWI_E014MSG); + break; + } + } + XM_OUT16(IoC, Port, XM_TX_THR, SWord); + + /* setup register defaults for the Tx Command Register */ + XM_OUT16(IoC, Port, XM_TX_CMD, XM_TX_AUTO_PAD); + + /* setup register defaults for the Rx Command Register */ + SWord = XM_RX_STRIP_FCS | XM_RX_LENERR_OK; + + if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + SWord |= XM_RX_BIG_PK_OK; + } + + if (pPrt->PLinkModeConf == SK_LMODE_HALF) { + /* + * If in manual half duplex mode the other side might be in + * full duplex mode, so ignore if a carrier extension is not seen + * on frames received + */ + SWord |= XM_RX_DIS_CEXT; + } + + XM_OUT16(IoC, Port, XM_RX_CMD, SWord); + + /* + * setup register defaults for the Mode Register + * - Don't strip error frames to avoid Store & Forward + * on the Rx side. + * - Enable 'Check Station Address' bit + * - Enable 'Check Address Array' bit + */ + XM_OUT32(IoC, Port, XM_MODE, XM_DEF_MODE); + + /* + * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK) + * - Enable all bits excepting 'Octets Rx OK Low CntOv' + * and 'Octets Rx OK Hi Cnt Ov'. + */ + XM_OUT32(IoC, Port, XM_RX_EV_MSK, XMR_DEF_MSK); + + /* + * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK) + * - Enable all bits excepting 'Octets Tx OK Low CntOv' + * and 'Octets Tx OK Hi Cnt Ov'. + */ + XM_OUT32(IoC, Port, XM_TX_EV_MSK, XMT_DEF_MSK); + + /* + * Do NOT init XMAC interrupt mask here. + * All interrupts remain disable until link comes up! + */ + + /* + * Any additional configuration changes may be done now. + * The last action is to enable the Rx and Tx state machine. + * This should be done after the auto-negotiation process + * has been completed successfully. + */ +} /* SkXmInitMac */ + +/****************************************************************************** + * + * SkGmInitMac() - Initialize the GMAC + * + * Description: + * Initialize the GMAC of the specified port. + * The GMAC must be reset or stopped before calling this function. + * + * Note: + * The GMAC's Rx and Tx state machine is still disabled when returning. + * + * Returns: + * nothing + */ +void SkGmInitMac( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + int i; + SK_U16 SWord; + SK_U32 DWord; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PState == SK_PRT_STOP) { + /* Port State: SK_PRT_STOP */ + /* Verify that the reset bit is cleared */ + SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord); + + if ((DWord & GMC_RST_SET) != 0) { + /* PState does not match HW state */ + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG); + /* Correct it */ + pPrt->PState = SK_PRT_RESET; + } + } + + if (pPrt->PState == SK_PRT_RESET) { + /* set GPHY Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET); + + /* set GMAC Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET); + + /* clear GMAC Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_CLR); + + /* set GMAC Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET); + + /* set HWCFG_MODE */ + DWord = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | + GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE | + (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP : + GPC_HWCFG_GMII_FIB); + + /* set GPHY Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET); + + /* release GPHY Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR); + + /* clear GMAC Control reset */ + SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); + + /* Dummy read the Interrupt source register */ + SK_IN16(IoC, GMAC_IRQ_SRC, &SWord); + +#ifndef VCPU + /* read Id from PHY */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1); + + SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE); +#endif /* VCPU */ + } + + (void)SkGmResetCounter(pAC, IoC, Port); + + SWord = 0; + + /* speed settings */ + switch (pPrt->PLinkSpeed) { + case SK_LSPEED_AUTO: + case SK_LSPEED_1000MBPS: + SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100; + break; + case SK_LSPEED_100MBPS: + SWord |= GM_GPCR_SPEED_100; + break; + case SK_LSPEED_10MBPS: + break; + } + + /* duplex settings */ + if (pPrt->PLinkMode != SK_LMODE_HALF) { + /* set full duplex */ + SWord |= GM_GPCR_DUP_FULL; + } + + /* flow control settings */ + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + /* disable auto-negotiation for flow-control */ + SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS; + break; + case SK_FLOW_MODE_LOC_SEND: + SWord |= GM_GPCR_FC_RX_DIS; + break; + case SK_FLOW_MODE_SYMMETRIC: + /* TBD */ + case SK_FLOW_MODE_SYM_OR_REM: + /* enable auto-negotiation for flow-control and */ + /* enable Rx and Tx of pause frames */ + break; + } + + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + /* disable auto-update for speed, duplex and flow-control */ + SWord |= GM_GPCR_AU_ALL_DIS; + } + + /* setup General Purpose Control Register */ + GM_OUT16(IoC, Port, GM_GP_CTRL, SWord); + + /* setup Transmit Control Register */ + GM_OUT16(IoC, Port, GM_TX_CTRL, GM_TXCR_COL_THR); + + /* setup Receive Control Register */ + GM_OUT16(IoC, Port, GM_RX_CTRL, GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA | + GM_RXCR_CRC_DIS); + + /* setup Transmit Flow Control Register */ + GM_OUT16(IoC, Port, GM_TX_FLOW_CTRL, 0xffff); + + /* setup Transmit Parameter Register */ +#ifdef VCPU + GM_IN16(IoC, Port, GM_TX_PARAM, &SWord); +#endif /* VCPU */ + + SWord = JAM_LEN_VAL(3) | JAM_IPG_VAL(11) | IPG_JAM_DATA(26); + + GM_OUT16(IoC, Port, GM_TX_PARAM, SWord); + + /* configure the Serial Mode Register */ +#ifdef VCPU + GM_IN16(IoC, Port, GM_SERIAL_MODE, &SWord); +#endif /* VCPU */ + + SWord = GM_SMOD_VLAN_ENA | IPG_VAL_FAST_ETH; + + if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + /* enable jumbo mode (Max. Frame Length = 9018) */ + SWord |= GM_SMOD_JUMBO_ENA; + } + + GM_OUT16(IoC, Port, GM_SERIAL_MODE, SWord); + + /* + * configure the GMACs Station Addresses + * in PROM you can find our addresses at: + * B2_MAC_1 = xx xx xx xx xx x0 virtual address + * B2_MAC_2 = xx xx xx xx xx x1 is programmed to GMAC A + * B2_MAC_3 = xx xx xx xx xx x2 is reserved for DualPort + */ + + for (i = 0; i < 3; i++) { + /* + * The following 2 statements are together endianess + * independent. Remember this when changing. + */ + /* physical address: will be used for pause frames */ + SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord); + +#ifdef WA_DEV_16 + /* WA for deviation #16 */ + if (pAC->GIni.GIChipRev == 0) { + /* swap the address bytes */ + SWord = ((SWord & 0xff00) >> 8) | ((SWord & 0x00ff) << 8); + + /* write to register in reversed order */ + GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + (2 - i) * 4), SWord); + } + else { + GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord); + } +#else + GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord); +#endif /* WA_DEV_16 */ + + /* virtual address: will be used for data */ + SK_IN16(IoC, (B2_MAC_1 + Port * 8 + i * 2), &SWord); + + GM_OUT16(IoC, Port, (GM_SRC_ADDR_2L + i * 4), SWord); + + /* reset Multicast filtering Hash registers 1-3 */ + GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + 4*i, 0); + } + + /* reset Multicast filtering Hash register 4 */ + GM_OUT16(IoC, Port, GM_MC_ADDR_H4, 0); + + /* enable interrupt mask for counter overflows */ + GM_OUT16(IoC, Port, GM_TX_IRQ_MSK, 0); + GM_OUT16(IoC, Port, GM_RX_IRQ_MSK, 0); + GM_OUT16(IoC, Port, GM_TR_IRQ_MSK, 0); + + /* read General Purpose Status */ + GM_IN16(IoC, Port, GM_GP_STAT, &SWord); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("MAC Stat Reg=0x%04X\n", SWord)); + +#ifdef SK_DIAG + c_print("MAC Stat Reg=0x%04X\n", SWord); +#endif /* SK_DIAG */ + +} /* SkGmInitMac */ + + +/****************************************************************************** + * + * SkXmInitDupMd() - Initialize the XMACs Duplex Mode + * + * Description: + * This function initializes the XMACs Duplex Mode. + * It should be called after successfully finishing + * the Auto-negotiation Process + * + * Returns: + * nothing + */ +void SkXmInitDupMd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + switch (pAC->GIni.GP[Port].PLinkModeStatus) { + case SK_LMODE_STAT_AUTOHALF: + case SK_LMODE_STAT_HALF: + /* Configuration Actions for Half Duplex Mode */ + /* + * XM_BURST = default value. We are probable not quick + * enough at the 'XMAC' bus to burst 8kB. + * The XMAC stops bursting if no transmit frames + * are available or the burst limit is exceeded. + */ + /* XM_TX_RT_LIM = default value (15) */ + /* XM_TX_STIME = default value (0xff = 4096 bit times) */ + break; + case SK_LMODE_STAT_AUTOFULL: + case SK_LMODE_STAT_FULL: + /* Configuration Actions for Full Duplex Mode */ + /* + * The duplex mode is configured by the PHY, + * therefore it seems to be that there is nothing + * to do here. + */ + break; + case SK_LMODE_STAT_UNKNOWN: + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E007, SKERR_HWI_E007MSG); + break; + } +} /* SkXmInitDupMd */ + + +/****************************************************************************** + * + * SkXmInitPauseMd() - initialize the Pause Mode to be used for this port + * + * Description: + * This function initializes the Pause Mode which should + * be used for this port. + * It should be called after successfully finishing + * the Auto-negotiation Process + * + * Returns: + * nothing + */ +void SkXmInitPauseMd( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U32 DWord; + SK_U16 Word; + + pPrt = &pAC->GIni.GP[Port]; + + XM_IN16(IoC, Port, XM_MMU_CMD, &Word); + + if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE || + pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) { + + /* Disable Pause Frame Reception */ + Word |= XM_MMU_IGN_PF; + } + else { + /* + * enabling pause frame reception is required for 1000BT + * because the XMAC is not reset if the link is going down + */ + /* Enable Pause Frame Reception */ + Word &= ~XM_MMU_IGN_PF; + } + + XM_OUT16(IoC, Port, XM_MMU_CMD, Word); + + XM_IN32(IoC, Port, XM_MODE, &DWord); + + if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_SYMMETRIC || + pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) { + + /* + * Configure Pause Frame Generation + * Use internal and external Pause Frame Generation. + * Sending pause frames is edge triggered. + * Send a Pause frame with the maximum pause time if + * internal oder external FIFO full condition occurs. + * Send a zero pause time frame to re-start transmission. + */ + + /* XM_PAUSE_DA = '010000C28001' (default) */ + + /* XM_MAC_PTIME = 0xffff (maximum) */ + /* remember this value is defined in big endian (!) */ + XM_OUT16(IoC, Port, XM_MAC_PTIME, 0xffff); + + /* Set Pause Mode in Mode Register */ + DWord |= XM_PAUSE_MODE; + + /* Set Pause Mode in MAC Rx FIFO */ + SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_PAUSE); + } + else { + /* + * disable pause frame generation is required for 1000BT + * because the XMAC is not reset if the link is going down + */ + /* Disable Pause Mode in Mode Register */ + DWord &= ~XM_PAUSE_MODE; + + /* Disable Pause Mode in MAC Rx FIFO */ + SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_DIS_PAUSE); + } + + XM_OUT32(IoC, Port, XM_MODE, DWord); +} /* SkXmInitPauseMd*/ + + +/****************************************************************************** + * + * SkXmInitPhyXmac() - Initialize the XMAC Phy registers + * + * Description: initializes all the XMACs Phy registers + * + * Note: + * + * Returns: + * nothing + */ +static void SkXmInitPhyXmac( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ + SK_GEPORT *pPrt; + SK_U16 Ctrl; + + pPrt = &pAC->GIni.GP[Port]; + Ctrl = 0; + + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyXmac: no auto-negotiation Port %d\n", Port)); + /* Set DuplexMode in Config register */ + if (pPrt->PLinkMode == SK_LMODE_FULL) { + Ctrl |= PHY_CT_DUP_MD; + } + + /* + * Do NOT enable Auto-negotiation here. This would hold + * the link down because no IDLEs are transmitted + */ + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyXmac: with auto-negotiation Port %d\n", Port)); + /* Set Auto-negotiation advertisement */ + + /* Set Full/half duplex capabilities */ + switch (pPrt->PLinkMode) { + case SK_LMODE_AUTOHALF: + Ctrl |= PHY_X_AN_HD; + break; + case SK_LMODE_AUTOFULL: + Ctrl |= PHY_X_AN_FD; + break; + case SK_LMODE_AUTOBOTH: + Ctrl |= PHY_X_AN_FD | PHY_X_AN_HD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015, + SKERR_HWI_E015MSG); + } + + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + Ctrl |= PHY_X_P_NO_PAUSE; + break; + case SK_FLOW_MODE_LOC_SEND: + Ctrl |= PHY_X_P_ASYM_MD; + break; + case SK_FLOW_MODE_SYMMETRIC: + Ctrl |= PHY_X_P_SYM_MD; + break; + case SK_FLOW_MODE_SYM_OR_REM: + Ctrl |= PHY_X_P_BOTH_MD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + + /* Write AutoNeg Advertisement Register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_AUNE_ADV, Ctrl); + + /* Restart Auto-negotiation */ + Ctrl = PHY_CT_ANE | PHY_CT_RE_CFG; + } + + if (DoLoop) { + /* Set the Phy Loopback bit, too */ + Ctrl |= PHY_CT_LOOP; + } + + /* Write to the Phy control register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_CTRL, Ctrl); +} /* SkXmInitPhyXmac */ + + +/****************************************************************************** + * + * SkXmInitPhyBcom() - Initialize the Broadcom Phy registers + * + * Description: initializes all the Broadcom Phy registers + * + * Note: + * + * Returns: + * nothing + */ +static void SkXmInitPhyBcom( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ + SK_GEPORT *pPrt; + SK_U16 Ctrl1; + SK_U16 Ctrl2; + SK_U16 Ctrl3; + SK_U16 Ctrl4; + SK_U16 Ctrl5; + + Ctrl1 = PHY_CT_SP1000; + Ctrl2 = 0; + Ctrl3 = PHY_SEL_TYPE; + Ctrl4 = PHY_B_PEC_EN_LTR; + Ctrl5 = PHY_B_AC_TX_TST; + + pPrt = &pAC->GIni.GP[Port]; + + /* manually Master/Slave ? */ + if (pPrt->PMSMode != SK_MS_MODE_AUTO) { + Ctrl2 |= PHY_B_1000C_MSE; + + if (pPrt->PMSMode == SK_MS_MODE_MASTER) { + Ctrl2 |= PHY_B_1000C_MSC; + } + } + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyBcom: no auto-negotiation Port %d\n", Port)); + /* Set DuplexMode in Config register */ + Ctrl1 |= (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0); + + /* Determine Master/Slave manually if not already done */ + if (pPrt->PMSMode == SK_MS_MODE_AUTO) { + Ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */ + } + + /* + * Do NOT enable Auto-negotiation here. This would hold + * the link down because no IDLES are transmitted + */ + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyBcom: with auto-negotiation Port %d\n", Port)); + /* Set Auto-negotiation advertisement */ + + /* + * Workaround BCOM Errata #1 for the C5 type. + * 1000Base-T Link Acquisition Failure in Slave Mode + * Set Repeater/DTE bit 10 of the 1000Base-T Control Register + */ + Ctrl2 |= PHY_B_1000C_RD; + + /* Set Full/half duplex capabilities */ + switch (pPrt->PLinkMode) { + case SK_LMODE_AUTOHALF: + Ctrl2 |= PHY_B_1000C_AHD; + break; + case SK_LMODE_AUTOFULL: + Ctrl2 |= PHY_B_1000C_AFD; + break; + case SK_LMODE_AUTOBOTH: + Ctrl2 |= PHY_B_1000C_AFD | PHY_B_1000C_AHD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015, + SKERR_HWI_E015MSG); + } + + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + Ctrl3 |= PHY_B_P_NO_PAUSE; + break; + case SK_FLOW_MODE_LOC_SEND: + Ctrl3 |= PHY_B_P_ASYM_MD; + break; + case SK_FLOW_MODE_SYMMETRIC: + Ctrl3 |= PHY_B_P_SYM_MD; + break; + case SK_FLOW_MODE_SYM_OR_REM: + Ctrl3 |= PHY_B_P_BOTH_MD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + + /* Restart Auto-negotiation */ + Ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG; + } + + /* Initialize LED register here? */ + /* No. Please do it in SkDgXmitLed() (if required) and swap + init order of LEDs and XMAC. (MAl) */ + + /* Write 1000Base-T Control Register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, Ctrl2); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2)); + + /* Write AutoNeg Advertisement Register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, Ctrl3); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3)); + + if (DoLoop) { + /* Set the Phy Loopback bit, too */ + Ctrl1 |= PHY_CT_LOOP; + } + + if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { + /* configure FIFO to high latency for transmission of ext. packets */ + Ctrl4 |= PHY_B_PEC_HIGH_LA; + + /* configure reception of extended packets */ + Ctrl5 |= PHY_B_AC_LONG_PACK; + + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, Ctrl5); + } + + /* Configure LED Traffic Mode and Jumbo Frame usage if specified */ + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, Ctrl4); + + /* Write to the Phy control register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, Ctrl1); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Control Reg=0x%04X\n", Ctrl1)); +} /* SkXmInitPhyBcom */ + + +/****************************************************************************** + * + * SkGmInitPhyMarv() - Initialize the Marvell Phy registers + * + * Description: initializes all the Marvell Phy registers + * + * Note: + * + * Returns: + * nothing + */ +static void SkGmInitPhyMarv( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ + SK_GEPORT *pPrt; + SK_U16 PhyCtrl; + SK_U16 C1000BaseT; + SK_U16 AutoNegAdv; + SK_U16 ExtPhyCtrl; + SK_U16 PhyStat; + SK_U16 PhyStat1; + SK_U16 PhySpecStat; + SK_U16 LedCtrl; + SK_BOOL AutoNeg; + +#ifdef VCPU + VCPUprintf(0, "SkGmInitPhyMarv(), Port=%u, DoLoop=%u\n", + Port, DoLoop); +#else /* VCPU */ + + pPrt = &pAC->GIni.GP[Port]; + + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + AutoNeg = SK_FALSE; + } + else { + AutoNeg = SK_TRUE; + } + + if (!DoLoop) { + /* Read Ext. PHY Specific Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl); + + ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | + PHY_M_EC_MAC_S_MSK); + + ExtPhyCtrl |= PHY_M_EC_M_DSC(1) | PHY_M_EC_S_DSC(1) | + PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Ext.PHYCtrl=0x%04X\n", ExtPhyCtrl)); + + /* Read PHY Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl); + + /* Assert software reset */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, + (SK_U16)(PhyCtrl | PHY_CT_RESET)); + } +#endif /* VCPU */ + + PhyCtrl = 0 /* PHY_CT_COL_TST */; + C1000BaseT = 0; + AutoNegAdv = PHY_SEL_TYPE; + + /* manually Master/Slave ? */ + if (pPrt->PMSMode != SK_MS_MODE_AUTO) { + /* enable Manual Master/Slave */ + C1000BaseT |= PHY_M_1000C_MSE; + + if (pPrt->PMSMode == SK_MS_MODE_MASTER) { + C1000BaseT |= PHY_M_1000C_MSC; /* set it to Master */ + } + } + + /* Auto-negotiation ? */ + if (!AutoNeg) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyMarv: no auto-negotiation Port %d\n", Port)); + + if (pPrt->PLinkMode == SK_LMODE_FULL) { + /* Set Full Duplex Mode */ + PhyCtrl |= PHY_CT_DUP_MD; + } + + /* Set Master/Slave manually if not already done */ + if (pPrt->PMSMode == SK_MS_MODE_AUTO) { + C1000BaseT |= PHY_M_1000C_MSE; /* set it to Slave */ + } + + /* Set Speed */ + switch (pPrt->PLinkSpeed) { + case SK_LSPEED_AUTO: + case SK_LSPEED_1000MBPS: + PhyCtrl |= PHY_CT_SP1000; + break; + case SK_LSPEED_100MBPS: + PhyCtrl |= PHY_CT_SP100; + break; + case SK_LSPEED_10MBPS: + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019, + SKERR_HWI_E019MSG); + } + + if (!DoLoop) { + PhyCtrl |= PHY_CT_RESET; + } + /* + * Do NOT enable Auto-negotiation here. This would hold + * the link down because no IDLES are transmitted + */ + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyMarv: with auto-negotiation Port %d\n", Port)); + + PhyCtrl |= PHY_CT_ANE; + + if (pAC->GIni.GICopperType) { + /* Set Speed capabilities */ + switch (pPrt->PLinkSpeed) { + case SK_LSPEED_AUTO: + C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD; + AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD | + PHY_M_AN_10_FD | PHY_M_AN_10_HD; + break; + case SK_LSPEED_1000MBPS: + C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD; + break; + case SK_LSPEED_100MBPS: + AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD | + PHY_M_AN_10_FD | PHY_M_AN_10_HD; + break; + case SK_LSPEED_10MBPS: + AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019, + SKERR_HWI_E019MSG); + } + + /* Set Full/half duplex capabilities */ + switch (pPrt->PLinkMode) { + case SK_LMODE_AUTOHALF: + C1000BaseT &= ~PHY_M_1000C_AFD; + AutoNegAdv &= ~(PHY_M_AN_100_FD | PHY_M_AN_10_FD); + break; + case SK_LMODE_AUTOFULL: + C1000BaseT &= ~PHY_M_1000C_AHD; + AutoNegAdv &= ~(PHY_M_AN_100_HD | PHY_M_AN_10_HD); + break; + case SK_LMODE_AUTOBOTH: + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015, + SKERR_HWI_E015MSG); + } + + /* Set Auto-negotiation advertisement */ + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + AutoNegAdv |= PHY_B_P_NO_PAUSE; + break; + case SK_FLOW_MODE_LOC_SEND: + AutoNegAdv |= PHY_B_P_ASYM_MD; + break; + case SK_FLOW_MODE_SYMMETRIC: + AutoNegAdv |= PHY_B_P_SYM_MD; + break; + case SK_FLOW_MODE_SYM_OR_REM: + AutoNegAdv |= PHY_B_P_BOTH_MD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + } + else { /* special defines for FIBER (88E1011S only) */ + + /* Set Full/half duplex capabilities */ + switch (pPrt->PLinkMode) { + case SK_LMODE_AUTOHALF: + AutoNegAdv |= PHY_M_AN_1000X_AHD; + break; + case SK_LMODE_AUTOFULL: + AutoNegAdv |= PHY_M_AN_1000X_AFD; + break; + case SK_LMODE_AUTOBOTH: + AutoNegAdv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015, + SKERR_HWI_E015MSG); + } + + /* Set Auto-negotiation advertisement */ + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + AutoNegAdv |= PHY_M_P_NO_PAUSE_X; + break; + case SK_FLOW_MODE_LOC_SEND: + AutoNegAdv |= PHY_M_P_ASYM_MD_X; + break; + case SK_FLOW_MODE_SYMMETRIC: + AutoNegAdv |= PHY_M_P_SYM_MD_X; + break; + case SK_FLOW_MODE_SYM_OR_REM: + AutoNegAdv |= PHY_M_P_BOTH_MD_X; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + } + + if (!DoLoop) { + /* Restart Auto-negotiation */ + PhyCtrl |= PHY_CT_RE_CFG; + } + } + +#ifdef VCPU + /* + * E-mail from Gu Lin (08-03-2002): + */ + + /* Program PHY register 30 as 16'h0708 for simulation speed up */ + SkGmPhyWrite(pAC, IoC, Port, 30, 0x0708); + + VCpuWait(2000); + +#else /* VCPU */ + + /* Write 1000Base-T Control Register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("1000B-T Ctrl=0x%04X\n", C1000BaseT)); + + /* Write AutoNeg Advertisement Register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Auto-Neg.Ad.=0x%04X\n", AutoNegAdv)); +#endif /* VCPU */ + + if (DoLoop) { + /* Set the PHY Loopback bit */ + PhyCtrl |= PHY_CT_LOOP; + + /* Program PHY register 16 as 16'h0400 to force link good */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_FL_GOOD); + +#if 0 + if (pPrt->PLinkSpeed != SK_LSPEED_AUTO) { + /* Write Ext. PHY Specific Control */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, + (SK_U16)((pPrt->PLinkSpeed + 2) << 4)); + } + } + else if (pPrt->PLinkSpeed == SK_LSPEED_10MBPS) { + /* Write PHY Specific Control */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_EN_DET_MSK); + } +#endif /* 0 */ + } + + /* Write to the PHY Control register */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl); + +#ifdef VCPU + VCpuWait(2000); +#else + + LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS) | PHY_M_LED_BLINK_RT(BLINK_84MS); + +#ifdef ACT_LED_BLINK + LedCtrl |= PHY_M_LEDC_RX_CTRL | PHY_M_LEDC_TX_CTRL; +#endif /* ACT_LED_BLINK */ + +#ifdef DUP_LED_NORMAL + LedCtrl |= PHY_M_LEDC_DP_CTRL; +#endif /* DUP_LED_NORMAL */ + + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl); + +#endif /* VCPU */ + +#ifdef SK_DIAG + c_print("Set PHY Ctrl=0x%04X\n", PhyCtrl); + c_print("Set 1000 B-T=0x%04X\n", C1000BaseT); + c_print("Set Auto-Neg=0x%04X\n", AutoNegAdv); + c_print("Set Ext Ctrl=0x%04X\n", ExtPhyCtrl); +#endif /* SK_DIAG */ + +#ifndef xDEBUG + /* Read PHY Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Ctrl Reg.=0x%04X\n", PhyCtrl)); + + /* Read 1000Base-T Control Register */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("1000B-T Ctrl =0x%04X\n", C1000BaseT)); + + /* Read AutoNeg Advertisement Register */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &AutoNegAdv); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Auto-Neg. Ad.=0x%04X\n", AutoNegAdv)); + + /* Read Ext. PHY Specific Control */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Ext PHY Ctrl=0x%04X\n", ExtPhyCtrl)); + + /* Read PHY Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Stat Reg.=0x%04X\n", PhyStat)); + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat1); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Stat Reg.=0x%04X\n", PhyStat1)); + + /* Read PHY Specific Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Spec Stat=0x%04X\n", PhySpecStat)); +#endif /* DEBUG */ + +#ifdef SK_DIAG + c_print("PHY Ctrl Reg=0x%04X\n", PhyCtrl); + c_print("PHY 1000 Reg=0x%04X\n", C1000BaseT); + c_print("PHY AnAd Reg=0x%04X\n", AutoNegAdv); + c_print("Ext Ctrl Reg=0x%04X\n", ExtPhyCtrl); + c_print("PHY Stat Reg=0x%04X\n", PhyStat); + c_print("PHY Stat Reg=0x%04X\n", PhyStat1); + c_print("PHY Spec Reg=0x%04X\n", PhySpecStat); +#endif /* SK_DIAG */ + +} /* SkGmInitPhyMarv */ + + +#ifdef OTHER_PHY +/****************************************************************************** + * + * SkXmInitPhyLone() - Initialize the Level One Phy registers + * + * Description: initializes all the Level One Phy registers + * + * Note: + * + * Returns: + * nothing + */ +static void SkXmInitPhyLone( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ + SK_GEPORT *pPrt; + SK_U16 Ctrl1; + SK_U16 Ctrl2; + SK_U16 Ctrl3; + + Ctrl1 = PHY_CT_SP1000; + Ctrl2 = 0; + Ctrl3 = PHY_SEL_TYPE; + + pPrt = &pAC->GIni.GP[Port]; + + /* manually Master/Slave ? */ + if (pPrt->PMSMode != SK_MS_MODE_AUTO) { + Ctrl2 |= PHY_L_1000C_MSE; + + if (pPrt->PMSMode == SK_MS_MODE_MASTER) { + Ctrl2 |= PHY_L_1000C_MSC; + } + } + /* Auto-negotiation ? */ + if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) { + /* + * level one spec say: "1000Mbps: manual mode not allowed" + * but lets see what happens... + */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyLone: no auto-negotiation Port %d\n", Port)); + /* Set DuplexMode in Config register */ + Ctrl1 = (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0); + + /* Determine Master/Slave manually if not already done */ + if (pPrt->PMSMode == SK_MS_MODE_AUTO) { + Ctrl2 |= PHY_L_1000C_MSE; /* set it to Slave */ + } + + /* + * Do NOT enable Auto-negotiation here. This would hold + * the link down because no IDLES are transmitted + */ + } + else { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("InitPhyLone: with auto-negotiation Port %d\n", Port)); + /* Set Auto-negotiation advertisement */ + + /* Set Full/half duplex capabilities */ + switch (pPrt->PLinkMode) { + case SK_LMODE_AUTOHALF: + Ctrl2 |= PHY_L_1000C_AHD; + break; + case SK_LMODE_AUTOFULL: + Ctrl2 |= PHY_L_1000C_AFD; + break; + case SK_LMODE_AUTOBOTH: + Ctrl2 |= PHY_L_1000C_AFD | PHY_L_1000C_AHD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015, + SKERR_HWI_E015MSG); + } + + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + Ctrl3 |= PHY_L_P_NO_PAUSE; + break; + case SK_FLOW_MODE_LOC_SEND: + Ctrl3 |= PHY_L_P_ASYM_MD; + break; + case SK_FLOW_MODE_SYMMETRIC: + Ctrl3 |= PHY_L_P_SYM_MD; + break; + case SK_FLOW_MODE_SYM_OR_REM: + Ctrl3 |= PHY_L_P_BOTH_MD; + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + + /* Restart Auto-negotiation */ + Ctrl1 = PHY_CT_ANE | PHY_CT_RE_CFG; + + } + + /* Initialize LED register here ? */ + /* No. Please do it in SkDgXmitLed() (if required) and swap + init order of LEDs and XMAC. (MAl) */ + + /* Write 1000Base-T Control Register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_1000T_CTRL, Ctrl2); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2)); + + /* Write AutoNeg Advertisement Register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_AUNE_ADV, Ctrl3); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3)); + + + if (DoLoop) { + /* Set the Phy Loopback bit, too */ + Ctrl1 |= PHY_CT_LOOP; + } + + /* Write to the Phy control register */ + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_CTRL, Ctrl1); + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Control Reg=0x%04X\n", Ctrl1)); +} /* SkXmInitPhyLone */ + + +/****************************************************************************** + * + * SkXmInitPhyNat() - Initialize the National Phy registers + * + * Description: initializes all the National Phy registers + * + * Note: + * + * Returns: + * nothing + */ +static void SkXmInitPhyNat( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ +/* todo: National */ +} /* SkXmInitPhyNat */ +#endif /* OTHER_PHY */ + + +/****************************************************************************** + * + * SkMacInitPhy() - Initialize the PHY registers + * + * Description: calls the Init PHY routines dep. on board type + * + * Note: + * + * Returns: + * nothing + */ +void SkMacInitPhy( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + switch (pPrt->PhyType) { + case SK_PHY_XMAC: + SkXmInitPhyXmac(pAC, IoC, Port, DoLoop); + break; + case SK_PHY_BCOM: + SkXmInitPhyBcom(pAC, IoC, Port, DoLoop); + break; + case SK_PHY_MARV_COPPER: + case SK_PHY_MARV_FIBER: + SkGmInitPhyMarv(pAC, IoC, Port, DoLoop); + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmInitPhyLone(pAC, IoC, Port, DoLoop); + break; + case SK_PHY_NAT: + SkXmInitPhyNat(pAC, IoC, Port, DoLoop); + break; +#endif /* OTHER_PHY */ + } +} /* SkMacInitPhy */ + + +#ifndef SK_DIAG +/****************************************************************************** + * + * SkXmAutoNegLipaXmac() - Decides whether Link Partner could do auto-neg + * + * This function analyses the Interrupt status word. If any of the + * Auto-negotiating interrupt bits are set, the PLipaAutoNeg variable + * is set true. + */ +void SkXmAutoNegLipaXmac( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U16 IStatus) /* Interrupt Status word to analyse */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO && + (IStatus & (XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND)) != 0) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegLipa: AutoNeg detected on Port %d, IStatus=0x%04x\n", + Port, IStatus)); + pPrt->PLipaAutoNeg = SK_LIPA_AUTO; + } +} /* SkXmAutoNegLipaXmac */ + + +/****************************************************************************** + * + * SkMacAutoNegLipaPhy() - Decides whether Link Partner could do auto-neg + * + * This function analyses the PHY status word. + * If any of the Auto-negotiating bits are set, the PLipaAutoNeg variable + * is set true. + */ +void SkMacAutoNegLipaPhy( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_U16 PhyStat) /* PHY Status word to analyse */ +{ + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO && + (PhyStat & PHY_ST_AN_OVER) != 0) { + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat=0x%04x\n", + Port, PhyStat)); + pPrt->PLipaAutoNeg = SK_LIPA_AUTO; + } +} /* SkMacAutoNegLipaPhy */ +#endif /* SK_DIAG */ + + +/****************************************************************************** + * + * SkXmAutoNegDoneXmac() - Auto-negotiation handling + * + * Description: + * This function handles the auto-negotiation if the Done bit is set. + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +static int SkXmAutoNegDoneXmac( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 ResAb; /* Resolved Ability */ + SK_U16 LPAb; /* Link Partner Ability */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegDoneXmac, Port %d\n",Port)); + + pPrt = &pAC->GIni.GP[Port]; + + /* Get PHY parameters */ + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LPAb); + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb); + + if ((LPAb & PHY_X_AN_RFB) != 0) { + /* At least one of the remote fault bit is set */ + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Remote fault bit set Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); + } + + /* Check Duplex mismatch */ + if ((ResAb & (PHY_X_RS_HD | PHY_X_RS_FD)) == PHY_X_RS_FD) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + } + else if ((ResAb & (PHY_X_RS_HD | PHY_X_RS_FD)) == PHY_X_RS_HD) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + } + else { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Duplex mode mismatch Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_DUP_CAP); + } + + /* Check PAUSE mismatch */ + /* We are NOT using chapter 4.23 of the Xaqti manual */ + /* We are using IEEE 802.3z/D5.0 Table 37-4 */ + if ((pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC || + pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) && + (LPAb & PHY_X_P_SYM_MD) != 0) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM && + (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) { + /* Enable PAUSE receive, disable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; + } + else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND && + (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) { + /* Disable PAUSE receive, enable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; + } + else { + /* PAUSE mismatch -> no PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + } + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + + return(SK_AND_OK); +} /* SkXmAutoNegDoneXmac */ + + +/****************************************************************************** + * + * SkXmAutoNegDoneBcom() - Auto-negotiation handling + * + * Description: + * This function handles the auto-negotiation if the Done bit is set. + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +static int SkXmAutoNegDoneBcom( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 LPAb; /* Link Partner Ability */ + SK_U16 AuxStat; /* Auxiliary Status */ + +#if 0 +01-Sep-2000 RA;:;: + SK_U16 ResAb; /* Resolved Ability */ +#endif /* 0 */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegDoneBcom, Port %d\n", Port)); + pPrt = &pAC->GIni.GP[Port]; + + /* Get PHY parameters */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LPAb); +#if 0 +01-Sep-2000 RA;:;: + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb); +#endif /* 0 */ + + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &AuxStat); + + if ((LPAb & PHY_B_AN_RF) != 0) { + /* Remote fault bit is set: Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Remote fault bit set Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); + } + + /* Check Duplex mismatch */ + if ((AuxStat & PHY_B_AS_AN_RES_MSK) == PHY_B_RES_1000FD) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + } + else if ((AuxStat & PHY_B_AS_AN_RES_MSK) == PHY_B_RES_1000HD) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + } + else { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Duplex mode mismatch Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_DUP_CAP); + } + +#if 0 +01-Sep-2000 RA;:;: + /* Check Master/Slave resolution */ + if ((ResAb & PHY_B_1000S_MSF) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Master/Slave Fault Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + return(SK_AND_OTHER); + } + + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? + SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE; +#endif /* 0 */ + + /* Check PAUSE mismatch */ + /* We are using IEEE 802.3z/D5.0 Table 37-4 */ + if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PAUSE_MSK) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRR) { + /* Enable PAUSE receive, disable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; + } + else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRT) { + /* Disable PAUSE receive, enable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; + } + else { + /* PAUSE mismatch -> no PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + } + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + + return(SK_AND_OK); +} /* SkXmAutoNegDoneBcom */ + + +/****************************************************************************** + * + * SkGmAutoNegDoneMarv() - Auto-negotiation handling + * + * Description: + * This function handles the auto-negotiation if the Done bit is set. + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +static int SkGmAutoNegDoneMarv( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 LPAb; /* Link Partner Ability */ + SK_U16 ResAb; /* Resolved Ability */ + SK_U16 AuxStat; /* Auxiliary Status */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegDoneMarv, Port %d\n", Port)); + pPrt = &pAC->GIni.GP[Port]; + + /* Get PHY parameters */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LPAb); + + if ((LPAb & PHY_M_AN_RF) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Remote fault bit set Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); + } + + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb); + + /* Check Master/Slave resolution */ + if ((ResAb & PHY_B_1000S_MSF) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Master/Slave Fault Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + return(SK_AND_OTHER); + } + + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ? + (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE; + + /* Read PHY Specific Status */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &AuxStat); + + /* Check Speed & Duplex resolved */ + if ((AuxStat & PHY_M_PS_SPDUP_RES) == 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Speed & Duplex not resolved Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; + return(SK_AND_DUP_CAP); + } + + if ((AuxStat & PHY_M_PS_FULL_DUP) != 0) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + } + else { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + } + + /* Check PAUSE mismatch */ + /* We are using IEEE 802.3z/D5.0 Table 37-4 */ + if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_PAUSE_MSK) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_RX_P_EN) { + /* Enable PAUSE receive, disable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; + } + else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_TX_P_EN) { + /* Disable PAUSE receive, enable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; + } + else { + /* PAUSE mismatch -> no PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + } + + /* set used link speed */ + switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) { + case (unsigned)PHY_M_PS_SPEED_1000: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS; + break; + case PHY_M_PS_SPEED_100: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_100MBPS; + break; + default: + pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_10MBPS; + } + + return(SK_AND_OK); +} /* SkGmAutoNegDoneMarv */ + + +#ifdef OTHER_PHY +/****************************************************************************** + * + * SkXmAutoNegDoneLone() - Auto-negotiation handling + * + * Description: + * This function handles the auto-negotiation if the Done bit is set. + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +static int SkXmAutoNegDoneLone( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 ResAb; /* Resolved Ability */ + SK_U16 LPAb; /* Link Partner Ability */ + SK_U16 QuickStat; /* Auxiliary Status */ + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegDoneLone, Port %d\n",Port)); + pPrt = &pAC->GIni.GP[Port]; + + /* Get PHY parameters */ + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LPAb); + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ResAb); + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_Q_STAT, &QuickStat); + + if ((LPAb & PHY_L_AN_RF) != 0) { + /* Remote fault bit is set */ + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("AutoNegFail: Remote fault bit set Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + return(SK_AND_OTHER); + } + + /* Check Duplex mismatch */ + if ((QuickStat & PHY_L_QS_DUP_MOD) != 0) { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL; + } + else { + pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF; + } + + /* Check Master/Slave resolution */ + if ((ResAb & PHY_L_1000S_MSF) != 0) { + /* Error */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("Master/Slave Fault Port %d\n", Port)); + pPrt->PAutoNegFail = SK_TRUE; + pPrt->PMSStatus = SK_MS_STAT_FAULT; + return(SK_AND_OTHER); + } + else if (ResAb & PHY_L_1000S_MSR) { + pPrt->PMSStatus = SK_MS_STAT_MASTER; + } + else { + pPrt->PMSStatus = SK_MS_STAT_SLAVE; + } + + /* Check PAUSE mismatch */ + /* We are using IEEE 802.3z/D5.0 Table 37-4 */ + /* we must manually resolve the abilities here */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; + switch (pPrt->PFlowCtrlMode) { + case SK_FLOW_MODE_NONE: + /* default */ + break; + case SK_FLOW_MODE_LOC_SEND: + if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) == + (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) { + /* Disable PAUSE receive, enable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND; + } + break; + case SK_FLOW_MODE_SYMMETRIC: + if ((QuickStat & PHY_L_QS_PAUSE) != 0) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + break; + case SK_FLOW_MODE_SYM_OR_REM: + if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) == + PHY_L_QS_AS_PAUSE) { + /* Enable PAUSE receive, disable PAUSE transmit */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND; + } + else if ((QuickStat & PHY_L_QS_PAUSE) != 0) { + /* Symmetric PAUSE */ + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC; + } + break; + default: + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016, + SKERR_HWI_E016MSG); + } + + return(SK_AND_OK); +} /* SkXmAutoNegDoneLone */ + + +/****************************************************************************** + * + * SkXmAutoNegDoneNat() - Auto-negotiation handling + * + * Description: + * This function handles the auto-negotiation if the Done bit is set. + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +static int SkXmAutoNegDoneNat( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ +/* todo: National */ + return(SK_AND_OK); +} /* SkXmAutoNegDoneNat */ +#endif /* OTHER_PHY */ + + +/****************************************************************************** + * + * SkMacAutoNegDone() - Auto-negotiation handling + * + * Description: calls the auto-negotiation done routines dep. on board type + * + * Returns: + * SK_AND_OK o.k. + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened + */ +int SkMacAutoNegDone( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + int Rtv; + + pPrt = &pAC->GIni.GP[Port]; + + switch (pPrt->PhyType) { + case SK_PHY_XMAC: + Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port); + break; + case SK_PHY_BCOM: + Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port); + break; + case SK_PHY_MARV_COPPER: + case SK_PHY_MARV_FIBER: + Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port); + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port); + break; + case SK_PHY_NAT: + Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port); + break; +#endif /* OTHER_PHY */ + default: + return(SK_AND_OTHER); + } + + if (Rtv != SK_AND_OK) { + return(Rtv); + } + + /* We checked everything and may now enable the link */ + pPrt->PAutoNegFail = SK_FALSE; + + SkMacRxTxEnable(pAC, IoC, Port); + + return(SK_AND_OK); +} /* SkMacAutoNegDone */ + + +/****************************************************************************** + * + * SkXmSetRxTxEn() - Special Set Rx/Tx Enable and some features in XMAC + * + * Description: + * sets MAC or PHY LoopBack and Duplex Mode in the MMU Command Reg. + * enables Rx/Tx + * + * Returns: N/A + */ +static void SkXmSetRxTxEn( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Para) /* Parameter to set: MAC or PHY LoopBack, Duplex Mode */ +{ + SK_U16 Word; + + XM_IN16(IoC, Port, XM_MMU_CMD, &Word); + + switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) { + case SK_MAC_LOOPB_ON: + Word |= XM_MMU_MAC_LB; + break; + case SK_MAC_LOOPB_OFF: + Word &= ~XM_MMU_MAC_LB; + break; + } + + switch (Para & (SK_PHY_LOOPB_ON | SK_PHY_LOOPB_OFF)) { + case SK_PHY_LOOPB_ON: + Word |= XM_MMU_GMII_LOOP; + break; + case SK_PHY_LOOPB_OFF: + Word &= ~XM_MMU_GMII_LOOP; + break; + } + + switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) { + case SK_PHY_FULLD_ON: + Word |= XM_MMU_GMII_FD; + break; + case SK_PHY_FULLD_OFF: + Word &= ~XM_MMU_GMII_FD; + break; + } + + XM_OUT16(IoC, Port, XM_MMU_CMD, Word | XM_MMU_ENA_RX | XM_MMU_ENA_TX); + + /* dummy read to ensure writing */ + XM_IN16(IoC, Port, XM_MMU_CMD, &Word); + +} /* SkXmSetRxTxEn */ + + +/****************************************************************************** + * + * SkGmSetRxTxEn() - Special Set Rx/Tx Enable and some features in GMAC + * + * Description: + * sets MAC LoopBack and Duplex Mode in the General Purpose Control Reg. + * enables Rx/Tx + * + * Returns: N/A + */ +static void SkGmSetRxTxEn( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Para) /* Parameter to set: MAC LoopBack, Duplex Mode */ +{ + SK_U16 Ctrl; + + GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl); + + switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) { + case SK_MAC_LOOPB_ON: + Ctrl |= GM_GPCR_LOOP_ENA; + break; + case SK_MAC_LOOPB_OFF: + Ctrl &= ~GM_GPCR_LOOP_ENA; + break; + } + + switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) { + case SK_PHY_FULLD_ON: + Ctrl |= GM_GPCR_DUP_FULL; + break; + case SK_PHY_FULLD_OFF: + Ctrl &= ~GM_GPCR_DUP_FULL; + break; + } + + GM_OUT16(IoC, Port, GM_GP_CTRL, Ctrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); + + /* dummy read to ensure writing */ + GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl); + +} /* SkGmSetRxTxEn */ + + +/****************************************************************************** + * + * SkMacSetRxTxEn() - Special Set Rx/Tx Enable and parameters + * + * Description: calls the Special Set Rx/Tx Enable routines dep. on board type + * + * Returns: N/A + */ +void SkMacSetRxTxEn( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +int Para) +{ + if (pAC->GIni.GIGenesis) { + + SkXmSetRxTxEn(pAC, IoC, Port, Para); + } + else { + + SkGmSetRxTxEn(pAC, IoC, Port, Para); + } + +} /* SkMacSetRxTxEn */ + + +/****************************************************************************** + * + * SkMacRxTxEnable() - Enable Rx/Tx activity if port is up + * + * Description: enables Rx/Tx dep. on board type + * + * Returns: + * 0 o.k. + * != 0 Error happened + */ +int SkMacRxTxEnable( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 Reg; /* 16-bit register value */ + SK_U16 IntMask; /* MAC interrupt mask */ + SK_U16 SWord; + + pPrt = &pAC->GIni.GP[Port]; + + if (!pPrt->PHWLinkUp) { + /* The Hardware link is NOT up */ + return(0); + } + + if ((pPrt->PLinkMode == SK_LMODE_AUTOHALF || + pPrt->PLinkMode == SK_LMODE_AUTOFULL || + pPrt->PLinkMode == SK_LMODE_AUTOBOTH) && + pPrt->PAutoNegFail) { + /* Auto-negotiation is not done or failed */ + return(0); + } + + if (pAC->GIni.GIGenesis) { + /* set Duplex Mode and Pause Mode */ + SkXmInitDupMd(pAC, IoC, Port); + + SkXmInitPauseMd(pAC, IoC, Port); + + /* + * Initialize the Interrupt Mask Register. Default IRQs are... + * - Link Asynchronous Event + * - Link Partner requests config + * - Auto Negotiation Done + * - Rx Counter Event Overflow + * - Tx Counter Event Overflow + * - Transmit FIFO Underrun + */ + IntMask = XM_DEF_MSK; + +#ifdef DEBUG + /* add IRQ for Receive FIFO Overflow */ + IntMask &= ~XM_IS_RXF_OV; +#endif /* DEBUG */ + + if (pPrt->PhyType != SK_PHY_XMAC) { + /* disable GP0 interrupt bit */ + IntMask |= XM_IS_INP_ASS; + } + XM_OUT16(IoC, Port, XM_IMSK, IntMask); + + /* get MMU Command Reg. */ + XM_IN16(IoC, Port, XM_MMU_CMD, &Reg); + + if (pPrt->PhyType != SK_PHY_XMAC && + (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL)) { + /* set to Full Duplex */ + Reg |= XM_MMU_GMII_FD; + } + + switch (pPrt->PhyType) { + case SK_PHY_BCOM: + /* + * Workaround BCOM Errata (#10523) for all BCom Phys + * Enable Power Management after link up + */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, + (SK_U16)(SWord & ~PHY_B_AC_DIS_PM)); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_INT_ENAB, PHY_L_DEF_MSK); + break; + case SK_PHY_NAT: + /* todo National: + SkXmPhyWrite(pAC, IoC, Port, PHY_NAT_INT_MASK, PHY_N_DEF_MSK); */ + /* no interrupts possible from National ??? */ + break; +#endif /* OTHER_PHY */ + } + + /* enable Rx/Tx */ + XM_OUT16(IoC, Port, XM_MMU_CMD, Reg | XM_MMU_ENA_RX | XM_MMU_ENA_TX); + } + else { + /* + * Initialize the Interrupt Mask Register. Default IRQs are... + * - Rx Counter Event Overflow + * - Tx Counter Event Overflow + * - Transmit FIFO Underrun + */ + IntMask = GMAC_DEF_MSK; + +#ifdef DEBUG + /* add IRQ for Receive FIFO Overrun */ + IntMask |= GM_IS_RX_FF_OR; +#endif /* DEBUG */ + + SK_OUT8(IoC, GMAC_IRQ_MSK, (SK_U8)IntMask); + + /* get General Purpose Control */ + GM_IN16(IoC, Port, GM_GP_CTRL, &Reg); + + if (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL || + pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) { + /* set to Full Duplex */ + Reg |= GM_GPCR_DUP_FULL; + } + + /* enable Rx/Tx */ + GM_OUT16(IoC, Port, GM_GP_CTRL, Reg | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); + +#ifndef VCPU + /* Enable all PHY interrupts */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); +#endif /* VCPU */ + } + + return(0); + +} /* SkMacRxTxEnable */ + + +/****************************************************************************** + * + * SkMacRxTxDisable() - Disable Receiver and Transmitter + * + * Description: disables Rx/Tx dep. on board type + * + * Returns: N/A + */ +void SkMacRxTxDisable( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 Word; + + if (pAC->GIni.GIGenesis) { + + XM_IN16(IoC, Port, XM_MMU_CMD, &Word); + + XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); + + /* dummy read to ensure writing */ + XM_IN16(IoC, Port, XM_MMU_CMD, &Word); + } + else { + + GM_IN16(IoC, Port, GM_GP_CTRL, &Word); + + GM_OUT16(IoC, Port, GM_GP_CTRL, Word & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)); + + /* dummy read to ensure writing */ + GM_IN16(IoC, Port, GM_GP_CTRL, &Word); + } +} /* SkMacRxTxDisable */ + + +/****************************************************************************** + * + * SkMacIrqDisable() - Disable IRQ from MAC + * + * Description: sets the IRQ-mask to disable IRQ dep. on board type + * + * Returns: N/A + */ +void SkMacIrqDisable( +SK_AC *pAC, /* Adapter Context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 Word; + + pPrt = &pAC->GIni.GP[Port]; + + if (pAC->GIni.GIGenesis) { + + /* disable all XMAC IRQs */ + XM_OUT16(IoC, Port, XM_IMSK, 0xffff); + + /* Disable all PHY interrupts */ + switch (pPrt->PhyType) { + case SK_PHY_BCOM: + /* Make sure that PHY is initialized */ + if (pPrt->PState != SK_PRT_RESET) { + /* NOT allowed if BCOM is in RESET state */ + /* Workaround BCOM Errata (#10523) all BCom */ + /* Disable Power Management if link is down */ + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Word); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, + (SK_U16)(Word | PHY_B_AC_DIS_PM)); + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, 0xffff); + } + break; +#ifdef OTHER_PHY + case SK_PHY_LONE: + SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_INT_ENAB, 0); + break; + case SK_PHY_NAT: + /* todo: National + SkXmPhyWrite(pAC, IoC, Port, PHY_NAT_INT_MASK, 0xffff); */ + break; +#endif /* OTHER_PHY */ + } + } + else { + /* disable all GMAC IRQs */ + SK_OUT8(IoC, GMAC_IRQ_MSK, 0); + +#ifndef VCPU + /* Disable all PHY interrupts */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0); +#endif /* VCPU */ + } +} /* SkMacIrqDisable */ + + +#ifdef SK_DIAG +/****************************************************************************** + * + * SkXmSendCont() - Enable / Disable Send Continuous Mode + * + * Description: enable / disable Send Continuous Mode on XMAC + * + * Returns: + * nothing + */ +void SkXmSendCont( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL Enable) /* Enable / Disable */ +{ + SK_U32 MdReg; + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + + if (Enable) { + MdReg |= XM_MD_TX_CONT; + } + else { + MdReg &= ~XM_MD_TX_CONT; + } + /* setup Mode Register */ + XM_OUT32(IoC, Port, XM_MODE, MdReg); + +} /* SkXmSendCont*/ + +/****************************************************************************** + * + * SkMacTimeStamp() - Enable / Disable Time Stamp + * + * Description: enable / disable Time Stamp generation for Rx packets + * + * Returns: + * nothing + */ +void SkMacTimeStamp( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL Enable) /* Enable / Disable */ +{ + SK_U32 MdReg; + SK_U8 TimeCtrl; + + if (pAC->GIni.GIGenesis) { + + XM_IN32(IoC, Port, XM_MODE, &MdReg); + + if (Enable) { + MdReg |= XM_MD_ATS; + } + else { + MdReg &= ~XM_MD_ATS; + } + /* setup Mode Register */ + XM_OUT32(IoC, Port, XM_MODE, MdReg); + } + else { + if (Enable) { + TimeCtrl = GMT_ST_START | GMT_ST_CLR_IRQ; + } + else { + TimeCtrl = GMT_ST_STOP | GMT_ST_CLR_IRQ; + } + /* Start/Stop Time Stamp Timer */ + SK_OUT8(pAC, GMAC_TI_ST_CTRL, TimeCtrl); + } +} /* SkMacTimeStamp*/ + +#else /* SK_DIAG */ + +/****************************************************************************** + * + * SkXmIrq() - Interrupt Service Routine + * + * Description: services an Interrupt Request of the XMAC + * + * Note: + * With an external PHY, some interrupt bits are not meaningfull any more: + * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE + * - LinkPartnerReqConfig (bit #10) XM_IS_LIPA_RC + * - Page Received (bit #9) XM_IS_RX_PAGE + * - NextPageLoadedForXmt (bit #8) XM_IS_TX_PAGE + * - AutoNegDone (bit #7) XM_IS_AND + * Also probably not valid any more is the GP0 input bit: + * - GPRegisterBit0set XM_IS_INP_ASS + * + * Returns: + * nothing + */ +void SkXmIrq( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_EVPARA Para; + SK_U16 IStatus; /* Interrupt status read from the XMAC */ + SK_U16 IStatus2; + + pPrt = &pAC->GIni.GP[Port]; + + XM_IN16(IoC, Port, XM_ISRC, &IStatus); + + /* LinkPartner Auto-negable? */ + if (pPrt->PhyType == SK_PHY_XMAC) { + SkXmAutoNegLipaXmac(pAC, IoC, Port, IStatus); + } + else { + /* mask bits that are not used with ext. PHY */ + IStatus &= ~(XM_IS_LNK_AE | XM_IS_LIPA_RC | + XM_IS_RX_PAGE | XM_IS_TX_PAGE | + XM_IS_AND | XM_IS_INP_ASS); + } + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("XmacIrq Port %d Isr 0x%04x\n", Port, IStatus)); + + if (!pPrt->PHWLinkUp) { + /* Spurious XMAC interrupt */ + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("SkXmIrq: spurious interrupt on Port %d\n", Port)); + return; + } + + if ((IStatus & XM_IS_INP_ASS) != 0) { + /* Reread ISR Register if link is not in sync */ + XM_IN16(IoC, Port, XM_ISRC, &IStatus2); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("SkXmIrq: Link async. Double check Port %d 0x%04x 0x%04x\n", + Port, IStatus, IStatus2)); + IStatus &= ~XM_IS_INP_ASS; + IStatus |= IStatus2; + } + + if ((IStatus & XM_IS_LNK_AE) != 0) { + /* not used, GP0 is used instead */ + } + + if ((IStatus & XM_IS_TX_ABORT) != 0) { + /* not used */ + } + + if ((IStatus & XM_IS_FRC_INT) != 0) { + /* not used, use ASIC IRQ instead if needed */ + } + + if ((IStatus & (XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE)) != 0) { + SkHWLinkDown(pAC, IoC, Port); + + /* Signal to RLMT */ + Para.Para32[0] = (SK_U32)Port; + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para); + + /* Start workaround Errata #2 timer */ + SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME, + SKGE_HWAC, SK_HWEV_WATIM, Para); + } + + if ((IStatus & XM_IS_RX_PAGE) != 0) { + /* not used */ + } + + if ((IStatus & XM_IS_TX_PAGE) != 0) { + /* not used */ + } + + if ((IStatus & XM_IS_AND) != 0) { + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("SkXmIrq: AND on link that is up Port %d\n", Port)); + } + + if ((IStatus & XM_IS_TSC_OV) != 0) { + /* not used */ + } + + /* Combined Tx & Rx Counter Overflow SIRQ Event */ + if ((IStatus & (XM_IS_RXC_OV | XM_IS_TXC_OV)) != 0) { + Para.Para32[0] = (SK_U32)Port; + Para.Para32[1] = (SK_U32)IStatus; + SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para); + } + + if ((IStatus & XM_IS_RXF_OV) != 0) { + /* normal situation -> no effect */ +#ifdef DEBUG + pPrt->PRxOverCnt++; +#endif /* DEBUG */ + } + + if ((IStatus & XM_IS_TXF_UR) != 0) { + /* may NOT happen -> error log */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E020, SKERR_SIRQ_E020MSG); + } + + if ((IStatus & XM_IS_TX_COMP) != 0) { + /* not served here */ + } + + if ((IStatus & XM_IS_RX_COMP) != 0) { + /* not served here */ + } +} /* SkXmIrq */ + + +/****************************************************************************** + * + * SkGmIrq() - Interrupt Service Routine + * + * Description: services an Interrupt Request of the GMAC + * + * Note: + * + * Returns: + * nothing + */ +void SkGmIrq( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_EVPARA Para; + SK_U8 IStatus; /* Interrupt status */ + + pPrt = &pAC->GIni.GP[Port]; + + SK_IN8(IoC, GMAC_IRQ_SRC, &IStatus); + + /* LinkPartner Auto-negable? */ + SkMacAutoNegLipaPhy(pAC, IoC, Port, IStatus); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, + ("GmacIrq Port %d Isr 0x%04x\n", Port, IStatus)); + + /* Combined Tx & Rx Counter Overflow SIRQ Event */ + if (IStatus & (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV)) { + /* these IRQs will be cleared by reading GMACs register */ + Para.Para32[0] = (SK_U32)Port; + Para.Para32[1] = (SK_U32)IStatus; + SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para); + } + + if (IStatus & GM_IS_RX_FF_OR) { + /* clear GMAC Rx FIFO Overrun IRQ */ + SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FO); +#ifdef DEBUG + pPrt->PRxOverCnt++; +#endif /* DEBUG */ + } + + if (IStatus & GM_IS_TX_FF_UR) { + /* clear GMAC Tx FIFO Underrun IRQ */ + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FU); + /* may NOT happen -> error log */ + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E020, SKERR_SIRQ_E020MSG); + } + + if (IStatus & GM_IS_TX_COMPL) { + /* not served here */ + } + + if (IStatus & GM_IS_RX_COMPL) { + /* not served here */ + } +} /* SkGmIrq */ + +/****************************************************************************** + * + * SkMacIrq() - Interrupt Service Routine for MAC + * + * Description: calls the Interrupt Service Routine dep. on board type + * + * Returns: + * nothing + */ +void SkMacIrq( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port) /* Port Index (MAC_1 + n) */ +{ + + if (pAC->GIni.GIGenesis) { + /* IRQ from XMAC */ + SkXmIrq(pAC, IoC, Port); + } + else { + /* IRQ from GMAC */ + SkGmIrq(pAC, IoC, Port); + } +} /* SkMacIrq */ + +#endif /* !SK_DIAG */ + +/****************************************************************************** + * + * SkXmUpdateStats() - Force the XMAC to output the current statistic + * + * Description: + * The XMAC holds its statistic internally. To obtain the current + * values a command must be sent so that the statistic data will + * be written to a predefined memory area on the adapter. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkXmUpdateStats( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port) /* Port Index (MAC_1 + n) */ +{ + SK_GEPORT *pPrt; + SK_U16 StatReg; + int WaitIndex; + + pPrt = &pAC->GIni.GP[Port]; + WaitIndex = 0; + + /* Send an update command to XMAC specified */ + XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); + + /* + * It is an auto-clearing register. If the command bits + * went to zero again, the statistics are transferred. + * Normally the command should be executed immediately. + * But just to be sure we execute a loop. + */ + do { + + XM_IN16(IoC, Port, XM_STAT_CMD, &StatReg); + + if (++WaitIndex > 10) { + + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E021, SKERR_HWI_E021MSG); + + return(1); + } + } while ((StatReg & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) != 0); + + return(0); +} /* SkXmUpdateStats */ + +/****************************************************************************** + * + * SkGmUpdateStats() - Force the GMAC to output the current statistic + * + * Description: + * Empty function for GMAC. Statistic data is accessible in direct way. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmUpdateStats( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port) /* Port Index (MAC_1 + n) */ +{ + return(0); +} + +/****************************************************************************** + * + * SkXmMacStatistic() - Get XMAC counter value + * + * Description: + * Gets the 32bit counter value. Except for the octet counters + * the lower 32bit are counted in hardware and the upper 32bit + * must be counted in software by monitoring counter overflow interrupts. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkXmMacStatistic( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 StatAddr, /* MIB counter base address */ +SK_U32 *pVal) /* ptr to return statistic value */ +{ + if ((StatAddr < XM_TXF_OK) || (StatAddr > XM_RXF_MAX_SZ)) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG); + + return(1); + } + + XM_IN32(IoC, Port, StatAddr, pVal); + + return(0); +} /* SkXmMacStatistic */ + +/****************************************************************************** + * + * SkGmMacStatistic() - Get GMAC counter value + * + * Description: + * Gets the 32bit counter value. Except for the octet counters + * the lower 32bit are counted in hardware and the upper 32bit + * must be counted in software by monitoring counter overflow interrupts. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmMacStatistic( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 StatAddr, /* MIB counter base address */ +SK_U32 *pVal) /* ptr to return statistic value */ +{ + + if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) { + + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr)); + return(1); + } + + GM_IN32(IoC, Port, StatAddr, pVal); + + return(0); +} /* SkGmMacStatistic */ + +/****************************************************************************** + * + * SkXmResetCounter() - Clear MAC statistic counter + * + * Description: + * Force the XMAC to clear its statistic counter. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkXmResetCounter( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port) /* Port Index (MAC_1 + n) */ +{ + XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC); + /* Clear two times according to Errata #3 */ + XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC); + + return(0); +} /* SkXmResetCounter */ + +/****************************************************************************** + * + * SkGmResetCounter() - Clear MAC statistic counter + * + * Description: + * Force GMAC to clear its statistic counter. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmResetCounter( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port) /* Port Index (MAC_1 + n) */ +{ + SK_U16 Reg; /* Phy Address Register */ + SK_U16 Word; + int i; + + GM_IN16(IoC, Port, GM_PHY_ADDR, &Reg); + +#ifndef VCPU + /* set MIB Clear Counter Mode */ + GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR); + + /* read all MIB Counters with Clear Mode set */ + for (i = 0; i < GM_MIB_CNT_SIZE; i++) { + /* the reset is performed only when the lower 16 bits are read */ + GM_IN16(IoC, Port, GM_MIB_CNT_BASE + 8*i, &Word); + } + + /* clear MIB Clear Counter Mode */ + GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg); +#endif /* !VCPU */ + + return(0); +} /* SkGmResetCounter */ + +/****************************************************************************** + * + * SkXmOverflowStatus() - Gets the status of counter overflow interrupt + * + * Description: + * Checks the source causing an counter overflow interrupt. On success the + * resulting counter overflow status is written to , whereas the + * upper dword stores the XMAC ReceiveCounterEvent register and the lower + * dword the XMAC TransmitCounterEvent register. + * + * Note: + * For XMAC the interrupt source is a self-clearing register, so the source + * must be checked only once. SIRQ module does another check to be sure + * that no interrupt get lost during process time. + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkXmOverflowStatus( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 IStatus, /* Interupt Status from MAC */ +SK_U64 *pStatus) /* ptr for return overflow status value */ +{ + SK_U64 Status; /* Overflow status */ + SK_U32 RegVal; + + Status = 0; + + if ((IStatus & XM_IS_RXC_OV) != 0) { + + XM_IN32(IoC, Port, XM_RX_CNT_EV, &RegVal); + Status |= (SK_U64)RegVal << 32; + } + + if ((IStatus & XM_IS_TXC_OV) != 0) { + + XM_IN32(IoC, Port, XM_TX_CNT_EV, &RegVal); + Status |= (SK_U64)RegVal; + } + + *pStatus = Status; + + return(0); +} /* SkXmOverflowStatus */ + + +/****************************************************************************** + * + * SkGmOverflowStatus() - Gets the status of counter overflow interrupt + * + * Description: + * Checks the source causing an counter overflow interrupt. On success the + * resulting counter overflow status is written to , whereas the + * the following bit coding is used: + * 63:56 - unused + * 55:48 - TxRx interrupt register bit7:0 + * 32:47 - Rx interrupt register + * 31:24 - unused + * 23:16 - TxRx interrupt register bit15:8 + * 15:0 - Tx interrupt register + * + * Returns: + * 0: success + * 1: something went wrong + */ +int SkGmOverflowStatus( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +unsigned int Port, /* Port Index (MAC_1 + n) */ +SK_U16 IStatus, /* Interupt Status from MAC */ +SK_U64 *pStatus) /* ptr for return overflow status value */ +{ + SK_U64 Status; /* Overflow status */ + SK_U16 RegVal; + + Status = 0; + + if ((IStatus & GM_IS_RX_CO_OV) != 0) { + /* this register is self-clearing after read */ + GM_IN16(IoC, Port, GM_RX_IRQ_SRC, &RegVal); + Status |= (SK_U64)RegVal << 32; + } + + if ((IStatus & GM_IS_TX_CO_OV) != 0) { + /* this register is self-clearing after read */ + GM_IN16(IoC, Port, GM_TX_IRQ_SRC, &RegVal); + Status |= (SK_U64)RegVal; + } + + /* this register is self-clearing after read */ + GM_IN16(IoC, Port, GM_TR_IRQ_SRC, &RegVal); + /* Rx overflow interrupt register bits (LoByte)*/ + Status |= (SK_U64)((SK_U8)RegVal) << 48; + /* Tx overflow interrupt register bits (HiByte)*/ + Status |= (SK_U64)(RegVal >> 8) << 16; + + *pStatus = Status; + + return(0); +} /* SkGmOverflowStatus */ + +/****************************************************************************** + * + * SkGmCableDiagStatus() - Starts / Gets status of cable diagnostic test + * + * Description: + * starts the cable diagnostic test if 'StartTest' is true + * gets the results if 'StartTest' is true + * + * NOTE: this test is meaningful only when link is down + * + * Returns: + * 0: success + * 1: no YUKON copper + * 2: test in progress + */ +int SkGmCableDiagStatus( +SK_AC *pAC, /* adapter context */ +SK_IOC IoC, /* IO context */ +int Port, /* Port Index (MAC_1 + n) */ +SK_BOOL StartTest) /* flag for start / get result */ +{ + int i; + SK_U16 RegVal; + SK_GEPORT *pPrt; + + pPrt = &pAC->GIni.GP[Port]; + + if (pPrt->PhyType != SK_PHY_MARV_COPPER) { + + return(1); + } + + if (StartTest) { + /* only start the cable test */ + if ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4) { + /* apply TDR workaround from Marvell */ + SkGmPhyWrite(pAC, IoC, Port, 29, 0x001e); + + SkGmPhyWrite(pAC, IoC, Port, 30, 0xcc00); + SkGmPhyWrite(pAC, IoC, Port, 30, 0xc800); + SkGmPhyWrite(pAC, IoC, Port, 30, 0xc400); + SkGmPhyWrite(pAC, IoC, Port, 30, 0xc000); + SkGmPhyWrite(pAC, IoC, Port, 30, 0xc100); + } + + /* set address to 0 for MDI[0] */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0); + + /* Read Cable Diagnostic Reg */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal); + + /* start Cable Diagnostic Test */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, + (SK_U16)(RegVal | PHY_M_CABD_ENA_TEST)); + + return(0); + } + + /* Read Cable Diagnostic Reg */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal); + + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL, + ("PHY Cable Diag.=0x%04X\n", RegVal)); + + if ((RegVal & PHY_M_CABD_ENA_TEST) != 0) { + /* test is running */ + return(2); + } + + /* get the test results */ + for (i = 0; i < 4; i++) { + /* set address to i for MDI[i] */ + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i); + + /* get Cable Diagnostic values */ + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal); + + pPrt->PMdiPairLen[i] = (SK_U8)(RegVal & PHY_M_CABD_DIST_MSK); + + pPrt->PMdiPairSts[i] = (SK_U8)((RegVal & PHY_M_CABD_STAT_MSK) >> 13); + } + + return(0); +} /* SkGmCableDiagStatus */ + +#endif /* CONFIG_SK98 */ + +/* End of file */ diff --git a/drivers/sk98lin/u-boot_compat.h b/drivers/sk98lin/u-boot_compat.h new file mode 100644 index 000000000..1e385f8ef --- /dev/null +++ b/drivers/sk98lin/u-boot_compat.h @@ -0,0 +1,98 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _UBOOT_COMPAT_H__ +#define _UBOOT_COMPAT_H__ + + +#include +#include +#include +#include +#include + +#define __initdata +#define __init +#define __exit + +#define netif_stop_queue(x) +#define netif_wake_queue(x) +#define netif_running(x) 0 +#define unregister_netdev(x) +#define remove_proc_entry(x,y) + +#define dev_addr enetaddr + +#define spin_lock_irqsave(x,y) y = 0; +#define spin_lock_init(x) +#define spin_lock(x) +#define spin_unlock_irqrestore(x,y) +#define spin_unlock(x) + + +#define ENODEV 1 +#define EAGAIN 2 +#define EBUSY 3 + +#define HZ CFG_HZ + + +#define printk printf +#define KERN_ERR +#define KERN_WARNING +#define KERN_INFO + +#define MOD_INC_USE_COUNT +#define MOD_DEC_USE_COUNT + + +#define kmalloc(x,y) malloc(x) +#define kfree(x) free(x) +#define GFP_ATOMIC 0 + +#define pci_alloc_consistent(x,y,z) (void *)(*(dma_addr_t *)(z) = (dma_addr_t)malloc(y)) +#define pci_free_consistent(x,y,z,d) free(z) +#define pci_dma_sync_single(x,y,z,d) +#define pci_unmap_page(x,y,z,d) +#define pci_unmap_single(x,y,z,d) +#define pci_present() 1 + +struct sk_buff +{ + u8 * data; + u32 len; + u8 * data_unaligned; +}; + +struct sk_buff * alloc_skb(u32 size, int dummy); +void dev_kfree_skb_any(struct sk_buff *skb); +void skb_reserve(struct sk_buff *skb, unsigned int len); +void skb_put(struct sk_buff *skb, unsigned int len); + +#define dev_kfree_skb dev_kfree_skb_any +#define dev_kfree_skb_irq dev_kfree_skb_any + +#define eth_copy_and_sum(dest,src,len,base) memcpy(dest->data,src,len); + + +#endif /* _UBOOT_COMPAT_H__ */ diff --git a/drivers/sk98lin/uboot_drv.c b/drivers/sk98lin/uboot_drv.c new file mode 100644 index 000000000..263dac810 --- /dev/null +++ b/drivers/sk98lin/uboot_drv.c @@ -0,0 +1,143 @@ +/* + * Driver for SysKonnect Gigabit Ethernet Server Adapters. + * + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_SK98) + +#include "h/skdrv1st.h" +#include "h/skdrv2nd.h" +#include "u-boot_compat.h" + + +#define SKGE_MAX_CARDS 2 + + +extern int skge_probe(struct eth_device **); +extern void SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs); +extern void SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs); +extern int SkGeOpen(struct eth_device *); +extern int SkGeClose(struct eth_device *); +extern int SkGeXmit(struct sk_buff *skb, struct eth_device *dev); +extern void ReceiveIrq(SK_AC *pAC, RX_PORT *pRxPort, SK_BOOL SlowPathLock); + +static int skge_init(struct eth_device *dev, bd_t * bis); +static int skge_send(struct eth_device *dev, volatile void *packet, int length); +static int skge_recv(struct eth_device *dev); +static void skge_halt(struct eth_device *dev); + +int skge_initialize(bd_t * bis) +{ + int numdev, i; + struct eth_device *dev[SKGE_MAX_CARDS]; + + numdev = skge_probe(&dev[0]); + + if (numdev > SKGE_MAX_CARDS) + { + printf("ERROR: numdev > SKGE_MAX_CARDS\n"); + } + + for (i = 0; i < numdev; i++) + { + sprintf (dev[i]->name, "SK98#%d", i); + + dev[i]->init = skge_init; + dev[i]->halt = skge_halt; + dev[i]->send = skge_send; + dev[i]->recv = skge_recv; + + eth_register(dev[i]); + } + + return numdev; +} + + +static int skge_init(struct eth_device *dev, bd_t * bis) +{ + int ret; + SK_AC * pAC = ((DEV_NET*)dev->priv)->pAC; + int i; + + ret = SkGeOpen(dev); + + while (pAC->Rlmt.Port[0].PortState != SK_RLMT_PS_GOING_UP) + { + SkGeIsrOnePort (0, pAC->dev[0], 0); + } + + for (i = 0; i < 100; i ++) + { + udelay(1000); + } + + return ret; +} + + +static void skge_halt(struct eth_device *dev) +{ + SkGeClose(dev); +} + + +static int skge_send(struct eth_device *dev, volatile void *packet, + int length) +{ + int ret = -1; + struct sk_buff * skb = alloc_skb(length, 0); + + if (! skb) + { + printf("skge_send: failed to alloc skb\n"); + goto Done; + } + + memcpy(skb->data, (void*)packet, length); + ret = SkGeXmit(skb, dev); + +Done: + return ret; +} + + +static int skge_recv(struct eth_device *dev) +{ + DEV_NET *pNet; + SK_AC *pAC; + int FromPort = 0; + + pNet = (DEV_NET*) dev->priv; + pAC = pNet->pAC; + + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); + + return 0; +} + + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sk98lin/uboot_skb.c b/drivers/sk98lin/uboot_skb.c new file mode 100644 index 000000000..3a487a8e3 --- /dev/null +++ b/drivers/sk98lin/uboot_skb.c @@ -0,0 +1,122 @@ +/* + * Definitions for the 'struct sk_buff' memory handlers in U-Boot. + * + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_SK98 + +#include +#include "u-boot_compat.h" + +#define MAX_SKB 50 + +static struct sk_buff *sk_table[MAX_SKB]; + + +struct sk_buff * alloc_skb(u32 size, int dummy) +{ + int i; + struct sk_buff * ret = NULL; + + for (i = 0; i < MAX_SKB; i++) + { + if (sk_table[i]) + { + /* Already allocated. + */ + continue; + } + + sk_table[i] = malloc(sizeof(struct sk_buff)); + if (! sk_table[i]) + { + printf("alloc_skb: malloc failed\n"); + break; + } + + memset(sk_table[i], 0, sizeof(struct sk_buff)); + sk_table[i]->data = sk_table[i]->data_unaligned = + malloc(size + 16); + if (! sk_table[i]->data) + { + printf("alloc_skb: malloc failed\n"); + free(sk_table[i]); + sk_table[i] = NULL; + break; + } + + sk_table[i]->data += 16 - ((u32)sk_table[i]->data & 15); + sk_table[i]->len = size; + + break; + } + + if (i < MAX_SKB) + { + ret = sk_table[i]; + } + + if (! ret) + { + printf("Unable to allocate skb!\n"); + } + + return ret; +} + +void dev_kfree_skb_any(struct sk_buff *skb) +{ + int i; + + for (i = 0; i < MAX_SKB; i++) + { + if (sk_table[i] != skb) + { + continue; + } + + free(skb->data_unaligned); + free(skb); + sk_table[i] = NULL; + break; + } + + if (i == MAX_SKB) + { + printf("SKB allocation error!\n"); + } +} + +void skb_reserve(struct sk_buff *skb, unsigned int len) +{ + skb->data+=len; +} + +void skb_put(struct sk_buff *skb, unsigned int len) +{ + skb->len+=len; +} + +#endif /* CONFIG_SK98 */ diff --git a/drivers/sl811.h b/drivers/sl811.h new file mode 100644 index 000000000..c1f9f013b --- /dev/null +++ b/drivers/sl811.h @@ -0,0 +1,104 @@ +#ifndef __UBOOT_SL811_H +#define __UBOOT_SL811_H + +#undef SL811_DEBUG + +#ifdef SL811_DEBUG + #define PDEBUG(level, fmt, args...) \ + if (debug >= (level)) printf("[%s:%d] " fmt, \ + __PRETTY_FUNCTION__, __LINE__ , ## args) +#else + #define PDEBUG(level, fmt, args...) do {} while(0) +#endif + +/* Sl811 host control register */ +#define SL811_CTRL_A 0x00 +#define SL811_ADDR_A 0x01 +#define SL811_LEN_A 0x02 +#define SL811_STS_A 0x03 /* read */ +#define SL811_PIDEP_A 0x03 /* write */ +#define SL811_CNT_A 0x04 /* read */ +#define SL811_DEV_A 0x04 /* write */ +#define SL811_CTRL1 0x05 +#define SL811_INTR 0x06 +#define SL811_CTRL_B 0x08 +#define SL811_ADDR_B 0x09 +#define SL811_LEN_B 0x0A +#define SL811_STS_B 0x0B /* read */ +#define SL811_PIDEP_B 0x0B /* write */ +#define SL811_CNT_B 0x0C /* read */ +#define SL811_DEV_B 0x0C /* write */ +#define SL811_INTRSTS 0x0D /* write clears bitwise */ +#define SL811_HWREV 0x0E /* read */ +#define SL811_SOFLOW 0x0E /* write */ +#define SL811_SOFCNTDIV 0x0F /* read */ +#define SL811_CTRL2 0x0F /* write */ + +/* USB control register bits (addr 0x00 and addr 0x08) */ +#define SL811_USB_CTRL_ARM 0x01 +#define SL811_USB_CTRL_ENABLE 0x02 +#define SL811_USB_CTRL_DIR_OUT 0x04 +#define SL811_USB_CTRL_ISO 0x10 +#define SL811_USB_CTRL_SOF 0x20 +#define SL811_USB_CTRL_TOGGLE_1 0x40 +#define SL811_USB_CTRL_PREAMBLE 0x80 + +/* USB status register bits (addr 0x03 and addr 0x0B) */ +#define SL811_USB_STS_ACK 0x01 +#define SL811_USB_STS_ERROR 0x02 +#define SL811_USB_STS_TIMEOUT 0x04 +#define SL811_USB_STS_TOGGLE_1 0x08 +#define SL811_USB_STS_SETUP 0x10 +#define SL811_USB_STS_OVERFLOW 0x20 +#define SL811_USB_STS_NAK 0x40 +#define SL811_USB_STS_STALL 0x80 + +/* Control register 1 bits (addr 0x05) */ +#define SL811_CTRL1_SOF 0x01 +#define SL811_CTRL1_RESET 0x08 +#define SL811_CTRL1_JKSTATE 0x10 +#define SL811_CTRL1_SPEED_LOW 0x20 +#define SL811_CTRL1_SUSPEND 0x40 + +/* Interrut enable (addr 0x06) and interrupt status register bits (addr 0x0D) */ +#define SL811_INTR_DONE_A 0x01 +#define SL811_INTR_DONE_B 0x02 +#define SL811_INTR_SOF 0x10 +#define SL811_INTR_INSRMV 0x20 +#define SL811_INTR_DETECT 0x40 +#define SL811_INTR_NOTPRESENT 0x40 +#define SL811_INTR_SPEED_FULL 0x80 /* only in status reg */ + +/* HW rev and SOF lo register bits (addr 0x0E) */ +#define SL811_HWR_HWREV 0xF0 + +/* SOF counter and control reg 2 (addr 0x0F) */ +#define SL811_CTL2_SOFHI 0x3F +#define SL811_CTL2_DSWAP 0x40 +#define SL811_CTL2_HOST 0x80 + +/* Set up for 1-ms SOF time. */ +#define SL811_12M_LOW 0xE0 +#define SL811_12M_HI 0x2E + +#define SL811_DATA_START 0x10 +#define SL811_DATA_LIMIT 240 + +/* Requests: bRequest << 8 | bmRequestType */ +#define RH_GET_STATUS 0x0080 +#define RH_CLEAR_FEATURE 0x0100 +#define RH_SET_FEATURE 0x0300 +#define RH_SET_ADDRESS 0x0500 +#define RH_GET_DESCRIPTOR 0x0680 +#define RH_SET_DESCRIPTOR 0x0700 +#define RH_GET_CONFIGURATION 0x0880 +#define RH_SET_CONFIGURATION 0x0900 +#define RH_GET_STATE 0x0280 +#define RH_GET_INTERFACE 0x0A80 +#define RH_SET_INTERFACE 0x0B00 +#define RH_SYNC_FRAME 0x0C80 + + +#define PIDEP(pid, ep) (((pid) & 0x0f) << 4 | (ep)) + +#endif /* __UBOOT_SL811_H */ diff --git a/drivers/sl811_usb.c b/drivers/sl811_usb.c new file mode 100644 index 000000000..b0cdf0bc2 --- /dev/null +++ b/drivers/sl811_usb.c @@ -0,0 +1,737 @@ +/* + * (C) Copyright 2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This code is based on linux driver for sl811hs chip, source at + * drivers/usb/host/sl811.c: + * + * SL811 Host Controller Interface driver for USB. + * + * Copyright (c) 2003/06, Courage Co., Ltd. + * + * Based on: + * 1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap, + * Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, + * Adam Richter, Gregory P. Smith; + * 2.Original SL811 driver (hc_sl811.o) by Pei Liu + * 3.Rewrited as sl811.o by Yin Aihua + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#ifdef CONFIG_USB_SL811HS +#include +#include +#include "sl811.h" + +#include "../board/kup/common/kup.h" + +#ifdef __PPC__ +# define EIEIO __asm__ volatile ("eieio") +#else +# define EIEIO /* nothing */ +#endif + +#define SL811_ADR (0x50000000) +#define SL811_DAT (0x50000001) + +#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);}) + +#ifdef SL811_DEBUG +static int debug = 9; +#endif + +static int root_hub_devnum = 0; +static struct usb_port_status rh_status = { 0 };/* root hub port status */ + +static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, + void *data, int buf_len, struct devrequest *cmd); + +static void sl811_write (__u8 index, __u8 data) +{ + *(volatile unsigned char *) (SL811_ADR) = index; + EIEIO; + *(volatile unsigned char *) (SL811_DAT) = data; + EIEIO; +} + +static __u8 sl811_read (__u8 index) +{ + __u8 data; + + *(volatile unsigned char *) (SL811_ADR) = index; + EIEIO; + data = *(volatile unsigned char *) (SL811_DAT); + EIEIO; + return (data); +} + +/* + * Read consecutive bytes of data from the SL811H/SL11H buffer + */ +static void inline sl811_read_buf(__u8 offset, __u8 *buf, __u8 size) +{ + *(volatile unsigned char *) (SL811_ADR) = offset; + EIEIO; + while (size--) { + *buf++ = *(volatile unsigned char *) (SL811_DAT); + EIEIO; + } +} + +/* + * Write consecutive bytes of data to the SL811H/SL11H buffer + */ +static void inline sl811_write_buf(__u8 offset, __u8 *buf, __u8 size) +{ + *(volatile unsigned char *) (SL811_ADR) = offset; + EIEIO; + while (size--) { + *(volatile unsigned char *) (SL811_DAT) = *buf++; + EIEIO; + } +} + +int usb_init_kup4x (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + int i; + unsigned char tmp; + + memctl = &immap->im_memctl; + memctl->memc_or7 = 0xFFFF8726; + memctl->memc_br7 = 0x50000401; /* start at 0x50000000 */ + /* BP 14 low = USB ON */ + immap->im_cpm.cp_pbdat &= ~(BP_USB_VCC); + /* PB 14 nomal port */ + immap->im_cpm.cp_pbpar &= ~(BP_USB_VCC); + /* output */ + immap->im_cpm.cp_pbdir |= (BP_USB_VCC); + + puts ("USB: "); + + for (i = 0x10; i < 0xff; i++) { + sl811_write(i, i); + tmp = (sl811_read(i)); + if (tmp != i) { + printf ("SL811 compare error index=0x%02x read=0x%02x\n", i, tmp); + return (-1); + } + } + printf ("SL811 ready\n"); + return (0); +} + +/* + * This function resets SL811HS controller and detects the speed of + * the connecting device + * + * Return: 0 = no device attached; 1 = USB device attached + */ +static int sl811_hc_reset(void) +{ + int status ; + + sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_12M_HI); + sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); + + mdelay(20); + + /* Disable hardware SOF generation, clear all irq status. */ + sl811_write(SL811_CTRL1, 0); + mdelay(2); + sl811_write(SL811_INTRSTS, 0xff); + status = sl811_read(SL811_INTRSTS); + + if (status & SL811_INTR_NOTPRESENT) { + /* Device is not present */ + PDEBUG(0, "Device not present\n"); + rh_status.wPortStatus &= ~(USB_PORT_STAT_CONNECTION | USB_PORT_STAT_ENABLE); + rh_status.wPortChange |= USB_PORT_STAT_C_CONNECTION; + sl811_write(SL811_INTR, SL811_INTR_INSRMV); + return 0; + } + + /* Send SOF to address 0, endpoint 0. */ + sl811_write(SL811_LEN_B, 0); + sl811_write(SL811_PIDEP_B, PIDEP(USB_PID_SOF, 0)); + sl811_write(SL811_DEV_B, 0x00); + sl811_write(SL811_SOFLOW, SL811_12M_LOW); + + if (status & SL811_INTR_SPEED_FULL) { + /* full speed device connect directly to root hub */ + PDEBUG (0, "Full speed Device attached\n"); + + sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); + mdelay(20); + sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_12M_HI); + sl811_write(SL811_CTRL1, SL811_CTRL1_SOF); + + /* start the SOF or EOP */ + sl811_write(SL811_CTRL_B, SL811_USB_CTRL_ARM); + rh_status.wPortStatus |= USB_PORT_STAT_CONNECTION; + rh_status.wPortStatus &= ~USB_PORT_STAT_LOW_SPEED; + mdelay(2); + sl811_write(SL811_INTRSTS, 0xff); + } else { + /* slow speed device connect directly to root-hub */ + PDEBUG(0, "Low speed Device attached\n"); + + sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); + mdelay(20); + sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_CTL2_DSWAP | SL811_12M_HI); + sl811_write(SL811_CTRL1, SL811_CTRL1_SPEED_LOW | SL811_CTRL1_SOF); + + /* start the SOF or EOP */ + sl811_write(SL811_CTRL_B, SL811_USB_CTRL_ARM); + rh_status.wPortStatus |= USB_PORT_STAT_CONNECTION | USB_PORT_STAT_LOW_SPEED; + mdelay(2); + sl811_write(SL811_INTRSTS, 0xff); + } + + rh_status.wPortChange |= USB_PORT_STAT_C_CONNECTION; + sl811_write(SL811_INTR, /*SL811_INTR_INSRMV*/SL811_INTR_DONE_A); + + return 1; +} + +int usb_lowlevel_init(void) +{ + root_hub_devnum = 0; + sl811_hc_reset(); + return 0; +} + +int usb_lowlevel_stop(void) +{ + sl811_hc_reset(); + return 0; +} + +static int calc_needed_buswidth(int bytes, int need_preamble) +{ + return !need_preamble ? bytes * 8 + 256 : 8 * 8 * bytes + 2048; +} + +static int sl811_send_packet(struct usb_device *dev, unsigned long pipe, __u8 *buffer, int len) +{ + __u8 ctrl = SL811_USB_CTRL_ARM | SL811_USB_CTRL_ENABLE; + __u16 status = 0; + int err = 0, time_start = get_timer(0); + int need_preamble = !(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) && + usb_pipeslow(pipe); + + if (len > 239) + return -1; + + if (usb_pipeout(pipe)) + ctrl |= SL811_USB_CTRL_DIR_OUT; + if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) + ctrl |= SL811_USB_CTRL_TOGGLE_1; + if (need_preamble) + ctrl |= SL811_USB_CTRL_PREAMBLE; + + sl811_write(SL811_INTRSTS, 0xff); + + while (err < 3) { + sl811_write(SL811_ADDR_A, 0x10); + sl811_write(SL811_LEN_A, len); + if (usb_pipeout(pipe) && len) + sl811_write_buf(0x10, buffer, len); + + if (!(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) && + sl811_read(SL811_SOFCNTDIV)*64 < calc_needed_buswidth(len, need_preamble)) + ctrl |= SL811_USB_CTRL_SOF; + else + ctrl &= ~SL811_USB_CTRL_SOF; + + sl811_write(SL811_CTRL_A, ctrl); + while (!(sl811_read(SL811_INTRSTS) & SL811_INTR_DONE_A)) { + if (5*CFG_HZ < get_timer(time_start)) { + printf("USB transmit timed out\n"); + return -USB_ST_CRC_ERR; + } + } + + sl811_write(SL811_INTRSTS, 0xff); + status = sl811_read(SL811_STS_A); + + if (status & SL811_USB_STS_ACK) { + int remainder = sl811_read(SL811_CNT_A); + if (remainder) { + PDEBUG(0, "usb transfer remainder = %d\n", remainder); + len -= remainder; + } + if (usb_pipein(pipe) && len) + sl811_read_buf(0x10, buffer, len); + return len; + } + + if ((status & SL811_USB_STS_NAK) == SL811_USB_STS_NAK) + continue; + + PDEBUG(0, "usb transfer error %#x\n", (int)status); + err++; + } + + err = 0; + + if (status & SL811_USB_STS_ERROR) + err |= USB_ST_BUF_ERR; + if (status & SL811_USB_STS_TIMEOUT) + err |= USB_ST_CRC_ERR; + if (status & SL811_USB_STS_STALL) + err |= USB_ST_STALLED; + + return -err; +} + +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len) +{ + int dir_out = usb_pipeout(pipe); + int ep = usb_pipeendpoint(pipe); + int max = usb_maxpacket(dev, pipe); + int done = 0; + + PDEBUG(7, "dev = %ld pipe = %ld buf = %p size = %d dir_out = %d\n", + usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out); + + dev->status = 0; + + sl811_write(SL811_DEV_A, usb_pipedevice(pipe)); + sl811_write(SL811_PIDEP_A, PIDEP(!dir_out ? USB_PID_IN : USB_PID_OUT, ep)); + while (done < len) { + int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done, + max > len - done ? len - done : max); + if (res < 0) { + dev->status = -res; + return res; + } + + if (!dir_out && res < max) /* short packet */ + break; + + done += res; + usb_dotoggle(dev, ep, dir_out); + } + + dev->act_len = done; + + return 0; +} + +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len,struct devrequest *setup) +{ + int done = 0; + int devnum = usb_pipedevice(pipe); + int ep = usb_pipeendpoint(pipe); + + dev->status = 0; + + if (devnum == root_hub_devnum) + return sl811_rh_submit_urb(dev, pipe, buffer, len, setup); + + PDEBUG(7, "dev = %d pipe = %ld buf = %p size = %d rt = %#x req = %#x bus = %i\n", + devnum, ep, buffer, len, (int)setup->requesttype, + (int)setup->request, sl811_read(SL811_SOFCNTDIV)*64); + + sl811_write(SL811_DEV_A, devnum); + sl811_write(SL811_PIDEP_A, PIDEP(USB_PID_SETUP, ep)); + /* setup phase */ + usb_settoggle(dev, ep, 1, 0); + if (sl811_send_packet(dev, usb_sndctrlpipe(dev, ep), + (__u8*)setup, sizeof(*setup)) == sizeof(*setup)) { + int dir_in = usb_pipein(pipe); + int max = usb_maxpacket(dev, pipe); + + /* data phase */ + sl811_write(SL811_PIDEP_A, + PIDEP(dir_in ? USB_PID_IN : USB_PID_OUT, ep)); + usb_settoggle(dev, ep, usb_pipeout(pipe), 1); + while (done < len) { + int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done, + max > len - done ? len - done : max); + if (res < 0) { + PDEBUG(0, "status data failed!\n"); + dev->status = -res; + return 0; + } + done += res; + usb_dotoggle(dev, ep, usb_pipeout(pipe)); + if (dir_in && res < max) /* short packet */ + break; + } + + /* status phase */ + sl811_write(SL811_PIDEP_A, + PIDEP(!dir_in ? USB_PID_IN : USB_PID_OUT, ep)); + usb_settoggle(dev, ep, !usb_pipeout(pipe), 1); + if (sl811_send_packet(dev, + !dir_in ? usb_rcvctrlpipe(dev, ep) : + usb_sndctrlpipe(dev, ep), + 0, 0) < 0) { + PDEBUG(0, "status phase failed!\n"); + dev->status = -1; + } + } else { + PDEBUG(0, "setup phase failed!\n"); + dev->status = -1; + } + + dev->act_len = done; + + return done; +} + +int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, int interval) +{ + PDEBUG(0, "dev = %p pipe = %#lx buf = %p size = %d int = %d\n", dev, pipe, + buffer, len, interval); + return -1; +} + +/* + * SL811 Virtual Root Hub + */ + +/* Device descriptor */ +static __u8 sl811_rh_dev_des[] = +{ + 0x12, /* __u8 bLength; */ + 0x01, /* __u8 bDescriptorType; Device */ + 0x10, /* __u16 bcdUSB; v1.1 */ + 0x01, + 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ + 0x00, /* __u8 bDeviceSubClass; */ + 0x00, /* __u8 bDeviceProtocol; */ + 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ + 0x00, /* __u16 idVendor; */ + 0x00, + 0x00, /* __u16 idProduct; */ + 0x00, + 0x00, /* __u16 bcdDevice; */ + 0x00, + 0x00, /* __u8 iManufacturer; */ + 0x02, /* __u8 iProduct; */ + 0x01, /* __u8 iSerialNumber; */ + 0x01 /* __u8 bNumConfigurations; */ +}; + +/* Configuration descriptor */ +static __u8 sl811_rh_config_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x02, /* __u8 bDescriptorType; Configuration */ + 0x19, /* __u16 wTotalLength; */ + 0x00, + 0x01, /* __u8 bNumInterfaces; */ + 0x01, /* __u8 bConfigurationValue; */ + 0x00, /* __u8 iConfiguration; */ + 0x40, /* __u8 bmAttributes; + Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, + 4..0: resvd */ + 0x00, /* __u8 MaxPower; */ + + /* interface */ + 0x09, /* __u8 if_bLength; */ + 0x04, /* __u8 if_bDescriptorType; Interface */ + 0x00, /* __u8 if_bInterfaceNumber; */ + 0x00, /* __u8 if_bAlternateSetting; */ + 0x01, /* __u8 if_bNumEndpoints; */ + 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ + 0x00, /* __u8 if_bInterfaceSubClass; */ + 0x00, /* __u8 if_bInterfaceProtocol; */ + 0x00, /* __u8 if_iInterface; */ + + /* endpoint */ + 0x07, /* __u8 ep_bLength; */ + 0x05, /* __u8 ep_bDescriptorType; Endpoint */ + 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ + 0x03, /* __u8 ep_bmAttributes; Interrupt */ + 0x08, /* __u16 ep_wMaxPacketSize; */ + 0x00, + 0xff /* __u8 ep_bInterval; 255 ms */ +}; + +/* root hub class descriptor*/ +static __u8 sl811_rh_hub_des[] = +{ + 0x09, /* __u8 bLength; */ + 0x29, /* __u8 bDescriptorType; Hub-descriptor */ + 0x01, /* __u8 bNbrPorts; */ + 0x00, /* __u16 wHubCharacteristics; */ + 0x00, + 0x50, /* __u8 bPwrOn2pwrGood; 2ms */ + 0x00, /* __u8 bHubContrCurrent; 0 mA */ + 0xfc, /* __u8 DeviceRemovable; *** 7 Ports max *** */ + 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ +}; + +/* + * helper routine for returning string descriptors in UTF-16LE + * input can actually be ISO-8859-1; ASCII is its 7-bit subset + */ +static int ascii2utf (char *s, u8 *utf, int utfmax) +{ + int retval; + + for (retval = 0; *s && utfmax > 1; utfmax -= 2, retval += 2) { + *utf++ = *s++; + *utf++ = 0; + } + return retval; +} + +/* + * root_hub_string is used by each host controller's root hub code, + * so that they're identified consistently throughout the system. + */ +static int usb_root_hub_string (int id, int serial, char *type, __u8 *data, int len) +{ + char buf [30]; + + /* assert (len > (2 * (sizeof (buf) + 1))); + assert (strlen (type) <= 8);*/ + + /* language ids */ + if (id == 0) { + *data++ = 4; *data++ = 3; /* 4 bytes data */ + *data++ = 0; *data++ = 0; /* some language id */ + return 4; + + /* serial number */ + } else if (id == 1) { + sprintf (buf, "%#x", serial); + + /* product description */ + } else if (id == 2) { + sprintf (buf, "USB %s Root Hub", type); + + /* id 3 == vendor description */ + + /* unsupported IDs --> "stall" */ + } else + return 0; + + ascii2utf (buf, data + 2, len - 2); + data [0] = 2 + strlen(buf) * 2; + data [1] = 3; + return data [0]; +} + +/* helper macro */ +#define OK(x) len = (x); break + +/* + * This function handles all USB request to the the virtual root hub + */ +static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, + void *data, int buf_len, struct devrequest *cmd) +{ + __u8 data_buf[16]; + __u8 *bufp = data_buf; + int len = 0; + int status = 0; + + __u16 bmRType_bReq; + __u16 wValue; + __u16 wIndex; + __u16 wLength; + + if (usb_pipeint(pipe)) { + PDEBUG(0, "interrupt transfer unimplemented!\n"); + return 0; + } + + bmRType_bReq = cmd->requesttype | (cmd->request << 8); + wValue = le16_to_cpu (cmd->value); + wIndex = le16_to_cpu (cmd->index); + wLength = le16_to_cpu (cmd->length); + + PDEBUG(5, "submit rh urb, req = %d(%x) val = %#x index = %#x len=%d\n", + bmRType_bReq, bmRType_bReq, wValue, wIndex, wLength); + + /* Request Destination: + without flags: Device, + USB_RECIP_INTERFACE: interface, + USB_RECIP_ENDPOINT: endpoint, + USB_TYPE_CLASS means HUB here, + USB_RECIP_OTHER | USB_TYPE_CLASS almost ever means HUB_PORT here + */ + switch (bmRType_bReq) { + case RH_GET_STATUS: + *(__u16 *)bufp = cpu_to_le16(1); + OK(2); + + case RH_GET_STATUS | USB_RECIP_INTERFACE: + *(__u16 *)bufp = cpu_to_le16(0); + OK(2); + + case RH_GET_STATUS | USB_RECIP_ENDPOINT: + *(__u16 *)bufp = cpu_to_le16(0); + OK(2); + + case RH_GET_STATUS | USB_TYPE_CLASS: + *(__u32 *)bufp = cpu_to_le32(0); + OK(4); + + case RH_GET_STATUS | USB_RECIP_OTHER | USB_TYPE_CLASS: + *(__u32 *)bufp = cpu_to_le32(rh_status.wPortChange<<16 | rh_status.wPortStatus); + OK(4); + + case RH_CLEAR_FEATURE | USB_RECIP_ENDPOINT: + switch (wValue) { + case 1: + OK(0); + } + break; + + case RH_CLEAR_FEATURE | USB_TYPE_CLASS: + switch (wValue) { + case C_HUB_LOCAL_POWER: + OK(0); + + case C_HUB_OVER_CURRENT: + OK(0); + } + break; + + case RH_CLEAR_FEATURE | USB_RECIP_OTHER | USB_TYPE_CLASS: + switch (wValue) { + case USB_PORT_FEAT_ENABLE: + rh_status.wPortStatus &= ~USB_PORT_STAT_ENABLE; + OK(0); + + case USB_PORT_FEAT_SUSPEND: + rh_status.wPortStatus &= ~USB_PORT_STAT_SUSPEND; + OK(0); + + case USB_PORT_FEAT_POWER: + rh_status.wPortStatus &= ~USB_PORT_STAT_POWER; + OK(0); + + case USB_PORT_FEAT_C_CONNECTION: + rh_status.wPortChange &= ~USB_PORT_STAT_C_CONNECTION; + OK(0); + + case USB_PORT_FEAT_C_ENABLE: + rh_status.wPortChange &= ~USB_PORT_STAT_C_ENABLE; + OK(0); + + case USB_PORT_FEAT_C_SUSPEND: + rh_status.wPortChange &= ~USB_PORT_STAT_C_SUSPEND; + OK(0); + + case USB_PORT_FEAT_C_OVER_CURRENT: + rh_status.wPortChange &= ~USB_PORT_STAT_C_OVERCURRENT; + OK(0); + + case USB_PORT_FEAT_C_RESET: + rh_status.wPortChange &= ~USB_PORT_STAT_C_RESET; + OK(0); + } + break; + + case RH_SET_FEATURE | USB_RECIP_OTHER | USB_TYPE_CLASS: + switch (wValue) { + case USB_PORT_FEAT_SUSPEND: + rh_status.wPortStatus |= USB_PORT_STAT_SUSPEND; + OK(0); + + case USB_PORT_FEAT_RESET: + rh_status.wPortStatus |= USB_PORT_STAT_RESET; + rh_status.wPortChange = 0; + rh_status.wPortChange |= USB_PORT_STAT_C_RESET; + rh_status.wPortStatus &= ~USB_PORT_STAT_RESET; + rh_status.wPortStatus |= USB_PORT_STAT_ENABLE; + OK(0); + + case USB_PORT_FEAT_POWER: + rh_status.wPortStatus |= USB_PORT_STAT_POWER; + OK(0); + + case USB_PORT_FEAT_ENABLE: + rh_status.wPortStatus |= USB_PORT_STAT_ENABLE; + OK(0); + } + break; + + case RH_SET_ADDRESS: + root_hub_devnum = wValue; + OK(0); + + case RH_GET_DESCRIPTOR: + switch ((wValue & 0xff00) >> 8) { + case USB_DT_DEVICE: + len = sizeof(sl811_rh_dev_des); + bufp = sl811_rh_dev_des; + OK(len); + + case USB_DT_CONFIG: + len = sizeof(sl811_rh_config_des); + bufp = sl811_rh_config_des; + OK(len); + + case USB_DT_STRING: + len = usb_root_hub_string(wValue & 0xff, (int)(long)0, "SL811HS", data, wLength); + if (len > 0) { + bufp = data; + OK(len); + } + + default: + status = -32; + } + break; + + case RH_GET_DESCRIPTOR | USB_TYPE_CLASS: + len = sizeof(sl811_rh_hub_des); + bufp = sl811_rh_hub_des; + OK(len); + + case RH_GET_CONFIGURATION: + bufp[0] = 0x01; + OK(1); + + case RH_SET_CONFIGURATION: + OK(0); + + default: + PDEBUG(1, "unsupported root hub command\n"); + status = -32; + } + + len = min(len, buf_len); + if (data != bufp) + memcpy(data, bufp, len); + + PDEBUG(5, "len = %d, status = %d\n", len, status); + + usb_dev->status = status; + usb_dev->act_len = len; + + return status == 0 ? len : status; +} + +#endif /* CONFIG_USB_SL811HS */ diff --git a/drivers/sm501.c b/drivers/sm501.c new file mode 100644 index 000000000..23db02cd1 --- /dev/null +++ b/drivers/sm501.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2002 + * Stäubli Faverges - + * Pierre AUBERT p.aubert@staubli.com + * + * (C) Copyright 2005 + * Martin Krause TQ-Systems GmbH martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Basic video support for SMI SM501 "Voyager" graphic controller + */ + +#include + +#ifdef CONFIG_VIDEO_SM501 + +#include +#include + +#define read8(ptrReg) \ + *(volatile unsigned char *)(sm501.isaBase + ptrReg) + +#define write8(ptrReg,value) \ + *(volatile unsigned char *)(sm501.isaBase + ptrReg) = value + +#define read16(ptrReg) \ + (*(volatile unsigned short *)(sm501.isaBase + ptrReg)) + +#define write16(ptrReg,value) \ + (*(volatile unsigned short *)(sm501.isaBase + ptrReg) = value) + +#define read32(ptrReg) \ + (*(volatile unsigned int *)(sm501.isaBase + ptrReg)) + +#define write32(ptrReg, value) \ + (*(volatile unsigned int *)(sm501.isaBase + ptrReg) = value) + +GraphicDevice sm501; + +/*----------------------------------------------------------------------------- + * SmiSetRegs -- + *----------------------------------------------------------------------------- + */ +static void SmiSetRegs (void) +{ + /* + * The content of the chipset register depends on the board (clocks, + * ...) + */ + const SMI_REGS *preg = board_get_regs (); + while (preg->Index) { + write32 (preg->Index, preg->Value); + /* + * Insert a delay between + */ + udelay (1000); + preg ++; + } +} + +/*----------------------------------------------------------------------------- + * video_hw_init -- + *----------------------------------------------------------------------------- + */ +void *video_hw_init (void) +{ + unsigned int *vm, i; + + memset (&sm501, 0, sizeof (GraphicDevice)); + + /* + * Initialization of the access to the graphic chipset Retreive base + * address of the chipset (see board/RPXClassic/eccx.c) + */ + if ((sm501.isaBase = board_video_init ()) == 0) { + return (NULL); + } + + if ((sm501.frameAdrs = board_video_get_fb ()) == 0) { + return (NULL); + } + + sm501.winSizeX = board_get_width (); + sm501.winSizeY = board_get_height (); + +#if defined(CONFIG_VIDEO_SM501_8BPP) + sm501.gdfIndex = GDF__8BIT_INDEX; + sm501.gdfBytesPP = 1; + +#elif defined(CONFIG_VIDEO_SM501_16BPP) + sm501.gdfIndex = GDF_16BIT_565RGB; + sm501.gdfBytesPP = 2; + +#elif defined(CONFIG_VIDEO_SM501_32BPP) + sm501.gdfIndex = GDF_32BIT_X888RGB; + sm501.gdfBytesPP = 4; +#else +#error Unsupported SM501 BPP +#endif + + sm501.memSize = sm501.winSizeX * sm501.winSizeY * sm501.gdfBytesPP; + + /* Load Smi registers */ + SmiSetRegs (); + + /* (see board/RPXClassic/RPXClassic.c) */ + board_validate_screen (sm501.isaBase); + + /* Clear video memory */ + i = sm501.memSize/4; + vm = (unsigned int *)sm501.frameAdrs; + while(i--) + *vm++ = 0; + + return (&sm501); +} + +/*----------------------------------------------------------------------------- + * video_set_lut -- + *----------------------------------------------------------------------------- + */ +void video_set_lut ( + unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ +} + +#endif /* CONFIG_VIDEO_SM501 */ diff --git a/drivers/smc91111.c b/drivers/smc91111.c new file mode 100644 index 000000000..f91e4b984 --- /dev/null +++ b/drivers/smc91111.c @@ -0,0 +1,1623 @@ +/*------------------------------------------------------------------------ + . smc91111.c + . This is a driver for SMSC's 91C111 single-chip Ethernet device. + . + . (C) Copyright 2002 + . Sysgo Real-Time Solutions, GmbH + . Rolf Offermanns + . + . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + . Developed by Simple Network Magic Corporation (SNMC) + . Copyright (C) 1996 by Erik Stahlman (ES) + . + . This program is free software; you can redistribute it and/or modify + . it under the terms of the GNU General Public License as published by + . the Free Software Foundation; either version 2 of the License, or + . (at your option) any later version. + . + . This program is distributed in the hope that it will be useful, + . but WITHOUT ANY WARRANTY; without even the implied warranty of + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + . GNU General Public License for more details. + . + . You should have received a copy of the GNU General Public License + . along with this program; if not, write to the Free Software + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + . + . Information contained in this file was obtained from the LAN91C111 + . manual from SMC. To get a copy, if you really want one, you can find + . information under www.smsc.com. + . + . + . "Features" of the SMC chip: + . Integrated PHY/MAC for 10/100BaseT Operation + . Supports internal and external MII + . Integrated 8K packet memory + . EEPROM interface for configuration + . + . Arguments: + . io = for the base address + . irq = for the IRQ + . + . author: + . Erik Stahlman ( erik@vt.edu ) + . Daris A Nevil ( dnevil@snmc.com ) + . + . + . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) + . + . Sources: + . o SMSC LAN91C111 databook (www.smsc.com) + . o smc9194.c by Erik Stahlman + . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) + . + . History: + . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. + . 10/17/01 Marco Hasewinkel Modify for DNP/1110 + . 07/25/01 Woojung Huh Modify for ADS Bitsy + . 04/25/01 Daris A Nevil Initial public release through SMSC + . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 + ----------------------------------------------------------------------------*/ + +#include +#include +#include +#include "smc91111.h" +#include + +#ifdef CONFIG_DRIVER_SMC91111 + +/* Use power-down feature of the chip */ +#define POWER_DOWN 0 + +#define NO_AUTOPROBE + +#define SMC_DEBUG 0 + +#if SMC_DEBUG > 1 +static const char version[] = + "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; +#endif + +/* Autonegotiation timeout in seconds */ +#ifndef CONFIG_SMC_AUTONEG_TIMEOUT +#define CONFIG_SMC_AUTONEG_TIMEOUT 10 +#endif + +/*------------------------------------------------------------------------ + . + . Configuration options, for the experienced user to change. + . + -------------------------------------------------------------------------*/ + +/* + . Wait time for memory to be free. This probably shouldn't be + . tuned that much, as waiting for this means nothing else happens + . in the system +*/ +#define MEMORY_WAIT_TIME 16 + + +#if (SMC_DEBUG > 2 ) +#define PRINTK3(args...) printf(args) +#else +#define PRINTK3(args...) +#endif + +#if SMC_DEBUG > 1 +#define PRINTK2(args...) printf(args) +#else +#define PRINTK2(args...) +#endif + +#ifdef SMC_DEBUG +#define PRINTK(args...) printf(args) +#else +#define PRINTK(args...) +#endif + + +/*------------------------------------------------------------------------ + . + . The internal workings of the driver. If you are changing anything + . here with the SMC stuff, you should have the datasheet and know + . what you are doing. + . + -------------------------------------------------------------------------*/ +#define CARDNAME "LAN91C111" + +/* Memory sizing constant */ +#define LAN91C111_MEMORY_MULTIPLIER (1024*2) + +#ifndef CONFIG_SMC91111_BASE +#define CONFIG_SMC91111_BASE 0x20000300 +#endif + +#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE + +#define SMC_DEV_NAME "SMC91111" +#define SMC_PHY_ADDR 0x0000 +#define SMC_ALLOC_MAX_TRY 5 +#define SMC_TX_TIMEOUT 30 + +#define SMC_PHY_CLOCK_DELAY 1000 + +#define ETH_ZLEN 60 + +#ifdef CONFIG_SMC_USE_32_BIT +#define USE_32_BIT 1 +#else +#undef USE_32_BIT +#endif +/*----------------------------------------------------------------- + . + . The driver can be entered at any of the following entry points. + . + .------------------------------------------------------------------ */ + +extern int eth_init(bd_t *bd); +extern void eth_halt(void); +extern int eth_rx(void); +extern int eth_send(volatile void *packet, int length); + +#ifdef SHARED_RESOURCES + extern void swap_to(int device_id); +#endif + +/* + . This is called by register_netdev(). It is responsible for + . checking the portlist for the SMC9000 series chipset. If it finds + . one, then it will initialize the device, find the hardware information, + . and sets up the appropriate device parameters. + . NOTE: Interrupts are *OFF* when this procedure is called. + . + . NB:This shouldn't be static since it is referred to externally. +*/ +int smc_init(void); + +/* + . This is called by unregister_netdev(). It is responsible for + . cleaning up before the driver is finally unregistered and discarded. +*/ +void smc_destructor(void); + +/* + . The kernel calls this function when someone wants to use the device, + . typically 'ifconfig ethX up'. +*/ +static int smc_open(bd_t *bd); + + +/* + . This is called by the kernel in response to 'ifconfig ethX down'. It + . is responsible for cleaning up everything that the open routine + . does, and maybe putting the card into a powerdown state. +*/ +static int smc_close(void); + +/* + . Configures the PHY through the MII Management interface +*/ +#ifndef CONFIG_SMC91111_EXT_PHY +static void smc_phy_configure(void); +#endif /* !CONFIG_SMC91111_EXT_PHY */ + +/* + . This is a separate procedure to handle the receipt of a packet, to + . leave the interrupt code looking slightly cleaner +*/ +static int smc_rcv(void); + +/* See if a MAC address is defined in the current environment. If so use it. If not + . print a warning and set the environment and other globals with the default. + . If an EEPROM is present it really should be consulted. +*/ +int smc_get_ethaddr(bd_t *bd); +int get_rom_mac(uchar *v_rom_mac); + +/* + ------------------------------------------------------------ + . + . Internal routines + . + ------------------------------------------------------------ +*/ + +#ifdef CONFIG_SMC_USE_IOFUNCS +/* + * input and output functions + * + * Implemented due to inx,outx macros accessing the device improperly + * and putting the device into an unkown state. + * + * For instance, on Sharp LPD7A400 SDK, affects were chip memory + * could not be free'd (hence the alloc failures), duplicate packets, + * packets being corrupt (shifted) on the wire, etc. Switching to the + * inx,outx functions fixed this problem. + */ +static inline word SMC_inw(dword offset); +static inline void SMC_outw(word value, dword offset); +static inline byte SMC_inb(dword offset); +static inline void SMC_outb(byte value, dword offset); +static inline void SMC_insw(dword offset, volatile uchar* buf, dword len); +static inline void SMC_outsw(dword offset, uchar* buf, dword len); + +#define barrier() __asm__ __volatile__("": : :"memory") + +static inline word SMC_inw(dword offset) +{ + word v; + v = *((volatile word*)(SMC_BASE_ADDRESS+offset)); + barrier(); *(volatile u32*)(0xc0000000); + return v; +} + +static inline void SMC_outw(word value, dword offset) +{ + *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value; + barrier(); *(volatile u32*)(0xc0000000); +} + +static inline byte SMC_inb(dword offset) +{ + word _w; + + _w = SMC_inw(offset & ~((dword)1)); + return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); +} + +static inline void SMC_outb(byte value, dword offset) +{ + word _w; + + _w = SMC_inw(offset & ~((dword)1)); + if (offset & 1) + *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff); + else + *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00); +} + +static inline void SMC_insw(dword offset, volatile uchar* buf, dword len) +{ + volatile word *p = (volatile word *)buf; + + while (len-- > 0) { + *p++ = SMC_inw(offset); + barrier(); + *((volatile u32*)(0xc0000000)); + } +} + +static inline void SMC_outsw(dword offset, uchar* buf, dword len) +{ + volatile word *p = (volatile word *)buf; + + while (len-- > 0) { + SMC_outw(*p++, offset); + barrier(); + *(volatile u32*)(0xc0000000); + } +} +#endif /* CONFIG_SMC_USE_IOFUNCS */ + +static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8}; + +/* + * This function must be called before smc_open() if you want to override + * the default mac address. + */ + +void smc_set_mac_addr(const unsigned char *addr) { + int i; + + for (i=0; i < sizeof(smc_mac_addr); i++){ + smc_mac_addr[i] = addr[i]; + } +} + +/* + * smc_get_macaddr is no longer used. If you want to override the default + * mac address, call smc_get_mac_addr as a part of the board initialization. + */ + +#if 0 +void smc_get_macaddr( byte *addr ) { + /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ + unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); + int i; + + + for (i=0; i<6; i++) { + addr[0] = *(dnp1110_mac+0); + addr[1] = *(dnp1110_mac+1); + addr[2] = *(dnp1110_mac+2); + addr[3] = *(dnp1110_mac+3); + addr[4] = *(dnp1110_mac+4); + addr[5] = *(dnp1110_mac+5); + } +} +#endif /* 0 */ + +/*********************************************** + * Show available memory * + ***********************************************/ +void dump_memory_info(void) +{ + word mem_info; + word old_bank; + + old_bank = SMC_inw(BANK_SELECT)&0xF; + + SMC_SELECT_BANK(0); + mem_info = SMC_inw( MIR_REG ); + PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048); + + SMC_SELECT_BANK(old_bank); +} +/* + . A rather simple routine to print out a packet for debugging purposes. +*/ +#if SMC_DEBUG > 2 +static void print_packet( byte *, int ); +#endif + +#define tx_done(dev) 1 + + +/* this does a soft reset on the device */ +static void smc_reset( void ); + +/* Enable Interrupts, Receive, and Transmit */ +static void smc_enable( void ); + +/* this puts the device in an inactive state */ +static void smc_shutdown( void ); + +/* Routines to Read and Write the PHY Registers across the + MII Management Interface +*/ + +#ifndef CONFIG_SMC91111_EXT_PHY +static word smc_read_phy_register(byte phyreg); +static void smc_write_phy_register(byte phyreg, word phydata); +#endif /* !CONFIG_SMC91111_EXT_PHY */ + + +static int poll4int (byte mask, int timeout) +{ + int tmo = get_timer (0) + timeout * CFG_HZ; + int is_timeout = 0; + word old_bank = SMC_inw (BSR_REG); + + PRINTK2 ("Polling...\n"); + SMC_SELECT_BANK (2); + while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) { + if (get_timer (0) >= tmo) { + is_timeout = 1; + break; + } + } + + /* restore old bank selection */ + SMC_SELECT_BANK (old_bank); + + if (is_timeout) + return 1; + else + return 0; +} + +/* Only one release command at a time, please */ +static inline void smc_wait_mmu_release_complete (void) +{ + int count = 0; + + /* assume bank 2 selected */ + while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + udelay (1); /* Wait until not busy */ + if (++count > 200) + break; + } +} + +/* + . Function: smc_reset( void ) + . Purpose: + . This sets the SMC91111 chip to its normal state, hopefully from whatever + . mess that any other DOS driver has put it in. + . + . Maybe I should reset more registers to defaults in here? SOFTRST should + . do that for me. + . + . Method: + . 1. send a SOFT RESET + . 2. wait for it to finish + . 3. enable autorelease mode + . 4. reset the memory management unit + . 5. clear all interrupts + . +*/ +static void smc_reset (void) +{ + PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); + + /* This resets the registers mostly to defaults, but doesn't + affect EEPROM. That seems unnecessary */ + SMC_SELECT_BANK (0); + SMC_outw (RCR_SOFTRST, RCR_REG); + + /* Setup the Configuration Register */ + /* This is necessary because the CONFIG_REG is not affected */ + /* by a soft reset */ + + SMC_SELECT_BANK (1); +#if defined(CONFIG_SMC91111_EXT_PHY) + SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); +#else + SMC_outw (CONFIG_DEFAULT, CONFIG_REG); +#endif + + + /* Release from possible power-down state */ + /* Configuration register is not affected by Soft Reset */ + SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG); + + SMC_SELECT_BANK (0); + + /* this should pause enough for the chip to be happy */ + udelay (10); + + /* Disable transmit and receive functionality */ + SMC_outw (RCR_CLEAR, RCR_REG); + SMC_outw (TCR_CLEAR, TCR_REG); + + /* set the control register */ + SMC_SELECT_BANK (1); + SMC_outw (CTL_DEFAULT, CTL_REG); + + /* Reset the MMU */ + SMC_SELECT_BANK (2); + smc_wait_mmu_release_complete (); + SMC_outw (MC_RESET, MMU_CMD_REG); + while (SMC_inw (MMU_CMD_REG) & MC_BUSY) + udelay (1); /* Wait until not busy */ + + /* Note: It doesn't seem that waiting for the MMU busy is needed here, + but this is a place where future chipsets _COULD_ break. Be wary + of issuing another MMU command right after this */ + + /* Disable all interrupts */ + SMC_outb (0, IM_REG); +} + +/* + . Function: smc_enable + . Purpose: let the chip talk to the outside work + . Method: + . 1. Enable the transmitter + . 2. Enable the receiver + . 3. Enable interrupts +*/ +static void smc_enable() +{ + PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); + SMC_SELECT_BANK( 0 ); + /* see the header file for options in TCR/RCR DEFAULT*/ + SMC_outw( TCR_DEFAULT, TCR_REG ); + SMC_outw( RCR_DEFAULT, RCR_REG ); + + /* clear MII_DIS */ +/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ +} + +/* + . Function: smc_shutdown + . Purpose: closes down the SMC91xxx chip. + . Method: + . 1. zero the interrupt mask + . 2. clear the enable receive flag + . 3. clear the enable xmit flags + . + . TODO: + . (1) maybe utilize power down mode. + . Why not yet? Because while the chip will go into power down mode, + . the manual says that it will wake up in response to any I/O requests + . in the register space. Empirical results do not show this working. +*/ +static void smc_shutdown() +{ + PRINTK2(CARDNAME ": smc_shutdown\n"); + + /* no more interrupts for me */ + SMC_SELECT_BANK( 2 ); + SMC_outb( 0, IM_REG ); + + /* and tell the card to stay away from that nasty outside world */ + SMC_SELECT_BANK( 0 ); + SMC_outb( RCR_CLEAR, RCR_REG ); + SMC_outb( TCR_CLEAR, TCR_REG ); +#ifdef SHARED_RESOURCES + swap_to(FLASH); +#endif +} + + +/* + . Function: smc_hardware_send_packet(struct net_device * ) + . Purpose: + . This sends the actual packet to the SMC9xxx chip. + . + . Algorithm: + . First, see if a saved_skb is available. + . ( this should NOT be called if there is no 'saved_skb' + . Now, find the packet number that the chip allocated + . Point the data pointers at it in memory + . Set the length word in the chip's memory + . Dump the packet to chip memory + . Check if a last byte is needed ( odd length packet ) + . if so, set the control flag right + . Tell the card to send it + . Enable the transmit interrupt, so I know if it failed + . Free the kernel data if I actually sent it. +*/ +static int smc_send_packet (volatile void *packet, int packet_length) +{ + byte packet_no; + unsigned long ioaddr; + byte *buf; + int length; + int numPages; + int try = 0; + int time_out; + byte status; + byte saved_pnr; + word saved_ptr; + + /* save PTR and PNR registers before manipulation */ + SMC_SELECT_BANK (2); + saved_pnr = SMC_inb( PN_REG ); + saved_ptr = SMC_inw( PTR_REG ); + + PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); + + length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; + + /* allocate memory + ** The MMU wants the number of pages to be the number of 256 bytes + ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) + ** + ** The 91C111 ignores the size bits, but the code is left intact + ** for backwards and future compatibility. + ** + ** Pkt size for allocating is data length +6 (for additional status + ** words, length and ctl!) + ** + ** If odd size then last byte is included in this header. + */ + numPages = ((length & 0xfffe) + 6); + numPages >>= 8; /* Divide by 256 */ + + if (numPages > 7) { + printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); + return 0; + } + + /* now, try to allocate the memory */ + SMC_SELECT_BANK (2); + SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG); + + /* FIXME: the ALLOC_INT bit never gets set * + * so the following will always give a * + * memory allocation error. * + * same code works in armboot though * + * -ro + */ + +again: + try++; + time_out = MEMORY_WAIT_TIME; + do { + status = SMC_inb (SMC91111_INT_REG); + if (status & IM_ALLOC_INT) { + /* acknowledge the interrupt */ + SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG); + break; + } + } while (--time_out); + + if (!time_out) { + PRINTK2 ("%s: memory allocation, try %d failed ...\n", + SMC_DEV_NAME, try); + if (try < SMC_ALLOC_MAX_TRY) + goto again; + else + return 0; + } + + PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", + SMC_DEV_NAME, try); + + /* I can send the packet now.. */ + + ioaddr = SMC_BASE_ADDRESS; + + buf = (byte *) packet; + + /* If I get here, I _know_ there is a packet slot waiting for me */ + packet_no = SMC_inb (AR_REG); + if (packet_no & AR_FAILED) { + /* or isn't there? BAD CHIP! */ + printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); + return 0; + } + + /* we have a packet address, so tell the card to use it */ +#ifndef CONFIG_XAENIAX + SMC_outb (packet_no, PN_REG); +#else + /* On Xaeniax board, we can't use SMC_outb here because that way + * the Allocate MMU command will end up written to the command register + * as well, which will lead to a problem. + */ + SMC_outl (packet_no << 16, 0); +#endif + /* do not write new ptr value if Write data fifo not empty */ + while ( saved_ptr & PTR_NOTEMPTY ) + printf ("Write data fifo not empty!\n"); + + /* point to the beginning of the packet */ + SMC_outw (PTR_AUTOINC, PTR_REG); + + PRINTK3 ("%s: Trying to xmit packet of length %x\n", + SMC_DEV_NAME, length); + +#if SMC_DEBUG > 2 + printf ("Transmitting Packet\n"); + print_packet (buf, length); +#endif + + /* send the packet length ( +6 for status, length and ctl byte ) + and the status word ( set to zeros ) */ +#ifdef USE_32_BIT + SMC_outl ((length + 6) << 16, SMC91111_DATA_REG); +#else + SMC_outw (0, SMC91111_DATA_REG); + /* send the packet length ( +6 for status words, length, and ctl */ + SMC_outw ((length + 6), SMC91111_DATA_REG); +#endif + + /* send the actual data + . I _think_ it's faster to send the longs first, and then + . mop up by sending the last word. It depends heavily + . on alignment, at least on the 486. Maybe it would be + . a good idea to check which is optimal? But that could take + . almost as much time as is saved? + */ +#ifdef USE_32_BIT + SMC_outsl (SMC91111_DATA_REG, buf, length >> 2); +#ifndef CONFIG_XAENIAX + if (length & 0x2) + SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), + SMC91111_DATA_REG); +#else + /* On XANEIAX, we can only use 32-bit writes, so we need to handle + * unaligned tail part specially. The standard code doesn't work. + */ + if ((length & 3) == 3) { + u16 * ptr = (u16*) &buf[length-3]; + SMC_outl((*ptr) | ((0x2000 | buf[length-1]) << 16), + SMC91111_DATA_REG); + } else if ((length & 2) == 2) { + u16 * ptr = (u16*) &buf[length-2]; + SMC_outl(*ptr, SMC91111_DATA_REG); + } else if (length & 1) { + SMC_outl((0x2000 | buf[length-1]), SMC91111_DATA_REG); + } else { + SMC_outl(0, SMC91111_DATA_REG); + } +#endif +#else + SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1); +#endif /* USE_32_BIT */ + +#ifndef CONFIG_XAENIAX + /* Send the last byte, if there is one. */ + if ((length & 1) == 0) { + SMC_outw (0, SMC91111_DATA_REG); + } else { + SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG); + } +#endif + + /* and let the chipset deal with it */ + SMC_outw (MC_ENQUEUE, MMU_CMD_REG); + + /* poll for TX INT */ + /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */ + /* poll for TX_EMPTY INT - autorelease enabled */ + if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { + /* sending failed */ + PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); + + /* release packet */ + /* no need to release, MMU does that now */ +#ifdef CONFIG_XAENIAX + SMC_outw (MC_FREEPKT, MMU_CMD_REG); +#endif + + /* wait for MMU getting ready (low) */ + while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + udelay (10); + } + + PRINTK2 ("MMU ready\n"); + + + return 0; + } else { + /* ack. int */ + SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG); + /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ + PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, + length); + + /* release packet */ + /* no need to release, MMU does that now */ +#ifdef CONFIG_XAENIAX + SMC_outw (MC_FREEPKT, MMU_CMD_REG); +#endif + + /* wait for MMU getting ready (low) */ + while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + udelay (10); + } + + PRINTK2 ("MMU ready\n"); + + + } + + /* restore previously saved registers */ +#ifndef CONFIG_XAENIAX + SMC_outb( saved_pnr, PN_REG ); +#else + /* On Xaeniax board, we can't use SMC_outb here because that way + * the Allocate MMU command will end up written to the command register + * as well, which will lead to a problem. + */ + SMC_outl(saved_pnr << 16, 0); +#endif + SMC_outw( saved_ptr, PTR_REG ); + + return length; +} + +/*------------------------------------------------------------------------- + | + | smc_destructor( struct net_device * dev ) + | Input parameters: + | dev, pointer to the device structure + | + | Output: + | None. + | + --------------------------------------------------------------------------- +*/ +void smc_destructor() +{ + PRINTK2(CARDNAME ": smc_destructor\n"); +} + + +/* + * Open and Initialize the board + * + * Set up everything, reset the card, etc .. + * + */ +static int smc_open (bd_t * bd) +{ + int i, err; + + PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME); + + /* reset the hardware */ + smc_reset (); + smc_enable (); + + /* Configure the PHY */ +#ifndef CONFIG_SMC91111_EXT_PHY + smc_phy_configure (); +#endif + + /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ +/* SMC_SELECT_BANK(0); */ +/* SMC_outw(0, RPC_REG); */ + SMC_SELECT_BANK (1); + + err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */ + if (err < 0) { + memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */ + return (-1); /* upper code ignores this, but NOT bi_enetaddr */ + } +#ifdef USE_32_BIT + for (i = 0; i < 6; i += 2) { + word address; + + address = smc_mac_addr[i + 1] << 8; + address |= smc_mac_addr[i]; + SMC_outw (address, (ADDR0_REG + i)); + } +#else + for (i = 0; i < 6; i++) + SMC_outb (smc_mac_addr[i], (ADDR0_REG + i)); +#endif + + return 0; +} + +/*------------------------------------------------------------- + . + . smc_rcv - receive a packet from the card + . + . There is ( at least ) a packet waiting to be read from + . chip-memory. + . + . o Read the status + . o If an error, record it + . o otherwise, read in the packet + -------------------------------------------------------------- +*/ +static int smc_rcv() +{ + int packet_number; + word status; + word packet_length; + int is_error = 0; +#ifdef USE_32_BIT + dword stat_len; +#endif + byte saved_pnr; + word saved_ptr; + + SMC_SELECT_BANK(2); + /* save PTR and PTR registers */ + saved_pnr = SMC_inb( PN_REG ); + saved_ptr = SMC_inw( PTR_REG ); + + packet_number = SMC_inw( RXFIFO_REG ); + + if ( packet_number & RXFIFO_REMPTY ) { + + return 0; + } + + PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); + /* start reading from the start of the packet */ + SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); + + /* First two words are status and packet_length */ +#ifdef USE_32_BIT + stat_len = SMC_inl(SMC91111_DATA_REG); + status = stat_len & 0xffff; + packet_length = stat_len >> 16; +#else + status = SMC_inw( SMC91111_DATA_REG ); + packet_length = SMC_inw( SMC91111_DATA_REG ); +#endif + + packet_length &= 0x07ff; /* mask off top bits */ + + PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); + + if ( !(status & RS_ERRORS ) ){ + /* Adjust for having already read the first two words */ + packet_length -= 4; /*4; */ + + + /* set odd length for bug in LAN91C111, */ + /* which never sets RS_ODDFRAME */ + /* TODO ? */ + + +#ifdef USE_32_BIT + PRINTK3(" Reading %d dwords (and %d bytes) \n", + packet_length >> 2, packet_length & 3 ); + /* QUESTION: Like in the TX routine, do I want + to send the DWORDs or the bytes first, or some + mixture. A mixture might improve already slow PIO + performance */ + SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 ); + /* read the left over bytes */ + if (packet_length & 3) { + int i; + + byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3)); + dword leftover = SMC_inl(SMC91111_DATA_REG); + for (i=0; i<(packet_length & 3); i++) + *tail++ = (byte) (leftover >> (8*i)) & 0xff; + } +#else + PRINTK3(" Reading %d words and %d byte(s) \n", + (packet_length >> 1 ), packet_length & 1 ); + SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1); + +#endif /* USE_32_BIT */ + +#if SMC_DEBUG > 2 + printf("Receiving Packet\n"); + print_packet( NetRxPackets[0], packet_length ); +#endif + } else { + /* error ... */ + /* TODO ? */ + is_error = 1; + } + + while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) + udelay(1); /* Wait until not busy */ + + /* error or good, tell the card to get rid of this packet */ + SMC_outw( MC_RELEASE, MMU_CMD_REG ); + + while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) + udelay(1); /* Wait until not busy */ + + /* restore saved registers */ +#ifndef CONFIG_XAENIAX + SMC_outb( saved_pnr, PN_REG ); +#else + /* On Xaeniax board, we can't use SMC_outb here because that way + * the Allocate MMU command will end up written to the command register + * as well, which will lead to a problem. + */ + SMC_outl( saved_pnr << 16, 0); +#endif + SMC_outw( saved_ptr, PTR_REG ); + + if (!is_error) { + /* Pass the packet up to the protocol layers. */ + NetReceive(NetRxPackets[0], packet_length); + return packet_length; + } else { + return 0; + } + +} + + +/*---------------------------------------------------- + . smc_close + . + . this makes the board clean up everything that it can + . and not talk to the outside world. Caused by + . an 'ifconfig ethX down' + . + -----------------------------------------------------*/ +static int smc_close() +{ + PRINTK2("%s: smc_close\n", SMC_DEV_NAME); + + /* clear everything */ + smc_shutdown(); + + return 0; +} + + +#if 0 +/*------------------------------------------------------------ + . Modify a bit in the LAN91C111 register set + .-------------------------------------------------------------*/ +static word smc_modify_regbit(int bank, int ioaddr, int reg, + unsigned int bit, int val) +{ + word regval; + + SMC_SELECT_BANK( bank ); + + regval = SMC_inw( reg ); + if (val) + regval |= bit; + else + regval &= ~bit; + + SMC_outw( regval, 0 ); + return(regval); +} + + +/*------------------------------------------------------------ + . Retrieve a bit in the LAN91C111 register set + .-------------------------------------------------------------*/ +static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit) +{ + SMC_SELECT_BANK( bank ); + if ( SMC_inw( reg ) & bit) + return(1); + else + return(0); +} + + +/*------------------------------------------------------------ + . Modify a LAN91C111 register (word access only) + .-------------------------------------------------------------*/ +static void smc_modify_reg(int bank, int ioaddr, int reg, word val) +{ + SMC_SELECT_BANK( bank ); + SMC_outw( val, reg ); +} + + +/*------------------------------------------------------------ + . Retrieve a LAN91C111 register (word access only) + .-------------------------------------------------------------*/ +static int smc_get_reg(int bank, int ioaddr, int reg) +{ + SMC_SELECT_BANK( bank ); + return(SMC_inw( reg )); +} + +#endif /* 0 */ + +/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ + +#if (SMC_DEBUG > 2 ) + +/*------------------------------------------------------------ + . Debugging function for viewing MII Management serial bitstream + .-------------------------------------------------------------*/ +static void smc_dump_mii_stream (byte * bits, int size) +{ + int i; + + printf ("BIT#:"); + for (i = 0; i < size; ++i) { + printf ("%d", i % 10); + } + + printf ("\nMDOE:"); + for (i = 0; i < size; ++i) { + if (bits[i] & MII_MDOE) + printf ("1"); + else + printf ("0"); + } + + printf ("\nMDO :"); + for (i = 0; i < size; ++i) { + if (bits[i] & MII_MDO) + printf ("1"); + else + printf ("0"); + } + + printf ("\nMDI :"); + for (i = 0; i < size; ++i) { + if (bits[i] & MII_MDI) + printf ("1"); + else + printf ("0"); + } + + printf ("\n"); +} +#endif + +/*------------------------------------------------------------ + . Reads a register from the MII Management serial interface + .-------------------------------------------------------------*/ +#ifndef CONFIG_SMC91111_EXT_PHY +static word smc_read_phy_register (byte phyreg) +{ + int oldBank; + int i; + byte mask; + word mii_reg; + byte bits[64]; + int clk_idx = 0; + int input_idx; + word phydata; + byte phyaddr = SMC_PHY_ADDR; + + /* 32 consecutive ones on MDO to establish sync */ + for (i = 0; i < 32; ++i) + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Start code <01> */ + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Read command <10> */ + bits[clk_idx++] = MII_MDOE | MII_MDO; + bits[clk_idx++] = MII_MDOE; + + /* Output the PHY address, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyaddr & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Output the phy register number, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyreg & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Tristate and turnaround (2 bit times) */ + bits[clk_idx++] = 0; + /*bits[clk_idx++] = 0; */ + + /* Input starts at this bit time */ + input_idx = clk_idx; + + /* Will input 16 bits */ + for (i = 0; i < 16; ++i) + bits[clk_idx++] = 0; + + /* Final clock bit */ + bits[clk_idx++] = 0; + + /* Save the current bank */ + oldBank = SMC_inw (BANK_SELECT); + + /* Select bank 3 */ + SMC_SELECT_BANK (3); + + /* Get the current MII register value */ + mii_reg = SMC_inw (MII_REG); + + /* Turn off all MII Interface bits */ + mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); + + /* Clock all 64 cycles */ + for (i = 0; i < sizeof bits; ++i) { + /* Clock Low - output data */ + SMC_outw (mii_reg | bits[i], MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + + /* Clock Hi - input data */ + SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + bits[i] |= SMC_inw (MII_REG) & MII_MDI; + } + + /* Return to idle state */ + /* Set clock to low, data to low, and output tristated */ + SMC_outw (mii_reg, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + /* Restore original bank select */ + SMC_SELECT_BANK (oldBank); + + /* Recover input data */ + phydata = 0; + for (i = 0; i < 16; ++i) { + phydata <<= 1; + + if (bits[input_idx++] & MII_MDI) + phydata |= 0x0001; + } + +#if (SMC_DEBUG > 2 ) + printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", + phyaddr, phyreg, phydata); + smc_dump_mii_stream (bits, sizeof bits); +#endif + + return (phydata); +} + + +/*------------------------------------------------------------ + . Writes a register to the MII Management serial interface + .-------------------------------------------------------------*/ +static void smc_write_phy_register (byte phyreg, word phydata) +{ + int oldBank; + int i; + word mask; + word mii_reg; + byte bits[65]; + int clk_idx = 0; + byte phyaddr = SMC_PHY_ADDR; + + /* 32 consecutive ones on MDO to establish sync */ + for (i = 0; i < 32; ++i) + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Start code <01> */ + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Write command <01> */ + bits[clk_idx++] = MII_MDOE; + bits[clk_idx++] = MII_MDOE | MII_MDO; + + /* Output the PHY address, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyaddr & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Output the phy register number, msb first */ + mask = (byte) 0x10; + for (i = 0; i < 5; ++i) { + if (phyreg & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Tristate and turnaround (2 bit times) */ + bits[clk_idx++] = 0; + bits[clk_idx++] = 0; + + /* Write out 16 bits of data, msb first */ + mask = 0x8000; + for (i = 0; i < 16; ++i) { + if (phydata & mask) + bits[clk_idx++] = MII_MDOE | MII_MDO; + else + bits[clk_idx++] = MII_MDOE; + + /* Shift to next lowest bit */ + mask >>= 1; + } + + /* Final clock bit (tristate) */ + bits[clk_idx++] = 0; + + /* Save the current bank */ + oldBank = SMC_inw (BANK_SELECT); + + /* Select bank 3 */ + SMC_SELECT_BANK (3); + + /* Get the current MII register value */ + mii_reg = SMC_inw (MII_REG); + + /* Turn off all MII Interface bits */ + mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); + + /* Clock all cycles */ + for (i = 0; i < sizeof bits; ++i) { + /* Clock Low - output data */ + SMC_outw (mii_reg | bits[i], MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + + /* Clock Hi - input data */ + SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + bits[i] |= SMC_inw (MII_REG) & MII_MDI; + } + + /* Return to idle state */ + /* Set clock to low, data to low, and output tristated */ + SMC_outw (mii_reg, MII_REG); + udelay (SMC_PHY_CLOCK_DELAY); + + /* Restore original bank select */ + SMC_SELECT_BANK (oldBank); + +#if (SMC_DEBUG > 2 ) + printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", + phyaddr, phyreg, phydata); + smc_dump_mii_stream (bits, sizeof bits); +#endif +} +#endif /* !CONFIG_SMC91111_EXT_PHY */ + + +/*------------------------------------------------------------ + . Waits the specified number of milliseconds - kernel friendly + .-------------------------------------------------------------*/ +#ifndef CONFIG_SMC91111_EXT_PHY +static void smc_wait_ms(unsigned int ms) +{ + udelay(ms*1000); +} +#endif /* !CONFIG_SMC91111_EXT_PHY */ + + +/*------------------------------------------------------------ + . Configures the specified PHY using Autonegotiation. Calls + . smc_phy_fixed() if the user has requested a certain config. + .-------------------------------------------------------------*/ +#ifndef CONFIG_SMC91111_EXT_PHY +static void smc_phy_configure () +{ + int timeout; + byte phyaddr; + word my_phy_caps; /* My PHY capabilities */ + word my_ad_caps; /* My Advertised capabilities */ + word status = 0; /*;my status = 0 */ + int failed = 0; + + PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); + + + /* Get the detected phy address */ + phyaddr = SMC_PHY_ADDR; + + /* Reset the PHY, setting all other bits to zero */ + smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST); + + /* Wait for the reset to complete, or time out */ + timeout = 6; /* Wait up to 3 seconds */ + while (timeout--) { + if (!(smc_read_phy_register (PHY_CNTL_REG) + & PHY_CNTL_RST)) { + /* reset complete */ + break; + } + + smc_wait_ms (500); /* wait 500 millisecs */ + } + + if (timeout < 1) { + printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); + goto smc_phy_configure_exit; + } + + /* Read PHY Register 18, Status Output */ + /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ + + /* Enable PHY Interrupts (for register 18) */ + /* Interrupts listed here are disabled */ + smc_write_phy_register (PHY_MASK_REG, 0xffff); + + /* Configure the Receive/Phy Control register */ + SMC_SELECT_BANK (0); + SMC_outw (RPC_DEFAULT, RPC_REG); + + /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ + my_phy_caps = smc_read_phy_register (PHY_STAT_REG); + my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ + + if (my_phy_caps & PHY_STAT_CAP_T4) + my_ad_caps |= PHY_AD_T4; + + if (my_phy_caps & PHY_STAT_CAP_TXF) + my_ad_caps |= PHY_AD_TX_FDX; + + if (my_phy_caps & PHY_STAT_CAP_TXH) + my_ad_caps |= PHY_AD_TX_HDX; + + if (my_phy_caps & PHY_STAT_CAP_TF) + my_ad_caps |= PHY_AD_10_FDX; + + if (my_phy_caps & PHY_STAT_CAP_TH) + my_ad_caps |= PHY_AD_10_HDX; + + /* Update our Auto-Neg Advertisement Register */ + smc_write_phy_register (PHY_AD_REG, my_ad_caps); + + /* Read the register back. Without this, it appears that when */ + /* auto-negotiation is restarted, sometimes it isn't ready and */ + /* the link does not come up. */ + smc_read_phy_register(PHY_AD_REG); + + PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); + PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); + + /* Restart auto-negotiation process in order to advertise my caps */ + smc_write_phy_register (PHY_CNTL_REG, + PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); + + /* Wait for the auto-negotiation to complete. This may take from */ + /* 2 to 3 seconds. */ + /* Wait for the reset to complete, or time out */ + timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; + while (timeout--) { + + status = smc_read_phy_register (PHY_STAT_REG); + if (status & PHY_STAT_ANEG_ACK) { + /* auto-negotiate complete */ + break; + } + + smc_wait_ms (500); /* wait 500 millisecs */ + + /* Restart auto-negotiation if remote fault */ + if (status & PHY_STAT_REM_FLT) { + printf ("%s: PHY remote fault detected\n", + SMC_DEV_NAME); + + /* Restart auto-negotiation */ + printf ("%s: PHY restarting auto-negotiation\n", + SMC_DEV_NAME); + smc_write_phy_register (PHY_CNTL_REG, + PHY_CNTL_ANEG_EN | + PHY_CNTL_ANEG_RST | + PHY_CNTL_SPEED | + PHY_CNTL_DPLX); + } + } + + if (timeout < 1) { + printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); + failed = 1; + } + + /* Fail if we detected an auto-negotiate remote fault */ + if (status & PHY_STAT_REM_FLT) { + printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); + failed = 1; + } + + /* Re-Configure the Receive/Phy Control register */ + SMC_outw (RPC_DEFAULT, RPC_REG); + +smc_phy_configure_exit: ; + +} +#endif /* !CONFIG_SMC91111_EXT_PHY */ + + +#if SMC_DEBUG > 2 +static void print_packet( byte * buf, int length ) +{ + int i; + int remainder; + int lines; + + printf("Packet of length %d \n", length ); + +#if SMC_DEBUG > 3 + lines = length / 16; + remainder = length % 16; + + for ( i = 0; i < lines ; i ++ ) { + int cur; + + for ( cur = 0; cur < 8; cur ++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + printf("%02x%02x ", a, b ); + } + printf("\n"); + } + for ( i = 0; i < remainder/2 ; i++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + printf("%02x%02x ", a, b ); + } + printf("\n"); +#endif +} +#endif + +int eth_init(bd_t *bd) { +#ifdef SHARED_RESOURCES + swap_to(ETHERNET); +#endif + return (smc_open(bd)); +} + +void eth_halt() { + smc_close(); +} + +int eth_rx() { + return smc_rcv(); +} + +int eth_send(volatile void *packet, int length) { + return smc_send_packet(packet, length); +} + +int smc_get_ethaddr (bd_t * bd) +{ + int env_size, rom_valid, env_present = 0, reg; + char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66"; + char s_env_mac[64]; + uchar v_env_mac[6], v_rom_mac[6]; + + env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac)); + if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */ + printf ("\n*** ERROR: ethaddr is not set properly!!\n"); + return (-1); + } + + if (env_size > 0) { + env_present = 1; + s = s_env_mac; + } + + for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */ + v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; + } + + rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */ + + if (!env_present) { /* if NO env */ + if (rom_valid) { /* but ROM is valid */ + v_mac = (char *)v_rom_mac; + sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", + v_mac[0], v_mac[1], v_mac[2], v_mac[3], + v_mac[4], v_mac[5]); + setenv ("ethaddr", s_env_mac); + } else { /* no env, bad ROM */ + printf ("\n*** ERROR: ethaddr is NOT set !!\n"); + return (-1); + } + } else { /* good env, don't care ROM */ + v_mac = (char *)v_env_mac; /* always use a good env over a ROM */ + } + + if (env_present && rom_valid) { /* if both env and ROM are good */ + if (memcmp (v_env_mac, v_rom_mac, 6) != 0) { + printf ("\nWarning: MAC addresses don't match:\n"); + printf ("\tHW MAC address: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + v_rom_mac[0], v_rom_mac[1], + v_rom_mac[2], v_rom_mac[3], + v_rom_mac[4], v_rom_mac[5] ); + printf ("\t\"ethaddr\" value: " + "%02X:%02X:%02X:%02X:%02X:%02X\n", + v_env_mac[0], v_env_mac[1], + v_env_mac[2], v_env_mac[3], + v_env_mac[4], v_env_mac[5]) ; + debug ("### Set MAC addr from environment\n"); + } + } + memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */ + smc_set_mac_addr ((uchar *)v_mac); /* use old function to update smc default */ + PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1], + v_mac[2], v_mac[3], v_mac[4], v_mac[5]); + return (0); +} + +int get_rom_mac (uchar *v_rom_mac) +{ +#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ + char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; + + memcpy (v_rom_mac, hw_mac_addr, 6); + return (1); +#else + int i; + int valid_mac = 0; + + SMC_SELECT_BANK (1); + for (i=0; i<6; i++) + { + v_rom_mac[i] = SMC_inb ((ADDR0_REG + i)); + valid_mac |= v_rom_mac[i]; + } + + return (valid_mac ? 1 : 0); +#endif +} +#endif /* CONFIG_DRIVER_SMC91111 */ diff --git a/drivers/smc91111.h b/drivers/smc91111.h new file mode 100644 index 000000000..d03cbc320 --- /dev/null +++ b/drivers/smc91111.h @@ -0,0 +1,719 @@ +/*------------------------------------------------------------------------ + . smc91111.h - macros for the LAN91C111 Ethernet Driver + . + . (C) Copyright 2002 + . Sysgo Real-Time Solutions, GmbH + . Rolf Offermanns + . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) + . Developed by Simple Network Magic Corporation (SNMC) + . Copyright (C) 1996 by Erik Stahlman (ES) + . + . This program is free software; you can redistribute it and/or modify + . it under the terms of the GNU General Public License as published by + . the Free Software Foundation; either version 2 of the License, or + . (at your option) any later version. + . + . This program is distributed in the hope that it will be useful, + . but WITHOUT ANY WARRANTY; without even the implied warranty of + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + . GNU General Public License for more details. + . + . You should have received a copy of the GNU General Public License + . along with this program; if not, write to the Free Software + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + . + . This file contains register information and access macros for + . the LAN91C111 single chip ethernet controller. It is a modified + . version of the smc9194.h file. + . + . Information contained in this file was obtained from the LAN91C111 + . manual from SMC. To get a copy, if you really want one, you can find + . information under www.smsc.com. + . + . Authors + . Erik Stahlman ( erik@vt.edu ) + . Daris A Nevil ( dnevil@snmc.com ) + . + . History + . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device + . + ---------------------------------------------------------------------------*/ +#ifndef _SMC91111_H_ +#define _SMC91111_H_ + +#include +#include + +/* + * This function may be called by the board specific initialisation code + * in order to override the default mac address. + */ + +void smc_set_mac_addr (const unsigned char *addr); + + +/* I want some simple types */ + +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned long int dword; + +/* + . DEBUGGING LEVELS + . + . 0 for normal operation + . 1 for slightly more details + . >2 for various levels of increasingly useless information + . 2 for interrupt tracking, status flags + . 3 for packet info + . 4 for complete packet dumps +*/ +/*#define SMC_DEBUG 0 */ + +/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ + +#define SMC_IO_EXTENT 16 + +#ifdef CONFIG_PXA250 + +#ifdef CONFIG_XSENGINE +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1)))) +#define SMC_inb(p) ({ \ + unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \ + unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ + if (__p & 2) __v >>= 8; \ + else __v &= 0xff; \ + __v; }) +#elif defined(CONFIG_XAENIAX) +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inw(z) ({ \ + unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \ + unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ + if (__p & 3) __v >>= 16; \ + else __v &= 0xffff; \ + __v; }) +#define SMC_inb(p) ({ \ + unsigned int ___v = SMC_inw((p) & ~1); \ + if (p & 1) ___v >>= 8; \ + else ___v &= 0xff; \ + ___v; }) +#else +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inb(p) ({ \ + unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \ + unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ + if (__p & 1) __v >>= 8; \ + else __v &= 0xff; \ + __v; }) +#endif + +#ifdef CONFIG_XSENGINE +#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d) +#elif defined (CONFIG_XAENIAX) +#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outw(d,p) ({ \ + dword __dwo = SMC_inl((p) & ~3); \ + dword __dwn = (word)(d); \ + __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ + __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ + SMC_outl(__dwo, (p) & ~3); \ +}) +#else +#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) +#endif + +#define SMC_outb(d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(__w,(r)&~1); \ + }) + +#define SMC_outsl(r,b,l) ({ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl( *(__b2 + __i), r); \ + } \ + }) + +#define SMC_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw( *(__b2 + __i), r); \ + } \ + }) + +#define SMC_insl(r,b,l) ({ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl(r); \ + SMC_inl(0); \ + }; \ + }) + +#define SMC_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw(r); \ + SMC_inw(0); \ + }; \ + }) + +#define SMC_insb(r,b,l) ({ int __i ; \ + byte *__b2; \ + __b2 = (byte *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inb(r); \ + SMC_inb(0); \ + }; \ + }) + +#else /* if not CONFIG_PXA250 */ + +#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ +/* + * We have only 16 Bit PCMCIA access on Socket 0 + */ + +#ifdef CONFIG_ADNPESC1 +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) +#elif CONFIG_BLACKFIN +#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); asm("ssync;"); __v;}) +#else +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#endif +#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) + +#ifdef CONFIG_ADNPESC1 +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d) +#elif CONFIG_BLACKFIN +#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d);asm("ssync;");} +#else +#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) +#endif +#define SMC_outb(d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((r)&~1); \ + __w &= ((r)&1) ? 0x00FF : 0xFF00; \ + __w |= ((r)&1) ? __d<<8 : __d; \ + SMC_outw(__w,(r)&~1); \ + }) +#if 0 +#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) +#else +#define SMC_outsw(r,b,l) ({ int __i; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outw( *(__b2 + __i), r); \ + } \ + }) +#endif + +#if 0 +#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) +#else +#define SMC_insw(r,b,l) ({ int __i ; \ + word *__b2; \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inw(r); \ + SMC_inw(0); \ + }; \ + }) +#endif + +#endif /* CONFIG_SMC_USE_IOFUNCS */ + +#if defined(CONFIG_SMC_USE_32_BIT) + +#ifdef CONFIG_XSENGINE +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) +#else +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) +#endif + +#define SMC_insl(r,b,l) ({ int __i ; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + *(__b2 + __i) = SMC_inl(r); \ + SMC_inl(0); \ + }; \ + }) + +#ifdef CONFIG_XSENGINE +#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) +#else +#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) +#endif +#define SMC_outsl(r,b,l) ({ int __i; \ + dword *__b2; \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ + SMC_outl( *(__b2 + __i), r); \ + } \ + }) + +#endif /* CONFIG_SMC_USE_32_BIT */ + +#endif + +/*--------------------------------------------------------------- + . + . A description of the SMSC registers is probably in order here, + . although for details, the SMC datasheet is invaluable. + . + . Basically, the chip has 4 banks of registers ( 0 to 3 ), which + . are accessed by writing a number into the BANK_SELECT register + . ( I also use a SMC_SELECT_BANK macro for this ). + . + . The banks are configured so that for most purposes, bank 2 is all + . that is needed for simple run time tasks. + -----------------------------------------------------------------------*/ + +/* + . Bank Select Register: + . + . yyyy yyyy 0000 00xx + . xx = bank number + . yyyy yyyy = 0x33, for identification purposes. +*/ +#define BANK_SELECT 14 + +/* Transmit Control Register */ +/* BANK 0 */ +#define TCR_REG 0x0000 /* transmit control register */ +#define TCR_ENABLE 0x0001 /* When 1 we can transmit */ +#define TCR_LOOP 0x0002 /* Controls output pin LBK */ +#define TCR_FORCOL 0x0004 /* When 1 will force a collision */ +#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ +#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ +#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ +#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ +#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ +#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ +#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ + +#define TCR_CLEAR 0 /* do NOTHING */ +/* the default settings for the TCR register : */ +/* QUESTION: do I want to enable padding of short packets ? */ +#define TCR_DEFAULT TCR_ENABLE + + +/* EPH Status Register */ +/* BANK 0 */ +#define EPH_STATUS_REG 0x0002 +#define ES_TX_SUC 0x0001 /* Last TX was successful */ +#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ +#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ +#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ +#define ES_16COL 0x0010 /* 16 Collisions Reached */ +#define ES_SQET 0x0020 /* Signal Quality Error Test */ +#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ +#define ES_TXDEFR 0x0080 /* Transmit Deferred */ +#define ES_LATCOL 0x0200 /* Late collision detected on last tx */ +#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ +#define ES_EXC_DEF 0x0800 /* Excessive Deferral */ +#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ +#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ +#define ES_TXUNRN 0x8000 /* Tx Underrun */ + + +/* Receive Control Register */ +/* BANK 0 */ +#define RCR_REG 0x0004 +#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ +#define RCR_PRMS 0x0002 /* Enable promiscuous mode */ +#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ +#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ +#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ +#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ +#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ +#define RCR_SOFTRST 0x8000 /* resets the chip */ + +/* the normal settings for the RCR register : */ +#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) +#define RCR_CLEAR 0x0 /* set it to a base state */ + +/* Counter Register */ +/* BANK 0 */ +#define COUNTER_REG 0x0006 + +/* Memory Information Register */ +/* BANK 0 */ +#define MIR_REG 0x0008 + +/* Receive/Phy Control Register */ +/* BANK 0 */ +#define RPC_REG 0x000A +#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ +#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ +#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ +#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ +#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ +#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ +#define RPC_LED_RES (0x01) /* LED = Reserved */ +#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ +#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ +#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ +#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ +#define RPC_LED_TX (0x06) /* LED = TX packet occurred */ +#define RPC_LED_RX (0x07) /* LED = RX packet occurred */ +#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) +/* buggy schematic: LEDa -> yellow, LEDb --> green */ +#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ + | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ + | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) +#elif defined(CONFIG_ADNPESC1) +/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ +#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ + | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ + | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) +#else +/* SMSC reference design: LEDa --> green, LEDb --> yellow */ +#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ + | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ + | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) +#endif + +/* Bank 0 0x000C is reserved */ + +/* Bank Select Register */ +/* All Banks */ +#define BSR_REG 0x000E + + +/* Configuration Reg */ +/* BANK 1 */ +#define CONFIG_REG 0x0000 +#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ +#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ +#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ +#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ + +/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ +#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) + + +/* Base Address Register */ +/* BANK 1 */ +#define BASE_REG 0x0002 + + +/* Individual Address Registers */ +/* BANK 1 */ +#define ADDR0_REG 0x0004 +#define ADDR1_REG 0x0006 +#define ADDR2_REG 0x0008 + + +/* General Purpose Register */ +/* BANK 1 */ +#define GP_REG 0x000A + + +/* Control Register */ +/* BANK 1 */ +#define CTL_REG 0x000C +#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ +#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ +#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ +#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ +#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ +#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ +#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ +#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ +#define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ + +/* MMU Command Register */ +/* BANK 2 */ +#define MMU_CMD_REG 0x0000 +#define MC_BUSY 1 /* When 1 the last release has not completed */ +#define MC_NOP (0<<5) /* No Op */ +#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ +#define MC_RESET (2<<5) /* Reset MMU to initial state */ +#define MC_REMOVE (3<<5) /* Remove the current rx packet */ +#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ +#define MC_FREEPKT (5<<5) /* Release packet in PNR register */ +#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ +#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ + + +/* Packet Number Register */ +/* BANK 2 */ +#define PN_REG 0x0002 + + +/* Allocation Result Register */ +/* BANK 2 */ +#define AR_REG 0x0003 +#define AR_FAILED 0x80 /* Alocation Failed */ + + +/* RX FIFO Ports Register */ +/* BANK 2 */ +#define RXFIFO_REG 0x0004 /* Must be read as a word */ +#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ + + +/* TX FIFO Ports Register */ +/* BANK 2 */ +#define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ +#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ + + +/* Pointer Register */ +/* BANK 2 */ +#define PTR_REG 0x0006 +#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ +#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ +#define PTR_READ 0x2000 /* When 1 the operation is a read */ +#define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ + + +/* Data Register */ +/* BANK 2 */ +#define SMC91111_DATA_REG 0x0008 + + +/* Interrupt Status/Acknowledge Register */ +/* BANK 2 */ +#define SMC91111_INT_REG 0x000C + + +/* Interrupt Mask Register */ +/* BANK 2 */ +#define IM_REG 0x000D +#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ +#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ +#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ +#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ +#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ +#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ +#define IM_TX_INT 0x02 /* Transmit Interrrupt */ +#define IM_RCV_INT 0x01 /* Receive Interrupt */ + + +/* Multicast Table Registers */ +/* BANK 3 */ +#define MCAST_REG1 0x0000 +#define MCAST_REG2 0x0002 +#define MCAST_REG3 0x0004 +#define MCAST_REG4 0x0006 + + +/* Management Interface Register (MII) */ +/* BANK 3 */ +#define MII_REG 0x0008 +#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ +#define MII_MDOE 0x0008 /* MII Output Enable */ +#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ +#define MII_MDI 0x0002 /* MII Input, pin MDI */ +#define MII_MDO 0x0001 /* MII Output, pin MDO */ + + +/* Revision Register */ +/* BANK 3 */ +#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ + + +/* Early RCV Register */ +/* BANK 3 */ +/* this is NOT on SMC9192 */ +#define ERCV_REG 0x000C +#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ +#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ + +/* External Register */ +/* BANK 7 */ +#define EXT_REG 0x0000 + + +#define CHIP_9192 3 +#define CHIP_9194 4 +#define CHIP_9195 5 +#define CHIP_9196 6 +#define CHIP_91100 7 +#define CHIP_91100FD 8 +#define CHIP_91111FD 9 + +#if 0 +static const char * chip_ids[ 15 ] = { + NULL, NULL, NULL, + /* 3 */ "SMC91C90/91C92", + /* 4 */ "SMC91C94", + /* 5 */ "SMC91C95", + /* 6 */ "SMC91C96", + /* 7 */ "SMC91C100", + /* 8 */ "SMC91C100FD", + /* 9 */ "SMC91C111", + NULL, NULL, + NULL, NULL, NULL}; +#endif + +/* + . Transmit status bits +*/ +#define TS_SUCCESS 0x0001 +#define TS_LOSTCAR 0x0400 +#define TS_LATCOL 0x0200 +#define TS_16COL 0x0010 + +/* + . Receive status bits +*/ +#define RS_ALGNERR 0x8000 +#define RS_BRODCAST 0x4000 +#define RS_BADCRC 0x2000 +#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ +#define RS_TOOLONG 0x0800 +#define RS_TOOSHORT 0x0400 +#define RS_MULTICAST 0x0001 +#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) + + +/* PHY Types */ +enum { + PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ + PHY_LAN83C180 +}; + + +/* PHY Register Addresses (LAN91C111 Internal PHY) */ + +/* PHY Control Register */ +#define PHY_CNTL_REG 0x00 +#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ +#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ +#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ +#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ +#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ +#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ +#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ +#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ +#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ + +/* PHY Status Register */ +#define PHY_STAT_REG 0x01 +#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ +#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ +#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ +#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ +#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ +#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ +#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ +#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ +#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ +#define PHY_STAT_LINK 0x0004 /* 1=valid link */ +#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ +#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ + +/* PHY Identifier Registers */ +#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ +#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ + +/* PHY Auto-Negotiation Advertisement Register */ +#define PHY_AD_REG 0x04 +#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ +#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ +#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ +#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ +#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ +#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ +#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ +#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ +#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ + +/* PHY Auto-negotiation Remote End Capability Register */ +#define PHY_RMT_REG 0x05 +/* Uses same bit definitions as PHY_AD_REG */ + +/* PHY Configuration Register 1 */ +#define PHY_CFG1_REG 0x10 +#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ +#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ +#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ +#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ +#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ +#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ +#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ +#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ +#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ +#define PHY_CFG1_TLVL_MASK 0x003C +#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ + + +/* PHY Configuration Register 2 */ +#define PHY_CFG2_REG 0x11 +#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ +#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ +#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ +#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ + +/* PHY Status Output (and Interrupt status) Register */ +#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ +#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ +#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ +#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ +#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ +#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ +#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ +#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ +#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ +#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ +#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ + +/* PHY Interrupt/Status Mask Register */ +#define PHY_MASK_REG 0x13 /* Interrupt Mask */ +/* Uses the same bit definitions as PHY_INT_REG */ + + +/*------------------------------------------------------------------------- + . I define some macros to make it easier to do somewhat common + . or slightly complicated, repeated tasks. + --------------------------------------------------------------------------*/ + +/* select a register bank, 0 to 3 */ + +#define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); } + +/* this enables an interrupt in the interrupt mask register */ +#define SMC_ENABLE_INT(x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(2);\ + mask = SMC_inb( IM_REG );\ + mask |= (x);\ + SMC_outb( mask, IM_REG ); \ +} + +/* this disables an interrupt from the interrupt mask register */ + +#define SMC_DISABLE_INT(x) {\ + unsigned char mask;\ + SMC_SELECT_BANK(2);\ + mask = SMC_inb( IM_REG );\ + mask &= ~(x);\ + SMC_outb( mask, IM_REG ); \ +} + +/*---------------------------------------------------------------------- + . Define the interrupts that I want to receive from the card + . + . I want: + . IM_EPH_INT, for nasty errors + . IM_RCV_INT, for happy received packets + . IM_RX_OVRN_INT, because I have to kick the receiver + . IM_MDINT, for PHY Register 18 Status Changes + --------------------------------------------------------------------------*/ +#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ + IM_MDINT) + +#endif /* _SMC_91111_H_ */ diff --git a/drivers/smiLynxEM.c b/drivers/smiLynxEM.c new file mode 100644 index 000000000..20f9beb01 --- /dev/null +++ b/drivers/smiLynxEM.c @@ -0,0 +1,858 @@ +/* + * (C) Copyright 1997-2002 ELTEC Elektronik AG + * Frank Gottschling + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * smiLynxEM.c + * + * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator + * + * modification history + * -------------------- + * 04-18-2002 Rewritten for U-Boot . + * + * 18-03-2004 - Unify videomodes handling with the ct69000 + * - The video output can be set via the variable "videoout" + * in the environment. + * videoout=1 output on LCD + * videoout=2 output on CRT (default value) + * + */ + +#include + +#if defined(CONFIG_VIDEO_SMI_LYNXEM) + +#include +#include +#include "videomodes.h" +/* + * Export Graphic Device + */ +GraphicDevice smi; + +/* + * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external + */ +#define VIDEO_MEM_SIZE 0x400000 + + +/* + * ISA mapped regs + */ +#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */ +#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */ +#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */ +#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */ +#define SMI_ISR1 (pGD->isaBase + 0x03ca) +#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */ +#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */ +#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */ +#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */ +#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */ +#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */ +#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/ +#define SMI_INDX_ATTR (pGD->isaBase + 0x03c0) /* attributes index reg */ + +/* + * Video processor control + */ +typedef struct { + unsigned int control; + unsigned int colorKey; + unsigned int colorKeyMask; + unsigned int start; + unsigned short offset; + unsigned short width; + unsigned int fifoPrio; + unsigned int fifoERL; + unsigned int YUVtoRGB; +} SmiVideoProc; + +/* + * Video window control + */ +typedef struct { + unsigned short top; + unsigned short left; + unsigned short bottom; + unsigned short right; + unsigned int srcStart; + unsigned short width; + unsigned short offset; + unsigned char hStretch; + unsigned char vStretch; +} SmiVideoWin; + +/* + * Capture port control + */ +typedef struct { + unsigned int control; + unsigned short topClip; + unsigned short leftClip; + unsigned short srcHeight; + unsigned short srcWidth; + unsigned int srcBufStart1; + unsigned int srcBufStart2; + unsigned short srcOffset; + unsigned short fifoControl; +} SmiCapturePort; + + +/* + * Register values for common video modes + */ +static char SMI_SCR[] = { + /* all modes */ + 0x10, 0xff, 0x11, 0xff, 0x12, 0xff, 0x13, 0xff, 0x15, 0x90, + 0x17, 0x20, 0x18, 0xb1, 0x19, 0x00, +}; +static char SMI_EXT_CRT[] = { + 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00, + 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00, +}; +static char SMI_ATTR [] = { + 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, + 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0b, + 0x0c, 0x0c, 0x0d, 0x0d, 0x0e, 0x0e, 0x0f, 0x0f, 0x10, 0x41, 0x11, 0x00, + 0x12, 0x0f, 0x13, 0x00, 0x14, 0x00, +}; +static char SMI_GCR[18] = { + 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x40, + 0x06, 0x05, 0x07, 0x0f, 0x08, 0xff, +}; +static char SMI_SEQR[] = { + 0x00, 0x00, 0x01, 0x01, 0x02, 0x0f, 0x03, 0x03, 0x04, 0x0e, 0x00, 0x03, +}; +static char SMI_PCR [] = { + 0x20, 0x04, 0x21, 0x30, 0x22, 0x00, 0x23, 0x00, 0x24, 0x00, +}; +static char SMI_MCR[] = { + 0x60, 0x01, 0x61, 0x00, +#ifdef CONFIG_HMI1001 + 0x62, 0x74, /* Memory type is not configured by pins on HMI1001 */ +#endif +}; + +static char SMI_HCR[] = { + 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00, + 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00, +}; + + +/******************************************************************************* + * + * Write SMI ISA register + */ +static void smiWrite (unsigned short index, char reg, char val) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + out8 ((pGD->isaBase + index), reg); + out8 ((pGD->isaBase + index + 1), val); +} + +/******************************************************************************* + * + * Write a table of SMI ISA register + */ +static void smiLoadRegs ( + unsigned int iReg, + unsigned int dReg, + char *regTab, + unsigned int tabSize + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register int i; + + for (i=0; icprBase + 0x0004), ((pCP->topClip<<16) | pCP->leftClip)); + out32r ((pGD->cprBase + 0x0008), ((pCP->srcHeight<<16) | pCP->srcWidth)); + out32r ((pGD->cprBase + 0x000c), pCP->srcBufStart1/8); + out32r ((pGD->cprBase + 0x0010), pCP->srcBufStart2/8); + out32r ((pGD->cprBase + 0x0014), pCP->srcOffset/8); + out32r ((pGD->cprBase + 0x0018), pCP->fifoControl); + out32r ((pGD->cprBase + 0x0000), pCP->control); +} + + +/******************************************************************************* + * + * Init video processor registers + */ +static void smiInitVideoProcessor (void) +{ + SmiVideoProc smiVP = { 0x100000, 0, 0, 0, 0, 1600, 0x1200543, 4, 0xededed }; + SmiVideoWin smiVW = { 0, 0, 599, 799, 0, 1600, 0, 0, 0 }; + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register SmiVideoProc *pVP = (SmiVideoProc *)&smiVP; + register SmiVideoWin *pVWin = (SmiVideoWin *)&smiVW; + + pVP->width = pGD->plnSizeX * pGD->gdfBytesPP; + pVP->control |= pGD->gdfIndex << 16; + pVWin->bottom = pGD->winSizeY - 1; + pVWin->right = pGD->winSizeX - 1; + pVWin->width = pVP->width; + + /* color key */ + out32r ((pGD->vprBase + 0x0004), pVP->colorKey); + + /* color key mask */ + out32r ((pGD->vprBase + 0x0008), pVP->colorKeyMask); + + /* data src start adrs */ + out32r ((pGD->vprBase + 0x000c), pVP->start / 8); + + /* data width and offset */ + out32r ((pGD->vprBase + 0x0010), + ((pVP->offset / 8 * pGD->gdfBytesPP) << 16) | + (pGD->plnSizeX / 8 * pGD->gdfBytesPP)); + + /* video window 1 */ + out32r ((pGD->vprBase + 0x0014), + ((pVWin->top << 16) | pVWin->left)); + + out32r ((pGD->vprBase + 0x0018), + ((pVWin->bottom << 16) | pVWin->right)); + + out32r ((pGD->vprBase + 0x001c), pVWin->srcStart / 8); + + out32r ((pGD->vprBase + 0x0020), + (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); + + out32r ((pGD->vprBase + 0x0024), + (((pVWin->hStretch) << 8) | pVWin->vStretch)); + + /* video window 2 */ + out32r ((pGD->vprBase + 0x0028), + ((pVWin->top << 16) | pVWin->left)); + + out32r ((pGD->vprBase + 0x002c), + ((pVWin->bottom << 16) | pVWin->right)); + + out32r ((pGD->vprBase + 0x0030), + pVWin->srcStart / 8); + + out32r ((pGD->vprBase + 0x0034), + (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); + + out32r ((pGD->vprBase + 0x0038), + (((pVWin->hStretch) << 8) | pVWin->vStretch)); + + /* fifo prio control */ + out32r ((pGD->vprBase + 0x0054), pVP->fifoPrio); + + /* fifo empty request levell */ + out32r ((pGD->vprBase + 0x0058), pVP->fifoERL); + + /* conversion constant */ + out32r ((pGD->vprBase + 0x005c), pVP->YUVtoRGB); + + /* vpr control word */ + out32r ((pGD->vprBase + 0x0000), pVP->control); +} + +/****************************************************************************** + * + * Init drawing engine registers + */ +static void smiInitDrawingEngine (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&smi; + unsigned int val; + + /* don't start now */ + out32r ((pGD->dprBase + 0x000c), 0x000f0000); + + /* set rop2 to copypen */ + val = 0xffff3ff0 & in32r ((pGD->dprBase + 0x000c)); + out32r ((pGD->dprBase + 0x000c), (val | 0x8000 | 0x0c)); + + /* set clip rect */ + out32r ((pGD->dprBase + 0x002c), 0); + out32r ((pGD->dprBase + 0x0030), + ((pGD->winSizeY<<16) | pGD->winSizeX * pGD->gdfBytesPP )); + + /* src row pitch */ + val = 0xffff0000 & (in32r ((pGD->dprBase + 0x0010))); + out32r ((pGD->dprBase + 0x0010), + (val | pGD->plnSizeX * pGD->gdfBytesPP)); + + /* dst row pitch */ + val = 0x0000ffff & (in32r ((pGD->dprBase + 0x0010))); + out32r ((pGD->dprBase + 0x0010), + (((pGD->plnSizeX * pGD->gdfBytesPP)<<16) | val)); + + /* window width src/dst */ + out32r ((pGD->dprBase + 0x003c), + (((pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)<<16) | + (pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff))); + out16r ((pGD->dprBase + 0x001e), 0x0000); + + /* src base adrs */ + out32r ((pGD->dprBase + 0x0040), + (((pGD->frameAdrs/8) & 0x000fffff))); + + /* dst base adrs */ + out32r ((pGD->dprBase + 0x0044), + (((pGD->frameAdrs/8) & 0x000fffff))); + + /* foreground color */ + out32r ((pGD->dprBase + 0x0014), pGD->fg); + + /* background color */ + out32r ((pGD->dprBase + 0x0018), pGD->bg); + + /* xcolor */ + out32r ((pGD->dprBase + 0x0020), 0x00ffffff); + + /* xcolor mask */ + out32r ((pGD->dprBase + 0x0024), 0x00ffffff); + + /* bit mask */ + out32r ((pGD->dprBase + 0x0028), 0x00ffffff); + + /* load mono pattern */ + out32r ((pGD->dprBase + 0x0034), 0); + out32r ((pGD->dprBase + 0x0038), 0); +} + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_710 }, + { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_712 }, + { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_810 }, + { } +}; + +/*****************************************************************************/ +static void smiLoadMsr (struct ctfb_res_modes *mode) +{ + unsigned char h_synch_high, v_synch_high; + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */ + v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */ + out8 (SMI_MISC_REG, (h_synch_high | v_synch_high | 0x29)); + /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01 + * Selects the upper 64KB page.Bit5=1 + * CLK2 (left reserved in standard VGA) Bit3|2=1|0 + * Disables CPU access to frame buffer. Bit1=0 + * Sets the I/O address decode for ST01, FCR, and all CR registers + * to the 3Dx I/O address range (CGA emulation). Bit0=1 + */ +} +/*****************************************************************************/ +static void smiLoadCrt (struct ctfb_res_modes *var, int bits_per_pixel) +{ + unsigned char cr[0x7a]; + int i; + unsigned int hd, hs, he, ht, hbs, hbe; /* Horizontal. */ + unsigned int vd, vs, ve, vt, vbs, vbe; /* vertical */ + unsigned int bpp, wd, dblscan, interlaced; + + const int LineCompare = 0x3ff; + unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + /* Horizontal */ + hd = (var->xres) / 8; /* HDisp. */ + hs = (var->xres + var->right_margin) / 8; /* HsStrt */ + he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */ + ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */ + /* Blank */ + hbs = hd; + hbe = 0; /* Blank end at 0 */ + + /* Vertical */ + vd = var->yres; /* VDisplay */ + vs = var->yres + var->lower_margin; /* VSyncStart */ + ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */ + vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */ + vbs = vd; + vbe = 0; + + bpp = bits_per_pixel; + dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0; + interlaced = var->vmode & FB_VMODE_INTERLACED; + + + if (bpp == 15) + bpp = 16; + wd = var->xres * bpp / 64; /* double words per line */ + if (interlaced) { /* we divide all vertical timings, exept vd */ + vs >>= 1; + vbs >>= 1; + ve >>= 1; + vt >>= 1; + } + + memset (cr, 0, sizeof (cr)); + cr[0x00] = ht - 5; + cr[0x01] = hd - 1; + cr[0x02] = hbs - 1; + cr[0x03] = (hbe & 0x1F); + cr[0x04] = hs; + cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); + + cr[0x06] = (vt - 2) & 0xFF; + cr[0x07] = (((vt - 2) & 0x100) >> 8) + | (((vd - 1) & 0x100) >> 7) + | ((vs & 0x100) >> 6) + | (((vbs - 1) & 0x100) >> 5) + | ((LineCompare & 0x100) >> 4) + | (((vt - 2) & 0x200) >> 4) + | (((vd - 1) & 0x200) >> 3) + | ((vs & 0x200) >> 2); + + cr[0x30] = ((vt - 2) & 0x400) >> 7 + | (((vd - 1) & 0x400) >> 8) + | (((vbs - 1) & 0x400) >> 9) + | ((vs & 0x400) >> 10) + | (interlaced) ? 0x80 : 0; + + + cr[0x08] = 0x00; + cr[0x09] = (dblscan << 7) + | ((LineCompare & 0x200) >> 3) + | (((vbs - 1) & 0x200) >> 4) + | (TextScanLines - 1); + + cr[0x10] = vs & 0xff; /* VSyncPulseStart */ + cr[0x11] = (ve & 0x0f); + cr[0x12] = (vd - 1) & 0xff; /* LineCount */ + cr[0x13] = wd & 0xff; + cr[0x14] = 0x40; + cr[0x15] = (vbs - 1) & 0xff; + cr[0x16] = vbe & 0xff; + cr[0x17] = 0xe3; /* but it does not work */ + cr[0x18] = 0xff & LineCompare; + cr[0x22] = 0x00; /* todo? */ + + + /* now set the registers */ + for (i = 0; i <= 0x18; i++) { /*CR00 .. CR18 */ + smiWrite (SMI_INDX_D4, i, cr[i]); + } + i = 0x22; /*CR22 */ + smiWrite (SMI_INDX_D4, i, cr[i]); + i = 0x30; /*CR30 */ + smiWrite (SMI_INDX_D4, i, cr[i]); +} + +/*****************************************************************************/ +#define REF_FREQ 14318180 +#define PMIN 1 +#define PMAX 255 +#define QMIN 1 +#define QMAX 63 + +static unsigned int FindPQ (unsigned int freq, unsigned int *pp, unsigned int *pq) +{ + unsigned int n = QMIN, m = 0; + long long int L = 0, P = freq, Q = REF_FREQ, H = P >> 1; + long long int D = 0x7ffffffffffffffLL; + + for (n = QMIN; n <= QMAX; n++) { + m = PMIN; /* p/q ~ freq/ref -> p*ref-freq*q ~ 0 */ + L = P * n - m * Q; + while (L > 0 && m < PMAX) { + L -= REF_FREQ; /* difference is greater as 0 subtract fref */ + m++; /* and increment m */ + } + /* difference is less or equal than 0 or m > maximum */ + if (m > PMAX) + break; /* no solution: if we increase n we get the same situation */ + /* L is <= 0 now */ + if (-L > H && m > PMIN) { /* if difference > the half fref */ + L += REF_FREQ; /* we take the situation before */ + m--; /* because its closer to 0 */ + } + L = (L < 0) ? -L : +L; /* absolute value */ + if (D < L) /* if last difference was better take next n */ + continue; + D = L; + *pp = m; + *pq = n; /* keep improved data */ + if (D == 0) + break; /* best result we can get */ + } + return (unsigned int) (0xffffffff & D); +} + +/*****************************************************************************/ +static void smiLoadCcr (struct ctfb_res_modes *var, unsigned short device_id) +{ + unsigned int p = 0; + unsigned int q = 0; + long long freq; + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + smiWrite (SMI_INDX_C4, 0x65, 0); + smiWrite (SMI_INDX_C4, 0x66, 0); + smiWrite (SMI_INDX_C4, 0x68, 0x50); + if (device_id == PCI_DEVICE_ID_SMI_810) { + smiWrite (SMI_INDX_C4, 0x69, 0x3); + } else { + smiWrite (SMI_INDX_C4, 0x69, 0x0); + } + + /* Memory clock */ + switch (device_id) { + case PCI_DEVICE_ID_SMI_710 : + smiWrite (SMI_INDX_C4, 0x6a, 0x75); + break; + case PCI_DEVICE_ID_SMI_712 : + smiWrite (SMI_INDX_C4, 0x6a, 0x80); + break; + default : + smiWrite (SMI_INDX_C4, 0x6a, 0x53); + break; + } + smiWrite (SMI_INDX_C4, 0x6b, 0x15); + + /* VCLK */ + freq = 1000000000000LL / var -> pixclock; + + FindPQ ((unsigned int)freq, &p, &q); + + smiWrite (SMI_INDX_C4, 0x6c, p); + smiWrite (SMI_INDX_C4, 0x6d, q); + +} + +/******************************************************************************* + * + * Init video chip with common Linux graphic modes (lilo) + */ +void *video_hw_init (void) +{ + GraphicDevice *pGD = (GraphicDevice *)&smi; + unsigned short device_id; + pci_dev_t devbusfn; + int videomode; + unsigned long t1, hsynch, vsynch; + unsigned int pci_mem_base, *vm; + char *penv; + int tmp, i, bits_per_pixel; + struct ctfb_res_modes *res_mode; + struct ctfb_res_modes var_mode; + unsigned char videoout; + + /* Search for video chip */ + printf("Video: "); + + if ((devbusfn = pci_find_devices(supported, 0)) < 0) + { + printf ("Controller not found !\n"); + return (NULL); + } + + /* PCI setup */ + pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id); + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base); + pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base); + + tmp = 0; + + videomode = CFG_DEFAULT_VIDEO_MODE; + /* get video mode via environment */ + if ((penv = getenv ("videomode")) != NULL) { + /* deceide if it is a string */ + if (penv[0] <= '9') { + videomode = (int) simple_strtoul (penv, NULL, 16); + tmp = 1; + } + } else { + tmp = 1; + } + if (tmp) { + /* parameter are vesa modes */ + /* search params */ + for (i = 0; i < VESA_MODES_COUNT; i++) { + if (vesa_modes[i].vesanr == videomode) + break; + } + if (i == VESA_MODES_COUNT) { + printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE); + i = 0; + } + res_mode = + (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i]. + resindex]; + bits_per_pixel = vesa_modes[i].bits_per_pixel; + } else { + + res_mode = (struct ctfb_res_modes *) &var_mode; + bits_per_pixel = video_get_params (res_mode, penv); + } + + /* calculate hsynch and vsynch freq (info only) */ + t1 = (res_mode->left_margin + res_mode->xres + + res_mode->right_margin + res_mode->hsync_len) / 8; + t1 *= 8; + t1 *= res_mode->pixclock; + t1 /= 1000; + hsynch = 1000000000L / t1; + t1 *= + (res_mode->upper_margin + res_mode->yres + + res_mode->lower_margin + res_mode->vsync_len); + t1 /= 1000; + vsynch = 1000000000L / t1; + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, + res_mode->yres, bits_per_pixel, (hsynch / 1000), + (vsynch / 1000)); + printf ("%s\n", pGD->modeIdent); + pGD->winSizeX = res_mode->xres; + pGD->winSizeY = res_mode->yres; + pGD->plnSizeX = res_mode->xres; + pGD->plnSizeY = res_mode->yres; + switch (bits_per_pixel) { + case 8: + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + break; + case 15: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_15BIT_555RGB; + break; + case 16: + pGD->gdfBytesPP = 2; + pGD->gdfIndex = GDF_16BIT_565RGB; + break; + case 24: + pGD->gdfBytesPP = 3; + pGD->gdfIndex = GDF_24BIT_888RGB; + break; + } + + pGD->isaBase = CFG_ISA_IO; + pGD->pciBase = pci_mem_base; + pGD->dprBase = (pci_mem_base + 0x400000 + 0x8000); + pGD->vprBase = (pci_mem_base + 0x400000 + 0xc000); + pGD->cprBase = (pci_mem_base + 0x400000 + 0xe000); + pGD->frameAdrs = pci_mem_base; + pGD->memSize = VIDEO_MEM_SIZE; + + /* Set up hardware : select color mode, + set Register base to isa 3dx for 3?x regs*/ + out8 (SMI_MISC_REG, 0x01); + + /* Turn off display */ + smiWrite (SMI_INDX_C4, 0x01, 0x20); + + /* Unlock ext. crt regs */ + out8 (SMI_LOCK_REG, 0x40); + + /* Unlock crt regs 0-7 */ + smiWrite (SMI_INDX_D4, 0x11, 0x0e); + + /* Sytem Control Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SCR, sizeof(SMI_SCR)); + + /* extented CRT Register */ + smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5, SMI_EXT_CRT, sizeof(SMI_EXT_CRT)); + + /* Attributes controller registers */ + smiLoadRegs (SMI_INDX_ATTR, SMI_INDX_ATTR, SMI_ATTR, sizeof(SMI_ATTR)); + + /* Graphics Controller Register */ + smiLoadRegs (SMI_INDX_CE, SMI_DATA_CF, SMI_GCR, sizeof(SMI_GCR)); + + /* Sequencer Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SEQR, sizeof(SMI_SEQR)); + + /* Power Control Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_PCR, sizeof(SMI_PCR)); + + /* Memory Control Register */ + /* Register MSR62 is a power on configurable register. We don't */ + /* modify it */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_MCR, sizeof(SMI_MCR)); + + /* Set misc output register */ + smiLoadMsr (res_mode); + + /* Set CRT and Clock control registers */ + smiLoadCrt (res_mode, bits_per_pixel); + + smiLoadCcr (res_mode, device_id); + + /* Hardware Cusor Register */ + smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_HCR, sizeof(SMI_HCR)); + + /* Enable Display */ + videoout = 2; /* Default output is CRT */ + if ((penv = getenv ("videoout")) != NULL) { + /* deceide if it is a string */ + videoout = (int) simple_strtoul (penv, NULL, 16); + } + smiWrite (SMI_INDX_C4, 0x31, videoout); + + /* Video processor default setup */ + smiInitVideoProcessor (); + + /* Capture port default setup */ + smiInitCapturePort (); + + /* Drawing engine default setup */ + smiInitDrawingEngine (); + + /* Turn on display */ + smiWrite (0x3c4, 0x01, 0x01); + + /* Clear video memory */ + i = pGD->memSize/4; + vm = (unsigned int *)pGD->pciBase; + while(i--) + *vm++ = 0; + return ((void*)&smi); +} + +/******************************************************************************* + * + * Drawing engine fill on screen region + */ +void video_hw_rectfill ( + unsigned int bpp, /* bytes per pixel */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y, /* frame height */ + unsigned int color /* fill color */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register unsigned int control; + + dim_x *= bpp; + + out32r ((pGD->dprBase + 0x0014), color); + out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y)); + out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y)); + + control = 0x0000ffff & in32r ((pGD->dprBase + 0x000c)); + + control |= 0x80010000; + + out32r ((pGD->dprBase + 0x000c), control); + + /* Wait for drawing processor */ + do + { + out8 ((pGD->isaBase + 0x3c4), 0x16); + } while (in8 (pGD->isaBase + 0x3c5) & 0x08); +} + +/******************************************************************************* + * + * Drawing engine bitblt with screen region + */ +void video_hw_bitblt ( + unsigned int bpp, /* bytes per pixel */ + unsigned int src_x, /* source pos x */ + unsigned int src_y, /* source pos y */ + unsigned int dst_x, /* dest pos x */ + unsigned int dst_y, /* dest pos y */ + unsigned int dim_x, /* frame width */ + unsigned int dim_y /* frame height */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + register unsigned int control; + + dim_x *= bpp; + + if ((src_ydprBase + 0x0000), (((src_x+dim_x-1)<<16) | (src_y+dim_y-1))); + out32r ((pGD->dprBase + 0x0004), (((dst_x+dim_x-1)<<16) | (dst_y+dim_y-1))); + control = 0x88000000; + } else { + out32r ((pGD->dprBase + 0x0000), ((src_x<<16) | src_y)); + out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y)); + control = 0x80000000; + } + + out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y)); + control |= (0x0000ffff & in32r ((pGD->dprBase + 0x000c))); + out32r ((pGD->dprBase + 0x000c), control); + + /* Wait for drawing processor */ + do + { + out8 ((pGD->isaBase + 0x3c4), 0x16); + } while (in8 (pGD->isaBase + 0x3c5) & 0x08); +} + +/******************************************************************************* + * + * Set a RGB color in the LUT (8 bit index) + */ +void video_set_lut ( + unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + register GraphicDevice *pGD = (GraphicDevice *)&smi; + + out8 (SMI_LUT_MASK, 0xff); + + out8 (SMI_LUT_START, (char)index); + + out8 (SMI_LUT_RGB, r>>2); /* red */ + udelay (10); + out8 (SMI_LUT_RGB, g>>2); /* green */ + udelay (10); + out8 (SMI_LUT_RGB, b>>2); /* blue */ + udelay (10); +} + +#endif /* CONFIG_VIDEO_SMI_LYNXEM */ diff --git a/drivers/smsc9118.c b/drivers/smsc9118.c new file mode 100755 index 000000000..afd26b5a6 --- /dev/null +++ b/drivers/smsc9118.c @@ -0,0 +1,920 @@ +//-------------------------------------------------------------------------- +// +// File name: smsc9118.c +// +// Abstract: Driver for SMSC LAN9118 ethernet controller. +// +// Start Automated RH +// *** Do not edit between "Start Automated RH" and "End Automated RH" *** +// +// Copyright 2005, Seagate Technology LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// +// Revision History +// +// *** Do not edit between "Start Automated RH" and "End Automated RH" *** +// End Automated RH +// +//-------------------------------------------------------------------------- +/*--------------------------------------------------------------------------- + * Copyright(c) 2005-2006 SMSC + * + * Use of this source code is subject to the terms of the SMSC Software + * License Agreement (SLA) under which you licensed this software product. + * If you did not accept the terms of the SLA, you are not authorized to use + * this source code. + * + * This code and information is provided as is without warranty of any kind, + * either expressed or implied, including but not limited to the implied + * warranties of merchantability and/or fitness for a particular purpose. + * + * File name : smsc9118.c + * Description : smsc9118 polled driver (non-interrupt driven) + * + * History : + * 09-27-06 MDG v1.0 (First Release) + * modified for ARM platform + *----------------------------------------------------------------------------*/ + +#include +#include +#include +#include "smsc9118.h" +#include + +#ifdef CONFIG_DRIVER_SMSC9118 + +//************************************************************************* + // FUNCTION PROTOTYPES + +//************************************************************************* +int eth_init(bd_t *bd); +void eth_halt(void); +int eth_rx(void); +int eth_send(volatile void *packet, int length); +extern void *malloc( unsigned ); // +extern void free( void * ); // + +//************************************************************************* + // LOCAL DEFINITIONS AND MACROS + +//************************************************************************* +//#define DEBUG +#define GPIO_OUT(val) (*GPIO_CFG = ((*GPIO_CFG & ~GPIO_CFG_GPIOD_MSK) | (val & GPIO_CFG_GPIOD_MSK))) +#define ENET_MAX_MTU PKTSIZE +#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN +#define NUM_RX_BUFF PKTBUFSRX +#define ENET_ADDR_LENGTH 6 +#define TX_TIMEOUT_COUNT 30 // waiting for TX_FIFO to drain + + +//************************************************************************* + // GLOBAL DATA + +//************************************************************************* +static const char date_code[] = BUILD_NUMBER; + +static char * txbp; // TX buffer pointer (only 1 buffer) +static volatile uchar * rxbp[PKTBUFSRX]; // Receiver buffer queue (IP layers) +static struct rxQue rxAvlQue[PKTBUFSRX]; // Receive buffer available queue +static int rxNdx = 0; // Current receive buffer index +static int rxNdxIn = 0; // Used for input +static int rxNdxOut = 0; // Used for output to protocol layer +static ushort lastTxTag = 0x0; +static unsigned char macAddr[ENET_ADDR_LENGTH]; + +// Temp variables +//#ifdef DEBUG +ulong MaxRxFifoSz; +ulong TotalInts = 0; +ulong TotalRXE = 0; +ulong TotalRxPackets = 0; +ulong TotalBytes = 0; +ulong EmptyReads = 0; + +ulong RxPacketBuf[400]; +ulong SWIntTriggered = FALSE; +ulong TotalRxDrop = 0; +ulong TotalPackets = 0; +ulong TotalWords = 0; +ulong TBLower1, TBLower2; +//#endif +// Temp variables + + +//************************************************************************* + // EXTERNS + +//************************************************************************* +#ifdef DEBUG +extern int use_smsc9118; +#endif + +static void lan9118_udelay(unsigned long delta) // Arg is really microseconds +{ + const unsigned long start = *FREE_RUN, // Start timing + usec = delta * (25000000/1000000); + + // usec adjusted for 25MHz on-chip clock, 1 microsecond (1/1000000) scaling + do { + delta = *FREE_RUN; + if (delta >= start) + delta = (delta - start); + else + delta = (delta - start) + 1; // use 0x100000000, not 0xffffffff + } while (delta < usec); +} + +static int MacBusy(int ReqTO) +{ + int timeout = ReqTO; + int RetVal = FALSE; // No timeout + + while (timeout--) { + if (!(*MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY)) { + goto done; + } + } + RetVal = TRUE; // Timeout +done: + return (RetVal); +} + +static ulong +GetMacReg(int Reg) +{ + ulong RegVal = 0xffffffff; + + if (*MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY) { + LAN9118_WARN("GetMacReg: previous command not complete\n"); + goto done; + } + + *MAC_CSR_CMD = MAC_RD_CMD(Reg); + DELAY(1); + + if (MacBusy(MAC_TIMEOUT) == TRUE) { + LAN9118_WARN("GetMacReg: timeout waiting for response " + "from MAC\n"); + goto done; + } + + RegVal = *MAC_CSR_DATA; +done: + return (RegVal); +} + +static int +PhyBusy(int ReqTO) +{ + int timeout = ReqTO; + int RetVal = FALSE; // No timeout + + while (timeout--) { + if (!(GetMacReg(MAC_MIIACC) & MAC_MIIACC_MII_BUSY)) { + goto done; + } + } + + RetVal = TRUE; // Timeout +done: + return (RetVal); +} + +static int +SetMacReg(int Reg, ulong Value) +{ + int RetVal = FALSE; + + if (*MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY) { + LAN9118_WARN("SetMacReg: previous command not complete\n"); + goto done; + } + + *MAC_CSR_DATA = Value; + DELAY(1); + *MAC_CSR_CMD = MAC_WR_CMD(Reg); + DELAY(1); + + if (MacBusy(MAC_TIMEOUT) == TRUE) { + LAN9118_WARN("SetMacReg: timeout waiting for response " + "from MAC\n"); + goto done; + } + + RetVal = TRUE; +done: + return (RetVal); +} + +static ushort +GetPhyReg(unchar Reg) +{ + ushort RegVal = 0xffff; + + if (GetMacReg(MAC_MIIACC) & MAC_MIIACC_MII_BUSY) { + LAN9118_WARN("GetPhyReg: MII busy\n"); + RegVal = 0; + goto done; + } + + SetMacReg(MAC_MIIACC, MAC_MII_RD_CMD((unchar)PHY_ADDR, Reg)); + DELAY(1); + + if (PhyBusy(PHY_TIMEOUT) == TRUE) { + LAN9118_WARN("GetPhyReg: timeout waiting for MII command\n"); + goto done; + } + + RegVal = (ushort)GetMacReg(MAC_MIIDATA); +done: + return (RegVal); +} + +static int +SetPhyReg(unchar Reg, ushort Value) +{ + int RetVal = FALSE; + + if (GetMacReg(MAC_MIIACC) & MAC_MIIACC_MII_BUSY) { + LAN9118_WARN("SetPhyReg: MII busy\n"); + goto done; + } + + SetMacReg(MAC_MIIDATA, Value); + DELAY(1); + SetMacReg(MAC_MIIACC, MAC_MII_WR_CMD((unchar)PHY_ADDR, Reg)); + DELAY(1); + + if (PhyBusy(PHY_TIMEOUT) == TRUE) { + LAN9118_WARN("SetPhyReg: timeout waiting for MII command\n"); + goto done; + } + + RetVal = TRUE; +done: + return (RetVal); +} + +// Display directly accessed, Control/Status Registers +static int +DumpCsrRegs(void) +{ + printf("ID_REV:\t\t0x%0.8x\n", *ID_REV); + printf("IRQ_CFG:\t0x%0.8x\n", *IRQ_CFG); + printf("INT_STS:\t0x%0.8x\n", *INT_STS); + printf("INT_EN:\t\t0x%0.8x\n", *INT_EN); + printf("BYTE_TEST:\t0x%0.8x\n", *BYTE_TEST); + printf("FIFO_INT:\t0x%0.8x\n", *FIFO_INT); + printf("RX_CFG:\t\t0x%0.8x\n", *RX_CFG); + printf("TX_CFG:\t\t0x%0.8x\n", *TX_CFG); + printf("HW_CFG:\t\t0x%0.8x\n", *HW_CFG); + printf("RX_DP_CTL:\t0x%0.8x\n", *RX_DP_CTL); + printf("RX_FIFO_INF:\t0x%0.8x\n", *RX_FIFO_INF); + printf("TX_FIFO_INF:\t0x%0.8x\n", *TX_FIFO_INF); + printf("PWR_MGMT:\t0x%0.8x\n", *PWR_MGMT); + printf("GPIO_CFG:\t0x%0.8x\n", *GPIO_CFG); + printf("GPT_CFG:\t0x%0.8x\n", *GPT_CFG); + printf("GPT_CNT:\t0x%0.8x\n", *GPT_CNT); + printf("FPGA_REV:\t0x%0.8x\n", *FPGA_REV); + printf("ENDIAN:\t\t0x%0.8x\n", *ENDIAN); + printf("FREE_RUN\t0x%0.8x\n", *FREE_RUN); + printf("RX_DROP\t\t0x%0.8x\n", *RX_DROP); + printf("MAC_CSR_CMD\t0x%0.8x\n", *MAC_CSR_CMD); + printf("MAC_CSR_DATA\t0x%0.8x\n", *MAC_CSR_DATA); + printf("AFC_CFG\t\t0x%0.8x\n", *AFC_CFG); + return (0); +} + +// Display Media Access Controller Registers +static int +DumpMacRegs(void) +{ + printf("MAC_CR\t\t0x%0.8x\n", GetMacReg(MAC_CR)); + printf("MAC_ADDRH\t0x%0.8x\n", GetMacReg(MAC_ADDRH)); + printf("MAC_ADDRL\t0x%0.8x\n", GetMacReg(MAC_ADDRL)); + printf("MAC_HASHH\t0x%0.8x\n", GetMacReg(MAC_HASHH)); + printf("MAC_HASHL\t0x%0.8x\n", GetMacReg(MAC_HASHL)); + printf("MAC_MIIACC\t0x%0.8x\n", GetMacReg(MAC_MIIACC)); + printf("MAC_MIIDATA\t0x%0.8x\n", GetMacReg(MAC_MIIDATA)); + printf("MAC_FLOW\t0x%0.8x\n", GetMacReg(MAC_FLOW)); + printf("MAC_VLAN1\t0x%0.8x\n", GetMacReg(MAC_VLAN1)); + printf("MAC_VLAN2\t0x%0.8x\n", GetMacReg(MAC_VLAN2)); + printf("MAC_WUFF\t0x%0.8x\n", GetMacReg(MAC_WUFF)); + printf("MAC_WUCSR\t0x%0.8x\n", GetMacReg(MAC_WUCSR)); + return (0); +} + +// Display PHYsical media interface registers +static int +DumpPhyRegs(void) +{ + printf("PHY_BCR\t\t0x%0.4x\n", GetPhyReg(PHY_BCR)); + printf("PHY_BSR\t\t0x%0.4x\n", GetPhyReg(PHY_BSR)); + printf("PHY_ID1\t\t0x%0.4x\n", GetPhyReg(PHY_ID1)); + printf("PHY_ID2\t\t0x%0.4x\n", GetPhyReg(PHY_ID2)); + printf("PHY_ANAR\t0x%0.4x\n", GetPhyReg(PHY_ANAR)); + printf("PHY_ANLPAR\t0x%0.4x\n", GetPhyReg(PHY_ANLPAR)); + printf("PHY_ANEXPR\t0x%0.4x\n", GetPhyReg(PHY_ANEXPR)); + printf("PHY_SILREV\t0x%0.4x\n", GetPhyReg(PHY_SILREV)); + printf("PHY_MCSR\t0x%0.4x\n", GetPhyReg(PHY_MCSR)); + printf("PHY_SPMODES\t0x%0.4x\n", GetPhyReg(PHY_SPMODES)); + printf("PHY_CSIR\t0x%0.4x\n", GetPhyReg(PHY_CSIR)); + printf("PHY_ISR\t\t0x%0.4x\n", GetPhyReg(PHY_ISR)); + printf("PHY_IMR\t\t0x%0.4x\n", GetPhyReg(PHY_IMR)); + printf("PHY_PHYSCSR\t0x%0.4x\n", GetPhyReg(PHY_PHYSCSR)); + return (0); +} + +static int +lan9118_open(bd_t *bis) +{ + int RetVal = TRUE; + int timeout; + int i; + static unsigned mac_addrh = 0, mac_addrl = 0; + +#ifdef DEBUG + TotalInts = 0; + TotalRXE = 0; + TotalBytes = 0; + + printf("DRIVER_VERSION : %X, ", DRIVER_VERSION); + printf("DATECODE : %s\r\n", BUILD_NUMBER); + + if (bis->bi_bootflags & 0x40000000) { + use_smsc9118 = 1; + } +#endif //DEBUG + + // Because we just came out of h/w reset we can't be sure that + // the chip has completed reset and may have to implement the + // workaround for Errata 5, stepping A0. Therefore we need to + // check the ID_REV in little endian, the reset default. + if (((*ID_REV & ID_REV_ID_MASK) == ID_REV_CHIP_118) || + ((*ID_REV & ID_REV_ID_MASK) == ID_REV_CHIP_218) || + ((*ID_REV & ID_REV_ID_MASK) == ID_REV_CHIP_211) || + ((*ID_REV & ID_REV_ID_MASK) == ID_REV_CHIP_221)) + { + printf("LAN9x18 (0x%08x) detected.\n", *ID_REV); + } + else + { + printf("Failed to detect LAN9118. ID_REV = 0x%08x\n", *ID_REV); + RetVal = FALSE; + goto done; + } + + // Does SoftReset to 118 + *HW_CFG = HW_CFG_SRST; + DELAY(10); + + // Is the internal PHY running? + if ((*PWR_MGMT & PWR_MGMT_PM_MODE_MSK) != 0) { + // Apparently not... + *BYTE_TEST = 0x0; // Wake it up + DELAY(1); + timeout = PHY_TIMEOUT; + while (timeout-- && ((*PWR_MGMT & PWR_MGMT_PME_READY) == 0)) { + lan9118_udelay(1); + } + if ((*PWR_MGMT & PWR_MGMT_PME_READY) == 0) { + LAN9118_WARN("LAN9118: PHY not ready"); + LAN9118_WARN(" - aborting\n"); + RetVal = FALSE; + goto done; + } + } + + // Setup TX and RX resources. + + // There is one TX buffer. + if ((txbp = (char *)malloc(ENET_MAX_MTU_ALIGNED)) == NULL) { + LAN9118_WARN("lan9118_open: can't get TX buffer\n"); + goto cleanup; + } + + // The receive buffers are allocated and aligned by upper layer + // software. + for (i = 0; i < PKTBUFSRX; i++) { + rxbp[i] = NetRxPackets[i]; + rxAvlQue[i].index = -1; + } + + rxNdx = 0; + rxNdxIn = 0; + rxNdxOut = 0; + lastTxTag = 0x0; + + // Set TX Fifo Size + *HW_CFG = 0x00040000; // 4K for TX + + // This value is dependent on TX Fifo Size since there's a limited + // amount of Fifo space. + MaxRxFifoSz = 13440; // Decimal + + // Set automatic flow control. + *AFC_CFG = 0x008c46af; + + // Flash LEDs. + *GPIO_CFG = 0x70700000; + + // Disable interrupts until the rest of initialization is complete. + *INT_EN = 0x0; // Clear interrupt enables + *INT_STS = 0xffffffff; // Clear pending interrupts + *IRQ_CFG = 0x00000001; // IRQ disable + + // Enable flow control and pause frame time + SetMacReg(MAC_FLOW, 0xffff0002); + + // Set MAC address, if octet 0 is non-null assume it's all good. + memcpy(macAddr, bis->bi_enetaddr, ENET_ADDR_LENGTH); + if (mac_addrh != 0 || mac_addrl != 0) { + printf("Setting mac address: %02x:%02x:%02x:%02x:%02x:%02x\n", + macAddr[0], macAddr[1], macAddr[2], + macAddr[3], macAddr[4], macAddr[5]); + mac_addrh = macAddr[5] << 8 | macAddr[4]; + mac_addrl = macAddr[3] << 24 | macAddr[2] << 16 | + macAddr[1] << 8 | macAddr[0]; + SetMacReg(MAC_ADDRH, mac_addrh); + SetMacReg(MAC_ADDRL, mac_addrl); + } else { + char s_env_mac[64]; + char *env_var; + + mac_addrl = *((unsigned int *)macAddr) = GetMacReg(MAC_ADDRL); + mac_addrh = *((unsigned int *)macAddr + 1) = GetMacReg(MAC_ADDRH); + + if ( (GetMacReg(MAC_ADDRL) == 0xffffffff) && (GetMacReg(MAC_ADDRH) == 0xffff) ) { + + /* Case: No Mac id in EEPROM : Bad case */ + env_var = getenv("ethaddr"); + + if (env_var == NULL) { + /* No ethaddr env */ + printf("\n*** ERROR: Mac id is not programmed in EEPROM\n"); + printf("\tsetenv ethaddr 'xx:xx:xx:xx:xx:xx';saveenv"); + printf("\n Then reboot u-boot for NFS to work\n\n"); + RetVal = -1; + goto done; + } + else { + /* Get env var and populate macAddr */ + unsigned char len, i; + + len = strlen(env_var); + strcpy(s_env_mac,env_var); + // Format xx:xx:xx:xx:xx:xx + // Convert to digits: back to school days + for(i=0; i= 'A') && (s_env_mac[i] <= 'F') ) { + s_env_mac[i] -= 'A'; + s_env_mac[i] += 0xa; + } else if ( (s_env_mac[i] >= 'a') && (s_env_mac[i] <= 'f') ){ + s_env_mac[i] -= 'a'; + s_env_mac[i] += 0xa; + } else if ( (s_env_mac[i] >= '0') && (s_env_mac[i] <= '9') ){ + s_env_mac[i] -= '0'; + } else { + printf("\n wrong hex digit %c\n", s_env_mac[i]); + RetVal = -1; + goto done; + } + } + + macAddr[0] = 16*s_env_mac[0] + s_env_mac[1]; + macAddr[1] = 16*s_env_mac[3] + s_env_mac[4]; + macAddr[2] = 16*s_env_mac[6] + s_env_mac[7]; + macAddr[3] = 16*s_env_mac[9] + s_env_mac[10]; + macAddr[4] = 16*s_env_mac[12] + s_env_mac[13]; + macAddr[5] = 16*(s_env_mac[15]) + s_env_mac[16]; + } + } + + sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", + macAddr[0], macAddr[1], macAddr[2], macAddr[3], + macAddr[4], macAddr[5]); + printf("Read mac address: %s\n", s_env_mac); + setenv ("ethaddr", s_env_mac); + memcpy(bis->bi_enetaddr, macAddr, ENET_ADDR_LENGTH); + } + + // Dump old status and data + *TX_CFG = (TX_CFG_TXS_DUMP | TX_CFG_TXD_DUMP); + *RX_CFG = (RX_CFG_FORCE_DISCARD); + + // Initialize Tx parameters + *HW_CFG = ((*HW_CFG & HW_CFG_TX_FIF_SZ_MSK) | HW_CFG_SF); + *FIFO_INT = FIFO_INT_TDAL_MSK; // Max out value + *INT_EN |= INT_EN_TDFA_INT_EN; + { + // Disable MAC heartbeat SQE and enable MAC transmitter + ulong macCR = GetMacReg(MAC_CR); + macCR |= (MAC_CR_TXEN | MAC_CR_HBDIS); + macCR &= ~MAC_CR_PRMS; // Turn off promiscuous mode + macCR |= MAC_CR_BCAST; // Don't accept broadcast frames + SetMacReg(MAC_CR, macCR); + } + + // Initialize Rx parameters + *RX_CFG = 0x00000000; // 4byte end-alignment + { + // Enable receiver. + ulong macCR = GetMacReg(MAC_CR); + SetMacReg(MAC_CR, (macCR | MAC_CR_RXEN)); + } + *FIFO_INT = ((*FIFO_INT & 0xffff0000) | 0x00000101); + *INT_EN |= (INT_EN_RSFL_INT_EN | INT_EN_RXE_INT_EN); + *INT_EN |= INT_EN_RXDFH_INT_EN; + + // Initialize PHY parameters +#if 1 + if (((GetPhyReg(PHY_ID1) == PHY_ID1_LAN9118) && + (GetPhyReg(PHY_ID2) == PHY_ID2_LAN9118)) || + ((GetPhyReg(PHY_ID1) == PHY_ID1_LAN9218) && + (GetPhyReg(PHY_ID2) == PHY_ID2_LAN9218))) +#else + if(1) +#endif + { + // Reset the PHY + SetPhyReg(PHY_BCR, PHY_BCR_RST); + timeout = PHY_TIMEOUT; + lan9118_udelay(50*1000); // > 50ms + while(timeout-- && (GetPhyReg(PHY_BCR) & PHY_BCR_RST)) + { + lan9118_udelay(10); + } + if (timeout == 0) + { + LAN9118_WARN("PHY reset incomplete\n"); + RetVal = FALSE; + goto done; + } + + // Setup and start auto negotiation + { + ushort anar; + ushort bcr; + char * spddplx; + + anar = GetPhyReg(PHY_ANAR); + anar &= ~PHY_ANAR_PAUSE_OP_MSK; + anar |= PHY_ANAR_PAUSE_OP_BOTH; + anar |= (PHY_ANAR_10_FDPLX | PHY_ANAR_10_ABLE | + PHY_ANAR_100_TX_FDPLX | PHY_ANAR_100_TX_ABLE); + SetPhyReg(PHY_ANAR, anar); + + DELAY(2); + bcr = GetPhyReg(PHY_BCR); + bcr |= (PHY_BCR_SS | PHY_BCR_FDPLX); + SetPhyReg(PHY_BCR, bcr); + DELAY(2); + + printf("start Auto negotiation... (take ~2sec)\n"); + bcr = GetPhyReg(PHY_BCR); + bcr |= (PHY_BCR_ANE | PHY_BCR_RSTAN); + SetPhyReg(PHY_BCR, bcr); + DELAY(2); + + timeout = PHY_AN_TIMEOUT; + while((timeout--) && ((GetPhyReg(PHY_BSR) & PHY_BSR_ANC) == 0)) { + lan9118_udelay(500000); + } + if ((GetPhyReg(PHY_BSR) & PHY_BSR_ANC) == 0) { + LAN9118_WARN("Auto negotiation failed\n"); + RetVal = FALSE; + goto done; + } + + if ((GetPhyReg(PHY_BSR) & PHY_BSR_LINK_STATUS) == 0) { + LAN9118_WARN("Link down\n"); + RetVal = FALSE; + goto done; + } + + switch ((GetPhyReg(PHY_PHYSCSR) & PHY_PHYSCSR_SPEED_MSK)>>2) { + case 0x01: + spddplx = "10BaseT, half duplex"; + break; + case 0x02: + spddplx = "100BaseTX, half duplex"; + break; + case 0x05: + spddplx = "10BaseT, full duplex"; + break; + case 0x06: + spddplx = "100BaseTX, full duplex"; + break; + default: + spddplx = "Unknown"; + break; + } + printf("Auto negotiation complete, %s\n", spddplx); + } + + // If PHYs auto negotiated for full duplex, enable full duplex in MAC. + if ((GetPhyReg(PHY_ANAR) & GetPhyReg(PHY_ANLPAR)) & 0x0140) { + SetMacReg(MAC_CR, (GetMacReg(MAC_CR) | 0x00100000)); + } + // correct PHY_ID is detected + goto done; + } + else + { + printf("Unknown PHY ID : 0x%x, 0x%x\n", GetPhyReg(PHY_ID1), GetPhyReg(PHY_ID2)); + } + + goto done; + +cleanup: + if (txbp != NULL) { + free(txbp); + } + +done: + return (RetVal); +} + +static void +lan9118_close(void) +{ + // Release the TX buffer. + if (txbp != NULL) { + free(txbp); + } + txbp = NULL; +} + +static int +lan9118_read(void) +{ + int curBufNdx; + int loopCount = 0; + ulong rxStatus; + ulong count; + ulong len; + int ffwdOk = TRUE; + int timeout; + int handled = 0; + + while((*RX_FIFO_INF & 0x00ff0000) != 0) { + if (loopCount >= NUM_RX_BUFF) { +//printf("read: loopCount exceeded\n"); + break; // Packet buffers full + } + + curBufNdx = rxNdx; + loopCount++; + if (++rxNdx >= NUM_RX_BUFF) { + rxNdx = 0; // Wrap buffer slot # + } + + rxStatus = *RX_STATUS_FIFO_PORT; + len = count = rxStatus >> 16; + + if (count >= 4*sizeof(ulong)) { + ffwdOk = TRUE; // Use h/w to toss packet + } else { + ffwdOk = FALSE; // Have to empty manually on error + } + + if (count != 0) { + if (count > ENET_MAX_MTU) { + count = 0; + } else { + if ((rxStatus & TX_STATUS_FIFO_ES) != 0) { + count = 0; + } + } + } + + if (count == 0) { + if (ffwdOk == TRUE) { + // Drain it the fast way + *RX_DP_CTL = RX_DP_FFWD; + timeout = FFWD_TIMEOUT; + while (timeout-- && (*RX_DP_CTL & RX_DP_FFWD)) { + lan9118_udelay(1); + } + if ((*RX_DP_CTL & RX_DP_FFWD) != 0) { + LAN9118_WARN("lan9118_read: fast " + "forward op failed\n"); + break; + } + } else { + // Drain it manually + while (len--) { + volatile ulong tmp; + tmp = *RX_FIFO_PORT; + } + } + } else if (rxAvlQue[rxNdxIn].index != -1) { + LAN9118_WARN("lan9118_read: read buffers full!\n"); + break; + } else { + register ulong *rxbpl; + int ndx; + + TotalRxPackets++; + TotalBytes += count; + rxAvlQue[rxNdxIn].index = curBufNdx; + rxAvlQue[rxNdxIn].len = count; + if (++rxNdxIn >= NUM_RX_BUFF) { + rxNdxIn = 0; + } + + // Copy this packet to a NetRxPacket buffer + handled = 1; +//printf("read: %d empty reads prior to this one\n", EmptyReads); + EmptyReads = 0; + rxbpl = (ulong *)rxbp[curBufNdx]; + for (ndx = (count+3)/sizeof(ulong); ndx > 0; ndx--) { + *rxbpl++ = *RX_FIFO_PORT; + } +#if 0 +{ + printf("Received: packet contents follows.\n"); + int i; + for (i = 1; i <= count; i++) { + printf("0x%02x ", rxbp[curBufNdx][i-1]); + if (!(i%16)) + printf("\n"); + } + printf("\n"); +} +#endif + DELAY(3); + } + } + + if (handled) { + for (;;) { + curBufNdx = rxAvlQue[rxNdxOut].index; + if (curBufNdx == -1) { + len = -1; // Nothing else received +//printf("read: nothing else received: rxNdxOut: %d curBufNdx: %d\n", rxNdxOut, curBufNdx); + break; + } + len = rxAvlQue[rxNdxOut].len; +//printf("read: sending a packet up: rxNdxOut: %d curBufNdx: %d\n", rxNdxOut, curBufNdx); + NetReceive(NetRxPackets[curBufNdx], len - 4); + rxAvlQue[rxNdxOut].index = -1; // Free buffer + if (++rxNdxOut >= NUM_RX_BUFF) { + rxNdxOut = 0; // Handle wrap + } + } + } else { + EmptyReads++; + return (-1); // Nothing was received + } + + return (len); +} + + +static int sendToNet(uchar * txbp, int len) +{ + ulong tx_cmd_a, tx_cmd_b; + int i; + ulong * txbpl = (ulong *)txbp; + + lastTxTag++; + +#if DEBUG + { + printf("sendToNet: packet contents follows.\n"); + int i; + int j = 0; + for (i = 0; i < len; i++) { + if (++j == 20) { + j = 0; + printf("\n"); + } + printf("%0.1x ", txbp[i]); + } + printf("\n"); + +// printf("sendToNet: peek TX status: 0x%0.8x\n", +// *TX_STATUS_FIFO_PEEK); + } +#endif // DEBUG + + tx_cmd_a = (((ulong)txbp & 0x3) << 16) | 0x00003000 | len; + tx_cmd_b = (lastTxTag << 16) | len; + +#if DEBUG + printf("sendToNet: tx_cmd_a: 0x%0.8x tx_cmd_b: 0x%0.8x\n", + tx_cmd_a, tx_cmd_b); +#endif // DEBUG + + *TX_FIFO_PORT = tx_cmd_a; + *TX_FIFO_PORT = tx_cmd_b; + + for (i = (len+3)/sizeof(ulong); i > 0; i--) { + *TX_FIFO_PORT = *txbpl++; + } + + *TX_CFG = TX_CFG_TX_ON; // Enable transmitter + + return (TRUE); +} + +static int lan9118_write(volatile void *ptr, int len) +{ + ulong startTime; + ulong timeout; + char statusStr[64]; + + if (len > ENET_MAX_MTU) { + len = ENET_MAX_MTU; + } + + // Copy the packet. + memcpy((void *)txbp, (void *)ptr, len); + + // Drain the TX status fifo just in case there are old (good) statuses. + for (timeout=0; timeout TX_TIMEOUT) { + return (-1); + } + } else { + ulong txStatus = *TX_STATUS_FIFO_PORT; + + if ((txStatus & TX_STATUS_FIFO_ES) == TX_STATUS_FIFO_ES) { + sprintf(statusStr, "lan9118_write: error " + "status: 0x%0.8x\n", txStatus); + LAN9118_WARN(statusStr); + return (-1); + } else { + *TX_CFG |= TX_CFG_STOP_TX; // Stop transmitter + return (len); // successful send + } + } + } +} + +int eth_init(bd_t *bd) +{ + return lan9118_open(bd); +} + +void eth_halt(void) +{ + lan9118_close(); +} + +int eth_rx(void) +{ + int r; + + r = lan9118_read(); + + return r; +} + +int eth_send(volatile void *packet, int length) +{ + return lan9118_write(packet, length); +} + +#endif // #ifdef CONFIG_DRIVER_SMSC9118 diff --git a/drivers/smsc9118.h b/drivers/smsc9118.h new file mode 100644 index 000000000..c338f58b7 --- /dev/null +++ b/drivers/smsc9118.h @@ -0,0 +1,490 @@ +//-------------------------------------------------------------------------- +// +// File name: smsc9118.h +// +// Abstract: Address map and register definitions for SMSC LAN9118 +// ethernet controller. +// +// Start Automated RH +// *** Do not edit between "Start Automated RH" and "End Automated RH" *** +// +// Copyright 2005, Seagate Technology LLC +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// +// Revision History +// +// *** Do not edit between "Start Automated RH" and "End Automated RH" *** +// End Automated RH +// +// +//-------------------------------------------------------------------------- +/*--------------------------------------------------------------------------- + * Copyright(c) 2005-2006 SMSC + * + * Use of this source code is subject to the terms of the SMSC Software + * License Agreement (SLA) under which you licensed this software product. + * If you did not accept the terms of the SLA, you are not authorized to use + * this source code. + * + * This code and information is provided as is without warranty of any kind, + * either expressed or implied, including but not limited to the implied + * warranties of merchantability and/or fitness for a particular purpose. + * + * File name : smsc9118.c + * Description : smsc9118 polled driver (non-interrupt driven) + * + * History : + * 09-27-06 MDG First Release + * modified for ARM platform + *----------------------------------------------------------------------------*/ + +#ifdef CONFIG_DRIVER_SMSC9118 + +//************************************************************************* + // GLOBAL DEFINITIONS + +//************************************************************************* +#define LAN9118_WARN(s) (printf("%s", s)) + +#define DRIVER_VERSION 0x101 +#define BUILD_NUMBER "092706" + +//************************************************************************* + // DATA STRUCTURE DEFINITIONS + +//************************************************************************* + + +#ifndef _SMSC9118_H +#define _SMSC9118_H + +#ifndef CONFIG_SMSC9118_BASE +#error "CONFIG_SMSC9118_BASE is not defined." +#else +#define SMSC9118_BASE CONFIG_SMSC9118_BASE +#endif + +#define MAC_TIMEOUT 200 +#define PHY_TIMEOUT 200 +//#define PHY_AN_TIMEOUT 3000 * 1000 // 3 seconds +#define PHY_AN_TIMEOUT 10 // 3 seconds +#define SRST_TIMEOUT 100 +#define TX_TIMEOUT 3000 // 3000 * 1/HZ +#define FFWD_TIMEOUT 100 +#define PHY_ADDR 1 +#define FALSE 0 +#define TRUE 1 + +#define DELAY(n) ( { \ + int _i = 100*n; \ + do { \ + volatile ulong _temp; \ + _temp = *BYTE_TEST; \ + } while (--_i); \ + } ) + +struct rxQue { + int index; // Index into NetRxPackets[] + int len; // Length of packet at this index +}; + +// Lan9118 memory map + +// Control/Status Register Map (directly addressable registers) +#define RX_FIFO_PORT (volatile ulong *)(SMSC9118_BASE + 0x0) +#define RX_FIFO_ALIAS_PORTS (volatile ulong *)(SMSC9118_BASE + 0x4) +#define TX_FIFO_PORT (volatile ulong *)(SMSC9118_BASE + 0x20) +#define TX_FIFO_ALIAS_PORTS (volatile ulong *)(SMSC9118_BASE + 0x24) +#define RX_STATUS_FIFO_PORT (volatile ulong *)(SMSC9118_BASE + 0x40) +#define RX_STATUS_FIFO_PEEK (volatile ulong *)(SMSC9118_BASE + 0x44) +#define TX_STATUS_FIFO_PORT (volatile ulong *)(SMSC9118_BASE + 0x48) +#define TX_STATUS_FIFO_PEEK (volatile ulong *)(SMSC9118_BASE + 0x4C) +#define TX_STATUS_FIFO_ES (0x00008000) +#define TX_STATUS_FIFO_TAG_MSK (0xffff0000) + +#define ID_REV (volatile ulong *)(SMSC9118_BASE + 0x50) +#define ID_REV_ID_MASK (0xFFFF0000) +#define ID_REV_CHIP_118 (0x01180000) +#define ID_REV_CHIP_218 (0x118A0000) +#define ID_REV_CHIP_211 (0x92110000) +#define ID_REV_CHIP_221 (0x92210000) +#define ID_REV_REV_MASK (0x0000FFFF) + +#define IRQ_CFG (volatile ulong *)(SMSC9118_BASE + 0x54) +#define IRQ_CFG_MASTER_INT (0x00001000) +#define IRQ_CFG_ENABLE (0x00000100) +#define IRQ_CFG_IRQ_POL_HIGH (0x00000010) +#define IRQ_CFG_IRQ_TYPE_PUPU (0x00000001) + +#define INT_STS (volatile ulong *)(SMSC9118_BASE + 0x58) +#define INT_STS_SW_INT (0x80000000) +#define INT_STS_TXSTOP_INT (0x02000000) +#define INT_STS_RXSTOP_INT (0x01000000) +#define INT_STS_RXDFH_INT (0x00800000) +#define INT_STS_RXDF_INT (0x00400000) +#define INT_STS_TIOC_INT (0x00200000) +#define INT_STS_GPT_INT (0x00080000) +#define INT_STS_PHY_INT (0x00040000) +#define INT_STS_PMT_INT (0x00020000) +#define INT_STS_TXSO_INT (0x00010000) +#define INT_STS_RWT_INT (0x00008000) +#define INT_STS_RXE_INT (0x00004000) +#define INT_STS_TXE_INT (0x00002000) +#define INT_STS_ERX_INT (0x00001000) +#define INT_STS_TDFU_INT (0x00000800) +#define INT_STS_TDFO_INT (0x00000400) +#define INT_STS_TDFA_INT (0x00000200) +#define INT_STS_TSFF_INT (0x00000100) +#define INT_STS_TSFL_INT (0x00000080) +#define INT_STS_RDFO_INT (0x00000040) +#define INT_STS_RDFL_INT (0x00000020) +#define INT_STS_RSFF_INT (0x00000010) +#define INT_STS_RSFL_INT (0x00000008) +#define INT_STS_GPIO2_INT (0x00000004) +#define INT_STS_GPIO1_INT (0x00000002) +#define INT_STS_GPIO0_INT (0x00000001) + +#define INT_EN (volatile ulong *)(SMSC9118_BASE + 0x5C) +#define INT_EN_SW_INT_EN (0x80000000) +#define INT_EN_TXSTOP_INT_EN (0x02000000) +#define INT_EN_RXSTOP_INT_EN (0x01000000) +#define INT_EN_RXDFH_INT_EN (0x00800000) +#define INT_EN_RXDF_INT_EN (0x00400000) +#define INT_EN_TIOC_INT_EN (0x00200000) +#define INT_EN_GPT_INT_EN (0x00080000) +#define INT_EN_PHY_INT_EN (0x00040000) +#define INT_EN_PMT_INT_EN (0x00020000) +#define INT_EN_TXSO_INT_EN (0x00010000) +#define INT_EN_RWT_INT_EN (0x00008000) +#define INT_EN_RXE_INT_EN (0x00004000) +#define INT_EN_TXE_INT_EN (0x00002000) +#define INT_EN_ERX_INT_EN (0x00001000) +#define INT_EN_TDFU_INT_EN (0x00000800) +#define INT_EN_TDFO_INT_EN (0x00000400) +#define INT_EN_TDFA_INT_EN (0x00000200) +#define INT_EN_TSFF_INT_EN (0x00000100) +#define INT_EN_TSFL_INT_EN (0x00000080) +#define INT_EN_RDFO_INT_EN (0x00000040) +#define INT_EN_RDFL_INT_EN (0x00000020) +#define INT_EN_RSFF_INT_EN (0x00000010) +#define INT_EN_RSFL_INT_EN (0x00000008) +#define INT_EN_GPIO2_EN (0x00000004) +#define INT_EN_GPIO1_EN (0x00000002) +#define INT_EN_GPIO0_EN (0x00000001) + +#define BYTE_TEST (volatile ulong *)(SMSC9118_BASE + 0x64) +#define BYTE_TEST_VAL (0x87654321) + +#define FIFO_INT (volatile ulong *)(SMSC9118_BASE + 0x68) +#define FIFO_INT_TDAL_MSK (0xFF000000) +#define FIFO_INT_TSL_MSK (0x00FF0000) +#define FIFO_INT_RDAL_MSK (0x0000FF00) +#define FIFO_INT_RSL_MSK (0x000000FF) + +#define RX_CFG (volatile ulong *)(SMSC9118_BASE + 0x6C) +#define RX_CFG_END_ALIGN4 (0x00000000) +#define RX_CFG_END_ALIGN16 (0x40000000) +#define RX_CFG_END_ALIGN32 (0x80000000) +#define RX_CFG_FORCE_DISCARD (0x00008000) +#define RX_CFG_RXDOFF_MSK (0x00003C00) +#define RX_CFG_RXBAD (0x00000001) + +#define TX_CFG (volatile ulong *)(SMSC9118_BASE + 0x70) +#define TX_CFG_TXS_DUMP (0x00008000) +#define TX_CFG_TXD_DUMP (0x00004000) +#define TX_CFG_TXSAO (0x00000004) +#define TX_CFG_TX_ON (0x00000002) +#define TX_CFG_STOP_TX (0x00000001) + +#define HW_CFG (volatile ulong *)(SMSC9118_BASE + 0x74) +#define HW_CFG_TTM (0x00200000) +#define HW_CFG_SF (0x00100000) +#define HW_CFG_TX_FIF_SZ_MSK (0x000F0000) +#define HW_CFG_TR_MSK (0x00003000) +#define HW_CFG_BITMD_MSK (0x00000004) +#define HW_CFG_BITMD_32 (0x00000004) +#define HW_CFG_SRST_TO (0x00000002) +#define HW_CFG_SRST (0x00000001) + +#define RX_DP_CTL (volatile ulong *)(SMSC9118_BASE + 0x78) +#define RX_DP_FFWD (0x80000000) +#define RX_DP_RX_FFWD_MSK (0x00000FFF) + +#define RX_FIFO_INF (volatile ulong *)(SMSC9118_BASE + 0x7C) +#define RX_FIFO_RXSUSED_MSK (0x00FF0000) +#define RX_FIFO_RXDUSED_MSK (0x0000FFFF) + +#define TX_FIFO_INF (volatile ulong *)(SMSC9118_BASE + 0x80) +#define TX_FIFO_TXSUSED_MSK (0x00FF0000) +#define TX_FIFO_TDFREE_MSK (0x0000FFFF) + +#define PWR_MGMT (volatile ulong *)(SMSC9118_BASE + 0x84) +#define PWR_MGMT_PM_MODE_MSK (0x00030000) +#define PWR_MGMT_PM_MODE_MSK_LE (0x00000003) +#define PWR_MGMT_PM__D0 (0x00000000) +#define PWR_MGMT_PM__D1 (0x00010000) +#define PWR_MGMT_PM__D2 (0x00020000) +#define PWR_MGMT_PHY_RST (0x00000400) +#define PWR_MGMT_WOL_EN (0x00000200) +#define PWR_MGMT_ED_EN (0x00000100) +#define PWR_MGMT_PME_TYPE_PUPU (0x00000040) +#define PWR_MGMT_WUPS_MSK (0x00000030) +#define PWR_MGMT_WUPS_NOWU (0x00000000) +#define PWR_MGMT_WUPS_D2D0 (0x00000010) +#define PWR_MGMT_WUPS_D1D0 (0x00000020) +#define PWR_MGMT_WUPS_UNDEF (0x00000030) +#define PWR_MGMT_PME_IND_PUL (0x00000008) +#define PWR_MGMT_PME_POL_HIGH (0x00000004) +#define PWR_MGMT_PME_EN (0x00000002) +#define PWR_MGMT_PME_READY (0x00000001) + +#define GPIO_CFG (volatile ulong *)(SMSC9118_BASE + 0x88) +#define GPIO_CFG_LEDx_MSK (0x70000000) +#define GPIO_CFG_LED1_EN (0x10000000) +#define GPIO_CFG_LED2_EN (0x20000000) +#define GPIO_CFG_LED3_EN (0x40000000) +#define GPIO_CFG_GPIOBUFn_MSK (0x00070000) +#define GPIO_CFG_GPIOBUF0_PUPU (0x00010000) +#define GPIO_CFG_GPIOBUF1_PUPU (0x00020000) +#define GPIO_CFG_GPIOBUF2_PUPU (0x00040000) +#define GPIO_CFG_GPDIRn_MSK (0x00000700) +#define GPIO_CFG_GPIOBUF0_OUT (0x00000100) +#define GPIO_CFG_GPIOBUF1_OUT (0x00000200) +#define GPIO_CFG_GPIOBUF2_OUT (0x00000400) +#define GPIO_CFG_GPIOD_MSK (0x00000007) +#define GPIO_CFG_GPIOD0 (0x00000001) +#define GPIO_CFG_GPIOD1 (0x00000002) +#define GPIO_CFG_GPIOD2 (0x00000004) + +#define GPT_CFG (volatile ulong *)(SMSC9118_BASE + 0x8C) +#define GPT_CFG_TIMER_EN (0x20000000) +#define GPT_CFG_GPT_LOAD_MSK (0x0000FFFF) + +#define GPT_CNT (volatile ulong *)(SMSC9118_BASE + 0x90) +#define GPT_CNT_MSK (0x0000FFFF) + +#define FPGA_REV (volatile ulong *)(SMSC9118_BASE + 0x94) + +#define ENDIAN (volatile ulong *)(SMSC9118_BASE + 0x98) +#define ENDIAN_BIG (0xFFFFFFFF) + +#define FREE_RUN (volatile ulong *)(SMSC9118_BASE + 0x9C) +#define FREE_RUN_FR_CNT_MSK (0xFFFFFFFF) + +#define RX_DROP (volatile ulong *)(SMSC9118_BASE + 0xA0) +#define RX_DROP_RX_DFC_MSK (0xFFFFFFFF) + +#define MAC_CSR_CMD (volatile ulong *)(SMSC9118_BASE + 0xA4) +#define MAC_CSR_CMD_CSR_BUSY (0x80000000) +#define MAC_CSR_CMD_RNW (0x40000000) +#define MAC_RD_CMD(Reg) ((Reg & 0x000000FF) | \ + (MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_RNW)) +#define MAC_WR_CMD(Reg) ((Reg & 0x000000FF) | \ + (MAC_CSR_CMD_CSR_BUSY)) + +#define MAC_CSR_DATA (volatile ulong *)(SMSC9118_BASE + 0xA8) + +#define AFC_CFG (volatile ulong *)(SMSC9118_BASE + 0xAC) +#define AFC_CFG_AFC_HI_MSK (0x00FF0000) +#define AFC_CFG_AFC_LO_MSK (0x0000FF00) + +#define E2P_CMD (volatile ulong *)(SMSC9118_BASE + 0xB0) +#define E2P_DATA (volatile ulong *)(SMSC9118_BASE + 0xB4) + +// MAC Control and Status Registers (accessed through MAC_CSR_CMD/_DATA regs) +#define MAC_CR (0x1) +#define MAC_CR_RXALL (0x80000000) +#define MAC_CR_HBDIS (0x10000000) +#define MAC_CR_RCVOWN (0x00800000) +#define MAC_CR_LOOPBK (0x00200000) +#define MAC_CR_FDPX (0x00100000) +#define MAC_CR_MCPAS (0x00080000) +#define MAC_CR_PRMS (0x00040000) +#define MAC_CR_INVFILT (0x00020000) +#define MAC_CR_PASSBAD (0x00010000) +#define MAC_CR_HFILT (0x00008000) +#define MAC_CR_HPFILT (0x00002000) +#define MAC_CR_LCOLL (0x00001000) +#define MAC_CR_BCAST (0x00000800) +#define MAC_CR_DISRTY (0x00000400) +#define MAC_CR_PADSTR (0x00000100) +#define MAC_CR_BOLMT_MSK (0x000000C0) +#define MAC_CR_BOLMT_10 (0x00000000) +#define MAC_CR_BOLMT_8 (0x00000040) +#define MAC_CR_BOLMT_4 (0x00000080) +#define MAC_CR_BOLMT_1 (0x000000C0) +#define MAC_CR_DFCHK (0x00000020) +#define MAC_CR_TXEN (0x00000008) +#define MAC_CR_RXEN (0x00000004) + +#define MAC_ADDRH (0x2) +#define MAC_ADDRH_MSK (0x0000FFFF) + +#define MAC_ADDRL (0x3) +#define MAC_ADDRL_MSK (0xFFFFFFFF) + +#define MAC_HASHH (0x4) +#define MAC_HASHH_MSK (0xFFFFFFFF) + +#define MAC_HASHL (0x5) +#define MAC_HASHL_MSK (0xFFFFFFFF) + +#define MAC_MIIACC (0x6) +#define MAC_MIIACC_MII_WRITE (0x00000002) +#define MAC_MIIACC_MII_BUSY (0x00000001) +#define MAC_MII_RD_CMD(Addr,Reg) (((Addr & 0x1f) << 11) | \ + ((Reg & 0x1f)) << 6) +#define MAC_MII_WR_CMD(Addr,Reg) (((Addr & 0x1f) << 11) | \ + ((Reg & 0x1f) << 6) | \ + MAC_MIIACC_MII_WRITE) + +#define MAC_MIIDATA (0x7) +#define MAC_MIIDATA_MSK (0x0000FFFF) +#define MAC_MII_DATA(Data) (Data & MAC_MIIDATA_MSK) + +#define MAC_FLOW (0x8) +#define MAC_FLOW_FCPT_MSK (0xFFFF0000) +#define MAC_FLOW_FCPASS (0x00000004) +#define MAC_FLOW_FCEN (0x00000002) +#define MAC_FLOW_FCBSY (0x00000001) + +#define MAC_VLAN1 (0x9) +#define MAC_VLAN2 (0xA) +#define MAC_WUFF (0xB) + +#define MAC_WUCSR (0xC) +#define MAC_WUCSR_GUE (0x00000200) +#define MAC_WUCSR_WUFR (0x00000040) +#define MAC_WUCSR_MPR (0x00000020) +#define MAC_WUCSR_WUEN (0x00000004) +#define MAC_WUCSR_MPEN (0x00000002) + +// PHY Control and Status Registers (accessed through MAC_MIIACC/_MIIDATA regs) +#define PHY_BCR (0x0) +#define PHY_BCR_RST (0x8000) +#define PHY_BCR_LOOPBK (0x4000) +#define PHY_BCR_SS (0x2000) +#define PHY_BCR_ANE (0x1000) +#define PHY_BCR_PWRDN (0x0800) +#define PHY_BCR_RSTAN (0x0200) +#define PHY_BCR_FDPLX (0x0100) +#define PHY_BCR_COLLTST (0x0080) + +#define PHY_BSR (0x1) +#define PHY_BSR_100_T4_ABLE (0x8000) +#define PHY_BSR_100_TX_FDPLX (0x4000) +#define PHY_BSR_100_TX_HDPLX (0x2000) +#define PHY_BSR_10_FDPLX (0x1000) +#define PHY_BSR_10_HDPLX (0x0800) +#define PHY_BSR_ANC (0x0020) +#define PHY_BSR_REM_FAULT (0x0010) +#define PHY_BSR_AN_ABLE (0x0008) +#define PHY_BSR_LINK_STATUS (0x0004) +#define PHY_BSR_JAB_DET (0x0002) +#define PHY_BSR_EXT_CAP (0x0001) + +#define PHY_ID1 (0x2) +#define PHY_ID1_MSK (0xFFFF) +#define PHY_ID1_LAN9118 (0x0007) +#define PHY_ID1_LAN9218 (PHY_ID1_LAN9118) + +#define PHY_ID2 (0x3) +#define PHY_ID2_MSK (0xFFFF) +#define PHY_ID2_MODEL_MSK (0x03F0) +#define PHY_ID2_REV_MSK (0x000F) +#define PHY_ID2_LAN9118 (0xC0D1) +#define PHY_ID2_LAN9218 (0xC0C3) + +#define PHY_ANAR (0x4) +#define PHY_ANAR_NXTPG_CAP (0x8000) +#define PHY_ANAR_REM_FAULT (0x2000) +#define PHY_ANAR_PAUSE_OP_MSK (0x0C00) +#define PHY_ANAR_PAUSE_OP_NONE (0x0000) +#define PHY_ANAR_PAUSE_OP_ASLP (0x0400) +#define PHY_ANAR_PAUSE_OP_SLP (0x0800) +#define PHY_ANAR_PAUSE_OP_BOTH (0x0C00) +#define PHY_ANAR_100_T4_ABLE (0x0200) +#define PHY_ANAR_100_TX_FDPLX (0x0100) +#define PHY_ANAR_100_TX_ABLE (0x0080) +#define PHY_ANAR_10_FDPLX (0x0040) +#define PHY_ANAR_10_ABLE (0x0020) + +#define PHY_ANLPAR (0x5) +#define PHY_ANLPAR_NXTPG_CAP (0x8000) +#define PHY_ANLPAR_ACK (0x4000) +#define PHY_ANLPAR_REM_FAULT (0x2000) +#define PHY_ANLPAR_PAUSE_CAP (0x0400) +#define PHY_ANLPAR_100_T4_ABLE (0x0200) +#define PHY_ANLPAR_100_TX_FDPLX (0x0100) +#define PHY_ANLPAR_100_TX_ABLE (0x0080) +#define PHY_ANLPAR_10_FDPLX (0x0040) +#define PHY_ANLPAR_10_ABLE (0x0020) + +#define PHY_ANEXPR (0x6) +#define PHY_ANEXPR_PARDET_FAULT (0x0010) +#define PHY_ANEXPR_LP_NXTPG_CAP (0x0008) +#define PHY_ANEXPR_NXTPG_CAP (0x0004) +#define PHY_ANEXPR_NEWPG_REC (0x0002) +#define PHY_ANEXPR_LP_AN_ABLE (0x0001) + +#define PHY_SILREV (0x10) + +#define PHY_MCSR (0x11) +#define PHY_MCSR_FASTRIP (0x4000) +#define PHY_MCSR_EDPWRDOWN (0x2000) +#define PHY_MCSR_LOWSQEN (0x0800) +#define PHY_MCSR_MDPREBP (0x0400) +#define PHY_MCSR_FASTEST (0x0100) +#define PHY_MCSR_PHYADBP (0x0008) +#define PHY_MCSR_FGLS (0x0004) +#define PHY_MCSR_ENERGYON (0x0002) + +#define PHY_SPMODES (0x12) + +#define PHY_CSIR (0x1B) +#define PHY_CSIR_SQEOFF (0x0800) +#define PHY_CSIR_FEFIEN (0x0020) +#define PHY_CSIR_XPOL (0x0010) + +#define PHY_ISR (0x1C) +#define PHY_ISR_INT7 (0x0080) +#define PHY_ISR_INT6 (0x0040) +#define PHY_ISR_INT5 (0x0020) +#define PHY_ISR_INT4 (0x0010) +#define PHY_ISR_INT3 (0x0008) +#define PHY_ISR_INT2 (0x0004) +#define PHY_ISR_INT1 (0x0002) + +#define PHY_IMR (0x1E) +#define PHY_IMR_INT7 (0x0080) +#define PHY_IMR_INT6 (0x0040) +#define PHY_IMR_INT5 (0x0020) +#define PHY_IMR_INT4 (0x0010) +#define PHY_IMR_INT3 (0x0008) +#define PHY_IMR_INT2 (0x0004) +#define PHY_IMR_INT1 (0x0002) + +#define PHY_PHYSCSR (0x1F) +#define PHY_PHYSCSR_ANDONE (0x1000) +#define PHY_PHYSCSR_4B5B_EN (0x0040) +#define PHY_PHYSCSR_SPEED_MSK (0x001C) +#define PHY_PHYSCSR_SPEED_10HD (0x0004) +#define PHY_PHYSCSR_SPEED_10FD (0x0014) +#define PHY_PHYSCSR_SPEED_100HD (0x0008) +#define PHY_PHYSCSR_SPEED_100FD (0x0018) +#endif // #ifndef _SMSC9118_H + +#endif // CONFIG_DRIVER_SMSC9118 diff --git a/drivers/status_led.c b/drivers/status_led.c new file mode 100644 index 000000000..ddb6c22e8 --- /dev/null +++ b/drivers/status_led.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* + * The purpose of this code is to signal the operational status of a + * target which usually boots over the network; while running in + * U-Boot, a status LED is blinking. As soon as a valid BOOTP reply + * message has been received, the LED is turned off. The Linux + * kernel, once it is running, will start blinking the LED again, + * with another frequency. + */ + +/* ------------------------------------------------------------------------- */ + +#ifdef CONFIG_STATUS_LED + +typedef struct { + led_id_t mask; + int state; + int period; + int cnt; +} led_dev_t; + +led_dev_t led_dev[] = { + { STATUS_LED_BIT, + STATUS_LED_STATE, + STATUS_LED_PERIOD, + 0, + }, +#if defined(STATUS_LED_BIT1) + { STATUS_LED_BIT1, + STATUS_LED_STATE1, + STATUS_LED_PERIOD1, + 0, + }, +#endif +#if defined(STATUS_LED_BIT2) + { STATUS_LED_BIT2, + STATUS_LED_STATE2, + STATUS_LED_PERIOD2, + 0, + }, +#endif +#if defined(STATUS_LED_BIT3) + { STATUS_LED_BIT3, + STATUS_LED_STATE3, + STATUS_LED_PERIOD3, + 0, + }, +#endif +}; + +#define MAX_LED_DEV (sizeof(led_dev)/sizeof(led_dev_t)) + +static int status_led_init_done = 0; + +static void status_led_init (void) +{ + led_dev_t *ld; + int i; + + for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) + __led_init (ld->mask, ld->state); + status_led_init_done = 1; +} + +void status_led_tick (ulong timestamp) +{ + led_dev_t *ld; + int i; + + if (!status_led_init_done) + status_led_init (); + + for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) { + + if (ld->state != STATUS_LED_BLINKING) + continue; + + if (++ld->cnt >= ld->period) { + __led_toggle (ld->mask); + ld->cnt -= ld->period; + } + + } +} + +void status_led_set (int led, int state) +{ + led_dev_t *ld; + + if (led < 0 || led >= MAX_LED_DEV) + return; + + if (!status_led_init_done) + status_led_init (); + + ld = &led_dev[led]; + + ld->state = state; + if (state == STATUS_LED_BLINKING) { + ld->cnt = 0; /* always start with full period */ + state = STATUS_LED_ON; /* always start with LED _ON_ */ + } + __led_set (ld->mask, state); +} + +#endif /* CONFIG_STATUS_LED */ diff --git a/drivers/sym53c8xx.c b/drivers/sym53c8xx.c new file mode 100644 index 000000000..ae10f80ec --- /dev/null +++ b/drivers/sym53c8xx.c @@ -0,0 +1,793 @@ +/* + * (C) Copyright 2001 + * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * partly derived from + * linux/drivers/scsi/sym53c8xx.c + * + */ + +/* + * SCSI support based on the chip sym53C810. + * + * 09-19-2001 Andreas Heppel, Sysgo RTS GmbH + * The local version of this driver for the BAB750 board does not + * use interrupts but polls the chip instead (see the call of + * 'handle_scsi_int()' in 'scsi_issue()'. + */ + +#include + +#ifdef CONFIG_SCSI_SYM53C8XX + +#include +#include +#include +#include +#include + +#undef SYM53C8XX_DEBUG + +#ifdef SYM53C8XX_DEBUG +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX) + +#undef SCSI_SINGLE_STEP +/* + * Single Step is only used for debug purposes + */ +#ifdef SCSI_SINGLE_STEP +static unsigned long start_script_select; +static unsigned long start_script_msgout; +static unsigned long start_script_msgin; +static unsigned long start_script_msg_ext; +static unsigned long start_script_cmd; +static unsigned long start_script_data_in; +static unsigned long start_script_data_out; +static unsigned long start_script_status; +static unsigned long start_script_complete; +static unsigned long start_script_error; +static unsigned long start_script_reselection; +static unsigned int len_script_select; +static unsigned int len_script_msgout; +static unsigned int len_script_msgin; +static unsigned int len_script_msg_ext; +static unsigned int len_script_cmd; +static unsigned int len_script_data_in; +static unsigned int len_script_data_out; +static unsigned int len_script_status; +static unsigned int len_script_complete; +static unsigned int len_script_error; +static unsigned int len_script_reselection; +#endif + + +static unsigned short scsi_int_mask; /* shadow register for SCSI related interrupts */ +static unsigned char script_int_mask; /* shadow register for SCRIPT related interrupts */ +static unsigned long script_select[8]; /* script for selection */ +static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */ +static unsigned long script_msgin[14]; /* script for message in phase */ +static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */ +static unsigned long script_cmd[18]; /* script for command phase */ +static unsigned long script_data_in[8]; /* script for data in phase */ +static unsigned long script_data_out[8]; /* script for data out phase */ +static unsigned long script_status[6]; /* script for status phase */ +static unsigned long script_complete[10]; /* script for complete */ +static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */ +static unsigned long script_error[2]; /* script for error handling */ + +static unsigned long int_stat[3]; /* interrupt status */ +static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */ + +#define bus_to_phys(a) pci_mem_to_phys(busdevfunc, (unsigned long) (a)) +#define phys_to_bus(a) pci_phys_to_mem(busdevfunc, (unsigned long) (a)) + +#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */ + +#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */ +#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */ + +/********************************************************************************* + * forward declerations + */ + +void scsi_chip_init(void); +void handle_scsi_int(void); + + +/******************************************************************************** + * reports SCSI errors to the user + */ +void scsi_print_error(ccb *pccb) +{ + int i; + printf("SCSI Error: Target %d LUN %d Command %02X\n",pccb->target, pccb->lun, pccb->cmd[0]); + printf(" CCB: "); + for(i=0;icmdlen;i++) + printf("%02X ",pccb->cmd[i]); + printf("(len=%d)\n",pccb->cmdlen); + printf(" Cntrl: "); + switch(pccb->contr_stat) { + case SIR_COMPLETE: printf("Complete (no Error)\n"); break; + case SIR_SEL_ATN_NO_MSG_OUT: printf("Selected with ATN no MSG out phase\n"); break; + case SIR_CMD_OUT_ILL_PH: printf("Command out illegal phase\n"); break; + case SIR_MSG_RECEIVED: printf("MSG received Error\n"); break; + case SIR_DATA_IN_ERR: printf("Data in Error\n"); break; + case SIR_DATA_OUT_ERR: printf("Data out Error\n"); break; + case SIR_SCRIPT_ERROR: printf("Script Error\n"); break; + case SIR_MSG_OUT_NO_CMD: printf("MSG out no Command phase\n"); break; + case SIR_MSG_OVER7: printf("MSG in over 7 bytes\n"); break; + case INT_ON_FY: printf("Interrupt on fly\n"); break; + case SCSI_SEL_TIME_OUT: printf("SCSI Selection Timeout\n"); break; + case SCSI_HNS_TIME_OUT: printf("SCSI Handshake Timeout\n"); break; + case SCSI_MA_TIME_OUT: printf("SCSI Phase Error\n"); break; + case SCSI_UNEXP_DIS: printf("SCSI unexpected disconnect\n"); break; + default: printf("unknown status %lx\n",pccb->contr_stat); break; + } + printf(" Sense: SK %x (",pccb->sense_buf[2]&0x0f); + switch(pccb->sense_buf[2]&0xf) { + case SENSE_NO_SENSE: printf("No Sense)"); break; + case SENSE_RECOVERED_ERROR: printf("Recovered Error)"); break; + case SENSE_NOT_READY: printf("Not Ready)"); break; + case SENSE_MEDIUM_ERROR: printf("Medium Error)"); break; + case SENSE_HARDWARE_ERROR: printf("Hardware Error)"); break; + case SENSE_ILLEGAL_REQUEST: printf("Illegal request)"); break; + case SENSE_UNIT_ATTENTION: printf("Unit Attention)"); break; + case SENSE_DATA_PROTECT: printf("Data Protect)"); break; + case SENSE_BLANK_CHECK: printf("Blank check)"); break; + case SENSE_VENDOR_SPECIFIC: printf("Vendor specific)"); break; + case SENSE_COPY_ABORTED: printf("Copy aborted)"); break; + case SENSE_ABORTED_COMMAND: printf("Aborted Command)"); break; + case SENSE_VOLUME_OVERFLOW: printf("Volume overflow)"); break; + case SENSE_MISCOMPARE: printf("Misscompare\n"); break; + default: printf("Illegal Sensecode\n"); break; + } + printf(" ASC %x ASCQ %x\n",pccb->sense_buf[12],pccb->sense_buf[13]); + printf(" Status: "); + switch(pccb->status) { + case S_GOOD : printf("Good\n"); break; + case S_CHECK_COND: printf("Check condition\n"); break; + case S_COND_MET: printf("Condition Met\n"); break; + case S_BUSY: printf("Busy\n"); break; + case S_INT: printf("Intermediate\n"); break; + case S_INT_COND_MET: printf("Intermediate condition met\n"); break; + case S_CONFLICT: printf("Reservation conflict\n"); break; + case S_TERMINATED: printf("Command terminated\n"); break; + case S_QUEUE_FULL: printf("Task set full\n"); break; + default: printf("unknown: %02X\n",pccb->status); break; + } + +} + + +/****************************************************************************** + * sets-up the SCSI controller + * the base memory address is retrived via the pci_read_config_dword + */ +void scsi_low_level_init(int busdevfunc) +{ + unsigned int cmd; + unsigned int addr; + unsigned char vec; + + pci_read_config_byte(busdevfunc, PCI_INTERRUPT_LINE, &vec); + pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_1, &addr); + + addr = bus_to_phys(addr & ~0xf); + + /* + * Enable bus mastering in case this has not been done, yet. + */ + pci_read_config_dword(busdevfunc, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + pci_write_config_dword(busdevfunc, PCI_COMMAND, cmd); + + scsi_mem_addr = addr; + + scsi_chip_init(); + scsi_bus_reset(); +} + + +/************************************************************************************ + * Low level Part of SCSI Driver + */ + +/* + * big-endian -> little endian conversion for the script + */ +unsigned long swap_script(unsigned long val) +{ + unsigned long tmp; + tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000); + return tmp; +} + + +void scsi_write_byte(ulong offset,unsigned char val) +{ + out8(scsi_mem_addr+offset,val); +} + + +unsigned char scsi_read_byte(ulong offset) +{ + return(in8(scsi_mem_addr+offset)); +} + + +/******************************************************************************** + * interrupt handler + */ +void handle_scsi_int(void) +{ + unsigned char stat,stat1,stat2; + unsigned short sstat; + int i; +#ifdef SCSI_SINGLE_STEP + unsigned long tt; +#endif + stat=scsi_read_byte(ISTAT); + if((stat & DIP)==DIP) { /* DMA Interrupt pending */ + stat1=scsi_read_byte(DSTAT); +#ifdef SCSI_SINGLE_STEP + if((stat1 & SSI)==SSI) + { + tt=in32r(scsi_mem_addr+DSP); + if(((tt)>=start_script_select) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msgout) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msgin) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_msg_ext) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_cmd) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_data_in) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_data_out) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_status) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_complete) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_error) && ((tt)>2); + goto end_single; + } + if(((tt)>=start_script_reselection) && ((tt)>2); + goto end_single; + } + printf("sc: %lx\n",tt); +end_single: + stat2=scsi_read_byte(DCNTL); + stat2|=STD; + scsi_write_byte(DCNTL,stat2); + } +#endif + if((stat1 & SIR)==SIR) /* script interrupt */ + { + int_stat[0]=in32(scsi_mem_addr+DSPS); + } + if((stat1 & DFE)==0) { /* fifo not epmty */ + scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ + stat2=scsi_read_byte(STEST3); + scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ + } + } + if((stat & SIP)==SIP) { /* scsi interrupt */ + sstat = (unsigned short)scsi_read_byte(SIST+1); + sstat <<=8; + sstat |= (unsigned short)scsi_read_byte(SIST); + for(i=0;i<3;i++) { + if(int_stat[i]==0) + break; /* found an empty int status */ + } + int_stat[i]=SCSI_INT_STATE | sstat; + stat1=scsi_read_byte(DSTAT); + if((stat1 & DFE)==0) { /* fifo not epmty */ + scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */ + stat2=scsi_read_byte(STEST3); + scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */ + } + } + if((stat & INTF)==INTF) { /* interrupt on Fly */ + scsi_write_byte(ISTAT,stat); /* clear it */ + for(i=0;i<3;i++) { + if(int_stat[i]==0) + break; /* found an empty int status */ + } + int_stat[i]=INT_ON_FY; + } +} + +void scsi_bus_reset(void) +{ + unsigned char t; + int i; + int end = CFG_SCSI_SPIN_UP_TIME*1000; + + t=scsi_read_byte(SCNTL1); + scsi_write_byte(SCNTL1,(t | CRST)); + udelay(50); + scsi_write_byte(SCNTL1,t); + + puts("waiting for devices to spin up"); + for(i=0;i>8)); + scsi_write_byte(DIEN,script_int_mask); +} + +void scsi_write_dsp(unsigned long start) +{ + unsigned long val; +#ifdef SCSI_SINGLE_STEP + unsigned char t; +#endif + val = start; + out32r(scsi_mem_addr + DSP,start); +#ifdef SCSI_SINGLE_STEP + t=scsi_read_byte(DCNTL); + t|=STD; + scsi_write_byte(DCNTL,t); +#endif +} + +/* only used for debug purposes */ +void scsi_print_script(void) +{ + printf("script_select @ 0x%08lX\n",(unsigned long)&script_select[0]); + printf("script_msgout @ 0x%08lX\n",(unsigned long)&script_msgout[0]); + printf("script_msgin @ 0x%08lX\n",(unsigned long)&script_msgin[0]); + printf("script_msgext @ 0x%08lX\n",(unsigned long)&script_msg_ext[0]); + printf("script_cmd @ 0x%08lX\n",(unsigned long)&script_cmd[0]); + printf("script_data_in @ 0x%08lX\n",(unsigned long)&script_data_in[0]); + printf("script_data_out @ 0x%08lX\n",(unsigned long)&script_data_out[0]); + printf("script_status @ 0x%08lX\n",(unsigned long)&script_status[0]); + printf("script_complete @ 0x%08lX\n",(unsigned long)&script_complete[0]); + printf("script_error @ 0x%08lX\n",(unsigned long)&script_error[0]); +} + + +void scsi_set_script(ccb *pccb) +{ + int busdevfunc = pccb->priv; + int i; + i=0; + script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe)); + script_select[i++]=0; /* LED ON */ + script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */ + script_select[i++]=0; + /* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */ + script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16); + script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */ + script_select[i++]=swap_script(SCR_JUMP); /* next section */ + /* script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */ + script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */ + +#ifdef SCSI_SINGLE_STEP + start_script_select=(unsigned long)&script_select[0]; + len_script_select=i*4; +#endif + + i=0; + script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT))); + script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT; + script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT); + script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0])); + script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */ + script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */ + script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */ + script_msgout[i++]=SIR_MSG_OUT_NO_CMD; + +#ifdef SCSI_SINGLE_STEP + start_script_msgout=(unsigned long)&script_msgout[0]; + len_script_msgout=i*4; +#endif + i=0; + script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND); + script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS))); /* status ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_status[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND))); /* command ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT))); /* message out ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0])); + script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */ + script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */ + script_cmd[i++]=SIR_CMD_OUT_ILL_PH; +#ifdef SCSI_SINGLE_STEP + start_script_cmd=(unsigned long)&script_cmd[0]; + len_script_cmd=i*4; +#endif + i=0; + script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */ + script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ + script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); + script_data_out[i++]=swap_script(phys_to_bus(&script_status[0])); + script_data_out[i++]=swap_script(SCR_INT); + script_data_out[i++]=SIR_DATA_OUT_ERR; + +#ifdef SCSI_SINGLE_STEP + start_script_data_out=(unsigned long)&script_data_out[0]; + len_script_data_out=i*4; +#endif + i=0; + script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move */ + script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */ + script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS))); + script_data_in[i++]=swap_script(phys_to_bus(&script_status[0])); + script_data_in[i++]=swap_script(SCR_INT); + script_data_in[i++]=SIR_DATA_IN_ERR; +#ifdef SCSI_SINGLE_STEP + start_script_data_in=(unsigned long)&script_data_in[0]; + len_script_data_in=i*4; +#endif + i=0; + script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); + script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP))); + script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0])); + script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED))); + script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0])); + script_msgin[i++]=swap_script(SCR_INT); + script_msgin[i++]=SIR_MSG_RECEIVED; +#ifdef SCSI_SINGLE_STEP + start_script_msgin=(unsigned long)&script_msgin[0]; + len_script_msgin=i*4; +#endif + i=0; + script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */ + script_msg_ext[i++]=0; + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */ + script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7])); + script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN))); + script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */ + script_msg_ext[i++]=swap_script(SCR_INT); + script_msg_ext[i++]=SIR_MSG_OVER7; +#ifdef SCSI_SINGLE_STEP + start_script_msg_ext=(unsigned long)&script_msg_ext[0]; + len_script_msg_ext=i*4; +#endif + i=0; + script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS); + script_status[i++]=swap_script(phys_to_bus(&pccb->status)); + script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); + script_status[i++]=swap_script(phys_to_bus(&script_msgin[0])); + script_status[i++]=swap_script(SCR_INT); + script_status[i++]=SIR_STATUS_ILL_PH; +#ifdef SCSI_SINGLE_STEP + start_script_status=(unsigned long)&script_status[0]; + len_script_status=i*4; +#endif + i=0; + script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f)); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN)); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_WAIT_DISC); + script_complete[i++]=0; + script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01)); + script_complete[i++]=0; /* LED OFF */ + script_complete[i++]=swap_script(SCR_INT); + script_complete[i++]=SIR_COMPLETE; +#ifdef SCSI_SINGLE_STEP + start_script_complete=(unsigned long)&script_complete[0]; + len_script_complete=i*4; +#endif + i=0; + script_error[i++]=swap_script(SCR_INT); /* interrupt if error */ + script_error[i++]=SIR_SCRIPT_ERROR; +#ifdef SCSI_SINGLE_STEP + start_script_error=(unsigned long)&script_error[0]; + len_script_error=i*4; +#endif + i=0; + script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */ + script_reselection[i++]=0; + script_reselection[i++]=swap_script(SCR_WAIT_RESEL); + script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */ +#ifdef SCSI_SINGLE_STEP + start_script_reselection=(unsigned long)&script_reselection[0]; + len_script_reselection=i*4; +#endif +} + + +void scsi_issue(ccb *pccb) +{ + int busdevfunc = pccb->priv; + int i; + unsigned short sstat; + int retrycnt; /* retry counter */ + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + /* struct pccb must be set-up correctly */ + retrycnt=0; + PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]); + pccb->trans_bytes=0; /* no bytes transfered yet */ + scsi_set_script(pccb); /* fill in SCRIPT */ + scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */ + script_int_mask=0xff; /* enable all Ints */ + scsi_int_enable(); + scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */ + /* now we have to wait for IRQs */ +retry: + /* + * This version of the driver is _not_ interrupt driven, + * but polls the chip's interrupt registers (ISTAT, DSTAT). + */ + while(int_stat[0]==0) + handle_scsi_int(); + + if(int_stat[0]==SIR_COMPLETE) { + if(pccb->msgin[0]==M_DISCONNECT) { + PRINTF("Wait for reselection\n"); + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */ + goto retry; + } + pccb->contr_stat=SIR_COMPLETE; + return; + } + if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */ + sstat=(unsigned short)int_stat[0]; + if((sstat & STO)==STO) { /* selection timeout */ + pccb->contr_stat=SCSI_SEL_TIME_OUT; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Selection Timeout\n",pccb->target); + return; + } + if((sstat & UDC)==UDC) { /* unexpected disconnect */ + pccb->contr_stat=SCSI_UNEXP_DIS; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); + return; + } + if((sstat & RSL)==RSL) { /* reselection */ + pccb->contr_stat=SCSI_UNEXP_DIS; + scsi_write_byte(GPREG,0x01); + PRINTF("ID: %X Unexpected Disconnect\n",pccb->target); + return; + } + if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */ + if(retrycnttrans_bytes=pccb->datalen - + ((unsigned long)scsi_read_byte(DBC) | + ((unsigned long)scsi_read_byte(DBC+1)<<8) | + ((unsigned long)scsi_read_byte(DBC+2)<<16)); + for(i=0;i<3;i++) + int_stat[i]=0; /* delete all int status */ + retrycnt++; + PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n", + pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes); + scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */ + goto retry; + } + if((sstat & MA)==MA) + pccb->contr_stat=SCSI_MA_TIME_OUT; + else + pccb->contr_stat=SCSI_HNS_TIME_OUT; + PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat); + return; + } /* no phase int */ +/* if((sstat & CMP)==CMP) { + pccb->contr_stat=SIR_COMPLETE; + return; + } +*/ + PRINTF("SCSI INT %lX\n",int_stat[0]); + pccb->contr_stat=int_stat[0]; + return; + } /* end scsi int */ + PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL)); + pccb->contr_stat=int_stat[0]; + return; +} + +int scsi_exec(ccb *pccb) +{ + unsigned char tmpcmd[16],tmpstat; + int i,retrycnt,t; + unsigned long transbytes,datalen; + unsigned char *tmpptr; + retrycnt=0; +retry: + scsi_issue(pccb); + if(pccb->contr_stat!=SIR_COMPLETE) + return FALSE; + if(pccb->status==S_GOOD) + return TRUE; + if(pccb->status==S_CHECK_COND) { /* check condition */ + for(i=0;i<16;i++) + tmpcmd[i]=pccb->cmd[i]; + pccb->cmd[0]=SCSI_REQ_SENSE; + pccb->cmd[1]=pccb->lun<<5; + pccb->cmd[2]=0; + pccb->cmd[3]=0; + pccb->cmd[4]=14; + pccb->cmd[5]=0; + pccb->cmdlen=6; + pccb->msgout[0]=SCSI_IDENTIFY; + transbytes=pccb->trans_bytes; + tmpptr=pccb->pdata; + pccb->pdata=&pccb->sense_buf[0]; + datalen=pccb->datalen; + pccb->datalen=14; + tmpstat=pccb->status; + scsi_issue(pccb); + for(i=0;i<16;i++) + pccb->cmd[i]=tmpcmd[i]; + pccb->trans_bytes=transbytes; + pccb->pdata=tmpptr; + pccb->datalen=datalen; + pccb->status=tmpstat; + PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f, + pccb->sense_buf[12],pccb->sense_buf[13]); + switch(pccb->sense_buf[2]&0xf) { + case SENSE_NO_SENSE: + case SENSE_RECOVERED_ERROR: + /* seems to be ok */ + return TRUE; + break; + case SENSE_NOT_READY: + if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) { + /* if device is not in process of becoming ready */ + return FALSE; + break; + } /* else fall through */ + case SENSE_UNIT_ATTENTION: + if(retrycnttarget,retrycnt); + for(t=0;ttarget,retrycnt); + return FALSE; + default: + return FALSE; + } + } + PRINTF("Status = %X\n",pccb->status); + return FALSE; +} + + +void scsi_chip_init(void) +{ + /* first we issue a soft reset */ + scsi_write_byte(ISTAT,SRST); + udelay(1000); + scsi_write_byte(ISTAT,0); + /* setup chip */ + scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */ + scsi_write_byte(SCNTL1,0x00); + scsi_write_byte(SCNTL2,0x00); +#ifndef CFG_SCSI_SYM53C8XX_CCF /* config value for none 40 mhz clocks */ + scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */ +#else + scsi_write_byte(SCNTL3,CFG_SCSI_SYM53C8XX_CCF); /* config value for none 40 mhz clocks */ +#endif + scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */ + scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */ + scsi_write_byte(SDID,0x00); /* targed SCSI ID = 0 */ + scsi_int_mask=0x0000; /* no Interrupt is enabled */ + script_int_mask=0x00; + scsi_int_enable(); + scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */ + scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */ + scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */ + scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */ + scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */ + scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */ + scsi_write_byte(STEST3,0x80); /* enable tolerANT */ + scsi_write_byte(CTEST3,0x04); /* clear FIFO */ + scsi_write_byte(CTEST4,0x00); + scsi_write_byte(CTEST5,0x00); +#ifdef SCSI_SINGLE_STEP +/* scsi_write_byte(DCNTL,IRQM | SSM); */ + scsi_write_byte(DCNTL,IRQD | SSM); + scsi_write_byte(DMODE,MAN); +#else +/* scsi_write_byte(DCNTL,IRQM); */ + scsi_write_byte(DCNTL,IRQD); + scsi_write_byte(DMODE,0x00); +#endif +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_SCSI) */ + + +#endif /* CONFIG_SCSI_SYM53C8XX */ diff --git a/drivers/ti_pci1410a.c b/drivers/ti_pci1410a.c new file mode 100644 index 000000000..d5297b572 --- /dev/null +++ b/drivers/ti_pci1410a.c @@ -0,0 +1,665 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * + * Lots of code copied from: + * + * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series. + * (C) 1999-2000 Magnus Damm + * + * "The ExCA standard specifies that socket controllers should provide + * two IO and five memory windows per socket, which can be independently + * configured and positioned in the host address space and mapped to + * arbitrary segments of card address space. " - David A Hinds. 1999 + * + * This controller does _not_ meet the ExCA standard. + * + * m8xx pcmcia controller brief info: + * + 8 windows (attrib, mem, i/o) + * + up to two slots (SLOT_A and SLOT_B) + * + inputpins, outputpins, event and mask registers. + * - no offset register. sigh. + * + * Because of the lacking offset register we must map the whole card. + * We assign each memory window PCMCIA_MEM_WIN_SIZE address space. + * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO + * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE. + * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE. + * They are maximum 64KByte each... + */ + + +#undef DEBUG /**/ + +/* + * PCMCIA support + */ +#include +#include +#include +#include +#include + +#include + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && defined(CONFIG_IDE_TI_CARDBUS) + +int pcmcia_on(int ide_base_bus); + +static int pcmcia_off(void); +static int hardware_disable(int slot); +static int hardware_enable(int slot); +static int voltage_set(int slot, int vcc, int vpp); +static void print_funcid(int func); +static void print_fixed(volatile uchar *p); +static int identify(volatile uchar *p); +static int check_ide_device(int slot, int ide_base_bus); + + +/* ------------------------------------------------------------------------- */ + + +const char *indent = "\t "; + +/* ------------------------------------------------------------------------- */ + + +int do_pinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ +#ifndef CFG_FIRST_PCMCIA_BUS +# define CFG_FIRST_PCMCIA_BUS 0 +#endif + + int rcode = 0; + + if (argc != 2) { + printf ("Usage: pinit {on | off}\n"); + return 1; + } + if (strcmp(argv[1],"on") == 0) { + rcode = pcmcia_on(CFG_FIRST_PCMCIA_BUS); + } else if (strcmp(argv[1],"off") == 0) { + rcode = pcmcia_off(); + } else { + printf ("Usage: pinit {on | off}\n"); + return 1; + } + + return rcode; +} + +/* ------------------------------------------------------------------------- */ + + +static struct pci_device_id supported[] = { + { PCI_VENDOR_ID_TI, 0xac50 }, /* Ti PCI1410A */ + { PCI_VENDOR_ID_TI, 0xac56 }, /* Ti PCI1510 */ + { } +}; + +static pci_dev_t devbusfn; +static u32 socket_base; +static u32 pcmcia_cis_ptr; + +int pcmcia_on(int ide_base_bus) +{ + u16 dev_id; + u32 socket_status; + int slot = 0; + int cis_len; + u16 io_base; + u16 io_len; + + /* + * Find the CardBus PCI device(s). + */ + if ((devbusfn = pci_find_devices(supported, 0)) < 0) { + printf("Ti CardBus: not found\n"); + return 1; + } + + pci_read_config_word(devbusfn, PCI_DEVICE_ID, &dev_id); + + if (dev_id == 0xac56) { + debug("Enable PCMCIA Ti PCI1510\n"); + } else { + debug("Enable PCMCIA Ti PCI1410A\n"); + } + + pcmcia_cis_ptr = CFG_PCMCIA_CIS_WIN; + cis_len = CFG_PCMCIA_CIS_WIN_SIZE; + + io_base = CFG_PCMCIA_IO_WIN; + io_len = CFG_PCMCIA_IO_WIN_SIZE; + + /* + * Setup the PCI device. + */ + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &socket_base); + socket_base &= ~0xf; + + socket_status = readl(socket_base+8); + if ((socket_status & 6) == 0) { + printf("Card Present: "); + + switch (socket_status & 0x3c00) { + + case 0x400: + printf("5V "); + break; + case 0x800: + printf("3.3V "); + break; + case 0xc00: + printf("3.3/5V "); + break; + default: + printf("unsupported Vcc "); + break; + } + switch (socket_status & 0x30) { + case 0x10: + printf("16bit PC-Card\n"); + break; + case 0x20: + printf("32bit CardBus Card\n"); + break; + default: + printf("8bit PC-Card\n"); + break; + } + } + + + writeb(0x41, socket_base + 0x806); /* Enable I/O window 0 and memory window 0 */ + writeb(0x0e, socket_base + 0x807); /* Reset I/O window options */ + + /* Careful: the linux yenta driver do not seem to reset the offset + * in the i/o windows, so leaving them non-zero is a problem */ + + writeb(io_base & 0xff, socket_base + 0x808); /* I/O window 0 base address */ + writeb(io_base>>8, socket_base + 0x809); + writeb((io_base + io_len - 1) & 0xff, socket_base + 0x80a); /* I/O window 0 end address */ + writeb((io_base + io_len - 1)>>8, socket_base + 0x80b); + writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address 0x000 */ + writeb(0x00, socket_base + 0x837); + + + writeb((pcmcia_cis_ptr&0x000ff000) >> 12, + socket_base + 0x810); /* Memory window 0 start address bits 19-12 */ + writeb((pcmcia_cis_ptr&0x00f00000) >> 20, + socket_base + 0x811); /* Memory window 0 start address bits 23-20 */ + writeb(((pcmcia_cis_ptr+cis_len-1) & 0x000ff000) >> 12, + socket_base + 0x812); /* Memory window 0 end address bits 19-12*/ + writeb(((pcmcia_cis_ptr+cis_len-1) & 0x00f00000) >> 20, + socket_base + 0x813); /* Memory window 0 end address bits 23-20*/ + writeb(0x00, socket_base + 0x814); /* Memory window 0 offset bits 19-12 */ + writeb(0x40, socket_base + 0x815); /* Memory window 0 offset bits 23-20 and + * options (read/write, attribute access) */ + writeb(0x00, socket_base + 0x816); /* ExCA card-detect and general control */ + writeb(0x00, socket_base + 0x81e); /* ExCA global control (interrupt modes) */ + + writeb((pcmcia_cis_ptr & 0xff000000) >> 24, + socket_base + 0x840); /* Memory window address bits 31-24 */ + + + /* turn off voltage */ + if (voltage_set(slot, 0, 0)) { + return 1; + } + + /* Enable external hardware */ + if (hardware_enable(slot)) { + return 1; + } + + if (check_ide_device(slot, ide_base_bus)) { + return 1; + } + + return 0; +} + +/* ------------------------------------------------------------------------- */ + + +static int pcmcia_off (void) +{ + int slot = 0; + + writeb(0x00, socket_base + 0x806); /* disable all I/O and memory windows */ + + writeb(0x00, socket_base + 0x808); /* I/O window 0 base address */ + writeb(0x00, socket_base + 0x809); + writeb(0x00, socket_base + 0x80a); /* I/O window 0 end address */ + writeb(0x00, socket_base + 0x80b); + writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address */ + writeb(0x00, socket_base + 0x837); + + writeb(0x00, socket_base + 0x80c); /* I/O window 1 base address */ + writeb(0x00, socket_base + 0x80d); + writeb(0x00, socket_base + 0x80e); /* I/O window 1 end address */ + writeb(0x00, socket_base + 0x80f); + writeb(0x00, socket_base + 0x838); /* I/O window 1 offset address */ + writeb(0x00, socket_base + 0x839); + + writeb(0x00, socket_base + 0x810); /* Memory window 0 start address */ + writeb(0x00, socket_base + 0x811); + writeb(0x00, socket_base + 0x812); /* Memory window 0 end address */ + writeb(0x00, socket_base + 0x813); + writeb(0x00, socket_base + 0x814); /* Memory window 0 offset */ + writeb(0x00, socket_base + 0x815); + + writeb(0xc0, socket_base + 0x840); /* Memory window 0 page address */ + + + /* turn off voltage */ + voltage_set(slot, 0, 0); + + /* disable external hardware */ + printf ("Shutdown and Poweroff Ti PCI1410A\n"); + hardware_disable(slot); + + return 0; +} + + +/* ------------------------------------------------------------------------- */ + + +#define MAX_TUPEL_SZ 512 +#define MAX_FEATURES 4 +int ide_devices_found; +static int check_ide_device(int slot, int ide_base_bus) +{ + volatile uchar *ident = NULL; + volatile uchar *feature_p[MAX_FEATURES]; + volatile uchar *p, *start; + int n_features = 0; + uchar func_id = ~0; + uchar code, len; + ushort config_base = 0; + int found = 0; + int i; + u32 socket_status; + + debug ("PCMCIA MEM: %08X\n", pcmcia_cis_ptr); + + socket_status = readl(socket_base+8); + + if ((socket_status & 6) != 0 || (socket_status & 0x20) != 0) { + printf("no card or CardBus card\n"); + return 1; + } + + start = p = (volatile uchar *) pcmcia_cis_ptr; + + while ((p - start) < MAX_TUPEL_SZ) { + + code = *p; p += 2; + + if (code == 0xFF) { /* End of chain */ + break; + } + + len = *p; p += 2; +#if defined(DEBUG) && (DEBUG > 1) + { + volatile uchar *q = p; + printf ("\nTuple code %02x length %d\n\tData:", + code, len); + + for (i = 0; i < len; ++i) { + printf (" %02x", *q); + q+= 2; + } + } +#endif /* DEBUG */ + switch (code) { + case CISTPL_VERS_1: + ident = p + 4; + break; + case CISTPL_FUNCID: + /* Fix for broken SanDisk which may have 0x80 bit set */ + func_id = *p & 0x7F; + break; + case CISTPL_FUNCE: + if (n_features < MAX_FEATURES) + feature_p[n_features++] = p; + break; + case CISTPL_CONFIG: + config_base = (*(p+6) << 8) + (*(p+4)); + debug ("\n## Config_base = %04x ###\n", config_base); + default: + break; + } + p += 2 * len; + } + + found = identify(ident); + + if (func_id != ((uchar)~0)) { + print_funcid (func_id); + + if (func_id == CISTPL_FUNCID_FIXED) + found = 1; + else + return 1; /* no disk drive */ + } + + for (i=0; i id_str) { + if (*t == ' ') { + *t = '\0'; + } else { + break; + } + } + puts(id_str); + putc('\n'); + + for (card=known_cards; *card; ++card) { + debug ("## Compare against \"%s\"\n", *card); + if (strcmp(*card, id_str) == 0) { /* found! */ + debug ("## CARD FOUND ##\n"); + return 1; + } + } + + return 0; /* don't know */ +} + +#endif /* CONFIG_IDE_TI_CARDBUS */ diff --git a/drivers/tigon3.c b/drivers/tigon3.c new file mode 100644 index 000000000..ec2cd2ac3 --- /dev/null +++ b/drivers/tigon3.c @@ -0,0 +1,6200 @@ +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/******************************************************************************/ +#include +#include +#if (CONFIG_COMMANDS & CFG_CMD_NET) && !defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_TIGON3) +#ifdef CONFIG_BMW +#include +#endif +#include +#include +#include "bcm570x_mm.h" + +#define EMBEDDED 1 +/******************************************************************************/ +/* Local functions. */ +/******************************************************************************/ + +LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice); +LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice); + +static LM_STATUS LM_TranslateRequestedMediaType( + LM_REQUESTED_MEDIA_TYPE RequestedMediaType, + PLM_MEDIA_TYPE pMediaType, PLM_LINE_SPEED pLineSpeed, + PLM_DUPLEX_MODE pDuplexMode); + +static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice); + +__inline static LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice); +__inline static LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice); + +static LM_STATUS LM_ForceAutoNegBcm540xPhy(PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType); +static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice, + LM_REQUESTED_MEDIA_TYPE RequestedMediaType); +static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice, + LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd); +#if INCLUDE_TBI_SUPPORT +STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice); +#endif +STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice); +STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid); +STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, + LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize); +STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number); +STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice); +STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, + PT3_SND_BD pSendBd); + +/******************************************************************************/ +/* External functions. */ +/******************************************************************************/ + +LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice); + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_UINT32 +LM_RegRdInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 Register) { + LM_UINT32 Value32; + +#if PCIX_TARGET_WORKAROUND + MM_ACQUIRE_UNDI_LOCK(pDevice); +#endif + MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register); + MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32); +#if PCIX_TARGET_WORKAROUND + MM_RELEASE_UNDI_LOCK(pDevice); +#endif + + return Value32; +} /* LM_RegRdInd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_RegWrInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 Register, +LM_UINT32 Value32) { + +#if PCIX_TARGET_WORKAROUND + MM_ACQUIRE_UNDI_LOCK(pDevice); +#endif + MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register); + MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, Value32); +#if PCIX_TARGET_WORKAROUND + MM_RELEASE_UNDI_LOCK(pDevice); +#endif +} /* LM_RegWrInd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_UINT32 +LM_MemRdInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 MemAddr) { + LM_UINT32 Value32; + + MM_ACQUIRE_UNDI_LOCK(pDevice); +#ifdef BIG_ENDIAN_HOST + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + Value32 = REG_RD(pDevice, PciCfg.MemWindowData); + /* Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */ +#else + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32); +#endif + MM_RELEASE_UNDI_LOCK(pDevice); + + return Value32; +} /* LM_MemRdInd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_MemWrInd( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 MemAddr, +LM_UINT32 Value32) { + MM_ACQUIRE_UNDI_LOCK(pDevice); +#ifdef BIG_ENDIAN_HOST + REG_WR(pDevice,PciCfg.MemWindowBaseAddr,MemAddr); + REG_WR(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4],Value32); +#else + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32); +#endif + MM_RELEASE_UNDI_LOCK(pDevice); +} /* LM_MemWrInd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_QueueRxPackets( +PLM_DEVICE_BLOCK pDevice) { + LM_STATUS Lmstatus; + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd; + LM_UINT32 StdBdAdded = 0; +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + LM_UINT32 JumboBdAdded = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + Lmstatus = LM_STATUS_SUCCESS; + + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + while(pPacket) { + switch(pPacket->u.Rx.RcvProdRing) { +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ + /* Initialize the buffer descriptor. */ + pRcvBd = + &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx]; + pRcvBd->Flags = RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING; + pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize; + + /* Initialize the receive buffer pointer */ +#if 0 /* Jimmy, deleted in new */ + pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; + pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; +#endif + MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); + + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - + MM_UINT_PTR(pDevice->pPacketDescBase)); + + /* Update the producer index. */ + pDevice->RxJumboProdIdx = (pDevice->RxJumboProdIdx + 1) & + T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + + JumboBdAdded++; + break; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ + /* Initialize the buffer descriptor. */ + pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx]; + pRcvBd->Flags = RCV_BD_FLAG_END; + pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE; + + /* Initialize the receive buffer pointer */ +#if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */ + pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; + pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; +#endif + MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); + + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - + MM_UINT_PTR(pDevice->pPacketDescBase)); + + /* Update the producer index. */ + pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) & + T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + + StdBdAdded++; + break; + + case T3_UNKNOWN_RCV_PROD_RING: + default: + Lmstatus = LM_STATUS_FAILURE; + break; + } /* switch */ + + /* Bail out if there is any error. */ + if(Lmstatus != LM_STATUS_SUCCESS) + { + break; + } + + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + } /* while */ + + wmb(); + /* Update the procedure index. */ + if(StdBdAdded) + { + MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, pDevice->RxStdProdIdx); + } +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if(JumboBdAdded) + { + MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, + pDevice->RxJumboProdIdx); + } +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + return Lmstatus; +} /* LM_QueueRxPackets */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_VOID +LM_NvramInit( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + /* Intialize clock period and state machine. */ + Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) | + SEEPROM_ADDR_FSM_RESET; + REG_WR(pDevice, Grc.EepromAddr, Value32); + + for(j = 0; j < 100; j++) + { + MM_Wait(10); + } + + /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */ + Value32 = REG_RD(pDevice, Grc.LocalCtrl); + REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM); + + /* Set the 5701 compatibility mode if we are using EEPROM. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + { + Value32 = REG_RD(pDevice, Nvram.Config1); + if((Value32 & FLASH_INTERFACE_ENABLE) == 0) + { + /* Use the new interface to read EEPROM. */ + Value32 &= ~FLASH_COMPAT_BYPASS; + + REG_WR(pDevice, Nvram.Config1, Value32); + } + } +} /* LM_NvRamInit */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_EepromRead( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 *pData) +{ + LM_UINT32 Value32; + LM_UINT32 Addr; + LM_UINT32 Dev; + LM_UINT32 j; + + if(Offset > SEEPROM_CHIP_SIZE) + { + return LM_STATUS_FAILURE; + } + + Dev = Offset / SEEPROM_CHIP_SIZE; + Addr = Offset % SEEPROM_CHIP_SIZE; + + Value32 = REG_RD(pDevice, Grc.EepromAddr); + Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK | + SEEPROM_ADDR_RW_MASK); + REG_WR(pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID(Dev) | + SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_READ); + + for(j = 0; j < 1000; j++) + { + Value32 = REG_RD(pDevice, Grc.EepromAddr); + if(Value32 & SEEPROM_ADDR_COMPLETE) + { + break; + } + MM_Wait(10); + } + + if(Value32 & SEEPROM_ADDR_COMPLETE) + { + Value32 = REG_RD(pDevice, Grc.EepromData); + *pData = Value32; + + return LM_STATUS_SUCCESS; + } + + return LM_STATUS_FAILURE; +} /* LM_EepromRead */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_NvramRead( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 Offset, + LM_UINT32 *pData) +{ + LM_UINT32 Value32; + LM_STATUS Status; + LM_UINT32 j; + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Status = LM_EepromRead(pDevice, Offset, pData); + } + else + { + /* Determine if we have flash or EEPROM. */ + Value32 = REG_RD(pDevice, Nvram.Config1); + if(Value32 & FLASH_INTERFACE_ENABLE) + { + if(Value32 & FLASH_SSRAM_BUFFERRED_MODE) + { + Offset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) << + BUFFERED_FLASH_PAGE_POS) + + (Offset % BUFFERED_FLASH_PAGE_SIZE); + } + } + + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + for (j = 0; j < 1000; j++) + { + if (REG_RD(pDevice, Nvram.SwArb) & SW_ARB_GNT1) + { + break; + } + MM_Wait(20); + } + if (j == 1000) + { + return LM_STATUS_FAILURE; + } + + /* Read from flash or EEPROM with the new 5703/02 interface. */ + REG_WR(pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK); + + REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT | + NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); + + /* Wait for the done bit to clear. */ + for(j = 0; j < 500; j++) + { + MM_Wait(10); + + Value32 = REG_RD(pDevice, Nvram.Cmd); + if(!(Value32 & NVRAM_CMD_DONE)) + { + break; + } + } + + /* Wait for the done bit. */ + if(!(Value32 & NVRAM_CMD_DONE)) + { + for(j = 0; j < 500; j++) + { + MM_Wait(10); + + Value32 = REG_RD(pDevice, Nvram.Cmd); + if(Value32 & NVRAM_CMD_DONE) + { + MM_Wait(10); + + *pData = REG_RD(pDevice, Nvram.ReadData); + + /* Change the endianess. */ + *pData = ((*pData & 0xff) << 24)| ((*pData & 0xff00) << 8)| + ((*pData & 0xff0000) >> 8) | ((*pData >> 24) & 0xff); + + break; + } + } + } + + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1); + if(Value32 & NVRAM_CMD_DONE) + { + Status = LM_STATUS_SUCCESS; + } + else + { + Status = LM_STATUS_FAILURE; + } + } + + return Status; +} /* LM_NvramRead */ + + +STATIC void +LM_ReadVPD(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Vpd_arr[256/4]; + LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0]; + LM_UINT32 *Vpd_dptr = &Vpd_arr[0]; + LM_UINT32 Value32; + unsigned int j; + + /* Read PN from VPD */ + for (j = 0; j < 256; j += 4, Vpd_dptr++ ) + { + if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) { + printf("BCM570x: LM_ReadVPD: VPD read failed" + " (no EEPROM onboard)\n"); + return; + } + *Vpd_dptr = cpu_to_le32(Value32); + } + for (j = 0; j < 256; ) + { + unsigned int Vpd_r_len; + unsigned int Vpd_r_end; + + if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) + { + j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8); + } + else if (Vpd[j] == 0x90) + { + Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8); + j += 3; + Vpd_r_end = Vpd_r_len + j; + while (j < Vpd_r_end) + { + if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) + { + unsigned int len = Vpd[j + 2]; + + if (len <= 24) + { + memcpy(pDevice->PartNo, &Vpd[j + 3], len); + } + break; + } + else + { + if (Vpd[j + 2] == 0) + { + break; + } + j = j + Vpd[j + 2]; + } + } + break; + } + else { + break; + } + } +} + +STATIC void +LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32, offset, ver_offset; + int i; + + if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS) + return; + if (Value32 != 0xaa559966) + return; + if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS) + return; + + offset = ((offset & 0xff) << 24)| ((offset & 0xff00) << 8)| + ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff); + if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS) + return; + if ((Value32 == 0x0300000e) && + (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) && + (Value32 == 0)) { + + if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS) + return; + ver_offset = ((ver_offset & 0xff0000) >> 8) | + ((ver_offset >> 24) & 0xff); + for (i = 0; i < 16; i += 4) { + if (LM_NvramRead(pDevice, offset + ver_offset + i, &Value32) != + LM_STATUS_SUCCESS) + { + return; + } + *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = cpu_to_le32(Value32); + } + } + else { + char c; + + if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS) + return; + + i = 0; + c = ((Value32 & 0xff0000) >> 16); + + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } + else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i++] = '.'; + c = (Value32 & 0xff000000) >> 24; + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } + else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i] = 0; + } +} + +STATIC void +LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 PciState = pDevice->PciState; + LM_UINT32 ClockCtrl; + char *SpeedStr = ""; + + if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) + { + strcpy(pDevice->BusSpeedStr, "32-bit "); + } + else + { + strcpy(pDevice->BusSpeedStr, "64-bit "); + } + if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) + { + strcat(pDevice->BusSpeedStr, "PCI "); + if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) + { + SpeedStr = "66MHz"; + } + else + { + SpeedStr = "33MHz"; + } + } + else + { + strcat(pDevice->BusSpeedStr, "PCIX "); + if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) + { + SpeedStr = "133MHz"; + } + else + { + ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f; + switch (ClockCtrl) + { + case 0: + SpeedStr = "33MHz"; + break; + + case 2: + SpeedStr = "50MHz"; + break; + + case 4: + SpeedStr = "66MHz"; + break; + + case 6: + SpeedStr = "100MHz"; + break; + + case 7: + SpeedStr = "133MHz"; + break; + } + } + } + strcat(pDevice->BusSpeedStr, SpeedStr); +} + +/******************************************************************************/ +/* Description: */ +/* This routine initializes default parameters and reads the PCI */ +/* configurations. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_GetAdapterInfo( +PLM_DEVICE_BLOCK pDevice) +{ + PLM_ADAPTER_INFO pAdapterInfo; + LM_UINT32 Value32; + LM_STATUS Status; + LM_UINT32 j; + LM_UINT32 EeSigFound; + LM_UINT32 EePhyTypeSerdes = 0; + LM_UINT32 EePhyLedMode = 0; + LM_UINT32 EePhyId = 0; + + /* Get Device Id and Vendor Id */ + Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->PciVendorId = (LM_UINT16) Value32; + pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16); + + /* If we are not getting the write adapter, exit. */ + if((Value32 != T3_PCI_ID_BCM5700) && + (Value32 != T3_PCI_ID_BCM5701) && + (Value32 != T3_PCI_ID_BCM5702) && + (Value32 != T3_PCI_ID_BCM5702x) && + (Value32 != T3_PCI_ID_BCM5702FE) && + (Value32 != T3_PCI_ID_BCM5703) && + (Value32 != T3_PCI_ID_BCM5703x) && + (Value32 != T3_PCI_ID_BCM5704)) + { + return LM_STATUS_FAILURE; + } + + Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->PciRevId = (LM_UINT8) Value32; + + /* Get IRQ. */ + Status = MM_ReadConfig32(pDevice, PCI_INT_LINE_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->Irq = (LM_UINT8) Value32; + + /* Get interrupt pin. */ + pDevice->IntPin = (LM_UINT8) (Value32 >> 8); + + /* Get chip revision id. */ + Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32); + pDevice->ChipRevId = Value32 >> 16; + + /* Get subsystem vendor. */ + Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->SubsystemVendorId = (LM_UINT16) Value32; + + /* Get PCI subsystem id. */ + pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16); + + /* Get the cache line size. */ + MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32); + pDevice->CacheLineSize = (LM_UINT8) Value32; + pDevice->SavedCacheLineReg = Value32; + + if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 && + pDevice->ChipRevId != T3_CHIP_ID_5703_A2 && + pDevice->ChipRevId != T3_CHIP_ID_5704_A0) + { + pDevice->UndiFix = FALSE; + } +#if !PCIX_TARGET_WORKAROUND + pDevice->UndiFix = FALSE; +#endif + /* Map the memory base to system address space. */ + if (!pDevice->UndiFix) + { + Status = MM_MapMemBase(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + /* Initialize the memory view pointer. */ + pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase; + } + +#if PCIX_TARGET_WORKAROUND + /* store whether we are in PCI are PCI-X mode */ + pDevice->EnablePciXFix = FALSE; + + MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); + if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) + { + /* Enable PCI-X workaround only if we are running on 5700 BX. */ + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + pDevice->EnablePciXFix = TRUE; + } + } + if (pDevice->UndiFix) + { + pDevice->EnablePciXFix = TRUE; + } +#endif + /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */ + /* management register may be clobbered which may cause the */ + /* BCM5700 to go into D3 state. While in this state, we will */ + /* not have memory mapped register access. As a workaround, we */ + /* need to restore the device to D0 state. */ + MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32); + Value32 |= T3_PM_PME_ASSERTED; + Value32 &= ~T3_PM_POWER_STATE_MASK; + Value32 |= T3_PM_POWER_STATE_D0; + MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32); + + /* read the current PCI command word */ + MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32); + + /* Make sure bus-mastering is enabled. */ + Value32 |= PCI_BUSMASTER_ENABLE; + +#if PCIX_TARGET_WORKAROUND + /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR# + are enabled */ + if (pDevice->EnablePciXFix == TRUE) { + Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE | + PCI_PARITY_ERROR_ENABLE); + } + if (pDevice->UndiFix) + { + Value32 &= ~PCI_MEM_SPACE_ENABLE; + } + +#endif + + if(pDevice->EnableMWI) + { + Value32 |= PCI_MEMORY_WRITE_INVALIDATE; + } + else { + Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE); + } + + /* Error out if mem-mapping is NOT enabled for PCI systems */ + if (!(Value32 | PCI_MEM_SPACE_ENABLE)) + { + return LM_STATUS_FAILURE; + } + + /* save the value we are going to write into the PCI command word */ + pDevice->PciCommandStatusWords = Value32; + + Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + + /* Set power state to D0. */ + LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + +#ifdef BIG_ENDIAN_PCI + pDevice->MiscHostCtrl = + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; +#else /* No CPU Swap modes for PCI IO */ + + /* Setup the mode registers. */ + pDevice->MiscHostCtrl = + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | +#ifdef BIG_ENDIAN_HOST + MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP | +#endif /* BIG_ENDIAN_HOST */ + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; +#endif /* !BIG_ENDIAN_PCI */ + + /* write to PCI misc host ctr first in order to enable indirect accesses */ + MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl); + + REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl); + +#ifdef BIG_ENDIAN_PCI + Value32 = GRC_MODE_WORD_SWAP_DATA| + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; +#else +/* No CPU Swap modes for PCI IO */ +#ifdef BIG_ENDIAN_HOST + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; +#else + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; +#endif +#endif /* !BIG_ENDIAN_PCI */ + + REG_WR(pDevice, Grc.Mode, Value32); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1); + } + MM_Wait(40); + + /* Enable indirect memory access */ + REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + + if (REG_RD(pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) + { + REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK); + REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK); + MM_Wait(40); /* required delay is 27usec */ + } + REG_WR(pDevice, PciCfg.ClockCtrl, 0); + REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); + +#if PCIX_TARGET_WORKAROUND + MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); + if ((pDevice->EnablePciXFix == FALSE) && + ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) + { + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B5) + { + __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300])); + __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); + __raw_writel(0xffffffff, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); + if (__raw_readl(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]))) + { + pDevice->EnablePciXFix = TRUE; + } + } + } +#endif +#if 1 + /* + * This code was at the beginning of else block below, but that's + * a bug if node address in shared memory. + */ + MM_Wait(50); + LM_NvramInit(pDevice); +#endif + /* Get the node address. First try to get in from the shared memory. */ + /* If the signature is not present, then get it from the NVRAM. */ + Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX); + if((Value32 >> 16) == 0x484b) + { + + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[1] = (LM_UINT8) Value32; + + Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX); + + pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24); + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[5] = (LM_UINT8) Value32; + + Status = LM_STATUS_SUCCESS; + } + else + { + Status = LM_NvramRead(pDevice, 0x7c, &Value32); + if(Status == LM_STATUS_SUCCESS) + { + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24); + + Status = LM_NvramRead(pDevice, 0x80, &Value32); + + pDevice->NodeAddress[2] = (LM_UINT8) Value32; + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24); + } + } + + /* Assign a default address. */ + if(Status != LM_STATUS_SUCCESS) + { +#ifndef EMBEDDED + printk(KERN_ERR "Cannot get MAC addr from NVRAM. Using default.\n"); +#endif + pDevice->NodeAddress[0] = 0x00; pDevice->NodeAddress[1] = 0x10; + pDevice->NodeAddress[2] = 0x18; pDevice->NodeAddress[3] = 0x68; + pDevice->NodeAddress[4] = 0x61; pDevice->NodeAddress[5] = 0x76; + } + + pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0]; + pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1]; + pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2]; + pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3]; + pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4]; + pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5]; + + /* Initialize the default values. */ + pDevice->NoTxPseudoHdrChksum = FALSE; + pDevice->NoRxPseudoHdrChksum = FALSE; + pDevice->NicSendBd = FALSE; + pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT; + pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT; + pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS; + pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS; + pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES; + pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES; + pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; + pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE; + pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; + pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE; + pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS; + pDevice->EnableMWI = FALSE; + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->DisableAutoNeg = FALSE; + pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO; + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO; + pDevice->LedMode = LED_MODE_AUTO; + pDevice->ResetPhyOnInit = TRUE; + pDevice->DelayPciGrant = TRUE; + pDevice->UseTaggedStatus = FALSE; + pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE; + + pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO; + pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO; + pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO; + + pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO; + pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE; + pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE; + pDevice->EnableTbi = FALSE; +#if INCLUDE_TBI_SUPPORT + pDevice->PollTbiLink = BAD_DEFAULT_VALUE; +#endif + + switch (T3_ASIC_REV(pDevice->ChipRevId)) + { + case T3_ASIC_REV_5704: + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64; + break; + default: + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96; + break; + } + + pDevice->LinkStatus = LM_STATUS_LINK_DOWN; + pDevice->QueueRxPackets = TRUE; + + pDevice->EnableWireSpeed = TRUE; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Make this is a known adapter. */ + pAdapterInfo = LM_GetAdapterInfoBySsid(pDevice->SubsystemVendorId, + pDevice->SubsystemId); + + pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK; + if (pDevice->BondId != GRC_MISC_BD_ID_5700 && + pDevice->BondId != GRC_MISC_BD_ID_5701 && + pDevice->BondId != GRC_MISC_BD_ID_5702FE && + pDevice->BondId != GRC_MISC_BD_ID_5703 && + pDevice->BondId != GRC_MISC_BD_ID_5703S && + pDevice->BondId != GRC_MISC_BD_ID_5704 && + pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) + { + return LM_STATUS_UNKNOWN_ADAPTER; + } + + pDevice->SplitModeEnable = SPLIT_MODE_DISABLE; + if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) && + (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) + { + pDevice->SplitModeEnable = SPLIT_MODE_ENABLE; + pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ; + } + + /* Get Eeprom info. */ + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR); + if (Value32 == T3_NIC_DATA_SIG) + { + EeSigFound = TRUE; + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR); + + /* Determine PHY type. */ + switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) + { + case T3_NIC_CFG_PHY_TYPE_COPPER: + EePhyTypeSerdes = FALSE; + break; + + case T3_NIC_CFG_PHY_TYPE_FIBER: + EePhyTypeSerdes = TRUE; + break; + + default: + EePhyTypeSerdes = FALSE; + break; + } + + /* Determine PHY led mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) + { + case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED: + EePhyLedMode = LED_MODE_THREE_LINK; + break; + + case T3_NIC_CFG_LED_MODE_LINK_SPEED: + EePhyLedMode = LED_MODE_LINK10; + break; + + default: + EePhyLedMode = LED_MODE_AUTO; + break; + } + } + else + { + switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) + { + case T3_NIC_CFG_LED_MODE_OPEN_DRAIN: + EePhyLedMode = LED_MODE_OPEN_DRAIN; + break; + + case T3_NIC_CFG_LED_MODE_OUTPUT: + EePhyLedMode = LED_MODE_OUTPUT; + break; + + default: + EePhyLedMode = LED_MODE_AUTO; + break; + } + } + if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || + pDevice->ChipRevId == T3_CHIP_ID_5703_A2) + { + /* Enable EEPROM write protection. */ + if(Value32 & T3_NIC_EEPROM_WP) + { + pDevice->EepromWp = TRUE; + } + } + + /* Get the PHY Id. */ + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR); + if (Value32) + { + EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) & + PHY_ID1_OUI_MASK) << 10; + + Value32 = Value32 & T3_NIC_PHY_ID2_MASK; + + EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | + (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); + } + else + { + EePhyId = 0; + } + } + else + { + EeSigFound = FALSE; + } + + /* Set the PHY address. */ + pDevice->PhyAddr = PHY_DEVICE_ID; + + /* Disable auto polling. */ + pDevice->MiMode = 0xc0000; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait(40); + + /* Get the PHY id. */ + LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32); + pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10; + + LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32); + pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | + (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); + + /* Set the EnableTbi flag to false if we have a copper PHY. */ + switch(pDevice->PhyId & PHY_ID_MASK) + { + case PHY_BCM5400_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM5401_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM5411_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM5701_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM5703_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM5704_PHY_ID: + pDevice->EnableTbi = FALSE; + break; + + case PHY_BCM8002_PHY_ID: + pDevice->EnableTbi = TRUE; + break; + + default: + + if (pAdapterInfo) + { + pDevice->PhyId = pAdapterInfo->PhyId; + pDevice->EnableTbi = pAdapterInfo->Serdes; + } + else if (EeSigFound) + { + pDevice->PhyId = EePhyId; + pDevice->EnableTbi = EePhyTypeSerdes; + } + break; + } + + /* Bail out if we don't know the copper PHY id. */ + if(UNKNOWN_PHY_ID(pDevice->PhyId) && !pDevice->EnableTbi) + { + return LM_STATUS_FAILURE; + } + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) + { + if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) + { + pDevice->SavedCacheLineReg &= 0xffff00ff; + pDevice->SavedCacheLineReg |= 0x4000; + } + } + /* Change driver parameters. */ + Status = MM_GetConfig(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + +#if INCLUDE_5701_AX_FIX + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + pDevice->ResetPhyOnInit = TRUE; + } +#endif + + /* Save the current phy link status. */ + if(!pDevice->EnableTbi) + { + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + /* If we don't have link reset the PHY. */ + if(!(Value32 & PHY_STATUS_LINK_PASS) || pDevice->ResetPhyOnInit) + { + + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); + + for(j = 0; j < 100; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) + { + MM_Wait(40); + break; + } + } + + +#if INCLUDE_5701_AX_FIX + /* 5701_AX_BX bug: only advertises 10mb speed. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + Value32 = BCM540X_AN_AD_1000BASET_HALF | + BCM540X_AN_AD_1000BASET_FULL | BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; + + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } +#endif + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) + { + LM_WritePhy(pDevice, 0x18, 0x0c00); + LM_WritePhy(pDevice, 0x17, 0x201f); + LM_WritePhy(pDevice, 0x15, 0x2aaa); + } + if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + LM_WritePhy(pDevice, 0x1c, 0x8d68); + LM_WritePhy(pDevice, 0x1c, 0x8d68); + } + /* Enable Ethernet@WireSpeed. */ + if(pDevice->EnableWireSpeed) + { + LM_WritePhy(pDevice, 0x18, 0x7007); + LM_ReadPhy(pDevice, 0x18, &Value32); + LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4); + } + } + } + + /* Turn off tap power management. */ + if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + { + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + + MM_Wait(40); + } + +#if INCLUDE_TBI_SUPPORT + pDevice->IgnoreTbiLinkChange = FALSE; + + if(pDevice->EnableTbi) + { + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) || + pDevice->DisableAutoNeg) + { + pDevice->PollTbiLink = FALSE; + } + } + else + { + pDevice->PollTbiLink = FALSE; + } +#endif /* INCLUDE_TBI_SUPPORT */ + + /* UseTaggedStatus is only valid for 5701 and later. */ + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->UseTaggedStatus = FALSE; + + pDevice->CoalesceMode = 0; + } + else + { + pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT | + HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT; + } + + /* Set the status block size. */ + if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX && + T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) + { + pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE; + } + + /* Check the DURING_INT coalescing ticks parameters. */ + if(pDevice->UseTaggedStatus) + { + if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxCoalescingTicksDuringInt = + DEFAULT_RX_COALESCING_TICKS_DURING_INT; + } + + if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxCoalescingTicksDuringInt = + DEFAULT_TX_COALESCING_TICKS_DURING_INT; + } + + if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxMaxCoalescedFramesDuringInt = + DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT; + } + + if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxMaxCoalescedFramesDuringInt = + DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT; + } + } + else + { + if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxCoalescingTicksDuringInt = 0; + } + + if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxCoalescingTicksDuringInt = 0; + } + + if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxMaxCoalescedFramesDuringInt = 0; + } + + if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxMaxCoalescedFramesDuringInt = 0; + } + } + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */)) + { + pDevice->RxJumboDescCnt = 0; + if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) + { + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + } + } + else + { + pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ + + COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK; + + if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) + { + pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE; + pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */; + } + pDevice->TxMtu = pDevice->RxMtu; + + } +#else + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + pDevice->RxPacketDescCnt = +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboDescCnt + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + pDevice->RxStdDescCnt; + + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) + { + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + } + + if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) + { + pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE; + } + + /* Configure the proper ways to get link change interrupt. */ + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } + else + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + } + } + else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + /* Auto-polling does not work on 5700_AX and 5700_BX. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } + } + + /* Determine the method to get link change status. */ + if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) + { + /* The link status bit in the status block does not work on 5700_AX */ + /* and 5700_BX chips. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + else + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK; + } + } + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + + /* Configure PHY led mode. */ + if(pDevice->LedMode == LED_MODE_AUTO) + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + if(pDevice->SubsystemVendorId == T3_SVID_DELL) + { + pDevice->LedMode = LED_MODE_LINK10; + } + else + { + pDevice->LedMode = LED_MODE_THREE_LINK; + + if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) + { + pDevice->LedMode = EePhyLedMode; + } + } + + /* bug? 5701 in LINK10 mode does not seem to work when */ + /* PhyIntMode is LINK_READY. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && +#if INCLUDE_TBI_SUPPORT + pDevice->EnableTbi == FALSE && +#endif + pDevice->LedMode == LED_MODE_LINK10) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + + if(pDevice->EnableTbi) + { + pDevice->LedMode = LED_MODE_THREE_LINK; + } + } + else + { + if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) + { + pDevice->LedMode = EePhyLedMode; + } + else + { + pDevice->LedMode = LED_MODE_OPEN_DRAIN; + } + } + } + + /* Enable OneDmaAtOnce. */ + if(pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) + { + pDevice->OneDmaAtOnce = FALSE; + } + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2) + { + pDevice->WolSpeed = WOL_SPEED_10MB; + } + else + { + pDevice->WolSpeed = WOL_SPEED_100MB; + } + + /* Offloadings. */ + pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE; + + /* Turn off task offloading on Ax. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5700_B0) + { + pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM); + } + pDevice->PciState = REG_RD(pDevice, PciCfg.PciState); + LM_ReadVPD(pDevice); + LM_ReadBootCodeVersion(pDevice); + LM_GetBusSpeed(pDevice); + + return LM_STATUS_SUCCESS; +} /* LM_GetAdapterInfo */ + +STATIC PLM_ADAPTER_INFO +LM_GetAdapterInfoBySsid( + LM_UINT16 Svid, + LM_UINT16 Ssid) +{ + static LM_ADAPTER_INFO AdapterArr[] = + { + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 }, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5701_PHY_ID, 0}, + + { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 }, + { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 }, + + { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 }, + + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 }, + + }; + LM_UINT32 j; + + for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++) + { + if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) + { + return &AdapterArr[j]; + } + } + + return NULL; +} + + +/******************************************************************************/ +/* Description: */ +/* This routine sets up receive/transmit buffer descriptions queues. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_InitializeAdapter( +PLM_DEVICE_BLOCK pDevice) +{ + LM_PHYSICAL_ADDRESS MemPhy; + PLM_UINT8 pMemVirt; + PLM_PACKET pPacket; + LM_STATUS Status; + LM_UINT32 Size; + LM_UINT32 j; + + /* Set power state to D0. */ + LM_SetPowerState(pDevice, LM_POWER_STATE_D0); + + /* Intialize the queues. */ + QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container, + MAX_RX_PACKET_DESC_COUNT); + QQ_InitQueue(&pDevice->RxPacketFreeQ.Container, + MAX_RX_PACKET_DESC_COUNT); + + QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT); + QQ_InitQueue(&pDevice->TxPacketActiveQ.Container,MAX_TX_PACKET_DESC_COUNT); + QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT); + + /* Allocate shared memory for: status block, the buffers for receive */ + /* rings -- standard, mini, jumbo, and return rings. */ + Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) + + T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + + /* Memory for host based Send BD. */ + if(pDevice->NicSendBd == FALSE) + { + Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + } + + /* Allocate the memory block. */ + Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + + /* Program DMA Read/Write */ + if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) + { + pDevice->DmaReadWriteCtrl = 0x763f000f; + } + else + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) + { + pDevice->DmaReadWriteCtrl = 0x761f0000; + } + else + { + pDevice->DmaReadWriteCtrl = 0x761b000f; + } + if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || + pDevice->ChipRevId == T3_CHIP_ID_5703_A2) + { + pDevice->OneDmaAtOnce = TRUE; + } + } + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) + { + pDevice->DmaReadWriteCtrl &= 0xfffffff0; + } + + if(pDevice->OneDmaAtOnce) + { + pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE; + } + REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); + + if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + /* Status block. */ + pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt; + pDevice->StatusBlkPhy = MemPhy; + pMemVirt += T3_STATUS_BLOCK_SIZE; + LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE); + + /* Statistics block. */ + pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt; + pDevice->StatsBlkPhy = MemPhy; + pMemVirt += sizeof(T3_STATS_BLOCK); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK)); + + /* Receive standard BD buffer. */ + pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RxStdBdPhy = MemPhy; + + pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Receive jumbo BD buffer. */ + pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RxJumboBdPhy = MemPhy; + + pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Receive return BD buffer. */ + pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt; + pDevice->RcvRetBdPhy = MemPhy; + + pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + + /* Set up Send BD. */ + if(pDevice->NicSendBd == FALSE) + { + pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt; + pDevice->SendBdPhy = MemPhy; + + pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT); + } + else + { + pDevice->pSendBdVirt = (PT3_SND_BD) + pDevice->pMemView->uIntMem.First32k.BufferDesc; + pDevice->SendBdPhy.High = 0; + pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR; + } + + /* Allocate memory for packet descriptors. */ + Size = (pDevice->RxPacketDescCnt + + pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE; + Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + pDevice->pPacketDescBase = (PLM_VOID) pPacket; + + /* Create transmit packet descriptors from the memory block and add them */ + /* to the TxPacketFreeQ for each send ring. */ + for(j = 0; j < pDevice->TxPacketDescCnt; j++) + { + /* Ring index. */ + pPacket->Flags = 0; + + /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */ + QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for(j.. */ + + /* Create receive packet descriptors from the memory block and add them */ + /* to the RxPacketFreeQ. Create the Standard packet descriptors. */ + for(j = 0; j < pDevice->RxStdDescCnt; j++) + { + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING; + + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE; + + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for */ + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Create the Jumbo packet descriptors. */ + for(j = 0; j < pDevice->RxJumboDescCnt; j++) + { + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING; + + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize; + + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + } /* for */ +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Initialize the rest of the packet descriptors. */ + Status = MM_InitializeUmPackets(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } /* if */ + + /* Default receive mask. */ + pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST | + LM_ACCEPT_UNICAST; + + /* Make sure we are in the first 32k memory window or NicSendBd. */ + REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); + + /* Initialize the hardware. */ + Status = LM_ResetAdapter(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + + /* We are done with initialization. */ + pDevice->InitDone = TRUE; + + return LM_STATUS_SUCCESS; +} /* LM_InitializeAdapter */ + + +/******************************************************************************/ +/* Description: */ +/* This function Enables/Disables a given block. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_CntrlBlock( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 mask,LM_UINT32 cntrl) +{ + LM_UINT32 j,i,data; + LM_UINT32 MaxWaitCnt; + + MaxWaitCnt = 2; + j = 0; + + for(i = 0 ; i < 32; i++) + { + if(!(mask & (1 << i))) + continue; + + switch (1 << i) + { + case T3_BLOCK_DMA_RD: + data = REG_RD(pDevice, DmaRead.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~DMA_READ_MODE_ENABLE; + REG_WR(pDevice, DmaRead.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, DmaRead.Mode, data | DMA_READ_MODE_ENABLE); + break; + + case T3_BLOCK_DMA_COMP: + data = REG_RD(pDevice,DmaComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~DMA_COMP_MODE_ENABLE; + REG_WR(pDevice, DmaComp.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, DmaComp.Mode, data | DMA_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_RX_BD_INITIATOR: + data = REG_RD(pDevice, RcvBdIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_BD_IN_MODE_ENABLE; + REG_WR(pDevice, RcvBdIn.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvBdIn.Mode,data | RCV_BD_IN_MODE_ENABLE); + break; + + case T3_BLOCK_RX_BD_COMP: + data = REG_RD(pDevice, RcvBdComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_BD_COMP_MODE_ENABLE; + REG_WR(pDevice, RcvBdComp.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvBdComp.Mode,data | RCV_BD_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_DMA_WR: + data = REG_RD(pDevice, DmaWrite.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~DMA_WRITE_MODE_ENABLE; + REG_WR(pDevice, DmaWrite.Mode,data); + + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, DmaWrite.Mode,data | DMA_WRITE_MODE_ENABLE); + break; + + case T3_BLOCK_MSI_HANDLER: + data = REG_RD(pDevice, Msi.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~MSI_MODE_ENABLE; + REG_WR(pDevice, Msi.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, Msi.Mode) & MSI_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, Msi.Mode, data |MSI_MODE_ENABLE); + break; + + case T3_BLOCK_RX_LIST_PLMT: + data = REG_RD(pDevice, RcvListPlmt.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_LIST_PLMT_MODE_ENABLE; + REG_WR(pDevice, RcvListPlmt.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvListPlmt.Mode,data | RCV_LIST_PLMT_MODE_ENABLE); + break; + + case T3_BLOCK_RX_LIST_SELECTOR: + data = REG_RD(pDevice, RcvListSel.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_LIST_SEL_MODE_ENABLE; + REG_WR(pDevice, RcvListSel.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvListSel.Mode,data |RCV_LIST_SEL_MODE_ENABLE); + break; + + case T3_BLOCK_RX_DATA_INITIATOR: + data = REG_RD(pDevice, RcvDataBdIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_DATA_BD_IN_MODE_ENABLE; + REG_WR(pDevice, RcvDataBdIn.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvDataBdIn.Mode, data | RCV_DATA_BD_IN_MODE_ENABLE); + break; + + case T3_BLOCK_RX_DATA_COMP: + data = REG_RD(pDevice, RcvDataComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_DATA_COMP_MODE_ENABLE; + REG_WR(pDevice, RcvDataComp.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvDataComp.Mode,data | RCV_DATA_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_HOST_COALESING: + data = REG_RD(pDevice, HostCoalesce.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~HOST_COALESCE_ENABLE; + REG_WR(pDevice, HostCoalesce.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, HostCoalesce.Mode, data | HOST_COALESCE_ENABLE); + break; + + case T3_BLOCK_MAC_RX_ENGINE: + if(cntrl == LM_DISABLE) + { + pDevice->RxMode &= ~RX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE)) + { + break; + } + MM_Wait(10); + } + } + else + { + pDevice->RxMode |= RX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + } + break; + + case T3_BLOCK_MBUF_CLUSTER_FREE: + data = REG_RD(pDevice, MbufClusterFree.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE; + REG_WR(pDevice, MbufClusterFree.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, MbufClusterFree.Mode, data | MBUF_CLUSTER_FREE_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_BD_INITIATOR: + data = REG_RD(pDevice, SndBdIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_BD_IN_MODE_ENABLE; + REG_WR(pDevice, SndBdIn.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndBdIn.Mode, data | SND_BD_IN_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_BD_COMP: + data = REG_RD(pDevice, SndBdComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_BD_COMP_MODE_ENABLE; + REG_WR(pDevice, SndBdComp.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndBdComp.Mode, data | SND_BD_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_BD_SELECTOR: + data = REG_RD(pDevice, SndBdSel.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_BD_SEL_MODE_ENABLE; + REG_WR(pDevice, SndBdSel.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndBdSel.Mode, data | SND_BD_SEL_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_DATA_INITIATOR: + data = REG_RD(pDevice, SndDataIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~T3_SND_DATA_IN_MODE_ENABLE; + REG_WR(pDevice, SndDataIn.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndDataIn.Mode,data | T3_SND_DATA_IN_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_DATA_COMP: + data = REG_RD(pDevice, SndDataComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_DATA_COMP_MODE_ENABLE; + REG_WR(pDevice, SndDataComp.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndDataComp.Mode,data | SND_DATA_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_MAC_TX_ENGINE: + if(cntrl == LM_DISABLE) + { + pDevice->TxMode &= ~TX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + { + pDevice->TxMode |= TX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + } + break; + + case T3_BLOCK_MEM_ARBITOR: + data = REG_RD(pDevice, MemArbiter.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~T3_MEM_ARBITER_MODE_ENABLE; + REG_WR(pDevice, MemArbiter.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, MemArbiter.Mode,data|T3_MEM_ARBITER_MODE_ENABLE); + break; + + case T3_BLOCK_MBUF_MANAGER: + data = REG_RD(pDevice, BufMgr.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~BUFMGR_MODE_ENABLE; + REG_WR(pDevice, BufMgr.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, BufMgr.Mode,data | BUFMGR_MODE_ENABLE); + break; + + case T3_BLOCK_MAC_GLOBAL: + if(cntrl == LM_DISABLE) + { + pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | + MAC_MODE_ENABLE_FHDE); + } + else + { + pDevice->MacMode |= (MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | + MAC_MODE_ENABLE_FHDE); + } + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + break; + + default: + return LM_STATUS_FAILURE; + } /* switch */ + + if(j >= MaxWaitCnt) + { + return LM_STATUS_FAILURE; + } + } + + return LM_STATUS_SUCCESS; +} + +/******************************************************************************/ +/* Description: */ +/* This function reinitializes the adapter. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_ResetAdapter( +PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT16 Value16; + LM_UINT32 j, k; + + /* Disable interrupt. */ + LM_DisableInterrupt(pDevice); + + /* May get a spurious interrupt */ + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED; + + /* Disable transmit and receive DMA engines. Abort all pending requests. */ + if(pDevice->InitDone) + { + LM_Abort(pDevice); + } + + pDevice->ShuttingDown = FALSE; + + LM_ResetChip(pDevice); + + /* Bug: Athlon fix for B3 silicon only. This bit does not do anything */ + /* in other chip revisions. */ + if(pDevice->DelayPciGrant) + { + Value32 = REG_RD(pDevice, PciCfg.ClockCtrl); + REG_WR(pDevice, PciCfg.ClockCtrl, Value32 | BIT_31); + } + + if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 = REG_RD(pDevice, PciCfg.PciState); + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + REG_WR(pDevice, PciCfg.PciState, Value32); + } + } + + /* Enable TaggedStatus mode. */ + if(pDevice->UseTaggedStatus) + { + pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE; + } + + /* Restore PCI configuration registers. */ + MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, + pDevice->SavedCacheLineReg); + MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, + (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + + /* Clear the statistics block. */ + for(j = 0x0300; j < 0x0b00; j++) + { + MEM_WR_OFFSET(pDevice, j, 0); + } + + /* Initialize the statistis Block */ + pDevice->pStatusBlkVirt->Status = 0; + pDevice->pStatusBlkVirt->RcvStdConIdx = 0; + pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; + pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + + for(j = 0; j < 16; j++) + { + pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0; + pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0; + } + + for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++) + { + pDevice->pRxStdBdVirt[k].HostAddr.High = 0; + pDevice->pRxStdBdVirt[k].HostAddr.Low = 0; + } + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Receive jumbo BD buffer. */ + for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) + { + pDevice->pRxJumboBdVirt[k].HostAddr.High = 0; + pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0; + } +#endif + + REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); + + /* GRC mode control register. */ +#ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */ + Value32 = + GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_INT_ON_MAC_ATTN | + GRC_MODE_HOST_STACK_UP; +#else + /* No CPU Swap modes for PCI IO */ + Value32 = +#ifdef BIG_ENDIAN_HOST + GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA | +#else + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA | +#endif + GRC_MODE_INT_ON_MAC_ATTN | + GRC_MODE_HOST_STACK_UP; +#endif /* !BIG_ENDIAN_PCI */ + + /* Configure send BD mode. */ + if(pDevice->NicSendBd == FALSE) + { + Value32 |= GRC_MODE_HOST_SEND_BDS; + } + else + { + Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS; + } + + /* Configure pseudo checksum mode. */ + if(pDevice->NoTxPseudoHdrChksum) + { + Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM; + } + + if(pDevice->NoRxPseudoHdrChksum) + { + Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM; + } + + REG_WR(pDevice, Grc.Mode, Value32); + + /* Setup the timer prescalar register. */ + REG_WR(pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */ + + /* Set up the MBUF pool base address and size. */ + REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); + REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize); + + /* Set up the DMA descriptor pool base address and size. */ + REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR); + REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE); + + /* Configure MBUF and Threshold watermarks */ + /* Configure the DMA read MBUF low water mark. */ + if(pDevice->DmaMbufLowMark) + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + pDevice->DmaMbufLowMark); + } + else + { + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK); + } + else + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO); + } + } + + /* Configure the MAC Rx MBUF low water mark. */ + if(pDevice->RxMacMbufLowMark) + { + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + pDevice->RxMacMbufLowMark); + } + else + { + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) + { + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK); + } + else + { + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO); + } + } + + /* Configure the MBUF high water mark. */ + if(pDevice->MbufHighMark) + { + REG_WR(pDevice, BufMgr.MbufHighWaterMark, pDevice->MbufHighMark); + } + else + { + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) + { + REG_WR(pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK); + } + else + { + REG_WR(pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK_JUMBO); + } + } + + REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK); + REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK); + + /* Enable buffer manager. */ + REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); + + for(j = 0 ;j < 2000; j++) + { + if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE) + break; + MM_Wait(10); + } + + if(j >= 2000) + { + return LM_STATUS_FAILURE; + } + + /* Enable the FTQs. */ + REG_WR(pDevice, Ftq.Reset, 0xffffffff); + REG_WR(pDevice, Ftq.Reset, 0); + + /* Wait until FTQ is ready */ + for(j = 0; j < 2000; j++) + { + if(REG_RD(pDevice, Ftq.Reset) == 0) + break; + MM_Wait(10); + } + + if(j >= 2000) + { + return LM_STATUS_FAILURE; + } + + /* Initialize the Standard Receive RCB. */ + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High, + pDevice->RxStdBdPhy.High); + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low, + pDevice->RxStdBdPhy.Low); + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags, + MAX_STD_RCV_BUFFER_SIZE << 16); + + /* Initialize the Jumbo Receive RCB. */ + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High, + pDevice->RxJumboBdPhy.High); + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low, + pDevice->RxJumboBdPhy.Low); + + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0); + +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Initialize the Mini Receive RCB. */ + REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags, + T3_RCB_FLAG_RING_DISABLED); + + { + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR); + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR); + } + + /* Receive BD Ring replenish threshold. */ + REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8); +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8); +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + /* Disable all the unused rings. */ + for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) { + MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); + } /* for */ + + /* Initialize the indices. */ + pDevice->SendProdIdx = 0; + pDevice->SendConIdx = 0; + + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0); + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0); + + /* Set up host or NIC based send RCB. */ + if(pDevice->NicSendBd == FALSE) + { + MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, + pDevice->SendBdPhy.High); + MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, + pDevice->SendBdPhy.Low); + + /* Set up the NIC ring address in the RCB. */ + MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR); + + /* Setup the RCB. */ + MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags, + T3_SEND_RCB_ENTRY_COUNT << 16); + + for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) + { + pDevice->pSendBdVirt[k].HostAddr.High = 0; + pDevice->pSendBdVirt[k].HostAddr.Low = 0; + } + } + else + { + MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0); + MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0); + MEM_WR(pDevice, SendRcb[0].NicRingAddr, + pDevice->SendBdPhy.Low); + + for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) + { + __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.High)); + __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.Low)); + __raw_writel(0, &(pDevice->pSendBdVirt[k].u1.Len_Flags)); + pDevice->ShadowSendBd[k].HostAddr.High = 0; + pDevice->ShadowSendBd[k].u1.Len_Flags = 0; + } + } + atomic_set(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1); + + /* Configure the receive return rings. */ + for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) + { + MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); + } + + pDevice->RcvRetConIdx = 0; + + MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High, + pDevice->RcvRetBdPhy.High); + MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low, + pDevice->RcvRetBdPhy.Low); + + /* Set up the NIC ring address in the RCB. */ + /* Not very clear from the spec. I am guessing that for Receive */ + /* Return Ring, NicRingAddr is not used. */ + MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0); + + /* Setup the RCB. */ + MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags, + T3_RCV_RETURN_RCB_ENTRY_COUNT << 16); + + /* Reinitialize RX ring producer index */ + MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0); + MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0); + MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0); + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + pDevice->RxJumboProdIdx = 0; + pDevice->RxJumboQueuedCnt = 0; +#endif + + /* Reinitialize our copy of the indices. */ + pDevice->RxStdProdIdx = 0; + pDevice->RxStdQueuedCnt = 0; + +#if T3_JUMBO_RCV_ENTRY_COUNT + pDevice->RxJumboProdIdx = 0; +#endif /* T3_JUMBO_RCV_ENTRY_COUNT */ + + /* Configure the MAC address. */ + LM_SetMacAddress(pDevice, pDevice->NodeAddress); + + /* Initialize the transmit random backoff seed. */ + Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] + + pDevice->NodeAddress[2] + pDevice->NodeAddress[3] + + pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) & + MAC_TX_BACKOFF_SEED_MASK; + REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32); + + /* Receive MTU. Frames larger than the MTU is marked as oversized. */ + REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8); /* CRC + VLAN. */ + + /* Configure Time slot/IPG per 802.3 */ + REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); + + /* + * Configure Receive Rules so that packets don't match + * Programmble rule will be queued to Return Ring 1 + */ + REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS); + + /* + * Configure to have 16 Classes of Services (COS) and one + * queue per class. Bad frames are queued to RRR#1. + * And frames don't match rules are also queued to COS#1. + */ + REG_WR(pDevice, RcvListPlmt.Config, 0x181); + + /* Enable Receive Placement Statistics */ + REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff); + REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE); + + /* Enable Send Data Initator Statistics */ + REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff); + REG_WR(pDevice, SndDataIn.StatsCtrl, + T3_SND_DATA_IN_STATS_CTRL_ENABLE | \ + T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE); + + /* Disable the host coalescing state machine before configuring it's */ + /* parameters. */ + REG_WR(pDevice, HostCoalesce.Mode, 0); + for(j = 0; j < 2000; j++) + { + Value32 = REG_RD(pDevice, HostCoalesce.Mode); + if(!(Value32 & HOST_COALESCE_ENABLE)) + { + break; + } + MM_Wait(10); + } + + /* Host coalescing configurations. */ + REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks); + REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks); + REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames, + pDevice->RxMaxCoalescedFrames); + REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames, + pDevice->TxMaxCoalescedFrames); + REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt, + pDevice->RxCoalescingTicksDuringInt); + REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt, + pDevice->TxCoalescingTicksDuringInt); + REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt, + pDevice->RxMaxCoalescedFramesDuringInt); + REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt, + pDevice->TxMaxCoalescedFramesDuringInt); + + /* Initialize the address of the status block. The NIC will DMA */ + /* the status block to this memory which resides on the host. */ + REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High, + pDevice->StatusBlkPhy.High); + REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low, + pDevice->StatusBlkPhy.Low); + + /* Initialize the address of the statistics block. The NIC will DMA */ + /* the statistics to this block of memory. */ + REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High, + pDevice->StatsBlkPhy.High); + REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low, + pDevice->StatsBlkPhy.Low); + + REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks, + pDevice->StatsCoalescingTicks); + + REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300); + REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00); + + /* Enable Host Coalesing state machine */ + REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE | + pDevice->CoalesceMode); + + /* Enable the Receive BD Completion state machine. */ + REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE | + RCV_BD_COMP_MODE_ATTN_ENABLE); + + /* Enable the Receive List Placement state machine. */ + REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE); + + /* Enable the Receive List Selector state machine. */ + REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE | + RCV_LIST_SEL_MODE_ATTN_ENABLE); + + /* Enable transmit DMA, clear statistics. */ + pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS | + MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS); + + /* GRC miscellaneous local control register. */ + pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN | + GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM; + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1; + } + + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); + MM_Wait(40); + + /* Reset RX counters. */ + for(j = 0; j < sizeof(LM_RX_COUNTERS); j++) + { + ((PLM_UINT8) &pDevice->RxCounters)[j] = 0; + } + + /* Reset TX counters. */ + for(j = 0; j < sizeof(LM_TX_COUNTERS); j++) + { + ((PLM_UINT8) &pDevice->TxCounters)[j] = 0; + } + + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); + + /* Enable the DMA Completion state machine. */ + REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE); + + /* Enable the DMA Write state machine. */ + Value32 = DMA_WRITE_MODE_ENABLE | + DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE; + REG_WR(pDevice, DmaWrite.Mode, Value32); + + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + Value16 = REG_RD(pDevice, PciCfg.PciXCommand); + Value16 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK); + Value16 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) & + PCIX_CMD_MAX_BURST_MASK); + if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) + { + Value16 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL) + & PCIX_CMD_MAX_SPLIT_MASK; + } + REG_WR(pDevice, PciCfg.PciXCommand, Value16); + } + } + + /* Enable the Read DMA state machine. */ + Value32 = DMA_READ_MODE_ENABLE | + DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_READ_MODE_LONG_READ_ATTN_ENABLE; + + if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) + { + Value32 |= DMA_READ_MODE_SPLIT_ENABLE; + } + REG_WR(pDevice, DmaRead.Mode, Value32); + + /* Enable the Receive Data Completion state machine. */ + REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE | + RCV_DATA_COMP_MODE_ATTN_ENABLE); + + /* Enable the Mbuf Cluster Free state machine. */ + REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE); + + /* Enable the Send Data Completion state machine. */ + REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE); + + /* Enable the Send BD Completion state machine. */ + REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE | + SND_BD_COMP_MODE_ATTN_ENABLE); + + /* Enable the Receive BD Initiator state machine. */ + REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE | + RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE); + + /* Enable the Receive Data and Receive BD Initiator state machine. */ + REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE | + RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE); + + /* Enable the Send Data Initiator state machine. */ + REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE); + + /* Enable the Send BD Initiator state machine. */ + REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE | + SND_BD_IN_MODE_ATTN_ENABLE); + + /* Enable the Send BD Selector state machine. */ + REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE | + SND_BD_SEL_MODE_ATTN_ENABLE); + +#if INCLUDE_5701_AX_FIX + /* Load the firmware for the 5701_A0 workaround. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0) + { + LM_LoadRlsFirmware(pDevice); + } +#endif + + /* Enable the transmitter. */ + pDevice->TxMode = TX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + + /* Enable the receiver. */ + pDevice->RxMode = RX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + + if (pDevice->RestoreOnWakeUp) + { + pDevice->RestoreOnWakeUp = FALSE; + pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg; + pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType; + } + + /* Disable auto polling. */ + pDevice->MiMode = 0xc0000; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = LED_CTRL_PHY_MODE_1; + } + else + { + if(pDevice->LedMode == LED_MODE_OUTPUT) + { + Value32 = LED_CTRL_PHY_MODE_2; + } + else + { + Value32 = LED_CTRL_PHY_MODE_1; + } + } + REG_WR(pDevice, MacCtrl.LedCtrl, Value32); + + /* Activate Link to enable MAC state machine */ + REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN); + + if (pDevice->EnableTbi) + { + REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET); + MM_Wait(10); + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) + { + REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000); + } + } + /* Setup the phy chip. */ + LM_SetupPhy(pDevice); + + if (!pDevice->EnableTbi) { + /* Clear CRC stats */ + LM_ReadPhy(pDevice, 0x1e, &Value32); + LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000); + LM_ReadPhy(pDevice, 0x14, &Value32); + } + + /* Set up the receive mask. */ + LM_SetReceiveMask(pDevice, pDevice->ReceiveMask); + + /* Queue Rx packet buffers. */ + if(pDevice->QueueRxPackets) + { + LM_QueueRxPackets(pDevice); + } + + /* Enable interrupt to the host. */ + if(pDevice->InitDone) + { + LM_EnableInterrupt(pDevice); + } + + return LM_STATUS_SUCCESS; +} /* LM_ResetAdapter */ + + +/******************************************************************************/ +/* Description: */ +/* This routine disables the adapter from generating interrupts. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_DisableInterrupt( + PLM_DEVICE_BLOCK pDevice) +{ + REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl | + MISC_HOST_CTRL_MASK_PCI_INT); + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); + + return LM_STATUS_SUCCESS; +} + + +/******************************************************************************/ +/* Description: */ +/* This routine enables the adapter to generate interrupts. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_EnableInterrupt( + PLM_DEVICE_BLOCK pDevice) +{ + REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl & + ~MISC_HOST_CTRL_MASK_PCI_INT); + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); + + if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) + { + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_SET_INT); + } + + return LM_STATUS_SUCCESS; +} + + +/******************************************************************************/ +/* Description: */ +/* This routine puts a packet on the wire if there is a transmit DMA */ +/* descriptor available; otherwise the packet is queued for later */ +/* transmission. If the second argue is NULL, this routine will put */ +/* the queued packet on the wire if possible. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +#if 0 +LM_STATUS +LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + LM_UINT32 FragCount; + PT3_SND_BD pSendBd; + PT3_SND_BD pShadowSendBd; + LM_UINT32 Value32, Len; + LM_UINT32 Idx; + + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) { + return LM_5700SendPacket(pDevice, pPacket); + } + + /* Update the SendBdLeft count. */ + atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + /* Initalize the send buffer descriptors. */ + Idx = pDevice->SendProdIdx; + + pSendBd = &pDevice->pSendBdVirt[Idx]; + + /* Next producer index. */ + if (pDevice->NicSendBd == TRUE) + { + T3_64BIT_HOST_ADDR paddr; + + pShadowSendBd = &pDevice->ShadowSendBd[Idx]; + for(FragCount = 0; ; ) + { + MM_MapTxDma(pDevice, pPacket, &paddr, &Len, FragCount); + /* Initialize the pointer to the send buffer fragment. */ + if (paddr.High != pShadowSendBd->HostAddr.High) + { + __raw_writel(paddr.High, &(pSendBd->HostAddr.High)); + pShadowSendBd->HostAddr.High = paddr.High; + } + __raw_writel(paddr.Low, &(pSendBd->HostAddr.Low)); + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + Value32 |= SND_BD_FLAG_END; + if (Value32 != pShadowSendBd->u1.Len_Flags) + { + __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); + } + break; + } + else + { + if (Value32 != pShadowSendBd->u1.Len_Flags) + { + __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); + } + } + + pSendBd++; + pShadowSendBd++; + if (Idx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + pShadowSendBd = &pDevice->ShadowSendBd[0]; + } + } /* for */ + + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + + wmb(); + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + + } + else + { + for(FragCount = 0; ; ) + { + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); + + pSendBd->u2.VlanTag = pPacket->VlanTag; + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; + break; + } + else + { + pSendBd->u1.Len_Flags = Value32; + } + pSendBd++; + if (Idx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } /* for */ + + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + + wmb(); + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + + } + + /* Update the producer index. */ + pDevice->SendProdIdx = Idx; + + return LM_STATUS_SUCCESS; +} +#endif + +LM_STATUS +LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) +{ + LM_UINT32 FragCount; + PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd; + T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT]; + LM_UINT32 StartIdx, Idx; + + while (1) + { + /* Initalize the send buffer descriptors. */ + StartIdx = Idx = pDevice->SendProdIdx; + + if (pDevice->NicSendBd) + { + pTmpSendBd = pSendBd = &NicSendBdArr[0]; + } + else + { + pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx]; + } + + /* Next producer index. */ + for(FragCount = 0; ; ) + { + LM_UINT32 Value32, Len; + + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); + + pSendBd->u2.VlanTag = pPacket->VlanTag; + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; + break; + } + else + { + pSendBd->u1.Len_Flags = Value32; + } + pSendBd++; + if ((Idx == 0) && !pDevice->NicSendBd) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } /* for */ + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) == + LM_STATUS_SUCCESS) + { + if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS) + { + QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); + return LM_STATUS_FAILURE; + } + continue; + } + } + break; + } + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + + if (pDevice->NicSendBd) + { + pSendBd = &pDevice->pSendBdVirt[StartIdx]; + pShadowSendBd = &pDevice->ShadowSendBd[StartIdx]; + + while (StartIdx != Idx) + { + LM_UINT32 Value32; + + if ((Value32 = pTmpSendBd->HostAddr.High) != + pShadowSendBd->HostAddr.High) + { + __raw_writel(Value32, &(pSendBd->HostAddr.High)); + pShadowSendBd->HostAddr.High = Value32; + } + + __raw_writel(pTmpSendBd->HostAddr.Low, &(pSendBd->HostAddr.Low)); + + if ((Value32 = pTmpSendBd->u1.Len_Flags) != + pShadowSendBd->u1.Len_Flags) + { + __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) + { + __raw_writel(pTmpSendBd->u2.VlanTag, &(pSendBd->u2.VlanTag)); + } + + StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (StartIdx == 0) + pSendBd = &pDevice->pSendBdVirt[0]; + else + pSendBd++; + pTmpSendBd++; + } + wmb(); + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + } + } + else + { + wmb(); + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + } + } + + /* Update the SendBdLeft count. */ + atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + /* Update the producer index. */ + pDevice->SendProdIdx = Idx; + + return LM_STATUS_SUCCESS; +} + +STATIC LM_STATUS +LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, + PT3_SND_BD pSendBd) +{ + int FragCount; + LM_UINT32 Idx, Base, Len; + + Idx = pDevice->SendProdIdx; + for(FragCount = 0; ; ) + { + Len = pSendBd->u1.Len_Flags >> 16; + if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) && + (pSendBd->HostAddr.High == 0) && + ((Base + 8 + Len) < Base)) + { + return LM_STATUS_SUCCESS; + } + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + break; + } + pSendBd++; + if (!pDevice->NicSendBd) + { + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (Idx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } + } + return LM_STATUS_FAILURE; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static unsigned long +ComputeCrc32( +unsigned char *pBuffer, +unsigned long BufferSize) { + unsigned long Reg; + unsigned long Tmp; + unsigned long j, k; + + Reg = 0xffffffff; + + for(j = 0; j < BufferSize; j++) + { + Reg ^= pBuffer[j]; + + for(k = 0; k < 8; k++) + { + Tmp = Reg & 0x01; + + Reg >>= 1; + + if(Tmp) + { + Reg ^= 0xedb88320; + } + } + } + + return ~Reg; +} /* ComputeCrc32 */ + + +/******************************************************************************/ +/* Description: */ +/* This routine sets the receive control register according to ReceiveMask */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_SetReceiveMask( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 Mask) { + LM_UINT32 ReceiveMask; + LM_UINT32 RxMode; + LM_UINT32 j, k; + + ReceiveMask = Mask; + + RxMode = pDevice->RxMode; + + if(Mask & LM_ACCEPT_UNICAST) + { + Mask &= ~LM_ACCEPT_UNICAST; + } + + if(Mask & LM_ACCEPT_MULTICAST) + { + Mask &= ~LM_ACCEPT_MULTICAST; + } + + if(Mask & LM_ACCEPT_ALL_MULTICAST) + { + Mask &= ~LM_ACCEPT_ALL_MULTICAST; + } + + if(Mask & LM_ACCEPT_BROADCAST) + { + Mask &= ~LM_ACCEPT_BROADCAST; + } + + RxMode &= ~RX_MODE_PROMISCUOUS_MODE; + if(Mask & LM_PROMISCUOUS_MODE) + { + RxMode |= RX_MODE_PROMISCUOUS_MODE; + Mask &= ~LM_PROMISCUOUS_MODE; + } + + RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED); + if(Mask & LM_ACCEPT_ERROR_PACKET) + { + RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED; + Mask &= ~LM_ACCEPT_ERROR_PACKET; + } + + /* Make sure all the bits are valid before committing changes. */ + if(Mask) + { + return LM_STATUS_FAILURE; + } + + /* Commit the new filter. */ + pDevice->RxMode = RxMode; + REG_WR(pDevice, MacCtrl.RxMode, RxMode); + + pDevice->ReceiveMask = ReceiveMask; + + /* Set up the MC hash table. */ + if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST) + { + for(k = 0; k < 4; k++) + { + REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff); + } + } + else if(ReceiveMask & LM_ACCEPT_MULTICAST) + { + LM_UINT32 HashReg[4]; + + HashReg[0] = 0; HashReg[1] = 0; HashReg[2] = 0; HashReg[3] = 0; + for(j = 0; j < pDevice->McEntryCount; j++) + { + LM_UINT32 RegIndex; + LM_UINT32 Bitpos; + LM_UINT32 Crc32; + + Crc32 = ComputeCrc32(pDevice->McTable[j], ETHERNET_ADDRESS_SIZE); + + /* The most significant 7 bits of the CRC32 (no inversion), */ + /* are used to index into one of the possible 128 bit positions. */ + Bitpos = ~Crc32 & 0x7f; + + /* Hash register index. */ + RegIndex = (Bitpos & 0x60) >> 5; + + /* Bit to turn on within a hash register. */ + Bitpos &= 0x1f; + + /* Enable the multicast bit. */ + HashReg[RegIndex] |= (1 << Bitpos); + } + + /* REV_AX has problem with multicast filtering where it uses both */ + /* DA and SA to perform hashing. */ + for(k = 0; k < 4; k++) + { + REG_WR(pDevice, MacCtrl.HashReg[k], HashReg[k]); + } + } + else + { + /* Reject all multicast frames. */ + for(j = 0; j < 4; j++) + { + REG_WR(pDevice, MacCtrl.HashReg[j], 0); + } + } + + /* By default, Tigon3 will accept broadcast frames. We need to setup */ + if(ReceiveMask & LM_ACCEPT_BROADCAST) + { + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + } + else + { + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE2_RULE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE2_VALUE); + } + + /* disable the rest of the rules. */ + for(j = RCV_LAST_RULE_IDX; j < 16; j++) + { + REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0); + REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0); + } + + return LM_STATUS_SUCCESS; +} /* LM_SetReceiveMask */ + + +/******************************************************************************/ +/* Description: */ +/* Disable the interrupt and put the transmitter and receiver engines in */ +/* an idle state. Also aborts all pending send requests and receive */ +/* buffers. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_Abort( +PLM_DEVICE_BLOCK pDevice) +{ + PLM_PACKET pPacket; + LM_UINT Idx; + + LM_DisableInterrupt(pDevice); + + /* Disable all the state machines. */ + LM_CntrlBlock(pDevice,T3_BLOCK_MAC_RX_ENGINE,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_INITIATOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_PLMT,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_SELECTOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_INITIATOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_COMP,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_COMP,LM_DISABLE); + + LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_SELECTOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_INITIATOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_INITIATOR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_DMA_RD,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_COMP,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_DMA_COMP,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_COMP,LM_DISABLE); + + /* Clear TDE bit */ + pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + + LM_CntrlBlock(pDevice,T3_BLOCK_MAC_TX_ENGINE,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_HOST_COALESING,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_DMA_WR,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_CLUSTER_FREE,LM_DISABLE); + + /* Reset all FTQs */ + REG_WR(pDevice, Ftq.Reset, 0xffffffff); + REG_WR(pDevice, Ftq.Reset, 0x0); + + LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_MANAGER,LM_DISABLE); + LM_CntrlBlock(pDevice,T3_BLOCK_MEM_ARBITOR,LM_DISABLE); + + MM_ACQUIRE_INT_LOCK(pDevice); + + /* Abort packets that have already queued to go out. */ + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->TxPacketActiveQ.Container); + while(pPacket) + { + + pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED; + pDevice->TxCounters.TxPacketAbortedCnt++; + + atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); + + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->TxPacketActiveQ.Container); + } + + /* Cleanup the receive return rings. */ + LM_ServiceRxInterrupt(pDevice); + + /* Don't want to indicate rx packets in Ndis miniport shutdown context. */ + /* Doing so may cause system crash. */ + if(!pDevice->ShuttingDown) + { + /* Indicate packets to the protocol. */ + MM_IndicateTxPackets(pDevice); + + /* Indicate received packets to the protocols. */ + MM_IndicateRxPackets(pDevice); + } + else + { + /* Move the receive packet descriptors in the ReceivedQ to the */ + /* free queue. */ + for(; ;) + { + pPacket = (PLM_PACKET) QQ_PopHead( + &pDevice->RxPacketReceivedQ.Container); + if(pPacket == NULL) + { + break; + } + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } + } + + /* Clean up the Std Receive Producer ring. */ + Idx = pDevice->pStatusBlkVirt->RcvStdConIdx; + + while(Idx != pDevice->RxStdProdIdx) { + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pDevice->pRxStdBdVirt[Idx].Opaque)); + + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + } /* while */ + + /* Reinitialize our copy of the indices. */ + pDevice->RxStdProdIdx = 0; + +#if T3_JUMBO_RCV_RCB_ENTRY_COUNT + /* Clean up the Jumbo Receive Producer ring. */ + Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx; + + while(Idx != pDevice->RxJumboProdIdx) { + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pDevice->pRxJumboBdVirt[Idx].Opaque)); + + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + + Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + } /* while */ + + /* Reinitialize our copy of the indices. */ + pDevice->RxJumboProdIdx = 0; +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ + + MM_RELEASE_INT_LOCK(pDevice); + + /* Initialize the statistis Block */ + pDevice->pStatusBlkVirt->Status = 0; + pDevice->pStatusBlkVirt->RcvStdConIdx = 0; + pDevice->pStatusBlkVirt->RcvJumboConIdx = 0; + pDevice->pStatusBlkVirt->RcvMiniConIdx = 0; + + return LM_STATUS_SUCCESS; +} /* LM_Abort */ + + +/******************************************************************************/ +/* Description: */ +/* Disable the interrupt and put the transmitter and receiver engines in */ +/* an idle state. Aborts all pending send requests and receive buffers. */ +/* Also free all the receive buffers. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_Halt( +PLM_DEVICE_BLOCK pDevice) { + PLM_PACKET pPacket; + LM_UINT32 EntryCnt; + + LM_Abort(pDevice); + + /* Get the number of entries in the queue. */ + EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container); + + /* Make sure all the packets have been accounted for. */ + for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) + { + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + if (pPacket == 0) + break; + + MM_FreeRxBuffer(pDevice, pPacket); + + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } + + LM_ResetChip(pDevice); + + /* Restore PCI configuration registers. */ + MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, + pDevice->SavedCacheLineReg); + LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, + (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + + /* Reprogram the MAC address. */ + LM_SetMacAddress(pDevice, pDevice->NodeAddress); + + return LM_STATUS_SUCCESS; +} /* LM_Halt */ + + +STATIC LM_STATUS +LM_ResetChip(PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + /* Wait for access to the nvram interface before resetting. This is */ + /* a workaround to prevent EEPROM corruption. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + { + /* Request access to the flash interface. */ + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + + for(j = 0; j < 100000; j++) + { + Value32 = REG_RD(pDevice, Nvram.SwArb); + if(Value32 & SW_ARB_GNT1) + { + break; + } + MM_Wait(10); + } + } + + /* Global reset. */ + REG_WR(pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET); + MM_Wait(40); MM_Wait(40); MM_Wait(40); + + /* make sure we re-enable indirect accesses */ + MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, + pDevice->MiscHostCtrl); + + /* Set MAX PCI retry to zero. */ + Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE; + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + } + } + MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32); + + /* Restore PCI command register. */ + MM_WriteConfig32(pDevice, PCI_COMMAND_REG, + pDevice->PciCommandStatusWords); + + /* Disable PCI-X relaxed ordering bit. */ + MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32); + Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING; + MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32); + + /* Enable memory arbiter. */ + REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); + +#ifdef BIG_ENDIAN_PCI /* This from jfd */ + Value32 = GRC_MODE_WORD_SWAP_DATA| + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; +#else +#ifdef BIG_ENDIAN_HOST + /* Reconfigure the mode register. */ + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA; +#else + /* Reconfigure the mode register. */ + Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; +#endif +#endif + REG_WR(pDevice, Grc.Mode, Value32); + + /* Prevent PXE from restarting. */ + MEM_WR_OFFSET(pDevice, 0x0b50, T3_MAGIC_NUM); + + if(pDevice->EnableTbi) { + pDevice->MacMode = MAC_MODE_PORT_MODE_TBI; + REG_WR(pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI); + } + else { + REG_WR(pDevice, MacCtrl.Mode, 0); + } + + /* Wait for the firmware to finish initialization. */ + for(j = 0; j < 100000; j++) + { + MM_Wait(10); + + Value32 = MEM_RD_OFFSET(pDevice, 0x0b50); + if(Value32 == ~T3_MAGIC_NUM) + { + break; + } + } + return LM_STATUS_SUCCESS; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static void +LM_ServiceTxInterrupt( +PLM_DEVICE_BLOCK pDevice) { + PLM_PACKET pPacket; + LM_UINT32 HwConIdx; + LM_UINT32 SwConIdx; + + HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; + + /* Get our copy of the consumer index. The buffer descriptors */ + /* that are in between the consumer indices are freed. */ + SwConIdx = pDevice->SendConIdx; + + /* Move the packets from the TxPacketActiveQ that are sent out to */ + /* the TxPacketXmittedQ. Packets that are sent use the */ + /* descriptors that are between SwConIdx and HwConIdx. */ + while(SwConIdx != HwConIdx) + { + /* Get the packet that was sent from the TxPacketActiveQ. */ + pPacket = (PLM_PACKET) QQ_PopHead( + &pDevice->TxPacketActiveQ.Container); + + /* Set the return status. */ + pPacket->PacketStatus = LM_STATUS_SUCCESS; + + /* Put the packet in the TxPacketXmittedQ for indication later. */ + QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); + + /* Move to the next packet's BD. */ + SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) & + T3_SEND_RCB_ENTRY_COUNT_MASK; + + /* Update the number of unused BDs. */ + atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + + /* Get the new updated HwConIdx. */ + HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; + } /* while */ + + /* Save the new SwConIdx. */ + pDevice->SendConIdx = SwConIdx; + +} /* LM_ServiceTxInterrupt */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +__inline static void +LM_ServiceRxInterrupt( +PLM_DEVICE_BLOCK pDevice) { + PLM_PACKET pPacket; + PT3_RCV_BD pRcvBd; + LM_UINT32 HwRcvRetProdIdx; + LM_UINT32 SwRcvRetConIdx; + + /* Loop thru the receive return rings for received packets. */ + HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + + SwRcvRetConIdx = pDevice->RcvRetConIdx; + while(SwRcvRetConIdx != HwRcvRetProdIdx) + { + pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx]; + + /* Get the received packet descriptor. */ + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pRcvBd->Opaque)); + + /* Check the error flag. */ + if(pRcvBd->ErrorFlag && + pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) + { + pPacket->PacketStatus = LM_STATUS_FAILURE; + + pDevice->RxCounters.RxPacketErrCnt++; + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) + { + pDevice->RxCounters.RxErrCrcCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) + { + pDevice->RxCounters.RxErrCollCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) + { + pDevice->RxCounters.RxErrLinkLostCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) + { + pDevice->RxCounters.RxErrPhyDecodeCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) + { + pDevice->RxCounters.RxErrOddNibbleCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) + { + pDevice->RxCounters.RxErrMacAbortCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) + { + pDevice->RxCounters.RxErrShortPacketCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) + { + pDevice->RxCounters.RxErrNoResourceCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) + { + pDevice->RxCounters.RxErrLargePacketCnt++; + } + } + else + { + pPacket->PacketStatus = LM_STATUS_SUCCESS; + pPacket->PacketSize = pRcvBd->Len - 4; + + pPacket->Flags = pRcvBd->Flags; + if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) + { + pPacket->VlanTag = pRcvBd->VlanTag; + } + + pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum; + } + + /* Put the packet descriptor containing the received packet */ + /* buffer in the RxPacketReceivedQ for indication later. */ + QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket); + + /* Go to the next buffer descriptor. */ + SwRcvRetConIdx = (SwRcvRetConIdx + 1) & + T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK; + + /* Get the updated HwRcvRetProdIdx. */ + HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + } /* while */ + + pDevice->RcvRetConIdx = SwRcvRetConIdx; + + /* Update the receive return ring consumer index. */ + MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx); +} /* LM_ServiceRxInterrupt */ + + +/******************************************************************************/ +/* Description: */ +/* This is the interrupt event handler routine. It acknowledges all */ +/* pending interrupts and process all pending events. */ +/* */ +/* Return: */ +/* LM_STATUS_SUCCESS */ +/******************************************************************************/ +LM_STATUS +LM_ServiceInterrupts( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + int ServicePhyInt = FALSE; + + /* Setup the phy chip whenever the link status changes. */ + if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) + { + Value32 = REG_RD(pDevice, MacCtrl.Status); + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) + { + if (Value32 & MAC_STATUS_MI_INTERRUPT) + { + ServicePhyInt = TRUE; + } + } + else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED) + { + ServicePhyInt = TRUE; + } + } + else + { + if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS) + { + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | + (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); + ServicePhyInt = TRUE; + } + } +#if INCLUDE_TBI_SUPPORT + if (pDevice->IgnoreTbiLinkChange == TRUE) + { + ServicePhyInt = FALSE; + } +#endif + if (ServicePhyInt == TRUE) + { + LM_SetupPhy(pDevice); + } + + /* Service receive and transmit interrupts. */ + LM_ServiceRxInterrupt(pDevice); + LM_ServiceTxInterrupt(pDevice); + + /* No spinlock for this queue since this routine is serialized. */ + if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container)) + { + /* Indicate receive packets. */ + MM_IndicateRxPackets(pDevice); + /* LM_QueueRxPackets(pDevice); */ + } + + /* No spinlock for this queue since this routine is serialized. */ + if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container)) + { + MM_IndicateTxPackets(pDevice); + } + + return LM_STATUS_SUCCESS; +} /* LM_ServiceInterrupts */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_MulticastAdd( +PLM_DEVICE_BLOCK pDevice, +PLM_UINT8 pMcAddress) { + PLM_UINT8 pEntry; + LM_UINT32 j; + + pEntry = pDevice->McTable[0]; + for(j = 0; j < pDevice->McEntryCount; j++) + { + if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) + { + /* Found a match, increment the instance count. */ + pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1; + + return LM_STATUS_SUCCESS; + } + + pEntry += LM_MC_ENTRY_SIZE; + } + + if(pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) + { + return LM_STATUS_FAILURE; + } + + pEntry = pDevice->McTable[pDevice->McEntryCount]; + + COPY_ETH_ADDRESS(pMcAddress, pEntry); + pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1; + + pDevice->McEntryCount++; + + LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST); + + return LM_STATUS_SUCCESS; +} /* LM_MulticastAdd */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_MulticastDel( +PLM_DEVICE_BLOCK pDevice, +PLM_UINT8 pMcAddress) { + PLM_UINT8 pEntry; + LM_UINT32 j; + + pEntry = pDevice->McTable[0]; + for(j = 0; j < pDevice->McEntryCount; j++) + { + if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) + { + /* Found a match, decrement the instance count. */ + pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1; + + /* No more instance left, remove the address from the table. */ + /* Move the last entry in the table to the delete slot. */ + if(pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 && + pDevice->McEntryCount > 1) + { + + COPY_ETH_ADDRESS( + pDevice->McTable[pDevice->McEntryCount-1], pEntry); + pEntry[LM_MC_INSTANCE_COUNT_INDEX] = + pDevice->McTable[pDevice->McEntryCount-1] + [LM_MC_INSTANCE_COUNT_INDEX]; + } + pDevice->McEntryCount--; + + /* Update the receive mask if the table is empty. */ + if(pDevice->McEntryCount == 0) + { + LM_SetReceiveMask(pDevice, + pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); + } + + return LM_STATUS_SUCCESS; + } + + pEntry += LM_MC_ENTRY_SIZE; + } + + return LM_STATUS_FAILURE; +} /* LM_MulticastDel */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_MulticastClear( +PLM_DEVICE_BLOCK pDevice) { + pDevice->McEntryCount = 0; + + LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); + + return LM_STATUS_SUCCESS; +} /* LM_MulticastClear */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetMacAddress( + PLM_DEVICE_BLOCK pDevice, + PLM_UINT8 pMacAddress) +{ + LM_UINT32 j; + + for(j = 0; j < 4; j++) + { + REG_WR(pDevice, MacCtrl.MacAddr[j].High, + (pMacAddress[0] << 8) | pMacAddress[1]); + REG_WR(pDevice, MacCtrl.MacAddr[j].Low, + (pMacAddress[2] << 24) | (pMacAddress[3] << 16) | + (pMacAddress[4] << 8) | pMacAddress[5]); + } + + return LM_STATUS_SUCCESS; +} + + +/******************************************************************************/ +/* Description: */ +/* Sets up the default line speed, and duplex modes based on the requested */ +/* media type. */ +/* */ +/* Return: */ +/* None. */ +/******************************************************************************/ +static LM_STATUS +LM_TranslateRequestedMediaType( +LM_REQUESTED_MEDIA_TYPE RequestedMediaType, +PLM_MEDIA_TYPE pMediaType, +PLM_LINE_SPEED pLineSpeed, +PLM_DUPLEX_MODE pDuplexMode) { + *pMediaType = LM_MEDIA_TYPE_AUTO; + *pLineSpeed = LM_LINE_SPEED_UNKNOWN; + *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN; + + /* determine media type */ + switch(RequestedMediaType) { + case LM_REQUESTED_MEDIA_TYPE_BNC: + *pMediaType = LM_MEDIA_TYPE_BNC; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO: + *pMediaType = LM_MEDIA_TYPE_UTP; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + default: + break; + } /* switch */ + + return LM_STATUS_SUCCESS; +} /* LM_TranslateRequestedMediaType */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* LM_STATUS_LINK_ACTIVE */ +/* LM_STATUS_LINK_DOWN */ +/******************************************************************************/ +static LM_STATUS +LM_InitBcm540xPhy( +PLM_DEVICE_BLOCK pDevice) +{ + LM_LINE_SPEED CurrentLineSpeed; + LM_DUPLEX_MODE CurrentDuplexMode; + LM_STATUS CurrentLinkStatus; + LM_UINT32 Value32; + LM_UINT32 j; + +#if 1 /* jmb: bugfix -- moved here, out of code that sets initial pwr state */ + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x2); +#endif + if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) + { + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + if(!pDevice->InitDone) + { + Value32 = 0; + } + + if(!(Value32 & PHY_STATUS_LINK_PASS)) + { + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + for(j = 0; j < 1000; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + if(Value32 & PHY_STATUS_LINK_PASS) + { + MM_Wait(40); + break; + } + } + + if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV) + { + if(!(Value32 & PHY_STATUS_LINK_PASS) && + (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS)) + { + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); + for(j = 0; j < 100; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(!(Value32 & PHY_CTRL_PHY_RESET)) + { + MM_Wait(40); + break; + } + } + + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + } + } + } + } + else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + /* Bug: 5701 A0, B0 TX CRC workaround. */ + LM_WritePhy(pDevice, 0x15, 0x0a75); + LM_WritePhy(pDevice, 0x1c, 0x8c68); + LM_WritePhy(pDevice, 0x1c, 0x8d68); + LM_WritePhy(pDevice, 0x1c, 0x8c68); + } + + /* Acknowledge interrupts. */ + LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32); + + /* Configure the interrupt mask. */ + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) + { + LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE); + } + + /* Configure PHY led mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 || + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)) + { + if(pDevice->LedMode == LED_MODE_THREE_LINK) + { + LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, + BCM540X_EXT_CTRL_LINK3_LED_MODE); + } + else + { + LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0); + } + } + + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + + /* Get current link and duplex mode. */ + for(j = 0; j < 100; j++) + { + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + if(Value32 & PHY_STATUS_LINK_PASS) + { + break; + } + MM_Wait(40); + } + + if(Value32 & PHY_STATUS_LINK_PASS) + { + + /* Determine the current line and duplex settings. */ + LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); + for(j = 0; j < 2000; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); + if(Value32) + { + break; + } + } + + switch(Value32 & BCM540X_AUX_SPEED_MASK) + { + case BCM540X_AUX_10BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_10BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case BCM540X_AUX_100BASETX_HD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_100BASETX_FD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case BCM540X_AUX_100BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_100BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + default: + + CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN; + CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN; + break; + } + + /* Make sure we are in auto-neg mode. */ + for (j = 0; j < 200; j++) + { + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(Value32 && Value32 != 0x7fff) + { + break; + } + + if(Value32 == 0 && pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) + { + break; + } + + MM_Wait(10); + } + + /* Use the current line settings for "auto" mode. */ + if(pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) + { + if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + + /* We may be exiting low power mode and the link is in */ + /* 10mb. In this case, we need to restart autoneg. */ + LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &Value32); + pDevice->advertising1000 = Value32; + /* 5702FE supports 10/100Mb only. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703 || + pDevice->BondId != GRC_MISC_BD_ID_5702FE) + { + if(!(Value32 & (BCM540X_AN_AD_1000BASET_HALF | + BCM540X_AN_AD_1000BASET_FULL))) + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + else + { + /* Force line settings. */ + /* Use the current setting if it matches the user's requested */ + /* setting. */ + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if((pDevice->LineSpeed == CurrentLineSpeed) && + (pDevice->DuplexMode == CurrentDuplexMode)) + { + if ((pDevice->DisableAutoNeg && + !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) || + (!pDevice->DisableAutoNeg && + (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + + /* Save line settings. */ + pDevice->LineSpeed = CurrentLineSpeed; + pDevice->DuplexMode = CurrentDuplexMode; + pDevice->MediaType = LM_MEDIA_TYPE_UTP; + } + + return CurrentLinkStatus; +} /* LM_InitBcm540xPhy */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetFlowControl( + PLM_DEVICE_BLOCK pDevice, + LM_UINT32 LocalPhyAd, + LM_UINT32 RemotePhyAd) +{ + LM_FLOW_CONTROL FlowCap; + + /* Resolve flow control. */ + FlowCap = LM_FLOW_CONTROL_NONE; + + /* See Table 28B-3 of 802.3ab-1999 spec. */ + if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) + { + if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) + { + if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) + { + if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE) + { + FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + else + { + if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + } + else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) + { + if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) && + (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + } + } + else + { + FlowCap = pDevice->FlowControlCap; + } + + /* Enable/disable rx PAUSE. */ + pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL; + if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE && + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) + { + pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE; + pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL; + + } + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + + /* Enable/disable tx PAUSE. */ + pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL; + if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE && + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) + { + pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; + pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL; + + } + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + + return LM_STATUS_SUCCESS; +} + + +#if INCLUDE_TBI_SUPPORT +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_InitBcm800xPhy( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + LM_UINT32 j; + + Value32 = REG_RD(pDevice, MacCtrl.Status); + + /* Reset the SERDES during init and when we have link. */ + if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) + { + /* Set PLL lock range. */ + LM_WritePhy(pDevice, 0x16, 0x8007); + + /* Software reset. */ + LM_WritePhy(pDevice, 0x00, 0x8000); + + /* Wait for reset to complete. */ + for(j = 0; j < 500; j++) + { + MM_Wait(10); + } + + /* Config mode; seletct PMA/Ch 1 regs. */ + LM_WritePhy(pDevice, 0x10, 0x8411); + + /* Enable auto-lock and comdet, select txclk for tx. */ + LM_WritePhy(pDevice, 0x11, 0x0a10); + + LM_WritePhy(pDevice, 0x18, 0x00a0); + LM_WritePhy(pDevice, 0x16, 0x41ff); + + /* Assert and deassert POR. */ + LM_WritePhy(pDevice, 0x13, 0x0400); + MM_Wait(40); + LM_WritePhy(pDevice, 0x13, 0x0000); + + LM_WritePhy(pDevice, 0x11, 0x0a50); + MM_Wait(40); + LM_WritePhy(pDevice, 0x11, 0x0a10); + + /* Delay for signal to stabilize. */ + for(j = 0; j < 15000; j++) + { + MM_Wait(10); + } + + /* Deselect the channel register so we can read the PHY id later. */ + LM_WritePhy(pDevice, 0x10, 0x8011); + } + + return LM_STATUS_SUCCESS; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +STATIC LM_STATUS +LM_SetupFiberPhy( + PLM_DEVICE_BLOCK pDevice) +{ + LM_STATUS CurrentLinkStatus; + AUTONEG_STATUS AnStatus = 0; + LM_UINT32 Value32; + LM_UINT32 Cnt; + LM_UINT32 j, k; + + pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK); + + /* Initialize the send_config register. */ + REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); + + /* Enable TBI and full duplex mode. */ + pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + + /* Initialize the BCM8002 SERDES PHY. */ + switch(pDevice->PhyId & PHY_ID_MASK) + { + case PHY_BCM8002_PHY_ID: + LM_InitBcm800xPhy(pDevice); + break; + + default: + break; + } + + /* Enable link change interrupt. */ + REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); + + /* Default to link down. */ + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + + /* Get the link status. */ + Value32 = REG_RD(pDevice, MacCtrl.Status); + if(Value32 & MAC_STATUS_PCS_SYNCED) + { + if((pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO) || + (pDevice->DisableAutoNeg == FALSE)) + { + /* auto-negotiation mode. */ + /* Initialize the autoneg default capaiblities. */ + AutonegInit(&pDevice->AnInfo); + + /* Set the context pointer to point to the main device structure. */ + pDevice->AnInfo.pContext = pDevice; + + /* Setup flow control advertisement register. */ + Value32 = GetPhyAdFlowCntrlSettings(pDevice); + if(Value32 & PHY_AN_AD_PAUSE_CAPABLE) + { + pDevice->AnInfo.mr_adv_sym_pause = 1; + } + else + { + pDevice->AnInfo.mr_adv_sym_pause = 0; + } + + if(Value32 & PHY_AN_AD_ASYM_PAUSE) + { + pDevice->AnInfo.mr_adv_asym_pause = 1; + } + else + { + pDevice->AnInfo.mr_adv_asym_pause = 0; + } + + /* Try to autoneg up to six times. */ + if (pDevice->IgnoreTbiLinkChange) + { + Cnt = 1; + } + else + { + Cnt = 6; + } + for (j = 0; j < Cnt; j++) + { + REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); + + Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK; + REG_WR(pDevice, MacCtrl.Mode, Value32); + MM_Wait(20); + + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + + MM_Wait(20); + + pDevice->AnInfo.State = AN_STATE_UNKNOWN; + pDevice->AnInfo.CurrentTime_us = 0; + + REG_WR(pDevice, Grc.Timer, 0); + for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) && + (k < 75000); k++) + { + AnStatus = Autoneg8023z(&pDevice->AnInfo); + + if((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) + { + break; + } + + pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer); + + } + if((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) + { + break; + } + if (j >= 1) + { + if (!(REG_RD(pDevice, MacCtrl.Status) & + MAC_STATUS_PCS_SYNCED)) { + break; + } + } + } + + /* Stop sending configs. */ + MM_AnTxIdle(&pDevice->AnInfo); + + /* Resolve flow control settings. */ + if((AnStatus == AUTONEG_STATUS_DONE) && + pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok && + pDevice->AnInfo.mr_lp_adv_full_duplex) + { + LM_UINT32 RemotePhyAd; + LM_UINT32 LocalPhyAd; + + LocalPhyAd = 0; + if(pDevice->AnInfo.mr_adv_sym_pause) + { + LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE; + } + + if(pDevice->AnInfo.mr_adv_asym_pause) + { + LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE; + } + + RemotePhyAd = 0; + if(pDevice->AnInfo.mr_lp_adv_sym_pause) + { + RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE; + } + + if(pDevice->AnInfo.mr_lp_adv_asym_pause) + { + RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE; + } + + LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + for (j = 0; j < 30; j++) + { + MM_Wait(20); + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MM_Wait(20); + if ((REG_RD(pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) + break; + } + if (pDevice->PollTbiLink) + { + Value32 = REG_RD(pDevice, MacCtrl.Status); + if (Value32 & MAC_STATUS_RECEIVING_CFG) + { + pDevice->IgnoreTbiLinkChange = TRUE; + } + else + { + pDevice->IgnoreTbiLinkChange = FALSE; + } + } + Value32 = REG_RD(pDevice, MacCtrl.Status); + if (CurrentLinkStatus == LM_STATUS_LINK_DOWN && + (Value32 & MAC_STATUS_PCS_SYNCED) && + ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } + else + { + /* We are forcing line speed. */ + pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl(pDevice, 0, 0); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + } + } + /* Set the link polarity bit. */ + pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | + (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); + + for (j = 0; j < 100; j++) + { + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MM_Wait(5); + if ((REG_RD(pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) + break; + } + + Value32 = REG_RD(pDevice, MacCtrl.Status); + if((Value32 & MAC_STATUS_PCS_SYNCED) == 0) + { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + if (pDevice->DisableAutoNeg == FALSE) + { + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + MM_Wait(1); + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + } + } + + /* Initialize the current link status. */ + if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) + { + pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS; + pDevice->DuplexMode = LM_DUPLEX_MODE_FULL; + REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_1000MBPS_LED_ON); + } + else + { + pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN; + pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN; + REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_OVERRIDE_TRAFFIC_LED); + } + + /* Indicate link status. */ + if (pDevice->LinkStatus != CurrentLinkStatus) { + pDevice->LinkStatus = CurrentLinkStatus; + MM_IndicateStatus(pDevice, CurrentLinkStatus); + } + + return LM_STATUS_SUCCESS; +} +#endif /* INCLUDE_TBI_SUPPORT */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetupCopperPhy( + PLM_DEVICE_BLOCK pDevice) +{ + LM_STATUS CurrentLinkStatus; + LM_UINT32 Value32; + + /* Assume there is not link first. */ + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + + /* Disable phy link change attention. */ + REG_WR(pDevice, MacCtrl.MacEvent, 0); + + /* Clear link change attention. */ + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + + /* Disable auto-polling for the moment. */ + pDevice->MiMode = 0xc0000; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait(40); + + /* Determine the requested line speed and duplex. */ + pDevice->OldLineSpeed = pDevice->LineSpeed; + LM_TranslateRequestedMediaType(pDevice->RequestedMediaType, + &pDevice->MediaType, &pDevice->LineSpeed, &pDevice->DuplexMode); + + /* Initialize the phy chip. */ + switch(pDevice->PhyId & PHY_ID_MASK) + { + case PHY_BCM5400_PHY_ID: + case PHY_BCM5401_PHY_ID: + case PHY_BCM5411_PHY_ID: + case PHY_BCM5701_PHY_ID: + case PHY_BCM5703_PHY_ID: + case PHY_BCM5704_PHY_ID: + CurrentLinkStatus = LM_InitBcm540xPhy(pDevice); + break; + + default: + break; + } + + if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) + { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + } + + /* Setup flow control. */ + pDevice->FlowControl = LM_FLOW_CONTROL_NONE; + if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) + { + LM_FLOW_CONTROL FlowCap; /* Flow control capability. */ + + FlowCap = LM_FLOW_CONTROL_NONE; + + if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) + { + if(pDevice->DisableAutoNeg == FALSE || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) + { + LM_UINT32 ExpectedPhyAd; + LM_UINT32 LocalPhyAd; + LM_UINT32 RemotePhyAd; + + LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd); + pDevice->advertising = LocalPhyAd; + LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE); + + ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice); + + if(LocalPhyAd != ExpectedPhyAd) + { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + } + else + { + LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG, + &RemotePhyAd); + + LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + } + } + else + { + pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl(pDevice, 0, 0); + } + } + } + + if(CurrentLinkStatus == LM_STATUS_LINK_DOWN) + { + LM_ForceAutoNeg(pDevice, pDevice->RequestedMediaType); + + /* If we force line speed, we make get link right away. */ + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + if(Value32 & PHY_STATUS_LINK_PASS) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } + + /* GMII interface. */ + pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK; + if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) + { + if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS || + pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) + { + pDevice->MacMode |= MAC_MODE_PORT_MODE_MII; + } + else + { + pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; + } + } + else { + pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; + } + + /* Set the MAC to operate in the appropriate duplex mode. */ + pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX; + if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) + { + pDevice->MacMode |= MAC_MODE_HALF_DUPLEX; + } + + /* Set the link polarity bit. */ + pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + if((pDevice->LedMode == LED_MODE_LINK10) || + (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE && + pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) + { + pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + } + } + else + { + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) + { + pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + } + + /* Set LED mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = LED_CTRL_PHY_MODE_1; + } + else + { + if(pDevice->LedMode == LED_MODE_OUTPUT) + { + Value32 = LED_CTRL_PHY_MODE_2; + } + else + { + Value32 = LED_CTRL_PHY_MODE_1; + } + } + REG_WR(pDevice, MacCtrl.LedCtrl, Value32); + } + + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + + /* Enable auto polling. */ + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + } + + /* Enable phy link change attention. */ + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) + { + REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT); + } + else + { + REG_WR(pDevice, MacCtrl.MacEvent, + MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); + } + if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) && + (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) && + (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && + (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) && + (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) || + !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) + { + MM_Wait(120); + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX, + T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE); + } + + /* Indicate link status. */ + if (pDevice->LinkStatus != CurrentLinkStatus) { + pDevice->LinkStatus = CurrentLinkStatus; + MM_IndicateStatus(pDevice, CurrentLinkStatus); + } + + return LM_STATUS_SUCCESS; +} /* LM_SetupCopperPhy */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetupPhy( + PLM_DEVICE_BLOCK pDevice) +{ + LM_STATUS LmStatus; + LM_UINT32 Value32; + +#if INCLUDE_TBI_SUPPORT + if(pDevice->EnableTbi) + { + LmStatus = LM_SetupFiberPhy(pDevice); + } + else +#endif /* INCLUDE_TBI_SUPPORT */ + { + LmStatus = LM_SetupCopperPhy(pDevice); + } + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 = REG_RD(pDevice, PciCfg.PciState); + REG_WR(pDevice, PciCfg.PciState, + Value32 | T3_PCI_STATE_RETRY_SAME_DMA); + } + } + if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && + (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) + { + REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff); + } + else + { + REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); + } + + return LmStatus; +} + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_ReadPhy( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 PhyReg, +PLM_UINT32 pData32) { + LM_UINT32 Value32; + LM_UINT32 j; + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & + ~MI_MODE_AUTO_POLLING_ENABLE); + MM_Wait(40); + } + + Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | + ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | + MI_COM_CMD_READ | MI_COM_START; + + REG_WR(pDevice, MacCtrl.MiCom, Value32); + + for(j = 0; j < 20; j++) + { + MM_Wait(25); + + Value32 = REG_RD(pDevice, MacCtrl.MiCom); + + if(!(Value32 & MI_COM_BUSY)) + { + MM_Wait(5); + Value32 = REG_RD(pDevice, MacCtrl.MiCom); + Value32 &= MI_COM_PHY_DATA_MASK; + break; + } + } + + if(Value32 & MI_COM_BUSY) + { + Value32 = 0; + } + + *pData32 = Value32; + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait(40); + } +} /* LM_ReadPhy */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_VOID +LM_WritePhy( +PLM_DEVICE_BLOCK pDevice, +LM_UINT32 PhyReg, +LM_UINT32 Data32) { + LM_UINT32 Value32; + LM_UINT32 j; + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & + ~MI_MODE_AUTO_POLLING_ENABLE); + MM_Wait(40); + } + + Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | + ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | + (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START; + + REG_WR(pDevice, MacCtrl.MiCom, Value32); + + for(j = 0; j < 20; j++) + { + MM_Wait(25); + + Value32 = REG_RD(pDevice, MacCtrl.MiCom); + + if(!(Value32 & MI_COM_BUSY)) + { + MM_Wait(5); + break; + } + } + + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) + { + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait(40); + } +} /* LM_WritePhy */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS +LM_SetPowerState( +PLM_DEVICE_BLOCK pDevice, +LM_POWER_STATE PowerLevel) { + LM_UINT32 PmeSupport; + LM_UINT32 Value32; + LM_UINT32 PmCtrl; + + /* make sureindirect accesses are enabled*/ + MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl); + + /* Clear the PME_ASSERT bit and the power state bits. Also enable */ + /* the PME bit. */ + MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl); + + PmCtrl |= T3_PM_PME_ASSERTED; + PmCtrl &= ~T3_PM_POWER_STATE_MASK; + + /* Set the appropriate power state. */ + if(PowerLevel == LM_POWER_STATE_D0) + { + + /* Bring the card out of low power mode. */ + PmCtrl |= T3_PM_POWER_STATE_D0; + MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); + + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); + MM_Wait (40); +#if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */ + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02); +#endif + + return LM_STATUS_SUCCESS; + } + else if(PowerLevel == LM_POWER_STATE_D1) + { + PmCtrl |= T3_PM_POWER_STATE_D1; + } + else if(PowerLevel == LM_POWER_STATE_D2) + { + PmCtrl |= T3_PM_POWER_STATE_D2; + } + else if(PowerLevel == LM_POWER_STATE_D3) + { + PmCtrl |= T3_PM_POWER_STATE_D3; + } + else + { + return LM_STATUS_FAILURE; + } + PmCtrl |= T3_PM_PME_ENABLE; + + /* Mask out all interrupts so LM_SetupPhy won't be called while we are */ + /* setting new line speed. */ + Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl); + REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT); + + if(!pDevice->RestoreOnWakeUp) + { + pDevice->RestoreOnWakeUp = TRUE; + pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg; + pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType; + } + + /* Force auto-negotiation to 10 line speed. */ + pDevice->DisableAutoNeg = FALSE; + pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS; + LM_SetupPhy(pDevice); + + /* Put the driver in the initial state, and go through the power down */ + /* sequence. */ + LM_Halt(pDevice); + + MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport); + + if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) + { + + /* Enable WOL. */ + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a); + MM_Wait(40); + + /* Set LED mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = LED_CTRL_PHY_MODE_1; + } + else + { + if(pDevice->LedMode == LED_MODE_OUTPUT) + { + Value32 = LED_CTRL_PHY_MODE_2; + } + else + { + Value32 = LED_CTRL_PHY_MODE_1; + } + } + + Value32 = MAC_MODE_PORT_MODE_MII; + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + if(pDevice->LedMode == LED_MODE_LINK10 || + pDevice->WolSpeed == WOL_SPEED_10MB) + { + Value32 |= MAC_MODE_LINK_POLARITY; + } + } + else + { + Value32 |= MAC_MODE_LINK_POLARITY; + } + REG_WR(pDevice, MacCtrl.Mode, Value32); + MM_Wait(40); MM_Wait(40); MM_Wait(40); + + /* Always enable magic packet wake-up if we have vaux. */ + if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) && + (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) + { + Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE; + } + + REG_WR(pDevice, MacCtrl.Mode, Value32); + + /* Enable the receiver. */ + REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE); + } + + /* Disable tx/rx clocks, and seletect an alternate clock. */ + if(pDevice->WolSpeed == WOL_SPEED_100MB) + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK; + } + else + { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK; + } + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + + MM_Wait(40); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK; + } + else + { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } + + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + + MM_Wait(40); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } + else + { + Value32 = T3_PCI_44MHZ_CORE_CLOCK; + } + + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + } + else + { + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_POWER_DOWN_PCI_PLL133; + } + else + { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_POWER_DOWN_PCI_PLL133; + } + + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + } + + MM_Wait(40); + + if(!pDevice->EepromWp && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) + { + /* Switch adapter to auxilliary power. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + MM_Wait(40); + } + else + { + /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); + MM_Wait(40); + + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); + MM_Wait(40); + + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + MM_Wait(40); + } + } + + /* Set the phy to low power mode. */ + /* Put the the hardware in low power mode. */ + MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); + + return LM_STATUS_SUCCESS; +} /* LM_SetPowerState */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +static LM_UINT32 +GetPhyAdFlowCntrlSettings( + PLM_DEVICE_BLOCK pDevice) +{ + LM_UINT32 Value32; + + Value32 = 0; + + /* Auto negotiation flow control only when autonegotiation is enabled. */ + if(pDevice->DisableAutoNeg == FALSE || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) + { + /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */ + if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) || + ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) && + (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) + { + Value32 |= PHY_AN_AD_PAUSE_CAPABLE; + } + else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + { + Value32 |= PHY_AN_AD_ASYM_PAUSE; + } + else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) + { + Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE; + } + } + + return Value32; +} + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/* LM_STATUS_FAILURE */ +/* LM_STATUS_SUCCESS */ +/* */ +/******************************************************************************/ +static LM_STATUS +LM_ForceAutoNegBcm540xPhy( +PLM_DEVICE_BLOCK pDevice, +LM_REQUESTED_MEDIA_TYPE RequestedMediaType) +{ + LM_MEDIA_TYPE MediaType; + LM_LINE_SPEED LineSpeed; + LM_DUPLEX_MODE DuplexMode; + LM_UINT32 NewPhyCtrl; + LM_UINT32 Value32; + LM_UINT32 Cnt; + + /* Get the interface type, line speed, and duplex mode. */ + LM_TranslateRequestedMediaType(RequestedMediaType, &MediaType, &LineSpeed, + &DuplexMode); + + if (pDevice->RestoreOnWakeUp) + { + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF; + if (pDevice->WolSpeed == WOL_SPEED_100MB) + { + Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + } + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } + /* Setup the auto-negotiation advertisement register. */ + else if(LineSpeed == LM_LINE_SPEED_UNKNOWN) + { + /* Setup the 10/100 Mbps auto-negotiation advertisement register. */ + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + /* Advertise 1000Mbps */ + Value32 = BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL; + +#if INCLUDE_5701_AX_FIX + /* Bug: workaround for CRC error in gigabit mode when we are in */ + /* slave mode. This will force the PHY to operate in */ + /* master mode. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + Value32 |= BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + } +#endif + + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; + } + else + { + if(LineSpeed == LM_LINE_SPEED_1000MBPS) + { + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + if(DuplexMode != LM_DUPLEX_MODE_FULL) + { + Value32 = BCM540X_AN_AD_1000BASET_HALF; + } + else + { + Value32 = BCM540X_AN_AD_1000BASET_FULL; + } + + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; + } + else if(LineSpeed == LM_LINE_SPEED_100MBPS) + { + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + + if(DuplexMode != LM_DUPLEX_MODE_FULL) + { + Value32 = PHY_AN_AD_100BASETX_HALF; + } + else + { + Value32 = PHY_AN_AD_100BASETX_FULL; + } + + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } + else if(LineSpeed == LM_LINE_SPEED_10MBPS) + { + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + + if(DuplexMode != LM_DUPLEX_MODE_FULL) + { + Value32 = PHY_AN_AD_10BASET_HALF; + } + else + { + Value32 = PHY_AN_AD_10BASET_FULL; + } + + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } + } + + /* Force line speed if auto-negotiation is disabled. */ + if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) + { + /* This code path is executed only when there is link. */ + pDevice->MediaType = MediaType; + pDevice->LineSpeed = LineSpeed; + pDevice->DuplexMode = DuplexMode; + + /* Force line seepd. */ + NewPhyCtrl = 0; + switch(LineSpeed) + { + case LM_LINE_SPEED_10MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS; + break; + case LM_LINE_SPEED_100MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS; + break; + case LM_LINE_SPEED_1000MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; + break; + default: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; + break; + } + + if(DuplexMode == LM_DUPLEX_MODE_FULL) + { + NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE; + } + + /* Don't do anything if the PHY_CTRL is already what we wanted. */ + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(Value32 != NewPhyCtrl) + { + /* Temporary bring the link down before forcing line speed. */ + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE); + + /* Wait for link to go down. */ + for(Cnt = 0; Cnt < 15000; Cnt++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + if(!(Value32 & PHY_STATUS_LINK_PASS)) + { + MM_Wait(40); + break; + } + } + + LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl); + MM_Wait(40); + } + } + else + { + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } + + return LM_STATUS_SUCCESS; +} /* LM_ForceAutoNegBcm540xPhy */ + + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +static LM_STATUS +LM_ForceAutoNeg( +PLM_DEVICE_BLOCK pDevice, +LM_REQUESTED_MEDIA_TYPE RequestedMediaType) +{ + LM_STATUS LmStatus; + + /* Initialize the phy chip. */ + switch(pDevice->PhyId & PHY_ID_MASK) + { + case PHY_BCM5400_PHY_ID: + case PHY_BCM5401_PHY_ID: + case PHY_BCM5411_PHY_ID: + case PHY_BCM5701_PHY_ID: + case PHY_BCM5703_PHY_ID: + case PHY_BCM5704_PHY_ID: + LmStatus = LM_ForceAutoNegBcm540xPhy(pDevice, RequestedMediaType); + break; + + default: + LmStatus = LM_STATUS_FAILURE; + break; + } + + return LmStatus; +} /* LM_ForceAutoNeg */ + +/******************************************************************************/ +/* Description: */ +/* */ +/* Return: */ +/******************************************************************************/ +LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice, + PT3_FWIMG_INFO pFwImg, + LM_UINT32 LoadCpu, + LM_UINT32 StartCpu) +{ + LM_UINT32 i; + LM_UINT32 address; + + if (LoadCpu & T3_RX_CPU_ID) + { + if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + /* First of all clear scrach pad memory */ + for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i+=4) + { + LM_RegWrInd(pDevice,T3_RX_CPU_SPAD_ADDR+i,0); + } + + /* Copy code first */ + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); + for (i = 0; i <= pFwImg->Text.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); + } + + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); + for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); + } + + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); + for (i= 0; i <= pFwImg->Data.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); + } + } + + if (LoadCpu & T3_TX_CPU_ID) + { + if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + /* First of all clear scrach pad memory */ + for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4) + { + LM_RegWrInd(pDevice,T3_TX_CPU_SPAD_ADDR+i,0); + } + + /* Copy code first */ + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); + for (i= 0; i <= pFwImg->Text.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); + } + + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); + for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); + } + + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); + for (i= 0; i <= pFwImg->Data.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); + } + } + + if (StartCpu & T3_RX_CPU_ID) + { + /* Start Rx CPU */ + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); + for (i = 0 ; i < 5; i++) + { + if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC)) + break; + + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); + MM_Wait(1000); + } + + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode, 0); + } + + if (StartCpu & T3_TX_CPU_ID) + { + /* Start Tx CPU */ + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); + for (i = 0 ; i < 5; i++) + { + if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC)) + break; + + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); + REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); + MM_Wait(1000); + } + + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.mode, 0); + } + + return LM_STATUS_SUCCESS; +} + +STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number) +{ + LM_UINT32 i; + + if (cpu_number == T3_RX_CPU_ID) + { + for (i = 0 ; i < 10000; i++) + { + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + + if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT) + break; + } + + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + MM_Wait(10); + } + else + { + for (i = 0 ; i < 10000; i++) + { + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); + + if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT) + break; + } + } + + return (( i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS); +} + + +int +LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) +{ + LM_UINT32 Oldcfg; + int j; + int ret = 0; + + if(BlinkDurationSec == 0) + { + return 0; + } + if(BlinkDurationSec > 120) + { + BlinkDurationSec = 120; + } + + Oldcfg = REG_RD(pDevice, MacCtrl.LedCtrl); + for(j = 0; j < BlinkDurationSec * 2; j++) + { + if(j % 2) + { + /* Turn on the LEDs. */ + REG_WR(pDevice, MacCtrl.LedCtrl, + LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_1000MBPS_LED_ON | + LED_CTRL_100MBPS_LED_ON | + LED_CTRL_10MBPS_LED_ON | + LED_CTRL_OVERRIDE_TRAFFIC_LED | + LED_CTRL_BLINK_TRAFFIC_LED | + LED_CTRL_TRAFFIC_LED); + } + else + { + /* Turn off the LEDs. */ + REG_WR(pDevice, MacCtrl.LedCtrl, + LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_OVERRIDE_TRAFFIC_LED); + } + +#ifndef EMBEDDED + current->state = TASK_INTERRUPTIBLE; + if (schedule_timeout(HZ/2) != 0) { + ret = -EINTR; + break; + } +#else + udelay(100000); /* 1s sleep */ +#endif + } + REG_WR(pDevice, MacCtrl.LedCtrl, Oldcfg); + return ret; +} + +int t3_do_dma(PLM_DEVICE_BLOCK pDevice, + LM_PHYSICAL_ADDRESS host_addr_phy, int length, + int dma_read) +{ + T3_DMA_DESC dma_desc; + int i; + LM_UINT32 dma_desc_addr; + LM_UINT32 value32; + + REG_WR(pDevice, BufMgr.Mode, 0); + REG_WR(pDevice, Ftq.Reset, 0); + + dma_desc.host_addr.High = host_addr_phy.High; + dma_desc.host_addr.Low = host_addr_phy.Low; + dma_desc.nic_mbuf = 0x2100; + dma_desc.len = length; + dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */ + + if (dma_read) + { + dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) | + T3_QID_DMA_HIGH_PRI_READ; + REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE); + } + else + { + dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) | + T3_QID_DMA_HIGH_PRI_WRITE; + REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE); + } + + dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR; + + /* Writing this DMA descriptor to DMA memory */ + for (i = 0; i < sizeof(T3_DMA_DESC); i += 4) + { + value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i)); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, cpu_to_le32(value32)); + } + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0); + + if (dma_read) + REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr); + else + REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr); + + for (i = 0; i < 40; i++) + { + if (dma_read) + value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue); + else + value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue); + + if ((value32 & 0xffff) == dma_desc_addr) + break; + + MM_Wait(10); + } + + return LM_STATUS_SUCCESS; +} + +STATIC LM_STATUS +LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, + LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize) +{ + int j; + LM_UINT32 *ptr; + int dma_success = 0; + + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + { + return LM_STATUS_SUCCESS; + } + while (!dma_success) + { + /* Fill data with incremental patterns */ + ptr = (LM_UINT32 *)pBufferVirt; + for (j = 0; j < BufferSize/4; j++) + *ptr++ = j; + + if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE) + { + return LM_STATUS_FAILURE; + } + + MM_Wait(40); + ptr = (LM_UINT32 *)pBufferVirt; + /* Fill data with zero */ + for (j = 0; j < BufferSize/4; j++) + *ptr++ = 0; + + if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE) + { + return LM_STATUS_FAILURE; + } + + MM_Wait(40); + /* Check for data */ + ptr = (LM_UINT32 *)pBufferVirt; + for (j = 0; j < BufferSize/4; j++) + { + if (*ptr++ != j) + { + if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK) + == DMA_CTRL_WRITE_BOUNDARY_DISABLE) + { + pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl & + ~DMA_CTRL_WRITE_BOUNDARY_MASK) | + DMA_CTRL_WRITE_BOUNDARY_16; + REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, + pDevice->DmaReadWriteCtrl); + break; + } + else + { + return LM_STATUS_FAILURE; + } + } + } + if (j == (BufferSize/4)) + dma_success = 1; + } + return LM_STATUS_SUCCESS; +} +#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_TIGON3 */ diff --git a/drivers/tigon3.h b/drivers/tigon3.h new file mode 100644 index 000000000..ea4367d61 --- /dev/null +++ b/drivers/tigon3.h @@ -0,0 +1,3430 @@ + +/******************************************************************************/ +/* */ +/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */ +/* Corporation. */ +/* All rights reserved. */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation, located in the file LICENSE. */ +/* */ +/* History: */ +/* */ +/******************************************************************************/ + +#ifndef TIGON3_H +#define TIGON3_H + +#include "bcm570x_lm.h" +#if INCLUDE_TBI_SUPPORT +#include "bcm570x_autoneg.h" +#endif + + +/* io defines */ +#if !defined(BIG_ENDIAN_HOST) +#define readl(addr) \ + (LONGSWAP((*(volatile unsigned int *)(addr)))) +#define writel(b,addr) \ + ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b))) +#else +#if 0 /* !defined(PPC603) */ +#define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr))) +#define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b)) +#else +#if 1 +#define readl(addr) (*(volatile unsigned int*)(addr)) +#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b)) +#else +extern int sprintf(char* buf, const char* f, ...); +static __inline unsigned int readl(void* addr){ + char buf[128]; + unsigned int tmp = (*(volatile unsigned int*)(addr)); + sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0); + sysSerialPrintString(buf); + return tmp; +} +static __inline void writel(unsigned int b, unsigned int addr){ + char buf[128]; + ((*(volatile unsigned int *) (addr)) = (b)); + sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0); + sysSerialPrintString(buf); +} +#endif +#endif /* PPC603 */ +#endif + + +/******************************************************************************/ +/* Constants. */ +/******************************************************************************/ + +/* Maxim number of packet descriptors used for sending packets. */ +#define MAX_TX_PACKET_DESC_COUNT 600 +#define DEFAULT_TX_PACKET_DESC_COUNT 2 + +/* Maximum number of packet descriptors used for receiving packets. */ +#if T3_JUMBO_RCB_ENTRY_COUNT +#define MAX_RX_PACKET_DESC_COUNT \ + (T3_STD_RCV_RCB_ENTRY_COUNT + T3_JUMBO_RCV_RCB_ENTRY_COUNT) +#else +#define MAX_RX_PACKET_DESC_COUNT 800 +#endif +#define DEFAULT_RX_PACKET_DESC_COUNT 2 + +/* Threshhold for double copying small tx packets. 0 will disable double */ +/* copying of small Tx packets. */ +#define DEFAULT_TX_COPY_BUFFER_SIZE 0 +#define MIN_TX_COPY_BUFFER_SIZE 64 +#define MAX_TX_COPY_BUFFER_SIZE 512 + +/* Cache line. */ +#define COMMON_CACHE_LINE_SIZE 0x20 +#define COMMON_CACHE_LINE_MASK (COMMON_CACHE_LINE_SIZE-1) + +/* Maximum number of fragment we can handle. */ +#ifndef MAX_FRAGMENT_COUNT +#define MAX_FRAGMENT_COUNT 32 +#endif + +/* B0 bug. */ +#define BCM5700_BX_MIN_FRAG_SIZE 10 +#define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ +#define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1) +#define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \ + MAX_FRAGMENT_COUNT) + +/* MAGIC number. */ +/* #define T3_MAGIC_NUM 'KevT' */ +#define T3_FIRMWARE_MAILBOX 0x0b50 +#define T3_MAGIC_NUM 0x4B657654 +#define T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b + +#define T3_NIC_DATA_SIG_ADDR 0x0b54 +#define T3_NIC_DATA_SIG 0x4b657654 + +#define T3_NIC_DATA_NIC_CFG_ADDR 0x0b58 +#define T3_NIC_CFG_LED_MODE_UNKNOWN BIT_NONE +#define T3_NIC_CFG_LED_MODE_TRIPLE_SPEED BIT_2 +#define T3_NIC_CFG_LED_MODE_LINK_SPEED BIT_3 +#define T3_NIC_CFG_LED_MODE_OPEN_DRAIN BIT_2 +#define T3_NIC_CFG_LED_MODE_OUTPUT BIT_3 +#define T3_NIC_CFG_LED_MODE_MASK (BIT_2 | BIT_3) +#define T3_NIC_CFG_PHY_TYPE_UNKNOWN BIT_NONE +#define T3_NIC_CFG_PHY_TYPE_COPPER BIT_4 +#define T3_NIC_CFG_PHY_TYPE_FIBER BIT_5 +#define T3_NIC_CFG_PHY_TYPE_MASK (BIT_4 | BIT_5) +#define T3_NIC_CFG_ENABLE_WOL BIT_6 +#define T3_NIC_CFG_ENABLE_ASF BIT_7 +#define T3_NIC_EEPROM_WP BIT_8 + +#define T3_NIC_DATA_PHY_ID_ADDR 0x0b74 +#define T3_NIC_PHY_ID1_MASK 0xffff0000 +#define T3_NIC_PHY_ID2_MASK 0x0000ffff + +#define T3_CMD_MAILBOX 0x0b78 +#define T3_CMD_NICDRV_ALIVE 0x01 +#define T3_CMD_NICDRV_PAUSE_FW 0x02 +#define T3_CMD_NICDRV_IPV4ADDR_CHANGE 0x03 +#define T3_CMD_NICDRV_IPV6ADDR_CHANGE 0x04 +#define T3_CMD_5703A0_FIX_DMAFW_DMAR 0x05 +#define T3_CMD_5703A0_FIX_DMAFW_DMAW 0x06 + +#define T3_CMD_LENGTH_MAILBOX 0x0b7c +#define T3_CMD_DATA_MAILBOX 0x0b80 + +#define T3_ASF_FW_STATUS_MAILBOX 0x0c00 + +#define T3_DRV_STATE_MAILBOX 0x0c04 +#define T3_DRV_STATE_START 0x01 +#define T3_DRV_STATE_UNLOAD 0x02 +#define T3_DRV_STATE_WOL 0x03 +#define T3_DRV_STATE_SUSPEND 0x04 + +#define T3_FW_RESET_TYPE_MAILBOX 0x0c08 + +#define T3_MAC_ADDR_HIGH_MAILBOX 0x0c14 +#define T3_MAC_ADDR_LOW_MAILBOX 0x0c18 + +/******************************************************************************/ +/* Hardware constants. */ +/******************************************************************************/ + +/* Number of entries in the send ring: must be 512. */ +#define T3_SEND_RCB_ENTRY_COUNT 512 +#define T3_SEND_RCB_ENTRY_COUNT_MASK (T3_SEND_RCB_ENTRY_COUNT-1) + +/* Number of send RCBs. May be 1-16 but for now, only support one. */ +#define T3_MAX_SEND_RCB_COUNT 16 + +/* Number of entries in the Standard Receive RCB. Must be 512 entries. */ +#define T3_STD_RCV_RCB_ENTRY_COUNT 512 +#define T3_STD_RCV_RCB_ENTRY_COUNT_MASK (T3_STD_RCV_RCB_ENTRY_COUNT-1) +#define DEFAULT_STD_RCV_DESC_COUNT 200 /* Must be < 512. */ +#define MAX_STD_RCV_BUFFER_SIZE 0x600 + +/* Number of entries in the Mini Receive RCB. This value can either be */ +/* 0, 1024. Currently Mini Receive RCB is disabled. */ +#ifndef T3_MINI_RCV_RCB_ENTRY_COUNT +#define T3_MINI_RCV_RCB_ENTRY_COUNT 0 +#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */ +#define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK (T3_MINI_RCV_RCB_ENTRY_COUNT-1) +#define MAX_MINI_RCV_BUFFER_SIZE 512 +#define DEFAULT_MINI_RCV_BUFFER_SIZE 64 +#define DEFAULT_MINI_RCV_DESC_COUNT 100 /* Must be < 1024. */ + +/* Number of entries in the Jumbo Receive RCB. This value must 256 or 0. */ +/* Currently, Jumbo Receive RCB is disabled. */ +#ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT +#define T3_JUMBO_RCV_RCB_ENTRY_COUNT 0 +#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ +#define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1) + +#define MAX_JUMBO_RCV_BUFFER_SIZE (10 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_RCV_BUFFER_SIZE (4 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_RCV_DESC_COUNT 128 /* Must be < 256. */ + +#define MAX_JUMBO_TX_BUFFER_SIZE (8 * 1024) /* > 1514 */ +#define DEFAULT_JUMBO_TX_BUFFER_SIZE (4 * 1024) /* > 1514 */ + +/* Number of receive return RCBs. Maybe 1-16 but for now, only support one. */ +#define T3_MAX_RCV_RETURN_RCB_COUNT 16 + +/* Number of entries in a Receive Return ring. This value is either 1024 */ +/* or 2048. */ +#ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT +#define T3_RCV_RETURN_RCB_ENTRY_COUNT 1024 +#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */ +#define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK (T3_RCV_RETURN_RCB_ENTRY_COUNT-1) + + +/* Default coalescing parameters. */ +#define DEFAULT_RX_COALESCING_TICKS 100 +#define MAX_RX_COALESCING_TICKS 500 +#define DEFAULT_TX_COALESCING_TICKS 400 +#define MAX_TX_COALESCING_TICKS 500 +#define DEFAULT_RX_MAX_COALESCED_FRAMES 10 +#define MAX_RX_MAX_COALESCED_FRAMES 100 +#define ADAPTIVE_LO_RX_MAX_COALESCED_FRAMES 5 +#define ADAPTIVE_HI_RX_MAX_COALESCED_FRAMES 42 +#define ADAPTIVE_LO_RX_COALESCING_TICKS 50 +#define ADAPTIVE_HI_RX_COALESCING_TICKS 300 +#define ADAPTIVE_LO_PKT_THRESH 30000 +#define ADAPTIVE_HI_PKT_THRESH 74000 +#define DEFAULT_TX_MAX_COALESCED_FRAMES 40 +#define ADAPTIVE_LO_TX_MAX_COALESCED_FRAMES 25 +#define ADAPTIVE_HI_TX_MAX_COALESCED_FRAMES 75 +#define MAX_TX_MAX_COALESCED_FRAMES 100 + +#define DEFAULT_RX_COALESCING_TICKS_DURING_INT 25 +#define DEFAULT_TX_COALESCING_TICKS_DURING_INT 25 +#define DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT 5 +#define DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT 5 + +#define BAD_DEFAULT_VALUE 0xffffffff + +#define DEFAULT_STATS_COALESCING_TICKS 1000000 +#define MAX_STATS_COALESCING_TICKS 3600000000U + + +/* Receive BD Replenish thresholds. */ +#define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD 4 +#define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD 4 + +#define SPLIT_MODE_DISABLE 0 +#define SPLIT_MODE_ENABLE 1 + +#define SPLIT_MODE_5704_MAX_REQ 3 + +/* Maximum physical fragment size. */ +#define MAX_FRAGMENT_SIZE (64 * 1024) + + +/* Standard view. */ +#define T3_STD_VIEW_SIZE (64 * 1024) +#define T3_FLAT_VIEW_SIZE (32 * 1024 * 1024) + + +/* Buffer descriptor base address on the NIC's memory. */ + +#define T3_NIC_SND_BUFFER_DESC_ADDR 0x4000 +#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR 0x6000 +#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR 0x7000 + +#define T3_NIC_STD_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xc000 +#define T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xd000 +#define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000 + +#define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \ + sizeof(T3_SND_BD) / 4) + +#define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \ + sizeof(T3_RCV_BD) / 4) + +#define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \ + sizeof(T3_EXT_RCV_BD) / 4) + + +/* MBUF pool. */ +#define T3_NIC_MBUF_POOL_ADDR 0x8000 +/* #define T3_NIC_MBUF_POOL_SIZE 0x18000 */ +#define T3_NIC_MBUF_POOL_SIZE96 0x18000 +#define T3_NIC_MBUF_POOL_SIZE64 0x10000 + + +#define T3_NIC_MBUF_POOL_ADDR_EXT_MEM 0x20000 + +/* DMA descriptor pool */ +#define T3_NIC_DMA_DESC_POOL_ADDR 0x2000 +#define T3_NIC_DMA_DESC_POOL_SIZE 0x2000 /* 8KB. */ + +#define T3_DEF_DMA_MBUF_LOW_WMARK 0x40 +#define T3_DEF_RX_MAC_MBUF_LOW_WMARK 0x20 +#define T3_DEF_MBUF_HIGH_WMARK 0x60 + +#define T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO 304 +#define T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO 152 +#define T3_DEF_MBUF_HIGH_WMARK_JUMBO 380 + +#define T3_DEF_DMA_DESC_LOW_WMARK 5 +#define T3_DEF_DMA_DESC_HIGH_WMARK 10 + +/* Maximum size of giant TCP packet can be sent */ +#define T3_TCP_SEG_MAX_OFFLOAD_SIZE 64*1000 +#define T3_TCP_SEG_MIN_NUM_SEG 20 + +#define T3_RX_CPU_ID 0x1 +#define T3_TX_CPU_ID 0x2 +#define T3_RX_CPU_SPAD_ADDR 0x30000 +#define T3_RX_CPU_SPAD_SIZE 0x4000 +#define T3_TX_CPU_SPAD_ADDR 0x34000 +#define T3_TX_CPU_SPAD_SIZE 0x4000 + +typedef struct T3_DIR_ENTRY +{ + PLM_UINT8 Buffer; + LM_UINT32 Offset; + LM_UINT32 Length; +} T3_DIR_ENTRY,*PT3_DIR_ENTRY; + +typedef struct T3_FWIMG_INFO +{ + LM_UINT32 StartAddress; + T3_DIR_ENTRY Text; + T3_DIR_ENTRY ROnlyData; + T3_DIR_ENTRY Data; + T3_DIR_ENTRY Sbss; + T3_DIR_ENTRY Bss; +} T3_FWIMG_INFO, *PT3_FWIMG_INFO; + + +/******************************************************************************/ +/* Tigon3 PCI Registers. */ +/******************************************************************************/ +#define T3_PCI_ID_BCM5700 0x164414e4 +#define T3_PCI_ID_BCM5701 0x164514e4 +#define T3_PCI_ID_BCM5702 0x164614e4 +#define T3_PCI_ID_BCM5702x 0x16A614e4 +#define T3_PCI_ID_BCM5703 0x164714e4 +#define T3_PCI_ID_BCM5703x 0x16A714e4 +#define T3_PCI_ID_BCM5702FE 0x164D14e4 +#define T3_PCI_ID_BCM5704 0x164814e4 + +#define T3_PCI_VENDOR_ID (T3_PCI_ID & 0xffff) +#define T3_PCI_DEVICE_ID (T3_PCI_ID >> 16) + +#define T3_PCI_MISC_HOST_CTRL_REG 0x68 + +/* The most significant 16bit of register 0x68. */ +/* ChipId:4, ChipRev:4, MetalRev:8 */ +#define T3_CHIP_ID_5700_A0 0x7000 +#define T3_CHIP_ID_5700_A1 0x7001 +#define T3_CHIP_ID_5700_B0 0x7100 +#define T3_CHIP_ID_5700_B1 0x7101 +#define T3_CHIP_ID_5700_C0 0x7200 + +#define T3_CHIP_ID_5701_A0 0x0000 +#define T3_CHIP_ID_5701_B0 0x0100 +#define T3_CHIP_ID_5701_B2 0x0102 +#define T3_CHIP_ID_5701_B5 0x0105 + +#define T3_CHIP_ID_5703_A0 0x1000 +#define T3_CHIP_ID_5703_A1 0x1001 +#define T3_CHIP_ID_5703_A2 0x1002 + +#define T3_CHIP_ID_5704_A0 0x2000 + +/* Chip Id. */ +#define T3_ASIC_REV(_ChipRevId) ((_ChipRevId) >> 12) +#define T3_ASIC_REV_5700 0x07 +#define T3_ASIC_REV_5701 0x00 +#define T3_ASIC_REV_5703 0x01 +#define T3_ASIC_REV_5704 0x02 + + +/* Chip id and revision. */ +#define T3_CHIP_REV(_ChipRevId) ((_ChipRevId) >> 8) +#define T3_CHIP_REV_5700_AX 0x70 +#define T3_CHIP_REV_5700_BX 0x71 +#define T3_CHIP_REV_5700_CX 0x72 +#define T3_CHIP_REV_5701_AX 0x00 + +/* Metal revision. */ +#define T3_METAL_REV(_ChipRevId) ((_ChipRevId) & 0xff) +#define T3_METAL_REV_A0 0x00 +#define T3_METAL_REV_A1 0x01 +#define T3_METAL_REV_B0 0x00 +#define T3_METAL_REV_B1 0x01 +#define T3_METAL_REV_B2 0x02 + +#define T3_PCI_REG_CLOCK_CTRL 0x74 + +#define T3_PCI_DISABLE_RX_CLOCK BIT_10 +#define T3_PCI_DISABLE_TX_CLOCK BIT_11 +#define T3_PCI_SELECT_ALTERNATE_CLOCK BIT_12 +#define T3_PCI_POWER_DOWN_PCI_PLL133 BIT_15 +#define T3_PCI_44MHZ_CORE_CLOCK BIT_18 + + +#define T3_PCI_REG_ADDR_REG 0x78 +#define T3_PCI_REG_DATA_REG 0x80 + +#define T3_PCI_MEM_WIN_ADDR_REG 0x7c +#define T3_PCI_MEM_WIN_DATA_REG 0x84 + +#define T3_PCI_PM_CAP_REG 0x48 + +#define T3_PCI_PM_CAP_PME_D3COLD BIT_31 +#define T3_PCI_PM_CAP_PME_D3HOT BIT_30 + +#define T3_PCI_PM_STATUS_CTRL_REG 0x4c + +#define T3_PM_POWER_STATE_MASK (BIT_0 | BIT_1) +#define T3_PM_POWER_STATE_D0 BIT_NONE +#define T3_PM_POWER_STATE_D1 BIT_0 +#define T3_PM_POWER_STATE_D2 BIT_1 +#define T3_PM_POWER_STATE_D3 (BIT_0 | BIT_1) + +#define T3_PM_PME_ENABLE BIT_8 +#define T3_PM_PME_ASSERTED BIT_15 + + +/* PCI state register. */ +#define T3_PCI_STATE_REG 0x70 + +#define T3_PCI_STATE_FORCE_RESET BIT_0 +#define T3_PCI_STATE_INT_NOT_ACTIVE BIT_1 +#define T3_PCI_STATE_CONVENTIONAL_PCI_MODE BIT_2 +#define T3_PCI_STATE_BUS_SPEED_HIGH BIT_3 +#define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 + + +/* Broadcom subsystem/subvendor IDs. */ +#define T3_SVID_BROADCOM 0x14e4 + +#define T3_SSID_BROADCOM_BCM95700A6 0x1644 +#define T3_SSID_BROADCOM_BCM95701A5 0x0001 +#define T3_SSID_BROADCOM_BCM95700T6 0x0002 /* BCM8002 */ +#define T3_SSID_BROADCOM_BCM95700A9 0x0003 /* Agilent */ +#define T3_SSID_BROADCOM_BCM95701T1 0x0005 +#define T3_SSID_BROADCOM_BCM95701T8 0x0006 +#define T3_SSID_BROADCOM_BCM95701A7 0x0007 /* Agilent */ +#define T3_SSID_BROADCOM_BCM95701A10 0x0008 +#define T3_SSID_BROADCOM_BCM95701A12 0x8008 +#define T3_SSID_BROADCOM_BCM95703Ax1 0x0009 +#define T3_SSID_BROADCOM_BCM95703Ax2 0x8009 + +/* 3COM subsystem/subvendor IDs. */ +#define T3_SVID_3COM 0x10b7 + +#define T3_SSID_3COM_3C996T 0x1000 +#define T3_SSID_3COM_3C996BT 0x1006 +#define T3_SSID_3COM_3C996CT 0x1002 +#define T3_SSID_3COM_3C997T 0x1003 +#define T3_SSID_3COM_3C1000T 0x1007 +#define T3_SSID_3COM_3C940BR01 0x1008 + +/* Fiber boards. */ +#define T3_SSID_3COM_3C996SX 0x1004 +#define T3_SSID_3COM_3C997SX 0x1005 + + +/* Dell subsystem/subvendor IDs. */ + +#define T3_SVID_DELL 0x1028 + +#define T3_SSID_DELL_VIPER 0x00d1 +#define T3_SSID_DELL_JAGUAR 0x0106 +#define T3_SSID_DELL_MERLOT 0x0109 +#define T3_SSID_DELL_SLIM_MERLOT 0x010a + +/* Compaq subsystem/subvendor IDs */ + +#define T3_SVID_COMPAQ 0x0e11 + +#define T3_SSID_COMPAQ_BANSHEE 0x007c +#define T3_SSID_COMPAQ_BANSHEE_2 0x009a +#define T3_SSID_COMPAQ_CHANGELING 0x007d +#define T3_SSID_COMPAQ_NC7780 0x0085 +#define T3_SSID_COMPAQ_NC7780_2 0x0099 + + +/******************************************************************************/ +/* MII registers. */ +/******************************************************************************/ + +/* Control register. */ +#define PHY_CTRL_REG 0x00 + +#define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13) +#define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE +#define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13 +#define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6 +#define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7 +#define PHY_CTRL_FULL_DUPLEX_MODE BIT_8 +#define PHY_CTRL_RESTART_AUTO_NEG BIT_9 +#define PHY_CTRL_ISOLATE_PHY BIT_10 +#define PHY_CTRL_LOWER_POWER_MODE BIT_11 +#define PHY_CTRL_AUTO_NEG_ENABLE BIT_12 +#define PHY_CTRL_LOOPBACK_MODE BIT_14 +#define PHY_CTRL_PHY_RESET BIT_15 + + +/* Status register. */ +#define PHY_STATUS_REG 0x01 + +#define PHY_STATUS_LINK_PASS BIT_2 +#define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5 + + +/* Phy Id registers. */ +#define PHY_ID1_REG 0x02 +#define PHY_ID1_OUI_MASK 0xffff + +#define PHY_ID2_REG 0x03 +#define PHY_ID2_REV_MASK 0x000f +#define PHY_ID2_MODEL_MASK 0x03f0 +#define PHY_ID2_OUI_MASK 0xfc00 + + +/* Auto-negotiation advertisement register. */ +#define PHY_AN_AD_REG 0x04 + +#define PHY_AN_AD_ASYM_PAUSE BIT_11 +#define PHY_AN_AD_PAUSE_CAPABLE BIT_10 +#define PHY_AN_AD_10BASET_HALF BIT_5 +#define PHY_AN_AD_10BASET_FULL BIT_6 +#define PHY_AN_AD_100BASETX_HALF BIT_7 +#define PHY_AN_AD_100BASETX_FULL BIT_8 +#define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01 + + +/* Auto-negotiation Link Partner Ability register. */ +#define PHY_LINK_PARTNER_ABILITY_REG 0x05 + +#define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11 +#define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10 + + +/* Auto-negotiation expansion register. */ +#define PHY_AN_EXPANSION_REG 0x06 + + +/******************************************************************************/ +/* BCM5400 and BCM5401 phy info. */ +/******************************************************************************/ + +#define PHY_DEVICE_ID 1 + +/* OUI: bit 31-10; Model#: bit 9-4; Rev# bit 3-0. */ +#define PHY_UNKNOWN_PHY 0x00000000 +#define PHY_BCM5400_PHY_ID 0x60008040 +#define PHY_BCM5401_PHY_ID 0x60008050 +#define PHY_BCM5411_PHY_ID 0x60008070 +#define PHY_BCM5701_PHY_ID 0x60008110 +#define PHY_BCM5703_PHY_ID 0x60008160 +#define PHY_BCM5704_PHY_ID 0x60008190 +#define PHY_BCM8002_PHY_ID 0x60010140 + +#define PHY_BCM5401_B0_REV 0x1 +#define PHY_BCM5401_B2_REV 0x3 +#define PHY_BCM5401_C0_REV 0x6 + +#define PHY_ID_OUI_MASK 0xfffffc00 +#define PHY_ID_MODEL_MASK 0x000003f0 +#define PHY_ID_REV_MASK 0x0000000f +#define PHY_ID_MASK (PHY_ID_OUI_MASK | \ + PHY_ID_MODEL_MASK) + + +#define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID)) + + +/* 1000Base-T control register. */ +#define BCM540X_1000BASET_CTRL_REG 0x09 + +#define BCM540X_AN_AD_1000BASET_HALF BIT_8 +#define BCM540X_AN_AD_1000BASET_FULL BIT_9 +#define BCM540X_CONFIG_AS_MASTER BIT_11 +#define BCM540X_ENABLE_CONFIG_AS_MASTER BIT_12 + + +/* Extended control register. */ +#define BCM540X_EXT_CTRL_REG 0x10 + +#define BCM540X_EXT_CTRL_LINK3_LED_MODE BIT_1 +#define BCM540X_EXT_CTRL_TBI BIT_15 + +/* PHY extended status register. */ +#define BCM540X_EXT_STATUS_REG 0x11 + +#define BCM540X_EXT_STATUS_LINK_PASS BIT_8 + + +/* DSP Coefficient Read/Write Port. */ +#define BCM540X_DSP_RW_PORT 0x15 + + +/* DSP Coeficient Address Register. */ +#define BCM540X_DSP_ADDRESS_REG 0x17 + +#define BCM540X_DSP_TAP_NUMBER_MASK 0x00 +#define BCM540X_DSP_AGC_A 0x00 +#define BCM540X_DSP_AGC_B 0x01 +#define BCM540X_DSP_MSE_PAIR_STATUS 0x02 +#define BCM540X_DSP_SOFT_DECISION 0x03 +#define BCM540X_DSP_PHASE_REG 0x04 +#define BCM540X_DSP_SKEW 0x05 +#define BCM540X_DSP_POWER_SAVER_UPPER_BOUND 0x06 +#define BCM540X_DSP_POWER_SAVER_LOWER_BOUND 0x07 +#define BCM540X_DSP_LAST_ECHO 0x08 +#define BCM540X_DSP_FREQUENCY 0x09 +#define BCM540X_DSP_PLL_BANDWIDTH 0x0a +#define BCM540X_DSP_PLL_PHASE_OFFSET 0x0b + +#define BCM540X_DSP_FILTER_DCOFFSET (BIT_10 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT3 (BIT_8 | BIT_9 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT2 (BIT_9 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT1 (BIT_8 | BIT_11) +#define BCM540X_DSP_FILTER_FEXT0 BIT_11 +#define BCM540X_DSP_FILTER_NEXT3 (BIT_8 | BIT_9 | BIT_10) +#define BCM540X_DSP_FILTER_NEXT2 (BIT_9 | BIT_10) +#define BCM540X_DSP_FILTER_NEXT1 (BIT_8 | BIT_10) +#define BCM540X_DSP_FILTER_NEXT0 BIT_10 +#define BCM540X_DSP_FILTER_ECHO (BIT_8 | BIT_9) +#define BCM540X_DSP_FILTER_DFE BIT_9 +#define BCM540X_DSP_FILTER_FFE BIT_8 + +#define BCM540X_DSP_CONTROL_ALL_FILTERS BIT_12 + +#define BCM540X_DSP_SEL_CH_0 BIT_NONE +#define BCM540X_DSP_SEL_CH_1 BIT_13 +#define BCM540X_DSP_SEL_CH_2 BIT_14 +#define BCM540X_DSP_SEL_CH_3 (BIT_13 | BIT_14) + +#define BCM540X_CONTROL_ALL_CHANNELS BIT_15 + + +/* Auxilliary Control Register (Shadow Register) */ +#define BCM5401_AUX_CTRL 0x18 + +#define BCM5401_SHADOW_SEL_MASK 0x7 +#define BCM5401_SHADOW_SEL_NORMAL 0x00 +#define BCM5401_SHADOW_SEL_10BASET 0x01 +#define BCM5401_SHADOW_SEL_POWER_CONTROL 0x02 +#define BCM5401_SHADOW_SEL_IP_PHONE 0x03 +#define BCM5401_SHADOW_SEL_MISC_TEST1 0x04 +#define BCM5401_SHADOW_SEL_MISC_TEST2 0x05 +#define BCM5401_SHADOW_SEL_IP_PHONE_SEED 0x06 + + +/* Shadow register selector == '000' */ +#define BCM5401_SHDW_NORMAL_DIAG_MODE BIT_3 +#define BCM5401_SHDW_NORMAL_DISABLE_MBP BIT_4 +#define BCM5401_SHDW_NORMAL_DISABLE_LOW_PWR BIT_5 +#define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6 +#define BCM5401_SHDW_NORMAL_DISABLE_PRF BIT_7 +#define BCM5401_SHDW_NORMAL_RX_SLICING_NORMAL BIT_NONE +#define BCM5401_SHDW_NORMAL_RX_SLICING_4D BIT_8 +#define BCM5401_SHDW_NORMAL_RX_SLICING_3LVL_1D BIT_9 +#define BCM5401_SHDW_NORMAL_RX_SLICING_5LVL_1D (BIT_8 | BIT_9) +#define BCM5401_SHDW_NORMAL_TX_6DB_CODING BIT_10 +#define BCM5401_SHDW_NORMAL_ENABLE_SM_DSP_CLOCK BIT_11 +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_4NS BIT_NONE +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_5NS BIT_12 +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_3NS BIT_13 +#define BCM5401_SHDW_NORMAL_EDGERATE_CTRL_0NS (BIT_12 | BIT_13) +#define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH BIT_14 +#define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK BIT_15 + + +/* Auxilliary status summary. */ +#define BCM540X_AUX_STATUS_REG 0x19 + +#define BCM540X_AUX_LINK_PASS BIT_2 +#define BCM540X_AUX_SPEED_MASK (BIT_8 | BIT_9 | BIT_10) +#define BCM540X_AUX_10BASET_HD BIT_8 +#define BCM540X_AUX_10BASET_FD BIT_9 +#define BCM540X_AUX_100BASETX_HD (BIT_8 | BIT_9) +#define BCM540X_AUX_100BASET4 BIT_10 +#define BCM540X_AUX_100BASETX_FD (BIT_8 | BIT_10) +#define BCM540X_AUX_100BASET_HD (BIT_9 | BIT_10) +#define BCM540X_AUX_100BASET_FD (BIT_8 | BIT_9 | BIT_10) + + +/* Interrupt status. */ +#define BCM540X_INT_STATUS_REG 0x1a + +#define BCM540X_INT_LINK_CHANGE BIT_1 +#define BCM540X_INT_SPEED_CHANGE BIT_2 +#define BCM540X_INT_DUPLEX_CHANGE BIT_3 +#define BCM540X_INT_AUTO_NEG_PAGE_RX BIT_10 + + +/* Interrupt mask register. */ +#define BCM540X_INT_MASK_REG 0x1b + + +/******************************************************************************/ +/* Register definitions. */ +/******************************************************************************/ + +typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER; +typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER; +typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER; + +typedef struct { + /* Big endian format. */ + T3_32BIT_REGISTER High; + T3_32BIT_REGISTER Low; +} T3_64BIT_REGISTER, *PT3_64BIT_REGISTER; + +typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR; + +#define T3_NUM_OF_DMA_DESC 256 +#define T3_NUM_OF_MBUF 768 + +typedef struct +{ + T3_64BIT_REGISTER host_addr; + T3_32BIT_REGISTER nic_mbuf; + T3_16BIT_REGISTER len; + T3_16BIT_REGISTER cqid_sqid; + T3_32BIT_REGISTER flags; + T3_32BIT_REGISTER opaque1; + T3_32BIT_REGISTER opaque2; + T3_32BIT_REGISTER opaque3; +}T3_DMA_DESC, *PT3_DMA_DESC; + + +/******************************************************************************/ +/* Ring control block. */ +/******************************************************************************/ + +typedef struct { + T3_64BIT_REGISTER HostRingAddr; + + union { + struct { +#ifdef BIG_ENDIAN_HOST + T3_16BIT_REGISTER MaxLen; + T3_16BIT_REGISTER Flags; +#else /* BIG_ENDIAN_HOST */ + T3_16BIT_REGISTER Flags; + T3_16BIT_REGISTER MaxLen; +#endif + } s; + + T3_32BIT_REGISTER MaxLen_Flags; + } u; + + T3_32BIT_REGISTER NicRingAddr; +} T3_RCB, *PT3_RCB; + +#define T3_RCB_FLAG_USE_EXT_RECV_BD BIT_0 +#define T3_RCB_FLAG_RING_DISABLED BIT_1 + + +/******************************************************************************/ +/* Status block. */ +/******************************************************************************/ + +/* + * Size of status block is actually 0x50 bytes. Use 0x80 bytes for + * cache line alignment. + */ +#define T3_STATUS_BLOCK_SIZE 0x80 + +typedef struct { + volatile LM_UINT32 Status; + #define STATUS_BLOCK_UPDATED BIT_0 + #define STATUS_BLOCK_LINK_CHANGED_STATUS BIT_1 + #define STATUS_BLOCK_ERROR BIT_2 + + volatile LM_UINT32 StatusTag; + +#ifdef BIG_ENDIAN_HOST + volatile LM_UINT16 RcvStdConIdx; + volatile LM_UINT16 RcvJumboConIdx; + + volatile LM_UINT16 Reserved2; + volatile LM_UINT16 RcvMiniConIdx; + + struct { + volatile LM_UINT16 SendConIdx; /* Send consumer index. */ + volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ + } Idx[16]; +#else /* BIG_ENDIAN_HOST */ + volatile LM_UINT16 RcvJumboConIdx; + volatile LM_UINT16 RcvStdConIdx; + + volatile LM_UINT16 RcvMiniConIdx; + volatile LM_UINT16 Reserved2; + + struct { + volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ + volatile LM_UINT16 SendConIdx; /* Send consumer index. */ + } Idx[16]; +#endif +} T3_STATUS_BLOCK, *PT3_STATUS_BLOCK; + + +/******************************************************************************/ +/* Receive buffer descriptors. */ +/******************************************************************************/ + +typedef struct { + T3_64BIT_HOST_ADDR HostAddr; + +#ifdef BIG_ENDIAN_HOST + volatile LM_UINT16 Index; + volatile LM_UINT16 Len; + + volatile LM_UINT16 Type; + volatile LM_UINT16 Flags; + + volatile LM_UINT16 IpCksum; + volatile LM_UINT16 TcpUdpCksum; + + volatile LM_UINT16 ErrorFlag; + volatile LM_UINT16 VlanTag; +#else /* BIG_ENDIAN_HOST */ + volatile LM_UINT16 Len; + volatile LM_UINT16 Index; + + volatile LM_UINT16 Flags; + volatile LM_UINT16 Type; + + volatile LM_UINT16 TcpUdpCksum; + volatile LM_UINT16 IpCksum; + + volatile LM_UINT16 VlanTag; + volatile LM_UINT16 ErrorFlag; +#endif + + volatile LM_UINT32 Reserved; + volatile LM_UINT32 Opaque; +} T3_RCV_BD, *PT3_RCV_BD; + + +typedef struct { + T3_64BIT_HOST_ADDR HostAddr[3]; + +#ifdef BIG_ENDIAN_HOST + LM_UINT16 Len1; + LM_UINT16 Len2; + + LM_UINT16 Len3; + LM_UINT16 Reserved1; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 Len2; + LM_UINT16 Len1; + + LM_UINT16 Reserved1; + LM_UINT16 Len3; +#endif + + T3_RCV_BD StdRcvBd; +} T3_EXT_RCV_BD, *PT3_EXT_RCV_BD; + + +/* Error flags. */ +#define RCV_BD_ERR_BAD_CRC 0x0001 +#define RCV_BD_ERR_COLL_DETECT 0x0002 +#define RCV_BD_ERR_LINK_LOST_DURING_PKT 0x0004 +#define RCV_BD_ERR_PHY_DECODE_ERR 0x0008 +#define RCV_BD_ERR_ODD_NIBBLED_RCVD_MII 0x0010 +#define RCV_BD_ERR_MAC_ABORT 0x0020 +#define RCV_BD_ERR_LEN_LT_64 0x0040 +#define RCV_BD_ERR_TRUNC_NO_RESOURCES 0x0080 +#define RCV_BD_ERR_GIANT_FRAME_RCVD 0x0100 + + +/* Buffer descriptor flags. */ +#define RCV_BD_FLAG_END 0x0004 +#define RCV_BD_FLAG_JUMBO_RING 0x0020 +#define RCV_BD_FLAG_VLAN_TAG 0x0040 +#define RCV_BD_FLAG_FRAME_HAS_ERROR 0x0400 +#define RCV_BD_FLAG_MINI_RING 0x0800 +#define RCV_BD_FLAG_IP_CHKSUM_FIELD 0x1000 +#define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD 0x2000 +#define RCV_BD_FLAG_TCP_PACKET 0x4000 + + +/******************************************************************************/ +/* Send buffer descriptor. */ +/******************************************************************************/ + +typedef struct { + T3_64BIT_HOST_ADDR HostAddr; + + union { + struct { +#ifdef BIG_ENDIAN_HOST + LM_UINT16 Len; + LM_UINT16 Flags; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 Flags; + LM_UINT16 Len; +#endif + } s1; + + LM_UINT32 Len_Flags; + } u1; + + union { + struct { +#ifdef BIG_ENDIAN_HOST + LM_UINT16 Reserved; + LM_UINT16 VlanTag; +#else /* BIG_ENDIAN_HOST */ + LM_UINT16 VlanTag; + LM_UINT16 Reserved; +#endif + } s2; + + LM_UINT32 VlanTag; + } u2; +} T3_SND_BD, *PT3_SND_BD; + + +/* Send buffer descriptor flags. */ +#define SND_BD_FLAG_TCP_UDP_CKSUM 0x0001 +#define SND_BD_FLAG_IP_CKSUM 0x0002 +#define SND_BD_FLAG_END 0x0004 +#define SND_BD_FLAG_IP_FRAG 0x0008 +#define SND_BD_FLAG_IP_FRAG_END 0x0010 +#define SND_BD_FLAG_VLAN_TAG 0x0040 +#define SND_BD_FLAG_COAL_NOW 0x0080 +#define SND_BD_FLAG_CPU_PRE_DMA 0x0100 +#define SND_BD_FLAG_CPU_POST_DMA 0x0200 +#define SND_BD_FLAG_INSERT_SRC_ADDR 0x1000 +#define SND_BD_FLAG_CHOOSE_SRC_ADDR 0x6000 +#define SND_BD_FLAG_DONT_GEN_CRC 0x8000 + +/* MBUFs */ +typedef struct T3_MBUF_FRAME_DESC { +#ifdef BIG_ENDIAN_HOST + LM_UINT32 status_control; + union { + struct { + LM_UINT8 cqid; + LM_UINT8 reserved1; + LM_UINT16 length; + }s1; + LM_UINT32 word; + }u1; + union { + struct + { + LM_UINT16 ip_hdr_start; + LM_UINT16 tcp_udp_hdr_start; + }s2; + + LM_UINT32 word; + }u2; + + union { + struct { + LM_UINT16 data_start; + LM_UINT16 vlan_id; + }s3; + + LM_UINT32 word; + }u3; + + union { + struct { + LM_UINT16 ip_checksum; + LM_UINT16 tcp_udp_checksum; + }s4; + + LM_UINT32 word; + }u4; + + union { + struct { + LM_UINT16 pseudo_checksum; + LM_UINT16 checksum_status; + }s5; + + LM_UINT32 word; + }u5; + + union { + struct { + LM_UINT16 rule_match; + LM_UINT8 class; + LM_UINT8 rupt; + }s6; + + LM_UINT32 word; + }u6; + + union { + struct { + LM_UINT16 reserved2; + LM_UINT16 mbuf_num; + }s7; + + LM_UINT32 word; + }u7; + + LM_UINT32 reserved3; + LM_UINT32 reserved4; +#else + LM_UINT32 status_control; + union { + struct { + LM_UINT16 length; + LM_UINT8 reserved1; + LM_UINT8 cqid; + }s1; + LM_UINT32 word; + }u1; + union { + struct + { + LM_UINT16 tcp_udp_hdr_start; + LM_UINT16 ip_hdr_start; + }s2; + + LM_UINT32 word; + }u2; + + union { + struct { + LM_UINT16 vlan_id; + LM_UINT16 data_start; + }s3; + + LM_UINT32 word; + }u3; + + union { + struct { + LM_UINT16 tcp_udp_checksum; + LM_UINT16 ip_checksum; + }s4; + + LM_UINT32 word; + }u4; + + union { + struct { + LM_UINT16 checksum_status; + LM_UINT16 pseudo_checksum; + }s5; + + LM_UINT32 word; + }u5; + + union { + struct { + LM_UINT8 rupt; + LM_UINT8 class; + LM_UINT16 rule_match; + }s6; + + LM_UINT32 word; + }u6; + + union { + struct { + LM_UINT16 mbuf_num; + LM_UINT16 reserved2; + }s7; + + LM_UINT32 word; + }u7; + + LM_UINT32 reserved3; + LM_UINT32 reserved4; +#endif +}T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC; + +typedef struct T3_MBUF_HDR { + union { + struct { + unsigned int C:1; + unsigned int F:1; + unsigned int reserved1:7; + unsigned int next_mbuf:16; + unsigned int length:7; + }s1; + + LM_UINT32 word; + }u1; + + LM_UINT32 next_frame_ptr; +}T3_MBUF_HDR, *PT3_MBUF_HDR; + +typedef struct T3_MBUF +{ + T3_MBUF_HDR hdr; + union + { + struct { + T3_MBUF_FRAME_DESC frame_hdr; + LM_UINT32 data[20]; + }s1; + + struct { + LM_UINT32 data[30]; + }s2; + }body; +}T3_MBUF, *PT3_MBUF; + +#define T3_MBUF_BASE (T3_NIC_MBUF_POOL_ADDR >> 7) +#define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7) + + +/******************************************************************************/ +/* Statistics block. */ +/******************************************************************************/ + +typedef struct { + LM_UINT8 Reserved0[0x400-0x300]; + + /* Statistics maintained by Receive MAC. */ + T3_64BIT_REGISTER ifHCInOctets; + T3_64BIT_REGISTER Reserved1; + T3_64BIT_REGISTER etherStatsFragments; + T3_64BIT_REGISTER ifHCInUcastPkts; + T3_64BIT_REGISTER ifHCInMulticastPkts; + T3_64BIT_REGISTER ifHCInBroadcastPkts; + T3_64BIT_REGISTER dot3StatsFCSErrors; + T3_64BIT_REGISTER dot3StatsAlignmentErrors; + T3_64BIT_REGISTER xonPauseFramesReceived; + T3_64BIT_REGISTER xoffPauseFramesReceived; + T3_64BIT_REGISTER macControlFramesReceived; + T3_64BIT_REGISTER xoffStateEntered; + T3_64BIT_REGISTER dot3StatsFramesTooLong; + T3_64BIT_REGISTER etherStatsJabbers; + T3_64BIT_REGISTER etherStatsUndersizePkts; + T3_64BIT_REGISTER inRangeLengthError; + T3_64BIT_REGISTER outRangeLengthError; + T3_64BIT_REGISTER etherStatsPkts64Octets; + T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets; + T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets; + T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets; + T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets; + T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets; + T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets; + T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets; + T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets; + T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets; + + T3_64BIT_REGISTER Unused1[37]; + + /* Statistics maintained by Transmit MAC. */ + T3_64BIT_REGISTER ifHCOutOctets; + T3_64BIT_REGISTER Reserved2; + T3_64BIT_REGISTER etherStatsCollisions; + T3_64BIT_REGISTER outXonSent; + T3_64BIT_REGISTER outXoffSent; + T3_64BIT_REGISTER flowControlDone; + T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors; + T3_64BIT_REGISTER dot3StatsSingleCollisionFrames; + T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames; + T3_64BIT_REGISTER dot3StatsDeferredTransmissions; + T3_64BIT_REGISTER Reserved3; + T3_64BIT_REGISTER dot3StatsExcessiveCollisions; + T3_64BIT_REGISTER dot3StatsLateCollisions; + T3_64BIT_REGISTER dot3Collided2Times; + T3_64BIT_REGISTER dot3Collided3Times; + T3_64BIT_REGISTER dot3Collided4Times; + T3_64BIT_REGISTER dot3Collided5Times; + T3_64BIT_REGISTER dot3Collided6Times; + T3_64BIT_REGISTER dot3Collided7Times; + T3_64BIT_REGISTER dot3Collided8Times; + T3_64BIT_REGISTER dot3Collided9Times; + T3_64BIT_REGISTER dot3Collided10Times; + T3_64BIT_REGISTER dot3Collided11Times; + T3_64BIT_REGISTER dot3Collided12Times; + T3_64BIT_REGISTER dot3Collided13Times; + T3_64BIT_REGISTER dot3Collided14Times; + T3_64BIT_REGISTER dot3Collided15Times; + T3_64BIT_REGISTER ifHCOutUcastPkts; + T3_64BIT_REGISTER ifHCOutMulticastPkts; + T3_64BIT_REGISTER ifHCOutBroadcastPkts; + T3_64BIT_REGISTER dot3StatsCarrierSenseErrors; + T3_64BIT_REGISTER ifOutDiscards; + T3_64BIT_REGISTER ifOutErrors; + + T3_64BIT_REGISTER Unused2[31]; + + /* Statistics maintained by Receive List Placement. */ + T3_64BIT_REGISTER COSIfHCInPkts[16]; + T3_64BIT_REGISTER COSFramesDroppedDueToFilters; + T3_64BIT_REGISTER nicDmaWriteQueueFull; + T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull; + T3_64BIT_REGISTER nicNoMoreRxBDs; + T3_64BIT_REGISTER ifInDiscards; + T3_64BIT_REGISTER ifInErrors; + T3_64BIT_REGISTER nicRecvThresholdHit; + + T3_64BIT_REGISTER Unused3[9]; + + /* Statistics maintained by Send Data Initiator. */ + T3_64BIT_REGISTER COSIfHCOutPkts[16]; + T3_64BIT_REGISTER nicDmaReadQueueFull; + T3_64BIT_REGISTER nicDmaReadHighPriQueueFull; + T3_64BIT_REGISTER nicSendDataCompQueueFull; + + /* Statistics maintained by Host Coalescing. */ + T3_64BIT_REGISTER nicRingSetSendProdIndex; + T3_64BIT_REGISTER nicRingStatusUpdate; + T3_64BIT_REGISTER nicInterrupts; + T3_64BIT_REGISTER nicAvoidedInterrupts; + T3_64BIT_REGISTER nicSendThresholdHit; + + LM_UINT8 Reserved4[0xb00-0x9c0]; +} T3_STATS_BLOCK, *PT3_STATS_BLOCK; + + +/******************************************************************************/ +/* PCI configuration registers. */ +/******************************************************************************/ + +typedef struct { + T3_16BIT_REGISTER VendorId; + T3_16BIT_REGISTER DeviceId; + + T3_16BIT_REGISTER Command; + T3_16BIT_REGISTER Status; + + T3_32BIT_REGISTER ClassCodeRevId; + + T3_8BIT_REGISTER CacheLineSize; + T3_8BIT_REGISTER LatencyTimer; + T3_8BIT_REGISTER HeaderType; + T3_8BIT_REGISTER Bist; + + T3_32BIT_REGISTER MemBaseAddrLow; + T3_32BIT_REGISTER MemBaseAddrHigh; + + LM_UINT8 Unused1[20]; + + T3_16BIT_REGISTER SubsystemVendorId; + T3_16BIT_REGISTER SubsystemId; + + T3_32BIT_REGISTER RomBaseAddr; + + T3_8BIT_REGISTER PciXCapiblityPtr; + LM_UINT8 Unused2[7]; + + T3_8BIT_REGISTER IntLine; + T3_8BIT_REGISTER IntPin; + T3_8BIT_REGISTER MinGnt; + T3_8BIT_REGISTER MaxLat; + + T3_8BIT_REGISTER PciXCapabilities; + T3_8BIT_REGISTER PmCapabilityPtr; + T3_16BIT_REGISTER PciXCommand; + + T3_32BIT_REGISTER PciXStatus; + + T3_8BIT_REGISTER PmCapabilityId; + T3_8BIT_REGISTER VpdCapabilityPtr; + T3_16BIT_REGISTER PmCapabilities; + + T3_16BIT_REGISTER PmCtrlStatus; + #define PM_CTRL_PME_STATUS BIT_15 + #define PM_CTRL_PME_ENABLE BIT_8 + #define PM_CTRL_PME_POWER_STATE_D0 0 + #define PM_CTRL_PME_POWER_STATE_D1 1 + #define PM_CTRL_PME_POWER_STATE_D2 2 + #define PM_CTRL_PME_POWER_STATE_D3H 3 + + T3_8BIT_REGISTER BridgeSupportExt; + T3_8BIT_REGISTER PmData; + + T3_8BIT_REGISTER VpdCapabilityId; + T3_8BIT_REGISTER MsiCapabilityPtr; + T3_16BIT_REGISTER VpdAddrFlag; + #define VPD_FLAG_WRITE (1 << 15) + #define VPD_FLAG_RW_MASK (1 << 15) + #define VPD_FLAG_READ 0 + + + T3_32BIT_REGISTER VpdData; + + T3_8BIT_REGISTER MsiCapabilityId; + T3_8BIT_REGISTER NextCapabilityPtr; + T3_16BIT_REGISTER MsiCtrl; + #define MSI_CTRL_64BIT_CAP (1 << 7) + #define MSI_CTRL_MSG_ENABLE(x) (x << 4) + #define MSI_CTRL_MSG_CAP(x) (x << 1) + #define MSI_CTRL_ENABLE (1 << 0) + + + T3_32BIT_REGISTER MsiAddrLow; + T3_32BIT_REGISTER MsiAddrHigh; + + T3_16BIT_REGISTER MsiData; + T3_16BIT_REGISTER Unused3; + + T3_32BIT_REGISTER MiscHostCtrl; + #define MISC_HOST_CTRL_CLEAR_INT BIT_0 + #define MISC_HOST_CTRL_MASK_PCI_INT BIT_1 + #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP BIT_2 + #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP BIT_3 + #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW BIT_4 + #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW BIT_5 + #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP BIT_6 + #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS BIT_7 + #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE BIT_8 + #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE BIT_9 + + T3_32BIT_REGISTER DmaReadWriteCtrl; + #define DMA_CTRL_WRITE_BOUNDARY_MASK (BIT_11 | BIT_12 | BIT_13) + #define DMA_CTRL_WRITE_BOUNDARY_DISABLE 0 + #define DMA_CTRL_WRITE_BOUNDARY_16 BIT_11 + #define DMA_CTRL_WRITE_BOUNDARY_32 BIT_12 + #define DMA_CTRL_WRITE_BOUNDARY_64 (BIT_12 | BIT_11) + #define DMA_CTRL_WRITE_BOUNDARY_128 BIT_13 + #define DMA_CTRL_WRITE_BOUNDARY_256 (BIT_13 | BIT_11) + #define DMA_CTRL_WRITE_BOUNDARY_512 (BIT_13 | BIT_12) + #define DMA_CTRL_WRITE_BOUNDARY_1024 (BIT_13 | BIT_12 | BIT_11) + #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE BIT_14 + + + T3_32BIT_REGISTER PciState; + #define T3_PCI_STATE_FORCE_PCI_RESET BIT_0 + #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE BIT_1 + #define T3_PCI_STATE_NOT_PCI_X_BUS BIT_2 + #define T3_PCI_STATE_HIGH_BUS_SPEED BIT_3 + #define T3_PCI_STATE_32BIT_PCI_BUS BIT_4 + #define T3_PCI_STATE_PCI_ROM_ENABLE BIT_5 + #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE BIT_6 + #define T3_PCI_STATE_FLAT_VIEW BIT_8 + #define T3_PCI_STATE_RETRY_SAME_DMA BIT_13 + + T3_32BIT_REGISTER ClockCtrl; + #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE BIT_11 + #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE BIT_10 + #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE BIT_9 + + T3_32BIT_REGISTER RegBaseAddr; + + T3_32BIT_REGISTER MemWindowBaseAddr; + +#ifdef NIC_CPU_VIEW + /* These registers are ONLY visible to NIC CPU */ + T3_32BIT_REGISTER PowerConsumed; + T3_32BIT_REGISTER PowerDissipated; +#else /* NIC_CPU_VIEW */ + T3_32BIT_REGISTER RegData; + T3_32BIT_REGISTER MemWindowData; +#endif /* !NIC_CPU_VIEW */ + + T3_32BIT_REGISTER ModeCtrl; + + T3_32BIT_REGISTER MiscCfg; + + T3_32BIT_REGISTER MiscLocalCtrl; + + T3_32BIT_REGISTER Unused4; + + /* NOTE: Big/Little-endian clarification needed. Are these register */ + /* in big or little endian formate. */ + T3_64BIT_REGISTER StdRingProdIdx; + T3_64BIT_REGISTER RcvRetRingConIdx; + T3_64BIT_REGISTER SndProdIdx; + + LM_UINT8 Unused5[80]; +} T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION; + +#define PCIX_CMD_MAX_SPLIT_MASK 0x0070 +#define PCIX_CMD_MAX_SPLIT_SHL 4 +#define PCIX_CMD_MAX_BURST_MASK 0x000c +#define PCIX_CMD_MAX_BURST_SHL 2 +#define PCIX_CMD_MAX_BURST_CPIOB 2 + +/******************************************************************************/ +/* Mac control registers. */ +/******************************************************************************/ + +typedef struct { + /* MAC mode control. */ + T3_32BIT_REGISTER Mode; + #define MAC_MODE_GLOBAL_RESET BIT_0 + #define MAC_MODE_HALF_DUPLEX BIT_1 + #define MAC_MODE_PORT_MODE_MASK (BIT_2 | BIT_3) + #define MAC_MODE_PORT_MODE_TBI (BIT_2 | BIT_3) + #define MAC_MODE_PORT_MODE_GMII BIT_3 + #define MAC_MODE_PORT_MODE_MII BIT_2 + #define MAC_MODE_PORT_MODE_NONE BIT_NONE + #define MAC_MODE_PORT_INTERNAL_LOOPBACK BIT_4 + #define MAC_MODE_TAGGED_MAC_CONTROL BIT_7 + #define MAC_MODE_TX_BURSTING BIT_8 + #define MAC_MODE_MAX_DEFER BIT_9 + #define MAC_MODE_LINK_POLARITY BIT_10 + #define MAC_MODE_ENABLE_RX_STATISTICS BIT_11 + #define MAC_MODE_CLEAR_RX_STATISTICS BIT_12 + #define MAC_MODE_FLUSH_RX_STATISTICS BIT_13 + #define MAC_MODE_ENABLE_TX_STATISTICS BIT_14 + #define MAC_MODE_CLEAR_TX_STATISTICS BIT_15 + #define MAC_MODE_FLUSH_TX_STATISTICS BIT_16 + #define MAC_MODE_SEND_CONFIGS BIT_17 + #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE BIT_18 + #define MAC_MODE_ACPI_POWER_ON_ENABLE BIT_19 + #define MAC_MODE_ENABLE_MIP BIT_20 + #define MAC_MODE_ENABLE_TDE BIT_21 + #define MAC_MODE_ENABLE_RDE BIT_22 + #define MAC_MODE_ENABLE_FHDE BIT_23 + + /* MAC status */ + T3_32BIT_REGISTER Status; + #define MAC_STATUS_PCS_SYNCED BIT_0 + #define MAC_STATUS_SIGNAL_DETECTED BIT_1 + #define MAC_STATUS_RECEIVING_CFG BIT_2 + #define MAC_STATUS_CFG_CHANGED BIT_3 + #define MAC_STATUS_SYNC_CHANGED BIT_4 + #define MAC_STATUS_PORT_DECODE_ERROR BIT_10 + #define MAC_STATUS_LINK_STATE_CHANGED BIT_12 + #define MAC_STATUS_MI_COMPLETION BIT_22 + #define MAC_STATUS_MI_INTERRUPT BIT_23 + #define MAC_STATUS_AP_ERROR BIT_24 + #define MAC_STATUS_ODI_ERROR BIT_25 + #define MAC_STATUS_RX_STATS_OVERRUN BIT_26 + #define MAC_STATUS_TX_STATS_OVERRUN BIT_27 + + /* Event Enable */ + T3_32BIT_REGISTER MacEvent; + #define MAC_EVENT_ENABLE_PORT_DECODE_ERR BIT_10 + #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN BIT_12 + #define MAC_EVENT_ENABLE_MI_COMPLETION BIT_22 + #define MAC_EVENT_ENABLE_MI_INTERRUPT BIT_23 + #define MAC_EVENT_ENABLE_AP_ERROR BIT_24 + #define MAC_EVENT_ENABLE_ODI_ERROR BIT_25 + #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN BIT_26 + #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN BIT_27 + + /* Led control. */ + T3_32BIT_REGISTER LedCtrl; + #define LED_CTRL_OVERRIDE_LINK_LED BIT_0 + #define LED_CTRL_1000MBPS_LED_ON BIT_1 + #define LED_CTRL_100MBPS_LED_ON BIT_2 + #define LED_CTRL_10MBPS_LED_ON BIT_3 + #define LED_CTRL_OVERRIDE_TRAFFIC_LED BIT_4 + #define LED_CTRL_BLINK_TRAFFIC_LED BIT_5 + #define LED_CTRL_TRAFFIC_LED BIT_6 + #define LED_CTRL_1000MBPS_LED_STATUS BIT_7 + #define LED_CTRL_100MBPS_LED_STATUS BIT_8 + #define LED_CTRL_10MBPS_LED_STATUS BIT_9 + #define LED_CTRL_TRAFFIC_LED_STATUS BIT_10 + #define LED_CTRL_MAC_MODE BIT_NONE + #define LED_CTRL_PHY_MODE_1 BIT_11 + #define LED_CTRL_PHY_MODE_2 BIT_12 + #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 + #define LED_CTRL_OVERRIDE_BLINK_PERIOD BIT_19 + #define LED_CTRL_OVERRIDE_BLINK_RATE BIT_31 + + /* MAC addresses. */ + struct { + T3_32BIT_REGISTER High; /* Upper 2 bytes. */ + T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ + } MacAddr[4]; + + /* ACPI Mbuf pointer. */ + T3_32BIT_REGISTER AcpiMbufPtr; + + /* ACPI Length and Offset. */ + T3_32BIT_REGISTER AcpiLengthOffset; + #define ACPI_LENGTH_MASK 0xffff + #define ACPI_OFFSET_MASK 0x0fff0000 + #define ACPI_LENGTH(x) x + #define ACPI_OFFSET(x) ((x) << 16) + + /* Transmit random backoff. */ + T3_32BIT_REGISTER TxBackoffSeed; + #define MAC_TX_BACKOFF_SEED_MASK 0x3ff + + /* Receive MTU */ + T3_32BIT_REGISTER MtuSize; + #define MAC_RX_MTU_MASK 0xffff + + /* Gigabit PCS Test. */ + T3_32BIT_REGISTER PcsTest; + #define MAC_PCS_TEST_DATA_PATTERN_MASK 0x0fffff + #define MAC_PCS_TEST_ENABLE BIT_20 + + /* Transmit Gigabit Auto-Negotiation. */ + T3_32BIT_REGISTER TxAutoNeg; + #define MAC_AN_TX_AN_DATA_MASK 0xffff + + /* Receive Gigabit Auto-Negotiation. */ + T3_32BIT_REGISTER RxAutoNeg; + #define MAC_AN_RX_AN_DATA_MASK 0xffff + + /* MI Communication. */ + T3_32BIT_REGISTER MiCom; + #define MI_COM_CMD_MASK (BIT_26 | BIT_27) + #define MI_COM_CMD_WRITE BIT_26 + #define MI_COM_CMD_READ BIT_27 + #define MI_COM_READ_FAILED BIT_28 + #define MI_COM_START BIT_29 + #define MI_COM_BUSY BIT_29 + + #define MI_COM_PHY_ADDR_MASK 0x1f + #define MI_COM_FIRST_PHY_ADDR_BIT 21 + + #define MI_COM_PHY_REG_ADDR_MASK 0x1f + #define MI_COM_FIRST_PHY_REG_ADDR_BIT 16 + + #define MI_COM_PHY_DATA_MASK 0xffff + + /* MI Status. */ + T3_32BIT_REGISTER MiStatus; + #define MI_STATUS_ENABLE_LINK_STATUS_ATTN BIT_0 + + /* MI Mode. */ + T3_32BIT_REGISTER MiMode; + #define MI_MODE_CLOCK_SPEED_10MHZ BIT_0 + #define MI_MODE_USE_SHORT_PREAMBLE BIT_1 + #define MI_MODE_AUTO_POLLING_ENABLE BIT_4 + #define MI_MODE_CORE_CLOCK_SPEED_62MHZ BIT_15 + + /* Auto-polling status. */ + T3_32BIT_REGISTER AutoPollStatus; + #define AUTO_POLL_ERROR BIT_0 + + /* Transmit MAC mode. */ + T3_32BIT_REGISTER TxMode; + #define TX_MODE_RESET BIT_0 + #define TX_MODE_ENABLE BIT_1 + #define TX_MODE_ENABLE_FLOW_CONTROL BIT_4 + #define TX_MODE_ENABLE_BIG_BACKOFF BIT_5 + #define TX_MODE_ENABLE_LONG_PAUSE BIT_6 + + /* Transmit MAC status. */ + T3_32BIT_REGISTER TxStatus; + #define TX_STATUS_RX_CURRENTLY_XOFFED BIT_0 + #define TX_STATUS_SENT_XOFF BIT_1 + #define TX_STATUS_SENT_XON BIT_2 + #define TX_STATUS_LINK_UP BIT_3 + #define TX_STATUS_ODI_UNDERRUN BIT_4 + #define TX_STATUS_ODI_OVERRUN BIT_5 + + /* Transmit MAC length. */ + T3_32BIT_REGISTER TxLengths; + #define TX_LEN_SLOT_TIME_MASK 0xff + #define TX_LEN_IPG_MASK 0x0f00 + #define TX_LEN_IPG_CRS_MASK (BIT_12 | BIT_13) + + /* Receive MAC mode. */ + T3_32BIT_REGISTER RxMode; + #define RX_MODE_RESET BIT_0 + #define RX_MODE_ENABLE BIT_1 + #define RX_MODE_ENABLE_FLOW_CONTROL BIT_2 + #define RX_MODE_KEEP_MAC_CONTROL BIT_3 + #define RX_MODE_KEEP_PAUSE BIT_4 + #define RX_MODE_ACCEPT_OVERSIZED BIT_5 + #define RX_MODE_ACCEPT_RUNTS BIT_6 + #define RX_MODE_LENGTH_CHECK BIT_7 + #define RX_MODE_PROMISCUOUS_MODE BIT_8 + #define RX_MODE_NO_CRC_CHECK BIT_9 + #define RX_MODE_KEEP_VLAN_TAG BIT_10 + + /* Receive MAC status. */ + T3_32BIT_REGISTER RxStatus; + #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED BIT_0 + #define RX_STATUS_XOFF_RECEIVED BIT_1 + #define RX_STATUS_XON_RECEIVED BIT_2 + + /* Hash registers. */ + T3_32BIT_REGISTER HashReg[4]; + + /* Receive placement rules registers. */ + struct { + T3_32BIT_REGISTER Rule; + T3_32BIT_REGISTER Value; + } RcvRules[16]; + + #define RCV_DISABLE_RULE_MASK 0x7fffffff + + #define RCV_RULE1_REJECT_BROADCAST_IDX 0x00 + #define REJECT_BROADCAST_RULE1_RULE 0xc2000000 + #define REJECT_BROADCAST_RULE1_VALUE 0xffffffff + + #define RCV_RULE2_REJECT_BROADCAST_IDX 0x01 + #define REJECT_BROADCAST_RULE2_RULE 0x86000004 + #define REJECT_BROADCAST_RULE2_VALUE 0xffffffff + +#if INCLUDE_5701_AX_FIX + #define RCV_LAST_RULE_IDX 0x04 +#else + #define RCV_LAST_RULE_IDX 0x02 +#endif + + T3_32BIT_REGISTER RcvRuleCfg; + #define RX_RULE_DEFAULT_CLASS (1 << 3) + + LM_UINT8 Reserved1[140]; + + T3_32BIT_REGISTER SerdesCfg; + T3_32BIT_REGISTER SerdesStatus; + + LM_UINT8 Reserved2[104]; + + volatile LM_UINT8 TxMacState[16]; + volatile LM_UINT8 RxMacState[20]; + + LM_UINT8 Reserved3[476]; + + T3_32BIT_REGISTER RxStats[26]; + + LM_UINT8 Reserved4[24]; + + T3_32BIT_REGISTER TxStats[28]; + + LM_UINT8 Reserved5[784]; +} T3_MAC_CONTROL, *PT3_MAC_CONTROL; + + +/******************************************************************************/ +/* Send data initiator control registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define T3_SND_DATA_IN_MODE_RESET BIT_0 + #define T3_SND_DATA_IN_MODE_ENABLE BIT_1 + #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN BIT_2 + + T3_32BIT_REGISTER StatsCtrl; + #define T3_SND_DATA_IN_STATS_CTRL_ENABLE BIT_0 + #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE BIT_1 + #define T3_SND_DATA_IN_STATS_CTRL_CLEAR BIT_2 + #define T3_SND_DATA_IN_STATS_CTRL_FLUSH BIT_3 + #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO BIT_4 + + T3_32BIT_REGISTER StatsEnableMask; + T3_32BIT_REGISTER StatsIncMask; + + LM_UINT8 Reserved[108]; + + T3_32BIT_REGISTER ClassOfServCnt[16]; + T3_32BIT_REGISTER DmaReadQFullCnt; + T3_32BIT_REGISTER DmaPriorityReadQFullCnt; + T3_32BIT_REGISTER SdcQFullCnt; + + T3_32BIT_REGISTER NicRingSetSendProdIdxCnt; + T3_32BIT_REGISTER StatusUpdatedCnt; + T3_32BIT_REGISTER InterruptsCnt; + T3_32BIT_REGISTER AvoidInterruptsCnt; + T3_32BIT_REGISTER SendThresholdHitCnt; + + /* Unused space. */ + LM_UINT8 Unused[800]; +} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR; + + +/******************************************************************************/ +/* Send data completion control registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define SND_DATA_COMP_MODE_RESET BIT_0 + #define SND_DATA_COMP_MODE_ENABLE BIT_1 + + /* Unused space. */ + LM_UINT8 Unused[1020]; +} T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION; + + +/******************************************************************************/ +/* Send BD Ring Selector Control Registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define SND_BD_SEL_MODE_RESET BIT_0 + #define SND_BD_SEL_MODE_ENABLE BIT_1 + #define SND_BD_SEL_MODE_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define SND_BD_SEL_STATUS_ERROR_ATTN BIT_2 + + T3_32BIT_REGISTER HwDiag; + + /* Unused space. */ + LM_UINT8 Unused1[52]; + + /* Send BD Ring Selector Local NIC Send BD Consumer Index. */ + T3_32BIT_REGISTER NicSendBdSelConIdx[16]; + + /* Unused space. */ + LM_UINT8 Unused2[896]; +} T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR; + + +/******************************************************************************/ +/* Send BD initiator control registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define SND_BD_IN_MODE_RESET BIT_0 + #define SND_BD_IN_MODE_ENABLE BIT_1 + #define SND_BD_IN_MODE_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define SND_BD_IN_STATUS_ERROR_ATTN BIT_2 + + /* Send BD initiator local NIC send BD producer index. */ + T3_32BIT_REGISTER NicSendBdInProdIdx[16]; + + /* Unused space. */ + LM_UINT8 Unused2[952]; +} T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR; + + +/******************************************************************************/ +/* Send BD Completion Control. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define SND_BD_COMP_MODE_RESET BIT_0 + #define SND_BD_COMP_MODE_ENABLE BIT_1 + #define SND_BD_COMP_MODE_ATTN_ENABLE BIT_2 + + /* Unused space. */ + LM_UINT8 Unused2[1020]; +} T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION; + + +/******************************************************************************/ +/* Receive list placement control registers. */ +/******************************************************************************/ + +typedef struct { + /* Mode. */ + T3_32BIT_REGISTER Mode; + #define RCV_LIST_PLMT_MODE_RESET BIT_0 + #define RCV_LIST_PLMT_MODE_ENABLE BIT_1 + #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE BIT_2 + #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE BIT_3 + #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE BIT_4 + + /* Status. */ + T3_32BIT_REGISTER Status; + #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN BIT_2 + #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN BIT_3 + #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN BIT_4 + + /* Receive selector list lock register. */ + T3_32BIT_REGISTER Lock; + #define RCV_LIST_SEL_LOCK_REQUEST_MASK 0xffff + #define RCV_LIST_SEL_LOCK_GRANT_MASK 0xffff0000 + + /* Selector non-empty bits. */ + T3_32BIT_REGISTER NonEmptyBits; + #define RCV_LIST_SEL_NON_EMPTY_MASK 0xffff + + /* Receive list placement configuration register. */ + T3_32BIT_REGISTER Config; + + /* Receive List Placement statistics Control. */ + T3_32BIT_REGISTER StatsCtrl; +#define RCV_LIST_STATS_ENABLE BIT_0 +#define RCV_LIST_STATS_FAST_UPDATE BIT_1 + + /* Receive List Placement statistics Enable Mask. */ + T3_32BIT_REGISTER StatsEnableMask; + + /* Receive List Placement statistics Increment Mask. */ + T3_32BIT_REGISTER StatsIncMask; + + /* Unused space. */ + LM_UINT8 Unused1[224]; + + struct { + T3_32BIT_REGISTER Head; + T3_32BIT_REGISTER Tail; + T3_32BIT_REGISTER Count; + + /* Unused space. */ + LM_UINT8 Unused[4]; + } RcvSelectorList[16]; + + /* Local statistics counter. */ + T3_32BIT_REGISTER ClassOfServCnt[16]; + + T3_32BIT_REGISTER DropDueToFilterCnt; + T3_32BIT_REGISTER DmaWriteQFullCnt; + T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt; + T3_32BIT_REGISTER NoMoreReceiveBdCnt; + T3_32BIT_REGISTER IfInDiscardsCnt; + T3_32BIT_REGISTER IfInErrorsCnt; + T3_32BIT_REGISTER RcvThresholdHitCnt; + + /* Another unused space. */ + LM_UINT8 Unused2[420]; +} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT; + + +/******************************************************************************/ +/* Receive Data and Receive BD Initiator Control. */ +/******************************************************************************/ + +typedef struct { + /* Mode. */ + T3_32BIT_REGISTER Mode; + #define RCV_DATA_BD_IN_MODE_RESET BIT_0 + #define RCV_DATA_BD_IN_MODE_ENABLE BIT_1 + #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED BIT_2 + #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG BIT_3 + #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE BIT_4 + + /* Status. */ + T3_32BIT_REGISTER Status; + #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED BIT_2 + #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG BIT_3 + #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE BIT_4 + + /* Split frame minium size. */ + T3_32BIT_REGISTER SplitFrameMinSize; + + /* Unused space. */ + LM_UINT8 Unused1[0x2440-0x240c]; + + /* Receive RCBs. */ + T3_RCB JumboRcvRcb; + T3_RCB StdRcvRcb; + T3_RCB MiniRcvRcb; + + /* Receive Data and Receive BD Ring Initiator Local NIC Receive */ + /* BD Consumber Index. */ + T3_32BIT_REGISTER NicJumboConIdx; + T3_32BIT_REGISTER NicStdConIdx; + T3_32BIT_REGISTER NicMiniConIdx; + + /* Unused space. */ + LM_UINT8 Unused2[4]; + + /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */ + T3_32BIT_REGISTER RcvDataBdProdIdx[16]; + + /* Receive Data and Receive BD Initiator Hardware Diagnostic. */ + T3_32BIT_REGISTER HwDiag; + + /* Unused space. */ + LM_UINT8 Unused3[828]; +} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR; + + +/******************************************************************************/ +/* Receive Data Completion Control Registes. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define RCV_DATA_COMP_MODE_RESET BIT_0 + #define RCV_DATA_COMP_MODE_ENABLE BIT_1 + #define RCV_DATA_COMP_MODE_ATTN_ENABLE BIT_2 + + /* Unused spaced. */ + LM_UINT8 Unused[1020]; +} T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION; + + +/******************************************************************************/ +/* Receive BD Initiator Control. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define RCV_BD_IN_MODE_RESET BIT_0 + #define RCV_BD_IN_MODE_ENABLE BIT_1 + #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN BIT_2 + + T3_32BIT_REGISTER NicJumboRcvProdIdx; + T3_32BIT_REGISTER NicStdRcvProdIdx; + T3_32BIT_REGISTER NicMiniRcvProdIdx; + + T3_32BIT_REGISTER MiniRcvThreshold; + T3_32BIT_REGISTER StdRcvThreshold; + T3_32BIT_REGISTER JumboRcvThreshold; + + /* Unused space. */ + LM_UINT8 Unused[992]; +} T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR; + + +/******************************************************************************/ +/* Receive BD Completion Control Registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define RCV_BD_COMP_MODE_RESET BIT_0 + #define RCV_BD_COMP_MODE_ENABLE BIT_1 + #define RCV_BD_COMP_MODE_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define RCV_BD_COMP_STATUS_ERROR_ATTN BIT_2 + + T3_32BIT_REGISTER NicJumboRcvBdProdIdx; + T3_32BIT_REGISTER NicStdRcvBdProdIdx; + T3_32BIT_REGISTER NicMiniRcvBdProdIdx; + + /* Unused space. */ + LM_UINT8 Unused[1004]; +} T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION; + + +/******************************************************************************/ +/* Receive list selector control register. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define RCV_LIST_SEL_MODE_RESET BIT_0 + #define RCV_LIST_SEL_MODE_ENABLE BIT_1 + #define RCV_LIST_SEL_MODE_ATTN_ENABLE BIT_2 + + T3_32BIT_REGISTER Status; + #define RCV_LIST_SEL_STATUS_ERROR_ATTN BIT_2 + + /* Unused space. */ + LM_UINT8 Unused[1016]; +} T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR; + + +/******************************************************************************/ +/* Mbuf cluster free registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; +#define MBUF_CLUSTER_FREE_MODE_RESET BIT_0 +#define MBUF_CLUSTER_FREE_MODE_ENABLE BIT_1 + + T3_32BIT_REGISTER Status; + + /* Unused space. */ + LM_UINT8 Unused[1016]; +} T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE; + + +/******************************************************************************/ +/* Host coalescing control registers. */ +/******************************************************************************/ + +typedef struct { + /* Mode. */ + T3_32BIT_REGISTER Mode; + #define HOST_COALESCE_RESET BIT_0 + #define HOST_COALESCE_ENABLE BIT_1 + #define HOST_COALESCE_ATTN BIT_2 + #define HOST_COALESCE_NOW BIT_3 + #define HOST_COALESCE_FULL_STATUS_MODE BIT_NONE + #define HOST_COALESCE_64_BYTE_STATUS_MODE BIT_7 + #define HOST_COALESCE_32_BYTE_STATUS_MODE BIT_8 + #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT BIT_9 + #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT BIT_10 + #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE BIT_11 + #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE BIT_12 + + /* Status. */ + T3_32BIT_REGISTER Status; + #define HOST_COALESCE_ERROR_ATTN BIT_2 + + /* Receive coalescing ticks. */ + T3_32BIT_REGISTER RxCoalescingTicks; + + /* Send coalescing ticks. */ + T3_32BIT_REGISTER TxCoalescingTicks; + + /* Receive max coalesced frames. */ + T3_32BIT_REGISTER RxMaxCoalescedFrames; + + /* Send max coalesced frames. */ + T3_32BIT_REGISTER TxMaxCoalescedFrames; + + /* Receive coalescing ticks during interrupt. */ + T3_32BIT_REGISTER RxCoalescedTickDuringInt; + + /* Send coalescing ticks during interrupt. */ + T3_32BIT_REGISTER TxCoalescedTickDuringInt; + + /* Receive max coalesced frames during interrupt. */ + T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt; + + /* Send max coalesced frames during interrupt. */ + T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt; + + /* Statistics tick. */ + T3_32BIT_REGISTER StatsCoalescingTicks; + + /* Unused space. */ + LM_UINT8 Unused2[4]; + + /* Statistics host address. */ + T3_64BIT_REGISTER StatsBlkHostAddr; + + /* Status block host address.*/ + T3_64BIT_REGISTER StatusBlkHostAddr; + + /* Statistics NIC address. */ + T3_32BIT_REGISTER StatsBlkNicAddr; + + /* Statust block NIC address. */ + T3_32BIT_REGISTER StatusBlkNicAddr; + + /* Flow attention registers. */ + T3_32BIT_REGISTER FlowAttn; + + /* Unused space. */ + LM_UINT8 Unused3[4]; + + T3_32BIT_REGISTER NicJumboRcvBdConIdx; + T3_32BIT_REGISTER NicStdRcvBdConIdx; + T3_32BIT_REGISTER NicMiniRcvBdConIdx; + + /* Unused space. */ + LM_UINT8 Unused4[36]; + + T3_32BIT_REGISTER NicRetProdIdx[16]; + T3_32BIT_REGISTER NicSndBdConIdx[16]; + + /* Unused space. */ + LM_UINT8 Unused5[768]; +} T3_HOST_COALESCING, *PT3_HOST_COALESCING; + + +/******************************************************************************/ +/* Memory arbiter registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; +#define T3_MEM_ARBITER_MODE_RESET BIT_0 +#define T3_MEM_ARBITER_MODE_ENABLE BIT_1 + + T3_32BIT_REGISTER Status; + + T3_32BIT_REGISTER ArbTrapAddrLow; + T3_32BIT_REGISTER ArbTrapAddrHigh; + + /* Unused space. */ + LM_UINT8 Unused[1008]; +} T3_MEM_ARBITER, *PT3_MEM_ARBITER; + + +/******************************************************************************/ +/* Buffer manager control register. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define BUFMGR_MODE_RESET BIT_0 + #define BUFMGR_MODE_ENABLE BIT_1 + #define BUFMGR_MODE_ATTN_ENABLE BIT_2 + #define BUFMGR_MODE_BM_TEST BIT_3 + #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE BIT_4 + + T3_32BIT_REGISTER Status; + #define BUFMGR_STATUS_ERROR BIT_2 + #define BUFMGR_STATUS_MBUF_LOW BIT_4 + + T3_32BIT_REGISTER MbufPoolAddr; + T3_32BIT_REGISTER MbufPoolSize; + T3_32BIT_REGISTER MbufReadDmaLowWaterMark; + T3_32BIT_REGISTER MbufMacRxLowWaterMark; + T3_32BIT_REGISTER MbufHighWaterMark; + + T3_32BIT_REGISTER RxCpuMbufAllocReq; + #define BUFMGR_MBUF_ALLOC_BIT BIT_31 + T3_32BIT_REGISTER RxCpuMbufAllocResp; + T3_32BIT_REGISTER TxCpuMbufAllocReq; + T3_32BIT_REGISTER TxCpuMbufAllocResp; + + T3_32BIT_REGISTER DmaDescPoolAddr; + T3_32BIT_REGISTER DmaDescPoolSize; + T3_32BIT_REGISTER DmaLowWaterMark; + T3_32BIT_REGISTER DmaHighWaterMark; + + T3_32BIT_REGISTER RxCpuDmaAllocReq; + T3_32BIT_REGISTER RxCpuDmaAllocResp; + T3_32BIT_REGISTER TxCpuDmaAllocReq; + T3_32BIT_REGISTER TxCpuDmaAllocResp; + + T3_32BIT_REGISTER Hwdiag[3]; + + /* Unused space. */ + LM_UINT8 Unused[936]; +} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER; + + +/******************************************************************************/ +/* Read DMA control registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define DMA_READ_MODE_RESET BIT_0 + #define DMA_READ_MODE_ENABLE BIT_1 + #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 + #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 + #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 + #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 + #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 + #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 + #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 + #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE BIT_9 + #define DMA_READ_MODE_SPLIT_ENABLE BIT_11 + #define DMA_READ_MODE_SPLIT_RESET BIT_12 + + T3_32BIT_REGISTER Status; + #define DMA_READ_STATUS_TARGET_ABORT_ATTN BIT_2 + #define DMA_READ_STATUS_MASTER_ABORT_ATTN BIT_3 + #define DMA_READ_STATUS_PARITY_ERROR_ATTN BIT_4 + #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN BIT_5 + #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN BIT_6 + #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN BIT_7 + #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN BIT_8 + #define DMA_READ_STATUS_LONG_READ_ATTN BIT_9 + + /* Unused space. */ + LM_UINT8 Unused[1016]; +} T3_DMA_READ, *PT3_DMA_READ; + +typedef union T3_CPU +{ + struct + { + T3_32BIT_REGISTER mode; + #define CPU_MODE_HALT BIT_10 + #define CPU_MODE_RESET BIT_0 + T3_32BIT_REGISTER state; + T3_32BIT_REGISTER EventMask; + T3_32BIT_REGISTER reserved1[4]; + T3_32BIT_REGISTER PC; + T3_32BIT_REGISTER Instruction; + T3_32BIT_REGISTER SpadUnderflow; + T3_32BIT_REGISTER WatchdogClear; + T3_32BIT_REGISTER WatchdogVector; + T3_32BIT_REGISTER WatchdogSavedPC; + T3_32BIT_REGISTER HardwareBp; + T3_32BIT_REGISTER reserved2[3]; + T3_32BIT_REGISTER WatchdogSavedState; + T3_32BIT_REGISTER LastBrchAddr; + T3_32BIT_REGISTER SpadUnderflowSet; + T3_32BIT_REGISTER reserved3[(0x200-0x50)/4]; + T3_32BIT_REGISTER Regs[32]; + T3_32BIT_REGISTER reserved4[(0x400-0x280)/4]; + }reg; +}T3_CPU, *PT3_CPU; + +/******************************************************************************/ +/* Write DMA control registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define DMA_WRITE_MODE_RESET BIT_0 + #define DMA_WRITE_MODE_ENABLE BIT_1 + #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE BIT_2 + #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE BIT_3 + #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE BIT_4 + #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE BIT_5 + #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE BIT_6 + #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE BIT_7 + #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE BIT_8 + #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE BIT_9 + + T3_32BIT_REGISTER Status; + #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN BIT_2 + #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN BIT_3 + #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN BIT_4 + #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN BIT_5 + #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN BIT_6 + #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN BIT_7 + #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN BIT_8 + #define DMA_WRITE_STATUS_LONG_READ_ATTN BIT_9 + + /* Unused space. */ + LM_UINT8 Unused[1016]; +} T3_DMA_WRITE, *PT3_DMA_WRITE; + + +/******************************************************************************/ +/* Mailbox registers. */ +/******************************************************************************/ + +typedef struct { + /* Interrupt mailbox registers. */ + T3_64BIT_REGISTER Interrupt[4]; + + /* General mailbox registers. */ + T3_64BIT_REGISTER General[8]; + + /* Reload statistics mailbox. */ + T3_64BIT_REGISTER ReloadStat; + + /* Receive BD ring producer index registers. */ + T3_64BIT_REGISTER RcvStdProdIdx; + T3_64BIT_REGISTER RcvJumboProdIdx; + T3_64BIT_REGISTER RcvMiniProdIdx; + + /* Receive return ring consumer index registers. */ + T3_64BIT_REGISTER RcvRetConIdx[16]; + + /* Send BD ring host producer index registers. */ + T3_64BIT_REGISTER SendHostProdIdx[16]; + + /* Send BD ring nic producer index registers. */ + T3_64BIT_REGISTER SendNicProdIdx[16]; +}T3_MAILBOX, *PT3_MAILBOX; + +typedef struct { + T3_MAILBOX Mailbox; + + /* Priority mailbox registers. */ + T3_32BIT_REGISTER HighPriorityEventVector; + T3_32BIT_REGISTER HighPriorityEventMask; + T3_32BIT_REGISTER LowPriorityEventVector; + T3_32BIT_REGISTER LowPriorityEventMask; + + /* Unused space. */ + LM_UINT8 Unused[496]; +} T3_GRC_MAILBOX, *PT3_GRC_MAILBOX; + + +/******************************************************************************/ +/* Flow through queues. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Reset; + + LM_UINT8 Unused[12]; + + T3_32BIT_REGISTER DmaNormalReadFtqCtrl; + T3_32BIT_REGISTER DmaNormalReadFtqFullCnt; + T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaHighReadFtqCtrl; + T3_32BIT_REGISTER DmaHighReadFtqFullCnt; + T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaCompDiscardFtqCtrl; + T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt; + T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek; + + T3_32BIT_REGISTER SendBdCompFtqCtrl; + T3_32BIT_REGISTER SendBdCompFtqFullCnt; + T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek; + + T3_32BIT_REGISTER SendDataInitiatorFtqCtrl; + T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt; + T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaNormalWriteFtqCtrl; + T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt; + T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek; + + T3_32BIT_REGISTER DmaHighWriteFtqCtrl; + T3_32BIT_REGISTER DmaHighWriteFtqFullCnt; + T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek; + + T3_32BIT_REGISTER SwType1FtqCtrl; + T3_32BIT_REGISTER SwType1FtqFullCnt; + T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SwType1FtqFifoWritePeek; + + T3_32BIT_REGISTER SendDataCompFtqCtrl; + T3_32BIT_REGISTER SendDataCompFtqFullCnt; + T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek; + + T3_32BIT_REGISTER HostCoalesceFtqCtrl; + T3_32BIT_REGISTER HostCoalesceFtqFullCnt; + T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek; + + T3_32BIT_REGISTER MacTxFtqCtrl; + T3_32BIT_REGISTER MacTxFtqFullCnt; + T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER MacTxFtqFifoWritePeek; + + T3_32BIT_REGISTER MbufClustFreeFtqCtrl; + T3_32BIT_REGISTER MbufClustFreeFtqFullCnt; + T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvBdCompFtqCtrl; + T3_32BIT_REGISTER RcvBdCompFtqFullCnt; + T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvListPlmtFtqCtrl; + T3_32BIT_REGISTER RcvListPlmtFtqFullCnt; + T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek; + + T3_32BIT_REGISTER RcvDataCompFtqCtrl; + T3_32BIT_REGISTER RcvDataCompFtqFullCnt; + T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue; + T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek; + + T3_32BIT_REGISTER SwType2FtqCtrl; + T3_32BIT_REGISTER SwType2FtqFullCnt; + T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue; + T3_32BIT_REGISTER SwType2FtqFifoWritePeek; + + /* Unused space. */ + LM_UINT8 Unused2[736]; +} T3_FTQ, *PT3_FTQ; + + +/******************************************************************************/ +/* Message signaled interrupt registers. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; +#define MSI_MODE_RESET BIT_0 +#define MSI_MODE_ENABLE BIT_1 + T3_32BIT_REGISTER Status; + + T3_32BIT_REGISTER MsiFifoAccess; + + /* Unused space. */ + LM_UINT8 Unused[1012]; +} T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT; + + +/******************************************************************************/ +/* DMA Completion registes. */ +/******************************************************************************/ + +typedef struct { + T3_32BIT_REGISTER Mode; + #define DMA_COMP_MODE_RESET BIT_0 + #define DMA_COMP_MODE_ENABLE BIT_1 + + /* Unused space. */ + LM_UINT8 Unused[1020]; +} T3_DMA_COMPLETION, *PT3_DMA_COMPLETION; + + +/******************************************************************************/ +/* GRC registers. */ +/******************************************************************************/ + +typedef struct { + /* Mode control register. */ + T3_32BIT_REGISTER Mode; + #define GRC_MODE_UPDATE_ON_COALESCING BIT_0 + #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA BIT_1 + #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA BIT_2 + #define GRC_MODE_BYTE_SWAP_DATA BIT_4 + #define GRC_MODE_WORD_SWAP_DATA BIT_5 + #define GRC_MODE_SPLIT_HEADER_MODE BIT_8 + #define GRC_MODE_NO_FRAME_CRACKING BIT_9 + #define GRC_MODE_INCLUDE_CRC BIT_10 + #define GRC_MODE_ALLOW_BAD_FRAMES BIT_11 + #define GRC_MODE_NO_INTERRUPT_ON_SENDS BIT_13 + #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE BIT_14 + #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE BIT_15 + #define GRC_MODE_HOST_STACK_UP BIT_16 + #define GRC_MODE_HOST_SEND_BDS BIT_17 + #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM BIT_20 + #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM BIT_23 + #define GRC_MODE_INT_ON_TX_CPU_ATTN BIT_24 + #define GRC_MODE_INT_ON_RX_CPU_ATTN BIT_25 + #define GRC_MODE_INT_ON_MAC_ATTN BIT_26 + #define GRC_MODE_INT_ON_DMA_ATTN BIT_27 + #define GRC_MODE_INT_ON_FLOW_ATTN BIT_28 + #define GRC_MODE_4X_NIC_BASED_SEND_RINGS BIT_29 + #define GRC_MODE_MULTICAST_FRAME_ENABLE BIT_30 + + /* Misc configuration register. */ + T3_32BIT_REGISTER MiscCfg; + #define GRC_MISC_CFG_CORE_CLOCK_RESET BIT_0 + #define GRC_MISC_PRESCALAR_TIMER_MASK 0xfe + #define GRC_MISC_BD_ID_MASK 0x0001e000 + #define GRC_MISC_BD_ID_5700 0x0001e000 + #define GRC_MISC_BD_ID_5701 0x00000000 + #define GRC_MISC_BD_ID_5703 0x00000000 + #define GRC_MISC_BD_ID_5703S 0x00002000 + #define GRC_MISC_BD_ID_5702FE 0x00004000 + #define GRC_MISC_BD_ID_5704 0x00000000 + #define GRC_MISC_BD_ID_5704CIOBE 0x00004000 + + /* Miscellaneous local control register. */ + T3_32BIT_REGISTER LocalCtrl; + #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE BIT_0 + #define GRC_MISC_LOCAL_CTRL_CLEAR_INT BIT_1 + #define GRC_MISC_LOCAL_CTRL_SET_INT BIT_2 + #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN BIT_3 + #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0 BIT_8 + #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1 BIT_9 + #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2 BIT_10 + #define GRC_MISC_LOCAL_CTRL_GPIO_OE0 BIT_11 + #define GRC_MISC_LOCAL_CTRL_GPIO_OE1 BIT_12 + #define GRC_MISC_LOCAL_CTRL_GPIO_OE2 BIT_13 + #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 BIT_14 + #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 BIT_15 + #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2 BIT_16 + #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY BIT_17 + #define GRC_MISC_LOCAL_CTRL_BANK_SELECT BIT_21 + #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE BIT_22 + + #define GRC_MISC_MEMSIZE_256K 0 + #define GRC_MISC_MEMSIZE_512K (1 << 18) + #define GRC_MISC_MEMSIZE_1024K (2 << 18) + #define GRC_MISC_MEMSIZE_2048K (3 << 18) + #define GRC_MISC_MEMSIZE_4096K (4 << 18) + #define GRC_MISC_MEMSIZE_8192K (5 << 18) + #define GRC_MISC_MEMSIZE_16M (6 << 18) + #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM BIT_24 + + + T3_32BIT_REGISTER Timer; + + T3_32BIT_REGISTER RxCpuEvent; + T3_32BIT_REGISTER RxTimerRef; + T3_32BIT_REGISTER RxCpuSemaphore; + T3_32BIT_REGISTER RemoteRxCpuAttn; + + T3_32BIT_REGISTER TxCpuEvent; + T3_32BIT_REGISTER TxTimerRef; + T3_32BIT_REGISTER TxCpuSemaphore; + T3_32BIT_REGISTER RemoteTxCpuAttn; + + T3_64BIT_REGISTER MemoryPowerUp; + + T3_32BIT_REGISTER EepromAddr; + #define SEEPROM_ADDR_WRITE 0 + #define SEEPROM_ADDR_READ (1 << 31) + #define SEEPROM_ADDR_RW_MASK 0x80000000 + #define SEEPROM_ADDR_COMPLETE (1 << 30) + #define SEEPROM_ADDR_FSM_RESET (1 << 29) + #define SEEPROM_ADDR_DEV_ID(x) (x << 26) + #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000 + #define SEEPROM_ADDR_START (1 << 25) + #define SEEPROM_ADDR_CLK_PERD(x) (x << 16) + #define SEEPROM_ADDR_ADDRESS(x) (x & 0xfffc) + #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff + + #define SEEPROM_CLOCK_PERIOD 60 + #define SEEPROM_CHIP_SIZE (64 * 1024) + + T3_32BIT_REGISTER EepromData; + T3_32BIT_REGISTER EepromCtrl; + + T3_32BIT_REGISTER MdiCtrl; + T3_32BIT_REGISTER SepromDelay; + + /* Unused space. */ + LM_UINT8 Unused[948]; +} T3_GRC, *PT3_GRC; + + +/******************************************************************************/ +/* NVRAM control registers. */ +/******************************************************************************/ + +typedef struct +{ + T3_32BIT_REGISTER Cmd; + #define NVRAM_CMD_RESET BIT_0 + #define NVRAM_CMD_DONE BIT_3 + #define NVRAM_CMD_DO_IT BIT_4 + #define NVRAM_CMD_WR BIT_5 + #define NVRAM_CMD_RD BIT_NONE + #define NVRAM_CMD_ERASE BIT_6 + #define NVRAM_CMD_FIRST BIT_7 + #define NVRAM_CMD_LAST BIT_8 + + T3_32BIT_REGISTER Status; + T3_32BIT_REGISTER WriteData; + + T3_32BIT_REGISTER Addr; + #define NVRAM_ADDRESS_MASK 0xffffff + + T3_32BIT_REGISTER ReadData; + + /* Flash config 1 register. */ + T3_32BIT_REGISTER Config1; + #define FLASH_INTERFACE_ENABLE BIT_0 + #define FLASH_SSRAM_BUFFERRED_MODE BIT_1 + #define FLASH_PASS_THRU_MODE BIT_2 + #define FLASH_BIT_BANG_MODE BIT_3 + #define FLASH_COMPAT_BYPASS BIT_31 + + /* Buffered flash (Atmel: AT45DB011B) specific information */ + #define BUFFERED_FLASH_PAGE_POS 9 + #define BUFFERED_FLASH_BYTE_ADDR_MASK ((1<pMemView->OffsetName)) + +#define REG_WR(pDevice, OffsetName, Value32) \ + (((OFFSETOF(T3_STD_MEM_MAP, OffsetName) >=0x200 ) && \ + (OFFSETOF(T3_STD_MEM_MAP, OffsetName) <0x400)) || \ + ((pDevice)->EnablePciXFix == FALSE)) ? \ + (void) writel(Value32, &((pDevice)->pMemView->OffsetName)) : \ + LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32) + +#define MB_REG_RD(pDevice, OffsetName) \ + readl(&((pDevice)->pMemView->OffsetName)) + +#define MB_REG_WR(pDevice, OffsetName, Value32) \ + writel(Value32, &((pDevice)->pMemView->OffsetName)) + +#define REG_RD_OFFSET(pDevice, Offset) \ + readl(&((LM_UINT8 *) (pDevice)->pMemView + Offset)) + +#define REG_WR_OFFSET(pDevice, Offset, Value32) \ + (((Offset >=0x200 ) && (Offset < 0x400)) || \ + ((pDevice)->EnablePciXFix == FALSE)) ? \ + (void) writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) : \ + LM_RegWrInd(pDevice, Offset, Value32) + +#define MEM_RD(pDevice, AddrName) \ + LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) +#define MEM_WR(pDevice, AddrName, Value32) \ + LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) + +#define MEM_RD_OFFSET(pDevice, Offset) \ + LM_MemRdInd(pDevice, Offset) +#define MEM_WR_OFFSET(pDevice, Offset, Value32) \ + LM_MemWrInd(pDevice, Offset, Value32) + +#else /* normal target access path below */ + +/* Register access. */ +#define REG_RD(pDevice, OffsetName) \ + readl(&((pDevice)->pMemView->OffsetName)) +#define REG_WR(pDevice, OffsetName, Value32) \ + writel(Value32, &((pDevice)->pMemView->OffsetName)) + +#define REG_RD_OFFSET(pDevice, Offset) \ + readl(((LM_UINT8 *) (pDevice)->pMemView + Offset)) +#define REG_WR_OFFSET(pDevice, Offset, Value32) \ + writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) + + +/* There could be problem access the memory window directly. For now, */ +/* we have to go through the PCI configuration register. */ +#define MEM_RD(pDevice, AddrName) \ + LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) +#define MEM_WR(pDevice, AddrName, Value32) \ + LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) + +#define MEM_RD_OFFSET(pDevice, Offset) \ + LM_MemRdInd(pDevice, Offset) +#define MEM_WR_OFFSET(pDevice, Offset, Value32) \ + LM_MemWrInd(pDevice, Offset, Value32) + +#endif /* PCIX_TARGET_WORKAROUND */ + +#endif /* Jimmy, merging */ + + /* Jimmy...rest of file is new stuff! */ +/******************************************************************************/ +/* NIC register read/write macros. */ +/******************************************************************************/ + +/* MAC register access. */ +LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register); +LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, + LM_UINT32 Value32); + +/* MAC memory access. */ +LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr); +LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, + LM_UINT32 Value32); + +#define MB_REG_WR(pDevice, OffsetName, Value32) \ + ((pDevice)->UndiFix) ? \ + LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \ + Value32) : \ + (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) + +#define MB_REG_RD(pDevice, OffsetName) \ + (((pDevice)->UndiFix) ? \ + LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \ + __raw_readl(&((pDevice)->pMemView->OffsetName))) + +#define REG_RD(pDevice, OffsetName) \ + (((pDevice)->UndiFix) ? \ + LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) : \ + __raw_readl(&((pDevice)->pMemView->OffsetName))) + +#if PCIX_TARGET_WORKAROUND + +#define REG_WR(pDevice, OffsetName, Value32) \ + ((pDevice)->EnablePciXFix == FALSE) ? \ + (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) : \ + LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName), Value32) + +#else + +#define REG_WR(pDevice, OffsetName, Value32) \ + __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) + +#endif + +#define MEM_RD(pDevice, AddrName) \ + LM_MemRdInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName)) +#define MEM_WR(pDevice, AddrName, Value32) \ + LM_MemWrInd(pDevice, OFFSETOF(T3_FIRST_32K_SRAM, AddrName), Value32) + +#define MEM_RD_OFFSET(pDevice, Offset) \ + LM_MemRdInd(pDevice, Offset) +#define MEM_WR_OFFSET(pDevice, Offset, Value32) \ + LM_MemWrInd(pDevice, Offset, Value32) + +#endif /* TIGON3_H */ diff --git a/drivers/tqm8xx_pcmcia.c b/drivers/tqm8xx_pcmcia.c new file mode 100644 index 000000000..a0f53cd68 --- /dev/null +++ b/drivers/tqm8xx_pcmcia.c @@ -0,0 +1,330 @@ +/* -------------------------------------------------------------------- */ +/* TQM8xxL Boards by TQ Components */ +/* SC8xx Boards by SinoVee Microsystems */ +/* -------------------------------------------------------------------- */ +#include +#ifdef CONFIG_8xx +#include +#endif +#include + +#undef CONFIG_PCMCIA + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +#define CONFIG_PCMCIA +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) +#define CONFIG_PCMCIA +#endif + +#if defined(CONFIG_PCMCIA) \ + && (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)) + +#if defined(CONFIG_VIRTLAB2) +#define PCMCIA_BOARD_MSG "Virtlab2" +#elif defined(CONFIG_TQM8xxL) +#define PCMCIA_BOARD_MSG "TQM8xxL" +#elif defined(CONFIG_SVM_SC8xx) +#define PCMCIA_BOARD_MSG "SC8xx" +#endif + +#if defined(CONFIG_NSCU) + +#define power_config(slot) do {} while (0) +#define power_off(slot) do {} while (0) +#define power_on_5_0(slot) do {} while (0) +#define power_on_3_3(slot) do {} while (0) + +#elif defined(CONFIG_HMI10) + +static inline void power_config(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + /* + * Configure Port B pins for + * 5 Volts Enable and 3 Volts enable + */ + immap->im_cpm.cp_pbpar &= ~(0x00000300); +} + +static inline void power_off(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + /* remove all power */ + immap->im_cpm.cp_pbdat |= 0x00000300; +} + +static inline void power_on_5_0(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + immap->im_cpm.cp_pbdat &= ~(0x0000100); + immap->im_cpm.cp_pbdir |= 0x00000300; +} + +static inline void power_on_3_3(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + immap->im_cpm.cp_pbdat &= ~(0x0000200); + immap->im_cpm.cp_pbdir |= 0x00000300; +} + +#elif defined(CONFIG_VIRTLAB2) + +#define power_config(slot) do {} while (0) +static inline void power_off(int slot) +{ + volatile unsigned char *powerctl = + (volatile unsigned char *)PCMCIA_CTRL; + *powerctl = 0; +} + +static inline void power_on_5_0(int slot) +{ + volatile unsigned char *powerctl = + (volatile unsigned char *)PCMCIA_CTRL; + *powerctl = 2; /* Enable 5V Vccout */ +} + +static inline void power_on_3_3(int slot) +{ + volatile unsigned char *powerctl = + (volatile unsigned char *)PCMCIA_CTRL; + *powerctl = 1; /* Enable 3.3V Vccout */ +} + +#else + +static inline void power_config(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + /* + * Configure Port C pins for + * 5 Volts Enable and 3 Volts enable + */ + immap->im_ioport.iop_pcpar &= ~(0x0002 | 0x0004); + immap->im_ioport.iop_pcso &= ~(0x0002 | 0x0004); +} + +static inline void power_off(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + immap->im_ioport.iop_pcdat &= ~(0x0002 | 0x0004); +} + +static inline void power_on_5_0(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + immap->im_ioport.iop_pcdat |= 0x0004; + immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004); +} + +static inline void power_on_3_3(int slot) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + immap->im_ioport.iop_pcdat |= 0x0002; + immap->im_ioport.iop_pcdir |= (0x0002 | 0x0004); +} + +#endif + +#ifdef CONFIG_HMI10 +static inline int check_card_is_absent(int slot) +{ + volatile pcmconf8xx_t *pcmp = + (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + return pcmp->pcmc_pipr & (0x10000000 >> (slot << 4)); +} +#else +static inline int check_card_is_absent(int slot) +{ + volatile pcmconf8xx_t *pcmp = + (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + return pcmp->pcmc_pipr & (0x18000000 >> (slot << 4)); +} +#endif + +#ifdef NSCU_OE_INV +#define NSCU_GCRX_CXOE 0 +#else +#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE +#endif + +int pcmcia_hardware_enable(int slot) +{ + volatile pcmconf8xx_t *pcmp = + (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + volatile sysconf8xx_t *sysp = + (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); + uint reg, mask; + + debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + udelay(10000); + + /* + * Configure SIUMCR to enable PCMCIA port B + * (VFLS[0:1] are not used for debugging, we connect FRZ# instead) + */ + sysp->sc_siumcr &= ~SIUMCR_DBGC11; /* set DBGC to 00 */ + + /* clear interrupt state, and disable interrupts */ + pcmp->pcmc_pscr = PCMCIA_MASK(slot); + pcmp->pcmc_per &= ~PCMCIA_MASK(slot); + + /* + * Disable interrupts, DMA, and PCMCIA buffers + * (isolate the interface) and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= NSCU_GCRX_CXOE; + + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + power_config(slot); + power_off(slot); + + /* + * Make sure there is a card in the slot, then configure the interface. + */ + udelay(10000); + debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__, + &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); + + if (check_card_is_absent(slot)) { + printf (" No Card found\n"); + return (1); + } + + /* + * Power On. + */ + mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot); + reg = pcmp->pcmc_pipr; + debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", + reg, + (reg&PCMCIA_VS1(slot))?"n":"ff", + (reg&PCMCIA_VS2(slot))?"n":"ff"); + + if ((reg & mask) == mask) { + power_on_5_0(slot); + puts (" 5.0V card found: "); + } else { + power_on_3_3(slot); + puts (" 3.3V card found: "); + } + +#if 0 + /* VCC switch error flag, PCMCIA slot INPACK_ pin */ + cp->cp_pbdir &= ~(0x0020 | 0x0010); + cp->cp_pbpar &= ~(0x0020 | 0x0010); + udelay(500000); +#endif + + udelay(1000); + debug ("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + reg &= ~NSCU_GCRX_CXOE; + + PCMCIA_PGCRX(slot) = reg; + + udelay(250000); /* some cards need >150 ms to come up :-( */ + + debug ("# hardware_enable done\n"); + + return (0); +} + + +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) +int pcmcia_hardware_disable(int slot) +{ + u_long reg; + + debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); + + + /* remove all power */ + power_off(slot); + + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = 0; + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= NSCU_GCRX_CXOE; /* active low */ + + PCMCIA_PGCRX(slot) = reg; + + udelay(10000); + + return (0); +} +#endif /* CFG_CMD_PCMCIA */ + +int pcmcia_voltage_set(int slot, int vcc, int vpp) +{ +#ifndef CONFIG_NSCU + u_long reg; +# ifdef DEBUG + volatile pcmconf8xx_t *pcmp = + (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); +# endif + + debug ("voltage_set: " PCMCIA_BOARD_MSG + " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", + 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); + + /* + * Disable PCMCIA buffers (isolate the interface) + * and assert RESET signal + */ + debug ("Disable PCMCIA buffers and assert RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */ + reg |= NSCU_GCRX_CXOE; /* active low */ + + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug ("PCMCIA power OFF\n"); + power_config(slot); + power_off(slot); + + switch(vcc) { + case 0: break; + case 33: power_on_3_3(slot); break; + case 50: power_on_5_0(slot); break; + default: goto done; + } + + /* Checking supported voltages */ + + debug("PIPR: 0x%x --> %s\n", pcmp->pcmc_pipr, + (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); + + if (vcc) + debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3"); + else + debug("PCMCIA powered down\n"); + +done: + debug("Enable PCMCIA buffers and stop RESET\n"); + reg = PCMCIA_PGCRX(slot); + reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */ + reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */ + reg &= ~NSCU_GCRX_CXOE; /* active low */ + + PCMCIA_PGCRX(slot) = reg; + udelay(500); + + debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A'); +#endif /* CONFIG_NSCU */ + return (0); +} + +#endif /* CONFIG_PCMCIA && (CONFIG_TQM8xxL || CONFIG_SVM_SC8xx) */ diff --git a/drivers/tsec.c b/drivers/tsec.c new file mode 100644 index 000000000..7ec565ca6 --- /dev/null +++ b/drivers/tsec.c @@ -0,0 +1,1185 @@ +/* + * tsec.c + * Freescale Three Speed Ethernet Controller driver + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003, Motorola, Inc. + * author Andy Fleming + * + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_TSEC_ENET) +#include "tsec.h" +#include "miiphy.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define TX_BUF_CNT 2 + +static uint rxIdx; /* index of the current RX buffer */ +static uint txIdx; /* index of the current TX buffer */ + +typedef volatile struct rtxbd { + txbd8_t txbd[TX_BUF_CNT]; + rxbd8_t rxbd[PKTBUFSRX]; +} RTXBD; + +struct tsec_info_struct { + unsigned int phyaddr; + u32 flags; + unsigned int phyregidx; +}; + + +/* The tsec_info structure contains 3 values which the + * driver uses to determine how to operate a given ethernet + * device. For now, the structure is initialized with the + * knowledge that all current implementations have 2 TSEC + * devices, and one FEC. The information needed is: + * phyaddr - The address of the PHY which is attached to + * the given device. + * + * flags - This variable indicates whether the device + * supports gigabit speed ethernet, and whether it should be + * in reduced mode. + * + * phyregidx - This variable specifies which ethernet device + * controls the MII Management registers which are connected + * to the PHY. For 8540/8560, only TSEC1 (index 0) has + * access to the PHYs, so all of the entries have "0". + * + * The values specified in the table are taken from the board's + * config file in include/configs/. When implementing a new + * board with ethernet capability, it is necessary to define: + * TSEC1_PHY_ADDR + * TSEC1_PHYIDX + * TSEC2_PHY_ADDR + * TSEC2_PHYIDX + * + * and for 8560: + * FEC_PHY_ADDR + * FEC_PHYIDX + */ +static struct tsec_info_struct tsec_info[] = { +#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1) + {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, +#else + { 0, 0, 0}, +#endif +#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2) + {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, +#else + { 0, 0, 0}, +#endif +#ifdef CONFIG_MPC85XX_FEC + {FEC_PHY_ADDR, 0, FEC_PHYIDX}, +#else +# if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) + {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, +# else + { 0, 0, 0}, +# endif +# if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) + {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX}, +# else + { 0, 0, 0}, +# endif +#endif +}; + +#define MAXCONTROLLERS (4) + +static int relocated = 0; + +static struct tsec_private *privlist[MAXCONTROLLERS]; + +#ifdef __GNUC__ +static RTXBD rtx __attribute__ ((aligned(8))); +#else +#error "rtx must be 64-bit aligned" +#endif + +static int tsec_send(struct eth_device* dev, volatile void *packet, int length); +static int tsec_recv(struct eth_device* dev); +static int tsec_init(struct eth_device* dev, bd_t * bd); +static void tsec_halt(struct eth_device* dev); +static void init_registers(volatile tsec_t *regs); +static void startup_tsec(struct eth_device *dev); +static int init_phy(struct eth_device *dev); +void write_phy_reg(struct tsec_private *priv, uint regnum, uint value); +uint read_phy_reg(struct tsec_private *priv, uint regnum); +struct phy_info * get_phy_info(struct eth_device *dev); +void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); +static void adjust_link(struct eth_device *dev); +static void relocate_cmds(void); +static int tsec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +static int tsec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); + +/* Initialize device structure. Returns success if PHY + * initialization succeeded (i.e. if it recognizes the PHY) + */ +int tsec_initialize(bd_t *bis, int index, char *devname) +{ + struct eth_device* dev; + int i; + struct tsec_private *priv; + + dev = (struct eth_device*) malloc(sizeof *dev); + + if(NULL == dev) + return 0; + + memset(dev, 0, sizeof *dev); + + priv = (struct tsec_private *) malloc(sizeof(*priv)); + + if(NULL == priv) + return 0; + + privlist[index] = priv; + priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE); + priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR + + tsec_info[index].phyregidx*TSEC_SIZE); + + priv->phyaddr = tsec_info[index].phyaddr; + priv->flags = tsec_info[index].flags; + + sprintf(dev->name, devname); + dev->iobase = 0; + dev->priv = priv; + dev->init = tsec_init; + dev->halt = tsec_halt; + dev->send = tsec_send; + dev->recv = tsec_recv; + + /* Tell u-boot to get the addr from the env */ + for(i=0;i<6;i++) + dev->enetaddr[i] = 0; + + eth_register(dev); + + + /* Reset the MAC */ + priv->regs->maccfg1 |= MACCFG1_SOFT_RESET; + priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET); + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \ + && !defined(BITBANGMII) + miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write); +#endif + + /* Try to initialize PHY here, and return */ + return init_phy(dev); +} + + +/* Initializes data structures and registers for the controller, + * and brings the interface up. Returns the link status, meaning + * that it returns success if the link is up, failure otherwise. + * This allows u-boot to find the first active controller. */ +int tsec_init(struct eth_device* dev, bd_t * bd) +{ + uint tempval; + char tmpbuf[MAC_ADDR_LEN]; + int i; + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + /* Make sure the controller is stopped */ + tsec_halt(dev); + + /* Init MACCFG2. Defaults to GMII */ + regs->maccfg2 = MACCFG2_INIT_SETTINGS; + + /* Init ECNTRL */ + regs->ecntrl = ECNTRL_INIT_SETTINGS; + + /* Copy the station address into the address registers. + * Backwards, because little endian MACS are dumb */ + for(i=0;ienetaddr[i]; + } + regs->macstnaddr1 = *((uint *)(tmpbuf)); + + tempval = *((uint *)(tmpbuf +4)); + + regs->macstnaddr2 = tempval; + + /* reset the indices to zero */ + rxIdx = 0; + txIdx = 0; + + /* Clear out (for the most part) the other registers */ + init_registers(regs); + + /* Ready the device for tx/rx */ + startup_tsec(dev); + + /* If there's no link, fail */ + return priv->link; + +} + + +/* Write value to the device's PHY through the registers + * specified in priv, modifying the register specified in regnum. + * It will wait for the write to be done (or for a timeout to + * expire) before exiting + */ +void write_phy_reg(struct tsec_private *priv, uint regnum, uint value) +{ + volatile tsec_t *regbase = priv->phyregs; + uint phyid = priv->phyaddr; + int timeout=1000000; + + regbase->miimadd = (phyid << 8) | regnum; + regbase->miimcon = value; + asm("sync"); + + timeout=1000000; + while((regbase->miimind & MIIMIND_BUSY) && timeout--); +} + + +/* Reads register regnum on the device's PHY through the + * registers specified in priv. It lowers and raises the read + * command, and waits for the data to become valid (miimind + * notvalid bit cleared), and the bus to cease activity (miimind + * busy bit cleared), and then returns the value + */ +uint read_phy_reg(struct tsec_private *priv, uint regnum) +{ + uint value; + volatile tsec_t *regbase = priv->phyregs; + uint phyid = priv->phyaddr; + + /* Put the address of the phy, and the register + * number into MIIMADD */ + regbase->miimadd = (phyid << 8) | regnum; + + /* Clear the command register, and wait */ + regbase->miimcom = 0; + asm("sync"); + + /* Initiate a read command, and wait */ + regbase->miimcom = MIIM_READ_COMMAND; + asm("sync"); + + /* Wait for the the indication that the read is done */ + while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))); + + /* Grab the value read from the PHY */ + value = regbase->miimstat; + + return value; +} + + +/* Discover which PHY is attached to the device, and configure it + * properly. If the PHY is not recognized, then return 0 + * (failure). Otherwise, return 1 + */ +static int init_phy(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + struct phy_info *curphy; + + /* Assign a Physical address to the TBI */ + + { + volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR); + regs->tbipa = TBIPA_VALUE; + regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE); + regs->tbipa = TBIPA_VALUE; + asm("sync"); + } + + /* Reset MII (due to new addresses) */ + priv->phyregs->miimcfg = MIIMCFG_RESET; + asm("sync"); + priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE; + asm("sync"); + while(priv->phyregs->miimind & MIIMIND_BUSY); + + if(0 == relocated) + relocate_cmds(); + + /* Get the cmd structure corresponding to the attached + * PHY */ + curphy = get_phy_info(dev); + + if(NULL == curphy) { + printf("%s: No PHY found\n", dev->name); + + return 0; + } + + priv->phyinfo = curphy; + + phy_run_commands(priv, priv->phyinfo->config); + + return 1; +} + + +/* Returns which value to write to the control register. */ +/* For 10/100, the value is slightly different */ +uint mii_cr_init(uint mii_reg, struct tsec_private *priv) +{ + if(priv->flags & TSEC_GIGABIT) + return MIIM_CONTROL_INIT; + else + return MIIM_CR_INIT; +} + + +/* Parse the status register for link, and then do + * auto-negotiation */ +uint mii_parse_sr(uint mii_reg, struct tsec_private *priv) +{ + /* + * Wait if PHY is capable of autonegotiation and autonegotiation is not complete + */ + mii_reg = read_phy_reg(priv, MIIM_STATUS); + if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + int i = 0; + + puts ("Waiting for PHY auto negotiation to complete"); + while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts (" TIMEOUT !\n"); + priv->link = 0; + break; + } + + if ((i++ % 1000) == 0) { + putc ('.'); + } + udelay (1000); /* 1 ms */ + mii_reg = read_phy_reg(priv, MIIM_STATUS); + } + puts (" done\n"); + priv->link = 1; + udelay (500000); /* another 500 ms (results in faster booting) */ + } else { + priv->link = 1; + } + + return 0; +} + + +/* Parse the 88E1011's status register for speed and duplex + * information */ +uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv) +{ + uint speed; + + mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); + + if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && + (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { + int i = 0; + + puts ("Waiting for PHY realtime link"); + while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) && + (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts (" TIMEOUT !\n"); + priv->link = 0; + break; + } + + if ((i++ % 1000) == 0) { + putc ('.'); + } + udelay (1000); /* 1 ms */ + mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS); + } + puts (" done\n"); + udelay (500000); /* another 500 ms (results in faster booting) */ + } + + if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED); + + switch(speed) { + case MIIM_88E1011_PHYSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_88E1011_PHYSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + } + + return 0; +} + + +/* Parse the cis8201's status register for speed and duplex + * information */ +uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv) +{ + uint speed; + + if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED; + switch(speed) { + case MIIM_CIS8201_AUXCONSTAT_GBIT: + priv->speed = 1000; + break; + case MIIM_CIS8201_AUXCONSTAT_100: + priv->speed = 100; + break; + default: + priv->speed = 10; + break; + } + + return 0; +} + + +/* Parse the DM9161's status register for speed and duplex + * information */ +uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv) +{ + if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H)) + priv->speed = 100; + else + priv->speed = 10; + + if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F)) + priv->duplexity = 1; + else + priv->duplexity = 0; + + return 0; +} + + +/* Hack to write all 4 PHYs with the LED values */ +uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv) +{ + uint phyid; + volatile tsec_t *regbase = priv->phyregs; + int timeout=1000000; + + for(phyid=0;phyid<4;phyid++) { + regbase->miimadd = (phyid << 8) | mii_reg; + regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT; + asm("sync"); + + timeout=1000000; + while((regbase->miimind & MIIMIND_BUSY) && timeout--); + } + + return MIIM_CIS8204_SLEDCON_INIT; +} + +uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv) +{ + if (priv->flags & TSEC_REDUCED) + return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII; + else + return MIIM_CIS8204_EPHYCON_INIT; +} + +/* Initialized required registers to appropriate values, zeroing + * those we don't care about (unless zero is bad, in which case, + * choose a more appropriate value) */ +static void init_registers(volatile tsec_t *regs) +{ + /* Clear IEVENT */ + regs->ievent = IEVENT_INIT_CLEAR; + + regs->imask = IMASK_INIT_CLEAR; + + regs->hash.iaddr0 = 0; + regs->hash.iaddr1 = 0; + regs->hash.iaddr2 = 0; + regs->hash.iaddr3 = 0; + regs->hash.iaddr4 = 0; + regs->hash.iaddr5 = 0; + regs->hash.iaddr6 = 0; + regs->hash.iaddr7 = 0; + + regs->hash.gaddr0 = 0; + regs->hash.gaddr1 = 0; + regs->hash.gaddr2 = 0; + regs->hash.gaddr3 = 0; + regs->hash.gaddr4 = 0; + regs->hash.gaddr5 = 0; + regs->hash.gaddr6 = 0; + regs->hash.gaddr7 = 0; + + regs->rctrl = 0x00000000; + + /* Init RMON mib registers */ + memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); + + regs->rmon.cam1 = 0xffffffff; + regs->rmon.cam2 = 0xffffffff; + + regs->mrblr = MRBLR_INIT_SETTINGS; + + regs->minflr = MINFLR_INIT_SETTINGS; + + regs->attr = ATTR_INIT_SETTINGS; + regs->attreli = ATTRELI_INIT_SETTINGS; + +} + + +/* Configure maccfg2 based on negotiated speed and duplex + * reported by PHY handling code */ +static void adjust_link(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + if(priv->link) { + if(priv->duplexity != 0) + regs->maccfg2 |= MACCFG2_FULL_DUPLEX; + else + regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX); + + switch(priv->speed) { + case 1000: + regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) + | MACCFG2_GMII); + break; + case 100: + case 10: + regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) + | MACCFG2_MII); + + /* If We're in reduced mode, we need + * to say whether we're 10 or 100 MB. + */ + if ((priv->speed == 100) + && (priv->flags & TSEC_REDUCED)) + regs->ecntrl |= ECNTRL_R100; + else + regs->ecntrl &= ~(ECNTRL_R100); + break; + default: + printf("%s: Speed was bad\n", dev->name); + break; + } + + printf("Speed: %d, %s duplex\n", priv->speed, + (priv->duplexity) ? "full" : "half"); + + } else { + printf("%s: No link.\n", dev->name); + } +} + + +/* Set up the buffers and their descriptors, and bring up the + * interface */ +static void startup_tsec(struct eth_device *dev) +{ + int i; + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + /* Point to the buffer descriptors */ + regs->tbase = (unsigned int)(&rtx.txbd[txIdx]); + regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]); + + /* Initialize the Rx Buffer descriptors */ + for (i = 0; i < PKTBUFSRX; i++) { + rtx.rxbd[i].status = RXBD_EMPTY; + rtx.rxbd[i].length = 0; + rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i]; + } + rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP; + + /* Initialize the TX Buffer Descriptors */ + for(i=0; iphyinfo->startup); + adjust_link(dev); + + /* Enable Transmit and Receive */ + regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN); + + /* Tell the DMA it is clear to go */ + regs->dmactrl |= DMACTRL_INIT_SETTINGS; + regs->tstat = TSTAT_CLEAR_THALT; + regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); +} + +/* This returns the status bits of the device. The return value + * is never checked, and this is what the 8260 driver did, so we + * do the same. Presumably, this would be zero if there were no + * errors */ +static int tsec_send(struct eth_device* dev, volatile void *packet, int length) +{ + int i; + int result = 0; + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + /* Find an empty buffer descriptor */ + for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + if (i >= TOUT_LOOP) { + debug ("%s: tsec: tx buffers full\n", dev->name); + return result; + } + } + + rtx.txbd[txIdx].bufPtr = (uint)packet; + rtx.txbd[txIdx].length = length; + rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); + + /* Tell the DMA to go */ + regs->tstat = TSTAT_CLEAR_THALT; + + /* Wait for buffer to be transmitted */ + for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + if (i >= TOUT_LOOP) { + debug ("%s: tsec: tx error\n", dev->name); + return result; + } + } + + txIdx = (txIdx + 1) % TX_BUF_CNT; + result = rtx.txbd[txIdx].status & TXBD_STATS; + + return result; +} + +static int tsec_recv(struct eth_device* dev) +{ + int length; + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { + + length = rtx.rxbd[rxIdx].length; + + /* Send the packet up if there were no errors */ + if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { + NetReceive(NetRxPackets[rxIdx], length - 4); + } else { + printf("Got error %x\n", + (rtx.rxbd[rxIdx].status & RXBD_STATS)); + } + + rtx.rxbd[rxIdx].length = 0; + + /* Set the wrap bit if this is the last element in the list */ + rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + + rxIdx = (rxIdx + 1) % PKTBUFSRX; + } + + if(regs->ievent&IEVENT_BSY) { + regs->ievent = IEVENT_BSY; + regs->rstat = RSTAT_CLEAR_RHALT; + } + + return -1; + +} + + +/* Stop the interface */ +static void tsec_halt(struct eth_device* dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + volatile tsec_t *regs = priv->regs; + + regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS); + regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS); + + while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))); + + regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN); + + /* Shut down the PHY, as needed */ + phy_run_commands(priv, priv->phyinfo->shutdown); +} + + +struct phy_info phy_info_M88E1011S = { + 0x01410c6, + "Marvell 88E1011S", + 4, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +struct phy_info phy_info_M88E1111S = { + 0x01410cc, + "Marvell 88E1111S", + 4, + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +struct phy_info phy_info_cis8204 = { + 0x3f11, + "Cicada Cis8204", + 6, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled}, + {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +/* Cicada 8201 */ +struct phy_info phy_info_cis8201 = { + 0xfc41, + "CIS8201", + 4, + (struct phy_cmd[]) { /* config */ + /* Override PHY config settings */ + {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL}, + /* Set up the interface mode */ + {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Read the Status (2x to make sure link is right) */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + + +struct phy_info phy_info_dm9161 = { + 0x0181b88, + "Davicom DM9161E", + 4, + (struct phy_cmd[]) { /* config */ + {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL}, + /* Do not bypass the scrambler/descrambler */ + {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL}, + /* Clear 10BTCSR to default */ + {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL}, + /* Configure some basic stuff */ + {MIIM_CONTROL, MIIM_CR_INIT, NULL}, + /* Restart Auto Negotiation */ + {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv) +{ + unsigned int speed; + if (priv->link) { + speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK; + + switch (speed) { + case MIIM_LXT971_SR2_10HDX: + priv->speed = 10; + priv->duplexity = 0; + break; + case MIIM_LXT971_SR2_10FDX: + priv->speed = 10; + priv->duplexity = 1; + break; + case MIIM_LXT971_SR2_100HDX: + priv->speed = 100; + priv->duplexity = 0; + default: + priv->speed = 100; + priv->duplexity = 1; + break; + } + } else { + priv->speed = 0; + priv->duplexity = 0; + } + + return 0; +} + +static struct phy_info phy_info_lxt971 = { + 0x0001378e, + "LXT971", + 4, + (struct phy_cmd []) { /* config */ + { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */ + { miim_end, } + }, + (struct phy_cmd []) { /* startup - enable interrupts */ + /* { 0x12, 0x00f2, NULL }, */ + { MIIM_STATUS, miim_read, NULL }, + { MIIM_STATUS, miim_read, &mii_parse_sr }, + { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 }, + { miim_end, } + }, + (struct phy_cmd []) { /* shutdown - disable interrupts */ + { miim_end, } + }, +}; + +/* Parse the DP83865's link and auto-neg status register for speed and duplex + * information */ +uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv) +{ + switch (mii_reg & MIIM_DP83865_SPD_MASK) { + + case MIIM_DP83865_SPD_1000: + priv->speed = 1000; + break; + + case MIIM_DP83865_SPD_100: + priv->speed = 100; + break; + + default: + priv->speed = 10; + break; + + } + + if (mii_reg & MIIM_DP83865_DPX_FULL) + priv->duplexity = 1; + else + priv->duplexity = 0; + + return 0; +} + +struct phy_info phy_info_dp83865 = { + 0x20005c7, + "NatSemi DP83865", + 4, + (struct phy_cmd[]) { /* config */ + {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the link and auto-neg status */ + {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + +struct phy_info *phy_info[] = { +#if 0 + &phy_info_cis8201, +#endif + &phy_info_cis8204, + &phy_info_M88E1011S, + &phy_info_M88E1111S, + &phy_info_dm9161, + &phy_info_lxt971, + &phy_info_dp83865, + NULL +}; + + +/* Grab the identifier of the device's PHY, and search through + * all of the known PHYs to see if one matches. If so, return + * it, if not, return NULL */ +struct phy_info * get_phy_info(struct eth_device *dev) +{ + struct tsec_private *priv = (struct tsec_private *)dev->priv; + uint phy_reg, phy_ID; + int i; + struct phy_info *theInfo = NULL; + + /* Grab the bits from PHYIR1, and put them in the upper half */ + phy_reg = read_phy_reg(priv, MIIM_PHYIR1); + phy_ID = (phy_reg & 0xffff) << 16; + + /* Grab the bits from PHYIR2, and put them in the lower half */ + phy_reg = read_phy_reg(priv, MIIM_PHYIR2); + phy_ID |= (phy_reg & 0xffff); + + /* loop through all the known PHY types, and find one that */ + /* matches the ID we read from the PHY. */ + for(i=0; phy_info[i]; i++) { + if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) + theInfo = phy_info[i]; + } + + if(theInfo == NULL) + { + printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID); + return NULL; + } else { + debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); + } + + return theInfo; +} + + +/* Execute the given series of commands on the given device's + * PHY, running functions as necessary*/ +void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) +{ + int i; + uint result; + volatile tsec_t *phyregs = priv->phyregs; + + phyregs->miimcfg = MIIMCFG_RESET; + + phyregs->miimcfg = MIIMCFG_INIT_VALUE; + + while(phyregs->miimind & MIIMIND_BUSY); + + for(i=0;cmd->mii_reg != miim_end;i++) { + if(cmd->mii_data == miim_read) { + result = read_phy_reg(priv, cmd->mii_reg); + + if(cmd->funct != NULL) + (*(cmd->funct))(result, priv); + + } else { + if(cmd->funct != NULL) + result = (*(cmd->funct))(cmd->mii_reg, priv); + else + result = cmd->mii_data; + + write_phy_reg(priv, cmd->mii_reg, result); + + } + cmd++; + } +} + + +/* Relocate the function pointers in the phy cmd lists */ +static void relocate_cmds(void) +{ + struct phy_cmd **cmdlistptr; + struct phy_cmd *cmd; + int i,j,k; + + for(i=0; phy_info[i]; i++) { + /* First thing's first: relocate the pointers to the + * PHY command structures (the structs were done) */ + phy_info[i] = (struct phy_info *) ((uint)phy_info[i] + + gd->reloc_off); + phy_info[i]->name += gd->reloc_off; + phy_info[i]->config = + (struct phy_cmd *)((uint)phy_info[i]->config + + gd->reloc_off); + phy_info[i]->startup = + (struct phy_cmd *)((uint)phy_info[i]->startup + + gd->reloc_off); + phy_info[i]->shutdown = + (struct phy_cmd *)((uint)phy_info[i]->shutdown + + gd->reloc_off); + + cmdlistptr = &phy_info[i]->config; + j=0; + for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) { + k=0; + for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) { + /* Only relocate non-NULL pointers */ + if(cmd->funct) + cmd->funct += gd->reloc_off; + + k++; + } + j++; + } + } + + relocated = 1; +} + + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \ + && !defined(BITBANGMII) + +struct tsec_private * get_priv_for_phy(unsigned char phyaddr) +{ + int i; + + for(i=0;iphyaddr == phyaddr) + return privlist[i]; + } + + return NULL; +} + +/* + * Read a MII PHY register. + * + * Returns: + * 0 on success + */ +static int tsec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + unsigned short ret; + struct tsec_private *priv = get_priv_for_phy(addr); + + if(NULL == priv) { + printf("Can't read PHY at address %d\n", addr); + return -1; + } + + ret = (unsigned short)read_phy_reg(priv, reg); + *value = ret; + + return 0; +} + +/* + * Write a MII PHY register. + * + * Returns: + * 0 on success + */ +static int tsec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct tsec_private *priv = get_priv_for_phy(addr); + + if(NULL == priv) { + printf("Can't write PHY at address %d\n", addr); + return -1; + } + + write_phy_reg(priv, reg, value); + + return 0; +} + +#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + && !defined(BITBANGMII) */ + +#endif /* CONFIG_TSEC_ENET */ diff --git a/drivers/tsec.h b/drivers/tsec.h new file mode 100644 index 000000000..b55b2992b --- /dev/null +++ b/drivers/tsec.h @@ -0,0 +1,520 @@ +/* + * tsec.h + * + * Driver for the Motorola Triple Speed Ethernet Controller + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003, Motorola, Inc. + * maintained by Xianghua Xiao (x.xiao@motorola.com) + * author Andy Fleming + * + */ + +#ifndef __TSEC_H +#define __TSEC_H + +#include +#include + +#ifndef CFG_TSEC1_OFFSET + #define CFG_TSEC1_OFFSET (0x24000) +#endif + +#define TSEC_SIZE 0x01000 + +/* FIXME: Should these be pushed back to 83xx and 85xx config files? */ +#if defined(CONFIG_MPC85xx) + #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) +#elif defined(CONFIG_MPC83XX) + #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET) +#endif + + +#define MAC_ADDR_LEN 6 + +/* #define TSEC_TIMEOUT 1000000 */ +#define TSEC_TIMEOUT 1000 +#define TOUT_LOOP 1000000 + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ + +/* MAC register bits */ +#define MACCFG1_SOFT_RESET 0x80000000 +#define MACCFG1_RESET_RX_MC 0x00080000 +#define MACCFG1_RESET_TX_MC 0x00040000 +#define MACCFG1_RESET_RX_FUN 0x00020000 +#define MACCFG1_RESET_TX_FUN 0x00010000 +#define MACCFG1_LOOPBACK 0x00000100 +#define MACCFG1_RX_FLOW 0x00000020 +#define MACCFG1_TX_FLOW 0x00000010 +#define MACCFG1_SYNCD_RX_EN 0x00000008 +#define MACCFG1_RX_EN 0x00000004 +#define MACCFG1_SYNCD_TX_EN 0x00000002 +#define MACCFG1_TX_EN 0x00000001 + +#define MACCFG2_INIT_SETTINGS 0x00007205 +#define MACCFG2_FULL_DUPLEX 0x00000001 +#define MACCFG2_IF 0x00000300 +#define MACCFG2_GMII 0x00000200 +#define MACCFG2_MII 0x00000100 + +#define ECNTRL_INIT_SETTINGS 0x00001000 +#define ECNTRL_TBI_MODE 0x00000020 +#define ECNTRL_R100 0x00000008 + +#define miim_end -2 +#define miim_read -1 + +#define TBIPA_VALUE 0x1f +#define MIIMCFG_INIT_VALUE 0x00000003 +#define MIIMCFG_RESET 0x80000000 + +#define MIIMIND_BUSY 0x00000001 +#define MIIMIND_NOTVALID 0x00000004 + +#define MIIM_CONTROL 0x00 +#define MIIM_CONTROL_RESET 0x00009140 +#define MIIM_CONTROL_INIT 0x00001140 +#define MIIM_CONTROL_RESTART 0x00001340 +#define MIIM_ANEN 0x00001000 + +#define MIIM_CR 0x00 +#define MIIM_CR_RST 0x00008000 +#define MIIM_CR_INIT 0x00001000 + +#define MIIM_STATUS 0x1 +#define MIIM_STATUS_AN_DONE 0x00000020 +#define MIIM_STATUS_LINK 0x0004 +#define PHY_BMSR_AUTN_ABLE 0x0008 +#define PHY_BMSR_AUTN_COMP 0x0020 + +#define MIIM_PHYIR1 0x2 +#define MIIM_PHYIR2 0x3 + +#define MIIM_ANAR 0x4 +#define MIIM_ANAR_INIT 0x1e1 + +#define MIIM_TBI_ANLPBPA 0x5 +#define MIIM_TBI_ANLPBPA_HALF 0x00000040 +#define MIIM_TBI_ANLPBPA_FULL 0x00000020 + +#define MIIM_TBI_ANEX 0x6 +#define MIIM_TBI_ANEX_NP 0x00000004 +#define MIIM_TBI_ANEX_PRX 0x00000002 + +#define MIIM_GBIT_CONTROL 0x9 +#define MIIM_GBIT_CONTROL_INIT 0xe00 + +/* Cicada Auxiliary Control/Status Register */ +#define MIIM_CIS8201_AUX_CONSTAT 0x1c +#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 +#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 +#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 +#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 +#define MIIM_CIS8201_AUXCONSTAT_100 0x0008 + +/* Cicada Extended Control Register 1 */ +#define MIIM_CIS8201_EXT_CON1 0x17 +#define MIIM_CIS8201_EXTCON1_INIT 0x0000 + +/* Cicada 8204 Extended PHY Control Register 1 */ +#define MIIM_CIS8204_EPHY_CON 0x17 +#define MIIM_CIS8204_EPHYCON_INIT 0x0006 +#define MIIM_CIS8204_EPHYCON_RGMII 0x1100 + +/* Cicada 8204 Serial LED Control Register */ +#define MIIM_CIS8204_SLED_CON 0x1b +#define MIIM_CIS8204_SLEDCON_INIT 0x1115 + +#define MIIM_GBIT_CON 0x09 +#define MIIM_GBIT_CON_ADVERT 0x0e00 + +/* 88E1011 PHY Status Register */ +#define MIIM_88E1011_PHY_STATUS 0x11 +#define MIIM_88E1011_PHYSTAT_SPEED 0xc000 +#define MIIM_88E1011_PHYSTAT_GBIT 0x8000 +#define MIIM_88E1011_PHYSTAT_100 0x4000 +#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 +#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 +#define MIIM_88E1011_PHYSTAT_LINK 0x0400 + +/* DM9161 Control register values */ +#define MIIM_DM9161_CR_STOP 0x0400 +#define MIIM_DM9161_CR_RSTAN 0x1200 + +#define MIIM_DM9161_SCR 0x10 +#define MIIM_DM9161_SCR_INIT 0x0610 + +/* DM9161 Specified Configuration and Status Register */ +#define MIIM_DM9161_SCSR 0x11 +#define MIIM_DM9161_SCSR_100F 0x8000 +#define MIIM_DM9161_SCSR_100H 0x4000 +#define MIIM_DM9161_SCSR_10F 0x2000 +#define MIIM_DM9161_SCSR_10H 0x1000 + +/* DM9161 10BT Configuration/Status */ +#define MIIM_DM9161_10BTCSR 0x12 +#define MIIM_DM9161_10BTCSR_INIT 0x7800 + +/* LXT971 Status 2 registers */ +#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ +#define MIIM_LXT971_SR2_SPEED_MASK 0x4200 +#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ +#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ + +/* DP83865 Control register values */ +#define MIIM_DP83865_CR_INIT 0x9200 + +/* DP83865 Link and Auto-Neg Status Register */ +#define MIIM_DP83865_LANR 0x11 +#define MIIM_DP83865_SPD_MASK 0x0018 +#define MIIM_DP83865_SPD_1000 0x0010 +#define MIIM_DP83865_SPD_100 0x0008 +#define MIIM_DP83865_DPX_FULL 0x0002 + +#define MIIM_READ_COMMAND 0x00000001 + +#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN + +#define MINFLR_INIT_SETTINGS 0x00000040 + +#define DMACTRL_INIT_SETTINGS 0x000000c3 +#define DMACTRL_GRS 0x00000010 +#define DMACTRL_GTS 0x00000008 + +#define TSTAT_CLEAR_THALT 0x80000000 +#define RSTAT_CLEAR_RHALT 0x00800000 + + +#define IEVENT_INIT_CLEAR 0xffffffff +#define IEVENT_BABR 0x80000000 +#define IEVENT_RXC 0x40000000 +#define IEVENT_BSY 0x20000000 +#define IEVENT_EBERR 0x10000000 +#define IEVENT_MSRO 0x04000000 +#define IEVENT_GTSC 0x02000000 +#define IEVENT_BABT 0x01000000 +#define IEVENT_TXC 0x00800000 +#define IEVENT_TXE 0x00400000 +#define IEVENT_TXB 0x00200000 +#define IEVENT_TXF 0x00100000 +#define IEVENT_IE 0x00080000 +#define IEVENT_LC 0x00040000 +#define IEVENT_CRL 0x00020000 +#define IEVENT_XFUN 0x00010000 +#define IEVENT_RXB0 0x00008000 +#define IEVENT_GRSC 0x00000100 +#define IEVENT_RXF0 0x00000080 + +#define IMASK_INIT_CLEAR 0x00000000 +#define IMASK_TXEEN 0x00400000 +#define IMASK_TXBEN 0x00200000 +#define IMASK_TXFEN 0x00100000 +#define IMASK_RXFEN0 0x00000080 + + +/* Default Attribute fields */ +#define ATTR_INIT_SETTINGS 0x000000c0 +#define ATTRELI_INIT_SETTINGS 0x00000000 + + +/* TxBD status field bits */ +#define TXBD_READY 0x8000 +#define TXBD_PADCRC 0x4000 +#define TXBD_WRAP 0x2000 +#define TXBD_INTERRUPT 0x1000 +#define TXBD_LAST 0x0800 +#define TXBD_CRC 0x0400 +#define TXBD_DEF 0x0200 +#define TXBD_HUGEFRAME 0x0080 +#define TXBD_LATECOLLISION 0x0080 +#define TXBD_RETRYLIMIT 0x0040 +#define TXBD_RETRYCOUNTMASK 0x003c +#define TXBD_UNDERRUN 0x0002 +#define TXBD_STATS 0x03ff + +/* RxBD status field bits */ +#define RXBD_EMPTY 0x8000 +#define RXBD_RO1 0x4000 +#define RXBD_WRAP 0x2000 +#define RXBD_INTERRUPT 0x1000 +#define RXBD_LAST 0x0800 +#define RXBD_FIRST 0x0400 +#define RXBD_MISS 0x0100 +#define RXBD_BROADCAST 0x0080 +#define RXBD_MULTICAST 0x0040 +#define RXBD_LARGE 0x0020 +#define RXBD_NONOCTET 0x0010 +#define RXBD_SHORT 0x0008 +#define RXBD_CRCERR 0x0004 +#define RXBD_OVERRUN 0x0002 +#define RXBD_TRUNCATED 0x0001 +#define RXBD_STATS 0x003f + +typedef struct txbd8 +{ + ushort status; /* Status Fields */ + ushort length; /* Buffer length */ + uint bufPtr; /* Buffer Pointer */ +} txbd8_t; + +typedef struct rxbd8 +{ + ushort status; /* Status Fields */ + ushort length; /* Buffer Length */ + uint bufPtr; /* Buffer Pointer */ +} rxbd8_t; + +typedef struct rmon_mib +{ + /* Transmit and Receive Counters */ + uint tr64; /* Transmit and Receive 64-byte Frame Counter */ + uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ + uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ + uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ + uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ + uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ + uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ + /* Receive Counters */ + uint rbyt; /* Receive Byte Counter */ + uint rpkt; /* Receive Packet Counter */ + uint rfcs; /* Receive FCS Error Counter */ + uint rmca; /* Receive Multicast Packet (Counter) */ + uint rbca; /* Receive Broadcast Packet */ + uint rxcf; /* Receive Control Frame Packet */ + uint rxpf; /* Receive Pause Frame Packet */ + uint rxuo; /* Receive Unknown OP Code */ + uint raln; /* Receive Alignment Error */ + uint rflr; /* Receive Frame Length Error */ + uint rcde; /* Receive Code Error */ + uint rcse; /* Receive Carrier Sense Error */ + uint rund; /* Receive Undersize Packet */ + uint rovr; /* Receive Oversize Packet */ + uint rfrg; /* Receive Fragments */ + uint rjbr; /* Receive Jabber */ + uint rdrp; /* Receive Drop */ + /* Transmit Counters */ + uint tbyt; /* Transmit Byte Counter */ + uint tpkt; /* Transmit Packet */ + uint tmca; /* Transmit Multicast Packet */ + uint tbca; /* Transmit Broadcast Packet */ + uint txpf; /* Transmit Pause Control Frame */ + uint tdfr; /* Transmit Deferral Packet */ + uint tedf; /* Transmit Excessive Deferral Packet */ + uint tscl; /* Transmit Single Collision Packet */ + /* (0x2_n700) */ + uint tmcl; /* Transmit Multiple Collision Packet */ + uint tlcl; /* Transmit Late Collision Packet */ + uint txcl; /* Transmit Excessive Collision Packet */ + uint tncl; /* Transmit Total Collision */ + + uint res2; + + uint tdrp; /* Transmit Drop Frame */ + uint tjbr; /* Transmit Jabber Frame */ + uint tfcs; /* Transmit FCS Error */ + uint txcf; /* Transmit Control Frame */ + uint tovr; /* Transmit Oversize Frame */ + uint tund; /* Transmit Undersize Frame */ + uint tfrg; /* Transmit Fragments Frame */ + /* General Registers */ + uint car1; /* Carry Register One */ + uint car2; /* Carry Register Two */ + uint cam1; /* Carry Register One Mask */ + uint cam2; /* Carry Register Two Mask */ +} rmon_mib_t; + +typedef struct tsec_hash_regs +{ + uint iaddr0; /* Individual Address Register 0 */ + uint iaddr1; /* Individual Address Register 1 */ + uint iaddr2; /* Individual Address Register 2 */ + uint iaddr3; /* Individual Address Register 3 */ + uint iaddr4; /* Individual Address Register 4 */ + uint iaddr5; /* Individual Address Register 5 */ + uint iaddr6; /* Individual Address Register 6 */ + uint iaddr7; /* Individual Address Register 7 */ + uint res1[24]; + uint gaddr0; /* Group Address Register 0 */ + uint gaddr1; /* Group Address Register 1 */ + uint gaddr2; /* Group Address Register 2 */ + uint gaddr3; /* Group Address Register 3 */ + uint gaddr4; /* Group Address Register 4 */ + uint gaddr5; /* Group Address Register 5 */ + uint gaddr6; /* Group Address Register 6 */ + uint gaddr7; /* Group Address Register 7 */ + uint res2[24]; +} tsec_hash_t; + +typedef struct tsec +{ + /* General Control and Status Registers (0x2_n000) */ + uint res000[4]; + + uint ievent; /* Interrupt Event */ + uint imask; /* Interrupt Mask */ + uint edis; /* Error Disabled */ + uint res01c; + uint ecntrl; /* Ethernet Control */ + uint minflr; /* Minimum Frame Length */ + uint ptv; /* Pause Time Value */ + uint dmactrl; /* DMA Control */ + uint tbipa; /* TBI PHY Address */ + + uint res034[3]; + uint res040[48]; + + /* Transmit Control and Status Registers (0x2_n100) */ + uint tctrl; /* Transmit Control */ + uint tstat; /* Transmit Status */ + uint res108; + uint tbdlen; /* Tx BD Data Length */ + uint res110[5]; + uint ctbptr; /* Current TxBD Pointer */ + uint res128[23]; + uint tbptr; /* TxBD Pointer */ + uint res188[30]; + /* (0x2_n200) */ + uint res200; + uint tbase; /* TxBD Base Address */ + uint res208[42]; + uint ostbd; /* Out of Sequence TxBD */ + uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ + uint res2b8[18]; + + /* Receive Control and Status Registers (0x2_n300) */ + uint rctrl; /* Receive Control */ + uint rstat; /* Receive Status */ + uint res308; + uint rbdlen; /* RxBD Data Length */ + uint res310[4]; + uint res320; + uint crbptr; /* Current Receive Buffer Pointer */ + uint res328[6]; + uint mrblr; /* Maximum Receive Buffer Length */ + uint res344[16]; + uint rbptr; /* RxBD Pointer */ + uint res388[30]; + /* (0x2_n400) */ + uint res400; + uint rbase; /* RxBD Base Address */ + uint res408[62]; + + /* MAC Registers (0x2_n500) */ + uint maccfg1; /* MAC Configuration #1 */ + uint maccfg2; /* MAC Configuration #2 */ + uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ + uint hafdup; /* Half-duplex */ + uint maxfrm; /* Maximum Frame */ + uint res514; + uint res518; + + uint res51c; + + uint miimcfg; /* MII Management: Configuration */ + uint miimcom; /* MII Management: Command */ + uint miimadd; /* MII Management: Address */ + uint miimcon; /* MII Management: Control */ + uint miimstat; /* MII Management: Status */ + uint miimind; /* MII Management: Indicators */ + + uint res538; + + uint ifstat; /* Interface Status */ + uint macstnaddr1; /* Station Address, part 1 */ + uint macstnaddr2; /* Station Address, part 2 */ + uint res548[46]; + + /* (0x2_n600) */ + uint res600[32]; + + /* RMON MIB Registers (0x2_n680-0x2_n73c) */ + rmon_mib_t rmon; + uint res740[48]; + + /* Hash Function Registers (0x2_n800) */ + tsec_hash_t hash; + + uint res900[128]; + + /* Pattern Registers (0x2_nb00) */ + uint resb00[62]; + uint attr; /* Default Attribute Register */ + uint attreli; /* Default Attribute Extract Length and Index */ + + /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ + uint resc00[256]; +} tsec_t; + +#define TSEC_GIGABIT (1) + +/* This flag currently only has + * meaning if we're using the eTSEC */ +#define TSEC_REDUCED (1 << 1) + +struct tsec_private { + volatile tsec_t *regs; + volatile tsec_t *phyregs; + struct phy_info *phyinfo; + uint phyaddr; + u32 flags; + uint link; + uint duplexity; + uint speed; +}; + + +/* + * struct phy_cmd: A command for reading or writing a PHY register + * + * mii_reg: The register to read or write + * + * mii_data: For writes, the value to put in the register. + * A value of -1 indicates this is a read. + * + * funct: A function pointer which is invoked for each command. + * For reads, this function will be passed the value read + * from the PHY, and process it. + * For writes, the result of this function will be written + * to the PHY register + */ +struct phy_cmd { + uint mii_reg; + uint mii_data; + uint (*funct) (uint mii_reg, struct tsec_private* priv); +}; + +/* struct phy_info: a structure which defines attributes for a PHY + * + * id will contain a number which represents the PHY. During + * startup, the driver will poll the PHY to find out what its + * UID--as defined by registers 2 and 3--is. The 32-bit result + * gotten from the PHY will be shifted right by "shift" bits to + * discard any bits which may change based on revision numbers + * unimportant to functionality + * + * The struct phy_cmd entries represent pointers to an arrays of + * commands which tell the driver what to do to the PHY. + */ +struct phy_info { + uint id; + char *name; + uint shift; + /* Called to configure the PHY, and modify the controller + * based on the results */ + struct phy_cmd *config; + + /* Called when starting up the controller */ + struct phy_cmd *startup; + + /* Called when bringing down the controller */ + struct phy_cmd *shutdown; +}; + +#endif /* __TSEC_H */ diff --git a/drivers/twl4030.c b/drivers/twl4030.c new file mode 100644 index 000000000..c46085e2e --- /dev/null +++ b/drivers/twl4030.c @@ -0,0 +1,823 @@ +/* + * Copyright (C) 2007-2008 Texas Instruments, Inc. + * + * USB + * Imported from omap3-dev drivers/usb/twl4030_usb.c + * This is unique part of the copyright + * + * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller + * + * (C) Copyright 2009 Atin Malaviya (atin.malaviya@gmail.com) + * + * Based on: twl4030_usb.c in linux 2.6 (drivers/i2c/chips/twl4030_usb.c) + * Copyright (C) 2004-2007 Texas Instruments + * Copyright (C) 2008 Nokia Corporation + * Contact: Felipe Balbi + * + * Author: Atin Malaviya (atin.malaviya@gmail.com) + * + * + * Keypad + * + * (C) Copyright 2009 + * Windriver, + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include + +/* + * Battery + */ +#define mdelay(n) ({ unsigned long msec = (n); while (msec--) udelay(1000); }) + +/* Functions to read and write from TWL4030 */ +static inline int twl4030_i2c_write_u8(u8 chip_no, u8 val, u8 reg) +{ + return i2c_write(chip_no, reg, 1, &val, 1); +} + +static inline int twl4030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg) +{ + return i2c_read(chip_no, reg, 1, val, 1); +} + +/* + * Sets and clears bits on an given register on a given module + */ +static inline int clear_n_set(u8 chip_no, u8 clear, u8 set, u8 reg) +{ + int ret; + u8 val = 0; + + /* Gets the initial register value */ + ret = twl4030_i2c_read_u8(chip_no, &val, reg); + if (ret) { + printf("a\n"); + return ret; + } + + /* Clearing all those bits to clear */ + val &= ~(clear); + + /* Setting all those bits to set */ + val |= set; + + /* Update the register */ + ret = twl4030_i2c_write_u8(chip_no, val, reg); + if (ret) { + printf("b\n"); + return ret; + } + return 0; +} + +/* + * Disable/Enable AC Charge funtionality. + */ +static int twl4030_ac_charger_enable(int enable) +{ + int ret; + + if (enable) { + /* forcing the field BCIAUTOAC (BOOT_BCI[0]) to 1 */ + ret = clear_n_set(TWL4030_CHIP_PM_MASTER, 0, + (CONFIG_DONE | BCIAUTOWEN | BCIAUTOAC), + REG_BOOT_BCI); + if (ret) + return ret; + } else { + /* forcing the field BCIAUTOAC (BOOT_BCI[0]) to 0 */ + ret = clear_n_set(TWL4030_CHIP_PM_MASTER, BCIAUTOAC, + (CONFIG_DONE | BCIAUTOWEN), + REG_BOOT_BCI); + if (ret) + return ret; + } + return 0; +} + +/* + * Disable/Enable USB Charge funtionality. + */ +static int twl4030_usb_charger_enable(int enable) +{ + u8 value; + int ret; + + if (enable) { + /* enable access to BCIIREF1 */ + ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xE7, + REG_BCIMFKEY); + if (ret) + return ret; + + /* set charging current = 852mA */ + ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xFF, + REG_BCIIREF1); + if (ret) + return ret; + + /* forcing the field BCIAUTOUSB (BOOT_BCI[1]) to 1 */ + ret = clear_n_set(TWL4030_CHIP_PM_MASTER, 0, + (CONFIG_DONE | BCIAUTOWEN | BCIAUTOUSB), + REG_BOOT_BCI); + if (ret) + return ret; + + /* Enabling interfacing with usb thru OCP */ + ret = clear_n_set(TWL4030_CHIP_USB, 0, PHY_DPLL_CLK, + REG_PHY_CLK_CTRL); + if (ret) + return ret; + + value = 0; + + while (!(value & PHY_DPLL_CLK)) { + udelay(10); + ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &value, + REG_PHY_CLK_CTRL_STS); + if (ret) + return ret; + } + + /* OTG_EN (POWER_CTRL[5]) to 1 */ + ret = clear_n_set(TWL4030_CHIP_USB, 0, OTG_EN, + REG_POWER_CTRL); + if (ret) + return ret; + + mdelay(50); + + /* forcing USBFASTMCHG(BCIMFSTS4[2]) to 1 */ + ret = clear_n_set(TWL4030_CHIP_MAIN_CHARGE, 0, + USBFASTMCHG, REG_BCIMFSTS4); + if (ret) + return ret; + } else { + ret = clear_n_set(TWL4030_CHIP_PM_MASTER, BCIAUTOUSB, + (CONFIG_DONE | BCIAUTOWEN), REG_BOOT_BCI); + if (ret) + return ret; + } + + return 0; +} + +/* + * Setup the twl4030 MADC module to measure the backup + * battery voltage. + */ +static int twl4030_madc_setup(void) +{ + int ret = 0; + + /* turning MADC clocks on */ + ret = clear_n_set(TWL4030_CHIP_INTBR, 0, + (MADC_HFCLK_EN | DEFAULT_MADC_CLK_EN), REG_GPBR1); + if (ret) + return ret; + + /* turning adc_on */ + ret = twl4030_i2c_write_u8(TWL4030_CHIP_MADC, MADC_ON, + REG_CTRL1); + if (ret) + return ret; + + /* setting MDC channel 9 to trigger by SW1 */ + ret = clear_n_set(TWL4030_CHIP_MADC, 0, SW1_CH9_SEL, + REG_SW1SELECT_MSB); + + return ret; +} + +/* + * Charge backup battery through main battery + */ +static int twl4030_charge_backup_battery(void) +{ + int ret; + + ret = clear_n_set(TWL4030_CHIP_PM_RECEIVER, 0xff, + (BBCHEN | BBSEL_3200mV | BBISEL_150uA), REG_BB_CFG); + if (ret) + return ret; + + return 0; +} + +/* + * Helper function to read a 2-byte register on BCI module + */ +static int read_bci_val(u8 reg) +{ + int ret = 0, temp = 0; + u8 val; + + /* reading MSB */ + ret = twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, reg + 1); + if (ret) + return ret; + + temp = ((int)(val & 0x03)) << 8; + + /* reading LSB */ + ret = twl4030_i2c_read_u8(TWL4030_CHIP_MAIN_CHARGE, &val, reg); + if (ret) + return ret; + + return temp + val; +} + +/* + * Triggers the sw1 request for the twl4030 module to measure the sw1 selected + * channels + */ +static int twl4030_madc_sw1_trigger(void) +{ + u8 val; + int ret; + + /* Triggering SW1 MADC convertion */ + ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, REG_CTRL_SW1); + if (ret) + return ret; + + val |= SW1_TRIGGER; + + ret = twl4030_i2c_write_u8(TWL4030_CHIP_MADC, val, REG_CTRL_SW1); + if (ret) + return ret; + + /* Waiting until the SW1 conversion ends*/ + val = BUSY; + + while (!((val & EOC_SW1) && (!(val & BUSY)))) { + ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &val, + REG_CTRL_SW1); + if (ret) + return ret; + mdelay(10); + } + + return 0; +} + +/* + * Return battery voltage + */ +static int twl4030_get_battery_voltage(void) +{ + int volt; + + volt = read_bci_val(T2_BATTERY_VOLT); + return (volt * 588) / 100; +} + +/* + * Return the battery backup voltage + */ +static int twl4030_get_backup_battery_voltage(void) +{ + int ret, temp; + u8 volt; + + /* trigger MADC convertion */ + twl4030_madc_sw1_trigger(); + + ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &volt, REG_GPCH9 + 1); + if (ret) + return ret; + + temp = ((int) volt) << 2; + + ret = twl4030_i2c_read_u8(TWL4030_CHIP_MADC, &volt, REG_GPCH9); + if (ret) + return ret; + + temp = temp + ((int) ((volt & MADC_LSB_MASK) >> 6)); + + return (temp * 441) / 100; +} + +#if 0 /* Maybe used in future */ +/* + * Return the AC power supply voltage + */ +static int twl4030_get_ac_charger_voltage(void) +{ + int volt = read_bci_val(T2_BATTERY_ACVOLT); + return (volt * 735) / 100; +} + +/* + * Return the USB power supply voltage + */ +static int twl4030_get_usb_charger_voltage(void) +{ + int volt = read_bci_val(T2_BATTERY_USBVOLT); + return (volt * 2058) / 300; +} +#endif + +/* + * Battery charging main function called from board-specific file + */ + +int twl4030_init_battery_charging(void) +{ + u8 hwsts; + int battery_volt = 0, charger_present = 0; + int ret = 0, ac_t2_enabled = 0, charger_tries = 0; + +#ifdef CONFIG_3430ZOOM2 + /* For Zoom2 enable Main charge Automatic mode: + * by enabling MADC clocks + */ + + OMAP3_LED_ERROR_ON(); + + /* Disable USB, enable AC: 0x35 defalut */ + ret = clear_n_set(TWL4030_CHIP_PM_MASTER, BCIAUTOUSB, + BCIAUTOAC, + REG_BOOT_BCI); + + /* Enable AC charging : ROM code is shutting down MADC CLK */ + ret = clear_n_set(TWL4030_CHIP_INTBR, 0, + (MADC_HFCLK_EN | DEFAULT_MADC_CLK_EN), REG_GPBR1); + + udelay(100); + + ret = clear_n_set(TWL4030_CHIP_PM_MASTER, + BCIAUTOAC | CVENAC, + 0, + REG_BOOT_BCI); + + /* Change charging current */ + ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xE7, + REG_BCIMFKEY); + /* set 1 Amp charging */ + ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0x58, + REG_BCIIREF1); + ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0xE7, + REG_BCIMFKEY); + ret = twl4030_i2c_write_u8(TWL4030_CHIP_MAIN_CHARGE, 0x03, + REG_BCIIREF2); + + /* Set CGAIN=1 */ + ret = clear_n_set(TWL4030_CHIP_MAIN_CHARGE, + 0, + CGAIN, + REG_BCICTL1); + + ret = clear_n_set(TWL4030_CHIP_PM_MASTER, + 0, + BCIAUTOAC | CVENAC, + REG_BOOT_BCI); + + +#endif + +#ifdef CFG_BATTERY_CHARGING + /* Read the sts_hw_conditions register */ + twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &hwsts, + REG_STS_HW_CONDITIONS); + + /* AC T2 charger present */ + if (hwsts & STS_CHG) { + OMAP3_LED_OK_ON(); /* Blue LED - on */ + ret = twl4030_ac_charger_enable(1); + if (ret) + return ret; + udelay(10000); /* 0.01 sec */ + charger_present = 1; + ac_t2_enabled = 1; + OMAP3_LED_OK_OFF(); /* Blue LED - off */ + } + + /* USB charger present */ + if ((hwsts & STS_VBUS) | (hwsts & STS_USB)) { + OMAP3_LED_OK_ON(); /* Blue LED - on */ + charger_present = 1; + } + + ret = twl4030_madc_setup(); + if (ret) { + printf("twl4030 madc setup error %d\n", ret); + return ret; + } + + /* usb charging is enabled regardless of the whether the + * charger is attached, otherwise we will not be able to enable + * usb charging at a later stage + */ + ret = twl4030_usb_charger_enable(1); + if (ret) + return ret; + udelay(10000); /* 0.01 sec */ + OMAP3_LED_OK_OFF(); /* Blue LED - off */ + + /* AC charging is enabled regardless of the whether the + * charger is attached + */ + if (!ac_t2_enabled) { + ret = twl4030_ac_charger_enable(1); + if (ret) + return ret; + } + + /* backup battery charges through main battery */ + ret = twl4030_charge_backup_battery(); + if (ret) { + printf("backup battery charging error\n"); + return ret; + } + + battery_volt = twl4030_get_battery_voltage(); + printf("Battery levels: main %d mV, backup %d mV\n", + battery_volt, twl4030_get_backup_battery_voltage()); + if (battery_volt < CFG_LOW_BAT) { + printf("Main battery charge too low!\n"); + printf("Please connect USB or AC charger to continue.\n"); + /* + * Main charging loop + * If the battery volage is below CFG_LOW_BAT, attempt is made + * to recharge the battery to CFG_BAT_CHG. The main led will + * blink red until either the ac or the usb charger is connected. + */ + do { + /* Read the sts_hw_conditions register */ + twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &hwsts, + REG_STS_HW_CONDITIONS); + + if ((hwsts & STS_CHG) | + ((hwsts & STS_VBUS) | (hwsts & STS_USB))) { + OMAP3_LED_OK_OFF(); /* Blue LED - off */ + charger_present = 1; + } else { + OMAP3_LED_ERROR_OFF(); + udelay(10000); /* 0.01 sec */ + } + + if (charger_present) { + OMAP3_LED_OK_ON(); /* Blue LED - on */ + udelay(10000); /* 0.01 sec */ + } else + OMAP3_LED_ERROR_ON(); + + charger_tries++; + + if (ctrlc()) { + printf("Battery charging terminated by user\n"); + printf("Battery charged to %d\n", battery_volt); + break; + } else if (charger_tries > + CFG_CHARGER_TRIES_MAX) { + printf("No charger connected, \ + giving up on charging.\n"); + break; + } + + } while (((battery_volt = twl4030_get_battery_voltage()) + < CFG_BAT_CHG) && (!charger_present)); + /* If debug board charger is connected, + * battery_volt is approximately 4100mV + */ + } + + OMAP3_LED_OK_OFF(); /* Blue LED - off */ + OMAP3_LED_ERROR_OFF(); + +#endif + + return ret; + +} + +#if (defined(CONFIG_TWL4030_KEYPAD) && (CONFIG_TWL4030_KEYPAD)) +/* + * Keypad + */ +int twl4030_keypad_init(void) +{ + int ret = 0; + u8 ctrl; + ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl, KEYPAD_KEYP_CTRL_REG); + if (!ret) { + ctrl |= KEYPAD_CTRL_KBD_ON | KEYPAD_CTRL_SOFT_NRST; + ctrl &= ~KEYPAD_CTRL_SOFTMODEN; + ret = twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl, KEYPAD_KEYP_CTRL_REG); + } + return ret; +} + +int twl4030_keypad_reset(void) +{ + int ret = 0; + u8 ctrl; + ret = twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &ctrl, KEYPAD_KEYP_CTRL_REG); + if (!ret) { + ctrl &= ~KEYPAD_CTRL_SOFT_NRST; + ret = twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, ctrl, KEYPAD_KEYP_CTRL_REG); + } + return ret; +} + +int twl4030_keypad_keys_pressed(unsigned char *key1, unsigned char *key2) +{ + int ret = 0; + u8 cb, c, rb, r; + for (cb = 0; cb < 8; cb++) { + c = 0xff & ~(1 << cb); + twl4030_i2c_write_u8(TWL4030_CHIP_KEYPAD, c, KEYPAD_KBC_REG); + twl4030_i2c_read_u8(TWL4030_CHIP_KEYPAD, &r, KEYPAD_KBR_REG); + for (rb = 0; rb < 8; rb++) { + if (!(r & (1 << rb))) { + if (!ret) + *key1 = cb << 3 | rb; + else if (1 == ret) + *key2 = cb << 3 | rb; + ret++; + } + } + } + return ret; +} + +#endif + +/* USB */ + +#if (defined(CONFIG_TWL4030_USB) && (CONFIG_TWL4030_USB)) + +static int twl4030_usb_write(u8 address, u8 data) +{ + int ret = 0; + ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, data, address); + if (ret != 0) + printf("TWL4030:USB:Write[0x%x] Error %d\n", address, ret); + + return ret; +} + +static int twl4030_usb_read(u8 address) +{ + u8 data; + int ret = 0; + ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &data, address); + if (ret == 0) + ret = data; + else + printf("TWL4030:USB:Read[0x%x] Error %d\n", address, ret); + + return ret; +} + +static int twl4030_usb_set_bits(u8 reg, u8 bits) +{ + return twl4030_usb_write(reg + 1, bits); +} + +static int twl4030_usb_clear_bits(u8 reg, u8 bits) +{ + return twl4030_usb_write(reg + 2, bits); +} + +static void twl4030_usb_ldo_init(void) +{ + /* Enable writing to power configuration registers */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0xC0, PM_MASTER_PROTECT_KEY); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x0C, PM_MASTER_PROTECT_KEY); + + /* put VUSB3V1 LDO in active state */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, PM_RECEIVER_VUSB_DEDICATED2); + + /* input to VUSB3V1 LDO is from VBAT, not VBUS */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x14, PM_RECEIVER_VUSB_DEDICATED1); + + /* turn on 3.1V regulator */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, PM_RECEIVER_VUSB3V1_DEV_GRP); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, PM_RECEIVER_VUSB3V1_TYPE); + + /* turn on 1.5V regulator */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, PM_RECEIVER_VUSB1V5_DEV_GRP); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, PM_RECEIVER_VUSB1V5_TYPE); + + /* turn on 1.8V regulator */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, PM_RECEIVER_VUSB1V8_DEV_GRP); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, PM_RECEIVER_VUSB1V8_TYPE); + + /* disable access to power configuration registers */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x00, PM_MASTER_PROTECT_KEY); +} + +static void twl4030_phy_power(void) +{ + u8 pwr; + + pwr = twl4030_usb_read(USB_PHY_PWR_CTRL); + pwr &= ~USB_PHYPWD; + twl4030_usb_write(USB_PHY_PWR_CTRL, pwr); + twl4030_usb_write(USB_PHY_CLK_CTRL, twl4030_usb_read(USB_PHY_CLK_CTRL) | + (USB_CLOCKGATING_EN | USB_CLK32K_EN)); +} + +int twl4030_usb_init(void) +{ + unsigned long timeout; + + /* twl4030 ldo init */ + twl4030_usb_ldo_init(); + + /* Enable the twl4030 phy */ + twl4030_phy_power(); + + /* enable DPLL to access PHY registers over I2C */ + twl4030_usb_write(USB_PHY_CLK_CTRL, twl4030_usb_read(USB_PHY_CLK_CTRL) | + USB_REQ_PHY_DPLL_CLK); + timeout = 1000 * 1000; /* 1 sec */ + while (!(twl4030_usb_read(USB_PHY_CLK_CTRL_STS) & USB_PHY_DPLL_CLK) && + 0 < timeout) { + udelay(10); + timeout -= 10; + } + if (!(twl4030_usb_read(USB_PHY_CLK_CTRL_STS) & USB_PHY_DPLL_CLK)) { + printf("Timeout setting T2 HSUSB PHY DPLL clock\n"); + return -1; + } + + /* Enable ULPI mode */ + twl4030_usb_clear_bits(USB_IFC_CTRL, USB_CARKITMODE); + twl4030_usb_set_bits(USB_POWER_CTRL, USB_OTG_ENAB); + twl4030_usb_clear_bits(USB_FUNC_CTRL, USB_XCVRSELECT_MASK | USB_OPMODE_MASK); + /* let ULPI control the DPLL clock */ + twl4030_usb_write(USB_PHY_CLK_CTRL, twl4030_usb_read(USB_PHY_CLK_CTRL) & + ~USB_REQ_PHY_DPLL_CLK); + return 0; +} + +#endif + +/* + * Power Reset + */ +void twl4030_power_reset_init(void) +{ +#ifdef CONFIG_3430ZOOM2 + clear_n_set(TWL4030_CHIP_PM_MASTER, 0, SW_EVENTS_STOPON_PWRON, + PM_MASTER_P1_SW_EVENTS); +#endif +} + +#ifdef CONFIG_CMD_VOLTAGE + +/* Override the weakly defined voltage_info function */ +void voltage_info (void) +{ + u8 vdd1_dev_grp, vdd1_type, vdd1_remap, vdd1_cfg, vdd1_misc_cfg; + u8 vdd1_test1, vdd1_test2, vdd1_osc, vdd1_vsel, vdd1_vmode_cfg; + u8 vdd1_vfloor, vdd1_vroof, vdd1_step; + u8 vdd2_dev_grp, vdd2_type, vdd2_remap, vdd2_cfg, vdd2_misc_cfg; + u8 vdd2_test1, vdd2_test2, vdd2_osc, vdd2_vsel, vdd2_vmode_cfg; + u8 vdd2_vfloor, vdd2_vroof, vdd2_step; + unsigned int vdd1 = 0; + unsigned int vdd2 = 0; + /* Units are in micro volts */ + unsigned int base = 600000; + unsigned int scale = 12500; + + /* VDD1 */ + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_dev_grp, + PM_RECEIVER_VDD1_DEV_GRP); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_type, + PM_RECEIVER_VDD1_TYPE); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_remap, + PM_RECEIVER_VDD1_REMAP); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_cfg, + PM_RECEIVER_VDD1_CFG); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_misc_cfg, + PM_RECEIVER_VDD1_MISC_CFG); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_test1, + PM_RECEIVER_VDD1_TEST1); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_test2, + PM_RECEIVER_VDD1_TEST2); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_osc, + PM_RECEIVER_VDD1_OSC); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_vsel, + PM_RECEIVER_VDD1_VSEL); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_vmode_cfg, + PM_RECEIVER_VDD1_VMODE_CFG); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_vfloor, + PM_RECEIVER_VDD1_VFLOOR); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_vroof, + PM_RECEIVER_VDD1_VROOF); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd1_step, + PM_RECEIVER_VDD1_STEP); + + printf("VDD1 Regs\n"); + printf("\tDEV_GRP 0x%x\n", vdd1_dev_grp); + printf("\tTYPE 0x%x\n", vdd1_type); + printf("\tREMAP 0x%x\n", vdd1_remap); + printf("\tCFG 0x%x\n", vdd1_cfg); + printf("\tMISC_CFG 0x%x\n", vdd1_misc_cfg); + printf("\tTEST1 0x%x\n", vdd1_test1); + printf("\tTEST2 0x%x\n", vdd1_test2); + printf("\tOSC 0x%x\n", vdd1_osc); + printf("\tVSEL 0x%x\n", vdd1_vsel); + printf("\tVMODE_CFG 0x%x\n", vdd1_vmode_cfg); + printf("\tVFLOOR 0x%x\n", vdd1_vfloor); + printf("\tVROOF 0x%x\n", vdd1_vroof); + printf("\tSTEP 0x%x\n", vdd1_step); + + /* VDD2 */ + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_dev_grp, + PM_RECEIVER_VDD2_DEV_GRP); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_type, + PM_RECEIVER_VDD2_TYPE); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_remap, + PM_RECEIVER_VDD2_REMAP); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_cfg, + PM_RECEIVER_VDD2_CFG); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_misc_cfg, + PM_RECEIVER_VDD2_MISC_CFG); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_test1, + PM_RECEIVER_VDD2_TEST1); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_test2, + PM_RECEIVER_VDD2_TEST2); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_osc, + PM_RECEIVER_VDD2_OSC); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_vsel, + PM_RECEIVER_VDD2_VSEL); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_vmode_cfg, + PM_RECEIVER_VDD2_VMODE_CFG); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_vfloor, + PM_RECEIVER_VDD2_VFLOOR); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_vroof, + PM_RECEIVER_VDD2_VROOF); + twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER, &vdd2_step, + PM_RECEIVER_VDD2_STEP); + + printf("VDD2 Regs\n"); + printf("\tDEV_GRP 0x%x\n", vdd2_dev_grp); + printf("\tTYPE 0x%x\n", vdd2_type); + printf("\tREMAP 0x%x\n", vdd2_remap); + printf("\tCFG 0x%x\n", vdd2_cfg); + printf("\tMISC_CFG 0x%x\n", vdd2_misc_cfg); + printf("\tTEST1 0x%x\n", vdd2_test1); + printf("\tTEST2 0x%x\n", vdd2_test2); + printf("\tOSC 0x%x\n", vdd2_osc); + printf("\tVSEL 0x%x\n", vdd2_vsel); + printf("\tVMODE_CFG 0x%x\n", vdd2_vmode_cfg); + printf("\tVFLOOR 0x%x\n", vdd2_vfloor); + printf("\tVROOF 0x%x\n", vdd2_vroof); + printf("\tSTEP 0x%x\n", vdd2_step); + + /* Calculated the voltages */ + printf("\n"); + if (!(vdd1_cfg & 1)) + { + /* voltage controled by vsel */ + vdd1 = scale * vdd1_vsel + base; + printf("VDD1 calculated to be "); + if (!(vdd1 % 1000)) { + printf("%d mV\n", vdd1 / 1000); + } else { + printf("%d uV\n", vdd1); + } + } else { + printf("VDD1 calculation unsupport for this mode\n"); + } + + if (!(vdd2_cfg & 1)) + { + /* voltage controled by vsel */ + vdd2 = scale * vdd2_vsel + base; + printf("VDD2 calculated to be "); + if (!(vdd2 % 1000)) { + printf("%d mV\n", vdd2 / 1000); + } else { + printf("%d uV\n", vdd2); + } + } else { + printf("VDD2 calculation unsupport for this mode\n"); + } +} + + +#endif diff --git a/drivers/usbdcore.c b/drivers/usbdcore.c new file mode 100644 index 000000000..308c7cecc --- /dev/null +++ b/drivers/usbdcore.c @@ -0,0 +1,684 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usbd/usbd.c.c - USB Device Core Layer + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include +#include "usbdcore.h" + +#define MAX_INTERFACES 2 + + +int maxstrings = 20; + +/* Global variables ************************************************************************** */ + +struct usb_string_descriptor **usb_strings; + +int usb_devices; + +extern struct usb_function_driver ep0_driver; + +int registered_functions; +int registered_devices; + +char *usbd_device_events[] = { + "DEVICE_UNKNOWN", + "DEVICE_INIT", + "DEVICE_CREATE", + "DEVICE_HUB_CONFIGURED", + "DEVICE_RESET", + "DEVICE_ADDRESS_ASSIGNED", + "DEVICE_CONFIGURED", + "DEVICE_SET_INTERFACE", + "DEVICE_SET_FEATURE", + "DEVICE_CLEAR_FEATURE", + "DEVICE_DE_CONFIGURED", + "DEVICE_BUS_INACTIVE", + "DEVICE_BUS_ACTIVITY", + "DEVICE_POWER_INTERRUPTION", + "DEVICE_HUB_RESET", + "DEVICE_DESTROY", + "DEVICE_FUNCTION_PRIVATE", +}; + +char *usbd_device_states[] = { + "STATE_INIT", + "STATE_CREATED", + "STATE_ATTACHED", + "STATE_POWERED", + "STATE_DEFAULT", + "STATE_ADDRESSED", + "STATE_CONFIGURED", + "STATE_UNKNOWN", +}; + +char *usbd_device_requests[] = { + "GET STATUS", /* 0 */ + "CLEAR FEATURE", /* 1 */ + "RESERVED", /* 2 */ + "SET FEATURE", /* 3 */ + "RESERVED", /* 4 */ + "SET ADDRESS", /* 5 */ + "GET DESCRIPTOR", /* 6 */ + "SET DESCRIPTOR", /* 7 */ + "GET CONFIGURATION", /* 8 */ + "SET CONFIGURATION", /* 9 */ + "GET INTERFACE", /* 10 */ + "SET INTERFACE", /* 11 */ + "SYNC FRAME", /* 12 */ +}; + +char *usbd_device_descriptors[] = { + "UNKNOWN", /* 0 */ + "DEVICE", /* 1 */ + "CONFIG", /* 2 */ + "STRING", /* 3 */ + "INTERFACE", /* 4 */ + "ENDPOINT", /* 5 */ + "DEVICE QUALIFIER", /* 6 */ + "OTHER SPEED", /* 7 */ + "INTERFACE POWER", /* 8 */ +}; + +char *usbd_device_status[] = { + "USBD_OPENING", + "USBD_OK", + "USBD_SUSPENDED", + "USBD_CLOSING", +}; + + +/* Descriptor support functions ************************************************************** */ + + +/** + * usbd_get_string - find and return a string descriptor + * @index: string index to return + * + * Find an indexed string and return a pointer to a it. + */ +struct usb_string_descriptor *usbd_get_string (__u8 index) +{ + if (index >= maxstrings) { + return NULL; + } + return usb_strings[index]; +} + + +/* Access to device descriptor functions ***************************************************** */ + + +/* * + * usbd_device_configuration_instance - find a configuration instance for this device + * @device: + * @configuration: index to configuration, 0 - N-1 + * + * Get specifed device configuration. Index should be bConfigurationValue-1. + */ +static struct usb_configuration_instance *usbd_device_configuration_instance (struct usb_device_instance *device, + unsigned int port, unsigned int configuration) +{ + /* XXX */ + configuration = configuration ? configuration - 1 : 0; + + if (configuration >= device->configurations) { + return NULL; + } + return device->configuration_instance_array + configuration; +} + + +/* * + * usbd_device_interface_instance + * @device: + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * + * Return the specified interface descriptor for the specified device. + */ +struct usb_interface_instance *usbd_device_interface_instance (struct usb_device_instance *device, int port, int configuration, int interface) +{ + struct usb_configuration_instance *configuration_instance; + + if ((configuration_instance = usbd_device_configuration_instance (device, port, configuration)) == NULL) { + return NULL; + } + if (interface >= configuration_instance->interfaces) { + return NULL; + } + return configuration_instance->interface_instance_array + interface; +} + +/* * + * usbd_device_alternate_descriptor_list + * @device: + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: alternate setting + * + * Return the specified alternate descriptor for the specified device. + */ +struct usb_alternate_instance *usbd_device_alternate_instance (struct usb_device_instance *device, int port, int configuration, int interface, int alternate) +{ + struct usb_interface_instance *interface_instance; + + if ((interface_instance = usbd_device_interface_instance (device, port, configuration, interface)) == NULL) { + return NULL; + } + + if (alternate >= interface_instance->alternates) { + return NULL; + } + + return interface_instance->alternates_instance_array + alternate; +} + + +/* * + * usbd_device_device_descriptor + * @device: which device + * @configuration: index to configuration, 0 - N-1 + * @port: which port + * + * Return the specified configuration descriptor for the specified device. + */ +struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_instance *device, int port) +{ + return (device->device_descriptor); +} + + +/** + * usbd_device_configuration_descriptor + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * + * Return the specified configuration descriptor for the specified device. + */ +struct usb_configuration_descriptor *usbd_device_configuration_descriptor (struct + usb_device_instance + *device, int port, int configuration) +{ + struct usb_configuration_instance *configuration_instance; + if (!(configuration_instance = usbd_device_configuration_instance (device, port, configuration))) { + return NULL; + } + return (configuration_instance->configuration_descriptor); +} + + +/** + * usbd_device_interface_descriptor + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: alternate setting + * + * Return the specified interface descriptor for the specified device. + */ +struct usb_interface_descriptor *usbd_device_interface_descriptor (struct usb_device_instance + *device, int port, int configuration, int interface, int alternate) +{ + struct usb_interface_instance *interface_instance; + if (!(interface_instance = usbd_device_interface_instance (device, port, configuration, interface))) { + return NULL; + } + if ((alternate < 0) || (alternate >= interface_instance->alternates)) { + return NULL; + } + return (interface_instance->alternates_instance_array[alternate].interface_descriptor); +} + +/** + * usbd_device_endpoint_descriptor_index + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: index setting + * @index: which index + * + * Return the specified endpoint descriptor for the specified device. + */ +struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor_index (struct usb_device_instance + *device, int port, int configuration, int interface, int alternate, int index) +{ + struct usb_alternate_instance *alternate_instance; + + if (!(alternate_instance = usbd_device_alternate_instance (device, port, configuration, interface, alternate))) { + return NULL; + } + if (index >= alternate_instance->endpoints) { + return NULL; + } + return *(alternate_instance->endpoints_descriptor_array + index); +} + + +/** + * usbd_device_endpoint_transfersize + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @index: which index + * + * Return the specified endpoint transfer size; + */ +int usbd_device_endpoint_transfersize (struct usb_device_instance *device, int port, int configuration, int interface, int alternate, int index) +{ + struct usb_alternate_instance *alternate_instance; + + if (!(alternate_instance = usbd_device_alternate_instance (device, port, configuration, interface, alternate))) { + return 0; + } + if (index >= alternate_instance->endpoints) { + return 0; + } + return *(alternate_instance->endpoint_transfersize_array + index); +} + + +/** + * usbd_device_endpoint_descriptor + * @device: which device + * @port: which port + * @configuration: index to configuration, 0 - N-1 + * @interface: index to interface + * @alternate: alternate setting + * @endpoint: which endpoint + * + * Return the specified endpoint descriptor for the specified device. + */ +struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *device, int port, int configuration, int interface, int alternate, int endpoint) +{ + struct usb_endpoint_descriptor *endpoint_descriptor; + int i; + + for (i = 0; !(endpoint_descriptor = usbd_device_endpoint_descriptor_index (device, port, configuration, interface, alternate, i)); i++) { + if (endpoint_descriptor->bEndpointAddress == endpoint) { + return endpoint_descriptor; + } + } + return NULL; +} + +/** + * usbd_endpoint_halted + * @device: point to struct usb_device_instance + * @endpoint: endpoint to check + * + * Return non-zero if endpoint is halted. + */ +int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint) +{ + return (device->status == USB_STATUS_HALT); +} + + +/** + * usbd_rcv_complete - complete a receive + * @endpoint: + * @len: + * @urb_bad: + * + * Called from rcv interrupt to complete. + */ +void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad) +{ + if (endpoint) { + struct urb *rcv_urb; + + /*usbdbg("len: %d urb: %p\n", len, endpoint->rcv_urb); */ + + /* if we had an urb then update actual_length, dispatch if neccessary */ + if ((rcv_urb = endpoint->rcv_urb)) { + + /*usbdbg("actual: %d buffer: %d\n", */ + /*rcv_urb->actual_length, rcv_urb->buffer_length); */ + + /* check the urb is ok, are we adding data less than the packetsize */ + if (!urb_bad && (len <= endpoint->rcv_packetSize)) { + /*usbdbg("updating actual_length by %d\n",len); */ + + /* increment the received data size */ + rcv_urb->actual_length += len; + + } else { + usberr(" RECV_ERROR actual: %d buffer: %d urb_bad: %d\n", + rcv_urb->actual_length, rcv_urb->buffer_length, urb_bad); + + rcv_urb->actual_length = 0; + rcv_urb->status = RECV_ERROR; + } + } else { + usberr("no rcv_urb!"); + } + } else { + usberr("no endpoint!"); + } + +} + +/** + * usbd_tx_complete - complete a transmit + * @endpoint: + * @resetart: + * + * Called from tx interrupt to complete. + */ +void usbd_tx_complete (struct usb_endpoint_instance *endpoint) +{ + if (endpoint) { + struct urb *tx_urb; + + /* if we have a tx_urb advance or reset, finish if complete */ + if ((tx_urb = endpoint->tx_urb)) { + int sent = endpoint->last; + endpoint->sent += sent; + endpoint->last -= sent; + + if( (endpoint->tx_urb->actual_length - endpoint->sent) <= 0 ) { + tx_urb->actual_length = 0; + endpoint->sent = 0; + endpoint->last = 0; + + /* Remove from active, save for re-use */ + urb_detach(tx_urb); + urb_append(&endpoint->done, tx_urb); + /*usbdbg("done->next %p, tx_urb %p, done %p", */ + /* endpoint->done.next, tx_urb, &endpoint->done); */ + + endpoint->tx_urb = first_urb_detached(&endpoint->tx); + if( endpoint->tx_urb ) { + endpoint->tx_queue--; + usbdbg("got urb from tx list"); + } + if( !endpoint->tx_urb ) { + /*usbdbg("taking urb from done list"); */ + endpoint->tx_urb = first_urb_detached(&endpoint->done); + } + if( !endpoint->tx_urb ) { + usbdbg("allocating new urb for tx_urb"); + endpoint->tx_urb = usbd_alloc_urb(tx_urb->device, endpoint); + } + } + } + } +} + +/* URB linked list functions ***************************************************** */ + +/* + * Initialize an urb_link to be a single element list. + * If the urb_link is being used as a distinguished list head + * the list is empty when the head is the only link in the list. + */ +void urb_link_init (urb_link * ul) +{ + if (ul) { + ul->prev = ul->next = ul; + } +} + +/* + * Detach an urb_link from a list, and set it + * up as a single element list, so no dangling + * pointers can be followed, and so it can be + * joined to another list if so desired. + */ +void urb_detach (struct urb *urb) +{ + if (urb) { + urb_link *ul = &urb->link; + ul->next->prev = ul->prev; + ul->prev->next = ul->next; + urb_link_init (ul); + } +} + +/* + * Return the first urb_link in a list with a distinguished + * head "hd", or NULL if the list is empty. This will also + * work as a predicate, returning NULL if empty, and non-NULL + * otherwise. + */ +urb_link *first_urb_link (urb_link * hd) +{ + urb_link *nx; + if (NULL != hd && NULL != (nx = hd->next) && nx != hd) { + /* There is at least one element in the list */ + /* (besides the distinguished head). */ + return (nx); + } + /* The list is empty */ + return (NULL); +} + +/* + * Return the first urb in a list with a distinguished + * head "hd", or NULL if the list is empty. + */ +struct urb *first_urb (urb_link * hd) +{ + urb_link *nx; + if (NULL == (nx = first_urb_link (hd))) { + /* The list is empty */ + return (NULL); + } + return (p2surround (struct urb, link, nx)); +} + +/* + * Detach and return the first urb in a list with a distinguished + * head "hd", or NULL if the list is empty. + * + */ +struct urb *first_urb_detached (urb_link * hd) +{ + struct urb *urb; + if ((urb = first_urb (hd))) { + urb_detach (urb); + } + return urb; +} + + +/* + * Append an urb_link (or a whole list of + * urb_links) to the tail of another list + * of urb_links. + */ +void urb_append (urb_link * hd, struct urb *urb) +{ + if (hd && urb) { + urb_link *new = &urb->link; + + /* This allows the new urb to be a list of urbs, */ + /* with new pointing at the first, but the link */ + /* must be initialized. */ + /* Order is important here... */ + urb_link *pul = hd->prev; + new->prev->next = hd; + hd->prev = new->prev; + new->prev = pul; + pul->next = new; + } +} + +/* URB create/destroy functions ***************************************************** */ + +/** + * usbd_alloc_urb - allocate an URB appropriate for specified endpoint + * @device: device instance + * @endpoint: endpoint + * + * Allocate an urb structure. The usb device urb structure is used to + * contain all data associated with a transfer, including a setup packet for + * control transfers. + * + * NOTE: endpoint_address MUST contain a direction flag. + */ +struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint) +{ + struct urb *urb; + + if( !(urb = (struct urb*)malloc(sizeof(struct urb))) ) { + usberr(" F A T A L: malloc(%u) FAILED!!!!", sizeof(struct urb)); + return NULL; + } + + /* Fill in known fields */ + memset(urb, 0, sizeof(struct urb)); + urb->endpoint = endpoint; + urb->device = device; + urb->buffer = (u8*)urb->buffer_data; + urb->buffer_length = sizeof(urb->buffer_data); + + urb_link_init (&urb->link); + + return urb; +} + +/** + * usbd_dealloc_urb - deallocate an URB and associated buffer + * @urb: pointer to an urb structure + * + * Deallocate an urb structure and associated data. + */ +void usbd_dealloc_urb (struct urb *urb) +{ + if (urb) { + free (urb); + } +} + +/* Event signaling functions ***************************************************** */ + +/** + * usbd_device_event - called to respond to various usb events + * @device: pointer to struct device + * @event: event to respond to + * + * Used by a Bus driver to indicate an event. + */ +void usbd_device_event_irq (struct usb_device_instance *device, usb_device_event_t event, int data) +{ + usb_device_state_t state; + + if (!device || !device->bus) { + usberr("(%p,%d) NULL device or device->bus", device, event); + return; + } + + state = device->device_state; + + usbinfo("%s", usbd_device_events[event]); + + switch (event) { + case DEVICE_UNKNOWN: + break; + case DEVICE_INIT: + device->device_state = STATE_INIT; + break; + + case DEVICE_CREATE: + device->device_state = STATE_ATTACHED; + break; + + case DEVICE_HUB_CONFIGURED: + device->device_state = STATE_POWERED; + break; + + case DEVICE_RESET: + device->device_state = STATE_DEFAULT; + device->address = 0; + break; + + case DEVICE_ADDRESS_ASSIGNED: + device->device_state = STATE_ADDRESSED; + break; + + case DEVICE_CONFIGURED: + device->device_state = STATE_CONFIGURED; + break; + + case DEVICE_DE_CONFIGURED: + device->device_state = STATE_ADDRESSED; + break; + + case DEVICE_BUS_INACTIVE: + if (device->status != USBD_CLOSING) { + device->status = USBD_SUSPENDED; + } + break; + case DEVICE_BUS_ACTIVITY: + if (device->status != USBD_CLOSING) { + device->status = USBD_OK; + } + break; + + case DEVICE_SET_INTERFACE: + break; + case DEVICE_SET_FEATURE: + break; + case DEVICE_CLEAR_FEATURE: + break; + + case DEVICE_POWER_INTERRUPTION: + device->device_state = STATE_POWERED; + break; + case DEVICE_HUB_RESET: + device->device_state = STATE_ATTACHED; + break; + case DEVICE_DESTROY: + device->device_state = STATE_UNKNOWN; + break; + + case DEVICE_FUNCTION_PRIVATE: + break; + + default: + usbdbg("event %d - not handled",event); + break; + } + /*usbdbg("%s event: %d oldstate: %d newstate: %d status: %d address: %d", + device->name, event, state, + device->device_state, device->status, device->address); */ + + /* tell the bus interface driver */ + if( device->event ) { + /* usbdbg("calling device->event"); */ + device->event(device, event, data); + } +} diff --git a/drivers/usbdcore_ep0.c b/drivers/usbdcore_ep0.c new file mode 100644 index 000000000..260befe97 --- /dev/null +++ b/drivers/usbdcore_ep0.c @@ -0,0 +1,686 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usbd/ep0.c + * + * Copyright (c) 2000, 2001, 2002 Lineo + * Copyright (c) 2001 Hewlett Packard + * + * By: + * Stuart Lynne , + * Tom Rushworth , + * Bruce Balden + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +/* + * This is the builtin ep0 control function. It implements all required functionality + * for responding to control requests (SETUP packets). + * + * XXX + * + * Currently we do not pass any SETUP packets (or other) to the configured + * function driver. This may need to change. + * + * XXX + */ + +#include + +#if defined(CONFIG_OMAP1510) && defined(CONFIG_USB_DEVICE) +#include "usbdcore.h" + +#if 0 +#define dbg_ep0(lvl,fmt,args...) serial_printf("[%s] %s:%d: "fmt"\n",__FILE__,__FUNCTION__,__LINE__,##args) +#else +#define dbg_ep0(lvl,fmt,args...) +#endif + +/* EP0 Configuration Set ********************************************************************* */ + + +/** + * ep0_get_status - fill in URB data with appropriate status + * @device: + * @urb: + * @index: + * @requesttype: + * + */ +static int ep0_get_status (struct usb_device_instance *device, + struct urb *urb, int index, int requesttype) +{ + char *cp; + + urb->actual_length = 2; + cp = urb->buffer; + cp[0] = cp[1] = 0; + + switch (requesttype) { + case USB_REQ_RECIPIENT_DEVICE: + cp[0] = USB_STATUS_SELFPOWERED; + break; + case USB_REQ_RECIPIENT_INTERFACE: + break; + case USB_REQ_RECIPIENT_ENDPOINT: + cp[0] = usbd_endpoint_halted (device, index); + break; + case USB_REQ_RECIPIENT_OTHER: + urb->actual_length = 0; + default: + break; + } + dbg_ep0 (2, "%02x %02x", cp[0], cp[1]); + return 0; +} + +/** + * ep0_get_one + * @device: + * @urb: + * @result: + * + * Set a single byte value in the urb send buffer. Return non-zero to signal + * a request error. + */ +static int ep0_get_one (struct usb_device_instance *device, struct urb *urb, + __u8 result) +{ + urb->actual_length = 1; /* XXX 2? */ + ((char *) urb->buffer)[0] = result; + return 0; +} + +/** + * copy_config + * @urb: pointer to urb + * @data: pointer to configuration data + * @length: length of data + * + * Copy configuration data to urb transfer buffer if there is room for it. + */ +static void copy_config (struct urb *urb, void *data, int max_length, + int max_buf) +{ + int available; + int length; + + /*dbg_ep0(3, "-> actual: %d buf: %d max_buf: %d max_length: %d data: %p", */ + /* urb->actual_length, urb->buffer_length, max_buf, max_length, data); */ + + if (!data) { + dbg_ep0 (1, "data is NULL"); + return; + } + if (!(length = *(unsigned char *) data)) { + dbg_ep0 (1, "length is zero"); + return; + } + + if (length > max_length) { + dbg_ep0 (1, "length: %d >= max_length: %d", length, + max_length); + return; + } + /*dbg_ep0(1, " actual: %d buf: %d max_buf: %d max_length: %d length: %d", */ + /* urb->actual_length, urb->buffer_length, max_buf, max_length, length); */ + + if ((available = + /*urb->buffer_length */ max_buf - urb->actual_length) <= 0) { + return; + } + /*dbg_ep0(1, "actual: %d buf: %d max_buf: %d length: %d available: %d", */ + /* urb->actual_length, urb->buffer_length, max_buf, length, available); */ + + if (length > available) { + length = available; + } + /*dbg_ep0(1, "actual: %d buf: %d max_buf: %d length: %d available: %d", */ + /* urb->actual_length, urb->buffer_length, max_buf, length, available); */ + + memcpy (urb->buffer + urb->actual_length, data, length); + urb->actual_length += length; + + dbg_ep0 (3, + "copy_config: <- actual: %d buf: %d max_buf: %d max_length: %d available: %d", + urb->actual_length, urb->buffer_length, max_buf, max_length, + available); +} + +/** + * ep0_get_descriptor + * @device: + * @urb: + * @max: + * @descriptor_type: + * @index: + * + * Called by ep0_rx_process for a get descriptor device command. Determine what + * descriptor is being requested, copy to send buffer. Return zero if ok to send, + * return non-zero to signal a request error. + */ +static int ep0_get_descriptor (struct usb_device_instance *device, + struct urb *urb, int max, int descriptor_type, + int index) +{ + int port = 0; /* XXX compound device */ + char *cp; + + /*dbg_ep0(3, "max: %x type: %x index: %x", max, descriptor_type, index); */ + + if (!urb || !urb->buffer || !urb->buffer_length + || (urb->buffer_length < 255)) { + dbg_ep0 (2, "invalid urb %p", urb); + return -1L; + } + + /* setup tx urb */ + urb->actual_length = 0; + cp = urb->buffer; + + dbg_ep0 (2, "%s", USBD_DEVICE_DESCRIPTORS (descriptor_type)); + + switch (descriptor_type) { + case USB_DESCRIPTOR_TYPE_DEVICE: + { + struct usb_device_descriptor *device_descriptor; + + if (! + (device_descriptor = + usbd_device_device_descriptor (device, port))) { + return -1; + } + /* copy descriptor for this device */ + copy_config (urb, device_descriptor, + sizeof (struct usb_device_descriptor), + max); + + /* correct the correct control endpoint 0 max packet size into the descriptor */ + device_descriptor = + (struct usb_device_descriptor *) urb->buffer; + device_descriptor->bMaxPacketSize0 = + urb->device->bus->maxpacketsize; + + } + /*dbg_ep0(3, "copied device configuration, actual_length: %x", urb->actual_length); */ + break; + + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + { + int bNumInterface; + struct usb_configuration_descriptor + *configuration_descriptor; + struct usb_device_descriptor *device_descriptor; + + if (! + (device_descriptor = + usbd_device_device_descriptor (device, port))) { + return -1; + } + /*dbg_ep0(2, "%d %d", index, device_descriptor->bNumConfigurations); */ + if (index > device_descriptor->bNumConfigurations) { + dbg_ep0 (0, "index too large: %d > %d", index, + device_descriptor-> + bNumConfigurations); + return -1; + } + + if (! + (configuration_descriptor = + usbd_device_configuration_descriptor (device, + port, + index))) { + dbg_ep0 (0, + "usbd_device_configuration_descriptor failed: %d", + index); + return -1; + } + copy_config (urb, configuration_descriptor, + sizeof (struct + usb_configuration_descriptor), + max); + + + /* iterate across interfaces for specified configuration */ + dbg_ep0 (0, "bNumInterfaces: %d", + configuration_descriptor->bNumInterfaces); + for (bNumInterface = 0; + bNumInterface < + configuration_descriptor->bNumInterfaces; + bNumInterface++) { + + int bAlternateSetting; + struct usb_interface_instance + *interface_instance; + + dbg_ep0 (3, "[%d] bNumInterfaces: %d", + bNumInterface, + configuration_descriptor->bNumInterfaces); + + if (! (interface_instance = usbd_device_interface_instance (device, + port, index, bNumInterface))) + { + dbg_ep0 (3, "[%d] interface_instance NULL", + bNumInterface); + return -1; + } + /* iterate across interface alternates */ + for (bAlternateSetting = 0; + bAlternateSetting < interface_instance->alternates; + bAlternateSetting++) { + /*int class; */ + int bNumEndpoint; + struct usb_interface_descriptor *interface_descriptor; + + struct usb_alternate_instance *alternate_instance; + + dbg_ep0 (3, "[%d:%d] alternates: %d", + bNumInterface, + bAlternateSetting, + interface_instance->alternates); + + if (! (alternate_instance = usbd_device_alternate_instance (device, port, index, bNumInterface, bAlternateSetting))) { + dbg_ep0 (3, "[%d] alternate_instance NULL", + bNumInterface); + return -1; + } + /* copy descriptor for this interface */ + copy_config (urb, alternate_instance->interface_descriptor, + sizeof (struct usb_interface_descriptor), + max); + + /*dbg_ep0(3, "[%d:%d] classes: %d endpoints: %d", bNumInterface, bAlternateSetting, */ + /* alternate_instance->classes, alternate_instance->endpoints); */ + + /* iterate across classes for this alternate interface */ +#if 0 + for (class = 0; + class < alternate_instance->classes; + class++) { + struct usb_class_descriptor *class_descriptor; + /*dbg_ep0(3, "[%d:%d:%d] classes: %d", bNumInterface, bAlternateSetting, */ + /* class, alternate_instance->classes); */ + if (!(class_descriptor = usbd_device_class_descriptor_index (device, port, index, bNumInterface, bAlternateSetting, class))) { + dbg_ep0 (3, "[%d] class NULL", + class); + return -1; + } + /* copy descriptor for this class */ + copy_config (urb, class_descriptor, + sizeof (struct usb_class_descriptor), + max); + } +#endif + + /* iterate across endpoints for this alternate interface */ + interface_descriptor = alternate_instance->interface_descriptor; + for (bNumEndpoint = 0; + bNumEndpoint < alternate_instance->endpoints; + bNumEndpoint++) { + struct usb_endpoint_descriptor *endpoint_descriptor; + dbg_ep0 (3, "[%d:%d:%d] endpoint: %d", + bNumInterface, + bAlternateSetting, + bNumEndpoint, + interface_descriptor-> + bNumEndpoints); + if (!(endpoint_descriptor = usbd_device_endpoint_descriptor_index (device, port, index, bNumInterface, bAlternateSetting, bNumEndpoint))) { + dbg_ep0 (3, "[%d] endpoint NULL", + bNumEndpoint); + return -1; + } + /* copy descriptor for this endpoint */ + copy_config (urb, endpoint_descriptor, + sizeof (struct usb_endpoint_descriptor), + max); + } + } + } + dbg_ep0 (3, "lengths: %d %d", + le16_to_cpu (configuration_descriptor->wTotalLength), + urb->actual_length); + } + break; + + case USB_DESCRIPTOR_TYPE_STRING: + { + struct usb_string_descriptor *string_descriptor; + + if (!(string_descriptor = usbd_get_string (index))) { + return -1; + } + /*dbg_ep0(3, "string_descriptor: %p", string_descriptor); */ + copy_config (urb, string_descriptor, string_descriptor->bLength, max); + } + break; + case USB_DESCRIPTOR_TYPE_INTERFACE: + return -1; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + return -1; + case USB_DESCRIPTOR_TYPE_HID: + { + return -1; /* unsupported at this time */ +#if 0 + int bNumInterface = + le16_to_cpu (urb->device_request.wIndex); + int bAlternateSetting = 0; + int class = 0; + struct usb_class_descriptor *class_descriptor; + + if (!(class_descriptor = + usbd_device_class_descriptor_index (device, + port, 0, + bNumInterface, + bAlternateSetting, + class)) + || class_descriptor->descriptor.hid.bDescriptorType != USB_DT_HID) { + dbg_ep0 (3, "[%d] interface is not HID", + bNumInterface); + return -1; + } + /* copy descriptor for this class */ + copy_config (urb, class_descriptor, + class_descriptor->descriptor.hid.bLength, + max); +#endif + } + break; + case USB_DESCRIPTOR_TYPE_REPORT: + { + return -1; /* unsupported at this time */ +#if 0 + int bNumInterface = + le16_to_cpu (urb->device_request.wIndex); + int bAlternateSetting = 0; + int class = 0; + struct usb_class_report_descriptor *report_descriptor; + + if (!(report_descriptor = + usbd_device_class_report_descriptor_index + (device, port, 0, bNumInterface, + bAlternateSetting, class)) + || report_descriptor->bDescriptorType != + USB_DT_REPORT) { + dbg_ep0 (3, "[%d] descriptor is not REPORT", + bNumInterface); + return -1; + } + /* copy report descriptor for this class */ + /*copy_config(urb, &report_descriptor->bData[0], report_descriptor->wLength, max); */ + if (max - urb->actual_length > 0) { + int length = + MIN (report_descriptor->wLength, + max - urb->actual_length); + memcpy (urb->buffer + urb->actual_length, + &report_descriptor->bData[0], length); + urb->actual_length += length; + } +#endif + } + break; + default: + return -1; + } + + + dbg_ep0 (1, "urb: buffer: %p buffer_length: %2d actual_length: %2d packet size: %2d", + urb->buffer, urb->buffer_length, urb->actual_length, + device->bus->endpoint_array[0].tx_packetSize); +/* + if ((urb->actual_length < max) && !(urb->actual_length % device->bus->endpoint_array[0].tx_packetSize)) { + dbg_ep0(0, "adding null byte"); + urb->buffer[urb->actual_length++] = 0; + dbg_ep0(0, "urb: buffer_length: %2d actual_length: %2d packet size: %2d", + urb->buffer_length, urb->actual_length device->bus->endpoint_array[0].tx_packetSize); + } +*/ + return 0; + +} + +/** + * ep0_recv_setup - called to indicate URB has been received + * @urb: pointer to struct urb + * + * Check if this is a setup packet, process the device request, put results + * back into the urb and return zero or non-zero to indicate success (DATA) + * or failure (STALL). + * + */ +int ep0_recv_setup (struct urb *urb) +{ + /*struct usb_device_request *request = urb->buffer; */ + /*struct usb_device_instance *device = urb->device; */ + + struct usb_device_request *request; + struct usb_device_instance *device; + int address; + + dbg_ep0 (0, "entering ep0_recv_setup()"); + if (!urb || !urb->device) { + dbg_ep0 (3, "invalid URB %p", urb); + return -1; + } + + request = &urb->device_request; + device = urb->device; + + dbg_ep0 (3, "urb: %p device: %p", urb, urb->device); + + + /*dbg_ep0(2, "- - - - - - - - - -"); */ + + dbg_ep0 (2, + "bmRequestType:%02x bRequest:%02x wValue:%04x wIndex:%04x wLength:%04x %s", + request->bmRequestType, request->bRequest, + le16_to_cpu (request->wValue), le16_to_cpu (request->wIndex), + le16_to_cpu (request->wLength), + USBD_DEVICE_REQUESTS (request->bRequest)); + + /* handle USB Standard Request (c.f. USB Spec table 9-2) */ + if ((request->bmRequestType & USB_REQ_TYPE_MASK) != 0) { + dbg_ep0 (1, "non standard request: %x", + request->bmRequestType & USB_REQ_TYPE_MASK); + return -1; /* Stall here */ + } + + switch (device->device_state) { + case STATE_CREATED: + case STATE_ATTACHED: + case STATE_POWERED: + /* It actually is important to allow requests in these states, + * Windows will request descriptors before assigning an + * address to the client. + */ + + /*dbg_ep0 (1, "request %s not allowed in this state: %s", */ + /* USBD_DEVICE_REQUESTS(request->bRequest), */ + /* usbd_device_states[device->device_state]); */ + /*return -1; */ + break; + + case STATE_INIT: + case STATE_DEFAULT: + switch (request->bRequest) { + case USB_REQ_GET_STATUS: + case USB_REQ_GET_INTERFACE: + case USB_REQ_SYNCH_FRAME: /* XXX should never see this (?) */ + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + case USB_REQ_SET_DESCRIPTOR: + /* case USB_REQ_SET_CONFIGURATION: */ + case USB_REQ_SET_INTERFACE: + dbg_ep0 (1, + "request %s not allowed in DEFAULT state: %s", + USBD_DEVICE_REQUESTS (request->bRequest), + usbd_device_states[device->device_state]); + return -1; + + case USB_REQ_SET_CONFIGURATION: + case USB_REQ_SET_ADDRESS: + case USB_REQ_GET_DESCRIPTOR: + case USB_REQ_GET_CONFIGURATION: + break; + } + case STATE_ADDRESSED: + case STATE_CONFIGURED: + break; + case STATE_UNKNOWN: + dbg_ep0 (1, "request %s not allowed in UNKNOWN state: %s", + USBD_DEVICE_REQUESTS (request->bRequest), + usbd_device_states[device->device_state]); + return -1; + } + + /* handle all requests that return data (direction bit set on bm RequestType) */ + if ((request->bmRequestType & USB_REQ_DIRECTION_MASK)) { + + dbg_ep0 (3, "Device-to-Host"); + + switch (request->bRequest) { + + case USB_REQ_GET_STATUS: + return ep0_get_status (device, urb, request->wIndex, + request->bmRequestType & + USB_REQ_RECIPIENT_MASK); + + case USB_REQ_GET_DESCRIPTOR: + return ep0_get_descriptor (device, urb, + le16_to_cpu (request->wLength), + le16_to_cpu (request->wValue) >> 8, + le16_to_cpu (request->wValue) & 0xff); + + case USB_REQ_GET_CONFIGURATION: + return ep0_get_one (device, urb, + device->configuration); + + case USB_REQ_GET_INTERFACE: + return ep0_get_one (device, urb, device->alternate); + + case USB_REQ_SYNCH_FRAME: /* XXX should never see this (?) */ + return -1; + + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + case USB_REQ_SET_ADDRESS: + case USB_REQ_SET_DESCRIPTOR: + case USB_REQ_SET_CONFIGURATION: + case USB_REQ_SET_INTERFACE: + return -1; + } + } + /* handle the requests that do not return data */ + else { + + + /*dbg_ep0(3, "Host-to-Device"); */ + switch (request->bRequest) { + + case USB_REQ_CLEAR_FEATURE: + case USB_REQ_SET_FEATURE: + dbg_ep0 (0, "Host-to-Device"); + switch (request-> + bmRequestType & USB_REQ_RECIPIENT_MASK) { + case USB_REQ_RECIPIENT_DEVICE: + /* XXX DEVICE_REMOTE_WAKEUP or TEST_MODE would be added here */ + /* XXX fall through for now as we do not support either */ + case USB_REQ_RECIPIENT_INTERFACE: + case USB_REQ_RECIPIENT_OTHER: + dbg_ep0 (0, "request %s not", + USBD_DEVICE_REQUESTS (request->bRequest)); + default: + return -1; + + case USB_REQ_RECIPIENT_ENDPOINT: + dbg_ep0 (0, "ENDPOINT: %x", le16_to_cpu (request->wValue)); + if (le16_to_cpu (request->wValue) == USB_ENDPOINT_HALT) { + /*return usbd_device_feature (device, le16_to_cpu (request->wIndex), */ + /* request->bRequest == USB_REQ_SET_FEATURE); */ + /* NEED TO IMPLEMENT THIS!!! */ + return -1; + } else { + dbg_ep0 (1, "request %s bad wValue: %04x", + USBD_DEVICE_REQUESTS + (request->bRequest), + le16_to_cpu (request->wValue)); + return -1; + } + } + + case USB_REQ_SET_ADDRESS: + /* check if this is a re-address, reset first if it is (this shouldn't be possible) */ + if (device->device_state != STATE_DEFAULT) { + dbg_ep0 (1, "set_address: %02x state: %s", + le16_to_cpu (request->wValue), + usbd_device_states[device->device_state]); + return -1; + } + address = le16_to_cpu (request->wValue); + if ((address & 0x7f) != address) { + dbg_ep0 (1, "invalid address %04x %04x", + address, address & 0x7f); + return -1; + } + device->address = address; + + /*dbg_ep0(2, "address: %d %d %d", */ + /* request->wValue, le16_to_cpu(request->wValue), device->address); */ + + serial_printf ("DEVICE_ADDRESS_ASSIGNED.. event?\n"); + return 0; + + case USB_REQ_SET_DESCRIPTOR: /* XXX should we support this? */ + dbg_ep0 (0, "set descriptor: NOT SUPPORTED"); + return -1; + + case USB_REQ_SET_CONFIGURATION: + /* c.f. 9.4.7 - the top half of wValue is reserved */ + /* */ + if ((device->configuration = + le16_to_cpu (request->wValue) & 0x7f) != 0) { + /* c.f. 9.4.7 - zero is the default or addressed state, in our case this */ + /* is the same is configuration zero */ + device->configuration = 0; /* TBR - ?????? */ + } + /* reset interface and alternate settings */ + device->interface = device->alternate = 0; + + /*dbg_ep0(2, "set configuration: %d", device->configuration); */ + /*serial_printf("DEVICE_CONFIGURED.. event?\n"); */ + return 0; + + case USB_REQ_SET_INTERFACE: + device->interface = le16_to_cpu (request->wIndex); + device->alternate = le16_to_cpu (request->wValue); + /*dbg_ep0(2, "set interface: %d alternate: %d", device->interface, device->alternate); */ + serial_printf ("DEVICE_SET_INTERFACE.. event?\n"); + return 0; + + case USB_REQ_GET_STATUS: + case USB_REQ_GET_DESCRIPTOR: + case USB_REQ_GET_CONFIGURATION: + case USB_REQ_GET_INTERFACE: + case USB_REQ_SYNCH_FRAME: /* XXX should never see this (?) */ + return -1; + } + } + return -1; +} + +#endif diff --git a/drivers/usbdcore_omap1510.c b/drivers/usbdcore_omap1510.c new file mode 100644 index 000000000..1d54a6357 --- /dev/null +++ b/drivers/usbdcore_omap1510.c @@ -0,0 +1,1520 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * Based on + * linux/drivers/usb/device/bi/omap.c + * TI OMAP1510 USB bus interface driver + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * (C) Copyright 2002 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#if defined(CONFIG_OMAP1510) && defined(CONFIG_USB_DEVICE) + +#include +#ifdef CONFIG_OMAP_SX1 +#include +#endif + +#include "usbdcore.h" +#include "usbdcore_omap1510.h" +#include "usbdcore_ep0.h" + + +#define UDC_INIT_MDELAY 80 /* Device settle delay */ +#define UDC_MAX_ENDPOINTS 31 /* Number of endpoints on this UDC */ + +/* Some kind of debugging output... */ +#if 1 +#define UDCDBG(str) +#define UDCDBGA(fmt,args...) +#else /* The bugs still exists... */ +#define UDCDBG(str) serial_printf("[%s] %s:%d: " str "\n", __FILE__,__FUNCTION__,__LINE__) +#define UDCDBGA(fmt,args...) serial_printf("[%s] %s:%d: " fmt "\n", __FILE__,__FUNCTION__,__LINE__, ##args) +#endif + +#if 1 +#define UDCREG(name) +#define UDCREGL(name) +#else /* The bugs still exists... */ +#define UDCREG(name) serial_printf("%s():%d: %s[%08x]=%.4x\n",__FUNCTION__,__LINE__, (#name), name, inw(name)) /* For 16-bit regs */ +#define UDCREGL(name) serial_printf("%s():%d: %s[%08x]=%.8x\n",__FUNCTION__,__LINE__, (#name), name, inl(name)) /* For 32-bit regs */ +#endif + + +static struct urb *ep0_urb = NULL; + +static struct usb_device_instance *udc_device; /* Used in interrupt handler */ +static u16 udc_devstat = 0; /* UDC status (DEVSTAT) */ +static u32 udc_interrupts = 0; + +static void udc_stall_ep (unsigned int ep_addr); + + +static struct usb_endpoint_instance *omap1510_find_ep (int ep) +{ + int i; + + for (i = 0; i < udc_device->bus->max_endpoints; i++) { + if (udc_device->bus->endpoint_array[i].endpoint_address == ep) + return &udc_device->bus->endpoint_array[i]; + } + return NULL; +} + +/* ************************************************************************** */ +/* IO + */ + +/* + * omap1510_prepare_endpoint_for_rx + * + * This function implements TRM Figure 14-11. + * + * The endpoint to prepare for transfer is specified as a physical endpoint + * number. For OUT (rx) endpoints 1 through 15, the corresponding endpoint + * configuration register is checked to see if the endpoint is ISO or not. + * If the OUT endpoint is valid and is non-ISO then its FIFO is enabled. + * No action is taken for endpoint 0 or for IN (tx) endpoints 16 through 30. + */ +static void omap1510_prepare_endpoint_for_rx (int ep_addr) +{ + int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + + UDCDBGA ("omap1510_prepare_endpoint %x", ep_addr); + if (((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT)) { + if ((inw (UDC_EP_RX (ep_num)) & + (UDC_EPn_RX_Valid | UDC_EPn_RX_Iso)) == + UDC_EPn_RX_Valid) { + /* rx endpoint is valid, non-ISO, so enable its FIFO */ + outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); + outw (UDC_Set_FIFO_En, UDC_CTRL); + outw (0, UDC_EP_NUM); + } + } +} + +/* omap1510_configure_endpoints + * + * This function implements TRM Figure 14-10. + */ +static void omap1510_configure_endpoints (struct usb_device_instance *device) +{ + int ep; + struct usb_bus_instance *bus; + struct usb_endpoint_instance *endpoint; + unsigned short ep_ptr; + unsigned short ep_size; + unsigned short ep_isoc; + unsigned short ep_doublebuffer; + int ep_addr; + int packet_size; + int buffer_size; + int attributes; + + bus = device->bus; + + /* There is a dedicated 2048 byte buffer for USB packets that may be + * arbitrarily partitioned among the endpoints on 8-byte boundaries. + * The first 8 bytes are reserved for receiving setup packets on + * endpoint 0. + */ + ep_ptr = 8; /* reserve the first 8 bytes for the setup fifo */ + + for (ep = 0; ep < bus->max_endpoints; ep++) { + endpoint = bus->endpoint_array + ep; + ep_addr = endpoint->endpoint_address; + if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* IN endpoint */ + packet_size = endpoint->tx_packetSize; + attributes = endpoint->tx_attributes; + } else { + /* OUT endpoint */ + packet_size = endpoint->rcv_packetSize; + attributes = endpoint->rcv_attributes; + } + + switch (packet_size) { + case 0: + ep_size = 0; + break; + case 8: + ep_size = 0; + break; + case 16: + ep_size = 1; + break; + case 32: + ep_size = 2; + break; + case 64: + ep_size = 3; + break; + case 128: + ep_size = 4; + break; + case 256: + ep_size = 5; + break; + case 512: + ep_size = 6; + break; + default: + UDCDBGA ("ep 0x%02x has bad packet size %d", + ep_addr, packet_size); + packet_size = 0; + ep_size = 0; + break; + } + + switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) { + case USB_ENDPOINT_XFER_CONTROL: + case USB_ENDPOINT_XFER_BULK: + case USB_ENDPOINT_XFER_INT: + default: + /* A non-isochronous endpoint may optionally be + * double-buffered. For now we disable + * double-buffering. + */ + ep_doublebuffer = 0; + ep_isoc = 0; + if (packet_size > 64) + packet_size = 0; + if (!ep || !ep_doublebuffer) + buffer_size = packet_size; + else + buffer_size = packet_size * 2; + break; + case USB_ENDPOINT_XFER_ISOC: + /* Isochronous endpoints are always double- + * buffered, but the double-buffering bit + * in the endpoint configuration register + * becomes the msb of the endpoint size so we + * set the double-buffering flag to zero. + */ + ep_doublebuffer = 0; + ep_isoc = 1; + buffer_size = packet_size * 2; + break; + } + + /* check to see if our packet buffer RAM is exhausted */ + if ((ep_ptr + buffer_size) > 2048) { + UDCDBGA ("out of packet RAM for ep 0x%02x buf size %d", ep_addr, buffer_size); + buffer_size = packet_size = 0; + } + + /* force a default configuration for endpoint 0 since it is + * always enabled + */ + if (!ep && ((packet_size < 8) || (packet_size > 64))) { + buffer_size = packet_size = 64; + ep_size = 3; + } + + if (!ep) { + /* configure endpoint 0 */ + outw ((ep_size << 12) | (ep_ptr >> 3), UDC_EP0); + /*UDCDBGA("ep 0 buffer offset 0x%03x packet size 0x%03x", */ + /* ep_ptr, packet_size); */ + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* IN endpoint */ + if (packet_size) { + outw ((1 << 15) | (ep_doublebuffer << 14) | + (ep_size << 12) | (ep_isoc << 11) | + (ep_ptr >> 3), + UDC_EP_TX (ep_addr & + USB_ENDPOINT_NUMBER_MASK)); + UDCDBGA ("IN ep %d buffer offset 0x%03x" + " packet size 0x%03x", + ep_addr & USB_ENDPOINT_NUMBER_MASK, + ep_ptr, packet_size); + } else { + outw (0, + UDC_EP_TX (ep_addr & + USB_ENDPOINT_NUMBER_MASK)); + } + } else { + /* OUT endpoint */ + if (packet_size) { + outw ((1 << 15) | (ep_doublebuffer << 14) | + (ep_size << 12) | (ep_isoc << 11) | + (ep_ptr >> 3), + UDC_EP_RX (ep_addr & + USB_ENDPOINT_NUMBER_MASK)); + UDCDBGA ("OUT ep %d buffer offset 0x%03x" + " packet size 0x%03x", + ep_addr & USB_ENDPOINT_NUMBER_MASK, + ep_ptr, packet_size); + } else { + outw (0, + UDC_EP_RX (ep_addr & + USB_ENDPOINT_NUMBER_MASK)); + } + } + ep_ptr += buffer_size; + } +} + +/* omap1510_deconfigure_device + * + * This function balances omap1510_configure_device. + */ +static void omap1510_deconfigure_device (void) +{ + int epnum; + + UDCDBG ("clear Cfg_Lock"); + outw (inw (UDC_SYSCON1) & ~UDC_Cfg_Lock, UDC_SYSCON1); + UDCREG (UDC_SYSCON1); + + /* deconfigure all endpoints */ + for (epnum = 1; epnum <= 15; epnum++) { + outw (0, UDC_EP_RX (epnum)); + outw (0, UDC_EP_TX (epnum)); + } +} + +/* omap1510_configure_device + * + * This function implements TRM Figure 14-9. + */ +static void omap1510_configure_device (struct usb_device_instance *device) +{ + omap1510_configure_endpoints (device); + + + /* Figure 14-9 indicates we should enable interrupts here, but we have + * other routines (udc_all_interrupts, udc_suspended_interrupts) to + * do that. + */ + + UDCDBG ("set Cfg_Lock"); + outw (inw (UDC_SYSCON1) | UDC_Cfg_Lock, UDC_SYSCON1); + UDCREG (UDC_SYSCON1); +} + +/* omap1510_write_noniso_tx_fifo + * + * This function implements TRM Figure 14-30. + * + * If the endpoint has an active tx_urb, then the next packet of data from the + * URB is written to the tx FIFO. The total amount of data in the urb is given + * by urb->actual_length. The maximum amount of data that can be sent in any + * one packet is given by endpoint->tx_packetSize. The number of data bytes + * from this URB that have already been transmitted is given by endpoint->sent. + * endpoint->last is updated by this routine with the number of data bytes + * transmitted in this packet. + * + * In accordance with Figure 14-30, the EP_NUM register must already have been + * written with the value to select the appropriate tx FIFO before this routine + * is called. + */ +static void omap1510_write_noniso_tx_fifo (struct usb_endpoint_instance + *endpoint) +{ + struct urb *urb = endpoint->tx_urb; + + if (urb) { + unsigned int last, i; + + UDCDBGA ("urb->buffer %p, buffer_length %d, actual_length %d", + urb->buffer, urb->buffer_length, urb->actual_length); + if ((last = + MIN (urb->actual_length - endpoint->sent, + endpoint->tx_packetSize))) { + u8 *cp = urb->buffer + endpoint->sent; + + UDCDBGA ("endpoint->sent %d, tx_packetSize %d, last %d", endpoint->sent, endpoint->tx_packetSize, last); + + if (((u32) cp & 1) == 0) { /* word aligned? */ + outsw (UDC_DATA, cp, last >> 1); + } else { /* byte aligned. */ + for (i = 0; i < (last >> 1); i++) { + u16 w = ((u16) cp[2 * i + 1] << 8) | + (u16) cp[2 * i]; + outw (w, UDC_DATA); + } + } + if (last & 1) { + outb (*(cp + last - 1), UDC_DATA); + } + } + endpoint->last = last; + } +} + +/* omap1510_read_noniso_rx_fifo + * + * This function implements TRM Figure 14-28. + * + * If the endpoint has an active rcv_urb, then the next packet of data is read + * from the rcv FIFO and written to rcv_urb->buffer at offset + * rcv_urb->actual_length to append the packet data to the data from any + * previous packets for this transfer. We assume that there is sufficient room + * left in the buffer to hold an entire packet of data. + * + * The return value is the number of bytes read from the FIFO for this packet. + * + * In accordance with Figure 14-28, the EP_NUM register must already have been + * written with the value to select the appropriate rcv FIFO before this routine + * is called. + */ +static int omap1510_read_noniso_rx_fifo (struct usb_endpoint_instance + *endpoint) +{ + struct urb *urb = endpoint->rcv_urb; + int len = 0; + + if (urb) { + len = inw (UDC_RXFSTAT); + + if (len) { + unsigned char *cp = urb->buffer + urb->actual_length; + + insw (UDC_DATA, cp, len >> 1); + if (len & 1) + *(cp + len - 1) = inb (UDC_DATA); + } + } + return len; +} + +/* omap1510_prepare_for_control_write_status + * + * This function implements TRM Figure 14-17. + * + * We have to deal here with non-autodecoded control writes that haven't already + * been dealt with by ep0_recv_setup. The non-autodecoded standard control + * write requests are: set/clear endpoint feature, set configuration, set + * interface, and set descriptor. ep0_recv_setup handles set/clear requests for + * ENDPOINT_HALT by halting the endpoint for a set request and resetting the + * endpoint for a clear request. ep0_recv_setup returns an error for + * SET_DESCRIPTOR requests which causes them to be terminated with a stall by + * the setup handler. A SET_INTERFACE request is handled by ep0_recv_setup by + * generating a DEVICE_SET_INTERFACE event. This leaves only the + * SET_CONFIGURATION event for us to deal with here. + * + */ +static void omap1510_prepare_for_control_write_status (struct urb *urb) +{ + struct usb_device_request *request = &urb->device_request;; + + /* check for a SET_CONFIGURATION request */ + if (request->bRequest == USB_REQ_SET_CONFIGURATION) { + int configuration = le16_to_cpu (request->wValue) & 0xff; + unsigned short devstat = inw (UDC_DEVSTAT); + + if ((devstat & (UDC_ADD | UDC_CFG)) == UDC_ADD) { + /* device is currently in ADDRESSED state */ + if (configuration) { + /* Assume the specified non-zero configuration + * value is valid and switch to the CONFIGURED + * state. + */ + outw (UDC_Dev_Cfg, UDC_SYSCON2); + } + } else if ((devstat & UDC_CFG) == UDC_CFG) { + /* device is currently in CONFIGURED state */ + if (!configuration) { + /* Switch to ADDRESSED state. */ + outw (UDC_Clr_Cfg, UDC_SYSCON2); + } + } + } + + /* select EP0 tx FIFO */ + outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); + /* clear endpoint (no data bytes in status stage) */ + outw (UDC_Clr_EP, UDC_CTRL); + /* enable the EP0 tx FIFO */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + /* deselect the endpoint */ + outw (UDC_EP_Dir, UDC_EP_NUM); +} + +/* udc_state_transition_up + * udc_state_transition_down + * + * Helper functions to implement device state changes. The device states and + * the events that transition between them are: + * + * STATE_ATTACHED + * || /\ + * \/ || + * DEVICE_HUB_CONFIGURED DEVICE_HUB_RESET + * || /\ + * \/ || + * STATE_POWERED + * || /\ + * \/ || + * DEVICE_RESET DEVICE_POWER_INTERRUPTION + * || /\ + * \/ || + * STATE_DEFAULT + * || /\ + * \/ || + * DEVICE_ADDRESS_ASSIGNED DEVICE_RESET + * || /\ + * \/ || + * STATE_ADDRESSED + * || /\ + * \/ || + * DEVICE_CONFIGURED DEVICE_DE_CONFIGURED + * || /\ + * \/ || + * STATE_CONFIGURED + * + * udc_state_transition_up transitions up (in the direction from STATE_ATTACHED + * to STATE_CONFIGURED) from the specified initial state to the specified final + * state, passing through each intermediate state on the way. If the initial + * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then + * no state transitions will take place. + * + * udc_state_transition_down transitions down (in the direction from + * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the + * specified final state, passing through each intermediate state on the way. + * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final + * state, then no state transitions will take place. + * + * These functions must only be called with interrupts disabled. + */ +static void udc_state_transition_up (usb_device_state_t initial, + usb_device_state_t final) +{ + if (initial < final) { + switch (initial) { + case STATE_ATTACHED: + usbd_device_event_irq (udc_device, + DEVICE_HUB_CONFIGURED, 0); + if (final == STATE_POWERED) + break; + case STATE_POWERED: + usbd_device_event_irq (udc_device, DEVICE_RESET, 0); + if (final == STATE_DEFAULT) + break; + case STATE_DEFAULT: + usbd_device_event_irq (udc_device, + DEVICE_ADDRESS_ASSIGNED, 0); + if (final == STATE_ADDRESSED) + break; + case STATE_ADDRESSED: + usbd_device_event_irq (udc_device, DEVICE_CONFIGURED, + 0); + case STATE_CONFIGURED: + break; + default: + break; + } + } +} + +static void udc_state_transition_down (usb_device_state_t initial, + usb_device_state_t final) +{ + if (initial > final) { + switch (initial) { + case STATE_CONFIGURED: + usbd_device_event_irq (udc_device, DEVICE_DE_CONFIGURED, 0); + if (final == STATE_ADDRESSED) + break; + case STATE_ADDRESSED: + usbd_device_event_irq (udc_device, DEVICE_RESET, 0); + if (final == STATE_DEFAULT) + break; + case STATE_DEFAULT: + usbd_device_event_irq (udc_device, DEVICE_POWER_INTERRUPTION, 0); + if (final == STATE_POWERED) + break; + case STATE_POWERED: + usbd_device_event_irq (udc_device, DEVICE_HUB_RESET, 0); + case STATE_ATTACHED: + break; + default: + break; + } + } +} + +/* Handle all device state changes. + * This function implements TRM Figure 14-21. + */ +static void omap1510_udc_state_changed (void) +{ + u16 bits; + u16 devstat = inw (UDC_DEVSTAT); + + UDCDBGA ("state changed, devstat %x, old %x", devstat, udc_devstat); + + bits = devstat ^ udc_devstat; + if (bits) { + if (bits & UDC_ATT) { + if (devstat & UDC_ATT) { + UDCDBG ("device attached and powered"); + udc_state_transition_up (udc_device->device_state, STATE_POWERED); + } else { + UDCDBG ("device detached or unpowered"); + udc_state_transition_down (udc_device->device_state, STATE_ATTACHED); + } + } + if (bits & UDC_USB_Reset) { + if (devstat & UDC_USB_Reset) { + UDCDBG ("device reset in progess"); + udc_state_transition_down (udc_device->device_state, STATE_POWERED); + } else { + UDCDBG ("device reset completed"); + } + } + if (bits & UDC_DEF) { + if (devstat & UDC_DEF) { + UDCDBG ("device entering default state"); + udc_state_transition_up (udc_device->device_state, STATE_DEFAULT); + } else { + UDCDBG ("device leaving default state"); + udc_state_transition_down (udc_device->device_state, STATE_POWERED); + } + } + if (bits & UDC_SUS) { + if (devstat & UDC_SUS) { + UDCDBG ("entering suspended state"); + usbd_device_event_irq (udc_device, DEVICE_BUS_INACTIVE, 0); + } else { + UDCDBG ("leaving suspended state"); + usbd_device_event_irq (udc_device, DEVICE_BUS_ACTIVITY, 0); + } + } + if (bits & UDC_R_WK_OK) { + UDCDBGA ("remote wakeup %s", (devstat & UDC_R_WK_OK) + ? "enabled" : "disabled"); + } + if (bits & UDC_ADD) { + if (devstat & UDC_ADD) { + UDCDBG ("default -> addressed"); + udc_state_transition_up (udc_device->device_state, STATE_ADDRESSED); + } else { + UDCDBG ("addressed -> default"); + udc_state_transition_down (udc_device->device_state, STATE_DEFAULT); + } + } + if (bits & UDC_CFG) { + if (devstat & UDC_CFG) { + UDCDBG ("device configured"); + /* The ep0_recv_setup function generates the + * DEVICE_CONFIGURED event when a + * USB_REQ_SET_CONFIGURATION setup packet is + * received, so we should already be in the + * state STATE_CONFIGURED. + */ + udc_state_transition_up (udc_device->device_state, STATE_CONFIGURED); + } else { + UDCDBG ("device deconfigured"); + udc_state_transition_down (udc_device->device_state, STATE_ADDRESSED); + } + } + } + + /* Clear interrupt source */ + outw (UDC_DS_Chg, UDC_IRQ_SRC); + + /* Save current DEVSTAT */ + udc_devstat = devstat; +} + +/* Handle SETUP USB interrupt. + * This function implements TRM Figure 14-14. + */ +static void omap1510_udc_setup (struct usb_endpoint_instance *endpoint) +{ + UDCDBG ("-> Entering device setup"); + + do { + const int setup_pktsize = 8; + unsigned char *datap = + (unsigned char *) &ep0_urb->device_request; + + /* Gain access to EP 0 setup FIFO */ + outw (UDC_Setup_Sel, UDC_EP_NUM); + + /* Read control request data */ + insb (UDC_DATA, datap, setup_pktsize); + + UDCDBGA ("EP0 setup read [%x %x %x %x %x %x %x %x]", + *(datap + 0), *(datap + 1), *(datap + 2), + *(datap + 3), *(datap + 4), *(datap + 5), + *(datap + 6), *(datap + 7)); + + /* Reset EP0 setup FIFO */ + outw (0, UDC_EP_NUM); + } while (inw (UDC_IRQ_SRC) & UDC_Setup); + + /* Try to process setup packet */ + if (ep0_recv_setup (ep0_urb)) { + /* Not a setup packet, stall next EP0 transaction */ + udc_stall_ep (0); + UDCDBG ("can't parse setup packet, still waiting for setup"); + return; + } + + /* Check direction */ + if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK) + == USB_REQ_HOST2DEVICE) { + UDCDBG ("control write on EP0"); + if (le16_to_cpu (ep0_urb->device_request.wLength)) { + /* We don't support control write data stages. + * The only standard control write request with a data + * stage is SET_DESCRIPTOR, and ep0_recv_setup doesn't + * support that so we just stall those requests. A + * function driver might support a non-standard + * write request with a data stage, but it isn't + * obvious what we would do with the data if we read it + * so we'll just stall it. It seems like the API isn't + * quite right here. + */ +#if 0 + /* Here is what we would do if we did support control + * write data stages. + */ + ep0_urb->actual_length = 0; + outw (0, UDC_EP_NUM); + /* enable the EP0 rx FIFO */ + outw (UDC_Set_FIFO_En, UDC_CTRL); +#else + /* Stall this request */ + UDCDBG ("Stalling unsupported EP0 control write data " + "stage."); + udc_stall_ep (0); +#endif + } else { + omap1510_prepare_for_control_write_status (ep0_urb); + } + } else { + UDCDBG ("control read on EP0"); + /* The ep0_recv_setup function has already placed our response + * packet data in ep0_urb->buffer and the packet length in + * ep0_urb->actual_length. + */ + endpoint->tx_urb = ep0_urb; + endpoint->sent = 0; + /* select the EP0 tx FIFO */ + outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); + /* Write packet data to the FIFO. omap1510_write_noniso_tx_fifo + * will update endpoint->last with the number of bytes written + * to the FIFO. + */ + omap1510_write_noniso_tx_fifo (endpoint); + /* enable the FIFO to start the packet transmission */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + /* deselect the EP0 tx FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + } + + UDCDBG ("<- Leaving device setup"); +} + +/* Handle endpoint 0 RX interrupt + * This routine implements TRM Figure 14-16. + */ +static void omap1510_udc_ep0_rx (struct usb_endpoint_instance *endpoint) +{ + unsigned short status; + + UDCDBG ("RX on EP0"); + /* select EP0 rx FIFO */ + outw (UDC_EP_Sel, UDC_EP_NUM); + + status = inw (UDC_STAT_FLG); + + if (status & UDC_ACK) { + /* Check direction */ + if ((ep0_urb->device_request.bmRequestType + & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) { + /* This rx interrupt must be for a control write data + * stage packet. + * + * We don't support control write data stages. + * We should never end up here. + */ + + /* clear the EP0 rx FIFO */ + outw (UDC_Clr_EP, UDC_CTRL); + + /* deselect the EP0 rx FIFO */ + outw (0, UDC_EP_NUM); + + UDCDBG ("Stalling unexpected EP0 control write " + "data stage packet"); + udc_stall_ep (0); + } else { + /* This rx interrupt must be for a control read status + * stage packet. + */ + UDCDBG ("ACK on EP0 control read status stage packet"); + /* deselect EP0 rx FIFO */ + outw (0, UDC_EP_NUM); + } + } else if (status & UDC_STALL) { + UDCDBG ("EP0 stall during RX"); + /* deselect EP0 rx FIFO */ + outw (0, UDC_EP_NUM); + } else { + /* deselect EP0 rx FIFO */ + outw (0, UDC_EP_NUM); + } +} + +/* Handle endpoint 0 TX interrupt + * This routine implements TRM Figure 14-18. + */ +static void omap1510_udc_ep0_tx (struct usb_endpoint_instance *endpoint) +{ + unsigned short status; + struct usb_device_request *request = &ep0_urb->device_request; + + UDCDBG ("TX on EP0"); + /* select EP0 TX FIFO */ + outw (UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); + + status = inw (UDC_STAT_FLG); + if (status & UDC_ACK) { + /* Check direction */ + if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) == + USB_REQ_HOST2DEVICE) { + /* This tx interrupt must be for a control write status + * stage packet. + */ + UDCDBG ("ACK on EP0 control write status stage packet"); + /* deselect EP0 TX FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + } else { + /* This tx interrupt must be for a control read data + * stage packet. + */ + int wLength = le16_to_cpu (request->wLength); + + /* Update our count of bytes sent so far in this + * transfer. + */ + endpoint->sent += endpoint->last; + + /* We are finished with this transfer if we have sent + * all of the bytes in our tx urb (urb->actual_length) + * unless we need a zero-length terminating packet. We + * need a zero-length terminating packet if we returned + * fewer bytes than were requested (wLength) by the host, + * and the number of bytes we returned is an exact + * multiple of the packet size endpoint->tx_packetSize. + */ + if ((endpoint->sent == ep0_urb->actual_length) + && ((ep0_urb->actual_length == wLength) + || (endpoint->last != + endpoint->tx_packetSize))) { + /* Done with control read data stage. */ + UDCDBG ("control read data stage complete"); + /* deselect EP0 TX FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + /* select EP0 RX FIFO to prepare for control + * read status stage. + */ + outw (UDC_EP_Sel, UDC_EP_NUM); + /* clear the EP0 RX FIFO */ + outw (UDC_Clr_EP, UDC_CTRL); + /* enable the EP0 RX FIFO */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + /* deselect the EP0 RX FIFO */ + outw (0, UDC_EP_NUM); + } else { + /* We still have another packet of data to send + * in this control read data stage or else we + * need a zero-length terminating packet. + */ + UDCDBG ("ACK control read data stage packet"); + omap1510_write_noniso_tx_fifo (endpoint); + /* enable the EP0 tx FIFO to start transmission */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + /* deselect EP0 TX FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + } + } + } else if (status & UDC_STALL) { + UDCDBG ("EP0 stall during TX"); + /* deselect EP0 TX FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + } else { + /* deselect EP0 TX FIFO */ + outw (UDC_EP_Dir, UDC_EP_NUM); + } +} + +/* Handle RX transaction on non-ISO endpoint. + * This function implements TRM Figure 14-27. + * The ep argument is a physical endpoint number for a non-ISO OUT endpoint + * in the range 1 to 15. + */ +static void omap1510_udc_epn_rx (int ep) +{ + unsigned short status; + + /* Check endpoint status */ + status = inw (UDC_STAT_FLG); + + if (status & UDC_ACK) { + int nbytes; + struct usb_endpoint_instance *endpoint = + omap1510_find_ep (ep); + + nbytes = omap1510_read_noniso_rx_fifo (endpoint); + usbd_rcv_complete (endpoint, nbytes, 0); + + /* enable rx FIFO to prepare for next packet */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + } else if (status & UDC_STALL) { + UDCDBGA ("STALL on RX endpoint %d", ep); + } else if (status & UDC_NAK) { + UDCDBGA ("NAK on RX ep %d", ep); + } else { + serial_printf ("omap-bi: RX on ep %d with status %x", ep, + status); + } +} + +/* Handle TX transaction on non-ISO endpoint. + * This function implements TRM Figure 14-29. + * The ep argument is a physical endpoint number for a non-ISO IN endpoint + * in the range 16 to 30. + */ +static void omap1510_udc_epn_tx (int ep) +{ + unsigned short status; + + /*serial_printf("omap1510_udc_epn_tx( %x )\n",ep); */ + + /* Check endpoint status */ + status = inw (UDC_STAT_FLG); + + if (status & UDC_ACK) { + struct usb_endpoint_instance *endpoint = + omap1510_find_ep (ep); + + /* We need to transmit a terminating zero-length packet now if + * we have sent all of the data in this URB and the transfer + * size was an exact multiple of the packet size. + */ + if (endpoint->tx_urb + && (endpoint->last == endpoint->tx_packetSize) + && (endpoint->tx_urb->actual_length - endpoint->sent - + endpoint->last == 0)) { + /* Prepare to transmit a zero-length packet. */ + endpoint->sent += endpoint->last; + /* write 0 bytes of data to FIFO */ + omap1510_write_noniso_tx_fifo (endpoint); + /* enable tx FIFO to start transmission */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + } else if (endpoint->tx_urb + && endpoint->tx_urb->actual_length) { + /* retire the data that was just sent */ + usbd_tx_complete (endpoint); + /* Check to see if we have more data ready to transmit + * now. + */ + if (endpoint->tx_urb + && endpoint->tx_urb->actual_length) { + /* write data to FIFO */ + omap1510_write_noniso_tx_fifo (endpoint); + /* enable tx FIFO to start transmission */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + } + } + } else if (status & UDC_STALL) { + UDCDBGA ("STALL on TX endpoint %d", ep); + } else if (status & UDC_NAK) { + UDCDBGA ("NAK on TX endpoint %d", ep); + } else { + /*serial_printf("omap-bi: TX on ep %d with status %x\n", ep, status); */ + } +} + + +/* +------------------------------------------------------------------------------- +*/ + +/* Handle general USB interrupts and dispatch according to type. + * This function implements TRM Figure 14-13. + */ +void omap1510_udc_irq (void) +{ + u16 irq_src = inw (UDC_IRQ_SRC); + int valid_irq = 0; + + if (!(irq_src & ~UDC_SOF_Flg)) /* ignore SOF interrupts ) */ + return; + + UDCDBGA ("< IRQ #%d start >- %x", udc_interrupts, irq_src); + /*serial_printf("< IRQ #%d start >- %x\n", udc_interrupts, irq_src); */ + + if (irq_src & UDC_DS_Chg) { + /* Device status changed */ + omap1510_udc_state_changed (); + valid_irq++; + } + if (irq_src & UDC_EP0_RX) { + /* Endpoint 0 receive */ + outw (UDC_EP0_RX, UDC_IRQ_SRC); /* ack interrupt */ + omap1510_udc_ep0_rx (udc_device->bus->endpoint_array + 0); + valid_irq++; + } + if (irq_src & UDC_EP0_TX) { + /* Endpoint 0 transmit */ + outw (UDC_EP0_TX, UDC_IRQ_SRC); /* ack interrupt */ + omap1510_udc_ep0_tx (udc_device->bus->endpoint_array + 0); + valid_irq++; + } + if (irq_src & UDC_Setup) { + /* Device setup */ + omap1510_udc_setup (udc_device->bus->endpoint_array + 0); + valid_irq++; + } + /*if (!valid_irq) */ + /* serial_printf("unknown interrupt, IRQ_SRC %.4x\n", irq_src); */ + UDCDBGA ("< IRQ #%d end >", udc_interrupts); + udc_interrupts++; +} + +/* This function implements TRM Figure 14-26. */ +void omap1510_udc_noniso_irq (void) +{ + unsigned short epnum; + unsigned short irq_src = inw (UDC_IRQ_SRC); + int valid_irq = 0; + + if (!(irq_src & (UDC_EPn_RX | UDC_EPn_TX))) + return; + + UDCDBGA ("non-ISO IRQ, IRQ_SRC %x", inw (UDC_IRQ_SRC)); + + if (irq_src & UDC_EPn_RX) { /* Endpoint N OUT transaction */ + /* Determine the endpoint number for this interrupt */ + epnum = (inw (UDC_EPN_STAT) & 0x0f00) >> 8; + UDCDBGA ("RX on ep %x", epnum); + + /* acknowledge interrupt */ + outw (UDC_EPn_RX, UDC_IRQ_SRC); + + if (epnum) { + /* select the endpoint FIFO */ + outw (UDC_EP_Sel | epnum, UDC_EP_NUM); + + omap1510_udc_epn_rx (epnum); + + /* deselect the endpoint FIFO */ + outw (epnum, UDC_EP_NUM); + } + valid_irq++; + } + if (irq_src & UDC_EPn_TX) { /* Endpoint N IN transaction */ + /* Determine the endpoint number for this interrupt */ + epnum = (inw (UDC_EPN_STAT) & 0x000f) | USB_DIR_IN; + UDCDBGA ("TX on ep %x", epnum); + + /* acknowledge interrupt */ + outw (UDC_EPn_TX, UDC_IRQ_SRC); + + if (epnum) { + /* select the endpoint FIFO */ + outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); + + omap1510_udc_epn_tx (epnum); + + /* deselect the endpoint FIFO */ + outw (UDC_EP_Dir | epnum, UDC_EP_NUM); + } + valid_irq++; + } + if (!valid_irq) + serial_printf (": unknown non-ISO interrupt, IRQ_SRC %.4x\n", + irq_src); +} + +/* +------------------------------------------------------------------------------- +*/ + + +/* + * Start of public functions. + */ + +/* Called to start packet transmission. */ +void udc_endpoint_write (struct usb_endpoint_instance *endpoint) +{ + unsigned short epnum = + endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK; + + UDCDBGA ("Starting transmit on ep %x", epnum); + + if (endpoint->tx_urb) { + /* select the endpoint FIFO */ + outw (UDC_EP_Sel | UDC_EP_Dir | epnum, UDC_EP_NUM); + /* write data to FIFO */ + omap1510_write_noniso_tx_fifo (endpoint); + /* enable tx FIFO to start transmission */ + outw (UDC_Set_FIFO_En, UDC_CTRL); + /* deselect the endpoint FIFO */ + outw (UDC_EP_Dir | epnum, UDC_EP_NUM); + } +} + +/* Start to initialize h/w stuff */ +int udc_init (void) +{ + u16 udc_rev; + uchar value; + ulong gpio; + int i; + + /* Let the device settle down before we start */ + for (i = 0; i < UDC_INIT_MDELAY; i++) udelay(1000); + + udc_device = NULL; + + UDCDBG ("starting"); + + /* Check peripheral reset. Must be 1 to make sure + MPU TIPB peripheral reset is inactive */ + UDCREG (ARM_RSTCT2); + + /* Set and check clock control. + * We might ought to be using the clock control API to do + * this instead of fiddling with the clock registers directly + * here. + */ + outw ((1 << 4) | (1 << 5), CLOCK_CTRL); + UDCREG (CLOCK_CTRL); + /* Set and check APLL */ + outw (0x0008, APLL_CTRL); + UDCREG (APLL_CTRL); + /* Set and check DPLL */ + outw (0x2210, DPLL_CTRL); + UDCREG (DPLL_CTRL); + /* Set and check SOFT */ + outw ((1 << 4) | (1 << 3) | 1, SOFT_REQ); + /* Short delay to wait for DPLL */ + udelay (1000); + + /* Print banner with device revision */ + udc_rev = inw (UDC_REV) & 0xff; + printf ("USB: TI OMAP1510 USB function module rev %d.%d\n", + udc_rev >> 4, udc_rev & 0xf); + +#ifdef CONFIG_OMAP_SX1 + i2c_read (0x32, 0x04, 1, &value, 1); + value |= 0x04; + i2c_write (0x32, 0x04, 1, &value, 1); + + i2c_read (0x32, 0x03, 1, &value, 1); + value |= 0x01; + i2c_write (0x32, 0x03, 1, &value, 1); + + gpio = inl(GPIO_PIN_CONTROL_REG); + gpio |= 0x0002; /* A_IRDA_OFF */ + gpio |= 0x0800; /* A_SWITCH */ + gpio |= 0x8000; /* A_USB_ON */ + outl (gpio, GPIO_PIN_CONTROL_REG); + + gpio = inl(GPIO_DIR_CONTROL_REG); + gpio &= ~0x0002; /* A_IRDA_OFF */ + gpio &= ~0x0800; /* A_SWITCH */ + gpio &= ~0x8000; /* A_USB_ON */ + outl (gpio, GPIO_DIR_CONTROL_REG); + + gpio = inl(GPIO_DATA_OUTPUT_REG); + gpio |= 0x0002; /* A_IRDA_OFF */ + gpio &= ~0x0800; /* A_SWITCH */ + gpio &= ~0x8000; /* A_USB_ON */ + outl (gpio, GPIO_DATA_OUTPUT_REG); +#endif + + /* The VBUS_MODE bit selects whether VBUS detection is done via + * software (1) or hardware (0). When software detection is + * selected, VBUS_CTRL selects whether USB is not connected (0) + * or connected (1). + */ + outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); + outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); + UDCREGL (FUNC_MUX_CTRL_0); + + /* + * At this point, device is ready for configuration... + */ + + UDCDBG ("disable USB interrupts"); + outw (0, UDC_IRQ_EN); + UDCREG (UDC_IRQ_EN); + + UDCDBG ("disable USB DMA"); + outw (0, UDC_DMA_IRQ_EN); + UDCREG (UDC_DMA_IRQ_EN); + + UDCDBG ("initialize SYSCON1"); + outw (UDC_Self_Pwr | UDC_Pullup_En, UDC_SYSCON1); + UDCREG (UDC_SYSCON1); + + return 0; +} + +/* Stall endpoint */ +static void udc_stall_ep (unsigned int ep_addr) +{ + /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ + int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + + UDCDBGA ("stall ep_addr %d", ep_addr); + + /* REVISIT? + * The OMAP TRM section 14.2.4.2 says we must check that the FIFO + * is empty before halting the endpoint. The current implementation + * doesn't check that the FIFO is empty. + */ + + if (!ep_num) { + outw (UDC_Stall_Cmd, UDC_SYSCON2); + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { + if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { + /* we have a valid rx endpoint, so halt it */ + outw (UDC_EP_Sel | ep_num, UDC_EP_NUM); + outw (UDC_Set_Halt, UDC_CTRL); + outw (ep_num, UDC_EP_NUM); + } + } else { + if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { + /* we have a valid tx endpoint, so halt it */ + outw (UDC_EP_Sel | UDC_EP_Dir | ep_num, UDC_EP_NUM); + outw (UDC_Set_Halt, UDC_CTRL); + outw (ep_num, UDC_EP_NUM); + } + } +} + +/* Reset endpoint */ +#if 0 +static void udc_reset_ep (unsigned int ep_addr) +{ + /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ + int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + + UDCDBGA ("reset ep_addr %d", ep_addr); + + if (!ep_num) { + /* control endpoint 0 can't be reset */ + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) { + UDCDBGA ("UDC_EP_RX(%d) = 0x%04x", ep_num, + inw (UDC_EP_RX (ep_num))); + if (inw (UDC_EP_RX (ep_num)) & UDC_EPn_RX_Valid) { + /* we have a valid rx endpoint, so reset it */ + outw (ep_num | UDC_EP_Sel, UDC_EP_NUM); + outw (UDC_Reset_EP, UDC_CTRL); + outw (ep_num, UDC_EP_NUM); + UDCDBGA ("OUT endpoint %d reset", ep_num); + } + } else { + UDCDBGA ("UDC_EP_TX(%d) = 0x%04x", ep_num, + inw (UDC_EP_TX (ep_num))); + /* Resetting of tx endpoints seems to be causing the USB function + * module to fail, which causes problems when the driver is + * uninstalled. We'll skip resetting tx endpoints for now until + * we figure out what the problem is. + */ +#if 0 + if (inw (UDC_EP_TX (ep_num)) & UDC_EPn_TX_Valid) { + /* we have a valid tx endpoint, so reset it */ + outw (ep_num | UDC_EP_Dir | UDC_EP_Sel, UDC_EP_NUM); + outw (UDC_Reset_EP, UDC_CTRL); + outw (ep_num | UDC_EP_Dir, UDC_EP_NUM); + UDCDBGA ("IN endpoint %d reset", ep_num); + } +#endif + } +} +#endif + +/* ************************************************************************** */ + +/** + * udc_check_ep - check logical endpoint + * + * Return physical endpoint number to use for this logical endpoint or zero if not valid. + */ +#if 0 +int udc_check_ep (int logical_endpoint, int packetsize) +{ + if ((logical_endpoint == 0x80) || + ((logical_endpoint & 0x8f) != logical_endpoint)) { + return 0; + } + + switch (packetsize) { + case 8: + case 16: + case 32: + case 64: + case 128: + case 256: + case 512: + break; + default: + return 0; + } + + return EP_ADDR_TO_PHYS_EP (logical_endpoint); +} +#endif + +/* + * udc_setup_ep - setup endpoint + * + * Associate a physical endpoint with endpoint_instance + */ +void udc_setup_ep (struct usb_device_instance *device, + unsigned int ep, struct usb_endpoint_instance *endpoint) +{ + UDCDBGA ("setting up endpoint addr %x", endpoint->endpoint_address); + + /* This routine gets called by bi_modinit for endpoint 0 and from + * bi_config for all of the other endpoints. bi_config gets called + * during the DEVICE_CREATE, DEVICE_CONFIGURED, and + * DEVICE_SET_INTERFACE events. We need to reconfigure the OMAP packet + * RAM after bi_config scans the selected device configuration and + * initializes the endpoint structures, but before this routine enables + * the OUT endpoint FIFOs. Since bi_config calls this routine in a + * loop for endpoints 1 through UDC_MAX_ENDPOINTS, we reconfigure our + * packet RAM here when ep==1. + * I really hate to do this here, but it seems like the API exported + * by the USB bus interface controller driver to the usbd-bi module + * isn't quite right so there is no good place to do this. + */ + if (ep == 1) { + omap1510_deconfigure_device (); + omap1510_configure_device (device); + } + + if (endpoint && (ep < UDC_MAX_ENDPOINTS)) { + int ep_addr = endpoint->endpoint_address; + + if (!ep_addr) { + /* nothing to do for endpoint 0 */ + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + /* nothing to do for IN (tx) endpoints */ + } else { /* OUT (rx) endpoint */ + if (endpoint->rcv_packetSize) { + /*struct urb* urb = &(urb_out_array[ep&0xFF]); */ + /*urb->endpoint = endpoint; */ + /*urb->device = device; */ + /*urb->buffer_length = sizeof(urb->buffer); */ + + /*endpoint->rcv_urb = urb; */ + omap1510_prepare_endpoint_for_rx (ep_addr); + } + } + } +} + +/** + * udc_disable_ep - disable endpoint + * @ep: + * + * Disable specified endpoint + */ +#if 0 +void udc_disable_ep (unsigned int ep_addr) +{ + /*int ep_addr = PHYS_EP_TO_EP_ADDR(ep); */ + int ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK; + struct usb_endpoint_instance *endpoint = omap1510_find_ep (ep_addr); /*udc_device->bus->endpoint_array + ep; */ + + UDCDBGA ("disable ep_addr %d", ep_addr); + + if (!ep_num) { + /* nothing to do for endpoint 0 */ ; + } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { + if (endpoint->tx_packetSize) { + /* we have a valid tx endpoint */ + /*usbd_flush_tx(endpoint); */ + endpoint->tx_urb = NULL; + } + } else { + if (endpoint->rcv_packetSize) { + /* we have a valid rx endpoint */ + /*usbd_flush_rcv(endpoint); */ + endpoint->rcv_urb = NULL; + } + } +} +#endif + +/* ************************************************************************** */ + +/** + * udc_connected - is the USB cable connected + * + * Return non-zero if cable is connected. + */ +#if 0 +int udc_connected (void) +{ + return ((inw (UDC_DEVSTAT) & UDC_ATT) == UDC_ATT); +} +#endif + +/* Turn on the USB connection by enabling the pullup resistor */ +void udc_connect (void) +{ + UDCDBG ("connect, enable Pullup"); + outl (0x00000018, FUNC_MUX_CTRL_D); +} + +/* Turn off the USB connection by disabling the pullup resistor */ +void udc_disconnect (void) +{ + UDCDBG ("disconnect, disable Pullup"); + outl (0x00000000, FUNC_MUX_CTRL_D); +} + +/* ************************************************************************** */ + + +/* + * udc_disable_interrupts - disable interrupts + * switch off interrupts + */ +#if 0 +void udc_disable_interrupts (struct usb_device_instance *device) +{ + UDCDBG ("disabling all interrupts"); + outw (0, UDC_IRQ_EN); +} +#endif + +/* ************************************************************************** */ + +/** + * udc_ep0_packetsize - return ep0 packetsize + */ +#if 0 +int udc_ep0_packetsize (void) +{ + return EP0_PACKETSIZE; +} +#endif + +/* Switch on the UDC */ +void udc_enable (struct usb_device_instance *device) +{ + UDCDBGA ("enable device %p, status %d", device, device->status); + + /* initialize driver state variables */ + udc_devstat = 0; + + /* Save the device structure pointer */ + udc_device = device; + + /* Setup ep0 urb */ + if (!ep0_urb) { + ep0_urb = + usbd_alloc_urb (udc_device, + udc_device->bus->endpoint_array); + } else { + serial_printf ("udc_enable: ep0_urb already allocated %p\n", + ep0_urb); + } + + UDCDBG ("Check clock status"); + UDCREG (STATUS_REQ); + + /* The VBUS_MODE bit selects whether VBUS detection is done via + * software (1) or hardware (0). When software detection is + * selected, VBUS_CTRL selects whether USB is not connected (0) + * or connected (1). + */ + outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_CTRL | UDC_VBUS_MODE, + FUNC_MUX_CTRL_0); + UDCREGL (FUNC_MUX_CTRL_0); + + omap1510_configure_device (device); +} + +/* Switch off the UDC */ +void udc_disable (void) +{ + UDCDBG ("disable UDC"); + + omap1510_deconfigure_device (); + + /* The VBUS_MODE bit selects whether VBUS detection is done via + * software (1) or hardware (0). When software detection is + * selected, VBUS_CTRL selects whether USB is not connected (0) + * or connected (1). + */ + outl (inl (FUNC_MUX_CTRL_0) | UDC_VBUS_MODE, FUNC_MUX_CTRL_0); + outl (inl (FUNC_MUX_CTRL_0) & ~UDC_VBUS_CTRL, FUNC_MUX_CTRL_0); + UDCREGL (FUNC_MUX_CTRL_0); + + /* Free ep0 URB */ + if (ep0_urb) { + /*usbd_dealloc_urb(ep0_urb); */ + ep0_urb = NULL; + } + + /* Reset device pointer. + * We ought to do this here to balance the initialization of udc_device + * in udc_enable, but some of our other exported functions get called + * by the bus interface driver after udc_disable, so we have to hang on + * to the device pointer to avoid a null pointer dereference. */ + /* udc_device = NULL; */ +} + +/** + * udc_startup - allow udc code to do any additional startup + */ +void udc_startup_events (struct usb_device_instance *device) +{ + /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ + usbd_device_event_irq (device, DEVICE_INIT, 0); + + /* The DEVICE_CREATE event puts the USB device in the state + * STATE_ATTACHED. + */ + usbd_device_event_irq (device, DEVICE_CREATE, 0); + + /* Some USB controller driver implementations signal + * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. + * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, + * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. + * The OMAP USB client controller has the capability to detect when the + * USB cable is connected to a powered USB bus via the ATT bit in the + * DEVSTAT register, so we will defer the DEVICE_HUB_CONFIGURED and + * DEVICE_RESET events until later. + */ + + udc_enable (device); +} + +#endif diff --git a/drivers/usbtty.c b/drivers/usbtty.c new file mode 100644 index 000000000..ce4a12e16 --- /dev/null +++ b/drivers/usbtty.c @@ -0,0 +1,665 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +#ifdef CONFIG_USB_TTY + +#include +#include +#include "usbtty.h" + +#if 0 +#define TTYDBG(fmt,args...) serial_printf("[%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args) +#else +#define TTYDBG(fmt,args...) do{}while(0) +#endif + +#if 0 +#define TTYERR(fmt,args...) serial_printf("ERROR![%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args) +#else +#define TTYERR(fmt,args...) do{}while(0) +#endif + +/* + * Buffers to hold input and output data + */ +#define USBTTY_BUFFER_SIZE 256 +static circbuf_t usbtty_input; +static circbuf_t usbtty_output; + + +/* + * Instance variables + */ +static device_t usbttydev; +static struct usb_device_instance device_instance[1]; +static struct usb_bus_instance bus_instance[1]; +static struct usb_configuration_instance config_instance[NUM_CONFIGS]; +static struct usb_interface_instance interface_instance[NUM_INTERFACES]; +static struct usb_alternate_instance alternate_instance[NUM_INTERFACES]; +static struct usb_endpoint_instance endpoint_instance[NUM_ENDPOINTS+1]; /* one extra for control endpoint */ + +/* + * Static allocation of urbs + */ +#define RECV_ENDPOINT 1 +#define TX_ENDPOINT 2 + +/* + * Global flag + */ +int usbtty_configured_flag = 0; + + +/* + * Serial number + */ +static char serial_number[16]; + +/* + * Descriptors + */ +static u8 wstrLang[4] = {4,USB_DT_STRING,0x9,0x4}; +static u8 wstrManufacturer[2 + 2*(sizeof(CONFIG_USBD_MANUFACTURER)-1)]; +static u8 wstrProduct[2 + 2*(sizeof(CONFIG_USBD_PRODUCT_NAME)-1)]; +static u8 wstrSerial[2 + 2*(sizeof(serial_number) - 1)]; +static u8 wstrConfiguration[2 + 2*(sizeof(CONFIG_USBD_CONFIGURATION_STR)-1)]; +static u8 wstrInterface[2 + 2*(sizeof(CONFIG_USBD_INTERFACE_STR)-1)]; + +static struct usb_string_descriptor *usbtty_string_table[] = { + (struct usb_string_descriptor*)wstrLang, + (struct usb_string_descriptor*)wstrManufacturer, + (struct usb_string_descriptor*)wstrProduct, + (struct usb_string_descriptor*)wstrSerial, + (struct usb_string_descriptor*)wstrConfiguration, + (struct usb_string_descriptor*)wstrInterface +}; +extern struct usb_string_descriptor **usb_strings; /* defined and used by omap1510_ep0.c */ + +static struct usb_device_descriptor device_descriptor = { + bLength: sizeof(struct usb_device_descriptor), + bDescriptorType: USB_DT_DEVICE, + bcdUSB: USB_BCD_VERSION, + bDeviceClass: USBTTY_DEVICE_CLASS, + bDeviceSubClass: USBTTY_DEVICE_SUBCLASS, + bDeviceProtocol: USBTTY_DEVICE_PROTOCOL, + bMaxPacketSize0: EP0_MAX_PACKET_SIZE, + idVendor: CONFIG_USBD_VENDORID, + idProduct: CONFIG_USBD_PRODUCTID, + bcdDevice: USBTTY_BCD_DEVICE, + iManufacturer: STR_MANUFACTURER, + iProduct: STR_PRODUCT, + iSerialNumber: STR_SERIAL, + bNumConfigurations: NUM_CONFIGS + }; +static struct usb_configuration_descriptor config_descriptors[NUM_CONFIGS] = { + { + bLength: sizeof(struct usb_configuration_descriptor), + bDescriptorType: USB_DT_CONFIG, + wTotalLength: (sizeof(struct usb_configuration_descriptor)*NUM_CONFIGS) + + (sizeof(struct usb_interface_descriptor)*NUM_INTERFACES) + + (sizeof(struct usb_endpoint_descriptor)*NUM_ENDPOINTS), + bNumInterfaces: NUM_INTERFACES, + bConfigurationValue: 1, + iConfiguration: STR_CONFIG, + bmAttributes: BMATTRIBUTE_SELF_POWERED | BMATTRIBUTE_RESERVED, + bMaxPower: USBTTY_MAXPOWER + }, +}; +static struct usb_interface_descriptor interface_descriptors[NUM_INTERFACES] = { + { + bLength: sizeof(struct usb_interface_descriptor), + bDescriptorType: USB_DT_INTERFACE, + bInterfaceNumber: 0, + bAlternateSetting: 0, + bNumEndpoints: NUM_ENDPOINTS, + bInterfaceClass: USBTTY_INTERFACE_CLASS, + bInterfaceSubClass: USBTTY_INTERFACE_SUBCLASS, + bInterfaceProtocol: USBTTY_INTERFACE_PROTOCOL, + iInterface: STR_INTERFACE + }, +}; +static struct usb_endpoint_descriptor ep_descriptors[NUM_ENDPOINTS] = { + { + bLength: sizeof(struct usb_endpoint_descriptor), + bDescriptorType: USB_DT_ENDPOINT, + bEndpointAddress: CONFIG_USBD_SERIAL_OUT_ENDPOINT | USB_DIR_OUT, + bmAttributes: USB_ENDPOINT_XFER_BULK, + wMaxPacketSize: CONFIG_USBD_SERIAL_OUT_PKTSIZE, + bInterval: 0 + }, + { + bLength: sizeof(struct usb_endpoint_descriptor), + bDescriptorType: USB_DT_ENDPOINT, + bEndpointAddress: CONFIG_USBD_SERIAL_IN_ENDPOINT | USB_DIR_IN, + bmAttributes: USB_ENDPOINT_XFER_BULK, + wMaxPacketSize: CONFIG_USBD_SERIAL_IN_PKTSIZE, + bInterval: 0 + }, + { + bLength: sizeof(struct usb_endpoint_descriptor), + bDescriptorType: USB_DT_ENDPOINT, + bEndpointAddress: CONFIG_USBD_SERIAL_INT_ENDPOINT | USB_DIR_IN, + bmAttributes: USB_ENDPOINT_XFER_INT, + wMaxPacketSize: CONFIG_USBD_SERIAL_INT_PKTSIZE, + bInterval: 0 + }, +}; +static struct usb_endpoint_descriptor *ep_descriptor_ptrs[NUM_ENDPOINTS] = { + &(ep_descriptors[0]), + &(ep_descriptors[1]), + &(ep_descriptors[2]), +}; + +/* utility function for converting char* to wide string used by USB */ +static void str2wide (char *str, u16 * wide) +{ + int i; + + for (i = 0; i < strlen (str) && str[i]; i++) + wide[i] = (u16) str[i]; +} + +/* + * Prototypes + */ +static void usbtty_init_strings (void); +static void usbtty_init_instances (void); +static void usbtty_init_endpoints (void); + +static void usbtty_event_handler (struct usb_device_instance *device, + usb_device_event_t event, int data); +static int usbtty_configured (void); + +static int write_buffer (circbuf_t * buf); +static int fill_buffer (circbuf_t * buf); + +void usbtty_poll (void); +static void pretend_interrupts (void); + + +/* + * Test whether a character is in the RX buffer + */ +int usbtty_tstc (void) +{ + usbtty_poll (); + return (usbtty_input.size > 0); +} + +/* + * Read a single byte from the usb client port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int usbtty_getc (void) +{ + char c; + + while (usbtty_input.size <= 0) { + usbtty_poll (); + } + + buf_pop (&usbtty_input, &c, 1); + return c; +} + +/* + * Output a single byte to the usb client port. + */ +void usbtty_putc (const char c) +{ + buf_push (&usbtty_output, &c, 1); + /* If \n, also do \r */ + if (c == '\n') + buf_push (&usbtty_output, "\r", 1); + + /* Poll at end to handle new data... */ + if ((usbtty_output.size + 2) >= usbtty_output.totalsize) { + usbtty_poll (); + } +} + + +/* usbtty_puts() helper function for finding the next '\n' in a string */ +static int next_nl_pos (const char *s) +{ + int i; + + for (i = 0; s[i] != '\0'; i++) { + if (s[i] == '\n') + return i; + } + return i; +} + +/* + * Output a string to the usb client port. + */ +static void __usbtty_puts (const char *str, int len) +{ + int maxlen = usbtty_output.totalsize; + int space, n; + + /* break str into chunks < buffer size, if needed */ + while (len > 0) { + space = maxlen - usbtty_output.size; + + /* Empty buffer here, if needed, to ensure space... */ + if (space <= 0) { + write_buffer (&usbtty_output); + space = maxlen - usbtty_output.size; + if (space <= 0) { + space = len; /* allow old data to be overwritten. */ + } + } + + n = MIN (space, MIN (len, maxlen)); + buf_push (&usbtty_output, str, n); + + str += n; + len -= n; + } +} + +void usbtty_puts (const char *str) +{ + int n; + int len = strlen (str); + + /* add '\r' for each '\n' */ + while (len > 0) { + n = next_nl_pos (str); + + if (str[n] == '\n') { + __usbtty_puts (str, n + 1); + __usbtty_puts ("\r", 1); + str += (n + 1); + len -= (n + 1); + } else { + /* No \n found. All done. */ + __usbtty_puts (str, n); + break; + } + } + + /* Poll at end to handle new data... */ + usbtty_poll (); +} + +/* + * Initialize the usb client port. + * + */ +int drv_usbtty_init (void) +{ + int rc; + char * sn; + int snlen; + + if (!(sn = getenv("serial#"))) { + sn = "000000000000"; + } + snlen = strlen(sn); + if (snlen > sizeof(serial_number) - 1) { + printf ("Warning: serial number %s is too long (%d > %d)\n", + sn, snlen, sizeof(serial_number) - 1); + snlen = sizeof(serial_number) - 1; + } + memcpy (serial_number, sn, snlen); + serial_number[snlen] = '\0'; + + /* prepare buffers... */ + buf_init (&usbtty_input, USBTTY_BUFFER_SIZE); + buf_init (&usbtty_output, USBTTY_BUFFER_SIZE); + + /* Now, set up USB controller and infrastructure */ + udc_init (); /* Basic USB initialization */ + + usbtty_init_strings (); + usbtty_init_instances (); + + udc_startup_events (device_instance); /* Enable our device, initialize udc pointers */ + udc_connect (); /* Enable pullup for host detection */ + + usbtty_init_endpoints (); + + /* Device initialization */ + memset (&usbttydev, 0, sizeof (usbttydev)); + + strcpy (usbttydev.name, "usbtty"); + usbttydev.ext = 0; /* No extensions */ + usbttydev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT; + usbttydev.tstc = usbtty_tstc; /* 'tstc' function */ + usbttydev.getc = usbtty_getc; /* 'getc' function */ + usbttydev.putc = usbtty_putc; /* 'putc' function */ + usbttydev.puts = usbtty_puts; /* 'puts' function */ + + rc = device_register (&usbttydev); + + return (rc == 0) ? 1 : rc; +} + +static void usbtty_init_strings (void) +{ + struct usb_string_descriptor *string; + + string = (struct usb_string_descriptor *) wstrManufacturer; + string->bLength = sizeof (wstrManufacturer); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_MANUFACTURER, string->wData); + + string = (struct usb_string_descriptor *) wstrProduct; + string->bLength = sizeof (wstrProduct); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_PRODUCT_NAME, string->wData); + + string = (struct usb_string_descriptor *) wstrSerial; + string->bLength = 2 + 2*strlen(serial_number); + string->bDescriptorType = USB_DT_STRING; + str2wide (serial_number, string->wData); + + string = (struct usb_string_descriptor *) wstrConfiguration; + string->bLength = sizeof (wstrConfiguration); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_CONFIGURATION_STR, string->wData); + + string = (struct usb_string_descriptor *) wstrInterface; + string->bLength = sizeof (wstrInterface); + string->bDescriptorType = USB_DT_STRING; + str2wide (CONFIG_USBD_INTERFACE_STR, string->wData); + + /* Now, initialize the string table for ep0 handling */ + usb_strings = usbtty_string_table; +} + +static void usbtty_init_instances (void) +{ + int i; + + /* initialize device instance */ + memset (device_instance, 0, sizeof (struct usb_device_instance)); + device_instance->device_state = STATE_INIT; + device_instance->device_descriptor = &device_descriptor; + device_instance->event = usbtty_event_handler; + device_instance->bus = bus_instance; + device_instance->configurations = NUM_CONFIGS; + device_instance->configuration_instance_array = config_instance; + + /* initialize bus instance */ + memset (bus_instance, 0, sizeof (struct usb_bus_instance)); + bus_instance->device = device_instance; + bus_instance->endpoint_array = endpoint_instance; + bus_instance->max_endpoints = 1; + bus_instance->maxpacketsize = 64; + bus_instance->serial_number_str = serial_number; + + /* configuration instance */ + memset (config_instance, 0, + sizeof (struct usb_configuration_instance)); + config_instance->interfaces = NUM_INTERFACES; + config_instance->configuration_descriptor = config_descriptors; + config_instance->interface_instance_array = interface_instance; + + /* interface instance */ + memset (interface_instance, 0, + sizeof (struct usb_interface_instance)); + interface_instance->alternates = 1; + interface_instance->alternates_instance_array = alternate_instance; + + /* alternates instance */ + memset (alternate_instance, 0, + sizeof (struct usb_alternate_instance)); + alternate_instance->interface_descriptor = interface_descriptors; + alternate_instance->endpoints = NUM_ENDPOINTS; + alternate_instance->endpoints_descriptor_array = ep_descriptor_ptrs; + + /* endpoint instances */ + memset (&endpoint_instance[0], 0, + sizeof (struct usb_endpoint_instance)); + endpoint_instance[0].endpoint_address = 0; + endpoint_instance[0].rcv_packetSize = EP0_MAX_PACKET_SIZE; + endpoint_instance[0].rcv_attributes = USB_ENDPOINT_XFER_CONTROL; + endpoint_instance[0].tx_packetSize = EP0_MAX_PACKET_SIZE; + endpoint_instance[0].tx_attributes = USB_ENDPOINT_XFER_CONTROL; + udc_setup_ep (device_instance, 0, &endpoint_instance[0]); + + for (i = 1; i <= NUM_ENDPOINTS; i++) { + memset (&endpoint_instance[i], 0, + sizeof (struct usb_endpoint_instance)); + + endpoint_instance[i].endpoint_address = + ep_descriptors[i - 1].bEndpointAddress; + + endpoint_instance[i].rcv_packetSize = + ep_descriptors[i - 1].wMaxPacketSize; + endpoint_instance[i].rcv_attributes = + ep_descriptors[i - 1].bmAttributes; + + endpoint_instance[i].tx_packetSize = + ep_descriptors[i - 1].wMaxPacketSize; + endpoint_instance[i].tx_attributes = + ep_descriptors[i - 1].bmAttributes; + + urb_link_init (&endpoint_instance[i].rcv); + urb_link_init (&endpoint_instance[i].rdy); + urb_link_init (&endpoint_instance[i].tx); + urb_link_init (&endpoint_instance[i].done); + + if (endpoint_instance[i].endpoint_address & USB_DIR_IN) + endpoint_instance[i].tx_urb = + usbd_alloc_urb (device_instance, + &endpoint_instance[i]); + else + endpoint_instance[i].rcv_urb = + usbd_alloc_urb (device_instance, + &endpoint_instance[i]); + } +} + +static void usbtty_init_endpoints (void) +{ + int i; + + bus_instance->max_endpoints = NUM_ENDPOINTS + 1; + for (i = 0; i <= NUM_ENDPOINTS; i++) { + udc_setup_ep (device_instance, i, &endpoint_instance[i]); + } +} + + +/*********************************************************************************/ + +static struct urb *next_urb (struct usb_device_instance *device, + struct usb_endpoint_instance *endpoint) +{ + struct urb *current_urb = NULL; + int space; + + /* If there's a queue, then we should add to the last urb */ + if (!endpoint->tx_queue) { + current_urb = endpoint->tx_urb; + } else { + /* Last urb from tx chain */ + current_urb = + p2surround (struct urb, link, endpoint->tx.prev); + } + + /* Make sure this one has enough room */ + space = current_urb->buffer_length - current_urb->actual_length; + if (space > 0) { + return current_urb; + } else { /* No space here */ + /* First look at done list */ + current_urb = first_urb_detached (&endpoint->done); + if (!current_urb) { + current_urb = usbd_alloc_urb (device, endpoint); + } + + urb_append (&endpoint->tx, current_urb); + endpoint->tx_queue++; + } + return current_urb; +} + +static int write_buffer (circbuf_t * buf) +{ + if (!usbtty_configured ()) { + return 0; + } + + if (buf->size) { + + struct usb_endpoint_instance *endpoint = + &endpoint_instance[TX_ENDPOINT]; + struct urb *current_urb = NULL; + char *dest; + + int space_avail; + int popnum, popped; + int total = 0; + + /* Break buffer into urb sized pieces, and link each to the endpoint */ + while (buf->size > 0) { + current_urb = next_urb (device_instance, endpoint); + if (!current_urb) { + TTYERR ("current_urb is NULL, buf->size %d\n", + buf->size); + return total; + } + + dest = current_urb->buffer + + current_urb->actual_length; + + space_avail = + current_urb->buffer_length - + current_urb->actual_length; + popnum = MIN (space_avail, buf->size); + if (popnum == 0) + break; + + popped = buf_pop (buf, dest, popnum); + if (popped == 0) + break; + current_urb->actual_length += popped; + total += popped; + + /* If endpoint->last == 0, then transfers have not started on this endpoint */ + if (endpoint->last == 0) { + udc_endpoint_write (endpoint); + } + + } /* end while */ + return total; + } /* end if tx_urb */ + + return 0; +} + +static int fill_buffer (circbuf_t * buf) +{ + struct usb_endpoint_instance *endpoint = + &endpoint_instance[RECV_ENDPOINT]; + + if (endpoint->rcv_urb && endpoint->rcv_urb->actual_length) { + unsigned int nb = endpoint->rcv_urb->actual_length; + char *src = (char *) endpoint->rcv_urb->buffer; + + buf_push (buf, src, nb); + endpoint->rcv_urb->actual_length = 0; + + return nb; + } + + return 0; +} + +static int usbtty_configured (void) +{ + return usbtty_configured_flag; +} + +/*********************************************************************************/ + +static void usbtty_event_handler (struct usb_device_instance *device, + usb_device_event_t event, int data) +{ + switch (event) { + case DEVICE_RESET: + case DEVICE_BUS_INACTIVE: + usbtty_configured_flag = 0; + break; + case DEVICE_CONFIGURED: + usbtty_configured_flag = 1; + break; + + case DEVICE_ADDRESS_ASSIGNED: + usbtty_init_endpoints (); + + default: + break; + } +} + +/*********************************************************************************/ + + +/* + * Since interrupt handling has not yet been implemented, we use this function + * to handle polling. This is called by the tstc,getc,putc,puts routines to + * update the USB state. + */ +void usbtty_poll (void) +{ + /* New interrupts? */ + pretend_interrupts (); + + /* Write any output data to host buffer (do this before checking interrupts to avoid missing one) */ + if (usbtty_configured ()) { + write_buffer (&usbtty_output); + } + + /* New interrupts? */ + pretend_interrupts (); + + /* Check for new data from host.. (do this after checking interrupts to get latest data) */ + if (usbtty_configured ()) { + fill_buffer (&usbtty_input); + } + + /* New interrupts? */ + pretend_interrupts (); +} + +static void pretend_interrupts (void) +{ + /* Loop while we have interrupts. + * If we don't do this, the input chain + * polling delay is likely to miss + * host requests. + */ + while (inw (UDC_IRQ_SRC) & ~UDC_SOF_Flg) { + /* Handle any new IRQs */ + omap1510_udc_irq (); + omap1510_udc_noniso_irq (); + } +} +#endif diff --git a/drivers/usbtty.h b/drivers/usbtty.h new file mode 100644 index 000000000..79c2fe57d --- /dev/null +++ b/drivers/usbtty.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2003 + * Gerry Hamel, geh@ti.com, Texas Instruments + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __USB_TTY_H__ +#define __USB_TTY_H__ + + +#include "usbdcore.h" +#include "usbdcore_omap1510.h" + + +#define NUM_CONFIGS 1 +#define NUM_INTERFACES 1 +#define NUM_ENDPOINTS 3 + +#define EP0_MAX_PACKET_SIZE 64 + +#define CONFIG_USBD_CONFIGURATION_STR "TTY via USB" +#define CONFIG_USBD_INTERFACE_STR "Simple Serial Data Interface - Bulk Mode" + + +#define CONFIG_USBD_SERIAL_OUT_ENDPOINT 2 +#define CONFIG_USBD_SERIAL_OUT_PKTSIZE 64 +#define CONFIG_USBD_SERIAL_IN_ENDPOINT 1 +#define CONFIG_USBD_SERIAL_IN_PKTSIZE 64 +#define CONFIG_USBD_SERIAL_INT_ENDPOINT 5 +#define CONFIG_USBD_SERIAL_INT_PKTSIZE 16 + + +#define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS +#define USBTTY_DEVICE_SUBCLASS COMMUNICATIONS_NO_SUBCLASS +#define USBTTY_DEVICE_PROTOCOL COMMUNICATIONS_NO_PROTOCOL + +#define USBTTY_INTERFACE_CLASS 0xFF /* Vendor Specific */ +#define USBTTY_INTERFACE_SUBCLASS 0x02 +#define USBTTY_INTERFACE_PROTOCOL 0x01 + +#define USBTTY_BCD_DEVICE 0x0 +#define USBTTY_MAXPOWER 0x0 + +#define STR_MANUFACTURER 1 +#define STR_PRODUCT 2 +#define STR_SERIAL 3 +#define STR_CONFIG 4 +#define STR_INTERFACE 5 + +#endif diff --git a/drivers/videomodes.c b/drivers/videomodes.c new file mode 100644 index 000000000..c81e5bc14 --- /dev/null +++ b/drivers/videomodes.c @@ -0,0 +1,208 @@ +/* + * (C) Copyright 2004 + * Pierre Aubert, Staubli Faverges , + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + Get Parameters for the video mode: + The default video mode can be defined in CFG_DEFAULT_VIDEO_MODE. + If undefined, default video mode is set to 0x301 + Parameters can be set via the variable "videomode" in the environment. + 2 diferent ways are possible: + "videomode=301" - 301 is a hexadecimal number describing the VESA + mode. Following modes are implemented: + + Colors 640x480 800x600 1024x768 1152x864 1280x1024 + --------+--------------------------------------------- + 8 bits | 0x301 0x303 0x305 0x161 0x307 + 15 bits | 0x310 0x313 0x316 0x162 0x319 + 16 bits | 0x311 0x314 0x317 0x163 0x31A + 24 bits | 0x312 0x315 0x318 ? 0x31B + --------+--------------------------------------------- + "videomode=bootargs" + - the parameters are parsed from the bootargs. + The format is "NAME:VALUE,NAME:VALUE" etc. + Ex.: + "bootargs=video=ctfb:x:800,y:600,depth:16,pclk:25000" + Parameters not included in the list will be taken from + the default mode, which is one of the following: + mode:0 640x480x24 + mode:1 800x600x16 + mode:2 1024x768x8 + mode:3 960x720x24 + mode:4 1152x864x16 + mode:5 1280x1024x8 + + if "mode" is not provided within the parameter list, + mode:0 is assumed. + Following parameters are supported: + x xres = visible resolution horizontal + y yres = visible resolution vertical + pclk pixelclocks in pico sec + le left_marging time from sync to picture in pixelclocks + ri right_marging time from picture to sync in pixelclocks + up upper_margin time from sync to picture + lo lower_margin + hs hsync_len length of horizontal sync + vs vsync_len length of vertical sync + sync see FB_SYNC_* + vmode see FB_VMODE_* + depth Color depth in bits per pixel + All other parameters in the variable bootargs are ignored. + It is also possible to set the parameters direct in the + variable "videomode", or in another variable i.e. + "myvideo" and setting the variable "videomode=myvideo".. +****************************************************************************/ + +#include +#include "videomodes.h" + +const struct ctfb_vesa_modes vesa_modes[VESA_MODES_COUNT] = { + {0x301, RES_MODE_640x480, 8}, + {0x310, RES_MODE_640x480, 15}, + {0x311, RES_MODE_640x480, 16}, + {0x312, RES_MODE_640x480, 24}, + {0x303, RES_MODE_800x600, 8}, + {0x313, RES_MODE_800x600, 15}, + {0x314, RES_MODE_800x600, 16}, + {0x315, RES_MODE_800x600, 24}, + {0x305, RES_MODE_1024x768, 8}, + {0x316, RES_MODE_1024x768, 15}, + {0x317, RES_MODE_1024x768, 16}, + {0x318, RES_MODE_1024x768, 24}, + {0x161, RES_MODE_1152x864, 8}, + {0x162, RES_MODE_1152x864, 15}, + {0x163, RES_MODE_1152x864, 16}, + {0x307, RES_MODE_1280x1024, 8}, + {0x319, RES_MODE_1280x1024, 15}, + {0x31A, RES_MODE_1280x1024, 16}, + {0x31B, RES_MODE_1280x1024, 24}, +}; +const struct ctfb_res_modes res_mode_init[RES_MODES_COUNT] = { + /* x y pixclk le ri up lo hs vs s vmode */ + {640, 480, 39721, 40, 24, 32, 11, 96, 2, 0, FB_VMODE_NONINTERLACED}, + {800, 600, 27778, 64, 24, 22, 1, 72, 2, 0, FB_VMODE_NONINTERLACED}, + {1024, 768, 15384, 168, 8, 29, 3, 144, 4, 0, FB_VMODE_NONINTERLACED}, + {960, 720, 13100, 160, 40, 32, 8, 80, 4, 0, FB_VMODE_NONINTERLACED}, + {1152, 864, 12004, 200, 64, 32, 16, 80, 4, 0, FB_VMODE_NONINTERLACED}, + {1280, 1024, 9090, 200, 48, 26, 1, 184, 3, 0, FB_VMODE_NONINTERLACED}, +}; + +/************************************************************************ + * Get Parameters for the video mode: + */ +/********************************************************************* + * returns the length to the next seperator + */ +static int +video_get_param_len (char *start, char sep) +{ + int i = 0; + while ((*start != 0) && (*start != sep)) { + start++; + i++; + } + return i; +} + +static int +video_search_param (char *start, char *param) +{ + int len, totallen, i; + char *p = start; + len = strlen (param); + totallen = len + strlen (start); + for (i = 0; i < totallen; i++) { + if (strncmp (p++, param, len) == 0) + return (i); + } + return -1; +} + +/*************************************************************** + * Get parameter via the environment as it is done for the + * linux kernel i.e: + * video=ctfb:x:800,xv:1280,y:600,yv:1024,depth:16,mode:0,pclk:25000, + * le:56,ri:48,up:26,lo:5,hs:152,vs:2,sync:0,vmode:0,accel:0 + * + * penv is a pointer to the environment, containing the string, or the name of + * another environment variable. It could even be the term "bootargs" + */ + +#define GET_OPTION(name,var) \ + if(strncmp(p,name,strlen(name))==0) { \ + val_s=p+strlen(name); \ + var=simple_strtoul(val_s, NULL, 10); \ + } + +int video_get_params (struct ctfb_res_modes *pPar, char *penv) +{ + char *p, *s, *val_s; + int i = 0, t; + int bpp; + int mode; + /* first search for the environment containing the real param string */ + s = penv; + if ((p = getenv (s)) != NULL) { + s = p; + } + /* in case of the bootargs line, we have to start + * after "video=ctfb:" + */ + i = video_search_param (s, "video=ctfb:"); + if (i >= 0) { + s += i; + s += strlen ("video=ctfb:"); + } + /* search for mode as a default value */ + p = s; + t = 0; + mode = 0; /* default */ + while ((i = video_get_param_len (p, ',')) != 0) { + GET_OPTION ("mode:", mode) + p += i; + if (*p != 0) + p++; /* skip ',' */ + } + if (mode >= RES_MODES_COUNT) + mode = 0; + *pPar = res_mode_init[mode]; /* copy default values */ + bpp = 24 - ((mode % 3) * 8); + p = s; /* restart */ + while ((i = video_get_param_len (p, ',')) != 0) { + GET_OPTION ("x:", pPar->xres) + GET_OPTION ("y:", pPar->yres) + GET_OPTION ("le:", pPar->left_margin) + GET_OPTION ("ri:", pPar->right_margin) + GET_OPTION ("up:", pPar->upper_margin) + GET_OPTION ("lo:", pPar->lower_margin) + GET_OPTION ("hs:", pPar->hsync_len) + GET_OPTION ("vs:", pPar->vsync_len) + GET_OPTION ("sync:", pPar->sync) + GET_OPTION ("vmode:", pPar->vmode) + GET_OPTION ("pclk:", pPar->pixclock) + GET_OPTION ("depth:", bpp) + p += i; + if (*p != 0) + p++; /* skip ',' */ + } + return bpp; +} diff --git a/drivers/videomodes.h b/drivers/videomodes.h new file mode 100644 index 000000000..e2dffe7fe --- /dev/null +++ b/drivers/videomodes.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2004 + * Pierre Aubert, Staubli Faverges , + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef CFG_DEFAULT_VIDEO_MODE +#define CFG_DEFAULT_VIDEO_MODE 0x301 +#endif + +/* Some mode definitions */ +#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ +#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ +#define FB_SYNC_EXT 4 /* external sync */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ + /* vtotal = 144d/288n/576i => PAL */ + /* vtotal = 121d/242n/484i => NTSC */ +#define FB_SYNC_ON_GREEN 32 /* sync on green */ +#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +#define FB_VMODE_INTERLACED 1 /* interlaced */ +#define FB_VMODE_DOUBLE 2 /* double scan */ +#define FB_VMODE_MASK 255 + +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ +#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */ + + +/****************************************************************** + * Resolution Struct + ******************************************************************/ +struct ctfb_res_modes { + int xres; /* visible resolution */ + int yres; + /* Timing: All values in pixclocks, except pixclock (of course) */ + int pixclock; /* pixel clock in ps (pico seconds) */ + int left_margin; /* time from sync to picture */ + int right_margin; /* time from picture to sync */ + int upper_margin; /* time from sync to picture */ + int lower_margin; + int hsync_len; /* length of horizontal sync */ + int vsync_len; /* length of vertical sync */ + int sync; /* see FB_SYNC_* */ + int vmode; /* see FB_VMODE_* */ +}; + +/****************************************************************** + * Vesa Mode Struct + ******************************************************************/ +struct ctfb_vesa_modes { + int vesanr; /* Vesa number as in LILO (VESA Nr + 0x200} */ + int resindex; /* index to resolution struct */ + int bits_per_pixel; /* bpp */ +}; + +#define RES_MODE_640x480 0 +#define RES_MODE_800x600 1 +#define RES_MODE_1024x768 2 +#define RES_MODE_960_720 3 +#define RES_MODE_1152x864 4 +#define RES_MODE_1280x1024 5 +#define RES_MODES_COUNT 6 + +#define VESA_MODES_COUNT 19 + +extern const struct ctfb_vesa_modes vesa_modes[]; +extern const struct ctfb_res_modes res_mode_init[]; + +int video_get_params (struct ctfb_res_modes *pPar, char *penv); diff --git a/drivers/w83c553f.c b/drivers/w83c553f.c new file mode 100644 index 000000000..5d82ed4dd --- /dev/null +++ b/drivers/w83c553f.c @@ -0,0 +1,226 @@ +/* + * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH + * Andreas Heppel + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Initialisation of the PCI-to-ISA bridge and disabling the BIOS + * write protection (for flash) in function 0 of the chip. + * Enabling function 1 (IDE controller of the chip. + */ + +#include +#include + +#ifdef CFG_WINBOND_83C553 + +#include +#include + +#include + +#define out8(addr,val) do { \ + out_8((u8*) (addr),(val)); udelay(1); \ + } while (0) +#define out16(addr,val) do { \ + out_be16((u16*) (addr),(val)); udelay(1); \ + } while (0) + +extern uint ide_bus_offset[CFG_IDE_MAXBUS]; + +void initialise_pic(void); +void initialise_dma(void); + +void initialise_w83c553f(void) +{ + pci_dev_t devbusfn; + unsigned char reg8; + unsigned short reg16; + unsigned int reg32; + + devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0); + if (devbusfn == -1) + { + printf("Error: Cannot find W83C553F controller on any PCI bus."); + return; + } + + pci_read_config_word(devbusfn, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; + pci_write_config_word(devbusfn, PCI_COMMAND, reg16); + + pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8); + /* 16 MB ISA memory space */ + reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7); + reg8 &= ~IPADCR_MBE512; + pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8); + + pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8); + /* switch off BIOS write protection */ + reg8 |= CSCR_UBIOSCSE; + reg8 &= ~CSCR_BIOSWP; + pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8); + + /* + * Interrupt routing: + * - IDE -> IRQ 9/0 + * - INTA -> IRQ 10 + * - INTB -> IRQ 11 + * - INTC -> IRQ 14 + * - INTD -> IRQ 15 + */ + pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90); + pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF); + + /* + * Read IDE bus offsets from function 1 device. + * We must unmask the LSB indicating that ist is an IO address. + */ + devbusfn |= PCI_BDF(0,0,1); + + /* + * Switch off legacy IRQ for IDE and IDE port 1. + */ + pci_write_config_byte(devbusfn, 0x09, 0x8F); + + pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32); + reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16); + pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32); + + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]); + ide_bus_offset[0] &= ~1; +#if CFG_IDE_MAXBUS > 1 + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]); + ide_bus_offset[1] &= ~1; +#endif + + /* + * Enable function 1, IDE -> busmastering and IO space access + */ + pci_read_config_word(devbusfn, PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word(devbusfn, PCI_COMMAND, reg16); + + /* + * Initialise ISA interrupt controller + */ + initialise_pic(); + + /* + * Initialise DMA controller + */ + initialise_dma(); +} + +void initialise_pic(void) +{ + out8(W83C553F_PIC1_ICW1, 0x11); + out8(W83C553F_PIC1_ICW2, 0x08); + out8(W83C553F_PIC1_ICW3, 0x04); + out8(W83C553F_PIC1_ICW4, 0x01); + out8(W83C553F_PIC1_OCW1, 0xfb); + out8(W83C553F_PIC1_ELC, 0x20); + + out8(W83C553F_PIC2_ICW1, 0x11); + out8(W83C553F_PIC2_ICW2, 0x08); + out8(W83C553F_PIC2_ICW3, 0x02); + out8(W83C553F_PIC2_ICW4, 0x01); + out8(W83C553F_PIC2_OCW1, 0xff); + out8(W83C553F_PIC2_ELC, 0xce); + + out8(W83C553F_TMR1_CMOD, 0x74); + + out8(W83C553F_PIC2_OCW1, 0x20); + out8(W83C553F_PIC1_OCW1, 0x20); + + out8(W83C553F_PIC2_OCW1, 0x2b); + out8(W83C553F_PIC1_OCW1, 0x2b); +} + +void initialise_dma(void) +{ + unsigned int channel; + unsigned int rvalue1, rvalue2; + + /* perform a H/W reset of the devices */ + + out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00); + out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000); + + /* initialise all channels to a sane state */ + + for (channel = 0; channel < 4; channel++) { + /* + * dependent upon the channel, setup the specifics: + * + * demand + * address-increment + * autoinitialize-disable + * verify-transfer + */ + + switch (channel) { + case 0: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL); + break; + case 1: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); + break; + case 2: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); + break; + case 3: + rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); + rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); + break; + default: + rvalue1 = 0x00; + rvalue2 = 0x00; + break; + } + + /* write to write mode registers */ + + out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF); + out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF); + } + + /* enable all channels */ + + out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00); + out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000); + /* + * initialize the global DMA configuration + * + * DACK# active low + * DREQ active high + * fixed priority + * channel group enable + */ + + out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00); + out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000); +} + +#endif /* CFG_WINBOND_83C553 */ diff --git a/drivers/zoom2_debug_board.c b/drivers/zoom2_debug_board.c new file mode 100644 index 000000000..8b1dc90e1 --- /dev/null +++ b/drivers/zoom2_debug_board.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2009 + * Windriver, + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#include +#include + +#define DEBUG_BOARD_CONNECTED 1 +#define DEBUG_BOARD_NOT_CONNECTED 0 + +static int debug_board_connected = DEBUG_BOARD_CONNECTED; + +static void zoom2_debug_board_detect(void) +{ + unsigned int val; + /* GPIO to query for debug board + 158 db board query, bank 5, index 30 */ + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + + val = __raw_readl(&gpio5_base->datain); + + /* Check the bit for gpio 158 */ + if (!(val & (1 << 30))) + debug_board_connected = DEBUG_BOARD_NOT_CONNECTED; +} + +int zoom2_debug_board_connected(void) +{ + static int first_time = 1; + + if (first_time) { + zoom2_debug_board_detect(); + first_time = 0; + } + return debug_board_connected; +} + diff --git a/drivers/zoom2_led.c b/drivers/zoom2_led.c new file mode 100644 index 000000000..5381e951f --- /dev/null +++ b/drivers/zoom2_led.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2009 + * Windriver, + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include + +/* GPIO LEDs + 173 red , bank 6, index 13 + 154 blue , bank 5, index 26 + 61 blue2, bank 2, index 29 + 94 green, bank 3, index 30 (3630zoom3) */ + + +#if defined (CONFIG_ZOOM2_LED) + +void omap3_zoom2_led_red_off(void) +{ + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + + sr32((u32)&gpio6_base->cleardataout, 13, 1, 1); /* red off */ +} + +void omap3_zoom2_led_blue_off(void) +{ + gpio_t *gpio2_base = (gpio_t *)OMAP34XX_GPIO2_BASE; + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + + sr32((u32)&gpio5_base->cleardataout, 26, 1, 1); /* blue off */ + sr32((u32)&gpio2_base->cleardataout, 29, 1, 1); /* blue 2 off */ +} + +#if defined(CONFIG_3630ZOOM3) +void omap3_zoom2_led_green_off(void) +{ + gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; + + sr32((u32)&gpio3_base->cleardataout, 30, 1, 1); /* green off */ +} +#endif + +void omap3_zoom2_led_red_on(void) +{ + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + + #if defined(CONFIG_3630ZOOM3) + omap3_zoom2_led_green_off(); + #endif + omap3_zoom2_led_blue_off(); + + sr32((u32)&gpio6_base->setdataout, 13, 1, 1); /* red on */ +} + +void omap3_zoom2_led_blue_on(void) +{ + gpio_t *gpio2_base = (gpio_t *)OMAP34XX_GPIO2_BASE; + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + + #if defined(CONFIG_3630ZOOM3) + omap3_zoom2_led_green_off(); + #endif + omap3_zoom2_led_red_off(); + + sr32((u32)&gpio5_base->setdataout, 26, 1, 1); /* blue on */ + sr32((u32)&gpio2_base->setdataout, 29, 1, 1); /* blue 2 on */ +} + +#if defined(CONFIG_3630ZOOM3) +void omap3_zoom2_led_green_on(void) +{ + gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; + omap3_zoom2_led_blue_off(); + omap3_zoom2_led_red_off(); + sr32((u32)&gpio3_base->setdataout, 30, 1, 1); /* green on */ +} +#endif + +#endif /* CONFIG_ZOOM2_LED */ diff --git a/drivers/zoom2_serial.c b/drivers/zoom2_serial.c new file mode 100644 index 000000000..afe705a56 --- /dev/null +++ b/drivers/zoom2_serial.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2009 + * Windriver, + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This file was adapted from cpu/mpc5xxx/serial.c + * + */ + +#include "zoom2_serial.h" + +int zoom2_debug_board_connected(void); + +int quad_init_dev(unsigned long base) +{ + /* The Quad UART is on the debug board. + Check if the debug board is attached before using the UART */ + if (zoom2_debug_board_connected()) { + NS16550_t port = (NS16550_t) base; + int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE; + + NS16550_init(port, clock_divisor); + } + /* We have to lie here, otherwise the board init code will hang + on the check */ + return 0; +} + +void quad_putc_dev(unsigned long base, const char c) +{ + if (zoom2_debug_board_connected()) { + NS16550_t port = (NS16550_t) base; + + if (c == '\n') + quad_putc_dev(base, '\r'); + + NS16550_putc(port, c); + } +} + +void quad_puts_dev(unsigned long base, const char *s) +{ + if (zoom2_debug_board_connected()) { + while (*s) + quad_putc_dev(base, *s++); + } +} + +int quad_getc_dev(unsigned long base) +{ + if (zoom2_debug_board_connected()) { + NS16550_t port = (NS16550_t) base; + + return NS16550_getc(port); + } else { + return 0; + } +} + +int quad_tstc_dev(unsigned long base) +{ + if (zoom2_debug_board_connected()) { + NS16550_t port = (NS16550_t) base; + + return NS16550_tstc(port); + } else { + return 0; + } +} + +void quad_setbrg_dev(unsigned long base) +{ + if (zoom2_debug_board_connected()) { + NS16550_t port = (NS16550_t) base; + + int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE; + + NS16550_reinit(port, clock_divisor); + } +} + +QUAD_INIT(0) +QUAD_INIT(1) +QUAD_INIT(2) +QUAD_INIT(3) + diff --git a/dtt/Makefile b/dtt/Makefile new file mode 100644 index 000000000..0a334784d --- /dev/null +++ b/dtt/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2001 +# Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +#CFLAGS += -DDEBUG + +LIB = libdtt.a + +OBJS = lm75.o ds1621.o adm1021.o + +all: $(LIB) + +$(LIB): $(START) $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/dtt/adm1021.c b/dtt/adm1021.c new file mode 100644 index 000000000..14c38f0a8 --- /dev/null +++ b/dtt/adm1021.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2003 + * Murray Jensen, CSIRO-MIT, Murray.Jensen@csiro.au + * + * based on dtt/lm75.c which is ... + * + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Analog Devices's ADM1021 + * "Low Cost Microprocessor System Temperature Monitor" + */ + +#include + +#ifdef CONFIG_DTT_ADM1021 + +#include +#include + +typedef + struct { + uint i2c_addr:7; /* 7bit i2c chip address */ + uint conv_rate:3; /* conversion rate */ + uint enable_alert:1; /* enable alert output pin */ + uint enable_local:1; /* enable internal temp sensor */ + uint max_local:8; /* internal temp maximum */ + uint min_local:8; /* internal temp minimum */ + uint enable_remote:1; /* enable remote temp sensor */ + uint max_remote:8; /* remote temp maximum */ + uint min_remote:8; /* remote temp minimum */ + } +dtt_cfg_t; + +dtt_cfg_t dttcfg[] = CFG_DTT_ADM1021; + +int +dtt_read (int sensor, int reg) +{ + dtt_cfg_t *dcp = &dttcfg[sensor >> 1]; + uchar data; + + if (i2c_read(dcp->i2c_addr, reg, 1, &data, 1) != 0) + return -1; + + return (int)data; +} /* dtt_read() */ + +int +dtt_write (int sensor, int reg, int val) +{ + dtt_cfg_t *dcp = &dttcfg[sensor >> 1]; + uchar data; + + data = (uchar)(val & 0xff); + + if (i2c_write(dcp->i2c_addr, reg, 1, &data, 1) != 0) + return 1; + + return 0; +} /* dtt_write() */ + +static int +_dtt_init (int sensor) +{ + dtt_cfg_t *dcp = &dttcfg[sensor >> 1]; + int reg, val; + + if (((sensor & 1) == 0 ? dcp->enable_local : dcp->enable_remote) == 0) + return 1; /* sensor is disabled (or rather ignored) */ + + /* + * Setup High Limit register + */ + if ((sensor & 1) == 0) { + reg = DTT_WRITE_LOC_HIGHLIM; + val = dcp->max_local; + } + else { + reg = DTT_WRITE_REM_HIGHLIM; + val = dcp->max_remote; + } + if (dtt_write (sensor, reg, val) != 0) + return 1; + + /* + * Setup Low Limit register + */ + if ((sensor & 1) == 0) { + reg = DTT_WRITE_LOC_LOWLIM; + val = dcp->min_local; + } + else { + reg = DTT_WRITE_REM_LOWLIM; + val = dcp->min_remote; + } + if (dtt_write (sensor, reg, val) != 0) + return 1; + + /* shouldn't hurt if the rest gets done twice */ + + /* + * Setup Conversion Rate register + */ + if (dtt_write (sensor, DTT_WRITE_CONVRATE, dcp->conv_rate) != 0) + return 1; + + /* + * Setup configuraton register + */ + val = 0; /* running */ + if (dcp->enable_alert == 0) + val |= DTT_CONFIG_ALERT_MASKED; /* mask ALERT pin */ + if (dtt_write (sensor, DTT_WRITE_CONFIG, val) != 0) + return 1; + + return 0; +} /* _dtt_init() */ + +int +dtt_init (void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + const char *const header = "DTT: "; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf ("%s%d FAILED INIT\n", header, i+1); + else + printf ("%s%d is %i C\n", header, i+1, + dtt_get_temp(sensors[i])); + } + + return (0); +} /* dtt_init() */ + +int +dtt_get_temp (int sensor) +{ + signed char val; + + if ((sensor & 1) == 0) + val = dtt_read(sensor, DTT_READ_LOC_VALUE); + else + val = dtt_read(sensor, DTT_READ_REM_VALUE); + + return (int) val; +} /* dtt_get_temp() */ + +#endif /* CONFIG_DTT_ADM1021 */ diff --git a/dtt/ds1621.c b/dtt/ds1621.c new file mode 100644 index 000000000..494818131 --- /dev/null +++ b/dtt/ds1621.c @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2001 + * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Dallas Semiconductor's DS1621 Digital Thermometer and Thermostat. + */ + +#include + +#ifdef CONFIG_DTT_DS1621 +#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ + (CFG_EEPROM_PAGE_WRITE_BITS < 1) +# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_DS1621" +#endif +#include +#include + +/* + * Device code + */ +#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */ + +int dtt_read(int sensor, int reg) +{ + int dlen; + uchar data[2]; + + /* + * Calculate sensor address and command. + * + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/ + + /* + * Prepare to handle 2 byte result. + */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) + dlen = 2; + else + dlen = 1; + + /* + * Now try to read the register. + */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return 1; + + /* + * Handle 2 byte result. + */ + if (dlen == 2) + return ((int)((short)data[1] + (((short)data[0]) << 8))); + + return (int)data[0]; +} /* dtt_read() */ + + +int dtt_write(int sensor, int reg, int val) +{ + int dlen; + uchar data[2]; + + /* + * Calculate sensor address and register. + * + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); + + /* + * Handle various data sizes. + */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) { + dlen = 2; + data[0] = (char)((val >> 8) & 0xff); /* MSB first */ + data[1] = (char)(val & 0xff); + } + else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) { + dlen = 0; + data[0] = (char)0; + data[1] = (char)0; + } + else { + dlen = 1; + data[0] = (char)(val & 0xff); + } + + /* + * Write value to device. + */ + if (i2c_write(sensor, reg, 1, data, dlen) != 0) + return 1; + + return 0; +} /* dtt_write() */ + + +static int _dtt_init(int sensor) +{ + int val; + + /* + * Setup High Temp. + */ + val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0) + return 1; + udelay(50000); /* Max 50ms */ + + /* + * Setup Low Temp - hysteresis. + */ + val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0) + return 1; + udelay(50000); /* Max 50ms */ + + /* + * Setup configuraton register + * + * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES + * + * We run in polled mode, since there isn't any way to know if this + * lousy device is ready to provide temperature readings on power up. + */ + val = 0x9; + if (dtt_write(sensor, DTT_CONFIG, val) != 0) + return 1; + udelay(50000); /* Max 50ms */ + + return 0; +} /* _dtt_init() */ + + +int dtt_init (void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("DTT%d: FAILED\n", i+1); + else + printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i])); + } + + return (0); +} /* dtt_init() */ + + +int dtt_get_temp(int sensor) +{ + int i; + + /* + * Start a conversion, may take up to 1 second. + */ + dtt_write(sensor, DTT_WRITE_START_CONV, 0); + for (i = 0; i <= 10; i++) { + udelay(100000); + if (dtt_read(sensor, DTT_CONFIG) & 0x80) + break; + } + + return (dtt_read(sensor, DTT_READ_TEMP) / 256); +} /* dtt_get_temp() */ + + +#endif /* CONFIG_DTT_DS1621 */ diff --git a/dtt/lm75.c b/dtt/lm75.c new file mode 100644 index 000000000..59daa4539 --- /dev/null +++ b/dtt/lm75.c @@ -0,0 +1,180 @@ +/* + * (C) Copyright 2001 + * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * On Semiconductor's LM75 Temperature Sensor + */ + +#include + +#ifdef CONFIG_DTT_LM75 +#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \ + (CFG_EEPROM_PAGE_WRITE_BITS < 1) +# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_LM75" +#endif + +#include +#include + + +/* + * Device code + */ +#define DTT_I2C_DEV_CODE 0x48 /* ON Semi's LM75 device */ + +int dtt_read(int sensor, int reg) +{ + int dlen; + uchar data[2]; + + /* + * Validate 'reg' param + */ + if((reg < 0) || (reg > 3)) + return -1; + + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate address of lm75 */ + + /* + * Prepare to handle 2 byte result. + */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_HYST) || + (reg == DTT_TEMP_SET)) + dlen = 2; + else + dlen = 1; + + /* + * Now try to read the register. + */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return -1; + + /* + * Handle 2 byte result. + */ + if (dlen == 2) + return ((int)((short)data[1] + (((short)data[0]) << 8))); + + + return (int)data[0]; +} /* dtt_read() */ + + +int dtt_write(int sensor, int reg, int val) +{ + int dlen; + uchar data[2]; + + /* + * Validate 'reg' param + */ + if ((reg < 0) || (reg > 3)) + return 1; + + /* + * Calculate sensor address and register. + */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* calculate address of lm75 */ + + /* + * Handle 2 byte values. + */ + if ((reg == DTT_READ_TEMP) || + (reg == DTT_TEMP_HYST) || + (reg == DTT_TEMP_SET)) { + dlen = 2; + data[0] = (char)((val >> 8) & 0xff); /* MSB first */ + data[1] = (char)(val & 0xff); + } else { + dlen = 1; + data[0] = (char)(val & 0xff); + } + + /* + * Write value to register. + */ + if (i2c_write(sensor, reg, 1, data, dlen) != 0) + return 1; + + return 0; +} /* dtt_write() */ + + +static int _dtt_init(int sensor) +{ + int val; + + /* + * Setup TSET ( trip point ) register + */ + val = ((CFG_DTT_MAX_TEMP * 2) << 7) & 0xff80; /* trip */ + if (dtt_write(sensor, DTT_TEMP_SET, val) != 0) + return 1; + + /* + * Setup THYST ( untrip point ) register - Hysteresis + */ + val = (((CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_HYST, val) != 0) + return 1; + + /* + * Setup configuraton register + */ + /* config = 6 sample integration, int mode, active low, and enable */ + val = 0x18; + if (dtt_write(sensor, DTT_CONFIG, val) != 0) + return 1; + + return 0; +} /* _dtt_init() */ + + +int dtt_init (void) +{ + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; + const char *const header = "DTT: "; + + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("%s%d FAILED INIT\n", header, i+1); + else + printf("%s%d is %i C\n", header, i+1, + dtt_get_temp(sensors[i])); + } + + return (0); +} /* dtt_init() */ + +int dtt_get_temp(int sensor) +{ + return (dtt_read(sensor, DTT_READ_TEMP) / 256); +} /* dtt_get_temp() */ + +#endif /* CONFIG_DTT_LM75 */ diff --git a/examples/Makefile b/examples/Makefile index 66b354daa..51344b71d 100644 --- a/examples/Makefile +++ b/examples/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000-2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -30,7 +30,7 @@ LOAD_ADDR = 0x40000 endif ifeq ($(ARCH),arm) -ifeq ($(BOARD),omap2420h4) +ifeq ($(CPU),omap3) LOAD_ADDR = 0x80300000 else LOAD_ADDR = 0xc100000 @@ -61,83 +61,56 @@ ifeq ($(ARCH),blackfin) LOAD_ADDR = 0x1000 endif -ifeq ($(ARCH),avr32) -LOAD_ADDR = 0x00000000 -endif - -ifeq ($(ARCH),sh) -LOAD_ADDR = 0x8C000000 -endif - -ifeq ($(ARCH),sparc) -LOAD_ADDR = 0x00000000 -L $(gcclibdir) -T sparc.lds -endif - include $(TOPDIR)/config.mk -ELF = hello_world SREC = hello_world.srec -BIN = hello_world.bin +BIN = hello_world.bin hello_world ifeq ($(CPU),mpc8xx) -ELF += test_burst -SREC += test_burst.srec -BIN += test_burst.bin +SREC = test_burst.srec +BIN = test_burst.bin test_burst endif ifeq ($(ARCH),i386) -ELF += 82559_eeprom -SREC += 82559_eeprom.srec -BIN += 82559_eeprom.bin +SREC += 82559_eeprom.srec +BIN += 82559_eeprom.bin 82559_eeprom endif ifeq ($(ARCH),ppc) -ELF += sched -SREC += sched.srec -BIN += sched.bin +SREC += sched.srec +BIN += sched.bin sched endif ifeq ($(ARCH),blackfin) -ELF += smc91111_eeprom SREC += smc91111_eeprom.srec -BIN += smc91111_eeprom.bin +BIN += smc91111_eeprom.bin smc91111_eeprom endif # The following example is pretty 8xx specific... ifeq ($(CPU),mpc8xx) -ELF += timer -SREC += timer.srec -BIN += timer.bin +SREC += timer.srec +BIN += timer.bin timer endif # The following example is 8260 specific... ifeq ($(CPU),mpc8260) -ELF += mem_to_mem_idma2intr -SREC += mem_to_mem_idma2intr.srec -BIN += mem_to_mem_idma2intr.bin -endif - -# Demo for 52xx IRQs -ifeq ($(CPU),mpc5xxx) -ELF += interrupt -SREC += interrupt.srec -BIN += interrupt.bin +SREC += mem_to_mem_idma2intr.srec +BIN += mem_to_mem_idma2intr.bin mem_to_mem_idma2intr endif # Utility for resetting i82559 EEPROM ifeq ($(BOARD),oxc) -ELF += eepro100_eeprom -SREC += eepro100_eeprom.srec -BIN += eepro100_eeprom.bin +SREC += eepro100_eeprom.srec +BIN += eepro100_eeprom.bin eepro100_eeprom endif ifeq ($(BIG_ENDIAN),y) EX_LDFLAGS += -EB endif -COBJS := $(SREC:.srec=.o) +OBJS = $(SREC:.srec=.o) -LIB = $(obj)libstubs.a +LIB = libstubs.a LIBAOBJS= ifeq ($(ARCH),ppc) LIBAOBJS+= $(ARCH)_longjmp.o $(ARCH)_setjmp.o @@ -146,45 +119,36 @@ ifeq ($(CPU),mpc8xx) LIBAOBJS+= test_burst_lib.o endif LIBCOBJS= stubs.o - -LIBOBJS = $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS)) - -SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(if $(LIBAOBJS),$(LIBAOBJS:.o=.S)) -OBJS := $(addprefix $(obj),$(COBJS)) -ELF := $(addprefix $(obj),$(ELF)) -BIN := $(addprefix $(obj),$(BIN)) -SREC := $(addprefix $(obj),$(SREC)) +LIBOBJS = $(LIBAOBJS) $(LIBCOBJS) gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`) CPPFLAGS += -I.. -all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF) +all: .depend $(OBJS) $(LIB) $(SREC) $(BIN) ######################################################################### -$(LIB): $(obj).depend $(LIBOBJS) - $(AR) $(ARFLAGS) $@ $(LIBOBJS) - -$(ELF): -$(obj)%: $(obj)%.o $(LIB) - $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ - -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ - -L$(gcclibdir) -lgcc +$(LIB): .depend $(LIBOBJS) + $(AR) crv $@ $(LIBOBJS) +%: %.o $(LIB) + $(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \ + -o $@ -e $(<:.o=) $< $(LIB) \ + -L$(gcclibdir) -lgcc $(SREC): -$(obj)%.srec: $(obj)% - $(OBJCOPY) -O srec $< $@ 2>/dev/null +%.srec: % + $(OBJCOPY) -O srec $< $@ 2>/dev/null $(BIN): -$(obj)%.bin: $(obj)% - $(OBJCOPY) -O binary $< $@ 2>/dev/null +%.bin: % + $(OBJCOPY) -O binary $< $@ 2>/dev/null ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) + $(CC) -M $(CFLAGS) $(OBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/examples/eepro100_eeprom.c b/examples/eepro100_eeprom.c index 2b15d05ad..a52e68d4e 100644 --- a/examples/eepro100_eeprom.c +++ b/examples/eepro100_eeprom.c @@ -17,9 +17,8 @@ * and release the resulting code under the GPL. */ -/* avoid unnecessary memcpy function */ -#define __HAVE_ARCH_MEMCPY -#define _PPC_STRING_H_ +#define _PPC_STRING_H_ /* avoid unnecessary str/mem functions */ +#define _LINUX_STRING_H_ /* avoid unnecessary str/mem functions */ #include #include diff --git a/examples/mips.lds b/examples/mips.lds index aceb6e900..9d9849bf5 100644 --- a/examples/mips.lds +++ b/examples/mips.lds @@ -39,21 +39,21 @@ SECTIONS . = ALIGN(4); .data : { *(.data) } - . = .; - _gp = ALIGN(16) + 0x7ff0; + . = ALIGN(4); + .sdata : { *(.sdata) } - .got : { - __got_start = .; - *(.got) - __got_end = .; - } + _gp = ALIGN(16); + + __got_start = .; + .got : { *(.got) } + __got_end = .; .sdata : { *(.sdata) } . = ALIGN(4); __bss_start = .; - .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .sbss : { *(.sbss) } + .bss : { *(.bss) } _end = .; } diff --git a/examples/nios.lds b/examples/nios.lds index 18072f71b..dd5bfad7b 100644 --- a/examples/nios.lds +++ b/examples/nios.lds @@ -51,7 +51,7 @@ SECTIONS __bss_start = .; . = ALIGN(4); - .bss (NOLOAD) : + .bss : { *(.bss) } diff --git a/examples/nios2.lds b/examples/nios2.lds index 6a100dc2f..277a0a7a6 100644 --- a/examples/nios2.lds +++ b/examples/nios2.lds @@ -74,7 +74,7 @@ SECTIONS * bss follows. We keep it adjacent to simplify init code. */ __bss_start = .; - .sbss (NOLOAD) : + .sbss : { *(.sbss) *(.sbss.*) @@ -82,7 +82,7 @@ SECTIONS *(.scommon) } . = ALIGN(4); - .bss (NOLOAD) : + .bss : { *(.bss) *(.bss.*) diff --git a/examples/sched.c b/examples/sched.c index b32766fed..ae01e0b05 100644 --- a/examples/sched.c +++ b/examples/sched.c @@ -199,7 +199,7 @@ static void thread_yield (void) PDEBUG ("thread_yield: current tid=%d", current_tid); -#define SWITCH(new) \ +#define SWITCH(new) \ if(lthreads[new].state == STATE_RUNNABLE) { \ PDEBUG("thread_yield: %d match, ctx=0x%08x", \ new, \ @@ -207,11 +207,11 @@ static void thread_yield (void) if(setjmp(lthreads[current_tid].context) == 0) { \ current_tid = new; \ PDEBUG("thread_yield: tid %d returns 0", \ - new); \ + new); \ longjmp(lthreads[new].context, 1); \ } else { \ PDEBUG("thread_yield: tid %d returns 1", \ - new); \ + new); \ return; \ } \ } diff --git a/examples/smc91111_eeprom.c b/examples/smc91111_eeprom.c index 62347c7e3..98e3e86ff 100644 --- a/examples/smc91111_eeprom.c +++ b/examples/smc91111_eeprom.c @@ -29,19 +29,12 @@ #include #include -#include "../drivers/net/smc91111.h" - -#ifdef CONFIG_DRIVER_SMC91111 - -#ifdef pFIO0_DIR -# define pFIO_DIR pFIO0_DIR -# define pFIO_FLAG_S pFIO0_FLAG_S -#endif +#include "../drivers/smc91111.h" #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE #define EEPROM 0x1; #define MAC 0x2; -#define UNKNOWN 0x4; +#define UNKNOWN 0x4; void dump_reg (void); void dump_eeprom (void); @@ -66,9 +59,17 @@ int smc91111_eeprom (int argc, char *argv[]) return (0); } - *pFIO_DIR = 0x01; - *pFIO_FLAG_S = 0x01; - SSYNC(); + asm ("p2.h = 0xFFC0;"); + asm ("p2.l = 0x0730;"); + asm ("r0 = 0x01;"); + asm ("w[p2] = r0;"); + asm ("ssync;"); + + asm ("p2.h = 0xffc0;"); + asm ("p2.l = 0x0708;"); + asm ("r0 = 0x01;"); + asm ("w[p2] = r0;"); + asm ("ssync;"); if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { printf ("Can't find SMSC91111\n"); @@ -386,13 +387,3 @@ void dump_reg (void) printf ("\n"); } } - -#else - -int smc91111_eeprom (int argc, char *argv[]) -{ - printf("Not supported for this board\n"); - return 1; -} - -#endif diff --git a/examples/stubs.c b/examples/stubs.c index ec5353216..d5b567667 100644 --- a/examples/stubs.c +++ b/examples/stubs.c @@ -25,14 +25,14 @@ gd_t *global_data; : : "i"(XF_ ## x * sizeof(void *)) : "eax", "ecx"); #elif defined(CONFIG_PPC) /* - * r2 holds the pointer to the global_data, r11 is a call-clobbered + * r29 holds the pointer to the global_data, r11 is a call-clobbered * register */ #define EXPORT_FUNC(x) \ asm volatile ( \ " .globl " #x "\n" \ #x ":\n" \ -" lwz %%r11, %0(%%r2)\n" \ +" lwz %%r11, %0(%%r29)\n" \ " lwz %%r11, %1(%%r11)\n" \ " mtctr %%r11\n" \ " bctr\n" \ @@ -132,57 +132,12 @@ gd_t *global_data; */ #define EXPORT_FUNC(x) \ asm volatile ( \ -" .globl _" #x "\n_" \ +" .globl " #x "\n" \ #x ":\n" \ " P0 = [P5 + %0]\n" \ " P0 = [P0 + %1]\n" \ " JUMP (P0)\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0"); -#elif defined(CONFIG_AVR32) -/* - * r6 holds the pointer to the global_data. r8 is call clobbered. - */ -#define EXPORT_FUNC(x) \ - asm volatile( \ - " .globl\t" #x "\n" \ - #x ":\n" \ - " ld.w r8, r6[%0]\n" \ - " ld.w pc, r8[%1]\n" \ - : \ - : "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \ - : "r8"); -#elif defined(CONFIG_SH) -/* - * r13 holds the pointer to the global_data. r1 is a call clobbered. - */ -#define EXPORT_FUNC(x) \ - asm volatile ( \ - " .align 2\n" \ - " .globl " #x "\n" \ - #x ":\n" \ - " mov r13, r1\n" \ - " add %0, r1\n" \ - " add %1, r1\n" \ - " jmp @r1\n" \ - " nop\n" \ - " nop\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1"); -#elif defined(CONFIG_SPARC) -/* - * g7 holds the pointer to the global_data. g1 is call clobbered. - */ -#define EXPORT_FUNC(x) \ - asm volatile( \ -" .globl\t" #x "\n" \ -#x ":\n" \ -" set %0, %%g1\n" \ -" or %%g1, %%g7, %%g1\n" \ -" ld [%%g1], %%g1\n" \ -" ld [%%g1 + %1], %%g1\n" \ -" call %%g1\n" \ -" nop\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x) : "g1" ); - #else #error stubs definition missing for this architecture #endif @@ -206,7 +161,7 @@ extern unsigned long __bss_start, _end; void app_startup(char **argv) { - unsigned char * cp = (unsigned char *) &__bss_start; + unsigned char * cp = (unsigned char *)&__bss_start; /* Zero out BSS */ while (cp < (unsigned char *)&_end) { diff --git a/examples/test_burst.c b/examples/test_burst.c index d8c5ed4a9..f09707ff9 100644 --- a/examples/test_burst.c +++ b/examples/test_burst.c @@ -173,7 +173,7 @@ static int test_burst_start (unsigned long size, unsigned long pattern) int i, n; int res = 1; - printf ("Test pattern %08lx ...", pattern); + printf ("Test pattern %08x ...", pattern); n = size / 4; @@ -248,7 +248,7 @@ static void test_desc(unsigned long size) { printf( "The following tests will be conducted:\n" - "1) Map %ld-byte region of physical RAM at 0x%08x\n" + "1) Map %d-byte region of physical RAM at 0x%08x\n" " into two virtual regions:\n" " one cached at 0x%08x and\n" " the the other uncached at 0x%08x.\n", @@ -277,8 +277,8 @@ static void test_error( p[1] = val; p[2] = pattern; - printf ("\nError at step %s, addr %08lx: read %08lx, pattern %08lx", - step, (unsigned long)addr, val, pattern); + printf ("\nError at step %s, addr %08x: read %08x, pattern %08x", + step, addr, val, pattern); } static void signal_init(void) diff --git a/examples/test_burst_lib.S b/examples/test_burst_lib.S index aef4e3242..5bb498142 100644 --- a/examples/test_burst_lib.S +++ b/examples/test_burst_lib.S @@ -70,7 +70,7 @@ mmu_init: * we can load the instruction and data TLB registers with the * same values. */ - lwz r9,20(r2) /* gd->ram_size */ + lwz r9,20(r29) /* gd->ram_size */ addis r9,r9,-0x80 mr r8, r9 /* Higher 8 Meg in SDRAM */ diff --git a/examples/timer.c b/examples/timer.c index 6628b21de..13ec06f02 100644 --- a/examples/timer.c +++ b/examples/timer.c @@ -253,7 +253,7 @@ int timer (int argc, char *argv[]) ); #endif } else { - printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n"); + printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n"); } printf (usage); } diff --git a/examples/x86-testapp.c b/examples/x86-testapp.c index e8603d9ba..a1ab319ae 100644 --- a/examples/x86-testapp.c +++ b/examples/x86-testapp.c @@ -30,11 +30,11 @@ asm volatile ( \ asm volatile ( \ " .globl mon_" #x "\n" \ "mon_" #x ":\n" \ -" lwz %%r11, %0(%%r2)\n" \ +" lwz %%r11, %0(%%r29)\n" \ " lwz %%r11, %1(%%r11)\n" \ " mtctr %%r11\n" \ " bctr\n" \ - : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "r11", "r2"); + : : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "r11", "r29"); #elif defined(__arm__) #define EXPORT_FUNC(x) \ asm volatile ( \ @@ -67,7 +67,7 @@ int main(void) #if defined(__i386__) xxx_t *pq; #elif defined(__powerpc__) - register volatile xxx_t *pq asm("r2"); + register volatile xxx_t *pq asm("r29"); #elif defined(__arm__) register volatile xxx_t *pq asm("r8"); #elif defined(__mips__) diff --git a/fs/Makefile b/fs/Makefile index 273d90e01..79cbdeaa7 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -24,6 +24,6 @@ SUBDIRS := jffs2 cramfs fdos fat reiserfs ext2 -$(obj).depend all: +.depend all: @for dir in $(SUBDIRS) ; do \ $(MAKE) -C $$dir $@ ; done diff --git a/fs/cramfs/Makefile b/fs/cramfs/Makefile index 13c043fcd..54a475ef8 100644 --- a/fs/cramfs/Makefile +++ b/fs/cramfs/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,27 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)libcramfs.a +LIB = libcramfs.a AOBJS = COBJS = cramfs.o uncompress.o - -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) +OBJS = $(AOBJS) $(COBJS) #CPPFLAGS += all: $(LIB) $(AOBJS) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/fs/cramfs/cramfs.c b/fs/cramfs/cramfs.c index e53c783e5..48e7f63aa 100644 --- a/fs/cramfs/cramfs.c +++ b/fs/cramfs/cramfs.c @@ -27,7 +27,7 @@ #include #include -#if defined(CONFIG_CMD_CRAMFS) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) #include #include diff --git a/fs/cramfs/uncompress.c b/fs/cramfs/uncompress.c index cf6796790..170832a9c 100644 --- a/fs/cramfs/uncompress.c +++ b/fs/cramfs/uncompress.c @@ -25,12 +25,28 @@ #include #include -#if defined(CONFIG_CMD_CRAMFS) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) static z_stream stream; -void *zalloc(void *, unsigned, unsigned); -void zfree(void *, void *, unsigned); +#define ZALLOC_ALIGNMENT 16 + +static void *zalloc (void *x, unsigned items, unsigned size) +{ + void *p; + + size *= items; + size = (size + ZALLOC_ALIGNMENT - 1) & ~(ZALLOC_ALIGNMENT - 1); + + p = malloc (size); + + return (p); +} + +static void zfree (void *x, void *addr, unsigned nb) +{ + free (addr); +} /* Returns length of decompressed data. */ int cramfs_uncompress_block (void *dst, void *src, int srclen) diff --git a/fs/ext2/Makefile b/fs/ext2/Makefile index 8313cdc17..3b193684f 100644 --- a/fs/ext2/Makefile +++ b/fs/ext2/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2003 # Pavel Bartusek, Sysgo Real-Time Solutions AG, pba@sysgo.de # @@ -27,26 +24,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)libext2fs.a +LIB = libext2fs.a AOBJS = COBJS = ext2fs.o dev.o - -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) +OBJS = $(AOBJS) $(COBJS) #CPPFLAGS += all: $(LIB) $(AOBJS) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/fs/ext2/dev.c b/fs/ext2/dev.c index 1728b34fc..69a58bb77 100644 --- a/fs/ext2/dev.c +++ b/fs/ext2/dev.c @@ -25,7 +25,7 @@ #include -#if defined(CONFIG_CMD_EXT2) +#if (CONFIG_COMMANDS & CFG_CMD_EXT2) #include #include @@ -139,4 +139,4 @@ int ext2fs_devread (int sector, int byte_offset, int byte_len, char *buf) { } return (1); } -#endif +#endif /* CFG_CMD_EXT2FS */ diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c index 78335510e..407cac16a 100644 --- a/fs/ext2/ext2fs.c +++ b/fs/ext2/ext2fs.c @@ -25,7 +25,7 @@ #include -#if defined(CONFIG_CMD_EXT2) +#if (CONFIG_COMMANDS & CFG_CMD_EXT2) #include #include #include @@ -875,4 +875,4 @@ fail: return (0); } -#endif +#endif /* CFG_CMD_EXT2FS */ diff --git a/fs/fat/Makefile b/fs/fat/Makefile index 87af73b7e..e4627577b 100644 --- a/fs/fat/Makefile +++ b/fs/fat/Makefile @@ -19,27 +19,28 @@ # MA 02111-1307 USA # +TOPDIR=../../ + include $(TOPDIR)/config.mk -LIB = $(obj)libfat.a +LIB = libfat.a AOBJS = COBJS = fat.o file.o -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) +OBJS = $(AOBJS) $(COBJS) all: $(LIB) $(AOBJS) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 49c78ed79..99a5eebe1 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -31,7 +31,7 @@ #include #include -#if defined(CONFIG_CMD_FAT) +#if (CONFIG_COMMANDS & CFG_CMD_FAT) /* * Convert a string to lowercase. @@ -51,7 +51,8 @@ static int cur_part = 1; #define DOS_PART_TBL_OFFSET 0x1be #define DOS_PART_MAGIC_OFFSET 0x1fe -#define DOS_FS_TYPE_OFFSET 0x36 +//#define DOS_FS_TYPE_OFFSET 0x36 +#define DOS_FS_TYPE_OFFSET 0x52 int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) { @@ -59,8 +60,7 @@ int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) if (cur_dev == NULL) return -1; if (cur_dev->block_read) { - return cur_dev->block_read (cur_dev->dev - , startblock, getsize, (unsigned long *)bufptr); + return cur_dev->block_read (cur_dev->dev, startblock, getsize, (unsigned long *)bufptr); } return -1; } @@ -70,11 +70,10 @@ int fat_register_device(block_dev_desc_t *dev_desc, int part_no) { unsigned char buffer[SECTOR_SIZE]; - disk_partition_t info; if (!dev_desc->block_read) return -1; - cur_dev = dev_desc; + cur_dev=dev_desc; /* check if we have a MBR (on floppies we have only a PBR) */ if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) { printf ("** Can't read from device %d **\n", dev_desc->dev); @@ -85,41 +84,35 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) /* no signature found */ return -1; } -#if (defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) || \ - defined(CONFIG_SYSTEMACE) ) - /* First we assume, there is a MBR */ - if (!get_partition_info (dev_desc, part_no, &info)) { - part_offset = info.start; - cur_part = part_no; - } else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) { + if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { /* ok, we assume we are on a PBR only */ cur_part = 1; - part_offset = 0; - } else { - printf ("** Partition %d not valid on device %d **\n", - part_no, dev_desc->dev); - return -1; + part_offset=0; } - + else { +#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || (CONFIG_COMMANDS & CFG_CMD_MMC) || \ + defined(CONFIG_SYSTEMACE) + disk_partition_t info; + if(!get_partition_info(dev_desc, part_no, &info)) { + part_offset = info.start; + cur_part = part_no; + } + else { + printf ("** Partition %d not valid on device %d **\n",part_no,dev_desc->dev); + return -1; + } #else - if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { - /* ok, we assume we are on a PBR only */ - cur_part = 1; - part_offset = 0; - info.start = part_offset; - } else { /* FIXME we need to determine the start block of the * partition where the DOS FS resides. This can be done * by using the get_partition_info routine. For this * purpose the libpart must be included. */ - part_offset = 32; + //part_offset=32; + part_offset=63; cur_part = 1; - } #endif + } return 0; } @@ -223,7 +216,7 @@ get_fatent(fsdata *mydata, __u32 entry) /* Read a new block of FAT entries into the cache. */ if (bufnum != mydata->fatbufnum) { int getsize = FATBUFSIZE/FS_BLOCK_SIZE; - __u8 *bufptr = mydata->fatbuf; + __u8 *bufptr = (__u8 *)mydata->fatbuf; __u32 fatlength = mydata->fatlength; __u32 startblock = bufnum * FATBUFBLOCKS; @@ -309,7 +302,7 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer, unsigned long size) if(size % FS_BLOCK_SIZE) { __u8 tmpbuf[FS_BLOCK_SIZE]; idx= size/FS_BLOCK_SIZE; - if (disk_read(startsect + idx, 1, tmpbuf) < 0) { + if (disk_read((startsect + idx), 1, tmpbuf) < 0) { FAT_DPRINT("Error reading data\n"); return -1; } @@ -653,9 +646,9 @@ static dir_entry *get_dentfromdir (fsdata * mydata, int startsect, } curclust = get_fatent (mydata, curclust); if (CHECK_CLUST(curclust, mydata->fatsize)) { - FAT_DPRINT ("curclust: 0x%x\n", curclust); - FAT_ERROR ("Invalid FAT entry\n"); - return NULL; + FAT_DPRINT("curclust: 0x%x\n", curclust); + FAT_ERROR("Invalid FAT entry\n"); + return NULL; } } @@ -981,10 +974,8 @@ file_fat_detectfs(void) printf("No current device\n"); return 1; } -#if defined(CONFIG_CMD_IDE) || \ - defined(CONFIG_CMD_SCSI) || \ - defined(CONFIG_CMD_USB) || \ - defined(CONFIG_MMC) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || defined(CONFIG_MMC) printf("Interface: "); switch(cur_dev->if_type) { case IF_TYPE_IDE : printf("IDE"); break; @@ -1005,8 +996,7 @@ file_fat_detectfs(void) memcpy (vol_label, volinfo.volume_label, 11); vol_label[11] = '\0'; volinfo.fs_type[5]='\0'; - printf("Partition %d: Filesystem: %s \"%s\"\n" - ,cur_part,volinfo.fs_type,vol_label); + printf("Partition %d: Filesystem: %s \"%s\"\n",cur_part,volinfo.fs_type,vol_label); return 0; } @@ -1021,8 +1011,11 @@ file_fat_ls(const char *dir) long file_fat_read(const char *filename, void *buffer, unsigned long maxsize) { - printf("reading %s\n",filename); - return do_fat_read(filename, buffer, maxsize, LS_NO); + //printf("reading %s\n",filename); + //return do_fat_read(filename, buffer, maxsize, LS_NO); + long ret; + ret = do_fat_read(filename, buffer, maxsize, LS_NO); + return ret; } -#endif +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FAT) */ diff --git a/fs/fat/file.c b/fs/fat/file.c index 514dbaecb..f999ac5a2 100644 --- a/fs/fat/file.c +++ b/fs/fat/file.c @@ -32,7 +32,7 @@ #include #include -#if defined(CONFIG_CMD_FAT) +#if (CONFIG_COMMANDS & CFG_CMD_FAT) /* Supported filesystems */ static const struct filesystem filesystems[] = { @@ -205,4 +205,4 @@ file_read(const char *filename, void *buffer, unsigned long maxsize) return filesystems[current_filesystem].read(arg, buffer, maxsize); } -#endif +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FAT) */ diff --git a/fs/fdos/Makefile b/fs/fdos/Makefile index 2dba0fb69..c25e744b9 100644 --- a/fs/fdos/Makefile +++ b/fs/fdos/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2002 # Stäubli Faverges - # Pierre AUBERT p.aubert@staubli.com @@ -28,27 +25,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)libfdos.a +LIB = libfdos.a AOBJS = COBJS = fat.o vfat.o dev.o fdos.o fs.o subdir.o - -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) +OBJS = $(AOBJS) $(COBJS) #CPPFLAGS += all: $(LIB) $(AOBJS) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/fs/fdos/dev.c b/fs/fdos/dev.c index 271d0e790..5dea5cd78 100644 --- a/fs/fdos/dev.c +++ b/fs/fdos/dev.c @@ -28,7 +28,7 @@ #include "dos.h" #include "fdos.h" -#if defined(CONFIG_CMD_FDOS) +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) #define NB_HEADS 2 #define NB_TRACKS 80 diff --git a/fs/fdos/fat.c b/fs/fdos/fat.c index 2e2d2b8ce..2ef2371e1 100644 --- a/fs/fdos/fat.c +++ b/fs/fdos/fat.c @@ -26,7 +26,7 @@ #include #include -#if defined(CONFIG_CMD_FDOS) +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) #include "dos.h" #include "fdos.h" diff --git a/fs/fdos/fdos.c b/fs/fdos/fdos.c index 5be6a960e..a29f43d97 100644 --- a/fs/fdos/fdos.c +++ b/fs/fdos/fdos.c @@ -25,7 +25,7 @@ #include #include -#if defined(CONFIG_CMD_FDOS) +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) #include #include "dos.h" #include "fdos.h" diff --git a/fs/fdos/fs.c b/fs/fdos/fs.c index aded6708d..3b9d09e49 100644 --- a/fs/fdos/fs.c +++ b/fs/fdos/fs.c @@ -26,7 +26,7 @@ #include #include -#if defined(CONFIG_CMD_FDOS) +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) #include "dos.h" #include "fdos.h" diff --git a/fs/fdos/subdir.c b/fs/fdos/subdir.c index 497f554f9..97b25047a 100644 --- a/fs/fdos/subdir.c +++ b/fs/fdos/subdir.c @@ -26,7 +26,7 @@ #include #include -#if defined(CONFIG_CMD_FDOS) +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) #include "dos.h" #include "fdos.h" diff --git a/fs/fdos/vfat.c b/fs/fdos/vfat.c index 0e7883b0a..46a464b29 100644 --- a/fs/fdos/vfat.c +++ b/fs/fdos/vfat.c @@ -25,7 +25,7 @@ #include #include -#if defined(CONFIG_CMD_FDOS) +#if (CONFIG_COMMANDS & CFG_CMD_FDOS) #include #include "dos.h" diff --git a/fs/jffs2/Makefile b/fs/jffs2/Makefile index a071af1f6..f28b17a41 100644 --- a/fs/jffs2/Makefile +++ b/fs/jffs2/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,34 +23,26 @@ include $(TOPDIR)/config.mk -LIB = $(obj)libjffs2.a +LIB = libjffs2.a AOBJS = -COBJS-y += jffs2_1pass.o -COBJS-y += compr_rtime.o -COBJS-y += compr_rubin.o -COBJS-y += compr_zlib.o -COBJS-y += mini_inflate.o -COBJS-y += compr_lzo.o -COBJS-y += compr_lzari.o - -COBJS := $(COBJS-y) -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) +COBJS = jffs2_1pass.o compr_rtime.o compr_rubin.o compr_zlib.o mini_inflate.o +COBJS += compr_lzo.o compr_lzari.o +OBJS = $(AOBJS) $(COBJS) #CPPFLAGS += all: $(LIB) $(AOBJS) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/fs/jffs2/compr_lzari.c b/fs/jffs2/compr_lzari.c index f64bc74a9..828b6e551 100644 --- a/fs/jffs2/compr_lzari.c +++ b/fs/jffs2/compr_lzari.c @@ -50,7 +50,7 @@ All rights reserved. Permission granted for non-commercial use. #include -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI) +#if ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI)) #include #include @@ -259,4 +259,4 @@ int lzari_decompress(unsigned char *data_in, unsigned char *cpage_out, { return Decode(data_in, cpage_out, srclen, destlen); } -#endif +#endif /* ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI)) */ diff --git a/fs/jffs2/compr_lzo.c b/fs/jffs2/compr_lzo.c index a32b9934e..b6c590ac8 100644 --- a/fs/jffs2/compr_lzo.c +++ b/fs/jffs2/compr_lzo.c @@ -67,7 +67,7 @@ #include -#if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI) +#if ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI)) #include #include @@ -402,4 +402,4 @@ int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out, return lzo1x_decompress (data_in, srclen, cpage_out, &outlen, NULL); } -#endif +#endif /* ((CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CONFIG_JFFS2_LZO_LZARI)) */ diff --git a/fs/jffs2/compr_rtime.c b/fs/jffs2/compr_rtime.c index 144263c42..9bb4f1bcb 100644 --- a/fs/jffs2/compr_rtime.c +++ b/fs/jffs2/compr_rtime.c @@ -46,7 +46,7 @@ */ #include -#if defined(CONFIG_CMD_JFFS2) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) #include @@ -88,4 +88,4 @@ void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out, } } -#endif +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/compr_rubin.c b/fs/jffs2/compr_rubin.c index f6f3fa1b5..74577d9c6 100644 --- a/fs/jffs2/compr_rubin.c +++ b/fs/jffs2/compr_rubin.c @@ -39,7 +39,7 @@ */ #include -#if defined(CONFIG_CMD_JFFS2) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) #include #include @@ -123,4 +123,4 @@ void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, rubin_do_decompress(bits, data_in+8, cpage_out, dstlen); } -#endif +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/compr_zlib.c b/fs/jffs2/compr_zlib.c index 29dfe1b66..1b35585ee 100644 --- a/fs/jffs2/compr_zlib.c +++ b/fs/jffs2/compr_zlib.c @@ -37,7 +37,7 @@ #include #include -#if defined(CONFIG_CMD_JFFS2) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) #include #include @@ -45,8 +45,8 @@ long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, __u32 srclen, __u32 destlen) { - return (decompress_block(cpage_out, data_in + 2, (void *) ldr_memcpy)); + return (decompress_block(cpage_out, data_in + 2, ldr_memcpy)); } -#endif +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 8a06777ae..41ff4c1fb 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -52,7 +52,7 @@ * for a bootloader as small and simple as possible. Instead of worring about * unneccesary data copies, node scans, etc, I just optimized for the known * common case, a kernel, which looks like: - * (1) most pages are 4096 bytes + * (1) most pages are 4096 bytes * (2) version numbers are somewhat sorted in acsending order * (3) multiple compressed blocks making up one page is uncommon * @@ -116,9 +116,8 @@ #include #include #include -#include -#if defined(CONFIG_CMD_JFFS2) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) #include #include @@ -126,13 +125,13 @@ #include "jffs2_private.h" -#define NODE_CHUNK 1024 /* size of memory allocation chunk in b_nodes */ -#define SPIN_BLKSIZE 18 /* spin after having scanned 1< #else @@ -165,6 +163,9 @@ static struct part_info *current_part; /* this one defined in nand_legacy.c */ int read_jffs2_nand(size_t start, size_t len, size_t * retlen, u_char * buf, int nanddev); +#else +/* info for NAND chips, defined in drivers/nand/nand.c */ +extern nand_info_t nand_info[]; #endif #define NAND_PAGE_SIZE 512 @@ -183,7 +184,11 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf) { struct mtdids *id = current_part->dev->id; u32 bytes_read = 0; +#if defined(CFG_NAND_LEGACY) size_t retlen; +#else + ulong retlen; +#endif int cpy_bytes; while (bytes_read < size) { @@ -269,10 +274,10 @@ static void put_fl_mem_nand(void *buf) { free(buf); } -#endif +#endif /* #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */ -#if defined(CONFIG_CMD_FLASH) +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) /* * Support for jffs2 on top of NOR-flash * @@ -295,7 +300,7 @@ static inline void *get_node_mem_nor(u32 off) { return (void*)get_fl_mem_nor(off); } -#endif +#endif /* #if (CONFIG_COMMANDS & CFG_CMD_FLASH) */ /* @@ -306,12 +311,12 @@ static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf) { struct mtdids *id = current_part->dev->id; -#if defined(CONFIG_CMD_FLASH) +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) if (id->type == MTD_DEV_TYPE_NOR) return get_fl_mem_nor(off); #endif -#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) if (id->type == MTD_DEV_TYPE_NAND) return get_fl_mem_nand(off, size, ext_buf); #endif @@ -324,13 +329,12 @@ static inline void *get_node_mem(u32 off) { struct mtdids *id = current_part->dev->id; -#if defined(CONFIG_CMD_FLASH) +#if (CONFIG_COMMANDS & CFG_CMD_FLASH) if (id->type == MTD_DEV_TYPE_NOR) return get_node_mem_nor(off); #endif -#if defined(CONFIG_JFFS2_NAND) && \ - defined(CONFIG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) if (id->type == MTD_DEV_TYPE_NAND) return get_node_mem_nand(off); #endif @@ -341,8 +345,7 @@ static inline void *get_node_mem(u32 off) static inline void put_fl_mem(void *buf) { -#if defined(CONFIG_JFFS2_NAND) && \ - defined(CONFIG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) struct mtdids *id = current_part->dev->id; if (id->type == MTD_DEV_TYPE_NAND) @@ -739,7 +742,7 @@ jffs2_1pass_find_inode(struct b_lists * pL, const char *name, u32 pino) } if (jDir->version == version && inode != 0) { - /* I'm pretty sure this isn't legal */ + /* I'm pretty sure this isn't legal */ putstr(" ** ERROR ** "); putnstr(jDir->name, jDir->nsize); putLabeledWord(" has dup version =", version); @@ -957,13 +960,13 @@ jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino) for(b = pL->dir.listHead; b; b = b->next) { jDir = (struct jffs2_raw_dirent *) get_node_mem(b->offset); if (ino == jDir->ino) { - if (jDir->version < version) { + if (jDir->version < version) { put_fl_mem(jDir); continue; } if (jDir->version == version && jDirFoundType) { - /* I'm pretty sure this isn't legal */ + /* I'm pretty sure this isn't legal */ putstr(" ** ERROR ** "); putnstr(jDir->name, jDir->nsize); putLabeledWord(" has dup version (resolve) = ", @@ -1149,7 +1152,7 @@ dump_dirents(struct b_lists *pL) putLabeledWord("\tbuild_list: type = ", jDir->type); putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc); putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc); - putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */ + putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */ b = b->next; put_fl_mem(jDir); } @@ -1181,13 +1184,11 @@ jffs2_1pass_build_lists(struct part_info * part) /* start at the beginning of the partition */ while (offset < max) { - if ((oldoffset >> SPIN_BLKSIZE) != (offset >> SPIN_BLKSIZE)) { + if ((oldoffset >> SPIN_BLKSIZE) != (offset >> SPIN_BLKSIZE)) { printf("\b\b%c ", spinner[counter++ % sizeof(spinner)]); oldoffset = offset; } - WATCHDOG_RESET(); - node = (struct jffs2_unknown_node *) get_node_mem((u32)part->offset + offset); if (node->magic == JFFS2_MAGIC_BITMASK && hdr_crc(node)) { /* if its a fragment add it */ @@ -1213,18 +1214,16 @@ jffs2_1pass_build_lists(struct part_info * part) } else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) { if (node->totlen != sizeof(struct jffs2_unknown_node)) printf("OOPS Cleanmarker has bad size " - "%d != %zu\n", - node->totlen, + "%d != %d\n", node->totlen, sizeof(struct jffs2_unknown_node)); } else if (node->nodetype == JFFS2_NODETYPE_PADDING) { if (node->totlen < sizeof(struct jffs2_unknown_node)) printf("OOPS Padding has bad size " - "%d < %zu\n", - node->totlen, + "%d < %d\n", node->totlen, sizeof(struct jffs2_unknown_node)); } else { - printf("Unknown node type: %x len %d offset 0x%x\n", - node->nodetype, + printf("Unknown node type: %x len %d " + "offset 0x%x\n", node->nodetype, node->totlen, offset); } offset += ((node->totlen + 3) & ~3); @@ -1395,4 +1394,4 @@ jffs2_1pass_info(struct part_info * part) return 1; } -#endif +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c index 3ce9c9825..e78af7578 100644 --- a/fs/jffs2/jffs2_nand_1pass.c +++ b/fs/jffs2/jffs2_nand_1pass.c @@ -1,6 +1,6 @@ #include -#if !defined(CFG_NAND_LEGACY) && defined(CONFIG_CMD_JFFS2) +#if !defined(CFG_NAND_LEGACY) && (CONFIG_COMMANDS & CFG_CMD_JFFS2) #include #include @@ -758,7 +758,7 @@ dump_dirents(struct b_lists *pL) putLabeledWord("\tbuild_list: type = ", jDir->type); putLabeledWord("\tbuild_list: node_crc = ", jDir->node_crc); putLabeledWord("\tbuild_list: name_crc = ", jDir->name_crc); - putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */ + putLabeledWord("\tbuild_list: offset = ", b->offset); /* FIXME: ? [RS] */ b = b->next; put_fl_mem(jDir); } @@ -864,18 +864,16 @@ jffs2_1pass_build_lists(struct part_info * part) } else if (node->nodetype == JFFS2_NODETYPE_CLEANMARKER) { if (node->totlen != sizeof(struct jffs2_unknown_node)) printf("OOPS Cleanmarker has bad size " - "%d != %zu\n", - node->totlen, + "%d != %d\n", node->totlen, sizeof(struct jffs2_unknown_node)); } else if (node->nodetype == JFFS2_NODETYPE_PADDING) { if (node->totlen < sizeof(struct jffs2_unknown_node)) printf("OOPS Padding has bad size " - "%d < %zu\n", - node->totlen, + "%d < %d\n", node->totlen, sizeof(struct jffs2_unknown_node)); } else { - printf("Unknown node type: %x len %d offset 0x%x\n", - node->nodetype, + printf("Unknown node type: %x len %d " + "offset 0x%x\n", node->nodetype, node->totlen, offset); } offset += ((node->totlen + 3) & ~3); @@ -1035,4 +1033,4 @@ jffs2_1pass_info(struct part_info * part) return 1; } -#endif +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/jffs2/mini_inflate.c b/fs/jffs2/mini_inflate.c index 4c50fc32d..4f511ec1a 100644 --- a/fs/jffs2/mini_inflate.c +++ b/fs/jffs2/mini_inflate.c @@ -25,7 +25,7 @@ #include -#if defined(CONFIG_CMD_JFFS2) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) #include @@ -393,4 +393,4 @@ long decompress_block(unsigned char *dest, unsigned char *source, return stream.error ? -stream.error : stream.decoded; } -#endif +#endif /* CFG_CMD_JFFS2 */ diff --git a/fs/reiserfs/Makefile b/fs/reiserfs/Makefile index e8711a411..98a9a8d30 100644 --- a/fs/reiserfs/Makefile +++ b/fs/reiserfs/Makefile @@ -1,7 +1,4 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# # (C) Copyright 2003 # Pavel Bartusek, Sysgo Real-Time Solutions AG, pba@sysgo.de # @@ -27,26 +24,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)libreiserfs.a +LIB = libreiserfs.a AOBJS = COBJS = reiserfs.o dev.o mode_string.o - -SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) +OBJS = $(AOBJS) $(COBJS) #CPPFLAGS += all: $(LIB) $(AOBJS) -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + ######################################################################### -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c) + $(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@ -sinclude $(obj).depend +sinclude .depend ######################################################################### diff --git a/fs/reiserfs/dev.c b/fs/reiserfs/dev.c index 46dc41463..6f6056f33 100644 --- a/fs/reiserfs/dev.c +++ b/fs/reiserfs/dev.c @@ -19,7 +19,7 @@ #include -#if defined(CONFIG_CMD_REISER) +#if (CONFIG_COMMANDS & CFG_CMD_REISER) #include #include @@ -35,7 +35,7 @@ int reiserfs_set_blk_dev(block_dev_desc_t *rbdd, int part) reiserfs_block_dev_desc = rbdd; if (part == 0) { - /* disk doesn't use partition table */ + /* disk doesn't use partition table */ part_info.start = 0; part_info.size = rbdd->lba; part_info.blksz = rbdd->blksz; @@ -120,4 +120,4 @@ int reiserfs_devread (int sector, int byte_offset, int byte_len, char *buf) return 1; } -#endif +#endif /* CFG_CMD_REISERFS */ diff --git a/fs/reiserfs/mode_string.c b/fs/reiserfs/mode_string.c index 3e57ee4a9..bc565fbdd 100644 --- a/fs/reiserfs/mode_string.c +++ b/fs/reiserfs/mode_string.c @@ -1,3 +1,4 @@ +/* vi: set sw=4 ts=4: */ /* * mode_string implementation for busybox * @@ -25,7 +26,7 @@ #include -#if defined(CONFIG_CMD_REISER) +#if (CONFIG_COMMANDS & CFG_CMD_REISER) #include #if ( S_ISUID != 04000 ) || ( S_ISGID != 02000 ) || ( S_ISVTX != 01000 ) \ @@ -138,4 +139,4 @@ const char *bb_mode_string(int mode) #endif -#endif +#endif /* CFG_CMD_REISER */ diff --git a/fs/reiserfs/reiserfs.c b/fs/reiserfs/reiserfs.c index aa9636163..31c25ebc7 100644 --- a/fs/reiserfs/reiserfs.c +++ b/fs/reiserfs/reiserfs.c @@ -29,7 +29,7 @@ */ #include -#if defined(CONFIG_CMD_REISER) +#if (CONFIG_COMMANDS & CFG_CMD_REISER) #include #include @@ -983,4 +983,4 @@ reiserfs_open (char *filename) return filemax; } -#endif +#endif /* CFG_CMD_REISER */ diff --git a/fs/reiserfs/reiserfs_private.h b/fs/reiserfs/reiserfs_private.h index ef7eaf01a..d0197cb80 100644 --- a/fs/reiserfs/reiserfs_private.h +++ b/fs/reiserfs/reiserfs_private.h @@ -44,37 +44,37 @@ /* This is the new super block of a journaling reiserfs system */ struct reiserfs_super_block { - __u32 s_block_count; /* blocks count */ - __u32 s_free_blocks; /* free blocks count */ - __u32 s_root_block; /* root block number */ - __u32 s_journal_block; /* journal block number */ - __u32 s_journal_dev; /* journal device number */ - __u32 s_journal_size; /* size of the journal on FS creation. used to make sure they don't overflow it */ - __u32 s_journal_trans_max; /* max number of blocks in a transaction. */ - __u32 s_journal_magic; /* random value made on fs creation */ - __u32 s_journal_max_batch; /* max number of blocks to batch into a trans */ - __u32 s_journal_max_commit_age; /* in seconds, how old can an async commit be */ - __u32 s_journal_max_trans_age; /* in seconds, how old can a transaction be */ - __u16 s_blocksize; /* block size */ - __u16 s_oid_maxsize; /* max size of object id array */ + __u32 s_block_count; /* blocks count */ + __u32 s_free_blocks; /* free blocks count */ + __u32 s_root_block; /* root block number */ + __u32 s_journal_block; /* journal block number */ + __u32 s_journal_dev; /* journal device number */ + __u32 s_journal_size; /* size of the journal on FS creation. used to make sure they don't overflow it */ + __u32 s_journal_trans_max; /* max number of blocks in a transaction. */ + __u32 s_journal_magic; /* random value made on fs creation */ + __u32 s_journal_max_batch; /* max number of blocks to batch into a trans */ + __u32 s_journal_max_commit_age; /* in seconds, how old can an async commit be */ + __u32 s_journal_max_trans_age; /* in seconds, how old can a transaction be */ + __u16 s_blocksize; /* block size */ + __u16 s_oid_maxsize; /* max size of object id array */ __u16 s_oid_cursize; /* current size of object id array */ - __u16 s_state; /* valid or error */ - char s_magic[16]; /* reiserfs magic string indicates that file system is reiserfs */ - __u16 s_tree_height; /* height of disk tree */ - __u16 s_bmap_nr; /* amount of bitmap blocks needed to address each block of file system */ + __u16 s_state; /* valid or error */ + char s_magic[16]; /* reiserfs magic string indicates that file system is reiserfs */ + __u16 s_tree_height; /* height of disk tree */ + __u16 s_bmap_nr; /* amount of bitmap blocks needed to address each block of file system */ __u16 s_version; char s_unused[128]; /* zero filled by mkreiserfs */ }; -#define sb_root_block(sbp) (__le32_to_cpu((sbp)->s_root_block)) -#define sb_journal_block(sbp) (__le32_to_cpu((sbp)->s_journal_block)) +#define sb_root_block(sbp) (__le32_to_cpu((sbp)->s_root_block)) +#define sb_journal_block(sbp) (__le32_to_cpu((sbp)->s_journal_block)) #define set_sb_journal_block(sbp,v) ((sbp)->s_journal_block = __cpu_to_le32(v)) -#define sb_journal_size(sbp) (__le32_to_cpu((sbp)->s_journal_size)) -#define sb_blocksize(sbp) (__le16_to_cpu((sbp)->s_blocksize)) +#define sb_journal_size(sbp) (__le32_to_cpu((sbp)->s_journal_size)) +#define sb_blocksize(sbp) (__le16_to_cpu((sbp)->s_blocksize)) #define set_sb_blocksize(sbp,v) ((sbp)->s_blocksize = __cpu_to_le16(v)) -#define sb_version(sbp) (__le16_to_cpu((sbp)->s_version)) -#define set_sb_version(sbp,v) ((sbp)->s_version = __cpu_to_le16(v)) +#define sb_version(sbp) (__le16_to_cpu((sbp)->s_version)) +#define set_sb_version(sbp,v) ((sbp)->s_version = __cpu_to_le16(v)) #define REISERFS_MAX_SUPPORTED_VERSION 2 @@ -137,7 +137,7 @@ struct offset_v1 * hashing the name and using few bits (23 or more) of the resulting * hash, and generation number that allows distinguishing names with * hash collisions. If number of collisions overflows generation - * number, we return EEXIST. High order bit is 0 always + * number, we return EEXIST. High order bit is 0 always */ __u32 k_offset; __u32 k_uniqueness; @@ -153,7 +153,7 @@ struct offset_v2 { * hashing the name and using few bits (23 or more) of the resulting * hash, and generation number that allows distinguishing names with * hash collisions. If number of collisions overflows generation - * number, we return EEXIST. High order bit is 0 always + * number, we return EEXIST. High order bit is 0 always */ #if defined(__LITTLE_ENDIAN_BITFIELD) @@ -192,8 +192,8 @@ static inline loff_t offset_v2_k_offset( const struct offset_v2 *v2 ) return tmp.offset_v2.k_offset; } #elif (__BYTE_ORDER == __LITTLE_ENDIAN) -# define offset_v2_k_type(v2) ((v2)->k_type) -# define offset_v2_k_offset(v2) ((v2)->k_offset) +# define offset_v2_k_type(v2) ((v2)->k_type) +# define offset_v2_k_offset(v2) ((v2)->k_offset) #else #error "__BYTE_ORDER must be __LITTLE_ENDIAN or __BIG_ENDIAN" #endif @@ -219,14 +219,14 @@ struct key or internal node, and not the header of an unformatted node. */ struct block_head { - __u16 blk_level; /* Level of a block in the tree. */ - __u16 blk_nr_item; /* Number of keys/items in a block. */ + __u16 blk_level; /* Level of a block in the tree. */ + __u16 blk_nr_item; /* Number of keys/items in a block. */ __u16 blk_free_space; /* Block free space in bytes. */ struct key blk_right_delim_key; /* Right delimiting key for this block (supported for leaf level nodes only) */ }; #define BLKH_SIZE (sizeof (struct block_head)) -#define DISK_LEAF_NODE_LEVEL 1 /* Leaf node level. */ +#define DISK_LEAF_NODE_LEVEL 1 /* Leaf node level. */ struct item_head { @@ -245,7 +245,7 @@ struct item_head number of directory entries in the directory item. */ __u16 ih_entry_count; } __attribute__ ((__packed__)) u; - __u16 ih_item_len; /* total size of the item body */ + __u16 ih_item_len; /* total size of the item body */ __u16 ih_item_location; /* an offset to the item body * within the block */ __u16 ih_version; /* 0 for all old items, 2 for new @@ -254,13 +254,13 @@ struct item_head done */ } __attribute__ ((__packed__)); -/* size of item header */ +/* size of item header */ #define IH_SIZE (sizeof (struct item_head)) #define ITEM_VERSION_1 0 #define ITEM_VERSION_2 1 -#define ih_version(ih) (__le16_to_cpu((ih)->ih_version)) +#define ih_version(ih) (__le16_to_cpu((ih)->ih_version)) #define IH_KEY_OFFSET(ih) (ih_version(ih) == ITEM_VERSION_1 \ ? __le32_to_cpu((ih)->ih_key.u.v1.k_offset) \ @@ -271,13 +271,13 @@ struct item_head : offset_v2_k_type(&((ih)->ih_key.u.v2)) == V2_##type) /***************************************************************************/ -/* DISK CHILD */ +/* DISK CHILD */ /***************************************************************************/ /* Disk child pointer: The pointer from an internal node of the tree to a node that is on disk. */ struct disk_child { - __u32 dc_block_number; /* Disk child's block number. */ - __u16 dc_size; /* Disk child's used space. */ + __u32 dc_block_number; /* Disk child's block number. */ + __u16 dc_size; /* Disk child's used space. */ __u16 dc_reserved; }; @@ -297,7 +297,7 @@ struct stat_data_v1 __u16 sd_gid; /* group */ __u32 sd_size; /* file size */ __u32 sd_atime; /* time of last access */ - __u32 sd_mtime; /* time file was last modified */ + __u32 sd_mtime; /* time file was last modified */ __u32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ union { __u32 sd_rdev; @@ -314,25 +314,25 @@ struct stat_data_v1 policy. Someday. -Hans */ } __attribute__ ((__packed__)); -#define stat_data_v1(ih) (ih_version(ih) == ITEM_VERSION_1) -#define sd_v1_mode(sdp) ((sdp)->sd_mode) -#define sd_v1_nlink(sdp) (__le16_to_cpu((sdp)->sd_nlink)) -#define sd_v1_uid(sdp) (__le16_to_cpu((sdp)->sd_uid)) -#define sd_v1_gid(sdp) (__le16_to_cpu((sdp)->sd_gid)) -#define sd_v1_size(sdp) (__le32_to_cpu((sdp)->sd_size)) -#define sd_v1_mtime(sdp) (__le32_to_cpu((sdp)->sd_mtime)) +#define stat_data_v1(ih) (ih_version(ih) == ITEM_VERSION_1) +#define sd_v1_mode(sdp) ((sdp)->sd_mode) +#define sd_v1_nlink(sdp) (__le16_to_cpu((sdp)->sd_nlink)) +#define sd_v1_uid(sdp) (__le16_to_cpu((sdp)->sd_uid)) +#define sd_v1_gid(sdp) (__le16_to_cpu((sdp)->sd_gid)) +#define sd_v1_size(sdp) (__le32_to_cpu((sdp)->sd_size)) +#define sd_v1_mtime(sdp) (__le32_to_cpu((sdp)->sd_mtime)) /* Stat Data on disk (reiserfs version of UFS disk inode minus the address blocks) */ struct stat_data { __u16 sd_mode; /* file type, permissions */ - __u16 sd_attrs; /* persistent inode flags */ + __u16 sd_attrs; /* persistent inode flags */ __u32 sd_nlink; /* number of hard links */ __u64 sd_size; /* file size */ __u32 sd_uid; /* owner */ __u32 sd_gid; /* group */ __u32 sd_atime; /* time of last access */ - __u32 sd_mtime; /* time file was last modified */ + __u32 sd_mtime; /* time file was last modified */ __u32 sd_ctime; /* time inode (stat data) was last changed (except changes to sd_atime and sd_mtime) */ __u32 sd_blocks; union { @@ -350,16 +350,16 @@ struct stat_data { } __attribute__ ((__packed__)) u; } __attribute__ ((__packed__)); -#define stat_data_v2(ih) (ih_version(ih) == ITEM_VERSION_2) -#define sd_v2_mode(sdp) (__le16_to_cpu((sdp)->sd_mode)) -#define sd_v2_nlink(sdp) (__le32_to_cpu((sdp)->sd_nlink)) -#define sd_v2_size(sdp) (__le64_to_cpu((sdp)->sd_size)) -#define sd_v2_uid(sdp) (__le32_to_cpu((sdp)->sd_uid)) -#define sd_v2_gid(sdp) (__le32_to_cpu((sdp)->sd_gid)) -#define sd_v2_mtime(sdp) (__le32_to_cpu((sdp)->sd_mtime)) +#define stat_data_v2(ih) (ih_version(ih) == ITEM_VERSION_2) +#define sd_v2_mode(sdp) (__le16_to_cpu((sdp)->sd_mode)) +#define sd_v2_nlink(sdp) (__le32_to_cpu((sdp)->sd_nlink)) +#define sd_v2_size(sdp) (__le64_to_cpu((sdp)->sd_size)) +#define sd_v2_uid(sdp) (__le32_to_cpu((sdp)->sd_uid)) +#define sd_v2_gid(sdp) (__le32_to_cpu((sdp)->sd_gid)) +#define sd_v2_mtime(sdp) (__le32_to_cpu((sdp)->sd_mtime)) -#define sd_mode(sdp) (__le16_to_cpu((sdp)->sd_mode)) -#define sd_size(sdp) (__le32_to_cpu((sdp)->sd_size)) +#define sd_mode(sdp) (__le16_to_cpu((sdp)->sd_mode)) +#define sd_size(sdp) (__le32_to_cpu((sdp)->sd_size)) #define sd_size_hi(sdp) (__le32_to_cpu((sdp)->sd_size_hi)) struct reiserfs_de_head @@ -376,11 +376,11 @@ struct reiserfs_de_head }; #define DEH_SIZE (sizeof (struct reiserfs_de_head)) -#define deh_offset(p_deh) (__le32_to_cpu((p_deh)->deh_offset)) -#define deh_dir_id(p_deh) (__le32_to_cpu((p_deh)->deh_dir_id)) -#define deh_objectid(p_deh) (__le32_to_cpu((p_deh)->deh_objectid)) -#define deh_location(p_deh) (__le16_to_cpu((p_deh)->deh_location)) -#define deh_state(p_deh) (__le16_to_cpu((p_deh)->deh_state)) +#define deh_offset(p_deh) (__le32_to_cpu((p_deh)->deh_offset)) +#define deh_dir_id(p_deh) (__le32_to_cpu((p_deh)->deh_dir_id)) +#define deh_objectid(p_deh) (__le32_to_cpu((p_deh)->deh_objectid)) +#define deh_location(p_deh) (__le16_to_cpu((p_deh)->deh_location)) +#define deh_state(p_deh) (__le16_to_cpu((p_deh)->deh_state)) #define DEH_Statdata (1 << 0) /* not used now */ @@ -413,7 +413,7 @@ struct reiserfs_de_head #define S_ISLNK(mode) (((mode) & 0170000) == 0120000) #define PATH_MAX 1024 /* include/linux/limits.h */ -#define MAX_LINK_COUNT 5 /* number of symbolic links to follow */ +#define MAX_LINK_COUNT 5 /* number of symbolic links to follow */ /* The size of the node cache */ #define FSYSREISER_CACHE_SIZE 24*1024 @@ -449,9 +449,9 @@ struct fsys_reiser_info /* The current depth of the reiser tree. */ __u16 tree_depth; /* SECTOR_SIZE << blocksize_shift == blocksize. */ - __u8 blocksize_shift; + __u8 blocksize_shift; /* 1 << full_blocksize_shift == blocksize. */ - __u8 fullblocksize_shift; + __u8 fullblocksize_shift; /* The reiserfs block size (must be a power of 2) */ __u16 blocksize; /* The number of cached tree nodes */ @@ -466,14 +466,14 @@ struct fsys_reiser_info /* The cached s+tree blocks in FSYS_BUF, see below * for a more detailed description. */ -#define ROOT ((char *) ((int) FSYS_BUF)) +#define ROOT ((char *) ((int) FSYS_BUF)) #define CACHE(i) (ROOT + ((i) << INFO->fullblocksize_shift)) -#define LEAF CACHE (DISK_LEAF_NODE_LEVEL) +#define LEAF CACHE (DISK_LEAF_NODE_LEVEL) #define BLOCKHEAD(cache) ((struct block_head *) cache) -#define ITEMHEAD ((struct item_head *) ((int) LEAF + BLKH_SIZE)) -#define KEY(cache) ((struct key *) ((int) cache + BLKH_SIZE)) -#define DC(cache) ((struct disk_child *) \ +#define ITEMHEAD ((struct item_head *) ((int) LEAF + BLKH_SIZE)) +#define KEY(cache) ((struct key *) ((int) cache + BLKH_SIZE)) +#define DC(cache) ((struct disk_child *) \ ((int) cache + BLKH_SIZE + KEY_SIZE * nr_item)) /* The fsys_reiser_info block. */ @@ -487,8 +487,8 @@ struct fsys_reiser_info * this list is stopped with a 0xffffffff marker and the remaining * uncommitted transactions aren't cached. */ -#define JOURNAL_START ((__u32 *) (INFO + 1)) -#define JOURNAL_END ((__u32 *) (FSYS_BUF + FSYS_BUFLEN)) +#define JOURNAL_START ((__u32 *) (INFO + 1)) +#define JOURNAL_END ((__u32 *) (FSYS_BUF + FSYS_BUFLEN)) static __inline__ unsigned long diff --git a/include/405_mal.h b/include/405_mal.h index 1415cbe1b..059858695 100644 --- a/include/405_mal.h +++ b/include/405_mal.h @@ -92,10 +92,7 @@ #define MAL_ESR_PBEI 0x00000001 /* ^^ ^^ */ /* Mal IER */ -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) +#ifdef CONFIG_440SPE #define MAL_IER_PT 0x00000080 #define MAL_IER_PRE 0x00000040 #define MAL_IER_PWE 0x00000020 diff --git a/include/405gp_i2c.h b/include/405gp_i2c.h new file mode 100644 index 000000000..5a9a49753 --- /dev/null +++ b/include/405gp_i2c.h @@ -0,0 +1,64 @@ +#ifndef _405gp_i2c_h_ +#define _405gp_i2c_h_ + +#define I2C_REGISTERS_BASE_ADDRESS 0xEF600500 +#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) +#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF) +#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR) +#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR) +#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL) +#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL) +#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS) +#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) +#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) +#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) +#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV) +#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) +#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) +#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) +#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL) + +/* MDCNTL Register Bit definition */ +#define IIC_MDCNTL_HSCL 0x01 +#define IIC_MDCNTL_EUBS 0x02 +#define IIC_MDCNTL_EINT 0x04 +#define IIC_MDCNTL_ESM 0x08 +#define IIC_MDCNTL_FSM 0x10 +#define IIC_MDCNTL_EGC 0x20 +#define IIC_MDCNTL_FMDB 0x40 +#define IIC_MDCNTL_FSDB 0x80 + +/* CNTL Register Bit definition */ +#define IIC_CNTL_PT 0x01 +#define IIC_CNTL_READ 0x02 +#define IIC_CNTL_CHT 0x04 +#define IIC_CNTL_RPST 0x08 +/* bit 2/3 for Transfer count*/ +#define IIC_CNTL_AMD 0x40 +#define IIC_CNTL_HMT 0x80 + +/* STS Register Bit definition */ +#define IIC_STS_PT 0X01 +#define IIC_STS_IRQA 0x02 +#define IIC_STS_ERR 0X04 +#define IIC_STS_SCMP 0x08 +#define IIC_STS_MDBF 0x10 +#define IIC_STS_MDBS 0X20 +#define IIC_STS_SLPR 0x40 +#define IIC_STS_SSS 0x80 + +/* EXTSTS Register Bit definition */ +#define IIC_EXTSTS_XFRA 0X01 +#define IIC_EXTSTS_ICT 0X02 +#define IIC_EXTSTS_LA 0X04 + +/* XTCNTLSS Register Bit definition */ +#define IIC_XTCNTLSS_SRST 0x01 +#define IIC_XTCNTLSS_EPI 0x02 +#define IIC_XTCNTLSS_SDBF 0x04 +#define IIC_XTCNTLSS_SBDD 0x08 +#define IIC_XTCNTLSS_SWS 0x10 +#define IIC_XTCNTLSS_SWC 0x20 +#define IIC_XTCNTLSS_SRS 0x40 +#define IIC_XTCNTLSS_SRC 0x80 +#endif diff --git a/include/405gp_pci.h b/include/405gp_pci.h new file mode 100644 index 000000000..3c1adec19 --- /dev/null +++ b/include/405gp_pci.h @@ -0,0 +1,52 @@ +#ifndef _405GP_PCI_H +#define _405GP_PCI_H + +/*----------------------------------------------------------------------------+ +| 405GP PCI core memory map defines. ++----------------------------------------------------------------------------*/ +#define MIN_PCI_MEMADDR1 0x80000000 +#define MIN_PCI_MEMADDR2 0x00000000 +#define MIN_PLB_PCI_IOADDR 0xE8000000 /* PLB side of PCI I/O address space */ +#define MIN_PCI_PCI_IOADDR 0x00000000 /* PCI side of PCI I/O address space */ +#define MAX_PCI_DEVICES 32 + +/*----------------------------------------------------------------------------+ +| Defines for the 405GP PCI Config address and data registers followed by +| defines for the standard PCI device configuration header. ++----------------------------------------------------------------------------*/ +#define PCICFGADR 0xEEC00000 +#define PCICFGDATA 0xEEC00004 + +#define PCIBUSNUM 0x40 /* 405GP specific parameters */ +#define PCISUBBUSNUM 0x41 +#define PCIDISCOUNT 0x42 +#define PCIBRDGOPT1 0x4A +#define PCIBRDGOPT2 0x60 + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Master local configuration regs. ++----------------------------------------------------------------------------*/ +#define PMM0LA 0xEF400000 +#define PMM0MA 0xEF400004 +#define PMM0PCILA 0xEF400008 +#define PMM0PCIHA 0xEF40000C +#define PMM1LA 0xEF400010 +#define PMM1MA 0xEF400014 +#define PMM1PCILA 0xEF400018 +#define PMM1PCIHA 0xEF40001C +#define PMM2LA 0xEF400020 +#define PMM2MA 0xEF400024 +#define PMM2PCILA 0xEF400028 +#define PMM2PCIHA 0xEF40002C + +/*----------------------------------------------------------------------------+ +| Defines for 405GP PCI Target local configuration regs. ++----------------------------------------------------------------------------*/ +#define PTM1MS 0xEF400030 +#define PTM1LA 0xEF400034 +#define PTM2MS 0xEF400038 +#define PTM2LA 0xEF40003C + +#define PCIDEVID_405GP 0x0 + +#endif diff --git a/include/440_i2c.h b/include/440_i2c.h new file mode 100644 index 000000000..9c90a9e3c --- /dev/null +++ b/include/440_i2c.h @@ -0,0 +1,70 @@ +#ifndef _440_i2c_h_ +#define _440_i2c_h_ + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700) +#else +#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400) +#endif /*CONFIG_440EP CONFIG_440GR*/ + +#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR +#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) +#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF) +#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR) +#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR) +#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL) +#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL) +#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS) +#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) +#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) +#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) +#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV) +#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) +#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) +#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) +#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL) + +/* MDCNTL Register Bit definition */ +#define IIC_MDCNTL_HSCL 0x01 +#define IIC_MDCNTL_EUBS 0x02 +#define IIC_MDCNTL_EINT 0x04 +#define IIC_MDCNTL_ESM 0x08 +#define IIC_MDCNTL_FSM 0x10 +#define IIC_MDCNTL_EGC 0x20 +#define IIC_MDCNTL_FMDB 0x40 +#define IIC_MDCNTL_FSDB 0x80 + +/* CNTL Register Bit definition */ +#define IIC_CNTL_PT 0x01 +#define IIC_CNTL_READ 0x02 +#define IIC_CNTL_CHT 0x04 +#define IIC_CNTL_RPST 0x08 +/* bit 2/3 for Transfer count*/ +#define IIC_CNTL_AMD 0x40 +#define IIC_CNTL_HMT 0x80 + +/* STS Register Bit definition */ +#define IIC_STS_PT 0X01 +#define IIC_STS_IRQA 0x02 +#define IIC_STS_ERR 0X04 +#define IIC_STS_SCMP 0x08 +#define IIC_STS_MDBF 0x10 +#define IIC_STS_MDBS 0X20 +#define IIC_STS_SLPR 0x40 +#define IIC_STS_SSS 0x80 + +/* EXTSTS Register Bit definition */ +#define IIC_EXTSTS_XFRA 0X01 +#define IIC_EXTSTS_ICT 0X02 +#define IIC_EXTSTS_LA 0X04 + +/* XTCNTLSS Register Bit definition */ +#define IIC_XTCNTLSS_SRST 0x01 +#define IIC_XTCNTLSS_EPI 0x02 +#define IIC_XTCNTLSS_SDBF 0x04 +#define IIC_XTCNTLSS_SBDD 0x08 +#define IIC_XTCNTLSS_SWS 0x10 +#define IIC_XTCNTLSS_SWC 0x20 +#define IIC_XTCNTLSS_SRS 0x40 +#define IIC_XTCNTLSS_SRC 0x80 +#endif diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index 4a03cecb5..a6287982a 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -34,7 +34,6 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */ -#define _START_OFFSET EXC_OFF_SYS_RESET /*---------------------------------------------------------------- * l2cr values @@ -112,7 +111,6 @@ typedef enum __cpu_t { CPU_750CX, CPU_750FX, CPU_750GX, CPU_7400, CPU_7410, - CPU_7447A, CPU_7448, CPU_7450, CPU_7455, CPU_7457, CPU_UNKNOWN} cpu_t; diff --git a/include/ACEX1K.h b/include/ACEX1K.h index 354e0f0e4..f75c463f3 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -35,11 +35,6 @@ extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize ); extern int ACEX1K_info( Altera_desc *desc ); extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off ); -extern int CYC2_load( Altera_desc *desc, void *image, size_t size ); -extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize ); -extern int CYC2_info( Altera_desc *desc ); -extern int CYC2_reloc( Altera_desc *desc, ulong reloc_off ); - /* Slave Serial Implementation function table */ typedef struct { Altera_pre_fn pre; @@ -53,18 +48,6 @@ typedef struct { int relocated; } Altera_ACEX1K_Passive_Serial_fns; -/* Slave Serial Implementation function table */ -typedef struct { - Altera_pre_fn pre; - Altera_config_fn config; - Altera_status_fn status; - Altera_done_fn done; - Altera_write_fn write; - Altera_abort_fn abort; - Altera_post_fn post; - int relocated; -} Altera_CYC2_Passive_Serial_fns; - /* Device Image Sizes *********************************************************************/ /* ACEX1K */ @@ -73,13 +56,9 @@ typedef struct { * Filesize of an *.rbf file is 166965 Bytes */ #if 0 -#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */ +#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */ #endif -#define Altera_EP1K100_SIZE (166965*8) - -#define Altera_EP2C8_SIZE 247942 -#define Altera_EP2C20_SIZE 586562 -#define Altera_EP2C35_SIZE 883905 +#define Altera_EP1K100_SIZE (166965*8) /* Descriptor Macros *********************************************************************/ diff --git a/include/SA-1100.h b/include/SA-1100.h index 7589df238..9985783e5 100644 --- a/include/SA-1100.h +++ b/include/SA-1100.h @@ -1,20 +1,20 @@ /* - * FILE SA-1100.h + * FILE SA-1100.h * - * Version 1.2 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date January 1998 (April 1997) - * System StrongARM SA-1100 + * Version 1.2 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date January 1998 (April 1997) + * System StrongARM SA-1100 * Language C or ARM Assembly - * Purpose Definition of constants related to the StrongARM - * SA-1100 microprocessor (Advanced RISC Machine (ARM) - * architecture version 4). This file is based on the - * StrongARM SA-1100 data sheet version 2.2. + * Purpose Definition of constants related to the StrongARM + * SA-1100 microprocessor (Advanced RISC Machine (ARM) + * architecture version 4). This file is based on the + * StrongARM SA-1100 data sheet version 2.2. * - * Language-specific definitions are selected by the - * macro "LANGUAGE", which should be defined as either - * "C" (default) or "Assembly". + * Language-specific definitions are selected by the + * macro "LANGUAGE", which should be defined as either + * "C" (default) or "Assembly". */ @@ -32,17 +32,17 @@ #include -#define C 0 +#define C 0 #define Assembly 1 #if LANGUAGE == C -typedef unsigned short Word16 ; -typedef unsigned int Word32 ; -typedef Word32 Word ; -typedef Word Quad [4] ; -typedef void *Address ; -typedef void (*ExcpHndlr) (void) ; +typedef unsigned short Word16 ; +typedef unsigned int Word32 ; +typedef Word32 Word ; +typedef Word Quad [4] ; +typedef void *Address ; +typedef void (*ExcpHndlr) (void) ; #endif /* LANGUAGE == C */ @@ -50,65 +50,65 @@ typedef void (*ExcpHndlr) (void) ; * Memory */ -#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */ +#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */ #define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */ -#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ - /* [byte] */ -#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ - /* [byte] */ -#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ - /* [byte] */ -#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ - /* [byte] */ +#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ + /* [byte] */ +#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ + /* [byte] */ +#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ + /* [byte] */ +#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ + /* [byte] */ -#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ -#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ -#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */ -#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */ -#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */ +#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ +#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ +#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */ +#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */ +#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */ #define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */ -#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ +#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ (0x00000000 + (Nb)*StMemBnkSp) -#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ -#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ -#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ -#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */ +#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ +#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ +#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ +#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */ #if LANGUAGE == C -typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; -#define StMemBnk /* Static Memory Bank [0..3] */ \ +typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; +#define StMemBnk /* Static Memory Bank [0..3] */ \ ((StMemBnkType *) io_p2v (_StMemBnk (0))) -#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ -#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ -#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ -#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */ +#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ +#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ +#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ +#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */ #endif /* LANGUAGE == C */ -#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ +#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ (0xC0000000 + (Nb)*DRAMBnkSp) -#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ -#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ -#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ -#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */ +#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ +#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ +#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ +#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */ #if LANGUAGE == C -typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; -#define DRAMBnk /* DRAM Bank [0..3] */ \ +typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; +#define DRAMBnk /* DRAM Bank [0..3] */ \ ((DRAMBnkType *) io_p2v (_DRAMBnk (0))) -#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ -#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ -#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ -#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */ +#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ +#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ +#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ +#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */ #endif /* LANGUAGE == C */ -#define _ZeroMem 0xE0000000 /* Zero Memory bank */ +#define _ZeroMem 0xE0000000 /* Zero Memory bank */ #if LANGUAGE == C -typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; -#define ZeroMem /* Zero Memory bank */ \ +typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; +#define ZeroMem /* Zero Memory bank */ \ (*((ZeroMemType *) io_p2v (_ZeroMem))) #endif /* LANGUAGE == C */ @@ -118,60 +118,60 @@ typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; */ #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ -#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ -#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ +#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ +#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ -#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ +#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ -#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ -#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ +#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ +#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ -#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ -#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ +#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ +#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ -#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ +#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ (0x20000000 + (Nb)*PCMCIASp) -#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ -#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ +#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ +#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ (_PCMCIA (Nb) + 2*PCMCIAPrtSp) -#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ +#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ (_PCMCIA (Nb) + 3*PCMCIAPrtSp) -#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ -#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ -#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ -#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ +#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ +#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ +#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ +#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ -#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ -#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ -#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ -#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ +#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ +#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ +#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ +#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ #if LANGUAGE == C -typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; +typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; -#define PCMCIA0 /* PCMCIA 0 */ \ +#define PCMCIA0 /* PCMCIA 0 */ \ (*((PCMCIAType *) io_p2v (_PCMCIA0))) -#define PCMCIA0IO /* PCMCIA 0 I/O */ \ +#define PCMCIA0IO /* PCMCIA 0 I/O */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO))) -#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ +#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr))) -#define PCMCIA0Mem /* PCMCIA 0 Memory */ \ +#define PCMCIA0Mem /* PCMCIA 0 Memory */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem))) -#define PCMCIA1 /* PCMCIA 1 */ \ +#define PCMCIA1 /* PCMCIA 1 */ \ (*((PCMCIAType *) io_p2v (_PCMCIA1))) -#define PCMCIA1IO /* PCMCIA 1 I/O */ \ +#define PCMCIA1IO /* PCMCIA 1 I/O */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO))) -#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ +#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr))) -#define PCMCIA1Mem /* PCMCIA 1 Memory */ \ +#define PCMCIA1Mem /* PCMCIA 1 Memory */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem))) #endif /* LANGUAGE == C */ @@ -181,254 +181,254 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * Universal Serial Bus (USB) Device Controller (UDC) control registers * * Registers - * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control Register (read/write). - * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Address Register (read/write). + * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control Register (read/write). + * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Address Register (read/write). * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Output Maximum Packet size register - * (read/write). + * Controller (UDC) Output Maximum Packet size register + * (read/write). * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Input Maximum Packet size register - * (read/write). + * Controller (UDC) Input Maximum Packet size register + * (read/write). * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 0 - * (read/write). + * Controller (UDC) Control/Status register end-point 0 + * (read/write). * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 1 - * (output, read/write). + * Controller (UDC) Control/Status register end-point 1 + * (output, read/write). * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 2 - * (input, read/write). - * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Data register end-point 0 - * (read/write). - * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Write Count register end-point 0 - * (read). - * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Data Register (read/write). - * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Status Register (read/write). + * Controller (UDC) Control/Status register end-point 2 + * (input, read/write). + * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data register end-point 0 + * (read/write). + * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Write Count register end-point 0 + * (read). + * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data Register (read/write). + * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Status Register (read/write). */ #define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */ #define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */ #define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */ - /* Packet size reg. */ + /* Packet size reg. */ #define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */ - /* Packet size reg. */ + /* Packet size reg. */ #define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 0 */ + /* reg. end-point 0 */ #define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 1 (output) */ + /* reg. end-point 1 (output) */ #define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 2 (input) */ -#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ - /* end-point 0 */ -#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ - /* reg. end-point 0 */ -#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ -#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ + /* reg. end-point 2 (input) */ +#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ + /* end-point 0 */ +#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ + /* reg. end-point 0 */ +#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ +#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ #if LANGUAGE == C -#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ +#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCCR))) -#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ +#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCAR))) -#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ - /* Packet size reg. */ \ +#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ + /* Packet size reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCOMP))) -#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ - /* Packet size reg. */ \ +#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ + /* Packet size reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCIMP))) -#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 0 */ \ +#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 0 */ \ (*((volatile Word *) io_p2v (_Ser0UDCCS0))) -#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 1 (output) */ \ +#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 1 (output) */ \ (*((volatile Word *) io_p2v (_Ser0UDCCS1))) -#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 2 (input) */ \ +#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 2 (input) */ \ (*((volatile Word *) io_p2v (_Ser0UDCCS2))) -#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ - /* end-point 0 */ \ +#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ + /* end-point 0 */ \ (*((volatile Word *) io_p2v (_Ser0UDCD0))) -#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ - /* reg. end-point 0 */ \ +#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ + /* reg. end-point 0 */ \ (*((volatile Word *) io_p2v (_Ser0UDCWC))) -#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ +#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCDR))) -#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ +#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCSR))) #endif /* LANGUAGE == C */ -#define UDCCR_UDD 0x00000001 /* UDC Disable */ -#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ +#define UDCCR_UDD 0x00000001 /* UDC Disable */ +#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ -#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ - /* (disable) */ -#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ - /* (disable) */ -#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ - /* (disable) */ +#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ + /* (disable) */ +#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ + /* (disable) */ +#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ + /* (disable) */ #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ - /* (disable) */ + /* (disable) */ #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ -#define UDCAR_ADD Fld (7, 0) /* function ADDress */ +#define UDCAR_ADD Fld (7, 0) /* function ADDress */ #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ - /* [byte] */ -#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ - /* [1..256 byte] */ \ + /* [byte] */ +#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ + /* [1..256 byte] */ \ (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ - /* [byte] */ -#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ - /* [1..256 byte] */ \ + /* [byte] */ +#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ + /* [1..256 byte] */ \ (((Size) - 1) << FShft (UDCIMP_INMAXP)) -#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ -#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ -#define UDCCS0_SST 0x00000004 /* Sent STall */ -#define UDCCS0_FST 0x00000008 /* Force STall */ -#define UDCCS0_DE 0x00000010 /* Data End */ -#define UDCCS0_SE 0x00000020 /* Setup End (read) */ +#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ +#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ +#define UDCCS0_SST 0x00000004 /* Sent STall */ +#define UDCCS0_FST 0x00000008 /* Force STall */ +#define UDCCS0_DE 0x00000010 /* Data End */ +#define UDCCS0_SE 0x00000020 /* Setup End (read) */ #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ - /* (write) */ -#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ + /* (write) */ +#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ - /* Service request (read) */ -#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ -#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ -#define UDCCS1_SST 0x00000008 /* Sent STall */ -#define UDCCS1_FST 0x00000010 /* Force STall */ + /* Service request (read) */ +#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ +#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ +#define UDCCS1_SST 0x00000008 /* Sent STall */ +#define UDCCS1_FST 0x00000010 /* Force STall */ #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ - /* Service request (read) */ -#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ + /* Service request (read) */ +#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ -#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ -#define UDCCS2_SST 0x00000010 /* Sent STall */ -#define UDCCS2_FST 0x00000020 /* Force STall */ +#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ +#define UDCCS2_SST 0x00000010 /* Sent STall */ +#define UDCCS2_FST 0x00000020 /* Force STall */ -#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#define UDCWC_WC Fld (4, 0) /* Write Count */ +#define UDCWC_WC Fld (4, 0) /* Write Count */ -#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ -#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ -#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ -#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ -#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ -#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ +#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ +#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ +#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ +#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ +#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ /* * Universal Asynchronous Receiver/Transmitter (UART) control registers * * Registers - * Ser1UTCR0 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser1UTCR1 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser1UTCR2 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser1UTCR3 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser1UTDR Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser1UTSR0 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser1UTSR1 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). + * Ser1UTCR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser1UTCR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser1UTCR2 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser1UTCR3 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser1UTDR Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser1UTSR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser1UTSR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). * - * Ser2UTCR0 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser2UTCR1 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser2UTCR2 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser2UTCR3 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser2UTCR4 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 4 - * (read/write). - * Ser2UTDR Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser2UTSR0 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser2UTSR1 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). + * Ser2UTCR0 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser2UTCR1 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser2UTCR2 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser2UTCR3 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser2UTCR4 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 4 + * (read/write). + * Ser2UTDR Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser2UTSR0 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser2UTSR1 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). * - * Ser3UTCR0 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser3UTCR1 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser3UTCR2 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser3UTCR3 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser3UTDR Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser3UTSR0 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser3UTSR1 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). + * Ser3UTCR0 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser3UTCR1 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser3UTCR2 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser3UTCR3 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser3UTDR Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser3UTSR0 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser3UTSR1 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fua, Tua Frequency, period of the UART communication. + * or 3.5795 MHz). + * fua, Tua Frequency, period of the UART communication. */ -#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ +#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ (0x80010000 + ((Nb) - 1)*0x00020000) -#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ +#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ (0x80010004 + ((Nb) - 1)*0x00020000) -#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ +#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ (0x80010008 + ((Nb) - 1)*0x00020000) -#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ +#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ (0x8001000C + ((Nb) - 1)*0x00020000) -#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ +#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ (0x80010010 + ((Nb) - 1)*0x00020000) -#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ +#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ (0x80010014 + ((Nb) - 1)*0x00020000) -#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ +#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ (0x8001001C + ((Nb) - 1)*0x00020000) -#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ +#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ (0x80010020 + ((Nb) - 1)*0x00020000) #define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ #define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ #define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ #define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ -#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ +#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ #define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ #define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ @@ -437,7 +437,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ #define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ #define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ -#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ +#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ #define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ #define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ @@ -445,57 +445,57 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ #define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ #define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ -#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ +#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ #define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ #define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ #if LANGUAGE == C -#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ +#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser1UTCR0))) -#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ +#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser1UTCR1))) -#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ +#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_Ser1UTCR2))) -#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ +#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ (*((volatile Word *) io_p2v (_Ser1UTCR3))) -#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ +#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser1UTDR))) -#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ +#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser1UTSR0))) -#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ +#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser1UTSR1))) -#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ +#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser2UTCR0))) -#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ +#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser2UTCR1))) -#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ +#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_Ser2UTCR2))) -#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ +#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ (*((volatile Word *) io_p2v (_Ser2UTCR3))) -#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ +#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ (*((volatile Word *) io_p2v (_Ser2UTCR4))) -#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ +#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser2UTDR))) -#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ +#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser2UTSR0))) -#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ +#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser2UTSR1))) -#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ +#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser3UTCR0))) -#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ +#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser3UTCR1))) -#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ +#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_Ser3UTCR2))) -#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ +#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ (*((volatile Word *) io_p2v (_Ser3UTCR3))) -#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ +#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser3UTDR))) -#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ +#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser3UTSR0))) -#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ +#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser3UTSR1))) #elif LANGUAGE == Assembly @@ -526,89 +526,89 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #endif /* LANGUAGE == C */ -#define UTCR0_PE 0x00000001 /* Parity Enable */ -#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ -#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ -#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ -#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ -#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ -#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ -#define UTCR0_DSS 0x00000008 /* Data Size Select */ -#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ -#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ -#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ - /* (ser. port 1: GPIO [18], */ - /* ser. port 3: GPIO [20]) */ -#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ -#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ -#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ -#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ -#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ +#define UTCR0_PE 0x00000001 /* Parity Enable */ +#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ +#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ +#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ +#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ +#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ +#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ +#define UTCR0_DSS 0x00000008 /* Data Size Select */ +#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ +#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ +#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ + /* (ser. port 1: GPIO [18], */ + /* ser. port 3: GPIO [20]) */ +#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ +#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ +#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ +#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ +#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ -#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ +#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ (UTCR0_1StpBit + UTCR0_8BitData) #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ /* fua = fxtl/(16*(BRD[11:0] + 1)) */ /* Tua = 16*(BRD [11:0] + 1)*Txtl */ -#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ +#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ FShft (UTCR1_BRD)) -#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ +#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ FShft (UTCR2_BRD)) /* fua = fxtl/(16*Floor (Div/16)) */ /* Tua = 16*Floor (Div/16)*Txtl */ -#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ +#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ FShft (UTCR1_BRD)) -#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ +#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ FShft (UTCR2_BRD)) /* fua = fxtl/(16*Ceil (Div/16)) */ /* Tua = 16*Ceil (Div/16)*Txtl */ -#define UTCR3_RXE 0x00000001 /* Receive Enable */ -#define UTCR3_TXE 0x00000002 /* Transmit Enable */ -#define UTCR3_BRK 0x00000004 /* BReaK mode */ +#define UTCR3_RXE 0x00000001 /* Receive Enable */ +#define UTCR3_TXE 0x00000002 /* Transmit Enable */ +#define UTCR3_BRK 0x00000004 /* BReaK mode */ #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ + /* more Interrupt Enable */ #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ -#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ + /* Interrupt Enable */ +#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ +#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ /* TIE, LBM can be set or cleared) */ \ (UTCR3_RXE + UTCR3_TXE) #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ - /* (HP-SIR) modulation Enable */ + /* (HP-SIR) modulation Enable */ #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ -#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ -#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ -#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ -#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ +#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ +#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ +#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ +#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ -#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ +#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ #endif /* 0 */ #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ -#define UTSR0_RID 0x00000004 /* Receiver IDle */ -#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ -#define UTSR0_REB 0x00000010 /* Receive End of Break */ -#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ + /* more Service request (read) */ +#define UTSR0_RID 0x00000004 /* Receiver IDle */ +#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ +#define UTSR0_REB 0x00000010 /* Receive End of Break */ +#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ -#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ +#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ -#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ +#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ @@ -617,27 +617,27 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * Synchronous Data Link Controller (SDLC) control registers * * Registers - * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 0 (read/write). - * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 1 (read/write). - * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 2 (read/write). - * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 3 (read/write). - * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 4 (read/write). - * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) - * Data Register (read/write). - * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) - * Status Register 0 (read/write). - * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) - * Status Register 1 (read/write). + * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 0 (read/write). + * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 1 (read/write). + * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 2 (read/write). + * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 3 (read/write). + * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 4 (read/write). + * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) + * Data Register (read/write). + * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) + * Status Register 0 (read/write). + * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) + * Status Register 1 (read/write). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fsd, Tsd Frequency, period of the SDLC communication. + * or 3.5795 MHz). + * fsd, Tsd Frequency, period of the SDLC communication. */ #define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */ @@ -645,110 +645,110 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */ #define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */ #define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */ -#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */ +#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */ #define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */ #define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */ #if LANGUAGE == C -#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ +#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser1SDCR0))) -#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ +#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser1SDCR1))) -#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ +#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_Ser1SDCR2))) -#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ +#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ (*((volatile Word *) io_p2v (_Ser1SDCR3))) -#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ +#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ (*((volatile Word *) io_p2v (_Ser1SDCR4))) -#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ +#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser1SDDR))) -#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ +#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser1SDSR0))) -#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ +#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser1SDSR1))) #endif /* LANGUAGE == C */ -#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ -#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ -#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ +#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ +#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ +#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ -#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ -#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ -#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ -#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ -#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ +#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ +#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ +#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ +#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ +#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ - /* (GPIO [16]) */ -#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ -#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ -#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ -#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ -#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ -#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ -#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ + /* (GPIO [16]) */ +#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ +#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ +#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ +#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ +#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ +#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ +#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ -#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ - /* (GPIO [17]) */ -#define SDCR1_TXE 0x00000002 /* Transmit Enable */ -#define SDCR1_RXE 0x00000004 /* Receive Enable */ +#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ + /* (GPIO [17]) */ +#define SDCR1_TXE 0x00000002 /* Transmit Enable */ +#define SDCR1_RXE 0x00000004 /* Receive Enable */ #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ + /* more Interrupt Enable */ #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define SDCR1_AME 0x00000020 /* Address Match Enable */ + /* Interrupt Enable */ +#define SDCR1_AME 0x00000020 /* Address Match Enable */ #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ -#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ -#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ +#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ +#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ -#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ +#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ -#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ +#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ FShft (SDCR3_BRD)) -#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ +#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ FShft (SDCR4_BRD)) /* fsd = fxtl/(16*Floor (Div/16)) */ /* Tsd = 16*Floor (Div/16)*Txtl */ -#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ +#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ FShft (SDCR3_BRD)) -#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ +#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ FShft (SDCR4_BRD)) /* fsd = fxtl/(16*Ceil (Div/16)) */ /* Tsd = 16*Ceil (Div/16)*Txtl */ -#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ +#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ -#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ +#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ #endif /* 0 */ -#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ -#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ -#define SDSR0_RAB 0x00000004 /* Receive ABort */ +#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ +#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ +#define SDSR0_RAB 0x00000004 /* Receive ABort */ #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ + /* more Service request (read) */ #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ -#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ +#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ -#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ -#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ -#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ +#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ +#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ +#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ @@ -756,159 +756,159 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * High-Speed Serial to Parallel controller (HSSP) control registers * * Registers - * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 0 (read/write). - * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 1 (read/write). - * Ser2HSDR Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Data Register (read/write). - * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Status Register 0 (read/write). - * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Status Register 1 (read). - * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 2 (read/write). - * [The HSCR2 register is only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] + * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 0 (read/write). + * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 1 (read/write). + * Ser2HSDR Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Data Register (read/write). + * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Status Register 0 (read/write). + * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Status Register 1 (read). + * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 2 (read/write). + * [The HSCR2 register is only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] */ #define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */ #define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */ -#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */ +#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */ #define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */ #define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */ #define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */ #if LANGUAGE == C -#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ +#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser2HSCR0))) -#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ +#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser2HSCR1))) -#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ +#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser2HSDR))) -#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ +#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser2HSSR0))) -#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ +#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser2HSSR1))) -#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ +#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_Ser2HSCR2))) #endif /* LANGUAGE == C */ -#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ +#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ -#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ -#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ +#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ +#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ -#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ -#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ -#define HSCR0_TXE 0x00000008 /* Transmit Enable */ -#define HSCR0_RXE 0x00000010 /* Receive Enable */ +#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ +#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ +#define HSCR0_TXE 0x00000008 /* Transmit Enable */ +#define HSCR0_RXE 0x00000010 /* Receive Enable */ #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Interrupt Enable */ + /* more Interrupt Enable */ #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define HSCR0_AME 0x00000080 /* Address Match Enable */ + /* Interrupt Enable */ +#define HSCR0_AME 0x00000080 /* Address Match Enable */ -#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ +#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ -#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ +#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ -#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ +#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ #endif /* 0 */ -#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ -#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ -#define HSSR0_RAB 0x00000004 /* Receive ABort */ +#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ +#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ +#define HSSR0_RAB 0x00000004 /* Receive ABort */ #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Service request (read) */ -#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ + /* more Service request (read) */ +#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ -#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ +#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ -#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ -#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ +#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ +#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ -#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ - /* (inverted) */ -#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ - /* (non-inverted) */ +#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ + /* (inverted) */ +#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ + /* (non-inverted) */ #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ -#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ - /* (inverted) */ -#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ - /* (non-inverted) */ +#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ + /* (inverted) */ +#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ + /* (non-inverted) */ /* * Multi-media Communications Port (MCP) control registers * * Registers - * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) - * Control Register 0 (read/write). - * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 0 (audio, read/write). - * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 1 (telecom, read/write). - * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 2 (CODEC registers, read/write). - * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) - * Status Register (read/write). - * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) - * Control Register 1 (read/write). - * [The MCCR1 register is only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] + * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) + * Control Register 0 (read/write). + * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 0 (audio, read/write). + * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 1 (telecom, read/write). + * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 2 (CODEC registers, read/write). + * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) + * Status Register (read/write). + * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) + * Control Register 1 (read/write). + * [The MCCR1 register is only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] * * Clocks - * fmc, Tmc Frequency, period of the MCP communication (10 MHz, - * 12 MHz, or GPIO [21]). + * fmc, Tmc Frequency, period of the MCP communication (10 MHz, + * 12 MHz, or GPIO [21]). * faud, Taud Frequency, period of the audio sampling. * ftcm, Ttcm Frequency, period of the telecom sampling. */ #define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */ -#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ - /* (audio) */ -#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ - /* (telecom) */ -#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ - /* (CODEC reg.) */ -#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ +#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ + /* (audio) */ +#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ + /* (telecom) */ +#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ + /* (CODEC reg.) */ +#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ #define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */ #if LANGUAGE == C -#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ +#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser4MCCR0))) -#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ - /* (audio) */ \ +#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ + /* (audio) */ \ (*((volatile Word *) io_p2v (_Ser4MCDR0))) -#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ - /* (telecom) */ \ +#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ + /* (telecom) */ \ (*((volatile Word *) io_p2v (_Ser4MCDR1))) -#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ - /* (CODEC reg.) */ \ +#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ + /* (CODEC reg.) */ \ (*((volatile Word *) io_p2v (_Ser4MCDR2))) -#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ +#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ (*((volatile Word *) io_p2v (_Ser4MCSR))) -#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ +#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser4MCCR1))) #endif /* LANGUAGE == C */ #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ - /* [6..127] */ - /* faud = fmc/(32*ASD) */ - /* Taud = 32*ASD*Tmc */ -#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ - /* [192..4064] */ \ + /* [6..127] */ + /* faud = fmc/(32*ASD) */ + /* Taud = 32*ASD*Tmc */ +#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ + /* [192..4064] */ \ ((Div)/32 << FShft (MCCR0_ASD)) /* faud = fmc/(32*Floor (Div/32)) */ /* Taud = 32*Floor (Div/32)*Tmc */ @@ -916,12 +916,12 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; (((Div) + 31)/32 << FShft (MCCR0_ASD)) /* faud = fmc/(32*Ceil (Div/32)) */ /* Taud = 32*Ceil (Div/32)*Tmc */ -#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ - /* Divisor/32 [16..127] */ - /* ftcm = fmc/(32*TSD) */ - /* Ttcm = 32*TSD*Tmc */ -#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ - /* [512..4064] */ \ +#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ + /* Divisor/32 [16..127] */ + /* ftcm = fmc/(32*TSD) */ + /* Ttcm = 32*TSD*Tmc */ +#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ + /* [512..4064] */ \ ((Div)/32 << FShft (MCCR0_TSD)) /* ftcm = fmc/(32*Floor (Div/32)) */ /* Ttcm = 32*Floor (Div/32)*Tmc */ @@ -929,460 +929,460 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; (((Div) + 31)/32 << FShft (MCCR0_TSD)) /* ftcm = fmc/(32*Ceil (Div/32)) */ /* Ttcm = 32*Ceil (Div/32)*Tmc */ -#define MCCR0_MCE 0x00010000 /* MCP Enable */ -#define MCCR0_ECS 0x00020000 /* External Clock Select */ +#define MCCR0_MCE 0x00010000 /* MCP Enable */ +#define MCCR0_ECS 0x00020000 /* External Clock Select */ #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ -#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ -#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ - /* sampling/storing Mode */ -#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ +#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ +#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ + /* sampling/storing Mode */ +#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ + /* or less interrupt Enable */ #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ - /* or more interrupt Enable */ + /* or more interrupt Enable */ #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ + /* or less interrupt Enable */ #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ - /* more interrupt Enable */ -#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ + /* more interrupt Enable */ +#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ -#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ +#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ (((Div) - 1) << FShft (MCCR0_ECP)) -#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ - /* FIFOs */ +#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ + /* FIFOs */ #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ - /* FIFOs */ + /* FIFOs */ - /* receive/transmit CODEC reg. */ - /* FIFOs: */ -#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ -#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ -#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ -#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ -#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ + /* receive/transmit CODEC reg. */ + /* FIFOs: */ +#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ +#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ +#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ +#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ +#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ /* or less Service request (read) */ #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ - /* more Service request (read) */ + /* more Service request (read) */ #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ /* or less Service request (read) */ #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ /* or more Service request (read) */ #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ -#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ +#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ - /* (read) */ + /* (read) */ #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ - /* (read) */ + /* (read) */ #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ - /* (read) */ + /* (read) */ #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ - /* (read) */ + /* (read) */ #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ - /* (read) */ + /* (read) */ #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ - /* (read) */ -#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ + /* (read) */ +#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ -#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ -#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ - /* (11.981 MHz) */ -#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ - /* (9.585 MHz) */ +#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ +#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ + /* (11.981 MHz) */ +#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ + /* (9.585 MHz) */ /* * Synchronous Serial Port (SSP) control registers * * Registers - * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control - * Register 0 (read/write). - * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control - * Register 1 (read/write). - * [Bits SPO and SP are only implemented in versions 2.0 - * (rev. = 8) and higher of the StrongARM SA-1100.] - * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data - * Register (read/write). - * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status - * Register (read/write). + * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control + * Register 0 (read/write). + * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control + * Register 1 (read/write). + * [Bits SPO and SP are only implemented in versions 2.0 + * (rev. = 8) and higher of the StrongARM SA-1100.] + * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data + * Register (read/write). + * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status + * Register (read/write). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fss, Tss Frequency, period of the SSP communication. + * or 3.5795 MHz). + * fss, Tss Frequency, period of the SSP communication. */ #define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */ #define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */ -#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */ -#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */ +#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */ +#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */ #if LANGUAGE == C -#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ +#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser4SSCR0))) -#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ +#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser4SSCR1))) -#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ +#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser4SSDR))) -#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ +#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ (*((volatile Word *) io_p2v (_Ser4SSSR))) #endif /* LANGUAGE == C */ #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ -#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ +#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ (((Size) - 1) << FShft (SSCR0_DSS)) -#define SSCR0_FRF Fld (2, 4) /* FRame Format */ -#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ - /* Interface (SPI) format */ \ +#define SSCR0_FRF Fld (2, 4) /* FRame Format */ +#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ + /* Interface (SPI) format */ \ (0 << FShft (SSCR0_FRF)) -#define SSCR0_TI /* Texas Instruments Synchronous */ \ - /* Serial format */ \ +#define SSCR0_TI /* Texas Instruments Synchronous */ \ + /* Serial format */ \ (1 << FShft (SSCR0_FRF)) -#define SSCR0_National /* National Microwire format */ \ +#define SSCR0_National /* National Microwire format */ \ (2 << FShft (SSCR0_FRF)) -#define SSCR0_SSE 0x00000080 /* SSP Enable */ +#define SSCR0_SSE 0x00000080 /* SSP Enable */ #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ - /* fss = fxtl/(2*(SCR + 1)) */ - /* Tss = 2*(SCR + 1)*Txtl */ -#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ + /* fss = fxtl/(2*(SCR + 1)) */ + /* Tss = 2*(SCR + 1)*Txtl */ +#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ (((Div) - 2)/2 << FShft (SSCR0_SCR)) /* fss = fxtl/(2*Floor (Div/2)) */ - /* Tss = 2*Floor (Div/2)*Txtl */ + /* Tss = 2*Floor (Div/2)*Txtl */ #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ (((Div) - 1)/2 << FShft (SSCR0_SCR)) /* fss = fxtl/(2*Ceil (Div/2)) */ - /* Tss = 2*Ceil (Div/2)*Txtl */ + /* Tss = 2*Ceil (Div/2)*Txtl */ #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ - /* Interrupt Enable */ + /* Interrupt Enable */ #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ + /* Interrupt Enable */ +#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ -#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ -#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ -#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ +#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ +#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ +#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ /* after frame (SFRM, 1st edge) */ #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ /* after frame (SFRM, 1st edge) */ -#define SSCR1_ECS 0x00000020 /* External Clock Select */ -#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ -#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ +#define SSCR1_ECS 0x00000020 /* External Clock Select */ +#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ +#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ -#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ +#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ +#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ - /* Service request (read) */ -#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ + /* Service request (read) */ +#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ /* * Operating System (OS) timer control registers * * Registers - * OSMR0 Operating System (OS) timer Match Register 0 - * (read/write). - * OSMR1 Operating System (OS) timer Match Register 1 - * (read/write). - * OSMR2 Operating System (OS) timer Match Register 2 - * (read/write). - * OSMR3 Operating System (OS) timer Match Register 3 - * (read/write). - * OSCR Operating System (OS) timer Counter Register - * (read/write). - * OSSR Operating System (OS) timer Status Register - * (read/write). - * OWER Operating System (OS) timer Watch-dog Enable Register - * (read/write). - * OIER Operating System (OS) timer Interrupt Enable Register - * (read/write). + * OSMR0 Operating System (OS) timer Match Register 0 + * (read/write). + * OSMR1 Operating System (OS) timer Match Register 1 + * (read/write). + * OSMR2 Operating System (OS) timer Match Register 2 + * (read/write). + * OSMR3 Operating System (OS) timer Match Register 3 + * (read/write). + * OSCR Operating System (OS) timer Counter Register + * (read/write). + * OSSR Operating System (OS) timer Status Register + * (read/write). + * OWER Operating System (OS) timer Watch-dog Enable Register + * (read/write). + * OIER Operating System (OS) timer Interrupt Enable Register + * (read/write). */ -#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ +#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ (0x90000000 + (Nb)*4) -#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ -#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ -#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ -#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */ -#define _OSCR 0x90000010 /* OS timer Counter Reg. */ -#define _OSSR 0x90000014 /* OS timer Status Reg. */ -#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */ -#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */ +#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ +#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ +#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ +#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */ +#define _OSCR 0x90000010 /* OS timer Counter Reg. */ +#define _OSSR 0x90000014 /* OS timer Status Reg. */ +#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */ +#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */ #if LANGUAGE == C -#define OSMR /* OS timer Match Reg. [0..3] */ \ +#define OSMR /* OS timer Match Reg. [0..3] */ \ ((volatile Word *) io_p2v (_OSMR (0))) -#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ -#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ -#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ -#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ -#define OSCR /* OS timer Counter Reg. */ \ +#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ +#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ +#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ +#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ +#define OSCR /* OS timer Counter Reg. */ \ (*((volatile Word *) io_p2v (_OSCR))) -#define OSSR /* OS timer Status Reg. */ \ +#define OSSR /* OS timer Status Reg. */ \ (*((volatile Word *) io_p2v (_OSSR))) -#define OWER /* OS timer Watch-dog Enable Reg. */ \ +#define OWER /* OS timer Watch-dog Enable Reg. */ \ (*((volatile Word *) io_p2v (_OWER))) -#define OIER /* OS timer Interrupt Enable Reg. */ \ +#define OIER /* OS timer Interrupt Enable Reg. */ \ (*((volatile Word *) io_p2v (_OIER))) #endif /* LANGUAGE == C */ -#define OSSR_M(Nb) /* Match detected [0..3] */ \ +#define OSSR_M(Nb) /* Match detected [0..3] */ \ (0x00000001 << (Nb)) -#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ -#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ -#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ -#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ +#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ +#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ +#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ +#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ -#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ - /* (set only) */ +#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ + /* (set only) */ -#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ +#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ (0x00000001 << (Nb)) -#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ -#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ -#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ -#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ +#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ +#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ +#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ +#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ /* * Real-Time Clock (RTC) control registers * * Registers - * RTAR Real-Time Clock (RTC) Alarm Register (read/write). - * RCNR Real-Time Clock (RTC) CouNt Register (read/write). - * RTTR Real-Time Clock (RTC) Trim Register (read/write). - * RTSR Real-Time Clock (RTC) Status Register (read/write). + * RTAR Real-Time Clock (RTC) Alarm Register (read/write). + * RCNR Real-Time Clock (RTC) CouNt Register (read/write). + * RTTR Real-Time Clock (RTC) Trim Register (read/write). + * RTSR Real-Time Clock (RTC) Status Register (read/write). * * Clocks * frtx, Trtx Frequency, period of the real-time clock crystal - * (32.768 kHz nominal). + * (32.768 kHz nominal). * frtc, Trtc Frequency, period of the real-time clock counter - * (1 Hz nominal). + * (1 Hz nominal). */ -#define _RTAR 0x90010000 /* RTC Alarm Reg. */ -#define _RCNR 0x90010004 /* RTC CouNt Reg. */ -#define _RTTR 0x90010008 /* RTC Trim Reg. */ -#define _RTSR 0x90010010 /* RTC Status Reg. */ +#define _RTAR 0x90010000 /* RTC Alarm Reg. */ +#define _RCNR 0x90010004 /* RTC CouNt Reg. */ +#define _RTTR 0x90010008 /* RTC Trim Reg. */ +#define _RTSR 0x90010010 /* RTC Status Reg. */ #if LANGUAGE == C -#define RTAR /* RTC Alarm Reg. */ \ +#define RTAR /* RTC Alarm Reg. */ \ (*((volatile Word *) io_p2v (_RTAR))) -#define RCNR /* RTC CouNt Reg. */ \ +#define RCNR /* RTC CouNt Reg. */ \ (*((volatile Word *) io_p2v (_RCNR))) -#define RTTR /* RTC Trim Reg. */ \ +#define RTTR /* RTC Trim Reg. */ \ (*((volatile Word *) io_p2v (_RTTR))) -#define RTSR /* RTC Status Reg. */ \ +#define RTSR /* RTC Status Reg. */ \ (*((volatile Word *) io_p2v (_RTSR))) #endif /* LANGUAGE == C */ -#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ -#define RTTR_D Fld (10, 16) /* trim Delete count */ +#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ +#define RTTR_D Fld (10, 16) /* trim Delete count */ /* frtc = (1023*(C + 1) - D)*frtx/ */ - /* (1023*(C + 1)^2) */ + /* (1023*(C + 1)^2) */ /* Trtc = (1023*(C + 1)^2)*Trtx/ */ - /* (1023*(C + 1) - D) */ + /* (1023*(C + 1) - D) */ -#define RTSR_AL 0x00000001 /* ALarm detected */ -#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ -#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ -#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ +#define RTSR_AL 0x00000001 /* ALarm detected */ +#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ +#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ +#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ /* * Power Manager (PM) control registers * * Registers - * PMCR Power Manager (PM) Control Register (read/write). - * PSSR Power Manager (PM) Sleep Status Register (read/write). - * PSPR Power Manager (PM) Scratch-Pad Register (read/write). - * PWER Power Manager (PM) Wake-up Enable Register - * (read/write). - * PCFR Power Manager (PM) general ConFiguration Register - * (read/write). - * PPCR Power Manager (PM) Phase-Locked Loop (PLL) - * Configuration Register (read/write). - * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) - * Sleep state Register (read/write, see GPIO pins). - * POSR Power Manager (PM) Oscillator Status Register (read). + * PMCR Power Manager (PM) Control Register (read/write). + * PSSR Power Manager (PM) Sleep Status Register (read/write). + * PSPR Power Manager (PM) Scratch-Pad Register (read/write). + * PWER Power Manager (PM) Wake-up Enable Register + * (read/write). + * PCFR Power Manager (PM) general ConFiguration Register + * (read/write). + * PPCR Power Manager (PM) Phase-Locked Loop (PLL) + * Configuration Register (read/write). + * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) + * Sleep state Register (read/write, see GPIO pins). + * POSR Power Manager (PM) Oscillator Status Register (read). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). + * or 3.5795 MHz). * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). */ -#define _PMCR 0x90020000 /* PM Control Reg. */ -#define _PSSR 0x90020004 /* PM Sleep Status Reg. */ -#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */ -#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */ -#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */ -#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */ -#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */ -#define _POSR 0x9002001C /* PM Oscillator Status Reg. */ +#define _PMCR 0x90020000 /* PM Control Reg. */ +#define _PSSR 0x90020004 /* PM Sleep Status Reg. */ +#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */ +#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */ +#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */ +#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */ +#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */ +#define _POSR 0x9002001C /* PM Oscillator Status Reg. */ #if LANGUAGE == C -#define PMCR /* PM Control Reg. */ \ +#define PMCR /* PM Control Reg. */ \ (*((volatile Word *) io_p2v (_PMCR))) -#define PSSR /* PM Sleep Status Reg. */ \ +#define PSSR /* PM Sleep Status Reg. */ \ (*((volatile Word *) io_p2v (_PSSR))) -#define PSPR /* PM Scratch-Pad Reg. */ \ +#define PSPR /* PM Scratch-Pad Reg. */ \ (*((volatile Word *) io_p2v (_PSPR))) -#define PWER /* PM Wake-up Enable Reg. */ \ +#define PWER /* PM Wake-up Enable Reg. */ \ (*((volatile Word *) io_p2v (_PWER))) -#define PCFR /* PM general ConFiguration Reg. */ \ +#define PCFR /* PM general ConFiguration Reg. */ \ (*((volatile Word *) io_p2v (_PCFR))) -#define PPCR /* PM PLL Configuration Reg. */ \ +#define PPCR /* PM PLL Configuration Reg. */ \ (*((volatile Word *) io_p2v (_PPCR))) -#define PGSR /* PM GPIO Sleep state Reg. */ \ +#define PGSR /* PM GPIO Sleep state Reg. */ \ (*((volatile Word *) io_p2v (_PGSR))) -#define POSR /* PM Oscillator Status Reg. */ \ +#define POSR /* PM Oscillator Status Reg. */ \ (*((volatile Word *) io_p2v (_POSR))) #elif LANGUAGE == Assembly -#define PMCR (io_p2v (_PMCR)) -#define PSSR (io_p2v (_PSSR)) -#define PSPR (io_p2v (_PSPR)) -#define PWER (io_p2v (_PWER)) -#define PCFR (io_p2v (_PCFR)) -#define PPCR (io_p2v (_PPCR)) -#define PGSR (io_p2v (_PGSR)) -#define POSR (io_p2v (_POSR)) +#define PMCR (io_p2v (_PMCR)) +#define PSSR (io_p2v (_PSSR)) +#define PSPR (io_p2v (_PSPR)) +#define PWER (io_p2v (_PWER)) +#define PCFR (io_p2v (_PCFR)) +#define PPCR (io_p2v (_PPCR)) +#define PGSR (io_p2v (_PGSR)) +#define POSR (io_p2v (_POSR)) #endif /* LANGUAGE == C */ -#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ +#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ -#define PSSR_SS 0x00000001 /* Software Sleep */ -#define PSSR_BFS 0x00000002 /* Battery Fault Status */ - /* (BATT_FAULT) */ +#define PSSR_SS 0x00000001 /* Software Sleep */ +#define PSSR_BFS 0x00000002 /* Battery Fault Status */ + /* (BATT_FAULT) */ #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ -#define PSSR_DH 0x00000008 /* DRAM control Hold */ -#define PSSR_PH 0x00000010 /* Peripheral control Hold */ +#define PSSR_DH 0x00000008 /* DRAM control Hold */ +#define PSSR_PH 0x00000010 /* Peripheral control Hold */ -#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ -#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ -#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ -#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ -#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ -#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ -#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ -#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ -#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ -#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ -#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ -#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ -#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ -#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ -#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ -#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ -#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ -#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ -#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ -#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ -#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ -#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ -#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ -#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ -#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ -#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ -#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ -#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ -#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ -#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ +#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ +#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ +#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ +#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ +#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ +#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ +#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ +#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ +#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ +#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ +#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ +#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ +#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ +#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ +#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ +#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ +#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ +#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ +#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ +#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ +#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ +#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ +#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ +#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ +#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ +#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ +#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ +#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ +#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ +#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ -#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ -#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ -#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ -#define PCFR_FS 0x00000004 /* Float Static memory pins */ +#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ +#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ +#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ +#define PCFR_FS 0x00000004 /* Float Static memory pins */ #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ -#define PCFR_FO 0x00000008 /* Force RTC oscillator */ - /* (32.768 kHz) enable On */ +#define PCFR_FO 0x00000008 /* Force RTC oscillator */ + /* (32.768 kHz) enable On */ -#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ -#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ +#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ +#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ (0x00 << FShft (PPCR_CCF)) -#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ +#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ (0x01 << FShft (PPCR_CCF)) -#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ +#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ (0x02 << FShft (PPCR_CCF)) -#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ +#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ (0x03 << FShft (PPCR_CCF)) -#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ +#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ (0x04 << FShft (PPCR_CCF)) -#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ +#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ (0x05 << FShft (PPCR_CCF)) -#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ +#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ (0x06 << FShft (PPCR_CCF)) -#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ +#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ (0x07 << FShft (PPCR_CCF)) -#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ +#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ (0x08 << FShft (PPCR_CCF)) -#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ +#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ (0x09 << FShft (PPCR_CCF)) -#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ +#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ (0x0A << FShft (PPCR_CCF)) -#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ +#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ (0x0B << FShft (PPCR_CCF)) -#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ +#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ (0x0C << FShft (PPCR_CCF)) -#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ +#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ (0x0D << FShft (PPCR_CCF)) -#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ +#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ (0x0E << FShft (PPCR_CCF)) -#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ +#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ (0x0F << FShft (PPCR_CCF)) - /* 3.6864 MHz crystal (fxtl): */ -#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ -#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ -#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ -#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ -#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ -#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ -#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ -#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ -#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ -#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ -#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ -#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ -#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ -#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ -#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ -#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ - /* 3.5795 MHz crystal (fxtl): */ -#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ -#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ -#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ -#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ -#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ -#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ -#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ -#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ -#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ -#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ -#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ -#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ -#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ -#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ -#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ -#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ + /* 3.6864 MHz crystal (fxtl): */ +#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ +#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ +#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ +#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ +#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ +#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ +#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ +#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ +#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ +#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ +#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ +#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ +#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ +#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ +#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ +#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ + /* 3.5795 MHz crystal (fxtl): */ +#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ +#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ +#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ +#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ +#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ +#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ +#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ +#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ +#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ +#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ +#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ +#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ +#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ +#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ +#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ +#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ @@ -1391,75 +1391,75 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * Reset Controller (RC) control registers * * Registers - * RSRR Reset Controller (RC) Software Reset Register - * (read/write). - * RCSR Reset Controller (RC) Status Register (read/write). + * RSRR Reset Controller (RC) Software Reset Register + * (read/write). + * RCSR Reset Controller (RC) Status Register (read/write). */ -#define _RSRR 0x90030000 /* RC Software Reset Reg. */ -#define _RCSR 0x90030004 /* RC Status Reg. */ +#define _RSRR 0x90030000 /* RC Software Reset Reg. */ +#define _RCSR 0x90030004 /* RC Status Reg. */ #if LANGUAGE == C -#define RSRR /* RC Software Reset Reg. */ \ +#define RSRR /* RC Software Reset Reg. */ \ (*((volatile Word *) io_p2v (_RSRR))) -#define RCSR /* RC Status Reg. */ \ +#define RCSR /* RC Status Reg. */ \ (*((volatile Word *) io_p2v (_RCSR))) #endif /* LANGUAGE == C */ -#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ +#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ -#define RCSR_HWR 0x00000001 /* HardWare Reset */ -#define RCSR_SWR 0x00000002 /* SoftWare Reset */ -#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ -#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ +#define RCSR_HWR 0x00000001 /* HardWare Reset */ +#define RCSR_SWR 0x00000002 /* SoftWare Reset */ +#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ +#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ /* * Test unit control registers * * Registers - * TUCR Test Unit Control Register (read/write). + * TUCR Test Unit Control Register (read/write). */ -#define _TUCR 0x90030008 /* Test Unit Control Reg. */ +#define _TUCR 0x90030008 /* Test Unit Control Reg. */ #if LANGUAGE == C -#define TUCR /* Test Unit Control Reg. */ \ +#define TUCR /* Test Unit Control Reg. */ \ (*((volatile Word *) io_p2v (_TUCR))) #endif /* LANGUAGE == C */ -#define TUCR_TIC 0x00000040 /* TIC mode */ -#define TUCR_TTST 0x00000080 /* Trim TeST mode */ -#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ - /* Check */ -#define TUCR_PMD 0x00000200 /* Power Management Disable */ -#define TUCR_MR 0x00000400 /* Memory Request mode */ +#define TUCR_TIC 0x00000040 /* TIC mode */ +#define TUCR_TTST 0x00000080 /* Trim TeST mode */ +#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ + /* Check */ +#define TUCR_PMD 0x00000200 /* Power Management Disable */ +#define TUCR_MR 0x00000400 /* Memory Request mode */ #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ /* grant (MBGNT) on GPIO [22:21] */ -#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ -#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ +#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ +#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ -#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ +#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ -#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ +#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ (0 << FShft (TUCR_TSEL)) -#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ +#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ (1 << FShft (TUCR_TSEL)) -#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ +#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ (2 << FShft (TUCR_TSEL)) -#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ +#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ (3 << FShft (TUCR_TSEL)) -#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ - /* Clocks on GPIO [26:27] */ \ +#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ + /* Clocks on GPIO [26:27] */ \ (4 << FShft (TUCR_TSEL)) -#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ - /* (Alternative) */ \ +#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ + /* (Alternative) */ \ (5 << FShft (TUCR_TSEL)) -#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ +#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ (6 << FShft (TUCR_TSEL)) -#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ +#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ (7 << FShft (TUCR_TSEL)) @@ -1467,52 +1467,52 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * General-Purpose Input/Output (GPIO) control registers * * Registers - * GPLR General-Purpose Input/Output (GPIO) Pin Level - * Register (read). - * GPDR General-Purpose Input/Output (GPIO) Pin Direction - * Register (read/write). - * GPSR General-Purpose Input/Output (GPIO) Pin output Set - * Register (write). - * GPCR General-Purpose Input/Output (GPIO) Pin output Clear - * Register (write). - * GRER General-Purpose Input/Output (GPIO) Rising-Edge - * detect Register (read/write). - * GFER General-Purpose Input/Output (GPIO) Falling-Edge - * detect Register (read/write). - * GEDR General-Purpose Input/Output (GPIO) Edge Detect - * status Register (read/write). - * GAFR General-Purpose Input/Output (GPIO) Alternate - * Function Register (read/write). + * GPLR General-Purpose Input/Output (GPIO) Pin Level + * Register (read). + * GPDR General-Purpose Input/Output (GPIO) Pin Direction + * Register (read/write). + * GPSR General-Purpose Input/Output (GPIO) Pin output Set + * Register (write). + * GPCR General-Purpose Input/Output (GPIO) Pin output Clear + * Register (write). + * GRER General-Purpose Input/Output (GPIO) Rising-Edge + * detect Register (read/write). + * GFER General-Purpose Input/Output (GPIO) Falling-Edge + * detect Register (read/write). + * GEDR General-Purpose Input/Output (GPIO) Edge Detect + * status Register (read/write). + * GAFR General-Purpose Input/Output (GPIO) Alternate + * Function Register (read/write). * * Clock * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). */ -#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */ -#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */ -#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */ -#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */ -#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */ -#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */ -#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */ -#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */ +#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */ +#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */ +#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */ +#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */ +#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */ +#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */ +#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */ +#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */ #if LANGUAGE == C -#define GPLR /* GPIO Pin Level Reg. */ \ +#define GPLR /* GPIO Pin Level Reg. */ \ (*((volatile Word *) io_p2v (_GPLR))) -#define GPDR /* GPIO Pin Direction Reg. */ \ +#define GPDR /* GPIO Pin Direction Reg. */ \ (*((volatile Word *) io_p2v (_GPDR))) -#define GPSR /* GPIO Pin output Set Reg. */ \ +#define GPSR /* GPIO Pin output Set Reg. */ \ (*((volatile Word *) io_p2v (_GPSR))) -#define GPCR /* GPIO Pin output Clear Reg. */ \ +#define GPCR /* GPIO Pin output Clear Reg. */ \ (*((volatile Word *) io_p2v (_GPCR))) -#define GRER /* GPIO Rising-Edge detect Reg. */ \ +#define GRER /* GPIO Rising-Edge detect Reg. */ \ (*((volatile Word *) io_p2v (_GRER))) -#define GFER /* GPIO Falling-Edge detect Reg. */ \ +#define GFER /* GPIO Falling-Edge detect Reg. */ \ (*((volatile Word *) io_p2v (_GFER))) -#define GEDR /* GPIO Edge Detect status Reg. */ \ +#define GEDR /* GPIO Edge Detect status Reg. */ \ (*((volatile Word *) io_p2v (_GEDR))) -#define GAFR /* GPIO Alternate Function Reg. */ \ +#define GAFR /* GPIO Alternate Function Reg. */ \ (*((volatile Word *) io_p2v (_GAFR))) #elif LANGUAGE == Assembly @@ -1530,280 +1530,280 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define GPIO_MIN (0) #define GPIO_MAX (27) -#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ +#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ (0x00000001 << (Nb)) -#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ -#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ -#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ -#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ -#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ -#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ -#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ -#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ -#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ -#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ -#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ -#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ -#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ -#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ -#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ -#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ -#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ -#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ -#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ -#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ -#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ -#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ -#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ -#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ -#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ -#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ -#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ -#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ +#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ +#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ +#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ +#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ +#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ +#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ +#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ +#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ +#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ +#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ +#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ +#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ +#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ +#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ +#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ +#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ +#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ +#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ +#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ +#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ +#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ +#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ +#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ +#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ +#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ +#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ +#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ +#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ -#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ +#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ GPIO_GPIO ((Nb) - 6) -#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ -#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ -#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ -#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ -#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ -#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ -#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ -#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ - /* ser. port 4: */ -#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ -#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ -#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ -#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ - /* ser. port 1: */ -#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ -#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ -#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ -#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ -#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ - /* ser. port 4: */ -#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ - /* ser. port 3: */ -#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ - /* ser. port 4: */ -#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ - /* test controller: */ -#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ -#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ -#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ -#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ -#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ -#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ +#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ +#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ +#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ +#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ +#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ +#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ +#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ +#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ + /* ser. port 4: */ +#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ +#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ +#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ +#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ + /* ser. port 1: */ +#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ +#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ +#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ +#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ +#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ + /* ser. port 4: */ +#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ + /* ser. port 3: */ +#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ + /* ser. port 4: */ +#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ + /* test controller: */ +#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ +#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ +#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ +#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ +#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ +#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ -#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ +#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ -#define GPDR_In 0 /* Input */ -#define GPDR_Out 1 /* Output */ +#define GPDR_In 0 /* Input */ +#define GPDR_Out 1 /* Output */ /* * Interrupt Controller (IC) control registers * * Registers - * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) - * Pending register (read). - * ICMR Interrupt Controller (IC) Mask Register (read/write). - * ICLR Interrupt Controller (IC) Level Register (read/write). - * ICCR Interrupt Controller (IC) Control Register - * (read/write). - * [The ICCR register is only implemented in versions 2.0 - * (rev. = 8) and higher of the StrongARM SA-1100.] - * ICFP Interrupt Controller (IC) Fast Interrupt reQuest - * (FIQ) Pending register (read). - * ICPR Interrupt Controller (IC) Pending Register (read). - * [The ICPR register is active low (inverted) in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it is active high (non-inverted) in - * versions 2.0 (rev. = 8) and higher.] + * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) + * Pending register (read). + * ICMR Interrupt Controller (IC) Mask Register (read/write). + * ICLR Interrupt Controller (IC) Level Register (read/write). + * ICCR Interrupt Controller (IC) Control Register + * (read/write). + * [The ICCR register is only implemented in versions 2.0 + * (rev. = 8) and higher of the StrongARM SA-1100.] + * ICFP Interrupt Controller (IC) Fast Interrupt reQuest + * (FIQ) Pending register (read). + * ICPR Interrupt Controller (IC) Pending Register (read). + * [The ICPR register is active low (inverted) in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it is active high (non-inverted) in + * versions 2.0 (rev. = 8) and higher.] */ -#define _ICIP 0x90050000 /* IC IRQ Pending reg. */ -#define _ICMR 0x90050004 /* IC Mask Reg. */ -#define _ICLR 0x90050008 /* IC Level Reg. */ -#define _ICCR 0x9005000C /* IC Control Reg. */ -#define _ICFP 0x90050010 /* IC FIQ Pending reg. */ -#define _ICPR 0x90050020 /* IC Pending Reg. */ +#define _ICIP 0x90050000 /* IC IRQ Pending reg. */ +#define _ICMR 0x90050004 /* IC Mask Reg. */ +#define _ICLR 0x90050008 /* IC Level Reg. */ +#define _ICCR 0x9005000C /* IC Control Reg. */ +#define _ICFP 0x90050010 /* IC FIQ Pending reg. */ +#define _ICPR 0x90050020 /* IC Pending Reg. */ #if LANGUAGE == C -#define ICIP /* IC IRQ Pending reg. */ \ +#define ICIP /* IC IRQ Pending reg. */ \ (*((volatile Word *) io_p2v (_ICIP))) -#define ICMR /* IC Mask Reg. */ \ +#define ICMR /* IC Mask Reg. */ \ (*((volatile Word *) io_p2v (_ICMR))) -#define ICLR /* IC Level Reg. */ \ +#define ICLR /* IC Level Reg. */ \ (*((volatile Word *) io_p2v (_ICLR))) -#define ICCR /* IC Control Reg. */ \ +#define ICCR /* IC Control Reg. */ \ (*((volatile Word *) io_p2v (_ICCR))) -#define ICFP /* IC FIQ Pending reg. */ \ +#define ICFP /* IC FIQ Pending reg. */ \ (*((volatile Word *) io_p2v (_ICFP))) -#define ICPR /* IC Pending Reg. */ \ +#define ICPR /* IC Pending Reg. */ \ (*((volatile Word *) io_p2v (_ICPR))) #endif /* LANGUAGE == C */ -#define IC_GPIO(Nb) /* GPIO [0..10] */ \ +#define IC_GPIO(Nb) /* GPIO [0..10] */ \ (0x00000001 << (Nb)) -#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ -#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ -#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ -#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ -#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ -#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ -#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ -#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ -#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ -#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ -#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ -#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ -#define IC_LCD 0x00001000 /* LCD controller */ -#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ -#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ -#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ -#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ -#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ -#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ -#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ -#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ +#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ +#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ +#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ +#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ +#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ +#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ +#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ +#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ +#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ +#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ +#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ +#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ +#define IC_LCD 0x00001000 /* LCD controller */ +#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ +#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ +#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ +#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ +#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ +#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ +#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ +#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ (0x00100000 << (Nb)) -#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ -#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ -#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ -#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ -#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ -#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ -#define IC_OST(Nb) /* OS Timer match [0..3] */ \ +#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ +#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ +#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ +#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ +#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ +#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ +#define IC_OST(Nb) /* OS Timer match [0..3] */ \ (0x04000000 << (Nb)) -#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ -#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ -#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ -#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ -#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ -#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ +#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ +#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ +#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ +#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ +#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ +#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ -#define ICLR_IRQ 0 /* Interrupt ReQuest */ -#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ +#define ICLR_IRQ 0 /* Interrupt ReQuest */ +#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ -#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ - /* Mask */ +#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ + /* Mask */ #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ - /* (ICMR ignored) */ + /* (ICMR ignored) */ #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ - /* enable (ICMR used) */ + /* enable (ICMR used) */ /* * Peripheral Pin Controller (PPC) control registers * * Registers - * PPDR Peripheral Pin Controller (PPC) Pin Direction - * Register (read/write). - * PPSR Peripheral Pin Controller (PPC) Pin State Register - * (read/write). - * PPAR Peripheral Pin Controller (PPC) Pin Assignment - * Register (read/write). - * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin - * Direction Register (read/write). - * PPFR Peripheral Pin Controller (PPC) Pin Flag Register - * (read). + * PPDR Peripheral Pin Controller (PPC) Pin Direction + * Register (read/write). + * PPSR Peripheral Pin Controller (PPC) Pin State Register + * (read/write). + * PPAR Peripheral Pin Controller (PPC) Pin Assignment + * Register (read/write). + * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin + * Direction Register (read/write). + * PPFR Peripheral Pin Controller (PPC) Pin Flag Register + * (read). */ -#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */ -#define _PPSR 0x90060004 /* PPC Pin State Reg. */ -#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ -#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ - /* Reg. */ -#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ +#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */ +#define _PPSR 0x90060004 /* PPC Pin State Reg. */ +#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ +#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ + /* Reg. */ +#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ #if LANGUAGE == C -#define PPDR /* PPC Pin Direction Reg. */ \ +#define PPDR /* PPC Pin Direction Reg. */ \ (*((volatile Word *) io_p2v (_PPDR))) -#define PPSR /* PPC Pin State Reg. */ \ +#define PPSR /* PPC Pin State Reg. */ \ (*((volatile Word *) io_p2v (_PPSR))) -#define PPAR /* PPC Pin Assignment Reg. */ \ +#define PPAR /* PPC Pin Assignment Reg. */ \ (*((volatile Word *) io_p2v (_PPAR))) -#define PSDR /* PPC Sleep-mode pin Direction */ \ - /* Reg. */ \ +#define PSDR /* PPC Sleep-mode pin Direction */ \ + /* Reg. */ \ (*((volatile Word *) io_p2v (_PSDR))) -#define PPFR /* PPC Pin Flag Reg. */ \ +#define PPFR /* PPC Pin Flag Reg. */ \ (*((volatile Word *) io_p2v (_PPFR))) #endif /* LANGUAGE == C */ -#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ +#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ (0x00000001 << (Nb)) -#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ -#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ -#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ -#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ -#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ -#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ -#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ -#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ -#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ -#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ -#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ -#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ - /* ser. port 1: */ -#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ -#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ - /* ser. port 2: */ -#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ -#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ - /* ser. port 3: */ -#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ -#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ - /* ser. port 4: */ -#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ -#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ -#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ -#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ +#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ +#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ +#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ +#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ +#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ +#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ +#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ +#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ +#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ +#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ +#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ +#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ + /* ser. port 1: */ +#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ +#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ + /* ser. port 2: */ +#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ +#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ + /* ser. port 3: */ +#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ +#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ + /* ser. port 4: */ +#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ +#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ +#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ +#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ -#define PPDR_In 0 /* Input */ -#define PPDR_Out 1 /* Output */ +#define PPDR_In 0 /* Input */ +#define PPDR_Out 1 /* Output */ - /* ser. port 1: */ -#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ -#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ -#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ - /* ser. port 4: */ -#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ + /* ser. port 1: */ +#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ +#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ +#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ + /* ser. port 4: */ +#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ - /* & SFRM_C */ -#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ + /* & SFRM_C */ +#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ -#define PSDR_OutL 0 /* Output Low in sleep mode */ -#define PSDR_Flt 1 /* Floating (input) in sleep mode */ +#define PSDR_OutL 0 /* Output Low in sleep mode */ +#define PSDR_Flt 1 /* Floating (input) in sleep mode */ -#define PPFR_LCD 0x00000001 /* LCD controller */ +#define PPFR_LCD 0x00000001 /* LCD controller */ #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ -#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ -#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ -#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ -#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ -#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ -#define PPFR_PerEn 0 /* Peripheral Enabled */ -#define PPFR_PPCEn 1 /* PPC Enabled */ +#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ +#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ +#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ +#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ +#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ +#define PPFR_PerEn 0 /* Peripheral Enabled */ +#define PPFR_PPCEn 1 /* PPC Enabled */ /* * Dynamic Random-Access Memory (DRAM) control registers * * Registers - * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) - * CoNFiGuration register (read/write). - * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 0 - * (read/write). - * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 1 - * (read/write). - * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 2 - * (read/write). + * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) + * CoNFiGuration register (read/write). + * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 0 + * (read/write). + * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 1 + * (read/write). + * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 2 + * (read/write). * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). @@ -1811,23 +1811,23 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * fcas, Tcas Frequency, period of the DRAM CAS shift registers. */ - /* Memory system: */ -#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ -#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ + /* Memory system: */ +#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ +#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ (0xA0000004 + (Nb)*4) -#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ -#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ -#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ +#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ +#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ +#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ #if LANGUAGE == C - /* Memory system: */ -#define MDCNFG /* DRAM CoNFiGuration reg. */ \ + /* Memory system: */ +#define MDCNFG /* DRAM CoNFiGuration reg. */ \ (*((volatile Word *) io_p2v (_MDCNFG))) -#define MDCAS /* DRAM CAS shift reg. [0..3] */ \ +#define MDCAS /* DRAM CAS shift reg. [0..3] */ \ ((volatile Word *) io_p2v (_MDCAS (0))) -#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ -#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ -#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ +#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ +#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ +#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ #elif LANGUAGE == Assembly @@ -1836,58 +1836,58 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #endif /* LANGUAGE == C */ /* SA1100 MDCNFG values */ -#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ +#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ (0x00000001 << (Nb)) -#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ -#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ -#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ -#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ -#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ -#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ +#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ +#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ +#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ +#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ +#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ +#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ (((Add) - 9) << FShft (MDCNFG_DRAC)) #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ - /* (fcas = fcpu/2) */ + /* (fcas = fcpu/2) */ #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ -#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ +#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) -#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ +#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) -#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ -#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ +#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ +#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) -#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ +#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) -#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ -#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ +#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ +#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ ((Tcpu) << FShft (MDCNFG_TDL)) #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ - /* [Tmem] */ -#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ - /* [0..262136 Tcpu] */ \ + /* [Tmem] */ +#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ + /* [0..262136 Tcpu] */ \ ((Tcpu)/8 << FShft (MDCNFG_DRI)) /* SA1110 MDCNFG values */ -#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ -#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ +#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ +#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ -#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ +#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ - /* bank 0/1 */ + /* bank 0/1 */ #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ -#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ +#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ - /* deassertion 0/1 */ + /* deassertion 0/1 */ #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ -#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ -#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ +#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ +#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ -#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ +#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ - /* bank 0/1 */ + /* bank 0/1 */ #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ -#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ +#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ - /* deassertion 0/1 */ + /* deassertion 0/1 */ #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ @@ -1895,32 +1895,32 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * Static memory control registers * * Registers - * MSC0 Memory system: Static memory Control register 0 - * (read/write). - * MSC1 Memory system: Static memory Control register 1 - * (read/write). + * MSC0 Memory system: Static memory Control register 0 + * (read/write). + * MSC1 Memory system: Static memory Control register 1 + * (read/write). * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). */ - /* Memory system: */ -#define _MSC(Nb) /* Static memory Control reg. */ \ - /* [0..1] */ \ + /* Memory system: */ +#define _MSC(Nb) /* Static memory Control reg. */ \ + /* [0..1] */ \ (0xA0000010 + (Nb)*4) -#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ -#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ +#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ +#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ #define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */ #if LANGUAGE == C - /* Memory system: */ -#define MSC /* Static memory Control reg. */ \ - /* [0..1] */ \ + /* Memory system: */ +#define MSC /* Static memory Control reg. */ \ + /* [0..1] */ \ ((volatile Word *) io_p2v (_MSC (0))) -#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ -#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ -#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */ +#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ +#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ +#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */ #elif LANGUAGE == Assembly @@ -1930,54 +1930,54 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #endif /* LANGUAGE == C */ -#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ +#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ Fld (16, ((Nb) Modulo 2)*16) -#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ -#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ -#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ -#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ +#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ +#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ +#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ +#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ -#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ -#define MSC_NonBrst /* Non-Burst static memory */ \ +#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ +#define MSC_NonBrst /* Non-Burst static memory */ \ (0 << FShft (MSC_RT)) -#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ +#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ (1 << FShft (MSC_RT)) -#define MSC_Brst4 /* Burst-of-4 static memory */ \ +#define MSC_Brst4 /* Burst-of-4 static memory */ \ (2 << FShft (MSC_RT)) -#define MSC_Brst8 /* Burst-of-8 static memory */ \ +#define MSC_Brst8 /* Burst-of-8 static memory */ \ (3 << FShft (MSC_RT)) -#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ -#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ -#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ -#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ - /* First access - 1(.5) [Tmem] */ -#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ +#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ +#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ +#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ +#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ + /* First access - 1(.5) [Tmem] */ +#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ /* static memory) [3..65 Tcpu] */ \ ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) -#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ +#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) -#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ +#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ /* static memory) [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) -#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ +#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) -#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ - /* Next access - 1 [Tmem] */ -#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ +#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ + /* Next access - 1 [Tmem] */ +#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ /* static memory) [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) -#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ +#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) -#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ +#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ /* static memory) [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) -#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ +#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) -#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ - /* time/2 [Tmem] */ -#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ +#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ + /* time/2 [Tmem] */ +#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ (((Tcpu)/4) << FShft (MSC_RRR)) -#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ +#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) @@ -1986,8 +1986,8 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * register * * Register - * MECR Memory system: Expansion memory bus (PCMCIA) - * Configuration Register (read/write). + * MECR Memory system: Expansion memory bus (PCMCIA) + * Configuration Register (read/write). * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). @@ -1995,37 +1995,37 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). */ - /* Memory system: */ -#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ - /* Configuration Reg. */ + /* Memory system: */ +#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ + /* Configuration Reg. */ #if LANGUAGE == C - /* Memory system: */ -#define MECR /* Expansion memory bus (PCMCIA) */ \ - /* Configuration Reg. */ \ + /* Memory system: */ +#define MECR /* Expansion memory bus (PCMCIA) */ \ + /* Configuration Reg. */ \ (*((volatile Word *) io_p2v (_MECR))) #endif /* LANGUAGE == C */ -#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ +#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ Fld (15, (Nb)*16) -#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ -#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ +#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ +#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ -#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ -#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ +#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ +#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) -#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ +#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) -#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ - /* [Tmem] */ -#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ +#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ + /* [Tmem] */ +#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) -#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ +#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ -#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ +#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) -#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ +#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) /* @@ -2035,7 +2035,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _MDREFR 0xA000001C #if LANGUAGE == C - /* Memory system: */ + /* Memory system: */ #define MDREFR \ (*((volatile Word *) io_p2v (_MDREFR))) @@ -2064,769 +2064,769 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * Direct Memory Access (DMA) control registers * * Registers - * DDAR0 Direct Memory Access (DMA) Device Address Register - * channel 0 (read/write). - * DCSR0 Direct Memory Access (DMA) Control and Status - * Register channel 0 (read/write). - * DBSA0 Direct Memory Access (DMA) Buffer Start address - * register A channel 0 (read/write). - * DBTA0 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 0 (read/write). - * DBSB0 Direct Memory Access (DMA) Buffer Start address - * register B channel 0 (read/write). - * DBTB0 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 0 (read/write). + * DDAR0 Direct Memory Access (DMA) Device Address Register + * channel 0 (read/write). + * DCSR0 Direct Memory Access (DMA) Control and Status + * Register channel 0 (read/write). + * DBSA0 Direct Memory Access (DMA) Buffer Start address + * register A channel 0 (read/write). + * DBTA0 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 0 (read/write). + * DBSB0 Direct Memory Access (DMA) Buffer Start address + * register B channel 0 (read/write). + * DBTB0 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 0 (read/write). * - * DDAR1 Direct Memory Access (DMA) Device Address Register - * channel 1 (read/write). - * DCSR1 Direct Memory Access (DMA) Control and Status - * Register channel 1 (read/write). - * DBSA1 Direct Memory Access (DMA) Buffer Start address - * register A channel 1 (read/write). - * DBTA1 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 1 (read/write). - * DBSB1 Direct Memory Access (DMA) Buffer Start address - * register B channel 1 (read/write). - * DBTB1 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 1 (read/write). + * DDAR1 Direct Memory Access (DMA) Device Address Register + * channel 1 (read/write). + * DCSR1 Direct Memory Access (DMA) Control and Status + * Register channel 1 (read/write). + * DBSA1 Direct Memory Access (DMA) Buffer Start address + * register A channel 1 (read/write). + * DBTA1 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 1 (read/write). + * DBSB1 Direct Memory Access (DMA) Buffer Start address + * register B channel 1 (read/write). + * DBTB1 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 1 (read/write). * - * DDAR2 Direct Memory Access (DMA) Device Address Register - * channel 2 (read/write). - * DCSR2 Direct Memory Access (DMA) Control and Status - * Register channel 2 (read/write). - * DBSA2 Direct Memory Access (DMA) Buffer Start address - * register A channel 2 (read/write). - * DBTA2 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 2 (read/write). - * DBSB2 Direct Memory Access (DMA) Buffer Start address - * register B channel 2 (read/write). - * DBTB2 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 2 (read/write). + * DDAR2 Direct Memory Access (DMA) Device Address Register + * channel 2 (read/write). + * DCSR2 Direct Memory Access (DMA) Control and Status + * Register channel 2 (read/write). + * DBSA2 Direct Memory Access (DMA) Buffer Start address + * register A channel 2 (read/write). + * DBTA2 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 2 (read/write). + * DBSB2 Direct Memory Access (DMA) Buffer Start address + * register B channel 2 (read/write). + * DBTB2 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 2 (read/write). * - * DDAR3 Direct Memory Access (DMA) Device Address Register - * channel 3 (read/write). - * DCSR3 Direct Memory Access (DMA) Control and Status - * Register channel 3 (read/write). - * DBSA3 Direct Memory Access (DMA) Buffer Start address - * register A channel 3 (read/write). - * DBTA3 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 3 (read/write). - * DBSB3 Direct Memory Access (DMA) Buffer Start address - * register B channel 3 (read/write). - * DBTB3 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 3 (read/write). + * DDAR3 Direct Memory Access (DMA) Device Address Register + * channel 3 (read/write). + * DCSR3 Direct Memory Access (DMA) Control and Status + * Register channel 3 (read/write). + * DBSA3 Direct Memory Access (DMA) Buffer Start address + * register A channel 3 (read/write). + * DBTA3 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 3 (read/write). + * DBSB3 Direct Memory Access (DMA) Buffer Start address + * register B channel 3 (read/write). + * DBTB3 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 3 (read/write). * - * DDAR4 Direct Memory Access (DMA) Device Address Register - * channel 4 (read/write). - * DCSR4 Direct Memory Access (DMA) Control and Status - * Register channel 4 (read/write). - * DBSA4 Direct Memory Access (DMA) Buffer Start address - * register A channel 4 (read/write). - * DBTA4 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 4 (read/write). - * DBSB4 Direct Memory Access (DMA) Buffer Start address - * register B channel 4 (read/write). - * DBTB4 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 4 (read/write). + * DDAR4 Direct Memory Access (DMA) Device Address Register + * channel 4 (read/write). + * DCSR4 Direct Memory Access (DMA) Control and Status + * Register channel 4 (read/write). + * DBSA4 Direct Memory Access (DMA) Buffer Start address + * register A channel 4 (read/write). + * DBTA4 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 4 (read/write). + * DBSB4 Direct Memory Access (DMA) Buffer Start address + * register B channel 4 (read/write). + * DBTB4 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 4 (read/write). * - * DDAR5 Direct Memory Access (DMA) Device Address Register - * channel 5 (read/write). - * DCSR5 Direct Memory Access (DMA) Control and Status - * Register channel 5 (read/write). - * DBSA5 Direct Memory Access (DMA) Buffer Start address - * register A channel 5 (read/write). - * DBTA5 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 5 (read/write). - * DBSB5 Direct Memory Access (DMA) Buffer Start address - * register B channel 5 (read/write). - * DBTB5 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 5 (read/write). + * DDAR5 Direct Memory Access (DMA) Device Address Register + * channel 5 (read/write). + * DCSR5 Direct Memory Access (DMA) Control and Status + * Register channel 5 (read/write). + * DBSA5 Direct Memory Access (DMA) Buffer Start address + * register A channel 5 (read/write). + * DBTA5 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 5 (read/write). + * DBSB5 Direct Memory Access (DMA) Buffer Start address + * register B channel 5 (read/write). + * DBTB5 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 5 (read/write). */ -#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ +#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ -#define _DDAR(Nb) /* DMA Device Address Reg. */ \ - /* channel [0..5] */ \ +#define _DDAR(Nb) /* DMA Device Address Reg. */ \ + /* channel [0..5] */ \ (0xB0000000 + (Nb)*DMASp) -#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ - /* channel [0..5] (write) */ \ +#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ + /* channel [0..5] (write) */ \ (0xB0000004 + (Nb)*DMASp) -#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ - /* channel [0..5] (write) */ \ +#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ + /* channel [0..5] (write) */ \ (0xB0000008 + (Nb)*DMASp) -#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ - /* channel [0..5] (read) */ \ +#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ + /* channel [0..5] (read) */ \ (0xB000000C + (Nb)*DMASp) -#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ - /* channel [0..5] */ \ +#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ + /* channel [0..5] */ \ (0xB0000010 + (Nb)*DMASp) -#define _DBTA(Nb) /* DMA Buffer Transfer count */ \ - /* reg. A channel [0..5] */ \ +#define _DBTA(Nb) /* DMA Buffer Transfer count */ \ + /* reg. A channel [0..5] */ \ (0xB0000014 + (Nb)*DMASp) -#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ - /* channel [0..5] */ \ +#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ + /* channel [0..5] */ \ (0xB0000018 + (Nb)*DMASp) -#define _DBTB(Nb) /* DMA Buffer Transfer count */ \ - /* reg. B channel [0..5] */ \ +#define _DBTB(Nb) /* DMA Buffer Transfer count */ \ + /* reg. B channel [0..5] */ \ (0xB000001C + (Nb)*DMASp) -#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ - /* channel 0 */ +#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ + /* channel 0 */ #define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */ - /* channel 0 (write) */ + /* channel 0 (write) */ #define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */ - /* channel 0 (write) */ + /* channel 0 (write) */ #define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */ - /* channel 0 (read) */ -#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ - /* channel 0 */ -#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ - /* reg. A channel 0 */ -#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ - /* channel 0 */ -#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ - /* reg. B channel 0 */ + /* channel 0 (read) */ +#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ + /* channel 0 */ +#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ + /* reg. A channel 0 */ +#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ + /* channel 0 */ +#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ + /* reg. B channel 0 */ -#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ - /* channel 1 */ +#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ + /* channel 1 */ #define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */ - /* channel 1 (write) */ + /* channel 1 (write) */ #define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */ - /* channel 1 (write) */ + /* channel 1 (write) */ #define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */ - /* channel 1 (read) */ -#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ - /* channel 1 */ -#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ - /* reg. A channel 1 */ -#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ - /* channel 1 */ -#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ - /* reg. B channel 1 */ + /* channel 1 (read) */ +#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ + /* channel 1 */ +#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ + /* reg. A channel 1 */ +#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ + /* channel 1 */ +#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ + /* reg. B channel 1 */ -#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ - /* channel 2 */ +#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ + /* channel 2 */ #define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */ - /* channel 2 (write) */ + /* channel 2 (write) */ #define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */ - /* channel 2 (write) */ + /* channel 2 (write) */ #define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */ - /* channel 2 (read) */ -#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ - /* channel 2 */ -#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ - /* reg. A channel 2 */ -#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ - /* channel 2 */ -#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ - /* reg. B channel 2 */ + /* channel 2 (read) */ +#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ + /* channel 2 */ +#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ + /* reg. A channel 2 */ +#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ + /* channel 2 */ +#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ + /* reg. B channel 2 */ -#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ - /* channel 3 */ +#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ + /* channel 3 */ #define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */ - /* channel 3 (write) */ + /* channel 3 (write) */ #define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */ - /* channel 3 (write) */ + /* channel 3 (write) */ #define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */ - /* channel 3 (read) */ -#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ - /* channel 3 */ -#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ - /* reg. A channel 3 */ -#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ - /* channel 3 */ -#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ - /* reg. B channel 3 */ + /* channel 3 (read) */ +#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ + /* channel 3 */ +#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ + /* reg. A channel 3 */ +#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ + /* channel 3 */ +#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ + /* reg. B channel 3 */ -#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ - /* channel 4 */ +#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ + /* channel 4 */ #define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */ - /* channel 4 (write) */ + /* channel 4 (write) */ #define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */ - /* channel 4 (write) */ + /* channel 4 (write) */ #define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */ - /* channel 4 (read) */ -#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ - /* channel 4 */ -#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ - /* reg. A channel 4 */ -#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ - /* channel 4 */ -#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ - /* reg. B channel 4 */ + /* channel 4 (read) */ +#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ + /* channel 4 */ +#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ + /* reg. A channel 4 */ +#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ + /* channel 4 */ +#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ + /* reg. B channel 4 */ -#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ - /* channel 5 */ +#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ + /* channel 5 */ #define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */ - /* channel 5 (write) */ + /* channel 5 (write) */ #define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */ - /* channel 5 (write) */ + /* channel 5 (write) */ #define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */ - /* channel 5 (read) */ -#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ - /* channel 5 */ -#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ - /* reg. A channel 5 */ -#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ - /* channel 5 */ -#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ - /* reg. B channel 5 */ + /* channel 5 (read) */ +#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ + /* channel 5 */ +#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ + /* reg. A channel 5 */ +#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ + /* channel 5 */ +#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ + /* reg. B channel 5 */ #if LANGUAGE == C -#define DDAR0 /* DMA Device Address Reg. */ \ - /* channel 0 */ \ +#define DDAR0 /* DMA Device Address Reg. */ \ + /* channel 0 */ \ (*((volatile Word *) io_p2v (_DDAR0))) -#define SetDCSR0 /* Set DMA Control & Status Reg. */ \ - /* channel 0 (write) */ \ +#define SetDCSR0 /* Set DMA Control & Status Reg. */ \ + /* channel 0 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR0))) -#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ - /* channel 0 (write) */ \ +#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ + /* channel 0 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR0))) -#define RdDCSR0 /* Read DMA Control & Status Reg. */ \ - /* channel 0 (read) */ \ +#define RdDCSR0 /* Read DMA Control & Status Reg. */ \ + /* channel 0 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR0))) -#define DBSA0 /* DMA Buffer Start address reg. A */ \ - /* channel 0 */ \ +#define DBSA0 /* DMA Buffer Start address reg. A */ \ + /* channel 0 */ \ (*((volatile Address *) io_p2v (_DBSA0))) -#define DBTA0 /* DMA Buffer Transfer count */ \ - /* reg. A channel 0 */ \ +#define DBTA0 /* DMA Buffer Transfer count */ \ + /* reg. A channel 0 */ \ (*((volatile Word *) io_p2v (_DBTA0))) -#define DBSB0 /* DMA Buffer Start address reg. B */ \ - /* channel 0 */ \ +#define DBSB0 /* DMA Buffer Start address reg. B */ \ + /* channel 0 */ \ (*((volatile Address *) io_p2v (_DBSB0))) -#define DBTB0 /* DMA Buffer Transfer count */ \ - /* reg. B channel 0 */ \ +#define DBTB0 /* DMA Buffer Transfer count */ \ + /* reg. B channel 0 */ \ (*((volatile Word *) io_p2v (_DBTB0))) -#define DDAR1 /* DMA Device Address Reg. */ \ - /* channel 1 */ \ +#define DDAR1 /* DMA Device Address Reg. */ \ + /* channel 1 */ \ (*((volatile Word *) io_p2v (_DDAR1))) -#define SetDCSR1 /* Set DMA Control & Status Reg. */ \ - /* channel 1 (write) */ \ +#define SetDCSR1 /* Set DMA Control & Status Reg. */ \ + /* channel 1 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR1))) -#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ - /* channel 1 (write) */ \ +#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ + /* channel 1 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR1))) -#define RdDCSR1 /* Read DMA Control & Status Reg. */ \ - /* channel 1 (read) */ \ +#define RdDCSR1 /* Read DMA Control & Status Reg. */ \ + /* channel 1 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR1))) -#define DBSA1 /* DMA Buffer Start address reg. A */ \ - /* channel 1 */ \ +#define DBSA1 /* DMA Buffer Start address reg. A */ \ + /* channel 1 */ \ (*((volatile Address *) io_p2v (_DBSA1))) -#define DBTA1 /* DMA Buffer Transfer count */ \ - /* reg. A channel 1 */ \ +#define DBTA1 /* DMA Buffer Transfer count */ \ + /* reg. A channel 1 */ \ (*((volatile Word *) io_p2v (_DBTA1))) -#define DBSB1 /* DMA Buffer Start address reg. B */ \ - /* channel 1 */ \ +#define DBSB1 /* DMA Buffer Start address reg. B */ \ + /* channel 1 */ \ (*((volatile Address *) io_p2v (_DBSB1))) -#define DBTB1 /* DMA Buffer Transfer count */ \ - /* reg. B channel 1 */ \ +#define DBTB1 /* DMA Buffer Transfer count */ \ + /* reg. B channel 1 */ \ (*((volatile Word *) io_p2v (_DBTB1))) -#define DDAR2 /* DMA Device Address Reg. */ \ - /* channel 2 */ \ +#define DDAR2 /* DMA Device Address Reg. */ \ + /* channel 2 */ \ (*((volatile Word *) io_p2v (_DDAR2))) -#define SetDCSR2 /* Set DMA Control & Status Reg. */ \ - /* channel 2 (write) */ \ +#define SetDCSR2 /* Set DMA Control & Status Reg. */ \ + /* channel 2 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR2))) -#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ - /* channel 2 (write) */ \ +#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ + /* channel 2 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR2))) -#define RdDCSR2 /* Read DMA Control & Status Reg. */ \ - /* channel 2 (read) */ \ +#define RdDCSR2 /* Read DMA Control & Status Reg. */ \ + /* channel 2 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR2))) -#define DBSA2 /* DMA Buffer Start address reg. A */ \ - /* channel 2 */ \ +#define DBSA2 /* DMA Buffer Start address reg. A */ \ + /* channel 2 */ \ (*((volatile Address *) io_p2v (_DBSA2))) -#define DBTA2 /* DMA Buffer Transfer count */ \ - /* reg. A channel 2 */ \ +#define DBTA2 /* DMA Buffer Transfer count */ \ + /* reg. A channel 2 */ \ (*((volatile Word *) io_p2v (_DBTA2))) -#define DBSB2 /* DMA Buffer Start address reg. B */ \ - /* channel 2 */ \ +#define DBSB2 /* DMA Buffer Start address reg. B */ \ + /* channel 2 */ \ (*((volatile Address *) io_p2v (_DBSB2))) -#define DBTB2 /* DMA Buffer Transfer count */ \ - /* reg. B channel 2 */ \ +#define DBTB2 /* DMA Buffer Transfer count */ \ + /* reg. B channel 2 */ \ (*((volatile Word *) io_p2v (_DBTB2))) -#define DDAR3 /* DMA Device Address Reg. */ \ - /* channel 3 */ \ +#define DDAR3 /* DMA Device Address Reg. */ \ + /* channel 3 */ \ (*((volatile Word *) io_p2v (_DDAR3))) -#define SetDCSR3 /* Set DMA Control & Status Reg. */ \ - /* channel 3 (write) */ \ +#define SetDCSR3 /* Set DMA Control & Status Reg. */ \ + /* channel 3 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR3))) -#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ - /* channel 3 (write) */ \ +#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ + /* channel 3 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR3))) -#define RdDCSR3 /* Read DMA Control & Status Reg. */ \ - /* channel 3 (read) */ \ +#define RdDCSR3 /* Read DMA Control & Status Reg. */ \ + /* channel 3 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR3))) -#define DBSA3 /* DMA Buffer Start address reg. A */ \ - /* channel 3 */ \ +#define DBSA3 /* DMA Buffer Start address reg. A */ \ + /* channel 3 */ \ (*((volatile Address *) io_p2v (_DBSA3))) -#define DBTA3 /* DMA Buffer Transfer count */ \ - /* reg. A channel 3 */ \ +#define DBTA3 /* DMA Buffer Transfer count */ \ + /* reg. A channel 3 */ \ (*((volatile Word *) io_p2v (_DBTA3))) -#define DBSB3 /* DMA Buffer Start address reg. B */ \ - /* channel 3 */ \ +#define DBSB3 /* DMA Buffer Start address reg. B */ \ + /* channel 3 */ \ (*((volatile Address *) io_p2v (_DBSB3))) -#define DBTB3 /* DMA Buffer Transfer count */ \ - /* reg. B channel 3 */ \ +#define DBTB3 /* DMA Buffer Transfer count */ \ + /* reg. B channel 3 */ \ (*((volatile Word *) io_p2v (_DBTB3))) -#define DDAR4 /* DMA Device Address Reg. */ \ - /* channel 4 */ \ +#define DDAR4 /* DMA Device Address Reg. */ \ + /* channel 4 */ \ (*((volatile Word *) io_p2v (_DDAR4))) -#define SetDCSR4 /* Set DMA Control & Status Reg. */ \ - /* channel 4 (write) */ \ +#define SetDCSR4 /* Set DMA Control & Status Reg. */ \ + /* channel 4 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR4))) -#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ - /* channel 4 (write) */ \ +#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ + /* channel 4 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR4))) -#define RdDCSR4 /* Read DMA Control & Status Reg. */ \ - /* channel 4 (read) */ \ +#define RdDCSR4 /* Read DMA Control & Status Reg. */ \ + /* channel 4 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR4))) -#define DBSA4 /* DMA Buffer Start address reg. A */ \ - /* channel 4 */ \ +#define DBSA4 /* DMA Buffer Start address reg. A */ \ + /* channel 4 */ \ (*((volatile Address *) io_p2v (_DBSA4))) -#define DBTA4 /* DMA Buffer Transfer count */ \ - /* reg. A channel 4 */ \ +#define DBTA4 /* DMA Buffer Transfer count */ \ + /* reg. A channel 4 */ \ (*((volatile Word *) io_p2v (_DBTA4))) -#define DBSB4 /* DMA Buffer Start address reg. B */ \ - /* channel 4 */ \ +#define DBSB4 /* DMA Buffer Start address reg. B */ \ + /* channel 4 */ \ (*((volatile Address *) io_p2v (_DBSB4))) -#define DBTB4 /* DMA Buffer Transfer count */ \ - /* reg. B channel 4 */ \ +#define DBTB4 /* DMA Buffer Transfer count */ \ + /* reg. B channel 4 */ \ (*((volatile Word *) io_p2v (_DBTB4))) -#define DDAR5 /* DMA Device Address Reg. */ \ - /* channel 5 */ \ +#define DDAR5 /* DMA Device Address Reg. */ \ + /* channel 5 */ \ (*((volatile Word *) io_p2v (_DDAR5))) -#define SetDCSR5 /* Set DMA Control & Status Reg. */ \ - /* channel 5 (write) */ \ +#define SetDCSR5 /* Set DMA Control & Status Reg. */ \ + /* channel 5 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR5))) -#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ - /* channel 5 (write) */ \ +#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ + /* channel 5 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR5))) -#define RdDCSR5 /* Read DMA Control & Status Reg. */ \ - /* channel 5 (read) */ \ +#define RdDCSR5 /* Read DMA Control & Status Reg. */ \ + /* channel 5 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR5))) -#define DBSA5 /* DMA Buffer Start address reg. A */ \ - /* channel 5 */ \ +#define DBSA5 /* DMA Buffer Start address reg. A */ \ + /* channel 5 */ \ (*((volatile Address *) io_p2v (_DBSA5))) -#define DBTA5 /* DMA Buffer Transfer count */ \ - /* reg. A channel 5 */ \ +#define DBTA5 /* DMA Buffer Transfer count */ \ + /* reg. A channel 5 */ \ (*((volatile Word *) io_p2v (_DBTA5))) -#define DBSB5 /* DMA Buffer Start address reg. B */ \ - /* channel 5 */ \ +#define DBSB5 /* DMA Buffer Start address reg. B */ \ + /* channel 5 */ \ (*((volatile Address *) io_p2v (_DBSB5))) -#define DBTB5 /* DMA Buffer Transfer count */ \ - /* reg. B channel 5 */ \ +#define DBTB5 /* DMA Buffer Transfer count */ \ + /* reg. B channel 5 */ \ (*((volatile Word *) io_p2v (_DBTB5))) #endif /* LANGUAGE == C */ -#define DDAR_RW 0x00000001 /* device data Read/Write */ -#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ - /* (memory -> device) */ -#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ - /* (device -> memory) */ -#define DDAR_E 0x00000002 /* big/little Endian device */ -#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ -#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ -#define DDAR_BS 0x00000004 /* device Burst Size */ -#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ -#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ -#define DDAR_DW 0x00000008 /* device Data Width */ -#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ -#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ -#define DDAR_DS Fld (4, 4) /* Device Select */ -#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ +#define DDAR_RW 0x00000001 /* device data Read/Write */ +#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ + /* (memory -> device) */ +#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ + /* (device -> memory) */ +#define DDAR_E 0x00000002 /* big/little Endian device */ +#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ +#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ +#define DDAR_BS 0x00000004 /* device Burst Size */ +#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ +#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ +#define DDAR_DW 0x00000008 /* device Data Width */ +#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ +#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ +#define DDAR_DS Fld (4, 4) /* Device Select */ +#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ (0x0 << FShft (DDAR_DS)) -#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ +#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ (0x1 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ +#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ (0x2 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ +#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ (0x3 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ +#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ (0x4 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ +#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ (0x5 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ +#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ (0x6 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ +#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ (0x7 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ +#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ (0x8 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ +#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ (0x9 << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ - /* (audio) */ \ +#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ + /* (audio) */ \ (0xA << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ - /* (audio) */ \ +#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ + /* (audio) */ \ (0xB << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ - /* (telecom) */ \ +#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ + /* (telecom) */ \ (0xC << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ - /* (telecom) */ \ +#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ + /* (telecom) */ \ (0xD << FShft (DDAR_DS)) -#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ +#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ (0xE << FShft (DDAR_DS)) -#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ +#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ (0xF << FShft (DDAR_DS)) -#define DDAR_DA Fld (24, 8) /* Device Address */ -#define DDAR_DevAdd(Add) /* Device Address */ \ +#define DDAR_DA Fld (24, 8) /* Device Address */ +#define DDAR_DevAdd(Add) /* Device Address */ \ (((Add) & 0xF0000000) | \ (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) -#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ +#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR)) -#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ +#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR)) -#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ +#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR)) -#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ +#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR)) -#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ +#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR)) -#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ +#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR)) -#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ +#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR)) -#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ +#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR)) -#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ +#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR)) -#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ +#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR)) -#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ +#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR)) -#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ +#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR)) -#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ +#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0)) -#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ +#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0)) -#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ - /* (telecom) */ \ +#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ + /* (telecom) */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1)) -#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ - /* (telecom) */ \ +#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ + /* (telecom) */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1)) -#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ +#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR)) -#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ +#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR)) -#define DCSR_RUN 0x00000001 /* DMA RUNing */ -#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ -#define DCSR_ERROR 0x00000004 /* DMA ERROR */ -#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ +#define DCSR_RUN 0x00000001 /* DMA RUNing */ +#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ +#define DCSR_ERROR 0x00000004 /* DMA ERROR */ +#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ #define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ -#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ +#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ #define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ -#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ -#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ -#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ +#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ +#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ +#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ -#define DBT_TC Fld (13, 0) /* Transfer Count */ -#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ -#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ +#define DBT_TC Fld (13, 0) /* Transfer Count */ +#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ +#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ /* * Liquid Crystal Display (LCD) control registers * * Registers - * LCCR0 Liquid Crystal Display (LCD) Control Register 0 - * (read/write). - * [Bits LDM, BAM, and ERM are only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - * LCSR Liquid Crystal Display (LCD) Status Register - * (read/write). - * [Bit LDD can be only read in versions 1.0 (rev. = 1) - * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be - * read and written (cleared) in versions 2.0 (rev. = 8) - * and higher.] - * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Base Address Register channel 1 (read/write). - * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Current Address Register channel 1 (read). - * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Base Address Register channel 2 (read/write). - * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Current Address Register channel 2 (read). - * LCCR1 Liquid Crystal Display (LCD) Control Register 1 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher.] - * LCCR2 Liquid Crystal Display (LCD) Control Register 2 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher.] - * LCCR3 Liquid Crystal Display (LCD) Control Register 3 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher. Bit PCP is only - * implemented in versions 2.0 (rev. = 8) and higher of - * the StrongARM SA-1100.] + * LCCR0 Liquid Crystal Display (LCD) Control Register 0 + * (read/write). + * [Bits LDM, BAM, and ERM are only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + * LCSR Liquid Crystal Display (LCD) Status Register + * (read/write). + * [Bit LDD can be only read in versions 1.0 (rev. = 1) + * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be + * read and written (cleared) in versions 2.0 (rev. = 8) + * and higher.] + * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Base Address Register channel 1 (read/write). + * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Current Address Register channel 1 (read). + * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Base Address Register channel 2 (read/write). + * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Current Address Register channel 2 (read). + * LCCR1 Liquid Crystal Display (LCD) Control Register 1 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher.] + * LCCR2 Liquid Crystal Display (LCD) Control Register 2 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher.] + * LCCR3 Liquid Crystal Display (LCD) Control Register 3 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher. Bit PCP is only + * implemented in versions 2.0 (rev. = 8) and higher of + * the StrongARM SA-1100.] * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). * fpix, Tpix Frequency, period of the pixel clock. - * fln, Tln Frequency, period of the line clock. - * fac, Tac Frequency, period of the AC bias clock. + * fln, Tln Frequency, period of the line clock. + * fac, Tac Frequency, period of the AC bias clock. */ -#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ -#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ - /* [byte] */ \ +#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ +#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ + /* [byte] */ \ (16*LCD_PEntrySp) -#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ - /* [byte] */ \ +#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ + /* [byte] */ \ (256*LCD_PEntrySp) -#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ - /* dummy-Palette Space [byte] */ \ +#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ + /* dummy-Palette Space [byte] */ \ (16*LCD_PEntrySp) #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ -#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ -#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ -#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ +#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ +#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ +#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ (0 << FShft (LCD_PBS)) -#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ +#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ (1 << FShft (LCD_PBS)) -#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ +#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ (2 << FShft (LCD_PBS)) -#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ -#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ -#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ -#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ -#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ -#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ -#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ -#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ -#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ -#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ -#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ -#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ -#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ -#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ -#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ -#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ - /* (Alternative) */ +#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ +#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ +#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ +#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ +#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ +#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ +#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ +#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ +#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ +#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ +#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ +#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ +#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ +#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ +#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ +#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ + /* (Alternative) */ -#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ -#define _LCSR 0xB0100004 /* LCD Status Reg. */ -#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ - /* channel 1 */ -#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ - /* channel 1 */ -#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ - /* channel 2 */ -#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ - /* channel 2 */ -#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ -#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ -#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ +#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ +#define _LCSR 0xB0100004 /* LCD Status Reg. */ +#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ + /* channel 1 */ +#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ + /* channel 1 */ +#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ + /* channel 2 */ +#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ + /* channel 2 */ +#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ +#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ +#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ #if LANGUAGE == C -#define LCCR0 /* LCD Control Reg. 0 */ \ +#define LCCR0 /* LCD Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_LCCR0))) -#define LCSR /* LCD Status Reg. */ \ +#define LCSR /* LCD Status Reg. */ \ (*((volatile Word *) io_p2v (_LCSR))) -#define DBAR1 /* LCD DMA Base Address Reg. */ \ - /* channel 1 */ \ +#define DBAR1 /* LCD DMA Base Address Reg. */ \ + /* channel 1 */ \ (*((volatile Address *) io_p2v (_DBAR1))) -#define DCAR1 /* LCD DMA Current Address Reg. */ \ - /* channel 1 */ \ +#define DCAR1 /* LCD DMA Current Address Reg. */ \ + /* channel 1 */ \ (*((volatile Address *) io_p2v (_DCAR1))) -#define DBAR2 /* LCD DMA Base Address Reg. */ \ - /* channel 2 */ \ +#define DBAR2 /* LCD DMA Base Address Reg. */ \ + /* channel 2 */ \ (*((volatile Address *) io_p2v (_DBAR2))) -#define DCAR2 /* LCD DMA Current Address Reg. */ \ - /* channel 2 */ \ +#define DCAR2 /* LCD DMA Current Address Reg. */ \ + /* channel 2 */ \ (*((volatile Address *) io_p2v (_DCAR2))) -#define LCCR1 /* LCD Control Reg. 1 */ \ +#define LCCR1 /* LCD Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_LCCR1))) -#define LCCR2 /* LCD Control Reg. 2 */ \ +#define LCCR2 /* LCD Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_LCCR2))) -#define LCCR3 /* LCD Control Reg. 3 */ \ +#define LCCR3 /* LCD Control Reg. 3 */ \ (*((volatile Word *) io_p2v (_LCCR3))) #endif /* LANGUAGE == C */ -#define LCCR0_LEN 0x00000001 /* LCD ENable */ +#define LCCR0_LEN 0x00000001 /* LCD ENable */ #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ -#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ -#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ -#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ - /* Select */ -#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ -#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ -#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ - /* interrupt Mask (disable) */ -#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ - /* interrupt Mask (disable) */ +#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ +#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ +#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ + /* Select */ +#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ +#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ +#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ + /* interrupt Mask (disable) */ +#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ + /* interrupt Mask (disable) */ #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ /* IUU, OOL, OUL, OOU, and OUU) */ - /* interrupt Mask (disable) */ + /* interrupt Mask (disable) */ #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ -#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ -#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ -#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ -#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ -#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ +#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ +#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ +#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ +#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ +#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ - /* display mode) */ -#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ - /* display */ -#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ - /* display */ -#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ - /* [Tmem] */ -#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ - /* [0..510 Tcpu] */ \ + /* display mode) */ +#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ + /* display */ +#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ + /* display */ +#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ + /* [Tmem] */ +#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ + /* [0..510 Tcpu] */ \ ((Tcpu)/2 << FShft (LCCR0_PDD)) -#define LCSR_LDD 0x00000001 /* LCD Disable Done */ -#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ -#define LCSR_BER 0x00000004 /* Bus ERror */ -#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ -#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ - /* panel */ -#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ - /* panel */ -#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ - /* panel */ -#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ - /* panel */ -#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ - /* panel */ -#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ - /* panel */ -#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ - /* panel */ -#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ - /* panel */ +#define LCSR_LDD 0x00000001 /* LCD Disable Done */ +#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ +#define LCSR_BER 0x00000004 /* Bus ERror */ +#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ +#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ + /* panel */ +#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ + /* panel */ +#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ + /* panel */ +#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ + /* panel */ +#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ + /* panel */ +#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ + /* panel */ +#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ + /* panel */ +#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ + /* panel */ -#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ +#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ +#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ +#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ /* pulse Width - 2 [Tpix] (L_LCLK) */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [2..65 Tpix] */ \ +#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ + /* pulse Width [2..65 Tpix] */ \ (((Tpix) - 2) << FShft (LCCR1_HSW)) #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ + /* count - 1 [Tpix] */ +#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ + /* [1..256 Tpix] */ \ (((Tpix) - 1) << FShft (LCCR1_ELW)) #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ + /* Wait count - 1 [Tpix] */ +#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ + /* [1..256 Tpix] */ \ (((Tpix) - 1) << FShft (LCCR1_BLW)) -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ +#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ +#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ (((Line) - 1) << FShft (LCCR2_LPP)) #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ + /* Width - 1 [Tln] (L_FCLK) */ +#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ + /* Width [1..64 Tln] */ \ (((Tln) - 1) << FShft (LCCR2_VSW)) #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ + /* count [Tln] */ +#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ + /* [0..255 Tln] */ \ ((Tln) << FShft (LCCR2_EFW)) #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ + /* Wait count [Tln] */ +#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ + /* [0..255 Tln] */ \ ((Tln) << FShft (LCCR2_BFW)) -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ - /* [1..255] (L_PCLK) */ - /* fpix = fcpu/(2*(PCD + 2)) */ - /* Tpix = 2*(PCD + 2)*Tcpu */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ +#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ + /* [1..255] (L_PCLK) */ + /* fpix = fcpu/(2*(PCD + 2)) */ + /* Tpix = 2*(PCD + 2)*Tcpu */ +#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ (((Div) - 4)/2 << FShft (LCCR3_PCD)) /* fpix = fcpu/(2*Floor (Div/2)) */ /* Tpix = 2*Floor (Div/2)*Tcpu */ #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ (((Div) - 3)/2 << FShft (LCCR3_PCD)) /* fpix = fcpu/(2*Ceil (Div/2)) */ - /* Tpix = 2*Ceil (Div/2)*Tcpu */ + /* Tpix = 2*Ceil (Div/2)*Tcpu */ #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ - /* [Tln] (L_BIAS) */ -#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ + /* [Tln] (L_BIAS) */ +#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ (((Div) - 2)/2 << FShft (LCCR3_ACB)) /* fac = fln/(2*Floor (Div/2)) */ - /* Tac = 2*Floor (Div/2)*Tln */ -#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ + /* Tac = 2*Floor (Div/2)*Tln */ +#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ (((Div) - 1)/2 << FShft (LCCR3_ACB)) - /* fac = fln/(2*Ceil (Div/2)) */ - /* Tac = 2*Ceil (Div/2)*Tln */ -#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ - /* Interrupt */ -#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ - /* Off */ \ + /* fac = fln/(2*Ceil (Div/2)) */ + /* Tac = 2*Ceil (Div/2)*Tln */ +#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ + /* Interrupt */ +#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ + /* Off */ \ (0 << FShft (LCCR3_API)) -#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ - /* [1..15] */ \ +#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ + /* [1..15] */ \ ((Trans) << FShft (LCCR3_API)) #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ - /* Polarity (L_FCLK) */ + /* Polarity (L_FCLK) */ #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ + /* active High */ #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ -#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ - /* pulse Polarity (L_LCLK) */ -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - /* pulse active Low */ + /* active Low */ +#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ + /* pulse Polarity (L_LCLK) */ +#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ + /* pulse active High */ +#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ + /* pulse active Low */ #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ -#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ -#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ +#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ +#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ - /* active display mode) */ -#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ -#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ + /* active display mode) */ +#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ +#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ #undef C diff --git a/include/_exports.h b/include/_exports.h index af43885c5..61dcaaf33 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -12,15 +12,7 @@ EXPORT_FUNC(udelay) EXPORT_FUNC(get_timer) EXPORT_FUNC(vprintf) EXPORT_FUNC(do_reset) -EXPORT_FUNC(getenv) -EXPORT_FUNC(setenv) -#ifdef CONFIG_HAS_UID -EXPORT_FUNC(forceenv) -#endif -EXPORT_FUNC(simple_strtoul) -EXPORT_FUNC(simple_strtol) -EXPORT_FUNC(strcmp) -#if defined(CONFIG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) EXPORT_FUNC(i2c_write) EXPORT_FUNC(i2c_read) -#endif +#endif /* CFG_CMD_I2C */ diff --git a/include/altera.h b/include/altera.h index c03fe87c4..74b6729f9 100644 --- a/include/altera.h +++ b/include/altera.h @@ -27,21 +27,20 @@ #ifndef _ALTERA_H_ #define _ALTERA_H_ +/* + * See include/xilinx.h for another working example. + */ + /* Altera Model definitions *********************************************************************/ #define CFG_ACEX1K CFG_FPGA_DEV( 0x1 ) -#define CFG_CYCLON2 CFG_FPGA_DEV( 0x2 ) -#define CFG_STRATIX_II CFG_FPGA_DEV( 0x4 ) #define CFG_ALTERA_ACEX1K (CFG_FPGA_ALTERA | CFG_ACEX1K) -#define CFG_ALTERA_CYCLON2 (CFG_FPGA_ALTERA | CFG_CYCLON2) -#define CFG_ALTERA_STRATIX_II (CFG_FPGA_ALTERA | CFG_STRATIX_II) /* Add new models here */ /* Altera Interface definitions *********************************************************************/ #define CFG_ALTERA_IF_PS CFG_FPGA_IF( 0x1 ) /* passive serial */ -#define CFG_ALTERA_IF_FPP CFG_FPGA_IF( 0x2 ) /* fast passive parallel */ /* Add new interfaces here */ typedef enum { /* typedef Altera_iface */ @@ -51,16 +50,12 @@ typedef enum { /* typedef Altera_iface */ passive_parallel_asynchronous, /* parallel data */ passive_serial_asynchronous, /* serial data w/ internal clock (not used) */ altera_jtag_mode, /* jtag/tap serial (not used ) */ - fast_passive_parallel, /* fast passive parallel (FPP) */ - fast_passive_parallel_security, /* fast passive parallel with security (FPPS) */ max_altera_iface_type /* insert all new types before this */ } Altera_iface; /* end, typedef Altera_iface */ typedef enum { /* typedef Altera_Family */ min_altera_type, /* insert all new types after this */ Altera_ACEX1K, /* ACEX1K Family */ - Altera_CYC2, /* CYCLONII Family */ - Altera_StratixII, /* StratixII Familiy */ /* Add new models here */ max_altera_type /* insert all new types before this */ } Altera_Family; /* end, typedef Altera_Family */ @@ -89,19 +84,7 @@ typedef int (*Altera_status_fn)( int cookie ); typedef int (*Altera_done_fn)( int cookie ); typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); -typedef int (*Altera_write_fn)(void *buf, size_t len, int flush, int cookie); typedef int (*Altera_abort_fn)( int cookie ); typedef int (*Altera_post_fn)( int cookie ); -typedef struct { - Altera_pre_fn pre; - Altera_config_fn config; - Altera_status_fn status; - Altera_done_fn done; - Altera_clk_fn clk; - Altera_data_fn data; - Altera_abort_fn abort; - Altera_post_fn post; -} altera_board_specific_func; - #endif /* _ALTERA_H_ */ diff --git a/include/arm925t.h b/include/arm925t.h index 3d767b35c..ab343eaac 100644 --- a/include/arm925t.h +++ b/include/arm925t.h @@ -6,6 +6,10 @@ #ifndef __ARM925T_H__ #define __ARM925T_H__ +void gpioreserve(ushort mask); +void gpiosetdir(ushort mask, ushort in); +void gpiosetout(ushort mask, ushort out); +void gpioinit(void); void archflashwp(void *archdata, int wp); #endif /*__ARM925T_H__*/ diff --git a/include/armcoremodule.h b/include/armcoremodule.h index f1ded85fc..7dac6f8c9 100644 --- a/include/armcoremodule.h +++ b/include/armcoremodule.h @@ -28,20 +28,20 @@ #ifndef __ARMCOREMODULE_H #define __ARMCOREMODULE_H -#define CM_BASE 0x10000000 +#define CM_BASE 0x10000000 /* CM registers common to all CMs */ /* Note that observed values after reboot into the ARM Boot Monitor have been used as defaults, rather than the POR values */ -#define OS_CTRL 0x0000000C +#define OS_CTRL 0x0000000C #define CMMASK_REMAP 0x00000005 /* set remap & led */ #define CMMASK_RESET 0x00000008 -#define OS_LOCK 0x00000014 -#define CMVAL_LOCK1 0x0000A000 /* locking value */ +#define OS_LOCK 0x00000014 +#define CMVAL_LOCK1 0x0000A000 /* locking value */ #define CMVAL_LOCK2 0x0000005F /* locking value */ #define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */ #define OS_SDRAM 0x00000020 -#define OS_INIT 0x00000024 +#define OS_INIT 0x00000024 #define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ #define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ #define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */ diff --git a/include/asm-arm/arch-arm1136/bits.h b/include/asm-arm/arch-arm1136/bits.h new file mode 100644 index 000000000..8522335bf --- /dev/null +++ b/include/asm-arm/arch-arm1136/bits.h @@ -0,0 +1,48 @@ +/* bits.h + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif diff --git a/include/asm-arm/arch-arm1136/clocks.h b/include/asm-arm/arch-arm1136/clocks.h new file mode 100644 index 000000000..8e00d2e3e --- /dev/null +++ b/include/asm-arm/arch-arm1136/clocks.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_CLOCKS_H_ +#define _OMAP24XX_CLOCKS_H_ + +#define COMMIT_DIVIDERS 0x1 +#define MODE_BYPASS_FAST 0x2 +#define APLL_LOCK 0xc +#define DPLL_LOCK 0x3 /* DPLL lock */ +#define LDELAY 12000000 + +#if defined(CONFIG_OMAP242X) +#include +#elif defined(CONFIG_OMAP243X) +#include +#endif + +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#endif + + + + + + + + diff --git a/include/asm-arm/arch-arm1136/clocks242x.h b/include/asm-arm/arch-arm1136/clocks242x.h new file mode 100644 index 000000000..0ae1c4ea4 --- /dev/null +++ b/include/asm-arm/arch-arm1136/clocks242x.h @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP242X_CLOCKS_H_ +#define _OMAP242X_CLOCKS_H_ + +/****************************************************************************; +; PRCM Scheme I +; +; Enable clocks and DPLL for: +; DPLL=330, DPLLout=660 M=1,N=55 CM_CLKSEL1_PLL[21:8] 12/2*55 +; Core=660 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=330 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DSPF=220 (dsp domain) 3 CM_CLKSEL_DSP[4:0] +; DSPI=110 6 CM_CLKSEL_DSP[6:5] +; DSP_S activated CM_CLKSEL_DSP[7] +; IVAF=165 (dsp domain) 4 CM_CLKSEL_DSP[12:8] +; IVAF=82.5 auto +; IVAI auto +; IVA_MPU auto +; IVA_S bypass CM_CLKSEL_DSP[13] +; GFXF=82.5 (gfx domain) 8 CM_CLKSEL_FGX[2:0] +; SSI_SSRF=220 3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=110 auto +; L3=165Mhz (sdram) 4 CM_CLKSEL1_CORE[4:0] +; L4=82.5Mhz 8 +; C_L4_USB=41.25 16 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define I_DPLL_OUT_X2 0x2 /* x2 core out */ +#define I_MPU_DIV 0x2 /* mpu = core/2 */ +#define I_DSP_DIV 0x3c3 /* dsp & iva divider */ +#define I_GFX_DIV 0x2 +#define I_BUS_DIV 0x04601044 +#ifdef INPUT_CLK_13MHZ +#define I_DPLL_330 0x0114AC00 /* 13MHz */ +#else +#define I_DPLL_330 0x01837100 /* 12MHz */ +#endif + +/****************************************************************************; +; PRCM Scheme II +; +; Enable clocks and DPLL for: +; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 +; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] +; DSPI=100 6 CM_CLKSEL_DSP[6:5] +; DSP_S bypass CM_CLKSEL_DSP[7] +; IVAF=200 (dsp domain) 3 CM_CLKSEL_DSP[12:8] +; IVAF=100 auto +; IVAI auto +; IVA_MPU auto +; IVA_S bypass CM_CLKSEL_DSP[13] +; GFXF=50 (gfx domain) 12 CM_CLKSEL_FGX[2:0] +; SSI_SSRF=200 3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=100 auto +; L3=100Mhz (sdram) 6 CM_CLKSEL1_CORE[4:0] +; L4=100Mhz 6 +; C_L4_USB=50 12 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define II_DPLL_OUT_X2 0x2 /* x2 core out */ +#define II_MPU_DIV 0x2 /* mpu = core/2 */ +#define II_DSP_DIV 0x343 /* dsp & iva divider */ +#define II_GFX_DIV 0x2 +#define II_BUS_DIV 0x04601026 +#ifdef INPUT_CLK_13MHZ +#define II_DPLL_300 0x0112CC00 /* 13MHz */ +#else +#define II_DPLL_300 0x01832100 /* 12MHz */ +#endif + +/****************************************************************************; +; PRCM Scheme III +; +; Enable clocks and DPLL for: +; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 +; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] +; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] +; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] +; DSP_S ACTIVATED CM_CLKSEL_DSP[7] +; IVAF=88.67 (dsp domain) /3 CM_CLKSEL_DSP[12:8] +; IVAF=88.67 auto +; IVAI auto +; IVA_MPU auto +; IVA_S ACTIVATED CM_CLKSEL_DSP[13] +; GFXF=66.5 (gfx domain) /8 CM_CLKSEL_FGX[2:0]: +; SSI_SSRF=177.3 /3 CM_CLKSEL1_CORE[24:20] +; SSI_SSTF=88.67 auto +; L3=133Mhz (sdram) /4 CM_CLKSEL1_CORE[4:0] +; L4=66.5Mhz /8 +; C_L4_USB=33.25 /16 CM_CLKSEL1_CORE[6:5] +***************************************************************************/ +#define III_DPLL_OUT_X2 0x2 /* x2 core out */ +#define III_MPU_DIV 0x2 /* mpu = core/2 */ +#define III_DSP_DIV 0x23C3 /* dsp & iva divider sych enabled*/ +#define III_GFX_DIV 0x2 +#define III_BUS_DIV 0x08301044 +#ifdef INPUT_CLK_13MHZ +#define III_DPLL_266 0x0110AC00 /* 13MHz */ +#else +#define III_DPLL_266 0x01885500 /* 12MHz */ +#endif + +/* set defaults for boot up */ +#ifdef PRCM_CONFIG_I +# define DPLL_OUT I_DPLL_OUT_X2 +# define MPU_DIV I_MPU_DIV +# define DSP_DIV I_DSP_DIV +# define GFX_DIV I_GFX_DIV +# define BUS_DIV I_BUS_DIV +# define DPLL_VAL I_DPLL_266 +#elif PRCM_CONFIG_II +# define DPLL_OUT II_DPLL_OUT_X2 +# define MPU_DIV II_MPU_DIV +# define DSP_DIV II_DSP_DIV +# define GFX_DIV II_GFX_DIV +# define BUS_DIV II_BUS_DIV +# define DPLL_VAL II_DPLL_300 +#elif PRCM_CONFIG_III +# define DPLL_OUT III_DPLL_OUT_X2 +# define MPU_DIV III_MPU_DIV +# define DSP_DIV III_DSP_DIV +# define GFX_DIV III_GFX_DIV +# define BUS_DIV III_BUS_DIV +# define DPLL_VAL III_DPLL_266 +#endif + +#endif diff --git a/include/asm-arm/arch-arm1136/clocks243x.h b/include/asm-arm/arch-arm1136/clocks243x.h new file mode 100644 index 000000000..18d2e4677 --- /dev/null +++ b/include/asm-arm/arch-arm1136/clocks243x.h @@ -0,0 +1,223 @@ +/* + * (C) Copyright 2005 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP243X_CLOCKS_H_ +#define _OMAP243X_CLOCKS_H_ + +/* cm_clksel core fields not ratio governed */ +#define RX_CLKSEL_DSS1 (0x10 << 8) +#define RX_CLKSEL_DSS2 (0x0 << 13) +#define RX_CLKSEL_SSI (0x5 << 20) + +/* 2430 Ratio's */ +/* 2430-Ratio Config 1 */ +#define R1_CLKSEL_L3 (4 << 0) +#define R1_CLKSEL_L4 (2 << 5) +#define R1_CLKSEL_USB (4 << 25) +#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ + | RX_CLKSEL_DSS1 | R1_CLKSEL_L4 | R1_CLKSEL_L3 +#define R1_CLKSEL_MPU (2 << 0) +#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU +#define R1_CLKSEL_DSP (2 << 0) +#define R1_CLKSEL_DSP_IF (2 << 5) +#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF +#define R1_CLKSEL_GFX (2 << 0) +#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX +#define R1_CLKSEL_MDM (4 << 0) +#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM + +/* 2430-Ratio Config 2 */ +#define R2_CLKSEL_L3 (6 << 0) +#define R2_CLKSEL_L4 (2 << 5) +#define R2_CLKSEL_USB (2 << 25) +#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ + | RX_CLKSEL_DSS1 | R2_CLKSEL_L4 | R2_CLKSEL_L3 +#define R2_CLKSEL_MPU (2 << 0) +#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU +#define R2_CLKSEL_DSP (2 << 0) +#define R2_CLKSEL_DSP_IF (3 << 5) +#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF +#define R2_CLKSEL_GFX (2 << 0) +#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX +#define R2_CLKSEL_MDM (6 << 0) +#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM + +/* 2430-Ratio Boot */ +#define RB_CLKSEL_L3 (1 << 0) +#define RB_CLKSEL_L4 (1 << 5) +#define RB_CLKSEL_USB (1 << 25) +#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | RX_CLKSEL_DSS2 \ + | RX_CLKSEL_DSS1 | RB_CLKSEL_L4 | RB_CLKSEL_L3 +#define RB_CLKSEL_MPU (1 << 0) +#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU +#define RB_CLKSEL_DSP (1 << 0) +#define RB_CLKSEL_DSP_IF (1 << 5) +#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF +#define RB_CLKSEL_GFX (1 << 0) +#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX +#define RB_CLKSEL_MDM (1 << 0) +#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM + +/* 2430 Target modes: Along with each configuration the CPU has several modes + * which goes along with them. Modes mainly are the addition of descrite DPLL + * combinations to go along with a ratio. + */ +/* hardware goverend */ +#define MX_48M_SRC (0 << 3) +#define MX_54M_SRC (0 << 5) +#define MX_APLLS_CLIKIN_12 (3 << 23) +#define MX_APLLS_CLIKIN_13 (2 << 23) +#define MX_APLLS_CLIKIN_19_2 (0 << 23) + +/* 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed */ + +/* boot (boot) */ +#define MB_DPLL_MULT (1 << 12) +#define MB_DPLL_DIV (0 << 8) +#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ + | MB_DPLL_MULT | MX_APLLS_CLIKIN_12 + +#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ + | MB_DPLL_MULT | MX_APLLS_CLIKIN_13 + +#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV \ + | MB_DPLL_MULT | MX_APLLS_CLIKIN_19 + +/* #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz */ + +#define M2_DPLL_MULT_12 (55 << 12) +#define M2_DPLL_DIV_12 (1 << 8) +#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_12 \ + | M2_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 +/* Use 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2, relock time issue */ +#define M2_DPLL_MULT_13 (330 << 12) +#define M2_DPLL_DIV_13 (12 << 8) +#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_13 \ + | M2_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 +#define M2_DPLL_MULT_19 (275 << 12) +#define M2_DPLL_DIV_19 (15 << 8) +#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M2_DPLL_DIV_19 \ + | M2_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 + +/* #3 (ratio2) DPLL = 330*2 = 660MHz, L3=110MHz */ +#define M3_DPLL_MULT_12 (55 << 12) +#define M3_DPLL_DIV_12 (1 << 8) +#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_12 \ + | M3_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 +#define M3_DPLL_MULT_13 (330 << 12) +#define M3_DPLL_DIV_13 (12 << 8) +#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_13 \ + | M3_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 +#define M3_DPLL_MULT_19 (275 << 12) +#define M3_DPLL_DIV_19 (15 << 8) +#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M3_DPLL_DIV_19 \ + | M3_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 + +/* #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz*/ +#define M4_DPLL_MULT_12 (133 << 12) +#define M4_DPLL_DIV_12 (3 << 8) +#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_12 \ + | M4_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 +#define M4_DPLL_MULT_13 (399 << 12) +#define M4_DPLL_DIV_13 (12 << 8) +#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_13 \ + | M4_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 +#define M4_DPLL_MULT_19 (145 << 12) +#define M4_DPLL_DIV_19 (6 << 8) +#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M4_DPLL_DIV_19 \ + | M4_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 + +/* #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz, L3=133MHz */ +#define M5A_DPLL_MULT_12 (133 << 12) +#define M5A_DPLL_DIV_12 (5 << 8) +#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_12 \ + | M5A_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 +#define M5A_DPLL_MULT_13 (266 << 12) +#define M5A_DPLL_DIV_13 (12 << 8) +#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_13 \ + | M5A_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 +#define M5A_DPLL_MULT_19 (180 << 12) +#define M5A_DPLL_DIV_19 (12 << 8) +#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M5A_DPLL_DIV_19 \ + | M5A_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 + +/* #5b (ratio1) target DPLL = 200*2 = 400MHz, L3=100MHz */ +#define M5B_DPLL_MULT_12 (50 << 12) +#define M5B_DPLL_DIV_12 (2 << 8) +#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_12 \ + | M5B_DPLL_MULT_12 | MX_APLLS_CLIKIN_12 +#define M5B_DPLL_MULT_13 (200 << 12) +#define M5B_DPLL_DIV_13 (12 << 8) + +#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_13 \ + | M5B_DPLL_MULT_13 | MX_APLLS_CLIKIN_13 +#define M5B_DPLL_MULT_19 (125 << 12) +#define M5B_DPLL_DIV_19 (31 << 8) +#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | M5B_DPLL_DIV_19 \ + | M5B_DPLL_MULT_19 | MX_APLLS_CLIKIN_19_2 + +/* 2430 - chassis (sedna) */ + /* 165 (ratio1) same as above #2 */ + /* 150 (ratio1)*/ + /* 133 (ratio2) same as above #4 */ + /* 110 (ratio2) same as above #3*/ + /* 104 (ratio2)*/ + /* boot (boot) */ + +/* high and low operation value */ +#define MX_CLKSEL2_PLL_2x_VAL (2 << 0) +#define MX_CLKSEL2_PLL_1x_VAL (1 << 0) + +/* set defaults for boot up */ +#if defined(PRCM_CONFIG_2) /* ARM-330MHz IVA2-330MHz L3-165MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R1_CLKSEL_MPU +# define DSP_DIV R1_CM_CLKSEL_DSP_VAL +# define GFX_DIV R1_CM_CLKSEL_GFX_VAL +# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M2_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R2_CM_CLKSEL_MDM_VAL +#elif defined(PRCM_CONFIG_3) /* ARM-330MHz IVA2-330MHz L3-110MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R2_CLKSEL_MPU +# define DSP_DIV R2_CM_CLKSEL_DSP_VAL +# define GFX_DIV R2_CM_CLKSEL_GFX_VAL +# define BUS_DIV R2_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M3_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R2_CM_CLKSEL_MDM_VAL +#elif defined(PRCM_CONFIG_5A) /* ARM-266MHz IVA2-266MHz L3-133MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R1_CLKSEL_MPU +# define DSP_DIV R1_CM_CLKSEL_DSP_VAL +# define GFX_DIV R1_CM_CLKSEL_GFX_VAL +# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M5A_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R2_CM_CLKSEL_MDM_VAL +#elif defined(PRCM_CONFIG_5B) /* ARM-200MHz IVA2-200MHz L3-100MHz */ +# define DPLL_OUT MX_CLKSEL2_PLL_2x_VAL +# define MPU_DIV R1_CLKSEL_MPU +# define DSP_DIV R1_CM_CLKSEL_DSP_VAL +# define GFX_DIV R1_CM_CLKSEL_GFX_VAL +# define BUS_DIV R1_CM_CLKSEL1_CORE_VAL +# define DPLL_VAL M5B_CM_CLKSEL1_PLL_13_VAL +# define MDM_DIV R1_CM_CLKSEL_MDM_VAL +#endif + +#endif diff --git a/include/asm-arm/arch-arm1136/cpu.h b/include/asm-arm/arch-arm1136/cpu.h new file mode 100644 index 000000000..ff17cbccb --- /dev/null +++ b/include/asm-arm/arch-arm1136/cpu.h @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2005 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _OMAP24XX_CPU_H +#define _OMAP24XX_CPU_H +/* CPU Specific Headers */ +#ifdef CONFIG_OMAP242X +#include +#endif +#ifdef CONFIG_OMAP243X +#include +#endif + +/* Register offsets of common modules */ +/* Control */ +#define CONTROL_STATUS (OMAP24XX_CTRL_BASE + 0x2F8) +#define OMAP24XX_MCR (OMAP24XX_CTRL_BASE + 0x8C) + +/* Tap Information */ +#define TAP_IDCODE_REG (OMAP24XX_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP24XX_TAP_BASE+0x208) + +/* device type */ +#define DEVICE_MASK (BIT8|BIT9|BIT10) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* GPMC CS3/cs4/cs6 not avaliable */ +#define GPMC_SYSCONFIG (OMAP24XX_GPMC_BASE+0x10) +#define GPMC_IRQENABLE (OMAP24XX_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP24XX_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP24XX_GPMC_BASE+0x50) + +#define GPMC_CONFIG_CS0 (OMAP24XX_GPMC_BASE+0x60) +#define GPMC_CONFIG_WIDTH (0x30) + +#define GPMC_CONFIG1 (0x00) +#define GPMC_CONFIG2 (0x04) +#define GPMC_CONFIG3 (0x08) +#define GPMC_CONFIG4 (0x0C) +#define GPMC_CONFIG5 (0x10) +#define GPMC_CONFIG6 (0x14) +#define GPMC_CONFIG7 (0x18) +#define GPMC_NAND_CMD (0x1C) +#define GPMC_NAND_ADR (0x20) +#define GPMC_NAND_DAT (0x24) + +/* GPMC Mapping */ +# define FLASH_BASE 0x04000000 /* NOR flash (64 Meg aligned) */ +# define DEBUG_BASE 0x08000000 /* debug board */ +# define NAND_BASE 0x0C000000 /* NAND flash */ +# define SIBLEY_MAP1 0x10000000 /* Sibley1 flash */ +# define SIBLEY_MAP2 0x14000000 /* Sibley2 flash */ +# define PCMCIA_BASE 0x18000000 /* PCMCIA region */ +# define ONENAND_MAP 0x20000000 /* OneNand flash */ + +/* SMS */ +#define SMS_SYSCONFIG (OMAP24XX_SMS_BASE+0x10) +#define SMS_CLASS_ARB0 (OMAP24XX_SMS_BASE+0xD0) +#define BURSTCOMPLETE_GROUP7 BIT31 + +/* SDRC */ +#define SDRC_SYSCONFIG (OMAP24XX_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP24XX_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP24XX_SDRC_BASE+0x40) +#define SDRC_SHARING (OMAP24XX_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP24XX_SDRC_BASE+0x60) +#define SDRC_DLLA_STATUS (OMAP24XX_SDRC_BASE+0x64) +#define SDRC_DLLB_CTRL (OMAP24XX_SDRC_BASE+0x68) +#define SDRC_DLLB_STATUS (OMAP24XX_SDRC_BASE+0x6C) +#define DLLPHASE BIT1 +#define LOADDLL BIT2 +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK (BIT8|BIT9) + +#define SDRC_POWER (OMAP24XX_SDRC_BASE+0x70) +#define SDRC_MCFG_0 (OMAP24XX_SDRC_BASE+0x80) +#define SDRC_MR_0 (OMAP24XX_SDRC_BASE+0x84) +#define SDRC_ACTIM_CTRLA_0 (OMAP24XX_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLB_0 (OMAP24XX_SDRC_BASE+0xA0) +#define SDRC_ACTIM_CTRLA_1 (OMAP24XX_SDRC_BASE+0xC4) +#define SDRC_ACTIM_CTRLB_1 (OMAP24XX_SDRC_BASE+0xC8) +#define SDRC_RFR_CTRL (OMAP24XX_SDRC_BASE+0xA4) +#define SDRC_MANUAL_0 (OMAP24XX_SDRC_BASE+0xA8) +#define OMAP24XX_SDRC_CS0 0x80000000 +#define OMAP24XX_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ + +/* Watchdog */ +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define PRCM_CLKSRC_CTRL (OMAP24XX_CM_BASE+0x060) +#define PRCM_CLKOUT_CTRL (OMAP24XX_CM_BASE+0x070) +#define PRCM_CLKEMUL_CTRL (OMAP24XX_CM_BASE+0x078) +#define PRCM_CLKCFG_CTRL (OMAP24XX_CM_BASE+0x080) +#define PRCM_CLKCFG_STATUS (OMAP24XX_CM_BASE+0x084) +#define CM_CLKSEL_MPU (OMAP24XX_CM_BASE+0x140) +#define RM_RSTST_MPU (OMAP24XX_CM_BASE+0x158) +#define CM_FCLKEN1_CORE (OMAP24XX_CM_BASE+0x200) +#define CM_FCLKEN2_CORE (OMAP24XX_CM_BASE+0x204) +#define CM_ICLKEN1_CORE (OMAP24XX_CM_BASE+0x210) +#define CM_ICLKEN2_CORE (OMAP24XX_CM_BASE+0x214) +#define CM_CLKSEL1_CORE (OMAP24XX_CM_BASE+0x240) +#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440) +#define CM_CLKSEL2_CORE (OMAP24XX_CM_BASE+0x244) +#define CM_FCLKEN_GFX (OMAP24XX_CM_BASE+0x300) +#define CM_ICLKEN_GFX (OMAP24XX_CM_BASE+0x310) +#define CM_CLKSEL_GFX (OMAP24XX_CM_BASE+0x340) +#define RM_RSTCTRL_GFX (OMAP24XX_CM_BASE+0x350) +#define CM_FCLKEN_WKUP (OMAP24XX_CM_BASE+0x400) +#define CM_ICLKEN_WKUP (OMAP24XX_CM_BASE+0x410) +#define CM_CLKSEL_WKUP (OMAP24XX_CM_BASE+0x440) +#define PM_RSTCTRL_WKUP (OMAP24XX_CM_BASE+0x450) +#define CM_CLKEN_PLL (OMAP24XX_CM_BASE+0x500) +#define CM_IDLEST_CKGEN (OMAP24XX_CM_BASE+0x520) +#define CM_CLKSEL1_PLL (OMAP24XX_CM_BASE+0x540) +#define CM_CLKSEL2_PLL (OMAP24XX_CM_BASE+0x544) +#define CM_CLKSEL_DSP (OMAP24XX_CM_BASE+0x840) +#define CM_CLKSEL_MDM (OMAP24XX_CM_BASE+0xC40) + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) + +/* IVA2 */ +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +/* I2C base */ +#define I2C_BASE1 (OMAP24XX_L4_IO_BASE + 0x70000) +#define I2C_BASE2 (OMAP24XX_L4_IO_BASE + 0x72000) + +#endif diff --git a/include/asm-arm/arch-arm1136/i2c.h b/include/asm-arm/arch-arm1136/i2c.h new file mode 100644 index 000000000..a71bd7d2e --- /dev/null +++ b/include/asm-arm/arch-arm1136/i2c.h @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_I2C_H_ +#define _OMAP24XX_I2C_H_ + +/* Get the i2c base addresses */ +#include + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#define I2C_REV (0x00) +#define I2C_IE (0x04) +#define I2C_STAT (0x08) +#define I2C_IV (0x0c) +#define I2C_BUF (0x14) +#define I2C_CNT (0x18) +#define I2C_DATA (0x1c) +#define I2C_SYSC (0x20) +#define I2C_CON (0x24) +#define I2C_OA (0x28) +#define I2C_SA (0x2c) +#define I2C_PSC (0x30) +#define I2C_SCLL (0x34) +#define I2C_SCLH (0x38) +#define I2C_SYSTEST (0x3c) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_GC_IE (1 << 5) +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_GC (1 << 5) +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ + +/* I2C Buffer Configuration Register (I2C_BUF): */ + +#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ + +/* I2C System Test Register (I2C_SYSTEST): */ + +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ +#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ + +#define I2C_SCLL_SCLL (0) +#define I2C_SCLL_SCLL_M (0xFF) +#define I2C_SCLL_HSSCLL (8) +#define I2C_SCLH_HSSCLL_M (0xFF) +#define I2C_SCLH_SCLH (0) +#define I2C_SCLH_SCLH_M (0xFF) +#define I2C_SCLH_HSSCLH (8) +#define I2C_SCLH_HSSCLH_M (0xFF) + +#define OMAP_I2C_STANDARD 100 +#define OMAP_I2C_FAST_MODE 400 +#define OMAP_I2C_HIGH_SPEED 3400 + +#define SYSTEM_CLOCK_12 12000 +#define SYSTEM_CLOCK_13 13000 +#define SYSTEM_CLOCK_192 19200 +#define SYSTEM_CLOCK_96 96000 + +#ifdef CONFIG_OMAP243X +#define I2C_IP_CLK SYSTEM_CLOCK_96 +#define I2C_PSC_MAX (0x0f) +#define I2C_PSC_MIN (0x00) +#else +/* 242x */ +#ifdef INPUT_CLK_13MHZ +#define I2C_IP_CLK SYSTEM_CLOCK_13 +#else +#define I2C_IP_CLK SYSTEM_CLOCK_12 +#endif +#define I2C_PSC_MAX (0xff) +#define I2C_PSC_MIN (0x00) +#endif + +#endif diff --git a/include/asm-arm/arch-arm1136/mem.h b/include/asm-arm/arch-arm1136/mem.h new file mode 100644 index 000000000..2a3da7360 --- /dev/null +++ b/include/asm-arm/arch-arm1136/mem.h @@ -0,0 +1,383 @@ + +/* + * (C) Copyright 2004-2005 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP24XX_MEM_H_ +#define _OMAP24XX_MEM_H_ + +#define SDRC_CS0_OSET 0x0 +#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ + +#ifndef __ASSEMBLY__ +/* struct's for holding data tables for current boards, they are getting used + early in init when NO global access are there */ +struct sdrc_data_s { + u32 sdrc_sharing; + u32 sdrc_mdcfg_0_ddr; + u32 sdrc_mdcfg_0_sdr; + u32 sdrc_actim_ctrla_0; + u32 sdrc_actim_ctrlb_0; + u32 sdrc_rfr_ctrl; + u32 sdrc_mr_0_ddr; + u32 sdrc_mr_0_sdr; + u32 sdrc_dllab_ctrl; +} /*__attribute__ ((packed))*/; +typedef struct sdrc_data_s sdrc_data_t; + +typedef enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR = 3, +} mem_t; + +#endif + +/* set the 243x-SDRC incoming address convention */ +#if defined(SDRC_B_R_C) +#define B_ALL (0 << 6) /* bank-row-column */ +#elif defined(SDRC_B1_R_B0_C) +#define B_ALL (1 << 6) /* bank1-row-bank0-column */ +#elif defined(SDRC_R_B_C) +#define B_ALL (2 << 6) /* row-bank-column */ +#endif + +/* Slower full frequency range default timings for x32 operation*/ +#define H4_2420_SDRC_SHARING 0x00000100 +#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */ +#define H4_2420_SDRC_MR_0_SDR 0x00000031 +#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */ +#define SDP_2430_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) /* Infin ddr module */ +#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */ +#define H4_2420_SDRC_MR_0_DDR 0x00000032 + +#define H4_2422_SDRC_SHARING 0x00004b00 +#define H4_2422_SDRC_MDCFG_MONO_DDR 0x01A02011 /* stacked mono die ddr on 2422 */ +#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked dual die ddr on 2422 */ +#define H4_2422_SDRC_MR_0_DDR 0x00000032 + +#define H4_2423_SDRC_SHARING 0x00004900 /* 2420POP board cke1 not connected */ +#define H4_2423_SDRC_MDCFG_0_DDR 0x01A02011 /* stacked dual die ddr on 2423 */ +#define H4_2423_SDRC_MDCFG_1_DDR 0x00801011 /* stacked dual die ddr on 2423 */ + +/* ES1 work around timings */ +#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */ +#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020 +#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */ + +/* optimized timings good for current shipping parts */ +#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485 +#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e +#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */ +#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */ +#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50 = 0x3de */ +#define SDP_24XX_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50 = 0x4e2 */ +#define H4_242X_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 90deg, allow DPLLout*1 to work (combo)*/ +#define H4_242X_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 90deg, for ES2 */ +#define SDP_24XX_SDRC_DLLAB_CTRL_165MHz 0x0000170C /* 72deg, code will recalc dll load */ + +/* Infineon part of 2430SDP (133MHz optimized) ~ 7.5ns + * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 + * TDPL = 15/7.5 = 2 + * TRRD = 15/2.5 = 2 + * TRCD = 22.5/7.5 = 3 + * TRP = 22.5/7.5 = 3 + * TRAS = 45/7.5 = 6 + * TRC = 65/7.5 = 8.6->9 + * TRFC = 75/7.5 = 10 + * ACTIMB + * TCKE = 2 + * XSR = 120/7.5 = 16 + */ +#define TDAL_133 5 +#define TDPL_133 2 +#define TRRD_133 2 +#define TRCD_133 3 +#define TRP_133 3 +#define TRAS_133 6 +#define TRC_133 9 +#define TRFC_133 10 +#define V_ACTIMA_133 ((TRFC_133 << 27) | (TRC_133 << 22) | (TRAS_133 << 18) |(TRP_133 << 15) | \ + (TRCD_133 << 12) |(TRRD_133 << 9) |(TDPL_133 << 6) | (TDAL_133)) + +#define TCKE_133 2 +#define XSR_133 16 +#define V_ACTIMB_133 ((TCKE_133 << 12) | (XSR_133 << 0)) + +/* Infineon part of 2430SDP (165MHz optimized) 6.06ns + * ACTIMA + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 18/6 = 3 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 72/6 = 12 + * ACTIMB + * TCKE = 2 + * XSR = 120/6 = 20 + */ +#define TDAL_165 6 +#define TDPL_165 3 +#define TRRD_165 2 +#define TRCD_165 3 +#define TRP_165 3 +#define TRAS_165 7 +#define TRC_165 10 +#define TRFC_165 12 +#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) |(TRP_165 << 15) | \ + (TRCD_165 << 12) |(TRRD_165 << 9) |(TDPL_165 << 6) | (TDAL_165)) + +#define TCKE_165 2 +#define XSR_165 20 +#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0)) + +#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133 +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz +# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_100MHz +#elif defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) +# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz +# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133 +# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz +# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz +# define H4_2420_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz +# define SDP_2430_SDRC_DLLAB_CTRL 0x0000730E +# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz +# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz +# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz +# define H4_2422_SDRC_DLLAB_CTRL H4_242X_SDRC_DLLAB_CTRL_133MHz +#elif defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) +# define H4_2420_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 +# define SDP_2430_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 +# define H4_2420_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 +# define H4_2420_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz +# define H4_2420_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz +# define SDP_2430_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz +# define H4_2422_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 +# define H4_2422_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 +# define H4_2422_SDRC_RFR_CTRL SDP_24XX_SDRC_RFR_CTRL_165MHz +# define H4_2422_SDRC_DLLAB_CTRL SDP_24XX_SDRC_DLLAB_CTRL_165MHz +#endif + +/* + * GPMC settings - + * Definitions is as per the following format + * # define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of the same. + * if values are independent of the board, this definition will be present in this file + * if values are dependent on the board, then this should go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * STNOR - Intel Strata Flash + * SMNAND - Samsung NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley NOR + * ONNAND - Samsung One NAND + * + * include/configs/file.h contains the following defn - for all CS we are interested + * #define OMAP24XX_GPMC_CSx PART + * #define OMAP24XX_GPMC_CSx_SIZE Size + * #define OMAP24XX_GPMC_CSx_MAP Map + * Where: + * x - CS number + * PART - Part Name as defined above + * SIZE - how big is the mapping to be + * GPMC_SIZE_128M - 0x8 + * GPMC_SIZE_64M - 0xC + * GPMC_SIZE_32M - 0xE + * GPMC_SIZE_16M - 0xF + * MAP - Map this CS to which address(GPMC address space)- Absolute address + * >>24 before being used. + */ + +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#if defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) /* L3 at 100MHz */ +# define SMNAND_GPMC_CONFIG1 0x0 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x000f0f01 +# define STNOR_GPMC_CONFIG3 0x00050502 +# define STNOR_GPMC_CONFIG4 0x0C060C06 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x0 /* 0? Not defined so far... this value is reset val as per gpmc doc */ +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001F1F00 +# define MPDB_GPMC_CONFIG3 0x00080802 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x031A1F1F +# define MPDB_GPMC_CONFIG6 0x000003C2 +#endif + +#if defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) || defined(PRCM_CONFIG_3) /* L3 at 133MHz */ +# define SMNAND_GPMC_CONFIG1 0x00001800 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x10081008 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x000004c4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x000004C4 + +# define SIBNOR_GPMC_CONFIG1 0x3 +# define SIBNOR_GPMC_CONFIG2 0x00151501 +# define SIBNOR_GPMC_CONFIG3 0x00060602 +# define SIBNOR_GPMC_CONFIG4 0x10081008 +# define SIBNOR_GPMC_CONFIG5 0x01131F1F +# define SIBNOR_GPMC_CONFIG6 0x00000000 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000c0c01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0c040c04 +# define ONENAND_GPMC_CONFIG5 0x010C1010 +# define ONENAND_GPMC_CONFIG6 0x00000000 + +# define PCMCIA_GPMC_CONFIG1 0x01E91200 +# define PCMCIA_GPMC_CONFIG2 0x001E1E01 +# define PCMCIA_GPMC_CONFIG3 0x00020203 +# define PCMCIA_GPMC_CONFIG4 0x1D041D04 +# define PCMCIA_GPMC_CONFIG5 0x031D1F1F +# define PCMCIA_GPMC_CONFIG6 0x000004C4 +#endif /* endif CFG_PRCM_III */ + +#if defined (PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) /* L3 at 165MHz */ +# define SMNAND_GPMC_CONFIG1 0x00001800 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x11091109 +# define STNOR_GPMC_CONFIG5 0x01141F1F +# define STNOR_GPMC_CONFIG6 0x000004c4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1c0b1c0a +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x000004C4 + +# define SIBNOR_GPMC_CONFIG1 0x3 +# define SIBNOR_GPMC_CONFIG2 0x00151501 +# define SIBNOR_GPMC_CONFIG3 0x00060602 +# define SIBNOR_GPMC_CONFIG4 0x11091109 +# define SIBNOR_GPMC_CONFIG5 0x01141F1F +# define SIBNOR_GPMC_CONFIG6 0x00000000 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000F0F01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0F040F04 +# define ONENAND_GPMC_CONFIG5 0x010F1010 +# define ONENAND_GPMC_CONFIG6 0x00000000 + +# define PCMCIA_GPMC_CONFIG1 0x01E91200 +# define PCMCIA_GPMC_CONFIG2 0x001E1E01 +# define PCMCIA_GPMC_CONFIG3 0x00020203 +# define PCMCIA_GPMC_CONFIG4 0x1D041D04 +# define PCMCIA_GPMC_CONFIG5 0x031D1F1F +# define PCMCIA_GPMC_CONFIG6 0x000004C4 + +#endif + +#if 0 +/* Board Specific Settings for each of the configurations for chips + * whose values change as per platform. - None currently + */ +#if CONFIG_OMAP24XXH4 +#include +#endif + +#if CONFIG_2430SDP +#include +#endif + +#endif /* if 0 */ + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define PROC_NOR 1 +#define PROC_NAND 2 +#define PISMO_SIBLEY0 3 +#define PISMO_SIBLEY1 4 +#define PISMO_ONENAND 5 +#define DBG_MPDB 6 +#define PISMO_PCMCIA 7 + +/* make it readable for the gpmc_init */ +#define PROC_NOR_BASE FLASH_BASE +#define PROC_NAND_BASE NAND_BASE +#define PISMO_SIB0_BASE SIBLEY_MAP1 +#define PISMO_SIB1_BASE SIBLEY_MAP2 +#define PISMO_ONEN_BASE ONENAND_MAP +#define DBG_MPDB_BASE DEBUG_BASE +#define PISMO_PCMCIA_BASE PCMCIA_BASE + +#endif /* endif _OMAP24XX_MEM_H_ */ diff --git a/include/asm-arm/arch-arm1136/mux.h b/include/asm-arm/arch-arm1136/mux.h new file mode 100644 index 000000000..e61f9f18f --- /dev/null +++ b/include/asm-arm/arch-arm1136/mux.h @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP2420_MUX_H_ +#define _OMAP2420_MUX_H_ + +#ifndef __ASSEMBLY__ +typedef unsigned char uint8; +typedef unsigned int uint32; + +void muxSetupSDRC(void); +void muxSetupGPMC(void); +void muxSetupUsb0(void); +void muxSetupUart3(void); +void muxSetupI2C1(void); +void muxSetupUART1(void); +void muxSetupLCD(void); +void muxSetupCamera(void); +void muxSetupMMCSD(void) ; +void muxSetupTouchScreen(void) ; +void muxSetupHDQ(void); +#endif + +#define USB_OTG_CTRL ((volatile uint32 *)0x4805E30C) + +/* Pin Muxing registers used for HDQ (Smart battery) */ +#define CONTROL_PADCONF_HDQ_SIO ((volatile unsigned char *)0x48000115) + +/* Pin Muxing registers used for GPMC */ +#define CONTROL_PADCONF_GPMC_D2_BYTE0 ((volatile unsigned char *)0x48000088) +#define CONTROL_PADCONF_GPMC_D2_BYTE1 ((volatile unsigned char *)0x48000089) +#define CONTROL_PADCONF_GPMC_D2_BYTE2 ((volatile unsigned char *)0x4800008A) +#define CONTROL_PADCONF_GPMC_D2_BYTE3 ((volatile unsigned char *)0x4800008B) + +#define CONTROL_PADCONF_GPMC_NCS0_BYTE0 ((volatile unsigned char *)0x4800008C) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE1 ((volatile unsigned char *)0x4800008D) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE2 ((volatile unsigned char *)0x4800008E) +#define CONTROL_PADCONF_GPMC_NCS0_BYTE3 ((volatile unsigned char *)0x4800008F) + +/* Pin Muxing registers used for SDRC */ +#define CONTROL_PADCONF_SDRC_STK_DM1 0xAC +#define CONTROL_PADCONF_SDRC_DQS1 0xB0 + +#define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0) +#define CONTROL_PADCONF_SDRC_NCS0_BYTE1 ((volatile unsigned char *)0x480000A1) +#define CONTROL_PADCONF_SDRC_NCS0_BYTE2 ((volatile unsigned char *)0x480000A2) +#define CONTROL_PADCONF_SDRC_NCS0_BYTE3 ((volatile unsigned char *)0x480000A3) + +#define CONTROL_PADCONF_SDRC_A14_BYTE0 ((volatile unsigned char *)0x48000030) +#define CONTROL_PADCONF_SDRC_A14_BYTE1 ((volatile unsigned char *)0x48000031) +#define CONTROL_PADCONF_SDRC_A14_BYTE2 ((volatile unsigned char *)0x48000032) +#define CONTROL_PADCONF_SDRC_A14_BYTE3 ((volatile unsigned char *)0x48000033) + +/* Pin Muxing registers used for Touch Screen (SPI) */ +#define CONTROL_PADCONF_SPI1_CLK ((volatile unsigned char *)0x480000FF) +#define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100) +#define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101) +#define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102) + +#define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B) + +/* Pin Muxing registers used for MMCSD */ +#define CONTROL_PADCONF_MMC_CLKI ((volatile unsigned char *)0x480000FE) +#define CONTROL_PADCONF_MMC_CLKO ((volatile unsigned char *)0x480000F3) +#define CONTROL_PADCONF_MMC_CMD ((volatile unsigned char *)0x480000F4) +#define CONTROL_PADCONF_MMC_DAT0 ((volatile unsigned char *)0x480000F5) +#define CONTROL_PADCONF_MMC_DAT1 ((volatile unsigned char *)0x480000F6) +#define CONTROL_PADCONF_MMC_DAT2 ((volatile unsigned char *)0x480000F7) +#define CONTROL_PADCONF_MMC_DAT3 ((volatile unsigned char *)0x480000F8) +#define CONTROL_PADCONF_MMC_DAT_DIR0 ((volatile unsigned char *)0x480000F9) +#define CONTROL_PADCONF_MMC_DAT_DIR1 ((volatile unsigned char *)0x480000FA) +#define CONTROL_PADCONF_MMC_DAT_DIR2 ((volatile unsigned char *)0x480000FB) +#define CONTROL_PADCONF_MMC_DAT_DIR3 ((volatile unsigned char *)0x480000FC) +#define CONTROL_PADCONF_MMC_CMD_DIR ((volatile unsigned char *)0x480000FD) + +#define CONTROL_PADCONF_SDRC_A14 ((volatile unsigned char *)0x48000030) +#define CONTROL_PADCONF_SDRC_A13 ((volatile unsigned char *)0x48000031) + +/* Pin Muxing registers used for CAMERA */ +#define CONTROL_PADCONF_SYS_NRESWARM ((volatile unsigned char *)0x4800012B) + +#define CONTROL_PADCONF_CAM_XCLK ((volatile unsigned char *)0x480000DC) +#define CONTROL_PADCONF_CAM_LCLK ((volatile unsigned char *)0x480000DB) +#define CONTROL_PADCONF_CAM_VS ((volatile unsigned char *)0x480000DA) +#define CONTROL_PADCONF_CAM_HS ((volatile unsigned char *)0x480000D9) +#define CONTROL_PADCONF_CAM_D0 ((volatile unsigned char *)0x480000D8) +#define CONTROL_PADCONF_CAM_D1 ((volatile unsigned char *)0x480000D7) +#define CONTROL_PADCONF_CAM_D2 ((volatile unsigned char *)0x480000D6) +#define CONTROL_PADCONF_CAM_D3 ((volatile unsigned char *)0x480000D5) +#define CONTROL_PADCONF_CAM_D4 ((volatile unsigned char *)0x480000D4) +#define CONTROL_PADCONF_CAM_D5 ((volatile unsigned char *)0x480000D3) +#define CONTROL_PADCONF_CAM_D6 ((volatile unsigned char *)0x480000D2) +#define CONTROL_PADCONF_CAM_D7 ((volatile unsigned char *)0x480000D1) +#define CONTROL_PADCONF_CAM_D8 ((volatile unsigned char *)0x480000D0) +#define CONTROL_PADCONF_CAM_D9 ((volatile unsigned char *)0x480000CF) + +/* Pin Muxing registers used for LCD */ +#define CONTROL_PADCONF_DSS_D0 ((volatile unsigned char *)0x480000B3) +#define CONTROL_PADCONF_DSS_D1 ((volatile unsigned char *)0x480000B4) +#define CONTROL_PADCONF_DSS_D2 ((volatile unsigned char *)0x480000B5) +#define CONTROL_PADCONF_DSS_D3 ((volatile unsigned char *)0x480000B6) +#define CONTROL_PADCONF_DSS_D4 ((volatile unsigned char *)0x480000B7) +#define CONTROL_PADCONF_DSS_D5 ((volatile unsigned char *)0x480000B8) +#define CONTROL_PADCONF_DSS_D6 ((volatile unsigned char *)0x480000B9) +#define CONTROL_PADCONF_DSS_D7 ((volatile unsigned char *)0x480000BA) +#define CONTROL_PADCONF_DSS_D8 ((volatile unsigned char *)0x480000BB) +#define CONTROL_PADCONF_DSS_D9 ((volatile unsigned char *)0x480000BC) +#define CONTROL_PADCONF_DSS_D10 ((volatile unsigned char *)0x480000BD) +#define CONTROL_PADCONF_DSS_D11 ((volatile unsigned char *)0x480000BE) +#define CONTROL_PADCONF_DSS_D12 ((volatile unsigned char *)0x480000BF) +#define CONTROL_PADCONF_DSS_D13 ((volatile unsigned char *)0x480000C0) +#define CONTROL_PADCONF_DSS_D14 ((volatile unsigned char *)0x480000C1) +#define CONTROL_PADCONF_DSS_D15 ((volatile unsigned char *)0x480000C2) +#define CONTROL_PADCONF_DSS_D16 ((volatile unsigned char *)0x480000C3) +#define CONTROL_PADCONF_DSS_D17 ((volatile unsigned char *)0x480000C4) +#define CONTROL_PADCONF_DSS_PCLK ((volatile unsigned char *)0x480000CB) +#define CONTROL_PADCONF_DSS_VSYNC ((volatile unsigned char *)0x480000CC) +#define CONTROL_PADCONF_DSS_HSYNC ((volatile unsigned char *)0x480000CD) +#define CONTROL_PADCONF_DSS_ACBIAS ((volatile unsigned char *)0x480000CE) + +/* Pin Muxing registers used for UART1 */ +#define CONTROL_PADCONF_UART1_CTS ((volatile unsigned char *)0x480000C5) +#define CONTROL_PADCONF_UART1_RTS ((volatile unsigned char *)0x480000C6) +#define CONTROL_PADCONF_UART1_TX ((volatile unsigned char *)0x480000C7) +#define CONTROL_PADCONF_UART1_RX ((volatile unsigned char *)0x480000C8) + +/* Pin Muxing registers used for I2C1 */ +#define CONTROL_PADCONF_I2C1_SCL ((volatile unsigned char *)0x48000111) +#define CONTROL_PADCONF_I2C1_SDA ((volatile unsigned char *)0x48000112) + +/* Pin Muxing registres used for USB0. */ +#define CONTROL_PADCONF_USB0_PUEN ((volatile uint8 *)0x4800011D) +#define CONTROL_PADCONF_USB0_VP ((volatile uint8 *)0x4800011E) +#define CONTROL_PADCONF_USB0_VM ((volatile uint8 *)0x4800011F) +#define CONTROL_PADCONF_USB0_RCV ((volatile uint8 *)0x48000120) +#define CONTROL_PADCONF_USB0_TXEN ((volatile uint8 *)0x48000121) +#define CONTROL_PADCONF_USB0_SE0 ((volatile uint8 *)0x48000122) +#define CONTROL_PADCONF_USB0_DAT ((volatile uint8 *)0x48000123) + +/* Pin Muxing registers used for UART3/IRDA */ +#define CONTROL_PADCONF_UART3_TX_IRTX ((volatile uint8 *)0x48000118) +#define CONTROL_PADCONF_UART3_RX_IRRX ((volatile uint8 *)0x48000119) + +#endif diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h new file mode 100644 index 000000000..e8638a609 --- /dev/null +++ b/include/asm-arm/arch-arm1136/omap2420.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP2420_SYS_H_ +#define _OMAP2420_SYS_H_ + +#include + +/* + * 2420 specific Section + */ +#define OMAP24XX_L4_IO_BASE (0x48000000) + +/* L3 Firewall */ +#define A_REQINFOPERM0 0x68005048 +#define A_READPERM0 0x68005050 +#define A_WRITEPERM0 0x68005058 + +/* CONTROL */ +#define OMAP24XX_CTRL_BASE (0x48000000) + +/* TAP information */ +#define OMAP24XX_TAP_BASE (0x48014000) + +/* GPMC */ +#define OMAP24XX_GPMC_BASE (0x6800A000) + +/* SMS */ +#define OMAP24XX_SMS_BASE 0x68008000 + +/* SDRC */ +#define OMAP24XX_SDRC_BASE 0x68009000 + +/* UART */ +#define OMAP24XX_UART1 0x4806A000 +#define OMAP24XX_UART2 0x4806C000 +#define OMAP24XX_UART3 0x4806E000 + +/* General Purpose Timers */ +#define OMAP24XX_GPT1 0x48028000 +#define OMAP24XX_GPT2 0x4802A000 +#define OMAP24XX_GPT3 0x48078000 +#define OMAP24XX_GPT4 0x4807A000 +#define OMAP24XX_GPT5 0x4807C000 +#define OMAP24XX_GPT6 0x4807E000 +#define OMAP24XX_GPT7 0x48080000 +#define OMAP24XX_GPT8 0x48082000 +#define OMAP24XX_GPT9 0x48084000 +#define OMAP24XX_GPT10 0x48086000 +#define OMAP24XX_GPT11 0x48088000 +#define OMAP24XX_GPT12 0x4808A000 + + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE 0x48020000 +#define WD2_BASE 0x48022000 +#define WD3_BASE 0x48024000 +#define WD4_BASE 0x48026000 + +/* 32KTIMER */ +#define SYNC_32KTIMER 0x48004000 +#define S32K_CR (SYNC_32KTIMER+0x10) + +/* PRCM */ +#define OMAP24XX_CM_BASE 0x48008000 + +/* + * H4 specific Section + */ + +/* + * The 2420's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + */ +#if defined(CONFIG_OMAP24XXH4) + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + +/* FPGA on Debug board.*/ +#define ETH_CONTROL_REG (DEBUG_BASE+0x30b) +#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) +#endif /* endif CONFIG_2420H4 */ + +#endif diff --git a/include/asm-arm/arch-arm1136/omap2430.h b/include/asm-arm/arch-arm1136/omap2430.h new file mode 100644 index 000000000..8a3441825 --- /dev/null +++ b/include/asm-arm/arch-arm1136/omap2430.h @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2004-2005 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP2430_SYS_H_ +#define _OMAP2430_SYS_H_ + +#include + +/* + * 2430 specific Section + */ + +/* Stuff on L3 Interconnect */ +#define SMX_APE_BASE 0x68000000 + +/* L3 Firewall */ +#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) +#define A_READPERM0 (SMX_APE_BASE + 0x05050) +#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) + +/* GPMC */ +#define OMAP24XX_GPMC_BASE (0x6E000000) + +/* SMS */ +#define OMAP24XX_SMS_BASE 0x6C000000 + +/* SDRC */ +#define OMAP24XX_SDRC_BASE 0x6D000000 + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP243X_CORE_L4_IO_BASE 0x48000000 + +#define OMAP243X_WAKEUP_L4_IO_BASE 0x49000000 + +#define OMAP24XX_L4_IO_BASE OMAP243X_CORE_L4_IO_BASE + +/* CONTROL */ +#define OMAP24XX_CTRL_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x2000) + +/* TAP information */ +#define OMAP24XX_TAP_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0xA000) + +/* UART */ +#define OMAP24XX_UART1 (OMAP24XX_L4_IO_BASE+0x6a000) +#define OMAP24XX_UART2 (OMAP24XX_L4_IO_BASE+0x6c000) +#define OMAP24XX_UART3 (OMAP24XX_L4_IO_BASE+0x6e000) + +/* General Purpose Timers */ +#define OMAP24XX_GPT1 (OMAP243X_WAKEUP_L4_IO_BASE+0x18000) +#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000) +#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000) +#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000) +#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000) +#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000) +#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000) +#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000) +#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000) +#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000) +#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000) +#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000) + + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x14000) +#define WD2_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x16000) +#define WD3_BASE (OMAP24XX_L4_IO_BASE+0x24000) /* not present */ +#define WD4_BASE (OMAP24XX_L4_IO_BASE+0x26000) + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x20000) +#define S32K_CR (SYNC_32KTIMER_BASE+0x10) + +/* PRCM */ +#define OMAP24XX_CM_BASE (OMAP243X_WAKEUP_L4_IO_BASE+0x06000) + +/* + * SDP2430 specific Section + */ + +/* + * The 243x's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + * Same as in SDP2430 + */ +#if (CONFIG_2430SDP) + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + +/* FPGA on Debug board.*/ +#define ETH_CONTROL_REG (DEBUG_BASE+0x30b) +#define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) +#define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) +#define LED_REGISTER (DEBUG_BASE+0x40) +#define FPGA_REV_REGISTER (DEBUG_BASE+0x10) +#define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) +#define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) +#define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) +#define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) +#define I2C2_MEMORY_STATUS_REG (DEBUG_BASE+0x10000+0xA) +#define ENHANCED_UI_EE_NAME "750-2038" +#define GDP_MB_EE_NAME "750-2031-3" + +#endif /* endif (CONFIG_2430SDP) */ + +#endif diff --git a/include/asm-arm/arch-arm1136/rev.h b/include/asm-arm/arch-arm1136/rev.h new file mode 100644 index 000000000..9aedbc533 --- /dev/null +++ b/include/asm-arm/arch-arm1136/rev.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP24XX_REV_H_ +#define _OMAP24XX_REV_H_ + +typedef struct h4_system_data { + /* base board info */ + u32 base_b_rev; /* rev from base board i2c */ + /* cpu board info */ + u32 cpu_b_rev; /* rev from cpu board i2c */ + u32 cpu_b_mux; /* mux type on daughter board */ + u32 cpu_b_ddr_type; /* mem type */ + u32 cpu_b_ddr_speed; /* ddr speed rating */ + u32 cpu_b_switches; /* boot ctrl switch settings */ + /* cpu info */ + u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ + u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ +} h4_sys_data; + +#define CDB_DDR_COMBO /* combo part on cpu daughter card */ +#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_2420 0x2420 +#define CPU_2422 0x2422 +#define CPU_2430 0x2430 + +#define CPU_2422_ES1 1 +#define CPU_2422_ES2 2 +#define CPU_2420_ES1 1 +#define CPU_2420_ES2 2 + +#endif diff --git a/include/asm-arm/arch-arm1136/sizes.h b/include/asm-arm/arch-arm1136/sizes.h new file mode 100644 index 000000000..aaba18f15 --- /dev/null +++ b/include/asm-arm/arch-arm1136/sizes.h @@ -0,0 +1,49 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_31M 0x01F00000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/include/asm-arm/arch-arm1136/sys_info.h b/include/asm-arm/arch-arm1136/sys_info.h new file mode 100644 index 000000000..e5a51acd9 --- /dev/null +++ b/include/asm-arm/arch-arm1136/sys_info.h @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP24XX_SYS_INFO_H_ +#define _OMAP24XX_SYS_INFO_H_ + +typedef struct h4_system_data { + /* base board info */ + u32 base_b_rev; /* rev from base board i2c */ + /* cpu board info */ + u32 cpu_b_rev; /* rev from cpu board i2c */ + u32 cpu_b_mux; /* mux type on daughter board */ + u32 cpu_b_ddr_type; /* mem type */ + u32 cpu_b_ddr_speed; /* ddr speed rating */ + u32 cpu_b_switches; /* boot ctrl switch settings */ + /* cpu info */ + u32 cpu_type; /* type of cpu; 2420, 2422, 2430,...*/ + u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/ +} h4_sys_data; + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_2420 0x2420 +#define CPU_2422 0x2422 /* 2420 + 64M stacked */ +#define CPU_2423 0x2423 /* 2420 + 96M stacked */ +#define CPU_2430 0x2430 + +/* 242x real hardware: + * ES1 = rev 0 + * ES2 = rev 1 + * ES2.05 = rev 2 + * ES2.1 = rev 3 + * ES2.1.1 = rev 4 + * ES2.2 = rev 5 + */ + +/* 242x code defines: + * ES1 = 0+1 = 1 + * ES2 = 1+1 = 2 + * ES2.05 = 2+1 = 3 + * ES2.1 = 3+1 = 4 + * ES2.1.1 = 4+1 = 5 + * ES2.2 = 5+1 = 6 + */ +#define CPU_2422_ES1 1 +#define CPU_2422_ES2 2 +#define CPU_2422_ES2_05 3 +#define CPU_2422_ES2_1 4 +#define CPU_2422_ES2_1_1 5 +#define CPU_2422_ES2_2 6 + +#define CPU_2420_ES1 1 +#define CPU_2420_ES2 2 +#define CPU_2420_ES2_05 3 +#define CPU_2420_ES2_1 4 +#define CPU_2420_ES2_1_1 5 +#define CPU_2420_ES2_2 6 + +#define CPU_242X_ES1 1 +#define CPU_242X_ES2 2 +#define CPU_242X_ES2_05 3 +#define CPU_242X_ES2_1 4 +#define CPU_242X_ES2_1_1 5 +#define CPU_242X_ES2_2 6 + +/* 243x real hardware: + * ES1 = rev 0 + * ES2 = rev 1 + * + * 243x code defines: + * ES1 = 0+1 = 1 + * ES2 = 1+1 = 2 + * ES2.1.0 = 2+1 = 3 + */ +#define CPU_2430_ES1 1 +#define CPU_2430_ES2 2 +#define CPU_2430_ES2_1_0 3 + +#define CPU_2420_CHIPID 0x0B5D9000 +#define CPU_2430_CHIPID 0x0B68A000 +#define CPU_24XX_ID_MASK 0x0FFFF000 +#define CPU_242X_REV_MASK 0xF0000000 +#define CPU_242X_PID_MASK 0x000F0000 + +#define BOARD_H4_MENELAUS 1 +#define BOARD_H4_SDP 2 +#define BOARD_H4_MENELAUS_HRP 3 +#define BOARD_SDP_2430_M1 4 /* pre-T2 platform */ +#define BOARD_SDP_2430_T2 5 /* Triton2 companion chip */ +#define BOARD_GDP_2430_T2 6 /* 2430 GDP Variant */ + +/* Various SDP Variants */ +#define BOARD_SDP_2430_0_1 0x01 +#define BOARD_SDP_2430_1_0 0x10 +#define BOARD_SDP_2430_1_1 0x11 +#define BOARD_SDP_2430_2_1 0x20 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ +#define I2C_TRITON2 0x4B /* addres of power group */ + +#endif diff --git a/include/asm-arm/arch-arm1136/sys_proto.h b/include/asm-arm/arch-arm1136/sys_proto.h new file mode 100644 index 000000000..9d8e5b262 --- /dev/null +++ b/include/asm-arm/arch-arm1136/sys_proto.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2004 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP24XX_SYS_PROTO_H_ +#define _OMAP24XX_SYS_PROTO_H_ + +void prcm_init(void); +void memif_init(void); +void sdrc_init(void); +void do_sdrc_init(u32,u32); +void gpmc_init(void); + +void ether_init(void); +void watchdog_init(void); +void set_muxconf_regs(void); +void peripheral_enable(void); + +u32 get_cpu_type(void); +u32 get_cpu_rev(void); +u32 get_mem_type(void); +u32 get_sysboot_value(void); +u32 get_gpmc0_base(void); +u32 is_gpmc_muxed(void); +u32 get_gpmc0_type(void); +u32 get_gpmc0_width(void); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); +u32 get_board_type(void); +void display_board_info(u32); +void update_mux(u32,u32); +u32 get_sdr_cs_size(u32 offset); + +u32 running_in_sdram(void); +u32 running_in_sram(void); +u32 running_in_flash(void); +u32 running_from_internal_boot(void); +u32 get_device_type(void); +#endif diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h index c650c3b00..f0529fd09 100644 --- a/include/asm-arm/arch-arm720t/netarm_mem_module.h +++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h @@ -170,15 +170,15 @@ /* Option B Registers (0xFFC0_00x8) */ #define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001) #define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002) -#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) -#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) -#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) +#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) +#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) +#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) -#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) -#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) -#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) +#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) +#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) +#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) #endif #endif diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/include/asm-arm/arch-arm720t/netarm_ser_module.h index 6fbae11c8..fceabd173 100644 --- a/include/asm-arm/arch-arm720t/netarm_ser_module.h +++ b/include/asm-arm/arch-arm720t/netarm_ser_module.h @@ -284,21 +284,21 @@ typedef struct { /* from section 7.5.4 of HW Ref Guide */ /* #ifdef CONFIG_NETARM_PLL_BYPASS */ -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_EXT_5 | \ - ( ( ( ( NETARM_XTAL_FREQ / \ - ( x * 10 ) ) - 1 ) / 16 ) & \ +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_EXT_5 | \ + ( ( ( ( NETARM_XTAL_FREQ / \ + ( x * 10 ) ) - 1 ) / 16 ) & \ NETARM_SER_BR_MASK ) ) /* #else -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_SYSTEM | \ - ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ - ( x * 2 ) ) - 1 ) / 16 ) & \ +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_SYSTEM | \ + ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ + ( x * 2 ) ) - 1 ) / 16 ) & \ NETARM_SER_BR_MASK ) ) #endif */ @@ -313,13 +313,13 @@ typedef struct { /* #ifdef CONFIG_NETARM_PLL_BYPASS */ #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ + ( x * 5 * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) /* #else #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ + ( x * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) #endif */ @@ -327,11 +327,11 @@ typedef struct { #if 0 #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ + ( x * 5 * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ + ( x * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) #endif diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-arm720t/s3c4510b.h index 6b8c8edd7..73a3b6d85 100644 --- a/include/asm-arm/arch-arm720t/s3c4510b.h +++ b/include/asm-arm/arch-arm720t/s3c4510b.h @@ -35,7 +35,7 @@ /* Special Register Start Address After System Reset */ #define REG_BASE (0x03ff0000) -#define SPSTR (REG_BASE) +#define SPSTR (REG_BASE) /* *********************** */ /* System Manager Register */ @@ -100,7 +100,7 @@ #define REG_I2C_CON (REG_BASE+0xf000) #define REG_I2C_BUF (REG_BASE+0xf004) #define REG_I2C_PS (REG_BASE+0xf008) -#define REG_I2C_COUNT (REG_BASE+0xf00c) +#define REG_I2C_COUNT (REG_BASE+0xf00c) /********************/ /* GDMA 0 */ @@ -149,7 +149,7 @@ /********************/ /* Timer Register */ /********************/ -#define REG_TMOD (REG_BASE+0x6000) +#define REG_TMOD (REG_BASE+0x6000) #define REG_TDATA0 (REG_BASE+0x6004) #define REG_TDATA1 (REG_BASE+0x6008) #define REG_TCNT0 (REG_BASE+0x600c) @@ -159,8 +159,8 @@ /* I/O Port Interface */ /**********************/ #define REG_IOPMODE (REG_BASE+0x5000) -#define REG_IOPCON (REG_BASE+0x5004) -#define REG_IOPDATA (REG_BASE+0x5008) +#define REG_IOPCON (REG_BASE+0x5004) +#define REG_IOPDATA (REG_BASE+0x5008) /*********************************/ /* Interrupt Controller Register */ diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 95db0177c..97d470484 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -25,85 +25,84 @@ #ifndef AT91RM9200_H #define AT91RM9200_H -#ifndef __ASSEMBLY__ typedef volatile unsigned int AT91_REG; /* Hardware register definition */ -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ -/*****************************************************************************/ +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/******************************************************************************/ typedef struct _AT91S_TC { - AT91_REG TC_CCR; /* Channel Control Register */ - AT91_REG TC_CMR; /* Channel Mode Register */ - AT91_REG Reserved0[2]; /* */ - AT91_REG TC_CV; /* Counter Value */ - AT91_REG TC_RA; /* Register A */ - AT91_REG TC_RB; /* Register B */ - AT91_REG TC_RC; /* Register C */ - AT91_REG TC_SR; /* Status Register */ - AT91_REG TC_IER; /* Interrupt Enable Register */ - AT91_REG TC_IDR; /* Interrupt Disable Register */ - AT91_REG TC_IMR; /* Interrupt Mask Register */ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register */ + AT91_REG Reserved0[2]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ } AT91S_TC, *AT91PS_TC; -#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ -#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ -#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ -#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ -#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK*/ -#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ -#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ -#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ +#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ +#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ +#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ +#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ +#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */ +#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ +#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ +#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Usart */ -/*****************************************************************************/ +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Usart */ +/******************************************************************************/ typedef struct _AT91S_USART { - AT91_REG US_CR; /* Control Register */ - AT91_REG US_MR; /* Mode Register */ - AT91_REG US_IER; /* Interrupt Enable Register */ - AT91_REG US_IDR; /* Interrupt Disable Register */ - AT91_REG US_IMR; /* Interrupt Mask Register */ - AT91_REG US_CSR; /* Channel Status Register */ - AT91_REG US_RHR; /* Receiver Holding Register */ - AT91_REG US_THR; /* Transmitter Holding Register */ - AT91_REG US_BRGR; /* Baud Rate Generator Register */ - AT91_REG US_RTOR; /* Receiver Time-out Register */ - AT91_REG US_TTGR; /* Transmitter Time-guard Register */ - AT91_REG Reserved0[5]; /* */ - AT91_REG US_FIDI; /* FI_DI_Ratio Register */ - AT91_REG US_NER; /* Nb Errors Register */ - AT91_REG US_XXR; /* XON_XOFF Register */ - AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[5]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG US_XXR; /* XON_XOFF Register */ + AT91_REG US_IF; /* IRDA_FILTER Register */ AT91_REG Reserved1[44]; /* */ - AT91_REG US_RPR; /* Receive Pointer Register */ - AT91_REG US_RCR; /* Receive Counter Register */ - AT91_REG US_TPR; /* Transmit Pointer Register */ - AT91_REG US_TCR; /* Transmit Counter Register */ - AT91_REG US_RNPR; /* Receive Next Pointer Register */ - AT91_REG US_RNCR; /* Receive Next Counter Register */ - AT91_REG US_TNPR; /* Transmit Next Pointer Register */ - AT91_REG US_TNCR; /* Transmit Next Counter Register */ - AT91_REG US_PTCR; /* PDC Transfer Control Register */ - AT91_REG US_PTSR; /* PDC Transfer Status Register */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ } AT91S_USART, *AT91PS_USART; -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ -/*****************************************************************************/ +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ +/******************************************************************************/ typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; /* Main Oscillator Register */ - AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ - AT91_REG CKGR_PLLAR; /* PLL A Register */ - AT91_REG CKGR_PLLBR; /* PLL B Register */ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG CKGR_PLLAR; /* PLL A Register */ + AT91_REG CKGR_PLLBR; /* PLL B Register */ } AT91S_CKGR, *AT91PS_CKGR; /* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ @@ -142,78 +141,78 @@ typedef struct _AT91S_CKGR #define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ #define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ -/*****************************************************************************/ +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ +/******************************************************************************/ typedef struct _AT91S_PIO { - AT91_REG PIO_PER; /* PIO Enable Register */ - AT91_REG PIO_PDR; /* PIO Disable Register */ - AT91_REG PIO_PSR; /* PIO Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PIO_OER; /* Output Enable Register */ - AT91_REG PIO_ODR; /* Output Disable Registerr */ - AT91_REG PIO_OSR; /* Output Status Register */ - AT91_REG Reserved1[1]; /* */ - AT91_REG PIO_IFER; /* Input Filter Enable Register */ - AT91_REG PIO_IFDR; /* Input Filter Disable Register */ - AT91_REG PIO_IFSR; /* Input Filter Status Register */ - AT91_REG Reserved2[1]; /* */ - AT91_REG PIO_SODR; /* Set Output Data Register */ - AT91_REG PIO_CODR; /* Clear Output Data Register */ - AT91_REG PIO_ODSR; /* Output Data Status Register */ - AT91_REG PIO_PDSR; /* Pin Data Status Register */ - AT91_REG PIO_IER; /* Interrupt Enable Register */ - AT91_REG PIO_IDR; /* Interrupt Disable Register */ - AT91_REG PIO_IMR; /* Interrupt Mask Register */ - AT91_REG PIO_ISR; /* Interrupt Status Register */ - AT91_REG PIO_MDER; /* Multi-driver Enable Register */ - AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ - AT91_REG PIO_MDSR; /* Multi-driver Status Register */ - AT91_REG Reserved3[1]; /* */ - AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ - AT91_REG PIO_PPUER; /* Pull-up Enable Register */ - AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ - AT91_REG Reserved4[1]; /* */ - AT91_REG PIO_ASR; /* Select A Register */ - AT91_REG PIO_BSR; /* Select B Register */ - AT91_REG PIO_ABSR; /* AB Select Status Register */ - AT91_REG Reserved5[9]; /* */ - AT91_REG PIO_OWER; /* Output Write Enable Register */ - AT91_REG PIO_OWDR; /* Output Write Disable Register */ - AT91_REG PIO_OWSR; /* Output Write Status Register */ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[1]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[1]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[1]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[1]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ + AT91_REG Reserved4[1]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[9]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ } AT91S_PIO, *AT91PS_PIO; -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Debug Unit */ -/*****************************************************************************/ +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/******************************************************************************/ typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; /* Control Register */ - AT91_REG DBGU_MR; /* Mode Register */ - AT91_REG DBGU_IER; /* Interrupt Enable Register */ - AT91_REG DBGU_IDR; /* Interrupt Disable Register */ - AT91_REG DBGU_IMR; /* Interrupt Mask Register */ - AT91_REG DBGU_CSR; /* Channel Status Register */ - AT91_REG DBGU_RHR; /* Receiver Holding Register */ - AT91_REG DBGU_THR; /* Transmitter Holding Register */ - AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ - AT91_REG Reserved0[7]; /* */ - AT91_REG DBGU_C1R; /* Chip ID1 Register */ - AT91_REG DBGU_C2R; /* Chip ID2 Register */ - AT91_REG DBGU_FNTR; /* Force NTRST Register */ - AT91_REG Reserved1[45]; /* */ - AT91_REG DBGU_RPR; /* Receive Pointer Register */ - AT91_REG DBGU_RCR; /* Receive Counter Register */ - AT91_REG DBGU_TPR; /* Transmit Pointer Register */ - AT91_REG DBGU_TCR; /* Transmit Counter Register */ - AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ - AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ - AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ - AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ - AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ - AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[7]; /* */ + AT91_REG DBGU_C1R; /* Chip ID1 Register */ + AT91_REG DBGU_C2R; /* Chip ID2 Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[45]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ } AT91S_DBGU, *AT91PS_DBGU; /* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ @@ -243,12 +242,12 @@ typedef struct _AT91S_DBGU #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ -/*****************************************************************************/ +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ +/******************************************************************************/ typedef struct _AT91S_SMC2 { - AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ + AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ } AT91S_SMC2, *AT91PS_SMC2; /* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ @@ -268,26 +267,26 @@ typedef struct _AT91S_SMC2 #define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ #define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Power Management Controler */ -/*****************************************************************************/ +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Power Management Controler */ +/******************************************************************************/ typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; /* System Clock Enable Register */ - AT91_REG PMC_SCDR; /* System Clock Disable Register */ - AT91_REG PMC_SCSR; /* System Clock Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ - AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ - AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ - AT91_REG Reserved1[5]; /* */ - AT91_REG PMC_MCKR; /* Master Clock Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ - AT91_REG PMC_IER; /* Interrupt Enable Register */ - AT91_REG PMC_IDR; /* Interrupt Disable Register */ - AT91_REG PMC_SR; /* Status Register */ - AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[1]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[5]; /* */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved2[3]; /* */ + AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ } AT91S_PMC, *AT91PS_PMC; /*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ @@ -342,54 +341,54 @@ typedef struct _AT91S_PMC /*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ /*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Ethernet MAC */ -/*****************************************************************************/ +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Ethernet MAC */ +/******************************************************************************/ typedef struct _AT91S_EMAC { - AT91_REG EMAC_CTL; /* Network Control Register */ - AT91_REG EMAC_CFG; /* Network Configuration Register */ - AT91_REG EMAC_SR; /* Network Status Register */ - AT91_REG EMAC_TAR; /* Transmit Address Register */ - AT91_REG EMAC_TCR; /* Transmit Control Register */ - AT91_REG EMAC_TSR; /* Transmit Status Register */ - AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ - AT91_REG Reserved0[1]; /* */ - AT91_REG EMAC_RSR; /* Receive Status Register */ - AT91_REG EMAC_ISR; /* Interrupt Status Register */ - AT91_REG EMAC_IER; /* Interrupt Enable Register */ - AT91_REG EMAC_IDR; /* Interrupt Disable Register */ - AT91_REG EMAC_IMR; /* Interrupt Mask Register */ - AT91_REG EMAC_MAN; /* PHY Maintenance Register */ - AT91_REG Reserved1[2]; /* */ - AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ - AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ - AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ - AT91_REG EMAC_OK; /* Frames Received OK Register */ - AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ - AT91_REG EMAC_ALE; /* Alignment Error Register */ - AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ - AT91_REG EMAC_LCOL; /* Late Collision Register */ - AT91_REG EMAC_ECOL; /* Excessive Collision Register */ - AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ - AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ - AT91_REG EMAC_CDE; /* Code Error Register */ - AT91_REG EMAC_ELR; /* Excessive Length Error Register */ - AT91_REG EMAC_RJB; /* Receive Jabber Register */ - AT91_REG EMAC_USF; /* Undersize Frame Register */ - AT91_REG EMAC_SQEE; /* SQE Test Error Register */ - AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ - AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ - AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ - AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ - AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ - AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ - AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ - AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ - AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ - AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ + AT91_REG EMAC_CTL; /* Network Control Register */ + AT91_REG EMAC_CFG; /* Network Configuration Register */ + AT91_REG EMAC_SR; /* Network Status Register */ + AT91_REG EMAC_TAR; /* Transmit Address Register */ + AT91_REG EMAC_TCR; /* Transmit Control Register */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG Reserved0[1]; /* */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG Reserved1[2]; /* */ + AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ + AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ + AT91_REG EMAC_OK; /* Frames Received OK Register */ + AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CDE; /* Code Error Register */ + AT91_REG EMAC_ELR; /* Excessive Length Error Register */ + AT91_REG EMAC_RJB; /* Receive Jabber Register */ + AT91_REG EMAC_USF; /* Undersize Frame Register */ + AT91_REG EMAC_SQEE; /* SQE Test Error Register */ + AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ + AT91_REG Reserved2[3]; /* */ + AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ + AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ } AT91S_EMAC, *AT91PS_EMAC; /* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */ @@ -425,11 +424,11 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ -/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */ +/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */ #define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ #define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ -/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */ +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */ #define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ #define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ @@ -443,7 +442,7 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ -/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */ +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ #define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ #define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ #define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ @@ -457,8 +456,8 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ #define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ -/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */ -/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */ +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ /* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ /* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ #define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ @@ -472,32 +471,32 @@ typedef struct _AT91S_EMAC #define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ #define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ -/*****************************************************************************/ +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/******************************************************************************/ typedef struct _AT91S_SPI { - AT91_REG SPI_CR; /* Control Register */ - AT91_REG SPI_MR; /* Mode Register */ - AT91_REG SPI_RDR; /* Receive Data Register */ - AT91_REG SPI_TDR; /* Transmit Data Register */ - AT91_REG SPI_SR; /* Status Register */ - AT91_REG SPI_IER; /* Interrupt Enable Register */ - AT91_REG SPI_IDR; /* Interrupt Disable Register */ - AT91_REG SPI_IMR; /* Interrupt Mask Register */ - AT91_REG Reserved0[4]; /* */ - AT91_REG SPI_CSR[4]; /* Chip Select Register */ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[4]; /* */ + AT91_REG SPI_CSR[4]; /* Chip Select Register */ AT91_REG Reserved1[48]; /* */ - AT91_REG SPI_RPR; /* Receive Pointer Register */ - AT91_REG SPI_RCR; /* Receive Counter Register */ - AT91_REG SPI_TPR; /* Transmit Pointer Register */ - AT91_REG SPI_TCR; /* Transmit Counter Register */ - AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ - AT91_REG SPI_RNCR; /* Receive Next Counter Register */ - AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ - AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ - AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ - AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ } AT91S_SPI, *AT91PS_SPI; /* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ @@ -537,7 +536,7 @@ typedef struct _AT91S_SPI #define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ /* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ /* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ #define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ @@ -556,21 +555,21 @@ typedef struct _AT91S_SPI #define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ #define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ -/*****************************************************************************/ -/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ -/*****************************************************************************/ +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ +/******************************************************************************/ typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; /* Receive Pointer Register */ - AT91_REG PDC_RCR; /* Receive Counter Register */ - AT91_REG PDC_TPR; /* Transmit Pointer Register */ - AT91_REG PDC_TCR; /* Transmit Counter Register */ - AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ - AT91_REG PDC_RNCR; /* Receive Next Counter Register */ - AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ - AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ - AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ - AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ } AT91S_PDC, *AT91PS_PDC; /* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ @@ -693,15 +692,11 @@ typedef struct _AT91S_PDC #define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ #define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB3 */ -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PB3 */ #define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */ #define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */ #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ #define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ #define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ @@ -742,44 +737,26 @@ typedef struct _AT91S_PDC #define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ #define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) /* (AIC) Base Address */ -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ -#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ -#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base Address */ -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ -#if 0 -#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */ -#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */ -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */ -#endif - -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */ -#if 0 -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */ -#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */ -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */ -#endif -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ -#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */ -#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */ #define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ - +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ #define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ +#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ #define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ #define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ #define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ #define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ #define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ -#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ +#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ -#endif /* __ASSEMBLY__ */ -#endif /* AT91RM9200_H */ +#endif diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h index b868e38a3..8bb0c4752 100644 --- a/include/asm-arm/arch-at91rm9200/hardware.h +++ b/include/asm-arm/arch-at91rm9200/hardware.h @@ -24,6 +24,8 @@ #ifndef __ASSEMBLY__ #include "AT91RM9200.h" +#else +#include "AT91RM9200_inc.h" #endif /* Virtual and Physical base address for system peripherals */ diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index ec94ba913..318de22a4 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -6,11 +6,11 @@ * */ -#define IO_ADDRESS(x) ((x) | IMX_IO_BASE) - # ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 *)IO_ADDRESS(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) +# define __REG(x) (*((volatile u32 *)(x))) +# define __REG2(x,y) \ + ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ + : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) # else # define __REG(x) (x) # define __REG2(x,y) ((x)+(y)) @@ -87,20 +87,14 @@ /* PLL registers */ #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ -#define CSCR_SPLL_RESTART (1<<22) -#define CSCR_MPLL_RESTART (1<<21) -#define CSCR_SYSTEM_SEL (1<<16) -#define CSCR_BCLK_DIV (0xf<<10) -#define CSCR_MPU_PRESC (1<<15) -#define CSCR_SPEN (1<<1) -#define CSCR_MPEN (1<<0) - #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ +#define CSCR_MPLL_RESTART (1<<21) + /* * GPIO Module and I/O Multiplexer * x = 0..3 for reg_A, reg_B, reg_C, reg_D @@ -123,12 +117,9 @@ #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) -#define GPIO_PORT_MAX 3 - #define GPIO_PIN_MASK 0x1f #define GPIO_PORT_MASK (0x3 << 5) -#define GPIO_PORT_SHIFT 5 #define GPIO_PORTA (0<<5) #define GPIO_PORTB (1<<5) #define GPIO_PORTC (2<<5) @@ -141,37 +132,24 @@ #define GPIO_PF (0<<9) #define GPIO_AF (1<<9) -#define GPIO_OCR_SHIFT 10 #define GPIO_OCR_MASK (3<<10) #define GPIO_AIN (0<<10) #define GPIO_BIN (1<<10) #define GPIO_CIN (2<<10) -#define GPIO_DR (3<<10) +#define GPIO_GPIO (3<<10) -#define GPIO_AOUT_SHIFT 12 -#define GPIO_AOUT_MASK (3<<12) -#define GPIO_AOUT (0<<12) -#define GPIO_AOUT_ISR (1<<12) -#define GPIO_AOUT_0 (2<<12) -#define GPIO_AOUT_1 (3<<12) - -#define GPIO_BOUT_SHIFT 14 -#define GPIO_BOUT_MASK (3<<14) -#define GPIO_BOUT (0<<14) -#define GPIO_BOUT_ISR (1<<14) -#define GPIO_BOUT_0 (2<<14) -#define GPIO_BOUT_1 (3<<14) - -#define GPIO_GIUS (1<<16) +#define GPIO_AOUT (1<<12) +#define GPIO_BOUT (1<<13) /* assignements for GPIO alternate/primary functions */ /* FIXME: This list is not completed. The correct directions are * missing on some (many) pins */ -#define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 ) +#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) +#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) -#define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 ) +#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) @@ -189,7 +167,7 @@ #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) -#define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 ) +#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) @@ -218,11 +196,11 @@ #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) -#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 ) +#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 ) #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) -#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 ) +#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 ) #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) -#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 ) +#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 ) #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) @@ -257,27 +235,19 @@ #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) -#define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 ) -#define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 ) -#define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 ) -#define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 ) -#define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 ) -#define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 ) -#define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 ) -#define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31) #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) -#define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) -#define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 ) +#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) +#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) -#define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 ) +#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) -#define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 ) +#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) -#define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 ) +#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) @@ -299,31 +269,7 @@ #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) -#define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 ) - -/* - * PWM controller - */ -#define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */ -#define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */ -#define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */ -#define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */ - -#define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */ -#define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */ -#define PWMC_SWR (0x01<<16) /* Software Reset */ -#define PWMC_CLKSRC (0x01<<15) /* Clock Source */ -#define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */ -#define PWMC_IRQ (0x01<< 7) /* Interrupt Request */ -#define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */ -#define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */ -#define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */ -#define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ -#define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */ - -#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ -#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ -#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ +#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) /* * DMA Controller @@ -345,7 +291,7 @@ #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ -#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ +#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */ #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ @@ -455,11 +401,8 @@ #define POS_POS(x) ((x) & 1f) #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) -#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) -#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) -#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) -#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) -#define LSCR1_GRAY1(x) (((x) & 0xf)) +#define LSCR1_GRAY1(x) (((x) & 0xf) << 4) +#define LSCR1_GRAY2(x) ((x) & 0xf) #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) #define PWMR_CLS(x) (((x) & 0x1ff) << 16) @@ -535,9 +478,9 @@ #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ #define UCR1_DOZE (1<<1) /* Doze */ #define UCR1_UARTEN (1<<0) /* UART enabled */ -#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ -#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ -#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ #define UCR2_CTS (1<<12) /* Clear to send */ #define UCR2_ESCEN (1<<11) /* Escape enable */ #define UCR2_PREN (1<<8) /* Parity enable */ @@ -547,8 +490,8 @@ #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ #define UCR2_TXEN (1<<2) /* Transmitter enabled */ #define UCR2_RXEN (1<<1) /* Receiver enabled */ -#define UCR2_SRST (1<<0) /* SW reset */ -#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ #define UCR3_PARERREN (1<<12) /* Parity enable */ #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ #define UCR3_DSR (1<<10) /* Data set ready */ @@ -558,51 +501,51 @@ #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ -#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ -#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ -#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ -#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ -#define UCR4_INVR (1<<9) /* Inverted infrared reception */ -#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ -#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ -#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ -#define UCR4_IRSC (1<<5) /* IR special case */ -#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ -#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ -#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ -#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ -#define USR1_RTSS (1<<14) /* RTS pin status */ -#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ -#define USR1_RTSD (1<<12) /* RTS delta */ -#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ -#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ -#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ -#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ -#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ -#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ -#define USR2_IDLE (1<<12) /* Idle condition */ -#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ -#define USR2_WAKE (1<<7) /* Wake */ -#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ -#define USR2_TXDC (1<<3) /* Transmitter complete */ -#define USR2_BRCD (1<<2) /* Break condition */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ #define USR2_ORE (1<<1) /* Overrun error */ #define USR2_RDR (1<<0) /* Recv data ready */ #define UTS_FRCPERR (1<<13) /* Force parity error */ #define UTS_LOOP (1<<12) /* Loop tx and rx */ #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ -#define UTS_TXFULL (1<<4) /* TxFIFO full */ -#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ #define UTS_SOFTRST (1<<0) /* Software reset */ /* General purpose timers registers */ diff --git a/include/asm-arm/arch-ixp/ixp425.h b/include/asm-arm/arch-ixp/ixp425.h index 2114437dc..11dc356a9 100644 --- a/include/asm-arm/arch-ixp/ixp425.h +++ b/include/asm-arm/arch-ixp/ixp425.h @@ -53,13 +53,13 @@ * * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr * - * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG + * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG * * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG * * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL * - * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG + * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG */ /* @@ -171,17 +171,17 @@ #define IXP425_SDR_REFRESH_OFFSET 0x04 #define IXP425_SDR_IR_OFFSET 0x08 -#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) +#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) #define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET) -#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) -#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) +#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) +#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) /* * UART registers */ -#define IXP425_UART1 0 -#define IXP425_UART2 0x1000 +#define IXP425_UART1 0 +#define IXP425_UART2 0x1000 #define IXP425_UART_RBR_OFFSET 0x00 #define IXP425_UART_THR_OFFSET 0x00 @@ -476,49 +476,49 @@ */ /* CSR bit definitions */ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) +#define PCI_CSR_HOST BIT(0) +#define PCI_CSR_ARBEN BIT(1) +#define PCI_CSR_ADS BIT(2) +#define PCI_CSR_PDS BIT(3) +#define PCI_CSR_ABE BIT(4) +#define PCI_CSR_DBT BIT(5) +#define PCI_CSR_ASE BIT(8) +#define PCI_CSR_IC BIT(15) /* ISR (Interrupt status) Register bit definitions */ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) +#define PCI_ISR_PSE BIT(0) +#define PCI_ISR_PFE BIT(1) +#define PCI_ISR_PPE BIT(2) +#define PCI_ISR_AHBE BIT(3) +#define PCI_ISR_APDC BIT(4) +#define PCI_ISR_PADC BIT(5) +#define PCI_ISR_ADB BIT(6) +#define PCI_ISR_PDB BIT(7) /* INTEN (Interrupt Enable) Register bit definitions */ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) +#define PCI_INTEN_PSE BIT(0) +#define PCI_INTEN_PFE BIT(1) +#define PCI_INTEN_PPE BIT(2) +#define PCI_INTEN_AHBE BIT(3) +#define PCI_INTEN_APDC BIT(4) +#define PCI_INTEN_PADC BIT(5) +#define PCI_INTEN_ADB BIT(6) +#define PCI_INTEN_PDB BIT(7) /* * Shift value for byte enable on NP cmd/byte enable register */ -#define IXP425_PCI_NP_CBE_BESL 4 +#define IXP425_PCI_NP_CBE_BESL 4 /* * PCI commands supported by NP access unit */ -#define NP_CMD_IOREAD 0x2 -#define NP_CMD_IOWRITE 0x3 -#define NP_CMD_CONFIGREAD 0xa -#define NP_CMD_CONFIGWRITE 0xb -#define NP_CMD_MEMREAD 0x6 -#define NP_CMD_MEMWRITE 0x7 +#define NP_CMD_IOREAD 0x2 +#define NP_CMD_IOWRITE 0x3 +#define NP_CMD_CONFIGREAD 0xa +#define NP_CMD_CONFIGWRITE 0xb +#define NP_CMD_MEMREAD 0x6 +#define NP_CMD_MEMWRITE 0x7 #if 0 #ifndef __ASSEMBLY__ diff --git a/include/asm-arm/arch-omap3/bits.h b/include/asm-arm/arch-omap3/bits.h new file mode 100644 index 000000000..8522335bf --- /dev/null +++ b/include/asm-arm/arch-omap3/bits.h @@ -0,0 +1,48 @@ +/* bits.h + * Copyright (c) 2004 Texas Instruments + * + * This package is free software; you can redistribute it and/or + * modify it under the terms of the license found in the file + * named COPYING that should have accompanied this file. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif diff --git a/include/asm-arm/arch-omap3/clocks.h b/include/asm-arm/arch-omap3/clocks.h new file mode 100644 index 000000000..a942e69ab --- /dev/null +++ b/include/asm-arm/arch-omap3/clocks.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP34XX_CLOCKS_H_ +#define _OMAP34XX_CLOCKS_H_ + +#define LDELAY 12000000 + +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#include + +#endif diff --git a/include/asm-arm/arch-omap3/clocks343x.h b/include/asm-arm/arch-omap3/clocks343x.h new file mode 100644 index 000000000..51e6acd8c --- /dev/null +++ b/include/asm-arm/arch-omap3/clocks343x.h @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP343X_CLOCKS_H_ +#define _OMAP343X_CLOCKS_H_ + +#define PLL_STOP 1 /* PER & IVA */ +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ + +/* The following configurations are OPP and SysClk value independant + * and hence are defined here. All the other DPLL related values are + * tabulated in lowlevel_init.S. + */ + +/* CORE DPLL */ +# define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ +# define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ +# define CORE_FUSB_DIV 2 /* 41.5MHz: */ +# define CORE_L4_DIV 2 /* 83MHz : L4 */ +# define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ +# define GFX_DIV 0 /* 110MHz : CM_CLKSEL_GFX */ +# define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ + +/* PER DPLL */ +# define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ +# define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ +# define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ +# define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ + +# define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) + +#ifdef PRCM_CLK_CFG2_332MHZ +# define M_12 0xA6 +# define N_12 0x05 +# define FSEL_12 0x07 +# define M2_12 0x01 /* M3 of 2 */ + +# define M_12_ES1 0x0E +# define FSL_12_ES1 0x03 +# define M2_12_ES1 0x1 /* M3 of 2 */ + +# define M_13 0x14C +# define N_13 0x0C +# define FSEL_13 0x03 +# define M2_13 0x01 /* M3 of 2 */ + +# define M_13_ES1 0x1B2 +# define N_13_ES1 0x10 +# define FSL_13_ES1 0x03 +# define M2_13_ES1 0x01 /* M3 of 2 */ + +# define M_19p2 0x19F +# define N_19p2 0x17 +# define FSEL_19p2 0x03 +# define M2_19p2 0x01 /* M3 of 2 */ + +# define M_19p2_ES1 0x19F +# define N_19p2_ES1 0x17 +# define FSL_19p2_ES1 0x03 +# define M2_19p2_ES1 0x01 /* M3 of 2 */ + +# define M_26 0xA6 +# define N_26 0x0C +# define FSEL_26 0x07 +# define M2_26 0x01 /* M3 of 2 */ + +# define M_26_ES1 0x1B2 +# define N_26_ES1 0x21 +# define FSL_26_ES1 0x03 +# define M2_26_ES1 0x01 /* M3 of 2 */ + +# define M_38p4 0x19F +# define N_38p4 0x2F +# define FSEL_38p4 0x03 +# define M2_38p4 0x01 /* M3 of 2 */ + +# define M_38p4_ES1 0x19F +# define N_38p4_ES1 0x2F +# define FSL_38p4_ES1 0x03 +# define M2_38p4_ES1 0x01 /* M3 of 2 */ + +#elif defined(PRCM_CLK_CFG2_266MHZ) +# define M_12 0x85 +# define N_12 0x05 +# define FSEL_12 0x07 +# define M2_12 0x02 /* M3 of 2 */ + +# define M_12_ES1 0x85 /* 0x10A */ +# define N_12_ES1 0x05 /* 0x05 */ +# define FSL_12_ES1 0x07 /* 0x7 */ +# define M2_12_ES1 0x2 /* 0x2 with an M3 of 4*/ + +# define M_13 0x10A +# define N_13 0x0C +# define FSEL_13 0x3 +# define M2_13 0x1 /* M3 of 2 */ + +# define M_13_ES1 0x10A /* 0x214 */ +# define N_13_ES1 0x0C /* 0xC */ +# define FSL_13_ES1 0x3 /* 0x3 */ +# define M2_13_ES1 0x1 /* 0x2 with an M3 of 4*/ + +# define M_19p2 0x115 +# define N_19p2 0x13 +# define FSEL_19p2 0x03 +# define M2_19p2 0x01 /* M3 of 2 */ + +# define M_19p2_ES1 0x115 /* 0x299 */ +# define N_19p2_ES1 0x13 /* 0x17 */ +# define FSL_19p2_ES1 0x03 /* 0x03 */ +# define M2_19p2_ES1 0x01 /* 0x2 with M3 of 4 */ + +# define M_26 0x85 +# define N_26 0x0C +# define FSEL_26 0x07 +# define M2_26 0x01 /* M3 of 2 */ + +# define M_26_ES1 0x85 /* 0x10A */ +# define N_26_ES1 0x0C /* 0xC */ +# define FSL_26_ES1 0x07 /* 0x7 */ +# define M2_26_ES1 0x01 /* 0x2 with an M3 of 4 */ + +# define M_38p4 0x11C +# define N_38p4 0x28 +# define FSEL_38p4 0x03 +# define M2_38p4 0x01 /* M3 of 2 */ + +# define M_38p4_ES1 0x11C /* 0x299 */ +# define N_38p4_ES1 0x28 /* 0x2f */ +# define FSL_38p4_ES1 0x03 /* 0x3 */ +# define M2_38p4_ES1 0x01 /* 0x2 with an M3 of 4*/ + +#endif + +#endif /* endif _OMAP343X_CLOCKS_H_ */ diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h new file mode 100644 index 000000000..f69d508ef --- /dev/null +++ b/include/asm-arm/arch-omap3/cpu.h @@ -0,0 +1,275 @@ +/* + * (C) Copyright 2006 - 2009 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _OMAP34XX_CPU_H +#define _OMAP34XX_CPU_H +#include + +/* Register offsets of common modules */ +/* Control */ +#define CONTROL_STATUS (OMAP34XX_CTRL_BASE + 0x2F0) +#define OMAP34XX_MCR (OMAP34XX_CTRL_BASE + 0x8C) +#define CONTROL_SCALABLE_OMAP_STATUS (OMAP34XX_CTRL_BASE + 0x44C) +#define CONTROL_SCALABLE_OMAP_OCP (OMAP34XX_CTRL_BASE + 0x534) + +#define OMAP34XX_ID_L4_IO_BASE 0x4830A200 +#ifndef __ASSEMBLY__ +typedef struct ctrl_id { + unsigned char res1[0x4]; + unsigned int idcode; /* 0x04 */ + unsigned int prod_id; /* 0x08 */ + unsigned char res2[0x0C]; + unsigned int die_id_0; /* 0x18 */ + unsigned int die_id_1; /* 0x1C */ + unsigned int die_id_2; /* 0x20 */ + unsigned int die_id_3; /* 0x24 */ +} ctrl_id_t; +#endif /* __ASSEMBLY__ */ + +/* Tap Information */ +#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE+0x204) +#define PRODUCTION_ID (OMAP34XX_TAP_BASE+0x208) + +/* device type */ +#define DEVICE_MASK (BIT8|BIT9|BIT10) +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* GPMC CS3/cs4/cs6 not avaliable */ +#define GPMC_BASE (OMAP34XX_GPMC_BASE) +#define GPMC_SYSCONFIG (OMAP34XX_GPMC_BASE+0x10) +#define GPMC_IRQSTATUS (OMAP34XX_GPMC_BASE+0x18) +#define GPMC_IRQENABLE (OMAP34XX_GPMC_BASE+0x1C) +#define GPMC_TIMEOUT_CONTROL (OMAP34XX_GPMC_BASE+0x40) +#define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50) +#define GPMC_STATUS (OMAP34XX_GPMC_BASE+0x54) + +#define GPMC_CONFIG_CS0 (OMAP34XX_GPMC_BASE+0x60) +#define GPMC_CONFIG_WIDTH (0x30) + +#define GPMC_CONFIG1 (0x00) +#define GPMC_CONFIG2 (0x04) +#define GPMC_CONFIG3 (0x08) +#define GPMC_CONFIG4 (0x0C) +#define GPMC_CONFIG5 (0x10) +#define GPMC_CONFIG6 (0x14) +#define GPMC_CONFIG7 (0x18) +#define GPMC_NAND_CMD (0x1C) +#define GPMC_NAND_ADR (0x20) +#define GPMC_NAND_DAT (0x24) + +#define GPMC_ECC_CONFIG (0x1F4) +#define GPMC_ECC_CONTROL (0x1F8) +#define GPMC_ECC_SIZE_CONFIG (0x1FC) +#define GPMC_ECC1_RESULT (0x200) +#define GPMC_ECC2_RESULT (0x204) +#define GPMC_ECC3_RESULT (0x208) +#define GPMC_ECC4_RESULT (0x20C) +#define GPMC_ECC5_RESULT (0x210) +#define GPMC_ECC6_RESULT (0x214) +#define GPMC_ECC7_RESULT (0x218) +#define GPMC_ECC8_RESULT (0x21C) +#define GPMC_ECC9_RESULT (0x220) + +#define GPMC_PREFETCH_CONFIG1 (0x1e0) +#define GPMC_PREFETCH_CONFIG2 (0x1e4) +#define GPMC_PREFETCH_CONTROL (0x1ec) +#define GPMC_PREFETCH_STATUS (0x1f0) + +/* GPMC Mapping */ +# define FLASH_BASE 0x10000000 /* NOR flash (aligned to 256 Meg) */ +# define FLASH_BASE_SDPV1 0x04000000 /* NOR flash (aligned to 64 Meg) */ +# define FLASH_BASE_SDPV2 0x10000000 /* NOR flash (aligned to 256 Meg) */ +# define DEBUG_BASE 0x08000000 /* debug board */ +# define NAND_BASE 0x30000000 /* NAND addr (actual size small port)*/ +# define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ +# define ONENAND_MAP 0x20000000 /* OneNand addr (actual size small port */ +# define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom2 Serial chip address */ + +/* SMS */ +#define SMS_SYSCONFIG (OMAP34XX_SMS_BASE+0x10) +#define SMS_RG_ATT0 (OMAP34XX_SMS_BASE+0x48) +#define SMS_CLASS_ARB0 (OMAP34XX_SMS_BASE+0xD0) +#define BURSTCOMPLETE_GROUP7 BIT31 + +/* SDRC */ +#define SDRC_SYSCONFIG (OMAP34XX_SDRC_BASE+0x10) +#define SDRC_STATUS (OMAP34XX_SDRC_BASE+0x14) +#define SDRC_CS_CFG (OMAP34XX_SDRC_BASE+0x40) +#define SDRC_SHARING (OMAP34XX_SDRC_BASE+0x44) +#define SDRC_DLLA_CTRL (OMAP34XX_SDRC_BASE+0x60) +#define SDRC_DLLA_STATUS (OMAP34XX_SDRC_BASE+0x64) +#define SDRC_DLLB_CTRL (OMAP34XX_SDRC_BASE+0x68) +#define SDRC_DLLB_STATUS (OMAP34XX_SDRC_BASE+0x6C) +#define DLLPHASE BIT1 +#define LOADDLL BIT2 +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK (BIT8|BIT9) + +#define SDRC_POWER (OMAP34XX_SDRC_BASE+0x70) +#define WAKEUPPROC BIT26 + +#define SDRC_MCFG_0 (OMAP34XX_SDRC_BASE+0x80) +#define SDRC_MCFG_1 (OMAP34XX_SDRC_BASE+0x80 + 0x30) +#define SDRC_MR_0 (OMAP34XX_SDRC_BASE+0x84) +#define SDRC_MR_1 (OMAP34XX_SDRC_BASE+0x84 + 0x30) +#define SDRC_EMR2_0 (OMAP34XX_SDRC_BASE+0x8C) +#define SDRC_EMR2_1 (OMAP34XX_SDRC_BASE+0x8C + 0x30) +#define SDRC_ACTIM_CTRLA_0 (OMAP34XX_SDRC_BASE+0x9C) +#define SDRC_ACTIM_CTRLA_1 (OMAP34XX_SDRC_BASE+0x9C + 0x28) +#define SDRC_ACTIM_CTRLB_0 (OMAP34XX_SDRC_BASE+0xA0) +#define SDRC_ACTIM_CTRLB_1 (OMAP34XX_SDRC_BASE+0xA0 + 0x28) +#define SDRC_RFR_CTRL_0 (OMAP34XX_SDRC_BASE+0xA4) +#define SDRC_RFR_CTRL_1 (OMAP34XX_SDRC_BASE + 0xA4 + 0x30) +#define SDRC_MANUAL_0 (OMAP34XX_SDRC_BASE+0xA8) +#define SDRC_MANUAL_1 (OMAP34XX_SDRC_BASE+0xA8 + 0x30) +#define OMAP34XX_SDRC_CS0 0x80000000 +#define OMAP34XX_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET BIT1 +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +/* timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ +#define GPT_EN ((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */ + +/* Watchdog */ +#define WWPS 0x34 /* r */ +#define WSPR 0x48 /* rw */ +#define WLDR 0x2c /* rw */ +#define WTGR 0x30 /* rw */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define CM_FCLKEN_IVA2 0x48004000 +#define CM_CLKEN_PLL_IVA2 0x48004004 +#define CM_IDLEST_PLL_IVA2 0x48004024 +#define CM_CLKSEL1_PLL_IVA2 0x48004040 +#define CM_CLKSEL2_PLL_IVA2 0x48004044 +#define CM_CLKEN_PLL_MPU 0x48004904 +#define CM_IDLEST_PLL_MPU 0x48004924 +#define CM_CLKSEL1_PLL_MPU 0x48004940 +#define CM_CLKSEL2_PLL_MPU 0x48004944 +#define CM_FCLKEN1_CORE 0x48004a00 +#define CM_ICLKEN1_CORE 0x48004a10 +#define CM_ICLKEN2_CORE 0x48004a14 +#define CM_IDLEST1_CORE 0x48004a20 +#define CM_AUTOIDLE1_CORE 0x48004a30 +#define CM_CLKSEL_CORE 0x48004a40 +#define CM_FCLKEN_GFX 0x48004b00 +#define CM_ICLKEN_GFX 0x48004b10 +#define CM_CLKSEL_GFX 0x48004b40 +#define CM_FCLKEN_WKUP 0x48004c00 +#define CM_ICLKEN_WKUP 0x48004c10 +#define CM_CLKSEL_WKUP 0x48004c40 +#define CM_IDLEST_WKUP 0x48004c20 +#define CM_CLKEN_PLL 0x48004d00 +#define CM_IDLEST_CKGEN 0x48004d20 +#define CM_CLKSEL1_PLL 0x48004d40 +#define CM_CLKSEL2_PLL 0x48004d44 +#define CM_CLKSEL3_PLL 0x48004d48 +#define CM_FCLKEN_DSS 0x48004e00 +#define CM_ICLKEN_DSS 0x48004e10 +#define CM_CLKSEL_DSS 0x48004e40 +#define CM_FCLKEN_CAM 0x48004f00 +#define CM_ICLKEN_CAM 0x48004f10 +#define CM_CLKSEL_CAM 0x48004F40 +#define CM_FCLKEN_PER 0x48005000 +#define CM_ICLKEN_PER 0x48005010 +#define CM_CLKSEL_PER 0x48005040 +#define CM_CLKSEL1_EMU 0x48005140 + +#define PRM_CLKSEL 0x48306d40 +#define PRM_RSTCTRL 0x48307250 +#define PRM_CLKSRC_CTRL 0x48307270 +#define PRM_RSTTST 0x48307258 + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12C00) +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) +#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) +#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) +#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) + +#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) +#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) +#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) + +#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) +#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) +#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) +#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) + +#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) +#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) +#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) + +#define IVA2_REQ_INFO_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x68) +#define IVA2_READ_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x70) +#define IVA2_WRITE_PERMISSION_1 (PM_IVA2_BASE_ADDR_ARM + 0x78) + +#define IVA2_REQ_INFO_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x88) +#define IVA2_READ_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x90) +#define IVA2_WRITE_PERMISSION_2 (PM_IVA2_BASE_ADDR_ARM + 0x98) + +#define IVA2_REQ_INFO_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xA8) +#define IVA2_READ_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB0) +#define IVA2_WRITE_PERMISSION_3 (PM_IVA2_BASE_ADDR_ARM + 0xB8) + +/* I2C base */ +#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) +#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) +#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) + +#endif diff --git a/include/asm-arm/arch-omap3/dpll_table_34xx.S b/include/asm-arm/arch-omap3/dpll_table_34xx.S new file mode 100644 index 000000000..55b372918 --- /dev/null +++ b/include/asm-arm/arch-omap3/dpll_table_34xx.S @@ -0,0 +1,175 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +mpu_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x0FE,0x07,0x05,0x01 +/* ES2 */ +.word 0x0FA,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x17D,0x0C,0x03,0x01 +/* ES2 */ +.word 0x1F4,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x179,0x12,0x04,0x01 +/* ES2 */ +.word 0x271,0x17,0x03,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x17D,0x19,0x03,0x01 +/* ES2 */ +.word 0x0FA,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x1FA,0x32,0x03,0x01 +/* ES2 */ +.word 0x271,0x2F,0x03,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +iva_dpll_param: +/* 12MHz */ +/* ES1 */ +.word 0x07D,0x05,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x05,0x07,0x01 +/* 3410 */ +.word 0x085,0x05,0x07,0x01 + +/* 13MHz */ +/* ES1 */ +.word 0x0FA,0x0C,0x03,0x01 +/* ES2 */ +.word 0x168,0x0C,0x03,0x01 +/* 3410 */ +.word 0x10A,0x0C,0x03,0x01 + +/* 19.2MHz */ +/* ES1 */ +.word 0x082,0x09,0x07,0x01 +/* ES2 */ +.word 0x0E1,0x0B,0x06,0x01 +/* 3410 */ +.word 0x14C,0x17,0x03,0x01 + +/* 26MHz */ +/* ES1 */ +.word 0x07D,0x0C,0x07,0x01 +/* ES2 */ +.word 0x0B4,0x0C,0x07,0x01 +/* 3410 */ +.word 0x085,0x0C,0x07,0x01 + +/* 38.4MHz */ +/* ES1 */ +.word 0x13F,0x30,0x03,0x01 +/* ES2 */ +.word 0x0E1,0x17,0x06,0x01 +/* 3410 */ +.word 0x14C,0x2F,0x03,0x01 + + +/* Core DPLL targets for L3 at 166 & L133 */ +core_dpll_param: +/* 12MHz */ +/* ES1 */ +.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1 +/* ES2 */ +.word M_12,N_12,FSEL_12,M2_12 +/* 3410 */ +.word M_12,N_12,FSEL_12,M2_12 + +/* 13MHz */ +/* ES1 */ +.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1 +/* ES2 */ +.word M_13,N_13,FSEL_13,M2_13 +/* 3410 */ +.word M_13,N_13,FSEL_13,M2_13 + +/* 19.2MHz */ +/* ES1 */ +.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1 +/* ES2 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 +/* 3410 */ +.word M_19p2,N_19p2,FSEL_19p2,M2_19p2 + +/* 26MHz */ +/* ES1 */ +.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1 +/* ES2 */ +.word M_26,N_26,FSEL_26,M2_26 +/* 3410 */ +.word M_26,N_26,FSEL_26,M2_26 + +/* 38.4MHz */ +/* ES1 */ +.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1 +/* ES2 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 +/* 3410 */ +.word M_38p4,N_38p4,FSEL_38p4,M2_38p4 + +/* PER DPLL values are same for both ES1 and ES2 */ +per_dpll_param: +/* 12MHz */ +.word 0xD8,0x05,0x07,0x09 + +/* 13MHz */ +.word 0x1B0,0x0C,0x03,0x09 + +/* 19.2MHz */ +.word 0xE1,0x09,0x07,0x09 + +/* 26MHz */ +.word 0xD8,0x0C,0x07,0x09 + +/* 38.4MHz */ +.word 0xE1,0x13,0x07,0x09 + diff --git a/include/asm-arm/arch-omap3/dpll_table_36xx.S b/include/asm-arm/arch-omap3/dpll_table_36xx.S new file mode 100644 index 000000000..cb7805b0d --- /dev/null +++ b/include/asm-arm/arch-omap3/dpll_table_36xx.S @@ -0,0 +1,118 @@ +/* + * Board specific setup info + * + * (C) Copyright 2009 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* DPLL(1-4) PARAM TABLES */ +/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal + * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). + * The values are defined for all possible sysclk and for ES1 and ES2. + */ + +/* WARNING : Only the 26MHz timing has been tested */ + +/* Vdd1 = 1.20 for mpu and iva default */ + +mpu_dpll_param: +/* 12MHz */ +.word 50, 0, 0, 1 +/* 13MHz */ +.word 600, 12, 0, 1 +/* 19.2MHz */ +.word 125, 3, 0, 1 +/* 26MHz */ +.word 300, 12, 0, 1 +/* 38.4MHz */ +.word 125, 7, 0, 1 + +iva_dpll_param: +/* 12MHz */ +.word 130, 2, 0, 1 +/* 13MHz */ +.word 40, 0, 0, 1 +/* 19.2MHz */ +.word 325, 11, 0, 1 +/* 26MHz */ +.word 20, 0, 0, 1 +/* 38.4MHz */ +.word 325, 23, 0, 1 + +#if defined(PRCM_CLK_CFG2_400MHZ) + +core_dpll_param: +/* 12MHz */ +.word 100, 2, 0, 1 +/* 13MHz */ +.word 400, 12, 0, 1 +/* 19.2MHz */ +.word 375, 17, 0, 1 +/* 26MHz */ +.word 200, 12, 0, 1 +/* 38.4MHz */ +.word 375, 35, 0, 1 + +#elif defined(PRCM_CLK_CFG2_332MHZ) + +core_dpll_param: +/* 12MHz */ +.word 83, 2, 0, 1 +/* 13MHz */ +.word 332, 12, 0, 1 +/* 19.2MHz */ +.word 514, 23, 0, 1 +/* 26MHz */ +.word 166, 12, 0, 1 +/* 38.4MHz */ +.word 415, 47, 0, 1 + +#else +#error "Undefined memory speed" +#endif /* PRCM_CLK_CFG2_* */ + + +per_dpll_param: +#if defined(CONFIG_PER_M2_192) +/* sys(kHz), m, n, clkin, sd, dco, m2, m3, m4, m5, m6, m2div */ +.word 12000, 720, 4, 0, 7, 4, 9, 32, 10, 8, 6, 1 +.word 13000, 864, 0, 1, 7, 4, 9, 32, 10, 8, 6, 1 +.word 19200, 720, 7, 0, 7, 4, 9, 32, 10, 8, 6, 1 +.word 26000, 864, 12, 0, 7, 4, 9, 32, 10, 8, 6, 1 +.word 38400, 720, 15, 0, 7, 4, 9, 32, 10, 8, 6, 1 +.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +#elif defined(CONFIG_PER_SGX_192) +/* sys(kHz), m, n, clkin, sd, dco, m2, m3, m4, m5, m6, m2div */ +.word 12000, 720, 4, 0, 7, 4, 9, 32, 10, 8, 6, 2 +.word 13000, 864, 0, 1, 7, 4, 9, 32, 10, 8, 6, 2 +.word 19200, 720, 7, 0, 7, 4, 9, 32, 10, 8, 6, 2 +.word 26000, 864, 12, 0, 7, 4, 9, 32, 10, 8, 6, 2 +.word 38400, 720, 15, 0, 7, 4, 9, 32, 10, 8, 6, 2 +.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +#else /* Default to 96 MHz M2 */ +/* sys(kHz), m, n, clkin, sd, dco, m2, m3, m4, m5, m6, m2div */ +.word 12000, 360, 4, 0, 4, 2, 9, 16, 5, 4, 3, 1 +.word 13000, 432, 0, 1, 4, 2, 9, 16, 5, 4, 3, 1 +.word 19200, 360, 7, 0, 4, 2, 9, 16, 5, 4, 3, 1 +.word 26000, 432, 12, 0, 4, 2, 9, 16, 5, 4, 3, 1 +.word 38400, 360, 15, 0, 4, 2, 9, 16, 5, 4, 3, 1 +.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +#endif diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h new file mode 100644 index 000000000..a89e6070c --- /dev/null +++ b/include/asm-arm/arch-omap3/i2c.h @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2004-2006 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP34XX_I2C_H_ +#define _OMAP34XX_I2C_H_ + +/* Get the i2c base addresses */ +#include + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#define I2C_REV (0x00) +#define I2C_IE (0x04) +#define I2C_STAT (0x08) +#define I2C_IV (0x0c) +#define I2C_SYSS (0x10) +#define I2C_BUF (0x14) +#define I2C_CNT (0x18) +#define I2C_DATA (0x1c) +#define I2C_SYSC (0x20) +#define I2C_CON (0x24) +#define I2C_OA (0x28) +#define I2C_SA (0x2c) +#define I2C_PSC (0x30) +#define I2C_SCLL (0x34) +#define I2C_SCLH (0x38) +#define I2C_SYSTEST (0x3c) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_GC_IE (1 << 5) +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_GC (1 << 5) +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ + +/* I2C Buffer Configuration Register (I2C_BUF): */ + +#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ + +/* I2C System Test Register (I2C_SYSTEST): */ + +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ +#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ + +/* I2C System Control Register (I2C_SYSC): */ + +#define I2C_SYSC_SRST (1 << 1) /* Software Reset */ + +/* I2C System Status Register (I2C_SYSS): */ + +#define I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ + + +#define I2C_SCLL_SCLL (0) +#define I2C_SCLL_SCLL_M (0xFF) +#define I2C_SCLL_HSSCLL (8) +#define I2C_SCLH_HSSCLL_M (0xFF) +#define I2C_SCLH_SCLH (0) +#define I2C_SCLH_SCLH_M (0xFF) +#define I2C_SCLH_HSSCLH (8) +#define I2C_SCLH_HSSCLH_M (0xFF) + +#define OMAP_I2C_STANDARD 100 +#define OMAP_I2C_FAST_MODE 400 +#define OMAP_I2C_HIGH_SPEED 3400 + +#define SYSTEM_CLOCK_12 12000 +#define SYSTEM_CLOCK_13 13000 +#define SYSTEM_CLOCK_192 19200 +#define SYSTEM_CLOCK_96 96000 + +#define I2C_IP_CLK SYSTEM_CLOCK_96 + +#ifndef I2C_IP_CLK +#define I2C_IP_CLK SYSTEM_CLOCK_96 +#endif + +/* Boards may want to define I2C_INTERNAL_SAMPLING_CLK */ + +/* These are the trim values for standard and fast speed */ +#ifndef I2C_FASTSPEED_SCLL_TRIM +#define I2C_FASTSPEED_SCLL_TRIM 7 +#endif +#ifndef I2C_FASTSPEED_SCLH_TRIM +#define I2C_FASTSPEED_SCLH_TRIM 5 +#endif + +/* These are the trim values for high speed */ +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM +#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM +#endif +#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM +#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM +#endif +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM +#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM +#endif +#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM +#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM +#endif + +#define I2C_PSC_MAX (0x0f) +#define I2C_PSC_MIN (0x00) + +#endif diff --git a/include/asm-arm/arch-omap3/led.h b/include/asm-arm/arch-omap3/led.h new file mode 100644 index 000000000..077484dc2 --- /dev/null +++ b/include/asm-arm/arch-omap3/led.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2009 + * Windriver, + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP3_LED_H +#define _OMAP3_LED_H + +#if defined (CONFIG_ZOOM2_LED) + +extern void omap3_zoom2_led_red_on(void); +extern void omap3_zoom2_led_red_off(void); +extern void omap3_zoom2_led_blue_on(void); +extern void omap3_zoom2_led_blue_off(void); +#if defined(CONFIG_3630ZOOM3) +extern void omap3_zoom2_led_green_on(void); +extern void omap3_zoom2_led_green_off(void); +#endif + +#define OMAP3_LED_OK_ON() omap3_zoom2_led_blue_on () +#define OMAP3_LED_OK_OFF() omap3_zoom2_led_blue_off () + +#if defined(CONFIG_3630ZOOM3) +#define OMAP3_LED_ERROR_ON() omap3_zoom2_led_green_on() +#define OMAP3_LED_ERROR_OFF() omap3_zoom2_led_green_off() +#elif defined(CONFIG_3430ZOOM2) & !defined(CONFIG_3630ZOOM3) +#define OMAP3_LED_ERROR_ON() omap3_zoom2_led_red_on () +#define OMAP3_LED_ERROR_OFF() omap3_zoom2_led_red_off() +#endif + +#endif /* CONFIG_ZOOM2_LED */ + +#ifndef OMAP3_LED_OK_ON +#define OMAP3_LED_OK_ON() +#endif +#ifndef OMAP3_LED_OK_OFF +#define OMAP3_LED_OK_OFF() +#endif +#ifndef OMAP3_LED_ERROR_ON +#define OMAP3_LED_ERROR_ON() +#endif +#ifndef OMAP3_LED_ERROR_OFF +#define OMAP3_LED_ERROR_OFF() +#endif + +#endif /* _OMAP3_LED_H */ diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h new file mode 100644 index 000000000..de8272fb3 --- /dev/null +++ b/include/asm-arm/arch-omap3/mem.h @@ -0,0 +1,777 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP34XX_MEM_H_ +#define _OMAP34XX_MEM_H_ + +#define MCFG_RAMTYPE_POS 0 +#define MCFG_DDRTYPE_POS 2 +#define MCFG_DEEPPD_POS 3 +#define MCFG_B32NOT16_POS 4 +#define MCFG_BANKALLOCATION_POS 6 +#define MCFG_RAMSIZE_POS 8 +#define MCFG_ADDRMUXLEGACY_POS 19 +#define MCFG_ADDRMUX_POS 20 +#define MCFG_CASWIDTH_POS 20 +#define MCFG_RASWIDTH_POS 24 +#define MCFG_LOCKSTATUS_POS 30 + +#define ACTIM_CTRLA_TDAL_POS 0 +#define ACTIM_CTRLA_TDPL_POS 6 +#define ACTIM_CTRLA_TRRD_POS 9 +#define ACTIM_CTRLA_TRCD_POS 12 +#define ACTIM_CTRLA_TRP_POS 15 +#define ACTIM_CTRLA_TRAS_POS 18 +#define ACTIM_CTRLA_TRC_POS 22 +#define ACTIM_CTRLA_TRFC_POS 27 + +#define ACTIM_CTRLB_TXSR_POS 0 +#define ACTIM_CTRLB_TXP_POS 8 +#define ACTIM_CTRLB_TCKE_POS 12 +#define ACTIM_CTRLB_TWTR_POS 16 + +#define SDRC_CS0_OSET 0x0 +#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ + +#ifndef __ASSEMBLY__ + +typedef enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR = 3, +} mem_t; + +#endif + +/* set the 343x-SDRC incoming address convention */ +#if defined(SDRC_B_R_C) +#define B_ALL (0 << 6) /* bank-row-column */ +#elif defined(SDRC_B1_R_B0_C) +#define B_ALL (1 << 6) /* bank1-row-bank0-column */ +#elif defined(SDRC_R_B_C) +#define B_ALL (2 << 6) /* row-bank-column */ +#endif + +/* Future memory combinations based on past */ +#define SDP_SDRC_MDCFG_MONO_DDR 0x0 +#define SDP_COMBO_MDCFG_0_DDR 0x0 +#define SDP_SDRC_MDCFG_0_SDR 0x0 + +/* Slower full frequency range default timings for x32 operation*/ +#define SDP_SDRC_SHARING 0x00000100 +#define SDP_SDRC_MR_0_SDR 0x00000031 + +#ifdef CONFIG_3430ZEBU +#define SDP_SDRC_MDCFG_0_DDR (0x02582019|B_ALL) /* Infin ddr module */ +#elif CONFIG_3430SDP +#define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) /* Infin ddr module */ +#define SDP_SDRC_MDCFG_0_DDR_2G (0x03588019|B_ALL) /* QIMONDA ddr module */ +#elif CONFIG_OMAP3_BEAGLE +#define SDP_SDRC_MDCFG_0_DDR (0x00D04019|B_ALL) /* Samsung MCP ddr module */ +#elif defined(CONFIG_3430ZOOM2_512M) ||\ + defined(CONFIG_3630ZOOM3) || defined(CONFIG_3630SDP) +#define SDP_SDRC_MDCFG_0_DDR (0x03588099) /* Hynix MCP ddr module */ +#elif defined(CONFIG_3630SDP_1G) || defined(CONFIG_3630ZOOM3_1G) +#define SDP_SDRC_MDCFG_0_DDR (0x03590099) /* Hynix MCP ddr module */ +#elif defined (CONFIG_SANTIAGO) || defined(CONFIG_MONOPOLI) || \ + defined(CONFIG_STRASBOURG) + +#if defined(__VARIANT_RENNES_B1) +#define SDP_SDRC_CS_CFG 4 +/* MT46H128M16: 512MB = 2 x 32Meg x 16 x 4 banks */ +#define SDP_SDRC_MDCFG_0_DDR ((3 << MCFG_RASWIDTH_POS) | /* RAS address width: 14 (A0-A13) */ \ + (6 << MCFG_CASWIDTH_POS) | /* CAS address width: 11 (A0-A9) (A11) */ \ + (1 << MCFG_ADDRMUXLEGACY_POS) | /* flexible address muxing */ \ + (256 << MCFG_RAMSIZE_POS) | /* 512MB */ \ + (2 << MCFG_BANKALLOCATION_POS) | /* row-bank-column */ \ + (1 << MCFG_B32NOT16_POS) | /* 32-bit RAM */ \ + (1 << MCFG_DEEPPD_POS) | /* deep-power-down supported */ \ + (0 << MCFG_DDRTYPE_POS) | /* mobile DDR */ \ + (1 << MCFG_RAMTYPE_POS)) /* DDR-SDRAM */ +#else /* __VARIANT_RENNES_B1 */ +#define SDP_SDRC_CS_CFG 2 +/* same settings for santiago (with MT46H64M32), monopoli (with K4X2G323PB) + and Strasbourg (K4X2G323PB or MT46H64M32) */ +#define SDP_SDRC_MDCFG_0_DDR ((3 << MCFG_RASWIDTH_POS) | /* RAS address width: 14 (A0-A13) */ \ + (5 << MCFG_CASWIDTH_POS) | /* CAS address width: 10 (A0-A9) */ \ + (1 << MCFG_ADDRMUXLEGACY_POS) | /* flexible address muxing */ \ + (128 << MCFG_RAMSIZE_POS) | /* 256MB */ \ + (2 << MCFG_BANKALLOCATION_POS) | /* row-bank-column */ \ + (1 << MCFG_B32NOT16_POS) | /* 32-bit RAM */ \ + (1 << MCFG_DEEPPD_POS) | /* deep-power-down supported */ \ + (0 << MCFG_DDRTYPE_POS) | /* mobile DDR */ \ + (1 << MCFG_RAMTYPE_POS)) /* DDR-SDRAM */ +#endif /* __VARIANT_RENNES_B1 */ +#endif + +#define SDP_SDRC_MR_0_DDR 0x00000032 + +#ifdef CONFIG_STRASBOURG +#define SDP_SDRC_EMR2_0_DDR 0x00000020 +#else +#define SDP_SDRC_EMR2_0_DDR 0x00000000 +#endif + +/* optimized timings good for current shipping parts */ +#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define ZOOM3_3630_RFR_CTRL_200MHz 0x0005e601 + +#define DLL_OFFSET 0 +#define DLL_WRITEDDRCLKX2DIS 1 +#define DLL_ENADLL 1 +#define DLL_LOCKDLL 0 +#define DLL_DLLPHASE_72 0 +#define DLL_DLLPHASE_90 1 + +#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ + (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) + +#if defined(CONFIG_3430LABRADOR) || defined(CONFIG_BEAGLE_REV2) +/* Micron part of 3430 Labrador (133MHz optimized) ~ 7.5ns + * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 + * TDPL = 15/7.5 = 2 + * TRRD = 15/7.5 = 2 + * TRCD = 22.5/7.5 = 3 + * TRP = 22.5/7.5 = 3 + * TRAS = 45/7.5 = 6 + * TRC = 75/7.5 = 10 + * TRFC = 125/7.5 = 16.6->17 + * ACTIMB + * TWTR = 1 + * TCKE = 1 + * TXSR = 138/7.5 = 18.3->19 + * TXP = 25/7.5 = 3.3->4 + */ +#define TDAL_133 5 +#define TDPL_133 2 +#define TRRD_133 2 +#define TRCD_133 3 +#define TRP_133 3 +#define TRAS_133 6 +#define TRC_133 10 +#define TRFC_133 17 +#define V_ACTIMA_133 ((TRFC_133 << 27) | (TRC_133 << 22) | (TRAS_133 << 18) \ + |(TRP_133 << 15) | (TRCD_133 << 12) |(TRRD_133 << 9) |(TDPL_133 << 6) \ + | (TDAL_133)) + +#define TWTR_133 1 +#define TCKE_133 1 +#define TXSR_133 19 +#define TXP_133 4 +#define V_ACTIMB_133 ((TWTR_133 << 16) | (TCKE_133 << 12) | (TXP_133 << 8) \ + | (TXSR_133 << 0)) +#else +/* Infineon part of 3430SDP (133MHz optimized) ~ 7.5ns + * TDAL = Twr/Tck + Trp/tck = 15/7.5 + 22.5/7.5 = 2 + 3 = 5 + * TDPL = 15/7.5 = 2 + * TRRD = 15/2.5 = 2 + * TRCD = 22.5/7.5 = 3 + * TRP = 22.5/7.5 = 3 + * TRAS = 45/7.5 = 6 + * TRC = 65/7.5 = 8.6->9 + * TRFC = 75/7.5 = 10 + * ACTIMB + * TWTR = 1 + * TCKE = 2 + * TXP = = 12/7.5=1.6=2 + * XSR = 120/7.5 = 16 + */ +#define TDAL_133 5 +#define TDPL_133 2 +#define TRRD_133 2 +#define TRCD_133 3 +#define TRP_133 3 +#define TRAS_133 6 +#define TRC_133 9 +#define TRFC_133 10 +#define V_ACTIMA_133 ((TRFC_133 << 27) | (TRC_133 << 22) | (TRAS_133 << 18) \ + |(TRP_133 << 15) | (TRCD_133 << 12) |(TRRD_133 << 9) |(TDPL_133 << 6) \ + | (TDAL_133)) + +#define TWTR_133 1 +#define TCKE_133 2 +#define TXP_133 2 +#define XSR_133 16 +#define V_ACTIMB_133 ((TCKE_133 << 12) | (XSR_133 << 0)) | \ + (TXP_133 << 8) | (TWTR_133 << 16) +#endif +#define V_ACTIMA_100 V_ACTIMA_133 +#define V_ACTIMB_100 V_ACTIMB_133 + +#if defined(CONFIG_3430LABRADOR) || defined(CONFIG_BEAGLE_REV2) +/* Micron part of 3430 Labrador (166MHz optimized) 6.02ns + * ACTIMA + * -TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 + * -TDPL (Twr) = 15/6 = 2.5 -> 3 + * -TRRD = 12/6 = 2 + * -TRCD = 18/6 = 3 + * -TRP = 18/6 = 3 + * -TRAS = 42/6 = 7 + * -TRC = 60/6 = 10 + * -TRFC = 125/6 = 20.8 -> 21 + * ACTIMB + * -TWTR = 1 + * -TCKE = 1 + * -TXP = 25/6 = 5 + * -XSR = 138/6 = 23 + */ +#define TDAL_165 6 +#define TDPL_165 3 +#define TRRD_165 2 +#define TRCD_165 3 +#define TRP_165 3 +#define TRAS_165 7 +#define TRC_165 10 +#define TRFC_165 21 +#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) \ + | (TRP_165 << 15) | (TRCD_165 << 12) |(TRRD_165 << 9) | \ + (TDPL_165 << 6) | (TDAL_165)) + +#define TWTR_165 1 +#define TCKE_165 1 +#define TXP_165 5 +#define XSR_165 23 +#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0)) | \ + (TXP_165 << 8) | (TWTR_165 << 16) + +#elif defined(CONFIG_3430ZOOM2_512M) ||\ + defined(CONFIG_3630ZOOM3) || defined(CONFIG_3630SDP)\ + || defined(CONFIG_3630SDP_1G) || defined(CONFIG_3630ZOOM3_1G) \ + || defined(CONFIG_3730OVERO) || (defined(CONFIG_STRASBOURG) && defined(DDR_MT46H64M32)) + +/* Hynix part of 3430 Zoom2 (166MHz optimized) 6.02ns + * ACTIMA + * -TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 + * -TDPL (Twr) = 15/6 = 2.5 -> 3 + * -TRRD = 12/6 = 2 + * -TRCD = 18/6 = 3 + * -TRP = 18/6 = 3 + * -TRAS = 42/6 = 7 + * -TRC = 60/6 = 10 + * -TRFC = 97.5/6 = 17 + * ACTIMB + * -TWTR = 1 + * -TCKE = 1 + * -TXP = 1+1 + * -XSR = 140/6 = 24 + */ +#define TDAL_165 6 +#define TDPL_165 3 +#define TRRD_165 2 +#define TRCD_165 3 +#define TRP_165 3 +#define TRAS_165 7 +#define TRC_165 10 +#define TRFC_165 21 +#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) |\ + (TRP_165 << 15) | (TRCD_165 << 12) | (TRRD_165 << 9) | \ + (TDPL_165 << 6) | (TDAL_165)) + +#define TWTR_165 1 +#define TCKE_165 1 +#define TXP_165 2 +#define XSR_165 24 +#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \ + (TXP_165 << 8) | (TWTR_165 << 16)) + +/* TODO : Cleanup magic */ +#define V_ACTIMA_200 0xa2e1b4c6 +#define V_ACTIMB_200 0x0002131c + +#elif defined (DDR_MT46H64M32) || defined (DDR_MT46H128M16) + +#if defined(PRCM_CLK_CFG2_400MHZ) + +/* DDR running at 200MHz */ + +#define SDP_SDRC_RFR_CTRL 0x0005e601 /* (7.8us / 5ns) - 50 */ + +#define V_ACTIMA_200 ((6 << ACTIM_CTRLA_TDAL_POS) | \ + (3 << ACTIM_CTRLA_TDPL_POS) | \ + (2 << ACTIM_CTRLA_TRRD_POS) | \ + (3 << ACTIM_CTRLA_TRCD_POS) | \ + (3 << ACTIM_CTRLA_TRP_POS) | \ + (8 << ACTIM_CTRLA_TRAS_POS) | \ + (11 << ACTIM_CTRLA_TRC_POS) | \ + (15 << ACTIM_CTRLA_TRFC_POS)) + +#define V_ACTIMB_200 ((23 << ACTIM_CTRLB_TXSR_POS) | \ + (2 << ACTIM_CTRLB_TXP_POS) | \ + (1 << ACTIM_CTRLB_TCKE_POS) | \ + (2 << ACTIM_CTRLB_TWTR_POS)) +#else +/* DDR running at 166MHz */ + +#define SDP_SDRC_RFR_CTRL 0x0004e201 /* (7.8us / 6ns) - 50 */ + +#define V_ACTIMA_165 ((6 << ACTIM_CTRLA_TDAL_POS) | \ + (3 << ACTIM_CTRLA_TDPL_POS) | \ + (2 << ACTIM_CTRLA_TRRD_POS) | \ + (3 << ACTIM_CTRLA_TRCD_POS) | \ + (3 << ACTIM_CTRLA_TRP_POS) | \ + (7 << ACTIM_CTRLA_TRAS_POS) | \ + (10 << ACTIM_CTRLA_TRC_POS) | \ + (12 << ACTIM_CTRLA_TRFC_POS)) + +#define V_ACTIMB_165 ((19 << ACTIM_CTRLB_TXSR_POS) | \ + (1 << ACTIM_CTRLB_TXP_POS) | \ + (1 << ACTIM_CTRLB_TCKE_POS) | \ + (1 << ACTIM_CTRLB_TWTR_POS)) +#endif + +#elif defined (DDR_K4X2G323PB) + +#if defined(PRCM_CLK_CFG2_332MHZ) +/* DDR running at 166MHz */ + +/* tREFI = (tREF / (2 ^ RASWIDTH)) = (64ms / (2 ^ 14)) = 3.906us */ +#define SDP_SDRC_RFR_CTRL 0x00025901 /* (3.906us / 6ns) - 50 */ + +#define V_ACTIMA_165 ((6 << ACTIM_CTRLA_TDAL_POS) | \ + (3 << ACTIM_CTRLA_TDPL_POS) | \ + (2 << ACTIM_CTRLA_TRRD_POS) | \ + (3 << ACTIM_CTRLA_TRCD_POS) | \ + (3 << ACTIM_CTRLA_TRP_POS) | \ + (7 << ACTIM_CTRLA_TRAS_POS) | \ + (10 << ACTIM_CTRLA_TRC_POS) | \ + (12 << ACTIM_CTRLA_TRFC_POS)) + +#define V_ACTIMB_165 ((19 << ACTIM_CTRLB_TXSR_POS) | \ + (1 << ACTIM_CTRLB_TXP_POS) | \ + (1 << ACTIM_CTRLB_TCKE_POS) | \ + (1 << ACTIM_CTRLB_TWTR_POS)) +#elif defined(PRCM_CLK_CFG2_400MHZ) +/* DDR running at 200MHz */ + +/* tREFI = (tREF / (2 ^ RASWIDTH)) = (64ms / (2 ^ 14)) = 3.906us */ +#define SDP_SDRC_RFR_CTRL 0x0002db01 /* (3.906us / 6ns) - 50 */ + +/* ACTIMA + * -TDAL = Twr/Tck + Trp/tck = 12/5 + 15/5 = 2.4 + 3 = 5.4 -> 6 + * -TDPL (Twr) = 12/5 = 2.4 -> 3 + * -TRRD = 10/5 = 2 + * -TRCD = 15/5 = 3 + * -TRP = 15/5 = 3 + * -TRAS = 40/5 = 8 + * -TRC = 55/5 = 11 + * -TRFC = 120/5 = 24 + * ACTIMB + * -TWTR = 2 tCK + * -TCKE = 2 tCK + * -TXP = 2 tCK + * -XSR = 120/5 = 24 + */ +#define V_ACTIMA_200 ((6 << ACTIM_CTRLA_TDAL_POS) | \ + (3 << ACTIM_CTRLA_TDPL_POS) | \ + (2 << ACTIM_CTRLA_TRRD_POS) | \ + (3 << ACTIM_CTRLA_TRCD_POS) | \ + (3 << ACTIM_CTRLA_TRP_POS) | \ + (8 << ACTIM_CTRLA_TRAS_POS) | \ + (11 << ACTIM_CTRLA_TRC_POS) | \ + (24 << ACTIM_CTRLA_TRFC_POS)) + +#define V_ACTIMB_200 ((24 << ACTIM_CTRLB_TXSR_POS) | \ + (2 << ACTIM_CTRLB_TXP_POS) | \ + (2 << ACTIM_CTRLB_TCKE_POS) | \ + (2 << ACTIM_CTRLB_TWTR_POS)) +#else +#error not supported +#endif + +#else /* sdp3430 */ +/* Infineon part of 3430SDP (166MHz optimized) 6.02ns + * ACTIMA + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 18/6 = 3 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 72/6 = 12 + * ACTIMB + * TCKE = 2 + * XSR = 120/6 = 20 + */ +#define TDAL_165 6 +#define TDPL_165 3 +#define TRRD_165 2 +#define TRCD_165 3 +#define TRP_165 3 +#define TRAS_165 7 +#define TRC_165 10 +#define TRFC_165 12 +#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | (TRAS_165 << 18) \ + | (TRP_165 << 15) | (TRCD_165 << 12) |(TRRD_165 << 9) | \ + (TDPL_165 << 6) | (TDAL_165)) + +#define TWTR_165 1 +#define TCKE_165 2 +#define TXP_165 2 +#define XSR_165 20 +#define V_ACTIMB_165 ((TCKE_165 << 12) | (XSR_165 << 0)) | \ + (TXP_165 << 8) | (TWTR_165 << 16) +#endif + +/* New and compatability speed defines */ +#if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B) +# define L3_100MHZ /* Use with <= 100MHz SDRAM */ +#elif defined (PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III) || defined(PRCM_CONFIG_5A) +# define L3_133MHZ /* Use with <= 133MHz SDRAM*/ +#elif defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) || defined(PRCM_CONFIG_2) +# define L3_165MHZ /* Use with <= 165MHz SDRAM (L3=166 on 3430) */ +#elif defined(PRCM_CLK_CFG2_400MHZ) +# define L3_200MHZ /* Use with <= 200MHz SDRAM (L3=200 on 3630) */ +#else +#error "Undefined bus speed" +#endif + +#if defined(L3_100MHZ) +# define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_100 +# define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_100 +# if !defined(SDP_SDRC_RFR_CTRL) +# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_100MHz +# endif +#elif defined(L3_133MHZ) +# define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_133 +# define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_133 +# if !defined(SDP_SDRC_RFR_CTRL) +# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_133MHz +# endif +#elif defined(L3_165MHZ) +# define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 +# define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 +# if !defined(SDP_SDRC_RFR_CTRL) +# define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz +# endif +#elif defined(L3_200MHZ) +# define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_200 +# define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_200 +# if !defined(SDP_SDRC_RFR_CTRL) +# define SDP_SDRC_RFR_CTRL ZOOM3_3630_RFR_CTRL_200MHz +# endif +#endif + +/* + * GPMC settings - + * Definitions is as per the following format + * # define _GPMC_CONFIG + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * STNOR - Intel Strata Flash + * SMNAND - Samsung NAND + * M_NAND - Micron Large page x16 NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley NOR + * ONNAND - Samsung One NAND + * + * include/configs/file.h contains the defn - for all CS we are interested + * #define OMAP34XX_GPMC_CSx PART + * #define OMAP34XX_GPMC_CSx_SIZE Size + * #define OMAP34XX_GPMC_CSx_MAP Map + * Where: + * x - CS number + * PART - Part Name as defined above + * SIZE - how big is the mapping to be + * GPMC_SIZE_128M - 0x8 + * GPMC_SIZE_64M - 0xC + * GPMC_SIZE_32M - 0xE + * GPMC_SIZE_16M - 0xF + * MAP - Map this CS to which address(GPMC address space)- Absolute address + * >>24 before being used. + */ +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#if defined(L3_100MHZ) +# define SMNAND_GPMC_CONFIG1 0x0 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x00000A80 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 0x00141400 +# define M_NAND_GPMC_CONFIG3 0x00141400 +# define M_NAND_GPMC_CONFIG4 0x0F010F01 +# define M_NAND_GPMC_CONFIG5 0x010C1414 +# define M_NAND_GPMC_CONFIG6 0x1f0f0A80 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x000f0f01 +# define STNOR_GPMC_CONFIG3 0x00050502 +# define STNOR_GPMC_CONFIG4 0x0C060C06 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x1F0F0000 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001F1F00 +# define MPDB_GPMC_CONFIG3 0x00080802 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x031A1F1F +# define MPDB_GPMC_CONFIG6 0x000003C2 +#endif + +#if defined(L3_133MHZ) +# define SMNAND_GPMC_CONFIG1 0x00000800 +# define SMNAND_GPMC_CONFIG2 0x00141400 +# define SMNAND_GPMC_CONFIG3 0x00141400 +# define SMNAND_GPMC_CONFIG4 0x0F010F01 +# define SMNAND_GPMC_CONFIG5 0x010C1414 +# define SMNAND_GPMC_CONFIG6 0x1F0F0A80 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define M_NAND_GPMC_CONFIG1 0x00001800 /* might reuse smnand, with |= 1000 */ +# define M_NAND_GPMC_CONFIG2 0x00141400 +# define M_NAND_GPMC_CONFIG3 0x00141400 +# define M_NAND_GPMC_CONFIG4 0x0F010F01 +# define M_NAND_GPMC_CONFIG5 0x010C1414 +# define M_NAND_GPMC_CONFIG6 0x1F0F0A80 +# define M_NAND_GPMC_CONFIG7 0x00000C44 + +# define STNOR_GPMC_CONFIG1 0x1203 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x10081008 +# define STNOR_GPMC_CONFIG5 0x01131F1F +# define STNOR_GPMC_CONFIG6 0x1F0F04c4 + +# define SIBNOR_GPMC_CONFIG1 0x1200 +# define SIBNOR_GPMC_CONFIG2 0x001f1f00 +# define SIBNOR_GPMC_CONFIG3 0x00080802 +# define SIBNOR_GPMC_CONFIG4 0x1C091C09 +# define SIBNOR_GPMC_CONFIG5 0x01131F1F +# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 + +/* ES1 SDP and ES1 chip Debug FPGA */ +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1C091C09 +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x000004C4 + +/* ES2 SDP and ES2 chip Debug FPGA */ +# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 +# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 +# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 +# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 +# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F +# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 + +# define LAB_ENET_GPMC_CONFIG1 0x00611000 +# define LAB_ENET_GPMC_CONFIG2 0x001F1F01 +# define LAB_ENET_GPMC_CONFIG3 0x00080803 +# define LAB_ENET_GPMC_CONFIG4 0x1D091D09 +# define LAB_ENET_GPMC_CONFIG5 0x041D1F1F +# define LAB_ENET_GPMC_CONFIG6 0x1D0904C4 + +# define P2_GPMC_CONFIG1 0x0 +# define P2_GPMC_CONFIG2 0x0 +# define P2_GPMC_CONFIG3 0x0 +# define P2_GPMC_CONFIG4 0x0 +# define P2_GPMC_CONFIG5 0x0 +# define P2_GPMC_CONFIG6 0x0 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000c0c01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0c040c04 +# define ONENAND_GPMC_CONFIG5 0x010C1010 +# define ONENAND_GPMC_CONFIG6 0x1F060000 + +#endif /* endif L3_133MHZ */ + +#if defined (L3_165MHZ) +# define SMNAND_GPMC_CONFIG1 0x00000800 +# define SMNAND_GPMC_CONFIG2 0x00060600 +# define SMNAND_GPMC_CONFIG3 0x00060401 +# define SMNAND_GPMC_CONFIG4 0x05010801 +# define SMNAND_GPMC_CONFIG5 0x00090B0B +# define SMNAND_GPMC_CONFIG6 0x050001C0 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 0x00141400 +# define M_NAND_GPMC_CONFIG3 0x00141400 +# define M_NAND_GPMC_CONFIG4 0x0F010F01 +# define M_NAND_GPMC_CONFIG5 0x010C1414 +# define M_NAND_GPMC_CONFIG6 0x1F0F0A80 +# define M_NAND_GPMC_CONFIG7 0x00000C44 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x11091109 +# define STNOR_GPMC_CONFIG5 0x01141F1F +# define STNOR_GPMC_CONFIG6 0x1F0F04c4 + +# define SIBNOR_GPMC_CONFIG1 0x1200 +# define SIBNOR_GPMC_CONFIG2 0x001f1f00 +# define SIBNOR_GPMC_CONFIG3 0x00080802 +# define SIBNOR_GPMC_CONFIG4 0x1C091C09 +# define SIBNOR_GPMC_CONFIG5 0x01131F1F +# define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 + +# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 +# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 +# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 +# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 +# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F +# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1c0b1c0a +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x1F0F04C4 + +# define LAB_ENET_GPMC_CONFIG1 0x00611000 +# define LAB_ENET_GPMC_CONFIG2 0x001F1F01 +# define LAB_ENET_GPMC_CONFIG3 0x00080803 +# define LAB_ENET_GPMC_CONFIG4 0x1D091D09 +# define LAB_ENET_GPMC_CONFIG5 0x041D1F1F +# define LAB_ENET_GPMC_CONFIG6 0x1D0904C4 + +# define P2_GPMC_CONFIG1 0x0 +# define P2_GPMC_CONFIG2 0x0 +# define P2_GPMC_CONFIG3 0x0 +# define P2_GPMC_CONFIG4 0x0 +# define P2_GPMC_CONFIG5 0x0 +# define P2_GPMC_CONFIG6 0x0 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000F0F01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0F040F04 +# define ONENAND_GPMC_CONFIG5 0x010F1010 +# define ONENAND_GPMC_CONFIG6 0x1F060000 +#endif /* L3_165MHZ */ + +#if defined(L3_200MHZ) +# define SMNAND_GPMC_CONFIG1 0x00000800 +# define SMNAND_GPMC_CONFIG2 0x00060600 +# define SMNAND_GPMC_CONFIG3 0x00060401 +# define SMNAND_GPMC_CONFIG4 0x05010801 +# define SMNAND_GPMC_CONFIG5 0x00090B0B +# define SMNAND_GPMC_CONFIG6 0x050001C0 +# define SMNAND_GPMC_CONFIG7 0x00000C44 + +# define M_NAND_GPMC_CONFIG1 0x00001800 +# define M_NAND_GPMC_CONFIG2 0x00181800 +# define M_NAND_GPMC_CONFIG3 0x00181800 +# define M_NAND_GPMC_CONFIG4 0x12021202 +# define M_NAND_GPMC_CONFIG5 0x020f1818 +# define M_NAND_GPMC_CONFIG6 0x00000c80 +# define M_NAND_GPMC_CONFIG7 0x00000870 + +# define STNOR_GPMC_CONFIG1 0x3 +# define STNOR_GPMC_CONFIG2 0x00151501 +# define STNOR_GPMC_CONFIG3 0x00060602 +# define STNOR_GPMC_CONFIG4 0x11091109 +# define STNOR_GPMC_CONFIG5 0x01141F1F +# define STNOR_GPMC_CONFIG6 0x1F0F04c4 + +# define SIBNOR_GPMC_CONFIG1 0x1210 +# define SIBNOR_GPMC_CONFIG2 0x00131300 +# define SIBNOR_GPMC_CONFIG3 0x00050501 +# define SIBNOR_GPMC_CONFIG4 0x11061106 +# define SIBNOR_GPMC_CONFIG5 0x010c1313 +# define SIBNOR_GPMC_CONFIG6 0x130902c2 + +# define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 +# define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 +# define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 +# define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 +# define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F +# define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 + +# define MPDB_GPMC_CONFIG1 0x00011000 +# define MPDB_GPMC_CONFIG2 0x001f1f01 +# define MPDB_GPMC_CONFIG3 0x00080803 +# define MPDB_GPMC_CONFIG4 0x1c0b1c0a +# define MPDB_GPMC_CONFIG5 0x041f1F1F +# define MPDB_GPMC_CONFIG6 0x1F0F04C4 + +# define LAB_ENET_GPMC_CONFIG1 0x00611000 +# define LAB_ENET_GPMC_CONFIG2 0x001F1F01 +# define LAB_ENET_GPMC_CONFIG3 0x00080803 +# define LAB_ENET_GPMC_CONFIG4 0x1D091D09 +# define LAB_ENET_GPMC_CONFIG5 0x041D1F1F +# define LAB_ENET_GPMC_CONFIG6 0x1D0904C4 + +# define P2_GPMC_CONFIG1 0x0 +# define P2_GPMC_CONFIG2 0x0 +# define P2_GPMC_CONFIG3 0x0 +# define P2_GPMC_CONFIG4 0x0 +# define P2_GPMC_CONFIG5 0x0 +# define P2_GPMC_CONFIG6 0x0 + +# define ONENAND_GPMC_CONFIG1 0x00001200 +# define ONENAND_GPMC_CONFIG2 0x000F0F01 +# define ONENAND_GPMC_CONFIG3 0x00030301 +# define ONENAND_GPMC_CONFIG4 0x0F040F04 +# define ONENAND_GPMC_CONFIG5 0x010F1010 +# define ONENAND_GPMC_CONFIG6 0x1F060000 + +#endif /* L3_200MHZ */ + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define PISMO1_NOR 1 +#define PISMO1_NAND 2 +#define PISMO2_CS0 3 +#define PISMO2_CS1 4 +#define PISMO1_ONENAND 5 +#define DBG_MPDB 6 +#define PISMO2_NAND_CS0 7 +#define PISMO2_NAND_CS1 8 + +/* make it readable for the gpmc_init */ +#define PISMO1_NOR_BASE FLASH_BASE +#define PISMO1_NAND_BASE NAND_BASE +#define PISMO2_CS0_BASE PISMO2_MAP1 +#define PISMO1_ONEN_BASE ONENAND_MAP +#define DBG_MPDB_BASE DEBUG_BASE + +#endif /* endif _OMAP34XX_MEM_H_ */ diff --git a/include/asm-arm/arch-omap3/mmc.h b/include/asm-arm/arch-omap3/mmc.h new file mode 100644 index 000000000..ef5699eb3 --- /dev/null +++ b/include/asm-arm/arch-omap3/mmc.h @@ -0,0 +1,191 @@ +/* + * include/asm-arm/arch-omap3/mmc.h + * + * Based on the file include/asm-arm/arch-pxa/mmc.h, + * with the below copyright. + * Author: Vladimir Shebordaev, Igor Oblakov + * Copyright: MontaVista Software Inc. + * + * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * History: 05/03/08 + * Modified for use in omap3 MMC driver. + */ +#ifndef __MMC_OMAP_H__ +#define __MMC_OMAP_H__ + +/* PXA-250 MMC controller registers */ + +/* MMC_STRPCL */ +#define MMC_STRPCL_STOP_CLK (0x0001UL) +#define MMC_STRPCL_START_CLK (0x0002UL) + +/* MMC_STAT */ + +#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN \ + | MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE \ + | MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR) + +/* MMC_CLKRT */ +#define MMC_CLKRT_20MHZ (0x0000UL) +#define MMC_CLKRT_10MHZ (0x0001UL) +#define MMC_CLKRT_5MHZ (0x0002UL) +#define MMC_CLKRT_2_5MHZ (0x0003UL) +#define MMC_CLKRT_1_25MHZ (0x0004UL) +#define MMC_CLKRT_0_625MHZ (0x0005UL) +#define MMC_CLKRT_0_3125MHZ (0x0006UL) + +/* MMC_SPI */ +#define MMC_SPI_DISABLE (0x00UL) +#define MMC_SPI_EN (0x01UL) +#define MMC_SPI_CS_EN (0x01UL << 2) +#define MMC_SPI_CS_ADDRESS (0x01UL << 3) +#define MMC_SPI_CRC_ON (0x01UL << 1) + +/* MMC_CMDAT */ +#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) +#define MMC_CMDAT_INIT (0x0001UL << 6) +#define MMC_CMDAT_BUSY (0x0001UL << 5) +#define MMC_CMDAT_STREAM (0x0001UL << 4) +#define MMC_CMDAT_BLOCK (0x0000UL << 4) +#define MMC_CMDAT_WRITE (0x0001UL << 3) +#define MMC_CMDAT_READ (0x0000UL << 3) +#define MMC_CMDAT_DATA_EN (0x0001UL << 2) +#define MMC_CMDAT_R1 (0x0001UL) +#define MMC_CMDAT_R2 (0x0002UL) +#define MMC_CMDAT_R3 (0x0003UL) + +/* MMC_RESTO */ +#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ + +/* MMC_RDTO */ +#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ + +/* MMC_BLKLEN */ +#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ + +/* MMC_PRTBUF */ +#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) +#define MMC_PRTBUF_BUF_FULL (0x00UL) + +/* MMC_I_MASK */ +#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_MASK_STOP_CMD (0x01UL << 3) +#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) +#define MMC_I_MASK_PRG_DONE (0x01UL << 1) +#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) +#define MMC_I_MASK_ALL (0x07fUL) + + +/* MMC_I_REG */ +#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_REG_STOP_CMD (0x01UL << 3) +#define MMC_I_REG_END_CMD_RES (0x01UL << 2) +#define MMC_I_REG_PRG_DONE (0x01UL << 1) +#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) +#define MMC_I_REG_ALL (0x007fUL) + +/* MMC_CMD */ +#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ +#define CMD(x) (x) + +#define MMC_DEFAULT_RCA 1 + +#define MMC_BLOCK_SIZE 512 +#define MMC_CMD_RESET 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RCA 3 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_BLOCK 17 +#define MMC_CMD_RD_BLK_MULTI 18 +#define MMC_CMD_WRITE_BLOCK 24 + +#define MMC_MAX_BLOCK_SIZE 512 + +#define MMC_R1_IDLE_STATE 0x01 +#define MMC_R1_ERASE_STATE 0x02 +#define MMC_R1_ILLEGAL_CMD 0x04 +#define MMC_R1_COM_CRC_ERR 0x08 +#define MMC_R1_ERASE_SEQ_ERR 0x01 +#define MMC_R1_ADDR_ERR 0x02 +#define MMC_R1_PARAM_ERR 0x04 + +#define MMC_R1B_WP_ERASE_SKIP 0x0002 +#define MMC_R1B_ERR 0x0004 +#define MMC_R1B_CC_ERR 0x0008 +#define MMC_R1B_CARD_ECC_ERR 0x0010 +#define MMC_R1B_WP_VIOLATION 0x0020 +#define MMC_R1B_ERASE_PARAM 0x0040 +#define MMC_R1B_OOR 0x0080 +#define MMC_R1B_IDLE_STATE 0x0100 +#define MMC_R1B_ERASE_RESET 0x0200 +#define MMC_R1B_ILLEGAL_CMD 0x0400 +#define MMC_R1B_COM_CRC_ERR 0x0800 +#define MMC_R1B_ERASE_SEQ_ERR 0x1000 +#define MMC_R1B_ADDR_ERR 0x2000 +#define MMC_R1B_PARAM_ERR 0x4000 + +typedef struct mmc_cid { +/* FIXME: BYTE_ORDER */ + unsigned char year:4, + month:4; + unsigned char sn[3]; + unsigned char fwrev:4, + hwrev:4; + unsigned char name[6]; + unsigned char id[3]; +} mmc_cid_t; + +typedef struct mmc_csd { + unsigned char ecc:2, + file_format:2, + tmp_write_protect:1, + perm_write_protect:1, + copy:1, + file_format_grp:1; + unsigned long int content_prot_app:1, + rsvd3:4, + write_bl_partial:1, + write_bl_len:4, + r2w_factor:3, + default_ecc:2, + wp_grp_enable:1, + wp_grp_size:5, + erase_grp_mult:5, + erase_grp_size:5, + c_size_mult1:3, + vdd_w_curr_max:3, + vdd_w_curr_min:3, + vdd_r_curr_max:3, + vdd_r_curr_min:3, + c_size:12, + rsvd2:2, + dsr_imp:1, + read_blk_misalign:1, + write_blk_misalign:1, + read_bl_partial:1; + + unsigned short read_bl_len:4, + ccc:12; + unsigned char tran_speed; + unsigned char nsac; + unsigned char taac; + unsigned char rsvd1:2, + spec_vers:4, + csd_structure:2; +} mmc_csd_t; + + +#endif /* __MMC_OMAP_H__ */ diff --git a/include/asm-arm/arch-omap3/musb_regs.h b/include/asm-arm/arch-omap3/musb_regs.h new file mode 100644 index 000000000..b61330c18 --- /dev/null +++ b/include/asm-arm/arch-omap3/musb_regs.h @@ -0,0 +1,312 @@ +/* + * Copied from omapkernel linux kernel source drivers/usb/musb/musb_regs.h + * Copyright (C) 2008 Windriver + * + * MUSB OTG driver register defines + * + * Copyright 2005 Mentor Graphics Corporation + * Copyright (C) 2005-2006 by Texas Instruments + * Copyright (C) 2006-2007 Nokia Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MUSB_REGS_H__ +#define __MUSB_REGS_H__ + +#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ + +/* + * Common USB registers + */ + +#define MUSB_FADDR 0x00 /* 8-bit */ +#define MUSB_POWER 0x01 /* 8-bit */ + +#define MUSB_INTRTX 0x02 /* 16-bit */ +#define MUSB_INTRRX 0x04 +#define MUSB_INTRTXE 0x06 +#define MUSB_INTRRXE 0x08 +#define MUSB_INTRUSB 0x0A /* 8 bit */ +#define MUSB_INTRUSBE 0x0B /* 8 bit */ +#define MUSB_FRAME 0x0C +#define MUSB_INDEX 0x0E /* 8 bit */ +#define MUSB_TESTMODE 0x0F /* 8 bit */ + +/* + * Additional Control Registers + */ + +#define MUSB_DEVCTL 0x60 /* 8 bit */ + +/* These are always controlled through the INDEX register */ +#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */ +#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */ +#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */ +#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */ + +/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */ +#define MUSB_HWVERS 0x6C /* 8 bit */ + +#define MUSB_EPINFO 0x78 /* 8 bit */ +#define MUSB_RAMINFO 0x79 /* 8 bit */ +#define MUSB_LINKINFO 0x7a /* 8 bit */ +#define MUSB_VPLEN 0x7b /* 8 bit */ +#define MUSB_HS_EOF1 0x7c /* 8 bit */ +#define MUSB_FS_EOF1 0x7d /* 8 bit */ +#define MUSB_LS_EOF1 0x7e /* 8 bit */ + +/* Offsets to endpoint registers */ +#define MUSB_TXMAXP 0x00 +#define MUSB_TXCSR 0x02 +#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */ +#define MUSB_RXMAXP 0x04 +#define MUSB_RXCSR 0x06 +#define MUSB_RXCOUNT 0x08 +#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */ +#define MUSB_TXTYPE 0x0A +#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */ +#define MUSB_TXINTERVAL 0x0B +#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */ +#define MUSB_RXTYPE 0x0C +#define MUSB_RXINTERVAL 0x0D +#define MUSB_FIFOSIZE 0x0F +#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */ + +/* Offsets to endpoint registers in indexed model (using INDEX register) */ +#define MUSB_INDEXED_OFFSET(_epnum, _offset) \ + (0x10 + (_offset)) + +/* Offsets to endpoint registers in flat models */ +#define MUSB_FLAT_OFFSET(_epnum, _offset) \ + (0x100 + (0x10*(_epnum)) + (_offset)) + +/* "bus control"/target registers, for host side multipoint (external hubs) */ +#define MUSB_TXFUNCADDR 0x00 +#define MUSB_TXHUBADDR 0x02 +#define MUSB_TXHUBPORT 0x03 + +#define MUSB_RXFUNCADDR 0x04 +#define MUSB_RXHUBADDR 0x06 +#define MUSB_RXHUBPORT 0x07 + +#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \ + (0x80 + (8*(_epnum)) + (_offset)) + +/* DMA Control Registers */ +#define MUSB_DMA_INTR 0x200 +#define MUSB_DMA_CNTL_CH(n) (0x204 + ((n-1)*0x10)) +#define MUSB_DMA_ADDR_CH(n) (0x208 + ((n-1)*0x10)) +#define MUSB_DMA_COUNT_CH(n) (0x20C + ((n-1)*0x10)) + +/* + * MUSB Register bits + */ + +/* POWER */ +#define MUSB_POWER_ISOUPDATE 0x80 +#define MUSB_POWER_SOFTCONN 0x40 +#define MUSB_POWER_HSENAB 0x20 +#define MUSB_POWER_HSMODE 0x10 +#define MUSB_POWER_RESET 0x08 +#define MUSB_POWER_RESUME 0x04 +#define MUSB_POWER_SUSPENDM 0x02 +#define MUSB_POWER_ENSUSPEND 0x01 + +/* INTRUSB */ +#define MUSB_INTR_SUSPEND 0x01 +#define MUSB_INTR_RESUME 0x02 +#define MUSB_INTR_RESET 0x04 +#define MUSB_INTR_BABBLE 0x04 +#define MUSB_INTR_SOF 0x08 +#define MUSB_INTR_CONNECT 0x10 +#define MUSB_INTR_DISCONNECT 0x20 +#define MUSB_INTR_SESSREQ 0x40 +#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ + +/* DEVCTL */ +#define MUSB_DEVCTL_BDEVICE 0x80 +#define MUSB_DEVCTL_FSDEV 0x40 +#define MUSB_DEVCTL_LSDEV 0x20 +#define MUSB_DEVCTL_VBUS 0x18 +#define MUSB_DEVCTL_VBUS_SHIFT 3 +#define MUSB_DEVCTL_HM 0x04 +#define MUSB_DEVCTL_HR 0x02 +#define MUSB_DEVCTL_SESSION 0x01 + +/* TESTMODE */ +#define MUSB_TEST_FORCE_HOST 0x80 +#define MUSB_TEST_FIFO_ACCESS 0x40 +#define MUSB_TEST_FORCE_FS 0x20 +#define MUSB_TEST_FORCE_HS 0x10 +#define MUSB_TEST_PACKET 0x08 +#define MUSB_TEST_K 0x04 +#define MUSB_TEST_J 0x02 +#define MUSB_TEST_SE0_NAK 0x01 + +/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ +#define MUSB_FIFOSZ_DPB 0x10 +/* Allocation size (8, 16, 32, ... 4096) */ +#define MUSB_FIFOSZ_SIZE 0x0f + +/* CSR0 */ +#define MUSB_CSR0_FLUSHFIFO 0x0100 +#define MUSB_CSR0_TXPKTRDY 0x0002 +#define MUSB_CSR0_RXPKTRDY 0x0001 + +/* CSR0 in Peripheral mode */ +#define MUSB_CSR0_P_SVDSETUPEND 0x0080 +#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 +#define MUSB_CSR0_P_SENDSTALL 0x0020 +#define MUSB_CSR0_P_SETUPEND 0x0010 +#define MUSB_CSR0_P_DATAEND 0x0008 +#define MUSB_CSR0_P_SENTSTALL 0x0004 + +/* CSR0 in Host mode */ +#define MUSB_CSR0_H_DIS_PING 0x0800 +#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ +#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ +#define MUSB_CSR0_H_NAKTIMEOUT 0x0080 +#define MUSB_CSR0_H_STATUSPKT 0x0040 +#define MUSB_CSR0_H_REQPKT 0x0020 +#define MUSB_CSR0_H_ERROR 0x0010 +#define MUSB_CSR0_H_SETUPPKT 0x0008 +#define MUSB_CSR0_H_RXSTALL 0x0004 + +/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_CSR0_P_WZC_BITS \ + (MUSB_CSR0_P_SENTSTALL) +#define MUSB_CSR0_H_WZC_BITS \ + (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ + | MUSB_CSR0_RXPKTRDY) + +/* TxType/RxType */ +#define MUSB_TYPE_SPEED 0xc0 +#define MUSB_TYPE_SPEED_SHIFT 6 +#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ +#define MUSB_TYPE_PROTO_SHIFT 4 +#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ + +/* CONFIGDATA */ +#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ +#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ +#define MUSB_CONFIGDATA_BIGENDIAN 0x20 +#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ +#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ +#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ +#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ +#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ + +/* TXCSR in Peripheral and Host mode */ +#define MUSB_TXCSR_AUTOSET 0x8000 +#define MUSB_TXCSR_MODE 0x2000 +#define MUSB_TXCSR_DMAENAB 0x1000 +#define MUSB_TXCSR_FRCDATATOG 0x0800 +#define MUSB_TXCSR_DMAMODE 0x0400 +#define MUSB_TXCSR_CLRDATATOG 0x0040 +#define MUSB_TXCSR_FLUSHFIFO 0x0008 +#define MUSB_TXCSR_FIFONOTEMPTY 0x0002 +#define MUSB_TXCSR_TXPKTRDY 0x0001 + +/* TXCSR in Peripheral mode */ +#define MUSB_TXCSR_P_ISO 0x4000 +#define MUSB_TXCSR_P_INCOMPTX 0x0080 +#define MUSB_TXCSR_P_SENTSTALL 0x0020 +#define MUSB_TXCSR_P_SENDSTALL 0x0010 +#define MUSB_TXCSR_P_UNDERRUN 0x0004 + +/* TXCSR in Host mode */ +#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 +#define MUSB_TXCSR_H_DATATOGGLE 0x0100 +#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 +#define MUSB_TXCSR_H_RXSTALL 0x0020 +#define MUSB_TXCSR_H_ERROR 0x0004 + +/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_TXCSR_P_WZC_BITS \ + (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ + | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) +#define MUSB_TXCSR_H_WZC_BITS \ + (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ + | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) + +/* RXCSR in Peripheral and Host mode */ +#define MUSB_RXCSR_AUTOCLEAR 0x8000 +#define MUSB_RXCSR_DMAENAB 0x2000 +#define MUSB_RXCSR_DISNYET 0x1000 +#define MUSB_RXCSR_PID_ERR 0x1000 +#define MUSB_RXCSR_DMAMODE 0x0800 +#define MUSB_RXCSR_INCOMPRX 0x0100 +#define MUSB_RXCSR_CLRDATATOG 0x0080 +#define MUSB_RXCSR_FLUSHFIFO 0x0010 +#define MUSB_RXCSR_DATAERROR 0x0008 +#define MUSB_RXCSR_FIFOFULL 0x0002 +#define MUSB_RXCSR_RXPKTRDY 0x0001 + +/* RXCSR in Peripheral mode */ +#define MUSB_RXCSR_P_ISO 0x4000 +#define MUSB_RXCSR_P_SENTSTALL 0x0040 +#define MUSB_RXCSR_P_SENDSTALL 0x0020 +#define MUSB_RXCSR_P_OVERRUN 0x0004 + +/* RXCSR in Host mode */ +#define MUSB_RXCSR_H_AUTOREQ 0x4000 +#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 +#define MUSB_RXCSR_H_DATATOGGLE 0x0200 +#define MUSB_RXCSR_H_RXSTALL 0x0040 +#define MUSB_RXCSR_H_REQPKT 0x0020 +#define MUSB_RXCSR_H_ERROR 0x0004 + +/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_RXCSR_P_WZC_BITS \ + (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ + | MUSB_RXCSR_RXPKTRDY) +#define MUSB_RXCSR_H_WZC_BITS \ + (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ + | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) + +/* HUBADDR */ +#define MUSB_HUBADDR_MULTI_TT 0x80 + +/* DMA Control */ +#define MUSB_DMA_CNTL_BUSRT_MODE_0 0x0000 +#define MUSB_DMA_CNTL_BUSRT_MODE_1 0x0200 +#define MUSB_DMA_CNTL_BUSRT_MODE_2 0x0400 +#define MUSB_DMA_CNTL_BUSRT_MODE_3 0x0600 +#define MUSB_DMA_CNTL_ERR 0x0100 +#define MUSB_DMA_CNTL_END_POINT(n) ((n)<<4) +#define MUSB_DMA_CNTL_INTERRUPT_ENABLE 0x0008 +#define MUSB_DMA_CNTL_MODE_0 0x0000 +#define MUSB_DMA_CNTL_MODE_1 0x0004 +#define MUSB_DMA_CNTL_WRITE 0x0000 +#define MUSB_DMA_CNTL_READ 0x0002 +#define MUSB_DMA_CNTL_ENABLE 0x0001 + +/* Tx/Rx fifo size */ +#define MUSB_TXFIFOSZ_DPB 0x0010 +#define MUSB_RXFIFOSZ_DPB 0x0010 +#endif /* __MUSB_REGS_H__ */ diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-arm/arch-omap3/mux.h new file mode 100644 index 000000000..eba1c307c --- /dev/null +++ b/include/asm-arm/arch-omap3/mux.h @@ -0,0 +1,456 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Syed Mohammed Khasim + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP3430_MUX_H_ +#define _OMAP3430_MUX_H_ + +/* + * OFF_PD - Off mode pull type down + * OFF_PU - Off mode pull type up + * OFF_OUT_PTD - Off Mode Mux low for OUT + * OFF_OUT_PTU - Off Mode Mux high for OUT + * OFF_IN - Off Mode Mux set to IN + * OFF_OUT - Off Mode Mux set to OUT + * OFF_EN - Off Mode Mux Enable + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + */ + +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 11) +#define OFF_OUT_PTU (1 << 11) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) + +#define IEN (1 << 8) +#define IDIS (0 << 8) +#define PTU (1 << 4) +#define PTD (0 << 4) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif /* #ifdef CONFIG_OFF_PADCONF */ + +/* + * To get the actual address the offset has to added + * with OMAP34XX_CTRL_BASE to get the actual address + */ + +/*SDRC*/ +#define CONTROL_PADCONF_SDRC_D0 0x0030 +#define CONTROL_PADCONF_SDRC_D1 0x0032 +#define CONTROL_PADCONF_SDRC_D2 0x0034 +#define CONTROL_PADCONF_SDRC_D3 0x0036 +#define CONTROL_PADCONF_SDRC_D4 0x0038 +#define CONTROL_PADCONF_SDRC_D5 0x003A +#define CONTROL_PADCONF_SDRC_D6 0x003C +#define CONTROL_PADCONF_SDRC_D7 0x003E +#define CONTROL_PADCONF_SDRC_D8 0x0040 +#define CONTROL_PADCONF_SDRC_D9 0x0042 +#define CONTROL_PADCONF_SDRC_D10 0x0044 +#define CONTROL_PADCONF_SDRC_D11 0x0046 +#define CONTROL_PADCONF_SDRC_D12 0x0048 +#define CONTROL_PADCONF_SDRC_D13 0x004A +#define CONTROL_PADCONF_SDRC_D14 0x004C +#define CONTROL_PADCONF_SDRC_D15 0x004E +#define CONTROL_PADCONF_SDRC_D16 0x0050 +#define CONTROL_PADCONF_SDRC_D17 0x0052 +#define CONTROL_PADCONF_SDRC_D18 0x0054 +#define CONTROL_PADCONF_SDRC_D19 0x0056 +#define CONTROL_PADCONF_SDRC_D20 0x0058 +#define CONTROL_PADCONF_SDRC_D21 0x005A +#define CONTROL_PADCONF_SDRC_D22 0x005C +#define CONTROL_PADCONF_SDRC_D23 0x005E +#define CONTROL_PADCONF_SDRC_D24 0x0060 +#define CONTROL_PADCONF_SDRC_D25 0x0062 +#define CONTROL_PADCONF_SDRC_D26 0x0064 +#define CONTROL_PADCONF_SDRC_D27 0x0066 +#define CONTROL_PADCONF_SDRC_D28 0x0068 +#define CONTROL_PADCONF_SDRC_D29 0x006A +#define CONTROL_PADCONF_SDRC_D30 0x006C +#define CONTROL_PADCONF_SDRC_D31 0x006E +#define CONTROL_PADCONF_SDRC_CLK 0x0070 +#define CONTROL_PADCONF_SDRC_DQS0 0x0072 +#define CONTROL_PADCONF_SDRC_DQS1 0x0074 +#define CONTROL_PADCONF_SDRC_DQS2 0x0076 +#define CONTROL_PADCONF_SDRC_DQS3 0x0078 +/*GPMC*/ +#define CONTROL_PADCONF_GPMC_A1 0x007A +#define CONTROL_PADCONF_GPMC_A2 0x007C +#define CONTROL_PADCONF_GPMC_A3 0x007E +#define CONTROL_PADCONF_GPMC_A4 0x0080 +#define CONTROL_PADCONF_GPMC_A5 0x0082 +#define CONTROL_PADCONF_GPMC_A6 0x0084 +#define CONTROL_PADCONF_GPMC_A7 0x0086 +#define CONTROL_PADCONF_GPMC_A8 0x0088 +#define CONTROL_PADCONF_GPMC_A9 0x008A +#define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_D0 0x008E +#define CONTROL_PADCONF_GPMC_D1 0x0090 +#define CONTROL_PADCONF_GPMC_D2 0x0092 +#define CONTROL_PADCONF_GPMC_D3 0x0094 +#define CONTROL_PADCONF_GPMC_D4 0x0096 +#define CONTROL_PADCONF_GPMC_D5 0x0098 +#define CONTROL_PADCONF_GPMC_D6 0x009A +#define CONTROL_PADCONF_GPMC_D7 0x009C +#define CONTROL_PADCONF_GPMC_D8 0x009E +#define CONTROL_PADCONF_GPMC_D9 0x00A0 +#define CONTROL_PADCONF_GPMC_D10 0x00A2 +#define CONTROL_PADCONF_GPMC_D11 0x00A4 +#define CONTROL_PADCONF_GPMC_D12 0x00A6 +#define CONTROL_PADCONF_GPMC_D13 0x00A8 +#define CONTROL_PADCONF_GPMC_D14 0x00AA +#define CONTROL_PADCONF_GPMC_D15 0x00AC +#define CONTROL_PADCONF_GPMC_nCS0 0x00AE +#define CONTROL_PADCONF_GPMC_nCS1 0x00B0 +#define CONTROL_PADCONF_GPMC_nCS2 0x00B2 +#define CONTROL_PADCONF_GPMC_nCS3 0x00B4 +#define CONTROL_PADCONF_GPMC_nCS4 0x00B6 +#define CONTROL_PADCONF_GPMC_nCS5 0x00B8 +#define CONTROL_PADCONF_GPMC_nCS6 0x00BA +#define CONTROL_PADCONF_GPMC_nCS7 0x00BC +#define CONTROL_PADCONF_GPMC_CLK 0x00BE +#define CONTROL_PADCONF_GPMC_nADV_ALE 0x00C0 +#define CONTROL_PADCONF_GPMC_nOE 0x00C2 +#define CONTROL_PADCONF_GPMC_nWE 0x00C4 +#define CONTROL_PADCONF_GPMC_nBE0_CLE 0x00C6 +#define CONTROL_PADCONF_GPMC_nBE1 0x00C8 +#define CONTROL_PADCONF_GPMC_nWP 0x00CA +#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC +#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE +#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 +#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 +/*DSS*/ +#define CONTROL_PADCONF_DSS_PCLK 0x00D4 +#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 +#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 +#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA + +#if defined(CONFIG_OMAP36XX) +#define CONTROL_PADCONF_DSS_DATA0 0x0100 /* dss_data18 */ +#define CONTROL_PADCONF_DSS_DATA1 0x0102 /* dss_data19 */ +#define CONTROL_PADCONF_DSS_DATA2 0x0104 /* dss_data20 */ +#define CONTROL_PADCONF_DSS_DATA3 0x0106 /* dss_data21 */ +#define CONTROL_PADCONF_DSS_DATA4 0x0108 /* dss_data22 */ +#define CONTROL_PADCONF_DSS_DATA5 0x010A /* dss_data23 */ +#else +#define CONTROL_PADCONF_DSS_DATA0 0x00DC +#define CONTROL_PADCONF_DSS_DATA1 0x00DE +#define CONTROL_PADCONF_DSS_DATA2 0x00E0 +#define CONTROL_PADCONF_DSS_DATA3 0x00E2 +#define CONTROL_PADCONF_DSS_DATA4 0x00E4 +#define CONTROL_PADCONF_DSS_DATA5 0x00E6 +#endif +#define CONTROL_PADCONF_DSS_DATA6 0x00E8 +#define CONTROL_PADCONF_DSS_DATA7 0x00EA +#define CONTROL_PADCONF_DSS_DATA8 0x00EC +#define CONTROL_PADCONF_DSS_DATA9 0x00EE +#define CONTROL_PADCONF_DSS_DATA10 0x00F0 +#define CONTROL_PADCONF_DSS_DATA11 0x00F2 +#define CONTROL_PADCONF_DSS_DATA12 0x00F4 +#define CONTROL_PADCONF_DSS_DATA13 0x00F6 +#define CONTROL_PADCONF_DSS_DATA14 0x00F8 +#define CONTROL_PADCONF_DSS_DATA15 0x00FA +#define CONTROL_PADCONF_DSS_DATA16 0x00FC +#define CONTROL_PADCONF_DSS_DATA17 0x00FE +#if defined(CONFIG_OMAP36XX) +#define CONTROL_PADCONF_DSS_DATA18 0x0A0A /* sys_boot0, gpio2 */ +#define CONTROL_PADCONF_DSS_DATA19 0x0A0C /* sys_boot1, gpio3 */ +#define CONTROL_PADCONF_DSS_DATA20 0x0A10 /* sys_boot3, gpio5 */ +#define CONTROL_PADCONF_DSS_DATA21 0x0A12 /* sys_boot4, gpio6 */ +#define CONTROL_PADCONF_DSS_DATA22 0x0A14 /* sys_boot5, gpio7 */ +#define CONTROL_PADCONF_DSS_DATA23 0x0A16 /* sys_boot6, gpio8 */ +#else +#define CONTROL_PADCONF_DSS_DATA18 0x0100 +#define CONTROL_PADCONF_DSS_DATA19 0x0102 +#define CONTROL_PADCONF_DSS_DATA20 0x0104 +#define CONTROL_PADCONF_DSS_DATA21 0x0106 +#define CONTROL_PADCONF_DSS_DATA22 0x0108 +#define CONTROL_PADCONF_DSS_DATA23 0x010A +#endif +/*CAMERA*/ +#define CONTROL_PADCONF_CAM_HS 0x010C +#define CONTROL_PADCONF_CAM_VS 0x010E +#define CONTROL_PADCONF_CAM_XCLKA 0x0110 +#define CONTROL_PADCONF_CAM_PCLK 0x0112 +#define CONTROL_PADCONF_CAM_FLD 0x0114 +#define CONTROL_PADCONF_CAM_D0 0x0116 +#define CONTROL_PADCONF_CAM_D1 0x0118 +#define CONTROL_PADCONF_CAM_D2 0x011A +#define CONTROL_PADCONF_CAM_D3 0x011C +#define CONTROL_PADCONF_CAM_D4 0x011E +#define CONTROL_PADCONF_CAM_D5 0x0120 +#define CONTROL_PADCONF_CAM_D6 0x0122 +#define CONTROL_PADCONF_CAM_D7 0x0124 +#define CONTROL_PADCONF_CAM_D8 0x0126 +#define CONTROL_PADCONF_CAM_D9 0x0128 +#define CONTROL_PADCONF_CAM_D10 0x012A +#define CONTROL_PADCONF_CAM_D11 0x012C +#define CONTROL_PADCONF_CAM_XCLKB 0x012E +#define CONTROL_PADCONF_CAM_WEN 0x0130 +#define CONTROL_PADCONF_CAM_STROBE 0x0132 +#define CONTROL_PADCONF_CSI2_DX0 0x0134 +#define CONTROL_PADCONF_CSI2_DY0 0x0136 +#define CONTROL_PADCONF_CSI2_DX1 0x0138 +#define CONTROL_PADCONF_CSI2_DY1 0x013A +/*Audio Interface */ +#define CONTROL_PADCONF_McBSP2_FSX 0x013C +#define CONTROL_PADCONF_McBSP2_CLKX 0x013E +#define CONTROL_PADCONF_McBSP2_DR 0x0140 +#define CONTROL_PADCONF_McBSP2_DX 0x0142 +#define CONTROL_PADCONF_ +#define CONTROL_PADCONF_MMC1_CLK 0x0144 +#define CONTROL_PADCONF_MMC1_CMD 0x0146 +#define CONTROL_PADCONF_MMC1_DAT0 0x0148 +#define CONTROL_PADCONF_MMC1_DAT1 0x014A +#define CONTROL_PADCONF_MMC1_DAT2 0x014C +#define CONTROL_PADCONF_MMC1_DAT3 0x014E +#define CONTROL_PADCONF_MMC1_DAT4 0x0150 +#define CONTROL_PADCONF_MMC1_DAT5 0x0152 +#define CONTROL_PADCONF_MMC1_DAT6 0x0154 +#define CONTROL_PADCONF_MMC1_DAT7 0x0156 +/*Wireless LAN */ +#define CONTROL_PADCONF_MMC2_CLK 0x0158 +#define CONTROL_PADCONF_MMC2_CMD 0x015A +#define CONTROL_PADCONF_MMC2_DAT0 0x015C +#define CONTROL_PADCONF_MMC2_DAT1 0x015E +#define CONTROL_PADCONF_MMC2_DAT2 0x0160 +#define CONTROL_PADCONF_MMC2_DAT3 0x0162 +#define CONTROL_PADCONF_MMC2_DAT4 0x0164 +#define CONTROL_PADCONF_MMC2_DAT5 0x0166 +#define CONTROL_PADCONF_MMC2_DAT6 0x0168 +#define CONTROL_PADCONF_MMC2_DAT7 0x016A +/*Bluetooth*/ +#define CONTROL_PADCONF_McBSP3_DX 0x016C +#define CONTROL_PADCONF_McBSP3_DR 0x016E +#define CONTROL_PADCONF_McBSP3_CLKX 0x0170 +#define CONTROL_PADCONF_McBSP3_FSX 0x0172 +#define CONTROL_PADCONF_UART2_CTS 0x0174 +#define CONTROL_PADCONF_UART2_RTS 0x0176 +#define CONTROL_PADCONF_UART2_TX 0x0178 +#define CONTROL_PADCONF_UART2_RX 0x017A +/*Modem Interface */ +#define CONTROL_PADCONF_UART1_TX 0x017C +#define CONTROL_PADCONF_UART1_RTS 0x017E +#define CONTROL_PADCONF_UART1_CTS 0x0180 +#define CONTROL_PADCONF_UART1_RX 0x0182 +#define CONTROL_PADCONF_McBSP4_CLKX 0x0184 +#define CONTROL_PADCONF_McBSP4_DR 0x0186 +#define CONTROL_PADCONF_McBSP4_DX 0x0188 +#define CONTROL_PADCONF_McBSP4_FSX 0x018A +#define CONTROL_PADCONF_McBSP1_CLKR 0x018C +#define CONTROL_PADCONF_McBSP1_FSR 0x018E +#define CONTROL_PADCONF_McBSP1_DX 0x0190 +#define CONTROL_PADCONF_McBSP1_DR 0x0192 +#define CONTROL_PADCONF_McBSP_CLKS 0x0194 +#define CONTROL_PADCONF_McBSP1_FSX 0x0196 +#define CONTROL_PADCONF_McBSP1_CLKX 0x0198 +/*Serial Interface*/ +#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A +#define CONTROL_PADCONF_UART3_RTS_SD 0x019C +#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E +#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 +#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 +#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 +#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 +#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 +#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA +#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC +#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE +#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 +#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 +#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 +#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 +#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 +#define CONTROL_PADCONF_I2C1_SCL 0x01BA +#define CONTROL_PADCONF_I2C1_SDA 0x01BC +#define CONTROL_PADCONF_I2C2_SCL 0x01BE +#define CONTROL_PADCONF_I2C2_SDA 0x01C0 +#define CONTROL_PADCONF_I2C3_SCL 0x01C2 +#define CONTROL_PADCONF_I2C3_SDA 0x01C4 +#define CONTROL_PADCONF_I2C4_SCL 0x0A00 +#define CONTROL_PADCONF_I2C4_SDA 0x0A02 +#define CONTROL_PADCONF_HDQ_SIO 0x01C6 +#define CONTROL_PADCONF_McSPI1_CLK 0x01C8 +#define CONTROL_PADCONF_McSPI1_SIMO 0x01CA +#define CONTROL_PADCONF_McSPI1_SOMI 0x01CC +#define CONTROL_PADCONF_McSPI1_CS0 0x01CE +#define CONTROL_PADCONF_McSPI1_CS1 0x01D0 +#define CONTROL_PADCONF_McSPI1_CS2 0x01D2 +#define CONTROL_PADCONF_McSPI1_CS3 0x01D4 +#define CONTROL_PADCONF_McSPI2_CLK 0x01D6 +#define CONTROL_PADCONF_McSPI2_SIMO 0x01D8 +#define CONTROL_PADCONF_McSPI2_SOMI 0x01DA +#define CONTROL_PADCONF_McSPI2_CS0 0x01DC +#define CONTROL_PADCONF_McSPI2_CS1 0x01DE +/*Control and debug */ +#define CONTROL_PADCONF_SYS_32K 0x0A04 +#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 +#define CONTROL_PADCONF_SYS_nIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A +#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C +#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E +#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 +#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 +#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 +#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 +#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 +#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A +#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 +#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_TCK 0x0A1E +#define CONTROL_PADCONF_JTAG_TMS 0x0A20 +#define CONTROL_PADCONF_JTAG_TDI 0x0A22 +#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 +#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 +#define CONTROL_PADCONF_ETK_CLK 0x0A28 +#define CONTROL_PADCONF_ETK_CTL 0x0A2A +#define CONTROL_PADCONF_ETK_D0 0x0A2C +#define CONTROL_PADCONF_ETK_D1 0x0A2E +#define CONTROL_PADCONF_ETK_D2 0x0A30 +#define CONTROL_PADCONF_ETK_D3 0x0A32 +#define CONTROL_PADCONF_ETK_D4 0x0A34 +#define CONTROL_PADCONF_ETK_D5 0x0A36 +#define CONTROL_PADCONF_ETK_D6 0x0A38 +#define CONTROL_PADCONF_ETK_D7 0x0A3A +#define CONTROL_PADCONF_ETK_D8 0x0A3C +#define CONTROL_PADCONF_ETK_D9 0x0A3E +#define CONTROL_PADCONF_ETK_D10 0x0A40 +#define CONTROL_PADCONF_ETK_D11 0x0A42 +#define CONTROL_PADCONF_ETK_D12 0x0A44 +#define CONTROL_PADCONF_ETK_D13 0x0A46 +#define CONTROL_PADCONF_ETK_D14 0x0A48 +#define CONTROL_PADCONF_ETK_D15 0x0A4A + +#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 +#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA +#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC +#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE +#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 +#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 +#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 +#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 +#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 +#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA +#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC +#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE +#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 +#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 +#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 +#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 +#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 +#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA + +/*Die to Die */ +#define CONTROL_PADCONF_d2d_mcad0 0x01E4 +#define CONTROL_PADCONF_d2d_mcad1 0x01E6 +#define CONTROL_PADCONF_d2d_mcad2 0x01E8 +#define CONTROL_PADCONF_d2d_mcad3 0x01EA +#define CONTROL_PADCONF_d2d_mcad4 0x01EC +#define CONTROL_PADCONF_d2d_mcad5 0x01EE +#define CONTROL_PADCONF_d2d_mcad6 0x01F0 +#define CONTROL_PADCONF_d2d_mcad7 0x01F2 +#define CONTROL_PADCONF_d2d_mcad8 0x01F4 +#define CONTROL_PADCONF_d2d_mcad9 0x01F6 +#define CONTROL_PADCONF_d2d_mcad10 0x01F8 +#define CONTROL_PADCONF_d2d_mcad11 0x01FA +#define CONTROL_PADCONF_d2d_mcad12 0x01FC +#define CONTROL_PADCONF_d2d_mcad13 0x01FE +#define CONTROL_PADCONF_d2d_mcad14 0x0200 +#define CONTROL_PADCONF_d2d_mcad15 0x0202 +#define CONTROL_PADCONF_d2d_mcad16 0x0204 +#define CONTROL_PADCONF_d2d_mcad17 0x0206 +#define CONTROL_PADCONF_d2d_mcad18 0x0208 +#define CONTROL_PADCONF_d2d_mcad19 0x020A +#define CONTROL_PADCONF_d2d_mcad20 0x020C +#define CONTROL_PADCONF_d2d_mcad21 0x020E +#define CONTROL_PADCONF_d2d_mcad22 0x0210 +#define CONTROL_PADCONF_d2d_mcad23 0x0212 +#define CONTROL_PADCONF_d2d_mcad24 0x0214 +#define CONTROL_PADCONF_d2d_mcad25 0x0216 +#define CONTROL_PADCONF_d2d_mcad26 0x0218 +#define CONTROL_PADCONF_d2d_mcad27 0x021A +#define CONTROL_PADCONF_d2d_mcad28 0x021C +#define CONTROL_PADCONF_d2d_mcad29 0x021E +#define CONTROL_PADCONF_d2d_mcad30 0x0220 +#define CONTROL_PADCONF_d2d_mcad31 0x0222 +#define CONTROL_PADCONF_d2d_mcad32 0x0224 +#define CONTROL_PADCONF_d2d_mcad33 0x0226 +#define CONTROL_PADCONF_d2d_mcad34 0x0228 +#define CONTROL_PADCONF_d2d_mcad35 0x022A +#define CONTROL_PADCONF_d2d_mcad36 0x022C +#define CONTROL_PADCONF_d2d_clk26mi 0x022E +#define CONTROL_PADCONF_d2d_nrespwron 0x0230 +#define CONTROL_PADCONF_d2d_nreswarm 0x0232 +#define CONTROL_PADCONF_d2d_arm9nirq 0x0234 +#define CONTROL_PADCONF_d2d_uma2p6fiq 0x0236 +#define CONTROL_PADCONF_d2d_spint 0x0238 +#define CONTROL_PADCONF_d2d_frint 0x023A +#define CONTROL_PADCONF_d2d_dmareq0 0x023C +#define CONTROL_PADCONF_d2d_dmareq1 0x023E +#define CONTROL_PADCONF_d2d_dmareq2 0x0240 +#define CONTROL_PADCONF_d2d_dmareq3 0x0242 +#define CONTROL_PADCONF_d2d_n3gtrst 0x0244 +#define CONTROL_PADCONF_d2d_n3gtdi 0x0246 +#define CONTROL_PADCONF_d2d_n3gtdo 0x0248 +#define CONTROL_PADCONF_d2d_n3gtms 0x024A +#define CONTROL_PADCONF_d2d_n3gtck 0x024C +#define CONTROL_PADCONF_d2d_n3grtck 0x024E +#define CONTROL_PADCONF_d2d_mstdby 0x0250 +#define CONTROL_PADCONF_d2d_swakeup 0x0A4C +#define CONTROL_PADCONF_d2d_idlereq 0x0252 +#define CONTROL_PADCONF_d2d_idleack 0x0254 +#define CONTROL_PADCONF_d2d_mwrite 0x0256 +#define CONTROL_PADCONF_d2d_swrite 0x0258 +#define CONTROL_PADCONF_d2d_mread 0x025A +#define CONTROL_PADCONF_d2d_sread 0x025C +#define CONTROL_PADCONF_d2d_mbusflag 0x025E +#define CONTROL_PADCONF_d2d_sbusflag 0x0260 +#define CONTROL_PADCONF_sdrc_cke0 0x0262 +#define CONTROL_PADCONF_sdrc_cke1 0x0264 +#define CONTROL_PADCONF_gpmc_a11 0x0266 + +#endif diff --git a/include/asm-arm/arch-omap3/omap3430.h b/include/asm-arm/arch-omap3/omap3430.h new file mode 100644 index 000000000..4890e4189 --- /dev/null +++ b/include/asm-arm/arch-omap3/omap3430.h @@ -0,0 +1,221 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP3430_SYS_H_ +#define _OMAP3430_SYS_H_ + +#include + +/* + * 3430 specific Section + */ + +/* Stuff on L3 Interconnect */ +#define SMX_APE_BASE 0x68000000 + +/* L3 Firewall */ +#define A_REQINFOPERM0 (SMX_APE_BASE + 0x05048) +#define A_READPERM0 (SMX_APE_BASE + 0x05050) +#define A_WRITEPERM0 (SMX_APE_BASE + 0x05058) + +/* GPMC */ +#define OMAP34XX_GPMC_BASE (0x6E000000) + +/* SMS */ +#define OMAP34XX_SMS_BASE 0x6C000000 + +/* SDRC */ +#define OMAP34XX_SDRC_BASE 0x6D000000 + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 + +#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 + +#define OMAP34XX_L4_PER 0x49000000 + +#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE + +/* CONTROL */ +#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE+0x2000) + +/* TAP information dont know for 3430*/ +#define OMAP34XX_TAP_BASE (0x49000000) /*giving some junk for virtio */ + +/* UART */ +#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE+0x6a000) +#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE+0x6c000) +#define OMAP34XX_UART3 (OMAP34XX_L4_PER+0x20000) +#define OMAP34XX_UART4 (OMAP34XX_L4_PER+0x42000) + +/* General Purpose Timers */ +#define OMAP34XX_GPT1 0x48318000 +#define OMAP34XX_GPT2 0x49032000 +#define OMAP34XX_GPT3 0x49034000 +#define OMAP34XX_GPT4 0x49036000 +#define OMAP34XX_GPT5 0x49038000 +#define OMAP34XX_GPT6 0x4903A000 +#define OMAP34XX_GPT7 0x4903C000 +#define OMAP34XX_GPT8 0x4903E000 +#define OMAP34XX_GPT9 0x49040000 +#define OMAP34XX_GPT10 0x48086000 +#define OMAP34XX_GPT11 0x48088000 +#define OMAP34XX_GPT12 0x48304000 + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE (0x4830C000) +#define WD2_BASE (0x48314000) +#define WD3_BASE (0x49030000) + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE (0x48320000) +#define S32K_CR (SYNC_32KTIMER_BASE+0x10) + +/* OMAP3 GPIO registers */ +#define OMAP34XX_GPIO1_BASE 0x48310000 +#define OMAP34XX_GPIO2_BASE 0x49050000 +#define OMAP34XX_GPIO3_BASE 0x49052000 +#define OMAP34XX_GPIO4_BASE 0x49054000 +#define OMAP34XX_GPIO5_BASE 0x49056000 +#define OMAP34XX_GPIO6_BASE 0x49058000 +#define OMAP34XX_GPIO_OE 0x34 +#define OMAP34XX_GPIO_DATAIN 0x38 +#define OMAP34XX_GPIO_DATAOUT 0x3C + +#ifndef __ASSEMBLY__ +typedef struct gpio { + unsigned char res1[0x34]; + unsigned int oe; /* 0x34 */ + unsigned int datain; /* 0x38 */ + unsigned char res2[0x54]; + unsigned int cleardataout; /* 0x90 */ + unsigned int setdataout; /* 0x94 */ +} gpio_t; +#endif + +#define GPIO0 (0x1 << 0) +#define GPIO1 (0x1 << 1) +#define GPIO2 (0x1 << 2) +#define GPIO3 (0x1 << 3) +#define GPIO4 (0x1 << 4) +#define GPIO5 (0x1 << 5) +#define GPIO6 (0x1 << 6) +#define GPIO7 (0x1 << 7) +#define GPIO8 (0x1 << 8) +#define GPIO9 (0x1 << 9) +#define GPIO10 (0x1 << 10) +#define GPIO11 (0x1 << 11) +#define GPIO12 (0x1 << 12) +#define GPIO13 (0x1 << 13) +#define GPIO14 (0x1 << 14) +#define GPIO15 (0x1 << 15) +#define GPIO16 (0x1 << 16) +#define GPIO17 (0x1 << 17) +#define GPIO18 (0x1 << 18) +#define GPIO19 (0x1 << 19) +#define GPIO20 (0x1 << 20) +#define GPIO21 (0x1 << 21) +#define GPIO22 (0x1 << 22) +#define GPIO23 (0x1 << 23) +#define GPIO24 (0x1 << 24) +#define GPIO25 (0x1 << 25) +#define GPIO26 (0x1 << 26) +#define GPIO27 (0x1 << 27) +#define GPIO28 (0x1 << 28) +#define GPIO29 (0x1 << 29) +#define GPIO30 (0x1 << 30) +#define GPIO31 (0x1 << 31) + +/* CM_FCLKEN_PER and CM_ICLKEN_PER */ +#define CLKEN_PER_EN_GPIO6_BIT 17 +#define CLKEN_PER_EN_GPIO5_BIT 16 +#define CLKEN_PER_EN_GPIO4_BIT 15 +#define CLKEN_PER_EN_GPIO3_BIT 14 +#define CLKEN_PER_EN_GPIO2_BIT 13 +#define CLKEN_PER_EN_WDT3_BIT 12 +#define CLKEN_PER_EN_UART3_BIT 11 +#define CLKEN_PER_EN_GPT9_BIT 10 +#define CLKEN_PER_EN_GPT8_BIT 9 +#define CLKEN_PER_EN_GPT7_BIT 8 +#define CLKEN_PER_EN_GPT6_BIT 7 +#define CLKEN_PER_EN_GPT5_BIT 6 +#define CLKEN_PER_EN_GPT4_BIT 5 +#define CLKEN_PER_EN_GPT3_BIT 4 +#define CLKEN_PER_EN_GPT2_BIT 3 +#define CLKEN_PER_EN_MCBSP4_BIT 2 +#define CLKEN_PER_EN_MCBSP3_BIT 1 +#define CLKEN_PER_EN_MCBSP2_BIT 0 + +/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP */ +#define CLKEN_WKUP_EN_WDT2_BIT 5 +#define CLKEN_WKUP_EN_GPIO1_BIT 3 +#define CLKEN_WKUP_EN_GPT1_BIT 0 + +/* + * SDP3430 specific Section + */ + +/* + * The 343x's chip selects are programmable. The mask ROM + * does configure CS0 to 0x08000000 before dispatch. So, if + * you want your code to live below that address, you have to + * be prepared to jump though hoops, to reset the base address. + * Same as in SDP3430 + */ +#ifdef CONFIG_OMAP34XX +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC +#endif + +#if defined(CONFIG_3430SDP) || defined(CONFIG_3630SDP) +/* FPGA on Debug board.*/ +# define ETH_CONTROL_REG (DEBUG_BASE+0x30b) +# define LAN_RESET_REGISTER (DEBUG_BASE+0x1c) + +# define DIP_SWITCH_INPUT_REG2 (DEBUG_BASE+0x60) +# define LED_REGISTER (DEBUG_BASE+0x40) +# define FPGA_REV_REGISTER (DEBUG_BASE+0x10) +# define EEPROM_MAIN_BRD (DEBUG_BASE+0x10000+0x1800) +# define EEPROM_CONN_BRD (DEBUG_BASE+0x10000+0x1900) +# define EEPROM_UI_BRD (DEBUG_BASE+0x10000+0x1A00) +# define EEPROM_MCAM_BRD (DEBUG_BASE+0x10000+0x1B00) +# define ENHANCED_UI_EE_NAME "750-2075" +#endif + +#define FLIP_FLOP_LOCATION (OMAP34XX_CTRL_BASE + 0x09FC) +#define FLIP_FLOP_BIT 31 +#define EPICFAIL_BIT 30 + +#define GLOBAL_COLD_RST (1 << 0) +#define GLOBAL_SW_RST (1 << 1) +#define MPU_WD_RST (1 << 4) + +#endif /* _OMAP3430_SYS_H_ */ diff --git a/include/asm-arm/arch-omap3/rev.h b/include/asm-arm/arch-omap3/rev.h new file mode 100644 index 000000000..cd325fb73 --- /dev/null +++ b/include/asm-arm/arch-omap3/rev.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * + * Richard Woodruff + * Syed Mohammed Khasim + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP34XX_REV_H_ +#define _OMAP34XX_REV_H_ + +#define CDB_DDR_COMBO /* combo part on cpu daughter card */ +#define CDB_DDR_IPDB /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_3430 0x3430 + +/* + * 343x real hardware: + * ES1 = rev 0 + * + * ES2 onwards, the value maps to contents of IDCODE register [31:28]. + */ +#define CPU_3XX_ES10 0 +#define CPU_3XX_ES20 1 +#define CPU_3XX_ES21 2 +#define CPU_3XX_ES30 3 +#define CPU_3XX_ES31 4 +#define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1) + +#define CPU_3XX_ID_SHIFT 28 + +#endif diff --git a/include/asm-arm/arch-omap3/sizes.h b/include/asm-arm/arch-omap3/sizes.h new file mode 100644 index 000000000..aaba18f15 --- /dev/null +++ b/include/asm-arm/arch-omap3/sizes.h @@ -0,0 +1,49 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +/* Size defintions + * Copyright (C) ARM Limited 1998. All rights reserved. + */ + +#ifndef __sizes_h +#define __sizes_h 1 + +/* handy sizes */ +#define SZ_1K 0x00000400 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_31M 0x01F00000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#endif /* __sizes_h */ diff --git a/include/asm-arm/arch-omap3/sys_info.h b/include/asm-arm/arch-omap3/sys_info.h new file mode 100644 index 000000000..0b51eccac --- /dev/null +++ b/include/asm-arm/arch-omap3/sys_info.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP34XX_SYS_INFO_H_ +#define _OMAP34XX_SYS_INFO_H_ + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +/* Currently Virtio models this one */ +#define CPU_3430_CHIPID 0x0B68A000 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define I2C_MENELAUS 0x72 /* i2c id for companion chip */ +#define I2C_TRITON2 0x4B /* addres of power group */ + +#define BOOT_FAST_XIP 0x1f + +/* SDP definitions according to FPGA Rev. Is this OK?? */ +#define SDP_3430_V1 0x1 +#define SDP_3430_V2 0x2 + +#define BOARD_3430_LABRADOR 0x80 +#define BOARD_3430_LABRADOR_V1 0x1 + +#endif diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h new file mode 100644 index 000000000..18a037c8c --- /dev/null +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP34XX_SYS_PROTO_H_ +#define _OMAP34XX_SYS_PROTO_H_ + +void prcm_init(void); +void per_clocks_enable(void); + +void memif_init(void); +void sdrc_init(void); +void do_sdrc_init(u32,u32); +void gpmc_init(void); + +void ether_init(void); +void watchdog_init(void); +void set_muxconf_regs(void); + +u32 get_cpu_type(void); +u32 get_cpu_rev(void); +u32 cpu_is_3410(void); +u32 get_mem_type(void); +inline u32 get_sysboot_value(void); +u32 get_gpmc0_base(void); +u32 is_gpmc_muxed(void); +u32 get_gpmc0_type(void); +u32 get_gpmc0_width(void); +u32 get_board_type(void); +void display_board_info(u32); +void update_mux(u32,u32); +u32 get_sdr_cs_size(u32 offset); +u32 running_in_sdram(void); +u32 running_in_sram(void); +u32 running_in_flash(void); +u32 running_from_internal_boot(void); +u32 get_device_type(void); + +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); +void sdelay(unsigned long loops); +void dieid_num_r(void); + +#endif diff --git a/include/asm-arm/arch-omap3/usb34xx.h b/include/asm-arm/arch-omap3/usb34xx.h new file mode 100644 index 000000000..26956ba66 --- /dev/null +++ b/include/asm-arm/arch-omap3/usb34xx.h @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2008 + * Windriver + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP34XX_USB_H_ +#define _OMAP34XX_USB_H_ + +#include "omap3430.h" +#include "musb_regs.h" + +#define OMAP34XX_USB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) +#define OMAP34XX_OTG_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB400) + +/* Remap musb */ + +#define OMAP34XX_USB_FADDR (OMAP34XX_USB_BASE + MUSB_FADDR) +#define OMAP34XX_USB_POWER (OMAP34XX_USB_BASE + MUSB_POWER) +#define OMAP34XX_USB_INTRTX (OMAP34XX_USB_BASE + MUSB_INTRTX) +#define OMAP34XX_USB_INTRRX (OMAP34XX_USB_BASE + MUSB_INTRRX) +#define OMAP34XX_USB_INTRTXE (OMAP34XX_USB_BASE + MUSB_INTRTXE) +#define OMAP34XX_USB_INTRRXE (OMAP34XX_USB_BASE + MUSB_INTRRXE) +#define OMAP34XX_USB_INTRUSB (OMAP34XX_USB_BASE + MUSB_INTRUSB) +#define OMAP34XX_USB_INTRUSBE (OMAP34XX_USB_BASE + MUSB_INTRUSBE) +#define OMAP34XX_USB_FRAME (OMAP34XX_USB_BASE + MUSB_FRAME) +#define OMAP34XX_USB_INDEX (OMAP34XX_USB_BASE + MUSB_INDEX) +#define OMAP34XX_USB_TESTMODE (OMAP34XX_USB_BASE + MUSB_TESTMODE) + +#define OMAP34XX_USB_EP(n) (OMAP34XX_USB_BASE + 0x100 + 0x10*(n)) +#define OMAP34XX_USB_TXMAXP(n) (OMAP34XX_USB_EP(n) + MUSB_TXMAXP) +#define OMAP34XX_USB_TXCSR(n) (OMAP34XX_USB_EP(n) + MUSB_TXCSR) +#define OMAP34XX_USB_RXMAXP(n) (OMAP34XX_USB_EP(n) + MUSB_RXMAXP) +#define OMAP34XX_USB_RXCSR(n) (OMAP34XX_USB_EP(n) + MUSB_RXCSR) +#define OMAP34XX_USB_RXCOUNT(n) (OMAP34XX_USB_EP(n) + MUSB_RXCOUNT) +#define OMAP34XX_USB_TXTYPE(n) (OMAP34XX_USB_EP(n) + MUSB_TXTYPE) +#define OMAP34XX_USB_TXINTERVAL(n) (OMAP34XX_USB_EP(n) + MUSB_TXINTERVAL) +#define OMAP34XX_USB_RXTYPE(n) (OMAP34XX_USB_EP(n) + MUSB_RXTYPE) +#define OMAP34XX_USB_RXINTERVAL(n) (OMAP34XX_USB_EP(n) + MUSB_RXINTERVAL) +#define OMAP34XX_USB_FIFOSIZE(n) (OMAP34XX_USB_EP(n) + MUSB_FIFOSIZE) + +#define OMAP34XX_USB_TXFIFOSZ (OMAP34XX_USB_BASE + MUSB_TXFIFOSZ) +#define OMAP34XX_USB_RXFIFOSZ (OMAP34XX_USB_BASE + MUSB_RXFIFOSZ) +#define OMAP34XX_USB_TXFIFOADD (OMAP34XX_USB_BASE + MUSB_TXFIFOADD) +#define OMAP34XX_USB_RXFIFOADD (OMAP34XX_USB_BASE + MUSB_RXFIFOADD) + +#define OMAP34XX_USB_CSR0 (OMAP34XX_USB_TXCSR(0)) +#define OMAP34XX_USB_COUNT0 (OMAP34XX_USB_RXCOUNT(0)) +#define OMAP34XX_USB_TYPE0 (OMAP34XX_USB_TXTYPE(0)) +#define OMAP34XX_USB_NAKLIMIT0 (OMAP34XX_USB_TXINTERVAL(0)) +#define OMAP34XX_USB_CONFIGDATA (OMAP34XX_USB_FIFOSIZE(0)) + +#define OMAP34XX_USB_FIFO(n) (OMAP34XX_USB_BASE + 0x20 + ((n) * 4)) +#define OMAP34XX_USB_FIFO_0 (OMAP34XX_USB_FIFO(0)) + +#define OMAP34XX_USB_DEVCTL (OMAP34XX_USB_BASE + MUSB_DEVCTL) + + +#define OMAP34XX_USB_INTRUSB_VBUSERR (1 << 7) +#define OMAP34XX_USB_INTRUSB_SESSREQ (1 << 6) +#define OMAP34XX_USB_INTRUSB_DISCON (1 << 5) +#define OMAP34XX_USB_INTRUSB_CONN (1 << 4) +#define OMAP34XX_USB_INTRUSB_SOF (1 << 3) +#define OMAP34XX_USB_INTRUSB_RESET_BABBLE (1 << 2) +#define OMAP34XX_USB_INTRUSB_RESUME (1 << 1) +#define OMAP34XX_USB_INTRUSB_SUSPEND (1 << 0) +#define OMAP34XX_USB_INTRUSB_ALL 0xff + +#define OMAP34XX_USB_INTRTX_EP_15 (1 << 15) +#define OMAP34XX_USB_INTRTX_EP_14 (1 << 14) +#define OMAP34XX_USB_INTRTX_EP_13 (1 << 13) +#define OMAP34XX_USB_INTRTX_EP_12 (1 << 12) +#define OMAP34XX_USB_INTRTX_EP_11 (1 << 11) +#define OMAP34XX_USB_INTRTX_EP_10 (1 << 10) +#define OMAP34XX_USB_INTRTX_EP_9 (1 << 9) +#define OMAP34XX_USB_INTRTX_EP_8 (1 << 8) +#define OMAP34XX_USB_INTRTX_EP_7 (1 << 7) +#define OMAP34XX_USB_INTRTX_EP_6 (1 << 6) +#define OMAP34XX_USB_INTRTX_EP_5 (1 << 5) +#define OMAP34XX_USB_INTRTX_EP_4 (1 << 4) +#define OMAP34XX_USB_INTRTX_EP_3 (1 << 3) +#define OMAP34XX_USB_INTRTX_EP_2 (1 << 2) +#define OMAP34XX_USB_INTRTX_EP_1 (1 << 1) +#define OMAP34XX_USB_INTRTX_EP_0 (1 << 0) +#define OMAP34XX_USB_INTRTX_EP_ALL 0xffff + +#define OMAP34XX_USB_INTRRX_EP_15 (1 << 15) +#define OMAP34XX_USB_INTRRX_EP_14 (1 << 14) +#define OMAP34XX_USB_INTRRX_EP_13 (1 << 13) +#define OMAP34XX_USB_INTRRX_EP_12 (1 << 12) +#define OMAP34XX_USB_INTRRX_EP_11 (1 << 11) +#define OMAP34XX_USB_INTRRX_EP_10 (1 << 10) +#define OMAP34XX_USB_INTRRX_EP_9 (1 << 9) +#define OMAP34XX_USB_INTRRX_EP_8 (1 << 8) +#define OMAP34XX_USB_INTRRX_EP_7 (1 << 7) +#define OMAP34XX_USB_INTRRX_EP_6 (1 << 6) +#define OMAP34XX_USB_INTRRX_EP_5 (1 << 5) +#define OMAP34XX_USB_INTRRX_EP_4 (1 << 4) +#define OMAP34XX_USB_INTRRX_EP_3 (1 << 3) +#define OMAP34XX_USB_INTRRX_EP_2 (1 << 2) +#define OMAP34XX_USB_INTRRX_EP_1 (1 << 1) +/* 0 is reserved */ +#define OMAP34XX_USB_INTRRX_EP_ALL 0xfffe + +/* DMA Control Registers */ +#define OMAP34XX_USB_DMA_INTR (OMAP34XX_USB_BASE + MUSB_DMA_INTR) +#define OMAP34XX_USB_DMA_CNTL_CH(n) (OMAP34XX_USB_BASE + MUSB_DMA_CNTL_CH(n)) +#define OMAP34XX_USB_DMA_ADDR_CH(n) (OMAP34XX_USB_BASE + MUSB_DMA_ADDR_CH(n)) +#define OMAP34XX_USB_DMA_COUNT_CH(n) (OMAP34XX_USB_BASE + MUSB_DMA_COUNT_CH(n)) + +/* OTG */ +#define OMAP34XX_OTG_REVISION (OMAP34XX_OTG_BASE + 0x00) +#define OMAP34XX_OTG_SYSCONFIG (OMAP34XX_OTG_BASE + 0x04) +#define OMAP34XX_OTG_SYSSTATUS (OMAP34XX_OTG_BASE + 0x08) +#define OMAP34XX_OTG_INTERFSEL (OMAP34XX_OTG_BASE + 0x0C) +#define OMAP34XX_OTG_FORCESTDBY (OMAP34XX_OTG_BASE + 0x14) + +#define OMAP34XX_OTG_SYSCONFIG_SMART_STANDBY_MODE 0x2000 +#define OMAP34XX_OTG_SYSCONFIG_NO_STANDBY_MODE 0x1000 +#define OMAP34XX_OTG_SYSCONFIG_SMART_IDLE_MODE 0x0010 +#define OMAP34XX_OTG_SYSCONFIG_NO_IDLE_MODE 0x0008 +#define OMAP34XX_OTG_SYSCONFIG_ENABLEWAKEUP 0x0004 +#define OMAP34XX_OTG_SYSCONFIG_SOFTRESET 0x0002 +#define OMAP34XX_OTG_SYSCONFIG_AUTOIDLE 0x0001 + +#define OMAP34XX_OTG_SYSSTATUS_RESETDONE 0x0001 + +#define OMAP34XX_OTG_INTERFSEL_OMAP 0x0001 + +#define OMAP34XX_OTG_FORCESTDBY_STANDBY 0x0001 + +#endif /* _OMAP34XX_USB_H_ */ diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h index 104a21c2e..2ac5ea21c 100644 --- a/include/asm-arm/arch-pxa/bitfield.h +++ b/include/asm-arm/arch-pxa/bitfield.h @@ -1,13 +1,13 @@ /* - * FILE bitfield.h + * FILE bitfield.h * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. + * Purpose Definition of macros to operate on bit fields. */ @@ -35,11 +35,11 @@ * line-size limit). * * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. * * Output - * Fld Encoded bit field. + * Fld Encoded bit field. */ #define Fld(Size, Shft) (((Size) << 16) + (Shft)) @@ -54,14 +54,14 @@ * bit field. * * Input - * Field Encoded bit field (using the macro "Fld"). + * Field Encoded bit field (using the macro "Fld"). * * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. */ #define FSize(Field) ((Field) >> 16) @@ -79,11 +79,11 @@ * former appropriately. * * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FInsrt Bit-field value positioned appropriately. + * FInsrt Bit-field value positioned appropriately. */ #define FInsrt(Value, Field) \ @@ -98,11 +98,11 @@ * shifting it appropriately. * * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FExtr Bit-field value. + * FExtr Bit-field value. */ #define FExtr(Data, Field) \ diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h index 85e144b68..a62679a1a 100644 --- a/include/asm-arm/arch-pxa/mmc.h +++ b/include/asm-arm/arch-pxa/mmc.h @@ -16,100 +16,109 @@ /* PXA-250 MMC controller registers */ /* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (0x0001UL) +#define MMC_STRPCL_STOP_CLK (0x0001UL) #define MMC_STRPCL_START_CLK (0x0002UL) /* MMC_STAT */ #define MMC_STAT_END_CMD_RES (0x0001UL << 13) -#define MMC_STAT_PRG_DONE (0x0001UL << 12) -#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) -#define MMC_STAT_CLK_EN (0x0001UL << 8) -#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) -#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) +#define MMC_STAT_PRG_DONE (0x0001UL << 12) +#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) +#define MMC_STAT_CLK_EN (0x0001UL << 8) +#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) +#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) +#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) #define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4) -#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) -#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) -#define MMC_STAT_READ_TIME_OUT (0x0001UL) +#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) +#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) +#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) +#define MMC_STAT_READ_TIME_OUT (0x0001UL) #define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\ |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\ |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR) /* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ (0x0000UL) -#define MMC_CLKRT_10MHZ (0x0001UL) -#define MMC_CLKRT_5MHZ (0x0002UL) +#define MMC_CLKRT_20MHZ (0x0000UL) +#define MMC_CLKRT_10MHZ (0x0001UL) +#define MMC_CLKRT_5MHZ (0x0002UL) #define MMC_CLKRT_2_5MHZ (0x0003UL) -#define MMC_CLKRT_1_25MHZ (0x0004UL) -#define MMC_CLKRT_0_625MHZ (0x0005UL) -#define MMC_CLKRT_0_3125MHZ (0x0006UL) +#define MMC_CLKRT_1_25MHZ (0x0004UL) +#define MMC_CLKRT_0_625MHZ (0x0005UL) +#define MMC_CLKRT_0_3125MHZ (0x0006UL) /* MMC_SPI */ -#define MMC_SPI_DISABLE (0x00UL) -#define MMC_SPI_EN (0x01UL) -#define MMC_SPI_CS_EN (0x01UL << 2) -#define MMC_SPI_CS_ADDRESS (0x01UL << 3) -#define MMC_SPI_CRC_ON (0x01UL << 1) +#define MMC_SPI_DISABLE (0x00UL) +#define MMC_SPI_EN (0x01UL) +#define MMC_SPI_CS_EN (0x01UL << 2) +#define MMC_SPI_CS_ADDRESS (0x01UL << 3) +#define MMC_SPI_CRC_ON (0x01UL << 1) /* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (0x0001UL << 8) #define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) -#define MMC_CMDAT_INIT (0x0001UL << 6) -#define MMC_CMDAT_BUSY (0x0001UL << 5) -#define MMC_CMDAT_BCR (0x0003UL << 5) +#define MMC_CMDAT_INIT (0x0001UL << 6) +#define MMC_CMDAT_BUSY (0x0001UL << 5) #define MMC_CMDAT_STREAM (0x0001UL << 4) -#define MMC_CMDAT_BLOCK (0x0000UL << 4) -#define MMC_CMDAT_WRITE (0x0001UL << 3) -#define MMC_CMDAT_READ (0x0000UL << 3) -#define MMC_CMDAT_DATA_EN (0x0001UL << 2) -#define MMC_CMDAT_R0 (0) -#define MMC_CMDAT_R1 (0x0001UL) -#define MMC_CMDAT_R2 (0x0002UL) -#define MMC_CMDAT_R3 (0x0003UL) +#define MMC_CMDAT_BLOCK (0x0000UL << 4) +#define MMC_CMDAT_WRITE (0x0001UL << 3) +#define MMC_CMDAT_READ (0x0000UL << 3) +#define MMC_CMDAT_DATA_EN (0x0001UL << 2) +#define MMC_CMDAT_R1 (0x0001UL) +#define MMC_CMDAT_R2 (0x0002UL) +#define MMC_CMDAT_R3 (0x0003UL) /* MMC_RESTO */ -#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ +#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ /* MMC_RDTO */ -#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ +#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ /* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ +#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ /* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) +#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) #define MMC_PRTBUF_BUF_FULL (0x00UL ) /* MMC_I_MASK */ #define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) #define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_MASK_STOP_CMD (0x01UL << 3) -#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) -#define MMC_I_MASK_PRG_DONE (0x01UL << 1) +#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_MASK_STOP_CMD (0x01UL << 3) +#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) +#define MMC_I_MASK_PRG_DONE (0x01UL << 1) #define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) -#define MMC_I_MASK_ALL (0x07fUL) +#define MMC_I_MASK_ALL (0x07fUL) /* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) #define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_REG_STOP_CMD (0x01UL << 3) -#define MMC_I_REG_END_CMD_RES (0x01UL << 2) -#define MMC_I_REG_PRG_DONE (0x01UL << 1) -#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) -#define MMC_I_REG_ALL (0x007fUL) +#define MMC_I_REG_STOP_CMD (0x01UL << 3) +#define MMC_I_REG_END_CMD_RES (0x01UL << 2) +#define MMC_I_REG_PRG_DONE (0x01UL << 1) +#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) +#define MMC_I_REG_ALL (0x007fUL) /* MMC_CMD */ -#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ +#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ #define CMD(x) (x) #define MMC_DEFAULT_RCA 1 #define MMC_BLOCK_SIZE 512 +#define MMC_CMD_RESET 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RCA 3 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_BLOCK 17 +#define MMC_CMD_RD_BLK_MULTI 18 +#define MMC_CMD_WRITE_BLOCK 24 + #define MMC_MAX_BLOCK_SIZE 512 #define MMC_R1_IDLE_STATE 0x01 @@ -149,41 +158,43 @@ typedef struct mmc_cid typedef struct mmc_csd { - uint8_t csd_structure:2, - spec_ver:4, - rsvd1:2; - uint8_t taac; - uint8_t nsac; - uint8_t tran_speed; - uint16_t ccc:12, - read_bl_len:4; - uint64_t read_bl_partial:1, - write_blk_misalign:1, - read_blk_misalign:1, - dsr_imp:1, - rsvd2:2, - c_size:12, - vdd_r_curr_min:3, - vdd_r_curr_max:3, - vdd_w_curr_min:3, - vdd_w_curr_max:3, - c_size_mult:3, - erase_blk_en:1, - sector_size:7, - wp_grp_size:7, - wp_grp_enable:1, - default_ecc:2, - r2w_factor:3, - write_bl_len:4, - write_bl_partial:1, - rsvd3:4, - content_prot_app:1; - uint8_t file_format_grp:1, - copy:1, - perm_write_protect:1, - tmp_write_protect:1, - file_format:2, - ecc:2; + uchar ecc:2, + file_format:2, + tmp_write_protect:1, + perm_write_protect:1, + copy:1, + file_format_grp:1; + uint64_t content_prot_app:1, + rsvd3:4, + write_bl_partial:1, + write_bl_len:4, + r2w_factor:3, + default_ecc:2, + wp_grp_enable:1, + wp_grp_size:5, + erase_grp_mult:5, + erase_grp_size:5, + c_size_mult1:3, + vdd_w_curr_max:3, + vdd_w_curr_min:3, + vdd_r_curr_max:3, + vdd_r_curr_min:3, + c_size:12, + rsvd2:2, + dsr_imp:1, + read_blk_misalign:1, + write_blk_misalign:1, + read_bl_partial:1; + + ushort read_bl_len:4, + ccc:12; + uchar tran_speed; + uchar nsac; + uchar taac; + uchar rsvd1:2, + spec_vers:4, + csd_structure:2; } mmc_csd_t; + #endif /* __MMC_PXA_P_H__ */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index e0145688e..ebda7192e 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -592,11 +592,9 @@ typedef void (*ExcpHndlr) (void) ; #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ - /* * USB Device Controller */ -#ifndef CONFIG_CPU_MONAHANS #define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ #define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ #define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ @@ -751,28 +749,11 @@ typedef void (*ExcpHndlr) (void) ; #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ -#endif /* ! CONFIG_CPU_MONAHANS */ - -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) - -/* - * USB Client Controller (incomplete) - */ -#define UDCCR __REG(0x40600000) -#define UDCICR0 __REG(0x40600004) -#define UDCCIR0 __REG(0x40600008) -#define UDCISR0 __REG(0x4060000c) -#define UDCSIR1 __REG(0x40600010) -#define UDCFNR __REG(0x40600014) -#define UDCOTGICR __REG(0x40600018) -#define UDCOTGISR __REG(0x4060001c) -#define UP2OCR __REG(0x40600020) -#define UP3OCR __REG(0x40600024) +#if defined(CONFIG_PXA27X) /* * USB Host Controller */ -#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */ #define UHCREV __REG(0x4C000000) #define UHCHCON __REG(0x4C000004) #define UHCCOMS __REG(0x4C000008) @@ -1288,15 +1269,15 @@ typedef void (*ExcpHndlr) (void) ; #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) -#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) -#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) -#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) -#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) -#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) -#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) -#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) -#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ - ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) +#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3) +#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3) +#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3) +#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3) +#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3) +#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3) +#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3) +#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \ + ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)) #else #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) diff --git a/include/asm-arm/arch-s3c24x0/memory.h b/include/asm-arm/arch-s3c24x0/memory.h index 5e254d235..333f21867 100644 --- a/include/asm-arm/arch-s3c24x0/memory.h +++ b/include/asm-arm/arch-s3c24x0/memory.h @@ -103,10 +103,10 @@ extern unsigned long __phys_to_virt(unsigned long ppage); * The nodes are matched with the physical memory bank addresses which are * incidentally the same as virtual addresses. * - * node 0: 0xc0000000 - 0xc7ffffff - * node 1: 0xc8000000 - 0xcfffffff - * node 2: 0xd0000000 - 0xd7ffffff - * node 3: 0xd8000000 - 0xdfffffff + * node 0: 0xc0000000 - 0xc7ffffff + * node 1: 0xc8000000 - 0xcfffffff + * node 2: 0xd0000000 - 0xd7ffffff + * node 3: 0xd8000000 - 0xdfffffff */ #define NR_NODES 4 diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h index 104a21c2e..2ac5ea21c 100644 --- a/include/asm-arm/arch-sa1100/bitfield.h +++ b/include/asm-arm/arch-sa1100/bitfield.h @@ -1,13 +1,13 @@ /* - * FILE bitfield.h + * FILE bitfield.h * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. + * Purpose Definition of macros to operate on bit fields. */ @@ -35,11 +35,11 @@ * line-size limit). * * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. * * Output - * Fld Encoded bit field. + * Fld Encoded bit field. */ #define Fld(Size, Shft) (((Size) << 16) + (Shft)) @@ -54,14 +54,14 @@ * bit field. * * Input - * Field Encoded bit field (using the macro "Fld"). + * Field Encoded bit field (using the macro "Fld"). * * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. */ #define FSize(Field) ((Field) >> 16) @@ -79,11 +79,11 @@ * former appropriately. * * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FInsrt Bit-field value positioned appropriately. + * FInsrt Bit-field value positioned appropriately. */ #define FInsrt(Value, Field) \ @@ -98,11 +98,11 @@ * shifting it appropriately. * * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FExtr Bit-field value. + * FExtr Bit-field value. */ #define FExtr(Data, Field) \ diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h index 7e2a53adb..9daf16e76 100644 --- a/include/asm-arm/global_data.h +++ b/include/asm-arm/global_data.h @@ -23,6 +23,9 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H + +#include + /* * The following data structure is placed in some memory wich is * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or @@ -48,10 +51,12 @@ typedef struct global_data { #if 0 unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; - phys_size_t ram_size; /* RAM size */ + unsigned long ram_size; /* RAM size */ unsigned long reset_status; /* reset status register at boot */ #endif void **jt; /* jump table */ + + struct tomtom_global_data tomtom; /* TomTom specific global variables */ } gd_t; /* @@ -60,9 +65,6 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index f4ae30700..648a10dd9 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -29,34 +29,6 @@ #include #endif /* XXX###XXX */ -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - /* * Generic virtual read/write. Note that we don't support half-word * read/writes. We define __arch_*[bl] here, and leave __arch_*w @@ -123,7 +95,7 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen); * only. Their primary purpose is to access PCI and ISA peripherals. * * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerous + * big endian mode connectivity is in place, as described by numerious * ARM documents: * * PCI: D0-D7 D8-D15 D16-D23 D24-D31 diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index b347857c9..835a97616 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -377,12 +377,13 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_SE4000 364 #define MACH_TYPE_QUADRICEPS 365 #define MACH_TYPE_BRONCO 366 +#define MACH_TYPE_ESL_WIRELESS_TAB 367 #define MACH_TYPE_ESL_SOFCOMP 368 #define MACH_TYPE_S5C7375 369 #define MACH_TYPE_SPEARHEAD 370 #define MACH_TYPE_PANTERA 371 #define MACH_TYPE_PRAYOGLITE 372 -#define MACH_TYPE_GUMSTIK 373 +#define MACH_TYPE_GUMSTIX 373 #define MACH_TYPE_RCUBE 374 #define MACH_TYPE_REA_OLV 375 #define MACH_TYPE_PXA_IPHONE 376 @@ -555,7 +556,6 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_BOXER 544 #define MACH_TYPE_SHEPHERD 545 #define MACH_TYPE_AML42800AA 546 -#define MACH_TYPE_MACH_TYPE_ML674001 547 #define MACH_TYPE_LPC2294 548 #define MACH_TYPE_SWITCHGRASS 549 #define MACH_TYPE_ENS_CMU 550 @@ -743,7 +743,6 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_ITE8152 735 #define MACH_TYPE_LPC3XXX 736 #define MACH_TYPE_PUPPETEER 737 -#define MACH_TYPE_MACH_VADATECH 738 #define MACH_TYPE_E570 739 #define MACH_TYPE_X50 740 #define MACH_TYPE_RECON 741 @@ -834,13 +833,13 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP_GSAMPLE 826 #define MACH_TYPE_REALVIEW_EB 827 #define MACH_TYPE_SAMOA 828 -#define MACH_TYPE_T3XSCALE 829 +#define MACH_TYPE_PALMT3 829 #define MACH_TYPE_I878 830 #define MACH_TYPE_BORZOI 831 #define MACH_TYPE_GECKO 832 #define MACH_TYPE_DS101 833 #define MACH_TYPE_OMAP_PALMTT2 834 -#define MACH_TYPE_XSCALE_PALMLD 835 +#define MACH_TYPE_PALMLD 835 #define MACH_TYPE_CC9C 836 #define MACH_TYPE_SBC1670 837 #define MACH_TYPE_IXDP28X5 838 @@ -849,7 +848,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_ARCOM_ZEUS 841 #define MACH_TYPE_OSIRIS 842 #define MACH_TYPE_MAESTRO 843 -#define MACH_TYPE_TUNGE2 844 +#define MACH_TYPE_PALMTE2 844 #define MACH_TYPE_IXBBM 845 #define MACH_TYPE_MX27ADS 846 #define MACH_TYPE_AX8004 847 @@ -890,7 +889,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMI_BOARD 882 #define MACH_TYPE_MX21CIV 883 #define MACH_TYPE_MAHI_CDAC 884 -#define MACH_TYPE_XSCALE_PALMTX 885 +#define MACH_TYPE_PALMTX 885 #define MACH_TYPE_S3C2413 887 #define MACH_TYPE_SAMSYS_EP0 888 #define MACH_TYPE_WG302V1 889 @@ -913,7 +912,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_APF9328 906 #define MACH_TYPE_OMAP_WIPOQ 907 #define MACH_TYPE_OMAP_TWIP 908 -#define MACH_TYPE_XSCALE_PALMTREO650 909 +#define MACH_TYPE_TREO650 909 #define MACH_TYPE_ACUMEN 910 #define MACH_TYPE_XP100 911 #define MACH_TYPE_FS2410 912 @@ -921,8 +920,8 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_SQ2FTLPALM 914 #define MACH_TYPE_BSEMSERVER 915 #define MACH_TYPE_NETCLIENT 916 -#define MACH_TYPE_XSCALE_PALMTT5 917 -#define MACH_TYPE_OMAP_PALMTC 918 +#define MACH_TYPE_PALMT5 917 +#define MACH_TYPE_PALMTC 918 #define MACH_TYPE_OMAP_APOLLON 919 #define MACH_TYPE_MXC30030EVB 920 #define MACH_TYPE_REA_2D 921 @@ -1093,7 +1092,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_MULTMDW 1087 #define MACH_TYPE_MBA2440 1088 #define MACH_TYPE_ECSD 1089 -#define MACH_TYPE_ZIRE31 1090 +#define MACH_TYPE_PALMZ31 1090 #define MACH_TYPE_FSG 1091 #define MACH_TYPE_RAZOR101 1092 #define MACH_TYPE_OPERA_TDM 1093 @@ -1215,7 +1214,6 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_EM7210 1212 #define MACH_TYPE_HTCHERMES 1213 #define MACH_TYPE_ETI_C1 1214 -#define MACH_TYPE_MACH_DEP2410 1215 #define MACH_TYPE_AC100 1216 #define MACH_TYPE_SNEETCH 1217 #define MACH_TYPE_STUDENTMATE 1218 @@ -1230,7 +1228,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_VPAC270 1227 #define MACH_TYPE_RD129 1228 #define MACH_TYPE_HTCWIZARD 1229 -#define MACH_TYPE_XSCALE_TREO680 1230 +#define MACH_TYPE_TREO680 1230 #define MACH_TYPE_TECON_TMEZON 1231 #define MACH_TYPE_ZYLONITE 1233 #define MACH_TYPE_GENE1270 1234 @@ -1378,7 +1376,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OLIP8 1378 #define MACH_TYPE_GHI270HG 1379 #define MACH_TYPE_DAVINCI_DM6467_EVM 1380 -#define MACH_TYPE_DAVINCI_DM350_EVM 1381 +#define MACH_TYPE_DAVINCI_DM355_EVM 1381 #define MACH_TYPE_BLACKRIVER 1383 #define MACH_TYPE_SANDGATEWP 1384 #define MACH_TYPE_CDOTBWSG 1385 @@ -1416,10 +1414,10 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CNTY_TITAN 1418 #define MACH_TYPE_APP3XX 1419 #define MACH_TYPE_SIDEOATSGRAMA 1420 -#define MACH_TYPE_XSCALE_PALMT700P 1421 -#define MACH_TYPE_XSCALE_PALMT700W 1422 -#define MACH_TYPE_XSCALE_PALMT750 1423 -#define MACH_TYPE_XSCALE_PALMT755P 1424 +#define MACH_TYPE_TREO700P 1421 +#define MACH_TYPE_TREO700W 1422 +#define MACH_TYPE_TREO750 1423 +#define MACH_TYPE_TREO755P 1424 #define MACH_TYPE_EZREGANUT9200 1425 #define MACH_TYPE_SARGE 1426 #define MACH_TYPE_A696 1427 @@ -1453,12 +1451,12 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_H6044 1458 #define MACH_TYPE_APP 1459 #define MACH_TYPE_TCT_HAMMER 1460 -#define MACH_TYPE_HERMES 1461 +#define MACH_TYPE_HERALD 1461 #define MACH_TYPE_ARTEMIS 1462 #define MACH_TYPE_HTCTITAN 1463 #define MACH_TYPE_QRANIUM 1464 #define MACH_TYPE_ADX_WSC2 1465 -#define MACH_TYPE_ADX_MEDINET 1466 +#define MACH_TYPE_ADX_MEDCOM 1466 #define MACH_TYPE_BBOARD 1467 #define MACH_TYPE_CAMBRIA 1468 #define MACH_TYPE_MT7XXX 1469 @@ -1514,7 +1512,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CORSICA 1519 #define MACH_TYPE_BIGEYE 1520 #define MACH_TYPE_TLL5000 1522 -#define MACH_TYPE_HNI_X270 1523 +#define MACH_TYPE_BEBOT 1523 #define MACH_TYPE_QONG 1524 #define MACH_TYPE_TCOMPACT 1525 #define MACH_TYPE_PUMA5 1526 @@ -1595,7 +1593,1580 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_P300 1602 #define MACH_TYPE_XDACOMET 1603 #define MACH_TYPE_DEXFLEX2 1604 +#define MACH_TYPE_OW 1605 +#define MACH_TYPE_ARMEBS3 1606 +#define MACH_TYPE_U3 1607 +#define MACH_TYPE_SMDK2450 1608 +#define MACH_TYPE_RSI_EWS 1609 +#define MACH_TYPE_TNB 1610 +#define MACH_TYPE_TOEPATH 1611 +#define MACH_TYPE_KB9263 1612 +#define MACH_TYPE_MT7108 1613 +#define MACH_TYPE_SMTR2440 1614 +#define MACH_TYPE_MANAO 1615 +#define MACH_TYPE_CM_X300 1616 +#define MACH_TYPE_GULFSTREAM_KP 1617 +#define MACH_TYPE_LANREADYFN522 1618 +#define MACH_TYPE_ARMA37 1619 +#define MACH_TYPE_MENDEL 1620 +#define MACH_TYPE_PELCO_ILIAD 1621 +#define MACH_TYPE_UNIT2P 1622 +#define MACH_TYPE_INC20OTTER 1623 +#define MACH_TYPE_AT91SAM9G20EK 1624 +#define MACH_TYPE_STORCENTER 1625 +#define MACH_TYPE_SMDK6410 1626 +#define MACH_TYPE_U300 1627 +#define MACH_TYPE_U500 1628 +#define MACH_TYPE_DS9260 1629 +#define MACH_TYPE_RIVERROCK 1630 +#define MACH_TYPE_SCIBATH 1631 +#define MACH_TYPE_AT91SAM7SE512EK 1632 +#define MACH_TYPE_WRT350N_V2 1633 +#define MACH_TYPE_MULTIMEDIA 1634 +#define MACH_TYPE_MARVIN 1635 +#define MACH_TYPE_X500 1636 +#define MACH_TYPE_AWLUG4LCU 1637 +#define MACH_TYPE_PALERMOC 1638 +#define MACH_TYPE_OMAP_LDP 1639 +#define MACH_TYPE_IP500 1640 +#define MACH_TYPE_ASE2 1642 +#define MACH_TYPE_MX35EVB 1643 +#define MACH_TYPE_AML_M8050 1644 +#define MACH_TYPE_MX35_3DS 1645 +#define MACH_TYPE_MARS 1646 +#define MACH_TYPE_NEUROS_OSD2 1647 +#define MACH_TYPE_BADGER 1648 +#define MACH_TYPE_TRIZEPS4WL 1649 +#define MACH_TYPE_TRIZEPS5 1650 +#define MACH_TYPE_MARLIN 1651 +#define MACH_TYPE_TS78XX 1652 +#define MACH_TYPE_HPIPAQ214 1653 +#define MACH_TYPE_AT572D940DCM 1654 +#define MACH_TYPE_NE1BOARD 1655 +#define MACH_TYPE_ZANTE 1656 #define MACH_TYPE_SFFSDR 1657 +#define MACH_TYPE_TW2662 1658 +#define MACH_TYPE_VF10XX 1659 +#define MACH_TYPE_ZORAN43XX 1660 +#define MACH_TYPE_SONIX926 1661 +#define MACH_TYPE_CELESTIALSEMI 1662 +#define MACH_TYPE_CC9M2443JS 1663 +#define MACH_TYPE_TW5334 1664 +#define MACH_TYPE_HTCARTEMIS 1665 +#define MACH_TYPE_NAL_HLITE 1666 +#define MACH_TYPE_HTCVOGUE 1667 +#define MACH_TYPE_SMARTWEB 1668 +#define MACH_TYPE_MV86XX 1669 +#define MACH_TYPE_MV87XX 1670 +#define MACH_TYPE_SONGYOUNGHO 1671 +#define MACH_TYPE_YOUNGHOTEMA 1672 +#define MACH_TYPE_PCM037 1673 +#define MACH_TYPE_MMVP 1674 +#define MACH_TYPE_MMAP 1675 +#define MACH_TYPE_PTID2410 1676 +#define MACH_TYPE_JAMES_926 1677 +#define MACH_TYPE_FM6000 1678 +#define MACH_TYPE_DB88F6281_BP 1680 +#define MACH_TYPE_RD88F6192_NAS 1681 +#define MACH_TYPE_RD88F6281 1682 +#define MACH_TYPE_DB78X00_BP 1683 +#define MACH_TYPE_SMDK2416 1685 +#define MACH_TYPE_OCE_SPIDER_SI 1686 +#define MACH_TYPE_OCE_SPIDER_SK 1687 +#define MACH_TYPE_ROVERN6 1688 +#define MACH_TYPE_PELCO_EVOLUTION 1689 +#define MACH_TYPE_WBD111 1690 +#define MACH_TYPE_ELARACPE 1691 +#define MACH_TYPE_MABV3 1692 +#define MACH_TYPE_MV2120 1693 +#define MACH_TYPE_CSB737 1695 +#define MACH_TYPE_MX51_3DS 1696 +#define MACH_TYPE_G900 1697 +#define MACH_TYPE_APF27 1698 +#define MACH_TYPE_GGUS2000 1699 +#define MACH_TYPE_OMAP_2430_MIMIC 1700 +#define MACH_TYPE_IMX27LITE 1701 +#define MACH_TYPE_ALMEX 1702 +#define MACH_TYPE_CONTROL 1703 +#define MACH_TYPE_MBA2410 1704 +#define MACH_TYPE_VOLCANO 1705 +#define MACH_TYPE_ZENITH 1706 +#define MACH_TYPE_MUCHIP 1707 +#define MACH_TYPE_MAGELLAN 1708 +#define MACH_TYPE_USB_A9260 1709 +#define MACH_TYPE_USB_A9263 1710 +#define MACH_TYPE_QIL_A9260 1711 +#define MACH_TYPE_CME9210 1712 +#define MACH_TYPE_HCZH4 1713 +#define MACH_TYPE_SPEARBASIC 1714 +#define MACH_TYPE_DEP2440 1715 +#define MACH_TYPE_HDL_GXR 1716 +#define MACH_TYPE_HDL_GT 1717 +#define MACH_TYPE_HDL_4G 1718 +#define MACH_TYPE_S3C6000 1719 +#define MACH_TYPE_MMSP2_MDK 1720 +#define MACH_TYPE_MPX220 1721 +#define MACH_TYPE_KZM_ARM11_01 1722 +#define MACH_TYPE_HTC_POLARIS 1723 +#define MACH_TYPE_HTC_KAISER 1724 +#define MACH_TYPE_LG_KS20 1725 +#define MACH_TYPE_HHGPS 1726 +#define MACH_TYPE_NOKIA_N810_WIMAX 1727 +#define MACH_TYPE_INSIGHT 1728 +#define MACH_TYPE_SAPPHIRE 1729 +#define MACH_TYPE_CSB637XO 1730 +#define MACH_TYPE_EVISIONG 1731 +#define MACH_TYPE_STMP37XX 1732 +#define MACH_TYPE_STMP378X 1733 +#define MACH_TYPE_TNT 1734 +#define MACH_TYPE_TBXT 1735 +#define MACH_TYPE_PLAYMATE 1736 +#define MACH_TYPE_PNS10 1737 +#define MACH_TYPE_EZNAVI 1738 +#define MACH_TYPE_PS4000 1739 +#define MACH_TYPE_EZX_A780 1740 +#define MACH_TYPE_EZX_E680 1741 +#define MACH_TYPE_EZX_A1200 1742 +#define MACH_TYPE_EZX_E6 1743 +#define MACH_TYPE_EZX_E2 1744 +#define MACH_TYPE_EZX_A910 1745 +#define MACH_TYPE_CWMX31 1746 +#define MACH_TYPE_SL2312 1747 +#define MACH_TYPE_BLENNY 1748 +#define MACH_TYPE_DS107 1749 +#define MACH_TYPE_DSX07 1750 +#define MACH_TYPE_PICOCOM1 1751 +#define MACH_TYPE_LYNX_WOLVERINE 1752 +#define MACH_TYPE_UBISYS_P9_SC19 1753 +#define MACH_TYPE_KRATOS_LOW 1754 +#define MACH_TYPE_M700 1755 +#define MACH_TYPE_EDMINI_V2 1756 +#define MACH_TYPE_ZIPIT2 1757 +#define MACH_TYPE_HSLFEMTOCELL 1758 +#define MACH_TYPE_DAINTREE_AT91 1759 +#define MACH_TYPE_SG560USB 1760 +#define MACH_TYPE_OMAP3_PANDORA 1761 +#define MACH_TYPE_USR8200 1762 +#define MACH_TYPE_S1S65K 1763 +#define MACH_TYPE_S2S65A 1764 +#define MACH_TYPE_ICORE 1765 +#define MACH_TYPE_MSS2 1766 +#define MACH_TYPE_BELMONT 1767 +#define MACH_TYPE_ASUSP525 1768 +#define MACH_TYPE_LB88RC8480 1769 +#define MACH_TYPE_HIPXA 1770 +#define MACH_TYPE_MX25_3DS 1771 +#define MACH_TYPE_M800 1772 +#define MACH_TYPE_OMAP3530_LV_SOM 1773 +#define MACH_TYPE_PRIMA_EVB 1774 +#define MACH_TYPE_MX31BT1 1775 +#define MACH_TYPE_ATLAS4_EVB 1776 +#define MACH_TYPE_MX31CICADA 1777 +#define MACH_TYPE_MI424WR 1778 +#define MACH_TYPE_AXS_ULTRAX 1779 +#define MACH_TYPE_AT572D940DEB 1780 +#define MACH_TYPE_DAVINCI_DA830_EVM 1781 +#define MACH_TYPE_EP9302 1782 +#define MACH_TYPE_AT572D940HFEB 1783 +#define MACH_TYPE_CYBOOK3 1784 +#define MACH_TYPE_WDG002 1785 +#define MACH_TYPE_SG560ADSL 1786 +#define MACH_TYPE_NEXTIO_N2800_ICA 1787 +#define MACH_TYPE_DOVE_DB 1788 +#define MACH_TYPE_MARVELL_NEWDB 1789 +#define MACH_TYPE_VANDIHUD 1790 +#define MACH_TYPE_MAGX_E8 1791 +#define MACH_TYPE_MAGX_Z6 1792 +#define MACH_TYPE_MAGX_V8 1793 +#define MACH_TYPE_MAGX_U9 1794 +#define MACH_TYPE_TOUGHCF08 1795 +#define MACH_TYPE_ZW4400 1796 +#define MACH_TYPE_MARAT91 1797 +#define MACH_TYPE_OVERO 1798 +#define MACH_TYPE_AT2440EVB 1799 +#define MACH_TYPE_NEOCORE926 1800 +#define MACH_TYPE_WNR854T 1801 +#define MACH_TYPE_IMX27 1802 +#define MACH_TYPE_MOOSE_DB 1803 +#define MACH_TYPE_FAB4 1804 +#define MACH_TYPE_HTCDIAMOND 1805 +#define MACH_TYPE_FIONA 1806 +#define MACH_TYPE_MXC30030_X 1807 +#define MACH_TYPE_BMP1000 1808 +#define MACH_TYPE_LOGI9200 1809 +#define MACH_TYPE_TQMA31 1810 +#define MACH_TYPE_CCW9P9215JS 1811 +#define MACH_TYPE_RD88F5181L_GE 1812 +#define MACH_TYPE_SIFMAIN 1813 +#define MACH_TYPE_SAM9_L9261 1814 +#define MACH_TYPE_CC9M2443 1815 +#define MACH_TYPE_XARIA300 1816 +#define MACH_TYPE_IT9200 1817 +#define MACH_TYPE_RD88F5181L_FXO 1818 +#define MACH_TYPE_KRISS_SENSOR 1819 +#define MACH_TYPE_PILZ_PMI5 1820 +#define MACH_TYPE_JADE 1821 +#define MACH_TYPE_KS8695_SOFTPLC 1822 +#define MACH_TYPE_GPRISC3 1823 +#define MACH_TYPE_STAMP9G20 1824 +#define MACH_TYPE_SMDK6430 1825 +#define MACH_TYPE_SMDKC100 1826 +#define MACH_TYPE_TAVOREVB 1827 +#define MACH_TYPE_SAAR 1828 +#define MACH_TYPE_DEISTER_EYECAM 1829 +#define MACH_TYPE_AT91SAM9M10G45EK 1830 +#define MACH_TYPE_LINKSTATION_PRODUO 1831 +#define MACH_TYPE_HIT_B0 1832 +#define MACH_TYPE_ADX_RMU 1833 +#define MACH_TYPE_XG_CPE_MAIN 1834 +#define MACH_TYPE_EDB9407A 1835 +#define MACH_TYPE_DTB9608 1836 +#define MACH_TYPE_EM104V1 1837 +#define MACH_TYPE_DEMO 1838 +#define MACH_TYPE_LOGI9260 1839 +#define MACH_TYPE_MX31_EXM32 1840 +#define MACH_TYPE_USB_A9G20 1841 +#define MACH_TYPE_PICPROJE2008 1842 +#define MACH_TYPE_CS_E9315 1843 +#define MACH_TYPE_QIL_A9G20 1844 +#define MACH_TYPE_SHA_PON020 1845 +#define MACH_TYPE_NAD 1846 +#define MACH_TYPE_SBC35_A9260 1847 +#define MACH_TYPE_SBC35_A9G20 1848 +#define MACH_TYPE_DAVINCI_BEGINNING 1849 +#define MACH_TYPE_UWC 1850 +#define MACH_TYPE_MXLADS 1851 +#define MACH_TYPE_HTCNIKE 1852 +#define MACH_TYPE_DEISTER_PXA270 1853 +#define MACH_TYPE_CME9210JS 1854 +#define MACH_TYPE_CC9P9360 1855 +#define MACH_TYPE_MOCHA 1856 +#define MACH_TYPE_WAPD170AG 1857 +#define MACH_TYPE_LINKSTATION_MINI 1858 +#define MACH_TYPE_AFEB9260 1859 +#define MACH_TYPE_W90X900 1860 +#define MACH_TYPE_W90X700 1861 +#define MACH_TYPE_KT300IP 1862 +#define MACH_TYPE_KT300IP_G20 1863 +#define MACH_TYPE_SRCM 1864 +#define MACH_TYPE_WLNX_9260 1865 +#define MACH_TYPE_OPENMOKO_GTA03 1866 +#define MACH_TYPE_OSPREY2 1867 +#define MACH_TYPE_KBIO9260 1868 +#define MACH_TYPE_GINZA 1869 +#define MACH_TYPE_A636N 1870 +#define MACH_TYPE_IMX27IPCAM 1871 +#define MACH_TYPE_NEMOC 1872 +#define MACH_TYPE_GENEVA 1873 +#define MACH_TYPE_HTCPHAROS 1874 +#define MACH_TYPE_NEONC 1875 +#define MACH_TYPE_NAS7100 1876 +#define MACH_TYPE_TEUPHONE 1877 +#define MACH_TYPE_ANNAX_ETH2 1878 +#define MACH_TYPE_CSB733 1879 +#define MACH_TYPE_BK3 1880 +#define MACH_TYPE_OMAP_EM32 1881 +#define MACH_TYPE_ET9261CP 1882 +#define MACH_TYPE_JASPERC 1883 +#define MACH_TYPE_ISSI_ARM9 1884 +#define MACH_TYPE_UED 1885 +#define MACH_TYPE_ESIBLADE 1886 +#define MACH_TYPE_EYE02 1887 +#define MACH_TYPE_IMX27KBD 1888 +#define MACH_TYPE_SST61VC010_FPGA 1889 +#define MACH_TYPE_KIXVP435 1890 +#define MACH_TYPE_KIXNP435 1891 +#define MACH_TYPE_AFRICA 1892 +#define MACH_TYPE_NH233 1893 +#define MACH_TYPE_RD88F6183AP_GE 1894 +#define MACH_TYPE_BCM4760 1895 +#define MACH_TYPE_EDDY_V2 1896 +#define MACH_TYPE_REALVIEW_PBA8 1897 +#define MACH_TYPE_HID_A7 1898 +#define MACH_TYPE_HERO 1899 +#define MACH_TYPE_OMAP_POSEIDON 1900 +#define MACH_TYPE_REALVIEW_PBX 1901 +#define MACH_TYPE_MICRO9S 1902 +#define MACH_TYPE_MAKO 1903 +#define MACH_TYPE_XDAFLAME 1904 +#define MACH_TYPE_PHIDGET_SBC2 1905 +#define MACH_TYPE_LIMESTONE 1906 +#define MACH_TYPE_IPROBE_C32 1907 +#define MACH_TYPE_RUT100 1908 +#define MACH_TYPE_ASUSP535 1909 +#define MACH_TYPE_HTCRAPHAEL 1910 +#define MACH_TYPE_SYGDG1 1911 +#define MACH_TYPE_SYGDG2 1912 +#define MACH_TYPE_SEOUL 1913 +#define MACH_TYPE_SALERNO 1914 +#define MACH_TYPE_UCN_S3C64XX 1915 +#define MACH_TYPE_MSM7201A 1916 +#define MACH_TYPE_LPR1 1917 +#define MACH_TYPE_ARMADILLO500FX 1918 +#define MACH_TYPE_G3EVM 1919 +#define MACH_TYPE_Z3_DM355 1920 +#define MACH_TYPE_W90P910EVB 1921 +#define MACH_TYPE_W90P920EVB 1922 +#define MACH_TYPE_W90P950EVB 1923 +#define MACH_TYPE_W90N960EVB 1924 +#define MACH_TYPE_CAMHD 1925 +#define MACH_TYPE_MVC100 1926 +#define MACH_TYPE_ELECTRUM_200 1927 +#define MACH_TYPE_HTCJADE 1928 +#define MACH_TYPE_MEMPHIS 1929 +#define MACH_TYPE_IMX27SBC 1930 +#define MACH_TYPE_LEXTAR 1931 +#define MACH_TYPE_MV88F6281GTW_GE 1932 +#define MACH_TYPE_NCP 1933 +#define MACH_TYPE_Z32AN 1934 +#define MACH_TYPE_TMQ_CAPD 1935 +#define MACH_TYPE_OMAP3_WL 1936 +#define MACH_TYPE_CHUMBY 1937 +#define MACH_TYPE_ATSARM9 1938 +#define MACH_TYPE_DAVINCI_DM365_EVM 1939 +#define MACH_TYPE_BAHAMAS 1940 +#define MACH_TYPE_DAS 1941 +#define MACH_TYPE_MINIDAS 1942 +#define MACH_TYPE_VK1000 1943 +#define MACH_TYPE_CENTRO 1944 +#define MACH_TYPE_CTERA_2BAY 1945 +#define MACH_TYPE_EDGECONNECT 1946 +#define MACH_TYPE_ND27000 1947 +#define MACH_TYPE_GEMALTO_COBRA 1948 +#define MACH_TYPE_INGELABS_COMET 1949 +#define MACH_TYPE_POLLUX_WIZ 1950 +#define MACH_TYPE_BLACKSTONE 1951 +#define MACH_TYPE_TOPAZ 1952 +#define MACH_TYPE_AIXLE 1953 +#define MACH_TYPE_MW998 1954 +#define MACH_TYPE_NOKIA_RX51 1955 +#define MACH_TYPE_VSC5605EV 1956 +#define MACH_TYPE_NT98700DK 1957 +#define MACH_TYPE_ICONTACT 1958 +#define MACH_TYPE_SWARCO_FRCPU 1959 +#define MACH_TYPE_SWARCO_SCPU 1960 +#define MACH_TYPE_BBOX_P16 1961 +#define MACH_TYPE_BSTD 1962 +#define MACH_TYPE_SBC2440II 1963 +#define MACH_TYPE_PCM034 1964 +#define MACH_TYPE_NESO 1965 +#define MACH_TYPE_WLNX_9G20 1966 +#define MACH_TYPE_OMAP_ZOOM2 1967 +#define MACH_TYPE_TOTEMNOVA 1968 +#define MACH_TYPE_C5000 1969 +#define MACH_TYPE_UNIPO_AT91SAM9263 1970 +#define MACH_TYPE_ETHERNUT5 1971 +#define MACH_TYPE_ARM11 1972 +#define MACH_TYPE_CPUAT9260 1973 +#define MACH_TYPE_CPUPXA255 1974 +#define MACH_TYPE_CPUIMX27 1975 +#define MACH_TYPE_CHEFLUX 1976 +#define MACH_TYPE_EB_CPUX9K2 1977 +#define MACH_TYPE_OPCOTEC 1978 +#define MACH_TYPE_YT 1979 +#define MACH_TYPE_MOTOQ 1980 +#define MACH_TYPE_BSB1 1981 +#define MACH_TYPE_ACS5K 1982 +#define MACH_TYPE_MILAN 1983 +#define MACH_TYPE_QUARTZV2 1984 +#define MACH_TYPE_RSVP 1985 +#define MACH_TYPE_RMP200 1986 +#define MACH_TYPE_SNAPPER_9260 1987 +#define MACH_TYPE_DSM320 1988 +#define MACH_TYPE_ADSGCM 1989 +#define MACH_TYPE_ASE2_400 1990 +#define MACH_TYPE_PIZZA 1991 +#define MACH_TYPE_SPOT_NGPL 1992 +#define MACH_TYPE_ARMATA 1993 +#define MACH_TYPE_EXEDA 1994 +#define MACH_TYPE_MX31SF005 1995 +#define MACH_TYPE_F5D8231_4_V2 1996 +#define MACH_TYPE_Q2440 1997 +#define MACH_TYPE_QQ2440 1998 +#define MACH_TYPE_MINI2440 1999 +#define MACH_TYPE_COLIBRI300 2000 +#define MACH_TYPE_JADES 2001 +#define MACH_TYPE_SPARK 2002 +#define MACH_TYPE_BENZINA 2003 +#define MACH_TYPE_BLAZE 2004 +#define MACH_TYPE_LINKSTATION_LS_HGL 2005 +#define MACH_TYPE_HTCKOVSKY 2006 +#define MACH_TYPE_SONY_PRS505 2007 +#define MACH_TYPE_HANLIN_V3 2008 +#define MACH_TYPE_SAPPHIRA 2009 +#define MACH_TYPE_DACK_SDA_01 2010 +#define MACH_TYPE_ARMBOX 2011 +#define MACH_TYPE_HARRIS_RVP 2012 +#define MACH_TYPE_RIBALDO 2013 +#define MACH_TYPE_AGORA 2014 +#define MACH_TYPE_OMAP3_MINI 2015 +#define MACH_TYPE_A9SAM6432_B 2016 +#define MACH_TYPE_USG2410 2017 +#define MACH_TYPE_PC72052_I10_REVB 2018 +#define MACH_TYPE_MX35_EXM32 2019 +#define MACH_TYPE_TOPAS910 2020 +#define MACH_TYPE_HYENA 2021 +#define MACH_TYPE_POSPAX 2022 +#define MACH_TYPE_HDL_GX 2023 +#define MACH_TYPE_CTERA_4BAY 2024 +#define MACH_TYPE_CTERA_PLUG_C 2025 +#define MACH_TYPE_CRWEA_PLUG_I 2026 +#define MACH_TYPE_EGAUGE2 2027 +#define MACH_TYPE_DIDJ 2028 +#define MACH_TYPE_MEISTER 2029 +#define MACH_TYPE_HTCBLACKSTONE 2030 +#define MACH_TYPE_CPUAT9G20 2031 +#define MACH_TYPE_SMDK6440 2032 +#define MACH_TYPE_OMAP_35XX_MVP 2033 +#define MACH_TYPE_CTERA_PLUG_I 2034 +#define MACH_TYPE_PVG610 2035 +#define MACH_TYPE_HPRW6815 2036 +#define MACH_TYPE_OMAP3_OSWALD 2037 +#define MACH_TYPE_NAS4220B 2038 +#define MACH_TYPE_HTCRAPHAEL_CDMA 2039 +#define MACH_TYPE_HTCDIAMOND_CDMA 2040 +#define MACH_TYPE_SCALER 2041 +#define MACH_TYPE_ZYLONITE2 2042 +#define MACH_TYPE_ASPENITE 2043 +#define MACH_TYPE_TETON 2044 +#define MACH_TYPE_TTC_DKB 2045 +#define MACH_TYPE_BISHOP2 2046 +#define MACH_TYPE_IPPV5 2047 +#define MACH_TYPE_FARM926 2048 +#define MACH_TYPE_MMCCPU 2049 +#define MACH_TYPE_SGMSFL 2050 +#define MACH_TYPE_TT8000 2051 +#define MACH_TYPE_ZRN4300LP 2052 +#define MACH_TYPE_MPTC 2053 +#define MACH_TYPE_H6051 2054 +#define MACH_TYPE_PVG610_101 2055 +#define MACH_TYPE_STAMP9261_PC_EVB 2056 +#define MACH_TYPE_PELCO_ODYSSEUS 2057 +#define MACH_TYPE_TNY_A9260 2058 +#define MACH_TYPE_TNY_A9G20 2059 +#define MACH_TYPE_AESOP_MP2530F 2060 +#define MACH_TYPE_DX900 2061 +#define MACH_TYPE_CPODC2 2062 +#define MACH_TYPE_TILT_8925 2063 +#define MACH_TYPE_DAVINCI_DM357_EVM 2064 +#define MACH_TYPE_SWORDFISH 2065 +#define MACH_TYPE_CORVUS 2066 +#define MACH_TYPE_TAURUS 2067 +#define MACH_TYPE_AXM 2068 +#define MACH_TYPE_AXC 2069 +#define MACH_TYPE_BABY 2070 +#define MACH_TYPE_MP200 2071 +#define MACH_TYPE_PCM043 2072 +#define MACH_TYPE_HANLIN_V3C 2073 +#define MACH_TYPE_KBK9G20 2074 +#define MACH_TYPE_ADSTURBOG5 2075 +#define MACH_TYPE_AVENGER_LITE1 2076 +#define MACH_TYPE_SUC 2077 +#define MACH_TYPE_AT91SAM7S256 2078 +#define MACH_TYPE_MENDOZA 2079 +#define MACH_TYPE_KIRA 2080 +#define MACH_TYPE_MX1HBM 2081 +#define MACH_TYPE_QUATRO43XX 2082 +#define MACH_TYPE_QUATRO4230 2083 +#define MACH_TYPE_NSB400 2084 +#define MACH_TYPE_DRP255 2085 +#define MACH_TYPE_THOTH 2086 +#define MACH_TYPE_FIRESTONE 2087 +#define MACH_TYPE_ASUSP750 2088 +#define MACH_TYPE_CTERA_DL 2089 +#define MACH_TYPE_SOCR 2090 +#define MACH_TYPE_HTCOXYGEN 2091 +#define MACH_TYPE_HEROC 2092 +#define MACH_TYPE_ZENO6800 2093 +#define MACH_TYPE_SC2MCS 2094 +#define MACH_TYPE_GENE100 2095 +#define MACH_TYPE_AS353X 2096 +#define MACH_TYPE_SHEEVAPLUG 2097 +#define MACH_TYPE_AT91SAM9G20 2098 +#define MACH_TYPE_MV88F6192GTW_FE 2099 +#define MACH_TYPE_CC9200 2100 +#define MACH_TYPE_SM9200 2101 +#define MACH_TYPE_TP9200 2102 +#define MACH_TYPE_SNAPPERDV 2103 +#define MACH_TYPE_AVENGERS_LITE 2104 +#define MACH_TYPE_AVENGERS_LITE1 2105 +#define MACH_TYPE_OMAP3AXON 2106 +#define MACH_TYPE_MA8XX 2107 +#define MACH_TYPE_MP201EK 2108 +#define MACH_TYPE_DAVINCI_TUX 2109 +#define MACH_TYPE_MPA1600 2110 +#define MACH_TYPE_PELCO_TROY 2111 +#define MACH_TYPE_NSB667 2112 +#define MACH_TYPE_ROVERS5_4MPIX 2113 +#define MACH_TYPE_TWOCOM 2114 +#define MACH_TYPE_UBISYS_P9_RCU3R2 2115 +#define MACH_TYPE_HERO_ESPRESSO 2116 +#define MACH_TYPE_AFEUSB 2117 +#define MACH_TYPE_T830 2118 +#define MACH_TYPE_SPD8020_CC 2119 +#define MACH_TYPE_OM_3D7K 2120 +#define MACH_TYPE_PICOCOM2 2121 +#define MACH_TYPE_UWG4MX27 2122 +#define MACH_TYPE_UWG4MX31 2123 +#define MACH_TYPE_CHERRY 2124 +#define MACH_TYPE_MX51_BABBAGE 2125 +#define MACH_TYPE_S3C2440TURKIYE 2126 +#define MACH_TYPE_TX37 2127 +#define MACH_TYPE_SBC2800_9G20 2128 +#define MACH_TYPE_BENZGLB 2129 +#define MACH_TYPE_BENZTD 2130 +#define MACH_TYPE_CARTESIO_PLUS 2131 +#define MACH_TYPE_SOLRAD_G20 2132 +#define MACH_TYPE_MX27WALLACE 2133 +#define MACH_TYPE_FMZWEBMODUL 2134 +#define MACH_TYPE_RD78X00_MASA 2135 +#define MACH_TYPE_SMALLOGGER 2136 +#define MACH_TYPE_CCW9P9215 2137 +#define MACH_TYPE_DM355_LEOPARD 2138 +#define MACH_TYPE_TS219 2139 +#define MACH_TYPE_TNY_A9263 2140 +#define MACH_TYPE_APOLLO 2141 +#define MACH_TYPE_AT91CAP9STK 2142 +#define MACH_TYPE_SPC300 2143 +#define MACH_TYPE_EKO 2144 +#define MACH_TYPE_CCW9M2443 2145 +#define MACH_TYPE_CCW9M2443JS 2146 +#define MACH_TYPE_M2M_ROUTER_DEVICE 2147 +#define MACH_TYPE_STAR9104NAS 2148 +#define MACH_TYPE_PCA100 2149 +#define MACH_TYPE_Z3_DM365_MOD_01 2150 +#define MACH_TYPE_HIPOX 2151 +#define MACH_TYPE_OMAP3_PITEDS 2152 +#define MACH_TYPE_BM150R 2153 +#define MACH_TYPE_TBONE 2154 +#define MACH_TYPE_MERLIN 2155 +#define MACH_TYPE_FALCON 2156 +#define MACH_TYPE_DAVINCI_DA850_EVM 2157 +#define MACH_TYPE_S5P6440 2158 +#define MACH_TYPE_AT91SAM9G10EK 2159 +#define MACH_TYPE_OMAP_4430SDP 2160 +#define MACH_TYPE_LPC313X 2161 +#define MACH_TYPE_MAGX_ZN5 2162 +#define MACH_TYPE_MAGX_EM30 2163 +#define MACH_TYPE_MAGX_VE66 2164 +#define MACH_TYPE_MEESC 2165 +#define MACH_TYPE_OTC570 2166 +#define MACH_TYPE_BCU2412 2167 +#define MACH_TYPE_BEACON 2168 +#define MACH_TYPE_ACTIA_TGW 2169 +#define MACH_TYPE_E4430 2170 +#define MACH_TYPE_QL300 2171 +#define MACH_TYPE_BTMAVB101 2172 +#define MACH_TYPE_BTMAWB101 2173 +#define MACH_TYPE_SQ201 2174 +#define MACH_TYPE_QUATRO45XX 2175 +#define MACH_TYPE_OPENPAD 2176 +#define MACH_TYPE_TX25 2177 +#define MACH_TYPE_OMAP3_TORPEDO 2178 +#define MACH_TYPE_HTCRAPHAEL_K 2179 +#define MACH_TYPE_LAL43 2181 +#define MACH_TYPE_HTCRAPHAEL_CDMA500 2182 +#define MACH_TYPE_ANW6410 2183 +#define MACH_TYPE_HTCPROPHET 2185 +#define MACH_TYPE_CFA_10022 2186 +#define MACH_TYPE_IMX27_VISSTRIM_M10 2187 +#define MACH_TYPE_PX2IMX27 2188 +#define MACH_TYPE_STM3210E_EVAL 2189 +#define MACH_TYPE_DVS10 2190 +#define MACH_TYPE_PORTUXG20 2191 +#define MACH_TYPE_ARM_SPV 2192 +#define MACH_TYPE_SMDKC110 2193 +#define MACH_TYPE_CABESPRESSO 2194 +#define MACH_TYPE_HMC800 2195 +#define MACH_TYPE_SHOLES 2196 +#define MACH_TYPE_BTMXC31 2197 +#define MACH_TYPE_DT501 2198 +#define MACH_TYPE_KTX 2199 +#define MACH_TYPE_OMAP3517EVM 2200 +#define MACH_TYPE_NETSPACE_V2 2201 +#define MACH_TYPE_NETSPACE_MAX_V2 2202 +#define MACH_TYPE_D2NET_V2 2203 +#define MACH_TYPE_NET2BIG_V2 2204 +#define MACH_TYPE_NET4BIG_V2 2205 +#define MACH_TYPE_NET5BIG_V2 2206 +#define MACH_TYPE_ENDB2443 2207 +#define MACH_TYPE_INETSPACE_V2 2208 +#define MACH_TYPE_TROS 2209 +#define MACH_TYPE_PELCO_HOMER 2210 +#define MACH_TYPE_OFSP8 2211 +#define MACH_TYPE_AT91SAM9G45EKES 2212 +#define MACH_TYPE_GUF_CUPID 2213 +#define MACH_TYPE_EAB1R 2214 +#define MACH_TYPE_DESIREC 2215 +#define MACH_TYPE_CORDOBA 2216 +#define MACH_TYPE_IRVINE 2217 +#define MACH_TYPE_SFF772 2218 +#define MACH_TYPE_PELCO_MILANO 2219 +#define MACH_TYPE_PC7302 2220 +#define MACH_TYPE_BIP6000 2221 +#define MACH_TYPE_SILVERMOON 2222 +#define MACH_TYPE_VC0830 2223 +#define MACH_TYPE_DT430 2224 +#define MACH_TYPE_JI42PF 2225 +#define MACH_TYPE_GNET_KSM 2226 +#define MACH_TYPE_GNET_SGM 2227 +#define MACH_TYPE_GNET_SGR 2228 +#define MACH_TYPE_OMAP3_ICETEKEVM 2229 +#define MACH_TYPE_PNP 2230 +#define MACH_TYPE_CTERA_2BAY_K 2231 +#define MACH_TYPE_CTERA_2BAY_U 2232 +#define MACH_TYPE_SAS_C 2233 +#define MACH_TYPE_VMA2315 2234 +#define MACH_TYPE_VCS 2235 +#define MACH_TYPE_SPEAR600 2236 +#define MACH_TYPE_SPEAR300 2237 +#define MACH_TYPE_SPEAR1300 2238 +#define MACH_TYPE_LILLY1131 2239 +#define MACH_TYPE_ARVOO_AX301 2240 +#define MACH_TYPE_MAPPHONE 2241 +#define MACH_TYPE_LEGEND 2242 +#define MACH_TYPE_SALSA 2243 +#define MACH_TYPE_LOUNGE 2244 +#define MACH_TYPE_VISION 2245 +#define MACH_TYPE_VMB20 2246 +#define MACH_TYPE_HY2410 2247 +#define MACH_TYPE_HY9315 2248 +#define MACH_TYPE_BULLWINKLE 2249 +#define MACH_TYPE_ARM_ULTIMATOR2 2250 +#define MACH_TYPE_VS_V210 2252 +#define MACH_TYPE_VS_V212 2253 +#define MACH_TYPE_HMT 2254 +#define MACH_TYPE_SUEN3 2255 +#define MACH_TYPE_VESPER 2256 +#define MACH_TYPE_STR9 2257 +#define MACH_TYPE_OMAP3_WL_FF 2258 +#define MACH_TYPE_SIMCOM 2259 +#define MACH_TYPE_MCWEBIO 2260 +#define MACH_TYPE_OMAP3_PHRAZER 2261 +#define MACH_TYPE_DARWIN 2262 +#define MACH_TYPE_ORATISCOMU 2263 +#define MACH_TYPE_RTSBC20 2264 +#define MACH_TYPE_I780 2265 +#define MACH_TYPE_GEMINI324 2266 +#define MACH_TYPE_ORATISLAN 2267 +#define MACH_TYPE_ORATISALOG 2268 +#define MACH_TYPE_ORATISMADI 2269 +#define MACH_TYPE_ORATISOT16 2270 +#define MACH_TYPE_ORATISDESK 2271 +#define MACH_TYPE_VEXPRESS 2272 +#define MACH_TYPE_SINTEXO 2273 +#define MACH_TYPE_CM3389 2274 +#define MACH_TYPE_OMAP3_CIO 2275 +#define MACH_TYPE_SGH_I900 2276 +#define MACH_TYPE_BST100 2277 +#define MACH_TYPE_PASSION 2278 +#define MACH_TYPE_INDESIGN_AT91SAM 2279 +#define MACH_TYPE_C4_BADGER 2280 +#define MACH_TYPE_C4_VIPER 2281 +#define MACH_TYPE_D2NET 2282 +#define MACH_TYPE_BIGDISK 2283 +#define MACH_TYPE_NOTALVISION 2284 +#define MACH_TYPE_OMAP3_KBOC 2285 +#define MACH_TYPE_CYCLONE 2286 +#define MACH_TYPE_NINJA 2287 +#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288 +#define MACH_TYPE_BCMRING 2289 +#define MACH_TYPE_RESOL_DL2 2290 +#define MACH_TYPE_IFOSW 2291 +#define MACH_TYPE_HTCRHODIUM 2292 +#define MACH_TYPE_HTCTOPAZ 2293 +#define MACH_TYPE_MATRIX504 2294 +#define MACH_TYPE_MRFSA 2295 +#define MACH_TYPE_SC_P270 2296 +#define MACH_TYPE_ATLAS5_EVB 2297 +#define MACH_TYPE_PELCO_LOBOX 2298 +#define MACH_TYPE_DILAX_PCU200 2299 +#define MACH_TYPE_LEONARDO 2300 +#define MACH_TYPE_ZORAN_APPROACH7 2301 +#define MACH_TYPE_DP6XX 2302 +#define MACH_TYPE_BCM2153_VESPER 2303 +#define MACH_TYPE_MAHIMAHI 2304 +#define MACH_TYPE_CLICKC 2305 +#define MACH_TYPE_ZB_GATEWAY 2306 +#define MACH_TYPE_TAZCARD 2307 +#define MACH_TYPE_TAZDEV 2308 +#define MACH_TYPE_ANNAX_CB_ARM 2309 +#define MACH_TYPE_ANNAX_DM3 2310 +#define MACH_TYPE_CEREBRIC 2311 +#define MACH_TYPE_ORCA 2312 +#define MACH_TYPE_PC9260 2313 +#define MACH_TYPE_EMS285A 2314 +#define MACH_TYPE_GEC2410 2315 +#define MACH_TYPE_GEC2440 2316 +#define MACH_TYPE_ARCH_MW903 2317 +#define MACH_TYPE_MW2440 2318 +#define MACH_TYPE_ECAC2378 2319 +#define MACH_TYPE_TAZKIOSK 2320 +#define MACH_TYPE_WHITERABBIT_MCH 2321 +#define MACH_TYPE_SBOX9263 2322 +#define MACH_TYPE_OREO 2323 +#define MACH_TYPE_SMDK6442 2324 +#define MACH_TYPE_OPENRD_BASE 2325 +#define MACH_TYPE_INCREDIBLE 2326 +#define MACH_TYPE_INCREDIBLEC 2327 +#define MACH_TYPE_HEROCT 2328 +#define MACH_TYPE_MMNET1000 2329 +#define MACH_TYPE_DEVKIT8000 2330 +#define MACH_TYPE_DEVKIT9000 2331 +#define MACH_TYPE_MX31TXTR 2332 +#define MACH_TYPE_U380 2333 +#define MACH_TYPE_HUALU_BOARD 2334 +#define MACH_TYPE_NPCMX50 2335 +#define MACH_TYPE_MX51_EFIKAMX 2336 +#define MACH_TYPE_MX51_LANGE52 2337 +#define MACH_TYPE_RIOM 2338 +#define MACH_TYPE_COMCAS 2339 +#define MACH_TYPE_WSI_MX27 2340 +#define MACH_TYPE_CM_T35 2341 +#define MACH_TYPE_NET2BIG 2342 +#define MACH_TYPE_MOTOROLA_A1600 2343 +#define MACH_TYPE_IGEP0020 2344 +#define MACH_TYPE_IGEP0010 2345 +#define MACH_TYPE_MV6281GTWGE2 2346 +#define MACH_TYPE_SCAT100 2347 +#define MACH_TYPE_SANMINA 2348 +#define MACH_TYPE_MOMENTO 2349 +#define MACH_TYPE_NUC9XX 2350 +#define MACH_TYPE_NUC910EVB 2351 +#define MACH_TYPE_NUC920EVB 2352 +#define MACH_TYPE_NUC950EVB 2353 +#define MACH_TYPE_NUC945EVB 2354 +#define MACH_TYPE_NUC960EVB 2355 +#define MACH_TYPE_NUC932EVB 2356 +#define MACH_TYPE_NUC900 2357 +#define MACH_TYPE_SD1SOC 2358 +#define MACH_TYPE_LN2440BC 2359 +#define MACH_TYPE_RSBC 2360 +#define MACH_TYPE_OPENRD_CLIENT 2361 +#define MACH_TYPE_HPIPAQ11X 2362 +#define MACH_TYPE_WAYLAND 2363 +#define MACH_TYPE_ACNBSX102 2364 +#define MACH_TYPE_HWAT91 2365 +#define MACH_TYPE_AT91SAM9263CS 2366 +#define MACH_TYPE_CSB732 2367 +#define MACH_TYPE_U8500 2368 +#define MACH_TYPE_HUQIU 2369 +#define MACH_TYPE_MX51_EFIKASB 2370 +#define MACH_TYPE_PMT1G 2371 +#define MACH_TYPE_HTCELF 2372 +#define MACH_TYPE_ARMADILLO420 2373 +#define MACH_TYPE_ARMADILLO440 2374 +#define MACH_TYPE_U_CHIP_DUAL_ARM 2375 +#define MACH_TYPE_CSR_BDB3 2376 +#define MACH_TYPE_DOLBY_CAT1018 2377 +#define MACH_TYPE_HY9307 2378 +#define MACH_TYPE_A_ES 2379 +#define MACH_TYPE_DAVINCI_IRIF 2380 +#define MACH_TYPE_AGAMA9263 2381 +#define MACH_TYPE_MARVELL_JASPER 2382 +#define MACH_TYPE_FLINT 2383 +#define MACH_TYPE_TAVOREVB3 2384 +#define MACH_TYPE_SCH_M490 2386 +#define MACH_TYPE_RBL01 2387 +#define MACH_TYPE_OMNIFI 2388 +#define MACH_TYPE_OTAVALO 2389 +#define MACH_TYPE_SIENA 2390 +#define MACH_TYPE_HTC_EXCALIBUR_S620 2391 +#define MACH_TYPE_HTC_OPAL 2392 +#define MACH_TYPE_TOUCHBOOK 2393 +#define MACH_TYPE_LATTE 2394 +#define MACH_TYPE_XA200 2395 +#define MACH_TYPE_NIMROD 2396 +#define MACH_TYPE_CC9P9215_3G 2397 +#define MACH_TYPE_CC9P9215_3GJS 2398 +#define MACH_TYPE_TK71 2399 +#define MACH_TYPE_COMHAM3525 2400 +#define MACH_TYPE_MX31EREBUS 2401 +#define MACH_TYPE_MCARDMX27 2402 +#define MACH_TYPE_PARADISE 2403 +#define MACH_TYPE_TIDE 2404 +#define MACH_TYPE_WZL2440 2405 +#define MACH_TYPE_SDRDEMO 2406 +#define MACH_TYPE_ETHERCAN2 2407 +#define MACH_TYPE_ECMIMG20 2408 +#define MACH_TYPE_OMAP_DRAGON 2409 +#define MACH_TYPE_HALO 2410 +#define MACH_TYPE_HUANGSHAN 2411 +#define MACH_TYPE_VL_MA2SC 2412 +#define MACH_TYPE_RAUMFELD_RC 2413 +#define MACH_TYPE_RAUMFELD_CONNECTOR 2414 +#define MACH_TYPE_RAUMFELD_SPEAKER 2415 +#define MACH_TYPE_MULTIBUS_MASTER 2416 +#define MACH_TYPE_MULTIBUS_PBK 2417 +#define MACH_TYPE_TNETV107X 2418 +#define MACH_TYPE_SNAKE 2419 +#define MACH_TYPE_CWMX27 2420 +#define MACH_TYPE_SCH_M480 2421 +#define MACH_TYPE_PLATYPUS 2422 +#define MACH_TYPE_PSS2 2423 +#define MACH_TYPE_DAVINCI_APM150 2424 +#define MACH_TYPE_STR9100 2425 +#define MACH_TYPE_NET5BIG 2426 +#define MACH_TYPE_SEABED9263 2427 +#define MACH_TYPE_MX51_M2ID 2428 +#define MACH_TYPE_OCTVOCPLUS_EB 2429 +#define MACH_TYPE_KLK_FIREFOX 2430 +#define MACH_TYPE_KLK_WIRMA_MODULE 2431 +#define MACH_TYPE_KLK_WIRMA_MMI 2432 +#define MACH_TYPE_SUPERSONIC 2433 +#define MACH_TYPE_LIBERTY 2434 +#define MACH_TYPE_MH355 2435 +#define MACH_TYPE_PC7802 2436 +#define MACH_TYPE_GNET_SGC 2437 +#define MACH_TYPE_EINSTEIN15 2438 +#define MACH_TYPE_CMPD 2439 +#define MACH_TYPE_DAVINCI_HASE1 2440 +#define MACH_TYPE_LGEINCITEPHONE 2441 +#define MACH_TYPE_EA313X 2442 +#define MACH_TYPE_FWBD_39064 2443 +#define MACH_TYPE_FWBD_390128 2444 +#define MACH_TYPE_PELCO_MOE 2445 +#define MACH_TYPE_MINIMIX27 2446 +#define MACH_TYPE_OMAP3_THUNDER 2447 +#define MACH_TYPE_PASSIONC 2448 +#define MACH_TYPE_MX27AMATA 2449 +#define MACH_TYPE_BGAT1 2450 +#define MACH_TYPE_BUZZ 2451 +#define MACH_TYPE_MB9G20 2452 +#define MACH_TYPE_YUSHAN 2453 +#define MACH_TYPE_LIZARD 2454 +#define MACH_TYPE_OMAP3POLYCOM 2455 +#define MACH_TYPE_SMDKV210 2456 +#define MACH_TYPE_BRAVO 2457 +#define MACH_TYPE_SIOGENTOO1 2458 +#define MACH_TYPE_SIOGENTOO2 2459 +#define MACH_TYPE_SM3K 2460 +#define MACH_TYPE_ACER_TEMPO_F900 2461 +#define MACH_TYPE_SST61VC010_DEV 2462 +#define MACH_TYPE_GLITTERTIND 2463 +#define MACH_TYPE_OMAP_ZOOM3 2464 +#define MACH_TYPE_OMAP_3630SDP 2465 +#define MACH_TYPE_CYBOOK2440 2466 +#define MACH_TYPE_TORINO_S 2467 +#define MACH_TYPE_HAVANA 2468 +#define MACH_TYPE_BEAUMONT_11 2469 +#define MACH_TYPE_VANGUARD 2470 +#define MACH_TYPE_S5PC110_DRACO 2471 +#define MACH_TYPE_CARTESIO_TWO 2472 +#define MACH_TYPE_ASTER 2473 +#define MACH_TYPE_VOGUESV210 2474 +#define MACH_TYPE_ACM500X 2475 +#define MACH_TYPE_KM9260 2476 +#define MACH_TYPE_NIDEFLEXG1 2477 +#define MACH_TYPE_CTERA_PLUG_IO 2478 +#define MACH_TYPE_SMARTQ7 2479 +#define MACH_TYPE_AT91SAM9G10EK2 2480 +#define MACH_TYPE_ASUSP527 2481 +#define MACH_TYPE_AT91SAM9G20MPM2 2482 +#define MACH_TYPE_TOPASA900 2483 +#define MACH_TYPE_ELECTRUM_100 2484 +#define MACH_TYPE_MX51GRB 2485 +#define MACH_TYPE_XEA300 2486 +#define MACH_TYPE_HTCSTARTREK 2487 +#define MACH_TYPE_LIMA 2488 +#define MACH_TYPE_CSB740 2489 +#define MACH_TYPE_USB_S8815 2490 +#define MACH_TYPE_WATSON_EFM_PLUGIN 2491 +#define MACH_TYPE_MILKYWAY 2492 +#define MACH_TYPE_G4EVM 2493 +#define MACH_TYPE_PICOMOD6 2494 +#define MACH_TYPE_OMAPL138_HAWKBOARD 2495 +#define MACH_TYPE_IP6000 2496 +#define MACH_TYPE_IP6010 2497 +#define MACH_TYPE_UTM400 2498 +#define MACH_TYPE_OMAP3_ZYBEX 2499 +#define MACH_TYPE_WIRELESS_SPACE 2500 +#define MACH_TYPE_SX560 2501 +#define MACH_TYPE_TS41X 2502 +#define MACH_TYPE_ELPHEL10373 2503 +#define MACH_TYPE_RHOBOT 2504 +#define MACH_TYPE_MX51_REFRESH 2505 +#define MACH_TYPE_LS9260 2506 +#define MACH_TYPE_SHANK 2507 +#define MACH_TYPE_QSD8X50_ST1 2508 +#define MACH_TYPE_AT91SAM9M10EKES 2509 +#define MACH_TYPE_HIRAM 2510 +#define MACH_TYPE_PHY3250 2511 +#define MACH_TYPE_EA3250 2512 +#define MACH_TYPE_FDI3250 2513 +#define MACH_TYPE_WHITESTONE 2514 +#define MACH_TYPE_AT91SAM9263NIT 2515 +#define MACH_TYPE_CCMX51 2516 +#define MACH_TYPE_CCMX51JS 2517 +#define MACH_TYPE_CCWMX51 2518 +#define MACH_TYPE_CCWMX51JS 2519 +#define MACH_TYPE_MINI6410 2520 +#define MACH_TYPE_TINY6410 2521 +#define MACH_TYPE_NANO6410 2522 +#define MACH_TYPE_AT572D940HFNLDB 2523 +#define MACH_TYPE_HTCLEO 2524 +#define MACH_TYPE_AVP13 2525 +#define MACH_TYPE_XXSVIDEOD 2526 +#define MACH_TYPE_VPNEXT 2527 +#define MACH_TYPE_SWARCO_ITC3 2528 +#define MACH_TYPE_TX51 2529 +#define MACH_TYPE_DOLBY_CAT1021 2530 +#define MACH_TYPE_MX28EVK 2531 +#define MACH_TYPE_PHOENIX260 2532 +#define MACH_TYPE_UVACA_STORK 2533 +#define MACH_TYPE_SMARTQ5 2534 +#define MACH_TYPE_ALL3078 2535 +#define MACH_TYPE_CTERA_2BAY_DS 2536 +#define MACH_TYPE_SIOGENTOO3 2537 +#define MACH_TYPE_EPB5000 2538 +#define MACH_TYPE_HY9263 2539 +#define MACH_TYPE_ACER_TEMPO_M900 2540 +#define MACH_TYPE_ACER_TEMPO_DX900 2541 +#define MACH_TYPE_ACER_TEMPO_X960 2542 +#define MACH_TYPE_ACER_ETEN_V900 2543 +#define MACH_TYPE_ACER_ETEN_X900 2544 +#define MACH_TYPE_BONNELL 2545 +#define MACH_TYPE_OHT_MX27 2546 +#define MACH_TYPE_HTCQUARTZ 2547 +#define MACH_TYPE_DAVINCI_DM6467TEVM 2548 +#define MACH_TYPE_C3AX03 2549 +#define MACH_TYPE_MXT_TD60 2550 +#define MACH_TYPE_ESYX 2551 +#define MACH_TYPE_DOVE_DB2 2552 +#define MACH_TYPE_BULLDOG 2553 +#define MACH_TYPE_DERELL_ME2000 2554 +#define MACH_TYPE_BCMRING_BASE 2555 +#define MACH_TYPE_BCMRING_EVM 2556 +#define MACH_TYPE_BCMRING_EVM_JAZZ 2557 +#define MACH_TYPE_BCMRING_SP 2558 +#define MACH_TYPE_BCMRING_SV 2559 +#define MACH_TYPE_BCMRING_SV_JAZZ 2560 +#define MACH_TYPE_BCMRING_TABLET 2561 +#define MACH_TYPE_BCMRING_VP 2562 +#define MACH_TYPE_BCMRING_EVM_SEIKOR 2563 +#define MACH_TYPE_BCMRING_SP_WQVGA 2564 +#define MACH_TYPE_BCMRING_CUSTOM 2565 +#define MACH_TYPE_ACER_S200 2566 +#define MACH_TYPE_BT270 2567 +#define MACH_TYPE_ISEO 2568 +#define MACH_TYPE_CEZANNE 2569 +#define MACH_TYPE_LUCCA 2570 +#define MACH_TYPE_SUPERSMART 2571 +#define MACH_TYPE_CS_MISANO 2572 +#define MACH_TYPE_MAGNOLIA2 2573 +#define MACH_TYPE_EMXX 2574 +#define MACH_TYPE_OUTLAW 2575 +#define MACH_TYPE_RIOT_BEI2 2576 +#define MACH_TYPE_RIOT_VOX 2577 +#define MACH_TYPE_RIOT_X37 2578 +#define MACH_TYPE_MEGA25MX 2579 +#define MACH_TYPE_BENZINA2 2580 +#define MACH_TYPE_IGNITE 2581 +#define MACH_TYPE_FOGGIA 2582 +#define MACH_TYPE_AREZZO 2583 +#define MACH_TYPE_LEICA_SKYWALKER 2584 +#define MACH_TYPE_JACINTO2_JAMR 2585 +#define MACH_TYPE_GTS_NOVA 2586 +#define MACH_TYPE_P3600 2587 +#define MACH_TYPE_DLT2 2588 +#define MACH_TYPE_DF3120 2589 +#define MACH_TYPE_ECUCORE_9G20 2590 +#define MACH_TYPE_NAUTEL_LPC3240 2591 +#define MACH_TYPE_GLACIER 2592 +#define MACH_TYPE_PHRAZER_BULLDOG 2593 +#define MACH_TYPE_OMAP3_BULLDOG 2594 +#define MACH_TYPE_PCA101 2595 +#define MACH_TYPE_BUZZC 2596 +#define MACH_TYPE_SASIE2 2597 +#define MACH_TYPE_DAVINCI_CIO 2598 +#define MACH_TYPE_SMARTMETER_DL 2599 +#define MACH_TYPE_WZL6410 2600 +#define MACH_TYPE_WZL6410M 2601 +#define MACH_TYPE_WZL6410F 2602 +#define MACH_TYPE_WZL6410I 2603 +#define MACH_TYPE_SPACECOM1 2604 +#define MACH_TYPE_PINGU920 2605 +#define MACH_TYPE_BRAVOC 2606 +#define MACH_TYPE_CYBO2440 2607 +#define MACH_TYPE_VDSSW 2608 +#define MACH_TYPE_ROMULUS 2609 +#define MACH_TYPE_OMAP_MAGIC 2610 +#define MACH_TYPE_ELTD100 2611 +#define MACH_TYPE_CAPC7117 2612 +#define MACH_TYPE_SWAN 2613 +#define MACH_TYPE_VEU 2614 +#define MACH_TYPE_RM2 2615 +#define MACH_TYPE_TT2100 2616 +#define MACH_TYPE_VENICE 2617 +#define MACH_TYPE_PC7323 2618 +#define MACH_TYPE_MASP 2619 +#define MACH_TYPE_FUJITSU_TVSTBSOC 2620 +#define MACH_TYPE_FUJITSU_TVSTBSOC1 2621 +#define MACH_TYPE_LEXIKON 2622 +#define MACH_TYPE_MINI2440V2 2623 +#define MACH_TYPE_ICONTROL 2624 +#define MACH_TYPE_SHEEVAD 2625 +#define MACH_TYPE_QSD8X50A_ST1_1 2626 +#define MACH_TYPE_QSD8X50A_ST1_5 2627 +#define MACH_TYPE_BEE 2628 +#define MACH_TYPE_MX23EVK 2629 +#define MACH_TYPE_AP4EVB 2630 +#define MACH_TYPE_STOCKHOLM 2631 +#define MACH_TYPE_LPC_H3131 2632 +#define MACH_TYPE_STINGRAY 2633 +#define MACH_TYPE_KRAKEN 2634 +#define MACH_TYPE_GW2388 2635 +#define MACH_TYPE_JADECPU 2636 +#define MACH_TYPE_CARLISLE 2637 +#define MACH_TYPE_LUX_SF9 2638 +#define MACH_TYPE_NEMID_TB 2639 +#define MACH_TYPE_TERRIER 2640 +#define MACH_TYPE_TURBOT 2641 +#define MACH_TYPE_SANDDAB 2642 +#define MACH_TYPE_MX35_CICADA 2643 +#define MACH_TYPE_GHI2703D 2644 +#define MACH_TYPE_LUX_SFX9 2645 +#define MACH_TYPE_LUX_SF9G 2646 +#define MACH_TYPE_LUX_EDK9 2647 +#define MACH_TYPE_HW90240 2648 +#define MACH_TYPE_DM365_LEOPARD 2649 +#define MACH_TYPE_MITYOMAPL138 2650 +#define MACH_TYPE_SCAT110 2651 +#define MACH_TYPE_ACER_A1 2652 +#define MACH_TYPE_CMCONTROL 2653 +#define MACH_TYPE_PELCO_LAMAR 2654 +#define MACH_TYPE_RFP43 2655 +#define MACH_TYPE_SK86R0301 2656 +#define MACH_TYPE_CTPXA 2657 +#define MACH_TYPE_EPB_ARM9_A 2658 +#define MACH_TYPE_GURUPLUG 2659 +#define MACH_TYPE_SPEAR310 2660 +#define MACH_TYPE_SPEAR320 2661 +#define MACH_TYPE_ROBOTX 2662 +#define MACH_TYPE_LSXHL 2663 +#define MACH_TYPE_SMARTLITE 2664 +#define MACH_TYPE_CWS2 2665 +#define MACH_TYPE_M619 2666 +#define MACH_TYPE_SMARTVIEW 2667 +#define MACH_TYPE_LSA_SALSA 2668 +#define MACH_TYPE_KIZBOX 2669 +#define MACH_TYPE_HTCCHARMER 2670 +#define MACH_TYPE_GUF_NESO_LT 2671 +#define MACH_TYPE_PM9G45 2672 +#define MACH_TYPE_HTCPANTHER 2673 +#define MACH_TYPE_HTCPANTHER_CDMA 2674 +#define MACH_TYPE_REB01 2675 +#define MACH_TYPE_AQUILA 2676 +#define MACH_TYPE_SPARK_SLS_HW2 2677 +#define MACH_TYPE_ESATA_SHEEVAPLUG 2678 +#define MACH_TYPE_MSM7X30_SURF 2679 +#define MACH_TYPE_MICRO2440 2680 +#define MACH_TYPE_AM2440 2681 +#define MACH_TYPE_TQ2440 2682 +#define MACH_TYPE_LPC2478OEM 2683 +#define MACH_TYPE_AK880X 2684 +#define MACH_TYPE_COBRA3530 2685 +#define MACH_TYPE_PMPPB 2686 +#define MACH_TYPE_U6715 2687 +#define MACH_TYPE_AXAR1500_SENDER 2688 +#define MACH_TYPE_G30_DVB 2689 +#define MACH_TYPE_VC088X 2690 +#define MACH_TYPE_MIOA702 2691 +#define MACH_TYPE_HPMIN 2692 +#define MACH_TYPE_AK880XAK 2693 +#define MACH_TYPE_ARM926TOMAP850 2694 +#define MACH_TYPE_LKEVM 2695 +#define MACH_TYPE_MW6410 2696 +#define MACH_TYPE_TERASTATION_WXL 2697 +#define MACH_TYPE_CPU8000E 2698 +#define MACH_TYPE_CATANIA 2699 +#define MACH_TYPE_TOKYO 2700 +#define MACH_TYPE_MSM7201A_SURF 2701 +#define MACH_TYPE_MSM7201A_FFA 2702 +#define MACH_TYPE_MSM7X25_SURF 2703 +#define MACH_TYPE_MSM7X25_FFA 2704 +#define MACH_TYPE_MSM7X27_SURF 2705 +#define MACH_TYPE_MSM7X27_FFA 2706 +#define MACH_TYPE_MSM7X30_FFA 2707 +#define MACH_TYPE_QSD8X50_SURF 2708 +#define MACH_TYPE_QSD8X50_COMET 2709 +#define MACH_TYPE_QSD8X50_FFA 2710 +#define MACH_TYPE_QSD8X50A_SURF 2711 +#define MACH_TYPE_QSD8X50A_FFA 2712 +#define MACH_TYPE_ADX_XGCP10 2713 +#define MACH_TYPE_MCGWUMTS2A 2714 +#define MACH_TYPE_MOBIKT 2715 +#define MACH_TYPE_MX53_EVK 2716 +#define MACH_TYPE_IGEP0030 2717 +#define MACH_TYPE_AXELL_H40_H50_CTRL 2718 +#define MACH_TYPE_DTCOMMOD 2719 +#define MACH_TYPE_GOULD 2720 +#define MACH_TYPE_SIBERIA 2721 +#define MACH_TYPE_SBC3530 2722 +#define MACH_TYPE_QARM 2723 +#define MACH_TYPE_MIPS 2724 +#define MACH_TYPE_MX27GRB 2725 +#define MACH_TYPE_SBC8100 2726 +#define MACH_TYPE_SAARB 2727 +#define MACH_TYPE_OMAP3MINI 2728 +#define MACH_TYPE_CNMBOOK7SE 2729 +#define MACH_TYPE_CATAN 2730 +#define MACH_TYPE_HARMONY 2731 +#define MACH_TYPE_TONGA 2732 +#define MACH_TYPE_CYBOOK_ORIZON 2733 +#define MACH_TYPE_HTCRHODIUMCDMA 2734 +#define MACH_TYPE_EPC_G45 2735 +#define MACH_TYPE_EPC_LPC3250 2736 +#define MACH_TYPE_MXC91341EVB 2737 +#define MACH_TYPE_RTW1000 2738 +#define MACH_TYPE_BOBCAT 2739 +#define MACH_TYPE_TRIZEPS6 2740 +#define MACH_TYPE_MSM7X30_FLUID 2741 +#define MACH_TYPE_NEDAP9263 2742 +#define MACH_TYPE_NETGEAR_MS2110 2743 +#define MACH_TYPE_BMX 2744 +#define MACH_TYPE_NETSTREAM 2745 +#define MACH_TYPE_VPNEXT_RCU 2746 +#define MACH_TYPE_VPNEXT_MPU 2747 +#define MACH_TYPE_BCMRING_TABLET_V1 2748 +#define MACH_TYPE_SGARM10 2749 +#define MACH_TYPE_CM_T3517 2750 +#define MACH_TYPE_OMAP3_CPS 2751 +#define MACH_TYPE_AXAR1500_RECEIVER 2752 +#define MACH_TYPE_WBD222 2753 +#define MACH_TYPE_MT65XX 2754 +#define MACH_TYPE_MSM8X60_SURF 2755 +#define MACH_TYPE_MSM8X60_SIM 2756 +#define MACH_TYPE_VMC300 2757 +#define MACH_TYPE_TCC8000_SDK 2758 +#define MACH_TYPE_NANOS 2759 +#define MACH_TYPE_STAMP9G10 2760 +#define MACH_TYPE_STAMP9G45 2761 +#define MACH_TYPE_H6053 2762 +#define MACH_TYPE_SMINT01 2763 +#define MACH_TYPE_PRTLVT2 2764 +#define MACH_TYPE_AP420 2765 +#define MACH_TYPE_HTCSHIFT 2766 +#define MACH_TYPE_DAVINCI_DM365_FC 2767 +#define MACH_TYPE_MSM8X55_SURF 2768 +#define MACH_TYPE_MSM8X55_FFA 2769 +#define MACH_TYPE_ESL_VAMANA 2770 +#define MACH_TYPE_SBC35 2771 +#define MACH_TYPE_MPX6446 2772 +#define MACH_TYPE_OREO_CONTROLLER 2773 +#define MACH_TYPE_KOPIN_MODELS 2774 +#define MACH_TYPE_TTC_VISION2 2775 +#define MACH_TYPE_CNS3420VB 2776 +#define MACH_TYPE_LPC2 2777 +#define MACH_TYPE_OLYMPUS 2778 +#define MACH_TYPE_VORTEX 2779 +#define MACH_TYPE_S5PC200 2780 +#define MACH_TYPE_ECUCORE_9263 2781 +#define MACH_TYPE_SMDKC200 2782 +#define MACH_TYPE_EMSISO_SX27 2783 +#define MACH_TYPE_APX_SOM9G45_EK 2784 +#define MACH_TYPE_SONGSHAN 2785 +#define MACH_TYPE_TIANSHAN 2786 +#define MACH_TYPE_VPX500 2787 +#define MACH_TYPE_AM3517SAM 2788 +#define MACH_TYPE_SKAT91_SIM508 2789 +#define MACH_TYPE_SKAT91_S3E 2790 +#define MACH_TYPE_OMAP4_PANDA 2791 +#define MACH_TYPE_DF7220 2792 +#define MACH_TYPE_NEMINI 2793 +#define MACH_TYPE_T8200 2794 +#define MACH_TYPE_APF51 2795 +#define MACH_TYPE_DR_RC_UNIT 2796 +#define MACH_TYPE_BORDEAUX 2797 +#define MACH_TYPE_CATANIA_B 2798 +#define MACH_TYPE_MX51_OCEAN 2799 +#define MACH_TYPE_TI8168EVM 2800 +#define MACH_TYPE_NEOCOREOMAP 2801 +#define MACH_TYPE_WITHINGS_WBP 2802 +#define MACH_TYPE_DBPS 2803 +#define MACH_TYPE_SBC9261 2804 +#define MACH_TYPE_PCBFP0001 2805 +#define MACH_TYPE_SPEEDY 2806 +#define MACH_TYPE_CHRYSAOR 2807 +#define MACH_TYPE_TANGO 2808 +#define MACH_TYPE_SYNOLOGY_DSX11 2809 +#define MACH_TYPE_HANLIN_V3EXT 2810 +#define MACH_TYPE_HANLIN_V5 2811 +#define MACH_TYPE_HANLIN_V3PLUS 2812 +#define MACH_TYPE_IRIVER_STORY 2813 +#define MACH_TYPE_IREX_ILIAD 2814 +#define MACH_TYPE_IREX_DR1000 2815 +#define MACH_TYPE_TETON_BGA 2816 +#define MACH_TYPE_SNAPPER9G45 2817 +#define MACH_TYPE_TAM3517 2818 +#define MACH_TYPE_PDC100 2819 +#define MACH_TYPE_EUKREA_CPUIMX25 2820 +#define MACH_TYPE_EUKREA_CPUIMX35 2821 +#define MACH_TYPE_EUKREA_CPUIMX51SD 2822 +#define MACH_TYPE_EUKREA_CPUIMX51 2823 +#define MACH_TYPE_P565 2824 +#define MACH_TYPE_ACER_A4 2825 +#define MACH_TYPE_DAVINCI_DM368_BIP 2826 +#define MACH_TYPE_ESHARE 2827 +#define MACH_TYPE_HW_OMAPL138_EUROPA 2828 +#define MACH_TYPE_WLBARGN 2829 +#define MACH_TYPE_BM170 2830 +#define MACH_TYPE_NETSPACE_MINI_V2 2831 +#define MACH_TYPE_NETSPACE_PLUG_V2 2832 +#define MACH_TYPE_SIEMENS_L1 2833 +#define MACH_TYPE_ELV_LCU1 2834 +#define MACH_TYPE_MCU1 2835 +#define MACH_TYPE_OMAP3_TAO3530 2836 +#define MACH_TYPE_OMAP3_PCUTOUCH 2837 +#define MACH_TYPE_SMDKC210 2838 +#define MACH_TYPE_OMAP3_BRAILLO 2839 +#define MACH_TYPE_SPYPLUG 2840 +#define MACH_TYPE_GINGER 2841 +#define MACH_TYPE_TNY_T3530 2842 +#define MACH_TYPE_PCA102 2843 +#define MACH_TYPE_SPADE 2844 +#define MACH_TYPE_MXC25_TOPAZ 2845 +#define MACH_TYPE_T5325 2846 +#define MACH_TYPE_GW2361 2847 +#define MACH_TYPE_ELOG 2848 +#define MACH_TYPE_INCOME 2849 +#define MACH_TYPE_BCM589X 2850 +#define MACH_TYPE_ETNA 2851 +#define MACH_TYPE_HAWKS 2852 +#define MACH_TYPE_MESON 2853 +#define MACH_TYPE_XSBASE255 2854 +#define MACH_TYPE_PVM2030 2855 +#define MACH_TYPE_MIOA502 2856 +#define MACH_TYPE_VVBOX_SDORIG2 2857 +#define MACH_TYPE_VVBOX_SDLITE2 2858 +#define MACH_TYPE_VVBOX_SDPRO4 2859 +#define MACH_TYPE_HTC_SPV_M700 2860 +#define MACH_TYPE_MX257SX 2861 +#define MACH_TYPE_GONI 2862 +#define MACH_TYPE_MSM8X55_SVLTE_FFA 2863 +#define MACH_TYPE_MSM8X55_SVLTE_SURF 2864 +#define MACH_TYPE_QUICKSTEP 2865 +#define MACH_TYPE_DMW96 2866 +#define MACH_TYPE_HAMMERHEAD 2867 +#define MACH_TYPE_TRIDENT 2868 +#define MACH_TYPE_LIGHTNING 2869 +#define MACH_TYPE_ICONNECT 2870 +#define MACH_TYPE_AUTOBOT 2871 +#define MACH_TYPE_COCONUT 2872 +#define MACH_TYPE_DURIAN 2873 +#define MACH_TYPE_CAYENNE 2874 +#define MACH_TYPE_FUJI 2875 +#define MACH_TYPE_SYNOLOGY_6282 2876 +#define MACH_TYPE_EM1SY 2877 +#define MACH_TYPE_M502 2878 +#define MACH_TYPE_MATRIX518 2879 +#define MACH_TYPE_TINY_GURNARD 2880 +#define MACH_TYPE_SPEAR1310 2881 +#define MACH_TYPE_BV07 2882 +#define MACH_TYPE_MXT_TD61 2883 +#define MACH_TYPE_OPENRD_ULTIMATE 2884 +#define MACH_TYPE_DEVIXP 2885 +#define MACH_TYPE_MICCPT 2886 +#define MACH_TYPE_MIC256 2887 +#define MACH_TYPE_AS1167 2888 +#define MACH_TYPE_OMAP3_IBIZA 2889 +#define MACH_TYPE_U5500 2890 +#define MACH_TYPE_DAVINCI_PICTO 2891 +#define MACH_TYPE_MECHA 2892 +#define MACH_TYPE_BUBBA3 2893 +#define MACH_TYPE_PUPITRE 2894 +#define MACH_TYPE_TEGRA_HARMONY 2895 +#define MACH_TYPE_TEGRA_VOGUE 2896 +#define MACH_TYPE_TEGRA_E1165 2897 +#define MACH_TYPE_SIMPLENET 2898 +#define MACH_TYPE_EC4350TBM 2899 +#define MACH_TYPE_PEC_TC 2900 +#define MACH_TYPE_PEC_HC2 2901 +#define MACH_TYPE_ESL_MOBILIS_A 2902 +#define MACH_TYPE_ESL_MOBILIS_B 2903 +#define MACH_TYPE_ESL_WAVE_A 2904 +#define MACH_TYPE_ESL_WAVE_B 2905 +#define MACH_TYPE_UNISENSE_MMM 2906 +#define MACH_TYPE_BLUESHARK 2907 +#define MACH_TYPE_E10 2908 +#define MACH_TYPE_APP3K_ROBIN 2909 +#define MACH_TYPE_POV15HD 2910 +#define MACH_TYPE_STELLA 2911 +#define MACH_TYPE_MACH_HTC_IOLITE 2912 +#define MACH_TYPE_LINKSTATION_LSCHL 2913 +#define MACH_TYPE_NETWALKER 2914 +#define MACH_TYPE_ACSX106 2915 +#define MACH_TYPE_ATLAS5_C1 2916 +#define MACH_TYPE_NSB3AST 2917 +#define MACH_TYPE_GNET_SLC 2918 +#define MACH_TYPE_AF4000 2919 +#define MACH_TYPE_ARK9431 2920 +#define MACH_TYPE_FS_S5PC100 2921 +#define MACH_TYPE_OMAP3505NOVA8 2922 +#define MACH_TYPE_OMAP3621_EDP1 2923 +#define MACH_TYPE_ORATISAES 2924 +#define MACH_TYPE_SMDKV310 2925 +#define MACH_TYPE_SIEMENS_L0 2926 +#define MACH_TYPE_VENTANA 2927 +#define MACH_TYPE_WM8505_7IN_NETBOOK 2928 +#define MACH_TYPE_EC4350SDB 2929 +#define MACH_TYPE_MIMAS 2930 +#define MACH_TYPE_TITAN 2931 +#define MACH_TYPE_CRANEBOARD 2932 +#define MACH_TYPE_ES2440 2933 +#define MACH_TYPE_NAJAY_A9263 2934 +#define MACH_TYPE_HTCTORNADO 2935 +#define MACH_TYPE_DIMM_MX257 2936 +#define MACH_TYPE_JIGEN 2937 +#define MACH_TYPE_SMDK6450 2938 +#define MACH_TYPE_MENO_QNG 2939 +#define MACH_TYPE_NS2416 2940 +#define MACH_TYPE_RPC353 2941 +#define MACH_TYPE_TQ6410 2942 +#define MACH_TYPE_SKY6410 2943 +#define MACH_TYPE_DYNASTY 2944 +#define MACH_TYPE_VIVO 2945 +#define MACH_TYPE_BURY_BL7582 2946 +#define MACH_TYPE_BURY_BPS5270 2947 +#define MACH_TYPE_BASI 2948 +#define MACH_TYPE_TN200 2949 +#define MACH_TYPE_C2MMI 2950 +#define MACH_TYPE_MESON_6236M 2951 +#define MACH_TYPE_MESON_8626M 2952 +#define MACH_TYPE_TUBE 2953 +#define MACH_TYPE_MESSINA 2954 +#define MACH_TYPE_MX50_ARM2 2955 +#define MACH_TYPE_CETUS9263 2956 +#define MACH_TYPE_BROWNSTONE 2957 +#define MACH_TYPE_VMX25 2958 +#define MACH_TYPE_VMX51 2959 +#define MACH_TYPE_ABACUS 2960 +#define MACH_TYPE_CM4745 2961 +#define MACH_TYPE_ORATISLINK 2962 +#define MACH_TYPE_DAVINCI_DM365_DVR 2963 +#define MACH_TYPE_NETVIZ 2964 +#define MACH_TYPE_FLEXIBITY 2965 +#define MACH_TYPE_WLAN_COMPUTER 2966 +#define MACH_TYPE_LPC24XX 2967 +#define MACH_TYPE_SPICA 2968 +#define MACH_TYPE_GPSDISPLAY 2969 +#define MACH_TYPE_BIPNET 2970 +#define MACH_TYPE_OVERO_CTU_INERTIAL 2971 +#define MACH_TYPE_DAVINCI_DM355_MMM 2972 +#define MACH_TYPE_PC9260_V2 2973 +#define MACH_TYPE_PTX7545 2974 +#define MACH_TYPE_TM_EFDC 2975 +#define MACH_TYPE_WALDO1 2976 +#define MACH_TYPE_OMAP3_WALDO1 2977 +#define MACH_TYPE_FLYER 2978 +#define MACH_TYPE_TORNADO3240 2979 +#define MACH_TYPE_SOLI_01 2980 +#define MACH_TYPE_OMAPL138_EUROPALC 2981 +#define MACH_TYPE_HELIOS_V1 2982 +#define MACH_TYPE_NETSPACE_LITE_V2 2983 +#define MACH_TYPE_SSC 2984 +#define MACH_TYPE_PREMIERWAVE_EN 2985 +#define MACH_TYPE_WASABI 2986 +#define MACH_TYPE_VIVOW 2987 +#define MACH_TYPE_MX50_RDP 2988 +#define MACH_TYPE_UNIVERSAL_C210 2989 +#define MACH_TYPE_REAL6410 2990 +#define MACH_TYPE_SPX_SAKURA 2991 +#define MACH_TYPE_IJ3K_2440 2992 +#define MACH_TYPE_OMAP3_BC10 2993 +#define MACH_TYPE_THEBE 2994 +#define MACH_TYPE_RV082 2995 +#define MACH_TYPE_ARMLGUEST 2996 +#define MACH_TYPE_TJINC1000 2997 +#define MACH_TYPE_DOCKSTAR 2998 +#define MACH_TYPE_AX8008 2999 +#define MACH_TYPE_GNET_SGCE 3000 +#define MACH_TYPE_PXWNAS_500_1000 3001 +#define MACH_TYPE_EA20 3002 +#define MACH_TYPE_AWM2 3003 +#define MACH_TYPE_TI8148EVM 3004 +#define MACH_TYPE_TEGRA_SEABOARD 3005 +#define MACH_TYPE_LINKSTATION_CHLV2 3006 +#define MACH_TYPE_TERA_PRO2_RACK 3007 +#define MACH_TYPE_RUBYS 3008 +#define MACH_TYPE_AQUARIUS 3009 +#define MACH_TYPE_MX53_ARD 3010 +#define MACH_TYPE_MX53_SMD 3011 +#define MACH_TYPE_LSWXL 3012 +#define MACH_TYPE_DOVE_AVNG_V3 3013 +#define MACH_TYPE_SDI_ESS_9263 3014 +#define MACH_TYPE_JOCPU550 3015 +#define MACH_TYPE_MSM8X60_RUMI3 3016 +#define MACH_TYPE_MSM8X60_FFA 3017 +#define MACH_TYPE_YANOMAMI 3018 +#define MACH_TYPE_GTA04 3019 +#define MACH_TYPE_CM_A510 3020 +#define MACH_TYPE_OMAP3_RFS200 3021 +#define MACH_TYPE_KX33XX 3022 +#define MACH_TYPE_PTX7510 3023 +#define MACH_TYPE_TOP9000 3024 +#define MACH_TYPE_TEENOTE 3025 +#define MACH_TYPE_TS3 3026 +#define MACH_TYPE_A0 3027 +#define MACH_TYPE_FSM9XXX_SURF 3028 +#define MACH_TYPE_FSM9XXX_FFA 3029 +#define MACH_TYPE_FRRHWCDMA60W 3030 +#define MACH_TYPE_REMUS 3031 +#define MACH_TYPE_AT91CAP7XDK 3032 +#define MACH_TYPE_AT91CAP7STK 3033 +#define MACH_TYPE_KT_SBC_SAM9_1 3034 +#define MACH_TYPE_ORATISROUTER 3035 +#define MACH_TYPE_ARMADA_XP_DB 3036 +#define MACH_TYPE_SPDM 3037 +#define MACH_TYPE_GTIB 3038 +#define MACH_TYPE_DGM3240 3039 +#define MACH_TYPE_ATLAS_I_LPE 3040 +#define MACH_TYPE_HTCMEGA 3041 +#define MACH_TYPE_TRICORDER 3042 +#define MACH_TYPE_TX28 3043 +#define MACH_TYPE_BSTBRD 3044 +#define MACH_TYPE_PWB3090 3045 +#define MACH_TYPE_IDEA6410 3046 +#define MACH_TYPE_QBC9263 3047 +#define MACH_TYPE_BORABORA 3048 +#define MACH_TYPE_VALDEZ 3049 +#define MACH_TYPE_LS9G20 3050 +#define MACH_TYPE_MIOS_V1 3051 +#define MACH_TYPE_S5PC110_CRESPO 3052 +#define MACH_TYPE_CONTROLTEK9G20 3053 +#define MACH_TYPE_TIN307 3054 +#define MACH_TYPE_TIN510 3055 +#define MACH_TYPE_EP3517 3056 +#define MACH_TYPE_BLUECHEESE 3057 +#define MACH_TYPE_TEM3X30 3058 +#define MACH_TYPE_HARVEST_DESOTO 3059 +#define MACH_TYPE_MSM8X60_QRDC 3060 +#define MACH_TYPE_SPEAR900 3061 +#define MACH_TYPE_PCONTROL_G20 3062 +#define MACH_TYPE_RDSTOR 3063 +#define MACH_TYPE_USDLOADER 3064 +#define MACH_TYPE_TSOPLOADER 3065 +#define MACH_TYPE_KRONOS 3066 +#define MACH_TYPE_FFCORE 3067 +#define MACH_TYPE_MONE 3068 +#define MACH_TYPE_UNIT2S 3069 +#define MACH_TYPE_ACER_A5 3070 +#define MACH_TYPE_ETHERPRO_ISP 3071 +#define MACH_TYPE_STRETCHS7000 3072 +#define MACH_TYPE_P87_SMARTSIM 3073 +#define MACH_TYPE_TULIP 3074 +#define MACH_TYPE_SUNFLOWER 3075 +#define MACH_TYPE_RIB 3076 +#define MACH_TYPE_CLOD 3077 +#define MACH_TYPE_RUMP 3078 +#define MACH_TYPE_TENDERLOIN 3079 +#define MACH_TYPE_SHORTLOIN 3080 +#define MACH_TYPE_CRESPO 3081 +#define MACH_TYPE_ANTARES 3082 +#define MACH_TYPE_WB40N 3083 +#define MACH_TYPE_HERRING 3084 +#define MACH_TYPE_NAXY400 3085 +#define MACH_TYPE_NAXY1200 3086 +#define MACH_TYPE_VPR200 3087 +#define MACH_TYPE_BUG20 3088 +#define MACH_TYPE_GOFLEXNET 3089 +#define MACH_TYPE_TORBRECK 3090 +#define MACH_TYPE_SAARB_MG1 3091 +#define MACH_TYPE_CALLISTO 3092 +#define MACH_TYPE_MULTHSU 3093 +#define MACH_TYPE_SALUDA 3094 +#define MACH_TYPE_PEMP_OMAP3_APOLLO 3095 +#define MACH_TYPE_VC0718 3096 +#define MACH_TYPE_MVBLX 3097 +#define MACH_TYPE_INHAND_APEIRON 3098 +#define MACH_TYPE_INHAND_FURY 3099 +#define MACH_TYPE_INHAND_SIREN 3100 +#define MACH_TYPE_HDNVP 3101 +#define MACH_TYPE_SOFTWINNER 3102 +#define MACH_TYPE_PRIMA2_EVB 3103 +#define MACH_TYPE_NAS6210 3104 +#define MACH_TYPE_UNISDEV 3105 +#define MACH_TYPE_SBCA11 3106 +#define MACH_TYPE_SAGA 3107 +#define MACH_TYPE_NS_K330 3108 +#define MACH_TYPE_TANNA 3109 +#define MACH_TYPE_IMATE8502 3110 +#define MACH_TYPE_ASPEN 3111 +#define MACH_TYPE_DAINTREE_CWAC 3112 +#define MACH_TYPE_ZMX25 3113 +#define MACH_TYPE_MAPLE1 3114 +#define MACH_TYPE_QSD8X72_SURF 3115 +#define MACH_TYPE_QSD8X72_FFA 3116 +#define MACH_TYPE_ABILENE 3117 +#define MACH_TYPE_EIGEN_TTR 3118 +#define MACH_TYPE_IOMEGA_IX2_200 3119 +#define MACH_TYPE_CORETEC_VCX7400 3120 +#define MACH_TYPE_SANTIAGO 3121 +#define MACH_TYPE_MX257SOL 3122 +#define MACH_TYPE_STRASBOURG 3123 +#define MACH_TYPE_MSM8X60_FLUID 3124 +#define MACH_TYPE_SMARTQV5 3125 +#define MACH_TYPE_SMARTQV3 3126 +#define MACH_TYPE_SMARTQV7 3127 +#define MACH_TYPE_PAZ00 3128 +#define MACH_TYPE_ACMENETUSFOXG20 3129 +#define MACH_TYPE_HTCWILLOW 3130 +#define MACH_TYPE_FWBD_0404 3131 +#define MACH_TYPE_HDGU 3132 +#define MACH_TYPE_PYRAMID 3133 +#define MACH_TYPE_EPIPHAN 3134 +#define MACH_TYPE_OMAP_BENDER 3135 +#define MACH_TYPE_GURNARD 3136 +#define MACH_TYPE_GTL_IT5100 3137 +#define MACH_TYPE_BCM2708 3138 +#define MACH_TYPE_MX51_GGC 3139 +#define MACH_TYPE_SHARESPACE 3140 +#define MACH_TYPE_HABA_KNX_EXPLORER 3141 +#define MACH_TYPE_SIMTEC_KIRKMOD 3142 +#define MACH_TYPE_CRUX 3143 +#define MACH_TYPE_MX51_BRAVO 3144 +#define MACH_TYPE_CHARON 3145 +#define MACH_TYPE_PICOCOM3 3146 +#define MACH_TYPE_PICOCOM4 3147 +#define MACH_TYPE_SERRANO 3148 +#define MACH_TYPE_DOUBLESHOT 3149 +#define MACH_TYPE_EVSY 3150 +#define MACH_TYPE_HUASHAN 3151 +#define MACH_TYPE_LAUSANNE 3152 +#define MACH_TYPE_EMERALD 3153 +#define MACH_TYPE_TQMA35 3154 +#define MACH_TYPE_MARVEL 3155 +#define MACH_TYPE_MANUAE 3156 +#define MACH_TYPE_CHACHA 3157 +#define MACH_TYPE_LEMON 3158 +#define MACH_TYPE_CSC 3159 +#define MACH_TYPE_GIRA_KNXIP_ROUTER 3160 +#define MACH_TYPE_T20 3161 +#define MACH_TYPE_HDMINI 3162 +#define MACH_TYPE_SCIPHONE_G2 3163 +#define MACH_TYPE_EXPRESS 3164 +#define MACH_TYPE_EXPRESS_KT 3165 +#define MACH_TYPE_MAXIMASP 3166 +#define MACH_TYPE_NITROGEN_IMX51 3167 +#define MACH_TYPE_NITROGEN_IMX53 3168 +#define MACH_TYPE_SUNFIRE 3169 +#define MACH_TYPE_AROWANA 3170 +#define MACH_TYPE_TEGRA_DAYTONA 3171 +#define MACH_TYPE_TEGRA_SWORDFISH 3172 +#define MACH_TYPE_EDISON 3173 +#define MACH_TYPE_SVP8500V1 3174 +#define MACH_TYPE_SVP8500V2 3175 +#define MACH_TYPE_SVP5500 3176 +#define MACH_TYPE_B5500 3177 +#define MACH_TYPE_S5500 3178 +#define MACH_TYPE_ICON 3179 +#define MACH_TYPE_ELEPHANT 3180 +#define MACH_TYPE_MSM8X60_FUSION 3181 +#define MACH_TYPE_SHOOTER 3182 +#define MACH_TYPE_SPADE_LTE 3183 +#define MACH_TYPE_PHILHWANI 3184 +#define MACH_TYPE_GSNCOMM 3185 +#define MACH_TYPE_STRASBOURG_A2 3186 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -5977,6 +7548,18 @@ extern unsigned int __machine_arch_type; # define machine_is_bronco() (0) #endif +#ifdef CONFIG_ARCH_ESL_WIRELESS_TAB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_WIRELESS_TAB +# endif +# define machine_is_esl_wireless_tab() (machine_arch_type == MACH_TYPE_ESL_WIRELESS_TAB) +#else +# define machine_is_esl_wireless_tab() (0) +#endif + #ifdef CONFIG_ARCH_ESL_SOFCOMP # ifdef machine_arch_type # undef machine_arch_type @@ -6037,14 +7620,14 @@ extern unsigned int __machine_arch_type; # define machine_is_prayoglite() (0) #endif -#ifdef CONFIG_ARCH_GUMSTIK +#ifdef CONFIG_ARCH_GUMSTIX # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_GUMSTIK +# define machine_arch_type MACH_TYPE_GUMSTIX # endif -# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIK) +# define machine_is_gumstix() (machine_arch_type == MACH_TYPE_GUMSTIX) #else # define machine_is_gumstix() (0) #endif @@ -8113,18 +9696,6 @@ extern unsigned int __machine_arch_type; # define machine_is_aml42800aa() (0) #endif -#ifdef CONFIG_MACH_MACH_TYPE_ML674001 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MACH_TYPE_ML674001 -# endif -# define machine_is_ml674001() (machine_arch_type == MACH_TYPE_MACH_TYPE_ML674001) -#else -# define machine_is_ml674001() (0) -#endif - #ifdef CONFIG_MACH_LPC2294 # ifdef machine_arch_type # undef machine_arch_type @@ -10369,18 +11940,6 @@ extern unsigned int __machine_arch_type; # define machine_is_puppeteer() (0) #endif -#ifdef CONFIG_MACH_MACH_VADATECH -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MACH_VADATECH -# endif -# define machine_is_vt001() (machine_arch_type == MACH_TYPE_MACH_VADATECH) -#else -# define machine_is_vt001() (0) -#endif - #ifdef CONFIG_MACH_E570 # ifdef machine_arch_type # undef machine_arch_type @@ -11461,16 +13020,16 @@ extern unsigned int __machine_arch_type; # define machine_is_samoa() (0) #endif -#ifdef CONFIG_MACH_T3XSCALE +#ifdef CONFIG_MACH_PALMT3 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_T3XSCALE +# define machine_arch_type MACH_TYPE_PALMT3 # endif -# define machine_is_t3xscale() (machine_arch_type == MACH_TYPE_T3XSCALE) +# define machine_is_palmt3() (machine_arch_type == MACH_TYPE_PALMT3) #else -# define machine_is_t3xscale() (0) +# define machine_is_palmt3() (0) #endif #ifdef CONFIG_MACH_I878 @@ -11533,16 +13092,16 @@ extern unsigned int __machine_arch_type; # define machine_is_omap_palmtt2() (0) #endif -#ifdef CONFIG_MACH_XSCALE_PALMLD +#ifdef CONFIG_MACH_PALMLD # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XSCALE_PALMLD +# define machine_arch_type MACH_TYPE_PALMLD # endif -# define machine_is_xscale_palmld() (machine_arch_type == MACH_TYPE_XSCALE_PALMLD) +# define machine_is_palmld() (machine_arch_type == MACH_TYPE_PALMLD) #else -# define machine_is_xscale_palmld() (0) +# define machine_is_palmld() (0) #endif #ifdef CONFIG_MACH_CC9C @@ -11641,16 +13200,16 @@ extern unsigned int __machine_arch_type; # define machine_is_maestro() (0) #endif -#ifdef CONFIG_MACH_TUNGE2 +#ifdef CONFIG_MACH_PALMTE2 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_TUNGE2 +# define machine_arch_type MACH_TYPE_PALMTE2 # endif -# define machine_is_tunge2() (machine_arch_type == MACH_TYPE_TUNGE2) +# define machine_is_palmte2() (machine_arch_type == MACH_TYPE_PALMTE2) #else -# define machine_is_tunge2() (0) +# define machine_is_palmte2() (0) #endif #ifdef CONFIG_MACH_IXBBM @@ -12133,16 +13692,16 @@ extern unsigned int __machine_arch_type; # define machine_is_mahi_cdac() (0) #endif -#ifdef CONFIG_MACH_XSCALE_PALMTX +#ifdef CONFIG_MACH_PALMTX # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XSCALE_PALMTX +# define machine_arch_type MACH_TYPE_PALMTX # endif -# define machine_is_xscale_palmtx() (machine_arch_type == MACH_TYPE_XSCALE_PALMTX) +# define machine_is_palmtx() (machine_arch_type == MACH_TYPE_PALMTX) #else -# define machine_is_xscale_palmtx() (0) +# define machine_is_palmtx() (0) #endif #ifdef CONFIG_MACH_S3C2413 @@ -12409,16 +13968,16 @@ extern unsigned int __machine_arch_type; # define machine_is_omap_twip() (0) #endif -#ifdef CONFIG_MACH_XSCALE_PALMTREO650 +#ifdef CONFIG_MACH_TREO650 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XSCALE_PALMTREO650 +# define machine_arch_type MACH_TYPE_TREO650 # endif -# define machine_is_xscale_treo650() (machine_arch_type == MACH_TYPE_XSCALE_PALMTREO650) +# define machine_is_treo650() (machine_arch_type == MACH_TYPE_TREO650) #else -# define machine_is_xscale_treo650() (0) +# define machine_is_treo650() (0) #endif #ifdef CONFIG_MACH_ACUMEN @@ -12505,28 +14064,28 @@ extern unsigned int __machine_arch_type; # define machine_is_netclient() (0) #endif -#ifdef CONFIG_MACH_XSCALE_PALMTT5 +#ifdef CONFIG_MACH_PALMT5 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XSCALE_PALMTT5 +# define machine_arch_type MACH_TYPE_PALMT5 # endif -# define machine_is_xscale_palmtt5() (machine_arch_type == MACH_TYPE_XSCALE_PALMTT5) +# define machine_is_palmt5() (machine_arch_type == MACH_TYPE_PALMT5) #else -# define machine_is_xscale_palmtt5() (0) +# define machine_is_palmt5() (0) #endif -#ifdef CONFIG_MACH_OMAP_PALMTC +#ifdef CONFIG_MACH_PALMTC # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_OMAP_PALMTC +# define machine_arch_type MACH_TYPE_PALMTC # endif -# define machine_is_xscale_palmtc() (machine_arch_type == MACH_TYPE_OMAP_PALMTC) +# define machine_is_palmtc() (machine_arch_type == MACH_TYPE_PALMTC) #else -# define machine_is_xscale_palmtc() (0) +# define machine_is_palmtc() (0) #endif #ifdef CONFIG_MACH_OMAP_APOLLON @@ -12560,9 +14119,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_REA_2D # endif -# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D) +# define machine_is_rea_cpu2() (machine_arch_type == MACH_TYPE_REA_2D) #else -# define machine_is_rea_2d() (0) +# define machine_is_rea_cpu2() (0) #endif #ifdef CONFIG_MACH_TI3E524 @@ -14569,16 +16128,16 @@ extern unsigned int __machine_arch_type; # define machine_is_ecsd() (0) #endif -#ifdef CONFIG_MACH_ZIRE31 +#ifdef CONFIG_MACH_PALMZ31 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_ZIRE31 +# define machine_arch_type MACH_TYPE_PALMZ31 # endif -# define machine_is_zire31() (machine_arch_type == MACH_TYPE_ZIRE31) +# define machine_is_palmz31() (machine_arch_type == MACH_TYPE_PALMZ31) #else -# define machine_is_zire31() (0) +# define machine_is_palmz31() (0) #endif #ifdef CONFIG_MACH_FSG @@ -16033,18 +17592,6 @@ extern unsigned int __machine_arch_type; # define machine_is_eti_c1() (0) #endif -#ifdef CONFIG_MACH_MACH_DEP2410 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MACH_DEP2410 -# endif -# define machine_is_mach_dep2410() (machine_arch_type == MACH_TYPE_MACH_DEP2410) -#else -# define machine_is_mach_dep2410() (0) -#endif - #ifdef CONFIG_MACH_AC100 # ifdef machine_arch_type # undef machine_arch_type @@ -16213,16 +17760,16 @@ extern unsigned int __machine_arch_type; # define machine_is_htcwizard() (0) #endif -#ifdef CONFIG_MACH_XSCALE_TREO680 +#ifdef CONFIG_MACH_TREO680 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XSCALE_TREO680 +# define machine_arch_type MACH_TYPE_TREO680 # endif -# define machine_is_xscale_treo680() (machine_arch_type == MACH_TYPE_XSCALE_TREO680) +# define machine_is_treo680() (machine_arch_type == MACH_TYPE_TREO680) #else -# define machine_is_xscale_treo680() (0) +# define machine_is_treo680() (0) #endif #ifdef CONFIG_MACH_TECON_TMEZON @@ -16501,18 +18048,6 @@ extern unsigned int __machine_arch_type; # define machine_is_schmoogie() (0) #endif -#ifdef CONFIG_MACH_SFFSDR -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SFFSDR -# endif -# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR) -#else -# define machine_is_sffsdr() (0) -#endif - #ifdef CONFIG_MACH_AZTOOL # ifdef machine_arch_type # undef machine_arch_type @@ -17276,9 +18811,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_HYNET_INE # endif -# define machine_is_hynet_ine() (machine_arch_type == MACH_TYPE_HYNET_INE) +# define machine_is_argonst_foundation() (machine_arch_type == MACH_TYPE_HYNET_INE) #else -# define machine_is_hynet_ine() (0) +# define machine_is_argonst_foundation() (0) #endif #ifdef CONFIG_MACH_HYNET_APP @@ -18001,14 +19536,14 @@ extern unsigned int __machine_arch_type; # define machine_is_davinci_dm6467_evm() (0) #endif -#ifdef CONFIG_MACH_DAVINCI_DM350_EVM +#ifdef CONFIG_MACH_DAVINCI_DM355_EVM # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_DAVINCI_DM350_EVM +# define machine_arch_type MACH_TYPE_DAVINCI_DM355_EVM # endif -# define machine_is_davinci_dm355_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM350_EVM) +# define machine_is_davinci_dm355_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM) #else # define machine_is_davinci_dm355_evm() (0) #endif @@ -18457,52 +19992,52 @@ extern unsigned int __machine_arch_type; # define machine_is_sideoatsgrama() (0) #endif -#ifdef CONFIG_MACH_XSCALE_PALMT700P +#ifdef CONFIG_MACH_TREO700P # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XSCALE_PALMT700P +# define machine_arch_type MACH_TYPE_TREO700P # endif -# define machine_is_xscale_palmt700p() (machine_arch_type == MACH_TYPE_XSCALE_PALMT700P) +# define machine_is_treo700p() (machine_arch_type == MACH_TYPE_TREO700P) #else -# define machine_is_xscale_palmt700p() (0) +# define machine_is_treo700p() (0) #endif -#ifdef CONFIG_MACH_XSCALE_PALMT700W +#ifdef CONFIG_MACH_TREO700W # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XSCALE_PALMT700W +# define machine_arch_type MACH_TYPE_TREO700W # endif -# define machine_is_xscale_palmt700w() (machine_arch_type == MACH_TYPE_XSCALE_PALMT700W) +# define machine_is_treo700w() (machine_arch_type == MACH_TYPE_TREO700W) #else -# define machine_is_xscale_palmt700w() (0) +# define machine_is_treo700w() (0) #endif -#ifdef CONFIG_MACH_XSCALE_PALMT750 +#ifdef CONFIG_MACH_TREO750 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XSCALE_PALMT750 +# define machine_arch_type MACH_TYPE_TREO750 # endif -# define machine_is_xscale_palmt750() (machine_arch_type == MACH_TYPE_XSCALE_PALMT750) +# define machine_is_treo750() (machine_arch_type == MACH_TYPE_TREO750) #else -# define machine_is_xscale_palmt750() (0) +# define machine_is_treo750() (0) #endif -#ifdef CONFIG_MACH_XSCALE_PALMT755P +#ifdef CONFIG_MACH_TREO755P # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XSCALE_PALMT755P +# define machine_arch_type MACH_TYPE_TREO755P # endif -# define machine_is_xscale_palmt755p() (machine_arch_type == MACH_TYPE_XSCALE_PALMT755P) +# define machine_is_treo755p() (machine_arch_type == MACH_TYPE_TREO755P) #else -# define machine_is_xscale_palmt755p() (0) +# define machine_is_treo755p() (0) #endif #ifdef CONFIG_MACH_EZREGANUT9200 @@ -18901,14 +20436,14 @@ extern unsigned int __machine_arch_type; # define machine_is_tct_hammer() (0) #endif -#ifdef CONFIG_MACH_HERMES +#ifdef CONFIG_MACH_HERALD # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_HERMES +# define machine_arch_type MACH_TYPE_HERALD # endif -# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERMES) +# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERALD) #else # define machine_is_herald() (0) #endif @@ -18961,16 +20496,16 @@ extern unsigned int __machine_arch_type; # define machine_is_adx_wsc2() (0) #endif -#ifdef CONFIG_MACH_ADX_MEDINET +#ifdef CONFIG_MACH_ADX_MEDCOM # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_ADX_MEDINET +# define machine_arch_type MACH_TYPE_ADX_MEDCOM # endif -# define machine_is_adx_medinet() (machine_arch_type == MACH_TYPE_ADX_MEDINET) +# define machine_is_adx_medcom() (machine_arch_type == MACH_TYPE_ADX_MEDCOM) #else -# define machine_is_adx_medinet() (0) +# define machine_is_adx_medcom() (0) #endif #ifdef CONFIG_MACH_BBOARD @@ -19633,16 +21168,16 @@ extern unsigned int __machine_arch_type; # define machine_is_tll5000() (0) #endif -#ifdef CONFIG_MACH_HNI_X270 +#ifdef CONFIG_MACH_BEBOT # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_HNI_X270 +# define machine_arch_type MACH_TYPE_BEBOT # endif -# define machine_is_hni270() (machine_arch_type == MACH_TYPE_HNI_X270) +# define machine_is_bebot() (machine_arch_type == MACH_TYPE_BEBOT) #else -# define machine_is_hni270() (0) +# define machine_is_bebot() (0) #endif #ifdef CONFIG_MACH_QONG @@ -20605,11 +22140,18897 @@ extern unsigned int __machine_arch_type; # define machine_is_dexflex2() (0) #endif +#ifdef CONFIG_MACH_OW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OW +# endif +# define machine_is_ow() (machine_arch_type == MACH_TYPE_OW) +#else +# define machine_is_ow() (0) +#endif + +#ifdef CONFIG_MACH_ARMEBS3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMEBS3 +# endif +# define machine_is_armebs3() (machine_arch_type == MACH_TYPE_ARMEBS3) +#else +# define machine_is_armebs3() (0) +#endif + +#ifdef CONFIG_MACH_U3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U3 +# endif +# define machine_is_u3() (machine_arch_type == MACH_TYPE_U3) +#else +# define machine_is_u3() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2450 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2450 +# endif +# define machine_is_smdk2450() (machine_arch_type == MACH_TYPE_SMDK2450) +#else +# define machine_is_smdk2450() (0) +#endif + +#ifdef CONFIG_MACH_RSI_EWS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSI_EWS +# endif +# define machine_is_rsi_ews() (machine_arch_type == MACH_TYPE_RSI_EWS) +#else +# define machine_is_rsi_ews() (0) +#endif + +#ifdef CONFIG_MACH_TNB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNB +# endif +# define machine_is_tnb() (machine_arch_type == MACH_TYPE_TNB) +#else +# define machine_is_tnb() (0) +#endif + +#ifdef CONFIG_MACH_TOEPATH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOEPATH +# endif +# define machine_is_toepath() (machine_arch_type == MACH_TYPE_TOEPATH) +#else +# define machine_is_toepath() (0) +#endif + +#ifdef CONFIG_MACH_KB9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KB9263 +# endif +# define machine_is_kb9263() (machine_arch_type == MACH_TYPE_KB9263) +#else +# define machine_is_kb9263() (0) +#endif + +#ifdef CONFIG_MACH_MT7108 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MT7108 +# endif +# define machine_is_mt7108() (machine_arch_type == MACH_TYPE_MT7108) +#else +# define machine_is_mt7108() (0) +#endif + +#ifdef CONFIG_MACH_SMTR2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMTR2440 +# endif +# define machine_is_smtr2440() (machine_arch_type == MACH_TYPE_SMTR2440) +#else +# define machine_is_smtr2440() (0) +#endif + +#ifdef CONFIG_MACH_MANAO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MANAO +# endif +# define machine_is_manao() (machine_arch_type == MACH_TYPE_MANAO) +#else +# define machine_is_manao() (0) +#endif + +#ifdef CONFIG_MACH_CM_X300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_X300 +# endif +# define machine_is_cm_x300() (machine_arch_type == MACH_TYPE_CM_X300) +#else +# define machine_is_cm_x300() (0) +#endif + +#ifdef CONFIG_MACH_GULFSTREAM_KP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GULFSTREAM_KP +# endif +# define machine_is_gulfstream_kp() (machine_arch_type == MACH_TYPE_GULFSTREAM_KP) +#else +# define machine_is_gulfstream_kp() (0) +#endif + +#ifdef CONFIG_MACH_LANREADYFN522 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LANREADYFN522 +# endif +# define machine_is_lanreadyfn522() (machine_arch_type == MACH_TYPE_LANREADYFN522) +#else +# define machine_is_lanreadyfn522() (0) +#endif + +#ifdef CONFIG_MACH_ARMA37 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMA37 +# endif +# define machine_is_arma37() (machine_arch_type == MACH_TYPE_ARMA37) +#else +# define machine_is_arma37() (0) +#endif + +#ifdef CONFIG_MACH_MENDEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MENDEL +# endif +# define machine_is_mendel() (machine_arch_type == MACH_TYPE_MENDEL) +#else +# define machine_is_mendel() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_ILIAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_ILIAD +# endif +# define machine_is_pelco_iliad() (machine_arch_type == MACH_TYPE_PELCO_ILIAD) +#else +# define machine_is_pelco_iliad() (0) +#endif + +#ifdef CONFIG_MACH_UNIT2P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNIT2P +# endif +# define machine_is_unit2p() (machine_arch_type == MACH_TYPE_UNIT2P) +#else +# define machine_is_unit2p() (0) +#endif + +#ifdef CONFIG_MACH_INC20OTTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INC20OTTER +# endif +# define machine_is_inc20otter() (machine_arch_type == MACH_TYPE_INC20OTTER) +#else +# define machine_is_inc20otter() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20EK +# endif +# define machine_is_at91sam9g20ek() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK) +#else +# define machine_is_at91sam9g20ek() (0) +#endif + +#ifdef CONFIG_MACH_STORCENTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STORCENTER +# endif +# define machine_is_sc_ge2() (machine_arch_type == MACH_TYPE_STORCENTER) +#else +# define machine_is_sc_ge2() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6410 +# endif +# define machine_is_smdk6410() (machine_arch_type == MACH_TYPE_SMDK6410) +#else +# define machine_is_smdk6410() (0) +#endif + +#ifdef CONFIG_MACH_U300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U300 +# endif +# define machine_is_u300() (machine_arch_type == MACH_TYPE_U300) +#else +# define machine_is_u300() (0) +#endif + +#ifdef CONFIG_MACH_U500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U500 +# endif +# define machine_is_u500() (machine_arch_type == MACH_TYPE_U500) +#else +# define machine_is_u500() (0) +#endif + +#ifdef CONFIG_MACH_DS9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DS9260 +# endif +# define machine_is_ds9260() (machine_arch_type == MACH_TYPE_DS9260) +#else +# define machine_is_ds9260() (0) +#endif + +#ifdef CONFIG_MACH_RIVERROCK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIVERROCK +# endif +# define machine_is_riverrock() (machine_arch_type == MACH_TYPE_RIVERROCK) +#else +# define machine_is_riverrock() (0) +#endif + +#ifdef CONFIG_MACH_SCIBATH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCIBATH +# endif +# define machine_is_scibath() (machine_arch_type == MACH_TYPE_SCIBATH) +#else +# define machine_is_scibath() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM7SE512EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM7SE512EK +# endif +# define machine_is_at91sam7se() (machine_arch_type == MACH_TYPE_AT91SAM7SE512EK) +#else +# define machine_is_at91sam7se() (0) +#endif + +#ifdef CONFIG_MACH_WRT350N_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WRT350N_V2 +# endif +# define machine_is_wrt350n_v2() (machine_arch_type == MACH_TYPE_WRT350N_V2) +#else +# define machine_is_wrt350n_v2() (0) +#endif + +#ifdef CONFIG_MACH_MULTIMEDIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIMEDIA +# endif +# define machine_is_multimedia() (machine_arch_type == MACH_TYPE_MULTIMEDIA) +#else +# define machine_is_multimedia() (0) +#endif + +#ifdef CONFIG_MACH_MARVIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARVIN +# endif +# define machine_is_marvin() (machine_arch_type == MACH_TYPE_MARVIN) +#else +# define machine_is_marvin() (0) +#endif + +#ifdef CONFIG_MACH_X500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_X500 +# endif +# define machine_is_x500() (machine_arch_type == MACH_TYPE_X500) +#else +# define machine_is_x500() (0) +#endif + +#ifdef CONFIG_MACH_AWLUG4LCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AWLUG4LCU +# endif +# define machine_is_awlug4lcu() (machine_arch_type == MACH_TYPE_AWLUG4LCU) +#else +# define machine_is_awlug4lcu() (0) +#endif + +#ifdef CONFIG_MACH_PALERMOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALERMOC +# endif +# define machine_is_palermoc() (machine_arch_type == MACH_TYPE_PALERMOC) +#else +# define machine_is_palermoc() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_LDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_LDP +# endif +# define machine_is_omap_ldp() (machine_arch_type == MACH_TYPE_OMAP_LDP) +#else +# define machine_is_omap_ldp() (0) +#endif + +#ifdef CONFIG_MACH_IP500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP500 +# endif +# define machine_is_ip500() (machine_arch_type == MACH_TYPE_IP500) +#else +# define machine_is_ip500() (0) +#endif + +#ifdef CONFIG_MACH_ASE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASE2 +# endif +# define machine_is_ase2() (machine_arch_type == MACH_TYPE_ASE2) +#else +# define machine_is_ase2() (0) +#endif + +#ifdef CONFIG_MACH_MX35EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX35EVB +# endif +# define machine_is_mx35evb() (machine_arch_type == MACH_TYPE_MX35EVB) +#else +# define machine_is_mx35evb() (0) +#endif + +#ifdef CONFIG_MACH_AML_M8050 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AML_M8050 +# endif +# define machine_is_aml_m8050() (machine_arch_type == MACH_TYPE_AML_M8050) +#else +# define machine_is_aml_m8050() (0) +#endif + +#ifdef CONFIG_MACH_MX35_3DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX35_3DS +# endif +# define machine_is_mx35_3ds() (machine_arch_type == MACH_TYPE_MX35_3DS) +#else +# define machine_is_mx35_3ds() (0) +#endif + +#ifdef CONFIG_MACH_MARS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARS +# endif +# define machine_is_mars() (machine_arch_type == MACH_TYPE_MARS) +#else +# define machine_is_mars() (0) +#endif + +#ifdef CONFIG_MACH_NEUROS_OSD2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEUROS_OSD2 +# endif +# define machine_is_neuros_osd2() (machine_arch_type == MACH_TYPE_NEUROS_OSD2) +#else +# define machine_is_neuros_osd2() (0) +#endif + +#ifdef CONFIG_MACH_BADGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BADGER +# endif +# define machine_is_badger() (machine_arch_type == MACH_TYPE_BADGER) +#else +# define machine_is_badger() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS4WL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS4WL +# endif +# define machine_is_trizeps4wl() (machine_arch_type == MACH_TYPE_TRIZEPS4WL) +#else +# define machine_is_trizeps4wl() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS5 +# endif +# define machine_is_trizeps5() (machine_arch_type == MACH_TYPE_TRIZEPS5) +#else +# define machine_is_trizeps5() (0) +#endif + +#ifdef CONFIG_MACH_MARLIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARLIN +# endif +# define machine_is_marlin() (machine_arch_type == MACH_TYPE_MARLIN) +#else +# define machine_is_marlin() (0) +#endif + +#ifdef CONFIG_MACH_TS78XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS78XX +# endif +# define machine_is_ts78xx() (machine_arch_type == MACH_TYPE_TS78XX) +#else +# define machine_is_ts78xx() (0) +#endif + +#ifdef CONFIG_MACH_HPIPAQ214 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPIPAQ214 +# endif +# define machine_is_hpipaq214() (machine_arch_type == MACH_TYPE_HPIPAQ214) +#else +# define machine_is_hpipaq214() (0) +#endif + +#ifdef CONFIG_MACH_AT572D940DCM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT572D940DCM +# endif +# define machine_is_at572d940dcm() (machine_arch_type == MACH_TYPE_AT572D940DCM) +#else +# define machine_is_at572d940dcm() (0) +#endif + +#ifdef CONFIG_MACH_NE1BOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NE1BOARD +# endif +# define machine_is_ne1board() (machine_arch_type == MACH_TYPE_NE1BOARD) +#else +# define machine_is_ne1board() (0) +#endif + +#ifdef CONFIG_MACH_ZANTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZANTE +# endif +# define machine_is_zante() (machine_arch_type == MACH_TYPE_ZANTE) +#else +# define machine_is_zante() (0) +#endif + +#ifdef CONFIG_MACH_SFFSDR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SFFSDR +# endif +# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR) +#else +# define machine_is_sffsdr() (0) +#endif + +#ifdef CONFIG_MACH_TW2662 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TW2662 +# endif +# define machine_is_tw2662() (machine_arch_type == MACH_TYPE_TW2662) +#else +# define machine_is_tw2662() (0) +#endif + +#ifdef CONFIG_MACH_VF10XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VF10XX +# endif +# define machine_is_vf10xx() (machine_arch_type == MACH_TYPE_VF10XX) +#else +# define machine_is_vf10xx() (0) +#endif + +#ifdef CONFIG_MACH_ZORAN43XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZORAN43XX +# endif +# define machine_is_zoran43xx() (machine_arch_type == MACH_TYPE_ZORAN43XX) +#else +# define machine_is_zoran43xx() (0) +#endif + +#ifdef CONFIG_MACH_SONIX926 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONIX926 +# endif +# define machine_is_sonix926() (machine_arch_type == MACH_TYPE_SONIX926) +#else +# define machine_is_sonix926() (0) +#endif + +#ifdef CONFIG_MACH_CELESTIALSEMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CELESTIALSEMI +# endif +# define machine_is_celestialsemi() (machine_arch_type == MACH_TYPE_CELESTIALSEMI) +#else +# define machine_is_celestialsemi() (0) +#endif + +#ifdef CONFIG_MACH_CC9M2443JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9M2443JS +# endif +# define machine_is_cc9m2443js() (machine_arch_type == MACH_TYPE_CC9M2443JS) +#else +# define machine_is_cc9m2443js() (0) +#endif + +#ifdef CONFIG_MACH_TW5334 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TW5334 +# endif +# define machine_is_tw5334() (machine_arch_type == MACH_TYPE_TW5334) +#else +# define machine_is_tw5334() (0) +#endif + +#ifdef CONFIG_MACH_HTCARTEMIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCARTEMIS +# endif +# define machine_is_omap_htcartemis() (machine_arch_type == MACH_TYPE_HTCARTEMIS) +#else +# define machine_is_omap_htcartemis() (0) +#endif + +#ifdef CONFIG_MACH_NAL_HLITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAL_HLITE +# endif +# define machine_is_nal_hlite() (machine_arch_type == MACH_TYPE_NAL_HLITE) +#else +# define machine_is_nal_hlite() (0) +#endif + +#ifdef CONFIG_MACH_HTCVOGUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCVOGUE +# endif +# define machine_is_htcvogue() (machine_arch_type == MACH_TYPE_HTCVOGUE) +#else +# define machine_is_htcvogue() (0) +#endif + +#ifdef CONFIG_MACH_SMARTWEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTWEB +# endif +# define machine_is_smartweb() (machine_arch_type == MACH_TYPE_SMARTWEB) +#else +# define machine_is_smartweb() (0) +#endif + +#ifdef CONFIG_MACH_MV86XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV86XX +# endif +# define machine_is_mv86xx() (machine_arch_type == MACH_TYPE_MV86XX) +#else +# define machine_is_mv86xx() (0) +#endif + +#ifdef CONFIG_MACH_MV87XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV87XX +# endif +# define machine_is_mv87xx() (machine_arch_type == MACH_TYPE_MV87XX) +#else +# define machine_is_mv87xx() (0) +#endif + +#ifdef CONFIG_MACH_SONGYOUNGHO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONGYOUNGHO +# endif +# define machine_is_songyoungho() (machine_arch_type == MACH_TYPE_SONGYOUNGHO) +#else +# define machine_is_songyoungho() (0) +#endif + +#ifdef CONFIG_MACH_YOUNGHOTEMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YOUNGHOTEMA +# endif +# define machine_is_younghotema() (machine_arch_type == MACH_TYPE_YOUNGHOTEMA) +#else +# define machine_is_younghotema() (0) +#endif + +#ifdef CONFIG_MACH_PCM037 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM037 +# endif +# define machine_is_pcm037() (machine_arch_type == MACH_TYPE_PCM037) +#else +# define machine_is_pcm037() (0) +#endif + +#ifdef CONFIG_MACH_MMVP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMVP +# endif +# define machine_is_mmvp() (machine_arch_type == MACH_TYPE_MMVP) +#else +# define machine_is_mmvp() (0) +#endif + +#ifdef CONFIG_MACH_MMAP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMAP +# endif +# define machine_is_mmap() (machine_arch_type == MACH_TYPE_MMAP) +#else +# define machine_is_mmap() (0) +#endif + +#ifdef CONFIG_MACH_PTID2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PTID2410 +# endif +# define machine_is_ptid2410() (machine_arch_type == MACH_TYPE_PTID2410) +#else +# define machine_is_ptid2410() (0) +#endif + +#ifdef CONFIG_MACH_JAMES_926 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JAMES_926 +# endif +# define machine_is_james_926() (machine_arch_type == MACH_TYPE_JAMES_926) +#else +# define machine_is_james_926() (0) +#endif + +#ifdef CONFIG_MACH_FM6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FM6000 +# endif +# define machine_is_fm6000() (machine_arch_type == MACH_TYPE_FM6000) +#else +# define machine_is_fm6000() (0) +#endif + +#ifdef CONFIG_MACH_DB88F6281_BP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DB88F6281_BP +# endif +# define machine_is_db88f6281_bp() (machine_arch_type == MACH_TYPE_DB88F6281_BP) +#else +# define machine_is_db88f6281_bp() (0) +#endif + +#ifdef CONFIG_MACH_RD88F6192_NAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F6192_NAS +# endif +# define machine_is_rd88f6192_nas() (machine_arch_type == MACH_TYPE_RD88F6192_NAS) +#else +# define machine_is_rd88f6192_nas() (0) +#endif + +#ifdef CONFIG_MACH_RD88F6281 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F6281 +# endif +# define machine_is_rd88f6281() (machine_arch_type == MACH_TYPE_RD88F6281) +#else +# define machine_is_rd88f6281() (0) +#endif + +#ifdef CONFIG_MACH_DB78X00_BP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DB78X00_BP +# endif +# define machine_is_db78x00_bp() (machine_arch_type == MACH_TYPE_DB78X00_BP) +#else +# define machine_is_db78x00_bp() (0) +#endif + +#ifdef CONFIG_MACH_SMDK2416 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK2416 +# endif +# define machine_is_smdk2416() (machine_arch_type == MACH_TYPE_SMDK2416) +#else +# define machine_is_smdk2416() (0) +#endif + +#ifdef CONFIG_MACH_OCE_SPIDER_SI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCE_SPIDER_SI +# endif +# define machine_is_oce_spider_si() (machine_arch_type == MACH_TYPE_OCE_SPIDER_SI) +#else +# define machine_is_oce_spider_si() (0) +#endif + +#ifdef CONFIG_MACH_OCE_SPIDER_SK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCE_SPIDER_SK +# endif +# define machine_is_oce_spider_sk() (machine_arch_type == MACH_TYPE_OCE_SPIDER_SK) +#else +# define machine_is_oce_spider_sk() (0) +#endif + +#ifdef CONFIG_MACH_ROVERN6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERN6 +# endif +# define machine_is_rovern6() (machine_arch_type == MACH_TYPE_ROVERN6) +#else +# define machine_is_rovern6() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_EVOLUTION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_EVOLUTION +# endif +# define machine_is_pelco_evolution() (machine_arch_type == MACH_TYPE_PELCO_EVOLUTION) +#else +# define machine_is_pelco_evolution() (0) +#endif + +#ifdef CONFIG_MACH_WBD111 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WBD111 +# endif +# define machine_is_wbd111() (machine_arch_type == MACH_TYPE_WBD111) +#else +# define machine_is_wbd111() (0) +#endif + +#ifdef CONFIG_MACH_ELARACPE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELARACPE +# endif +# define machine_is_elaracpe() (machine_arch_type == MACH_TYPE_ELARACPE) +#else +# define machine_is_elaracpe() (0) +#endif + +#ifdef CONFIG_MACH_MABV3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MABV3 +# endif +# define machine_is_mabv3() (machine_arch_type == MACH_TYPE_MABV3) +#else +# define machine_is_mabv3() (0) +#endif + +#ifdef CONFIG_MACH_MV2120 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV2120 +# endif +# define machine_is_mv2120() (machine_arch_type == MACH_TYPE_MV2120) +#else +# define machine_is_mv2120() (0) +#endif + +#ifdef CONFIG_MACH_CSB737 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB737 +# endif +# define machine_is_csb737() (machine_arch_type == MACH_TYPE_CSB737) +#else +# define machine_is_csb737() (0) +#endif + +#ifdef CONFIG_MACH_MX51_3DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_3DS +# endif +# define machine_is_mx51_3ds() (machine_arch_type == MACH_TYPE_MX51_3DS) +#else +# define machine_is_mx51_3ds() (0) +#endif + +#ifdef CONFIG_MACH_G900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G900 +# endif +# define machine_is_g900() (machine_arch_type == MACH_TYPE_G900) +#else +# define machine_is_g900() (0) +#endif + +#ifdef CONFIG_MACH_APF27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APF27 +# endif +# define machine_is_apf27() (machine_arch_type == MACH_TYPE_APF27) +#else +# define machine_is_apf27() (0) +#endif + +#ifdef CONFIG_MACH_GGUS2000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GGUS2000 +# endif +# define machine_is_ggus2000() (machine_arch_type == MACH_TYPE_GGUS2000) +#else +# define machine_is_ggus2000() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_2430_MIMIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_2430_MIMIC +# endif +# define machine_is_omap_2430_mimic() (machine_arch_type == MACH_TYPE_OMAP_2430_MIMIC) +#else +# define machine_is_omap_2430_mimic() (0) +#endif + +#ifdef CONFIG_MACH_IMX27LITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27LITE +# endif +# define machine_is_imx27lite() (machine_arch_type == MACH_TYPE_IMX27LITE) +#else +# define machine_is_imx27lite() (0) +#endif + +#ifdef CONFIG_MACH_ALMEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALMEX +# endif +# define machine_is_almex() (machine_arch_type == MACH_TYPE_ALMEX) +#else +# define machine_is_almex() (0) +#endif + +#ifdef CONFIG_MACH_CONTROL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CONTROL +# endif +# define machine_is_control() (machine_arch_type == MACH_TYPE_CONTROL) +#else +# define machine_is_control() (0) +#endif + +#ifdef CONFIG_MACH_MBA2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MBA2410 +# endif +# define machine_is_mba2410() (machine_arch_type == MACH_TYPE_MBA2410) +#else +# define machine_is_mba2410() (0) +#endif + +#ifdef CONFIG_MACH_VOLCANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VOLCANO +# endif +# define machine_is_volcano() (machine_arch_type == MACH_TYPE_VOLCANO) +#else +# define machine_is_volcano() (0) +#endif + +#ifdef CONFIG_MACH_ZENITH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZENITH +# endif +# define machine_is_zenith() (machine_arch_type == MACH_TYPE_ZENITH) +#else +# define machine_is_zenith() (0) +#endif + +#ifdef CONFIG_MACH_MUCHIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MUCHIP +# endif +# define machine_is_muchip() (machine_arch_type == MACH_TYPE_MUCHIP) +#else +# define machine_is_muchip() (0) +#endif + +#ifdef CONFIG_MACH_MAGELLAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGELLAN +# endif +# define machine_is_magellan() (machine_arch_type == MACH_TYPE_MAGELLAN) +#else +# define machine_is_magellan() (0) +#endif + +#ifdef CONFIG_MACH_USB_A9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USB_A9260 +# endif +# define machine_is_usb_a9260() (machine_arch_type == MACH_TYPE_USB_A9260) +#else +# define machine_is_usb_a9260() (0) +#endif + +#ifdef CONFIG_MACH_USB_A9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USB_A9263 +# endif +# define machine_is_usb_a9263() (machine_arch_type == MACH_TYPE_USB_A9263) +#else +# define machine_is_usb_a9263() (0) +#endif + +#ifdef CONFIG_MACH_QIL_A9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QIL_A9260 +# endif +# define machine_is_qil_a9260() (machine_arch_type == MACH_TYPE_QIL_A9260) +#else +# define machine_is_qil_a9260() (0) +#endif + +#ifdef CONFIG_MACH_CME9210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CME9210 +# endif +# define machine_is_cme9210() (machine_arch_type == MACH_TYPE_CME9210) +#else +# define machine_is_cme9210() (0) +#endif + +#ifdef CONFIG_MACH_HCZH4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HCZH4 +# endif +# define machine_is_hczh4() (machine_arch_type == MACH_TYPE_HCZH4) +#else +# define machine_is_hczh4() (0) +#endif + +#ifdef CONFIG_MACH_SPEARBASIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEARBASIC +# endif +# define machine_is_spearbasic() (machine_arch_type == MACH_TYPE_SPEARBASIC) +#else +# define machine_is_spearbasic() (0) +#endif + +#ifdef CONFIG_MACH_DEP2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEP2440 +# endif +# define machine_is_dep2440() (machine_arch_type == MACH_TYPE_DEP2440) +#else +# define machine_is_dep2440() (0) +#endif + +#ifdef CONFIG_MACH_HDL_GXR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDL_GXR +# endif +# define machine_is_hdl_gxr() (machine_arch_type == MACH_TYPE_HDL_GXR) +#else +# define machine_is_hdl_gxr() (0) +#endif + +#ifdef CONFIG_MACH_HDL_GT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDL_GT +# endif +# define machine_is_hdl_gt() (machine_arch_type == MACH_TYPE_HDL_GT) +#else +# define machine_is_hdl_gt() (0) +#endif + +#ifdef CONFIG_MACH_HDL_4G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDL_4G +# endif +# define machine_is_hdl_4g() (machine_arch_type == MACH_TYPE_HDL_4G) +#else +# define machine_is_hdl_4g() (0) +#endif + +#ifdef CONFIG_MACH_S3C6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C6000 +# endif +# define machine_is_s3c6000() (machine_arch_type == MACH_TYPE_S3C6000) +#else +# define machine_is_s3c6000() (0) +#endif + +#ifdef CONFIG_MACH_MMSP2_MDK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMSP2_MDK +# endif +# define machine_is_mmsp2_mdk() (machine_arch_type == MACH_TYPE_MMSP2_MDK) +#else +# define machine_is_mmsp2_mdk() (0) +#endif + +#ifdef CONFIG_MACH_MPX220 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPX220 +# endif +# define machine_is_mpx220() (machine_arch_type == MACH_TYPE_MPX220) +#else +# define machine_is_mpx220() (0) +#endif + +#ifdef CONFIG_MACH_KZM_ARM11_01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KZM_ARM11_01 +# endif +# define machine_is_kzm_arm11_01() (machine_arch_type == MACH_TYPE_KZM_ARM11_01) +#else +# define machine_is_kzm_arm11_01() (0) +#endif + +#ifdef CONFIG_MACH_HTC_POLARIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_POLARIS +# endif +# define machine_is_htc_polaris() (machine_arch_type == MACH_TYPE_HTC_POLARIS) +#else +# define machine_is_htc_polaris() (0) +#endif + +#ifdef CONFIG_MACH_HTC_KAISER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_KAISER +# endif +# define machine_is_htc_kaiser() (machine_arch_type == MACH_TYPE_HTC_KAISER) +#else +# define machine_is_htc_kaiser() (0) +#endif + +#ifdef CONFIG_MACH_LG_KS20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LG_KS20 +# endif +# define machine_is_lg_ks20() (machine_arch_type == MACH_TYPE_LG_KS20) +#else +# define machine_is_lg_ks20() (0) +#endif + +#ifdef CONFIG_MACH_HHGPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HHGPS +# endif +# define machine_is_hhgps() (machine_arch_type == MACH_TYPE_HHGPS) +#else +# define machine_is_hhgps() (0) +#endif + +#ifdef CONFIG_MACH_NOKIA_N810_WIMAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOKIA_N810_WIMAX +# endif +# define machine_is_nokia_n810_wimax() (machine_arch_type == MACH_TYPE_NOKIA_N810_WIMAX) +#else +# define machine_is_nokia_n810_wimax() (0) +#endif + +#ifdef CONFIG_MACH_INSIGHT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INSIGHT +# endif +# define machine_is_insight() (machine_arch_type == MACH_TYPE_INSIGHT) +#else +# define machine_is_insight() (0) +#endif + +#ifdef CONFIG_MACH_SAPPHIRE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAPPHIRE +# endif +# define machine_is_sapphire() (machine_arch_type == MACH_TYPE_SAPPHIRE) +#else +# define machine_is_sapphire() (0) +#endif + +#ifdef CONFIG_MACH_CSB637XO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB637XO +# endif +# define machine_is_csb637xo() (machine_arch_type == MACH_TYPE_CSB637XO) +#else +# define machine_is_csb637xo() (0) +#endif + +#ifdef CONFIG_MACH_EVISIONG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EVISIONG +# endif +# define machine_is_evisiong() (machine_arch_type == MACH_TYPE_EVISIONG) +#else +# define machine_is_evisiong() (0) +#endif + +#ifdef CONFIG_MACH_STMP37XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STMP37XX +# endif +# define machine_is_stmp37xx() (machine_arch_type == MACH_TYPE_STMP37XX) +#else +# define machine_is_stmp37xx() (0) +#endif + +#ifdef CONFIG_MACH_STMP378X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STMP378X +# endif +# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP378X) +#else +# define machine_is_stmp378x() (0) +#endif + +#ifdef CONFIG_MACH_TNT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNT +# endif +# define machine_is_tnt() (machine_arch_type == MACH_TYPE_TNT) +#else +# define machine_is_tnt() (0) +#endif + +#ifdef CONFIG_MACH_TBXT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TBXT +# endif +# define machine_is_tbxt() (machine_arch_type == MACH_TYPE_TBXT) +#else +# define machine_is_tbxt() (0) +#endif + +#ifdef CONFIG_MACH_PLAYMATE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLAYMATE +# endif +# define machine_is_playmate() (machine_arch_type == MACH_TYPE_PLAYMATE) +#else +# define machine_is_playmate() (0) +#endif + +#ifdef CONFIG_MACH_PNS10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNS10 +# endif +# define machine_is_pns10() (machine_arch_type == MACH_TYPE_PNS10) +#else +# define machine_is_pns10() (0) +#endif + +#ifdef CONFIG_MACH_EZNAVI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZNAVI +# endif +# define machine_is_eznavi() (machine_arch_type == MACH_TYPE_EZNAVI) +#else +# define machine_is_eznavi() (0) +#endif + +#ifdef CONFIG_MACH_PS4000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PS4000 +# endif +# define machine_is_ps4000() (machine_arch_type == MACH_TYPE_PS4000) +#else +# define machine_is_ps4000() (0) +#endif + +#ifdef CONFIG_MACH_EZX_A780 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_A780 +# endif +# define machine_is_ezx_a780() (machine_arch_type == MACH_TYPE_EZX_A780) +#else +# define machine_is_ezx_a780() (0) +#endif + +#ifdef CONFIG_MACH_EZX_E680 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_E680 +# endif +# define machine_is_ezx_e680() (machine_arch_type == MACH_TYPE_EZX_E680) +#else +# define machine_is_ezx_e680() (0) +#endif + +#ifdef CONFIG_MACH_EZX_A1200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_A1200 +# endif +# define machine_is_ezx_a1200() (machine_arch_type == MACH_TYPE_EZX_A1200) +#else +# define machine_is_ezx_a1200() (0) +#endif + +#ifdef CONFIG_MACH_EZX_E6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_E6 +# endif +# define machine_is_ezx_e6() (machine_arch_type == MACH_TYPE_EZX_E6) +#else +# define machine_is_ezx_e6() (0) +#endif + +#ifdef CONFIG_MACH_EZX_E2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_E2 +# endif +# define machine_is_ezx_e2() (machine_arch_type == MACH_TYPE_EZX_E2) +#else +# define machine_is_ezx_e2() (0) +#endif + +#ifdef CONFIG_MACH_EZX_A910 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX_A910 +# endif +# define machine_is_ezx_a910() (machine_arch_type == MACH_TYPE_EZX_A910) +#else +# define machine_is_ezx_a910() (0) +#endif + +#ifdef CONFIG_MACH_CWMX31 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWMX31 +# endif +# define machine_is_cwmx31() (machine_arch_type == MACH_TYPE_CWMX31) +#else +# define machine_is_cwmx31() (0) +#endif + +#ifdef CONFIG_MACH_SL2312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SL2312 +# endif +# define machine_is_sl2312() (machine_arch_type == MACH_TYPE_SL2312) +#else +# define machine_is_sl2312() (0) +#endif + +#ifdef CONFIG_MACH_BLENNY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLENNY +# endif +# define machine_is_blenny() (machine_arch_type == MACH_TYPE_BLENNY) +#else +# define machine_is_blenny() (0) +#endif + +#ifdef CONFIG_MACH_DS107 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DS107 +# endif +# define machine_is_ds107() (machine_arch_type == MACH_TYPE_DS107) +#else +# define machine_is_ds107() (0) +#endif + +#ifdef CONFIG_MACH_DSX07 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSX07 +# endif +# define machine_is_dsx07() (machine_arch_type == MACH_TYPE_DSX07) +#else +# define machine_is_dsx07() (0) +#endif + +#ifdef CONFIG_MACH_PICOCOM1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOCOM1 +# endif +# define machine_is_picocom1() (machine_arch_type == MACH_TYPE_PICOCOM1) +#else +# define machine_is_picocom1() (0) +#endif + +#ifdef CONFIG_MACH_LYNX_WOLVERINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LYNX_WOLVERINE +# endif +# define machine_is_lynx_wolverine() (machine_arch_type == MACH_TYPE_LYNX_WOLVERINE) +#else +# define machine_is_lynx_wolverine() (0) +#endif + +#ifdef CONFIG_MACH_UBISYS_P9_SC19 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UBISYS_P9_SC19 +# endif +# define machine_is_ubisys_p9_sc19() (machine_arch_type == MACH_TYPE_UBISYS_P9_SC19) +#else +# define machine_is_ubisys_p9_sc19() (0) +#endif + +#ifdef CONFIG_MACH_KRATOS_LOW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KRATOS_LOW +# endif +# define machine_is_kratos_low() (machine_arch_type == MACH_TYPE_KRATOS_LOW) +#else +# define machine_is_kratos_low() (0) +#endif + +#ifdef CONFIG_MACH_M700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M700 +# endif +# define machine_is_m700() (machine_arch_type == MACH_TYPE_M700) +#else +# define machine_is_m700() (0) +#endif + +#ifdef CONFIG_MACH_EDMINI_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDMINI_V2 +# endif +# define machine_is_edmini_v2() (machine_arch_type == MACH_TYPE_EDMINI_V2) +#else +# define machine_is_edmini_v2() (0) +#endif + +#ifdef CONFIG_MACH_ZIPIT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZIPIT2 +# endif +# define machine_is_zipit2() (machine_arch_type == MACH_TYPE_ZIPIT2) +#else +# define machine_is_zipit2() (0) +#endif + +#ifdef CONFIG_MACH_HSLFEMTOCELL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HSLFEMTOCELL +# endif +# define machine_is_hslfemtocell() (machine_arch_type == MACH_TYPE_HSLFEMTOCELL) +#else +# define machine_is_hslfemtocell() (0) +#endif + +#ifdef CONFIG_MACH_DAINTREE_AT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAINTREE_AT91 +# endif +# define machine_is_daintree_at91() (machine_arch_type == MACH_TYPE_DAINTREE_AT91) +#else +# define machine_is_daintree_at91() (0) +#endif + +#ifdef CONFIG_MACH_SG560USB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG560USB +# endif +# define machine_is_sg560usb() (machine_arch_type == MACH_TYPE_SG560USB) +#else +# define machine_is_sg560usb() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_PANDORA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PANDORA +# endif +# define machine_is_omap3_pandora() (machine_arch_type == MACH_TYPE_OMAP3_PANDORA) +#else +# define machine_is_omap3_pandora() (0) +#endif + +#ifdef CONFIG_MACH_USR8200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USR8200 +# endif +# define machine_is_usr8200() (machine_arch_type == MACH_TYPE_USR8200) +#else +# define machine_is_usr8200() (0) +#endif + +#ifdef CONFIG_MACH_S1S65K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S1S65K +# endif +# define machine_is_s1s65k() (machine_arch_type == MACH_TYPE_S1S65K) +#else +# define machine_is_s1s65k() (0) +#endif + +#ifdef CONFIG_MACH_S2S65A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S2S65A +# endif +# define machine_is_s2s65a() (machine_arch_type == MACH_TYPE_S2S65A) +#else +# define machine_is_s2s65a() (0) +#endif + +#ifdef CONFIG_MACH_ICORE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICORE +# endif +# define machine_is_icore() (machine_arch_type == MACH_TYPE_ICORE) +#else +# define machine_is_icore() (0) +#endif + +#ifdef CONFIG_MACH_MSS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSS2 +# endif +# define machine_is_mss2() (machine_arch_type == MACH_TYPE_MSS2) +#else +# define machine_is_mss2() (0) +#endif + +#ifdef CONFIG_MACH_BELMONT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BELMONT +# endif +# define machine_is_belmont() (machine_arch_type == MACH_TYPE_BELMONT) +#else +# define machine_is_belmont() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP525 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP525 +# endif +# define machine_is_asusp525() (machine_arch_type == MACH_TYPE_ASUSP525) +#else +# define machine_is_asusp525() (0) +#endif + +#ifdef CONFIG_MACH_LB88RC8480 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LB88RC8480 +# endif +# define machine_is_lb88rc8480() (machine_arch_type == MACH_TYPE_LB88RC8480) +#else +# define machine_is_lb88rc8480() (0) +#endif + +#ifdef CONFIG_MACH_HIPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIPXA +# endif +# define machine_is_hipxa() (machine_arch_type == MACH_TYPE_HIPXA) +#else +# define machine_is_hipxa() (0) +#endif + +#ifdef CONFIG_MACH_MX25_3DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX25_3DS +# endif +# define machine_is_mx25_3ds() (machine_arch_type == MACH_TYPE_MX25_3DS) +#else +# define machine_is_mx25_3ds() (0) +#endif + +#ifdef CONFIG_MACH_M800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M800 +# endif +# define machine_is_m800() (machine_arch_type == MACH_TYPE_M800) +#else +# define machine_is_m800() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3530_LV_SOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3530_LV_SOM +# endif +# define machine_is_omap3530_lv_som() (machine_arch_type == MACH_TYPE_OMAP3530_LV_SOM) +#else +# define machine_is_omap3530_lv_som() (0) +#endif + +#ifdef CONFIG_MACH_PRIMA_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRIMA_EVB +# endif +# define machine_is_prima_evb() (machine_arch_type == MACH_TYPE_PRIMA_EVB) +#else +# define machine_is_prima_evb() (0) +#endif + +#ifdef CONFIG_MACH_MX31BT1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31BT1 +# endif +# define machine_is_mx31bt1() (machine_arch_type == MACH_TYPE_MX31BT1) +#else +# define machine_is_mx31bt1() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS4_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS4_EVB +# endif +# define machine_is_atlas4_evb() (machine_arch_type == MACH_TYPE_ATLAS4_EVB) +#else +# define machine_is_atlas4_evb() (0) +#endif + +#ifdef CONFIG_MACH_MX31CICADA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31CICADA +# endif +# define machine_is_mx31cicada() (machine_arch_type == MACH_TYPE_MX31CICADA) +#else +# define machine_is_mx31cicada() (0) +#endif + +#ifdef CONFIG_MACH_MI424WR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MI424WR +# endif +# define machine_is_mi424wr() (machine_arch_type == MACH_TYPE_MI424WR) +#else +# define machine_is_mi424wr() (0) +#endif + +#ifdef CONFIG_MACH_AXS_ULTRAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXS_ULTRAX +# endif +# define machine_is_axs_ultrax() (machine_arch_type == MACH_TYPE_AXS_ULTRAX) +#else +# define machine_is_axs_ultrax() (0) +#endif + +#ifdef CONFIG_MACH_AT572D940DEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT572D940DEB +# endif +# define machine_is_at572d940deb() (machine_arch_type == MACH_TYPE_AT572D940DEB) +#else +# define machine_is_at572d940deb() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DA830_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DA830_EVM +# endif +# define machine_is_davinci_da830_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM) +#else +# define machine_is_davinci_da830_evm() (0) +#endif + +#ifdef CONFIG_MACH_EP9302 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EP9302 +# endif +# define machine_is_ep9302() (machine_arch_type == MACH_TYPE_EP9302) +#else +# define machine_is_ep9302() (0) +#endif + +#ifdef CONFIG_MACH_AT572D940HFEB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT572D940HFEB +# endif +# define machine_is_at572d940hfek() (machine_arch_type == MACH_TYPE_AT572D940HFEB) +#else +# define machine_is_at572d940hfek() (0) +#endif + +#ifdef CONFIG_MACH_CYBOOK3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBOOK3 +# endif +# define machine_is_cybook3() (machine_arch_type == MACH_TYPE_CYBOOK3) +#else +# define machine_is_cybook3() (0) +#endif + +#ifdef CONFIG_MACH_WDG002 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WDG002 +# endif +# define machine_is_wdg002() (machine_arch_type == MACH_TYPE_WDG002) +#else +# define machine_is_wdg002() (0) +#endif + +#ifdef CONFIG_MACH_SG560ADSL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SG560ADSL +# endif +# define machine_is_sg560adsl() (machine_arch_type == MACH_TYPE_SG560ADSL) +#else +# define machine_is_sg560adsl() (0) +#endif + +#ifdef CONFIG_MACH_NEXTIO_N2800_ICA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEXTIO_N2800_ICA +# endif +# define machine_is_nextio_n2800_ica() (machine_arch_type == MACH_TYPE_NEXTIO_N2800_ICA) +#else +# define machine_is_nextio_n2800_ica() (0) +#endif + +#ifdef CONFIG_MACH_DOVE_DB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOVE_DB +# endif +# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_DOVE_DB) +#else +# define machine_is_dove_db() (0) +#endif + +#ifdef CONFIG_MACH_MARVELL_NEWDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARVELL_NEWDB +# endif +# define machine_is_dove_avng() (machine_arch_type == MACH_TYPE_MARVELL_NEWDB) +#else +# define machine_is_dove_avng() (0) +#endif + +#ifdef CONFIG_MACH_VANDIHUD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VANDIHUD +# endif +# define machine_is_vandihud() (machine_arch_type == MACH_TYPE_VANDIHUD) +#else +# define machine_is_vandihud() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_E8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_E8 +# endif +# define machine_is_magx_e8() (machine_arch_type == MACH_TYPE_MAGX_E8) +#else +# define machine_is_magx_e8() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_Z6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_Z6 +# endif +# define machine_is_magx_z6() (machine_arch_type == MACH_TYPE_MAGX_Z6) +#else +# define machine_is_magx_z6() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_V8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_V8 +# endif +# define machine_is_magx_v8() (machine_arch_type == MACH_TYPE_MAGX_V8) +#else +# define machine_is_magx_v8() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_U9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_U9 +# endif +# define machine_is_magx_u9() (machine_arch_type == MACH_TYPE_MAGX_U9) +#else +# define machine_is_magx_u9() (0) +#endif + +#ifdef CONFIG_MACH_TOUGHCF08 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOUGHCF08 +# endif +# define machine_is_toughcf08() (machine_arch_type == MACH_TYPE_TOUGHCF08) +#else +# define machine_is_toughcf08() (0) +#endif + +#ifdef CONFIG_MACH_ZW4400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZW4400 +# endif +# define machine_is_zw4400() (machine_arch_type == MACH_TYPE_ZW4400) +#else +# define machine_is_zw4400() (0) +#endif + +#ifdef CONFIG_MACH_MARAT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARAT91 +# endif +# define machine_is_marat91() (machine_arch_type == MACH_TYPE_MARAT91) +#else +# define machine_is_marat91() (0) +#endif + +#ifdef CONFIG_MACH_OVERO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OVERO +# endif +# define machine_is_overo() (machine_arch_type == MACH_TYPE_OVERO) +#else +# define machine_is_overo() (0) +#endif + +#ifdef CONFIG_MACH_AT2440EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT2440EVB +# endif +# define machine_is_at2440evb() (machine_arch_type == MACH_TYPE_AT2440EVB) +#else +# define machine_is_at2440evb() (0) +#endif + +#ifdef CONFIG_MACH_NEOCORE926 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEOCORE926 +# endif +# define machine_is_neocore926() (machine_arch_type == MACH_TYPE_NEOCORE926) +#else +# define machine_is_neocore926() (0) +#endif + +#ifdef CONFIG_MACH_WNR854T +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WNR854T +# endif +# define machine_is_wnr854t() (machine_arch_type == MACH_TYPE_WNR854T) +#else +# define machine_is_wnr854t() (0) +#endif + +#ifdef CONFIG_MACH_IMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27 +# endif +# define machine_is_imx27() (machine_arch_type == MACH_TYPE_IMX27) +#else +# define machine_is_imx27() (0) +#endif + +#ifdef CONFIG_MACH_MOOSE_DB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOOSE_DB +# endif +# define machine_is_moose_db() (machine_arch_type == MACH_TYPE_MOOSE_DB) +#else +# define machine_is_moose_db() (0) +#endif + +#ifdef CONFIG_MACH_FAB4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FAB4 +# endif +# define machine_is_fab4() (machine_arch_type == MACH_TYPE_FAB4) +#else +# define machine_is_fab4() (0) +#endif + +#ifdef CONFIG_MACH_HTCDIAMOND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCDIAMOND +# endif +# define machine_is_htcdiamond() (machine_arch_type == MACH_TYPE_HTCDIAMOND) +#else +# define machine_is_htcdiamond() (0) +#endif + +#ifdef CONFIG_MACH_FIONA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FIONA +# endif +# define machine_is_fiona() (machine_arch_type == MACH_TYPE_FIONA) +#else +# define machine_is_fiona() (0) +#endif + +#ifdef CONFIG_MACH_MXC30030_X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC30030_X +# endif +# define machine_is_mxc30030_x() (machine_arch_type == MACH_TYPE_MXC30030_X) +#else +# define machine_is_mxc30030_x() (0) +#endif + +#ifdef CONFIG_MACH_BMP1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BMP1000 +# endif +# define machine_is_bmp1000() (machine_arch_type == MACH_TYPE_BMP1000) +#else +# define machine_is_bmp1000() (0) +#endif + +#ifdef CONFIG_MACH_LOGI9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOGI9200 +# endif +# define machine_is_logi9200() (machine_arch_type == MACH_TYPE_LOGI9200) +#else +# define machine_is_logi9200() (0) +#endif + +#ifdef CONFIG_MACH_TQMA31 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TQMA31 +# endif +# define machine_is_tqma31() (machine_arch_type == MACH_TYPE_TQMA31) +#else +# define machine_is_tqma31() (0) +#endif + +#ifdef CONFIG_MACH_CCW9P9215JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9P9215JS +# endif +# define machine_is_ccw9p9215js() (machine_arch_type == MACH_TYPE_CCW9P9215JS) +#else +# define machine_is_ccw9p9215js() (0) +#endif + +#ifdef CONFIG_MACH_RD88F5181L_GE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F5181L_GE +# endif +# define machine_is_rd88f5181l_ge() (machine_arch_type == MACH_TYPE_RD88F5181L_GE) +#else +# define machine_is_rd88f5181l_ge() (0) +#endif + +#ifdef CONFIG_MACH_SIFMAIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIFMAIN +# endif +# define machine_is_sifmain() (machine_arch_type == MACH_TYPE_SIFMAIN) +#else +# define machine_is_sifmain() (0) +#endif + +#ifdef CONFIG_MACH_SAM9_L9261 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAM9_L9261 +# endif +# define machine_is_sam9_l9261() (machine_arch_type == MACH_TYPE_SAM9_L9261) +#else +# define machine_is_sam9_l9261() (0) +#endif + +#ifdef CONFIG_MACH_CC9M2443 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9M2443 +# endif +# define machine_is_cc9m2443() (machine_arch_type == MACH_TYPE_CC9M2443) +#else +# define machine_is_cc9m2443() (0) +#endif + +#ifdef CONFIG_MACH_XARIA300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XARIA300 +# endif +# define machine_is_xaria300() (machine_arch_type == MACH_TYPE_XARIA300) +#else +# define machine_is_xaria300() (0) +#endif + +#ifdef CONFIG_MACH_IT9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IT9200 +# endif +# define machine_is_it9200() (machine_arch_type == MACH_TYPE_IT9200) +#else +# define machine_is_it9200() (0) +#endif + +#ifdef CONFIG_MACH_RD88F5181L_FXO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F5181L_FXO +# endif +# define machine_is_rd88f5181l_fxo() (machine_arch_type == MACH_TYPE_RD88F5181L_FXO) +#else +# define machine_is_rd88f5181l_fxo() (0) +#endif + +#ifdef CONFIG_MACH_KRISS_SENSOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KRISS_SENSOR +# endif +# define machine_is_kriss_sensor() (machine_arch_type == MACH_TYPE_KRISS_SENSOR) +#else +# define machine_is_kriss_sensor() (0) +#endif + +#ifdef CONFIG_MACH_PILZ_PMI5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PILZ_PMI5 +# endif +# define machine_is_pilz_pmi5() (machine_arch_type == MACH_TYPE_PILZ_PMI5) +#else +# define machine_is_pilz_pmi5() (0) +#endif + +#ifdef CONFIG_MACH_JADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JADE +# endif +# define machine_is_jade() (machine_arch_type == MACH_TYPE_JADE) +#else +# define machine_is_jade() (0) +#endif + +#ifdef CONFIG_MACH_KS8695_SOFTPLC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KS8695_SOFTPLC +# endif +# define machine_is_ks8695_softplc() (machine_arch_type == MACH_TYPE_KS8695_SOFTPLC) +#else +# define machine_is_ks8695_softplc() (0) +#endif + +#ifdef CONFIG_MACH_GPRISC3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GPRISC3 +# endif +# define machine_is_gprisc3() (machine_arch_type == MACH_TYPE_GPRISC3) +#else +# define machine_is_gprisc3() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9G20 +# endif +# define machine_is_stamp9g20() (machine_arch_type == MACH_TYPE_STAMP9G20) +#else +# define machine_is_stamp9g20() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6430 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6430 +# endif +# define machine_is_smdk6430() (machine_arch_type == MACH_TYPE_SMDK6430) +#else +# define machine_is_smdk6430() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC100 +# endif +# define machine_is_smdkc100() (machine_arch_type == MACH_TYPE_SMDKC100) +#else +# define machine_is_smdkc100() (0) +#endif + +#ifdef CONFIG_MACH_TAVOREVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAVOREVB +# endif +# define machine_is_tavorevb() (machine_arch_type == MACH_TYPE_TAVOREVB) +#else +# define machine_is_tavorevb() (0) +#endif + +#ifdef CONFIG_MACH_SAAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAAR +# endif +# define machine_is_saar() (machine_arch_type == MACH_TYPE_SAAR) +#else +# define machine_is_saar() (0) +#endif + +#ifdef CONFIG_MACH_DEISTER_EYECAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEISTER_EYECAM +# endif +# define machine_is_deister_eyecam() (machine_arch_type == MACH_TYPE_DEISTER_EYECAM) +#else +# define machine_is_deister_eyecam() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9M10G45EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9M10G45EK +# endif +# define machine_is_at91sam9m10g45ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK) +#else +# define machine_is_at91sam9m10g45ek() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_PRODUO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_PRODUO +# endif +# define machine_is_linkstation_produo() (machine_arch_type == MACH_TYPE_LINKSTATION_PRODUO) +#else +# define machine_is_linkstation_produo() (0) +#endif + +#ifdef CONFIG_MACH_HIT_B0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIT_B0 +# endif +# define machine_is_hit_b0() (machine_arch_type == MACH_TYPE_HIT_B0) +#else +# define machine_is_hit_b0() (0) +#endif + +#ifdef CONFIG_MACH_ADX_RMU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADX_RMU +# endif +# define machine_is_adx_rmu() (machine_arch_type == MACH_TYPE_ADX_RMU) +#else +# define machine_is_adx_rmu() (0) +#endif + +#ifdef CONFIG_MACH_XG_CPE_MAIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XG_CPE_MAIN +# endif +# define machine_is_xg_cpe_main() (machine_arch_type == MACH_TYPE_XG_CPE_MAIN) +#else +# define machine_is_xg_cpe_main() (0) +#endif + +#ifdef CONFIG_MACH_EDB9407A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9407A +# endif +# define machine_is_edb9407a() (machine_arch_type == MACH_TYPE_EDB9407A) +#else +# define machine_is_edb9407a() (0) +#endif + +#ifdef CONFIG_MACH_DTB9608 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DTB9608 +# endif +# define machine_is_dtb9608() (machine_arch_type == MACH_TYPE_DTB9608) +#else +# define machine_is_dtb9608() (0) +#endif + +#ifdef CONFIG_MACH_EM104V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EM104V1 +# endif +# define machine_is_em104v1() (machine_arch_type == MACH_TYPE_EM104V1) +#else +# define machine_is_em104v1() (0) +#endif + +#ifdef CONFIG_MACH_DEMO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEMO +# endif +# define machine_is_demo() (machine_arch_type == MACH_TYPE_DEMO) +#else +# define machine_is_demo() (0) +#endif + +#ifdef CONFIG_MACH_LOGI9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOGI9260 +# endif +# define machine_is_logi9260() (machine_arch_type == MACH_TYPE_LOGI9260) +#else +# define machine_is_logi9260() (0) +#endif + +#ifdef CONFIG_MACH_MX31_EXM32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31_EXM32 +# endif +# define machine_is_mx31_exm32() (machine_arch_type == MACH_TYPE_MX31_EXM32) +#else +# define machine_is_mx31_exm32() (0) +#endif + +#ifdef CONFIG_MACH_USB_A9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USB_A9G20 +# endif +# define machine_is_usb_a9g20() (machine_arch_type == MACH_TYPE_USB_A9G20) +#else +# define machine_is_usb_a9g20() (0) +#endif + +#ifdef CONFIG_MACH_PICPROJE2008 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICPROJE2008 +# endif +# define machine_is_picproje2008() (machine_arch_type == MACH_TYPE_PICPROJE2008) +#else +# define machine_is_picproje2008() (0) +#endif + +#ifdef CONFIG_MACH_CS_E9315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CS_E9315 +# endif +# define machine_is_cs_e9315() (machine_arch_type == MACH_TYPE_CS_E9315) +#else +# define machine_is_cs_e9315() (0) +#endif + +#ifdef CONFIG_MACH_QIL_A9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QIL_A9G20 +# endif +# define machine_is_qil_a9g20() (machine_arch_type == MACH_TYPE_QIL_A9G20) +#else +# define machine_is_qil_a9g20() (0) +#endif + +#ifdef CONFIG_MACH_SHA_PON020 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHA_PON020 +# endif +# define machine_is_sha_pon020() (machine_arch_type == MACH_TYPE_SHA_PON020) +#else +# define machine_is_sha_pon020() (0) +#endif + +#ifdef CONFIG_MACH_NAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAD +# endif +# define machine_is_nad() (machine_arch_type == MACH_TYPE_NAD) +#else +# define machine_is_nad() (0) +#endif + +#ifdef CONFIG_MACH_SBC35_A9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC35_A9260 +# endif +# define machine_is_sbc35_a9260() (machine_arch_type == MACH_TYPE_SBC35_A9260) +#else +# define machine_is_sbc35_a9260() (0) +#endif + +#ifdef CONFIG_MACH_SBC35_A9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC35_A9G20 +# endif +# define machine_is_sbc35_a9g20() (machine_arch_type == MACH_TYPE_SBC35_A9G20) +#else +# define machine_is_sbc35_a9g20() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_BEGINNING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_BEGINNING +# endif +# define machine_is_davinci_beginning() (machine_arch_type == MACH_TYPE_DAVINCI_BEGINNING) +#else +# define machine_is_davinci_beginning() (0) +#endif + +#ifdef CONFIG_MACH_UWC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UWC +# endif +# define machine_is_uwc() (machine_arch_type == MACH_TYPE_UWC) +#else +# define machine_is_uwc() (0) +#endif + +#ifdef CONFIG_MACH_MXLADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXLADS +# endif +# define machine_is_mxlads() (machine_arch_type == MACH_TYPE_MXLADS) +#else +# define machine_is_mxlads() (0) +#endif + +#ifdef CONFIG_MACH_HTCNIKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCNIKE +# endif +# define machine_is_htcnike() (machine_arch_type == MACH_TYPE_HTCNIKE) +#else +# define machine_is_htcnike() (0) +#endif + +#ifdef CONFIG_MACH_DEISTER_PXA270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEISTER_PXA270 +# endif +# define machine_is_deister_pxa270() (machine_arch_type == MACH_TYPE_DEISTER_PXA270) +#else +# define machine_is_deister_pxa270() (0) +#endif + +#ifdef CONFIG_MACH_CME9210JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CME9210JS +# endif +# define machine_is_cme9210js() (machine_arch_type == MACH_TYPE_CME9210JS) +#else +# define machine_is_cme9210js() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9360 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9360 +# endif +# define machine_is_cc9p9360() (machine_arch_type == MACH_TYPE_CC9P9360) +#else +# define machine_is_cc9p9360() (0) +#endif + +#ifdef CONFIG_MACH_MOCHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOCHA +# endif +# define machine_is_mocha() (machine_arch_type == MACH_TYPE_MOCHA) +#else +# define machine_is_mocha() (0) +#endif + +#ifdef CONFIG_MACH_WAPD170AG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WAPD170AG +# endif +# define machine_is_wapd170ag() (machine_arch_type == MACH_TYPE_WAPD170AG) +#else +# define machine_is_wapd170ag() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_MINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_MINI +# endif +# define machine_is_linkstation_mini() (machine_arch_type == MACH_TYPE_LINKSTATION_MINI) +#else +# define machine_is_linkstation_mini() (0) +#endif + +#ifdef CONFIG_MACH_AFEB9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AFEB9260 +# endif +# define machine_is_afeb9260() (machine_arch_type == MACH_TYPE_AFEB9260) +#else +# define machine_is_afeb9260() (0) +#endif + +#ifdef CONFIG_MACH_W90X900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90X900 +# endif +# define machine_is_w90x900() (machine_arch_type == MACH_TYPE_W90X900) +#else +# define machine_is_w90x900() (0) +#endif + +#ifdef CONFIG_MACH_W90X700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90X700 +# endif +# define machine_is_w90x700() (machine_arch_type == MACH_TYPE_W90X700) +#else +# define machine_is_w90x700() (0) +#endif + +#ifdef CONFIG_MACH_KT300IP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KT300IP +# endif +# define machine_is_kt300ip() (machine_arch_type == MACH_TYPE_KT300IP) +#else +# define machine_is_kt300ip() (0) +#endif + +#ifdef CONFIG_MACH_KT300IP_G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KT300IP_G20 +# endif +# define machine_is_kt300ip_g20() (machine_arch_type == MACH_TYPE_KT300IP_G20) +#else +# define machine_is_kt300ip_g20() (0) +#endif + +#ifdef CONFIG_MACH_SRCM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SRCM +# endif +# define machine_is_srcm() (machine_arch_type == MACH_TYPE_SRCM) +#else +# define machine_is_srcm() (0) +#endif + +#ifdef CONFIG_MACH_WLNX_9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WLNX_9260 +# endif +# define machine_is_wlnx_9260() (machine_arch_type == MACH_TYPE_WLNX_9260) +#else +# define machine_is_wlnx_9260() (0) +#endif + +#ifdef CONFIG_MACH_OPENMOKO_GTA03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENMOKO_GTA03 +# endif +# define machine_is_openmoko_gta03() (machine_arch_type == MACH_TYPE_OPENMOKO_GTA03) +#else +# define machine_is_openmoko_gta03() (0) +#endif + +#ifdef CONFIG_MACH_OSPREY2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OSPREY2 +# endif +# define machine_is_osprey2() (machine_arch_type == MACH_TYPE_OSPREY2) +#else +# define machine_is_osprey2() (0) +#endif + +#ifdef CONFIG_MACH_KBIO9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KBIO9260 +# endif +# define machine_is_kbio9260() (machine_arch_type == MACH_TYPE_KBIO9260) +#else +# define machine_is_kbio9260() (0) +#endif + +#ifdef CONFIG_MACH_GINZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GINZA +# endif +# define machine_is_ginza() (machine_arch_type == MACH_TYPE_GINZA) +#else +# define machine_is_ginza() (0) +#endif + +#ifdef CONFIG_MACH_A636N +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A636N +# endif +# define machine_is_a636n() (machine_arch_type == MACH_TYPE_A636N) +#else +# define machine_is_a636n() (0) +#endif + +#ifdef CONFIG_MACH_IMX27IPCAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27IPCAM +# endif +# define machine_is_imx27ipcam() (machine_arch_type == MACH_TYPE_IMX27IPCAM) +#else +# define machine_is_imx27ipcam() (0) +#endif + +#ifdef CONFIG_MACH_NEMOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEMOC +# endif +# define machine_is_nemoc() (machine_arch_type == MACH_TYPE_NEMOC) +#else +# define machine_is_nemoc() (0) +#endif + +#ifdef CONFIG_MACH_GENEVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GENEVA +# endif +# define machine_is_geneva() (machine_arch_type == MACH_TYPE_GENEVA) +#else +# define machine_is_geneva() (0) +#endif + +#ifdef CONFIG_MACH_HTCPHAROS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPHAROS +# endif +# define machine_is_htcpharos() (machine_arch_type == MACH_TYPE_HTCPHAROS) +#else +# define machine_is_htcpharos() (0) +#endif + +#ifdef CONFIG_MACH_NEONC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEONC +# endif +# define machine_is_neonc() (machine_arch_type == MACH_TYPE_NEONC) +#else +# define machine_is_neonc() (0) +#endif + +#ifdef CONFIG_MACH_NAS7100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAS7100 +# endif +# define machine_is_nas7100() (machine_arch_type == MACH_TYPE_NAS7100) +#else +# define machine_is_nas7100() (0) +#endif + +#ifdef CONFIG_MACH_TEUPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEUPHONE +# endif +# define machine_is_teuphone() (machine_arch_type == MACH_TYPE_TEUPHONE) +#else +# define machine_is_teuphone() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_ETH2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_ETH2 +# endif +# define machine_is_annax_eth2() (machine_arch_type == MACH_TYPE_ANNAX_ETH2) +#else +# define machine_is_annax_eth2() (0) +#endif + +#ifdef CONFIG_MACH_CSB733 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB733 +# endif +# define machine_is_csb733() (machine_arch_type == MACH_TYPE_CSB733) +#else +# define machine_is_csb733() (0) +#endif + +#ifdef CONFIG_MACH_BK3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BK3 +# endif +# define machine_is_bk3() (machine_arch_type == MACH_TYPE_BK3) +#else +# define machine_is_bk3() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_EM32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_EM32 +# endif +# define machine_is_omap_em32() (machine_arch_type == MACH_TYPE_OMAP_EM32) +#else +# define machine_is_omap_em32() (0) +#endif + +#ifdef CONFIG_MACH_ET9261CP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ET9261CP +# endif +# define machine_is_et9261cp() (machine_arch_type == MACH_TYPE_ET9261CP) +#else +# define machine_is_et9261cp() (0) +#endif + +#ifdef CONFIG_MACH_JASPERC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JASPERC +# endif +# define machine_is_jasperc() (machine_arch_type == MACH_TYPE_JASPERC) +#else +# define machine_is_jasperc() (0) +#endif + +#ifdef CONFIG_MACH_ISSI_ARM9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ISSI_ARM9 +# endif +# define machine_is_issi_arm9() (machine_arch_type == MACH_TYPE_ISSI_ARM9) +#else +# define machine_is_issi_arm9() (0) +#endif + +#ifdef CONFIG_MACH_UED +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UED +# endif +# define machine_is_ued() (machine_arch_type == MACH_TYPE_UED) +#else +# define machine_is_ued() (0) +#endif + +#ifdef CONFIG_MACH_ESIBLADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESIBLADE +# endif +# define machine_is_esiblade() (machine_arch_type == MACH_TYPE_ESIBLADE) +#else +# define machine_is_esiblade() (0) +#endif + +#ifdef CONFIG_MACH_EYE02 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EYE02 +# endif +# define machine_is_eye02() (machine_arch_type == MACH_TYPE_EYE02) +#else +# define machine_is_eye02() (0) +#endif + +#ifdef CONFIG_MACH_IMX27KBD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27KBD +# endif +# define machine_is_imx27kbd() (machine_arch_type == MACH_TYPE_IMX27KBD) +#else +# define machine_is_imx27kbd() (0) +#endif + +#ifdef CONFIG_MACH_SST61VC010_FPGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SST61VC010_FPGA +# endif +# define machine_is_p87_fpga() (machine_arch_type == MACH_TYPE_SST61VC010_FPGA) +#else +# define machine_is_p87_fpga() (0) +#endif + +#ifdef CONFIG_MACH_KIXVP435 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIXVP435 +# endif +# define machine_is_kixvp435() (machine_arch_type == MACH_TYPE_KIXVP435) +#else +# define machine_is_kixvp435() (0) +#endif + +#ifdef CONFIG_MACH_KIXNP435 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIXNP435 +# endif +# define machine_is_kixnp435() (machine_arch_type == MACH_TYPE_KIXNP435) +#else +# define machine_is_kixnp435() (0) +#endif + +#ifdef CONFIG_MACH_AFRICA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AFRICA +# endif +# define machine_is_africa() (machine_arch_type == MACH_TYPE_AFRICA) +#else +# define machine_is_africa() (0) +#endif + +#ifdef CONFIG_MACH_NH233 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NH233 +# endif +# define machine_is_nh233() (machine_arch_type == MACH_TYPE_NH233) +#else +# define machine_is_nh233() (0) +#endif + +#ifdef CONFIG_MACH_RD88F6183AP_GE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F6183AP_GE +# endif +# define machine_is_rd88f6183ap_ge() (machine_arch_type == MACH_TYPE_RD88F6183AP_GE) +#else +# define machine_is_rd88f6183ap_ge() (0) +#endif + +#ifdef CONFIG_MACH_BCM4760 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM4760 +# endif +# define machine_is_bcm4760() (machine_arch_type == MACH_TYPE_BCM4760) +#else +# define machine_is_bcm4760() (0) +#endif + +#ifdef CONFIG_MACH_EDDY_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDDY_V2 +# endif +# define machine_is_eddy_v2() (machine_arch_type == MACH_TYPE_EDDY_V2) +#else +# define machine_is_eddy_v2() (0) +#endif + +#ifdef CONFIG_MACH_REALVIEW_PBA8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REALVIEW_PBA8 +# endif +# define machine_is_realview_pba8() (machine_arch_type == MACH_TYPE_REALVIEW_PBA8) +#else +# define machine_is_realview_pba8() (0) +#endif + +#ifdef CONFIG_MACH_HID_A7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HID_A7 +# endif +# define machine_is_hid_a7() (machine_arch_type == MACH_TYPE_HID_A7) +#else +# define machine_is_hid_a7() (0) +#endif + +#ifdef CONFIG_MACH_HERO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HERO +# endif +# define machine_is_hero() (machine_arch_type == MACH_TYPE_HERO) +#else +# define machine_is_hero() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_POSEIDON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_POSEIDON +# endif +# define machine_is_omap_poseidon() (machine_arch_type == MACH_TYPE_OMAP_POSEIDON) +#else +# define machine_is_omap_poseidon() (0) +#endif + +#ifdef CONFIG_MACH_REALVIEW_PBX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REALVIEW_PBX +# endif +# define machine_is_realview_pbx() (machine_arch_type == MACH_TYPE_REALVIEW_PBX) +#else +# define machine_is_realview_pbx() (0) +#endif + +#ifdef CONFIG_MACH_MICRO9S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO9S +# endif +# define machine_is_micro9s() (machine_arch_type == MACH_TYPE_MICRO9S) +#else +# define machine_is_micro9s() (0) +#endif + +#ifdef CONFIG_MACH_MAKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAKO +# endif +# define machine_is_mako() (machine_arch_type == MACH_TYPE_MAKO) +#else +# define machine_is_mako() (0) +#endif + +#ifdef CONFIG_MACH_XDAFLAME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XDAFLAME +# endif +# define machine_is_xdaflame() (machine_arch_type == MACH_TYPE_XDAFLAME) +#else +# define machine_is_xdaflame() (0) +#endif + +#ifdef CONFIG_MACH_PHIDGET_SBC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHIDGET_SBC2 +# endif +# define machine_is_phidget_sbc2() (machine_arch_type == MACH_TYPE_PHIDGET_SBC2) +#else +# define machine_is_phidget_sbc2() (0) +#endif + +#ifdef CONFIG_MACH_LIMESTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIMESTONE +# endif +# define machine_is_limestone() (machine_arch_type == MACH_TYPE_LIMESTONE) +#else +# define machine_is_limestone() (0) +#endif + +#ifdef CONFIG_MACH_IPROBE_C32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPROBE_C32 +# endif +# define machine_is_iprobe_c32() (machine_arch_type == MACH_TYPE_IPROBE_C32) +#else +# define machine_is_iprobe_c32() (0) +#endif + +#ifdef CONFIG_MACH_RUT100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RUT100 +# endif +# define machine_is_rut100() (machine_arch_type == MACH_TYPE_RUT100) +#else +# define machine_is_rut100() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP535 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP535 +# endif +# define machine_is_asusp535() (machine_arch_type == MACH_TYPE_ASUSP535) +#else +# define machine_is_asusp535() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL +# endif +# define machine_is_htcraphael() (machine_arch_type == MACH_TYPE_HTCRAPHAEL) +#else +# define machine_is_htcraphael() (0) +#endif + +#ifdef CONFIG_MACH_SYGDG1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYGDG1 +# endif +# define machine_is_sygdg1() (machine_arch_type == MACH_TYPE_SYGDG1) +#else +# define machine_is_sygdg1() (0) +#endif + +#ifdef CONFIG_MACH_SYGDG2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYGDG2 +# endif +# define machine_is_sygdg2() (machine_arch_type == MACH_TYPE_SYGDG2) +#else +# define machine_is_sygdg2() (0) +#endif + +#ifdef CONFIG_MACH_SEOUL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SEOUL +# endif +# define machine_is_seoul() (machine_arch_type == MACH_TYPE_SEOUL) +#else +# define machine_is_seoul() (0) +#endif + +#ifdef CONFIG_MACH_SALERNO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SALERNO +# endif +# define machine_is_salerno() (machine_arch_type == MACH_TYPE_SALERNO) +#else +# define machine_is_salerno() (0) +#endif + +#ifdef CONFIG_MACH_UCN_S3C64XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UCN_S3C64XX +# endif +# define machine_is_ucn_s3c64xx() (machine_arch_type == MACH_TYPE_UCN_S3C64XX) +#else +# define machine_is_ucn_s3c64xx() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A +# endif +# define machine_is_msm7201a() (machine_arch_type == MACH_TYPE_MSM7201A) +#else +# define machine_is_msm7201a() (0) +#endif + +#ifdef CONFIG_MACH_LPR1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPR1 +# endif +# define machine_is_lpr1() (machine_arch_type == MACH_TYPE_LPR1) +#else +# define machine_is_lpr1() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO500FX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO500FX +# endif +# define machine_is_armadillo500fx() (machine_arch_type == MACH_TYPE_ARMADILLO500FX) +#else +# define machine_is_armadillo500fx() (0) +#endif + +#ifdef CONFIG_MACH_G3EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G3EVM +# endif +# define machine_is_g3evm() (machine_arch_type == MACH_TYPE_G3EVM) +#else +# define machine_is_g3evm() (0) +#endif + +#ifdef CONFIG_MACH_Z3_DM355 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Z3_DM355 +# endif +# define machine_is_z3_dm355() (machine_arch_type == MACH_TYPE_Z3_DM355) +#else +# define machine_is_z3_dm355() (0) +#endif + +#ifdef CONFIG_MACH_W90P910EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90P910EVB +# endif +# define machine_is_w90p910evb() (machine_arch_type == MACH_TYPE_W90P910EVB) +#else +# define machine_is_w90p910evb() (0) +#endif + +#ifdef CONFIG_MACH_W90P920EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90P920EVB +# endif +# define machine_is_w90p920evb() (machine_arch_type == MACH_TYPE_W90P920EVB) +#else +# define machine_is_w90p920evb() (0) +#endif + +#ifdef CONFIG_MACH_W90P950EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90P950EVB +# endif +# define machine_is_w90p950evb() (machine_arch_type == MACH_TYPE_W90P950EVB) +#else +# define machine_is_w90p950evb() (0) +#endif + +#ifdef CONFIG_MACH_W90N960EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90N960EVB +# endif +# define machine_is_w90n960evb() (machine_arch_type == MACH_TYPE_W90N960EVB) +#else +# define machine_is_w90n960evb() (0) +#endif + +#ifdef CONFIG_MACH_CAMHD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAMHD +# endif +# define machine_is_camhd() (machine_arch_type == MACH_TYPE_CAMHD) +#else +# define machine_is_camhd() (0) +#endif + +#ifdef CONFIG_MACH_MVC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MVC100 +# endif +# define machine_is_mvc100() (machine_arch_type == MACH_TYPE_MVC100) +#else +# define machine_is_mvc100() (0) +#endif + +#ifdef CONFIG_MACH_ELECTRUM_200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELECTRUM_200 +# endif +# define machine_is_electrum_200() (machine_arch_type == MACH_TYPE_ELECTRUM_200) +#else +# define machine_is_electrum_200() (0) +#endif + +#ifdef CONFIG_MACH_HTCJADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCJADE +# endif +# define machine_is_htcjade() (machine_arch_type == MACH_TYPE_HTCJADE) +#else +# define machine_is_htcjade() (0) +#endif + +#ifdef CONFIG_MACH_MEMPHIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEMPHIS +# endif +# define machine_is_memphis() (machine_arch_type == MACH_TYPE_MEMPHIS) +#else +# define machine_is_memphis() (0) +#endif + +#ifdef CONFIG_MACH_IMX27SBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27SBC +# endif +# define machine_is_imx27sbc() (machine_arch_type == MACH_TYPE_IMX27SBC) +#else +# define machine_is_imx27sbc() (0) +#endif + +#ifdef CONFIG_MACH_LEXTAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEXTAR +# endif +# define machine_is_lextar() (machine_arch_type == MACH_TYPE_LEXTAR) +#else +# define machine_is_lextar() (0) +#endif + +#ifdef CONFIG_MACH_MV88F6281GTW_GE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV88F6281GTW_GE +# endif +# define machine_is_mv88f6281gtw_ge() (machine_arch_type == MACH_TYPE_MV88F6281GTW_GE) +#else +# define machine_is_mv88f6281gtw_ge() (0) +#endif + +#ifdef CONFIG_MACH_NCP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NCP +# endif +# define machine_is_ncp() (machine_arch_type == MACH_TYPE_NCP) +#else +# define machine_is_ncp() (0) +#endif + +#ifdef CONFIG_MACH_Z32AN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Z32AN +# endif +# define machine_is_z32an_series() (machine_arch_type == MACH_TYPE_Z32AN) +#else +# define machine_is_z32an_series() (0) +#endif + +#ifdef CONFIG_MACH_TMQ_CAPD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TMQ_CAPD +# endif +# define machine_is_tmq_capd() (machine_arch_type == MACH_TYPE_TMQ_CAPD) +#else +# define machine_is_tmq_capd() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_WL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_WL +# endif +# define machine_is_omap3_wl() (machine_arch_type == MACH_TYPE_OMAP3_WL) +#else +# define machine_is_omap3_wl() (0) +#endif + +#ifdef CONFIG_MACH_CHUMBY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHUMBY +# endif +# define machine_is_chumby() (machine_arch_type == MACH_TYPE_CHUMBY) +#else +# define machine_is_chumby() (0) +#endif + +#ifdef CONFIG_MACH_ATSARM9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATSARM9 +# endif +# define machine_is_atsarm9() (machine_arch_type == MACH_TYPE_ATSARM9) +#else +# define machine_is_atsarm9() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM365_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM365_EVM +# endif +# define machine_is_davinci_dm365_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM) +#else +# define machine_is_davinci_dm365_evm() (0) +#endif + +#ifdef CONFIG_MACH_BAHAMAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BAHAMAS +# endif +# define machine_is_bahamas() (machine_arch_type == MACH_TYPE_BAHAMAS) +#else +# define machine_is_bahamas() (0) +#endif + +#ifdef CONFIG_MACH_DAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAS +# endif +# define machine_is_das() (machine_arch_type == MACH_TYPE_DAS) +#else +# define machine_is_das() (0) +#endif + +#ifdef CONFIG_MACH_MINIDAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINIDAS +# endif +# define machine_is_minidas() (machine_arch_type == MACH_TYPE_MINIDAS) +#else +# define machine_is_minidas() (0) +#endif + +#ifdef CONFIG_MACH_VK1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VK1000 +# endif +# define machine_is_vk1000() (machine_arch_type == MACH_TYPE_VK1000) +#else +# define machine_is_vk1000() (0) +#endif + +#ifdef CONFIG_MACH_CENTRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CENTRO +# endif +# define machine_is_centro() (machine_arch_type == MACH_TYPE_CENTRO) +#else +# define machine_is_centro() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY +# endif +# define machine_is_ctera_2bay() (machine_arch_type == MACH_TYPE_CTERA_2BAY) +#else +# define machine_is_ctera_2bay() (0) +#endif + +#ifdef CONFIG_MACH_EDGECONNECT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDGECONNECT +# endif +# define machine_is_edgeconnect() (machine_arch_type == MACH_TYPE_EDGECONNECT) +#else +# define machine_is_edgeconnect() (0) +#endif + +#ifdef CONFIG_MACH_ND27000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ND27000 +# endif +# define machine_is_nd27000() (machine_arch_type == MACH_TYPE_ND27000) +#else +# define machine_is_nd27000() (0) +#endif + +#ifdef CONFIG_MACH_GEMALTO_COBRA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMALTO_COBRA +# endif +# define machine_is_cobra() (machine_arch_type == MACH_TYPE_GEMALTO_COBRA) +#else +# define machine_is_cobra() (0) +#endif + +#ifdef CONFIG_MACH_INGELABS_COMET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INGELABS_COMET +# endif +# define machine_is_ingelabs_comet() (machine_arch_type == MACH_TYPE_INGELABS_COMET) +#else +# define machine_is_ingelabs_comet() (0) +#endif + +#ifdef CONFIG_MACH_POLLUX_WIZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POLLUX_WIZ +# endif +# define machine_is_pollux_wiz() (machine_arch_type == MACH_TYPE_POLLUX_WIZ) +#else +# define machine_is_pollux_wiz() (0) +#endif + +#ifdef CONFIG_MACH_BLACKSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLACKSTONE +# endif +# define machine_is_blackstone() (machine_arch_type == MACH_TYPE_BLACKSTONE) +#else +# define machine_is_blackstone() (0) +#endif + +#ifdef CONFIG_MACH_TOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOPAZ +# endif +# define machine_is_topaz() (machine_arch_type == MACH_TYPE_TOPAZ) +#else +# define machine_is_topaz() (0) +#endif + +#ifdef CONFIG_MACH_AIXLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AIXLE +# endif +# define machine_is_aixle() (machine_arch_type == MACH_TYPE_AIXLE) +#else +# define machine_is_aixle() (0) +#endif + +#ifdef CONFIG_MACH_MW998 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW998 +# endif +# define machine_is_mw998() (machine_arch_type == MACH_TYPE_MW998) +#else +# define machine_is_mw998() (0) +#endif + +#ifdef CONFIG_MACH_NOKIA_RX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOKIA_RX51 +# endif +# define machine_is_nokia_rx51() (machine_arch_type == MACH_TYPE_NOKIA_RX51) +#else +# define machine_is_nokia_rx51() (0) +#endif + +#ifdef CONFIG_MACH_VSC5605EV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VSC5605EV +# endif +# define machine_is_vsc5605ev() (machine_arch_type == MACH_TYPE_VSC5605EV) +#else +# define machine_is_vsc5605ev() (0) +#endif + +#ifdef CONFIG_MACH_NT98700DK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NT98700DK +# endif +# define machine_is_nt98700dk() (machine_arch_type == MACH_TYPE_NT98700DK) +#else +# define machine_is_nt98700dk() (0) +#endif + +#ifdef CONFIG_MACH_ICONTACT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICONTACT +# endif +# define machine_is_icontact() (machine_arch_type == MACH_TYPE_ICONTACT) +#else +# define machine_is_icontact() (0) +#endif + +#ifdef CONFIG_MACH_SWARCO_FRCPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCO_FRCPU +# endif +# define machine_is_swarco_frcpu() (machine_arch_type == MACH_TYPE_SWARCO_FRCPU) +#else +# define machine_is_swarco_frcpu() (0) +#endif + +#ifdef CONFIG_MACH_SWARCO_SCPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCO_SCPU +# endif +# define machine_is_swarco_scpu() (machine_arch_type == MACH_TYPE_SWARCO_SCPU) +#else +# define machine_is_swarco_scpu() (0) +#endif + +#ifdef CONFIG_MACH_BBOX_P16 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BBOX_P16 +# endif +# define machine_is_bbox_p16() (machine_arch_type == MACH_TYPE_BBOX_P16) +#else +# define machine_is_bbox_p16() (0) +#endif + +#ifdef CONFIG_MACH_BSTD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSTD +# endif +# define machine_is_bstd() (machine_arch_type == MACH_TYPE_BSTD) +#else +# define machine_is_bstd() (0) +#endif + +#ifdef CONFIG_MACH_SBC2440II +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC2440II +# endif +# define machine_is_sbc2440ii() (machine_arch_type == MACH_TYPE_SBC2440II) +#else +# define machine_is_sbc2440ii() (0) +#endif + +#ifdef CONFIG_MACH_PCM034 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM034 +# endif +# define machine_is_pcm034() (machine_arch_type == MACH_TYPE_PCM034) +#else +# define machine_is_pcm034() (0) +#endif + +#ifdef CONFIG_MACH_NESO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NESO +# endif +# define machine_is_neso() (machine_arch_type == MACH_TYPE_NESO) +#else +# define machine_is_neso() (0) +#endif + +#ifdef CONFIG_MACH_WLNX_9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WLNX_9G20 +# endif +# define machine_is_wlnx_9g20() (machine_arch_type == MACH_TYPE_WLNX_9G20) +#else +# define machine_is_wlnx_9g20() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_ZOOM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_ZOOM2 +# endif +# define machine_is_omap_zoom2() (machine_arch_type == MACH_TYPE_OMAP_ZOOM2) +#else +# define machine_is_omap_zoom2() (0) +#endif + +#ifdef CONFIG_MACH_TOTEMNOVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOTEMNOVA +# endif +# define machine_is_totemnova() (machine_arch_type == MACH_TYPE_TOTEMNOVA) +#else +# define machine_is_totemnova() (0) +#endif + +#ifdef CONFIG_MACH_C5000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C5000 +# endif +# define machine_is_c5000() (machine_arch_type == MACH_TYPE_C5000) +#else +# define machine_is_c5000() (0) +#endif + +#ifdef CONFIG_MACH_UNIPO_AT91SAM9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNIPO_AT91SAM9263 +# endif +# define machine_is_unipo_at91sam9263() (machine_arch_type == MACH_TYPE_UNIPO_AT91SAM9263) +#else +# define machine_is_unipo_at91sam9263() (0) +#endif + +#ifdef CONFIG_MACH_ETHERNUT5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETHERNUT5 +# endif +# define machine_is_ethernut5() (machine_arch_type == MACH_TYPE_ETHERNUT5) +#else +# define machine_is_ethernut5() (0) +#endif + +#ifdef CONFIG_MACH_ARM11 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM11 +# endif +# define machine_is_arm11() (machine_arch_type == MACH_TYPE_ARM11) +#else +# define machine_is_arm11() (0) +#endif + +#ifdef CONFIG_MACH_CPUAT9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUAT9260 +# endif +# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260) +#else +# define machine_is_cpuat9260() (0) +#endif + +#ifdef CONFIG_MACH_CPUPXA255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUPXA255 +# endif +# define machine_is_cpupxa255() (machine_arch_type == MACH_TYPE_CPUPXA255) +#else +# define machine_is_cpupxa255() (0) +#endif + +#ifdef CONFIG_MACH_CPUIMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUIMX27 +# endif +# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) +#else +# define machine_is_eukrea_cpuimx27() (0) +#endif + +#ifdef CONFIG_MACH_CHEFLUX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHEFLUX +# endif +# define machine_is_cheflux() (machine_arch_type == MACH_TYPE_CHEFLUX) +#else +# define machine_is_cheflux() (0) +#endif + +#ifdef CONFIG_MACH_EB_CPUX9K2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EB_CPUX9K2 +# endif +# define machine_is_eb_cpux9k2() (machine_arch_type == MACH_TYPE_EB_CPUX9K2) +#else +# define machine_is_eb_cpux9k2() (0) +#endif + +#ifdef CONFIG_MACH_OPCOTEC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPCOTEC +# endif +# define machine_is_opcotec() (machine_arch_type == MACH_TYPE_OPCOTEC) +#else +# define machine_is_opcotec() (0) +#endif + +#ifdef CONFIG_MACH_YT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YT +# endif +# define machine_is_yt() (machine_arch_type == MACH_TYPE_YT) +#else +# define machine_is_yt() (0) +#endif + +#ifdef CONFIG_MACH_MOTOQ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOQ +# endif +# define machine_is_motoq() (machine_arch_type == MACH_TYPE_MOTOQ) +#else +# define machine_is_motoq() (0) +#endif + +#ifdef CONFIG_MACH_BSB1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSB1 +# endif +# define machine_is_bsb1() (machine_arch_type == MACH_TYPE_BSB1) +#else +# define machine_is_bsb1() (0) +#endif + +#ifdef CONFIG_MACH_ACS5K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACS5K +# endif +# define machine_is_acs5k() (machine_arch_type == MACH_TYPE_ACS5K) +#else +# define machine_is_acs5k() (0) +#endif + +#ifdef CONFIG_MACH_MILAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MILAN +# endif +# define machine_is_milan() (machine_arch_type == MACH_TYPE_MILAN) +#else +# define machine_is_milan() (0) +#endif + +#ifdef CONFIG_MACH_QUARTZV2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUARTZV2 +# endif +# define machine_is_quartzv2() (machine_arch_type == MACH_TYPE_QUARTZV2) +#else +# define machine_is_quartzv2() (0) +#endif + +#ifdef CONFIG_MACH_RSVP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSVP +# endif +# define machine_is_rsvp() (machine_arch_type == MACH_TYPE_RSVP) +#else +# define machine_is_rsvp() (0) +#endif + +#ifdef CONFIG_MACH_RMP200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RMP200 +# endif +# define machine_is_rmp200() (machine_arch_type == MACH_TYPE_RMP200) +#else +# define machine_is_rmp200() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPER_9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPER_9260 +# endif +# define machine_is_snapper_9260() (machine_arch_type == MACH_TYPE_SNAPPER_9260) +#else +# define machine_is_snapper_9260() (0) +#endif + +#ifdef CONFIG_MACH_DSM320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSM320 +# endif +# define machine_is_dsm320() (machine_arch_type == MACH_TYPE_DSM320) +#else +# define machine_is_dsm320() (0) +#endif + +#ifdef CONFIG_MACH_ADSGCM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSGCM +# endif +# define machine_is_adsgcm() (machine_arch_type == MACH_TYPE_ADSGCM) +#else +# define machine_is_adsgcm() (0) +#endif + +#ifdef CONFIG_MACH_ASE2_400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASE2_400 +# endif +# define machine_is_ase2_400() (machine_arch_type == MACH_TYPE_ASE2_400) +#else +# define machine_is_ase2_400() (0) +#endif + +#ifdef CONFIG_MACH_PIZZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PIZZA +# endif +# define machine_is_pizza() (machine_arch_type == MACH_TYPE_PIZZA) +#else +# define machine_is_pizza() (0) +#endif + +#ifdef CONFIG_MACH_SPOT_NGPL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPOT_NGPL +# endif +# define machine_is_spot_ngpl() (machine_arch_type == MACH_TYPE_SPOT_NGPL) +#else +# define machine_is_spot_ngpl() (0) +#endif + +#ifdef CONFIG_MACH_ARMATA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMATA +# endif +# define machine_is_armata() (machine_arch_type == MACH_TYPE_ARMATA) +#else +# define machine_is_armata() (0) +#endif + +#ifdef CONFIG_MACH_EXEDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXEDA +# endif +# define machine_is_exeda() (machine_arch_type == MACH_TYPE_EXEDA) +#else +# define machine_is_exeda() (0) +#endif + +#ifdef CONFIG_MACH_MX31SF005 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31SF005 +# endif +# define machine_is_mx31sf005() (machine_arch_type == MACH_TYPE_MX31SF005) +#else +# define machine_is_mx31sf005() (0) +#endif + +#ifdef CONFIG_MACH_F5D8231_4_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_F5D8231_4_V2 +# endif +# define machine_is_f5d8231_4_v2() (machine_arch_type == MACH_TYPE_F5D8231_4_V2) +#else +# define machine_is_f5d8231_4_v2() (0) +#endif + +#ifdef CONFIG_MACH_Q2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Q2440 +# endif +# define machine_is_q2440() (machine_arch_type == MACH_TYPE_Q2440) +#else +# define machine_is_q2440() (0) +#endif + +#ifdef CONFIG_MACH_QQ2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QQ2440 +# endif +# define machine_is_qq2440() (machine_arch_type == MACH_TYPE_QQ2440) +#else +# define machine_is_qq2440() (0) +#endif + +#ifdef CONFIG_MACH_MINI2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI2440 +# endif +# define machine_is_mini2440() (machine_arch_type == MACH_TYPE_MINI2440) +#else +# define machine_is_mini2440() (0) +#endif + +#ifdef CONFIG_MACH_COLIBRI300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLIBRI300 +# endif +# define machine_is_colibri300() (machine_arch_type == MACH_TYPE_COLIBRI300) +#else +# define machine_is_colibri300() (0) +#endif + +#ifdef CONFIG_MACH_JADES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JADES +# endif +# define machine_is_jades() (machine_arch_type == MACH_TYPE_JADES) +#else +# define machine_is_jades() (0) +#endif + +#ifdef CONFIG_MACH_SPARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPARK +# endif +# define machine_is_spark() (machine_arch_type == MACH_TYPE_SPARK) +#else +# define machine_is_spark() (0) +#endif + +#ifdef CONFIG_MACH_BENZINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZINA +# endif +# define machine_is_benzina() (machine_arch_type == MACH_TYPE_BENZINA) +#else +# define machine_is_benzina() (0) +#endif + +#ifdef CONFIG_MACH_BLAZE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLAZE +# endif +# define machine_is_blaze() (machine_arch_type == MACH_TYPE_BLAZE) +#else +# define machine_is_blaze() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_LS_HGL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_LS_HGL +# endif +# define machine_is_linkstation_ls_hgl() (machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL) +#else +# define machine_is_linkstation_ls_hgl() (0) +#endif + +#ifdef CONFIG_MACH_HTCKOVSKY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCKOVSKY +# endif +# define machine_is_htckovsky() (machine_arch_type == MACH_TYPE_HTCKOVSKY) +#else +# define machine_is_htckovsky() (0) +#endif + +#ifdef CONFIG_MACH_SONY_PRS505 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONY_PRS505 +# endif +# define machine_is_sony_prs505() (machine_arch_type == MACH_TYPE_SONY_PRS505) +#else +# define machine_is_sony_prs505() (0) +#endif + +#ifdef CONFIG_MACH_HANLIN_V3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HANLIN_V3 +# endif +# define machine_is_hanlin_v3() (machine_arch_type == MACH_TYPE_HANLIN_V3) +#else +# define machine_is_hanlin_v3() (0) +#endif + +#ifdef CONFIG_MACH_SAPPHIRA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAPPHIRA +# endif +# define machine_is_sapphira() (machine_arch_type == MACH_TYPE_SAPPHIRA) +#else +# define machine_is_sapphira() (0) +#endif + +#ifdef CONFIG_MACH_DACK_SDA_01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DACK_SDA_01 +# endif +# define machine_is_dack_sda_01() (machine_arch_type == MACH_TYPE_DACK_SDA_01) +#else +# define machine_is_dack_sda_01() (0) +#endif + +#ifdef CONFIG_MACH_ARMBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMBOX +# endif +# define machine_is_armbox() (machine_arch_type == MACH_TYPE_ARMBOX) +#else +# define machine_is_armbox() (0) +#endif + +#ifdef CONFIG_MACH_HARRIS_RVP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HARRIS_RVP +# endif +# define machine_is_harris_rvp() (machine_arch_type == MACH_TYPE_HARRIS_RVP) +#else +# define machine_is_harris_rvp() (0) +#endif + +#ifdef CONFIG_MACH_RIBALDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIBALDO +# endif +# define machine_is_ribaldo() (machine_arch_type == MACH_TYPE_RIBALDO) +#else +# define machine_is_ribaldo() (0) +#endif + +#ifdef CONFIG_MACH_AGORA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AGORA +# endif +# define machine_is_agora() (machine_arch_type == MACH_TYPE_AGORA) +#else +# define machine_is_agora() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_MINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_MINI +# endif +# define machine_is_omap3_mini() (machine_arch_type == MACH_TYPE_OMAP3_MINI) +#else +# define machine_is_omap3_mini() (0) +#endif + +#ifdef CONFIG_MACH_A9SAM6432_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A9SAM6432_B +# endif +# define machine_is_a9sam6432_b() (machine_arch_type == MACH_TYPE_A9SAM6432_B) +#else +# define machine_is_a9sam6432_b() (0) +#endif + +#ifdef CONFIG_MACH_USG2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USG2410 +# endif +# define machine_is_usg2410() (machine_arch_type == MACH_TYPE_USG2410) +#else +# define machine_is_usg2410() (0) +#endif + +#ifdef CONFIG_MACH_PC72052_I10_REVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC72052_I10_REVB +# endif +# define machine_is_pc72052_i10_revb() (machine_arch_type == MACH_TYPE_PC72052_I10_REVB) +#else +# define machine_is_pc72052_i10_revb() (0) +#endif + +#ifdef CONFIG_MACH_MX35_EXM32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX35_EXM32 +# endif +# define machine_is_mx35_exm32() (machine_arch_type == MACH_TYPE_MX35_EXM32) +#else +# define machine_is_mx35_exm32() (0) +#endif + +#ifdef CONFIG_MACH_TOPAS910 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOPAS910 +# endif +# define machine_is_topas910() (machine_arch_type == MACH_TYPE_TOPAS910) +#else +# define machine_is_topas910() (0) +#endif + +#ifdef CONFIG_MACH_HYENA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HYENA +# endif +# define machine_is_hyena() (machine_arch_type == MACH_TYPE_HYENA) +#else +# define machine_is_hyena() (0) +#endif + +#ifdef CONFIG_MACH_POSPAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POSPAX +# endif +# define machine_is_pospax() (machine_arch_type == MACH_TYPE_POSPAX) +#else +# define machine_is_pospax() (0) +#endif + +#ifdef CONFIG_MACH_HDL_GX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDL_GX +# endif +# define machine_is_hdl_gx() (machine_arch_type == MACH_TYPE_HDL_GX) +#else +# define machine_is_hdl_gx() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_4BAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_4BAY +# endif +# define machine_is_ctera_4bay() (machine_arch_type == MACH_TYPE_CTERA_4BAY) +#else +# define machine_is_ctera_4bay() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_PLUG_C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_PLUG_C +# endif +# define machine_is_ctera_plug_c() (machine_arch_type == MACH_TYPE_CTERA_PLUG_C) +#else +# define machine_is_ctera_plug_c() (0) +#endif + +#ifdef CONFIG_MACH_CRWEA_PLUG_I +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CRWEA_PLUG_I +# endif +# define machine_is_crwea_plug_i() (machine_arch_type == MACH_TYPE_CRWEA_PLUG_I) +#else +# define machine_is_crwea_plug_i() (0) +#endif + +#ifdef CONFIG_MACH_EGAUGE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EGAUGE2 +# endif +# define machine_is_egauge2() (machine_arch_type == MACH_TYPE_EGAUGE2) +#else +# define machine_is_egauge2() (0) +#endif + +#ifdef CONFIG_MACH_DIDJ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DIDJ +# endif +# define machine_is_didj() (machine_arch_type == MACH_TYPE_DIDJ) +#else +# define machine_is_didj() (0) +#endif + +#ifdef CONFIG_MACH_MEISTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEISTER +# endif +# define machine_is_m_s3c2443() (machine_arch_type == MACH_TYPE_MEISTER) +#else +# define machine_is_m_s3c2443() (0) +#endif + +#ifdef CONFIG_MACH_HTCBLACKSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCBLACKSTONE +# endif +# define machine_is_htcblackstone() (machine_arch_type == MACH_TYPE_HTCBLACKSTONE) +#else +# define machine_is_htcblackstone() (0) +#endif + +#ifdef CONFIG_MACH_CPUAT9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUAT9G20 +# endif +# define machine_is_cpuat9g20() (machine_arch_type == MACH_TYPE_CPUAT9G20) +#else +# define machine_is_cpuat9g20() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6440 +# endif +# define machine_is_smdk6440() (machine_arch_type == MACH_TYPE_SMDK6440) +#else +# define machine_is_smdk6440() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_35XX_MVP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_35XX_MVP +# endif +# define machine_is_omap_35xx_mvp() (machine_arch_type == MACH_TYPE_OMAP_35XX_MVP) +#else +# define machine_is_omap_35xx_mvp() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_PLUG_I +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_PLUG_I +# endif +# define machine_is_ctera_plug_i() (machine_arch_type == MACH_TYPE_CTERA_PLUG_I) +#else +# define machine_is_ctera_plug_i() (0) +#endif + +#ifdef CONFIG_MACH_PVG610 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PVG610 +# endif +# define machine_is_pvg610_100() (machine_arch_type == MACH_TYPE_PVG610) +#else +# define machine_is_pvg610_100() (0) +#endif + +#ifdef CONFIG_MACH_HPRW6815 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPRW6815 +# endif +# define machine_is_hprw6815() (machine_arch_type == MACH_TYPE_HPRW6815) +#else +# define machine_is_hprw6815() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_OSWALD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_OSWALD +# endif +# define machine_is_omap3_oswald() (machine_arch_type == MACH_TYPE_OMAP3_OSWALD) +#else +# define machine_is_omap3_oswald() (0) +#endif + +#ifdef CONFIG_MACH_NAS4220B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAS4220B +# endif +# define machine_is_nas4220b() (machine_arch_type == MACH_TYPE_NAS4220B) +#else +# define machine_is_nas4220b() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA +# endif +# define machine_is_htcraphael_cdma() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA) +#else +# define machine_is_htcraphael_cdma() (0) +#endif + +#ifdef CONFIG_MACH_HTCDIAMOND_CDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCDIAMOND_CDMA +# endif +# define machine_is_htcdiamond_cdma() (machine_arch_type == MACH_TYPE_HTCDIAMOND_CDMA) +#else +# define machine_is_htcdiamond_cdma() (0) +#endif + +#ifdef CONFIG_MACH_SCALER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCALER +# endif +# define machine_is_scaler() (machine_arch_type == MACH_TYPE_SCALER) +#else +# define machine_is_scaler() (0) +#endif + +#ifdef CONFIG_MACH_ZYLONITE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZYLONITE2 +# endif +# define machine_is_zylonite2() (machine_arch_type == MACH_TYPE_ZYLONITE2) +#else +# define machine_is_zylonite2() (0) +#endif + +#ifdef CONFIG_MACH_ASPENITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASPENITE +# endif +# define machine_is_aspenite() (machine_arch_type == MACH_TYPE_ASPENITE) +#else +# define machine_is_aspenite() (0) +#endif + +#ifdef CONFIG_MACH_TETON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TETON +# endif +# define machine_is_teton() (machine_arch_type == MACH_TYPE_TETON) +#else +# define machine_is_teton() (0) +#endif + +#ifdef CONFIG_MACH_TTC_DKB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TTC_DKB +# endif +# define machine_is_ttc_dkb() (machine_arch_type == MACH_TYPE_TTC_DKB) +#else +# define machine_is_ttc_dkb() (0) +#endif + +#ifdef CONFIG_MACH_BISHOP2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BISHOP2 +# endif +# define machine_is_bishop2() (machine_arch_type == MACH_TYPE_BISHOP2) +#else +# define machine_is_bishop2() (0) +#endif + +#ifdef CONFIG_MACH_IPPV5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPPV5 +# endif +# define machine_is_ippv5() (machine_arch_type == MACH_TYPE_IPPV5) +#else +# define machine_is_ippv5() (0) +#endif + +#ifdef CONFIG_MACH_FARM926 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FARM926 +# endif +# define machine_is_farm926() (machine_arch_type == MACH_TYPE_FARM926) +#else +# define machine_is_farm926() (0) +#endif + +#ifdef CONFIG_MACH_MMCCPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMCCPU +# endif +# define machine_is_mmccpu() (machine_arch_type == MACH_TYPE_MMCCPU) +#else +# define machine_is_mmccpu() (0) +#endif + +#ifdef CONFIG_MACH_SGMSFL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGMSFL +# endif +# define machine_is_sgmsfl() (machine_arch_type == MACH_TYPE_SGMSFL) +#else +# define machine_is_sgmsfl() (0) +#endif + +#ifdef CONFIG_MACH_TT8000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TT8000 +# endif +# define machine_is_tt8000() (machine_arch_type == MACH_TYPE_TT8000) +#else +# define machine_is_tt8000() (0) +#endif + +#ifdef CONFIG_MACH_ZRN4300LP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZRN4300LP +# endif +# define machine_is_zrn4300lp() (machine_arch_type == MACH_TYPE_ZRN4300LP) +#else +# define machine_is_zrn4300lp() (0) +#endif + +#ifdef CONFIG_MACH_MPTC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPTC +# endif +# define machine_is_mptc() (machine_arch_type == MACH_TYPE_MPTC) +#else +# define machine_is_mptc() (0) +#endif + +#ifdef CONFIG_MACH_H6051 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6051 +# endif +# define machine_is_h6051() (machine_arch_type == MACH_TYPE_H6051) +#else +# define machine_is_h6051() (0) +#endif + +#ifdef CONFIG_MACH_PVG610_101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PVG610_101 +# endif +# define machine_is_pvg610_101() (machine_arch_type == MACH_TYPE_PVG610_101) +#else +# define machine_is_pvg610_101() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9261_PC_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9261_PC_EVB +# endif +# define machine_is_stamp9261_pc_evb() (machine_arch_type == MACH_TYPE_STAMP9261_PC_EVB) +#else +# define machine_is_stamp9261_pc_evb() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_ODYSSEUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_ODYSSEUS +# endif +# define machine_is_pelco_odysseus() (machine_arch_type == MACH_TYPE_PELCO_ODYSSEUS) +#else +# define machine_is_pelco_odysseus() (0) +#endif + +#ifdef CONFIG_MACH_TNY_A9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNY_A9260 +# endif +# define machine_is_tny_a9260() (machine_arch_type == MACH_TYPE_TNY_A9260) +#else +# define machine_is_tny_a9260() (0) +#endif + +#ifdef CONFIG_MACH_TNY_A9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNY_A9G20 +# endif +# define machine_is_tny_a9g20() (machine_arch_type == MACH_TYPE_TNY_A9G20) +#else +# define machine_is_tny_a9g20() (0) +#endif + +#ifdef CONFIG_MACH_AESOP_MP2530F +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AESOP_MP2530F +# endif +# define machine_is_aesop_mp2530f() (machine_arch_type == MACH_TYPE_AESOP_MP2530F) +#else +# define machine_is_aesop_mp2530f() (0) +#endif + +#ifdef CONFIG_MACH_DX900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DX900 +# endif +# define machine_is_dx900() (machine_arch_type == MACH_TYPE_DX900) +#else +# define machine_is_dx900() (0) +#endif + +#ifdef CONFIG_MACH_CPODC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPODC2 +# endif +# define machine_is_cpodc2() (machine_arch_type == MACH_TYPE_CPODC2) +#else +# define machine_is_cpodc2() (0) +#endif + +#ifdef CONFIG_MACH_TILT_8925 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TILT_8925 +# endif +# define machine_is_tilt_8925() (machine_arch_type == MACH_TYPE_TILT_8925) +#else +# define machine_is_tilt_8925() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM357_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM357_EVM +# endif +# define machine_is_davinci_dm357_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM357_EVM) +#else +# define machine_is_davinci_dm357_evm() (0) +#endif + +#ifdef CONFIG_MACH_SWORDFISH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWORDFISH +# endif +# define machine_is_swordfish() (machine_arch_type == MACH_TYPE_SWORDFISH) +#else +# define machine_is_swordfish() (0) +#endif + +#ifdef CONFIG_MACH_CORVUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORVUS +# endif +# define machine_is_corvus() (machine_arch_type == MACH_TYPE_CORVUS) +#else +# define machine_is_corvus() (0) +#endif + +#ifdef CONFIG_MACH_TAURUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAURUS +# endif +# define machine_is_taurus() (machine_arch_type == MACH_TYPE_TAURUS) +#else +# define machine_is_taurus() (0) +#endif + +#ifdef CONFIG_MACH_AXM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXM +# endif +# define machine_is_axm() (machine_arch_type == MACH_TYPE_AXM) +#else +# define machine_is_axm() (0) +#endif + +#ifdef CONFIG_MACH_AXC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXC +# endif +# define machine_is_axc() (machine_arch_type == MACH_TYPE_AXC) +#else +# define machine_is_axc() (0) +#endif + +#ifdef CONFIG_MACH_BABY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BABY +# endif +# define machine_is_baby() (machine_arch_type == MACH_TYPE_BABY) +#else +# define machine_is_baby() (0) +#endif + +#ifdef CONFIG_MACH_MP200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP200 +# endif +# define machine_is_mp200() (machine_arch_type == MACH_TYPE_MP200) +#else +# define machine_is_mp200() (0) +#endif + +#ifdef CONFIG_MACH_PCM043 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM043 +# endif +# define machine_is_pcm043() (machine_arch_type == MACH_TYPE_PCM043) +#else +# define machine_is_pcm043() (0) +#endif + +#ifdef CONFIG_MACH_HANLIN_V3C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HANLIN_V3C +# endif +# define machine_is_hanlin_v3c() (machine_arch_type == MACH_TYPE_HANLIN_V3C) +#else +# define machine_is_hanlin_v3c() (0) +#endif + +#ifdef CONFIG_MACH_KBK9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KBK9G20 +# endif +# define machine_is_kbk9g20() (machine_arch_type == MACH_TYPE_KBK9G20) +#else +# define machine_is_kbk9g20() (0) +#endif + +#ifdef CONFIG_MACH_ADSTURBOG5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSTURBOG5 +# endif +# define machine_is_adsturbog5() (machine_arch_type == MACH_TYPE_ADSTURBOG5) +#else +# define machine_is_adsturbog5() (0) +#endif + +#ifdef CONFIG_MACH_AVENGER_LITE1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVENGER_LITE1 +# endif +# define machine_is_avenger_lite1() (machine_arch_type == MACH_TYPE_AVENGER_LITE1) +#else +# define machine_is_avenger_lite1() (0) +#endif + +#ifdef CONFIG_MACH_SUC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUC +# endif +# define machine_is_suc82x() (machine_arch_type == MACH_TYPE_SUC) +#else +# define machine_is_suc82x() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM7S256 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM7S256 +# endif +# define machine_is_at91sam7s256() (machine_arch_type == MACH_TYPE_AT91SAM7S256) +#else +# define machine_is_at91sam7s256() (0) +#endif + +#ifdef CONFIG_MACH_MENDOZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MENDOZA +# endif +# define machine_is_mendoza() (machine_arch_type == MACH_TYPE_MENDOZA) +#else +# define machine_is_mendoza() (0) +#endif + +#ifdef CONFIG_MACH_KIRA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIRA +# endif +# define machine_is_kira() (machine_arch_type == MACH_TYPE_KIRA) +#else +# define machine_is_kira() (0) +#endif + +#ifdef CONFIG_MACH_MX1HBM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX1HBM +# endif +# define machine_is_mx1hbm() (machine_arch_type == MACH_TYPE_MX1HBM) +#else +# define machine_is_mx1hbm() (0) +#endif + +#ifdef CONFIG_MACH_QUATRO43XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUATRO43XX +# endif +# define machine_is_quatro43xx() (machine_arch_type == MACH_TYPE_QUATRO43XX) +#else +# define machine_is_quatro43xx() (0) +#endif + +#ifdef CONFIG_MACH_QUATRO4230 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUATRO4230 +# endif +# define machine_is_quatro4230() (machine_arch_type == MACH_TYPE_QUATRO4230) +#else +# define machine_is_quatro4230() (0) +#endif + +#ifdef CONFIG_MACH_NSB400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB400 +# endif +# define machine_is_nsb400() (machine_arch_type == MACH_TYPE_NSB400) +#else +# define machine_is_nsb400() (0) +#endif + +#ifdef CONFIG_MACH_DRP255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DRP255 +# endif +# define machine_is_drp255() (machine_arch_type == MACH_TYPE_DRP255) +#else +# define machine_is_drp255() (0) +#endif + +#ifdef CONFIG_MACH_THOTH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_THOTH +# endif +# define machine_is_thoth() (machine_arch_type == MACH_TYPE_THOTH) +#else +# define machine_is_thoth() (0) +#endif + +#ifdef CONFIG_MACH_FIRESTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FIRESTONE +# endif +# define machine_is_firestone() (machine_arch_type == MACH_TYPE_FIRESTONE) +#else +# define machine_is_firestone() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP750 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP750 +# endif +# define machine_is_asusp750() (machine_arch_type == MACH_TYPE_ASUSP750) +#else +# define machine_is_asusp750() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_DL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_DL +# endif +# define machine_is_ctera_dl() (machine_arch_type == MACH_TYPE_CTERA_DL) +#else +# define machine_is_ctera_dl() (0) +#endif + +#ifdef CONFIG_MACH_SOCR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOCR +# endif +# define machine_is_socr() (machine_arch_type == MACH_TYPE_SOCR) +#else +# define machine_is_socr() (0) +#endif + +#ifdef CONFIG_MACH_HTCOXYGEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCOXYGEN +# endif +# define machine_is_htcoxygen() (machine_arch_type == MACH_TYPE_HTCOXYGEN) +#else +# define machine_is_htcoxygen() (0) +#endif + +#ifdef CONFIG_MACH_HEROC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HEROC +# endif +# define machine_is_heroc() (machine_arch_type == MACH_TYPE_HEROC) +#else +# define machine_is_heroc() (0) +#endif + +#ifdef CONFIG_MACH_ZENO6800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZENO6800 +# endif +# define machine_is_zeno6800() (machine_arch_type == MACH_TYPE_ZENO6800) +#else +# define machine_is_zeno6800() (0) +#endif + +#ifdef CONFIG_MACH_SC2MCS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SC2MCS +# endif +# define machine_is_sc2mcs() (machine_arch_type == MACH_TYPE_SC2MCS) +#else +# define machine_is_sc2mcs() (0) +#endif + +#ifdef CONFIG_MACH_GENE100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GENE100 +# endif +# define machine_is_gene100() (machine_arch_type == MACH_TYPE_GENE100) +#else +# define machine_is_gene100() (0) +#endif + +#ifdef CONFIG_MACH_AS353X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS353X +# endif +# define machine_is_as353x() (machine_arch_type == MACH_TYPE_AS353X) +#else +# define machine_is_as353x() (0) +#endif + +#ifdef CONFIG_MACH_SHEEVAPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHEEVAPLUG +# endif +# define machine_is_sheevaplug() (machine_arch_type == MACH_TYPE_SHEEVAPLUG) +#else +# define machine_is_sheevaplug() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20 +# endif +# define machine_is_at91sam9g20() (machine_arch_type == MACH_TYPE_AT91SAM9G20) +#else +# define machine_is_at91sam9g20() (0) +#endif + +#ifdef CONFIG_MACH_MV88F6192GTW_FE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV88F6192GTW_FE +# endif +# define machine_is_mv88f6192gtw_fe() (machine_arch_type == MACH_TYPE_MV88F6192GTW_FE) +#else +# define machine_is_mv88f6192gtw_fe() (0) +#endif + +#ifdef CONFIG_MACH_CC9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9200 +# endif +# define machine_is_cc9200() (machine_arch_type == MACH_TYPE_CC9200) +#else +# define machine_is_cc9200() (0) +#endif + +#ifdef CONFIG_MACH_SM9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SM9200 +# endif +# define machine_is_sm9200() (machine_arch_type == MACH_TYPE_SM9200) +#else +# define machine_is_sm9200() (0) +#endif + +#ifdef CONFIG_MACH_TP9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TP9200 +# endif +# define machine_is_tp9200() (machine_arch_type == MACH_TYPE_TP9200) +#else +# define machine_is_tp9200() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPERDV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPERDV +# endif +# define machine_is_snapperdv() (machine_arch_type == MACH_TYPE_SNAPPERDV) +#else +# define machine_is_snapperdv() (0) +#endif + +#ifdef CONFIG_MACH_AVENGERS_LITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVENGERS_LITE +# endif +# define machine_is_avengers_lite() (machine_arch_type == MACH_TYPE_AVENGERS_LITE) +#else +# define machine_is_avengers_lite() (0) +#endif + +#ifdef CONFIG_MACH_AVENGERS_LITE1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVENGERS_LITE1 +# endif +# define machine_is_avengers_lite1() (machine_arch_type == MACH_TYPE_AVENGERS_LITE1) +#else +# define machine_is_avengers_lite1() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3AXON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3AXON +# endif +# define machine_is_omap3axon() (machine_arch_type == MACH_TYPE_OMAP3AXON) +#else +# define machine_is_omap3axon() (0) +#endif + +#ifdef CONFIG_MACH_MA8XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MA8XX +# endif +# define machine_is_ma8xx() (machine_arch_type == MACH_TYPE_MA8XX) +#else +# define machine_is_ma8xx() (0) +#endif + +#ifdef CONFIG_MACH_MP201EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP201EK +# endif +# define machine_is_mp201ek() (machine_arch_type == MACH_TYPE_MP201EK) +#else +# define machine_is_mp201ek() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_TUX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_TUX +# endif +# define machine_is_davinci_tux() (machine_arch_type == MACH_TYPE_DAVINCI_TUX) +#else +# define machine_is_davinci_tux() (0) +#endif + +#ifdef CONFIG_MACH_MPA1600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPA1600 +# endif +# define machine_is_mpa1600() (machine_arch_type == MACH_TYPE_MPA1600) +#else +# define machine_is_mpa1600() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_TROY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_TROY +# endif +# define machine_is_pelco_troy() (machine_arch_type == MACH_TYPE_PELCO_TROY) +#else +# define machine_is_pelco_troy() (0) +#endif + +#ifdef CONFIG_MACH_NSB667 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB667 +# endif +# define machine_is_nsb667() (machine_arch_type == MACH_TYPE_NSB667) +#else +# define machine_is_nsb667() (0) +#endif + +#ifdef CONFIG_MACH_ROVERS5_4MPIX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERS5_4MPIX +# endif +# define machine_is_rovers5_4mpix() (machine_arch_type == MACH_TYPE_ROVERS5_4MPIX) +#else +# define machine_is_rovers5_4mpix() (0) +#endif + +#ifdef CONFIG_MACH_TWOCOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TWOCOM +# endif +# define machine_is_twocom() (machine_arch_type == MACH_TYPE_TWOCOM) +#else +# define machine_is_twocom() (0) +#endif + +#ifdef CONFIG_MACH_UBISYS_P9_RCU3R2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UBISYS_P9_RCU3R2 +# endif +# define machine_is_ubisys_p9_rcu3r2() (machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3R2) +#else +# define machine_is_ubisys_p9_rcu3r2() (0) +#endif + +#ifdef CONFIG_MACH_HERO_ESPRESSO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HERO_ESPRESSO +# endif +# define machine_is_hero_espresso() (machine_arch_type == MACH_TYPE_HERO_ESPRESSO) +#else +# define machine_is_hero_espresso() (0) +#endif + +#ifdef CONFIG_MACH_AFEUSB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AFEUSB +# endif +# define machine_is_afeusb() (machine_arch_type == MACH_TYPE_AFEUSB) +#else +# define machine_is_afeusb() (0) +#endif + +#ifdef CONFIG_MACH_T830 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T830 +# endif +# define machine_is_t830() (machine_arch_type == MACH_TYPE_T830) +#else +# define machine_is_t830() (0) +#endif + +#ifdef CONFIG_MACH_SPD8020_CC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPD8020_CC +# endif +# define machine_is_spd8020_cc() (machine_arch_type == MACH_TYPE_SPD8020_CC) +#else +# define machine_is_spd8020_cc() (0) +#endif + +#ifdef CONFIG_MACH_OM_3D7K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OM_3D7K +# endif +# define machine_is_om_3d7k() (machine_arch_type == MACH_TYPE_OM_3D7K) +#else +# define machine_is_om_3d7k() (0) +#endif + +#ifdef CONFIG_MACH_PICOCOM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOCOM2 +# endif +# define machine_is_picocom2() (machine_arch_type == MACH_TYPE_PICOCOM2) +#else +# define machine_is_picocom2() (0) +#endif + +#ifdef CONFIG_MACH_UWG4MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UWG4MX27 +# endif +# define machine_is_uwg4mx27() (machine_arch_type == MACH_TYPE_UWG4MX27) +#else +# define machine_is_uwg4mx27() (0) +#endif + +#ifdef CONFIG_MACH_UWG4MX31 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UWG4MX31 +# endif +# define machine_is_uwg4mx31() (machine_arch_type == MACH_TYPE_UWG4MX31) +#else +# define machine_is_uwg4mx31() (0) +#endif + +#ifdef CONFIG_MACH_CHERRY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHERRY +# endif +# define machine_is_cherry() (machine_arch_type == MACH_TYPE_CHERRY) +#else +# define machine_is_cherry() (0) +#endif + +#ifdef CONFIG_MACH_MX51_BABBAGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_BABBAGE +# endif +# define machine_is_mx51_babbage() (machine_arch_type == MACH_TYPE_MX51_BABBAGE) +#else +# define machine_is_mx51_babbage() (0) +#endif + +#ifdef CONFIG_MACH_S3C2440TURKIYE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2440TURKIYE +# endif +# define machine_is_s3c2440turkiye() (machine_arch_type == MACH_TYPE_S3C2440TURKIYE) +#else +# define machine_is_s3c2440turkiye() (0) +#endif + +#ifdef CONFIG_MACH_TX37 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX37 +# endif +# define machine_is_tx37() (machine_arch_type == MACH_TYPE_TX37) +#else +# define machine_is_tx37() (0) +#endif + +#ifdef CONFIG_MACH_SBC2800_9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC2800_9G20 +# endif +# define machine_is_sbc2800_9g20() (machine_arch_type == MACH_TYPE_SBC2800_9G20) +#else +# define machine_is_sbc2800_9g20() (0) +#endif + +#ifdef CONFIG_MACH_BENZGLB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZGLB +# endif +# define machine_is_benzglb() (machine_arch_type == MACH_TYPE_BENZGLB) +#else +# define machine_is_benzglb() (0) +#endif + +#ifdef CONFIG_MACH_BENZTD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZTD +# endif +# define machine_is_benztd() (machine_arch_type == MACH_TYPE_BENZTD) +#else +# define machine_is_benztd() (0) +#endif + +#ifdef CONFIG_MACH_CARTESIO_PLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARTESIO_PLUS +# endif +# define machine_is_cartesio_plus() (machine_arch_type == MACH_TYPE_CARTESIO_PLUS) +#else +# define machine_is_cartesio_plus() (0) +#endif + +#ifdef CONFIG_MACH_SOLRAD_G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOLRAD_G20 +# endif +# define machine_is_solrad_g20() (machine_arch_type == MACH_TYPE_SOLRAD_G20) +#else +# define machine_is_solrad_g20() (0) +#endif + +#ifdef CONFIG_MACH_MX27WALLACE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27WALLACE +# endif +# define machine_is_mx27wallace() (machine_arch_type == MACH_TYPE_MX27WALLACE) +#else +# define machine_is_mx27wallace() (0) +#endif + +#ifdef CONFIG_MACH_FMZWEBMODUL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FMZWEBMODUL +# endif +# define machine_is_fmzwebmodul() (machine_arch_type == MACH_TYPE_FMZWEBMODUL) +#else +# define machine_is_fmzwebmodul() (0) +#endif + +#ifdef CONFIG_MACH_RD78X00_MASA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD78X00_MASA +# endif +# define machine_is_rd78x00_masa() (machine_arch_type == MACH_TYPE_RD78X00_MASA) +#else +# define machine_is_rd78x00_masa() (0) +#endif + +#ifdef CONFIG_MACH_SMALLOGGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMALLOGGER +# endif +# define machine_is_smallogger() (machine_arch_type == MACH_TYPE_SMALLOGGER) +#else +# define machine_is_smallogger() (0) +#endif + +#ifdef CONFIG_MACH_CCW9P9215 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9P9215 +# endif +# define machine_is_ccw9p9215() (machine_arch_type == MACH_TYPE_CCW9P9215) +#else +# define machine_is_ccw9p9215() (0) +#endif + +#ifdef CONFIG_MACH_DM355_LEOPARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM355_LEOPARD +# endif +# define machine_is_dm355_leopard() (machine_arch_type == MACH_TYPE_DM355_LEOPARD) +#else +# define machine_is_dm355_leopard() (0) +#endif + +#ifdef CONFIG_MACH_TS219 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS219 +# endif +# define machine_is_ts219() (machine_arch_type == MACH_TYPE_TS219) +#else +# define machine_is_ts219() (0) +#endif + +#ifdef CONFIG_MACH_TNY_A9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNY_A9263 +# endif +# define machine_is_tny_a9263() (machine_arch_type == MACH_TYPE_TNY_A9263) +#else +# define machine_is_tny_a9263() (0) +#endif + +#ifdef CONFIG_MACH_APOLLO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APOLLO +# endif +# define machine_is_apollo() (machine_arch_type == MACH_TYPE_APOLLO) +#else +# define machine_is_apollo() (0) +#endif + +#ifdef CONFIG_MACH_AT91CAP9STK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91CAP9STK +# endif +# define machine_is_at91cap9stk() (machine_arch_type == MACH_TYPE_AT91CAP9STK) +#else +# define machine_is_at91cap9stk() (0) +#endif + +#ifdef CONFIG_MACH_SPC300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPC300 +# endif +# define machine_is_spc300() (machine_arch_type == MACH_TYPE_SPC300) +#else +# define machine_is_spc300() (0) +#endif + +#ifdef CONFIG_MACH_EKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EKO +# endif +# define machine_is_eko() (machine_arch_type == MACH_TYPE_EKO) +#else +# define machine_is_eko() (0) +#endif + +#ifdef CONFIG_MACH_CCW9M2443 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9M2443 +# endif +# define machine_is_ccw9m2443() (machine_arch_type == MACH_TYPE_CCW9M2443) +#else +# define machine_is_ccw9m2443() (0) +#endif + +#ifdef CONFIG_MACH_CCW9M2443JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9M2443JS +# endif +# define machine_is_ccw9m2443js() (machine_arch_type == MACH_TYPE_CCW9M2443JS) +#else +# define machine_is_ccw9m2443js() (0) +#endif + +#ifdef CONFIG_MACH_M2M_ROUTER_DEVICE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M2M_ROUTER_DEVICE +# endif +# define machine_is_m2m_router_device() (machine_arch_type == MACH_TYPE_M2M_ROUTER_DEVICE) +#else +# define machine_is_m2m_router_device() (0) +#endif + +#ifdef CONFIG_MACH_STAR9104NAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAR9104NAS +# endif +# define machine_is_str9104nas() (machine_arch_type == MACH_TYPE_STAR9104NAS) +#else +# define machine_is_str9104nas() (0) +#endif + +#ifdef CONFIG_MACH_PCA100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCA100 +# endif +# define machine_is_pca100() (machine_arch_type == MACH_TYPE_PCA100) +#else +# define machine_is_pca100() (0) +#endif + +#ifdef CONFIG_MACH_Z3_DM365_MOD_01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Z3_DM365_MOD_01 +# endif +# define machine_is_z3_dm365_mod_01() (machine_arch_type == MACH_TYPE_Z3_DM365_MOD_01) +#else +# define machine_is_z3_dm365_mod_01() (0) +#endif + +#ifdef CONFIG_MACH_HIPOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIPOX +# endif +# define machine_is_hipox() (machine_arch_type == MACH_TYPE_HIPOX) +#else +# define machine_is_hipox() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_PITEDS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PITEDS +# endif +# define machine_is_omap3_piteds() (machine_arch_type == MACH_TYPE_OMAP3_PITEDS) +#else +# define machine_is_omap3_piteds() (0) +#endif + +#ifdef CONFIG_MACH_BM150R +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BM150R +# endif +# define machine_is_bm150r() (machine_arch_type == MACH_TYPE_BM150R) +#else +# define machine_is_bm150r() (0) +#endif + +#ifdef CONFIG_MACH_TBONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TBONE +# endif +# define machine_is_tbone() (machine_arch_type == MACH_TYPE_TBONE) +#else +# define machine_is_tbone() (0) +#endif + +#ifdef CONFIG_MACH_MERLIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MERLIN +# endif +# define machine_is_merlin() (machine_arch_type == MACH_TYPE_MERLIN) +#else +# define machine_is_merlin() (0) +#endif + +#ifdef CONFIG_MACH_FALCON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FALCON +# endif +# define machine_is_falcon() (machine_arch_type == MACH_TYPE_FALCON) +#else +# define machine_is_falcon() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DA850_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DA850_EVM +# endif +# define machine_is_davinci_da850_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) +#else +# define machine_is_davinci_da850_evm() (0) +#endif + +#ifdef CONFIG_MACH_S5P6440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5P6440 +# endif +# define machine_is_s5p6440() (machine_arch_type == MACH_TYPE_S5P6440) +#else +# define machine_is_s5p6440() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G10EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G10EK +# endif +# define machine_is_at91sam9g10ek() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK) +#else +# define machine_is_at91sam9g10ek() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_4430SDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_4430SDP +# endif +# define machine_is_omap_4430sdp() (machine_arch_type == MACH_TYPE_OMAP_4430SDP) +#else +# define machine_is_omap_4430sdp() (0) +#endif + +#ifdef CONFIG_MACH_LPC313X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC313X +# endif +# define machine_is_lpc313x() (machine_arch_type == MACH_TYPE_LPC313X) +#else +# define machine_is_lpc313x() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_ZN5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_ZN5 +# endif +# define machine_is_magx_zn5() (machine_arch_type == MACH_TYPE_MAGX_ZN5) +#else +# define machine_is_magx_zn5() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_EM30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_EM30 +# endif +# define machine_is_magx_em30() (machine_arch_type == MACH_TYPE_MAGX_EM30) +#else +# define machine_is_magx_em30() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_VE66 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_VE66 +# endif +# define machine_is_magx_ve66() (machine_arch_type == MACH_TYPE_MAGX_VE66) +#else +# define machine_is_magx_ve66() (0) +#endif + +#ifdef CONFIG_MACH_MEESC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEESC +# endif +# define machine_is_meesc() (machine_arch_type == MACH_TYPE_MEESC) +#else +# define machine_is_meesc() (0) +#endif + +#ifdef CONFIG_MACH_OTC570 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTC570 +# endif +# define machine_is_otc570() (machine_arch_type == MACH_TYPE_OTC570) +#else +# define machine_is_otc570() (0) +#endif + +#ifdef CONFIG_MACH_BCU2412 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCU2412 +# endif +# define machine_is_bcu2412() (machine_arch_type == MACH_TYPE_BCU2412) +#else +# define machine_is_bcu2412() (0) +#endif + +#ifdef CONFIG_MACH_BEACON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEACON +# endif +# define machine_is_beacon() (machine_arch_type == MACH_TYPE_BEACON) +#else +# define machine_is_beacon() (0) +#endif + +#ifdef CONFIG_MACH_ACTIA_TGW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTIA_TGW +# endif +# define machine_is_actia_tgw() (machine_arch_type == MACH_TYPE_ACTIA_TGW) +#else +# define machine_is_actia_tgw() (0) +#endif + +#ifdef CONFIG_MACH_E4430 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E4430 +# endif +# define machine_is_e4430() (machine_arch_type == MACH_TYPE_E4430) +#else +# define machine_is_e4430() (0) +#endif + +#ifdef CONFIG_MACH_QL300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QL300 +# endif +# define machine_is_ql300() (machine_arch_type == MACH_TYPE_QL300) +#else +# define machine_is_ql300() (0) +#endif + +#ifdef CONFIG_MACH_BTMAVB101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTMAVB101 +# endif +# define machine_is_btmavb101() (machine_arch_type == MACH_TYPE_BTMAVB101) +#else +# define machine_is_btmavb101() (0) +#endif + +#ifdef CONFIG_MACH_BTMAWB101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTMAWB101 +# endif +# define machine_is_btmawb101() (machine_arch_type == MACH_TYPE_BTMAWB101) +#else +# define machine_is_btmawb101() (0) +#endif + +#ifdef CONFIG_MACH_SQ201 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SQ201 +# endif +# define machine_is_sq201() (machine_arch_type == MACH_TYPE_SQ201) +#else +# define machine_is_sq201() (0) +#endif + +#ifdef CONFIG_MACH_QUATRO45XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUATRO45XX +# endif +# define machine_is_quatro45xx() (machine_arch_type == MACH_TYPE_QUATRO45XX) +#else +# define machine_is_quatro45xx() (0) +#endif + +#ifdef CONFIG_MACH_OPENPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENPAD +# endif +# define machine_is_openpad() (machine_arch_type == MACH_TYPE_OPENPAD) +#else +# define machine_is_openpad() (0) +#endif + +#ifdef CONFIG_MACH_TX25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX25 +# endif +# define machine_is_tx25() (machine_arch_type == MACH_TYPE_TX25) +#else +# define machine_is_tx25() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_TORPEDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_TORPEDO +# endif +# define machine_is_omap3_torpedo() (machine_arch_type == MACH_TYPE_OMAP3_TORPEDO) +#else +# define machine_is_omap3_torpedo() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL_K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL_K +# endif +# define machine_is_htcraphael_k() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_K) +#else +# define machine_is_htcraphael_k() (0) +#endif + +#ifdef CONFIG_MACH_LAL43 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LAL43 +# endif +# define machine_is_lal43() (machine_arch_type == MACH_TYPE_LAL43) +#else +# define machine_is_lal43() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA500 +# endif +# define machine_is_htcraphael_cdma500() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA500) +#else +# define machine_is_htcraphael_cdma500() (0) +#endif + +#ifdef CONFIG_MACH_ANW6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANW6410 +# endif +# define machine_is_anw6410() (machine_arch_type == MACH_TYPE_ANW6410) +#else +# define machine_is_anw6410() (0) +#endif + +#ifdef CONFIG_MACH_HTCPROPHET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPROPHET +# endif +# define machine_is_htcprophet() (machine_arch_type == MACH_TYPE_HTCPROPHET) +#else +# define machine_is_htcprophet() (0) +#endif + +#ifdef CONFIG_MACH_CFA_10022 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CFA_10022 +# endif +# define machine_is_cfa_10022() (machine_arch_type == MACH_TYPE_CFA_10022) +#else +# define machine_is_cfa_10022() (0) +#endif + +#ifdef CONFIG_MACH_IMX27_VISSTRIM_M10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27_VISSTRIM_M10 +# endif +# define machine_is_imx27_visstrim_m10() (machine_arch_type == MACH_TYPE_IMX27_VISSTRIM_M10) +#else +# define machine_is_imx27_visstrim_m10() (0) +#endif + +#ifdef CONFIG_MACH_PX2IMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PX2IMX27 +# endif +# define machine_is_px2imx27() (machine_arch_type == MACH_TYPE_PX2IMX27) +#else +# define machine_is_px2imx27() (0) +#endif + +#ifdef CONFIG_MACH_STM3210E_EVAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STM3210E_EVAL +# endif +# define machine_is_stm3210e_eval() (machine_arch_type == MACH_TYPE_STM3210E_EVAL) +#else +# define machine_is_stm3210e_eval() (0) +#endif + +#ifdef CONFIG_MACH_DVS10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DVS10 +# endif +# define machine_is_dvs10() (machine_arch_type == MACH_TYPE_DVS10) +#else +# define machine_is_dvs10() (0) +#endif + +#ifdef CONFIG_MACH_PORTUXG20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PORTUXG20 +# endif +# define machine_is_portuxg20() (machine_arch_type == MACH_TYPE_PORTUXG20) +#else +# define machine_is_portuxg20() (0) +#endif + +#ifdef CONFIG_MACH_ARM_SPV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM_SPV +# endif +# define machine_is_arm_spv() (machine_arch_type == MACH_TYPE_ARM_SPV) +#else +# define machine_is_arm_spv() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC110 +# endif +# define machine_is_smdkc110() (machine_arch_type == MACH_TYPE_SMDKC110) +#else +# define machine_is_smdkc110() (0) +#endif + +#ifdef CONFIG_MACH_CABESPRESSO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CABESPRESSO +# endif +# define machine_is_cabespresso() (machine_arch_type == MACH_TYPE_CABESPRESSO) +#else +# define machine_is_cabespresso() (0) +#endif + +#ifdef CONFIG_MACH_HMC800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMC800 +# endif +# define machine_is_hmc800() (machine_arch_type == MACH_TYPE_HMC800) +#else +# define machine_is_hmc800() (0) +#endif + +#ifdef CONFIG_MACH_SHOLES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHOLES +# endif +# define machine_is_sholes() (machine_arch_type == MACH_TYPE_SHOLES) +#else +# define machine_is_sholes() (0) +#endif + +#ifdef CONFIG_MACH_BTMXC31 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTMXC31 +# endif +# define machine_is_btmxc31() (machine_arch_type == MACH_TYPE_BTMXC31) +#else +# define machine_is_btmxc31() (0) +#endif + +#ifdef CONFIG_MACH_DT501 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DT501 +# endif +# define machine_is_dt501() (machine_arch_type == MACH_TYPE_DT501) +#else +# define machine_is_dt501() (0) +#endif + +#ifdef CONFIG_MACH_KTX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KTX +# endif +# define machine_is_ktx() (machine_arch_type == MACH_TYPE_KTX) +#else +# define machine_is_ktx() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3517EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3517EVM +# endif +# define machine_is_omap3517evm() (machine_arch_type == MACH_TYPE_OMAP3517EVM) +#else +# define machine_is_omap3517evm() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_V2 +# endif +# define machine_is_netspace_v2() (machine_arch_type == MACH_TYPE_NETSPACE_V2) +#else +# define machine_is_netspace_v2() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_MAX_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_MAX_V2 +# endif +# define machine_is_netspace_max_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MAX_V2) +#else +# define machine_is_netspace_max_v2() (0) +#endif + +#ifdef CONFIG_MACH_D2NET_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D2NET_V2 +# endif +# define machine_is_d2net_v2() (machine_arch_type == MACH_TYPE_D2NET_V2) +#else +# define machine_is_d2net_v2() (0) +#endif + +#ifdef CONFIG_MACH_NET2BIG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET2BIG_V2 +# endif +# define machine_is_net2big_v2() (machine_arch_type == MACH_TYPE_NET2BIG_V2) +#else +# define machine_is_net2big_v2() (0) +#endif + +#ifdef CONFIG_MACH_NET4BIG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET4BIG_V2 +# endif +# define machine_is_net4big_v2() (machine_arch_type == MACH_TYPE_NET4BIG_V2) +#else +# define machine_is_net4big_v2() (0) +#endif + +#ifdef CONFIG_MACH_NET5BIG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET5BIG_V2 +# endif +# define machine_is_net5big_v2() (machine_arch_type == MACH_TYPE_NET5BIG_V2) +#else +# define machine_is_net5big_v2() (0) +#endif + +#ifdef CONFIG_MACH_ENDB2443 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENDB2443 +# endif +# define machine_is_endb2443() (machine_arch_type == MACH_TYPE_ENDB2443) +#else +# define machine_is_endb2443() (0) +#endif + +#ifdef CONFIG_MACH_INETSPACE_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INETSPACE_V2 +# endif +# define machine_is_inetspace_v2() (machine_arch_type == MACH_TYPE_INETSPACE_V2) +#else +# define machine_is_inetspace_v2() (0) +#endif + +#ifdef CONFIG_MACH_TROS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TROS +# endif +# define machine_is_tros() (machine_arch_type == MACH_TYPE_TROS) +#else +# define machine_is_tros() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_HOMER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_HOMER +# endif +# define machine_is_pelco_homer() (machine_arch_type == MACH_TYPE_PELCO_HOMER) +#else +# define machine_is_pelco_homer() (0) +#endif + +#ifdef CONFIG_MACH_OFSP8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OFSP8 +# endif +# define machine_is_ofsp8() (machine_arch_type == MACH_TYPE_OFSP8) +#else +# define machine_is_ofsp8() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G45EKES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G45EKES +# endif +# define machine_is_at91sam9g45ekes() (machine_arch_type == MACH_TYPE_AT91SAM9G45EKES) +#else +# define machine_is_at91sam9g45ekes() (0) +#endif + +#ifdef CONFIG_MACH_GUF_CUPID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUF_CUPID +# endif +# define machine_is_guf_cupid() (machine_arch_type == MACH_TYPE_GUF_CUPID) +#else +# define machine_is_guf_cupid() (0) +#endif + +#ifdef CONFIG_MACH_EAB1R +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EAB1R +# endif +# define machine_is_eab1r() (machine_arch_type == MACH_TYPE_EAB1R) +#else +# define machine_is_eab1r() (0) +#endif + +#ifdef CONFIG_MACH_DESIREC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DESIREC +# endif +# define machine_is_desirec() (machine_arch_type == MACH_TYPE_DESIREC) +#else +# define machine_is_desirec() (0) +#endif + +#ifdef CONFIG_MACH_CORDOBA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORDOBA +# endif +# define machine_is_cordoba() (machine_arch_type == MACH_TYPE_CORDOBA) +#else +# define machine_is_cordoba() (0) +#endif + +#ifdef CONFIG_MACH_IRVINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IRVINE +# endif +# define machine_is_irvine() (machine_arch_type == MACH_TYPE_IRVINE) +#else +# define machine_is_irvine() (0) +#endif + +#ifdef CONFIG_MACH_SFF772 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SFF772 +# endif +# define machine_is_sff772() (machine_arch_type == MACH_TYPE_SFF772) +#else +# define machine_is_sff772() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_MILANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_MILANO +# endif +# define machine_is_pelco_milano() (machine_arch_type == MACH_TYPE_PELCO_MILANO) +#else +# define machine_is_pelco_milano() (0) +#endif + +#ifdef CONFIG_MACH_PC7302 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7302 +# endif +# define machine_is_pc7302() (machine_arch_type == MACH_TYPE_PC7302) +#else +# define machine_is_pc7302() (0) +#endif + +#ifdef CONFIG_MACH_BIP6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIP6000 +# endif +# define machine_is_bip6000() (machine_arch_type == MACH_TYPE_BIP6000) +#else +# define machine_is_bip6000() (0) +#endif + +#ifdef CONFIG_MACH_SILVERMOON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SILVERMOON +# endif +# define machine_is_silvermoon() (machine_arch_type == MACH_TYPE_SILVERMOON) +#else +# define machine_is_silvermoon() (0) +#endif + +#ifdef CONFIG_MACH_VC0830 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC0830 +# endif +# define machine_is_vc0830() (machine_arch_type == MACH_TYPE_VC0830) +#else +# define machine_is_vc0830() (0) +#endif + +#ifdef CONFIG_MACH_DT430 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DT430 +# endif +# define machine_is_dt430() (machine_arch_type == MACH_TYPE_DT430) +#else +# define machine_is_dt430() (0) +#endif + +#ifdef CONFIG_MACH_JI42PF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JI42PF +# endif +# define machine_is_ji42pf() (machine_arch_type == MACH_TYPE_JI42PF) +#else +# define machine_is_ji42pf() (0) +#endif + +#ifdef CONFIG_MACH_GNET_KSM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_KSM +# endif +# define machine_is_gnet_ksm() (machine_arch_type == MACH_TYPE_GNET_KSM) +#else +# define machine_is_gnet_ksm() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGM +# endif +# define machine_is_gnet_sgm() (machine_arch_type == MACH_TYPE_GNET_SGM) +#else +# define machine_is_gnet_sgm() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGR +# endif +# define machine_is_gnet_sgr() (machine_arch_type == MACH_TYPE_GNET_SGR) +#else +# define machine_is_gnet_sgr() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_ICETEKEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_ICETEKEVM +# endif +# define machine_is_omap3_icetekevm() (machine_arch_type == MACH_TYPE_OMAP3_ICETEKEVM) +#else +# define machine_is_omap3_icetekevm() (0) +#endif + +#ifdef CONFIG_MACH_PNP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNP +# endif +# define machine_is_pnp() (machine_arch_type == MACH_TYPE_PNP) +#else +# define machine_is_pnp() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY_K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY_K +# endif +# define machine_is_ctera_2bay_k() (machine_arch_type == MACH_TYPE_CTERA_2BAY_K) +#else +# define machine_is_ctera_2bay_k() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY_U +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY_U +# endif +# define machine_is_ctera_2bay_u() (machine_arch_type == MACH_TYPE_CTERA_2BAY_U) +#else +# define machine_is_ctera_2bay_u() (0) +#endif + +#ifdef CONFIG_MACH_SAS_C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAS_C +# endif +# define machine_is_sas_c() (machine_arch_type == MACH_TYPE_SAS_C) +#else +# define machine_is_sas_c() (0) +#endif + +#ifdef CONFIG_MACH_VMA2315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMA2315 +# endif +# define machine_is_vma2315() (machine_arch_type == MACH_TYPE_VMA2315) +#else +# define machine_is_vma2315() (0) +#endif + +#ifdef CONFIG_MACH_VCS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VCS +# endif +# define machine_is_vcs() (machine_arch_type == MACH_TYPE_VCS) +#else +# define machine_is_vcs() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR600 +# endif +# define machine_is_spear600() (machine_arch_type == MACH_TYPE_SPEAR600) +#else +# define machine_is_spear600() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR300 +# endif +# define machine_is_spear300() (machine_arch_type == MACH_TYPE_SPEAR300) +#else +# define machine_is_spear300() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR1300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR1300 +# endif +# define machine_is_spear1300() (machine_arch_type == MACH_TYPE_SPEAR1300) +#else +# define machine_is_spear1300() (0) +#endif + +#ifdef CONFIG_MACH_LILLY1131 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LILLY1131 +# endif +# define machine_is_lilly1131() (machine_arch_type == MACH_TYPE_LILLY1131) +#else +# define machine_is_lilly1131() (0) +#endif + +#ifdef CONFIG_MACH_ARVOO_AX301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARVOO_AX301 +# endif +# define machine_is_arvoo_ax301() (machine_arch_type == MACH_TYPE_ARVOO_AX301) +#else +# define machine_is_arvoo_ax301() (0) +#endif + +#ifdef CONFIG_MACH_MAPPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAPPHONE +# endif +# define machine_is_mapphone() (machine_arch_type == MACH_TYPE_MAPPHONE) +#else +# define machine_is_mapphone() (0) +#endif + +#ifdef CONFIG_MACH_LEGEND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEGEND +# endif +# define machine_is_legend() (machine_arch_type == MACH_TYPE_LEGEND) +#else +# define machine_is_legend() (0) +#endif + +#ifdef CONFIG_MACH_SALSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SALSA +# endif +# define machine_is_salsa() (machine_arch_type == MACH_TYPE_SALSA) +#else +# define machine_is_salsa() (0) +#endif + +#ifdef CONFIG_MACH_LOUNGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOUNGE +# endif +# define machine_is_lounge() (machine_arch_type == MACH_TYPE_LOUNGE) +#else +# define machine_is_lounge() (0) +#endif + +#ifdef CONFIG_MACH_VISION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VISION +# endif +# define machine_is_vision() (machine_arch_type == MACH_TYPE_VISION) +#else +# define machine_is_vision() (0) +#endif + +#ifdef CONFIG_MACH_VMB20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMB20 +# endif +# define machine_is_vmb20() (machine_arch_type == MACH_TYPE_VMB20) +#else +# define machine_is_vmb20() (0) +#endif + +#ifdef CONFIG_MACH_HY2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY2410 +# endif +# define machine_is_hy2410() (machine_arch_type == MACH_TYPE_HY2410) +#else +# define machine_is_hy2410() (0) +#endif + +#ifdef CONFIG_MACH_HY9315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9315 +# endif +# define machine_is_hy9315() (machine_arch_type == MACH_TYPE_HY9315) +#else +# define machine_is_hy9315() (0) +#endif + +#ifdef CONFIG_MACH_BULLWINKLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BULLWINKLE +# endif +# define machine_is_bullwinkle() (machine_arch_type == MACH_TYPE_BULLWINKLE) +#else +# define machine_is_bullwinkle() (0) +#endif + +#ifdef CONFIG_MACH_ARM_ULTIMATOR2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM_ULTIMATOR2 +# endif +# define machine_is_arm_ultimator2() (machine_arch_type == MACH_TYPE_ARM_ULTIMATOR2) +#else +# define machine_is_arm_ultimator2() (0) +#endif + +#ifdef CONFIG_MACH_VS_V210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VS_V210 +# endif +# define machine_is_vs_v210() (machine_arch_type == MACH_TYPE_VS_V210) +#else +# define machine_is_vs_v210() (0) +#endif + +#ifdef CONFIG_MACH_VS_V212 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VS_V212 +# endif +# define machine_is_vs_v212() (machine_arch_type == MACH_TYPE_VS_V212) +#else +# define machine_is_vs_v212() (0) +#endif + +#ifdef CONFIG_MACH_HMT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMT +# endif +# define machine_is_hmt() (machine_arch_type == MACH_TYPE_HMT) +#else +# define machine_is_hmt() (0) +#endif + +#ifdef CONFIG_MACH_SUEN3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUEN3 +# endif +# define machine_is_suen3() (machine_arch_type == MACH_TYPE_SUEN3) +#else +# define machine_is_suen3() (0) +#endif + +#ifdef CONFIG_MACH_VESPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VESPER +# endif +# define machine_is_vesper() (machine_arch_type == MACH_TYPE_VESPER) +#else +# define machine_is_vesper() (0) +#endif + +#ifdef CONFIG_MACH_STR9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STR9 +# endif +# define machine_is_str9() (machine_arch_type == MACH_TYPE_STR9) +#else +# define machine_is_str9() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_WL_FF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_WL_FF +# endif +# define machine_is_omap3_wl_ff() (machine_arch_type == MACH_TYPE_OMAP3_WL_FF) +#else +# define machine_is_omap3_wl_ff() (0) +#endif + +#ifdef CONFIG_MACH_SIMCOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMCOM +# endif +# define machine_is_simcom() (machine_arch_type == MACH_TYPE_SIMCOM) +#else +# define machine_is_simcom() (0) +#endif + +#ifdef CONFIG_MACH_MCWEBIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCWEBIO +# endif +# define machine_is_mcwebio() (machine_arch_type == MACH_TYPE_MCWEBIO) +#else +# define machine_is_mcwebio() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_PHRAZER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PHRAZER +# endif +# define machine_is_omap3_phrazer() (machine_arch_type == MACH_TYPE_OMAP3_PHRAZER) +#else +# define machine_is_omap3_phrazer() (0) +#endif + +#ifdef CONFIG_MACH_DARWIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DARWIN +# endif +# define machine_is_darwin() (machine_arch_type == MACH_TYPE_DARWIN) +#else +# define machine_is_darwin() (0) +#endif + +#ifdef CONFIG_MACH_ORATISCOMU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISCOMU +# endif +# define machine_is_oratiscomu() (machine_arch_type == MACH_TYPE_ORATISCOMU) +#else +# define machine_is_oratiscomu() (0) +#endif + +#ifdef CONFIG_MACH_RTSBC20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTSBC20 +# endif +# define machine_is_rtsbc20() (machine_arch_type == MACH_TYPE_RTSBC20) +#else +# define machine_is_rtsbc20() (0) +#endif + +#ifdef CONFIG_MACH_I780 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I780 +# endif +# define machine_is_sgh_i780() (machine_arch_type == MACH_TYPE_I780) +#else +# define machine_is_sgh_i780() (0) +#endif + +#ifdef CONFIG_MACH_GEMINI324 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMINI324 +# endif +# define machine_is_gemini324() (machine_arch_type == MACH_TYPE_GEMINI324) +#else +# define machine_is_gemini324() (0) +#endif + +#ifdef CONFIG_MACH_ORATISLAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISLAN +# endif +# define machine_is_oratislan() (machine_arch_type == MACH_TYPE_ORATISLAN) +#else +# define machine_is_oratislan() (0) +#endif + +#ifdef CONFIG_MACH_ORATISALOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISALOG +# endif +# define machine_is_oratisalog() (machine_arch_type == MACH_TYPE_ORATISALOG) +#else +# define machine_is_oratisalog() (0) +#endif + +#ifdef CONFIG_MACH_ORATISMADI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISMADI +# endif +# define machine_is_oratismadi() (machine_arch_type == MACH_TYPE_ORATISMADI) +#else +# define machine_is_oratismadi() (0) +#endif + +#ifdef CONFIG_MACH_ORATISOT16 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISOT16 +# endif +# define machine_is_oratisot16() (machine_arch_type == MACH_TYPE_ORATISOT16) +#else +# define machine_is_oratisot16() (0) +#endif + +#ifdef CONFIG_MACH_ORATISDESK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISDESK +# endif +# define machine_is_oratisdesk() (machine_arch_type == MACH_TYPE_ORATISDESK) +#else +# define machine_is_oratisdesk() (0) +#endif + +#ifdef CONFIG_MACH_VEXPRESS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VEXPRESS +# endif +# define machine_is_vexpress() (machine_arch_type == MACH_TYPE_VEXPRESS) +#else +# define machine_is_vexpress() (0) +#endif + +#ifdef CONFIG_MACH_SINTEXO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SINTEXO +# endif +# define machine_is_sintexo() (machine_arch_type == MACH_TYPE_SINTEXO) +#else +# define machine_is_sintexo() (0) +#endif + +#ifdef CONFIG_MACH_CM3389 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM3389 +# endif +# define machine_is_cm3389() (machine_arch_type == MACH_TYPE_CM3389) +#else +# define machine_is_cm3389() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_CIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_CIO +# endif +# define machine_is_omap3_cio() (machine_arch_type == MACH_TYPE_OMAP3_CIO) +#else +# define machine_is_omap3_cio() (0) +#endif + +#ifdef CONFIG_MACH_SGH_I900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGH_I900 +# endif +# define machine_is_sgh_i900() (machine_arch_type == MACH_TYPE_SGH_I900) +#else +# define machine_is_sgh_i900() (0) +#endif + +#ifdef CONFIG_MACH_BST100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BST100 +# endif +# define machine_is_bst100() (machine_arch_type == MACH_TYPE_BST100) +#else +# define machine_is_bst100() (0) +#endif + +#ifdef CONFIG_MACH_PASSION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSION +# endif +# define machine_is_passion() (machine_arch_type == MACH_TYPE_PASSION) +#else +# define machine_is_passion() (0) +#endif + +#ifdef CONFIG_MACH_INDESIGN_AT91SAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INDESIGN_AT91SAM +# endif +# define machine_is_indesign_at91sam() (machine_arch_type == MACH_TYPE_INDESIGN_AT91SAM) +#else +# define machine_is_indesign_at91sam() (0) +#endif + +#ifdef CONFIG_MACH_C4_BADGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C4_BADGER +# endif +# define machine_is_c4_badger() (machine_arch_type == MACH_TYPE_C4_BADGER) +#else +# define machine_is_c4_badger() (0) +#endif + +#ifdef CONFIG_MACH_C4_VIPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C4_VIPER +# endif +# define machine_is_c4_viper() (machine_arch_type == MACH_TYPE_C4_VIPER) +#else +# define machine_is_c4_viper() (0) +#endif + +#ifdef CONFIG_MACH_D2NET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D2NET +# endif +# define machine_is_d2net() (machine_arch_type == MACH_TYPE_D2NET) +#else +# define machine_is_d2net() (0) +#endif + +#ifdef CONFIG_MACH_BIGDISK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIGDISK +# endif +# define machine_is_bigdisk() (machine_arch_type == MACH_TYPE_BIGDISK) +#else +# define machine_is_bigdisk() (0) +#endif + +#ifdef CONFIG_MACH_NOTALVISION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOTALVISION +# endif +# define machine_is_notalvision() (machine_arch_type == MACH_TYPE_NOTALVISION) +#else +# define machine_is_notalvision() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_KBOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_KBOC +# endif +# define machine_is_omap3_kboc() (machine_arch_type == MACH_TYPE_OMAP3_KBOC) +#else +# define machine_is_omap3_kboc() (0) +#endif + +#ifdef CONFIG_MACH_CYCLONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYCLONE +# endif +# define machine_is_cyclone() (machine_arch_type == MACH_TYPE_CYCLONE) +#else +# define machine_is_cyclone() (0) +#endif + +#ifdef CONFIG_MACH_NINJA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NINJA +# endif +# define machine_is_ninja() (machine_arch_type == MACH_TYPE_NINJA) +#else +# define machine_is_ninja() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20EK_2MMC +# endif +# define machine_is_at91sam9g20ek_2mmc() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC) +#else +# define machine_is_at91sam9g20ek_2mmc() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING +# endif +# define machine_is_bcmring() (machine_arch_type == MACH_TYPE_BCMRING) +#else +# define machine_is_bcmring() (0) +#endif + +#ifdef CONFIG_MACH_RESOL_DL2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RESOL_DL2 +# endif +# define machine_is_resol_dl2() (machine_arch_type == MACH_TYPE_RESOL_DL2) +#else +# define machine_is_resol_dl2() (0) +#endif + +#ifdef CONFIG_MACH_IFOSW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IFOSW +# endif +# define machine_is_ifosw() (machine_arch_type == MACH_TYPE_IFOSW) +#else +# define machine_is_ifosw() (0) +#endif + +#ifdef CONFIG_MACH_HTCRHODIUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRHODIUM +# endif +# define machine_is_htcrhodium() (machine_arch_type == MACH_TYPE_HTCRHODIUM) +#else +# define machine_is_htcrhodium() (0) +#endif + +#ifdef CONFIG_MACH_HTCTOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCTOPAZ +# endif +# define machine_is_htctopaz() (machine_arch_type == MACH_TYPE_HTCTOPAZ) +#else +# define machine_is_htctopaz() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX504 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX504 +# endif +# define machine_is_matrix504() (machine_arch_type == MACH_TYPE_MATRIX504) +#else +# define machine_is_matrix504() (0) +#endif + +#ifdef CONFIG_MACH_MRFSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MRFSA +# endif +# define machine_is_mrfsa() (machine_arch_type == MACH_TYPE_MRFSA) +#else +# define machine_is_mrfsa() (0) +#endif + +#ifdef CONFIG_MACH_SC_P270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SC_P270 +# endif +# define machine_is_sc_p270() (machine_arch_type == MACH_TYPE_SC_P270) +#else +# define machine_is_sc_p270() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS5_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS5_EVB +# endif +# define machine_is_atlas5_evb() (machine_arch_type == MACH_TYPE_ATLAS5_EVB) +#else +# define machine_is_atlas5_evb() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_LOBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_LOBOX +# endif +# define machine_is_pelco_lobox() (machine_arch_type == MACH_TYPE_PELCO_LOBOX) +#else +# define machine_is_pelco_lobox() (0) +#endif + +#ifdef CONFIG_MACH_DILAX_PCU200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DILAX_PCU200 +# endif +# define machine_is_dilax_pcu200() (machine_arch_type == MACH_TYPE_DILAX_PCU200) +#else +# define machine_is_dilax_pcu200() (0) +#endif + +#ifdef CONFIG_MACH_LEONARDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEONARDO +# endif +# define machine_is_leonardo() (machine_arch_type == MACH_TYPE_LEONARDO) +#else +# define machine_is_leonardo() (0) +#endif + +#ifdef CONFIG_MACH_ZORAN_APPROACH7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZORAN_APPROACH7 +# endif +# define machine_is_zoran_approach7() (machine_arch_type == MACH_TYPE_ZORAN_APPROACH7) +#else +# define machine_is_zoran_approach7() (0) +#endif + +#ifdef CONFIG_MACH_DP6XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DP6XX +# endif +# define machine_is_dp6xx() (machine_arch_type == MACH_TYPE_DP6XX) +#else +# define machine_is_dp6xx() (0) +#endif + +#ifdef CONFIG_MACH_BCM2153_VESPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM2153_VESPER +# endif +# define machine_is_bcm2153_vesper() (machine_arch_type == MACH_TYPE_BCM2153_VESPER) +#else +# define machine_is_bcm2153_vesper() (0) +#endif + +#ifdef CONFIG_MACH_MAHIMAHI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAHIMAHI +# endif +# define machine_is_mahimahi() (machine_arch_type == MACH_TYPE_MAHIMAHI) +#else +# define machine_is_mahimahi() (0) +#endif + +#ifdef CONFIG_MACH_CLICKC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLICKC +# endif +# define machine_is_clickc() (machine_arch_type == MACH_TYPE_CLICKC) +#else +# define machine_is_clickc() (0) +#endif + +#ifdef CONFIG_MACH_ZB_GATEWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZB_GATEWAY +# endif +# define machine_is_zb_gateway() (machine_arch_type == MACH_TYPE_ZB_GATEWAY) +#else +# define machine_is_zb_gateway() (0) +#endif + +#ifdef CONFIG_MACH_TAZCARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZCARD +# endif +# define machine_is_tazcard() (machine_arch_type == MACH_TYPE_TAZCARD) +#else +# define machine_is_tazcard() (0) +#endif + +#ifdef CONFIG_MACH_TAZDEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZDEV +# endif +# define machine_is_tazdev() (machine_arch_type == MACH_TYPE_TAZDEV) +#else +# define machine_is_tazdev() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_CB_ARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_CB_ARM +# endif +# define machine_is_annax_cb_arm() (machine_arch_type == MACH_TYPE_ANNAX_CB_ARM) +#else +# define machine_is_annax_cb_arm() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_DM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_DM3 +# endif +# define machine_is_annax_dm3() (machine_arch_type == MACH_TYPE_ANNAX_DM3) +#else +# define machine_is_annax_dm3() (0) +#endif + +#ifdef CONFIG_MACH_CEREBRIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEREBRIC +# endif +# define machine_is_cerebric() (machine_arch_type == MACH_TYPE_CEREBRIC) +#else +# define machine_is_cerebric() (0) +#endif + +#ifdef CONFIG_MACH_ORCA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORCA +# endif +# define machine_is_orca() (machine_arch_type == MACH_TYPE_ORCA) +#else +# define machine_is_orca() (0) +#endif + +#ifdef CONFIG_MACH_PC9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC9260 +# endif +# define machine_is_pc9260() (machine_arch_type == MACH_TYPE_PC9260) +#else +# define machine_is_pc9260() (0) +#endif + +#ifdef CONFIG_MACH_EMS285A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMS285A +# endif +# define machine_is_ems285a() (machine_arch_type == MACH_TYPE_EMS285A) +#else +# define machine_is_ems285a() (0) +#endif + +#ifdef CONFIG_MACH_GEC2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEC2410 +# endif +# define machine_is_gec2410() (machine_arch_type == MACH_TYPE_GEC2410) +#else +# define machine_is_gec2410() (0) +#endif + +#ifdef CONFIG_MACH_GEC2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEC2440 +# endif +# define machine_is_gec2440() (machine_arch_type == MACH_TYPE_GEC2440) +#else +# define machine_is_gec2440() (0) +#endif + +#ifdef CONFIG_MACH_ARCH_MW903 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCH_MW903 +# endif +# define machine_is_mw903() (machine_arch_type == MACH_TYPE_ARCH_MW903) +#else +# define machine_is_mw903() (0) +#endif + +#ifdef CONFIG_MACH_MW2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW2440 +# endif +# define machine_is_mw2440() (machine_arch_type == MACH_TYPE_MW2440) +#else +# define machine_is_mw2440() (0) +#endif + +#ifdef CONFIG_MACH_ECAC2378 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECAC2378 +# endif +# define machine_is_ecac2378() (machine_arch_type == MACH_TYPE_ECAC2378) +#else +# define machine_is_ecac2378() (0) +#endif + +#ifdef CONFIG_MACH_TAZKIOSK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZKIOSK +# endif +# define machine_is_tazkiosk() (machine_arch_type == MACH_TYPE_TAZKIOSK) +#else +# define machine_is_tazkiosk() (0) +#endif + +#ifdef CONFIG_MACH_WHITERABBIT_MCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITERABBIT_MCH +# endif +# define machine_is_whiterabbit_mch() (machine_arch_type == MACH_TYPE_WHITERABBIT_MCH) +#else +# define machine_is_whiterabbit_mch() (0) +#endif + +#ifdef CONFIG_MACH_SBOX9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBOX9263 +# endif +# define machine_is_sbox9263() (machine_arch_type == MACH_TYPE_SBOX9263) +#else +# define machine_is_sbox9263() (0) +#endif + +#ifdef CONFIG_MACH_OREO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OREO +# endif +# define machine_is_oreo_camera() (machine_arch_type == MACH_TYPE_OREO) +#else +# define machine_is_oreo_camera() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6442 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6442 +# endif +# define machine_is_smdk6442() (machine_arch_type == MACH_TYPE_SMDK6442) +#else +# define machine_is_smdk6442() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_BASE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_BASE +# endif +# define machine_is_openrd_base() (machine_arch_type == MACH_TYPE_OPENRD_BASE) +#else +# define machine_is_openrd_base() (0) +#endif + +#ifdef CONFIG_MACH_INCREDIBLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCREDIBLE +# endif +# define machine_is_incredible() (machine_arch_type == MACH_TYPE_INCREDIBLE) +#else +# define machine_is_incredible() (0) +#endif + +#ifdef CONFIG_MACH_INCREDIBLEC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCREDIBLEC +# endif +# define machine_is_incrediblec() (machine_arch_type == MACH_TYPE_INCREDIBLEC) +#else +# define machine_is_incrediblec() (0) +#endif + +#ifdef CONFIG_MACH_HEROCT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HEROCT +# endif +# define machine_is_heroct() (machine_arch_type == MACH_TYPE_HEROCT) +#else +# define machine_is_heroct() (0) +#endif + +#ifdef CONFIG_MACH_MMNET1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMNET1000 +# endif +# define machine_is_mmnet1000() (machine_arch_type == MACH_TYPE_MMNET1000) +#else +# define machine_is_mmnet1000() (0) +#endif + +#ifdef CONFIG_MACH_DEVKIT8000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVKIT8000 +# endif +# define machine_is_devkit8000() (machine_arch_type == MACH_TYPE_DEVKIT8000) +#else +# define machine_is_devkit8000() (0) +#endif + +#ifdef CONFIG_MACH_DEVKIT9000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVKIT9000 +# endif +# define machine_is_devkit9000() (machine_arch_type == MACH_TYPE_DEVKIT9000) +#else +# define machine_is_devkit9000() (0) +#endif + +#ifdef CONFIG_MACH_MX31TXTR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31TXTR +# endif +# define machine_is_mx31txtr() (machine_arch_type == MACH_TYPE_MX31TXTR) +#else +# define machine_is_mx31txtr() (0) +#endif + +#ifdef CONFIG_MACH_U380 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U380 +# endif +# define machine_is_u380() (machine_arch_type == MACH_TYPE_U380) +#else +# define machine_is_u380() (0) +#endif + +#ifdef CONFIG_MACH_HUALU_BOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUALU_BOARD +# endif +# define machine_is_oamp3_hualu() (machine_arch_type == MACH_TYPE_HUALU_BOARD) +#else +# define machine_is_oamp3_hualu() (0) +#endif + +#ifdef CONFIG_MACH_NPCMX50 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NPCMX50 +# endif +# define machine_is_npcmx50() (machine_arch_type == MACH_TYPE_NPCMX50) +#else +# define machine_is_npcmx50() (0) +#endif + +#ifdef CONFIG_MACH_MX51_EFIKAMX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_EFIKAMX +# endif +# define machine_is_mx51_efikamx() (machine_arch_type == MACH_TYPE_MX51_EFIKAMX) +#else +# define machine_is_mx51_efikamx() (0) +#endif + +#ifdef CONFIG_MACH_MX51_LANGE52 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_LANGE52 +# endif +# define machine_is_mx51_lange52() (machine_arch_type == MACH_TYPE_MX51_LANGE52) +#else +# define machine_is_mx51_lange52() (0) +#endif + +#ifdef CONFIG_MACH_RIOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOM +# endif +# define machine_is_riom() (machine_arch_type == MACH_TYPE_RIOM) +#else +# define machine_is_riom() (0) +#endif + +#ifdef CONFIG_MACH_COMCAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMCAS +# endif +# define machine_is_comcas() (machine_arch_type == MACH_TYPE_COMCAS) +#else +# define machine_is_comcas() (0) +#endif + +#ifdef CONFIG_MACH_WSI_MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WSI_MX27 +# endif +# define machine_is_wsi_mx27() (machine_arch_type == MACH_TYPE_WSI_MX27) +#else +# define machine_is_wsi_mx27() (0) +#endif + +#ifdef CONFIG_MACH_CM_T35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_T35 +# endif +# define machine_is_cm_t35() (machine_arch_type == MACH_TYPE_CM_T35) +#else +# define machine_is_cm_t35() (0) +#endif + +#ifdef CONFIG_MACH_NET2BIG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET2BIG +# endif +# define machine_is_net2big() (machine_arch_type == MACH_TYPE_NET2BIG) +#else +# define machine_is_net2big() (0) +#endif + +#ifdef CONFIG_MACH_MOTOROLA_A1600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOROLA_A1600 +# endif +# define machine_is_motorola_a1600() (machine_arch_type == MACH_TYPE_MOTOROLA_A1600) +#else +# define machine_is_motorola_a1600() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0020 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0020 +# endif +# define machine_is_igep0020() (machine_arch_type == MACH_TYPE_IGEP0020) +#else +# define machine_is_igep0020() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0010 +# endif +# define machine_is_igep0010() (machine_arch_type == MACH_TYPE_IGEP0010) +#else +# define machine_is_igep0010() (0) +#endif + +#ifdef CONFIG_MACH_MV6281GTWGE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV6281GTWGE2 +# endif +# define machine_is_mv6281gtwge2() (machine_arch_type == MACH_TYPE_MV6281GTWGE2) +#else +# define machine_is_mv6281gtwge2() (0) +#endif + +#ifdef CONFIG_MACH_SCAT100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCAT100 +# endif +# define machine_is_scat100() (machine_arch_type == MACH_TYPE_SCAT100) +#else +# define machine_is_scat100() (0) +#endif + +#ifdef CONFIG_MACH_SANMINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANMINA +# endif +# define machine_is_sanmina() (machine_arch_type == MACH_TYPE_SANMINA) +#else +# define machine_is_sanmina() (0) +#endif + +#ifdef CONFIG_MACH_MOMENTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOMENTO +# endif +# define machine_is_momento() (machine_arch_type == MACH_TYPE_MOMENTO) +#else +# define machine_is_momento() (0) +#endif + +#ifdef CONFIG_MACH_NUC9XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC9XX +# endif +# define machine_is_nuc9xx() (machine_arch_type == MACH_TYPE_NUC9XX) +#else +# define machine_is_nuc9xx() (0) +#endif + +#ifdef CONFIG_MACH_NUC910EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC910EVB +# endif +# define machine_is_nuc910evb() (machine_arch_type == MACH_TYPE_NUC910EVB) +#else +# define machine_is_nuc910evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC920EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC920EVB +# endif +# define machine_is_nuc920evb() (machine_arch_type == MACH_TYPE_NUC920EVB) +#else +# define machine_is_nuc920evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC950EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC950EVB +# endif +# define machine_is_nuc950evb() (machine_arch_type == MACH_TYPE_NUC950EVB) +#else +# define machine_is_nuc950evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC945EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC945EVB +# endif +# define machine_is_nuc945evb() (machine_arch_type == MACH_TYPE_NUC945EVB) +#else +# define machine_is_nuc945evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC960EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC960EVB +# endif +# define machine_is_nuc960evb() (machine_arch_type == MACH_TYPE_NUC960EVB) +#else +# define machine_is_nuc960evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC932EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC932EVB +# endif +# define machine_is_nuc932evb() (machine_arch_type == MACH_TYPE_NUC932EVB) +#else +# define machine_is_nuc932evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC900 +# endif +# define machine_is_nuc900() (machine_arch_type == MACH_TYPE_NUC900) +#else +# define machine_is_nuc900() (0) +#endif + +#ifdef CONFIG_MACH_SD1SOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SD1SOC +# endif +# define machine_is_sd1soc() (machine_arch_type == MACH_TYPE_SD1SOC) +#else +# define machine_is_sd1soc() (0) +#endif + +#ifdef CONFIG_MACH_LN2440BC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LN2440BC +# endif +# define machine_is_ln2440bc() (machine_arch_type == MACH_TYPE_LN2440BC) +#else +# define machine_is_ln2440bc() (0) +#endif + +#ifdef CONFIG_MACH_RSBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSBC +# endif +# define machine_is_rsbc() (machine_arch_type == MACH_TYPE_RSBC) +#else +# define machine_is_rsbc() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_CLIENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_CLIENT +# endif +# define machine_is_openrd_client() (machine_arch_type == MACH_TYPE_OPENRD_CLIENT) +#else +# define machine_is_openrd_client() (0) +#endif + +#ifdef CONFIG_MACH_HPIPAQ11X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPIPAQ11X +# endif +# define machine_is_hpipaq11x() (machine_arch_type == MACH_TYPE_HPIPAQ11X) +#else +# define machine_is_hpipaq11x() (0) +#endif + +#ifdef CONFIG_MACH_WAYLAND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WAYLAND +# endif +# define machine_is_wayland() (machine_arch_type == MACH_TYPE_WAYLAND) +#else +# define machine_is_wayland() (0) +#endif + +#ifdef CONFIG_MACH_ACNBSX102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACNBSX102 +# endif +# define machine_is_acnbsx102() (machine_arch_type == MACH_TYPE_ACNBSX102) +#else +# define machine_is_acnbsx102() (0) +#endif + +#ifdef CONFIG_MACH_HWAT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HWAT91 +# endif +# define machine_is_hwat91() (machine_arch_type == MACH_TYPE_HWAT91) +#else +# define machine_is_hwat91() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263CS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263CS +# endif +# define machine_is_at91sam9263cs() (machine_arch_type == MACH_TYPE_AT91SAM9263CS) +#else +# define machine_is_at91sam9263cs() (0) +#endif + +#ifdef CONFIG_MACH_CSB732 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB732 +# endif +# define machine_is_csb732() (machine_arch_type == MACH_TYPE_CSB732) +#else +# define machine_is_csb732() (0) +#endif + +#ifdef CONFIG_MACH_U8500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U8500 +# endif +# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500) +#else +# define machine_is_u8500() (0) +#endif + +#ifdef CONFIG_MACH_HUQIU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUQIU +# endif +# define machine_is_huqiu() (machine_arch_type == MACH_TYPE_HUQIU) +#else +# define machine_is_huqiu() (0) +#endif + +#ifdef CONFIG_MACH_MX51_EFIKASB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_EFIKASB +# endif +# define machine_is_mx51_efikasb() (machine_arch_type == MACH_TYPE_MX51_EFIKASB) +#else +# define machine_is_mx51_efikasb() (0) +#endif + +#ifdef CONFIG_MACH_PMT1G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PMT1G +# endif +# define machine_is_pmt1g() (machine_arch_type == MACH_TYPE_PMT1G) +#else +# define machine_is_pmt1g() (0) +#endif + +#ifdef CONFIG_MACH_HTCELF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCELF +# endif +# define machine_is_htcelf() (machine_arch_type == MACH_TYPE_HTCELF) +#else +# define machine_is_htcelf() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO420 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO420 +# endif +# define machine_is_armadillo420() (machine_arch_type == MACH_TYPE_ARMADILLO420) +#else +# define machine_is_armadillo420() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO440 +# endif +# define machine_is_armadillo440() (machine_arch_type == MACH_TYPE_ARMADILLO440) +#else +# define machine_is_armadillo440() (0) +#endif + +#ifdef CONFIG_MACH_U_CHIP_DUAL_ARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U_CHIP_DUAL_ARM +# endif +# define machine_is_u_chip_dual_arm() (machine_arch_type == MACH_TYPE_U_CHIP_DUAL_ARM) +#else +# define machine_is_u_chip_dual_arm() (0) +#endif + +#ifdef CONFIG_MACH_CSR_BDB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSR_BDB3 +# endif +# define machine_is_csr_bdb3() (machine_arch_type == MACH_TYPE_CSR_BDB3) +#else +# define machine_is_csr_bdb3() (0) +#endif + +#ifdef CONFIG_MACH_DOLBY_CAT1018 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOLBY_CAT1018 +# endif +# define machine_is_dolby_cat1018() (machine_arch_type == MACH_TYPE_DOLBY_CAT1018) +#else +# define machine_is_dolby_cat1018() (0) +#endif + +#ifdef CONFIG_MACH_HY9307 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9307 +# endif +# define machine_is_hy9307() (machine_arch_type == MACH_TYPE_HY9307) +#else +# define machine_is_hy9307() (0) +#endif + +#ifdef CONFIG_MACH_A_ES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A_ES +# endif +# define machine_is_aspire_easystore() (machine_arch_type == MACH_TYPE_A_ES) +#else +# define machine_is_aspire_easystore() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_IRIF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_IRIF +# endif +# define machine_is_davinci_irif() (machine_arch_type == MACH_TYPE_DAVINCI_IRIF) +#else +# define machine_is_davinci_irif() (0) +#endif + +#ifdef CONFIG_MACH_AGAMA9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AGAMA9263 +# endif +# define machine_is_agama9263() (machine_arch_type == MACH_TYPE_AGAMA9263) +#else +# define machine_is_agama9263() (0) +#endif + +#ifdef CONFIG_MACH_MARVELL_JASPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARVELL_JASPER +# endif +# define machine_is_marvell_jasper() (machine_arch_type == MACH_TYPE_MARVELL_JASPER) +#else +# define machine_is_marvell_jasper() (0) +#endif + +#ifdef CONFIG_MACH_FLINT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLINT +# endif +# define machine_is_flint() (machine_arch_type == MACH_TYPE_FLINT) +#else +# define machine_is_flint() (0) +#endif + +#ifdef CONFIG_MACH_TAVOREVB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAVOREVB3 +# endif +# define machine_is_tavorevb3() (machine_arch_type == MACH_TYPE_TAVOREVB3) +#else +# define machine_is_tavorevb3() (0) +#endif + +#ifdef CONFIG_MACH_SCH_M490 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCH_M490 +# endif +# define machine_is_sch_m490() (machine_arch_type == MACH_TYPE_SCH_M490) +#else +# define machine_is_sch_m490() (0) +#endif + +#ifdef CONFIG_MACH_RBL01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RBL01 +# endif +# define machine_is_rbl01() (machine_arch_type == MACH_TYPE_RBL01) +#else +# define machine_is_rbl01() (0) +#endif + +#ifdef CONFIG_MACH_OMNIFI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMNIFI +# endif +# define machine_is_omnifi() (machine_arch_type == MACH_TYPE_OMNIFI) +#else +# define machine_is_omnifi() (0) +#endif + +#ifdef CONFIG_MACH_OTAVALO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTAVALO +# endif +# define machine_is_otavalo() (machine_arch_type == MACH_TYPE_OTAVALO) +#else +# define machine_is_otavalo() (0) +#endif + +#ifdef CONFIG_MACH_SIENA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIENA +# endif +# define machine_is_siena() (machine_arch_type == MACH_TYPE_SIENA) +#else +# define machine_is_siena() (0) +#endif + +#ifdef CONFIG_MACH_HTC_EXCALIBUR_S620 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_EXCALIBUR_S620 +# endif +# define machine_is_htc_excalibur_s620() (machine_arch_type == MACH_TYPE_HTC_EXCALIBUR_S620) +#else +# define machine_is_htc_excalibur_s620() (0) +#endif + +#ifdef CONFIG_MACH_HTC_OPAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_OPAL +# endif +# define machine_is_htc_opal() (machine_arch_type == MACH_TYPE_HTC_OPAL) +#else +# define machine_is_htc_opal() (0) +#endif + +#ifdef CONFIG_MACH_TOUCHBOOK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOUCHBOOK +# endif +# define machine_is_touchbook() (machine_arch_type == MACH_TYPE_TOUCHBOOK) +#else +# define machine_is_touchbook() (0) +#endif + +#ifdef CONFIG_MACH_LATTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LATTE +# endif +# define machine_is_latte() (machine_arch_type == MACH_TYPE_LATTE) +#else +# define machine_is_latte() (0) +#endif + +#ifdef CONFIG_MACH_XA200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XA200 +# endif +# define machine_is_xa200() (machine_arch_type == MACH_TYPE_XA200) +#else +# define machine_is_xa200() (0) +#endif + +#ifdef CONFIG_MACH_NIMROD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMROD +# endif +# define machine_is_nimrod() (machine_arch_type == MACH_TYPE_NIMROD) +#else +# define machine_is_nimrod() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215_3G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215_3G +# endif +# define machine_is_cc9p9215_3g() (machine_arch_type == MACH_TYPE_CC9P9215_3G) +#else +# define machine_is_cc9p9215_3g() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215_3GJS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215_3GJS +# endif +# define machine_is_cc9p9215_3gjs() (machine_arch_type == MACH_TYPE_CC9P9215_3GJS) +#else +# define machine_is_cc9p9215_3gjs() (0) +#endif + +#ifdef CONFIG_MACH_TK71 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TK71 +# endif +# define machine_is_tk71() (machine_arch_type == MACH_TYPE_TK71) +#else +# define machine_is_tk71() (0) +#endif + +#ifdef CONFIG_MACH_COMHAM3525 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMHAM3525 +# endif +# define machine_is_comham3525() (machine_arch_type == MACH_TYPE_COMHAM3525) +#else +# define machine_is_comham3525() (0) +#endif + +#ifdef CONFIG_MACH_MX31EREBUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31EREBUS +# endif +# define machine_is_mx31erebus() (machine_arch_type == MACH_TYPE_MX31EREBUS) +#else +# define machine_is_mx31erebus() (0) +#endif + +#ifdef CONFIG_MACH_MCARDMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCARDMX27 +# endif +# define machine_is_mcardmx27() (machine_arch_type == MACH_TYPE_MCARDMX27) +#else +# define machine_is_mcardmx27() (0) +#endif + +#ifdef CONFIG_MACH_PARADISE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PARADISE +# endif +# define machine_is_paradise() (machine_arch_type == MACH_TYPE_PARADISE) +#else +# define machine_is_paradise() (0) +#endif + +#ifdef CONFIG_MACH_TIDE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIDE +# endif +# define machine_is_tide() (machine_arch_type == MACH_TYPE_TIDE) +#else +# define machine_is_tide() (0) +#endif + +#ifdef CONFIG_MACH_WZL2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL2440 +# endif +# define machine_is_wzl2440() (machine_arch_type == MACH_TYPE_WZL2440) +#else +# define machine_is_wzl2440() (0) +#endif + +#ifdef CONFIG_MACH_SDRDEMO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SDRDEMO +# endif +# define machine_is_sdrdemo() (machine_arch_type == MACH_TYPE_SDRDEMO) +#else +# define machine_is_sdrdemo() (0) +#endif + +#ifdef CONFIG_MACH_ETHERCAN2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETHERCAN2 +# endif +# define machine_is_ethercan2() (machine_arch_type == MACH_TYPE_ETHERCAN2) +#else +# define machine_is_ethercan2() (0) +#endif + +#ifdef CONFIG_MACH_ECMIMG20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECMIMG20 +# endif +# define machine_is_ecmimg20() (machine_arch_type == MACH_TYPE_ECMIMG20) +#else +# define machine_is_ecmimg20() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_DRAGON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_DRAGON +# endif +# define machine_is_omap_dragon() (machine_arch_type == MACH_TYPE_OMAP_DRAGON) +#else +# define machine_is_omap_dragon() (0) +#endif + +#ifdef CONFIG_MACH_HALO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HALO +# endif +# define machine_is_halo() (machine_arch_type == MACH_TYPE_HALO) +#else +# define machine_is_halo() (0) +#endif + +#ifdef CONFIG_MACH_HUANGSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUANGSHAN +# endif +# define machine_is_huangshan() (machine_arch_type == MACH_TYPE_HUANGSHAN) +#else +# define machine_is_huangshan() (0) +#endif + +#ifdef CONFIG_MACH_VL_MA2SC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VL_MA2SC +# endif +# define machine_is_vl_ma2sc() (machine_arch_type == MACH_TYPE_VL_MA2SC) +#else +# define machine_is_vl_ma2sc() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_RC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_RC +# endif +# define machine_is_raumfeld_rc() (machine_arch_type == MACH_TYPE_RAUMFELD_RC) +#else +# define machine_is_raumfeld_rc() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_CONNECTOR +# endif +# define machine_is_raumfeld_connector() (machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR) +#else +# define machine_is_raumfeld_connector() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_SPEAKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_SPEAKER +# endif +# define machine_is_raumfeld_speaker() (machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER) +#else +# define machine_is_raumfeld_speaker() (0) +#endif + +#ifdef CONFIG_MACH_MULTIBUS_MASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIBUS_MASTER +# endif +# define machine_is_multibus_master() (machine_arch_type == MACH_TYPE_MULTIBUS_MASTER) +#else +# define machine_is_multibus_master() (0) +#endif + +#ifdef CONFIG_MACH_MULTIBUS_PBK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIBUS_PBK +# endif +# define machine_is_multibus_pbk() (machine_arch_type == MACH_TYPE_MULTIBUS_PBK) +#else +# define machine_is_multibus_pbk() (0) +#endif + +#ifdef CONFIG_MACH_TNETV107X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNETV107X +# endif +# define machine_is_tnetv107x() (machine_arch_type == MACH_TYPE_TNETV107X) +#else +# define machine_is_tnetv107x() (0) +#endif + +#ifdef CONFIG_MACH_SNAKE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAKE +# endif +# define machine_is_snake() (machine_arch_type == MACH_TYPE_SNAKE) +#else +# define machine_is_snake() (0) +#endif + +#ifdef CONFIG_MACH_CWMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWMX27 +# endif +# define machine_is_cwmx27() (machine_arch_type == MACH_TYPE_CWMX27) +#else +# define machine_is_cwmx27() (0) +#endif + +#ifdef CONFIG_MACH_SCH_M480 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCH_M480 +# endif +# define machine_is_sch_m480() (machine_arch_type == MACH_TYPE_SCH_M480) +#else +# define machine_is_sch_m480() (0) +#endif + +#ifdef CONFIG_MACH_PLATYPUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PLATYPUS +# endif +# define machine_is_platypus() (machine_arch_type == MACH_TYPE_PLATYPUS) +#else +# define machine_is_platypus() (0) +#endif + +#ifdef CONFIG_MACH_PSS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PSS2 +# endif +# define machine_is_pss2() (machine_arch_type == MACH_TYPE_PSS2) +#else +# define machine_is_pss2() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_APM150 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_APM150 +# endif +# define machine_is_davinci_apm150() (machine_arch_type == MACH_TYPE_DAVINCI_APM150) +#else +# define machine_is_davinci_apm150() (0) +#endif + +#ifdef CONFIG_MACH_STR9100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STR9100 +# endif +# define machine_is_str9100() (machine_arch_type == MACH_TYPE_STR9100) +#else +# define machine_is_str9100() (0) +#endif + +#ifdef CONFIG_MACH_NET5BIG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET5BIG +# endif +# define machine_is_net5big() (machine_arch_type == MACH_TYPE_NET5BIG) +#else +# define machine_is_net5big() (0) +#endif + +#ifdef CONFIG_MACH_SEABED9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SEABED9263 +# endif +# define machine_is_seabed9263() (machine_arch_type == MACH_TYPE_SEABED9263) +#else +# define machine_is_seabed9263() (0) +#endif + +#ifdef CONFIG_MACH_MX51_M2ID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_M2ID +# endif +# define machine_is_mx51_m2id() (machine_arch_type == MACH_TYPE_MX51_M2ID) +#else +# define machine_is_mx51_m2id() (0) +#endif + +#ifdef CONFIG_MACH_OCTVOCPLUS_EB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OCTVOCPLUS_EB +# endif +# define machine_is_octvocplus_eb() (machine_arch_type == MACH_TYPE_OCTVOCPLUS_EB) +#else +# define machine_is_octvocplus_eb() (0) +#endif + +#ifdef CONFIG_MACH_KLK_FIREFOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_FIREFOX +# endif +# define machine_is_klk_firefox() (machine_arch_type == MACH_TYPE_KLK_FIREFOX) +#else +# define machine_is_klk_firefox() (0) +#endif + +#ifdef CONFIG_MACH_KLK_WIRMA_MODULE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_WIRMA_MODULE +# endif +# define machine_is_klk_wirma_module() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MODULE) +#else +# define machine_is_klk_wirma_module() (0) +#endif + +#ifdef CONFIG_MACH_KLK_WIRMA_MMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KLK_WIRMA_MMI +# endif +# define machine_is_klk_wirma_mmi() (machine_arch_type == MACH_TYPE_KLK_WIRMA_MMI) +#else +# define machine_is_klk_wirma_mmi() (0) +#endif + +#ifdef CONFIG_MACH_SUPERSONIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUPERSONIC +# endif +# define machine_is_supersonic() (machine_arch_type == MACH_TYPE_SUPERSONIC) +#else +# define machine_is_supersonic() (0) +#endif + +#ifdef CONFIG_MACH_LIBERTY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIBERTY +# endif +# define machine_is_liberty() (machine_arch_type == MACH_TYPE_LIBERTY) +#else +# define machine_is_liberty() (0) +#endif + +#ifdef CONFIG_MACH_MH355 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MH355 +# endif +# define machine_is_mh355() (machine_arch_type == MACH_TYPE_MH355) +#else +# define machine_is_mh355() (0) +#endif + +#ifdef CONFIG_MACH_PC7802 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7802 +# endif +# define machine_is_pc7802() (machine_arch_type == MACH_TYPE_PC7802) +#else +# define machine_is_pc7802() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGC +# endif +# define machine_is_gnet_sgc() (machine_arch_type == MACH_TYPE_GNET_SGC) +#else +# define machine_is_gnet_sgc() (0) +#endif + +#ifdef CONFIG_MACH_EINSTEIN15 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EINSTEIN15 +# endif +# define machine_is_einstein15() (machine_arch_type == MACH_TYPE_EINSTEIN15) +#else +# define machine_is_einstein15() (0) +#endif + +#ifdef CONFIG_MACH_CMPD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMPD +# endif +# define machine_is_cmpd() (machine_arch_type == MACH_TYPE_CMPD) +#else +# define machine_is_cmpd() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_HASE1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_HASE1 +# endif +# define machine_is_davinci_hase1() (machine_arch_type == MACH_TYPE_DAVINCI_HASE1) +#else +# define machine_is_davinci_hase1() (0) +#endif + +#ifdef CONFIG_MACH_LGEINCITEPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LGEINCITEPHONE +# endif +# define machine_is_lgeincitephone() (machine_arch_type == MACH_TYPE_LGEINCITEPHONE) +#else +# define machine_is_lgeincitephone() (0) +#endif + +#ifdef CONFIG_MACH_EA313X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EA313X +# endif +# define machine_is_ea313x() (machine_arch_type == MACH_TYPE_EA313X) +#else +# define machine_is_ea313x() (0) +#endif + +#ifdef CONFIG_MACH_FWBD_39064 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FWBD_39064 +# endif +# define machine_is_fwbd_39064() (machine_arch_type == MACH_TYPE_FWBD_39064) +#else +# define machine_is_fwbd_39064() (0) +#endif + +#ifdef CONFIG_MACH_FWBD_390128 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FWBD_390128 +# endif +# define machine_is_fwbd_390128() (machine_arch_type == MACH_TYPE_FWBD_390128) +#else +# define machine_is_fwbd_390128() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_MOE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_MOE +# endif +# define machine_is_pelco_moe() (machine_arch_type == MACH_TYPE_PELCO_MOE) +#else +# define machine_is_pelco_moe() (0) +#endif + +#ifdef CONFIG_MACH_MINIMIX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINIMIX27 +# endif +# define machine_is_minimix27() (machine_arch_type == MACH_TYPE_MINIMIX27) +#else +# define machine_is_minimix27() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_THUNDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_THUNDER +# endif +# define machine_is_omap3_thunder() (machine_arch_type == MACH_TYPE_OMAP3_THUNDER) +#else +# define machine_is_omap3_thunder() (0) +#endif + +#ifdef CONFIG_MACH_PASSIONC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSIONC +# endif +# define machine_is_passionc() (machine_arch_type == MACH_TYPE_PASSIONC) +#else +# define machine_is_passionc() (0) +#endif + +#ifdef CONFIG_MACH_MX27AMATA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27AMATA +# endif +# define machine_is_mx27amata() (machine_arch_type == MACH_TYPE_MX27AMATA) +#else +# define machine_is_mx27amata() (0) +#endif + +#ifdef CONFIG_MACH_BGAT1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BGAT1 +# endif +# define machine_is_bgat1() (machine_arch_type == MACH_TYPE_BGAT1) +#else +# define machine_is_bgat1() (0) +#endif + +#ifdef CONFIG_MACH_BUZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUZZ +# endif +# define machine_is_buzz() (machine_arch_type == MACH_TYPE_BUZZ) +#else +# define machine_is_buzz() (0) +#endif + +#ifdef CONFIG_MACH_MB9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB9G20 +# endif +# define machine_is_mb9g20() (machine_arch_type == MACH_TYPE_MB9G20) +#else +# define machine_is_mb9g20() (0) +#endif + +#ifdef CONFIG_MACH_YUSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YUSHAN +# endif +# define machine_is_yushan() (machine_arch_type == MACH_TYPE_YUSHAN) +#else +# define machine_is_yushan() (0) +#endif + +#ifdef CONFIG_MACH_LIZARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIZARD +# endif +# define machine_is_lizard() (machine_arch_type == MACH_TYPE_LIZARD) +#else +# define machine_is_lizard() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3POLYCOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3POLYCOM +# endif +# define machine_is_omap3polycom() (machine_arch_type == MACH_TYPE_OMAP3POLYCOM) +#else +# define machine_is_omap3polycom() (0) +#endif + +#ifdef CONFIG_MACH_SMDKV210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKV210 +# endif +# define machine_is_smdkv210() (machine_arch_type == MACH_TYPE_SMDKV210) +#else +# define machine_is_smdkv210() (0) +#endif + +#ifdef CONFIG_MACH_BRAVO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRAVO +# endif +# define machine_is_bravo() (machine_arch_type == MACH_TYPE_BRAVO) +#else +# define machine_is_bravo() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO1 +# endif +# define machine_is_siogentoo1() (machine_arch_type == MACH_TYPE_SIOGENTOO1) +#else +# define machine_is_siogentoo1() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO2 +# endif +# define machine_is_siogentoo2() (machine_arch_type == MACH_TYPE_SIOGENTOO2) +#else +# define machine_is_siogentoo2() (0) +#endif + +#ifdef CONFIG_MACH_SM3K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SM3K +# endif +# define machine_is_sm3k() (machine_arch_type == MACH_TYPE_SM3K) +#else +# define machine_is_sm3k() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_F900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_F900 +# endif +# define machine_is_acer_tempo_f900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_F900) +#else +# define machine_is_acer_tempo_f900() (0) +#endif + +#ifdef CONFIG_MACH_SST61VC010_DEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SST61VC010_DEV +# endif +# define machine_is_p87_dev() (machine_arch_type == MACH_TYPE_SST61VC010_DEV) +#else +# define machine_is_p87_dev() (0) +#endif + +#ifdef CONFIG_MACH_GLITTERTIND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GLITTERTIND +# endif +# define machine_is_glittertind() (machine_arch_type == MACH_TYPE_GLITTERTIND) +#else +# define machine_is_glittertind() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_ZOOM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_ZOOM3 +# endif +# define machine_is_omap_zoom3() (machine_arch_type == MACH_TYPE_OMAP_ZOOM3) +#else +# define machine_is_omap_zoom3() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_3630SDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_3630SDP +# endif +# define machine_is_omap_3630sdp() (machine_arch_type == MACH_TYPE_OMAP_3630SDP) +#else +# define machine_is_omap_3630sdp() (0) +#endif + +#ifdef CONFIG_MACH_CYBOOK2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBOOK2440 +# endif +# define machine_is_cybook2440() (machine_arch_type == MACH_TYPE_CYBOOK2440) +#else +# define machine_is_cybook2440() (0) +#endif + +#ifdef CONFIG_MACH_TORINO_S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TORINO_S +# endif +# define machine_is_torino_s() (machine_arch_type == MACH_TYPE_TORINO_S) +#else +# define machine_is_torino_s() (0) +#endif + +#ifdef CONFIG_MACH_HAVANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAVANA +# endif +# define machine_is_havana() (machine_arch_type == MACH_TYPE_HAVANA) +#else +# define machine_is_havana() (0) +#endif + +#ifdef CONFIG_MACH_BEAUMONT_11 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEAUMONT_11 +# endif +# define machine_is_beaumont_11() (machine_arch_type == MACH_TYPE_BEAUMONT_11) +#else +# define machine_is_beaumont_11() (0) +#endif + +#ifdef CONFIG_MACH_VANGUARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VANGUARD +# endif +# define machine_is_vanguard() (machine_arch_type == MACH_TYPE_VANGUARD) +#else +# define machine_is_vanguard() (0) +#endif + +#ifdef CONFIG_MACH_S5PC110_DRACO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5PC110_DRACO +# endif +# define machine_is_s5pc110_draco() (machine_arch_type == MACH_TYPE_S5PC110_DRACO) +#else +# define machine_is_s5pc110_draco() (0) +#endif + +#ifdef CONFIG_MACH_CARTESIO_TWO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARTESIO_TWO +# endif +# define machine_is_cartesio_two() (machine_arch_type == MACH_TYPE_CARTESIO_TWO) +#else +# define machine_is_cartesio_two() (0) +#endif + +#ifdef CONFIG_MACH_ASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASTER +# endif +# define machine_is_aster() (machine_arch_type == MACH_TYPE_ASTER) +#else +# define machine_is_aster() (0) +#endif + +#ifdef CONFIG_MACH_VOGUESV210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VOGUESV210 +# endif +# define machine_is_voguesv210() (machine_arch_type == MACH_TYPE_VOGUESV210) +#else +# define machine_is_voguesv210() (0) +#endif + +#ifdef CONFIG_MACH_ACM500X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACM500X +# endif +# define machine_is_acm500x() (machine_arch_type == MACH_TYPE_ACM500X) +#else +# define machine_is_acm500x() (0) +#endif + +#ifdef CONFIG_MACH_KM9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KM9260 +# endif +# define machine_is_km9260() (machine_arch_type == MACH_TYPE_KM9260) +#else +# define machine_is_km9260() (0) +#endif + +#ifdef CONFIG_MACH_NIDEFLEXG1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIDEFLEXG1 +# endif +# define machine_is_nideflexg1() (machine_arch_type == MACH_TYPE_NIDEFLEXG1) +#else +# define machine_is_nideflexg1() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_PLUG_IO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_PLUG_IO +# endif +# define machine_is_ctera_plug_io() (machine_arch_type == MACH_TYPE_CTERA_PLUG_IO) +#else +# define machine_is_ctera_plug_io() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQ7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQ7 +# endif +# define machine_is_smartq7() (machine_arch_type == MACH_TYPE_SMARTQ7) +#else +# define machine_is_smartq7() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G10EK2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G10EK2 +# endif +# define machine_is_at91sam9g10ek2() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK2) +#else +# define machine_is_at91sam9g10ek2() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP527 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP527 +# endif +# define machine_is_asusp527() (machine_arch_type == MACH_TYPE_ASUSP527) +#else +# define machine_is_asusp527() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20MPM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20MPM2 +# endif +# define machine_is_at91sam9g20mpm2() (machine_arch_type == MACH_TYPE_AT91SAM9G20MPM2) +#else +# define machine_is_at91sam9g20mpm2() (0) +#endif + +#ifdef CONFIG_MACH_TOPASA900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOPASA900 +# endif +# define machine_is_topasa900() (machine_arch_type == MACH_TYPE_TOPASA900) +#else +# define machine_is_topasa900() (0) +#endif + +#ifdef CONFIG_MACH_ELECTRUM_100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELECTRUM_100 +# endif +# define machine_is_electrum_100() (machine_arch_type == MACH_TYPE_ELECTRUM_100) +#else +# define machine_is_electrum_100() (0) +#endif + +#ifdef CONFIG_MACH_MX51GRB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51GRB +# endif +# define machine_is_mx51grb() (machine_arch_type == MACH_TYPE_MX51GRB) +#else +# define machine_is_mx51grb() (0) +#endif + +#ifdef CONFIG_MACH_XEA300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XEA300 +# endif +# define machine_is_xea300() (machine_arch_type == MACH_TYPE_XEA300) +#else +# define machine_is_xea300() (0) +#endif + +#ifdef CONFIG_MACH_HTCSTARTREK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCSTARTREK +# endif +# define machine_is_htcstartrek() (machine_arch_type == MACH_TYPE_HTCSTARTREK) +#else +# define machine_is_htcstartrek() (0) +#endif + +#ifdef CONFIG_MACH_LIMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIMA +# endif +# define machine_is_lima() (machine_arch_type == MACH_TYPE_LIMA) +#else +# define machine_is_lima() (0) +#endif + +#ifdef CONFIG_MACH_CSB740 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB740 +# endif +# define machine_is_csb740() (machine_arch_type == MACH_TYPE_CSB740) +#else +# define machine_is_csb740() (0) +#endif + +#ifdef CONFIG_MACH_USB_S8815 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USB_S8815 +# endif +# define machine_is_usb_s8815() (machine_arch_type == MACH_TYPE_USB_S8815) +#else +# define machine_is_usb_s8815() (0) +#endif + +#ifdef CONFIG_MACH_WATSON_EFM_PLUGIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WATSON_EFM_PLUGIN +# endif +# define machine_is_watson_efm_plugin() (machine_arch_type == MACH_TYPE_WATSON_EFM_PLUGIN) +#else +# define machine_is_watson_efm_plugin() (0) +#endif + +#ifdef CONFIG_MACH_MILKYWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MILKYWAY +# endif +# define machine_is_milkyway() (machine_arch_type == MACH_TYPE_MILKYWAY) +#else +# define machine_is_milkyway() (0) +#endif + +#ifdef CONFIG_MACH_G4EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G4EVM +# endif +# define machine_is_g4evm() (machine_arch_type == MACH_TYPE_G4EVM) +#else +# define machine_is_g4evm() (0) +#endif + +#ifdef CONFIG_MACH_PICOMOD6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOMOD6 +# endif +# define machine_is_picomod6() (machine_arch_type == MACH_TYPE_PICOMOD6) +#else +# define machine_is_picomod6() (0) +#endif + +#ifdef CONFIG_MACH_OMAPL138_HAWKBOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAPL138_HAWKBOARD +# endif +# define machine_is_omapl138_hawkboard() (machine_arch_type == MACH_TYPE_OMAPL138_HAWKBOARD) +#else +# define machine_is_omapl138_hawkboard() (0) +#endif + +#ifdef CONFIG_MACH_IP6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP6000 +# endif +# define machine_is_ip6000() (machine_arch_type == MACH_TYPE_IP6000) +#else +# define machine_is_ip6000() (0) +#endif + +#ifdef CONFIG_MACH_IP6010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IP6010 +# endif +# define machine_is_ip6010() (machine_arch_type == MACH_TYPE_IP6010) +#else +# define machine_is_ip6010() (0) +#endif + +#ifdef CONFIG_MACH_UTM400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UTM400 +# endif +# define machine_is_utm400() (machine_arch_type == MACH_TYPE_UTM400) +#else +# define machine_is_utm400() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_ZYBEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_ZYBEX +# endif +# define machine_is_omap3_zybex() (machine_arch_type == MACH_TYPE_OMAP3_ZYBEX) +#else +# define machine_is_omap3_zybex() (0) +#endif + +#ifdef CONFIG_MACH_WIRELESS_SPACE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WIRELESS_SPACE +# endif +# define machine_is_wireless_space() (machine_arch_type == MACH_TYPE_WIRELESS_SPACE) +#else +# define machine_is_wireless_space() (0) +#endif + +#ifdef CONFIG_MACH_SX560 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SX560 +# endif +# define machine_is_sx560() (machine_arch_type == MACH_TYPE_SX560) +#else +# define machine_is_sx560() (0) +#endif + +#ifdef CONFIG_MACH_TS41X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS41X +# endif +# define machine_is_ts41x() (machine_arch_type == MACH_TYPE_TS41X) +#else +# define machine_is_ts41x() (0) +#endif + +#ifdef CONFIG_MACH_ELPHEL10373 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELPHEL10373 +# endif +# define machine_is_elphel10373() (machine_arch_type == MACH_TYPE_ELPHEL10373) +#else +# define machine_is_elphel10373() (0) +#endif + +#ifdef CONFIG_MACH_RHOBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RHOBOT +# endif +# define machine_is_rhobot() (machine_arch_type == MACH_TYPE_RHOBOT) +#else +# define machine_is_rhobot() (0) +#endif + +#ifdef CONFIG_MACH_MX51_REFRESH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_REFRESH +# endif +# define machine_is_mx51_refresh() (machine_arch_type == MACH_TYPE_MX51_REFRESH) +#else +# define machine_is_mx51_refresh() (0) +#endif + +#ifdef CONFIG_MACH_LS9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LS9260 +# endif +# define machine_is_ls9260() (machine_arch_type == MACH_TYPE_LS9260) +#else +# define machine_is_ls9260() (0) +#endif + +#ifdef CONFIG_MACH_SHANK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHANK +# endif +# define machine_is_shank() (machine_arch_type == MACH_TYPE_SHANK) +#else +# define machine_is_shank() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_ST1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_ST1 +# endif +# define machine_is_qsd8x50_st1() (machine_arch_type == MACH_TYPE_QSD8X50_ST1) +#else +# define machine_is_qsd8x50_st1() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9M10EKES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9M10EKES +# endif +# define machine_is_at91sam9m10ekes() (machine_arch_type == MACH_TYPE_AT91SAM9M10EKES) +#else +# define machine_is_at91sam9m10ekes() (0) +#endif + +#ifdef CONFIG_MACH_HIRAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIRAM +# endif +# define machine_is_hiram() (machine_arch_type == MACH_TYPE_HIRAM) +#else +# define machine_is_hiram() (0) +#endif + +#ifdef CONFIG_MACH_PHY3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHY3250 +# endif +# define machine_is_phy3250() (machine_arch_type == MACH_TYPE_PHY3250) +#else +# define machine_is_phy3250() (0) +#endif + +#ifdef CONFIG_MACH_EA3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EA3250 +# endif +# define machine_is_ea3250() (machine_arch_type == MACH_TYPE_EA3250) +#else +# define machine_is_ea3250() (0) +#endif + +#ifdef CONFIG_MACH_FDI3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FDI3250 +# endif +# define machine_is_fdi3250() (machine_arch_type == MACH_TYPE_FDI3250) +#else +# define machine_is_fdi3250() (0) +#endif + +#ifdef CONFIG_MACH_WHITESTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITESTONE +# endif +# define machine_is_htcwhitestone() (machine_arch_type == MACH_TYPE_WHITESTONE) +#else +# define machine_is_htcwhitestone() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263NIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263NIT +# endif +# define machine_is_at91sam9263nit() (machine_arch_type == MACH_TYPE_AT91SAM9263NIT) +#else +# define machine_is_at91sam9263nit() (0) +#endif + +#ifdef CONFIG_MACH_CCMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCMX51 +# endif +# define machine_is_ccmx51() (machine_arch_type == MACH_TYPE_CCMX51) +#else +# define machine_is_ccmx51() (0) +#endif + +#ifdef CONFIG_MACH_CCMX51JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCMX51JS +# endif +# define machine_is_ccmx51js() (machine_arch_type == MACH_TYPE_CCMX51JS) +#else +# define machine_is_ccmx51js() (0) +#endif + +#ifdef CONFIG_MACH_CCWMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCWMX51 +# endif +# define machine_is_ccwmx51() (machine_arch_type == MACH_TYPE_CCWMX51) +#else +# define machine_is_ccwmx51() (0) +#endif + +#ifdef CONFIG_MACH_CCWMX51JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCWMX51JS +# endif +# define machine_is_ccwmx51js() (machine_arch_type == MACH_TYPE_CCWMX51JS) +#else +# define machine_is_ccwmx51js() (0) +#endif + +#ifdef CONFIG_MACH_MINI6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI6410 +# endif +# define machine_is_mini6410() (machine_arch_type == MACH_TYPE_MINI6410) +#else +# define machine_is_mini6410() (0) +#endif + +#ifdef CONFIG_MACH_TINY6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TINY6410 +# endif +# define machine_is_tiny6410() (machine_arch_type == MACH_TYPE_TINY6410) +#else +# define machine_is_tiny6410() (0) +#endif + +#ifdef CONFIG_MACH_NANO6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NANO6410 +# endif +# define machine_is_nano6410() (machine_arch_type == MACH_TYPE_NANO6410) +#else +# define machine_is_nano6410() (0) +#endif + +#ifdef CONFIG_MACH_AT572D940HFNLDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT572D940HFNLDB +# endif +# define machine_is_at572d940hfnldb() (machine_arch_type == MACH_TYPE_AT572D940HFNLDB) +#else +# define machine_is_at572d940hfnldb() (0) +#endif + +#ifdef CONFIG_MACH_HTCLEO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCLEO +# endif +# define machine_is_htcleo() (machine_arch_type == MACH_TYPE_HTCLEO) +#else +# define machine_is_htcleo() (0) +#endif + +#ifdef CONFIG_MACH_AVP13 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AVP13 +# endif +# define machine_is_avp13() (machine_arch_type == MACH_TYPE_AVP13) +#else +# define machine_is_avp13() (0) +#endif + +#ifdef CONFIG_MACH_XXSVIDEOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XXSVIDEOD +# endif +# define machine_is_xxsvideod() (machine_arch_type == MACH_TYPE_XXSVIDEOD) +#else +# define machine_is_xxsvideod() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT +# endif +# define machine_is_vpnext() (machine_arch_type == MACH_TYPE_VPNEXT) +#else +# define machine_is_vpnext() (0) +#endif + +#ifdef CONFIG_MACH_SWARCO_ITC3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCO_ITC3 +# endif +# define machine_is_swarco_itc3() (machine_arch_type == MACH_TYPE_SWARCO_ITC3) +#else +# define machine_is_swarco_itc3() (0) +#endif + +#ifdef CONFIG_MACH_TX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX51 +# endif +# define machine_is_tx51() (machine_arch_type == MACH_TYPE_TX51) +#else +# define machine_is_tx51() (0) +#endif + +#ifdef CONFIG_MACH_DOLBY_CAT1021 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOLBY_CAT1021 +# endif +# define machine_is_dolby_cat1021() (machine_arch_type == MACH_TYPE_DOLBY_CAT1021) +#else +# define machine_is_dolby_cat1021() (0) +#endif + +#ifdef CONFIG_MACH_MX28EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX28EVK +# endif +# define machine_is_mx28evk() (machine_arch_type == MACH_TYPE_MX28EVK) +#else +# define machine_is_mx28evk() (0) +#endif + +#ifdef CONFIG_MACH_PHOENIX260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHOENIX260 +# endif +# define machine_is_phoenix260() (machine_arch_type == MACH_TYPE_PHOENIX260) +#else +# define machine_is_phoenix260() (0) +#endif + +#ifdef CONFIG_MACH_UVACA_STORK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UVACA_STORK +# endif +# define machine_is_uvaca_stork() (machine_arch_type == MACH_TYPE_UVACA_STORK) +#else +# define machine_is_uvaca_stork() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQ5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQ5 +# endif +# define machine_is_smartq5() (machine_arch_type == MACH_TYPE_SMARTQ5) +#else +# define machine_is_smartq5() (0) +#endif + +#ifdef CONFIG_MACH_ALL3078 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ALL3078 +# endif +# define machine_is_all3078() (machine_arch_type == MACH_TYPE_ALL3078) +#else +# define machine_is_all3078() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY_DS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY_DS +# endif +# define machine_is_ctera_2bay_ds() (machine_arch_type == MACH_TYPE_CTERA_2BAY_DS) +#else +# define machine_is_ctera_2bay_ds() (0) +#endif + +#ifdef CONFIG_MACH_SIOGENTOO3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIOGENTOO3 +# endif +# define machine_is_siogentoo3() (machine_arch_type == MACH_TYPE_SIOGENTOO3) +#else +# define machine_is_siogentoo3() (0) +#endif + +#ifdef CONFIG_MACH_EPB5000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPB5000 +# endif +# define machine_is_epb5000() (machine_arch_type == MACH_TYPE_EPB5000) +#else +# define machine_is_epb5000() (0) +#endif + +#ifdef CONFIG_MACH_HY9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9263 +# endif +# define machine_is_hy9263() (machine_arch_type == MACH_TYPE_HY9263) +#else +# define machine_is_hy9263() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_M900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_M900 +# endif +# define machine_is_acer_tempo_m900() (machine_arch_type == MACH_TYPE_ACER_TEMPO_M900) +#else +# define machine_is_acer_tempo_m900() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_DX900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_DX900 +# endif +# define machine_is_acer_tempo_dx650() (machine_arch_type == MACH_TYPE_ACER_TEMPO_DX900) +#else +# define machine_is_acer_tempo_dx650() (0) +#endif + +#ifdef CONFIG_MACH_ACER_TEMPO_X960 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_TEMPO_X960 +# endif +# define machine_is_acer_tempo_x960() (machine_arch_type == MACH_TYPE_ACER_TEMPO_X960) +#else +# define machine_is_acer_tempo_x960() (0) +#endif + +#ifdef CONFIG_MACH_ACER_ETEN_V900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_ETEN_V900 +# endif +# define machine_is_acer_eten_v900() (machine_arch_type == MACH_TYPE_ACER_ETEN_V900) +#else +# define machine_is_acer_eten_v900() (0) +#endif + +#ifdef CONFIG_MACH_ACER_ETEN_X900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_ETEN_X900 +# endif +# define machine_is_acer_eten_x900() (machine_arch_type == MACH_TYPE_ACER_ETEN_X900) +#else +# define machine_is_acer_eten_x900() (0) +#endif + +#ifdef CONFIG_MACH_BONNELL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BONNELL +# endif +# define machine_is_bonnell() (machine_arch_type == MACH_TYPE_BONNELL) +#else +# define machine_is_bonnell() (0) +#endif + +#ifdef CONFIG_MACH_OHT_MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OHT_MX27 +# endif +# define machine_is_oht_mx27() (machine_arch_type == MACH_TYPE_OHT_MX27) +#else +# define machine_is_oht_mx27() (0) +#endif + +#ifdef CONFIG_MACH_HTCQUARTZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCQUARTZ +# endif +# define machine_is_htcquartz() (machine_arch_type == MACH_TYPE_HTCQUARTZ) +#else +# define machine_is_htcquartz() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM6467TEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM6467TEVM +# endif +# define machine_is_davinci_dm6467tevm() (machine_arch_type == MACH_TYPE_DAVINCI_DM6467TEVM) +#else +# define machine_is_davinci_dm6467tevm() (0) +#endif + +#ifdef CONFIG_MACH_C3AX03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C3AX03 +# endif +# define machine_is_c3ax03() (machine_arch_type == MACH_TYPE_C3AX03) +#else +# define machine_is_c3ax03() (0) +#endif + +#ifdef CONFIG_MACH_MXT_TD60 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXT_TD60 +# endif +# define machine_is_mxt_td60() (machine_arch_type == MACH_TYPE_MXT_TD60) +#else +# define machine_is_mxt_td60() (0) +#endif + +#ifdef CONFIG_MACH_ESYX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESYX +# endif +# define machine_is_esyx() (machine_arch_type == MACH_TYPE_ESYX) +#else +# define machine_is_esyx() (0) +#endif + +#ifdef CONFIG_MACH_DOVE_DB2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOVE_DB2 +# endif +# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB2) +#else +# define machine_is_dove_db2() (0) +#endif + +#ifdef CONFIG_MACH_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BULLDOG +# endif +# define machine_is_bulldog() (machine_arch_type == MACH_TYPE_BULLDOG) +#else +# define machine_is_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_DERELL_ME2000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DERELL_ME2000 +# endif +# define machine_is_derell_me2000() (machine_arch_type == MACH_TYPE_DERELL_ME2000) +#else +# define machine_is_derell_me2000() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_BASE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_BASE +# endif +# define machine_is_bcmring_base() (machine_arch_type == MACH_TYPE_BCMRING_BASE) +#else +# define machine_is_bcmring_base() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM +# endif +# define machine_is_bcmring_evm() (machine_arch_type == MACH_TYPE_BCMRING_EVM) +#else +# define machine_is_bcmring_evm() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM_JAZZ +# endif +# define machine_is_bcmring_evm_jazz() (machine_arch_type == MACH_TYPE_BCMRING_EVM_JAZZ) +#else +# define machine_is_bcmring_evm_jazz() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SP +# endif +# define machine_is_bcmring_sp() (machine_arch_type == MACH_TYPE_BCMRING_SP) +#else +# define machine_is_bcmring_sp() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SV +# endif +# define machine_is_bcmring_sv() (machine_arch_type == MACH_TYPE_BCMRING_SV) +#else +# define machine_is_bcmring_sv() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SV_JAZZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SV_JAZZ +# endif +# define machine_is_bcmring_sv_jazz() (machine_arch_type == MACH_TYPE_BCMRING_SV_JAZZ) +#else +# define machine_is_bcmring_sv_jazz() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_TABLET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_TABLET +# endif +# define machine_is_bcmring_tablet() (machine_arch_type == MACH_TYPE_BCMRING_TABLET) +#else +# define machine_is_bcmring_tablet() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_VP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_VP +# endif +# define machine_is_bcmring_vp() (machine_arch_type == MACH_TYPE_BCMRING_VP) +#else +# define machine_is_bcmring_vp() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_EVM_SEIKOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_EVM_SEIKOR +# endif +# define machine_is_bcmring_evm_seikor() (machine_arch_type == MACH_TYPE_BCMRING_EVM_SEIKOR) +#else +# define machine_is_bcmring_evm_seikor() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_SP_WQVGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_SP_WQVGA +# endif +# define machine_is_bcmring_sp_wqvga() (machine_arch_type == MACH_TYPE_BCMRING_SP_WQVGA) +#else +# define machine_is_bcmring_sp_wqvga() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_CUSTOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_CUSTOM +# endif +# define machine_is_bcmring_custom() (machine_arch_type == MACH_TYPE_BCMRING_CUSTOM) +#else +# define machine_is_bcmring_custom() (0) +#endif + +#ifdef CONFIG_MACH_ACER_S200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_S200 +# endif +# define machine_is_acer_s200() (machine_arch_type == MACH_TYPE_ACER_S200) +#else +# define machine_is_acer_s200() (0) +#endif + +#ifdef CONFIG_MACH_BT270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BT270 +# endif +# define machine_is_bt270() (machine_arch_type == MACH_TYPE_BT270) +#else +# define machine_is_bt270() (0) +#endif + +#ifdef CONFIG_MACH_ISEO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ISEO +# endif +# define machine_is_iseo() (machine_arch_type == MACH_TYPE_ISEO) +#else +# define machine_is_iseo() (0) +#endif + +#ifdef CONFIG_MACH_CEZANNE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEZANNE +# endif +# define machine_is_cezanne() (machine_arch_type == MACH_TYPE_CEZANNE) +#else +# define machine_is_cezanne() (0) +#endif + +#ifdef CONFIG_MACH_LUCCA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUCCA +# endif +# define machine_is_lucca() (machine_arch_type == MACH_TYPE_LUCCA) +#else +# define machine_is_lucca() (0) +#endif + +#ifdef CONFIG_MACH_SUPERSMART +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUPERSMART +# endif +# define machine_is_supersmart() (machine_arch_type == MACH_TYPE_SUPERSMART) +#else +# define machine_is_supersmart() (0) +#endif + +#ifdef CONFIG_MACH_CS_MISANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CS_MISANO +# endif +# define machine_is_arm11_board() (machine_arch_type == MACH_TYPE_CS_MISANO) +#else +# define machine_is_arm11_board() (0) +#endif + +#ifdef CONFIG_MACH_MAGNOLIA2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGNOLIA2 +# endif +# define machine_is_magnolia2() (machine_arch_type == MACH_TYPE_MAGNOLIA2) +#else +# define machine_is_magnolia2() (0) +#endif + +#ifdef CONFIG_MACH_EMXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMXX +# endif +# define machine_is_emxx() (machine_arch_type == MACH_TYPE_EMXX) +#else +# define machine_is_emxx() (0) +#endif + +#ifdef CONFIG_MACH_OUTLAW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OUTLAW +# endif +# define machine_is_outlaw() (machine_arch_type == MACH_TYPE_OUTLAW) +#else +# define machine_is_outlaw() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_BEI2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_BEI2 +# endif +# define machine_is_riot_bei2() (machine_arch_type == MACH_TYPE_RIOT_BEI2) +#else +# define machine_is_riot_bei2() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_VOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_VOX +# endif +# define machine_is_riot_gx2() (machine_arch_type == MACH_TYPE_RIOT_VOX) +#else +# define machine_is_riot_gx2() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_X37 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_X37 +# endif +# define machine_is_riot_x37() (machine_arch_type == MACH_TYPE_RIOT_X37) +#else +# define machine_is_riot_x37() (0) +#endif + +#ifdef CONFIG_MACH_MEGA25MX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEGA25MX +# endif +# define machine_is_mega25mx() (machine_arch_type == MACH_TYPE_MEGA25MX) +#else +# define machine_is_mega25mx() (0) +#endif + +#ifdef CONFIG_MACH_BENZINA2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZINA2 +# endif +# define machine_is_benzina2() (machine_arch_type == MACH_TYPE_BENZINA2) +#else +# define machine_is_benzina2() (0) +#endif + +#ifdef CONFIG_MACH_IGNITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGNITE +# endif +# define machine_is_ignite() (machine_arch_type == MACH_TYPE_IGNITE) +#else +# define machine_is_ignite() (0) +#endif + +#ifdef CONFIG_MACH_FOGGIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FOGGIA +# endif +# define machine_is_foggia() (machine_arch_type == MACH_TYPE_FOGGIA) +#else +# define machine_is_foggia() (0) +#endif + +#ifdef CONFIG_MACH_AREZZO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AREZZO +# endif +# define machine_is_arezzo() (machine_arch_type == MACH_TYPE_AREZZO) +#else +# define machine_is_arezzo() (0) +#endif + +#ifdef CONFIG_MACH_LEICA_SKYWALKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEICA_SKYWALKER +# endif +# define machine_is_leica_skywalker() (machine_arch_type == MACH_TYPE_LEICA_SKYWALKER) +#else +# define machine_is_leica_skywalker() (0) +#endif + +#ifdef CONFIG_MACH_JACINTO2_JAMR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JACINTO2_JAMR +# endif +# define machine_is_jacinto2_jamr() (machine_arch_type == MACH_TYPE_JACINTO2_JAMR) +#else +# define machine_is_jacinto2_jamr() (0) +#endif + +#ifdef CONFIG_MACH_GTS_NOVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTS_NOVA +# endif +# define machine_is_gts_nova() (machine_arch_type == MACH_TYPE_GTS_NOVA) +#else +# define machine_is_gts_nova() (0) +#endif + +#ifdef CONFIG_MACH_P3600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P3600 +# endif +# define machine_is_p3600() (machine_arch_type == MACH_TYPE_P3600) +#else +# define machine_is_p3600() (0) +#endif + +#ifdef CONFIG_MACH_DLT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DLT2 +# endif +# define machine_is_dlt2() (machine_arch_type == MACH_TYPE_DLT2) +#else +# define machine_is_dlt2() (0) +#endif + +#ifdef CONFIG_MACH_DF3120 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DF3120 +# endif +# define machine_is_df3120() (machine_arch_type == MACH_TYPE_DF3120) +#else +# define machine_is_df3120() (0) +#endif + +#ifdef CONFIG_MACH_ECUCORE_9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECUCORE_9G20 +# endif +# define machine_is_ecucore_9g20() (machine_arch_type == MACH_TYPE_ECUCORE_9G20) +#else +# define machine_is_ecucore_9g20() (0) +#endif + +#ifdef CONFIG_MACH_NAUTEL_LPC3240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAUTEL_LPC3240 +# endif +# define machine_is_nautel_lpc3240() (machine_arch_type == MACH_TYPE_NAUTEL_LPC3240) +#else +# define machine_is_nautel_lpc3240() (0) +#endif + +#ifdef CONFIG_MACH_GLACIER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GLACIER +# endif +# define machine_is_glacier() (machine_arch_type == MACH_TYPE_GLACIER) +#else +# define machine_is_glacier() (0) +#endif + +#ifdef CONFIG_MACH_PHRAZER_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHRAZER_BULLDOG +# endif +# define machine_is_phrazer_bulldog() (machine_arch_type == MACH_TYPE_PHRAZER_BULLDOG) +#else +# define machine_is_phrazer_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_BULLDOG +# endif +# define machine_is_omap3_bulldog() (machine_arch_type == MACH_TYPE_OMAP3_BULLDOG) +#else +# define machine_is_omap3_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_PCA101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCA101 +# endif +# define machine_is_pca101() (machine_arch_type == MACH_TYPE_PCA101) +#else +# define machine_is_pca101() (0) +#endif + +#ifdef CONFIG_MACH_BUZZC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUZZC +# endif +# define machine_is_buzzc() (machine_arch_type == MACH_TYPE_BUZZC) +#else +# define machine_is_buzzc() (0) +#endif + +#ifdef CONFIG_MACH_SASIE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SASIE2 +# endif +# define machine_is_sasie2() (machine_arch_type == MACH_TYPE_SASIE2) +#else +# define machine_is_sasie2() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_CIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_CIO +# endif +# define machine_is_davinci_dm6467_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO) +#else +# define machine_is_davinci_dm6467_cio() (0) +#endif + +#ifdef CONFIG_MACH_SMARTMETER_DL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTMETER_DL +# endif +# define machine_is_smartmeter_dl() (machine_arch_type == MACH_TYPE_SMARTMETER_DL) +#else +# define machine_is_smartmeter_dl() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410 +# endif +# define machine_is_wzl6410() (machine_arch_type == MACH_TYPE_WZL6410) +#else +# define machine_is_wzl6410() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410M +# endif +# define machine_is_wzl6410m() (machine_arch_type == MACH_TYPE_WZL6410M) +#else +# define machine_is_wzl6410m() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410F +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410F +# endif +# define machine_is_wzl6410f() (machine_arch_type == MACH_TYPE_WZL6410F) +#else +# define machine_is_wzl6410f() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410I +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410I +# endif +# define machine_is_wzl6410i() (machine_arch_type == MACH_TYPE_WZL6410I) +#else +# define machine_is_wzl6410i() (0) +#endif + +#ifdef CONFIG_MACH_SPACECOM1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPACECOM1 +# endif +# define machine_is_spacecom1() (machine_arch_type == MACH_TYPE_SPACECOM1) +#else +# define machine_is_spacecom1() (0) +#endif + +#ifdef CONFIG_MACH_PINGU920 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PINGU920 +# endif +# define machine_is_pingu920() (machine_arch_type == MACH_TYPE_PINGU920) +#else +# define machine_is_pingu920() (0) +#endif + +#ifdef CONFIG_MACH_BRAVOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRAVOC +# endif +# define machine_is_bravoc() (machine_arch_type == MACH_TYPE_BRAVOC) +#else +# define machine_is_bravoc() (0) +#endif + +#ifdef CONFIG_MACH_CYBO2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBO2440 +# endif +# define machine_is_mydev() (machine_arch_type == MACH_TYPE_CYBO2440) +#else +# define machine_is_mydev() (0) +#endif + +#ifdef CONFIG_MACH_VDSSW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VDSSW +# endif +# define machine_is_vdssw() (machine_arch_type == MACH_TYPE_VDSSW) +#else +# define machine_is_vdssw() (0) +#endif + +#ifdef CONFIG_MACH_ROMULUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROMULUS +# endif +# define machine_is_romulus() (machine_arch_type == MACH_TYPE_ROMULUS) +#else +# define machine_is_romulus() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_MAGIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_MAGIC +# endif +# define machine_is_omap_magic() (machine_arch_type == MACH_TYPE_OMAP_MAGIC) +#else +# define machine_is_omap_magic() (0) +#endif + +#ifdef CONFIG_MACH_ELTD100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELTD100 +# endif +# define machine_is_eltd100() (machine_arch_type == MACH_TYPE_ELTD100) +#else +# define machine_is_eltd100() (0) +#endif + +#ifdef CONFIG_MACH_CAPC7117 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAPC7117 +# endif +# define machine_is_capc7117() (machine_arch_type == MACH_TYPE_CAPC7117) +#else +# define machine_is_capc7117() (0) +#endif + +#ifdef CONFIG_MACH_SWAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWAN +# endif +# define machine_is_swan() (machine_arch_type == MACH_TYPE_SWAN) +#else +# define machine_is_swan() (0) +#endif + +#ifdef CONFIG_MACH_VEU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VEU +# endif +# define machine_is_veu() (machine_arch_type == MACH_TYPE_VEU) +#else +# define machine_is_veu() (0) +#endif + +#ifdef CONFIG_MACH_RM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RM2 +# endif +# define machine_is_rm2() (machine_arch_type == MACH_TYPE_RM2) +#else +# define machine_is_rm2() (0) +#endif + +#ifdef CONFIG_MACH_TT2100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TT2100 +# endif +# define machine_is_tt2100() (machine_arch_type == MACH_TYPE_TT2100) +#else +# define machine_is_tt2100() (0) +#endif + +#ifdef CONFIG_MACH_VENICE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VENICE +# endif +# define machine_is_venice() (machine_arch_type == MACH_TYPE_VENICE) +#else +# define machine_is_venice() (0) +#endif + +#ifdef CONFIG_MACH_PC7323 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7323 +# endif +# define machine_is_pc7323() (machine_arch_type == MACH_TYPE_PC7323) +#else +# define machine_is_pc7323() (0) +#endif + +#ifdef CONFIG_MACH_MASP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MASP +# endif +# define machine_is_masp() (machine_arch_type == MACH_TYPE_MASP) +#else +# define machine_is_masp() (0) +#endif + +#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC +# endif +# define machine_is_fujitsu_tvstbsoc0() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC) +#else +# define machine_is_fujitsu_tvstbsoc0() (0) +#endif + +#ifdef CONFIG_MACH_FUJITSU_TVSTBSOC1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_TVSTBSOC1 +# endif +# define machine_is_fujitsu_tvstbsoc1() (machine_arch_type == MACH_TYPE_FUJITSU_TVSTBSOC1) +#else +# define machine_is_fujitsu_tvstbsoc1() (0) +#endif + +#ifdef CONFIG_MACH_LEXIKON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEXIKON +# endif +# define machine_is_lexikon() (machine_arch_type == MACH_TYPE_LEXIKON) +#else +# define machine_is_lexikon() (0) +#endif + +#ifdef CONFIG_MACH_MINI2440V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI2440V2 +# endif +# define machine_is_mini2440v2() (machine_arch_type == MACH_TYPE_MINI2440V2) +#else +# define machine_is_mini2440v2() (0) +#endif + +#ifdef CONFIG_MACH_ICONTROL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICONTROL +# endif +# define machine_is_icontrol() (machine_arch_type == MACH_TYPE_ICONTROL) +#else +# define machine_is_icontrol() (0) +#endif + +#ifdef CONFIG_MACH_SHEEVAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHEEVAD +# endif +# define machine_is_gplugd() (machine_arch_type == MACH_TYPE_SHEEVAD) +#else +# define machine_is_gplugd() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_ST1_1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_1 +# endif +# define machine_is_qsd8x50a_st1_1() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_1) +#else +# define machine_is_qsd8x50a_st1_1() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_ST1_5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_ST1_5 +# endif +# define machine_is_qsd8x50a_st1_5() (machine_arch_type == MACH_TYPE_QSD8X50A_ST1_5) +#else +# define machine_is_qsd8x50a_st1_5() (0) +#endif + +#ifdef CONFIG_MACH_BEE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEE +# endif +# define machine_is_bee() (machine_arch_type == MACH_TYPE_BEE) +#else +# define machine_is_bee() (0) +#endif + +#ifdef CONFIG_MACH_MX23EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX23EVK +# endif +# define machine_is_mx23evk() (machine_arch_type == MACH_TYPE_MX23EVK) +#else +# define machine_is_mx23evk() (0) +#endif + +#ifdef CONFIG_MACH_AP4EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AP4EVB +# endif +# define machine_is_ap4evb() (machine_arch_type == MACH_TYPE_AP4EVB) +#else +# define machine_is_ap4evb() (0) +#endif + +#ifdef CONFIG_MACH_STOCKHOLM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STOCKHOLM +# endif +# define machine_is_stockholm() (machine_arch_type == MACH_TYPE_STOCKHOLM) +#else +# define machine_is_stockholm() (0) +#endif + +#ifdef CONFIG_MACH_LPC_H3131 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC_H3131 +# endif +# define machine_is_lpc_h3131() (machine_arch_type == MACH_TYPE_LPC_H3131) +#else +# define machine_is_lpc_h3131() (0) +#endif + +#ifdef CONFIG_MACH_STINGRAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STINGRAY +# endif +# define machine_is_stingray() (machine_arch_type == MACH_TYPE_STINGRAY) +#else +# define machine_is_stingray() (0) +#endif + +#ifdef CONFIG_MACH_KRAKEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KRAKEN +# endif +# define machine_is_kraken() (machine_arch_type == MACH_TYPE_KRAKEN) +#else +# define machine_is_kraken() (0) +#endif + +#ifdef CONFIG_MACH_GW2388 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GW2388 +# endif +# define machine_is_gw2388() (machine_arch_type == MACH_TYPE_GW2388) +#else +# define machine_is_gw2388() (0) +#endif + +#ifdef CONFIG_MACH_JADECPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JADECPU +# endif +# define machine_is_jadecpu() (machine_arch_type == MACH_TYPE_JADECPU) +#else +# define machine_is_jadecpu() (0) +#endif + +#ifdef CONFIG_MACH_CARLISLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARLISLE +# endif +# define machine_is_carlisle() (machine_arch_type == MACH_TYPE_CARLISLE) +#else +# define machine_is_carlisle() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SF9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SF9 +# endif +# define machine_is_lux_sf9() (machine_arch_type == MACH_TYPE_LUX_SF9) +#else +# define machine_is_lux_sf9() (0) +#endif + +#ifdef CONFIG_MACH_NEMID_TB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEMID_TB +# endif +# define machine_is_nemid_tb() (machine_arch_type == MACH_TYPE_NEMID_TB) +#else +# define machine_is_nemid_tb() (0) +#endif + +#ifdef CONFIG_MACH_TERRIER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERRIER +# endif +# define machine_is_terrier() (machine_arch_type == MACH_TYPE_TERRIER) +#else +# define machine_is_terrier() (0) +#endif + +#ifdef CONFIG_MACH_TURBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TURBOT +# endif +# define machine_is_turbot() (machine_arch_type == MACH_TYPE_TURBOT) +#else +# define machine_is_turbot() (0) +#endif + +#ifdef CONFIG_MACH_SANDDAB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDDAB +# endif +# define machine_is_sanddab() (machine_arch_type == MACH_TYPE_SANDDAB) +#else +# define machine_is_sanddab() (0) +#endif + +#ifdef CONFIG_MACH_MX35_CICADA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX35_CICADA +# endif +# define machine_is_mx35_cicada() (machine_arch_type == MACH_TYPE_MX35_CICADA) +#else +# define machine_is_mx35_cicada() (0) +#endif + +#ifdef CONFIG_MACH_GHI2703D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GHI2703D +# endif +# define machine_is_ghi2703d() (machine_arch_type == MACH_TYPE_GHI2703D) +#else +# define machine_is_ghi2703d() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SFX9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SFX9 +# endif +# define machine_is_lux_sfx9() (machine_arch_type == MACH_TYPE_LUX_SFX9) +#else +# define machine_is_lux_sfx9() (0) +#endif + +#ifdef CONFIG_MACH_LUX_SF9G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_SF9G +# endif +# define machine_is_lux_sf9g() (machine_arch_type == MACH_TYPE_LUX_SF9G) +#else +# define machine_is_lux_sf9g() (0) +#endif + +#ifdef CONFIG_MACH_LUX_EDK9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUX_EDK9 +# endif +# define machine_is_lux_edk9() (machine_arch_type == MACH_TYPE_LUX_EDK9) +#else +# define machine_is_lux_edk9() (0) +#endif + +#ifdef CONFIG_MACH_HW90240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90240 +# endif +# define machine_is_hw90240() (machine_arch_type == MACH_TYPE_HW90240) +#else +# define machine_is_hw90240() (0) +#endif + +#ifdef CONFIG_MACH_DM365_LEOPARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM365_LEOPARD +# endif +# define machine_is_dm365_leopard() (machine_arch_type == MACH_TYPE_DM365_LEOPARD) +#else +# define machine_is_dm365_leopard() (0) +#endif + +#ifdef CONFIG_MACH_MITYOMAPL138 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MITYOMAPL138 +# endif +# define machine_is_mityomapl138() (machine_arch_type == MACH_TYPE_MITYOMAPL138) +#else +# define machine_is_mityomapl138() (0) +#endif + +#ifdef CONFIG_MACH_SCAT110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCAT110 +# endif +# define machine_is_scat110() (machine_arch_type == MACH_TYPE_SCAT110) +#else +# define machine_is_scat110() (0) +#endif + +#ifdef CONFIG_MACH_ACER_A1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_A1 +# endif +# define machine_is_acer_a1() (machine_arch_type == MACH_TYPE_ACER_A1) +#else +# define machine_is_acer_a1() (0) +#endif + +#ifdef CONFIG_MACH_CMCONTROL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMCONTROL +# endif +# define machine_is_cmcontrol() (machine_arch_type == MACH_TYPE_CMCONTROL) +#else +# define machine_is_cmcontrol() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_LAMAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_LAMAR +# endif +# define machine_is_pelco_lamar() (machine_arch_type == MACH_TYPE_PELCO_LAMAR) +#else +# define machine_is_pelco_lamar() (0) +#endif + +#ifdef CONFIG_MACH_RFP43 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RFP43 +# endif +# define machine_is_rfp43() (machine_arch_type == MACH_TYPE_RFP43) +#else +# define machine_is_rfp43() (0) +#endif + +#ifdef CONFIG_MACH_SK86R0301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SK86R0301 +# endif +# define machine_is_sk86r0301() (machine_arch_type == MACH_TYPE_SK86R0301) +#else +# define machine_is_sk86r0301() (0) +#endif + +#ifdef CONFIG_MACH_CTPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTPXA +# endif +# define machine_is_ctpxa() (machine_arch_type == MACH_TYPE_CTPXA) +#else +# define machine_is_ctpxa() (0) +#endif + +#ifdef CONFIG_MACH_EPB_ARM9_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPB_ARM9_A +# endif +# define machine_is_epb_arm9_a() (machine_arch_type == MACH_TYPE_EPB_ARM9_A) +#else +# define machine_is_epb_arm9_a() (0) +#endif + +#ifdef CONFIG_MACH_GURUPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GURUPLUG +# endif +# define machine_is_guruplug() (machine_arch_type == MACH_TYPE_GURUPLUG) +#else +# define machine_is_guruplug() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR310 +# endif +# define machine_is_spear310() (machine_arch_type == MACH_TYPE_SPEAR310) +#else +# define machine_is_spear310() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR320 +# endif +# define machine_is_spear320() (machine_arch_type == MACH_TYPE_SPEAR320) +#else +# define machine_is_spear320() (0) +#endif + +#ifdef CONFIG_MACH_ROBOTX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROBOTX +# endif +# define machine_is_robotx() (machine_arch_type == MACH_TYPE_ROBOTX) +#else +# define machine_is_robotx() (0) +#endif + +#ifdef CONFIG_MACH_LSXHL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LSXHL +# endif +# define machine_is_lsxhl() (machine_arch_type == MACH_TYPE_LSXHL) +#else +# define machine_is_lsxhl() (0) +#endif + +#ifdef CONFIG_MACH_SMARTLITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTLITE +# endif +# define machine_is_smartlite() (machine_arch_type == MACH_TYPE_SMARTLITE) +#else +# define machine_is_smartlite() (0) +#endif + +#ifdef CONFIG_MACH_CWS2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CWS2 +# endif +# define machine_is_cws2() (machine_arch_type == MACH_TYPE_CWS2) +#else +# define machine_is_cws2() (0) +#endif + +#ifdef CONFIG_MACH_M619 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M619 +# endif +# define machine_is_m619() (machine_arch_type == MACH_TYPE_M619) +#else +# define machine_is_m619() (0) +#endif + +#ifdef CONFIG_MACH_SMARTVIEW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTVIEW +# endif +# define machine_is_smartview() (machine_arch_type == MACH_TYPE_SMARTVIEW) +#else +# define machine_is_smartview() (0) +#endif + +#ifdef CONFIG_MACH_LSA_SALSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LSA_SALSA +# endif +# define machine_is_lsa_salsa() (machine_arch_type == MACH_TYPE_LSA_SALSA) +#else +# define machine_is_lsa_salsa() (0) +#endif + +#ifdef CONFIG_MACH_KIZBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIZBOX +# endif +# define machine_is_kizbox() (machine_arch_type == MACH_TYPE_KIZBOX) +#else +# define machine_is_kizbox() (0) +#endif + +#ifdef CONFIG_MACH_HTCCHARMER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCCHARMER +# endif +# define machine_is_htccharmer() (machine_arch_type == MACH_TYPE_HTCCHARMER) +#else +# define machine_is_htccharmer() (0) +#endif + +#ifdef CONFIG_MACH_GUF_NESO_LT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUF_NESO_LT +# endif +# define machine_is_guf_neso_lt() (machine_arch_type == MACH_TYPE_GUF_NESO_LT) +#else +# define machine_is_guf_neso_lt() (0) +#endif + +#ifdef CONFIG_MACH_PM9G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PM9G45 +# endif +# define machine_is_pm9g45() (machine_arch_type == MACH_TYPE_PM9G45) +#else +# define machine_is_pm9g45() (0) +#endif + +#ifdef CONFIG_MACH_HTCPANTHER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPANTHER +# endif +# define machine_is_htcpanther() (machine_arch_type == MACH_TYPE_HTCPANTHER) +#else +# define machine_is_htcpanther() (0) +#endif + +#ifdef CONFIG_MACH_HTCPANTHER_CDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPANTHER_CDMA +# endif +# define machine_is_htcpanther_cdma() (machine_arch_type == MACH_TYPE_HTCPANTHER_CDMA) +#else +# define machine_is_htcpanther_cdma() (0) +#endif + +#ifdef CONFIG_MACH_REB01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REB01 +# endif +# define machine_is_reb01() (machine_arch_type == MACH_TYPE_REB01) +#else +# define machine_is_reb01() (0) +#endif + +#ifdef CONFIG_MACH_AQUILA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AQUILA +# endif +# define machine_is_aquila() (machine_arch_type == MACH_TYPE_AQUILA) +#else +# define machine_is_aquila() (0) +#endif + +#ifdef CONFIG_MACH_SPARK_SLS_HW2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPARK_SLS_HW2 +# endif +# define machine_is_spark_sls_hw2() (machine_arch_type == MACH_TYPE_SPARK_SLS_HW2) +#else +# define machine_is_spark_sls_hw2() (0) +#endif + +#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESATA_SHEEVAPLUG +# endif +# define machine_is_sheeva_esata() (machine_arch_type == MACH_TYPE_ESATA_SHEEVAPLUG) +#else +# define machine_is_sheeva_esata() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_SURF +# endif +# define machine_is_msm7x30_surf() (machine_arch_type == MACH_TYPE_MSM7X30_SURF) +#else +# define machine_is_msm7x30_surf() (0) +#endif + +#ifdef CONFIG_MACH_MICRO2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO2440 +# endif +# define machine_is_micro2440() (machine_arch_type == MACH_TYPE_MICRO2440) +#else +# define machine_is_micro2440() (0) +#endif + +#ifdef CONFIG_MACH_AM2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AM2440 +# endif +# define machine_is_am2440() (machine_arch_type == MACH_TYPE_AM2440) +#else +# define machine_is_am2440() (0) +#endif + +#ifdef CONFIG_MACH_TQ2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TQ2440 +# endif +# define machine_is_tq2440() (machine_arch_type == MACH_TYPE_TQ2440) +#else +# define machine_is_tq2440() (0) +#endif + +#ifdef CONFIG_MACH_LPC2478OEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC2478OEM +# endif +# define machine_is_lpc2478oem() (machine_arch_type == MACH_TYPE_LPC2478OEM) +#else +# define machine_is_lpc2478oem() (0) +#endif + +#ifdef CONFIG_MACH_AK880X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AK880X +# endif +# define machine_is_ak880x() (machine_arch_type == MACH_TYPE_AK880X) +#else +# define machine_is_ak880x() (0) +#endif + +#ifdef CONFIG_MACH_COBRA3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COBRA3530 +# endif +# define machine_is_cobra3530() (machine_arch_type == MACH_TYPE_COBRA3530) +#else +# define machine_is_cobra3530() (0) +#endif + +#ifdef CONFIG_MACH_PMPPB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PMPPB +# endif +# define machine_is_pmppb() (machine_arch_type == MACH_TYPE_PMPPB) +#else +# define machine_is_pmppb() (0) +#endif + +#ifdef CONFIG_MACH_U6715 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U6715 +# endif +# define machine_is_u6715() (machine_arch_type == MACH_TYPE_U6715) +#else +# define machine_is_u6715() (0) +#endif + +#ifdef CONFIG_MACH_AXAR1500_SENDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXAR1500_SENDER +# endif +# define machine_is_axar1500_sender() (machine_arch_type == MACH_TYPE_AXAR1500_SENDER) +#else +# define machine_is_axar1500_sender() (0) +#endif + +#ifdef CONFIG_MACH_G30_DVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G30_DVB +# endif +# define machine_is_g30_dvb() (machine_arch_type == MACH_TYPE_G30_DVB) +#else +# define machine_is_g30_dvb() (0) +#endif + +#ifdef CONFIG_MACH_VC088X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC088X +# endif +# define machine_is_vc088x() (machine_arch_type == MACH_TYPE_VC088X) +#else +# define machine_is_vc088x() (0) +#endif + +#ifdef CONFIG_MACH_MIOA702 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIOA702 +# endif +# define machine_is_mioa702() (machine_arch_type == MACH_TYPE_MIOA702) +#else +# define machine_is_mioa702() (0) +#endif + +#ifdef CONFIG_MACH_HPMIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPMIN +# endif +# define machine_is_hpmin() (machine_arch_type == MACH_TYPE_HPMIN) +#else +# define machine_is_hpmin() (0) +#endif + +#ifdef CONFIG_MACH_AK880XAK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AK880XAK +# endif +# define machine_is_ak880xak() (machine_arch_type == MACH_TYPE_AK880XAK) +#else +# define machine_is_ak880xak() (0) +#endif + +#ifdef CONFIG_MACH_ARM926TOMAP850 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM926TOMAP850 +# endif +# define machine_is_arm926tomap850() (machine_arch_type == MACH_TYPE_ARM926TOMAP850) +#else +# define machine_is_arm926tomap850() (0) +#endif + +#ifdef CONFIG_MACH_LKEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LKEVM +# endif +# define machine_is_lkevm() (machine_arch_type == MACH_TYPE_LKEVM) +#else +# define machine_is_lkevm() (0) +#endif + +#ifdef CONFIG_MACH_MW6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW6410 +# endif +# define machine_is_mw6410() (machine_arch_type == MACH_TYPE_MW6410) +#else +# define machine_is_mw6410() (0) +#endif + +#ifdef CONFIG_MACH_TERASTATION_WXL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERASTATION_WXL +# endif +# define machine_is_terastation_wxl() (machine_arch_type == MACH_TYPE_TERASTATION_WXL) +#else +# define machine_is_terastation_wxl() (0) +#endif + +#ifdef CONFIG_MACH_CPU8000E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPU8000E +# endif +# define machine_is_cpu8000e() (machine_arch_type == MACH_TYPE_CPU8000E) +#else +# define machine_is_cpu8000e() (0) +#endif + +#ifdef CONFIG_MACH_CATANIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATANIA +# endif +# define machine_is_catania() (machine_arch_type == MACH_TYPE_CATANIA) +#else +# define machine_is_catania() (0) +#endif + +#ifdef CONFIG_MACH_TOKYO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOKYO +# endif +# define machine_is_tokyo() (machine_arch_type == MACH_TYPE_TOKYO) +#else +# define machine_is_tokyo() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A_SURF +# endif +# define machine_is_msm7201a_surf() (machine_arch_type == MACH_TYPE_MSM7201A_SURF) +#else +# define machine_is_msm7201a_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A_FFA +# endif +# define machine_is_msm7201a_ffa() (machine_arch_type == MACH_TYPE_MSM7201A_FFA) +#else +# define machine_is_msm7201a_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X25_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X25_SURF +# endif +# define machine_is_msm7x25_surf() (machine_arch_type == MACH_TYPE_MSM7X25_SURF) +#else +# define machine_is_msm7x25_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X25_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X25_FFA +# endif +# define machine_is_msm7x25_ffa() (machine_arch_type == MACH_TYPE_MSM7X25_FFA) +#else +# define machine_is_msm7x25_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X27_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X27_SURF +# endif +# define machine_is_msm7x27_surf() (machine_arch_type == MACH_TYPE_MSM7X27_SURF) +#else +# define machine_is_msm7x27_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X27_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X27_FFA +# endif +# define machine_is_msm7x27_ffa() (machine_arch_type == MACH_TYPE_MSM7X27_FFA) +#else +# define machine_is_msm7x27_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_FFA +# endif +# define machine_is_msm7x30_ffa() (machine_arch_type == MACH_TYPE_MSM7X30_FFA) +#else +# define machine_is_msm7x30_ffa() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_SURF +# endif +# define machine_is_qsd8x50_surf() (machine_arch_type == MACH_TYPE_QSD8X50_SURF) +#else +# define machine_is_qsd8x50_surf() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_COMET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_COMET +# endif +# define machine_is_qsd8x50_comet() (machine_arch_type == MACH_TYPE_QSD8X50_COMET) +#else +# define machine_is_qsd8x50_comet() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50_FFA +# endif +# define machine_is_qsd8x50_ffa() (machine_arch_type == MACH_TYPE_QSD8X50_FFA) +#else +# define machine_is_qsd8x50_ffa() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_SURF +# endif +# define machine_is_qsd8x50a_surf() (machine_arch_type == MACH_TYPE_QSD8X50A_SURF) +#else +# define machine_is_qsd8x50a_surf() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X50A_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X50A_FFA +# endif +# define machine_is_qsd8x50a_ffa() (machine_arch_type == MACH_TYPE_QSD8X50A_FFA) +#else +# define machine_is_qsd8x50a_ffa() (0) +#endif + +#ifdef CONFIG_MACH_ADX_XGCP10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADX_XGCP10 +# endif +# define machine_is_adx_xgcp10() (machine_arch_type == MACH_TYPE_ADX_XGCP10) +#else +# define machine_is_adx_xgcp10() (0) +#endif + +#ifdef CONFIG_MACH_MCGWUMTS2A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCGWUMTS2A +# endif +# define machine_is_mcgwumts2a() (machine_arch_type == MACH_TYPE_MCGWUMTS2A) +#else +# define machine_is_mcgwumts2a() (0) +#endif + +#ifdef CONFIG_MACH_MOBIKT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOBIKT +# endif +# define machine_is_mobikt() (machine_arch_type == MACH_TYPE_MOBIKT) +#else +# define machine_is_mobikt() (0) +#endif + +#ifdef CONFIG_MACH_MX53_EVK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX53_EVK +# endif +# define machine_is_mx53_evk() (machine_arch_type == MACH_TYPE_MX53_EVK) +#else +# define machine_is_mx53_evk() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0030 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0030 +# endif +# define machine_is_igep0030() (machine_arch_type == MACH_TYPE_IGEP0030) +#else +# define machine_is_igep0030() (0) +#endif + +#ifdef CONFIG_MACH_AXELL_H40_H50_CTRL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXELL_H40_H50_CTRL +# endif +# define machine_is_axell_h40_h50_ctrl() (machine_arch_type == MACH_TYPE_AXELL_H40_H50_CTRL) +#else +# define machine_is_axell_h40_h50_ctrl() (0) +#endif + +#ifdef CONFIG_MACH_DTCOMMOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DTCOMMOD +# endif +# define machine_is_dtcommod() (machine_arch_type == MACH_TYPE_DTCOMMOD) +#else +# define machine_is_dtcommod() (0) +#endif + +#ifdef CONFIG_MACH_GOULD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GOULD +# endif +# define machine_is_gould() (machine_arch_type == MACH_TYPE_GOULD) +#else +# define machine_is_gould() (0) +#endif + +#ifdef CONFIG_MACH_SIBERIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIBERIA +# endif +# define machine_is_siberia() (machine_arch_type == MACH_TYPE_SIBERIA) +#else +# define machine_is_siberia() (0) +#endif + +#ifdef CONFIG_MACH_SBC3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC3530 +# endif +# define machine_is_sbc3530() (machine_arch_type == MACH_TYPE_SBC3530) +#else +# define machine_is_sbc3530() (0) +#endif + +#ifdef CONFIG_MACH_QARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QARM +# endif +# define machine_is_qarm() (machine_arch_type == MACH_TYPE_QARM) +#else +# define machine_is_qarm() (0) +#endif + +#ifdef CONFIG_MACH_MIPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIPS +# endif +# define machine_is_mips() (machine_arch_type == MACH_TYPE_MIPS) +#else +# define machine_is_mips() (0) +#endif + +#ifdef CONFIG_MACH_MX27GRB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27GRB +# endif +# define machine_is_mx27grb() (machine_arch_type == MACH_TYPE_MX27GRB) +#else +# define machine_is_mx27grb() (0) +#endif + +#ifdef CONFIG_MACH_SBC8100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC8100 +# endif +# define machine_is_sbc8100() (machine_arch_type == MACH_TYPE_SBC8100) +#else +# define machine_is_sbc8100() (0) +#endif + +#ifdef CONFIG_MACH_SAARB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAARB +# endif +# define machine_is_saarb() (machine_arch_type == MACH_TYPE_SAARB) +#else +# define machine_is_saarb() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3MINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3MINI +# endif +# define machine_is_omap3mini() (machine_arch_type == MACH_TYPE_OMAP3MINI) +#else +# define machine_is_omap3mini() (0) +#endif + +#ifdef CONFIG_MACH_CNMBOOK7SE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNMBOOK7SE +# endif +# define machine_is_cnmbook7se() (machine_arch_type == MACH_TYPE_CNMBOOK7SE) +#else +# define machine_is_cnmbook7se() (0) +#endif + +#ifdef CONFIG_MACH_CATAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATAN +# endif +# define machine_is_catan() (machine_arch_type == MACH_TYPE_CATAN) +#else +# define machine_is_catan() (0) +#endif + +#ifdef CONFIG_MACH_HARMONY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HARMONY +# endif +# define machine_is_harmony() (machine_arch_type == MACH_TYPE_HARMONY) +#else +# define machine_is_harmony() (0) +#endif + +#ifdef CONFIG_MACH_TONGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TONGA +# endif +# define machine_is_tonga() (machine_arch_type == MACH_TYPE_TONGA) +#else +# define machine_is_tonga() (0) +#endif + +#ifdef CONFIG_MACH_CYBOOK_ORIZON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBOOK_ORIZON +# endif +# define machine_is_cybook_orizon() (machine_arch_type == MACH_TYPE_CYBOOK_ORIZON) +#else +# define machine_is_cybook_orizon() (0) +#endif + +#ifdef CONFIG_MACH_HTCRHODIUMCDMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRHODIUMCDMA +# endif +# define machine_is_htcrhodiumcdma() (machine_arch_type == MACH_TYPE_HTCRHODIUMCDMA) +#else +# define machine_is_htcrhodiumcdma() (0) +#endif + +#ifdef CONFIG_MACH_EPC_G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPC_G45 +# endif +# define machine_is_epc_g45() (machine_arch_type == MACH_TYPE_EPC_G45) +#else +# define machine_is_epc_g45() (0) +#endif + +#ifdef CONFIG_MACH_EPC_LPC3250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPC_LPC3250 +# endif +# define machine_is_epc_lpc3250() (machine_arch_type == MACH_TYPE_EPC_LPC3250) +#else +# define machine_is_epc_lpc3250() (0) +#endif + +#ifdef CONFIG_MACH_MXC91341EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC91341EVB +# endif +# define machine_is_mxc91341evb() (machine_arch_type == MACH_TYPE_MXC91341EVB) +#else +# define machine_is_mxc91341evb() (0) +#endif + +#ifdef CONFIG_MACH_RTW1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTW1000 +# endif +# define machine_is_rtw1000() (machine_arch_type == MACH_TYPE_RTW1000) +#else +# define machine_is_rtw1000() (0) +#endif + +#ifdef CONFIG_MACH_BOBCAT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BOBCAT +# endif +# define machine_is_bobcat() (machine_arch_type == MACH_TYPE_BOBCAT) +#else +# define machine_is_bobcat() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS6 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS6 +# endif +# define machine_is_trizeps6() (machine_arch_type == MACH_TYPE_TRIZEPS6) +#else +# define machine_is_trizeps6() (0) +#endif + +#ifdef CONFIG_MACH_MSM7X30_FLUID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7X30_FLUID +# endif +# define machine_is_msm7x30_fluid() (machine_arch_type == MACH_TYPE_MSM7X30_FLUID) +#else +# define machine_is_msm7x30_fluid() (0) +#endif + +#ifdef CONFIG_MACH_NEDAP9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEDAP9263 +# endif +# define machine_is_nedap9263() (machine_arch_type == MACH_TYPE_NEDAP9263) +#else +# define machine_is_nedap9263() (0) +#endif + +#ifdef CONFIG_MACH_NETGEAR_MS2110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETGEAR_MS2110 +# endif +# define machine_is_netgear_ms2110() (machine_arch_type == MACH_TYPE_NETGEAR_MS2110) +#else +# define machine_is_netgear_ms2110() (0) +#endif + +#ifdef CONFIG_MACH_BMX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BMX +# endif +# define machine_is_bmx() (machine_arch_type == MACH_TYPE_BMX) +#else +# define machine_is_bmx() (0) +#endif + +#ifdef CONFIG_MACH_NETSTREAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSTREAM +# endif +# define machine_is_netstream() (machine_arch_type == MACH_TYPE_NETSTREAM) +#else +# define machine_is_netstream() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT_RCU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT_RCU +# endif +# define machine_is_vpnext_rcu() (machine_arch_type == MACH_TYPE_VPNEXT_RCU) +#else +# define machine_is_vpnext_rcu() (0) +#endif + +#ifdef CONFIG_MACH_VPNEXT_MPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPNEXT_MPU +# endif +# define machine_is_vpnext_mpu() (machine_arch_type == MACH_TYPE_VPNEXT_MPU) +#else +# define machine_is_vpnext_mpu() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING_TABLET_V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING_TABLET_V1 +# endif +# define machine_is_bcmring_tablet_v1() (machine_arch_type == MACH_TYPE_BCMRING_TABLET_V1) +#else +# define machine_is_bcmring_tablet_v1() (0) +#endif + +#ifdef CONFIG_MACH_SGARM10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGARM10 +# endif +# define machine_is_sgarm10() (machine_arch_type == MACH_TYPE_SGARM10) +#else +# define machine_is_sgarm10() (0) +#endif + +#ifdef CONFIG_MACH_CM_T3517 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_T3517 +# endif +# define machine_is_cm_t3517() (machine_arch_type == MACH_TYPE_CM_T3517) +#else +# define machine_is_cm_t3517() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_CPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_CPS +# endif +# define machine_is_omap3_cps() (machine_arch_type == MACH_TYPE_OMAP3_CPS) +#else +# define machine_is_omap3_cps() (0) +#endif + +#ifdef CONFIG_MACH_AXAR1500_RECEIVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AXAR1500_RECEIVER +# endif +# define machine_is_axar1500_receiver() (machine_arch_type == MACH_TYPE_AXAR1500_RECEIVER) +#else +# define machine_is_axar1500_receiver() (0) +#endif + +#ifdef CONFIG_MACH_WBD222 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WBD222 +# endif +# define machine_is_wbd222() (machine_arch_type == MACH_TYPE_WBD222) +#else +# define machine_is_wbd222() (0) +#endif + +#ifdef CONFIG_MACH_MT65XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MT65XX +# endif +# define machine_is_mt65xx() (machine_arch_type == MACH_TYPE_MT65XX) +#else +# define machine_is_mt65xx() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_SURF +# endif +# define machine_is_msm8x60_surf() (machine_arch_type == MACH_TYPE_MSM8X60_SURF) +#else +# define machine_is_msm8x60_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_SIM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_SIM +# endif +# define machine_is_msm8x60_sim() (machine_arch_type == MACH_TYPE_MSM8X60_SIM) +#else +# define machine_is_msm8x60_sim() (0) +#endif + +#ifdef CONFIG_MACH_VMC300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMC300 +# endif +# define machine_is_vmc300() (machine_arch_type == MACH_TYPE_VMC300) +#else +# define machine_is_vmc300() (0) +#endif + +#ifdef CONFIG_MACH_TCC8000_SDK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TCC8000_SDK +# endif +# define machine_is_tcc8000_sdk() (machine_arch_type == MACH_TYPE_TCC8000_SDK) +#else +# define machine_is_tcc8000_sdk() (0) +#endif + +#ifdef CONFIG_MACH_NANOS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NANOS +# endif +# define machine_is_nanos() (machine_arch_type == MACH_TYPE_NANOS) +#else +# define machine_is_nanos() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9G10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9G10 +# endif +# define machine_is_stamp9g10() (machine_arch_type == MACH_TYPE_STAMP9G10) +#else +# define machine_is_stamp9g10() (0) +#endif + +#ifdef CONFIG_MACH_STAMP9G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAMP9G45 +# endif +# define machine_is_stamp9g45() (machine_arch_type == MACH_TYPE_STAMP9G45) +#else +# define machine_is_stamp9g45() (0) +#endif + +#ifdef CONFIG_MACH_H6053 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_H6053 +# endif +# define machine_is_h6053() (machine_arch_type == MACH_TYPE_H6053) +#else +# define machine_is_h6053() (0) +#endif + +#ifdef CONFIG_MACH_SMINT01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMINT01 +# endif +# define machine_is_smint01() (machine_arch_type == MACH_TYPE_SMINT01) +#else +# define machine_is_smint01() (0) +#endif + +#ifdef CONFIG_MACH_PRTLVT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRTLVT2 +# endif +# define machine_is_prtlvt2() (machine_arch_type == MACH_TYPE_PRTLVT2) +#else +# define machine_is_prtlvt2() (0) +#endif + +#ifdef CONFIG_MACH_AP420 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AP420 +# endif +# define machine_is_ap420() (machine_arch_type == MACH_TYPE_AP420) +#else +# define machine_is_ap420() (0) +#endif + +#ifdef CONFIG_MACH_HTCSHIFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCSHIFT +# endif +# define machine_is_htcclio() (machine_arch_type == MACH_TYPE_HTCSHIFT) +#else +# define machine_is_htcclio() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM365_FC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM365_FC +# endif +# define machine_is_davinci_dm365_fc() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_FC) +#else +# define machine_is_davinci_dm365_fc() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_SURF +# endif +# define machine_is_msm8x55_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SURF) +#else +# define machine_is_msm8x55_surf() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_FFA +# endif +# define machine_is_msm8x55_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_FFA) +#else +# define machine_is_msm8x55_ffa() (0) +#endif + +#ifdef CONFIG_MACH_ESL_VAMANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_VAMANA +# endif +# define machine_is_esl_vamana() (machine_arch_type == MACH_TYPE_ESL_VAMANA) +#else +# define machine_is_esl_vamana() (0) +#endif + +#ifdef CONFIG_MACH_SBC35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC35 +# endif +# define machine_is_sbc35() (machine_arch_type == MACH_TYPE_SBC35) +#else +# define machine_is_sbc35() (0) +#endif + +#ifdef CONFIG_MACH_MPX6446 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MPX6446 +# endif +# define machine_is_mpx6446() (machine_arch_type == MACH_TYPE_MPX6446) +#else +# define machine_is_mpx6446() (0) +#endif + +#ifdef CONFIG_MACH_OREO_CONTROLLER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OREO_CONTROLLER +# endif +# define machine_is_oreo_controller() (machine_arch_type == MACH_TYPE_OREO_CONTROLLER) +#else +# define machine_is_oreo_controller() (0) +#endif + +#ifdef CONFIG_MACH_KOPIN_MODELS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KOPIN_MODELS +# endif +# define machine_is_kopin_models() (machine_arch_type == MACH_TYPE_KOPIN_MODELS) +#else +# define machine_is_kopin_models() (0) +#endif + +#ifdef CONFIG_MACH_TTC_VISION2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TTC_VISION2 +# endif +# define machine_is_ttc_vision2() (machine_arch_type == MACH_TYPE_TTC_VISION2) +#else +# define machine_is_ttc_vision2() (0) +#endif + +#ifdef CONFIG_MACH_CNS3420VB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CNS3420VB +# endif +# define machine_is_cns3420vb() (machine_arch_type == MACH_TYPE_CNS3420VB) +#else +# define machine_is_cns3420vb() (0) +#endif + +#ifdef CONFIG_MACH_LPC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC2 +# endif +# define machine_is_lpc_evo() (machine_arch_type == MACH_TYPE_LPC2) +#else +# define machine_is_lpc_evo() (0) +#endif + +#ifdef CONFIG_MACH_OLYMPUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OLYMPUS +# endif +# define machine_is_olympus() (machine_arch_type == MACH_TYPE_OLYMPUS) +#else +# define machine_is_olympus() (0) +#endif + +#ifdef CONFIG_MACH_VORTEX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VORTEX +# endif +# define machine_is_vortex() (machine_arch_type == MACH_TYPE_VORTEX) +#else +# define machine_is_vortex() (0) +#endif + +#ifdef CONFIG_MACH_S5PC200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5PC200 +# endif +# define machine_is_s5pc200() (machine_arch_type == MACH_TYPE_S5PC200) +#else +# define machine_is_s5pc200() (0) +#endif + +#ifdef CONFIG_MACH_ECUCORE_9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECUCORE_9263 +# endif +# define machine_is_ecucore_9263() (machine_arch_type == MACH_TYPE_ECUCORE_9263) +#else +# define machine_is_ecucore_9263() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC200 +# endif +# define machine_is_smdkc200() (machine_arch_type == MACH_TYPE_SMDKC200) +#else +# define machine_is_smdkc200() (0) +#endif + +#ifdef CONFIG_MACH_EMSISO_SX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMSISO_SX27 +# endif +# define machine_is_emsiso_sx27() (machine_arch_type == MACH_TYPE_EMSISO_SX27) +#else +# define machine_is_emsiso_sx27() (0) +#endif + +#ifdef CONFIG_MACH_APX_SOM9G45_EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APX_SOM9G45_EK +# endif +# define machine_is_apx_som9g45_ek() (machine_arch_type == MACH_TYPE_APX_SOM9G45_EK) +#else +# define machine_is_apx_som9g45_ek() (0) +#endif + +#ifdef CONFIG_MACH_SONGSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SONGSHAN +# endif +# define machine_is_songshan() (machine_arch_type == MACH_TYPE_SONGSHAN) +#else +# define machine_is_songshan() (0) +#endif + +#ifdef CONFIG_MACH_TIANSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIANSHAN +# endif +# define machine_is_tianshan() (machine_arch_type == MACH_TYPE_TIANSHAN) +#else +# define machine_is_tianshan() (0) +#endif + +#ifdef CONFIG_MACH_VPX500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPX500 +# endif +# define machine_is_vpx500() (machine_arch_type == MACH_TYPE_VPX500) +#else +# define machine_is_vpx500() (0) +#endif + +#ifdef CONFIG_MACH_AM3517SAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AM3517SAM +# endif +# define machine_is_am3517sam() (machine_arch_type == MACH_TYPE_AM3517SAM) +#else +# define machine_is_am3517sam() (0) +#endif + +#ifdef CONFIG_MACH_SKAT91_SIM508 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKAT91_SIM508 +# endif +# define machine_is_skat91_sim508() (machine_arch_type == MACH_TYPE_SKAT91_SIM508) +#else +# define machine_is_skat91_sim508() (0) +#endif + +#ifdef CONFIG_MACH_SKAT91_S3E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKAT91_S3E +# endif +# define machine_is_skat91_s3e() (machine_arch_type == MACH_TYPE_SKAT91_S3E) +#else +# define machine_is_skat91_s3e() (0) +#endif + +#ifdef CONFIG_MACH_OMAP4_PANDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP4_PANDA +# endif +# define machine_is_omap4_panda() (machine_arch_type == MACH_TYPE_OMAP4_PANDA) +#else +# define machine_is_omap4_panda() (0) +#endif + +#ifdef CONFIG_MACH_DF7220 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DF7220 +# endif +# define machine_is_df7220() (machine_arch_type == MACH_TYPE_DF7220) +#else +# define machine_is_df7220() (0) +#endif + +#ifdef CONFIG_MACH_NEMINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEMINI +# endif +# define machine_is_nemini() (machine_arch_type == MACH_TYPE_NEMINI) +#else +# define machine_is_nemini() (0) +#endif + +#ifdef CONFIG_MACH_T8200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T8200 +# endif +# define machine_is_t8200() (machine_arch_type == MACH_TYPE_T8200) +#else +# define machine_is_t8200() (0) +#endif + +#ifdef CONFIG_MACH_APF51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APF51 +# endif +# define machine_is_apf51() (machine_arch_type == MACH_TYPE_APF51) +#else +# define machine_is_apf51() (0) +#endif + +#ifdef CONFIG_MACH_DR_RC_UNIT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DR_RC_UNIT +# endif +# define machine_is_dr_rc_unit() (machine_arch_type == MACH_TYPE_DR_RC_UNIT) +#else +# define machine_is_dr_rc_unit() (0) +#endif + +#ifdef CONFIG_MACH_BORDEAUX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BORDEAUX +# endif +# define machine_is_bordeaux() (machine_arch_type == MACH_TYPE_BORDEAUX) +#else +# define machine_is_bordeaux() (0) +#endif + +#ifdef CONFIG_MACH_CATANIA_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CATANIA_B +# endif +# define machine_is_catania_b() (machine_arch_type == MACH_TYPE_CATANIA_B) +#else +# define machine_is_catania_b() (0) +#endif + +#ifdef CONFIG_MACH_MX51_OCEAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_OCEAN +# endif +# define machine_is_mx51_ocean() (machine_arch_type == MACH_TYPE_MX51_OCEAN) +#else +# define machine_is_mx51_ocean() (0) +#endif + +#ifdef CONFIG_MACH_TI8168EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TI8168EVM +# endif +# define machine_is_ti8168evm() (machine_arch_type == MACH_TYPE_TI8168EVM) +#else +# define machine_is_ti8168evm() (0) +#endif + +#ifdef CONFIG_MACH_NEOCOREOMAP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEOCOREOMAP +# endif +# define machine_is_neocoreomap() (machine_arch_type == MACH_TYPE_NEOCOREOMAP) +#else +# define machine_is_neocoreomap() (0) +#endif + +#ifdef CONFIG_MACH_WITHINGS_WBP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WITHINGS_WBP +# endif +# define machine_is_withings_wbp() (machine_arch_type == MACH_TYPE_WITHINGS_WBP) +#else +# define machine_is_withings_wbp() (0) +#endif + +#ifdef CONFIG_MACH_DBPS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DBPS +# endif +# define machine_is_dbps() (machine_arch_type == MACH_TYPE_DBPS) +#else +# define machine_is_dbps() (0) +#endif + +#ifdef CONFIG_MACH_SBC9261 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC9261 +# endif +# define machine_is_at91sam9261() (machine_arch_type == MACH_TYPE_SBC9261) +#else +# define machine_is_at91sam9261() (0) +#endif + +#ifdef CONFIG_MACH_PCBFP0001 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCBFP0001 +# endif +# define machine_is_pcbfp0001() (machine_arch_type == MACH_TYPE_PCBFP0001) +#else +# define machine_is_pcbfp0001() (0) +#endif + +#ifdef CONFIG_MACH_SPEEDY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEEDY +# endif +# define machine_is_speedy() (machine_arch_type == MACH_TYPE_SPEEDY) +#else +# define machine_is_speedy() (0) +#endif + +#ifdef CONFIG_MACH_CHRYSAOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHRYSAOR +# endif +# define machine_is_chrysaor() (machine_arch_type == MACH_TYPE_CHRYSAOR) +#else +# define machine_is_chrysaor() (0) +#endif + +#ifdef CONFIG_MACH_TANGO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TANGO +# endif +# define machine_is_tango() (machine_arch_type == MACH_TYPE_TANGO) +#else +# define machine_is_tango() (0) +#endif + +#ifdef CONFIG_MACH_SYNOLOGY_DSX11 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYNOLOGY_DSX11 +# endif +# define machine_is_synology_dsx11() (machine_arch_type == MACH_TYPE_SYNOLOGY_DSX11) +#else +# define machine_is_synology_dsx11() (0) +#endif + +#ifdef CONFIG_MACH_HANLIN_V3EXT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HANLIN_V3EXT +# endif +# define machine_is_hanlin_v3ext() (machine_arch_type == MACH_TYPE_HANLIN_V3EXT) +#else +# define machine_is_hanlin_v3ext() (0) +#endif + +#ifdef CONFIG_MACH_HANLIN_V5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HANLIN_V5 +# endif +# define machine_is_hanlin_v5() (machine_arch_type == MACH_TYPE_HANLIN_V5) +#else +# define machine_is_hanlin_v5() (0) +#endif + +#ifdef CONFIG_MACH_HANLIN_V3PLUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HANLIN_V3PLUS +# endif +# define machine_is_hanlin_v3plus() (machine_arch_type == MACH_TYPE_HANLIN_V3PLUS) +#else +# define machine_is_hanlin_v3plus() (0) +#endif + +#ifdef CONFIG_MACH_IRIVER_STORY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IRIVER_STORY +# endif +# define machine_is_iriver_story() (machine_arch_type == MACH_TYPE_IRIVER_STORY) +#else +# define machine_is_iriver_story() (0) +#endif + +#ifdef CONFIG_MACH_IREX_ILIAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IREX_ILIAD +# endif +# define machine_is_irex_iliad() (machine_arch_type == MACH_TYPE_IREX_ILIAD) +#else +# define machine_is_irex_iliad() (0) +#endif + +#ifdef CONFIG_MACH_IREX_DR1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IREX_DR1000 +# endif +# define machine_is_irex_dr1000() (machine_arch_type == MACH_TYPE_IREX_DR1000) +#else +# define machine_is_irex_dr1000() (0) +#endif + +#ifdef CONFIG_MACH_TETON_BGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TETON_BGA +# endif +# define machine_is_teton_bga() (machine_arch_type == MACH_TYPE_TETON_BGA) +#else +# define machine_is_teton_bga() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPER9G45 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPER9G45 +# endif +# define machine_is_snapper9g45() (machine_arch_type == MACH_TYPE_SNAPPER9G45) +#else +# define machine_is_snapper9g45() (0) +#endif + +#ifdef CONFIG_MACH_TAM3517 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAM3517 +# endif +# define machine_is_tam3517() (machine_arch_type == MACH_TYPE_TAM3517) +#else +# define machine_is_tam3517() (0) +#endif + +#ifdef CONFIG_MACH_PDC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PDC100 +# endif +# define machine_is_pdc100() (machine_arch_type == MACH_TYPE_PDC100) +#else +# define machine_is_pdc100() (0) +#endif + +#ifdef CONFIG_MACH_EUKREA_CPUIMX25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX25 +# endif +# define machine_is_eukrea_cpuimx25sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX25) +#else +# define machine_is_eukrea_cpuimx25sd() (0) +#endif + +#ifdef CONFIG_MACH_EUKREA_CPUIMX35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX35 +# endif +# define machine_is_eukrea_cpuimx35sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX35) +#else +# define machine_is_eukrea_cpuimx35sd() (0) +#endif + +#ifdef CONFIG_MACH_EUKREA_CPUIMX51SD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX51SD +# endif +# define machine_is_eukrea_cpuimx51sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51SD) +#else +# define machine_is_eukrea_cpuimx51sd() (0) +#endif + +#ifdef CONFIG_MACH_EUKREA_CPUIMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX51 +# endif +# define machine_is_eukrea_cpuimx51() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51) +#else +# define machine_is_eukrea_cpuimx51() (0) +#endif + +#ifdef CONFIG_MACH_P565 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P565 +# endif +# define machine_is_p565() (machine_arch_type == MACH_TYPE_P565) +#else +# define machine_is_p565() (0) +#endif + +#ifdef CONFIG_MACH_ACER_A4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_A4 +# endif +# define machine_is_acer_a4() (machine_arch_type == MACH_TYPE_ACER_A4) +#else +# define machine_is_acer_a4() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM368_BIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM368_BIP +# endif +# define machine_is_davinci_dm368_bip() (machine_arch_type == MACH_TYPE_DAVINCI_DM368_BIP) +#else +# define machine_is_davinci_dm368_bip() (0) +#endif + +#ifdef CONFIG_MACH_ESHARE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESHARE +# endif +# define machine_is_eshare() (machine_arch_type == MACH_TYPE_ESHARE) +#else +# define machine_is_eshare() (0) +#endif + +#ifdef CONFIG_MACH_HW_OMAPL138_EUROPA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW_OMAPL138_EUROPA +# endif +# define machine_is_omapl138_europa() (machine_arch_type == MACH_TYPE_HW_OMAPL138_EUROPA) +#else +# define machine_is_omapl138_europa() (0) +#endif + +#ifdef CONFIG_MACH_WLBARGN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WLBARGN +# endif +# define machine_is_wlbargn() (machine_arch_type == MACH_TYPE_WLBARGN) +#else +# define machine_is_wlbargn() (0) +#endif + +#ifdef CONFIG_MACH_BM170 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BM170 +# endif +# define machine_is_bm170() (machine_arch_type == MACH_TYPE_BM170) +#else +# define machine_is_bm170() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_MINI_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_MINI_V2 +# endif +# define machine_is_netspace_mini_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MINI_V2) +#else +# define machine_is_netspace_mini_v2() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_PLUG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_PLUG_V2 +# endif +# define machine_is_netspace_plug_v2() (machine_arch_type == MACH_TYPE_NETSPACE_PLUG_V2) +#else +# define machine_is_netspace_plug_v2() (0) +#endif + +#ifdef CONFIG_MACH_SIEMENS_L1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIEMENS_L1 +# endif +# define machine_is_siemens_l1() (machine_arch_type == MACH_TYPE_SIEMENS_L1) +#else +# define machine_is_siemens_l1() (0) +#endif + +#ifdef CONFIG_MACH_ELV_LCU1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELV_LCU1 +# endif +# define machine_is_elv_lcu1() (machine_arch_type == MACH_TYPE_ELV_LCU1) +#else +# define machine_is_elv_lcu1() (0) +#endif + +#ifdef CONFIG_MACH_MCU1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCU1 +# endif +# define machine_is_mcu1() (machine_arch_type == MACH_TYPE_MCU1) +#else +# define machine_is_mcu1() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_TAO3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_TAO3530 +# endif +# define machine_is_omap3_tao3530() (machine_arch_type == MACH_TYPE_OMAP3_TAO3530) +#else +# define machine_is_omap3_tao3530() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_PCUTOUCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PCUTOUCH +# endif +# define machine_is_omap3_pcutouch() (machine_arch_type == MACH_TYPE_OMAP3_PCUTOUCH) +#else +# define machine_is_omap3_pcutouch() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC210 +# endif +# define machine_is_smdkc210() (machine_arch_type == MACH_TYPE_SMDKC210) +#else +# define machine_is_smdkc210() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_BRAILLO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_BRAILLO +# endif +# define machine_is_omap3_braillo() (machine_arch_type == MACH_TYPE_OMAP3_BRAILLO) +#else +# define machine_is_omap3_braillo() (0) +#endif + +#ifdef CONFIG_MACH_SPYPLUG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPYPLUG +# endif +# define machine_is_spyplug() (machine_arch_type == MACH_TYPE_SPYPLUG) +#else +# define machine_is_spyplug() (0) +#endif + +#ifdef CONFIG_MACH_GINGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GINGER +# endif +# define machine_is_ginger() (machine_arch_type == MACH_TYPE_GINGER) +#else +# define machine_is_ginger() (0) +#endif + +#ifdef CONFIG_MACH_TNY_T3530 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNY_T3530 +# endif +# define machine_is_tny_t3530() (machine_arch_type == MACH_TYPE_TNY_T3530) +#else +# define machine_is_tny_t3530() (0) +#endif + +#ifdef CONFIG_MACH_PCA102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCA102 +# endif +# define machine_is_pca102() (machine_arch_type == MACH_TYPE_PCA102) +#else +# define machine_is_pca102() (0) +#endif + +#ifdef CONFIG_MACH_SPADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPADE +# endif +# define machine_is_spade() (machine_arch_type == MACH_TYPE_SPADE) +#else +# define machine_is_spade() (0) +#endif + +#ifdef CONFIG_MACH_MXC25_TOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC25_TOPAZ +# endif +# define machine_is_mxc25_topaz() (machine_arch_type == MACH_TYPE_MXC25_TOPAZ) +#else +# define machine_is_mxc25_topaz() (0) +#endif + +#ifdef CONFIG_MACH_T5325 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T5325 +# endif +# define machine_is_t5325() (machine_arch_type == MACH_TYPE_T5325) +#else +# define machine_is_t5325() (0) +#endif + +#ifdef CONFIG_MACH_GW2361 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GW2361 +# endif +# define machine_is_gw2361() (machine_arch_type == MACH_TYPE_GW2361) +#else +# define machine_is_gw2361() (0) +#endif + +#ifdef CONFIG_MACH_ELOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELOG +# endif +# define machine_is_elog() (machine_arch_type == MACH_TYPE_ELOG) +#else +# define machine_is_elog() (0) +#endif + +#ifdef CONFIG_MACH_INCOME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCOME +# endif +# define machine_is_income() (machine_arch_type == MACH_TYPE_INCOME) +#else +# define machine_is_income() (0) +#endif + +#ifdef CONFIG_MACH_BCM589X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM589X +# endif +# define machine_is_bcm589x() (machine_arch_type == MACH_TYPE_BCM589X) +#else +# define machine_is_bcm589x() (0) +#endif + +#ifdef CONFIG_MACH_ETNA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETNA +# endif +# define machine_is_etna() (machine_arch_type == MACH_TYPE_ETNA) +#else +# define machine_is_etna() (0) +#endif + +#ifdef CONFIG_MACH_HAWKS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAWKS +# endif +# define machine_is_hawks() (machine_arch_type == MACH_TYPE_HAWKS) +#else +# define machine_is_hawks() (0) +#endif + +#ifdef CONFIG_MACH_MESON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESON +# endif +# define machine_is_meson() (machine_arch_type == MACH_TYPE_MESON) +#else +# define machine_is_meson() (0) +#endif + +#ifdef CONFIG_MACH_XSBASE255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSBASE255 +# endif +# define machine_is_xsbase255() (machine_arch_type == MACH_TYPE_XSBASE255) +#else +# define machine_is_xsbase255() (0) +#endif + +#ifdef CONFIG_MACH_PVM2030 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PVM2030 +# endif +# define machine_is_pvm2030() (machine_arch_type == MACH_TYPE_PVM2030) +#else +# define machine_is_pvm2030() (0) +#endif + +#ifdef CONFIG_MACH_MIOA502 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIOA502 +# endif +# define machine_is_mioa502() (machine_arch_type == MACH_TYPE_MIOA502) +#else +# define machine_is_mioa502() (0) +#endif + +#ifdef CONFIG_MACH_VVBOX_SDORIG2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVBOX_SDORIG2 +# endif +# define machine_is_vvbox_sdorig2() (machine_arch_type == MACH_TYPE_VVBOX_SDORIG2) +#else +# define machine_is_vvbox_sdorig2() (0) +#endif + +#ifdef CONFIG_MACH_VVBOX_SDLITE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVBOX_SDLITE2 +# endif +# define machine_is_vvbox_sdlite2() (machine_arch_type == MACH_TYPE_VVBOX_SDLITE2) +#else +# define machine_is_vvbox_sdlite2() (0) +#endif + +#ifdef CONFIG_MACH_VVBOX_SDPRO4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VVBOX_SDPRO4 +# endif +# define machine_is_vvbox_sdpro4() (machine_arch_type == MACH_TYPE_VVBOX_SDPRO4) +#else +# define machine_is_vvbox_sdpro4() (0) +#endif + +#ifdef CONFIG_MACH_HTC_SPV_M700 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_SPV_M700 +# endif +# define machine_is_htc_spv_m700() (machine_arch_type == MACH_TYPE_HTC_SPV_M700) +#else +# define machine_is_htc_spv_m700() (0) +#endif + +#ifdef CONFIG_MACH_MX257SX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX257SX +# endif +# define machine_is_mx257sx() (machine_arch_type == MACH_TYPE_MX257SX) +#else +# define machine_is_mx257sx() (0) +#endif + +#ifdef CONFIG_MACH_GONI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GONI +# endif +# define machine_is_goni() (machine_arch_type == MACH_TYPE_GONI) +#else +# define machine_is_goni() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_SVLTE_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_FFA +# endif +# define machine_is_msm8x55_svlte_ffa() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_FFA) +#else +# define machine_is_msm8x55_svlte_ffa() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X55_SVLTE_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X55_SVLTE_SURF +# endif +# define machine_is_msm8x55_svlte_surf() (machine_arch_type == MACH_TYPE_MSM8X55_SVLTE_SURF) +#else +# define machine_is_msm8x55_svlte_surf() (0) +#endif + +#ifdef CONFIG_MACH_QUICKSTEP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUICKSTEP +# endif +# define machine_is_quickstep() (machine_arch_type == MACH_TYPE_QUICKSTEP) +#else +# define machine_is_quickstep() (0) +#endif + +#ifdef CONFIG_MACH_DMW96 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DMW96 +# endif +# define machine_is_dmw96() (machine_arch_type == MACH_TYPE_DMW96) +#else +# define machine_is_dmw96() (0) +#endif + +#ifdef CONFIG_MACH_HAMMERHEAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAMMERHEAD +# endif +# define machine_is_hammerhead() (machine_arch_type == MACH_TYPE_HAMMERHEAD) +#else +# define machine_is_hammerhead() (0) +#endif + +#ifdef CONFIG_MACH_TRIDENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIDENT +# endif +# define machine_is_trident() (machine_arch_type == MACH_TYPE_TRIDENT) +#else +# define machine_is_trident() (0) +#endif + +#ifdef CONFIG_MACH_LIGHTNING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIGHTNING +# endif +# define machine_is_lightning() (machine_arch_type == MACH_TYPE_LIGHTNING) +#else +# define machine_is_lightning() (0) +#endif + +#ifdef CONFIG_MACH_ICONNECT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICONNECT +# endif +# define machine_is_iconnect() (machine_arch_type == MACH_TYPE_ICONNECT) +#else +# define machine_is_iconnect() (0) +#endif + +#ifdef CONFIG_MACH_AUTOBOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AUTOBOT +# endif +# define machine_is_autobot() (machine_arch_type == MACH_TYPE_AUTOBOT) +#else +# define machine_is_autobot() (0) +#endif + +#ifdef CONFIG_MACH_COCONUT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COCONUT +# endif +# define machine_is_coconut() (machine_arch_type == MACH_TYPE_COCONUT) +#else +# define machine_is_coconut() (0) +#endif + +#ifdef CONFIG_MACH_DURIAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DURIAN +# endif +# define machine_is_durian() (machine_arch_type == MACH_TYPE_DURIAN) +#else +# define machine_is_durian() (0) +#endif + +#ifdef CONFIG_MACH_CAYENNE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAYENNE +# endif +# define machine_is_cayenne() (machine_arch_type == MACH_TYPE_CAYENNE) +#else +# define machine_is_cayenne() (0) +#endif + +#ifdef CONFIG_MACH_FUJI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJI +# endif +# define machine_is_fuji() (machine_arch_type == MACH_TYPE_FUJI) +#else +# define machine_is_fuji() (0) +#endif + +#ifdef CONFIG_MACH_SYNOLOGY_6282 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYNOLOGY_6282 +# endif +# define machine_is_synology_6282() (machine_arch_type == MACH_TYPE_SYNOLOGY_6282) +#else +# define machine_is_synology_6282() (0) +#endif + +#ifdef CONFIG_MACH_EM1SY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EM1SY +# endif +# define machine_is_em1sy() (machine_arch_type == MACH_TYPE_EM1SY) +#else +# define machine_is_em1sy() (0) +#endif + +#ifdef CONFIG_MACH_M502 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M502 +# endif +# define machine_is_m502() (machine_arch_type == MACH_TYPE_M502) +#else +# define machine_is_m502() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX518 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX518 +# endif +# define machine_is_matrix518() (machine_arch_type == MACH_TYPE_MATRIX518) +#else +# define machine_is_matrix518() (0) +#endif + +#ifdef CONFIG_MACH_TINY_GURNARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TINY_GURNARD +# endif +# define machine_is_tiny_gurnard() (machine_arch_type == MACH_TYPE_TINY_GURNARD) +#else +# define machine_is_tiny_gurnard() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR1310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR1310 +# endif +# define machine_is_spear1310() (machine_arch_type == MACH_TYPE_SPEAR1310) +#else +# define machine_is_spear1310() (0) +#endif + +#ifdef CONFIG_MACH_BV07 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BV07 +# endif +# define machine_is_bv07() (machine_arch_type == MACH_TYPE_BV07) +#else +# define machine_is_bv07() (0) +#endif + +#ifdef CONFIG_MACH_MXT_TD61 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXT_TD61 +# endif +# define machine_is_mxt_td61() (machine_arch_type == MACH_TYPE_MXT_TD61) +#else +# define machine_is_mxt_td61() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_ULTIMATE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_ULTIMATE +# endif +# define machine_is_openrd_ultimate() (machine_arch_type == MACH_TYPE_OPENRD_ULTIMATE) +#else +# define machine_is_openrd_ultimate() (0) +#endif + +#ifdef CONFIG_MACH_DEVIXP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVIXP +# endif +# define machine_is_devixp() (machine_arch_type == MACH_TYPE_DEVIXP) +#else +# define machine_is_devixp() (0) +#endif + +#ifdef CONFIG_MACH_MICCPT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICCPT +# endif +# define machine_is_miccpt() (machine_arch_type == MACH_TYPE_MICCPT) +#else +# define machine_is_miccpt() (0) +#endif + +#ifdef CONFIG_MACH_MIC256 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIC256 +# endif +# define machine_is_mic256() (machine_arch_type == MACH_TYPE_MIC256) +#else +# define machine_is_mic256() (0) +#endif + +#ifdef CONFIG_MACH_AS1167 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AS1167 +# endif +# define machine_is_as1167() (machine_arch_type == MACH_TYPE_AS1167) +#else +# define machine_is_as1167() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_IBIZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_IBIZA +# endif +# define machine_is_omap3_ibiza() (machine_arch_type == MACH_TYPE_OMAP3_IBIZA) +#else +# define machine_is_omap3_ibiza() (0) +#endif + +#ifdef CONFIG_MACH_U5500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U5500 +# endif +# define machine_is_u5500() (machine_arch_type == MACH_TYPE_U5500) +#else +# define machine_is_u5500() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_PICTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_PICTO +# endif +# define machine_is_davinci_picto() (machine_arch_type == MACH_TYPE_DAVINCI_PICTO) +#else +# define machine_is_davinci_picto() (0) +#endif + +#ifdef CONFIG_MACH_MECHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MECHA +# endif +# define machine_is_mecha() (machine_arch_type == MACH_TYPE_MECHA) +#else +# define machine_is_mecha() (0) +#endif + +#ifdef CONFIG_MACH_BUBBA3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUBBA3 +# endif +# define machine_is_bubba3() (machine_arch_type == MACH_TYPE_BUBBA3) +#else +# define machine_is_bubba3() (0) +#endif + +#ifdef CONFIG_MACH_PUPITRE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PUPITRE +# endif +# define machine_is_pupitre() (machine_arch_type == MACH_TYPE_PUPITRE) +#else +# define machine_is_pupitre() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_HARMONY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_HARMONY +# endif +# define machine_is_tegra_harmony() (machine_arch_type == MACH_TYPE_TEGRA_HARMONY) +#else +# define machine_is_tegra_harmony() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_VOGUE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_VOGUE +# endif +# define machine_is_tegra_vogue() (machine_arch_type == MACH_TYPE_TEGRA_VOGUE) +#else +# define machine_is_tegra_vogue() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_E1165 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_E1165 +# endif +# define machine_is_tegra_e1165() (machine_arch_type == MACH_TYPE_TEGRA_E1165) +#else +# define machine_is_tegra_e1165() (0) +#endif + +#ifdef CONFIG_MACH_SIMPLENET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMPLENET +# endif +# define machine_is_simplenet() (machine_arch_type == MACH_TYPE_SIMPLENET) +#else +# define machine_is_simplenet() (0) +#endif + +#ifdef CONFIG_MACH_EC4350TBM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EC4350TBM +# endif +# define machine_is_ec4350tbm() (machine_arch_type == MACH_TYPE_EC4350TBM) +#else +# define machine_is_ec4350tbm() (0) +#endif + +#ifdef CONFIG_MACH_PEC_TC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEC_TC +# endif +# define machine_is_pec_tc() (machine_arch_type == MACH_TYPE_PEC_TC) +#else +# define machine_is_pec_tc() (0) +#endif + +#ifdef CONFIG_MACH_PEC_HC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEC_HC2 +# endif +# define machine_is_pec_hc2() (machine_arch_type == MACH_TYPE_PEC_HC2) +#else +# define machine_is_pec_hc2() (0) +#endif + +#ifdef CONFIG_MACH_ESL_MOBILIS_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_MOBILIS_A +# endif +# define machine_is_esl_mobilis_a() (machine_arch_type == MACH_TYPE_ESL_MOBILIS_A) +#else +# define machine_is_esl_mobilis_a() (0) +#endif + +#ifdef CONFIG_MACH_ESL_MOBILIS_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_MOBILIS_B +# endif +# define machine_is_esl_mobilis_b() (machine_arch_type == MACH_TYPE_ESL_MOBILIS_B) +#else +# define machine_is_esl_mobilis_b() (0) +#endif + +#ifdef CONFIG_MACH_ESL_WAVE_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_WAVE_A +# endif +# define machine_is_esl_wave_a() (machine_arch_type == MACH_TYPE_ESL_WAVE_A) +#else +# define machine_is_esl_wave_a() (0) +#endif + +#ifdef CONFIG_MACH_ESL_WAVE_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESL_WAVE_B +# endif +# define machine_is_esl_wave_b() (machine_arch_type == MACH_TYPE_ESL_WAVE_B) +#else +# define machine_is_esl_wave_b() (0) +#endif + +#ifdef CONFIG_MACH_UNISENSE_MMM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNISENSE_MMM +# endif +# define machine_is_unisense_mmm() (machine_arch_type == MACH_TYPE_UNISENSE_MMM) +#else +# define machine_is_unisense_mmm() (0) +#endif + +#ifdef CONFIG_MACH_BLUESHARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUESHARK +# endif +# define machine_is_blueshark() (machine_arch_type == MACH_TYPE_BLUESHARK) +#else +# define machine_is_blueshark() (0) +#endif + +#ifdef CONFIG_MACH_E10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E10 +# endif +# define machine_is_e10() (machine_arch_type == MACH_TYPE_E10) +#else +# define machine_is_e10() (0) +#endif + +#ifdef CONFIG_MACH_APP3K_ROBIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APP3K_ROBIN +# endif +# define machine_is_app3k_robin() (machine_arch_type == MACH_TYPE_APP3K_ROBIN) +#else +# define machine_is_app3k_robin() (0) +#endif + +#ifdef CONFIG_MACH_POV15HD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POV15HD +# endif +# define machine_is_pov15hd() (machine_arch_type == MACH_TYPE_POV15HD) +#else +# define machine_is_pov15hd() (0) +#endif + +#ifdef CONFIG_MACH_STELLA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STELLA +# endif +# define machine_is_stella() (machine_arch_type == MACH_TYPE_STELLA) +#else +# define machine_is_stella() (0) +#endif + +#ifdef CONFIG_MACH_MACH_HTC_IOLITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MACH_HTC_IOLITE +# endif +# define machine_is_htc_iolite() (machine_arch_type == MACH_TYPE_MACH_HTC_IOLITE) +#else +# define machine_is_htc_iolite() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_LSCHL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_LSCHL +# endif +# define machine_is_linkstation_lschl() (machine_arch_type == MACH_TYPE_LINKSTATION_LSCHL) +#else +# define machine_is_linkstation_lschl() (0) +#endif + +#ifdef CONFIG_MACH_NETWALKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETWALKER +# endif +# define machine_is_netwalker() (machine_arch_type == MACH_TYPE_NETWALKER) +#else +# define machine_is_netwalker() (0) +#endif + +#ifdef CONFIG_MACH_ACSX106 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACSX106 +# endif +# define machine_is_acsx106() (machine_arch_type == MACH_TYPE_ACSX106) +#else +# define machine_is_acsx106() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS5_C1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS5_C1 +# endif +# define machine_is_atlas5_c1() (machine_arch_type == MACH_TYPE_ATLAS5_C1) +#else +# define machine_is_atlas5_c1() (0) +#endif + +#ifdef CONFIG_MACH_NSB3AST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NSB3AST +# endif +# define machine_is_nsb3ast() (machine_arch_type == MACH_TYPE_NSB3AST) +#else +# define machine_is_nsb3ast() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SLC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SLC +# endif +# define machine_is_gnet_slc() (machine_arch_type == MACH_TYPE_GNET_SLC) +#else +# define machine_is_gnet_slc() (0) +#endif + +#ifdef CONFIG_MACH_AF4000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AF4000 +# endif +# define machine_is_af4000() (machine_arch_type == MACH_TYPE_AF4000) +#else +# define machine_is_af4000() (0) +#endif + +#ifdef CONFIG_MACH_ARK9431 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARK9431 +# endif +# define machine_is_ark9431() (machine_arch_type == MACH_TYPE_ARK9431) +#else +# define machine_is_ark9431() (0) +#endif + +#ifdef CONFIG_MACH_FS_S5PC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FS_S5PC100 +# endif +# define machine_is_fs_s5pc100() (machine_arch_type == MACH_TYPE_FS_S5PC100) +#else +# define machine_is_fs_s5pc100() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3505NOVA8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3505NOVA8 +# endif +# define machine_is_omap3505nova8() (machine_arch_type == MACH_TYPE_OMAP3505NOVA8) +#else +# define machine_is_omap3505nova8() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3621_EDP1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3621_EDP1 +# endif +# define machine_is_omap3621_edp1() (machine_arch_type == MACH_TYPE_OMAP3621_EDP1) +#else +# define machine_is_omap3621_edp1() (0) +#endif + +#ifdef CONFIG_MACH_ORATISAES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISAES +# endif +# define machine_is_oratisaes() (machine_arch_type == MACH_TYPE_ORATISAES) +#else +# define machine_is_oratisaes() (0) +#endif + +#ifdef CONFIG_MACH_SMDKV310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKV310 +# endif +# define machine_is_smdkv310() (machine_arch_type == MACH_TYPE_SMDKV310) +#else +# define machine_is_smdkv310() (0) +#endif + +#ifdef CONFIG_MACH_SIEMENS_L0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIEMENS_L0 +# endif +# define machine_is_siemens_l0() (machine_arch_type == MACH_TYPE_SIEMENS_L0) +#else +# define machine_is_siemens_l0() (0) +#endif + +#ifdef CONFIG_MACH_VENTANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VENTANA +# endif +# define machine_is_ventana() (machine_arch_type == MACH_TYPE_VENTANA) +#else +# define machine_is_ventana() (0) +#endif + +#ifdef CONFIG_MACH_WM8505_7IN_NETBOOK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WM8505_7IN_NETBOOK +# endif +# define machine_is_wm8505_7in_netbook() (machine_arch_type == MACH_TYPE_WM8505_7IN_NETBOOK) +#else +# define machine_is_wm8505_7in_netbook() (0) +#endif + +#ifdef CONFIG_MACH_EC4350SDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EC4350SDB +# endif +# define machine_is_ec4350sdb() (machine_arch_type == MACH_TYPE_EC4350SDB) +#else +# define machine_is_ec4350sdb() (0) +#endif + +#ifdef CONFIG_MACH_MIMAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIMAS +# endif +# define machine_is_mimas() (machine_arch_type == MACH_TYPE_MIMAS) +#else +# define machine_is_mimas() (0) +#endif + +#ifdef CONFIG_MACH_TITAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TITAN +# endif +# define machine_is_titan() (machine_arch_type == MACH_TYPE_TITAN) +#else +# define machine_is_titan() (0) +#endif + +#ifdef CONFIG_MACH_CRANEBOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CRANEBOARD +# endif +# define machine_is_craneboard() (machine_arch_type == MACH_TYPE_CRANEBOARD) +#else +# define machine_is_craneboard() (0) +#endif + +#ifdef CONFIG_MACH_ES2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ES2440 +# endif +# define machine_is_es2440() (machine_arch_type == MACH_TYPE_ES2440) +#else +# define machine_is_es2440() (0) +#endif + +#ifdef CONFIG_MACH_NAJAY_A9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAJAY_A9263 +# endif +# define machine_is_najay_a9263() (machine_arch_type == MACH_TYPE_NAJAY_A9263) +#else +# define machine_is_najay_a9263() (0) +#endif + +#ifdef CONFIG_MACH_HTCTORNADO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCTORNADO +# endif +# define machine_is_htctornado() (machine_arch_type == MACH_TYPE_HTCTORNADO) +#else +# define machine_is_htctornado() (0) +#endif + +#ifdef CONFIG_MACH_DIMM_MX257 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DIMM_MX257 +# endif +# define machine_is_dimm_mx257() (machine_arch_type == MACH_TYPE_DIMM_MX257) +#else +# define machine_is_dimm_mx257() (0) +#endif + +#ifdef CONFIG_MACH_JIGEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JIGEN +# endif +# define machine_is_jigen301() (machine_arch_type == MACH_TYPE_JIGEN) +#else +# define machine_is_jigen301() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6450 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6450 +# endif +# define machine_is_smdk6450() (machine_arch_type == MACH_TYPE_SMDK6450) +#else +# define machine_is_smdk6450() (0) +#endif + +#ifdef CONFIG_MACH_MENO_QNG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MENO_QNG +# endif +# define machine_is_meno_qng() (machine_arch_type == MACH_TYPE_MENO_QNG) +#else +# define machine_is_meno_qng() (0) +#endif + +#ifdef CONFIG_MACH_NS2416 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NS2416 +# endif +# define machine_is_ns2416() (machine_arch_type == MACH_TYPE_NS2416) +#else +# define machine_is_ns2416() (0) +#endif + +#ifdef CONFIG_MACH_RPC353 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RPC353 +# endif +# define machine_is_rpc353() (machine_arch_type == MACH_TYPE_RPC353) +#else +# define machine_is_rpc353() (0) +#endif + +#ifdef CONFIG_MACH_TQ6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TQ6410 +# endif +# define machine_is_tq6410() (machine_arch_type == MACH_TYPE_TQ6410) +#else +# define machine_is_tq6410() (0) +#endif + +#ifdef CONFIG_MACH_SKY6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SKY6410 +# endif +# define machine_is_sky6410() (machine_arch_type == MACH_TYPE_SKY6410) +#else +# define machine_is_sky6410() (0) +#endif + +#ifdef CONFIG_MACH_DYNASTY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DYNASTY +# endif +# define machine_is_dynasty() (machine_arch_type == MACH_TYPE_DYNASTY) +#else +# define machine_is_dynasty() (0) +#endif + +#ifdef CONFIG_MACH_VIVO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VIVO +# endif +# define machine_is_vivo() (machine_arch_type == MACH_TYPE_VIVO) +#else +# define machine_is_vivo() (0) +#endif + +#ifdef CONFIG_MACH_BURY_BL7582 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BURY_BL7582 +# endif +# define machine_is_bury_bl7582() (machine_arch_type == MACH_TYPE_BURY_BL7582) +#else +# define machine_is_bury_bl7582() (0) +#endif + +#ifdef CONFIG_MACH_BURY_BPS5270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BURY_BPS5270 +# endif +# define machine_is_bury_bps5270() (machine_arch_type == MACH_TYPE_BURY_BPS5270) +#else +# define machine_is_bury_bps5270() (0) +#endif + +#ifdef CONFIG_MACH_BASI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BASI +# endif +# define machine_is_basi() (machine_arch_type == MACH_TYPE_BASI) +#else +# define machine_is_basi() (0) +#endif + +#ifdef CONFIG_MACH_TN200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TN200 +# endif +# define machine_is_tn200() (machine_arch_type == MACH_TYPE_TN200) +#else +# define machine_is_tn200() (0) +#endif + +#ifdef CONFIG_MACH_C2MMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C2MMI +# endif +# define machine_is_c2mmi() (machine_arch_type == MACH_TYPE_C2MMI) +#else +# define machine_is_c2mmi() (0) +#endif + +#ifdef CONFIG_MACH_MESON_6236M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESON_6236M +# endif +# define machine_is_meson_6236m() (machine_arch_type == MACH_TYPE_MESON_6236M) +#else +# define machine_is_meson_6236m() (0) +#endif + +#ifdef CONFIG_MACH_MESON_8626M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESON_8626M +# endif +# define machine_is_meson_8626m() (machine_arch_type == MACH_TYPE_MESON_8626M) +#else +# define machine_is_meson_8626m() (0) +#endif + +#ifdef CONFIG_MACH_TUBE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TUBE +# endif +# define machine_is_tube() (machine_arch_type == MACH_TYPE_TUBE) +#else +# define machine_is_tube() (0) +#endif + +#ifdef CONFIG_MACH_MESSINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MESSINA +# endif +# define machine_is_messina() (machine_arch_type == MACH_TYPE_MESSINA) +#else +# define machine_is_messina() (0) +#endif + +#ifdef CONFIG_MACH_MX50_ARM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX50_ARM2 +# endif +# define machine_is_mx50_arm2() (machine_arch_type == MACH_TYPE_MX50_ARM2) +#else +# define machine_is_mx50_arm2() (0) +#endif + +#ifdef CONFIG_MACH_CETUS9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CETUS9263 +# endif +# define machine_is_cetus9263() (machine_arch_type == MACH_TYPE_CETUS9263) +#else +# define machine_is_cetus9263() (0) +#endif + +#ifdef CONFIG_MACH_BROWNSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BROWNSTONE +# endif +# define machine_is_brownstone() (machine_arch_type == MACH_TYPE_BROWNSTONE) +#else +# define machine_is_brownstone() (0) +#endif + +#ifdef CONFIG_MACH_VMX25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMX25 +# endif +# define machine_is_vmx25() (machine_arch_type == MACH_TYPE_VMX25) +#else +# define machine_is_vmx25() (0) +#endif + +#ifdef CONFIG_MACH_VMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMX51 +# endif +# define machine_is_vmx51() (machine_arch_type == MACH_TYPE_VMX51) +#else +# define machine_is_vmx51() (0) +#endif + +#ifdef CONFIG_MACH_ABACUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ABACUS +# endif +# define machine_is_abacus() (machine_arch_type == MACH_TYPE_ABACUS) +#else +# define machine_is_abacus() (0) +#endif + +#ifdef CONFIG_MACH_CM4745 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM4745 +# endif +# define machine_is_cm4745() (machine_arch_type == MACH_TYPE_CM4745) +#else +# define machine_is_cm4745() (0) +#endif + +#ifdef CONFIG_MACH_ORATISLINK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISLINK +# endif +# define machine_is_oratislink() (machine_arch_type == MACH_TYPE_ORATISLINK) +#else +# define machine_is_oratislink() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM365_DVR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM365_DVR +# endif +# define machine_is_davinci_dm365_dvr() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_DVR) +#else +# define machine_is_davinci_dm365_dvr() (0) +#endif + +#ifdef CONFIG_MACH_NETVIZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETVIZ +# endif +# define machine_is_netviz() (machine_arch_type == MACH_TYPE_NETVIZ) +#else +# define machine_is_netviz() (0) +#endif + +#ifdef CONFIG_MACH_FLEXIBITY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLEXIBITY +# endif +# define machine_is_flexibity() (machine_arch_type == MACH_TYPE_FLEXIBITY) +#else +# define machine_is_flexibity() (0) +#endif + +#ifdef CONFIG_MACH_WLAN_COMPUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WLAN_COMPUTER +# endif +# define machine_is_wlan_computer() (machine_arch_type == MACH_TYPE_WLAN_COMPUTER) +#else +# define machine_is_wlan_computer() (0) +#endif + +#ifdef CONFIG_MACH_LPC24XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC24XX +# endif +# define machine_is_lpc24xx() (machine_arch_type == MACH_TYPE_LPC24XX) +#else +# define machine_is_lpc24xx() (0) +#endif + +#ifdef CONFIG_MACH_SPICA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPICA +# endif +# define machine_is_spica() (machine_arch_type == MACH_TYPE_SPICA) +#else +# define machine_is_spica() (0) +#endif + +#ifdef CONFIG_MACH_GPSDISPLAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GPSDISPLAY +# endif +# define machine_is_gpsdisplay() (machine_arch_type == MACH_TYPE_GPSDISPLAY) +#else +# define machine_is_gpsdisplay() (0) +#endif + +#ifdef CONFIG_MACH_BIPNET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIPNET +# endif +# define machine_is_bipnet() (machine_arch_type == MACH_TYPE_BIPNET) +#else +# define machine_is_bipnet() (0) +#endif + +#ifdef CONFIG_MACH_OVERO_CTU_INERTIAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OVERO_CTU_INERTIAL +# endif +# define machine_is_overo_ctu_inertial() (machine_arch_type == MACH_TYPE_OVERO_CTU_INERTIAL) +#else +# define machine_is_overo_ctu_inertial() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM355_MMM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM355_MMM +# endif +# define machine_is_davinci_dm355_mmm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_MMM) +#else +# define machine_is_davinci_dm355_mmm() (0) +#endif + +#ifdef CONFIG_MACH_PC9260_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC9260_V2 +# endif +# define machine_is_pc9260_v2() (machine_arch_type == MACH_TYPE_PC9260_V2) +#else +# define machine_is_pc9260_v2() (0) +#endif + +#ifdef CONFIG_MACH_PTX7545 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PTX7545 +# endif +# define machine_is_ptx7545() (machine_arch_type == MACH_TYPE_PTX7545) +#else +# define machine_is_ptx7545() (0) +#endif + +#ifdef CONFIG_MACH_TM_EFDC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TM_EFDC +# endif +# define machine_is_tm_efdc() (machine_arch_type == MACH_TYPE_TM_EFDC) +#else +# define machine_is_tm_efdc() (0) +#endif + +#ifdef CONFIG_MACH_WALDO1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WALDO1 +# endif +# define machine_is_remove_me() (machine_arch_type == MACH_TYPE_WALDO1) +#else +# define machine_is_remove_me() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_WALDO1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_WALDO1 +# endif +# define machine_is_omap3_waldo1() (machine_arch_type == MACH_TYPE_OMAP3_WALDO1) +#else +# define machine_is_omap3_waldo1() (0) +#endif + +#ifdef CONFIG_MACH_FLYER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLYER +# endif +# define machine_is_flyer() (machine_arch_type == MACH_TYPE_FLYER) +#else +# define machine_is_flyer() (0) +#endif + +#ifdef CONFIG_MACH_TORNADO3240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TORNADO3240 +# endif +# define machine_is_tornado3240() (machine_arch_type == MACH_TYPE_TORNADO3240) +#else +# define machine_is_tornado3240() (0) +#endif + +#ifdef CONFIG_MACH_SOLI_01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOLI_01 +# endif +# define machine_is_soli_01() (machine_arch_type == MACH_TYPE_SOLI_01) +#else +# define machine_is_soli_01() (0) +#endif + +#ifdef CONFIG_MACH_OMAPL138_EUROPALC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAPL138_EUROPALC +# endif +# define machine_is_omapl138_europalc() (machine_arch_type == MACH_TYPE_OMAPL138_EUROPALC) +#else +# define machine_is_omapl138_europalc() (0) +#endif + +#ifdef CONFIG_MACH_HELIOS_V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HELIOS_V1 +# endif +# define machine_is_helios_v1() (machine_arch_type == MACH_TYPE_HELIOS_V1) +#else +# define machine_is_helios_v1() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_LITE_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_LITE_V2 +# endif +# define machine_is_netspace_lite_v2() (machine_arch_type == MACH_TYPE_NETSPACE_LITE_V2) +#else +# define machine_is_netspace_lite_v2() (0) +#endif + +#ifdef CONFIG_MACH_SSC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SSC +# endif +# define machine_is_ssc() (machine_arch_type == MACH_TYPE_SSC) +#else +# define machine_is_ssc() (0) +#endif + +#ifdef CONFIG_MACH_PREMIERWAVE_EN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PREMIERWAVE_EN +# endif +# define machine_is_premierwave_en() (machine_arch_type == MACH_TYPE_PREMIERWAVE_EN) +#else +# define machine_is_premierwave_en() (0) +#endif + +#ifdef CONFIG_MACH_WASABI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WASABI +# endif +# define machine_is_wasabi() (machine_arch_type == MACH_TYPE_WASABI) +#else +# define machine_is_wasabi() (0) +#endif + +#ifdef CONFIG_MACH_VIVOW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VIVOW +# endif +# define machine_is_vivo_w() (machine_arch_type == MACH_TYPE_VIVOW) +#else +# define machine_is_vivo_w() (0) +#endif + +#ifdef CONFIG_MACH_MX50_RDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX50_RDP +# endif +# define machine_is_mx50_rdp() (machine_arch_type == MACH_TYPE_MX50_RDP) +#else +# define machine_is_mx50_rdp() (0) +#endif + +#ifdef CONFIG_MACH_UNIVERSAL_C210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNIVERSAL_C210 +# endif +# define machine_is_universal_c210() (machine_arch_type == MACH_TYPE_UNIVERSAL_C210) +#else +# define machine_is_universal_c210() (0) +#endif + +#ifdef CONFIG_MACH_REAL6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REAL6410 +# endif +# define machine_is_real6410() (machine_arch_type == MACH_TYPE_REAL6410) +#else +# define machine_is_real6410() (0) +#endif + +#ifdef CONFIG_MACH_SPX_SAKURA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPX_SAKURA +# endif +# define machine_is_spx_sakura() (machine_arch_type == MACH_TYPE_SPX_SAKURA) +#else +# define machine_is_spx_sakura() (0) +#endif + +#ifdef CONFIG_MACH_IJ3K_2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IJ3K_2440 +# endif +# define machine_is_ij3k_2440() (machine_arch_type == MACH_TYPE_IJ3K_2440) +#else +# define machine_is_ij3k_2440() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_BC10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_BC10 +# endif +# define machine_is_omap3_bc10() (machine_arch_type == MACH_TYPE_OMAP3_BC10) +#else +# define machine_is_omap3_bc10() (0) +#endif + +#ifdef CONFIG_MACH_THEBE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_THEBE +# endif +# define machine_is_thebe() (machine_arch_type == MACH_TYPE_THEBE) +#else +# define machine_is_thebe() (0) +#endif + +#ifdef CONFIG_MACH_RV082 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RV082 +# endif +# define machine_is_rv082() (machine_arch_type == MACH_TYPE_RV082) +#else +# define machine_is_rv082() (0) +#endif + +#ifdef CONFIG_MACH_ARMLGUEST +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMLGUEST +# endif +# define machine_is_armlguest() (machine_arch_type == MACH_TYPE_ARMLGUEST) +#else +# define machine_is_armlguest() (0) +#endif + +#ifdef CONFIG_MACH_TJINC1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TJINC1000 +# endif +# define machine_is_tjinc1000() (machine_arch_type == MACH_TYPE_TJINC1000) +#else +# define machine_is_tjinc1000() (0) +#endif + +#ifdef CONFIG_MACH_DOCKSTAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOCKSTAR +# endif +# define machine_is_dockstar() (machine_arch_type == MACH_TYPE_DOCKSTAR) +#else +# define machine_is_dockstar() (0) +#endif + +#ifdef CONFIG_MACH_AX8008 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AX8008 +# endif +# define machine_is_ax8008() (machine_arch_type == MACH_TYPE_AX8008) +#else +# define machine_is_ax8008() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGCE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGCE +# endif +# define machine_is_gnet_sgce() (machine_arch_type == MACH_TYPE_GNET_SGCE) +#else +# define machine_is_gnet_sgce() (0) +#endif + +#ifdef CONFIG_MACH_PXWNAS_500_1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXWNAS_500_1000 +# endif +# define machine_is_pxwnas_500_1000() (machine_arch_type == MACH_TYPE_PXWNAS_500_1000) +#else +# define machine_is_pxwnas_500_1000() (0) +#endif + +#ifdef CONFIG_MACH_EA20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EA20 +# endif +# define machine_is_ea20() (machine_arch_type == MACH_TYPE_EA20) +#else +# define machine_is_ea20() (0) +#endif + +#ifdef CONFIG_MACH_AWM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AWM2 +# endif +# define machine_is_awm2() (machine_arch_type == MACH_TYPE_AWM2) +#else +# define machine_is_awm2() (0) +#endif + +#ifdef CONFIG_MACH_TI8148EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TI8148EVM +# endif +# define machine_is_ti8148evm() (machine_arch_type == MACH_TYPE_TI8148EVM) +#else +# define machine_is_ti8148evm() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_SEABOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_SEABOARD +# endif +# define machine_is_tegra_seaboard() (machine_arch_type == MACH_TYPE_TEGRA_SEABOARD) +#else +# define machine_is_tegra_seaboard() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_CHLV2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_CHLV2 +# endif +# define machine_is_linkstation_chlv2() (machine_arch_type == MACH_TYPE_LINKSTATION_CHLV2) +#else +# define machine_is_linkstation_chlv2() (0) +#endif + +#ifdef CONFIG_MACH_TERA_PRO2_RACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TERA_PRO2_RACK +# endif +# define machine_is_tera_pro2_rack() (machine_arch_type == MACH_TYPE_TERA_PRO2_RACK) +#else +# define machine_is_tera_pro2_rack() (0) +#endif + +#ifdef CONFIG_MACH_RUBYS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RUBYS +# endif +# define machine_is_rubys() (machine_arch_type == MACH_TYPE_RUBYS) +#else +# define machine_is_rubys() (0) +#endif + +#ifdef CONFIG_MACH_AQUARIUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AQUARIUS +# endif +# define machine_is_aquarius() (machine_arch_type == MACH_TYPE_AQUARIUS) +#else +# define machine_is_aquarius() (0) +#endif + +#ifdef CONFIG_MACH_MX53_ARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX53_ARD +# endif +# define machine_is_mx53_ard() (machine_arch_type == MACH_TYPE_MX53_ARD) +#else +# define machine_is_mx53_ard() (0) +#endif + +#ifdef CONFIG_MACH_MX53_SMD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX53_SMD +# endif +# define machine_is_mx53_smd() (machine_arch_type == MACH_TYPE_MX53_SMD) +#else +# define machine_is_mx53_smd() (0) +#endif + +#ifdef CONFIG_MACH_LSWXL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LSWXL +# endif +# define machine_is_lswxl() (machine_arch_type == MACH_TYPE_LSWXL) +#else +# define machine_is_lswxl() (0) +#endif + +#ifdef CONFIG_MACH_DOVE_AVNG_V3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOVE_AVNG_V3 +# endif +# define machine_is_dove_avng_v3() (machine_arch_type == MACH_TYPE_DOVE_AVNG_V3) +#else +# define machine_is_dove_avng_v3() (0) +#endif + +#ifdef CONFIG_MACH_SDI_ESS_9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SDI_ESS_9263 +# endif +# define machine_is_sdi_ess_9263() (machine_arch_type == MACH_TYPE_SDI_ESS_9263) +#else +# define machine_is_sdi_ess_9263() (0) +#endif + +#ifdef CONFIG_MACH_JOCPU550 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JOCPU550 +# endif +# define machine_is_jocpu550() (machine_arch_type == MACH_TYPE_JOCPU550) +#else +# define machine_is_jocpu550() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_RUMI3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_RUMI3 +# endif +# define machine_is_msm8x60_rumi3() (machine_arch_type == MACH_TYPE_MSM8X60_RUMI3) +#else +# define machine_is_msm8x60_rumi3() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_FFA +# endif +# define machine_is_msm8x60_ffa() (machine_arch_type == MACH_TYPE_MSM8X60_FFA) +#else +# define machine_is_msm8x60_ffa() (0) +#endif + +#ifdef CONFIG_MACH_YANOMAMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YANOMAMI +# endif +# define machine_is_yanomami() (machine_arch_type == MACH_TYPE_YANOMAMI) +#else +# define machine_is_yanomami() (0) +#endif + +#ifdef CONFIG_MACH_GTA04 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTA04 +# endif +# define machine_is_gta04() (machine_arch_type == MACH_TYPE_GTA04) +#else +# define machine_is_gta04() (0) +#endif + +#ifdef CONFIG_MACH_CM_A510 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_A510 +# endif +# define machine_is_cm_a510() (machine_arch_type == MACH_TYPE_CM_A510) +#else +# define machine_is_cm_a510() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_RFS200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_RFS200 +# endif +# define machine_is_omap3_rfs200() (machine_arch_type == MACH_TYPE_OMAP3_RFS200) +#else +# define machine_is_omap3_rfs200() (0) +#endif + +#ifdef CONFIG_MACH_KX33XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KX33XX +# endif +# define machine_is_kx33xx() (machine_arch_type == MACH_TYPE_KX33XX) +#else +# define machine_is_kx33xx() (0) +#endif + +#ifdef CONFIG_MACH_PTX7510 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PTX7510 +# endif +# define machine_is_ptx7510() (machine_arch_type == MACH_TYPE_PTX7510) +#else +# define machine_is_ptx7510() (0) +#endif + +#ifdef CONFIG_MACH_TOP9000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOP9000 +# endif +# define machine_is_top9000() (machine_arch_type == MACH_TYPE_TOP9000) +#else +# define machine_is_top9000() (0) +#endif + +#ifdef CONFIG_MACH_TEENOTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEENOTE +# endif +# define machine_is_teenote() (machine_arch_type == MACH_TYPE_TEENOTE) +#else +# define machine_is_teenote() (0) +#endif + +#ifdef CONFIG_MACH_TS3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS3 +# endif +# define machine_is_ts3() (machine_arch_type == MACH_TYPE_TS3) +#else +# define machine_is_ts3() (0) +#endif + +#ifdef CONFIG_MACH_A0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A0 +# endif +# define machine_is_a0() (machine_arch_type == MACH_TYPE_A0) +#else +# define machine_is_a0() (0) +#endif + +#ifdef CONFIG_MACH_FSM9XXX_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FSM9XXX_SURF +# endif +# define machine_is_fsm9xxx_surf() (machine_arch_type == MACH_TYPE_FSM9XXX_SURF) +#else +# define machine_is_fsm9xxx_surf() (0) +#endif + +#ifdef CONFIG_MACH_FSM9XXX_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FSM9XXX_FFA +# endif +# define machine_is_fsm9xxx_ffa() (machine_arch_type == MACH_TYPE_FSM9XXX_FFA) +#else +# define machine_is_fsm9xxx_ffa() (0) +#endif + +#ifdef CONFIG_MACH_FRRHWCDMA60W +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FRRHWCDMA60W +# endif +# define machine_is_frrhwcdma60w() (machine_arch_type == MACH_TYPE_FRRHWCDMA60W) +#else +# define machine_is_frrhwcdma60w() (0) +#endif + +#ifdef CONFIG_MACH_REMUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REMUS +# endif +# define machine_is_remus() (machine_arch_type == MACH_TYPE_REMUS) +#else +# define machine_is_remus() (0) +#endif + +#ifdef CONFIG_MACH_AT91CAP7XDK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91CAP7XDK +# endif +# define machine_is_at91cap7xdk() (machine_arch_type == MACH_TYPE_AT91CAP7XDK) +#else +# define machine_is_at91cap7xdk() (0) +#endif + +#ifdef CONFIG_MACH_AT91CAP7STK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91CAP7STK +# endif +# define machine_is_at91cap7stk() (machine_arch_type == MACH_TYPE_AT91CAP7STK) +#else +# define machine_is_at91cap7stk() (0) +#endif + +#ifdef CONFIG_MACH_KT_SBC_SAM9_1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KT_SBC_SAM9_1 +# endif +# define machine_is_kt_sbc_sam9_1() (machine_arch_type == MACH_TYPE_KT_SBC_SAM9_1) +#else +# define machine_is_kt_sbc_sam9_1() (0) +#endif + +#ifdef CONFIG_MACH_ORATISROUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISROUTER +# endif +# define machine_is_at91sam9263router() (machine_arch_type == MACH_TYPE_ORATISROUTER) +#else +# define machine_is_at91sam9263router() (0) +#endif + +#ifdef CONFIG_MACH_ARMADA_XP_DB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADA_XP_DB +# endif +# define machine_is_armada_xp_db() (machine_arch_type == MACH_TYPE_ARMADA_XP_DB) +#else +# define machine_is_armada_xp_db() (0) +#endif + +#ifdef CONFIG_MACH_SPDM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPDM +# endif +# define machine_is_spdm() (machine_arch_type == MACH_TYPE_SPDM) +#else +# define machine_is_spdm() (0) +#endif + +#ifdef CONFIG_MACH_GTIB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTIB +# endif +# define machine_is_gtib() (machine_arch_type == MACH_TYPE_GTIB) +#else +# define machine_is_gtib() (0) +#endif + +#ifdef CONFIG_MACH_DGM3240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DGM3240 +# endif +# define machine_is_dgm3240() (machine_arch_type == MACH_TYPE_DGM3240) +#else +# define machine_is_dgm3240() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS_I_LPE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS_I_LPE +# endif +# define machine_is_iv_atlas_i_lpe() (machine_arch_type == MACH_TYPE_ATLAS_I_LPE) +#else +# define machine_is_iv_atlas_i_lpe() (0) +#endif + +#ifdef CONFIG_MACH_HTCMEGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCMEGA +# endif +# define machine_is_htcmega() (machine_arch_type == MACH_TYPE_HTCMEGA) +#else +# define machine_is_htcmega() (0) +#endif + +#ifdef CONFIG_MACH_TRICORDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRICORDER +# endif +# define machine_is_tricorder() (machine_arch_type == MACH_TYPE_TRICORDER) +#else +# define machine_is_tricorder() (0) +#endif + +#ifdef CONFIG_MACH_TX28 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX28 +# endif +# define machine_is_tx28() (machine_arch_type == MACH_TYPE_TX28) +#else +# define machine_is_tx28() (0) +#endif + +#ifdef CONFIG_MACH_BSTBRD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSTBRD +# endif +# define machine_is_bstbrd() (machine_arch_type == MACH_TYPE_BSTBRD) +#else +# define machine_is_bstbrd() (0) +#endif + +#ifdef CONFIG_MACH_PWB3090 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PWB3090 +# endif +# define machine_is_pwb3090() (machine_arch_type == MACH_TYPE_PWB3090) +#else +# define machine_is_pwb3090() (0) +#endif + +#ifdef CONFIG_MACH_IDEA6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IDEA6410 +# endif +# define machine_is_idea6410() (machine_arch_type == MACH_TYPE_IDEA6410) +#else +# define machine_is_idea6410() (0) +#endif + +#ifdef CONFIG_MACH_QBC9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QBC9263 +# endif +# define machine_is_qbc9263() (machine_arch_type == MACH_TYPE_QBC9263) +#else +# define machine_is_qbc9263() (0) +#endif + +#ifdef CONFIG_MACH_BORABORA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BORABORA +# endif +# define machine_is_borabora() (machine_arch_type == MACH_TYPE_BORABORA) +#else +# define machine_is_borabora() (0) +#endif + +#ifdef CONFIG_MACH_VALDEZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VALDEZ +# endif +# define machine_is_valdez() (machine_arch_type == MACH_TYPE_VALDEZ) +#else +# define machine_is_valdez() (0) +#endif + +#ifdef CONFIG_MACH_LS9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LS9G20 +# endif +# define machine_is_ls9g20() (machine_arch_type == MACH_TYPE_LS9G20) +#else +# define machine_is_ls9g20() (0) +#endif + +#ifdef CONFIG_MACH_MIOS_V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIOS_V1 +# endif +# define machine_is_mios_v1() (machine_arch_type == MACH_TYPE_MIOS_V1) +#else +# define machine_is_mios_v1() (0) +#endif + +#ifdef CONFIG_MACH_S5PC110_CRESPO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5PC110_CRESPO +# endif +# define machine_is_s5pc110_crespo() (machine_arch_type == MACH_TYPE_S5PC110_CRESPO) +#else +# define machine_is_s5pc110_crespo() (0) +#endif + +#ifdef CONFIG_MACH_CONTROLTEK9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CONTROLTEK9G20 +# endif +# define machine_is_controltek9g20() (machine_arch_type == MACH_TYPE_CONTROLTEK9G20) +#else +# define machine_is_controltek9g20() (0) +#endif + +#ifdef CONFIG_MACH_TIN307 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIN307 +# endif +# define machine_is_tin307() (machine_arch_type == MACH_TYPE_TIN307) +#else +# define machine_is_tin307() (0) +#endif + +#ifdef CONFIG_MACH_TIN510 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIN510 +# endif +# define machine_is_tin510() (machine_arch_type == MACH_TYPE_TIN510) +#else +# define machine_is_tin510() (0) +#endif + +#ifdef CONFIG_MACH_EP3517 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EP3517 +# endif +# define machine_is_ep3505() (machine_arch_type == MACH_TYPE_EP3517) +#else +# define machine_is_ep3505() (0) +#endif + +#ifdef CONFIG_MACH_BLUECHEESE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUECHEESE +# endif +# define machine_is_bluecheese() (machine_arch_type == MACH_TYPE_BLUECHEESE) +#else +# define machine_is_bluecheese() (0) +#endif + +#ifdef CONFIG_MACH_TEM3X30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEM3X30 +# endif +# define machine_is_tem3x30() (machine_arch_type == MACH_TYPE_TEM3X30) +#else +# define machine_is_tem3x30() (0) +#endif + +#ifdef CONFIG_MACH_HARVEST_DESOTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HARVEST_DESOTO +# endif +# define machine_is_harvest_desoto() (machine_arch_type == MACH_TYPE_HARVEST_DESOTO) +#else +# define machine_is_harvest_desoto() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_QRDC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_QRDC +# endif +# define machine_is_msm8x60_qrdc() (machine_arch_type == MACH_TYPE_MSM8X60_QRDC) +#else +# define machine_is_msm8x60_qrdc() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR900 +# endif +# define machine_is_spear900() (machine_arch_type == MACH_TYPE_SPEAR900) +#else +# define machine_is_spear900() (0) +#endif + +#ifdef CONFIG_MACH_PCONTROL_G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCONTROL_G20 +# endif +# define machine_is_pcontrol_g20() (machine_arch_type == MACH_TYPE_PCONTROL_G20) +#else +# define machine_is_pcontrol_g20() (0) +#endif + +#ifdef CONFIG_MACH_RDSTOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RDSTOR +# endif +# define machine_is_rdstor() (machine_arch_type == MACH_TYPE_RDSTOR) +#else +# define machine_is_rdstor() (0) +#endif + +#ifdef CONFIG_MACH_USDLOADER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_USDLOADER +# endif +# define machine_is_usdloader() (machine_arch_type == MACH_TYPE_USDLOADER) +#else +# define machine_is_usdloader() (0) +#endif + +#ifdef CONFIG_MACH_TSOPLOADER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TSOPLOADER +# endif +# define machine_is_tsoploader() (machine_arch_type == MACH_TYPE_TSOPLOADER) +#else +# define machine_is_tsoploader() (0) +#endif + +#ifdef CONFIG_MACH_KRONOS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KRONOS +# endif +# define machine_is_kronos() (machine_arch_type == MACH_TYPE_KRONOS) +#else +# define machine_is_kronos() (0) +#endif + +#ifdef CONFIG_MACH_FFCORE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FFCORE +# endif +# define machine_is_ffcore() (machine_arch_type == MACH_TYPE_FFCORE) +#else +# define machine_is_ffcore() (0) +#endif + +#ifdef CONFIG_MACH_MONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MONE +# endif +# define machine_is_mone() (machine_arch_type == MACH_TYPE_MONE) +#else +# define machine_is_mone() (0) +#endif + +#ifdef CONFIG_MACH_UNIT2S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNIT2S +# endif +# define machine_is_unit2s() (machine_arch_type == MACH_TYPE_UNIT2S) +#else +# define machine_is_unit2s() (0) +#endif + +#ifdef CONFIG_MACH_ACER_A5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACER_A5 +# endif +# define machine_is_acer_a5() (machine_arch_type == MACH_TYPE_ACER_A5) +#else +# define machine_is_acer_a5() (0) +#endif + +#ifdef CONFIG_MACH_ETHERPRO_ISP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETHERPRO_ISP +# endif +# define machine_is_etherpro_isp() (machine_arch_type == MACH_TYPE_ETHERPRO_ISP) +#else +# define machine_is_etherpro_isp() (0) +#endif + +#ifdef CONFIG_MACH_STRETCHS7000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STRETCHS7000 +# endif +# define machine_is_stretchs7000() (machine_arch_type == MACH_TYPE_STRETCHS7000) +#else +# define machine_is_stretchs7000() (0) +#endif + +#ifdef CONFIG_MACH_P87_SMARTSIM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P87_SMARTSIM +# endif +# define machine_is_p87_smartsim() (machine_arch_type == MACH_TYPE_P87_SMARTSIM) +#else +# define machine_is_p87_smartsim() (0) +#endif + +#ifdef CONFIG_MACH_TULIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TULIP +# endif +# define machine_is_tulip() (machine_arch_type == MACH_TYPE_TULIP) +#else +# define machine_is_tulip() (0) +#endif + +#ifdef CONFIG_MACH_SUNFLOWER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUNFLOWER +# endif +# define machine_is_sunflower() (machine_arch_type == MACH_TYPE_SUNFLOWER) +#else +# define machine_is_sunflower() (0) +#endif + +#ifdef CONFIG_MACH_RIB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIB +# endif +# define machine_is_rib() (machine_arch_type == MACH_TYPE_RIB) +#else +# define machine_is_rib() (0) +#endif + +#ifdef CONFIG_MACH_CLOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLOD +# endif +# define machine_is_clod() (machine_arch_type == MACH_TYPE_CLOD) +#else +# define machine_is_clod() (0) +#endif + +#ifdef CONFIG_MACH_RUMP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RUMP +# endif +# define machine_is_rump() (machine_arch_type == MACH_TYPE_RUMP) +#else +# define machine_is_rump() (0) +#endif + +#ifdef CONFIG_MACH_TENDERLOIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TENDERLOIN +# endif +# define machine_is_tenderloin() (machine_arch_type == MACH_TYPE_TENDERLOIN) +#else +# define machine_is_tenderloin() (0) +#endif + +#ifdef CONFIG_MACH_SHORTLOIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHORTLOIN +# endif +# define machine_is_shortloin() (machine_arch_type == MACH_TYPE_SHORTLOIN) +#else +# define machine_is_shortloin() (0) +#endif + +#ifdef CONFIG_MACH_CRESPO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CRESPO +# endif +# define machine_is_roml1() (machine_arch_type == MACH_TYPE_CRESPO) +#else +# define machine_is_roml1() (0) +#endif + +#ifdef CONFIG_MACH_ANTARES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANTARES +# endif +# define machine_is_antares() (machine_arch_type == MACH_TYPE_ANTARES) +#else +# define machine_is_antares() (0) +#endif + +#ifdef CONFIG_MACH_WB40N +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WB40N +# endif +# define machine_is_wb40n() (machine_arch_type == MACH_TYPE_WB40N) +#else +# define machine_is_wb40n() (0) +#endif + +#ifdef CONFIG_MACH_HERRING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HERRING +# endif +# define machine_is_herring() (machine_arch_type == MACH_TYPE_HERRING) +#else +# define machine_is_herring() (0) +#endif + +#ifdef CONFIG_MACH_NAXY400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAXY400 +# endif +# define machine_is_naxy400() (machine_arch_type == MACH_TYPE_NAXY400) +#else +# define machine_is_naxy400() (0) +#endif + +#ifdef CONFIG_MACH_NAXY1200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAXY1200 +# endif +# define machine_is_naxy1200() (machine_arch_type == MACH_TYPE_NAXY1200) +#else +# define machine_is_naxy1200() (0) +#endif + +#ifdef CONFIG_MACH_VPR200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VPR200 +# endif +# define machine_is_vpr200() (machine_arch_type == MACH_TYPE_VPR200) +#else +# define machine_is_vpr200() (0) +#endif + +#ifdef CONFIG_MACH_BUG20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUG20 +# endif +# define machine_is_bug20() (machine_arch_type == MACH_TYPE_BUG20) +#else +# define machine_is_bug20() (0) +#endif + +#ifdef CONFIG_MACH_GOFLEXNET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GOFLEXNET +# endif +# define machine_is_goflexnet() (machine_arch_type == MACH_TYPE_GOFLEXNET) +#else +# define machine_is_goflexnet() (0) +#endif + +#ifdef CONFIG_MACH_TORBRECK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TORBRECK +# endif +# define machine_is_torbreck() (machine_arch_type == MACH_TYPE_TORBRECK) +#else +# define machine_is_torbreck() (0) +#endif + +#ifdef CONFIG_MACH_SAARB_MG1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAARB_MG1 +# endif +# define machine_is_saarb_mg1() (machine_arch_type == MACH_TYPE_SAARB_MG1) +#else +# define machine_is_saarb_mg1() (0) +#endif + +#ifdef CONFIG_MACH_CALLISTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CALLISTO +# endif +# define machine_is_callisto() (machine_arch_type == MACH_TYPE_CALLISTO) +#else +# define machine_is_callisto() (0) +#endif + +#ifdef CONFIG_MACH_MULTHSU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTHSU +# endif +# define machine_is_multhsu() (machine_arch_type == MACH_TYPE_MULTHSU) +#else +# define machine_is_multhsu() (0) +#endif + +#ifdef CONFIG_MACH_SALUDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SALUDA +# endif +# define machine_is_saluda() (machine_arch_type == MACH_TYPE_SALUDA) +#else +# define machine_is_saluda() (0) +#endif + +#ifdef CONFIG_MACH_PEMP_OMAP3_APOLLO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEMP_OMAP3_APOLLO +# endif +# define machine_is_pemp_omap3_apollo() (machine_arch_type == MACH_TYPE_PEMP_OMAP3_APOLLO) +#else +# define machine_is_pemp_omap3_apollo() (0) +#endif + +#ifdef CONFIG_MACH_VC0718 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC0718 +# endif +# define machine_is_vc0718() (machine_arch_type == MACH_TYPE_VC0718) +#else +# define machine_is_vc0718() (0) +#endif + +#ifdef CONFIG_MACH_MVBLX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MVBLX +# endif +# define machine_is_mvblx() (machine_arch_type == MACH_TYPE_MVBLX) +#else +# define machine_is_mvblx() (0) +#endif + +#ifdef CONFIG_MACH_INHAND_APEIRON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHAND_APEIRON +# endif +# define machine_is_inhand_apeiron() (machine_arch_type == MACH_TYPE_INHAND_APEIRON) +#else +# define machine_is_inhand_apeiron() (0) +#endif + +#ifdef CONFIG_MACH_INHAND_FURY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHAND_FURY +# endif +# define machine_is_inhand_fury() (machine_arch_type == MACH_TYPE_INHAND_FURY) +#else +# define machine_is_inhand_fury() (0) +#endif + +#ifdef CONFIG_MACH_INHAND_SIREN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INHAND_SIREN +# endif +# define machine_is_inhand_siren() (machine_arch_type == MACH_TYPE_INHAND_SIREN) +#else +# define machine_is_inhand_siren() (0) +#endif + +#ifdef CONFIG_MACH_HDNVP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDNVP +# endif +# define machine_is_hdnvp() (machine_arch_type == MACH_TYPE_HDNVP) +#else +# define machine_is_hdnvp() (0) +#endif + +#ifdef CONFIG_MACH_SOFTWINNER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SOFTWINNER +# endif +# define machine_is_softwinner() (machine_arch_type == MACH_TYPE_SOFTWINNER) +#else +# define machine_is_softwinner() (0) +#endif + +#ifdef CONFIG_MACH_PRIMA2_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRIMA2_EVB +# endif +# define machine_is_prima2_evb() (machine_arch_type == MACH_TYPE_PRIMA2_EVB) +#else +# define machine_is_prima2_evb() (0) +#endif + +#ifdef CONFIG_MACH_NAS6210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAS6210 +# endif +# define machine_is_nas6210() (machine_arch_type == MACH_TYPE_NAS6210) +#else +# define machine_is_nas6210() (0) +#endif + +#ifdef CONFIG_MACH_UNISDEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNISDEV +# endif +# define machine_is_unisdev() (machine_arch_type == MACH_TYPE_UNISDEV) +#else +# define machine_is_unisdev() (0) +#endif + +#ifdef CONFIG_MACH_SBCA11 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBCA11 +# endif +# define machine_is_sbca11() (machine_arch_type == MACH_TYPE_SBCA11) +#else +# define machine_is_sbca11() (0) +#endif + +#ifdef CONFIG_MACH_SAGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAGA +# endif +# define machine_is_saga() (machine_arch_type == MACH_TYPE_SAGA) +#else +# define machine_is_saga() (0) +#endif + +#ifdef CONFIG_MACH_NS_K330 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NS_K330 +# endif +# define machine_is_ns_k330() (machine_arch_type == MACH_TYPE_NS_K330) +#else +# define machine_is_ns_k330() (0) +#endif + +#ifdef CONFIG_MACH_TANNA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TANNA +# endif +# define machine_is_tanna() (machine_arch_type == MACH_TYPE_TANNA) +#else +# define machine_is_tanna() (0) +#endif + +#ifdef CONFIG_MACH_IMATE8502 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMATE8502 +# endif +# define machine_is_imate8502() (machine_arch_type == MACH_TYPE_IMATE8502) +#else +# define machine_is_imate8502() (0) +#endif + +#ifdef CONFIG_MACH_ASPEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASPEN +# endif +# define machine_is_aspen() (machine_arch_type == MACH_TYPE_ASPEN) +#else +# define machine_is_aspen() (0) +#endif + +#ifdef CONFIG_MACH_DAINTREE_CWAC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAINTREE_CWAC +# endif +# define machine_is_daintree_cwac() (machine_arch_type == MACH_TYPE_DAINTREE_CWAC) +#else +# define machine_is_daintree_cwac() (0) +#endif + +#ifdef CONFIG_MACH_ZMX25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZMX25 +# endif +# define machine_is_zmx25() (machine_arch_type == MACH_TYPE_ZMX25) +#else +# define machine_is_zmx25() (0) +#endif + +#ifdef CONFIG_MACH_MAPLE1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAPLE1 +# endif +# define machine_is_maple1() (machine_arch_type == MACH_TYPE_MAPLE1) +#else +# define machine_is_maple1() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X72_SURF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X72_SURF +# endif +# define machine_is_qsd8x72_surf() (machine_arch_type == MACH_TYPE_QSD8X72_SURF) +#else +# define machine_is_qsd8x72_surf() (0) +#endif + +#ifdef CONFIG_MACH_QSD8X72_FFA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QSD8X72_FFA +# endif +# define machine_is_qsd8x72_ffa() (machine_arch_type == MACH_TYPE_QSD8X72_FFA) +#else +# define machine_is_qsd8x72_ffa() (0) +#endif + +#ifdef CONFIG_MACH_ABILENE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ABILENE +# endif +# define machine_is_abilene() (machine_arch_type == MACH_TYPE_ABILENE) +#else +# define machine_is_abilene() (0) +#endif + +#ifdef CONFIG_MACH_EIGEN_TTR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EIGEN_TTR +# endif +# define machine_is_eigen_ttr() (machine_arch_type == MACH_TYPE_EIGEN_TTR) +#else +# define machine_is_eigen_ttr() (0) +#endif + +#ifdef CONFIG_MACH_IOMEGA_IX2_200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IOMEGA_IX2_200 +# endif +# define machine_is_iomega_ix2_200() (machine_arch_type == MACH_TYPE_IOMEGA_IX2_200) +#else +# define machine_is_iomega_ix2_200() (0) +#endif + +#ifdef CONFIG_MACH_CORETEC_VCX7400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORETEC_VCX7400 +# endif +# define machine_is_coretec_vcx7400() (machine_arch_type == MACH_TYPE_CORETEC_VCX7400) +#else +# define machine_is_coretec_vcx7400() (0) +#endif + +#ifdef CONFIG_MACH_SANTIAGO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANTIAGO +# endif +# define machine_is_santiago() (machine_arch_type == MACH_TYPE_SANTIAGO) +#else +# define machine_is_santiago() (0) +#endif + +#ifdef CONFIG_MACH_MX257SOL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX257SOL +# endif +# define machine_is_mx257sol() (machine_arch_type == MACH_TYPE_MX257SOL) +#else +# define machine_is_mx257sol() (0) +#endif + +#ifdef CONFIG_MACH_STRASBOURG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STRASBOURG +# endif +# define machine_is_strasbourg() (machine_arch_type == MACH_TYPE_STRASBOURG) +#else +# define machine_is_strasbourg() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_FLUID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_FLUID +# endif +# define machine_is_msm8x60_fluid() (machine_arch_type == MACH_TYPE_MSM8X60_FLUID) +#else +# define machine_is_msm8x60_fluid() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQV5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQV5 +# endif +# define machine_is_smartqv5() (machine_arch_type == MACH_TYPE_SMARTQV5) +#else +# define machine_is_smartqv5() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQV3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQV3 +# endif +# define machine_is_smartqv3() (machine_arch_type == MACH_TYPE_SMARTQV3) +#else +# define machine_is_smartqv3() (0) +#endif + +#ifdef CONFIG_MACH_SMARTQV7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTQV7 +# endif +# define machine_is_smartqv7() (machine_arch_type == MACH_TYPE_SMARTQV7) +#else +# define machine_is_smartqv7() (0) +#endif + +#ifdef CONFIG_MACH_PAZ00 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PAZ00 +# endif +# define machine_is_tegra_paz00() (machine_arch_type == MACH_TYPE_PAZ00) +#else +# define machine_is_tegra_paz00() (0) +#endif + +#ifdef CONFIG_MACH_ACMENETUSFOXG20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACMENETUSFOXG20 +# endif +# define machine_is_acmenetusfoxg20() (machine_arch_type == MACH_TYPE_ACMENETUSFOXG20) +#else +# define machine_is_acmenetusfoxg20() (0) +#endif + +#ifdef CONFIG_MACH_HTCWILLOW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCWILLOW +# endif +# define machine_is_htc_willow() (machine_arch_type == MACH_TYPE_HTCWILLOW) +#else +# define machine_is_htc_willow() (0) +#endif + +#ifdef CONFIG_MACH_FWBD_0404 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FWBD_0404 +# endif +# define machine_is_fwbd_0404() (machine_arch_type == MACH_TYPE_FWBD_0404) +#else +# define machine_is_fwbd_0404() (0) +#endif + +#ifdef CONFIG_MACH_HDGU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDGU +# endif +# define machine_is_hdgu() (machine_arch_type == MACH_TYPE_HDGU) +#else +# define machine_is_hdgu() (0) +#endif + +#ifdef CONFIG_MACH_PYRAMID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PYRAMID +# endif +# define machine_is_pyramid() (machine_arch_type == MACH_TYPE_PYRAMID) +#else +# define machine_is_pyramid() (0) +#endif + +#ifdef CONFIG_MACH_EPIPHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EPIPHAN +# endif +# define machine_is_epiphan() (machine_arch_type == MACH_TYPE_EPIPHAN) +#else +# define machine_is_epiphan() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_BENDER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_BENDER +# endif +# define machine_is_omap_bender() (machine_arch_type == MACH_TYPE_OMAP_BENDER) +#else +# define machine_is_omap_bender() (0) +#endif + +#ifdef CONFIG_MACH_GURNARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GURNARD +# endif +# define machine_is_gurnard() (machine_arch_type == MACH_TYPE_GURNARD) +#else +# define machine_is_gurnard() (0) +#endif + +#ifdef CONFIG_MACH_GTL_IT5100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTL_IT5100 +# endif +# define machine_is_gtl_it5100() (machine_arch_type == MACH_TYPE_GTL_IT5100) +#else +# define machine_is_gtl_it5100() (0) +#endif + +#ifdef CONFIG_MACH_BCM2708 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM2708 +# endif +# define machine_is_bcm2708() (machine_arch_type == MACH_TYPE_BCM2708) +#else +# define machine_is_bcm2708() (0) +#endif + +#ifdef CONFIG_MACH_MX51_GGC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_GGC +# endif +# define machine_is_mx51_ggc() (machine_arch_type == MACH_TYPE_MX51_GGC) +#else +# define machine_is_mx51_ggc() (0) +#endif + +#ifdef CONFIG_MACH_SHARESPACE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHARESPACE +# endif +# define machine_is_sharespace() (machine_arch_type == MACH_TYPE_SHARESPACE) +#else +# define machine_is_sharespace() (0) +#endif + +#ifdef CONFIG_MACH_HABA_KNX_EXPLORER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HABA_KNX_EXPLORER +# endif +# define machine_is_haba_knx_explorer() (machine_arch_type == MACH_TYPE_HABA_KNX_EXPLORER) +#else +# define machine_is_haba_knx_explorer() (0) +#endif + +#ifdef CONFIG_MACH_SIMTEC_KIRKMOD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMTEC_KIRKMOD +# endif +# define machine_is_simtec_kirkmod() (machine_arch_type == MACH_TYPE_SIMTEC_KIRKMOD) +#else +# define machine_is_simtec_kirkmod() (0) +#endif + +#ifdef CONFIG_MACH_CRUX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CRUX +# endif +# define machine_is_crux() (machine_arch_type == MACH_TYPE_CRUX) +#else +# define machine_is_crux() (0) +#endif + +#ifdef CONFIG_MACH_MX51_BRAVO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_BRAVO +# endif +# define machine_is_mx51_bravo() (machine_arch_type == MACH_TYPE_MX51_BRAVO) +#else +# define machine_is_mx51_bravo() (0) +#endif + +#ifdef CONFIG_MACH_CHARON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHARON +# endif +# define machine_is_charon() (machine_arch_type == MACH_TYPE_CHARON) +#else +# define machine_is_charon() (0) +#endif + +#ifdef CONFIG_MACH_PICOCOM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOCOM3 +# endif +# define machine_is_picocom3() (machine_arch_type == MACH_TYPE_PICOCOM3) +#else +# define machine_is_picocom3() (0) +#endif + +#ifdef CONFIG_MACH_PICOCOM4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PICOCOM4 +# endif +# define machine_is_picocom4() (machine_arch_type == MACH_TYPE_PICOCOM4) +#else +# define machine_is_picocom4() (0) +#endif + +#ifdef CONFIG_MACH_SERRANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SERRANO +# endif +# define machine_is_serrano() (machine_arch_type == MACH_TYPE_SERRANO) +#else +# define machine_is_serrano() (0) +#endif + +#ifdef CONFIG_MACH_DOUBLESHOT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOUBLESHOT +# endif +# define machine_is_doubleshot() (machine_arch_type == MACH_TYPE_DOUBLESHOT) +#else +# define machine_is_doubleshot() (0) +#endif + +#ifdef CONFIG_MACH_EVSY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EVSY +# endif +# define machine_is_evsy() (machine_arch_type == MACH_TYPE_EVSY) +#else +# define machine_is_evsy() (0) +#endif + +#ifdef CONFIG_MACH_HUASHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUASHAN +# endif +# define machine_is_huashan() (machine_arch_type == MACH_TYPE_HUASHAN) +#else +# define machine_is_huashan() (0) +#endif + +#ifdef CONFIG_MACH_LAUSANNE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LAUSANNE +# endif +# define machine_is_lausanne() (machine_arch_type == MACH_TYPE_LAUSANNE) +#else +# define machine_is_lausanne() (0) +#endif + +#ifdef CONFIG_MACH_EMERALD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMERALD +# endif +# define machine_is_emerald() (machine_arch_type == MACH_TYPE_EMERALD) +#else +# define machine_is_emerald() (0) +#endif + +#ifdef CONFIG_MACH_TQMA35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TQMA35 +# endif +# define machine_is_tqma35() (machine_arch_type == MACH_TYPE_TQMA35) +#else +# define machine_is_tqma35() (0) +#endif + +#ifdef CONFIG_MACH_MARVEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARVEL +# endif +# define machine_is_marvel() (machine_arch_type == MACH_TYPE_MARVEL) +#else +# define machine_is_marvel() (0) +#endif + +#ifdef CONFIG_MACH_MANUAE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MANUAE +# endif +# define machine_is_manuae() (machine_arch_type == MACH_TYPE_MANUAE) +#else +# define machine_is_manuae() (0) +#endif + +#ifdef CONFIG_MACH_CHACHA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHACHA +# endif +# define machine_is_chacha() (machine_arch_type == MACH_TYPE_CHACHA) +#else +# define machine_is_chacha() (0) +#endif + +#ifdef CONFIG_MACH_LEMON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEMON +# endif +# define machine_is_lemon() (machine_arch_type == MACH_TYPE_LEMON) +#else +# define machine_is_lemon() (0) +#endif + +#ifdef CONFIG_MACH_CSC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSC +# endif +# define machine_is_csc() (machine_arch_type == MACH_TYPE_CSC) +#else +# define machine_is_csc() (0) +#endif + +#ifdef CONFIG_MACH_GIRA_KNXIP_ROUTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GIRA_KNXIP_ROUTER +# endif +# define machine_is_gira_knxip_router() (machine_arch_type == MACH_TYPE_GIRA_KNXIP_ROUTER) +#else +# define machine_is_gira_knxip_router() (0) +#endif + +#ifdef CONFIG_MACH_T20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T20 +# endif +# define machine_is_t20() (machine_arch_type == MACH_TYPE_T20) +#else +# define machine_is_t20() (0) +#endif + +#ifdef CONFIG_MACH_HDMINI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HDMINI +# endif +# define machine_is_hdmini() (machine_arch_type == MACH_TYPE_HDMINI) +#else +# define machine_is_hdmini() (0) +#endif + +#ifdef CONFIG_MACH_SCIPHONE_G2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCIPHONE_G2 +# endif +# define machine_is_sciphone_g2() (machine_arch_type == MACH_TYPE_SCIPHONE_G2) +#else +# define machine_is_sciphone_g2() (0) +#endif + +#ifdef CONFIG_MACH_EXPRESS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXPRESS +# endif +# define machine_is_express() (machine_arch_type == MACH_TYPE_EXPRESS) +#else +# define machine_is_express() (0) +#endif + +#ifdef CONFIG_MACH_EXPRESS_KT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXPRESS_KT +# endif +# define machine_is_express_kt() (machine_arch_type == MACH_TYPE_EXPRESS_KT) +#else +# define machine_is_express_kt() (0) +#endif + +#ifdef CONFIG_MACH_MAXIMASP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAXIMASP +# endif +# define machine_is_maximasp() (machine_arch_type == MACH_TYPE_MAXIMASP) +#else +# define machine_is_maximasp() (0) +#endif + +#ifdef CONFIG_MACH_NITROGEN_IMX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NITROGEN_IMX51 +# endif +# define machine_is_nitrogen_imx51() (machine_arch_type == MACH_TYPE_NITROGEN_IMX51) +#else +# define machine_is_nitrogen_imx51() (0) +#endif + +#ifdef CONFIG_MACH_NITROGEN_IMX53 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NITROGEN_IMX53 +# endif +# define machine_is_nitrogen_imx53() (machine_arch_type == MACH_TYPE_NITROGEN_IMX53) +#else +# define machine_is_nitrogen_imx53() (0) +#endif + +#ifdef CONFIG_MACH_SUNFIRE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUNFIRE +# endif +# define machine_is_sunfire() (machine_arch_type == MACH_TYPE_SUNFIRE) +#else +# define machine_is_sunfire() (0) +#endif + +#ifdef CONFIG_MACH_AROWANA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AROWANA +# endif +# define machine_is_arowana() (machine_arch_type == MACH_TYPE_AROWANA) +#else +# define machine_is_arowana() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_DAYTONA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_DAYTONA +# endif +# define machine_is_tegra_daytona() (machine_arch_type == MACH_TYPE_TEGRA_DAYTONA) +#else +# define machine_is_tegra_daytona() (0) +#endif + +#ifdef CONFIG_MACH_TEGRA_SWORDFISH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEGRA_SWORDFISH +# endif +# define machine_is_tegra_swordfish() (machine_arch_type == MACH_TYPE_TEGRA_SWORDFISH) +#else +# define machine_is_tegra_swordfish() (0) +#endif + +#ifdef CONFIG_MACH_EDISON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDISON +# endif +# define machine_is_edison() (machine_arch_type == MACH_TYPE_EDISON) +#else +# define machine_is_edison() (0) +#endif + +#ifdef CONFIG_MACH_SVP8500V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SVP8500V1 +# endif +# define machine_is_svp8500v1() (machine_arch_type == MACH_TYPE_SVP8500V1) +#else +# define machine_is_svp8500v1() (0) +#endif + +#ifdef CONFIG_MACH_SVP8500V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SVP8500V2 +# endif +# define machine_is_svp8500v2() (machine_arch_type == MACH_TYPE_SVP8500V2) +#else +# define machine_is_svp8500v2() (0) +#endif + +#ifdef CONFIG_MACH_SVP5500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SVP5500 +# endif +# define machine_is_svp5500() (machine_arch_type == MACH_TYPE_SVP5500) +#else +# define machine_is_svp5500() (0) +#endif + +#ifdef CONFIG_MACH_B5500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_B5500 +# endif +# define machine_is_b5500() (machine_arch_type == MACH_TYPE_B5500) +#else +# define machine_is_b5500() (0) +#endif + +#ifdef CONFIG_MACH_S5500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5500 +# endif +# define machine_is_s5500() (machine_arch_type == MACH_TYPE_S5500) +#else +# define machine_is_s5500() (0) +#endif + +#ifdef CONFIG_MACH_ICON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICON +# endif +# define machine_is_icon() (machine_arch_type == MACH_TYPE_ICON) +#else +# define machine_is_icon() (0) +#endif + +#ifdef CONFIG_MACH_ELEPHANT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELEPHANT +# endif +# define machine_is_elephant() (machine_arch_type == MACH_TYPE_ELEPHANT) +#else +# define machine_is_elephant() (0) +#endif + +#ifdef CONFIG_MACH_MSM8X60_FUSION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM8X60_FUSION +# endif +# define machine_is_msm8x60_fusion() (machine_arch_type == MACH_TYPE_MSM8X60_FUSION) +#else +# define machine_is_msm8x60_fusion() (0) +#endif + +#ifdef CONFIG_MACH_SHOOTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHOOTER +# endif +# define machine_is_shooter() (machine_arch_type == MACH_TYPE_SHOOTER) +#else +# define machine_is_shooter() (0) +#endif + +#ifdef CONFIG_MACH_SPADE_LTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPADE_LTE +# endif +# define machine_is_spade_lte() (machine_arch_type == MACH_TYPE_SPADE_LTE) +#else +# define machine_is_spade_lte() (0) +#endif + +#ifdef CONFIG_MACH_PHILHWANI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHILHWANI +# endif +# define machine_is_philhwani() (machine_arch_type == MACH_TYPE_PHILHWANI) +#else +# define machine_is_philhwani() (0) +#endif + +#ifdef CONFIG_MACH_GSNCOMM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GSNCOMM +# endif +# define machine_is_gsncomm() (machine_arch_type == MACH_TYPE_GSNCOMM) +#else +# define machine_is_gsncomm() (0) +#endif + +#ifdef CONFIG_MACH_STRASBOURG_A2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STRASBOURG_A2 +# endif +# define machine_is_strasbourg_a2() (machine_arch_type == MACH_TYPE_STRASBOURG_A2) +#else +# define machine_is_strasbourg_a2() (0) +#endif + /* * These have not yet been registered */ -/* #define MACH_TYPE_367 <> */ -#define machine_is_esl_wireless_tab() (0) #ifndef machine_arch_type #define machine_arch_type __machine_arch_type diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h index 71dc049da..13e9806bd 100644 --- a/include/asm-arm/types.h +++ b/include/asm-arm/types.h @@ -17,9 +17,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif /* @@ -45,9 +45,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - #endif /* __KERNEL__ */ #endif diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h index 4ee5a327e..41e7a8f7d 100644 --- a/include/asm-arm/u-boot-arm.h +++ b/include/asm-arm/u-boot-arm.h @@ -52,7 +52,7 @@ void setup_revision_tag (struct tag **params); /* To be fixed! */ /* ------------------------------------------------------------ */ /* common/cmd_nvedit.c */ -int setenv (char *, char *); +void setenv (char *, char *); /* cpu/.../interrupt.c */ void reset_timer_masked (void); diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h index b11d5558f..fc2747599 100644 --- a/include/asm-arm/u-boot.h +++ b/include/asm-arm/u-boot.h @@ -47,11 +47,14 @@ typedef struct bd_info { { ulong start; ulong size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; + } bi_dram[CONFIG_NR_DRAM_BANKS]; #ifdef CONFIG_HAS_ETH1 /* second onboard ethernet port */ unsigned char bi_enet1addr[6]; #endif +#ifdef CONFIG_BOARD_REVISION + ulong bi_board_revision; +#endif } bd_t; #define bi_env_data bi_env->data diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h index 2e55b6a61..65d2c2534 100644 --- a/include/asm-blackfin/bitops.h +++ b/include/asm-blackfin/bitops.h @@ -1,7 +1,7 @@ /* * U-boot - bitops.h Routines for bit operations * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _BLACKFIN_BITOPS_H @@ -59,20 +59,20 @@ static __inline__ unsigned long ffz(unsigned long word) static __inline__ void set_bit(int nr, volatile void *addr) { - int *a = (int *)addr; + int *a = (int *) addr; int mask; unsigned long flags; a += nr >> 5; mask = 1 << (nr & 0x1f); - local_irq_save(flags); + save_and_cli(flags); *a |= mask; - local_irq_restore(flags); + restore_flags(flags); } static __inline__ void __set_bit(int nr, volatile void *addr) { - int *a = (int *)addr; + int *a = (int *) addr; int mask; a += nr >> 5; @@ -88,33 +88,33 @@ static __inline__ void __set_bit(int nr, volatile void *addr) static __inline__ void clear_bit(int nr, volatile void *addr) { - int *a = (int *)addr; + int *a = (int *) addr; int mask; unsigned long flags; a += nr >> 5; mask = 1 << (nr & 0x1f); - local_irq_save(flags); + save_and_cli(flags); *a &= ~mask; - local_irq_restore(flags); + restore_flags(flags); } static __inline__ void change_bit(int nr, volatile void *addr) { int mask, flags; - unsigned long *ADDR = (unsigned long *)addr; + unsigned long *ADDR = (unsigned long *) addr; ADDR += nr >> 5; mask = 1 << (nr & 31); - local_irq_save(flags); + save_and_cli(flags); *ADDR ^= mask; - local_irq_restore(flags); + restore_flags(flags); } static __inline__ void __change_bit(int nr, volatile void *addr) { int mask; - unsigned long *ADDR = (unsigned long *)addr; + unsigned long *ADDR = (unsigned long *) addr; ADDR += nr >> 5; mask = 1 << (nr & 31); @@ -124,15 +124,15 @@ static __inline__ void __change_bit(int nr, volatile void *addr) static __inline__ int test_and_set_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; + volatile unsigned int *a = (volatile unsigned int *) addr; unsigned long flags; a += nr >> 5; mask = 1 << (nr & 0x1f); - local_irq_save(flags); + save_and_cli(flags); retval = (mask & *a) != 0; *a |= mask; - local_irq_restore(flags); + restore_flags(flags); return retval; } @@ -140,7 +140,7 @@ static __inline__ int test_and_set_bit(int nr, volatile void *addr) static __inline__ int __test_and_set_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; + volatile unsigned int *a = (volatile unsigned int *) addr; a += nr >> 5; mask = 1 << (nr & 0x1f); @@ -152,15 +152,15 @@ static __inline__ int __test_and_set_bit(int nr, volatile void *addr) static __inline__ int test_and_clear_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; + volatile unsigned int *a = (volatile unsigned int *) addr; unsigned long flags; a += nr >> 5; mask = 1 << (nr & 0x1f); - local_irq_save(flags); + save_and_cli(flags); retval = (mask & *a) != 0; *a &= ~mask; - local_irq_restore(flags); + restore_flags(flags); return retval; } @@ -168,7 +168,7 @@ static __inline__ int test_and_clear_bit(int nr, volatile void *addr) static __inline__ int __test_and_clear_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; + volatile unsigned int *a = (volatile unsigned int *) addr; a += nr >> 5; mask = 1 << (nr & 0x1f); @@ -180,15 +180,15 @@ static __inline__ int __test_and_clear_bit(int nr, volatile void *addr) static __inline__ int test_and_change_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; + volatile unsigned int *a = (volatile unsigned int *) addr; unsigned long flags; a += nr >> 5; mask = 1 << (nr & 0x1f); - local_irq_save(flags); + save_and_cli(flags); retval = (mask & *a) != 0; *a ^= mask; - local_irq_restore(flags); + restore_flags(flags); return retval; } @@ -196,7 +196,7 @@ static __inline__ int test_and_change_bit(int nr, volatile void *addr) static __inline__ int __test_and_change_bit(int nr, volatile void *addr) { int mask, retval; - volatile unsigned int *a = (volatile unsigned int *)addr; + volatile unsigned int *a = (volatile unsigned int *) addr; a += nr >> 5; mask = 1 << (nr & 0x1f); @@ -208,15 +208,16 @@ static __inline__ int __test_and_change_bit(int nr, volatile void *addr) /* * This routine doesn't need to be atomic. */ -static __inline__ int __constant_test_bit(int nr, const volatile void *addr) +static __inline__ int __constant_test_bit(int nr, + const volatile void *addr) { return ((1UL << (nr & 31)) & - (((const volatile unsigned int *)addr)[nr >> 5])) != 0; + (((const volatile unsigned int *) addr)[nr >> 5])) != 0; } static __inline__ int __test_bit(int nr, volatile void *addr) { - int *a = (int *)addr; + int *a = (int *) addr; int mask; a += nr >> 5; @@ -234,7 +235,7 @@ static __inline__ int __test_bit(int nr, volatile void *addr) static __inline__ int find_next_zero_bit(void *addr, int size, int offset) { - unsigned long *p = ((unsigned long *)addr) + (offset >> 5); + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; unsigned long tmp; @@ -289,14 +290,14 @@ static __inline__ int ext2_set_bit(int nr, volatile void *addr) { int mask, retval; unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *)addr; + volatile unsigned char *ADDR = (unsigned char *) addr; ADDR += nr >> 3; mask = 1 << (nr & 0x07); - local_irq_save(flags); + save_and_cli(flags); retval = (mask & *ADDR) != 0; *ADDR |= mask; - local_irq_restore(flags); + restore_flags(flags); return retval; } @@ -304,21 +305,21 @@ static __inline__ int ext2_clear_bit(int nr, volatile void *addr) { int mask, retval; unsigned long flags; - volatile unsigned char *ADDR = (unsigned char *)addr; + volatile unsigned char *ADDR = (unsigned char *) addr; ADDR += nr >> 3; mask = 1 << (nr & 0x07); - local_irq_save(flags); + save_and_cli(flags); retval = (mask & *ADDR) != 0; *ADDR &= ~mask; - local_irq_restore(flags); + restore_flags(flags); return retval; } static __inline__ int ext2_test_bit(int nr, const volatile void *addr) { int mask; - const volatile unsigned char *ADDR = (const unsigned char *)addr; + const volatile unsigned char *ADDR = (const unsigned char *) addr; ADDR += nr >> 3; mask = 1 << (nr & 0x07); @@ -330,9 +331,10 @@ static __inline__ int ext2_test_bit(int nr, const volatile void *addr) static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, - unsigned long offset) + unsigned long + offset) { - unsigned long *p = ((unsigned long *)addr) + (offset >> 5); + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); unsigned long result = offset & ~31UL; unsigned long tmp; diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h index 204d02b5f..fbdbf30fa 100644 --- a/include/asm-blackfin/blackfin.h +++ b/include/asm-blackfin/blackfin.h @@ -1,15 +1,46 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh - * DO NOT EDIT THIS FILE +/* + * U-boot - blackfin.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ -#ifndef __MACH_GLOB_BLACKFIN__ -#define __MACH_GLOB_BLACKFIN__ +#ifndef _BLACKFIN_H_ +#define _BLACKFIN_H_ + +#include +#include -#include "blackfin_def.h" #ifndef __ASSEMBLY__ -#include "blackfin_cdef.h" -#endif -#include "blackfin_local.h" +#ifndef ASSEMBLY -#endif /* __MACH_GLOB_BLACKFIN__ */ +#ifdef SHARED_RESOURCES + #include +#endif +#include + +#endif +#endif + +#include +#include +#include + +#endif diff --git a/include/asm-blackfin/blackfin_defs.h b/include/asm-blackfin/blackfin_defs.h new file mode 100644 index 000000000..219021597 --- /dev/null +++ b/include/asm-blackfin/blackfin_defs.h @@ -0,0 +1,83 @@ +/* + * U-boot - blackfin_defs.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_DEFS_H__ +#define __BLACKFIN_DEFS_H__ + +#define TS_MAGICKEY 0x5a5a5a5a +#define TASK_STATE 0 +#define TASK_FLAGS 4 +#define TASK_PTRACE 24 +#define TASK_BLOCKED 636 +#define TASK_COUNTER 32 +#define TASK_SIGPENDING 8 +#define TASK_NEEDRESCHED 20 +#define TASK_THREAD 600 +#define TASK_MM 44 +#define TASK_ACTIVE_MM 80 +#define THREAD_KSP 0 +#define THREAD_USP 4 +#define THREAD_SR 8 +#define THREAD_ESP0 12 +#define THREAD_PC 16 +#define PT_ORIG_R0 208 +#define PT_R0 204 +#define PT_R1 200 +#define PT_R2 196 +#define PT_R3 192 +#define PT_R4 188 +#define PT_R5 184 +#define PT_R6 180 +#define PT_R7 176 +#define PT_P0 172 +#define PT_P1 168 +#define PT_P2 164 +#define PT_P3 160 +#define PT_P4 156 +#define PT_P5 152 +#define PT_A0w 72 +#define PT_A1w 64 +#define PT_A0x 76 +#define PT_A1x 68 +#define PT_RETS 28 +#define PT_RESERVED 32 +#define PT_ASTAT 36 +#define PT_SEQSTAT 8 +#define PT_PC 24 +#define PT_IPEND 0 +#define PT_USP 144 +#define PT_FP 148 +#define PT_SYSCFG 4 +#define IRQ_HANDLER 0 +#define IRQ_DEVID 8 +#define IRQ_NEXT 16 +#define STAT_IRQ 5148 +#define SIGSEGV 11 +#define SEGV_MAPERR 196609 +#define SIGTRAP 5 +#define PT_PTRACED 1 +#define PT_TRACESYS 2 +#define PT_DTRACE 4 + +#endif diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h index a1a52a5c1..3b4df4e13 100644 --- a/include/asm-blackfin/byteorder.h +++ b/include/asm-blackfin/byteorder.h @@ -1,7 +1,7 @@ /* * U-boot - byteorder.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _BLACKFIN_BYTEORDER_H diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index e36af2da3..7715f645d 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -1,20 +1,20 @@ -/* - * cplb.h - defines for managing CPLB tables +/************************************************************************ * - * Copyright (c) 2002-2007 Analog Devices Inc. + * cplb.h * - * Licensed under the GPL-2 or later. - */ + * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. + * + ************************************************************************/ -#ifndef __ASM_BLACKFIN_CPLB_H__ -#define __ASM_BLACKFIN_CPLB_H__ +/* Defines necessary for cplb initialisation routines. */ -#include +#ifndef _CPLB_H +#define _CPLB_H #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1 #define CPLB_ENABLE_DCACHE2_P 2 -#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */ +#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated!*/ #define CPLB_ENABLE_ICPLBS_P 4 #define CPLB_ENABLE_DCPLBS_P 5 @@ -42,40 +42,7 @@ #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE -#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID -#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL +#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID +#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL -/* Data Attibutes*/ - -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) -#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) -#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) - -#if ANOMALY_05000158 -# define ANOMALY_05000158_WORKAROUND 0x200 -#else -# define ANOMALY_05000158_WORKAROUND 0 -#endif - -#ifdef CONFIG_DCACHE_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) -#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) - -#else /*Write Through */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) -#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) -#endif - -#if defined(CONFIG_BF561) -#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */ -#else -#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */ -#endif -#endif /* _CPLB_H */ +#endif /* _CPLB_H */ diff --git a/include/asm-blackfin/cplbtab.h b/include/asm-blackfin/cplbtab.h new file mode 100644 index 000000000..ab7d989b1 --- /dev/null +++ b/include/asm-blackfin/cplbtab.h @@ -0,0 +1,572 @@ +/*This file is subject to the terms and conditions of the GNU General Public + * License. + * + * Blackfin BF533/2.6 support : LG Soft India + * Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd + * Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's + * shouldn't be victimized. cplbmgr.S search logic is corrected + * to findout the appropriate victim. + * 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC + * : LG Soft India + */ +#include + +#ifndef __ARCH_BFINNOMMU_CPLBTAB_H +#define __ARCH_BFINNOMMU_CPLBTAB_H + +/************************************************************************* + * ICPLB TABLE + *************************************************************************/ + +.data + +/* This table is configurable */ + +.align 4; + +/* Data Attibutes*/ + +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158 0x200 +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ + #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) + #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) + +#else /*Write Through*/ + #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) + #define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) + #define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) +#endif + +.global icplb_table +icplb_table: +.byte4 0xFFA00000; +.byte4 (L1_IMEMORY); +.byte4 0x00000000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ +.byte4 0x00400000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ +.byte4 0x07C00000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page14*/ +.byte4 0x00800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ +.byte4 0x01000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/ +#ifndef CONFIG_EZKIT /*STAMP Memory regions*/ +.byte4 0x02000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/ +#endif +.byte4 0xffffffff; /* end of section - termination*/ + +.align 4; +.global ipdt_table +ipdt_table: +#ifdef CONFIG_CPLB_INFO +.byte4 0x00000000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page0*/ +.byte4 0x00400000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ +#endif +.byte4 0x00800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page3*/ +.byte4 0x01000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/ +#ifndef CONFIG_EZKIT /*STAMP Memory regions*/ +.byte4 0x02000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/ +.byte4 0x03800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page14*/ +.byte4 0x03C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page15*/ +#endif +.byte4 0x20200000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ +.byte4 0x20100000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ +.byte4 0x20000000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ +.byte4 0x20300000; /*Fix for Network*/ +.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ + +#ifdef CONFIG_STAMP +.byte4 0x04000000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x04400000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x04800000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x04C00000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05000000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05400000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05800000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x05C00000; +.byte4 (SDRAM_IGENERIC); +.byte4 0x06000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page25*/ +.byte4 0x06400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page26*/ +.byte4 0x06800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page27*/ +.byte4 0x06C00000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page28*/ +.byte4 0x07000000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page29*/ +.byte4 0x07400000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page30*/ +.byte4 0x07800000; +.byte4 (SDRAM_IGENERIC); /*SDRAM_Page31*/ +#ifdef CONFIG_CPLB_INFO +.byte4 0x07C00000; +.byte4 (SDRAM_IKERNEL); /*SDRAM_Page32*/ +#endif +#endif +.byte4 0xffffffff; /* end of section - termination*/ + +/********************************************************************* + * DCPLB TABLE + ********************************************************************/ + +.global dcplb_table +dcplb_table: +.byte4 0x00000000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ +.byte4 0x00400000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ +.byte4 0x07C00000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/ +.byte4 0x00800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ +.byte4 0x01000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ +#ifndef CONFIG_EZKIT +.byte4 0x02000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/ +.byte4 0x03800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/ +#endif +.byte4 0xffffffff; /*end of section - termination*/ + +/********************************************************************** + * PAGE DESCRIPTOR TABLE + * + **********************************************************************/ + +/* Till here we are discussing about the static memory management model. + * However, the operating envoronments commonly define more CPLB + * descriptors to cover the entire addressable memory than will fit into + * the available on-chip 16 CPLB MMRs. When this happens, the below table + * will be used which will hold all the potentially required CPLB descriptors + * + * This is how Page descriptor Table is implemented in uClinux/Blackfin. + */ +.global dpdt_table +dpdt_table: +#ifdef CONFIG_CPLB_INFO +.byte4 0x00000000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/ +.byte4 0x00400000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ +#endif +.byte4 0x00800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ +.byte4 0x00C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ +.byte4 0x01000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ +.byte4 0x01400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/ +.byte4 0x01800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ +.byte4 0x01C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ + +#ifndef CONFIG_EZKIT +.byte4 0x02000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ +.byte4 0x02400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/ +.byte4 0x02800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/ +.byte4 0x02C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/ +.byte4 0x03000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/ +.byte4 0x03400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/ +.byte4 0x03800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/ +.byte4 0x03C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page15*/ +#endif +.byte4 0x20200000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ +.byte4 0x20100000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ +.byte4 0x20000000; +.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ +.byte4 0x20300000; /*Fix for Network*/ +.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ + +#ifdef CONFIG_STAMP +.byte4 0x04000000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x04400000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x04800000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x04C00000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05000000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05400000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05800000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x05C00000; +.byte4 (SDRAM_DGENERIC); +.byte4 0x06000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page25*/ +.byte4 0x06400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page26*/ +.byte4 0x06800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page27*/ +.byte4 0x06C00000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page28*/ +.byte4 0x07000000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page29*/ +.byte4 0x07400000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page30*/ +.byte4 0x07800000; +.byte4 (SDRAM_DGENERIC); /*SDRAM_Page31*/ +#ifdef CONFIG_CPLB_INFO +.byte4 0x07C00000; +.byte4 (SDRAM_DKERNEL); /*SDRAM_Page32*/ +#endif +#endif + +.byte4 0xFF900000; +.byte4 (L1_DMEMORY); +.byte4 0xFF901000; +.byte4 (L1_DMEMORY); +.byte4 0xFF902000; +.byte4 (L1_DMEMORY); +.byte4 0xFF903000; +.byte4 (L1_DMEMORY); +.byte4 0xFF904000; +.byte4 (L1_DMEMORY); +.byte4 0xFF905000; +.byte4 (L1_DMEMORY); +.byte4 0xFF906000; +.byte4 (L1_DMEMORY); +.byte4 0xFF907000; +.byte4 (L1_DMEMORY); +.byte4 0xFF800000; +.byte4 (L1_DMEMORY); +.byte4 0xFF801000; +.byte4 (L1_DMEMORY); +.byte4 0xFF802000; +.byte4 (L1_DMEMORY); +.byte4 0xFF803000; +.byte4 (L1_DMEMORY); + +.byte4 0xffffffff; /*end of section - termination*/ + +#ifdef CONFIG_CPLB_INFO +.global ipdt_swapcount_table; /* swapin count first, then swapout count*/ +ipdt_swapcount_table: +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 10 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 20 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 30 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 40 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 50 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 60 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 70 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 90 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 100 */ + +.global dpdt_swapcount_table; /* swapin count first, then swapout count*/ +dpdt_swapcount_table: +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 10 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 20 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 30 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 40 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 50 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 60 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 70 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 80 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 100 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 110 */ +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; +.byte4 0x00000000; /* 120 */ + +#endif + +#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/cpu/bf533_irq.h new file mode 100644 index 000000000..9c5230db4 --- /dev/null +++ b/include/asm-blackfin/cpu/bf533_irq.h @@ -0,0 +1,137 @@ +/* + * U-boot bf533_irq.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c + * Changed by HuTao Apr18, 2003 + * + * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle + * + * Adapted for BlackFin (ADI) by Ted Ma + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc. + * + * Adapted for BlackFin BF533 by Bas Vermeulen + * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl) + + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF533_IRQ_H_ +#define _BF533_IRQ_H_ + +/* + * Interrupt source definitions + * Event Source Core Event Name Number + * EMU 0 + * Reset RST 1 + * NMI NMI 2 + * Exception EVX 3 + * Reserved -- 4 + * Hardware Error IVHW 5 + * Core Timer IVTMR 6 + * PLL Wakeup Interrupt IVG7 7 + * DMA Error (generic) IVG7 8 + * PPI Error Interrupt IVG7 9 + * SPORT0 Error Interrupt IVG7 10 + * SPORT1 Error Interrupt IVG7 11 + * SPI Error Interrupt IVG7 12 + * UART Error Interrupt IVG7 13 + * RTC Interrupt IVG8 14 + * DMA0 Interrupt (PPI) IVG8 15 + * DMA1 (SPORT0 RX) IVG9 16 + * DMA2 (SPORT0 TX) IVG9 17 + * DMA3 (SPORT1 RX) IVG9 18 + * DMA4 (SPORT1 TX) IVG9 19 + * DMA5 (PPI) IVG10 20 + * DMA6 (UART RX) IVG10 21 + * DMA7 (UART TX) IVG10 22 + * Timer0 IVG11 23 + * Timer1 IVG11 24 + * Timer2 IVG11 25 + * PF Interrupt A IVG12 26 + * PF Interrupt B IVG12 27 + * DMA8/9 Interrupt IVG13 28 + * DMA10/11 Interrupt IVG13 29 + * Watchdog Timer IVG13 30 + * Software Interrupt 1 IVG14 31 + * Software Interrupt 2 -- + * (lowest priority) IVG15 32 + */ + +/* The ABSTRACT IRQ definitions */ + +/* The first seven of the following are fixed, + * the rest you change if you need to + */ + +#define IRQ_EMU 0 /* Emulation */ +#define IRQ_RST 1 /* reset */ +#define IRQ_NMI 2 /* Non Maskable */ +#define IRQ_EVX 3 /* Exception */ +#define IRQ_UNUSED 4 /* - unused interrupt */ +#define IRQ_HWERR 5 /* Hardware Error */ +#define IRQ_CORETMR 6 /* Core timer */ +#define IRQ_PLL_WAKEUP 7 /* PLL Wakeup Interrupt */ +#define IRQ_DMA_ERROR 8 /* DMA Error (general) */ +#define IRQ_PPI_ERROR 9 /* PPI Error Interrupt */ +#define IRQ_SPORT0_ERROR 10 /* SPORT0 Error Interrupt */ +#define IRQ_SPORT1_ERROR 11 /* SPORT1 Error Interrupt */ +#define IRQ_SPI_ERROR 12 /* SPI Error Interrupt */ +#define IRQ_UART_ERROR 13 /* UART Error Interrupt */ +#define IRQ_RTC 14 /* RTC Interrupt */ +#define IRQ_PPI 15 /* DMA0 Interrupt (PPI) */ +#define IRQ_SPORT0 16 /* DMA1 Interrupt (SPORT0 RX) */ +#define IRQ_SPARE1 17 /* DMA2 Interrupt (SPORT0 TX) */ +#define IRQ_SPORT1 18 /* DMA3 Interrupt (SPORT1 RX) */ +#define IRQ_SPARE2 19 /* DMA4 Interrupt (SPORT1 TX) */ +#define IRQ_SPI 20 /* DMA5 Interrupt (SPI) */ +#define IRQ_UART 21 /* DMA6 Interrupt (UART RX) */ +#define IRQ_SPARE3 22 /* DMA7 Interrupt (UART TX) */ +#define IRQ_TMR0 23 /* Timer 0 */ +#define IRQ_TMR1 24 /* Timer 1 */ +#define IRQ_TMR2 25 /* Timer 2 */ +#define IRQ_PROG_INTA 26 /* Programmable Flags A (8) */ +#define IRQ_PROG_INTB 27 /* Programmable Flags B (8) */ +#define IRQ_MEM_DMA0 28 /* DMA8/9 Interrupt (Memory DMA Stream 0) */ +#define IRQ_MEM_DMA1 29 /* DMA10/11 Interrupt (Memory DMA Stream 1) */ +#define IRQ_WATCH 30 /* Watch Dog Timer */ +#define IRQ_SW_INT1 31 /* Software Int 1 */ +#define IRQ_SW_INT2 32 /* Software Int 2 (reserved for SYSCALL) */ + +#define IRQ_UART_RX_BIT 0x4000 +#define IRQ_UART_TX_BIT 0x8000 +#define IRQ_UART_ERROR_BIT 0x40 + +#define IVG7 7 +#define IVG8 8 +#define IVG9 9 +#define IVG10 10 +#define IVG11 11 +#define IVG12 12 +#define IVG13 13 +#define IVG14 14 +#define IVG15 15 +#define SYS_IRQS 33 + +#endif diff --git a/include/asm-blackfin/cpu/bf533_rtc.h b/include/asm-blackfin/cpu/bf533_rtc.h new file mode 100644 index 000000000..bc09922a5 --- /dev/null +++ b/include/asm-blackfin/cpu/bf533_rtc.h @@ -0,0 +1,46 @@ +/* + * U-boot - bf533_rtc.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BF533_RTC_H_ +#define _BF533_RTC_H_ + +void rtc_init(void); +void wait_for_complete(void); +void rtc_reset(void); + +#define MIN_TO_SECS(_x_) (60 * _x_) +#define HRS_TO_SECS(_x_) (60 * 60 * _x_) +#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_) + +#define NUM_SECS_IN_DAY (24 * 3600) +#define NUM_SECS_IN_HOUR (3600) +#define NUM_SECS_IN_MIN (60) + +/* Shift values for RTC_STAT register */ +#define DAY_BITS_OFF 17 +#define HOUR_BITS_OFF 12 +#define MIN_BITS_OFF 6 +#define SEC_BITS_OFF 0 + +#endif diff --git a/include/asm-blackfin/cpu/bf533_serial.h b/include/asm-blackfin/cpu/bf533_serial.h new file mode 100644 index 000000000..d5e162a8f --- /dev/null +++ b/include/asm-blackfin/cpu/bf533_serial.h @@ -0,0 +1,79 @@ +/* + * U-boot bf533_serial.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef _BF533_SERIAL_H_ +#define _BF533_SERIAL_H_ + +#define BYTE_REF(addr) (*((volatile char*)addr)) +#define HALFWORD_REF(addr) (*((volatile short*)addr)) +#define WORD_REF(addr) (*((volatile long*)addr)) + +#define UART_THR_LO HALFWORD_REF(UART_THR) +#define UART_RBR_LO HALFWORD_REF(UART_RBR) +#define UART_DLL_LO HALFWORD_REF(UART_DLL) +#define UART_IER_LO HALFWORD_REF(UART_IER) +#define UART_IER_ERBFI 0x01 +#define UART_IER_ETBEI 0x02 +#define UART_IER_ELSI 0x04 +#define UART_IER_EDDSI 0x08 + +#define UART_DLH_LO HALFWORD_REF(UART_DLH) +#define UART_IIR_LO HALFWORD_REF(UART_IIR) +#define UART_IIR_NOINT 0x01 +#define UART_IIR_STATUS 0x06 +#define UART_IIR_LSR 0x06 +#define UART_IIR_RBR 0x04 +#define UART_IIR_THR 0x02 +#define UART_IIR_MSR 0x00 + +#define UART_LCR_LO HALFWORD_REF(UART_LCR) +#define UART_LCR_WLS5 0 +#define UART_LCR_WLS6 0x01 +#define UART_LCR_WLS7 0x02 +#define UART_LCR_WLS8 0x03 +#define UART_LCR_STB 0x04 +#define UART_LCR_PEN 0x08 +#define UART_LCR_EPS 0x10 +#define UART_LCR_SP 0x20 +#define UART_LCR_SB 0x40 +#define UART_LCR_DLAB 0x80 + +#define UART_MCR_LO HALFWORD_REF(UART_MCR) + +#define UART_LSR_LO HALFWORD_REF(UART_LSR) +#define UART_LSR_DR 0x01 +#define UART_LSR_OE 0x02 +#define UART_LSR_PE 0x04 +#define UART_LSR_FE 0x08 +#define UART_LSR_BI 0x10 +#define UART_LSR_THRE 0x20 +#define UART_LSR_TEMT 0x40 + +#define UART_MSR_LO HALFWORD_REF(UART_MSR) +#define UART_SCR_LO HALFWORD_REF(UART_SCR) +#define UART_GCTL_LO HALFWORD_REF(UART_GCTL) +#define UART_GCTL_UCEN 0x01 + +#endif diff --git a/include/asm-blackfin/cpu/cdefBF531.h b/include/asm-blackfin/cpu/cdefBF531.h new file mode 100644 index 000000000..68d841d18 --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF531.h @@ -0,0 +1,24 @@ +/* + * cdefBF531.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEFBF531_H +#define _CDEFBF531_H + +#include + +#endif /* _CDEFBF531_H */ diff --git a/include/asm-blackfin/cpu/cdefBF532.h b/include/asm-blackfin/cpu/cdefBF532.h new file mode 100644 index 000000000..a4d422f76 --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF532.h @@ -0,0 +1,398 @@ +/* + * cdefBF532.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEF_BF532_H +#define _CDEF_BF532_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning cdefBF532.h should only be included for 532 compatible chips. + * #endif + */ + +/* include all Core registers and bit definitions */ +#include + +/* include core specific register pointer definitions */ +#include + +/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */ +#define pPLL_CTL ((volatile unsigned short *)PLL_CTL) +#define pPLL_STAT ((volatile unsigned short *)PLL_STAT) +#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT) +#define pCHIPID ((volatile unsigned long *)CHIPID) +#define pSWRST ((volatile unsigned short *)SWRST) +#define pSYSCR ((volatile unsigned short *)SYSCR) +#define pPLL_DIV ((volatile unsigned short *)PLL_DIV) +#define pVR_CTL ((volatile unsigned short *)VR_CTL) + +/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ +#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0) +#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1) +#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2) +#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3) +#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK) +#define pSIC_ISR ((volatile unsigned long *)SIC_ISR) +#define pSIC_IWR ((volatile unsigned long *)SIC_IWR) + +/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */ +#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL) +#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT) +#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT) + +/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */ +#define pRTC_STAT ((volatile unsigned long *)RTC_STAT) +#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL) +#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT) +#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT) +#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM) +#define pRTC_FAST ((volatile unsigned short *)RTC_FAST) +#define pRTC_PREN ((volatile unsigned short *)RTC_PREN) + +/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ +#define pFIO_DIR ((volatile unsigned short *)FIO_DIR) +#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C) +#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S) +#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C) +#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S) +#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C) +#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S) +#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR) +#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE) +#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH) +#define pFIO_INEN ((volatile unsigned short *)FIO_INEN) +#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D) +#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T) +#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D) +#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T) +#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D) +#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T) + +/* DMA Test Registers */ +#define pDMA_CCOMP ((volatile unsigned long *)DMA_CCOMP) +#define pDMA_ACOMP ((volatile unsigned long *)DMA_ACOMP) +#define pDMA_MISR ((volatile unsigned long *)DMA_MISR) +#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER) +#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT) +#define pDMA_TMODE ((volatile unsigned short *)DMA_TMODE) +#define pDMA_TMCHAN ((volatile unsigned short *)DMA_TMCHAN) +#define pDMA_TMSTAT ((volatile unsigned short *)DMA_TMSTAT) +#define pDMA_TMBD ((volatile unsigned short *)DMA_TMBD) +#define pDMA_TMM0D ((volatile unsigned short *)DMA_TMM0D) +#define pDMA_TMM1D ((volatile unsigned short *)DMA_TMM1D) +#define pDMA_TMMA ((volatile void **)DMA_TMMA) + +/* DMA Controller */ +#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG) +#define pDMA0_NEXT_DESC_PTR ((volatile void **)DMA0_NEXT_DESC_PTR) +#define pDMA0_START_ADDR ((volatile void **)DMA0_START_ADDR) +#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT) +#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT) +#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY) +#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY) +#define pDMA0_CURR_DESC_PTR ((volatile void **)DMA0_CURR_DESC_PTR) +#define pDMA0_CURR_ADDR ((volatile void **)DMA0_CURR_ADDR) +#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT) +#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT) +#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS) +#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP) + +#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG) +#define pDMA1_NEXT_DESC_PTR ((volatile void **)DMA1_NEXT_DESC_PTR) +#define pDMA1_START_ADDR ((volatile void **)DMA1_START_ADDR) +#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT) +#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT) +#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY) +#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY) +#define pDMA1_CURR_DESC_PTR ((volatile void **)DMA1_CURR_DESC_PTR) +#define pDMA1_CURR_ADDR ((volatile void **)DMA1_CURR_ADDR) +#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT) +#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT) +#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS) +#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP) + +#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG) +#define pDMA2_NEXT_DESC_PTR ((volatile void **)DMA2_NEXT_DESC_PTR) +#define pDMA2_START_ADDR ((volatile void **)DMA2_START_ADDR) +#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT) +#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT) +#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY) +#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY) +#define pDMA2_CURR_DESC_PTR ((volatile void **)DMA2_CURR_DESC_PTR) +#define pDMA2_CURR_ADDR ((volatile void **)DMA2_CURR_ADDR) +#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT) +#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT) +#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS) +#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP) + +#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG) +#define pDMA3_NEXT_DESC_PTR ((volatile void **)DMA3_NEXT_DESC_PTR) +#define pDMA3_START_ADDR ((volatile void **)DMA3_START_ADDR) +#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT) +#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT) +#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY) +#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY) +#define pDMA3_CURR_DESC_PTR ((volatile void **)DMA3_CURR_DESC_PTR) +#define pDMA3_CURR_ADDR ((volatile void **)DMA3_CURR_ADDR) +#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT) +#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT) +#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS) +#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP) + +#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG) +#define pDMA4_NEXT_DESC_PTR ((volatile void **)DMA4_NEXT_DESC_PTR) +#define pDMA4_START_ADDR ((volatile void **)DMA4_START_ADDR) +#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT) +#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT) +#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY) +#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY) +#define pDMA4_CURR_DESC_PTR ((volatile void **)DMA4_CURR_DESC_PTR) +#define pDMA4_CURR_ADDR ((volatile void **)DMA4_CURR_ADDR) +#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT) +#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT) +#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS) +#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP) + +#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG) +#define pDMA5_NEXT_DESC_PTR ((volatile void **)DMA5_NEXT_DESC_PTR) +#define pDMA5_START_ADDR ((volatile void **)DMA5_START_ADDR) +#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT) +#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT) +#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY) +#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY) +#define pDMA5_CURR_DESC_PTR ((volatile void **)DMA5_CURR_DESC_PTR) +#define pDMA5_CURR_ADDR ((volatile void **)DMA5_CURR_ADDR) +#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT) +#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT) +#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS) +#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP) + +#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG) +#define pDMA6_NEXT_DESC_PTR ((volatile void **)DMA6_NEXT_DESC_PTR) +#define pDMA6_START_ADDR ((volatile void **)DMA6_START_ADDR) +#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT) +#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT) +#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY) +#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY) +#define pDMA6_CURR_DESC_PTR ((volatile void **)DMA6_CURR_DESC_PTR) +#define pDMA6_CURR_ADDR ((volatile void **)DMA6_CURR_ADDR) +#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT) +#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT) +#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS) +#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP) + +#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG) +#define pDMA7_NEXT_DESC_PTR ((volatile void **)DMA7_NEXT_DESC_PTR) +#define pDMA7_START_ADDR ((volatile void **)DMA7_START_ADDR) +#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT) +#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT) +#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY) +#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY) +#define pDMA7_CURR_DESC_PTR ((volatile void **)DMA7_CURR_DESC_PTR) +#define pDMA7_CURR_ADDR ((volatile void **)DMA7_CURR_ADDR) +#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT) +#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT) +#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS) +#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP) + +#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG) +#define pMDMA_D1_NEXT_DESC_PTR ((volatile void **)MDMA_D1_NEXT_DESC_PTR) +#define pMDMA_D1_START_ADDR ((volatile void **)MDMA_D1_START_ADDR) +#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT) +#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT) +#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY) +#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY) +#define pMDMA_D1_CURR_DESC_PTR ((volatile void **)MDMA_D1_CURR_DESC_PTR) +#define pMDMA_D1_CURR_ADDR ((volatile void **)MDMA_D1_CURR_ADDR) +#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT) +#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT) +#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS) +#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP) + +#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG) +#define pMDMA_S1_NEXT_DESC_PTR ((volatile void **)MDMA_S1_NEXT_DESC_PTR) +#define pMDMA_S1_START_ADDR ((volatile void **)MDMA_S1_START_ADDR) +#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT) +#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT) +#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY) +#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY) +#define pMDMA_S1_CURR_DESC_PTR ((volatile void **)MDMA_S1_CURR_DESC_PTR) +#define pMDMA_S1_CURR_ADDR ((volatile void **)MDMA_S1_CURR_ADDR) +#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT) +#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT) +#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS) +#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP) + +#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG) +#define pMDMA_D0_NEXT_DESC_PTR ((volatile void **)MDMA_D0_NEXT_DESC_PTR) +#define pMDMA_D0_START_ADDR ((volatile void **)MDMA_D0_START_ADDR) +#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT) +#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT) +#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY) +#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY) +#define pMDMA_D0_CURR_DESC_PTR ((volatile void **)MDMA_D0_CURR_DESC_PTR) +#define pMDMA_D0_CURR_ADDR ((volatile void **)MDMA_D0_CURR_ADDR) +#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT) +#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT) +#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS) +#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP) + +#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG) +#define pMDMA_S0_NEXT_DESC_PTR ((volatile void **)MDMA_S0_NEXT_DESC_PTR) +#define pMDMA_S0_START_ADDR ((volatile void **)MDMA_S0_START_ADDR) +#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT) +#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT) +#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY) +#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY) +#define pMDMA_S0_CURR_DESC_PTR ((volatile void **)MDMA_S0_CURR_DESC_PTR) +#define pMDMA_S0_CURR_ADDR ((volatile void **)MDMA_S0_CURR_ADDR) +#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT) +#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT) +#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS) +#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP) + +/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */ +#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL) +#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0) +#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1) + +/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */ +/* #define L1SBAR 0xFFC04840 */ /* L1 SRAM Base Address Register */ +/* #define L1CSR 0xFFC04844 */ /* L1 SRAM Control Initialization Register */ + +/* + * #define pDB_ACOMP ((volatile void **)DB_ACOMP) + * #define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP) + */ + +/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */ +#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL) +#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC) +#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT) +#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL) + +/* UART Controller */ +#define pUART_THR ((volatile unsigned short *)UART_THR) +#define pUART_RBR ((volatile unsigned short *)UART_RBR) +#define pUART_DLL ((volatile unsigned short *)UART_DLL) +#define pUART_IER ((volatile unsigned short *)UART_IER) +#define pUART_DLH ((volatile unsigned short *)UART_DLH) +#define pUART_IIR ((volatile unsigned short *)UART_IIR) +#define pUART_LCR ((volatile unsigned short *)UART_LCR) +#define pUART_MCR ((volatile unsigned short *)UART_MCR) +#define pUART_LSR ((volatile unsigned short *)UART_LSR) + +/* + * #define UART_MSR + */ +#define pUART_SCR ((volatile unsigned short *)UART_SCR) +#define pUART_GCTL ((volatile unsigned short *)UART_GCTL) + +/* SPI Controller */ +#define pSPI_CTL ((volatile unsigned short *)SPI_CTL) +#define pSPI_FLG ((volatile unsigned short *)SPI_FLG) +#define pSPI_STAT ((volatile unsigned short *)SPI_STAT) +#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR) +#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR) +#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD) +#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW) + +/* TIMER 0, 1, 2 Registers */ +#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG) +#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER) +#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD) +#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH) + +#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG) +#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER) +#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD) +#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH) + +#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG) +#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER) +#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD) +#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH) + +#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE) +#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE) +#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS) + +/* SPORT0 Controller */ +#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1) +#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2) +#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV) +#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV) +#define pSPORT0_TX ((volatile long *)SPORT0_TX) +#define pSPORT0_RX ((volatile long *)SPORT0_RX) +#define pSPORT0_TX32 ((volatile long *)SPORT0_TX) +#define pSPORT0_RX32 ((volatile long *)SPORT0_RX) +#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX) +#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX) +#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1) +#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2) +#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV) +#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV) +#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT) +#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL) +#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1) +#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2) +#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0) +#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1) +#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2) +#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3) +#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0) +#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1) +#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2) +#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3) + +/* SPORT1 Controller */ +#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1) +#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2) +#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV) +#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV) +#define pSPORT1_TX ((volatile long *)SPORT1_TX) +#define pSPORT1_RX ((volatile long *)SPORT1_RX) +#define pSPORT1_TX32 ((volatile long *)SPORT1_TX) +#define pSPORT1_RX32 ((volatile long *)SPORT1_RX) +#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX) +#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX) +#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1) +#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2) +#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV) +#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV) +#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT) +#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL) +#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1) +#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2) +#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0) +#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1) +#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2) +#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3) +#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0) +#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1) +#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2) +#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3) + +/* Parallel Peripheral Interface (PPI) */ +#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL) +#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS) +#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY) +#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT) +#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME) + +#endif /* _CDEF_BF532_H */ diff --git a/include/asm-blackfin/cpu/cdefBF533.h b/include/asm-blackfin/cpu/cdefBF533.h new file mode 100644 index 000000000..8c751e607 --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF533.h @@ -0,0 +1,24 @@ +/* + * cdefBF533.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEFBF533_H +#define _CDEFBF533_H + +#include + +#endif /* _CDEFBF533_H */ diff --git a/include/asm-blackfin/cpu/cdefBF53x.h b/include/asm-blackfin/cpu/cdefBF53x.h new file mode 100644 index 000000000..db4eaa9cf --- /dev/null +++ b/include/asm-blackfin/cpu/cdefBF53x.h @@ -0,0 +1,32 @@ +/************************************************************************ + * + * cdefBF53x.h + * + * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. + * + ************************************************************************/ + +#ifndef _CDEFBF53x_H +#define _CDEFBF53x_H + +#if defined(__ADSPBF531__) + #include +#elif defined(__ADSPBF532__) + #include +#elif defined(__ADSPBF533__) + #include +#elif defined(__ADSPBF561__) + #include +#elif defined(__ADSPBF535__) + #include +#elif defined(__AD6532__) + #include +#else + #if defined(__ADSPLPBLACKFIN__) + #include + #else + #include + #endif +#endif + +#endif /* _CDEFBF53x_H */ diff --git a/include/asm-blackfin/cpu/cdef_LPBlackfin.h b/include/asm-blackfin/cpu/cdef_LPBlackfin.h new file mode 100644 index 000000000..e6471cbcb --- /dev/null +++ b/include/asm-blackfin/cpu/cdef_LPBlackfin.h @@ -0,0 +1,185 @@ +/* + * cdef_LPBlackfin.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _CDEF_LPBLACKFIN_H +#define _CDEF_LPBLACKFIN_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning cdef_LPBlackfin.h should only be included for 532 compatible chips. + * #endif + */ +#include + +/* Cache & SRAM Memory */ +#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS) +#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL) +#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS) +#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR) + +/* #define MMR_TIMEOUT 0xFFE00010 */ /* Memory-Mapped Register Timeout Register */ +#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0) +#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1) +#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2) +#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3) +#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4) +#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5) +#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6) +#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7) +#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8) +#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9) +#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10) +#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11) +#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12) +#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13) +#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14) +#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15) +#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0) +#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1) +#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2) +#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3) +#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4) +#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5) +#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6) +#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7) +#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8) +#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9) +#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10) +#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11) +#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12) +#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13) +#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14) +#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15) +#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND) + +/* #define DTEST_INDEX 0xFFE00304 */ /* Data Test Index Register */ +#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0) +#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1) + +/* + * # define DTEST_DATA2 0xFFE00408 Data Test Data Register + * #define DTEST_DATA3 0xFFE0040C Data Test Data Register + */ +#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL) +#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS) +#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR) +#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0) +#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1) +#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2) +#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3) +#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4) +#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5) +#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6) +#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7) +#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8) +#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9) +#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10) +#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11) +#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12) +#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13) +#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14) +#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15) +#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0) +#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1) +#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2) +#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3) +#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4) +#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5) +#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6) +#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7) +#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8) +#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9) +#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10) +#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11) +#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12) +#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13) +#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14) +#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15) +#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND) + +/* #define ITEST_INDEX 0xFFE01304 */ /* Instruction Test Index Register */ +#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0) +#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1) + +/* Event/Interrupt Registers */ +#define pEVT0 ((volatile void **)EVT0) +#define pEVT1 ((volatile void **)EVT1) +#define pEVT2 ((volatile void **)EVT2) +#define pEVT3 ((volatile void **)EVT3) +#define pEVT4 ((volatile void **)EVT4) +#define pEVT5 ((volatile void **)EVT5) +#define pEVT6 ((volatile void **)EVT6) +#define pEVT7 ((volatile void **)EVT7) +#define pEVT8 ((volatile void **)EVT8) +#define pEVT9 ((volatile void **)EVT9) +#define pEVT10 ((volatile void **)EVT10) +#define pEVT11 ((volatile void **)EVT11) +#define pEVT12 ((volatile void **)EVT12) +#define pEVT13 ((volatile void **)EVT13) +#define pEVT14 ((volatile void **)EVT14) +#define pEVT15 ((volatile void **)EVT15) +#define pIMASK ((volatile unsigned long *)IMASK) +#define pIPEND ((volatile unsigned long *)IPEND) +#define pILAT ((volatile unsigned long *)ILAT) + +/* Core Timer Registers */ +#define pTCNTL ((volatile unsigned long *)TCNTL) +#define pTPERIOD ((volatile unsigned long *)TPERIOD) +#define pTSCALE ((volatile unsigned long *)TSCALE) +#define pTCOUNT ((volatile unsigned long *)TCOUNT) + +/* Debug/MP/Emulation Registers */ +#define pDSPID ((volatile unsigned long *)DSPID) +#define pDBGCTL ((volatile unsigned long *)DBGCTL) +#define pDBGSTAT ((volatile unsigned long *)DBGSTAT) +#define pEMUDAT ((volatile unsigned long *)EMUDAT) + +/* Trace Buffer Registers */ +#define pTBUFCTL ((volatile unsigned long *)TBUFCTL) +#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT) +#define pTBUF ((volatile void **)TBUF) + +/* Watch Point Control Registers */ +#define pWPIACTL ((volatile unsigned long *)WPIACTL) +#define pWPIA0 ((volatile void **)WPIA0) +#define pWPIA1 ((volatile void **)WPIA1) +#define pWPIA2 ((volatile void **)WPIA2) +#define pWPIA3 ((volatile void **)WPIA3) +#define pWPIA4 ((volatile void **)WPIA4) +#define pWPIA5 ((volatile void **)WPIA5) +#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0) +#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1) +#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2) +#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3) +#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4) +#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5) +#define pWPDACTL ((volatile unsigned long *)WPDACTL) +#define pWPDA0 ((volatile void **)WPDA0) +#define pWPDA1 ((volatile void **)WPDA1) +#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0) +#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1) +#define pWPSTAT ((volatile unsigned long *)WPSTAT) + +/* Performance Monitor Registers */ +#define pPFCTL ((volatile unsigned long *)PFCTL) +#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0) +#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1) + +/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */ + +#endif /* _CDEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/cpu/defBF531.h b/include/asm-blackfin/cpu/defBF531.h new file mode 100644 index 000000000..6c7cd5a6d --- /dev/null +++ b/include/asm-blackfin/cpu/defBF531.h @@ -0,0 +1,24 @@ +/* + * defBF531.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEFBF531_H +#define _DEFBF531_H + +#include + +#endif /* _DEFBF531_H */ diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h new file mode 100644 index 000000000..26a5fe644 --- /dev/null +++ b/include/asm-blackfin/cpu/defBF532.h @@ -0,0 +1,1159 @@ +/* + * defBF532.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ + +#ifndef _DEF_BF532_H +#define _DEF_BF532_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning defBF532.h should only be included for 532 compatible chips + * #endif + */ + +/* include all Core registers and bit definitions */ +#include + +/* Helper macros + * usage: + * P0.H = HI(UART_THR); + * P0.L = LO(UART_THR); + */ + +#define LO(con32) ((con32) & 0xFFFF) +#define lo(con32) ((con32) & 0xFFFF) +#define HI(con32) (((con32) >> 16) & 0xFFFF) +#define hi(con32) (((con32) >> 16) & 0xFFFF) + +/* + * System MMR Register Map + */ + +/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ +#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ +#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ +#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */ +#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ +#define SYSCR 0xFFC00104 /* System Configuration register */ + +/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ + +/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ + +/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ + +/* UART Controller (0xFFC00400 - 0xFFC004FF) */ +#define UART_THR 0xFFC00400 /* Transmit Holding register */ +#define UART_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART_LCR 0xFFC0040C /* Line Control Register */ +#define UART_MCR 0xFFC00410 /* Modem Control Register */ +#define UART_LSR 0xFFC00414 /* Line Status Register */ +/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */ +#define UART_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART_GCTL 0xFFC00424 /* Global Control Register */ + +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define SPI_CTL 0xFFC00500 /* SPI Control Register */ +#define SPI_FLG 0xFFC00504 /* SPI Flag register */ +#define SPI_STAT 0xFFC00508 /* SPI Status register */ +#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ +#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ +#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ +#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ + +/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ + +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ + +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ + +#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ +#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ +#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ +#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ +#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ +#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ +#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ +#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ +#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ +#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ +#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ +#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ +#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ +#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ +#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ +#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ +#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ +#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ + +/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ + +/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ + +/* Asynchronous Memory Controller - External Bus Interface Unit */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ + +/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ + +/* DMA Test Registers */ +#define DMA_CCOMP 0xFFC00B04 /* DMA Cycle Count Register */ +#define DMA_ACOMP 0xFFC00B00 /* Debug Compare Address Register */ +#define DMA_MISR 0xFFC00B08 /* MISR Register */ +#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ +#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ +#define DMA_TMODE 0xFFC00B14 /* DMA Test Modes Register */ +#define DMA_TMCHAN 0xFFC00B18 /* DMA Testmode Selected Channel Register */ +#define DMA_TMSTAT 0xFFC00B1C /* DMA Testmode Channel Status Register */ +#define DMA_TMBD 0xFFC00B20 /* DMA Testmode DAB Bus Data Register */ +#define DMA_TMM0D 0xFFC00B24 /* DMA Testmode Mem0 Data Register */ +#define DMA_TMM1D 0xFFC00B28 /* DMA Testmode Mem1 Data Register */ +#define DMA_TMMA 0xFFC00B2C /* DMA Testmode Memory Address Register */ + +/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ + +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ + +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ + +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ + +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ + +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ + +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ + +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ + +#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ + +#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ + +#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ + +#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ + +/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ + +/* + * System MMR Register Bits + */ +/* + * PLL AND RESET MASKS + */ + +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ +#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ +#define STOPCK_OFF 0x00000008 /* Core clock off */ +#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ +#define BYPASS 0x00000100 /* Bypass the PLL */ + +/* PLL_DIV Masks */ +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ + +/* SWRST Mask */ +#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ + +/* + * SYSTEM INTERRUPT CONTROLLER MASKS + */ + +/* SIC_IAR0 Masks */ +#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ +#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ +#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ +#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ +#define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ +#define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ +#define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ +#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ + +/* SIC_IAR1 Masks */ +#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ +#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ +#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ +#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ +#define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ +#define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ +#define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ +#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ + +/* SIC_IAR2 Masks */ +#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ +#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ +#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ +#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ +#define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ +#define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ +#define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ +#define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ + +/* SIC_IMASK Masks */ +#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ +#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ +#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ +#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ + +/* SIC_IWR Masks */ +#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ +#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ +#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ +#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ + +/* + * WATCHDOG TIMER MASKS + */ +/* Watchdog Timer WDOG_CTL Register */ +#define ICTL(x) ((x<<1) & 0x0006) +#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */ +#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */ +#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */ +#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */ + +#define TMR_EN 0x0000 +#define TMR_DIS 0x0AD0 +#define TRO 0x8000 + +#define ICTL_P0 0x01 +#define ICTL_P1 0x02 +#define TRO_P 0x0F + +/* RTC_STAT and RTC_ALARM register */ +#define RTSEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTHR 0x0001F000 /* Real-Time Clock Hours */ +#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* RTC_ICTL register */ +#define SWIE 0x0001 /* Stopwatch Interrupt Enable */ +#define AIE 0x0002 /* Alarm Interrupt Enable */ +#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MIE 0x0008 /* Minutes Interrupt Enable */ +#define HIE 0x0010 /* Hours Interrupt Enable */ +#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WCIE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_ISTAT register */ +#define SWEF 0x0001 /* Stopwatch Event Flag */ +#define AEF 0x0002 /* Alarm Event Flag */ +#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */ +#define MEF 0x0008 /* Minutes Event Flag */ +#define HEF 0x0010 /* Hours Event Flag */ +#define DEF 0x0020 /* 24 Hours (Days) Event Flag */ +#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */ +#define WPS 0x4000 /* Write Pending Status (RO) */ +#define WCOM 0x8000 /* Write Complete */ + +/* RTC_FAST Mask (RTC_PREN Mask) */ +#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */ +#define PREN 0x00000001 /* ** Must be set after power-up for proper operation of RTC */ + +/* + * UART CONTROLLER MASKS + */ + +/* UART_LCR Register */ +#define DLAB 0x80 +#define SB 0x40 +#define STP 0x20 +#define EPS 0x10 +#define PEN 0x08 +#define STB 0x04 +#define WLS(x) ((x-5) & 0x03) + +#define DLAB_P 0x07 +#define SB_P 0x06 +#define STP_P 0x05 +#define EPS_P 0x04 +#define PEN_P 0x03 +#define STB_P 0x02 +#define WLS_P1 0x01 +#define WLS_P0 0x00 + +/* UART_MCR Register */ +#define LOOP_ENA 0x10 +#define LOOP_ENA_P 0x04 + +/* UART_LSR Register */ +#define TEMT 0x40 +#define THRE 0x20 +#define BI 0x10 +#define FE 0x08 +#define PE 0x04 +#define OE 0x02 +#define DR 0x01 + +#define TEMP_P 0x06 +#define THRE_P 0x05 +#define BI_P 0x04 +#define FE_P 0x03 +#define PE_P 0x02 +#define OE_P 0x01 +#define DR_P 0x00 + +/* UART_IER Register */ +#define ELSI 0x04 +#define ETBEI 0x02 +#define ERBFI 0x01 + +#define ELSI_P 0x02 +#define ETBEI_P 0x01 +#define ERBFI_P 0x00 + +/* UART_IIR Register */ +#define STATUS(x) ((x << 1) & 0x06) +#define NINT 0x01 +#define STATUS_P1 0x02 +#define STATUS_P0 0x01 +#define NINT_P 0x00 + +/* UART_GCTL Register */ +#define FFE 0x20 +#define FPE 0x10 +#define RPOLC 0x08 +#define TPOLC 0x04 +#define IREN 0x02 +#define UCEN 0x01 + +#define FFE_P 0x05 +#define FPE_P 0x04 +#define RPOLC_P 0x03 +#define TPOLC_P 0x02 +#define IREN_P 0x01 +#define UCEN_P 0x00 + +/* + * SERIAL PORT MASKS + */ +/* SPORTx_TCR1 Masks */ +#define TSPEN 0x0001 /* TX enable */ +#define ITCLK 0x0002 /* Internal TX Clock Select */ +#define TDTYPE 0x000C /* TX Data Formatting Select */ +#define TLSBIT 0x0010 /* TX Bit Order */ +#define ITFS 0x0200 /* Internal TX Frame Sync Select */ +#define TFSR 0x0400 /* TX Frame Sync Required Select */ +#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ +#define LTFS 0x1000 /* Low TX Frame Sync Select */ +#define LATFS 0x2000 /* Late TX Frame Sync Select */ +#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ + +/* SPORTx_TCR2 Masks */ +#define SLEN 0x001F /*TX Word Length */ +#define TXSE 0x0100 /*TX Secondary Enable */ +#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ +#define TRFST 0x0400 /*TX Right-First Data Order */ + +/* SPORTx_RCR1 Masks */ +#define RSPEN 0x0001 /* RX enable */ +#define IRCLK 0x0002 /* Internal RX Clock Select */ +#define RDTYPE 0x000C /* RX Data Formatting Select */ +#define RULAW 0x0008 /* u-Law enable */ +#define RALAW 0x000C /* A-Law enable */ +#define RLSBIT 0x0010 /* RX Bit Order */ +#define IRFS 0x0200 /* Internal RX Frame Sync Select */ +#define RFSR 0x0400 /* RX Frame Sync Required Select */ +#define LRFS 0x1000 /* Low RX Frame Sync Select */ +#define LARFS 0x2000 /* Late RX Frame Sync Select */ +#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ + +/* SPORTx_RCR2 Masks */ +#define SLEN 0x001F /* RX Word Length */ +#define RXSE 0x0100 /* RX Secondary Enable */ +#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ +#define RRFST 0x0400 /* Right-First Data Order */ + +/* SPORTx_STAT Masks */ +#define RXNE 0x0001 /* RX FIFO Not Empty Status */ +#define RUVF 0x0002 /* RX Underflow Status */ +#define ROVF 0x0004 /* RX Overflow Status */ +#define TXF 0x0008 /* TX FIFO Full Status */ +#define TUVF 0x0010 /* TX Underflow Status */ +#define TOVF 0x0020 /* TX Overflow Status */ +#define TXHRE 0x0040 /* TX Hold Register Empty */ + +/* SPORTx_MCMC1 Masks */ +#define WSIZE 0x0000F000 /* Multichannel Window Size Field */ +#define WOFF 0x000003FF /* /Multichannel Window Offset Field */ + +/* SPORTx_MCMC2 Masks */ +#define MCCRM 0x00000003 /* Multichannel Clock Recovery Mode */ +#define MCDTXPE 0x00000004 /* Multichannel DMA Transmit Packing */ +#define MCDRXPE 0x00000008 /* Multichannel DMA Receive Packing */ +#define MCMEN 0x00000010 /* Multichannel Frame Mode Enable */ +#define FSDR 0x00000080 /* Multichannel Frame Sync to Data Relationship */ +#define MFD 0x0000F000 /* Multichannel Frame Delay */ + +/* + * PARALLEL PERIPHERAL INTERFACE (PPI) MASKS + */ + +/* PPI_CONTROL Masks */ +#define PORT_EN 0x00000001 /* PPI Port Enable */ +#define PORT_DIR 0x00000002 /* PPI Port Direction */ +#define XFR_TYPE 0x0000000C /* PPI Transfer Type */ +#define PORT_CFG 0x00000030 /* PPI Port Configuration */ +#define FLD_SEL 0x00000040 /* PPI Active Field Select */ +#define PACK_EN 0x00000080 /* PPI Packing Mode */ +#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ +#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ +#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ +#define DLENGTH 0x00003800 /* PPI Data Length */ +#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ +#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ +#define POL 0x0000C000 /* PPI Signal Polarities */ + +/* PPI_STATUS Masks */ +#define FLD 0x00000400 /* Field Indicator */ +#define FT_ERR 0x00000800 /* Frame Track Error */ +#define OVR 0x00001000 /* FIFO Overflow Error */ +#define UNDR 0x00002000 /* FIFO Underrun Error */ +#define ERR_DET 0x00004000 /* Error Detected Indicator */ +#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ + +/* + * DMA CONTROLLER MASKS + */ + +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x00000001 /* Channel Enable */ +#define WNR 0x00000002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ +#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ +#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ +#define DMA2D 0x00000010 /* 2D/1D* Mode */ +#define RESTART 0x00000020 /* Restart */ +#define DI_SEL 0x00000040 /* Data Interrupt Select */ +#define DI_EN 0x00000080 /* Data Interrupt Enable */ +#define NDSIZE 0x00000900 /* Next Descriptor Size */ +#define FLOW 0x00007000 /* Flow Control */ + +#define DMAEN_P 0 /* Channel Enable */ +#define WNR_P 1 /* Channel Direction (W/R*) */ +#define DMA2D_P 4 /* 2D/1D* Mode */ +#define RESTART_P 5 /* Restart */ +#define DI_SEL_P 6 /* Data Interrupt Select */ +#define DI_EN_P 7 /* Data Interrupt Enable */ + +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x00000001 /* DMA Done Indicator */ +#define DMA_ERR 0x00000002 /* DMA Error Indicator */ +#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x00000008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0 /* DMA Done Indicator */ +#define DMA_ERR_P 1 /* DMA Error Indicator */ +#define DFETCH_P 2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 3 /* DMA Running Indicator */ + +/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ +#define CTYPE 0x00000040 /* DMA Channel Type Indicator */ +#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ +#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ +#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ +#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ +#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ +#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ +#define PMAP 0x00007000 /* DMA Peripheral Map Field */ + +/* + * GENERAL PURPOSE TIMER MASKS + */ + +/* PWM Timer bit definitions */ + +/* TIMER_ENABLE Register */ +#define TIMEN0 0x0001 +#define TIMEN1 0x0002 +#define TIMEN2 0x0004 + +#define TIMEN0_P 0x00 +#define TIMEN1_P 0x01 +#define TIMEN2_P 0x02 + +/* TIMER_DISABLE Register */ +#define TIMDIS0 0x0001 +#define TIMDIS1 0x0002 +#define TIMDIS2 0x0004 + +#define TIMDIS0_P 0x00 +#define TIMDIS1_P 0x01 +#define TIMDIS2_P 0x02 + +/* TIMER_STATUS Register */ +#define TIMIL0 0x0001 +#define TIMIL1 0x0002 +#define TIMIL2 0x0004 +#define TOVL_ERR0 0x0010 +#define TOVL_ERR1 0x0020 +#define TOVL_ERR2 0x0040 +#define TRUN0 0x1000 +#define TRUN1 0x2000 +#define TRUN2 0x4000 + +#define TIMIL0_P 0x00 +#define TIMIL1_P 0x01 +#define TIMIL2_P 0x02 +#define TOVL_ERR0_P 0x04 +#define TOVL_ERR1_P 0x05 +#define TOVL_ERR2_P 0x06 +#define TRUN0_P 0x0C +#define TRUN1_P 0x0D +#define TRUN2_P 0x0E + +/* TIMERx_CONFIG Registers */ +#define PWM_OUT 0x0001 +#define WDTH_CAP 0x0002 +#define EXT_CLK 0x0003 +#define PULSE_HI 0x0004 +#define PERIOD_CNT 0x0008 +#define IRQ_ENA 0x0010 +#define TIN_SEL 0x0020 +#define OUT_DIS 0x0040 +#define CLK_SEL 0x0080 +#define TOGGLE_HI 0x0100 +#define EMU_RUN 0x0200 +#define ERR_TYP(x) ((x & 0x03) << 14) + +#define TMODE_P0 0x00 +#define TMODE_P1 0x01 +#define PULSE_HI_P 0x02 +#define PERIOD_CNT_P 0x03 +#define IRQ_ENA_P 0x04 +#define TIN_SEL_P 0x05 +#define OUT_DIS_P 0x06 +#define CLK_SEL_P 0x07 +#define TOGGLE_HI_P 0x08 +#define EMU_RUN_P 0x09 +#define ERR_TYP_P0 0x0E +#define ERR_TYP_P1 0x0F + +/* + * PROGRAMMABLE FLAG MASKS + */ + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ +#define PF0 0x0001 +#define PF1 0x0002 +#define PF2 0x0004 +#define PF3 0x0008 +#define PF4 0x0010 +#define PF5 0x0020 +#define PF6 0x0040 +#define PF7 0x0080 +#define PF8 0x0100 +#define PF9 0x0200 +#define PF10 0x0400 +#define PF11 0x0800 +#define PF12 0x1000 +#define PF13 0x2000 +#define PF14 0x4000 +#define PF15 0x8000 + +/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */ +#define PF0_P 0 +#define PF1_P 1 +#define PF2_P 2 +#define PF3_P 3 +#define PF4_P 4 +#define PF5_P 5 +#define PF6_P 6 +#define PF7_P 7 +#define PF8_P 8 +#define PF9_P 9 +#define PF10_P 10 +#define PF11_P 11 +#define PF12_P 12 +#define PF13_P 13 +#define PF14_P 14 +#define PF15_P 15 + +/* + * SERIAL PERIPHERAL INTERFACE (SPI) MASKS + */ + +/* SPI_CTL Masks */ +#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ +#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ +#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ +#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ +#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */ +#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */ +#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */ +#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */ +#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */ +#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */ +#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */ +#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */ + +/* SPI_FLG Masks */ +#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ +#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ + +/* SPI_FLG Bit Positions */ +#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ +#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ +#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ +#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ +#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ +#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ +#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ +#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ + +/* SPI_STAT Masks */ +#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */ +#define MODF 0x00000002 /* Set(=1)in a master device when some other device tries to become master */ +#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ +#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ +#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */ +#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ +#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ + +/* + * ASYNCHRONOUS MEMORY CONTROLLER MASKS + */ + +/* AMGCTL Masks */ +#define AMCKEN 0x00000001 /* Enable CLKOUT */ +#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ +#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ +#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ +#define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ + +/* AMGCTL Bit Positions */ +#define AMCKEN_P 0x00000000 /* Enable CLKOUT */ +#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ +#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ +#define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ + +/* AMBCTL0 Masks */ +#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ +#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ +#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ +#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ +#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ +#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ +#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ +#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ +#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ +#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ +#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ +#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ +#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ +#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ +#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ +#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ +#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ +#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ +#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ +#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ +#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ +#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ +#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ +#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ +#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ +#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ +#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ +#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ +#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ +#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ +#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ +#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ +#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ +#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ +#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ +#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ +#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ +#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ +#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ +#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ +#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ +#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ +#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ +#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ +#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ +#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ +#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ +#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ +#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ +#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ +#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ +#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ +#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ +#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ +#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ +#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ +#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ +#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ +#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ +#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ +#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ +#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ +#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ +#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ +#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ +#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ +#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ +#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ +#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ +#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ +#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ +#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ +#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ +#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ +#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ +#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ +#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ +#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ +#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ +#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ + +/* AMBCTL1 Masks */ +#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ +#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ +#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ +#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ +#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ +#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ +#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ +#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ +#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ +#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ +#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ +#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ +#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ +#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ +#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ +#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ +#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ +#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ +#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ +#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ +#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ +#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ +#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ +#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ +#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ +#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ +#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ +#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ +#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ +#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ +#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ +#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ +#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ +#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ +#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ +#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ +#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ +#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ +#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ +#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ +#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ +#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ +#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ +#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ +#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ +#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ +#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ +#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ +#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ +#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ +#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ +#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ +#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ +#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ +#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ +#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ +#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ +#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ +#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ +#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ +#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ +#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ +#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ +#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ +#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ +#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ +#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ +#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ +#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ +#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ +#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ +#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ +#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ +#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ +#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ +#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ +#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ +#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ +#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ +#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ + +/* + * SDRAM CONTROLLER MASKS + */ + +/* SDGCTL Masks */ +#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ +#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ +#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ +#define PFE 0x00000010 /* Enable SDRAM prefetch */ +#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ +#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ +#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ +#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ +#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ +#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ +#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ +#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ +#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ +#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ +#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ +#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ +#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ +#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ +#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ +#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ +#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ +#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ +#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ +#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ +#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ +#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ +#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ +#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ +#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ +#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ +#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ +#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ +#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ +#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ +#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ +#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ +#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ +#define PUPSD 0x00200000 /* Power-up start delay */ +#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ +#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ +#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ +#define EBUFE 0x02000000 /* Enable external buffering timing */ +#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ +#define EMREN 0x10000000 /* Extended mode register enable */ +#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ +#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ + +/* EBIU_SDBCTL Masks */ +#define EBE 0x00000001 /* Enable SDRAM external bank */ +#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ +#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ +#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ +#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ +#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ +#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ +#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ + +/* EBIU_SDSTAT Masks */ +#define SDCI 0x00000001 /* SDRAM controller is idle */ +#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ +#define SDPUA 0x00000004 /* SDRAM power up active */ +#define SDRS 0x00000008 /* SDRAM is in reset state */ +#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ +#define BGSTAT 0x00000020 /* Bus granted */ + +#endif /* _DEF_BF532_H */ diff --git a/include/asm-blackfin/cpu/defBF533.h b/include/asm-blackfin/cpu/defBF533.h new file mode 100644 index 000000000..90e50afa7 --- /dev/null +++ b/include/asm-blackfin/cpu/defBF533.h @@ -0,0 +1,24 @@ +/* + * defBF533.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEFBF533_H +#define _DEFBF533_H + +#include + +#endif /* _DEFBF533_H */ diff --git a/include/asm-blackfin/cpu/defBF533_extn.h b/include/asm-blackfin/cpu/defBF533_extn.h new file mode 100644 index 000000000..a9a1c7ccb --- /dev/null +++ b/include/asm-blackfin/cpu/defBF533_extn.h @@ -0,0 +1,76 @@ +/* + * defBF533_extn.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +#ifndef _DEF_BF533_EXTN_H +#define _DEF_BF533_EXTN_H + +#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */ +/* Delay inserted for PLL transition */ +#define DELAY 0x1000 + +#define L1_ISRAM 0xFFA00000 +#define L1_ISRAM_END 0xFFA10000 +#define DATA_BANKA_SRAM 0xFF800000 +#define DATA_BANKA_SRAM_END 0xFF808000 +#define DATA_BANKB_SRAM 0xFF900000 +#define DATA_BANKB_SRAM_END 0xFF908000 +#define SYSMMR_BASE 0xFFC00000 +#define WDSIZE16 0x00000004 + +/* Event Vector Table Address */ +#define EVT_EMULATION_ADDR 0xffe02000 +#define EVT_RESET_ADDR 0xffe02004 +#define EVT_NMI_ADDR 0xffe02008 +#define EVT_EXCEPTION_ADDR 0xffe0200c +#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010 +#define EVT_HARDWARE_ERROR_ADDR 0xffe02014 +#define EVT_TIMER_ADDR 0xffe02018 +#define EVT_IVG7_ADDR 0xffe0201c +#define EVT_IVG8_ADDR 0xffe02020 +#define EVT_IVG9_ADDR 0xffe02024 +#define EVT_IVG10_ADDR 0xffe02028 +#define EVT_IVG11_ADDR 0xffe0202c +#define EVT_IVG12_ADDR 0xffe02030 +#define EVT_IVG13_ADDR 0xffe02034 +#define EVT_IVG14_ADDR 0xffe02038 +#define EVT_IVG15_ADDR 0xffe0203c +#define EVT_OVERRIDE_ADDR 0xffe02100 + +/* IMASK Bit values */ +#define IVG15_POS 0x00008000 +#define IVG14_POS 0x00004000 +#define IVG13_POS 0x00002000 +#define IVG12_POS 0x00001000 +#define IVG11_POS 0x00000800 +#define IVG10_POS 0x00000400 +#define IVG9_POS 0x00000200 +#define IVG8_POS 0x00000100 +#define IVG7_POS 0x00000080 +#define IVGTMR_POS 0x00000040 +#define IVGHW_POS 0x00000020 + +#define WDOG_TMR_DISABLE (0xAD << 4) +#define ICTL_RST 0x00000000 +#define ICTL_NMI 0x00000002 +#define ICTL_GP 0x00000004 +#define ICTL_DISABLE 0x00000003 + +/* Watch Dog timer values setup */ +#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE + +#endif /* _DEF_BF533_EXTN_H */ diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h new file mode 100644 index 000000000..9ac78c836 --- /dev/null +++ b/include/asm-blackfin/cpu/def_LPBlackfin.h @@ -0,0 +1,445 @@ +/* + * def_LPBlackfin.h + * + * This file is subject to the terms and conditions of the GNU Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Non-GPL License also available as part of VisualDSP++ + * + * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html + * + * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved + * + * This file under source code control, please send bugs or changes to: + * dsptools.support@analog.com + * + */ + +/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */ + +#ifndef _DEF_LPBLACKFIN_H +#define _DEF_LPBLACKFIN_H + +/* + * #if !defined(__ADSPLPBLACKFIN__) + * #warning def_LPBlackfin.h should only be included for 532 compatible chips. + * #endif + */ + +#define MK_BMSK_( x ) (1<31 */ +#define TEST_WAY0 0x00000000 /* Access Way0 */ +#define TEST_WAY1 0x04000000 /* Access Way1 */ + +/* ** ITEST_COMMAND only */ +#define TEST_WAY2 0x08000000 /* Access Way2 */ +#define TEST_WAY3 0x0C000000 /* Access Way3 */ + +/* ** DTEST_COMMAND only */ +#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */ +#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */ + +#endif /* _DEF_LPBLACKFIN_H */ diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h new file mode 100644 index 000000000..108c2792a --- /dev/null +++ b/include/asm-blackfin/current.h @@ -0,0 +1,40 @@ +/* + * U-boot - current.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_CURRENT_H +#define _BLACKFIN_CURRENT_H +/* + * current.h + * (C) Copyright 2000, Lineo, David McCullough + * + * rather than dedicate a register (as the m68k source does), we + * just keep a global, we should probably just change it all to be + * current and lose _current_task. + */ + +extern struct task_struct *_current_task; +#define get_current() _current_task +#define current _current_task + +#endif diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h index ea0b3664e..dbb73887e 100644 --- a/include/asm-blackfin/delay.h +++ b/include/asm-blackfin/delay.h @@ -1,7 +1,7 @@ /* * U-boot - delay.h Routines for introducing delays * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _BLACKFIN_DELAY_H @@ -35,9 +35,9 @@ extern __inline__ void __delay(unsigned long loops) { __asm__ __volatile__("1:\t%0 += -1;\n\t" - "cc = %0 == 0;\n\t" - "if ! cc jump 1b;\n":"=d"(loops) - :"0"(loops)); + "cc = %0 == 0;\n\t" + "if ! cc jump 1b;\n":"=d"(loops) + :"0"(loops)); } /* diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h index ef74d686a..607a5b8e9 100644 --- a/include/asm-blackfin/entry.h +++ b/include/asm-blackfin/entry.h @@ -1,7 +1,7 @@ /* - * entry.h - routines for context saving and restoring (for interrupts/exceptions) + * U-boot - entry.h Routines for context saving and restoring * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,14 +18,44 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef __BLACKFIN_ENTRY_H #define __BLACKFIN_ENTRY_H + +#include +#include +#include + +/* + * Stack layout in 'ret_from_exception': + * + */ + +/* + * Register %p2 is now set to the current task throughout + * the whole kernel. + */ + #ifdef __ASSEMBLY__ +#define LFLUSH_I_AND_D 0x00000808 +#define LSIGTRAP 5 + +/* process bits for task_struct.flags */ +#define PF_TRACESYS_OFF 3 +#define PF_TRACESYS_BIT 5 +#define PF_PTRACED_OFF 3 +#define PF_PTRACED_BIT 4 +#define PF_DTRACE_OFF 1 +#define PF_DTRACE_BIT 5 + +#define NEW_PT_REGS + +#if defined(NEW_PT_REGS) + #define SAVE_ALL_INT save_context_no_interrupts #define SAVE_ALL_SYS save_context_no_interrupts #define SAVE_CONTEXT save_context_with_interrupts @@ -34,6 +64,16 @@ #define RESTORE_ALL_SYS restore_context_no_interrupts #define RESTORE_CONTEXT restore_context_with_interrupts +#else + +#define SAVE_ALL_INT save_all_int +#define SAVE_ALL_SYS save_all_sys +#define SAVE_CONTEXT save_context +#define RESTORE_ALL restore_context +#define RESTORE_CONTEXT restore_context + +#endif + /* * Code to save processor context. * We even save the register which are preserved by a function call @@ -245,5 +285,101 @@ sp += 4; .endm +#if !defined(NEW_PT_REGS) +/* + * a -1 in the orig_r0 field signifies + * that the stack frame is NOT for syscall + */ +.macro save_all_int +/* reserved and disable the single step of SYSCFG, by Steven Chen 03/07/10 */ + [--sp] = r0; + r0.l = 0x30; /* Errata for BF533 */ + r0.h = 0x0; + syscfg = r0; /* disable single step flag in SYSCFG */ + r0 = [sp++]; + [--sp] = syscfg; /* store SYSCFG */ + + [--sp] = r0; /* Reserved for IPEND */ + [--sp] = fp; + [--sp] = usp; + [--sp] = r0; + + [--sp] = r0; + r0 = [sp + 8]; + [--sp] = a0.x; + [--sp] = a1.x; + [--sp] = a0.w; + [--sp] = a1.w; + [--sp] = rets; + [--sp] = astat; + [--sp] = seqstat; + [--sp] = retx; /* current pc when exception happens */ + [--sp] = ( r7:5, p5:0 ); + [--sp] = r1; + [--sp] = r2; + [--sp] = r4; + [--sp] = r3; +.endm + +.macro save_all_sys + [--sp] = r0; + [--sp] = r0; + [--sp] = a0.x; + [--sp] = a1.x; + [--sp] = a0.w; + [--sp] = a1.w; + [--sp] = rets; + [--sp] = astat; + [--sp] = seqstat; + [--sp] = retx; /* current pc when exception happens */ + [--sp] = ( r7:5, p5:0 ); + [--sp] = r1; + [--sp] = r2; + [--sp] = r4; + [--sp] = r3; +.endm + +.macro restore_all + r3 = [sp++]; + r4 = [sp++]; + r2 = [sp++]; + r1 = [sp++]; + ( r7:5, p5:0 ) = [sp++]; + retx = [sp++]; + seqstat = [sp++]; + astat = [sp++]; + rets = [sp++]; + a1.w = [sp++]; + a0.w = [sp++]; + a1.x = [sp++]; + a0.x = [sp++]; + sp += 4; /* orig r0 */ + r0 = [sp++]; + + sp += 4; + fp = [sp++]; + sp +=4; /* Skip the IPEND */ + + syscfg = [sp++]; + +.endm + +#endif + +#define STR(X) STR1(X) +#define STR1(X) #X + +#if defined(NEW_PT_REGS) + +#define PT_OFF_ORIG_R0 208 +#define PT_OFF_SR 8 + +#else + +#define PT_OFF_ORIG_R0 0x54 +#define PT_OFF_SR 0x38 /* seqstat in pt_regs */ + #endif #endif + +#endif diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h index 0d2c61803..713bba0b2 100644 --- a/include/asm-blackfin/errno.h +++ b/include/asm-blackfin/errno.h @@ -1,7 +1,7 @@ /* * U-boot - errno.h Error number defines * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _BLACKFIN_ERRNO_H diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index b0b01e485..56a12f07b 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -1,7 +1,7 @@ /* * U-boot - global_data.h Declarations for global data of u-boot * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,13 +21,15 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include + /* * The following data structure is placed in some memory wich is * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or @@ -43,16 +45,11 @@ typedef struct global_data { unsigned long board_type; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ + unsigned long ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ - unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) - unsigned long post_log_word; /* Record POST activities */ - unsigned long post_init_f_time; /* When post_init_f started */ -#endif - - void **jt; /* jump table */ + void **jt; /* jump table */ } gd_t; /* @@ -61,10 +58,7 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ -#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5") +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P5") #endif diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h new file mode 100644 index 000000000..1ee050ec1 --- /dev/null +++ b/include/asm-blackfin/hw_irq.h @@ -0,0 +1,37 @@ +/* + * U-boot - hw_irq.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h + * BlackFin (ADI) assembler restricted values by Ted Ma + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#ifdef CONFIG_EZKIT533 +#include +#endif +#ifdef CONFIG_STAMP +#include +#endif diff --git a/include/asm-blackfin/io-kernel.h b/include/asm-blackfin/io-kernel.h new file mode 100644 index 000000000..0b0572ffa --- /dev/null +++ b/include/asm-blackfin/io-kernel.h @@ -0,0 +1,135 @@ +/* + * U-boot - io-kernel.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_IO_H +#define _BLACKFIN_IO_H + +#ifdef __KERNEL__ + +#include + +/* + * These are for ISA/PCI shared memory _only_ and should never be used + * on any other type of memory, including Zorro memory. They are meant to + * access the bus in the bus byte order which is little-endian!. + * + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the m68k architecture, we just read/write the + * memory location directly. + */ +/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates + * two accesses to memory, which may be undesireable for some devices. + */ +#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; }) +#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; }) +#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; }) +#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) +#define inb(addr) cf_inb((volatile unsigned char*)(addr)) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(x,addr) cf_outb((unsigned char)(x), (volatile unsigned char*)(addr)) +#define outw(x,addr) ((void) writew(x,addr)) +#define outl(x,addr) ((void) writel(x,addr)) +#define inb_p(addr) inb(addr) +#define inw_p(addr) inw(addr) +#define inl_p(addr) inl(addr) +#define outb_p(x,addr) outb(x,addr) +#define outw_p(x,addr) outw(x,addr) +#define outl_p(x,addr) outl(x,addr) +#define insb(port, addr, count) memcpy((void*)addr, (void*)port, count) +#define insw(port, addr, count) cf_insw((unsigned short*)addr, (unsigned short*)(port), (count)) +#define insl(port, addr, count) memcpy((void*)addr, (void*)port, (4*count)) +#define outsb(port, addr, count) memcpy((void*)port, (void*)addr, count) +#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count)) +#define outsl(port, addr, count) memcpy((void*)port, (void*)addr, (4*count)) +#define IO_SPACE_LIMIT 0xffff + +/* Values for nocacheflag and cmode */ +#define IOMAP_FULL_CACHING 0 +#define IOMAP_NOCACHE_SER 1 +#define IOMAP_NOCACHE_NONSER 2 +#define IOMAP_WRITETHROUGH 3 + +#ifndef __ASSEMBLY__ +extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); +extern void __iounmap(void *addr, unsigned long size); +extern inline void *ioremap(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); +} +extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_FULL_CACHING); +} + +extern void iounmap(void *addr); + +/* Nothing to do */ + +extern void blkfin_inv_cache_all(void); + +#endif + +#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) +#define dma_cache_wback(_start,_size) do { } while (0) +#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) + +/* Pages to physical address... */ +#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) +#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) + +#define mm_ptov(vaddr) ((void *) (vaddr)) +#define mm_vtop(vaddr) ((unsigned long) (vaddr)) +#define phys_to_virt(vaddr) ((void *) (vaddr)) +#define virt_to_phys(vaddr) ((unsigned long) (vaddr)) + +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +#endif + +#endif diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index da5891498..e5b388e26 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -1,7 +1,7 @@ /* * U-boot - io.h IO routines * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _BLACKFIN_IO_H @@ -27,42 +27,13 @@ #ifdef __KERNEL__ -#include - -static inline void sync(void) -{ - SSYNC(); -} +#include /* function prototypes for CF support */ extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words); extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words); extern unsigned char cf_inb(volatile unsigned char *addr); -extern void cf_outb(unsigned char val, volatile unsigned char *addr); - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} +extern void cf_outb(unsigned char val, volatile unsigned char* addr); /* * These are for ISA/PCI shared memory _only_ and should never be used @@ -75,72 +46,38 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) * memory location directly. */ -#ifndef __ASSEMBLY__ -static inline unsigned char readb(const volatile void *addr) -{ - unsigned int val; - int tmp; +#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; }) +#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; }) +#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; }) - __asm__ __volatile__ ("cli %1;\n\t" - "NOP; NOP; SSYNC;\n\t" - "%0 = b [%2] (z);\n\t" - "sti %1;\n\t" - : "=d"(val), "=d"(tmp): "a"(addr)); +#define writeb(b,addr) {((*(volatile unsigned char *) (addr)) = (b)); asm("ssync;");} +#define writew(b,addr) {((*(volatile unsigned short *) (addr)) = (b)); asm("ssync;");} +#define writel(b,addr) {((*(volatile unsigned int *) (addr)) = (b)); asm("ssync;");} - return (unsigned char) val; -} +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) -static inline unsigned short readw(const volatile void *addr) -{ - unsigned int val; - int tmp; +#define inb_p(addr) readb((addr) + BF533_PCIIO_BASE) +#define inb(addr) cf_inb((volatile unsigned char*)(addr)) - __asm__ __volatile__ ("cli %1;\n\t" - "NOP; NOP; SSYNC;\n\t" - "%0 = w [%2] (z);\n\t" - "sti %1;\n\t" - : "=d"(val), "=d"(tmp): "a"(addr)); +#define outb(x,addr) cf_outb((unsigned char)(x), (volatile unsigned char*)(addr)) +#define outb_p(x,addr) outb(x, (addr) + BF533_PCIIO_BASE) - return (unsigned short) val; -} +#define inw(addr) readw((addr) + BF533_PCIIO_BASE) +#define inl(addr) readl((addr) + BF533_PCIIO_BASE) -static inline unsigned int readl(const volatile void *addr) -{ - unsigned int val; - int tmp; +#define outw(x,addr) writew(x, (addr) + BF533_PCIIO_BASE) +#define outl(x,addr) writel(x, (addr) + BF533_PCIIO_BASE) - __asm__ __volatile__ ("cli %1;\n\t" - "NOP; NOP; SSYNC;\n\t" - "%0 = [%2];\n\t" - "sti %1;\n\t" - : "=d"(val), "=d"(tmp): "a"(addr)); - return val; -} +#define insb(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), count) +#define insw(port, addr, count) cf_insw((unsigned short*)addr, (unsigned short*)(port), (count)) +#define insl(port, addr, count) memcpy((void*)addr, (void*)(BF533_PCIIO_BASE + port), (4*count)) -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl - -#endif /* __ASSEMBLY__ */ - -#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel - -#define memset_io(a, b, c) memset((void *)(a), (b), (c)) -#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) -#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) - -#define inb(addr) cf_inb((volatile unsigned char *)(addr)) -#define outb(x, addr) cf_outb((unsigned char)(x), (volatile unsigned char *)(addr)) - -#define insw(port, addr, count) cf_insw((unsigned short *)addr, (unsigned short *)(port), (count)) - -#define outsw(port, addr, count) cf_outsw((unsigned short *)(port), (unsigned short *)addr, (count)) +#define outsb(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, count) +#define outsw(port,addr,count) cf_outsw((unsigned short*)(port), (unsigned short*)addr, (count)) +#define outsl(port,addr,count) memcpy((void*)(BF533_PCIIO_BASE + port), (void*)addr, (4*count)) #define IO_SPACE_LIMIT 0xffff @@ -158,7 +95,8 @@ extern inline void *ioremap(unsigned long physaddr, unsigned long size) { return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); } -extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) +extern inline void *ioremap_nocache(unsigned long physaddr, + unsigned long size) { return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); } @@ -176,9 +114,9 @@ extern inline void *ioremap_fullcache(unsigned long physaddr, extern void iounmap(void *addr); extern void blkfin_inv_cache_all(void); -#define dma_cache_inv(_start, _size) do { blkfin_inv_cache_all(); } while (0) -#define dma_cache_wback(_start, _size) do { } while (0) -#define dma_cache_wback_inv(_start, _size) do { blkfin_inv_cache_all(); } while (0) +#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) +#define dma_cache_wback(_start,_size) do { } while (0) +#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0) #endif #endif diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h new file mode 100644 index 000000000..5fbc5a363 --- /dev/null +++ b/include/asm-blackfin/irq.h @@ -0,0 +1,142 @@ +/* + * U-boot - irq.h Interrupt related header file + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file was based on + * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c + * + * Changed by HuTao Apr18, 2003 + * + * Copyright was missing when I got the code so took from MIPS arch ...MaTed--- + * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle + * + * Adapted for BlackFin (ADI) by Ted Ma + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2002 Lineo, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_IRQ_H_ +#define _BLACKFIN_IRQ_H_ + +#include +#include + +/* + * On the Blackfin, the interrupt structure allows remmapping of the hardware + * levels. + * - I'm going to assume that the H/W level is going to stay at the default + * settings. If someone wants to go through and abstart this out, feel free + * to mod the interrupt numbering scheme. + * - I'm abstracting the interrupts so that uClinux does not know anything + * about the H/W levels. If you want to change the H/W AND keep the abstracted + * levels that uClinux sees, you should be able to do most of it here. + * - I've left the "abstract" numbering sparce in case someone wants to pull the + * interrupts apart (just the TX/RX for the various devices) + */ + +#define NR_IRQS SYS_IRQS +/* + * "Generic" interrupt sources + */ +#define IRQ_SCHED_TIMER (8) /* interrupt source for scheduling timer */ + +static __inline__ int irq_cannonicalize(int irq) +{ + return irq; +} + +/* + * Machine specific interrupt sources. + * + * Adding an interrupt service routine for a source with this bit + * set indicates a special machine specific interrupt source. + * The machine specific files define these sources. + * + * The IRQ_MACHSPEC bit is now gone - the only thing it did was to + * introduce unnecessary overhead. + * + * All interrupt handling is actually machine specific so it is better + * to use function pointers, as used by the Sparc port, and select the + * interrupt handling functions when initializing the kernel. This way + * we save some unnecessary overhead at run-time. + * 01/11/97 - Jes + */ + +extern void (*mach_enable_irq) (unsigned int); +extern void (*mach_disable_irq) (unsigned int); +extern int sys_request_irq(unsigned int, + void (*)(int, void *, struct pt_regs *), + unsigned long, const char *, void *); +extern void sys_free_irq(unsigned int, void *); + +/* + * various flags for request_irq() - the Amiga now uses the standard + * mechanism like all other architectures - SA_INTERRUPT and SA_SHIRQ + * are your friends. + */ +#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */ +#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */ +#define IRQ_FLG_FAST (0x0004) +#define IRQ_FLG_SLOW (0x0008) +#define IRQ_FLG_STD (0x8000) /* internally used */ + +/* + * This structure is used to chain together the ISRs for a particular + * interrupt source (if it supports chaining). + */ +typedef struct irq_node { + void (*handler) (int, void *, struct pt_regs *); + unsigned long flags; + void *dev_id; + const char *devname; + struct irq_node *next; +} irq_node_t; + +/* + * This structure has only 4 elements for speed reasons + */ +typedef struct irq_handler { + void (*handler) (int, void *, struct pt_regs *); + unsigned long flags; + void *dev_id; + const char *devname; +} irq_handler_t; + +/* count of spurious interrupts */ +extern volatile unsigned int num_spurious; + +/* + * This function returns a new irq_node_t + */ +extern irq_node_t *new_irq_node(void); + +/* + * Some drivers want these entry points + */ +#define enable_irq(x) (mach_enable_irq ? (*mach_enable_irq)(x) : 0) +#define disable_irq(x) (mach_disable_irq ? (*mach_disable_irq)(x) : 0) + +#define enable_irq_nosync(x) enable_irq(x) +#define disable_irq_nosync(x) disable_irq(x) + +#endif diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h index fbb497c7b..18f0c36d2 100644 --- a/include/asm-blackfin/linkage.h +++ b/include/asm-blackfin/linkage.h @@ -1,7 +1,7 @@ /* * U-boot - linkage.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _LINUX_LINKAGE_H @@ -51,24 +51,10 @@ #define ALIGN __ALIGN #define ALIGN_STR __ALIGN_STR -#define LENTRY(name) \ - ALIGN; \ - SYMBOL_NAME_LABEL(name) - #define ENTRY(name) \ .globl SYMBOL_NAME(name); \ - LENTRY(name) -#endif - -#ifndef END -#define END(name) \ - .size name, .-name -#endif - -#ifndef ENDPROC -#define ENDPROC(name) \ - .type name, @function; \ - END(name) + ALIGN; \ + SYMBOL_NAME_LABEL(name) #endif #endif diff --git a/include/asm-blackfin/machdep.h b/include/asm-blackfin/machdep.h new file mode 100644 index 000000000..0a43ba1c5 --- /dev/null +++ b/include/asm-blackfin/machdep.h @@ -0,0 +1,89 @@ +/* + * U-boot - machdep.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_MACHDEP_H +#define _BLACKFIN_MACHDEP_H + +/* Machine dependent initial routines: + * + * Based on include/asm-m68knommu/machdep.h + * For blackfin, just now we only have bfin, so they'd point to the default bfin + * + */ + +struct pt_regs; +struct kbd_repeat; +struct mktime; +struct hwclk_time; +struct gendisk; +struct buffer_head; + +extern void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *)); + +/* machine dependent keyboard functions */ +extern int (*mach_keyb_init) (void); +extern int (*mach_kbdrate) (struct kbd_repeat *); +extern void (*mach_kbd_leds) (unsigned int); + +/* machine dependent irq functions */ +extern void (*mach_init_IRQ) (void); +extern void (*(*mach_default_handler)[]) (int, void *, struct pt_regs *); +extern int (*mach_request_irq) (unsigned int irq, + void (*handler) (int, void *, + struct pt_regs *), + unsigned long flags, const char *devname, + void *dev_id); +extern void (*mach_free_irq) (unsigned int irq, void *dev_id); +extern void (*mach_get_model) (char *model); +extern int (*mach_get_hardware_list) (char *buffer); +extern int (*mach_get_irq_list) (char *buf); +extern void (*mach_process_int) (int irq, struct pt_regs * fp); + +/* machine dependent timer functions */ +extern unsigned long (*mach_gettimeoffset) (void); +extern void (*mach_gettod) (int *year, int *mon, int *day, int *hour, + int *min, int *sec); +extern int (*mach_hwclk) (int, struct hwclk_time *); +extern int (*mach_set_clock_mmss) (unsigned long); +extern void (*mach_reset) (void); +extern void (*mach_halt) (void); +extern void (*mach_power_off) (void); +extern unsigned long (*mach_hd_init) (unsigned long, unsigned long); +extern void (*mach_hd_setup) (char *, int *); +extern long mach_max_dma_address; +extern void (*mach_floppy_setup) (char *, int *); +extern void (*mach_floppy_eject) (void); +extern void (*mach_heartbeat) (int); +extern void (*mach_l2_flush) (int); +extern int mach_sysrq_key; +extern int mach_sysrq_shift_state; +extern int mach_sysrq_shift_mask; +extern char *mach_sysrq_xlate; + +#ifdef CONFIG_UCLINUX +extern void config_BSP(char *command, int len); +extern void (*mach_tick) (void); +#endif + +#endif diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h index cb448ad61..1a13d908e 100644 --- a/include/asm-blackfin/mem_init.h +++ b/include/asm-blackfin/mem_init.h @@ -1,7 +1,7 @@ /* * U-boot - mem_init.h Header file for memory initialization * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,17 +18,11 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \ - CONFIG_MEM_MT48LC64M4A2FB_7E || \ - CONFIG_MEM_MT48LC16M8A2TG_75 || \ - CONFIG_MEM_MT48LC8M16A2TG_7E || \ - CONFIG_MEM_MT48LC8M32B2B5_7 || \ - CONFIG_MEM_MT48LC32M8A2_75) - +#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E ) #if ( CONFIG_SCLK_HZ > 119402985 ) #define SDRAM_tRP TRP_2 #define SDRAM_tRP_num 2 @@ -72,7 +66,7 @@ #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 ) #define SDRAM_tRP TRP_1 #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_3 + #define SDRAM_tRAS TRAS_4 #define SDRAM_tRAS_num 3 #define SDRAM_tRCD TRCD_1 #define SDRAM_tWR TWR_2 @@ -105,46 +99,18 @@ #if (CONFIG_MEM_MT48LC16M16A2TG_75) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_3 #endif #if (CONFIG_MEM_MT48LC64M4A2FB_7E) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_2 #endif -#if (CONFIG_MEM_MT48LC16M8A2TG_75) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_MT48LC32M8A2_75) -/*SDRAM INFORMATION: */ -#define SDRAM_Tref 64 /* Refresh period in milliseconds */ -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ -#define SDRAM_CL CL_3 -#endif - -#if (CONFIG_MEM_MT48LC8M16A2TG_7E) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_2 -#endif - -#if (CONFIG_MEM_MT48LC8M32B2B5_7) - /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ - #define SDRAM_CL CL_3 -#endif - #if ( CONFIG_MEM_SIZE == 128 ) #define SDRAM_SIZE EBSZ_128 #endif diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h new file mode 100644 index 000000000..406ece537 --- /dev/null +++ b/include/asm-blackfin/page.h @@ -0,0 +1,128 @@ +/* + * U-boot - page.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_PAGE_H +#define _BLACKFIN_PAGE_H + +#include + +/* PAGE_SHIFT determines the page size */ + +#define PAGE_SHIFT (12) +#define PAGE_SIZE (4096) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +#ifdef __KERNEL__ + +#include + +#if PAGE_SHIFT < 13 +#define KTHREAD_SIZE (8192) +#else +#define KTHREAD_SIZE PAGE_SIZE +#endif + +#ifndef __ASSEMBLY__ + +#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) +#define free_user_page(page, addr) free_page(addr) + +#define clear_page(page) memset((page), 0, PAGE_SIZE) +#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) + +#define clear_user_page(page, vaddr) clear_page(page) +#define copy_user_page(to, from, vaddr) copy_page(to, from) + +/* + * These are used to make use of C type-checking.. + */ +typedef struct { + unsigned long pte; +} pte_t; +typedef struct { + unsigned long pmd[16]; +} pmd_t; +typedef struct { + unsigned long pgd; +} pgd_t; +typedef struct { + unsigned long pgprot; +} pgprot_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((&x)->pmd[0]) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgd(x) ((pgd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +/* to align the pointer to the (next) page boundary */ +#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) + +/* Pure 2^n version of get_order */ +extern __inline__ int get_order(unsigned long size) +{ + int order; + + size = (size - 1) >> (PAGE_SHIFT - 1); + order = -1; + do { + size >>= 1; + order++; + } while (size); + return order; +} + +#endif /* !__ASSEMBLY__ */ + +#include + +#define PAGE_OFFSET (PAGE_OFFSET_RAW) + +#ifndef __ASSEMBLY__ + +#define __pa(vaddr) virt_to_phys((void *)vaddr) +#define __va(paddr) phys_to_virt((unsigned long)paddr) + +#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) +#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) +#define VALID_PAGE(page) ((page - mem_map) < max_mapnr) + +#define BUG() do { \ + \ + while (1); /* dead-loop */ \ +} while (0) + +#define PAGE_BUG(page) do { \ + BUG(); \ +} while (0) + +#endif + +#endif + +#endif diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h new file mode 100644 index 000000000..262473fc3 --- /dev/null +++ b/include/asm-blackfin/page_offset.h @@ -0,0 +1,35 @@ +/* + * U-boot - page_offset.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Changes made by Akbar Hussain April 10, 2001 + */ + +#include + +/* This handles the memory map.. */ + +#ifdef CONFIG_BLACKFIN +#define PAGE_OFFSET_RAW 0x00000000 +#endif diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h index 39651d206..f1f2b5ffc 100644 --- a/include/asm-blackfin/posix_types.h +++ b/include/asm-blackfin/posix_types.h @@ -1,7 +1,7 @@ /* * U-boot - posix_types.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef __ARCH_BLACKFIN_POSIX_TYPES_H @@ -59,9 +59,6 @@ typedef unsigned int __kernel_gid32_t; typedef unsigned short __kernel_old_uid_t; typedef unsigned short __kernel_old_gid_t; -#define BOOL_WAS_DEFINED -typedef enum { false = 0, true = 1 } bool; - #ifdef __GNUC__ typedef long long __kernel_loff_t; #endif diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h index d700ccef2..19bd72010 100644 --- a/include/asm-blackfin/processor.h +++ b/include/asm-blackfin/processor.h @@ -1,7 +1,7 @@ /* * U-boot - processor.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * This file is based on * include/asm-m68k/processor.h @@ -23,13 +23,152 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef __ASM_BLACKFIN_PROCESSOR_H #define __ASM_BLACKFIN_PROCESSOR_H -/* Stub to make stupid common code happy */ +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#include +#include +#include +#include + +extern inline unsigned long rdusp(void) +{ + unsigned long usp; + + __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp)); + return usp; +} + +extern inline void wrusp(unsigned long usp) +{ + __asm__ __volatile__("usp = %0;\n\t"::"da"(usp)); +} + +/* + * User space process size: 3.75GB. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. + */ +#define TASK_SIZE (0xF0000000UL) + +/* + * Bus types + */ +#define EISA_bus 0 +#define MCA_bus 0 + +/* There is no pc register avaliable for BLACKFIN, so we are going to get + * it indirectly + */ + +#if 0 +inline unsigned long obtain_pc_indirectly(void) +{ + unsigned long pc; + __asm__ __volatile__("%0 = rets;\n":"=d"(pc)); + return (pc - 4); /* call pcrel24 is 4 bytes long */ +} +#endif + +/* + * if you change this structure, you must change the code and offsets + * in m68k/machasm.S + */ + +struct thread_struct { + unsigned long ksp; /* kernel stack pointer */ + unsigned long usp; /* user stack pointer */ + unsigned short seqstat; /* saved status register */ + unsigned long esp0; /* points to SR of stack frame pt_regs */ + unsigned long pc; /* instruction pointer */ +}; + +#define INIT_MMAP { &init_mm, 0, 0x40000000, NULL, __pgprot(_PAGE_PRESENT|_PAGE_ACCESSED), VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL } + +#define INIT_THREAD { \ + sizeof(init_stack) + (unsigned long) init_stack, 0, \ + PS_S, 0\ +} + +/* + * Do necessary setup to start up a newly executed thread. + * + * pass the data segment into user programs if it exists, + * it can't hurt anything as far as I can tell + */ +#define start_thread(_regs, _pc, _usp) \ +do { \ + set_fs(USER_DS); /* reads from user space */ \ + (_regs)->pc = (_pc); \ + if (current->mm) \ + (_regs)->r5 = current->mm->start_data; \ + (_regs)->seqstat &= ~0x0c00; \ + wrusp(_usp); \ + /* Adde by HuTao, May 26, 2003 3:39PM */\ + if ((_regs)->ipend & 0x8000) /* check whether system in supper mode - StChen */\ + (_regs)->ipend = 0x0;\ +} while(0) + +/* Forward declaration, a strange C thing */ +struct task_struct; + +/* Free all resources held by a thread. */ +static inline void release_thread(struct task_struct *dead_task) +{ +} + +extern int kernel_thread(int (*fn) (void *), void *arg, + unsigned long flags); + +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) +#define forget_segments() do { } while (0) + +/* + * Free current thread data structures etc.. + */ +static inline void exit_thread(void) +{ +} + +/* + * Return saved PC of a blocked thread. + */ +extern inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + extern void scheduling_functions_start_here(void); + extern void scheduling_functions_end_here(void); + return 0; +} + +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) \ + ({ \ + unsigned long eip = 0; \ + if ((tsk)->thread.esp0 > PAGE_SIZE && \ + MAP_NR((tsk)->thread.esp0) < max_mapnr) \ + eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ + eip; }) +#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) +#define THREAD_SIZE (2*PAGE_SIZE) + +/* Allocation and freeing of basic task resources. */ +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) #endif diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h index f1b7d0064..afd57773a 100644 --- a/include/asm-blackfin/ptrace.h +++ b/include/asm-blackfin/ptrace.h @@ -1,7 +1,7 @@ /* * U-boot - ptrace.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _BLACKFIN_PTRACE_H diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h new file mode 100644 index 000000000..9e6d817fc --- /dev/null +++ b/include/asm-blackfin/segment.h @@ -0,0 +1,46 @@ +/* + * U-boot - segment.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_SEGMENT_H +#define _BLACKFIN_SEGMENT_H + +/* define constants */ +typedef unsigned long mm_segment_t; /* domain register */ + +#define KERNEL_CS 0x0 +#define KERNEL_DS 0x0 +#define __KERNEL_CS 0x0 +#define __KERNEL_DS 0x0 + +#define USER_CS 0x1 +#define USER_DS 0x1 +#define __USER_CS 0x1 +#define __USER_DS 0x1 + +#define get_ds() (KERNEL_DS) +#define get_fs() (__USER_DS) +#define segment_eq(a,b) ((a) == (b)) +#define set_fs(val) + +#endif diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h new file mode 100644 index 000000000..6ce96880a --- /dev/null +++ b/include/asm-blackfin/setup.h @@ -0,0 +1,86 @@ +/* + * U-boot - setup.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * asm/setup.h -- Definition of the Linux/Blackfin setup information + * Copyright Lineo, Inc 2001 Tony Kou + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BLACKFIN_SETUP_H +#define _BLACKFIN_SETUP_H + +#include + +/* + * Linux/Blackfin Architectures + */ + +#define MACH_BFIN 1 + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ +extern unsigned long blackfin_machtype; +#endif + +#if defined(CONFIG_BFIN) +#define MACH_IS_BFIN (blackfin_machtype == MACH_BFIN) +#endif + +#ifndef MACH_TYPE +#define MACH_TYPE (blackfin_machtype) +#endif + +#endif + +/* + * CPU, FPU and MMU types + * + * Note: we don't need now: + * + */ + +#ifndef __ASSEMBLY__ +extern unsigned long blackfin_cputype; +#ifdef CONFIG_VME +extern unsigned long vme_brdtype; +#endif + +/* + * Miscellaneous + */ + +#define NUM_MEMINFO 4 +#define CL_SIZE 256 + +extern int blackfin_num_memory; /* # of memory blocks found (and used) */ +extern int blackfin_realnum_memory; /* real # of memory blocks found */ +extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */ + +struct mem_info { + unsigned long addr; /* physical address of memory chunk */ + unsigned long size; /* length of memory chunk (in bytes) */ +}; +#endif + +#endif diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h index 2ac899069..fbef18618 100644 --- a/include/asm-blackfin/shared_resources.h +++ b/include/asm-blackfin/shared_resources.h @@ -1,7 +1,7 @@ /* * U-boot - setup.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _SHARED_RESOURCES_H_ @@ -27,7 +27,7 @@ void swap_to(int device_id); -#define FLASH 0 +#define FLASH 0 #define ETHERNET 1 #endif /* _SHARED_RESOURCES_H_ */ diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h index 18306dd54..ffd81d61a 100644 --- a/include/asm-blackfin/string.h +++ b/include/asm-blackfin/string.h @@ -1,7 +1,7 @@ /* * U-boot - string.h String functions * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ /* Changed by Lineo Inc. May 2001 */ @@ -29,26 +29,23 @@ #ifdef __KERNEL__ /* only set these up for kernel code */ -#include -#include +#include +#include +#include #define __HAVE_ARCH_STRCPY #define __HAVE_ARCH_STRNCPY #define __HAVE_ARCH_STRCMP #define __HAVE_ARCH_STRNCMP #define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMCMP -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_MEMMOVE extern char *strcpy(char *dest, const char *src); extern char *strncpy(char *dest, const char *src, size_t n); extern int strcmp(const char *cs, const char *ct); extern int strncmp(const char *cs, const char *ct, size_t count); -extern void *memcpy(void *dest, const void *src, size_t count); +extern void * memcpy(void * dest,const void *src,size_t count); extern void *memset(void *s, int c, size_t count); extern int memcmp(const void *, const void *, __kernel_size_t); -extern void *memmove(void *dest, const void *src, size_t count); #else /* KERNEL */ diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h index 6bc7208ca..0e53adfe0 100644 --- a/include/asm-blackfin/system.h +++ b/include/asm-blackfin/system.h @@ -1,7 +1,7 @@ /* * U-boot - system.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,55 +18,110 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _BLACKFIN_SYSTEM_H #define _BLACKFIN_SYSTEM_H +#include /* get configuration macros */ +#include +#include +#include +#include + +#define prepare_to_switch() do { } while(0) + +/* + * switch_to(n) should switch tasks to task ptr, first checking that + * ptr isn't the current task, in which case it does nothing. This + * also clears the TS-flag if the task we switched to has used the + * math co-processor latest. + * + * 05/25/01 - Tony Kou (tonyko@lineo.ca) + * + * Adapted for BlackFin (ADI) by Ted Ma, Metrowerks, and Motorola GSG + * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com) + * Copyright (c) 2003 Metrowerks (www.metrowerks.com) + */ + +asmlinkage void resume(void); + +#define switch_to(prev,next,last) { \ + void *_last; \ + __asm__ __volatile__( \ + "r0 = %1;\n\t" \ + "r1 = %2;\n\t" \ + "call resume;\n\t" \ + "%0 = r0;\n\t" \ + : "=d" (_last) \ + : "d" (prev), \ + "d" (next) \ + : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\ + (last) = _last; \ +} + +/* Force kerenl switch to user mode -- Steven Chen */ +#define switch_to_user_mode() { \ + __asm__ __volatile__( \ + "call kernel_to_user_mode;\n\t" \ + :: \ + : "CC", "R0", "R1", "R2", "R3", "R4", "R5", "P0", "P1");\ +} + /* * Interrupt configuring macros. */ extern int irq_flags; -#define local_irq_enable() \ - __asm__ __volatile__ ( \ - "sti %0;" \ - : \ - : "d" (irq_flags) \ - ) +#define __sti() { \ + __asm__ __volatile__ ( \ + "r3 = %0;" \ + "sti r3;" \ + ::"m"(irq_flags):"R3"); \ +} -#define local_irq_disable() \ - do { \ - int __tmp_dummy; \ - __asm__ __volatile__ ( \ - "cli %0;" \ - : "=d" (__tmp_dummy) \ - ); \ - } while (0) +#define __cli() { \ + __asm__ __volatile__ ( \ + "cli r3;" \ + :::"R3"); \ +} -# define local_irq_save(x) \ - __asm__ __volatile__ ( \ - "cli %0;" \ - : "=&d" (x) \ - ) +#define __save_flags(x) { \ + __asm__ __volatile__ ( \ + "cli r3;" \ + "%0 = r3;" \ + "sti r3;" \ + ::"m"(x):"R3"); \ +} -#define local_save_flags(x) \ - __asm__ __volatile__ ( \ - "cli %0;" \ - "sti %0;" \ - : "=d" (x) \ - ) +#define __save_and_cli(x) { \ + __asm__ __volatile__ ( \ + "cli r3;" \ + "%0 = r3;" \ + ::"m"(x):"R3"); \ +} -#define irqs_enabled_from_flags(x) ((x) != 0x1f) +#define __restore_flags(x) { \ + __asm__ __volatile__ ( \ + "r3 = %0;" \ + "sti r3;" \ + ::"m"(x):"R3"); \ +} -#define local_irq_restore(x) \ - do { \ - if (irqs_enabled_from_flags(x)) \ - local_irq_enable(); \ - } while (0) +/* For spinlocks etc */ +#define local_irq_save(x) __save_and_cli(x) +#define local_irq_restore(x) __restore_flags(x) +#define local_irq_disable() __cli() +#define local_irq_enable() __sti() + +#define cli() __cli() +#define sti() __sti() +#define save_flags(x) __save_flags(x) +#define restore_flags(x) __restore_flags(x) +#define save_and_cli(x) __save_and_cli(x) /* * Force strict CPU ordering. @@ -79,43 +134,49 @@ extern int irq_flags; #define set_mb(var, value) set_rmb(var, value) #define set_wmb(var, value) do { var = value; wmb(); } while (0) -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#endif + +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#define tas(ptr) (xchg((ptr),1)) struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((volatile struct __xchg_dummy *)(x)) +#define __xg(x) ((volatile struct __xchg_dummy *)(x)) static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) { - unsigned long tmp = 0; + unsigned long tmp; unsigned long flags = 0; - local_irq_save(flags); + save_and_cli(flags); switch (size) { case 1: - __asm__ __volatile__ - ("%0 = b%2 (z);\n\t" - "b%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); break; case 2: - __asm__ __volatile__ - ("%0 = w%2 (z);\n\t" - "w%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); break; case 4: - __asm__ __volatile__ - ("%0 = %2;\n\t" - "%2 = %1;\n\t" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + __asm__ __volatile__("%0 = %2;\n\t" "%2 = %1;\n\t": "=&d"(tmp): "d"(x), "m"(*__xg(ptr)):"memory"); break; } - local_irq_restore(flags); + restore_flags(flags); return tmp; } +/* Depend on whether Blackfin has hard reset function */ +/* YES it does, but it is tricky to implement - FIXME later ...MaTed--- */ +#define HARD_RESET_NOW() ({}) + #endif /* _BLACKFIN_SYSTEM_H */ diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h index b90cedacb..29e6eba6f 100644 --- a/include/asm-blackfin/traps.h +++ b/include/asm-blackfin/traps.h @@ -1,7 +1,7 @@ /* * U-boot - traps.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * This file is based on * linux/include/asm/traps.h @@ -23,8 +23,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ /* diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h index 2160ba0d0..942ed275a 100644 --- a/include/asm-blackfin/types.h +++ b/include/asm-blackfin/types.h @@ -1,7 +1,7 @@ /* * U-boot - types.h * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * See file CREDITS for list of people who contributed to this * project. @@ -18,8 +18,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _BLACKFIN_TYPES_H @@ -50,9 +50,9 @@ typedef __signed__ int __s32; typedef unsigned int __u32; /* HK0617 -- Changes to unsigned long temporarily */ -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif /* @@ -78,9 +78,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - #endif #endif diff --git a/include/asm-blackfin/u-boot.h b/include/asm-blackfin/u-boot.h index 9d2903be9..ec3933803 100644 --- a/include/asm-blackfin/u-boot.h +++ b/include/asm-blackfin/u-boot.h @@ -1,7 +1,7 @@ /* * U-boot - u-boot.h Structure declarations for board specific data * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005 blackfin.uclinux.org * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -21,8 +21,8 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef _U_BOOT_H_ @@ -32,18 +32,16 @@ typedef struct bd_info { int bi_baudrate; /* serial console baudrate */ unsigned long bi_ip_addr; /* IP Address */ unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ - const char *bi_r_version; - const char *bi_cpu; - const char *bi_board_name; - unsigned long bi_vco; - unsigned long bi_cclk; - unsigned long bi_sclk; } bd_t; +#define bi_env_data bi_env->data +#define bi_env_crc bi_env->crc + #endif /* _U_BOOT_H_ */ diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h new file mode 100644 index 000000000..8578166a3 --- /dev/null +++ b/include/asm-blackfin/uaccess.h @@ -0,0 +1,207 @@ +/* + * U-boot - uaccess.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * This file is based on + * Based on: include/asm-m68knommu/uaccess.h + * Changes made by Lineo Inc. May 2001 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_UACCESS_H +#define __BLACKFIN_UACCESS_H + +/* + * User space memory access functions + */ +#include +#include + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +/* We let the MMU do all checking */ +static inline int access_ok(int type, const void *addr, unsigned long size) +{ + return ((unsigned long) addr < 0x10f00000); /* need final decision - Tony */ +} + +static inline int verify_area(int type, const void *addr, + unsigned long size) +{ + return access_ok(type, addr, size) ? 0 : -EFAULT; +} + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry { + unsigned long insn, fixup; +}; + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + +/* + * These are the main single-value transfer routines. They automatically + * use the right size if we just have the right pointer type. + */ + +#define put_user(x, ptr) \ +({ \ + int __pu_err = 0; \ + typeof(*(ptr)) __pu_val = (x); \ + switch (sizeof (*(ptr))) { \ + case 1: \ + __put_user_asm(__pu_err, __pu_val, ptr, B); \ + break; \ + case 2: \ + __put_user_asm(__pu_err, __pu_val, ptr, W); \ + break; \ + case 4: \ + __put_user_asm(__pu_err, __pu_val, ptr, ); \ + break; \ + default: \ + __pu_err = __put_user_bad(); \ + break; \ + } \ + __pu_err; \ +}) +/* + * [pregs] = dregs ==> 32bits + * H[pregs] = dregs ==> 16bits + * B[pregs] = dregs ==> 8 bits + */ + +#define __put_user(x, ptr) put_user(x, ptr) + +static inline int bad_user_access_length(void) +{ + panic("bad_user_access_length"); + return -1; +} + +#define __put_user_bad() (bad_user_access_length(), (-EFAULT)) + +/* + * Tell gcc we read from memory instead of writing: this is because + * we do not write to any memory gcc knows about, so there are no + * aliasing issues. + */ + +#define __ptr(x) ((unsigned long *)(x)) + +#define __put_user_asm(err,x,ptr,bhw) \ + __asm__ (#bhw"[%1] = %0;\n\t" \ + : /* no outputs */ \ + :"d" (x),"a" (__ptr(ptr)) : "memory") + +#define get_user(x, ptr) \ +({ \ + int __gu_err = 0; \ + typeof(*(ptr)) __gu_val = 0; \ + switch (sizeof(*(ptr))) { \ + case 1: \ + __get_user_asm(__gu_err, __gu_val, ptr, B, "=d",(Z)); \ + break; \ + case 2: \ + __get_user_asm(__gu_err, __gu_val, ptr, W, "=r",(Z)); \ + break; \ + case 4: \ + __get_user_asm(__gu_err, __gu_val, ptr, , "=r",); \ + break; \ + default: \ + __gu_val = 0; \ + __gu_err = __get_user_bad(); \ + break; \ + } \ + (x) = __gu_val; \ + __gu_err; \ +}) + +/* dregs = [pregs] ==> 32bits + * H[pregs] ==> 16bits + * B[pregs] ==> 8 bits + */ + +#define __get_user(x, ptr) get_user(x, ptr) +#define __get_user_bad() (bad_user_access_length(), (-EFAULT)) + +#define __get_user_asm(err,x,ptr,bhw,reg,option) \ + __asm__ ("%0 =" #bhw "[%1]"#option";\n\t" \ + : "=d" (x) \ + : "a" (__ptr(ptr))) + +#define copy_from_user(to, from, n) (memcpy(to, from, n), 0) +#define copy_to_user(to, from, n) (memcpy(to, from, n), 0) + +#define __copy_from_user(to, from, n) copy_from_user(to, from, n) +#define __copy_to_user(to, from, n) copy_to_user(to, from, n) + +#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; }) +#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; }) + +/* + * Copy a null terminated string from userspace. + */ + +static inline long strncpy_from_user(char *dst, const char *src, + long count) +{ + char *tmp; + strncpy(dst, src, count); + for (tmp = dst; *tmp && count > 0; tmp++, count--); + return (tmp - dst); /* DAVIDM should we count a NUL ? check getname */ +} + +/* + * Return the size of a string (including the ending 0) + * + * Return 0 on exception, a value greater than N if too long + */ +static inline long strnlen_user(const char *src, long n) +{ + return (strlen(src) + 1); /* DAVIDM make safer */ +} + +#define strlen_user(str) strnlen_user(str, 32767) + +/* + * Zero Userspace + */ + +static inline unsigned long clear_user(void *to, unsigned long n) +{ + memset(to, 0, n); + return (0); +} + +#endif diff --git a/include/asm-blackfin/virtconvert.h b/include/asm-blackfin/virtconvert.h new file mode 100644 index 000000000..769f5a089 --- /dev/null +++ b/include/asm-blackfin/virtconvert.h @@ -0,0 +1,47 @@ +/* + * U-boot - virtconvert.h + * + * Copyright (c) 2005 blackfin.uclinux.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BLACKFIN_VIRT_CONVERT__ +#define __BLACKFIN_VIRT_CONVERT__ + +/* + * Macros used for converting between virtual and physical mappings. + */ + +#ifdef __KERNEL__ + +#include +#include +#include + +#define mm_vtop(vaddr) ((unsigned long) vaddr) +#define mm_ptov(vaddr) ((unsigned long) vaddr) +#define phys_to_virt(vaddr) ((unsigned long) vaddr) +#define virt_to_phys(vaddr) ((unsigned long) vaddr) + +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +#endif +#endif diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h index 5dfb59510..1d309d5b5 100644 --- a/include/asm-i386/global_data.h +++ b/include/asm-i386/global_data.h @@ -43,7 +43,7 @@ typedef struct { unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; - phys_size_t ram_size; /* RAM size */ + unsigned long ram_size; /* RAM size */ unsigned long reset_status; /* reset status register at boot */ void **jt; /* jump table */ } gd_t; @@ -54,9 +54,6 @@ typedef struct { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ extern gd_t *global_data; diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h index 0f7e7a551..d5abbbe52 100644 --- a/include/asm-i386/ic/sc520.h +++ b/include/asm-i386/ic/sc520.h @@ -25,209 +25,209 @@ #define _ASM_IC_SC520_H_ 1 /* Memory mapped configuration registers, MMCR */ -#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */ -#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */ -#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */ -#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */ -#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/ -#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/ -#define SC520_ECCCTL 0x0020 /* ECC Control Register */ -#define SC520_ECCSTA 0x0021 /* ECC Status Register */ -#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */ -#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */ -#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ -#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */ -#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */ -#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */ -#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */ -#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */ -#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */ -#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */ -#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */ -#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */ -#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */ -#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */ -#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */ -#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */ -#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */ -#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */ -#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */ -#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */ -#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */ -#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */ -#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */ -#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */ -#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */ -#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */ -#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */ -#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */ -#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */ -#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */ -#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */ -#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */ -#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ -#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ -#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */ -#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */ -#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */ -#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */ -#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */ -#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */ -#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */ -#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */ -#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */ -#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */ -#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */ -#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */ -#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */ -#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */ -#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */ -#define SC520_CLKSEL 0x0c26 /* Clock Select */ -#define SC520_DSCTL 0x0c28 /* Drive Strength Control */ -#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */ -#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */ -#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */ -#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */ -#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */ -#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */ -#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */ -#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */ -#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ -#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ -#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */ -#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */ -#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */ -#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */ -#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */ -#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */ -#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */ -#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */ -#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */ -#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */ -#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */ -#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */ -#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */ -#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */ -#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */ -#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */ -#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */ -#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */ -#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */ -#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */ -#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */ -#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */ -#define SC520_SSICTL 0x0cd0 /* SSI Control */ -#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */ -#define SC520_SSICMD 0x0cd2 /* SSI Command */ -#define SC520_SSISTA 0x0cd3 /* SSI Status */ -#define SC520_SSIRCV 0x0cd4 /* SSI Receive */ -#define SC520_PICICR 0x0d00 /* Interrupt Control Register */ -#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */ -#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */ -#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */ -#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */ -#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */ -#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */ -#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */ -#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */ -#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */ -#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */ -#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */ -#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */ -#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */ -#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */ -#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */ -#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */ -#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */ -#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */ -#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */ -#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */ -#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */ -#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */ -#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */ -#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */ -#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */ -#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */ -#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */ -#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */ -#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */ -#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */ -#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */ -#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */ -#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */ -#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */ -#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */ -#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */ -#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */ -#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */ -#define SC520_SYSINFO 0x0d70 /* System Board Information Register */ -#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */ -#define SC520_RESSTA 0x0d74 /* Reset Status Register */ -#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */ -#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */ -#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */ -#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */ -#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */ -#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */ -#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */ -#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */ -#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */ -#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */ -#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */ -#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */ -#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */ -#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */ -#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */ -#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */ -#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */ -#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */ -#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */ -#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */ -#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */ -#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */ -#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */ -#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */ -#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */ -#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */ -#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */ -#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */ -#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */ -#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */ +#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */ +#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */ +#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */ +#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */ +#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/ +#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/ +#define SC520_ECCCTL 0x0020 /* ECC Control Register */ +#define SC520_ECCSTA 0x0021 /* ECC Status Register */ +#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */ +#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */ +#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ +#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */ +#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */ +#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */ +#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */ +#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */ +#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */ +#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */ +#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */ +#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */ +#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */ +#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */ +#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */ +#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */ +#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */ +#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */ +#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */ +#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */ +#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */ +#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */ +#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */ +#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */ +#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */ +#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */ +#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */ +#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */ +#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */ +#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */ +#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */ +#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */ +#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ +#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ +#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */ +#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */ +#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */ +#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */ +#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */ +#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */ +#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */ +#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */ +#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */ +#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */ +#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */ +#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */ +#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */ +#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */ +#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */ +#define SC520_CLKSEL 0x0c26 /* Clock Select */ +#define SC520_DSCTL 0x0c28 /* Drive Strength Control */ +#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */ +#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */ +#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */ +#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */ +#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */ +#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */ +#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */ +#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */ +#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ +#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ +#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */ +#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */ +#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */ +#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */ +#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */ +#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */ +#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */ +#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */ +#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */ +#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */ +#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */ +#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */ +#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */ +#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */ +#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */ +#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */ +#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */ +#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */ +#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */ +#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */ +#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */ +#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */ +#define SC520_SSICTL 0x0cd0 /* SSI Control */ +#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */ +#define SC520_SSICMD 0x0cd2 /* SSI Command */ +#define SC520_SSISTA 0x0cd3 /* SSI Status */ +#define SC520_SSIRCV 0x0cd4 /* SSI Receive */ +#define SC520_PICICR 0x0d00 /* Interrupt Control Register */ +#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */ +#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */ +#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */ +#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */ +#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */ +#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */ +#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */ +#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */ +#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */ +#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */ +#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */ +#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */ +#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */ +#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */ +#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */ +#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */ +#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */ +#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */ +#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */ +#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */ +#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */ +#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */ +#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */ +#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */ +#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */ +#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */ +#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */ +#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */ +#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */ +#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */ +#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */ +#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */ +#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */ +#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */ +#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */ +#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */ +#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */ +#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */ +#define SC520_SYSINFO 0x0d70 /* System Board Information Register */ +#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */ +#define SC520_RESSTA 0x0d74 /* Reset Status Register */ +#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */ +#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */ +#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */ +#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */ +#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */ +#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */ +#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */ +#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */ +#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */ +#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */ +#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */ +#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */ +#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */ +#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */ +#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */ +#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */ +#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */ +#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */ +#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */ +#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */ +#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */ +#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */ +#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */ +#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */ +#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */ +#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */ +#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */ +#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */ +#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */ +#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */ /* MMCR Register bits (not all of them :) ) */ /* SSI Stuff */ -#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */ -#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */ -#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */ -#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */ -#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */ -#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */ -#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */ -#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */ +#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */ +#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */ +#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */ +#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */ +#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */ +#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */ +#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */ +#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */ -#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */ -#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */ -#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */ -#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */ +#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */ +#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */ +#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */ +#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */ -#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */ -#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */ -#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */ -#define SSISTA_BSY 0x02 /* SSI Busy */ -#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ +#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */ +#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */ +#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */ +#define SSISTA_BSY 0x02 /* SSI Busy */ +#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ /* BITS for SC520_ADDDECCTL: */ -#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ -#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ -#define RTC_DIS 0x04 /* RTC Disable */ -#define UART2_DIS 0x02 /* UART2 Disable */ -#define UART1_DIS 0x01 /* UART1 Disable */ +#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ +#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ +#define RTC_DIS 0x04 /* RTC Disable */ +#define UART2_DIS 0x02 /* UART2 Disable */ +#define UART1_DIS 0x01 /* UART1 Disable */ /* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */ #define SC520_REG_ADDR 0x00000cf8 @@ -256,7 +256,7 @@ /* PCI bus memory from 0x10000000 to 0x26ffffff * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */ #define SC520_PCI_MEM_PHYS 0x10000000 -#define SC520_PCI_MEM_BUS 0x10000000 +#define SC520_PCI_MEM_BUS 0x10000000 #define SC520_PCI_MEM_SIZE 0x17000000 /* 0x28000000 - 0x3fffffff is used by the flash banks */ diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h index 2c57140fb..85d44aaa1 100644 --- a/include/asm-i386/io.h +++ b/include/asm-i386/io.h @@ -201,32 +201,4 @@ __OUTS(b) __OUTS(w) __OUTS(l) -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - #endif diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h index 9a40e383e..69f8a5a7c 100644 --- a/include/asm-i386/types.h +++ b/include/asm-i386/types.h @@ -17,9 +17,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif /* @@ -45,9 +45,6 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - #endif /* __KERNEL__ */ #endif diff --git a/include/asm-i386/u-boot.h b/include/asm-i386/u-boot.h index fc5a2ae59..1e19f8f3d 100644 --- a/include/asm-i386/u-boot.h +++ b/include/asm-i386/u-boot.h @@ -38,7 +38,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-i386/zimage.h b/include/asm-i386/zimage.h index b6266e456..c7103b1f3 100644 --- a/include/asm-i386/zimage.h +++ b/include/asm-i386/zimage.h @@ -70,5 +70,6 @@ void *load_zimage(char *image, unsigned long kernel_size, int auto_boot); void boot_zimage(void *setup_base); +image_header_t *fake_zimage_header(image_header_t *hdr, void *ptr, int size); #endif diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h index 0f9e8abe9..32837142c 100644 --- a/include/asm-m68k/bitops.h +++ b/include/asm-m68k/bitops.h @@ -15,43 +15,4 @@ extern int test_and_set_bit(int nr, volatile void *addr); extern int test_and_clear_bit(int nr, volatile void *addr); extern int test_and_change_bit(int nr, volatile void *addr); -#ifdef __KERNEL__ - -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -extern __inline__ int ffs(int x) -{ - int r = 1; - - if (!x) - return 0; - if (!(x & 0xffff)) { - x >>= 16; - r += 16; - } - if (!(x & 0xff)) { - x >>= 8; - r += 8; - } - if (!(x & 0xf)) { - x >>= 4; - r += 4; - } - if (!(x & 3)) { - x >>= 2; - r += 2; - } - if (!(x & 1)) { - x >>= 1; - r += 1; - } - return r; -} -#define __ffs(x) (ffs(x) - 1) - -#endif /* __KERNEL__ */ - #endif /* _M68K_BITOPS_H */ diff --git a/include/asm-m68k/byteorder.h b/include/asm-m68k/byteorder.h index 0e2a0ed8c..ce613ac38 100644 --- a/include/asm-m68k/byteorder.h +++ b/include/asm-m68k/byteorder.h @@ -1,107 +1,7 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - #ifndef _M68K_BYTEORDER_H #define _M68K_BYTEORDER_H #include - -#ifdef __GNUC__ -#define __sw16(x) \ - ((__u16)( \ - (((__u16)(x) & (__u16)0x00ffU) << 8) | \ - (((__u16)(x) & (__u16)0xff00U) >> 8) )) -#define __sw32(x) \ - ((__u32)( \ - (((__u32)(x)) << 24) | \ - (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ - (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ - (((__u32)(x)) >> 24) )) - -extern __inline__ unsigned ld_le16(const volatile unsigned short *addr) -{ - unsigned result = *addr; - return __sw16(result); -} - -extern __inline__ void st_le16(volatile unsigned short *addr, - const unsigned val) -{ - *addr = __sw16(val); -} - -extern __inline__ unsigned ld_le32(const volatile unsigned *addr) -{ - unsigned result = *addr; - return __sw32(result); -} - -extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) -{ - *addr = __sw32(val); -} - -#if 0 -/* alas, egcs sounds like it has a bug in this code that doesn't use the - inline asm correctly, and can cause file corruption. Until I hear that - it's fixed, I can live without the extra speed. I hope. */ -#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90) -#if 0 -# define __arch_swab16(x) ld_le16(&x) -# define __arch_swab32(x) ld_le32(&x) -#else -static __inline__ __attribute__ ((const)) -__u16 ___arch__swab16(__u16 value) -{ - return __sw16(value); -} - -static __inline__ __attribute__ ((const)) -__u32 ___arch__swab32(__u32 value) -{ - return __sw32(value); -} - -#define __arch__swab32(x) ___arch__swab32(x) -#define __arch__swab16(x) ___arch__swab16(x) -#endif /* 0 */ - -#endif - -/* The same, but returns converted value from the location pointer by addr. */ -#define __arch__swab16p(addr) ld_le16(addr) -#define __arch__swab32p(addr) ld_le32(addr) - -/* The same, but do the conversion in situ, ie. put the value back to addr. */ -#define __arch__swab16s(addr) st_le16(addr,*addr) -#define __arch__swab32s(addr) st_le32(addr,*addr) -#endif - -#endif /* __GNUC__ */ - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -#define __BYTEORDER_HAS_U64__ -#endif #include -#endif /* _M68K_BYTEORDER_H */ +#endif /* _M68K_BYTEORDER_H */ diff --git a/include/asm-m68k/fec.h b/include/asm-m68k/fec.h index e63959902..5bbbfb245 100644 --- a/include/asm-m68k/fec.h +++ b/include/asm-m68k/fec.h @@ -5,10 +5,6 @@ * MPC8xx Communication Processor Module. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) * - * Add FEC Structure and definitions - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * * See file CREDITS for list of people who contributed to this * project. * @@ -34,59 +30,51 @@ /* Buffer descriptors used FEC. */ typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ +#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ /* Buffer descriptor control/status used by Ethernet receive. */ #define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_RO1 ((ushort)0x4000) #define BD_ENET_RX_WRAP ((ushort)0x2000) #define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_RO2 BD_ENET_RX_INTR #define BD_ENET_RX_LAST ((ushort)0x0800) #define BD_ENET_RX_FIRST ((ushort)0x0400) #define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_BC ((ushort)0x0080) -#define BD_ENET_RX_MC ((ushort)0x0040) #define BD_ENET_RX_LG ((ushort)0x0020) #define BD_ENET_RX_NO ((ushort)0x0010) #define BD_ENET_RX_SH ((ushort)0x0008) #define BD_ENET_RX_CR ((ushort)0x0004) #define BD_ENET_RX_OV ((ushort)0x0002) #define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_TR BD_ENET_RX_CL #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ /* Buffer descriptor control/status used by Ethernet transmit. */ #define BD_ENET_TX_READY ((ushort)0x8000) #define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_TO1 BD_ENET_TX_PAD #define BD_ENET_TX_WRAP ((ushort)0x2000) #define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_ #define BD_ENET_TX_LAST ((ushort)0x0800) #define BD_ENET_TX_TC ((ushort)0x0400) #define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_ABC BD_ENET_TX_DEF #define BD_ENET_TX_HB ((ushort)0x0100) #define BD_ENET_TX_LC ((ushort)0x0080) #define BD_ENET_TX_RL ((ushort)0x0040) @@ -95,260 +83,4 @@ typedef struct cpm_buf_desc { #define BD_ENET_TX_CSL ((ushort)0x0001) #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ -/********************************************************************* -* Fast Ethernet Controller (FEC) -*********************************************************************/ -/* FEC private information */ -struct fec_info_s { - int index; - u32 iobase; - u32 pinmux; - u32 miibase; - int phy_addr; - int dup_spd; - char *phy_name; - int phyname_init; - cbd_t *rxbd; /* Rx BD */ - cbd_t *txbd; /* Tx BD */ - uint rxIdx; - uint txIdx; - char *txbuf; - int initialized; - struct fec_info_s *next; -}; - -#ifdef CONFIG_MCFFEC -/* Register read/write struct */ -typedef struct fec { -#ifdef CONFIG_M5272 - u32 ecr; /* 0x00 */ - u32 eir; /* 0x04 */ - u32 eimr; /* 0x08 */ - u32 ivsr; /* 0x0C */ - u32 rdar; /* 0x10 */ - u32 tdar; /* 0x14 */ - u8 resv1[0x28]; /* 0x18 */ - u32 mmfr; /* 0x40 */ - u32 mscr; /* 0x44 */ - u8 resv2[0x44]; /* 0x48 */ - u32 frbr; /* 0x8C */ - u32 frsr; /* 0x90 */ - u8 resv3[0x10]; /* 0x94 */ - u32 tfwr; /* 0xA4 */ - u32 res4; /* 0xA8 */ - u32 tfsr; /* 0xAC */ - u8 resv4[0x50]; /* 0xB0 */ - u32 opd; /* 0x100 - dummy */ - u32 rcr; /* 0x104 */ - u32 mibc; /* 0x108 */ - u8 resv5[0x38]; /* 0x10C */ - u32 tcr; /* 0x144 */ - u8 resv6[0x270]; /* 0x148 */ - u32 iaur; /* 0x3B8 - dummy */ - u32 ialr; /* 0x3BC - dummy */ - u32 palr; /* 0x3C0 */ - u32 paur; /* 0x3C4 */ - u32 gaur; /* 0x3C8 */ - u32 galr; /* 0x3CC */ - u32 erdsr; /* 0x3D0 */ - u32 etdsr; /* 0x3D4 */ - u32 emrbr; /* 0x3D8 */ - u8 resv12[0x74]; /* 0x18C */ -#else - u8 resv0[0x4]; - u32 eir; - u32 eimr; - u8 resv1[0x4]; - u32 rdar; - u32 tdar; - u8 resv2[0xC]; - u32 ecr; - u8 resv3[0x18]; - u32 mmfr; - u32 mscr; - u8 resv4[0x1C]; - u32 mibc; - u8 resv5[0x1C]; - u32 rcr; - u8 resv6[0x3C]; - u32 tcr; - u8 resv7[0x1C]; - u32 palr; - u32 paur; - u32 opd; - u8 resv8[0x28]; - u32 iaur; - u32 ialr; - u32 gaur; - u32 galr; - u8 resv9[0x1C]; - u32 tfwr; - u8 resv10[0x4]; - u32 frbr; - u32 frsr; - u8 resv11[0x2C]; - u32 erdsr; - u32 etdsr; - u32 emrbr; - u8 resv12[0x74]; -#endif - - u32 rmon_t_drop; - u32 rmon_t_packets; - u32 rmon_t_bc_pkt; - u32 rmon_t_mc_pkt; - u32 rmon_t_crc_align; - u32 rmon_t_undersize; - u32 rmon_t_oversize; - u32 rmon_t_frag; - u32 rmon_t_jab; - u32 rmon_t_col; - u32 rmon_t_p64; - u32 rmon_t_p65to127; - u32 rmon_t_p128to255; - u32 rmon_t_p256to511; - u32 rmon_t_p512to1023; - u32 rmon_t_p1024to2047; - u32 rmon_t_p_gte2048; - u32 rmon_t_octets; - - u32 ieee_t_drop; - u32 ieee_t_frame_ok; - u32 ieee_t_1col; - u32 ieee_t_mcol; - u32 ieee_t_def; - u32 ieee_t_lcol; - u32 ieee_t_excol; - u32 ieee_t_macerr; - u32 ieee_t_cserr; - u32 ieee_t_sqe; - u32 ieee_t_fdxfc; - u32 ieee_t_octets_ok; - u8 resv13[0x8]; - - u32 rmon_r_drop; - u32 rmon_r_packets; - u32 rmon_r_bc_pkt; - u32 rmon_r_mc_pkt; - u32 rmon_r_crc_align; - u32 rmon_r_undersize; - u32 rmon_r_oversize; - u32 rmon_r_frag; - u32 rmon_r_jab; - u32 rmon_r_resvd_0; - u32 rmon_r_p64; - u32 rmon_r_p65to127; - u32 rmon_r_p128to255; - u32 rmon_r_p256to511; - u32 rmon_r_p512to1023; - u32 rmon_r_p1024to2047; - u32 rmon_r_p_gte2048; - u32 rmon_r_octets; - - u32 ieee_r_drop; - u32 ieee_r_frame_ok; - u32 ieee_r_crc; - u32 ieee_r_align; - u32 ieee_r_macerr; - u32 ieee_r_fdxfc; - u32 ieee_r_octets_ok; -} fec_t; -#endif /* CONFIG_MCFFEC */ - -/********************************************************************* -* Fast Ethernet Controller (FEC) -*********************************************************************/ -/* Bit definitions and macros for FEC_EIR */ -#define FEC_EIR_CLEAR_ALL (0xFFF80000) -#define FEC_EIR_HBERR (0x80000000) -#define FEC_EIR_BABR (0x40000000) -#define FEC_EIR_BABT (0x20000000) -#define FEC_EIR_GRA (0x10000000) -#define FEC_EIR_TXF (0x08000000) -#define FEC_EIR_TXB (0x04000000) -#define FEC_EIR_RXF (0x02000000) -#define FEC_EIR_RXB (0x01000000) -#define FEC_EIR_MII (0x00800000) -#define FEC_EIR_EBERR (0x00400000) -#define FEC_EIR_LC (0x00200000) -#define FEC_EIR_RL (0x00100000) -#define FEC_EIR_UN (0x00080000) - -/* Bit definitions and macros for FEC_RDAR */ -#define FEC_RDAR_R_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for FEC_TDAR */ -#define FEC_TDAR_X_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for FEC_ECR */ -#define FEC_ECR_ETHER_EN (0x00000002) -#define FEC_ECR_RESET (0x00000001) - -/* Bit definitions and macros for FEC_MMFR */ -#define FEC_MMFR_DATA(x) (((x)&0xFFFF)) -#define FEC_MMFR_ST(x) (((x)&0x03)<<30) -#define FEC_MMFR_ST_01 (0x40000000) -#define FEC_MMFR_OP_RD (0x20000000) -#define FEC_MMFR_OP_WR (0x10000000) -#define FEC_MMFR_PA(x) (((x)&0x1F)<<23) -#define FEC_MMFR_RA(x) (((x)&0x1F)<<18) -#define FEC_MMFR_TA(x) (((x)&0x03)<<16) -#define FEC_MMFR_TA_10 (0x00020000) - -/* Bit definitions and macros for FEC_MSCR */ -#define FEC_MSCR_DIS_PREAMBLE (0x00000080) -#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1) - -/* Bit definitions and macros for FEC_MIBC */ -#define FEC_MIBC_MIB_DISABLE (0x80000000) -#define FEC_MIBC_MIB_IDLE (0x40000000) - -/* Bit definitions and macros for FEC_RCR */ -#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16) -#define FEC_RCR_FCE (0x00000020) -#define FEC_RCR_BC_REJ (0x00000010) -#define FEC_RCR_PROM (0x00000008) -#define FEC_RCR_MII_MODE (0x00000004) -#define FEC_RCR_DRT (0x00000002) -#define FEC_RCR_LOOP (0x00000001) - -/* Bit definitions and macros for FEC_TCR */ -#define FEC_TCR_RFC_PAUSE (0x00000010) -#define FEC_TCR_TFC_PAUSE (0x00000008) -#define FEC_TCR_FDEN (0x00000004) -#define FEC_TCR_HBC (0x00000002) -#define FEC_TCR_GTS (0x00000001) - -/* Bit definitions and macros for FEC_PAUR */ -#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16) -#define FEC_PAUR_TYPE(x) ((x)&0xFFFF) - -/* Bit definitions and macros for FEC_OPD */ -#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) -#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for FEC_TFWR */ -#define FEC_TFWR_X_WMRK(x) ((x)&0x03) -#define FEC_TFWR_X_WMRK_64 (0x01) -#define FEC_TFWR_X_WMRK_128 (0x02) -#define FEC_TFWR_X_WMRK_192 (0x03) - -/* Bit definitions and macros for FEC_FRBR */ -#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2) - -/* Bit definitions and macros for FEC_FRSR */ -#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2) - -/* Bit definitions and macros for FEC_ERDSR */ -#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for FEC_ETDSR */ -#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for FEC_EMRBR */ -#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4) - -#define FEC_RESET_DELAY 100 -#define FEC_RX_TOUT 100 - -#endif /* fec_h */ +#endif /* fec_h */ diff --git a/include/asm-m68k/global_data.h b/include/asm-m68k/global_data.h index 10c693153..f68352f12 100644 --- a/include/asm-m68k/global_data.h +++ b/include/asm-m68k/global_data.h @@ -39,27 +39,12 @@ typedef struct global_data { unsigned long baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; -#ifdef CONFIG_PCI - unsigned long pci_clk; -#endif -#ifdef CONFIG_EXTRA_CLOCK - unsigned long inp_clk; - unsigned long vco_clk; - unsigned long flb_clk; -#endif -#ifdef CONFIG_FSL_I2C - unsigned long i2c1_clk; - unsigned long i2c2_clk; -#endif - phys_size_t ram_size; /* RAM size */ + unsigned long ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long reset_status; /* reset status register at boot */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long have_console; /* serial_init() was called */ -#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) - unsigned long fb_base; /* Base addr of framebuffer memory */ -#endif #ifdef CONFIG_BOARD_TYPES unsigned long board_type; #endif @@ -72,9 +57,6 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #if 0 extern gd_t *global_data; diff --git a/include/asm-m68k/immap_5249.h b/include/asm-m68k/immap_5249.h index 6c6fbcce4..a2c127182 100644 --- a/include/asm-m68k/immap_5249.h +++ b/include/asm-m68k/immap_5249.h @@ -25,11 +25,19 @@ #ifndef __IMMAP_5249__ #define __IMMAP_5249__ -#define MMAP_INTC (CFG_MBAR + 0x00000040) -#define MMAP_DTMR0 (CFG_MBAR + 0x00000140) -#define MMAP_DTMR1 (CFG_MBAR + 0x00000180) -#define MMAP_UART0 (CFG_MBAR + 0x000001C0) -#define MMAP_UART1 (CFG_MBAR + 0x00000200) -#define MMAP_QSPI (CFG_MBAR + 0x00000400) +/* Timer module registers + */ +typedef struct timer_ctrl { + ushort timer_tmr; + ushort res1; + ushort timer_trr; + ushort res2; + ushort timer_tcap; + ushort res3; + ushort timer_tcn; + ushort res4; + ushort timer_ter; + uchar res5[14]; +} timer_t; -#endif /* __IMMAP_5249__ */ +#endif /* __IMMAP_5249__ */ diff --git a/include/asm-m68k/immap_5271.h b/include/asm-m68k/immap_5271.h index d9dc01591..424dc1d1f 100644 --- a/include/asm-m68k/immap_5271.h +++ b/include/asm-m68k/immap_5271.h @@ -26,73 +26,73 @@ #ifndef __IMMAP_5271__ #define __IMMAP_5271__ -#define MMAP_SCM (CFG_MBAR + 0x00000000) -#define MMAP_SDRAM (CFG_MBAR + 0x00000040) -#define MMAP_FBCS (CFG_MBAR + 0x00000080) -#define MMAP_DMA0 (CFG_MBAR + 0x00000100) -#define MMAP_DMA1 (CFG_MBAR + 0x00000110) -#define MMAP_DMA2 (CFG_MBAR + 0x00000120) -#define MMAP_DMA3 (CFG_MBAR + 0x00000130) -#define MMAP_UART0 (CFG_MBAR + 0x00000200) -#define MMAP_UART1 (CFG_MBAR + 0x00000240) -#define MMAP_UART2 (CFG_MBAR + 0x00000280) -#define MMAP_I2C (CFG_MBAR + 0x00000300) -#define MMAP_QSPI (CFG_MBAR + 0x00000340) -#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) -#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) -#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) -#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) -#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) -#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) -#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) -#define MMAP_FEC (CFG_MBAR + 0x00001000) -#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) -#define MMAP_GPIO (CFG_MBAR + 0x00100000) -#define MMAP_CCM (CFG_MBAR + 0x00110000) -#define MMAP_PLL (CFG_MBAR + 0x00120000) -#define MMAP_EPORT (CFG_MBAR + 0x00130000) -#define MMAP_WDOG (CFG_MBAR + 0x00140000) -#define MMAP_PIT0 (CFG_MBAR + 0x00150000) -#define MMAP_PIT1 (CFG_MBAR + 0x00160000) -#define MMAP_PIT2 (CFG_MBAR + 0x00170000) -#define MMAP_PIT3 (CFG_MBAR + 0x00180000) -#define MMAP_MDHA (CFG_MBAR + 0x00190000) -#define MMAP_RNG (CFG_MBAR + 0x001A0000) -#define MMAP_SKHA (CFG_MBAR + 0x001B0000) -#define MMAP_CAN1 (CFG_MBAR + 0x001C0000) -#define MMAP_ETPU (CFG_MBAR + 0x001D0000) -#define MMAP_CAN2 (CFG_MBAR + 0x001F0000) +/* Interrupt module registers +*/ +typedef struct int_ctrl { + uint int_icr1; + uint int_icr2; + uint int_icr3; + uint int_icr4; + uint int_isr; + uint int_pitr; + uint int_piwr; + uchar res1[3]; + uchar int_pivr; +} intctrl_t; -/* Interrupt module registers */ -typedef struct int0_ctrl { - /* Interrupt Controller 0 */ - u32 iprh0; /* 0x00 Pending Register High */ - u32 iprl0; /* 0x04 Pending Register Low */ - u32 imrh0; /* 0x08 Mask Register High */ - u32 imrl0; /* 0x0C Mask Register Low */ - u32 frch0; /* 0x10 Force Register High */ - u32 frcl0; /* 0x14 Force Register Low */ - u8 irlr; /* 0x18 */ - u8 iacklpr; /* 0x19 */ - u16 res1[19]; /* 0x1a - 0x3c */ - u8 icr0[64]; /* 0x40 - 0x7F Control registers */ - u32 res3[24]; /* 0x80 - 0xDF */ - u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ - u8 res4[3]; /* 0xE1 - 0xE3 */ - u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ - u8 res5[3]; /* 0xE5 - 0xE7 */ - u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ - u8 res6[3]; /* 0xE9 - 0xEB */ - u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ - u8 res7[3]; /* 0xED - 0xEF */ - u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ - u8 res8[3]; /* 0xF1 - 0xF3 */ - u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ - u8 res9[3]; /* 0xF5 - 0xF7 */ - u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ - u8 resa[3]; /* 0xF9 - 0xFB */ - u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ - u8 resb[3]; /* 0xFD - 0xFF */ -} int0_t; +/* Timer module registers + */ +typedef struct timer_ctrl { + ushort timer_tmr; + ushort res1; + ushort timer_trr; + ushort res2; + ushort timer_tcap; + ushort res3; + ushort timer_tcn; + ushort res4; + ushort timer_ter; + uchar res5[14]; +} timer_t; -#endif /* __IMMAP_5271__ */ + /* Fast ethernet controller registers + */ +typedef struct fec { + uint res1; + uint fec_ievent; + uint fec_imask; + uint res2; + uint fec_r_des_active; + uint fec_x_des_active; + uint res3[3]; + uint fec_ecntrl; + uint res4[6]; + uint fec_mii_data; + uint fec_mii_speed; + uint res5[7]; + uint fec_mibc; + uint res6[7]; + uint fec_r_cntrl; + uint res7[15]; + uint fec_x_cntrl; + uint res8[7]; + uint fec_addr_low; + uint fec_addr_high; + uint fec_opd; + uint res9[10]; + uint fec_ihash_table_high; + uint fec_ihash_table_low; + uint fec_ghash_table_high; + uint fec_ghash_table_low; + uint res10[7]; + uint fec_tfwr; + uint res11; + uint fec_r_bound; + uint fec_r_fstart; + uint res12[11]; + uint fec_r_des_start; + uint fec_x_des_start; + uint fec_r_buff_size; +} fec_t; + +#endif /* __IMMAP_5271__ */ diff --git a/include/asm-m68k/immap_5272.h b/include/asm-m68k/immap_5272.h index 2ebb140b0..ecb4906f3 100644 --- a/include/asm-m68k/immap_5272.h +++ b/include/asm-m68k/immap_5272.h @@ -25,326 +25,423 @@ #ifndef __IMMAP_5272__ #define __IMMAP_5272__ -#define MMAP_CFG (CFG_MBAR + 0x00000000) -#define MMAP_INTC (CFG_MBAR + 0x00000020) -#define MMAP_FBCS (CFG_MBAR + 0x00000040) -#define MMAP_GPIO (CFG_MBAR + 0x00000080) -#define MMAP_QSPI (CFG_MBAR + 0x000000A0) -#define MMAP_PWM (CFG_MBAR + 0x000000C0) -#define MMAP_DMA0 (CFG_MBAR + 0x000000E0) -#define MMAP_UART0 (CFG_MBAR + 0x00000100) -#define MMAP_UART1 (CFG_MBAR + 0x00000140) -#define MMAP_SDRAM (CFG_MBAR + 0x00000180) -#define MMAP_TMR0 (CFG_MBAR + 0x00000200) -#define MMAP_TMR1 (CFG_MBAR + 0x00000220) -#define MMAP_TMR2 (CFG_MBAR + 0x00000240) -#define MMAP_TMR3 (CFG_MBAR + 0x00000260) -#define MMAP_WDOG (CFG_MBAR + 0x00000280) -#define MMAP_PLIC (CFG_MBAR + 0x00000300) -#define MMAP_FEC (CFG_MBAR + 0x00000840) -#define MMAP_USB (CFG_MBAR + 0x00001000) - -/* System configuration registers */ -typedef struct sys_ctrl { - uint sc_mbar; - ushort sc_scr; - ushort sc_spr; - uint sc_pmr; - char res1[2]; - ushort sc_alpr; - uint sc_dir; - char res2[12]; +/* System configuration registers +*/ +typedef struct sys_ctrl { + uint sc_mbar; + ushort sc_scr; + ushort sc_spr; + uint sc_pmr; + char res1[2]; + ushort sc_alpr; + uint sc_dir; + char res2[12]; } sysctrl_t; -/* Interrupt module registers */ +/* Interrupt module registers +*/ typedef struct int_ctrl { - uint int_icr1; - uint int_icr2; - uint int_icr3; - uint int_icr4; - uint int_isr; - uint int_pitr; - uint int_piwr; - uchar res1[3]; - uchar int_pivr; + uint int_icr1; + uint int_icr2; + uint int_icr3; + uint int_icr4; + uint int_isr; + uint int_pitr; + uint int_piwr; + uchar res1[3]; + uchar int_pivr; } intctrl_t; -/* Chip select module registers */ -typedef struct cs_ctlr { - uint cs_br0; - uint cs_or0; - uint cs_br1; - uint cs_or1; - uint cs_br2; - uint cs_or2; - uint cs_br3; - uint cs_or3; - uint cs_br4; - uint cs_or4; - uint cs_br5; - uint cs_or5; - uint cs_br6; - uint cs_or6; - uint cs_br7; - uint cs_or7; +/* Chip select module registers. +*/ +typedef struct cs_ctlr { + uint cs_br0; + uint cs_or0; + uint cs_br1; + uint cs_or1; + uint cs_br2; + uint cs_or2; + uint cs_br3; + uint cs_or3; + uint cs_br4; + uint cs_or4; + uint cs_br5; + uint cs_or5; + uint cs_br6; + uint cs_or6; + uint cs_br7; + uint cs_or7; } csctrl_t; -/* GPIO port registers */ -typedef struct gpio_ctrl { - uint gpio_pacnt; - ushort gpio_paddr; - ushort gpio_padat; - uint gpio_pbcnt; - ushort gpio_pbddr; - ushort gpio_pbdat; - uchar res1[4]; - ushort gpio_pcddr; - ushort gpio_pcdat; - uint gpio_pdcnt; - uchar res2[4]; +/* GPIO port registers +*/ +typedef struct gpio_ctrl { + uint gpio_pacnt; + ushort gpio_paddr; + ushort gpio_padat; + uint gpio_pbcnt; + ushort gpio_pbddr; + ushort gpio_pbdat; + uchar res1[4]; + ushort gpio_pcddr; + ushort gpio_pcdat; + uint gpio_pdcnt; + uchar res2[4]; } gpio_t; -/* QSPI module registers */ -typedef struct qspi_ctrl { - ushort qspi_qmr; - uchar res1[2]; - ushort qspi_qdlyr; - uchar res2[2]; - ushort qspi_qwr; - uchar res3[2]; - ushort qspi_qir; - uchar res4[2]; - ushort qspi_qar; - uchar res5[2]; - ushort qspi_qdr; - uchar res6[10]; +/* QSPI module registers + */ +typedef struct qspi_ctrl { + ushort qspi_qmr; + uchar res1[2]; + ushort qspi_qdlyr; + uchar res2[2]; + ushort qspi_qwr; + uchar res3[2]; + ushort qspi_qir; + uchar res4[2]; + ushort qspi_qar; + uchar res5[2]; + ushort qspi_qdr; + uchar res6[10]; } qspi_t; -/* PWM module registers */ -typedef struct pwm_ctrl { - uchar pwm_pwcr0; - uchar res1[3]; - uchar pwm_pwcr1; - uchar res2[3]; - uchar pwm_pwcr2; - uchar res3[7]; - uchar pwm_pwwd0; - uchar res4[3]; - uchar pwm_pwwd1; - uchar res5[3]; - uchar pwm_pwwd2; - uchar res6[7]; +/* PWM module registers + */ +typedef struct pwm_ctrl { + uchar pwm_pwcr0; + uchar res1[3]; + uchar pwm_pwcr1; + uchar res2[3]; + uchar pwm_pwcr2; + uchar res3[7]; + uchar pwm_pwwd0; + uchar res4[3]; + uchar pwm_pwwd1; + uchar res5[3]; + uchar pwm_pwwd2; + uchar res6[7]; } pwm_t; -/* DMA module registers */ -typedef struct dma_ctrl { - ulong dma_dmr; - uchar res1[2]; - ushort dma_dir; - ulong dma_dbcr; - ulong dma_dsar; - ulong dma_ddar; - uchar res2[12]; +/* DMA module registers + */ +typedef struct dma_ctrl { + ulong dma_dmr; + uchar res1[2]; + ushort dma_dir; + ulong dma_dbcr; + ulong dma_dsar; + ulong dma_ddar; + uchar res2[12]; } dma_t; -/* SDRAM controller registers, offset: 0x180 */ +/* UART module registers + */ +typedef struct uart_ctrl { + uchar uart_umr; + uchar res1[3]; + uchar uart_usr_ucsr; + uchar res2[3]; + uchar uart_ucr; + uchar res3[3]; + uchar uart_urb_utb; + uchar res4[3]; + uchar uart_uipcr_uacr; + uchar res5[3]; + uchar uart_uisr_uimr; + uchar res6[3]; + uchar uart_udu; + uchar res7[3]; + uchar uart_udl; + uchar res8[3]; + uchar uart_uabu; + uchar res9[3]; + uchar uart_uabl; + uchar res10[3]; + uchar uart_utf; + uchar res11[3]; + uchar uart_urf; + uchar res12[3]; + uchar uart_ufpd; + uchar res13[3]; + uchar uart_uip; + uchar res14[3]; + uchar uart_uop1; + uchar res15[3]; + uchar uart_uop0; + uchar res16[3]; +} uart_t; + +/* SDRAM controller registers, offset: 0x180 + */ typedef struct sdram_ctrl { - uchar res1[2]; - ushort sdram_sdcr; - uchar res2[2]; - ushort sdram_sdtr; - uchar res3[120]; + uchar res1[2]; + ushort sdram_sdcr; + uchar res2[2]; + ushort sdram_sdtr; + uchar res3[120]; } sdramctrl_t; -/* Watchdog registers */ +/* Timer module registers + */ +typedef struct timer_ctrl { + ushort timer_tmr; + ushort res1; + ushort timer_trr; + ushort res2; + ushort timer_tcap; + ushort res3; + ushort timer_tcn; + ushort res4; + ushort timer_ter; + uchar res5[14]; +} timer_t; + +/* Watchdog registers + */ typedef struct wdog_ctrl { - ushort wdog_wrrr; - ushort res1; - ushort wdog_wirr; - ushort res2; - ushort wdog_wcr; - ushort res3; - ushort wdog_wer; - uchar res4[114]; + ushort wdog_wrrr; + ushort res1; + ushort wdog_wirr; + ushort res2; + ushort wdog_wcr; + ushort res3; + ushort wdog_wer; + uchar res4[114]; } wdog_t; -/* PLIC module registers */ +/* PLIC module registers + */ typedef struct plic_ctrl { - ulong plic_p0b1rr; - ulong plic_p1b1rr; - ulong plic_p2b1rr; - ulong plic_p3b1rr; - ulong plic_p0b2rr; - ulong plic_p1b2rr; - ulong plic_p2b2rr; - ulong plic_p3b2rr; - uchar plic_p0drr; - uchar plic_p1drr; - uchar plic_p2drr; - uchar plic_p3drr; - uchar res1[4]; - ulong plic_p0b1tr; - ulong plic_p1b1tr; - ulong plic_p2b1tr; - ulong plic_p3b1tr; - ulong plic_p0b2tr; - ulong plic_p1b2tr; - ulong plic_p2b2tr; - ulong plic_p3b2tr; - uchar plic_p0dtr; - uchar plic_p1dtr; - uchar plic_p2dtr; - uchar plic_p3dtr; - uchar res2[4]; - ushort plic_p0cr; - ushort plic_p1cr; - ushort plic_p2cr; - ushort plic_p3cr; - ushort plic_p0icr; - ushort plic_p1icr; - ushort plic_p2icr; - ushort plic_p3icr; - ushort plic_p0gmr; - ushort plic_p1gmr; - ushort plic_p2gmr; - ushort plic_p3gmr; - ushort plic_p0gmt; - ushort plic_p1gmt; - ushort plic_p2gmt; - ushort plic_p3gmt; - uchar res3; - uchar plic_pgmts; - uchar plic_pgmta; - uchar res4; - uchar plic_p0gcir; - uchar plic_p1gcir; - uchar plic_p2gcir; - uchar plic_p3gcir; - uchar plic_p0gcit; - uchar plic_p1gcit; - uchar plic_p2gcit; - uchar plic_p3gcit; - uchar res5[3]; - uchar plic_pgcitsr; - uchar res6[3]; - uchar plic_pdcsr; - ushort plic_p0psr; - ushort plic_p1psr; - ushort plic_p2psr; - ushort plic_p3psr; - ushort plic_pasr; - uchar res7; - uchar plic_plcr; - ushort res8; - ushort plic_pdrqr; - ushort plic_p0sdr; - ushort plic_p1sdr; - ushort plic_p2sdr; - ushort plic_p3sdr; - ushort res9; - ushort plic_pcsr; - uchar res10[1184]; + ulong plic_p0b1rr; + ulong plic_p1b1rr; + ulong plic_p2b1rr; + ulong plic_p3b1rr; + ulong plic_p0b2rr; + ulong plic_p1b2rr; + ulong plic_p2b2rr; + ulong plic_p3b2rr; + uchar plic_p0drr; + uchar plic_p1drr; + uchar plic_p2drr; + uchar plic_p3drr; + uchar res1[4]; + ulong plic_p0b1tr; + ulong plic_p1b1tr; + ulong plic_p2b1tr; + ulong plic_p3b1tr; + ulong plic_p0b2tr; + ulong plic_p1b2tr; + ulong plic_p2b2tr; + ulong plic_p3b2tr; + uchar plic_p0dtr; + uchar plic_p1dtr; + uchar plic_p2dtr; + uchar plic_p3dtr; + uchar res2[4]; + ushort plic_p0cr; + ushort plic_p1cr; + ushort plic_p2cr; + ushort plic_p3cr; + ushort plic_p0icr; + ushort plic_p1icr; + ushort plic_p2icr; + ushort plic_p3icr; + ushort plic_p0gmr; + ushort plic_p1gmr; + ushort plic_p2gmr; + ushort plic_p3gmr; + ushort plic_p0gmt; + ushort plic_p1gmt; + ushort plic_p2gmt; + ushort plic_p3gmt; + uchar res3; + uchar plic_pgmts; + uchar plic_pgmta; + uchar res4; + uchar plic_p0gcir; + uchar plic_p1gcir; + uchar plic_p2gcir; + uchar plic_p3gcir; + uchar plic_p0gcit; + uchar plic_p1gcit; + uchar plic_p2gcit; + uchar plic_p3gcit; + uchar res5[3]; + uchar plic_pgcitsr; + uchar res6[3]; + uchar plic_pdcsr; + ushort plic_p0psr; + ushort plic_p1psr; + ushort plic_p2psr; + ushort plic_p3psr; + ushort plic_pasr; + uchar res7; + uchar plic_plcr; + ushort res8; + ushort plic_pdrqr; + ushort plic_p0sdr; + ushort plic_p1sdr; + ushort plic_p2sdr; + ushort plic_p3sdr; + ushort res9; + ushort plic_pcsr; + uchar res10[1184]; } plic_t; -/* USB module registers */ +/* Fast ethernet controller registers + */ +typedef struct fec { + uint fec_ecntrl; /* ethernet control register */ + uint fec_ievent; /* interrupt event register */ + uint fec_imask; /* interrupt mask register */ + uint fec_ivec; /* interrupt level and vector status */ + uint fec_r_des_active; /* Rx ring updated flag */ + uint fec_x_des_active; /* Tx ring updated flag */ + uint res3[10]; /* reserved */ + uint fec_mii_data; /* MII data register */ + uint fec_mii_speed; /* MII speed control register */ + uint res4[17]; /* reserved */ + uint fec_r_bound; /* end of RAM (read-only) */ + uint fec_r_fstart; /* Rx FIFO start address */ + uint res5[6]; /* reserved */ + uint fec_x_fstart; /* Tx FIFO start address */ + uint res7[21]; /* reserved */ + uint fec_r_cntrl; /* Rx control register */ + uint fec_r_hash; /* Rx hash register */ + uint res8[14]; /* reserved */ + uint fec_x_cntrl; /* Tx control register */ + uint res9[0x9e]; /* reserved */ + uint fec_addr_low; /* lower 32 bits of station address */ + uint fec_addr_high; /* upper 16 bits of station address */ + uint fec_hash_table_high; /* upper 32-bits of hash table */ + uint fec_hash_table_low; /* lower 32-bits of hash table */ + uint fec_r_des_start; /* beginning of Rx descriptor ring */ + uint fec_x_des_start; /* beginning of Tx descriptor ring */ + uint fec_r_buff_size; /* Rx buffer size */ + uint res2[9]; /* reserved */ + uchar fec_fifo[960]; /* fifo RAM */ +} fec_t; + +/* USB module registers +*/ typedef struct usb { - ushort res1; - ushort usb_fnr; - ushort res2; - ushort usb_fnmr; - ushort res3; - ushort usb_rfmr; - ushort res4; - ushort usb_rfmmr; - uchar res5[3]; - uchar usb_far; - ulong usb_asr; - ulong usb_drr1; - ulong usb_drr2; - ushort res6; - ushort usb_specr; - ushort res7; - ushort usb_ep0sr; - ulong usb_iep0cfg; - ulong usb_oep0cfg; - ulong usb_ep1cfg; - ulong usb_ep2cfg; - ulong usb_ep3cfg; - ulong usb_ep4cfg; - ulong usb_ep5cfg; - ulong usb_ep6cfg; - ulong usb_ep7cfg; - ulong usb_ep0ctl; - ushort res8; - ushort usb_ep1ctl; - ushort res9; - ushort usb_ep2ctl; - ushort res10; - ushort usb_ep3ctl; - ushort res11; - ushort usb_ep4ctl; - ushort res12; - ushort usb_ep5ctl; - ushort res13; - ushort usb_ep6ctl; - ushort res14; - ushort usb_ep7ctl; - ulong usb_ep0isr; - ushort res15; - ushort usb_ep1isr; - ushort res16; - ushort usb_ep2isr; - ushort res17; - ushort usb_ep3isr; - ushort res18; - ushort usb_ep4isr; - ushort res19; - ushort usb_ep5isr; - ushort res20; - ushort usb_ep6isr; - ushort res21; - ushort usb_ep7isr; - ulong usb_ep0imr; - ushort res22; - ushort usb_ep1imr; - ushort res23; - ushort usb_ep2imr; - ushort res24; - ushort usb_ep3imr; - ushort res25; - ushort usb_ep4imr; - ushort res26; - ushort usb_ep5imr; - ushort res27; - ushort usb_ep6imr; - ushort res28; - ushort usb_ep7imr; - ulong usb_ep0dr; - ulong usb_ep1dr; - ulong usb_ep2dr; - ulong usb_ep3dr; - ulong usb_ep4dr; - ulong usb_ep5dr; - ulong usb_ep6dr; - ulong usb_ep7dr; - ushort res29; - ushort usb_ep0dpr; - ushort res30; - ushort usb_ep1dpr; - ushort res31; - ushort usb_ep2dpr; - ushort res32; - ushort usb_ep3dpr; - ushort res33; - ushort usb_ep4dpr; - ushort res34; - ushort usb_ep5dpr; - ushort res35; - ushort usb_ep6dpr; - ushort res36; - ushort usb_ep7dpr; - uchar res37[788]; - uchar usb_cfgram[1024]; + ushort res1; + ushort usb_fnr; + ushort res2; + ushort usb_fnmr; + ushort res3; + ushort usb_rfmr; + ushort res4; + ushort usb_rfmmr; + uchar res5[3]; + uchar usb_far; + ulong usb_asr; + ulong usb_drr1; + ulong usb_drr2; + ushort res6; + ushort usb_specr; + ushort res7; + ushort usb_ep0sr; + ulong usb_iep0cfg; + ulong usb_oep0cfg; + ulong usb_ep1cfg; + ulong usb_ep2cfg; + ulong usb_ep3cfg; + ulong usb_ep4cfg; + ulong usb_ep5cfg; + ulong usb_ep6cfg; + ulong usb_ep7cfg; + ulong usb_ep0ctl; + ushort res8; + ushort usb_ep1ctl; + ushort res9; + ushort usb_ep2ctl; + ushort res10; + ushort usb_ep3ctl; + ushort res11; + ushort usb_ep4ctl; + ushort res12; + ushort usb_ep5ctl; + ushort res13; + ushort usb_ep6ctl; + ushort res14; + ushort usb_ep7ctl; + ulong usb_ep0isr; + ushort res15; + ushort usb_ep1isr; + ushort res16; + ushort usb_ep2isr; + ushort res17; + ushort usb_ep3isr; + ushort res18; + ushort usb_ep4isr; + ushort res19; + ushort usb_ep5isr; + ushort res20; + ushort usb_ep6isr; + ushort res21; + ushort usb_ep7isr; + ulong usb_ep0imr; + ushort res22; + ushort usb_ep1imr; + ushort res23; + ushort usb_ep2imr; + ushort res24; + ushort usb_ep3imr; + ushort res25; + ushort usb_ep4imr; + ushort res26; + ushort usb_ep5imr; + ushort res27; + ushort usb_ep6imr; + ushort res28; + ushort usb_ep7imr; + ulong usb_ep0dr; + ulong usb_ep1dr; + ulong usb_ep2dr; + ulong usb_ep3dr; + ulong usb_ep4dr; + ulong usb_ep5dr; + ulong usb_ep6dr; + ulong usb_ep7dr; + ushort res29; + ushort usb_ep0dpr; + ushort res30; + ushort usb_ep1dpr; + ushort res31; + ushort usb_ep2dpr; + ushort res32; + ushort usb_ep3dpr; + ushort res33; + ushort usb_ep4dpr; + ushort res34; + ushort usb_ep5dpr; + ushort res35; + ushort usb_ep6dpr; + ushort res36; + ushort usb_ep7dpr; + uchar res37[788]; + uchar usb_cfgram[1024]; } usb_t; -#endif /* __IMMAP_5272__ */ +/* Internal memory map. +*/ +typedef struct immap { + sysctrl_t sysctrl_reg; /* System configuration registers */ + intctrl_t intctrl_reg; /* Interrupt controller registers */ + csctrl_t csctrl_reg; /* Chip select controller registers */ + gpio_t gpio_reg; /* GPIO controller registers */ + qspi_t qspi_reg; /* QSPI controller registers */ + pwm_t pwm_reg; /* Pulse width modulation registers */ + dma_t dma_reg; /* DMA registers */ + uart_t uart_reg[2]; /* UART registers */ + sdramctrl_t sdram_reg; /* SDRAM controller registers */ + timer_t timer_reg[4]; /* Timer registers */ + wdog_t wdog_reg; /* Watchdog registers */ + plic_t plic_reg; /* Physical layer interface registers */ + fec_t fec_reg; /* Fast ethernet controller registers */ + usb_t usb_reg; /* USB controller registers */ +} immap_t; + +#endif /* __IMMAP_5272__ */ diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h index e82960ac0..6553b0869 100644 --- a/include/asm-m68k/immap_5282.h +++ b/include/asm-m68k/immap_5282.h @@ -25,168 +25,61 @@ #ifndef __IMMAP_5282__ #define __IMMAP_5282__ -#define MMAP_SCM (CFG_MBAR + 0x00000000) -#define MMAP_SDRAMC (CFG_MBAR + 0x00000040) -#define MMAP_FBCS (CFG_MBAR + 0x00000080) -#define MMAP_DMA0 (CFG_MBAR + 0x00000100) -#define MMAP_DMA1 (CFG_MBAR + 0x00000140) -#define MMAP_DMA2 (CFG_MBAR + 0x00000180) -#define MMAP_DMA3 (CFG_MBAR + 0x000001C0) -#define MMAP_UART0 (CFG_MBAR + 0x00000200) -#define MMAP_UART1 (CFG_MBAR + 0x00000240) -#define MMAP_UART2 (CFG_MBAR + 0x00000280) -#define MMAP_I2C (CFG_MBAR + 0x00000300) -#define MMAP_QSPI (CFG_MBAR + 0x00000340) -#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) -#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) -#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) -#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) -#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) -#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) -#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) -#define MMAP_FEC (CFG_MBAR + 0x00001000) -#define MMAP_FECFIFO (CFG_MBAR + 0x00001400) -#define MMAP_GPIO (CFG_MBAR + 0x00100000) -#define MMAP_CCM (CFG_MBAR + 0x00110000) -#define MMAP_PLL (CFG_MBAR + 0x00120000) -#define MMAP_EPORT (CFG_MBAR + 0x00130000) -#define MMAP_WDOG (CFG_MBAR + 0x00140000) -#define MMAP_PIT0 (CFG_MBAR + 0x00150000) -#define MMAP_PIT1 (CFG_MBAR + 0x00160000) -#define MMAP_PIT2 (CFG_MBAR + 0x00170000) -#define MMAP_PIT3 (CFG_MBAR + 0x00180000) -#define MMAP_QADC (CFG_MBAR + 0x00190000) -#define MMAP_GPTMRA (CFG_MBAR + 0x001A0000) -#define MMAP_GPTMRB (CFG_MBAR + 0x001B0000) -#define MMAP_CAN (CFG_MBAR + 0x001C0000) -#define MMAP_CFMC (CFG_MBAR + 0x001D0000) -#define MMAP_CFMMEM (CFG_MBAR + 0x04000000) +struct sys_ctrl { + uint ipsbar; + char res1[4]; + uint rambar; + char res2[4]; + uchar crsr; + uchar cwcr; + uchar lpicr; + uchar cwsr; + uint dmareqc; + char res3[4]; + uint mpark; -/* System Control Module */ -typedef struct scm_ctrl { - u32 ipsbar; - u32 res1; - u32 rambar; - u32 res2; - u8 crsr; - u8 cwcr; - u8 lpicr; - u8 cwsr; - u32 res3; - u8 mpark; - u8 res4[3]; - u8 pacr0; - u8 pacr1; - u8 pacr2; - u8 pacr3; - u8 pacr4; - u8 res5; - u8 pacr5; - u8 pacr6; - u8 pacr7; - u8 res6; - u8 pacr8; - u8 res7; - u8 gpacr0; - u8 gpacr1; - u16 res8; -} scm_t; + /* TODO: finish these */ +}; -/* Flexbus module Chip select registers */ -typedef struct fbcs_ctrl { - u16 csar0; /* 0x00 Chip-Select Address Register 0 */ - u16 res0; - u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */ - u16 res1; /* 0x08 */ - u16 cscr0; /* 0x0A Chip-Select Control Register 0 */ +/* Fast ethernet controller registers + */ +typedef struct fec { + uint res1; /* reserved 1000*/ + uint fec_ievent; /* interrupt event register 1004*/ /* EIR */ + uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */ + uint res2; /* reserved 100c*/ + uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */ + uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */ + uint res3[3]; /* reserved 1018*/ + uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */ + uint res4[6]; /* reserved 1028*/ + uint fec_mii_data; /* MII data register 1040*/ /* MDATA */ + uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */ + /*1044*/ + uint res5[7]; /* reserved 1048*/ + uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */ + uint res6[7]; /* reserved 1068*/ + uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */ + uint res7[15]; /* reserved 1088*/ + uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */ + uint res8[7]; /* reserved 10C8*/ + uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */ + uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */ + uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */ + uint res9[10]; /* reserved 10F0*/ + uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */ + uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */ + uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */ + uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */ + uint res10[7]; /* reserved 1128*/ + uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */ + uint res11; /* reserved 1148*/ + uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */ + uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */ + uint res12[11]; /* reserved 1154*/ + uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */ + uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */ + uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */ +} fec_t; - u16 csar1; /* 0x0C Chip-Select Address Register 1 */ - u16 res2; - u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */ - u16 res3; /* 0x14 */ - u16 cscr1; /* 0x16 Chip-Select Control Register 1 */ - - u16 csar2; /* 0x18 Chip-Select Address Register 2 */ - u16 res4; - u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */ - u16 res5; /* 0x20 */ - u16 cscr2; /* 0x22 Chip-Select Control Register 2 */ - - u16 csar3; /* 0x24 Chip-Select Address Register 3 */ - u16 res6; - u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */ - u16 res7; /* 0x2C */ - u16 cscr3; /* 0x2E Chip-Select Control Register 3 */ - - u16 csar4; /* 0x30 Chip-Select Address Register 4 */ - u16 res8; - u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */ - u16 res9; /* 0x38 */ - u16 cscr4; /* 0x3A Chip-Select Control Register 4 */ - - u16 csar5; /* 0x3C Chip-Select Address Register 5 */ - u16 res10; - u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */ - u16 res11; /* 0x44 */ - u16 cscr5; /* 0x46 Chip-Select Control Register 5 */ - - u16 csar6; /* 0x48 Chip-Select Address Register 5 */ - u16 res12; - u32 csmr6; /* 0x4C Chip-Select Mask Register 5 */ - u16 res13; /* 0x50 */ - u16 cscr6; /* 0x52 Chip-Select Control Register 5 */ - - u16 csar7; /* 0x54 Chip-Select Address Register 5 */ - u16 res14; - u32 csmr7; /* 0x58 Chip-Select Mask Register 5 */ - u16 res15; /* 0x5C */ - u16 cscr7; /* 0x5E Chip-Select Control Register 5 */ -} fbcs_t; - -/* Interrupt module registers */ -typedef struct int0_ctrl { - /* Interrupt Controller 0 */ - u32 iprh0; /* 0x00 Pending Register High */ - u32 iprl0; /* 0x04 Pending Register Low */ - u32 imrh0; /* 0x08 Mask Register High */ - u32 imrl0; /* 0x0C Mask Register Low */ - u32 frch0; /* 0x10 Force Register High */ - u32 frcl0; /* 0x14 Force Register Low */ - u8 irlr; /* 0x18 */ - u8 iacklpr; /* 0x19 */ - u16 res1[19]; /* 0x1a - 0x3c */ - u8 icr0[64]; /* 0x40 - 0x7F Control registers */ - u32 res3[24]; /* 0x80 - 0xDF */ - u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */ - u8 res4[3]; /* 0xE1 - 0xE3 */ - u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */ - u8 res5[3]; /* 0xE5 - 0xE7 */ - u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */ - u8 res6[3]; /* 0xE9 - 0xEB */ - u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */ - u8 res7[3]; /* 0xED - 0xEF */ - u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */ - u8 res8[3]; /* 0xF1 - 0xF3 */ - u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */ - u8 res9[3]; /* 0xF5 - 0xF7 */ - u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */ - u8 resa[3]; /* 0xF9 - 0xFB */ - u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */ - u8 resb[3]; /* 0xFD - 0xFF */ -} int0_t; - -/* Clock Module registers */ -typedef struct pll_ctrl { - u16 syncr; /* 0x00 synthesizer control register */ - u16 synsr; /* 0x02 synthesizer status register */ -} pll_t; - -/* Watchdog registers */ -typedef struct wdog_ctrl { - ushort wcr; - ushort wmr; - ushort wcntr; - ushort wsr; -} wdog_t; - -#endif /* __IMMAP_5282__ */ +#endif /* __IMMAP_5282__ */ diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 1fccc1292..79a9626b5 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -1,254 +1 @@ -/* - * IO header file - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_M68K_IO_H__ -#define __ASM_M68K_IO_H__ - -#include - -#define __raw_readb(addr) (*(volatile u8 *)(addr)) -#define __raw_readw(addr) (*(volatile u16 *)(addr)) -#define __raw_readl(addr) (*(volatile u32 *)(addr)) - -#define __raw_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) -#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w)) -#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l)) - -#define readb(addr) in_8((volatile u8 *)(addr)) -#define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) -#if !defined(__BIG_ENDIAN) -#define readw(addr) (*(volatile u16 *) (addr)) -#define readl(addr) (*(volatile u32 *) (addr)) -#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) -#else -#define readw(addr) in_le16((volatile u16 *)(addr)) -#define readl(addr) in_le32((volatile u32 *)(addr)) -#define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) -#define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) -#endif - -/* - * The insw/outsw/insl/outsl macros don't do byte-swapping. - * They are only used in practice for transferring buffers which - * are arrays of bytes, and byte-swapping is not appropriate in - * that case. - paulus - */ -#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) -#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - -#define inb(port) in_8((u8 *)((port)+_IO_BASE)) -#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) -#if !defined(__BIG_ENDIAN) -#define inw(port) in_be16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_be32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) -#else -#define inw(port) in_le16((u16 *)((port)+_IO_BASE)) -#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) -#define inl(port) in_le32((u32 *)((port)+_IO_BASE)) -#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) -#endif - -extern inline void _insb(volatile u8 * port, void *buf, int ns) -{ - u8 *data = (u8 *) buf; - while (ns--) - *data++ = *port; -} - -extern inline void _outsb(volatile u8 * port, const void *buf, int ns) -{ - u8 *data = (u8 *) buf; - while (ns--) - *port = *data++; -} - -extern inline void _insw(volatile u16 * port, void *buf, int ns) -{ - u16 *data = (u16 *) buf; - while (ns--) - *data++ = __sw16(*port); -} - -extern inline void _outsw(volatile u16 * port, const void *buf, int ns) -{ - u16 *data = (u16 *) buf; - while (ns--) { - *port = __sw16(*data); - data++; - } -} - -extern inline void _insl(volatile u32 * port, void *buf, int nl) -{ - u32 *data = (u32 *) buf; - while (nl--) - *data++ = __sw32(*port); -} - -extern inline void _outsl(volatile u32 * port, const void *buf, int nl) -{ - u32 *data = (u32 *) buf; - while (nl--) { - *port = __sw32(*data); - data++; - } -} - -extern inline void _insw_ns(volatile u16 * port, void *buf, int ns) -{ - u16 *data = (u16 *) buf; - while (ns--) - *data++ = *port; -} - -extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) -{ - u16 *data = (u16 *) buf; - while (ns--) { - *port = *data++; - } -} - -extern inline void _insl_ns(volatile u32 * port, void *buf, int nl) -{ - u32 *data = (u32 *) buf; - while (nl--) - *data++ = *port; -} - -extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) -{ - u32 *data = (u32 *) buf; - while (nl--) { - *port = *data; - data++; - } -} - -/* - * The *_ns versions below don't do byte-swapping. - * Neither do the standard versions now, these are just here - * for older code. - */ -#define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) -#define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) -#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) - -#define IO_SPACE_LIMIT ~0 - -/* - * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - */ -extern inline int in_8(volatile u8 * addr) -{ - return (int)*addr; -} - -extern inline void out_8(volatile u8 * addr, int val) -{ - *addr = (u8) val; -} - -extern inline int in_le16(volatile u16 * addr) -{ - return __sw16(*addr); -} - -extern inline int in_be16(volatile u16 * addr) -{ - return (*addr & 0xFFFF); -} - -extern inline void out_le16(volatile u16 * addr, int val) -{ - *addr = __sw16(val); -} - -extern inline void out_be16(volatile u16 * addr, int val) -{ - *addr = (u16) val; -} - -extern inline unsigned in_le32(volatile u32 * addr) -{ - return __sw32(*addr); -} - -extern inline unsigned in_be32(volatile u32 * addr) -{ - return (*addr); -} - -extern inline void out_le32(volatile unsigned *addr, int val) -{ - *addr = __sw32(val); -} - -extern inline void out_be32(volatile unsigned *addr, int val) -{ - *addr = val; -} - -static inline void sync(void) -{ - /* This sync function is for PowerPC or other architecture instruction - * ColdFire does not have this instruction. Dummy function, added for - * compatibility (CFI driver) - */ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void *map_physmem(phys_addr_t paddr, unsigned long len, - unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -#endif /* __ASM_M68K_IO_H__ */ +/* */ diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h index facf0c909..8c1b07755 100644 --- a/include/asm-m68k/m5249.h +++ b/include/asm-m68k/m5249.h @@ -24,6 +24,7 @@ * MA 02111-1307 USA */ + #ifndef mcf5249_h #define mcf5249_h /****************************************************************************/ @@ -31,21 +32,22 @@ /* * useful definitions for reading/writing MBAR offset memory */ -#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y -#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x)) -#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y -#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y -#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y +#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x)) +#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y +#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y +#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y + /* * Size of internal RAM */ -#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */ -#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */ +#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */ +#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */ /* * Define the 5249 SIM register set addresses. @@ -54,47 +56,51 @@ /***************** ***** MBAR1 ***** *****************/ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ -#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ +#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ +#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ -#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ -#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ -#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ -#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ -#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ -#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ -#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ -#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ -#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ -#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ +#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ +#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ +#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ -#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ -#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ +#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ -#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ -#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ -#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ -#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ -#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ -#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ -#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ -#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ -#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ -#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ -#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ +#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ +#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ +#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ +#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ +#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ +#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ +#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ +#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ +#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ +#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ +#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ +#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ +#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ + +/** UART Bases **/ +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ /***************** ***** MBAR2 ***** @@ -103,39 +109,39 @@ /* GPIO Addresses * Note: These are offset from MBAR2! */ -#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */ -#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w) */ -#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w) */ -#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */ -#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */ -#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */ -#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */ -#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */ +#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */ +#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w)*/ +#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w)*/ +#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */ +#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */ +#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */ +#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */ +#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */ -#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */ -#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */ -#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */ +#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */ +#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */ +#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */ -#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */ -#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */ -#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */ +#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */ +#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */ +#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */ -#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */ -#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */ -#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */ -#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */ -#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */ -#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */ -#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */ -#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */ +#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */ +#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */ +#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */ +#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */ +#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */ +#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */ +#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */ +#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */ -#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */ -#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */ +#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */ +#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */ -#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */ -#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */ +#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */ +#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */ -#define MCFSIM_PLLCR 0x180 /* PLL Control register */ +#define MCFSIM_PLLCR 0x180 /* PLL Control register */ /* * Some symbol defines for the above... @@ -152,20 +158,21 @@ /* * Bit definitions for the ICR family of registers. */ -#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ -#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ -#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ -#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ -#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ -#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ -#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ -#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ -#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ +#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ +#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ +#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ +#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ +#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ +#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ +#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ +#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ +#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ + +#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ +#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ +#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ +#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ -#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ -#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ -#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ -#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ /* * Macros to read/set IMR register. It is 32 bits on the 5249. @@ -177,4 +184,4 @@ #define mcf_setimr(imr) \ *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); -#endif /* mcf5249_h */ +#endif /* mcf5249_h */ diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h index be343987f..765414fdc 100644 --- a/include/asm-m68k/m5271.h +++ b/include/asm-m68k/m5271.h @@ -25,6 +25,7 @@ * MA 02111-1307 USA */ + #ifndef _MCF5271_H_ #define _MCF5271_H_ @@ -56,12 +57,6 @@ #define MCF_GPIO_PAR_FECI2C 0x100047 #define MCF_GPIO_PAR_UART 0x100048 -#define MCF_CCM_CIR 0x11000A -#define MCF_CCM_CIR_PRN_MASK 0x3F -#define MCF_CCM_CIR_PIN_LEN 6 -#define MCF_CCM_CIR_PIN_MCF5270 0x2e -#define MCF_CCM_CIR_PIN_MCF5271 0x80 - #define MCF_GPIO_AD_ADDR23 0x80 #define MCF_GPIO_AD_ADDR22 0x40 #define MCF_GPIO_AD_ADDR21 0x20 @@ -90,7 +85,7 @@ #define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00 #define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300 -#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) #define MCF_SDRAMC_DCR 0x000040 #define MCF_SDRAMC_DACR0 0x000048 @@ -116,104 +111,4 @@ #define MCFSIM_ICR1 0x000C41 -/********************************************************************* -* Interrupt Controller (INTC) -*********************************************************************/ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_SCM (8) -#define INT0_LO_DMA0 (9) -#define INT0_LO_DMA1 (10) -#define INT0_LO_DMA2 (11) -#define INT0_LO_DMA3 (12) -#define INT0_LO_UART0 (13) -#define INT0_LO_UART1 (14) -#define INT0_LO_UART2 (15) -#define INT0_LO_RSVD1 (16) -#define INT0_LO_I2C (17) -#define INT0_LO_QSPI (18) -#define INT0_LO_DTMR0 (19) -#define INT0_LO_DTMR1 (20) -#define INT0_LO_DTMR2 (21) -#define INT0_LO_DTMR3 (22) -#define INT0_LO_FEC_TXF (23) -#define INT0_LO_FEC_TXB (24) -#define INT0_LO_FEC_UN (25) -#define INT0_LO_FEC_RL (26) -#define INT0_LO_FEC_RXF (27) -#define INT0_LO_FEC_RXB (28) -#define INT0_LO_FEC_MII (29) -#define INT0_LO_FEC_LC (30) -#define INT0_LO_FEC_HBERR (31) -#define INT0_HI_FEC_GRA (32) -#define INT0_HI_FEC_EBERR (33) -#define INT0_HI_FEC_BABT (34) -#define INT0_HI_FEC_BABR (35) -#define INT0_HI_PIT0 (36) -#define INT0_HI_PIT1 (37) -#define INT0_HI_PIT2 (38) -#define INT0_HI_PIT3 (39) -#define INT0_HI_RNG (40) -#define INT0_HI_SKHA (41) -#define INT0_HI_MDHA (42) -#define INT0_HI_CAN1_BUF0I (43) -#define INT0_HI_CAN1_BUF1I (44) -#define INT0_HI_CAN1_BUF2I (45) -#define INT0_HI_CAN1_BUF3I (46) -#define INT0_HI_CAN1_BUF4I (47) -#define INT0_HI_CAN1_BUF5I (48) -#define INT0_HI_CAN1_BUF6I (49) -#define INT0_HI_CAN1_BUF7I (50) -#define INT0_HI_CAN1_BUF8I (51) -#define INT0_HI_CAN1_BUF9I (52) -#define INT0_HI_CAN1_BUF10I (53) -#define INT0_HI_CAN1_BUF11I (54) -#define INT0_HI_CAN1_BUF12I (55) -#define INT0_HI_CAN1_BUF13I (56) -#define INT0_HI_CAN1_BUF14I (57) -#define INT0_HI_CAN1_BUF15I (58) -#define INT0_HI_CAN1_ERRINT (59) -#define INT0_HI_CAN1_BOFFINT (60) -/* 60-63 Reserved */ - -/* Bit definitions and macros for INTC_IPRL */ -#define INTC_IPRL_INT31 (0x80000000) -#define INTC_IPRL_INT30 (0x40000000) -#define INTC_IPRL_INT29 (0x20000000) -#define INTC_IPRL_INT28 (0x10000000) -#define INTC_IPRL_INT27 (0x08000000) -#define INTC_IPRL_INT26 (0x04000000) -#define INTC_IPRL_INT25 (0x02000000) -#define INTC_IPRL_INT24 (0x01000000) -#define INTC_IPRL_INT23 (0x00800000) -#define INTC_IPRL_INT22 (0x00400000) -#define INTC_IPRL_INT21 (0x00200000) -#define INTC_IPRL_INT20 (0x00100000) -#define INTC_IPRL_INT19 (0x00080000) -#define INTC_IPRL_INT18 (0x00040000) -#define INTC_IPRL_INT17 (0x00020000) -#define INTC_IPRL_INT16 (0x00010000) -#define INTC_IPRL_INT15 (0x00008000) -#define INTC_IPRL_INT14 (0x00004000) -#define INTC_IPRL_INT13 (0x00002000) -#define INTC_IPRL_INT12 (0x00001000) -#define INTC_IPRL_INT11 (0x00000800) -#define INTC_IPRL_INT10 (0x00000400) -#define INTC_IPRL_INT9 (0x00000200) -#define INTC_IPRL_INT8 (0x00000100) -#define INTC_IPRL_INT7 (0x00000080) -#define INTC_IPRL_INT6 (0x00000040) -#define INTC_IPRL_INT5 (0x00000020) -#define INTC_IPRL_INT4 (0x00000010) -#define INTC_IPRL_INT3 (0x00000008) -#define INTC_IPRL_INT2 (0x00000004) -#define INTC_IPRL_INT1 (0x00000002) -#define INTC_IPRL_INT0 (0x00000001) - -#endif /* _MCF5271_H_ */ +#endif /* _MCF5271_H_ */ diff --git a/include/asm-m68k/m5272.h b/include/asm-m68k/m5272.h index 895f89df7..54d4a3209 100644 --- a/include/asm-m68k/m5272.h +++ b/include/asm-m68k/m5272.h @@ -24,6 +24,7 @@ * MA 02111-1307 USA */ + #ifndef mcf5272_h #define mcf5272_h /****************************************************************************/ @@ -34,173 +35,65 @@ #define INT_RAM_SIZE 4096 -#define GPIO_PACNT_PA15MSK (0xC0000000) -#define GPIO_PACNT_DGNT1 (0x40000000) -#define GPIO_PACNT_PA14MSK (0x30000000) -#define GPIO_PACNT_DREQ1 (0x10000000) -#define GPIO_PACNT_PA13MSK (0x0C000000) -#define GPIO_PACNT_DFSC3 (0x04000000) -#define GPIO_PACNT_PA12MSK (0x03000000) -#define GPIO_PACNT_DFSC2 (0x01000000) -#define GPIO_PACNT_PA11MSK (0x00C00000) -#define GPIO_PACNT_QSPI_CS1 (0x00800000) -#define GPIO_PACNT_PA10MSK (0x00300000) -#define GPIO_PACNT_DREQ0 (0x00100000) -#define GPIO_PACNT_PA9MSK (0x000C0000) -#define GPIO_PACNT_DGNT0 (0x00040000) -#define GPIO_PACNT_PA8MSK (0x00030000) -#define GPIO_PACNT_FSC0 (0x00010000) -#define GPIO_PACNT_FSR0 (0x00010000) -#define GPIO_PACNT_PA7MSK (0x0000C000) -#define GPIO_PACNT_DOUT3 (0x00008000) -#define GPIO_PACNT_QSPI_CS3 (0x00004000) -#define GPIO_PACNT_PA6MSK (0x00003000) -#define GPIO_PACNT_USB_RXD (0x00001000) -#define GPIO_PACNT_PA5MSK (0x00000C00) -#define GPIO_PACNT_USB_TXEN (0x00000400) -#define GPIO_PACNT_PA4MSK (0x00000300) -#define GPIO_PACNT_USB_SUSP (0x00000100) -#define GPIO_PACNT_PA3MSK (0x000000C0) -#define GPIO_PACNT_USB_TN (0x00000040) -#define GPIO_PACNT_PA2MSK (0x00000030) -#define GPIO_PACNT_USB_RN (0x00000010) -#define GPIO_PACNT_PA1MSK (0x0000000C) -#define GPIO_PACNT_USB_RP (0x00000004) -#define GPIO_PACNT_PA0MSK (0x00000003) -#define GPIO_PACNT_USB_TP (0x00000001) -#define GPIO_PBCNT_PB15MSK (0xC0000000) -#define GPIO_PBCNT_E_MDC (0x40000000) -#define GPIO_PBCNT_PB14MSK (0x30000000) -#define GPIO_PBCNT_E_RXER (0x10000000) -#define GPIO_PBCNT_PB13MSK (0x0C000000) -#define GPIO_PBCNT_E_RXD1 (0x04000000) -#define GPIO_PBCNT_PB12MSK (0x03000000) -#define GPIO_PBCNT_E_RXD2 (0x01000000) -#define GPIO_PBCNT_PB11MSK (0x00C00000) -#define GPIO_PBCNT_E_RXD3 (0x00400000) -#define GPIO_PBCNT_PB10MSK (0x00300000) -#define GPIO_PBCNT_E_TXD1 (0x00100000) -#define GPIO_PBCNT_PB9MSK (0x000C0000) -#define GPIO_PBCNT_E_TXD2 (0x00040000) -#define GPIO_PBCNT_PB8MSK (0x00030000) -#define GPIO_PBCNT_E_TXD3 (0x00010000) -#define GPIO_PBCNT_PB7MSK (0x0000C000) -#define GPIO_PBCNT_TOUT0 (0x00004000) -#define GPIO_PBCNT_PB6MSK (0x00003000) -#define GPIO_PBCNT_TA (0x00001000) -#define GPIO_PBCNT_PB4MSK (0x00000300) -#define GPIO_PBCNT_URT0_CLK (0x00000100) -#define GPIO_PBCNT_PB3MSK (0x000000C0) -#define GPIO_PBCNT_URT0_RTS (0x00000040) -#define GPIO_PBCNT_PB2MSK (0x00000030) -#define GPIO_PBCNT_URT0_CTS (0x00000010) -#define GPIO_PBCNT_PB1MSK (0x0000000C) -#define GPIO_PBCNT_URT0_RXD (0x00000004) -#define GPIO_PBCNT_URT0_TIN2 (0x00000004) -#define GPIO_PBCNT_PB0MSK (0x00000003) -#define GPIO_PBCNT_URT0_TXD (0x00000001) +/* + * Define the 5272 SIM register set addresses. + */ +#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ +#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ +#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ +#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ +#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ -#define GPIO_PDCNT_PD7MSK (0x0000C000) -#define GPIO_PDCNT_TIN1 (0x00008000) -#define GPIO_PDCNT_PWM_OUT2 (0x00004000) -#define GPIO_PDCNT_PD6MSK (0x00003000) -#define GPIO_PDCNT_TOUT1 (0x00002000) -#define GPIO_PDCNT_PWM_OUT1 (0x00001000) -#define GPIO_PDCNT_PD5MSK (0x00000C00) -#define GPIO_PDCNT_INT4 (0x00000C00) -#define GPIO_PDCNT_DIN3 (0x00000800) -#define GPIO_PDCNT_PD4MSK (0x00000300) -#define GPIO_PDCNT_URT1_TXD (0x00000200) -#define GPIO_PDCNT_DOUT0 (0x00000100) -#define GPIO_PDCNT_PD3MSK (0x000000C0) -#define GPIO_PDCNT_INT5 (0x000000C0) -#define GPIO_PDCNT_URT1_RTS (0x00000080) -#define GPIO_PDCNT_PD2MSK (0x00000030) -#define GPIO_PDCNT_QSPI_CS2 (0x00000030) -#define GPIO_PDCNT_URT1_CTS (0x00000020) -#define GPIO_PDCNT_PD1MSK (0x0000000C) -#define GPIO_PDCNT_URT1_RXD (0x00000008) -#define GPIO_PDCNT_URT1_TIN3 (0x00000008) -#define GPIO_PDCNT_DIN0 (0x00000004) -#define GPIO_PDCNT_PD0MSK (0x00000003) -#define GPIO_PDCNT_URT1_CLK (0x00000002) -#define GPIO_PDCNT_DCL0 (0x00000001) +#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ -#define INT_RSVD0 (0) -#define INT_INT1 (1) -#define INT_INT2 (2) -#define INT_INT3 (3) -#define INT_INT4 (4) -#define INT_TMR0 (5) -#define INT_TMR1 (6) -#define INT_TMR2 (7) -#define INT_TMR3 (8) -#define INT_UART1 (9) -#define INT_UART2 (10) -#define INT_PLIP (11) -#define INT_PLIA (12) -#define INT_USB0 (13) -#define INT_USB1 (14) -#define INT_USB2 (15) -#define INT_USB3 (16) -#define INT_USB4 (17) -#define INT_USB5 (18) -#define INT_USB6 (19) -#define INT_USB7 (20) -#define INT_DMA (21) -#define INT_ERX (22) -#define INT_ETX (23) -#define INT_ENTC (24) -#define INT_QSPI (25) -#define INT_INT5 (26) -#define INT_INT6 (27) -#define INT_SWTO (28) +#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ +#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ +#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ +#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ -#define INT_ICR1_TMR0MASK (0x000F000) -#define INT_ICR1_TMR0PI (0x0008000) -#define INT_ICR1_TMR0IPL(x) (((x)&0x7)<<12) -#define INT_ICR1_TMR1MASK (0x0000F00) -#define INT_ICR1_TMR1PI (0x0000800) -#define INT_ICR1_TMR1IPL(x) (((x)&0x7)<<8) -#define INT_ICR1_TMR2MASK (0x00000F0) -#define INT_ICR1_TMR2PI (0x0000080) -#define INT_ICR1_TMR2IPL(x) (((x)&0x7)<<4) -#define INT_ICR1_TMR3MASK (0x000000F) -#define INT_ICR1_TMR3PI (0x0000008) -#define INT_ICR1_TMR3IPL(x) (((x)&0x7)) +#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ +#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ +#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ +#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ -#define INT_ISR_INT31 (0x80000000) -#define INT_ISR_INT30 (0x40000000) -#define INT_ISR_INT29 (0x20000000) -#define INT_ISR_INT28 (0x10000000) -#define INT_ISR_INT27 (0x08000000) -#define INT_ISR_INT26 (0x04000000) -#define INT_ISR_INT25 (0x02000000) -#define INT_ISR_INT24 (0x01000000) -#define INT_ISR_INT23 (0x00800000) -#define INT_ISR_INT22 (0x00400000) -#define INT_ISR_INT21 (0x00200000) -#define INT_ISR_INT20 (0x00100000) -#define INT_ISR_INT19 (0x00080000) -#define INT_ISR_INT18 (0x00040000) -#define INT_ISR_INT17 (0x00020000) -#define INT_ISR_INT16 (0x00010000) -#define INT_ISR_INT15 (0x00008000) -#define INT_ISR_INT14 (0x00004000) -#define INT_ISR_INT13 (0x00002000) -#define INT_ISR_INT12 (0x00001000) -#define INT_ISR_INT11 (0x00000800) -#define INT_ISR_INT10 (0x00000400) -#define INT_ISR_INT9 (0x00000200) -#define INT_ISR_INT8 (0x00000100) -#define INT_ISR_INT7 (0x00000080) -#define INT_ISR_INT6 (0x00000040) -#define INT_ISR_INT5 (0x00000020) -#define INT_ISR_INT4 (0x00000010) -#define INT_ISR_INT3 (0x00000008) -#define INT_ISR_INT2 (0x00000004) -#define INT_ISR_INT1 (0x00000002) -#define INT_ISR_INT0 (0x00000001) +#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ +#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ +#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ +#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ +#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ +#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ +#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ +#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ +#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ +#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ +#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ +#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ +#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ +#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ +#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ +#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ -#endif /* mcf5272_h */ +#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ +#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ +#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ +#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ +#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ +#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ + +#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ +#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ +#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ +#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ +#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ +#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ +#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ +#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ +#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ + +#endif /* mcf5272_h */ diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h index f6a6b0408..e5058a46a 100644 --- a/include/asm-m68k/m5282.h +++ b/include/asm-m68k/m5282.h @@ -23,99 +23,7 @@ /****************************************************************************/ #ifndef m5282_h #define m5282_h - -/********************************************************************* -* PLL Clock Module -*********************************************************************/ -/* Bit definitions and macros for PLL_SYNCR */ -#define PLL_SYNCR_LOLRE (0x8000) -#define PLL_SYNCR_MFD2 (0x4000) -#define PLL_SYNCR_MFD1 (0x2000) -#define PLL_SYNCR_MFD0 (0x1000) -#define PLL_SYNCR_LOCRE (0x0800) -#define PLL_SYNCR_RFC2 (0x0400) -#define PLL_SYNCR_RFC1 (0x0200) -#define PLL_SYNCR_RFC0 (0x0100) -#define PLL_SYNCR_LOCEN (0x0080) -#define PLL_SYNCR_DISCLK (0x0040) -#define PLL_SYNCR_FWKUP (0x0020) -#define PLL_SYNCR_STPMD1 (0x0008) -#define PLL_SYNCR_STPMD0 (0x0004) - -/* Bit definitions and macros for PLL_SYNSR */ -#define PLL_SYNSR_MODE (0x0080) -#define PLL_SYNSR_PLLSEL (0x0040) -#define PLL_SYNSR_PLLREF (0x0020) -#define PLL_SYNSR_LOCKS (0x0010) -#define PLL_SYNSR_LOCK (0x0008) -#define PLL_SYNSR_LOCS (0x0004) - -/********************************************************************* -* Interrupt Controller (INTC) -*********************************************************************/ -#define INT0_LO_RSVD0 (0) -#define INT0_LO_EPORT1 (1) -#define INT0_LO_EPORT2 (2) -#define INT0_LO_EPORT3 (3) -#define INT0_LO_EPORT4 (4) -#define INT0_LO_EPORT5 (5) -#define INT0_LO_EPORT6 (6) -#define INT0_LO_EPORT7 (7) -#define INT0_LO_SCM_SWT1 (8) -#define INT0_LO_DMA_00 (9) -#define INT0_LO_DMA_01 (10) -#define INT0_LO_DMA_02 (11) -#define INT0_LO_DMA_03 (12) -#define INT0_LO_UART0 (13) -#define INT0_LO_UART1 (14) -#define INT0_LO_UART2 (15) -#define INT0_LO_RSVD1 (16) -#define INT0_LO_I2C (17) -#define INT0_LO_QSPI (18) -#define INT0_LO_DTMR0 (19) -#define INT0_LO_DTMR1 (20) -#define INT0_LO_DTMR2 (21) -#define INT0_LO_DTMR3 (22) -#define INT0_LO_FEC_TXF (23) -#define INT0_LO_FEC_TXB (24) -#define INT0_LO_FEC_UN (25) -#define INT0_LO_FEC_RL (26) -#define INT0_LO_FEC_RXF (27) -#define INT0_LO_FEC_RXB (28) -#define INT0_LO_FEC_MII (29) -#define INT0_LO_FEC_LC (30) -#define INT0_LO_FEC_HBERR (31) -#define INT0_HI_FEC_GRA (32) -#define INT0_HI_FEC_EBERR (33) -#define INT0_HI_FEC_BABT (34) -#define INT0_HI_FEC_BABR (35) -#define INT0_HI_PMM_LVDF (36) -#define INT0_HI_QADC_CF1 (37) -#define INT0_HI_QADC_CF2 (38) -#define INT0_HI_QADC_PF1 (39) -#define INT0_HI_QADC_PF2 (40) -#define INT0_HI_GPTA_TOF (41) -#define INT0_HI_GPTA_PAIF (42) -#define INT0_HI_GPTA_PAOVF (43) -#define INT0_HI_GPTA_C0F (44) -#define INT0_HI_GPTA_C1F (45) -#define INT0_HI_GPTA_C2F (46) -#define INT0_HI_GPTA_C3F (47) -#define INT0_HI_GPTB_TOF (48) -#define INT0_HI_GPTB_PAIF (49) -#define INT0_HI_GPTB_PAOVF (50) -#define INT0_HI_GPTB_C0F (51) -#define INT0_HI_GPTB_C1F (52) -#define INT0_HI_GPTB_C2F (53) -#define INT0_HI_GPTB_C3F (54) -#define INT0_HI_PIT0 (55) -#define INT0_HI_PIT1 (56) -#define INT0_HI_PIT2 (57) -#define INT0_HI_PIT3 (58) -#define INT0_HI_CFM_CBEIF (59) -#define INT0_HI_CFM_CCIF (60) -#define INT0_HI_CFM_PVIF (61) -#define INT0_HI_CFM_AEIF (62) +/****************************************************************************/ /* * Size of internal RAM @@ -188,49 +96,49 @@ #define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B)) #define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C)) #define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D)) -#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E)) -#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F)) -#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030)) -#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031)) -#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032)) -#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033)) -#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034)) -#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035)) -#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036)) -#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037)) -#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038)) -#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039)) +#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E)) +#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F)) +#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030)) +#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031)) +#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032)) +#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033)) +#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034)) +#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035)) +#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036)) +#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037)) +#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038)) +#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039)) -#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C)) -#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D)) -#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E)) -#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F)) -#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040)) -#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041)) -#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042)) -#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043)) -#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044)) -#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045)) -#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046)) -#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047)) -#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048)) -#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049)) -#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A)) -#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B)) -#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C)) -#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D)) +#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C)) +#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D)) +#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E)) +#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F)) +#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040)) +#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041)) +#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042)) +#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043)) +#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044)) +#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045)) +#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046)) +#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047)) +#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048)) +#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049)) +#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A)) +#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B)) +#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C)) +#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D)) -#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050)) -#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051)) -#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052)) -#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054)) -#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055)) -#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056)) -#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058)) -#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059)) -#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A)) -#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B)) -#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C)) +#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050)) +#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051)) +#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052)) +#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054)) +#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055)) +#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056)) +#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058)) +#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059)) +#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A)) +#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B)) +#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C)) /* Bit level definitions and macros */ #define MCFGPIO_PORT7 (0x80) @@ -263,6 +171,7 @@ #define MCFGPIO_Px0 (0x01) #define MCFGPIO_Px(x) (0x01< + +/* + * Get address specific defines for this ColdFire member. + */ +#if defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) +#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ +#elif defined(CONFIG_M5272) +#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ +#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ +#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) +#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ +#elif defined(CONFIG_M5282) | defined(CONFIG_M5271) +#define MCFTIMER_BASE1 0x150000 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x160000 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0x170000 /* Base address of TIMER4 */ +#define MCFTIMER_BASE4 0x180000 /* Base address of TIMER3 */ +#endif + +/* + * Define the TIMER register set addresses. + */ +#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ +#define MCFTIMER_TRR 0x02 /* Timer Reference (r/w) */ +#define MCFTIMER_TCR 0x04 /* Timer Capture reg (r/w) */ +#define MCFTIMER_TCN 0x06 /* Timer Counter reg (r/w) */ +#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ + + +/* + * Define the TIMER register set addresses for 5282. + */ +#define MCFTIMER_PCSR 0 +#define MCFTIMER_PMR 1 +#define MCFTIMER_PCNTR 2 + +/* + * Bit definitions for the Timer Mode Register (TMR). + * Register bit flags are common accross ColdFires. + */ +#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ +#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ +#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ +#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ +#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ +#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ +#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ +#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ +#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ +#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ +#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ +#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ +#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ +#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ +#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ +#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ +#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ + +/* + * Bit definitions for the Timer Event Registers (TER). + */ +#define MCFTIMER_TER_CAP 0x01 /* Capture event */ +#define MCFTIMER_TER_REF 0x02 /* Refernece event */ + +/* + * Bit definitions for the 5282 PIT Control and Status Register (PCSR). + */ +#define MCFTIMER_PCSR_EN 0x0001 +#define MCFTIMER_PCSR_RLD 0x0002 +#define MCFTIMER_PCSR_PIF 0x0004 +#define MCFTIMER_PCSR_PIE 0x0008 +#define MCFTIMER_PCSR_OVW 0x0010 +#define MCFTIMER_PCSR_HALTED 0x0020 +#define MCFTIMER_PCSR_DOZE 0x0040 + + +/****************************************************************************/ +#endif /* mcftimer_h */ diff --git a/include/asm-m68k/mcfuart.h b/include/asm-m68k/mcfuart.h new file mode 100644 index 000000000..7c0999d61 --- /dev/null +++ b/include/asm-m68k/mcfuart.h @@ -0,0 +1,221 @@ +/* + * mcfuart.h -- ColdFire internal UART support defines. + * + * File copied from mcfuart.h of uCLinux distribution: + * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/****************************************************************************/ +#ifndef mcfuart_h +#define mcfuart_h +/****************************************************************************/ + +#include + +/* + * Define the base address of the UARTS within the MBAR address + * space. + */ +#if defined(CONFIG_M5272) +#define MCFUART_BASE1 0x100 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#elif defined(CONFIG_M5204) || defined(CONFIG_M5206) || defined(CONFIG_M5206e) +#if defined(CONFIG_NETtel) +#define MCFUART_BASE1 0x180 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#else +#define MCFUART_BASE1 0x140 /* Base address of UART1 */ +#define MCFUART_BASE2 0x180 /* Base address of UART2 */ +#endif +#elif defined(CONFIG_M5282) || defined(CONFIG_M5271) +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) +#if defined(CONFIG_NETtel) || defined(CONFIG_DISKtel) || defined(CONFIG_SECUREEDGEMP3) +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ +#else +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#endif +#endif + + +/* + * Define the ColdFire UART register set addresses. + */ +#define MCFUART_UMR 0x00 /* Mode register (r/w) */ +#define MCFUART_USR 0x04 /* Status register (r) */ +#define MCFUART_UCSR 0x04 /* Clock Select (w) */ +#define MCFUART_UCR 0x08 /* Command register (w) */ +#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ +#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ +#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ +#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ +#define MCFUART_UISR 0x14 /* Interrup Status (r) */ +#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ +#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ +#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ +#ifdef CONFIG_M5272 +#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ +#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ +#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ +#else +#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ +#endif +#define MCFUART_UIPR 0x34 /* Input Port (r) */ +#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ +#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ + +#ifdef CONFIG_M5249 +/* Note: This isn't in the 5249 docs */ +#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ +#endif + +/* + * Define bit flags in Mode Register 1 (MR1). + */ +#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ +#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ +#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ +#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ +#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ + +#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ +#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ +#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ +#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ +#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ + +#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ +#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ +#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ +#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ + +/* + * Define bit flags in Mode Register 2 (MR2). + */ +#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ +#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ +#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ +#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ +#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ + +#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ +#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ +#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ + +/* + * Define bit flags in Status Register (USR). + */ +#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ +#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ +#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ +#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ +#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ +#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ +#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ +#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ + +#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ + MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) + +/* + * Define bit flags in Clock Select Register (UCSR). + */ +#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ +#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ +#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ + +#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ +#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ +#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ + +/* + * Define bit flags in Command Register (UCR). + */ +#define MCFUART_UCR_CMDNULL 0x00 /* No command */ +#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ +#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ +#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ +#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ +#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ +#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ +#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ + +#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ +#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ +#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ +#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ +#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ +#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ + +/* + * Define bit flags in Input Port Change Register (UIPCR). + */ +#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ +#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ + +/* + * Define bit flags in Input Port Register (UIP). + */ +#define MCFUART_UIPR_CTS 0x01 /* CTS value */ + +/* + * Define bit flags in Output Port Registers (UOP). + * Clear bit by writing to UOP0, set by writing to UOP1. + */ +#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ + +/* + * Define bit flags in the Auxiliary Control Register (UACR). + */ +#define MCFUART_UACR_IEC 0x01 /* Input enable control */ + +/* + * Define bit flags in Interrupt Status Register (UISR). + * These same bits are used for the Interrupt Mask Register (UIMR). + */ +#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ +#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ +#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ +#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ + +#ifdef CONFIG_M5272 +/* + * Define bit flags in the Transmitter FIFO Register (UTF). + */ +#define MCFUART_UTF_TXB 0x1f /* transmitter data level */ +#define MCFUART_UTF_FULL 0x20 /* transmitter fifo full */ +#define MCFUART_UTF_TXS 0xc0 /* transmitter status */ + +/* + * Define bit flags in the Receiver FIFO Register (URF). + */ +#define MCFUART_URF_RXB 0x1f /* receiver data level */ +#define MCFUART_URF_FULL 0x20 /* receiver fifo full */ +#define MCFUART_URF_RXS 0xc0 /* receiver status */ +#endif + +/****************************************************************************/ +#endif /* mcfuart_h */ diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h index 01535beb1..75b241883 100644 --- a/include/asm-m68k/ptrace.h +++ b/include/asm-m68k/ptrace.h @@ -28,32 +28,32 @@ #ifndef __ASSEMBLY__ struct pt_regs { - ulong d0; - ulong d1; - ulong d2; - ulong d3; - ulong d4; - ulong d5; - ulong d6; - ulong d7; - ulong a0; - ulong a1; - ulong a2; - ulong a3; - ulong a4; - ulong a5; - ulong a6; -#if defined(__M68K__) - unsigned format:4; /* frame format specifier */ - unsigned vector:12; /* vector offset */ + ulong d0; + ulong d1; + ulong d2; + ulong d3; + ulong d4; + ulong d5; + ulong d6; + ulong d7; + ulong a0; + ulong a1; + ulong a2; + ulong a3; + ulong a4; + ulong a5; + ulong a6; +#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249) || defined(CONFIG_M5271) + unsigned format : 4; /* frame format specifier */ + unsigned vector : 12; /* vector offset */ unsigned short sr; - unsigned long pc; + unsigned long pc; #else unsigned short sr; - unsigned long pc; + unsigned long pc; #endif }; -#endif /* #ifndef __ASSEMBLY__ */ +#endif /* #ifndef __ASSEMBLY__ */ -#endif /* #ifndef _M68K_PTRACE_H */ +#endif /* #ifndef _M68K_PTRACE_H */ diff --git a/include/asm-m68k/types.h b/include/asm-m68k/types.h index 44b4ca5bd..e673cb085 100644 --- a/include/asm-m68k/types.h +++ b/include/asm-m68k/types.h @@ -14,9 +14,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif typedef struct { @@ -44,9 +44,6 @@ typedef unsigned long long u64; /* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h index 5a0d5fe48..7a6a8c1ff 100644 --- a/include/asm-m68k/u-boot.h +++ b/include/asm-m68k/u-boot.h @@ -37,44 +37,24 @@ #ifndef __ASSEMBLY__ typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_mbar_base; /* base of internal registers */ - unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ - unsigned long bi_boot_params; /* where this board expects params */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned char bi_enetaddr[6]; /* Ethernet adress */ - unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ - unsigned long bi_intfreq; /* Internal Freq, in MHz */ - unsigned long bi_busfreq; /* Bus Freq, in MHz */ -#ifdef CONFIG_PCI - unsigned long bi_pcifreq; /* pci Freq in MHz */ -#endif -#ifdef CONFIG_EXTRA_CLOCK - unsigned long bi_inpfreq; /* input Freq in MHz */ - unsigned long bi_vcofreq; /* vco Freq in MHz */ - unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ -#endif - unsigned long bi_baudrate; /* Console Baudrate */ - -#ifdef CONFIG_HAS_ETH1 - /* second onboard ethernet port */ - unsigned char bi_enet1addr[6]; -#endif -#ifdef CONFIG_HAS_ETH2 - /* third onboard ethernet port */ - unsigned char bi_enet2addr[6]; -#endif -#ifdef CONFIG_HAS_ETH3 - unsigned char bi_enet3addr[6]; -#endif + unsigned long bi_memstart; /* start of DRAM memory */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ + unsigned long bi_mbar_base; /* base of internal registers */ + unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ + unsigned long bi_baudrate; /* Console Baudrate */ } bd_t; -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLY__ */ -#endif /* __U_BOOT_H__ */ +#endif /* __U_BOOT_H__ */ diff --git a/include/asm-microblaze/arch-microblaze/xbasic_types.h b/include/asm-microblaze/arch-microblaze/xbasic_types.h new file mode 100644 index 000000000..25012e6b9 --- /dev/null +++ b/include/asm-microblaze/arch-microblaze/xbasic_types.h @@ -0,0 +1,301 @@ +/****************************************************************************** +* +* Author: Xilinx, Inc. +* +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of the GNU General Public License as published by the +* Free Software Foundation; either version 2 of the License, or (at your +* option) any later version. +* +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A +* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS +* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, +* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE +* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING +* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. +* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO +* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY +* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM +* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND +* FITNESS FOR A PARTICULAR PURPOSE. +* +* +* Xilinx hardware products are not intended for use in life support +* appliances, devices, or systems. Use in such applications is +* expressly prohibited. +* +* +* (c) Copyright 2002-2003 Xilinx Inc. +* All rights reserved. +* +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, write to the Free Software Foundation, Inc., +* 675 Mass Ave, Cambridge, MA 02139, USA. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xbasic_types.h +* +* This file contains basic types for Xilinx software IP. These types do not +* follow the standard naming convention with respect to using the component +* name in front of each name because they are considered to be primitives. +* +* @note +* +* This file contains items which are architecture dependent. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	 Who	Date	Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  12/14/01 First release
+*	rmm  05/09/03 Added "xassert always" macros to rid ourselves of diab
+*		      compiler warnings
+*
+* +******************************************************************************/ + +#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ +#define XBASIC_TYPES_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef NULL +#define NULL 0 +#endif +/** Null */ + +#define XCOMPONENT_IS_READY 0x11111111 /* component has been initialized */ +#define XCOMPONENT_IS_STARTED 0x22222222 /* component has been started */ + +/* the following constants and declarations are for unit test purposes and are + * designed to be used in test applications. + */ +#define XTEST_PASSED 0 +#define XTEST_FAILED 1 + +#define XASSERT_NONE 0 +#define XASSERT_OCCURRED 1 + +extern unsigned int XAssertStatus; +extern void XAssert(char *, int); + +/**************************** Type Definitions *******************************/ + +/** @name Primitive types + * These primitive types are created for transportability. + * They are dependent upon the target architecture. + * @{ + */ +#include + +typedef struct { + u32 Upper; + u32 Lower; +} Xuint64; + +/* Xilinx's unsigned integer types */ +typedef u32 Xuint32; +typedef u16 Xuint16; +typedef u8 Xuint8; + +/* and signed integer types */ +typedef s32 Xint32; +typedef s16 Xint16; +typedef s8 Xint8; + +#ifndef NULL +#define NULL 0 +#endif + +typedef unsigned long Xboolean; +#define XNULL NULL + +#define XTRUE 1 +#define XFALSE 0 + +/*@}*/ + +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber); + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return +* +* The upper 32 bits of the 64 bit word. +* +* @note +* +* None. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return +* +* The lower 32 bits of the 64 bit word. +* +* @note +* +* None. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do not return anything +* (void). This in conjunction with the XWaitInAssert boolean can be used to +* accomodate tests so that asserts which fail allow execution to continue. +* +* @param expression is the expression to evaluate. If it evaluates to false, +* the assert occurs. +* +* @return +* +* Returns void unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_VOID(expression) \ +{ \ + if (expression) { \ + XAssertStatus = XASSERT_NONE; \ + } else { \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* This assert macro is to be used for functions that do return a value. This in +* conjunction with the XWaitInAssert boolean can be used to accomodate tests so +* that asserts which fail allow execution to continue. +* +* @param expression is the expression to evaluate. If it evaluates to false, +* the assert occurs. +* +* @return +* +* Returns 0 unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_NONVOID(expression) \ +{ \ + if (expression) { \ + XAssertStatus = XASSERT_NONE; \ + } else { \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do not +* return anything (void). Use for instances where an assert should always +* occur. +* +* @return +* +* Returns void unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_VOID_ALWAYS() \ +{ \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* Always assert. This assert macro is to be used for functions that do return +* a value. Use for instances where an assert should always occur. +* +* @return +* +* Returns void unless the XWaitInAssert variable is true, in which case +* no return is made and an infinite loop is entered. +* +* @note +* +* None. +* +******************************************************************************/ +#define XASSERT_NONVOID_ALWAYS() \ +{ \ + XAssert(__FILE__, __LINE__); \ + XAssertStatus = XASSERT_OCCURRED; \ + return 0; \ +} + +#else + +#define XASSERT_VOID(expression) +#define XASSERT_VOID_ALWAYS() +#define XASSERT_NONVOID(expression) +#define XASSERT_NONVOID_ALWAYS() +#endif + +/************************** Function Prototypes ******************************/ + +void XAssertSetCallback(XAssertCallback Routine); + +#endif /* end of protection macro */ diff --git a/include/asm-microblaze/arch-microblaze/xio.h b/include/asm-microblaze/arch-microblaze/xio.h new file mode 100644 index 000000000..7eed327d4 --- /dev/null +++ b/include/asm-microblaze/arch-microblaze/xio.h @@ -0,0 +1,63 @@ +/* + * xio.h + * + * Defines XIo functions for Xilinx OCP in terms of Linux primitives + * + * Author: MontaVista Software, Inc. + * source@mvista.com + * + * 2002 (c) MontaVista, Software, Inc. This file is licensed under the terms + * of the GNU General Public License version 2. This program is licensed + * "as is" without any warranty of any kind, whether express or implied. + */ + +#ifndef XIO_H +#define XIO_H + +#include "xbasic_types.h" +#include + +typedef u32 XIo_Address; + +extern inline u8 +XIo_In8(XIo_Address InAddress) +{ + return (u8) in_8((volatile unsigned char *) InAddress); +} +extern inline u16 +XIo_In16(XIo_Address InAddress) +{ + return (u16) in_be16((volatile unsigned short *) InAddress); +} +extern inline u32 +XIo_In32(XIo_Address InAddress) +{ + return (u32) in_be32((volatile unsigned *) InAddress); +} +extern inline void +XIo_Out8(XIo_Address OutAddress, u8 Value) +{ + out_8((volatile unsigned char *) OutAddress, Value); +} +extern inline void +XIo_Out16(XIo_Address OutAddress, u16 Value) +{ + out_be16((volatile unsigned short *) OutAddress, Value); +} +extern inline void +XIo_Out32(XIo_Address OutAddress, u32 Value) +{ + out_be32((volatile unsigned *) OutAddress, Value); +} + +#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s))) +#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s))) +#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s))) +#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s))) + +#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s))) +#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s))) +#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s))) +#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s))) + +#endif /* XIO_H */ diff --git a/include/asm-microblaze/arch-microblaze/xuartlite_l.h b/include/asm-microblaze/arch-microblaze/xuartlite_l.h new file mode 100644 index 000000000..b381a0d7b --- /dev/null +++ b/include/asm-microblaze/arch-microblaze/xuartlite_l.h @@ -0,0 +1,256 @@ +/***************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002 Xilinx Inc. +* All rights reserved. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xuartlite_l.h +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the device. High-level driver functions +* are defined in xuartlite.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm  04/25/02 First release
+*
+* +*****************************************************************************/ + +#ifndef XUARTLITE_L_H /* prevent circular inclusions */ +#define XUARTLITE_L_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xbasic_types.h" +#include "xio.h" + +/************************** Constant Definitions ****************************/ + +/* UART Lite register offsets */ + +#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ +#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */ +#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */ +#define XUL_CONTROL_REG_OFFSET 12 /* control register, write only */ + +/* control register bit positions */ + +#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */ +#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */ +#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */ + +/* status register bit positions */ + +#define XUL_SR_PARITY_ERROR 0x80 +#define XUL_SR_FRAMING_ERROR 0x40 +#define XUL_SR_OVERRUN_ERROR 0x20 +#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */ +#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */ +#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */ +#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ + +/* the following constant specifies the size of the FIFOs, the size of the + * FIFOs includes the transmitter and receiver such that it is the total number + * of bytes that the UART can buffer + */ +#define XUL_FIFO_SIZE 16 + +/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a + * per instance basis + */ +#define XUL_STOP_BITS 1 + +/* Parity definitions + */ +#define XUL_PARITY_NONE 0 +#define XUL_PARITY_ODD 1 +#define XUL_PARITY_EVEN 2 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/***************************************************************************** +* +* Low-level driver macros and functions. The list below provides signatures +* to help the user use the macros. +* +* void XUartLite_mSetControlReg(u32 BaseAddress, u32 Mask) +* u32 XUartLite_mGetControlReg(u32 BaseAddress) +* u32 XUartLite_mGetStatusReg(u32 BaseAddress) +* +* Xboolean XUartLite_mIsReceiveEmpty(u32 BaseAddress) +* Xboolean XUartLite_mIsTransmitFull(u32 BaseAddress) +* Xboolean XUartLite_mIsIntrEnabled(u32 BaseAddress) +* +* void XUartLite_mEnableIntr(u32 BaseAddress) +* void XUartLite_mDisableIntr(u32 BaseAddress) +* +* void XUartLite_SendByte(u32 BaseAddress, u8 Data); +* u8 XUartLite_RecvByte(u32 BaseAddress); +* +*****************************************************************************/ + +/****************************************************************************/ +/** +* +* Set the contents of the control register. Use the XUL_CR_* constants defined +* above to create the bit-mask to be written to the register. +* +* @param BaseAddress is the base address of the device +* @param Mask is the 32-bit value to write to the control register +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mSetControlReg(BaseAddress, Mask) \ + XIo_Out32((BaseAddress) + XUL_CONTROL_REG_OFFSET, (Mask)) + + +/****************************************************************************/ +/** +* +* Get the contents of the control register. Use the XUL_CR_* constants defined +* above to interpret the bit-mask returned. +* +* @param BaseAddress is the base address of the device +* +* @return A 32-bit value representing the contents of the control register. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mGetControlReg(BaseAddress) \ + XIo_In32((BaseAddress) + XUL_CONTROL_REG_OFFSET) + + +/****************************************************************************/ +/** +* +* Get the contents of the status register. Use the XUL_SR_* constants defined +* above to interpret the bit-mask returned. +* +* @param BaseAddress is the base address of the device +* +* @return A 32-bit value representing the contents of the status register. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mGetStatusReg(BaseAddress) \ + XIo_In32((BaseAddress) + XUL_STATUS_REG_OFFSET) + + +/****************************************************************************/ +/** +* +* Check to see if the receiver has data. +* +* @param BaseAddress is the base address of the device +* +* @return XTRUE if the receiver is empty, XFALSE if there is data present. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mIsReceiveEmpty(BaseAddress) \ + (!(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA)) + + +/****************************************************************************/ +/** +* +* Check to see if the transmitter is full. +* +* @param BaseAddress is the base address of the device +* +* @return XTRUE if the transmitter is full, XFALSE otherwise. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mIsTransmitFull(BaseAddress) \ + (XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) + + +/****************************************************************************/ +/** +* +* Check to see if the interrupt is enabled. +* +* @param BaseAddress is the base address of the device +* +* @return XTRUE if the interrupt is enabled, XFALSE otherwise. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mIsIntrEnabled(BaseAddress) \ + (XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) + + +/****************************************************************************/ +/** +* +* Enable the device interrupt. Preserve the contents of the control register. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mEnableIntr(BaseAddress) \ + XUartLite_mSetControlReg((BaseAddress), \ + XUartLite_mGetControlReg((BaseAddress)) | XUL_CR_ENABLE_INTR) + + +/****************************************************************************/ +/** +* +* Disable the device interrupt. Preserve the contents of the control register. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mDisableIntr(BaseAddress) \ + XUartLite_mSetControlReg((BaseAddress), \ + XUartLite_mGetControlReg((BaseAddress)) & ~XUL_CR_ENABLE_INTR) + + +/************************** Function Prototypes *****************************/ + +void XUartLite_SendByte(u32 BaseAddress, u8 Data); +u8 XUartLite_RecvByte(u32 BaseAddress); + + +#endif /* end of protection macro */ diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h index 376786fca..a6e783424 100644 --- a/include/asm-microblaze/global_data.h +++ b/include/asm-microblaze/global_data.h @@ -52,9 +52,6 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31") diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h index 8804724bf..33590454c 100644 --- a/include/asm-microblaze/io.h +++ b/include/asm-microblaze/io.h @@ -16,8 +16,6 @@ #ifndef __MICROBLAZE_IO_H__ #define __MICROBLAZE_IO_H__ -#include - #define IO_SPACE_LIMIT 0xFFFFFFFF #define readb(addr) \ @@ -127,32 +125,4 @@ io_outsl (unsigned long port, const void *src, unsigned long count) #define ioremap_writethrough(physaddr, size) (physaddr) #define ioremap_fullcache(physaddr, size) (physaddr) -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - #endif /* __MICROBLAZE_IO_H__ */ diff --git a/include/asm-microblaze/platform.h b/include/asm-microblaze/platform.h new file mode 100644 index 000000000..2096cce45 --- /dev/null +++ b/include/asm-microblaze/platform.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_SUZAKU +#include +#endif diff --git a/include/asm-microblaze/serial_xuartlite.h b/include/asm-microblaze/serial_xuartlite.h new file mode 100644 index 000000000..6cd1e83b9 --- /dev/null +++ b/include/asm-microblaze/serial_xuartlite.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include diff --git a/include/asm-microblaze/suzaku.h b/include/asm-microblaze/suzaku.h new file mode 100644 index 000000000..c57a144d3 --- /dev/null +++ b/include/asm-microblaze/suzaku.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* System Register (GPIO) */ +#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000 +#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0) diff --git a/include/asm-microblaze/types.h b/include/asm-microblaze/types.h index 77094f62d..8c4bef287 100644 --- a/include/asm-microblaze/types.h +++ b/include/asm-microblaze/types.h @@ -25,9 +25,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif /* @@ -52,9 +52,6 @@ typedef unsigned long long u64; /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; #endif /* __KERNEL__ */ #endif /* _ASM_TYPES_H */ diff --git a/include/asm-microblaze/u-boot.h b/include/asm-microblaze/u-boot.h index 9db491ec9..e2035bd79 100644 --- a/include/asm-microblaze/u-boot.h +++ b/include/asm-microblaze/u-boot.h @@ -34,7 +34,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index 3a1e6d615..b8214b1c8 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -3,94 +3,16 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 99 Ralf Baechle - * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. + * Copyright (C) 1996 by Ralf Baechle + * Copyright (C) 2000 by Maciej W. Rozycki + * + * Defitions for the address spaces of the MIPS CPUs. */ -#ifndef _ASM_ADDRSPACE_H -#define _ASM_ADDRSPACE_H - -/* - * Configure language - */ -#ifdef __ASSEMBLY__ -#define _ATYPE_ -#define _ATYPE32_ -#define _ATYPE64_ -#define _CONST64_(x) x -#else -#define _ATYPE_ __PTRDIFF_TYPE__ -#define _ATYPE32_ int -#define _ATYPE64_ __s64 -#ifdef CONFIG_64BIT -#define _CONST64_(x) x ## L -#else -#define _CONST64_(x) x ## LL -#endif -#endif - -/* - * 32-bit MIPS address spaces - */ -#ifdef __ASSEMBLY__ -#define _ACAST32_ -#define _ACAST64_ -#else -#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ -#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ -#endif - -/* - * Returns the kernel segment base of a given address - */ -#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) - -/* - * Returns the physical address of a CKSEGx / XKPHYS address - */ -#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) -#define XPHYSADDR(a) ((_ACAST64_(a)) & \ - _CONST64_(0x000000ffffffffff)) - -#ifdef CONFIG_64BIT - -/* - * Memory segments (64bit kernel mode addresses) - * The compatibility segments use the full 64-bit sign extended value. Note - * the R8000 doesn't have them so don't reference these in generic MIPS code. - */ -#define XKUSEG _CONST64_(0x0000000000000000) -#define XKSSEG _CONST64_(0x4000000000000000) -#define XKPHYS _CONST64_(0x8000000000000000) -#define XKSEG _CONST64_(0xc000000000000000) -#define CKSEG0 _CONST64_(0xffffffff80000000) -#define CKSEG1 _CONST64_(0xffffffffa0000000) -#define CKSSEG _CONST64_(0xffffffffc0000000) -#define CKSEG3 _CONST64_(0xffffffffe0000000) - -#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) - -#else - -#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) - -/* - * Map an address to a certain kernel segment - */ -#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) -#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) -#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) -#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3) +#ifndef __ASM_MIPS_ADDRSPACE_H +#define __ASM_MIPS_ADDRSPACE_H /* * Memory segments (32bit kernel mode addresses) - * These are the traditional names used in the 32-bit universe. */ #define KUSEG 0x00000000 #define KSEG0 0x80000000 @@ -98,68 +20,63 @@ #define KSEG2 0xc0000000 #define KSEG3 0xe0000000 -#define CKUSEG 0x00000000 -#define CKSEG0 0x80000000 -#define CKSEG1 0xa0000000 -#define CKSEG2 0xc0000000 -#define CKSEG3 0xe0000000 +#define K0BASE KSEG0 +/* + * Returns the kernel segment base of a given address + */ +#ifndef __ASSEMBLY__ +#define KSEGX(a) (((unsigned long)(a)) & 0xe0000000) +#else +#define KSEGX(a) ((a) & 0xe0000000) #endif /* - * Cache modes for XKPHYS address conversion macros + * Returns the physical address of a KSEG0/KSEG1 address */ -#define K_CALG_COH_EXCL1_NOL2 0 -#define K_CALG_COH_SHRL1_NOL2 1 -#define K_CALG_UNCACHED 2 -#define K_CALG_NONCOHERENT 3 -#define K_CALG_COH_EXCL 4 -#define K_CALG_COH_SHAREABLE 5 -#define K_CALG_NOTUSED 6 -#define K_CALG_UNCACHED_ACCEL 7 - -/* - * 64-bit address conversions - */ -#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) -#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) -#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ - (_CONST64_(cm) << 59) | (a)) +#ifndef __ASSEMBLY__ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) +#else +#define PHYSADDR(a) ((a) & 0x1fffffff) +#endif /* * Returns the uncached address of a sdram address */ #ifndef __ASSEMBLY__ -#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229) +#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229) /* We use a 36 bit physical address map here and cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) -#else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) KSEG1ADDR(a) -#endif /* CONFIG_SOC_AU1X00 */ +#else /* !CONFIG_AU1X00 */ +#define UNCACHED_SDRAM(a) PHYSADDR(a) +#endif /* CONFIG_AU1X00 */ #endif /* __ASSEMBLY__ */ - /* - * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting - * the region, 3 bits for the CCA mode. This leaves 59 bits of which the - * R8000 implements most with its 48-bit physical address space. + * Map an address to a certain kernel segment */ -#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ - -#ifndef CONFIG_CPU_R8000 - -/* - * The R8000 doesn't have the 32-bit compat spaces so we don't define them - * in order to catch bugs in the source code. - */ - -#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) -#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ - +#ifndef __ASSEMBLY__ +#define KSEG0ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG0)) +#define KSEG1ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG1)) +#define KSEG2ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG2)) +#define KSEG3ADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | KSEG3)) +#else +#define KSEG0ADDR(a) (((a) & 0x1fffffff) | KSEG0) +#define KSEG1ADDR(a) (((a) & 0x1fffffff) | KSEG1) +#define KSEG2ADDR(a) (((a) & 0x1fffffff) | KSEG2) +#define KSEG3ADDR(a) (((a) & 0x1fffffff) | KSEG3) #endif -#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) -#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) +/* + * Memory segments (64bit kernel mode addresses) + */ +#define XKUSEG 0x0000000000000000 +#define XKSSEG 0x4000000000000000 +#define XKPHYS 0x8000000000000000 +#define XKSEG 0xc000000000000000 +#define CKSEG0 0xffffffff80000000 +#define CKSEG1 0xffffffffa0000000 +#define CKSSEG 0xffffffffc0000000 +#define CKSEG3 0xffffffffe0000000 -#endif /* _ASM_ADDRSPACE_H */ +#endif /* __ASM_MIPS_ADDRSPACE_H */ diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h index 2a948e8fe..a4e9947d9 100644 --- a/include/asm-mips/au1x00.h +++ b/include/asm-mips/au1x00.h @@ -5,7 +5,7 @@ * * Copyright 2000,2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * ppopov@mvista.com or source@mvista.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -137,7 +137,7 @@ static __inline__ int au_ffs(int x) #define CP0_DEBUG $23 /* SDRAM Controller */ -#ifdef CONFIG_SOC_AU1550 +#ifdef CONFIG_AU1550 #define MEM_SDMODE0 0xB4000800 #define MEM_SDMODE1 0xB4000808 @@ -156,7 +156,7 @@ static __inline__ int au_ffs(int x) #define MEM_SDWRMD1 0xB4000888 #define MEM_SDWRMD2 0xB4000890 -#else /* CONFIG_SOC_AU1550 */ +#else /* CONFIG_AU1550 */ #define MEM_SDMODE0 0xB4000000 #define MEM_SDMODE1 0xB4000004 @@ -174,7 +174,7 @@ static __inline__ int au_ffs(int x) #define MEM_SDWRMD1 0xB4000028 #define MEM_SDWRMD2 0xB400002C -#endif /* CONFIG_SOC_AU1550 */ +#endif /* CONFIG_AU1550 */ #define MEM_SDSLEEP 0xB4000030 #define MEM_SDSMCKE 0xB4000034 diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index b5e685feb..b9604cf20 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h @@ -1,62 +1,18 @@ -/* +/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $ + * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 99, 2003 by Ralf Baechle + * Copyright (C) by Ralf Baechle */ -#ifndef _ASM_BYTEORDER_H -#define _ASM_BYTEORDER_H +#ifndef _MIPS_BYTEORDER_H +#define _MIPS_BYTEORDER_H #include #ifdef __GNUC__ -#ifdef CONFIG_CPU_MIPSR2 - -static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) -{ - __asm__( - " wsbh %0, %1 \n" - : "=r" (x) - : "r" (x)); - - return x; -} -#define __arch__swab16(x) ___arch__swab16(x) - -static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) -{ - __asm__( - " wsbh %0, %1 \n" - " rotr %0, %0, 16 \n" - : "=r" (x) - : "r" (x)); - - return x; -} -#define __arch__swab32(x) ___arch__swab32(x) - -#ifdef CONFIG_CPU_MIPS64_R2 - -static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) -{ - __asm__( - " dsbh %0, %1 \n" - " dshd %0, %0 \n" - " drotr %0, %0, 32 \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -#define __arch__swab64(x) ___arch__swab64(x) - -#endif /* CONFIG_CPU_MIPS64_R2 */ - -#endif /* CONFIG_CPU_MIPSR2 */ - #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) # define __BYTEORDER_HAS_U64__ # define __SWAB_64_THRU_32__ @@ -64,12 +20,12 @@ static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) #endif /* __GNUC__ */ -#if defined(__MIPSEB__) +#if defined (__MIPSEB__) # include -#elif defined(__MIPSEL__) +#elif defined (__MIPSEL__) # include #else # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" #endif -#endif /* _ASM_BYTEORDER_H */ +#endif /* _MIPS_BYTEORDER_H */ diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h index f3ce72186..9cc2b8721 100644 --- a/include/asm-mips/cachectl.h +++ b/include/asm-mips/cachectl.h @@ -1,12 +1,10 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * cachectl.h -- defines for MIPS cache control system calls * * Copyright (C) 1994, 1995, 1996 by Ralf Baechle */ -#ifndef _ASM_CACHECTL -#define _ASM_CACHECTL +#ifndef __ASM_MIPS_CACHECTL +#define __ASM_MIPS_CACHECTL /* * Options for cacheflush system call @@ -23,4 +21,4 @@ #define CACHEABLE 0 /* make pages cacheable */ #define UNCACHEABLE 1 /* make pages uncacheable */ -#endif /* _ASM_CACHECTL */ +#endif /* __ASM_MIPS_CACHECTL */ diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index 70bcad769..66b0b361f 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h @@ -5,81 +5,43 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle - * (C) Copyright 1999 Silicon Graphics, Inc. + * (C) Copyright 1996, 1997 by Ralf Baechle */ -#ifndef __ASM_CACHEOPS_H -#define __ASM_CACHEOPS_H +#ifndef __ASM_MIPS_CACHEOPS_H +#define __ASM_MIPS_CACHEOPS_H /* - * Cache Operations available on all MIPS processors with R4000-style caches + * Cache Operations */ #define Index_Invalidate_I 0x00 #define Index_Writeback_Inv_D 0x01 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 -#else -#define Hit_Invalidate_I 0x10 -#endif -#define Hit_Invalidate_D 0x11 -#define Hit_Writeback_Inv_D 0x15 - -/* - * R4000-specific cacheops - */ -#define Create_Dirty_Excl_D 0x0d -#define Fill 0x14 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 - -/* - * R4000SC and R4400SC-specific cacheops - */ #define Index_Invalidate_SI 0x02 #define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 #define Index_Load_Tag_SI 0x06 #define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 #define Index_Store_Tag_SI 0x0A #define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d #define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 #define Hit_Invalidate_SI 0x12 #define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 + /* 0x16 is unused */ #define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + /* 0x1a is unused */ #define Hit_Writeback_SD 0x1b + /* 0x1c is unused */ + /* 0x1e is unused */ #define Hit_Set_Virtual_SI 0x1e #define Hit_Set_Virtual_SD 0x1f -/* - * R5000-specific cacheops - */ -#define R5K_Page_Invalidate_S 0x17 - -/* - * RM7000-specific cacheops - */ -#define Page_Invalidate_T 0x16 - -/* - * R10000-specific cacheops - * - * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. - * Most of the _S cacheops are identical to the R4000SC _SD cacheops. - */ -#define Index_Writeback_Inv_S 0x03 -#define Index_Load_Tag_S 0x07 -#define Index_Store_Tag_S 0x0B -#define Hit_Invalidate_S 0x13 -#define Cache_Barrier 0x14 -#define Hit_Writeback_Inv_S 0x17 -#define Index_Load_Data_I 0x18 -#define Index_Load_Data_D 0x19 -#define Index_Load_Data_S 0x1b -#define Index_Store_Data_I 0x1c -#define Index_Store_Data_D 0x1d -#define Index_Store_Data_S 0x1f - -#endif /* __ASM_CACHEOPS_H */ +#endif /* __ASM_MIPS_CACHEOPS_H */ diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h index ecee6dea6..a024194ba 100644 --- a/include/asm-mips/global_data.h +++ b/include/asm-mips/global_data.h @@ -41,7 +41,7 @@ typedef struct global_data { unsigned long flags; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ + unsigned long ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ @@ -54,9 +54,6 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0") diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 3a0f33f20..857fb0302 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -71,21 +71,7 @@ * instruction, so the lower 16 bits must be zero. Should be true on * on any sane architecture; generic code does not use this assumption. */ -extern const unsigned long mips_io_port_base; - -/* - * Gcc will generate code to load the value of mips_io_port_base after each - * function call which may be fairly wasteful in some cases. So we don't - * play quite by the book. We tell gcc mips_io_port_base is a long variable - * which solves the code generation issue. Now we need to violate the - * aliasing rules a little to make initialization possible and finally we - * will need the barrier() to fight side effects of the aliasing chat. - * This trickery will eventually collapse under gcc's optimizer. Oh well. - */ -static inline void set_io_port_base(unsigned long base) -{ - * (unsigned long *) &mips_io_port_base = base; -} +extern unsigned long mips_io_port_base; /* * Thanks to James van Artsdalen for a better timing-fix than @@ -120,7 +106,7 @@ static inline void set_io_port_base(unsigned long base) */ extern inline unsigned long virt_to_phys(volatile void * address) { - return CPHYSADDR(address); + return PHYSADDR(address); } extern inline void * phys_to_virt(unsigned long address) @@ -133,7 +119,7 @@ extern inline void * phys_to_virt(unsigned long address) */ extern inline unsigned long virt_to_bus(volatile void * address) { - return CPHYSADDR(address); + return PHYSADDR(address); } extern inline void * bus_to_virt(unsigned long address) @@ -461,32 +447,4 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); #define dma_cache_wback(start,size) _dma_cache_wback(start,size) #define dma_cache_inv(start,size) _dma_cache_inv(start,size) -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - #endif /* _ASM_IO_H */ diff --git a/include/asm-mips/isadep.h b/include/asm-mips/isadep.h index 24c6cda79..3cd1eb8eb 100644 --- a/include/asm-mips/isadep.h +++ b/include/asm-mips/isadep.h @@ -1,15 +1,16 @@ /* - * Various ISA level dependent constants. + * Various ISA level dependant constants. * Most of the following constants reflect the different layout * of Coprocessor 0 registers. * * Copyright (c) 1998 Harald Koerfgen */ +#include #ifndef __ASM_ISADEP_H #define __ASM_ISADEP_H -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) +#if defined(CONFIG_CPU_R3000) /* * R2000 or R3000 */ diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index be7e5c65e..0586c53d3 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -7,8 +7,8 @@ * Copyright (C) 2000 Silicon Graphics, Inc. * Modified for further R[236]000 support by Paul M. Antoine, 1996. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 07 MIPS Technologies, Inc. - * Copyright (C) 2003, 2004 Maciej W. Rozycki + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2003 Maciej W. Rozycki */ #ifndef _ASM_MIPSREGS_H #define _ASM_MIPSREGS_H @@ -28,15 +28,6 @@ #define STR(x) __STR(x) #endif -/* - * Configure language - */ -#ifdef __ASSEMBLY__ -#define _ULCAST_ -#else -#define _ULCAST_ (unsigned long) -#endif - /* * Coprocessor 0 register names */ @@ -64,15 +55,12 @@ #define CP0_XCONTEXT $20 #define CP0_FRAMEMASK $21 #define CP0_DIAGNOSTIC $22 -#define CP0_DEBUG $23 -#define CP0_DEPC $24 #define CP0_PERFORMANCE $25 #define CP0_ECC $26 #define CP0_CACHEERR $27 #define CP0_TAGLO $28 #define CP0_TAGHI $29 #define CP0_ERROREPC $30 -#define CP0_DESAVE $31 /* * R4640/R4650 cp0 register names. These registers are listed @@ -94,27 +82,11 @@ #define CP0_S1_DERRADDR0 $26 #define CP0_S1_DERRADDR1 $27 #define CP0_S1_INTCONTROL $20 - -/* - * Coprocessor 0 Set 2 register names - */ -#define CP0_S2_SRSCTL $12 /* MIPSR2 */ - -/* - * Coprocessor 0 Set 3 register names - */ -#define CP0_S3_SRSMAP $12 /* MIPSR2 */ - -/* - * TX39 Series - */ -#define CP0_TX39_CACHE $7 - /* * Coprocessor 1 (FPU) register names */ -#define CP1_REVISION $0 -#define CP1_STATUS $31 +#define CP1_REVISION $0 +#define CP1_STATUS $31 /* * FPU Status Register Values @@ -123,113 +95,230 @@ * Status Register Values */ -#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ -#define FPU_CSR_COND 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ -#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ -#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ -#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ -#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ -#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ -#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ -#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ +#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ +#define FPU_CSR_COND 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND0 0x00800000 /* $fcc0 */ +#define FPU_CSR_COND1 0x02000000 /* $fcc1 */ +#define FPU_CSR_COND2 0x04000000 /* $fcc2 */ +#define FPU_CSR_COND3 0x08000000 /* $fcc3 */ +#define FPU_CSR_COND4 0x10000000 /* $fcc4 */ +#define FPU_CSR_COND5 0x20000000 /* $fcc5 */ +#define FPU_CSR_COND6 0x40000000 /* $fcc6 */ +#define FPU_CSR_COND7 0x80000000 /* $fcc7 */ /* * X the exception cause indicator * E the exception enable * S the sticky/flag bit - */ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 +*/ +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 /* rounding mode */ -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ + /* * Values for PageMask register */ +#include #ifdef CONFIG_CPU_VR41XX - -/* Why doesn't stupidity hurt ... */ - -#define PM_1K 0x00000000 -#define PM_4K 0x00001800 -#define PM_16K 0x00007800 -#define PM_64K 0x0001f800 -#define PM_256K 0x0007f800 - +#define PM_1K 0x00000000 +#define PM_4K 0x00001800 +#define PM_16K 0x00007800 +#define PM_64K 0x0001f800 +#define PM_256K 0x0007f800 #else - -#define PM_4K 0x00000000 -#define PM_16K 0x00006000 -#define PM_64K 0x0001e000 -#define PM_256K 0x0007e000 -#define PM_1M 0x001fe000 -#define PM_4M 0x007fe000 -#define PM_16M 0x01ffe000 -#define PM_64M 0x07ffe000 -#define PM_256M 0x1fffe000 - +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 #endif /* * Values used for computation of new tlb entries */ -#define PL_4K 12 -#define PL_16K 14 -#define PL_64K 16 -#define PL_256K 18 -#define PL_1M 20 -#define PL_4M 22 -#define PL_16M 24 -#define PL_64M 26 -#define PL_256M 28 +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 + +/* + * Macros to access the system control coprocessor + */ +#define read_32bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "mfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +#define read_32bit_cp0_set1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +/* + * For now use this only with interrupts disabled! + */ +#define read_64bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0,"STR(source)"\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res;}) + +#define write_32bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + "mtc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_32bit_cp0_set1_register(register,value) \ + __asm__ __volatile__( \ + "ctc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_64bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%0,"STR(register)"\n\t" \ + ".set\tmips0" \ + : : "r" (value)) + +/* + * This should be changed when we get a compiler that support the MIPS32 ISA. + */ +#define read_mips32_cp0_config1() \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + :"=r" (__res)); \ + __res;}) + +#define tlb_write_indexed() \ + __asm__ __volatile__( \ + ".set noreorder\n\t" \ + "tlbwi\n\t" \ +".set reorder") /* * R4x00 interrupt enable / cause bits */ -#define IE_SW0 (_ULCAST_(1) << 8) -#define IE_SW1 (_ULCAST_(1) << 9) -#define IE_IRQ0 (_ULCAST_(1) << 10) -#define IE_IRQ1 (_ULCAST_(1) << 11) -#define IE_IRQ2 (_ULCAST_(1) << 12) -#define IE_IRQ3 (_ULCAST_(1) << 13) -#define IE_IRQ4 (_ULCAST_(1) << 14) -#define IE_IRQ5 (_ULCAST_(1) << 15) +#define IE_SW0 (1<< 8) +#define IE_SW1 (1<< 9) +#define IE_IRQ0 (1<<10) +#define IE_IRQ1 (1<<11) +#define IE_IRQ2 (1<<12) +#define IE_IRQ3 (1<<13) +#define IE_IRQ4 (1<<14) +#define IE_IRQ5 (1<<15) /* * R4x00 interrupt cause bits */ -#define C_SW0 (_ULCAST_(1) << 8) -#define C_SW1 (_ULCAST_(1) << 9) -#define C_IRQ0 (_ULCAST_(1) << 10) -#define C_IRQ1 (_ULCAST_(1) << 11) -#define C_IRQ2 (_ULCAST_(1) << 12) -#define C_IRQ3 (_ULCAST_(1) << 13) -#define C_IRQ4 (_ULCAST_(1) << 14) -#define C_IRQ5 (_ULCAST_(1) << 15) +#define C_SW0 (1<< 8) +#define C_SW1 (1<< 9) +#define C_IRQ0 (1<<10) +#define C_IRQ1 (1<<11) +#define C_IRQ2 (1<<12) +#define C_IRQ3 (1<<13) +#define C_IRQ4 (1<<14) +#define C_IRQ5 (1<<15) + +#ifndef _LANGUAGE_ASSEMBLY +/* + * Manipulate the status register. + * Mostly used to access the interrupt bits. + */ +#define __BUILD_SET_CP0(name,register) \ +extern __inline__ unsigned int \ +set_cp0_##name(unsigned int set) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res |= set; \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} \ + \ +extern __inline__ unsigned int \ +clear_cp0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res &= ~clear; \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} \ + \ +extern __inline__ unsigned int \ +change_cp0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res &= ~change; \ + res |= (new & change); \ + if(change) \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} + +__BUILD_SET_CP0(status,CP0_STATUS) +__BUILD_SET_CP0(cause,CP0_CAUSE) +__BUILD_SET_CP0(config,CP0_CONFIG) + +#endif /* defined (_LANGUAGE_ASSEMBLY) */ /* * Bitfields in the R4xx0 cp0 status register @@ -243,21 +332,14 @@ # define KSU_KERNEL 0x00000000 #define ST0_UX 0x00000020 #define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 +#define ST0_KX 0x00000080 #define ST0_DE 0x00010000 #define ST0_CE 0x00020000 -/* - * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate - * cacheops in userspace. This bit exists only on RM7000 and RM9000 - * processors. - */ -#define ST0_CO 0x08000000 - /* * Bitfields in the R[23]000 cp0 status register. */ -#define ST0_IEC 0x00000001 +#define ST0_IEC 0x00000001 #define ST0_KUC 0x00000002 #define ST0_IEP 0x00000004 #define ST0_KUP 0x00000008 @@ -271,36 +353,31 @@ /* * Bits specific to the R4640/R4650 */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) - -/* - * Enable the MIPS MDMX and DSP ASEs - */ -#define ST0_MX 0x01000000 +#define ST0_UM (1 << 4) +#define ST0_IL (1 << 23) +#define ST0_DL (1 << 24) /* * Bitfields in the TX39 family CP0 Configuration Register 3 */ #define TX39_CONF_ICS_SHIFT 19 #define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 #define TX39_CONF_DCS_SHIFT 16 #define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 #define TX39_CONF_RF_SHIFT 10 #define TX39_CONF_RF_MASK 0x00000c00 #define TX39_CONF_DOZE 0x00000200 @@ -318,40 +395,39 @@ */ #define ST0_IM 0x0000ff00 #define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSF_IP0 (1 << 8) #define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSF_IP1 (1 << 9) #define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSF_IP2 (1 << 10) #define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSF_IP3 (1 << 11) #define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSF_IP4 (1 << 12) #define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSF_IP5 (1 << 13) #define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSF_IP6 (1 << 14) #define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSF_IP7 (1 << 15) #define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSF_IP8 (1 << 0) #define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSF_IP9 (1 << 1) #define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSF_IP10 (1 << 2) #define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSF_IP11 (1 << 3) #define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSF_IP12 (1 << 4) #define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSF_IP13 (1 << 5) #define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSF_IP14 (1 << 6) #define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define STATUSF_IP15 (1 << 7) #define ST0_CH 0x00040000 #define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 #define ST0_BEV 0x00400000 #define ST0_RE 0x02000000 #define ST0_FR 0x04000000 @@ -368,36 +444,35 @@ * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. */ #define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEF_EXCCODE (31 << 2) #define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEF_IP (255 << 8) #define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEF_IP0 (1 << 8) #define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEF_IP1 (1 << 9) #define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEF_IP2 (1 << 10) #define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEF_IP3 (1 << 11) #define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEF_IP4 (1 << 12) #define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEF_IP5 (1 << 13) #define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEF_IP6 (1 << 14) #define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEF_IP7 (1 << 15) #define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEF_IV (1 << 23) #define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEF_CE (3 << 28) #define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) +#define CAUSEF_BD (1 << 31) /* - * Bits in the coprocessor 0 config register. + * Bits in the coprozessor 0 config register. */ -/* Generic bits. */ #define CONF_CM_CACHABLE_NO_WA 0 #define CONF_CM_CACHABLE_WA 1 #define CONF_CM_UNCACHED 2 @@ -407,958 +482,66 @@ #define CONF_CM_CACHABLE_CUW 6 #define CONF_CM_CACHABLE_ACCELERATED 7 #define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) - -/* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) - -/* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) - -/* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) - -/* Bits specific to the RM7000. */ -#define RM7K_CONF_SE (_ULCAST_(1) << 3) -#define RM7K_CONF_TE (_ULCAST_(1) << 12) -#define RM7K_CONF_CLK (_ULCAST_(1) << 16) -#define RM7K_CONF_TC (_ULCAST_(1) << 17) -#define RM7K_CONF_SI (_ULCAST_(3) << 20) -#define RM7K_CONF_SC (_ULCAST_(1) << 31) - -/* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) - -/* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_P4K (_ULCAST_(1) << 13) -#define VR41_CONF_BP (_ULCAST_(1) << 16) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) - -/* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) - -/* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) - -/* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) +#define CONF_DB (1 << 4) +#define CONF_IB (1 << 5) +#define CONF_SC (1 << 17) +#define CONF_AC (1 << 23) +#define CONF_HALT (1 << 25) /* - * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. - */ -#define MIPS_CONF1_FP (_ULCAST_(1) << 0) -#define MIPS_CONF1_EP (_ULCAST_(1) << 1) -#define MIPS_CONF1_CA (_ULCAST_(1) << 2) -#define MIPS_CONF1_WR (_ULCAST_(1) << 3) -#define MIPS_CONF1_PC (_ULCAST_(1) << 4) -#define MIPS_CONF1_MD (_ULCAST_(1) << 5) -#define MIPS_CONF1_C2 (_ULCAST_(1) << 6) -#define MIPS_CONF1_DA (_ULCAST_(7) << 7) -#define MIPS_CONF1_DL (_ULCAST_(7) << 10) -#define MIPS_CONF1_DS (_ULCAST_(7) << 13) -#define MIPS_CONF1_IA (_ULCAST_(7) << 16) -#define MIPS_CONF1_IL (_ULCAST_(7) << 19) -#define MIPS_CONF1_IS (_ULCAST_(7) << 22) -#define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) - -#define MIPS_CONF2_SA (_ULCAST_(15)<< 0) -#define MIPS_CONF2_SL (_ULCAST_(15)<< 4) -#define MIPS_CONF2_SS (_ULCAST_(15)<< 8) -#define MIPS_CONF2_SU (_ULCAST_(15)<< 12) -#define MIPS_CONF2_TA (_ULCAST_(15)<< 16) -#define MIPS_CONF2_TL (_ULCAST_(15)<< 20) -#define MIPS_CONF2_TS (_ULCAST_(15)<< 24) -#define MIPS_CONF2_TU (_ULCAST_(7) << 28) - -#define MIPS_CONF3_TL (_ULCAST_(1) << 0) -#define MIPS_CONF3_SM (_ULCAST_(1) << 1) -#define MIPS_CONF3_MT (_ULCAST_(1) << 2) -#define MIPS_CONF3_SP (_ULCAST_(1) << 4) -#define MIPS_CONF3_VINT (_ULCAST_(1) << 5) -#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) -#define MIPS_CONF3_LPA (_ULCAST_(1) << 7) -#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) -#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) - -#define MIPS_CONF7_WII (_ULCAST_(1) << 31) - -#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) - -/* - * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. - */ -#define MIPS_FPIR_S (_ULCAST_(1) << 16) -#define MIPS_FPIR_D (_ULCAST_(1) << 17) -#define MIPS_FPIR_PS (_ULCAST_(1) << 18) -#define MIPS_FPIR_3D (_ULCAST_(1) << 19) -#define MIPS_FPIR_W (_ULCAST_(1) << 20) -#define MIPS_FPIR_L (_ULCAST_(1) << 21) -#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) - -#ifndef __ASSEMBLY__ - -/* - * Functions to access the R10000 performance counters. These are basically - * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit - * performance counter number encoded into bits 1 ... 5 of the instruction. - * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware - * disassembler these will look like an access to sel 0 or 1. - */ -#define read_r10k_perf_cntr(counter) \ -({ \ - unsigned int __res; \ - __asm__ __volatile__( \ - "mfpc\t%0, %1" \ - : "=r" (__res) \ - : "i" (counter)); \ - \ - __res; \ -}) - -#define write_r10k_perf_cntr(counter,val) \ -do { \ - __asm__ __volatile__( \ - "mtpc\t%0, %1" \ - : \ - : "r" (val), "i" (counter)); \ -} while (0) - -#define read_r10k_perf_event(counter) \ -({ \ - unsigned int __res; \ - __asm__ __volatile__( \ - "mfps\t%0, %1" \ - : "=r" (__res) \ - : "i" (counter)); \ - \ - __res; \ -}) - -#define write_r10k_perf_cntl(counter,val) \ -do { \ - __asm__ __volatile__( \ - "mtps\t%0, %1" \ - : \ - : "r" (val), "i" (counter)); \ -} while (0) - -/* - * Macros to access the system control coprocessor - */ - -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __read_64bit_c0_register(source, sel) \ -({ unsigned long long __res; \ - if (sizeof(unsigned long) == 4) \ - __res = __read_64bit_c0_split(source, sel); \ - else if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -#define __write_64bit_c0_register(register, sel, value) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_64bit_c0_split(register, sel, value); \ - else if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ -} while (0) - -#define __read_ulong_c0_register(reg, sel) \ - ((sizeof(unsigned long) == 4) ? \ - (unsigned long) __read_32bit_c0_register(reg, sel) : \ - (unsigned long) __read_64bit_c0_register(reg, sel)) - -#define __write_ulong_c0_register(reg, sel, val) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_32bit_c0_register(reg, sel, val); \ - else \ - __write_64bit_c0_register(reg, sel, val); \ -} while (0) - -/* - * On RM7000/RM9000 these are uses to access cop0 set 1 registers - */ -#define __read_32bit_c0_ctrl_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - "cfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - __res; \ -}) - -#define __write_32bit_c0_ctrl_register(register, value) \ -do { \ - __asm__ __volatile__( \ - "ctc0\t%z0, " #register "\n\t" \ - : : "Jr" ((unsigned int)(value))); \ -} while (0) - -/* - * These versions are only needed for systems with more than 38 bits of - * physical address space running the 32-bit kernel. That's none atm :-) - */ -#define __read_64bit_c0_split(source, sel) \ -({ \ - unsigned long long __val; \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (__val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (__val)); \ - local_irq_restore(__flags); \ - \ - __val; \ -}) - -#define __write_64bit_c0_split(source, sel, val) \ -do { \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - local_irq_restore(__flags); \ -} while (0) - -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) - -#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) - -#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) - -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) - -#define read_c0_context() __read_ulong_c0_register($4, 0) -#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) - -#define read_c0_userlocal() __read_ulong_c0_register($4, 2) -#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) - -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) - -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) - -#define read_c0_info() __read_32bit_c0_register($7, 0) - -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) - -#define read_c0_badvaddr() __read_ulong_c0_register($8, 0) -#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) - -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) - -#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ -#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) - -#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ -#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) - -#define read_c0_entryhi() __read_ulong_c0_register($10, 0) -#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) - -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) - -#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ -#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) - -#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ -#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) - -#define read_c0_status() __read_32bit_c0_register($12, 0) -#ifdef CONFIG_MIPS_MT_SMTC -#define write_c0_status(val) \ -do { \ - __write_32bit_c0_register($12, 0, val); \ - __ehb(); \ -} while (0) -#else -/* - * Legacy non-SMTC code, which may be hazardous - * but which might not support EHB - */ -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) -#endif /* CONFIG_MIPS_MT_SMTC */ - -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) - -#define read_c0_epc() __read_ulong_c0_register($14, 0) -#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) - -#define read_c0_prid() __read_32bit_c0_register($15, 0) - -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define read_c0_config4() __read_32bit_c0_register($16, 4) -#define read_c0_config5() __read_32bit_c0_register($16, 5) -#define read_c0_config6() __read_32bit_c0_register($16, 6) -#define read_c0_config7() __read_32bit_c0_register($16, 7) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) -#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) -#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) -#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) -#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) - -/* - * The WatchLo register. There may be upto 8 of them. - */ -#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) -#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) -#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) -#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) -#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) -#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) -#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) -#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) -#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) -#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) -#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) -#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) -#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) -#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) -#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) -#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) - -/* - * The WatchHi register. There may be upto 8 of them. - */ -#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) -#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) -#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) -#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) -#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) -#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) -#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) -#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) - -#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) -#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) -#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) -#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) -#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) -#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) -#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) -#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) - -#define read_c0_xcontext() __read_ulong_c0_register($20, 0) -#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) - -#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) -#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) - -#define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) - -/* RM9000 PerfControl performance counter control register */ -#define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) -#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) - -#define read_c0_diag() __read_32bit_c0_register($22, 0) -#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) - -#define read_c0_diag1() __read_32bit_c0_register($22, 1) -#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) - -#define read_c0_diag2() __read_32bit_c0_register($22, 2) -#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) - -#define read_c0_diag3() __read_32bit_c0_register($22, 3) -#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) - -#define read_c0_diag4() __read_32bit_c0_register($22, 4) -#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) - -#define read_c0_diag5() __read_32bit_c0_register($22, 5) -#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) - -#define read_c0_debug() __read_32bit_c0_register($23, 0) -#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) - -#define read_c0_depc() __read_ulong_c0_register($24, 0) -#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) - -/* - * MIPS32 / MIPS64 performance counters - */ -#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) -#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) -#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) -#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) -#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) -#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) -#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) -#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) -#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) -#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) -#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) -#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) -#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) -#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) -#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) -#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) - -/* RM9000 PerfCount performance counter register */ -#define read_c0_perfcount() __read_64bit_c0_register($25, 0) -#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) - -#define read_c0_ecc() __read_32bit_c0_register($26, 0) -#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) - -#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) - -#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) - -#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) - -#define read_c0_taglo() __read_32bit_c0_register($28, 0) -#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) - -#define read_c0_dtaglo() __read_32bit_c0_register($28, 2) -#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) - -#define read_c0_taghi() __read_32bit_c0_register($29, 0) -#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) - -#define read_c0_errorepc() __read_ulong_c0_register($30, 0) -#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) - -/* MIPSR2 */ -#define read_c0_hwrena() __read_32bit_c0_register($7, 0) -#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) - -#define read_c0_intctl() __read_32bit_c0_register($12, 1) -#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) - -#define read_c0_srsctl() __read_32bit_c0_register($12, 2) -#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) - -#define read_c0_srsmap() __read_32bit_c0_register($12, 3) -#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) - -#define read_c0_ebase() __read_32bit_c0_register($15, 1) -#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) - -/* - * Macros to access the floating point coprocessor control registers - */ -#define read_32bit_cp1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "cfc1\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) - -#define rddsp(mask) \ -({ \ - unsigned int __res; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # rddsp $1, %x1 \n" \ - " .word 0x7c000cb8 | (%x1 << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__res) \ - : "i" (mask)); \ - __res; \ -}) - -#define wrdsp(val, mask) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # wrdsp $1, %x1 \n" \ - " .word 0x7c2004f8 | (%x1 << 11) \n" \ - " .set pop \n" \ - : \ - : "r" (val), "i" (mask)); \ -} while (0) - -#define mfhi0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac0 \n" \ - " .word 0x00000810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac1 \n" \ - " .word 0x00200810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac2 \n" \ - " .word 0x00400810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mfhi3() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mfhi %0, $ac3 \n" \ - " .word 0x00600810 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo0() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac0 \n" \ - " .word 0x00000812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo1() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac1 \n" \ - " .word 0x00200812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo2() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac2 \n" \ - " .word 0x00400812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mflo3() \ -({ \ - unsigned long __treg; \ - \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " # mflo %0, $ac3 \n" \ - " .word 0x00600812 \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ - : "=r" (__treg)); \ - __treg; \ -}) - -#define mthi0(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac0 \n" \ - " .word 0x00200011 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mthi1(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac1 \n" \ - " .word 0x00200811 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mthi2(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac2 \n" \ - " .word 0x00201011 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mthi3(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mthi $1, $ac3 \n" \ - " .word 0x00201811 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo0(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac0 \n" \ - " .word 0x00200013 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo1(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac1 \n" \ - " .word 0x00200813 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo2(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac2 \n" \ - " .word 0x00201013 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -#define mtlo3(x) \ -do { \ - __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mtlo $1, $ac3 \n" \ - " .word 0x00201813 \n" \ - " .set pop \n" \ - : \ - : "r" (x)); \ -} while (0) - -/* - * TLB operations. + * R10000 performance counter definitions. * - * It is responsibility of the caller to take care of any TLB hazards. + * FIXME: The R10000 performance counter opens a nice way to implement CPU + * time accounting with a precission of one cycle. I don't have + * R10000 silicon but just a manual, so ... */ -static inline void tlb_probe(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbp\n\t" - ".set reorder"); -} - -static inline void tlb_read(void) -{ -#if MIPS34K_MISSED_ITLB_WAR - int res = 0; - - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set mips32r2 \n" - " .word 0x41610001 # dvpe $1 \n" - " move %0, $1 \n" - " ehb \n" - " .set pop \n" - : "=r" (res)); - - instruction_hazard(); -#endif - - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbr\n\t" - ".set reorder"); - -#if MIPS34K_MISSED_ITLB_WAR - if ((res & _ULCAST_(1))) - __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set mips32r2 \n" - " .word 0x41600021 # evpe \n" - " ehb \n" - " .set pop \n"); -#endif -} - -static inline void tlb_write_indexed(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwi\n\t" - ".set reorder"); -} - -static inline void tlb_write_random(void) -{ - __asm__ __volatile__( - ".set noreorder\n\t" - "tlbwr\n\t" - ".set reorder"); -} /* - * Manipulate bits in a c0 register. + * Events counted by counter #0 */ -#define __BUILD_SET_C0(name) \ -static inline unsigned int \ -set_c0_##name(unsigned int set) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ - \ - return res; \ -} \ - \ -static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ - \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ - \ - return res; \ -} +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 -__BUILD_SET_C0(status) -__BUILD_SET_C0(cause) -__BUILD_SET_C0(config) -__BUILD_SET_C0(intcontrol) -__BUILD_SET_C0(intctl) -__BUILD_SET_C0(srsmap) +/* + * Events counted by counter #1 + */ +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 -#endif /* !__ASSEMBLY__ */ +/* + * These flags define in which priviledge mode the counters count events + */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ #endif /* _ASM_MIPSREGS_H */ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 24858ddda..6838aee98 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -4,9 +4,9 @@ * for more details. * * Copyright (C) 1994 Waldorf GMBH - * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle + * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001 Ralf Baechle * Copyright (C) 1996 Paul M. Antoine - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 1999 Silicon Graphics, Inc. */ #ifndef _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H @@ -15,26 +15,92 @@ #include +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#if !defined (_LANGUAGE_ASSEMBLY) +#if 0 +#include +#endif #include #include #include #include -/* - * Return current * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) +struct mips_cpuinfo { + unsigned long udelay_val; + unsigned long *pgd_quick; + unsigned long *pte_quick; + unsigned long pgtable_cache_sz; +}; /* * System setup and hardware flags.. + * XXX: Should go into mips_cpuinfo. */ -extern void (*cpu_wait)(void); +extern void (*cpu_wait)(void); /* only available on R4[26]00 and R3081 */ +extern void r3081_wait(void); +extern void r4k_wait(void); +extern char cyclecounter_available; /* only available from R4000 upwards. */ +extern struct mips_cpuinfo boot_cpu_data; extern unsigned int vced_count, vcei_count; +#ifdef CONFIG_SMP +extern struct mips_cpuinfo cpu_data[]; +#define current_cpu_data cpu_data[smp_processor_id()] +#else +#define cpu_data &boot_cpu_data +#define current_cpu_data boot_cpu_data +#endif + +/* + * Bus types (default is ISA, but people can check others with these..) + * MCA_bus hardcoded to 0 for now. + * + * This needs to be extended since MIPS systems are being delivered with + * numerous different types of bus systems. + */ +extern int EISA_bus; +#define MCA_bus 0 +#define MCA_bus__is_a_macro /* for versions in ksyms.c */ + +/* + * MIPS has no problems with write protection + */ +#define wp_works_ok 1 +#define wp_works_ok__is_a_macro /* for versions in ksyms.c */ + +/* Lazy FPU handling on uni-processor */ +extern struct task_struct *last_task_used_math; + +/* + * User space process size: 2GB. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. TASK_SIZE + * for a 64 bit kernel expandable to 8192EB, of which the current MIPS + * implementations will "only" be able to use 1TB ... + */ +#define TASK_SIZE (0x7fff8000UL) + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Size of io_bitmap in longwords: 32 is ports 0-0x3ff. + */ +#define IO_BITMAP_SIZE 32 + #define NUM_FPU_REGS 32 -typedef __u64 fpureg_t; +struct mips_fpu_hard_struct { + double fp_regs[NUM_FPU_REGS]; + unsigned int control; +}; /* * It would be nice to add some more fields for emulator statistics, but there @@ -42,29 +108,25 @@ typedef __u64 fpureg_t; * be recalculated by hand. So the additional information will be private to * the FPU emulator for now. See asm-mips/fpu_emulator.h. */ - -struct mips_fpu_struct { - fpureg_t fpr[NUM_FPU_REGS]; - unsigned int fcr31; +typedef u64 fpureg_t; +struct mips_fpu_soft_struct { + fpureg_t regs[NUM_FPU_REGS]; + unsigned int sr; }; -#define NUM_DSP_REGS 6 - -typedef __u32 dspreg_t; - -struct mips_dsp_state { - dspreg_t dspr[NUM_DSP_REGS]; - unsigned int dspcontrol; +union mips_fpu_union { + struct mips_fpu_hard_struct hard; + struct mips_fpu_soft_struct soft; }; +#define INIT_FPU { \ + {{0,},} \ +} + typedef struct { unsigned long seg; } mm_segment_t; -#define ARCH_MIN_TASKALIGN 8 - -struct mips_abi; - /* * If you change thread_struct remember to change the #defines below too! */ @@ -78,36 +140,131 @@ struct thread_struct { unsigned long cp0_status; /* Saved fpu/fpu emulator stuff. */ - struct mips_fpu_struct fpu; -#ifdef CONFIG_MIPS_MT_FPAFF - /* Emulated instruction count */ - unsigned long emulated_fp; - /* Saved per-thread scheduler affinity mask */ - cpumask_t user_cpus_allowed; -#endif /* CONFIG_MIPS_MT_FPAFF */ - - /* Saved state of the DSP ASE, if available. */ - struct mips_dsp_state dsp; + union mips_fpu_union fpu; /* Other stuff associated with the thread. */ unsigned long cp0_badvaddr; /* Last user fault */ unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ unsigned long error_code; unsigned long trap_no; +#define MF_FIXADE 1 /* Fix address errors in software */ +#define MF_LOGADE 2 /* Log address errors to syslog */ + unsigned long mflags; + mm_segment_t current_ds; unsigned long irix_trampoline; /* Wheee... */ unsigned long irix_oldctx; - struct mips_abi *abi; + + /* + * These are really only needed if the full FPU emulator is configured. + * Would be made conditional on MIPS_FPU_EMULATOR if it weren't for the + * fact that having offset.h rebuilt differently for different config + * options would be asking for trouble. + * + * Saved EPC during delay-slot emulation (see math-emu/cp1emu.c) + */ + unsigned long dsemul_epc; + + /* + * Pointer to instruction used to induce address error + */ + unsigned long dsemul_aerpc; }; -struct task_struct; +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + +#define INIT_THREAD { \ + /* \ + * saved main processor registers \ + */ \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, \ + /* \ + * saved cp0 stuff \ + */ \ + 0, \ + /* \ + * saved fpu/fpu emulator stuff \ + */ \ + INIT_FPU, \ + /* \ + * Other stuff associated with the process \ + */ \ + 0, 0, 0, 0, \ + /* \ + * For now the default is to fix address errors \ + */ \ + MF_FIXADE, { 0 }, 0, 0, \ + /* \ + * dsemul_epc and dsemul_aerpc should never be used uninitialized, \ + * but... \ + */ \ + 0 ,0 \ +} + +#ifdef __KERNEL__ + +#define KERNEL_STACK_SIZE 8192 + +#if !defined (_LANGUAGE_ASSEMBLY) /* Free all resources held by a thread. */ #define release_thread(thread) do { } while(0) -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while (0) +extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); -#define cpu_relax() barrier() +/* Copy and release all segment info associated with a VM */ +#define copy_segments(p, mm) do { } while(0) +#define release_segments(mm) do { } while(0) + +/* + * Return saved PC of a blocked thread. + */ +extern inline unsigned long thread_saved_pc(struct thread_struct *t) +{ + extern void ret_from_fork(void); + + /* New born processes are a special case */ + if (t->reg31 == (unsigned long) ret_from_fork) + return t->reg31; + + return ((unsigned long *)t->reg29)[10]; +} + +/* + * Do necessary setup to start up a newly executed thread. + */ +#define start_thread(regs, new_pc, new_sp) do { \ + /* New thread looses kernel privileges. */ \ + regs->cp0_status = (regs->cp0_status & ~(ST0_CU0|ST0_KSU)) | KU_USER;\ + regs->cp0_epc = new_pc; \ + regs->regs[29] = new_sp; \ + current->thread.current_ds = USER_DS; \ +} while (0) + +unsigned long get_wchan(struct task_struct *p); + +#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs)) +#define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32) +#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc))) +#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29]))) + +/* Allocation and freeing of basic task resources. */ +/* + * NOTE! The task struct and the stack go together + */ +#define THREAD_SIZE (2*PAGE_SIZE) +#define alloc_task_struct() \ + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count) + +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) + +#define cpu_relax() do { } while (0) + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ +#endif /* __KERNEL__ */ /* * Return_address is a replacement for __builtin_return_address(count) @@ -123,20 +280,4 @@ struct task_struct; */ #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) -#ifdef CONFIG_CPU_HAS_PREFETCH - -#define ARCH_HAS_PREFETCH - -static inline void prefetch(const void *addr) -{ - __asm__ __volatile__( - " .set mips4 \n" - " pref %0, (%1) \n" - " .set mips0 \n" - : - : "i" (Pref_Load), "r" (addr)); -} - -#endif - #endif /* _ASM_PROCESSOR_H */ diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 5659c0c87..2517adb2a 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h @@ -3,12 +3,17 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000 by Ralf Baechle + * + * Machine dependent structs and defines to help the user use + * the ptrace system call. */ #ifndef _ASM_PTRACE_H #define _ASM_PTRACE_H +#include +#include + /* 0 - 31 are integer registers, 32 - 63 are fp registers. */ #define FPR_BASE 32 #define PC 64 @@ -18,69 +23,63 @@ #define MMLO 68 #define FPC_CSR 69 #define FPC_EIR 70 -#define DSP_BASE 71 /* 3 more hi / lo register pairs */ -#define DSP_CONTROL 77 -#define ACX 78 +#ifndef _LANGUAGE_ASSEMBLY /* * This struct defines the way the registers are stored on the stack during a * system call/exception. As usual the registers k0/k1 aren't being saved. */ struct pt_regs { -#ifdef CONFIG_32BIT /* Pad bytes for argument save space on the stack. */ unsigned long pad0[6]; -#endif /* Saved main processor registers. */ unsigned long regs[32]; - /* Saved special registers. */ - unsigned long cp0_status; - unsigned long hi; + /* Other saved registers. */ unsigned long lo; -#ifdef CONFIG_CPU_HAS_SMARTMIPS - unsigned long acx; -#endif - unsigned long cp0_badvaddr; - unsigned long cp0_cause; + unsigned long hi; + + /* + * saved cp0 registers + */ unsigned long cp0_epc; -#ifdef CONFIG_MIPS_MT_SMTC - unsigned long cp0_tcstatus; -#endif /* CONFIG_MIPS_MT_SMTC */ -} __attribute__ ((aligned (8))); + unsigned long cp0_badvaddr; + unsigned long cp0_status; + unsigned long cp0_cause; +}; + +#endif /* !(_LANGUAGE_ASSEMBLY) */ /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 +/* #define PTRACE_GETREGS 12 */ +/* #define PTRACE_SETREGS 13 */ +/* #define PTRACE_GETFPREGS 14 */ +/* #define PTRACE_SETFPREGS 15 */ /* #define PTRACE_GETFPXREGS 18 */ /* #define PTRACE_SETFPXREGS 19 */ -#define PTRACE_OLDSETOPTIONS 21 +#define PTRACE_SETOPTIONS 21 -#define PTRACE_GET_THREAD_AREA 25 -#define PTRACE_SET_THREAD_AREA 26 +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 -/* Calls to trace a 64bit program from a 32bit program. */ -#define PTRACE_PEEKTEXT_3264 0xc0 -#define PTRACE_PEEKDATA_3264 0xc1 -#define PTRACE_POKETEXT_3264 0xc2 -#define PTRACE_POKEDATA_3264 0xc3 -#define PTRACE_GET_THREAD_AREA_3264 0xc4 +#if 0 /* def _LANGUAGE_ASSEMBLY */ +#include +#endif #ifdef __KERNEL__ -#include - +#ifndef _LANGUAGE_ASSEMBLY /* * Does the process account for user or for system time? */ #define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) #define instruction_pointer(regs) ((regs)->cp0_epc) -#define profile_pc(regs) instruction_pointer(regs) + +extern void show_regs(struct pt_regs *); +#endif /* !(_LANGUAGE_ASSEMBLY) */ #endif diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h index fc6bc0c16..35505b70f 100644 --- a/include/asm-mips/reg.h +++ b/include/asm-mips/reg.h @@ -7,50 +7,48 @@ * for more details. * * Copyright (C) 1995, 1999 by Ralf Baechle - * Copyright (C) 1995, 1999 Silicon Graphics */ #ifndef __ASM_MIPS_REG_H #define __ASM_MIPS_REG_H -#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H) - -#define EF_R0 6 -#define EF_R1 7 -#define EF_R2 8 -#define EF_R3 9 -#define EF_R4 10 -#define EF_R5 11 -#define EF_R6 12 -#define EF_R7 13 -#define EF_R8 14 -#define EF_R9 15 -#define EF_R10 16 -#define EF_R11 17 -#define EF_R12 18 -#define EF_R13 19 -#define EF_R14 20 -#define EF_R15 21 -#define EF_R16 22 -#define EF_R17 23 -#define EF_R18 24 -#define EF_R19 25 -#define EF_R20 26 -#define EF_R21 27 -#define EF_R22 28 -#define EF_R23 29 -#define EF_R24 30 -#define EF_R25 31 - +/* + * This defines/structures correspond to the register layout on stack - + * if the order here is changed, it needs to be updated in + * include/asm-mips/stackframe.h + */ +#define EF_REG0 6 +#define EF_REG1 7 +#define EF_REG2 8 +#define EF_REG3 9 +#define EF_REG4 10 +#define EF_REG5 11 +#define EF_REG6 12 +#define EF_REG7 13 +#define EF_REG8 14 +#define EF_REG9 15 +#define EF_REG10 16 +#define EF_REG11 17 +#define EF_REG12 18 +#define EF_REG13 19 +#define EF_REG14 20 +#define EF_REG15 21 +#define EF_REG16 22 +#define EF_REG17 23 +#define EF_REG18 24 +#define EF_REG19 25 +#define EF_REG20 26 +#define EF_REG21 27 +#define EF_REG22 28 +#define EF_REG23 29 +#define EF_REG24 30 +#define EF_REG25 31 /* * k0/k1 unsaved */ -#define EF_R26 32 -#define EF_R27 33 - -#define EF_R28 34 -#define EF_R29 35 -#define EF_R30 36 -#define EF_R31 37 +#define EF_REG28 34 +#define EF_REG29 35 +#define EF_REG30 36 +#define EF_REG31 37 /* * Saved special registers @@ -61,66 +59,8 @@ #define EF_CP0_EPC 40 #define EF_CP0_BADVADDR 41 #define EF_CP0_STATUS 42 -#define EF_CP0_CAUSE 43 -#define EF_UNUSED0 44 +#define EF_CP0_CAUSE 44 -#define EF_SIZE 180 - -#endif - -#ifdef CONFIG_64BIT - -#define EF_R0 0 -#define EF_R1 1 -#define EF_R2 2 -#define EF_R3 3 -#define EF_R4 4 -#define EF_R5 5 -#define EF_R6 6 -#define EF_R7 7 -#define EF_R8 8 -#define EF_R9 9 -#define EF_R10 10 -#define EF_R11 11 -#define EF_R12 12 -#define EF_R13 13 -#define EF_R14 14 -#define EF_R15 15 -#define EF_R16 16 -#define EF_R17 17 -#define EF_R18 18 -#define EF_R19 19 -#define EF_R20 20 -#define EF_R21 21 -#define EF_R22 22 -#define EF_R23 23 -#define EF_R24 24 -#define EF_R25 25 - -/* - * k0/k1 unsaved - */ -#define EF_R26 26 -#define EF_R27 27 - -#define EF_R28 28 -#define EF_R29 29 -#define EF_R30 30 -#define EF_R31 31 - -/* - * Saved special registers - */ -#define EF_LO 32 -#define EF_HI 33 - -#define EF_CP0_EPC 34 -#define EF_CP0_BADVADDR 35 -#define EF_CP0_STATUS 36 -#define EF_CP0_CAUSE 37 - -#define EF_SIZE 304 /* size in bytes */ - -#endif /* CONFIG_64BIT */ +#define EF_SIZE 180 /* size in bytes */ #endif /* __ASM_MIPS_REG_H */ diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h index 2e65cc3c4..691d047b6 100644 --- a/include/asm-mips/regdef.h +++ b/include/asm-mips/regdef.h @@ -1,100 +1,52 @@ /* + * include/asm-mips/regdefs.h + * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1985 MIPS Computer Systems, Inc. - * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle - * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. + * Copyright (C) 1994, 1995 by Ralf Baechle */ -#ifndef _ASM_REGDEF_H -#define _ASM_REGDEF_H -#include - -#if _MIPS_SIM == _MIPS_SIM_ABI32 +#ifndef __ASM_MIPS_REGDEF_H +#define __ASM_MIPS_REGDEF_H /* * Symbolic register names for 32 bit ABI */ -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define t5 $13 -#define t6 $14 -#define t7 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ +#define zero $0 /* wired zero */ +#define AT $1 /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ #define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ +#define ra $31 /* return address */ -#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ - -#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 - -#define zero $0 /* wired zero */ -#define AT $at /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value - caller saved */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ -#define ta0 $8 -#define a5 $9 -#define ta1 $9 -#define a6 $10 -#define ta2 $10 -#define a7 $11 -#define ta3 $11 -#define t0 $12 /* caller saved */ -#define t1 $13 -#define t2 $14 -#define t3 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 /* callee address for PIC/temp */ -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel temporary */ -#define k1 $27 -#define gp $28 /* global pointer - caller saved for PIC */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* callee saved */ -#define ra $31 /* return address */ - -#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ - -#endif /* _ASM_REGDEF_H */ +#endif /* __ASM_MIPS_REGDEF_H */ diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h index 579a591e6..463a111b4 100644 --- a/include/asm-mips/string.h +++ b/include/asm-mips/string.h @@ -1,39 +1,157 @@ -/* +/* $Id: string.h,v 1.13 2000/02/19 14:12:14 harald Exp $ + * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle - * Copyright (c) 2000 by Silicon Graphics, Inc. - * Copyright (c) 2001 MIPS Technologies, Inc. + * Copyright (c) 1994, 1995, 1996, 1997, 1998 by Ralf Baechle */ -#ifndef _ASM_STRING_H -#define _ASM_STRING_H +#ifndef __ASM_MIPS_STRING_H +#define __ASM_MIPS_STRING_H -/* - * We don't do inline string functions, since the - * optimised inline asm versions are not small. - */ +#include -#undef __HAVE_ARCH_STRCPY -extern char *strcpy(char *__dest, __const__ char *__src); +#define __HAVE_ARCH_STRCPY +extern __inline__ char *strcpy(char *__dest, __const__ char *__src) +{ + char *__xdest = __dest; -#undef __HAVE_ARCH_STRNCPY -extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n); + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tlbu\t$1,(%1)\n\t" + "addiu\t%1,1\n\t" + "sb\t$1,(%0)\n\t" + "bnez\t$1,1b\n\t" + "addiu\t%0,1\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (__dest), "=r" (__src) + : "0" (__dest), "1" (__src) + : "$1","memory"); -#undef __HAVE_ARCH_STRCMP -extern int strcmp(__const__ char *__cs, __const__ char *__ct); + return __xdest; +} -#undef __HAVE_ARCH_STRNCMP -extern int strncmp(__const__ char *__cs, __const__ char *__ct, __kernel_size_t __count); +#define __HAVE_ARCH_STRNCPY +extern __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n) +{ + char *__xdest = __dest; + + if (__n == 0) + return __xdest; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tlbu\t$1,(%1)\n\t" + "subu\t%2,1\n\t" + "sb\t$1,(%0)\n\t" + "beqz\t$1,2f\n\t" + "addiu\t%0,1\n\t" + "bnez\t%2,1b\n\t" + "addiu\t%1,1\n" + "2:\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (__dest), "=r" (__src), "=r" (__n) + : "0" (__dest), "1" (__src), "2" (__n) + : "$1","memory"); + + return __dest; +} + +#define __HAVE_ARCH_STRCMP +extern __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct) +{ + int __res; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + "lbu\t%2,(%0)\n" + "1:\tlbu\t$1,(%1)\n\t" + "addiu\t%0,1\n\t" + "bne\t$1,%2,2f\n\t" + "addiu\t%1,1\n\t" + "bnez\t%2,1b\n\t" + "lbu\t%2,(%0)\n\t" +#if defined(CONFIG_CPU_R3000) + "nop\n\t" +#endif + "move\t%2,$1\n" + "2:\tsubu\t%2,$1\n" + "3:\t.set\tat\n\t" + ".set\treorder" + : "=r" (__cs), "=r" (__ct), "=r" (__res) + : "0" (__cs), "1" (__ct) + : "$1"); + + return __res; +} + +#define __HAVE_ARCH_STRNCMP +extern __inline__ int +strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count) +{ + int __res; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n" + "1:\tlbu\t%3,(%0)\n\t" + "beqz\t%2,2f\n\t" + "lbu\t$1,(%1)\n\t" + "subu\t%2,1\n\t" + "bne\t$1,%3,3f\n\t" + "addiu\t%0,1\n\t" + "bnez\t%3,1b\n\t" + "addiu\t%1,1\n" + "2:\n\t" +#if defined(CONFIG_CPU_R3000) + "nop\n\t" +#endif + "move\t%3,$1\n" + "3:\tsubu\t%3,$1\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res) + : "0" (__cs), "1" (__ct), "2" (__count) + : "$1"); + + return __res; +} #undef __HAVE_ARCH_MEMSET -extern void *memset(void *__s, int __c, __kernel_size_t __count); +extern void *memset(void *__s, int __c, size_t __count); #undef __HAVE_ARCH_MEMCPY -extern void *memcpy(void *__to, __const__ void *__from, __kernel_size_t __n); +extern void *memcpy(void *__to, __const__ void *__from, size_t __n); #undef __HAVE_ARCH_MEMMOVE -extern void *memmove(void *__dest, __const__ void *__src, __kernel_size_t __n); +extern void *memmove(void *__dest, __const__ void *__src, size_t __n); -#endif /* _ASM_STRING_H */ +/* Don't build bcopy at all ... */ +#define __HAVE_ARCH_BCOPY + +#define __HAVE_ARCH_MEMSCAN +extern __inline__ void *memscan(void *__addr, int __c, size_t __size) +{ + char *__end = (char *)__addr + __size; + + __asm__(".set\tpush\n\t" + ".set\tnoat\n\t" + ".set\treorder\n\t" + "1:\tbeq\t%0,%1,2f\n\t" + "addiu\t%0,1\n\t" + "lb\t$1,-1(%0)\n\t" + "bne\t$1,%4,1b\n" + "2:\t.set\tpop" + : "=r" (__addr), "=r" (__end) + : "0" (__addr), "1" (__end), "r" (__c) + : "$1"); + + return __addr; +} + +#endif /* __ASM_MIPS_STRING_H */ diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h index d4bb85999..e757e228a 100644 --- a/include/asm-mips/types.h +++ b/include/asm-mips/types.h @@ -1,4 +1,5 @@ -/* +/* $Id: types.h,v 1.3 1999/08/18 23:37:50 ralf Exp $ + * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. @@ -9,8 +10,6 @@ #ifndef _ASM_TYPES_H #define _ASM_TYPES_H -#ifndef __ASSEMBLY__ - typedef unsigned short umode_t; /* @@ -34,24 +33,18 @@ typedef unsigned long __u64; #else -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif #endif -#endif /* __ASSEMBLY__ */ - /* * These aren't exported outside the kernel to avoid name space clashes */ #ifdef __KERNEL__ -#define BITS_PER_LONG _MIPS_SZLONG - -#ifndef __ASSEMBLY__ - typedef __signed char s8; typedef unsigned char u8; @@ -75,32 +68,9 @@ typedef unsigned long long u64; #endif -#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ - || defined(CONFIG_64BIT) -typedef u64 dma_addr_t; +#define BITS_PER_LONG _MIPS_SZLONG -typedef u64 phys_addr_t; -typedef u64 phys_size_t; - -#else -typedef u32 dma_addr_t; - -typedef u32 phys_addr_t; -typedef u32 phys_size_t; - -#endif -typedef u64 dma64_addr_t; - -/* - * Don't use phys_t. You've been warned. - */ -#ifdef CONFIG_64BIT_PHYS_ADDR -typedef unsigned long long phys_t; -#else -typedef unsigned long phys_t; -#endif - -#endif /* __ASSEMBLY__ */ +typedef unsigned long dma_addr_t; #endif /* __KERNEL__ */ diff --git a/include/asm-mips/u-boot.h b/include/asm-mips/u-boot.h index 9ecb9ac32..d1273a453 100644 --- a/include/asm-mips/u-boot.h +++ b/include/asm-mips/u-boot.h @@ -38,7 +38,7 @@ typedef struct bd_info { unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h index a56f939df..fd1138920 100644 --- a/include/asm-nios/global_data.h +++ b/include/asm-nios/global_data.h @@ -30,7 +30,7 @@ typedef struct global_data { unsigned long baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ + unsigned long ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ @@ -45,9 +45,6 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("%g7") diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h index 8b788068b..07499d966 100644 --- a/include/asm-nios/io.h +++ b/include/asm-nios/io.h @@ -23,32 +23,24 @@ #ifndef __ASM_NIOS_IO_H_ #define __ASM_NIOS_IO_H_ -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - #define readb(addr)\ ({unsigned char val;\ asm volatile( " pfxio 0 \n"\ - " ld %0, [%1] \n"\ + " ld %0, [%1] \n"\ " ext8d %0, %1 \n"\ :"=r"(val) : "r" (addr)); val;}) #define readw(addr)\ ({unsigned short val;\ asm volatile( " pfxio 0 \n"\ - " ld %0, [%1] \n"\ + " ld %0, [%1] \n"\ " ext16d %0, %1 \n"\ :"=r"(val) : "r" (addr)); val;}) #define readl(addr)\ ({unsigned long val;\ asm volatile( " pfxio 0 \n"\ - " ld %0, [%1] \n"\ + " ld %0, [%1] \n"\ :"=r"(val) : "r" (addr)); val;}) #define writeb(addr,val)\ @@ -105,32 +97,4 @@ static inline void outsl (unsigned long port, const void *src, unsigned long cou while (count--) outl (*p++, port); } -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - #endif /* __ASM_NIOS_IO_H_ */ diff --git a/include/asm-nios/types.h b/include/asm-nios/types.h index 636e12fd3..43fd8f6d2 100644 --- a/include/asm-nios/types.h +++ b/include/asm-nios/types.h @@ -25,9 +25,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif /* @@ -52,9 +52,6 @@ typedef unsigned long long u64; /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; #endif /* __KERNEL__ */ #endif /* _NIOS_TYPES_H */ diff --git a/include/asm-nios/u-boot.h b/include/asm-nios/u-boot.h index 3436185a8..aae4be13c 100644 --- a/include/asm-nios/u-boot.h +++ b/include/asm-nios/u-boot.h @@ -34,7 +34,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h index cd17e0894..a1ac28856 100644 --- a/include/asm-nios2/global_data.h +++ b/include/asm-nios2/global_data.h @@ -29,7 +29,7 @@ typedef struct global_data { unsigned long baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ + unsigned long ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ @@ -44,9 +44,6 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r15") diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index 2f1ec26bd..0fab53bf0 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -24,47 +24,12 @@ #ifndef __ASM_NIOS2_IO_H_ #define __ASM_NIOS2_IO_H_ -static inline void sync(void) -{ - __asm__ __volatile__ ("sync" : : : "memory"); -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} +#define sync() asm volatile ("sync" : : : "memory"); extern unsigned char inb (unsigned char *port); extern unsigned short inw (unsigned short *port); extern unsigned inl (unsigned port); -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - #define readb(addr)\ ({unsigned char val;\ asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) diff --git a/include/asm-nios2/types.h b/include/asm-nios2/types.h index ea859c077..39e264178 100644 --- a/include/asm-nios2/types.h +++ b/include/asm-nios2/types.h @@ -25,9 +25,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif /* @@ -52,9 +52,6 @@ typedef unsigned long long u64; /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; #endif /* __KERNEL__ */ #endif /* __ASM_NIOS2_TYPES_H */ diff --git a/include/asm-nios2/u-boot.h b/include/asm-nios2/u-boot.h index de8c4052f..3f299624a 100644 --- a/include/asm-nios2/u-boot.h +++ b/include/asm-nios2/u-boot.h @@ -33,7 +33,7 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ diff --git a/include/asm-ppc/5xx_immap.h b/include/asm-ppc/5xx_immap.h index 72cbab43e..8e570573b 100644 --- a/include/asm-ppc/5xx_immap.h +++ b/include/asm-ppc/5xx_immap.h @@ -408,31 +408,31 @@ typedef struct uimb { /* Internal Memory Map MPC555 */ typedef struct immap { - char res1[262144]; /* CMF Flash A 256 Kbytes */ - char res2[196608]; /* CMF Flash B 192 Kbytes */ - char res3[2670592]; /* Reserved for Flash */ - sysconf5xx_t im_siu_conf; /* SIU Configuration */ + char res1[262144]; /* CMF Flash A 256 Kbytes */ + char res2[196608]; /* CMF Flash B 192 Kbytes */ + char res3[2670592]; /* Reserved for Flash */ + sysconf5xx_t im_siu_conf; /* SIU Configuration */ memctl5xx_t im_memctl; /* Memory Controller */ sit5xx_t im_sit; /* System Integration Timers */ car5xx_t im_clkrst; /* Clocks and Reset */ - sitk5xx_t im_sitk; /* System Integration Timer Keys*/ - cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ + sitk5xx_t im_sitk; /* System Integration Timer Keys*/ + cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ fl5xx_t im_fla; /* Flash Module A */ fl5xx_t im_flb; /* Flash Module B */ - char res4[14208]; /* Reserved for SIU */ - dprc5xx_t im_dprc; /* Dpram Control Register */ - char res5[8180]; /* Reserved */ - char dptram[6144]; /* Dptram */ - char res6[2048]; /* Reserved */ + char res4[14208]; /* Reserved for SIU */ + dprc5xx_t im_dprc; /* Dpram Control Register */ + char res5[8180]; /* Reserved */ + char dptram[6144]; /* Dptram */ + char res6[2048]; /* Reserved */ tpu5xx_t im_tpua; /* Time Proessing Unit A */ - tpu5xx_t im_tpub; /* Time Processing Unit B */ - qadc5xx_t im_qadca; /* QADC A */ - qadc5xx_t im_qadcb; /* QADC B */ + tpu5xx_t im_tpub; /* Time Processing Unit B */ + qadc5xx_t im_qadca; /* QADC A */ + qadc5xx_t im_qadcb; /* QADC B */ qsmcm5xx_t im_qsmcm; /* SCI and SPI */ - mios5xx_t im_mios; /* MIOS */ - tcan5xx_t im_tcana; /* Toucan A */ - tcan5xx_t im_tcanb; /* Toucan B */ - char res7[1792]; /* Reserved */ + mios5xx_t im_mios; /* MIOS */ + tcan5xx_t im_tcana; /* Toucan A */ + tcan5xx_t im_tcanb; /* Toucan B */ + char res7[1792]; /* Reserved */ uimb5xx_t im_uimb; /* UIMB */ } immap_t; diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h index daa66cf91..3264915d8 100644 --- a/include/asm-ppc/bitops.h +++ b/include/asm-ppc/bitops.h @@ -152,7 +152,6 @@ extern __inline__ int test_bit(int nr, __const__ volatile void *addr) } /* Return the bit position of the most significant 1 bit in a word */ -/* - the result is undefined when x == 0 */ extern __inline__ int __ilog2(unsigned int x) { int lz; @@ -168,57 +167,6 @@ extern __inline__ int ffz(unsigned int x) return __ilog2(x & -x); } -/* - * fls: find last (most-significant) bit set. - * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. - * - * On powerpc, __ilog2(0) returns -1, but this is not safe in general - */ -static __inline__ int fls(unsigned int x) -{ - return __ilog2(x) + 1; -} - -/** - * fls64 - find last set bit in a 64-bit word - * @x: the word to search - * - * This is defined in a similar way as the libc and compiler builtin - * ffsll, but returns the position of the most significant set bit. - * - * fls64(value) returns 0 if value is 0 or the position of the last - * set bit if value is nonzero. The last (most significant) bit is - * at position 64. - */ -#if BITS_PER_LONG == 32 -static inline int fls64(__u64 x) -{ - __u32 h = x >> 32; - if (h) - return fls(h) + 32; - return fls(x); -} -#elif BITS_PER_LONG == 64 -static inline int fls64(__u64 x) -{ - if (x == 0) - return 0; - return __ilog2(x) + 1; -} -#else -#error BITS_PER_LONG not 32 or 64 -#endif - -static inline int __ilog2_u64(u64 n) -{ - return fls64(n) - 1; -} - -static inline int ffs64(u64 x) -{ - return __ilog2_u64(x & -x) + 1ull; -} - #ifdef __KERNEL__ /* @@ -339,7 +287,7 @@ extern __inline__ int ext2_test_bit(int nr, __const__ void * addr) #define ext2_find_first_zero_bit(addr, size) \ ext2_find_next_zero_bit((addr), (size), 0) -static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, +extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) { unsigned int *p = ((unsigned int *) addr) + (offset >> 5); diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 9d9b9717d..5befab4d5 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -8,22 +8,15 @@ #include /* bytes per L1 cache line */ -#if defined(CONFIG_8xx) || defined(CONFIG_IOP480) -#define L1_CACHE_SHIFT 4 -#elif defined(CONFIG_PPC64BRIDGE) -#define L1_CACHE_SHIFT 7 +#if !defined(CONFIG_8xx) || defined(CONFIG_8260) +#if defined(CONFIG_PPC64BRIDGE) +#define L1_CACHE_BYTES 128 #else -#define L1_CACHE_SHIFT 5 -#endif - -#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -/* - * For compatibility reasons support the CFG_CACHELINE_SIZE too - */ -#ifndef CFG_CACHELINE_SIZE -#define CFG_CACHELINE_SIZE L1_CACHE_BYTES -#endif +#define L1_CACHE_BYTES 32 +#endif /* PPC64 */ +#else +#define L1_CACHE_BYTES 16 +#endif /* !8xx || 8260 */ #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define L1_CACHE_PAGES 8 @@ -42,8 +35,6 @@ extern void flush_dcache_range(unsigned long start, unsigned long stop); extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); -extern void flush_dcache(void); -extern void invalidate_dcache(void); #ifdef CFG_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); #endif /* CFG_INIT_RAM_LOCK */ diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index 05db0de8f..908007cbc 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -6,69 +6,71 @@ #ifndef __E300_H__ #define __E300_H__ -#define PVR_E300C1 0x80830000 -#define PVR_E300C2 0x80840000 -#define PVR_E300C3 0x80850000 -#define PVR_E300C4 0x80860000 +/* + * e300 Processor Version & Revision Numbers + */ +#define PVR_83xx 0x80830000 +#define PVR_8349_REV10 (PVR_83xx | 0x0010) +#define PVR_8349_REV11 (PVR_83xx | 0x0011) /* * Hardware Implementation-Dependent Register 0 (HID0) */ /* #define HID0 1008 already defined in processor.h */ -#define HID0_MASK_MACHINE_CHECK 0x00000000 -#define HID0_ENABLE_MACHINE_CHECK 0x80000000 +#define HID0_MASK_MACHINE_CHECK 0x00000000 +#define HID0_ENABLE_MACHINE_CHECK 0x80000000 -#define HID0_DISABLE_CACHE_PARITY 0x00000000 -#define HID0_ENABLE_CACHE_PARITY 0x40000000 +#define HID0_DISABLE_CACHE_PARITY 0x00000000 +#define HID0_ENABLE_CACHE_PARITY 0x40000000 -#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ -#define HID0_ENABLE_ADDRESS_PARITY 0x20000000 +#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ +#define HID0_ENABLE_ADDRESS_PARITY 0x20000000 -#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ -#define HID0_ENABLE_DATE_PARITY 0x10000000 +#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ +#define HID0_ENABLE_DATE_PARITY 0x10000000 -#define HID0_CORE_CLK_OUT 0x00000000 -#define HID0_CORE_CLK_OUT_DIV_2 0x08000000 +#define HID0_CORE_CLK_OUT 0x00000000 +#define HID0_CORE_CLK_OUT_DIV_2 0x08000000 #define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */ #define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000 -#define HID0_DISABLE_DOSE_MODE 0x00000000 -#define HID0_ENABLE_DOSE_MODE 0x00800000 +#define HID0_DISABLE_DOSE_MODE 0x00000000 +#define HID0_ENABLE_DOSE_MODE 0x00800000 -#define HID0_DISABLE_NAP_MODE 0x00000000 -#define HID0_ENABLE_NAP_MODE 0x00400000 +#define HID0_DISABLE_NAP_MODE 0x00000000 +#define HID0_ENABLE_NAP_MODE 0x00400000 -#define HID0_DISABLE_SLEEP_MODE 0x00000000 -#define HID0_ENABLE_SLEEP_MODE 0x00200000 +#define HID0_DISABLE_SLEEP_MODE 0x00000000 +#define HID0_ENABLE_SLEEP_MODE 0x00200000 #define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000 #define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000 -#define HID0_SOFT_RESET 0x00010000 +#define HID0_SOFT_RESET 0x00010000 -#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 -#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 +#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 +#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 -#define HID0_DISABLE_DATA_CACHE 0x00000000 -#define HID0_ENABLE_DATA_CACHE 0x00004000 +#define HID0_DISABLE_DATA_CACHE 0x00000000 +#define HID0_ENABLE_DATA_CACHE 0x00004000 -#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 +#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 -#define HID0_LOCK_DATA_CACHE 0x00001000 +#define HID0_LOCK_DATA_CACHE 0x00001000 #define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800 -#define HID0_INVALIDATE_DATA_CACHE 0x00000400 +#define HID0_INVALIDATE_DATA_CACHE 0x00000400 -#define HID0_DISABLE_M_BIT 0x00000000 -#define HID0_ENABLE_M_BIT 0x00000080 +#define HID0_DISABLE_M_BIT 0x00000000 +#define HID0_ENABLE_M_BIT 0x00000080 -#define HID0_FBIOB 0x00000010 +#define HID0_FBIOB 0x00000010 -#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 -#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 +#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 +#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 #define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000 #define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001 @@ -90,37 +92,37 @@ /* BAT (block address translation */ -#define BATU_BEPI_MSK 0xfffe0000 -#define BATU_BL_MSK 0x00001ffc +#define BATU_BEPI_MSK 0xfffe0000 +#define BATU_BL_MSK 0x00001ffc -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 -#define BATL_BRPN_MSK 0xfffe0000 -#define BATL_WIMG_MSK 0x00000078 +#define BATL_BRPN_MSK 0xfffe0000 +#define BATL_WIMG_MSK 0x00000078 -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 #endif /* __E300_H__ */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index be2ce2477..b73af9646 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -40,77 +40,34 @@ typedef struct global_data { bd_t *bd; unsigned long flags; unsigned long baudrate; - unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; -#if defined(CONFIG_8xx) - unsigned long brg_clk; -#endif #if defined(CONFIG_CPM2) /* There are many clocks on the MPC8260 - see page 9-5 */ unsigned long vco_out; unsigned long cpm_clk; unsigned long scc_clk; unsigned long brg_clk; -#ifdef CONFIG_PCI - unsigned long pci_clk; #endif -#endif - unsigned long mem_clk; #if defined(CONFIG_MPC83XX) /* There are other clocks in the MPC83XX */ u32 csb_clk; -#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) u32 tsec1_clk; u32 tsec2_clk; - u32 usbdr_clk; -#endif -#if defined (CONFIG_MPC834X) - u32 usbmph_clk; -#endif /* CONFIG_MPC834X */ -#if defined(CONFIG_MPC8315) - u32 tdm_clk; -#endif -#if defined(CONFIG_MPC837X) - u32 sdhc_clk; -#endif u32 core_clk; + u32 usbmph_clk; + u32 usbdr_clk; + u32 i2c_clk; u32 enc_clk; u32 lbiu_clk; u32 lclk_clk; + u32 ddr_clk; u32 pci_clk; -#if defined(CONFIG_MPC837X) - u32 pciexp1_clk; - u32 pciexp2_clk; -#endif -#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) - u32 sata_clk; -#endif -#if defined(CONFIG_MPC8360) - u32 mem_sec_clk; -#endif /* CONFIG_MPC8360 */ -#endif -#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) - u32 i2c1_clk; - u32 i2c2_clk; -#endif -#if defined(CONFIG_QE) - u32 qe_clk; - u32 brg_clk; - uint mp_alloc_base; - uint mp_alloc_top; -#endif /* CONFIG_QE */ -#if defined(CONFIG_FSL_LAW) - u32 used_laws; #endif #if defined(CONFIG_MPC5xxx) unsigned long ipb_clk; unsigned long pci_clk; #endif -#if defined(CONFIG_MPC512X) - u32 ips_clk; - u32 csb_clk; - u32 pci_clk; -#endif /* CONFIG_MPC512X */ #if defined(CONFIG_MPC8220) unsigned long bExtUart; unsigned long inp_clk; @@ -119,7 +76,7 @@ typedef struct global_data { unsigned long pev_clk; unsigned long flb_clk; #endif - phys_size_t ram_size; /* RAM size */ + unsigned long ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long reset_status; /* reset status register at boot */ unsigned long env_addr; /* Address of Environment struct */ @@ -129,9 +86,6 @@ typedef struct global_data { unsigned int dp_alloc_base; unsigned int dp_alloc_top; #endif -#if defined(CONFIG_4xx) - u32 uart_clk; -#endif /* CONFIG_4xx */ #if defined(CFG_GT_6426x) unsigned int mirror_hack[16]; #endif @@ -158,11 +112,8 @@ typedef struct global_data { unsigned long do_mdm_init; unsigned long be_quiet; #endif -#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5) +#ifdef CONFIG_LWMON unsigned long kbd_status; -#endif -#if defined(CONFIG_WD_MAX_RATE) - unsigned long long wdt_last; /* trace watch-dog triggering rate */ #endif void **jt; /* jump table */ } gd_t; @@ -173,12 +124,9 @@ typedef struct global_data { #define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #if 1 -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r29") #else /* We could use plain global data, but the resulting code is bigger */ #define XTRN_DECLARE_GLOBAL_DATA_PTR extern #define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \ diff --git a/include/asm-ppc/i2c.h b/include/asm-ppc/i2c.h new file mode 100644 index 000000000..1680d3a7c --- /dev/null +++ b/include/asm-ppc/i2c.h @@ -0,0 +1,103 @@ +/* + * Freescale I2C Controller + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003, Motorola, Inc. + * author: Eran Liberty (liberty@freescale.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_I2C_H_ +#define _ASM_I2C_H_ + +#include + +typedef struct i2c +{ + u8 adr; /**< I2C slave address */ +#define I2C_ADR 0xFE +#define I2C_ADR_SHIFT 1 +#define I2C_ADR_RES ~(I2C_ADR) + u8 res0[3]; + u8 fdr; /**< I2C frequency divider register */ +#define IC2_FDR 0x3F +#define IC2_FDR_SHIFT 0 +#define IC2_FDR_RES ~(IC2_FDR) + u8 res1[3]; + u8 cr; /**< I2C control redister */ +#define I2C_CR_MEN 0x80 +#define I2C_CR_MIEN 0x40 +#define I2C_CR_MSTA 0x20 +#define I2C_CR_MTX 0x10 +#define I2C_CR_TXAK 0x08 +#define I2C_CR_RSTA 0x04 +#define I2C_CR_BCST 0x01 + u8 res2[3]; + u8 sr; /**< I2C status register */ +#define I2C_SR_MCF 0x80 +#define I2C_SR_MAAS 0x40 +#define I2C_SR_MBB 0x20 +#define I2C_SR_MAL 0x10 +#define I2C_SR_BCSTM 0x08 +#define I2C_SR_SRW 0x04 +#define I2C_SR_MIF 0x02 +#define I2C_SR_RXAK 0x01 + u8 res3[3]; + u8 dr; /**< I2C data register */ +#define I2C_DR 0xFF +#define I2C_DR_SHIFT 0 +#define I2C_DR_RES ~(I2C_DR) + u8 res4[3]; + u8 dfsrr; /**< I2C digital filter sampling rate register */ +#define I2C_DFSRR 0x3F +#define I2C_DFSRR_SHIFT 0 +#define I2C_DFSRR_RES ~(I2C_DR) + u8 res5[3]; + u8 res6[0xE8]; +} i2c_t; + +#ifndef CFG_HZ +#error CFG_HZ is not defined in /include/configs/${BOARD}.h +#endif +#define I2C_TIMEOUT (CFG_HZ/4) + +#ifndef CFG_IMMRBAR +#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h +#endif + +#ifndef CFG_I2C_OFFSET +#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h +#endif + +#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X) +/* + * MPC8349 have two i2c bus + */ +extern i2c_t * mpc8349_i2c; +#define I2C mpc8349_i2c +#else +#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET)) +#endif + +#define I2C_READ 1 +#define I2C_WRITE 0 + +#endif /* _ASM_I2C_H_ */ diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 5b215393e..c2b4c5c6a 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -1,832 +1,1186 @@ /* - * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. - * - * MPC83xx Internal Memory Map - * - * Contributors: - * Dave Liu - * Tanya Jiang - * Mandy Lavi - * Eran Liberty - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * MPC8349 Internal Memory Map + * Copyright (c) 2004 Freescale Semiconductor. + * Eran Liberty (liberty@freescale.com) * + * based on: + * - MPC8260 Internal Memory Map + * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) + * - MPC85xx Internal Memory Map + * Copyright(c) 2002,2003 Motorola Inc. + * Xianghua Xiao (x.xiao@motorola.com) */ -#ifndef __IMMAP_83xx__ -#define __IMMAP_83xx__ +#ifndef __IMMAP_8349__ +#define __IMMAP_8349__ #include -#include -#include +#include /* - * Local Access Window + * Local Access Window. */ -typedef struct law83xx { - u32 bar; /* LBIU local access window base address register */ - u32 ar; /* LBIU local access window attribute register */ -} law83xx_t; +typedef struct law8349 { + u32 bar; /* LBIU local access window base address register */ +/* Identifies the 20 most-significant address bits of the base of local + * access window n. The specified base address should be aligned to the + * window size, as defined by LBLAWARn[SIZE]. + */ +#define LAWBAR_BAR 0xFFFFF000 +#define LAWBAR_RES ~(LAWBAR_BAR) + u32 ar; /* LBIU local access window attribute register */ +} law8349_t; /* - * System configuration registers + * System configuration registers. */ -typedef struct sysconf83xx { - u32 immrbar; /* Internal memory map base address register */ +typedef struct sysconf8349 { + u32 immrbar; /* Internal memory map base address register */ u8 res0[0x04]; - u32 altcbar; /* Alternate configuration base address register */ + u32 altcbar; /* Alternate configuration base address register */ +/* Identifies the12 most significant address bits of an alternate base + * address used for boot sequencer configuration accesses. + */ +#define ALTCBAR_BASE_ADDR 0xFFF00000 +#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ u8 res1[0x14]; - law83xx_t lblaw[4]; /* LBIU local access window */ + law8349_t lblaw[4]; /* LBIU local access window */ u8 res2[0x20]; - law83xx_t pcilaw[2]; /* PCI local access window */ + law8349_t pcilaw[2]; /* PCI local access window */ u8 res3[0x30]; - law83xx_t ddrlaw[2]; /* DDR local access window */ + law8349_t ddrlaw[2]; /* DDR local access window */ u8 res4[0x50]; - u32 sgprl; /* System General Purpose Register Low */ - u32 sgprh; /* System General Purpose Register High */ - u32 spridr; /* System Part and Revision ID Register */ + u32 sgprl; /* System General Purpose Register Low */ + u32 sgprh; /* System General Purpose Register High */ + u32 spridr; /* System Part and Revision ID Register */ +#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ u8 res5[0x04]; - u32 spcr; /* System Priority Configuration Register */ - u32 sicrl; /* System I/O Configuration Register Low */ - u32 sicrh; /* System I/O Configuration Register High */ - u8 res6[0x0C]; - u32 ddrcdr; /* DDR Control Driver Register */ - u32 ddrdsr; /* DDR Debug Status Register */ - u32 obir; /* Output Buffer Impedance Register */ - u8 res7[0xCC]; -} sysconf83xx_t; + u32 spcr; /* System Priority Configuration Register */ +#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ +#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */ +#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */ +#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */ +#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */ +#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */ +#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */ +#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ +#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ +#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ +#define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \ + | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \ + | SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP) + u32 sicrl; /* System General Purpose Register Low */ +#define SICRL_LDP_A 0x80000000 +#define SICRL_USB1 0x40000000 +#define SICRL_USB0 0x20000000 +#define SICRL_UART 0x0C000000 +#define SICRL_GPIO1_A 0x02000000 +#define SICRL_GPIO1_B 0x01000000 +#define SICRL_GPIO1_C 0x00800000 +#define SICRL_GPIO1_D 0x00400000 +#define SICRL_GPIO1_E 0x00200000 +#define SICRL_GPIO1_F 0x00180000 +#define SICRL_GPIO1_G 0x00040000 +#define SICRL_GPIO1_H 0x00020000 +#define SICRL_GPIO1_I 0x00010000 +#define SICRL_GPIO1_J 0x00008000 +#define SICRL_GPIO1_K 0x00004000 +#define SICRL_GPIO1_L 0x00003000 +#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \ + | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \ + | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \ + | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \ + | SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L ) + u32 sicrh; /* System General Purpose Register High */ +#define SICRH_DDR 0x80000000 +#define SICRH_TSEC1_A 0x10000000 +#define SICRH_TSEC1_B 0x08000000 +#define SICRH_TSEC1_C 0x04000000 +#define SICRH_TSEC1_D 0x02000000 +#define SICRH_TSEC1_E 0x01000000 +#define SICRH_TSEC1_F 0x00800000 +#define SICRH_TSEC2_A 0x00400000 +#define SICRH_TSEC2_B 0x00200000 +#define SICRH_TSEC2_C 0x00100000 +#define SICRH_TSEC2_D 0x00080000 +#define SICRH_TSEC2_E 0x00040000 +#define SICRH_TSEC2_F 0x00020000 +#define SICRH_TSEC2_G 0x00010000 +#define SICRH_TSEC2_H 0x00008000 +#define SICRH_GPIO2_A 0x00004000 +#define SICRH_GPIO2_B 0x00002000 +#define SICRH_GPIO2_C 0x00001000 +#define SICRH_GPIO2_D 0x00000800 +#define SICRH_GPIO2_E 0x00000400 +#define SICRH_GPIO2_F 0x00000200 +#define SICRH_GPIO2_G 0x00000180 +#define SICRH_GPIO2_H 0x00000060 +#define SICRH_TSOBI1 0x00000002 +#define SICRH_TSOBI2 0x00000001 +#define SICRh_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \ + | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \ + | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \ + | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \ + | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \ + | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \ + | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \ + | SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \ + | SICRH_TSOBI2) + u8 res6[0xE4]; +} sysconf8349_t; /* * Watch Dog Timer (WDT) Registers */ -typedef struct wdt83xx { +typedef struct wdt8349 { u8 res0[4]; - u32 swcrr; /* System watchdog control register */ - u32 swcnr; /* System watchdog count register */ + u32 swcrr; /* System watchdog control register */ + u32 swcnr; /* System watchdog count register */ +#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. +#define SWCNR_RES ~(SWCNR_SWCN) u8 res1[2]; - u16 swsrr; /* System watchdog service register */ + u16 swsrr; /* System watchdog service register */ u8 res2[0xF0]; -} wdt83xx_t; +} wdt8349_t; /* * RTC/PIT Module Registers */ -typedef struct rtclk83xx { - u32 cnr; /* control register */ - u32 ldr; /* load register */ - u32 psr; /* prescale register */ - u32 ctr; /* counter value field register */ - u32 evr; /* event register */ - u32 alr; /* alarm register */ +typedef struct rtclk8349 { + u32 cnr; /* control register */ +#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */ +#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */ +#define CNR_AIM 0x00000002 /* Alarm Interrupt Mask Bit */ +#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */ +#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) + u32 ldr; /* load register */ + u32 psr; /* prescale register */ + u32 ctr; /* register */ + u32 evr; /* event register */ +#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */ +#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */ +#define RTEVR_RES ~(EVR_SIF | EVR_AIF) + u32 alr; /* alarm register */ u8 res0[0xE8]; -} rtclk83xx_t; +} rtclk8349_t; /* - * Global timer module + * Global timper module */ -typedef struct gtm83xx { - u8 cfr1; /* Timer1/2 Configuration */ - u8 res0[3]; - u8 cfr2; /* Timer3/4 Configuration */ - u8 res1[10]; - u16 mdr1; /* Timer1 Mode Register */ - u16 mdr2; /* Timer2 Mode Register */ - u16 rfr1; /* Timer1 Reference Register */ - u16 rfr2; /* Timer2 Reference Register */ - u16 cpr1; /* Timer1 Capture Register */ - u16 cpr2; /* Timer2 Capture Register */ - u16 cnr1; /* Timer1 Counter Register */ - u16 cnr2; /* Timer2 Counter Register */ - u16 mdr3; /* Timer3 Mode Register */ - u16 mdr4; /* Timer4 Mode Register */ - u16 rfr3; /* Timer3 Reference Register */ - u16 rfr4; /* Timer4 Reference Register */ - u16 cpr3; /* Timer3 Capture Register */ - u16 cpr4; /* Timer4 Capture Register */ - u16 cnr3; /* Timer3 Counter Register */ - u16 cnr4; /* Timer4 Counter Register */ - u16 evr1; /* Timer1 Event Register */ - u16 evr2; /* Timer2 Event Register */ - u16 evr3; /* Timer3 Event Register */ - u16 evr4; /* Timer4 Event Register */ - u16 psr1; /* Timer1 Prescaler Register */ - u16 psr2; /* Timer2 Prescaler Register */ - u16 psr3; /* Timer3 Prescaler Register */ - u16 psr4; /* Timer4 Prescaler Register */ - u8 res[0xC0]; -} gtm83xx_t; + +typedef struct gtm8349 { + u8 cfr1; /* Timer1/2 Configuration */ +#define CFR1_PCAS 0x80 /* Pair Cascade mode */ +#define CFR1_BCM 0x40 /* Backward compatible mode */ +#define CFR1_STP2 0x20 /* Stop timer */ +#define CFR1_RST2 0x10 /* Reset timer */ +#define CFR1_GM2 0x08 /* Gate mode for pin 2 */ +#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ +#define CFR1_STP1 0x02 /* Stop timer */ +#define CFR1_RST1 0x01 /* Reset timer */ + u8 res0[3]; + u8 cfr2; /* Timer3/4 Configuration */ +#define CFR2_PCAS 0x80 /* Pair Cascade mode */ +#define CFR2_SCAS 0x40 /* Super Cascade mode */ +#define CFR2_STP4 0x20 /* Stop timer */ +#define CFR2_RST4 0x10 /* Reset timer */ +#define CFR2_GM4 0x08 /* Gate mode for pin 4 */ +#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ +#define CFR2_STP3 0x02 /* Stop timer */ +#define CFR2_RST3 0x01 /* Reset timer */ + u8 res1[10]; + u16 mdr1; /* Timer1 Mode Register */ +#define MDR_SPS 0xff00 /* Secondary Prescaler value */ +#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ +#define MDR_OM 0x0020 /* Output mode */ +#define MDR_ORI 0x0010 /* Output reference interrupt enable */ +#define MDR_FRR 0x0008 /* Free run/restart */ +#define MDR_ICLK 0x0006 /* Input clock source for the timer */ +#define MDR_GE 0x0001 /* Gate enable */ + u16 mdr2; /* Timer2 Mode Register */ + u16 rfr1; /* Timer1 Reference Register */ + u16 rfr2; /* Timer2 Reference Register */ + u16 cpr1; /* Timer1 Capture Register */ + u16 cpr2; /* Timer2 Capture Register */ + u16 cnr1; /* Timer1 Counter Register */ + u16 cnr2; /* Timer2 Counter Register */ + u16 mdr3; /* Timer3 Mode Register */ + u16 mdr4; /* Timer4 Mode Register */ + u16 rfr3; /* Timer3 Reference Register */ + u16 rfr4; /* Timer4 Reference Register */ + u16 cpr3; /* Timer3 Capture Register */ + u16 cpr4; /* Timer4 Capture Register */ + u16 cnr3; /* Timer3 Counter Register */ + u16 cnr4; /* Timer4 Counter Register */ + u16 evr1; /* Timer1 Event Register */ + u16 evr2; /* Timer2 Event Register */ + u16 evr3; /* Timer3 Event Register */ + u16 evr4; /* Timer4 Event Register */ +#define GTEVR_REF 0x0002 /* Output reference event */ +#define GTEVR_CAP 0x0001 /* Counter Capture event */ +#define GTEVR_RES ~(EVR_CAP|EVR_REF) + u16 psr1; /* Timer1 Prescaler Register */ + u16 psr2; /* Timer2 Prescaler Register */ + u16 psr3; /* Timer3 Prescaler Register */ + u16 psr4; /* Timer4 Prescaler Register */ + u8 res[0xC0]; +} gtm8349_t; /* * Integrated Programmable Interrupt Controller */ -typedef struct ipic83xx { - u32 sicfr; /* System Global Interrupt Configuration Register */ - u32 sivcr; /* System Global Interrupt Vector Register */ - u32 sipnr_h; /* System Internal Interrupt Pending Register - High */ - u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */ - u32 siprr_a; /* System Internal Interrupt Group A Priority Register */ - u8 res0[8]; - u32 siprr_d; /* System Internal Interrupt Group D Priority Register */ - u32 simsr_h; /* System Internal Interrupt Mask Register - High */ - u32 simsr_l; /* System Internal Interrupt Mask Register - Low */ - u8 res1[4]; - u32 sepnr; /* System External Interrupt Pending Register */ - u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */ - u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */ - u32 semsr; /* System External Interrupt Mask Register */ - u32 secnr; /* System External Interrupt Control Register */ - u32 sersr; /* System Error Status Register */ - u32 sermr; /* System Error Mask Register */ - u32 sercr; /* System Error Control Register */ - u8 res2[4]; - u32 sifcr_h; /* System Internal Interrupt Force Register - High */ - u32 sifcr_l; /* System Internal Interrupt Force Register - Low */ - u32 sefcr; /* System External Interrupt Force Register */ - u32 serfr; /* System Error Force Register */ - u32 scvcr; /* System Critical Interrupt Vector Register */ - u32 smvcr; /* System Management Interrupt Vector Register */ - u8 res3[0x98]; -} ipic83xx_t; +typedef struct ipic8349 { + u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */ +#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ +#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ +#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */ +#define SICFR_IPSD 0x00080000 /* Internal interrupts Priority Scheme for group D */ +#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */ +#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */ +#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT) + u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */ +#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */ +#define SICVR_IVEC 0x0000007f /* Interrupt vector */ +#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) + u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ +#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ +#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ +#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ +#define SIIH_TSEC2TX 0x10000000 /* TSEC2 Tx interrupt */ +#define SIIH_TSEC2RX 0x08000000 /* TSEC2 Rx interrupt */ +#define SIIH_TSEC2ER 0x04000000 /* TSEC2 Eror interrupt */ +#define SIIH_USB2DR 0x02000000 /* USB2 DR interrupt */ +#define SIIH_USB2MPH 0x01000000 /* USB2 MPH interrupt */ +#define SIIH_UART1 0x00000080 /* UART1 interrupt */ +#define SIIH_UART2 0x00000040 /* UART2 interrupt */ +#define SIIH_SEC 0x00000020 /* SEC interrupt */ +#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ +#define SIIH_I2C2 0x00000002 /* I2C1 interrupt */ +#define SIIH_SPI 0x00000001 /* SPI interrupt */ +#define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \ + | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \ + | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \ + | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \ + | SIIH_I2C2 | SIIH_SPI) + u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ +#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ +#define SIIL_PIT 0x40000000 /* PIT interrupt */ +#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ +#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */ +#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */ +#define SIIL_MU 0x04000000 /* Message Unit interrupt */ +#define SIIL_SBA 0x02000000 /* System Bus Arbiter interrupt */ +#define SIIL_DMA 0x01000000 /* DMA interrupt */ +#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */ +#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */ +#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */ +#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */ +#define SIIL_DDR 0x00080000 /* DDR interrupt */ +#define SIIL_LBC 0x00040000 /* LBC interrupt */ +#define SIIL_GTM2 0x00020000 /* GTM2 interrupt */ +#define SIIL_GTM6 0x00010000 /* GTM6 interrupt */ +#define SIIL_PMC 0x00008000 /* PMC interrupt */ +#define SIIL_GTM3 0x00000800 /* GTM3 interrupt */ +#define SIIL_GTM7 0x00000400 /* GTM7 interrupt */ +#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ +#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ +#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ +#define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \ + | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \ + | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \ + | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \ + | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \ + | SIIL_GTM5 |SIIL_DPTC ) + u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */ + u8 res0[8]; + u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */ + u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */ + u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */ + u8 res1[4]; + u32 sepnr; /* System External Interrupt Pending Register (SEI) */ + u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */ + u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */ +#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */ +#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */ +#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */ +#define PRR_3 0x00700000 /* Priority Register, Position 3 programming */ +#define PRR_4 0x0000e000 /* Priority Register, Position 4 programming */ +#define PRR_5 0x00001c00 /* Priority Register, Position 5 programming */ +#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */ +#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */ +#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7) + u32 semsr; /* System External Interrupt Mask Register (SEI) */ +#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */ +#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */ +#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */ +#define SEI_IRQ3 0x10000000 /* IRQ3 external interrupt */ +#define SEI_IRQ4 0x08000000 /* IRQ4 external interrupt */ +#define SEI_IRQ5 0x04000000 /* IRQ5 external interrupt */ +#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */ +#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */ +#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */ +#define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \ + | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \ + | SEI_SIRQ0) + u32 secnr; /* System External Interrupt Control Register (SECNR) */ +#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ +#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ +#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ +#define SECNR_SYSA1T 0x00300000 /* MIXA1 priority position IPIC output interrupt type */ +#define SECNR_EDI0 0x00008000 /* IRQ0 external interrupt edge/level detect */ +#define SECNR_EDI1 0x00004000 /* IRQ1 external interrupt edge/level detect */ +#define SECNR_EDI2 0x00002000 /* IRQ2 external interrupt edge/level detect */ +#define SECNR_EDI3 0x00001000 /* IRQ3 external interrupt edge/level detect */ +#define SECNR_EDI4 0x00000800 /* IRQ4 external interrupt edge/level detect */ +#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */ +#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */ +#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */ +#define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \ + | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \ + | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \ + | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7) + u32 sersr; /* System Error Status Register (SERR) */ + u32 sermr; /* System Error Mask Register (SERR) */ +#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ +#define SERR_WDT 0x40000000 /* WDT MCP request */ +#define SERR_SBA 0x20000000 /* SBA MCP request */ +#define SERR_DDR 0x10000000 /* DDR MCP request */ +#define SERR_LBC 0x08000000 /* LBC MCP request */ +#define SERR_PCI1 0x04000000 /* PCI1 MCP request */ +#define SERR_PCI2 0x02000000 /* PCI2 MCP request */ +#define SERR_MU 0x01000000 /* MU MCP request */ +#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ +#define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \ + |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \ + |SERR_RNC ) + u32 sercr; /* System Error Control Register (SERCR) */ +#define SERCR_MCPR 0x00000001 /* MCP Route */ +#define SERCR_RES ~(SERCR_MCPR) + u8 res2[4]; + u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */ + u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */ + u32 sefcr; /* System External Interrupt Force Register (SEI) */ + u32 serfr; /* System Error Force Register (SERR) */ + u8 res3[0xA0]; +} ipic8349_t; /* * System Arbiter Registers */ -typedef struct arbiter83xx { - u32 acr; /* Arbiter Configuration Register */ - u32 atr; /* Arbiter Timers Register */ +typedef struct arbiter8349 { + u32 acr; /* Arbiter Configuration Register */ +#define ACR_COREDIS 0x10000000 /* Core disable. */ +#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ +#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ +#define ACR_RPTCNT 0x00000700 /* Repeat count. */ +#define ACR_APARK 0x00000030 /* Address parking. */ +#define ACR_PARKM 0x0000000F /* Parking master. */ +#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM) + u32 atr; /* Arbiter Timers Register */ +#define ATR_DTO 0x00FF0000 /* Data time out. */ +#define ATR_ATO 0x000000FF /* Address time out. */ +#define ATR_RES ~(ATR_DTO|ATR_ATO) u8 res[4]; - u32 aer; /* Arbiter Event Register */ - u32 aidr; /* Arbiter Interrupt Definition Register */ - u32 amr; /* Arbiter Mask Register */ - u32 aeatr; /* Arbiter Event Attributes Register */ - u32 aeadr; /* Arbiter Event Address Register */ - u32 aerr; /* Arbiter Event Response Register */ + u32 aer; /* Arbiter Event Register (AE)*/ + u32 aidr; /* Arbiter Interrupt Definition Register (AE) */ + u32 amr; /* Arbiter Mask Register (AE) */ + u32 aeatr; /* Arbiter Event Attributes Register */ +#define AEATR_EVENT 0x07000000 /* Event type. */ +#define AEATR_MSTR_ID 0x001F0000 /* Master Id. */ +#define AEATR_TBST 0x00000800 /* Transfer burst. */ +#define AEATR_TSIZE 0x00000700 /* Transfer Size. */ +#define AEATR_TTYPE 0x0000001F /* Transfer Type. */ +#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE) + u32 aeadr; /* Arbiter Event Address Register */ + u32 aerr; /* Arbiter Event Response Register (AE)*/ +#define AE_ETEA 0x00000020 /* Transfer error. */ +#define AE_RES_ 0x00000010 /* Reserved transfer type. */ +#define AE_ECW 0x00000008 /* External control word transfer type. */ +#define AE_AO 0x00000004 /* Address Only transfer type. */ +#define AE_DTO 0x00000002 /* Data time out. */ +#define AE_ATO 0x00000001 /* Address time out. */ +#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO) u8 res1[0xDC]; -} arbiter83xx_t; +} arbiter8349_t; /* * Reset Module */ -typedef struct reset83xx { - u32 rcwl; /* Reset Configuration Word Low Register */ - u32 rcwh; /* Reset Configuration Word High Register */ - u8 res0[8]; - u32 rsr; /* Reset Status Register */ - u32 rmr; /* Reset Mode Register */ - u32 rpr; /* Reset protection Register */ - u32 rcr; /* Reset Control Register */ - u32 rcer; /* Reset Control Enable Register */ - u8 res1[0xDC]; -} reset83xx_t; +typedef struct reset8349 { + u32 rcwl; /* RCWL Register */ +#define RCWL_LBIUCM 0x80000000 /* LBIUCM */ +#define RCWL_LBIUCM_SHIFT 31 +#define RCWL_DDRCM 0x40000000 /* DDRCM */ +#define RCWL_DDRCM_SHIFT 30 +#define RCWL_SVCOD 0x30000000 /* SVCOD */ +#define RCWL_SPMF 0x0f000000 /* SPMF */ +#define RCWL_SPMF_SHIFT 24 +#define RCWL_COREPLL 0x007F0000 /* COREPLL */ +#define RCWL_COREPLL_SHIFT 16 +#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ +#define RCWL_CEPDF 0x00000020 /* CEPDF */ +#define RCWL_CEPMF 0x0000001F /* CEPMF */ +#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) + u32 rcwh; /* RCHL Register */ +#define RCWH_PCIHOST 0x80000000 /* PCIHOST */ +#define RCWH_PCIHOST_SHIFT 31 +#define RCWH_PCI64 0x40000000 /* PCI64 */ +#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */ +#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */ +#define RCWH_COREDIS 0x08000000 /* COREDIS */ +#define RCWH_BMS 0x04000000 /* BMS */ +#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */ +#define RCWH_SWEN 0x00800000 /* SWEN */ +#define RCWH_ROMLOC 0x00700000 /* ROMLOC */ +#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */ +#define RCWH_TSEC2M 0x00003000 /* TSEC2M */ +#define RCWH_TPR 0x00000100 /* TPR */ +#define RCWH_TLE 0x00000008 /* TLE */ +#define RCWH_LALE 0x00000004 /* LALE */ +#define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \ + | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \ + | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \ + | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \ + | RCWH_TLE | RCWH_LALE) + u8 res0[8]; + u32 rsr; /* Reset status Register */ +#define RSR_RSTSRC 0xE0000000 /* Reset source */ +#define RSR_RSTSRC_SHIFT 29 +#define RSR_BSF 0x00010000 /* Boot seq. fail */ +#define RSR_BSF_SHIFT 16 +#define RSR_SWSR 0x00002000 /* software soft reset */ +#define RSR_SWSR_SHIFT 13 +#define RSR_SWHR 0x00001000 /* software hard reset */ +#define RSR_SWHR_SHIFT 12 +#define RSR_JHRS 0x00000200 /* jtag hreset */ +#define RSR_JHRS_SHIFT 9 +#define RSR_JSRS 0x00000100 /* jtag sreset status */ +#define RSR_JSRS_SHIFT 8 +#define RSR_CSHR 0x00000010 /* checkstop reset status */ +#define RSR_CSHR_SHIFT 4 +#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +#define RSR_SWRS_SHIFT 3 +#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +#define RSR_BMRS_SHIFT 2 +#define RSR_SRS 0x00000002 /* soft reset status */ +#define RSR_SRS_SHIFT 1 +#define RSR_HRS 0x00000001 /* hard reset status */ +#define RSR_HRS_SHIFT 0 +#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS) + u32 rmr; /* Reset mode Register */ +#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +#define RMR_CSRE_SHIFT 0 +#define RMR_RES ~(RMR_CSRE) + u32 rpr; /* Reset protection Register */ + u32 rcr; /* Reset Control Register */ +#define RCR_SWHR 0x00000002 /* software hard reset */ +#define RCR_SWSR 0x00000001 /* software soft reset */ +#define RCR_RES ~(RCR_SWHR | RCR_SWSR) + u32 rcer; /* Reset Control Enable Register */ +#define RCER_CRE 0x00000001 /* software hard reset */ +#define RCER_RES ~(RCER_CRE) + u8 res1[0xDC]; +} reset8349_t; -/* - * Clock Module - */ -typedef struct clk83xx { - u32 spmr; /* system PLL mode Register */ - u32 occr; /* output clock control Register */ - u32 sccr; /* system clock control Register */ - u8 res0[0xF4]; -} clk83xx_t; +typedef struct clk8349 { + u32 spmr; /* system PLL mode Register */ +#define SPMR_LBIUCM 0x80000000 /* LBIUCM */ +#define SPMR_DDRCM 0x40000000 /* DDRCM */ +#define SPMR_SVCOD 0x30000000 /* SVCOD */ +#define SPMR_SPMF 0x0F000000 /* SPMF */ +#define SPMR_CKID 0x00800000 /* CKID */ +#define SPMR_CKID_SHIFT 23 +#define SPMR_COREPLL 0x007F0000 /* COREPLL */ +#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ +#define SPMR_CEPDF 0x00000020 /* CEPDF */ +#define SPMR_CEPMF 0x0000001F /* CEPMF */ +#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \ + | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \ + | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF) + u32 occr; /* output clock control Register */ +#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ +#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ +#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ +#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */ +#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */ +#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */ +#define OCCR_PCICOE6 0x02000000 /* PCICOE6 */ +#define OCCR_PCICOE7 0x01000000 /* PCICOE7 */ +#define OCCR_PCICD0 0x00800000 /* PCICD0 */ +#define OCCR_PCICD1 0x00400000 /* PCICD1 */ +#define OCCR_PCICD2 0x00200000 /* PCICD2 */ +#define OCCR_PCICD3 0x00100000 /* PCICD3 */ +#define OCCR_PCICD4 0x00080000 /* PCICD4 */ +#define OCCR_PCICD5 0x00040000 /* PCICD5 */ +#define OCCR_PCICD6 0x00020000 /* PCICD6 */ +#define OCCR_PCICD7 0x00010000 /* PCICD7 */ +#define OCCR_PCI1CR 0x00000002 /* PCI1CR */ +#define OCCR_PCI2CR 0x00000001 /* PCI2CR */ +#define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \ + | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \ + | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \ + | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \ + | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \ + | OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR ) + u32 sccr; /* system clock control Register */ +#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ +#define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ +#define SCCR_TSEC2CM_SHIFT 28 +#define SCCR_ENCCM 0x03000000 /* ENCCM */ +#define SCCR_ENCCM_SHIFT 24 +#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */ +#define SCCR_USBMPHCM_SHIFT 22 +#define SCCR_USBDRCM 0x00300000 /* USBDRCM */ +#define SCCR_USBDRCM_SHIFT 20 +#define SCCR_PCICM 0x00010000 /* PCICM */ +#define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \ + | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM) + u8 res0[0xF4]; +} clk8349_t; /* * Power Management Control Module */ -typedef struct pmc83xx { - u32 pmccr; /* PMC Configuration Register */ - u32 pmcer; /* PMC Event Register */ - u32 pmcmr; /* PMC Mask Register */ - u32 pmccr1; /* PMC Configuration Register 1 */ - u32 pmccr2; /* PMC Configuration Register 2 */ - u8 res0[0xEC]; -} pmc83xx_t; +typedef struct pmc8349 { + u32 pmccr; /* PMC Configuration Register */ +#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ +#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ +#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN) + u32 pmcer; /* PMC Event Register */ +#define PMCER_PMCI 0x00000001 /* PMC Interrupt */ +#define PMCER_RES ~(PMCER_PMCI) + u32 pmcmr; /* PMC Mask Register */ +#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ +#define PMCMR_RES ~(PMCMR_PMCIE) + u8 res0[0xF4]; +} pmc8349_t; + /* - * General purpose I/O module + * general purpose I/O module */ -typedef struct gpio83xx { - u32 dir; /* direction register */ - u32 odr; /* open drain register */ - u32 dat; /* data register */ - u32 ier; /* interrupt event register */ - u32 imr; /* interrupt mask register */ - u32 icr; /* external interrupt control register */ +typedef struct gpio8349 { + u32 dir; /* direction register */ + u32 odr; /* open drain register */ + u32 dat; /* data register */ + u32 ier; /* interrupt event register */ + u32 imr; /* interrupt mask register */ + u32 icr; /* external interrupt control register */ u8 res0[0xE8]; -} gpio83xx_t; - -/* - * QE Ports Interrupts Registers - */ -typedef struct qepi83xx { - u8 res0[0xC]; - u32 qepier; /* QE Ports Interrupt Event Register */ - u32 qepimr; /* QE Ports Interrupt Mask Register */ - u32 qepicr; /* QE Ports Interrupt Control Register */ - u8 res1[0xE8]; -} qepi83xx_t; - -/* - * QE Parallel I/O Ports - */ -typedef struct gpio_n { - u32 podr; /* Open Drain Register */ - u32 pdat; /* Data Register */ - u32 dir1; /* direction register 1 */ - u32 dir2; /* direction register 2 */ - u32 ppar1; /* Pin Assignment Register 1 */ - u32 ppar2; /* Pin Assignment Register 2 */ -} gpio_n_t; - -typedef struct qegpio83xx { - gpio_n_t ioport[0x7]; - u8 res0[0x358]; -} qepio83xx_t; - -/* - * QE Secondary Bus Access Windows - */ -typedef struct qesba83xx { - u32 lbmcsar; /* Local bus memory controller start address */ - u32 sdmcsar; /* Secondary DDR memory controller start address */ - u8 res0[0x38]; - u32 lbmcear; /* Local bus memory controller end address */ - u32 sdmcear; /* Secondary DDR memory controller end address */ - u8 res1[0x38]; - u32 lbmcar; /* Local bus memory controller attributes */ - u32 sdmcar; /* Secondary DDR memory controller attributes */ - u8 res2[0x378]; -} qesba83xx_t; +} gpio8349_t; /* * DDR Memory Controller Memory Map */ -typedef struct ddr_cs_bnds { +typedef struct ddr_cs_bnds{ u32 csbnds; - u8 res0[4]; +#define CSBNDS_SA 0x00FF0000 +#define CSBNDS_SA_SHIFT 8 +#define CSBNDS_EA 0x000000FF +#define CSBNDS_EA_SHIFT 24 + u8 res0[4]; } ddr_cs_bnds_t; -typedef struct ddr83xx { - ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ +typedef struct ddr8349{ + ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */ u8 res0[0x60]; - u32 cs_config[4]; /* Chip Select x Configuration */ - u8 res1[0x70]; - u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ - u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ - u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ - u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ - u32 sdram_cfg; /* SDRAM Control Configuration */ - u32 sdram_cfg2; /* SDRAM Control Configuration 2 */ - u32 sdram_mode; /* SDRAM Mode Configuration */ - u32 sdram_mode2; /* SDRAM Mode Configuration 2 */ - u32 sdram_md_cntl; /* SDRAM Mode Control */ - u32 sdram_interval; /* SDRAM Interval Configuration */ - u32 ddr_data_init; /* SDRAM Data Initialization */ + u32 cs_config[4]; /**< Chip Select x Configuration */ +#define CSCONFIG_EN 0x80000000 +#define CSCONFIG_AP 0x00800000 +#define CSCONFIG_ROW_BIT 0x00000700 +#define CSCONFIG_ROW_BIT_12 0x00000000 +#define CSCONFIG_ROW_BIT_13 0x00000100 +#define CSCONFIG_ROW_BIT_14 0x00000200 +#define CSCONFIG_COL_BIT 0x00000007 +#define CSCONFIG_COL_BIT_8 0x00000000 +#define CSCONFIG_COL_BIT_9 0x00000001 +#define CSCONFIG_COL_BIT_10 0x00000002 +#define CSCONFIG_COL_BIT_11 0x00000003 + u8 res1[0x78]; + u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */ +#define TIMING_CFG1_PRETOACT 0x70000000 +#define TIMING_CFG1_PRETOACT_SHIFT 28 +#define TIMING_CFG1_ACTTOPRE 0x0F000000 +#define TIMING_CFG1_ACTTOPRE_SHIFT 24 +#define TIMING_CFG1_ACTTORW 0x00700000 +#define TIMING_CFG1_ACTTORW_SHIFT 20 +#define TIMING_CFG1_CASLAT 0x00070000 +#define TIMING_CFG1_CASLAT_SHIFT 16 +#define TIMING_CFG1_REFREC 0x0000F000 +#define TIMING_CFG1_REFREC_SHIFT 12 +#define TIMING_CFG1_WRREC 0x00000700 +#define TIMING_CFG1_WRREC_SHIFT 8 +#define TIMING_CFG1_ACTTOACT 0x00000070 +#define TIMING_CFG1_ACTTOACT_SHIFT 4 +#define TIMING_CFG1_WRTORD 0x00000007 +#define TIMING_CFG1_WRTORD_SHIFT 0 +#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ +#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ + + u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ +#define TIMING_CFG2_CPO 0x0F000000 +#define TIMING_CFG2_CPO_SHIFT 24 +#define TIMING_CFG2_ACSM 0x00080000 +#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 +#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 +#define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ + + u32 sdram_cfg; /**< SDRAM Control Configuration */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 + u8 res2[4]; - u32 sdram_clk_cntl; /* SDRAM Clock Control */ - u8 res3[0x14]; - u32 ddr_init_addr; /* DDR training initialization address */ - u32 ddr_init_ext_addr; /* DDR training initialization extended address */ - u8 res4[0xAA8]; - u32 ddr_ip_rev1; /* DDR IP block revision 1 */ - u32 ddr_ip_rev2; /* DDR IP block revision 2 */ - u8 res5[0x200]; - u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ - u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ - u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ + u32 sdram_mode; /**< SDRAM Mode Configuration */ +#define SDRAM_MODE_ESD 0xFFFF0000 +#define SDRAM_MODE_ESD_SHIFT 16 +#define SDRAM_MODE_SD 0x0000FFFF +#define SDRAM_MODE_SD_SHIFT 0 +#define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ +#define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ +#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ +#define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ +#define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ +#define DDR_MODE_WEAK 0x0002 /* weak drivers */ +#define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ +#define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ +#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ +#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ +#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ +#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ +#define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ +#define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ +#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ +#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ +#define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125 µs */ +#define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ +#define DDR_MODE_MODEREG 0x0000 /* select mode register */ + + u8 res3[8]; + u32 sdram_interval; /**< SDRAM Interval Configuration */ +#define SDRAM_INTERVAL_REFINT 0x3FFF0000 +#define SDRAM_INTERVAL_REFINT_SHIFT 16 +#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF +#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 + u8 res9[8]; + u32 sdram_clk_cntl; +#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 +#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 + + u8 res4[0xCCC]; + u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ + u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ + u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ +#define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ +#define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ +#define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ +#define ECC_ERR_INJECT_EEIM_SHIFT 0 + u8 res5[0x14]; + u32 capture_data_hi; /**< Memory Data Path Read Capture High */ + u32 capture_data_lo; /**< Memory Data Path Read Capture Low */ + u32 capture_ecc; /**< Memory Data Path Read Capture ECC */ +#define CAPTURE_ECC_ECE (0xff000000>>24) +#define CAPTURE_ECC_ECE_SHIFT 0 u8 res6[0x14]; - u32 capture_data_hi; /* Memory Data Path Read Capture High */ - u32 capture_data_lo; /* Memory Data Path Read Capture Low */ - u32 capture_ecc; /* Memory Data Path Read Capture ECC */ - u8 res7[0x14]; - u32 err_detect; /* Memory Error Detect */ - u32 err_disable; /* Memory Error Disable */ - u32 err_int_en; /* Memory Error Interrupt Enable */ - u32 capture_attributes; /* Memory Error Attributes Capture */ - u32 capture_address; /* Memory Error Address Capture */ - u32 capture_ext_address;/* Memory Error Extended Address Capture */ - u32 err_sbe; /* Memory Single-Bit ECC Error Management */ - u8 res8[0xA4]; + u32 err_detect; /**< Memory Error Detect */ +#define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ +#define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ +#define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ +#define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ + u32 err_disable; /**< Memory Error Disable */ +#define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ +#define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ +#define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ +#define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED|ECC_ERROR_DISABLE_SBED|ECC_ERROR_DISABLE_MBED) + u32 err_int_en; /**< Memory Error Interrupt Enable */ +#define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ +#define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ +#define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ +#define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE|ECC_ERR_INT_EN_SBEE|ECC_ERR_INT_EN_MSEE) + u32 capture_attributes; /**< Memory Error Attributes Capture */ +#define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ +#define ECC_CAPT_ATTR_BNUM_SHIFT 28 +#define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ +#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 +#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 +#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 +#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 +#define ECC_CAPT_ATTR_TSIZ_SHIFT 24 +#define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ +#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 +#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 +#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 +#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 +#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) +#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 +#define ECC_CAPT_ATTR_TSRC_I2C 0x9 +#define ECC_CAPT_ATTR_TSRC_JTAG 0xA +#define ECC_CAPT_ATTR_TSRC_PCI1 0xD +#define ECC_CAPT_ATTR_TSRC_PCI2 0xE +#define ECC_CAPT_ATTR_TSRC_DMA 0xF +#define ECC_CAPT_ATTR_TSRC_SHIFT 16 +#define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ +#define ECC_CAPT_ATTR_TTYP_WRITE 0x1 +#define ECC_CAPT_ATTR_TTYP_READ 0x2 +#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 +#define ECC_CAPT_ATTR_TTYP_SHIFT 12 +#define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ + u32 capture_address; /**< Memory Error Address Capture */ + u32 capture_ext_address;/**< Memory Error Extended Address Capture */ + u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ +#define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255*/ +#define ECC_ERROR_MAN_SBET_SHIFT 16 +#define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255*/ +#define ECC_ERROR_MAN_SBEC_SHIFT 0 + u8 res7[0xA4]; u32 debug_reg; - u8 res9[0xFC]; -} ddr83xx_t; + u8 res8[0xFC]; +} ddr8349_t; + +/* + * I2C1 Controller + */ + /* * DUART */ -typedef struct duart83xx { - u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */ - u8 uier_udmb; /* combined register for UIER and UDMB */ - u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */ - u8 ulcr; /* line control register */ - u8 umcr; /* MODEM control register */ - u8 ulsr; /* line status register */ - u8 umsr; /* MODEM status register */ - u8 uscr; /* scratch register */ +typedef struct duart8349{ + u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */ + u8 uier_udmb; /**< combined register for UIER and UDMB */ + u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */ + u8 ulcr; /**< line control register */ + u8 umcr; /**< MODEM control register */ + u8 ulsr; /**< line status register */ + u8 umsr; /**< MODEM status register */ + u8 uscr; /**< scratch register */ u8 res0[8]; - u8 udsr; /* DMA status register */ + u8 udsr; /**< DMA status register */ u8 res1[3]; u8 res2[0xEC]; -} duart83xx_t; +} duart8349_t; /* * Local Bus Controller Registers */ -typedef struct lbus_bank { - u32 br; /* Base Register */ - u32 or; /* Option Register */ +typedef struct lbus_bank{ + u32 br; /**< Base Register */ + u32 or; /**< Base Register */ } lbus_bank_t; -typedef struct lbus83xx { +typedef struct lbus8349 { lbus_bank_t bank[8]; u8 res0[0x28]; - u32 mar; /* UPM Address Register */ + u32 mar; /**< UPM Address Register */ u8 res1[0x4]; - u32 mamr; /* UPMA Mode Register */ - u32 mbmr; /* UPMB Mode Register */ - u32 mcmr; /* UPMC Mode Register */ + u32 mamr; /**< UPMA Mode Register */ + u32 mbmr; /**< UPMB Mode Register */ + u32 mcmr; /**< UPMC Mode Register */ u8 res2[0x8]; - u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ - u32 mdr; /* UPM Data Register */ - u8 res3[0x4]; - u32 lsor; /* Special Operation Initiation Register */ - u32 lsdmr; /* SDRAM Mode Register */ + u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ + u32 mdr; /**< UPM Data Register */ + u8 res3[0x8]; + u32 lsdmr; /**< SDRAM Mode Register */ u8 res4[0x8]; - u32 lurt; /* UPM Refresh Timer */ - u32 lsrt; /* SDRAM Refresh Timer */ + u32 lurt; /**< UPM Refresh Timer */ + u32 lsrt; /**< SDRAM Refresh Timer */ u8 res5[0x8]; - u32 ltesr; /* Transfer Error Status Register */ - u32 ltedr; /* Transfer Error Disable Register */ - u32 lteir; /* Transfer Error Interrupt Register */ - u32 lteatr; /* Transfer Error Attributes Register */ - u32 ltear; /* Transfer Error Address Register */ + u32 ltesr; /**< Transfer Error Status Register */ + u32 ltedr; /**< Transfer Error Disable Register */ + u32 lteir; /**< Transfer Error Interrupt Register */ + u32 lteatr; /**< Transfer Error Attributes Register */ + u32 ltear; /**< Transfer Error Address Register */ u8 res6[0xC]; - u32 lbcr; /* Configuration Register */ - u32 lcrr; /* Clock Ratio Register */ - u8 res7[0x8]; - u32 fmr; /* Flash Mode Register */ - u32 fir; /* Flash Instruction Register */ - u32 fcr; /* Flash Command Register */ - u32 fbar; /* Flash Block Addr Register */ - u32 fpar; /* Flash Page Addr Register */ - u32 fbcr; /* Flash Byte Count Register */ - u8 res8[0xF08]; -} lbus83xx_t; + u32 lbcr; /**< Configuration Register */ +#define LBCR_LDIS 0x80000000 +#define LBCR_LDIS_SHIFT 31 +#define LBCR_BCTLC 0x00C00000 +#define LBCR_BCTLC_SHIFT 22 +#define LBCR_LPBSE 0x00020000 +#define LBCR_LPBSE_SHIFT 17 +#define LBCR_EPAR 0x00010000 +#define LBCR_EPAR_SHIFT 16 +#define LBCR_BMT 0x0000FF00 +#define LBCR_BMT_SHIFT 8 + u32 lcrr; /**< Clock Ratio Register */ +#define LCRR_DBYP 0x80000000 +#define LCRR_DBYP_SHIFT 31 +#define LCRR_BUFCMDC 0x30000000 +#define LCRR_BUFCMDC_SHIFT 28 +#define LCRR_ECL 0x03000000 +#define LCRR_ECL_SHIFT 24 +#define LCRR_EADC 0x00030000 +#define LCRR_EADC_SHIFT 16 +#define LCRR_CLKDIV 0x0000000F +#define LCRR_CLKDIV_SHIFT 0 + + + u8 res7[0x28]; + u8 res8[0xF00]; +} lbus8349_t; + +/* + * Serial Peripheral Interface + */ +typedef struct spi8349 +{ + u32 mode; /**< mode register */ + u32 event; /**< event register */ + u32 mask; /**< mask register */ + u32 com; /**< command register */ + u8 res0[0x10]; + u32 tx; /**< transmit register */ + u32 rx; /**< receive register */ + u8 res1[0xD8]; +} spi8349_t; + /* * DMA/Messaging Unit */ -typedef struct dma83xx { - u32 res0[0xC]; /* 0x0-0x29 reseverd */ - u32 omisr; /* 0x30 Outbound message interrupt status register */ - u32 omimr; /* 0x34 Outbound message interrupt mask register */ - u32 res1[0x6]; /* 0x38-0x49 reserved */ - u32 imr0; /* 0x50 Inbound message register 0 */ - u32 imr1; /* 0x54 Inbound message register 1 */ - u32 omr0; /* 0x58 Outbound message register 0 */ - u32 omr1; /* 0x5C Outbound message register 1 */ - u32 odr; /* 0x60 Outbound doorbell register */ - u32 res2; /* 0x64-0x67 reserved */ - u32 idr; /* 0x68 Inbound doorbell register */ - u32 res3[0x5]; /* 0x6C-0x79 reserved */ - u32 imisr; /* 0x80 Inbound message interrupt status register */ - u32 imimr; /* 0x84 Inbound message interrupt mask register */ - u32 res4[0x1E]; /* 0x88-0x99 reserved */ - u32 dmamr0; /* 0x100 DMA 0 mode register */ - u32 dmasr0; /* 0x104 DMA 0 status register */ - u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ - u32 res5; /* 0x10C reserved */ - u32 dmasar0; /* 0x110 DMA 0 source address register */ - u32 res6; /* 0x114 reserved */ - u32 dmadar0; /* 0x118 DMA 0 destination address register */ - u32 res7; /* 0x11C reserved */ - u32 dmabcr0; /* 0x120 DMA 0 byte count register */ - u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ - u32 res8[0x16]; /* 0x128-0x179 reserved */ - u32 dmamr1; /* 0x180 DMA 1 mode register */ - u32 dmasr1; /* 0x184 DMA 1 status register */ - u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ - u32 res9; /* 0x18C reserved */ - u32 dmasar1; /* 0x190 DMA 1 source address register */ - u32 res10; /* 0x194 reserved */ - u32 dmadar1; /* 0x198 DMA 1 destination address register */ - u32 res11; /* 0x19C reserved */ - u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ - u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ - u32 res12[0x16]; /* 0x1A8-0x199 reserved */ - u32 dmamr2; /* 0x200 DMA 2 mode register */ - u32 dmasr2; /* 0x204 DMA 2 status register */ - u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ - u32 res13; /* 0x20C reserved */ - u32 dmasar2; /* 0x210 DMA 2 source address register */ - u32 res14; /* 0x214 reserved */ - u32 dmadar2; /* 0x218 DMA 2 destination address register */ - u32 res15; /* 0x21C reserved */ - u32 dmabcr2; /* 0x220 DMA 2 byte count register */ - u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ - u32 res16[0x16]; /* 0x228-0x279 reserved */ - u32 dmamr3; /* 0x280 DMA 3 mode register */ - u32 dmasr3; /* 0x284 DMA 3 status register */ - u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ - u32 res17; /* 0x28C reserved */ - u32 dmasar3; /* 0x290 DMA 3 source address register */ - u32 res18; /* 0x294 reserved */ - u32 dmadar3; /* 0x298 DMA 3 destination address register */ - u32 res19; /* 0x29C reserved */ - u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ - u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ - u32 dmagsr; /* 0x2A8 DMA general status register */ - u32 res20[0x15]; /* 0x2AC-0x2FF reserved */ -} dma83xx_t; +typedef struct dma8349 { + u32 res0[0xC]; /* 0x0-0x29 reseverd */ + u32 omisr; /* 0x30 Outbound message interrupt status register */ + u32 omimr; /* 0x34 Outbound message interrupt mask register */ + u32 res1[0x6]; /* 0x38-0x49 reserved */ + + u32 imr0; /* 0x50 Inbound message register 0 */ + u32 imr1; /* 0x54 Inbound message register 1 */ + u32 omr0; /* 0x58 Outbound message register 0 */ + u32 omr1; /* 0x5C Outbound message register 1 */ + + u32 odr; /* 0x60 Outbound doorbell register */ + u32 res2; /* 0x64-0x67 reserved */ + u32 idr; /* 0x68 Inbound doorbell register */ + u32 res3[0x5]; /* 0x6C-0x79 reserved */ + + u32 imisr; /* 0x80 Inbound message interrupt status register */ + u32 imimr; /* 0x84 Inbound message interrupt mask register */ + u32 res4[0x1E]; /* 0x88-0x99 reserved */ + + u32 dmamr0; /* 0x100 DMA 0 mode register */ + u32 dmasr0; /* 0x104 DMA 0 status register */ + u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ + u32 res5; /* 0x10C reserved */ + u32 dmasar0; /* 0x110 DMA 0 source address register */ + u32 res6; /* 0x114 reserved */ + u32 dmadar0; /* 0x118 DMA 0 destination address register */ + u32 res7; /* 0x11C reserved */ + u32 dmabcr0; /* 0x120 DMA 0 byte count register */ + u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ + u32 res8[0x16]; /* 0x128-0x179 reserved */ + + u32 dmamr1; /* 0x180 DMA 1 mode register */ + u32 dmasr1; /* 0x184 DMA 1 status register */ + u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ + u32 res9; /* 0x18C reserved */ + u32 dmasar1; /* 0x190 DMA 1 source address register */ + u32 res10; /* 0x194 reserved */ + u32 dmadar1; /* 0x198 DMA 1 destination address register */ + u32 res11; /* 0x19C reserved */ + u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ + u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ + u32 res12[0x16];/* 0x1A8-0x199 reserved */ + + u32 dmamr2; /* 0x200 DMA 2 mode register */ + u32 dmasr2; /* 0x204 DMA 2 status register */ + u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ + u32 res13; /* 0x20C reserved */ + u32 dmasar2; /* 0x210 DMA 2 source address register */ + u32 res14; /* 0x214 reserved */ + u32 dmadar2; /* 0x218 DMA 2 destination address register */ + u32 res15; /* 0x21C reserved */ + u32 dmabcr2; /* 0x220 DMA 2 byte count register */ + u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ + u32 res16[0x16];/* 0x228-0x279 reserved */ + + u32 dmamr3; /* 0x280 DMA 3 mode register */ + u32 dmasr3; /* 0x284 DMA 3 status register */ + u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ + u32 res17; /* 0x28C reserved */ + u32 dmasar3; /* 0x290 DMA 3 source address register */ + u32 res18; /* 0x294 reserved */ + u32 dmadar3; /* 0x298 DMA 3 destination address register */ + u32 res19; /* 0x29C reserved */ + u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ + u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ + + u32 dmagsr; /* 0x2A8 DMA general status register */ + u32 res20[0x15];/* 0x2AC-0x2FF reserved */ +} dma8349_t; + +/* DMAMRn bits */ +#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */ +#define DMA_CHANNEL_TRANSFER_MODE_DIRECT (0x00000004) /* Bit - DMAMRn CTM */ +#define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN (0x00001000) /* Bit - DMAMRn SAHE */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B (0x00000000) /* 2Bit- DMAMRn SAHTS 1byte */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B (0x00004000) /* 2Bit- DMAMRn SAHTS 2bytes */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B (0x00008000) /* 2Bit- DMAMRn SAHTS 4bytes */ +#define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B (0x0000c000) /* 2Bit- DMAMRn SAHTS 8bytes */ +#define DMA_CHANNEL_SNOOP (0x00010000) /* Bit - DMAMRn DMSEN */ + +/* DMASRn bits */ +#define DMA_CHANNEL_BUSY (0x00000004) /* Bit - DMASRn CB */ +#define DMA_CHANNEL_TRANSFER_ERROR (0x00000080) /* Bit - DMASRn TE */ /* * PCI Software Configuration Registers */ -typedef struct pciconf83xx { - u32 config_address; +typedef struct pciconf8349 { + u32 config_address; +#define PCI_CONFIG_ADDRESS_EN 0x80000000 +#define PCI_CONFIG_ADDRESS_BN_SHIFT 16 +#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 +#define PCI_CONFIG_ADDRESS_DN_SHIFT 11 +#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 +#define PCI_CONFIG_ADDRESS_FN_SHIFT 8 +#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 +#define PCI_CONFIG_ADDRESS_RN_SHIFT 0 +#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc u32 config_data; u32 int_ack; - u8 res[116]; -} pciconf83xx_t; + u8 res[116]; +} pciconf8349_t; /* * PCI Outbound Translation Register */ typedef struct pci_outbound_window { - u32 potar; - u8 res0[4]; - u32 pobar; - u8 res1[4]; - u32 pocmr; - u8 res2[4]; -} pot83xx_t; - + u32 potar; + u8 res0[4]; + u32 pobar; + u8 res1[4]; + u32 pocmr; + u8 res2[4]; +} pot8349_t; /* * Sequencer */ -typedef struct ios83xx { - pot83xx_t pot[6]; - u8 res0[0x60]; - u32 pmcr; - u8 res1[4]; - u32 dtcr; - u8 res2[4]; -} ios83xx_t; +typedef struct ios8349 { + pot8349_t pot[6]; +#define POTAR_TA_MASK 0x000fffff +#define POBAR_BA_MASK 0x000fffff +#define POCMR_EN 0x80000000 +#define POCMR_IO 0x40000000 /* 0--memory space 1--I/O space */ +#define POCMR_SE 0x20000000 /* streaming enable */ +#define POCMR_DST 0x10000000 /* 0--PCI1 1--PCI2*/ +#define POCMR_CM_MASK 0x000fffff +#define POCMR_CM_4G 0x00000000 +#define POCMR_CM_2G 0x00080000 +#define POCMR_CM_1G 0x000C0000 +#define POCMR_CM_512M 0x000E0000 +#define POCMR_CM_256M 0x000F0000 +#define POCMR_CM_128M 0x000F8000 +#define POCMR_CM_64M 0x000FC000 +#define POCMR_CM_32M 0x000FE000 +#define POCMR_CM_16M 0x000FF000 +#define POCMR_CM_8M 0x000FF800 +#define POCMR_CM_4M 0x000FFC00 +#define POCMR_CM_2M 0x000FFE00 +#define POCMR_CM_1M 0x000FFF00 +#define POCMR_CM_512K 0x000FFF80 +#define POCMR_CM_256K 0x000FFFC0 +#define POCMR_CM_128K 0x000FFFE0 +#define POCMR_CM_64K 0x000FFFF0 +#define POCMR_CM_32K 0x000FFFF8 +#define POCMR_CM_16K 0x000FFFFC +#define POCMR_CM_8K 0x000FFFFE +#define POCMR_CM_4K 0x000FFFFF + u8 res0[0x60]; + u32 pmcr; + u8 res1[4]; + u32 dtcr; + u8 res2[4]; +} ios8349_t; /* * PCI Controller Control and Status Registers */ -typedef struct pcictrl83xx { - u32 esr; - u32 ecdr; +typedef struct pcictrl8349 { + u32 esr; +#define ESR_MERR 0x80000000 +#define ESR_APAR 0x00000400 +#define ESR_PCISERR 0x00000200 +#define ESR_MPERR 0x00000100 +#define ESR_TPERR 0x00000080 +#define ESR_NORSP 0x00000040 +#define ESR_TABT 0x00000020 + u32 ecdr; +#define ECDR_APAR 0x00000400 +#define ECDR_PCISERR 0x00000200 +#define ECDR_MPERR 0x00000100 +#define ECDR_TPERR 0x00000080 +#define ECDR_NORSP 0x00000040 +#define ECDR_TABT 0x00000020 u32 eer; - u32 eatcr; - u32 eacr; - u32 eeacr; - u32 edlcr; - u32 edhcr; - u32 gcr; - u32 ecr; - u32 gsr; - u8 res0[12]; - u32 pitar2; - u8 res1[4]; - u32 pibar2; - u32 piebar2; - u32 piwar2; - u8 res2[4]; - u32 pitar1; - u8 res3[4]; - u32 pibar1; - u32 piebar1; - u32 piwar1; - u8 res4[4]; - u32 pitar0; - u8 res5[4]; - u32 pibar0; - u8 res6[4]; - u32 piwar0; - u8 res7[132]; -} pcictrl83xx_t; +#define EER_APAR 0x00000400 +#define EER_PCISERR 0x00000200 +#define EER_MPERR 0x00000100 +#define EER_TPERR 0x00000080 +#define EER_NORSP 0x00000040 +#define EER_TABT 0x00000020 + u32 eatcr; +#define EATCR_ERRTYPR_MASK 0x70000000 +#define EATCR_ERRTYPR_APR 0x00000000 /* address parity error */ +#define EATCR_ERRTYPR_WDPR 0x10000000 /* write data parity error */ +#define EATCR_ERRTYPR_RDPR 0x20000000 /* read data parity error */ +#define EATCR_ERRTYPR_MA 0x30000000 /* master abort */ +#define EATCR_ERRTYPR_TA 0x40000000 /* target abort */ +#define EATCR_ERRTYPR_SE 0x50000000 /* system error indication received */ +#define EATCR_ERRTYPR_PEA 0x60000000 /* parity error indication received on a read */ +#define EATCR_ERRTYPR_PEW 0x70000000 /* parity error indication received on a write */ +#define EATCR_BN_MASK 0x0f000000 /* beat number */ +#define EATCR_BN_1st 0x00000000 +#define EATCR_BN_2ed 0x01000000 +#define EATCR_BN_3rd 0x02000000 +#define EATCR_BN_4th 0x03000000 +#define EATCR_BN_5th 0x0400000 +#define EATCR_BN_6th 0x05000000 +#define EATCR_BN_7th 0x06000000 +#define EATCR_BN_8th 0x07000000 +#define EATCR_BN_9th 0x08000000 +#define EATCR_TS_MASK 0x00300000 /* transaction size */ +#define EATCR_TS_4 0x00000000 +#define EATCR_TS_1 0x00100000 +#define EATCR_TS_2 0x00200000 +#define EATCR_TS_3 0x00300000 +#define EATCR_ES_MASK 0x000f0000 /* error source */ +#define EATCR_ES_EM 0x00000000 /* external master */ +#define EATCR_ES_DMA 0x00050000 +#define EATCR_CMD_MASK 0x0000f000 +#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable*/ +#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ +#define EATCR_HPB 0x00000004 /* high parity bit */ +#define EATCR_PB 0x00000002 /* parity bit*/ +#define EATCR_VI 0x00000001 /* error information valid */ + u32 eacr; + u32 eeacr; + u32 edlcr; + u32 edhcr; + u32 gcr; + u32 ecr; + u32 gsr; + u8 res0[12]; + u32 pitar2; + u8 res1[4]; + u32 pibar2; + u32 piebar2; + u32 piwar2; + u8 res2[4]; + u32 pitar1; + u8 res3[4]; + u32 pibar1; + u32 piebar1; + u32 piwar1; + u8 res4[4]; + u32 pitar0; + u8 res5[4]; + u32 pibar0; + u8 res6[4]; + u32 piwar0; + u8 res7[132]; +#define PITAR_TA_MASK 0x000fffff +#define PIBAR_MASK 0xffffffff +#define PIEBAR_EBA_MASK 0x000fffff +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_RTT_MASK 0x000f0000 +#define PIWAR_RTT_NO_SNOOP 0x00040000 +#define PIWAR_RTT_SNOOP 0x00050000 +#define PIWAR_WTT_MASK 0x0000f000 +#define PIWAR_WTT_NO_SNOOP 0x00004000 +#define PIWAR_WTT_SNOOP 0x00005000 +#define PIWAR_IWS_MASK 0x0000003F +#define PIWAR_IWS_4K 0x0000000B +#define PIWAR_IWS_8K 0x0000000C +#define PIWAR_IWS_16K 0x0000000D +#define PIWAR_IWS_32K 0x0000000E +#define PIWAR_IWS_64K 0x0000000F +#define PIWAR_IWS_128K 0x00000010 +#define PIWAR_IWS_256K 0x00000011 +#define PIWAR_IWS_512K 0x00000012 +#define PIWAR_IWS_1M 0x00000013 +#define PIWAR_IWS_2M 0x00000014 +#define PIWAR_IWS_4M 0x00000015 +#define PIWAR_IWS_8M 0x00000016 +#define PIWAR_IWS_16M 0x00000017 +#define PIWAR_IWS_32M 0x00000018 +#define PIWAR_IWS_64M 0x00000019 +#define PIWAR_IWS_128M 0x0000001A +#define PIWAR_IWS_256M 0x0000001B +#define PIWAR_IWS_512M 0x0000001C +#define PIWAR_IWS_1G 0x0000001D +#define PIWAR_IWS_2G 0x0000001E +} pcictrl8349_t; /* * USB */ -typedef struct usb83xx { - u8 fixme[0x1000]; -} usb83xx_t; +typedef struct usb8349 { + u8 fixme[0x2000]; +} usb8349_t; /* * TSEC */ -typedef struct tsec83xx { +typedef struct tsec8349 { u8 fixme[0x1000]; -} tsec83xx_t; +} tsec8349_t; /* * Security */ -typedef struct security83xx { +typedef struct security8349 { u8 fixme[0x10000]; -} security83xx_t; +} security8349_t; -/* - * PCI Express - */ -typedef struct pex83xx { - u8 fixme[0x1000]; -} pex83xx_t; - -/* - * SATA - */ -typedef struct sata83xx { - u8 fixme[0x1000]; -} sata83xx_t; - -/* - * eSDHC - */ -typedef struct sdhc83xx { - u8 fixme[0x1000]; -} sdhc83xx_t; - -/* - * SerDes - */ -typedef struct serdes83xx { - u8 fixme[0x100]; -} serdes83xx_t; - -/* - * On Chip ROM - */ -typedef struct rom83xx { - u8 mem[0x10000]; -} rom83xx_t; - -/* - * TDM - */ -typedef struct tdm83xx { - u8 fixme[0x200]; -} tdm83xx_t; - -/* - * TDM DMAC - */ -typedef struct tdmdmac83xx { - u8 fixme[0x2000]; -} tdmdmac83xx_t; - -#if defined(CONFIG_MPC834X) typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[2]; /* General purpose I/O module */ - u8 res0[0x200]; - u8 dll_ddr[0x100]; - u8 dll_lbc[0x100]; - u8 res1[0xE00]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res2[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res3[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ - u8 res4[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ - u8 res5[0x19900]; - usb83xx_t usb[2]; - tsec83xx_t tsec[2]; - u8 res6[0xA000]; - security83xx_t security; - u8 res7[0xC0000]; + sysconf8349_t sysconf; /* System configuration */ + wdt8349_t wdt; /* Watch Dog Timer (WDT) Registers */ + rtclk8349_t rtc; /* Real Time Clock Module Registers */ + rtclk8349_t pit; /* Periodic Interval Timer */ + gtm8349_t gtm[2]; /* Global Timers Module */ + ipic8349_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter8349_t arbiter; /* System Arbiter Registers */ + reset8349_t reset; /* Reset Module */ + clk8349_t clk; /* System Clock Module */ + pmc8349_t pmc; /* Power Management Control Module */ + gpio8349_t pgio[2]; /* general purpose I/O module */ + u8 res0[0x200]; + u8 DDL_DDR[0x100]; + u8 DDL_LBIU[0x100]; + u8 res1[0xE00]; + ddr8349_t ddr; /* DDR Memory Controller Memory */ + i2c_t i2c[2]; /* I2C1 Controller */ + u8 res2[0x1300]; + duart8349_t duart[2];/* DUART */ + u8 res3[0x900]; + lbus8349_t lbus; /* Local Bus Controller Registers */ + u8 res4[0x1000]; + spi8349_t spi; /* Serial Peripheral Interface */ + u8 res5[0xF00]; + dma8349_t dma; /* DMA */ + pciconf8349_t pci_conf[2]; /* PCI Software Configuration Registers */ + ios8349_t ios; /* Sequencer */ + pcictrl8349_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ + u8 res6[0x19900]; + usb8349_t usb; + tsec8349_t tsec[2]; + u8 res7[0xA000]; + security8349_t security; } immap_t; -#elif defined(CONFIG_MPC8313) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[1]; /* General purpose I/O module */ - u8 res0[0x1300]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res1[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res2[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ - u8 res3[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res4[0x80]; - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res5[0x1aa00]; - usb83xx_t usb[1]; - tsec83xx_t tsec[2]; - u8 res6[0xA000]; - security83xx_t security; - u8 res7[0xC0000]; -} immap_t; - -#elif defined(CONFIG_MPC8315) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[1]; /* General purpose I/O module */ - u8 res0[0x1300]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res1[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res2[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ - u8 res3[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res4[0x80]; - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res5[0xa00]; - pex83xx_t pciexp[2]; /* PCI Express Controller */ - u8 res6[0xb000]; - tdm83xx_t tdm; /* TDM Controller */ - u8 res7[0x1e00]; - sata83xx_t sata[2]; /* SATA Controller */ - u8 res8[0x9000]; - usb83xx_t usb[1]; /* USB DR Controller */ - tsec83xx_t tsec[2]; - u8 res9[0x6000]; - tdmdmac83xx_t tdmdmac; /* TDM DMAC */ - u8 res10[0x2000]; - security83xx_t security; - u8 res11[0xA3000]; - serdes83xx_t serdes[1]; /* SerDes Registers */ - u8 res12[0x1CF00]; -} immap_t; - -#elif defined(CONFIG_MPC837X) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - gpio83xx_t gpio[2]; /* General purpose I/O module */ - u8 res0[0x1200]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res1[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res2[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ - u8 res3[0x1000]; - spi8xxx_t spi; /* Serial Peripheral Interface */ - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res4[0x80]; - ios83xx_t ios; /* Sequencer */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res5[0xa00]; - pex83xx_t pciexp[2]; /* PCI Express Controller */ - u8 res6[0xd000]; - sata83xx_t sata[4]; /* SATA Controller */ - u8 res7[0x7000]; - usb83xx_t usb[1]; /* USB DR Controller */ - tsec83xx_t tsec[2]; - u8 res8[0x8000]; - sdhc83xx_t sdhc; /* SDHC Controller */ - u8 res9[0x1000]; - security83xx_t security; - u8 res10[0xA3000]; - serdes83xx_t serdes[2]; /* SerDes Registers */ - u8 res11[0xCE00]; - rom83xx_t rom; /* On Chip ROM */ -} immap_t; - -#elif defined(CONFIG_MPC8360) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - u8 res0[0x200]; - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - qepi83xx_t qepi; /* QE Ports Interrupts Registers */ - u8 res1[0x300]; - u8 dll_ddr[0x100]; - u8 dll_lbc[0x100]; - u8 res2[0x200]; - qepio83xx_t qepio; /* QE Parallel I/O ports */ - qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ - u8 res3[0x400]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res4[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res5[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ - u8 res6[0x2000]; - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res7[128]; - ios83xx_t ios; /* Sequencer (IOS) */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res8[0x4A00]; - ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ - u8 res9[0x22000]; - security83xx_t security; - u8 res10[0xC0000]; - u8 qe[0x100000]; /* QE block */ -} immap_t; - -#elif defined(CONFIG_MPC832X) -typedef struct immap { - sysconf83xx_t sysconf; /* System configuration */ - wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ - rtclk83xx_t rtc; /* Real Time Clock Module Registers */ - rtclk83xx_t pit; /* Periodic Interval Timer */ - gtm83xx_t gtm[2]; /* Global Timers Module */ - ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ - arbiter83xx_t arbiter; /* System Arbiter Registers */ - reset83xx_t reset; /* Reset Module */ - clk83xx_t clk; /* System Clock Module */ - pmc83xx_t pmc; /* Power Management Control Module */ - qepi83xx_t qepi; /* QE Ports Interrupts Registers */ - u8 res0[0x300]; - u8 dll_ddr[0x100]; - u8 dll_lbc[0x100]; - u8 res1[0x200]; - qepio83xx_t qepio; /* QE Parallel I/O ports */ - u8 res2[0x800]; - ddr83xx_t ddr; /* DDR Memory Controller Memory */ - fsl_i2c_t i2c[2]; /* I2C Controllers */ - u8 res3[0x1300]; - duart83xx_t duart[2]; /* DUART */ - u8 res4[0x900]; - lbus83xx_t lbus; /* Local Bus Controller Registers */ - u8 res5[0x2000]; - dma83xx_t dma; /* DMA */ - pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ - u8 res6[128]; - ios83xx_t ios; /* Sequencer (IOS) */ - pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ - u8 res7[0x27A00]; - security83xx_t security; - u8 res8[0xC0000]; - u8 qe[0x100000]; /* QE block */ -} immap_t; -#endif - -#endif /* __IMMAP_83xx__ */ +#endif /* __IMMAP_8349__ */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 113ba482d..2f10e9591 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1,8 +1,6 @@ /* * MPC85xx Internal Memory Map * - * Copyright 2007 Freescale Semiconductor. - * * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) * @@ -11,9 +9,6 @@ #ifndef __IMMAP_85xx__ #define __IMMAP_85xx__ -#include -#include - /* * Local-Access Registers and ECM Registers(0x0000-0x2000) */ @@ -57,7 +52,7 @@ typedef struct ccsr_local_ecm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */ + char res20[780]; uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ char res21[12]; uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ @@ -86,13 +81,8 @@ typedef struct ccsr_ddr { uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ - char res4a[48]; - uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */ - uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */ - uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ - uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ - char res5[48]; - uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ + char res5[112]; + uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ @@ -106,19 +96,9 @@ typedef struct ccsr_ddr { char res6[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ char res7[20]; - uint init_addr; /* 0x2148 - DDR training initialization address */ - uint init_ext_addr; /* 0x214C - DDR training initialization extended address */ - char res8_1[16]; - uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ - uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ - char reg8_1a[8]; - uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/ - uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/ - uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/ - uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ - uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ - uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ - char res8_1b[2672]; + uint init_address; /* 0x2148 - DDR training initialization address */ + uint init_ext_address; /* 0x214C - DDR training initialization extended address */ + char res8_1[2728]; uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ char res8_2[512]; @@ -149,8 +129,37 @@ typedef struct ccsr_ddr { * I2C Registers(0x3000-0x4000) */ typedef struct ccsr_i2c { - struct fsl_i2c i2c[1]; - u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; + u_char i2cadr; /* 0x3000 - I2C Address Register */ +#define MPC85xx_I2CADR_MASK 0xFE + char res1[3]; + u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */ +#define MPC85xx_I2CFDR_MASK 0x3F + char res2[3]; + u_char i2ccr; /* 0x3008 - I2C Control Register */ +#define MPC85xx_I2CCR_MEN 0x80 +#define MPC85xx_I2CCR_MIEN 0x40 +#define MPC85xx_I2CCR_MSTA 0x20 +#define MPC85xx_I2CCR_MTX 0x10 +#define MPC85xx_I2CCR_TXAK 0x08 +#define MPC85xx_I2CCR_RSTA 0x04 +#define MPC85xx_I2CCR_BCST 0x01 + char res3[3]; + u_char i2csr; /* 0x300c - I2C Status Register */ +#define MPC85xx_I2CSR_MCF 0x80 +#define MPC85xx_I2CSR_MAAS 0x40 +#define MPC85xx_I2CSR_MBB 0x20 +#define MPC85xx_I2CSR_MAL 0x10 +#define MPC85xx_I2CSR_BCSTM 0x08 +#define MPC85xx_I2CSR_SRW 0x04 +#define MPC85xx_I2CSR_MIF 0x02 +#define MPC85xx_I2CSR_RXAK 0x01 + char res4[3]; + u_char i2cdr; /* 0x3010 - I2C Data Register */ +#define MPC85xx_I2CDR_DATA 0xFF + char res5[3]; + u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */ +#define MPC85xx_I2CDFSRR 0x3F + char res6[4075]; } ccsr_i2c_t; #if defined(CONFIG_MPC8540) \ @@ -232,11 +241,12 @@ typedef struct ccsr_lbc { char res7[12]; uint lbcr; /* 0x50d0 - LBC Configuration Register */ uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ - char res8[3880]; + char res8[12072]; } ccsr_lbc_t; /* * PCI Registers(0x8000-0x9000) + * Omitting Reserved(0x9000-0x2_0000) */ typedef struct ccsr_pcix { uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ @@ -299,27 +309,9 @@ typedef struct ccsr_pcix { uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ - uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */ - char res11[476]; + char res11[94688]; } ccsr_pcix_t; -#define PCIX_COMMAND 0x62 -#define POWAR_EN 0x80000000 -#define POWAR_IO_READ 0x00080000 -#define POWAR_MEM_READ 0x00040000 -#define POWAR_IO_WRITE 0x00008000 -#define POWAR_MEM_WRITE 0x00004000 -#define POWAR_MEM_512M 0x0000001c -#define POWAR_IO_1M 0x00000013 - -#define PIWAR_EN 0x80000000 -#define PIWAR_PF 0x20000000 -#define PIWAR_LOCAL 0x00f00000 -#define PIWAR_READ_SNOOP 0x00050000 -#define PIWAR_WRITE_SNOOP 0x00005000 -#define PIWAR_MEM_2G 0x0000001e - - /* * L2 Cache Registers(0x2_0000-0x2_1000) */ @@ -735,10 +727,11 @@ typedef struct ccsr_tsec { } ccsr_tsec_t; /* - * PIC Registers(0x4_0000-0x8_0000) + * PIC Registers(0x2_6000-0x4_0000-0x8_0000) */ typedef struct ccsr_pic { - char res1[64]; /* 0x40000 */ + char res0[106496]; /* 0x26000-0x40000 */ + char res1[64]; uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ char res2[12]; uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ @@ -1054,7 +1047,7 @@ typedef struct ccsr_cpm { * 0x9000-0x90bff: General SIU */ typedef struct ccsr_cpm_siu { - char res1[80]; + char res1[80]; uint smaer; uint smser; uint smevr; @@ -1143,9 +1136,9 @@ typedef struct ccsr_cpm_timer { /* 0x91018-0x912ff: SDMA */ typedef struct ccsr_cpm_sdma { uchar sdsr; - char res1[3]; - uchar sdmr; - char res2[739]; + char res1[3]; + uchar sdmr; + char res2[739]; } ccsr_cpm_sdma_t; /* 0x91300-0x9131f: FCC1 */ @@ -1228,7 +1221,7 @@ typedef struct ccsr_cpm_fcc3_ext { /* 0x91400-0x915ef: TC layers */ typedef struct ccsr_cpm_tmp1 { - char res[496]; + char res[496]; } ccsr_cpm_tmp1_t; /* 0x915f0-0x9185f: BRGs:5,6,7,8 */ @@ -1296,7 +1289,7 @@ typedef struct ccsr_cpm_scc { /* 0x91a80-0x91a9f */ typedef struct ccsr_cpm_tmp2 { - char res[32]; + char res[32]; } ccsr_cpm_tmp2_t; /* 0x91aa0-0x91aff: SPI */ @@ -1338,16 +1331,16 @@ typedef struct ccsr_cpm { /* Some references are into the unique and known dpram spaces, * others are from the generic base. */ -#define im_dprambase im_dpram1 - u_char im_dpram1[16*1024]; - char res1[16*1024]; - u_char im_dpram2[16*1024]; - char res2[16*1024]; - ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ - ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ - ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ - ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ - ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ +#define im_dprambase im_dpram1 + u_char im_dpram1[16*1024]; + char res1[16*1024]; + u_char im_dpram2[16*1024]; + char res2[16*1024]; + ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ + ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ + ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ + ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ + ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ ccsr_cpm_fcc1_t im_cpm_fcc1; ccsr_cpm_fcc2_t im_cpm_fcc2; ccsr_cpm_fcc3_t im_cpm_fcc3; @@ -1536,43 +1529,16 @@ typedef struct ccsr_rio { char res58[60176]; } ccsr_rio_t; -/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */ -typedef struct par_io { - uint cpodr; /* 0x100 */ - uint cpdat; /* 0x104 */ - uint cpdir1; /* 0x108 */ - uint cpdir2; /* 0x10c */ - uint cppar1; /* 0x110 */ - uint cppar2; /* 0x114 */ - char res[8]; -}par_io_t; - /* * Global Utilities Register Block(0xe_0000-0xf_ffff) */ typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ uint porbmsr; /* 0xe0004 - POR boot mode status register */ -#define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ -#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 -#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 -#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 -#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 -#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 -#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 -#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 -#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 -#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 -#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 -#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 -#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 -#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ - uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ -#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020 - char res1[8]; + char res1[12]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ char res2[12]; uint gpiocr; /* 0xe0030 - GPIO control register */ @@ -1584,29 +1550,6 @@ typedef struct ccsr_gur { uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ -#define MPC85xx_DEVDISR_PCI1 0x80000000 -#define MPC85xx_DEVDISR_PCI2 0x40000000 -#define MPC85xx_DEVDISR_PCIE 0x20000000 -#define MPC85xx_DEVDISR_LBC 0x08000000 -#define MPC85xx_DEVDISR_PCIE2 0x04000000 -#define MPC85xx_DEVDISR_PCIE3 0x02000000 -#define MPC85xx_DEVDISR_SEC 0x01000000 -#define MPC85xx_DEVDISR_SRIO 0x00080000 -#define MPC85xx_DEVDISR_RMSG 0x00040000 -#define MPC85xx_DEVDISR_DDR 0x00010000 -#define MPC85xx_DEVDISR_CPU 0x00008000 -#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU -#define MPC85xx_DEVDISR_TB 0x00004000 -#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB -#define MPC85xx_DEVDISR_CPU1 0x00002000 -#define MPC85xx_DEVDISR_TB1 0x00001000 -#define MPC85xx_DEVDISR_DMA 0x00000400 -#define MPC85xx_DEVDISR_TSEC1 0x00000080 -#define MPC85xx_DEVDISR_TSEC2 0x00000040 -#define MPC85xx_DEVDISR_TSEC3 0x00000020 -#define MPC85xx_DEVDISR_TSEC4 0x00000010 -#define MPC85xx_DEVDISR_I2C 0x00000004 -#define MPC85xx_DEVDISR_DUART 0x00000002 char res7[12]; uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; @@ -1614,15 +1557,7 @@ typedef struct ccsr_gur { char res9[12]; uint pvr; /* 0xe00a0 - Processor version register */ uint svr; /* 0xe00a4 - System version register */ - char res10a[8]; - uint rstcr; /* 0xe00b0 - Reset control register */ -#ifdef CONFIG_MPC8568 - char res10b[76]; - par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */ - char res10c[3136]; -#else - char res10b[3404]; -#endif + char res10[3416]; uint clkocr; /* 0xe0e00 - Clock out select register */ char res11[12]; uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ @@ -1634,32 +1569,26 @@ typedef struct ccsr_gur { uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */ uint res14; /* 0xe0f28 */ uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ - char res15[61648]; /* 0xe0f30 to 0xefffff */ + char res15[61651]; } ccsr_gur_t; -#define PORDEVSR_PCI (0x00800000) /* PCI Mode */ +typedef struct immap { + ccsr_local_ecm_t im_local_ecm; + ccsr_ddr_t im_ddr; + ccsr_i2c_t im_i2c; + ccsr_duart_t im_duart; + ccsr_lbc_t im_lbc; + ccsr_pcix_t im_pcix; + ccsr_l2cache_t im_l2cache; + ccsr_dma_t im_dma; + ccsr_tsec_t im_tsec1; + ccsr_tsec_t im_tsec2; + ccsr_pic_t im_pic; + ccsr_cpm_t im_cpm; + ccsr_rio_t im_rio; + ccsr_gur_t im_gur; +} immap_t; -#define CFG_MPC85xx_GUTS_OFFSET (0xE0000) -#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET) -#define CFG_MPC85xx_ECM_OFFSET (0x0000) -#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET) -#define CFG_MPC85xx_DDR_OFFSET (0x2000) -#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET) -#define CFG_MPC85xx_DDR2_OFFSET (0x6000) -#define CFG_MPC85xx_DDR2_ADDR (CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET) -#define CFG_MPC85xx_LBC_OFFSET (0x5000) -#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET) -#define CFG_MPC85xx_PCIX_OFFSET (0x8000) -#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET) -#define CFG_MPC85xx_PCIX2_OFFSET (0x9000) -#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET) -#define CFG_MPC85xx_L2_OFFSET (0x20000) -#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET) -#define CFG_MPC85xx_DMA_OFFSET (0x21000) -#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET) -#define CFG_MPC85xx_PIC_OFFSET (0x40000) -#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET) -#define CFG_MPC85xx_CPM_OFFSET (0x80000) -#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET) +extern immap_t *immr; #endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index c3496818f..8e5fe113c 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -13,9 +13,6 @@ #define SIO_CONFIG_RA 0x398 #define SIO_CONFIG_RD 0x399 -#ifndef _IO_BASE -#define _IO_BASE 0 -#endif #define readb(addr) in_8((volatile u8 *)(addr)) #define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) @@ -98,20 +95,8 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl); * Acts as a barrier to ensure all previous I/O accesses have * completed before any further ones are issued. */ -static inline void eieio(void) -{ - __asm__ __volatile__ ("eieio" : : : "memory"); -} - -static inline void sync(void) -{ - __asm__ __volatile__ ("sync" : : : "memory"); -} - -static inline void isync(void) -{ - __asm__ __volatile__ ("isync" : : : "memory"); -} +#define eieio() __asm__ __volatile__ ("eieio" : : : "memory"); +#define sync() __asm__ __volatile__ ("sync" : : : "memory"); /* Enforce in-order execution of data I/O. * No distinction between read/write on PPC; use eieio for all three. @@ -120,182 +105,76 @@ static inline void isync(void) #define iobarrier_r() eieio() #define iobarrier_w() eieio() -/* - * Non ordered and non-swapping "raw" accessors - */ -#define __iomem -#define PCI_FIX_ADDR(addr) (addr) - -static inline unsigned char __raw_readb(const volatile void __iomem *addr) -{ - return *(volatile unsigned char *)PCI_FIX_ADDR(addr); -} -static inline unsigned short __raw_readw(const volatile void __iomem *addr) -{ - return *(volatile unsigned short *)PCI_FIX_ADDR(addr); -} -static inline unsigned int __raw_readl(const volatile void __iomem *addr) -{ - return *(volatile unsigned int *)PCI_FIX_ADDR(addr); -} -static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) -{ - *(volatile unsigned char *)PCI_FIX_ADDR(addr) = v; -} -static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) -{ - *(volatile unsigned short *)PCI_FIX_ADDR(addr) = v; -} -static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) -{ - *(volatile unsigned int *)PCI_FIX_ADDR(addr) = v; -} - /* * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. - * - * Read operations have additional twi & isync to make sure the read - * is actually performed (i.e. the data has come back) before we start - * executing any following instructions. */ -extern inline int in_8(const volatile unsigned char __iomem *addr) +extern inline int in_8(volatile u8 *addr) { - int ret; + int ret; - __asm__ __volatile__( - "sync; lbz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; } -extern inline void out_8(volatile unsigned char __iomem *addr, int val) +extern inline void out_8(volatile u8 *addr, int val) { - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); } -extern inline int in_le16(const volatile unsigned short __iomem *addr) +extern inline int in_le16(volatile u16 *addr) { - int ret; + int ret; - __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; + __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; } -extern inline int in_be16(const volatile unsigned short __iomem *addr) +extern inline int in_be16(volatile u16 *addr) { - int ret; + int ret; - __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; } -extern inline void out_le16(volatile unsigned short __iomem *addr, int val) +extern inline void out_le16(volatile u16 *addr, int val) { - __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); + __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); } -extern inline void out_be16(volatile unsigned short __iomem *addr, int val) +extern inline void out_be16(volatile u16 *addr, int val) { - __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); } -extern inline unsigned in_le32(const volatile unsigned __iomem *addr) +extern inline unsigned in_le32(volatile u32 *addr) { - unsigned ret; + unsigned ret; - __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; + __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; } -extern inline unsigned in_be32(const volatile unsigned __iomem *addr) +extern inline unsigned in_be32(volatile u32 *addr) { - unsigned ret; + unsigned ret; - __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); + return ret; } -extern inline void out_le32(volatile unsigned __iomem *addr, int val) +extern inline void out_le32(volatile unsigned *addr, int val) { - __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); + __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : + "r" (val), "r" (addr)); } -extern inline void out_be32(volatile unsigned __iomem *addr, int val) +extern inline void out_be32(volatile unsigned *addr, int val) { - __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); -} - -/* Clear and set bits in one shot. These macros can be used to clear and - * set multiple bits in a register using a single call. These macros can - * also be used to set a multiple-bit bit pattern using a mask, by - * specifying the mask in the 'clear' parameter and the new bit pattern - * in the 'set' parameter. - */ - -#define clrbits(type, addr, clear) \ - out_##type((addr), in_##type(addr) & ~(clear)) - -#define setbits(type, addr, set) \ - out_##type((addr), in_##type(addr) | (set)) - -#define clrsetbits(type, addr, clear, set) \ - out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) - -#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) -#define setbits_be32(addr, set) setbits(be32, addr, set) -#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) - -#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) -#define setbits_le32(addr, set) setbits(le32, addr, set) -#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) - -#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) -#define setbits_be16(addr, set) setbits(be16, addr, set) -#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) - -#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) -#define setbits_le16(addr, set) setbits(le16, addr, set) -#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) - -#define clrbits_8(addr, clear) clrbits(8, addr, clear) -#define setbits_8(addr, set) setbits(8, addr, set) -#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)((unsigned long)paddr); -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - + __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); } #endif diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h index daddb554d..f854df633 100644 --- a/include/asm-ppc/iopin_85xx.h +++ b/include/asm-ppc/iopin_85xx.h @@ -23,121 +23,121 @@ typedef struct { extern __inline__ void iopin_set_high (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; datp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_low (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_high (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_low (iopin_t * iopin) { - volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata; + volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata; return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_out (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; dirp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_in (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_out (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_in (iopin_t * iopin) { - volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira; + volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira; return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_odr (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; odrp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_act (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_odr (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_act (iopin_t * iopin) { - volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra; + volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra; return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_ded (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; parp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_gen (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_ded (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_gen (iopin_t * iopin) { - volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara; + volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara; return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } extern __inline__ void iopin_set_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; sorp[iopin->port * 8] |= (1 << (31 - iopin->pin)); } extern __inline__ void iopin_set_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin)); } extern __inline__ uint iopin_is_opt2 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1; } extern __inline__ uint iopin_is_opt1 (iopin_t * iopin) { - volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora; + volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora; return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1; } diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 050a7b647..baaf6f797 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -117,8 +117,8 @@ typedef struct _P601_BAT { */ typedef struct _pte { - unsigned long page_num:20; - unsigned long flags:12; /* Page flags (some unused bits) */ + unsigned long page_num:20; + unsigned long flags:12; /* Page flags (some unused bits) */ } pte; #define PD_SHIFT (10+12) /* Page directory */ @@ -140,16 +140,11 @@ extern void _tlbia(void); /* invalidate all TLB entries */ typedef enum { IBAT0 = 0, IBAT1, IBAT2, IBAT3, - DBAT0, DBAT1, DBAT2, DBAT3, -#ifdef CONFIG_HIGH_BATS - IBAT4, IBAT5, IBAT6, IBAT7, - DBAT4, DBAT5, DBAT6, DBAT7 -#endif + DBAT0, DBAT1, DBAT2, DBAT3 } ppc_bat_t; extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); -extern void print_bats(void); #endif /* __ASSEMBLY__ */ @@ -340,71 +335,91 @@ extern void print_bats(void); * instructions. */ +#define TLB_LO 1 +#define TLB_HI 0 + +#define TLB_DATA TLB_LO +#define TLB_TAG TLB_HI + +/* Tag portion */ + +#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ +#define TLB_PAGESZ_MASK 0x00000380 +#define TLB_PAGESZ(x) (((x) & 0x7) << 7) +#define PAGESZ_1K 0 +#define PAGESZ_4K 1 +#define PAGESZ_16K 2 +#define PAGESZ_64K 3 +#define PAGESZ_256K 4 +#define PAGESZ_1M 5 +#define PAGESZ_4M 6 +#define PAGESZ_16M 7 +#define TLB_VALID 0x00000040 /* Entry is valid */ + +/* Data portion */ + +#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ +#define TLB_PERM_MASK 0x00000300 +#define TLB_EX 0x00000200 /* Instruction execution allowed */ +#define TLB_WR 0x00000100 /* Writes permitted */ +#define TLB_ZSEL_MASK 0x000000F0 +#define TLB_ZSEL(x) (((x) & 0xF) << 4) +#define TLB_ATTR_MASK 0x0000000F +#define TLB_W 0x00000008 /* Caching is write-through */ +#define TLB_I 0x00000004 /* Caching is inhibited */ +#define TLB_M 0x00000002 /* Memory is coherent */ +#define TLB_G 0x00000001 /* Memory is guarded from prefetch */ + /* - * FSL Book-E support + * e500 support */ -#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) -#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) -#define MAS0_NV(x) ((x) & 0x00000FFF) +#define MAS0_TLBSEL 0x10000000 +#define MAS0_ESEL 0x000F0000 +#define MAS0_NV 0x00000001 -#define MAS1_VALID 0x80000000 -#define MAS1_IPROT 0x40000000 -#define MAS1_TID(x) ((x << 16) & 0x3FFF0000) -#define MAS1_TS 0x00001000 -#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00) +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 +#define MAS1_TID 0x00FF0000 +#define MAS1_TS 0x00001000 +#define MAS1_TSIZE 0x00000F00 -#define MAS2_EPN 0xFFFFF000 -#define MAS2_X0 0x00000040 -#define MAS2_X1 0x00000020 -#define MAS2_W 0x00000010 -#define MAS2_I 0x00000008 -#define MAS2_M 0x00000004 -#define MAS2_G 0x00000002 -#define MAS2_E 0x00000001 +#define MAS2_EPN 0xFFFFF000 +#define MAS2_SHAREN 0x00000200 +#define MAS2_X0 0x00000040 +#define MAS2_X1 0x00000020 +#define MAS2_W 0x00000010 +#define MAS2_I 0x00000008 +#define MAS2_M 0x00000004 +#define MAS2_G 0x00000002 +#define MAS2_E 0x00000001 -#define MAS3_RPN 0xFFFFF000 -#define MAS3_U0 0x00000200 -#define MAS3_U1 0x00000100 -#define MAS3_U2 0x00000080 -#define MAS3_U3 0x00000040 -#define MAS3_UX 0x00000020 -#define MAS3_SX 0x00000010 -#define MAS3_UW 0x00000008 -#define MAS3_SW 0x00000004 -#define MAS3_UR 0x00000002 -#define MAS3_SR 0x00000001 +#define MAS3_RPN 0xFFFFF000 +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 -#define MAS4_TLBSELD(x) MAS0_TLBSEL(x) -#define MAS4_TIDDSEL 0x000F0000 -#define MAS4_TSIZED(x) MAS1_TSIZE(x) -#define MAS4_X0D 0x00000040 -#define MAS4_X1D 0x00000020 -#define MAS4_WD 0x00000010 -#define MAS4_ID 0x00000008 -#define MAS4_MD 0x00000004 -#define MAS4_GD 0x00000002 -#define MAS4_ED 0x00000001 +#define MAS4_TLBSELD 0x10000000 +#define MAS4_TIDDSEL 0x00030000 +#define MAS4_DSHAREN 0x00001000 +#define MAS4_TSIZED(x) (x << 8) +#define MAS4_X0D 0x00000040 +#define MAS4_X1D 0x00000020 +#define MAS4_WD 0x00000010 +#define MAS4_ID 0x00000008 +#define MAS4_MD 0x00000004 +#define MAS4_GD 0x00000002 +#define MAS4_ED 0x00000001 -#define MAS6_SPID0 0x3FFF0000 -#define MAS6_SPID1 0x00007FFE -#define MAS6_SAS 0x00000001 -#define MAS6_SPID MAS6_SPID0 - -#define MAS7_RPN 0xFFFFFFFF - -#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \ - (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv)) -#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \ - ((((v) << 31) & MAS1_VALID) |\ - (((iprot) << 30) & MAS1_IPROT) |\ - (MAS1_TID(tid)) |\ - (((ts) << 12) & MAS1_TS) |\ - (MAS1_TSIZE(tsize))) -#define FSL_BOOKE_MAS2(epn, wimge) \ - (((epn) & MAS3_RPN) | (wimge)) -#define FSL_BOOKE_MAS3(rpn, user, perms) \ - (((rpn) & MAS3_RPN) | (user) | (perms)) +#define MAS6_SPID 0x00FF0000 +#define MAS6_SAS 0x00000001 #define BOOKE_PAGESZ_1K 0 #define BOOKE_PAGESZ_4K 1 @@ -416,67 +431,22 @@ extern void print_bats(void); #define BOOKE_PAGESZ_16M 7 #define BOOKE_PAGESZ_64M 8 #define BOOKE_PAGESZ_256M 9 -#define BOOKE_PAGESZ_1G 10 -#define BOOKE_PAGESZ_4G 11 -#define BOOKE_PAGESZ_16GB 12 -#define BOOKE_PAGESZ_64GB 13 -#define BOOKE_PAGESZ_256GB 14 -#define BOOKE_PAGESZ_1TB 15 +#define BOOKE_PAGESZ_1GB 10 +#define BOOKE_PAGESZ_4GB 11 -#ifdef CONFIG_E500 -#ifndef __ASSEMBLY__ -extern void set_tlb(u8 tlb, u32 epn, u64 rpn, - u8 perms, u8 wimge, - u8 ts, u8 esel, u8 tsize, u8 iprot); -extern void disable_tlb(u8 esel); -extern void invalidate_tlb(u8 tlb); -extern void init_tlbs(void); - -#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ - { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \ - .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot } - -struct fsl_e_tlb_entry { - u8 tlb; - u32 epn; - u64 rpn; - u8 perms; - u8 wimge; - u8 ts; - u8 esel; - u8 tsize; - u8 iprot; -}; - -extern struct fsl_e_tlb_entry tlb_table[]; -extern int num_tlb_entries; -#endif -#endif - -#if defined(CONFIG_MPC86xx) -#define LAWBAR_BASE_ADDR 0x00FFFFFF -#define LAWAR_TRGT_IF 0x01F00000 -#else #define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_TRGT_IF 0x00F00000 -#endif #define LAWAR_EN 0x80000000 +#define LAWAR_TRGT_IF 0x00F00000 #define LAWAR_SIZE 0x0000003F #define LAWAR_TRGT_IF_PCI 0x00000000 #define LAWAR_TRGT_IF_PCI1 0x00000000 #define LAWAR_TRGT_IF_PCIX 0x00000000 #define LAWAR_TRGT_IF_PCI2 0x00100000 -#define LAWAR_TRGT_IF_PCIE1 0x00200000 -#define LAWAR_TRGT_IF_PCIE2 0x00100000 -#define LAWAR_TRGT_IF_PCIE3 0x00300000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 -#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_RIO 0x00c00000 #define LAWAR_TRGT_IF_DDR 0x00f00000 -#define LAWAR_TRGT_IF_DDR1 0x00f00000 -#define LAWAR_TRGT_IF_DDR2 0x01600000 #define LAWAR_SIZE_BASE 0xa #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) @@ -499,167 +469,8 @@ extern int num_tlb_entries; #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) -#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) -#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) -#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) -#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) - -#ifdef CONFIG_440 -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID )) -#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn)) -#define TLB2(a) ((a) & 0x00000fbf) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ;\ -0: mflr r0 ;\ - mtlr r1 ;\ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - -/*----------------------------------------------------------------------------+ -| TLB specific defines. -+----------------------------------------------------------------------------*/ -#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL -#define TLB_16MB_ALIGN_MASK 0xFFF000000ULL -#define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL -#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL -#define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL -#define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL -#define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL -#define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL -#define TLB_256MB_SIZE 0x10000000 -#define TLB_16MB_SIZE 0x01000000 -#define TLB_1MB_SIZE 0x00100000 -#define TLB_256KB_SIZE 0x00040000 -#define TLB_64KB_SIZE 0x00010000 -#define TLB_16KB_SIZE 0x00004000 -#define TLB_4KB_SIZE 0x00001000 -#define TLB_1KB_SIZE 0x00000400 - -#define TLB_WORD0_EPN_MASK 0xFFFFFC00 -#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD0_V_MASK 0x00000200 -#define TLB_WORD0_V_ENABLE 0x00000200 -#define TLB_WORD0_V_DISABLE 0x00000000 -#define TLB_WORD0_TS_MASK 0x00000100 -#define TLB_WORD0_TS_1 0x00000100 -#define TLB_WORD0_TS_0 0x00000000 -#define TLB_WORD0_SIZE_MASK 0x000000F0 -#define TLB_WORD0_SIZE_1KB 0x00000000 -#define TLB_WORD0_SIZE_4KB 0x00000010 -#define TLB_WORD0_SIZE_16KB 0x00000020 -#define TLB_WORD0_SIZE_64KB 0x00000030 -#define TLB_WORD0_SIZE_256KB 0x00000040 -#define TLB_WORD0_SIZE_1MB 0x00000050 -#define TLB_WORD0_SIZE_16MB 0x00000070 -#define TLB_WORD0_SIZE_256MB 0x00000090 -#define TLB_WORD0_TPAR_MASK 0x0000000F -#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) -#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) - -#define TLB_WORD1_RPN_MASK 0xFFFFFC00 -#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00) -#define TLB_WORD1_PAR1_MASK 0x00000300 -#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) -#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03) -#define TLB_WORD1_PAR1_0 0x00000000 -#define TLB_WORD1_PAR1_1 0x00000100 -#define TLB_WORD1_PAR1_2 0x00000200 -#define TLB_WORD1_PAR1_3 0x00000300 -#define TLB_WORD1_ERPN_MASK 0x0000000F -#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0) -#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F) - -#define TLB_WORD2_PAR2_MASK 0xC0000000 -#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30) -#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03) -#define TLB_WORD2_PAR2_0 0x00000000 -#define TLB_WORD2_PAR2_1 0x40000000 -#define TLB_WORD2_PAR2_2 0x80000000 -#define TLB_WORD2_PAR2_3 0xC0000000 -#define TLB_WORD2_U0_MASK 0x00008000 -#define TLB_WORD2_U0_ENABLE 0x00008000 -#define TLB_WORD2_U0_DISABLE 0x00000000 -#define TLB_WORD2_U1_MASK 0x00004000 -#define TLB_WORD2_U1_ENABLE 0x00004000 -#define TLB_WORD2_U1_DISABLE 0x00000000 -#define TLB_WORD2_U2_MASK 0x00002000 -#define TLB_WORD2_U2_ENABLE 0x00002000 -#define TLB_WORD2_U2_DISABLE 0x00000000 -#define TLB_WORD2_U3_MASK 0x00001000 -#define TLB_WORD2_U3_ENABLE 0x00001000 -#define TLB_WORD2_U3_DISABLE 0x00000000 -#define TLB_WORD2_W_MASK 0x00000800 -#define TLB_WORD2_W_ENABLE 0x00000800 -#define TLB_WORD2_W_DISABLE 0x00000000 -#define TLB_WORD2_I_MASK 0x00000400 -#define TLB_WORD2_I_ENABLE 0x00000400 -#define TLB_WORD2_I_DISABLE 0x00000000 -#define TLB_WORD2_M_MASK 0x00000200 -#define TLB_WORD2_M_ENABLE 0x00000200 -#define TLB_WORD2_M_DISABLE 0x00000000 -#define TLB_WORD2_G_MASK 0x00000100 -#define TLB_WORD2_G_ENABLE 0x00000100 -#define TLB_WORD2_G_DISABLE 0x00000000 -#define TLB_WORD2_E_MASK 0x00000080 -#define TLB_WORD2_E_ENABLE 0x00000080 -#define TLB_WORD2_E_DISABLE 0x00000000 -#define TLB_WORD2_UX_MASK 0x00000020 -#define TLB_WORD2_UX_ENABLE 0x00000020 -#define TLB_WORD2_UX_DISABLE 0x00000000 -#define TLB_WORD2_UW_MASK 0x00000010 -#define TLB_WORD2_UW_ENABLE 0x00000010 -#define TLB_WORD2_UW_DISABLE 0x00000000 -#define TLB_WORD2_UR_MASK 0x00000008 -#define TLB_WORD2_UR_ENABLE 0x00000008 -#define TLB_WORD2_UR_DISABLE 0x00000000 -#define TLB_WORD2_SX_MASK 0x00000004 -#define TLB_WORD2_SX_ENABLE 0x00000004 -#define TLB_WORD2_SX_DISABLE 0x00000000 -#define TLB_WORD2_SW_MASK 0x00000002 -#define TLB_WORD2_SW_ENABLE 0x00000002 -#define TLB_WORD2_SW_DISABLE 0x00000000 -#define TLB_WORD2_SR_MASK 0x00000001 -#define TLB_WORD2_SR_ENABLE 0x00000001 -#define TLB_WORD2_SR_DISABLE 0x00000000 +#ifdef CONFIG_440SPE /*----------------------------------------------------------------------------+ | Following instructions are not available in Book E mode of the GNU assembler. +----------------------------------------------------------------------------*/ @@ -690,22 +501,14 @@ extern int num_tlb_entries; #define MSYNC .long 0x7c000000|\ (598<<1) -#define MBAR_INST .long 0x7c000000|\ +#define MBAR_INST .long 0x7c000000|\ (854<<1) -#ifndef __ASSEMBLY__ -/* Prototypes */ -void mttlb1(unsigned long index, unsigned long value); -void mttlb2(unsigned long index, unsigned long value); -void mttlb3(unsigned long index, unsigned long value); -unsigned long mftlb1(unsigned long index); -unsigned long mftlb2(unsigned long index); -unsigned long mftlb3(unsigned long index); +/*----------------------------------------------------------------------------+ +| Following instruction is not available in PPC405 mode of the GNU assembler. ++----------------------------------------------------------------------------*/ +#define TLBRE(rt,ra,ws) .long 0x7c000000|\ + (rt<<21)|(ra<<16)|(ws<<11)|(946<<1) -void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); -void remove_tlb(u32 vaddr, u32 size); -void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value); -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_440 */ +#endif #endif /* _PPC_MMU_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e61786809..44b23f1eb 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -18,9 +18,9 @@ #define MSR_SF (1<<63) #define MSR_ISF (1<<61) #endif /* CONFIG_PPC64BRIDGE */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ -#define MSR_SPE (1<<25) /* Enable SPE(e500) */ +#define MSR_SPE (1<<25) /* Enable SPE(e500) */ #define MSR_POW (1<<18) /* Enable Power Management */ #define MSR_WE (1<<18) /* Wait State Enable */ #define MSR_TGPR (1<<17) /* TLB Update registers in use */ @@ -32,21 +32,21 @@ #define MSR_ME (1<<12) /* Machine Check Enable */ #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ #define MSR_SE (1<<10) /* Single Step */ -#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ -#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ +#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ +#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ #define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction Relocate */ -#define MSR_IS (1<<5) /* Book E Instruction space */ -#define MSR_DR (1<<4) /* Data Relocate */ -#define MSR_DS (1<<4) /* Book E Data space */ +#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IS (1<<5) /* Book E Instruction space */ +#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DS (1<<4) /* Book E Data space */ #define MSR_PE (1<<3) /* Protection Enable */ #define MSR_PX (1<<2) /* Protection Exclusive Mode */ -#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ +#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ #define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little Endian */ +#define MSR_LE (1<<0) /* Little Endian */ #ifdef CONFIG_APUS_FAST_EXCEPT #define MSR_ MSR_ME|MSR_IP|MSR_RI @@ -54,10 +54,11 @@ #define MSR_ MSR_ME|MSR_RI #endif #ifndef CONFIG_E500 -#define MSR_KERNEL MSR_|MSR_IR|MSR_DR +#define MSR_KERNEL MSR_|MSR_IR|MSR_DR #else #define MSR_KERNEL MSR_ME #endif +#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE /* Floating Point Status and Control Register (FPSCR) Fields */ @@ -91,11 +92,6 @@ /* Special Purpose Registers (SPRNs)*/ -/* PPC440 Architecture is BOOK-E */ -#ifdef CONFIG_440 -#define CONFIG_BOOKE -#endif - #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ @@ -103,9 +99,9 @@ #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ #else -#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ -#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ -#endif /* CONFIG_BOOKE */ +#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ +#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ +#endif /* CONFIG_BOOKE */ #define SPRN_DAR 0x013 /* Data Address Register */ #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ @@ -115,21 +111,21 @@ #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ -#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ -#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ -#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ -#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ -#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ -#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ -#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ -#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ +#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ +#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ +#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ +#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ +#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ +#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ +#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ +#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ #define DBCR_EDM 0x80000000 #define DBCR_IDM 0x40000000 #define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 #define DBCR_RST_SYSTEM 3 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ @@ -157,18 +153,18 @@ #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ #ifndef CONFIG_BOOKE -#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ +#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ #else -#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ +#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ #endif /* CONFIG_BOOKE */ #ifndef CONFIG_BOOKE #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ #define SPRN_DBSR 0x3F0 /* Debug Status Register */ #else -#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ -#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ -#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ -#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ +#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ +#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ +#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ #endif /* CONFIG_BOOKE */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define DCCR_NOCACHE 0 /* Noncacheable */ @@ -180,7 +176,7 @@ #ifndef CONFIG_BOOKE #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ #else -#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ +#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ #endif /* CONFIG_BOOKE */ #define SPRN_DEC 0x016 /* Decrement Register */ #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ @@ -189,7 +185,7 @@ #ifndef CONFIG_BOOKE #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ #else -#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ +#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ #endif /* CONFIG_BOOKE */ #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ @@ -222,14 +218,12 @@ #define HID0_DPM (1<<20) #define HID0_ICE (1<> 16) & 0xFFFF) /* Version field */ #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ -#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ -#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ -#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ -#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ -#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ -#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ -#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ +#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ +#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ +#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ +#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ +#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ +#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ +#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ + +/* System-On-Chip Version Numbers (version field only) */ +#define SVR_MPC5200 0x8011 /* Processor Version Register */ @@ -793,15 +721,6 @@ #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 -#define PVR_405EZ_RA 0x41511460 -#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */ -#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ -#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ -#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */ -#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ -#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ -#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ -#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_440EP_RA 0x42221850 @@ -809,27 +728,15 @@ #define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ #define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ #define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ -#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ -#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ -#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ #define PVR_440GX_RA 0x51B21850 #define PVR_440GX_RB 0x51B21851 #define PVR_440GX_RC 0x51B21892 #define PVR_440GX_RF 0x51B21894 #define PVR_405EP_RB 0x51210950 -#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ -#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ -#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ -#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ -#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ -#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ -#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ -#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ -#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ -#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ -#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ -#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_440SP_RA 0x53221850 +#define PVR_440SP_RB 0x53221891 +#define PVR_440SPe_RA 0x53421890 +#define PVR_440SPe_RB 0x53421891 #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 @@ -844,16 +751,14 @@ #define PVR_750 PVR_740 #define PVR_740P 0x10080000 #define PVR_750P PVR_740P -#define PVR_7400 0x000C0000 -#define PVR_7410 0x800C0000 -#define PVR_7450 0x80000000 +#define PVR_7400 0x000C0000 +#define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 #define PVR_85xx 0x80200000 #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) -#define PVR_86xx 0x80040000 -#define PVR_86xx_REV1 (PVR_86xx | 0x0010) /* * For the 8xx processors, all of them report the same PVR family for @@ -865,25 +770,20 @@ #define PVR_823 PVR_821 #define PVR_850 PVR_821 #define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 +#define PVR_7400 0x000C0000 #define PVR_8240 0x00810100 /* * PowerQUICC II family processors report different PVR values depending * on silicon process (HiP3, HiP4, HiP7, etc.) */ -#define PVR_8260 PVR_8240 -#define PVR_8260_HIP3 0x00810101 -#define PVR_8260_HIP4 0x80811014 -#define PVR_8260_HIP7 0x80822011 +#define PVR_8260 PVR_8240 +#define PVR_8260_HIP3 0x00810101 +#define PVR_8260_HIP4 0x80811014 +#define PVR_8260_HIP7 0x80822011 #define PVR_8260_HIP7R1 0x80822013 #define PVR_8260_HIP7RA 0x80822014 -/* - * MPC 52xx - */ -#define PVR_5200 0x80822011 -#define PVR_5200B 0x80822014 /* * System Version Register @@ -894,57 +794,74 @@ #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ -#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ - #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ -/* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ - -/* whether MPC8xxxE (i.e. has SEC) */ -#if defined(CONFIG_MPC85xx) -#define IS_E_PROCESSOR(svr) (svr & 0x80000) -#else -#if defined(CONFIG_MPC83XX) -#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) -#endif -#endif /* - * SVR_SOC_VER() Version Values + * SVR_VER() Version Values */ -#define SVR_8533 0x803400 -#define SVR_8533_E 0x803C00 -#define SVR_8540 0x803000 -#define SVR_8541 0x807200 -#define SVR_8541_E 0x807A00 -#define SVR_8543 0x803200 -#define SVR_8543_E 0x803A00 -#define SVR_8544 0x803401 -#define SVR_8544_E 0x803C01 -#define SVR_8545 0x803102 -#define SVR_8545_E 0x803902 -#define SVR_8547_E 0x803901 -#define SVR_8548 0x803100 -#define SVR_8548_E 0x803900 -#define SVR_8555 0x807100 -#define SVR_8555_E 0x807900 -#define SVR_8560 0x807000 -#define SVR_8567 0x807600 -#define SVR_8567_E 0x807E00 -#define SVR_8568 0x807500 -#define SVR_8568_E 0x807D00 -#define SVR_8572 0x80E000 -#define SVR_8572_E 0x80E800 +#define SVR_8540 0x8030 +#define SVR_8560 0x8070 +#define SVR_8555 0x8079 +#define SVR_8541 0x807A +#define SVR_8548 0x8031 +#define SVR_8548_E 0x8039 -#define SVR_8610 0x80A000 -#define SVR_8641 0x809000 -#define SVR_8641D 0x809001 + +/* I am just adding a single entry for 8260 boards. I think we may be + * able to combine mbx, fads, rpxlite, bseip, and classic into a single + * generic 8xx as well. The boards containing these processors are either + * identical at the processor level (due to the high integration) or so + * wildly different that testing _machine at run time is best replaced by + * conditional compilation by board type (found in their respective .h file). + * -- Dan + */ +#define _MACH_prep 0x00000001 +#define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */ +#define _MACH_chrp 0x00000004 /* chrp machine */ +#define _MACH_mbx 0x00000008 /* Motorola MBX board */ +#define _MACH_apus 0x00000010 /* amiga with phase5 powerup */ +#define _MACH_fads 0x00000020 /* Motorola FADS board */ +#define _MACH_rpxlite 0x00000040 /* RPCG RPX-Lite 8xx board */ +#define _MACH_bseip 0x00000080 /* Bright Star Engineering ip-Engine */ +#define _MACH_yk 0x00000100 /* Motorola Yellowknife */ +#define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */ +#define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */ +#define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */ +#define _MACH_walnut 0x00001000 /* AMCC "Walnut" 405GP eval. board */ +#define _MACH_8260 0x00002000 /* Generic 8260 */ +#define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */ +#define _MACH_tqm860 0x00008000 /* TQM860/L */ +#define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */ +#define _MACH_hidden_dragon 0x00020000 /* Motorola Hidden Dragon eval board */ + + +/* see residual.h for these */ +#define _PREP_Motorola 0x01 /* motorola prep */ +#define _PREP_Firm 0x02 /* firmworks prep */ +#define _PREP_IBM 0x00 /* ibm prep */ +#define _PREP_Bull 0x03 /* bull prep */ +#define _PREP_Radstone 0x04 /* Radstone Technology PLC prep */ + +/* + * Radstone board types + */ +#define RS_SYS_TYPE_PPC1 0 +#define RS_SYS_TYPE_PPC2 1 +#define RS_SYS_TYPE_PPC1a 2 +#define RS_SYS_TYPE_PPC2a 3 +#define RS_SYS_TYPE_PPC4 4 +#define RS_SYS_TYPE_PPC4a 5 +#define RS_SYS_TYPE_PPC2ep 6 + +/* these are arbitrary */ +#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ +#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ #define _GLOBAL(n)\ .globl n;\ @@ -991,24 +908,6 @@ n: #define SR15 15 #ifndef __ASSEMBLY__ - -struct cpu_type { - char name[15]; - u32 soc_ver; -}; - -struct cpu_type *identify_cpu(u32 ver); - -#if defined(CONFIG_MPC85xx) -#define CPU_TYPE_ENTRY(n, v) \ - { .name = #n, .soc_ver = SVR_##v, } -#else -#if defined(CONFIG_MPC83XX) -#define CPU_TYPE_ENTRY(x) {#x, SPR_##x} -#endif -#endif - - #ifndef CONFIG_MACH_SPECIFIC extern int _machine; extern int have_of; @@ -1068,7 +967,7 @@ struct thread_struct { struct pt_regs *regs; /* Pointer to saved register state */ mm_segment_t fs; /* for get_fs() validation */ void *pgdir; /* root of page-table tree */ - signed long last_syscall; + signed long last_syscall; double fpr[32]; /* Complete floating point set */ unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ unsigned long fpscr; /* Floating point status */ @@ -1093,7 +992,7 @@ struct thread_struct { /* * Note: the vm_start and vm_end fields here should *not* - * be in kernel space. (Could vm_end == vm_start perhaps?) + * be in kernel space. (Could vm_end == vm_start perhaps?) */ #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ @@ -1123,7 +1022,7 @@ unsigned long get_wchan(struct task_struct *p); #define alloc_task_struct() \ ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) #define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) /* in process.c - for early bootup debug -- Cort */ int ll_printk(const char *, ...); diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h index 196613b9f..3c2f4e605 100644 --- a/include/asm-ppc/ptrace.h +++ b/include/asm-ppc/ptrace.h @@ -39,7 +39,7 @@ struct pt_regs { PPC_REG trap; /* Reason for being here */ PPC_REG dar; /* Fault registers */ PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ + PPC_REG result; /* Result of a system call */ }; #endif diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h index 715c868ab..4bd66a707 100644 --- a/include/asm-ppc/sigcontext.h +++ b/include/asm-ppc/sigcontext.h @@ -9,7 +9,7 @@ struct sigcontext_struct { int signal; unsigned long handler; unsigned long oldmask; - struct pt_regs *regs; + struct pt_regs *regs; }; #endif diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h index 864391f03..4ebbb9e02 100644 --- a/include/asm-ppc/types.h +++ b/include/asm-ppc/types.h @@ -14,9 +14,9 @@ typedef unsigned short __u16; typedef __signed__ int __s32; typedef unsigned int __u32; -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; #endif typedef struct { @@ -44,14 +44,6 @@ typedef unsigned long long u64; /* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; -#ifdef CONFIG_PHYS_64BIT -typedef unsigned long long phys_addr_t; -typedef unsigned long long phys_size_t; -#else -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; -#endif - #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 54ac01d36..f7aa55f33 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -38,14 +38,14 @@ typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ #if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ - || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) + || defined(CONFIG_E500) unsigned long bi_immr_base; /* base of IMMR register */ #endif #if defined(CONFIG_MPC5xxx) @@ -74,9 +74,6 @@ typedef struct bd_info { unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ unsigned long bi_vco; /* VCO Out from PLL, in MHz */ #endif -#if defined(CONFIG_MPC512X) - unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ -#endif /* CONFIG_MPC512X */ #if defined(CONFIG_MPC5xxx) unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ @@ -86,8 +83,6 @@ typedef struct bd_info { defined(CONFIG_405GP) || \ defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || \ - defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) || \ defined(CONFIG_440) unsigned char bi_s_version[4]; /* Version of this structure */ unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ @@ -112,11 +107,8 @@ typedef struct bd_info { unsigned char bi_enet3addr[6]; #endif -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ - defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) unsigned int bi_opbfreq; /* OPB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif @@ -124,16 +116,15 @@ typedef struct bd_info { unsigned char bi_sernum[8]; #endif #if defined(CONFIG_4xx) -#if defined(CONFIG_440GX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) - int bi_phynum[4]; /* Determines phy mapping */ - int bi_phymode[4]; /* Determines phy mode */ +#if defined(CONFIG_440GX) + int bi_phynum[4]; /* Determines phy mapping */ + int bi_phymode[4]; /* Determines phy mode */ #elif defined(CONFIG_405EP) || defined(CONFIG_440) - int bi_phynum[2]; /* Determines phy mapping */ - int bi_phymode[2]; /* Determines phy mode */ + int bi_phynum[2]; /* Determines phy mapping */ + int bi_phymode[2]; /* Determines phy mode */ #else - int bi_phynum[1]; /* Determines phy mapping */ - int bi_phymode[1]; /* Determines phy mode */ + int bi_phynum[1]; /* Determines phy mapping */ + int bi_phymode[1]; /* Determines phy mode */ #endif #endif /* defined(CONFIG_4xx) */ } bd_t; diff --git a/include/ata.h b/include/ata.h index aa6e90d47..8584226eb 100644 --- a/include/ata.h +++ b/include/ata.h @@ -83,66 +83,6 @@ #define ATA_DEVICE(x) ((x & 1)<<4) #define ATA_LBA 0xE0 -enum { - ATA_MAX_DEVICES = 1, /* per bus/port */ - ATA_MAX_PRD = 256, /* we could make these 256/256 */ - ATA_SECT_SIZE = 256, /*256 words per sector */ - - /* bits in ATA command block registers */ - ATA_HOB = (1 << 7), /* LBA48 selector */ - ATA_NIEN = (1 << 1), /* disable-irq flag */ - /*ATA_LBA = (1 << 6), */ /* LBA28 selector */ - ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */ - ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */ - ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */ - ATA_BUSY = (1 << 7), /* BSY status bit */ - ATA_DRDY = (1 << 6), /* device ready */ - ATA_DF = (1 << 5), /* device fault */ - ATA_DRQ = (1 << 3), /* data request i/o */ - ATA_ERR = (1 << 0), /* have an error */ - ATA_SRST = (1 << 2), /* software reset */ - ATA_ABORTED = (1 << 2), /* command aborted */ - /* ATA command block registers */ - ATA_REG_DATA = 0x00, - ATA_REG_ERR = 0x01, - ATA_REG_NSECT = 0x02, - ATA_REG_LBAL = 0x03, - ATA_REG_LBAM = 0x04, - ATA_REG_LBAH = 0x05, - ATA_REG_DEVICE = 0x06, - ATA_REG_STATUS = 0x07, - ATA_PCI_CTL_OFS = 0x02, - /* and their aliases */ - ATA_REG_FEATURE = ATA_REG_ERR, - ATA_REG_CMD = ATA_REG_STATUS, - ATA_REG_BYTEL = ATA_REG_LBAM, - ATA_REG_BYTEH = ATA_REG_LBAH, - ATA_REG_DEVSEL = ATA_REG_DEVICE, - ATA_REG_IRQ = ATA_REG_NSECT, - - /* SETFEATURES stuff */ - SETFEATURES_XFER = 0x03, - XFER_UDMA_7 = 0x47, - XFER_UDMA_6 = 0x46, - XFER_UDMA_5 = 0x45, - XFER_UDMA_4 = 0x44, - XFER_UDMA_3 = 0x43, - XFER_UDMA_2 = 0x42, - XFER_UDMA_1 = 0x41, - XFER_UDMA_0 = 0x40, - XFER_MW_DMA_2 = 0x22, - XFER_MW_DMA_1 = 0x21, - XFER_MW_DMA_0 = 0x20, - XFER_PIO_4 = 0x0C, - XFER_PIO_3 = 0x0B, - XFER_PIO_2 = 0x0A, - XFER_PIO_1 = 0x09, - XFER_PIO_0 = 0x08, - XFER_SW_DMA_2 = 0x12, - XFER_SW_DMA_1 = 0x11, - XFER_SW_DMA_0 = 0x10, - XFER_PIO_SLOW = 0x00 -}; /* * ATA Commands (only mandatory commands listed here) */ diff --git a/include/bcm5221.h b/include/bcm5221.h index 61424b127..6fb94aaef 100644 --- a/include/bcm5221.h +++ b/include/bcm5221.h @@ -23,7 +23,7 @@ * MA 02111-1307 USA */ -#define BCM5221_BMCR 0 /* Basic Mode Control Register */ +#define BCM5221_BMCR 0 /* Basic Mode Control Register */ #define BCM5221_BMSR 1 /* Basic Mode Status Register */ #define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */ #define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */ diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h index 46bf8db1a..9cc8f9fa3 100644 --- a/include/bedbug/ppc.h +++ b/include/bedbug/ppc.h @@ -321,7 +321,7 @@ struct opcode { array are the operand identifiers */ int (*hfunc)(struct ppc_ctx *); - /* Address of a function to handle the given + /* Address of a function to handle the given mnemonic */ char * name; /* The symbolic name of this opcode */ diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h index e675de320..66cf8eaea 100644 --- a/include/bedbug/tables.h +++ b/include/bedbug/tables.h @@ -12,43 +12,43 @@ */ struct operand operands[] = { - /*Field Name Bits Shift Hint Position */ - /*----- ------ ----- ----- ---- ------------ */ - { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */ + /*Field Name Bits Shift Hint Position */ + /*----- ------ ----- ----- ---- ------------ */ + { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */ { O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */ - { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */ - { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */ - { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */ - { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */ - { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */ - { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */ + { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */ + { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */ + { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */ + { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */ + { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */ + { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */ { O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */ - { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */ - { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */ - { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */ - { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */ + { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */ + { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */ + { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */ + { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */ { O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */ - { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */ - { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */ - { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */ - { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */ - { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */ - { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */ - { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */ - { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */ - { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */ - { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */ - { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */ + { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */ + { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */ + { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */ + { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */ + { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */ + { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */ + { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */ + { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */ + { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */ + { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */ + { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */ { O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */ - { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */ - { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */ + { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */ + { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */ { O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */ - { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */ - { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */ - { O_L, "O_L", 1, 21, 0 }, /* 10 */ + { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */ + { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */ + { O_L, "O_L", 1, 21, 0 }, /* 10 */ { O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */ { O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */ - { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */ + { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */ }; const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]); @@ -64,418 +64,418 @@ const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]); bit locations */ struct opcode opcodes[] = { - { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0}, - 0, "twi", 0 }, - { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "mulli", 0 }, - { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "subfic", 0 }, - { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0}, - 0, "cmpli", 0 }, - { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0}, - 0, "cmpi", 0 }, - { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addic", 0 }, - { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addic.", 0 }, - { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addi", H_RA0_IS_0 }, - { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addis", H_RA0_IS_0|H_IMM_HIGH }, - { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - handle_bc, "bc", H_RELATIVE }, - { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - 0, "bcl", H_RELATIVE }, - { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - 0, "bca", 0 }, - { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - 0, "bcla", 0 }, - { SC_OPCODE(17), SC_MASK, {0}, - 0, "sc", 0 }, - { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "b", H_RELATIVE }, - { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "bl", H_RELATIVE }, - { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "ba", 0 }, - { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "bla", 0 }, - { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS}, - 0, "mcrf", 0 }, + { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0}, + 0, "twi", 0 }, + { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "mulli", 0 }, + { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "subfic", 0 }, + { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0}, + 0, "cmpli", 0 }, + { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0}, + 0, "cmpi", 0 }, + { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addic", 0 }, + { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addic.", 0 }, + { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addi", H_RA0_IS_0 }, + { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addis", H_RA0_IS_0|H_IMM_HIGH }, + { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + handle_bc, "bc", H_RELATIVE }, + { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bcl", H_RELATIVE }, + { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bca", 0 }, + { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bcla", 0 }, + { SC_OPCODE(17), SC_MASK, {0}, + 0, "sc", 0 }, + { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "b", H_RELATIVE }, + { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "bl", H_RELATIVE }, + { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "ba", 0 }, + { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "bla", 0 }, + { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS}, + 0, "mcrf", 0 }, { XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bclr", 0 }, + 0, "bclr", 0 }, { XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bclrl", 0 }, + 0, "bclrl", 0 }, { XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crnor", 0 }, + 0, "crnor", 0 }, { XL_OPCODE(19,50,0), XL_MASK, {0}, - 0, "rfi", 0 }, + 0, "rfi", 0 }, { XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crandc", 0 }, + 0, "crandc", 0 }, { XL_OPCODE(19,150,0), XL_MASK, {0}, - 0, "isync", 0 }, + 0, "isync", 0 }, { XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crxor", 0 }, + 0, "crxor", 0 }, { XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crnand", 0 }, + 0, "crnand", 0 }, { XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crand", 0 }, + 0, "crand", 0 }, { XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "creqv", 0 }, + 0, "creqv", 0 }, { XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crorc", 0 }, + 0, "crorc", 0 }, { XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "cror", 0 }, + 0, "cror", 0 }, { XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bcctr", 0 }, + 0, "bcctr", 0 }, { XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bcctrl", 0 }, - { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwimi", 0 }, - { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwimi.", 0 }, - { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwinm", 0 }, - { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwinm.", 0 }, - { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, - 0, "rlwnm", 0 }, - { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, - 0, "rlwnm.", 0 }, - { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "ori", 0 }, - { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "oris", H_IMM_HIGH }, - { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "xori", 0 }, - { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "xoris", H_IMM_HIGH }, - { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "andi.", 0 }, - { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "andis.", H_IMM_HIGH }, - { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, - 0, "cmp", 0 }, - { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0}, - 0, "tw", 0 }, + 0, "bcctrl", 0 }, + { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwimi", 0 }, + { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwimi.", 0 }, + { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwinm", 0 }, + { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwinm.", 0 }, + { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, + 0, "rlwnm", 0 }, + { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, + 0, "rlwnm.", 0 }, + { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "ori", 0 }, + { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "oris", H_IMM_HIGH }, + { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "xori", 0 }, + { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "xoris", H_IMM_HIGH }, + { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "andi.", 0 }, + { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "andis.", H_IMM_HIGH }, + { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, + 0, "cmp", 0 }, + { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0}, + 0, "tw", 0 }, { XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfc", 0 }, + 0, "subfc", 0 }, { XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfc.", 0 }, + 0, "subfc.", 0 }, { XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addc", 0 }, + 0, "addc", 0 }, { XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addc.", 0 }, + 0, "addc.", 0 }, { XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhwu", 0 }, + 0, "mulhwu", 0 }, { XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhwu.", 0 }, - { X_OPCODE(31,19,0), X_MASK, {O_rD, 0}, - 0, "mfcr", 0 }, - { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwarx", H_RA0_IS_0 }, - { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwzx", H_RA0_IS_0 }, - { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "slw", 0 }, - { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "slw.", 0 }, - { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 }, - 0, "cntlzw", 0 }, - { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "cntlzw.", 0 }, - { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "and", 0 }, - { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "and.", 0 }, - { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, - 0, "cmpl", 0 }, + 0, "mulhwu.", 0 }, + { X_OPCODE(31,19,0), X_MASK, {O_rD, 0}, + 0, "mfcr", 0 }, + { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwarx", H_RA0_IS_0 }, + { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwzx", H_RA0_IS_0 }, + { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "slw", 0 }, + { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "slw.", 0 }, + { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 }, + 0, "cntlzw", 0 }, + { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "cntlzw.", 0 }, + { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "and", 0 }, + { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "and.", 0 }, + { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, + 0, "cmpl", 0 }, { XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subf", 0 }, + 0, "subf", 0 }, { XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subf.", 0 }, - { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbst", H_RA0_IS_0 }, - { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwzux", 0 }, - { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "andc", 0 }, - { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "andc.", 0 }, + 0, "subf.", 0 }, + { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbst", H_RA0_IS_0 }, + { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwzux", 0 }, + { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "andc", 0 }, + { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "andc.", 0 }, { XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhw", 0 }, + 0, "mulhw", 0 }, { XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhw.", 0 }, - { X_OPCODE(31,83,0), X_MASK, {O_rD, 0}, - 0, "mfmsr", 0 }, - { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbf", H_RA0_IS_0 }, - { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lbzx", H_RA0_IS_0 }, + 0, "mulhw.", 0 }, + { X_OPCODE(31,83,0), X_MASK, {O_rD, 0}, + 0, "mfmsr", 0 }, + { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbf", H_RA0_IS_0 }, + { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lbzx", H_RA0_IS_0 }, { XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "neg", 0 }, + 0, "neg", 0 }, { XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "neg.", 0 }, + 0, "neg.", 0 }, { X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lbzux", 0 }, + 0, "lbzux", 0 }, { X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "nor", 0 }, + 0, "nor", 0 }, { X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "nor.", 0 }, + 0, "nor.", 0 }, { XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfe", 0 }, + 0, "subfe", 0 }, { XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfe.", 0 }, + 0, "subfe.", 0 }, { XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "adde", 0 }, + 0, "adde", 0 }, { XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "adde.", 0 }, + 0, "adde.", 0 }, { XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0}, - 0, "mtcrf", 0 }, + 0, "mtcrf", 0 }, { X_OPCODE(31,146,0), X_MASK, {O_rS, 0}, - 0, "mtmsr", 0 }, + 0, "mtmsr", 0 }, { X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwcx.", 0 }, + 0, "stwcx.", 0 }, { X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwx", 0 }, + 0, "stwx", 0 }, { X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwux", 0 }, + 0, "stwux", 0 }, { XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfze", 0 }, + 0, "subfze", 0 }, { XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfze.", 0 }, + 0, "subfze.", 0 }, { XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addze", 0 }, + 0, "addze", 0 }, { XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addze.", 0 }, + 0, "addze.", 0 }, { X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0}, - 0, "mtsr", 0 }, + 0, "mtsr", 0 }, { X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stbx", H_RA0_IS_0 }, + 0, "stbx", H_RA0_IS_0 }, { XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfme", 0 }, + 0, "subfme", 0 }, { XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfme.", 0 }, + 0, "subfme.", 0 }, { XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addme", 0 }, + 0, "addme", 0 }, { XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addme.", 0 }, + 0, "addme.", 0 }, { XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullw", 0 }, + 0, "mullw", 0 }, { XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullw.", 0 }, + 0, "mullw.", 0 }, { X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0}, - 0, "mtsrin", 0 }, + 0, "mtsrin", 0 }, { X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbtst", H_RA0_IS_0 }, + 0, "dcbtst", H_RA0_IS_0 }, { X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stbux", 0 }, + 0, "stbux", 0 }, { XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "add", 0 }, + 0, "add", 0 }, { XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "add.", 0 }, + 0, "add.", 0 }, { X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbt", H_RA0_IS_0 }, + 0, "dcbt", H_RA0_IS_0 }, { X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhzx", H_RA0_IS_0 }, + 0, "lhzx", H_RA0_IS_0 }, { X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "eqv", 0 }, + 0, "eqv", 0 }, { X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "eqv.", 0 }, + 0, "eqv.", 0 }, { X_OPCODE(31,306,0), X_MASK, {O_rB, 0}, - 0, "tlbie", 0 }, + 0, "tlbie", 0 }, { X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "eciwx", H_RA0_IS_0 }, + 0, "eciwx", H_RA0_IS_0 }, { X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhzux", 0 }, + 0, "lhzux", 0 }, { X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "xor", 0 }, + 0, "xor", 0 }, { X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "xor.", 0 }, + 0, "xor.", 0 }, { XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0}, - 0, "mfspr", 0 }, + 0, "mfspr", 0 }, { X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhax", H_RA0_IS_0 }, + 0, "lhax", H_RA0_IS_0 }, { X_OPCODE(31,370,0), X_MASK, {0}, - 0, "tlbia", 0 }, + 0, "tlbia", 0 }, { XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0}, - 0, "mftb", 0 }, + 0, "mftb", 0 }, { X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhaux", 0 }, + 0, "lhaux", 0 }, { X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "sthx", H_RA0_IS_0 }, + 0, "sthx", H_RA0_IS_0 }, { X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "orc", 0 }, + 0, "orc", 0 }, { X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "orc.", 0 }, + 0, "orc.", 0 }, { X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "ecowx", H_RA0_IS_0 }, + 0, "ecowx", H_RA0_IS_0 }, { X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "sthux", 0 }, + 0, "sthux", 0 }, { X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "or", 0 }, + 0, "or", 0 }, { X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "or.", 0 }, + 0, "or.", 0 }, { XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwu", 0 }, + 0, "divwu", 0 }, { XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwu.", 0 }, + 0, "divwu.", 0 }, { XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0}, - 0, "mtspr", 0 }, + 0, "mtspr", 0 }, { X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbi", H_RA0_IS_0 }, + 0, "dcbi", H_RA0_IS_0 }, { X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "nand", 0 }, + 0, "nand", 0 }, { X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0}, - 0, "nand.", 0 }, + 0, "nand.", 0 }, { XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divw", 0 }, + 0, "divw", 0 }, { XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divw.", 0 }, + 0, "divw.", 0 }, { X_OPCODE(31,512,0), X_MASK, {O_crfD, 0}, - 0, "mcrxr", 0 }, + 0, "mcrxr", 0 }, { XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfco", 0 }, + 0, "subfco", 0 }, { XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfco.", 0 }, + 0, "subfco.", 0 }, { XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addco", 0 }, + 0, "addco", 0 }, { XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addco.", 0 }, + 0, "addco.", 0 }, { X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lswx", H_RA0_IS_0 }, + 0, "lswx", H_RA0_IS_0 }, { X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwbrx", H_RA0_IS_0 }, + 0, "lwbrx", H_RA0_IS_0 }, { X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "srw", 0 }, + 0, "srw", 0 }, { X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "srw.", 0 }, + 0, "srw.", 0 }, { XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfo", 0 }, + 0, "subfo", 0 }, { XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfo.", 0 }, + 0, "subfo.", 0 }, { X_OPCODE(31,566,0), X_MASK, {0}, - 0, "tlbsync", 0 }, + 0, "tlbsync", 0 }, { X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0}, - 0, "mfsr", 0 }, + 0, "mfsr", 0 }, { X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0}, - 0, "lswi", H_RA0_IS_0 }, + 0, "lswi", H_RA0_IS_0 }, { X_OPCODE(31,598,0), X_MASK, {0}, - 0, "sync", 0 }, + 0, "sync", 0 }, { XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "nego", 0 }, + 0, "nego", 0 }, { XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "nego.", 0 }, + 0, "nego.", 0 }, { XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfeo", 0 }, + 0, "subfeo", 0 }, { XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfeo.", 0 }, + 0, "subfeo.", 0 }, { XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addeo", 0 }, + 0, "addeo", 0 }, { XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addeo.", 0 }, + 0, "addeo.", 0 }, { X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0}, - 0, "mfsrin", 0 }, + 0, "mfsrin", 0 }, { X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stswx", H_RA0_IS_0 }, + 0, "stswx", H_RA0_IS_0 }, { X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwbrx", H_RA0_IS_0 }, + 0, "stwbrx", H_RA0_IS_0 }, { XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfzeo", 0 }, + 0, "subfzeo", 0 }, { XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfzeo.", 0 }, + 0, "subfzeo.", 0 }, { XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addzeo", 0 }, + 0, "addzeo", 0 }, { XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addzeo.", 0 }, + 0, "addzeo.", 0 }, { X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0}, - 0, "stswi", H_RA0_IS_0 }, + 0, "stswi", H_RA0_IS_0 }, { XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfmeo", 0 }, + 0, "subfmeo", 0 }, { XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfmeo.", 0 }, + 0, "subfmeo.", 0 }, { XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addmeo", 0 }, + 0, "addmeo", 0 }, { XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addmeo.", 0 }, + 0, "addmeo.", 0 }, { XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullwo", 0 }, + 0, "mullwo", 0 }, { XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullwo.", 0 }, + 0, "mullwo.", 0 }, { XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addo", 0 }, + 0, "addo", 0 }, { XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addo.", 0 }, + 0, "addo.", 0 }, { X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhbrx", H_RA0_IS_0 }, + 0, "lhbrx", H_RA0_IS_0 }, { X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "sraw", 0 }, + 0, "sraw", 0 }, { X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "sraw.", 0 }, + 0, "sraw.", 0 }, { X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, - 0, "srawi", 0 }, + 0, "srawi", 0 }, { X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, - 0, "srawi.", 0 }, + 0, "srawi.", 0 }, { X_OPCODE(31,854,0), X_MASK, {0}, - 0, "eieio", 0 }, + 0, "eieio", 0 }, { X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "sthbrx", H_RA0_IS_0 }, + 0, "sthbrx", H_RA0_IS_0 }, { X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsh", 0 }, + 0, "extsh", 0 }, { X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsh.", 0 }, + 0, "extsh.", 0 }, { X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsb", 0 }, + 0, "extsb", 0 }, { X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsb.", 0 }, + 0, "extsb.", 0 }, { XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwuo", 0 }, + 0, "divwuo", 0 }, { XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwuo.", 0 }, + 0, "divwuo.", 0 }, { X_OPCODE(31,978,0), X_MASK, {O_rB, 0}, - 0, "tlbld", 0 }, + 0, "tlbld", 0 }, { X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0}, - 0, "icbi", H_RA0_IS_0 }, + 0, "icbi", H_RA0_IS_0 }, { XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwo", 0 }, + 0, "divwo", 0 }, { XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwo.", 0 }, + 0, "divwo.", 0 }, { X_OPCODE(31,1010,0), X_MASK, {O_rB, 0}, - 0, "tlbli", 0 }, + 0, "tlbli", 0 }, { X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbz", H_RA0_IS_0 }, - { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lwz", H_RA0_IS_0 }, - { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lwzu", 0 }, - { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lbz", H_RA0_IS_0 }, - { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lbzu", 0 }, - { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stw", H_RA0_IS_0 }, - { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stwu", 0 }, - { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stb", H_RA0_IS_0 }, - { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stbu", 0 }, - { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lhz", H_RA0_IS_0 }, - { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lhzu", 0 }, - { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lha", H_RA0_IS_0 }, - { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lhau", 0 }, - { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "sth", H_RA0_IS_0 }, - { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "sthu", 0 }, - { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lmw", H_RA0_IS_0 }, - { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stmw", H_RA0_IS_0 }, + 0, "dcbz", H_RA0_IS_0 }, + { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lwz", H_RA0_IS_0 }, + { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lwzu", 0 }, + { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lbz", H_RA0_IS_0 }, + { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lbzu", 0 }, + { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stw", H_RA0_IS_0 }, + { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stwu", 0 }, + { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stb", H_RA0_IS_0 }, + { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stbu", 0 }, + { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhz", H_RA0_IS_0 }, + { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhzu", 0 }, + { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lha", H_RA0_IS_0 }, + { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhau", 0 }, + { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "sth", H_RA0_IS_0 }, + { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "sthu", 0 }, + { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lmw", H_RA0_IS_0 }, + { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stmw", H_RA0_IS_0 }, }; const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]); diff --git a/include/bootscript.h b/include/bootscript.h new file mode 100644 index 000000000..f3a734e93 --- /dev/null +++ b/include/bootscript.h @@ -0,0 +1,46 @@ +/* + * Import bootscripts from binary blobs + * See board/tomtom/... as an example of how this works + * + * Copyright (C) 2010 TomTom International B.V. + * + ************************************************************************ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + ************************************************************************ + */ + +#ifndef __BOOTSCRIPT_H +#define __BOOTSCRIPT_H + +#include + +#if defined(CONFIG_CMD_AUTOSCRIPT) || defined(CFG_CMD_AUTOSCRIPT) +static inline void __set_bootscript_in_env(char *e, void *p) +{ + char t[32]; + + sprintf(t, "autoscr %p", p); + setenv(e, t); +} +# define IMPORT_BOOTSCRIPT(s,v) \ + extern char _binary_##s##_image_start; \ + __set_bootscript_in_env(#v,&_binary_##s##_image_start); +#else +# define IMPORT_BOOTSCRIPT(s,v) __IMPORT_BOOTSCRIPT_is_broken__ +#endif + +#endif /* __BOOTSCRIPT_H */ + diff --git a/include/clps7111.h b/include/clps7111.h index baf600773..d122d847a 100644 --- a/include/clps7111.h +++ b/include/clps7111.h @@ -231,7 +231,7 @@ #define IO_RTCDR IO_WORD(RTCDR) #define IO_RTCMR IO_WORD(RTCMR) #define IO_PMPCON IO_WORD(PMPCON) -#define IO_CODR IO_BYTE(CODR) +#define IO_CODR IO_BYTE(CODR) #define IO_UARTDR IO_WORD(UARTDR) #define IO_UBRLCR IO_WORD(UBRLCR) #define IO_SYNCIO IO_WORD(SYNCIO) diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h new file mode 100644 index 000000000..8532cc9aa --- /dev/null +++ b/include/cmd_confdefs.h @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Definitions for Configuring the monitor commands + */ +#ifndef _CMD_CONFIG_H +#define _CMD_CONFIG_H + +/* + * Configurable monitor commands + */ +#define CFG_CMD_BDI 0x00000001ULL /* bdinfo */ +#define CFG_CMD_LOADS 0x00000002ULL /* loads */ +#define CFG_CMD_LOADB 0x00000004ULL /* loadb */ +#define CFG_CMD_IMI 0x00000008ULL /* iminfo */ +#define CFG_CMD_CACHE 0x00000010ULL /* icache, dcache */ +#define CFG_CMD_FLASH 0x00000020ULL /* flinfo, erase, protect */ +#define CFG_CMD_MEMORY 0x00000040ULL /* md, mm, nm, mw, cp, cmp, */ + /* crc, base, loop, mtest */ +#define CFG_CMD_NET 0x00000080ULL /* bootp, tftpboot, rarpboot */ +#define CFG_CMD_ENV 0x00000100ULL /* saveenv */ +#define CFG_CMD_KGDB 0x0000000000000200ULL /* kgdb */ +#define CFG_CMD_PCMCIA 0x00000400ULL /* PCMCIA support */ +#define CFG_CMD_IDE 0x00000800ULL /* IDE harddisk support */ +#define CFG_CMD_PCI 0x00001000ULL /* pciinfo */ +#define CFG_CMD_IRQ 0x00002000ULL /* irqinfo */ +#define CFG_CMD_BOOTD 0x00004000ULL /* bootd */ +#define CFG_CMD_CONSOLE 0x00008000ULL /* coninfo */ +#define CFG_CMD_EEPROM 0x00010000ULL /* EEPROM read/write support */ +#define CFG_CMD_ASKENV 0x00020000ULL /* ask for env variable */ +#define CFG_CMD_RUN 0x00040000ULL /* run command in env variable */ +#define CFG_CMD_ECHO 0x00080000ULL /* echo arguments */ +#define CFG_CMD_I2C 0x00100000ULL /* I2C serial bus support */ +#define CFG_CMD_REGINFO 0x00200000ULL /* Register dump */ +#define CFG_CMD_IMMAP 0x00400000ULL /* IMMR dump support */ +#define CFG_CMD_DATE 0x00800000ULL /* support for RTC, date/time...*/ +#define CFG_CMD_DHCP 0x01000000ULL /* DHCP Support */ +#define CFG_CMD_BEDBUG 0x02000000ULL /* Include BedBug Debugger */ +#define CFG_CMD_FDC 0x04000000ULL /* Floppy Disk Support */ +#define CFG_CMD_SCSI 0x08000000ULL /* SCSI Support */ +#define CFG_CMD_AUTOSCRIPT 0x10000000ULL /* Autoscript Support */ +#define CFG_CMD_MII 0x20000000ULL /* MII support */ +#define CFG_CMD_SETGETDCR 0x40000000ULL /* DCR support on 4xx */ +#define CFG_CMD_BSP 0x80000000ULL /* Board Specific functions */ + +#define CFG_CMD_ELF 0x0000000100000000ULL /* ELF (VxWorks) load/boot cmd */ +#define CFG_CMD_MISC 0x0000000200000000ULL /* Misc functions like sleep etc*/ +#define CFG_CMD_USB 0x0000000400000000ULL /* USB Support */ +#define CFG_CMD_DOC 0x0000000800000000ULL /* Disk-On-Chip Support */ +#define CFG_CMD_JFFS2 0x0000001000000000ULL /* JFFS2 Support */ +#define CFG_CMD_DTT 0x0000002000000000ULL /* Digital Therm and Thermostat */ +#define CFG_CMD_SDRAM 0x0000004000000000ULL /* SDRAM DIMM SPD info printout */ +#define CFG_CMD_DIAG 0x0000008000000000ULL /* Diagnostics */ +#define CFG_CMD_FPGA 0x0000010000000000ULL /* FPGA configuration Support */ +#define CFG_CMD_HWFLOW 0x0000020000000000ULL /* RTS/CTS hw flow control */ +#define CFG_CMD_SAVES 0x0000040000000000ULL /* save S record dump */ +#define CFG_CMD_SPI 0x0000100000000000ULL /* SPI utility */ +#define CFG_CMD_FDOS 0x0000200000000000ULL /* Floppy DOS support */ +#define CFG_CMD_VFD 0x0000400000000000ULL /* VFD support (TRAB) */ +#define CFG_CMD_NAND 0x0000800000000000ULL /* NAND support */ +#define CFG_CMD_BMP 0x0001000000000000ULL /* BMP support */ +#define CFG_CMD_PORTIO 0x0002000000000000ULL /* Port I/O */ +#define CFG_CMD_PING 0x0004000000000000ULL /* ping support */ +#define CFG_CMD_MMC 0x0008000000000000ULL /* MMC support */ +#define CFG_CMD_FAT 0x0010000000000000ULL /* FAT support */ +#define CFG_CMD_IMLS 0x0020000000000000ULL /* List all found images */ +#define CFG_CMD_ITEST 0x0040000000000000ULL /* Integer (and string) test */ +#define CFG_CMD_NFS 0x0080000000000000ULL /* NFS support */ +#define CFG_CMD_REISER 0x0100000000000000ULL /* Reiserfs support */ +#define CFG_CMD_CDP 0x0200000000000000ULL /* Cisco Discovery Protocol */ +#define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */ +#define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */ +#define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */ +#define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */ +#define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */ +#define CFG_CMD_ONENAND 0x8000000000000000ULL /* OneNAND support */ + +#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */ + +/* Commands that are considered "non-standard" for some reason + * (memory hogs, requires special hardware, not fully tested, etc.) + */ +#define CFG_CMD_NONSTD (CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_CACHE | \ + CFG_CMD_CDP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FDC | \ + CFG_CMD_FAT | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_IMMAP | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_MII | \ + CFG_CMD_MMC | \ + CFG_CMD_NAND | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_PING | \ + CFG_CMD_PORTIO | \ + CFG_CMD_REGINFO | \ + CFG_CMD_REISER | \ + CFG_CMD_SAVES | \ + CFG_CMD_SCSI | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP | \ + CFG_CMD_SPI | \ + CFG_CMD_UNIVERSE | \ + CFG_CMD_USB | \ + CFG_CMD_ONENAND | \ + CFG_CMD_VFD ) + +/* Default configuration + */ +#define CONFIG_CMD_DFL (CFG_CMD_ALL & ~CFG_CMD_NONSTD) + +#ifndef CONFIG_COMMANDS +#define CONFIG_COMMANDS CONFIG_CMD_DFL +#endif + + +/* + * optional BOOTP fields + */ + +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_NISDOMAIN 0x00000008 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 +#define CONFIG_BOOTP_BOOTFILESIZE 0x00000020 +#define CONFIG_BOOTP_DNS 0x00000040 +#define CONFIG_BOOTP_DNS2 0x00000080 +#define CONFIG_BOOTP_SEND_HOSTNAME 0x00000100 +#define CONFIG_BOOTP_NTPSERVER 0x00000200 +#define CONFIG_BOOTP_TIMEOFFSET 0x00000400 + +#define CONFIG_BOOTP_VENDOREX 0x80000000 + +#define CONFIG_BOOTP_ALL (~CONFIG_BOOTP_VENDOREX) + + +#define CONFIG_BOOTP_DEFAULT (CONFIG_BOOTP_SUBNETMASK | \ + CONFIG_BOOTP_GATEWAY | \ + CONFIG_BOOTP_HOSTNAME | \ + CONFIG_BOOTP_BOOTPATH) + +#ifndef CONFIG_BOOTP_MASK +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +#endif + +#endif /* _CMD_CONFIG_H */ diff --git a/include/command.h b/include/command.h index 4a27e9724..a2936ad8b 100644 --- a/include/command.h +++ b/include/command.h @@ -27,8 +27,6 @@ #ifndef __COMMAND_H #define __COMMAND_H -#include - #ifndef NULL #define NULL 0 #endif @@ -76,7 +74,7 @@ extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int * * void function (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); */ -typedef void command_t (cmd_tbl_t *, int, int, char *[]); +typedef void command_t (cmd_tbl_t *, int, int, char *[]); #endif /* __ASSEMBLY__ */ @@ -86,6 +84,12 @@ typedef void command_t (cmd_tbl_t *, int, int, char *[]); #define CMD_FLAG_REPEAT 0x0001 /* repeat last command */ #define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */ +/* + * Configurable monitor commands definitions have been moved + * to include/cmd_confdefs.h + */ + + #define Struct_Section __attribute__ ((unused,section (".u_boot_cmd"))) #ifdef CFG_LONGHELP diff --git a/include/common.h b/include/common.h index 2fcb1fd37..925361c98 100644 --- a/include/common.h +++ b/include/common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2007 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -38,7 +38,7 @@ typedef volatile unsigned char vu_char; #include #include #include -#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) +#if defined(CONFIG_PCI) && defined(CONFIG_440) #include #endif #if defined(CONFIG_8xx) @@ -65,9 +65,6 @@ typedef volatile unsigned char vu_char; #include #elif defined(CONFIG_MPC5xxx) #include -#elif defined(CONFIG_MPC512X) -#include -#include #elif defined(CONFIG_MPC8220) #include #elif defined(CONFIG_8260) @@ -82,10 +79,6 @@ typedef volatile unsigned char vu_char; #endif #include #endif -#ifdef CONFIG_MPC86xx -#include -#include -#endif #ifdef CONFIG_MPC85xx #include #include @@ -103,9 +96,6 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_ARM #define asmlinkage /* nothing */ #endif -#ifdef CONFIG_BLACKFIN -#include -#endif #include #include @@ -119,12 +109,6 @@ typedef volatile unsigned char vu_char; #define debugX(level,fmt,args...) #endif /* DEBUG */ -#define BUG() do { \ - printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ - panic("BUG!"); \ -} while (0) -#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) - typedef void (interrupt_handler_t)(void *); #include /* boot information for Linux kernel */ @@ -132,21 +116,20 @@ typedef void (interrupt_handler_t)(void *); /* * enable common handling for all TQM8xxL/M boards: - * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards + * - CONFIG_TQM8xxM will be defined for all TQM8xxM and TQM885D boards * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards - * and for the TQM885D board */ #if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \ defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) + defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) || \ + defined(CONFIG_TQM885D) # ifndef CONFIG_TQM8xxM # define CONFIG_TQM8xxM # endif #endif #if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \ defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \ - defined(CONFIG_TQM885D) + defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) # ifndef CONFIG_TQM8xxL # define CONFIG_TQM8xxL # endif @@ -176,17 +159,6 @@ typedef void (interrupt_handler_t)(void *); (__x > __y) ? __x : __y; }) -/** - * container_of - cast a member of a structure out to the containing structure - * @ptr: the pointer to the member. - * @type: the type of the container struct this is embedded in. - * @member: the name of the member within the struct. - * - */ -#define container_of(ptr, type, member) ({ \ - const typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) - /* * Function Prototypes */ @@ -202,53 +174,49 @@ int serial_buffered_tstc (void); void hang (void) __attribute__ ((noreturn)); /* */ -phys_size_t initdram (int); +long int initdram (int); int display_options (void); -void print_size (phys_size_t, const char *); -int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen); +void print_size (ulong, const char *); /* common/main.c */ void main_loop (void); int run_command (const char *cmd, int flag); int readline (const char *const prompt); -int readline_into_buffer (const char *const prompt, char * buffer); -int parse_line (char *, char *[]); void init_cmd_timeout(void); void reset_cmd_timeout(void); /* lib_$(ARCH)/board.c */ -void board_init_f (ulong) __attribute__ ((noreturn)); -void board_init_r (gd_t *, ulong) __attribute__ ((noreturn)); +void board_init_f (ulong); +void board_init_r (gd_t *, ulong); int checkboard (void); int checkflash (void); int checkdram (void); char * strmhz(char *buf, long hz); int last_stage_init(void); extern ulong monitor_flash_len; -int mac_read_from_eeprom(void); /* common/flash.c */ void flash_perror (int); /* common/cmd_autoscript.c */ -int autoscript (ulong addr, const char *fit_uname); +int autoscript (ulong addr); + +/* common/cmd_bootm.c */ +void print_image_hdr (image_header_t *hdr); extern ulong load_addr; /* Default Load Address */ +extern ulong load_size; /* last loaded size */ /* common/cmd_nvedit.c */ int env_init (void); void env_relocate (void); -int envmatch (uchar *, int); char *getenv (char *); int getenv_r (char *name, char *buf, unsigned len); int saveenv (void); #ifdef CONFIG_PPC /* ARM version to be fixed! */ -int inline setenv (char *, char *); +void inline setenv (char *, char *); #else -int setenv (char *, char *); -#ifdef CONFIG_HAS_UID -void forceenv (char *, char *); -#endif +void setenv (char *, char *); #endif /* CONFIG_PPC */ #ifdef CONFIG_ARM # include @@ -267,11 +235,10 @@ void pci_init (void); void pci_init_board(void); void pciinfo (int, int); -#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) +#if defined(CONFIG_PCI) && defined(CONFIG_440) +# if defined(CFG_PCI_PRE_INIT) int pci_pre_init (struct pci_controller * ); -#endif - -#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX)) +# endif # if defined(CFG_PCI_TARGET_INIT) void pci_target_init (struct pci_controller *); # endif @@ -279,11 +246,6 @@ void pciinfo (int, int); void pci_master_init (struct pci_controller *); # endif int is_pci_host (struct pci_controller *); -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_405EX) - void pcie_setup_hoses(int busno); -#endif #endif int misc_init_f (void); @@ -292,11 +254,8 @@ int misc_init_r (void); /* common/exports.c */ void jumptable_init(void); -/* api/api.c */ -void api_init (void); - /* common/memsize.c */ -long get_ram_size (volatile long *, long); +int get_ram_size (volatile long *, long); /* $(BOARD)/$(BOARD).c */ void reset_phy (void); @@ -346,8 +305,7 @@ void board_ether_init (void); #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_MBX) || \ defined(CONFIG_IAD210) || defined(CONFIG_XPEDITE1K) || \ - defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) || \ - defined(CONFIG_V38B) + defined(CONFIG_METROBOX) || defined(CONFIG_KAREF) void board_get_enetaddr (uchar *addr); #endif @@ -399,7 +357,7 @@ void icache_disable(void); int dcache_status (void); void dcache_enable (void); void dcache_disable(void); -void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn)); +void relocate_code (ulong, gd_t *, ulong); ulong get_endaddr (void); void trap_init (ulong); #if defined (CONFIG_4xx) || \ @@ -410,7 +368,6 @@ void trap_init (ulong); defined (CONFIG_74xx) || \ defined (CONFIG_MPC8220) || \ defined (CONFIG_MPC85xx) || \ - defined (CONFIG_MPC86xx) || \ defined (CONFIG_MPC83XX) unsigned char in8(unsigned int); void out8(unsigned int, unsigned char); @@ -427,15 +384,6 @@ void ppcDcbi(unsigned long value); void ppcSync(void); void ppcDcbz(unsigned long value); #endif -#if defined (CONFIG_MICROBLAZE) -unsigned short in16(unsigned int); -void out16(unsigned int, unsigned short value); -#endif - -#if defined (CONFIG_MPC83XX) -void ppcDWload(unsigned int *addr, unsigned int *ret); -void ppcDWstore(unsigned int *addr, unsigned int *value); -#endif /* $(CPU)/cpu.c */ int checkcpu (void); @@ -444,13 +392,6 @@ int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); void reset_cpu (ulong addr); -#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) -void ft_cpu_setup(void *blob, bd_t *bd); -#ifdef CONFIG_PCI -void ft_pci_setup(void *blob, bd_t *bd); -#endif -#endif - /* $(CPU)/serial.c */ int serial_init (void); @@ -476,12 +417,11 @@ int sdram_adjust_866 (void); int adjust_sdram_tbs_8xx (void); #if defined(CONFIG_8260) int prt_8260_clks (void); +#elif defined(CONFIG_MPC83XX) +int print_clock_conf(void); #elif defined(CONFIG_MPC5xxx) int prt_mpc5xxx_clks (void); #endif -#if defined(CONFIG_MPC512X) -int prt_mpc512xxx_clks (void); -#endif #if defined(CONFIG_MPC8220) int prt_mpc8220_clks (void); #endif @@ -490,8 +430,6 @@ ulong get_OPB_freq (void); ulong get_PCI_freq (void); #endif #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X) -void s3c2410_irq(void); -#define ARM920_IRQ_CALLBACK s3c2410_irq ulong get_FCLK (void); ulong get_HCLK (void); ulong get_PCLK (void); @@ -517,22 +455,18 @@ ulong get_bus_freq (ulong); #if defined(CONFIG_MPC85xx) typedef MPC85xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); -ulong get_ddr_freq (ulong); -#endif -#if defined(CONFIG_MPC86xx) -typedef MPC86xx_SYS_INFO sys_info_t; -void get_sys_info ( sys_info_t * ); #endif #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) # if defined(CONFIG_440) + typedef PPC440_SYS_INFO sys_info_t; # if defined(CONFIG_440SPE) unsigned long determine_sysper(void); unsigned long determine_pci_clock_per(void); # endif +# else + typedef PPC405_SYS_INFO sys_info_t; # endif -typedef PPC4xx_SYS_INFO sys_info_t; -int ppc440spe_revB(void); void get_sys_info ( sys_info_t * ); #endif @@ -540,15 +474,13 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_8xx) || defined(CONFIG_8260) void cpu_init_f (volatile immap_t *immr); #endif -#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) void cpu_init_f (void); #endif int cpu_init_r (void); #if defined(CONFIG_8260) int prt_8260_rsr (void); -#elif defined(CONFIG_MPC83XX) -int prt_83xx_rsr (void); #endif /* $(CPU)/interrupts.c */ @@ -607,16 +539,13 @@ ulong simple_strtoul(const char *cp,char **endp,unsigned int base); unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); #endif long simple_strtol(const char *cp,char **endp,unsigned int base); -void panic(const char *fmt, ...) - __attribute__ ((format (__printf__, 1, 2))); -int sprintf(char * buf, const char *fmt, ...) - __attribute__ ((format (__printf__, 2, 3))); +void panic(const char *fmt, ...); +int sprintf(char * buf, const char *fmt, ...); int vsprintf(char *buf, const char *fmt, va_list args); /* lib_generic/crc32.c */ -uint32_t crc32 (uint32_t, const unsigned char *, uint); -uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); -uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint); +ulong crc32 (ulong, const unsigned char *, uint); +ulong crc32_no_comp (ulong, const unsigned char *, uint); /* common/console.c */ int console_init_f(void); /* Before relocation; uses the serial stuff */ @@ -632,8 +561,7 @@ int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */ */ /* serial stuff */ -void serial_printf (const char *fmt, ...) - __attribute__ ((format (__printf__, 1, 2))); +void serial_printf (const char *fmt, ...); /* stdin */ int getc(void); @@ -642,8 +570,7 @@ int tstc(void); /* stdout */ void putc(const char c); void puts(const char *s); -void printf(const char *fmt, ...) - __attribute__ ((format (__printf__, 1, 2))); +void printf(const char *fmt, ...); void vprintf(const char *fmt, va_list args); /* stderr */ @@ -660,8 +587,7 @@ void vprintf(const char *fmt, va_list args); #define stderr 2 #define MAX_FILES 3 -void fprintf(int file, const char *fmt, ...) - __attribute__ ((format (__printf__, 2, 3))); +void fprintf(int file, const char *fmt, ...); void fputs(int file, const char *s); void fputc(int file, const char c); int ftstc(int file); @@ -669,36 +595,15 @@ int fgetc(int file); int pcmcia_init (void); -#ifdef CONFIG_STATUS_LED -# include +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress (int status); #endif -/* - * Board-specific Platform code can reimplement show_boot_progress () if needed - */ -void __attribute__((weak)) show_boot_progress (int val); #ifdef CONFIG_INIT_CRITICAL -#error CONFIG_INIT_CRITICAL is deprecated! +#error CONFIG_INIT_CRITICAL is depracted! #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. #endif #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) -#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) - -#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) - -/* Multicore arch functions */ -#ifdef CONFIG_MP -int cpu_status(int nr); -int cpu_reset(int nr); -int cpu_release(int nr, int argc, char *argv[]); -#endif - -#ifdef CONFIG_POST -#define CONFIG_HAS_POST -#endif - #endif /* __COMMON_H_ */ diff --git a/include/commproc.h b/include/commproc.h index 0a4e817fa..12400e3ed 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -159,8 +159,6 @@ typedef struct smc_uart { ushort smc_brkec; /* rcv'd break condition counter */ ushort smc_brkcr; /* xmt break count register */ ushort smc_rmask; /* Temporary bit mask */ - u_char res1[8]; - ushort smc_rpbase; /* Relocation pointer */ } smc_uart_t; /* Function code bits. @@ -786,19 +784,19 @@ typedef struct scc_enet { #undef SCC_ENET #define FEC_ENET -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ #endif /* CONFIG_GEN860T */ @@ -1122,32 +1120,6 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x0000003d) #endif /* CONFIG_MBX */ -/*** MGSUVD *********************************************************/ - -/* The MGSUVD Service Module uses SCC3 for Ethernet */ - -#ifdef CONFIG_MGSUVD -#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ -#define CPM_CR_ENET CPM_CR_CH_SCC3 -#define SCC_ENET 2 -#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ -#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ -#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ -#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ - -#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ - -#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ -#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ - -/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to - * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. - */ -#define SICR_ENET_MASK ((uint)0x00FF0000) -#define SICR_ENET_CLKRT ((uint)0x00250000) -#endif /* CONFIG_MGSUVD */ - - /*** MHPC ********************************************************/ #if defined(CONFIG_MHPC) @@ -1448,9 +1420,7 @@ typedef struct scc_enet { */ #define PROFF_ENET PROFF_SCC2 #define CPM_CR_ENET CPM_CR_CH_SCC2 -#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */ #define SCC_ENET 1 -#endif #define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ #define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ diff --git a/include/configs/A3000.h b/include/configs/A3000.h index dba1bf727..ca9592c23 100644 --- a/include/configs/A3000.h +++ b/include/configs/A3000.h @@ -52,20 +52,23 @@ #define CONFIG_BOOTDELAY 5 +#if 0 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_FLASH | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_NET | \ + CFG_CMD_PCI ) +#endif -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -/* - * Command line configuration. - */ -#include +#include /* @@ -87,7 +90,7 @@ *----------------------------------------------------------------------- */ #define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -95,9 +98,9 @@ * PCI stuff *----------------------------------------------------------------------- */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ #define CONFIG_NET_MULTI /* Multi ethernet cards support */ @@ -120,11 +123,11 @@ * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ -#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ -#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM +#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ +#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ +#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the @@ -170,7 +173,7 @@ * Definitions for initial stack pointer and data area */ -/* #define CFG_MONITOR_BASE TEXT_BASE */ +/* #define CFG_MONITOR_BASE TEXT_BASE */ /*#define CFG_GBL_DATA_SIZE 256*/ #define CFG_GBL_DATA_SIZE 128 #define CFG_INIT_RAM_ADDR 0x40000000 @@ -192,7 +195,7 @@ */ #define CFG_ROMNAL 7 #define CFG_ROMFAL 11 -#define CFG_DBUS_SIZE 0x3 +#define CFG_DBUS_SIZE 0x3 /* Bit-field values for MCCR2. */ @@ -218,7 +221,7 @@ #define CFG_EXTROM 1 #define CFG_REGDIMM 0 -#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ +#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ @@ -306,7 +309,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h index 5d28168fb..821efe5d4 100644 --- a/include/configs/ADCIOP.h +++ b/include/configs/ADCIOP.h @@ -59,32 +59,21 @@ #define CONFIG_IPADDR 10.0.18.222 #define CONFIG_SERVERIP 10.0.18.190 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_ASKENV ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ASKENV - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -191,6 +180,15 @@ #define CFG_ETH_DEV_FN 0x0000 #define CFG_ETH_IOBASE 0x0fff0000 +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ +#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h index 01ee72b8b..2efca1056 100644 --- a/include/configs/ADNPESC1.h +++ b/include/configs/ADNPESC1.h @@ -81,9 +81,9 @@ * appropriately -- this is very important if you plan to move your * memory to another place as configured at this time !!!). * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ @@ -401,8 +401,15 @@ #define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */ #define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */ +#define __SPI_CMD_OFF 0 /* allow default commands: */ + /* CFG_CMD_SPI */ + /* CFG_CMD_DATE */ + #else #undef CONFIG_NIOS_SPI /* NO SPI support */ +#define __SPI_CMD_OFF ( CFG_CMD_SPI \ + | CFG_CMD_DATE \ + ) #endif /*------------------------------------------------------------------------ @@ -563,47 +570,45 @@ #define CONFIG_POST CFG_POST_RTC #define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_CACHE | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_MMC | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_SCSI | \ + CFG_CMD_VFD | \ + CFG_CMD_USB | \ + CFG_CMD_XIMG | \ + __SPI_CMD_OFF ) ) -/* - * Command line configuration. - */ -#include -#define CONFIG_CMD_BSP -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REISER -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG - -#if (CFG_NIOS_CPU_SPI_NUMS == 1) -#define CONFIG_CMD_DATE -#define CONFIG_CMD_SPI -#endif +#include /*------------------------------------------------------------------------ * KGDB *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 9600 #endif @@ -646,6 +651,7 @@ #undef CFG_LOAD_ADDR /* force error break */ #endif + /* MEM test area */ #if (CFG_SDRAM_SIZE != 0) diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h index c8428b4e7..55210ebd3 100644 --- a/include/configs/ADNPESC1_base_32.h +++ b/include/configs/ADNPESC1_base_32.h @@ -370,10 +370,10 @@ #define CFG_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */ #define CFG_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */ -#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */ +#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */ #define CFG_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */ -#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */ +#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */ /* memory accessibility */ #undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h index f677b9c80..df2096564 100644 --- a/include/configs/ADS860.h +++ b/include/configs/ADS860.h @@ -37,21 +37,15 @@ #define CONFIG_DRAM_50MHZ 1 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_PCMCIA \ + | CFG_CMD_PING \ + ) -/* - * Command line configuration. - */ -#include -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_PING - -/* This is picked up again in fads.h */ -#define FADS_COMMANDS_ALREADY_DEFINED - -#include "../../board/fads/fads.h" +#include "fads.h" #define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h index 035ebc693..14d56bfd9 100644 --- a/include/configs/AMX860.h +++ b/include/configs/AMX860.h @@ -61,25 +61,7 @@ #undef CONFIG_BOOTARGS -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -88,22 +70,29 @@ #endif -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_SUBNETMASK +#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ + +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -115,7 +104,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -207,7 +196,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h index baa974103..ba4b1a2bc 100644 --- a/include/configs/AP1000.h +++ b/include/configs/AP1000.h @@ -22,6 +22,8 @@ * (easy to change) */ +#undef DEBUG + #define CONFIG_405 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ @@ -64,28 +66,18 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_IRQ | \ + CFG_CMD_MVENV | \ + CFG_CMD_PCI | \ + CFG_CMD_PING \ + ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MVENV -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -97,7 +89,7 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -191,6 +183,14 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Init Memory Controller: @@ -228,7 +228,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 2f266a242..3df99a008 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -1,7 +1,4 @@ /* - * (C) Copyright 2005-2008 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * * (C) Copyright 2001-2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * @@ -27,6 +24,7 @@ /* * board/config.h - configuration options, board specific */ + #ifndef __CONFIG_H #define __CONFIG_H @@ -34,188 +32,145 @@ * High Level Configuration Options * (easy to change) */ + #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_APCG405 1 /* ...on a APC405 board */ +#define CONFIG_APCG405 1 /* ...on a APC405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ -#define CONFIG_BOARD_EARLY_INIT_R 1 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */ -#define CONFIG_BOOTCOUNT_LIMIT 1 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS - -#define CFG_USB_LOAD_COMMAND "fatload usb 0 200000 pImage;" \ - "fatload usb 0 300000 pImage.initrd" -#define CFG_USB_SELF_COMMAND "usb start;run usb_load;usb stop;" \ - "run ramargs addip addcon usbargs;" \ - "bootm 200000 300000" -#define CFG_USB_ARGS "setenv bootargs $(bootargs) usbboot=1" -#define CFG_BOOTLIMIT "3" -#define CFG_ALT_BOOTCOMMAND "run usb_self;reset" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=abg405\0" \ - "bd_type=abg405\0" \ - "serial#=AA0000\0" \ - "kernel_addr=fe000000\0" \ - "ramdisk_addr=fe100000\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname)::off panic=1\0" \ - "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)" \ - " $(optargs)\0" \ - "flash_self=run ramargs addip addcon;" \ - "bootm $(kernel_addr) $(ramdisk_addr)\0" \ - "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;" \ - "bootm\0" \ - "rootpath=/tftpboot/abg405/target_root\0" \ - "img=/tftpboot/abg405/pImage\0" \ - "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 100000 fff80000 80000\0" \ - "ipaddr=10.0.111.111\0" \ - "netmask=255.255.0.0\0" \ - "serverip=10.0.0.190\0" \ - "splashimage=ffe80000\0" \ - "usb_load="CFG_USB_LOAD_COMMAND"\0" \ - "usb_self="CFG_USB_SELF_COMMAND"\0" \ - "usbargs="CFG_USB_ARGS"\0" \ - "bootlimit="CFG_BOOTLIMIT"\0" \ - "altbootcmd="CFG_ALT_BOOTCOMMAND"\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self;reset" - -#define CONFIG_ETHADDR 00:02:27:8e:00:00 +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm ffc00000 ffca0000" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm ffc00000" +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_NET_MULTI 1 -#undef CONFIG_HAS_ETH1 - #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_USB -#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via CF or USB */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#undef CFG_HUSH_PARSER /* use "hush" command parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#if 1 /* test-only */ #define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ +#else +#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ +#define CFG_BASE_BAUD 691200 +#endif /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ /* Only interrupt boot if space is pressed */ /* If a long serial cable is connected but */ /* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay -#undef CONFIG_AUTOBOOT_DELAY_STR +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ -/* +/*----------------------------------------------------------------------- * PCI stuff + *----------------------------------------------------------------------- */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_SKIP_HOST_BRIDGE 1 +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ + #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ @@ -226,123 +181,119 @@ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -/* +/*----------------------------------------------------------------------- * IDE/ATA stuff + *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS) /* max. 1 drives per IDE bus */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ -/* +/*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_MONITOR_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */ +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Init. Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/* +/*----------------------------------------------------------------------- * FLASH organization */ -#ifndef __ASSEMBLY__ -extern int flash_banks; -#endif +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_BASE 0xFE000000 /* test-only...*/ +#define CFG_FLASH_INCREMENT 0x01000000 /* test-only */ -#define CFG_FLASH_BASE 0xFE000000 -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CFG_MAX_FLASH_BANKS flash_banks /* max num of flash banks */ - /* updated in board_early_init_r */ -#define CFG_MAX_FLASH_BANKS_DETECT 2 -#define CFG_FLASH_QUIET_TEST 1 -#define CFG_FLASH_INCREMENT 0x01000000 -#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ -#define CFG_FLASH_AUTOPROTECT_LIST { \ - {0xfe000000, 0x500000}, \ - {0xffe80000, 0x180000} \ - } -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BANKS_LIST { \ - CFG_FLASH_BASE, \ - CFG_FLASH_BASE + CFG_FLASH_INCREMENT \ - } -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/* +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */ + +/*----------------------------------------------------------------------- * Environment Variable setup */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the */ - /* beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ -#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting vendor vars */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ -/* +/*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/* +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ -#define FLASH0_BA (CFG_FLASH_BASE + CFG_FLASH_INCREMENT) /* FLASH 0 BA */ -#define FLASH1_BA CFG_FLASH_BASE /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define PS2_BA 0xF0000600 /* PS/2 Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ -#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */ -#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */ -#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */ -#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */ -#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ +#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ +#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define DUART0_BA 0xF0000400 /* DUART Base Address */ +#define DUART1_BA 0xF0000408 /* DUART Base Address */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ +#define PS2_BA 0xF0000600 /* PS/2 Base Address */ +#define CF_BA 0xF0100000 /* CompactFlash Base Address */ +#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */ +#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */ +#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */ +#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */ +#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ -#define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */ +#define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */ -/* Memory Bank 0 (Flash Bank 0) initialization */ +/* Memory Bank 0 (Flash Bank 0) initialization */ #define CFG_EBC_PB0AP 0x92015480 #define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ -#define CFG_EBC_PB0AP_HWREV8 CFG_EBC_PB0AP -#define CFG_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */ -/* Memory Bank 1 (Flash Bank 1) initialization */ +/* Memory Bank 1 (Flash Bank 1) initialization */ #define CFG_EBC_PB1AP 0x92015480 #define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ @@ -366,7 +317,7 @@ extern int flash_banks; #define CFG_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ #define CFG_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/ -/* +/*----------------------------------------------------------------------- * FPGA stuff */ @@ -389,61 +340,48 @@ extern int flash_banks; #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ -/* +/*----------------------------------------------------------------------- * LCD Setup */ -#define CFG_LCD_BIG_MEM (VGA_BA + 0x200000) /* S1D13806 Mem Base */ -#define CFG_LCD_BIG_REG VGA_BA /* S1D13806 Reg Base */ -#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */ +#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ +#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ + +#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */ /* Image information... */ -#define CONFIG_LCD_USED CONFIG_LCD_BIG +#define CONFIG_LCD_USED CONFIG_LCD_BIG +#define CFG_LCD_HEADER_NAME "../common/s1d13806_640_480_16bpp.h" +#define CFG_LCD_LOGO_NAME "logo_640_480_24bpp.c" -#define CFG_LCD_MEM CFG_LCD_BIG_MEM -#define CFG_LCD_REG CFG_LCD_BIG_REG +#define CFG_LCD_MEM CFG_LCD_BIG_MEM +#define CFG_LCD_REG CFG_LCD_BIG_REG #define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20) -/* +/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 +#define CFG_TEMP_STACK_OCM 1 /* On Chip Memory location */ #define CFG_OCM_DATA_ADDR 0xF8000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* reserved bytes for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -/* reserve some memory for BOOT limit info */ -#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) - -#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ -#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 8) -#endif +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /* * Internal Definitions * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -/* - * PCI OHCI controller - */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_PCI_OHCI 1 -#define CFG_OHCI_SWAP_REG_ACCESS 1 -#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 -#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" -#define CONFIG_USB_STORAGE 1 -#define CFG_USB_OHCI_BOARD_INIT 1 - -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 06023819f..1cd0280e2 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -71,29 +71,17 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_BSP ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -104,7 +92,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -208,11 +196,21 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR 0xFFFB0000 /* Address of Environment Sector*/ #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ -#define CFG_ENV_SIZE 0x04000 /* Size of Environment */ +#define CFG_ENV_SIZE 0x04000 /* Size of Environment */ #define CFG_ENV_ADDR_REDUND 0xFFFA0000 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 85c6a992d..d03c05bf3 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -53,41 +53,25 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_NET_MULTI 1 -#undef CONFIG_HAS_ETH1 - #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -107,7 +91,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -148,18 +132,40 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } -#define NAND_MAX_CHIPS 1 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_LEGACY -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CFG_NAND_QUIET 1 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- * PCI stuff @@ -258,6 +264,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/Adder.h b/include/configs/Adder.h index cefdd2960..0e6b50f8b 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -37,12 +37,9 @@ #define CONFIG_ETHER_ON_FEC1 #define CONFIG_ETHER_ON_FEC2 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) #define CFG_DISCOVER_PHY -#define CONFIG_MII_INIT 1 #define FEC_ENET #endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ @@ -55,26 +52,15 @@ #define CFG_8xx_CPUCLK_MAX 133000000 #endif /* CONFIG_MPC852T */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - +/* This must be included AFTER the definition of CONFIG_COMMANDS */ +#include #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ @@ -131,7 +117,7 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 KB for Monitor */ #ifdef CONFIG_BZIP2 #define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ #else @@ -149,7 +135,7 @@ /* Environment is in flash */ #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CONFIG_ENV_OVERWRITE @@ -191,16 +177,16 @@ #define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) /* PISCR - Periodic Interrupt Status and Control */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CFG_PISCR (PISCR_PS | PISCR_PITF) /* PLPRCR - PLL, Low-Power, and Reset Control Register */ -/* #define CFG_PLPRCR PLPRCR_TEXPS */ +/* #define CFG_PLPRCR PLPRCR_TEXPS */ /* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 +#define SCCR_MASK SCCR_EBDF11 #define CFG_SCCR SCCR_RTSEL -#define CFG_DER 0 +#define CFG_DER 0 /*----------------------------------------------------------------------- * Cache Configuration @@ -215,8 +201,4 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h index 38b962f82..c08b2c39f 100644 --- a/include/configs/Alaska8220.h +++ b/include/configs/Alaska8220.h @@ -31,8 +31,6 @@ #define CONFIG_MPC8220 1 #define CONFIG_ALASKA8220 1 /* ... on Alaska board */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ @@ -41,6 +39,12 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Serial console configuration */ @@ -66,40 +70,31 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) #define CONFIG_NET_MULTI #define CONFIG_MII +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Autobooting */ @@ -287,7 +282,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -303,11 +298,6 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Various low-level settings */ diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h index 84efd2fe0..ea50f4150 100644 --- a/include/configs/AmigaOneG3SE.h +++ b/include/configs/AmigaOneG3SE.h @@ -54,48 +54,40 @@ #undef CONFIG_CLOCKS_IN_MHZ /* clocks passed to Linux in Hz */ -#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk_size=4096" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096" +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_AMIGA_PARTITION +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_NET | \ + CFG_CMD_IDE | \ + CFG_CMD_FDC | \ + CFG_CMD_CACHE | \ + CFG_CMD_CONSOLE| \ + CFG_CMD_USB | \ + CFG_CMD_BSP | \ + CFG_CMD_PCI ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NET -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FDC -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CONSOLE| -#define CONFIG_CMD_USB -#define CONFIG_CMD_BSP -#define CONFIG_CMD_PCI - +/* CFG_CMD_MII | \ */ #define CONFIG_PCI 1 /* #define CONFIG_PCI_SCAN_SHOW 1 */ #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -#define atoi(x) simple_strtoul(x,NULL,10) +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + /* * Miscellaneous configurable options @@ -255,7 +247,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -356,6 +348,8 @@ #define CONFIG_3COM /* #define CONFIG_BOOTP_RANDOM_DELAY */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) /* * USB configuration @@ -371,8 +365,7 @@ #define CONFIG_BOOTDELAY 5 /* Boot automatically after five seconds */ #define CONFIG_PREBOOT "" #define CONFIG_BOOTCOMMAND "fdcboot; diskboot" -#define CONFIG_MENUPROMPT \ - "Press any key to interrupt autoboot: %2d ", bootdelay +#define CONFIG_MENUPROMPT "Press any key to interrupt autoboot: %2d " #define CONFIG_MENUKEY ' ' #define CONFIG_MENUCOMMAND "menu" /* #define CONFIG_AUTOBOOT_KEYED */ diff --git a/include/configs/B2.h b/include/configs/B2.h index d6ab1adeb..e55858d34 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -37,7 +37,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_B2 1 /* on an B2 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ @@ -72,26 +72,16 @@ #define CONFIG_BAUDRATE 115200 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 5 #define CONFIG_ETHADDR 00:50:c2:1e:af:fb diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index 8ec70aa63..46bdfa2ee 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -28,6 +28,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#undef DEBUG #define GTREGREAD(x) 0xffffffff /* needed for debug */ /* @@ -65,30 +66,14 @@ #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_SCSI -#define CONFIG_CMD_IDE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_FDC -#define CONFIG_CMD_ELF +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\ + CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\ + CFG_CMD_FDC | CFG_CMD_ELF) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -101,7 +86,7 @@ */ #define CONFIG_CONS_INDEX 1 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -451,7 +436,7 @@ extern unsigned long bab7xx_get_gclk_freq (void); * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index b7574bf14..5b54f30e0 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -61,7 +61,10 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -89,7 +92,6 @@ # define CONFIG_PCI 1 # define CONFIG_PCI_PNP 1 /* #define CONFIG_PCI_SCAN_SHOW 1 */ -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_PCI_MEM_BUS 0x40000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -104,6 +106,12 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 +#ifdef CONFIG_PCI +# define ADD_PCI_CMD CFG_CMD_PCI +#else +# define ADD_PCI_CMD 0 +#endif + /* * Video console */ @@ -118,6 +126,12 @@ # define CONFIG_SPLASH_SCREEN # define CFG_CONSOLE_IS_IN_ENV +#ifdef CONFIG_VIDEO +# define ADD_BMP_CMD CFG_CMD_BMP +#else +# define ADD_BMP_CMD 0 +#endif + /* * Partitions */ @@ -130,7 +144,10 @@ */ #ifdef CONFIG_BC3450_USB # define CONFIG_USB_OHCI +# define ADD_USB_CMD CFG_CMD_USB # define CONFIG_USB_STORAGE +#else /* !CONFIG_BC3450_USB */ +# define ADD_USB_CMD 0 #endif /* CONFIG_BC3450_USB */ /* @@ -141,69 +158,66 @@ CFG_POST_I2C) #ifdef CONFIG_POST +# define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 +#else +# define CFG_CMD_POST_DIAG 0 #endif /* CONFIG_POST */ - /* - * BOOTP options + * IDE */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_BSP - -#ifdef CONFIG_VIDEO - #define CONFIG_CMD_BMP -#endif - #ifdef CONFIG_BC3450_IDE - #define CONFIG_CMD_IDE -#endif +# define ADD_IDE_CMD CFG_CMD_IDE +#else +# define ADD_IDE_CMD 0 +#endif /* CONFIG_BC3450_IDE */ -#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB) - #ifdef CONFIG_FAT - #define CONFIG_CMD_FAT - #endif +/* + * Filesystem support + */ +#if defined (CONFIG_BC3450_IDE) || defined (CONFIG_BC3450_USB) +#ifdef CONFIG_FAT +# define ADD_FAT_CMD CFG_CMD_FAT +#else +# define ADD_FAT_CMD 0 +#endif /* CONFIG_FAT */ - #ifdef CONFIG_EXT2 - #define CONFIG_CMD_EXT2 - #endif -#endif +#ifdef CONFIG_EXT2 +# define ADD_EXT2_CMD CFG_CMD_EXT2 +#else +# define ADD_EXT2_CMD 0 +#endif /* CONFIG_EXT2 */ +#endif /* CONFIG_BC3450_IDE / _USB */ -#ifdef CONFIG_BC3450_USB - #define CONFIG_CMD_USB -#endif - -#ifdef CONFIG_PCI - #define CONFIG_CMD_PCI -#endif - -#ifdef CONFIG_POST - #define CONFIG_CMD_DIAG -#endif +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_BMP_CMD | \ + ADD_IDE_CMD | \ + ADD_FAT_CMD | \ + ADD_EXT2_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP | \ + CFG_CMD_BSP) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -218,7 +232,7 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo;" #undef CONFIG_BOOTARGS @@ -268,17 +282,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet + * hasn't been tested with a IPB Bus Clock of 66 MHz. */ -#if defined(CFG_IPBCLK_EQUALS_XLBCLK) -# define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ +#if defined(CFG_IPBSPEED_133) +# define CFG_PCISPEED_66 /* define for 66MHz speed */ #endif /* @@ -436,7 +450,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -455,13 +469,9 @@ #define CFG_HZ 1000 /* dec freq: 1ms ticks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* - * Enable loopw command. + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) */ #define CONFIG_LOOPW @@ -478,7 +488,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 +#ifdef CFG_PCISPEED_66 # define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else # define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ diff --git a/include/configs/BMW.h b/include/configs/BMW.h index bb7856f67..3bd43d836 100644 --- a/include/configs/BMW.h +++ b/include/configs/BMW.h @@ -64,35 +64,28 @@ #define CFG_DOC_SUPPORT_2000 1 #define CFG_DOC_SUPPORT_MILLENNIUM 1 #define CFG_DOC_SHORT_TIMEOUT 1 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_ELF | \ + 0 ) - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DOC -#define CONFIG_CMD_ELF - - -/* CONFIG_CMD_DOC required legacy NAND support */ +/* CFG_CMD_DOC required legacy NAND support */ #define CFG_NAND_LEGACY #if 0 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \ + CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE) + #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ #endif +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + + /* * Miscellaneous configurable options */ @@ -300,7 +293,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index 7029dbdde..e0262a8f6 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -56,26 +56,13 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \ + CFG_CMD_IRQ | \ + CFG_CMD_EEPROM ) & \ + ~CFG_CMD_NET) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_EEPROM - -#undef CONFIG_CMD_NET - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -86,7 +73,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -181,6 +168,15 @@ /* mask of address bits that overflow into the "EEPROM chip address" */ #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 1603c9c0b..7ec4599eb 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -119,36 +119,24 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ @@ -167,7 +155,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -399,8 +387,6 @@ #define CFG_ENV_ADDR_REDUND 0xFFFFA000 #define CFG_ENV_SIZE_REDUND 0x2000 -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ #define CFG_NVRAM_SIZE 242 /* NVRAM size */ @@ -427,7 +413,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -473,7 +459,7 @@ #define CONFIG_VGA_AS_SINGLE_DEVICE /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ #define CFG_ISA_IO 0xE8000000 -/* see also drivers/video/videomodes.c */ +/* see also drivers/videomodes.c */ #define CFG_DEFAULT_VIDEO_MODE 0x303 #endif diff --git a/include/configs/CCM.h b/include/configs/CCM.h index 6194c5c6e..e8994ffef 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -94,35 +94,27 @@ #define CONFIG_MAC_PARTITION /* nod used yet */ #define CONFIG_DOS_PARTITION -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +/*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -137,7 +129,7 @@ #define CFG_LOAD_ADDR 0x00100000 /* default load address */ /* Ethernet hardware configuration done using port pins */ -#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */ +#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */ #define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */ #define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ #define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 285cd5c0e..1cca2859f 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -60,35 +60,28 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_BSP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_BSP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#define CFG_NAND_LEGACY #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -107,7 +100,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -155,18 +148,36 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } -#define NAND_MAX_CHIPS 1 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CFG_NAND_QUIET 1 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- * PCI stuff @@ -272,6 +283,16 @@ #define CFG_EEPROM_WREN 1 +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index 11107d499..b882f7a9b 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -50,40 +50,31 @@ #define CONFIG_BAUDRATE 9600 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #define CONFIG_BOOTDELAY 5 -/* - * BOOTP options +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ + CFG_CMD_FLASH | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP +#include /* @@ -334,7 +325,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 58900c309..56fd9a6d3 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -54,29 +54,16 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - -#undef CONFIG_CMD_NET +#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -93,7 +80,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -223,6 +210,16 @@ #define CFG_EEPROM_WREN 1 +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index bd43e1dc9..047e2f1ee 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -55,43 +55,32 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ -#define CONFIG_NET_MULTI 1 -#undef CONFIG_HAS_ETH1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_EEPROM +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -107,7 +96,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -266,6 +255,15 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index fd49f569a..d756f447f 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -37,7 +37,6 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ -#undef CONFIG_CPCI405_6U /* enable this for 6U boards */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ @@ -57,48 +56,52 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_NET_MULTI 1 -#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) -/* - * Command line configuration. - */ -#include +#if 0 /* test-only */ +#define CONFIG_NETCONSOLE +#define CONFIG_NET_MULTI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM +#ifdef CONFIG_NET_MULTI +#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ +#endif +#endif #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT +#if 0 /* test-only */ +#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -114,7 +117,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -241,6 +244,29 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/* + * JFFS2 partitions + */ + +/* No command line, one static partition, use whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ + +/* Use first bank for JFFS2, second bank contains U-Boot. + * + * Note: fake mtd_id's used, no linux mtd map file. + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=cpci4052-0" +#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)" +*/ + #if 0 /* Use NVRAM for environment variables */ /*----------------------------------------------------------------------- * NVRAM organization @@ -279,6 +305,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 55dd6296d..852d94a41 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -57,48 +57,39 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_NET_MULTI 1 -#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_NAND_LEGACY + + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -114,7 +105,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -237,6 +228,27 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +/* + * JFFS2 partitions + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ + +/* Use first bank for JFFS2, second bank contains U-Boot. + * + * Note: fake mtd_id's used, no linux mtd map file. + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=cpci405ab-0" +#define MTDPARTS_DEFAULT "mtdparts=cpci405ab-0:-(jffs2)" +*/ + /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC32) for environment */ @@ -266,6 +278,16 @@ #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ #define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index c17353920..2260327c3 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -56,42 +56,37 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_NET_MULTI 1 -#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) -/* - * Command line configuration. - */ -#include +#if 0 /* test-only */ +#define CONFIG_NETCONSOLE +#define CONFIG_NET_MULTI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM +#ifdef CONFIG_NET_MULTI +#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ +#endif +#endif #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -100,6 +95,11 @@ #undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_NAND_LEGACY + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -115,7 +115,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -152,9 +152,8 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ /* Only interrupt boot if special string is typed */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Autobooting in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n" #undef CONFIG_AUTOBOOT_DELAY_STR #undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ #define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/ @@ -250,6 +249,27 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +/* + * JFFS2 partitions + */ +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ + +/* Use first bank for JFFS2, second bank contains U-Boot. + * + * Note: fake mtd_id's used, no linux mtd map file. + */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=cpci405dt-0" +#define MTDPARTS_DEFAULT "mtdparts=cpci405dt-0:-(jffs2)" +*/ + #if 0 /* Use NVRAM for environment variables */ /*----------------------------------------------------------------------- * NVRAM organization @@ -288,6 +308,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * @@ -385,6 +415,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + /* * Internal Definitions * diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h new file mode 100644 index 000000000..a5bc773e1 --- /dev/null +++ b/include/configs/CPCI440.h @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2002 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * board/config_CPCI440.h - configuration for esd CPCI-440 board + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_EBONY 1 /* Board is ebony */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ +#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ +#if 1 +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#else +#define CFG_MONITOR_BASE 0x01fc0000 /* start of monitor */ +#endif +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ + +#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */ +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} + +/*----------------------------------------------------------------------- + * NVRAM/RTC + * + * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. + * The DS1743 code assumes this condition (i.e. -- it assumes the base + * address for the RTC registers is: + * + * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE + * + *----------------------------------------------------------------------*/ +#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ +#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#if 1 /* test-only */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */ +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#undef CFG_FLASH_BASE +#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/ + +#else /* test-only */ + +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 32 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#endif + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#if 0 /* test-only */ +#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ +#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ +#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ + +#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_ADDR \ + (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) +#else + +#if 0 /* test-only */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ + /* total size of a CAT24WC16 is 2048 bytes */ +#else +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#endif + +/*----------------------------------------------------------------------- + * I2C EEPROM (CAT24WC16) for environment + */ +#define CONFIG_HARD_I2C /* I2c with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#endif + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BAUDRATE 9600 + +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#if 0 /* test-only */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_KGDB | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF ) +#else +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM ) +/* test-only: support fehlt bisher... */ +/* CFG_CMD_IDE | \*/ +/* CFG_CMD_PCI | \*/ +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#if 0 /* test-only */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#endif + + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#if 0 +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ + +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ + +#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* Configuration Port location */ +#define CONFIG_PORT_ADDR 0xF0000500 + +/*----------------------------------------------------------------------- + * Definitions for Serial Presence Detect EEPROM address + * (to get SDRAM settings) + */ +#define SPD_EEPROM_ADDRESS 0x50 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 89edbde1d..244e45a75 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -61,8 +61,6 @@ #undef CONFIG_ECC /* enable ECC support */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* which initialization functions to call for this board */ #define CONFIG_MISC_INIT_R #define CONFIG_BOARD_PRE_INIT @@ -76,7 +74,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " -#define CONFIG_AUTO_COMPLETE 1 +#define CFG_AUTO_COMPLETE 1 /* Define which ETH port will be used for connecting the network */ #define CFG_ETH_PORT ETH_0 @@ -135,37 +133,30 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C \ + | CFG_CMD_CACHE \ + | CFG_CMD_EEPROM \ + | CFG_CMD_PCI \ + | CFG_CMD_ELF \ + | CFG_CMD_DATE \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_IDE \ + | CFG_CMD_FAT \ + | CFG_CMD_EXT2 \ + ) #define CONFIG_DOS_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #define CONFIG_USE_CPCIDVI #ifdef CONFIG_USE_CPCIDVI @@ -188,7 +179,7 @@ #define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -594,7 +585,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index 78b754c19..93d49f386 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -54,36 +54,15 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_ELF | \ + CFG_CMD_EEPROM ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -94,7 +73,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -205,6 +184,15 @@ #define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ /* total size of a CAT24WC08 is 1024 bytes */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 10cebc99c..16a9ea5dd 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -68,7 +68,9 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ @@ -110,14 +112,14 @@ #define CONFIG_PREBOOT \ "echo; " \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \ "echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /*----------------------------------------------------------------------- @@ -161,37 +163,27 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -356,7 +348,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index 3879d9b27..7a1dada2d 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -69,7 +69,9 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ @@ -114,7 +116,7 @@ #define CONFIG_PREBOOT \ "echo; " \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \ "echo" #undef CONFIG_BOOTARGS @@ -165,31 +167,27 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DOC -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) #ifdef CONFIG_PCI - #define CONFIG_CMD_PCI -#endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_PCI) +#else /* ! PCI */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C ) +#endif /* CONFIG_PCI */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CFG_NAND_LEGACY @@ -198,7 +196,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -371,7 +369,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -529,7 +527,7 @@ PSDMR_LDOTOPRE_1C |\ PSDMR_WRC_1C |\ PSDMR_CL_2) - + /* * Init Memory Controller: * diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 604779a69..63d7a9240 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -75,42 +75,38 @@ #define CONFIG_AUTOSCRIPT 1 -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_IMI -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_ENV -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_RUN -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_AUTOSCRIPT -#define CONFIG_CMD_SETGETDCR - +#define CONFIG_COMMANDS (\ + CFG_CMD_BDI|\ + CFG_CMD_IMI|\ + CFG_CMD_FLASH|\ + CFG_CMD_MEMORY|\ + CFG_CMD_NET|\ + CFG_CMD_ENV|\ + CFG_CMD_CONSOLE|\ + CFG_CMD_ASKENV|\ + CFG_CMD_ECHO|\ + CFG_CMD_IMMAP|\ + CFG_CMD_REGINFO|\ + CFG_CMD_DHCP|\ + CFG_CMD_DATE|\ + CFG_CMD_RUN|\ + CFG_CMD_I2C|\ + CFG_CMD_EEPROM|\ + CFG_CMD_DIAG|\ + CFG_CMD_AUTOSCRIPT|\ + CFG_CMD_SETGETDCR) /* - * BOOTP options + * optional BOOTP / DHCP fields */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_VENDOREX -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (\ + CONFIG_BOOTP_VENDOREX|\ + CONFIG_BOOTP_SUBNETMASK|\ + CONFIG_BOOTP_GATEWAY|\ + CONFIG_BOOTP_DNS|\ + CONFIG_BOOTP_HOSTNAME|\ + CONFIG_BOOTP_BOOTFILESIZE|\ + CONFIG_BOOTP_BOOTPATH) /* * how many time to fail & restart a net-TFTP before giving up & resetting @@ -127,19 +123,22 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */ +#define CFG_LOAD_ADDR 0x100000/* where to load what we get from TFTP */ #define CFG_TFTP_LOADADDR CFG_LOAD_ADDR -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_DRAM_TEST 1 /*----------------------------------------------------------------------- @@ -192,6 +191,12 @@ #define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE) /* END ENVIRONNEMENT FLASH */ +/*----------------------------------------------------------------------- + * Cache Configuration. Only used to ..?? clear it, I guess.. + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 + /* * Init Memory Controller: * @@ -218,7 +223,7 @@ #else #define CFG_OCM_DATA_ADDR 0xF0000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) diff --git a/include/configs/CU824.h b/include/configs/CU824.h index f36d8dacc..acc848471 100644 --- a/include/configs/CU824.h +++ b/include/configs/CU824.h @@ -50,34 +50,26 @@ #define CONFIG_BAUDRATE 9600 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ #define CONFIG_BOOTDELAY 5 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + 0 /* CFG_CMD_DATE */ | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP +#include /* @@ -286,7 +278,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -305,7 +297,7 @@ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_TULIP #define CONFIG_TULIP_USE_IO diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h index 117a1367c..997e1baa9 100644 --- a/include/configs/DASA_SIM.h +++ b/include/configs/DASA_SIM.h @@ -57,35 +57,32 @@ #define CONFIG_IPADDR 10.0.18.222 #define CONFIG_SERVERIP 10.0.18.190 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP - +#if 0 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_BSP | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ELF ) +#else +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP ) +#endif #if 0 /* Does not appear to be used?! If it is used, needs to be fixed */ #define CONFIG_SOFT_I2C /* Software I2C support enabled */ #endif #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -182,6 +179,15 @@ #define CFG_PCI9054_DEV_FN 0x0800 #define CFG_PCI9054_IOBASE 0x0eff0000 +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ +#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h index eef216dfa..bd7aff12c 100644 --- a/include/configs/DB64360.h +++ b/include/configs/DB64360.h @@ -169,7 +169,7 @@ if we use PCI it has its own MAC addr */ #undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ +/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ /* ronen - autoboot using tftp */ #if (CONFIG_BOOTDELAY >= 0) @@ -215,16 +215,8 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) /* * JFFS2 partitions * @@ -247,20 +239,17 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)" */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_CACHE \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_PCI \ + | CFG_CMD_NET ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -272,7 +261,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" /* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -569,7 +558,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h index b14cd0df1..4b72e9b9e 100644 --- a/include/configs/DB64460.h +++ b/include/configs/DB64460.h @@ -107,7 +107,7 @@ #undef CONFIG_BOOTARGS -/*#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */ +/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */ /* ronen - autoboot using tftp */ #if (CONFIG_BOOTDELAY >= 0) @@ -153,16 +153,8 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) /* * JFFS2 partitions * @@ -185,20 +177,17 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)" */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C \ + | CFG_CMD_EEPROM \ + | CFG_CMD_CACHE \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_PCI \ + | CFG_CMD_NET ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PCI -#define CONFIG_CMD_NET - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -210,7 +199,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" /* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -507,7 +496,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index fb0668907..b58846d83 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -76,9 +76,9 @@ * a memory resource (so you must make sure TEXT_BASE is chosen * appropriately). * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ @@ -446,44 +446,46 @@ #define CONFIG_NIOS_ASMI /* Enable ASMI */ #define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_MMC | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_REISER | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_VFD | \ + CFG_CMD_USB | \ + CFG_CMD_XIMG ) ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG +#include /*------------------------------------------------------------------------ * COMPACT FLASH *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_IDE) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) #define CONFIG_IDE_PREINIT /* Implement id_preinit */ #define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ #define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ @@ -501,12 +503,12 @@ #define CFG_CF_POWER 0x009209c0 /* CF Power FET PIO base*/ #define CFG_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */ -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ /*------------------------------------------------------------------------ * KGDB *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 9600 #endif diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index 7a9ef79ad..3e3803cd2 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -84,9 +84,9 @@ * a memory resource (so you must make sure TEXT_BASE is chosen * appropriately). * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ @@ -454,42 +454,47 @@ #endif /* CFG_NIOS_CPU_PIO_NUMS */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_MMC | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_VFD | \ + CFG_CMD_USB | \ + CFG_CMD_XIMG ) ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REISER -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG +#include /*------------------------------------------------------------------------ * KGDB *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 9600 #endif diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h index 011569941..4eb96290b 100644 --- a/include/configs/DK1S10_mtx_ldk_20.h +++ b/include/configs/DK1S10_mtx_ldk_20.h @@ -147,7 +147,7 @@ /* IDE i/f */ #define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ #define CFG_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ -#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ +#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ /* memory accessibility */ #undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 912fb2af1..2ae794dc2 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -55,29 +55,17 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -99,7 +87,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -241,6 +229,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/DU405.h b/include/configs/DU405.h index c8bf67fe9..5489a5393 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -58,33 +58,21 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/ @@ -97,7 +85,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -232,6 +220,15 @@ #define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ /* total size of a CAT24WC08 is 1024 bytes */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index 324eb6ce1..720b335b0 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -27,7 +27,9 @@ #define CONFIG_EB_MCF_EV123 +#undef DEBUG #undef CFG_HALT_BEFOR_RAM_JUMP +#undef ET_DEBUG /* * High Level Configuration Options (easy to change) @@ -38,8 +40,9 @@ #define CONFIG_MISC_INIT_R -#define CONFIG_MCFUART -#define CFG_UART_PORT (0) +#define FEC_ENET +#define CONFIG_ETHADDR 00:CF:52:82:EB:01 + #define CONFIG_BAUDRATE 9600 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -65,64 +68,17 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif +/*#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB)) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_LOADB -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET - -#define CONFIG_MCFTMR - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_NET_MULTI 1 -# define CONFIG_MII 1 -# define CONFIG_MII_INIT 1 -# define CFG_DISCOVER_PHY -# define CFG_RX_ETH_BUFFER 8 -# define CFG_FAULT_ECHO_LINK_DOWN - -# define CFG_FEC0_PINMUX 0 -# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CFG_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CFG_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CFG_FAULT_ECHO_LINK_DOWN -# define CFG_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CFG_DISCOVER_PHY */ -#endif - -#ifdef CONFIG_MCFFEC -# define CONFIG_ETHADDR 00:CF:52:82:EB:01 -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -# define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif /* CONFIG_MCFFEC */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 5 #define CFG_PROMPT "\nEV123 U-Boot> " #define CFG_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -154,12 +110,15 @@ */ #define CFG_MBAR 0x40000000 +#define CFG_DISCOVER_PHY +/* #define CFG_ENET_BD_BASE 0x380000 */ + /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR 0x20000000 #define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -180,7 +139,6 @@ #define CFG_FLASH_BASE 0xFFE00000 #define CFG_INT_FLASH_BASE 0xF0000000 -#define CFG_INT_FLASH_ENABLE 0x21 /* If M5282 port is fully implemented the monitor base will be behind * the vector table. */ @@ -221,13 +179,13 @@ #define CFG_CS0_BASE CFG_FLASH_BASE #define CFG_CS0_SIZE 2*1024*1024 #define CFG_CS0_WIDTH 16 -#define CFG_CS0_RO 0 +#define CFG_CS0_RO 0 #define CFG_CS0_WS 6 #define CFG_CS3_BASE 0xE0000000 #define CFG_CS3_SIZE 1*1024*1024 #define CFG_CS3_WIDTH 16 -#define CFG_CS3_RO 0 +#define CFG_CS3_RO 0 #define CFG_CS3_WS 6 /*----------------------------------------------------------------------- @@ -252,7 +210,7 @@ #define CFG_PEHLPAR 0xC0 #define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ #define CFG_DDRUA 0x05 -#define CFG_PJPAR 0xFF; +#define CFG_PJPAR 0xFF; /*----------------------------------------------------------------------- * CCM configuration diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h index c64537fbf..2c99b4b16 100644 --- a/include/configs/ELPPC.h +++ b/include/configs/ELPPC.h @@ -28,6 +28,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#undef DEBUG #define GTREGREAD(x) 0xffffffff /* needed for debug */ /* @@ -65,25 +66,12 @@ #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_JFFS2 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -96,7 +84,7 @@ */ #define CONFIG_CONS_INDEX 1 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -329,7 +317,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h index f927a2c9c..e73bcec44 100644 --- a/include/configs/ELPT860.h +++ b/include/configs/ELPT860.h @@ -81,15 +81,7 @@ "" #define CONFIG_BOOTCOMMAND "run ramboot" -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ @@ -99,15 +91,12 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -115,7 +104,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -235,7 +224,7 @@ */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index cfa633592..5507f352b 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -160,36 +160,25 @@ #define CONFIG_IPADDR 192.168.2.21 #define CONFIG_SERVERIP 192.168.2.16 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES - -#undef CONFIG_CMD_AUTOSCRIPT -#undef CONFIG_CMD_BOOTD -#undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_ITEST -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG - +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include /*------------------------------------------------------------------------ * MISC diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 7c526f759..6eca9f23d 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -154,35 +154,25 @@ #define CONFIG_IPADDR 192.168.2.21 #define CONFIG_SERVERIP 192.168.2.16 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include /*------------------------------------------------------------------------ * MISC diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 1fe8f68c2..976e79acb 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -154,35 +154,25 @@ #define CONFIG_IPADDR 192.168.2.21 #define CONFIG_SERVERIP 192.168.2.16 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include /*------------------------------------------------------------------------ * MISC diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h index 7824b900a..738763b86 100644 --- a/include/configs/EP88x.h +++ b/include/configs/EP88x.h @@ -42,7 +42,6 @@ #define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */ #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) #define CFG_DISCOVER_PHY -#define CONFIG_MII_INIT 1 #define FEC_ENET #endif /* CONFIG_FEC_ENET */ @@ -51,25 +50,15 @@ #define CFG_8xx_CPUCLK_MIN 40000000 #define CFG_8xx_CPUCLK_MAX 133000000 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) +/* This must be included AFTER the definition of CONFIG_COMMANDS */ +#include #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */ @@ -144,7 +133,7 @@ /* Environment is in flash */ #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_OR0_PRELIM 0xFC000160 @@ -192,13 +181,13 @@ #define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) /* PISCR - Periodic Interrupt Status and Control */ -#define CFG_PISCR PISCR_PS +#define CFG_PISCR PISCR_PS /* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 +#define SCCR_MASK SCCR_EBDF11 #define CFG_SCCR SCCR_RTSEL -#define CFG_DER 0 +#define CFG_DER 0 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index bfdcf6a55..c203aea92 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -96,26 +96,23 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH) /* - * BOOTP options + * #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \ + * CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \ + * CFG_CMD_ENV | CFG_CMD_FLASH) */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. +/* CFG_CMD_ENV est definie */ +/* ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV)) */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -124,7 +121,7 @@ */ #undef CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -323,6 +320,14 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Init Memory Controller: @@ -330,7 +335,7 @@ * BR0/1 and OR0/1 (FLASH) */ -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */ +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ @@ -360,7 +365,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h index 66e1203b7..b176c6f37 100644 --- a/include/configs/ESTEEM192E.h +++ b/include/configs/ESTEEM192E.h @@ -70,21 +70,10 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "BOOT: " /* Monitor Command Prompt */ diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h index 525051fb5..d55eb7d19 100644 --- a/include/configs/ETX094.h +++ b/include/configs/ETX094.h @@ -51,7 +51,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */ -#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ +#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ #define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */ #define CONFIG_ETHADDR 08:00:06:00:00:00 @@ -82,29 +82,17 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -191,7 +179,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h index c9d8c271b..78e571688 100644 --- a/include/configs/EVB64260.h +++ b/include/configs/EVB64260.h @@ -42,7 +42,7 @@ #define CONFIG_EVB64260 1 /* this is an EVB64260 board */ #define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ #undef CONFIG_ECC /* enable ECC support */ /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ @@ -91,7 +91,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp && " \ + "bootp && " \ "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:" \ "$netmask:$hostname:eth0:none; && " \ @@ -103,30 +103,21 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -400,7 +391,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -412,10 +403,10 @@ #define CFG_L2 #ifdef CONFIG_750CX -#define L2_INIT 0 +#define L2_INIT 0 #else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #endif #define L2_ENABLE (L2_INIT | L2CR_L2E) diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h index 99d1cf255..d85be424a 100644 --- a/include/configs/EXBITGEN.h +++ b/include/configs/EXBITGEN.h @@ -33,7 +33,7 @@ * (easy to change) */ -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */ @@ -82,21 +82,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -105,7 +94,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -205,6 +194,10 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/* Cache configuration */ +#define CFG_DCACHE_SIZE 8192 +#define CFG_CACHELINE_SIZE 32 + /* * Internal Definitions * @@ -213,7 +206,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index 6f3e6a75b..1b562d606 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -46,6 +46,7 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +/*Now included by CFG_CMD_PCMCIA */ /*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */ /* Video related */ @@ -93,10 +94,10 @@ #define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ #define CONFIG_BOOTARGS "" #define CONFIG_BOOTCOMMAND \ -"bootp ;" \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ +"bootp ;" \ +"setenv bootargs console=tty0 console=ttyS0 " \ +"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ "bootm" #else #define CONFIG_BOOTDELAY 0 /* autoboot disabled */ @@ -104,39 +105,17 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_TIMEOFFSET - - -/* - * Command line configuration. - */ -#include - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -206,13 +185,12 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -458,6 +436,10 @@ */ #define NR_8259_INTS 0 +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + /* * MPC8xx CPM Options */ diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h index 356705ba1..2a986f076 100644 --- a/include/configs/FADS850SAR.h +++ b/include/configs/FADS850SAR.h @@ -61,28 +61,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #undef CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -156,13 +143,12 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -410,6 +396,10 @@ */ #define NR_8259_INTS 0 +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + #define CONFIG_DISK_SPINUP_TIME 1000000 diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h index 38295c455..18de6b00e 100644 --- a/include/configs/FADS860T.h +++ b/include/configs/FADS860T.h @@ -38,7 +38,7 @@ #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1 -#include "../../board/fads/fads.h" +#include "fads.h" #ifdef USE_REAL_FLASH_VALUES /* diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h index 431844c7f..8babee140 100644 --- a/include/configs/FLAGADM.h +++ b/include/configs/FLAGADM.h @@ -62,39 +62,21 @@ /*#define CONFIG_WATCHDOG*/ /* watchdog enabled */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \ + CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \ + CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET) -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_IMI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_ENV -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_NET - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "EEG> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -170,7 +152,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h index 79b71db75..0dd21bc61 100644 --- a/include/configs/FPS850L.h +++ b/include/configs/FPS850L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -39,101 +39,45 @@ #undef CONFIG_8xx_CONS_SMC1 #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ #undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTCOUNT_LIMIT - +#define CONFIG_BAUDRATE 19200 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootm 40020000" /* autoboot command */ + +#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=FPS850L\0" \ - "bootfile=FPS850L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=FPS850L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" +#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ + "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ + "nfsaddrs=10.0.0.99:10.0.0.2" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_TIMEOFFSET +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~( \ + CFG_CMD_CONSOLE | \ + CFG_CMD_BDI | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_CACHE ) ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if defined(CONFIG_CMD_KGDB) +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -191,15 +135,11 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -209,20 +149,6 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -234,7 +160,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h index ec757e2ff..423d74ea0 100644 --- a/include/configs/FPS860L.h +++ b/include/configs/FPS860L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -40,100 +40,44 @@ #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 - -#define CONFIG_BOOTCOUNT_LIMIT - +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif +#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=FPS860L\0" \ - "bootfile=FPS860L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=FPS860L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" +#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ + "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ + "nfsaddrs=10.0.0.99:10.0.0.2" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_TIMEOFFSET +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if defined(CONFIG_CMD_KGDB) +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -191,15 +135,11 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -209,20 +149,6 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -234,7 +160,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -335,11 +261,9 @@ #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ -/* - * FLASH timing: - */ -#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) +/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ + OR_SCY_5_CLK | OR_EHTR) #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -368,42 +292,12 @@ /* * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 */ -#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CFG_MAMR_PTA 98 +/* periodic timer for refresh */ +#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ +/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ @@ -433,6 +327,4 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_SCC1_ENET - #endif /* __CONFIG_H */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h index c12ce48b6..db42fd06f 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -88,32 +88,20 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ #endif +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -132,7 +120,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -330,6 +318,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 037b115c1..6613f90a7 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -39,9 +39,9 @@ * Identify the board */ #if !defined(CONFIG_SC) -#define CONFIG_IDENT_STRING " B2" +#define CONFIG_IDENT_STRING " B2" #else -#define CONFIG_IDENT_STRING " SC" +#define CONFIG_IDENT_STRING " SC" #endif /* @@ -50,26 +50,26 @@ * generated by the DS1337 - and the DS1337 clock can be turned off. */ #if !defined(CONFIG_SC) -#define CONFIG_8xx_GCLK_FREQ 66600000 +#define CONFIG_8xx_GCLK_FREQ 66600000 #else -#define CONFIG_8xx_GCLK_FREQ 48000000 +#define CONFIG_8xx_GCLK_FREQ 48000000 #endif /* * The RS-232 console port is on SMC1 */ #define CONFIG_8xx_CONS_SMC1 -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 38400 /* * Set allowable console baud rates */ -#define CFG_BAUDRATE_TABLE { 9600, \ - 19200, \ - 38400, \ - 57600, \ - 115200, \ - } +#define CFG_BAUDRATE_TABLE { 9600, \ + 19200, \ + 38400, \ + 57600, \ + 115200, \ + } /* * Print console information @@ -132,12 +132,9 @@ /* * BOOTP options */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE \ + ) /* * The GEN860T network interface uses the on-chip 10/100 FEC with @@ -147,8 +144,7 @@ #define CONFIG_FEC_ENET #define CFG_DISCOVER_PHY #define CONFIG_MII -#define CONFIG_MII_INIT 1 -#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_ADDR 0 /* * Set default IP stuff just to get bootstrap entries into the @@ -172,7 +168,7 @@ * Enable I2C and select the hardware/software driver */ #define CONFIG_HARD_I2C 1 /* CPM based I2C */ -#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ +#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ #ifdef CONFIG_HARD_I2C #define CFG_I2C_SPEED 100000 /* clock speed in Hz */ @@ -181,7 +177,7 @@ #ifdef CONFIG_SOFT_I2C #define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ +#define PB_SDA 0x00000010 /* PB 27 */ #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) @@ -226,30 +222,35 @@ CFG_POST_UART | \ CFG_POST_SPR ) - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_FPGA -#define CONFIG_CMD_MII -#define CONFIG_CMD_BEDBUG - -#if !defined(CONFIG_SC) - #define CONFIG_CMD_DOC +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#else +#define CFG_CMD_POST_DIAG 0 #endif -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG +/* + * List of available monitor commands. Use the system default list + * plus add some of the "non-standard" commands back in. + * See ./cmd_confdefs.h + */ +#define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_FPGA | \ + CFG_CMD_MII | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_POST_DIAG ) + +#if !defined(CONFIG_SC) +#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC ) +#else +#define CONFIG_COMMANDS BASE_CONFIG_COMMANDS #endif /* @@ -274,12 +275,15 @@ * Virtex2 FPGA configuration support */ #define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_VIRTEX2 +#define CONFIG_FPGA CFG_XILINX_VIRTEX2 #define CFG_FPGA_PROG_FEEDBACK +/************************************************************************ + * This must be included AFTER the definition of any CONFIG_COMMANDS + */ +#include + #define CFG_NAND_LEGACY /* @@ -302,7 +306,7 @@ /* * Set buffer size for console I/O */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 #else #define CFG_CBSIZE 256 @@ -388,7 +392,7 @@ */ #define CFG_INIT_RAM_ADDR CFG_IMMR #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ +#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -467,7 +471,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */ #endif @@ -480,18 +484,18 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWE | \ + SYPCR_BMT | \ + SYPCR_BME | \ + SYPCR_SWF | \ + SYPCR_SWE | \ SYPCR_SWRI | \ SYPCR_SWP \ ) #else #define CFG_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ + SYPCR_BMT | \ + SYPCR_BME | \ + SYPCR_SWF | \ SYPCR_SWP \ ) #endif @@ -557,18 +561,18 @@ #define SCCR_MASK SCCR_EBDF11 #if !defined(CONFIG_SC) -#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ SCCR_DFNL000 | \ SCCR_DFNH000 \ ) #else -#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ SCCR_DFNL000 | \ SCCR_DFNH000 | \ SCCR_RTDIV | \ @@ -614,7 +618,7 @@ #define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ BR_MS_GPCM | \ BR_PS_8 | \ - BR_V \ + BR_V \ ) /* @@ -626,9 +630,9 @@ ) #define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ - BR_MS_UPMA | \ - BR_PS_32 | \ - BR_V \ + BR_MS_UPMA | \ + BR_PS_32 | \ + BR_V \ ) /* @@ -646,9 +650,9 @@ * MAMR settings for SDRAM */ #define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_PTAE | \ + MAMR_PTAE | \ MAMR_AMA_TYPE_1 | \ - MAMR_DSA_1_CYCL | \ + MAMR_DSA_1_CYCL | \ MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | \ MAMR_WLFA_1X | \ @@ -660,7 +664,7 @@ * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, * no burst. */ -#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ +#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ OR_CSNT_SAM | \ OR_ACS_DIV2 | \ OR_BI | \ @@ -685,20 +689,20 @@ */ #define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ OR_SCY_15_CLK | \ - OR_BI \ + OR_BI \ ) #define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ BR_PS_32 | \ BR_MS_GPCM | \ - BR_V \ + BR_V \ ) /* * CS4* configuration for FPGA SelectMap configuration interface. * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge * of GCLK1_50 */ -#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ +#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ OR_G5LS | \ OR_BI \ ) @@ -706,7 +710,7 @@ #define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ BR_PS_8 | \ BR_MS_UPMB | \ - BR_V \ + BR_V \ ) /* @@ -728,7 +732,7 @@ #define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ BR_PS_16 | \ BR_MS_GPCM | \ - BR_V \ + BR_V \ ) /* @@ -760,3 +764,5 @@ #endif #endif /* __CONFIG_GEN860T_H */ + +/* vim: set ts=4 tw=78 ai shiftwidth=4: */ diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h index f6d6ae0ce..8c01d97fa 100644 --- a/include/configs/GENIETV.h +++ b/include/configs/GENIETV.h @@ -80,10 +80,10 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 9600 -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 5000000 /* 4 MHz clock */ +#define MPC8XX_FACT 12 /* Multiply by 12 */ +#define MPC8XX_XIN 5000000 /* 4 MHz clock */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) +#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) #define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20) #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ @@ -95,9 +95,9 @@ #define CONFIG_BOOTARGS "" #define CONFIG_BOOTCOMMAND \ "bootp; tftp; " \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ +"setenv bootargs console=tty0 console=ttyS0 " \ +"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ "bootm " #else #define CONFIG_BOOTDELAY 0 /* autoboot disabled */ @@ -105,28 +105,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -197,7 +184,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ +#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/ /* values according to the manual */ @@ -206,7 +193,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -291,15 +278,15 @@ #define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */ /* FLASH timing */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ OR_SCY_15_CLK | OR_TRLX ) /*#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) */ -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */ +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */ #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */ /* @@ -348,6 +335,10 @@ */ #define NR_8259_INTS 0 +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + /* * MPC8xx CPM Options */ diff --git a/include/configs/GTH.h b/include/configs/GTH.h index 461670a10..03b965949 100644 --- a/include/configs/GTH.h +++ b/include/configs/GTH.h @@ -62,9 +62,8 @@ /* Only interrupt boot if space is pressed */ /* If a long serial cable is connected but */ /* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press space to abort autoboot in %d second\n", bootdelay +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n" #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " @@ -98,32 +97,18 @@ #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured #endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IDE - - +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ #define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -136,7 +121,7 @@ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ /* Default location to load data from net */ -#define CFG_LOAD_ADDR 0x100000 +#define CFG_LOAD_ADDR 0x100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -197,7 +182,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #undef CFG_ENV_IS_IN_EEPROM #define CFG_ENV_OFFSET 0x000E0000 -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */ @@ -205,7 +190,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 8ea1ac37d..dc40ebc86 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -41,7 +41,7 @@ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_HH405 1 /* ...on a HH405 board */ +#define CONFIG_HH405 1 /* ...on a HH405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -98,40 +98,26 @@ #define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ #define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ +#define ADD_BMP_CMD CFG_CMD_BMP +#else +#define ADD_BMP_CMD 0 #endif /* CONFIG_VIDEO */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - -#ifdef CONFIG_VIDEO -#define CONFIG_CMD_BMP -#endif +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + ADD_BMP_CMD | \ + CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -141,6 +127,11 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_NAND_LEGACY + #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -157,7 +148,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -207,18 +198,36 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } -#define NAND_MAX_CHIPS 1 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CFG_NAND_QUIET 1 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- * PCI stuff @@ -362,6 +371,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h index 26dd954c1..686474077 100644 --- a/include/configs/HIDDEN_DRAGON.h +++ b/include/configs/HIDDEN_DRAGON.h @@ -52,27 +52,16 @@ #define CONFIG_BAUDRATE 9600 #define CONFIG_DRAM_SPEED 100 /* MHz */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_NET | \ + CFG_CMD_PCI | \ + CFG_CMD_PING ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -374,7 +363,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h index 081ca6cc5..7cce87692 100644 --- a/include/configs/HMI10.h +++ b/include/configs/HMI10.h @@ -60,7 +60,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS @@ -117,15 +117,7 @@ #define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -133,25 +125,31 @@ #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - #ifdef CONFIG_SPLASH_SCREEN - #define CONFIG_CMD_BMP +# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BMP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +#else +# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) #endif +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -166,7 +164,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -224,15 +222,11 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -253,7 +247,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index a389d582d..f84e35621 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -60,30 +60,18 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -100,7 +88,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -147,18 +135,38 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } -#define NAND_MAX_CHIPS 1 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 +#define CFG_NAND_LEGACY -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CFG_NAND_QUIET 1 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- * PCI stuff @@ -257,6 +265,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h index 87827ead1..35d84aedf 100644 --- a/include/configs/IAD210.h +++ b/include/configs/IAD210.h @@ -63,36 +63,28 @@ # define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" /* using this define saves us updating another source file */ #define CONFIG_BOARD_EARLY_INIT_F 1 #undef CONFIG_BOOTARGS /* #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" */ #define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs" \ - "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ + "setenv bootargs root=/dev/nfs" \ + "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ #undef CONFIG_WATCHDOG /* watchdog disabled */ /* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) # undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ # define CONFIG_FEC_ENET 1 /* use FEC ethernet */ @@ -131,23 +123,20 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -159,7 +148,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -228,7 +217,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index f693956d4..cd1793589 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -68,28 +68,20 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ #define CONFIG_FEC_ENET 1 /* use FEC ethernet */ @@ -131,28 +123,25 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -164,7 +153,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -234,13 +223,12 @@ #define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment sector */ #define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */ -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index f7d4499f4..29eb874db 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -43,7 +43,7 @@ #define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS @@ -120,17 +120,6 @@ #define CFG_NS16550_COM1 (CFG_UART_BASE + 0x8000) - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8247@0" -#define OF_SOC "soc@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" - - /* * select ethernet configuration * @@ -139,23 +128,23 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ #undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ -#define CONFIG_ETHER_ON_FCC1 -#define FCC_ENET +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ /* - * - Rx-CLK is CLK10 - * - Tx-CLK is CLK9 + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) * - Enable Full Duplex in FSMR */ -# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) # define CFG_CPMFCR_RAMTYPE 0 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) @@ -170,36 +159,24 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SNTP +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_NAND | \ + CFG_CMD_I2C | \ + CFG_CMD_SNTP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -226,10 +203,7 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_BANKS_LIST { 0xFF800000 } -#define CFG_MAX_FLASH_BANKS_DETECT 1 + /* What should the base address of the main FLASH be and how big is * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk * The main FLASH is whichever is connected to *CS0. @@ -245,7 +219,7 @@ * FLASH organization */ #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ +#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */ #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ @@ -260,7 +234,7 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #define CFG_NAND_LEGACY #define CFG_NAND0_BASE 0xE1000000 @@ -321,7 +295,7 @@ #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0) #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0))) -#endif /* CONFIG_CMD_NAND */ +#endif /* CFG_CMD_NAND */ /*----------------------------------------------------------------------- * Hard Reset Configuration Words @@ -381,7 +355,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -500,7 +474,7 @@ #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ ORxG_SCY_6_CLK ) -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) /* Bank 1 - NAND Flash */ #define CFG_NAND_BASE CFG_NAND0_BASE @@ -529,12 +503,12 @@ */ #define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ - ORxS_ROWST_PBI0_A9 |\ + ORxS_ROWST_PBI0_A10 |\ ORxS_NUMR_12) -#define CFG_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ +#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\ PSDMR_BSMA_A15_A17 |\ - PSDMR_SDA10_PBI0_A10 |\ + PSDMR_SDA10_PBI0_A11 |\ PSDMR_RFRC_5_CLK |\ PSDMR_PRETOACT_2W |\ PSDMR_ACTTORW_2W |\ diff --git a/include/configs/IP860.h b/include/configs/IP860.h index e6c7fe656..0e20e5676 100644 --- a/include/configs/IP860.h +++ b/include/configs/IP860.h @@ -41,7 +41,7 @@ #define CONFIG_BAUDRATE 9600 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \ +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \ "\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0" #undef CONFIG_BOOTARGS @@ -88,32 +88,28 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP +/*----------------------------------------------------------------------*/ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -206,7 +202,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h index 7d564a095..c1565fc03 100644 --- a/include/configs/IPHASE4539.h +++ b/include/configs/IPHASE4539.h @@ -30,6 +30,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#undef DEBUG /* General debug */ + /*----------------------------------------------------------------------- * High Level Configuration Options * (easy to change) @@ -65,7 +67,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ @@ -92,14 +95,7 @@ #define CONFIG_8260_CLKIN 66666666 /* in Hz */ #define CONFIG_BAUDRATE 19200 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) /* * select i2c support configuration @@ -128,18 +124,17 @@ #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ #endif /* CONFIG_SOFT_I2C */ +#define CONFIG_COMMANDS CONFIG_CMD_DFL -/* - * Command line configuration. - */ -#include +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/ram rw" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -154,7 +149,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -262,7 +257,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -274,7 +269,7 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) + HID0_IFEM|HID0_ABE) #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) #define CFG_HID2 0 diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 760f7cca6..706bdb94f 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -58,7 +58,8 @@ * for FCC). * * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must - * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * be defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */ #define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */ @@ -105,28 +106,17 @@ #define CONFIG_8260_CLKIN 65536000 /* in Hz */ #define CONFIG_BAUDRATE 38400 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_REGINFO \ + ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO - +/* This must be included AFTER the definition of CONFIG_COMMANDS */ +#include #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */ @@ -186,7 +176,7 @@ /* Environment is in flash, there is little space left in Serial EEPROM */ #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h index 0ffdfac07..a0cb1dd48 100644 --- a/include/configs/IVML24.h +++ b/include/configs/IVML24.h @@ -72,33 +72,24 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IDE - - +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK \ + ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -191,7 +182,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -205,7 +196,7 @@ # if defined (CONFIG_IVML24_16M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) # elif defined (CONFIG_IVML24_32M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWP) @@ -265,7 +256,7 @@ /* 0x01800014 */ #define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000 | SCCR_DFLCD101 | \ @@ -458,8 +449,8 @@ #if defined (CONFIG_IVML24_16M) /* 8 column SDRAM */ # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) #elif defined (CONFIG_IVML24_32M) /* 128 MBit SDRAM */ # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h index ea3ffe0a1..46b4d5354 100644 --- a/include/configs/IVMS8.h +++ b/include/configs/IVMS8.h @@ -72,32 +72,24 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IDE - - +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK \ + ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -187,7 +179,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -200,7 +192,7 @@ #if defined(CONFIG_WATCHDOG) # if defined (CONFIG_IVMS8_16M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) # elif defined (CONFIG_IVMS8_32M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWP) @@ -259,7 +251,7 @@ /* 0x01800014 */ #define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000 | SCCR_DFLCD101 | \ @@ -440,8 +432,8 @@ #if defined (CONFIG_IVMS8_16M) /* 8 column SDRAM */ # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) #elif defined (CONFIG_IVMS8_32M) /* 128 MBit SDRAM */ #define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 3a347eac5..1152f838d 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -37,7 +37,10 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -58,7 +61,6 @@ #if defined(CONFIG_PCI) #define CONFIG_PCI_PNP 1 #define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_PCI_MEM_BUS 0x40000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -67,6 +69,7 @@ #define CONFIG_PCI_IO_BUS 0x50000000 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0x01000000 +#define ADD_PCI_CMD CFG_CMD_PCI #endif #define CFG_XLB_PIPELINING 1 @@ -77,8 +80,11 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#else +#else /* MPC5100 */ + #define CONFIG_MII 1 +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + #endif /* Partitions */ @@ -87,44 +93,31 @@ #define CONFIG_ISO_PARTITION /* USB */ -#define CONFIG_USB_OHCI_NEW +#if 1 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#define CFG_OHCI_BE_CONTROLLER -#undef CFG_USB_OHCI_BOARD_INIT -#define CFG_USB_OHCI_CPU_INIT 1 -#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CFG_USB_OHCI_SLOT_NAME "mpc5200" -#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 +#else +#define ADD_USB_CMD 0 +#endif #define CONFIG_TIMESTAMP /* Print image info with timestamp */ - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + ADD_PCI_CMD | \ + ADD_USB_CMD ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 @@ -145,7 +138,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -174,21 +167,11 @@ * IPB Bus clocking configuration. */ #if defined(CONFIG_LITE5200B) -#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ #else -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #endif #endif /* CONFIG_MPC5200 */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - /* * I2C configuration */ @@ -316,7 +299,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -332,11 +315,6 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Various low-level settings */ diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 5b40ef6b4..ccd1f1990 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -49,7 +49,6 @@ /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ #define CONFIG_SYSTEMACE 1 #define CFG_SYSTEMACE_BASE 0xf0000000 -#define CFG_SYSTEMACE_WIDTH 8 #define CONFIG_DOS_PARTITION 1 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ @@ -135,32 +134,20 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_FLASH | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PCI | \ + CFG_CMD_PING ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* watchdog disabled */ #undef CONFIG_WATCHDOG @@ -179,7 +166,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -279,6 +266,15 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * @@ -301,7 +297,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 816e63ba2..7bbceb01b 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -38,7 +38,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ #define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ @@ -178,42 +177,36 @@ #define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_PING -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT - +/*----------------------------------------------------------------------- + * Console/Commands/Parser + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_PING | \ + CFG_CMD_DIAG | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_ELF | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT) /* Include NetConsole support */ #define CONFIG_NETCONSOLE /* Include auto complete with tabs */ #define CONFIG_AUTO_COMPLETE 1 +#define CFG_AUTO_COMPLETE 1 #define CFG_ALT_MEMTEST 1 /* use real memory test */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */ @@ -224,7 +217,7 @@ /*----------------------------------------------------------------------- * Console Buffer *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -270,6 +263,7 @@ #define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) /* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ #define CFG_PCI_TARGET_INIT /* let board init pci target*/ #define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ @@ -281,6 +275,14 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ +#endif /* * Internal Definitions @@ -290,7 +292,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ #define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ #endif diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index e52fbfde0..9b950fc5d 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -89,15 +89,7 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -164,31 +156,32 @@ #define CONFIG_POST (CFG_POST_CPU | \ CFG_POST_RTC | \ CFG_POST_I2C) -#endif - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP #ifdef CONFIG_POST - #define CONFIG_CMD_DIAG +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#else +#define CFG_CMD_POST_DIAG 0 #endif +#endif + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -276,7 +269,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -488,8 +481,7 @@ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ #if 0 -#define CONFIG_AUTOBOOT_PROMPT \ - "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay +#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" #endif #define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ #define CONFIG_SILENT_CONSOLE 1 diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h index be0c7af8f..cd38b0f2c 100644 --- a/include/configs/KUP4X.h +++ b/include/configs/KUP4X.h @@ -99,15 +99,7 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -175,33 +167,34 @@ #define CONFIG_POST (CFG_POST_CPU | \ CFG_POST_RTC | \ CFG_POST_I2C) -#endif - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB #ifdef CONFIG_POST - #define CONFIG_CMD_DIAG +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#else +#define CFG_CMD_POST_DIAG 0 #endif +#endif + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_SNTP | \ + CFG_CMD_USB ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -288,7 +281,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -454,8 +447,7 @@ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ #if 0 -#define CONFIG_AUTOBOOT_PROMPT \ - "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay +#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" #endif #define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ #define CONFIG_SILENT_CONSOLE 1 diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h index e92069b5a..e44f1cc62 100644 --- a/include/configs/LANTEC.h +++ b/include/configs/LANTEC.h @@ -74,54 +74,64 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_XIMG - -#if !(CONFIG_LANTEC >= 2) - #undef CONFIG_CMD_DATE - #undef CONFIG_CMD_NET -#endif +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_CMD_MINIMAL 0 +#define CONFIG_CMD_TINY (CFG_CMD_FLASH | \ + CFG_CMD_MEMORY | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB) +#define CONFIG_CMD_NORMAL (CONFIG_CMD_DFL & ~CFG_CMD_BOOTD & ~CFG_CMD_REISER) +#define CONFIG_CMD_GDB (CONFIG_CMD_NORMAL | CFG_CMD_KGDB) +#define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \ + & ~CFG_CMD_BMP \ + & ~CFG_CMD_BSP \ + & ~CFG_CMD_DISPLAY \ + & ~CFG_CMD_DOC \ + & ~CFG_CMD_DTT \ + & ~CFG_CMD_EEPROM \ + & ~CFG_CMD_ELF \ + & ~CFG_CMD_EXT2 \ + & ~CFG_CMD_FDC \ + & ~CFG_CMD_FDOS \ + & ~CFG_CMD_HWFLOW \ + & ~CFG_CMD_I2C \ + & ~CFG_CMD_IDE \ + & ~CFG_CMD_IRQ \ + & ~CFG_CMD_JFFS2 \ + & ~CFG_CMD_KGDB \ + & ~CFG_CMD_MII \ + & ~CFG_CMD_MMC \ + & ~CFG_CMD_NAND \ + & ~CFG_CMD_PCI \ + & ~CFG_CMD_PCMCIA \ + & ~CFG_CMD_REISER \ + & ~CFG_CMD_SCSI \ + & ~CFG_CMD_SPI \ + & ~CFG_CMD_UNIVERSE\ + & ~CFG_CMD_USB \ + & ~CFG_CMD_VFD \ + & ~CFG_CMD_XIMG ) #if CONFIG_LANTEC >= 2 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ #endif +#if CONFIG_LANTEC >= 2 +# define CONFIG_COMMANDS CONFIG_CMD_FULL +#else +# define CONFIG_COMMANDS (CONFIG_CMD_FULL & ~CFG_CMD_DATE & ~CFG_CMD_NET) +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -193,7 +203,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index a6fac4cbf..f0fc01343 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -31,6 +31,9 @@ #ifndef _M5271EVB_H #define _M5271EVB_H +#define DEBUG +#undef DEBUG + /* * High Level Configuration Options (easy to change) */ @@ -38,120 +41,46 @@ #define CONFIG_M5271 /* define processor type */ #define CONFIG_M5271EVB /* define board type */ -#define CONFIG_MCFTMR +#define CONFIG_IPADDR 192.168.30.1 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_ETHADDR 00:06:3b:01:41:55 -#define CONFIG_MCFUART -#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG /* disable watchdog */ +#define CONFIG_BOOTDELAY 5 + /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ #ifndef CONFIG_MONITOR_IS_IN_RAM #define CFG_ENV_OFFSET 0x4000 -#else -#define CFG_ENV_ADDR 0xffe04000 -#endif #define CFG_ENV_SECT_SIZE 0x2000 #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC - -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_NET_MULTI 1 -# define CONFIG_MII 1 -# define CONFIG_MII_INIT 1 -# define CFG_DISCOVER_PHY -# define CFG_RX_ETH_BUFFER 8 -# define CFG_FAULT_ECHO_LINK_DOWN - -# define CFG_FEC0_PINMUX 0 -# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CFG_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CFG_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CFG_FAULT_ECHO_LINK_DOWN -# define CFG_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CFG_DISCOVER_PHY */ +#else +#define CFG_ENV_ADDR 0xffe04000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 #endif -/* I2C */ -#define CONFIG_FSL_I2C -#define CONFIG_HARD_I2C /* I2C with hw support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 80000 -#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_OFFSET 0x00000300 -#define CFG_IMMR CFG_MBAR +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET ) & ~(CFG_CMD_LOADS | CFG_CMD_LOADB)) -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ -#define CONFIG_BOOTFILE "u-boot.bin" -#ifdef CONFIG_MCFFEC -# define CONFIG_NET_RETRY_COUNT 5 -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -# define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME M5235EVB -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe2ffff;" \ - "era ffe00000 ffe2ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ - "save\0" \ - "" +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CFG_PROMPT "=> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 @@ -169,11 +98,16 @@ #define CFG_MBAR 0x40000000 /* Register Base Addrs */ +/* Enable FEC ethernet */ +#define FEC_ENET +#define CONFIG_NET_RETRY_COUNT 5 +#define CFG_ENET_BD_BASE 0x480000 + /* * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -184,7 +118,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #ifdef CONFIG_MONITOR_IS_IN_RAM @@ -202,11 +136,11 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 1000 #define CFG_FLASH_CFI 1 @@ -219,4 +153,4 @@ /* Port configuration */ #define CFG_FECI2C 0xF0 -#endif /* _M5271EVB_H */ +#endif /* _M5271EVB_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 7edd322bd..5fd6a95c4 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -33,20 +33,18 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5272 /* define processor type */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5272 /* define processor type */ -#define CONFIG_MCFTMR +#define FEC_ENET -#define CONFIG_MCFUART -#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } -#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ -#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ +#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -62,90 +60,30 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_MISC -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_MEMORY - -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \ + CFG_CMD_MII) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 5 -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_NET_MULTI 1 -# define CONFIG_MII 1 -# define CFG_DISCOVER_PHY -# define CFG_RX_ETH_BUFFER 8 -# define CFG_FAULT_ECHO_LINK_DOWN - -# define CFG_FEC0_PINMUX 0 -# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CFG_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CFG_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CFG_FAULT_ECHO_LINK_DOWN -# define CFG_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CFG_DISCOVER_PHY */ -#endif - -#ifdef CONFIG_MCFFEC -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -# define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME M5272C3 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe3ffff;" \ - "era ffe00000 ffe3ffff;" \ - "cp.b ${loadaddr} ffe00000 ${filesize};"\ - "save\0" \ - "" #define CFG_PROMPT "-> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x20000 + #define CFG_MEMTEST_START 0x400 #define CFG_MEMTEST_END 0x380000 + #define CFG_HZ 1000 #define CFG_CLK 66000000 @@ -154,15 +92,20 @@ * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ + #define CFG_MBAR 0x10000000 /* Register Base Addrs */ + #define CFG_SCR 0x0003; #define CFG_SPR 0xffff; +#define CFG_DISCOVER_PHY +#define CFG_ENET_BD_BASE 0x380000 + /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -173,7 +116,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #ifdef CONFIG_MONITOR_IS_IN_RAM @@ -191,13 +134,13 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ #define CFG_FLASH_ERASE_TOUT 1000 /*----------------------------------------------------------------------- @@ -210,18 +153,25 @@ */ #define CFG_BR0_PRELIM 0xFFE00201 #define CFG_OR0_PRELIM 0xFFE00014 + #define CFG_BR1_PRELIM 0 #define CFG_OR1_PRELIM 0 + #define CFG_BR2_PRELIM 0x30000001 #define CFG_OR2_PRELIM 0xFFF80000 + #define CFG_BR3_PRELIM 0 #define CFG_OR3_PRELIM 0 + #define CFG_BR4_PRELIM 0 #define CFG_OR4_PRELIM 0 + #define CFG_BR5_PRELIM 0 #define CFG_OR5_PRELIM 0 + #define CFG_BR6_PRELIM 0 #define CFG_OR6_PRELIM 0 + #define CFG_BR7_PRELIM 0x00000701 #define CFG_OR7_PRELIM 0xFFC0007C @@ -231,8 +181,9 @@ #define CFG_PACNT 0x00000000 #define CFG_PADDR 0x0000 #define CFG_PADAT 0x0000 -#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ +#define CFG_PBCNT 0x55554155 /* Ethernet/UART configuration */ #define CFG_PBDDR 0x0000 #define CFG_PBDAT 0x0000 #define CFG_PDCNT 0x00000000 -#endif /* _M5272C3_H */ + +#endif /* _M5272C3_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index df46ee443..cbb3e3bb9 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -33,17 +33,15 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF52x2 /* define processor family */ -#define CONFIG_M5282 /* define processor type */ +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5282 /* define processor type */ -#define CONFIG_MCFTMR +#define FEC_ENET -#define CONFIG_MCFUART -#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } -#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ +#define CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -52,82 +50,24 @@ #define CFG_ENV_SIZE 0x2000 #define CFG_ENV_IS_IN_FLASH 1 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -/* - * Command line configuration. - */ -#include -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII - -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_NET_MULTI 1 -# define CONFIG_MII 1 -# define CONFIG_MII_INIT 1 -# define CFG_DISCOVER_PHY -# define CFG_RX_ETH_BUFFER 8 -# define CFG_FAULT_ECHO_LINK_DOWN - -# define CFG_FEC0_PINMUX 0 -# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CFG_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CFG_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CFG_FAULT_ECHO_LINK_DOWN -# define CFG_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CFG_DISCOVER_PHY */ -#endif +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 5 -#ifdef CONFIG_MCFFEC -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -# define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME M5272C3 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe3ffff;" \ - "era ffe00000 ffe3ffff;" \ - "cp.b ${loadaddr} ffe00000 ${filesize};"\ - "save\0" \ - "" #define CFG_PROMPT "-> " -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x20000 @@ -137,10 +77,6 @@ #define CFG_HZ 1000000 #define CFG_CLK 64000000 -/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ - -#define CFG_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */ /* * Low Level Configuration Settings @@ -149,12 +85,15 @@ */ #define CFG_MBAR 0x40000000 +#undef CFG_DISCOVER_PHY +#define CFG_ENET_BD_BASE 0x380000 + /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR 0x20000000 -#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -164,88 +103,49 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SDRAM_SIZE 4 /* SDRAM size in MB */ #define CFG_FLASH_BASE 0xffe00000 #define CFG_INT_FLASH_BASE 0xf0000000 -#define CFG_INT_FLASH_ENABLE 0x21 /* If M5282 port is fully implemented the monitor base will be behind * the vector table. */ -#if (TEXT_BASE != CFG_INT_FLASH_BASE) -#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) -#else -#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ -#endif +/* #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) */ +#define CFG_MONITOR_BASE 0x20000 #define CFG_MONITOR_LEN 0x20000 #define CFG_MALLOC_LEN (256 << 10) #define CFG_BOOTPARAMS_LEN 64*1024 + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_FLASH_CFI -#ifdef CFG_FLASH_CFI - -# define CFG_FLASH_CFI_DRIVER 1 -# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ -# define CFG_FLASH_CHECKSUM -# define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#endif +#define CFG_MAX_FLASH_SECT 35 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_FLASH_ERASE_TOUT 10000000 /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 + /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CFG_CS0_BASE CFG_FLASH_BASE -#define CFG_CS0_SIZE 2*1024*1024 -#define CFG_CS0_WIDTH 16 -#define CFG_CS0_RO 0 -#define CFG_CS0_WS 6 -/* -#define CFG_CS3_BASE 0xE0000000 -#define CFG_CS3_SIZE 1*1024*1024 -#define CFG_CS3_WIDTH 16 -#define CFG_CS3_RO 0 -#define CFG_CS3_WS 6 -*/ + + /*----------------------------------------------------------------------- * Port configuration */ -#define CFG_PACNT 0x0000000 /* Port A D[31:24] */ -#define CFG_PADDR 0x0000000 -#define CFG_PADAT 0x0000000 -#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CFG_PBDDR 0x0000000 -#define CFG_PBDAT 0x0000000 -#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CFG_PCDDR 0x0000000 -#define CFG_PCDAT 0x0000000 - -#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CFG_PCDDR 0x0000000 -#define CFG_PCDAT 0x0000000 - -#define CFG_PEHLPAR 0xC0 -#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ -#define CFG_DDRUA 0x05 -#define CFG_PJPAR 0xFF; - -#endif /* _CONFIG_M5282EVB_H */ +#endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/MBX.h b/include/configs/MBX.h index d9f2addb5..d6e3fb8de 100644 --- a/include/configs/MBX.h +++ b/include/configs/MBX.h @@ -71,28 +71,14 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_NET -#define CONFIG_CMD_DFL -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_IDE - +#define CONFIG_COMMANDS ( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \ + CFG_CMD_PCMCIA | CFG_CMD_IDE ) #define CONFIG_DOS_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ @@ -102,7 +88,7 @@ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -201,7 +187,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h index 3b88507de..0ca097007 100644 --- a/include/configs/MBX860T.h +++ b/include/configs/MBX860T.h @@ -151,7 +151,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -379,6 +379,10 @@ */ #define NR_8259_INTS 0 +/* Machine type +*/ +#define _MACH_8xx (_MACH_fads) + /* * MPC8xx CPM Options */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index d61b49eee..b96557148 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -104,7 +104,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_METROBOX 1 /* Board is Metrobox */ #define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ @@ -242,33 +241,26 @@ #define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +/*----------------------------------------------------------------------- + * Console/Commands/Parser + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_PING | \ + CFG_CMD_DIAG | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_ELF | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT) - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_PING -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT +/* tbs 09-March-2005 Removed to be able to use 2nd serial */ +/* CFG_CMD_KGDB | \ */ /* Include NetConsole support */ @@ -276,9 +268,13 @@ /* Include auto complete with tabs */ #define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_AUTO_COMPLETE 1 +#define CFG_AUTO_COMPLETE 1 #define CFG_ALT_MEMTEST 1 /* use real memory test */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */ @@ -289,7 +285,7 @@ /*----------------------------------------------------------------------- * Console Buffer *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -335,6 +331,7 @@ #define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) /* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ #define CFG_PCI_TARGET_INIT /* let board init pci target*/ #define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ @@ -346,6 +343,14 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ +#endif /* * Internal Definitions @@ -355,7 +360,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ #define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ #endif diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h index dde774271..53684ca6b 100644 --- a/include/configs/MHPC.h +++ b/include/configs/MHPC.h @@ -115,36 +115,25 @@ #define CONFIG_BR0_WORKAROUND 1 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_REGINFO ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_REGINFO - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -236,7 +225,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index d683b87ae..7e57a0fae 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -50,43 +50,41 @@ ***********************************************************/ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ +/*********************************************************** + * Command definitions + ***********************************************************/ +#define MIP405_COMMON_CMDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SAVES | \ + CFG_CMD_BSP ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +#if defined(CONFIG_MIP405T) +#define CONFIG_COMMANDS \ + MIP405_COMMON_CMDS +#else +#define CONFIG_COMMANDS \ + (MIP405_COMMON_CMDS | \ + CFG_CMD_USB | \ + CFG_CMD_DOC ) - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_BSP - -#if !defined(CONFIG_MIP405T) - #define CONFIG_CMD_USB - #define CONFIG_CMD_DOC #endif +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CFG_NAND_LEGACY @@ -123,7 +121,7 @@ * (to get SDRAM settings) ***************************************************************/ /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 -#define SDRAM_EEPROM_READ_ADDRESS 0xA1 +#define SDRAM_EEPROM_READ_ADDRESS 0xA1 */ /************************************************************** * Environment definitions @@ -132,7 +130,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ @@ -167,7 +165,7 @@ **********************************************************/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -257,10 +255,19 @@ #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /*----------------------------------------------------------------------- * Logbuffer Configuration */ -#undef CONFIG_LOGBUFFER /* supported but not enabled */ +#undef CONFIG_LOGBUFFER /* supported but not enabled */ /*----------------------------------------------------------------------- * Bootcountlimit Configuration */ @@ -271,8 +278,8 @@ */ #if 0 /* enable this if POST is desired (is supported but not enabled) */ #define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_RTC | \ + CFG_POST_CPU | \ + CFG_POST_RTC | \ CFG_POST_I2C) #endif @@ -292,7 +299,7 @@ #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 -#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 +#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 /*----------------------------------------------------------------------- @@ -301,7 +308,7 @@ #define CFG_TEMP_STACK_OCM 1 #define CFG_OCM_DATA_ADDR 0xF0000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -362,7 +369,7 @@ #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ @@ -419,7 +426,7 @@ /************************************************************ * Debug support ************************************************************/ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ML2.h b/include/configs/ML2.h index 66dae2192..d8805ea5a 100644 --- a/include/configs/ML2.h +++ b/include/configs/ML2.h @@ -76,31 +76,20 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_JFFS2 - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_RTC -#undef CONFIG_CMD_PCI -#undef CONFIG_CMD_I2C +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & \ + ~( CFG_CMD_NET | \ + CFG_CMD_RTC | \ + CFG_CMD_PCI | \ + CFG_CMD_I2C \ + ) ) | \ + CFG_CMD_IRQ | \ + CFG_CMD_KGDB | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF | \ + CFG_CMD_JFFS2 ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -113,7 +102,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -201,6 +190,14 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Init Memory Controller: @@ -239,7 +236,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h index 021729b58..6ad2feb28 100644 --- a/include/configs/MOUSSE.h +++ b/include/configs/MOUSSE.h @@ -58,31 +58,14 @@ #endif #define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138" #define CONFIG_BOOTDELAY 3 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE - - +#define CONFIG_COMMANDS (CONFIG_CMD_DFL|CFG_CMD_ASKENV|CFG_CMD_DATE) #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_ETH_ADDR "00:10:18:10:00:06" #define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */ - +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include #include "../board/mousse/mousse.h" /* @@ -265,18 +248,18 @@ #else #define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT) #endif -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT1L CFG_IBAT1L /* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */ -#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) +#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) #define CFG_DBAT2U CFG_IBAT2U #define CFG_DBAT2L CFG_IBAT2L /* PCI Memory region 2: PCI Devices in 0xFD space */ -#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) #define CFG_DBAT3U CFG_IBAT3U #define CFG_DBAT3L CFG_IBAT3L @@ -299,7 +282,7 @@ #if 0 #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ +#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ #define CFG_ENV_SIZE 0x4000 /* Size of the Environment Sector */ #else #define CFG_ENV_IS_IN_NVRAM 1 @@ -339,7 +322,7 @@ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_TULIP diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 59d0bdbeb..6195bca85 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -101,7 +101,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ @@ -197,66 +198,59 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#if defined(CONFIG_OF_LIBFDT) -#define OF_CPU "cpu@0" -#define OF_TBCLK (bd->bi_busfreq / 4) -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM - -#undef CONFIG_CMD_XIMG +#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_KGDB | \ + CFG_CMD_MMC | \ + CFG_CMD_NAND | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_REISER | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_SNTP | \ + CFG_CMD_UNIVERSE | \ + CFG_CMD_USB | \ + CFG_CMD_VFD | \ + CFG_CMD_XIMG #if CONFIG_ADSTYPE == CFG_8272ADS - #undef CONFIG_CMD_SDRAM - #undef CONFIG_CMD_I2C - +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_EXCLUDE ) ) #elif CONFIG_ADSTYPE >= CFG_PQ2FADS - #undef CONFIG_CMD_SDRAM - #undef CONFIG_CMD_I2C - #undef CONFIG_CMD_PCI - +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_CMD_PCI | \ + CFG_EXCLUDE ) ) #else - #undef CONFIG_CMD_PCI - +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CMD_CFG_PCI | \ + CFG_EXCLUDE ) ) #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock2" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -274,7 +268,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -390,7 +384,7 @@ #endif /* CFG_RAMBOOT */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -403,9 +397,9 @@ #define CFG_BCR 0x100C0000 #define CFG_SIUMCR 0x0A200000 #define CFG_SCCR SCCR_DFBRG01 -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) +#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801 #define CFG_OR0_PRELIM 0xFF800876 -#define CFG_BR1_PRELIM (CFG_BCSR | 0x00001801) +#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 #define CFG_OR1_PRELIM 0xFFFF8010 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 3659002d5..4953b7053 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -83,7 +83,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ @@ -140,32 +141,40 @@ */ #define SPD_EEPROM_ADDRESS 0x50 + #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #define CONFIG_BAUDRATE 115200 -/* - * Command line configuration. - */ -#include -/* Commands we want, that are not part of default set */ -#define CONFIG_CMD_ASKENV /* ask for env variable */ -#define CONFIG_CMD_CACHE /* icache, dcache */ -#define CONFIG_CMD_DHCP /* DHCP Support */ -#define CONFIG_CMD_DIAG /* Diagnostics */ -#define CONFIG_CMD_IMMAP /* IMMR dump support */ -#define CONFIG_CMD_IRQ /* irqinfo */ -#define CONFIG_CMD_MII /* MII support */ -#define CONFIG_CMD_PCI /* pciinfo */ -#define CONFIG_CMD_PING /* ping support */ -#define CONFIG_CMD_PORTIO /* Port I/O */ -#define CONFIG_CMD_REGINFO /* Register dump */ -#define CONFIG_CMD_SAVES /* save S record dump */ -#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ - -/* Commands from default set we don't need */ -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ +#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_MMC | \ + CFG_CMD_NAND | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_REISER | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_SNTP | \ + CFG_CMD_VFD | \ + CFG_CMD_UNIVERSE | \ + CFG_CMD_USB | \ + CFG_CMD_XIMG ) ) /* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. @@ -193,19 +202,21 @@ "bootm" #endif /* CONFIG_BOOT_ROOT_NFS */ -/* - * BOOTP options +/* Add support for a few extra bootp options like: + * - File size + * - DNS */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -220,7 +231,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -272,6 +283,7 @@ #define SDRAM_SPD_ADDR 0x50 + /*----------------------------------------------------------------------- * BR2,BR3 - Base Register * Ref: Section 10.3.1 on page 10-14 @@ -369,6 +381,7 @@ #error "INVALID SDRAM CONFIGURATION" #endif + #define RS232EN_1 0x02000002 #define RS232EN_2 0x01000001 #define FETHIEN 0x08000008 @@ -380,6 +393,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + /* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */ /* 0x0EB2B645 */ #define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\ @@ -436,11 +450,13 @@ # define CFG_ENV_SIZE 0x200 #endif /* CFG_RAMBOOT */ + #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif + /*----------------------------------------------------------------------- * HIDx - Hardware Implementation-dependent Registers 2-11 *----------------------------------------------------------------------- diff --git a/include/configs/MPC8349ADS.h b/include/configs/MPC8349ADS.h new file mode 100644 index 000000000..d6d2fabee --- /dev/null +++ b/include/configs/MPC8349ADS.h @@ -0,0 +1,584 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mpc8349ads board configuration file + * + * Please refer to doc/README.mpc83xxads for more info. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +#define CONFIG_MII + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC8349 1 /* MPC8349 specific */ +#define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */ + +/* FIXME: Real PCI support will come in a follow-up update. */ +#undef CONFIG_PCI + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ + +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ + +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#endif +#endif + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMRBAR 0xE0000000 + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ + +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#undef CONFIG_DDR_2T_TIMING +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE + +#if defined(CONFIG_SPD_EEPROM) + /* + * Determine DDR configuration from I2C interface. + */ + #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ +#else + /* + * Manually set up DDR parameters + */ + #define CFG_DDR_SIZE 256 /* Mb */ + #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) + #define CFG_DDR_TIMING_1 0x37344321 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ + #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ + #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ + #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ +#endif + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ +/* #define CFG_FLASH_USE_BUFFER_WRITE */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM 0xff806ff7 /* 16Mb Flash size*/ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MID_FLASH_JUMP 0x7F000000 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +/* + * BCSR register on local bus 32KB, 8-bit wide for ADS config reg + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ +#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ + +#ifdef CFG_LB_SDRAM +/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/ +#define CFG_LBLAWBAR2_PRELIM 0xF0000000 +#define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ + | CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR8 \ + | CFG_LBC_LSDMR_PRETOACT6 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC3 \ + | CFG_LBC_LSDMR_CL3 \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) + +/* IO Configuration */ +#define CFG_IO_CONF (\ + IO_CONF_UART |\ + IO_CONF_TSEC1 |\ + IO_CONF_IRQ0 |\ + IO_CONF_IRQ1 |\ + IO_CONF_IRQ2 |\ + IO_CONF_IRQ3 |\ + IO_CONF_IRQ4 |\ + IO_CONF_IRQ5 |\ + IO_CONF_IRQ6 |\ + IO_CONF_IRQ7 ) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + +#define CFG_PCI2_MEM_BASE 0xA0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe3000000 +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#if defined(CONFIG_PCI) + +#define PCI_ALL_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +#if defined(CONFIG_TSEC_ENET) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_GMII 1 /* MII PHY management */ +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + ) +#endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) + +#if defined(PCI_64BIT) +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +#define CFG_HID0_INIT 0x000000000 + +#define CFG_HID0_FINAL CFG_HID0_INIT + +/* #define CFG_HID0_FINAL (\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_ENABLE_M_BIT |\ + HID0_ENABLE_ADDRESS_BROADCAST ) */ + +#define CFG_HID2 0x000000000 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:04:9f:11:22:33 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01 +#endif + +#define CONFIG_IPADDR 192.168.1.253 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=ramfs.83xx\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 870583845..66f164660 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -29,17 +29,18 @@ #ifndef __CONFIG_H #define __CONFIG_H +#undef DEBUG + /* * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC834X 1 /* MPC834X family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ #undef CONFIG_PCI -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ #define PCI_66M #ifdef PCI_66M @@ -60,7 +61,7 @@ #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ -#define CFG_IMMR 0xE0000000 +#define CFG_IMMRBAR 0xE0000000 #undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00000000 /* memtest region */ @@ -69,7 +70,7 @@ /* * DDR Setup */ -#define CONFIG_DDR_ECC /* support DDR ECC function */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ @@ -88,15 +89,8 @@ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING -/* - * DDRCDR - DDR Control Driver Register - */ -#define CFG_DDRCDR_VALUE 0x80080001 - #if defined(CONFIG_SPD_EEPROM) /* * Determine DDR configuration from I2C interface. @@ -107,21 +101,6 @@ * Manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* MB */ -#if defined(CONFIG_DDR_II) -#define CFG_DDRCDR 0x80080001 -#define CFG_DDR_CS2_BNDS 0x0000000f -#define CFG_DDR_CS2_CONFIG 0x80330102 -#define CFG_DDR_TIMING_0 0x00220802 -#define CFG_DDR_TIMING_1 0x38357322 -#define CFG_DDR_TIMING_2 0x2f9048c8 -#define CFG_DDR_TIMING_3 0x00000000 -#define CFG_DDR_CLK_CNTL 0x02000000 -#define CFG_DDR_MODE 0x47d00432 -#define CFG_DDR_MODE2 0x8000c000 -#define CFG_DDR_INTERVAL 0x03cf0080 -#define CFG_DDR_SDRAM_CFG 0x43000000 -#define CFG_DDR_SDRAM_CFG2 0x00401000 -#else #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) #define CFG_DDR_TIMING_1 0x36332321 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ @@ -136,7 +115,6 @@ #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ #endif #endif -#endif /* * SDRAM on the Local Bus @@ -150,20 +128,19 @@ #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 32 /* max flash size in MB */ +#define CFG_FLASH_SIZE 8 /* flash size in MB */ /* #define CFG_FLASH_USE_BUFFER_WRITE */ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ BR_V) /* valid */ -#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ +#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ @@ -208,11 +185,7 @@ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) #define CFG_LBC_LBCR 0x00000000 -/* - * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. - * if board has SRDAM on local bus, you can define CFG_LB_SDRAM - */ -#undef CFG_LB_SDRAM +#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ #ifdef CFG_LB_SDRAM /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ @@ -326,47 +299,29 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) +#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ /* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 -/* SPI */ -#define CONFIG_MPC8XXX_SPI -#undef CONFIG_SOFT_SPI /* SPI bit-banged */ - -/* GPIOs. Used as SPI chip selects */ -#define CFG_GPIO1_PRELIM -#define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ -#define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */ - /* TSEC */ #define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) #define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) +#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) /* USB */ #define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ @@ -413,7 +368,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xFIXME #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -432,16 +387,14 @@ #endif #define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -459,7 +412,7 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 @@ -477,35 +430,44 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - #if defined(CFG_RAMBOOT) - #undef CONFIG_CMD_ENV - #undef CONFIG_CMD_LOADS +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C \ + | CFG_CMD_DATE) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_DATE) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_DATE \ + ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + | CFG_CMD_DATE \ + ) +#endif #endif +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -516,7 +478,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -534,6 +496,13 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ #if 1 /*528/264*/ @@ -601,16 +570,6 @@ HRCWH_TSEC2M_IN_GMII ) #endif -/* - * System performance - */ -#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ -#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ -#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ - /* System IO Config */ #define CFG_SICRH SICRH_TSOBI1 #define CFG_SICRL SICRL_LDP_A @@ -625,7 +584,6 @@ #define CFG_HID2 HID2_HBE -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) @@ -657,8 +615,8 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) @@ -692,7 +650,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -705,21 +663,20 @@ #if defined(CONFIG_TSEC_ENET) #define CONFIG_ETHADDR 00:04:9f:ef:23:33 #define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH0 #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 #endif -#define CONFIG_IPADDR 192.168.1.253 +#define CONFIG_IPADDR 192.168.205.5 #define CONFIG_HOSTNAME mpc8349emds -#define CONFIG_ROOTPATH /nfsroot/rootfs -#define CONFIG_BOOTFILE uImage +#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx +#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -727,7 +684,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -746,31 +703,14 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=/tftpboot/mpc8349emds/uImage\0" \ "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ "update=protect off fe000000 fe03ffff; " \ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ - "upd=run load update\0" \ - "fdtaddr=400000\0" \ - "fdtfile=mpc8349emds.dtb\0" \ + "upd=run load;run update\0" \ "" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - #define CONFIG_BOOTCOMMAND "run flash_self" #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index d1d3cc360..131c83224 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -46,7 +46,7 @@ #endif #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -55,7 +55,6 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx @@ -69,10 +68,6 @@ * The board, however, can run at 66MHz. In any event, this value * must match the settings of some switches. Details can be found * in the README.mpc85xxads. - * - * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to - * 33MHz to accommodate, based on a PCI pin. - * Note that PCI-X won't work at 33MHz. */ #ifndef CONFIG_SYS_CLK_FREQ @@ -87,6 +82,9 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 @@ -95,9 +93,8 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -144,7 +141,7 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -265,16 +262,16 @@ #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -296,24 +293,12 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -#define CFG_64BIT_VSPRINTF 1 -#define CFG_64BIT_STRTOUL 1 - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ @@ -322,19 +307,19 @@ /* * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. + * Addresses are mapped 1-1. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -342,7 +327,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -354,20 +339,18 @@ #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT #if CONFIG_HAS_FEC @@ -375,7 +358,6 @@ #define CONFIG_MPC85XX_FEC_NAME "FEC" #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 -#define FEC_FLAGS 0 #endif /* Options are: TSEC[0-1], FEC */ @@ -402,34 +384,37 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ELF - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - #if defined(CFG_RAMBOOT) - #undef CONFIG_CMD_ENV - #undef CONFIG_CMD_LOADS + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif #endif +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -437,11 +422,10 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -459,6 +443,13 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + /* * Internal Definitions * @@ -467,7 +458,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -479,7 +470,6 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD @@ -507,10 +497,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -518,16 +506,14 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "bootm $loadaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" + "bootm $loadaddr $ramdiskaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index b13c81c2e..1af923103 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -30,21 +30,19 @@ #ifndef __CONFIG_H #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_MPC8540 1 /* MPC8540 specific */ #define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */ -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_PCI /* pci ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - /* Using Localbus SDRAM to emulate flash before we can program the flash, * normally you only need a flash-boot image(u-boot.bin),if unsure undef this. * Not availabe for EVAL board @@ -63,7 +61,7 @@ #endif /* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #undef CONFIG_BTB /* toggle branch predition */ #undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ @@ -81,9 +79,8 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ @@ -113,7 +110,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/ #define CFG_FLASH_CFI 1 -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -150,16 +147,16 @@ #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -168,7 +165,7 @@ #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} @@ -182,16 +179,12 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 /* General PCI */ #define CFG_PCI_MEM_BASE 0x80000000 @@ -203,26 +196,23 @@ #define CONFIG_NET_MULTI #undef CONFIG_EEPRO100 #define CONFIG_TULIP -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 -#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ +#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ #endif #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #define CFG_PCI_SUBSYS_DEVICEID 0x0008 #elif defined(CONFIG_TSEC_ENET) -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define CONFIG_MPC85XX_FEC 1 -#define CONFIG_HAS_ETH2 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define TSEC1_PHY_ADDR 7 #define TSEC2_PHY_ADDR 4 @@ -230,10 +220,6 @@ #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define FEC_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define FEC_FLAGS 0 - /* Options are: TSEC[0-1], FEC */ #define CONFIG_ETHPRIME "TSEC0" @@ -241,6 +227,8 @@ #define INTEL_LXT971_PHY 1 #endif +#undef DEBUG + /* Environment */ #ifndef CFG_RAMBOOT #if defined(CONFIG_RAM_AS_FLASH) @@ -262,38 +250,31 @@ #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" #define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ +#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #undef CONFIG_CMD_ENV - #undef CONFIG_CMD_LOADS +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \ + | CFG_CMD_PCI | CFG_CMD_I2C ) & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS )) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \ + | CFG_CMD_I2C ) & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS )) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ + | CFG_CMD_PING | CFG_CMD_I2C ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) +#endif #endif +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -303,7 +284,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -318,7 +299,14 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Internal Definitions @@ -328,7 +316,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index a64565db9..c96b98b54 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -38,7 +38,7 @@ #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -47,10 +47,6 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_FSL_VIA -#define CONFIG_FSL_CDS_EEPROM /* * When initializing flash, if we cannot find the manufacturer ID, @@ -69,10 +65,13 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 @@ -80,9 +79,8 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* @@ -152,7 +150,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -274,23 +272,21 @@ extern unsigned long get_clock_freq(void); * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ -#define CONFIG_FSL_CADMUS - #define CADMUS_BASE_ADDR 0xf8000000 #define CFG_BR3_PRELIM 0xf8000801 #define CFG_OR3_PRELIM 0xfff00ff7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -312,58 +308,47 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 /* * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. + * Addresses are mapped 1-1. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe2100000 -#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif #if defined(CONFIG_PCI) -#define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ +#endif + #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ @@ -373,20 +358,21 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 +#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT +#define FEC_PHYIDX 0 /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -404,29 +390,19 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF - #if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) #endif - +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -434,10 +410,9 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -452,7 +427,14 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif /* * Internal Definitions @@ -462,7 +444,7 @@ extern unsigned long get_clock_freq(void); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -473,7 +455,6 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD @@ -501,10 +482,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -512,8 +491,7 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "bootm $loadaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index acf6f0dce..4ca8bc35d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004 Freescale Semiconductor. * * See file CREDITS for list of people who contributed to this * project. @@ -11,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -36,29 +36,17 @@ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ -#define CONFIG_PCI /* enable any pci type devices */ -#define CONFIG_PCI1 /* PCI controller 1 */ -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#undef CONFIG_RIO -#undef CONFIG_PCI2 -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ - -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_PCI +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_FSL_VIA -#define CONFIG_FSL_CDS_EEPROM /* * When initializing flash, if we cannot find the manufacturer ID, @@ -77,16 +65,19 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ /* * Only possible on E500 Version 2 or newer cores. */ #define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 @@ -94,15 +85,10 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) -#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) -#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) - /* * DDR Setup */ @@ -120,6 +106,7 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_CLOCKS_IN_MHZ + /* * Local Bus Definitions */ @@ -137,9 +124,9 @@ extern unsigned long get_clock_freq(void); * Use GPCM = BRx[24:26] = 000 * Valid = BRx[31] = 1 * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 + * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 * * OR0, OR1: * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 @@ -150,12 +137,11 @@ extern unsigned long get_clock_freq(void); * TRLX = use relaxed timing = ORx[29] = 1 * EAD = use external address latch delay = OR[31] = 1 * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx */ -#define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */ -#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */ +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ #define CFG_BR0_PRELIM 0xff801001 #define CFG_BR1_PRELIM 0xff001001 @@ -170,7 +156,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -180,12 +166,7 @@ extern unsigned long get_clock_freq(void); /* * SDRAM on the Local Bus */ -#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ -#define CFG_LBC_CACHE_SIZE 64 -#define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ -#define CFG_LBC_NONCACHE_SIZE 64 - -#define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ /* @@ -199,14 +180,14 @@ extern unsigned long get_clock_freq(void); * SDRAM for MSEL = BR2[24:26] = 011 * Valid = BR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 * * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into * FIXME: the top 17 bits of BR2. */ -#define CFG_BR2_PRELIM 0xf0001861 +#define CFG_BR2_PRELIM 0xf0001861 /* * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. @@ -215,19 +196,19 @@ extern unsigned long get_clock_freq(void); * 64MB mask for AM, OR2[0:7] = 1111 1100 * XAM, OR2[17:18] = 11 * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 + * 13 rows OR2[23-25] = 100 * EAD set for extra time OR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */ #define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ /* * LSDMR masks @@ -255,7 +236,7 @@ extern unsigned long get_clock_freq(void); /* * Common settings for all Local Bus SDRAM commands. * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) + * or BSMA1617 (for CPU 1.0) (old) * is OR'ed in too. */ #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ @@ -275,146 +256,107 @@ extern unsigned long get_clock_freq(void); * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 * port-size = 8-bits = BR[19:20] = 01 * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 + * GPMC for MSEL = BR[24:26] = 000 + * Valid = BR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 * * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 + * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 + * CSNT OR[20] = 1 + * ACS OR[21:22] = 11 + * XACS OR[23] = 1 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 + * SETA OR[28] = 0 + * TRLX OR[29] = 1 + * EHTR OR[30] = 1 + * EAD extra time OR[31] = 1 * - * 0 4 8 12 16 20 24 28 + * 0 4 8 12 16 20 24 28 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ -#define CONFIG_FSL_CADMUS - #define CADMUS_BASE_ADDR 0xf8000000 -#define CFG_BR3_PRELIM 0xf8000801 -#define CFG_OR3_PRELIM 0xfff00ff7 +#define CFG_BR3_PRELIM 0xf8000801 +#define CFG_OR3_PRELIM 0xfff00ff7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ - -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ -#define CONFIG_CONS_INDEX 2 +#define CONFIG_CONS_INDEX 2 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) -#define CFG_BAUDRATE_TABLE \ +#define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ /* * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. + * Addresses are mapped 1-1. */ -#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ -#ifdef CONFIG_PCI2 #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe2800000 -#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ -#endif +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ -#ifdef CONFIG_PCIE1 -#define CFG_PCIE1_MEM_BASE 0xa0000000 -#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE -#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCIE1_IO_BASE 0x00000000 -#define CFG_PCIE1_IO_PHYS 0xe3000000 -#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ -#endif - -#ifdef CONFIG_RIO -/* - * RapidIO MMU - */ -#define CFG_RIO_MEM_BASE 0xC0000000 -#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ -#endif - -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ +#endif -/* PCI view of System Memory */ -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x80000000 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ @@ -422,37 +364,35 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC2" -#define CONFIG_TSEC4 -#define CONFIG_TSEC4_NAME "eTSEC3" +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" +#define CONFIG_MPC85XX_TSEC3 1 +#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" +#define CONFIG_MPC85XX_TSEC4 1 +#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 #define TSEC4_PHY_ADDR 3 +#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 #define TSEC4_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define FEC_PHYIDX 0 /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + #endif /* CONFIG_TSEC_ENET */ /* @@ -466,29 +406,19 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF - #if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) #endif - +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -496,10 +426,9 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -514,7 +443,14 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif /* * Internal Definitions @@ -524,7 +460,7 @@ extern unsigned long get_clock_freq(void); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -535,67 +471,51 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:E0:0C:00:00:FD +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD #endif -#define CONFIG_IPADDR 192.168.1.253 +#define CONFIG_IPADDR 192.168.1.253 -#define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE 8548cds/uImage.uboot -#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /nfsroot +#define CONFIG_BOOTFILE your.uImage -#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ +#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=mpc8548cds.dtb\0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 1948c0d27..a44e3ec84 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -38,7 +38,7 @@ #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -47,10 +47,6 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#define CONFIG_FSL_VIA -#define CONFIG_FSL_CDS_EEPROM /* * When initializing flash, if we cannot find the manufacturer ID, @@ -69,10 +65,13 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ #define CFG_MEMTEST_END 0x00400000 @@ -80,9 +79,8 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* @@ -152,7 +150,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -274,23 +272,21 @@ extern unsigned long get_clock_freq(void); * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ -#define CONFIG_FSL_CADMUS - #define CADMUS_BASE_ADDR 0xf8000000 #define CFG_BR3_PRELIM 0xf8000801 #define CFG_OR3_PRELIM 0xfff00ff7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -312,22 +308,13 @@ extern unsigned long get_clock_freq(void); #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 /* * General PCI @@ -336,35 +323,33 @@ extern unsigned long get_clock_freq(void); #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0x00000000 -#define CFG_PCI2_IO_PHYS 0xe2100000 -#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ +#define CFG_PCI2_IO_BASE 0xe3000000 +#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE +#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_MPC85XX_PCI2 +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ @@ -373,20 +358,21 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 +#define FEC_PHY_ADDR 3 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT +#define FEC_PHYIDX 0 /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -404,29 +390,19 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_ELF - #if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII) #endif - +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -434,10 +410,9 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -452,7 +427,14 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif /* * Internal Definitions @@ -462,7 +444,7 @@ extern unsigned long get_clock_freq(void); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -473,7 +455,6 @@ extern unsigned long get_clock_freq(void); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD @@ -501,10 +482,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -512,8 +491,7 @@ extern unsigned long get_clock_freq(void); "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "bootm $loadaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 272121627..2d5031b77 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -40,11 +40,12 @@ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ -#define CONFIG_MPC8560 1 #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -53,7 +54,6 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx @@ -81,8 +81,11 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ +#undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 @@ -91,9 +94,8 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -140,7 +142,7 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -261,23 +263,23 @@ #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ #undef CONFIG_CONS_NONE /* define if console on something else */ #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} @@ -288,21 +290,12 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ @@ -311,19 +304,19 @@ /* * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. + * Addresses are mapped 1-1. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0x00000000 -#define CFG_PCI1_IO_PHYS 0xe2000000 -#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ +#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -331,7 +324,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -340,34 +333,30 @@ #endif /* CONFIG_PCI */ -#ifdef CONFIG_TSEC_ENET +#if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif -#ifndef CONFIG_MII #define CONFIG_MII 1 /* MII PHY management */ -#endif -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" -#endif /* CONFIG_TSEC_ENET */ +#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ -#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ - -#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ #if (CONFIG_ETHER_INDEX == 2) @@ -385,12 +374,9 @@ #elif (CONFIG_ETHER_INDEX == 3) /* need more definitions here for FE3 */ #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -#ifndef CONFIG_MII -#define CONFIG_MII 1 /* MII PHY management */ -#endif +#endif /* CONFIG_ETHER_INDEX */ +#define CONFIG_MII /* MII PHY management */ #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ /* @@ -430,37 +416,46 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ELF - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - #if defined(CFG_RAMBOOT) - #undef CONFIG_CMD_ENV - #undef CONFIG_CMD_LOADS + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #elif defined(CONFIG_TSEC_ENET) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_ENV)) + #elif defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_ENV)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #elif defined(CONFIG_TSEC_ENET) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #elif defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif #endif +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -468,11 +463,10 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x1000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -490,6 +484,13 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + /* * Internal Definitions * @@ -498,7 +499,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -510,14 +511,11 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_HAS_ETH2 #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.1.253 @@ -538,29 +536,25 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyCPM\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=mpc8560ads.dtb\0" + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=400000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" #define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "bootm $loadaddr $ramdiskaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h index 233a8d19f..831cc5ecd 100644 --- a/include/configs/MPC86xADS.h +++ b/include/configs/MPC86xADS.h @@ -22,7 +22,7 @@ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ /* CPU type - pick one of these */ -#define CONFIG_MPC866T 1 +#define CONFIG_MPC866T 1 #undef CONFIG_MPC866P #undef CONFIG_MPC859T #undef CONFIG_MPC859DSL @@ -41,7 +41,7 @@ #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1 -#include "../../board/fads/fads.h" +#include "fads.h" #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) diff --git a/include/configs/MPC885ADS.h b/include/configs/MPC885ADS.h index f4d184277..1867c5bf0 100644 --- a/include/configs/MPC885ADS.h +++ b/include/configs/MPC885ADS.h @@ -27,7 +27,7 @@ #define CONFIG_SDRAM_50MHZ 1 -#include "../../board/fads/fads.h" +#include "fads.h" #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h index 4319e6c04..da52e0ec0 100644 --- a/include/configs/MUSENKI.h +++ b/include/configs/MUSENKI.h @@ -52,20 +52,11 @@ #define CONFIG_BOOTDELAY 5 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ - -/* - * Command line configuration. - */ -#include +#include /* @@ -86,7 +77,7 @@ * PCI stuff *----------------------------------------------------------------------- */ -#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP #define CONFIG_NET_MULTI /* Multi ethernet cards support */ @@ -289,7 +280,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h index 8e247af63..88eefa190 100644 --- a/include/configs/MVBLUE.h +++ b/include/configs/MVBLUE.h @@ -28,16 +28,16 @@ #define MV_VERSION "v0.2.0" /* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */ -#define ERR_NONE 0 -#define ERR_ENV 1 -#define ERR_BOOTM_BADMAGIC 2 -#define ERR_BOOTM_BADCRC 3 -#define ERR_BOOTM_GUNZIP 4 +#define ERR_NONE 0 +#define ERR_ENV 1 +#define ERR_BOOTM_BADMAGIC 2 +#define ERR_BOOTM_BADCRC 3 +#define ERR_BOOTM_GUNZIP 4 #define ERR_BOOTP_TIMEOUT 5 -#define ERR_DHCP 6 -#define ERR_TFTP 7 -#define ERR_NOLAN 8 -#define ERR_LANDRV 9 +#define ERR_DHCP 6 +#define ERR_TFTP 7 +#define ERR_NOLAN 8 +#define ERR_LANDRV 9 #define CONFIG_BOARD_TYPES 1 #define MVBLUE_BOARD_BOX 1 @@ -45,91 +45,63 @@ #if 0 #define ERR_LED(code) do { if (code) \ - *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \ - else \ - *(volatile char *)(0xff000003) = ( 1 ); \ -} while(0) + *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \ + else \ + *(volatile char *)(0xff000003) = ( 1 ); \ + } while(0) #else #define ERR_LED(code) #endif +#undef DEBUG + #define CONFIG_MPC824X 1 #define CONFIG_MPC8245 1 #define CONFIG_MVBLUE 1 #define CONFIG_CLOCKS_IN_MHZ 1 -#define CONFIG_BOARD_TYPES 1 +#define CONFIG_BOARD_TYPES 1 #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 3 #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "autoboot in %d seconds (stop with 's')...\n", bootdelay +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 's')...\n" #define CONFIG_AUTOBOOT_STOP_STR "s" #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_RESET_TO_RETRY 60 - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_NET -#define CONFIG_CMD_PCI -#define CONFIG_CMD_RUN +#define CONFIG_COMMANDS ( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP | \ + CFG_CMD_ECHO | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IMI | \ + CFG_CMD_IRQ | CFG_CMD_NET | CFG_CMD_PCI | CFG_CMD_RUN ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_NTPSERVER -#define CONFIG_BOOTP_TIMEOFFSET +#define CONFIG_BOOTP_MASK ( 0xffffffff ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* Max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 /* Default load address */ -#define CONFIG_BOOTCOMMAND "run nfsboot" +#define CONFIG_BOOTCOMMAND "run nfsboot" #define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2" -#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm" +#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm" #define CONFIG_EXTRA_ENV_SETTINGS \ "console_nr=0\0" \ @@ -157,11 +129,11 @@ #define CONFIG_PCI_SCAN_SHOW #define CONFIG_NET_MULTI -#define CONFIG_NET_RETRY_COUNT 5 +#define CONFIG_NET_RETRY_COUNT 5 #define CONFIG_TULIP #define CONFIG_TULIP_FIX_DAVICOM 1 -#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 +#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 #define CONFIG_HW_WATCHDOG @@ -225,7 +197,7 @@ */ #define CONFIG_SYS_CLK_FREQ 33000000 -#define CFG_HZ 10000 +#define CFG_HZ 10000 /* Bit-field values for MCCR1. */ #define CFG_ROMNAL 7 @@ -338,7 +310,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h index 87458e362..599591826 100644 --- a/include/configs/MVS1.h +++ b/include/configs/MVS1.h @@ -43,19 +43,16 @@ #undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */ #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ #undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ +#define CONFIG_BAUDRATE 115200 /* console baudrate */ #define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */ -#define CONFIG_PREBOOT "echo;" \ - "echo To mount root over NFS use \"run bootnet\";" \ - "echo To mount root from FLASH use \"run bootflash\";" \ - "echo" +#define CONFIG_PREBOOT "echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use \"run bootflash\";echo" #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ @@ -64,38 +61,29 @@ #undef CONFIG_STATUS_LED /* Status LED disabled/enabled */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_VENDOREX +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX ) #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +/* MVsensor uses a really minimal U-Boot ! */ +#define CONFIG_COMMANDS (CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_IMI | \ + CFG_CMD_FLASH | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_DHCP | \ + CFG_CMD_ENV | \ + CFG_CMD_BOOTD | \ + CFG_CMD_RUN ) -/* - * Command line configuration. - */ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_IMI -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_RUN - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -103,12 +91,12 @@ #undef CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -184,7 +172,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -196,7 +184,7 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif @@ -270,8 +258,8 @@ #define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ #define CFG_IDE_MAXBUS 0 /* max. no. of IDE buses */ diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 84c6e9b61..8da29c4af 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de + * (C) Copyright 2006 Detlev Zundel, dzu@denx.de * (C) Copyright 2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -65,36 +65,27 @@ #define CFG_MEASURE_CPUCLK #define CFG_8XX_XIN CONFIG_8xx_OSCLK -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d seconds...\n", bootdelay +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d seconds...\n" #define CONFIG_AUTOBOOT_DELAY_STR "ids" #define CONFIG_BOOT_RETRY_TIME 900 #define CONFIG_BOOT_RETRY_MIN 30 -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" -#define CONFIG_WATCHDOG /* watchdog enabled */ +#define CONFIG_WATCHDOG /* watchdog enabled */ #undef CONFIG_STATUS_LED /* Status LED disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_FEC_ENET 1 /* use FEC ethernet */ #define FEC_ENET @@ -143,28 +134,25 @@ #define CONFIG_RTC_PCF8563 #define CFG_I2C_RTC_ADDR 0x51 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_NAND | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NAND -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -176,7 +164,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -242,15 +230,25 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif /* * NAND flash support */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 +#define NAND_ChipID_UNKNOWN 0x00 +#define SECTORSIZE 512 +#define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define ADDR_COLUMN 1 +#define NAND_NO_RB + /*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index 27e7ab9bc..444f721cc 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -66,7 +66,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ + "tftpboot; " \ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" @@ -82,30 +82,21 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY #define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 #define CONFIG_RMII 1 /* use RMII interface */ #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ +#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ #define CONFIG_FEC1_PHY_NORXERR 1 #define CONFIG_ETHER_ON_FEC2 1 @@ -114,22 +105,20 @@ #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_CMD_CDP - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_NAND | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_MII | \ + CFG_CMD_CDP \ + ) #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ @@ -139,7 +128,7 @@ #define CFG_HUSH_PARSER 1 #define CFG_PROMPT_HUSH_PS2 "> " -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -231,7 +220,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -292,27 +281,27 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 25000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 40000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 75000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 10MHz #endif @@ -322,15 +311,15 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 66666666 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 50MHz #endif @@ -514,7 +503,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 56c76d325..25b63457c 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -60,11 +60,11 @@ #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ + "tftpboot; " \ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" @@ -77,40 +77,30 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY /* do not discover phys */ #define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 #define CONFIG_RMII 1 /* use RMII interface */ #if defined(CONFIG_NETTA_ISDN) #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ +#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ #define CONFIG_FEC1_PHY_NORXERR 1 #undef CONFIG_ETHER_ON_FEC2 #else #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ +#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ #define CONFIG_FEC1_PHY_NORXERR 1 #define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ +#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ #define CONFIG_FEC2_PHY_NORXERR 1 #endif @@ -121,28 +111,26 @@ CFG_POST_CODEC | \ CFG_POST_DSP ) - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_PING - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_CDP | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_FAT | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_PING | \ + 0) #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ @@ -152,7 +140,7 @@ #define CFG_HUSH_PARSER 1 #define CFG_PROMPT_HUSH_PS2 "> " -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -235,7 +223,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -296,27 +284,27 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 25000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 40000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 75000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 10MHz #endif @@ -326,19 +314,19 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 80000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 50MHz #endif @@ -633,7 +621,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index b8c48482a..e20e72495 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -66,9 +66,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_AUTOSCRIPT @@ -82,31 +82,21 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY #define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 #define CONFIG_RMII 1 /* use RMII interface */ #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ +#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ #define CONFIG_FEC1_PHY_NORXERR 1 #define CONFIG_ETHER_ON_FEC2 1 @@ -115,22 +105,20 @@ #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_CMD_CDP - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_NAND | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_MII | \ + CFG_CMD_CDP \ + ) #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ @@ -140,7 +128,7 @@ #define CFG_HUSH_PARSER 1 #define CFG_PROMPT_HUSH_PS2 "> " -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -232,7 +220,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -293,27 +281,27 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 25000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 40000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 75000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 10MHz #endif @@ -323,15 +311,15 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 66666666 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 50MHz #endif @@ -515,7 +503,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index 1293fb0e2..e30be0987 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -59,13 +59,13 @@ #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ @@ -81,45 +81,35 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_NISDOMAIN - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING +#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING ) #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -#define CONFIG_CMD_NAND +#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE | CFG_CMD_NAND) +#else +#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE #endif - #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -202,7 +192,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -411,7 +401,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index 21d90c303..d99442009 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -48,7 +48,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -67,16 +67,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=NSCU\0" \ - "bootfile=${hostname}/uImage\0" \ + "bootfile=/tftpboot/NSCU/uImage\0" \ "kernel_addr=40080000\0" \ "ramdisk_addr=40180000\0" \ - "u-boot=${hostname}/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -91,15 +84,7 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -108,23 +93,16 @@ #define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -132,14 +110,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history -*/ +#if 0 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -197,26 +175,21 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -228,7 +201,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -311,8 +284,8 @@ #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) #define CFG_PCMCIA_IO_ADDR (0xEC000000) #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ -#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ +#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ +#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ #undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ /*----------------------------------------------------------------------- diff --git a/include/configs/NX823.h b/include/configs/NX823.h index 2a4bd4724..1cb8b8ff3 100644 --- a/include/configs/NX823.h +++ b/include/configs/NX823.h @@ -47,7 +47,7 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */ #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ -#define CONFIG_BOOTARGS "ramdisk_size=8000 "\ +#define CONFIG_BOOTARGS "ramdisk=8000 "\ "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\ "nfsaddrs=10.77.77.20:10.77.77.250" #define CONFIG_BOOTCOMMAND "bootm 400e0000" @@ -55,35 +55,22 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled, for now */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT) #define CONFIG_AUTOSCRIPT -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_AUTOSCRIPT - - /* call various generic functions */ #define CONFIG_MISC_INIT_R +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -127,7 +114,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ @@ -165,7 +152,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 94b5bc965..aa9d1ba73 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -54,32 +54,20 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ELF -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ELF | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -89,7 +77,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -222,6 +210,15 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 4e030885f..2e7c505f9 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -54,32 +54,20 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ELF -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ASKENV | \ + CFG_CMD_ELF | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -89,7 +77,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -220,6 +208,15 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/OXC.h b/include/configs/OXC.h index 8d61bcd2d..787407c5e 100644 --- a/include/configs/OXC.h +++ b/include/configs/OXC.h @@ -51,23 +51,10 @@ #define CONFIG_BAUDRATE 9600 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ELF - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -312,7 +299,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h index 5a2d15770..a933e1b18 100644 --- a/include/configs/P3G4.h +++ b/include/configs/P3G4.h @@ -42,7 +42,7 @@ #define CONFIG_P3G4 1 /* this is a P3G4 board */ #define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ #undef CONFIG_ECC /* enable ECC support */ /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ @@ -81,7 +81,7 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -110,7 +110,7 @@ "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ "cp.b 100000 fff00000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ + "upd=run load;run update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -120,40 +120,30 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_UNIVERSE| \ + CFG_CMD_BSP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_UNIVERSE -#define CONFIG_CMD_BSP - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -406,7 +396,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -417,8 +407,8 @@ #define CFG_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #define L2_ENABLE (L2_INIT | L2CR_L2E) diff --git a/include/configs/PATI.h b/include/configs/PATI.h index 4b37eca7c..d88fff33e 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -32,53 +32,32 @@ */ #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_PATI 1 /* ...On a PATI board */ +#define CONFIG_PATI 1 /* ...On a PATI board */ /* Serial Console Configuration */ #define CONFIG_5xx_CONS_SCI1 #undef CONFIG_5xx_CONS_SCI2 #define CONFIG_BAUDRATE 9600 +#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \ + CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV | CFG_CMD_REGINFO | \ + CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP | \ + CFG_CMD_IMI | CFG_CMD_EEPROM | CFG_CMD_IRQ | CFG_CMD_MISC \ +) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_ENV -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_RUN -#define CONFIG_CMD_BSP -#define CONFIG_CMD_IMI -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MISC - +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_BOOTCOMMAND "" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "" /* autoboot command */ #define CONFIG_BOOTARGS "" /* */ -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ +#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ /*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ @@ -92,7 +71,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "pati=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -123,30 +102,30 @@ /* * Internal Memory Mapped (This is not the IMMR content) */ -#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ +#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ /* * Definitions for initial stack pointer and data area */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ +#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ +#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ +#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ /* * Start addresses for the final memory configuration * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ +#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ #define CFG_FLASH_BASE 0xffC00000 /* External flash */ #define PCI_BASE 0x03000000 /* PCI Base (CS2) */ #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ #define CFG_MONITOR_BASE 0xFFF00000 -/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ +/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ + /* This adress is given to the linker with -Ttext to */ + /* locate the text section at this adress. */ #define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ @@ -167,9 +146,9 @@ */ #define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ +#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_EEPROM @@ -180,8 +159,8 @@ #undef CFG_ENV_IS_IN_FLASH #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */ -#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */ +#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */ +#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */ #endif @@ -233,7 +212,7 @@ *----------------------------------------------------------------------- * Data show cycle */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register @@ -241,7 +220,7 @@ * Set all bits to 40 Mhz * */ -#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ +#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ #define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) @@ -251,12 +230,12 @@ *----------------------------------------------------------------------- * */ -#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ +#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ +#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ /*----------------------------------------------------------------------- * USIU - Memory Controller Register diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index e70c0d3d4..9d5c4f4d0 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -1,9 +1,6 @@ /* - * (C) Copyright 2007 - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com - * * (C) Copyright 2001-2004 - * Stefan Roese, DENX Software Engineering, sr@denx.de. + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * * See file CREDITS for list of people who contributed to this * project. @@ -35,6 +32,8 @@ * High Level Configuration Options * (easy to change) */ +#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $" + #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PCI405 1 /* ...on a PCI405 board */ @@ -54,9 +53,9 @@ "mem_linux=14336k\0" \ "optargs=panic=0\0" \ "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \ - "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ + "addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ "" -#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci" +#define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci" #define CONFIG_PREBOOT /* enable preboot variable */ @@ -68,29 +67,17 @@ #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -109,7 +96,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -251,6 +238,15 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index abb9bfc25..3a7f7f064 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -54,10 +54,10 @@ /*------------------------------------------------------------------------ * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -Monitor at top. + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ @@ -87,7 +87,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ #define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ #define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) +#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) /*------------------------------------------------------------------------ * CONSOLE @@ -122,32 +122,22 @@ #define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) #define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include /*------------------------------------------------------------------------ * MISC @@ -155,8 +145,8 @@ #define CFG_LONGHELP /* Provide extended help*/ #define CFG_PROMPT "==> " /* Command prompt */ #define CFG_CBSIZE 256 /* Console I/O buf size */ -#define CFG_MAXARGS 16 /* Max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ +#define CFG_MAXARGS 16 /* Max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ #define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ #define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h index 268b0343a..3a97fbcbd 100644 --- a/include/configs/PCIPPC2.h +++ b/include/configs/PCIPPC2.h @@ -53,37 +53,30 @@ #define CONFIG_PREBOOT "" #define CONFIG_BOOTDELAY 5 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_ELF | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + #define CFG_NAND_LEGACY /* @@ -230,7 +223,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h index 250b58604..130beb78e 100644 --- a/include/configs/PCIPPC6.h +++ b/include/configs/PCIPPC6.h @@ -53,39 +53,32 @@ #define CONFIG_PREBOOT "" #define CONFIG_BOOTDELAY 5 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SCSI -#define CONFIG_CMD_SNTP +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_ELF | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SCSI | \ + CFG_CMD_SNTP ) #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + */ +#include + #define CFG_NAND_LEGACY /* @@ -232,7 +225,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 5890012b4..806e95f48 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -40,42 +40,33 @@ ***********************************************************/ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IDE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FDC -#define CONFIG_CMD_SCSI -#define CONFIG_CMD_FAT -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF -#define CONFIG_CMD_USB -#define CONFIG_CMD_MII -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_DOC -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_BSP - +/*********************************************************** + * Command definitions + ***********************************************************/ +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_IDE | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_CACHE | \ + CFG_CMD_IRQ | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_REGINFO | \ + CFG_CMD_FDC | \ + CFG_CMD_SCSI | \ + CFG_CMD_FAT | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF | \ + CFG_CMD_USB | \ + CFG_CMD_MII | \ + CFG_CMD_SDRAM | \ + CFG_CMD_DOC | \ + CFG_CMD_PING | \ + CFG_CMD_SAVES | \ + CFG_CMD_BSP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CFG_NAND_LEGACY @@ -123,7 +114,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ @@ -159,7 +150,7 @@ **********************************************************/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -231,6 +222,15 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: */ @@ -252,7 +252,7 @@ #define CFG_TEMP_STACK_OCM 1 #define CFG_OCM_DATA_ADDR 0xF0000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -366,7 +366,7 @@ /************************************************************ * Debug support ************************************************************/ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index d90351add..83a7ec27b 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -160,41 +160,30 @@ #define CONFIG_IPADDR 192.168.2.21 #define CONFIG_SERVERIP 192.168.2.16 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVES - +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include /*------------------------------------------------------------------------ * COMPACT FLASH *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_IDE) +#if (CONFIG_COMMANDS & CFG_CMD_IDE) #define CONFIG_IDE_PREINIT /* Implement id_preinit */ #define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ #define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ @@ -212,12 +201,12 @@ #define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/ #define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ /*------------------------------------------------------------------------ * JFFS2 *----------------------------------------------------------------------*/ -#if defined(CONFIG_CMD_JFFS2) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) #define CFG_JFFS_CUSTOM_PART /* board defined part */ #endif diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index a3d1c56dc..dd5d83168 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -51,44 +51,33 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#if 0 /* test-only */ #define CONFIG_NET_MULTI 1 -#undef CONFIG_HAS_ETH1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY1_ADDR 1 /* PHY address */ +#else +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#endif #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -96,6 +85,10 @@ #define CONFIG_SUPPORT_VFAT #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ +#define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */ + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -115,7 +108,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -154,9 +147,8 @@ /* Only interrupt boot if space is pressed */ /* If a long serial cable is connected but */ /* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" #undef CONFIG_AUTOBOOT_DELAY_STR #define CONFIG_AUTOBOOT_STOP_STR " " @@ -168,18 +160,38 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } -#define NAND_MAX_CHIPS 1 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 +#define CFG_NAND_LEGACY -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CFG_NAND_QUIET 1 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- * PCI stuff @@ -256,6 +268,11 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -281,6 +298,9 @@ #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ /* total size of a CAT24WC16 is 2048 bytes */ +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ + /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC16) for environment */ @@ -289,8 +309,7 @@ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#define CFG_EEPROM_WREN 1 - +#if 1 /* test-only */ /* CAT24WC08/16... */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ @@ -298,9 +317,28 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ /* last 4 bits of the address */ +#else +/* CAT24WC32/64... */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ + /* 32 byte page write mode using*/ + /* last 5 bits of the address */ +#endif #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ @@ -381,16 +419,15 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CFG_GPIO0_OSRH 0x00000550 +#define CFG_GPIO0_OSRH 0x40000550 #define CFG_GPIO0_OSRL 0x00000110 #define CFG_GPIO0_ISR1H 0x00000000 #define CFG_GPIO0_ISR1L 0x15555445 #define CFG_GPIO0_TSRH 0x00000000 #define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0x77FE0014 +#define CFG_GPIO0_TCR 0xF7FE0014 #define CFG_DUART_RST (0x80000000 >> 14) -#define CFG_EEPROM_WP (0x80000000 >> 0) /* * Internal Definitions diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 259178f85..9c241e67e 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -40,7 +40,10 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -59,7 +62,6 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 #define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_PCI_MEM_BUS 0x40000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -75,6 +77,12 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #undef CONFIG_NS8382X +#define ADD_PCI_CMD CFG_CMD_PCI + +#else /* MPC5100 */ + +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + #endif /* Partitions */ @@ -83,48 +91,39 @@ /* USB */ #if 1 #define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 #endif -#if !defined(CONFIG_BOOT_ROM) +#if defined(CONFIG_BOOT_ROM) +#define ADD_DOC_CMD 0 +#else +#define ADD_DOC_CMD CFG_CMD_DOC /* DoC requires legacy NAND for now */ #define CFG_NAND_LEGACY #endif - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - -#if !defined(CONFIG_BOOT_ROM) -#define CONFIG_CMD_DOC -#endif - -#if defined(CONFIG_MPC5200) -#define CONFIG_CMD_PCI -#endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_DOC_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Autobooting @@ -132,7 +131,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -161,7 +160,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #endif /* * I2C configuration @@ -295,7 +294,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -311,11 +310,6 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Various low-level settings */ diff --git a/include/configs/PM826.h b/include/configs/PM826.h index 36e9aa56e..88fdb51ad 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -43,13 +43,13 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* enable I2C and select the hardware/software driver */ @@ -103,7 +103,8 @@ * - CONFIG_NET_MULTI must be defined * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #define CONFIG_NET_MULTI #undef CONFIG_ETHER_NONE /* define if ether on something else */ @@ -151,34 +152,33 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) #ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) +#else /* ! PCI */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +#endif /* CONFIG_PCI */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CFG_NAND_LEGACY @@ -197,7 +197,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -345,7 +345,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PM828.h b/include/configs/PM828.h index abf593cf7..37ee9771b 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -43,7 +43,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ @@ -103,7 +103,8 @@ * - CONFIG_NET_MULTI must be defined * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #define CONFIG_NET_MULTI #undef CONFIG_ETHER_NONE /* define if ether on something else */ @@ -151,34 +152,33 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DOC -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) #ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) +#else /* ! PCI */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DOC | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +#endif /* CONFIG_PCI */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Disk-On-Chip configuration @@ -196,7 +196,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -338,7 +338,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PM854.h b/include/configs/PM854.h index bd058fc15..da0118677 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -51,7 +51,6 @@ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx @@ -92,7 +91,6 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -195,16 +193,12 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration @@ -264,27 +258,23 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT #define CONFIG_MPC85XX_FEC 1 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 -#define FEC_FLAGS 0 /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" -#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 1 #define CONFIG_HAS_ETH2 1 @@ -309,36 +299,43 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - #if defined(CFG_RAMBOOT) - #undef CONFIG_CMD_ENV - #undef CONFIG_CMD_LOADS + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_MII \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif #endif +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -349,7 +346,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -368,6 +365,13 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + /* * Internal Definitions * @@ -376,7 +380,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 9355aafa6..4d834878e 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -43,7 +43,7 @@ #define CONFIG_PM856 1 /* PM856 board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_ECC /* only for ECC DDR module */ @@ -51,7 +51,6 @@ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* * sysclk for MPC85xx @@ -92,9 +91,8 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -141,7 +139,7 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -167,16 +165,16 @@ #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ @@ -192,16 +190,12 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 /* * EEPROM configuration @@ -236,7 +230,7 @@ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -244,7 +238,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -256,20 +250,19 @@ #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT #endif /* CONFIG_TSEC_ENET */ @@ -309,35 +302,41 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - #if defined(CFG_RAMBOOT) - #undef CONFIG_CMD_ENV - #undef CONFIG_CMD_LOADS + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #else + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #else + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_EEPROM \ + | CFG_CMD_DATE \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) + #endif #endif +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -348,7 +347,7 @@ #define CFG_LOAD_ADDR 0x1000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -367,6 +366,13 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + /* * Internal Definitions * @@ -375,7 +381,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -387,7 +393,6 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:40:42:01:00:00 #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:40:42:01:00:01 diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index adbe8a9fb..6e0bd7f23 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -63,37 +63,25 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_UNIVERSE -#define CONFIG_CMD_EEPROM - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_I2C | \ + CFG_CMD_PING | \ + CFG_CMD_UNIVERSE | \ + CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ @@ -112,7 +100,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -269,6 +257,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/PN62.h b/include/configs/PN62.h index da7d8b82b..a717659bb 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -42,29 +42,15 @@ #define CONFIG_CONS_INDEX 1 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_BSP - -#undef CONFIG_CMD_AUTOSCRIPT -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_ENV -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS +#define REMOVE_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_LOADS | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMLS ) +#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~REMOVE_COMMANDS) |\ + CFG_CMD_PCI |\ + CFG_CMD_BSP) #define CONFIG_BAUDRATE 19200 /* console baudrate */ @@ -73,7 +59,7 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_SERVERIP 10.0.0.201 -#define CONFIG_IPADDR 10.0.0.200 +#define CONFIG_IPADDR 10.0.0.200 #define CONFIG_ROOTPATH /opt/eldk/ppc_82xx #define CONFIG_NETMASK 255.255.255.0 #undef CONFIG_BOOTARGS @@ -81,7 +67,7 @@ /* Boot Linux with NFS root filesystem */ #define CONFIG_BOOTCOMMAND \ "setenv verify y;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ + "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ "loadp 100000; bootm" @@ -90,12 +76,16 @@ /* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ #define CONFIG_BOOTCOMMAND \ "setenv verify n;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ + "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ "root=/dev/ram rw " \ "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ "loadp 200000; bootm" #endif +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + /* * Miscellaneous configurable options */ @@ -128,7 +118,7 @@ /* * Networking stuff */ -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ #define CONFIG_PCNET_79C973 @@ -153,9 +143,9 @@ /*#define CFG_GBL_DATA_SIZE 256*/ #define CFG_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_NO_FLASH 1 /* There is no FLASH memory */ @@ -297,7 +287,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index cf9832434..16e2cc6d6 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -113,38 +113,26 @@ #endif #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */ @@ -174,7 +162,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -429,8 +417,6 @@ #define CFG_ENV_ADDR_REDUND 0xFFFFA000 #define CFG_ENV_SIZE_REDUND 0x2000 -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - #endif /* ENVIRONMENT_IN_EEPROM */ @@ -454,6 +440,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * @@ -496,7 +492,7 @@ #define CONFIG_VGA_AS_SINGLE_DEVICE /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ #define CFG_ISA_IO 0xE8000000 -/* see also drivers/video/videomodes.c */ +/* see also drivers/videomodes.c */ #define CFG_DEFAULT_VIDEO_MODE 0x303 #endif diff --git a/include/configs/QS823.h b/include/configs/QS823.h index cef9f42df..235bc480c 100644 --- a/include/configs/QS823.h +++ b/include/configs/QS823.h @@ -38,6 +38,7 @@ #undef CFG_DEVICE_NULLDEV /* null device */ #undef CONFIG_SILENT_CONSOLE /* silent console */ #undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ +#undef DEBUG /* debug output code */ #undef DEBUG_FLASH /* debug flash code */ #undef FLASH_DEBUG /* debug fash code */ #undef DEBUG_ENV /* debug environment code */ @@ -188,37 +189,27 @@ #undef CONFIG_STATUS_LED /* Status LED disabled */ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_DATE | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_RUN) -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_RUN - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /*----------------------------------------------------------------------- * Environment variable storage is in FLASH, one sector before U-boot @@ -237,7 +228,7 @@ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -312,7 +303,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -492,12 +483,12 @@ /* For boards with 16M of SDRAM */ #define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ +#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* For boards with 32M of SDRAM */ #define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ +#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) diff --git a/include/configs/QS850.h b/include/configs/QS850.h index ba5827a22..967582b45 100644 --- a/include/configs/QS850.h +++ b/include/configs/QS850.h @@ -38,6 +38,7 @@ #undef CFG_DEVICE_NULLDEV /* null device */ #undef CONFIG_SILENT_CONSOLE /* silent console */ #undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ +#undef DEBUG /* debug output code */ #undef DEBUG_FLASH /* debug flash code */ #undef FLASH_DEBUG /* debug fash code */ #undef DEBUG_ENV /* debug environment code */ @@ -188,37 +189,27 @@ #undef CONFIG_STATUS_LED /* Status LED disabled */ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_DATE | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MEMORY | \ + CFG_CMD_NET | \ + CFG_CMD_RUN) -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_RUN - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /*----------------------------------------------------------------------- * Environment variable storage is in FLASH, one sector before U-boot @@ -237,7 +228,7 @@ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -312,7 +303,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -492,12 +483,12 @@ /* For boards with 16M of SDRAM */ #define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ +#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* For boards with 32M of SDRAM */ #define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ +#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h index c98090185..32faa6160 100644 --- a/include/configs/QS860T.h +++ b/include/configs/QS860T.h @@ -38,6 +38,7 @@ #undef CFG_DEVICE_NULLDEV /* null device */ #undef CONFIG_SILENT_CONSOLE /* silent console */ #undef CFG_CONSOLE_INFO_QUIET /* silent console ? */ +#undef DEBUG /* debug output code */ #undef DEBUG_FLASH /* debug flash code */ #undef FLASH_DEBUG /* debug fash code */ #undef DEBUG_ENV /* debug environment code */ @@ -72,7 +73,7 @@ #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ #define CONFIG_PREBOOT "echo;" \ - "echo 'Type \\\"run flash_nfs\\\" to mount root filesystem over NFS';" \ + "echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \ "echo" #undef CONFIG_BOOTARGS @@ -91,33 +92,23 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ASKENV | \ + CFG_CMD_NET | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_NET -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* TODO */ @@ -145,7 +136,7 @@ CONFIG_SPI #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -219,7 +210,7 @@ CONFIG_SPI * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index a653cca96..82228c012 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -58,13 +58,13 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #undef CONFIG_SCC1_ENET @@ -79,14 +79,7 @@ #define CONFIG_CAN_DRIVER /* CAN Driver support enabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -118,23 +111,20 @@ #define CFG_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */ #define CFG_I2C_TEM_ADDR 0x49 /* Temperature Sensors */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NFS | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BMP -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_SNTP - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -144,7 +134,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -233,13 +223,12 @@ #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */ #define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */ -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index 9222d2155..242c837a3 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -61,13 +61,13 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_8xx_GCLK_FREQ 48000000L -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -79,15 +79,7 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #undef CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -102,40 +94,42 @@ #define CFG_EEPROM_WRITE_BITS 4 #define CFG_EEPROM_WRITE_DELAY_MS 10 -/* - * Command line configuration. - */ -#include +#define CONFIG_COMMANDS ( CFG_CMD_ALL & \ + ~CFG_CMD_BSP & \ + ~CFG_CMD_DATE & \ + ~CFG_CMD_DISPLAY& \ + ~CFG_CMD_DTT & \ + ~CFG_CMD_EXT2 & \ + ~CFG_CMD_FDC & \ + ~CFG_CMD_FDOS & \ + ~CFG_CMD_HWFLOW & \ + ~CFG_CMD_IDE & \ + ~CFG_CMD_IRQ & \ + ~CFG_CMD_JFFS2 & \ + ~CFG_CMD_MII & \ + ~CFG_CMD_MMC & \ + ~CFG_CMD_NAND & \ + ~CFG_CMD_PCI & \ + ~CFG_CMD_PCMCIA & \ + ~CFG_CMD_REISER & \ + ~CFG_CMD_SCSI & \ + ~CFG_CMD_SETGETDCR & \ + ~CFG_CMD_SNTP & \ + ~CFG_CMD_SPI & \ + ~CFG_CMD_UNIVERSE & \ + ~CFG_CMD_USB & \ + ~CFG_CMD_VFD & \ + ~CFG_CMD_XIMG ) -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_BMP -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DOC -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM - -#undef CONFIG_CMD_SETGETDCR -#undef CONFIG_CMD_XIMG +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -211,7 +205,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h index 706e2aadc..591382cd2 100644 --- a/include/configs/RPXClassic.h +++ b/include/configs/RPXClassic.h @@ -78,9 +78,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -88,26 +88,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ELF +#define CONFIG_COMMANDS ((CFG_CMD_ALL & ~CFG_CMD_NONSTD) | CFG_CMD_ELF) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -115,7 +104,7 @@ #define CFG_RESET_ADDRESS 0x80000000 #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -193,7 +182,7 @@ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFF000000 -#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE) +#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ @@ -233,7 +222,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -467,7 +456,7 @@ #define BCSR3 0xFA400003 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index 671094b69..48ada0ed9 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -51,9 +51,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -62,28 +62,17 @@ #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -156,7 +145,7 @@ #define CFG_DIRECT_FLASH_TFTP #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CONFIG_ENV_OVERWRITE @@ -165,7 +154,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -361,7 +350,7 @@ #define BCSR3 0xFA400003 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index faae407da..31025473f 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -68,8 +68,7 @@ #ifdef DEPLOYMENT #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "autoboot in %d seconds (stop with 'st')...\n", bootdelay +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n" #define CONFIG_AUTOBOOT_STOP_STR "st" #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_RESET_TO_RETRY 1 @@ -116,36 +115,29 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you don't want the advanced function */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_DHCP - #ifdef CONFIG_SPLASH_SCREEN -#define CONFIG_CMD_BMP -#endif - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BMP | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_REGINFO | \ + CFG_CMD_DHCP ) +#else +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_REGINFO | \ + CFG_CMD_DHCP ) +#endif /* CONFIG_SPLASH_SCREEN */ /* test-only */ #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ @@ -155,13 +147,16 @@ #endif /* 1 */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -205,7 +200,7 @@ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFF000000 -#if defined(DEBUG) || defined(CONFIG_CMD_IDE) +#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ @@ -244,7 +239,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index dfadd2a11..45907aa0e 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -91,7 +91,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ @@ -149,28 +150,13 @@ /* Monitor Command Prompt */ #define CFG_PROMPT "=> " - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_REGINFO - -#undef CONFIG_CMD_KGDB - +/* What U-Boot subsytems do you want enabled? */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ASKENV | \ + CFG_CMD_I2C | \ + CFG_CMD_REGINFO & \ + ~CFG_CMD_KGDB ) /* Where do the internal registers live? */ #define CFG_IMMR 0xF0000000 @@ -190,10 +176,13 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -321,7 +310,7 @@ */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index 6a7180193..3885bcdb1 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -92,15 +92,7 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -119,7 +111,7 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ # define CFG_I2C_SPEED 50000 /* 50 kHz is supposed to work */ # define CFG_I2C_SLAVE 0xFE @@ -143,26 +135,23 @@ #endif /* CONFIG_SOFT_I2C */ -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_DATE - -#undef CONFIG_CMD_PCMCIA -#undef CONFIG_CMD_IDE +#define CONFIG_COMMANDS ( ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_DATE ) & \ + ~( CFG_CMD_PCMCIA | \ + CFG_CMD_IDE ) ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -235,13 +224,11 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index 01ebc8f6e..dbc57e8b2 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -37,6 +37,8 @@ #define CONFIG_RATTLER /* Analogue&Micro Rattler board */ +#undef DEBUG + /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ #define CONFIG_ENV_OVERWRITE @@ -60,8 +62,8 @@ * SCC, 1-3 for FCC) * * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. + * must be defined elsewhere (as for the console), or CFG_CMD_NET must + * be removed from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ @@ -123,33 +125,22 @@ #define CONFIG_BAUDRATE 38400 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_JFFS2 \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -167,7 +158,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -193,7 +184,7 @@ #define CFG_DIRECT_FLASH_TFTP -#if defined(CONFIG_CMD_JFFS2) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) #define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS #define CFG_JFFS2_SORT_FRAGMENTS @@ -214,7 +205,7 @@ #define MTDIDS_DEFAULT "nor0=rattler-0" #define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)" */ -#endif /* CONFIG_CMD_JFFS2 */ +#endif /* CFG_CMD_JFFS2 */ #define CFG_MONITOR_BASE TEXT_BASE #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) @@ -250,13 +241,13 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ @@ -265,7 +256,7 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 8a53fdd0c..0451b2081 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -48,8 +48,7 @@ #define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ -#define CONFIG_MPC8540 1 +#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ @@ -57,7 +56,6 @@ #undef CONFIG_PCI /* pci ethernet support */ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE @@ -100,7 +98,6 @@ #else #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ #endif -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ @@ -217,16 +214,12 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 #define CFG_PCI_MEM_BASE 0xC0000000 #define CFG_PCI_MEM_PHYS 0xC0000000 @@ -341,37 +334,28 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_CMD_MII -#endif - -#if defined(CFG_RAMBOOT) - #undef CONFIG_CMD_ENV - #undef CONFIG_CMD_LOADS +#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV | \ + CFG_CMD_LOADS )) + #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) + #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) + #endif #endif +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -380,7 +364,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "SBC8540=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -398,6 +382,13 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Internal Definitions * @@ -406,7 +397,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/SBC8560.h b/include/configs/SBC8560.h new file mode 100644 index 000000000..8b46a17ed --- /dev/null +++ b/include/configs/SBC8560.h @@ -0,0 +1,410 @@ +/* + * (C) Copyright 2002,2003 Motorola,Inc. + * Xianghua Xiao + * + * (C) Copyright 2004 Wind River Systems Inc . + * Added support for Wind River SBC8560 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* mpc8560ads board configuration file */ +/* please refer to doc/README.mpc85xx for more info */ +/* make sure you change the MAC address and other network params first, + * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if XXX +#define DEBUG /* General debug */ +#define ET_DEBUG +#endif +#define TSEC_DEBUG + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ +#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ + + +#define CONFIG_CPM2 1 /* has CPM2 */ +#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */ + +#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_PCI /* pci ethernet support */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ + + +#define CONFIG_ENV_OVERWRITE + +/* Using Localbus SDRAM to emulate flash before we can program the flash, + * normally you need a flash-boot image(u-boot.bin), if so undef this. + */ +#undef CONFIG_RAM_AS_FLASH + +#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */ + #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */ +#else + #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */ +#endif + +/* below can be toggled for performance analysis. otherwise use default */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#undef CONFIG_BTB /* toggle branch predition */ +#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ + defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ + defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) +#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." +#endif + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ + +#if XXX + #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ +#else + #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ +#endif +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ + +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */ +#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */ + +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ + +#if defined(CONFIG_MPC85xx_REV1) + #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +#if defined(CONFIG_RAM_AS_FLASH) + #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ + #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */ + #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */ + #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */ +#else /* Boot from real Flash */ + #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ + #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ + #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */ + #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */ +#endif +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +/* local bus definitions */ +#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ +#define CFG_OR1_PRELIM 0xfc000ff7 + +#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */ +#define CFG_OR2_PRELIM 0x00000000 + +#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */ +#define CFG_OR3_PRELIM 0xfc000cc1 + +#if defined(CONFIG_RAM_AS_FLASH) + #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */ +#else + #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */ +#endif +#define CFG_OR4_PRELIM 0xfc000cc1 + +#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */ +#if 1 + #define CFG_OR5_PRELIM 0xff000ff7 +#else + #define CFG_OR5_PRELIM 0xff0000f0 +#endif + +#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */ +#define CFG_OR6_PRELIM 0xfc000ff7 +#define CFG_LBC_LCRR 0x00030002 /* local bus freq */ +#define CFG_LBC_LBCR 0x00000000 +#define CFG_LBC_LSRT 0x20000000 +#define CFG_LBC_MRTPR 0x20000000 +#define CFG_LBC_LSDMR_1 0x2861b723 +#define CFG_LBC_LSDMR_2 0x0861b723 +#define CFG_LBC_LSDMR_3 0x0861b723 +#define CFG_LBC_LSDMR_4 0x1861b723 +#define CFG_LBC_LSDMR_5 0x4061b723 + +/* just hijack the MOT BCSR def for SBC8560 misc devices */ +#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000) +/* the size of CS5 needs to be >= 16M for TLB and LAW setups */ + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ + +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */ +#define CONFIG_BAUDRATE 9600 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000) +#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000) + +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +#define CFG_PCI_MEM_BASE 0xC0000000 +#define CFG_PCI_MEM_PHYS 0xC0000000 +#define CFG_PCI_MEM_SIZE 0x10000000 + +#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ + +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 /* MII PHY management */ +# define CONFIG_MPC85xx_TSEC1 +# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0" +# define TSEC1_PHY_ADDR 25 +# define TSEC1_PHYIDX 0 +/* Options are: TSEC0 */ +# define CONFIG_ETHPRIME "TSEC0" + + +#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ + + #undef CONFIG_ETHER_NONE /* define if ether on something else */ + #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */ + #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ + + #if (CONFIG_ETHER_INDEX == 2) + /* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - Select bus for bd/buffers + * - Full duplex + */ + #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CFG_CPMFCR_RAMTYPE 0 + #define CFG_FCC_PSMR (FCC_PSMR_FDE) + + #elif (CONFIG_ETHER_INDEX == 3) + /* need more definitions here for FE3 */ + #endif /* CONFIG_ETHER_INDEX */ + + #define CONFIG_MII /* MII PHY management */ + #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ + /* + * GPIO pins used for bit-banged MII communications + */ + #define MDIO_PORT 2 /* Port C */ + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) + #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) + #define MDIO_READ ((iop->pdat & 0x00400000) != 0) + + #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ + else iop->pdat &= ~0x00400000 + + #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ + else iop->pdat &= ~0x00200000 + + #define MIIDELAY udelay(1) + +#endif + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#if 0 +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION /* use hardware protection */ +#endif +#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if 0 +/* XXX This doesn't work and I don't want to fix it */ +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) + #define CFG_RAMBOOT +#else + #undef CFG_RAMBOOT +#endif +#endif + +/* Environment */ +#if !defined(CFG_RAMBOOT) + #if defined(CONFIG_RAM_AS_FLASH) + #define CFG_ENV_IS_NOWHERE + #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) + #define CFG_ENV_SIZE 0x2000 + #else + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) + #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */ + #endif +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600" +/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/ +#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" +#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV | \ + CFG_CMD_LOADS )) + #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) & \ + ~(CFG_CMD_ENV)) + #endif +#else + #if defined(CONFIG_PCI) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ + CFG_CMD_PING | CFG_CMD_I2C) + #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ + CFG_CMD_PING | CFG_CMD_I2C) + #endif +#endif + +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ + #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/*Note: change below for your network setting!!! */ +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a +# define CONFIG_HAS_ETH1 +# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b +# define CONFIG_HAS_ETH2 +# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c +#endif + +#define CONFIG_SERVERIP YourServerIP +#define CONFIG_IPADDR YourTargetIP +#define CONFIG_GATEWAYIP YourGatewayIP +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_HOSTNAME SBC8560 +#define CONFIG_ROOTPATH YourRootPath +#define CONFIG_BOOTFILE YourImageName + +#endif /* __CONFIG_H */ diff --git a/include/configs/SCM.h b/include/configs/SCM.h index febfc3926..e263db65a 100644 --- a/include/configs/SCM.h +++ b/include/configs/SCM.h @@ -63,13 +63,13 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* enable I2C and select the hardware/software driver */ @@ -133,7 +133,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. * * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the * X.29 connector, and FCC2 is hardwired to the X.1 connector) @@ -165,7 +166,7 @@ * - Enable Full Duplex in FSMR */ # define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) +# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) # define CFG_CPMFCR_RAMTYPE 0 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) @@ -190,33 +191,23 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_BSP) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_BSP - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -362,7 +353,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h index 31853c8de..61896d0d7 100644 --- a/include/configs/SL8245.h +++ b/include/configs/SL8245.h @@ -53,22 +53,11 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI +#include /* @@ -90,10 +79,10 @@ * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ -#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM +#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } #define CFG_RESET_ADDRESS 0xFFF00100 @@ -266,7 +255,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/SM850.h b/include/configs/SM850.h index 465db4735..497762912 100644 --- a/include/configs/SM850.h +++ b/include/configs/SM850.h @@ -54,9 +54,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -68,34 +68,23 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -178,7 +167,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index 395c7a1e7..ae4dcc2cc 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -59,29 +59,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IDE - -#undef CONFIG_CMD_FLASH - - +#define CONFIG_COMMANDS \ +((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /*----------------------------------------------------------------------*/ #define CONFIG_ETHADDR 00:D0:93:00:01:CB @@ -96,7 +82,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -174,7 +160,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/SX1.h b/include/configs/SX1.h index 50ad7dd59..6ed98b8fb 100644 --- a/include/configs/SX1.h +++ b/include/configs/SX1.h @@ -93,26 +93,12 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \ + CFG_CMD_I2C ) & \ + ~CFG_CMD_NET) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_I2C - -#undef CONFIG_CMD_NET - - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #include #define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw" @@ -181,7 +167,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index aefc7eecb..a8454d99f 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -146,26 +146,14 @@ #define CFG_DISCOVER_PHY +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DATE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CFG_JFFS2_SORT_FRAGMENTS @@ -204,7 +192,7 @@ #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 @@ -238,7 +226,7 @@ */ #define CFG_LONGHELP /* undef to save a little memory */ #define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -250,7 +238,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -321,7 +309,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -465,7 +453,7 @@ #if 1 #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" #define CONFIG_AUTOBOOT_DELAY_STR "delayabit" #define CONFIG_AUTOBOOT_STOP_STR " " /* easy to stop for now */ #endif diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h index 5bbe3c591..f4339ecd9 100644 --- a/include/configs/Sandpoint8240.h +++ b/include/configs/Sandpoint8240.h @@ -80,30 +80,18 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_SDRAM | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_DRAM_SPEED 100 /* MHz */ @@ -396,7 +384,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h index a08451eb3..d42bd6923 100644 --- a/include/configs/Sandpoint8245.h +++ b/include/configs/Sandpoint8245.h @@ -51,28 +51,17 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* @@ -374,7 +363,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index dccdf0ca9..119bc2442 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -43,10 +43,6 @@ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ -#define CONFIG_MCFTMR - -#define CONFIG_MCFUART -#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -54,34 +50,20 @@ #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C ) & \ + ~(CFG_CMD_NET)) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C - -#undef CONFIG_CMD_NET - - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 #define CFG_PROMPT "=> " #define CFG_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index d21783b83..8a6e5a61b 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -42,7 +42,10 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -69,6 +72,12 @@ #define CFG_CONSOLE_IS_IN_ENV #endif +#ifdef CONFIG_VIDEO +#define ADD_BMP_CMD CFG_CMD_BMP +#else +#define ADD_BMP_CMD 0 +#endif + /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -76,6 +85,7 @@ /* USB */ #define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE /* POST support */ @@ -84,51 +94,41 @@ CFG_POST_I2C) #ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 +#else +#define CFG_CMD_POST_DIAG 0 #endif +/* IDE */ +#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_BSP -#define CONFIG_CMD_USB - -#ifdef CONFIG_VIDEO -#define CONFIG_CMD_BMP -#endif - -#ifdef CONFIG_POST -#define CONFIG__CMD_DIAG -#endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_BMP_CMD | \ + ADD_IDE_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP | \ + CFG_CMD_BSP) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -142,7 +142,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -200,17 +200,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ -#if defined(CFG_IPBCLK_EQUALS_XLBCLK) +#if defined(CFG_IPBSPEED_133) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ #endif /* @@ -337,7 +337,7 @@ #else #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ #endif /* CONFIG_TQM5200_B */ -#define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* @@ -394,8 +394,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -404,11 +403,6 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* Enable an alternate, more extensive memory test */ #define CFG_ALT_MEMTEST @@ -420,7 +414,8 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ /* - * Enable loopw command. + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) */ #define CONFIG_LOOPW @@ -437,7 +432,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 +#ifdef CFG_PCISPEED_66 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 4c447356a..f41dbd0cc 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -50,7 +50,10 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -69,7 +72,6 @@ # define CONFIG_PCI 1 # define CONFIG_PCI_PNP 1 # define CONFIG_PCI_SCAN_SHOW 1 -# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 # define CONFIG_PCI_MEM_BUS 0x40000000 # define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -79,6 +81,12 @@ # define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS # define CONFIG_PCI_IO_SIZE 0x01000000 +# define ADD_PCI_CMD CFG_CMD_PCI + +#else /* no Evaluation board */ + +# define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + #endif /* USB */ @@ -91,49 +99,49 @@ # else # define CONFIG_USB_CONFIG 0x00001000 # endif +# define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT # define CONFIG_DOS_PARTITION # define CONFIG_USB_STORAGE +#else + +# define ADD_USB_CMD 0 + #endif /* IDE */ #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) + +# define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT # define CONFIG_DOS_PARTITION + +#else + +# define ADD_IDE_CMD 0 + #endif - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_REGINFO - -#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_USB -#define CONFIG_CMD_PCI -#endif +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + ADD_IDE_CMD | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_BEDBUG \ + ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * MUST be low boot - HIGHBOOT is not supported anymore @@ -151,7 +159,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -178,7 +186,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ /* * I2C configuration @@ -328,7 +336,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -344,12 +352,6 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - #ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */ #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */ #define RTC(reg) (0xf0010000+reg) diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h index 151c407c8..2344b9681 100644 --- a/include/configs/TOP860.h +++ b/include/configs/TOP860.h @@ -107,28 +107,30 @@ */ #define CFG_MATCH_PARTIAL_CMD - /* - * Command line configuration. + * List of available monitor commands. Use the system default list + * plus add some of the "non-standard" commands back in. + * See ./cmd_confdefs.h */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_BEDBUG - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ELF | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_BEDBUG \ + ) #define CONFIG_AUTOSCRIPT 1 #define CFG_LOADS_BAUD_CHANGE 1 #undef CONFIG_LOADS_ECHO /* NO echo on for serial download */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ @@ -139,7 +141,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -201,11 +203,10 @@ * defines we need to get FEC running */ #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ -#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ -#define FEC_ENET 1 /* eth.c needs it that way... */ +#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ +#define FEC_ENET 1 /* eth.c needs it that way... */ #define CFG_DISCOVER_PHY 1 -#define CONFIG_MII 1 -#define CONFIG_MII_INIT 1 +#define CONFIG_MII 1 #define CONFIG_PHY_ADDR 31 /*----------------------------------------------------------------------- @@ -238,7 +239,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -287,7 +288,7 @@ *----------------------------------------------------------------------- * set up SYPCR: * 16 SWTC 0xffff Software watchdog timer count - * 8 BMT 0xff Bus monitor timing + * 8 BMT 0xff Bus monitor timing * 1 BME 1 Bus monitor enable * 3 0 000 * 1 SWF 1 Software watchdog freeze @@ -297,7 +298,7 @@ */ #if defined (CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) #endif @@ -410,11 +411,10 @@ /* * BOOTP options */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#undef CONFIG_BOOTP_MASK +#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE \ + ) /* diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index bfb478a86..be83b6767 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -37,17 +37,19 @@ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -/* On a Cameron or on a FO300 board or ... */ -#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300) +#ifndef CONFIG_CAM5200 /* On a Cameron board or ... */ #define CONFIG_STK52XX 1 /* ... on a STK52XX board */ #endif #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -56,20 +58,6 @@ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -#ifdef CONFIG_FO300 -#define CFG_DEVICE_NULLDEV 1 /* enable null device */ -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */ -#define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */ -#if 0 -#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ - /* switch is closed */ -#endif - -#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ - /* switch is open */ -#endif /* CONFIG_FO300 */ - #ifdef CONFIG_STK52XX #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ @@ -102,6 +90,12 @@ #define CONFIG_NS8382X 1 #endif /* CONFIG_STK52XX */ +#ifdef CONFIG_PCI +#define ADD_PCI_CMD CFG_CMD_PCI +#else +#define ADD_PCI_CMD 0 +#endif + /* * Video console */ @@ -111,19 +105,18 @@ #define CONFIG_VIDEO_SM501_32BPP #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO - -#ifndef CONFIG_FO300 -#define CONFIG_CONSOLE_EXTRA_INFO -#else -#define CONFIG_VIDEO_BMP_LOGO -#endif - #define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_CONSOLE_EXTRA_INFO #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN #define CFG_CONSOLE_IS_IN_ENV -#endif /* #ifndef CONFIG_TQM5200S */ +#endif +#ifdef CONFIG_VIDEO +#define ADD_BMP_CMD CFG_CMD_BMP +#else +#define ADD_BMP_CMD 0 +#endif /* Partitions */ #define CONFIG_MAC_PARTITION @@ -131,19 +124,12 @@ #define CONFIG_ISO_PARTITION /* USB */ -#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) -#define CONFIG_USB_OHCI_NEW -#define CFG_OHCI_BE_CONTROLLER +#ifdef CONFIG_STK52XX +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_USB - -#undef CFG_USB_OHCI_BOARD_INIT -#define CFG_USB_OHCI_CPU_INIT -#define CFG_USB_OHCI_REGS_BASE MPC5XXX_USB -#define CFG_USB_OHCI_SLOT_NAME "mpc5200" -#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 - +#else +#define ADD_USB_CMD 0 #endif #ifndef CONFIG_CAM5200 @@ -154,62 +140,44 @@ #endif #ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 +#else +#define CFG_CMD_POST_DIAG 0 #endif +/* IDE */ +#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) +#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) +#else +#define ADD_IDE_CMD 0 +#endif /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_BSP - -#ifdef CONFIG_VIDEO - #define CONFIG_CMD_BMP -#endif - -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 -#endif - -#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) || defined(CONFIG_FO300) - #define CONFIG_CMD_IDE - #define CONFIG_CMD_FAT - #define CONFIG_CMD_EXT2 -#endif - -#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) - #define CONFIG_CFG_USB - #define CONFIG_CFG_FAT -#endif - -#ifdef CONFIG_POST - #define CONFIG_CMD_DIAG -#endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_BMP_CMD | \ + ADD_IDE_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP | \ + CFG_CMD_BSP) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -228,51 +196,40 @@ #undef CONFIG_BOOTARGS -#if defined(CONFIG_TQM5200_B) && !defined(CFG_LOWBOOT) -# define ENV_UPDT \ - "update=protect off FFF00000 +${filesize};" \ - "erase FFF00000 +${filesize};" \ - "cp.b 200000 FFF00000 ${filesize};" \ - "protect on FFF00000 +${filesize}\0" -#else /* default lowboot configuration */ +#ifdef CONFIG_STK52XX +# if defined(CONFIG_TQM5200_B) +# if defined(CFG_LOWBOOT) # define ENV_UPDT \ - "update=protect off FC000000 +${filesize};" \ - "erase FC000000 +${filesize};" \ + "update=protect off FC000000 FC07FFFF;" \ + "erase FC000000 FC07FFFF;" \ "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 +${filesize}\0" -#endif - -#if defined(CONFIG_TQM5200) -#define CUSTOM_ENV_SETTINGS \ - "hostname=tqm5200\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" -#elif defined(CONFIG_CAM5200) -#define CUSTOM_ENV_SETTINGS \ - "bootfile=cam5200/uImage\0" \ - "u-boot=cam5200/u-boot.bin\0" \ - "setup=tftp 200000 cam5200/setup.img; autoscr 200000\0" -#endif - -#if defined(CONFIG_TQM5200_B) -#define ENV_FLASH_LAYOUT \ - "fdt_addr=FC100000\0" \ - "kernel_addr=FC140000\0" \ - "ramdisk_addr=FC600000\0" -#else /* !CONFIG_TQM5200_B */ -#define ENV_FLASH_LAYOUT \ - "fdt_addr=FC0A0000\0" \ - "kernel_addr=FC0C0000\0" \ - "ramdisk_addr=FC300000\0" -#endif + "protect on FC000000 FC07FFFF\0" +# else /* highboot */ +# define ENV_UPDT \ + "update=protect off FFF00000 FFF7FFFF;" \ + "erase FFF00000 FFF7FFFF;" \ + "cp.b 200000 FFF00000 ${filesize};" \ + "protect on FFF00000 FFF7FFFF\0" +# endif /* CFG_LOWBOOT */ +# else /* !CONFIG_TQM5200_B */ +# define ENV_UPDT \ + "update=protect off FC000000 FC05FFFF;" \ + "erase FC000000 FC05FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC05FFFF\0" +# endif /* CONFIG_TQM5200_B */ +#elif defined (CONFIG_CAM5200) +# define ENV_UPDT \ + "update=protect off FC000000 FC03FFFF;" \ + "erase FC000000 FC03FFFF;" \ + "cp.b 200000 FC000000 ${filesize};" \ + "protect on FC000000 FC03FFFF\0" +#else +# error "Unknown Carrier Board" +#endif /* CONFIG_STK52XX */ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "console=ttyPSC0\0" \ - ENV_FLASH_LAYOUT \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=600000\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -281,22 +238,15 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "flash_self_old=sete console ttyS0; run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "console=ttyS0,${baudrate}\0" \ "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ - "sete console ttyS0; run nfsargs addip addcons;bootm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcons; " \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - CUSTOM_ENV_SETTINGS \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ + "bootm\0" \ + "bootfile=/tftpboot/tqm5200/uImage\0" \ + "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ "load=tftp 200000 ${u-boot}\0" \ ENV_UPDT \ "" @@ -306,17 +256,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ -#if defined(CFG_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200) +#if defined(CFG_IPBSPEED_133) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of - * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ #endif /* @@ -372,29 +322,13 @@ */ #define CFG_FLASH_BASE 0xFC000000 -#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) -#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_WORD_SIZE unsigned int /* main flash device with */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CFG_FLASH_ADDR0 0x555 -#define CFG_FLASH_ADDR1 0x2AA -#define CFG_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ -#define CFG_MAX_FLASH_SECT 128 -#else /* use CFI flash driver */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#endif - #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ #define CFG_FLASH_USE_BUFFER_WRITE 1 #if defined (CONFIG_CAM5200) @@ -405,6 +339,9 @@ # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) #endif +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ + /* Dynamic MTD partition support */ #define CONFIG_JFFS2_CMDLINE #define MTDIDS_DEFAULT "nor0=TQM5200-0" @@ -413,9 +350,8 @@ # if defined(CONFIG_TQM5200_B) # if defined(CFG_LOWBOOT) # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \ - "256k(dtb)," \ - "2304k(kernel)," \ - "2560k(small-fs)," \ + "1536k(kernel)," \ + "3584k(small-fs)," \ "2m(initrd)," \ "8m(misc)," \ "16m(big-fs)" @@ -429,23 +365,17 @@ # endif /* CFG_LOWBOOT */ # else /* !CONFIG_TQM5200_B */ # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ - "128k(dtb)," \ - "2304k(kernel)," \ + "1408k(kernel)," \ "2m(initrd)," \ "4m(small-fs)," \ "8m(misc)," \ - "15m(big-fs)" + "16m(big-fs)" # endif /* CONFIG_TQM5200_B */ #elif defined (CONFIG_CAM5200) # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ "1792k(kernel)," \ - "5632k(rootfs)," \ - "24m(home)" -#elif defined (CONFIG_FO300) -# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ - "1408k(kernel)," \ + "3584k(small-fs)," \ "2m(initrd)," \ - "4m(small-fs)," \ "8m(misc)," \ "16m(big-fs)" #else @@ -457,7 +387,7 @@ */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ -#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) +#if defined(CONFIG_TQM5200_B) #define CFG_ENV_SECT_SIZE 0x40000 #else #define CFG_ENV_SECT_SIZE 0x20000 @@ -515,43 +445,28 @@ /* * GPIO configuration * - * use CS1: Bit 0 (mask: 0x80000000): - * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1). + * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): + * Bit 0 (mask: 0x80000000): 1 * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * SPI on PSC3 according to PSC3 setting. Use for CAM5200. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards and FO300 boards. Do not use - * with REV100 modules (because, there I2C1 is used as I2C bus). - * use ATA: Bits 6-7 (mask 0x03000000): - * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects. - * Use for CAM5200 board. - * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards. - * use PSC6: Bits 9-11 (mask 0x00700000): - * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as - * UART, CODEC or IrDA. - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to - * enable extended POST tests. - * Use for MINI-FAP and TQM5200_IB boards. - * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. - * Extended POST test is not available. - * Use for STK52xx, FO300 and CAM5200 boards. - * use PCI_DIS: Bit 16 (mask 0x00008000): - * 1 -> disable PCI controller (on CAM5200 board). - * use USB: Bits 18-19 (mask 0x00003000): - * 10 -> two UARTs (on FO300 and CAM5200). - * use PSC3: Bits 20-23 (mask: 0x00000f00): - * 0000 -> All PSC3 pins are GPIOs. - * 1100 -> UART/SPI (on FO300 board). - * 0100 -> UART (on CAM5200 board). - * use PSC2: Bits 25:27 (mask: 0x00000030): - * 000 -> All PSC2 pins are GPIOs. - * 100 -> UART (on CAM5200 board). - * 001 -> CAN1/2 on PSC2 pins. - * Use for REV100 STK52xx boards - * 01x -> Use AC97 (on FO300 board). - * use PSC1: Bits 29-31 (mask: 0x00000007): - * 100 -> UART (on all boards). + * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. + * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. + * Use for REV200 STK52XX boards. Do not use with REV100 modules + * (because, there I2C1 is used as I2C bus) + * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 + * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) + * 000 -> All PSC2 pins are GIOPs + * 001 -> CAN1/2 on PSC2 pins + * Use for REV100 STK52xx boards + * use PSC6: + * on STK52xx: + * use as UART. Pins PSC6_0 to PSC6_3 are used. + * Bits 9:11 (mask: 0x00700000): + * 101 -> PSC6 : Extended POST test is not available + * on MINI-FAP and TQM5200_IB: + * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): + * 000 -> PSC6 could not be used as UART, CODEC or IrDA + * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST + * tests. */ #if defined (CONFIG_MINIFAP) # define CFG_GPS_PORT_CONFIG 0x91000004 @@ -562,13 +477,9 @@ # if defined (CONFIG_TQM5200_REV100) # error TQM5200 REV100 not supported on STK52XX REV200 or above # else/* TQM5200 REV200 and above */ -# define CFG_GPS_PORT_CONFIG 0x91500404 +# define CFG_GPS_PORT_CONFIG 0x91500004 # endif # endif -#elif defined (CONFIG_FO300) -# define CFG_GPS_PORT_CONFIG 0x91502c24 -#elif defined (CONFIG_CAM5200) -# define CFG_GPS_PORT_CONFIG 0x8050A444 #else /* TMQ5200 Inbetriebnahme-Board */ # define CFG_GPS_PORT_CONFIG 0x81000004 #endif @@ -591,16 +502,10 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -620,7 +525,8 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ /* - * Enable loopw command. + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) */ #define CONFIG_LOOPW @@ -637,7 +543,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 +#ifdef CFG_PCISPEED_66 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ @@ -668,16 +574,6 @@ #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ -#if defined(CONFIG_CAM5200) -#define CFG_CS4_START 0xB0000000 -#define CFG_CS4_SIZE 0x00010000 -#define CFG_CS4_CFG 0x01019C10 - -#define CFG_CS5_START 0xD0000000 -#define CFG_CS5_SIZE 0x01208000 -#define CFG_CS5_CFG 0x1414BF10 -#endif - #define CFG_RESET_ADDRESS 0xff000000 /*----------------------------------------------------------------------- @@ -719,16 +615,4 @@ /* Interval between registers */ #define CFG_ATA_STRIDE 4 -/*----------------------------------------------------------------------- - * Open firmware flat tree support - *----------------------------------------------------------------------- - */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - #endif /* __CONFIG_H */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 9cc196410..b1c70f88c 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -37,8 +37,6 @@ #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ #ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ -#define CONFIG_LCD_INFO 1 /* ... and some board info */ #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ #endif @@ -53,7 +51,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS @@ -71,17 +69,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM823L\0" \ - "bootfile=TQM823L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM823L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM823L/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -98,42 +88,34 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - #ifdef CONFIG_SPLASH_SCREEN - #define CONFIG_CMD_BMP +# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BMP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +#else +# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) #endif - -#define CONFIG_NETCONSOLE +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -141,13 +123,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -205,15 +188,11 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -223,20 +202,6 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -248,7 +213,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 5edd37935..9f958f547 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -51,7 +51,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS @@ -69,17 +69,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM823M\0" \ - "bootfile=TQM823M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM823M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM823M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -96,39 +88,23 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -136,13 +112,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -200,39 +177,21 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -244,7 +203,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index ced87b507..49c387263 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -66,7 +66,7 @@ #define CONFIG_BAUDRATE 9600 #endif -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS @@ -167,7 +167,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. * * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the * X.29 connector, and FCC2 is hardwired to the X.1 connector) @@ -219,42 +220,24 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -395,7 +378,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 0d2ca7225..cec7e3ece 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -28,17 +28,19 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define DEBUG +#undef DEBUG + /* * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC83XX 1 /* MPC83XX family */ #define CONFIG_MPC834X 1 /* MPC834X specific */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_TQM834X 1 /* TQM834X board specific */ /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ -#define CFG_IMMR 0xff400000 +#define CFG_IMMRBAR 0xff400000 /* System clock. Primary input clock when in PCI host mode */ #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ @@ -81,7 +83,6 @@ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ /* buffered writes in the AMD chip set is not supported yet */ #undef CFG_FLASH_USE_BUFFER_WRITE @@ -113,7 +114,7 @@ extern int tqm834x_num_flash_banks; BR_MS_GPCM | BR_PS_32 | BR_V) /* FLASH timing (0x0000_0c54) */ -#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \ +#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \ OR_GPCM_SCY_5 | OR_GPCM_TRLX) #define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ @@ -176,12 +177,12 @@ extern int tqm834x_num_flash_banks; #define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* * Serial Port @@ -196,15 +197,14 @@ extern int tqm834x_num_flash_banks; #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) -#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) +#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) /* * I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_FSL_I2C #define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ #define CFG_I2C_SLAVE 0x7F /* slave address */ #define CFG_I2C_OFFSET 0x3000 @@ -231,13 +231,13 @@ extern int tqm834x_num_flash_banks; /* * TSEC */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_MII #define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET) +#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) #define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET) +#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) #if defined(CONFIG_TSEC_ENET) @@ -245,16 +245,14 @@ extern int tqm834x_num_flash_banks; #define CONFIG_NET_MULTI #endif -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" @@ -280,6 +278,7 @@ extern int tqm834x_num_flash_banks; #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ + #undef CONFIG_EEPRO100 #define CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -302,7 +301,7 @@ extern int tqm834x_num_flash_banks; #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH 1 /* Flash is not usable now */ @@ -314,38 +313,39 @@ extern int tqm834x_num_flash_banks; #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif +/* Common commands */ +#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\ + | CFG_CMD_PING | CFG_CMD_EEPROM \ + | CFG_CMD_MII | CFG_CMD_JFFS2 #if defined(CFG_RAMBOOT) - #undef CONFIG_CMD_ENV - #undef CONFIG_CMD_LOADS + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \ + | CFG_CMD_TQM8349_COMMON) \ + & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_TQM8349_COMMON) \ + & \ + ~(CFG_CMD_ENV | CFG_CMD_LOADS)) #endif +#else /* CFG_RAMBOOT */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ + | CFG_CMD_TQM8349_COMMON) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_TQM8349_COMMON) +#endif + +#endif /* CFG_RAMBOOT */ + +#include + /* * Miscellaneous configurable options */ @@ -353,13 +353,7 @@ extern int tqm834x_num_flash_banks; #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -379,6 +373,15 @@ extern int tqm834x_num_flash_banks; */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +/* + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ @@ -419,11 +422,9 @@ extern int tqm834x_num_flash_banks; #define CFG_SICRL SICRL_LDP_A /* i-cache and d-cache disabled */ -#define CFG_HID0_INIT 0x000000000 -#define CFG_HID0_FINAL CFG_HID0_INIT -#define CFG_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID2 0x000000000 /* DDR 0 - 512M */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) @@ -436,25 +437,16 @@ extern int tqm834x_num_flash_banks; #define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) /* PCI */ -#ifdef CONFIG_PCI -#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP) -#else -#define CFG_IBAT3L (0) -#define CFG_IBAT3U (0) -#define CFG_IBAT4L (0) -#define CFG_IBAT4U (0) -#define CFG_IBAT5L (0) -#define CFG_IBAT5U (0) -#endif /* IMMRBAR */ -#define CFG_IBAT6L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT6U (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP) +#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) /* FLASH */ #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) @@ -485,7 +477,7 @@ extern int tqm834x_num_flash_banks; #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -494,7 +486,23 @@ extern int tqm834x_num_flash_banks; * Environment Configuration */ -#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR D2:DA:5E:44:BC:29 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53 +#endif + +#define CONFIG_IPADDR 192.168.205.1 + +#define CONFIG_HOSTNAME tqm8349 +#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx +#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -502,14 +510,14 @@ extern int tqm834x_num_flash_banks; #define CONFIG_BAUDRATE 115200 #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "hostname=tqm834x\0" \ + "hostname=tqm83xx\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -521,16 +529,16 @@ extern int tqm834x_num_flash_banks; "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 400000 ${bootfile};run nfsargs addip addtty;" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/tqm834x/uImage\0" \ + "bootfile=/tftpboot/tqm83xx/uImage\0" \ "kernel_addr=80060000\0" \ "ramdisk_addr=80160000\0" \ - "load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0" \ + "load=tftp 100000 /tftpboot/tqm83xx/u-boot.bin\0" \ "update=protect off 80000000 8003ffff; " \ "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ - "upd=run load update\0" \ + "upd=run load;run update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -543,7 +551,7 @@ extern int tqm834x_num_flash_banks; #define MTDIDS_DEFAULT "nor0=TQM834x-0" /* default mtd partition table */ -#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\ +#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\ "1m(kernel),2m(initrd),"\ "-(user);"\ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 9edf0d807..16b2ce3f0 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -47,7 +47,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS @@ -65,17 +65,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM850L\0" \ - "bootfile=TQM850L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM850L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM850L/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -88,37 +80,23 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -/* - * Command line configuration. - */ -#include +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -126,13 +104,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -190,15 +169,11 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -208,20 +183,6 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -233,7 +194,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index e2c1ce80f..bbc69608b 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -45,7 +45,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS @@ -63,17 +63,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM850M\0" \ - "bootfile=TQM850M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM850M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM850M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -86,38 +78,23 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -125,13 +102,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -189,39 +167,21 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -233,7 +193,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index dd19d4e57..198db1954 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -49,7 +49,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -68,17 +68,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM855L\0" \ - "bootfile=TQM855L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM855L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM855L/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -91,39 +83,23 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -131,13 +107,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -195,15 +172,11 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -213,20 +186,6 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -238,7 +197,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 8a1c350cc..e25a7a204 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -49,7 +49,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -68,17 +68,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM855M\0" \ - "bootfile=TQM855M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM855M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM855M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -124,40 +116,24 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 5 #endif -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -165,13 +141,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -229,39 +206,21 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -273,7 +232,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d18f2346c..780f27433 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -1,7 +1,4 @@ /* - * (C) Copyright 2007 - * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. - * * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -30,7 +27,7 @@ */ /* - * TQM85xx (8560/40/55/41/48) board configuration file + * TQM85xx (8560/40/55/41) board configuration file */ #ifndef __CONFIG_H @@ -42,53 +39,23 @@ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ #define CONFIG_PCI -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */ -#ifdef CONFIG_TQM8548 -#define CONFIG_PCI1 -#define CONFIG_PCIE1 -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#endif - #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ - /* - * Configuration for big NOR Flashes - * - * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash. - * Please be aware, that this changes the whole memory map (new CCSRBAR - * address, etc). You have to use an adapted Linux kernel or FDT blob - * if this option is set. - */ -#undef CONFIG_TQM_BIGFLASH - /* - * NAND flash support (disabled by default) - * - * Warning: NAND support will likely increase the U-Boot image size - * to more than 256 KB. Please adjust TEXT_BASE if necessary. + * Only MPC8540 doesn't have CPM module */ -#undef CONFIG_NAND - -/* - * MPC8540 and MPC8548 don't have CPM module - */ -#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548) +#ifndef CONFIG_MPC8540 #define CONFIG_CPM2 1 /* has CPM2 */ #endif -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ - -#undef CONFIG_CAN_DRIVER /* CAN Driver support */ - /* * sysclk for MPC85xx * * Two valid values are: - * 33333333 - * 66666666 + * 33000000 + * 66000000 * * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz * is likely the desired value here, so that is now the default. @@ -119,138 +86,79 @@ * actual resources get mapped (not physical addresses) */ #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ -#ifdef CONFIG_TQM_BIGFLASH -#define CFG_CCSRBAR 0xA0000000 /* relocated CCSRBAR */ -#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ -#endif /* CONFIG_TQM_BIGFLASH */ -#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -#define CFG_PCI1_ADDR (CFG_CCSRBAR + 0x8000) -#define CFG_PCI2_ADDR (CFG_CCSRBAR + 0x9000) -#define CFG_PCIE1_ADDR (CFG_CCSRBAR + 0xa000) - /* * DDR Setup */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE +#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/ #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) /* TQM8540 & 8560 need DLL-override */ #define CONFIG_DDR_DLL /* DLL fix needed */ #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ -#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */ +#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */ -#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \ - defined(CONFIG_TQM8548) +#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ -#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */ - -/* - * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM - * series while new boards have 'N' type Flashes from the S29GLxxxN - * series, which have bigger sectors: 2 x 128 instead of 2 x 64 KB. - */ -#ifdef CONFIG_TQM8548 -#define CONFIG_TQM_FLASH_N_TYPE -#endif /* CONFIG_TQM8548 */ +#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */ /* * Flash on the Local Bus */ -#ifdef CONFIG_TQM_BIGFLASH -#define CFG_FLASH0 0xE0000000 -#define CFG_FLASH1 0xC0000000 -#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_FLASH0 0xFC000000 #define CFG_FLASH1 0xF8000000 -#endif /* CONFIG_TQM_BIGFLASH */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ -#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ +#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ -/* Default ORx timings are for <= 41.7 MHz Local Bus Clock. - * - * Note: According to timing specifications external addr latch delay - * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz. - * - * For other Local Bus Clocks see following table: - * - * Clock/MHz CFG_ORx_PRELIM - * 166 0x.....CA5 - * 133 0x.....C85 - * 100 0x.....C65 - * 83 0x.....FA2 - * 66 0x.....C82 - * 50 0x.....C60 - * 42 0x.....040 - * 33 0x.....030 - * 25 0x.....020 - * - */ -#ifdef CONFIG_TQM_BIGFLASH -#define CFG_BR0_PRELIM 0xE0001801 /* port size 32bit */ -#define CFG_OR0_PRELIM 0xE0000040 /* 512MB Flash */ -#define CFG_BR1_PRELIM 0xC0001801 /* port size 32bit */ -#define CFG_OR1_PRELIM 0xE0000040 /* 512MB Flash */ -#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ #define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */ -#endif /* CONFIG_TQM_BIGFLASH */ -#define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */ -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -/* - * Note: when changing the Local Bus clock divider you have to - * change the timing values in CFG_ORx_PRELIM. - * - * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8. - * LCRR[16:17] EADC : External address delay cycles. It should be set to 2 - * for Local Bus Clock > 83.3 MHz. - */ -#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ +#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR (CFG_CCSRBAR \ - + 0x04010000) /* Initial RAM address */ +#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */ -#define CFG_MALLOC_LEN (384 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #if defined(CONFIG_TQM8560) -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#else /* !CONFIG_TQM8560 */ +#else /* ! TQM8560 */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO @@ -263,50 +171,33 @@ #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) /* PS/2 Keyboard */ +#if !defined(CONFIG_TQM8560) #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ #define CONFIG_PS2SERIAL 2 /* .. on DUART2 */ #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ #define CONFIG_BOARD_EARLY_INIT_R 1 +#endif /* !CONFIG_TQM8560 */ #endif /* CONFIG_TQM8560 */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -/* CAN */ -#define CFG_CAN_BASE (CFG_CCSRBAR \ - + 0x03000000) /* CAN base address */ -#ifdef CONFIG_CAN_DRIVER -#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */ -#define CFG_OR2_CAN (CFG_CAN_OR_AM | OR_UPM_BI) -#define CFG_BR2_CAN ((CFG_CAN_BASE & BR_BA) | \ - BR_PS_8 | BR_MS_UPMC | BR_V) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * I2C - */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +/* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ -#define CFG_I2C_OFFSET 0x3000 /* I2C RTC */ #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ @@ -321,7 +212,7 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ #define CFG_EEPROM_PAGE_WRITE_ENABLE #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ /* I2C SYSMON (LM75) */ #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ @@ -330,64 +221,10 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 -#ifndef CONFIG_PCIE1 /* RapidIO MMU */ -#ifdef CONFIG_TQM_BIGFLASH -#define CFG_RIO_MEM_BASE 0xb0000000 /* base address */ -#define CFG_RIO_MEM_SIZE 0x10000000 /* 256M */ -#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ -#endif /* CONFIG_TQM_BIGFLASH */ #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#endif /* CONFIG_PCIE1 */ - -/* NAND FLASH */ -#ifdef CONFIG_NAND - -#undef CFG_NAND_LEGACY - -#define CONFIG_NAND_FSL_UPM 1 - -#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */ - -/* address distance between chip selects */ -#define CFG_NAND_SELECT_DEVICE 1 -#define CFG_NAND_CS_DIST 0x200 - -#define CFG_NAND_SIZE 0x8000 -#define CFG_NAND0_BASE (CFG_CCSRBAR + 0x03010000) -#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) -#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) -#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) - -#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 - -#if (CFG_MAX_NAND_DEVICE == 1) -#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } -#elif (CFG_MAX_NAND_DEVICE == 2) -#define CFG_NAND_QUIET_TEST 1 -#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ - CFG_NAND1_BASE, \ -} -#elif (CFG_MAX_NAND_DEVICE == 4) -#define CFG_NAND_QUIET_TEST 1 -#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ - CFG_NAND1_BASE, \ - CFG_NAND2_BASE, \ - CFG_NAND3_BASE, \ -} -#endif - -/* CS3 for NAND Flash */ -#define CFG_BR3_PRELIM ((CFG_NAND0_BASE & BR_BA) | BR_PS_8 | \ - BR_MS_UPMB | BR_V) -#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | OR_UPM_BI) - -#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */ - -#endif /* CONFIG_NAND */ +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI @@ -396,33 +233,9 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE (CFG_CCSRBAR + 0x02000000) +#define CFG_PCI1_IO_BASE 0xe2000000 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - -/* PCI view of System Memory */ -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x80000000 - -#ifdef CONFIG_PCIE1 -/* - * General PCI express - * Addresses are mapped 1-1. - */ -#ifdef CONFIG_TQM_BIGFLASH -#define CFG_PCIE1_MEM_BASE 0xb0000000 -#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 512M */ -#define CFG_PCIE1_IO_BASE 0xaf000000 -#else /* !CONFIG_TQM_BIGFLASH */ -#define CFG_PCIE1_MEM_BASE 0xc0000000 -#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCIE1_IO_BASE 0xef000000 -#endif /* CONFIG_TQM_BIGFLASH */ -#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE -#define CFG_PCIE1_IO_PHYS CFG_PCIE1_IO_BASE -#define CFG_PCIE1_IO_SIZE 0x1000000 /* 16M */ -#endif /* CONFIG_PCIE1 */ +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ #if defined(CONFIG_PCI) @@ -434,49 +247,25 @@ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ -#endif /* CONFIG_PCI */ +#endif /* CONFIG_PCI */ + #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_MPC85XX_TSEC1 1 +#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC85XX_TSEC2 1 +#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT #define FEC_PHY_ADDR 3 #define FEC_PHYIDX 0 -#define FEC_FLAGS 0 -#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 -#ifdef CONFIG_TQM8548 -/* - * TQM8548 has 4 ethernet ports. 4 ETSEC's. - * - * On the STK85xx Starterkit the ETSEC3/4 ports are on an - * additional adapter (AIO) between module and Starterkit. - */ -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "TSEC2" -#define CONFIG_TSEC4 1 -#define CONFIG_TSEC4_NAME "TSEC3" -#define TSEC3_PHY_ADDR 4 -#define TSEC4_PHY_ADDR 5 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define CONFIG_HAS_ETH3 -#define CONFIG_HAS_ETH4 -#endif /* CONFIG_TQM8548 */ - /* Options are TSEC[0-1], FEC */ #define CONFIG_ETHPRIME "TSEC0" @@ -505,7 +294,7 @@ * FCC2: a - c (X50.2 - 1) */ #define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ +#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ #endif #if defined(CONFIG_TQM8560) @@ -521,13 +310,12 @@ * FCC3: a - d (X50.2 - 3) */ #define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ +#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ #endif #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) #define CONFIG_ETHER_ON_FCC1 -#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \ - CMXFCR_TF1CS_MSK) +#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) #define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -535,8 +323,7 @@ #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) #define CONFIG_ETHER_ON_FCC2 -#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \ - CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) #define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -544,8 +331,7 @@ #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) #define CONFIG_ETHER_ON_FCC3 -#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \ - CMXFCR_TF3CS_MSK) +#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) #define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -555,69 +341,36 @@ * Environment */ #define CFG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_TQM_FLASH_N_TYPE -#define CFG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */ -#else /* !CONFIG_TQM_FLASH_N_TYPE */ -#define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ -#endif /* CONFIG_TQM_FLASH_N_TYPE */ -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_TIMESTAMP /* Print image info with ts */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -#ifdef CONFIG_NAND -/* - * Use NAND-FLash as JFFS2 device - */ -#define CONFIG_CMD_NAND -#define CONFIG_CMD_JFFS2 - -#define CONFIG_JFFS2_NAND 1 - -#ifdef CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nand0=TQM85xx-nand" -#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-" -#else -#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ -#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */ -#endif /* CONFIG_JFFS2_CMDLINE */ - -#endif /* CONFIG_NAND */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_DTT -#define CONFIG_CMD_MII +#define CONFIG_TIMESTAMP /* Print image info with ts */ #if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI +# define ADD_PCI_CMD (CFG_CMD_PCI) +#else +# define ADD_PCI_CMD 0 #endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + ADD_PCI_CMD | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DTT | \ + CFG_CMD_MII | \ + CFG_CMD_PING ) +#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ /* @@ -627,14 +380,13 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE + \ - sizeof(CFG_PROMPT) + 16) /* Print Buf Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ @@ -646,6 +398,13 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + /* * Internal Definitions * @@ -654,41 +413,26 @@ #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ - -/* - * Setup some board specific values for the default environment variables - */ -#ifdef CONFIG_CPM2 -#define CFG_ENV_CONSDEV "consdev=ttyCPM0\0" -#else -#define CFG_ENV_CONSDEV "consdev=ttyS0\0" -#endif -#define CFG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \ - MK_STR(CONFIG_HOSTNAME)".dtb\0" -#define CFG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0" -#define CFG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \ - "uboot_addr="MK_STR(TEXT_BASE)"\0" - #define CONFIG_EXTRA_ENV_SETTINGS \ - CFG_ENV_BOOTFILE \ - CFG_ENV_FDT_FILE \ - CFG_ENV_CONSDEV \ + CFG_BOOTFILE \ "netdev=eth0\0" \ + "consdev=ttyS0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -698,27 +442,20 @@ "addcons=setenv bootargs $bootargs " \ "console=$consdev,$baudrate\0" \ "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr - $fdt_addr\0" \ + "bootm $kernel_addr\0" \ "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ - "net_nfs=tftp $kernel_addr_r $bootfile;" \ - "tftp $fdt_addr_r $fdt_file;" \ - "run nfsargs addip addcons;" \ - "bootm $kernel_addr_r - $fdt_addr_r\0" \ + "bootm $kernel_addr $ramdisk_addr\0" \ + "net_nfs=tftp $loadaddr $bootfile;" \ + "run nfsargs addip addcons;bootm\0" \ "rootpath=/opt/eldk/ppc_85xx\0" \ - "fdt_addr_r=900000\0" \ - "kernel_addr_r=1000000\0" \ - "fdt_addr=ffec0000\0" \ - "kernel_addr=ffd00000\0" \ - "ramdisk_addr=ff800000\0" \ - CFG_ENV_UBOOT \ - "load=tftp 100000 $uboot\0" \ - "update=protect off $uboot_addr +$filesize;" \ - "erase $uboot_addr +$filesize;" \ - "cp.b 100000 $uboot_addr $filesize;" \ + "kernel_addr=FE000000\0" \ + "ramdisk_addr=FE100000\0" \ + "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ + "upd=run load;run update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 803cdb854..4a1a4325d 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -49,7 +49,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -68,17 +68,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM860L\0" \ - "bootfile=TQM860L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM860L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM860L/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -91,52 +83,41 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) #define CONFIG_NETCONSOLE +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -194,15 +175,11 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ @@ -212,20 +189,6 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -237,7 +200,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 071da1e60..4b754ba9c 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -49,7 +49,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -68,17 +68,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM860M\0" \ - "bootfile=TQM860M/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM860M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM860M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -91,39 +83,24 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -131,13 +108,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -183,7 +161,7 @@ #define CFG_FLASH_BASE 0x40000000 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -195,38 +173,21 @@ /*----------------------------------------------------------------------- * FLASH organization */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -238,7 +199,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -389,7 +350,7 @@ */ #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */ +#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ #define CFG_OR_TIMING_SDRAM 0x00000A00 @@ -465,10 +426,7 @@ #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 10 column SDRAM */ -#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + /* * Internal Definitions diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index d34f6bea6..1dc9f74d5 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -52,7 +52,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -71,17 +71,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM862L\0" \ - "bootfile=TQM862L/uImage\0" \ - "fdt_addr=40040000\0" \ - "kernel_addr=40060000\0" \ - "ramdisk_addr=40200000\0" \ - "u-boot=TQM862L/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM862L/uImage\0" \ + "kernel_addr=40040000\0" \ + "ramdisk_addr=40100000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -94,39 +86,23 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -134,13 +110,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -198,17 +175,14 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ @@ -216,20 +190,6 @@ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ - "128k(dtb)," \ - "1664k(kernel)," \ - "2m(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -241,7 +201,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 9270e4498..3df060c61 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -52,7 +52,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -71,17 +71,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM862M\0" \ - "bootfile=TQM862M/uImage\0" \ - "fdt_addr=40080000\0" \ - "kernel_addr=400A0000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM862M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM862M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -94,39 +86,23 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -134,13 +110,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -198,39 +175,22 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -242,7 +202,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index d916d5337..8f9c2c9cb 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -61,7 +61,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -80,17 +80,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "hostname=TQM866M\0" \ - "bootfile=TQM866M/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "u-boot=TQM866M/u-image.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=prot off 40000000 +${filesize};" \ - "era 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "sete filesize;save\0" \ + "bootfile=/tftpboot/TQM866M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -133,15 +125,7 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 4 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -150,24 +134,16 @@ #define CONFIG_TIMESTAMP /* but print image timestmps */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IDE -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -#define CONFIG_NETCONSOLE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -175,13 +151,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -227,7 +204,7 @@ #define CFG_FLASH_BASE 0x40000000 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -239,38 +216,21 @@ /*----------------------------------------------------------------------- * FLASH organization */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ -#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ - -/*----------------------------------------------------------------------- - * Dynamic MTD partition support - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=TQM8xxM-0" - -#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ - "128k(dtb)," \ - "1920k(kernel)," \ - "5632(rootfs)," \ - "4m(data)" - /*----------------------------------------------------------------------- * Hardware Information Block */ @@ -282,7 +242,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -448,30 +408,26 @@ #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) /* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. + * Memory Periodic Timer Prescaler + * Periodic timer for refresh, start with refresh rate for 40 MHz clock + * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) */ -#define CFG_MAMR_PTA 97 +#define CFG_MAMR_PTA 39 /* - * Memory Periodic Timer Prescaler Register (MPTPR) values. + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ /* * MAMR settings for SDRAM diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index f075442f3..ede4e3b9b 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -42,10 +42,17 @@ #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ #define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ #define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ -#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ +#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */ /* (it will be used if there is no */ /* 'cpuclk' variable with valid value) */ +#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */ + /* (function measure_gclk() */ + /* will be called) */ +#ifdef CFG_MEASURE_CPUCLK +#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */ +#endif + #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ @@ -57,7 +64,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -76,15 +83,9 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/TQM885D/uImage\0" \ - "fdt_addr=400C0000\0" \ - "kernel_addr=40100000\0" \ - "ramdisk_addr=40280000\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 40000000 +${filesize};" \ - "erase 40000000 +${filesize};" \ - "cp.b 200000 40000000 ${filesize};" \ - "protect on 40000000 +${filesize}\0" \ + "bootfile=/tftpboot/TQM866M/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -130,39 +131,28 @@ # define CONFIG_RTC_DS1337 1 # define CFG_I2C_RTC_ADDR 0x68 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ +#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ #define CONFIG_TIMESTAMP /* but print image timestmps */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -170,13 +160,14 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#if 0 +#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ +#endif #ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -197,7 +188,8 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* - * Enable loopw command. + * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) */ #define CONFIG_LOOPW @@ -229,7 +221,7 @@ #define CFG_FLASH_BASE 0x40000000 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ /* * For booting Linux, the board info and command line data @@ -241,20 +233,16 @@ /*----------------------------------------------------------------------- * FLASH organization */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_USE_BUFFER_WRITE 1 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ -#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) @@ -271,7 +259,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -437,30 +425,26 @@ #define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) /* - * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) - * - * CPUclock(MHz) * 31.2 - * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0 - * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 - * - * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us - * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us - * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us - * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us - * - * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will - * be met also in the default configuration, i.e. if environment variable - * 'cpuclk' is not set. + * Memory Periodic Timer Prescaler + * Periodic timer for refresh, start with refresh rate for 40 MHz clock + * (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK) */ -#define CFG_MAMR_PTA 128 +#define CFG_MAMR_PTA 39 /* - * Memory Periodic Timer Prescaler Register (MPTPR) values. + * For 16 MBit, refresh rates could be 31.3 us + * (= 64 ms / 2K = 125 / quad bursts). + * For a simpler initialization, 15.6 us is used instead. + * + * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks + * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank */ -/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ -#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 -/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ -#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ + +/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ +#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ /* * MAMR settings for SDRAM @@ -495,9 +479,8 @@ #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ -#if defined(CONFIG_CMD_MII) +#if (CONFIG_COMMANDS & CFG_CMD_MII) #define CFG_DISCOVER_PHY -#define CONFIG_MII_INIT 1 #endif #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 598fe7bf2..817570323 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -48,7 +48,10 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -60,6 +63,7 @@ /* * Video console */ +#if 1 #define CONFIG_VIDEO #define CONFIG_VIDEO_SED13806 #define CONFIG_VIDEO_SED13806_16BPP @@ -72,6 +76,10 @@ #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN +#define ADD_VIDEO_CMD CFG_CMD_BMP +#else +#define ADD_VIDEO_CMD 0 +#endif #ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ /* @@ -82,7 +90,6 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 #define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_PCI_MEM_BUS 0x40000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -98,9 +105,12 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 +#define ADD_PCI_CMD CFG_CMD_PCI + #else /* MGT5100 */ #define CONFIG_MII 1 +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ #endif @@ -109,36 +119,29 @@ #define CONFIG_DOS_PARTITION /* USB */ +#if 1 #define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#if defined(CONFIG_MPC5200) - #define CONFIG_CMD_PCI +#else +#define ADD_USB_CMD 0 #endif -#define CONFIG_CMD_BMP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_IDE | \ + ADD_VIDEO_CMD | \ + ADD_PCI_CMD | \ + ADD_USB_CMD) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #if (TEXT_BASE == 0xFE000000) /* Boot low */ # define CFG_LOWBOOT 1 @@ -152,7 +155,7 @@ #define CONFIG_PREBOOT \ "setenv stdout serial;setenv stderr serial;" \ "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -180,7 +183,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #endif /* @@ -300,7 +303,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -316,12 +319,6 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - /* * Various low-level settings */ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index ad8db613e..5f48a7093 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -44,37 +44,31 @@ #define USE_920T_MMU 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 +/*********************************************************** + * Command definition + ***********************************************************/ +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + /*CFG_CMD_JFFS2 |*/ \ + /*CFG_CMD_NAND |*/ \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_USB | \ + CFG_CMD_REGINFO | \ + CFG_CMD_FAT | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_BSP) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_USB -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FAT -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_BSP - +/* this must be included after the definiton of CONFIG_COMMANDS */ +#include #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " @@ -84,8 +78,8 @@ * address 0x50 with 16bit addressing ***********************************************************/ #define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ #define CFG_I2C_EEPROM_ADDR 0x50 #define CFG_I2C_EEPROM_ADDR_LEN 2 @@ -111,7 +105,7 @@ */ #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ #define CS8900_BASE 0x20000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ #define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ @@ -145,13 +139,13 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 10.0.0.110 #define CONFIG_SERVERIP 10.0.0.1 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ @@ -252,7 +246,7 @@ /*----------------------------------------------------------------------- * NAND flash settings */ -#if defined(CONFIG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) #define CFG_NAND_LEGACY #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ @@ -262,7 +256,7 @@ #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 @@ -286,6 +280,6 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_MTD_NAND_ECC_JFFS2 1 -#endif +#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ #endif /* __CONFIG_H */ diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 3ca928ec9..96f3d26cc 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -52,50 +52,34 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_NET_MULTI 1 -#undef CONFIG_HAS_ETH1 - #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ @@ -114,7 +98,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -157,18 +141,38 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } -#define NAND_MAX_CHIPS 1 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 +#define CFG_NAND_LEGACY -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 -#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CFG_NAND_QUIET 1 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- * PCI stuff @@ -208,6 +212,8 @@ #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ +#define CONFIG_ATAPI 1 /* ATAPI for Travelstar */ + #define CFG_ATA_BASE_ADDR 0xF0100000 #define CFG_ATA_IDE0_OFFSET 0x0000 #define CFG_ATA_IDE1_OFFSET 0x0010 @@ -246,6 +252,11 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#if 0 /* test-only */ +#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ +#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ +#endif + /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) @@ -278,12 +289,19 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */ -#define CFG_EEPROM_WREN 1 - +#if 0 /* test-only */ +/* CAT24WC08/16... */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ +#else /* CAT24WC32/64... */ #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ @@ -291,9 +309,20 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ /* 32 byte page write mode using*/ /* last 5 bits of the address */ +#endif #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ @@ -389,20 +418,18 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO */ -#define CFG_GPIO0_OSRH 0x00000550 +#define CFG_GPIO0_OSRH 0x40000550 #define CFG_GPIO0_OSRL 0x00000110 #define CFG_GPIO0_ISR1H 0x00000000 #define CFG_GPIO0_ISR1L 0x15555440 #define CFG_GPIO0_TSRH 0x00000000 #define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0x777E0017 +#define CFG_GPIO0_TCR 0xF7FE0017 #define CFG_DUART_RST (0x80000000 >> 14) #define CFG_LCD_ENDIAN (0x80000000 >> 7) -#define CFG_IIC_ON (0x80000000 >> 8) #define CFG_LCD0_RST (0x80000000 >> 30) #define CFG_LCD1_RST (0x80000000 >> 31) -#define CFG_EEPROM_WP (0x80000000 >> 0) /* * Internal Definitions diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index ec6f20554..f2f3ea7cc 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -60,33 +60,24 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_SEND_HOSTNAME ) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_BSP | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_BSP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -105,7 +96,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -247,6 +238,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index db05d82bf..92bade518 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -95,7 +95,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC #define CONFIG_ETHER_ON_FCC @@ -137,34 +138,24 @@ #endif -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_AUTOSCRIPT -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_IMLS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN +/* configure commands */ +#define CONFIG_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_BDI | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IMLS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * boot options & environment @@ -215,7 +206,7 @@ #define CFG_PROMPT "=> " /* console i/o buffer size */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 #else #define CFG_CBSIZE 256 @@ -314,7 +305,7 @@ /* cache configuration */ #define CFG_CACHELINE_SIZE 32 /* for MPC8260 */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of above */ #endif @@ -369,7 +360,7 @@ /* * MEMORY MAP * ---------- - * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored) + * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored) * CS1 - SDRAM 32MB/64Bit base=0x00000000 * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000 * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000 diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index bb6b6b9d2..8dc623ea0 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -70,31 +70,13 @@ #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ + CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO) - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_BSP -#define CONFIG_CMD_REGINFO +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ @@ -110,7 +92,7 @@ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -154,10 +136,10 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Set up values for external bus controller @@ -290,6 +272,15 @@ */ #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ +#endif + /* * Init Memory Controller: */ @@ -318,7 +309,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 3050cafa1..2bd98b3af 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -75,34 +75,14 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ + CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \ + CFG_CMD_DTT) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_BSP -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_DTT - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ @@ -118,7 +98,7 @@ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -161,10 +141,10 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Set up values for external bus controller @@ -293,6 +273,15 @@ */ #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ +#endif + /* * Init Memory Controller: */ @@ -321,7 +310,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 582d8cf86..faf855d24 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -60,31 +60,19 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_IRQ | \ + CFG_CMD_ELF | \ + CFG_CMD_NAND | \ + CFG_CMD_DATE | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NAND -#define CONFIG_CMD_DATE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -104,7 +92,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -145,16 +133,38 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#define CFG_NAND_BASE_LIST { CFG_NAND_BASE } -#define NAND_MAX_CHIPS 1 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_BIG_DELAY_US 25 +#define CFG_NAND_LEGACY -#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ -#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ -#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ -#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ +#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ +#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */ +#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ + +#define NAND_DISABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);} while(0) +#define NAND_ENABLE_CE(nand) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CE);} while(0) +#define NAND_CTL_CLRALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_ALE);} while(0) +#define NAND_CTL_SETALE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_ALE);} while(0) +#define NAND_CTL_CLRCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND_CLE);} while(0) +#define NAND_CTL_SETCLE(nandptr) do { out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CLE);} while(0) +#define NAND_WAIT_READY(nand) while (!(in32(GPIO0_IR) & CFG_NAND_RDY)) + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ /*----------------------------------------------------------------------- @@ -254,6 +264,16 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Init Memory Controller: * diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 38ea576a6..9b3251486 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -182,33 +182,25 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ #define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_DATE | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_DIAG | \ + CFG_CMD_FAT ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +/* CFG_CMD_DHCP | \ */ +/* CFG_CMD_KGDB | \ */ -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DATE -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_FAT - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -217,7 +209,7 @@ extern void out32(unsigned int, unsigned long); */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -246,6 +238,7 @@ extern void out32(unsigned int, unsigned long); #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ @@ -257,6 +250,14 @@ extern void out32(unsigned int, unsigned long); * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Internal Definitions @@ -266,7 +267,7 @@ extern void out32(unsigned int, unsigned long); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h index 1b4195a08..37ef1058f 100644 --- a/include/configs/Yukon8220.h +++ b/include/configs/Yukon8220.h @@ -31,8 +31,6 @@ #define CONFIG_MPC8220 1 #define CONFIG_YUKON8220 1 /* ... on Yukon board */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ @@ -41,6 +39,12 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Serial console configuration */ @@ -66,40 +70,31 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BOOTD | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) #define CONFIG_NET_MULTI #define CONFIG_MII +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Autobooting */ @@ -298,7 +293,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -314,11 +309,6 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Various low-level settings */ diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index b04be766f..a5085cfb7 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -55,8 +55,8 @@ * SCC, 1-3 for FCC) * * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. + * must be defined elsewhere (as for the console), or CFG_CMD_NET must + * be removed from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ @@ -106,33 +106,22 @@ #define CONFIG_BAUDRATE 38400 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_ASKENV \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -150,7 +139,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -200,13 +189,13 @@ HRCW_MODCK_H0111 \ ) /* 0x16848207 */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ @@ -234,7 +223,7 @@ #endif #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -259,18 +248,18 @@ #define CFG_LSRT 0x0F #define CFG_MPTPR 0x4000 -#define CFG_PSDRAM_BR (CFG_SDRAM_BASE | 0x00000041) +#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041 #define CFG_PSDRAM_OR 0xFC0028C0 -#define CFG_LSDRAM_BR (CFG_LSDRAM_BASE | 0x00001861) +#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861 #define CFG_LSDRAM_OR 0xFF803480 -#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00000801) +#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 #define CFG_OR0_PRELIM 0xFFE00856 -#define CFG_BR5_PRELIM (CFG_EEPROM | 0x00000801) +#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 #define CFG_OR5_PRELIM 0xFFFF03F6 -#define CFG_BR6_PRELIM (CFG_FLSIMM_BASE | 0x00001801) +#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801 #define CFG_OR6_PRELIM 0xFF000856 -#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801) +#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 #define CFG_OR7_PRELIM 0xFFFF83F6 #define CFG_RESET_ADDRESS 0xC0000000 diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h index 5ba8d1a71..f163d003b 100644 --- a/include/configs/ZUMA.h +++ b/include/configs/ZUMA.h @@ -101,29 +101,17 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MII /* enable MII commands */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_DATE - +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BSP | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_MII | \ + CFG_CMD_DATE) /* * JFFS2 partitions @@ -143,12 +131,15 @@ #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -358,7 +349,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h new file mode 100644 index 000000000..c4108912a --- /dev/null +++ b/include/configs/adsvix.h @@ -0,0 +1,347 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ +#define CONFIG_ADSVIX 1 /* on a Adsvix Board */ +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define RTC + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART on ADSVIX */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 38400 + +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SERVERIP 192.168.1.99 +#define CONFIG_BOOTCOMMAND "run boot_flash" +#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\ + " rw root=/dev/ram initrd=0xa0800000,5m" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "program_boot_cf=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if pinit on && " \ + "ide reset && " \ + "fatload ide 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_cf=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if pinit on && " \ + "ide reset && " \ + "fatload ide 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_cf=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if pinit on && " \ + "ide reset && " \ + "fatload ide 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_cf=" \ + "if pinit on && " \ + "ide reset && " \ + "fatload ide 0 0xa0030000 uzImage && " \ + "fatload ide 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "program_boot_mmc=" \ + "mw.b 0xa0010000 0xff 0x20000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 u-boot.bin; " \ + "then " \ + "protect off 0x0 0x1ffff; " \ + "erase 0x0 0x1ffff; " \ + "cp.b 0xa0010000 0x0 0x20000; " \ + "fi\0" \ + "program_uzImage_mmc=" \ + "mw.b 0xa0010000 0xff 0x180000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 uzImage; " \ + "then " \ + "protect off 0x40000 0x1bffff; " \ + "erase 0x40000 0x1bffff; " \ + "cp.b 0xa0010000 0x40000 0x180000; " \ + "fi\0" \ + "program_ramdisk_mmc=" \ + "mw.b 0xa0010000 0xff 0x500000; " \ + "if mmcinit && " \ + "fatload mmc 0 0xa0010000 ramdisk.gz; " \ + "then " \ + "protect off 0x1c0000 0x6bffff; " \ + "erase 0x1c0000 0x6bffff; " \ + "cp.b 0xa0010000 0x1c0000 0x500000; " \ + "fi\0" \ + "boot_mmc=" \ + "if mmcinit && " \ + "fatload mmc 0 0xa0030000 uzImage && " \ + "fatload mmc 0 0xa0800000 ramdisk.gz; " \ + "then " \ + "bootm 0xa0030000; " \ + "fi\0" \ + "boot_flash=" \ + "cp.b 0x1c0000 0xa0800000 0x500000; " \ + "bootm 0x40000\0" \ + +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +/* #define CONFIG_INITRD_TAG 1 */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER 1 +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_DEVICE_NULLDEV 1 + +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_MMC_BASE 0xF0000000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ + +#define CFG_GPSR0_VAL 0x00018004 +#define CFG_GPSR1_VAL 0x004F0080 +#define CFG_GPSR2_VAL 0x13EFC000 +#define CFG_GPSR3_VAL 0x0006E032 +#define CFG_GPCR0_VAL 0x084AFE1A +#define CFG_GPCR1_VAL 0x003003F2 +#define CFG_GPCR2_VAL 0x0C014000 +#define CFG_GPCR3_VAL 0x00000C00 +#define CFG_GPDR0_VAL 0xCBC3BFFC +#define CFG_GPDR1_VAL 0x00FFABF3 +#define CFG_GPDR2_VAL 0x1EEFFC00 +#define CFG_GPDR3_VAL 0x0187EC32 +#define CFG_GAFR0_L_VAL 0x84400000 +#define CFG_GAFR0_U_VAL 0xA51A8010 +#define CFG_GAFR1_L_VAL 0x699A955A +#define CFG_GAFR1_U_VAL 0x0005A0AA +#define CFG_GAFR2_L_VAL 0x40000000 +#define CFG_GAFR2_U_VAL 0x0109A400 +#define CFG_GAFR3_L_VAL 0x54000000 +#define CFG_GAFR3_U_VAL 0x00001409 + +#define CFG_PSSR_VAL 0x20 + +/* + * Clock settings + */ +#define CFG_CKEN 0x00400200 +#define CFG_CCCR 0x02000290 /* 520Mhz */ +/* #define CFG_CCCR 0x02000210 416 Mhz */ + +/* + * Memory settings + */ + +#define CFG_MSC0_VAL 0x23F2B3DB +#define CFG_MSC1_VAL 0x0000CCD1 +#define CFG_MSC2_VAL 0x0000B884 +#define CFG_MDCNFG_VAL 0x08000AC8 +#define CFG_MDREFR_VAL 0x0000001E +#define CFG_MDMRS_VAL 0x00000000 + +#define CFG_FLYCNFG_VAL 0x00010001 +#define CFG_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000002 +#define CFG_MCMEM0_VAL 0x00004204 +#define CFG_MCMEM1_VAL 0x00000000 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00000000 +#define CFG_MCIO0_VAL 0x00008407 +#define CFG_MCIO1_VAL 0x00000000 + +#define CONFIG_PXA_PCMCIA 1 +#define CONFIG_PXA_IDE 1 + +#define CONFIG_PCMCIA_SLOT_A 1 +/* just to keep build system happy */ + +#define CFG_PCMCIA_MEM_ADDR 0x28000000 +#define CFG_PCMCIA_MEM_SIZE 0x04000000 + + +#define CFG_IDE_MAXBUS 1 +/* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 +/* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR 0x20000000 + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET 0x1f0 + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET 0x1f0 + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x3f0 + +/* + * FLASH and environment organization + */ + +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_MONITOR_BASE 0 +#define CFG_MONITOR_LEN 0x20000 + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* write flash less slowly */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* Flash environment locations */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/aev.h b/include/configs/aev.h index c5e475921..8d9f0a166 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -41,11 +41,14 @@ #define CONFIG_AEVFIFO 1 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Serial console configuration */ @@ -62,7 +65,6 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* #define CONFIG_PCI_SCAN_SHOW 1 */ -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_PCI_MEM_BUS 0x40000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -89,42 +91,34 @@ CFG_POST_I2C) #ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 +#else +#define CFG_CMD_POST_DIAG 0 #endif - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_BMP_CMD | \ + CFG_CMD_PCI | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -138,7 +132,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -172,17 +166,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ -#if defined(CFG_IPBCLK_EQUALS_XLBCLK) +#if defined(CFG_IPBSPEED_133) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ #endif /* @@ -330,7 +324,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -349,13 +343,9 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* - * Enable loopw command. + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) */ #define CONFIG_LOOPW @@ -372,7 +362,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 +#ifdef CFG_PCISPEED_66 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ #else #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h index 98a83db29..9a1c5596b 100644 --- a/include/configs/armadillo.h +++ b/include/configs/armadillo.h @@ -41,9 +41,9 @@ * (easy to change) */ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */ +#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -71,24 +71,15 @@ #define CONFIG_BAUDRATE 115200 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) /* | CFG_CMD_JFFS2)*/ -/* - * Command line configuration. - */ -#include - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" +#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" #define CONFIG_BOOTCOMMAND "bootm 40000 180000" diff --git a/include/configs/assabet.h b/include/configs/assabet.h index d10f092f9..1a69ebe0d 100644 --- a/include/configs/assabet.h +++ b/include/configs/assabet.h @@ -29,6 +29,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#undef DEBUG + /* * High Level Configuration Options * (easy to change) @@ -64,30 +66,18 @@ #define CONFIG_BAUDRATE 115200 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" #define CFG_AUTOLOAD "n" /* No autoload */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index cd2eae206..8fad55d81 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -51,7 +51,7 @@ #define MC_ASR_VAL 0x00000000 #define MC_AASR_VAL 0x00000000 #define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ @@ -97,26 +97,18 @@ #define CONFIG_BOOTDELAY 3 /* #define CONFIG_ENV_OVERWRITE 1 */ +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | CFG_CMD_MII |\ + CFG_CMD_DHCP ) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_IMI | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC | \ + CFG_CMD_LOADS )) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NAND - -#define CFG_NAND_LEGACY +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 @@ -132,7 +124,6 @@ #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ -#include /* needed for port definitions */ #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) @@ -159,15 +150,10 @@ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII -/* AC Characteristics */ -/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - #define CONFIG_HAS_DATAFLASH 1 #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) -#define CFG_MAX_DATAFLASH_BANKS 2 -#define CFG_MAX_DATAFLASH_PAGES 16384 +#define CFG_MAX_DATAFLASH_BANKS 2 +#define CFG_MAX_DATAFLASH_PAGES 16384 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ #define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ @@ -188,11 +174,11 @@ #else #define CFG_ENV_IS_IN_FLASH 1 #ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ -#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ -#else #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ #define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */ +#else +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */ +#define CFG_ENV_SIZE 0x2000 /* 0x8000 */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ #endif /* CFG_ENV_IS_IN_DATAFLASH */ @@ -200,25 +186,44 @@ #define CFG_LOAD_ADDR 0x21000000 /* default load address */ #ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ -#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) -#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ -#else #define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ #define CFG_U_BOOT_BASE PHYS_FLASH_1 #define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */ +#else +#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */ +#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000) +#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -#define CFG_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 } +#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif + #define CFG_HZ 1000 #define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ #define CONFIG_STACKSIZE (32*1024) /* regular stack */ diff --git a/include/configs/atc.h b/include/configs/atc.h index 285b4e4da..bf6c1709d 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -64,7 +64,9 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #undef CONFIG_ETHER_NONE /* define if ether on something else */ @@ -104,14 +106,14 @@ #define CONFIG_PREBOOT \ "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\ "echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp;" \ "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ + "nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\ "bootm" @@ -122,37 +124,27 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PCMCIA -#define CONFIG_CMD_DATE -#define CONFIG_CMD_IDE +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_DATE | \ + CFG_CMD_IDE) #define CONFIG_DOS_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -182,9 +174,9 @@ #define CONFIG_RTC_DS12887 -#define RTC_BASE_ADDR 0xF5000000 -#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 -#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 +#define RTC_BASE_ADDR 0xF5000000 +#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 +#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 #define CONFIG_MISC_INIT_R @@ -293,7 +285,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 41058f88c..2c1c31927 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005-2007 + * (C) Copyright 2005-2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -32,16 +32,9 @@ *----------------------------------------------------------------------*/ #define CONFIG_BAMBOO 1 /* Board is BAMBOO */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ -#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -/* - * Include common defines/options for all AMCC eval boards - */ -#define CONFIG_HOSTNAME bamboo -#include "amcc-common.h" - #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ /* @@ -50,11 +43,16 @@ * 2nd ethernet port you have to "undef" the following define. */ #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ +#define CFG_NAND_LEGACY /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 @@ -75,10 +73,9 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (4 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -86,9 +83,14 @@ * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 /* define this if you want console on UART1 */ #undef CONFIG_UART1_CONSOLE +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + /*----------------------------------------------------------------------- * NVRAM/RTC * @@ -102,18 +104,21 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +/* + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#if 1 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else -#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ -#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #endif /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ @@ -123,12 +128,12 @@ #define CFG_FLASH_ADDR1 0x2aa #define CFG_FLASH_WORD_SIZE unsigned char -#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ -#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ +#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ +#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ @@ -136,80 +141,66 @@ #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif /* CFG_ENV_IS_IN_FLASH */ -/* - * IPL (Initial Program Loader, integrated inside CPU) - * Will load first 4k from NAND (SPL) into cache and execute it from there. - * - * SPL (Secondary Program Loader) - * Will load special U-Boot version (NUB) from NAND and execute it. This SPL - * has to fit into 4kByte. It sets up the CPU and configures the SDRAM - * controller and the NAND controller so that the special U-Boot image can be - * loaded from NAND to SDRAM. - * - * NUB (NAND U-Boot) - * This NAND U-Boot (NUB) is a special U-Boot version which can be started - * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. - * - * On 440EPx the SPL is copied to SDRAM before the NAND controller is - * set up. While still running from cache, I experienced problems accessing - * the NAND controller. sr - 2006-08-25 - */ -#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ -#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ -#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ -#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ -#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) - -/* - * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) - */ -#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ - -/* - * Now the NAND chip has to be defined (no autodetection used!) - */ -#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ - -#define CFG_NAND_ECCSIZE 256 -#define CFG_NAND_ECCBYTES 3 -#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) -#define CFG_NAND_OOBSIZE 16 -#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) -#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} - -#ifdef CFG_ENV_IS_IN_NAND -/* - * For NAND booting the environment is embedded in the U-Boot image. Please take - * look at the file board/amcc/sequoia/u-boot-nand.lds for details. - */ -#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE -#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) -#endif - /*----------------------------------------------------------------------- - * NAND FLASH + * NAND-FLASH related *----------------------------------------------------------------------*/ -#define CFG_MAX_NAND_DEVICE 2 -#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE -#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) -#define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_ADDR + 2 } -#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ +#define NAND_CMD_REG (0x00) /* NandFlash Command Register */ +#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */ +#define NAND_DATA_REG (0x08) /* NandFlash Data Register */ +#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */ +#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */ +#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */ +#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */ +#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */ +#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */ +#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */ +#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */ +#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */ +#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */ +#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */ +#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */ +#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */ +#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */ +#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */ +#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -#define CFG_NAND_CS 1 -#else -#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ -/* Memory Bank 0 (NAND-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x018003c0 -#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) -#endif +/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */ +#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */ +#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */ +#define NAND0_CMD_READ2 0x50 +#define NAND0_CMD_READ_ID 0x90 +#define NAND0_CMD_READ_STATUS 0x70 +#define NAND0_CMD_RESET 0xFF +#define NAND0_CMD_PAGE_PROG 0x80 +#define NAND0_CMD_PAGE_PROG_TRUE 0x10 +#define NAND0_CMD_PAGE_PROG_DUMMY 0x11 +#define NAND0_CMD_BLOCK_ERASE 0x60 +#define NAND0_CMD_BLOCK_ERASE_END 0xD0 + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0) +#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0) +#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0) +#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG)) +#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01)) + +/* not needed with 440EP NAND controller */ +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) /*----------------------------------------------------------------------- * DDR SDRAM @@ -217,14 +208,15 @@ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #undef CONFIG_DDR_ECC /* don't use ECC */ #define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ -#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} -#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ -#define CONFIG_PROG_SDRAM_TLB +#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51} /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_MULTI_EEPROMS #define CFG_I2C_EEPROM_ADDR (0xa8>>1) @@ -238,20 +230,52 @@ #define CFG_ENV_OFFSET 0x0 #endif /* CFG_ENV_IS_IN_EEPROM */ -/* - * Default environment variables - */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_POWERPC \ - CONFIG_AMCC_DEF_ENV_PPC_OLD \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \ + "netdev=eth0\0" \ + "hostname=bamboo\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/bamboo/uImage\0" \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ + "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \ + "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ + "cp.b 100000 fffa0000 60000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ "" +#define CONFIG_BOOTCOMMAND "run flash_self" -#define CONFIG_HAS_ETH0 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 1 @@ -259,6 +283,16 @@ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #endif /* CONFIG_BAMBOO_NAND */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI 1 /* required for netconsole */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + #ifdef CONFIG_440EP /* USB */ #define CONFIG_USB_OHCI @@ -268,27 +302,69 @@ #define USB_2_0_DEVICE #endif /*CONFIG_440EP*/ -/* - * Commands additional to the ones defined in amcc-common.h - */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - #ifdef CONFIG_BAMBOO_NAND -#define CONFIG_CMD_NAND -#endif +#define _CFG_CMD_NAND CFG_CMD_NAND +#else +#define _CFG_CMD_NAND 0 +#endif /* CONFIG_BAMBOO_NAND */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_USB | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ + _CFG_CMD_NAND | \ + CFG_CMD_SNTP ) #define CONFIG_SUPPORT_VFAT -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_LYNXKDI 1 /* support kdi files */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING + +#ifdef CONFIG_CMDLINE_EDITING +#undef CONFIG_AUTO_COMPLETE +#else +#define CONFIG_AUTO_COMPLETE +#endif /*----------------------------------------------------------------------- * PCI stuff @@ -301,10 +377,39 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/barco.h b/include/configs/barco.h index 4f57067db..624fa1d6e 100644 --- a/include/configs/barco.h +++ b/include/configs/barco.h @@ -70,34 +70,26 @@ #define CONFIG_BOOTARGS "mem=32M" - -/* - * BOOTP options +/* Add support for a few extra bootp options like: + * - File size + * - DNS */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_EEPROM | \ + CFG_CMD_PCI ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI - -#undef CONFIG_CMD_NET - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTCOMMAND "boot_default" +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTCOMMAND "boot_default" /* * Miscellaneous configurable options @@ -118,6 +110,7 @@ */ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP +#undef CFG_CMD_NET #define PCI_ENET0_IOADDR 0x80000000 #define PCI_ENET0_MEMADDR 0x80000000 @@ -135,9 +128,9 @@ #define CONFIG_LOGBUFFER #ifdef CONFIG_LOGBUFFER -#define CFG_STDOUT_ADDR 0x1FFC000 +#define CFG_STDOUT_ADDR 0x1FFC000 #else -#define CFG_STDOUT_ADDR 0x2B9000 +#define CFG_STDOUT_ADDR 0x2B9000 #endif #define CFG_RESET_ADDRESS 0xFFF00100 @@ -158,9 +151,9 @@ #define CFG_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #endif @@ -347,7 +340,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index acce82f62..4a79835d6 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -37,12 +37,6 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_BUBINGA 1 /* ...on a BUBINGA board */ -/* - * Include common defines/options for all AMCC eval boards - */ -#define CONFIG_HOSTNAME bubinga -#include "amcc-common.h" - #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ @@ -86,34 +80,103 @@ #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ #endif -/* - * Default environment variables - */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_PPC \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "netdev=eth0\0" \ + "hostname=bubinga\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/bubinga/uImage\0" \ "kernel_addr=fff80000\0" \ "ramdisk_addr=fff90000\0" \ + "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ "" +#define CONFIG_BOOTCOMMAND "run net_nfs" +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ -/* - * Commands additional to the ones defined in amcc-common.h - */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */ +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + /* * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. * If CFG_405_UART_ERRATA_59, then UART divisor is 31. @@ -128,16 +191,33 @@ #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CFG_BASE_BAUD 691200 +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + /*----------------------------------------------------------------------- * I2C stuff *----------------------------------------------------------------------- */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ -#if defined(CONFIG_CMD_EEPROM) +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ #endif @@ -177,9 +257,21 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 */ +#define CFG_SDRAM_BASE 0x00000000 #define CFG_SRAM_BASE 0xFFF00000 #define CFG_FLASH_BASE 0xFFF80000 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization @@ -195,7 +287,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ @@ -215,6 +307,14 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Init Memory Controller: @@ -316,4 +416,17 @@ #define FPGA_REG1_OFFB_FLASH 0x02 /* Off board flash */ #define FPGA_REG1_SRAM_BOOT 0x01 /* SRAM at 0xFFF80000 not Flash */ +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h index 6f0d4b0f8..ae75539c3 100644 --- a/include/configs/c2mon.h +++ b/include/configs/c2mon.h @@ -50,13 +50,13 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -68,15 +68,7 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -85,18 +77,15 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Miscellaneous configurable options @@ -109,7 +98,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -185,7 +174,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/canmb.h b/include/configs/canmb.h index f097e2c2f..2c160a448 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -31,16 +31,19 @@ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ -#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ +#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_BOARD_EARLY_INIT_R +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CONFIG_BOARD_EARLY_INIT_R /* * Serial console configuration @@ -49,30 +52,21 @@ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * MUST be low boot - HIGHBOOT is not supported anymore @@ -90,7 +84,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -117,7 +111,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ /* * Flash configuration, expect one 16 Megabyte Bank at most @@ -187,7 +181,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -205,11 +199,6 @@ #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Various low-level settings */ diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index c801f037e..6997c7a6f 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -39,7 +39,7 @@ #define BOARD_LATE_INIT 1 #define CONFIG_BAUDRATE 38400 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* * Size of malloc() pool @@ -61,21 +61,10 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 #define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2 @@ -86,7 +75,7 @@ #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400" #define CONFIG_CMDLINE_TAG -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -104,7 +93,7 @@ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #endif #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ @@ -137,21 +126,21 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ #define CFG_DRAM_BASE 0xa0000000 #define CFG_DRAM_SIZE 0x04000000 @@ -210,7 +199,7 @@ * FLASH and environment organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ /* timeout values are in ticks */ #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h index ae40b358e..5947c2a31 100644 --- a/include/configs/cm4008.h +++ b/include/configs/cm4008.h @@ -58,23 +58,10 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_ENV - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#undef CONFIG_COMMANDS +#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV)) #define CONFIG_BOOTDELAY 0 #define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200" diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h index c1dd33d1d..e62fc0633 100644 --- a/include/configs/cm41xx.h +++ b/include/configs/cm41xx.h @@ -58,23 +58,10 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_ENV - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#undef CONFIG_COMMANDS +#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV)) #define CONFIG_BOOTDELAY 0 #define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200" diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index bce5fcd82..572a70f12 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -50,7 +50,7 @@ #define MC_ASR_VAL 0x00000000 #define MC_AASR_VAL 0x00000000 #define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ +#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ @@ -104,51 +104,42 @@ #define CFG_I2C_EEPROM_ADDR 0x50 #define CFG_I2C_EEPROM_ADDR_LEN 1 #define CFG_I2C_EEPROM_ADDR_OVERFLOW -#else -#define CONFIG_TIMESTAMP #endif /* still about 20 kB free with this defined */ #define CFG_LONGHELP #define CONFIG_BOOTDELAY 1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC - -#if defined(CONFIG_HARD_I2C) - #define CONFIG_CMD_DATE - #define CONFIG_CMD_EEPROM - #define CONFIG_CMD_I2C +#ifdef CONFIG_HARD_I2C +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) & \ + ~(CFG_CMD_FPGA | CFG_CMD_MISC) ) +#else +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) & \ + ~(CFG_CMD_FPGA | CFG_CMD_MISC) ) +#define CONFIG_TIMESTAMP #endif - - #define CFG_LONGHELP +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */ +#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */ #define CFG_MEMTEST_START PHYS_SDRAM #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 @@ -186,6 +177,25 @@ #define CFG_MAXARGS 32 /* max number of command args */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif /* __ASSEMBLY__ */ + #define CFG_HZ 1000 #define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ /* AT91C_TC_TIMER_DIV1_CLOCK */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index ac2b7a1e7..e45991929 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -24,7 +24,7 @@ * File: cmi_mpc5xx.h * * Discription: Config header file for cmi - * board using an MPC5xx CPU + * board using an MPC5xx CPU * */ @@ -36,7 +36,7 @@ */ #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_CMI 1 /* Using the customized cmi board */ +#define CONFIG_CMI 1 /* Using the customized cmi board */ /* Serial Console Configuration */ #define CONFIG_5xx_CONS_SCI1 @@ -44,46 +44,24 @@ #define CONFIG_BAUDRATE 57600 +#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \ + CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV | \ + CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN | \ + CFG_CMD_IMI) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_NET /* disabeled - causes compile errors */ - -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_ENV -#define CONFIG_CMD_RUN -#define CONFIG_CMD_IMI - +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ #define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */ -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ +#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ #define CONFIG_STATUS_LED 1 /* Enable status led */ @@ -95,7 +73,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -121,30 +99,30 @@ /* * Internal Memory Mapped (This is not the IMMR content) */ -#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */ +#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */ /* * Definitions for initial stack pointer and data area */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */ +#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ +#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */ #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ +#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ /* * Start addresses for the final memory configuration * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ +#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ #define CFG_FLASH_BASE 0x02000000 /* External flash */ #define PLD_BASE 0x03000000 /* PLD */ #define ANYBUS_BASE 0x03010000 /* Anybus Module */ #define CFG_RESET_ADRESS 0x01000000 /* Adress which causes reset */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */ + /* This adress is given to the linker with -Ttext to */ + /* locate the text section at this adress. */ #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ #define CFG_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */ @@ -163,17 +141,16 @@ */ #define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ #define CFG_FLASH_PROTECTION 1 /* Physically section protection on */ #define CFG_ENV_IS_IN_FLASH 1 #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ -#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ +#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ +#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ #endif /*----------------------------------------------------------------------- @@ -219,7 +196,7 @@ *----------------------------------------------------------------------- * Data show cycle */ -#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ +#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register @@ -227,7 +204,7 @@ * Set all bits to 40 Mhz * */ -#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ +#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ #define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) @@ -236,12 +213,12 @@ *----------------------------------------------------------------------- * */ -#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ +#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ +#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ /*----------------------------------------------------------------------- * USIU - Memory Controller Register @@ -256,7 +233,7 @@ #define CFG_OR2_PRELIM (OR_ADDR_MK_FF) #define CFG_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8) #define CFG_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \ - OR_ACS_10 | OR_ETHR | OR_CSNT) + OR_ACS_10 | OR_ETHR | OR_CSNT) #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 649b053c2..9033fa88e 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -65,10 +65,8 @@ * Enable use of Ethernet * --- */ -#define CONFIG_MCFFEC -/* Enable Dma Timer */ -#define CONFIG_MCFTMR +#define FEC_ENET /* --- * Define baudrate for UART1 (console output, tftp, ...) @@ -78,8 +76,6 @@ * --- */ -#define CONFIG_MCFUART -#define CFG_UART_PORT (0) #define CONFIG_BAUDRATE 19200 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } @@ -101,7 +97,7 @@ * bootloader residing in flash ('chainloading'); if you want to use * chainloading or want to compile a u-boot binary that can be loaded into * RAM via BDM set - * "#if 0" to "#if 1" + * "#if 0" to "#if 1" * You will need a first stage bootloader then, e. g. colilo or a working BDM * cable (Background Debug Mode) * @@ -134,48 +130,16 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif - -/* - * BOOTP options +/* --- + * Define which commmands should be available at u-boot command prompt + * --- */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | CFG_CMD_PING & ~(CFG_CMD_LOADS | \ +CFG_CMD_LOADB) | CFG_CMD_MII) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING - -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_MII - -#ifdef CONFIG_MCFFEC -# define CONFIG_NET_MULTI 1 -# define CONFIG_MII 1 -# define CONFIG_MII_INIT 1 -# define CFG_DISCOVER_PHY -# define CFG_RX_ETH_BUFFER 8 -# define CFG_FAULT_ECHO_LINK_DOWN - -# define CFG_FEC0_PINMUX 0 -# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CFG_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CFG_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CFG_FAULT_ECHO_LINK_DOWN -# define CFG_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CFG_DISCOVER_PHY */ -#endif +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* *----------------------------------------------------------------------------- @@ -220,7 +184,7 @@ from which user programs will be started */ #define CFG_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h index 84d50c71d..aea2e6436 100644 --- a/include/configs/cogent_mpc8260.h +++ b/include/configs/cogent_mpc8260.h @@ -71,7 +71,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ @@ -87,25 +88,10 @@ #define CONFIG_BAUDRATE 9600 #endif +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_KGDB - -#undef CONFIG_CMD_NET - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #ifdef DEBUG #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -116,7 +102,7 @@ #define CONFIG_BOOTARGS "root=/dev/ram rw" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -138,7 +124,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -270,7 +256,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ #endif diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h index ce38af1dd..80962d35f 100644 --- a/include/configs/cogent_mpc8xx.h +++ b/include/configs/cogent_mpc8xx.h @@ -59,25 +59,10 @@ #define CFG_I2C_SLAVE 0x7F -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_I2C - -#undef CONFIG_CMD_NET +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -88,7 +73,7 @@ #define CONFIG_BOOTARGS "root=/dev/ram rw" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #define CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -103,7 +88,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -215,7 +200,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index fffd1fe1f..f9586fbcb 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -50,7 +50,10 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -71,7 +74,6 @@ #define CONFIG_PCI_PNP 1 #endif #define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_PCI_MEM_BUS 0x40000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -90,6 +92,12 @@ #define CONFIG_NS8382X 1 #endif +#define ADD_PCI_CMD CFG_CMD_PCI + +#else /* MPC5100 */ + +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + #endif /* Partitions */ @@ -99,35 +107,28 @@ /* USB */ #if 0 #define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 #endif /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_IDE | \ + CFG_CMD_I2C | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_DATE | \ + ADD_PCI_CMD ) - -/* - * Command line configuration. - */ -#include - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_I2C -#define CONFIG_CMD_BSP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_DATE +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 @@ -178,7 +179,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #endif /* * I2C configuration @@ -276,7 +277,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -294,11 +295,6 @@ #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Various low-level settings */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index eb93a8f08..776e1d2b7 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -61,21 +61,10 @@ #define CONFIG_BAUDRATE 115200 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200" diff --git a/include/configs/csb226.h b/include/configs/csb226.h index a807d0084..f04102e95 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -37,7 +37,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_CSB226 1 /* on a CSB226 board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -57,34 +57,10 @@ #define CONFIG_BAUDRATE 19200 #undef CONFIG_MISC_INIT_R /* not used yet */ +#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_IMI -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_ENV -#define CONFIG_CMD_RUN -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_CACHE - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0" @@ -97,7 +73,7 @@ #define CONFIG_CMDLINE_TAG 1 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 15bf1772b..27d64c1e4 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -33,7 +33,7 @@ * (easy to change) */ -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ @@ -73,32 +73,30 @@ #endif /* - * BOOTP options + * BOOTP/DHCP protocol configuration + * */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS2 - - +#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_BOOTFILESIZE ) /* - * Command line configuration. + * U-Boot Monitor Command Line Functions Configuration + * */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PCI -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_PCI | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Serial download configuration @@ -111,7 +109,7 @@ * KGDB Configuration * */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -127,7 +125,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -182,7 +180,7 @@ */ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ +#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ /* 32usec min. for LXT971A */ #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ @@ -289,6 +287,14 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/* + * Cache configuration + * + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 + /* * Miscellaneous board specific definitions * diff --git a/include/configs/csb472.h b/include/configs/csb472.h index b06c0a269..09d52ded9 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -33,7 +33,7 @@ * (easy to change) */ -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ @@ -73,31 +73,30 @@ #endif /* - * BOOTP options + * BOOTP/DHCP protocol configuration + * */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS2 - - +#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_DNS2 | \ + CONFIG_BOOTP_BOOTFILESIZE ) /* - * Command line configuration. + * U-Boot Monitor Command Line Functions Configuration + * */ -#include +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF | \ + CFG_CMD_IRQ | \ + CFG_CMD_I2C | \ + CFG_CMD_PCI | \ + CFG_CMD_DATE | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP ) -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PCI -#define CONFIG_CMD_DATE -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Serial download configuration @@ -110,7 +109,7 @@ * KGDB Configuration * */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -126,7 +125,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -181,7 +180,7 @@ */ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ +#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ /* 32usec min. for LXT971A */ #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ @@ -288,6 +287,14 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/* + * Cache configuration + * + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ + /* have only 8kB, 16kB is save here */ +#define CFG_CACHELINE_SIZE 32 + /* * Miscellaneous board specific definitions * diff --git a/include/configs/csb637.h b/include/configs/csb637.h index 735a211e0..071d5b7f3 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -51,7 +51,7 @@ #define MC_ASR_VAL 0x00000000 #define MC_AASR_VAL 0x00000000 #define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ @@ -99,26 +99,20 @@ #define CONFIG_BOOTDELAY 3 /* #define CONFIG_ENV_OVERWRITE 1 */ +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING ) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_IMI | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC | \ + CFG_CMD_LOADS )) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_PING - -#ifdef NAND_SUPPORT_HAS_BEEN_FIXED /* NAND support is broken / unimplemented */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 @@ -134,7 +128,6 @@ #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ -#include /* needed for port definitions */ #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) @@ -150,8 +143,6 @@ #define NAND_CTL_CLRCLE(nandptr) #define NAND_CTL_SETCLE(nandptr) -#endif /* NAND_SUPPORT_HAS_BEEN_FIXED */ - #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 #define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */ @@ -167,8 +158,8 @@ #undef CONFIG_HAS_DATAFLASH #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) -#define CFG_MAX_DATAFLASH_BANKS 0 -#define CFG_MAX_DATAFLASH_PAGES 16384 +#define CFG_MAX_DATAFLASH_BANKS 0 +#define CFG_MAX_DATAFLASH_PAGES 16384 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */ #define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */ @@ -206,16 +197,35 @@ #define CFG_LOAD_ADDR 0x21000000 /* default load address */ -#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 } +#define CFG_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600 } #define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif + #define CFG_HZ 1000 #define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */ - /* AT91C_TC_TIMER_DIV1_CLOCK */ + /* AT91C_TC_TIMER_DIV1_CLOCK */ #define CONFIG_STACKSIZE (32*1024) /* regular stack */ diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 0e10396df..4cc508529 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -30,21 +30,21 @@ #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_DBAU1X00 1 -#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_AU1X00 1 /* alchemy series cpu */ #ifdef CONFIG_DBAU1000 /* Also known as Merlot */ -#define CONFIG_SOC_AU1000 1 +#define CONFIG_AU1000 1 #else #ifdef CONFIG_DBAU1100 -#define CONFIG_SOC_AU1100 1 +#define CONFIG_AU1100 1 #else #ifdef CONFIG_DBAU1500 -#define CONFIG_SOC_AU1500 1 +#define CONFIG_AU1500 1 #else #ifdef CONFIG_DBAU1550 /* Cabernet */ -#define CONFIG_SOC_AU1550 1 +#define CONFIG_AU1550 1 #else #error "No valid board set" #endif @@ -75,57 +75,21 @@ #ifdef CONFIG_DBAU1550 /* Boot from flash by default, revert to bootp */ #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \ + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \ + CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \ + CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C)) #else /* CONFIG_DBAU1550 */ #define CONFIG_BOOTCOMMAND "bootp;bootm" + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \ + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \ + CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \ + CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG)) #endif /* CONFIG_DBAU1550 */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_BEDBUG -#undef CONFIG_CMD_ELF -#undef CONFIG_CMD_ENV -#undef CONFIG_CMD_FAT -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_RUN - - -#ifdef CONFIG_DBAU1550 - -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_NET - -#undef CONFIG_CMD_I2C -#undef CONFIG_CMD_IDE -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_PCMCIA - -#else - -#define CONFIG_CMD_IDE -#define CONFIG_CMD_DHCP - -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS - -#endif - +#include /* * Miscellaneous configurable options @@ -148,9 +112,7 @@ #error "Invalid CPU frequency - must be multiple of 12!" #endif -#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000) - -#define CFG_HZ 1000 +#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/debris.h b/include/configs/debris.h index 7667e5e60..8ff963f55 100644 --- a/include/configs/debris.h +++ b/include/configs/debris.h @@ -122,35 +122,23 @@ #define CONFIG_BAUDRATE 9600 #define CONFIG_DRAM_SPEED 100 /* MHz */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_KGBD -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGBD | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_SAVES | \ + CFG_CMD_SDRAM) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* @@ -447,7 +435,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/delta.h b/include/configs/delta.h index 14fde1a95..91284fdac 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -87,51 +87,22 @@ #define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - +/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */ #ifdef TURN_ON_ETHERNET - -#define CONFIG_CMD_PING - +# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) #else - -#define CONFIG_CMD_ENV -#define CONFIG_CMD_NAND -#define CONFIG_CMD_I2C - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS - +# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_ENV \ + | CFG_CMD_NAND \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_NET \ + | CFG_CMD_FLASH \ + | CFG_CMD_IMLS)) #endif -/* USB */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 -#include /* for OHCI_REGS_BASE */ - -#undef CFG_USB_OHCI_BOARD_INIT -#define CFG_USB_OHCI_CPU_INIT 1 -#define CFG_USB_OHCI_REGS_BASE OHCI_REGS_BASE -#define CFG_USB_OHCI_SLOT_NAME "delta" -#define CFG_USB_OHCI_MAX_ROOT_PORTS 3 - -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY -1 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b @@ -143,7 +114,7 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_TIMESTAMP -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -217,6 +188,7 @@ /* * NAND Flash */ +/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ #undef CFG_NAND_LEGACY #define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index e7873e95f..9ac2856f6 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -66,24 +66,13 @@ #define CONFIG_BAUDRATE 115200 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" #define CONFIG_ETHADDR 02:80:ad:20:31:b8 #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_IPADDR 172.22.2.23 @@ -91,7 +80,7 @@ #define CONFIG_BOOTFILE "dnp1110" #define CONFIG_BOOTCOMMAND "tftp; bootm" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h index f8e2c885b..a014c7c07 100644 --- a/include/configs/eXalion.h +++ b/include/configs/eXalion.h @@ -58,27 +58,17 @@ /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_FLASH | \ + CFG_CMD_SDRAM | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_ENV | \ + CFG_CMD_PCI ) - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_ENV -#define CONFIG_CMD_PCI +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /*----------------------------------------------------------------------- @@ -408,7 +398,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ebony.h b/include/configs/ebony.h index df444d8e9..a26af6952 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -32,17 +32,11 @@ *----------------------------------------------------------------------*/ #define CONFIG_EBONY 1 /* Board is ebony */ #define CONFIG_440GP 1 /* Specifc GP support */ -#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -/* - * Include common defines/options for all AMCC eval boards - */ -#define CONFIG_HOSTNAME ebony -#include "amcc-common.h" - /* * Define here the location of the environment variables (FLASH or NVRAM). * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only @@ -60,6 +54,7 @@ *----------------------------------------------------------------------*/ #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ @@ -78,11 +73,18 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} /*----------------------------------------------------------------------- * NVRAM/RTC @@ -119,7 +121,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ @@ -131,46 +133,120 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ -#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS -/* - * Default environment variables - */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_POWERPC \ - CONFIG_AMCC_DEF_ENV_PPC_OLD \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "netdev=eth0\0" \ + "hostname=ebony\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/ebony/uImage\0" \ "kernel_addr=ff800000\0" \ "ramdisk_addr=ff810000\0" \ + "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ "" +#define CONFIG_BOOTCOMMAND "run flash_self" +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 8 /* PHY address */ -#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ /* - * Commands additional to the ones defined in amcc-common.h + * Miscellaneous configurable options */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ /*----------------------------------------------------------------------- * PCI stuff @@ -183,9 +259,37 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h index 54330821b..bdda6292e 100644 --- a/include/configs/ep7312.h +++ b/include/configs/ep7312.h @@ -34,7 +34,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_EP7312 1 /* on an EP7312 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -62,34 +62,23 @@ #define CONFIG_BAUDRATE 9600 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_JFFS2 - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" -#define CONFIG_ETHADDR 08:00:3e:21:c7:f7 +#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" +#define CONFIG_ETHADDR 08:00:3e:21:c7:f7 /*#define CONFIG_NETMASK 255.255.0.0 */ /*#define CONFIG_IPADDR 172.22.2.128 */ /*#define CONFIG_SERVERIP 172.22.2.126 */ /*#define CONFIG_BOOTFILE "impa7" */ #define CONFIG_BOOTCOMMAND "bootp;bootm" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index 8a220b681..04147a55d 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -31,6 +31,8 @@ #define CONFIG_EP8248 /* Embedded Planet EP8248 board */ +#undef DEBUG + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ @@ -58,8 +60,8 @@ * SCC, 1-3 for FCC) * * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. + * must be defined elsewhere (as for the console), or CFG_CMD_NET must + * be removed from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ @@ -121,34 +123,23 @@ #define CONFIG_BAUDRATE 38400 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_ECHO \ + | CFG_CMD_I2C \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -166,7 +157,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -192,20 +183,20 @@ #define CFG_DIRECT_FLASH_TFTP -#if defined(CONFIG_CMD_JFFS2) +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS #define CFG_JFFS2_FIRST_SECTOR 0 #define CFG_JFFS2_LAST_SECTOR 62 #define CFG_JFFS2_SORT_FRAGMENTS #define CFG_JFFS_CUSTOM_PART -#endif +#endif /* CFG_CMD_JFFS2 */ -#if defined(CONFIG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) #define CONFIG_HARD_I2C 1 /* To enable I2C support */ #define CFG_I2C_SPEED 100000 /* I2C speed */ #define CFG_I2C_SLAVE 0x7F /* I2C slave address */ -#endif +#endif /* CFG_CMD_I2C */ #define CFG_MONITOR_BASE TEXT_BASE #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) @@ -234,13 +225,13 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ @@ -249,7 +240,7 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index 0ce6b80b9..686251930 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -28,17 +28,17 @@ * board/config.h - configuration options, board specific * * "EP8260 H, V.1.1" - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 16M Flash (4 x AM29DL323DB90WDI) - * - 128k NVRAM with RTC + * - 64M 60x Bus SDRAM + * - 32M Local Bus SDRAM + * - 16M Flash (4 x AM29DL323DB90WDI) + * - 128k NVRAM with RTC * * "EP8260 H2, V.1.3" (CFG_EP8260_H2) - * - 300MHz/133MHz/66MHz - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 32M Flash - * - 128k NVRAM with RTC + * - 300MHz/133MHz/66MHz + * - 64M 60x Bus SDRAM + * - 32M Local Bus SDRAM + * - 32M Flash + * - 128k NVRAM with RTC */ #ifndef __CONFIG_H @@ -183,7 +183,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ @@ -290,42 +291,39 @@ #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " - +/* What U-Boot subsytems do you want enabled? */ /* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +*/ +#define CONFIG_COMMANDS ( CFG_CMD_ALL & \ + ~( CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_DCR | \ + CFG_CMD_DHCP | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_DTT | \ + CFG_CMD_EEPROM | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_KGDB | \ + CFG_CMD_MII | \ + CFG_CMD_MMC | \ + CFG_CMD_NAND | \ + CFG_CMD_PCI | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_REISER | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_UNIVERSE| \ + CFG_CMD_USB | \ + CFG_CMD_VFD | \ + CFG_CMD_XIMG ) ) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_DCR -#undef CONFIG_CMD_XIMG - /* Where do the internal registers live? */ #define CFG_IMMR 0xF0000000 #define CFG_DEFAULT_IMMR 0x00010000 @@ -344,10 +342,13 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -408,7 +409,7 @@ CFG_SBC_HRCW_IMMR |\ HRCW_APPC10 |\ HRCW_CS10PC01 |\ - CFG_SBC_MODCK_H |\ + CFG_SBC_MODCK_H |\ CFG_SBC_HRCW_BOOT_FLAGS) #else #define CFG_HRCW_MASTER 0x10400245 @@ -495,7 +496,7 @@ */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index 1571477d0..88c2c7437 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -72,23 +72,12 @@ #define CONFIG_BAUDRATE 19200 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PING - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_ETHADDR 00:40:95:36:35:33 #define CONFIG_NETMASK 255.255.255.0 @@ -98,9 +87,9 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTCOMMAND "tftp 100000 uImage" -/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */ +/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h new file mode 100644 index 000000000..5eda6732c --- /dev/null +++ b/include/configs/ezkit533.h @@ -0,0 +1,188 @@ +#ifndef __CONFIG_EZKIT533_H__ +#define __CONFIG_EZKIT533_H__ + +#define CFG_LONGHELP 1 +#define CONFIG_BAUDRATE 57600 +#define CONFIG_STAMP 1 +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20310300 +#if 0 +#define CONFIG_MII +#define CFG_DISCOVER_PHY +#endif + +#define CONFIG_RTC_BF533 1 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 27000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 22 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 + +#define CONFIG_LOADS_ECHO 1 + + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE) +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off" + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE 0x02000000 +#define CFG_FLASH_BASE 0x20000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_FLASH0_BASE 0x20000000 +#define CFG_FLASH1_BASE 0x20200000 +#define CFG_FLASH2_BASE 0x20280000 +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#define POLL_MODE 1 +#define FLASH_TOT_SECT 40 +#define FLASH_SIZE 0x220000 +#define CFG_FLASH_SIZE 0x220000 + +/* + * Initialize PSD4256 registers for using I2C + */ +#define CONFIG_MISC_INIT_R + +/* + * I2C settings + * By default PF1 is used as SDA and PF0 as SCL on the Stamp board + */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF0 +#define PF_SDA PF1 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + + +#define __ADSPLPBLACKFIN__ 1 +#define __ADSPBF533__ 1 + +/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 + +#define CONFIG_VDSP 1 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h index 3b1b4ab95..b68a2dca0 100644 --- a/include/configs/gcplus.h +++ b/include/configs/gcplus.h @@ -29,6 +29,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#undef DEBUG + /* * The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000. * We don't actually init RAM in this case since we're using U-Boot as @@ -77,30 +79,18 @@ #define CONFIG_BAUDRATE 38400 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp" #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" #define CFG_AUTOLOAD "n" /* No autoload */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/gth2.h b/include/configs/gth2.h index 7f7190bcd..a49ed3bae 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -30,9 +30,9 @@ #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_GTH2 1 -#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_AU1X00 1 /* alchemy series cpu */ -#define CONFIG_SOC_AU1000 1 +#define CONFIG_AU1000 1 #define CONFIG_MISC_INIT_R 1 @@ -54,9 +54,8 @@ /* Only interrupt boot if space is pressed */ /* If a long serial cable is connected but */ /* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press space to abort autoboot in %d second\n", bootdelay +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n" #define CONFIG_AUTOBOOT_DELAY_STR "d" #define CONFIG_AUTOBOOT_STOP_STR " " @@ -72,37 +71,12 @@ /* Boot from Compact flash partition 2 as default */ #define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm" +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \ + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \ + CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \ + CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT )) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_IDE -#define CONFIG_CMD_DHCP - -#undef CONFIG_CMD_ENV -#undef CONFIG_CMD_FAT -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_ELF -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_BEDBUG -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_AUTOSCRIPT - +#include /* * Miscellaneous configurable options @@ -119,9 +93,7 @@ #define CFG_MHZ 500 -#define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000) - -#define CFG_HZ 1000 +#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index d9187825e..4f83b1945 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -51,6 +51,7 @@ #define __CONFIG_H /* Enable debug prints */ +#undef DEBUG /* General debug */ #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */ /* What is the oscillator's (UX2) frequency in Hz? */ @@ -193,7 +194,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC @@ -279,22 +281,18 @@ * To stop use: " " */ #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Autobooting in %d seconds, press \" \" to stop\n", bootdelay +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n" #define CONFIG_AUTOBOOT_STOP_STR " " #undef CONFIG_AUTOBOOT_DELAY_STR #define DEBUG_BOOTKEYS 0 -/* - * BOOTP options +/* Add support for a few extra bootp options like: + * - File size + * - DNS */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE | \ + CONFIG_BOOTP_DNS) /* undef this to save memory */ #define CFG_LONGHELP @@ -302,21 +300,14 @@ /* Monitor Command Prompt */ #define CFG_PROMPT "=> " - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII - -#undef CONFIG_CMD_KGDB - +/* What U-Boot subsytems do you want enabled? */ +#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_ELF | \ + CFG_CMD_ASKENV | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_MII) /* Where do the internal registers live? */ #define CFG_IMMR 0xf0000000 @@ -340,10 +331,13 @@ #define CONFIG_GW8260 1 /* on an GW8260 Board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -479,7 +473,7 @@ */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/hermes.h b/include/configs/hermes.h index 48b23bdcd..91117bab7 100644 --- a/include/configs/hermes.h +++ b/include/configs/hermes.h @@ -54,9 +54,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -64,28 +64,23 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_COMMANDS CONFIG_CMD_DFL -/* - * Command line configuration. - */ -#include +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/*----------------------------------------------------------------------*/ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +/*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -105,7 +100,7 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ +#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) @@ -162,7 +157,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -227,7 +222,7 @@ /* +0x0282 => 0x03800000 */ #define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000) diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index ad7cf7686..cfaf15322 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -38,9 +38,12 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_BOARD_EARLY_INIT_R +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CONFIG_BOARD_EARLY_INIT_R /* * Serial console configuration @@ -52,31 +55,22 @@ /* Partitions */ #define CONFIG_DOS_PARTITION - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ @@ -90,7 +84,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -116,7 +110,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ /* * I2C configuration @@ -216,7 +210,6 @@ */ #define CONFIG_MPC5xxx_FEC 1 #define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 /* MII PHY management */ /* * GPIO configuration @@ -228,7 +221,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -237,11 +230,6 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* Enable an alternate, more extensive memory test */ #define CFG_ALT_MEMTEST @@ -253,7 +241,8 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ /* - * Enable loopw command. + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) */ #define CONFIG_LOOPW @@ -338,7 +327,6 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 #define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_PCI_MEM_BUS 0x40000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 264192f26..8cad98dbd 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -69,7 +69,8 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ @@ -173,45 +174,32 @@ #define CONFIG_LAST_STAGE_INIT -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ + CFG_CMD_BEDBUG | \ + CFG_CMD_BMP | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DOC | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FDC | \ + CFG_CMD_FDOS | \ + CFG_CMD_FPGA | \ + CFG_CMD_HWFLOW | \ + CFG_CMD_IDE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NAND | \ + CFG_CMD_MMC | \ + CFG_CMD_PCMCIA | \ + CFG_CMD_PCI | \ + CFG_CMD_USB | \ + CFG_CMD_REISER | \ + CFG_CMD_SCSI | \ + CFG_CMD_SPI | \ + CFG_CMD_UNIVERSE| \ + CFG_CMD_VFD | \ + CFG_CMD_XIMG ) ) - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_CDP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_KGDB -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_PORTIO -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_XIMG +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #ifdef DEBUG #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -224,13 +212,13 @@ */ #define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ - "press to stop\n", bootdelay + "press to stop\n" #define CONFIG_AUTOBOOT_STOP_STR " " #undef CONFIG_AUTOBOOT_DELAY_STR #define DEBUG_BOOTKEYS 0 #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -259,7 +247,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -407,13 +395,12 @@ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ #endif diff --git a/include/configs/impa7.h b/include/configs/impa7.h index e9704fc9a..8b841ff54 100644 --- a/include/configs/impa7.h +++ b/include/configs/impa7.h @@ -34,7 +34,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_IMPA7 1 /* on an impA7 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */ +#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -61,26 +61,15 @@ #define CONFIG_BAUDRATE 9600 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_JFFS2 - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" +#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" /*#define CONFIG_ETHADDR 08:00:3e:26:0a:5a */ /*#define CONFIG_NETMASK 255.255.0.0 */ /*#define CONFIG_IPADDR 172.22.2.128 */ @@ -88,7 +77,7 @@ /*#define CONFIG_BOOTFILE "impa7" */ #define CONFIG_BOOTCOMMAND "bootp;bootm" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 2e4ee66cf..1c6216be8 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -48,7 +48,7 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -81,29 +81,15 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_SNTP ) +#include /* * Miscellaneous configurable options @@ -118,9 +104,7 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_MIPS_TIMER_FREQ (incaip_get_cpuclk() / 2) - -#define CFG_HZ 1000 +#define CFG_HZ (incaip_get_cpuclk() / 2) #define CFG_SDRAM_BASE 0x80000000 diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 6ec92c38c..773d5d2c1 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -40,7 +40,10 @@ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -57,7 +60,6 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 #define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_PCI_MEM_BUS 0x40000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -74,30 +76,21 @@ #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP | \ + CFG_CMD_USB ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ @@ -111,7 +104,7 @@ #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -145,7 +138,7 @@ "cp.l 100000 f0000b28 1\0" \ "ideargs=setenv bootargs root=/dev/hda1 rw\0" \ "ide_boot=ext2load ide 0:1 200000 uImage;" \ - "run ideargs addip addcons enable_disp;bootm\0" \ + "run ideargs addip addcons enable_disp;bootm" \ "brightness=255\0" \ "" @@ -154,29 +147,29 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ /* * Flash configuration */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 -#define CFG_FLASH_BASE 0xffe00000 -#define CFG_FLASH_SIZE 0x00200000 -#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } -#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_BASE 0xFFE00000 + +#define CFG_FLASH_SIZE 0x00200000 /* 2 MByte */ +#define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */ + +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) /* second sector */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ /* * Environment settings */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) #define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SECT_SIZE 0x2000 #define CONFIG_ENV_OVERWRITE 1 -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ /* * Memory map @@ -185,14 +178,7 @@ #define CFG_SDRAM_BASE 0x00000000 #define CFG_DEFAULT_MBAR 0x80000000 -/* - * SDRAM controller configuration - */ -#undef CONFIG_SDR_MT48LC16M16A2 -#undef CONFIG_DDR_MT46V16M16 -#undef CONFIG_DDR_MT46V32M16 -#undef CONFIG_DDR_HYB25D512160BF -#define CONFIG_DDR_K4H511638C +#define CONFIG_MPC5200_DDR /* Use ON-Chip SRAM until RAM will be available */ #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM @@ -213,7 +199,7 @@ # define CFG_RAMBOOT 1 #endif -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ @@ -253,7 +239,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -262,11 +248,6 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* Enable an alternate, more extensive memory test */ #define CFG_ALT_MEMTEST @@ -278,7 +259,8 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ /* - * Enable loopw command. + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) */ #define CONFIG_LOOPW diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 2b6505267..3cb9ebc45 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -34,7 +34,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -54,34 +54,10 @@ #define CONFIG_BAUDRATE 19200 #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMI -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_RUN - +#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE) +/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ @@ -136,11 +112,11 @@ /* * I2C bus */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xfe +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xfe -#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_IS_IN_EEPROM 1 #define CFG_ENV_OFFSET 0x00 /* environment starts here */ #define CFG_ENV_SIZE 1024 /* 1 KiB */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 1452bf2c4..2f6e3993b 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -66,26 +66,15 @@ #define CFG_SERIAL0 0x16000000 #define CFG_SERIAL1 0x17000000 +/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */ /*#define CONFIG_NET_MULTI */ +/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ + +#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_IMI -#define CONFIG_CMD_BDI -#define CONFIG_CMD_MEMORY - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 347fa0201..4189f9c99 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -70,28 +70,17 @@ #define CFG_SERIAL0 0x16000000 #define CFG_SERIAL1 0x17000000 - /* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_PCI) +*/ +#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \ + CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \ + ) +/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ -/* - * Command line configuration. - */ -#define CONFIG_CMD_BDI -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #if 0 #define CONFIG_BOOTDELAY 2 @@ -140,7 +129,7 @@ SIB at Block62 End Block62 address 0x24f80000 */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ /*----------------------------------------------------------------------- * FLASH and environment organization @@ -156,9 +145,9 @@ SIB at Block62 End Block62 address 0x24f80000 */ #define CFG_FLASH_BASE 0x24000000 -#define CFG_MAX_FLASH_SECT 64 +#define CFG_MAX_FLASH_SECT 64 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ @@ -168,7 +157,7 @@ SIB at Block62 End Block62 address 0x24f80000 /* * Move up the U-Boot & monitor area if more flash is fitted. * If this U-Boot is to be run on Integrators with varying flash sizes, - * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG + * drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG * register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE * - CFG_MONITOR_BASE is set to indicate that the environment is not * embedded in the boot monitor(s) area diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index b7c43fedf..9f9fdb25e 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -53,28 +53,14 @@ #define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ELF -#define CONFIG_CMD_PCI - +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_PCI) #define CONFIG_PCI #define CONFIG_NET_MULTI #define CONFIG_EEPRO100 +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +/* These are u-boot generic parameters */ +#include #define CONFIG_BOOTDELAY 3 /*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/ @@ -85,7 +71,7 @@ #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" #define CONFIG_CMDLINE_TAG -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -165,7 +151,7 @@ */ #define CFG_SDR_CONFIG 0xd #define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDRAM_REFRESH_CNT 0x81a /* * GPIO settings @@ -178,7 +164,7 @@ * FLASH and environment organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -193,7 +179,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index 05dc841e3..af4ecf621 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -75,27 +75,16 @@ #define CONFIG_BAUDRATE 115200 #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_ELF | \ + CFG_CMD_NET | \ + CFG_CMD_MII | \ + CFG_CMD_PING) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +/* These are u-boot generic parameters */ +#include #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -139,7 +128,7 @@ * Default configuration (environment varibles...) *----------------------------------------------------------------------*/ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -168,7 +157,7 @@ "update=protect off 50000000 5003ffff;era 50000000 5003ffff;" \ "cp.b 100000 50000000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ + "upd=run load;run update\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" @@ -201,13 +190,13 @@ */ #define CFG_SDR_CONFIG 0x18 #define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDRAM_REFRESH_CNT 0x81a /* * FLASH and environment organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -225,7 +214,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 7dcce836e..6590f6f5f 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -54,13 +54,10 @@ #define CFG_LONGHELP -#ifndef roundup -#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) -#endif /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (roundup(CFG_ENV_SIZE,4096) + 128*1024) +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_BAUDRATE 115200 @@ -81,29 +78,17 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_I2C | \ + CFG_CMD_PING | \ + CFG_CMD_DHCP ) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC)) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP - -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h index 569800aa2..61cf70576 100644 --- a/include/configs/kvme080.h +++ b/include/configs/kvme080.h @@ -60,45 +60,33 @@ #undef CONFIG_WATCHDOG -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_RTC_DS164x - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP) #define CONFIG_NETCONSOLE +#include + #define CFG_LONGHELP #define CFG_PROMPT "=> " #define CFG_CBSIZE 256 @@ -190,7 +178,7 @@ #define CONFIG_SYS_CLK_FREQ 33333333 #define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) +#if CONFIG_COMMANDS & CFG_CMD_KGDB # define CFG_CACHELINE_SHIFT 5 #endif diff --git a/include/configs/lart.h b/include/configs/lart.h index 4570398cd..a00640bf8 100644 --- a/include/configs/lart.h +++ b/include/configs/lart.h @@ -59,24 +59,13 @@ #define CONFIG_BAUDRATE 9600 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" #define CONFIG_ETHADDR 08:00:3e:26:0a:5b #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_IPADDR 172.22.2.131 @@ -84,7 +73,7 @@ #define CONFIG_BOOTFILE "elinos-lart" #define CONFIG_BOOTCOMMAND "tftp; bootm" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/logodl.h b/include/configs/logodl.h index 047b4a4f7..715ed74ea 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -34,7 +34,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_GEALOG 1 /* on a Logotronic GEALOG SG board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -54,26 +54,10 @@ #define CONFIG_BAUDRATE 19200 #undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_RUN - +#define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO) +/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h index 04148898e..d7d0460ef 100644 --- a/include/configs/lpd7a400.h +++ b/include/configs/lpd7a400.h @@ -55,32 +55,19 @@ #define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - #ifndef USE_920T_MMU - #define CONFIG_CMD_PING - #undef CONFIG_CMD_CACHE +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE)) #else - #define CONFIG_CMD_DATE +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE) #endif +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #define CONFIG_BOOTDELAY 3 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h index 11ede9681..4002e6849 100644 --- a/include/configs/lpd7a404.h +++ b/include/configs/lpd7a404.h @@ -55,32 +55,19 @@ #define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - #ifndef USE_920T_MMU - #define CONFIG_CMD_PING) - #undef CONFIG_CMD_CACHE +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE)) #else - #define CONFIG_CMD_DATE +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE) #endif +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #define CONFIG_BOOTDELAY 3 -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 805cc59b3..0335a0098 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -37,19 +37,18 @@ #define CONFIG_440 1 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -/* - * Include common defines/options for all AMCC eval boards - */ -#define CONFIG_HOSTNAME luan -#include "amcc-common.h" - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */ +#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) +#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */ + #define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ #define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ #define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ @@ -69,6 +68,7 @@ #define CFG_FLASH_BASE CFG_SMALL_FLASH #endif +#undef CFG_DRAM_TEST #if CFG_SRAM_BASE #define CFG_KBYTES_SDRAM 1024*2 #else @@ -88,8 +88,13 @@ * Serial Port *----------------------------------------------------------------------*/ #define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#undef CONFIG_SERIAL_MULTI #undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ @@ -127,55 +132,132 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ -#define CONFIG_DDR_ECC 1 /* with ECC support */ +#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */ +#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */ +#define IIC0_DIMM0_ADDR 0x52 +#define IIC0_DIMM1_ADDR 0x53 /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" -/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_PPC \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=luan\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):$(netdev):off panic=1\0" \ + "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/luan/uImage\0" \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc100000\0" \ + "load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ "" +#define CONFIG_BOOTCOMMAND "run flash_self" -#define CONFIG_HAS_ETH0 +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + #ifdef DEBUG #define CONFIG_PANIC_HANG #else #define CONFIG_HW_WATCHDOG /* watchdog */ #endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_CACHE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SETGETDCR | \ + CFG_CMD_SDRAM | \ + 0) + +/* this must be included AFTER the definition of CONFIG_COMMANDS */ +#include + /* - * Commands additional to the ones defined in amcc-common.h + * Miscellaneous configurable options */ -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SDRAM +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#undef CONFIG_LYNXKDI /* support kdi files */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- */ -#if defined(CONFIG_CMD_PCI) +#if (CONFIG_COMMANDS & CFG_CMD_PCI) /* General PCI */ #define CONFIG_PCI /* include pci support */ @@ -183,12 +265,42 @@ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ /* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #undef CFG_PCI_MASTER_INIT #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */ +#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif #endif /* __CONFIG_H */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 82fe19c72..ad1035b6d 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -42,7 +42,6 @@ #endif #define CONFIG_MMC 1 #define BOARD_LATE_INIT 1 -#define CONFIG_DOS_PARTITION #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -68,24 +67,10 @@ #define CONFIG_BAUDRATE 115200 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b @@ -97,7 +82,7 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_TIMESTAMP -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index 87abfba14..9b4c0046e 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -170,41 +170,34 @@ #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BMP -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - #ifdef CONFIG_POST -#define CONFIG_CMD_DIAG +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#else +#define CFG_CMD_POST_DIAG 0 #endif - +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_BMP | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_NFS | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_SNTP ) #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options @@ -217,7 +210,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -252,8 +245,7 @@ #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ #if 0 #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d sec...\n", bootdelay +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ #endif /*----------------------------------------------------------------------*/ @@ -284,7 +276,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) || defined(CONFIG_CMD_IDE) +#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ @@ -378,7 +370,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index e4c3f7239..ce33b85c9 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006-2008 + * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -37,10 +37,13 @@ #define CONFIG_MISC_INIT_R -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -48,36 +51,16 @@ * To select console on the one of 8 external UARTs, * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, * or as 5, 6, 7, or 8 for the second Quad UART. - * COM11, COM12, COM13, COM14 are located on the second Quad UART. * * CONFIG_PSC_CONSOLE must be undefined in this case. */ -#if !defined(CONFIG_PRS200) -/* MCC200 configuration: */ -#ifdef CONFIG_CONSOLE_COM12 -#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ -#else -#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ -#endif -#else -/* PRS200 configuration: */ -#undef CONFIG_QUART_CONSOLE -#endif /* CONFIG_PRS200 */ +/* #define CONFIG_QUART_CONSOLE 1 */ /* console is on UART1 of QUART1 */ /* * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 * and undefine CONFIG_QUART_CONSOLE. */ -#if !defined(CONFIG_PRS200) -/* MCC200 configuration: */ -#define CONFIG_SERIAL_MULTI 1 -#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ -#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ -#else -/* PRS200 configuration: */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#endif -#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \ - !defined(CONFIG_SERIAL_MULTI) +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) #error "Select only one console device!" #endif #define CONFIG_BAUDRATE 115200 @@ -89,95 +72,59 @@ /* USB */ #define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -/* automatic software updates (see board/mcc200/auto_update.c) */ -#define CONFIG_AUTO_UPDATE 1 - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_USB - -#undef CONFIG_CMD_NET +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + ADD_USB_CMD | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* * Autobooting */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) - -#ifdef CONFIG_PRS200 -# define CFG__BOARDNAME "prs200" -# define CFG__LINUX_CONSOLE "ttyS0" -#else -# define CFG__BOARDNAME "mcc200" -# define CFG__LINUX_CONSOLE "ttyEU5" -#endif - -/* Network */ -#define CONFIG_ETHADDR 00:17:17:ff:00:00 -#define CONFIG_IPADDR 10.76.9.29 -#define CONFIG_SERVERIP 10.76.9.1 - -#include /* For U-Boot version */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ubootver=" U_BOOT_VERSION "\0" \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "hostname=" CFG__BOARDNAME "\0" \ + "hostname=mcc200\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/mtdblock2 " \ - "rootfstype=cramfs\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate} " \ - "ubootver=${ubootver} board=${board}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ + "flash_nfs=run nfsargs addip;" \ "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ + "flash_self=run ramargs addip;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "console=" CFG__LINUX_CONSOLE "\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \ - "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \ - "text_base=" MK_STR(TEXT_BASE) "\0" \ - "kernel_addr=0xFC0C0000\0" \ - "update=protect off ${text_base} +${filesize};" \ - "era ${text_base} +${filesize};" \ - "cp.b 200000 ${text_base} ${filesize}\0" \ + "bootfile=/tftpboot/mcc200/uImage\0" \ + "baudrate=115200\0" \ + "load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0" \ + "update=protect off FFF00000 +${filesize};" \ + "era FFF00000 +${filesize};" \ + "cp.b 200000 FFF00000 ${filesize}\0" \ + "serverip=192.168.1.1\0" \ + "ipaddr=192.168.133.144\0" \ + "netmask=255.255.0.0\0" \ "unlock=yes\0" \ + "ethaddr=00:02:44:7D:73:3B\0" \ "" -#undef MK_STR -#undef XMK_STR #define CONFIG_BOOTCOMMAND "run flash_self" @@ -187,13 +134,13 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ /* * I2C configuration */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ #define CFG_I2C_SPEED 100000 /* 100 kHz */ #define CFG_I2C_SLAVE 0x7F @@ -203,9 +150,9 @@ * TEXT base always at 0xFFF00000 * ENV_ADDR always at 0xFFF40000 * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB + * 0xFE000000 for 32 MB + * 0xFF000000 for 16 MB + * 0xFF800000 for 8 MB */ #define CFG_FLASH_BASE 0xfc000000 #define CFG_FLASH_SIZE 0x04000000 @@ -227,9 +174,9 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ -#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ @@ -259,7 +206,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_BASE TEXT_BASE #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) # define CFG_RAMBOOT 1 #endif @@ -271,65 +218,41 @@ /* * Ethernet configuration */ -/*#define CONFIG_MPC5xxx_FEC 1*/ +#define CONFIG_MPC5xxx_FEC 1 /* * Define CONFIG_FEC_10MBIT to force FEC at 10Mb */ /* #define CONFIG_FEC_10MBIT 1 */ #define CONFIG_PHY_ADDR 1 -/* - * LCD Splash Screen - */ -#if !defined(CONFIG_PRS200) -#define CONFIG_LCD 1 -#define CONFIG_PROGRESSBAR 1 -#endif - -#if defined(CONFIG_LCD) -#define CONFIG_SPLASH_SCREEN 1 -#define CFG_CONSOLE_IS_IN_ENV 1 -#define LCD_BPP LCD_MONOCHROME -#endif - /* * GPIO configuration */ /* 0x10000004 = 32MB SDRAM */ /* 0x90000004 = 64MB SDRAM */ -#if defined(CONFIG_LCD) -/* set PSC2 in UART mode */ -#define CFG_GPS_PORT_CONFIG 0x00000044 -#else #define CFG_GPS_PORT_CONFIG 0x00000004 -#endif /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Various low-level settings */ @@ -352,13 +275,6 @@ #define CFG_CS1_SIZE 0x00001000 #define CFG_CS1_CFG 0x1d300 -/* Leica - build revision resistors */ -/* -#define CFG_CS3_START 0x80020000 -#define CFG_CS3_SIZE 0x00000004 -#define CFG_CS3_CFG 0x1d300 -*/ - /* * Select one of quarts as a default * console. If undefined - PSC console @@ -393,7 +309,7 @@ * One of four SC16C554 UARTs is selected with * A3-A4 (DA5-DA6) lines. */ -#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) +#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) #define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) #define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) @@ -414,8 +330,4 @@ #define CONFIG_USB_CLOCK 0x0001BBBB #define CONFIG_USB_CONFIG 0x00005000 -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR "432" -#define CONFIG_SILENT_CONSOLE 1 - #endif /* __CONFIG_H */ diff --git a/include/configs/ml300.h b/include/configs/ml300.h index 319923ad6..6762cd61e 100644 --- a/include/configs/ml300.h +++ b/include/configs/ml300.h @@ -54,7 +54,6 @@ #define CONFIG_405 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_XILINX_405 1 #define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */ #define CONFIG_SYSTEMACE 1 @@ -88,28 +87,13 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define REMOVE_COMMANDS (CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_FAT | \ + CFG_CMD_IMLS ) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NET) \ + & ~REMOVE_COMMANDS) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_NET - -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_FAT -#undef CONFIG_CMD_IMLS - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include /* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */ /* 300000000 */ @@ -160,6 +144,12 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ + /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h index 5159897db..20287674f 100644 --- a/include/configs/modnet50.h +++ b/include/configs/modnet50.h @@ -63,23 +63,12 @@ #define CONFIG_BAUDRATE 38400 -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_JFFS2)) -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_JFFS2 - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 192.168.30.2 @@ -90,10 +79,9 @@ /*#define CONFIG_BOOTDELAY 10*/ /* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */ #define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000" -#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K " \ - "root=/dev/ram keepinitrd" +#define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 87264fbb4..04f1f2408 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -47,7 +47,7 @@ #define CFG_ATMEL_PLL_INIT_BUG 1 #ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CFG_USE_MAIN_OSCILLATOR 1 +#define CFG_USE_MAIN_OSCILLATOR 1 /* flash */ #define MC_PUIA_VAL 0x00000000 #define MC_PUP_VAL 0x00000000 @@ -55,7 +55,7 @@ #define MC_ASR_VAL 0x00000000 #define MC_AASR_VAL 0x00000000 #define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ +#define SMC2_CSR_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ /* clocks */ #define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ @@ -101,18 +101,12 @@ #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ -#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_USB_OHCI 1 #define CONFIG_USB_KEYBOARD 1 #define CONFIG_USB_STORAGE 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_AT91C_PQFP_UHPBUG 1 -#undef CFG_USB_OHCI_BOARD_INIT -#define CFG_USB_OHCI_CPU_INIT 1 -#define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE -#define CFG_USB_OHCI_SLOT_NAME "at91rm9200" -#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 - #undef CONFIG_HARD_I2C #ifdef CONFIG_HARD_I2C @@ -129,56 +123,40 @@ #define CONFIG_BOOTDELAY 3 -#if !defined(CONFIG_HARD_I2C) +#ifdef CONFIG_HARD_I2C +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + CFG_CMD_MISC)) +#else +#define CONFIG_COMMANDS \ + ((CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP | \ + CFG_CMD_USB | \ + CFG_CMD_CACHE) & \ + ~(CFG_CMD_BDI | \ + CFG_CMD_IMI | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_FPGA | \ + CFG_CMD_MISC | \ + CFG_CMD_LOADS )) #define CONFIG_TIMESTAMP #endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#if defined(CONFIG_HARD_I2C) - - #define CONFIG_CMD_DATE - #define CONFIG_CMD_EEPROM - #define CONFIG_CMD_I2C - #define CONFIG_CMD_MISC - -#else - - #define CONFIG_CMD_USB - #define CONFIG_CMD_CACHE - - #undef CONFIG_CMD_AUTOSCRIPT - #undef CONFIG_CMD_BDI - #undef CONFIG_CMD_FPGA - #undef CONFIG_CMD_IMI - #undef CONFIG_CMD_LOADS - #undef CONFIG_CMD_MISC - -#endif - - #define CFG_LONGHELP +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ #define CFG_MEMTEST_START PHYS_SDRAM #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 @@ -216,6 +194,25 @@ #define CFG_DEVICE_DEREGISTER /* needs device_deregister */ #define LITTLEENDIAN 1 /* used by usb_ohci.c */ +#ifndef __ASSEMBLY__ +/*----------------------------------------------------------------------- + * Board specific extension for bd_info + * + * This structure is embedded in the global bd_info (bd_t) structure + * and can be used by the board specific code (eg board/...) + */ + +struct bd_info_ext { + /* helper variable for board environment handling + * + * env_crc_valid == 0 => uninitialised + * env_crc_valid > 0 => environment crc in flash is valid + * env_crc_valid < 0 => environment crc in flash is invalid + */ + int env_crc_valid; +}; +#endif /* __ASSEMBLY__ */ + #define CFG_HZ 1000 #define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ /* AT91C_TC_TIMER_DIV1_CLOCK */ @@ -230,8 +227,7 @@ #undef CONFIG_SILENT_CONSOLE /* enable silent startup */ #define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" #define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_AUTOBOOT_DELAY_STR "d" diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h index 5125b21e0..7f3dfd5c9 100644 --- a/include/configs/mx1ads.h +++ b/include/configs/mx1ads.h @@ -78,32 +78,25 @@ #define CONFIG_BAUDRATE 115200 +/*********************************************************** + * Command definition + ***********************************************************/ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_ELF +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + CFG_CMD_REGINFO | \ + CFG_CMD_ELF) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "root=/dev/msdk mem=48M" #define CONFIG_BOOTFILE "mx1ads" #define CONFIG_BOOTCOMMAND "tftp; bootm" -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h index d527d098f..9816be8dc 100644 --- a/include/configs/mx1fs2.h +++ b/include/configs/mx1fs2.h @@ -34,30 +34,22 @@ #undef _CONFIG_UART4 /* internal uart 4 */ #undef CONFIG_SILENT_CONSOLE /* use this to disable output */ - /* - * BOOTP options + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting + * functionality or size of u-boot code. */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_JFFS2 - -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_CONSOLE -#undef CONFIG_CMD_AUTOSCRIPT -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_PING -#undef CONFIG_CMD_DHCP +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + & ~CFG_CMD_LOADS \ + & ~CFG_CMD_CONSOLE \ + & ~CFG_CMD_AUTOSCRIPT \ + & ~CFG_CMD_NET \ + & ~CFG_CMD_PING \ + & ~CFG_CMD_DHCP \ + | CFG_CMD_JFFS2 \ + ) +#include /* * Boot options. Setting delay to -1 stops autostart count down. @@ -168,7 +160,7 @@ * Right now there is no gain for user, but later on booting kernel might be * possible. Consider using XIP kernel running from flash to save RAM * footprint. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. + * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. */ /* diff --git a/include/configs/netstar.h b/include/configs/netstar.h index 756b7c267..697796a11 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -48,15 +48,14 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 +#define CFG_DEVICE_NULLDEV 1 /* enable null device */ #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ -#define CFG_CONSOLE_INFO_QUIET /* * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ /* @@ -64,21 +63,30 @@ */ #define CFG_FLASH_BASE PHYS_FLASH_1 #define CFG_MAX_FLASH_BANKS 1 -#define PHYS_FLASH_1_SIZE (1 * 1024 * 1024) +#if (PHYS_SDRAM_1_SIZE == SZ_32M) +/*#if 1*/ +#define CFG_FLASH_CFI /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER /* Use the common driver */ +#define CFG_FLASH_EMPTY_INFO +#define CFG_MAX_FLASH_SECT 128 +#else +#define PHYS_FLASH_1_SIZE SZ_1M #define CFG_MAX_FLASH_SECT 19 #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */ #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) +#endif #define CFG_MONITOR_BASE PHYS_FLASH_1 -#define CFG_MONITOR_LEN (256 * 1024) +#define CFG_MONITOR_LEN SZ_256K /* * Environment settings */ #define CFG_ENV_IS_IN_FLASH +#define ENV_IS_SOLITARY #define CFG_ENV_ADDR 0x4000 -#define CFG_ENV_SIZE (8 * 1024) -#define CFG_ENV_SECT_SIZE (8 * 1024) +#define CFG_ENV_SIZE SZ_8K +#define CFG_ENV_SECT_SIZE SZ_8K #define CFG_ENV_ADDR_REDUND 0x6000 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE #define CONFIG_ENV_OVERWRITE @@ -87,12 +95,14 @@ * Size of malloc() pool */ #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_MALLOC_LEN (4 * 1024 * 1024) +/* XXX #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)*/ +#define CFG_MALLOC_LEN SZ_4M /* * The stack size is set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (1 * 1024 * 1024) /* regular stack */ +/* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */ +#define CONFIG_STACKSIZE SZ_1M /* regular stack */ /* * Hardware drivers @@ -122,82 +132,85 @@ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 #define CFG_NAND_BASE 0x04000000 + (2 << 23) -#define NAND_ALLOW_ERASE_ALL 1 /* - * partitions (mtdparts command line support) + * JFFS2 partitions (mtdparts command line support) */ #define CONFIG_JFFS2_CMDLINE #define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0" -#define MTDPARTS_DEFAULT "mtdparts=" \ - "omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \ - "omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)" +#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)" +#if 0 +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_DHCP | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_LOADB | \ + CFG_CMD_NET | \ + CFG_CMD_MEMORY | \ + CFG_CMD_PING | \ + CFG_CMD_RUN) -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_IMI -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NAND -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_RUN - +#else +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_BOOTD | \ + CFG_CMD_DHCP | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_NAND | \ + CFG_CMD_IMI | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_LOADB | \ + CFG_CMD_NET | \ + CFG_CMD_MEMORY | \ + CFG_CMD_PING | \ + CFG_CMD_RUN) #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ +#endif -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT #define CONFIG_LOOPW +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CFG_AUTOLOAD "n" /* No autoload */ -#define CONFIG_BOOTCOMMAND "run fboot" +#define CONFIG_BOOTCOMMAND "run nboot" #define CONFIG_PREBOOT "run setup" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autostart=yes\0" \ - "ospart=0\0" \ - "setup=setenv bootargs console=ttyS0,$baudrate " \ - "$mtdparts\0" \ - "setpart=" \ - "if test -n $swapos; then " \ - "setenv swapos; saveenv; " \ - "else " \ - "if test $ospart -eq 0; then setenv ospart 1;" \ - "else setenv ospart 0; fi; " \ - "fi\0" \ - "nfsargs=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ - "nfsroot=$rootpath root=/dev/nfs\0" \ - "flashargs=run setpart;setenv bootargs $bootargs " \ - "root=mtd:rootfs$ospart ro " \ - "rootfstype=jffs2\0" \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ - "fboot=run flashargs;nboot kernel$ospart\0" \ - "nboot=bootp;run nfsargs;tftp\0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "setup=setenv bootargs console=ttyS0,$baudrate " \ + "$mtdparts\0" \ + "ospart=0\0" \ + "setpart=" \ + "if test -n $swapos; then " \ + "if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\ + "setenv swapos; saveenv; " \ + "else " \ + "chpart nand0,$ospart; " \ + "fi\0" \ + "nfsargs=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ + "nfsroot=$rootpath root=/dev/nfs\0" \ + "flashargs=run setpart;setenv bootargs $bootargs " \ + "root=/dev/mtdblock$partition ro " \ + "rootfstype=jffs2\0" \ + "initrdargs=setenv bootargs $bootargs " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ + "iboot=bootp;run initrdargs;tftp;bootm\0" \ + "fboot=run flashargs;fsload /boot/uImage;bootm\0" \ + "nboot=bootp;run nfsargs;tftp;bootm\0" #if 0 /* feel free to disable for development */ #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ -#define CONFIG_AUTOBOOT_PROMPT \ - "\nNetStar PBX - boot in %d secs...\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */ +#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n" +#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */ +#define CONFIG_BOOT_RETRY_TIME 30 #endif /* @@ -215,8 +228,7 @@ #define CONFIG_AUTO_COMPLETE #define CFG_MEMTEST_START PHYS_SDRAM_1 -#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \ - (CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE) +#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h index f30cb46cf..0b1541d5c 100644 --- a/include/configs/ns9750dev.h +++ b/include/configs/ns9750dev.h @@ -62,38 +62,43 @@ /* * select serial console configuration */ -#define CONFIG_CONS_INDEX 1 /* Port B */ +#define CONFIG_CONS_INDEX 1 /* Port B */ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_BAUDRATE 38400 +/*********************************************************** + * Command definition + ***********************************************************/ +#if 0 /* @TODO */ +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_CACHE | \ + /*CFG_CMD_NAND |*/ \ + /*CFG_CMD_EEPROM |*/ \ + /*CFG_CMD_I2C |*/ \ + /*CFG_CMD_USB |*/ \ + CFG_CMD_REGINFO | \ + CFG_CMD_DATE | \ + CFG_CMD_ELF) +#else +#define CONFIG_COMMANDS \ + (CONFIG_CMD_BDI | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_CONSOLE | \ + CFG_CMD_LOADB | \ + CFG_CMD_LOADS | \ + CFG_CMD_MEMORY) +#endif -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #define CONFIG_BOOTDELAY 3 -/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ +/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ #define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */ #define CONFIG_NETMASK 255.255.255.0 @@ -103,7 +108,7 @@ /*#define CONFIG_BOOTFILE "elinos-lart" */ /*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 88bdb03e6..5c05a745d 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -37,7 +37,10 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Serial console configuration @@ -54,7 +57,6 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* #define CONFIG_PCI_SCAN_SHOW 1 */ -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_PCI_MEM_BUS 0x40000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -71,6 +73,8 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 +#define ADD_PCI_CMD CFG_CMD_PCI + /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -78,29 +82,20 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_PCI +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + ADD_PCI_CMD ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 @@ -114,7 +109,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -142,17 +137,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ -#if defined(CFG_IPBCLK_EQUALS_XLBCLK) +#if defined(CFG_IPBSPEED_133) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't + * been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ +#define CFG_PCISPEED_66 /* define for 66MHz speed */ #endif #endif @@ -251,7 +246,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -267,11 +262,6 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Various low-level settings */ @@ -286,7 +276,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 +#ifdef CFG_PCISPEED_66 /* * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash). */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 407aae721..a13d6a870 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -41,22 +41,18 @@ *----------------------------------------------------------------------*/ #define CONFIG_OCOTEA 1 /* Board is ebony */ #define CONFIG_440GX 1 /* Specifc GX support */ -#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -/* - * Include common defines/options for all AMCC eval boards - */ -#define CONFIG_HOSTNAME ocotea -#include "amcc-common.h" - /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ @@ -78,11 +74,18 @@ #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /*----------------------------------------------------------------------- * Environment @@ -133,7 +136,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ @@ -145,33 +148,65 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ -#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_ENABLE -#define CFG_EEPROM_PAGE_WRITE_BITS 3 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS -/* - * Default environment variables - */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_PPC \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "netdev=eth0\0" \ + "hostname=ocotea\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/ocotea/uImage\0" \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ + "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ "" +#define CONFIG_BOOTCOMMAND "run flash_self" +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 2 #define CONFIG_PHY2_ADDR 0x10 @@ -185,13 +220,58 @@ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ #define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + /* - * Commands additional to the ones defined in amcc-common.h + * Miscellaneous configurable options */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ /*----------------------------------------------------------------------- * PCI stuff @@ -204,9 +284,37 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h index 0be46eace..016d3d8bd 100644 --- a/include/configs/omap1510inn.h +++ b/include/configs/omap1510inn.h @@ -86,24 +86,11 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #include #define CONFIG_BOOTDELAY 3 @@ -111,7 +98,7 @@ #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" #define CFG_AUTOLOAD "n" /* No autoload */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ @@ -179,7 +166,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h index 74bba05fe..c6ca689a5 100644 --- a/include/configs/omap1610h2.h +++ b/include/configs/omap1610h2.h @@ -81,24 +81,11 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #include #define CONFIG_BOOTDELAY 3 @@ -106,7 +93,7 @@ #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" #define CFG_AUTOLOAD "n" /* No autoload */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ #endif diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h index 734f35439..f28ede096 100644 --- a/include/configs/omap1610inn.h +++ b/include/configs/omap1610inn.h @@ -82,24 +82,11 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #include #define CONFIG_BOOTDELAY 3 @@ -111,7 +98,7 @@ #define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ #define CONFIG_BOOTFILE "uImage" /* file to load */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ #endif diff --git a/include/configs/omap1710h3.h b/include/configs/omap1710h3.h new file mode 100644 index 000000000..0a2cf9df0 --- /dev/null +++ b/include/configs/omap1710h3.h @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2003 + * Texas Instruments. + * Kshitij Gupta + * Configuation settings for the TI OMAP H3 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +//#define CFG_NAND_BOOT + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +//#define CONFIG_INIT_CRITICAL /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP1710 1 /* which is in a 1710 */ +#define CONFIG_H3_OMAP1710 1 /* a H3 Board */ + +/* input clock of PLL */ +/* the OMAP1710 H3 has 12MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 12000000 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +/* +*/ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE 0x04000300 +#define CONFIG_LAN91C96_EXT_PHY + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1710 H3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_NAND | CFG_CMD_JFFS2) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#include + + +/* + * Board NAND Info. + */ +#ifdef CFG_NAND_BOOT +#define CFG_NAND_ADDR 0x0c000000 /* physical address to access nand at CS3*/ +#else +#define CFG_NAND_ADDR 0x0a000000 /* physical address to access nand at CS2B*/ +#endif + +#define CONFIG_H3_NAND_16BIT + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr + 2) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr + 4) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u16 *)((unsigned long)adr) = (__u16)(d); } while(0) +#define READ_NAND(adr) ((volatile __u16)(*(volatile __u16 *)(unsigned long)adr)) + +#define NAND_NO_RB 1 +#define NAND_WAIT_READY(nand) udelay(35) + +#define NAND_CTL_CLRALE(nandptr) udelay(1); +#define NAND_CTL_SETALE(nandptr) udelay(1); +#define NAND_CTL_CLRCLE(nandptr) udelay(1); +#define NAND_CTL_SETCLE(nandptr) udelay(1); +#define NAND_DISABLE_CE(nand) udelay(1); +#define NAND_ENABLE_CE(nand) udelay(1); + + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ + root=/dev/nfs rw nfsroot=157.87.82.48:\ + /home/a0875451/mwd/myfs/target ip=dhcp" +#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ +#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ +#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ +#define CONFIG_BOOTFILE "uImage" /* file to load */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "OMAP1710 H3 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x10000000 /* default load address */ + +/* The 1710 has 6 timers, they can be driven by the RefClk (12Mhz) or by + * DPLL1. This time is further subdivided by a local divisor. + */ +#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#ifdef CFG_NAND_BOOT +#define PHYS_FLASH_1 0x0a000000 /* Flash Bank #1 */ +#else +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#endif + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +#ifdef CFG_NAND_BOOT + +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x50000 /* environment starts here */ + +#else +/* addr of environment */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ + +#endif /* CFG_NAND_BOOT */ + +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) +#define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK 1 /* use flash_info[1] */ +#define CFG_JFFS2_NUM_BANKS 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 88a3f6eb9..7fa373fc8 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -33,30 +33,29 @@ */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP2420 1 /* which is in a 2420 */ -#define CONFIG_OMAP2420H4 1 /* and on a H4 board */ -/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */ -/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ +#define CONFIG_OMAP24XX 1 /* which is a 24XX Processor */ +#define CONFIG_OMAP242X 1 /* which is in a 242X */ +#define CONFIG_OMAP24XXH4 1 /* and on a H4 board */ /* Clock config to target*/ -#define PRCM_CONFIG_II 1 -/* #define PRCM_CONFIG_III 1 */ +/* #define PRCM_CONFIG_II 1 */ +#define PRCM_CONFIG_III 1 -#include /* get chip and board defs */ +#include /* get chip and board defs */ /* On H4, NOR and NAND flash are mutual exclusive. Define this if you want to use NAND */ -/*#define CFG_NAND_BOOT */ -#ifdef CONFIG_APTIX -#define V_SCLK 1500000 -#else +/* +#define CFG_NAND_BOOT +#define CFG_NAND_2420 +*/ + #define V_SCLK 12000000 -#endif /* input clock of PLL */ -/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ +/* the OMAP24XX H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ #define CONFIG_SYS_CLK_FREQ V_SCLK #undef CONFIG_USE_IRQ /* no support for IRQs */ @@ -82,36 +81,25 @@ * SMC91c96 Etherent */ #define CONFIG_DRIVER_LAN91C96 -#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300) +#define CONFIG_LAN91C96_BASE (DEBUG_BASE+0x300) #define CONFIG_LAN91C96_EXT_PHY /* * NS16550 Configuration */ -#ifdef CONFIG_APTIX -#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */ -#else #define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ -#endif #define CFG_NS16550 #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE (-4) #define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ -#define CFG_NS16550_COM1 OMAP2420_UART1 +#define CFG_NS16550_COM1 OMAP24XX_UART1 /* * select serial console configuration */ #define CONFIG_SERIAL1 1 /* UART1 on H4 */ - /* - * I2C configuration - */ -#define CONFIG_HARD_I2C -#define CFG_I2C_SPEED 100000 -#define CFG_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP24XX_I2C /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -119,40 +107,33 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} - -/* - * Command line configuration. - */ -#include - #ifdef CFG_NAND_BOOT - #define CONFIG_CMD_DHCP - #define CONFIG_CMD_I2C - #define CONFIG_CMD_NAND - #define CONFIG_CMD_JFFS2 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2) #else - #define CONFIG_CMD_DHCP - #define CONFIG_CMD_I2C - #define CONFIG_CMD_JFFS2 - - #undef CONFIG_CMD_AUTOSCRIPT +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) #endif +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - + /* + * I2C configuration + */ +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CONFIG_HARD_I2C +#define CFG_I2C_SPEED 100 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP24XX_I2C 1 +#endif /* * Board NAND Info. */ -#define CFG_NAND_LEGACY -#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ +#define CFG_NAND_ADDR NAND_BASE /* physical address to access nand at CS0*/ +#define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 @@ -165,17 +146,10 @@ #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0) -#define READ_NAND(adr) (*(volatile u16 *)0x6800A084) #define NAND_WAIT_READY(nand) udelay(10) - #define NAND_NO_RB 1 #define CFG_NAND_WP -#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) -#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) #define NAND_CTL_CLRALE(nandptr) #define NAND_CTL_SETALE(nandptr) @@ -184,6 +158,7 @@ #define NAND_DISABLE_CE(nand) #define NAND_ENABLE_CE(nand) + #define CONFIG_BOOTDELAY 3 #ifdef NFS_BOOT_DEFAULTS @@ -200,11 +175,7 @@ /* * Miscellaneous configurable options */ -#ifdef CONFIG_APTIX -#define V_PROMPT "OMAP2420 Aptix # " -#else #define V_PROMPT "OMAP242x H4 # " -#endif #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT V_PROMPT @@ -214,23 +185,18 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ -#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) +#define CFG_MEMTEST_START (OMAP24XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP24XX_SDRC_CS0+SZ_31M) #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ +#define CFG_LOAD_ADDR (OMAP24XX_SDRC_CS0) /* default load address */ /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ -#ifdef CONFIG_APTIX -#define V_PVT 3 -#else #define V_PVT 7 /* use with 12MHz/128 */ -#endif - -#define CFG_TIMERBASE OMAP2420_GPT2 +#define CFG_TIMERBASE OMAP24XX_GPT2 #define CFG_PVT V_PVT /* 2^(pvt+1) */ #define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) @@ -249,14 +215,14 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0 +#define PHYS_SDRAM_1 OMAP24XX_SDRC_CS0 #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ -#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 +#define PHYS_SDRAM_2 OMAP24XX_SDRC_CS1 #define PHYS_FLASH_SECT_SIZE SZ_128K -#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */ +#define PHYS_FLASH_1 FLASH_BASE /* Flash Bank #1 */ #define PHYS_FLASH_SIZE_1 SZ_32M -#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ +#define PHYS_FLASH_2 (FLASH_BASE+SZ_32M) /* same cs, 2 chips in series */ #define PHYS_FLASH_SIZE_2 SZ_32M /*----------------------------------------------------------------------- @@ -266,24 +232,27 @@ #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ #define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ -#define CFG_MONITOR_LEN SZ_128K /* Reserve 1 sector */ +#define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 } #ifdef CFG_NAND_BOOT #define CFG_ENV_IS_IN_NAND 1 #define CFG_ENV_OFFSET 0x80000 /* environment starts here */ #else -#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K) +#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_256K) #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE #define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ #endif + + + /*----------------------------------------------------------------------- * CFI FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ #define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ @@ -291,23 +260,40 @@ #define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) #define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK 1 /* use flash_info[1] */ +#define CFG_JFFS2_NUM_BANKS 1 -/* - * JFFS2 partitions - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor1" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 +/* GPMC Settings */ +#ifdef CFG_NAND_BOOT +/* NAND */ +#define FLASH_CONFIGURATION_IDX 1 +#else +/* NOR */ +#define FLASH_CONFIGURATION_IDX 0 +#endif +#define PROC_NOR_SIZE GPMC_SIZE_64M +#define PROC_NAND_SIZE GPMC_SIZE_64M +#define DBG_MPDB_SIZE GPMC_SIZE_16M -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor1=omap2420-1" -#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)" -*/ + +/* Other NAND Access APIs */ +#ifdef CFG_NAND_BOOT +#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)(0x6800A07C)= (d);} while(0) +#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)(0x6800A080) = (d);} while(0) +#define WRITE_NAND(d, adr) do {*(volatile u16 *)(0x6800A084)= (d);} while(0) +#define READ_NAND(adr) (*(volatile u16 *)(0x6800A084)) +#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) +#endif /* NAND Commands */ #endif /* __CONFIG_H */ diff --git a/include/configs/omap2430sdp.h b/include/configs/omap2430sdp.h new file mode 100644 index 000000000..dbd92b944 --- /dev/null +++ b/include/configs/omap2430sdp.h @@ -0,0 +1,305 @@ +/* + * (C) Copyright 2004-2005 + * Texas Instruments. + * Richard Woodruff + * Kshitij Gupta + * + * Configuration settings for the 242x TI SDP2430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP24XX 1 /* which is a 24XX */ +#define CONFIG_OMAP243X 1 /* which is in a 243X */ +#define CONFIG_2430SDP 1 /* working with SDP? make this 1 */ + +/* Clock config for target */ +//#define PRCM_CONFIG_5A 1 /* 2430 ES1 */ +#define PRCM_CONFIG_2 1 /* 2430 ES2+330ARM+DDR-165-PISMO */ + +#define OMAP2430_SQUARE_CLOCK_INPUT 1 + +#include /* get chip and board defs */ + +#define V_SCLK 13000000 + +/* input clock of PLL */ +/* the OMAP24XX SDP has 12MHz, 13MHz, or 19.2Mhz crystal input */ +#define CONFIG_SYS_CLK_FREQ V_SCLK + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK V_NS16550_CLK +#define CFG_NS16550_COM1 OMAP24XX_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on SDP */ +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +#define NET_CMDS (CFG_CMD_DHCP|CFG_CMD_NFS|CFG_CMD_NET) + +/* Config CMD*/ +//#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_NAND | CFG_CMD_ONENAND | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) + +//#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) + +#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ONENAND | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +/* + * SMC91c96 Etherent + */ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE (DEBUG_BASE+0x300) +#define CONFIG_LAN91C96_EXT_PHY +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CFG_I2C_SPEED 100 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP24XX_I2C 1 +#endif + +/* + * Board NAND Info. + */ +#define CFG_NAND_ADDR NAND_BASE /* physical address to access nand*/ +#define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/ + + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CFG_NAND_WP + + +#define CONFIG_BOOTDELAY 3 + +#ifdef NFS_BOOT_DEFAULTS +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" +#else + +#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" + +#endif + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP243X SDP # " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP24XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP24XX_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP24XX_SDRC_CS0) /* default load address */ + +/* The 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CFG_TIMERBASE OMAP24XX_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP24XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP24XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +//#define SDRC_B_R_C 1 +//#define SDRC_B1_R_B0_C 1 +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO - REV A Version is as follows */ +#define PISMO_CS0 PISMO_SIBLEY0 +#define PISMO_CS1 PISMO_SIBLEY1 +#define PISMO_CS2 PISMO_ONENAND +#define PROC_NOR_SIZE GPMC_SIZE_64M +#define PROC_NAND_SIZE GPMC_SIZE_64M +#define PISMO_SIB0_SIZE GPMC_SIZE_64M +#define PISMO_SIB1_SIZE GPMC_SIZE_64M +#define PISMO_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO_PCMCIA_SIZE GPMC_SIZE_128M + +#define PHYS_FLASH_SIZE SZ_32M +#define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ + +#define CFG_MAX_FLASH_BANKS 4 /* max number of flash banks */ +#define CFG_FLASH_BANKS_LIST { FLASH_BASE, FLASH_BASE + PHYS_FLASH_SIZE, SIBLEY_MAP1, SIBLEY_MAP2 } + + +# define CFG_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec + +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ +#define CFG_ONENAND_BASE ONENAND_MAP + +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_IS_IN_ONENAND 1 +#define CFG_ENV_IS_IN_FLASH 1 +#define ONENAND_ENV_OFFSET 0xc0000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x80000 /* environment starts here */ + +#define CFG_ENV_SECT_SIZE boot_flash_sec +#define CFG_ENV_OFFSET boot_flash_off +#define CFG_ENV_ADDR boot_flash_env_addr + + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ +#define CFG_FLASH_QUIET_TEST 1 /* Dont crib abt missing chips */ +#define CFG_FLASH_CFI_WIDTH 0x02 +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) +#define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK CFG_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CFG_JFFS2_NUM_BANKS 1 +#define CONFIG_LED_INFO +#define CONFIG_LED_LEN 16 + +#define ENV_IS_VARIABLE 1 + +#ifndef __ASSEMBLY__ +extern unsigned int nand_cs_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3430labrador.h b/include/configs/omap3430labrador.h new file mode 100644 index 000000000..f43bfcc96 --- /dev/null +++ b/include/configs/omap3430labrador.h @@ -0,0 +1,355 @@ +/* + * (C) Copyright 2006 + * Texas Instruments. + * Richard Woodruff + * Syed Mohammed Khasim + * + * Configuration settings for the 3430 TI SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_3430LABRADOR 1 /* working on Labrador */ +#define CONFIG_FASTBOOT 1 /* Using fastboot interface */ +#define CONFIG_TWL4030_USB 1 /* Initialize twl usb */ + +//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ + + +#include /* get chip and board defs */ + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#define V_SCLK V_OSCK + +//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK (48000000) /* 48MHz */ + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK V_NS16550_CLK +#define CFG_NS16550_COM1 OMAP34XX_UART1 +//#define CFG_NS16550_COM2 OMAP34XX_UART2 +#define CFG_NS16550_COM3 OMAP34XX_UART3 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL3 3 /* UART3 on board */ +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 3 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_MMC 1 +#define CFG_MMC_BASE 0xF0000000 +#define CONFIG_DOS_PARTITION 1 + +#define NET_CMDS (CFG_CMD_DHCP|CFG_CMD_NFS|CFG_CMD_NET) + +#ifndef CONFIG_OPTIONAL_NOR_POPULATED +//#define C_MSK (CFG_CMD_FLASH | CFG_CMD_IMLS) +#define C_MSK (CFG_CMD_IMLS | CFG_CMD_FLASH) +#endif + +/* Config CMD*/ +#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP |\ + CFG_CMD_FAT | CFG_CMD_MMC |\ + CFG_CMD_NAND) & ~(C_MSK)) + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +/* + * SMC91c96 Etherent + */ +#define CONFIG_DRIVER_SMSC9118 +#define CONFIG_SMSC9118_BASE (DEBUG_BASE) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CFG_I2C_SPEED 100 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +/* + * Board NAND Info. + */ +#define CFG_NAND_ADDR NAND_BASE /* physical address to access nand*/ +#define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/ +#define CFG_NAND_WIDTH_16 + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +/* To use the 256/512 byte s/w ecc define CFG_SW_ECC_(256/512) */ +/* Use the 512 byte ROM CODE HW ecc */ +#define CFG_HW_ECC_ROMCODE 1 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CFG_NAND_WP + +#define CONFIG_BOOTDELAY 3 + +#ifdef NFS_BOOT_DEFAULTS +#define CONFIG_BOOTARGS "mem=64M console=ttyS2,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" +#else +#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=64M console=ttyS2,115200n8 initrd=0x80600000,8M ramdisk_size=8192" +#endif + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP34XX LAB # " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 24 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ + +/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CFG_TIMERBASE OMAP34XX_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((V_SCLK)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +/*#define SDRC_B_R_C 1 */ +/*#define SDRC_B1_R_B0_C 1 */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +/** REMOVE ME ***/ +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 + +#define CFG_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M + +#define CFG_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec +/* Dummy declaration of flash banks to get compilation right */ +#define CFG_FLASH_BANKS_LIST {0, 0} + +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at start of flash */ + +#if 1 +#define CFG_ENV_IS_IN_NAND 1 +#define ENV_IS_VARIABLE 1 +#else +#define CFG_ENV_IS_NOWHERE 1 +#endif + +#ifdef CONFIG_OPTIONAL_NOR_POPULATED +# define CFG_ENV_IS_IN_FLASH 1 +#endif + +#define SMNAND_ENV_OFFSET 0x1c0000 /* environment starts here */ + +#define CFG_ENV_SECT_SIZE boot_flash_sec +#define CFG_ENV_OFFSET boot_flash_off +#define CFG_ENV_ADDR boot_flash_env_addr + + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#ifndef CONFIG_OPTIONAL_NOR_POPULATED +#define CFG_NO_FLASH 1 /* Disable NOR Flash support */ +#else +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ + +#if (!ENV_IS_VARIABLE) +/* saveenv fails when this variable is defined. + If env is variable, do not use buffered writes */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#endif + +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ +#define CFG_FLASH_QUIET_TEST 1 /* Dont crib abt missing chips */ +#define CFG_FLASH_CFI_WIDTH 0x02 +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) +#define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK CFG_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CFG_JFFS2_NUM_BANKS 1 +#define CONFIG_LED_INFOnand_read_buf16 +#define CONFIG_LED_LEN 16 +#endif /* optional NOR flash */ + +#ifndef __ASSEMBLY__ +extern unsigned int nand_cs_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +/* Fastboot variables */ +#define CFG_FASTBOOT_TRANSFER_BUFFER (PHYS_SDRAM_1 + SZ_16M) +#define CFG_FASTBOOT_TRANSFER_BUFFER_SIZE (SZ_128M - SZ_16M) + +/* Yaffs variables */ +#define CFG_NAND_YAFFS_WRITE + +/* Labrador Battery charging enable */ +#define CFG_BATTERY_CHARGING + +/* Labrador Battery threshold */ +#define CFG_LOW_BAT 3300 /* 3.3V */ +#define CFG_BAT_CHG 4000 /* 4.0V */ + +/* Labrador charger tries */ +#define CFG_CHARGER_TRIES_MAX 100 + +/* Command shell */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* Clock command */ +#define CONFIG_CMD_CLOCK 1 +#define CONFIG_CMD_CLOCK_INFO_CPU 1 + +/* Voltage command */ +#define CONFIG_CMD_VOLTAGE 1 + +#endif /* __CONFIG_H */ + diff --git a/include/configs/omap3430sdp.h b/include/configs/omap3430sdp.h new file mode 100644 index 000000000..fb855aa14 --- /dev/null +++ b/include/configs/omap3430sdp.h @@ -0,0 +1,336 @@ +/* + * (C) Copyright 2006 + * Texas Instruments. + * Richard Woodruff + * Syed Mohammed Khasim + * + * Configuration settings for the 3430 TI SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_3430SDP 1 /* working with SDP */ +//#define CONFIG_3430VIRTIO 1 /* working with SDP? comment this line */ +//#define CONFIG_3430ZEBU 1 /* enable this for 3430 ES2 ZeBu */ +//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ + +//#define CONFIG_ICACHE_OFF 1 /* disabling I Cache for ZeBu */ +//#define CONFIG_L2_OFF 1 + +#define CONFIG_OFF_PADCONF 0 /* Enable OFFMODE pad configuration */ + +#ifdef CONFIG_3430ZEBU + #define CFG_NO_FLASH 1 /* Disable Flash support */ + #define CONFIG_ICACHE_OFF 1 /* disabling I Cache for ZeBu */ +#endif + +#include /* get chip and board defs */ + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#define V_SCLK V_OSCK + +//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK V_NS16550_CLK +#define CFG_NS16550_COM1 OMAP34XX_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on SDP */ +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +#define NET_CMDS (CFG_CMD_DHCP|CFG_CMD_NFS|CFG_CMD_NET) + +/* Config CMD*/ +#ifdef CONFIG_3430ZEBU +#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP) \ + & ~(CFG_CMD_AUTOSCRIPT | CFG_CMD_FLASH | CFG_CMD_IMLS | CFG_CMD_NET) ) +#else +//#define CONFIG_COMMANDS (( CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ONENAND | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) +//#define CONFIG_COMMANDS (( CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_NAND | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) +#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP | \ + CFG_CMD_JFFS2 | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_ONENAND | \ + CFG_CMD_NAND) & ~CFG_CMD_AUTOSCRIPT) + +#endif + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +/* + * SMC91c96 Etherent + */ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE (DEBUG_BASE) +#define CONFIG_LAN91C96_EXT_PHY +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CFG_I2C_SPEED 400 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +/* + * Board NAND Info. + */ +#define CFG_NAND_ADDR NAND_BASE /* physical address to access nand*/ +#define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/ + + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +/* Use the 512 byte ROM CODE HW ecc */ +#define CFG_HW_ECC_ROMCODE 1 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CFG_NAND_WP + +/* Environment information */ +#if defined(CONFIG_3430ZEBU) && !defined(CONFIG_3430ES2) +/* Give the standard Kernel jump command as boot cmd and without any delay */ +#define CONFIG_BOOTDELAY 0 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootcmd=go 0x80008000\0" +#else +#define CONFIG_BOOTDELAY 3 + +#endif /*CONFIG_3430ZEBU */ + +#ifdef NFS_BOOT_DEFAULTS +#define CONFIG_BOOTARGS "mem=64M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" +#else +#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=64M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" +#endif + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP34XX SDP # " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 24 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ + +/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CFG_TIMERBASE OMAP34XX_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((V_SCLK)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +/*#define SDRC_B_R_C 1 */ +/*#define SDRC_B1_R_B0_C 1 */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 + +#define CFG_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M + +#define CFG_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec +/* Dummy declaration of flash banks to get compilation right */ +#define CFG_FLASH_BANKS_LIST {0, 0} + +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at start of flash */ +#define CFG_ONENAND_BASE ONENAND_MAP + +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_IS_IN_ONENAND 1 +#define CFG_ENV_IS_IN_FLASH 1 +#define ONENAND_ENV_OFFSET 0x1c0000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x1c0000 /* environment starts here */ + +#define CFG_ENV_SECT_SIZE boot_flash_sec +#define CFG_ENV_OFFSET boot_flash_off +#define CFG_ENV_ADDR boot_flash_env_addr + + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#ifndef CONFIG_3430ZEBU +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ +#define CFG_FLASH_QUIET_TEST 1 /* Dont crib abt missing chips */ +#define CFG_FLASH_CFI_WIDTH 0x02 +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) +#define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK CFG_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CFG_JFFS2_NUM_BANKS 1 +#define CONFIG_LED_INFO +#define CONFIG_LED_LEN 16 + +#define ENV_IS_VARIABLE 1 +#endif + +#ifndef __ASSEMBLY__ +extern unsigned int nand_cs_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) +#ifdef CFG_NAND_LEGACY +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) +#endif +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3430zoom2.h b/include/configs/omap3430zoom2.h new file mode 100644 index 000000000..ee452f7b7 --- /dev/null +++ b/include/configs/omap3430zoom2.h @@ -0,0 +1,384 @@ +/* + * (C) Copyright 2008 - 2009 Texas Instruments. + * + * Configuration settings for the 3430 TI Zoom2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_3430ZOOM2 1 /* working on Zoom2 board */ +#define CONFIG_FASTBOOT 1 /* Using fastboot interface */ +#define CONFIG_ZOOM2_LED 1 /* Using Zoom2 LED's */ +#define CONFIG_TWL4030_KEYPAD 1 /* Use the keypad */ +#define CONFIG_TWL4030_USB 1 /* Initialize twl usb */ +#define CONFIG_BOARD_REVISION 1 /* Board revision */ + +//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ + +#include /* get chip and board defs */ + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#define V_SCLK (V_OSCK >> 1) + +//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration: + * Zoom2 has external TL16CP754C + */ +#define CONFIG_SERIAL_MULTI 1 +/* 0 - 1 : first USB with respect to the left edge of the debug board + 2 - 3 : second USB with respect to the left edge of the debug board */ +#define DEFAULT_ZOOM2_SERIAL_DEVICE (&zoom2_serial_device0) + +#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ + +#define CFG_NS16550 +#define CFG_NS16550_REG_SIZE (-2) +#define CFG_NS16550_CLK V_NS16550_CLK +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200} + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_MMC 1 +#define CFG_MMC_BASE 0xF0000000 +#define CONFIG_DOS_PARTITION 1 + +#define NET_CMDS (CFG_CMD_DHCP|CFG_CMD_NFS|CFG_CMD_NET) + +#ifndef CONFIG_OPTIONAL_NOR_POPULATED +//#define C_MSK (CFG_CMD_FLASH | CFG_CMD_IMLS) +#define C_MSK (CFG_CMD_IMLS | CFG_CMD_FLASH) +#endif + +/* Config CMD*/ +#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP |\ + CFG_CMD_FAT | CFG_CMD_MMC |\ + CFG_CMD_NAND) & ~(C_MSK)) + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +/* + * SMC91c96 Etherent + */ +#define CONFIG_DRIVER_SMSC9118 +#define CONFIG_SMSC9118_BASE (DEBUG_BASE) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CFG_I2C_SPEED 400 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +/* + * Board NAND Info. + */ +#define CFG_NAND_ADDR NAND_BASE /* physical address to access nand*/ +#define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/ +#define CFG_NAND_WIDTH_16 + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +/* To use the 256/512 byte s/w ecc define CFG_SW_ECC_(256/512) */ +/* Use the 512 byte ROM CODE HW ecc */ +#define CFG_HW_ECC_ROMCODE 1 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CFG_NAND_WP + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"loadaddr=0x81c00000\0" \ +"nandloadaddr=0x81000000\0" \ +"console=ttyS3,115200n8\0" \ +"mmcroot=/dev/mmcblk0p2\0" \ +"nandroot=/dev/ram0\0" \ +"mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot} rootdelay=2\0" \ +"nandargs=setenv bootargs console=${console} " \ + "rootdelay=2\0" \ +"loaduimage=fatload mmc 0:1 ${loadaddr} uImage\0"\ +"mmcboot=echo Booting from mmc ...;" \ + " run mmcargs;" \ + " bootm ${loadaddr}\0" \ +"nandboot=echo Booting from nand ...;" \ + " nand unlock;" \ + " nand read.i ${nandloadaddr}" \ + " ${kernel_nand_offset}" \ + " ${kernel_nand_size};" \ + " run nandargs;" \ + " bootm ${nandloadaddr}\0" \ +"autoboot=if mmc init 0; then" \ + " run loaduimage;" \ + " run mmcboot;" \ + " else run nandboot;" \ + " fi;\0" \ + +#define CONFIG_BOOTCOMMAND "run autoboot" + +#ifdef NFS_BOOT_DEFAULTS +#define CONFIG_BOOTARGS "mem=64M console=ttyS3,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" +#else +#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=64M console=ttyS3,115200n8 initrd=0x80600000,8M ramdisk_size=8192" +#endif + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP34XX ZOOM2 # " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 24 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ + +/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CFG_TIMERBASE OMAP34XX_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((V_SCLK)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +/*#define SDRC_B_R_C 1 */ +/*#define SDRC_B1_R_B0_C 1 */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +/** REMOVE ME ***/ +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 +#define SERIAL_TL16CP754C_SIZE GPMC_SIZE_16M + +#define CFG_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M + +#define CFG_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec +/* Dummy declaration of flash banks to get compilation right */ +#define CFG_FLASH_BANKS_LIST {0, 0} + +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at start of flash */ + +#if 1 +#define CFG_ENV_IS_IN_NAND 1 +#define ENV_IS_VARIABLE 1 +#else +#define CFG_ENV_IS_NOWHERE 1 +#endif + +#ifdef CONFIG_OPTIONAL_NOR_POPULATED +# define CFG_ENV_IS_IN_FLASH 1 +#endif + +#define SMNAND_ENV_OFFSET 0x1c0000 /* environment starts here */ + +#define CFG_ENV_SECT_SIZE boot_flash_sec +#define CFG_ENV_OFFSET boot_flash_off +#define CFG_ENV_ADDR boot_flash_env_addr + + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#ifndef CONFIG_OPTIONAL_NOR_POPULATED +#define CFG_NO_FLASH 1 /* Disable NOR Flash support */ +#else +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#if (!ENV_IS_VARIABLE) +/* saveenv fails when this variable is defined. + If env is variable, do not use buffered writes */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#endif +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ +#define CFG_FLASH_QUIET_TEST 1 /* Dont crib abt missing chips */ +#define CFG_FLASH_CFI_WIDTH 0x02 +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) +#define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK CFG_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CFG_JFFS2_NUM_BANKS 1 +#define CONFIG_LED_INFOnand_read_buf16 +#define CONFIG_LED_LEN 16 +#endif /* optional NOR flash */ + +#ifndef __ASSEMBLY__ +extern unsigned int nand_cs_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +/* Fastboot variables */ +#define CFG_FASTBOOT_TRANSFER_BUFFER (PHYS_SDRAM_1 + SZ_16M) +#define CFG_FASTBOOT_TRANSFER_BUFFER_SIZE (SZ_256M - SZ_16M) +#define CFG_FASTBOOT_PREBOOT_KEYS 1 +#define CFG_FASTBOOT_PREBOOT_KEY1 0x37 /* 'ok' */ +#define CFG_FASTBOOT_PREBOOT_KEY2 0x00 /* unused */ +#define CFG_FASTBOOT_PREBOOT_INITIAL_WAIT (0) +#define CFG_FASTBOOT_PREBOOT_LOOP_MAXIMUM (1) +#define CFG_FASTBOOT_PREBOOT_LOOP_WAIT (0) + +/* Yaffs variables */ +#define CFG_NAND_YAFFS_WRITE + +/* Zoom2 Battery charging enable */ +#define CFG_BATTERY_CHARGING + +/* Zoom2 Battery threshold */ +#define CFG_LOW_BAT 3300 /* 3.3V */ +#define CFG_BAT_CHG 4000 /* 4.0V */ + +/* Zoom2 charger tries */ +#define CFG_CHARGER_TRIES_MAX 100 + +/* Command shell */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* Clock command */ +#define CONFIG_CMD_CLOCK 1 +#define CONFIG_CMD_CLOCK_INFO_CPU 1 + +/* Voltage command */ +#define CONFIG_CMD_VOLTAGE 1 + +#endif /* __CONFIG_H */ + diff --git a/include/configs/omap3530overo.h b/include/configs/omap3530overo.h new file mode 100644 index 000000000..deebb207e --- /dev/null +++ b/include/configs/omap3530overo.h @@ -0,0 +1,380 @@ +/* + * Configuration settings for the Gumstix Overo board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_3530OVERO 1 /* working on OMAP3530 OVERO */ +#define CONFIG_FASTBOOT 1 /* Using fastboot interface */ +#define CONFIG_TWL4030_USB 1 /* Initialize twl usb */ + +//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ + +#include /* get chip and board defs */ + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#define V_SCLK (V_OSCK >> 1) + +//#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */ +#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration: + */ +//#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ +#define V_NS16550_CLK (48000000) /* 1.8432 Mhz */ + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK V_NS16550_CLK +//#define CFG_NS16550_COM1 OMAP34XX_UART1 +//#define CFG_NS16550_COM2 OMAP34XX_UART2 +#define CFG_NS16550_COM3 OMAP34XX_UART3 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL3 3 /* UART3 on board */ +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 3 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_MMC 1 +#define CFG_MMC_BASE 0xF0000000 +#define CONFIG_DOS_PARTITION 1 + + +#ifndef CONFIG_OPTIONAL_NOR_POPULATED +//#define C_MSK (CFG_CMD_FLASH | CFG_CMD_IMLS) +#define C_MSK (CFG_CMD_IMLS | CFG_CMD_FLASH) +#endif + +/* Config CMD */ +#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL |\ + CFG_CMD_FAT | CFG_CMD_MMC | \ + CFG_CMD_NAND) & ~(C_MSK | CFG_CMD_NET | CFG_CMD_NFS | \ + CFG_CMD_FPGA | CFG_CMD_IMI)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CFG_I2C_SPEED 100 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +/* + * Board NAND Info. + */ +#define CFG_NAND_ADDR NAND_BASE /* physical address to access nand*/ +#define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/ +#define CFG_NAND_WIDTH_16 + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +/* To use the 256/512 byte s/w ecc define CFG_SW_ECC_(256/512) */ +/* Use the 512 byte ROM CODE HW ecc */ +#define CFG_HW_ECC_ROMCODE 1 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CFG_NAND_WP + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "autoscr ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init 0; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP3 OVERO # " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ + +/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CFG_TIMERBASE OMAP34XX_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((V_SCLK)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +/** REMOVE ME ***/ +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 +#define SERIAL_TL16CP754C_SIZE GPMC_SIZE_16M + +#define CFG_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M + +#define CFG_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec +/* Dummy declaration of flash banks to get compilation right */ +#define CFG_FLASH_BANKS_LIST {0, 0} + +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at start of flash */ + +#if 1 +#define CFG_ENV_IS_IN_NAND 1 +#define ENV_IS_VARIABLE 1 +#else +#define CFG_ENV_IS_NOWHERE 1 +#endif + +#ifdef CONFIG_OPTIONAL_NOR_POPULATED +# define CFG_ENV_IS_IN_FLASH 1 +#endif + +#define SMNAND_ENV_OFFSET 0x1c0000 /* environment starts here */ + +#define CFG_ENV_SECT_SIZE boot_flash_sec +#define CFG_ENV_OFFSET boot_flash_off +#define CFG_ENV_ADDR boot_flash_env_addr + + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#ifndef CONFIG_OPTIONAL_NOR_POPULATED +#define CFG_NO_FLASH 1 /* Disable NOR Flash support */ +#else +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#if (!ENV_IS_VARIABLE) +/* saveenv fails when this variable is defined. + If env is variable, do not use buffered writes */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#endif +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ +#define CFG_FLASH_QUIET_TEST 1 /* Dont crib abt missing chips */ +#define CFG_FLASH_CFI_WIDTH 0x02 +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) +#define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK CFG_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CFG_JFFS2_NUM_BANKS 1 +#define CONFIG_LED_INFOnand_read_buf16 +#define CONFIG_LED_LEN 16 +#endif /* optional NOR flash */ + +#ifndef __ASSEMBLY__ +extern unsigned int nand_cs_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +/* Fastboot variables */ +#define CFG_FASTBOOT_TRANSFER_BUFFER (PHYS_SDRAM_1 + SZ_16M) +#define CFG_FASTBOOT_TRANSFER_BUFFER_SIZE (SZ_256M - SZ_16M) +#define CFG_FASTBOOT_PREBOOT_KEYS 1 +#define CFG_FASTBOOT_PREBOOT_KEY1 0x37 /* 'ok' */ +#define CFG_FASTBOOT_PREBOOT_KEY2 0x00 /* unused */ +#define CFG_FASTBOOT_PREBOOT_INITIAL_WAIT (0) +#define CFG_FASTBOOT_PREBOOT_LOOP_MAXIMUM (1) +#define CFG_FASTBOOT_PREBOOT_LOOP_WAIT (0) + +/* Yaffs variables */ +#define CFG_NAND_YAFFS_WRITE + +/* Command shell */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* Clock command */ +#define CONFIG_CMD_CLOCK 1 +#define CONFIG_CMD_CLOCK_INFO_CPU 1 + +/* Voltage command */ +#define CONFIG_CMD_VOLTAGE 1 + +#if defined(CONFIG_CMD_NET) +/*---------------------------------------------------------------------------- + * SMSC9211 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- + */ + +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 + +#endif /* (CONFIG_CMD_NET) */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3630sdp.h b/include/configs/omap3630sdp.h new file mode 100644 index 000000000..a936563a7 --- /dev/null +++ b/include/configs/omap3630sdp.h @@ -0,0 +1,386 @@ +/* + * (C) Copyright 2006 + * Texas Instruments. + * Richard Woodruff + * Syed Mohammed Khasim + * + * Configuration settings for the 3430 TI SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP36XX 1 /* which is a 36XX */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_3630SDP 1 /* working with SDP */ + +#define CONFIG_OMAP3430 1 /* 3630 is similar to 3430 */ +#define CONFIG_FASTBOOT 1 /* Using fastboot interface */ +#define CONFIG_TWL4030_KEYPAD 1 /* Use the keypad */ +#define CONFIG_TWL4030_USB 1 /* Initialize twl usb */ + + +#include /* get chip and board defs */ + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#define V_SCLK V_OSCK + +#define PRCM_CLK_CFG2_400MHZ 1 /* VDD2=1.2v - 200MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ + +/* PER clock options, only uncomment 1 */ +/* Uncomment to run PER M2 at 2x 96MHz */ +/* #define CONFIG_PER_M2_192 */ +/* Uncomment to run PER SGX at 192MHz */ +/*#define CONFIG_PER_SGX_192*/ + +/* Uncommend to run PER at 2x 96MHz */ + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK V_NS16550_CLK +#define CFG_NS16550_COM1 OMAP34XX_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on SDP */ +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +#define NET_CMDS (CFG_CMD_DHCP|CFG_CMD_NFS|CFG_CMD_NET) + +/* Config CMD*/ +#define CONFIG_COMMANDS \ + ((CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP | \ + CFG_CMD_JFFS2 | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_ONENAND | \ + CFG_CMD_NAND) & ~CFG_CMD_AUTOSCRIPT) + + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +/* SMC91c96 Etherent */ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE (DEBUG_BASE) +#define CONFIG_LAN91C96_EXT_PHY +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CFG_I2C_SPEED 400 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +/* + * Board NAND Info. + */ +#define CFG_NAND_ADDR NAND_BASE /* physical address to access nand*/ +#define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/ +#define CFG_NAND_WIDTH_16 + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +/* To use the 256/512 byte s/w ecc define CFG_SW_ECC_(256/512) */ +/* Use the 512 byte ROM CODE HW ecc */ +#define CFG_HW_ECC_ROMCODE 1 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CFG_NAND_WP + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_EXTRA_ENV_SETTINGS \ +"loadaddr=0x81c00000\0" \ +"nandloadaddr=0x81000000\0" \ +"console=ttyS3,115200n8\0" \ +"mmcroot=/dev/mmcblk0p2\0" \ +"nandroot=/dev/ram0\0" \ +"mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot} rootdelay=2\0" \ +"nandargs=setenv bootargs console=${console} " \ + "rootdelay=2\0" \ +"loaduimage=fatload mmc 0:1 ${loadaddr} uImage\0"\ +"mmcboot=echo Booting from mmc ...;" \ + " run mmcargs;" \ + " bootm ${loadaddr}\0" \ +"nandboot=echo Booting from nand ...;" \ + " nand unlock;" \ + " nand read.i ${nandloadaddr}" \ + " ${kernel_nand_offset}" \ + " ${kernel_nand_size};" \ + " run nandargs;" \ + " bootm ${nandloadaddr}\0" \ +"autoboot=if mmc init 0; then" \ + " run loaduimage;" \ + " run mmcboot;" \ + " else run nandboot;" \ + " fi;\0" + +#define CONFIG_BOOTCOMMAND "run autoboot" + +#ifdef NFS_BOOT_DEFAULTS +#define CONFIG_BOOTARGS "mem=64M console=ttyS0,115200n8 noinitrd root=/dev/nfs"\ + " rw nfsroot=128.247.77.158:/home/a0393553/wtbu/rootfs ip=dhcp" +#else + +#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=64M console=ttyS0,115200n8 "\ + "initrd=0x81600000,16M ramdisk_size=16384 rootfstype=ext2 "\ + "video=omap24xxfbout:rotatio=0 " +#endif + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP36XX SDP # " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 24 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ + +/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CFG_TIMERBASE OMAP34XX_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((V_SCLK)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +/*#define SDRC_B_R_C 1 */ +/*#define SDRC_B1_R_B0_C 1 */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +/** REMOVE ME ***/ +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 + +#define CFG_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M + +#define CFG_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec +/* Dummy declaration of flash banks to get compilation right */ +#define CFG_FLASH_BANKS_LIST {0, 0} + +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at start of flash */ +#define CFG_ONENAND_BASE ONENAND_MAP + +#define CFG_ENV_IS_IN_NAND 1 +#define ENV_IS_VARIABLE 1 +#define CFG_ENV_IS_IN_ONENAND 1 +#define CFG_ENV_IS_IN_FLASH 1 +#define ONENAND_ENV_OFFSET 0x1c0000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x1c0000 /* environment starts here */ + +#define CFG_ENV_SECT_SIZE boot_flash_sec +#define CFG_ENV_OFFSET boot_flash_off +#define CFG_ENV_ADDR boot_flash_env_addr + + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ +#define CFG_FLASH_QUIET_TEST 1 /* Dont crib abt missing chips */ +#define CFG_FLASH_CFI_WIDTH 0x02 +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) +#define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK CFG_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CFG_JFFS2_NUM_BANKS 1 +#define CONFIG_LED_INFO +#define CONFIG_LED_LEN 16 + +#ifndef __ASSEMBLY__ +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; + +int get_boot_type(void); +void v7_flush_dcache_all(int, int); +void l2cache_enable(void); +void setup_auxcr(int, int); +int twl4030_init_battery_charging(void); +#endif + +#define WRITE_NAND_COMMAND(d, adr) \ + __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr) \ + __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() \ + do { *(volatile u32 *) (GPMC_CONFIG) |= 0x00000010; } while (0) +#define NAND_WP_ON() \ + do { *(volatile u32 *) (GPMC_CONFIG) &= ~0x00000010; } while (0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +/* Fastboot variables */ +#define CFG_FASTBOOT_TRANSFER_BUFFER (PHYS_SDRAM_1 + SZ_16M) +#define CFG_FASTBOOT_TRANSFER_BUFFER_SIZE (SZ_256M - SZ_16M) +#define CFG_FASTBOOT_PREBOOT_KEYS 1 +#define CFG_FASTBOOT_PREBOOT_KEY1 0x37 /* 'ok' */ +#define CFG_FASTBOOT_PREBOOT_KEY2 0x00 /* unused */ +#define CFG_FASTBOOT_PREBOOT_INITIAL_WAIT (0) +#define CFG_FASTBOOT_PREBOOT_LOOP_MAXIMUM (1) +#define CFG_FASTBOOT_PREBOOT_LOOP_WAIT (0) + +/* Yaffs variables */ +#define CFG_NAND_YAFFS_WRITE + +/* Zoom2 Battery charging enable */ +#define CFG_BATTERY_CHARGING + +/* Zoom2 Battery threshold */ +#define CFG_LOW_BAT 3300 /* 3.3V */ +#define CFG_BAT_CHG 4000 /* 4.0V */ + +/* Zoom2 charger tries */ +#define CFG_CHARGER_TRIES_MAX 100 + +/* Command shell */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* Clock command */ +#define CONFIG_CMD_CLOCK 1 +#define CONFIG_CMD_CLOCK_INFO_CPU 1 + +/* Voltage command */ +#define CONFIG_CMD_VOLTAGE 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3630zoom3.h b/include/configs/omap3630zoom3.h new file mode 100644 index 000000000..18a846c9e --- /dev/null +++ b/include/configs/omap3630zoom3.h @@ -0,0 +1,421 @@ +/* + * (C) Copyright 2008 - 2009 Texas Instruments. + * + * Configuration settings for the 3430 TI Zoom2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP36XX 1 /* which is a 36XX */ +#define CONFIG_OMAP34XX 1 /* reuse the 34XX setup */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_3630ZOOM3 1 /* working on Zoom3 board */ +#define CONFIG_3430ZOOM2 1 /* reuse Zoom2 setup */ +#define CONFIG_FASTBOOT 1 /* Using fastboot interface */ +#define CONFIG_ZOOM2_LED 1 /* Using Zoom2 LED's */ +#define CONFIG_TWL4030_KEYPAD 1 /* Use the keypad */ +#define CONFIG_TWL4030_USB 1 /* Initialize twl usb */ +#define CONFIG_BOARD_REVISION 1 /* Board revision */ +#if !defined(CONFIG_STORAGE_EMMC) +#define CONFIG_STORAGE_NAND 1 /* Flash to NAND using Fastboot */ +#endif + +//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ + +#include /* get chip and board defs */ + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#define V_SCLK (V_OSCK >> 1) + +#define PRCM_CLK_CFG2_400MHZ 1 /* VDD2=1.2v - 200MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ + +/* PER clock options, only uncomment 1 */ +/* Uncomment to run PER M2 at 2x 96MHz */ +/* #define CONFIG_PER_M2_192 */ +/* Uncomment to run PER SGX at 192MHz */ +/*define CONFIG_PER_SGX_192*/ + +/* Uncommend to run PER at 2x 96MHz */ + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration: + * Zoom2 has external TL16CP754C + */ +#define CONFIG_SERIAL_MULTI 1 +/* 0 - 1 : first USB with respect to the left edge of the debug board + 2 - 3 : second USB with respect to the left edge of the debug board */ +#define DEFAULT_ZOOM2_SERIAL_DEVICE (&zoom2_serial_device0) + +#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ + +#define CFG_NS16550 +#define CFG_NS16550_REG_SIZE (-2) +#define CFG_NS16550_CLK V_NS16550_CLK +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200} + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_MMC 1 +#define CFG_MMC_BASE 0xF0000000 +#define CONFIG_DOS_PARTITION 1 + +#define NET_CMDS (CFG_CMD_DHCP|CFG_CMD_NFS|CFG_CMD_NET) + +#ifndef CONFIG_OPTIONAL_NOR_POPULATED +//#define C_MSK (CFG_CMD_FLASH | CFG_CMD_IMLS) +#define C_MSK (CFG_CMD_IMLS | CFG_CMD_FLASH) +#endif + +/* Config CMD*/ +#if defined(CONFIG_STORAGE_NAND) +#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP |\ + CFG_CMD_FAT | CFG_CMD_MMC |\ + CFG_CMD_NAND) & ~(C_MSK)) +#elif defined(CONFIG_STORAGE_EMMC) +#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL | CFG_CMD_DHCP |\ + CFG_CMD_FAT | CFG_CMD_MMC) & ~(C_MSK)) +#endif + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_NET) +/* + * SMC91c96 Etherent + */ +#define CONFIG_DRIVER_SMSC9118 +#define CONFIG_SMSC9118_BASE (DEBUG_BASE) +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CFG_I2C_SPEED 400 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +#if defined(CONFIG_STORAGE_NAND) +/* + * Board NAND Info. + */ +#define CFG_NAND_ADDR NAND_BASE /* physical address to access nand*/ +#define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/ +#define CFG_NAND_WIDTH_16 + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +/* To use the 256/512 byte s/w ecc define CFG_SW_ECC_(256/512) */ +/* Use the 512 byte ROM CODE HW ecc */ +#define CFG_HW_ECC_ROMCODE 1 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_NO_RB 1 +#define CFG_NAND_WP +#endif + +#define NAND_MAX_CHIPS 1 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"loadaddr=0x81c00000\0" \ +"nandloadaddr=0x81000000\0" \ +"console=ttyS3,115200n8\0" \ +"mmcroot=/dev/mmcblk0p2\0" \ +"nandroot=/dev/ram0\0" \ +"mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot} rootdelay=2\0" \ +"nandargs=setenv bootargs console=${console} " \ + "rootdelay=2\0" \ +"loaduimage=fatload mmc 0:1 ${loadaddr} uImage\0"\ +"mmcboot=echo Booting from mmc ...;" \ + " run mmcargs;" \ + " bootm ${loadaddr}\0" \ +"nandboot=echo Booting from nand ...;" \ + " nand unlock;" \ + " nand read.i ${nandloadaddr}" \ + " ${kernel_nand_offset}" \ + " ${kernel_nand_size};" \ + " run nandargs;" \ + " bootm ${nandloadaddr}\0" \ +"autoboot=if mmc init 0; then" \ + " run loaduimage;" \ + " run mmcboot;" \ + " else run nandboot;" \ + " fi;\0" \ + +#define CONFIG_BOOTCOMMAND "run autoboot" + +#ifdef NFS_BOOT_DEFAULTS +#define CONFIG_BOOTARGS "mem=64M console=ttyS3,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" +#else +#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=64M console=ttyS3,115200n8 initrd=0x80600000,8M ramdisk_size=8192" +#endif + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP36XX ZOOM3 # " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 24 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ + +/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CFG_TIMERBASE OMAP34XX_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((V_SCLK)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +/*#define SDRC_B_R_C 1 */ +/*#define SDRC_B1_R_B0_C 1 */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +/** REMOVE ME ***/ +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 +#define SERIAL_TL16CP754C_SIZE GPMC_SIZE_16M + +#define CFG_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M + +#if defined(CONFIG_STORAGE_NAND) +#define CFG_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec +/* Dummy declaration of flash banks to get compilation right */ +#define CFG_FLASH_BANKS_LIST {0, 0} + +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at start of flash */ + +#if 1 +#define CFG_ENV_IS_IN_NAND 1 +#define ENV_IS_VARIABLE 1 +#else +#define CFG_ENV_IS_NOWHERE 1 +#endif + +#ifdef CONFIG_OPTIONAL_NOR_POPULATED +# define CFG_ENV_IS_IN_FLASH 1 +#endif + +#define SMNAND_ENV_OFFSET 0x1c0000 /* environment starts here */ + +#define CFG_ENV_SECT_SIZE boot_flash_sec +#define CFG_ENV_OFFSET boot_flash_off +#define CFG_ENV_ADDR boot_flash_env_addr +#endif + +#if defined(CONFIG_STORAGE_EMMC) +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at start of flash */ + +/* eMMC Variables */ +#define CFG_ENV_IS_IN_EMMC 1 +#define CFG_FLASH_BASE 0x0 +#define CFG_ENV_SECT_SIZE SZ_128K +#define CFG_ENV_OFFSET 0x700 +#define CFG_ENV_ADDR 0x700 + +#define ENV_IS_VARIABLE 1 +#endif +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#ifndef CONFIG_OPTIONAL_NOR_POPULATED +#define CFG_NO_FLASH 1 /* Disable NOR Flash support */ +#else +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#if (!ENV_IS_VARIABLE) +/* saveenv fails when this variable is defined. + If env is variable, do not use buffered writes */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#endif +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ +#define CFG_FLASH_QUIET_TEST 1 /* Dont crib abt missing chips */ +#define CFG_FLASH_CFI_WIDTH 0x02 +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) +#define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK CFG_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CFG_JFFS2_NUM_BANKS 1 +#define CONFIG_LED_INFOnand_read_buf16 +#define CONFIG_LED_LEN 16 +#endif /* optional NOR flash */ + +#ifndef __ASSEMBLY__ +extern unsigned int nand_cs_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#if defined(CONFIG_STORAGE_NAND) +#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) +#endif + +/* Fastboot variables */ +#define CFG_FASTBOOT_MMC_NO 1 /* Use eMMC */ +#define CFG_FASTBOOT_TRANSFER_BUFFER (PHYS_SDRAM_1 + SZ_16M) +#define CFG_FASTBOOT_TRANSFER_BUFFER_SIZE (SZ_512M - SZ_16M) +#define CFG_FASTBOOT_PREBOOT_KEYS 1 +#define CFG_FASTBOOT_PREBOOT_KEY1 0x37 /* 'ok' */ +#define CFG_FASTBOOT_PREBOOT_KEY2 0x00 /* unused */ +#define CFG_FASTBOOT_PREBOOT_INITIAL_WAIT (0) +#define CFG_FASTBOOT_PREBOOT_LOOP_MAXIMUM (1) +#define CFG_FASTBOOT_PREBOOT_LOOP_WAIT (0) + +#if defined(CONFIG_STORAGE_NAND) +/* Yaffs variables */ +#define CFG_NAND_YAFFS_WRITE +#endif + +/* Zoom2 Battery charging enable */ +#define CFG_BATTERY_CHARGING + +/* Zoom2 Battery threshold */ +#define CFG_LOW_BAT 3300 /* 3.3V */ +#define CFG_BAT_CHG 4000 /* 4.0V */ + +/* Zoom2 charger tries */ +#define CFG_CHARGER_TRIES_MAX 100 + +/* Command shell */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* Clock command */ +#define CONFIG_CMD_CLOCK 1 +#define CONFIG_CMD_CLOCK_INFO_CPU 1 + +/* Voltage command */ +#define CONFIG_CMD_VOLTAGE 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3730overo.h b/include/configs/omap3730overo.h new file mode 100644 index 000000000..3a6477b73 --- /dev/null +++ b/include/configs/omap3730overo.h @@ -0,0 +1,362 @@ +/* + * (C) Copyright 2009 - 2010 Texas Instruments SA. + * + * Configuration settings for the 3730 OVERO board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP36XX 1 /* which is a 36XX */ +#define CONFIG_OMAP34XX 1 /* reuse the 34XX setup */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_3730OVERO 1 +#define CONFIG_3530OVERO 1 +//#define CONFIG_FASTBOOT 1 /* Using fastboot interface */ +#define CONFIG_TWL4030_USB 1 /* Initialize twl usb */ + +//#define CONFIG_3430_AS_3410 1 /* true for 3430 in 3410 mode */ + +#include /* get chip and board defs */ + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ + +#define V_SCLK (V_OSCK >> 1) + +#define PRCM_CLK_CFG2_400MHZ 1 /* VDD2=1.15v - 200MHz DDR */ +//#define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */ +#define PRCM_PCLK_OPP2 1 /* ARM=500MHz - VDD1=1.20v */ + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration: + */ +#define V_NS16550_CLK (48000000) /* 48 MHz */ + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK V_NS16550_CLK +//#define CFG_NS16550_COM1 OMAP34XX_UART1 +//#define CFG_NS16550_COM2 OMAP34XX_UART2 +#define CFG_NS16550_COM3 OMAP34XX_UART3 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL3 3 /* UART3 on board */ +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 3 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + + +#define CONFIG_MMC 1 +#define CFG_MMC_BASE 0xF0000000 +#define CONFIG_DOS_PARTITION 1 + + +#ifndef CONFIG_OPTIONAL_NOR_POPULATED +//#define C_MSK (CFG_CMD_FLASH | CFG_CMD_IMLS) +#define C_MSK (CFG_CMD_IMLS | CFG_CMD_FLASH) +#endif + +/* Config CMD */ +#define CONFIG_COMMANDS ((CFG_CMD_I2C | CONFIG_CMD_DFL |\ + CFG_CMD_FAT | CFG_CMD_MMC ) \ + & ~(C_MSK | CFG_CMD_NET | CFG_CMD_NFS | \ + CFG_CMD_FPGA | CFG_CMD_IMI | CFG_CMD_NAND)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CFG_I2C_SPEED 400 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#endif + +#ifdef CFG_NAND +/* + * Board NAND Info. + */ +#define CFG_NAND_ADDR NAND_BASE /* physical address to access nand*/ +#define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0*/ +#define CFG_NAND_WIDTH_16 + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +/* To use the 256/512 byte s/w ecc define CFG_SW_ECC_(256/512) */ +/* Use the 512 byte ROM CODE HW ecc */ +#define CFG_HW_ECC_ROMCODE 1 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_NO_RB 1 +#define CFG_NAND_WP +#endif // #ifdef CFG_NAND + +#define NAND_MAX_CHIPS 1 // needed by nand.h even though CFG_CMD_NAND is undefined! hm... + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ +"loadaddr=0x81c00000\0" \ +"nandloadaddr=0x81000000\0" \ +"console=ttyS2,115200n8\0" \ +"mmcroot=/dev/mmcblk0p2\0" \ +"nandroot=/dev/ram0\0" \ +"mmcargs=setenv bootargs console=${console} " \ + "root=${mmcroot} rootdelay=2\0" \ +"nandargs=setenv bootargs console=${console} " \ + "rootdelay=2\0" \ +"loaduimage=fatload mmc 0:1 ${loadaddr} uImage\0"\ +"mmcboot=echo Booting from mmc ...;" \ + " run mmcargs;" \ + " bootm ${loadaddr}\0" \ +"nandboot=echo Booting from nand ...;" \ + " nand unlock;" \ + " nand read.i ${nandloadaddr}" \ + " ${kernel_nand_offset}" \ + " ${kernel_nand_size};" \ + " run nandargs;" \ + " bootm ${nandloadaddr}\0" \ +"autoboot=if mmc init 0; then" \ + " run loaduimage;" \ + " run mmcboot;" \ + " else run nandboot;" \ + " fi;\0" \ + +#define CONFIG_BOOTCOMMAND "run autoboot" + +#define CONFIG_AUTO_COMPLETE 1 + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP3730 OVERO # " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 24 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ + +/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CFG_TIMERBASE OMAP34XX_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((V_SCLK)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +/*#define SDRC_B_R_C 1 */ +/*#define SDRC_B1_R_B0_C 1 */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +/** REMOVE ME ***/ +#define PISMO1_NOR_SIZE_SDPV2 GPMC_SIZE_128M +#define PISMO1_NOR_SIZE GPMC_SIZE_64M + +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M +#define DBG_MPDB_SIZE GPMC_SIZE_16M +#define PISMO2_SIZE 0 +#define SERIAL_TL16CP754C_SIZE GPMC_SIZE_16M + +#define CFG_MAX_FLASH_SECT (520) /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CFG_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define PHYS_FLASH_SIZE_SDPV2 SZ_128M +#define PHYS_FLASH_SIZE SZ_32M + +#define CFG_FLASH_BASE boot_flash_base +#define PHYS_FLASH_SECT_SIZE boot_flash_sec +/* Dummy declaration of flash banks to get compilation right */ +#define CFG_FLASH_BANKS_LIST {0, 0} + +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at start of flash */ + +#if 0 +#define CFG_ENV_IS_IN_NAND 1 +#define ENV_IS_VARIABLE 1 +#else +#define CFG_ENV_IS_NOWHERE 1 +#endif + +#ifdef CONFIG_OPTIONAL_NOR_POPULATED +# define CFG_ENV_IS_IN_FLASH 1 +#endif + +#define SMNAND_ENV_OFFSET 0x1c0000 /* environment starts here */ + +#define CFG_ENV_SECT_SIZE boot_flash_sec +#define CFG_ENV_OFFSET boot_flash_off +#define CFG_ENV_ADDR boot_flash_env_addr + + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#ifndef CONFIG_OPTIONAL_NOR_POPULATED +#define CFG_NO_FLASH 1 /* Disable NOR Flash support */ +#else +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#if (!ENV_IS_VARIABLE) +/* saveenv fails when this variable is defined. + If env is variable, do not use buffered writes */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#endif +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ +#define CFG_FLASH_QUIET_TEST 1 /* Dont crib abt missing chips */ +#define CFG_FLASH_CFI_WIDTH 0x02 +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) +#define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK CFG_MAX_FLASH_BANKS /* use flash_info[2] */ +#define CFG_JFFS2_NUM_BANKS 1 +#define CONFIG_LED_INFOnand_read_buf16 +#define CONFIG_LED_LEN 16 +#endif /* optional NOR flash */ + +#ifndef __ASSEMBLY__ +extern unsigned int nand_cs_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#define WRITE_NAND_COMMAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD)) +#define WRITE_NAND_ADDRESS(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR)) +#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT)) +#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT)) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +/* Fastboot variables */ +#define CFG_FASTBOOT_TRANSFER_BUFFER (PHYS_SDRAM_1 + SZ_16M) +#define CFG_FASTBOOT_TRANSFER_BUFFER_SIZE (SZ_256M - SZ_16M) +#define CFG_FASTBOOT_PREBOOT_KEYS 1 +#define CFG_FASTBOOT_PREBOOT_KEY1 0x37 /* 'ok' */ +#define CFG_FASTBOOT_PREBOOT_KEY2 0x00 /* unused */ +#define CFG_FASTBOOT_PREBOOT_INITIAL_WAIT (0) +#define CFG_FASTBOOT_PREBOOT_LOOP_MAXIMUM (1) +#define CFG_FASTBOOT_PREBOOT_LOOP_WAIT (0) + +/* Yaffs variables */ +#define CFG_NAND_YAFFS_WRITE + +/* Command shell */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +/* Clock command */ +#define CONFIG_CMD_CLOCK 1 +#define CONFIG_CMD_CLOCK_INFO_CPU 1 + +/* Voltage command */ +#define CONFIG_CMD_VOLTAGE 1 + +#endif /* __CONFIG_H */ + diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h new file mode 100644 index 000000000..3a3b38961 --- /dev/null +++ b/include/configs/omap3_overo.h @@ -0,0 +1,320 @@ +/* + * Configuration settings for the Gumstix Overo board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_OVERO 1 /* working with overo */ + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include /* get chip and board defs */ +#include + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + +/* commands to include */ +#include + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ +#undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER 1 +#define CONFIG_TWL4030_LED 1 + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand */ + /* at CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "Overo # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#ifndef __ASSEMBLY__ +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#if defined(CONFIG_CMD_NET) +/*---------------------------------------------------------------------------- + * SMSC9211 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- + */ + +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 + +#endif /* (CONFIG_CMD_NET) */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h index e3bde4ff8..5db4f52be 100644 --- a/include/configs/omap5912osk.h +++ b/include/configs/omap5912osk.h @@ -86,24 +86,11 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #include #define CONFIG_BOOTDELAY 3 @@ -115,7 +102,7 @@ #define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ #define CONFIG_BOOTFILE "uImage" /* file to load */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ #endif @@ -174,7 +161,7 @@ * FLASH driver setup */ #define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ #define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h index c4d253af4..fda55cf06 100644 --- a/include/configs/omap730p2.h +++ b/include/configs/omap730p2.h @@ -90,24 +90,14 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT /* - * Command line configuration. + * This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - +#include #include #include @@ -122,7 +112,7 @@ #define CONFIG_SERVERIP 192.150.0.100 #define CONFIG_BOOTFILE "uImage" /* File to load */ -#if defined(CONFIG_CMD_KGDB) +#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */ #endif diff --git a/include/configs/omaptest2430.h b/include/configs/omaptest2430.h new file mode 100644 index 000000000..6b19e04f1 --- /dev/null +++ b/include/configs/omaptest2430.h @@ -0,0 +1,304 @@ +/* + * (C) Copyright 2004 + * Texas Instruments. + * Richard Woodruff + * Kshitij Gupta + * + * Configuration settings for the 242x TI H4 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP24XX 1 /* which is a 24XX Processor */ +#define CONFIG_OMAP242X 1 /* which is in a 242X */ +#define CONFIG_OMAP24XXH4 1 /* and on a H4 board */ +#define CONFIG_TEST2430 1 /* to test 2430SDP connectivity */ + +/* input clock of PLL */ +/* the OMAP24XX H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ +//#define INPUT_CLK_12MHZ 1 +#define INPUT_CLK_13MHZ 1 /* default is 12MHz */ + +#define PRCM_CONFIG_II 1 +//#define PRCM_CONFIG_III 1 + +#include /* get chip and board defs */ + +/* On H4, NOR and NAND flash are mutual exclusive. + Define this if you want to use NAND + */ +/*#define CFG_NAND_BOOT */ + +#ifdef INPUT_CLK_13MHZ +#define V_SCLK 13000000 +#else +#define V_SCLK 12000000 +#endif + +#define CONFIG_SYS_CLK_FREQ V_SCLK + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * SMC91c96 Etherent + */ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE (DEBUG_BASE+0x300) +#define CONFIG_LAN91C96_EXT_PHY + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ + +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ +#define CFG_NS16550_COM1 OMAP24XX_UART1 + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* UART1 on H4 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +#ifdef CFG_NAND_BOOT +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) +#endif +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + /* + * I2C configuration + */ +#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#define CONFIG_HARD_I2C +#define CFG_I2C_SPEED 100 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP24XX_I2C 1 +#endif + +/* + * Board NAND Info. + */ +#define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ + +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 + +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define NAND_WAIT_READY(nand) udelay(10) + +#define NAND_NO_RB 1 + +#define CFG_NAND_WP + +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) + + +#define CONFIG_BOOTDELAY 3 + +#ifdef NFS_BOOT_DEFAULTS +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp" +#else +#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192" +#endif + +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAPtest2430 # " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START (OMAP24XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP24XX_SDRC_CS0+SZ_31M) + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR (OMAP24XX_SDRC_CS0) /* default load address */ + +/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 /* use with 12MHz/128 */ +#define CFG_TIMERBASE OMAP24XX_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP24XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP24XX_SDRC_CS1 + +#define PHYS_FLASH_SECT_SIZE SZ_128K +#define PHYS_FLASH_1 FLASH_BASE /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE_1 SZ_32M +#define PHYS_FLASH_2 (FLASH_BASE+SZ_32M) /* same cs, 2 chips in series */ +#define PHYS_FLASH_SIZE_2 SZ_32M + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ +#define CFG_MONITOR_LEN SZ_128K /* Reserve 1 sector */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 } + +#ifdef CFG_NAND_BOOT +#define CFG_ENV_IS_IN_NAND 1 +#define CFG_ENV_OFFSET 0x80000 /* environment starts here */ +#else +#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K) +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ +#endif + + + + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ + +/* Flash banks JFFS2 should use */ +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE) +#define CFG_JFFS2_MEM_NAND +#define CFG_JFFS2_FIRST_BANK 1 /* use flash_info[1] */ +#define CFG_JFFS2_NUM_BANKS 1 + +/* GPMC Settings */ +#ifdef CFG_NAND_BOOT +/* NAND */ +#define OMAP24XX_GPMC_CS0 SMNAND +#else +/* NOR */ +#define OMAP24XX_GPMC_CS0 STNOR +#endif + +#define OMAP24XX_GPMC_CS0_SIZE GPMC_SIZE_64M +#define OMAP24XX_GPMC_CS0_MAP CFG_FLASH_BASE + +#define OMAP24XX_GPMC_CS1 MPDB +#define OMAP24XX_GPMC_CS1_SIZE GPMC_SIZE_16M +#define OMAP24XX_GPMC_CS1_MAP DEBUG_BASE + +/* Other NAND Access APIs */ +#ifdef CFG_NAND_BOOT +#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)(GPMC_NAND_CMD_0)= (d);} while(0) +#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)(GPMC_NAND_ADR_0) = (d);} while(0) +#define WRITE_NAND(d, adr) do {*(volatile u16 *)(GPMC_NAND_DAT_0)= (d);} while(0) +#define READ_NAND(adr) (*(volatile u16 *)(GPMC_NAND_DAT_0)) +#define NAND_WP_OFF() do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010;} while(0) +#define NAND_WP_ON() do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010;} while(0) +#define NAND_CTL_CLRALE(nandptr) +#define NAND_CTL_SETALE(nandptr) +#define NAND_CTL_CLRCLE(nandptr) +#define NAND_CTL_SETCLE(nandptr) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) +#endif /* NAND Commands */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/omapv1030gsample.h b/include/configs/omapv1030gsample.h new file mode 100644 index 000000000..c23716165 --- /dev/null +++ b/include/configs/omapv1030gsample.h @@ -0,0 +1,181 @@ +/* + * (C) Copyright 2005 + * Texas Instruments. + * Jian Zhang + * Configuation settings for the TI OMAPV1030 G-Sample board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_INIT_CRITICAL /* undef for developing */ + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAPV1030 1 /* which is in an OMAPV1030 */ +#define CONFIG_GSAMPLE_OMAPV1030 1 /* a G-Sample Board */ + +/* input clock of PLL */ +/* G-Sample has 13MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 13000000 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ +/* +*/ +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE 0x08400300 +#define CONFIG_LAN91C96_EXT_PHY + +/* + * NS16550 Configuration + */ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ +#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ +#define CFG_NS16550_COM2 0xfffb0800 /* uart2, bluetooth uart on helen */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 2 /* we use SERIAL 2 on OMAPV1030 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 2 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +//#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include +#include + + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ + root=/dev/nfs rw nfsroot=157.87.82.48:\ + /home/a0875451/mwd/myfs/target ip=dhcp" +#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ +#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ +#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ +#define CONFIG_BOOTFILE "uImage" /* file to load */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "G-SAMPLE # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x10000000 /* default load address */ + +/* The OMAPV1030 has 3 MPU timers, they can be driven by the RefClk (13Mhz) or by + * DPLL1. This time is further subdivided by a local divisor. + */ +#define CFG_TIMERBASE 0xFFFEC500 /* use MPU timer 1 */ +#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ +#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define PHYS_FLASH_1 0x0c000000 /* Flash Bank #1 */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ +#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ + +/* addr of environment */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ + +#define CFG_MAX_MTD_BANKS (CFG_MAX_FLASH_BANKS) + +#endif /* __CONFIG_H */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 82f239117..aa0901f3f 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -35,7 +35,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_P3P440 1 /* Board is P3P440 */ #define CONFIG_440GP 1 /* Specifc GP support */ -#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -118,7 +117,7 @@ * Default configuration (environment varibles...) *----------------------------------------------------------------------*/ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -147,7 +146,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ + "upd=run load;run update\0" \ "unlock=yes\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" @@ -168,37 +167,25 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_EEPROM | \ + CFG_CMD_SNTP ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_SNTP - +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -207,7 +194,7 @@ *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -239,6 +226,7 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ @@ -297,7 +285,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ @@ -311,6 +299,14 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif /* * Internal Definitions @@ -320,7 +316,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 2caa64173..ed1893f57 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -30,16 +30,16 @@ #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ #define CONFIG_PB1X00 1 -#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ +#define CONFIG_AU1X00 1 /* alchemy series cpu */ #ifdef CONFIG_PB1000 -#define CONFIG_SOC_AU1000 1 +#define CONFIG_AU1000 1 #else #ifdef CONFIG_PB1100 -#define CONFIG_SOC_AU1100 1 +#define CONFIG_AU1100 1 #else #ifdef CONFIG_PB1500 -#define CONFIG_SOC_AU1500 1 +#define CONFIG_AU1500 1 #else #error "No valid board set" #endif @@ -81,9 +81,7 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_MIPS_TIMER_FREQ 396000000 - -#define CFG_HZ 1000 +#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */ #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ @@ -134,8 +132,11 @@ /*---USB -------------------------------------------*/ #if 0 #define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION +#else +#define ADD_USB_CMD 0 #endif /*---ATA PCMCIA ------------------------------------*/ @@ -178,36 +179,11 @@ #define CFG_ICACHE_SIZE 16384 #define CFG_CACHELINE_SIZE 32 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - -#undef CONFIG_CMD_ENV -#undef CONFIG_CMD_FAT -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IDE -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_RUN -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_ELF -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_BEDBUG +#define CONFIG_COMMANDS \ + (((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \ + ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \ + CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \ + CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD) +#include #endif /* __CONFIG_H */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index ba6d93224..50c1c4fd4 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -27,18 +27,11 @@ #ifndef __CONFIG_H #define __CONFIG_H - -/* new uImage format support */ -#define CONFIG_FIT 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ - /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ #define CONFIG_PCS440EP 1 /* Board is PCS440EP */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ -#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ @@ -70,9 +63,8 @@ /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CFG_INIT_RAM_END (4 << 10) +#define CFG_INIT_RAM_END (8 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -110,28 +102,21 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -#define CONFIG_ENV_OVERWRITE 1 +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif /* CFG_ENV_IS_IN_FLASH */ -#define ENV_NAME_REVLEV "revision_level" -#define ENV_NAME_SOLDER "solder_switch" -#define ENV_NAME_DIP "dip" - /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #undef CONFIG_DDR_ECC /* don't use ECC */ #define SPD_EEPROM_ADDRESS {0x50} -#define CONFIG_PROG_SDRAM_TLB 1 /*----------------------------------------------------------------------- * I2C @@ -148,7 +133,7 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -156,8 +141,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=pcs440ep\0" \ - "use_eeprom_ethaddr=default\0" \ - "cs_test=off\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -178,7 +161,7 @@ "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ "cp.b 100000 FFFA0000 60000\0" \ - "upd=run load update\0" \ + "upd=run load;run update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -188,32 +171,6 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -/* check U-Boot image with SHA1 sum */ -#define CONFIG_SHA1_CHECK_UB_IMG 1 -#define CONFIG_SHA1_START CFG_MONITOR_BASE -#define CONFIG_SHA1_LEN CFG_MONITOR_LEN - -/*----------------------------------------------------------------------- - * Definitions for status LED - */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED 1 - -#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */ -#define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ -#define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */ -#define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ -#define STATUS_LED_STATE1 STATUS_LED_ON -#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */ -#define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ -#define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */ -#define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ -#define STATUS_LED_STATE3 STATUS_LED_OFF - -#define CONFIG_SHOW_BOOT_PROGRESS 1 - #define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -249,48 +206,37 @@ #define CONFIG_HW_WATCHDOG /* watchdog */ #endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ + CFG_CMD_USB ) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_REISER -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_USB #define CONFIG_SUPPORT_VFAT +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -319,6 +265,7 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT @@ -367,79 +314,88 @@ /*----------------------------------------------------------------------- * PPC440 GPIO Configuration */ -#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \ -{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6 EBC_CS_N(1) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7 EBC_CS_N(2) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8 EBC_CS_N(3) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9 EBC_CS_N(4) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO10 EBC_CS_N(5) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO11 EBC_BUS_ERR */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO12 ZII_p0Rxd(0) */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO13 ZII_p0Rxd(1) */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO14 ZII_p0Rxd(2) */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO15 ZII_p0Rxd(3) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16 ZII_p0Txd(0) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17 ZII_p0Txd(1) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18 ZII_p0Txd(2) */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19 ZII_p0Txd(3) */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO20 ZII_p0Rx_er */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO21 ZII_p0Rx_dv */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO22 ZII_p0RxCrs */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23 ZII_p0Tx_er */ \ +{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24 ZII_p0Tx_en */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO25 ZII_p0Col */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO26 USB2D_RXVALID */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO28 USB2D_TXVALID */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ +{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ +{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ }, \ { \ /* GPIO Core 1 */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ -{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO32 USB2D_OPMODE0 */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO33 USB2D_OPMODE1 */ \ +{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{ GPIO1_BASE, GPIO_IN, GPIO_ALT3 }, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ +{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37 UART0_RTS_N */ \ +{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_ALT2 }, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO40 UIC_IRQ(0) */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO41 UIC_IRQ(1) */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO42 UIC_IRQ(2) */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO43 UIC_IRQ(3) */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ +{ GPIO1_BASE, GPIO_BI, GPIO_SEL }, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO49 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO50 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO51 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO52 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO53 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO54 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO55 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO56 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO57 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO58 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO59 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO60 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO61 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO62 Unselect via TraceSelect Bit */ \ +{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO63 Unselect via TraceSelect Bit */ \ } \ } +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Internal Definitions * @@ -448,38 +404,9 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ - -#define CONFIG_IDE_PREINIT 1 -#define CONFIG_IDE_RESET 1 - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR CFG_CF1 - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET 0 - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x0000) - #endif /* __CONFIG_H */ diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index 7e393f761..73aa3a882 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -89,34 +89,28 @@ * ---------------------------------------------------------------- */ #define CFG_SPI_INIT_OFFSET 0xB00 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ + CFG_CMD_BSP | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP ) -/* - * Command line configuration. - */ -#include -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP +#define CONFIG_BOOTP_MASK \ + ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - +/*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -228,7 +222,7 @@ #if 0 /* Start port with environment in flash; switch to SPI EEPROM later */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */ #define CFG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */ #define CFG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */ @@ -313,7 +307,7 @@ /* 0x01800000 */ #define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000 | SCCR_DFLCD100 | \ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index aca70dce6..ba6b113d8 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006-2007 + * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * Configuation settings for the PDNB3 board. @@ -71,33 +71,19 @@ #define CONFIG_BAUDRATE 115200 #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_DATE | \ + CFG_CMD_NET | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_I2C | \ + CFG_CMD_ELF | \ + CFG_CMD_PING) -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ELF -#define CONFIG_CMD_PING - -#if !defined(CONFIG_SCPU) -#define CONFIG_CMD_NAND -#endif - +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +/* These are u-boot generic parameters */ +#include #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -140,7 +126,7 @@ * Default configuration (environment varibles...) *----------------------------------------------------------------------*/ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -170,10 +156,10 @@ "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \ "cp.b 100000 50000000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ + "upd=run load;run update\0" \ "ipaddr=10.0.0.233\0" \ "serverip=10.0.0.152\0" \ - "netmask=255.255.0.0\0" \ + "netmask=255.255.0.0\0" \ "ethaddr=c6:6f:13:36:f3:81\0" \ "eth1addr=c6:6f:13:36:f3:82\0" \ "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \ @@ -190,20 +176,12 @@ #define CFG_FLASH_BASE 0x50000000 #define CFG_MONITOR_BASE CFG_FLASH_BASE -#if defined(CONFIG_SCPU) -#define CFG_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */ -#else #define CFG_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */ -#endif /* * Expansion bus settings */ -#if defined(CONFIG_SCPU) -#define CFG_EXP_CS0 0x94d23C42 /* 8bit, max size */ -#else #define CFG_EXP_CS0 0x94913C43 /* 8bit, max size */ -#endif #define CFG_EXP_CS1 0x85000043 /* 8bit, 512bytes */ /* @@ -211,17 +189,11 @@ */ #define CFG_SDR_CONFIG 0x18 #define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDRAM_REFRESH_CNT 0x81a /* * FLASH and environment organization */ -#if defined(CONFIG_SCPU) -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ -#endif - #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -245,28 +217,20 @@ #define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) -#if defined(CONFIG_SCPU) -/* no redundant environment on SCPU */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#else -#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif -#if !defined(CONFIG_SCPU) /* * NAND-FLASH stuff */ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 #define CFG_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ -#endif /* * GPIO settings @@ -320,15 +284,9 @@ /* * I2C RTC */ -#if 0 /* test-only */ -#define CONFIG_RTC_DS1340 1 -#define CFG_I2C_RTC_ADDR 0x68 -#else -/* M41T11 Serial Access Timekeeper(R) SRAM */ #define CONFIG_RTC_M41T11 1 #define CFG_I2C_RTC_ADDR 0x68 #define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ -#endif /* * Spartan3 FPGA configuration support diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index c065d3328..fefdb3cca 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -49,7 +49,11 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Serial console configuration */ @@ -70,7 +74,6 @@ #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 #define CONFIG_PCI_SCAN_SHOW 1 -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 #define CONFIG_PCI_MEM_BUS 0x40000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -87,6 +90,13 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 #endif + +#define ADD_PCI_CMD CFG_CMD_PCI + +#else /* MPC5100 */ + +#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ + #endif /* Partitions */ @@ -96,35 +106,26 @@ /* USB */ #if 0 #define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 #endif - /* - * BOOTP options + * Supported commands */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE - -#ifdef CONFIG_MPC5200 -#define CONFIG_CMD_PCI -#endif +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF | \ + ADD_PCI_CMD ) +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 @@ -170,7 +171,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #endif /* * I2C configuration @@ -262,7 +263,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -280,11 +281,6 @@ #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Various low-level settings */ diff --git a/include/configs/plat-tomtom.conf b/include/configs/plat-tomtom.conf new file mode 100644 index 000000000..f93f0a0a5 --- /dev/null +++ b/include/configs/plat-tomtom.conf @@ -0,0 +1,185 @@ +/* + * U-Boot configuration for TomTom platforms + * + * Copyright (C) 2010 TomTom International B.V. + * + ************************************************************************ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + ************************************************************************ + */ + +#include +#include + +/** + * Bootscripts are at /board/tomtom/common/